[
  {
    "path": ".gitignore",
    "content": "venv/\n.clang-format\n.DS_Store\n.tags\n.ipynb_checkpoints\n.idea\n.overlay_init\n.overlay_consistent\n.sconsign.dblite\n.vscode*\nmodel2.png\na.out\n.hypothesis\n\n*.dylib\n*.DSYM\n*.d\n*.pyc\n*.pyo\n.*.swp\n.*.swo\n.*.un~\n*.tmp\n*.o\n*.o-*\n*.os\n*.os-*\n*.so\n*.a\n*.clb\n*.class\n*.pyxbldc\n*.vcd\nconfig.json\nclcache\ncompile_commands.json\n\npersist\nboard/obj/\nselfdrive/boardd/boardd\nselfdrive/logcatd/logcatd\nselfdrive/mapd/default_speeds_by_region.json\nselfdrive/proclogd/proclogd\n\n\nselfdrive/test/longitudinal_maneuvers/out\nselfdrive/visiond/visiond\nselfdrive/loggerd/loggerd\nselfdrive/loggerd/bootlog\nselfdrive/sensord/_gpsd\nselfdrive/sensord/_sensord\nselfdrive/camerad/camerad\nselfdrive/camerad/test/ae_gray_test\nselfdrive/modeld/_modeld\nselfdrive/modeld/_dmonitoringmodeld\n/src/\n\none\nopenpilot\nnotebooks\nxx\nhyperthneed\npanda_jungle\nprovisioning\n\n.coverage*\ncoverage.xml\nhtmlcov\npandaextra\n\n.mypy_cache/\nflycheck_*\n\ncppcheck_report.txt\ncomma*.sh\n\nselfdrive/modeld/thneed/compile\nmodels/*.thneed\n\n*.bz2\n!phonelibs/mapbox-gl-native-qt/aarch64/*.so\n!phonelibs/mapbox-gl-native-qt/jarch64/*.so"
  },
  {
    "path": "CHANGELOGS-DEV.md",
    "content": "dragonpilot 0.8.9-3\n========================\n* Bug fixes.\n* Fixed up auto updater.\n* Fixed Honda Jade dbc. (Thanks to @lijunhao731)\n* ADDED: 0.8.10 model.\n* ADDED: Nav for all device.\n* ADDED: Support for Nvidia Xavier.\n\ndragonpilot 0.8.9-2\n========================\n* Bug fixes.\n* Refactor UI related changes.\n* Updated Simplified Chinese translation. (Thanks to @CCZ)\n* WARNING: Due to recent OP change, Device w/ battery recommended setting autoshutdown to 1 min to prevent libusb error.\n* Re-tuned acceleraton profile. (Thank to @wer5lcy)\n* ADDED: Car port for Toyota Prius Alpha. (Thanks to @CT921)\n\ndragonpilot 0.8.9-1\n========================\n* Based on openpilot 0.8.8 devel.\n* Re-introduce Follow Distance 4th profile (2.2s / 1.8s / 1.5s / 1.2s).\n* ADDED: New softer sound for c3.\n* ADDED: Dynamic Lane Profile. (Thanks to @sunnyhaibin)\n* Bug Fixes.\n\ndragonpilot 0.8.8-2\n========================\n* ADDED: newer faster and modularized mapd and slow down for curve. (Thanks to @move-fast)\n* ADDED: Street name on the bottom bar.\n* ADDED: Now supports 1+3t / C2 / C3 / Jetson Xavier NX.\n* ADDED: Smoother tune for PRIUS_TSS2.\n* Bug fixes.\n\ndragonpilot 0.8.8-1\n========================\n** BETA TESTING ONLY **\n* Based on openpilot 0.8.8 devel.\n* FIXED: dashcam issue.\n* FIXED: some VW vehicles issue. (Thanks to @yayism)\n* FIXED: white panda + j533 acc issue. (Thanks to @lirudy)\n* ADDED: Auto fake black panda.\n* ADDED: 2018 chinese camry hybrid fingerprint (Thanks to @stingshen)\n* WIP: mapd.\n\ndragonpilot 0.8.7-4\n========================\n* 2017 JADE w/ Added Comma Pedal Support. (Thanks to @lijunhao731)\n* Fixed toyota / honda brake light display. (Thanks to @loveloveses)\n* Fixed UI toggle. (Thanks to @鄧育林、@謝聖鴻)\n* Fixed VW resume/display issue. (Thanks to @SKY)\n* Fixed CJK font installation issue.\n\ndragonpilot 0.8.7-3\n========================\n* Bug fixes.\n* Fixed gpxd.\n* Added some Chinese support.\n\ndragonpilot 0.8.7-2\n========================\n* Fixed sound issue.\n* Changed gpx logs to OSM compatible format.\n* HONDA: Added BSM support for CRV-Hybrid.\n* HONDA: Added toggle to force displaying km/h in HUD.\n* TOYOTA: Add new Toggles under DP - Cars to enable/disable Following Modes / Accel Modes with physical button feature.\n\ndragonpilot 0.8.7-1\n========================\n* Based on openpilot 0.8.7 devel.\n* Support 1+3t / C2 / Jetson Xavier NX.\n* Support White / Grey Panda.\n* TOYOTA: Can now change Following Modes with physical button from the steering wheel.\n* TOYOTA: Can now change Acceleration Modes with physical button if your car supports it.\n* TOYOTA: Added Low speed override toggles.\n* Dev UI now displays RPM reading.\n* Added Prebuilt toggle for faster boot.\n* Lexus RX high RPM fix. (Thanks to @crazysim).\n* Added toggle to launch Language settings.\n* Added toggle to launch Volume settings.\n* Added toggle to launch date/time settings.\n* Added toggle to flash panda.\n* Added toggle to recover panda firmware.\n* Added toggle to delete logging (/sdcard/realdata).\n* Added GPS Logger.\n\ndragonpilot 0.8.6-1\n========================\n* Based on openpilot 0.8.6 devel.\n* Support 1+3t / C2 / Jetson Xavier NX.\n* Support White / Grey Panda.\n\ndragonpilot 0.8.5-4\n========================\n* Added multiple toggles.\n* Code clean up.\n* Android app support. (see selfdrive/dragonpilot/HOWTO-APPD.md)\n* Better support for VW MPQ (Thanks to @Saber)\n\ndragonpilot 0.8.5-3\n========================\n* Added Jetson support toggle.\n* Added Steering Ratio controller.\n* Reduce Following Profile to 3 modes only. (1.8s / 1.5s / 1.2s)\n* Bug fixes.\n\ndragonpilot 0.8.5-2\n========================\n* Added black panda simulation toggle.\n* Added No GPS toggle.\n* Added No Battery Toggle.\n* Bug fixes.\n\ndragonpilot 0.8.5-1\n========================\n* Based on openpilot 0.8.5 devel.\n* 基於 openpilot 0.8.5 devel.\n* Support 1+3t / C2 / Jetson Xavier NX.\n* 支持 1+3t / C2 / Jetson Xavier NX.\n* No White/Grey Panda Support.\n* 不支持白灰熊.\n\ndragonpilot 0.8.4-3\n========================\n* 簡化 1+3t 安裝方法. (請查閱 HOWTO-ONEPLUS.md)\n* Simplied 1+3t installation. (See HOWTO-ONEPLUS.md)\n* 加回舊 ssh 登錄.\n* Good old ssh key.\n* 修復本田錯誤. (感謝 @loveloveses)\n* Fixed Honda bug. (Thanks to @loveloveses)\n\ndragonpilot 0.8.4-2\n========================\n* 加回可調整加速/跟車設定.\n* Added back Accel/Following Profile.\n* 支持 Headless Jetson Xavier NX (https://github.com/efinilan/xnxpilot.git)\n* Support Headless Jetson Xavier NX (https://github.com/efinilan/xnxpilot.git)\n* 支持 1+3t (需額外安裝手續)\n* Support 1+3t (Require additional install procedure)\n* 支持白/灰熊\n* Support White/Grey Panda.\n\ndragonpilot 0.8.4-1\n========================\n* 基於 openpilot 0.8.4 devel.\n* Based on openpilot 0.8.4 devel.\n\ndragonpilot 0.8.1\n========================\n* 基於最新 openpilot 0.8.1 devel.\n* Based on latest openpilot 0.8.1 devel.\n* 加入行車記錄按鈕。(感謝 @toyboxZ 提供)\n* Added REC screen button. (Thanks to @toyboxZ)\n\ndragonpilot 0.8.0\n========================\n* 基於最新 openpilot 0.8.0 devel.\n* Based on latest openpilot 0.8.0 devel.\n* 加入 git 錯誤修正。(感謝 @toyboxZ 提供)\n* Added git error fix. (Thanks to @toyboxZ)\n\ndragonpilot 0.7.10.1\n========================\n* HYUNDAI_GENESIS 使用 INDI 控制器。(感謝 @donfyffe 提供)\n* HYUNDAI_GENESIS uses INDI controller. (Thanks to @donfyffe)\n* HYUNDAI_GENESIS 加入 Cruise 按紐 和 lkMode 支援。(感謝 @donfyffe 建議)\n* HYUNDAI_GENESIS added Cruise button event and lkMode feature. (Thanks to @donfyffe)\n* 支援台灣版 2018 Huyndai IONIQ + smart MDPS (dp_hkg_smart_mdps) (感謝 @andy741217 提供)\n* Support 2018 Taiwan Hyundai IONIQ + smart MDPS (dp_hkg_smart_mdps) (Thanks to @andy741217)\n* 使用 openpilot v0.8 的模型。(感謝 @eisenheim)\n* Use openpilot v0.8 model. (Thanks to @eisenheim)\n* 加入 0.8 測試版的部分優化。\n* Added optimizations from pre-0.8.\n* 加入 dp_honda_eps_mod 設定來使用更高的扭力 (需 eps mod)。(感謝 @Wuxl_369 提供)\n* Added dp_honda_eps_mod setting to enable higher torque (eps mod required). (Thanks to @Wuxl_369)\n* 修正 VW 對白/灰熊的支援 (感謝 @lirudy 提供)\n* Fixed issue with white/grey panda support for VW (Thanks to @lirudy)\n* GENESIS_G70 優化 (感謝 @sebastian4k 提供)\n* GENESIS_G70 Optimisation (Thanks to @sebastian4k)\n* HYUNDAI_GENESIS 優化 (感謝 @donfyffe 提供)\n* HYUNDAI_GENESIS Optimisation (Thanks to @donfyffe)\n* 加入 Dynamic gas Lite。(感謝 @toyboxZ 提供)\n* Added Dynamic Gas Lite. (Thanks to @toyboxZ)\n* 加入來自 afa 的 Honda inspire, accord, crv SnG 優化。(感謝 @menwenliang 提供)\n* Added Honda inspire, accord, crv SnG optimisation from afa fork. (Thanks to @menwenliang)\n* 加入 dp_toyota_lowest_cruise_override_vego。(感謝 @toyboxZ 提供)\n* Added dp_toyota_lowest_cruise_override_vego. (Thanks to @toyboxZ)\n\ndragonpilot 0.7.10.0\n========================\n* 基於最新 openpilot 0.7.10 devel.\n* Based on latest openpilot 0.7.10 devel.\n* 修正 Prius 特定情況下無法操控方向盤的問題。\n* Fixed unable to regain Prius steering control under certain condition.\n* 更新 VW MQB 的支援。(需執行 scripts/vw.sh 腳本)\n* Updated support of VW MQB. (scripts/vw.sh script required)\n* 新增 2018 China Toyota CHR 指紋v2。（感謝 @xiaohongcheung 提供)\n* Added 2018 China Toyota CHR FPv2. (Thanks to @xiaohongcheung)\n* 加入 Headunit Reloaded Android Auto App 支援。(感謝 @Ninjaa 提供)\n* Added Headunit Reloaded Android Auto App Support. (Thanks to @Ninjaa)\n* 優化 nanovg。(感謝 @piggy 提供)\n* Optomized nanovg. (Thanks to @piggy)\n* 加入 complete_setup.sh (感謝 @深鲸希西 提供)\n* Added complete_setup.sh (Thanks to @深鲸希西)\n* Based on latest openpilot 0.7.10 devel.\n* 修正 EON 接 PC/USB 充電器時仍會自動關機的錯誤。(感謝 @小愛 回報)\n* Fixed auto shutdown issue when EON connect to PC/USB Charger. (Thanks to @LOVEChen)\n* HYUNDAI_GENESIS 使用 INDI 控制器。(感謝 @donfyffe 提供)\n* HYUNDAI_GENESIS uses INDI controller. (Thanks to @donfyffe)\n\ndragonpilot 0.7.8.3\n========================\n* VW 加入 6 分鐘時間方向盤控制限制輔助方案。(特別感謝 @actuallylemoncurd 提供代碼)\n* VW added 6 minutes timebomb assist. (dp_timebomb_assist, special thanks to @actuallylemoncurd)\n\ndragonpilot 0.7.8.2\n========================\n* 修正在沒網路的情況下，開機超過五分鐘的問題。\n* Fixed 5+ minutes boot time issue when there is no internet connection.\n* 錯誤回傳改使用 dp 的主機。\n* Used dp server for error reporting.\n* 更新服務改使用 gitee 的 IP 檢查連線狀態。\n* updated service uses gitee IP address instead.\n\ndragonpilot 0.7.8.1\n========================\n* 加入 ko-KR 翻譯。\n* Added ko-KR translation.\n* 加入 Honda Jade 支援。(感謝 @李俊灝)\n* Added Honda Jade support. (Thanks to @lijunhao731)\n* 修正 ui.cc 內存越界的問題。(感謝 @piggy 提供)\n* Fixed ui.cc memory out of bound issue. (Thanks to @piggy)\n* gpxd 記錄改自動存成 zip 格式。\n* gpxd now store in zip format.\n* 強制關閉 panda 檢查 DOS 硬體。\n* Force disabled DOS hardware check in panda.\n\ndragonpilot 0.7.8.0\n========================\n* 基於最新 openpilot 0.7.8 devel.\n* Based on latest openpilot 0.7.8 devel.\n* 加入重置 DP 設定按鈕。(感謝 @LOVEChen 建議)\n* Added \"Reset DP Settings\" button. (Thanks to @LOVEChen)\n* 將警示訊息更改為類似於概念 UI 的設計。\n* Alert messages changed to concept UI alike design.\n* 當 manager 出現錯誤後，按 Exit 按鈕會執行 reset_update 腳本。\n* Added ability to execute reset_update.sh when press \"Exit\" button once manager returned errors.\n\ndragonpilot 0.7.7.3\n========================\n* 修正方向盤監控。\n* Fixed steering monitor timer param.\n* 修正行駛時關閉畫面導致當機的錯誤。(感謝 @salmankhan, @stevej99, @bobbydough 回報)\n* Fixed screen frozen issue when \"screen off while driving\" toggle is enabled. (Thanks to @salmankhan, @stevej99, @bobbydough)\n* 加回 Dev Mini UI 開關。(感謝 @Ninjaa 建議)\n* Re-added Dev Mini UI. (Thanks to @Ninjaa)\n* 新增 (dp_reset_live_parameters_on_start) 每次發車重設 LiveParameters 值。(感謝 @eisenheim)\n* Added ability (dp_reset_live_param_on_start) to reset LiveParameters on each start. (Thanks @eisenheim)\n* 修正同時開啟 dp_toyota_zss 和 dp_lqr 產生的錯誤。(感謝 @bobbydough)\n* Fixed error cuased by enabling both dp_toyota_zss and dp_lqr at the same time. (Thanks to @bobbydough)\n* 新增 (dp_gpxd) 將 GPS 軌跡導出至 GPX 格式 (/sdcard/gpx_logs/）的功能。 （感謝 @mageymoo1）\n* Added ability (dp_gpxd) to export GPS track into GPX files (/sdcard/gpx_logs/). (Thanks to @mageymoo1)\n* 使用德國的車道寬度估算值。 （感謝 @arne182）\n* Used lane width estimate value from Germany. (Thanks to @arne182)\n\ndragonpilot 0.7.7.2\n========================\n* 加入 d_poly offset。 (感謝 @ShaneSmiskol)\n* Added d_poly offset. (Thanks to @ShaneSmiskol)\n* 加入 ZSS 支援。(感謝 @bobbydough, @WilliamPrius 建議, @bobbydough 測試)\n* Added ZSS support. (Thanks to @bobbydough, @WilliamPrius for recommendation, @bobbydough for testing)\n* 加入錯誤記錄至 /sdcard/crash_logs/ (感謝 @ShaneSmiskol 提供代碼)\n* Added error logs to /sdcard/crash_logs/ (Special Thanks to @ShaneSmiskol)\n* 加入 LQR 控制器開關進設定畫面。\n* Added LQR Controller toggle to settings.\n\ndragonpilot 0.7.7.1\n========================\n* 加入 C2 風扇靜音模式。(感謝 @dingliangxue)\n* Added C2 quiet fan mode. (Thanks to @dingliangxue)\n* 加入「輔助換道最低啟動速度」、「自動換道最低啟動速度」設定。\n* Added \"Assisted Lane Change Min Engage Speed\" and \"Auto Lane Change Min Engage Speed\" settings.\n* 加入回調校介面。(感謝 @Kent)\n* Re-added Dev UI. (Thanks to @Kent)\n* 加入 \"dp_lqr\" 設定來強制使用 RAV4 的 lqr 調校。(感謝 @eisenheim)\n* Added \"dp_lqr\" setting to force enable lqr tuning from RAV4. (Thanks to eisenheim)\n\ndragonpilot 0.7.7.0\n========================\n* 基於最新 openpilot 0.7.7 devel.\n* Based on latest openpilot 0.7.7 devel.\n* 當 Manager 出現錯誤時，顯示 IP 位置。(感謝 @dingliangxue)\n* When Manager failed, display IP address. (Thanks to  @dingliangxue)\n* 加回 sr learner 開關。\n* Re-added sr learner toggle.\n* 加回 加速模式 開關。\n* Re-added Accel Profile toggle.\n* Toyota 加入改寫最低巡航速度功能。(感謝 @Mojo)\n* Added Toyota to override lowerest cruise speed. (Thanks to @Mojo)\n* 介面加入盲點偵測顯示。(感謝 @wabes)\n* Added BSM indicator to UI. (Thanks to @wabes)\n* 加回彎道減速功能。(感謝 @Mojo)\n* re-added Slow On Curve functionality. (Thanks to @Mojo)\n\ndragonpilot 0.7.6.2\n========================\n* 修正無法正確關閉駕駛監控的問題。\n* Fixed unable to properly turn off driver monitor issue.\n\ndragonpilot 0.7.6.1\n========================\n* 基於最新 openpilot 0.7.6.1 devel.\n* Based on latest openpilot 0.7.6.1 devel.\n* 優化並整合 dp 服務。 (所有的設定檔已改名，請重新設定所有的功能)\n* Optimized and integrated several dp services. (Settings have been renamed, please re-config all settings)\n* 完全關閉 steer ratio learner。\n* Completely disabled steer ratio learner.\n* 移除「加速模式」。\n* Removed Accel Profile.\n* 加入本田皓影混電版指紋v1。(感謝 @劉駿)\n* Added Honda Breeze Hybrid FPv1. (Thanks to @劉駿)\n* 加入台灣版 Toyota Prius 4.5 指紋v1。(感謝 @jeekid)\n* Added Taiwan Toyota Prius 4.5 FPv1. (Thanks to @jeekid)\n\ndragonpilot 0.7.5.4\n========================\n* Dynamic Follow 更新模型。(感謝 @ShaneSmiskol 提供代碼、 @cgw1968 測試)\n* Updated Dynamic Follow model. (Special Thanks to @ShaneSmiskol for the feature and @cgw1968 for testing)\n\ndragonpilot 0.7.5.3\n========================\n* Dynamic Follow 更新至 ShaneSmiskol:stock_additions 0.7.5 版。(感謝 @ShaneSmiskol 提供代碼、 @Wei 測試)\n* Updated Dynamic Follow to ShaneSmiskol:stock_additions 0.7.5. (Special Thanks to @ShaneSmiskol for the feature and @Wei for testing)\n* 優化 Lexus GSH 轉向。(感謝 @簡銘佑 測試)\n* Optimize Lexus GSH steering. (Thanks to @簡銘佑)\n* C2 支援自動關機「DragonAutoShutdownAt」參數。(感謝 @cgw1968 建議)\n* C2 to support auto shutdown \"DragonAutoShutDownAt\" param. (Thanks to @cgw1968)\n* 修正出現「pedalPressed」的錯誤。(感謝 @Wei 回報)\n* Fixed issue showing \"pedalPressed\" error. (Thanks to @Wei)\n* 將剎車狀熊顯示於 dp 資訊欄。\n* Added brake indicator to dp infobar.\n* 修正「溫度監控」燈示。\n* Fixed \"Temp monitor\" indicator.\n* 加入「方向燈取消控制」延遲控制設。(感謝 @wabes 建議)\n* Added delay config to \"Disable Lat Control on Blinker\". (Thanks to @wabes)\n* 加入巴西版 2020 Corolla Hybrid 指紋v2。(感謝 @berno22 提供)\n* Added Brazil 2020 Corolla Hybrid FPv2. (Thanks to @berno22)\n\ndragonpilot 0.7.5.2\n========================\n* 加入對 VW MQB/PQ 的支援。(感謝 @dingliangxue 移植)\n* Added support to VW MQB/PQ platform. (Thanks to @dingliangxue)\n* 修改成 3 小時後停止供電。(感謝 @Wei 建議)\n* Updated to stop charging after 3 hrs. (Thanks to @Wei)\n* 移除行車記錄下的「碰撞偵測」功能。\n* Removed Impact Detection in Dashcam.\n* 修正開啟「Noctua 風扇」模式導致的錯誤。(感謝 @阿濤 回報)\n* Fixed a bug caused by enabling \"Noctua Mod\". (Thanks to @阿濤)\n* 修正「位智模式」無法顯示警示的問題。(感謝 @axandres 回報)\n* Fixed alert issue in waze mode. (Thanks to @axandres)\n* 修正無法顯示更新中圖示的問題。\n* Fixed unable to display \"UPDATING\" icon issue.\n* 加入「允許多次自動換道」功能。(感謝 @阿濤 建議)\n* Added \"Allow Continuous Auto Lane Change\" Toggle. (Thanks to @阿濤)\n* 修正開機後設定頁面有時會錯誤的問題。(感謝 @salmankhan、@Wei 回報)\n* Fixed setting page crash issue. (Thanks to @salmankhan, @Wei)\n* 修正熄火後一直出現更新訊息的錯誤。(感謝 @Sky Chang 回報)\n* Fixed issue that keep showing update prompt. (Thanks to @Sky Chang)\n\ndragonpilot 0.7.5.1\n========================\n* 修正因同時使用「社群功能」和「自定車型」造成的加減速問題。(特別感謝 @Wei、@Sky Chang、@Han9365、@鄧育林 的測試以及回報。)\n* Fixed acceleration issue caused by used of both \"Community Maintain Feature\" and \"Custom Car Model\". (Special Thanks to @Wei, @Sky Chang, @Han9365, @鄧育林)\n* 新增 DragonMaxSpeedLimit 設定值 (mph)，當如果車速高於此值 op 將會停止操控。(感謝 @Anthony 建議)\n* Added DragonMaxSpeedLimit parameter (mph), op will stop controlling when car speed is high than the value. (Thanks to @Anthony)\n* 更新 appd 使用 cnpmjs 來下載 APKs。\n* Updated appd to use cnpmjs to download APKs.\n* 修正更新服務。(感謝 @Wei)\n* Fixed Update Service. (Thanks to @Wei)\n* 新增加拿大版 2018 Toyota Sienna LTD 指紋(v2)。(感謝 明峰 提供)\n* Added Canada 2018 Toyota Sienna LTD fingerprint (v2). (Thanks to 明峰)\n* 新增「通過移動網路上傳」開關\n* Added Upload Over Mobile Network toggle.\n* 新增「通過熱點上傳」開關\n* Added Upload Over Hotspot toggle.\n* 新增加拿大版 2018 Toyota Sienna LTD 指紋(v1)。(感謝 明峰 提供)\n* Added Canada 2018 Toyota Sienna LTD fingerprint (v1). (Thanks to 明峰)\n* 新增大陸版 Volkswagen Golf GTI 指紋 (v1)。(感謝 easyeiji 提供)\n* Added China Volkswagen Golf GTI fingerprint (v1). (Thanks to easyeiji)\n\ndragonpilot 0.7.5.0\n========================\n* 基於最新 openpilot 0.7.5 devel-staging.\n* Based on latest openpilot 0.7.5 devel-staging.\n* 更新 dp 圖示 (特別感謝 @wabes 的設計與提供)。\n* Updated dp logo, special thanks to @wabes for the design.\n* 簡/繁中文版和 i18n 整合成為單一版本。  \n* Merged zhs/zht/i18n versions into one.\n* 新增大陸版 CAMRY HYBRID 指紋v2。(感謝 @杜子腾)\n* Added China Camery Hybrid FPv2. (Thanks to @杜子腾)\n* 新增台灣版 Altis HYBRID 指紋v1。(感謝 @Fish)\n* Added Taiwan Altis Hybrid FPv1. (Thanks to @Fish)\n* 新增行駛時關閉畫面功能。\n* Added Screen off while driving feature.\n* 新增倒車時關閉畫面功能。\n* Added Screen off while reversing feature.\n* 新增駕駛介面加入「加速模式」切換鈕。\n* Added acceleration profile toggle onto driving UI.\n* 新增自定車型功能，取代指紋暫存功能。\n* Replaced fingerprint cache with custom car model selector.\n* 新增可調亮度。\n* Added Brightness changer.\n* 新增部分德語支持。(特別感謝 @arne182 提供)\n* Added partial de_DE language support (Thanks to @arne182)\n* 新增停車碰撞偵測記錄功能。\n* Added off road impact detection to dashcam.\n\n2020-05-06\n========================\n* 更新 dp 圖示 (特別感謝 @wabes 的設計與提供)。\n* 中文版整合進 i18n 版。  \n* 刪除指紋暫存功能。\n* 新增 CAMERY HIBRID 指紋。(感謝 @杜子腾)\n* 新增行駛時關閉畫面功能。\n* 新增倒車時關閉畫面功能。\n* 新增駕駛介面加入「加速模式」切換鈕。\n* 新增自定義車型。\n\n2020-04-16\n========================\n* [DEVEL] 加入台灣版 2016 Lexus IS200t 指紋。(感謝 Philip / Cody Dai)\n* [DEVEL] 加入台灣版 2016 Toyota Prius 4.5 代指紋。(感謝 Philip)\n* [DEVEL] 加入台灣版 201x Toyota RAV4 4WD 指紋。(感謝 Philip)\n* [DEVEL] 加入台灣版 2020 Toyota Auris w/ LTA 指紋。(感謝 Philip)\n* [DEVEL] 修正 commIssue 錯誤。(感謝 Kent 協助)\n\n2020-04-13\n========================\n* [DEVEL] 加入可調整 Toyota Sng 起步反應值 (DragonToyotaSngResponse)。 (特別感謝 @Wei 提供 PR)\n* [DEVEL] 駕駛介面加入「動態調整車距」按鈕。(感謝 @cgw1968-5779 建議)\n* [DEVEL] 更新 update script。(感謝 深鯨希西 回報)\n\n2020-04-10\n========================\n* [DEVEL] 更新 panda 至最新的 comma:master 分支。\n* [DEVEL] 移除所有的第三方應用改為自動下載。\n* [DEVEL] 移除「啟用原廠 DSU 模式」、「安全帶檢查」、「車門檢查」開關。\n\n2020-03-31\n========================\n* [DEVEL] 更新至 2020-03-31 testing 分支。\n\n2020-03-27\n========================\n* [DEVEL] 更新至最新的 testing 分支:\n  * 加入波蘭版 2015 Lexus NX200T 支援。(感謝 wabes 提供)\n  * 調整「啟用原廠 DSU 模式」為不再需要 AHB 。(Enable Stock DSU Mode no longer requires \"AHB\" toggle)\n  * 加入「安全帶檢查」、「車門檢查」、「檔位檢查」、「溫度檢查」開關。\n  * 加入曲率學習功能 - Curvature Learner 。(感謝 zorrobyte 提供)\n  * 加入大陸版 2018 Toyota Highlander 支援。(感謝 toyboxZ 提供)\n  * 加入大陸版 2018 Toyota Camry 2.0 支援。(感謝 Rming 提供)\n  * 加入韓文支持。(感謝 crwusiz 提供)\n  * 調整 OFFROAD 主頁翻譯將 \"dragonpilot\" 改回 \"openpilot\"。\n\n2020-03-22\n========================\n* [DEVEL] 更新至最新的 testing 分支。\n\n2020-03-17\n========================\n* [DEVEL] 更新至最新的 testing 分支 (commaai:devel-staging 0.7.4)。\n* [DEVEL] 加入動態調整車距功能。(特別感謝 @ShaneSmiskol 提供 PR)\n\n2020-03-14\n========================\n* [DEVEL] 更新 pt-Br (葡萄牙語) 翻譯。(感謝 berno22 提供)\n* [DEVEL] 加入自動關機開關。(感謝 Rzxd 建議)\n* [DEVEL] 調高 Toyota 扭力容錯值。\n* [DEVEL] 優化讀取 dp 設定值。\n* [DEVEL] 加入 2019 手動 Civic 指紋。感謝 (AlexNoop 提供)\n* [DEVEL] dp 功能加入對 Subaru 車系的支援。\n\n2020-03-06\n========================\n* [DEVEL] 加入葡萄牙語支持。(感謝 berno22 提供)\n* [DEVEL] 加入大陸 2018 Camry、2020 RAV4 指紋。(感謝 笨木匠 提供)\n* [DEVEL] 建立 devel-i18n 取代 devel-en。\n* [DEVEL] devel-en is deprecated, please switch to devel-i18n instead.\n\n2020-03-04\n========================\n* [DEVEL] 加入顯示駕駛監控畫面。\n* [DEVEL] 加入加速模式選項。(特別感謝 @arne182, @cgw1968-5779 提供 PR)\n* [DEVEL] 修正 shutdownd 在 comma two 可能會不正常關機的錯誤。(感謝 @Wei, @Rzxd 回報)\n\n2020-02-25\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.3)。\n\n2020-02-21\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.3)。\n\n2020-02-14\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.2)。\n* [DEVEL] 修正錯誤。\n\n2020-02-08\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.2)。\n* [DEVEL] dp 功能加入對現代 (Hyundai) 車系的支援。\n* [DEVEL] 加入神盾測速照相自動啟動的開關。\n* [DEVEL] 更新高德地圖至 v4.5.0.600053。\n* [DEVEL] 使用 0.6.6 版的更新系統。\n* [DEVEL] 修正急剎問題。(感謝 kumar 提供)\n\n2020-01-31\n========================\n* [DEVEL] 移除行車介面電量、溫度顯示，(修正畫面當機、黑屏問題)\n\n2020-01-29\n========================\n* [DEVEL] 修正行車介面錯誤。(感謝 深鲸希西 測試；eisenheim、HeatNation 反應)\n\n2020-01-23\n========================\n* [DEVEL] 加入 Steer Ratio Learner 關閉。(感謝 eisenheim 建議)\n* [DEVEL] 行車介面加入電量、溫度。(感謝 eisenheim 建議)\n* [DEVEL] 優化 appd。\n\n2020-01-19\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.1)。\n* [DEVEL] 調整 appd 和 ALC 邏輯。\n\n2020-01-14\n========================\n* [DEVEL] 加入開機啟動個人熱點。(感謝 eisenheim 建議)\n\n2020-01-08\n========================\n* [DEVEL] 加入大陸版 2018 Lexus RX300 支援。(感謝 cafe 提供)\n* [DEVEL] 加入 DragonBTG 設定。(感謝 CloudJ、低調哥、歐姓Altis車主 提供)\n\n2019-12-31\n========================\n* [DEVEL-ZHS] 加回第三方應用。\n\n2019-12-29\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.0)。\n* [DEVEL] 輔助/自動變道改為可調整參數 (進階用戶)。(DragonAssistedLCMinMPH、DragonAutoLCMinMPH、DragonAutoLCDelay)\n* [DEVEL-ZHS] 修正無法運行第三方應用錯誤。(感謝 深鲸希西 反應)\n\n2019-12-18\n========================\n* [DEVEL] 修正自動換道邏輯。\n* [DEVEL] 更新 offroad 翻譯。\n* [DEVEL] 錯誤修正。\n* [DEVEL] 移除美版 2017 Civic Hatchback 指紋。(與其它車型衝突)\n\n2019-12-17\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.7.0)。\n* [DEVEL] 加入輔助換道開關。（24mph / 40kph 以上)\n* [DEVEL] 加入自動換道開關。（40mph / 65kph 以上)\n* [DEVEL] 加入大陸版 2019 雷凌汽油版指紋。 (感謝 Shell 提供)\n* [DEVEL] 加入大陸版 2019 卡羅拉汽油版指紋。 (感謝 Shell 提供)\n* [DEVEL] 加入美版 2017 Civic Hatchback 指紋。(感謝 CFranHonda 提供)\n\n2019-12-10\n========================\n* [DEVEL] 加入位智車機模式。 (Waze Mode)\n\n2019-11-21\n========================\n* [DEVEL] 修正 offroad 翻譯。(感謝 鄧育林 回報)\n* [DEVEL] 調整前車靜止移動偵測參數。\n* [DEVEL] 前車靜止移動偵測可在未啟用 dp 時運作。\n\n2019-11-18\n========================\n* [DEVEL] 修正 offroad 翻譯。(感謝 Cody、鄧育林 回報)\n\n2019-11-18\n========================\n* [DEVEL] 修正 frame 翻譯。\n\n2019-11-15\n========================\n* [DEVEL] 修正不會充電的錯誤。 (感謝 袁昊 反應)\n\n2019-11-15\n========================\n* [DEVEL] 修正充電控制。 (感謝 KT 反應)\n* [DEVEL] 更新 frame 翻譯，改為多語言版。 (感謝 深鲸希西、shaoching885、鄧育林 反應)\n* [DEVEL] 更新至最新的 commaai:devel (0.6.6)。\n\n2019-11-12\n========================\n* [DEVEL] 只顯示電量文字 (注意：有時不會更新，需要拔插 USB 線)\n* [DEVEL] 自動偵測並鎖定硬體 (EON / UNO)。\n\n2019-11-12\n========================\n* [DEVEL] 加入鎖定硬體 (EON / UNO) 的程式碼。\n\n2019-11-11\n========================\n* [DEVEL] 更新高德地圖至 v4.3.0.600310 R2098NSLAE\n* [DEVEL] 更新 MiXplorer 至 v6.40.3\n* [DEVEL] 更新至最新的 commaai:devel (0.6.6)。\n* [DEVEL] 前車靜止移動偵測加入偵測警示。\n\n2019-11-07\n========================\n* [DEVEL] 讓 Bosch 系統顯示三角。 (感謝 ching885 回報)\n* [DEVEL] 更新 offroad 多語言版簡體中文翻譯 (感謝 Rming 提供)\n\n2019-11-06\n========================\n* [DEVEL] 修正 0.6.6 appd 和 dashcamd 錯誤。 (感謝 鄧育林 回報)\n* [DEVEL] 更新至最新的 commaai:devel (0.6.6)。\n\n2019-11-05\n========================\n* [DEVEL] 加入台灣 Lexus 2017 GS450h 支援。 (感謝 簡銘佑 提供指紋)\n\n2019-11-01\n========================\n* [DEVEL] 新增神盾測速照相。 (感謝 Sky Chang 和 Wei Yi Chen)\n* [DEVEL] 修正 offroad 翻譯。 (感謝 Leo Hsieh)\n\n2019-11-01\n========================\n* [DEVEL] 移除 Miui 字型，縮小 dp 使用空間。\n* [DEVEL] 更新 offroad 為多語言版\n* [DEVEL] 更新至最新的 commaai:devel (0.6.5)。\n\n2019-10-29\n========================\n* [DEVEL] 加入 SnG 補丁。（感謝 楊雅智)\n\n2019-10-28\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.6.5)。\n* [DEVEL] 調整 dragon_allow_gas 邏輯 (請回報任何問題，需更新 Panda 韌體)\n\n2019-10-18\n========================\n* [DEVEL] 加入前車靜止移動偵測。(測試版，感謝 ucolchen)\n* [DEVEL] 移除強迫網路連線提示。(感謝 Shell)\n* [DEVEL] 修正 allow_gas 功能。\n\n2019-10-18\n========================\n* [DEVEL] 加入彎道減速功能開關。\n* [DEVEL] 強迫使用 dp 版 Panda 韌體。\n* [DEVEL] 更新至最新的 commaai:devel (0.6.5)。\n\n2019-10-17\n========================\n* [DEVEL] 加入「車型」顯示於 dp 設定畫面。\n* [DEVEL] 修正充電控制讀取預設值的錯誤。\n* [DEVEL] 修正無法顯示更新記錄的錯誤。\n\n2019-10-16\n========================\n* [DEVEL] 刷新 Panda 韌體按鈕將會自動重啟 EON。(感謝 鄧育林 建議)\n* [DEVEL] 下載更新記錄時使用 \"no-cache\" 標頭。\n* [DEVEL] 更新高德地圖至 v4.3.0\n* [DEVEL] 刪除 bs (Branch Switcher)\n\n2019-10-14\n========================\n* [DEVEL] 啟用自動更新功能。(感謝 鄧育林 提供)\n* [DEVEL] 清除不再使用的 dp params。\n* [DEVEL] 加入數字電量指示。(感謝 鄧育林 建議)\n* [DEVEL] 加入刷新 Panda 韌體按鈕。\n\n2019-10-11\n========================\n* [DEVEL] 更新至最新的 commaai:devel (0.6.5)。\n* [DEVEL] 加入台灣 2019 RAV4 汽油版指紋。 (感謝 Max Duan / CloudJ 提供)\n\n2019-10-09\n========================\n* [DEVEL] 加入當 LatCtrl 關閉時，畫面顯示提示訊息。\n\n2019-10-08\n========================\n* [DEVEL] 加回駕駛監控開關。\n* [DEVEL] 加入 bs (branch switcher) 程式。\n\n2019-10-07\n========================\n* [DEVEL] 加入台灣版 2019 RAV4H 油電版指紋。(感謝 Max Duan 提供)\n\n2019-10-05\n========================\n* [DEVEL] 移除 curvature learner: 轉角明顯比原廠小。\n* [DEVEL] 更新至最新的 commaai:devel (0.6.4)。\n\n2019-09-30\n========================\n* [DEVEL] 更新 curvature learner 版本至 v4。\n* [DEVEL] Lexus ISH 使用更精確的 EPS Steering Angle Sensor\n\n2019-09-27\n========================\n* [DEVEL] 加入 Zorrobyte 的 curvature learner (https://github.com/zorrobyte/openpilot)\n* [DEVEL] 加入可開關駕駛監控的程式碼。\n* [DEVEL] 取消當 steering 出現錯誤時，自動切斷方向控制 2 秒的機制。\n* [DEVEL] 讓行車介面的「方向盤」/「轉彎」圖示半透明化。\n\n2019-09-26\n========================\n* [DEVEL] 修正當「啟用記錄服務」關閉時，make 會有問題的錯誤。 (感謝 shaoching885 和 afa 回報)\n\n2019-09-24\n========================\n* [DEVEL] 行車介面加入可開關的「前車」、「路線」、「車道」設定。\n* [DEVEL] 行車介面加入可開關的「方向燈號」提示。 (感謝 CloudJ 建議，程式碼來源: https://github.com/kegman/openpilot)\n\n2019-09-23\n========================\n* [DEVEL] 優化讀取 params 的次數。\n* [DEVEL] 加入可開關的車道偏移警示。\n* [DEVEL] 修正充電控制邏輯。\n* [DEVEL] 加入台灣 Prius 4.5 指紋。 (感謝 Lin Hsin Hung 提供)\n\n2019-09-20\n========================\n* [DEVEL] 加入充電控制功能。 (感謝 loveloveses 和 KT 建議)\n\n2019-09-16\n========================\n* [DEVEL] 加入台灣 CT200h 指紋。 (感謝 CloudJ 提供)\n* [DEVEL] 加入美版 CT200h 移植。 (感謝 thomaspich 提供)\n\n2019-09-13\n========================\n* [DEVEL] 行車介面加入可開關的「速度顯示」設定。\n\n2019-09-09\n========================\n* [DEVEL] 加入 GreyPanda 模式。\n\n2019-08-28\n========================\n* [DEVEL] 加入可調警示音量。\n\n2019-08-27\n========================\n* [DEVEL] 自動關機改為可調時長。\n"
  },
  {
    "path": "CONTRIBUTING.md",
    "content": "# How to contribute\n\nOur software is open source so you can solve your own problems without needing help from others. And if you solve a problem and are so kind, you can upstream it for the rest of the world to use.\n\nMost open source development activity is coordinated through our [GitHub Discussions](https://github.com/commaai/openpilot/discussions) and [Discord](https://discord.comma.ai). A lot of documentation is available on our [blog](https://blog.comma.ai/).\n\n## Getting Started\n\n * Join our [Discord](https://discord.comma.ai)\n * Make sure you have a [GitHub account](https://github.com/signup/free)\n * Fork [our repositories](https://github.com/commaai) on GitHub\n\n## Testing\n\n### Automated Testing\n\nAll PRs and commits are automatically checked by GitHub Actions. Check out `.github/workflows/` for what GitHub Actions runs. Any new tests should be added to GitHub Actions.\n\n### Code Style and Linting\n\nCode is automatically checked for style by GitHub Actions as part of the automated tests. You can also run these tests yourself by running `pre-commit run --all`.\n\n## Car Ports (openpilot)\n\nWe've released a [Model Port guide](https://blog.comma.ai/openpilot-port-guide-for-toyota-models/) for porting to Toyota/Lexus models.\n\nIf you port openpilot to a substantially new car brand, see this more generic [Brand Port guide](https://blog.comma.ai/how-to-write-a-car-port-for-openpilot/).\n\n## Pull Requests\n\nPull requests should be against the master branch. Before running master on in-car hardware, you'll need to clone the submodules too. That can be done by recursively cloning the repository:\n```\ngit clone https://github.com/commaai/openpilot.git --recursive\n```\nOr alternatively, when on the master branch:\n```\ngit submodule update --init\n```\nThe reasons for having submodules on a dedicated repository and our new development philosophy can be found in our [post about externalization](https://blog.comma.ai/a-2020-theme-externalization/).\nModules that are in seperate repositories include:\n* cereal\n* laika\n* opendbc\n* panda\n* rednose\n"
  },
  {
    "path": "CONTRIBUTORS.md",
    "content": "# CONTRIBUTORS\n\nDue to the way we manage the source code, it is not possible to see all the contributors' info, hence we create a list here.\nIf you have contributed to DP project before and your name is not listed here, feel free to send us a PR to update this!\n\n### TEAM\nName                                                         | github                                                       | Role\n------------------------------------------------------------ | ------------------------------------------------------------ | ------------------------------------------------------------\ncafe                                                         | [cafe](https://github.com/coffice12)                         | Resource Provider\ncgw1968                                                      | [cgw1968](https://github.com/cgw1968-5779)                   | C2/C3 Toyota Beta Tester\nkumar                                                        | [rav4kumar](https://github.com/rav4kumar)                    | Release Maintainer\nloveloveses                                                  | [loveloveses](https://github.com/loveloveses)                | Wiki Maintainer\nRick Lan                                                     | [efinilan](https://github.com/efinilan)                      | Release Maintainer\nStupefacient                                                 | [Stupefacient](https://github.com/Stupefacient)              | C2/C3 Toyota Beta Tester\nCCZ                                                          | [CCZ](https://github.com/czdeee)                             | UI developer, Simplified Chinese Translator\n\n### CONTRIBUTORS\nName                                                         | github                                                      \n------------------------------------------------------------ | ------------------------------------------------------------\nandy741217                                                   | [andy741217](https://github.com/andy741217)                 \nArne Schwarck                                                | [arne182](https://github.com/arne182)                       \nberno22                                                      | [berno22](https://github.com/berno22)                       \nBobbydough                                                   | [Bobbydough](https://github.com/bobbydough)                 \nTIM                                                          | [TIM](https://github.com/CT921)                             \nCurtis Jenkins                                               | [actuallylemoncurd](https://github.com/actuallylemoncurd)   \nDFyffe                                                       | [donfyffe](https://github.com/donfyffe)                     \ndinglx                                                       | [dingliangxue](https://github.com/dingliangxue)             \neyezenheim                                                   | [eyezenheim](https://github.com/eyezenheim)                 \nJason Wen                                                    | [sunnyhaibin](https://github.com/sunnyhaibin)               \nkegman                                                       | [kegman](https://github.com/kegman)                         \nlijunhao731                                                  | [lijunhao731](https://github.com/lijunhao731)               \nlirudy                                                       | [lirudy](https://github.com/lirudy)                         \nLOVEChen                                                     | [LOVEChen](https://github.com/LOVEChen)                     \nmenwenliang                                                  | [menwenliang](https://github.com/menwenliang)               \nmove-fast                                                    | [move-fast](https://github.com/move-fast)                   \nNelson Chen                                                  | [nelsonjchen](https://github.com/nelsonjchen)               \nrming                                                        | [Rming](https://github.com/rming)                           \nsebastian4k                                                  | [sebastian4k](https://github.com/sebastian4k)               \nShane Smiskol                                                | [sshane](https://github.com/sshane)                         \ntoyboxZ                                                      | [toyboxZ](https://github.com/toyboxZ)                       \n"
  },
  {
    "path": "HOWTO-ONEPLUS.md",
    "content": "How to install on Oneplus 3t?\n------\n1. clone dragonpilot to /data/ and make sure it's named openpilot:\n   (手動安裝切換至 dp)\n```\ncd /data/ && rm -fr openpilot ; git clone https://github.com/dragonpilot-community/dragonpilot.git openpilot -b 0.8.8\n```\n\n2. run command:\n   (在 ssh 畫面下，輸入)\n```\ncd /data/openpilot/scripts/ && ./oneplus_update_neos.sh\n```\n\n3. Let it download and complete it update, after a couple of reboot, your screen will then stay in fastboot mode.\n   (等待下載並讓它重新開機，沒錯誤的話會進入 Android 機器人更新畫面，等自動重新開機)\n\n4. In fastboot mode, select use volume button to select to `Recovery mode` then press power button.\n   (在 fastboot 模式，用音量鍵上下選到 Recovery mode 再按下電源鍵)\n\n5. In Recovery mode, tap `apply update` -> `Choose from emulated` -> `0/` -> `update.zip` -> `Reboot system now`\n   (在 Recovery mode，點選 `apply update` -> `Choose from emulated` -> `0/` -> `update.zip` -> `Reboot system now`)\n   \n6. You should be able to boot into openpilot, if touch screen is not working, try to reboot again.\n   (你現在應該可以進入 openpilot 畫面，如果點擊畫面沒有反應，請再重新開機一次)\n"
  },
  {
    "path": "HOWTO-Translate.md",
    "content": "HOW TO Translate dragonpilot\n--\n\nIf you would like to help to translate dragonpilot into your native language, please:\n1. Contact dragonpilot team to generate language files for translation.\n\n2. Start translation, there will be 2 files: (locale = your language code)\n    * <openpilot>/selfdrive/assets/locales/**locale**/LC_MESSAGES/events.po\n      * This is for alerts messages. (e.g. on road warning messages) \n    * <openpilot>/selfdrive/ui/translations/**locale**.ts\n      * This is for UI. (e.g. settings pages)\n\n   We recommended to use a proper editor such as TextMate (mac) / notepad++ (win) / Intellij pyCharm.\n\n\n3. Submit a PR for your translation.\n\n4. dragonpilot team will review your PR and add it in the next release."
  },
  {
    "path": "Jenkinsfile",
    "content": "def phone(String ip, String step_label, String cmd) {\n  withCredentials([file(credentialsId: 'id_rsa', variable: 'key_file')]) {\n    def ssh_cmd = \"\"\"\nssh -tt -o StrictHostKeyChecking=no -i ${key_file} -p 8022 'comma@${ip}' /usr/bin/bash <<'EOF'\n\nset -e\n\nexport CI=1\nexport TEST_DIR=${env.TEST_DIR}\nexport SOURCE_DIR=${env.SOURCE_DIR}\nexport GIT_BRANCH=${env.GIT_BRANCH}\nexport GIT_COMMIT=${env.GIT_COMMIT}\n\nsource ~/.bash_profile\nif [ -f /TICI ]; then\n  source /etc/profile\nfi\n\nln -snf ${env.TEST_DIR} /data/pythonpath\n\nif [ -f /EON ]; then\n  echo \\$\\$ > /dev/cpuset/app/tasks || true\n  echo \\$PPID > /dev/cpuset/app/tasks || true\n  mkdir -p /dev/shm\n  chmod 777 /dev/shm\nfi\n\ncd ${env.TEST_DIR} || true\n${cmd}\nexit 0\n\nEOF\"\"\"\n\n    sh script: ssh_cmd, label: step_label\n  }\n}\n\ndef phone_steps(String device_type, steps) {\n  lock(resource: \"\", label: device_type, inversePrecedence: true, variable: 'device_ip', quantity: 1) {\n    timeout(time: 150, unit: 'MINUTES') {\n      phone(device_ip, \"git checkout\", readFile(\"selfdrive/test/setup_device_ci.sh\"),)\n      steps.each { item ->\n        phone(device_ip, item[0], item[1])\n      }\n    }\n  }\n}\n\npipeline {\n  agent none\n  environment {\n    TEST_DIR = \"/data/openpilot\"\n    SOURCE_DIR = \"/data/openpilot_source/\"\n  }\n  options {\n      timeout(time: 3, unit: 'HOURS')\n  }\n\n  stages {\n\n    stage('Build release2') {\n      agent {\n        docker {\n          image 'python:3.7.3'\n          args '--user=root'\n        }\n      }\n      when {\n        branch 'devel-staging'\n      }\n      steps {\n        phone_steps(\"eon-build\", [\n          [\"build release2-staging & dashcam-staging\", \"cd release && PUSH=1 ./build_release2.sh\"],\n        ])\n      }\n    }\n\n    stage('Build release3') {\n      agent {\n        docker {\n          image 'python:3.7.3'\n          args '--user=root'\n        }\n      }\n      when {\n        branch 'devel-staging'\n      }\n      steps {\n        phone_steps(\"tici\", [\n          [\"build release3-staging & dashcam3-staging\", \"PUSH=1 $SOURCE_DIR/release/build_release3.sh\"],\n        ])\n      }\n    }\n\n    stage('openpilot tests') {\n      when {\n        not {\n          anyOf {\n            branch 'master-ci'; branch 'devel'; branch 'devel-staging';\n            branch 'release2'; branch 'release2-staging'; branch 'dashcam'; branch 'dashcam-staging';\n            branch 'release3'; branch 'release3-staging'; branch 'dashcam3'; branch 'dashcam3-staging';\n            branch 'testing-closet*'; branch 'hotfix-*'\n          }\n        }\n      }\n\n      stages {\n\n        /*\n        stage('PC tests') {\n          agent {\n            dockerfile {\n              filename 'Dockerfile.openpilotci'\n              args '--privileged --shm-size=1G --user=root'\n            }\n          }\n          stages {\n            stage('Build') {\n              steps {\n                sh 'scons -j$(nproc)'\n              }\n            }\n          }\n          post {\n            always {\n              // fix permissions since docker runs as another user\n              sh \"chmod -R 777 .\"\n            }\n          }\n        }\n        */\n\n        stage('On-device Tests') {\n          agent {\n            docker {\n              /*\n              filename 'Dockerfile.ondevice_ci'\n              args \"--privileged -v /dev:/dev --shm-size=1G --user=root\"\n              */\n              image 'python:3.7.3'\n              args '--user=root'\n            }\n          }\n\n          stages {\n            stage('parallel tests') {\n              parallel {\n                stage('Devel Tests') {\n                  steps {\n                    phone_steps(\"eon-build\", [\n                      [\"build devel\", \"cd $SOURCE_DIR/release && EXTRA_FILES='tools/' ./build_devel.sh\"],\n                      [\"build openpilot\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"test manager\", \"python selfdrive/manager/test/test_manager.py\"],\n                      [\"onroad tests\", \"cd selfdrive/test/ && ./test_onroad.py\"],\n                      [\"test car interfaces\", \"cd selfdrive/car/tests/ && ./test_car_interfaces.py\"],\n                    ])\n                  }\n                }\n\n                stage('Replay Tests') {\n                  steps {\n                    phone_steps(\"eon2\", [\n                      [\"build\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"model replay\", \"cd selfdrive/test/process_replay && ./model_replay.py\"],\n                    ])\n                  }\n                }\n\n                stage('HW + Unit Tests') {\n                  steps {\n                    phone_steps(\"eon\", [\n                      [\"build\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"test athena\", \"nosetests -s selfdrive/athena/tests/test_athenad_old.py\"],\n                      [\"test sounds\", \"nosetests -s selfdrive/ui/tests/test_sounds.py\"],\n                      [\"test boardd loopback\", \"nosetests -s selfdrive/boardd/tests/test_boardd_loopback.py\"],\n                      [\"test loggerd\", \"python selfdrive/loggerd/tests/test_loggerd.py\"],\n                      [\"test encoder\", \"python selfdrive/loggerd/tests/test_encoder.py\"],\n                      [\"test logcatd\", \"python selfdrive/logcatd/tests/test_logcatd_android.py\"],\n                      //[\"test updater\", \"python installer/updater/test_updater.py\"],\n                    ])\n                  }\n                }\n\n                /*\n                stage('Power Consumption Tests') {\n                  steps {\n                    lock(resource: \"\", label: \"c2-zookeeper\", inversePrecedence: true, variable: 'device_ip', quantity: 1) {\n                      timeout(time: 90, unit: 'MINUTES') {\n                        sh script: \"/home/batman/tools/zookeeper/enable_and_wait.py $device_ip 120\", label: \"turn on device\"\n                        phone(device_ip, \"git checkout\", readFile(\"selfdrive/test/setup_device_ci.sh\"),)\n                        phone(device_ip, \"build\", \"scons -j4 && sync\")\n                        sh script: \"/home/batman/tools/zookeeper/disable.py $device_ip\", label: \"turn off device\"\n                        sh script: \"/home/batman/tools/zookeeper/enable_and_wait.py $device_ip 120\", label: \"turn on device\"\n                        sh script: \"/home/batman/tools/zookeeper/check_consumption.py 60 3\", label: \"idle power consumption after boot\"\n                        sh script: \"/home/batman/tools/zookeeper/ignition.py 1\", label: \"go onroad\"\n                        sh script: \"/home/batman/tools/zookeeper/check_consumption.py 60 10\", label: \"onroad power consumption\"\n                        sh script: \"/home/batman/tools/zookeeper/ignition.py 0\", label: \"go offroad\"\n                        sh script: \"/home/batman/tools/zookeeper/check_consumption.py 60 2\", label: \"idle power consumption offroad\"\n                      }\n                    }\n                  }\n                }\n                */\n\n                stage('tici Build') {\n                  environment {\n                    R3_PUSH = \"${env.BRANCH_NAME == 'master' ? '1' : ' '}\"\n                  }\n                  steps {\n                    phone_steps(\"tici\", [\n                      [\"build\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"onroad tests\", \"cd selfdrive/test/ && ./test_onroad.py\"],\n                    ])\n                  }\n                }\n\n                stage('Unit Tests (tici)') {\n                  steps {\n                    phone_steps(\"tici2\", [\n                      [\"build\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"test loggerd\", \"python selfdrive/loggerd/tests/test_loggerd.py\"],\n                      [\"test encoder\", \"LD_LIBRARY_PATH=/usr/local/lib python selfdrive/loggerd/tests/test_encoder.py\"],\n                    ])\n                  }\n                }\n\n                stage('camerad') {\n                  steps {\n                    phone_steps(\"eon-party\", [\n                      [\"build\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"test camerad\", \"python selfdrive/camerad/test/test_camerad.py\"],\n                      [\"test exposure\", \"python selfdrive/camerad/test/test_exposure.py\"],\n                    ])\n                  }\n                }\n\n                stage('Tici camerad') {\n                  steps {\n                    phone_steps(\"tici-party\", [\n                      [\"build\", \"cd selfdrive/manager && ./build.py\"],\n                      [\"test camerad\", \"python selfdrive/camerad/test/test_camerad.py\"],\n                      [\"test exposure\", \"python selfdrive/camerad/test/test_exposure.py\"],\n                    ])\n                  }\n                }\n\n              }\n            }\n\n            stage('Push master-ci') {\n              when {\n                branch 'master'\n              }\n              steps {\n                phone_steps(\"eon-build\", [\n                  [\"push devel\", \"cd $SOURCE_DIR/release && PUSH='master-ci' ./build_devel.sh\"],\n                ])\n              }\n            }\n\n          }\n\n          post {\n            always {\n              cleanWs()\n            }\n          }\n\n        }\n\n      }\n    }\n  }\n}\n\n"
  },
  {
    "path": "LICENSE",
    "content": "Copyright (c) 2018, Comma.ai, Inc.\n\nPermission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the \"Software\"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n"
  },
  {
    "path": "README-openpilot.md",
    "content": "![](https://user-images.githubusercontent.com/37757984/127420744-89ca219c-8f8e-46d3-bccf-c1cb53b81bb1.png)\n\nTable of Contents\n=======================\n\n* [What is openpilot?](#what-is-openpilot)\n* [Integration with Stock Features](#integration-with-stock-features)\n* [Supported Hardware](#supported-hardware)\n* [Supported Cars](#supported-cars)\n* [Community Maintained Cars and Features](#community-maintained-cars-and-features)\n* [Installation Instructions](#installation-instructions)\n* [Limitations of openpilot ALC and LDW](#limitations-of-openpilot-alc-and-ldw)\n* [Limitations of openpilot ACC and FCW](#limitations-of-openpilot-acc-and-fcw)\n* [Limitations of openpilot DM](#limitations-of-openpilot-dm)\n* [User Data and comma Account](#user-data-and-comma-account)\n* [Safety and Testing](#safety-and-testing)\n* [Testing on PC](#testing-on-pc)\n* [Community and Contributing](#community-and-contributing)\n* [Directory Structure](#directory-structure)\n* [Licensing](#licensing)\n\n---\n\nWhat is openpilot?\n------\n\n[openpilot](http://github.com/commaai/openpilot) is an open source driver assistance system. Currently, openpilot performs the functions of Adaptive Cruise Control (ACC), Automated Lane Centering (ALC), Forward Collision Warning (FCW) and Lane Departure Warning (LDW) for a growing variety of supported [car makes, models and model years](#supported-cars). In addition, while openpilot is engaged, a camera based Driver Monitoring (DM) feature alerts distracted and asleep drivers.\n\n<table>\n  <tr>\n    <td><a href=\"https://www.youtube.com/watch?v=mgAbfr42oI8\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/kAtT6Ei.png\"></a></td>\n    <td><a href=\"https://www.youtube.com/watch?v=394rJKeh76k\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/lTt8cS2.png\"></a></td>\n    <td><a href=\"https://www.youtube.com/watch?v=1iNOc3cq8cs\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/ANnuSpe.png\"></a></td>\n    <td><a href=\"https://www.youtube.com/watch?v=Vr6NgrB-zHw\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/Qypanuq.png\"></a></td>\n  </tr>\n  <tr>\n    <td><a href=\"https://www.youtube.com/watch?v=Ug41KIKF0oo\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/3caZ7xM.png\"></a></td>\n    <td><a href=\"https://www.youtube.com/watch?v=NVR_CdG1FRg\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/bAZOwql.png\"></a></td>\n    <td><a href=\"https://www.youtube.com/watch?v=tkEvIdzdfUE\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/EFINEzG.png\"></a></td>\n    <td><a href=\"https://www.youtube.com/watch?v=_P-N1ewNne4\" title=\"YouTube\" rel=\"noopener\"><img src=\"https://i.imgur.com/gAyAq22.png\"></a></td>\n  </tr>\n</table>\n\nIntegration with Stock Features\n------\n\nIn all supported cars:\n* Stock Lane Keep Assist (LKA) and stock ALC are replaced by openpilot ALC, which only functions when openpilot is engaged by the user.\n* Stock LDW is replaced by openpilot LDW.\n\nAdditionally, on specific supported cars (see ACC column in [supported cars](#supported-cars)):\n* Stock ACC is replaced by openpilot ACC.\n* openpilot FCW operates in addition to stock FCW.\n\nopenpilot should preserve all other vehicle's stock features, including, but are not limited to: FCW, Automatic Emergency Braking (AEB), auto high-beam, blind spot warning, and side collision warning.\n\nSupported Hardware\n------\n\nAt the moment, openpilot supports the EON Gold DevKit, [comma two](https://comma.ai/shop/products/two), and [comma three](https://comma.ai/shop/products/three). A [car harness](https://comma.ai/shop/products/car-harness) is recommended to connect your device to the car. For experimental purposes, openpilot can also run on an Ubuntu computer with external [webcams](https://github.com/commaai/openpilot/tree/master/tools/webcam).\n\nSupported Cars\n------\n\n| Make      | Model (US Market Reference)   | Supported Package | ACC              | No ACC accel below | No ALC below      |\n| ----------| ------------------------------| ------------------| -----------------| -------------------| ------------------|\n| Acura     | ILX 2016-19                   | AcuraWatch Plus   | openpilot        | 25mph<sup>1</sup>  | 25mph             |\n| Acura     | RDX 2016-18                   | AcuraWatch Plus   | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Acura     | RDX 2019-21                   | All               | Stock            | 0mph               | 3mph              |\n| Honda     | Accord 2018-20                | All               | Stock            | 0mph               | 3mph              |\n| Honda     | Accord Hybrid 2018-20         | All               | Stock            | 0mph               | 3mph              |\n| Honda     | Civic Hatchback 2017-21       | Honda Sensing     | Stock            | 0mph               | 12mph             |\n| Honda     | Civic Coupe 2016-18           | Honda Sensing     | openpilot        | 0mph               | 12mph             |\n| Honda     | Civic Coupe 2019-20           | All               | Stock            | 0mph               | 2mph<sup>2</sup>  |\n| Honda     | Civic Sedan 2016-18           | Honda Sensing     | openpilot        | 0mph               | 12mph             |\n| Honda     | Civic Sedan 2019-20           | All               | Stock            | 0mph               | 2mph<sup>2</sup>  |\n| Honda     | CR-V 2015-16                  | Touring           | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Honda     | CR-V 2017-21                  | Honda Sensing     | Stock            | 0mph               | 12mph             |\n| Honda     | CR-V Hybrid 2017-2019         | Honda Sensing     | Stock            | 0mph               | 12mph             |\n| Honda     | e 2020                        | All \t\t          | Stock            | 0mph               | 3mph              |\n| Honda     | Fit 2018-19                   | Honda Sensing     | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Honda     | HR-V 2019-20                  | Honda Sensing     | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Honda     | Insight 2019-21               | All               | Stock            | 0mph               | 3mph              |\n| Honda     | Inspire 2018                  | All               | Stock            | 0mph               | 3mph              |\n| Honda     | Odyssey 2018-20               | Honda Sensing     | openpilot        | 25mph<sup>1</sup>  | 0mph              |\n| Honda     | Passport 2019                 | All               | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Honda     | Pilot 2016-19                 | Honda Sensing     | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Honda     | Ridgeline 2017-21             | Honda Sensing     | openpilot        | 25mph<sup>1</sup>  | 12mph             |\n| Hyundai   | Palisade 2020-21              | All               | Stock            | 0mph               | 0mph              |\n| Hyundai   | Sonata 2020-21                | All               | Stock            | 0mph               | 0mph              |\n| Lexus     | CT Hybrid 2017-18             | LSS               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Lexus     | ES 2019-21                    | All               | openpilot        | 0mph               | 0mph              |\n| Lexus     | ES Hybrid 2017-18             | LSS               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Lexus     | ES Hybrid 2019-21             | All               | openpilot        | 0mph               | 0mph              |\n| Lexus     | IS 2017-2019                  | All               | Stock            | 22mph              | 0mph              |\n| Lexus     | NX 2018                       | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Lexus     | NX 2020                       | All               | openpilot        | 0mph               | 0mph              |\n| Lexus     | NX Hybrid 2018-19             | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Lexus     | RX 2016-18                    | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Lexus     | RX 2020-21                    | All               | openpilot        | 0mph               | 0mph              |\n| Lexus     | RX Hybrid 2016-19             | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Lexus     | RX Hybrid 2020-21             | All               | openpilot        | 0mph               | 0mph              |\n| Lexus     | UX Hybrid 2019-21             | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Alphard 2020                  | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Avalon 2016-21                | TSS-P             | Stock<sup>3</sup>| 20mph<sup>1</sup>  | 0mph              |\n| Toyota    | Avalon Hybrid 2019-21         | TSS-P             | Stock<sup>3</sup>| 20mph<sup>1</sup>  | 0mph              |\n| Toyota    | Camry 2018-20                 | All               | Stock            | 0mph<sup>4</sup>   | 0mph              |\n| Toyota    | Camry 2021                    | All               | openpilot        | 0mph<sup>4</sup>   | 0mph              |\n| Toyota    | Camry Hybrid 2018-20          | All               | Stock            | 0mph<sup>4</sup>   | 0mph              |\n| Toyota    | Camry Hybrid 2021             | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | C-HR 2017-20                  | All               | Stock            | 0mph               | 0mph              |\n| Toyota    | C-HR Hybrid 2017-19           | All               | Stock            | 0mph               | 0mph              |\n| Toyota    | Corolla 2017-19               | All               | Stock<sup>3</sup>| 20mph<sup>1</sup>  | 0mph              |\n| Toyota    | Corolla 2020-22               | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Corolla Hatchback 2019-21     | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Corolla Hybrid 2020-21        | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Highlander 2017-19            | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Toyota    | Highlander 2020-21            | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Highlander Hybrid 2017-19     | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Toyota    | Highlander Hybrid 2020-21     | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Mirai 2021\t                  | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Prius 2016-20                 | TSS-P             | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Toyota    | Prius 2021                    | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Prius Prime 2017-20           | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Toyota    | Prius Prime 2021              | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Rav4 2016-18                  | TSS-P             | Stock<sup>3</sup>| 20mph<sup>1</sup>  | 0mph              |\n| Toyota    | Rav4 2019-21                  | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Rav4 Hybrid 2016-18           | TSS-P             | Stock<sup>3</sup>| 0mph               | 0mph              |\n| Toyota    | Rav4 Hybrid 2019-21           | All               | openpilot        | 0mph               | 0mph              |\n| Toyota    | Sienna 2018-20                | All               | Stock<sup>3</sup>| 0mph               | 0mph              |\n\n<sup>1</sup>[Comma Pedal](https://github.com/commaai/openpilot/wiki/comma-pedal) is used to provide stop-and-go capability to some of the openpilot-supported cars that don't currently support stop-and-go. ***NOTE: The Comma Pedal is not officially supported by [comma](https://comma.ai).*** <br />\n<sup>2</sup>2019 Honda Civic 1.6L Diesel Sedan does not have ALC below 12mph. <br />\n<sup>3</sup>When disconnecting the Driver Support Unit (DSU), openpilot ACC will replace stock ACC. ***NOTE: disconnecting the DSU disables Automatic Emergency Braking (AEB).*** <br />\n<sup>4</sup>28mph for Camry 4CYL L, 4CYL LE and 4CYL SE which don't have Full-Speed Range Dynamic Radar Cruise Control. <br />\n\nCommunity Maintained Cars and Features\n------\n\n| Make      | Model (US Market Reference)   | Supported Package | ACC              | No ACC accel below | No ALC below |\n| ----------| ------------------------------| ------------------| -----------------| -------------------| -------------|\n| Audi      | A3 2014-19                    | Prestige          | Stock            | 0mph               | 0mph         |\n| Audi      | A3 Sportback e-tron 2017-18   | Prestige          | Stock            | 0mph               | 0mph         |\n| Audi      | Q2 2018                       | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Buick     | Regal 2018<sup>1</sup>        | Adaptive Cruise   | openpilot        | 0mph               | 7mph         |\n| Cadillac  | ATS 2018<sup>1</sup>          | Adaptive Cruise   | openpilot        | 0mph               | 7mph         |\n| Chevrolet | Malibu 2017<sup>1</sup>       | Adaptive Cruise   | openpilot        | 0mph               | 7mph         |\n| Chevrolet | Volt 2017-18<sup>1</sup>      | Adaptive Cruise   | openpilot        | 0mph               | 7mph         |\n| Chrysler  | Pacifica 2017-18              | Adaptive Cruise   | Stock            | 0mph               | 9mph         |\n| Chrysler  | Pacifica 2020                 | Adaptive Cruise   | Stock            | 0mph               | 39mph        |\n| Chrysler  | Pacifica Hybrid 2017-18       | Adaptive Cruise   | Stock            | 0mph               | 9mph         |\n| Chrysler  | Pacifica Hybrid 2019-21       | Adaptive Cruise   | Stock            | 0mph               | 39mph        |\n| Genesis   | G70 2018                      | All               | Stock            | 0mph               | 0mph         |\n| Genesis   | G80 2018                      | All               | Stock            | 0mph               | 0mph         |\n| Genesis   | G90 2018                      | All               | Stock            | 0mph               | 0mph         |\n| GMC       | Acadia 2018<sup>1</sup>       | Adaptive Cruise   | openpilot        | 0mph               | 7mph         |\n| Holden    | Astra 2017<sup>1</sup>        | Adaptive Cruise   | openpilot        | 0mph               | 7mph         |\n| Hyundai   | Elantra 2017-19               | SCC + LKAS        | Stock            | 19mph              | 34mph        |\n| Hyundai   | Elantra 2021                  | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Elantra Hybrid 2021           | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Genesis 2015-16               | SCC + LKAS        | Stock            | 19mph              | 37mph        |\n| Hyundai   | Ioniq Electric 2019           | SCC + LKAS        | Stock            | 0mph               | 32mph        |\n| Hyundai   | Ioniq Electric 2020           | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Ioniq PHEV 2020               | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Kona 2020                     | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Kona EV 2018-19               | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Kona Hybrid 2020              | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Santa Fe 2019-20              | All               | Stock            | 0mph               | 0mph         |\n| Hyundai   | Sonata 2018-2019              | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Hyundai   | Sonata Hybrid 2021            | All               | Stock            | 0mph               | 0mph         |\n| Hyundai   | Veloster 2019-20              | SCC + LKAS        | Stock            | 5mph               | 0mph         |\n| Jeep      | Grand Cherokee 2016-18        | Adaptive Cruise   | Stock            | 0mph               | 9mph         |\n| Jeep      | Grand Cherokee 2019-20        | Adaptive Cruise   | Stock            | 0mph               | 39mph        |\n| Kia       | Forte 2018-21                 | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Niro EV 2019-21               | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Niro Hybrid 2021              | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Niro PHEV 2019                | SCC + LKAS        | Stock            | 10mph              | 32mph        |\n| Kia       | Optima 2017                   | SCC + LKAS        | Stock            | 0mph               | 32mph        |\n| Kia       | Optima 2019                   | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Seltos 2021                   | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Sorento 2018-19               | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Stinger 2018                  | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Ceed 2019                     | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Kia       | Telluride 2020                | SCC + LKAS        | Stock            | 0mph               | 0mph         |\n| Nissan    | Altima 2019-20                | ProPILOT          | Stock            | 0mph               | 0mph         |\n| Nissan    | Leaf 2018-20                  | ProPILOT          | Stock            | 0mph               | 0mph         |\n| Nissan    | Rogue 2018-20                 | ProPILOT          | Stock            | 0mph               | 0mph         |\n| Nissan    | X-Trail 2017                  | ProPILOT          | Stock            | 0mph               | 0mph         |\n| SEAT      | Ateca 2018                    | Driver Assistance | Stock            | 0mph               | 0mph         |\n| SEAT      | Leon 2014-2020                | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Škoda     | Kodiaq 2018-19                | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Škoda     | Octavia 2015, 2018-19         | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Škoda     | Octavia RS 2016               | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Škoda     | Scala 2020                    | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Škoda     | Superb 2015-18                | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Subaru    | Ascent 2019                   | EyeSight          | Stock            | 0mph               | 0mph         |\n| Subaru    | Crosstrek 2018-19             | EyeSight          | Stock            | 0mph               | 0mph         |\n| Subaru    | Forester 2019-21              | EyeSight          | Stock            | 0mph               | 0mph         |\n| Subaru    | Impreza 2017-19               | EyeSight          | Stock            | 0mph               | 0mph         |\n| Volkswagen| Atlas 2018-19                 | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| e-Golf 2014, 2019-20          | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf 2015-20                  | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf Alltrack 2017-18         | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf GTE 2016                 | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf GTI 2018-20              | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf R 2016-19                | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf SportsVan 2016           | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Golf SportWagen 2015          | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Jetta 2018-20                 | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Jetta GLI 2021                | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Passat 2016-17<sup>2</sup>    | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| T-Cross 2021                  | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Tiguan 2020                   | Driver Assistance | Stock            | 0mph               | 0mph         |\n| Volkswagen| Touran 2017                   | Driver Assistance | Stock            | 0mph               | 0mph         |\n\n<sup>1</sup>Requires an [OBD-II car harness](https://comma.ai/shop/products/comma-car-harness) and [community built ASCM harness](https://github.com/commaai/openpilot/wiki/GM#hardware). ***NOTE: disconnecting the ASCM disables Automatic Emergency Braking (AEB).*** <br />\n<sup>2</sup>Only includes the MQB Passat sold outside of North America. The NMS Passat made in Chattanooga TN is not yet supported.\n\nCommunity Maintained Cars and Features are not verified by comma to meet our [safety model](SAFETY.md). Be extra cautious using them. They are only available after enabling the toggle in `Settings->Developer->Enable Community Features`.\n\nTo promote a car from community maintained, it must meet a few requirements. We must own one from the brand, we must sell the harness for it, has full ISO26262 in both panda and openpilot, there must be a path forward for longitudinal control, it must have AEB still enabled, and it must support fingerprinting 2.0\n\nAlthough they're not upstream, the community has openpilot running on other makes and models. See the 'Community Supported Models' section of each make [on our wiki](https://wiki.comma.ai/).\n\nInstallation Instructions\n------\n\nInstall openpilot on a supported device by entering ``https://openpilot.comma.ai`` during the installer setup.\n\nFollow these [video instructions](https://youtu.be/lcjqxCymins) to properly mount the device on the windshield. Note: openpilot features an automatic pose calibration routine and openpilot performance should not be affected by small pitch and yaw misalignments caused by imprecise device mounting.\n\nBefore placing the device on your windshield, check the state and local laws and ordinances where you drive. Some state laws prohibit or restrict the placement of objects on the windshield of a motor vehicle.\n\nYou will be able to engage openpilot after reviewing the onboarding screens and finishing the calibration procedure.\n\nLimitations of openpilot ALC and LDW\n------\n\nopenpilot ALC and openpilot LDW do not automatically drive the vehicle or reduce the amount of attention that must be paid to operate your vehicle. The driver must always keep control of the steering wheel and be ready to correct the openpilot ALC action at all times.\n\nWhile changing lanes, openpilot is not capable of looking next to you or checking your blind spot. Only nudge the wheel to initiate a lane change after you have confirmed it's safe to do so.\n\nMany factors can impact the performance of openpilot ALC and openpilot LDW, causing them to be unable to function as intended. These include, but are not limited to:\n\n* Poor visibility (heavy rain, snow, fog, etc.) or weather conditions that may interfere with sensor operation.\n* The road facing camera is obstructed, covered or damaged by mud, ice, snow, etc.\n* Obstruction caused by applying excessive paint or adhesive products (such as wraps, stickers, rubber coating, etc.) onto the vehicle.\n* The device is mounted incorrectly.\n* When in sharp curves, like on-off ramps, intersections etc...; openpilot is designed to be limited in the amount of steering torque it can produce.\n* In the presence of restricted lanes or construction zones.\n* When driving on highly banked roads or in presence of strong cross-wind.\n* Extremely hot or cold temperatures.\n* Bright light (due to oncoming headlights, direct sunlight, etc.).\n* Driving on hills, narrow, or winding roads.\n\nThe list above does not represent an exhaustive list of situations that may interfere with proper operation of openpilot components. It is the driver's responsibility to be in control of the vehicle at all times.\n\nLimitations of openpilot ACC and FCW\n------\n\nopenpilot ACC and openpilot FCW are not systems that allow careless or inattentive driving. It is still necessary for the driver to pay close attention to the vehicle’s surroundings and to be ready to re-take control of the gas and the brake at all times.\n\nMany factors can impact the performance of openpilot ACC and openpilot FCW, causing them to be unable to function as intended. These include, but are not limited to:\n\n* Poor visibility (heavy rain, snow, fog, etc.) or weather conditions that may interfere with sensor operation.\n* The road facing camera or radar are obstructed, covered, or damaged by mud, ice, snow, etc.\n* Obstruction caused by applying excessive paint or adhesive products (such as wraps, stickers, rubber coating, etc.) onto the vehicle.\n* The device is mounted incorrectly.\n* Approaching a toll booth, a bridge or a large metal plate.\n* When driving on roads with pedestrians, cyclists, etc...\n* In presence of traffic signs or stop lights, which are not detected by openpilot at this time.\n* When the posted speed limit is below the user selected set speed. openpilot does not detect speed limits at this time.\n* In presence of vehicles in the same lane that are not moving.\n* When abrupt braking maneuvers are required. openpilot is designed to be limited in the amount of deceleration and acceleration that it can produce.\n* When surrounding vehicles perform close cut-ins from neighbor lanes.\n* Driving on hills, narrow, or winding roads.\n* Extremely hot or cold temperatures.\n* Bright light (due to oncoming headlights, direct sunlight, etc.).\n* Interference from other equipment that generates radar waves.\n\nThe list above does not represent an exhaustive list of situations that may interfere with proper operation of openpilot components. It is the driver's responsibility to be in control of the vehicle at all times.\n\nLimitations of openpilot DM\n------\n\nopenpilot DM should not be considered an exact measurement of the alertness of the driver.\n\nMany factors can impact the performance of openpilot DM, causing it to be unable to function as intended. These include, but are not limited to:\n\n* Low light conditions, such as driving at night or in dark tunnels.\n* Bright light (due to oncoming headlights, direct sunlight, etc.).\n* The driver's face is partially or completely outside field of view of the driver facing camera.\n* The driver facing camera is obstructed, covered, or damaged.\n\nThe list above does not represent an exhaustive list of situations that may interfere with proper operation of openpilot components. A driver should not rely on openpilot DM to assess their level of attention.\n\nUser Data and comma Account\n------\n\nBy default, openpilot uploads the driving data to our servers. You can also access your data by pairing with the comma connect app ([iOS](https://apps.apple.com/us/app/comma-connect/id1456551889), [Android](https://play.google.com/store/apps/details?id=ai.comma.connect&hl=en_US)). We use your data to train better models and improve openpilot for everyone.\n\nopenpilot is open source software: the user is free to disable data collection if they wish to do so.\n\nopenpilot logs the road facing camera, CAN, GPS, IMU, magnetometer, thermal sensors, crashes, and operating system logs.\nThe driver facing camera is only logged if you explicitly opt-in in settings. The microphone is not recorded.\n\nBy using openpilot, you agree to [our Privacy Policy](https://connect.comma.ai/privacy). You understand that use of this software or its related services will generate certain types of user data, which may be logged and stored at the sole discretion of comma. By accepting this agreement, you grant an irrevocable, perpetual, worldwide right to comma for the use of this data.\n\nSafety and Testing\n----\n\n* openpilot observes ISO26262 guidelines, see [SAFETY.md](SAFETY.md) for more details.\n* openpilot has software in the loop [tests](.github/workflows/selfdrive_tests.yaml) that run on every commit.\n* The safety model code lives in panda and is written in C, see [code rigor](https://github.com/commaai/panda#code-rigor) for more details.\n* panda has software in the loop [safety tests](https://github.com/commaai/panda/tree/master/tests/safety).\n* Internally, we have a hardware in the loop Jenkins test suite that builds and unit tests the various processes.\n* panda has additional hardware in the loop [tests](https://github.com/commaai/panda/blob/master/Jenkinsfile).\n* We run the latest openpilot in a testing closet containing 10 comma devices continuously replaying routes.\n\nTesting on PC\n------\nFor simplified development and experimentation, openpilot can be run in the CARLA driving simulator, which allows you to develop openpilot without a car. The whole setup should only take a few minutes.\n\nSteps:\n1) Start the CARLA server on first terminal\n```\nbash -c \"$(curl https://raw.githubusercontent.com/commaai/openpilot/master/tools/sim/start_carla.sh)\"\n```\n2) Start openpilot on second terminal\n```\nbash -c \"$(curl https://raw.githubusercontent.com/commaai/openpilot/master/tools/sim/start_openpilot_docker.sh)\"\n```\n3) Press 1 to engage openpilot\n\nSee the full [README](tools/sim/README.md)\n\nYou should also take a look at the tools directory in master: lots of tools you can use to replay driving data, test, and develop openpilot from your PC.\n\n\nCommunity and Contributing\n------\n\nopenpilot is developed by [comma](https://comma.ai/) and by users like you. We welcome both pull requests and issues on [GitHub](http://github.com/commaai/openpilot). Bug fixes and new car ports are encouraged.\n\nYou can add support for your car by following guides we have written for [Brand](https://blog.comma.ai/how-to-write-a-car-port-for-openpilot/) and [Model](https://blog.comma.ai/openpilot-port-guide-for-toyota-models/) ports. Generally, a car with adaptive cruise control and lane keep assist is a good candidate. [Join our Discord](https://discord.comma.ai) to discuss car ports: most car makes have a dedicated channel.\n\nWant to get paid to work on openpilot? [comma is hiring](https://comma.ai/jobs/).\n\nAnd [follow us on Twitter](https://twitter.com/comma_ai).\n\nDirectory Structure\n------\n    .\n    ├── cereal              # The messaging spec and libs used for all logs\n    ├── common              # Library like functionality we've developed here\n    ├── installer/updater   # Manages updates of NEOS\n    ├── opendbc             # Files showing how to interpret data from cars\n    ├── panda               # Code used to communicate on CAN\n    ├── phonelibs           # External libraries\n    ├── pyextra             # Extra python packages not shipped in NEOS\n    └── selfdrive           # Code needed to drive the car\n        ├── assets          # Fonts, images, and sounds for UI\n        ├── athena          # Allows communication with the app\n        ├── boardd          # Daemon to talk to the board\n        ├── camerad         # Driver to capture images from the camera sensors\n        ├── car             # Car specific code to read states and control actuators\n        ├── common          # Shared C/C++ code for the daemons\n        ├── controls        # Planning and controls\n        ├── debug           # Tools to help you debug and do car ports\n        ├── locationd       # Precise localization and vehicle parameter estimation\n        ├── logcatd         # Android logcat as a service\n        ├── loggerd         # Logger and uploader of car data\n        ├── modeld          # Driving and monitoring model runners\n        ├── proclogd        # Logs information from proc\n        ├── sensord         # IMU interface code\n        ├── test            # Unit tests, system tests, and a car simulator\n        └── ui              # The UI\n\nLicensing\n------\n\nopenpilot is released under the MIT license. Some parts of the software are released under other licenses as specified.\n\nAny user of this software shall indemnify and hold harmless comma.ai, Inc. and its directors, officers, employees, agents, stockholders, affiliates, subcontractors and customers from and against all allegations, claims, actions, suits, demands, damages, liabilities, obligations, losses, settlements, judgments, costs and expenses (including without limitation attorneys’ fees and costs) which arise out of, relate to or result from any use of this software by user.\n\n**THIS IS ALPHA QUALITY SOFTWARE FOR RESEARCH PURPOSES ONLY. THIS IS NOT A PRODUCT.\nYOU ARE RESPONSIBLE FOR COMPLYING WITH LOCAL LAWS AND REGULATIONS.\nNO WARRANTY EXPRESSED OR IMPLIED.**\n\n---\n\n<img src=\"https://d1qb2nb5cznatu.cloudfront.net/startups/i/1061157-bc7e9bf3b246ece7322e6ffe653f6af8-medium_jpg.jpg?buster=1458363130\" width=\"75\"></img> <img src=\"https://cdn-images-1.medium.com/max/1600/1*C87EjxGeMPrkTuVRVWVg4w.png\" width=\"225\"></img>\n\n[![openpilot tests](https://github.com/commaai/openpilot/workflows/openpilot%20tests/badge.svg?event=push)](https://github.com/commaai/openpilot/actions)\n[![Total alerts](https://img.shields.io/lgtm/alerts/g/commaai/openpilot.svg?logo=lgtm&logoWidth=18)](https://lgtm.com/projects/g/commaai/openpilot/alerts/)\n[![Language grade: Python](https://img.shields.io/lgtm/grade/python/g/commaai/openpilot.svg?logo=lgtm&logoWidth=18)](https://lgtm.com/projects/g/commaai/openpilot/context:python)\n[![Language grade: C/C++](https://img.shields.io/lgtm/grade/cpp/g/commaai/openpilot.svg?logo=lgtm&logoWidth=18)](https://lgtm.com/projects/g/commaai/openpilot/context:cpp)\n[![codecov](https://codecov.io/gh/commaai/openpilot/branch/master/graph/badge.svg)](https://codecov.io/gh/commaai/openpilot)\n"
  },
  {
    "path": "README.md",
    "content": "Licensing\n------\nxnxpilot is released under the MIT license. Some parts of the software are released under other licenses as specified.\n\nAny user of this software shall indemnify and hold harmless Rick Lan, dragonpilot, comma.ai, Inc. and its directors, officers, employees, agents, stockholders, affiliates, subcontractors and customers from and against all allegations, claims, actions, suits, demands, damages, liabilities, obligations, losses, settlements, judgments, costs and expenses (including without limitation attorneys’ fees and costs) which arise out of, relate to or result from any use of this software by user.\n\n***THIS IS ALPHA QUALITY SOFTWARE FOR RESEARCH PURPOSES ONLY. THIS IS NOT A PRODUCT. YOU ARE RESPONSIBLE FOR COMPLYING WITH LOCAL LAWS AND REGULATIONS. NO WARRANTY EXPRESSED OR IMPLIED.***\n\n---\n\nTable of Contents\n------\n\n* [What is xnxpilot?](#what-is-xnxpilot)\n* [Showcase](#showcase)\n* [Checklist](#checklist)\n* [Hardware requirement](#hardware-requirement)\n* [Software requirement](#software-requirement)\n* [Hardware assimbly](#hardware-assembly)\n* [Installation](#installation)\n* [Credits](#credits)\n* [Notes](#notes)\n\n---\n\nWhat is xnxpilot?\n------\nxnxpilot (Xavier NX Pilot) is an open source driver assistance system based on [dragonpilot](http://github.com/dragonpilot-community/dragonpilot) and [openpilot](http://github.com/commaai/openpilot), running on a NVIDIA Jetson Xavier NX platform instead of a qualcomm 821 mobile phone.\n\n\n\nIf you would like to run it with minimal changes to openpilot, please see the example in \"doc\" branch, based on openpilot 0.8.4 \n\n---\n\nShowcase\n------\nSimulation:\n<table>\n  <tr>\n    <td><a href=\"https://youtu.be/ubxSSLWqyt8\" title=\"YouTube\" rel=\"noopener\"><img src=\"http://i3.ytimg.com/vi/ubxSSLWqyt8/hqdefault.jpg\"></a></td>\n  </tr>\n</table>\n\nOn road:\n<table>\n  <tr>\n    <td><a href=\"https://youtu.be/RqoTT5m4Kp8\" title=\"YouTube\" rel=\"noopener\"><img src=\"http://i3.ytimg.com/vi/RqoTT5m4Kp8/hqdefault.jpg\"></a></td>\n  </tr>\n</table>\n\nRunning on dragonpilot 0.8:\n<table>\n  <tr>\n    <td><a href=\"https://youtu.be/o2pm8bAJvAM\" title=\"YouTube\" rel=\"noopener\"><img src=\"http://i3.ytimg.com/vi/o2pm8bAJvAM/hqdefault.jpg\"></a></td>\n    <td><a href=\"https://youtu.be/GEr-K3D3sDU\" title=\"YouTube\" rel=\"noopener\"><img src=\"http://i3.ytimg.com/vi/GEr-K3D3sDU/hqdefault.jpg\"></a></td>\n  </tr>\n</table>\n\n---\n\nChecklist\n------\n- [x] Create build scripts\n- [x] Add patch samples / tutorials.\n- [x] On road lateral control tests.\n- [ ] On road longitudinal control tests.\n- [ ] Add IMU sensor to improve GPS accuracy.\n- [ ] Tuning. (WIP)\n\n---\n\nHardware Requirement\n------\n- [Nvidia Jetson Xavier NX](https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-xavier-nx/)\n- 32GB+ microsd card (UHS 3 speed minimum)\n- [Arducam IMX 477](https://www.amazon.com/gp/product/B08F743RGG/)\n- [comma.ai Black Panda](https://comma.ai/shop/products/panda) (or white/grey panda but require more code customization.)\n- (Optional) [comma.ai Windshield mount](https://github.com/commaai/neo/tree/master/case/eon)\n- (Optional) [GoPro flat adhesive mount](https://www.amazon.com/AFAITH-Adhesive-Mounts-GoPro-Camera/dp/B00BUD6LPY/)\n- (Optional) [Waveshare 4.3\" IPS Touchscreen](https://www.amazon.com.au/gp/product/B0852NW9FM/)\n- (Optional) [DCDZ Jetson Xavier NX Carrier Board NCB00](https://item.taobao.com/item.htm?ft=t&id=613984388047)\n- (Optional) [CSI to HDMI Extension Module](https://www.amazon.com/gp/product/B06XDNBM63/)\n- (Optional) Targus notebook charger for car.\n---\n\nSoftware Requirement\n------\n- [NVIDIA JetPack 4.6](https://developer.nvidia.com/jetpack-sdk-46)\n\n---\n\nHardware assembly\n------\nIt is important to know that your camera needs **firmly attached** onto your windshield, any small movement to the camera while driving may result dangerous steering/acceleration.\n\nI highly recommended to 3D print those commaai windshield mount (use with gopro mount) and use it to mount your camera, 24 degree one will do the job.\n\n---\n\nInstallation\n------\n1) [Install ubuntu 18.04 / Jetpack 4.6 on to sdcard](https://developer.nvidia.com/embedded/learn/get-started-jetson-xavier-nx-devkit)\n2) Insert your sd card to your jetson, have camera connect to CAM0, boot up, use the following configuration (installer will use those values to set up the device):\n  - username: **comma**\n  - password: **comma**\n  - hostname: **tici**\n  - mode: **20W 6 cores**\n\n3) Once installation finished, **SSH into the device** and continue the rest of the processes.\n4) run:\n  - `sudo /opt/nvidia/jetson-io/jetson-io.py`\n  - select `Configure Jetson Nano CSI Connector` > `Configure for compatible hardware` > `Camera IMX477 Dual` > `Save pin changes` > `Save and exit without rebooting`.\n\n5) clone this repo to your home directory (e.g. `cd ~/ && git clone https://github.com/efinilan/xnxpilot.git openpilot -b 0.8.9 --single-branch`)\n6) run `cd ~/openpilot/jetson/ && sudo bash env_installer.py`\n7) Take a rest, this will take around **1.5 hrs** to config your system and another **10 mins** to compile dragonpilot, depends on your internet connection.\n8) Congradulations, you have dragonpilot running on your jetson. \n---\n\nCredits\n------\n- [Commaai Openpilot](https://github.com/commaai/openpiplot)\n- [dragonpilot community](https://github.com/dragonpilot-community/dragonpilot/)\n- [RetroPilot Community](https://discord.gg/fGUuASVZKg)\n- [Unofficial OpenPilot Community](https://discord.gg/Mrf8FwfWSr)\n\n---\n\nNotes\n------\n#### set_core_affinity ####\nJetson Xavier NX has 6 cores running at 1.9 GHz, here is what I've defined:\n\n0 = camerad\n\n1 = modeld\n\n2 = boardd\n\n3 = controlsd\n\n4 = plannerd / radard\n\nThis will spread processes other CPU cores.\n"
  },
  {
    "path": "RELEASES.md",
    "content": "Version 0.8.9 (2021-09-14)\n========================\n * Improved fan control on comma three\n * AGNOS 1.5: improved stability\n * Honda e 2020 support\n\nVersion 0.8.8 (2021-08-27)\n========================\n * New driving model with improved laneless performance\n   * Trained on 5000+ hours of diverse driving data from 3000+ users in 40+ countries\n   * Better anti-cheating methods during simulator training ensure the model hugs less when in laneless mode\n   * All new desire ground-truthing stack makes the model better at lane changes\n * New driver monitoring model: improved performance on comma three\n * NEOS 18 for comma two: update packages\n * AGNOS 1.3 for comma three: fix display init at high temperatures\n * Improved auto-exposure on comma three\n * Improved longitudinal control on Honda Nidec cars\n * Hyundai Kona Hybrid 2020 support thanks to haram-KONA!\n * Hyundai Sonata Hybrid 2021 support thanks to Matt-Wash-Burn!\n * Kia Niro Hybrid 2021 support thanks to tetious!\n\nVersion 0.8.7 (2021-07-31)\n========================\n * comma three support!\n * Navigation alpha for the comma three!\n * Volkswagen T-Cross 2021 support thanks to jyoung8607!\n\nVersion 0.8.6 (2021-07-21)\n========================\n * Revamp lateral and longitudinal planners\n   * Refactor planner output API to be more readable and verbose\n   * Planners now output desired trajectories for speed, acceleration, curvature, and curvature rate\n   * Use MPC for longitudinal planning when no lead car is present, makes accel and decel smoother\n * Remove \"CHECK DRIVER FACE VISIBILITY\" warning\n * Fixed cruise fault on some TSS2.5 Camrys and international Toyotas\n * Hyundai Elantra Hybrid 2021 support thanks to tecandrew!\n * Hyundai Ioniq PHEV 2020 support thanks to YawWashout!\n * Kia Niro Hybrid 2019 support thanks to jyoung8607!\n * Škoda Octavia RS 2016 support thanks to jyoung8607!\n * Toyota Alphard 2020 support thanks to belm0!\n * Volkswagen Golf SportWagen 2015 support thanks to jona96!\n * Volkswagen Touran 2017 support thanks to jyoung8607!\n\nVersion 0.8.5 (2021-06-11)\n========================\n * NEOS update: improved reliability and stability with better voltage regulator configuration\n * Smart model-based Forward Collision Warning\n * CAN-based fingerprinting moved behind community features toggle\n * Improved longitudinal control on Toyotas with a comma pedal\n * Improved auto-brightness using road-facing camera\n * Added \"Software\" settings page with updater controls\n * Audi Q2 2018 support thanks to jyoung8607!\n * Hyundai Elantra 2021 support thanks to CruiseBrantley!\n * Lexus UX Hybrid 2019-2020 support thanks to brianhaugen2!\n * Toyota Avalon Hybrid 2019 support thanks to jbates9011!\n * SEAT Leon 2017 & 2020 support thanks to jyoung8607!\n * Škoda Octavia 2015 & 2019 support thanks to jyoung8607!\n\nVersion 0.8.4 (2021-05-17)\n========================\n * Delay controls start until system is ready\n * Fuzzy car identification, enabled with Community Features toggle\n * Localizer optimized for increased precision and less CPU usage\n * Retuned lateral control to be more aggressive when model is confident\n * Toyota Mirai 2021 support\n * Lexus NX 300 2020 support thanks to goesreallyfast!\n * Volkswagen Atlas 2018-19 support thanks to jyoung8607!\n\nVersion 0.8.3 (2021-04-01)\n========================\n * New model\n   * Trained on new diverse dataset from 2000+ users from 30+ countries\n   * Trained with improved segnet from the comma-pencil community project\n   * 🥬 Dramatically improved end-to-end lateral performance 🥬\n * Toggle added to disable the use of lanelines\n * NEOS update: update packages and support for new UI\n * New offroad UI based on Qt\n * Default SSH key only used for setup\n * Kia Ceed 2019 support thanks to ZanZaD13!\n * Kia Seltos 2021 support thanks to speedking456!\n * Added support for many Volkswagen and Škoda models thanks to jyoung8607!\n\nVersion 0.8.2 (2021-02-26)\n========================\n * Use model points directly in MPC (no more polyfits), making lateral planning more accurate\n * Use model heading prediction for smoother lateral control\n * Smarter actuator delay compensation\n * Improve qcamera resolution for improved video in explorer and connect\n * Adjust maximum engagement speed to better fit the model's training distribution\n * New driver monitoring model trained with 3x more diverse data\n * Improved face detection with masks\n * More predictable DM alerts when visibility is bad\n * Rewritten video streaming between openpilot processes\n * Improved longitudinal tuning on TSS2 Corolla and Rav4 thanks to briskspirit!\n * Audi A3 2015 and 2017 support thanks to keeleysam!\n * Nissan Altima 2020 support thanks to avolmensky!\n * Lexus ES Hybrid 2018 support thanks to TheInventorMan!\n * Toyota Camry Hybrid 2021 support thanks to alancyau!\n\nVersion 0.8.1 (2020-12-21)\n========================\n * Original EON is deprecated, upgrade to comma two\n * Better model performance in heavy rain\n * Better lane positioning in turns\n * Fixed bug where model would cut turns on empty roads at night\n * Fixed issue where some Toyotas would not completely stop thanks to briskspirit!\n * Toyota Camry 2021 with TSS2.5 support\n * Hyundai Ioniq Electric 2020 support thanks to baldwalker!\n\nVersion 0.8.0 (2020-11-30)\n========================\n * New driving model: fully 3D and improved cut-in detection\n * UI draws 2 road edges, 4 lanelines and paths in 3D\n * Major fixes to cut-in detection for openpilot longitudinal\n * Grey panda is no longer supported, upgrade to comma two or black panda\n * Lexus NX 2018 support thanks to matt12eagles!\n * Kia Niro EV 2020 support thanks to nickn17!\n * Toyota Prius 2021 support thanks to rav4kumar!\n * Improved lane positioning with uncertain lanelines, wide lanes and exits\n * Improved lateral control for Prius and Subaru\n\nVersion 0.7.10 (2020-10-29)\n========================\n * Grey panda is deprecated, upgrade to comma two or black panda\n * NEOS update: update to Python 3.8.2 and lower CPU frequency\n * Improved thermals due to reduced CPU frequency\n * Update SNPE to 1.41.0\n * Reduced offroad power consumption\n * Various system stability improvements\n * Acura RDX 2020 support thanks to csouers!\n\nVersion 0.7.9 (2020-10-09)\n========================\n * Improved car battery power management\n * Improved updater robustness\n * Improved realtime performance\n * Reduced UI and modeld lags\n * Increased torque on 2020 Hyundai Sonata and Palisade\n\nVersion 0.7.8 (2020-08-19)\n========================\n * New driver monitoring model: improved face detection and better compatibility with sunglasses\n * Download NEOS operating system updates in the background\n * Improved updater reliability and responsiveness\n * Hyundai Kona 2020, Veloster 2019, and Genesis G70 2018 support thanks to xps-genesis!\n\nVersion 0.7.7 (2020-07-20)\n========================\n * White panda is no longer supported, upgrade to comma two or black panda\n * Improved vehicle model estimation using high precision localizer\n * Improved thermal management on comma two\n * Improved autofocus for road-facing camera\n * Improved noise performance for driver-facing camera\n * Block lane change start using blindspot monitor on select Toyota, Hyundai, and Subaru\n * Fix GM ignition detection\n * Code cleanup and smaller release sizes\n * Hyundai Sonata 2020 promoted to officially supported car\n * Hyundai Ioniq Electric Limited 2019 and Ioniq SE 2020 support thanks to baldwalker!\n * Subaru Forester 2019 and Ascent 2019 support thanks to martinl!\n\nVersion 0.7.6.1 (2020-06-16)\n========================\n * Hotfix: update kernel on some comma twos (orders #8570-#8680)\n\nVersion 0.7.6 (2020-06-05)\n========================\n * White panda is deprecated, upgrade to comma two or black panda\n * 2017 Nissan X-Trail, 2018-19 Leaf and 2019 Rogue support thanks to avolmensky!\n * 2017 Mazda CX-5 support in dashcam mode thanks to Jafaral!\n * Huge CPU savings in modeld by using thneed!\n * Lots of code cleanup and refactors\n\nVersion 0.7.5 (2020-05-13)\n========================\n * Right-Hand Drive support for both driving and driver monitoring!\n * New driving model: improved at sharp turns and lead speed estimation\n * New driver monitoring model: overall improvement on comma two\n * Driver camera preview in settings to improve mounting position\n * Added support for many Hyundai, Kia, Genesis models thanks to xx979xx!\n * Improved lateral tuning for 2020 Toyota Rav 4 (hybrid)\n\nVersion 0.7.4 (2020-03-20)\n========================\n * New driving model: improved lane changes and lead car detection\n * Improved driver monitoring model: improve eye detection\n * Improved calibration stability\n * Improved lateral control on some 2019 and 2020 Toyota Prius\n * Improved lateral control on VW Golf: 20% more steering torque\n * Fixed bug where some 2017 and 2018 Toyota C-HR would use the wrong steering angle sensor\n * Support for Honda Insight thanks to theantihero!\n * Code cleanup in car abstraction layers and ui\n\nVersion 0.7.3 (2020-02-21)\n========================\n * Support for 2020 Highlander thanks to che220!\n * Support for 2018 Lexus NX 300h thanks to kengggg!\n * Speed up ECU firmware query\n * Fix bug where manager would sometimes hang after shutting down the car\n\nVersion 0.7.2 (2020-02-07)\n========================\n * ECU firmware version based fingerprinting for Honda & Toyota\n * New driving model: improved path prediction during turns and lane changes and better lead speed tracking\n * Improve driver monitoring under extreme lighting and add low accuracy alert\n * Support for 2019 Rav4 Hybrid thanks to illumiN8i!\n * Support for 2016, 2017 and 2020 Lexus RX thanks to illumiN8i!\n * Support for 2020 Chrysler Pacifica Hybrid thanks to adhintz!\n\nVersion 0.7.1 (2020-01-20)\n========================\n * comma two support!\n * Lane Change Assist above 45 mph!\n * Replace zmq with custom messaging library, msgq!\n * Supercombo model: calibration and driving models are combined for better lead estimate\n * More robust updater thanks to jyoung8607! Requires NEOS update\n * Improve low speed ACC tuning\n\nVersion 0.7 (2019-12-13)\n========================\n * Move to SCons build system!\n * Add Lane Departure Warning (LDW) for all supported vehicles!\n * NEOS update: increase wifi speed thanks to jyoung8607!\n * Adaptive driver monitoring based on scene\n * New driving model trained end-to-end: improve lane lines and lead detection\n * Smarter torque limit alerts for all cars\n * Improve GM longitudinal control: proper computations for 15Hz radar\n * Move GM port, Toyota with DSU removed, comma pedal in community features; toggle switch required\n * Remove upload over cellular toggle: only upload qlog and qcamera files if not on wifi\n * Refactor Panda code towards ISO26262 and SIL2 compliancy\n * Forward stock FCW for Honda Nidec\n * Volkswagen port now standard: comma Harness intercepts stock camera\n\nVersion 0.6.6 (2019-11-05)\n========================\n * Volkswagen support thanks to jyoung8607!\n * Toyota Corolla Hybrid with TSS 2.0 support thanks to u8511049!\n * Lexus ES with TSS 2.0 support thanks to energee!\n * Fix GM ignition detection and lock safety mode not required anymore\n * Log panda firmware and dongle ID thanks to martinl!\n * New driving model: improve path prediction and lead detection\n * New driver monitoring model, 4x smaller and running on DSP\n * Display an alert and don't start openpilot if panda has wrong firmware\n * Fix bug preventing EON from terminating processes after a drive\n * Remove support for Toyota giraffe without the 120Ohm resistor\n\nVersion 0.6.5 (2019-10-07)\n========================\n * NEOS update: upgrade to Python3 and new installer!\n * comma Harness support!\n * New driving model: improve path prediction\n * New driver monitoring model: more accurate face and eye detection\n * Redesign offroad screen to display updates and alerts\n * Increase maximum allowed acceleration\n * Prevent car 12V battery drain by cutting off EON charge after 3 days of no drive\n * Lexus CT Hybrid support thanks to thomaspich!\n * Louder chime for critical alerts\n * Add toggle to switch to dashcam mode\n * Fix \"invalid vehicle params\" error on DSU-less Toyota\n\nVersion 0.6.4 (2019-09-08)\n========================\n * Forward stock AEB for Honda Nidec\n * Improve lane centering on banked roads\n * Always-on forward collision warning\n * Always-on driver monitoring, except for right hand drive countries\n * Driver monitoring learns the user's normal driving position\n * Honda Fit support thanks to energee!\n * Lexus IS support\n\nVersion 0.6.3 (2019-08-12)\n========================\n * Alert sounds from EON: requires NEOS update\n * Improve driver monitoring: eye tracking and improved awareness logic\n * Improve path prediction with new driving model\n * Improve lane positioning with wide lanes and exits\n * Improve lateral control on RAV4\n * Slow down for turns using model\n * Open sourced regression test to verify outputs against reference logs\n * Open sourced regression test to sanity check all car models\n\nVersion 0.6.2 (2019-07-29)\n========================\n * New driving model!\n * Improve lane tracking with double lines\n * Strongly improve stationary vehicle detection\n * Strongly reduce cases of braking due to false leads\n * Better lead tracking around turns\n * Improve cut-in prediction by using neural network\n * Improve lateral control on Toyota Camry and C-HR thanks to zorrobyte!\n * Fix unintended openpilot disengagements on Jeep thanks to adhintz!\n * Fix delayed transition to offroad when car is turned off\n\nVersion 0.6.1 (2019-07-21)\n========================\n * Remote SSH with comma prime and [ssh.comma.ai](https://ssh.comma.ai)\n * Panda code Misra-c2012 compliance, tested against cppcheck coverage\n * Lockout openpilot after 3 terminal alerts for driver distracted or unresponsive\n * Toyota Sienna support thanks to wocsor!\n\nVersion 0.6 (2019-07-01)\n========================\n * New model, with double the pixels and ten times the temporal context!\n * Car should not take exits when in the right lane\n * openpilot uses only ~65% of the CPU (down from 75%)\n * Routes visible in connect/explorer after only 0.2% is uploaded (qlogs)\n * loggerd and sensord are open source, every line of openpilot is now open\n * Panda safety code is MISRA compliant and ships with a signed version on release2\n * New NEOS is 500MB smaller and has a reproducible usr/pipenv\n * Lexus ES Hybrid support thanks to wocsor!\n * Improve tuning for supported Toyota with TSS 2.0\n * Various other stability improvements\n\nVersion 0.5.13 (2019-05-31)\n==========================\n * Reduce panda power consumption by 70%, down to 80mW, when car is off (not for GM)\n * Reduce EON power consumption by 40%, down to 1100mW, when car is off\n * Reduce CPU utilization by 20% and improve stability\n * Temporarily remove mapd functionalities to improve stability\n * Add openpilot record-only mode for unsupported cars\n * Synchronize controlsd to boardd to reduce latency\n * Remove panda support for Subaru giraffe\n\nVersion 0.5.12 (2019-05-16)\n==========================\n * Improve lateral control for the Prius and Prius Prime\n * Compress logs before writing to disk\n * Remove old driving data when storage reaches 90% full\n * Fix small offset in following distance\n * Various small CPU optimizations\n * Improve offroad power consumption: require NEOS Update\n * Add default speed limits for Estonia thanks to martinl!\n * Subaru Crosstrek support thanks to martinl!\n * Toyota Avalon support thanks to njbrown09!\n * Toyota Rav4 with TSS 2.0 support thanks to wocsor!\n * Toyota Corolla with TSS 2.0 support thanks to wocsor!\n\nVersion 0.5.11 (2019-04-17)\n========================\n * Add support for Subaru\n * Reduce panda power consumption by 60% when car is off\n * Fix controlsd lag every 6 minutes. This would sometimes cause disengagements\n * Fix bug in controls with new angle-offset learner in MPC\n * Reduce cpu consumption of ubloxd by rewriting it in C++\n * Improve driver monitoring model and face detection\n * Improve performance of visiond and ui\n * Honda Passport 2019 support\n * Lexus RX Hybrid 2019 support thanks to schomems!\n * Improve road selection heuristic in mapd\n * Add Lane Departure Warning to dashboard for Toyota thanks to arne182\n\nVersion 0.5.10 (2019-03-19)\n========================\n * Self-tuning vehicle parameters: steering offset, tire stiffness and steering ratio\n * Improve longitudinal control at low speed when lead vehicle harshly decelerates\n * Fix panda bug going unexpectedly in DCP mode when EON is connected\n * Reduce white panda power consumption by 500mW when EON is disconnected by turning off WIFI\n * New Driver Monitoring Model\n * Support QR codes for login using comma connect\n * Refactor comma pedal FW and use CRC-8 checksum algorithm for safety. Reflashing pedal is required.\n   Please see `#hw-pedal` on [discord](discord.comma.ai) for assistance updating comma pedal.\n * Additional speed limit rules for Germany thanks to arne182\n * Allow negative speed limit offsets\n\nVersion 0.5.9 (2019-02-10)\n========================\n * Improve calibration using a dedicated neural network\n * Abstract planner in its own process to remove lags in controls process\n * Improve speed limits with country/region defaults by road type\n * Reduce mapd data usage with gzip thanks to eFiniLan\n * Zip log files in the background to reduce disk usage\n * Kia Optima support thanks to emmertex!\n * Buick Regal 2018 support thanks to HOYS!\n * Comma pedal support for Toyota thanks to wocsor! Note: tuning needed and not maintained by comma\n * Chrysler Pacifica and Jeep Grand Cherokee support thanks to adhintz!\n\nVersion 0.5.8 (2019-01-17)\n========================\n * Open sourced visiond\n * Auto-slowdown for upcoming turns\n * Chrysler/Jeep/Fiat support thanks to adhintz!\n * Honda Civic 2019 support thanks to csouers!\n * Improve use of car display in Toyota thanks to arne182!\n * No data upload when connected to Android or iOS hotspots and \"Enable Upload Over Cellular\" setting is off\n * EON stops charging when 12V battery drops below 11.8V\n\nVersion 0.5.7 (2018-12-06)\n========================\n * Speed limit from OpenStreetMap added to UI\n * Highlight speed limit when speed exceeds road speed limit plus a delta\n * Option to limit openpilot max speed to road speed limit plus a delta\n * Cadillac ATS support thanks to vntarasov!\n * GMC Acadia support thanks to CryptoKylan!\n * Decrease GPU power consumption\n * NEOSv8 autoupdate\n\nVersion 0.5.6 (2018-11-16)\n========================\n * Refresh settings layout and add feature descriptions\n * In Honda, keep stock camera on for logging and extra stock features; new openpilot giraffe setting is 0111!\n * In Toyota, option to keep stock camera on for logging and extra stock features (e.g. AHB); 120Ohm resistor required on giraffe.\n * Improve camera calibration stability\n * More tuning to Honda positive accelerations\n * Reduce brake pump use on Hondas\n * Chevrolet Malibu support thanks to tylergets!\n * Holden Astra support thanks to AlexHill!\n\nVersion 0.5.5 (2018-10-20)\n========================\n * Increase allowed Honda positive accelerations\n * Fix sporadic unexpected braking when passing semi-trucks in Toyota\n * Fix gear reading bug in Hyundai Elantra thanks to emmertex!\n\nVersion 0.5.4 (2018-09-25)\n========================\n * New Driving Model\n * New Driver Monitoring Model\n * Improve longitudinal mpc in mid-low speed braking\n * Honda Accord hybrid support thanks to energee!\n * Ship mpc binaries and sensibly reduce build time\n * Calibration more stable\n * More Hyundai and Kia cars supported thanks to emmertex!\n * Various GM Volt improvements thanks to vntarasov!\n\nVersion 0.5.3 (2018-09-03)\n========================\n * Hyundai Santa Fe support!\n * Honda Pilot 2019 support thanks to energee!\n * Toyota Highlander support thanks to daehahn!\n * Improve steering tuning for Honda Odyssey\n\nVersion 0.5.2 (2018-08-16)\n========================\n * New calibration: more accurate, a lot faster, open source!\n * Enable orbd\n * Add little endian support to CAN packer\n * Fix fingerprint for Honda Accord 1.5T\n * Improve driver monitoring model\n\nVersion 0.5.1 (2018-08-01)\n========================\n * Fix radar error on Civic sedan 2018\n * Improve thermal management logic\n * Alpha Toyota C-HR and Camry support!\n * Auto-switch Driver Monitoring to 3 min counter when inaccurate\n\nVersion 0.5 (2018-07-11)\n========================\n * Driver Monitoring (beta) option in settings!\n * Make visiond, loggerd and UI use less resources\n * 60 FPS UI\n * Better car parameters for most cars\n * New sidebar with stats\n * Remove Waze and Spotify to free up system resources\n * Remove rear view mirror option\n * Calibration 3x faster\n\nVersion 0.4.7.2 (2018-06-25)\n==========================\n * Fix loggerd lag issue\n * No longer prompt for updates\n * Mitigate right lane hugging for properly mounted EON (procedure on wiki)\n\nVersion 0.4.7.1 (2018-06-18)\n==========================\n * Fix Acura ILX steer faults\n * Fix bug in mock car\n\nVersion 0.4.7 (2018-06-15)\n==========================\n * New model!\n * GM Volt (and CT6 lateral) support!\n * Honda Bosch lateral support!\n * Improve actuator modeling to reduce lateral wobble\n * Minor refactor of car abstraction layer\n * Hack around orbd startup issue\n\nVersion 0.4.6 (2018-05-18)\n==========================\n * NEOSv6 required! Will autoupdate\n * Stability improvements\n * Fix all memory leaks\n * Update C++ compiler to clang6\n * Improve front camera exposure\n\nVersion 0.4.5 (2018-04-27)\n==========================\n * Release notes added to the update popup\n * Improve auto shut-off logic to disallow empty battery\n * Added onboarding instructions\n * Include orbd, the first piece of new calibration algorithm\n * Show remaining upload data instead of file numbers\n * Fix UI bugs\n * Fix memory leaks\n\nVersion 0.4.4 (2018-04-13)\n==========================\n * EON are flipped! Flip your EON's mount!\n * Alpha Honda Ridgeline support thanks to energee!\n * Support optional front camera recording\n * Upload over cellular toggle now applies to all files, not just video\n * Increase acceleration when closing lead gap\n * User now prompted for future updates\n * NEO no longer supported :(\n\nVersion 0.4.3.2 (2018-03-29)\n============================\n * Improve autofocus\n * Improve driving when only one lane line is detected\n * Added fingerprint for Toyota Corolla LE\n * Fixed Toyota Corolla steer error\n * Full-screen driving UI\n * Improved path drawing\n\nVersion 0.4.3.1 (2018-03-19)\n============================\n * Improve autofocus\n * Add check for MPC solution error\n * Make first distracted warning visual only\n\nVersion 0.4.3 (2018-03-13)\n==========================\n * Add HDR and autofocus\n * Update UI aesthetic\n * Grey panda works in Waze\n * Add alpha support for 2017 Honda Pilot\n * Slight increase in acceleration response from stop\n * Switch CAN sending to use CANPacker\n * Fix pulsing acceleration regression on Honda\n * Fix openpilot bugs when stock system is in use\n * Change starting logic for chffrplus to use battery voltage\n\nVersion 0.4.2 (2018-02-05)\n==========================\n * Add alpha support for 2017 Lexus RX Hybrid\n * Add alpha support for 2018 ACURA RDX\n * Updated fingerprint to include Toyota Rav4 SE and Prius Prime\n * Bugfixes for Acura ILX and Honda Odyssey\n\nVersion 0.4.1 (2018-01-30)\n==========================\n * Add alpha support for 2017 Toyota Corolla\n * Add alpha support for 2018 Honda Odyssey with Honda Sensing\n * Add alpha support for Grey Panda\n * Refactored car abstraction layer to make car ports easier\n * Increased steering torque limit on Honda CR-V by 30%\n\nVersion 0.4.0.2 (2018-01-18)\n==========================\n * Add focus adjustment slider\n * Minor bugfixes\n\nVersion 0.4.0.1 (2017-12-21)\n==========================\n * New UI to match chffrplus\n * Improved lateral control tuning to fix oscillations on Civic\n * Add alpha support for 2017 Toyota Rav4 Hybrid\n * Reduced CPU usage\n * Removed unnecessary utilization of fan at max speed\n * Minor bug fixes\n\nVersion 0.3.9 (2017-11-21)\n==========================\n * Add alpha support for 2017 Toyota Prius\n * Improved longitudinal control using model predictive control\n * Enable Forward Collision Warning\n * Acura ILX now maintains openpilot engaged at standstill when brakes are applied\n\nVersion 0.3.8.2 (2017-10-30)\n==========================\n * Add alpha support for 2017 Toyota RAV4\n * Smoother lateral control\n * Stay silent if stock system is connected through giraffe\n * Minor bug fixes\n\nVersion 0.3.7 (2017-09-30)\n==========================\n * Improved lateral control using model predictive control\n * Improved lane centering\n * Improved GPS\n * Reduced tendency of path deviation near right side exits\n * Enable engagement while the accelerator pedal is pressed\n * Enable engagement while the brake pedal is pressed, when stationary and with lead vehicle within 5m\n * Disable engagement when park brake or brake hold are active\n * Fixed sporadic longitudinal pulsing in Civic\n * Cleanups to vehicle interface\n\nVersion 0.3.6.1 (2017-08-15)\n============================\n * Mitigate low speed steering oscillations on some vehicles\n * Include board steering check for CR-V\n\nVersion 0.3.6 (2017-08-08)\n==========================\n * Fix alpha CR-V support\n * Improved GPS\n * Fix display of target speed not always matching HUD\n * Increased acceleration after stop\n * Mitigated some vehicles driving too close to the right line\n\nVersion 0.3.5 (2017-07-30)\n==========================\n * Fix bug where new devices would not begin calibration\n * Minor robustness improvements\n\nVersion 0.3.4 (2017-07-28)\n==========================\n * Improved model trained on more data\n * Much improved controls tuning\n * Performance improvements\n * Bugfixes and improvements to calibration\n * Driving log can play back video\n * Acura only: system now stays engaged below 25mph as long as brakes are applied\n\nVersion 0.3.3  (2017-06-28)\n===========================\n * Improved model trained on more data\n * Alpha CR-V support thanks to energee and johnnwvs!\n * Using the opendbc project for DBC files\n * Minor performance improvements\n * UI update thanks to pjlao307\n * Power off button\n * 6% more torque on the Civic\n\nVersion 0.3.2  (2017-05-22)\n===========================\n * Minor stability bugfixes\n * Added metrics and rear view mirror disable to settings\n * Update model with more crowdsourced data\n\nVersion 0.3.1  (2017-05-17)\n===========================\n * visiond stability bugfix\n * Add logging for angle and flashing\n\nVersion 0.3.0  (2017-05-12)\n===========================\n * Add CarParams struct to improve the abstraction layer\n * Refactor visiond IPC to support multiple clients\n * Add raw GPS and beginning support for navigation\n * Improve model in visiond using crowdsourced data\n * Add improved system logging to diagnose instability\n * Rewrite baseui in React Native\n * Moved calibration to the cloud\n\nVersion 0.2.9  (2017-03-01)\n===========================\n * Retain compatibility with NEOS v1\n\nVersion 0.2.8  (2017-02-27)\n===========================\n * Fix bug where frames were being dropped in minute 71\n\nVersion 0.2.7  (2017-02-08)\n===========================\n * Better performance and pictures at night\n * Fix ptr alignment issue in boardd\n * Fix brake error light, fix crash if too cold\n\nVersion 0.2.6  (2017-01-31)\n===========================\n * Fix bug in visiond model execution\n\nVersion 0.2.5  (2017-01-30)\n===========================\n * Fix race condition in manager\n\nVersion 0.2.4  (2017-01-27)\n===========================\n * OnePlus 3T support\n * Enable installation as NEOS app\n * Various minor bugfixes\n\nVersion 0.2.3  (2017-01-11)\n===========================\n * Reduce space usage by 80%\n * Add better logging\n * Add Travis CI\n\nVersion 0.2.2  (2017-01-10)\n===========================\n * Board triggers started signal on CAN messages\n * Improved autoexposure\n * Handle out of space, improve upload status\n\nVersion 0.2.1  (2016-12-14)\n===========================\n * Performance improvements, removal of more numpy\n * Fix boardd process priority\n * Make counter timer reset on use of steering wheel\n\nVersion 0.2  (2016-12-12)\n=========================\n * Car/Radar abstraction layers have shipped, see cereal/car.capnp\n * controlsd has been refactored\n * Shipped plant model and testing maneuvers\n * visiond exits more gracefully now\n * Hardware encoder in visiond should always init\n * ui now turns off the screen after 30 seconds\n * Switch to openpilot release branch for future releases\n * Added preliminary Docker container to run tests on PC\n\nVersion 0.1  (2016-11-29)\n=========================\n * Initial release of openpilot\n * Adaptive cruise control is working\n * Lane keep assist is working\n * Support for Acura ILX 2016 with AcuraWatch Plus\n * Support for Honda Civic 2016 Touring Edition\n"
  },
  {
    "path": "SAFETY.md",
    "content": "openpilot Safety\n======\n\nopenpilot is an Adaptive Cruise Control (ACC) and Automated Lane Centering (ALC) system.\nLike other ACC and ALC systems, openpilot is a failsafe passive system and it requires the\ndriver to be alert and to pay attention at all times.\n\nIn order to enforce driver alertness, openpilot includes a driver monitoring feature\nthat alerts the driver when distracted.\n\nHowever, even with an attentive driver, we must make further efforts for the system to be\nsafe. We repeat, **driver alertness is necessary, but not sufficient, for openpilot to be\nused safely** and openpilot is provided with no warranty of fitness for any purpose.\n\nopenpilot is developed in good faith to be compliant with FMVSS requirements and to follow\nindustry standards of safety for Level 2 Driver Assistance Systems. In particular, we observe\nISO26262 guidelines, including those from [pertinent documents](https://www.nhtsa.gov/sites/nhtsa.dot.gov/files/documents/13498a_812_573_alcsystemreport.pdf)\nreleased by NHTSA. In addition, we impose strict coding guidelines (like [MISRA C : 2012](https://www.misra.org.uk/what-is-misra/))\non parts of openpilot that are safety relevant. We also perform software-in-the-loop,\nhardware-in-the-loop and in-vehicle tests before each software release.\n\nFollowing Hazard and Risk Analysis and FMEA, at a very high level, we have designed openpilot\nensuring two main safety requirements.\n\n1. The driver must always be capable to immediately retake manual control of the vehicle,\n   by stepping on either pedal or by pressing the cancel button.\n2. The vehicle must not alter its trajectory too quickly for the driver to safely\n   react. This means that while the system is engaged, the actuators are constrained\n   to operate within reasonable limits.\n\nFor additional safety implementation details, refer to [panda safety model](https://github.com/commaai/panda#safety-model). For vehicle specific implementation of the safety concept, refer to [panda/board/safety/](https://github.com/commaai/panda/tree/master/board/safety).\n\n**Extra note**: comma.ai strongly discourages the use of openpilot forks with safety code either missing or\n  not fully meeting the above requirements.\n"
  },
  {
    "path": "SConstruct",
    "content": "import os\nimport shutil\nimport subprocess\nimport sys\nimport sysconfig\nimport platform\nimport numpy as np\n\nTICI = os.path.isfile('/TICI')\nJETSON = os.path.isfile('/JETSON')\n\nDecider('MD5-timestamp')\n\nAddOption('--test',\n          action='store_true',\n          help='build test files')\n\nAddOption('--setup',\n          action='store_true',\n          help='build setup and installer files')\n\nAddOption('--kaitai',\n          action='store_true',\n          help='Regenerate kaitai struct parsers')\n\nAddOption('--asan',\n          action='store_true',\n          help='turn on ASAN')\n\nAddOption('--ubsan',\n          action='store_true',\n          help='turn on UBSan')\n\nAddOption('--clazy',\n          action='store_true',\n          help='build with clazy')\n\nAddOption('--compile_db',\n          action='store_true',\n          help='build clang compilation database')\n\nAddOption('--mpc-generate',\n          action='store_true',\n          help='regenerates the mpc sources')\n\nAddOption('--snpe',\n          action='store_true',\n          help='use SNPE on PC')\n\nAddOption('--external-sconscript',\n          action='store',\n          metavar='FILE',\n          dest='external_sconscript',\n          help='add an external SConscript to the build')\n\nAddOption('--no-thneed',\n          action='store_true',\n          dest='no_thneed',\n          help='avoid using thneed')\n\nreal_arch = arch = subprocess.check_output([\"uname\", \"-m\"], encoding='utf8').rstrip()\nif platform.system() == \"Darwin\":\n  arch = \"Darwin\"\n\nif arch == \"aarch64\" and TICI:\n  arch = \"larch64\"\n\nUSE_WEBCAM = os.getenv(\"USE_WEBCAM\") is not None\n\nUSE_MIPI = os.getenv(\"USE_MIPI\") is not None\nif arch == \"aarch64\" and JETSON:\n  arch = \"jarch64\"\n\nlenv = {\n  \"PATH\": os.environ['PATH'],\n}\n\nif arch == \"aarch64\" or arch == \"larch64\":\n  lenv[\"LD_LIBRARY_PATH\"] = '/data/data/com.termux/files/usr/lib'\n\n  if arch == \"aarch64\":\n    # android\n    lenv[\"ANDROID_DATA\"] = os.environ['ANDROID_DATA']\n    lenv[\"ANDROID_ROOT\"] = os.environ['ANDROID_ROOT']\n\n  cpppath = [\n    \"#phonelibs/opencl/include\",\n  ]\n\n  libpath = [\n    \"/usr/local/lib\",\n    \"/usr/lib\",\n    \"/system/vendor/lib64\",\n    \"/system/comma/usr/lib\",\n    \"#phonelibs/nanovg\",\n  ]\n\n  if arch == \"larch64\":\n    libpath += [\n      \"#phonelibs/snpe/larch64\",\n      \"#phonelibs/libyuv/larch64/lib\",\n      \"/usr/lib/aarch64-linux-gnu\"\n    ]\n    cpppath += [\n      \"#selfdrive/camerad/include\",\n    ]\n    cflags = [\"-DQCOM2\", \"-mcpu=cortex-a57\"]\n    cxxflags = [\"-DQCOM2\", \"-mcpu=cortex-a57\"]\n    rpath = [\"/usr/local/lib\"]\n  else:\n    libpath += [\n      \"#phonelibs/snpe/aarch64\",\n      \"#phonelibs/libyuv/lib\",\n      \"/system/vendor/lib64\",\n      \"#phonelibs/mapbox-gl-native-qt/aarch64\",\n    ]\n    cflags = [\"-DQCOM\", \"-D_USING_LIBCXX\", \"-mcpu=cortex-a57\"]\n    cxxflags = [\"-DQCOM\", \"-D_USING_LIBCXX\", \"-mcpu=cortex-a57\"]\n    rpath = []\nelse:\n  cflags = []\n  cxxflags = []\n  cpppath = []\n  rpath = []\n\n  if arch == \"jarch64\":\n    libpath = [\n      \"#phonelibs/libyuv/larch64/lib\",\n      \"/usr/lib/aarch64-linux-gnu\",\n      \"#selfdrive/common\",\n      \"/usr/lib\",\n      \"/usr/local/lib\",\n      \"/usr/local/pocl/lib\",\n      \"#phonelibs/mapbox-gl-native-qt/jarch64\",\n    ]\n    cflags = [\"-DXNX\", \"-march=armv8.2-a\"]\n    cxxflags = [\"-DXNX\", \"-march=armv8.2-a\"]\n    rpath += [\"/usr/local/lib\"]\n  elif arch == \"Darwin\":\n    yuv_dir = \"mac\" if real_arch != \"arm64\" else \"mac_arm64\"\n    libpath = [\n      f\"#phonelibs/libyuv/{yuv_dir}/lib\",\n      \"/usr/local/lib\",\n      \"/opt/homebrew/lib\",\n      \"/usr/local/opt/openssl/lib\",\n      \"/opt/homebrew/opt/openssl/lib\",\n      \"/System/Library/Frameworks/OpenGL.framework/Libraries\",\n    ]\n    cflags += [\"-DGL_SILENCE_DEPRECATION\"]\n    cxxflags += [\"-DGL_SILENCE_DEPRECATION\"]\n    cpppath += [\n      \"/opt/homebrew/include\",\n      \"/usr/local/opt/openssl/include\",\n      \"/opt/homebrew/opt/openssl/include\"\n    ]\n  else:\n    libpath = [\n      \"#phonelibs/snpe/x86_64-linux-clang\",\n      \"#phonelibs/libyuv/x64/lib\",\n      \"#phonelibs/mapbox-gl-native-qt/x86_64\",\n      \"#cereal\",\n      \"#selfdrive/common\",\n      \"/usr/lib\",\n      \"/usr/local/lib\",\n    ]\n\n  if arch != \"jarch64\":\n    rpath += [\"phonelibs/snpe/x86_64-linux-clang\"]\n  rpath += [\n    \"cereal\",\n    \"selfdrive/common\"\n  ]\n\n  # allows shared libraries to work globally\n  rpath = [os.path.join(os.getcwd(), x) for x in rpath]\n\nif GetOption('asan'):\n  ccflags = [\"-fsanitize=address\", \"-fno-omit-frame-pointer\"]\n  ldflags = [\"-fsanitize=address\"]\nelif GetOption('ubsan'):\n  ccflags = [\"-fsanitize=undefined\"]\n  ldflags = [\"-fsanitize=undefined\"]\nelse:\n  ccflags = []\n  ldflags = []\n\n# no --as-needed on mac linker\nif arch != \"Darwin\":\n  ldflags += [\"-Wl,--as-needed\"]\n\n# Enable swaglog include in submodules\ncflags += [\"-DSWAGLOG\"]\ncxxflags += [\"-DSWAGLOG\"]\n\n# change pythonpath to this\nlenv[\"PYTHONPATH\"] = Dir(\"#\").path\n\nenv = Environment(\n  ENV=lenv,\n  CCFLAGS=[\n    \"-g\",\n    \"-fPIC\",\n    \"-O2\",\n    \"-Wunused\",\n    \"-Werror\",\n    \"-Wno-unknown-warning-option\",\n    \"-Wno-deprecated-register\",\n    \"-Wno-register\",\n    \"-Wno-inconsistent-missing-override\",\n    \"-Wno-c99-designator\",\n    \"-Wno-reorder-init-list\",\n  ] + cflags + ccflags,\n\n  CPPPATH=cpppath + [\n    \"#\",\n    \"#phonelibs/catch2/include\",\n    \"#phonelibs/bzip2\",\n    \"#phonelibs/libyuv/include\",\n    \"#phonelibs/openmax/include\",\n    \"#phonelibs/json11\",\n    \"#phonelibs/curl/include\",\n    \"#phonelibs/libgralloc/include\",\n    \"#phonelibs/android_frameworks_native/include\",\n    \"#phonelibs/android_hardware_libhardware/include\",\n    \"#phonelibs/android_system_core/include\",\n    \"#phonelibs/linux/include\",\n    \"#phonelibs/snpe/include\",\n    \"#phonelibs/mapbox-gl-native-qt/include\",\n    \"#phonelibs/nanovg\",\n    \"#phonelibs/qrcode\",\n    \"#phonelibs\",\n    \"#cereal\",\n    \"#opendbc/can\",\n  ],\n\n  CC='clang',\n  CXX='clang++',\n  LINKFLAGS=ldflags,\n\n  RPATH=rpath,\n\n  CFLAGS=[\"-std=gnu11\"] + cflags,\n  CXXFLAGS=[\"-std=c++1z\"] + cxxflags,\n  LIBPATH=libpath + [\n    \"#cereal\",\n    \"#phonelibs\",\n    \"#opendbc/can\",\n    \"#selfdrive/boardd\",\n    \"#selfdrive/common\",\n  ],\n  CYTHONCFILESUFFIX=\".cpp\",\n  COMPILATIONDB_USE_ABSPATH=True,\n  tools=[\"default\", \"cython\", \"compilation_db\"],\n)\n\nif GetOption('compile_db'):\n  env.CompilationDatabase('compile_commands.json')\n\n# Setup cache dir\ncache_dir = '/data/scons_cache' if TICI else '/tmp/scons_cache'\nCacheDir(cache_dir)\nClean([\".\"], cache_dir)\n\nnode_interval = 5\nnode_count = 0\ndef progress_function(node):\n  global node_count\n  node_count += node_interval\n  sys.stderr.write(\"progress: %d\\n\" % node_count)\n\nif os.environ.get('SCONS_PROGRESS'):\n  Progress(progress_function, interval=node_interval)\n\nSHARED = False\n\ndef abspath(x):\n  if arch == 'aarch64':\n    pth = os.path.join(\"/data/pythonpath\", x[0].path)\n    env.Depends(pth, x)\n    return File(pth)\n  else:\n    # rpath works elsewhere\n    return x[0].path.rsplit(\"/\", 1)[1][:-3]\n\n# Cython build enviroment\npy_include = sysconfig.get_paths()['include']\nenvCython = env.Clone()\nenvCython[\"CPPPATH\"] += [py_include, np.get_include()]\nenvCython[\"CCFLAGS\"] += [\"-Wno-#warnings\", \"-Wno-deprecated-declarations\"]\n\nenvCython[\"LIBS\"] = []\nif arch == \"Darwin\":\n  envCython[\"LINKFLAGS\"] = [\"-bundle\", \"-undefined\", \"dynamic_lookup\"]\nelif arch == \"aarch64\":\n  envCython[\"LINKFLAGS\"] = [\"-shared\"]\n  envCython[\"LIBS\"] = [os.path.basename(py_include)]\nelse:\n  envCython[\"LINKFLAGS\"] = [\"-pthread\", \"-shared\"]\n\nExport('envCython')\n\n# Qt build environment\nqt_env = env.Clone()\nqt_modules = [\"Widgets\", \"Gui\", \"Core\", \"Network\", \"Concurrent\", \"Multimedia\", \"Quick\", \"Qml\", \"QuickWidgets\", \"Location\", \"Positioning\"]\nif arch != \"aarch64\":\n  qt_modules += [\"DBus\"]\n\nqt_libs = []\nif arch == \"Darwin\":\n  if real_arch == \"arm64\":\n    qt_env['QTDIR'] = \"/opt/homebrew/opt/qt@5\"\n  else:\n    qt_env['QTDIR'] = \"/usr/local/opt/qt@5\"\n  qt_dirs = [\n    os.path.join(qt_env['QTDIR'], \"include\"),\n  ]\n  qt_dirs += [f\"{qt_env['QTDIR']}/include/Qt{m}\" for m in qt_modules]\n  qt_env[\"LINKFLAGS\"] += [\"-F\" + os.path.join(qt_env['QTDIR'], \"lib\")]\n  qt_env[\"FRAMEWORKS\"] += [f\"Qt{m}\" for m in qt_modules] + [\"OpenGL\"]\nelif arch == \"aarch64\":\n  qt_env['QTDIR'] = \"/system/comma/usr\"\n  qt_dirs = [\n    f\"/system/comma/usr/include/qt\",\n  ]\n  qt_dirs += [f\"/system/comma/usr/include/qt/Qt{m}\" for m in qt_modules]\n\n  qt_libs = [f\"Qt5{m}\" for m in qt_modules]\n  qt_libs += ['EGL', 'GLESv3', 'c++_shared']\nelse:\n  qt_env['QTDIR'] = \"/usr\"\n  qt_dirs = [\n    f\"/usr/include/{real_arch}-linux-gnu/qt5\",\n    f\"/usr/include/{real_arch}-linux-gnu/qt5/QtGui/5.12.8/QtGui\",\n  ]\n  qt_dirs += [f\"/usr/include/{real_arch}-linux-gnu/qt5/Qt{m}\" for m in qt_modules]\n\n  qt_libs = [f\"Qt5{m}\" for m in qt_modules]\n  if arch == \"larch64\" or arch == \"jarch64\":\n    qt_libs += [\"GLESv2\", \"wayland-client\"]\n  elif arch != \"Darwin\":\n    qt_libs += [\"GL\"]\n\nqt_env.Tool('qt')\nqt_env['CPPPATH'] += qt_dirs + [\"#selfdrive/ui/qt/\"]\nqt_flags = [\n  \"-D_REENTRANT\",\n  \"-DQT_NO_DEBUG\",\n  \"-DQT_WIDGETS_LIB\",\n  \"-DQT_GUI_LIB\",\n  \"-DQT_QUICK_LIB\",\n  \"-DQT_QUICKWIDGETS_LIB\",\n  \"-DQT_QML_LIB\",\n  \"-DQT_CORE_LIB\",\n  \"-DQT_MESSAGELOGCONTEXT\",\n]\nqt_env['CXXFLAGS'] += qt_flags\nqt_env['LIBPATH'] += ['#selfdrive/ui']\nqt_env['LIBS'] = qt_libs\n\nif GetOption(\"clazy\"):\n  checks = [\n    \"level0\",\n    \"level1\",\n    \"no-range-loop\",\n    \"no-non-pod-global-static\",\n  ]\n  qt_env['CXX'] = 'clazy'\n  qt_env['ENV']['CLAZY_IGNORE_DIRS'] = qt_dirs[0]\n  qt_env['ENV']['CLAZY_CHECKS'] = ','.join(checks)\n\nExport('env', 'qt_env', 'arch', 'real_arch', 'SHARED', 'USE_WEBCAM', 'USE_MIPI')\n\nSConscript(['selfdrive/common/SConscript'])\nImport('_common', '_gpucommon', '_gpu_libs')\n\nif SHARED:\n  common, gpucommon = abspath(common), abspath(gpucommon)\nelse:\n  common = [_common, 'json11']\n  gpucommon = [_gpucommon] + _gpu_libs\n\nExport('common', 'gpucommon')\n\n# cereal and messaging are shared with the system\nSConscript(['cereal/SConscript'])\nif SHARED:\n  cereal = abspath([File('cereal/libcereal_shared.so')])\n  messaging = abspath([File('cereal/libmessaging_shared.so')])\nelse:\n  cereal = [File('#cereal/libcereal.a')]\n  messaging = [File('#cereal/libmessaging.a')]\n  visionipc = [File('#cereal/libvisionipc.a')]\n\nExport('cereal', 'messaging', 'visionipc')\n\n# Build rednose library and ekf models\n\nrednose_config = {\n  'generated_folder': '#selfdrive/locationd/models/generated',\n  'to_build': {\n    'live': ('#selfdrive/locationd/models/live_kf.py', True, ['live_kf_constants.h']),\n    'car': ('#selfdrive/locationd/models/car_kf.py', True, []),\n  },\n}\n\nif arch != \"aarch64\":\n  rednose_config['to_build'].update({\n    'gnss': ('#selfdrive/locationd/models/gnss_kf.py', True, []),\n    'loc_4': ('#selfdrive/locationd/models/loc_kf.py', True, []),\n    'pos_computer_4': ('#rednose/helpers/lst_sq_computer.py', False, []),\n    'pos_computer_5': ('#rednose/helpers/lst_sq_computer.py', False, []),\n    'feature_handler_5': ('#rednose/helpers/feature_handler.py', False, []),\n    'lane': ('#xx/pipeline/lib/ekf/lane_kf.py', True, []),\n  })\n\nExport('rednose_config')\nSConscript(['rednose/SConscript'])\n\n# Build openpilot\n\nSConscript(['cereal/SConscript'])\nSConscript(['panda/board/SConscript'])\nSConscript(['opendbc/can/SConscript'])\n\nSConscript(['phonelibs/SConscript'])\n\nSConscript(['common/SConscript'])\nSConscript(['common/kalman/SConscript'])\nSConscript(['common/transformations/SConscript'])\n\nSConscript(['selfdrive/camerad/SConscript'])\nSConscript(['selfdrive/modeld/SConscript'])\n\nSConscript(['selfdrive/controls/lib/cluster/SConscript'])\nSConscript(['selfdrive/controls/lib/lateral_mpc/SConscript'])\nSConscript(['selfdrive/controls/lib/lead_mpc_lib/SConscript'])\nSConscript(['selfdrive/controls/lib/longitudinal_mpc_lib/SConscript'])\n\nSConscript(['selfdrive/boardd/SConscript'])\nSConscript(['selfdrive/proclogd/SConscript'])\nSConscript(['selfdrive/clocksd/SConscript'])\n\nSConscript(['selfdrive/loggerd/SConscript'])\n\nSConscript(['selfdrive/locationd/SConscript'])\nif not os.path.isfile(\"/JETSON\"):\n  SConscript(['selfdrive/sensord/SConscript'])\nSConscript(['selfdrive/ui/SConscript'])\n\nif arch != \"Darwin\":\n  SConscript(['selfdrive/logcatd/SConscript'])\n\nexternal_sconscript = GetOption('external_sconscript')\nif external_sconscript:\n  SConscript([external_sconscript])\n"
  },
  {
    "path": "cereal/.gitignore",
    "content": "gen\nnode_modules\npackage-lock.json\n*.tmp\n*.pyc\n__pycache__\n.*.swp\n.*.swo\n*.os\n*.o\n*.a\n\ntest_runner\n\nlibmessaging.*\nlibmessaging_shared.*\nservices.h\n.sconsign.dblite\nlibcereal_shared.*\n.mypy_cache/\ncatch2/\n"
  },
  {
    "path": "cereal/SConscript",
    "content": "Import('env', 'envCython', 'arch', 'common')\n\nimport shutil\n\ncereal_dir = Dir('.')\ngen_dir = Dir('gen')\nmessaging_dir = Dir('messaging')\n\n# Build cereal\n\nschema_files = ['log.capnp', 'car.capnp', 'legacy.capnp', 'dp.capnp']\nenv.Command([\"gen/c/include/c++.capnp.h\", \"gen/c/include/java.capnp.h\"], [], \"mkdir -p \" + gen_dir.path + \"/c/include && touch $TARGETS\")\nenv.Command([f'gen/cpp/{s}.c++' for s in schema_files] + [f'gen/cpp/{s}.h' for s in schema_files],\n            schema_files,\n            f\"capnpc --src-prefix={cereal_dir.path} $SOURCES -o c++:{gen_dir.path}/cpp/\")\n\nif shutil.which('capnpc-java'):\n  env.Command(['gen/java/Car.java', 'gen/java/Log.java'],\n              schema_files,\n              f\"capnpc $SOURCES --src-prefix={cereal_dir.path} -o java:{gen_dir.path}/java/\")\n\n# TODO: remove non shared cereal and messaging\ncereal_objects = env.SharedObject([f'gen/cpp/{s}.c++' for s in schema_files])\n\nenv.Library('cereal', cereal_objects)\nenv.SharedLibrary('cereal_shared', cereal_objects)\n\n# Build messaging\n\nservices_h = env.Command(['services.h'], ['services.py'], 'python3 ' + cereal_dir.path + '/services.py > $TARGET')\n\nmessaging_objects = env.SharedObject([\n  'messaging/messaging.cc',\n  'messaging/impl_zmq.cc',\n  'messaging/impl_msgq.cc',\n  'messaging/msgq.cc',\n  'messaging/socketmaster.cc',\n])\n\nmessaging_lib = env.Library('messaging', messaging_objects)\nDepends('messaging/impl_zmq.cc', services_h)\n\nenv.Program('messaging/bridge', ['messaging/bridge.cc'], LIBS=[messaging_lib, 'zmq', common])\nDepends('messaging/bridge.cc', services_h)\n\nenvCython.Program('messaging/messaging_pyx.so', 'messaging/messaging_pyx.pyx', LIBS=envCython[\"LIBS\"]+[messaging_lib, \"zmq\", common])\n\n\n# Build Vision IPC\nvipc_sources = [\n  'visionipc/ipc.cc',\n  'visionipc/visionipc_server.cc',\n  'visionipc/visionipc_client.cc',\n  'visionipc/visionbuf.cc',\n]\n\nif arch in [\"aarch64\", \"larch64\"]:\n  vipc_sources += ['visionipc/visionbuf_ion.cc']\nelse:\n  vipc_sources += ['visionipc/visionbuf_cl.cc']\n\nvipc_objects = env.SharedObject(vipc_sources)\nvipc = env.Library('visionipc', vipc_objects)\n\n\nlibs = envCython[\"LIBS\"]+[\"OpenCL\", \"zmq\", vipc, messaging_lib, common]\nif arch == \"aarch64\":\n  libs += [\"adreno_utils\"]\nif arch == \"Darwin\":\n  del libs[libs.index('OpenCL')]\n  envCython['FRAMEWORKS'] += ['OpenCL']\nenvCython.Program('visionipc/visionipc_pyx.so', 'visionipc/visionipc_pyx.pyx', LIBS=libs)\n\n\nif GetOption('test'):\n  env.Program('messaging/test_runner', ['messaging/test_runner.cc', 'messaging/msgq_tests.cc'], LIBS=[messaging_lib, common])\n  env.Program('visionipc/test_runner', ['visionipc/test_runner.cc', 'visionipc/visionipc_tests.cc'], LIBS=[vipc, messaging_lib, 'zmq', 'pthread', 'OpenCL', common])\n"
  },
  {
    "path": "cereal/__init__.py",
    "content": "# pylint: skip-file\nimport os\nimport capnp\n\nCEREAL_PATH = os.path.dirname(os.path.abspath(__file__))\ncapnp.remove_import_hook()\n\nlog = capnp.load(os.path.join(CEREAL_PATH, \"log.capnp\"))\ncar = capnp.load(os.path.join(CEREAL_PATH, \"car.capnp\"))\n"
  },
  {
    "path": "cereal/car.capnp",
    "content": "using Cxx = import \"./include/c++.capnp\";\n$Cxx.namespace(\"cereal\");\n\nusing Java = import \"./include/java.capnp\";\n$Java.package(\"ai.comma.openpilot.cereal\");\n$Java.outerClassname(\"Car\");\n\n@0x8e2af1e708af8b8d;\n\n# ******* events causing controls state machine transition *******\n\nstruct CarEvent @0x9b1657f34caf3ad3 {\n  name @0 :EventName;\n\n  # event types\n  enable @1 :Bool;\n  noEntry @2 :Bool;\n  warning @3 :Bool;   # alerts presented only when  enabled or soft disabling\n  userDisable @4 :Bool;\n  softDisable @5 :Bool;\n  immediateDisable @6 :Bool;\n  preEnable @7 :Bool;\n  permanent @8 :Bool; # alerts presented regardless of openpilot state\n\n  enum EventName @0xbaa8c5d505f727de {\n    canError @0;\n    steerUnavailable @1;\n    brakeUnavailable @2;\n    wrongGear @4;\n    doorOpen @5;\n    seatbeltNotLatched @6;\n    espDisabled @7;\n    wrongCarMode @8;\n    steerTempUnavailable @9;\n    reverseGear @10;\n    buttonCancel @11;\n    buttonEnable @12;\n    pedalPressed @13;\n    cruiseDisabled @14;\n    speedTooLow @17;\n    outOfSpace @18;\n    overheat @19;\n    calibrationIncomplete @20;\n    calibrationInvalid @21;\n    controlsMismatch @22;\n    pcmEnable @23;\n    pcmDisable @24;\n    noTarget @25;\n    radarFault @26;\n    brakeHold @28;\n    parkBrake @29;\n    manualRestart @30;\n    lowSpeedLockout @31;\n    plannerError @32;\n    joystickDebug @34;\n    steerTempUnavailableSilent @35;\n    resumeRequired @36;\n    preDriverDistracted @37;\n    promptDriverDistracted @38;\n    driverDistracted @39;\n    preDriverUnresponsive @43;\n    promptDriverUnresponsive @44;\n    driverUnresponsive @45;\n    belowSteerSpeed @46;\n    lowBattery @48;\n    vehicleModelInvalid @50;\n    accFaulted @51;\n    sensorDataInvalid @52;\n    commIssue @53;\n    tooDistracted @54;\n    posenetInvalid @55;\n    soundsUnavailable @56;\n    preLaneChangeLeft @57;\n    preLaneChangeRight @58;\n    laneChange @59;\n    communityFeatureDisallowed @62;\n    lowMemory @63;\n    stockAeb @64;\n    ldw @65;\n    carUnrecognized @66;\n    invalidLkasSetting @69;\n    speedTooHigh @70;\n    laneChangeBlocked @71;\n    relayMalfunction @72;\n    gasPressed @73;\n    stockFcw @74;\n    startup @75;\n    startupNoCar @76;\n    startupNoControl @77;\n    startupMaster @78;\n    startupFuzzyFingerprint @97;\n    startupNoFw @104;\n    fcw @79;\n    steerSaturated @80;\n    belowEngageSpeed @84;\n    noGps @85;\n    wrongCruiseMode @87;\n    modeldLagging @89;\n    deviceFalling @90;\n    fanMalfunction @91;\n    cameraMalfunction @92;\n    gpsMalfunction @94;\n    processNotRunning @95;\n    dashcamMode @96;\n    controlsInitializing @98;\n    usbError @99;\n    roadCameraError @100;\n    driverCameraError @101;\n    wideRoadCameraError @102;\n    localizerMalfunction @103;\n    highCpuUsage @105;\n\n    driverMonitorLowAccDEPRECATED @68;\n    radarCanErrorDEPRECATED @15;\n    radarCommIssueDEPRECATED @67;\n    gasUnavailableDEPRECATED @3;\n    dataNeededDEPRECATED @16;\n    modelCommIssueDEPRECATED @27;\n    ipasOverrideDEPRECATED @33;\n    geofenceDEPRECATED @40;\n    driverMonitorOnDEPRECATED @41;\n    driverMonitorOffDEPRECATED @42;\n    calibrationProgressDEPRECATED @47;\n    invalidGiraffeHondaDEPRECATED @49;\n    invalidGiraffeToyotaDEPRECATED @60;\n    internetConnectivityNeededDEPRECATED @61;\n    whitePandaUnsupportedDEPRECATED @81;\n    commIssueWarningDEPRECATED @83;\n    focusRecoverActiveDEPRECATED @86;\n    neosUpdateRequiredDEPRECATED @88;\n    modelLagWarningDEPRECATED @93;\n    startupOneplusDEPRECATED @82;\n\n    #dp\n    autoLaneChange @106;\n    manualSteeringRequired @107;\n    manualSteeringRequiredBlinkersOn @108;\n    leadCarMoving @109;\n\n    # timebomb assist\n    timebombWarn @110;\n    timebombBypassing @111;\n    timebombBypassed @112;\n    mapdAlert @113;\n    speedLimitActive @114;\n    speedLimitValueChange @115;\n  }\n}\n\n# ******* main car state @ 100hz *******\n# all speeds in m/s\n\nstruct CarState {\n  events @13 :List(CarEvent);\n\n  # car speed\n  vEgo @1 :Float32;         # best estimate of speed\n  aEgo @16 :Float32;        # best estimate of acceleration\n  vEgoRaw @17 :Float32;     # unfiltered speed from CAN sensors\n  yawRate @22 :Float32;     # best estimate of yaw rate\n  standstill @18 :Bool;\n  wheelSpeeds @2 :WheelSpeeds;\n\n  # gas pedal, 0.0-1.0\n  gas @3 :Float32;        # this is user + computer\n  gasPressed @4 :Bool;    # this is user pedal only\n\n  # brake pedal, 0.0-1.0\n  brake @5 :Float32;      # this is user pedal only\n  brakePressed @6 :Bool;  # this is user pedal only\n\n  # steering wheel\n  steeringAngleDeg @7 :Float32;\n  steeringAngleOffsetDeg @37 :Float32; # Offset betweens sensors in case there multiple\n  steeringRateDeg @15 :Float32;\n  steeringTorque @8 :Float32;      # TODO: standardize units\n  steeringTorqueEps @27 :Float32;  # TODO: standardize units\n  steeringPressed @9 :Bool;        # if the user is using the steering wheel\n  steeringRateLimited @29 :Bool;   # if the torque is limited by the rate limiter\n  steerWarning @35 :Bool;          # temporary steer unavailble\n  steerError @36 :Bool;            # permanent steer error\n  stockAeb @30 :Bool;\n  stockFcw @31 :Bool;\n  espDisabled @32 :Bool;\n\n  # cruise state\n  cruiseState @10 :CruiseState;\n\n  # gear\n  gearShifter @14 :GearShifter;\n\n  # button presses\n  buttonEvents @11 :List(ButtonEvent);\n  leftBlinker @20 :Bool;\n  rightBlinker @21 :Bool;\n  genericToggle @23 :Bool;\n\n  # lock info\n  doorOpen @24 :Bool;\n  seatbeltUnlatched @25 :Bool;\n  canValid @26 :Bool;\n\n  # clutch (manual transmission only)\n  clutchPressed @28 :Bool;\n\n  # which packets this state came from\n  canMonoTimes @12: List(UInt64);\n\n  # blindspot sensors\n  leftBlindspot @33 :Bool; # Is there something blocking the left lane change\n  rightBlindspot @34 :Bool; # Is there something blocking the right lane change\n\n  # dp\n  lkMode @38 :Bool;\n  stopSteering @39 :Bool; # timebomb - stopSteering\n  engineRPM @40 :Float32;\n  cruiseActualEnabled @41 :Bool;\n\n  struct WheelSpeeds {\n    # optional wheel speeds\n    fl @0 :Float32;\n    fr @1 :Float32;\n    rl @2 :Float32;\n    rr @3 :Float32;\n  }\n\n  struct CruiseState {\n    enabled @0 :Bool;\n    speed @1 :Float32;\n    available @2 :Bool;\n    speedOffset @3 :Float32;\n    standstill @4 :Bool;\n    nonAdaptive @5 :Bool;\n    speedLimit @6 :Float32;\n  }\n\n  enum GearShifter {\n    unknown @0;\n    park @1;\n    drive @2;\n    neutral @3;\n    reverse @4;\n    sport @5;\n    low @6;\n    brake @7;\n    eco @8;\n    manumatic @9;\n  }\n\n  # send on change\n  struct ButtonEvent {\n    pressed @0 :Bool;\n    type @1 :Type;\n\n    enum Type {\n      unknown @0;\n      leftBlinker @1;\n      rightBlinker @2;\n      accelCruise @3;\n      decelCruise @4;\n      cancel @5;\n      altButton1 @6;\n      altButton2 @7;\n      altButton3 @8;\n      setCruise @9;\n      resumeCruise @10;\n      gapAdjustCruise @11;\n    }\n  }\n\n  errorsDEPRECATED @0 :List(CarEvent.EventName);\n  brakeLights @19 :Bool;\n}\n\n# ******* radar state @ 20hz *******\n\nstruct RadarData @0x888ad6581cf0aacb {\n  errors @0 :List(Error);\n  points @1 :List(RadarPoint);\n\n  # which packets this state came from\n  canMonoTimes @2 :List(UInt64);\n\n  enum Error {\n    canError @0;\n    fault @1;\n    wrongConfig @2;\n  }\n\n  # similar to LiveTracks\n  # is one timestamp valid for all? I think so\n  struct RadarPoint {\n    trackId @0 :UInt64;  # no trackId reuse\n\n    # these 3 are the minimum required\n    dRel @1 :Float32; # m from the front bumper of the car\n    yRel @2 :Float32; # m\n    vRel @3 :Float32; # m/s\n\n    # these are optional and valid if they are not NaN\n    aRel @4 :Float32; # m/s^2\n    yvRel @5 :Float32; # m/s\n\n    # some radars flag measurements VS estimates\n    measured @6 :Bool;\n  }\n}\n\n# ******* car controls @ 100hz *******\n\nstruct CarControl {\n  # must be true for any actuator commands to work\n  enabled @0 :Bool;\n  active @7 :Bool;\n\n  actuators @6 :Actuators;\n\n  cruiseControl @4 :CruiseControl;\n  hudControl @5 :HUDControl;\n\n  struct Actuators {\n    # range from 0.0 - 1.0\n    gasDEPRECATED @0: Float32;\n    brakeDEPRECATED @1: Float32;\n    # range from -1.0 - 1.0\n    steer @2: Float32;\n    steeringAngleDeg @3: Float32;\n\n    accel @4: Float32; # m/s^2\n    longControlState @5: LongControlState;\n\n    enum LongControlState @0xe40f3a917d908282{\n      off @0;\n      pid @1;\n      stopping @2;\n      starting @3;\n    }\n\n  }\n\n  struct CruiseControl {\n    cancel @0: Bool;\n    override @1: Bool;\n    speedOverride @2: Float32;\n    accelOverride @3: Float32;\n  }\n\n  struct HUDControl {\n    speedVisible @0: Bool;\n    setSpeed @1: Float32;\n    lanesVisible @2: Bool;\n    leadVisible @3: Bool;\n    visualAlert @4: VisualAlert;\n    audibleAlert @5: AudibleAlert;\n    rightLaneVisible @6: Bool;\n    leftLaneVisible @7: Bool;\n    rightLaneDepart @8: Bool;\n    leftLaneDepart @9: Bool;\n\n    enum VisualAlert {\n      # these are the choices from the Honda\n      # map as good as you can for your car\n      none @0;\n      fcw @1;\n      steerRequired @2;\n      brakePressed @3;\n      wrongGear @4;\n      seatbeltUnbuckled @5;\n      speedTooHigh @6;\n      ldw @7;\n    }\n\n    enum AudibleAlert {\n      none @0;\n      chimeEngage @1;\n      chimeDisengage @2;\n      chimeError @3;\n      chimeWarning1 @4;\n      chimeWarning2 @5;\n      chimeWarningRepeat @6;\n      chimePrompt @7;\n      chimeWarning2Repeat @8;\n    }\n  }\n\n  gasDEPRECATED @1 :Float32;\n  brakeDEPRECATED @2 :Float32;\n  steeringTorqueDEPRECATED @3 :Float32;\n}\n\n# ****** car param ******\n\nstruct CarParams {\n  carName @0 :Text;\n  carFingerprint @1 :Text;\n  fuzzyFingerprint @55 :Bool;\n\n  enableGasInterceptor @2 :Bool;\n  pcmCruise @3 :Bool;        # is openpilot's state tied to the PCM's cruise state?\n  enableDsu @5 :Bool;        # driving support unit\n  enableApgs @6 :Bool;       # advanced parking guidance system\n  enableBsm @56 :Bool;       # blind spot monitoring\n  hasStockCamera @57 :Bool;  # factory LKAS/LDW camera is present\n\n  minEnableSpeed @7 :Float32;\n  minSteerSpeed @8 :Float32;\n  maxSteeringAngleDeg @54 :Float32;\n  safetyModel @9 :SafetyModel;\n  safetyModelPassive @42 :SafetyModel = silent;\n  safetyParam @10 :Int16;\n\n  steerMaxBP @11 :List(Float32);\n  steerMaxV @12 :List(Float32);\n  gasMaxBPDEPRECATED @13 :List(Float32);\n  gasMaxVDEPRECATED @14 :List(Float32);\n  brakeMaxBPDEPRECATED @15 :List(Float32);\n  brakeMaxVDEPRECATED @16 :List(Float32);\n\n  # things about the car in the manual\n  mass @17 :Float32;            # [kg] curb weight: all fluids no cargo\n  wheelbase @18 :Float32;       # [m] distance from rear axle to front axle\n  centerToFront @19 :Float32;   # [m] distance from center of mass to front axle\n  steerRatio @20 :Float32;      # [] ratio of steering wheel angle to front wheel angle\n  steerRatioRear @21 :Float32;  # [] ratio of steering wheel angle to rear wheel angle (usually 0)\n\n  # things we can derive\n  rotationalInertia @22 :Float32;    # [kg*m2] body rotational inertia\n  tireStiffnessFront @23 :Float32;   # [N/rad] front tire coeff of stiff\n  tireStiffnessRear @24 :Float32;    # [N/rad] rear tire coeff of stiff\n\n  longitudinalTuning @25 :LongitudinalPIDTuning;\n  lateralParams @48 :LateralParams;\n  lateralTuning :union {\n    pid @26 :LateralPIDTuning;\n    indi @27 :LateralINDITuning;\n    lqr @40 :LateralLQRTuning;\n  }\n\n  steerLimitAlert @28 :Bool;\n  steerLimitTimer @47 :Float32;  # time before steerLimitAlert is issued\n\n  vEgoStopping @29 :Float32; # Speed at which the car goes into stopping state\n  directAccelControl @30 :Bool; # Does the car have direct accel control or just gas/brake\n  stoppingControl @31 :Bool; # Does the car allows full control even at lows speeds when stopping\n  startAccel @32 :Float32; # Required acceleraton to overcome creep braking\n  steerRateCost @33 :Float32; # Lateral MPC cost on steering rate\n  steerControlType @34 :SteerControlType;\n  radarOffCan @35 :Bool; # True when radar objects aren't visible on CAN\n  minSpeedCan @51 :Float32; # Minimum vehicle speed from CAN (below this value drops to 0)\n  stoppingDecelRate @52 :Float32; # m/s^2/s while trying to stop\n  startingAccelRate @53 :Float32; # m/s^2/s while trying to start\n\n  steerActuatorDelay @36 :Float32; # Steering wheel actuator delay in seconds\n  longitudinalActuatorDelay @58 :Float32; # Gas/Brake actuator delay in seconds\n  openpilotLongitudinalControl @37 :Bool; # is openpilot doing the longitudinal control?\n  carVin @38 :Text; # VIN number queried during fingerprinting\n  dashcamOnly @41: Bool;\n  transmissionType @43 :TransmissionType;\n  carFw @44 :List(CarFw);\n\n  radarTimeStep @45: Float32 = 0.05;  # time delta between radar updates, 20Hz is very standard\n  communityFeature @46: Bool;  # true if a community maintained feature is detected\n  fingerprintSource @49: FingerprintSource;\n  networkLocation @50 :NetworkLocation;  # Where Panda/C2 is integrated into the car's CAN network\n\n  struct LateralParams {\n    torqueBP @0 :List(Int32);\n    torqueV @1 :List(Int32);\n  }\n\n  struct LateralPIDTuning {\n    kpBP @0 :List(Float32);\n    kpV @1 :List(Float32);\n    kiBP @2 :List(Float32);\n    kiV @3 :List(Float32);\n    kf @4 :Float32;\n  }\n\n  struct LongitudinalPIDTuning {\n    kpBP @0 :List(Float32);\n    kpV @1 :List(Float32);\n    kiBP @2 :List(Float32);\n    kiV @3 :List(Float32);\n    deadzoneBP @4 :List(Float32);\n    deadzoneV @5 :List(Float32);\n  }\n\n  struct LateralINDITuning {\n    outerLoopGainBP @4 :List(Float32);\n    outerLoopGainV @5 :List(Float32);\n    innerLoopGainBP @6 :List(Float32);\n    innerLoopGainV @7 :List(Float32);\n    timeConstantBP @8 :List(Float32);\n    timeConstantV @9 :List(Float32);\n    actuatorEffectivenessBP @10 :List(Float32);\n    actuatorEffectivenessV @11 :List(Float32);\n\n    outerLoopGainDEPRECATED @0 :Float32;\n    innerLoopGainDEPRECATED @1 :Float32;\n    timeConstantDEPRECATED @2 :Float32;\n    actuatorEffectivenessDEPRECATED @3 :Float32;\n  }\n\n  struct LateralLQRTuning {\n    scale @0 :Float32;\n    ki @1 :Float32;\n    dcGain @2 :Float32;\n\n    # State space system\n    a @3 :List(Float32);\n    b @4 :List(Float32);\n    c @5 :List(Float32);\n\n    k @6 :List(Float32);  # LQR gain\n    l @7 :List(Float32);  # Kalman gain\n  }\n\n  enum SafetyModel {\n    silent @0;\n    hondaNidec @1;\n    toyota @2;\n    elm327 @3;\n    gm @4;\n    hondaBoschGiraffe @5;\n    ford @6;\n    cadillac @7;\n    hyundai @8;\n    chrysler @9;\n    tesla @10;\n    subaru @11;\n    gmPassive @12;\n    mazda @13;\n    nissan @14;\n    volkswagen @15;\n    toyotaIpas @16;\n    allOutput @17;\n    gmAscm @18;\n    noOutput @19;  # like silent but without silent CAN TXs\n    hondaBoschHarness @20;\n    volkswagenPq @21;\n    subaruLegacy @22;  # pre-Global platform\n    hyundaiLegacy @23;\n    hyundaiCommunity @24;\n  }\n\n  enum SteerControlType {\n    torque @0;\n    angle @1;\n  }\n\n  enum TransmissionType {\n    unknown @0;\n    automatic @1;  # Traditional auto, including DSG\n    manual @2;  # True \"stick shift\" only\n    direct @3;  # Electric vehicle or other direct drive\n    cvt @4;\n  }\n\n  struct CarFw {\n    ecu @0 :Ecu;\n    fwVersion @1 :Data;\n    address @2: UInt32;\n    subAddress @3: UInt8;\n  }\n\n  enum Ecu {\n    eps @0;\n    esp @1;\n    fwdRadar @2;\n    fwdCamera @3;\n    engine @4;\n    unknown @5;\n    transmission @8; # Transmission Control Module\n    srs @9; # airbag\n    gateway @10; # can gateway\n    hud @11; # heads up display\n    combinationMeter @12; # instrument cluster\n\n    # Toyota only\n    dsu @6;\n    apgs @7;\n\n    # Honda only\n    vsa @13; # Vehicle Stability Assist\n    programmedFuelInjection @14;\n    electricBrakeBooster @15;\n    shiftByWire @16;\n  }\n\n  enum FingerprintSource {\n    can @0;\n    fw @1;\n    fixed @2;\n  }\n\n  enum NetworkLocation {\n    fwdCamera @0;  # Standard/default integration at LKAS camera\n    gateway @1;    # Integration at vehicle's CAN gateway\n  }\n\n  enableCameraDEPRECATED @4 :Bool;\n  isPandaBlackDEPRECATED @39: Bool;\n}\n"
  },
  {
    "path": "cereal/dp.capnp",
    "content": "using Cxx = import \"./include/c++.capnp\";\n$Cxx.namespace(\"cereal\");\n\nusing Java = import \"./include/java.capnp\";\n$Java.package(\"ai.comma.openpilot.cereal\");\n$Java.outerClassname(\"Dp\");\n\n@0xbfa7e645486440c7;\n\n# dp.capnp: a home for deprecated structs\n\n# dp\nstruct DragonConf {\n  dpThermalStarted @0 :Bool;\n  dpThermalOverheat @1 :Bool;\n  dpAtl @2 :Bool;\n  dpAtlOpLong @3 :Bool;\n  dpDashcamd @4 :Bool;\n  dpAutoShutdown @5 :Bool;\n  dpAthenad @6 :Bool;\n  dpUploader @7 :Bool;\n  dpLateralMode @8 :UInt8;\n  dpSignalOffDelay @9 :Float32;\n  dpLcMinMph @10 :UInt8;\n  dpLcAutoMinMph @11 :UInt8;\n  dpLcAutoDelay @12 :Float32;\n  dpLaneLessModeCtrl @13 :Bool;\n  dpLaneLessMode @14 :UInt8;\n  dpAllowGas @15 :Bool;\n  dpFollowingProfileCtrl @16 :Bool;\n  dpFollowingProfile @17 :UInt8;\n  dpAccelProfileCtrl @18 :Bool;\n  dpAccelProfile @19 :UInt8;\n  dpGearCheck @20 :Bool;\n  dpSpeedCheck @21 :Bool;\n  dpUiDisplayMode @22 :UInt8;\n  dpUiSpeed @23 :Bool;\n  dpUiEvent @24 :Bool;\n  dpUiMaxSpeed @25 :Bool;\n  dpUiFace @26 :Bool;\n  dpUiLane @27 :Bool;\n  dpUiLead @28 :Bool;\n  dpUiSide @29 :Bool;\n  dpUiTop @30 :Bool;\n  dpUiBlinker @31 :Bool;\n  dpUiBrightness @32 :UInt8;\n  dpUiVolume @33 :Int8;\n  dpToyotaLdw @34 :Bool;\n  dpToyotaSng @35 :Bool;\n  dpToyotaCruiseOverride @36 :Bool;\n  dpToyotaCruiseOverrideVego @37 :Bool;\n  dpToyotaCruiseOverrideAt @38 :Float32;\n  dpToyotaCruiseOverrideSpeed @39 :Float32;\n  dpVwTimebombAssist @40 :Bool;\n  dpIpAddr @41 :Text;\n  dpCameraOffset @42 :Int8;\n  dpPathOffset @43 :Int8;\n  dpLocale @44 :Text;\n  dpSrLearner @45 :Bool;\n  dpSrCustom @46 :Float32;\n  dpAppd @47 :Bool;\n  dpMapd @48 :Bool;\n}"
  },
  {
    "path": "cereal/include/c++.capnp",
    "content": "# Copyright (c) 2013-2014 Sandstorm Development Group, Inc. and contributors\n# Licensed under the MIT License:\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\n@0xbdf87d7bb8304e81;\n$namespace(\"capnp::annotations\");\n\nannotation namespace(file): Text;\nannotation name(field, enumerant, struct, enum, interface, method, param, group, union): Text;\n"
  },
  {
    "path": "cereal/include/java.capnp",
    "content": "# Copyright (c) 2013-2015 Sandstorm Development Group, Inc. and contributors\n# Licensed under the MIT License:\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\n@0xc5f1af96651f70ea;\n\nannotation package @0x9ee4c8f803b3b596 (file) : Text;\n# Name of the package, such as \"org.example.foo\", in which the generated code will reside.\n\nannotation outerClassname @0x9b066bb4881f7cd3 (file) : Text;\n# Name of the outer class that will wrap the generated code.\n"
  },
  {
    "path": "cereal/legacy.capnp",
    "content": "using Cxx = import \"./include/c++.capnp\";\n$Cxx.namespace(\"cereal\");\n\nusing Java = import \"./include/java.capnp\";\n$Java.package(\"ai.comma.openpilot.cereal\");\n$Java.outerClassname(\"Legacy\");\n\n@0x80ef1ec4889c2a63;\n\n# legacy.capnp: a home for deprecated structs\n\nstruct LogRotate @0x9811e1f38f62f2d1 {\n  segmentNum @0 :Int32;\n  path @1 :Text;\n}\n\nstruct LiveUI @0xc08240f996aefced {\n  rearViewCam @0 :Bool;\n  alertText1 @1 :Text;\n  alertText2 @2 :Text;\n  awarenessStatus @3 :Float32;\n}\n\nstruct UiLayoutState @0x88dcce08ad29dda0 {\n  activeApp @0 :App;\n  sidebarCollapsed @1 :Bool;\n  mapEnabled @2 :Bool;\n  mockEngaged @3 :Bool;\n\n  enum App @0x9917470acf94d285 {\n    home @0;\n    music @1;\n    nav @2;\n    settings @3;\n    none @4;\n  }\n}\n\nstruct OrbslamCorrection @0x8afd33dc9b35e1aa {\n  correctionMonoTime @0 :UInt64;\n  prePositionECEF @1 :List(Float64);\n  postPositionECEF @2 :List(Float64);\n  prePoseQuatECEF @3 :List(Float32);\n  postPoseQuatECEF @4 :List(Float32);\n  numInliers @5 :UInt32;\n}\n\nstruct EthernetPacket @0xa99a9d5b33cf5859 {\n  pkt @0 :Data;\n  ts @1 :Float32;\n}\n\nstruct CellInfo @0xcff7566681c277ce {\n  timestamp @0 :UInt64;\n  repr @1 :Text; # android toString() for now\n}\n\nstruct WifiScan @0xd4df5a192382ba0b {\n  bssid @0 :Text;\n  ssid @1 :Text;\n  capabilities @2 :Text;\n  frequency @3 :Int32;\n  level @4 :Int32;\n  timestamp @5 :Int64;\n\n  centerFreq0 @6 :Int32;\n  centerFreq1 @7 :Int32;\n  channelWidth @8 :ChannelWidth;\n  operatorFriendlyName @9 :Text;\n  venueName @10 :Text;\n  is80211mcResponder @11 :Bool;\n  passpoint @12 :Bool;\n\n  distanceCm @13 :Int32;\n  distanceSdCm @14 :Int32;\n\n  enum ChannelWidth @0xcb6a279f015f6b51 {\n    w20Mhz @0;\n    w40Mhz @1;\n    w80Mhz @2;\n    w160Mhz @3;\n    w80Plus80Mhz @4;\n  }\n}\n\nstruct LiveEventData @0x94b7baa90c5c321e {\n  name @0 :Text;\n  value @1 :Int32;\n}\n\nstruct ModelData @0xb8aad62cffef28a9 {\n  frameId @0 :UInt32;\n  frameAge @12 :UInt32;\n  frameDropPerc @13 :Float32;\n  timestampEof @9 :UInt64;\n  modelExecutionTime @14 :Float32;\n  gpuExecutionTime @16 :Float32;\n  rawPred @15 :Data;\n\n  path @1 :PathData;\n  leftLane @2 :PathData;\n  rightLane @3 :PathData;\n  lead @4 :LeadData;\n  freePath @6 :List(Float32);\n\n  settings @5 :ModelSettings;\n  leadFuture @7 :LeadData;\n  speed @8 :List(Float32);\n  meta @10 :MetaData;\n  longitudinal @11 :LongitudinalData;\n\n  struct PathData @0x8817eeea389e9f08 {\n    points @0 :List(Float32);\n    prob @1 :Float32;\n    std @2 :Float32;\n    stds @3 :List(Float32);\n    poly @4 :List(Float32);\n    validLen @5 :Float32;\n  }\n\n  struct LeadData @0xd1c9bef96d26fa91 {\n    dist @0 :Float32;\n    prob @1 :Float32;\n    std @2 :Float32;\n    relVel @3 :Float32;\n    relVelStd @4 :Float32;\n    relY @5 :Float32;\n    relYStd @6 :Float32;\n    relA @7 :Float32;\n    relAStd @8 :Float32;\n  }\n\n  struct ModelSettings @0xa26e3710efd3e914 {\n    bigBoxX @0 :UInt16;\n    bigBoxY @1 :UInt16;\n    bigBoxWidth @2 :UInt16;\n    bigBoxHeight @3 :UInt16;\n    boxProjection @4 :List(Float32);\n    yuvCorrection @5 :List(Float32);\n    inputTransform @6 :List(Float32);\n  }\n\n  struct MetaData @0x9744f25fb60f2bf8 {\n    engagedProb @0 :Float32;\n    desirePrediction @1 :List(Float32);\n    brakeDisengageProb @2 :Float32;\n    gasDisengageProb @3 :Float32;\n    steerOverrideProb @4 :Float32;\n    desireState @5 :List(Float32);\n  }\n\n  struct LongitudinalData @0xf98f999c6a071122 {\n    distances @2 :List(Float32);\n    speeds @0 :List(Float32);\n    accelerations @1 :List(Float32);\n  }\n}\n\nstruct ECEFPoint @0xc25bbbd524983447 {\n  x @0 :Float64;\n  y @1 :Float64;\n  z @2 :Float64;\n}\n\nstruct ECEFPointDEPRECATED @0xe10e21168db0c7f7 {\n  x @0 :Float32;\n  y @1 :Float32;\n  z @2 :Float32;\n}\n\nstruct GPSPlannerPoints @0xab54c59699f8f9f3 {\n  curPosDEPRECATED @0 :ECEFPointDEPRECATED;\n  pointsDEPRECATED @1 :List(ECEFPointDEPRECATED);\n  curPos @6 :ECEFPoint;\n  points @7 :List(ECEFPoint);\n  valid @2 :Bool;\n  trackName @3 :Text;\n  speedLimit @4 :Float32;\n  accelTarget @5 :Float32;\n}\n\nstruct GPSPlannerPlan @0xf5ad1d90cdc1dd6b {\n  valid @0 :Bool;\n  poly @1 :List(Float32);\n  trackName @2 :Text;\n  speed @3 :Float32;\n  acceleration @4 :Float32;\n  pointsDEPRECATED @5 :List(ECEFPointDEPRECATED);\n  points @6 :List(ECEFPoint);\n  xLookahead @7 :Float32;\n}\n\nstruct UiNavigationEvent @0x90c8426c3eaddd3b {\n  type @0: Type;\n  status @1: Status;\n  distanceTo @2: Float32;\n  endRoadPointDEPRECATED @3: ECEFPointDEPRECATED;\n  endRoadPoint @4: ECEFPoint;\n\n  enum Type @0xe8db07dcf8fcea05 {\n    none @0;\n    laneChangeLeft @1;\n    laneChangeRight @2;\n    mergeLeft @3;\n    mergeRight @4;\n    turnLeft @5;\n    turnRight @6;\n  }\n\n  enum Status @0xb9aa88c75ef99a1f {\n    none @0;\n    passive @1;\n    approaching @2;\n    active @3;\n  }\n}\n\nstruct LiveLocationData @0xb99b2bc7a57e8128 {\n  status @0 :UInt8;\n\n  # 3D fix\n  lat @1 :Float64;\n  lon @2 :Float64;\n  alt @3 :Float32;     # m\n\n  # speed\n  speed @4 :Float32;   # m/s\n\n  # NED velocity components\n  vNED @5 :List(Float32);\n\n  # roll, pitch, heading (x,y,z)\n  roll @6 :Float32;     # WRT to center of earth?\n  pitch @7 :Float32;    # WRT to center of earth?\n  heading @8 :Float32;  # WRT to north?\n\n  # what are these?\n  wanderAngle @9 :Float32;\n  trackAngle @10 :Float32;\n\n  # car frame -- https://upload.wikimedia.org/wikipedia/commons/f/f5/RPY_angles_of_cars.png\n\n  # gyro, in car frame, deg/s\n  gyro @11 :List(Float32);\n\n  # accel, in car frame, m/s^2\n  accel @12 :List(Float32);\n\n  accuracy @13 :Accuracy;\n\n  source @14 :SensorSource;\n  # if we are fixing a location in the past\n  fixMonoTime @15 :UInt64;\n\n  gpsWeek @16 :Int32;\n  timeOfWeek @17 :Float64;\n\n  positionECEF @18 :List(Float64);\n  poseQuatECEF @19 :List(Float32);\n  pitchCalibration @20 :Float32;\n  yawCalibration @21 :Float32;\n  imuFrame @22 :List(Float32);\n\n  struct Accuracy @0x943dc4625473b03f {\n    pNEDError @0 :List(Float32);\n    vNEDError @1 :List(Float32);\n    rollError @2 :Float32;\n    pitchError @3 :Float32;\n    headingError @4 :Float32;\n    ellipsoidSemiMajorError @5 :Float32;\n    ellipsoidSemiMinorError @6 :Float32;\n    ellipsoidOrientationError @7 :Float32;\n  }\n\n  enum SensorSource @0xc871d3cc252af657 {\n    applanix @0;\n    kalman @1;\n    orbslam @2;\n    timing @3;\n    dummy @4;\n  }\n}\n\nstruct OrbOdometry @0xd7700859ed1f5b76 {\n  # timing first\n  startMonoTime @0 :UInt64;\n  endMonoTime @1 :UInt64;\n\n  # fundamental matrix and error\n  f @2: List(Float64);\n  err @3: Float64;\n\n  # number of inlier points\n  inliers @4: Int32;\n\n  # for debug only\n  # indexed by endMonoTime features\n  # value is startMonoTime feature match\n  # -1 if no match\n  matches @5: List(Int16);\n}\n\nstruct OrbFeatures @0xcd60164a8a0159ef {\n  timestampEof @0 :UInt64;\n  # transposed arrays of normalized image coordinates\n  # len(xs) == len(ys) == len(descriptors) * 32\n  xs @1 :List(Float32);\n  ys @2 :List(Float32);\n  descriptors @3 :Data;\n  octaves @4 :List(Int8);\n\n  # match index to last OrbFeatures\n  # -1 if no match\n  timestampLastEof @5 :UInt64;\n  matches @6: List(Int16);\n}\n\nstruct OrbFeaturesSummary @0xd500d30c5803fa4f {\n  timestampEof @0 :UInt64;\n  timestampLastEof @1 :UInt64;\n\n  featureCount @2 :UInt16;\n  matchCount @3 :UInt16;\n  computeNs @4 :UInt64;\n}\n\nstruct OrbKeyFrame @0xc8233c0345e27e24 {\n  # this is a globally unique id for the KeyFrame\n  id @0: UInt64;\n\n  # this is the location of the KeyFrame\n  pos @1: ECEFPoint;\n\n  # these are the features in the world\n  # len(dpos) == len(descriptors) * 32\n  dpos @2 :List(ECEFPoint);\n  descriptors @3 :Data;\n}\n\nstruct KalmanOdometry @0x92e21bb7ea38793a {\n  trans @0 :List(Float32); # m/s in device frame\n  rot @1 :List(Float32); # rad/s in device frame\n  transStd @2 :List(Float32); # std m/s in device frame\n  rotStd @3 :List(Float32); # std rad/s in device frame\n}\n\nstruct OrbObservation @0x9b326d4e436afec7 {\n  observationMonoTime @0 :UInt64;\n  normalizedCoordinates @1 :List(Float32);\n  locationECEF @2 :List(Float64);\n  matchDistance @3: UInt32;\n}\n\nstruct CalibrationFeatures @0x8fdfadb254ea867a {\n  frameId @0 :UInt32;\n\n  p0 @1 :List(Float32);\n  p1 @2 :List(Float32);\n  status @3 :List(Int8);\n}\n\nstruct NavStatus @0xbd8822120928120c {\n  isNavigating @0 :Bool;\n  currentAddress @1 :Address;\n\n  struct Address @0xce7cd672cacc7814 {\n    title @0 :Text;\n    lat @1 :Float64;\n    lng @2 :Float64;\n    house @3 :Text;\n    address @4 :Text;\n    street @5 :Text;\n    city @6 :Text;\n    state @7 :Text;\n    country @8 :Text;\n  }\n}\n\nstruct NavUpdate @0xdb98be6565516acb {\n  isNavigating @0 :Bool;\n  curSegment @1 :Int32;\n  segments @2 :List(Segment);\n\n  struct LatLng @0x9eaef9187cadbb9b {\n    lat @0 :Float64;\n    lng @1 :Float64;\n  }\n\n  struct Segment @0xa5b39b4fc4d7da3f {\n    from @0 :LatLng;\n    to @1 :LatLng;\n    updateTime @2 :Int32;\n    distance @3 :Int32;\n    crossTime @4 :Int32;\n    exitNo @5 :Int32;\n    instruction @6 :Instruction;\n\n    parts @7 :List(LatLng);\n\n    enum Instruction @0xc5417a637451246f {\n      turnLeft @0;\n      turnRight @1;\n      keepLeft @2;\n      keepRight @3;\n      straight @4;\n      roundaboutExitNumber @5;\n      roundaboutExit @6;\n      roundaboutTurnLeft @7;\n      unkn8 @8;\n      roundaboutStraight @9;\n      unkn10 @10;\n      roundaboutTurnRight @11;\n      unkn12 @12;\n      roundaboutUturn @13;\n      unkn14 @14;\n      arrive @15;\n      exitLeft @16;\n      exitRight @17;\n      unkn18 @18;\n      uturn @19;\n      # ...\n    }\n  }\n}\n\nstruct TrafficEvent @0xacfa74a094e62626 {\n  type @0 :Type;\n  distance @1 :Float32;\n  action @2 :Action;\n  resuming @3 :Bool;\n\n  enum Type @0xd85d75253435bf4b {\n    stopSign @0;\n    lightRed @1;\n    lightYellow @2;\n    lightGreen @3;\n    stopLight @4;\n  }\n\n  enum Action @0xa6f6ce72165ccb49 {\n    none @0;\n    yield @1;\n    stop @2;\n    resumeReady @3;\n  }\n\n}\n\n\nstruct AndroidGnss @0xdfdf30d03fc485bd {\n  union {\n    measurements @0 :Measurements;\n    navigationMessage @1 :NavigationMessage;\n  }\n\n  struct Measurements @0xa20710d4f428d6cd {\n    clock @0 :Clock;\n    measurements @1 :List(Measurement);\n\n    struct Clock @0xa0e27b453a38f450 {\n      timeNanos @0 :Int64;\n      hardwareClockDiscontinuityCount @1 :Int32;\n\n      hasTimeUncertaintyNanos @2 :Bool;\n      timeUncertaintyNanos @3 :Float64;\n\n      hasLeapSecond @4 :Bool;\n      leapSecond @5 :Int32;\n\n      hasFullBiasNanos @6 :Bool;\n      fullBiasNanos @7 :Int64;\n\n      hasBiasNanos @8 :Bool;\n      biasNanos @9 :Float64;\n\n      hasBiasUncertaintyNanos @10 :Bool;\n      biasUncertaintyNanos @11 :Float64;\n\n      hasDriftNanosPerSecond @12 :Bool;\n      driftNanosPerSecond @13 :Float64;\n\n      hasDriftUncertaintyNanosPerSecond @14 :Bool;\n      driftUncertaintyNanosPerSecond @15 :Float64;\n    }\n\n    struct Measurement @0xd949bf717d77614d {\n      svId @0 :Int32;\n      constellation @1 :Constellation;\n\n      timeOffsetNanos @2 :Float64;\n      state @3 :Int32;\n      receivedSvTimeNanos @4 :Int64;\n      receivedSvTimeUncertaintyNanos @5 :Int64;\n      cn0DbHz @6 :Float64;\n      pseudorangeRateMetersPerSecond @7 :Float64;\n      pseudorangeRateUncertaintyMetersPerSecond @8 :Float64;\n      accumulatedDeltaRangeState @9 :Int32;\n      accumulatedDeltaRangeMeters @10 :Float64;\n      accumulatedDeltaRangeUncertaintyMeters @11 :Float64;\n\n      hasCarrierFrequencyHz @12 :Bool;\n      carrierFrequencyHz @13 :Float32;\n      hasCarrierCycles @14 :Bool;\n      carrierCycles @15 :Int64;\n      hasCarrierPhase @16 :Bool;\n      carrierPhase @17 :Float64;\n      hasCarrierPhaseUncertainty @18 :Bool;\n      carrierPhaseUncertainty @19 :Float64;\n      hasSnrInDb @20 :Bool;\n      snrInDb @21 :Float64;\n\n      multipathIndicator @22 :MultipathIndicator;\n\n      enum Constellation @0x9ef1f3ff0deb5ffb {\n        unknown @0;\n        gps @1;\n        sbas @2;\n        glonass @3;\n        qzss @4;\n        beidou @5;\n        galileo @6;\n      }\n\n      enum State @0xcbb9490adce12d72 {\n        unknown @0;\n        codeLock @1;\n        bitSync @2;\n        subframeSync @3;\n        towDecoded @4;\n        msecAmbiguous @5;\n        symbolSync @6;\n        gloStringSync @7;\n        gloTodDecoded @8;\n        bdsD2BitSync @9;\n        bdsD2SubframeSync @10;\n        galE1bcCodeLock @11;\n        galE1c2ndCodeLock @12;\n        galE1bPageSync @13;\n        sbasSync @14;\n      }\n\n      enum MultipathIndicator @0xc04e7b6231d4caa8 {\n        unknown @0;\n        detected @1;\n        notDetected @2;\n      }\n    }\n  }\n\n  struct NavigationMessage @0xe2517b083095fd4e {\n    type @0 :Int32;\n    svId @1 :Int32;\n    messageId @2 :Int32;\n    submessageId @3 :Int32;\n    data @4 :Data;\n    status @5 :Status;\n\n    enum Status @0xec1ff7996b35366f {\n      unknown @0;\n      parityPassed @1;\n      parityRebuilt @2;\n    }\n  }\n}\n\nstruct QcomGnss @0xde94674b07ae51c1 {\n  logTs @0 :UInt64;\n  union {\n    measurementReport @1 :MeasurementReport;\n    clockReport @2 :ClockReport;\n    drMeasurementReport @3 :DrMeasurementReport;\n    drSvPoly @4 :DrSvPolyReport;\n    rawLog @5 :Data;\n  }\n\n  enum MeasurementSource @0xd71a12b6faada7ee {\n    gps @0;\n    glonass @1;\n    beidou @2;\n  }\n\n  enum SVObservationState @0xe81e829a0d6c83e9 {\n    idle @0;\n    search @1;\n    searchVerify @2;\n    bitEdge @3;\n    trackVerify @4;\n    track @5;\n    restart @6;\n    dpo @7;\n    glo10msBe @8;\n    glo10msAt @9;\n  }\n\n  struct MeasurementStatus @0xe501010e1bcae83b {\n    subMillisecondIsValid @0 :Bool;\n    subBitTimeIsKnown @1 :Bool;\n    satelliteTimeIsKnown @2 :Bool;\n    bitEdgeConfirmedFromSignal @3 :Bool;\n    measuredVelocity @4 :Bool;\n    fineOrCoarseVelocity @5 :Bool;\n    lockPointValid @6 :Bool;\n    lockPointPositive @7 :Bool;\n    lastUpdateFromDifference @8 :Bool;\n    lastUpdateFromVelocityDifference @9 :Bool;\n    strongIndicationOfCrossCorelation @10 :Bool;\n    tentativeMeasurement @11 :Bool;\n    measurementNotUsable @12 :Bool;\n    sirCheckIsNeeded @13 :Bool;\n    probationMode @14 :Bool;\n\n    glonassMeanderBitEdgeValid @15 :Bool;\n    glonassTimeMarkValid @16 :Bool;\n\n    gpsRoundRobinRxDiversity @17 :Bool;\n    gpsRxDiversity @18 :Bool;\n    gpsLowBandwidthRxDiversityCombined @19 :Bool;\n    gpsHighBandwidthNu4 @20 :Bool;\n    gpsHighBandwidthNu8 @21 :Bool;\n    gpsHighBandwidthUniform @22 :Bool;\n    multipathIndicator @23 :Bool;\n\n    imdJammingIndicator @24 :Bool;\n    lteB13TxJammingIndicator @25 :Bool;\n    freshMeasurementIndicator @26 :Bool;\n\n    multipathEstimateIsValid @27 :Bool;\n    directionIsValid @28 :Bool;\n  }\n\n  struct MeasurementReport @0xf580d7d86b7b8692 {\n    source @0 :MeasurementSource;\n\n    fCount @1 :UInt32;\n\n    gpsWeek @2 :UInt16;\n    glonassCycleNumber @3 :UInt8;\n    glonassNumberOfDays @4 :UInt16;\n\n    milliseconds @5 :UInt32;\n    timeBias @6 :Float32;\n    clockTimeUncertainty @7 :Float32;\n    clockFrequencyBias @8 :Float32;\n    clockFrequencyUncertainty @9 :Float32;\n\n    sv @10 :List(SV);\n\n    struct SV @0xf10c595ae7bb2c27 {\n      svId @0 :UInt8;\n      observationState @2 :SVObservationState;\n      observations @3 :UInt8;\n      goodObservations @4 :UInt8;\n      gpsParityErrorCount @5 :UInt16;\n      glonassFrequencyIndex @1 :Int8;\n      glonassHemmingErrorCount @6 :UInt8;\n      filterStages @7 :UInt8;\n      carrierNoise @8 :UInt16;\n      latency @9 :Int16;\n      predetectInterval @10 :UInt8;\n      postdetections @11 :UInt16;\n\n      unfilteredMeasurementIntegral @12 :UInt32;\n      unfilteredMeasurementFraction @13 :Float32;\n      unfilteredTimeUncertainty @14 :Float32;\n      unfilteredSpeed @15 :Float32;\n      unfilteredSpeedUncertainty @16 :Float32;\n      measurementStatus @17 :MeasurementStatus;\n      multipathEstimate @18 :UInt32;\n      azimuth @19 :Float32;\n      elevation @20 :Float32;\n      carrierPhaseCyclesIntegral @21 :Int32;\n      carrierPhaseCyclesFraction @22 :UInt16;\n      fineSpeed @23 :Float32;\n      fineSpeedUncertainty @24 :Float32;\n      cycleSlipCount @25 :UInt8;\n    }\n\n  }\n\n  struct ClockReport @0xca965e4add8f4f0b {\n    hasFCount @0 :Bool;\n    fCount @1 :UInt32;\n\n    hasGpsWeek @2 :Bool;\n    gpsWeek @3 :UInt16;\n    hasGpsMilliseconds @4 :Bool;\n    gpsMilliseconds @5 :UInt32;\n    gpsTimeBias @6 :Float32;\n    gpsClockTimeUncertainty @7 :Float32;\n    gpsClockSource @8 :UInt8;\n\n    hasGlonassYear @9 :Bool;\n    glonassYear @10 :UInt8;\n    hasGlonassDay @11 :Bool;\n    glonassDay @12 :UInt16;\n    hasGlonassMilliseconds @13 :Bool;\n    glonassMilliseconds @14 :UInt32;\n    glonassTimeBias @15 :Float32;\n    glonassClockTimeUncertainty @16 :Float32;\n    glonassClockSource @17 :UInt8;\n\n    bdsWeek @18 :UInt16;\n    bdsMilliseconds @19 :UInt32;\n    bdsTimeBias @20 :Float32;\n    bdsClockTimeUncertainty @21 :Float32;\n    bdsClockSource @22 :UInt8;\n\n    galWeek @23 :UInt16;\n    galMilliseconds @24 :UInt32;\n    galTimeBias @25 :Float32;\n    galClockTimeUncertainty @26 :Float32;\n    galClockSource @27 :UInt8;\n\n    clockFrequencyBias @28 :Float32;\n    clockFrequencyUncertainty @29 :Float32;\n    frequencySource @30 :UInt8;\n    gpsLeapSeconds @31 :UInt8;\n    gpsLeapSecondsUncertainty @32 :UInt8;\n    gpsLeapSecondsSource @33 :UInt8;\n\n    gpsToGlonassTimeBiasMilliseconds @34 :Float32;\n    gpsToGlonassTimeBiasMillisecondsUncertainty @35 :Float32;\n    gpsToBdsTimeBiasMilliseconds @36 :Float32;\n    gpsToBdsTimeBiasMillisecondsUncertainty @37 :Float32;\n    bdsToGloTimeBiasMilliseconds @38 :Float32;\n    bdsToGloTimeBiasMillisecondsUncertainty @39 :Float32;\n    gpsToGalTimeBiasMilliseconds @40 :Float32;\n    gpsToGalTimeBiasMillisecondsUncertainty @41 :Float32;\n    galToGloTimeBiasMilliseconds @42 :Float32;\n    galToGloTimeBiasMillisecondsUncertainty @43 :Float32;\n    galToBdsTimeBiasMilliseconds @44 :Float32;\n    galToBdsTimeBiasMillisecondsUncertainty @45 :Float32;\n\n    hasRtcTime @46 :Bool;\n    systemRtcTime @47 :UInt32;\n    fCountOffset @48 :UInt32;\n    lpmRtcCount @49 :UInt32;\n    clockResets @50 :UInt32;\n  }\n\n  struct DrMeasurementReport @0x8053c39445c6c75c {\n\n    reason @0 :UInt8;\n    seqNum @1 :UInt8;\n    seqMax @2 :UInt8;\n    rfLoss @3 :UInt16;\n\n    systemRtcValid @4 :Bool;\n    fCount @5 :UInt32;\n    clockResets @6 :UInt32;\n    systemRtcTime @7 :UInt64;\n\n    gpsLeapSeconds @8 :UInt8;\n    gpsLeapSecondsUncertainty @9 :UInt8;\n    gpsToGlonassTimeBiasMilliseconds @10 :Float32;\n    gpsToGlonassTimeBiasMillisecondsUncertainty @11 :Float32;\n\n    gpsWeek @12 :UInt16;\n    gpsMilliseconds @13 :UInt32;\n    gpsTimeBiasMs @14 :UInt32;\n    gpsClockTimeUncertaintyMs @15 :UInt32;\n    gpsClockSource @16 :UInt8;\n\n    glonassClockSource @17 :UInt8;\n    glonassYear @18 :UInt8;\n    glonassDay @19 :UInt16;\n    glonassMilliseconds @20 :UInt32;\n    glonassTimeBias @21 :Float32;\n    glonassClockTimeUncertainty @22 :Float32;\n\n    clockFrequencyBias @23 :Float32;\n    clockFrequencyUncertainty @24 :Float32;\n    frequencySource @25 :UInt8;\n\n    source @26 :MeasurementSource;\n\n    sv @27 :List(SV);\n\n    struct SV @0xf08b81df8cbf459c {\n      svId @0 :UInt8;\n      glonassFrequencyIndex @1 :Int8;\n      observationState @2 :SVObservationState;\n      observations @3 :UInt8;\n      goodObservations @4 :UInt8;\n      filterStages @5 :UInt8;\n      predetectInterval @6 :UInt8;\n      cycleSlipCount @7 :UInt8;\n      postdetections @8 :UInt16;\n\n      measurementStatus @9 :MeasurementStatus;\n\n      carrierNoise @10 :UInt16;\n      rfLoss @11 :UInt16;\n      latency @12 :Int16;\n\n      filteredMeasurementFraction @13 :Float32;\n      filteredMeasurementIntegral @14 :UInt32;\n      filteredTimeUncertainty @15 :Float32;\n      filteredSpeed @16 :Float32;\n      filteredSpeedUncertainty @17 :Float32;\n\n      unfilteredMeasurementFraction @18 :Float32;\n      unfilteredMeasurementIntegral @19 :UInt32;\n      unfilteredTimeUncertainty @20 :Float32;\n      unfilteredSpeed @21 :Float32;\n      unfilteredSpeedUncertainty @22 :Float32;\n\n      multipathEstimate @23 :UInt32;\n      azimuth @24 :Float32;\n      elevation @25 :Float32;\n      dopplerAcceleration @26 :Float32;\n      fineSpeed @27 :Float32;\n      fineSpeedUncertainty @28 :Float32;\n\n      carrierPhase @29 :Float64;\n      fCount @30 :UInt32;\n\n      parityErrorCount @31 :UInt16;\n      goodParity @32 :Bool;\n    }\n  }\n\n  struct DrSvPolyReport @0xb1fb80811a673270 {\n    svId @0 :UInt16;\n    frequencyIndex @1 :Int8;\n\n    hasPosition @2 :Bool;\n    hasIono @3 :Bool;\n    hasTropo @4 :Bool;\n    hasElevation @5 :Bool;\n    polyFromXtra @6 :Bool;\n    hasSbasIono @7 :Bool;\n\n    iode @8 :UInt16;\n    t0 @9 :Float64;\n    xyz0 @10 :List(Float64);\n    xyzN @11 :List(Float64);\n    other @12 :List(Float32);\n\n    positionUncertainty @13 :Float32;\n    ionoDelay @14 :Float32;\n    ionoDot @15 :Float32;\n    sbasIonoDelay @16 :Float32;\n    sbasIonoDot @17 :Float32;\n    tropoDelay @18 :Float32;\n    elevation @19 :Float32;\n    elevationDot @20 :Float32;\n    elevationUncertainty @21 :Float32;\n    velocityCoeff @22 :List(Float64);\n  }\n}\n\nstruct LidarPts @0xe3d6685d4e9d8f7a {\n  r @0 :List(UInt16);        # uint16   m*500.0\n  theta @1 :List(UInt16);    # uint16 deg*100.0\n  reflect @2 :List(UInt8);   # uint8      0-255\n\n  # For storing out of file.\n  idx @3 :UInt64;\n\n  # For storing in file\n  pkt @4 :Data;\n}\n\n\n"
  },
  {
    "path": "cereal/log.capnp",
    "content": "using Cxx = import \"./include/c++.capnp\";\n$Cxx.namespace(\"cereal\");\n\nusing Java = import \"./include/java.capnp\";\n$Java.package(\"ai.comma.openpilot.cereal\");\n$Java.outerClassname(\"Log\");\n\nusing Car = import \"car.capnp\";\nusing Legacy = import \"legacy.capnp\";\nusing Dp = import \"dp.capnp\";\n\n@0xf3b1f17e25a4285b;\n\nconst logVersion :Int32 = 1;\n\nstruct Map(Key, Value) {\n  entries @0 :List(Entry);\n  struct Entry {\n    key @0 :Key;\n    value @1 :Value;\n  }\n}\n\nstruct InitData {\n  kernelArgs @0 :List(Text);\n  kernelVersion @15 :Text;\n  osVersion @18 :Text;\n\n  gctx @1 :Text;\n  dongleId @2 :Text;\n\n  deviceType @3 :DeviceType;\n  version @4 :Text;\n  gitCommit @10 :Text;\n  gitBranch @11 :Text;\n  gitRemote @13 :Text;\n\n  androidProperties @16 :Map(Text, Text);\n\n  pandaInfo @8 :PandaInfo;\n\n  dirty @9 :Bool;\n  passive @12 :Bool;\n  params @17 :Map(Text, Data);\n\n  enum DeviceType {\n    unknown @0;\n    neo @1;\n    chffrAndroid @2;\n    chffrIos @3;\n    tici @4;\n    pc @5;\n    jetson @6;\n  }\n\n  struct PandaInfo {\n    hasPanda @0 :Bool;\n    dongleId @1 :Text;\n    stVersion @2 :Text;\n    espVersion @3 :Text;\n  }\n\n  # ***** deprecated stuff *****\n  androidBuildInfo @5 :AndroidBuildInfo;\n  androidSensorsDEPRECATED @6 :List(AndroidSensor);\n  chffrAndroidExtraDEPRECATED @7 :ChffrAndroidExtra;\n  iosBuildInfoDEPRECATED @14 :IosBuildInfo;\n\n  struct AndroidBuildInfo {\n    board @0 :Text;\n    bootloader @1 :Text;\n    brand @2 :Text;\n    device @3 :Text;\n    display @4 :Text;\n    fingerprint @5 :Text;\n    hardware @6 :Text;\n    host @7 :Text;\n    id @8 :Text;\n    manufacturer @9 :Text;\n    model @10 :Text;\n    product @11 :Text;\n    radioVersion @12 :Text;\n    serial @13 :Text;\n    supportedAbis @14 :List(Text);\n    tags @15 :Text;\n    time @16 :Int64;\n    type @17 :Text;\n    user @18 :Text;\n\n    versionCodename @19 :Text;\n    versionRelease @20 :Text;\n    versionSdk @21 :Int32;\n    versionSecurityPatch @22 :Text;\n  }\n\n  struct AndroidSensor {\n    id @0 :Int32;\n    name @1 :Text;\n    vendor @2 :Text;\n    version @3 :Int32;\n    handle @4 :Int32;\n    type @5 :Int32;\n    maxRange @6 :Float32;\n    resolution @7 :Float32;\n    power @8 :Float32;\n    minDelay @9 :Int32;\n    fifoReservedEventCount @10 :UInt32;\n    fifoMaxEventCount @11 :UInt32;\n    stringType @12 :Text;\n    maxDelay @13 :Int32;\n  }\n\n  struct ChffrAndroidExtra {\n    allCameraCharacteristics @0 :Map(Text, Text);\n  }\n\n  struct IosBuildInfo {\n    appVersion @0 :Text;\n    appBuild @1 :UInt32;\n    osVersion @2 :Text;\n    deviceModel @3 :Text;\n  }\n}\n\nstruct FrameData {\n  frameId @0 :UInt32;\n  encodeId @1 :UInt32; # DEPRECATED\n\n  frameType @7 :FrameType;\n  frameLength @3 :Int32;\n\n  # Timestamps\n  timestampEof @2 :UInt64;\n  timestampSof @8 :UInt64;\n\n  # Exposure\n  integLines @4 :Int32;\n  highConversionGain @20 :Bool;\n  gain @15 :Float32; # This includes highConversionGain if enabled\n  measuredGreyFraction @21 :Float32;\n  targetGreyFraction @22 :Float32;\n\n  # Focus\n  lensPos @11 :Int32;\n  lensSag @12 :Float32;\n  lensErr @13 :Float32;\n  lensTruePos @14 :Float32;\n  focusVal @16 :List(Int16);\n  focusConf @17 :List(UInt8);\n  sharpnessScore @18 :List(UInt16);\n  recoverState @19 :Int32;\n\n  transform @10 :List(Float32);\n\n  androidCaptureResult @9 :AndroidCaptureResult;\n\n  image @6 :Data;\n  globalGainDEPRECATED @5 :Int32;\n\n  enum FrameType {\n    unknown @0;\n    neo @1;\n    chffrAndroid @2;\n    front @3;\n  }\n\n  struct AndroidCaptureResult {\n    sensitivity @0 :Int32;\n    frameDuration @1 :Int64;\n    exposureTime @2 :Int64;\n    rollingShutterSkew @3 :UInt64;\n    colorCorrectionTransform @4 :List(Int32);\n    colorCorrectionGains @5 :List(Float32);\n    displayRotation @6 :Int8;\n  }\n}\n\nstruct Thumbnail {\n  frameId @0 :UInt32;\n  timestampEof @1 :UInt64;\n  thumbnail @2 :Data;\n}\n\nstruct GPSNMEAData {\n  timestamp @0 :Int64;\n  localWallTime @1 :UInt64;\n  nmea @2 :Text;\n}\n\n# android sensor_event_t\nstruct SensorEventData {\n  version @0 :Int32;\n  sensor @1 :Int32;\n  type @2 :Int32;\n  timestamp @3 :Int64;\n  uncalibratedDEPRECATED @10 :Bool;\n\n  union {\n    acceleration @4 :SensorVec;\n    magnetic @5 :SensorVec;\n    orientation @6 :SensorVec;\n    gyro @7 :SensorVec;\n    pressure @9 :SensorVec;\n    magneticUncalibrated @11 :SensorVec;\n    gyroUncalibrated @12 :SensorVec;\n    proximity @13: Float32;\n    light @14: Float32;\n    temperature @15: Float32;\n  }\n  source @8 :SensorSource;\n\n  struct SensorVec {\n    v @0 :List(Float32);\n    status @1 :Int8;\n  }\n\n  enum SensorSource {\n    android @0;\n    iOS @1;\n    fiber @2;\n    velodyne @3;  # Velodyne IMU\n    bno055 @4;    # Bosch accelerometer\n    lsm6ds3 @5;   # accelerometer (c2)\n    bmp280 @6;    # barometer (c2)\n    mmc3416x @7;  # magnetometer (c2)\n    bmx055 @8;\n    rpr0521 @9;\n    lsm6ds3trc @10;\n    mmc5603nj @11;\n  }\n}\n\n# android struct GpsLocation\nstruct GpsLocationData {\n  # Contains GpsLocationFlags bits.\n  flags @0 :UInt16;\n\n  # Represents latitude in degrees.\n  latitude @1 :Float64;\n\n  # Represents longitude in degrees.\n  longitude @2 :Float64;\n\n  # Represents altitude in meters above the WGS 84 reference ellipsoid.\n  altitude @3 :Float64;\n\n  # Represents speed in meters per second.\n  speed @4 :Float32;\n\n  # Represents heading in degrees.\n  bearingDeg @5 :Float32;\n\n  # Represents expected accuracy in meters. (presumably 1 sigma?)\n  accuracy @6 :Float32;\n\n  # Timestamp for the location fix.\n  # Milliseconds since January 1, 1970.\n  timestamp @7 :Int64;\n\n  source @8 :SensorSource;\n\n  # Represents NED velocity in m/s.\n  vNED @9 :List(Float32);\n\n  # Represents expected vertical accuracy in meters. (presumably 1 sigma?)\n  verticalAccuracy @10 :Float32;\n\n  # Represents bearing accuracy in degrees. (presumably 1 sigma?)\n  bearingAccuracyDeg @11 :Float32;\n\n  # Represents velocity accuracy in m/s. (presumably 1 sigma?)\n  speedAccuracy @12 :Float32;\n\n  enum SensorSource {\n    android @0;\n    iOS @1;\n    car @2;\n    velodyne @3;  # Velodyne IMU\n    fusion @4;\n    external @5;\n    ublox @6;\n    trimble @7;\n  }\n}\n\nstruct CanData {\n  address @0 :UInt32;\n  busTime @1 :UInt16;\n  dat     @2 :Data;\n  src     @3 :UInt8;\n}\n\nstruct DeviceState @0xa4d8b5af2aa492eb {\n  usbOnline @12 :Bool;\n  networkType @22 :NetworkType;\n  networkInfo @31 :NetworkInfo;\n  networkStrength @24 :NetworkStrength;\n  offroadPowerUsageUwh @23 :UInt32;\n  carBatteryCapacityUwh @25 :UInt32;\n\n  fanSpeedPercentDesired @10 :UInt16;\n  started @11 :Bool;\n  startedMonoTime @13 :UInt64;\n\n  lastAthenaPingTime @32 :UInt64;\n\n  # system utilization\n  freeSpacePercent @7 :Float32;\n  memoryUsagePercent @19 :Int8;\n  gpuUsagePercent @33 :Int8;\n  cpuUsagePercent @34 :List(Int8);  # per-core cpu usage\n\n  # power\n  batteryPercent @8 :Int16;\n  batteryCurrent @15 :Int32;\n  chargingError @17 :Bool;\n  chargingDisabled @18 :Bool;\n\n  # device thermals\n  cpuTempC @26 :List(Float32);\n  gpuTempC @27 :List(Float32);\n  memoryTempC @28 :Float32;\n  ambientTempC @30 :Float32;\n  thermalStatus @14 :ThermalStatus;\n\n  enum ThermalStatus {\n    green @0;\n    yellow @1;\n    red @2;\n    danger @3;\n  }\n\n  enum NetworkType {\n    none @0;\n    wifi @1;\n    cell2G @2;\n    cell3G @3;\n    cell4G @4;\n    cell5G @5;\n    ethernet @6;\n  }\n\n  enum NetworkStrength {\n    unknown @0;\n    poor @1;\n    moderate @2;\n    good @3;\n    great @4;\n  }\n\n  struct NetworkInfo {\n    technology @0 :Text;\n    operator @1 :Text;\n    band @2 :Text;\n    channel @3 :UInt16;\n    extra @4 :Text;\n    state @5 :Text;\n  }\n\n  # deprecated\n  cpu0DEPRECATED @0 :UInt16;\n  cpu1DEPRECATED @1 :UInt16;\n  cpu2DEPRECATED @2 :UInt16;\n  cpu3DEPRECATED @3 :UInt16;\n  memDEPRECATED @4 :UInt16;\n  gpuDEPRECATED @5 :UInt16;\n  batDEPRECATED @6 :UInt32;\n  pa0DEPRECATED @21 :UInt16;\n  cpuUsagePercentDEPRECATED @20 :Int8;\n  batteryStatusDEPRECATED @9 :Text;\n  batteryVoltageDEPRECATED @16 :Int32;\n  batteryTempCDEPRECATED @29 :Float32;\n}\n\nstruct PandaState @0xa7649e2575e4591e {\n  # from can health\n  voltage @0 :UInt32;\n  current @1 :UInt32;\n  ignitionLine @2 :Bool;\n  controlsAllowed @3 :Bool;\n  gasInterceptorDetected @4 :Bool;\n  hasGps @6 :Bool;\n  canSendErrs @7 :UInt32;\n  canFwdErrs @8 :UInt32;\n  canRxErrs @19 :UInt32;\n  gmlanSendErrs @9 :UInt32;\n  pandaType @10 :PandaType;\n  fanSpeedRpm @11 :UInt16;\n  usbPowerMode @12 :UsbPowerMode;\n  ignitionCan @13 :Bool;\n  safetyModel @14 :Car.CarParams.SafetyModel;\n  safetyParam @20 :Int16;\n  faultStatus @15 :FaultStatus;\n  powerSaveEnabled @16 :Bool;\n  uptime @17 :UInt32;\n  faults @18 :List(FaultType);\n  harnessStatus @21 :HarnessStatus;\n  heartbeatLost @22 :Bool;\n\n  enum FaultStatus {\n    none @0;\n    faultTemp @1;\n    faultPerm @2;\n  }\n\n  enum FaultType {\n    relayMalfunction @0;\n    unusedInterruptHandled @1;\n    interruptRateCan1 @2;\n    interruptRateCan2 @3;\n    interruptRateCan3 @4;\n    interruptRateTach @5;\n    interruptRateGmlan @6;\n    interruptRateInterrupts @7;\n    interruptRateSpiDma @8;\n    interruptRateSpiCs @9;\n    interruptRateUart1 @10;\n    interruptRateUart2 @11;\n    interruptRateUart3 @12;\n    interruptRateUart5 @13;\n    interruptRateUartDma @14;\n    interruptRateUsb @15;\n    interruptRateTim1 @16;\n    interruptRateTim3 @17;\n    registerDivergent @18;\n    interruptRateKlineInit @19;\n    interruptRateClockSource @20;\n    interruptRateTick @21;\n    # Update max fault type in boardd when adding faults\n  }\n\n  enum PandaType @0x8a58adf93e5b3751 {\n    unknown @0;\n    whitePanda @1;\n    greyPanda @2;\n    blackPanda @3;\n    pedal @4;\n    uno @5;\n    dos @6;\n    redPanda @7;\n  }\n\n  enum UsbPowerMode {\n    none @0;\n    client @1;\n    cdp @2;\n    dcp @3;\n  }\n\n  enum HarnessStatus {\n    notConnected @0;\n    normal @1;\n    flipped @2;\n  }\n\n  startedSignalDetectedDEPRECATED @5 :Bool;\n}\n\nstruct RadarState @0x9a185389d6fdd05f {\n  canMonoTimes @10 :List(UInt64);\n  mdMonoTime @6 :UInt64;\n  carStateMonoTime @11 :UInt64;\n  radarErrors @12 :List(Car.RadarData.Error);\n\n  leadOne @3 :LeadData;\n  leadTwo @4 :LeadData;\n  cumLagMs @5 :Float32;\n\n  struct LeadData {\n    dRel @0 :Float32;\n    yRel @1 :Float32;\n    vRel @2 :Float32;\n    aRel @3 :Float32;\n    vLead @4 :Float32;\n    dPath @6 :Float32;\n    vLat @7 :Float32;\n    vLeadK @8 :Float32;\n    aLeadK @9 :Float32;\n    fcw @10 :Bool;\n    status @11 :Bool;\n    aLeadTau @12 :Float32;\n    modelProb @13 :Float32;\n    radar @14 :Bool;\n\n    aLeadDEPRECATED @5 :Float32;\n  }\n\n  # deprecated\n  ftMonoTimeDEPRECATED @7 :UInt64;\n  warpMatrixDEPRECATED @0 :List(Float32);\n  angleOffsetDEPRECATED @1 :Float32;\n  calStatusDEPRECATED @2 :Int8;\n  calCycleDEPRECATED @8 :Int32;\n  calPercDEPRECATED @9 :Int8;\n}\n\nstruct LiveCalibrationData {\n  calStatus @1 :Int8;\n  calCycle @2 :Int32;\n  calPerc @3 :Int8;\n  validBlocks @9 :Int32;\n\n  # view_frame_from_road_frame\n  # ui's is inversed needs new\n  extrinsicMatrix @4 :List(Float32);\n  # the direction of travel vector in device frame\n  rpyCalib @7 :List(Float32);\n  rpyCalibSpread @8 :List(Float32);\n\n  warpMatrixDEPRECATED @0 :List(Float32);\n  warpMatrix2DEPRECATED @5 :List(Float32);\n  warpMatrixBigDEPRECATED @6 :List(Float32);\n}\n\nstruct LiveTracks {\n  trackId @0 :Int32;\n  dRel @1 :Float32;\n  yRel @2 :Float32;\n  vRel @3 :Float32;\n  aRel @4 :Float32;\n  timeStamp @5 :Float32;\n  status @6 :Float32;\n  currentTime @7 :Float32;\n  stationary @8 :Bool;\n  oncoming @9 :Bool;\n}\n\nstruct ControlsState @0x97ff69c53601abf1 {\n  startMonoTime @48 :UInt64;\n  canMonoTimes @21 :List(UInt64);\n  longitudinalPlanMonoTime @28 :UInt64;\n  lateralPlanMonoTime @50 :UInt64;\n\n  state @31 :OpenpilotState;\n  enabled @19 :Bool;\n  active @36 :Bool;\n\n  longControlState @30 :Car.CarControl.Actuators.LongControlState;\n  vPid @2 :Float32;\n  vTargetLead @3 :Float32;\n  vCruise @22 :Float32;\n  upAccelCmd @4 :Float32;\n  uiAccelCmd @5 :Float32;\n  ufAccelCmd @33 :Float32;\n  aTarget @35 :Float32;\n  curvature @37 :Float32;  # path curvature from vehicle model\n  forceDecel @51 :Bool;\n\n  # UI alerts\n  alertText1 @24 :Text;\n  alertText2 @25 :Text;\n  alertStatus @38 :AlertStatus;\n  alertSize @39 :AlertSize;\n  alertBlinkingRate @42 :Float32;\n  alertType @44 :Text;\n  alertSound @56 :Car.CarControl.HUDControl.AudibleAlert;\n  engageable @41 :Bool;  # can OP be engaged?\n\n  cumLagMs @15 :Float32;\n  canErrorCounter @57 :UInt32;\n\n  lateralControlState :union {\n    indiState @52 :LateralINDIState;\n    pidState @53 :LateralPIDState;\n    lqrState @55 :LateralLQRState;\n    angleState @58 :LateralAngleState;\n    debugState @59 :LateralDebugState;\n  }\n\n  enum OpenpilotState @0xdbe58b96d2d1ac61 {\n    disabled @0;\n    preEnabled @1;\n    enabled @2;\n    softDisabling @3;\n  }\n\n  enum AlertStatus {\n    normal @0;       # low priority alert for user's convenience\n    userPrompt @1;   # mid priority alert that might require user intervention\n    critical @2;     # high priority alert that needs immediate user intervention\n  }\n\n  enum AlertSize {\n    none @0;    # don't display the alert\n    small @1;   # small box\n    mid @2;     # mid screen\n    full @3;    # full screen\n  }\n\n  struct LateralINDIState {\n    active @0 :Bool;\n    steeringAngleDeg @1 :Float32;\n    steeringRateDeg @2 :Float32;\n    steeringAccelDeg @3 :Float32;\n    rateSetPoint @4 :Float32;\n    accelSetPoint @5 :Float32;\n    accelError @6 :Float32;\n    delayedOutput @7 :Float32;\n    delta @8 :Float32;\n    output @9 :Float32;\n    saturated @10 :Bool;\n  }\n\n  struct LateralPIDState {\n    active @0 :Bool;\n    steeringAngleDeg @1 :Float32;\n    steeringRateDeg @2 :Float32;\n    angleError @3 :Float32;\n    p @4 :Float32;\n    i @5 :Float32;\n    f @6 :Float32;\n    output @7 :Float32;\n    saturated @8 :Bool;\n   }\n\n  struct LateralLQRState {\n    active @0 :Bool;\n    steeringAngleDeg @1 :Float32;\n    i @2 :Float32;\n    output @3 :Float32;\n    lqrOutput @4 :Float32;\n    saturated @5 :Bool;\n  }\n\n  struct LateralAngleState {\n    active @0 :Bool;\n    steeringAngleDeg @1 :Float32;\n    output @2 :Float32;\n    saturated @3 :Bool;\n  }\n\n  struct LateralDebugState {\n    active @0 :Bool;\n    steeringAngleDeg @1 :Float32;\n    output @2 :Float32;\n    saturated @3 :Bool;\n  }\n\n  # deprecated\n  vEgoDEPRECATED @0 :Float32;\n  vEgoRawDEPRECATED @32 :Float32;\n  aEgoDEPRECATED @1 :Float32;\n  canMonoTimeDEPRECATED @16 :UInt64;\n  radarStateMonoTimeDEPRECATED @17 :UInt64;\n  mdMonoTimeDEPRECATED @18 :UInt64;\n  yActualDEPRECATED @6 :Float32;\n  yDesDEPRECATED @7 :Float32;\n  upSteerDEPRECATED @8 :Float32;\n  uiSteerDEPRECATED @9 :Float32;\n  ufSteerDEPRECATED @34 :Float32;\n  aTargetMinDEPRECATED @10 :Float32;\n  aTargetMaxDEPRECATED @11 :Float32;\n  rearViewCamDEPRECATED @23 :Bool;\n  driverMonitoringOnDEPRECATED @43 :Bool;\n  hudLeadDEPRECATED @14 :Int32;\n  alertSoundDEPRECATED @45 :Text;\n  angleModelBiasDEPRECATED @27 :Float32;\n  gpsPlannerActiveDEPRECATED @40 :Bool;\n  decelForTurnDEPRECATED @47 :Bool;\n  decelForModelDEPRECATED @54 :Bool;\n  awarenessStatusDEPRECATED @26 :Float32;\n  angleSteers @13 :Float32; # dp\n  vCurvatureDEPRECATED @46 :Float32;\n  mapValidDEPRECATED @49 :Bool;\n  jerkFactorDEPRECATED @12 :Float32;\n  steerOverrideDEPRECATED @20 :Bool;\n  steeringAngleDesiredDeg @29 :Float32; # dp\n}\n\nstruct ModelDataV2 {\n  frameId @0 :UInt32;\n  frameAge @1 :UInt32;\n  frameDropPerc @2 :Float32;\n  timestampEof @3 :UInt64;\n  modelExecutionTime @15 :Float32;\n  gpuExecutionTime @17 :Float32;\n  rawPredictions @16 :Data;\n\n  # predicted future position, orientation, etc..\n  position @4 :XYZTData;\n  orientation @5 :XYZTData;\n  velocity @6 :XYZTData;\n  orientationRate @7 :XYZTData;\n\n  # prediction lanelines and road edges\n  laneLines @8 :List(XYZTData);\n  laneLineProbs @9 :List(Float32);\n  laneLineStds @13 :List(Float32);\n  roadEdges @10 :List(XYZTData);\n  roadEdgeStds @14 :List(Float32);\n\n  # predicted lead cars\n  leads @11 :List(LeadDataV2);\n  leadsV3 @18 :List(LeadDataV3);\n\n  meta @12 :MetaData;\n\n  # All SI units and in device frame\n  struct XYZTData {\n    x @0 :List(Float32);\n    y @1 :List(Float32);\n    z @2 :List(Float32);\n    t @3 :List(Float32);\n    xStd @4 :List(Float32);\n    yStd @5 :List(Float32);\n    zStd @6 :List(Float32);\n  }\n\n  struct LeadDataV2 {\n    prob @0 :Float32; # probability that car is your lead at time t\n    t @1 :Float32;\n\n    # x and y are relative position in device frame\n    # v is norm relative speed\n    # a is norm relative acceleration\n    xyva @2 :List(Float32);\n    xyvaStd @3 :List(Float32);\n  }\n\n  struct LeadDataV3 {\n    prob @0 :Float32; # probability that car is your lead at time t\n    probTime @1 :Float32;\n    t @2 :List(Float32);\n\n    # x and y are relative position in device frame\n    # v absolute norm speed\n    # a is derivative of v\n    x @3 :List(Float32);\n    xStd @4 :List(Float32);\n    y @5 :List(Float32);\n    yStd @6 :List(Float32);\n    v @7 :List(Float32);\n    vStd @8 :List(Float32);\n    a @9 :List(Float32);\n    aStd @10 :List(Float32);\n  }\n\n\n  struct MetaData {\n    engagedProb @0 :Float32;\n    desirePrediction @1 :List(Float32);\n    desireState @5 :List(Float32);\n    disengagePredictions @6 :DisengagePredictions;\n    hardBrakePredicted @7 :Bool;\n\n    # deprecated\n    brakeDisengageProbDEPRECATED @2 :Float32;\n    gasDisengageProbDEPRECATED @3 :Float32;\n    steerOverrideProbDEPRECATED @4 :Float32;\n  }\n\n  struct DisengagePredictions {\n    t @0 :List(Float32);\n    brakeDisengageProbs @1 :List(Float32);\n    gasDisengageProbs @2 :List(Float32);\n    steerOverrideProbs @3 :List(Float32);\n    brake3MetersPerSecondSquaredProbs @4 :List(Float32);\n    brake4MetersPerSecondSquaredProbs @5 :List(Float32);\n    brake5MetersPerSecondSquaredProbs @6 :List(Float32);\n  }\n}\n\nstruct EncodeIndex {\n  # picture from camera\n  frameId @0 :UInt32;\n  type @1 :Type;\n  # index of encoder from start of route\n  encodeId @2 :UInt32;\n  # minute long segment this frame is in\n  segmentNum @3 :Int32;\n  # index into camera file in segment in presentation order\n  segmentId @4 :UInt32;\n  # index into camera file in segment in encode order\n  segmentIdEncode @5 :UInt32;\n  timestampSof @6 :UInt64;\n  timestampEof @7 :UInt64;\n\n  enum Type {\n    bigBoxLossless @0;   # rcamera.mkv\n    fullHEVC @1;         # fcamera.hevc\n    bigBoxHEVC @2;       # bcamera.hevc\n    chffrAndroidH264 @3; # acamera\n    fullLosslessClip @4; # prcamera.mkv\n    front @5;            # dcamera.hevc\n  }\n}\n\nstruct AndroidLogEntry {\n  id @0 :UInt8;\n  ts @1 :UInt64;\n  priority @2 :UInt8;\n  pid @3 :Int32;\n  tid @4 :Int32;\n  tag @5 :Text;\n  message @6 :Text;\n}\n\nstruct LongitudinalPlan @0xe00b5b3eba12876c {\n  modelMonoTime @9 :UInt64;\n  hasLead @7 :Bool;\n  fcw @8 :Bool;\n  longitudinalPlanSource @15 :LongitudinalPlanSource;\n  processingDelay @29 :Float32;\n\n  # desired speed/accel/jerk over next 2.5s\n  accels @32 :List(Float32);\n  speeds @33 :List(Float32);\n  jerks @34 :List(Float32);\n\n  visionTurnControllerState @35 :VisionTurnControllerState;\n  visionTurnSpeed @36 :Float32;\n\n  speedLimitControlState @37 :SpeedLimitControlState;\n  speedLimit @38 :Float32;\n  speedLimitOffset @39 :Float32;\n  distToSpeedLimit @40 :Float32;\n  isMapSpeedLimit @41 :Bool;\n\n  distToTurn @42 :Float32;\n  turnSpeed @43 :Float32;\n  turnSpeedControlState @44 :SpeedLimitControlState;\n  turnSign @45 :Int16;\n\n  enum LongitudinalPlanSource {\n    cruise @0;\n    lead0 @1;\n    lead1 @2;\n    lead2 @3;\n    e2e @4;\n    turn @5;\n    limit @6;\n    turnlimit @7;\n  }\n\n  # deprecated\n  vCruiseDEPRECATED @16 :Float32;\n  aCruiseDEPRECATED @17 :Float32;\n  vTargetDEPRECATED @3 :Float32;\n  vTargetFutureDEPRECATED @14 :Float32;\n  aTargetDEPRECATED @18 :Float32;\n  vStartDEPRECATED @26 :Float32;\n  aStartDEPRECATED @27 :Float32;\n  vMaxDEPRECATED @20 :Float32;\n  radarStateMonoTimeDEPRECATED @10 :UInt64;\n  jerkFactorDEPRECATED @6 :Float32;\n  hasLeftLaneDEPRECATED @23 :Bool;\n  hasRightLaneDEPRECATED @24 :Bool;\n  aTargetMinDEPRECATED @4 :Float32;\n  aTargetMaxDEPRECATED @5 :Float32;\n  lateralValidDEPRECATED @0 :Bool;\n  longitudinalValidDEPRECATED @2 :Bool;\n  dPolyDEPRECATED @1 :List(Float32);\n  laneWidthDEPRECATED @11 :Float32;\n  vCurvatureDEPRECATED @21 :Float32;\n  decelForTurnDEPRECATED @22 :Bool;\n  mapValidDEPRECATED @25 :Bool;\n  radarValidDEPRECATED @28 :Bool;\n  radarCanErrorDEPRECATED @30 :Bool;\n  commIssueDEPRECATED @31 :Bool;\n  eventsDEPRECATED @13 :List(Car.CarEvent);\n  gpsTrajectoryDEPRECATED @12 :GpsTrajectory;\n  gpsPlannerActiveDEPRECATED @19 :Bool;\n\n  struct GpsTrajectory {\n    x @0 :List(Float32);\n    y @1 :List(Float32);\n  }\n\n  enum SpeedLimitControlState {\n    inactive @0; # No speed limit set or not enabled by parameter.\n    tempInactive @1; # User wants to ignore speed limit until it changes.\n    adapting @2; # Reducing speed to match new speed limit.\n    active @3; # Cruising at speed limit.\n  }\n  enum VisionTurnControllerState {\n    disabled @0; # No predicted substancial turn on vision range or feature disabled.\n    entering @1; # A subsantial turn is predicted ahead, adapting speed to turn confort levels.\n    turning @2; # Actively turning. Managing acceleration to provide a roll on turn feeling.\n    leaving @3; # Road ahead straightens. Start to allow positive acceleration.\n  }\n}\n\nstruct LateralPlan @0xe1e9318e2ae8b51e {\n  laneWidth @0 :Float32;\n  lProb @5 :Float32;\n  rProb @7 :Float32;\n  dPathPoints @20 :List(Float32);\n  dProb @21 :Float32;\n  dPathWLinesX @30 :List(Float32);\n  dPathWLinesY @31 :List(Float32);\n\n  mpcSolutionValid @9 :Bool;\n  desire @17 :Desire;\n  laneChangeState @18 :LaneChangeState;\n  laneChangeDirection @19 :LaneChangeDirection;\n\n\n  # desired curvatures over next 2.5s in rad/m\n  psis @26 :List(Float32);\n  curvatures @27 :List(Float32);\n  curvatureRates @28 :List(Float32);\n\n  # dp\n  dpALCAStartIn @29 :Float32;\n\n  # 30~31 are being used in mapd\n\n  dpLaneLessModeStatus @32 :Bool;\n\n  enum Desire {\n    none @0;\n    turnLeft @1;\n    turnRight @2;\n    laneChangeLeft @3;\n    laneChangeRight @4;\n    keepLeft @5;\n    keepRight @6;\n  }\n\n  enum LaneChangeState {\n    off @0;\n    preLaneChange @1;\n    laneChangeStarting @2;\n    laneChangeFinishing @3;\n  }\n\n  enum LaneChangeDirection {\n    none @0;\n    left @1;\n    right @2;\n  }\n\n  # deprecated\n  curvatureDEPRECATED @22 :Float32;\n  curvatureRateDEPRECATED @23 :Float32;\n  rawCurvatureDEPRECATED @24 :Float32;\n  rawCurvatureRateDEPRECATED @25 :Float32;\n  cProbDEPRECATED @3 :Float32;\n  dPolyDEPRECATED @1 :List(Float32);\n  cPolyDEPRECATED @2 :List(Float32);\n  lPolyDEPRECATED @4 :List(Float32);\n  rPolyDEPRECATED @6 :List(Float32);\n  modelValidDEPRECATED @12 :Bool;\n  commIssueDEPRECATED @15 :Bool;\n  posenetValidDEPRECATED @16 :Bool;\n  sensorValidDEPRECATED @14 :Bool;\n  paramsValidDEPRECATED @10 :Bool;\n  steeringAngleDegDEPRECATED @8 :Float32; # deg\n  steeringRateDegDEPRECATED @13 :Float32; # deg/s\n  angleOffsetDegDEPRECATED @11 :Float32;\n}\n\nstruct LiveLocationKalman {\n\n  # More info on reference frames:\n  # https://github.com/commaai/openpilot/tree/master/common/transformations\n\n  positionECEF @0 : Measurement;\n  positionGeodetic @1 : Measurement;\n  velocityECEF @2 : Measurement;\n  velocityNED @3 : Measurement;\n  velocityDevice @4 : Measurement;\n  accelerationDevice @5: Measurement;\n\n\n  # These angles are all eulers and roll, pitch, yaw\n  # orientationECEF transforms to rot matrix: ecef_from_device\n  orientationECEF @6 : Measurement;\n  calibratedOrientationECEF @20 : Measurement;\n  orientationNED @7 : Measurement;\n  angularVelocityDevice @8 : Measurement;\n\n  # orientationNEDCalibrated transforms to rot matrix: NED_from_calibrated\n  calibratedOrientationNED @9 : Measurement;\n\n  # Calibrated frame is simply device frame\n  # aligned with the vehicle\n  velocityCalibrated @10 : Measurement;\n  accelerationCalibrated @11 : Measurement;\n  angularVelocityCalibrated @12 : Measurement;\n\n  gpsWeek @13 :Int32;\n  gpsTimeOfWeek @14 :Float64;\n  status @15 :Status;\n  unixTimestampMillis @16 :Int64;\n  inputsOK @17 :Bool = true;\n  posenetOK @18 :Bool = true;\n  gpsOK @19 :Bool = true;\n  sensorsOK @21 :Bool = true;\n  deviceStable @22 :Bool = true;\n  timeSinceReset @23 :Float64;\n  excessiveResets @24 :Bool;\n\n  enum Status {\n    uninitialized @0;\n    uncalibrated @1;\n    valid @2;\n  }\n\n  struct Measurement {\n    value @0 : List(Float64);\n    std @1 : List(Float64);\n    valid @2 : Bool;\n  }\n}\n\nstruct ProcLog {\n  cpuTimes @0 :List(CPUTimes);\n  mem @1 :Mem;\n  procs @2 :List(Process);\n\n  struct Process {\n    pid @0 :Int32;\n    name @1 :Text;\n    state @2 :UInt8;\n    ppid @3 :Int32;\n\n    cpuUser @4 :Float32;\n    cpuSystem @5 :Float32;\n    cpuChildrenUser @6 :Float32;\n    cpuChildrenSystem @7 :Float32;\n    priority @8 :Int64;\n    nice @9 :Int32;\n    numThreads @10 :Int32;\n    startTime @11 :Float64;\n\n    memVms @12 :UInt64;\n    memRss @13 :UInt64;\n\n    processor @14 :Int32;\n\n    cmdline @15 :List(Text);\n    exe @16 :Text;\n  }\n\n  struct CPUTimes {\n    cpuNum @0 :Int64;\n    user @1 :Float32;\n    nice @2 :Float32;\n    system @3 :Float32;\n    idle @4 :Float32;\n    iowait @5 :Float32;\n    irq @6 :Float32;\n    softirq @7 :Float32;\n  }\n\n  struct Mem {\n    total @0 :UInt64;\n    free @1 :UInt64;\n    available @2 :UInt64;\n    buffers @3 :UInt64;\n    cached @4 :UInt64;\n    active @5 :UInt64;\n    inactive @6 :UInt64;\n    shared @7 :UInt64;\n  }\n}\n\nstruct UbloxGnss {\n  union {\n    measurementReport @0 :MeasurementReport;\n    ephemeris @1 :Ephemeris;\n    ionoData @2 :IonoData;\n    hwStatus @3 :HwStatus;\n    hwStatus2 @4 :HwStatus2;\n  }\n\n  struct MeasurementReport {\n    #received time of week in gps time in seconds and gps week\n    rcvTow @0 :Float64;\n    gpsWeek @1 :UInt16;\n    # leap seconds in seconds\n    leapSeconds @2 :UInt16;\n    # receiver status\n    receiverStatus @3 :ReceiverStatus;\n    # num of measurements to follow\n    numMeas @4 :UInt8;\n    measurements @5 :List(Measurement);\n\n    struct ReceiverStatus {\n      # leap seconds have been determined\n      leapSecValid @0 :Bool;\n      # Clock reset applied\n      clkReset @1 :Bool;\n    }\n\n    struct Measurement {\n      svId @0 :UInt8;\n      trackingStatus @1 :TrackingStatus;\n      # pseudorange in meters\n      pseudorange @2 :Float64;\n      # carrier phase measurement in cycles\n      carrierCycles @3 :Float64;\n      # doppler measurement in Hz\n      doppler @4 :Float32;\n      # GNSS id, 0 is gps\n      gnssId @5 :UInt8;\n      glonassFrequencyIndex @6 :UInt8;\n      # carrier phase locktime counter in ms\n      locktime @7 :UInt16;\n      # Carrier-to-noise density ratio (signal strength) in dBHz\n      cno @8 :UInt8;\n      # pseudorange standard deviation in meters\n      pseudorangeStdev @9 :Float32;\n      # carrier phase standard deviation in cycles\n      carrierPhaseStdev @10 :Float32;\n      # doppler standard deviation in Hz\n      dopplerStdev @11 :Float32;\n      sigId @12 :UInt8;\n\n      struct TrackingStatus {\n        # pseudorange valid\n        pseudorangeValid @0 :Bool;\n        # carrier phase valid\n        carrierPhaseValid @1 :Bool;\n        # half cycle valid\n        halfCycleValid @2 :Bool;\n        # half sycle subtracted from phase\n        halfCycleSubtracted @3 :Bool;\n      }\n    }\n  }\n\n  struct Ephemeris {\n    # This is according to the rinex (2?) format\n    svId @0 :UInt16;\n    year @1 :UInt16;\n    month @2 :UInt16;\n    day @3 :UInt16;\n    hour @4 :UInt16;\n    minute @5 :UInt16;\n    second @6 :Float32;\n    af0 @7 :Float64;\n    af1 @8 :Float64;\n    af2 @9 :Float64;\n\n    iode @10 :Float64;\n    crs @11 :Float64;\n    deltaN @12 :Float64;\n    m0 @13 :Float64;\n\n    cuc @14 :Float64;\n    ecc @15 :Float64;\n    cus @16 :Float64;\n    a @17 :Float64; # note that this is not the root!!\n\n    toe @18 :Float64;\n    cic @19 :Float64;\n    omega0 @20 :Float64;\n    cis @21 :Float64;\n\n    i0 @22 :Float64;\n    crc @23 :Float64;\n    omega @24 :Float64;\n    omegaDot @25 :Float64;\n\n    iDot @26 :Float64;\n    codesL2 @27 :Float64;\n    gpsWeek @28 :Float64;\n    l2 @29 :Float64;\n\n    svAcc @30 :Float64;\n    svHealth @31 :Float64;\n    tgd @32 :Float64;\n    iodc @33 :Float64;\n\n    transmissionTime @34 :Float64;\n    fitInterval @35 :Float64;\n\n    toc @36 :Float64;\n\n    ionoCoeffsValid @37 :Bool;\n    ionoAlpha @38 :List(Float64);\n    ionoBeta @39 :List(Float64);\n\n  }\n\n  struct IonoData {\n    svHealth @0 :UInt32;\n    tow  @1 :Float64;\n    gpsWeek @2 :Float64;\n\n    ionoAlpha @3 :List(Float64);\n    ionoBeta @4 :List(Float64);\n\n    healthValid @5 :Bool;\n    ionoCoeffsValid @6 :Bool;\n  }\n\n  struct HwStatus {\n    noisePerMS @0 :UInt16;\n    agcCnt @1 :UInt16;\n    aStatus @2 :AntennaSupervisorState;\n    aPower @3 :AntennaPowerStatus;\n    jamInd @4 :UInt8;\n    flags @5 :UInt8;\n\n    enum AntennaSupervisorState {\n      init @0;\n      dontknow @1;\n      ok @2;\n      short @3;\n      open @4;\n    }\n\n    enum AntennaPowerStatus {\n      off @0;\n      on @1;\n      dontknow @2;\n    }\n  }\n\n  struct HwStatus2 {\n    ofsI @0 :Int8;\n    magI @1 :UInt8;\n    ofsQ @2 :Int8;\n    magQ @3 :UInt8;\n    cfgSource @4 :ConfigSource;\n    lowLevCfg @5 :UInt32;\n    postStatus @6 :UInt32;\n\n    enum ConfigSource {\n      undefined @0;\n      rom @1;\n      otp @2;\n      configpins @3;\n      flash @4;\n    }\n  }\n}\n\nstruct Clocks {\n  bootTimeNanos @0 :UInt64;\n  monotonicNanos @1 :UInt64;\n  monotonicRawNanos @2 :UInt64;\n  wallTimeNanos @3 :UInt64;\n  modemUptimeMillis @4 :UInt64;\n}\n\nstruct LiveMpcData {\n  x @0 :List(Float32);\n  y @1 :List(Float32);\n  psi @2 :List(Float32);\n  curvature @3 :List(Float32);\n  qpIterations @4 :UInt32;\n  calculationTime @5 :UInt64;\n  cost @6 :Float64;\n}\n\nstruct LiveLongitudinalMpcData {\n  xEgo @0 :List(Float32);\n  vEgo @1 :List(Float32);\n  aEgo @2 :List(Float32);\n  xLead @3 :List(Float32);\n  vLead @4 :List(Float32);\n  aLead @5 :List(Float32);\n  aLeadTau @6 :Float32;    # lead accel time constant\n  qpIterations @7 :UInt32;\n  mpcId @8 :UInt32;\n  calculationTime @9 :UInt64;\n  cost @10 :Float64;\n}\n\nstruct Joystick {\n  # convenient for debug and live tuning\n  axes @0: List(Float32);\n  buttons @1: List(Bool);\n}\n\nstruct DriverState {\n  frameId @0 :UInt32;\n  modelExecutionTime @14 :Float32;\n  dspExecutionTime @16 :Float32;\n  rawPredictions @15 :Data;\n\n  faceOrientation @3 :List(Float32);\n  facePosition @4 :List(Float32);\n  faceProb @5 :Float32;\n  leftEyeProb @6 :Float32;\n  rightEyeProb @7 :Float32;\n  leftBlinkProb @8 :Float32;\n  rightBlinkProb @9 :Float32;\n  faceOrientationStd @11 :List(Float32);\n  facePositionStd @12 :List(Float32);\n  sunglassesProb @13 :Float32;\n  poorVision @17 :Float32;\n  partialFace @18 :Float32;\n  distractedPose @19 :Float32;\n  distractedEyes @20 :Float32;\n  eyesOnRoad @21 :Float32;\n  phoneUse @22 :Float32;\n\n  irPwrDEPRECATED @10 :Float32;\n  descriptorDEPRECATED @1 :List(Float32);\n  stdDEPRECATED @2 :Float32;\n}\n\nstruct DriverMonitoringState @0xb83cda094a1da284 {\n  events @0 :List(Car.CarEvent);\n  faceDetected @1 :Bool;\n  isDistracted @2 :Bool;\n  awarenessStatus @3 :Float32;\n  posePitchOffset @6 :Float32;\n  posePitchValidCount @7 :UInt32;\n  poseYawOffset @8 :Float32;\n  poseYawValidCount @9 :UInt32;\n  stepChange @10 :Float32;\n  awarenessActive @11 :Float32;\n  awarenessPassive @12 :Float32;\n  isLowStd @13 :Bool;\n  hiStdCount @14 :UInt32;\n  isActiveMode @16 :Bool;\n\n  isRHDDEPRECATED @4 :Bool;\n  isPreviewDEPRECATED @15 :Bool;\n  rhdCheckedDEPRECATED @5 :Bool;\n}\n\nstruct Boot {\n  wallTimeNanos @0 :UInt64;\n  pstore @4 :Map(Text, Data);\n  launchLog @3 :Text;\n\n  lastKmsgDEPRECATED @1 :Data;\n  lastPmsgDEPRECATED @2 :Data;\n}\n\nstruct LiveParametersData {\n  valid @0 :Bool;\n  gyroBias @1 :Float32;\n  angleOffsetDeg @2 :Float32;\n  angleOffsetAverageDeg @3 :Float32;\n  stiffnessFactor @4 :Float32;\n  steerRatio @5 :Float32;\n  sensorValid @6 :Bool;\n  yawRate @7 :Float32;\n  posenetSpeed @8 :Float32;\n  posenetValid @9 :Bool;\n}\n\nstruct LiveMapDataDEPRECATED {\n  speedLimitValid @0 :Bool;\n  speedLimit @1 :Float32;\n  speedAdvisoryValid @12 :Bool;\n  speedAdvisory @13 :Float32;\n  speedLimitAheadValid @14 :Bool;\n  speedLimitAhead @15 :Float32;\n  speedLimitAheadDistance @16 :Float32;\n  curvatureValid @2 :Bool;\n  curvature @3 :Float32;\n  wayId @4 :UInt64;\n  roadX @5 :List(Float32);\n  roadY @6 :List(Float32);\n  lastGps @7: GpsLocationData;\n  roadCurvatureX @8 :List(Float32);\n  roadCurvature @9 :List(Float32);\n  distToTurn @10 :Float32;\n  mapValid @11 :Bool;\n}\n\nstruct LiveMapData {\n  speedLimitValid @0 :Bool;\n  speedLimit @1 :Float32;\n  speedLimitAheadValid @2 :Bool;\n  speedLimitAhead @3 :Float32;\n  speedLimitAheadDistance @4 :Float32;\n  turnSpeedLimitValid @5 :Bool;\n  turnSpeedLimit @6 :Float32;\n  turnSpeedLimitEndDistance @7 :Float32;\n  turnSpeedLimitSign @8 :Int16;\n  turnSpeedLimitsAhead @9 :List(Float32);\n  turnSpeedLimitsAheadDistances @10 :List(Float32);\n  turnSpeedLimitsAheadSigns @11 :List(Int16);\n  lastGpsTimestamp @12 :Int64;  # Milliseconds since January 1, 1970.\n  currentRoadName @13 :Text;\n}\n\nstruct CameraOdometry {\n  frameId @4 :UInt32;\n  timestampEof @5 :UInt64;\n  trans @0 :List(Float32); # m/s in device frame\n  rot @1 :List(Float32); # rad/s in device frame\n  transStd @2 :List(Float32); # std m/s in device frame\n  rotStd @3 :List(Float32); # std rad/s in device frame\n}\n\nstruct Sentinel {\n  enum SentinelType {\n    endOfSegment @0;\n    endOfRoute @1;\n    startOfSegment @2;\n    startOfRoute @3;\n  }\n  type @0 :SentinelType;\n  signal @1 :Int32;\n}\n\nstruct ManagerState {\n  processes @0 :List(ProcessState);\n\n  struct ProcessState {\n    name @0 :Text;\n    pid @1 :Int32;\n    running @2 :Bool;\n    exitCode @3 :Int32;\n  }\n}\n\nstruct UploaderState {\n  immediateQueueSize @0 :UInt32;\n  immediateQueueCount @1 :UInt32;\n  rawQueueSize @2 :UInt32;\n  rawQueueCount @3 :UInt32;\n\n  # stats for last successfully uploaded file\n  lastTime @4 :Float32;  # s\n  lastSpeed @5 :Float32; # MB/s\n  lastFilename @6 :Text;\n}\n\nstruct Event {\n  logMonoTime @0 :UInt64;  # nanoseconds\n  valid @67 :Bool = true;\n\n  union {\n    # *********** log metadata ***********\n    initData @1 :InitData;\n    sentinel @73 :Sentinel;\n\n    # *********** bootlog ***********\n    boot @60 :Boot;\n\n    # ********** openpilot daemon msgs **********\n    gpsNMEA @3 :GPSNMEAData;\n    can @5 :List(CanData);\n    controlsState @7 :ControlsState;\n    sensorEvents @11 :List(SensorEventData);\n    pandaState @12 :PandaState;\n    radarState @13 :RadarState;\n    liveTracks @16 :List(LiveTracks);\n    sendcan @17 :List(CanData);\n    liveCalibration @19 :LiveCalibrationData;\n    carState @22 :Car.CarState;\n    carControl @23 :Car.CarControl;\n    longitudinalPlan @24 :LongitudinalPlan;\n    lateralPlan @64 :LateralPlan;\n    ubloxGnss @34 :UbloxGnss;\n    ubloxRaw @39 :Data;\n    gpsLocationExternal @48 :GpsLocationData;\n    driverState @59 :DriverState;\n    liveParameters @61 :LiveParametersData;\n    cameraOdometry @63 :CameraOdometry;\n    thumbnail @66: Thumbnail;\n    carEvents @68: List(Car.CarEvent);\n    carParams @69: Car.CarParams;\n    driverMonitoringState @71: DriverMonitoringState;\n    liveLocationKalman @72 :LiveLocationKalman;\n    modelV2 @75 :ModelDataV2;\n\n    # camera stuff, each camera state has a matching encode idx\n    roadCameraState @2 :FrameData;\n    driverCameraState @70: FrameData;\n    wideRoadCameraState @74: FrameData;\n    roadEncodeIdx @15 :EncodeIndex;\n    driverEncodeIdx @76 :EncodeIndex;\n    wideRoadEncodeIdx @77 :EncodeIndex;\n\n    # systems stuff\n    androidLog @20 :AndroidLogEntry;\n    managerState @78 :ManagerState;\n    uploaderState @79 :UploaderState;\n    procLog @33 :ProcLog;\n    clocks @35 :Clocks;\n    deviceState @6 :DeviceState;\n    logMessage @18 :Text;\n\n\n    # *********** debug ***********\n    testJoystick @52 :Joystick;\n\n    # *********** legacy + deprecated ***********\n    model @9 :Legacy.ModelData; # TODO: rename modelV2 and mark this as deprecated\n    liveMpcDEPRECATED @36 :LiveMpcData;\n    liveLongitudinalMpcDEPRECATED @37 :LiveLongitudinalMpcData;\n    liveLocationKalmanDEPRECATED @51 :Legacy.LiveLocationData;\n    orbslamCorrectionDEPRECATED @45 :Legacy.OrbslamCorrection;\n    liveUIDEPRECATED @14 :Legacy.LiveUI;\n    sensorEventDEPRECATED @4 :SensorEventData;\n    liveEventDEPRECATED @8 :List(Legacy.LiveEventData);\n    liveLocationDEPRECATED @25 :Legacy.LiveLocationData;\n    ethernetDataDEPRECATED @26 :List(Legacy.EthernetPacket);\n    cellInfoDEPRECATED @28 :List(Legacy.CellInfo);\n    wifiScanDEPRECATED @29 :List(Legacy.WifiScan);\n    uiNavigationEventDEPRECATED @50 :Legacy.UiNavigationEvent;\n    liveMapDataDEPRECATED @62 :LiveMapDataDEPRECATED;\n    gpsPlannerPointsDEPRECATED @40 :Legacy.GPSPlannerPoints;\n    gpsPlannerPlanDEPRECATED @41 :Legacy.GPSPlannerPlan;\n    applanixRawDEPRECATED @42 :Data;\n    androidGnssDEPRECATED @30 :Legacy.AndroidGnss;\n    qcomGnssDEPRECATD @31 :Legacy.QcomGnss;\n    lidarPtsDEPRECATED @32 :Legacy.LidarPts;\n    navStatusDEPRECATED @38 :Legacy.NavStatus;\n    trafficEventsDEPRECATED @43 :List(Legacy.TrafficEvent);\n    liveLocationTimingDEPRECATED @44 :Legacy.LiveLocationData;\n    liveLocationCorrectedDEPRECATED @46 :Legacy.LiveLocationData;\n    navUpdateDEPRECATED @27 :Legacy.NavUpdate;\n    orbObservationDEPRECATED @47 :List(Legacy.OrbObservation);\n    locationDEPRECATED @49 :Legacy.LiveLocationData;\n    orbOdometryDEPRECATED @53 :Legacy.OrbOdometry;\n    orbFeaturesDEPRECATED @54 :Legacy.OrbFeatures;\n    applanixLocationDEPRECATED @55 :Legacy.LiveLocationData;\n    orbKeyFrameDEPRECATED @56 :Legacy.OrbKeyFrame;\n    orbFeaturesSummaryDEPRECATED @58 :Legacy.OrbFeaturesSummary;\n    featuresDEPRECATED @10 :Legacy.CalibrationFeatures;\n    kalmanOdometryDEPRECATED @65 :Legacy.KalmanOdometry;\n    gpsLocationDEPRECATED @21 :GpsLocationData;\n    uiLayoutStateDEPRECATED @57 :Legacy.UiLayoutState;\n    dragonConf @80 :Dp.DragonConf;\n\n    #mapd\n    liveMapData @81: LiveMapData;\n  }\n}\n"
  },
  {
    "path": "cereal/logger/logger.h",
    "content": "#pragma once\n\n#ifdef SWAGLOG\n#include \"selfdrive/common/swaglog.h\"\n#else\n\n#define CLOUDLOG_DEBUG 10\n#define CLOUDLOG_INFO 20\n#define CLOUDLOG_WARNING 30\n#define CLOUDLOG_ERROR 40\n#define CLOUDLOG_CRITICAL 50\n\n#define cloudlog(lvl, fmt, ...) printf(fmt \"\\n\", ## __VA_ARGS__)\n\n#define LOGD(fmt, ...) cloudlog(CLOUDLOG_DEBUG, fmt, ## __VA_ARGS__)\n#define LOG(fmt, ...) cloudlog(CLOUDLOG_INFO, fmt, ## __VA_ARGS__)\n#define LOGW(fmt, ...) cloudlog(CLOUDLOG_WARNING, fmt, ## __VA_ARGS__)\n#define LOGE(fmt, ...) cloudlog(CLOUDLOG_ERROR, fmt, ## __VA_ARGS__)\n\n#endif\n"
  },
  {
    "path": "cereal/messaging/.gitignore",
    "content": "demo\nbridge\ntest_runner\n*.o\n*.os\n*.d\n*.a\n*.so\nmessaging_pyx.cpp\nbuild/\n"
  },
  {
    "path": "cereal/messaging/__init__.py",
    "content": "# must be build with scons\nfrom .messaging_pyx import Context, Poller, SubSocket, PubSocket  # pylint: disable=no-name-in-module, import-error\nfrom .messaging_pyx import MultiplePublishersError, MessagingError  # pylint: disable=no-name-in-module, import-error\nimport os\nimport capnp\n\nfrom typing import Optional, List, Union\nfrom collections import deque\n\nfrom cereal import log\nfrom cereal.services import service_list\n\nassert MultiplePublishersError\nassert MessagingError\n\nNO_TRAVERSAL_LIMIT = 2**64-1\nAVG_FREQ_HISTORY = 100\nSIMULATION = \"SIMULATION\" in os.environ\n\n# sec_since_boot is faster, but allow to run standalone too\ntry:\n  from common.realtime import sec_since_boot\nexcept ImportError:\n  import time\n  sec_since_boot = time.time\n  print(\"Warning, using python time.time() instead of faster sec_since_boot\")\n\ncontext = Context()\n\ndef log_from_bytes(dat: bytes) -> capnp.lib.capnp._DynamicStructReader:\n  return log.Event.from_bytes(dat, traversal_limit_in_words=NO_TRAVERSAL_LIMIT)\n\ndef new_message(service: Optional[str] = None, size: Optional[int] = None) -> capnp.lib.capnp._DynamicStructBuilder:\n  dat = log.Event.new_message()\n  dat.logMonoTime = int(sec_since_boot() * 1e9)\n  dat.valid = True\n  if service is not None:\n    if size is None:\n      dat.init(service)\n    else:\n      dat.init(service, size)\n  return dat\n\ndef pub_sock(endpoint: str) -> PubSocket:\n  sock = PubSocket()\n  sock.connect(context, endpoint)\n  return sock\n\ndef sub_sock(endpoint: str, poller: Optional[Poller] = None, addr: str = \"127.0.0.1\",\n             conflate: bool = False, timeout: Optional[int] = None) -> SubSocket:\n  sock = SubSocket()\n  sock.connect(context, endpoint, addr.encode('utf8'), conflate)\n\n  if timeout is not None:\n    sock.setTimeout(timeout)\n\n  if poller is not None:\n    poller.registerSocket(sock)\n  return sock\n\n\ndef drain_sock_raw(sock: SubSocket, wait_for_one: bool = False) -> List[bytes]:\n  \"\"\"Receive all message currently available on the queue\"\"\"\n  ret: List[bytes] = []\n  while 1:\n    if wait_for_one and len(ret) == 0:\n      dat = sock.receive()\n    else:\n      dat = sock.receive(non_blocking=True)\n\n    if dat is None:\n      break\n\n    ret.append(dat)\n\n  return ret\n\ndef drain_sock(sock: SubSocket, wait_for_one: bool = False) -> List[capnp.lib.capnp._DynamicStructReader]:\n  \"\"\"Receive all message currently available on the queue\"\"\"\n  ret: List[capnp.lib.capnp._DynamicStructReader] = []\n  while 1:\n    if wait_for_one and len(ret) == 0:\n      dat = sock.receive()\n    else:\n      dat = sock.receive(non_blocking=True)\n\n    if dat is None:  # Timeout hit\n      break\n\n    dat = log_from_bytes(dat)\n    ret.append(dat)\n\n  return ret\n\n\n# TODO: print when we drop packets?\ndef recv_sock(sock: SubSocket, wait: bool = False) -> Union[None, capnp.lib.capnp._DynamicStructReader]:\n  \"\"\"Same as drain sock, but only returns latest message. Consider using conflate instead.\"\"\"\n  dat = None\n\n  while 1:\n    if wait and dat is None:\n      rcv = sock.receive()\n    else:\n      rcv = sock.receive(non_blocking=True)\n\n    if rcv is None:  # Timeout hit\n      break\n\n    dat = rcv\n\n  if dat is not None:\n    dat = log_from_bytes(dat)\n\n  return dat\n\ndef recv_one(sock: SubSocket) -> Union[None, capnp.lib.capnp._DynamicStructReader]:\n  dat = sock.receive()\n  if dat is not None:\n    dat = log_from_bytes(dat)\n  return dat\n\ndef recv_one_or_none(sock: SubSocket) -> Union[None, capnp.lib.capnp._DynamicStructReader]:\n  dat = sock.receive(non_blocking=True)\n  if dat is not None:\n    dat = log_from_bytes(dat)\n  return dat\n\ndef recv_one_retry(sock: SubSocket) -> capnp.lib.capnp._DynamicStructReader:\n  \"\"\"Keep receiving until we get a message\"\"\"\n  while True:\n    dat = sock.receive()\n    if dat is not None:\n      return log_from_bytes(dat)\n\nclass SubMaster():\n  def __init__(self, services: List[str], poll: Optional[List[str]] = None,\n               ignore_alive: Optional[List[str]] = None, ignore_avg_freq: Optional[List[str]] = None,\n               addr: str = \"127.0.0.1\"):\n    self.frame = -1\n    self.updated = {s: False for s in services}\n    self.rcv_time = {s: 0. for s in services}\n    self.rcv_frame = {s: 0 for s in services}\n    self.alive = {s: False for s in services}\n    self.recv_dts = {s: deque([0.0] * AVG_FREQ_HISTORY, maxlen=AVG_FREQ_HISTORY) for s in services}\n    self.sock = {}\n    self.freq = {}\n    self.data = {}\n    self.valid = {}\n    self.logMonoTime = {}\n\n    self.poller = Poller()\n    self.non_polled_services = [s for s in services if poll is not None and\n                                len(poll) and s not in poll]\n\n    self.ignore_average_freq = [] if ignore_avg_freq is None else ignore_avg_freq\n    self.ignore_alive = [] if ignore_alive is None else ignore_alive\n\n    for s in services:\n      if addr is not None:\n        p = self.poller if s not in self.non_polled_services else None\n        self.sock[s] = sub_sock(s, poller=p, addr=addr, conflate=True)\n      self.freq[s] = service_list[s].frequency\n\n      try:\n        data = new_message(s)\n      except capnp.lib.capnp.KjException:  # pylint: disable=c-extension-no-member\n        data = new_message(s, 0) # lists\n\n      self.data[s] = getattr(data, s)\n      self.logMonoTime[s] = 0\n      self.valid[s] = data.valid\n\n  def __getitem__(self, s: str) -> capnp.lib.capnp._DynamicStructReader:\n    return self.data[s]\n\n  def update(self, timeout: int = 1000) -> None:\n    msgs = []\n    for sock in self.poller.poll(timeout):\n      msgs.append(recv_one_or_none(sock))\n\n    # non-blocking receive for non-polled sockets\n    for s in self.non_polled_services:\n      msgs.append(recv_one_or_none(self.sock[s]))\n    self.update_msgs(sec_since_boot(), msgs)\n\n  def update_msgs(self, cur_time: float, msgs: List[capnp.lib.capnp._DynamicStructReader]) -> None:\n    self.frame += 1\n    self.updated = dict.fromkeys(self.updated, False)\n    for msg in msgs:\n      if msg is None:\n        continue\n\n      s = msg.which()\n      self.updated[s] = True\n\n      if self.rcv_time[s] > 1e-5 and self.freq[s] > 1e-5 and (s not in self.non_polled_services) \\\n        and (s not in self.ignore_average_freq):\n        self.recv_dts[s].append(cur_time - self.rcv_time[s])\n\n      self.rcv_time[s] = cur_time\n      self.rcv_frame[s] = self.frame\n      self.data[s] = getattr(msg, s)\n      self.logMonoTime[s] = msg.logMonoTime\n      self.valid[s] = msg.valid\n\n      if SIMULATION:\n        self.alive[s] = True\n\n    if not SIMULATION:\n      for s in self.data:\n        # arbitrary small number to avoid float comparison. If freq is 0, we can skip the check\n        if self.freq[s] > 1e-5:\n          # alive if delay is within 10x the expected frequency\n          self.alive[s] = (cur_time - self.rcv_time[s]) < (10. / self.freq[s])\n\n          # alive if average frequency is higher than 90% of expected frequency\n          avg_dt = sum(self.recv_dts[s]) / AVG_FREQ_HISTORY\n          expected_dt = 1 / (self.freq[s] * 0.90)\n          self.alive[s] = self.alive[s] and (avg_dt < expected_dt)\n        else:\n          self.alive[s] = True\n\n  def all_alive(self, service_list=None) -> bool:\n    if service_list is None:  # check all\n      service_list = self.alive.keys()\n    return all(self.alive[s] for s in service_list if s not in self.ignore_alive)\n\n  def all_valid(self, service_list=None) -> bool:\n    if service_list is None:  # check all\n      service_list = self.valid.keys()\n    return all(self.valid[s] for s in service_list)\n\n  def all_alive_and_valid(self, service_list=None) -> bool:\n    if service_list is None:  # check all\n      service_list = self.alive.keys()\n    return self.all_alive(service_list=service_list) and self.all_valid(service_list=service_list)\n\nclass PubMaster():\n  def __init__(self, services: List[str]):\n    self.sock = {}\n    for s in services:\n      self.sock[s] = pub_sock(s)\n\n  def send(self, s: str, dat: Union[bytes, capnp.lib.capnp._DynamicStructBuilder]) -> None:\n    if not isinstance(dat, bytes):\n      dat = dat.to_bytes()\n    self.sock[s].send(dat)\n\n  def all_readers_updated(self, s: str) -> bool:\n    return self.sock[s].all_readers_updated()\n"
  },
  {
    "path": "cereal/messaging/bridge.cc",
    "content": "#include <algorithm>\n#include <cassert>\n#include <csignal>\n#include <iostream>\n#include <map>\n#include <string>\n\ntypedef void (*sighandler_t)(int sig);\n\n#include \"impl_msgq.h\"\n#include \"impl_zmq.h\"\n#include \"services.h\"\n\nvoid sigpipe_handler(int sig) {\n  assert(sig == SIGPIPE);\n  std::cout << \"SIGPIPE received\" << std::endl;\n}\n\nstatic std::vector<std::string> get_services(std::string whitelist_str, bool zmq_to_msgq) {\n  std::vector<std::string> service_list;\n  for (const auto& it : services) {\n    std::string name = it.name;\n    bool in_whitelist = whitelist_str.find(name) != std::string::npos;\n    if (name == \"plusFrame\" || name == \"uiLayoutState\" || (zmq_to_msgq && !in_whitelist)) {\n      continue;\n    }\n    service_list.push_back(name);\n  }\n  return service_list;\n}\n\nint main(int argc, char** argv) {\n  signal(SIGPIPE, (sighandler_t)sigpipe_handler);\n\n  bool zmq_to_msgq = argc > 2;\n  std::string ip = zmq_to_msgq ? argv[1] : \"127.0.0.1\";\n  std::string whitelist_str = zmq_to_msgq ? std::string(argv[2]) : \"\";\n\n  Poller *poller;\n  Context *pub_context;\n  Context *sub_context;\n  if (zmq_to_msgq) {  // republishes zmq debugging messages as msgq\n    poller = new ZMQPoller();\n    pub_context = new MSGQContext();\n    sub_context = new ZMQContext();\n  } else {\n    poller = new MSGQPoller();\n    pub_context = new ZMQContext();\n    sub_context = new MSGQContext();\n  }\n\n  std::map<SubSocket*, PubSocket*> sub2pub;\n  for (auto endpoint: get_services(whitelist_str, zmq_to_msgq)) {\n    PubSocket * pub_sock;\n    SubSocket * sub_sock;\n    if (zmq_to_msgq) {\n      pub_sock = new MSGQPubSocket();\n      sub_sock = new ZMQSubSocket();\n    } else {\n      pub_sock = new ZMQPubSocket();\n      sub_sock = new MSGQSubSocket();\n    }\n    pub_sock->connect(pub_context, endpoint);\n    sub_sock->connect(sub_context, endpoint, ip, false);\n\n    poller->registerSocket(sub_sock);\n    sub2pub[sub_sock] = pub_sock;\n  }\n\n  while (true) {\n    for (auto sub_sock : poller->poll(100)) {\n      Message * msg = sub_sock->receive();\n      if (msg == NULL) continue;\n      sub2pub[sub_sock]->sendMessage(msg);\n      delete msg;\n    }\n  }\n  return 0;\n}\n"
  },
  {
    "path": "cereal/messaging/impl_msgq.cc",
    "content": "#include <cassert>\n#include <cstring>\n#include <iostream>\n#include <cstdlib>\n#include <csignal>\n#include <cerrno>\n\n#include \"services.h\"\n#include \"impl_msgq.h\"\n\n\nvolatile sig_atomic_t msgq_do_exit = 0;\n\nvoid sig_handler(int signal) {\n  assert(signal == SIGINT || signal == SIGTERM);\n  msgq_do_exit = 1;\n}\n\nstatic bool service_exists(std::string path){\n  for (const auto& it : services) {\n    if (it.name == path) {\n      return true;\n    }\n  }\n  return false;\n}\n\nstatic size_t get_size(std::string endpoint){\n  size_t sz = DEFAULT_SEGMENT_SIZE;\n\n  if (endpoint == \"roadCameraState\" || endpoint == \"driverCameraState\" || endpoint == \"wideRoadCameraState\"){\n    sz *= 10;\n  }\n\n  return sz;\n}\n\n\nMSGQContext::MSGQContext() {\n}\n\nMSGQContext::~MSGQContext() {\n}\n\nvoid MSGQMessage::init(size_t sz) {\n  size = sz;\n  data = new char[size];\n}\n\nvoid MSGQMessage::init(char * d, size_t sz) {\n  size = sz;\n  data = new char[size];\n  memcpy(data, d, size);\n}\n\nvoid MSGQMessage::takeOwnership(char * d, size_t sz) {\n  size = sz;\n  data = d;\n}\n\nvoid MSGQMessage::close() {\n  if (size > 0){\n    delete[] data;\n  }\n  size = 0;\n}\n\nMSGQMessage::~MSGQMessage() {\n  this->close();\n}\n\nint MSGQSubSocket::connect(Context *context, std::string endpoint, std::string address, bool conflate, bool check_endpoint){\n  assert(context);\n  assert(address == \"127.0.0.1\");\n\n  if (check_endpoint && !service_exists(std::string(endpoint))){\n    std::cout << \"Warning, \" << std::string(endpoint) << \" is not in service list.\" << std::endl;\n  }\n\n  q = new msgq_queue_t;\n  int r = msgq_new_queue(q, endpoint.c_str(), get_size(endpoint));\n  if (r != 0){\n    return r;\n  }\n\n  msgq_init_subscriber(q);\n\n  if (conflate){\n    q->read_conflate = true;\n  }\n\n  timeout = -1;\n\n  return 0;\n}\n\n\nMessage * MSGQSubSocket::receive(bool non_blocking){\n  msgq_do_exit = 0;\n\n  void (*prev_handler_sigint)(int);\n  void (*prev_handler_sigterm)(int);\n  if (!non_blocking){\n    prev_handler_sigint = std::signal(SIGINT, sig_handler);\n    prev_handler_sigterm = std::signal(SIGTERM, sig_handler);\n  }\n\n  msgq_msg_t msg;\n\n  MSGQMessage *r = NULL;\n\n  int rc = msgq_msg_recv(&msg, q);\n\n  // Hack to implement blocking read with a poller. Don't use this\n  while (!non_blocking && rc == 0 && msgq_do_exit == 0){\n    msgq_pollitem_t items[1];\n    items[0].q = q;\n\n    int t = (timeout != -1) ? timeout : 100;\n\n    int n = msgq_poll(items, 1, t);\n    rc = msgq_msg_recv(&msg, q);\n\n    // The poll indicated a message was ready, but the receive failed. Try again\n    if (n == 1 && rc == 0){\n      continue;\n    }\n\n    if (timeout != -1){\n      break;\n    }\n  }\n\n\n  if (!non_blocking){\n    std::signal(SIGINT, prev_handler_sigint);\n    std::signal(SIGTERM, prev_handler_sigterm);\n  }\n\n  errno = msgq_do_exit ? EINTR : 0;\n\n  if (rc > 0){\n    if (msgq_do_exit){\n      msgq_msg_close(&msg); // Free unused message on exit\n    } else {\n      r = new MSGQMessage;\n      r->takeOwnership(msg.data, msg.size);\n    }\n  }\n\n  return (Message*)r;\n}\n\nvoid MSGQSubSocket::setTimeout(int t){\n  timeout = t;\n}\n\nMSGQSubSocket::~MSGQSubSocket(){\n  if (q != NULL){\n    msgq_close_queue(q);\n    delete q;\n  }\n}\n\nint MSGQPubSocket::connect(Context *context, std::string endpoint, bool check_endpoint){\n  assert(context);\n\n  if (check_endpoint && !service_exists(std::string(endpoint))){\n    std::cout << \"Warning, \" << std::string(endpoint) << \" is not in service list.\" << std::endl;\n  }\n\n  q = new msgq_queue_t;\n  int r = msgq_new_queue(q, endpoint.c_str(), get_size(endpoint));\n  if (r != 0){\n    return r;\n  }\n\n  msgq_init_publisher(q);\n\n  return 0;\n}\n\nint MSGQPubSocket::sendMessage(Message *message){\n  msgq_msg_t msg;\n  msg.data = message->getData();\n  msg.size = message->getSize();\n\n  return msgq_msg_send(&msg, q);\n}\n\nint MSGQPubSocket::send(char *data, size_t size){\n  msgq_msg_t msg;\n  msg.data = data;\n  msg.size = size;\n\n  return msgq_msg_send(&msg, q);\n}\n\nbool MSGQPubSocket::all_readers_updated() {\n  return msgq_all_readers_updated(q);\n}\n\nMSGQPubSocket::~MSGQPubSocket(){\n  if (q != NULL){\n    msgq_close_queue(q);\n    delete q;\n  }\n}\n\n\nvoid MSGQPoller::registerSocket(SubSocket * socket){\n  assert(num_polls + 1 < MAX_POLLERS);\n  polls[num_polls].q = (msgq_queue_t*)socket->getRawSocket();\n\n  sockets.push_back(socket);\n  num_polls++;\n}\n\nstd::vector<SubSocket*> MSGQPoller::poll(int timeout){\n  std::vector<SubSocket*> r;\n\n  msgq_poll(polls, num_polls, timeout);\n  for (size_t i = 0; i < num_polls; i++){\n    if (polls[i].revents){\n      r.push_back(sockets[i]);\n    }\n  }\n\n  return r;\n}\n"
  },
  {
    "path": "cereal/messaging/impl_msgq.h",
    "content": "#pragma once\n#include \"messaging.h\"\n#include \"msgq.h\"\n#include <zmq.h>\n#include <string>\n\n#define MAX_POLLERS 128\n\nclass MSGQContext : public Context {\nprivate:\n  void * context = NULL;\npublic:\n  MSGQContext();\n  void * getRawContext() {return context;}\n  ~MSGQContext();\n};\n\nclass MSGQMessage : public Message {\nprivate:\n  char * data;\n  size_t size;\npublic:\n  void init(size_t size);\n  void init(char *data, size_t size);\n  void takeOwnership(char *data, size_t size);\n  size_t getSize(){return size;}\n  char * getData(){return data;}\n  void close();\n  ~MSGQMessage();\n};\n\nclass MSGQSubSocket : public SubSocket {\nprivate:\n  msgq_queue_t * q = NULL;\n  int timeout;\npublic:\n  int connect(Context *context, std::string endpoint, std::string address, bool conflate=false, bool check_endpoint=true);\n  void setTimeout(int timeout);\n  void * getRawSocket() {return (void*)q;}\n  Message *receive(bool non_blocking=false);\n  ~MSGQSubSocket();\n};\n\nclass MSGQPubSocket : public PubSocket {\nprivate:\n  msgq_queue_t * q = NULL;\npublic:\n  int connect(Context *context, std::string endpoint, bool check_endpoint=true);\n  int sendMessage(Message *message);\n  int send(char *data, size_t size);\n  bool all_readers_updated();\n  ~MSGQPubSocket();\n};\n\nclass MSGQPoller : public Poller {\nprivate:\n  std::vector<SubSocket*> sockets;\n  msgq_pollitem_t polls[MAX_POLLERS];\n  size_t num_polls = 0;\n\npublic:\n  void registerSocket(SubSocket *socket);\n  std::vector<SubSocket*> poll(int timeout);\n  ~MSGQPoller(){};\n};\n"
  },
  {
    "path": "cereal/messaging/impl_zmq.cc",
    "content": "#include <cassert>\n#include <cstring>\n#include <iostream>\n#include <cstdlib>\n#include <cerrno>\n\n#include <zmq.h>\n\n#include \"services.h\"\n#include \"impl_zmq.h\"\n\nstatic int get_port(std::string endpoint) {\n  int port = -1;\n  for (const auto& it : services) {\n    std::string name = it.name;\n    if (name == endpoint) {\n      port = it.port;\n      break;\n    }\n  }\n\n  assert(port >= 0);\n  return port;\n}\n\nZMQContext::ZMQContext() {\n  context = zmq_ctx_new();\n}\n\nZMQContext::~ZMQContext() {\n  zmq_ctx_term(context);\n}\n\nvoid ZMQMessage::init(size_t sz) {\n  size = sz;\n  data = new char[size];\n}\n\nvoid ZMQMessage::init(char * d, size_t sz) {\n  size = sz;\n  data = new char[size];\n  memcpy(data, d, size);\n}\n\nvoid ZMQMessage::close() {\n  if (size > 0){\n    delete[] data;\n  }\n  size = 0;\n}\n\nZMQMessage::~ZMQMessage() {\n  this->close();\n}\n\n\nint ZMQSubSocket::connect(Context *context, std::string endpoint, std::string address, bool conflate, bool check_endpoint){\n  sock = zmq_socket(context->getRawContext(), ZMQ_SUB);\n  if (sock == NULL){\n    return -1;\n  }\n\n  zmq_setsockopt(sock, ZMQ_SUBSCRIBE, \"\", 0);\n\n  if (conflate){\n    int arg = 1;\n    zmq_setsockopt(sock, ZMQ_CONFLATE, &arg, sizeof(int));\n  }\n\n  int reconnect_ivl = 500;\n  zmq_setsockopt(sock, ZMQ_RECONNECT_IVL_MAX, &reconnect_ivl, sizeof(reconnect_ivl));\n\n  full_endpoint = \"tcp://\" + address + \":\";\n  if (check_endpoint){\n    full_endpoint += std::to_string(get_port(endpoint));\n  } else {\n    full_endpoint += endpoint;\n  }\n\n  return zmq_connect(sock, full_endpoint.c_str());\n}\n\n\nMessage * ZMQSubSocket::receive(bool non_blocking){\n  zmq_msg_t msg;\n  assert(zmq_msg_init(&msg) == 0);\n\n  int flags = non_blocking ? ZMQ_DONTWAIT : 0;\n  int rc = zmq_msg_recv(&msg, sock, flags);\n  Message *r = NULL;\n\n  if (rc >= 0){\n    // Make a copy to ensure the data is aligned\n    r = new ZMQMessage;\n    r->init((char*)zmq_msg_data(&msg), zmq_msg_size(&msg));\n  }\n\n  zmq_msg_close(&msg);\n  return r;\n}\n\nvoid ZMQSubSocket::setTimeout(int timeout){\n  zmq_setsockopt(sock, ZMQ_RCVTIMEO, &timeout, sizeof(int));\n}\n\nZMQSubSocket::~ZMQSubSocket(){\n  zmq_close(sock);\n}\n\nint ZMQPubSocket::connect(Context *context, std::string endpoint, bool check_endpoint){\n  sock = zmq_socket(context->getRawContext(), ZMQ_PUB);\n  if (sock == NULL){\n    return -1;\n  }\n\n  full_endpoint = \"tcp://*:\";\n  if (check_endpoint){\n    full_endpoint += std::to_string(get_port(endpoint));\n  } else {\n    full_endpoint += endpoint;\n  }\n\n  return zmq_bind(sock, full_endpoint.c_str());\n}\n\nint ZMQPubSocket::sendMessage(Message *message){\n  return zmq_send(sock, message->getData(), message->getSize(), ZMQ_DONTWAIT);\n}\n\nint ZMQPubSocket::send(char *data, size_t size){\n  return zmq_send(sock, data, size, ZMQ_DONTWAIT);\n}\n\nbool ZMQPubSocket::all_readers_updated() {\n  assert(false); // TODO not implemented\n  return false;\n}\n\nZMQPubSocket::~ZMQPubSocket(){\n  zmq_close(sock);\n}\n\n\nvoid ZMQPoller::registerSocket(SubSocket * socket){\n  assert(num_polls + 1 < MAX_POLLERS);\n  polls[num_polls].socket = socket->getRawSocket();\n  polls[num_polls].events = ZMQ_POLLIN;\n\n  sockets.push_back(socket);\n  num_polls++;\n}\n\nstd::vector<SubSocket*> ZMQPoller::poll(int timeout){\n  std::vector<SubSocket*> r;\n\n  int rc = zmq_poll(polls, num_polls, timeout);\n  if (rc < 0){\n    return r;\n  }\n\n  for (size_t i = 0; i < num_polls; i++){\n    if (polls[i].revents){\n      r.push_back(sockets[i]);\n    }\n  }\n\n  return r;\n}\n"
  },
  {
    "path": "cereal/messaging/impl_zmq.h",
    "content": "#pragma once\n#include \"messaging.h\"\n#include <zmq.h>\n#include <string>\n\n#define MAX_POLLERS 128\n\nclass ZMQContext : public Context {\nprivate:\n  void * context = NULL;\npublic:\n  ZMQContext();\n  void * getRawContext() {return context;}\n  ~ZMQContext();\n};\n\nclass ZMQMessage : public Message {\nprivate:\n  char * data;\n  size_t size;\npublic:\n  void init(size_t size);\n  void init(char *data, size_t size);\n  size_t getSize(){return size;}\n  char * getData(){return data;}\n  void close();\n  ~ZMQMessage();\n};\n\nclass ZMQSubSocket : public SubSocket {\nprivate:\n  void * sock;\n  std::string full_endpoint;\npublic:\n  int connect(Context *context, std::string endpoint, std::string address, bool conflate=false, bool check_endpoint=true);\n  void setTimeout(int timeout);\n  void * getRawSocket() {return sock;}\n  Message *receive(bool non_blocking=false);\n  ~ZMQSubSocket();\n};\n\nclass ZMQPubSocket : public PubSocket {\nprivate:\n  void * sock;\n  std::string full_endpoint;\npublic:\n  int connect(Context *context, std::string endpoint, bool check_endpoint=true);\n  int sendMessage(Message *message);\n  int send(char *data, size_t size);\n  bool all_readers_updated();\n  ~ZMQPubSocket();\n};\n\nclass ZMQPoller : public Poller {\nprivate:\n  std::vector<SubSocket*> sockets;\n  zmq_pollitem_t polls[MAX_POLLERS];\n  size_t num_polls = 0;\n\npublic:\n  void registerSocket(SubSocket *socket);\n  std::vector<SubSocket*> poll(int timeout);\n  ~ZMQPoller(){};\n};\n"
  },
  {
    "path": "cereal/messaging/messaging.cc",
    "content": "#include \"messaging.h\"\n#include \"impl_zmq.h\"\n#include \"impl_msgq.h\"\n\n#ifdef __APPLE__\nconst bool MUST_USE_ZMQ = true;\n#else\nconst bool MUST_USE_ZMQ = false;\n#endif\n\nbool messaging_use_zmq(){\n  return std::getenv(\"ZMQ\") || MUST_USE_ZMQ;\n}\n\nContext * Context::create(){\n  Context * c;\n  if (messaging_use_zmq()){\n    c = new ZMQContext();\n  } else {\n    c = new MSGQContext();\n  }\n  return c;\n}\n\nSubSocket * SubSocket::create(){\n  SubSocket * s;\n  if (messaging_use_zmq()){\n    s = new ZMQSubSocket();\n  } else {\n    s = new MSGQSubSocket();\n  }\n  return s;\n}\n\nSubSocket * SubSocket::create(Context * context, std::string endpoint, std::string address, bool conflate, bool check_endpoint){\n  SubSocket *s = SubSocket::create();\n  int r = s->connect(context, endpoint, address, conflate, check_endpoint);\n\n  if (r == 0) {\n    return s;\n  } else {\n    delete s;\n    return NULL;\n  }\n}\n\nPubSocket * PubSocket::create(){\n  PubSocket * s;\n  if (messaging_use_zmq()){\n    s = new ZMQPubSocket();\n  } else {\n    s = new MSGQPubSocket();\n  }\n  return s;\n}\n\nPubSocket * PubSocket::create(Context * context, std::string endpoint, bool check_endpoint){\n  PubSocket *s = PubSocket::create();\n  int r = s->connect(context, endpoint, check_endpoint);\n\n  if (r == 0) {\n    return s;\n  } else {\n    delete s;\n    return NULL;\n  }\n}\n\nPoller * Poller::create(){\n  Poller * p;\n  if (messaging_use_zmq()){\n    p = new ZMQPoller();\n  } else {\n    p = new MSGQPoller();\n  }\n  return p;\n}\n\nPoller * Poller::create(std::vector<SubSocket*> sockets){\n  Poller * p = Poller::create();\n\n  for (auto s : sockets){\n    p->registerSocket(s);\n  }\n  return p;\n}\n\nextern \"C\" Context * messaging_context_create() {\n  return Context::create();\n}\n\nextern \"C\" SubSocket * messaging_subsocket_create(Context* context, const char* endpoint) {\n  return SubSocket::create(context, std::string(endpoint));\n}\n\nextern \"C\" PubSocket * messaging_pubsocket_create(Context* context, const char* endpoint) {\n  return PubSocket::create(context, std::string(endpoint));\n}\n\nextern \"C\" Poller * messaging_poller_create(SubSocket** sockets, int size) {\n  std::vector<SubSocket*> socketsVec(sockets, sockets + size);\n  return Poller::create(socketsVec);\n}\n"
  },
  {
    "path": "cereal/messaging/messaging.h",
    "content": "#pragma once\n#include <cstddef>\n#include <map>\n#include <string>\n#include <vector>\n#include <capnp/serialize.h>\n#include \"../gen/cpp/log.capnp.h\"\n\n#ifdef __APPLE__\n#define CLOCK_BOOTTIME CLOCK_MONOTONIC\n#endif\n\n#define MSG_MULTIPLE_PUBLISHERS 100\n\nbool messaging_use_zmq();\n\nclass Context {\npublic:\n  virtual void * getRawContext() = 0;\n  static Context * create();\n  virtual ~Context(){};\n};\n\nclass Message {\npublic:\n  virtual void init(size_t size) = 0;\n  virtual void init(char * data, size_t size) = 0;\n  virtual void close() = 0;\n  virtual size_t getSize() = 0;\n  virtual char * getData() = 0;\n  virtual ~Message(){};\n};\n\n\nclass SubSocket {\npublic:\n  virtual int connect(Context *context, std::string endpoint, std::string address, bool conflate=false, bool check_endpoint=true) = 0;\n  virtual void setTimeout(int timeout) = 0;\n  virtual Message *receive(bool non_blocking=false) = 0;\n  virtual void * getRawSocket() = 0;\n  static SubSocket * create();\n  static SubSocket * create(Context * context, std::string endpoint, std::string address=\"127.0.0.1\", bool conflate=false, bool check_endpoint=true);\n  virtual ~SubSocket(){};\n};\n\nclass PubSocket {\npublic:\n  virtual int connect(Context *context, std::string endpoint, bool check_endpoint=true) = 0;\n  virtual int sendMessage(Message *message) = 0;\n  virtual int send(char *data, size_t size) = 0;\n  virtual bool all_readers_updated() = 0;\n  static PubSocket * create();\n  static PubSocket * create(Context * context, std::string endpoint, bool check_endpoint=true);\n  static PubSocket * create(Context * context, std::string endpoint, int port, bool check_endpoint=true);\n  virtual ~PubSocket(){};\n};\n\nclass Poller {\npublic:\n  virtual void registerSocket(SubSocket *socket) = 0;\n  virtual std::vector<SubSocket*> poll(int timeout) = 0;\n  static Poller * create();\n  static Poller * create(std::vector<SubSocket*> sockets);\n  virtual ~Poller(){};\n};\n\nclass SubMaster {\npublic:\n  SubMaster(const std::vector<const char *> &service_list,\n            const char *address = nullptr, const std::vector<const char *> &ignore_alive = {});\n  void update(int timeout = 1000);\n  void update_msgs(uint64_t current_time, const std::vector<std::pair<std::string, cereal::Event::Reader>> &messages);\n  inline bool allAlive(const std::vector<const char *> &service_list = {}) { return all_(service_list, false, true); }\n  inline bool allValid(const std::vector<const char *> &service_list = {}) { return all_(service_list, true, false); }\n  inline bool allAliveAndValid(const std::vector<const char *> &service_list = {}) { return all_(service_list, true, true); }\n  void drain();\n  ~SubMaster();\n\n  uint64_t frame = 0;\n  bool updated(const char *name) const;\n  bool alive(const char *name) const;\n  bool valid(const char *name) const;\n  uint64_t rcv_frame(const char *name) const;\n  uint64_t rcv_time(const char *name) const;\n  cereal::Event::Reader &operator[](const char *name) const;\n\nprivate:\n  bool all_(const std::vector<const char *> &service_list, bool valid, bool alive);\n  Poller *poller_ = nullptr;\n  struct SubMessage;\n  std::map<SubSocket *, SubMessage *> messages_;\n  std::map<std::string, SubMessage *> services_;\n};\n\nclass MessageBuilder : public capnp::MallocMessageBuilder {\npublic:\n  MessageBuilder() = default;\n\n  cereal::Event::Builder initEvent(bool valid = true) {\n    cereal::Event::Builder event = initRoot<cereal::Event>();\n    struct timespec t;\n    clock_gettime(CLOCK_BOOTTIME, &t);\n    uint64_t current_time = t.tv_sec * 1000000000ULL + t.tv_nsec;\n    event.setLogMonoTime(current_time);\n    event.setValid(valid);\n    return event;\n  }\n\n  kj::ArrayPtr<capnp::byte> toBytes() {\n    heapArray_ = capnp::messageToFlatArray(*this);\n    return heapArray_.asBytes();\n  }\n\nprivate:\n  kj::Array<capnp::word> heapArray_;\n};\n\nclass PubMaster {\npublic:\n  PubMaster(const std::vector<const char *> &service_list);\n  inline int send(const char *name, capnp::byte *data, size_t size) { return sockets_.at(name)->send((char *)data, size); }\n  int send(const char *name, MessageBuilder &msg);\n  ~PubMaster();\n\nprivate:\n  std::map<std::string, PubSocket *> sockets_;\n};\n\nclass AlignedBuffer {\npublic:\n  kj::ArrayPtr<const capnp::word> align(const char *data, const size_t size) {\n    words_size = size / sizeof(capnp::word) + 1;\n    if (aligned_buf.size() < words_size) {\n      aligned_buf = kj::heapArray<capnp::word>(words_size < 512 ? 512 : words_size);\n    }\n    memcpy(aligned_buf.begin(), data, size);\n    return aligned_buf.slice(0, words_size);\n  }\n  inline kj::ArrayPtr<const capnp::word> align(Message *m) {\n    return align(m->getData(), m->getSize());\n  }\nprivate:\n  kj::Array<capnp::word> aligned_buf;\n  size_t words_size;\n};\n"
  },
  {
    "path": "cereal/messaging/messaging.pxd",
    "content": "# distutils: language = c++\n#cython: language_level=3\n\nfrom libcpp.string cimport string\nfrom libcpp.vector cimport vector\nfrom libcpp cimport bool\n\n\ncdef extern from \"messaging.h\":\n  cdef cppclass Context:\n    @staticmethod\n    Context * create()\n\n  cdef cppclass Message:\n    void init(size_t)\n    void init(char *, size_t)\n    void close()\n    size_t getSize()\n    char *getData()\n\n  cdef cppclass SubSocket:\n    @staticmethod\n    SubSocket * create()\n    int connect(Context *, string, string, bool)\n    Message * receive(bool)\n    void setTimeout(int)\n\n  cdef cppclass PubSocket:\n    @staticmethod\n    PubSocket * create()\n    int connect(Context *, string)\n    int sendMessage(Message *)\n    int send(char *, size_t)\n    bool all_readers_updated()\n\n  cdef cppclass Poller:\n    @staticmethod\n    Poller * create()\n    void registerSocket(SubSocket *)\n    vector[SubSocket*] poll(int) nogil\n"
  },
  {
    "path": "cereal/messaging/messaging_pyx.pyx",
    "content": "# distutils: language = c++\n# cython: c_string_encoding=ascii, language_level=3\n\nimport sys\nfrom libcpp.string cimport string\nfrom libcpp cimport bool\nfrom libc cimport errno\n\n\nfrom .messaging cimport Context as cppContext\nfrom .messaging cimport SubSocket as cppSubSocket\nfrom .messaging cimport PubSocket as cppPubSocket\nfrom .messaging cimport Poller as cppPoller\nfrom .messaging cimport Message as cppMessage\n\n\nclass MessagingError(Exception):\n  pass\n\n\nclass MultiplePublishersError(MessagingError):\n  pass\n\n\ncdef class Context:\n  cdef cppContext * context\n\n  def __cinit__(self):\n    self.context = cppContext.create()\n\n  def term(self):\n    del self.context\n    self.context = NULL\n\n  def __dealloc__(self):\n    pass\n    # Deleting the context will hang if sockets are still active\n    # TODO: Figure out a way to make sure the context is closed last\n    # del self.context\n\n\ncdef class Poller:\n  cdef cppPoller * poller\n  cdef list sub_sockets\n\n  def __cinit__(self):\n    self.sub_sockets = []\n    self.poller = cppPoller.create()\n\n  def __dealloc__(self):\n    del self.poller\n\n  def registerSocket(self, SubSocket socket):\n    self.sub_sockets.append(socket)\n    self.poller.registerSocket(socket.socket)\n\n  def poll(self, timeout):\n    sockets = []\n    cdef int t = timeout\n\n    with nogil:\n      result = self.poller.poll(t)\n\n    for s in result:\n      socket = SubSocket()\n      socket.setPtr(s)\n      sockets.append(socket)\n\n    return sockets\n\ncdef class SubSocket:\n  cdef cppSubSocket * socket\n  cdef bool is_owner\n\n  def __cinit__(self):\n    self.socket = cppSubSocket.create()\n    self.is_owner = True\n\n    if self.socket == NULL:\n      raise MessagingError\n\n  def __dealloc__(self):\n    if self.is_owner:\n      del self.socket\n\n  cdef setPtr(self, cppSubSocket * ptr):\n    if self.is_owner:\n      del self.socket\n\n    self.is_owner = False\n    self.socket = ptr\n\n  def connect(self, Context context, string endpoint, string address=b\"127.0.0.1\", bool conflate=False):\n    r = self.socket.connect(context.context, endpoint, address, conflate)\n\n    if r != 0:\n      if errno.errno == errno.EADDRINUSE:\n        raise MultiplePublishersError\n      else:\n        raise MessagingError\n\n  def setTimeout(self, int timeout):\n    self.socket.setTimeout(timeout)\n\n  def receive(self, bool non_blocking=False):\n    msg = self.socket.receive(non_blocking)\n\n    if msg == NULL:\n      # If a blocking read returns no message check errno if SIGINT was caught in the C++ code\n      if errno.errno == errno.EINTR:\n        print(\"SIGINT received, exiting\")\n        sys.exit(1)\n\n      return None\n    else:\n      sz = msg.getSize()\n      m = msg.getData()[:sz]\n      del msg\n\n      return m\n\n\ncdef class PubSocket:\n  cdef cppPubSocket * socket\n\n  def __cinit__(self):\n    self.socket = cppPubSocket.create()\n    if self.socket == NULL:\n      raise MessagingError\n\n  def __dealloc__(self):\n    del self.socket\n\n  def connect(self, Context context, string endpoint):\n    r = self.socket.connect(context.context, endpoint)\n\n    if r != 0:\n      if errno.errno == errno.EADDRINUSE:\n        raise MultiplePublishersError\n      else:\n        raise MessagingError\n\n  def send(self, bytes data):\n    length = len(data)\n    r = self.socket.send(<char*>data, length)\n\n    if r != length:\n      if errno.errno == errno.EADDRINUSE:\n        raise MultiplePublishersError\n      else:\n        raise MessagingError\n\n  def all_readers_updated(self):\n    return self.socket.all_readers_updated()\n"
  },
  {
    "path": "cereal/messaging/msgq.cc",
    "content": "#include <iostream>\n#include <cassert>\n#include <cerrno>\n#include <cmath>\n#include <cstring>\n#include <cstdint>\n#include <chrono>\n#include <algorithm>\n#include <cstdlib>\n#include <csignal>\n#include <random>\n\n#include <poll.h>\n#include <sys/ioctl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/syscall.h>\n#include <fcntl.h>\n#include <unistd.h>\n\n#include <stdio.h>\n\n#include \"msgq.h\"\n\nvoid sigusr2_handler(int signal) {\n  assert(signal == SIGUSR2);\n}\n\nuint64_t msgq_get_uid(void){\n  std::random_device rd(\"/dev/urandom\");\n  std::uniform_int_distribution<uint64_t> distribution(0,std::numeric_limits<uint32_t>::max());\n\n  #ifdef __APPLE__\n    // TODO: this doesn't work\n    uint64_t uid = distribution(rd) << 32 | getpid();\n  #else\n    uint64_t uid = distribution(rd) << 32 | syscall(SYS_gettid);\n  #endif\n\n  return uid;\n}\n\nint msgq_msg_init_size(msgq_msg_t * msg, size_t size){\n  msg->size = size;\n  msg->data = new(std::nothrow) char[size];\n\n  return (msg->data == NULL) ? -1 : 0;\n}\n\n\nint msgq_msg_init_data(msgq_msg_t * msg, char * data, size_t size) {\n  int r = msgq_msg_init_size(msg, size);\n\n  if (r == 0)\n    memcpy(msg->data, data, size);\n\n  return r;\n}\n\nint msgq_msg_close(msgq_msg_t * msg){\n  if (msg->size > 0)\n    delete[] msg->data;\n\n  msg->size = 0;\n\n  return 0;\n}\n\nvoid msgq_reset_reader(msgq_queue_t * q){\n  int id = q->reader_id;\n  q->read_valids[id]->store(true);\n  q->read_pointers[id]->store(*q->write_pointer);\n}\n\nvoid msgq_wait_for_subscriber(msgq_queue_t *q){\n  while (*q->num_readers == 0){\n    ;\n  }\n\n  return;\n}\n\n\nint msgq_new_queue(msgq_queue_t * q, const char * path, size_t size){\n  assert(size < 0xFFFFFFFF); // Buffer must be smaller than 2^32 bytes\n  std::signal(SIGUSR2, sigusr2_handler);\n\n  const char * prefix = \"/dev/shm/\";\n  char * full_path = new char[strlen(path) + strlen(prefix) + 1];\n  strcpy(full_path, prefix);\n  strcat(full_path, path);\n\n  auto fd = open(full_path, O_RDWR | O_CREAT, 0664);\n  if (fd < 0) {\n    std::cout << \"Warning, could not open: \" << full_path << std::endl;\n    delete[] full_path;\n    return -1;\n  }\n  delete[] full_path;\n\n  int rc = ftruncate(fd, size + sizeof(msgq_header_t));\n  if (rc < 0){\n    close(fd);\n    return -1;\n  }\n  char * mem = (char*)mmap(NULL, size + sizeof(msgq_header_t), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n  close(fd);\n\n  if (mem == NULL){\n    return -1;\n  }\n  q->mmap_p = mem;\n\n  msgq_header_t *header = (msgq_header_t *)mem;\n\n  // Setup pointers to header segment\n  q->num_readers = reinterpret_cast<std::atomic<uint64_t>*>(&header->num_readers);\n  q->write_pointer = reinterpret_cast<std::atomic<uint64_t>*>(&header->write_pointer);\n  q->write_uid = reinterpret_cast<std::atomic<uint64_t>*>(&header->write_uid);\n\n  for (size_t i = 0; i < NUM_READERS; i++){\n    q->read_pointers[i] = reinterpret_cast<std::atomic<uint64_t>*>(&header->read_pointers[i]);\n    q->read_valids[i] = reinterpret_cast<std::atomic<uint64_t>*>(&header->read_valids[i]);\n    q->read_uids[i] = reinterpret_cast<std::atomic<uint64_t>*>(&header->read_uids[i]);\n  }\n\n  q->data = mem + sizeof(msgq_header_t);\n  q->size = size;\n  q->reader_id = -1;\n\n  q->endpoint = path;\n  q->read_conflate = false;\n\n  return 0;\n}\n\nvoid msgq_close_queue(msgq_queue_t *q){\n  if (q->mmap_p != NULL){\n    munmap(q->mmap_p, q->size + sizeof(msgq_header_t));\n  }\n}\n\n\nvoid msgq_init_publisher(msgq_queue_t * q) {\n  //std::cout << \"Starting publisher\" << std::endl;\n  uint64_t uid = msgq_get_uid();\n\n  *q->write_uid = uid;\n  *q->num_readers = 0;\n\n  for (size_t i = 0; i < NUM_READERS; i++){\n    *q->read_valids[i] = false;\n    *q->read_uids[i] = 0;\n  }\n\n  q->write_uid_local = uid;\n}\n\nstatic void thread_signal(uint32_t tid) {\n  #ifndef SYS_tkill\n    // TODO: this won't work for multithreaded programs\n    kill(tid, SIGUSR2);\n  #else\n    syscall(SYS_tkill, tid, SIGUSR2);\n  #endif\n}\n\nvoid msgq_init_subscriber(msgq_queue_t * q) {\n  assert(q != NULL);\n  assert(q->num_readers != NULL);\n\n  uint64_t uid = msgq_get_uid();\n\n  // Get reader id\n  while (true){\n    uint64_t cur_num_readers = *q->num_readers;\n    uint64_t new_num_readers = cur_num_readers + 1;\n\n    // No more slots available. Reset all subscribers to kick out inactive ones\n    if (new_num_readers > NUM_READERS){\n      std::cout << \"Warning, evicting all subscribers!\" << std::endl;\n      *q->num_readers = 0;\n\n      for (size_t i = 0; i < NUM_READERS; i++){\n        *q->read_valids[i] = false;\n\n        uint64_t old_uid = *q->read_uids[i];\n        *q->read_uids[i] = 0;\n\n        // Wake up reader in case they are in a poll\n        thread_signal(old_uid & 0xFFFFFFFF);\n      }\n\n      continue;\n    }\n\n    // Use atomic compare and swap to handle race condition\n    // where two subscribers start at the same time\n    if (std::atomic_compare_exchange_strong(q->num_readers,\n                                            &cur_num_readers,\n                                            new_num_readers)){\n      q->reader_id = cur_num_readers;\n      q->read_uid_local = uid;\n\n      // We start with read_valid = false,\n      // on the first read the read pointer will be synchronized with the write pointer\n      *q->read_valids[cur_num_readers] = false;\n      *q->read_pointers[cur_num_readers] = 0;\n      *q->read_uids[cur_num_readers] = uid;\n      break;\n    }\n  }\n\n  //std::cout << \"New subscriber id: \" << q->reader_id << \" uid: \" << q->read_uid_local << \" \" << q->endpoint << std::endl;\n  msgq_reset_reader(q);\n}\n\nint msgq_msg_send(msgq_msg_t * msg, msgq_queue_t *q){\n  // Die if we are no longer the active publisher\n  if (q->write_uid_local != *q->write_uid){\n    std::cout << \"Killing old publisher: \" << q->endpoint << std::endl;\n    errno = EADDRINUSE;\n    return -1;\n  }\n\n  uint64_t total_msg_size = ALIGN(msg->size + sizeof(int64_t));\n\n  // We need to fit at least three messages in the queue,\n  // then we can always safely access the last message\n  assert(3 * total_msg_size <= q->size);\n\n  uint64_t num_readers = *q->num_readers;\n\n  uint32_t write_cycles, write_pointer;\n  UNPACK64(write_cycles, write_pointer, *q->write_pointer);\n\n  char *p = q->data + write_pointer; // add base offset\n\n  // Check remaining space\n  // Always leave space for a wraparound tag for the next message, including alignment\n  int64_t remaining_space = q->size - write_pointer - total_msg_size - sizeof(int64_t);\n  if (remaining_space <= 0){\n    // Write -1 size tag indicating wraparound\n    *(int64_t*)p = -1;\n\n    // Invalidate all readers that are beyond the write pointer\n    // TODO: should we handle the case where a new reader shows up while this is running?\n    for (uint64_t i = 0; i < num_readers; i++){\n      uint64_t read_pointer = *q->read_pointers[i];\n      uint64_t read_cycles = read_pointer >> 32;\n      read_pointer &= 0xFFFFFFFF;\n\n      if ((read_pointer > write_pointer) && (read_cycles != write_cycles)) {\n        *q->read_valids[i] = false;\n      }\n    }\n\n    // Update global and local copies of write pointer and write_cycles\n    write_pointer = 0;\n    write_cycles = write_cycles + 1;\n    PACK64(*q->write_pointer, write_cycles, write_pointer);\n\n    // Set actual pointer to the beginning of the data segment\n    p = q->data;\n  }\n\n  // Invalidate readers that are in the area that will be written\n  uint64_t start = write_pointer;\n  uint64_t end = ALIGN(start + sizeof(int64_t) + msg->size);\n\n  for (uint64_t i = 0; i < num_readers; i++){\n    uint32_t read_cycles, read_pointer;\n    UNPACK64(read_cycles, read_pointer, *q->read_pointers[i]);\n\n    if ((read_pointer >= start) && (read_pointer < end) && (read_cycles != write_cycles)) {\n      *q->read_valids[i] = false;\n    }\n  }\n\n\n  // Write size tag\n  std::atomic<int64_t> *size_p = reinterpret_cast<std::atomic<int64_t>*>(p);\n  *size_p = msg->size;\n\n  // Copy data\n  memcpy(p + sizeof(int64_t), msg->data, msg->size);\n  __sync_synchronize();\n\n  // Update write pointer\n  uint32_t new_ptr = ALIGN(write_pointer + msg->size + sizeof(int64_t));\n  PACK64(*q->write_pointer, write_cycles, new_ptr);\n\n  // Notify readers\n  for (uint64_t i = 0; i < num_readers; i++){\n    uint64_t reader_uid = *q->read_uids[i];\n    thread_signal(reader_uid & 0xFFFFFFFF);\n  }\n\n  return msg->size;\n}\n\n\nint msgq_msg_ready(msgq_queue_t * q){\n start:\n  int id = q->reader_id;\n  assert(id >= 0); // Make sure subscriber is initialized\n\n  if (q->read_uid_local != *q->read_uids[id]){\n    std::cout << q->endpoint << \": Reader was evicted, reconnecting\" << std::endl;\n    msgq_init_subscriber(q);\n    goto start;\n  }\n\n  // Check valid\n  if (!*q->read_valids[id]){\n    msgq_reset_reader(q);\n    goto start;\n  }\n\n  uint32_t read_cycles, read_pointer;\n  UNPACK64(read_cycles, read_pointer, *q->read_pointers[id]);\n\n  uint32_t write_cycles, write_pointer;\n  UNPACK64(write_cycles, write_pointer, *q->write_pointer);\n\n  // Check if new message is available\n  return (read_pointer != write_pointer);\n}\n\nint msgq_msg_recv(msgq_msg_t * msg, msgq_queue_t * q){\n start:\n  int id = q->reader_id;\n  assert(id >= 0); // Make sure subscriber is initialized\n\n  if (q->read_uid_local != *q->read_uids[id]){\n    std::cout << q->endpoint << \": Reader was evicted, reconnecting\" << std::endl;\n    msgq_init_subscriber(q);\n    goto start;\n  }\n\n  // Check valid\n  if (!*q->read_valids[id]){\n    msgq_reset_reader(q);\n    goto start;\n  }\n\n  uint32_t read_cycles, read_pointer;\n  UNPACK64(read_cycles, read_pointer, *q->read_pointers[id]);\n\n  uint32_t write_cycles, write_pointer;\n  UNPACK64(write_cycles, write_pointer, *q->write_pointer);\n\n  char * p = q->data + read_pointer;\n\n  // Check if new message is available\n  if (read_pointer == write_pointer) {\n    msg->size = 0;\n    return 0;\n  }\n\n  // Read potential message size\n  std::atomic<int64_t> *size_p = reinterpret_cast<std::atomic<int64_t>*>(p);\n  std::int64_t size = *size_p;\n\n  // Check if the size that was read is valid\n  if (!*q->read_valids[id]){\n    msgq_reset_reader(q);\n    goto start;\n  }\n\n  // If size is -1 the buffer was full, and we need to wrap around\n  if (size == -1){\n    read_cycles++;\n    PACK64(*q->read_pointers[id], read_cycles, 0);\n    goto start;\n  }\n\n  // crashing is better than passing garbage data to the consumer\n  // the size will have weird value if it was overwritten by data accidentally\n  assert((uint64_t)size < q->size);\n  assert(size > 0);\n\n  uint32_t new_read_pointer = ALIGN(read_pointer + sizeof(std::int64_t) + size);\n\n  // If conflate is true, check if this is the latest message, else start over\n  if (q->read_conflate){\n    if (new_read_pointer != write_pointer){\n      // Update read pointer\n      PACK64(*q->read_pointers[id], read_cycles, new_read_pointer);\n      goto start;\n    }\n  }\n\n  // Copy message\n  if (msgq_msg_init_size(msg, size) < 0)\n    return -1;\n\n  __sync_synchronize();\n  memcpy(msg->data, p + sizeof(int64_t), size);\n  __sync_synchronize();\n\n  // Update read pointer\n  PACK64(*q->read_pointers[id], read_cycles, new_read_pointer);\n\n  // Check if the actual data that was copied is valid\n  if (!*q->read_valids[id]){\n    msgq_msg_close(msg);\n    msgq_reset_reader(q);\n    goto start;\n  }\n\n\n  return msg->size;\n}\n\n\n\nint msgq_poll(msgq_pollitem_t * items, size_t nitems, int timeout){\n  int num = 0;\n\n  // Check if messages ready\n  for (size_t i = 0; i < nitems; i++) {\n    items[i].revents = msgq_msg_ready(items[i].q);\n    if (items[i].revents) num++;\n  }\n\n  int ms = (timeout == -1) ? 100 : timeout;\n  struct timespec ts;\n  ts.tv_sec = ms / 1000;\n  ts.tv_nsec = (ms % 1000) * 1000 * 1000;\n\n\n  while (num == 0) {\n    int ret;\n\n    ret = nanosleep(&ts, &ts);\n\n    // Check if messages ready\n    for (size_t i = 0; i < nitems; i++) {\n      if (items[i].revents == 0 && msgq_msg_ready(items[i].q)){\n        num += 1;\n        items[i].revents = 1;\n      }\n    }\n\n    // exit if we had a timeout and the sleep finished\n    if (timeout != -1 && ret == 0){\n      break;\n    }\n  }\n\n  return num;\n}\n\nbool msgq_all_readers_updated(msgq_queue_t *q) {\n  uint64_t num_readers = *q->num_readers;\n  for (uint64_t i = 0; i < num_readers; i++) {\n    if (*q->read_valids[i] && *q->write_pointer != *q->read_pointers[i]) {\n      return false;\n    }\n  }\n  return num_readers > 0;\n}\n"
  },
  {
    "path": "cereal/messaging/msgq.h",
    "content": "#pragma once\n#include <cstdint>\n#include <cstring>\n#include <string>\n#include <atomic>\n\n#define DEFAULT_SEGMENT_SIZE (10 * 1024 * 1024)\n#define NUM_READERS 10\n#define ALIGN(n) ((n + (8 - 1)) & -8)\n\n#define UNPACK64(higher, lower, input) do {uint64_t tmp = input; higher = tmp >> 32; lower = tmp & 0xFFFFFFFF;} while (0)\n#define PACK64(output, higher, lower) output = ((uint64_t)higher << 32 ) | ((uint64_t)lower & 0xFFFFFFFF)\n\nstruct  msgq_header_t {\n  uint64_t num_readers;\n  uint64_t write_pointer;\n  uint64_t write_uid;\n  uint64_t read_pointers[NUM_READERS];\n  uint64_t read_valids[NUM_READERS];\n  uint64_t read_uids[NUM_READERS];\n};\n\nstruct msgq_queue_t {\n  std::atomic<uint64_t> *num_readers;\n  std::atomic<uint64_t> *write_pointer;\n  std::atomic<uint64_t> *write_uid;\n  std::atomic<uint64_t> *read_pointers[NUM_READERS];\n  std::atomic<uint64_t> *read_valids[NUM_READERS];\n  std::atomic<uint64_t> *read_uids[NUM_READERS];\n  char * mmap_p;\n  char * data;\n  size_t size;\n  int reader_id;\n  uint64_t read_uid_local;\n  uint64_t write_uid_local;\n\n  bool read_conflate;\n  std::string endpoint;\n};\n\nstruct msgq_msg_t {\n  size_t size;\n  char * data;\n};\n\nstruct msgq_pollitem_t {\n  msgq_queue_t *q;\n  int revents;\n};\n\nvoid msgq_wait_for_subscriber(msgq_queue_t *q);\nvoid msgq_reset_reader(msgq_queue_t *q);\n\nint msgq_msg_init_size(msgq_msg_t *msg, size_t size);\nint msgq_msg_init_data(msgq_msg_t *msg, char * data, size_t size);\nint msgq_msg_close(msgq_msg_t *msg);\n\nint msgq_new_queue(msgq_queue_t * q, const char * path, size_t size);\nvoid msgq_close_queue(msgq_queue_t *q);\nvoid msgq_init_publisher(msgq_queue_t * q);\nvoid msgq_init_subscriber(msgq_queue_t * q);\n\nint msgq_msg_send(msgq_msg_t *msg, msgq_queue_t *q);\nint msgq_msg_recv(msgq_msg_t *msg, msgq_queue_t *q);\nint msgq_msg_ready(msgq_queue_t * q);\nint msgq_poll(msgq_pollitem_t * items, size_t nitems, int timeout);\n\nbool msgq_all_readers_updated(msgq_queue_t *q);\n"
  },
  {
    "path": "cereal/messaging/socketmaster.cc",
    "content": "#include <time.h>\n#include <assert.h>\n#include <stdlib.h>\n#include <string>\n#include <mutex>\n\n#include \"services.h\"\n#include \"messaging.h\"\n\nconst bool SIMULATION = (getenv(\"SIMULATION\") != nullptr) && (std::string(getenv(\"SIMULATION\")) == \"1\");\n\nstatic inline uint64_t nanos_since_boot() {\n  struct timespec t;\n  clock_gettime(CLOCK_BOOTTIME, &t);\n  return t.tv_sec * 1000000000ULL + t.tv_nsec;\n}\n\nstatic const service *get_service(const char *name) {\n  for (const auto &it : services) {\n    if (strcmp(it.name, name) == 0) return &it;\n  }\n  return nullptr;\n}\n\nstatic inline bool inList(const std::vector<const char *> &list, const char *value) {\n  for (auto &v : list) {\n    if (strcmp(value, v) == 0) return true;\n  }\n  return false;\n}\n\nclass MessageContext {\npublic:\n  MessageContext() : ctx_(nullptr) {};\n  ~MessageContext() { delete ctx_; }\n  inline Context *context() {\n    std::call_once(init_flag, [=]() { ctx_ = Context::create(); });\n    return ctx_;\n  }\nprivate:\n  Context *ctx_;\n  std::once_flag init_flag;\n};\n\nMessageContext message_context;\n\nstruct SubMaster::SubMessage {\n  std::string name;\n  SubSocket *socket = nullptr;\n  int freq = 0;\n  bool updated = false, alive = false, valid = true, ignore_alive;\n  uint64_t rcv_time = 0, rcv_frame = 0;\n  void *allocated_msg_reader = nullptr;\n  capnp::FlatArrayMessageReader *msg_reader = nullptr;\n  AlignedBuffer aligned_buf;\n  cereal::Event::Reader event;\n};\n\nSubMaster::SubMaster(const std::vector<const char *> &service_list, const char *address,\n                     const std::vector<const char *> &ignore_alive) {\n  poller_ = Poller::create();\n  for (auto name : service_list) {\n    const service *serv = get_service(name);\n    assert(serv != nullptr);\n    SubSocket *socket = SubSocket::create(message_context.context(), name, address ? address : \"127.0.0.1\", true);\n    assert(socket != 0);\n    poller_->registerSocket(socket);\n    SubMessage *m = new SubMessage{\n      .name = name,\n      .socket = socket,\n      .freq = serv->frequency,\n      .ignore_alive = inList(ignore_alive, name),\n      .allocated_msg_reader = malloc(sizeof(capnp::FlatArrayMessageReader))};\n    m->msg_reader = new (m->allocated_msg_reader) capnp::FlatArrayMessageReader({});\n    messages_[socket] = m;\n    services_[name] = m;\n  }\n}\n\nvoid SubMaster::update(int timeout) {\n  for (auto &kv : messages_) kv.second->updated = false;\n\n  auto sockets = poller_->poll(timeout);\n  uint64_t current_time = nanos_since_boot();\n\n  std::vector<std::pair<std::string, cereal::Event::Reader>> messages;\n\n  for (auto s : sockets) {\n    Message *msg = s->receive(true);\n    if (msg == nullptr) continue;\n\n    SubMessage *m = messages_.at(s);\n\n    m->msg_reader->~FlatArrayMessageReader();\n    capnp::ReaderOptions options;\n    options.traversalLimitInWords = kj::maxValue; // Don't limit\n    m->msg_reader = new (m->allocated_msg_reader) capnp::FlatArrayMessageReader(m->aligned_buf.align(msg), options);\n    delete msg;\n    messages.push_back({m->name, m->msg_reader->getRoot<cereal::Event>()});\n  }\n\n  update_msgs(current_time, messages);\n}\n\nvoid SubMaster::update_msgs(uint64_t current_time, const std::vector<std::pair<std::string, cereal::Event::Reader>> &messages){\n  if (++frame == UINT64_MAX) frame = 1;\n\n  for(auto &kv : messages) {\n    auto m_find = services_.find(kv.first);\n    if (m_find == services_.end()){\n      continue;\n    }\n    SubMessage *m = m_find->second;\n    m->event = kv.second;\n    m->updated = true;\n    m->rcv_time = current_time;\n    m->rcv_frame = frame;\n    m->valid = m->event.getValid();\n    if (SIMULATION) m->alive = true;\n  }\n\n  if (!SIMULATION) {\n    for (auto &kv : messages_) {\n      SubMessage *m = kv.second;\n      m->alive = (m->freq <= (1e-5) || ((current_time - m->rcv_time) * (1e-9)) < (10.0 / m->freq));\n    }\n  }\n}\n\nbool SubMaster::all_(const std::vector<const char *> &service_list, bool valid, bool alive) {\n  int found = 0;\n  for (auto &kv : messages_) {\n    SubMessage *m = kv.second;\n    if (service_list.size() == 0 || inList(service_list, m->name.c_str())) {\n      found += (!valid || m->valid) && (!alive || (m->alive || m->ignore_alive));\n    }\n  }\n  return service_list.size() == 0 ? found == messages_.size() : found == service_list.size();\n}\n\nvoid SubMaster::drain() {\n  while (true) {\n    auto polls = poller_->poll(0);\n    if (polls.size() == 0)\n      break;\n\n    for (auto sock : polls) {\n      Message *msg = sock->receive(true);\n      delete msg;\n    }\n  }\n}\n\nbool SubMaster::updated(const char *name) const {\n  return services_.at(name)->updated;\n}\n\nbool SubMaster::alive(const char *name) const {\n  return services_.at(name)->alive;\n}\n\nbool SubMaster::valid(const char *name) const {\n  return services_.at(name)->valid;\n}\n\nuint64_t SubMaster::rcv_frame(const char *name) const {\n  return services_.at(name)->rcv_frame;\n}\n\nuint64_t SubMaster::rcv_time(const char *name) const {\n  return services_.at(name)->rcv_time;\n}\n\ncereal::Event::Reader &SubMaster::operator[](const char *name) const {\n  return services_.at(name)->event;\n};\n\nSubMaster::~SubMaster() {\n  delete poller_;\n  for (auto &kv : messages_) {\n    SubMessage *m = kv.second;\n    m->msg_reader->~FlatArrayMessageReader();\n    free(m->allocated_msg_reader);\n    delete m->socket;\n    delete m;\n  }\n}\n\nPubMaster::PubMaster(const std::vector<const char *> &service_list) {\n  for (auto name : service_list) {\n    assert(get_service(name) != nullptr);\n    PubSocket *socket = PubSocket::create(message_context.context(), name);\n    assert(socket);\n    sockets_[name] = socket;\n  }\n}\n\nint PubMaster::send(const char *name, MessageBuilder &msg) {\n  auto bytes = msg.toBytes();\n  return send(name, bytes.begin(), bytes.size());\n}\n\nPubMaster::~PubMaster() {\n  for (auto s : sockets_) delete s.second;\n}\n"
  },
  {
    "path": "cereal/services.py",
    "content": "#!/usr/bin/env python3\nimport os\nfrom typing import Optional\n\nTICI = os.path.isfile('/TICI')\nRESERVED_PORT = 8022  # sshd\nSTARTING_PORT = 8001\n\n\ndef new_port(port: int):\n  port += STARTING_PORT\n  return port + 1 if port >= RESERVED_PORT else port\n\n\nclass Service:\n  def __init__(self, port: int, should_log: bool, frequency: float, decimation: Optional[int] = None):\n    self.port = port\n    self.should_log = should_log\n    self.frequency = frequency\n    self.decimation = decimation\n\nDCAM_FREQ = 10. if not TICI else 20.\n\nservices = {\n  # service: (should_log, frequency, qlog decimation (optional))\n  \"sensorEvents\": (True, 100., 100),\n  \"gpsNMEA\": (True, 9.),\n  \"deviceState\": (True, 2., 1),\n  \"can\": (True, 100.),\n  \"controlsState\": (True, 100., 10),\n  \"pandaState\": (True, 2., 1),\n  \"radarState\": (True, 20., 5),\n  \"roadEncodeIdx\": (True, 20., 1),\n  \"liveTracks\": (True, 20.),\n  \"sendcan\": (True, 100.),\n  \"logMessage\": (True, 0.),\n  \"liveCalibration\": (True, 4., 4),\n  \"androidLog\": (True, 0., 1),\n  \"carState\": (True, 100., 10),\n  \"carControl\": (True, 100., 10),\n  \"longitudinalPlan\": (True, 20., 5),\n  \"procLog\": (True, 0.5),\n  \"gpsLocationExternal\": (True, 10., 1),\n  \"ubloxGnss\": (True, 10.),\n  \"clocks\": (True, 1., 1),\n  \"ubloxRaw\": (True, 20.),\n  \"liveLocationKalman\": (True, 20., 2),\n  \"liveParameters\": (True, 20., 2),\n  \"cameraOdometry\": (True, 20., 5),\n  \"lateralPlan\": (True, 20., 5),\n  \"thumbnail\": (True, 0.2, 1),\n  \"carEvents\": (True, 1., 1),\n  \"carParams\": (True, 0.02, 1),\n  \"roadCameraState\": (True, 20., 20),\n  \"driverCameraState\": (True, DCAM_FREQ, DCAM_FREQ),\n  \"driverEncodeIdx\": (True, DCAM_FREQ, 1),\n  \"driverState\": (True, DCAM_FREQ, DCAM_FREQ / 2),\n  \"driverMonitoringState\": (True, DCAM_FREQ, DCAM_FREQ / 2),\n  \"wideRoadEncodeIdx\": (True, 20., 1),\n  \"wideRoadCameraState\": (True, 20., 20),\n  \"modelV2\": (True, 20., 40),\n  \"managerState\": (True, 2., 1),\n  \"uploaderState\": (True, 0., 1),\n  \"liveMapData\": (True, 0.),\n\n  # debug\n  \"testJoystick\": (False, 0.),\n\n  # dp\n  \"thermal\": (True, 2., 1),\n  \"dragonConf\": (False, 1.),\n}\nservice_list = {name: Service(new_port(idx), *vals) for  # type: ignore\n                idx, (name, vals) in enumerate(services.items())}\n\n\ndef build_header():\n  h = \"\"\n  h += \"/* THIS IS AN AUTOGENERATED FILE, PLEASE EDIT services.py */\\n\"\n  h += \"#ifndef __SERVICES_H\\n\"\n  h += \"#define __SERVICES_H\\n\"\n  h += \"struct service { char name[0x100]; int port; bool should_log; int frequency; int decimation; };\\n\"\n  h += \"static struct service services[] = {\\n\"\n  for k, v in service_list.items():\n    should_log = \"true\" if v.should_log else \"false\"\n    decimation = -1 if v.decimation is None else v.decimation\n    h += '  { \"%s\", %d, %s, %d, %d },\\n' % \\\n         (k, v.port, should_log, v.frequency, decimation)\n  h += \"};\\n\"\n  h += \"#endif\\n\"\n  return h\n\n\nif __name__ == \"__main__\":\n  print(build_header())\n"
  },
  {
    "path": "cereal/visionipc/.gitignore",
    "content": "visionipc_pyx.cpp\n*.so\n"
  },
  {
    "path": "cereal/visionipc/__init__.py",
    "content": ""
  },
  {
    "path": "cereal/visionipc/ipc.cc",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <assert.h>\n#include <errno.h>\n\n#include <sys/mman.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n\n#ifdef __APPLE__\n#define getsocket() socket(AF_UNIX, SOCK_STREAM, 0)\n#else\n#define getsocket() socket(AF_UNIX, SOCK_SEQPACKET, 0)\n#endif\n\n#include \"ipc.h\"\n\nint ipc_connect(const char* socket_path) {\n  int err;\n\n  int sock = getsocket();\n\n  if (sock < 0) return -1;\n  struct sockaddr_un addr = {\n    .sun_family = AF_UNIX,\n  };\n  snprintf(addr.sun_path, sizeof(addr.sun_path), \"%s\", socket_path);\n  err = connect(sock, (struct sockaddr*)&addr, sizeof(addr));\n  if (err != 0) {\n    close(sock);\n    return -1;\n  }\n\n  return sock;\n}\n\nint ipc_bind(const char* socket_path) {\n  int err;\n\n  unlink(socket_path);\n\n  int sock = getsocket();\n\n  struct sockaddr_un addr = {\n    .sun_family = AF_UNIX,\n  };\n  snprintf(addr.sun_path, sizeof(addr.sun_path), \"%s\", socket_path);\n  err = bind(sock, (struct sockaddr *)&addr, sizeof(addr));\n  assert(err == 0);\n\n  err = listen(sock, 3);\n  assert(err == 0);\n\n  return sock;\n}\n\n\nint ipc_sendrecv_with_fds(bool send, int fd, void *buf, size_t buf_size, int* fds, int num_fds,\n                          int *out_num_fds) {\n  char control_buf[CMSG_SPACE(sizeof(int) * num_fds)];\n  memset(control_buf, 0, CMSG_SPACE(sizeof(int) * num_fds));\n\n  struct iovec iov = {\n    .iov_base = buf,\n    .iov_len = buf_size,\n  };\n  struct msghdr msg = {\n    .msg_iov = &iov,\n    .msg_iovlen = 1,\n  };\n\n  if (num_fds > 0) {\n    assert(fds);\n\n    msg.msg_control = control_buf;\n    msg.msg_controllen = CMSG_SPACE(sizeof(int) * num_fds);\n  }\n\n  if (send) {\n    if (num_fds) {\n      struct cmsghdr *cmsg = CMSG_FIRSTHDR(&msg);\n      assert(cmsg);\n      cmsg->cmsg_level = SOL_SOCKET;\n      cmsg->cmsg_type = SCM_RIGHTS;\n      cmsg->cmsg_len = CMSG_LEN(sizeof(int) * num_fds);\n      memcpy(CMSG_DATA(cmsg), fds, sizeof(int) * num_fds);\n    }\n    return sendmsg(fd, &msg, 0);\n  } else {\n    int r = recvmsg(fd, &msg, 0);\n    if (r < 0) return r;\n\n    int recv_fds = 0;\n    if (msg.msg_controllen > 0) {\n      struct cmsghdr *cmsg = CMSG_FIRSTHDR(&msg);\n      assert(cmsg);\n      assert(cmsg->cmsg_level == SOL_SOCKET && cmsg->cmsg_type == SCM_RIGHTS);\n      recv_fds = (cmsg->cmsg_len - CMSG_LEN(0));\n      assert(recv_fds > 0 && (recv_fds % sizeof(int)) == 0);\n      recv_fds /= sizeof(int);\n\n      assert(fds && recv_fds <= num_fds);\n      memcpy(fds, CMSG_DATA(cmsg), sizeof(int) * recv_fds);\n    }\n\n    if (msg.msg_flags) {\n      for (int i=0; i<recv_fds; i++) {\n        close(fds[i]);\n      }\n      return -1;\n    }\n\n    if (fds) {\n      assert(out_num_fds);\n      *out_num_fds = recv_fds;\n    }\n    return r;\n  }\n}\n"
  },
  {
    "path": "cereal/visionipc/ipc.h",
    "content": "#pragma once\n#include <cstddef>\n\nint ipc_connect(const char* socket_path);\nint ipc_bind(const char* socket_path);\nint ipc_sendrecv_with_fds(bool send, int fd, void *buf, size_t buf_size, int* fds, int num_fds,\n                          int *out_num_fds);\n"
  },
  {
    "path": "cereal/visionipc/test_runner.cc",
    "content": "#define CATCH_CONFIG_MAIN\n#include \"catch2/catch.hpp\"\n"
  },
  {
    "path": "cereal/visionipc/visionbuf.cc",
    "content": "#include \"visionbuf.h\"\n\n#define ALIGN(x, align) (((x) + (align)-1) & ~((align)-1))\n\n#ifdef QCOM\n// from libadreno_utils.so\nextern \"C\" void compute_aligned_width_and_height(int width,\n                                                 int height,\n                                                 int bpp,\n                                                 int tile_mode,\n                                                 int raster_mode,\n                                                 int padding_threshold,\n                                                 int *aligned_w,\n                                                 int *aligned_h);\n#endif\n\nvoid visionbuf_compute_aligned_width_and_height(int width, int height, int *aligned_w, int *aligned_h) {\n#ifdef QCOM\n  compute_aligned_width_and_height(ALIGN(width, 32), ALIGN(height, 32), 3, 0, 0, 512, aligned_w, aligned_h);\n#else\n  *aligned_w = width; *aligned_h = height;\n#endif\n}\n\nvoid VisionBuf::init_rgb(size_t width, size_t height, size_t stride) {\n  this->rgb = true;\n  this->width = width;\n  this->height = height;\n  this->stride = stride;\n}\n\nvoid VisionBuf::init_yuv(size_t width, size_t height){\n  this->rgb = false;\n  this->width = width;\n  this->height = height;\n\n  this->y = (uint8_t *)this->addr;\n  this->u = this->y + (width * height);\n  this->v = this->u + (width / 2 * height / 2);\n}\n"
  },
  {
    "path": "cereal/visionipc/visionbuf.h",
    "content": "#pragma once\n#include \"visionipc.h\"\n\n#define CL_USE_DEPRECATED_OPENCL_1_2_APIS\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\n\n#define VISIONBUF_SYNC_FROM_DEVICE 0\n#define VISIONBUF_SYNC_TO_DEVICE 1\n\nenum VisionStreamType {\n  VISION_STREAM_RGB_BACK,\n  VISION_STREAM_RGB_FRONT,\n  VISION_STREAM_RGB_WIDE,\n  VISION_STREAM_YUV_BACK,\n  VISION_STREAM_YUV_FRONT,\n  VISION_STREAM_YUV_WIDE,\n  VISION_STREAM_MAX,\n};\n\nclass VisionBuf {\n public:\n  size_t len = 0;\n  size_t mmap_len = 0;\n  void * addr = nullptr;\n  int fd = 0;\n\n  bool rgb = false;\n  size_t width = 0;\n  size_t height = 0;\n  size_t stride = 0;\n\n  // YUV\n  uint8_t * y = nullptr;\n  uint8_t * u = nullptr;\n  uint8_t * v = nullptr;\n\n  // Visionipc\n  uint64_t server_id = 0;\n  size_t idx = 0;\n  VisionStreamType type;\n\n  // OpenCL\n  cl_mem buf_cl = nullptr;\n  cl_command_queue copy_q = nullptr;\n\n  // ion\n  int handle = 0;\n\n  void allocate(size_t len);\n  void import();\n  void init_cl(cl_device_id device_id, cl_context ctx);\n  void init_rgb(size_t width, size_t height, size_t stride);\n  void init_yuv(size_t width, size_t height);\n  int sync(int dir);\n  int free();\n};\n\nvoid visionbuf_compute_aligned_width_and_height(int width, int height, int *aligned_w, int *aligned_h);\n"
  },
  {
    "path": "cereal/visionipc/visionbuf_cl.cc",
    "content": "#include \"visionbuf.h\"\n\n#include <atomic>\n#include <stdio.h>\n#include <fcntl.h>\n#include <assert.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <sys/mman.h>\n#include <sys/types.h>\n\nstd::atomic<int> offset = 0;\n\nstatic void *malloc_with_fd(size_t len, int *fd) {\n  char full_path[0x100];\n\n#ifdef __APPLE__\n  snprintf(full_path, sizeof(full_path)-1, \"/tmp/visionbuf_%d_%d\", getpid(), offset++);\n#else\n  snprintf(full_path, sizeof(full_path)-1, \"/dev/shm/visionbuf_%d_%d\", getpid(), offset++);\n#endif\n\n  *fd = open(full_path, O_RDWR | O_CREAT, 0664);\n  assert(*fd >= 0);\n\n  unlink(full_path);\n\n  ftruncate(*fd, len);\n  void *addr = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, *fd, 0);\n  assert(addr != MAP_FAILED);\n\n  return addr;\n}\n\nvoid VisionBuf::allocate(size_t len) {\n  int fd;\n  void *addr = malloc_with_fd(len, &fd);\n\n  this->len = len;\n  this->mmap_len = len;\n  this->addr = addr;\n  this->fd = fd;\n}\n\nvoid VisionBuf::init_cl(cl_device_id device_id, cl_context ctx){\n  int err;\n\n  this->copy_q = clCreateCommandQueue(ctx, device_id, 0, &err);\n  assert(err == 0);\n\n  this->buf_cl = clCreateBuffer(ctx, CL_MEM_READ_WRITE | CL_MEM_USE_HOST_PTR, this->len, this->addr, &err);\n  assert(err == 0);\n}\n\n\nvoid VisionBuf::import(){\n  assert(this->fd >= 0);\n  this->addr = mmap(NULL, this->mmap_len, PROT_READ | PROT_WRITE, MAP_SHARED, this->fd, 0);\n  assert(this->addr != MAP_FAILED);\n}\n\n\nint VisionBuf::sync(int dir) {\n  int err = 0;\n  if (!this->buf_cl) return 0;\n\n  if (dir == VISIONBUF_SYNC_FROM_DEVICE) {\n    err = clEnqueueReadBuffer(this->copy_q, this->buf_cl, CL_FALSE, 0, this->len, this->addr, 0, NULL, NULL);\n  } else {\n    err = clEnqueueWriteBuffer(this->copy_q, this->buf_cl, CL_FALSE, 0, this->len, this->addr, 0, NULL, NULL);\n  }\n\n  if (err == 0){\n    err = clFinish(this->copy_q);\n  }\n\n  return err;\n}\n\nint VisionBuf::free() {\n  int err = 0;\n  if (this->buf_cl){\n    err = clReleaseMemObject(this->buf_cl);\n    if (err != 0) return err;\n\n    err = clReleaseCommandQueue(this->copy_q);\n    if (err != 0) return err;\n  }\n\n  err = munmap(this->addr, this->len);\n  if (err != 0) return err;\n\n  err = close(this->fd);\n  return err;\n}\n"
  },
  {
    "path": "cereal/visionipc/visionbuf_ion.cc",
    "content": "#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <assert.h>\n#include <sys/mman.h>\n#include <sys/ioctl.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <linux/ion.h>\n#include <CL/cl_ext.h>\n\n#include <msm_ion.h>\n\n#include \"visionbuf.h\"\n\n\n// just hard-code these for convenience\n// size_t device_page_size = 0;\n// clGetDeviceInfo(device_id, CL_DEVICE_PAGE_SIZE_QCOM,\n//                 sizeof(device_page_size), &device_page_size,\n//                 NULL);\n\n// size_t padding_cl = 0;\n// clGetDeviceInfo(device_id, CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM,\n//                 sizeof(padding_cl), &padding_cl,\n//                 NULL);\n#define DEVICE_PAGE_SIZE_CL 4096\n#define PADDING_CL 0\n\nstatic int ion_fd = -1;\nstatic void ion_init() {\n  if (ion_fd == -1) {\n    ion_fd = open(\"/dev/ion\", O_RDWR | O_NONBLOCK);\n  }\n}\n\nvoid VisionBuf::allocate(size_t len) {\n  int err;\n\n  ion_init();\n\n  struct ion_allocation_data ion_alloc = {0};\n  ion_alloc.len = len + PADDING_CL;\n  ion_alloc.align = 4096;\n  ion_alloc.heap_id_mask = 1 << ION_IOMMU_HEAP_ID;\n  ion_alloc.flags = ION_FLAG_CACHED;\n\n  err = ioctl(ion_fd, ION_IOC_ALLOC, &ion_alloc);\n  assert(err == 0);\n\n  struct ion_fd_data ion_fd_data = {0};\n  ion_fd_data.handle = ion_alloc.handle;\n  err = ioctl(ion_fd, ION_IOC_SHARE, &ion_fd_data);\n  assert(err == 0);\n\n  void *addr = mmap(NULL, ion_alloc.len,\n                    PROT_READ | PROT_WRITE,\n                    MAP_SHARED, ion_fd_data.fd, 0);\n  assert(addr != MAP_FAILED);\n\n  memset(addr, 0, ion_alloc.len);\n\n  this->len = len;\n  this->mmap_len = ion_alloc.len;\n  this->addr = addr;\n  this->handle = ion_alloc.handle;\n  this->fd = ion_fd_data.fd;\n}\n\nvoid VisionBuf::import(){\n  int err;\n  assert(this->fd >= 0);\n\n  ion_init();\n\n  // Get handle\n  struct ion_fd_data fd_data = {0};\n  fd_data.fd = this->fd;\n  err = ioctl(ion_fd, ION_IOC_IMPORT, &fd_data);\n  assert(err == 0);\n\n  this->handle = fd_data.handle;\n  this->addr = mmap(NULL, this->mmap_len, PROT_READ | PROT_WRITE, MAP_SHARED, this->fd, 0);\n  assert(this->addr != MAP_FAILED);\n}\n\nvoid VisionBuf::init_cl(cl_device_id device_id, cl_context ctx) {\n  int err;\n\n  assert(((uintptr_t)this->addr % DEVICE_PAGE_SIZE_CL) == 0);\n\n  cl_mem_ion_host_ptr ion_cl = {0};\n  ion_cl.ext_host_ptr.allocation_type = CL_MEM_ION_HOST_PTR_QCOM;\n  ion_cl.ext_host_ptr.host_cache_policy = CL_MEM_HOST_UNCACHED_QCOM;\n  ion_cl.ion_filedesc = this->fd;\n  ion_cl.ion_hostptr = this->addr;\n\n  this->buf_cl = clCreateBuffer(ctx,\n                              CL_MEM_USE_HOST_PTR | CL_MEM_EXT_HOST_PTR_QCOM,\n                              this->len, &ion_cl, &err);\n  assert(err == 0);\n}\n\n\nint VisionBuf::sync(int dir) {\n  struct ion_flush_data flush_data = {0};\n  flush_data.handle = this->handle;\n  flush_data.vaddr = this->addr;\n  flush_data.offset = 0;\n  flush_data.length = this->len;\n\n  // ION_IOC_INV_CACHES ~= DMA_FROM_DEVICE\n  // ION_IOC_CLEAN_CACHES ~= DMA_TO_DEVICE\n  // ION_IOC_CLEAN_INV_CACHES ~= DMA_BIDIRECTIONAL\n\n  struct ion_custom_data custom_data = {0};\n\n   assert(dir == VISIONBUF_SYNC_FROM_DEVICE || dir == VISIONBUF_SYNC_TO_DEVICE);\n   custom_data.cmd = (dir == VISIONBUF_SYNC_FROM_DEVICE) ?\n     ION_IOC_INV_CACHES : ION_IOC_CLEAN_CACHES;\n\n  custom_data.arg = (unsigned long)&flush_data;\n  return ioctl(ion_fd, ION_IOC_CUSTOM, &custom_data);\n}\n\nint VisionBuf::free() {\n  int err = 0;\n\n  if (this->buf_cl){\n    err = clReleaseMemObject(this->buf_cl);\n    if (err != 0) return err;\n  }\n\n  err = munmap(this->addr, this->mmap_len);\n  if (err != 0) return err;\n\n  err = close(this->fd);\n  if (err != 0) return err;\n\n  struct ion_handle_data handle_data = {.handle = this->handle};\n  return ioctl(ion_fd, ION_IOC_FREE, &handle_data);\n}\n"
  },
  {
    "path": "cereal/visionipc/visionipc.h",
    "content": "#pragma once\n\n#include <cstdint>\n#include <cstddef>\n\nconstexpr int VISIONIPC_MAX_FDS = 128;\n\nstruct VisionIpcBufExtra {\n  uint32_t frame_id;\n  uint64_t timestamp_sof;\n  uint64_t timestamp_eof;\n};\n\nstruct VisionIpcPacket {\n  uint64_t server_id;\n  size_t idx;\n  struct VisionIpcBufExtra extra;\n};\n"
  },
  {
    "path": "cereal/visionipc/visionipc.pxd",
    "content": "# distutils: language = c++\n#cython: language_level=3\n\nfrom libcpp.string cimport string\nfrom libcpp.vector cimport vector\nfrom libc.stdint cimport uint32_t, uint64_t\nfrom libcpp cimport bool\n\ncdef extern from \"visionbuf.h\":\n  cdef enum VisionStreamType:\n    pass\n\n  cdef cppclass VisionBuf:\n    void * addr\n    size_t len\n    size_t width\n    size_t height\n    size_t stride\n\ncdef extern from \"visionipc.h\":\n  struct VisionIpcBufExtra:\n    uint32_t frame_id\n    uint64_t timestamp_sof\n    uint64_t timestamp_eof\n\ncdef extern from \"visionipc_server.h\":\n  cdef cppclass VisionIpcServer:\n    VisionIpcServer(string, void*, void*)\n    void create_buffers(VisionStreamType, size_t, bool, size_t, size_t)\n    VisionBuf * get_buffer(VisionStreamType)\n    void send(VisionBuf *, VisionIpcBufExtra *, bool)\n    void start_listener()\n\ncdef extern from \"visionipc_client.h\":\n  cdef cppclass VisionIpcClient:\n    VisionIpcClient(string, VisionStreamType, bool, void*, void*)\n    VisionBuf * recv(VisionIpcBufExtra *, int)\n    bool connect(bool)\n"
  },
  {
    "path": "cereal/visionipc/visionipc_client.cc",
    "content": "#include <chrono>\n#include <cassert>\n#include <iostream>\n#include <thread>\n\n#include \"visionipc/ipc.h\"\n#include \"visionipc/visionipc_client.h\"\n#include \"visionipc/visionipc_server.h\"\n#include \"logger/logger.h\"\n\nVisionIpcClient::VisionIpcClient(std::string name, VisionStreamType type, bool conflate, cl_device_id device_id, cl_context ctx) : name(name), type(type), device_id(device_id), ctx(ctx) {\n  msg_ctx = Context::create();\n  sock = SubSocket::create(msg_ctx, get_endpoint_name(name, type), \"127.0.0.1\", conflate, false);\n\n  poller = Poller::create();\n  poller->registerSocket(sock);\n}\n\n// Connect is not thread safe. Do not use the buffers while calling connect\nbool VisionIpcClient::connect(bool blocking){\n  connected = false;\n\n  // Cleanup old buffers on reconnect\n  for (size_t i = 0; i < num_buffers; i++){\n    if (buffers[i].free() != 0) {\n      LOGE(\"Failed to free buffer %zu\", i);\n    }\n  }\n\n  num_buffers = 0;\n\n  // Connect to server socket and ask for all FDs of type\n  std::string path = \"/tmp/visionipc_\" + name;\n\n  int socket_fd = -1;\n  while (socket_fd < 0) {\n    socket_fd = ipc_connect(path.c_str());\n\n    if (socket_fd < 0) {\n      if (blocking){\n        std::cout << \"VisionIpcClient connecting\" << std::endl;\n        std::this_thread::sleep_for(std::chrono::milliseconds(100));\n      } else {\n        return false;\n      }\n    }\n  }\n\n  // Send stream type to server to request FDs\n  int r = ipc_sendrecv_with_fds(true, socket_fd, &type, sizeof(type), nullptr, 0, nullptr);\n  assert(r == sizeof(type));\n\n  // Get FDs\n  int fds[VISIONIPC_MAX_FDS];\n  VisionBuf bufs[VISIONIPC_MAX_FDS];\n  r = ipc_sendrecv_with_fds(false, socket_fd, &bufs, sizeof(bufs), fds, VISIONIPC_MAX_FDS, &num_buffers);\n\n  assert(num_buffers > 0);\n  assert(r == sizeof(VisionBuf) * num_buffers);\n\n  // Import buffers\n  for (size_t i = 0; i < num_buffers; i++){\n    buffers[i] = bufs[i];\n    buffers[i].fd = fds[i];\n    buffers[i].import();\n    if (buffers[i].rgb) {\n      buffers[i].init_rgb(buffers[i].width, buffers[i].height, buffers[i].stride);\n    } else {\n      buffers[i].init_yuv(buffers[i].width, buffers[i].height);\n    }\n\n    if (device_id) buffers[i].init_cl(device_id, ctx);\n  }\n\n  connected = true;\n  return true;\n}\n\nVisionBuf * VisionIpcClient::recv(VisionIpcBufExtra * extra, const int timeout_ms){\n  auto p = poller->poll(timeout_ms);\n\n  if (!p.size()){\n    return nullptr;\n  }\n\n  Message * r = sock->receive(true);\n  if (r == nullptr){\n    return nullptr;\n  }\n\n  // Get buffer\n  assert(r->getSize() == sizeof(VisionIpcPacket));\n  VisionIpcPacket *packet = (VisionIpcPacket*)r->getData();\n\n  assert(packet->idx < num_buffers);\n  VisionBuf * buf = &buffers[packet->idx];\n\n  if (buf->server_id != packet->server_id){\n    connected = false;\n    delete r;\n    return nullptr;\n  }\n\n  if (extra) {\n    *extra = packet->extra;\n  }\n\n  if (buf->sync(VISIONBUF_SYNC_TO_DEVICE) != 0) {\n    LOGE(\"Failed to sync buffer\");\n  }\n\n  delete r;\n  return buf;\n}\n\n\n\nVisionIpcClient::~VisionIpcClient(){\n  for (size_t i = 0; i < num_buffers; i++){\n    if (buffers[i].free() != 0) {\n      LOGE(\"Failed to free buffer %zu\", i);\n    }\n  }\n\n  delete sock;\n  delete poller;\n  delete msg_ctx;\n}\n"
  },
  {
    "path": "cereal/visionipc/visionipc_client.h",
    "content": "#pragma once\n#include <vector>\n#include <string>\n#include <unistd.h>\n\n#include \"messaging/messaging.h\"\n#include \"visionipc/visionipc.h\"\n#include \"visionipc/visionbuf.h\"\n\nclass VisionIpcClient {\nprivate:\n  std::string name;\n  Context * msg_ctx;\n  SubSocket * sock;\n  Poller * poller;\n\n  VisionStreamType type;\n\n  cl_device_id device_id = nullptr;\n  cl_context ctx = nullptr;\n\n  void init_msgq(bool conflate);\n\npublic:\n  bool connected = false;\n  int num_buffers = 0;\n  VisionBuf buffers[VISIONIPC_MAX_FDS];\n  VisionIpcClient(std::string name, VisionStreamType type, bool conflate, cl_device_id device_id=nullptr, cl_context ctx=nullptr);\n  ~VisionIpcClient();\n  VisionBuf * recv(VisionIpcBufExtra * extra=nullptr, const int timeout_ms=100);\n  bool connect(bool blocking=true);\n};\n"
  },
  {
    "path": "cereal/visionipc/visionipc_pyx.pyx",
    "content": "# distutils: language = c++\n# cython: c_string_encoding=ascii, language_level=3\n\nimport sys\nimport numpy as np\ncimport numpy as cnp\nfrom cython.view cimport array\nfrom libc.string cimport memcpy\nfrom libc.stdint cimport uint32_t, uint64_t\nfrom libcpp cimport bool\nfrom libcpp.string cimport string\n\nfrom .visionipc cimport VisionIpcServer as cppVisionIpcServer\nfrom .visionipc cimport VisionIpcClient as cppVisionIpcClient\nfrom .visionipc cimport VisionBuf as cppVisionBuf\nfrom .visionipc cimport VisionIpcBufExtra\n\ncpdef enum VisionStreamType:\n  VISION_STREAM_RGB_BACK\n  VISION_STREAM_RGB_FRONT\n  VISION_STREAM_RGB_WIDE\n  VISION_STREAM_YUV_BACK\n  VISION_STREAM_YUV_FRONT\n  VISION_STREAM_YUV_WIDE\n\n\ncdef class VisionIpcServer:\n  cdef cppVisionIpcServer * server\n\n  def __init__(self, string name):\n    self.server = new cppVisionIpcServer(name, NULL, NULL)\n\n  def create_buffers(self,  VisionStreamType tp, size_t num_buffers, bool rgb, size_t width, size_t height):\n    self.server.create_buffers(tp, num_buffers, rgb, width, height)\n\n  def send(self, VisionStreamType tp, bytes data, uint32_t frame_id=0, uint64_t timestamp_sof=0, uint64_t timestamp_eof=0):\n    cdef cppVisionBuf * buf = self.server.get_buffer(tp)\n\n    # Populate buffer\n    assert buf.len == len(data)\n    memcpy(buf.addr, <char*>data, len(data))\n\n    cdef VisionIpcBufExtra extra\n    extra.frame_id = frame_id\n    extra.timestamp_sof = timestamp_sof\n    extra.timestamp_eof = timestamp_eof\n\n    self.server.send(buf, &extra, False)\n\n  def start_listener(self):\n    self.server.start_listener()\n\n  def __dealloc__(self):\n    del self.server\n\n\ncdef class VisionIpcClient:\n  cdef cppVisionBuf * buf\n  cdef cppVisionIpcClient * client\n\n  def __cinit__(self, string name, VisionStreamType stream, bool conflate):\n    self.client = new cppVisionIpcClient(name, stream, conflate, NULL, NULL)\n    self.buf = NULL\n\n  def __dealloc__(self):\n    del self.client\n\n  @property\n  def width(self):\n    return None if not self.buf else self.buf.width\n\n  @property\n  def height(self):\n    return None if not self.buf else self.buf.height\n\n  @property\n  def stride(self):\n    return None if not self.buf else self.buf.stride\n\n  def recv(self, int timeout_ms=100):\n    self.buf = self.client.recv(NULL, timeout_ms)\n    if not self.buf:\n      return None\n    cdef cnp.ndarray dat = np.empty(self.buf.len, dtype=np.uint8)\n    cdef char[:] dat_view = dat\n    memcpy(&dat_view[0], self.buf.addr, self.buf.len)\n    return dat\n\n  def connect(self, bool blocking):\n    return self.client.connect(blocking)\n"
  },
  {
    "path": "cereal/visionipc/visionipc_server.cc",
    "content": "#include <iostream>\n#include <chrono>\n#include <cassert>\n#include <random>\n\n#include <poll.h>\n#include <sys/socket.h>\n#include <unistd.h>\n\n#include \"messaging/messaging.h\"\n#include \"visionipc/ipc.h\"\n#include \"visionipc/visionipc_server.h\"\n#include \"logger/logger.h\"\n\nstd::string get_endpoint_name(std::string name, VisionStreamType type){\n  if (messaging_use_zmq()){\n    assert(name == \"camerad\");\n    return std::to_string(9000 + static_cast<int>(type));\n  } else {\n    return \"visionipc_\" + name + \"_\" + std::to_string(type);\n  }\n}\n\nVisionIpcServer::VisionIpcServer(std::string name, cl_device_id device_id, cl_context ctx) : name(name), device_id(device_id), ctx(ctx) {\n  msg_ctx = Context::create();\n\n  std::random_device rd(\"/dev/urandom\");\n  std::uniform_int_distribution<uint64_t> distribution(0,std::numeric_limits<uint64_t>::max());\n  server_id = distribution(rd);\n}\n\nvoid VisionIpcServer::create_buffers(VisionStreamType type, size_t num_buffers, bool rgb, size_t width, size_t height){\n  // TODO: assert that this type is not created yet\n  assert(num_buffers < VISIONIPC_MAX_FDS);\n  int aligned_w = 0, aligned_h = 0;\n\n  size_t size = 0;\n  size_t stride = 0; // Only used for RGB\n\n  if (rgb) {\n    visionbuf_compute_aligned_width_and_height(width, height, &aligned_w, &aligned_h);\n    size = (size_t)aligned_w * (size_t)aligned_h * 3;\n    stride = aligned_w * 3;\n  } else {\n    size = width * height * 3 / 2;\n  }\n\n\n  // Create map + alloc requested buffers\n  for (size_t i = 0; i < num_buffers; i++){\n    VisionBuf* buf = new VisionBuf();\n    buf->allocate(size);\n    buf->idx = i;\n    buf->type = type;\n\n    if (device_id) buf->init_cl(device_id, ctx);\n\n    rgb ? buf->init_rgb(width, height, stride) : buf->init_yuv(width, height);\n\n    buffers[type].push_back(buf);\n  }\n\n  cur_idx[type] = 0;\n\n  // Create msgq publisher for each of the `name` + type combos\n  // TODO: compute port number directly if using zmq\n  sockets[type] = PubSocket::create(msg_ctx, get_endpoint_name(name, type), false);\n}\n\n\nvoid VisionIpcServer::start_listener(){\n  listener_thread = std::thread(&VisionIpcServer::listener, this);\n}\n\n\nvoid VisionIpcServer::listener(){\n  std::cout << \"Starting listener for: \" << name << std::endl;\n\n  std::string path = \"/tmp/visionipc_\" + name;\n  int sock = ipc_bind(path.c_str());\n  assert(sock >= 0);\n\n  while (!should_exit){\n    // Wait for incoming connection\n    struct pollfd polls[1] = {{0}};\n    polls[0].fd = sock;\n    polls[0].events = POLLIN;\n\n    int ret = poll(polls, 1, 100);\n    if (ret < 0) {\n      if (errno == EINTR || errno == EAGAIN) continue;\n      std::cout << \"poll failed, stopping listener\" << std::endl;\n      break;\n    }\n\n    if (should_exit) break;\n    if (!polls[0].revents) {\n      continue;\n    }\n\n    // Handle incoming request\n    int fd = accept(sock, NULL, NULL);\n    assert(fd >= 0);\n\n    VisionStreamType type = VisionStreamType::VISION_STREAM_MAX;\n    int r = ipc_sendrecv_with_fds(false, fd, &type, sizeof(type), nullptr, 0, nullptr);\n    assert(r == sizeof(type));\n    if (buffers.count(type) <= 0) {\n      std::cout << \"got request for invalid buffer type: \" << type << std::endl;\n      close(fd);\n      continue;\n    }\n\n    int fds[VISIONIPC_MAX_FDS];\n    int num_fds = buffers[type].size();\n    VisionBuf bufs[VISIONIPC_MAX_FDS];\n\n    for (int i = 0; i < num_fds; i++){\n      fds[i] = buffers[type][i]->fd;\n      bufs[i] = *buffers[type][i];\n\n      // Remove some private openCL/ion metadata\n      bufs[i].buf_cl = 0;\n      bufs[i].copy_q = 0;\n      bufs[i].handle = 0;\n\n      bufs[i].server_id = server_id;\n    }\n\n    r = ipc_sendrecv_with_fds(true, fd, &bufs, sizeof(VisionBuf) * num_fds, fds, num_fds, nullptr);\n\n    close(fd);\n  }\n\n  std::cout << \"Stopping listener for: \" << name << std::endl;\n  close(sock);\n}\n\n\n\nVisionBuf * VisionIpcServer::get_buffer(VisionStreamType type){\n  // Do we want to keep track if the buffer has been sent out yet and warn user?\n  assert(buffers.count(type));\n  auto b = buffers[type];\n  return b[cur_idx[type]++ % b.size()];\n}\n\nvoid VisionIpcServer::send(VisionBuf * buf, VisionIpcBufExtra * extra, bool sync){\n  if (sync) {\n    if (buf->sync(VISIONBUF_SYNC_FROM_DEVICE) != 0) {\n      LOGE(\"Failed to sync buffer\");\n    }\n  }\n  assert(buffers.count(buf->type));\n  assert(buf->idx < buffers[buf->type].size());\n\n  // Send over correct msgq socket\n  VisionIpcPacket packet = {0};\n  packet.server_id = server_id;\n  packet.idx = buf->idx;\n  packet.extra = *extra;\n\n  sockets[buf->type]->send((char*)&packet, sizeof(packet));\n}\n\nVisionIpcServer::~VisionIpcServer(){\n  should_exit = true;\n  listener_thread.join();\n\n  // VisionBuf cleanup\n  for( auto const& [type, buf] : buffers ) {\n    for (VisionBuf* b : buf){\n      if (b->free() != 0) {\n        LOGE(\"Failed to free buffer\");\n      }\n      delete b;\n    }\n  }\n\n  // Messaging cleanup\n  for( auto const& [type, sock] : sockets ) {\n    delete sock;\n  }\n  delete msg_ctx;\n}\n"
  },
  {
    "path": "cereal/visionipc/visionipc_server.h",
    "content": "#pragma once\n#include <vector>\n#include <string>\n#include <thread>\n#include <atomic>\n#include <map>\n\n#include \"messaging/messaging.h\"\n#include \"visionipc/visionipc.h\"\n#include \"visionipc/visionbuf.h\"\n\nstd::string get_endpoint_name(std::string name, VisionStreamType type);\n\nclass VisionIpcServer {\n private:\n  cl_device_id device_id = nullptr;\n  cl_context ctx = nullptr;\n  uint64_t server_id;\n\n  std::atomic<bool> should_exit = false;\n  std::string name;\n  std::thread listener_thread;\n\n  std::map<VisionStreamType, std::atomic<size_t> > cur_idx;\n  std::map<VisionStreamType, std::vector<VisionBuf*> > buffers;\n  std::map<VisionStreamType, std::map<VisionBuf*, size_t> > idxs;\n\n  Context * msg_ctx;\n  std::map<VisionStreamType, PubSocket*> sockets;\n\n  void listener(void);\n\n public:\n  VisionIpcServer(std::string name, cl_device_id device_id=nullptr, cl_context ctx=nullptr);\n  ~VisionIpcServer();\n\n  VisionBuf * get_buffer(VisionStreamType type);\n\n  void create_buffers(VisionStreamType type, size_t num_buffers, bool rgb, size_t width, size_t height);\n  void send(VisionBuf * buf, VisionIpcBufExtra * extra, bool sync=true);\n  void start_listener();\n};\n"
  },
  {
    "path": "cereal/visionipc/visionipc_tests.cc",
    "content": "#include <thread>\n#include <chrono>\n\n#include \"catch2/catch.hpp\"\n#include \"visionipc_server.h\"\n#include \"visionipc_client.h\"\n\nstatic void zmq_sleep(int milliseconds=1000){\n  if (messaging_use_zmq()){\n    std::this_thread::sleep_for(std::chrono::milliseconds(milliseconds));\n  }\n}\n\nTEST_CASE(\"Connecting\"){\n  VisionIpcServer server(\"camerad\");\n  server.create_buffers(VISION_STREAM_YUV_BACK, 1, false, 100, 100);\n  server.start_listener();\n\n  VisionIpcClient client = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_BACK, false);\n  REQUIRE(client.connect());\n\n  REQUIRE(client.connected);\n}\n\nTEST_CASE(\"Check buffers\"){\n  size_t width = 100, height = 200, num_buffers = 5;\n  VisionIpcServer server(\"camerad\");\n  server.create_buffers(VISION_STREAM_YUV_BACK, num_buffers, false, width, height);\n  server.start_listener();\n\n  VisionIpcClient client = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_BACK, false);\n  REQUIRE(client.connect());\n\n  REQUIRE(client.buffers[0].width == width);\n  REQUIRE(client.buffers[0].height == height);\n  REQUIRE(client.buffers[0].len);\n  REQUIRE(client.num_buffers == num_buffers);\n}\n\nTEST_CASE(\"Check yuv/rgb\"){\n  VisionIpcServer server(\"camerad\");\n  server.create_buffers(VISION_STREAM_YUV_BACK, 1, false, 100, 100);\n  server.create_buffers(VISION_STREAM_RGB_BACK, 1, true, 100, 100);\n  server.start_listener();\n\n  VisionIpcClient client_yuv = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_BACK, false);\n  VisionIpcClient client_rgb = VisionIpcClient(\"camerad\", VISION_STREAM_RGB_BACK, false);\n  client_yuv.connect();\n  client_rgb.connect();\n\n  REQUIRE(client_rgb.buffers[0].rgb == true);\n  REQUIRE(client_yuv.buffers[0].rgb == false);\n}\n\nTEST_CASE(\"Send single buffer\"){\n  VisionIpcServer server(\"camerad\");\n  server.create_buffers(VISION_STREAM_YUV_BACK, 1, true, 100, 100);\n  server.start_listener();\n\n  VisionIpcClient client = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_BACK, false);\n  REQUIRE(client.connect());\n  zmq_sleep();\n\n  VisionBuf * buf = server.get_buffer(VISION_STREAM_YUV_BACK);\n  REQUIRE(buf != nullptr);\n\n  *((uint64_t*)buf->addr) = 1234;\n\n  VisionIpcBufExtra extra = {0};\n  extra.frame_id = 1337;\n\n  server.send(buf, &extra);\n\n  VisionIpcBufExtra extra_recv = {0};\n  VisionBuf * recv_buf = client.recv(&extra_recv);\n  REQUIRE(recv_buf != nullptr);\n  REQUIRE(*(uint64_t*)recv_buf->addr == 1234);\n  REQUIRE(extra_recv.frame_id == extra.frame_id);\n}\n\n\nTEST_CASE(\"Test no conflate\"){\n  VisionIpcServer server(\"camerad\");\n  server.create_buffers(VISION_STREAM_YUV_BACK, 1, true, 100, 100);\n  server.start_listener();\n\n  VisionIpcClient client = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_BACK, false);\n  REQUIRE(client.connect());\n  zmq_sleep();\n\n  VisionBuf * buf = server.get_buffer(VISION_STREAM_YUV_BACK);\n  REQUIRE(buf != nullptr);\n\n  VisionIpcBufExtra extra = {0};\n  extra.frame_id = 1;\n  server.send(buf, &extra);\n  extra.frame_id = 2;\n  server.send(buf, &extra);\n\n  VisionIpcBufExtra extra_recv = {0};\n  VisionBuf * recv_buf = client.recv(&extra_recv);\n  REQUIRE(recv_buf != nullptr);\n  REQUIRE(extra_recv.frame_id == 1);\n\n  recv_buf = client.recv(&extra_recv);\n  REQUIRE(recv_buf != nullptr);\n  REQUIRE(extra_recv.frame_id == 2);\n}\n\nTEST_CASE(\"Test conflate\"){\n  VisionIpcServer server(\"camerad\");\n  server.create_buffers(VISION_STREAM_YUV_BACK, 1, true, 100, 100);\n  server.start_listener();\n\n  VisionIpcClient client = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_BACK, true);\n  REQUIRE(client.connect());\n  zmq_sleep();\n\n  VisionBuf * buf = server.get_buffer(VISION_STREAM_YUV_BACK);\n  REQUIRE(buf != nullptr);\n\n  VisionIpcBufExtra extra = {0};\n  extra.frame_id = 1;\n  server.send(buf, &extra);\n  extra.frame_id = 2;\n  server.send(buf, &extra);\n\n  VisionIpcBufExtra extra_recv = {0};\n  VisionBuf * recv_buf = client.recv(&extra_recv);\n  REQUIRE(recv_buf != nullptr);\n  REQUIRE(extra_recv.frame_id == 2);\n\n  recv_buf = client.recv(&extra_recv);\n  REQUIRE(recv_buf == nullptr);\n}\n"
  },
  {
    "path": "common/.gitignore",
    "content": "*.cpp\n"
  },
  {
    "path": "common/SConscript",
    "content": "Import('envCython', 'common')\n\nenvCython.Program('clock.so', 'clock.pyx')\nenvCython.Program('params_pyx.so', 'params_pyx.pyx', LIBS=envCython['LIBS'] + [common, 'zmq'])\n"
  },
  {
    "path": "common/__init__.py",
    "content": ""
  },
  {
    "path": "common/api/__init__.py",
    "content": "import jwt\nimport os\nimport requests\nfrom datetime import datetime, timedelta\nfrom common.basedir import PERSIST\nfrom selfdrive.version import version\nfrom common.params import Params\n\nAPI_HOST = os.getenv('API_HOST', 'https://api.commadotai.com') if not Params().get_bool(\"dp_api_custom\") else Params().get(\"dp_api_custom_url\", encoding='utf-8')\n\nclass Api():\n  def __init__(self, dongle_id):\n    if \"commadotai\" in API_HOST and (Params().get_bool(\"dp_jetson\") or Params().get_bool(\"dp_atl\")):\n      raise RuntimeError(\"API access is disabled because you are not using custom server and you have jetson enabled.\")\n    self.dongle_id = dongle_id\n    with open(PERSIST+'/comma/id_rsa') as f:\n      self.private_key = f.read()\n\n  def get(self, *args, **kwargs):\n    return self.request('GET', *args, **kwargs)\n\n  def post(self, *args, **kwargs):\n    return self.request('POST', *args, **kwargs)\n\n  def request(self, method, endpoint, timeout=None, access_token=None, **params):\n    return api_get(endpoint, method=method, timeout=timeout, access_token=access_token, **params)\n\n  def get_token(self):\n    now = datetime.utcnow()\n    payload = {\n      'identity': self.dongle_id,\n      'nbf': now,\n      'iat': now,\n      'exp': now + timedelta(hours=1)\n    }\n    token = jwt.encode(payload, self.private_key, algorithm='RS256')\n    if isinstance(token, bytes):\n      token = token.decode('utf8')\n    return token\n    \n\ndef api_get(endpoint, method='GET', timeout=None, access_token=None, **params):\n  headers = {}\n  if access_token is not None:\n    headers['Authorization'] = \"JWT \"+access_token\n\n  headers['User-Agent'] = \"openpilot-\" + version\n\n  return requests.request(method, API_HOST + \"/\" + endpoint, timeout=timeout, headers=headers, params=params)\n"
  },
  {
    "path": "common/basedir.py",
    "content": "import os\nfrom pathlib import Path\n\nfrom selfdrive.hardware import PC\n\nBASEDIR = os.path.abspath(os.path.join(os.path.dirname(os.path.realpath(__file__)), \"../\"))\n\nif PC:\n  PERSIST = os.path.join(str(Path.home()), \".comma\", \"persist\")\nelse:\n  PERSIST = \"/persist\"\n"
  },
  {
    "path": "common/clock.pyx",
    "content": "# distutils: language = c++\n# cython: language_level = 3\nfrom posix.time cimport clock_gettime, timespec, CLOCK_MONOTONIC_RAW, clockid_t\n\nIF UNAME_SYSNAME == \"Darwin\":\n  # Darwin doesn't have a CLOCK_BOOTTIME\n  CLOCK_BOOTTIME = CLOCK_MONOTONIC_RAW\nELSE:\n  from posix.time cimport CLOCK_BOOTTIME\n\ncdef double readclock(clockid_t clock_id):\n  cdef timespec ts\n  cdef double current\n\n  clock_gettime(clock_id, &ts)\n  current = ts.tv_sec + (ts.tv_nsec / 1000000000.)\n  return current\n\ndef monotonic_time():\n  return readclock(CLOCK_MONOTONIC_RAW)\n\ndef sec_since_boot():\n  return readclock(CLOCK_BOOTTIME)\n\n"
  },
  {
    "path": "common/cython_hacks.py",
    "content": "import os\nimport sysconfig\nfrom Cython.Distutils import build_ext\n\ndef get_ext_filename_without_platform_suffix(filename):\n  name, ext = os.path.splitext(filename)\n  ext_suffix = sysconfig.get_config_var('EXT_SUFFIX')\n\n  if ext_suffix == ext:\n    return filename\n\n  ext_suffix = ext_suffix.replace(ext, '')\n  idx = name.find(ext_suffix)\n\n  if idx == -1:\n    return filename\n  else:\n    return name[:idx] + ext\n\nclass BuildExtWithoutPlatformSuffix(build_ext):\n  def get_ext_filename(self, ext_name):\n    filename = super().get_ext_filename(ext_name)\n    return get_ext_filename_without_platform_suffix(filename)\n"
  },
  {
    "path": "common/dict_helpers.py",
    "content": "# remove all keys that end in DEPRECATED\ndef strip_deprecated_keys(d):\n  for k in list(d.keys()):\n    if isinstance(k, str):\n      if k.endswith('DEPRECATED'):\n        d.pop(k)\n      elif isinstance(d[k], dict):\n        strip_deprecated_keys(d[k])\n  return d\n"
  },
  {
    "path": "common/dp_common.py",
    "content": "#!/usr/bin/env python3.7\nimport subprocess\nfrom cereal import car\nfrom common.params import Params\nfrom common.realtime import sec_since_boot\nimport os\nparams = Params()\nPARAM_PATH = params.get_params_path() + '/d/'\nLAST_MODIFIED = PARAM_PATH + \"dp_last_modified\"\n\ndef is_online():\n  try:\n    return not subprocess.call([\"ping\", \"-W\", \"4\", \"-c\", \"1\", \"117.28.245.92\"])\n  except ProcessLookupError:\n    return False\n\ndef common_controller_ctrl(enabled, dragonconf, blinker_on, steer_req, v_ego):\n  if enabled:\n    if dragonconf.dpLateralMode == 0 and blinker_on:\n      steer_req = 0 if isinstance(steer_req, int) else False\n  return steer_req\n\ndef common_interface_atl(ret, atl):\n  # dp\n  enable_acc = ret.cruiseState.enabled\n  if atl and ret.cruiseState.available:\n    enable_acc = True\n    if ret.gearShifter in [car.CarState.GearShifter.reverse, car.CarState.GearShifter.park]:\n      enable_acc = False\n    if ret.seatbeltUnlatched or ret.doorOpen:\n      enable_acc = False\n  return enable_acc\n\ndef common_interface_get_params_lqr(ret):\n  if params.get_bool('dp_lqr'):\n    ret.lateralTuning.init('lqr')\n    ret.lateralTuning.lqr.scale = 1500.0\n    ret.lateralTuning.lqr.ki = 0.05\n\n    ret.lateralTuning.lqr.a = [0., 1., -0.22619643, 1.21822268]\n    ret.lateralTuning.lqr.b = [-1.92006585e-04, 3.95603032e-05]\n    ret.lateralTuning.lqr.c = [1., 0.]\n    ret.lateralTuning.lqr.k = [-110.73572306, 451.22718255]\n    ret.lateralTuning.lqr.l = [0.3233671, 0.3185757]\n    ret.lateralTuning.lqr.dcGain = 0.002237852961363602\n  return ret\n\n\ndef get_last_modified(delay, old_check, old_modified):\n  new_check = sec_since_boot()\n  if os.path.isfile(LAST_MODIFIED) and old_check is None or new_check - old_check >= delay:\n    return new_check, os.stat(LAST_MODIFIED).st_mtime\n  else:\n    return old_check, old_modified\n\ndef param_get_if_updated(param, type, old_val, old_modified):\n  try:\n    modified = os.stat(PARAM_PATH + param).st_mtime\n  except OSError:\n    return old_val, old_modified\n  if old_modified != modified:\n    new_val = param_get(param, type, old_val)\n    new_modified = modified\n  else:\n    new_val = old_val\n    new_modified = old_modified\n  return new_val, new_modified\n\ndef param_get(param_name, type, default):\n  try:\n    val = params.get(param_name, encoding='utf8').rstrip('\\x00')\n    if type == 'bool':\n      val = val == '1'\n    elif type == 'int':\n      val = int(val)\n    elif type == 'float':\n      val = float(val)\n  except (TypeError, ValueError):\n    val = default\n  return val\n"
  },
  {
    "path": "common/dp_conf.py",
    "content": "#!/usr/bin/env python3.7\nimport os\nimport sys\nimport json\nimport time\nfrom math import floor\n\n'''\n* type: Bool, Int8, UInt8, UInt16, Float32\n* conf_type: param, struct\n* dependencies needs to use struct and loaded prior so we don't have to read the param multiple times.\n* update_once: True, False (the param will only load up once, need both param and struct defined)\n'''\nconfs = [\n  # thermald data\n  {'name': 'dp_thermal_started', 'default': False, 'type': 'Bool', 'conf_type': ['struct']},\n  {'name': 'dp_thermal_overheat', 'default': False, 'type': 'Bool', 'conf_type': ['struct']},\n\n  # custom api server\n  {'name': 'dp_api_custom', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_api_custom_url', 'default': 'https://api.retropilot.org', 'type': 'Text', 'depends': [{'name': 'dp_api_custom', 'vals': [True]}], 'conf_type': ['param']},\n\n  {'name': 'dp_atl', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct'], 'update_once': True},\n  {'name': 'dp_atl_op_long', 'default': False, 'type': 'Bool', 'depends': [{'name': 'dp_atl', 'vals': [True]}], 'conf_type': ['param', 'struct'], 'update_once': True},\n  # dashcam related\n  {'name': 'dp_dashcamd', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  # auto shutdown\n  {'name': 'dp_auto_shutdown', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_auto_shutdown_in', 'default': 90, 'type': 'UInt16', 'min': 0, 'max': 600, 'depends': [{'name': 'dp_auto_shutdown', 'vals': [True]}], 'conf_type': ['param']},\n  # service\n  {'name': 'dp_updated', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_logger', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_athenad', 'default': False, 'type': 'Bool', 'depends': [{'name': 'dp_atl', 'vals': [False]}], 'conf_type': ['param', 'struct'], 'update_once': True},\n  {'name': 'dp_uploader', 'default': False, 'type': 'Bool', 'depends': [{'name': 'dp_atl', 'vals': [False]}], 'conf_type': ['param', 'struct'], 'update_once': True},\n  # {'name': 'dp_gpxd', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_hotspot_on_boot', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  # lat ctrl\n  {'name': 'dp_lateral_mode', 'default': 1, 'type': 'UInt8', 'min': 0, 'max': 2, 'conf_type': ['param', 'struct']},\n  {'name': 'dp_signal_off_delay', 'default': 3., 'type': 'Float32', 'min': 0., 'max': 10., 'depends': [{'name': 'dp_lateral_mode', 'vals': [0]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_lc_min_mph', 'default': 45, 'type': 'UInt8', 'min': 0, 'max': 255, 'depends': [{'name': 'dp_lateral_mode', 'vals': [1,2]}], 'conf_type': ['param', 'struct']},\n  # {'name': 'dp_lc_auto_cont', 'default': False, 'type': 'Bool', 'depends': [{'name': 'dp_lateral_mode', 'vals': [2]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_lc_auto_min_mph', 'default': 60, 'type': 'UInt8', 'min': 0, 'max': 255, 'depends': [{'name': 'dp_lateral_mode', 'vals': [2]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_lc_auto_delay', 'default': 3., 'type': 'Float32', 'min': 0., 'max': 10., 'depends': [{'name': 'dp_lateral_mode', 'vals': [2]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_lane_less_mode_ctrl', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_lane_less_mode', 'default': 2, 'type': 'UInt8', 'min': 0, 'max': 2, 'depends': [{'name': 'dp_lane_less_mode_ctrl', 'vals': [True]}], 'conf_type': ['param', 'struct']},\n  # long ctrl\n  {'name': 'dp_allow_gas', 'default': False, 'type': 'Bool', 'depends': [{'name': 'dp_atl', 'vals': [False]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_following_profile_ctrl', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_following_profile', 'default': 0, 'type': 'UInt8', 'min': 0, 'max': 3, 'depends': [{'name': 'dp_following_profile_ctrl', 'vals': [True]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_accel_profile_ctrl', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_accel_profile', 'default': 0, 'type': 'UInt8', 'min': 0, 'max': 2, 'depends': [{'name': 'dp_accel_profile_ctrl', 'vals': [True]}], 'conf_type': ['param', 'struct']},\n  # safety\n  {'name': 'dp_gear_check', 'default': True, 'type': 'Bool', 'depends': [{'name': 'dp_atl', 'vals': [False]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_speed_check', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_temp_monitor', 'default': True, 'type': 'Bool', 'conf_type': ['param']},\n  # UIs\n  {'name': 'dp_ui_display_mode', 'default': 0, 'type': 'UInt8', 'min': 0, 'max': 2, 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_speed', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_event', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_max_speed', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_face', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_lane', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_lead', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_side', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_top', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_blinker', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_brightness', 'default': 0, 'type': 'UInt8', 'min': 0, 'max': 100, 'conf_type': ['param', 'struct']},\n  {'name': 'dp_ui_volume', 'default': -5, 'type': 'Int8', 'min': -5, 'max': 100, 'conf_type': ['param', 'struct']},\n  # toyota\n  {'name': 'dp_lexus_rx_rpm_fix', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_toyota_ldw', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_toyota_sng', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_toyota_zss', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_toyota_fp_btn_link', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_toyota_ap_btn_link', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_toyota_disable_relay', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_toyota_cruise_override', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_toyota_cruise_override_vego', 'default': False, 'type': 'Bool', 'depends': [{'name': 'dp_toyota_cruise_override', 'vals': [True]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_toyota_cruise_override_at', 'default': 44, 'type': 'Float32', 'depends': [{'name': 'dp_toyota_cruise_override', 'vals': [True]}], 'min': 0, 'max': 50., 'conf_type': ['param', 'struct']},\n  {'name': 'dp_toyota_cruise_override_speed', 'default': 32, 'type': 'Float32', 'depends': [{'name': 'dp_toyota_cruise_override', 'vals': [True]}], 'min': 0, 'max': 50., 'conf_type': ['param', 'struct']},\n  # hyundai\n  {'name': 'dp_hkg_smart_mdps', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  # honda\n  {'name': 'dp_honda_eps_mod', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_honda_kmh_display', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  # volkswagen\n  {'name': 'dp_vw_panda', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_vw_timebomb_assist', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  #misc\n  {'name': 'dp_ip_addr', 'default': '', 'type': 'Text', 'conf_type': ['struct']},\n  {'name': 'dp_fan_mode', 'default': 0, 'type': 'UInt8', 'min': 0, 'max': 2, 'conf_type': ['param']},\n  {'name': 'dp_last_modified', 'default': str(floor(time.time())), 'type': 'Text', 'conf_type': ['param']},\n  {'name': 'dp_camera_offset', 'default': 6, 'type': 'Int8', 'min': -100, 'max': 100, 'conf_type': ['param', 'struct']},\n  {'name': 'dp_path_offset', 'default': 0, 'type': 'Int8', 'min': -100, 'max': 100, 'conf_type': ['param', 'struct']},\n\n  {'name': 'dp_locale', 'default': 'en-US', 'type': 'Text', 'conf_type': ['param', 'struct'], 'update_once': True},\n  {'name': 'dp_reg', 'default': True, 'type': 'Bool', 'conf_type': ['param']},\n  # sr learner related\n  {'name': 'dp_sr_learner', 'default': True, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_sr_custom', 'default': 9.99, 'min': 9.99, 'max': 30., 'type': 'Float32', 'depends': [{'name': 'dp_sr_learner', 'vals': [False]}], 'conf_type': ['param', 'struct']},\n  {'name': 'dp_sr_stock', 'default': 9.99, 'min': 9.99, 'max': 100., 'type': 'Float32', 'conf_type': ['param']},\n\n  {'name': 'dp_lqr', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_reset_live_param_on_start', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n\n  {'name': 'dp_appd', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_jetson', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_car_assigned', 'default': '', 'type': 'Text', 'conf_type': ['param']},\n  {'name': 'dp_car_list', 'default': '', 'type': 'Text', 'conf_type': ['param']},\n  {'name': 'dp_no_batt', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_last_candidate', 'default': '', 'type': 'Text', 'conf_type': ['param']},\n  {'name': 'dp_prebuilt', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_gpxd', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_mapd', 'default': False, 'type': 'Bool', 'conf_type': ['param', 'struct']},\n  {'name': 'dp_otisserv', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_mapbox_token_pk', 'default': '', 'type': 'Text', 'conf_type': ['param']},\n  {'name': 'dp_mapbox_token_sk', 'default': '', 'type': 'Text', 'conf_type': ['param']},\n  {'name': 'dp_mapbox_full_screen', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_mapbox_traffic', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_mapbox_gmap_enable', 'default': False, 'type': 'Bool', 'conf_type': ['param']},\n  {'name': 'dp_mapbox_gmap_key', 'default': '', 'type': 'Text', 'conf_type': ['param']},\n]\n\ndef get_definition(name):\n  for conf in confs:\n    if conf['name'] == name:\n      return conf\n  return None\n\ndef to_param_val(name, val):\n  conf = get_definition(name)\n  if conf is not None:\n    type = conf['type'].lower()\n    try:\n      if 'bool' in type:\n        val = '1' if val else '0'\n      elif 'int' in type:\n        val = int(val)\n      elif 'float' in type:\n        val = float(val)\n      return str(val)\n    except (ValueError, TypeError):\n      return ''\n  return ''\n\ndef to_struct_val(name, val):\n  conf = get_definition(name)\n  if conf is not None:\n    try:\n      type = conf['type'].lower()\n      if 'bool' in type:\n        val = True if val == '1' else False\n      elif 'int' in type:\n        val = int(val)\n      elif 'float' in type:\n        val = float(val)\n      return val\n    except (ValueError, TypeError):\n      return None\n  return None\n\n'''\nfunction to convert param name into struct name.\n'''\ndef get_struct_name(snake_str):\n  components = snake_str.split('_')\n  # We capitalize the first letter of each component except the first one\n  # with the 'title' method and join them together.\n  return components[0] + ''.join(x.title() for x in components[1:])\n\n'''\nfunction to generate struct for log.capnp\n'''\ndef gen_log_struct():\n  count = 0\n  str = \"# dp\\n\"\n  str += \"struct DragonConf {\\n\"\n  for conf in confs:\n    name = get_struct_name(conf['name'])\n    if 'struct' in conf['conf_type']:\n      str += f\"  {name} @{count} :{conf['type']};\\n\"\n      count += 1\n  str += \"}\"\n  print(str)\n\n'''\nfunction to generate support car list\n'''\ndef get_support_car_list():\n  attrs = ['FINGERPRINTS', 'FW_VERSIONS']\n  cars = dict({\"cars\": []})\n  for car_folder in [x[0] for x in os.walk('/data/openpilot/selfdrive/car')]:\n    try:\n      car_name = car_folder.split('/')[-1]\n      if car_name != \"mock\":\n        names = []\n        for attr in attrs:\n          values = __import__('selfdrive.car.%s.values' % car_name, fromlist=[attr])\n          if hasattr(values, attr):\n            attr_values = getattr(values, attr)\n          else:\n            continue\n          if isinstance(attr_values, dict):\n            for f, v in attr_values.items():\n              if f not in names:\n                names.append(f)\n          names.sort()\n        brand_models = {\"brand\": car_name.upper(), \"models\": names }\n        cars[\"cars\"].append(brand_models)\n    except (ImportError, IOError, ValueError):\n      pass\n  return json.dumps(cars)\n\n'''\nfunction to init param value.\nshould add this into manager.py\n'''\ndef init_params_vals(params):\n  for conf in confs:\n    if 'param' in conf['conf_type']:\n      if conf['name'] == 'dp_car_list':\n        params.put(conf['name'], get_support_car_list())\n      elif params.get(conf['name']) is None:\n        params.put(conf['name'], to_param_val(conf['name'], conf['default']))\n\ndef gen_params_cc_keys():\n  for conf in confs:\n    if 'param' in conf['conf_type']:\n      print(\"    {\\\"%s\\\", PERSISTENT},\" % conf['name'])\n\n\nif __name__ == \"__main__\":\n  if (len(sys.argv) > 1) and sys.argv[1] == 'cc':\n    gen_params_cc_keys()\n  else:\n    gen_log_struct()\n"
  },
  {
    "path": "common/dp_time.py",
    "content": "#!/usr/bin/env python3.7\n\n# delay of reading last modified\nLAST_MODIFIED_THERMALD = 10.\nLAST_MODIFIED_SYSTEMD = 1.\nLAST_MODIFIED_LANE_PLANNER = 3.\nLAST_MODIFIED_UPLOADER = 10."
  },
  {
    "path": "common/ffi_wrapper.py",
    "content": "import os\nimport sys\nimport fcntl\nimport hashlib\nimport platform\nfrom cffi import FFI\n\ndef suffix():\n  if platform.system() == \"Darwin\":\n    return \".dylib\"\n  else:\n    return \".so\"\n\ndef ffi_wrap(name, c_code, c_header, tmpdir=\"/tmp/ccache\", cflags=\"\", libraries=None):\n  if libraries is None:\n    libraries = []\n\n  cache = name + \"_\" + hashlib.sha1(c_code.encode('utf-8')).hexdigest()\n  try:\n    os.mkdir(tmpdir)\n  except OSError:\n    pass\n\n  fd = os.open(tmpdir, 0)\n  fcntl.flock(fd, fcntl.LOCK_EX)\n  try:\n    sys.path.append(tmpdir)\n    try:\n      mod = __import__(cache)\n    except Exception:\n      print(\"cache miss {0}\".format(cache))\n      compile_code(cache, c_code, c_header, tmpdir, cflags, libraries)\n      mod = __import__(cache)\n  finally:\n    os.close(fd)\n\n  return mod.ffi, mod.lib\n\n\ndef compile_code(name, c_code, c_header, directory, cflags=\"\", libraries=None):\n  if libraries is None:\n    libraries = []\n\n  ffibuilder = FFI()\n  ffibuilder.set_source(name, c_code, source_extension='.cpp', libraries=libraries)\n  ffibuilder.cdef(c_header)\n  os.environ['OPT'] = \"-fwrapv -O2 -DNDEBUG -std=c++1z\"\n  os.environ['CFLAGS'] = cflags\n  ffibuilder.compile(verbose=True, debug=False, tmpdir=directory)\n\n\ndef wrap_compiled(name, directory):\n  sys.path.append(directory)\n  mod = __import__(name)\n  return mod.ffi, mod.lib\n"
  },
  {
    "path": "common/file_helpers.py",
    "content": "import os\nimport shutil\nimport tempfile\nfrom atomicwrites import AtomicWriter\n\n\ndef mkdirs_exists_ok(path):\n  if path.startswith('http://') or path.startswith('https://'):\n    raise ValueError('URL path')\n  try:\n    os.makedirs(path)\n  except OSError:\n    if not os.path.isdir(path):\n      raise\n\n\ndef rm_not_exists_ok(path):\n  try:\n    os.remove(path)\n  except OSError:\n    if os.path.exists(path):\n      raise\n\n\ndef rm_tree_or_link(path):\n  if os.path.islink(path):\n    os.unlink(path)\n  elif os.path.isdir(path):\n    shutil.rmtree(path)\n\n\ndef get_tmpdir_on_same_filesystem(path):\n  normpath = os.path.normpath(path)\n  parts = normpath.split(\"/\")\n  if len(parts) > 1 and parts[1] == \"scratch\":\n    return \"/scratch/tmp\"\n  elif len(parts) > 2 and parts[2] == \"runner\":\n    return \"/{}/runner/tmp\".format(parts[1])\n  return \"/tmp\"\n\n\nclass NamedTemporaryDir():\n  def __init__(self, temp_dir=None):\n    self._path = tempfile.mkdtemp(dir=temp_dir)\n\n  @property\n  def name(self):\n    return self._path\n\n  def close(self):\n    shutil.rmtree(self._path)\n\n  def __enter__(self):\n    return self\n\n  def __exit__(self, exc_type, exc_value, traceback):\n    self.close()\n\n\nclass CallbackReader:\n  \"\"\"Wraps a file, but overrides the read method to also\n  call a callback function with the number of bytes read so far.\"\"\"\n  def __init__(self, f, callback, *args):\n    self.f = f\n    self.callback = callback\n    self.cb_args = args\n    self.total_read = 0\n\n  def __getattr__(self, attr):\n    return getattr(self.f, attr)\n\n  def read(self, *args, **kwargs):\n    chunk = self.f.read(*args, **kwargs)\n    self.total_read += len(chunk)\n    self.callback(*self.cb_args, self.total_read)\n    return chunk\n\n\ndef _get_fileobject_func(writer, temp_dir):\n  def _get_fileobject():\n    return writer.get_fileobject(dir=temp_dir)\n  return _get_fileobject\n\n\ndef atomic_write_on_fs_tmp(path, **kwargs):\n  \"\"\"Creates an atomic writer using a temporary file in a temporary directory\n     on the same filesystem as path.\n  \"\"\"\n  # TODO(mgraczyk): This use of AtomicWriter relies on implementation details to set the temp\n  #                 directory.\n  writer = AtomicWriter(path, **kwargs)\n  return writer._open(_get_fileobject_func(writer, get_tmpdir_on_same_filesystem(path)))\n\n\ndef atomic_write_in_dir(path, **kwargs):\n  \"\"\"Creates an atomic writer using a temporary file in the same directory\n     as the destination file.\n  \"\"\"\n  writer = AtomicWriter(path, **kwargs)\n  return writer._open(_get_fileobject_func(writer, os.path.dirname(path)))\n"
  },
  {
    "path": "common/filter_simple.py",
    "content": "class FirstOrderFilter:\n  # first order filter\n  def __init__(self, x0, rc, dt, initialized=True):\n    self.x = x0\n    self.dt = dt\n    self.update_alpha(rc)\n    self.initialized = initialized\n\n  def update_alpha(self, rc):\n    self.alpha = self.dt / (rc + self.dt)\n\n  def update(self, x):\n    if self.initialized:\n      self.x = (1. - self.alpha) * self.x + self.alpha * x\n    else:\n      self.initialized = True\n      self.x = x\n    return self.x\n"
  },
  {
    "path": "common/gpio.py",
    "content": "def gpio_init(pin, output):\n  try:\n    with open(f\"/sys/class/gpio/gpio{pin}/direction\", 'wb') as f:\n      f.write(b\"out\" if output else b\"in\")\n  except Exception as e:\n    print(f\"Failed to set gpio {pin} direction: {e}\")\n\n\ndef gpio_set(pin, high):\n  try:\n    with open(f\"/sys/class/gpio/gpio{pin}/value\", 'wb') as f:\n      f.write(b\"1\" if high else b\"0\")\n  except Exception as e:\n    print(f\"Failed to set gpio {pin} value: {e}\")\n"
  },
  {
    "path": "common/i18n.py",
    "content": "import gettext\nfrom common.params import Params\nimport os\n\nlocale_dir = \"/data/openpilot/selfdrive/assets/locales\"\nsupported_language = [\"en-US\", \"zh-TW\", \"zh-CN\", \"ja-JP\", \"ko-KR\"]\n\ndef events():\n  if os.path.isfile(\"/EON\"):\n    locale = Params().get(\"dp_locale\", encoding='utf8')\n    locale = locale.strip() if locale is not None else \"en-US\"\n  else:\n    locale = \"en-US\"\n  i18n = gettext.translation(\"events\", localedir=locale_dir, fallback=True, languages=[locale])\n  i18n.install()\n  return i18n.gettext"
  },
  {
    "path": "common/kalman/.gitignore",
    "content": "simple_kalman_impl.c\n"
  },
  {
    "path": "common/kalman/SConscript",
    "content": "Import('envCython')\n\nenvCython.Program('simple_kalman_impl.so', 'simple_kalman_impl.pyx')\n"
  },
  {
    "path": "common/kalman/__init__.py",
    "content": ""
  },
  {
    "path": "common/kalman/simple_kalman.py",
    "content": "# pylint: skip-file\nfrom common.kalman.simple_kalman_impl import KF1D as KF1D\nassert KF1D\n"
  },
  {
    "path": "common/kalman/simple_kalman_impl.pxd",
    "content": "# cython: language_level = 3\n\ncdef class KF1D:\n  cdef public:\n    double x0_0\n    double x1_0\n    double K0_0\n    double K1_0\n    double A0_0\n    double A0_1\n    double A1_0\n    double A1_1\n    double C0_0\n    double C0_1\n    double A_K_0\n    double A_K_1\n    double A_K_2\n    double A_K_3\n"
  },
  {
    "path": "common/kalman/simple_kalman_impl.pyx",
    "content": "# distutils: language = c++\n# cython: language_level=3\n\ncdef class KF1D:\n  def __init__(self, x0, A, C, K):\n    self.x0_0 = x0[0][0]\n    self.x1_0 = x0[1][0]\n    self.A0_0 = A[0][0]\n    self.A0_1 = A[0][1]\n    self.A1_0 = A[1][0]\n    self.A1_1 = A[1][1]\n    self.C0_0 = C[0]\n    self.C0_1 = C[1]\n    self.K0_0 = K[0][0]\n    self.K1_0 = K[1][0]\n\n    self.A_K_0 = self.A0_0 - self.K0_0 * self.C0_0\n    self.A_K_1 = self.A0_1 - self.K0_0 * self.C0_1\n    self.A_K_2 = self.A1_0 - self.K1_0 * self.C0_0\n    self.A_K_3 = self.A1_1 - self.K1_0 * self.C0_1\n\n  def update(self, meas):\n    cdef double x0_0 = self.A_K_0 * self.x0_0 + self.A_K_1 * self.x1_0 + self.K0_0 * meas\n    cdef double x1_0 = self.A_K_2 * self.x0_0 + self.A_K_3 * self.x1_0 + self.K1_0 * meas\n    self.x0_0 = x0_0\n    self.x1_0 = x1_0\n\n    return [self.x0_0, self.x1_0]\n\n  @property\n  def x(self):\n    return [[self.x0_0], [self.x1_0]]\n\n  @x.setter\n  def x(self, x):\n    self.x0_0 = x[0][0]\n    self.x1_0 = x[1][0]\n"
  },
  {
    "path": "common/kalman/simple_kalman_old.py",
    "content": "import numpy as np\n\n\nclass KF1D:\n  # this EKF assumes constant covariance matrix, so calculations are much simpler\n  # the Kalman gain also needs to be precomputed using the control module\n\n  def __init__(self, x0, A, C, K):\n    self.x = x0\n    self.A = A\n    self.C = np.atleast_2d(C)\n    self.K = K\n\n    self.A_K = self.A - np.dot(self.K, self.C)\n\n    # K matrix needs to  be pre-computed as follow:\n    # import control\n    # (x, l, K) = control.dare(np.transpose(self.A), np.transpose(self.C), Q, R)\n    # self.K = np.transpose(K)\n\n  def update(self, meas):\n    self.x = np.dot(self.A_K, self.x) + np.dot(self.K, meas)\n    return self.x\n"
  },
  {
    "path": "common/kalman/tests/__init__.py",
    "content": ""
  },
  {
    "path": "common/kalman/tests/test_simple_kalman.py",
    "content": "import unittest\nimport random\nimport timeit\nimport numpy as np\n\nfrom common.kalman.simple_kalman import KF1D\nfrom common.kalman.simple_kalman_old import KF1D as KF1D_old\n\n\nclass TestSimpleKalman(unittest.TestCase):\n  def setUp(self):\n    dt = 0.01\n    x0_0 = 0.0\n    x1_0 = 0.0\n    A0_0 = 1.0\n    A0_1 = dt\n    A1_0 = 0.0\n    A1_1 = 1.0\n    C0_0 = 1.0\n    C0_1 = 0.0\n    K0_0 = 0.12287673\n    K1_0 = 0.29666309\n\n    self.kf_old = KF1D_old(x0=np.array([[x0_0], [x1_0]]),\n                           A=np.array([[A0_0, A0_1], [A1_0, A1_1]]),\n                           C=np.array([C0_0, C0_1]),\n                           K=np.array([[K0_0], [K1_0]]))\n\n    self.kf = KF1D(x0=[[x0_0], [x1_0]],\n                   A=[[A0_0, A0_1], [A1_0, A1_1]],\n                   C=[C0_0, C0_1],\n                   K=[[K0_0], [K1_0]])\n\n  def test_getter_setter(self):\n    self.kf.x = [[1.0], [1.0]]\n    self.assertEqual(self.kf.x, [[1.0], [1.0]])\n\n  def update_returns_state(self):\n      x = self.kf.update(100)\n      self.assertEqual(x, self.kf.x)\n\n  def test_old_equal_new(self):\n    for _ in range(1000):\n      v_wheel = random.uniform(0, 200)\n\n      x_old = self.kf_old.update(v_wheel)\n      x = self.kf.update(v_wheel)\n\n      # Compare the output x, verify that the error is less than 1e-4\n      np.testing.assert_almost_equal(x_old[0], x[0])\n      np.testing.assert_almost_equal(x_old[1], x[1])\n\n  def test_new_is_faster(self):\n    setup = \"\"\"\nimport numpy as np\n\nfrom common.kalman.simple_kalman import KF1D\nfrom common.kalman.simple_kalman_old import KF1D as KF1D_old\n\ndt = 0.01\nx0_0 = 0.0\nx1_0 = 0.0\nA0_0 = 1.0\nA0_1 = dt\nA1_0 = 0.0\nA1_1 = 1.0\nC0_0 = 1.0\nC0_1 = 0.0\nK0_0 = 0.12287673\nK1_0 = 0.29666309\n\nkf_old = KF1D_old(x0=np.array([[x0_0], [x1_0]]),\n                  A=np.array([[A0_0, A0_1], [A1_0, A1_1]]),\n                  C=np.array([C0_0, C0_1]),\n                  K=np.array([[K0_0], [K1_0]]))\n\nkf = KF1D(x0=[[x0_0], [x1_0]],\n          A=[[A0_0, A0_1], [A1_0, A1_1]],\n          C=[C0_0, C0_1],\n          K=[[K0_0], [K1_0]])\n    \"\"\"\n    kf_speed = timeit.timeit(\"kf.update(1234)\", setup=setup, number=10000)\n    kf_old_speed = timeit.timeit(\"kf_old.update(1234)\", setup=setup, number=10000)\n    self.assertTrue(kf_speed < kf_old_speed / 4)\n\nif __name__ == \"__main__\":\n  unittest.main()\n"
  },
  {
    "path": "common/logging_extra.py",
    "content": "import io\nimport os\nimport sys\nimport copy\nimport json\nimport uuid\nimport socket\nimport logging\nimport traceback\nfrom threading import local\nfrom collections import OrderedDict\nfrom contextlib import contextmanager\n\ndef json_handler(obj):\n  # if isinstance(obj, (datetime.date, datetime.time)):\n  #   return obj.isoformat()\n  return repr(obj)\n\ndef json_robust_dumps(obj):\n  return json.dumps(obj, default=json_handler)\n\nclass NiceOrderedDict(OrderedDict):\n  def __str__(self):\n    return json_robust_dumps(self)\n\nclass SwagFormatter(logging.Formatter):\n  def __init__(self, swaglogger):\n    logging.Formatter.__init__(self, None, '%a %b %d %H:%M:%S %Z %Y')\n\n    self.swaglogger = swaglogger\n    self.host = socket.gethostname()\n\n  def format_dict(self, record):\n    record_dict = NiceOrderedDict()\n\n    if isinstance(record.msg, dict):\n      record_dict['msg'] = record.msg\n    else:\n      try:\n        record_dict['msg'] = record.getMessage()\n      except (ValueError, TypeError):\n        record_dict['msg'] = [record.msg]+record.args\n\n    record_dict['ctx'] = self.swaglogger.get_ctx()\n\n    if record.exc_info:\n      record_dict['exc_info'] = self.formatException(record.exc_info)\n\n    record_dict['level'] = record.levelname\n    record_dict['levelnum'] = record.levelno\n    record_dict['name'] = record.name\n    record_dict['filename'] = record.filename\n    record_dict['lineno'] = record.lineno\n    record_dict['pathname'] = record.pathname\n    record_dict['module'] = record.module\n    record_dict['funcName'] = record.funcName\n    record_dict['host'] = self.host\n    record_dict['process'] = record.process\n    record_dict['thread'] = record.thread\n    record_dict['threadName'] = record.threadName\n    record_dict['created'] = record.created\n\n    return record_dict\n\n  def format(self, record):\n    if self.swaglogger is None:\n      raise Exception(\"must set swaglogger before calling format()\")\n    return json_robust_dumps(self.format_dict(record))\n\nclass SwagLogFileFormatter(SwagFormatter):\n  def fix_kv(self, k, v):\n    # append type to names to preserve legacy naming in logs\n    # avoids overlapping key namespaces with different types\n    # e.g. log.info() creates 'msg' -> 'msg$s'\n    #      log.event() creates 'msg.health.logMonoTime' -> 'msg.health.logMonoTime$i'\n    #      because overlapping namespace 'msg' caused problems\n    if isinstance(v, (str, bytes)):\n      k += \"$s\"\n    elif isinstance(v, float):\n      k += \"$f\"\n    elif isinstance(v, bool):\n      k += \"$b\"\n    elif isinstance(v, int):\n      k += \"$i\"\n    elif isinstance(v, dict):\n      nv = {}\n      for ik, iv in v.items():\n        ik, iv = self.fix_kv(ik, iv)\n        nv[ik] = iv\n      v = nv\n    elif isinstance(v, list):\n      k += \"$a\"\n    return k, v\n\n  def format(self, record):\n    if isinstance(record, str):\n      v = json.loads(record)\n    else:\n      v = self.format_dict(record)\n\n    mk, mv = self.fix_kv('msg', v['msg'])\n    del v['msg']\n    v[mk] = mv\n    v['id'] = uuid.uuid4().hex\n\n    return json_robust_dumps(v)\n\nclass SwagErrorFilter(logging.Filter):\n  def filter(self, record):\n    return record.levelno < logging.ERROR\n\ndef _tmpfunc():\n  return 0\n\ndef _srcfile():\n  return os.path.normcase(_tmpfunc.__code__.co_filename)\n\nclass SwagLogger(logging.Logger):\n  def __init__(self):\n    logging.Logger.__init__(self, \"swaglog\")\n\n    self.global_ctx = {}\n\n    self.log_local = local()\n    self.log_local.ctx = {}\n\n  def local_ctx(self):\n    try:\n      return self.log_local.ctx\n    except AttributeError:\n      self.log_local.ctx = {}\n      return self.log_local.ctx\n\n  def get_ctx(self):\n    return dict(self.local_ctx(), **self.global_ctx)\n\n  @contextmanager\n  def ctx(self, **kwargs):\n    old_ctx = self.local_ctx()\n    self.log_local.ctx = copy.copy(old_ctx) or {}\n    self.log_local.ctx.update(kwargs)\n    try:\n      yield\n    finally:\n      self.log_local.ctx = old_ctx\n\n  def bind(self, **kwargs):\n    self.local_ctx().update(kwargs)\n\n  def bind_global(self, **kwargs):\n    self.global_ctx.update(kwargs)\n\n  def event(self, event_name, *args, **kwargs):\n    evt = NiceOrderedDict()\n    evt['event'] = event_name\n    if args:\n      evt['args'] = args\n    evt.update(kwargs)\n    if 'error' in kwargs:\n      self.error(evt)\n    elif 'debug' in kwargs:\n      self.debug(evt)\n    else:\n      self.info(evt)\n\n  def findCaller(self, stack_info=False, stacklevel=1):\n    \"\"\"\n    Find the stack frame of the caller so that we can note the source\n    file name, line number and function name.\n    \"\"\"\n    f = sys._getframe(3)\n    #On some versions of IronPython, currentframe() returns None if\n    #IronPython isn't run with -X:Frames.\n    if f is not None:\n        f = f.f_back\n    orig_f = f\n    while f and stacklevel > 1:\n        f = f.f_back\n        stacklevel -= 1\n    if not f:\n        f = orig_f\n    rv = \"(unknown file)\", 0, \"(unknown function)\", None\n    while hasattr(f, \"f_code\"):\n        co = f.f_code\n        filename = os.path.normcase(co.co_filename)\n\n        # TODO: is this pylint exception correct?\n        if filename == _srcfile:  # pylint: disable=comparison-with-callable\n            f = f.f_back\n            continue\n        sinfo = None\n        if stack_info:\n            sio = io.StringIO()\n            sio.write('Stack (most recent call last):\\n')\n            traceback.print_stack(f, file=sio)\n            sinfo = sio.getvalue()\n            if sinfo[-1] == '\\n':\n                sinfo = sinfo[:-1]\n            sio.close()\n        rv = (co.co_filename, f.f_lineno, co.co_name, sinfo)\n        break\n    return rv\n\nif __name__ == \"__main__\":\n  log = SwagLogger()\n\n  stdout_handler = logging.StreamHandler(sys.stdout)\n  stdout_handler.setLevel(logging.INFO)\n  stdout_handler.addFilter(SwagErrorFilter())\n  log.addHandler(stdout_handler)\n\n  stderr_handler = logging.StreamHandler(sys.stderr)\n  stderr_handler.setLevel(logging.ERROR)\n  log.addHandler(stderr_handler)\n\n  log.info(\"asdasd %s\", \"a\")\n  log.info({'wut': 1})\n  log.warning(\"warning\")\n  log.error(\"error\")\n  log.critical(\"critical\")\n  log.event(\"test\", x=\"y\")\n\n  with log.ctx():\n    stdout_handler.setFormatter(SwagFormatter(log))\n    stderr_handler.setFormatter(SwagFormatter(log))\n    log.bind(user=\"some user\")\n    log.info(\"in req\")\n    print(\"\")\n    log.warning(\"warning\")\n    print(\"\")\n    log.error(\"error\")\n    print(\"\")\n    log.critical(\"critical\")\n    print(\"\")\n    log.event(\"do_req\", a=1, b=\"c\")\n"
  },
  {
    "path": "common/numpy_fast.py",
    "content": "def int_rnd(x):\n  return int(round(x))\n\ndef clip(x, lo, hi):\n  return max(lo, min(hi, x))\n\ndef interp(x, xp, fp):\n  N = len(xp)\n\n  def get_interp(xv):\n    hi = 0\n    while hi < N and xv > xp[hi]:\n      hi += 1\n    low = hi - 1\n    return fp[-1] if hi == N and xv > xp[low] else (\n      fp[0] if hi == 0 else\n      (xv - xp[low]) * (fp[hi] - fp[low]) / (xp[hi] - xp[low]) + fp[low])\n\n  return [get_interp(v) for v in x] if hasattr(x, '__iter__') else get_interp(x)\n\ndef mean(x):\n  return sum(x) / len(x)\n"
  },
  {
    "path": "common/params.py",
    "content": "from common.params_pyx import Params, ParamKeyType, UnknownKeyName, put_nonblocking # pylint: disable=no-name-in-module, import-error\nassert Params\nassert ParamKeyType\nassert UnknownKeyName\nassert put_nonblocking\n\nif __name__ == \"__main__\":\n  import sys\n  from common.params_pyx import keys # pylint: disable=no-name-in-module, import-error\n\n  params = Params()\n  if len(sys.argv) == 3:\n    name = sys.argv[1]\n    val = sys.argv[2]\n    assert name.encode(\"utf-8\") in keys.keys(), f\"unknown param: {name}\"\n    print(f\"SET: {name} = {val}\")\n    params.put(name, val)\n  elif len(sys.argv) == 2:\n    name = sys.argv[1]\n    assert name.encode(\"utf-8\") in keys.keys(), f\"unknown param: {name}\"\n    print(f\"GET: {name} = {params.get(name)}\")\n  else:\n    for k in keys.keys():\n      print(f\"GET: {k} = {params.get(k)}\")\n"
  },
  {
    "path": "common/params_pxd.pxd",
    "content": "from libcpp.string cimport string\nfrom libcpp cimport bool\n\ncdef extern from \"selfdrive/common/params.cc\":\n  pass\n\ncdef extern from \"selfdrive/common/util.cc\":\n  pass\n\ncdef extern from \"selfdrive/common/params.h\":\n  cpdef enum ParamKeyType:\n    PERSISTENT\n    CLEAR_ON_MANAGER_START\n    CLEAR_ON_PANDA_DISCONNECT\n    CLEAR_ON_IGNITION_ON\n    CLEAR_ON_IGNITION_OFF\n    ALL\n\n  cdef cppclass Params:\n    Params() nogil\n    Params(string) nogil\n    string get(string, bool) nogil\n    bool getBool(string) nogil\n    int remove(string) nogil\n    int put(string, string) nogil\n    int putBool(string, bool) nogil\n    bool checkKey(string) nogil\n    void clearAll(ParamKeyType)\n\n    string get_params_path()"
  },
  {
    "path": "common/params_pyx.pyx",
    "content": "# distutils: language = c++\n# cython: language_level = 3\nfrom libcpp cimport bool\nfrom libcpp.string cimport string\nfrom common.params_pxd cimport Params as c_Params, ParamKeyType as c_ParamKeyType\n\nimport os\nimport threading\nfrom common.basedir import BASEDIR\n\n\ncdef class ParamKeyType:\n  PERSISTENT = c_ParamKeyType.PERSISTENT\n  CLEAR_ON_MANAGER_START = c_ParamKeyType.CLEAR_ON_MANAGER_START\n  CLEAR_ON_PANDA_DISCONNECT = c_ParamKeyType.CLEAR_ON_PANDA_DISCONNECT\n  CLEAR_ON_IGNITION_ON = c_ParamKeyType.CLEAR_ON_IGNITION_ON\n  CLEAR_ON_IGNITION_OFF = c_ParamKeyType.CLEAR_ON_IGNITION_OFF\n  ALL = c_ParamKeyType.ALL\n\ndef ensure_bytes(v):\n  if isinstance(v, str):\n    return v.encode()\n  else:\n    return v\n\n\nclass UnknownKeyName(Exception):\n  pass\n\ncdef class Params:\n  cdef c_Params* p\n\n  def __cinit__(self, d=None):\n    cdef string path\n    if d is None:\n      with nogil:\n        self.p = new c_Params()\n    else:\n      path = <string>d.encode()\n      with nogil:\n        self.p = new c_Params(path)\n\n  def __dealloc__(self):\n    del self.p\n\n  def clear_all(self, tx_type=None):\n    if tx_type is None:\n      tx_type = ParamKeyType.ALL\n\n    self.p.clearAll(tx_type)\n\n  def check_key(self, key):\n    key = ensure_bytes(key)\n\n    if not self.p.checkKey(key):\n      raise UnknownKeyName(key)\n\n    return key\n\n  def get(self, key, bool block=False, encoding=None):\n    cdef string k = self.check_key(key)\n\n    cdef string val\n    with nogil:\n      val = self.p.get(k, block)\n\n    if val == b\"\":\n      if block:\n        # If we got no value while running in blocked mode\n        # it means we got an interrupt while waiting\n        raise KeyboardInterrupt\n      else:\n        return None\n\n    if encoding is not None:\n      return val.decode(encoding)\n    else:\n      return val\n\n  def get_bool(self, key):\n    cdef string k = self.check_key(key)\n    cdef bool r\n    with nogil:\n      r = self.p.getBool(k)\n    return r\n\n  def put(self, key, dat):\n    \"\"\"\n    Warning: This function blocks until the param is written to disk!\n    In very rare cases this can take over a second, and your code will hang.\n    Use the put_nonblocking helper function in time sensitive code, but\n    in general try to avoid writing params as much as possible.\n    \"\"\"\n    cdef string k = self.check_key(key)\n    cdef string dat_bytes = ensure_bytes(dat)\n    with nogil:\n      self.p.put(k, dat_bytes)\n\n  def put_bool(self, key, bool val):\n    cdef string k = self.check_key(key)\n    with nogil:\n      self.p.putBool(k, val)\n\n  def delete(self, key):\n    cdef string k = self.check_key(key)\n    with nogil:\n      self.p.remove(k)\n\n  def get_params_path(self):\n    return self.p.get_params_path().decode(\"utf-8\")\n\ndef put_nonblocking(key, val, d=None):\n  def f(key, val):\n    params = Params(d)\n    cdef string k = ensure_bytes(key)\n    params.put(k, val)\n\n  t = threading.Thread(target=f, args=(key, val))\n  t.start()\n  return t\n"
  },
  {
    "path": "common/profiler.py",
    "content": "import time\n\nclass Profiler():\n  def __init__(self, enabled=False):\n    self.enabled = enabled\n    self.cp = {}\n    self.cp_ignored = []\n    self.iter = 0\n    self.start_time = time.time()\n    self.last_time = self.start_time\n    self.tot = 0.\n\n  def reset(self, enabled=False):\n    self.enabled = enabled\n    self.cp = {}\n    self.cp_ignored = []\n    self.iter = 0\n    self.start_time = time.time()\n    self.last_time = self.start_time\n\n  def checkpoint(self, name, ignore=False):\n    # ignore flag needed when benchmarking threads with ratekeeper\n    if not self.enabled:\n      return\n    tt = time.time()\n    if name not in self.cp:\n      self.cp[name] = 0.\n      if ignore:\n        self.cp_ignored.append(name)\n    self.cp[name] += tt - self.last_time\n    if not ignore:\n      self.tot += tt - self.last_time\n    self.last_time = tt\n\n  def display(self):\n    if not self.enabled:\n      return\n    self.iter += 1\n    print(\"******* Profiling %d *******\" % self.iter)\n    for n, ms in sorted(self.cp.items(), key=lambda x: -x[1]):\n      if n in self.cp_ignored:\n        print(\"%30s: %9.2f  avg: %7.2f  percent: %3.0f   IGNORED\" % (n, ms*1000.0, ms*1000.0/self.iter, ms/self.tot*100))\n      else:\n        print(\"%30s: %9.2f  avg: %7.2f  percent: %3.0f\" % (n, ms*1000.0, ms*1000.0/self.iter, ms/self.tot*100))\n    print(\"Iter clock: %2.6f   TOTAL: %2.2f\" % (self.tot/self.iter, self.tot))\n"
  },
  {
    "path": "common/realtime.py",
    "content": "\"\"\"Utilities for reading real time clocks and keeping soft real time constraints.\"\"\"\nimport gc\nimport os\nimport time\nimport multiprocessing\nfrom typing import Optional\n\nfrom common.clock import sec_since_boot  # pylint: disable=no-name-in-module, import-error\nfrom selfdrive.hardware import PC, TICI\n\n\n# time step for each process\nDT_CTRL = 0.01  # controlsd\nDT_MDL = 0.05  # model\nDT_TRML = 0.5  # thermald and manager\n\n# driver monitoring\nif TICI:\n  DT_DMON = 0.05\nelse:\n  DT_DMON = 0.1\n\n\nclass Priority:\n  # CORE 2\n  # - modeld = 55\n  # - camerad = 54\n  CTRL_LOW = 51 # plannerd & radard\n\n  # CORE 3\n  # - boardd = 55\n  CTRL_HIGH = 53\n\n\ndef set_realtime_priority(level: int) -> None:\n  if not PC:\n    os.sched_setscheduler(0, os.SCHED_FIFO, os.sched_param(level))  # type: ignore[attr-defined]\n\n\ndef set_core_affinity(core: int) -> None:\n  if not PC:\n    os.sched_setaffinity(0, [core,])\n\n\ndef config_realtime_process(core: int, priority: int) -> None:\n  gc.disable()\n  set_realtime_priority(priority)\n  set_core_affinity(core)\n\n\nclass Ratekeeper:\n  def __init__(self, rate: int, print_delay_threshold: Optional[float] = 0.0) -> None:\n    \"\"\"Rate in Hz for ratekeeping. print_delay_threshold must be nonnegative.\"\"\"\n    self._interval = 1. / rate\n    self._next_frame_time = sec_since_boot() + self._interval\n    self._print_delay_threshold = print_delay_threshold\n    self._frame = 0\n    self._remaining = 0.0\n    self._process_name = multiprocessing.current_process().name\n\n  @property\n  def frame(self) -> int:\n    return self._frame\n\n  @property\n  def remaining(self) -> float:\n    return self._remaining\n\n  # Maintain loop rate by calling this at the end of each loop\n  def keep_time(self) -> bool:\n    lagged = self.monitor_time()\n    if self._remaining > 0:\n      time.sleep(self._remaining)\n    return lagged\n\n  # this only monitor the cumulative lag, but does not enforce a rate\n  def monitor_time(self) -> bool:\n    lagged = False\n    remaining = self._next_frame_time - sec_since_boot()\n    self._next_frame_time += self._interval\n    if self._print_delay_threshold is not None and remaining < -self._print_delay_threshold:\n      print(\"%s lagging by %.2f ms\" % (self._process_name, -remaining * 1000))\n      lagged = True\n    self._frame += 1\n    self._remaining = remaining\n    return lagged\n"
  },
  {
    "path": "common/spinner.py",
    "content": "import os\nimport subprocess\nfrom common.basedir import BASEDIR\n\n\nclass Spinner():\n  def __init__(self):\n    try:\n      self.spinner_proc = subprocess.Popen([\"./spinner\"],\n                                           stdin=subprocess.PIPE,\n                                           cwd=os.path.join(BASEDIR, \"selfdrive\", \"ui\"),\n                                           close_fds=True)\n    except OSError:\n      self.spinner_proc = None\n\n  def __enter__(self):\n    return self\n\n  def update(self, spinner_text: str):\n    if self.spinner_proc is not None:\n      self.spinner_proc.stdin.write(spinner_text.encode('utf8') + b\"\\n\")\n      try:\n        self.spinner_proc.stdin.flush()\n      except BrokenPipeError:\n        pass\n\n  def update_progress(self, cur: int, total: int):\n    self.update(str(round(100 * cur / total)))\n\n  def close(self):\n    if self.spinner_proc is not None:\n      try:\n        self.spinner_proc.stdin.close()\n      except BrokenPipeError:\n        pass\n      self.spinner_proc.terminate()\n      self.spinner_proc = None\n\n  def __del__(self):\n    self.close()\n\n  def __exit__(self, exc_type, exc_value, traceback):\n    self.close()\n\n\nif __name__ == \"__main__\":\n  import time\n  with Spinner() as s:\n    s.update(\"Spinner text\")\n    time.sleep(5.0)\n  print(\"gone\")\n  time.sleep(5.0)\n"
  },
  {
    "path": "common/stat_live.py",
    "content": "import numpy as np\n\nclass RunningStat():\n  # tracks realtime mean and standard deviation without storing any data\n  def __init__(self, priors=None, max_trackable=-1):\n    self.max_trackable = max_trackable\n    if priors is not None:\n      # initialize from history\n      self.M = priors[0]\n      self.S = priors[1]\n      self.n = priors[2]\n      self.M_last = self.M\n      self.S_last = self.S\n\n    else:\n      self.reset()\n\n  def reset(self):\n    self.M = 0.\n    self.S = 0.\n    self.M_last = 0.\n    self.S_last = 0.\n    self.n = 0\n\n  def push_data(self, new_data):\n    # short term memory hack\n    if self.max_trackable < 0 or self.n < self.max_trackable:\n      self.n += 1\n    if self.n == 0:\n      self.M_last = new_data\n      self.M = self.M_last\n      self.S_last = 0.\n    else:\n      self.M = self.M_last + (new_data - self.M_last) / self.n\n      self.S = self.S_last + (new_data - self.M_last) * (new_data - self.M)\n      self.M_last = self.M\n      self.S_last = self.S\n\n  def mean(self):\n    return self.M\n\n  def variance(self):\n    if self.n >= 2:\n      return self.S / (self.n - 1.)\n    else:\n      return 0\n\n  def std(self):\n    return np.sqrt(self.variance())\n\n  def params_to_save(self):\n    return [self.M, self.S, self.n]\n\nclass RunningStatFilter():\n  def __init__(self, raw_priors=None, filtered_priors=None, max_trackable=-1):\n    self.raw_stat = RunningStat(raw_priors, -1)\n    self.filtered_stat = RunningStat(filtered_priors, max_trackable)\n\n  def reset(self):\n    self.raw_stat.reset()\n    self.filtered_stat.reset()\n\n  def push_and_update(self, new_data):\n    _std_last = self.raw_stat.std()\n    self.raw_stat.push_data(new_data)\n    _delta_std = self.raw_stat.std() - _std_last\n    if _delta_std <= 0:\n      self.filtered_stat.push_data(new_data)\n    else:\n      pass\n      # self.filtered_stat.push_data(self.filtered_stat.mean())\n\n# class SequentialBayesian():\n"
  },
  {
    "path": "common/text_window.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport time\nimport subprocess\nfrom common.basedir import BASEDIR\n\n\nclass TextWindow:\n  def __init__(self, text):\n    try:\n      self.text_proc = subprocess.Popen([\"./text\", text],\n                                        stdin=subprocess.PIPE,\n                                        cwd=os.path.join(BASEDIR, \"selfdrive\", \"ui\"),\n                                        close_fds=True)\n    except OSError:\n      self.text_proc = None\n\n  def get_status(self):\n    if self.text_proc is not None:\n      self.text_proc.poll()\n      return self.text_proc.returncode\n    return None\n\n  def __enter__(self):\n    return self\n\n  def close(self):\n    if self.text_proc is not None:\n      self.text_proc.terminate()\n      self.text_proc = None\n\n  def wait_for_exit(self):\n    if self.text_proc is not None:\n      while True:\n        if self.get_status() == 1:\n          os.system('/data/openpilot/scripts/reset_update.sh')\n          return\n        time.sleep(0.1)\n\n  def __del__(self):\n    self.close()\n\n  def __exit__(self, exc_type, exc_value, traceback):\n    self.close()\n\n\nif __name__ == \"__main__\":\n  text = \"\"\"Traceback (most recent call last):\n  File \"./controlsd.py\", line 608, in <module>\n    main()\n  File \"./controlsd.py\", line 604, in main\n    controlsd_thread(sm, pm, logcan)\n  File \"./controlsd.py\", line 455, in controlsd_thread\n    1/0\nZeroDivisionError: division by zero\"\"\"\n  print(text)\n\n  with TextWindow(text) as s:\n    for _ in range(100):\n      if s.get_status() == 1:\n        print(\"Got exit button\")\n        break\n      time.sleep(0.1)\n  print(\"gone\")\n"
  },
  {
    "path": "common/timeout.py",
    "content": "import signal\n\nclass TimeoutException(Exception):\n  pass\n\nclass Timeout:\n  \"\"\"\n  Timeout context manager.\n  For example this code will raise a TimeoutException:\n  with Timeout(seconds=5, error_msg=\"Sleep was too long\"):\n    time.sleep(10)\n  \"\"\"\n  def __init__(self, seconds, error_msg=None):\n    if error_msg is None:\n      error_msg = 'Timed out after {} seconds'.format(seconds)\n    self.seconds = seconds\n    self.error_msg = error_msg\n\n  def handle_timeout(self, signume, frame):\n    raise TimeoutException(self.error_msg)\n\n  def __enter__(self):\n    signal.signal(signal.SIGALRM, self.handle_timeout)\n    signal.alarm(self.seconds)\n\n  def __exit__(self, exc_type, exc_val, exc_tb):\n    signal.alarm(0)\n"
  },
  {
    "path": "common/transformations/SConscript",
    "content": "Import('env', 'envCython')\n\ntransformations = env.Library('transformations', ['orientation.cc', 'coordinates.cc'])\nExport('transformations')\n\nenvCython.Program('transformations.so', 'transformations.pyx')\n"
  },
  {
    "path": "common/transformations/__init__.py",
    "content": ""
  },
  {
    "path": "common/transformations/camera.py",
    "content": "import numpy as np\n\nimport common.transformations.orientation as orient\nfrom selfdrive.hardware import TICI\n\n## -- hardcoded hardware params --\neon_f_focal_length = 910.0\neon_d_focal_length = 860.0\nleon_d_focal_length = 650.0\ntici_f_focal_length = 2648.0\ntici_e_focal_length = tici_d_focal_length = 567.0 # probably wrong? magnification is not consistent across frame\n\neon_f_frame_size = (1164, 874)\neon_d_frame_size = (1152, 864)\nleon_d_frame_size = (816, 612)\ntici_f_frame_size = tici_e_frame_size = tici_d_frame_size = (1928, 1208)\n\n# aka 'K' aka camera_frame_from_view_frame\neon_fcam_intrinsics = np.array([\n  [eon_f_focal_length,  0.0,  float(eon_f_frame_size[0])/2],\n  [0.0,  eon_f_focal_length,  float(eon_f_frame_size[1])/2],\n  [0.0,  0.0,                                          1.0]])\neon_intrinsics = eon_fcam_intrinsics # xx\n\nleon_dcam_intrinsics = np.array([\n  [leon_d_focal_length,  0.0,  float(leon_d_frame_size[0])/2],\n  [0.0,  leon_d_focal_length,  float(leon_d_frame_size[1])/2],\n  [0.0,  0.0,                                            1.0]])\n\neon_dcam_intrinsics = np.array([\n  [eon_d_focal_length,  0.0,  float(eon_d_frame_size[0])/2],\n  [0.0,  eon_d_focal_length,  float(eon_d_frame_size[1])/2],\n  [0.0,  0.0,                                          1.0]])\n\ntici_fcam_intrinsics = np.array([\n  [tici_f_focal_length,  0.0,  float(tici_f_frame_size[0])/2],\n  [0.0,  tici_f_focal_length,  float(tici_f_frame_size[1])/2],\n  [0.0,  0.0,                                            1.0]])\n\ntici_dcam_intrinsics = np.array([\n  [tici_d_focal_length,  0.0,  float(tici_d_frame_size[0])/2],\n  [0.0,  tici_d_focal_length,  float(tici_d_frame_size[1])/2],\n  [0.0,  0.0,                                            1.0]])\n\ntici_ecam_intrinsics = tici_dcam_intrinsics\n\n# aka 'K_inv' aka view_frame_from_camera_frame\neon_fcam_intrinsics_inv = np.linalg.inv(eon_fcam_intrinsics)\neon_intrinsics_inv = eon_fcam_intrinsics_inv # xx\n\ntici_fcam_intrinsics_inv = np.linalg.inv(tici_fcam_intrinsics)\ntici_ecam_intrinsics_inv = np.linalg.inv(tici_ecam_intrinsics)\n\n\nif not TICI:\n  FULL_FRAME_SIZE = eon_f_frame_size\n  FOCAL = eon_f_focal_length\n  fcam_intrinsics = eon_fcam_intrinsics\nelse:\n  FULL_FRAME_SIZE = tici_f_frame_size\n  FOCAL = tici_f_focal_length\n  fcam_intrinsics = tici_fcam_intrinsics\n\nW, H = FULL_FRAME_SIZE[0], FULL_FRAME_SIZE[1]\n\n\n# device/mesh : x->forward, y-> right, z->down\n# view : x->right, y->down, z->forward\ndevice_frame_from_view_frame = np.array([\n  [ 0.,  0.,  1.],\n  [ 1.,  0.,  0.],\n  [ 0.,  1.,  0.]\n])\nview_frame_from_device_frame = device_frame_from_view_frame.T\n\n\ndef get_calib_from_vp(vp):\n  vp_norm = normalize(vp)\n  yaw_calib = np.arctan(vp_norm[0])\n  pitch_calib = -np.arctan(vp_norm[1]*np.cos(yaw_calib))\n  roll_calib = 0\n  return roll_calib, pitch_calib, yaw_calib\n\n\n# aka 'extrinsic_matrix'\n# road : x->forward, y -> left, z->up\ndef get_view_frame_from_road_frame(roll, pitch, yaw, height):\n  device_from_road = orient.rot_from_euler([roll, pitch, yaw]).dot(np.diag([1, -1, -1]))\n  view_from_road = view_frame_from_device_frame.dot(device_from_road)\n  return np.hstack((view_from_road, [[0], [height], [0]]))\n\n\n# aka 'extrinsic_matrix'\ndef get_view_frame_from_calib_frame(roll, pitch, yaw, height):\n  device_from_calib= orient.rot_from_euler([roll, pitch, yaw])\n  view_from_calib = view_frame_from_device_frame.dot(device_from_calib)\n  return np.hstack((view_from_calib, [[0], [height], [0]]))\n\n\ndef vp_from_ke(m):\n  \"\"\"\n  Computes the vanishing point from the product of the intrinsic and extrinsic\n  matrices C = KE.\n\n  The vanishing point is defined as lim x->infinity C (x, 0, 0, 1).T\n  \"\"\"\n  return (m[0, 0]/m[2, 0], m[1, 0]/m[2, 0])\n\n\ndef vp_from_rpy(rpy, intrinsics=fcam_intrinsics):\n  e = get_view_frame_from_road_frame(rpy[0], rpy[1], rpy[2], 1.22)\n  ke = np.dot(intrinsics, e)\n  return vp_from_ke(ke)\n\n\ndef roll_from_ke(m):\n  # note: different from calibration.h/RollAnglefromKE: i think that one's just wrong\n  return np.arctan2(-(m[1, 0] - m[1, 1] * m[2, 0] / m[2, 1]),\n                    -(m[0, 0] - m[0, 1] * m[2, 0] / m[2, 1]))\n\n\ndef normalize(img_pts, intrinsics=fcam_intrinsics):\n  # normalizes image coordinates\n  # accepts single pt or array of pts\n  intrinsics_inv = np.linalg.inv(intrinsics)\n  img_pts = np.array(img_pts)\n  input_shape = img_pts.shape\n  img_pts = np.atleast_2d(img_pts)\n  img_pts = np.hstack((img_pts, np.ones((img_pts.shape[0], 1))))\n  img_pts_normalized = img_pts.dot(intrinsics_inv.T)\n  img_pts_normalized[(img_pts < 0).any(axis=1)] = np.nan\n  return img_pts_normalized[:, :2].reshape(input_shape)\n\n\ndef denormalize(img_pts, intrinsics=fcam_intrinsics, width=W, height=H):\n  # denormalizes image coordinates\n  # accepts single pt or array of pts\n  img_pts = np.array(img_pts)\n  input_shape = img_pts.shape\n  img_pts = np.atleast_2d(img_pts)\n  img_pts = np.hstack((img_pts, np.ones((img_pts.shape[0], 1))))\n  img_pts_denormalized = img_pts.dot(intrinsics.T)\n  img_pts_denormalized[img_pts_denormalized[:, 0] > width] = np.nan\n  img_pts_denormalized[img_pts_denormalized[:, 0] < 0] = np.nan\n  img_pts_denormalized[img_pts_denormalized[:, 1] > height] = np.nan\n  img_pts_denormalized[img_pts_denormalized[:, 1] < 0] = np.nan\n  return img_pts_denormalized[:, :2].reshape(input_shape)\n\n\ndef device_from_ecef(pos_ecef, orientation_ecef, pt_ecef):\n  # device from ecef frame\n  # device frame is x -> forward, y-> right, z -> down\n  # accepts single pt or array of pts\n  input_shape = pt_ecef.shape\n  pt_ecef = np.atleast_2d(pt_ecef)\n  ecef_from_device_rot = orient.rotations_from_quats(orientation_ecef)\n  device_from_ecef_rot = ecef_from_device_rot.T\n  pt_ecef_rel = pt_ecef - pos_ecef\n  pt_device = np.einsum('jk,ik->ij', device_from_ecef_rot, pt_ecef_rel)\n  return pt_device.reshape(input_shape)\n\n\ndef img_from_device(pt_device):\n  # img coordinates from pts in device frame\n  # first transforms to view frame, then to img coords\n  # accepts single pt or array of pts\n  input_shape = pt_device.shape\n  pt_device = np.atleast_2d(pt_device)\n  pt_view = np.einsum('jk,ik->ij', view_frame_from_device_frame, pt_device)\n\n  # This function should never return negative depths\n  pt_view[pt_view[:, 2] < 0] = np.nan\n\n  pt_img = pt_view/pt_view[:, 2:3]\n  return pt_img.reshape(input_shape)[:, :2]\n\n\ndef get_camera_frame_from_calib_frame(camera_frame_from_road_frame, intrinsics=fcam_intrinsics):\n  camera_frame_from_ground = camera_frame_from_road_frame[:, (0, 1, 3)]\n  calib_frame_from_ground = np.dot(intrinsics,\n                                     get_view_frame_from_road_frame(0, 0, 0, 1.22))[:, (0, 1, 3)]\n  ground_from_calib_frame = np.linalg.inv(calib_frame_from_ground)\n  camera_frame_from_calib_frame = np.dot(camera_frame_from_ground, ground_from_calib_frame)\n  return camera_frame_from_calib_frame\n"
  },
  {
    "path": "common/transformations/coordinates.cc",
    "content": "#define _USE_MATH_DEFINES\n\n#include <iostream>\n#include <cmath>\n#include <eigen3/Eigen/Dense>\n\n#include \"coordinates.hpp\"\n\n\n\ndouble a = 6378137; // lgtm [cpp/short-global-name]\ndouble b = 6356752.3142; // lgtm [cpp/short-global-name]\ndouble esq = 6.69437999014 * 0.001; // lgtm [cpp/short-global-name]\ndouble e1sq = 6.73949674228 * 0.001;\n\n\nstatic Geodetic to_degrees(Geodetic geodetic){\n  geodetic.lat = RAD2DEG(geodetic.lat);\n  geodetic.lon = RAD2DEG(geodetic.lon);\n  return geodetic;\n}\n\nstatic Geodetic to_radians(Geodetic geodetic){\n  geodetic.lat = DEG2RAD(geodetic.lat);\n  geodetic.lon = DEG2RAD(geodetic.lon);\n  return geodetic;\n}\n\n\nECEF geodetic2ecef(Geodetic g){\n  g = to_radians(g);\n  double xi = sqrt(1.0 - esq * pow(sin(g.lat), 2));\n  double x = (a / xi + g.alt) * cos(g.lat) * cos(g.lon);\n  double y = (a / xi + g.alt) * cos(g.lat) * sin(g.lon);\n  double z = (a / xi * (1.0 - esq) + g.alt) * sin(g.lat);\n  return {x, y, z};\n}\n\nGeodetic ecef2geodetic(ECEF e){\n  // Convert from ECEF to geodetic using Ferrari's methods\n  // https://en.wikipedia.org/wiki/Geographic_coordinate_conversion#Ferrari.27s_solution\n  double x = e.x;\n  double y = e.y;\n  double z = e.z;\n\n  double r = sqrt(x * x + y * y);\n  double Esq = a * a - b * b;\n  double F = 54 * b * b * z * z;\n  double G = r * r + (1 - esq) * z * z - esq * Esq;\n  double C = (esq * esq * F * r * r) / (pow(G, 3));\n  double S = cbrt(1 + C + sqrt(C * C + 2 * C));\n  double P = F / (3 * pow((S + 1 / S + 1), 2) * G * G);\n  double Q = sqrt(1 + 2 * esq * esq * P);\n  double r_0 = -(P * esq * r) / (1 + Q) + sqrt(0.5 * a * a*(1 + 1.0 / Q) - P * (1 - esq) * z * z / (Q * (1 + Q)) - 0.5 * P * r * r);\n  double U = sqrt(pow((r - esq * r_0), 2) + z * z);\n  double V = sqrt(pow((r - esq * r_0), 2) + (1 - esq) * z * z);\n  double Z_0 = b * b * z / (a * V);\n  double h = U * (1 - b * b / (a * V));\n\n  double lat = atan((z + e1sq * Z_0) / r);\n  double lon = atan2(y, x);\n\n  return to_degrees({lat, lon, h});\n}\n\nLocalCoord::LocalCoord(Geodetic g, ECEF e){\n  init_ecef <<  e.x, e.y, e.z;\n\n  g = to_radians(g);\n\n  ned2ecef_matrix <<\n    -sin(g.lat)*cos(g.lon), -sin(g.lon), -cos(g.lat)*cos(g.lon),\n    -sin(g.lat)*sin(g.lon), cos(g.lon), -cos(g.lat)*sin(g.lon),\n    cos(g.lat), 0, -sin(g.lat);\n  ecef2ned_matrix = ned2ecef_matrix.transpose();\n}\n\nNED LocalCoord::ecef2ned(ECEF e) {\n  Eigen::Vector3d ecef;\n  ecef << e.x, e.y, e.z;\n\n  Eigen::Vector3d ned = (ecef2ned_matrix * (ecef - init_ecef));\n  return {ned[0], ned[1], ned[2]};\n}\n\nECEF LocalCoord::ned2ecef(NED n) {\n  Eigen::Vector3d ned;\n  ned << n.n, n.e, n.d;\n\n  Eigen::Vector3d ecef = (ned2ecef_matrix * ned) + init_ecef;\n  return {ecef[0], ecef[1], ecef[2]};\n}\n\nNED LocalCoord::geodetic2ned(Geodetic g) {\n  ECEF e = ::geodetic2ecef(g);\n  return ecef2ned(e);\n}\n\nGeodetic LocalCoord::ned2geodetic(NED n){\n  ECEF e = ned2ecef(n);\n  return ::ecef2geodetic(e);\n}\n"
  },
  {
    "path": "common/transformations/coordinates.hpp",
    "content": "#pragma once\n\n#define DEG2RAD(x) ((x) * M_PI / 180.0)\n#define RAD2DEG(x) ((x) * 180.0 / M_PI)\n\nstruct ECEF {\n  double x, y, z;\n  Eigen::Vector3d to_vector(){\n    return Eigen::Vector3d(x, y, z);\n  }\n};\n\nstruct NED {\n  double n, e, d;\n  Eigen::Vector3d to_vector(){\n    return Eigen::Vector3d(n, e, d);\n  }\n};\n\nstruct Geodetic {\n  double lat, lon, alt;\n  bool radians=false;\n};\n\nECEF geodetic2ecef(Geodetic g);\nGeodetic ecef2geodetic(ECEF e);\n\nclass LocalCoord {\npublic:\n  Eigen::Matrix3d ned2ecef_matrix;\n  Eigen::Matrix3d ecef2ned_matrix;\n  Eigen::Vector3d init_ecef;\n  LocalCoord(Geodetic g, ECEF e);\n  LocalCoord(Geodetic g) : LocalCoord(g, ::geodetic2ecef(g)) {}\n  LocalCoord(ECEF e) : LocalCoord(::ecef2geodetic(e), e) {}\n\n  NED ecef2ned(ECEF e);\n  ECEF ned2ecef(NED n);\n  NED geodetic2ned(Geodetic g);\n  Geodetic ned2geodetic(NED n);\n};\n"
  },
  {
    "path": "common/transformations/coordinates.py",
    "content": "# pylint: skip-file\nfrom common.transformations.orientation import numpy_wrap\nfrom common.transformations.transformations import (ecef2geodetic_single,\n                                                    geodetic2ecef_single)\nfrom common.transformations.transformations import LocalCoord as LocalCoord_single\n\n\nclass LocalCoord(LocalCoord_single):\n  ecef2ned = numpy_wrap(LocalCoord_single.ecef2ned_single, (3,), (3,))\n  ned2ecef = numpy_wrap(LocalCoord_single.ned2ecef_single, (3,), (3,))\n  geodetic2ned = numpy_wrap(LocalCoord_single.geodetic2ned_single, (3,), (3,))\n  ned2geodetic = numpy_wrap(LocalCoord_single.ned2geodetic_single, (3,), (3,))\n\n\ngeodetic2ecef = numpy_wrap(geodetic2ecef_single, (3,), (3,))\necef2geodetic = numpy_wrap(ecef2geodetic_single, (3,), (3,))\n\ngeodetic_from_ecef = ecef2geodetic\necef_from_geodetic = geodetic2ecef\n"
  },
  {
    "path": "common/transformations/model.py",
    "content": "import numpy as np\n\nfrom common.transformations.camera import (FULL_FRAME_SIZE,\n                                           FOCAL,\n                                           get_view_frame_from_road_frame,\n                                           get_view_frame_from_calib_frame,\n                                           vp_from_ke)\n\n# segnet\nSEGNET_SIZE = (512, 384)\n\ndef get_segnet_frame_from_camera_frame(segnet_size=SEGNET_SIZE, full_frame_size=FULL_FRAME_SIZE):\n  return np.array([[float(segnet_size[0]) / full_frame_size[0],  0.0],\n                   [0.0,  float(segnet_size[1]) / full_frame_size[1]]])\nsegnet_frame_from_camera_frame = get_segnet_frame_from_camera_frame() # xx\n\n# model\nMODEL_INPUT_SIZE = (320, 160)\nMODEL_YUV_SIZE = (MODEL_INPUT_SIZE[0], MODEL_INPUT_SIZE[1] * 3 // 2)\nMODEL_CX = MODEL_INPUT_SIZE[0] / 2.\nMODEL_CY = 21.\n\nmodel_fl = 728.0\nmodel_height = 1.22\n\n# canonical model transform\nmodel_intrinsics = np.array([\n  [model_fl,  0.0,  MODEL_CX],\n  [0.0,  model_fl,  MODEL_CY],\n  [0.0,  0.0,            1.0]])\n\n\n# MED model\nMEDMODEL_INPUT_SIZE = (512, 256)\nMEDMODEL_YUV_SIZE = (MEDMODEL_INPUT_SIZE[0], MEDMODEL_INPUT_SIZE[1] * 3 // 2)\nMEDMODEL_CY = 47.6\n\nmedmodel_fl = 910.0\nmedmodel_intrinsics = np.array([\n  [medmodel_fl,  0.0,  0.5 * MEDMODEL_INPUT_SIZE[0]],\n  [0.0,  medmodel_fl,                   MEDMODEL_CY],\n  [0.0,  0.0,                                   1.0]])\n\n\n# CAL model\nCALMODEL_INPUT_SIZE = (512, 256)\nCALMODEL_YUV_SIZE = (CALMODEL_INPUT_SIZE[0], CALMODEL_INPUT_SIZE[1] * 3 // 2)\nCALMODEL_CY = 47.6\n\ncalmodel_fl = 606.7\ncalmodel_intrinsics = np.array([\n  [calmodel_fl,  0.0,  0.5 * CALMODEL_INPUT_SIZE[0]],\n  [0.0,  calmodel_fl,                   CALMODEL_CY],\n  [0.0,  0.0,                                   1.0]])\n\n\n# BIG model\nBIGMODEL_INPUT_SIZE = (1024, 512)\nBIGMODEL_YUV_SIZE = (BIGMODEL_INPUT_SIZE[0], BIGMODEL_INPUT_SIZE[1] * 3 // 2)\n\nbigmodel_fl = 910.0\nbigmodel_intrinsics = np.array([\n  [bigmodel_fl,  0.0,  0.5 * BIGMODEL_INPUT_SIZE[0]],\n  [0.0,  bigmodel_fl,             256 + MEDMODEL_CY],\n  [0.0,  0.0,                                   1.0]])\n\n\n# SBIG model (big model with the size of small model)\nSBIGMODEL_INPUT_SIZE = (512, 256)\nSBIGMODEL_YUV_SIZE = (SBIGMODEL_INPUT_SIZE[0], SBIGMODEL_INPUT_SIZE[1] * 3 // 2)\n\nsbigmodel_fl = 455.0\nsbigmodel_intrinsics = np.array([\n  [sbigmodel_fl,  0.0,  0.5 * SBIGMODEL_INPUT_SIZE[0]],\n  [0.0,  sbigmodel_fl,      0.5 * (256 + MEDMODEL_CY)],\n  [0.0,  0.0,                                     1.0]])\n\nmodel_frame_from_road_frame = np.dot(model_intrinsics,\n  get_view_frame_from_road_frame(0, 0, 0, model_height))\n\nbigmodel_frame_from_road_frame = np.dot(bigmodel_intrinsics,\n  get_view_frame_from_road_frame(0, 0, 0, model_height))\n\nmedmodel_frame_from_road_frame = np.dot(medmodel_intrinsics,\n  get_view_frame_from_road_frame(0, 0, 0, model_height))\n\nmedmodel_frame_from_calib_frame = np.dot(medmodel_intrinsics,\n  get_view_frame_from_calib_frame(0, 0, 0, 0))\n\nmodel_frame_from_bigmodel_frame = np.dot(model_intrinsics, np.linalg.inv(bigmodel_intrinsics))\nmedmodel_frame_from_bigmodel_frame = np.dot(medmodel_intrinsics, np.linalg.inv(bigmodel_intrinsics))\n\n\n# 'camera from model camera'\ndef get_model_height_transform(camera_frame_from_road_frame, height):\n  camera_frame_from_road_ground = np.dot(camera_frame_from_road_frame, np.array([\n    [1, 0, 0],\n    [0, 1, 0],\n    [0, 0, 0],\n    [0, 0, 1],\n  ]))\n\n  camera_frame_from_road_high = np.dot(camera_frame_from_road_frame, np.array([\n    [1, 0, 0],\n    [0, 1, 0],\n    [0, 0, height - model_height],\n    [0, 0, 1],\n  ]))\n\n  road_high_from_camera_frame = np.linalg.inv(camera_frame_from_road_high)\n  high_camera_from_low_camera = np.dot(camera_frame_from_road_ground, road_high_from_camera_frame)\n\n  return high_camera_from_low_camera\n\n\n# camera_frame_from_model_frame aka 'warp matrix'\n# was: calibration.h/CalibrationTransform\ndef get_camera_frame_from_model_frame(camera_frame_from_road_frame, height=model_height, camera_fl=FOCAL):\n  vp = vp_from_ke(camera_frame_from_road_frame)\n\n  model_zoom = camera_fl / model_fl\n  model_camera_from_model_frame = np.array([\n    [model_zoom,  0.0,  vp[0] - MODEL_CX * model_zoom],\n    [0.0,  model_zoom,  vp[1] - MODEL_CY * model_zoom],\n    [0.0,  0.0,                                   1.0],\n  ])\n\n  # This function is super slow, so skip it if height is very close to canonical\n  # TODO: speed it up!\n  if abs(height - model_height) > 0.001:\n    camera_from_model_camera = get_model_height_transform(camera_frame_from_road_frame, height)\n  else:\n    camera_from_model_camera = np.eye(3)\n\n  return np.dot(camera_from_model_camera, model_camera_from_model_frame)\n\n\ndef get_camera_frame_from_medmodel_frame(camera_frame_from_road_frame):\n  camera_frame_from_ground = camera_frame_from_road_frame[:, (0, 1, 3)]\n  medmodel_frame_from_ground = medmodel_frame_from_road_frame[:, (0, 1, 3)]\n\n  ground_from_medmodel_frame = np.linalg.inv(medmodel_frame_from_ground)\n  camera_frame_from_medmodel_frame = np.dot(camera_frame_from_ground, ground_from_medmodel_frame)\n\n  return camera_frame_from_medmodel_frame\n\n\ndef get_camera_frame_from_bigmodel_frame(camera_frame_from_road_frame):\n  camera_frame_from_ground = camera_frame_from_road_frame[:, (0, 1, 3)]\n  bigmodel_frame_from_ground = bigmodel_frame_from_road_frame[:, (0, 1, 3)]\n\n  ground_from_bigmodel_frame = np.linalg.inv(bigmodel_frame_from_ground)\n  camera_frame_from_bigmodel_frame = np.dot(camera_frame_from_ground, ground_from_bigmodel_frame)\n\n  return camera_frame_from_bigmodel_frame\n\n\ndef get_model_frame(snu_full, camera_frame_from_model_frame, size):\n  idxs = camera_frame_from_model_frame.dot(np.column_stack([np.tile(np.arange(size[0]), size[1]),\n                                                            np.tile(np.arange(size[1]), (size[0], 1)).T.flatten(),\n                                                            np.ones(size[0] * size[1])]).T).T.astype(int)\n  calib_flat = snu_full[idxs[:, 1], idxs[:, 0]]\n  if len(snu_full.shape) == 3:\n    calib = calib_flat.reshape((size[1], size[0], 3))\n  elif len(snu_full.shape) == 2:\n    calib = calib_flat.reshape((size[1], size[0]))\n  else:\n    raise ValueError(\"shape of input img is weird\")\n  return calib\n"
  },
  {
    "path": "common/transformations/orientation.cc",
    "content": "#define _USE_MATH_DEFINES\n\n#include <iostream>\n#include <cmath>\n#include <eigen3/Eigen/Dense>\n\n#include \"orientation.hpp\"\n#include \"coordinates.hpp\"\n\nEigen::Quaterniond ensure_unique(Eigen::Quaterniond quat){\n  if (quat.w() > 0){\n    return quat;\n  } else {\n    return Eigen::Quaterniond(-quat.w(), -quat.x(), -quat.y(), -quat.z());\n  }\n}\n\nEigen::Quaterniond euler2quat(Eigen::Vector3d euler){\n  Eigen::Quaterniond q;\n\n  q = Eigen::AngleAxisd(euler(2), Eigen::Vector3d::UnitZ())\n    * Eigen::AngleAxisd(euler(1), Eigen::Vector3d::UnitY())\n    * Eigen::AngleAxisd(euler(0), Eigen::Vector3d::UnitX());\n  return ensure_unique(q);\n}\n\n\nEigen::Vector3d quat2euler(Eigen::Quaterniond quat){\n  // TODO: switch to eigen implementation if the range of the Euler angles doesn't matter anymore\n  // Eigen::Vector3d euler = quat.toRotationMatrix().eulerAngles(2, 1, 0);\n  // return {euler(2), euler(1), euler(0)};\n  double gamma = atan2(2 * (quat.w() * quat.x() + quat.y() * quat.z()), 1 - 2 * (quat.x()*quat.x() + quat.y()*quat.y()));\n  double asin_arg_clipped = std::clamp(2 * (quat.w() * quat.y() - quat.z() * quat.x()), -1.0, 1.0);\n  double theta = asin(asin_arg_clipped);\n  double psi = atan2(2 * (quat.w() * quat.z() + quat.x() * quat.y()), 1 - 2 * (quat.y()*quat.y() + quat.z()*quat.z()));\n  return {gamma, theta, psi};\n}\n\nEigen::Matrix3d quat2rot(Eigen::Quaterniond quat){\n  return quat.toRotationMatrix();\n}\n\nEigen::Quaterniond rot2quat(const Eigen::Matrix3d &rot){\n  return ensure_unique(Eigen::Quaterniond(rot));\n}\n\nEigen::Matrix3d euler2rot(Eigen::Vector3d euler){\n  return quat2rot(euler2quat(euler));\n}\n\nEigen::Vector3d rot2euler(const Eigen::Matrix3d &rot){\n  return quat2euler(rot2quat(rot));\n}\n\nEigen::Matrix3d rot_matrix(double roll, double pitch, double yaw){\n  return euler2rot({roll, pitch, yaw});\n}\n\nEigen::Matrix3d rot(Eigen::Vector3d axis, double angle){\n  Eigen::Quaterniond q;\n  q = Eigen::AngleAxisd(angle, axis);\n  return q.toRotationMatrix();\n}\n\n\nEigen::Vector3d ecef_euler_from_ned(ECEF ecef_init, Eigen::Vector3d ned_pose) {\n  /*\n    Using Rotations to Build Aerospace Coordinate Systems\n    Don Koks\n    https://apps.dtic.mil/dtic/tr/fulltext/u2/a484864.pdf\n  */\n  LocalCoord converter = LocalCoord(ecef_init);\n  Eigen::Vector3d zero = ecef_init.to_vector();\n\n  Eigen::Vector3d x0 = converter.ned2ecef({1, 0, 0}).to_vector() - zero;\n  Eigen::Vector3d y0 = converter.ned2ecef({0, 1, 0}).to_vector() - zero;\n  Eigen::Vector3d z0 = converter.ned2ecef({0, 0, 1}).to_vector() - zero;\n\n  Eigen::Vector3d x1 = rot(z0, ned_pose(2)) * x0;\n  Eigen::Vector3d y1 = rot(z0, ned_pose(2)) * y0;\n  Eigen::Vector3d z1 = rot(z0, ned_pose(2)) * z0;\n\n  Eigen::Vector3d x2 = rot(y1, ned_pose(1)) * x1;\n  Eigen::Vector3d y2 = rot(y1, ned_pose(1)) * y1;\n  Eigen::Vector3d z2 = rot(y1, ned_pose(1)) * z1;\n\n  Eigen::Vector3d x3 = rot(x2, ned_pose(0)) * x2;\n  Eigen::Vector3d y3 = rot(x2, ned_pose(0)) * y2;\n\n\n  x0 = Eigen::Vector3d(1, 0, 0);\n  y0 = Eigen::Vector3d(0, 1, 0);\n  z0 = Eigen::Vector3d(0, 0, 1);\n\n  double psi = atan2(x3.dot(y0), x3.dot(x0));\n  double theta = atan2(-x3.dot(z0), sqrt(pow(x3.dot(x0), 2) + pow(x3.dot(y0), 2)));\n\n  y2 = rot(z0, psi) * y0;\n  z2 = rot(y2, theta) * z0;\n\n  double phi = atan2(y3.dot(z2), y3.dot(y2));\n\n  return {phi, theta, psi};\n}\n\nEigen::Vector3d ned_euler_from_ecef(ECEF ecef_init, Eigen::Vector3d ecef_pose){\n  /*\n    Using Rotations to Build Aerospace Coordinate Systems\n    Don Koks\n    https://apps.dtic.mil/dtic/tr/fulltext/u2/a484864.pdf\n  */\n  LocalCoord converter = LocalCoord(ecef_init);\n\n  Eigen::Vector3d x0 = Eigen::Vector3d(1, 0, 0);\n  Eigen::Vector3d y0 = Eigen::Vector3d(0, 1, 0);\n  Eigen::Vector3d z0 = Eigen::Vector3d(0, 0, 1);\n\n  Eigen::Vector3d x1 = rot(z0, ecef_pose(2)) * x0;\n  Eigen::Vector3d y1 = rot(z0, ecef_pose(2)) * y0;\n  Eigen::Vector3d z1 = rot(z0, ecef_pose(2)) * z0;\n\n  Eigen::Vector3d x2 = rot(y1, ecef_pose(1)) * x1;\n  Eigen::Vector3d y2 = rot(y1, ecef_pose(1)) * y1;\n  Eigen::Vector3d z2 = rot(y1, ecef_pose(1)) * z1;\n\n  Eigen::Vector3d x3 = rot(x2, ecef_pose(0)) * x2;\n  Eigen::Vector3d y3 = rot(x2, ecef_pose(0)) * y2;\n\n  Eigen::Vector3d zero = ecef_init.to_vector();\n  x0 = converter.ned2ecef({1, 0, 0}).to_vector() - zero;\n  y0 = converter.ned2ecef({0, 1, 0}).to_vector() - zero;\n  z0 = converter.ned2ecef({0, 0, 1}).to_vector() - zero;\n\n  double psi = atan2(x3.dot(y0), x3.dot(x0));\n  double theta = atan2(-x3.dot(z0), sqrt(pow(x3.dot(x0), 2) + pow(x3.dot(y0), 2)));\n\n  y2 = rot(z0, psi) * y0;\n  z2 = rot(y2, theta) * z0;\n\n  double phi = atan2(y3.dot(z2), y3.dot(y2));\n\n  return {phi, theta, psi};\n}\n\n"
  },
  {
    "path": "common/transformations/orientation.hpp",
    "content": "#pragma once\n#include <eigen3/Eigen/Dense>\n#include \"coordinates.hpp\"\n\n\nEigen::Quaterniond ensure_unique(Eigen::Quaterniond quat);\n\nEigen::Quaterniond euler2quat(Eigen::Vector3d euler);\nEigen::Vector3d quat2euler(Eigen::Quaterniond quat);\nEigen::Matrix3d quat2rot(Eigen::Quaterniond quat);\nEigen::Quaterniond rot2quat(const Eigen::Matrix3d &rot);\nEigen::Matrix3d euler2rot(Eigen::Vector3d euler);\nEigen::Vector3d rot2euler(const Eigen::Matrix3d &rot);\nEigen::Matrix3d rot_matrix(double roll, double pitch, double yaw);\nEigen::Matrix3d rot(Eigen::Vector3d axis, double angle);\nEigen::Vector3d ecef_euler_from_ned(ECEF ecef_init, Eigen::Vector3d ned_pose);\nEigen::Vector3d ned_euler_from_ecef(ECEF ecef_init, Eigen::Vector3d ecef_pose);\n"
  },
  {
    "path": "common/transformations/orientation.py",
    "content": "# pylint: skip-file\nimport numpy as np\n\nfrom common.transformations.transformations import (ecef_euler_from_ned_single,\n                                                    euler2quat_single,\n                                                    euler2rot_single,\n                                                    ned_euler_from_ecef_single,\n                                                    quat2euler_single,\n                                                    quat2rot_single,\n                                                    rot2euler_single,\n                                                    rot2quat_single)\n\n\ndef numpy_wrap(function, input_shape, output_shape):\n  \"\"\"Wrap a function to take either an input or list of inputs and return the correct shape\"\"\"\n  def f(*inps):\n    *args, inp = inps\n    inp = np.array(inp)\n    shape = inp.shape\n\n    if len(shape) == len(input_shape):\n      out_shape = output_shape\n    else:\n      out_shape = (shape[0],) + output_shape\n\n    # Add empty dimension if inputs is not a list\n    if len(shape) == len(input_shape):\n      inp.shape = (1, ) + inp.shape\n\n    result = np.asarray([function(*args, i) for i in inp])\n    result.shape = out_shape\n    return result\n  return f\n\n\neuler2quat = numpy_wrap(euler2quat_single, (3,), (4,))\nquat2euler = numpy_wrap(quat2euler_single, (4,), (3,))\nquat2rot = numpy_wrap(quat2rot_single, (4,), (3, 3))\nrot2quat = numpy_wrap(rot2quat_single, (3, 3), (4,))\neuler2rot = numpy_wrap(euler2rot_single, (3,), (3, 3))\nrot2euler = numpy_wrap(rot2euler_single, (3, 3), (3,))\necef_euler_from_ned = numpy_wrap(ecef_euler_from_ned_single, (3,), (3,))\nned_euler_from_ecef = numpy_wrap(ned_euler_from_ecef_single, (3,), (3,))\n\nquats_from_rotations = rot2quat\nquat_from_rot = rot2quat\nrotations_from_quats = quat2rot\nrot_from_quat = quat2rot\neuler_from_rot = rot2euler\neuler_from_quat = quat2euler\nrot_from_euler = euler2rot\nquat_from_euler = euler2quat\n"
  },
  {
    "path": "common/transformations/transformations.pxd",
    "content": "#cython: language_level=3\nfrom libcpp cimport bool\n\ncdef extern from \"orientation.cc\":\n  pass\n\ncdef extern from \"orientation.hpp\":\n  cdef cppclass Quaternion \"Eigen::Quaterniond\":\n    Quaternion()\n    Quaternion(double, double, double, double)\n    double w()\n    double x()\n    double y()\n    double z()\n\n  cdef cppclass Vector3 \"Eigen::Vector3d\":\n    Vector3()\n    Vector3(double, double, double)\n    double operator()(int)\n\n  cdef cppclass Matrix3 \"Eigen::Matrix3d\":\n    Matrix3()\n    Matrix3(double*)\n\n    double operator()(int, int)\n\n  Quaternion euler2quat(Vector3)\n  Vector3 quat2euler(Quaternion)\n  Matrix3 quat2rot(Quaternion)\n  Quaternion rot2quat(Matrix3)\n  Vector3 rot2euler(Matrix3)\n  Matrix3 euler2rot(Vector3)\n  Matrix3 rot_matrix(double, double, double)\n  Vector3 ecef_euler_from_ned(ECEF, Vector3)\n  Vector3 ned_euler_from_ecef(ECEF, Vector3)\n\n\ncdef extern from \"coordinates.cc\":\n  cdef struct ECEF:\n    double x\n    double y\n    double z\n\n  cdef struct NED:\n    double n\n    double e\n    double d\n\n  cdef struct Geodetic:\n    double lat\n    double lon\n    double alt\n    bool radians\n\n  ECEF geodetic2ecef(Geodetic)\n  Geodetic ecef2geodetic(ECEF)\n\n  cdef cppclass LocalCoord_c \"LocalCoord\":\n    Matrix3 ned2ecef_matrix\n    Matrix3 ecef2ned_matrix\n\n    LocalCoord_c(Geodetic, ECEF)\n    LocalCoord_c(Geodetic)\n    LocalCoord_c(ECEF)\n\n    NED ecef2ned(ECEF)\n    ECEF ned2ecef(NED)\n    NED geodetic2ned(Geodetic)\n    Geodetic ned2geodetic(NED)\n\ncdef extern from \"coordinates.hpp\":\n  pass\n"
  },
  {
    "path": "common/transformations/transformations.pyx",
    "content": "# distutils: language = c++\n# cython: language_level = 3\nfrom common.transformations.transformations cimport Matrix3, Vector3, Quaternion\nfrom common.transformations.transformations cimport ECEF, NED, Geodetic\n\nfrom common.transformations.transformations cimport euler2quat as euler2quat_c\nfrom common.transformations.transformations cimport quat2euler as quat2euler_c\nfrom common.transformations.transformations cimport quat2rot as quat2rot_c\nfrom common.transformations.transformations cimport rot2quat as rot2quat_c\nfrom common.transformations.transformations cimport euler2rot as euler2rot_c\nfrom common.transformations.transformations cimport rot2euler as rot2euler_c\nfrom common.transformations.transformations cimport rot_matrix as rot_matrix_c\nfrom common.transformations.transformations cimport ecef_euler_from_ned as ecef_euler_from_ned_c\nfrom common.transformations.transformations cimport ned_euler_from_ecef as ned_euler_from_ecef_c\nfrom common.transformations.transformations cimport geodetic2ecef as geodetic2ecef_c\nfrom common.transformations.transformations cimport ecef2geodetic as ecef2geodetic_c\nfrom common.transformations.transformations cimport LocalCoord_c\n\n\nimport cython\nimport numpy as np\ncimport numpy as np\n\ncdef np.ndarray[double, ndim=2] matrix2numpy(Matrix3 m):\n    return np.array([\n        [m(0, 0), m(0, 1), m(0, 2)],\n        [m(1, 0), m(1, 1), m(1, 2)],\n        [m(2, 0), m(2, 1), m(2, 2)],\n    ])\n\ncdef Matrix3 numpy2matrix(np.ndarray[double, ndim=2, mode=\"fortran\"] m):\n    assert m.shape[0] == 3\n    assert m.shape[1] == 3\n    return Matrix3(<double*>m.data)\n\ncdef ECEF list2ecef(ecef):\n    cdef ECEF e;\n    e.x = ecef[0]\n    e.y = ecef[1]\n    e.z = ecef[2]\n    return e\n\ncdef NED list2ned(ned):\n    cdef NED n;\n    n.n = ned[0]\n    n.e = ned[1]\n    n.d = ned[2]\n    return n\n\ncdef Geodetic list2geodetic(geodetic):\n    cdef Geodetic g\n    g.lat = geodetic[0]\n    g.lon = geodetic[1]\n    g.alt = geodetic[2]\n    return g\n\ndef euler2quat_single(euler):\n    cdef Vector3 e = Vector3(euler[0], euler[1], euler[2])\n    cdef Quaternion q = euler2quat_c(e)\n    return [q.w(), q.x(), q.y(), q.z()]\n\ndef quat2euler_single(quat):\n    cdef Quaternion q = Quaternion(quat[0], quat[1], quat[2], quat[3])\n    cdef Vector3 e = quat2euler_c(q);\n    return [e(0), e(1), e(2)]\n\ndef quat2rot_single(quat):\n    cdef Quaternion q = Quaternion(quat[0], quat[1], quat[2], quat[3])\n    cdef Matrix3 r = quat2rot_c(q)\n    return matrix2numpy(r)\n\ndef rot2quat_single(rot):\n    cdef Matrix3 r = numpy2matrix(np.asfortranarray(rot, dtype=np.double))\n    cdef Quaternion q = rot2quat_c(r)\n    return [q.w(), q.x(), q.y(), q.z()]\n\ndef euler2rot_single(euler):\n    cdef Vector3 e = Vector3(euler[0], euler[1], euler[2])\n    cdef Matrix3 r = euler2rot_c(e)\n    return matrix2numpy(r)\n\ndef rot2euler_single(rot):\n    cdef Matrix3 r = numpy2matrix(np.asfortranarray(rot, dtype=np.double))\n    cdef Vector3 e = rot2euler_c(r)\n    return [e(0), e(1), e(2)]\n\ndef rot_matrix(roll, pitch, yaw):\n    return matrix2numpy(rot_matrix_c(roll, pitch, yaw))\n\ndef ecef_euler_from_ned_single(ecef_init, ned_pose):\n    cdef ECEF init = list2ecef(ecef_init)\n    cdef Vector3 pose = Vector3(ned_pose[0], ned_pose[1], ned_pose[2])\n\n    cdef Vector3 e = ecef_euler_from_ned_c(init, pose)\n    return [e(0), e(1), e(2)]\n\ndef ned_euler_from_ecef_single(ecef_init, ecef_pose):\n    cdef ECEF init = list2ecef(ecef_init)\n    cdef Vector3 pose = Vector3(ecef_pose[0], ecef_pose[1], ecef_pose[2])\n\n    cdef Vector3 e = ned_euler_from_ecef_c(init, pose)\n    return [e(0), e(1), e(2)]\n\ndef geodetic2ecef_single(geodetic):\n    cdef Geodetic g = list2geodetic(geodetic)\n    cdef ECEF e = geodetic2ecef_c(g)\n    return [e.x, e.y, e.z]\n\ndef ecef2geodetic_single(ecef):\n    cdef ECEF e = list2ecef(ecef)\n    cdef Geodetic g = ecef2geodetic_c(e)\n    return [g.lat, g.lon, g.alt]\n\n\ncdef class LocalCoord:\n    cdef LocalCoord_c * lc\n\n    def __init__(self, geodetic=None, ecef=None):\n        assert (geodetic is not None) or (ecef is not None)\n        if geodetic is not None:\n            self.lc = new LocalCoord_c(list2geodetic(geodetic))\n        elif ecef is not None:\n            self.lc = new LocalCoord_c(list2ecef(ecef))\n\n    @property\n    def ned2ecef_matrix(self):\n        return matrix2numpy(self.lc.ned2ecef_matrix)\n\n    @property\n    def ecef2ned_matrix(self):\n        return matrix2numpy(self.lc.ecef2ned_matrix)\n\n    @property\n    def ned_from_ecef_matrix(self):\n        return self.ecef2ned_matrix\n\n    @property\n    def ecef_from_ned_matrix(self):\n        return self.ned2ecef_matrix\n\n    @classmethod\n    def from_geodetic(cls, geodetic):\n        return cls(geodetic=geodetic)\n\n    @classmethod\n    def from_ecef(cls, ecef):\n        return cls(ecef=ecef)\n\n    def ecef2ned_single(self, ecef):\n        assert self.lc\n        cdef ECEF e = list2ecef(ecef)\n        cdef NED n = self.lc.ecef2ned(e)\n        return [n.n, n.e, n.d]\n\n    def ned2ecef_single(self, ned):\n        assert self.lc\n        cdef NED n = list2ned(ned)\n        cdef ECEF e = self.lc.ned2ecef(n)\n        return [e.x, e.y, e.z]\n\n    def geodetic2ned_single(self, geodetic):\n        assert self.lc\n        cdef Geodetic g = list2geodetic(geodetic)\n        cdef NED n = self.lc.geodetic2ned(g)\n        return [n.n, n.e, n.d]\n\n    def ned2geodetic_single(self, ned):\n        assert self.lc\n        cdef NED n = list2ned(ned)\n        cdef Geodetic g = self.lc.ned2geodetic(n)\n        return [g.lat, g.lon, g.alt]\n\n    def __dealloc__(self):\n        del self.lc\n"
  },
  {
    "path": "common/xattr.py",
    "content": "import os\nfrom cffi import FFI\n\n# Workaround for the EON/termux build of Python having os.*xattr removed.\nffi = FFI()\nffi.cdef(\"\"\"\nint setxattr(const char *path, const char *name, const void *value, size_t size, int flags);\nssize_t getxattr(const char *path, const char *name, void *value, size_t size);\nssize_t listxattr(const char *path, char *list, size_t size);\nint removexattr(const char *path, const char *name);\n\"\"\")\nlibc = ffi.dlopen(None)\n\ndef setxattr(path, name, value, flags=0):\n  path = path.encode()\n  name = name.encode()\n  if libc.setxattr(path, name, value, len(value), flags) == -1:\n    raise OSError(ffi.errno, f\"{os.strerror(ffi.errno)}: setxattr({path}, {name}, {value}, {flags})\")\n\ndef getxattr(path, name, size=128):\n  path = path.encode()\n  name = name.encode()\n  value = ffi.new(f\"char[{size}]\")\n  l = libc.getxattr(path, name, value, size)\n  if l == -1:\n    # errno 61 means attribute hasn't been set\n    if ffi.errno == 61:\n      return None\n    raise OSError(ffi.errno, f\"{os.strerror(ffi.errno)}: getxattr({path}, {name}, {size})\")\n  return ffi.buffer(value)[:l]\n\ndef listxattr(path, size=128):\n  path = path.encode()\n  attrs = ffi.new(f\"char[{size}]\")\n  l = libc.listxattr(path, attrs, size)\n  if l == -1:\n    raise OSError(ffi.errno, f\"{os.strerror(ffi.errno)}: listxattr({path}, {size})\")\n  # attrs is b'\\0' delimited values (so chop off trailing empty item)\n  return [a.decode() for a in ffi.buffer(attrs)[:l].split(b\"\\0\")[0:-1]]\n\ndef removexattr(path, name):\n  path = path.encode()\n  name = name.encode()\n  if libc.removexattr(path, name) == -1:\n    raise OSError(ffi.errno, f\"{os.strerror(ffi.errno)}: removexattr({path}, {name})\")\n"
  },
  {
    "path": "installer/custom/install_gfortran.sh",
    "content": "#!/data/data/com.termux/files/usr/bin/sh\n# Get some needed tools. coreutils for mkdir command, gnugp for the signing key, and apt-transport-https to actually connect to the repo\napt-get update\napt-get --assume-yes upgrade\napt-get --assume-yes install coreutils gnupg\n\n# Make the sources.list.d directory\nmkdir -p $PREFIX/etc/apt/sources.list.d\n\n# Write the needed source file\necho \"deb https://its-pointless.github.io/files/24 termux extras\" > $PREFIX/etc/apt/sources.list.d/pointless.list\n\n# Add signing key from https://its-pointless.github.io/pointless.gpg\ncurl -sL https://its-pointless.github.io/pointless.gpg | apt-key add -\n\n# Update apt\napt update\n\n# install gfortran\napt install gcc-11 -y\nsetupclang-gfort-11\n\n# Elf cleaner is needed to remove a DT_ENTRY warning that prints out when gfortran -v is called to get \n# its version number and this breaks the pip installation script when fortran is used.\n\n# Build elf cleaner\nSCRIPTPATH=\"$( cd -- \"$(dirname \"$0\")\" >/dev/null 2>&1 ; pwd -P )\"\nELFCLEANERPATH=$SCRIPTPATH/termux-elf-cleaner/\ncd $ELFCLEANERPATH\nmake\n\n# Perform elf cleaner on gfortran\n./termux-elf-cleaner $(which gfortran)\n\n"
  },
  {
    "path": "installer/custom/termux-elf-cleaner/COPYING",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 3, 29 June 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU General Public License is a free, copyleft license for\nsoftware and other kinds of works.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nthe GNU General Public License is intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.  We, the Free Software Foundation, use the\nGNU General Public License for most of our software; it applies also to\nany other work released this way by its authors.  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthem if you wish), that you receive source code or can get it if you\nwant it, that you can change the software or use pieces of it in new\nfree programs, and that you know you can do these things.\n\n  To protect your rights, we need to prevent others from denying you\nthese rights or asking you to surrender the rights.  Therefore, you have\ncertain responsibilities if you distribute copies of the software, or if\nyou modify it: responsibilities to respect the freedom of others.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must pass on to the recipients the same\nfreedoms that you received.  You must make sure that they, too, receive\nor can get the source code.  And you must show them these terms so they\nknow their rights.\n\n  Developers that use the GNU GPL protect your rights with two steps:\n(1) assert copyright on the software, and (2) offer you this License\ngiving you legal permission to copy, distribute and/or modify it.\n\n  For the developers' and authors' protection, the GPL clearly explains\nthat there is no warranty for this free software.  For both users' and\nauthors' sake, the GPL requires that modified versions be marked as\nchanged, so that their problems will not be attributed erroneously to\nauthors of previous versions.\n\n  Some devices are designed to deny users access to install or run\nmodified versions of the software inside them, although the manufacturer\ncan do so.  This is fundamentally incompatible with the aim of\nprotecting users' freedom to change the software.  The systematic\npattern of such abuse occurs in the area of products for individuals to\nuse, which is precisely where it is most unacceptable.  Therefore, we\nhave designed this version of the GPL to prohibit the practice for those\nproducts.  If such problems arise substantially in other domains, we\nstand ready to extend this provision to those domains in future versions\nof the GPL, as needed to protect the freedom of users.\n\n  Finally, every program is threatened constantly by software patents.\nStates should not allow patents to restrict development and use of\nsoftware on general-purpose computers, but in those that do, we wish to\navoid the special danger that patents applied to a free program could\nmake it effectively proprietary.  To prevent this, the GPL assures that\npatents cannot be used to render the program non-free.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                       TERMS AND CONDITIONS\n\n  0. Definitions.\n\n  \"This License\" refers to version 3 of the GNU General Public License.\n\n  \"Copyright\" also means copyright-like laws that apply to other kinds of\nworks, such as semiconductor masks.\n\n  \"The Program\" refers to any copyrightable work licensed under this\nLicense.  Each licensee is addressed as \"you\".  \"Licensees\" and\n\"recipients\" may be individuals or organizations.\n\n  To \"modify\" a work means to copy from or adapt all or part of the work\nin a fashion requiring copyright permission, other than the making of an\nexact copy.  The resulting work is called a \"modified version\" of the\nearlier work or a work \"based on\" the earlier work.\n\n  A \"covered work\" means either the unmodified Program or a work based\non the Program.\n\n  To \"propagate\" a work means to do anything with it that, without\npermission, would make you directly or secondarily liable for\ninfringement under applicable copyright law, except executing it on a\ncomputer or modifying a private copy.  Propagation includes copying,\ndistribution (with or without modification), making available to the\npublic, and in some countries other activities as well.\n\n  To \"convey\" a work means any kind of propagation that enables other\nparties to make or receive copies.  Mere interaction with a user through\na computer network, with no transfer of a copy, is not conveying.\n\n  An interactive user interface displays \"Appropriate Legal Notices\"\nto the extent that it includes a convenient and prominently visible\nfeature that (1) displays an appropriate copyright notice, and (2)\ntells the user that there is no warranty for the work (except to the\nextent that warranties are provided), that licensees may convey the\nwork under this License, and how to view a copy of this License.  If\nthe interface presents a list of user commands or options, such as a\nmenu, a prominent item in the list meets this criterion.\n\n  1. Source Code.\n\n  The \"source code\" for a work means the preferred form of the work\nfor making modifications to it.  \"Object code\" means any non-source\nform of a work.\n\n  A \"Standard Interface\" means an interface that either is an official\nstandard defined by a recognized standards body, or, in the case of\ninterfaces specified for a particular programming language, one that\nis widely used among developers working in that language.\n\n  The \"System Libraries\" of an executable work include anything, other\nthan the work as a whole, that (a) is included in the normal form of\npackaging a Major Component, but which is not part of that Major\nComponent, and (b) serves only to enable use of the work with that\nMajor Component, or to implement a Standard Interface for which an\nimplementation is available to the public in source code form.  A\n\"Major Component\", in this context, means a major essential component\n(kernel, window system, and so on) of the specific operating system\n(if any) on which the executable work runs, or a compiler used to\nproduce the work, or an object code interpreter used to run it.\n\n  The \"Corresponding Source\" for a work in object code form means all\nthe source code needed to generate, install, and (for an executable\nwork) run the object code and to modify the work, including scripts to\ncontrol those activities.  However, it does not include the work's\nSystem Libraries, or general-purpose tools or generally available free\nprograms which are used unmodified in performing those activities but\nwhich are not part of the work.  For example, Corresponding Source\nincludes interface definition files associated with source files for\nthe work, and the source code for shared libraries and dynamically\nlinked subprograms that the work is specifically designed to require,\nsuch as by intimate data communication or control flow between those\nsubprograms and other parts of the work.\n\n  The Corresponding Source need not include anything that users\ncan regenerate automatically from other parts of the Corresponding\nSource.\n\n  The Corresponding Source for a work in source code form is that\nsame work.\n\n  2. Basic Permissions.\n\n  All rights granted under this License are granted for the term of\ncopyright on the Program, and are irrevocable provided the stated\nconditions are met.  This License explicitly affirms your unlimited\npermission to run the unmodified Program.  The output from running a\ncovered work is covered by this License only if the output, given its\ncontent, constitutes a covered work.  This License acknowledges your\nrights of fair use or other equivalent, as provided by copyright law.\n\n  You may make, run and propagate covered works that you do not\nconvey, without conditions so long as your license otherwise remains\nin force.  You may convey covered works to others for the sole purpose\nof having them make modifications exclusively for you, or provide you\nwith facilities for running those works, provided that you comply with\nthe terms of this License in conveying all material for which you do\nnot control copyright.  Those thus making or running the covered works\nfor you must do so exclusively on your behalf, under your direction\nand control, on terms that prohibit them from making any copies of\nyour copyrighted material outside their relationship with you.\n\n  Conveying under any other circumstances is permitted solely under\nthe conditions stated below.  Sublicensing is not allowed; section 10\nmakes it unnecessary.\n\n  3. Protecting Users' Legal Rights From Anti-Circumvention Law.\n\n  No covered work shall be deemed part of an effective technological\nmeasure under any applicable law fulfilling obligations under article\n11 of the WIPO copyright treaty adopted on 20 December 1996, or\nsimilar laws prohibiting or restricting circumvention of such\nmeasures.\n\n  When you convey a covered work, you waive any legal power to forbid\ncircumvention of technological measures to the extent such circumvention\nis effected by exercising rights under this License with respect to\nthe covered work, and you disclaim any intention to limit operation or\nmodification of the work as a means of enforcing, against the work's\nusers, your or third parties' legal rights to forbid circumvention of\ntechnological measures.\n\n  4. Conveying Verbatim Copies.\n\n  You may convey verbatim copies of the Program's source code as you\nreceive it, in any medium, provided that you conspicuously and\nappropriately publish on each copy an appropriate copyright notice;\nkeep intact all notices stating that this License and any\nnon-permissive terms added in accord with section 7 apply to the code;\nkeep intact all notices of the absence of any warranty; and give all\nrecipients a copy of this License along with the Program.\n\n  You may charge any price or no price for each copy that you convey,\nand you may offer support or warranty protection for a fee.\n\n  5. Conveying Modified Source Versions.\n\n  You may convey a work based on the Program, or the modifications to\nproduce it from the Program, in the form of source code under the\nterms of section 4, provided that you also meet all of these conditions:\n\n    a) The work must carry prominent notices stating that you modified\n    it, and giving a relevant date.\n\n    b) The work must carry prominent notices stating that it is\n    released under this License and any conditions added under section\n    7.  This requirement modifies the requirement in section 4 to\n    \"keep intact all notices\".\n\n    c) You must license the entire work, as a whole, under this\n    License to anyone who comes into possession of a copy.  This\n    License will therefore apply, along with any applicable section 7\n    additional terms, to the whole of the work, and all its parts,\n    regardless of how they are packaged.  This License gives no\n    permission to license the work in any other way, but it does not\n    invalidate such permission if you have separately received it.\n\n    d) If the work has interactive user interfaces, each must display\n    Appropriate Legal Notices; however, if the Program has interactive\n    interfaces that do not display Appropriate Legal Notices, your\n    work need not make them do so.\n\n  A compilation of a covered work with other separate and independent\nworks, which are not by their nature extensions of the covered work,\nand which are not combined with it such as to form a larger program,\nin or on a volume of a storage or distribution medium, is called an\n\"aggregate\" if the compilation and its resulting copyright are not\nused to limit the access or legal rights of the compilation's users\nbeyond what the individual works permit.  Inclusion of a covered work\nin an aggregate does not cause this License to apply to the other\nparts of the aggregate.\n\n  6. Conveying Non-Source Forms.\n\n  You may convey a covered work in object code form under the terms\nof sections 4 and 5, provided that you also convey the\nmachine-readable Corresponding Source under the terms of this License,\nin one of these ways:\n\n    a) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by the\n    Corresponding Source fixed on a durable physical medium\n    customarily used for software interchange.\n\n    b) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by a\n    written offer, valid for at least three years and valid for as\n    long as you offer spare parts or customer support for that product\n    model, to give anyone who possesses the object code either (1) a\n    copy of the Corresponding Source for all the software in the\n    product that is covered by this License, on a durable physical\n    medium customarily used for software interchange, for a price no\n    more than your reasonable cost of physically performing this\n    conveying of source, or (2) access to copy the\n    Corresponding Source from a network server at no charge.\n\n    c) Convey individual copies of the object code with a copy of the\n    written offer to provide the Corresponding Source.  This\n    alternative is allowed only occasionally and noncommercially, and\n    only if you received the object code with such an offer, in accord\n    with subsection 6b.\n\n    d) Convey the object code by offering access from a designated\n    place (gratis or for a charge), and offer equivalent access to the\n    Corresponding Source in the same way through the same place at no\n    further charge.  You need not require recipients to copy the\n    Corresponding Source along with the object code.  If the place to\n    copy the object code is a network server, the Corresponding Source\n    may be on a different server (operated by you or a third party)\n    that supports equivalent copying facilities, provided you maintain\n    clear directions next to the object code saying where to find the\n    Corresponding Source.  Regardless of what server hosts the\n    Corresponding Source, you remain obligated to ensure that it is\n    available for as long as needed to satisfy these requirements.\n\n    e) Convey the object code using peer-to-peer transmission, provided\n    you inform other peers where the object code and Corresponding\n    Source of the work are being offered to the general public at no\n    charge under subsection 6d.\n\n  A separable portion of the object code, whose source code is excluded\nfrom the Corresponding Source as a System Library, need not be\nincluded in conveying the object code work.\n\n  A \"User Product\" is either (1) a \"consumer product\", which means any\ntangible personal property which is normally used for personal, family,\nor household purposes, or (2) anything designed or sold for incorporation\ninto a dwelling.  In determining whether a product is a consumer product,\ndoubtful cases shall be resolved in favor of coverage.  For a particular\nproduct received by a particular user, \"normally used\" refers to a\ntypical or common use of that class of product, regardless of the status\nof the particular user or of the way in which the particular user\nactually uses, or expects or is expected to use, the product.  A product\nis a consumer product regardless of whether the product has substantial\ncommercial, industrial or non-consumer uses, unless such uses represent\nthe only significant mode of use of the product.\n\n  \"Installation Information\" for a User Product means any methods,\nprocedures, authorization keys, or other information required to install\nand execute modified versions of a covered work in that User Product from\na modified version of its Corresponding Source.  The information must\nsuffice to ensure that the continued functioning of the modified object\ncode is in no case prevented or interfered with solely because\nmodification has been made.\n\n  If you convey an object code work under this section in, or with, or\nspecifically for use in, a User Product, and the conveying occurs as\npart of a transaction in which the right of possession and use of the\nUser Product is transferred to the recipient in perpetuity or for a\nfixed term (regardless of how the transaction is characterized), the\nCorresponding Source conveyed under this section must be accompanied\nby the Installation Information.  But this requirement does not apply\nif neither you nor any third party retains the ability to install\nmodified object code on the User Product (for example, the work has\nbeen installed in ROM).\n\n  The requirement to provide Installation Information does not include a\nrequirement to continue to provide support service, warranty, or updates\nfor a work that has been modified or installed by the recipient, or for\nthe User Product in which it has been modified or installed.  Access to a\nnetwork may be denied when the modification itself materially and\nadversely affects the operation of the network or violates the rules and\nprotocols for communication across the network.\n\n  Corresponding Source conveyed, and Installation Information provided,\nin accord with this section must be in a format that is publicly\ndocumented (and with an implementation available to the public in\nsource code form), and must require no special password or key for\nunpacking, reading or copying.\n\n  7. Additional Terms.\n\n  \"Additional permissions\" are terms that supplement the terms of this\nLicense by making exceptions from one or more of its conditions.\nAdditional permissions that are applicable to the entire Program shall\nbe treated as though they were included in this License, to the extent\nthat they are valid under applicable law.  If additional permissions\napply only to part of the Program, that part may be used separately\nunder those permissions, but the entire Program remains governed by\nthis License without regard to the additional permissions.\n\n  When you convey a copy of a covered work, you may at your option\nremove any additional permissions from that copy, or from any part of\nit.  (Additional permissions may be written to require their own\nremoval in certain cases when you modify the work.)  You may place\nadditional permissions on material, added by you to a covered work,\nfor which you have or can give appropriate copyright permission.\n\n  Notwithstanding any other provision of this License, for material you\nadd to a covered work, you may (if authorized by the copyright holders of\nthat material) supplement the terms of this License with terms:\n\n    a) Disclaiming warranty or limiting liability differently from the\n    terms of sections 15 and 16 of this License; or\n\n    b) Requiring preservation of specified reasonable legal notices or\n    author attributions in that material or in the Appropriate Legal\n    Notices displayed by works containing it; or\n\n    c) Prohibiting misrepresentation of the origin of that material, or\n    requiring that modified versions of such material be marked in\n    reasonable ways as different from the original version; or\n\n    d) Limiting the use for publicity purposes of names of licensors or\n    authors of the material; or\n\n    e) Declining to grant rights under trademark law for use of some\n    trade names, trademarks, or service marks; or\n\n    f) Requiring indemnification of licensors and authors of that\n    material by anyone who conveys the material (or modified versions of\n    it) with contractual assumptions of liability to the recipient, for\n    any liability that these contractual assumptions directly impose on\n    those licensors and authors.\n\n  All other non-permissive additional terms are considered \"further\nrestrictions\" within the meaning of section 10.  If the Program as you\nreceived it, or any part of it, contains a notice stating that it is\ngoverned by this License along with a term that is a further\nrestriction, you may remove that term.  If a license document contains\na further restriction but permits relicensing or conveying under this\nLicense, you may add to a covered work material governed by the terms\nof that license document, provided that the further restriction does\nnot survive such relicensing or conveying.\n\n  If you add terms to a covered work in accord with this section, you\nmust place, in the relevant source files, a statement of the\nadditional terms that apply to those files, or a notice indicating\nwhere to find the applicable terms.\n\n  Additional terms, permissive or non-permissive, may be stated in the\nform of a separately written license, or stated as exceptions;\nthe above requirements apply either way.\n\n  8. Termination.\n\n  You may not propagate or modify a covered work except as expressly\nprovided under this License.  Any attempt otherwise to propagate or\nmodify it is void, and will automatically terminate your rights under\nthis License (including any patent licenses granted under the third\nparagraph of section 11).\n\n  However, if you cease all violation of this License, then your\nlicense from a particular copyright holder is reinstated (a)\nprovisionally, unless and until the copyright holder explicitly and\nfinally terminates your license, and (b) permanently, if the copyright\nholder fails to notify you of the violation by some reasonable means\nprior to 60 days after the cessation.\n\n  Moreover, your license from a particular copyright holder is\nreinstated permanently if the copyright holder notifies you of the\nviolation by some reasonable means, this is the first time you have\nreceived notice of violation of this License (for any work) from that\ncopyright holder, and you cure the violation prior to 30 days after\nyour receipt of the notice.\n\n  Termination of your rights under this section does not terminate the\nlicenses of parties who have received copies or rights from you under\nthis License.  If your rights have been terminated and not permanently\nreinstated, you do not qualify to receive new licenses for the same\nmaterial under section 10.\n\n  9. Acceptance Not Required for Having Copies.\n\n  You are not required to accept this License in order to receive or\nrun a copy of the Program.  Ancillary propagation of a covered work\noccurring solely as a consequence of using peer-to-peer transmission\nto receive a copy likewise does not require acceptance.  However,\nnothing other than this License grants you permission to propagate or\nmodify any covered work.  These actions infringe copyright if you do\nnot accept this License.  Therefore, by modifying or propagating a\ncovered work, you indicate your acceptance of this License to do so.\n\n  10. Automatic Licensing of Downstream Recipients.\n\n  Each time you convey a covered work, the recipient automatically\nreceives a license from the original licensors, to run, modify and\npropagate that work, subject to this License.  You are not responsible\nfor enforcing compliance by third parties with this License.\n\n  An \"entity transaction\" is a transaction transferring control of an\norganization, or substantially all assets of one, or subdividing an\norganization, or merging organizations.  If propagation of a covered\nwork results from an entity transaction, each party to that\ntransaction who receives a copy of the work also receives whatever\nlicenses to the work the party's predecessor in interest had or could\ngive under the previous paragraph, plus a right to possession of the\nCorresponding Source of the work from the predecessor in interest, if\nthe predecessor has it or can get it with reasonable efforts.\n\n  You may not impose any further restrictions on the exercise of the\nrights granted or affirmed under this License.  For example, you may\nnot impose a license fee, royalty, or other charge for exercise of\nrights granted under this License, and you may not initiate litigation\n(including a cross-claim or counterclaim in a lawsuit) alleging that\nany patent claim is infringed by making, using, selling, offering for\nsale, or importing the Program or any portion of it.\n\n  11. Patents.\n\n  A \"contributor\" is a copyright holder who authorizes use under this\nLicense of the Program or a work on which the Program is based.  The\nwork thus licensed is called the contributor's \"contributor version\".\n\n  A contributor's \"essential patent claims\" are all patent claims\nowned or controlled by the contributor, whether already acquired or\nhereafter acquired, that would be infringed by some manner, permitted\nby this License, of making, using, or selling its contributor version,\nbut do not include claims that would be infringed only as a\nconsequence of further modification of the contributor version.  For\npurposes of this definition, \"control\" includes the right to grant\npatent sublicenses in a manner consistent with the requirements of\nthis License.\n\n  Each contributor grants you a non-exclusive, worldwide, royalty-free\npatent license under the contributor's essential patent claims, to\nmake, use, sell, offer for sale, import and otherwise run, modify and\npropagate the contents of its contributor version.\n\n  In the following three paragraphs, a \"patent license\" is any express\nagreement or commitment, however denominated, not to enforce a patent\n(such as an express permission to practice a patent or covenant not to\nsue for patent infringement).  To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n  If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients.  \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n  If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n  A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License.  You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n  Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n  12. No Surrender of Others' Freedom.\n\n  If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all.  For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n  13. Use with the GNU Affero General Public License.\n\n  Notwithstanding any other provision of this License, you have\npermission to link or combine any covered work with a work licensed\nunder version 3 of the GNU Affero General Public License into a single\ncombined work, and to convey the resulting work.  The terms of this\nLicense will continue to apply to the part which is the covered work,\nbut the special requirements of the GNU Affero General Public License,\nsection 13, concerning interaction through a network will apply to the\ncombination as such.\n\n  14. Revised Versions of this License.\n\n  The Free Software Foundation may publish revised and/or new versions of\nthe GNU General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\n  Each version is given a distinguishing version number.  If the\nProgram specifies that a certain numbered version of the GNU General\nPublic License \"or any later version\" applies to it, you have the\noption of following the terms and conditions either of that numbered\nversion or of any later version published by the Free Software\nFoundation.  If the Program does not specify a version number of the\nGNU General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n  If the Program specifies that a proxy can decide which future\nversions of the GNU General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n  Later license versions may give you additional or different\npermissions.  However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n  15. Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    {one line to give the program's name and a brief idea of what it does.}\n    Copyright (C) {year}  {name of author}\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If the program does terminal interaction, make it output a short\nnotice like this when it starts in an interactive mode:\n\n    {project}  Copyright (C) {year}  {fullname}\n    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, your program's commands\nmight be different; for a GUI interface, you would use an \"about box\".\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU GPL, see\n<http://www.gnu.org/licenses/>.\n\n  The GNU General Public License does not permit incorporating your program\ninto proprietary programs.  If your program is a subroutine library, you\nmay consider it more useful to permit linking proprietary applications with\nthe library.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.  But first, please read\n<http://www.gnu.org/philosophy/why-not-lgpl.html>.\n"
  },
  {
    "path": "installer/custom/termux-elf-cleaner/Makefile",
    "content": "CXXFLAGS += -std=c++11 -Wall -Wextra -pedantic\nPREFIX ?= /usr/local\n\ntermux-elf-cleaner: termux-elf-cleaner.cpp\n\nclean:\n\trm -f termux-elf-cleaner\n\ninstall: termux-elf-cleaner\n\tmkdir -p $(PREFIX)/bin\n\tinstall termux-elf-cleaner $(PREFIX)/bin/termux-elf-cleaner\n\nuninstall:\n\trm -f $(PREFIX)/bin/termux-elf-cleaner\n\n.PHONY: clean install uninstall\n"
  },
  {
    "path": "installer/custom/termux-elf-cleaner/README.md",
    "content": "# termux-elf-cleaner\nUtility for Android ELF files to remove unused parts that the linker warns about.\n\n## Description\nWhen loading ELF files, the Android linker warns about unsupported dynamic section entries with warnings such as:\n\n    WARNING: linker: /data/data/org.kost.nmap.android.networkmapper/bin/nmap: unused DT entry: type 0x6ffffffe arg 0x8a7d4\n    WARNING: linker: /data/data/org.kost.nmap.android.networkmapper/bin/nmap: unused DT entry: type 0x6fffffff arg 0x3\n\nThis utility strips away the following dynamic section entries:\n\n- `DT_RPATH` - not supported in any Android version.\n- `DT_RUNPATH` - supported from Android 7.0.\n- `DT_VERDEF` - supported from Android 6.0.\n- `DT_VERDEFNUM` - supported from Android 6.0.\n- `DT_VERNEEDED` - supported from Android 6.0.\n- `DT_VERNEEDNUM` - supported from Android 6.0.\n- `DT_VERSYM` - supported from Android 6.0.\n\nIt also removes the three ELF sections of type:\n\n- `SHT_GNU_verdef`\n- `SHT_GNU_verneed`\n- `SHT_GNU_versym`\n\n## Usage\n```sh\nusage: termux-elf-cleaner <filenames>\n\nProcesses ELF files to remove unsupported section types and\ndynamic section entries which the Android linker warns about.\n```\n\n## Author\nFredrik Fornwall ([@fornwall](https://github.com/fornwall)).\n\n## License\n\nSPDX-License-Identifier: [GPL-3.0-or-later](https://spdx.org/licenses/GPL-3.0-or-later.html)\n"
  },
  {
    "path": "installer/custom/termux-elf-cleaner/elf.h",
    "content": "#ifndef ELF_H_INCLUDED\n#define ELF_H_INCLUDED\n\n#include <stdint.h>\n\n/* Type for a 16-bit quantity.  */\ntypedef uint16_t Elf32_Half;\ntypedef uint16_t Elf64_Half;\n\n/* Types for signed and unsigned 32-bit quantities.  */\ntypedef uint32_t Elf32_Word;\ntypedef int32_t  Elf32_Sword;\ntypedef uint32_t Elf64_Word;\ntypedef int32_t  Elf64_Sword;\n\n/* Types for signed and unsigned 64-bit quantities.  */\ntypedef uint64_t Elf32_Xword;\ntypedef int64_t  Elf32_Sxword;\ntypedef uint64_t Elf64_Xword;\ntypedef int64_t  Elf64_Sxword;\n\n/* Type of addresses.  */\ntypedef uint32_t Elf32_Addr;\ntypedef uint64_t Elf64_Addr;\n\n/* Type of file offsets.  */\ntypedef uint32_t Elf32_Off;\ntypedef uint64_t Elf64_Off;\n\n/* Type for section indices, which are 16-bit quantities.  */\ntypedef uint16_t Elf32_Section;\ntypedef uint16_t Elf64_Section;\n\n/* Type for version symbol information.  */\ntypedef Elf32_Half Elf32_Versym;\ntypedef Elf64_Half Elf64_Versym;\n\n\n/* The ELF file header.  This appears at the start of every ELF file.  */\ntypedef struct {\n\tunsigned char e_ident[16];     /* Magic number and other info */\n\tElf32_Half    e_type;                 /* Object file type */\n\tElf32_Half    e_machine;              /* Architecture */\n\tElf32_Word    e_version;              /* Object file version */\n\tElf32_Addr    e_entry;                /* Entry point virtual address */\n\tElf32_Off     e_phoff;                /* Program header table (usually follows elf header directly) file offset */\n\tElf32_Off     e_shoff;                /* Section header table (at end of file) file offset */\n\tElf32_Word    e_flags;                /* Processor-specific flags */\n\tElf32_Half    e_ehsize;               /* ELF header size in bytes */\n\tElf32_Half    e_phentsize;            /* Program header table entry size */\n\tElf32_Half    e_phnum;                /* Program header table entry count */\n\tElf32_Half    e_shentsize;            /* Section header table entry size */\n\tElf32_Half    e_shnum;                /* Section header table entry count */\n\tElf32_Half    e_shstrndx;             /* Section header string table index */\n} Elf32_Ehdr;\ntypedef struct {\n\tunsigned char e_ident[16];     /* Magic number and other info */\n\tElf64_Half    e_type;                 /* Object file type */\n\tElf64_Half    e_machine;              /* Architecture */\n\tElf64_Word    e_version;              /* Object file version */\n\tElf64_Addr    e_entry;                /* Entry point virtual address */\n\tElf64_Off     e_phoff;                /* Program header table file offset */\n\tElf64_Off     e_shoff;                /* Section header table file offset */\n\tElf64_Word    e_flags;                /* Processor-specific flags */\n\tElf64_Half    e_ehsize;               /* ELF header size in bytes */\n\tElf64_Half    e_phentsize;            /* Program header table entry size */\n\tElf64_Half    e_phnum;                /* Program header table entry count */\n\tElf64_Half    e_shentsize;            /* Section header table entry size */\n\tElf64_Half    e_shnum;                /* Section header table entry count */\n\tElf64_Half    e_shstrndx;             /* Section header string table index */\n} Elf64_Ehdr;\n\n/* Section header entry. The number of section entries in the file are determined by the \"e_shnum\" field of the ELF header.*/\ntypedef struct {\n\tElf32_Word    sh_name;                /* Section name (string tbl index) */\n\tElf32_Word    sh_type;                /* Section type */\n\tElf32_Word    sh_flags;               /* Section flags */\n\tElf32_Addr    sh_addr;                /* Section virtual addr at execution */\n\tElf32_Off     sh_offset;              /* Section file offset */\n\tElf32_Word    sh_size;                /* Section size in bytes */\n\tElf32_Word    sh_link;                /* Link to another section */\n\tElf32_Word    sh_info;                /* Additional section information */\n\tElf32_Word    sh_addralign;           /* Section alignment */\n\tElf32_Word    sh_entsize;             /* Entry size if section holds table */\n} Elf32_Shdr;\ntypedef struct {\n\tElf64_Word    sh_name;                /* Section name (string tbl index) */\n\tElf64_Word    sh_type;                /* Section type */\n\tElf64_Xword   sh_flags;               /* Section flags */\n\tElf64_Addr    sh_addr;                /* Section virtual addr at execution */\n\tElf64_Off     sh_offset;              /* Section file offset */\n\tElf64_Xword   sh_size;                /* Section size in bytes */\n\tElf64_Word    sh_link;                /* Link to another section */\n\tElf64_Word    sh_info;                /* Additional section information */\n\tElf64_Xword   sh_addralign;           /* Section alignment */\n\tElf64_Xword   sh_entsize;             /* Entry size if section holds table */\n} Elf64_Shdr;\n\n/* Legal values for sh_type (section type).  */\n#define SHT_NULL          0             /* Section header table entry unused */\n#define SHT_PROGBITS      1             /* Program data */\n#define SHT_SYMTAB        2             /* Symbol table */\n#define SHT_STRTAB        3             /* String table */\n#define SHT_RELA          4             /* Relocation entries with addends */\n#define SHT_HASH          5             /* Symbol hash table */\n#define SHT_DYNAMIC       6             /* Dynamic linking information. Contains Elf32_Dyn/Elf64_Dyn entries. */\n#define SHT_NOTE          7             /* Notes */\n#define SHT_NOBITS        8             /* Program space with no data (bss) */\n#define SHT_REL           9             /* Relocation entries, no addends */\n#define SHT_SHLIB         10            /* Reserved */\n#define SHT_DYNSYM        11            /* Dynamic linker symbol table */\n#define SHT_INIT_ARRAY    14            /* Array of constructors */\n#define SHT_FINI_ARRAY    15            /* Array of destructors */\n#define SHT_PREINIT_ARRAY 16            /* Array of pre-constructors */\n#define SHT_GROUP         17            /* Section group */\n#define SHT_SYMTAB_SHNDX  18            /* Extended section indeces */\n#define SHT_NUM           19            /* Number of defined types.  */\n#define SHT_LOOS          0x60000000    /* Start OS-specific.  */\n#define SHT_GNU_ATTRIBUTES 0x6ffffff5   /* Object attributes.  */\n#define SHT_GNU_HASH      0x6ffffff6    /* GNU-style hash table.  */\n#define SHT_GNU_LIBLIST   0x6ffffff7    /* Prelink library list */\n#define SHT_CHECKSUM      0x6ffffff8    /* Checksum for DSO content.  */\n#define SHT_LOSUNW        0x6ffffffa    /* Sun-specific low bound.  */\n#define SHT_SUNW_move     0x6ffffffa\n#define SHT_SUNW_COMDAT   0x6ffffffb\n#define SHT_SUNW_syminfo  0x6ffffffc\n#define SHT_GNU_verdef    0x6ffffffd    /* Version definition section.  */\n#define SHT_GNU_verneed   0x6ffffffe    /* Version needs section.  */\n#define SHT_GNU_versym    0x6fffffff    /* Version symbol table.  */\n#define SHT_HISUNW        0x6fffffff    /* Sun-specific high bound.  */\n#define SHT_HIOS          0x6fffffff    /* End OS-specific type */\n#define SHT_LOPROC        0x70000000    /* Start of processor-specific */\n#define SHT_HIPROC        0x7fffffff    /* End of processor-specific */\n#define SHT_LOUSER        0x80000000    /* Start of application-specific */\n#define SHT_HIUSER        0x8fffffff    /* End of application-specific */\n\n/* Dynamic section entry.  */\ntypedef struct {\n\tElf32_Sword d_tag;                  \t\t\t/* Dynamic entry type */\n\tunion { Elf32_Word d_val; Elf32_Addr d_ptr; } d_un; \t/* Integer or address value */\n} Elf32_Dyn;\ntypedef struct {\n\tElf64_Sxword d_tag;                  \t\t\t/* Dynamic entry type */\n\tunion { Elf64_Xword d_val; Elf64_Addr d_ptr; } d_un;\t/* Integer or address value */\n} Elf64_Dyn;\n\n/* Legal values for d_tag (dynamic entry type).  */\n#define DT_NULL         0               /* Marks end of dynamic section */\n#define DT_NEEDED       1               /* Name of needed library */\n#define DT_PLTRELSZ     2               /* Size in bytes of PLT relocs */\n#define DT_PLTGOT       3               /* Processor defined value */\n#define DT_HASH         4               /* Address of symbol hash table */\n#define DT_STRTAB       5               /* Address of string table */\n#define DT_SYMTAB       6               /* Address of symbol table */\n#define DT_RELA         7               /* Address of Rela relocs */\n#define DT_RELASZ       8               /* Total size of Rela relocs */\n#define DT_RELAENT      9               /* Size of one Rela reloc */\n#define DT_STRSZ        10              /* Size of string table */\n#define DT_SYMENT       11              /* Size of one symbol table entry */\n#define DT_INIT         12              /* Address of init function */\n#define DT_FINI         13              /* Address of termination function */\n#define DT_SONAME       14              /* Name of shared object */\n#define DT_RPATH        15              /* Library search path (deprecated) */\n#define DT_SYMBOLIC     16              /* Start symbol search here */\n#define DT_REL          17              /* Address of Rel relocs */\n#define DT_RELSZ        18              /* Total size of Rel relocs */\n#define DT_RELENT       19              /* Size of one Rel reloc */\n#define DT_PLTREL       20              /* Type of reloc in PLT */\n#define DT_DEBUG        21              /* For debugging; unspecified */\n#define DT_TEXTREL      22              /* Reloc might modify .text */\n#define DT_JMPREL       23              /* Address of PLT relocs */\n#define DT_BIND_NOW     24              /* Process relocations of object */\n#define DT_INIT_ARRAY   25              /* Array with addresses of init fct */\n#define DT_FINI_ARRAY   26              /* Array with addresses of fini fct */\n#define DT_INIT_ARRAYSZ 27              /* Size in bytes of DT_INIT_ARRAY */\n#define DT_FINI_ARRAYSZ 28              /* Size in bytes of DT_FINI_ARRAY */\n#define DT_RUNPATH      29              /* Library search path */\n#define DT_FLAGS        30              /* Flags for the object being loaded */\n#define DT_ENCODING     32              /* Start of encoded range */\n#define DT_PREINIT_ARRAY 32             /* Array with addresses of preinit fct*/\n#define DT_PREINIT_ARRAYSZ 33           /* size in bytes of DT_PREINIT_ARRAY */\n#define DT_NUM          34              /* Number used */\n#define DT_LOOS         0x6000000d      /* Start of OS-specific */\n#define DT_HIOS         0x6ffff000      /* End of OS-specific */\n#define DT_VERDEF       0x6ffffffc\n#define DT_VERDEFNUM    0x6ffffffd\n#define DT_LOPROC       0x70000000      /* Start of processor-specific */\n#define DT_HIPROC       0x7fffffff      /* End of processor-specific */\n\n\n/* Symbol table entry.  */\ntypedef struct {\n\tElf32_Word    st_name;                /* Symbol name (string tbl index) */\n\tElf32_Addr    st_value;               /* Symbol value */\n\tElf32_Word    st_size;                /* Symbol size */\n\tunsigned char st_info;                /* Symbol type and binding */\n\tunsigned char st_other;               /* Symbol visibility */\n\tElf32_Section st_shndx;               /* Section index */\n} Elf32_Sym;\n\ntypedef struct {\n\tElf64_Word    st_name;                /* Symbol name (string tbl index) */\n\tunsigned char st_info;                /* Symbol type and binding */\n\tunsigned char st_other;               /* Symbol visibility */\n\tElf64_Section st_shndx;               /* Section index */\n\tElf64_Addr    st_value;               /* Symbol value */\n\tElf64_Xword   st_size;                /* Symbol size */\n} Elf64_Sym;\n\n\n#endif\n"
  },
  {
    "path": "installer/custom/termux-elf-cleaner/termux-elf-cleaner.cpp",
    "content": "#include <algorithm>\n#include <fcntl.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <unistd.h>\n\n#ifndef __ANDROID_API__\n#define __ANDROID_API__ 21\n#endif\n\n// Include a local elf.h copy as not all platforms have it.\n#include \"elf.h\"\n\n#define DT_GNU_HASH 0x6ffffef5\n#define DT_VERSYM 0x6ffffff0\n#define DT_FLAGS_1 0x6ffffffb\n#define DT_VERNEEDED 0x6ffffffe\n#define DT_VERNEEDNUM 0x6fffffff\n\n#define DF_1_NOW\t0x00000001\t/* Set RTLD_NOW for this object.  */\n#define DF_1_GLOBAL\t0x00000002\t/* Set RTLD_GLOBAL for this object.  */\n#define DF_1_NODELETE\t0x00000008\t/* Set RTLD_NODELETE for this object.*/\n\n#if __ANDROID_API__ < 23\n#define SUPPORTED_DT_FLAGS_1 (DF_1_NOW | DF_1_GLOBAL)\n#else\n// The supported DT_FLAGS_1 values as of Android 6.0.\n#define SUPPORTED_DT_FLAGS_1 (DF_1_NOW | DF_1_GLOBAL | DF_1_NODELETE)\n#endif\n\ntemplate<typename ElfHeaderType /*Elf{32,64}_Ehdr*/,\n\t typename ElfSectionHeaderType /*Elf{32,64}_Shdr*/,\n\t typename ElfDynamicSectionEntryType /* Elf{32,64}_Dyn */>\nbool process_elf(uint8_t* bytes, size_t elf_file_size, char const* file_name)\n{\n\tif (sizeof(ElfSectionHeaderType) > elf_file_size) {\n\t\tfprintf(stderr, \"termux-elf-cleaner: Elf header for '%s' would end at %zu but file size only %zu\\n\", file_name, sizeof(ElfSectionHeaderType), elf_file_size);\n\t\treturn false;\n\t}\n\tElfHeaderType* elf_hdr = reinterpret_cast<ElfHeaderType*>(bytes);\n\n\tsize_t last_section_header_byte = elf_hdr->e_shoff + sizeof(ElfSectionHeaderType) * elf_hdr->e_shnum;\n\tif (last_section_header_byte > elf_file_size) {\n\t\tfprintf(stderr, \"termux-elf-cleaner: Section header for '%s' would end at %zu but file size only %zu\\n\", file_name, last_section_header_byte, elf_file_size);\n\t\treturn false;\n\t}\n\tElfSectionHeaderType* section_header_table = reinterpret_cast<ElfSectionHeaderType*>(bytes + elf_hdr->e_shoff);\n\n\tfor (unsigned int i = 1; i < elf_hdr->e_shnum; i++) {\n\t\tElfSectionHeaderType* section_header_entry = section_header_table + i;\n\t\tif (section_header_entry->sh_type == SHT_DYNAMIC) {\n\t\t\tsize_t const last_dynamic_section_byte = section_header_entry->sh_offset + section_header_entry->sh_size;\n\t\t\tif (last_dynamic_section_byte > elf_file_size) {\n\t\t\t\tfprintf(stderr, \"termux-elf-cleaner: Dynamic section for '%s' would end at %zu but file size only %zu\\n\", file_name, last_dynamic_section_byte, elf_file_size);\n\t\t\t\treturn false;\n\t\t\t}\n\n\t\t\tsize_t const dynamic_section_entries = section_header_entry->sh_size / sizeof(ElfDynamicSectionEntryType);\n\t\t\tElfDynamicSectionEntryType* const dynamic_section =\n\t\t\t\treinterpret_cast<ElfDynamicSectionEntryType*>(bytes + section_header_entry->sh_offset);\n\n\t\t\tunsigned int last_nonnull_entry_idx = 0;\n\t\t\tfor (unsigned int j = dynamic_section_entries - 1; j > 0; j--) {\n\t\t\t\tElfDynamicSectionEntryType* dynamic_section_entry = dynamic_section + j;\n\t\t\t\tif (dynamic_section_entry->d_tag != DT_NULL) {\n\t\t\t\t\tlast_nonnull_entry_idx = j;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tfor (unsigned int j = 0; j < dynamic_section_entries; j++) {\n\t\t\t\tElfDynamicSectionEntryType* dynamic_section_entry = dynamic_section + j;\n\t\t\t\tchar const* removed_name = nullptr;\n\t\t\t\tswitch (dynamic_section_entry->d_tag) {\n#if __ANDROID_API__ <= 21\n\t\t\t\t\tcase DT_GNU_HASH: removed_name = \"DT_GNU_HASH\"; break;\n#endif\n#if __ANDROID_API__ < 23\n\t\t\t\t\tcase DT_VERSYM: removed_name = \"DT_VERSYM\"; break;\n\t\t\t\t\tcase DT_VERNEEDED: removed_name = \"DT_VERNEEDED\"; break;\n\t\t\t\t\tcase DT_VERNEEDNUM: removed_name = \"DT_VERNEEDNUM\"; break;\n\t\t\t\t\tcase DT_VERDEF: removed_name = \"DT_VERDEF\"; break;\n\t\t\t\t\tcase DT_VERDEFNUM: removed_name = \"DT_VERDEFNUM\"; break;\n#endif\n\t\t\t\t\tcase DT_RPATH: removed_name = \"DT_RPATH\"; break;\n#if __ANDROID_API__ < 24\n\t\t\t\t\tcase DT_RUNPATH: removed_name = \"DT_RUNPATH\"; break;\n#endif\n\t\t\t\t}\n\t\t\t\tif (removed_name != nullptr) {\n\t\t\t\t\tprintf(\"termux-elf-cleaner: Removing the %s dynamic section entry from '%s'\\n\", removed_name, file_name);\n\t\t\t\t\t// Tag the entry with DT_NULL and put it last:\n\t\t\t\t\tdynamic_section_entry->d_tag = DT_NULL;\n\t\t\t\t\t// Decrease j to process new entry index:\n\t\t\t\t\tstd::swap(dynamic_section[j--], dynamic_section[last_nonnull_entry_idx--]);\n\t\t\t\t} else if (dynamic_section_entry->d_tag == DT_FLAGS_1) {\n\t\t\t\t\t// Remove unsupported DF_1_* flags to avoid linker warnings.\n\t\t\t\t\tdecltype(dynamic_section_entry->d_un.d_val) orig_d_val =\n\t\t\t\t\t\tdynamic_section_entry->d_un.d_val;\n\t\t\t\t\tdecltype(dynamic_section_entry->d_un.d_val) new_d_val =\n\t\t\t\t\t\t(orig_d_val & SUPPORTED_DT_FLAGS_1);\n\t\t\t\t\tif (new_d_val != orig_d_val) {\n\t\t\t\t\t\tprintf(\"termux-elf-cleaner: Replacing unsupported DF_1_* flags %llu with %llu in '%s'\\n\",\n\t\t\t\t\t\t       (unsigned long long) orig_d_val,\n\t\t\t\t\t\t       (unsigned long long) new_d_val,\n\t\t\t\t\t\t       file_name);\n\t\t\t\t\t\tdynamic_section_entry->d_un.d_val = new_d_val;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#if __ANDROID_API__ < 23\n\t\telse if (section_header_entry->sh_type == SHT_GNU_verdef ||\n\t\t\t   section_header_entry->sh_type == SHT_GNU_verneed ||\n\t\t\t   section_header_entry->sh_type == SHT_GNU_versym) {\n\t\t\tprintf(\"termux-elf-cleaner: Removing version section from '%s'\\n\", file_name);\n\t\t\tsection_header_entry->sh_type = SHT_NULL;\n\t\t}\n#endif\n\t}\n\treturn true;\n}\n\n\nint main(int argc, char const** argv)\n{\n\tif (argc < 2 || (argc == 2 && strcmp(argv[1], \"-h\")==0)) {\n\t\tfprintf(stderr, \"usage: %s <filenames>\\n\", argv[0]);\n\t\tfprintf(stderr, \"\\nProcesses ELF files to remove unsupported section types\\n\"\n\t\t\t\t\"and dynamic section entries which the Android linker (API %d)\\nwarns about.\\n\",\n\t\t\t\t__ANDROID_API__);\n\t\treturn 1;\n\t}\n\n\tfor (int i = 1; i < argc; i++) {\n\t\tchar const* file_name = argv[i];\n\t\tint fd = open(file_name, O_RDWR);\n\t\tif (fd < 0) {\n\t\t\tchar* error_message;\n\t\t\tif (asprintf(&error_message, \"open(\\\"%s\\\")\", file_name) == -1) error_message = (char*) \"open()\";\n\t\t\tperror(error_message);\n\t\t\treturn 1;\n\t\t}\n\n\t\tstruct stat st;\n\t\tif (fstat(fd, &st) < 0) { perror(\"fstat()\"); return 1; }\n\n\t\tif (st.st_size < (long long) sizeof(Elf32_Ehdr)) {\n\t\t\tclose(fd);\n\t\t\tcontinue;\n\t\t}\n\n\t\tvoid* mem = mmap(0, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n\t\tif (mem == MAP_FAILED) { perror(\"mmap()\"); return 1; }\n\n\t\tuint8_t* bytes = reinterpret_cast<uint8_t*>(mem);\n\t\tif (!(bytes[0] == 0x7F && bytes[1] == 'E' && bytes[2] == 'L' && bytes[3] == 'F')) {\n\t\t\t// Not the ELF magic number.\n\t\t\tmunmap(mem, st.st_size);\n\t\t\tclose(fd);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (bytes[/*EI_DATA*/5] != 1) {\n\t\t\tfprintf(stderr, \"termux-elf-cleaner: Not little endianness in '%s'\\n\", file_name);\n\t\t\tmunmap(mem, st.st_size);\n\t\t\tclose(fd);\n\t\t\tcontinue;\n\t\t}\n\n\t\tuint8_t const bit_value = bytes[/*EI_CLASS*/4];\n\t\tif (bit_value == 1) {\n\t\t\tif (!process_elf<Elf32_Ehdr, Elf32_Shdr, Elf32_Dyn>(bytes, st.st_size, file_name)) return 1;\n\t\t} else if (bit_value == 2) {\n\t\t\tif (!process_elf<Elf64_Ehdr, Elf64_Shdr, Elf64_Dyn>(bytes, st.st_size, file_name)) return 1;\n\t\t} else {\n\t\t\tprintf(\"termux-elf-cleaner: Incorrect bit value %d in '%s'\\n\", bit_value, file_name);\n\t\t\treturn 1;\n\t\t}\n\n\t\tif (msync(mem, st.st_size, MS_SYNC) < 0) { perror(\"msync()\"); return 1; }\n\n\t\tmunmap(mem, st.st_size);\n\t\tclose(fd);\n\t}\n\treturn 0;\n}\n"
  },
  {
    "path": "installer/updater/Makefile",
    "content": "CC = clang\nCXX = clang++\n\nPHONELIBS = ../../phonelibs\n\nWARN_FLAGS = -Werror=implicit-function-declaration \\\n             -Werror=incompatible-pointer-types \\\n             -Werror=int-conversion \\\n             -Werror=return-type \\\n             -Werror=format-extra-args\n\nCFLAGS = -std=gnu11 -g -fPIC -O2 $(WARN_FLAGS)\nCXXFLAGS = -std=c++1z -g -fPIC -O2 $(WARN_FLAGS)\n\nCURL_FLAGS = -I$(PHONELIBS)/curl/include\nCURL_LIBS = $(PHONELIBS)/curl/lib/libcurl.a \\\n            $(PHONELIBS)/zlib/lib/libz.a\n\nBORINGSSL_FLAGS = -I$(PHONELIBS)/boringssl/include\nBORINGSSL_LIBS = $(PHONELIBS)/boringssl/lib/libssl_static.a \\\n                 $(PHONELIBS)/boringssl/lib/libcrypto_static.a \\\n\nNANOVG_FLAGS = -I$(PHONELIBS)/nanovg\n\nJSON11_FLAGS = -I$(PHONELIBS)/json11\n\nOPENGL_LIBS = -lGLESv3\n\nFRAMEBUFFER_LIBS = -lutils -lgui -lEGL\n\n.PHONY: all\nall: updater\n\nOBJS = opensans_regular.ttf.o \\\n\t\t\t opensans_semibold.ttf.o \\\n\t\t\t opensans_bold.ttf.o \\\n       ../../selfdrive/common/util.o \\\n       ../../selfdrive/common/touch.o \\\n       ../../selfdrive/common/framebuffer.o \\\n       $(PHONELIBS)/json11/json11.o \\\n       $(PHONELIBS)/nanovg/nanovg.o\n\nDEPS := $(OBJS:.o=.d)\n\nupdater: updater.o $(OBJS)\n\t@echo \"[ LINK ] $@\"\n\t$(CXX) $(CPPFLAGS) -fPIC -o 'updater' $^ \\\n    $(FRAMEBUFFER_LIBS) \\\n    $(CURL_LIBS) \\\n    $(BORINGSSL_LIBS) \\\n    -L/system/vendor/lib64 \\\n    $(OPENGL_LIBS) \\\n    -lcutils -lm -llog\n\tstrip updater\n\nopensans_regular.ttf.o: ../../selfdrive/assets/fonts/opensans_regular.ttf\n\t@echo \"[ bin2o ] $@\"\n\tcd '$(dir $<)' && ld -r -b binary '$(notdir $<)' -o '$(abspath $@)'\n\nopensans_bold.ttf.o: ../../selfdrive/assets/fonts/opensans_bold.ttf\n\t@echo \"[ bin2o ] $@\"\n\tcd '$(dir $<)' && ld -r -b binary '$(notdir $<)' -o '$(abspath $@)'\n\nopensans_semibold.ttf.o: ../../selfdrive/assets/fonts/opensans_semibold.ttf\n\t@echo \"[ bin2o ] $@\"\n\tcd '$(dir $<)' && ld -r -b binary '$(notdir $<)' -o '$(abspath $@)'\n\n%.o: %.c\n\tmkdir -p $(@D)\n\t@echo \"[ CC ] $@\"\n\t$(CC) $(CPPFLAGS) $(CFLAGS) \\\n          -I../.. \\\n          -I$(PHONELIBS)/android_frameworks_native/include \\\n          -I$(PHONELIBS)/android_system_core/include \\\n          -I$(PHONELIBS)/android_hardware_libhardware/include \\\n          $(NANOVG_FLAGS) \\\n          -c -o '$@' '$<'\n\n%.o: %.cc\n\tmkdir -p $(@D)\n\t@echo \"[ CXX ] $@\"\n\t$(CXX) $(CPPFLAGS) $(CXXFLAGS) \\\n           -I../../selfdrive \\\n           -I../../ \\\n           -I$(PHONELIBS)/android_frameworks_native/include \\\n           -I$(PHONELIBS)/android_system_core/include \\\n           -I$(PHONELIBS)/android_hardware_libhardware/include \\\n           $(NANOVG_FLAGS) \\\n           $(JSON11_FLAGS) \\\n           $(CURL_FLAGS) \\\n           $(BORINGSSL_FLAGS) \\\n           -c -o '$@' '$<'\n\n\n.PHONY: clean\nclean:\n\trm -f $(OBJS) $(DEPS)\n\n-include $(DEPS)\n"
  },
  {
    "path": "installer/updater/oneplus.json",
    "content": "{\n  \"ota_url\": \"https://commadist.azureedge.net/neosupdate/ota-signed-5dc2575d713977666a8e14ae1b43a04d7f63123934c80fa10751d949a107653e.zip\",\n  \"ota_hash\": \"5dc2575d713977666a8e14ae1b43a04d7f63123934c80fa10751d949a107653e\",\n  \"recovery_url\": \"https://commadist.azureedge.net/neosupdate/recovery-db31ffe79dfd60be966fba6d1525a5081a920062b883644dc8f5734bcc6806bb.img\",\n  \"recovery_len\": 15926572,\n  \"recovery_hash\": \"db31ffe79dfd60be966fba6d1525a5081a920062b883644dc8f5734bcc6806bb\"\n}\n"
  },
  {
    "path": "installer/updater/update.json",
    "content": "{\n  \"ota_url\": \"https://commadist.azureedge.net/neosupdate/ota-signed-5dc2575d713977666a8e14ae1b43a04d7f63123934c80fa10751d949a107653e.zip\",\n  \"ota_hash\": \"5dc2575d713977666a8e14ae1b43a04d7f63123934c80fa10751d949a107653e\",\n  \"recovery_url\": \"https://commadist.azureedge.net/neosupdate/recovery-f01a55c9ba52ca57668d1684c6bf4118efd31916b04f8c1fcd8495013d3677eb.img\",\n  \"recovery_len\": 15222060,\n  \"recovery_hash\": \"f01a55c9ba52ca57668d1684c6bf4118efd31916b04f8c1fcd8495013d3677eb\"\n}\n"
  },
  {
    "path": "jetson/env_installer.sh",
    "content": "#!/bin/bash -e\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\n#####################################################################\n# Configuration:\n# * Use IMX 477 Arducam.\n# * Minimum of 32GB of U3 micro sdcard.\n# * Work on Nvidia Jetson Xavier NX only.\n# * Use Jetpack 4.6.\n# * setup your username / password as: comma / comma\n# * setup your host name as: tici\n# * change your camera settings in /opt/nvidia/jetson-io/jetson-io.py\n#####################################################################\n\nJETSON_ARCH=\"7.2\"\nPYENV_PYTHON_VERSION=\"3.8.10\"\nOPENPCV_VERSION=\"4.5.0\"\nLLVM_VERSION=\"12.0.1\"\nLLVM_INSTALL_FOLDER=\"llvm-12\"\nPOCL_VERSION=\"release_1_8\"\nUSERNAME=\"comma\"\n\nWORKSPACE=\"workspace\"\n###########################################################################\n############################### BASE SYSTEM ###############################\n###########################################################################\n\n# Nopasswd sudo\necho \"${USERNAME} ALL=(ALL) NOPASSWD:ALL\" | (sudo su -c 'EDITOR=\"tee -a\" visudo -f /etc/sudoers')\n\n# setup /bin/sh symlink\nsudo ln -sf /bin/bash /bin/sh\n\n# Disable automatic ondemand switching from ubuntu (cpu auto scaling)\nsudo systemctl disable ondemand\n\n# jetpack 4.6 has mode 8\nsudo nvpmodel -m 8\n\n# use performance governor\nsudo echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor\n\n# throttling prevention\nsudo sh -c 'echo 7000 > /sys/devices/c250000.i2c/i2c-7/7-0040/iio:device0/crit_current_limit_0'\n\n# allow max available CPU freq\nsudo sh -c 'for i in /sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq; do echo 1907200 > $i; done'\n\n# reduce reboot time (when a running job is stall)\nsudo sed -i -e 's/#DefaultTimeoutStopSec=90s/DefaultTimeoutStopSec=1s/g' /etc/systemd/system.conf\n\n#allow user to access USB\nsudo echo \"SUBSYSTEM==\\\"usb\\\", MODE=\\\"0666\\\", GROUP=\\\"users\\\"\" > $HOME/openpilot.rules\nsudo echo \"SUBSYSTEM==\\\"usb_device\\\", MODE=\\\"0666\\\", GROUP=\\\"users\\\"\" >> $HOME/openpilot.rules\nsudo mv $HOME/openpilot.rules /etc/udev/rules.d\nsudo chmod 644 /etc/udev/rules.d/openpilot.rules\nsudo chown root /etc/udev/rules.d/openpilot.rules\nsudo chgrp root /etc/udev/rules.d/openpilot.rules\n\n# Disable all useless systemctl services, if any, from agnos\nsudo systemctl mask apt-daily-upgrade.service\nsudo systemctl mask apt-daily.service\nsudo systemctl mask apt-daily-upgrade.timer\nsudo systemctl mask apt-daily.timer\nsudo systemctl disable nvpmodel.service\nsudo systemctl mask sys-devices-3100000.serial-tty-ttyTHS0.device\nsudo systemctl mask sys-devices-3110000.serial-tty-ttyTHS1.device\nsudo systemctl mask sys-devices-3110000.serial-tty-ttyTHS1.device\nsudo systemctl mask sys-devices-3140000.serial-tty-ttyTHS4.device\nsudo systemctl mask sys-devices-platform-serial8250-tty-ttyS0.device\nsudo systemctl mask sys-devices-platform-serial8250-tty-ttyS1.device\nsudo systemctl mask sys-devices-platform-serial8250-tty-ttyS2.device\nsudo systemctl mask sys-devices-platform-serial8250-tty-ttyS3.device\nsudo systemctl mask sys-kernel-debug.mount\nsudo systemctl mask motd-news.timer\nsudo systemctl mask remote-fs.target\nsudo systemctl disable nvzramconfig\nsudo systemctl mask plymouth-quit-wait.service # splash screen\nsudo systemctl mask plymouth-read-write.service # splash screen\nsudo systemctl mask alsa-restore.service # we dont have speakers, so no need alsa\nsudo systemctl disable nvphs.service\nsudo systemctl mask getty.target\nsudo systemctl disable nv_update_verifier.service\nsudo systemctl disable nvgetty.service\nsudo systemctl mask networkd-dispatcher.service\nsudo systemctl mask speech-dispatcher.service\nsudo systemctl disable nv-l4t-usb-device-mode.service\n\n# setup UI packages\nsudo apt update\nsudo apt purge -y gdm3 lightdm\nsudo apt install -y --no-install-recommends apt-utils lxdm lxde unclutter\n\n# install packages in ubuntu_setup.sh\n# without clang and qt, we need them from focal release (newer)\nsudo apt-get install -y --no-install-recommends \\\n    autoconf \\\n    build-essential \\\n    bzip2 \\\n    capnproto \\\n    cppcheck \\\n    libcapnp-dev \\\n    cmake \\\n    curl \\\n    ffmpeg \\\n    git \\\n    libavformat-dev libavcodec-dev libavdevice-dev libavutil-dev libswscale-dev libavresample-dev libavfilter-dev \\\n    libarchive-dev \\\n    libbz2-dev \\\n    libcurl4-openssl-dev \\\n    libeigen3-dev \\\n    libffi-dev \\\n    libglew-dev \\\n    libgles2-mesa-dev \\\n    libglfw3-dev \\\n    libglib2.0-0 \\\n    liblzma-dev \\\n    libomp-dev \\\n    libopencv-dev \\\n    libpng16-16 \\\n    libssl-dev \\\n    libstdc++-arm-none-eabi-newlib \\\n    libsqlite3-dev \\\n    libtool \\\n    libusb-1.0-0-dev \\\n    libzmq3-dev \\\n    libsdl-image1.2-dev libsdl-mixer1.2-dev libsdl-ttf2.0-dev libsmpeg-dev \\\n    libsdl1.2-dev  libportmidi-dev libswscale-dev libavformat-dev libavcodec-dev libfreetype6-dev \\\n    libsystemd-dev \\\n    locales \\\n    ocl-icd-libopencl1 \\\n    ocl-icd-opencl-dev \\\n    opencl-headers \\\n    python-dev \\\n    python3-pip \\\n    screen \\\n    sudo \\\n    vim \\\n    wget \\\n    htop \\\n    gcc-arm-none-eabi \\\n    gir1.2-notify\n\n# clean up\nsudo apt purge -y libreoffice* thunderbird* rhythmbox* transmission* mutter* *visionworks* ubuntu-wallpapers-bionic \\\n     *theme-ubuntu* remmina* branding-ubuntu light-themes pulseaudio packagekit ibus* \\\n     deluge smplayer* onboard* snapd* vpi1* galculator xmms2* youtube-dl unity-* whoopsie* \\\n     apport apparmor rpcbind gpsd isc-dhcp-server firefox printer-driver-* evolution-data-server* \\\n     lxmusic* avahi* yelp* vlc* nfs* ntfs* python-gi samba* docker* chromium-* system-config-printer-* \\\n     geoclue* totem* gnome-* modemmanager\nsudo apt autoremove -y && sudo apt clean -y\n\n# reinstall again making sure clean up didn't delete them.\nsudo apt install -y --no-install-recommends lxdm lxde\n\n# install packages from focal\nsudo sed -i -e 's#bionic#focal#g' /etc/apt/sources.list\nsudo apt update\nsudo apt install -y tmux nano\nsudo apt install -y --no-install-recommends \\\n\tclang \\\n\tqt5-default \\\n\tqtmultimedia5-dev \\\n\tqtwebengine5-dev \\\n  qtdeclarative5-dev \\\n\tqtchooser \\\n\tlibqt5x11extras5-dev \\\n  qtlocation5-dev \\\n  qtpositioning5-dev \\\n  libqt5sql5-sqlite \\\n  libqt5svg5-dev \\\n  libqt5opengl5-dev \\\n\tccache \\\n\tqml-module-qtquick2 \\\n\tlibreadline-dev\n\n# libqt5opengl5-dev is for mapbox\n\nsudo sed -i -e 's#focal#bionic#g' /etc/apt/sources.list\n\n# clean up again\nsudo apt update\nsudo apt purge -y mysql-common p7zip* ppp* kerneloops *gvfs*\nsudo apt autoremove -y\n\n# add missing wifi manager\nsudo apt install -y network-manager-gnome\n\n# delete sample files\nsudo rm -rf /usr/local/cuda/samples \\\n    /usr/src/cudnn_samples_* \\\n    /usr/src/tensorrt/data \\\n    /usr/src/tensorrt/samples \\\n    /usr/share/visionworks* ~/VisionWorks-SFM*Samples \\\n    /opt/nvidia/deepstream/deepstream*/samples\n\n#add user to the input device so it can read mouse\nsudo usermod -aG input ${USERNAME}\n\n# common folders\nsudo mkdir -p /data/ /data/params/d/ /data/media/0/ /persist/ /data/log /data/media/0/realdata/ /data/media/0/fakedata/\n\n# dp will recognize it as jetson\nsudo touch /JETSON\n\n# allow ssh in root because we will give openpilot full root access.\nsudo sed -i -e 's/#PermitRootLogin prohibit-password/PermitRootLogin yes/g' /etc/ssh/sshd_config\nsudo sed -i -e 's/#PasswordAuthentication yes/PasswordAuthentication yes/g' /etc/ssh/sshd_config\nsudo sed -i -e 's/#KerberosAuthentication no/KerberosAuthentication no/g' /etc/ssh/sshd_config\nsudo sed -i -e 's/#GSSAPIAuthentication no/GSSAPIAuthentication no/g' /etc/ssh/sshd_config\nsudo sed -i -e 's/#UseDNS no/UseDNS no/g' /etc/ssh/sshd_config\nsudo sed -i -e 's/#UsePAM yes/UsePAM no/g' /etc/ssh/sshd_config\n\n# install jtop\nsudo pip3 install setuptools\n# breaks after completion, remove for now. \n#sudo -H pip3 install -U jetson-stats\n\n###########################################################################\n############################ OPENPILOT RELATED ############################\n###########################################################################\n\n# install git lfs\nif ! command -v \"git-lfs\" > /dev/null 2>&1; then\n  curl -s https://packagecloud.io/install/repositories/github/git-lfs/script.deb.sh | sudo bash\n  sudo apt-get install git-lfs\nfi\n\n# install pyenv\nif ! command -v \"pyenv\" > /dev/null 2>&1; then\n  curl -L https://github.com/pyenv/pyenv-installer/raw/master/bin/pyenv-installer | bash\nfi\n\nexport PYENV_ROOT=\"$HOME/.pyenv\"\nexport PATH=\"$PYENV_ROOT/bin:$PATH\"\neval \"$(pyenv init --path)\"\n# install bashrc\nsource ~/.bashrc\nif [ -z \"$OPENPILOT_ENV\" ]; then\n  echo \"export PYENV_ROOT=\\\"$HOME/.pyenv\\\"\" >> ~/.bashrc\n  echo \"export PATH=\\\"$PYENV_ROOT/bin:$PATH\\\"\" >> ~/.bashrc\n  echo \"eval \\\"$(pyenv init --path)\\\"\" >> ~/.bashrc\n  echo \"source /data/openpilot/jetson/openpilot_env.sh\" >> ~/.bashrc\n  source $HOME/openpilot/jetson/openpilot_env.sh\n  source ~/.bashrc\n  echo \"added openpilot_env to bashrc\"\nfi\n\n\n# install python\npyenv install -s ${PYENV_PYTHON_VERSION}\npyenv global ${PYENV_PYTHON_VERSION}\npyenv rehash\neval \"$(pyenv init -)\"\n\n# **** in python env ****\npip install --upgrade pip==20.2.4\npip install pipenv==2020.8.13\n\npip install setuptools\npip install wheel\npip install pkgconfig\n\n# packages\npip install atomicwrites\npip install casadi\npip install cffi\npip install crcmod\npip install future-fstrings # for acados\npip install hexdump # for dump.py\npip install libusb1\npip install numpy\npip install psutil\npip install pycapnp==1.1.0\npip install cryptography\npip install pyzmq\npip install requests\npip install setproctitle\npip install smbus2\npip install sympy\npip install tqdm\npip install cython\npip install scons\npip install pycryptodome\npip install jinja2\npip install pyjwt\npip install pyserial\npip install sentry-sdk\n\n#pip install setuptools-cythonize\n#pip install logentries\n# mapd\npip install scipy\npip install overpy\n\n# openpilot tmux\necho \"unbind C-b\" > $HOME/.tmux.conf\necho \"set -g prefix \\`\" >> $HOME/.tmux.conf\necho \"bind-key \\` last-window\" >> $HOME/.tmux.conf\necho \"bind-key e send-prefix\" >> $HOME/.tmux.conf\necho \"bind-key S command-prompt -p 'Save log to file:' -I '/tmp/openpilot_log' 'capture-pane -S-7200; save-buffer %1; delete-buffer'\" >> $HOME/.tmux.conf\necho \"set -g status-position bottom\" >> $HOME/.tmux.conf\necho \"set -g status-style bg=colour234,fg=colour137,dim\" >> $HOME/.tmux.conf\necho \"set -g status-left ''\" >> $HOME/.tmux.conf\necho \"set -g status-right '#[fg=colour233,bg=colour241,bold] %d/%m #[fg=colour233,bg=colour245,bold] %H:%M:%S '\" >> $HOME/.tmux.conf\necho \"set -g status-right-length 50\" >> $HOME/.tmux.conf\necho \"set -g status-left-length 20\" >> $HOME/.tmux.conf\necho \"set -g history-limit 7200\" >> $HOME/.tmux.conf\necho \"setw -g window-status-current-style fg=colour81,bg=colour238,bold\" >> $HOME/.tmux.conf\necho \"setw -g window-status-current-format ' #I#[fg=colour250]:#[fg=colour255]#W#[fg=colour50]#F '\" >> $HOME/.tmux.conf\necho \"setw -g window-status-style fg=colour138,bg=colour235\" >> $HOME/.tmux.conf\necho \"setw -g window-status-format ' #I#[fg=colour237]:#[fg=colour250]#W#[fg=colour244]#F '\" >> $HOME/.tmux.conf\necho \"setw -g window-status-bell-style fg=colour255,bg=colour1,bold\" >> $HOME/.tmux.conf\n\n# move to /data/openpilot\ncd /data\nmv /home/${USERNAME}/openpilot /data/\n\n# make sure everything goes to the right display\necho \"export DISPLAY=:0.0\" >> $HOME/.bashrc\n\n# start openpilot correctly\necho \"export USE_MIPI=\\\"1\\\"\" >> $HOME/.bashrc\necho \"export NOSENSOR=\\\"1\\\"\" >> $HOME/.bashrc\necho \"export PASSIVE=\\\"0\\\"\" >> $HOME/.bashrc\n\n# start from /data/openpilot\necho \"[ -d \\\"/data/openpilot\\\" ] && cd /data/openpilot\" >> $HOME/.bashrc\n\n###########################################################################\n############################ DOWNLOAD PACKAGES ############################\n###########################################################################\nmkdir -p /data/${WORKSPACE}/\ncd /data/${WORKSPACE}/\nwget https://github.com/llvm/llvm-project/releases/download/llvmorg-${LLVM_VERSION}/clang+llvm-${LLVM_VERSION}-aarch64-linux-gnu.tar.xz &\nwget https://nvidia.box.com/shared/static/gjqofg7rkg97z3gc8jeyup6t8n9j8xjw.whl -O onnxruntime_gpu-1.8.0-cp38-cp38-linux_aarch64.whl &\ncurl -L https://github.com/opencv/opencv/archive/${OPENPCV_VERSION}.zip -o opencv-${OPENPCV_VERSION}.zip &\ncurl -L https://github.com/opencv/opencv_contrib/archive/${OPENPCV_VERSION}.zip -o opencv_contrib-${OPENPCV_VERSION}.zip &\nwait\n\n###########################################################################\n############################### ONNX RUNTIME ##############################\n###########################################################################\ncd /data/${WORKSPACE}/\npip install onnxruntime_gpu-1.8.0-cp38-cp38-linux_aarch64.whl\n\n###########################################################################\n################################## LLVM 12 ################################\n###########################################################################\n# for POCL\ncd /data/${WORKSPACE}/\ntar -xvf clang+llvm-${LLVM_VERSION}-aarch64-linux-gnu.tar.xz\nsudo mkdir -p /usr/lib/${LLVM_INSTALL_FOLDER}/\nsudo mv clang+llvm-${LLVM_VERSION}-aarch64-linux-gnu/* /usr/lib/${LLVM_INSTALL_FOLDER}/\n\n###########################################################################\n################################### POCL ##################################\n###########################################################################\ncd /data/${WORKSPACE}/\ngit clone --single-branch --branch ${POCL_VERSION} https://github.com/pocl/pocl.git\ncd /data/${WORKSPACE}/pocl\nmkdir build\ncd /data/${WORKSPACE}/pocl/build/\ncmake -DCMAKE_BUILD_TYPE=Release -DWITH_LLVM_CONFIG=/usr/lib/${LLVM_INSTALL_FOLDER}/bin/llvm-config -DENABLE_CUDA=ON -DSTATIC_LLVM=ON ..\nmake -j $(nproc)\nsudo make install\nmkdir -p /etc/OpenCL/vendors/\necho \"/usr/local/lib/libpocl.so\" > /etc/OpenCL/vendors/pocl.icd\n\n###########################################################################\n################################## OPENCV #################################\n###########################################################################\n# Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.\n#\n# NVIDIA Corporation and its licensors retain all intellectual property\n# and proprietary rights in and to this software, related documentation\n# and any modifications thereto.  Any use, reproduction, disclosure or\n# distribution of this software and related documentation without an express\n# license agreement from NVIDIA Corporation is strictly prohibited.\n\n# jetpack opencv doesn't have cuda that's why we compile manually\n# check jtop for more info.\ncd /data/${WORKSPACE}/\n\necho \"** Remove other OpenCV first\"\nsudo sudo apt-get purge -y *libopencv*\n\necho \"** Install requirement\"\nsudo apt-get update\nsudo apt-get install -y libgstreamer1.0-dev libgstreamer-plugins-base1.0-dev\nsudo apt-get install -y libtbb2 libtbb-dev libjpeg-dev libpng-dev libtiff-dev libdc1394-22-dev\nsudo apt-get install -y libv4l-dev v4l-utils qv4l2 v4l2ucp\n\nunzip opencv-${OPENPCV_VERSION}.zip\nunzip opencv_contrib-${OPENPCV_VERSION}.zip\ncd opencv-${OPENPCV_VERSION}/\n\necho \"** Building...\"\nmkdir release\ncd release/\ncmake -D WITH_CUDA=ON \\\n        -D WITH_CUDNN=OFF \\\n        -D CUDA_ARCH_BIN=\"${JETSON_ARCH}\" \\\n        -D CUDA_ARCH_PTX=\"\" \\\n        -D OPENCV_GENERATE_PKGCONFIG=ON \\\n        -D OPENCV_EXTRA_MODULES_PATH=../../opencv_contrib-${OPENPCV_VERSION}/modules \\\n        -D WITH_GSTREAMER=ON \\\n        -D WITH_LIBV4L=ON \\\n        -D BUILD_opencv_python2=OFF \\\n        -D BUILD_opencv_python3=ON \\\n        -D BUILD_TESTS=OFF \\\n        -D BUILD_PERF_TESTS=OFF \\\n        -D BUILD_EXAMPLES=OFF \\\n        -D CMAKE_BUILD_TYPE=RELEASE \\\n        -D CMAKE_INSTALL_PREFIX=/usr/local \\\n        -D WITH_GTK=OFF \\\n        -D ENABLE_FAST_MATH=ON \\\n        -D BUILD_opencv_java=OFF \\\n        -D WITH_QT=OFF \\\n        -D INSTALL_PYTHON_EXAMPLES=OFF \\\n        -D INSTALL_C_EXAMPLES=OFF \\\n        -D WITH_CUFFT=ON \\\n        -D WITH_CUBLAS=ON \\\n        -D WITH_1394=OFF \\\n        -D WITH_ANDROID_MEDIANDK=OFF \\\n        -D BUILD_JAVA=OFF \\\n        -D BUILD_FAT_JAVA_LIB=OFF \\\n        -D BUILD_opencv_python2=OFF \\\n        ..\nmake -j$(nproc)\nsudo make install\n###########################################################################\n################################## FINAL ##################################\n###########################################################################\ncd /data && rm -fr /data/${WORKSPACE}/\n\n# creates the necessary links and cache\nsudo ldconfig -v\n\n# delay restart\nsudo shutdown -r 1\n\n# clean up once last time\nsudo apt autoremove -y && sudo apt clean -y\n\n# lxdm give comma autologin\nsudo sed -i -e \"s/# autologin=dgod/autologin=${USERNAME}/g\" /etc/lxdm/default.conf\n\n# remove screensaver\nsudo sed -i -e 's/@xscreensaver -no-splash//g' /etc/xdg/lxsession/LXDE/autostart\n\n# auto start openpilot\nsudo sh -c 'echo \"@lxterminal --command tmux new-session -s '${USERNAME}' -d /data/openpilot/jetson/launcher.sh\" >> /etc/xdg/lxsession/LXDE/autostart'\n\n# comma as root\nUSERNAME=\"comma\"\nsudo sed -i -e \"s#${USERNAME}:x:1000:1000:${USERNAME}#${USERNAME}:x:0:0:${USERNAME}#g\" /etc/passwd\n"
  },
  {
    "path": "jetson/launcher.sh",
    "content": "#!/bin/bash -e\ncd /data/openpilot && bash -i launch_chffrplus.sh"
  },
  {
    "path": "jetson/openpilot_env.sh",
    "content": "if [ -z \"$OPENPILOT_ENV\" ]; then\n  export PYTHONPATH=\"/data/openpilot:$PYTHONPATH\"\n\n  unamestr=`uname`\n  if [[ \"$unamestr\" == 'Linux' ]]; then\n    export PATH=\"$HOME/.pyenv/bin:$PATH\"\n\n    # Pyenv suggests we place the below two lines in .profile before we source\n    # .bashrc, but there is no simple way to guarantee we do this correctly\n    # programmatically across heterogeneous systems. For end-user convenience,\n    # we add the lines here as a workaround.\n    # https://github.com/pyenv/pyenv/issues/1906\n    export PYENV_ROOT=\"$HOME/.pyenv\"\n    eval \"$(pyenv init --path)\"\n\n    eval \"$(pyenv virtualenv-init -)\"\n  elif [[ \"$unamestr\" == 'Darwin' ]]; then\n    # msgq doesn't work on mac\n    export ZMQ=1\n    export OBJC_DISABLE_INITIALIZE_FORK_SAFETY=YES\n  fi\n  eval \"$(pyenv init -)\"\n\n  export OPENPILOT_ENV=1\nfi\n"
  },
  {
    "path": "jetson/release.py",
    "content": "#!/usr/bin/env python3\n'''\nThis script is used to clean up files prior publish to xnxpilot.\nRun this in jetson device to clean up.\n\nDo not run this unless you know what you are doing.\n-- Rick Lan\n'''\n\nimport os\nimport sys\nimport subprocess\n\nPATH = \"/data/openpilot\"\n\nVERSION = \"0.8.9\"\n\nif not os.path.exists(\"/JETSON\"):\n  sys.exit(\"Please run this in Jetson device.\")\n\n# make sure we dont use prebuilt\nos.system(\"echo -n 0 > /data/params/d/dp_prebuilt\")\nos.system(\"rm -fr %s/prebuilt\" % PATH)\n\n# model clean up\nos.system(\"rm -fr %s/selfdrive/models/*.dlc\" % PATH)\n\n# ui clean up\nsubprocess.call(['sed -i -e \"s#selfdrive/ui/_ui##g \" ' + ('%s/.gitignore' % PATH)], shell=True)\nsubprocess.call(['sed -i -e \"s#selfdrive/ui/_soundd##g \" ' + ('%s/.gitignore' % PATH)], shell=True)\nos.system(\"rm -fr %s/selfdrive/ui/*_aarch64\" % PATH)\nos.system(\"rm -fr %s/selfdrive/ui/*_larch64\" % PATH)\nos.system(\"rm -fr %s/selfdrive/ui/*_c3\" % PATH)\nos.system(\"rm -fr %s/selfdrive/ui/qt/*_aarch64\" % PATH)\nos.system(\"rm -fr %s/selfdrive/ui/qt/*_larch64\" % PATH)\nos.system(\"rm -fr %s/selfdrive/ui/qt/*_c3\" % PATH)\n\nos.system(\"rm -fr %s/selfdrive/ui/SConscript\" % PATH)\nos.system(\"rm -fr %s/selfdrive/ui/.gitignore\" % PATH)\nos.system(\"find %s/selfdrive/ui/ -name '*.a' -delete\" % PATH)\nos.system(\"find %s/selfdrive/ui/ -name '*.o' -delete\" % PATH)\nos.system(\"find %s/selfdrive/ui/ -name '*.h' -delete\" % PATH)\nos.system(\"find %s/selfdrive/ui/ -name '*.cc' -delete\" % PATH)\n\n# delete panda\nos.system(\"rm -fr %s/panda/board/obj/panda.bin\" % PATH)\nos.system(\"rm -fr %s/panda/board/obj/panda.bin.signed\" % PATH)\n\n# misc\nos.system(\"rm -fr %s/selfdrive/golden\" % PATH)\nos.system(\"rm -fr %s/installer/updater/updater.cc\" % PATH)\nos.system(\"rm -fr %s/phonelibs/curl/\" % PATH)\nos.system(\"rm -fr %s/phonelibs/boringssl/\" % PATH)\nos.system(\"rm -fr %s/phonelibs/mapbox-gl-native-qt/aarch64\" % PATH)\nos.system(\"rm -fr %s/phonelibs/snpe/aarch64*\" % PATH)\n\n\n# change version string\nsubprocess.call([\"sed -i -e 's/.*/#define COMMA_VERSION \\\"\" + (\"%s-xnxpilot\" % VERSION) + \"\\\"/g' \" + ('%s/selfdrive/common/version.h' % PATH)], shell=True)\n\n"
  },
  {
    "path": "launch_chffrplus.sh",
    "content": "#!/usr/bin/bash\n\nif [ -z \"$BASEDIR\" ]; then\n  BASEDIR=\"/data/openpilot\"\nfi\n\nsource \"$BASEDIR/launch_env.sh\"\n\nDIR=\"$( cd \"$( dirname \"${BASH_SOURCE[0]}\" )\" >/dev/null && pwd )\"\n\nfunction two_init {\n  python /data/openpilot/scripts/installers/language_installer.py\n  python /data/openpilot/scripts/installers/sshkey_installer.py\n  python /data/openpilot/scripts/installers/font_installer.py\n  mount -o remount,rw /system\n  if [ ! -f /ONEPLUS ] && ! $(grep -q \"letv\" /proc/cmdline); then\n    sed -i -e 's#/dev/input/event1#/dev/input/event2#g' ~/.bash_profile\n    touch /ONEPLUS\n  else\n    if [ ! -f /LEECO ]; then\n      touch /LEECO\n    fi\n  fi\n  mount -o remount,r /system\n\n  # set IO scheduler\n  setprop sys.io.scheduler noop\n  for f in /sys/block/*/queue/scheduler; do\n    echo noop > $f\n  done\n\n  # *** shield cores 2-3 ***\n\n  # TODO: should we enable this?\n  # offline cores 2-3 to force recurring timers onto the other cores\n  #echo 0 > /sys/devices/system/cpu/cpu2/online\n  #echo 0 > /sys/devices/system/cpu/cpu3/online\n  #echo 1 > /sys/devices/system/cpu/cpu2/online\n  #echo 1 > /sys/devices/system/cpu/cpu3/online\n\n  # android gets two cores\n  echo 0-1 > /dev/cpuset/background/cpus\n  echo 0-1 > /dev/cpuset/system-background/cpus\n  echo 0-1 > /dev/cpuset/foreground/cpus\n  echo 0-1 > /dev/cpuset/foreground/boost/cpus\n  echo 0-1 > /dev/cpuset/android/cpus\n\n  # openpilot gets all the cores\n  echo 0-3 > /dev/cpuset/app/cpus\n\n  # mask off 2-3 from RPS and XPS - Receive/Transmit Packet Steering\n  echo 3 | tee  /sys/class/net/*/queues/*/rps_cpus\n  echo 3 | tee  /sys/class/net/*/queues/*/xps_cpus\n\n  # *** set up governors ***\n\n  # +50mW offroad, +500mW onroad for 30% more RAM bandwidth\n  echo \"performance\" > /sys/class/devfreq/soc:qcom,cpubw/governor\n  echo 1056000 > /sys/class/devfreq/soc:qcom,m4m/max_freq\n  echo \"performance\" > /sys/class/devfreq/soc:qcom,m4m/governor\n\n  # unclear if these help, but they don't seem to hurt\n  echo \"performance\" > /sys/class/devfreq/soc:qcom,memlat-cpu0/governor\n  echo \"performance\" > /sys/class/devfreq/soc:qcom,memlat-cpu2/governor\n\n  # GPU\n  echo \"performance\" > /sys/class/devfreq/b00000.qcom,kgsl-3d0/governor\n\n  # /sys/class/devfreq/soc:qcom,mincpubw is the only one left at \"powersave\"\n  # it seems to gain nothing but a wasted 500mW\n\n  # *** set up IRQ affinities ***\n\n  # Collect RIL and other possibly long-running I/O interrupts onto CPU 1\n  echo 1 > /proc/irq/78/smp_affinity_list # qcom,smd-modem (LTE radio)\n  echo 1 > /proc/irq/33/smp_affinity_list # ufshcd (flash storage)\n  echo 1 > /proc/irq/35/smp_affinity_list # wifi (wlan_pci)\n  echo 1 > /proc/irq/6/smp_affinity_list  # MDSS\n\n  # USB traffic needs realtime handling on cpu 3\n  [ -d \"/proc/irq/733\" ] && echo 3 > /proc/irq/733/smp_affinity_list\n  if [ -f /ONEPLUS ]; then\n    [ -d \"/proc/irq/736\" ] && echo 3 > /proc/irq/736/smp_affinity_list # USB for OP3T\n  fi\n\n  # GPU and camera get cpu 2\n  CAM_IRQS=\"177 178 179 180 181 182 183 184 185 186 192\"\n  for irq in $CAM_IRQS; do\n    echo 2 > /proc/irq/$irq/smp_affinity_list\n  done\n  echo 2 > /proc/irq/193/smp_affinity_list # GPU\n\n  # give GPU threads RT priority\n  for pid in $(pgrep \"kgsl\"); do\n    chrt -f -p 52 $pid\n  done\n\n  # the flippening!\n  LD_LIBRARY_PATH=\"\" content insert --uri content://settings/system --bind name:s:user_rotation --bind value:i:1\n\n  # disable bluetooth\n  service call bluetooth_manager 8\n\n  # wifi scan\n  wpa_cli IFNAME=wlan0 SCAN\n\n  # Check for NEOS update\n  if [ -f /LEECO ]; then\n    if [ $(< /VERSION) != \"$REQUIRED_NEOS_VERSION\" ]; then\n      if [ -f \"$DIR/scripts/continue.sh\" ]; then\n        cp \"$DIR/scripts/continue.sh\" \"/data/data/com.termux/files/continue.sh\"\n      fi\n\n      if [ ! -f \"$BASEDIR/prebuilt\" ]; then\n        # Clean old build products, but preserve the scons cache\n        cd $DIR\n        git clean -xdf\n        git submodule foreach --recursive git clean -xdf\n      fi\n\n      \"$DIR/installer/updater/updater\" \"file://$DIR/installer/updater/update.json\"\n    fi\n  fi\n\n  # One-time fix for a subset of OP3T with gyro orientation offsets.\n  # Remove and regenerate qcom sensor registry. Only done on OP3T mainboards.\n  # Performed exactly once. The old registry is preserved just-in-case, and\n  # doubles as a flag denoting we've already done the reset.\n  if [ -f /ONEPLUS ] && [ ! -f \"/persist/comma/op3t-sns-reg-backup\" ]; then\n    echo \"Performing OP3T sensor registry reset\"\n    mv /persist/sensors/sns.reg /persist/comma/op3t-sns-reg-backup &&\n      rm -f /persist/sensors/sensors_settings /persist/sensors/error_log /persist/sensors/gyro_sensitity_cal &&\n      echo \"restart\" > /sys/kernel/debug/msm_subsys/slpi &&\n      sleep 5  # Give Android sensor subsystem a moment to recover\n  fi\n}\n\nfunction tici_init {\n  # wait longer for weston to come up\n  if [ -f \"$BASEDIR/prebuilt\" ]; then\n    sleep 3\n  fi\n\n  # setup governors\n  sudo su -c 'echo \"performance\" > /sys/class/devfreq/soc:qcom,memlat-cpu0/governor'\n  sudo su -c 'echo \"performance\" > /sys/class/devfreq/soc:qcom,memlat-cpu4/governor'\n\n  # TODO: move this to agnos\n  # network manager config\n  nmcli connection modify --temporary lte gsm.auto-config yes\n  nmcli connection modify --temporary lte gsm.home-only yes\n  sudo rm -f /data/etc/NetworkManager/system-connections/*.nmmeta\n\n  # set success flag for current boot slot\n  sudo abctl --set_success\n\n  # Check if AGNOS update is required\n  if [ $(< /VERSION) != \"$AGNOS_VERSION\" ]; then\n    AGNOS_PY=\"$DIR/selfdrive/hardware/tici/agnos.py\"\n    MANIFEST=\"$DIR/selfdrive/hardware/tici/agnos.json\"\n    if $AGNOS_PY --verify $MANIFEST; then\n      sudo reboot\n    fi\n    $DIR/selfdrive/hardware/tici/updater $AGNOS_PY $MANIFEST\n  fi\n}\n\n# jetpack 4.6\nfunction jetson_init {\n  # jetpack 4.6 has mode 8\n  sudo nvpmodel -m 8\n\n  # use performance governor\n  sudo echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor\n\n  # run higher fan speed in case we need compilation\n  sudo echo 200 > /sys/devices/pwm-fan/target_pwm\n\n  # prevent throttling\n  echo 7000 > /sys/devices/c250000.i2c/i2c-7/7-0040/iio:device0/crit_current_limit_0\n\n  # use highest available cpu freq\n  for i in /sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq; do\n    echo 1907200 > $i;\n  done\n\n  # gpu min set to highest\n  sudo echo 1109250000 > /sys/devices/17000000.gv11b/devfreq/17000000.gv11b/min_freq\n\n  # set IO scheduler\n  for f in /sys/block/*/queue/scheduler; do\n    echo noop > $f\n  done\n\n  # give nvargus-daemon higer priority\n  for pid in $(pgrep \"nvargus-daemon\"); do\n    chrt -f -p 52 $pid\n  done\n\n  # scale 4.3\" 800x480 to 1920x1080\n  if [ \"$(xdpyinfo | awk '/dimensions/{print $2}')\" == \"800x480\" ]; then\n    xrandr --output HDMI-0 --mode 800x480 --scale 2.4x2.25\n  fi\n\n  # enable jetson mode\n  echo -n 1 > /data/params/d/dp_jetson\n\n  # disable blank screen etc.\n  xset s off\n  xset s noblank\n  xset -dpms\n\n  # hide mouse cursor\n  unclutter -idle 0 &\n}\n\nfunction launch {\n  # Remove orphaned git lock if it exists on boot\n  [ -f \"$DIR/.git/index.lock\" ] && rm -f $DIR/.git/index.lock\n\n  # Pull time from panda\n  $DIR/selfdrive/boardd/set_time.py\n\n  # Check to see if there's a valid overlay-based update available. Conditions\n  # are as follows:\n  #\n  # 1. The BASEDIR init file has to exist, with a newer modtime than anything in\n  #    the BASEDIR Git repo. This checks for local development work or the user\n  #    switching branches/forks, which should not be overwritten.\n  # 2. The FINALIZED consistent file has to exist, indicating there's an update\n  #    that completed successfully and synced to disk.\n\n  if [ -f \"${BASEDIR}/.overlay_init\" ]; then\n#    find ${BASEDIR}/.git -newer ${BASEDIR}/.overlay_init | grep -q '.' 2> /dev/null\n#    if [ $? -eq 0 ]; then\n#      echo \"${BASEDIR} has been modified, skipping overlay update installation\"\n#    else\n      if [ -f \"${STAGING_ROOT}/finalized/.overlay_consistent\" ]; then\n        if [ ! -d /data/safe_staging/old_openpilot ]; then\n          echo \"Valid overlay update found, installing\"\n          LAUNCHER_LOCATION=\"${BASH_SOURCE[0]}\"\n\n          mv $BASEDIR /data/safe_staging/old_openpilot\n          mv \"${STAGING_ROOT}/finalized\" $BASEDIR\n          cd $BASEDIR\n\n          # Partial mitigation for symlink-related filesystem corruption\n          # Ensure all files match the repo versions after update\n          git reset --hard\n          git submodule foreach --recursive git reset --hard\n\n          echo \"Restarting launch script ${LAUNCHER_LOCATION}\"\n          unset REQUIRED_NEOS_VERSION\n          unset AGNOS_VERSION\n          exec \"${LAUNCHER_LOCATION}\"\n        else\n          echo \"openpilot backup found, not updating\"\n          # TODO: restore backup? This means the updater didn't start after swapping\n        fi\n      fi\n#    fi\n  fi\n\n  # handle pythonpath\n  ln -sfn $(pwd) /data/pythonpath\n  export PYTHONPATH=\"$PWD:$PWD/pyextra\"\n\n  # dp - ignore chmod changes\n  git -C $DIR config core.fileMode false\n\n  # dp - apply custom patch\n  if [ -f \"/data/media/0/dp_patcher.py\" ]; then\n    python /data/media/0/dp_patcher.py\n  fi\n  # hardware specific init\n  if [ -f /EON ]; then\n    two_init\n  elif [ -f /TICI ]; then\n    tici_init\n  elif [ -f /JETSON ]; then\n    jetson_init\n    # make sure we have right models\n    if [ ! -f \"$DIR/models/supercombo.onnx\" ]; then\n      rm -fr $DIR/models/*.dlc\n      wget https://github.com/commaai/openpilot/raw/72a736f90e57a7d5845891ea34b17360b6f684d0/models/supercombo.onnx -O \"$DIR/models/supercombo.onnx\"\n    fi\n  fi\n\n  # write tmux scrollback to a file\n  tmux capture-pane -pq -S-1000 > /tmp/launch_log\n\n  # start manager\n  cd selfdrive/manager\n  if [ -f /EON ]; then\n    if [ ! -f \"/system/comma/usr/lib/libgfortran.so.5.0.0\" ]; then\n      mount -o remount,rw /system\n      tar -zxvf /data/openpilot/selfdrive/mapd/assets/libgfortran.tar.gz -C /system/comma/usr/lib/\n      mount -o remount,r /system\n    fi\n    if [ ! -d \"/system/comma/usr/lib/python3.8/site-packages/opspline\" ]; then\n      mount -o remount,rw /system\n      tar -zxvf /data/openpilot/selfdrive/mapd/assets/opspline.tar.gz -C /system/comma/usr/lib/python3.8/site-packages/\n      mount -o remount,r /system\n    fi\n    ./build.py && ./manager.py\n  elif [ -f /JETSON ]; then\n    ./build.py && ./manager.py\n  else\n    ./custom_dep.py && ./build.py && ./manager.py\n  fi\n  # if broken, keep on screen error\n  while true; do sleep 1; done\n}\n\nlaunch\n"
  },
  {
    "path": "launch_env.sh",
    "content": "#!/usr/bin/bash\n\nexport OMP_NUM_THREADS=1\nexport MKL_NUM_THREADS=1\nexport NUMEXPR_NUM_THREADS=1\nexport OPENBLAS_NUM_THREADS=1\nexport VECLIB_MAXIMUM_THREADS=1\n\nif [ -z \"$REQUIRED_NEOS_VERSION\" ]; then\n  export REQUIRED_NEOS_VERSION=\"18\"\nfi\n\nif [ -z \"$AGNOS_VERSION\" ]; then\n  export AGNOS_VERSION=\"1.5\"\nfi\n\nif [ -z \"$PASSIVE\" ]; then\n  export PASSIVE=\"1\"\nfi\n\nexport STAGING_ROOT=\"/data/safe_staging\"\n"
  },
  {
    "path": "launch_openpilot.sh",
    "content": "#!/usr/bin/bash\nsize=$(du -sb .git/index 2>/dev/null|awk '{print $1}')\necho $size|grep -E '^[0-9]+$' >/dev/null || size=0\nif [ $size -le 1024 ];then\n    rm .git/index 2>/dev/null\n    git reset\nfi\n\nexport PASSIVE=\"0\"\nexec ./launch_chffrplus.sh\n\n"
  },
  {
    "path": "opendbc/.gitignore",
    "content": ".mypy_cache/\n*.pyc\n*.os\n*.o\n*.tmp\n*.dylib\n.*.swp\n.DS_Store\n.sconsign.dblite\n\ncan/*.so\ncan/build/\ncan/obj/\ncan/packer_pyx.cpp\ncan/parser_pyx.cpp\ncan/packer_pyx.html\ncan/parser_pyx.html\n"
  },
  {
    "path": "opendbc/__init__.py",
    "content": "import os\nDBC_PATH = os.path.dirname(os.path.abspath(__file__))\n"
  },
  {
    "path": "opendbc/acura_ilx_2016_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"acura_ilx_2016_can.dbc starts here\";\n\n\n\nBO_ 145 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (0.02,-512) [-20|20] \"m/s2\" EON\n\nBO_ 228 STEERING_CONTROL: 5 ADAS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-3840|3840] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 316 GAS_PEDAL: 8 PCM\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ GEAR : 7|8@0+ (1,0) [0|256] \"\" EON\n SG_ GEAR_SHIFTER : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 419 GEAR \"10 = reverse, 11 = transition\";\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 419 GEAR_SHIFTER 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 780 HUD_LEAD 3 \"no_car\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/acura_ilx_2016_nidec.dbc",
    "content": "VERSION \"\"\n\n\nNS_ : \n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBS_:\n\nBU_: ADAS RADAR NEO XXX\n\n\nBO_ 768 VEHICLE_STATE: 8 ADAS\n SG_ SET_ME_XF9 : 7|8@0+ (1,0) [0|255] \"\" Vector__XXX\n SG_ VEHICLE_SPEED : 15|8@0+ (1,0) [0|255] \"kph\" Vector__XXX\n\nBO_ 769 VEHICLE_STATE2: 8 ADAS\n SG_ SET_ME_0F18510 : 7|28@0+ (1,0) [0|268435455] \"\" Vector__XXX\n SG_ SET_ME_25A0000 : 27|28@0+ (1,0) [0|268435455] \"\" Vector__XXX\n\nBO_ 1024 RADAR_DIAGNOSTIC: 8 RADAR\n SG_ RADAR_STATE : 7|8@0+ (1,0) [0|255] \"\" NEO\n\nBO_ 1040 XXX_101: 8 RADAR\n\nBO_ 1041 XXX_102: 8 RADAR\n\nBO_ 1042 XXX_103: 8 RADAR\n\nBO_ 1043 XXX_104: 8 RADAR\n\nBO_ 1044 XXX_105: 8 RADAR\n\nBO_ 1045 XXX_106: 8 RADAR\n\nBO_ 1046 XXX_107: 8 RADAR\n\nBO_ 1047 XXX_108: 8 RADAR\n\nBO_ 1056 XXX_109: 8 RADAR\n\nBO_ 1057 XXX_110: 8 RADAR\n\nBO_ 1058 XXX_111: 8 RADAR\n\nBO_ 1059 XXX_112: 8 RADAR\n\nBO_ 1060 XXX_113: 8 RADAR\n\nBO_ 1072 TRACK_0: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1073 TRACK_1: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1074 TRACK_2: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1075 TRACK_3: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1076 TRACK_4: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1077 TRACK_5: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1078 TRACK_6: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1079 TRACK_7: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1080 TRACK_8: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1081 TRACK_9: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1088 TRACK_10: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1089 TRACK_11: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1090 TRACK_12: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1091 TRACK_13: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1092 TRACK_14: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1093 TRACK_15: 8 RADAR\n SG_ LONG_DIST : 7|12@0+ (0.0625,0) [0|255.5] \"m\"  NEO\n SG_ NEW_TRACK : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LAT_DIST : 9|10@0- (0.0625,0) [0|63.5] \"m\"  NEO\n SG_ REL_SPEED : 31|12@0- (0.03125,0) [0|127.5] \"m/s\"  NEO\n\nBO_ 1279 XXX_114: 8 RADAR\n\nBO_ 1280 XXX_115: 8 RADAR\n\nBO_ 1296 XXX_116: 8 RADAR\n\nBO_ 1297 XXX_117: 8 RADAR\n\nBO_TX_BU_ 768 : NEO,ADAS;\nBO_TX_BU_ 769 : NEO,ADAS;\n\n\nCM_ SG_ 1024 RADAR_STATE \"need to find out more diagnostic values\";\nVAL_ 1024 RADAR_STATE 121 \"ok\" 110 \"faulted\" 105 \"wrong_config\";\n"
  },
  {
    "path": "opendbc/acura_rdx_2018_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"acura_rdx_2018_can.dbc starts here\";\n\n\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 392 GEARBOX: 6 XXX\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" XXX\n SG_ GEAR_SHIFTER : 27|4@0+ (1,0) [0|15] \"\" EON\n SG_ GEAR : 36|5@0+ (1,0) [0|31] \"\" EON\n\nBO_ 399 STEER_STATUS: 6 EPS\n SG_ STEER_TORQUE_SENSOR : 7|12@0- (-1,0) [-2047.5|2047.5] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 36|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 404 STEERING_CONTROL: 4 EON\n SG_ STEER_TORQUE : 7|12@0- (1,0) [-768|768] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EPS\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ PARKING_BRAKE_LIGHT : 2|1@0+ (1,0) [0|1] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 487 BRAKE_PRESSURE: 4 VSA\n SG_ BRAKE_PRESSURE1 : 7|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ BRAKE_PRESSURE2 : 9|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nCM_ SG_ 422 PARKING_BRAKE_LIGHT \"Believe this is just the dash light for the parking break\";\nVAL_ 392 GEAR_SHIFTER 0 \"S\" 1 \"P\" 2 \"R\" 4 \"N\" 8 \"D\" ;\nVAL_ 392 GEAR 26 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/acura_rdx_2020_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2020.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"acura_rdx_2020_can.dbc starts here\";\n\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 446 BRAKE_MODULE: 3 VSA\n SG_ BRAKE_PRESSED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BOH : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_2 : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nVAL_ 419 GEAR_SHIFTER  32 \"D\" 8 \"R\" 4 \"P\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/can/SConscript",
    "content": "Import('env', 'envCython', 'cereal')\n\nimport os\nfrom opendbc.can.process_dbc import process\n\ndbcs = []\nfor x in sorted(os.listdir('../')):\n  if x.endswith(\".dbc\"):\n    def compile_dbc(target, source, env):\n      process(source[0].path, target[0].path)\n    in_fn = [os.path.join('../', x), 'dbc_template.cc']\n    out_fn = os.path.join('dbc_out', x.replace(\".dbc\", \".cc\"))\n    dbc = env.Command(out_fn, in_fn, compile_dbc)\n    dbcs.append(dbc)\n\nlibdbc = env.SharedLibrary('libdbc', [\"dbc.cc\", \"parser.cc\", \"packer.cc\", \"common.cc\"]+dbcs, LIBS=[\"capnp\", \"kj\"])\n\n# Build packer and parser\nlenv = envCython.Clone()\nlenv[\"LINKFLAGS\"] += [libdbc[0].get_labspath()]\nparser = lenv.Program('parser_pyx.so', 'parser_pyx.pyx')\npacker = lenv.Program('packer_pyx.so', 'packer_pyx.pyx')\n\nlenv.Depends(parser, libdbc)\nlenv.Depends(packer, libdbc)\n"
  },
  {
    "path": "opendbc/can/__init__.py",
    "content": ""
  },
  {
    "path": "opendbc/can/can_define.py",
    "content": "from opendbc.can.parser_pyx import CANDefine  # pylint: disable=no-name-in-module, import-error\nassert CANDefine\n"
  },
  {
    "path": "opendbc/can/common.cc",
    "content": "#include \"common.h\"\n\nunsigned int honda_checksum(unsigned int address, uint64_t d, int l) {\n  d >>= ((8-l)*8); // remove padding\n  d >>= 4; // remove checksum\n\n  int s = 0;\n  bool extended = address > 0x7FF; // extended can\n  while (address) { s += (address & 0xF); address >>= 4; }\n  while (d) { s += (d & 0xF); d >>= 4; }\n  s = 8-s;\n  if (extended) s += 3;\n  s &= 0xF;\n\n  return s;\n}\n\nunsigned int toyota_checksum(unsigned int address, uint64_t d, int l) {\n  d >>= ((8-l)*8); // remove padding\n  d >>= 8; // remove checksum\n\n  unsigned int s = l;\n  while (address) { s += address & 0xFF; address >>= 8; }\n  while (d) { s += d & 0xFF; d >>= 8; }\n\n  return s & 0xFF;\n}\n\nunsigned int subaru_checksum(unsigned int address, uint64_t d, int l) {\n  d >>= ((8-l)*8); // remove padding\n\n  unsigned int s = 0;\n  while (address) { s += address & 0xFF; address >>= 8; }\n  l -= 1; // checksum is first byte\n  while (l) { s += d & 0xFF; d >>= 8; l -= 1; }\n\n  return s & 0xFF;\n}\n\nunsigned int chrysler_checksum(unsigned int address, uint64_t d, int l) {\n  /* This function does not want the checksum byte in the input data.\n  jeep chrysler canbus checksum from http://illmatics.com/Remote%20Car%20Hacking.pdf */\n  uint8_t checksum = 0xFF;\n  for (int j = 0; j < (l - 1); j++) {\n    uint8_t shift = 0x80;\n    uint8_t curr = (d >> 8*j) & 0xFF;\n    for (int i=0; i<8; i++) {\n      uint8_t bit_sum = curr & shift;\n      uint8_t temp_chk = checksum & 0x80U;\n      if (bit_sum != 0U) {\n        bit_sum = 0x1C;\n        if (temp_chk != 0U) {\n          bit_sum = 1;\n        }\n        checksum = checksum << 1;\n        temp_chk = checksum | 1U;\n        bit_sum ^= temp_chk;\n      } else {\n        if (temp_chk != 0U) {\n          bit_sum = 0x1D;\n        }\n        checksum = checksum << 1;\n        bit_sum ^= checksum;\n      }\n      checksum = bit_sum;\n      shift = shift >> 1;\n    }\n  }\n  return ~checksum & 0xFF;\n}\n\n// Static lookup table for fast computation of CRC8 poly 0x2F, aka 8H2F/AUTOSAR\nuint8_t crc8_lut_8h2f[256];\n\nvoid gen_crc_lookup_table(uint8_t poly, uint8_t crc_lut[]) {\n  uint8_t crc;\n  int i, j;\n\n   for (i = 0; i < 256; i++) {\n    crc = i;\n    for (j = 0; j < 8; j++) {\n      if ((crc & 0x80) != 0)\n        crc = (uint8_t)((crc << 1) ^ poly);\n      else\n        crc <<= 1;\n    }\n    crc_lut[i] = crc;\n  }\n}\n\nvoid init_crc_lookup_tables() {\n  // At init time, set up static lookup tables for fast CRC computation.\n\n  gen_crc_lookup_table(0x2F, crc8_lut_8h2f);    // CRC-8 8H2F/AUTOSAR for Volkswagen\n}\n\nunsigned int volkswagen_crc(unsigned int address, uint64_t d, int l) {\n  // Volkswagen uses standard CRC8 8H2F/AUTOSAR, but they compute it with\n  // a magic variable padding byte tacked onto the end of the payload.\n  // https://www.autosar.org/fileadmin/user_upload/standards/classic/4-3/AUTOSAR_SWS_CRCLibrary.pdf\n\n  uint8_t crc = 0xFF; // Standard init value for CRC8 8H2F/AUTOSAR\n\n  // CRC the payload first, skipping over the first byte where the CRC lives.\n  for (int i = 1; i < l; i++) {\n    crc ^= (d >> (i*8)) & 0xFF;\n    crc = crc8_lut_8h2f[crc];\n  }\n\n  // Look up and apply the magic final CRC padding byte, which permutes by CAN\n  // address, and additionally (for SOME addresses) by the message counter.\n  uint8_t counter = ((d >> 8) & 0xFF) & 0x0F;\n  switch(address) {\n    case 0x86:  // LWI_01 Steering Angle\n      crc ^= (uint8_t[]){0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86,0x86}[counter];\n      break;\n    case 0x9F:  // LH_EPS_03 Electric Power Steering\n      crc ^= (uint8_t[]){0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5}[counter];\n      break;\n    case 0xAD:  // Getriebe_11 Automatic Gearbox\n      crc ^= (uint8_t[]){0x3F,0x69,0x39,0xDC,0x94,0xF9,0x14,0x64,0xD8,0x6A,0x34,0xCE,0xA2,0x55,0xB5,0x2C}[counter];\n      break;\n    case 0xFD:  // ESP_21 Electronic Stability Program\n      crc ^= (uint8_t[]){0xB4,0xEF,0xF8,0x49,0x1E,0xE5,0xC2,0xC0,0x97,0x19,0x3C,0xC9,0xF1,0x98,0xD6,0x61}[counter];\n      break;\n    case 0x106: // ESP_05 Electronic Stability Program\n      crc ^= (uint8_t[]){0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07}[counter];\n      break;\n    case 0x117: // ACC_10 Automatic Cruise Control\n      crc ^= (uint8_t[]){0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16}[counter];\n      break;\n    case 0x120: // TSK_06 Drivetrain Coordinator\n      crc ^= (uint8_t[]){0xC4,0xE2,0x4F,0xE4,0xF8,0x2F,0x56,0x81,0x9F,0xE5,0x83,0x44,0x05,0x3F,0x97,0xDF}[counter];\n      break;\n    case 0x121: // Motor_20 Driver Throttle Inputs\n      crc ^= (uint8_t[]){0xE9,0x65,0xAE,0x6B,0x7B,0x35,0xE5,0x5F,0x4E,0xC7,0x86,0xA2,0xBB,0xDD,0xEB,0xB4}[counter];\n      break;\n    case 0x122: // ACC_06 Automatic Cruise Control\n      crc ^= (uint8_t[]){0x37,0x7D,0xF3,0xA9,0x18,0x46,0x6D,0x4D,0x3D,0x71,0x92,0x9C,0xE5,0x32,0x10,0xB9}[counter];\n      break;\n    case 0x126: // HCA_01 Heading Control Assist\n      crc ^= (uint8_t[]){0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA}[counter];\n      break;\n    case 0x12B: // GRA_ACC_01 Steering wheel controls for ACC\n      crc ^= (uint8_t[]){0x6A,0x38,0xB4,0x27,0x22,0xEF,0xE1,0xBB,0xF8,0x80,0x84,0x49,0xC7,0x9E,0x1E,0x2B}[counter];\n      break;\n    case 0x187: // EV_Gearshift \"Gear\" selection data for EVs with no gearbox\n      crc ^= (uint8_t[]){0x7F,0xED,0x17,0xC2,0x7C,0xEB,0x44,0x21,0x01,0xFA,0xDB,0x15,0x4A,0x6B,0x23,0x05}[counter];\n      break;\n    case 0x30C: // ACC_02 Automatic Cruise Control\n      crc ^= (uint8_t[]){0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F}[counter];\n      break;\n    case 0x30F: // SWA_01 Lane Change Assist (SpurWechselAssistent)\n      crc ^= (uint8_t[]){0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C}[counter];\n      break;\n    case 0x324: // ACC_04 Automatic Cruise Control\n      crc ^= (uint8_t[]){0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27,0x27}[counter];\n      break;\n    case 0x3C0: // Klemmen_Status_01 ignition and starting status\n      crc ^= (uint8_t[]){0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3,0xC3}[counter];\n      break;\n    case 0x65D: // ESP_20 Electronic Stability Program\n      crc ^= (uint8_t[]){0xAC,0xB3,0xAB,0xEB,0x7A,0xE1,0x3B,0xF7,0x73,0xBA,0x7C,0x9E,0x06,0x5F,0x02,0xD9}[counter];\n      break;\n    default:    // As-yet undefined CAN message, CRC check expected to fail\n      printf(\"Attempt to CRC check undefined Volkswagen message 0x%02X\\n\", address);\n      crc ^= (uint8_t[]){0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}[counter];\n      break;\n  }\n  crc = crc8_lut_8h2f[crc];\n\n  return crc ^ 0xFF; // Return after standard final XOR for CRC8 8H2F/AUTOSAR\n}\n\n\nunsigned int pedal_checksum(uint64_t d, int l) {\n  uint8_t crc = 0xFF;\n  uint8_t poly = 0xD5; // standard crc8\n\n  d >>= ((8-l)*8); // remove padding\n  d >>= 8; // remove checksum\n\n  int i, j;\n  for (i = 0; i < l - 1; i++) {\n    crc ^= (d >> (i*8)) & 0xFF;\n    for (j = 0; j < 8; j++) {\n      if ((crc & 0x80) != 0) {\n        crc = (uint8_t)((crc << 1) ^ poly);\n      }\n      else {\n        crc <<= 1;\n      }\n    }\n  }\n  return crc;\n}\n\n\nuint64_t read_u64_be(const uint8_t* v) {\n  return (((uint64_t)v[0] << 56)\n          | ((uint64_t)v[1] << 48)\n          | ((uint64_t)v[2] << 40)\n          | ((uint64_t)v[3] << 32)\n          | ((uint64_t)v[4] << 24)\n          | ((uint64_t)v[5] << 16)\n          | ((uint64_t)v[6] << 8)\n          | (uint64_t)v[7]);\n}\n\nuint64_t read_u64_le(const uint8_t* v) {\n  return ((uint64_t)v[0]\n          | ((uint64_t)v[1] << 8)\n          | ((uint64_t)v[2] << 16)\n          | ((uint64_t)v[3] << 24)\n          | ((uint64_t)v[4] << 32)\n          | ((uint64_t)v[5] << 40)\n          | ((uint64_t)v[6] << 48)\n          | ((uint64_t)v[7] << 56));\n}\n"
  },
  {
    "path": "opendbc/can/common.h",
    "content": "#pragma once\n\n#include <vector>\n#include <map>\n#include <unordered_map>\n\n#include \"common_dbc.h\"\n#include <capnp/dynamic.h>\n#include <capnp/serialize.h>\n\n#ifndef DYNAMIC_CAPNP\n#include \"cereal/gen/cpp/log.capnp.h\"\n#endif\n\n#define MAX_BAD_COUNTER 5\n\n// Helper functions\nunsigned int honda_checksum(unsigned int address, uint64_t d, int l);\nunsigned int toyota_checksum(unsigned int address, uint64_t d, int l);\nunsigned int subaru_checksum(unsigned int address, uint64_t d, int l);\nunsigned int chrysler_checksum(unsigned int address, uint64_t d, int l);\nvoid init_crc_lookup_tables();\nunsigned int volkswagen_crc(unsigned int address, uint64_t d, int l);\nunsigned int pedal_checksum(uint64_t d, int l);\nuint64_t read_u64_be(const uint8_t* v);\nuint64_t read_u64_le(const uint8_t* v);\n\nclass MessageState {\npublic:\n  uint32_t address;\n  unsigned int size;\n\n  std::vector<Signal> parse_sigs;\n  std::vector<double> vals;\n\n  uint16_t ts;\n  uint64_t seen;\n  uint64_t check_threshold;\n\n  uint8_t counter;\n  uint8_t counter_fail;\n\n  bool ignore_checksum = false;\n  bool ignore_counter = false;\n\n  bool parse(uint64_t sec, uint16_t ts_, uint8_t * dat);\n  bool update_counter_generic(int64_t v, int cnt_size);\n};\n\nclass CANParser {\nprivate:\n  const int bus;\n  kj::Array<capnp::word> aligned_buf;\n\n  const DBC *dbc = NULL;\n  std::unordered_map<uint32_t, MessageState> message_states;\n\npublic:\n  bool can_valid = false;\n  uint64_t last_sec = 0;\n\n  CANParser(int abus, const std::string& dbc_name,\n            const std::vector<MessageParseOptions> &options,\n            const std::vector<SignalParseOptions> &sigoptions);\n  CANParser(int abus, const std::string& dbc_name, bool ignore_checksum, bool ignore_counter);\n  #ifndef DYNAMIC_CAPNP\n  void update_string(const std::string &data, bool sendcan);\n  void UpdateCans(uint64_t sec, const capnp::List<cereal::CanData>::Reader& cans);\n  #endif\n  void UpdateCans(uint64_t sec, const capnp::DynamicStruct::Reader& cans);\n  void UpdateValid(uint64_t sec);\n  std::vector<SignalValue> query_latest();\n};\n\nclass CANPacker {\nprivate:\n  const DBC *dbc = NULL;\n  std::map<std::pair<uint32_t, std::string>, Signal> signal_lookup;\n  std::map<uint32_t, Msg> message_lookup;\n\npublic:\n  CANPacker(const std::string& dbc_name);\n  uint64_t pack(uint32_t address, const std::vector<SignalPackValue> &values, int counter);\n  Msg* lookup_message(uint32_t address);\n};\n"
  },
  {
    "path": "opendbc/can/common.pxd",
    "content": "# distutils: language = c++\n#cython: language_level=3\n\nfrom libc.stdint cimport uint32_t, uint64_t, uint16_t\nfrom libcpp.vector cimport vector\nfrom libcpp.map cimport map\nfrom libcpp.string cimport string\nfrom libcpp.unordered_set cimport unordered_set\nfrom libcpp cimport bool\n\n\ncdef extern from \"common_dbc.h\":\n  ctypedef enum SignalType:\n    DEFAULT,\n    HONDA_CHECKSUM,\n    HONDA_COUNTER,\n    TOYOTA_CHECKSUM,\n    PEDAL_CHECKSUM,\n    PEDAL_COUNTER,\n    VOLKSWAGEN_CHECKSUM,\n    VOLKSWAGEN_COUNTER,\n    SUBARU_CHECKSUM,\n    CHRYSLER_CHECKSUM\n\n  cdef struct Signal:\n    const char* name\n    int b1, b2, bo\n    bool is_signed\n    double factor, offset\n    SignalType type\n\n  cdef struct Msg:\n    const char* name\n    uint32_t address\n    unsigned int size\n    size_t num_sigs\n    const Signal *sigs\n\n  cdef struct Val:\n    const char* name\n    uint32_t address\n    const char* def_val\n    const Signal *sigs\n\n  cdef struct DBC:\n    const char* name\n    size_t num_msgs\n    const Msg *msgs\n    const Val *vals\n    size_t num_vals\n\n  cdef struct SignalParseOptions:\n    uint32_t address\n    const char* name\n    double default_value\n\n\n  cdef struct MessageParseOptions:\n    uint32_t address\n    int check_frequency\n\n  cdef struct SignalValue:\n    uint32_t address\n    uint16_t ts\n    const char* name\n    double value\n\n  cdef struct SignalPackValue:\n    string name\n    double value\n\n\ncdef extern from \"common.h\":\n  cdef const DBC* dbc_lookup(const string);\n\n  cdef cppclass CANParser:\n    bool can_valid\n    CANParser(int, string, vector[MessageParseOptions], vector[SignalParseOptions])\n    void update_string(string, bool)\n    vector[SignalValue] query_latest()\n\n  cdef cppclass CANPacker:\n   CANPacker(string)\n   uint64_t pack(uint32_t, vector[SignalPackValue], int counter)\n"
  },
  {
    "path": "opendbc/can/common_dbc.h",
    "content": "#pragma once\n\n#include <cstddef>\n#include <cstdint>\n#include <string>\n#include <vector>\n\n#define ARRAYSIZE(x) (sizeof(x)/sizeof(x[0]))\n\nstruct SignalPackValue {\n  std::string name;\n  double value;\n};\n\nstruct SignalParseOptions {\n  uint32_t address;\n  const char* name;\n  double default_value;\n};\n\nstruct MessageParseOptions {\n  uint32_t address;\n  int check_frequency;\n};\n\nstruct SignalValue {\n  uint32_t address;\n  uint16_t ts;\n  const char* name;\n  double value;\n};\n\nenum SignalType {\n  DEFAULT,\n  HONDA_CHECKSUM,\n  HONDA_COUNTER,\n  TOYOTA_CHECKSUM,\n  PEDAL_CHECKSUM,\n  PEDAL_COUNTER,\n  VOLKSWAGEN_CHECKSUM,\n  VOLKSWAGEN_COUNTER,\n  SUBARU_CHECKSUM,\n  CHRYSLER_CHECKSUM,\n};\n\nstruct Signal {\n  const char* name;\n  int b1, b2, bo;\n  bool is_signed;\n  double factor, offset;\n  bool is_little_endian;\n  SignalType type;\n};\n\nstruct Msg {\n  const char* name;\n  uint32_t address;\n  unsigned int size;\n  size_t num_sigs;\n  const Signal *sigs;\n};\n\nstruct Val {\n  const char* name;\n  uint32_t address;\n  const char* def_val;\n  const Signal *sigs;\n};\n\nstruct DBC {\n  const char* name;\n  size_t num_msgs;\n  const Msg *msgs;\n  const Val *vals;\n  size_t num_vals;\n};\n\nstd::vector<const DBC*>& get_dbcs();\nconst DBC* dbc_lookup(const std::string& dbc_name);\n\nvoid dbc_register(const DBC* dbc);\n\n#define dbc_init(dbc) \\\nstatic void __attribute__((constructor)) do_dbc_init_ ## dbc(void) { \\\n  dbc_register(&dbc); \\\n}\n"
  },
  {
    "path": "opendbc/can/dbc.cc",
    "content": "#include <vector>\n\n#include \"common_dbc.h\"\n\nstd::vector<const DBC*>& get_dbcs() {\n  static std::vector<const DBC*> vec;\n  return vec;\n}\n\nconst DBC* dbc_lookup(const std::string& dbc_name) {\n  for (const auto& dbci : get_dbcs()) {\n    if (dbc_name == dbci->name) {\n      return dbci;\n    }\n  }\n  return NULL;\n}\n\nvoid dbc_register(const DBC* dbc) {\n  get_dbcs().push_back(dbc);\n}\n\nextern \"C\" {\n  const DBC* dbc_lookup(const char* dbc_name) {\n    return dbc_lookup(std::string(dbc_name));\n  }\n}\n"
  },
  {
    "path": "opendbc/can/dbc.py",
    "content": "import re\nimport os\nimport struct\nimport sys\nimport numbers\nfrom collections import namedtuple, defaultdict\n\ndef int_or_float(s):\n  # return number, trying to maintain int format\n  if s.isdigit():\n    return int(s, 10)\n  else:\n    return float(s)\n\n\nDBCSignal = namedtuple(\n  \"DBCSignal\", [\"name\", \"start_bit\", \"size\", \"is_little_endian\", \"is_signed\",\n                \"factor\", \"offset\", \"tmin\", \"tmax\", \"units\"])\n\n\nclass dbc():\n  def __init__(self, fn):\n    self.name, _ = os.path.splitext(os.path.basename(fn))\n    with open(fn, encoding=\"ascii\") as f:\n      self.txt = f.readlines()\n    self._warned_addresses = set()\n\n    # regexps from https://github.com/ebroecker/canmatrix/blob/master/canmatrix/importdbc.py\n    bo_regexp = re.compile(r\"^BO\\_ (\\w+) (\\w+) *: (\\w+) (\\w+)\")\n    sg_regexp = re.compile(r\"^SG\\_ (\\w+) : (\\d+)\\|(\\d+)@(\\d+)([\\+|\\-]) \\(([0-9.+\\-eE]+),([0-9.+\\-eE]+)\\) \\[([0-9.+\\-eE]+)\\|([0-9.+\\-eE]+)\\] \\\"(.*)\\\" (.*)\")\n    sgm_regexp = re.compile(r\"^SG\\_ (\\w+) (\\w+) *: (\\d+)\\|(\\d+)@(\\d+)([\\+|\\-]) \\(([0-9.+\\-eE]+),([0-9.+\\-eE]+)\\) \\[([0-9.+\\-eE]+)\\|([0-9.+\\-eE]+)\\] \\\"(.*)\\\" (.*)\")\n    val_regexp = re.compile(r\"VAL\\_ (\\w+) (\\w+) (\\s*[-+]?[0-9]+\\s+\\\".+?\\\"[^;]*)\")\n\n    # A dictionary which maps message ids to tuples ((name, size), signals).\n    #   name is the ASCII name of the message.\n    #   size is the size of the message in bytes.\n    #   signals is a list signals contained in the message.\n    # signals is a list of DBCSignal in order of increasing start_bit.\n    self.msgs = {}\n\n    # A dictionary which maps message ids to a list of tuples (signal name, definition value pairs)\n    self.def_vals = defaultdict(list)\n\n    # lookup to bit reverse each byte\n    self.bits_index = [(i & ~0b111) + ((-i - 1) & 0b111) for i in range(64)]\n\n    for l in self.txt:\n      l = l.strip()\n\n      if l.startswith(\"BO_ \"):\n        # new group\n        dat = bo_regexp.match(l)\n\n        if dat is None:\n          print(\"bad BO {0}\".format(l))\n\n        name = dat.group(2)\n        size = int(dat.group(3))\n        ids = int(dat.group(1), 0)  # could be hex\n        if ids in self.msgs:\n          sys.exit(\"Duplicate address detected %d %s\" % (ids, self.name))\n\n        self.msgs[ids] = ((name, size), [])\n\n      if l.startswith(\"SG_ \"):\n        # new signal\n        dat = sg_regexp.match(l)\n        go = 0\n        if dat is None:\n          dat = sgm_regexp.match(l)\n          go = 1\n\n        if dat is None:\n          print(\"bad SG {0}\".format(l))\n\n        sgname = dat.group(1)\n        start_bit = int(dat.group(go + 2))\n        signal_size = int(dat.group(go + 3))\n        is_little_endian = int(dat.group(go + 4)) == 1\n        is_signed = dat.group(go + 5) == '-'\n        factor = int_or_float(dat.group(go + 6))\n        offset = int_or_float(dat.group(go + 7))\n        tmin = int_or_float(dat.group(go + 8))\n        tmax = int_or_float(dat.group(go + 9))\n        units = dat.group(go + 10)\n\n        self.msgs[ids][1].append(\n          DBCSignal(sgname, start_bit, signal_size, is_little_endian,\n                    is_signed, factor, offset, tmin, tmax, units))\n\n      if l.startswith(\"VAL_ \"):\n        # new signal value/definition\n        dat = val_regexp.match(l)\n\n        if dat is None:\n          print(\"bad VAL {0}\".format(l))\n\n        ids = int(dat.group(1), 0)  # could be hex\n        sgname = dat.group(2)\n        defvals = dat.group(3)\n\n        defvals = defvals.replace(\"?\", r\"\\?\")  # escape sequence in C++\n        defvals = defvals.split('\"')[:-1]\n\n        # convert strings to UPPER_CASE_WITH_UNDERSCORES\n        defvals[1::2] = [d.strip().upper().replace(\" \", \"_\") for d in defvals[1::2]]\n        defvals = '\"' + \"\".join(str(i) for i in defvals) + '\"'\n\n        self.def_vals[ids].append((sgname, defvals))\n\n    for msg in self.msgs.values():\n      msg[1].sort(key=lambda x: x.start_bit)\n\n    self.msg_name_to_address = {}\n    for address, m in self.msgs.items():\n      name = m[0][0]\n      self.msg_name_to_address[name] = address\n\n  def lookup_msg_id(self, msg_id):\n    if not isinstance(msg_id, numbers.Number):\n      msg_id = self.msg_name_to_address[msg_id]\n    return msg_id\n\n  def reverse_bytes(self, x):\n    return ((x & 0xff00000000000000) >> 56) | \\\n           ((x & 0x00ff000000000000) >> 40) | \\\n           ((x & 0x0000ff0000000000) >> 24) | \\\n           ((x & 0x000000ff00000000) >> 8) | \\\n           ((x & 0x00000000ff000000) << 8) | \\\n           ((x & 0x0000000000ff0000) << 24) | \\\n           ((x & 0x000000000000ff00) << 40) | \\\n           ((x & 0x00000000000000ff) << 56)\n\n  def encode(self, msg_id, dd):\n    \"\"\"Encode a CAN message using the dbc.\n\n       Inputs:\n        msg_id: The message ID.\n        dd: A dictionary mapping signal name to signal data.\n    \"\"\"\n    msg_id = self.lookup_msg_id(msg_id)\n\n    msg_def = self.msgs[msg_id]\n    size = msg_def[0][1]\n\n    result = 0\n    for s in msg_def[1]:\n      ival = dd.get(s.name)\n      if ival is not None:\n\n        ival = (ival / s.factor) - s.offset\n        ival = int(round(ival))\n\n        if s.is_signed and ival < 0:\n          ival = (1 << s.size) + ival\n\n        if s.is_little_endian:\n          shift = s.start_bit\n        else:\n          b1 = (s.start_bit // 8) * 8 + (-s.start_bit - 1) % 8\n          shift = 64 - (b1 + s.size)\n\n        mask = ((1 << s.size) - 1) << shift\n        dat = (ival & ((1 << s.size) - 1)) << shift\n\n        if s.is_little_endian:\n          mask = self.reverse_bytes(mask)\n          dat = self.reverse_bytes(dat)\n\n        result &= ~mask\n        result |= dat\n\n    result = struct.pack('>Q', result)\n    return result[:size]\n\n  def decode(self, x, arr=None, debug=False):\n    \"\"\"Decode a CAN message using the dbc.\n\n       Inputs:\n        x: A collection with elements (address, time, data), where address is\n           the CAN address, time is the bus time, and data is the CAN data as a\n           hex string.\n        arr: Optional list of signals which should be decoded and returned.\n        debug: True to print debugging statements.\n\n       Returns:\n        A tuple (name, data), where name is the name of the CAN message and data\n        is the decoded result. If arr is None, data is a dict of properties.\n        Otherwise data is a list of the same length as arr.\n\n        Returns (None, None) if the message could not be decoded.\n    \"\"\"\n\n    if arr is None:\n      out = {}\n    else:\n      out = [None] * len(arr)\n\n    msg = self.msgs.get(x[0])\n    if msg is None:\n      if x[0] not in self._warned_addresses:\n        # print(\"WARNING: Unknown message address {}\".format(x[0]))\n        self._warned_addresses.add(x[0])\n      return None, None\n\n    name = msg[0][0]\n    if debug:\n      print(name)\n\n    st = x[2].ljust(8, b'\\x00')\n    le, be = None, None\n\n    for s in msg[1]:\n      if arr is not None and s[0] not in arr:\n        continue\n\n      start_bit = s[1]\n      signal_size = s[2]\n      little_endian = s[3]\n      signed = s[4]\n      factor = s[5]\n      offset = s[6]\n\n      if little_endian:\n        if le is None:\n          le = struct.unpack(\"<Q\", st)[0]\n        tmp = le\n        shift_amount = start_bit\n      else:\n        if be is None:\n          be = struct.unpack(\">Q\", st)[0]\n        tmp = be\n        b1 = (start_bit // 8) * 8 + (-start_bit - 1) % 8\n        shift_amount = 64 - (b1 + signal_size)\n\n      if shift_amount < 0:\n        continue\n\n      tmp = (tmp >> shift_amount) & ((1 << signal_size) - 1)\n      if signed and (tmp >> (signal_size - 1)):\n        tmp -= (1 << signal_size)\n\n      tmp = tmp * factor + offset\n\n      # if debug:\n      #   print(\"%40s  %2d %2d  %7.2f %s\" % (s[0], s[1], s[2], tmp, s[-1]))\n\n      if arr is None:\n        out[s[0]] = tmp\n      else:\n        out[arr.index(s[0])] = tmp\n    return name, out\n\n  def get_signals(self, msg):\n    msg = self.lookup_msg_id(msg)\n    return [sgs.name for sgs in self.msgs[msg][1]]\n\n\nif __name__ == \"__main__\":\n   from opendbc import DBC_PATH\n\n   dbc_test = dbc(os.path.join(DBC_PATH, 'toyota_prius_2017_pt_generated.dbc'))\n   msg = ('STEER_ANGLE_SENSOR', {'STEER_ANGLE': -6.0, 'STEER_RATE': 4, 'STEER_FRACTION': -0.2})\n   encoded = dbc_test.encode(*msg)\n   decoded = dbc_test.decode((0x25, 0, encoded))\n   assert decoded == msg\n\n   dbc_test = dbc(os.path.join(DBC_PATH, 'hyundai_santa_fe_2019_ccan.dbc'))\n   decoded = dbc_test.decode((0x2b0, 0, \"\\xfa\\xfe\\x00\\x07\\x12\"))\n   assert abs(decoded[1]['SAS_Angle'] - (-26.2)) < 0.001\n\n   msg = ('SAS11', {'SAS_Stat': 7.0, 'MsgCount': 0.0, 'SAS_Angle': -26.200000000000003, 'SAS_Speed': 0.0, 'CheckSum': 0.0})\n   encoded = dbc_test.encode(*msg)\n   decoded = dbc_test.decode((0x2b0, 0, encoded))\n\n   assert decoded == msg\n"
  },
  {
    "path": "opendbc/can/dbc_out/.gitignore",
    "content": "*.cc\n\n"
  },
  {
    "path": "opendbc/can/dbc_out/.gitkeep",
    "content": ""
  },
  {
    "path": "opendbc/can/dbc_template.cc",
    "content": "#include \"common_dbc.h\"\n\nnamespace {\n\n{% for address, msg_name, msg_size, sigs in msgs %}\nconst Signal sigs_{{address}}[] = {\n  {% for sig in sigs %}\n    {\n      {% if sig.is_little_endian %}\n        {% set b1 = sig.start_bit %}\n      {% else %}\n        {% set b1 = (sig.start_bit//8)*8  + (-sig.start_bit-1) % 8 %}\n      {% endif %}\n      .name = \"{{sig.name}}\",\n      .b1 = {{b1}},\n      .b2 = {{sig.size}},\n      .bo = {{64 - (b1 + sig.size)}},\n      .is_signed = {{\"true\" if sig.is_signed else \"false\"}},\n      .factor = {{sig.factor}},\n      .offset = {{sig.offset}},\n      .is_little_endian = {{\"true\" if sig.is_little_endian else \"false\"}},\n      {% if checksum_type == \"honda\" and sig.name == \"CHECKSUM\" %}\n      .type = SignalType::HONDA_CHECKSUM,\n      {% elif checksum_type == \"honda\" and sig.name == \"COUNTER\" %}\n      .type = SignalType::HONDA_COUNTER,\n      {% elif checksum_type == \"toyota\" and sig.name == \"CHECKSUM\" %}\n      .type = SignalType::TOYOTA_CHECKSUM,\n      {% elif checksum_type == \"volkswagen\" and sig.name == \"CHECKSUM\" %}\n      .type = SignalType::VOLKSWAGEN_CHECKSUM,\n      {% elif checksum_type == \"volkswagen\" and sig.name == \"COUNTER\" %}\n      .type = SignalType::VOLKSWAGEN_COUNTER,\n      {% elif checksum_type == \"subaru\" and sig.name == \"CHECKSUM\" %}\n      .type = SignalType::SUBARU_CHECKSUM,\n      {% elif checksum_type == \"chrysler\" and sig.name == \"CHECKSUM\" %}\n      .type = SignalType::CHRYSLER_CHECKSUM,\n      {% elif address in [512, 513] and sig.name == \"CHECKSUM_PEDAL\" %}\n      .type = SignalType::PEDAL_CHECKSUM,\n      {% elif address in [512, 513] and sig.name == \"COUNTER_PEDAL\" %}\n      .type = SignalType::PEDAL_COUNTER,\n      {% else %}\n      .type = SignalType::DEFAULT,\n      {% endif %}\n    },\n  {% endfor %}\n};\n{% endfor %}\n\nconst Msg msgs[] = {\n{% for address, msg_name, msg_size, sigs in msgs %}\n  {% set address_hex = \"0x%X\" % address %}\n  {\n    .name = \"{{msg_name}}\",\n    .address = {{address_hex}},\n    .size = {{msg_size}},\n    .num_sigs = ARRAYSIZE(sigs_{{address}}),\n    .sigs = sigs_{{address}},\n  },\n{% endfor %}\n};\n\nconst Val vals[] = {\n{% for address, sig in def_vals %}\n  {% for sg_name, def_val in sig %}\n    {% set address_hex = \"0x%X\" % address %}\n    {\n      .name = \"{{sg_name}}\",\n      .address = {{address_hex}},\n      .def_val = {{def_val}},\n      .sigs = sigs_{{address}},\n    },\n  {% endfor %}\n{% endfor %}\n};\n\n}\n\nconst DBC {{dbc.name}} = {\n  .name = \"{{dbc.name}}\",\n  .num_msgs = ARRAYSIZE(msgs),\n  .msgs = msgs,\n  .vals = vals,\n  .num_vals = ARRAYSIZE(vals),\n};\n\ndbc_init({{dbc.name}})\n"
  },
  {
    "path": "opendbc/can/packer.cc",
    "content": "#include <cassert>\n#include <utility>\n#include <algorithm>\n#include <map>\n#include <cmath>\n\n#include \"common.h\"\n\n#define WARN printf\n\n// this is the same as read_u64_le, but uses uint64_t as in/out\nuint64_t ReverseBytes(uint64_t x) {\n  return ((x & 0xff00000000000000ull) >> 56) |\n          ((x & 0x00ff000000000000ull) >> 40) |\n          ((x & 0x0000ff0000000000ull) >> 24) |\n          ((x & 0x000000ff00000000ull) >> 8) |\n          ((x & 0x00000000ff000000ull) << 8) |\n          ((x & 0x0000000000ff0000ull) << 24) |\n          ((x & 0x000000000000ff00ull) << 40) |\n          ((x & 0x00000000000000ffull) << 56);\n}\n\nstatic uint64_t set_value(uint64_t ret, const Signal& sig, int64_t ival) {\n  int shift = sig.is_little_endian? sig.b1 : sig.bo;\n  uint64_t mask = ((1ULL << sig.b2)-1) << shift;\n  uint64_t dat = (ival & ((1ULL << sig.b2)-1)) << shift;\n  if (sig.is_little_endian) {\n    dat = ReverseBytes(dat);\n    mask = ReverseBytes(mask);\n  }\n  ret &= ~mask;\n  ret |= dat;\n  return ret;\n}\n\nCANPacker::CANPacker(const std::string& dbc_name) {\n  dbc = dbc_lookup(dbc_name);\n  assert(dbc);\n\n  for (int i=0; i<dbc->num_msgs; i++) {\n    const Msg* msg = &dbc->msgs[i];\n    message_lookup[msg->address] = *msg;\n    for (int j=0; j<msg->num_sigs; j++) {\n      const Signal* sig = &msg->sigs[j];\n      signal_lookup[std::make_pair(msg->address, std::string(sig->name))] = *sig;\n    }\n  }\n  init_crc_lookup_tables();\n}\n\nuint64_t CANPacker::pack(uint32_t address, const std::vector<SignalPackValue> &signals, int counter) {\n  uint64_t ret = 0;\n  for (const auto& sigval : signals) {\n    double value = sigval.value;\n\n    auto sig_it = signal_lookup.find(std::make_pair(address, sigval.name));\n    if (sig_it == signal_lookup.end()) {\n      WARN(\"undefined signal %s - %d\\n\", sigval.name.c_str(), address);\n      continue;\n    }\n    const auto& sig = sig_it->second;\n\n    int64_t ival = (int64_t)(round((value - sig.offset) / sig.factor));\n    if (ival < 0) {\n      ival = (1ULL << sig.b2) + ival;\n    }\n\n    ret = set_value(ret, sig, ival);\n  }\n\n  if (counter >= 0){\n    auto sig_it = signal_lookup.find(std::make_pair(address, \"COUNTER\"));\n    if (sig_it == signal_lookup.end()) {\n      WARN(\"COUNTER not defined\\n\");\n      return ret;\n    }\n    const auto& sig = sig_it->second;\n\n    if ((sig.type != SignalType::HONDA_COUNTER) && (sig.type != SignalType::VOLKSWAGEN_COUNTER)) {\n      WARN(\"COUNTER signal type not valid\\n\");\n    }\n\n    ret = set_value(ret, sig, counter);\n  }\n\n  auto sig_it_checksum = signal_lookup.find(std::make_pair(address, \"CHECKSUM\"));\n  if (sig_it_checksum != signal_lookup.end()) {\n    const auto& sig = sig_it_checksum->second;\n    if (sig.type == SignalType::HONDA_CHECKSUM) {\n      unsigned int chksm = honda_checksum(address, ret, message_lookup[address].size);\n      ret = set_value(ret, sig, chksm);\n    } else if (sig.type == SignalType::TOYOTA_CHECKSUM) {\n      unsigned int chksm = toyota_checksum(address, ret, message_lookup[address].size);\n      ret = set_value(ret, sig, chksm);\n    } else if (sig.type == SignalType::VOLKSWAGEN_CHECKSUM) {\n      // FIXME: Hackish fix for an endianness issue. The message is in reverse byte order\n      // until later in the pack process. Checksums can be run backwards, CRCs not so much.\n      // The correct fix is unclear but this works for the moment.\n      unsigned int chksm = volkswagen_crc(address, ReverseBytes(ret), message_lookup[address].size);\n      ret = set_value(ret, sig, chksm);\n    } else if (sig.type == SignalType::SUBARU_CHECKSUM) {\n      unsigned int chksm = subaru_checksum(address, ret, message_lookup[address].size);\n      ret = set_value(ret, sig, chksm);\n    } else if (sig.type == SignalType::CHRYSLER_CHECKSUM) {\n      unsigned int chksm = chrysler_checksum(address, ReverseBytes(ret), message_lookup[address].size);\n      ret = set_value(ret, sig, chksm);\n    } else {\n      //WARN(\"CHECKSUM signal type not valid\\n\");\n    }\n  }\n\n  return ret;\n}\n\nMsg* CANPacker::lookup_message(uint32_t address) {\n  return &message_lookup[address];\n}\n"
  },
  {
    "path": "opendbc/can/packer.py",
    "content": "# pylint: skip-file\nfrom opendbc.can.packer_pyx import CANPacker\nassert CANPacker\n"
  },
  {
    "path": "opendbc/can/packer_pyx.pyx",
    "content": "# distutils: language = c++\n# cython: c_string_encoding=ascii, language_level=3\n\nfrom libc.stdint cimport uint32_t, uint64_t\nfrom libcpp.vector cimport vector\nfrom libcpp.map cimport map\nfrom libcpp.string cimport string\nfrom libcpp cimport bool\nfrom posix.dlfcn cimport dlopen, dlsym, RTLD_LAZY\n\nfrom .common cimport CANPacker as cpp_CANPacker\nfrom .common cimport dbc_lookup, SignalPackValue, DBC\n\n\ncdef class CANPacker:\n  cdef:\n    cpp_CANPacker *packer\n    const DBC *dbc\n    map[string, (int, int)] name_to_address_and_size\n    map[int, int] address_to_size\n\n  def __init__(self, dbc_name):\n    self.dbc = dbc_lookup(dbc_name)\n    if not self.dbc:\n      raise RuntimeError(f\"Can't lookup {dbc_name}\")\n\n    self.packer = new cpp_CANPacker(dbc_name)\n    num_msgs = self.dbc[0].num_msgs\n    for i in range(num_msgs):\n      msg = self.dbc[0].msgs[i]\n      self.name_to_address_and_size[string(msg.name)] = (msg.address, msg.size)\n      self.address_to_size[msg.address] = msg.size\n\n  cdef uint64_t pack(self, addr, values, counter):\n    cdef vector[SignalPackValue] values_thing\n    values_thing.reserve(len(values))\n    cdef SignalPackValue spv\n\n    for name, value in values.iteritems():\n      spv.name = name.encode('utf8')\n      spv.value = value\n      values_thing.push_back(spv)\n\n    return self.packer.pack(addr, values_thing, counter)\n\n  cdef inline uint64_t ReverseBytes(self, uint64_t x):\n    return (((x & 0xff00000000000000ull) >> 56) |\n           ((x & 0x00ff000000000000ull) >> 40) |\n           ((x & 0x0000ff0000000000ull) >> 24) |\n           ((x & 0x000000ff00000000ull) >> 8) |\n           ((x & 0x00000000ff000000ull) << 8) |\n           ((x & 0x0000000000ff0000ull) << 24) |\n           ((x & 0x000000000000ff00ull) << 40) |\n           ((x & 0x00000000000000ffull) << 56))\n\n  cpdef make_can_msg(self, name_or_addr, bus, values, counter=-1):\n    cdef int addr, size\n    if type(name_or_addr) == int:\n      addr = name_or_addr\n      size = self.address_to_size[name_or_addr]\n    else:\n      addr, size = self.name_to_address_and_size[name_or_addr.encode('utf8')]\n    cdef uint64_t val = self.pack(addr, values, counter)\n    val = self.ReverseBytes(val)\n    return [addr, 0, (<char *>&val)[:size], bus]\n"
  },
  {
    "path": "opendbc/can/parser.cc",
    "content": "#include <cassert>\n#include <cstring>\n\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <algorithm>\n\n#include \"common.h\"\n\n#define DEBUG(...)\n// #define DEBUG printf\n#define INFO printf\n\nbool MessageState::parse(uint64_t sec, uint16_t ts_, uint8_t * dat) {\n  uint64_t dat_le = read_u64_le(dat);\n  uint64_t dat_be = read_u64_be(dat);\n\n  for (int i=0; i < parse_sigs.size(); i++) {\n    auto& sig = parse_sigs[i];\n    int64_t tmp;\n\n    if (sig.is_little_endian){\n      tmp = (dat_le >> sig.b1) & ((1ULL << sig.b2)-1);\n    } else {\n      tmp = (dat_be >> sig.bo) & ((1ULL << sig.b2)-1);\n    }\n\n    if (sig.is_signed) {\n      tmp -= (tmp >> (sig.b2-1)) ? (1ULL << sig.b2) : 0; //signed\n    }\n\n    DEBUG(\"parse 0x%X %s -> %lld\\n\", address, sig.name, tmp);\n\n    if (!ignore_checksum) {\n      if (sig.type == SignalType::HONDA_CHECKSUM) {\n        if (honda_checksum(address, dat_be, size) != tmp) {\n          INFO(\"0x%X CHECKSUM FAIL\\n\", address);\n          return false;\n        }\n      } else if (sig.type == SignalType::TOYOTA_CHECKSUM) {\n        if (toyota_checksum(address, dat_be, size) != tmp) {\n          INFO(\"0x%X CHECKSUM FAIL\\n\", address);\n          return false;\n        }\n      } else if (sig.type == SignalType::VOLKSWAGEN_CHECKSUM) {\n        if (volkswagen_crc(address, dat_le, size) != tmp) {\n          INFO(\"0x%X CRC FAIL\\n\", address);\n          return false;\n        }\n      } else if (sig.type == SignalType::SUBARU_CHECKSUM) {\n        if (subaru_checksum(address, dat_be, size) != tmp) {\n          INFO(\"0x%X CHECKSUM FAIL\\n\", address);\n          return false;\n        }\n      } else if (sig.type == SignalType::CHRYSLER_CHECKSUM) {\n        if (chrysler_checksum(address, dat_le, size) != tmp) {\n          INFO(\"0x%X CHECKSUM FAIL\\n\", address);\n          return false;\n        }\n      } else if (sig.type == SignalType::PEDAL_CHECKSUM) {\n        if (pedal_checksum(dat_be, size) != tmp) {\n          INFO(\"0x%X PEDAL CHECKSUM FAIL\\n\", address);\n          return false;\n        }\n      }\n    }\n    if (!ignore_counter) {\n      if (sig.type == SignalType::HONDA_COUNTER) {\n        if (!update_counter_generic(tmp, sig.b2)) {\n          return false;\n        }\n      } else if (sig.type == SignalType::VOLKSWAGEN_COUNTER) {\n          if (!update_counter_generic(tmp, sig.b2)) {\n          return false;\n        }\n      } else if (sig.type == SignalType::PEDAL_COUNTER) {\n        if (!update_counter_generic(tmp, sig.b2)) {\n          return false;\n        }\n      }\n    }\n\n    vals[i] = tmp * sig.factor + sig.offset;\n  }\n  ts = ts_;\n  seen = sec;\n\n  return true;\n}\n\n\nbool MessageState::update_counter_generic(int64_t v, int cnt_size) {\n  uint8_t old_counter = counter;\n  counter = v;\n  if (((old_counter+1) & ((1 << cnt_size) -1)) != v) {\n    counter_fail += 1;\n    if (counter_fail > 1) {\n      INFO(\"0x%X COUNTER FAIL %d -- %d vs %d\\n\", address, counter_fail, old_counter, (int)v);\n    }\n    if (counter_fail >= MAX_BAD_COUNTER) {\n      return false;\n    }\n  } else if (counter_fail > 0) {\n    counter_fail--;\n  }\n  return true;\n}\n\n\nCANParser::CANParser(int abus, const std::string& dbc_name,\n          const std::vector<MessageParseOptions> &options,\n          const std::vector<SignalParseOptions> &sigoptions)\n  : bus(abus), aligned_buf(kj::heapArray<capnp::word>(1024)) {\n\n  dbc = dbc_lookup(dbc_name);\n  assert(dbc);\n  init_crc_lookup_tables();\n\n  for (const auto& op : options) {\n    MessageState &state = message_states[op.address];\n    state.address = op.address;\n    // state.check_frequency = op.check_frequency,\n\n    // msg is not valid if a message isn't received for 10 consecutive steps\n    if (op.check_frequency > 0) {\n      state.check_threshold = (1000000000ULL / op.check_frequency) * 10;\n    }\n\n    const Msg* msg = NULL;\n    for (int i = 0; i < dbc->num_msgs; i++) {\n      if (dbc->msgs[i].address == op.address) {\n        msg = &dbc->msgs[i];\n        break;\n      }\n    }\n    if (!msg) {\n      fprintf(stderr, \"CANParser: could not find message 0x%X in DBC %s\\n\", op.address, dbc_name.c_str());\n      assert(false);\n    }\n\n    state.size = msg->size;\n\n    // track checksums and counters for this message\n    for (int i = 0; i < msg->num_sigs; i++) {\n      const Signal *sig = &msg->sigs[i];\n      if (sig->type != SignalType::DEFAULT) {\n        state.parse_sigs.push_back(*sig);\n        state.vals.push_back(0);\n      }\n    }\n\n    // track requested signals for this message\n    for (const auto& sigop : sigoptions) {\n      if (sigop.address != op.address) continue;\n\n      for (int i = 0; i < msg->num_sigs; i++) {\n        const Signal *sig = &msg->sigs[i];\n        if (strcmp(sig->name, sigop.name) == 0\n            && sig->type == SignalType::DEFAULT) {\n          state.parse_sigs.push_back(*sig);\n          state.vals.push_back(sigop.default_value);\n          break;\n        }\n      }\n    }\n  }\n}\n\nCANParser::CANParser(int abus, const std::string& dbc_name, bool ignore_checksum, bool ignore_counter)\n  : bus(abus) {\n  // Add all messages and signals\n\n  dbc = dbc_lookup(dbc_name);\n  assert(dbc);\n  init_crc_lookup_tables();\n\n  for (int i = 0; i < dbc->num_msgs; i++) {\n    const Msg* msg = &dbc->msgs[i];\n    MessageState state = {\n      .address = msg->address,\n      .size = msg->size,\n      .ignore_checksum = ignore_checksum,\n      .ignore_counter = ignore_counter,\n    };\n\n    for (int j = 0; j < msg->num_sigs; j++) {\n      const Signal *sig = &msg->sigs[j];\n      state.parse_sigs.push_back(*sig);\n      state.vals.push_back(0);\n    }\n\n    message_states[state.address] = state;\n  }\n}\n\n#ifndef DYNAMIC_CAPNP\nvoid CANParser::update_string(const std::string &data, bool sendcan) {\n  // format for board, make copy due to alignment issues.\n  const size_t buf_size = (data.length() / sizeof(capnp::word)) + 1;\n  if (aligned_buf.size() < buf_size) {\n    aligned_buf = kj::heapArray<capnp::word>(buf_size);\n  }\n  memcpy(aligned_buf.begin(), data.data(), data.length());\n\n  // extract the messages\n  capnp::FlatArrayMessageReader cmsg(aligned_buf.slice(0, buf_size));\n  cereal::Event::Reader event = cmsg.getRoot<cereal::Event>();\n\n  last_sec = event.getLogMonoTime();\n\n  auto cans = sendcan? event.getSendcan() : event.getCan();\n  UpdateCans(last_sec, cans);\n\n  UpdateValid(last_sec);\n}\n\nvoid CANParser::UpdateCans(uint64_t sec, const capnp::List<cereal::CanData>::Reader& cans) {\n  int msg_count = cans.size();\n\n  DEBUG(\"got %d messages\\n\", msg_count);\n\n  for (int i = 0; i < msg_count; i++) {\n    auto cmsg = cans[i];\n    // parse the messages\n    if (cmsg.getSrc() != bus) {\n      // DEBUG(\"skip %d: wrong bus\\n\", cmsg.getAddress());\n      continue;\n    }\n    auto state_it = message_states.find(cmsg.getAddress());\n    if (state_it == message_states.end()) {\n      // DEBUG(\"skip %d: not specified\\n\", cmsg.getAddress());\n      continue;\n    }\n\n    if (cmsg.getDat().size() > 8) continue; //shouldn't ever happen\n    uint8_t dat[8] = {0};\n    memcpy(dat, cmsg.getDat().begin(), cmsg.getDat().size());\n\n    state_it->second.parse(sec, cmsg.getBusTime(), dat);\n  }\n}\n#endif\n\nvoid CANParser::UpdateCans(uint64_t sec, const capnp::DynamicStruct::Reader& cmsg) {\n  // assume message struct is `cereal::CanData` and parse\n  assert(cmsg.has(\"address\") && cmsg.has(\"src\") && cmsg.has(\"dat\") && cmsg.has(\"busTime\"));\n\n  if (cmsg.get(\"src\").as<uint8_t>() != bus) {\n    DEBUG(\"skip %d: wrong bus\\n\", cmsg.get(\"address\").as<uint32_t>());\n    return;\n  }\n\n  auto state_it = message_states.find(cmsg.get(\"address\").as<uint32_t>());\n  if (state_it == message_states.end()) {\n    DEBUG(\"skip %d: not specified\\n\", cmsg.get(\"address\").as<uint32_t>());\n    return;\n  }\n\n  auto dat = cmsg.get(\"dat\").as<capnp::Data>();\n  if (dat.size() > 8) return; //shouldn't ever happen\n  uint8_t data[8] = {0};\n  memcpy(data, dat.begin(), dat.size());\n  state_it->second.parse(sec, cmsg.get(\"busTime\").as<uint16_t>(), data);\n}\n\nvoid CANParser::UpdateValid(uint64_t sec) {\n  can_valid = true;\n  for (const auto& kv : message_states) {\n    const auto& state = kv.second;\n    if (state.check_threshold > 0 && (sec - state.seen) > state.check_threshold) {\n      if (state.seen > 0) {\n        DEBUG(\"0x%X TIMEOUT\\n\", state.address);\n      } else {\n        DEBUG(\"0x%X MISSING\\n\", state.address);\n      }\n      can_valid = false;\n    }\n  }\n}\n\nstd::vector<SignalValue> CANParser::query_latest() {\n  std::vector<SignalValue> ret;\n\n  for (const auto& kv : message_states) {\n    const auto& state = kv.second;\n    if (last_sec != 0 && state.seen != last_sec) continue;\n\n    for (int i=0; i<state.parse_sigs.size(); i++) {\n      const Signal &sig = state.parse_sigs[i];\n      ret.push_back((SignalValue){\n        .address = state.address,\n        .ts = state.ts,\n        .name = sig.name,\n        .value = state.vals[i],\n      });\n    }\n  }\n\n  return ret;\n}\n"
  },
  {
    "path": "opendbc/can/parser.py",
    "content": "from opendbc.can.parser_pyx import CANParser, CANDefine  # pylint: disable=no-name-in-module, import-error\nassert CANParser, CANDefine\n"
  },
  {
    "path": "opendbc/can/parser_pyx.pyx",
    "content": "# distutils: language = c++\n# cython: c_string_encoding=ascii, language_level=3\n\nfrom libcpp.string cimport string\nfrom libcpp.vector cimport vector\nfrom libcpp.unordered_set cimport unordered_set\nfrom libc.stdint cimport uint32_t, uint64_t, uint16_t\nfrom libcpp.map cimport map\nfrom libcpp cimport bool\n\nfrom .common cimport CANParser as cpp_CANParser\nfrom .common cimport SignalParseOptions, MessageParseOptions, dbc_lookup, SignalValue, DBC\n\nimport os\nimport numbers\nfrom collections import defaultdict\n\ncdef int CAN_INVALID_CNT = 5\n\ncdef class CANParser:\n  cdef:\n    cpp_CANParser *can\n    const DBC *dbc\n    map[string, uint32_t] msg_name_to_address\n    map[uint32_t, string] address_to_msg_name\n    vector[SignalValue] can_values\n    bool test_mode_enabled\n\n  cdef readonly:\n    string dbc_name\n    dict vl\n    dict ts\n    bool can_valid\n    int can_invalid_cnt\n\n  def __init__(self, dbc_name, signals, checks=None, bus=0, enforce_checks=True):\n    if checks is None:\n      checks = []\n    checks = []\n    enforce_checks = False\n    self.can_valid = True\n    self.dbc_name = dbc_name\n    self.dbc = dbc_lookup(dbc_name)\n    if not self.dbc:\n      raise RuntimeError(f\"Can't find DBC: {dbc_name}\")\n    self.vl = {}\n    self.ts = {}\n\n    self.can_invalid_cnt = CAN_INVALID_CNT\n\n    cdef int i\n    cdef int num_msgs = self.dbc[0].num_msgs\n    for i in range(num_msgs):\n      msg = self.dbc[0].msgs[i]\n      name = msg.name.decode('utf8')\n\n      self.msg_name_to_address[name] = msg.address\n      self.address_to_msg_name[msg.address] = name\n      self.vl[msg.address] = {}\n      self.vl[name] = {}\n      self.ts[msg.address] = {}\n      self.ts[name] = {}\n\n    # Convert message names into addresses\n    for i in range(len(signals)):\n      s = signals[i]\n      if not isinstance(s[1], numbers.Number):\n        name = s[1].encode('utf8')\n        s = (s[0], self.msg_name_to_address[name], s[2])\n        signals[i] = s\n\n    for i in range(len(checks)):\n      c = checks[i]\n      if not isinstance(c[0], numbers.Number):\n        name = c[0].encode('utf8')\n        c = (self.msg_name_to_address[name], c[1])\n        checks[i] = c\n\n    if enforce_checks:\n      checked_addrs = {c[0] for c in checks}\n      signal_addrs = {s[1] for s in signals}\n      unchecked = signal_addrs - checked_addrs\n      if len(unchecked):\n        err_msg = ', '.join(f\"{self.address_to_msg_name[addr].decode()} ({hex(addr)})\" for addr in unchecked)\n        raise RuntimeError(f\"Unchecked addrs: {err_msg}\")\n\n    cdef vector[SignalParseOptions] signal_options_v\n    cdef SignalParseOptions spo\n    for sig_name, sig_address, sig_default in signals:\n      spo.address = sig_address\n      spo.name = sig_name\n      spo.default_value = sig_default\n      signal_options_v.push_back(spo)\n\n    message_options = dict((address, 0) for _, address, _ in signals)\n    message_options.update(dict(checks))\n\n    cdef vector[MessageParseOptions] message_options_v\n    cdef MessageParseOptions mpo\n    for msg_address, freq in message_options.items():\n      mpo.address = msg_address\n      mpo.check_frequency = freq\n      message_options_v.push_back(mpo)\n\n    self.can = new cpp_CANParser(bus, dbc_name, message_options_v, signal_options_v)\n    self.update_vl()\n\n  cdef unordered_set[uint32_t] update_vl(self):\n    cdef string sig_name\n    cdef unordered_set[uint32_t] updated_val\n\n    can_values = self.can.query_latest()\n    valid = self.can.can_valid\n\n    # Update invalid flag\n    self.can_invalid_cnt += 1\n    if valid:\n        self.can_invalid_cnt = 0\n    self.can_valid = self.can_invalid_cnt < CAN_INVALID_CNT\n\n    for cv in can_values:\n      # Cast char * directly to unicode\n      name = <unicode>self.address_to_msg_name[cv.address].c_str()\n      cv_name = <unicode>cv.name\n\n      self.vl[cv.address][cv_name] = cv.value\n      self.ts[cv.address][cv_name] = cv.ts\n\n      self.vl[name][cv_name] = cv.value\n      self.ts[name][cv_name] = cv.ts\n\n      updated_val.insert(cv.address)\n\n    return updated_val\n\n  def update_string(self, dat, sendcan=False):\n    self.can.update_string(dat, sendcan)\n    return self.update_vl()\n\n  def update_strings(self, strings, sendcan=False):\n    updated_vals = set()\n\n    for s in strings:\n      updated_val = self.update_string(s, sendcan)\n      updated_vals.update(updated_val)\n\n    return updated_vals\n\ncdef class CANDefine():\n  cdef:\n    const DBC *dbc\n\n  cdef public:\n    dict dv\n    string dbc_name\n\n  def __init__(self, dbc_name):\n    self.dbc_name = dbc_name\n    self.dbc = dbc_lookup(dbc_name)\n    if not self.dbc:\n      raise RuntimeError(f\"Can't find DBC: '{dbc_name}'\")\n\n    num_vals = self.dbc[0].num_vals\n\n    address_to_msg_name = {}\n\n    num_msgs = self.dbc[0].num_msgs\n    for i in range(num_msgs):\n      msg = self.dbc[0].msgs[i]\n      name = msg.name.decode('utf8')\n      address = msg.address\n      address_to_msg_name[address] = name\n\n    dv = defaultdict(dict)\n\n    for i in range(num_vals):\n      val = self.dbc[0].vals[i]\n\n      sgname = val.name.decode('utf8')\n      def_val = val.def_val.decode('utf8')\n      address = val.address\n      msgname = address_to_msg_name[address]\n\n      # separate definition/value pairs\n      def_val = def_val.split()\n      values = [int(v) for v in def_val[::2]]\n      defs = def_val[1::2]\n\n\n      # two ways to lookup: address or msg name\n      dv[address][sgname] = dict(zip(values, defs))\n      dv[msgname][sgname] = dv[address][sgname]\n\n      self.dv = dict(dv)\n"
  },
  {
    "path": "opendbc/can/process_dbc.py",
    "content": "#!/usr/bin/env python3\nfrom __future__ import print_function\nimport os\nimport sys\n\nimport jinja2\n\nfrom collections import Counter\nfrom opendbc.can.dbc import dbc\n\ndef process(in_fn, out_fn):\n  dbc_name = os.path.split(out_fn)[-1].replace('.cc', '')\n  # print(\"processing %s: %s -> %s\" % (dbc_name, in_fn, out_fn))\n\n  template_fn = os.path.join(os.path.dirname(__file__), \"dbc_template.cc\")\n\n  with open(template_fn, \"r\") as template_f:\n    template = jinja2.Template(template_f.read(), trim_blocks=True, lstrip_blocks=True)\n\n  can_dbc = dbc(in_fn)\n\n  # process counter and checksums first\n  msgs = [(address, msg_name, msg_size, sorted(msg_sigs, key=lambda s: s.name not in (\"COUNTER\", \"CHECKSUM\")))\n          for address, ((msg_name, msg_size), msg_sigs) in sorted(can_dbc.msgs.items()) if msg_sigs]\n\n  def_vals = {a: sorted(set(b)) for a, b in can_dbc.def_vals.items()}  # remove duplicates\n  def_vals = sorted(def_vals.items())\n\n  if can_dbc.name.startswith((\"honda_\", \"acura_\")):\n    checksum_type = \"honda\"\n    checksum_size = 4\n    counter_size = 2\n    checksum_start_bit = 3\n    counter_start_bit = 5\n    little_endian = False\n  elif can_dbc.name.startswith((\"toyota_\", \"lexus_\")):\n    checksum_type = \"toyota\"\n    checksum_size = 8\n    counter_size = None\n    checksum_start_bit = 7\n    counter_start_bit = None\n    little_endian = False\n  elif can_dbc.name.startswith((\"vw_\", \"volkswagen_\", \"audi_\", \"seat_\", \"skoda_\")):\n    checksum_type = \"volkswagen\"\n    checksum_size = 8\n    counter_size = 4\n    checksum_start_bit = 0\n    counter_start_bit = 0\n    little_endian = True\n  elif can_dbc.name.startswith((\"subaru_global_\")):\n    checksum_type = \"subaru\"\n    checksum_size = 8\n    counter_size = None\n    checksum_start_bit = 0\n    counter_start_bit = None\n    little_endian = True\n  elif can_dbc.name.startswith((\"chrysler_\")):\n    checksum_type = \"chrysler\"\n    checksum_size = 8\n    counter_size = None\n    checksum_start_bit = 7\n    counter_start_bit = None\n    little_endian = False\n  else:\n    checksum_type = None\n    checksum_size = None\n    counter_size = None\n    checksum_start_bit = None\n    counter_start_bit = None\n    little_endian = None\n\n  # sanity checks on expected COUNTER and CHECKSUM rules, as packer and parser auto-compute those signals\n  for address, msg_name, _, sigs in msgs:\n    dbc_msg_name = dbc_name + \" \" + msg_name\n    for sig in sigs:\n      if checksum_type is not None:\n        # checksum rules\n        if sig.name == \"CHECKSUM\":\n          if sig.size != checksum_size:\n            sys.exit(\"%s: CHECKSUM is not %d bits long\" % (dbc_msg_name, checksum_size))\n          if sig.start_bit % 8 != checksum_start_bit:\n            sys.exit(\"%s: CHECKSUM starts at wrong bit\" % dbc_msg_name)\n          if little_endian != sig.is_little_endian:\n            sys.exit(\"%s: CHECKSUM has wrong endianness\" % dbc_msg_name)\n        # counter rules\n        if sig.name == \"COUNTER\":\n          if counter_size is not None and sig.size != counter_size:\n            sys.exit(\"%s: COUNTER is not %d bits long\" % (dbc_msg_name, counter_size))\n          if counter_start_bit is not None and sig.start_bit % 8 != counter_start_bit:\n            print(counter_start_bit, sig.start_bit)\n            sys.exit(\"%s: COUNTER starts at wrong bit\" % dbc_msg_name)\n          if little_endian != sig.is_little_endian:\n            sys.exit(\"%s: COUNTER has wrong endianness\" % dbc_msg_name)\n      # pedal rules\n      if address in [0x200, 0x201]:\n        if sig.name == \"COUNTER_PEDAL\" and sig.size != 4:\n          sys.exit(\"%s: PEDAL COUNTER is not 4 bits long\" % dbc_msg_name)\n        if sig.name == \"CHECKSUM_PEDAL\" and sig.size != 8:\n          sys.exit(\"%s: PEDAL CHECKSUM is not 8 bits long\" % dbc_msg_name)\n\n  # Fail on duplicate message names\n  c = Counter([msg_name for address, msg_name, msg_size, sigs in msgs])\n  for name, count in c.items():\n    if count > 1:\n      sys.exit(\"%s: Duplicate message name in DBC file %s\" % (dbc_name, name))\n\n  parser_code = template.render(dbc=can_dbc, checksum_type=checksum_type, msgs=msgs, def_vals=def_vals, len=len)\n\n  with open(out_fn, \"a+\") as out_f:\n    out_f.seek(0)\n    if out_f.read() != parser_code:\n      out_f.seek(0)\n      out_f.truncate()\n      out_f.write(parser_code)\n\ndef main():\n  if len(sys.argv) != 3:\n    print(\"usage: %s dbc_directory output_filename\" % (sys.argv[0],))\n    sys.exit(0)\n\n  dbc_dir = sys.argv[1]\n  out_fn = sys.argv[2]\n\n  dbc_name = os.path.split(out_fn)[-1].replace('.cc', '')\n  in_fn = os.path.join(dbc_dir, dbc_name + '.dbc')\n\n  process(in_fn, out_fn)\n\n\nif __name__ == '__main__':\n  main()\n"
  },
  {
    "path": "opendbc/chrysler_pacifica_2017_hybrid.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\n\nBO_ 258 STEERING: 8 XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ UNKNOWN_STEERING : 50|3@0+ (1,0) [0|15] \"\" XXX\n SG_ STEERING_RATE : 20|13@0+ (0.3187251,-1305.498) [0|8191] \"deg/s\" XXX\n SG_ STEER_ANGLE : 4|13@0+ (0.3187251,-1307.888) [-360|360] \"deg\" XXX\n\nBO_ 514 SPEED_1: 8 XXX\n SG_ SPEED_LEFT : 7|12@0+ (0.071028,0) [0|65535] \"m/s\" XXX\n SG_ SPEED_RIGHT : 23|12@0+ (0.071028,0) [0|1023] \"m/s\" XXX\n\nBO_ 653 BRAKE_MODULE: 2 XXX\n SG_ BRAKE_PRESSURE : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PRESSED : 4|1@0+ (1,0) [0|4] \"\" XXX\n\nBO_ 820 DOORS: 8 XXX\n SG_ DOOR_OPEN_FR : 18|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_TRUNK : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ TURN_LIGHT_LEFT : 31|1@0+ (1,0) [0|1] \"\" XXX\n SG_ TURN_LIGHT_RIGHT : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM_DISPLAY : 58|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 746 GEAR: 5 XXX\n SG_ PRNDL : 2|3@0+ (1,0) [0|7] \"\" XXX\n SG_ GEAR_CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 31|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 284 BRAKE_1: 8 XXX\n SG_ SPEED_RELATED_1 : 37|14@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_RELATED_1_2 : 18|11@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_RELATED_1_1 : 3|12@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 320 BRAKE_2: 8 XXX\n SG_ SPEED_RELATED_2 : 47|8@0+ (1,0) [0|63] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PRESSED_2 : 2|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_PRESSED_ACC : 6|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 736 TRIP: 8 XXX\n SG_ COUNTER : 7|16@0+ (1,0) [0|65535] \"Meters\" XXX\n SG_ COUNTER_2 : 23|16@0+ (1,0) [0|65535] \"Meters\" XXX\n\nBO_ 344 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FL : 3|12@0+ (0.0189408,0) [0|65535] \"m/s\" XXX\n SG_ WHEEL_SPEED_RR : 51|12@0+ (0.0189408,0) [0|255] \"m/s\" XXX\n SG_ WHEEL_SPEED_RL : 35|12@0+ (0.0189408,0) [0|3] \"m/s\" XXX\n SG_ WHEEL_SPEED_FR : 19|12@0+ (0.0189408,0) [0|255] \"m/s\" XXX\n\nBO_ 792 STEERING_LEVERS: 8 XXX\n SG_ HIGH_BEAM_PUSHED_IN : 2|1@0+ (1,0) [0|3] \"\" XXX\n SG_ TURN_SIGNALS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HIGH_BEAM_FLASH : 3|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 264 ACCEL_PEDAL_MSG: 8 XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_PEDAL : 35|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 464 SEATBELT_STATUS: 8 XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 13|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 544 EPS_STATUS: 8 XXX\n SG_ LKAS_STATE : 23|4@0+ (1,0) [0|15] \"\" XXX\n SG_ TORQUE_DRIVER : 2|11@0+ (1,-1024) [-1024|1023] \"\" XXX\n SG_ TORQUE_MOTOR_RAW : 19|12@0+ (1,-2048) [-2048|2047] \"\" XXX\n SG_ TORQUE_MOTOR : 34|11@0+ (1,-1024) [-1024|1023] \"\" XXX\n SG_ AUTO_PARK_HAS_CONTROL_2 : 51|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 658 LKAS_COMMAND: 6 XXX\n SG_ COUNTER : 39|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LKAS_STEERING_TORQUE : 2|11@0+ (1,-1024) [0|1] \"\" XXX\n SG_ LKAS_HIGH_TORQUE : 4|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 678 LKAS_HUD: 8 XXX\n SG_ LKAS_ICON_COLOR : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LKAS_LANE_LINES : 19|4@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_ALERTS : 27|4@0+ (1,0) [0|1] \"\" XXX\n SG_ CAR_MODEL : 15|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 705 AUTO_PARK_BUTTON: 8 XXX\n SG_ AUTO_PARK_TOGGLE_2 : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AUTO_PARK_TOGGLE_1 : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ INCREASING_UNKNOWN : 38|7@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 719 AUTO_PARK_SIGNALS_1: 8 XXX\n SG_ AUTO_PARK_UNKNOWN_1 : 7|16@0+ (1,0) [0|31] \"\" XXX\n\nBO_ 671 AUTO_PARK_REQUEST: 8 XXX\n SG_ AUTO_PARK_CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ AUTO_PARK_STATUS : 7|5@0+ (1,0) [0|15] \"\" XXX\n SG_ AUTO_PARK_COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ AUTO_PARK_MODE : 22|2@0+ (1,0) [0|3] \"\" XXX\n SG_ AUTO_PARK_CMD : 2|11@0+ (1,-1024) [0|1] \"NM\" XXX\n\nBO_ 784 AUTO_PARK_LESS_INTERESTING: 8 XXX\n SG_ INCREASING_UNKNOWN : 55|8@0+ (1,0) [0|7] \"\" XXX\n SG_ AUTO_PARK_PERPENDICULAR_2 : 61|1@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 826 AUTO_PARK_SIGNALS_3: 8 XXX\n SG_ AUTO_PARK_HAS_CONTROL_3 : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUMAN_HAS_CONTROL : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AUTO_PARK_GEAR_1 : 27|4@0+ (1,0) [0|255] \"\" XXX\n SG_ AUTO_PARK_GEAR_2 : 35|4@0+ (1,0) [0|15] \"\" XXX\n SG_ AUTO_PARK_GEAR_3 : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 332 STEERING_2: 8 XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ENERGY_RELATED : 39|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ STEER_ANGLE_2 : 7|13@0+ (0.3187251,-1307.888) [-360|360] \"deg\" XXX\n\nBO_ 720 BLIND_SPOT_WARNINGS: 6 XXX\n SG_ BLIND_SPOT_RIGHT : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BLIND_SPOT_LEFT : 2|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 331 BRAKE_3: 8 XXX\n SG_ BRAKE_RELATED_3 : 7|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 608 PARKSENSE_SIGNAL: 8 XXX\n SG_ PARKSENSE_DISABLED : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ IN_REVERSE : 10|1@0+ (1,0) [0|255] \"\" XXX\n SG_ AUTO_PARK_HAS_CONTROL_1 : 16|1@0+ (1,0) [0|255] \"\" XXX\n SG_ HUMAN_HAS_CONTROL : 17|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 729 LKAS_HEARTBIT: 5 XXX\n SG_ LKAS_STATUS_OK : 31|16@0+ (1,0) [0|65535] \"\" XXX\n\nBO_ 274 NEW_MSG_112: 2 XXX\n\nBO_ 290 NEW_MSG_122: 6 XXX\n\nBO_ 376 NEW_MSG_178: 3 XXX\n\nBO_ 288 ACCEL_RELATED_120: 7 XXX\n SG_ COUNTER : 47|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ GAS_ENGINE_RPM_MAYBE : 31|16@0+ (1,0) [0|65535] \"\" XXX\n\nBO_ 257 ACCEL_RELATED_101: 5 XXX\n SG_ ENERGY_OR_RPM : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 388 NEW_MSG_184: 4 XXX\n\nBO_ 448 NEW_MSG_1c0: 6 XXX\n\nBO_ 456 NEW_MSG_1c8: 4 XXX\n\nBO_ 560 NEW_MSG_230: 4 XXX\n\nBO_ 564 NEW_MSG_234: 4 XXX\n\nBO_ 571 WHEEL_BUTTONS: 3 XXX\n SG_ CHECKSUM : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACC_FOLLOW_DEC : 1|1@0+ (1,0) [0|3] \"\" XXX\n SG_ ACC_SPEED_INC : 2|1@0+ (1,0) [0|255] \"\" XXX\n SG_ ACC_SPEED_DEC : 3|1@0+ (1,0) [0|3] \"\" XXX\n SG_ ACC_FOLLOW_INC : 8|1@0+ (1,0) [0|15] \"\" XXX\n SG_ ACC_CANCEL : 0|1@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 15|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ACC_RESUME : 4|1@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 669 NEW_MSG_29d: 3 XXX\n SG_ COUNTER : 15|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 825 AUDIBLE_BEEP_339: 2 XXX\n SG_ BEEP_339 : 7|16@0+ (1,0) [0|65535] \"\" XXX\n\nBO_ 856 NEW_MSG_358: 4 XXX\n\nBO_ 860 NEW_MSG_35c: 6 XXX\n\nBO_ 924 NEW_MSG_39c: 3 XXX\n\nBO_ 969 NEW_MSG_3c9: 4 XXX\n\nBO_ 974 NEW_MSG_3ce: 5 XXX\n\nBO_ 993 NEW_MSG_3e1: 7 XXX\n\nBO_ 838 NEW_MSG_346: 2 XXX\n\nBO_ 926 NEW_MSG_39e: 3 XXX\n\nBO_ 168 ACCEL_RELATED_a8: 8 XXX\n SG_ ACCEL_RELATED : 23|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 270 ACCEL_RELATED_10e: 8 XXX\n SG_ ACCEL_OR_RPM : 7|16@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ELECTRIC_MOTOR : 23|16@0+ (1,0) [0|65535] \"\" XXX\n\nBO_ 291 ENERGY_RELATED_123: 8 XXX\n SG_ ENERGY_GAIN_LOSS : 18|11@0- (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ENERGY_SMOOTHER_CURVE : 35|12@0+ (1,0) [0|2047] \"\" XXX\n\nBO_ 294 ENERGY_RELATED_126: 8 XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ UNKNOWN_126_1 : 3|12@0+ (1,0) [0|4095] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ UNKNOWN_126_2 : 35|12@0+ (1,0) [0|4095] \"\" XXX\n SG_ ENERGY_GAIN_LOSS_NOISY : 19|12@0+ (1,0) [0|2047] \"\" XXX\n\nBO_ 300 NEW_MSG_12C: 8 XXX\n\nBO_ 308 ACCEL_GAS_134: 8 XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ACCEL_134 : 46|7@0+ (1,0) [0|127] \"\" XXX\n\nBO_ 532 ENERGY_RELATED_214: 8 XXX\n SG_ NOISY_SLOWLY_DECREASING : 16|9@0+ (1,0) [0|255] \"\" XXX\n SG_ ENERGY_RELATED : 0|9@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 559 ACCEL_GAS_22F: 8 XXX\n SG_ ACCEL_22F : 3|4@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 655 CHARGING_MAYBE_28F: 8 XXX\n SG_ CHARGING : 1|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 660 BRAKE_RELATED_294: 8 XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PERHAPS_294 : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 764 ACCEL_RELATED_2FC: 8 XXX\n SG_ ACCEL_2FC : 13|6@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 816 TRACTION_BUTTON: 8 XXX\n SG_ TRACTION_OFF : 19|1@0+ (1,0) [0|3] \"\" XXX\n SG_ TOGGLE_PARKSENSE : 52|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 878 ACCEL_RELATED_36E: 8 XXX\n SG_ ACCEL_OR_RPM_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_OR_RPM_1 : 7|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 324 SPEED_2: 8 XXX\n SG_ SPEED_2 : 31|16@0+ (0.01,0) [0|255] \"m/s\" XXX\n\nBO_ 501 DASHBOARD: 8 XXX\n SG_ ACC_SPEED_CONFIG_KPH : 15|8@0+ (1,0) [0|3] \"km/h\" XXX\n SG_ ACC_SPEED_CONFIG_MPH : 23|8@0+ (1,0) [0|3] \"mph\" XXX\n SG_ ACC_DISTANCE_CONFIG_1 : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ACC_DISTANCE_CONFIG_2 : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SPEED_DIGITAL : 63|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CRUISE_STATE : 38|3@0+ (1,0) [0|7] \"\" XXX\n\nBO_ 639 NEW_MSG_27f: 8 XXX\n SG_ INCREASING : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 701 NEW_MSG_2bd: 8 XXX\n SG_ unknown_1 : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 832 UNKNOWN_340: 8 XXX\n SG_ SPEED_DIGITAL : 63|8@0+ (1,0) [0|255] \"mph\" XXX\n\nBO_ 848 UNKNOWN_350: 8 XXX\n SG_ INCREASING_LSB : 5|6@0+ (1,0) [0|255] \"\" XXX\n SG_ INCREASING_MSB : 12|5@0+ (1,0) [0|31] \"\" XXX\n\nBO_ 908 NEW_MSG_38c: 8 XXX\n SG_ INCREASING_MSB : 44|5@0+ (1,0) [0|31] \"\" XXX\n SG_ INCREASING_LSB : 61|6@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 938 NEW_MSG_3aa: 8 XXX\n SG_ INCREASING_UNKNOWN_1 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ INCREASING_UNKNOWN_2 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 940 NEW_MSG_3ac: 8 XXX\n SG_ INCREASING_1 : 35|4@0+ (1,0) [0|15] \"\" XXX\n SG_ INCREASING_2 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 941 NEW_MSG_3ad: 8 XXX\n SG_ INCREASING_1 : 36|5@0+ (1,0) [0|31] \"\" XXX\n SG_ INCREASING_2 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 500 ACC_2: 8 XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ACC_STATUS_1 : 7|3@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_MAYBE : 18|11@0+ (1,0) [0|255] \"\" XXX\n SG_ ACC_STATUS_2 : 21|3@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_BOOL_1 : 36|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 625 ACC_1: 8 XXX\n SG_ SPEED : 31|8@0+ (1,0) [0|255] \"km/h\" XXX\n SG_ ACCEL_PERHAPS : 39|16@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 268 ACC_10c: 8 XXX\n SG_ BRAKE_PERHAPS : 48|1@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 384 NEW_MSG_180: 8 XXX\n SG_ NEW_SIGNAL_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 39|8@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 853 NEW_MSG_355: 8 XXX\n\nBO_ 939 NEW_MSG_3ab: 8 XXX\n\nBO_ 512 NEW_MSG_200: 8 XXX\n SG_ NEW_SIGNAL_1 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ INCREASING : 27|12@0+ (1,0) [0|127] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\n\n\n\nCM_ SG_ 258 UNKNOWN_STEERING \"never goes above 4. see if human-applied torque\";\nCM_ SG_ 258 STEER_ANGLE \"positive is left (counter-clockwise)\";\nCM_ SG_ 514 SPEED_LEFT \"TODO find upper limit\";\nCM_ SG_ 653 BRAKE_PRESSURE \"max seems to be 148\";\nCM_ SG_ 820 TURN_LIGHT_LEFT \"oscillates with the light blinking\";\nCM_ SG_ 820 TURN_LIGHT_RIGHT \"hazard blinks both right and left lights\";\nCM_ SG_ 746 PRNDL \"5=L, 4=D, 3=N, 2=R, 1=P\";\nCM_ SG_ 746 GEAR_CHECKSUM \"different than the LKAS checksum. unknown non-simple algorithm. just build a lookup table for it.\";\nCM_ SG_ 284 SPEED_RELATED_1 \"Another Speed Signal, Maybe RPMs?\";\nCM_ SG_ 284 BRAKE_RELATED_1_1 \"Correlates with braking\";\nCM_ SG_ 320 BRAKE_PRESSED_2 \"Value is 5 when brake is pressed by human, 1 when ACC brake\";\nCM_ SG_ 320 BRAKE_PRESSED_ACC \"set when ACC brakes\";\nCM_ SG_ 792 TURN_SIGNALS \"1=Left, 2=Right\";\nCM_ SG_ 792 HIGH_BEAM_FLASH \"use this for genericToggle\";\nCM_ SG_ 264 ACCEL_PEDAL \"not in ACC so seems to be actual pedal. Use for gasPressed\";\nCM_ SG_ 544 LKAS_STATE \"2 when autopark has control, 8 when is actuatable by lkas, 4 when there is a fault\";\nCM_ SG_ 544 TORQUE_MOTOR_RAW \"has larger range than TORQUE_MOTOR but ut seems biased\";\nCM_ SG_ 658 COUNTER \"each message increments, 0..f\";\nCM_ SG_ 658 CHECKSUM \"checksum calculated with https://gist.github.com/adhintz/94bf8d19b9075539f50172ab0fb24ba1\";\nCM_ SG_ 658 LKAS_STEERING_TORQUE \"Most sent by stock system is 1024+-230. + is left. typically changes by 2 or 3 each 0.01s\";\nCM_ SG_ 678 LKAS_ICON_COLOR \"3 is yellow, 2 is green, 1 is white, 0 is null\";\nCM_ SG_ 678 LKAS_LANE_LINES \"0x01 transparent lines, 0x02 left white, 0x03 right white, 0x04 left yellow with car on top, 0x05 left yellow with car on top, 0x06 both white, 0x07 left yellow, 0x08 left yellow right white, 0x09 right yellow, 0x0a right yellow left white, 0x0b left yellow with car on top right white, 0x0c right yellow with car on top left white, (0x00, 0x0d, 0x0e, 0x0f) null\";\nCM_ SG_ 678 LKAS_ALERTS \"(0x01, 0x02) lane sense off, (0x03, 0x04, 0x06) place hands on steering wheel, 0x07 lane departure detected + place hands on steering wheel, (0x08, 0x09) lane sense unavailable + clean front windshield, 0x0b lane sense and auto high beam unavailable + clean front windshield, 0x0c lane sense unavailable + service required, (0x00, 0x05, 0x0a, 0x0d, 0x0e, 0x0f) null\";\nCM_ SG_ 705 AUTO_PARK_TOGGLE_1 \"set briefly when turning on or off self-parking\";\nCM_ SG_ 705 INCREASING_UNKNOWN \"sometimes decreasing\";\nCM_ SG_ 671 AUTO_PARK_CMD \"Request Appears to be in NM\";\nCM_ SG_ 671 AUTO_PARK_STATUS \"1 = IDLE / NO REQUEST 9 = START REQUEST 10 = REQUEST MODE 11 = REQUEST MODE\";\nCM_ SG_ 784 INCREASING_UNKNOWN \"perhaps distance traveled\";\nCM_ SG_ 826 AUTO_PARK_GEAR_1 \"Reverse=0, Forward=f\";\nCM_ SG_ 826 AUTO_PARK_GEAR_2 \"Reverse=0, Forward=f\";\nCM_ SG_ 826 AUTO_PARK_GEAR_3 \"Reverse=0, Forward=f\";\nCM_ SG_ 332 STEER_ANGLE_2 \"slightly lags the other steer_angle signal. also more noisy.\";\nCM_ SG_ 720 BLIND_SPOT_RIGHT \"yellow triangle alert on side view mirror when a car is in your blind spot\";\nCM_ SG_ 608 PARKSENSE_DISABLED \"set if parksense is disabled\";\nCM_ SG_ 729 LKAS_STATUS_OK \"Set to 0x0820 when LKAS system is plugged in.\";\nCM_ SG_ 288 UNKNOWN_CHECKSUM \"not the LKAS checksum\";\nCM_ SG_ 288 GAS_ENGINE_RPM_MAYBE \"lags acceleration, perhaps gas engine\";\nCM_ SG_ 257 ENERGY_OR_RPM \"perhaps energy consumption or RPMs\";\nCM_ SG_ 571 CHECKSUM \"standard checksum\";\nCM_ SG_ 825 BEEP_339 \"sent every 0.5s. 0050 is no beep. To beep send 4355 or 4155. Used by ParkSense warning.\";\nCM_ SG_ 270 ELECTRIC_MOTOR \"0x7fff indicates electric motor not in use\";\nCM_ SG_ 291 ENERGY_GAIN_LOSS \"unsure what this actually is\";\nCM_ SG_ 291 ENERGY_SMOOTHER_CURVE \"unsure what it is, but smoother\";\nCM_ SG_ 308 ACCEL_134 \"only set when human presses accel pedal\";\nCM_ SG_ 532 NOISY_SLOWLY_DECREASING \"perhaps battery but do not know\";\nCM_ SG_ 816 TRACTION_OFF \"set when traction off button is enabled\";\nCM_ SG_ 816 TOGGLE_PARKSENSE \"sending 3000071ec0ff9000 enables or disables parksense\";\nCM_ SG_ 324 SPEED_2 \"signal is approx half other speeds\";\nCM_ SG_ 501 ACC_SPEED_CONFIG_KPH \"speed configured for ACC\";\nCM_ SG_ 501 ACC_SPEED_CONFIG_MPH \"speed configured for ACC\";\nCM_ SG_ 639 INCREASING \"perhaps number of seconds divided by two for this drive\";\nCM_ SG_ 848 INCREASING_LSB \"lower part of time counter\";\nCM_ SG_ 848 INCREASING_MSB \"upper part of time counter\";\nCM_ SG_ 908 INCREASING_MSB \"time based\";\nCM_ SG_ 500 ACC_STATUS_1 \"2 briefly (9 packets) when ACC goes to green, 1 help when ACC coming to a stop and at a stop\";\nCM_ SG_ 500 BRAKE_MAYBE \"2046 in non-ACC and non-decel. Signal on deceleration. 818 for already stopped break.\";\nCM_ SG_ 500 ACC_STATUS_2 \"set to 1 in non-ACC, 3 when ACC enabled (white icon), and 7 when ACC in use (green icon)\";\nCM_ SG_ 500 BRAKE_BOOL_1 \"set to 1 when ACC decel. 0 on non-ACC and accel.\";\nCM_ SG_ 501 CRUISE_STATE \"may just be an icon, but seems to indicate different cruise modes: ACC and Non-ACC and engaged state for both.\";\nCM_ SG_ 625 SPEED \"zero on non-acc drives\";\nCM_ SG_ 625 ACCEL_PERHAPS \"set to 7767 on non-ACC drives. ACC drive 40k is constant speed, 42k is accelerating\";\nCM_ SG_ 268 BRAKE_PERHAPS \"triggers only on ACC braking\";\nCM_ SG_ 384 NEW_SIGNAL_1 \"set in ACC gas driving. not set in electric human. not sure about gas human driving.\";\nVAL_ 501 CRUISE_STATE 0 \"Off\" 1 \"CC On\" 2 \"CC Engaged\" 3 \"ACC On\" 4 \"ACC Engaged\";\nVAL_ 746 PRNDL 5 \"L\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 792 TURN_SIGNALS 2 \"Right\" 1 \"Left\" ;\n"
  },
  {
    "path": "opendbc/chrysler_pacifica_2017_hybrid_private_fusion.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\n\nBO_ 544 a_1: 8 XXX\n SG_ track_id : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_ACCEL : 3|12@0+ (1,0) [0|31] \"\" XXX\n SG_ status1 : 23|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_SPEED : 19|12@0+ (1,0) [0|65535] \"\" XXX\n SG_ status2 : 39|6@0+ (1,0) [0|15] \"\" XXX\n SG_ sig2 : 33|10@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 576 b_1: 8 XXX\n SG_ sig0 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ sig1 : 15|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ sig2 : 31|16@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 47|12@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 608 a_2: 8 XXX\n SG_ track_id : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_ACCEL : 3|12@0+ (1,0) [0|31] \"\" XXX\n SG_ status1 : 23|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_SPEED : 19|12@0+ (1,0) [0|65535] \"\" XXX\n SG_ status2 : 39|6@0+ (1,0) [0|15] \"\" XXX\n SG_ sig2 : 33|10@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 640 b_2: 8 XXX\n SG_ sig0 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ sig1 : 15|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ sig2 : 31|16@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 47|12@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 644 a_3: 8 XXX\n SG_ track_id : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_ACCEL : 3|12@0+ (1,0) [0|31] \"\" XXX\n SG_ status1 : 23|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_SPEED : 19|12@0+ (1,0) [0|65535] \"\" XXX\n SG_ status2 : 39|6@0+ (1,0) [0|15] \"\" XXX\n SG_ sig2 : 33|10@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 648 b_3: 8 XXX\n SG_ sig0 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ sig1 : 15|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ sig2 : 31|16@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 47|12@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 652 a_4: 8 XXX\n SG_ track_id : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_ACCEL : 3|12@0+ (1,0) [0|31] \"\" XXX\n SG_ status1 : 23|4@0+ (1,0) [0|15] \"\" XXX\n SG_ REL_SPEED : 19|12@0+ (1,0) [0|65535] \"\" XXX\n SG_ status2 : 39|6@0+ (1,0) [0|15] \"\" XXX\n SG_ sig2 : 33|10@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 656 b_4: 8 XXX\n SG_ sig0 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ sig1 : 15|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ sig2 : 31|16@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros : 47|12@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 512 unknown_200: 8 XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ increasing : 31|16@0+ (1,0) [0|255] \"\" XXX\n SG_ zeros_0 : 3|12@0+ (1,0) [0|63] \"\" XXX\n SG_ zeros_1 : 47|12@0+ (1,0) [0|63] \"\" XXX\n SG_ status0 : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ unknown_0 : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 514 unknown_202: 8 XXX\n SG_ COUNTER : 43|4@0+ (1,0) [0|15] \"\" XXX\n SG_ sig3 : 31|8@0+ (1,0) [0|65535] \"\" XXX\n SG_ increasing : 39|12@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 706 c_1: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n\nBO_ 708 c_2: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 710 c_3: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 712 c_4: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 714 c_5: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 716 c_6: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 718 c_7: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 720 c_8: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 722 c_9: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 724 c_10: 8 XXX\n SG_ LAT_DIST : 18|11@0+ (0.005,-1000) [0|2047] \"m\" XXX\n SG_ LONG_DIST : 34|11@0+ (0.073,0) [0|255] \"m\" XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 674 d_1: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 676 d_2: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 678 d_3: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 680 d_4: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 682 d_5: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 684 d_6: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 686 d_7: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 688 d_8: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 690 d_9: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 692 d_10: 8 XXX\n SG_ REL_SPEED : 17|10@0+ (0.2857,-146.278) [0|1023] \"m/s\" XXX\n\nBO_ 672 NEW_MSG_5: 8 XXX\n SG_ NEW_SIGNAL_1 : 9|10@0+ (1,0) [0|1023] \"\" XXX\n SG_ NEW_SIGNAL_2 : 45|10@0+ (1,0) [0|1023] \"\" XXX\n\n\n\n\nCM_ SG_ 544 track_id \"for message a_1 track_id is always 1, similar for other messages and track_id\";\nCM_ SG_ 544 REL_ACCEL \"perhaps REL_ACCEL because it responds faster and before REL_SPEED\";\nCM_ SG_ 544 sig2 \"perhaps distance to object. LONG_DIST or REL_ACCEL or REL_SPEED\";\nCM_ SG_ 576 zeros \"not always zero, sometimes has value when another car changes lanes\";\nCM_ SG_ 706 LAT_DIST \"positive is to the right, negative is to the left\";\n"
  },
  {
    "path": "opendbc/ford_fusion_2018_adas.dbc",
    "content": "VERSION \"\"\n\n\nNS_ : \n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\nBO_ 1280 Object_00: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1281 Object_01: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1282 Object_02: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1283 Object_03: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1284 Object_04: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1285 Object_05: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1286 Object_06: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1287 Object_07: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1288 Object_08: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1289 Object_09: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1290 Object_10: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1291 Object_11: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1292 Object_12: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1293 Object_13: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1294 Object_14: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1295 Object_15: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1296 Object_16: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1297 Object_17: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1298 Object_18: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1299 Object_19: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1300 Object_20: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1301 Object_21: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1302 Object_22: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1303 Object_23: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1304 Object_24: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1305 Object_25: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1306 Object_26: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1307 Object_27: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1308 Object_28: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1309 Object_29: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1310 Object_30: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1311 Object_31: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1312 Object_32: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1313 Object_33: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1314 Object_34: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1315 Object_35: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1316 Object_36: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1317 Object_37: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1318 Object_38: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1319 Object_39: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1320 Object_40: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1321 Object_41: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1322 Object_42: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1323 Object_43: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1324 Object_44: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1325 Object_45: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1326 Object_46: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1327 Object_47: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1328 Object_48: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1329 Object_49: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1330 Object_50: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1331 Object_51: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1332 Object_52: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1333 Object_53: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1334 Object_54: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1335 Object_55: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1336 Object_56: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1337 Object_57: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1338 Object_58: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1339 Object_59: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1340 Object_60: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1341 Object_61: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1342 Object_62: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\nBO_ 1343 Object_63: 8 XXX\n SG_ X_Rel : 18|11@0+ (0.1,0) [0|0] \"m\" XXX\n SG_ V_Rel : 52|13@0- (0.01,0) [0|0] \"m/s\" XXX\n SG_ A_Rel : 33|10@0- (0.05,0) [0|0] \"m/s2\" XXX\n SG_ Angle : 12|10@0- (-0.1,0) [0|0] \"deg\" XXX\n\n"
  },
  {
    "path": "opendbc/ford_fusion_2018_pt.dbc",
    "content": "VERSION \"\"\n\n\nNS_ : \n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\nBO_ 130 EPAS_INFO: 8 XXX\n SG_ SteMdule_U_Meas : 39|8@0+ (0.05,6.0) [0|0] \"Volts\" XXX\n SG_ SteMdule_I_Est : 21|12@0+ (0.05,-64.0) [0|0] \"Amps\" XXX\n SG_ EPAS_FAILURE : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SteeringColumnTorque : 7|8@0+ (0.0625,-8.0) [0|0] \"Nm\" XXX\n SG_ SAPPAngleControlStat6 : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SAPPAngleControlStat5 : 14|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SAPPAngleControlStat4 : 13|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SAPPAngleControlStat3 : 12|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SAPPAngleControlStat2 : 11|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SAPPAngleControlStat1 : 23|2@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 118 Steering_Wheel_Data_CG1: 8 XXX\n SG_ SteWhlRelInit_An_Sns : 6|15@0+ (0.1,-1600.0) [0|0] \"deg\" XXX\n SG_ SteWhlRelCalib_An_Sns : 23|15@0+ (0.1,-1600.0) [0|0] \"deg\" XXX\n SG_ SteWhlRelInit2_An_Sns : 55|16@0+ (0.1,-3200.0) [0|0] \"deg\" XXX\n SG_ SteWhlAn_No_Cs : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ SteWhlAn_No_Cnt : 47|4@0+ (1,0) [0|0] \"Counts\" XXX\n\nBO_ 131 Steering_Buttons: 8 XXX\n SG_ Right_Turn_Light : 5|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Left_Turn_Light : 4|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Dist_Decr : 12|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Dist_Incr : 11|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Cancel : 8|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Resume : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Set : 28|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Main : 38|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 145 Yaw_Data: 8 XXX\n SG_ VehYaw_W_Actl : 39|16@0+ (0.0002,-6.5) [0|0] \"rad/s\" XXX\n SG_ VehRol_W_Actl : 23|16@0+ (0.0002,-6.5) [0|0] \"rad/s\" XXX\n SG_ VehPtch_W_Actl : 7|16@0+ (0.0002,-6.5) [0|0] \"rad/s\" XXX\n\nBO_ 146 Accel_Data: 8 XXX\n SG_ VehVertAActl_D_Qf : 38|2@0+ (1,0) [0|0] \"\" XXX\n SG_ VehLongAActl_D_Qf : 22|2@0+ (1,0) [0|0] \"\" XXX\n SG_ VehLatAActl_D_Qf : 6|2@0+ (1,0) [0|0] \"\" XXX\n SG_ VehVert_A_Actl : 36|13@0+ (0.01,-40.0) [0|0] \"m/s^2\" XXX\n SG_ VehLong_A_Actl : 20|13@0+ (0.01,-40.0) [0|0] \"m/s^2\" XXX\n SG_ VehLat_A_Actl : 4|13@0+ (0.01,-40.0) [0|0] \"m/s^2\" XXX\n\nBO_ 357 Cruise_Status: 8 XXX\n SG_ Brake_Drv_Appl : 5|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Cruise_State : 11|4@0+ (1,0) [0|0] \"\" XXX\n SG_ Set_Speed : 23|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 516 EngineData_14: 8 XXX\n SG_ ApedPosScal_Pc_Actl : 1|10@0+ (0.1,0) [0|0] \"%\" XXX\n\nBO_ 535 WheelSpeed_CG1: 8 XXX\n SG_ WhlRr_W_Meas : 55|14@0+ (0.04,0) [0|0] \"rad/s\" XXX\n SG_ WhlRl_W_Meas : 39|14@0+ (0.04,0) [0|0] \"rad/s\" XXX\n SG_ WhlFr_W_Meas : 23|14@0+ (0.04,0) [0|0] \"rad/s\" XXX\n SG_ WhlFl_W_Meas : 7|14@0+ (0.04,0) [0|0] \"rad/s\" XXX\n\nBO_ 534 WheelData: 8 XXX\n SG_ WhlRotatRr_No_Cnt : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlDirRr_D_Actl : 33|2@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlDirRl_D_Actl : 39|2@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlDirFr_D_Actl : 37|2@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlDirFl_D_Actl : 35|2@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlRotatRl_No_Cnt : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlRotatFr_No_Cnt : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ WhlRotatFl_No_Cnt : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ WHEEL_ROLLING_TIMESTAMP : 47|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 947 Doors: 8 XXX\n SG_ Door_FL_Open : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Door_FR_Open : 60|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Door_RL_Open : 48|1@0+ (1,0) [0|0] \"\" XXX\n SG_ Door_RR_Open : 49|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 963 BCM_to_HS_Body: 8 XXX\n SG_ Brake_Lights : 8|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 970 Lane_Keep_Assist_Control: 8 XXX\n SG_ Lkas_Action : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ Lkas_Alert : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ Lane_Curvature : 15|12@0+ (5e-06,-0.01) [0|0] \"1/m\" XXX\n SG_ Steer_Angle_Req : 19|12@0+ (0.04297,-88.00445) [0|0] \"deg\" XXX\n\nBO_ 972 Lane_Keep_Assist_Status: 8 XXX\n SG_ LaHandsOff_B_Actl : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ LaActDeny_B_Actl : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ LaActAvail_D_Actl : 5|2@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 984 Lane_Keep_Assist_Ui: 8 XXX\n SG_ Set_Me_X80 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ Set_Me_X45 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ Lines_Hud : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ Hands_Warning_W_Chime : 50|1@0+ (1,0) [0|1] \"\" XXX\n SG_ Hands_Warning : 49|1@0+ (1,0) [0|1] \"\" XXX\n SG_ Set_Me_X30 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ SG_ 970 Lkas_Action \"only vals 4, 5, 8, 9 seem to work. 4 and 5 are a bit smoother\" ;\n\nVAL_ 357 Cruise_State 4 \"active\" 3 \"standby\" 0 \"off\" ;\nVAL_ 970 Lkas_Action 15 \"off\" 9 \"abrupt\" 8 \"abrupt2\" 5 \"smooth\" 4 \"smooth2\" ;\nVAL_ 970 Lkas_Alert 15 \"no_alert\" 3 \"high_intensity\" 2 \"mid_intensity\" 1 \"low_intensity\" ;\nVAL_ 972 LaActAvail_D_Actl 3 \"available\" 2 \"tbd\" 1 \"not_available\" 0 \"fault\" ;\nVAL_ 984 Lines_Hud 15 \"none\" 11 \"grey_yellow\" 8 \"green_red\" 7 \"yellow_grey\" 6 \"grey_grey\" 4 \"red_green\" 3 \"green_green\" ;\n"
  },
  {
    "path": "opendbc/gm_global_a_chassis.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBS_:\n\nBU_: K182_PACM K43_PSCM K17_EBCM NEO K124_ASCM\n\n\n\nBO_ 823 PACMParkAssitCmd: 7 NEO\n SG_ RollingCounter : 35|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ SteeringWheelChecksum : 47|16@0+ (1,0) [0|0] \"\"  NEO\n SG_ SteeringWheelCmd : 23|16@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 560 EBCMRegen: 6 K17_EBCM\n SG_ Regen : 1|10@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 368 EBCMFrictionBrakeStatus: 8 K17_EBCM\n SG_ FrictionBrakePressure : 23|16@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 789 EBCMFrictionBrakeCmd: 5 K17_EBCM\n SG_ RollingCounter : 33|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ FrictionBrakeMode : 7|4@0+ (1,0) [0|0] \"\"  NEO\n SG_ FrictionBrakeChecksum : 23|16@0+ (1,0) [0|0] \"\"  NEO\n SG_ FrictionBrakeCmd : 3|12@0- (1,0) [0|0] \"\"  NEO\n\nBO_TX_BU_ 823 : K43_PSCM,NEO;\nBO_TX_BU_ 789 : NEO,K17_EBCM;\n\n\nCM_ BU_ K182_PACM \"Parking Assist Control Module\";\nCM_ BU_ K43_PSCM \"Power Steering Control Module\";\nCM_ BU_ K17_EBCM \"Electronic Brake Control Module\";\nCM_ BU_ NEO \"Comma NEO\";\nCM_ BU_ K124_ASCM \"Active Safety Control Module\";\nBA_DEF_  \"UseGMParameterIDs\" INT 0 0;\nBA_DEF_  \"ProtocolType\" STRING ;\nBA_DEF_  \"BusType\" STRING ;\nBA_DEF_DEF_  \"UseGMParameterIDs\" 1;\nBA_DEF_DEF_  \"ProtocolType\" \"GMLAN\";\nBA_DEF_DEF_  \"BusType\" \"\";\nBA_ \"UseGMParameterIDs\" 0;\nBA_ \"BusType\" \"CAN\";\nBA_ \"ProtocolType\" \"GMLAN\";\n\n"
  },
  {
    "path": "opendbc/gm_global_a_object.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBS_:\n\nBU_: K109_FCM B233B_LRR NEO VIS_FO VIS2_FO K124_ASCM Vector__XXX EOCM_F_FO EOCM2A_IMX6_FO EOCM2A_K2_FO EOCM2A_K1_FO EOCM2B_IMX6_FO EOCM2B_K2_FO EOCM2B_K1_FO\nVAL_TABLE_ RangeMode 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ TrkConf 3 \"Confident\" 2 \"Speculative\" 1 \"Highly speculative\" 0 \"Invalid\" ;\nVAL_TABLE_ TrkMeasStatus 3 \"Measured current cycle\" 2 \"Latent track not detected\" 1 \"New object\" 0 \"No object\" ;\nVAL_TABLE_ TrkDynProp 4 \"Moving in opposite direction\" 3 \"Moving in same direction\" 2 \"Has moved but currently stopped\" 1 \"Has never moved,\" 0 \"Unknown\" ;\nVAL_TABLE_ FrntVsnInPthVehBrkNwSt 10 \"Active\" 5 \"Inactive\" ;\nVAL_TABLE_ FrntVsnClostPedBrkNwSt 10 \"Active\" 5 \"Inactive\" ;\nVAL_TABLE_ LaneSnsLLnPosValid 1 \"Invalid\" 0 \"Valid\" ;\nVAL_TABLE_ LnSnsRLnPosValid 1 \"Invalid\" 0 \"Valid\" ;\nVAL_TABLE_ ObjectType 7 \"no object present\" 6 \"fixed roadside object\" 5 \"fixed overhead object\" 4 \"pedestrian\" 3 \"motocycle  / bicycle\" 2 \"Large vehicle (semi)\" 1 \"4 Wheel Vehicle (car, small trk)\" 0 \"Unknown\" ;\nVAL_TABLE_ FwVsnCinCoutPotT9Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT8Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT7Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT6Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT5Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT4Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT3Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT2Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT1Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT12Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT11Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\nVAL_TABLE_ FwVsnCinCoutPotT10Rev 2 \"Right\" 1 \"Left\" 0 \"None\" ;\n\n\nBO_ 3221225472 VECTOR__INDEPENDENT_SIG_MSG: 0 Vector__XXX\n SG_ Always12 : 0|8@0+ (1,0) [0|0] \"\"  Vector__XXX\n SG_ TimeStatusChecksum : 0|12@0+ (1,0) [0|0] \"\"  Vector__XXX\n\nBO_ 161 ASCMTimeStatus: 7 NEO\n SG_ TimeStatus : 7|28@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ RollingCounter : 27|2@0+ (1,0) [0|0] \"\"  B233B_LRR\n\nBO_ 774 ASCMSteeringStatus: 8 NEO\n SG_ ASCMSterringStatusChecksum : 55|16@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ AlwaysF0 : 15|8@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ Always20 : 23|8@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ RollingCounter : 7|2@0+ (1,0) [0|0] \"\"  B233B_LRR\n\nBO_ 784 ASCMHeadlight: 2 NEO\n SG_ Always42 : 7|8@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ Always4 : 15|8@0+ (1,0) [0|0] \"\"  B233B_LRR\n\nBO_ 776 ASCMAccSpeedStatus: 7 NEO\n SG_ AccSpeedChecksum : 42|11@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ RollingCounter : 46|2@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ NearRangeMode : 43|1@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ FarRangeMode : 44|1@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ VehicleAcceleration : 19|12@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ VehicleSpeed : 15|12@0+ (1,0) [0|0] \"\"  B233B_LRR\n SG_ AlwaysOne : 3|1@0+ (1,0) [0|0] \"\"  B233B_LRR\n\nBO_ 1120 F_LRR_Obj_Header: 8 LRR_FO\n SG_ FLRRRollingCount : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FLRRModeCmdFdbk : 23|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FLRRNumValidTargets : 20|5@0+ (1,0) [0|31] \"\"  EOCM_F_FO\n SG_ FLRRTimeStampV : 31|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRTimeStamp : 2|11@0+ (1,0) [0|2047] \"ms\"  EOCM_F_FO\n SG_ FLRRRoadTypeInfo : 5|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FLRRBurstChecksum : 55|16@0+ (1,0) [0|65535] \"\"  EOCM_F_FO\n SG_ FLRRDiagSpare : 30|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRVltgOutRngLo : 44|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRVltgOutRngHi : 43|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRSvcAlgnInPrcs : 38|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRSnsrBlckd : 45|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRSnstvFltPrsntInt : 24|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRPlntAlgnInProc : 37|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRMsalgnYawRt : 47|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRMsalgnYawLt : 46|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRLonVelPlsblityFlt : 35|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRYawRtPlsblityFlt : 34|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRMsalgnPtchUp : 32|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRMsalgnPtchDn : 33|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRInitDiagCmplt : 40|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRHWFltPrsntInt : 25|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRExtIntrfrnc : 36|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRCANSgnlSpvFld : 29|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRCANRxErr : 28|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRTunlDtctd : 27|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRAmbTmpOutRngLw : 42|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRAmbTmpOutRngHi : 41|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRAntTngFltPrsnt : 26|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FLRRAlgnFltPrsnt : 39|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n\nBO_ 1134 LRRObject14: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1132 LRRObject12: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1131 LRRObject11: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1130 LRRObject10: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1129 LRRObject09: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1128 LRRObject08: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1127 LRRObject07: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1126 LRRObject06: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1125 LRRObject05: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1124 LRRObject04: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1123 LRRObject03: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1140 LRRObject20: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1139 LRRObject19: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1138 LRRObject18: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1137 LRRObject17: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1136 LRRObject16: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1135 LRRObject15: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1133 LRRObject13: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1122 LRRObject02: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n\nBO_ 1121 LRRObject01: 8 B233B_LRR\n SG_ TrkRange : 5|11@0+ (0.125,0) [0|255.875] \"m\"  NEO\n SG_ TrkRangeRate : 10|11@0- (0.125,0) [-128|127.875] \"m/s\"  NEO\n SG_ TrkRangeAccel : 31|9@0- (0.125,0) [-32|31.875] \"m/s^2\"  NEO\n SG_ TrkAzimuth : 35|12@0- (0.125,0) [-256|255.875] \"deg\"  NEO\n SG_ TrkWidth : 55|6@0+ (0.25,0) [0|15.75] \"m\"  NEO\n SG_ TrkObjectID : 61|6@0+ (1,0) [0|63] \"\"  NEO\n \n BO_ 1094 F_Vision_Obj_Track_12: 8 VIS2_FO\n SG_ FwdVsnObjTypTr12Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk12Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk12Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FVisionWidthTrk12 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk12 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnVertPosTrk12 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk12 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk12 : 34|11@0- (0.125,0) [-128|127.875] \"deg/sec\"  EOCM_F_FO\n SG_ FVisionConfTrk12 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ ObjDirTrk12 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk12 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk12 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n\nBO_ 1093 F_Vision_Obj_Track_11: 8 VIS2_FO\n SG_ FwdVsnObjTypTr11Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk11Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk11Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FVisionWidthTrk11 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk11 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnVertPosTrk11 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk11 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk11 : 34|11@0- (0.125,0) [-128|127.875] \"deg/sec\"  EOCM_F_FO\n SG_ FVisionConfTrk11 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ ObjDirTrk11 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk11 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk11 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n\nBO_ 1100 F_Vision_Obj_Track_12_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT12Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk12 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk12 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk12 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk12 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr12 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk12 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo12 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1099 F_Vision_Obj_Track_11_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT11Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk11 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk11 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk11 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk11 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr11 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk11 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo11 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1098 F_Vision_Obj_Track_10_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT10Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk10 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk10 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk10 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk10 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr10 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk10 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo10 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1097 F_Vision_Obj_Track_9_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT9Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk9 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk9 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk9 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk9 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr9 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk9 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo9 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1096 F_Vision_Obj_Track_8_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT8Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk8 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk8 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk8 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk8 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr8 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk8 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo8 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1095 F_Vision_Obj_Track_7_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT7Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk7 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk7 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk7 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk7 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr7 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk7 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo7 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1068 F_Vision_Obj_Track_6_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT6Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk6 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk6 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk6 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk6 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr6 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk6 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo6 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1067 F_Vision_Obj_Track_5_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT5Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk5 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk5 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk5 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk5 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr5 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk5 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo5 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1066 F_Vision_Obj_Track_4_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT4Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk4 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk4 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk4 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk4 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr4 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk4 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo4 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1065 F_Vision_Obj_Track_3_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT3Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk3 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk3 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk3 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk3 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr3 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk3 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo3 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1064 F_Vision_Obj_Track_2_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT2Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk2 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk2 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk2 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk2 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr2 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk2 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo2 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1063 F_Vision_Obj_Track_1_B: 8 VIS2_FO\n SG_ FwVsnCinCoutPotT1Rev : 5|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnObjSclChgTrk1 : 15|16@0- (0.0002,0) [-6.5536|6.5534] \"pix/sec\"  EOCM_F_FO\n SG_ FwdVsnObjAgeTrk1 : 62|7@0+ (1,0) [0|127] \"\"  EOCM_F_FO\n SG_ FwdVsnLongVlctyTrk1 : 42|12@0- (0.0625,0) [-128|127.9375] \"m/sec\"  EOCM_F_FO\n SG_ FwdVsnLatOfstTrk1 : 36|10@0- (0.125,0) [-64|63.875] \"m\"  EOCM_F_FO\n SG_ FwdVsnBrkLtStatTrk1 : 38|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FwdVsnTrnSigStatTr1 : 25|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FrtVsnBrstIDAddInfo1 : 7|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1088 F_Vision_Obj_Header_2: 8 VIS2_FO\n SG_ FrntVsnInPthVehBrkNwSt : 35|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FrntVsnClostPedBrkNwSt : 39|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FrntVsnClostPedObjID : 29|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FrntVsnClostPedAlrtNwFlg : 30|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrntVsnClostPedNotftnFlg : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrntVsnInPthVehAlrtNwFlg : 2|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrtVsnVldTgtNum2 : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FrtVsnTmStmp2V : 31|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrtVsnTmStmp2 : 10|11@0+ (1,0) [0|2047] \"\"  EOCM_F_FO\n SG_ FrtVsnRollCnt2 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FrtVsnBrstChksum2 : 55|16@0+ (1,0) [0|65535] \"\"  EOCM_F_FO\n\nBO_ 854 F_Vision_Environment_7: 3 VIS2_FO\n SG_ FwdVsnCnstrctAreaDst : 13|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ FwdVsnCnstrctZnDet : 15|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ FwdVsnEgoVehLnPos : 17|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ FwdVsnRdTypDet : 9|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ FwdVsnTunnlDetd : 23|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ FwdVsnTunnlDst : 21|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBrstID5 : 1|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\nBO_ 853 F_Vision_Environment_6: 8 VIS2_FO\n SG_ LnMrkg4LnSnsLnHdngTngtV : 7|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnHdngTngt : 23|8@0- (0.002,0) [-0.256|0.254] \"m/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnDstV : 56|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnDst : 15|8@0- (0.1,0) [-12.8|12.7] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnCrvtV : 6|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnCrvtGradV : 5|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnCrvtGrad : 47|16@0- (5.96e-8,0) [-0.0019529728|0.0019529132] \"1/(m*sec)\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnSnsLnCrvt : 31|16@0- (9.53e-7,0) [-0.031227904|0.031226951] \"1/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnQltyConfLvl : 63|7@0+ (0.7874016,0) [0|100.0000032] \"%\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnMrkrTyp : 4|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBrstID4 : 1|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\nBO_ 852 F_Vision_Environment_5: 8 VIS2_FO\n SG_ LnMrkg3LnSnsLnHdngTngtV : 7|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnHdngTngt : 23|8@0- (0.002,0) [-0.256|0.254] \"m/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnDstV : 56|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnDst : 15|8@0- (0.1,0) [-12.8|12.7] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnCrvtV : 6|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnCrvtGradV : 5|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnCrvtGrad : 47|16@0- (5.96e-8,0) [-0.0019529728|0.0019529132] \"1/(m*sec)\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnSnsLnCrvt : 31|16@0- (9.53e-7,0) [-0.031227904|0.031226951] \"1/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnQltyConfLvl : 63|7@0+ (0.7874016,0) [0|100.0000032] \"%\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnMrkrTyp : 4|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBrstID3 : 1|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\nBO_ 309 LHT_CameraObjConfirmation_FO: 1 VIS_FO\n SG_ HiBmRecmnd : 1|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ CtLghtDet : 0|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n\nBO_ 848 F_Vision_Environment: 8 VIS_FO\n SG_ FwdVsnEnvIllum : 37|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsTngtOfHdngLnRtV : 1|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsTngtOfHdngLnRt : 31|8@0- (0.002,0) [-0.256|0.254] \"m/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLnChngStatus : 39|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBurstChecksum : 55|16@0+ (1,0) [0|65535] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LaneSenseRollingCount : 7|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LaneSenseSystemOK : 4|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LaneSnsLLnPosValid : 2|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSenseDistToLLnEdge : 14|7@0+ (0.05,0) [0|6.35] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsRLnPosValid : 0|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsDistToRLnEdge : 22|7@0+ (0.05,0) [0|6.35] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LaneSenseTimeStampV : 5|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LaneSenseTimeStamp : 34|11@0+ (1,0) [0|2047] \"ms\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LaneSenseSystemOKV : 3|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\nBO_ 849 F_Vision_Environment_2: 8 VIS_FO\n SG_ LnSnsLatVRelToRgtMrkg : 23|8@0- (0.02,0) [-2.56|2.54] \"m/s\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM_F_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO\n SG_ LnSnsRtLnMrkgTypChgDst : 61|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsCrvtGrdntRtV : 63|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLnMrkgWdthRt : 62|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsRtAnchrLn : 57|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLtAnchrLn : 56|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLnCrvtrRghtV : 0|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLnCrvtrRght : 47|16@0- (9.53e-7,0) [-0.031227904|0.031226951] \"1/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsCrvtGrdntRt : 31|16@0- (5.96e-8,0) [-0.0019529728|0.0019529132] \"1/rad/s\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBurstID : 2|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLatVRelToLftMrkg : 15|8@0- (0.02,0) [-2.56|2.54] \"m/s\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\nBO_ 1056 F_Vision_Obj_Header: 6 VIS_FO\n SG_ FVsnSnsrBlckd : 24|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ ClstInPathVehObjID : 30|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FrtVsnFld : 6|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrtVsnIniDiagSuccCmpt : 5|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrtVsnSrvAlgnInPrcs : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FrtVsnUnvlbl : 7|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisionRollingCnt : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVISModeCmdFdbk : 4|3@0+ (1,0) [0|7] \"\"  EOCM_F_FO\n SG_ FVisionNumValidTrgts : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FVisionTimeStampV : 31|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisionTimeStamp : 10|11@0+ (1,0) [0|2047] \"ms\"  EOCM_F_FO\n SG_ VISBurstChecksum : 39|16@0+ (1,0) [0|65535] \"\"  EOCM_F_FO\n\nBO_ 1057 F_Vision_Obj_Track_1: 8 VIS_FO\n SG_ FwdVsnRngTrk1Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk1Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr1Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FwdVsnVertPosTrk1 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FVisBurstIDTrk1 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk1 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk1 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk1 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk1 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk1 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk1 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n SG_ ObjDirTrk1 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n\nBO_ 1058 F_Vision_Obj_Track_2: 8 VIS_FO\n SG_ FwdVsnVertPosTrk2 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk2Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk2Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ ObjDirTrk2 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr2Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk2 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk2 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk2 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk2 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk2 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk2 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk2 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 1059 F_Vision_Obj_Track_3: 8 VIS_FO\n SG_ FwdVsnVertPosTrk3 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk3Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk3Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr3Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ ObjDirTrk3 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk3 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk3 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk3 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk3 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk3 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk3 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk3 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 1060 F_Vision_Obj_Track_4: 8 VIS_FO\n SG_ FwdVsnVertPosTrk4 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk4 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk4 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n SG_ FwdVsnRngTrk4Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk4Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr4Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk4 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk4 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ ObjDirTrk4 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk4 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk4 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk4 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n\nBO_ 1061 F_Vision_Obj_Track_5: 8 VIS_FO\n SG_ FwdVsnVertPosTrk5 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk5Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk5Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr5Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ ObjDirTrk5 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk5 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk5 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk5 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk5 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk5 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk5 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk5 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 1062 F_Vision_Obj_Track_6: 8 VIS_FO\n SG_ FwdVsnVertPosTrk6 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk6Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk6Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr6Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ ObjDirTrk6 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk6 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk6 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk6 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk6 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk6 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk6 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk6 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 1089 F_Vision_Obj_Track_7: 8 VIS2_FO\n SG_ FVisBurstIDTrk7 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk7 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk7 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk7 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk7 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk7 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk7 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n SG_ FwdVsnRngTrk7Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr7Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk7Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnVertPosTrk7 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ ObjDirTrk7 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n\nBO_ 1090 F_Vision_Obj_Track_8: 8 VIS2_FO\n SG_ FVisBurstIDTrk8 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk8 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk8Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnVertPosTrk8 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk8Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr8Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ ObjDirTrk8 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk8 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk8 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk8 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk8 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk8 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 1091 F_Vision_Obj_Track_9: 8 VIS2_FO\n SG_ FwdVsnVertPosTrk9 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ FwdVsnRngTrk9Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk9Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr9Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ ObjDirTrk9 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk9 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk9 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk9 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk9 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk9 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk9 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk9 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 1092 F_Vision_Obj_Track_10: 8 VIS2_FO\n SG_ FwdVsnRngTrk10Rev : 16|12@0+ (0.1,0) [0|409.5] \"m\"  EOCM_F_FO\n SG_ FwdVsnAzmthTrk10Rev : 10|10@0- (0.1,0) [-51.2|51.1] \"deg\"  EOCM_F_FO\n SG_ FwdVsnObjTypTr10Rev : 14|4@0+ (1,0) [0|15] \"\"  EOCM_F_FO\n SG_ FwdVsnVertPosTrk10 : 53|6@0+ (0.25,-2) [-2|13.75] \"deg\"  EOCM_F_FO\n SG_ ObjDirTrk10 : 15|1@0+ (1,0) [0|1] \"\"  EOCM_F_FO\n SG_ FVisBurstIDTrk10 : 1|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionObjectIDTrk10 : 7|6@0+ (1,0) [0|63] \"\"  EOCM_F_FO\n SG_ FVisionConfTrk10 : 36|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionAzRateTrk10 : 34|11@0- (0.125,0) [-128|127.875] \"deg/s\"  EOCM_F_FO\n SG_ FVisionRelLaneTrk10 : 55|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionMeasStatTrk10 : 63|2@0+ (1,0) [0|3] \"\"  EOCM_F_FO\n SG_ FVisionWidthTrk10 : 61|6@0+ (0.25,0) [0|15.75] \"m\"  EOCM_F_FO\n\nBO_ 851 F_Vision_Environment_4: 8 VIS_FO\n SG_ LnMrkg3LnPrvwDst : 45|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsTtlNmLnMrkgDetRt : 4|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsRtLinCrsTm : 25|5@0+ (0.1,0) [0|3.1] \"s\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsNumPrlLnsDetRt : 33|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsNumPrlLnsDetLt : 36|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsCrvtGrdntLftV : 31|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLtLinCrsTm : 30|5@0+ (0.1,0) [0|3.1] \"s\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnPrvwDst : 50|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnMrkgTypChgDst : 61|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnMrkgTypChgDst : 40|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnMrkgWdth : 62|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4LnMarkrElvtd : 51|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg4AnchrLnLin : 57|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnMrkgWdth : 41|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3LnMarkrElvtd : 46|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkg3AnchrLnLin : 52|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBurstID2 : 1|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsCrvtGrdntLft : 15|16@0- (5.96e-8,0) [-0.0019529728|0.0019529132] \"1/rad/s\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\n BO_ 850 F_Vision_Environment_3: 8 VIS_FO\n SG_ LnSnsTtlNmLnMrkgDetLt : 58|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLtLnMrkgWdth : 63|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLtLnMrkgTypChgDst : 62|4@0+ (10,0) [0|150] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsTngtOfHdngLnLftV : 23|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsTngtOfHdngLnLft : 31|8@0- (0.002,0) [-0.256|0.254] \"m/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLnCrvtrLftV : 15|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsLnCrvtrLft : 39|16@0- (9.53e-7,0) [-0.031227904|0.031226951] \"1/m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkrTypRght : 50|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkrTypLft : 53|3@0+ (1,0) [0|7] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkrElvtdRght : 54|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnMrkrElvtdLft : 55|1@0+ (1,0) [0|1] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnSnsBurstID1 : 7|2@0+ (1,0) [0|3] \"\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnQltyCnfdncLvlRght : 22|7@0+ (0.7874016,0) [0|100.0000032] \"%\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnQltyCnfdncLvlLft : 14|7@0+ (0.7874016,0) [0|100.0000032] \"%\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnPrvwDstncRght : 2|3@0+ (10,0) [0|70] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n SG_ LnPrvwDstncLft : 5|3@0+ (10,0) [0|70] \"m\"  EOCM2A_IMX6_FO,EOCM2A_K2_FO,EOCM2A_K1_FO,EOCM2B_IMX6_FO,EOCM2B_K2_FO,EOCM2B_K1_FO,EOCM_F_FO\n\n\nBO_TX_BU_ 161 : K124_ASCM,NEO;\nBO_TX_BU_ 774 : K124_ASCM,NEO;\nBO_TX_BU_ 784 : K124_ASCM,NEO;\nBO_TX_BU_ 776 : K124_ASCM,NEO;\n\n\nCM_ BU_ K109_FCM \"Frontview Camera Module\";\nCM_ BU_ B233B_LRR \"Radar Sensor Module Long Range\";\nCM_ BU_ NEO \"Comma NEO\";\nCM_ BU_ VIS_FO \"Front Camera Data\";\nCM_ BU_ VIS2_FO \"Front Camera Data2\";\nCM_ BU_ K124_ASCM \"Active Safety Control Module\";\nCM_ BO_ 3221225472 \"This is a message for not used signals, created by Vector CANdb++ DBC OLE DB Provider.\";\nBA_DEF_  \"UseGMParameterIDs\" INT 0 0;\nBA_DEF_  \"ProtocolType\" STRING ;\nBA_DEF_  \"BusType\" STRING ;\nBA_DEF_DEF_  \"UseGMParameterIDs\" 1;\nBA_DEF_DEF_  \"ProtocolType\" \"GMLAN\";\nBA_DEF_DEF_  \"BusType\" \"\";\nBA_ \"BusType\" \"CAN\";\nBA_ \"ProtocolType\" \"GMLAN\";\nBA_ \"UseGMParameterIDs\" 0;\nVAL_ 776 NearRangeMode 1 \"Active\" 0 \"Inactive\";\nVAL_ 776 FarRangeMode 1 \"Active\" 0 \"Inactive\";\n"
  },
  {
    "path": "opendbc/gm_global_a_powertrain.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBS_:\n\nBU_: K16_BECM K73_TCIC K9_BCM K43_PSCM K17_EBCM K20_ECM K114B_HPCM NEO K124_ASCM EPB\nVAL_TABLE_ TurnSignals 2 \"Right Turn\" 1 \"Left Turn\" 0 \"None\" ;\nVAL_TABLE_ Intellibeam 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ HighBeamsActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ HighBeamsTemporary 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ ACCLeadCar 1 \"Present\" 0 \"Not Present\" ;\nVAL_TABLE_ ACCCmdActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ BrakePedalPressed 1 \"Pressed\" 0 \"Depressed\" ;\nVAL_TABLE_ DistanceButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ LKAButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ ACCButtons 6 \"Cancel\" 5 \"Main\" 3 \"Set\" 2 \"Resume\" 1 \"None\" ;\nVAL_TABLE_ DriveModeButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ PRNDL 3 \"Reverse\" 2 \"Drive\" 1 \"Neutral\" 0 \"Park\" ;\nVAL_TABLE_ ESPButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ DoorStatus 1 \"Opened\" 0 \"Closed\" ;\nVAL_TABLE_ SeatBeltStatus 1 \"Latched\" 0 \"Unlatched\" ;\nVAL_TABLE_ LKASteeringCmdActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ ACCGapLevel 3 \"Far\" 2 \"Med\" 1 \"Near\" 0 \"Inactive\" ;\nVAL_TABLE_ GasRegenCmdActiveInv 1 \"Inactive\" 0 \"Active\" ;\nVAL_TABLE_ GasRegenCmdActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ LKATorqueDeliveredStatus 3 \"Failed\" 2 \"Temp. Limited\" 1 \"Active\" 0 \"Inactive\" ;\nVAL_TABLE_ HandsOffSWDetectionStatus 1 \"Hands On\" 0 \"Hands Off\" ;\nVAL_TABLE_ HandsOffSWDetectionMode 2 \"Failed\" 1 \"Enabled\" 0 \"Disabled\" ;\n\n\nBO_ 189 EBCMRegenPaddle: 7 K17_EBCM\n SG_ RegenPaddle : 7|4@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 190 ECMAcceleratorPos: 6 K20_ECM\n SG_ BrakePedalPos : 15|8@0+ (1,0) [0|0] \"sticky\"  NEO\n SG_ GasPedalAndAcc : 23|8@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 201 ECMEngineStatus: 8 K20_ECM\n SG_ EngineTPS : 39|8@0+ (0.392156863,0) [0|100.000000065] \"%\" NEO\n SG_ EngineRPM : 13|14@0+ (0.25,0) [0|0] \"RPM\" NEO\n SG_ CruiseMainOn : 29|1@0+ (1,0) [0|1] \"\" NEO\n SG_ Brake_Pressed : 40|1@0+ (1,0) [0|1] \"\" NEO\n SG_ Standstill : 2|1@0+ (1,0) [0|1] \"\" NEO\n\nBO_ 209 EBCMBrakePedalTorque: 7 K17_EBCM\n SG_ BrakePedalTorque : 3|12@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 241 EBCMBrakePedalPosition: 6 K17_EBCM\n SG_ BrakePedalPosition : 15|8@0+ (1,0) [0|255] \"\"  NEO\n\nBO_ 298 BCMDoorBeltStatus: 8 K9_BCM\n SG_ RearLeftDoor : 8|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ FrontLeftDoor : 9|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ FrontRightDoor : 10|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ RearRightDoor : 23|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ LeftSeatBelt : 12|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ RightSeatBelt : 53|1@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 309 ECMPRDNL: 8 K20_ECM\n SG_ PRNDL : 2|3@0+ (1,0) [0|0] \"\"  NEO\n SG_ ESPButton : 4|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 320 BCMTurnSignals: 3 K9_BCM\n SG_ TurnSignals : 19|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ Intellibeam : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HighBeamsActive : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HighBeamsTemporary : 5|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 328 PSCM_148: 1 K43_PSCM\n\nBO_ 381 ESPStatus: 6 K20_ECM\n SG_ TractionControlOn : 5|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ MSG17D_AccPower : 35|12@0- (1,0) [0|0] \"\"  NEO\n\nBO_ 384 ASCMLKASteeringCmd: 4 NEO\n SG_ RollingCounter : 5|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ LKASteeringCmdChecksum : 19|12@0+ (1,0) [0|0] \"\"  NEO\n SG_ LKASteeringCmdActive : 3|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ LKASteeringCmd : 2|11@0- (1,0) [0|0] \"\"  NEO\n\nBO_ 388 PSCMStatus: 8 K43_PSCM\n SG_ HandsOffSWDetectionMode : 20|2@0+ (1,0) [0|3] \"\" NEO\n SG_ HandsOffSWlDetectionStatus : 21|1@0+ (1,0) [0|1] \"\" NEO\n SG_ LKATorqueDeliveredStatus : 5|3@0+ (1,0) [0|7] \"\" NEO\n SG_ LKADriverAppldTrq : 50|11@0- (0.01,0) [-10.24|10.23] \"Nm\" NEO\n SG_ LKATorqueDelivered : 18|11@0- (0.01,0) [0|1] \"\" NEO\n SG_ LKATotalTorqueDelivered : 2|11@0- (0.01,0) [-10.24|10.23] \"Nm\" NEO\n\nBO_ 417 AcceleratorPedal: 7 XXX\n SG_ AcceleratorPedal : 55|8@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 451 GasAndAcc: 8 XXX\n SG_ GasPedalAndAcc2 : 55|8@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 452 AcceleratorPedal2: 8 XXX\n SG_ CruiseState : 15|3@0+ (1,0) [0|7] \"\"  NEO\n SG_ AcceleratorPedal2 : 47|8@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 481 ASCMSteeringButton: 7 K124_ASCM\n SG_ DistanceButton : 22|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ LKAButton : 23|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ ACCButtons : 46|3@0+ (1,0) [0|0] \"\"  NEO\n SG_ DriveModeButton : 39|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 485 PSCMSteeringAngle: 8 K43_PSCM\n SG_ SteeringWheelAngle : 15|16@0- (0.0625,0) [-2047|2047] \"deg\"  NEO\n SG_ SteeringWheelRate : 27|12@0- (1,0) [-2047|2047] \"deg/s\"  NEO\n\nBO_ 489 EBCMVehicleDynamic: 8 K17_EBCM\n SG_ BrakePedalPressed : 6|1@0+ (1,0) [0|0] \"\" NEO\n SG_ LateralAcceleration : 3|10@0- (0.161,0) [-2047|2047] \"m/s2\" NEO\n SG_ YawRate : 35|12@0- (0.625,0) [0|1] \"\" NEO\n SG_ YawRate2 : 51|12@0- (0.0625,0) [-2047|2047] \"grad/s\" NEO\n\nBO_ 560 EPBStatus: 8 EPB\n SG_ EPBClosed : 12|1@0+ (1,0) [0|1] \"\"  NEO\n\nBO_ 711 BECMBatteryVoltageCurrent: 6 K17_EBCM\n SG_ HVBatteryVoltage : 31|12@0+ (0.125,0) [0|511.875] \"V\"  NEO\n SG_ HVBatteryCurrent : 12|13@0- (0.15,0) [-614.4|614.25] \"A\"  NEO\n\nBO_ 715 ASCMGasRegenCmd: 8 K124_ASCM\n SG_ GasRegenAlwaysOne2 : 9|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GasRegenAlwaysOne : 14|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GasRegenChecksum : 47|24@0+ (1,0) [0|0] \"\"  NEO\n SG_ GasRegenCmdActiveInv : 32|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ GasRegenFullStopActive : 13|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ GasRegenCmdActive : 0|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ RollingCounter : 7|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GasRegenAlwaysOne3 : 23|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GasRegenCmd : 22|12@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 717 ASCM_2CD: 5 K124_ASCM\n\nBO_ 810 TCICOnStarGPSPosition: 8 K73_TCIC\n SG_ GPSLongitude : 39|32@0+ (1,-2147483648) [0|0] \"milliarcsecond\"  NEO\n SG_ GPSLatitude : 7|32@0+ (1,0) [0|0] \"milliarcsecond\"  NEO\n\nBO_ 840 EBCMWheelSpdFront: 4 K17_EBCM\n SG_ FLWheelSpd : 7|16@0+ (0.0311,0) [0|255] \"km/h\"  NEO\n SG_ FRWheelSpd : 23|16@0+ (0.0311,0) [0|255] \"km/h\"  NEO\n\nBO_ 842 EBCMWheelSpdRear: 5 K17_EBCM\n SG_ RLWheelSpd : 7|16@0+ (0.0311,0) [0|255] \"km/h\"  NEO\n SG_ RRWheelSpd : 23|16@0+ (0.0311,0) [0|255] \"km/h\"  NEO\n\nBO_ 869 ASCM_365: 4 K124_ASCM\n\nBO_ 880 ASCMActiveCruiseControlStatus: 6 K124_ASCM\n SG_ ACCLeadCar : 44|1@0+ (1,0) [0|0] \"\" Vector__XXX\n SG_ ACCAlwaysOne2 : 32|1@0+ (1,0) [0|0] \"\" Vector__XXX\n SG_ ACCAlwaysOne : 0|1@0+ (1,0) [0|0] \"\" Vector__XXX\n SG_ ACCSpeedSetpoint : 19|12@0+ (1,0) [0|0] \"km/h\"  NEO\n SG_ ACCGapLevel : 21|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ ACCResumeButton : 1|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ ACCCmdActive : 23|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ FCWAlert : 41|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 1001 ECMVehicleSpeed: 8 K20_ECM\n SG_ VehicleSpeed : 7|16@0+ (0.01,0) [0|0] \"mph\"  NEO\n\nBO_ 1033 ASCMKeepAlive: 7 NEO\n SG_ ASCMKeepAliveAllZero : 7|56@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 1034 ASCM_40A: 7 K124_ASCM\n\nBO_ 1217 ECMEngineCoolantTemp: 8 K20_ECM\n SG_ EngineCoolantTemp : 23|8@0+ (1,-40) [0|0] \"C\"  NEO\n\nBO_ 1249 VIN_Part2: 8 K20_ECM\n SG_ VINPart2 : 7|64@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 1296 ASCM_510: 4 K124_ASCM\n\nBO_ 1300 VIN_Part1: 8 K20_ECM\n SG_ VINPart1 : 7|64@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 1912 PSCM_778: 8 K43_PSCM\n\nBO_ 1930 ASCM_78A: 7 K124_ASCM\n\nBO_TX_BU_ 384 : K124_ASCM,NEO;\nBO_TX_BU_ 880 : NEO,K124_ASCM;\nBO_TX_BU_ 1033 : K124_ASCM,NEO;\nBO_TX_BU_ 715 : NEO,K124_ASCM;\n\n\nCM_ BU_ K16_BECM \"Battery Energy Control Module\";\nCM_ BU_ K73_TCIC \"Telematics Communication Control Module\";\nCM_ BU_ K9_BCM \"Body Control Module\";\nCM_ BU_ K43_PSCM \"Power Steering Control Module\";\nCM_ BU_ K17_EBCM \"Electronic Brake Control Module\";\nCM_ BU_ K20_ECM \"Engine Control Module\";\nCM_ BU_ K114B_HPCM \"Hybrid Powertrain Control Module\";\nCM_ BU_ NEO \"Comma NEO\";\nCM_ BU_ K124_ASCM \"Active Safety Control Module\";\nCM_ SG_ 381 MSG17D_AccPower \"Need to investigate\";\nCM_ SG_ 190 GasPedalAndAcc \"ACC baseline is 62\";\nCM_ SG_ 451 GasPedalAndAcc2 \"ACC baseline is 62\";\nBA_DEF_  \"UseGMParameterIDs\" INT 0 0;\nBA_DEF_  \"ProtocolType\" STRING ;\nBA_DEF_  \"BusType\" STRING ;\nBA_DEF_DEF_  \"UseGMParameterIDs\" 1;\nBA_DEF_DEF_  \"ProtocolType\" \"GMLAN\";\nBA_DEF_DEF_  \"BusType\" \"\";\nBA_ \"BusType\" \"CAN\";\nBA_ \"ProtocolType\" \"GMLAN\";\nBA_ \"UseGMParameterIDs\" 0;\nVAL_ 481 DistanceButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 481 LKAButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 481 ACCButtons 6 \"Cancel\" 5 \"Main\" 3 \"Set\" 2 \"Resume\" 1 \"None\" ;\nVAL_ 481 DriveModeButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 452 CruiseState 4 \"Standstill\" 3 \"Faulted\" 1 \"Active\" 0 \"Off\" ;\nVAL_ 309 PRNDL 3 \"R\" 2 \"D\" 1 \"N\" 0 \"P\" ;\nVAL_ 309 ESPButton 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 384 LKASteeringCmdActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 880 ACCLeadCar 1 \"Present\" 0 \"Not Present\" ;\nVAL_ 880 ACCGapLevel 3 \"Far\" 2 \"Med\" 1 \"Near\" 0 \"Inactive\" ;\nVAL_ 880 ACCResumeButton 1 \"Pressed\" 0 \"Depressed\" ;\nVAL_ 880 ACCCmdActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 388 HandsOffSWDetectionMode 2 \"Failed\" 1 \"Enabled\" 0 \"Disabled\" ;\nVAL_ 388 HandsOffSWlDetectionStatus 1 \"Hands On\" 0 \"Hands Off\" ;\nVAL_ 388 LKATorqueDeliveredStatus 3 \"Failed\" 2 \"Temp. Limited\" 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 489 BrakePedalPressed 1 \"Pressed\" 0 \"Depressed\" ;\nVAL_ 715 GasRegenCmdActiveInv 1 \"Inactive\" 0 \"Active\" ;\nVAL_ 715 GasRegenCmdActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 320 Intellibeam 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 320 HighBeamsActive 1 \"Active\" 0 \"Inactive\" ;\nVAL_ 320 HighBeamsTemporary 1 \"Active\" 0 \"Inactive\" ;\n"
  },
  {
    "path": "opendbc/honda_accord_2018_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2018.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 13274 LKAS_HUD_A: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 13275 LKAS_HUD_B: 8 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" BDY\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"honda_accord_2018_can.dbc starts here\";\n\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 401 GEARBOX_15T: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\" EON\n SG_ BOH : 45|6@0+ (1,0) [0|63] \"\" XXX\n SG_ GEAR2 : 31|8@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 47|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 446 BRAKE_MODULE: 3 VSA\n SG_ BRAKE_PRESSED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BOH : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_2 : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nVAL_ 419 GEAR_SHIFTER  32 \"D\" 8 \"R\" 4 \"P\" ;\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_civic_hatchback_ex_2017_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2018.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 13274 LKAS_HUD_A: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 13275 LKAS_HUD_B: 8 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" BDY\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"honda_civic_hatchback_ex_2017_can.dbc starts here\";\n\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 401 GEARBOX: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\" EON\n SG_ BOH : 45|6@0+ (1,0) [0|63] \"\" XXX\n SG_ GEAR2 : 31|8@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 47|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 506 LEGACY_BRAKE_COMMAND: 8 ADAS\n SG_ CHIME : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|15] \"\" EON\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BOH : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_2 : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_civic_sedan_16_diesel_2019_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2018.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 13274 LKAS_HUD_A: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 13275 LKAS_HUD_B: 8 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" BDY\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"honda_civic_sedan_16_diesel_2019_can.dbc starts here\";\n\n\nBO_ 316 GAS_PEDAL_2: 8 XXX\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 419 GEARBOX: 8 XXX\n SG_ GEAR_SHIFTER : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ GEAR : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 506 LEGACY_BRAKE_COMMAND: 8 ADAS\n SG_ CHIME : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|15] \"\" EON\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH3 : 31|32@0+ (1,0) [0|4294967295] \"\" XXX\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nVAL_ 419 GEAR_SHIFTER 2 \"S\" 32 \"D\" 16 \"N\" 8 \"R\" 4 \"P\" ;\nVAL_ 419 GEAR 26 \"S\" 20 \"D\" 19 \"N\" 18 \"R\" 17 \"P\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_civic_touring_2016_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_civic_touring_2016_can.dbc starts here\";\n\n\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (0.02,-512) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 24|9@0- (-0.02,0) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 ADAS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-3840|3840] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 401 GEARBOX: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 493 HUD_SETTING: 5 XXX\n SG_ IMPERIAL_UNIT : 5|1@0+ (1,0) [0|1] \"\" EON\n\nBO_ 487 BRAKE_PRESSURE: 4 VSA\n SG_ BRAKE_PRESSURE1 : 7|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ BRAKE_PRESSURE2 : 9|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 545 ECON_STATUS: 6 XXX\n SG_ ECON_ON_2 : 37|2@0+ (1,0) [0|3] \"\" EON\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 662 SCM_BUTTONS: 4 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ CMBS_BUTTON : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ REVERSE_LIGHT : 18|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 862 HIGHBEAM_CONTROL: 8 ADAS\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ ZEROS_BOH_2 : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ DASHBOARD_ALERT : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 WIPERS: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 927 RADAR_HUD: 8 ADAS\n SG_ ZEROS_BOH : 7|17@0+ (1,0) [0|127] \"\" BDY\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|15] \"\" BDY\n SG_ ZEROS_BOH2 : 31|8@0+ (1,0) [0|127] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|15] \"\" BDY\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|15] \"\" BDY\n SG_ LEAD_SPEED : 39|9@0+ (1,0) [0|127] \"\" BDY\n SG_ LEAD_STATE : 46|3@0+ (1,0) [0|127] \"\" BDY\n SG_ LEAD_DISTANCE : 43|5@0+ (1,0) [0|31] \"\" BDY\n SG_ ZEROS_BOH3 : 54|7@0+ (1,0) [0|127] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 401 GEAR \"10 = reverse, 11 = transition\";\nCM_ SG_ 420 BRAKE_HOLD_RELATED \"On when Brake Hold engaged\";\nCM_ SG_ 450 EPB_STATE \"3 \\\"engaged\\\" 2 \\\"disengaging\\\" 1 \\\"engaging\\\" 0 \\\"disengaged\\\"\";\nCM_ SG_ 806 REVERSE_LIGHT \"Might be reverse gear selected and not the lights\";\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 450 EPB_STATE 3 \"engaged\" 2 \"disengaging\" 1 \"engaging\" 0 \"disengaged\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 884 DASHBOARD_ALERT 0 \"none\" 51 \"acc_problem\" 55 \"cmbs_problem\" 75 \"key_not_detected\" 79 \"fasten_seatbelt\" 111 \"lkas_problem\" 131 \"brake_system_problem\" 132 \"brake_hold_problem\" 139 \"tbd\" 161 \"door_open\"\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 927 ACC_ALERTS 29 \"esp_active_acc_canceled\" 10 \"b_pedal_applied\" 9 \"speed_too_low\" 8 \"speed_too_high\" 7 \"p_brake_applied\" 6 \"gear_no_d\" 5 \"seatbelt\" 4 \"too_steep_downhill\" 3 \"too_steep_uphill\" 2 \"too_close\" 1 \"no_vehicle_ahead\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_crv_ex_2017_body_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\nCM_ \"honda_crv_ex_2017_body.dbc starts here\";\nBO_ 318291879 BSM_STATUS_RIGHT: 8 XXX\n SG_ BSM_ALERT : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BSM_MODE : 6|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 318291615 BSM_STATUS_LEFT: 8 XXX\n SG_ BSM_ALERT : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BSM_MODE : 6|2@0+ (1,0) [0|3] \"\" XXX\n\nVAL_ 318291879 BSM_MODE 2 \"blind_spot\" 1 \"cross_traffic\" 0 \"off\";\nVAL_ 318291615 BSM_MODE 2 \"blind_spot\" 1 \"cross_traffic\" 0 \"off\";\n"
  },
  {
    "path": "opendbc/honda_crv_ex_2017_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2018.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 13274 LKAS_HUD_A: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 13275 LKAS_HUD_B: 8 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" BDY\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"honda_crv_ex_2017_can.dbc starts here\";\n\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n \nBO_ 401 GEARBOX: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\" EON\n SG_ BOH : 45|6@0+ (1,0) [0|63] \"\" XXX\n SG_ GEAR2 : 31|8@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 47|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 446 BRAKE_MODULE: 3 VSA\n SG_ BRAKE_PRESSED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH3 : 31|32@0+ (1,0) [0|4294967295] \"\" XXX\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 344 DISTANCE_COUNTER \"\";\nCM_ SG_ 450 EPB_STATE \"3: On, 2: Disengaging, 1: Engaging, 0: Off\";\nCM_ SG_ 479 CONTROL_ON \"Set to 5 when car is being controlled\";\nCM_ SG_ 479 RELATED_TO_GAS \"bits 7, 3, and 1 set to 1 when gas not applied\";\nCM_ SG_ 479 GAS_BRAKE \"Signed value, negative when braking and positive when applying gas\";\n\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_crv_executive_2016_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_crv_executive_2016_can.dbc starts here\";\n\n\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 6 EPS\n SG_ STEER_TORQUE_SENSOR : 7|12@0- (-1,0) [-2047.5|2047.5] \"tbd\"  EON\n SG_ STEER_TORQUE_MOTOR : 23|16@0- (-1,0) [-31000|31000] \"tbd\"  EON\n SG_ STEER_CONTROL_ACTIVE : 36|1@0+ (1,0) [0|1] \"\"  EON\n SG_ STEER_STATUS : 35|4@0+ (1,0) [0|15] \"\"  EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\"  EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\"  EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 404 STEERING_CONTROL: 4 EON\n SG_ STEER_TORQUE : 7|12@0- (1,0) [-768|768] \"\" EPS\n SG_ SET_ME_X00 : 11|4@0+ (1,0) [0|15] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EPS\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 487 BRAKE_PRESSURE: 4 VSA\n SG_ BRAKE_PRESSURE1 : 7|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ BRAKE_PRESSURE2 : 9|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 891 WIPERS: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 419 GEAR_SHIFTER  32 \"D\" 8 \"R\" 4 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_crv_hybrid_2019_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2018.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 13274 LKAS_HUD_A: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 13275 LKAS_HUD_B: 8 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" BDY\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"honda_crv_hybrid_2019_can.dbc starts here\";\n\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n \nBO_ 419 GEARBOX: 8 PCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BOH : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_2 : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 344 DISTANCE_COUNTER \"\";\nCM_ SG_ 450 EPB_STATE \"3: On, 2: Disengaging, 1: Engaging, 0: Off\";\nCM_ SG_ 479 CONTROL_ON \"Set to 5 when car is being controlled\";\nCM_ SG_ 479 RELATED_TO_GAS \"bits 7, 3, and 1 set to 1 when gas not applied\";\nCM_ SG_ 479 GAS_BRAKE \"Signed value, negative when braking and positive when applying gas\";\n\nVAL_ 419 GEAR_SHIFTER  32 \"D\" 8 \"R\" 4 \"P\" ;\nVAL_ 545 ECON_ON_2 0 \"off\" 3 \"on\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_crv_touring_2016_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_crv_touring_2016_can.dbc starts here\";\n\n\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 6 EPS\n SG_ STEER_TORQUE_SENSOR : 7|12@0- (-1,0) [-2047.5|2047.5] \"tbd\"  EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_CONTROL_ACTIVE : 36|1@0+ (1,0) [0|1] \"\"  EON\n SG_ STEER_STATUS : 35|4@0+ (1,0) [0|15] \"\"  EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\"  EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\"  EON\n\nBO_ 401 GEARBOX: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\"  EON\n SG_ GEAR : 35|4@0+ (1,0) [0|15] \"\"  EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\"  EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\"  EON\n\nBO_ 404 STEERING_CONTROL: 4 EON\n SG_ STEER_TORQUE : 7|12@0- (1,0) [-768|768] \"\" EPS\n SG_ SET_ME_X00 : 11|4@0+ (1,0) [0|15] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EPS\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 487 BRAKE_PRESSURE: 4 VSA\n SG_ BRAKE_PRESSURE1 : 7|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ BRAKE_PRESSURE2 : 9|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 891 WIPERS: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\n\nCM_ SG_ 401 GEAR \"10 = reverse, 11 = transition\";\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_fit_ex_2018_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_fit_ex_2018_can.dbc starts here\";\n\n\n\nBO_ 145 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (0.02,-512) [-20|20] \"m/s2\" EON\n\nBO_ 228 STEERING_CONTROL: 5 ADAS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-3840|3840] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 316 GAS_PEDAL: 8 PCM\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 401 GEARBOX: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ DRIVERS_DOOR_OPEN : 63|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 487 BRAKE_PRESSURE: 4 VSA\n SG_ BRAKE_PRESSURE1 : 7|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ BRAKE_PRESSURE2 : 9|10@0+ (0.015625,-103) [0|1000] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 862 HIGHBEAM_CONTROL: 8 ADAS\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ ZEROS_BOH_2 : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 401 GEAR \"10 = reverse, 11 = transition\";\nCM_ SG_ 420 BRAKE_HOLD_RELATED \"On when Brake Hold engaged\";\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_insight_ex_2019_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _bosch_2018.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM EON CAM RADAR PCM EPS VSA SCM BDY XXX EPB\n\nBO_ 148 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 25|10@0+ (-0.035,17.92) [-20|20] \"m/s2\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 228 STEERING_CONTROL: 5 EON\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ SET_ME_X00_2 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-4096|4096] \"\" EPS\n SG_ STEER_DOWN_TO_ZERO : 38|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" EPS\n\nBO_ 229 BOSCH_SUPPLEMENTAL_1: 8 XXX\n SG_ SET_ME_X04 : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 8|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X80 : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X10 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 232 BRAKE_HOLD: 7 XXX\n SG_ XMISSION_SPEED : 7|14@0- (1,0) [1|0] \"\" XXX\n SG_ COMPUTER_BRAKE : 39|16@0+ (1,0) [0|0] \"\" XXX\n SG_ COMPUTER_BRAKE_REQUEST : 29|1@0+ (1,0) [0|0] \"\" XXX\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 330 STEERING_SENSORS: 8 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ STEER_SENSOR_STATUS_1 : 34|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_2 : 33|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_SENSOR_STATUS_3 : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_WHEEL_ANGLE : 47|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 EPB\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" EON\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 479 ACC_CONTROL: 8 EON\n SG_ SET_TO_0 : 20|5@0+ (1,0) [0|1] \"\" XXX\n SG_ CONTROL_ON : 23|3@0+ (1,0) [0|5] \"\" XXX\n SG_ GAS_COMMAND : 7|16@0- (1,0) [0|0] \"\" XXX\n SG_ ACCEL_COMMAND : 31|11@0- (0.01,0) [0|0] \"m/s2\" XXX\n SG_ BRAKE_LIGHTS : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_REQUEST : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_RELEASE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_STATUS : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_BRAKING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_PREPARE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LAT_ACCEL : 7|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ LONG_ACCEL : 23|16@0- (0.0015,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 495 ACC_CONTROL_ON: 8 XXX\n SG_ SET_TO_75 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_30 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH2 : 47|16@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_FF : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_3 : 6|7@0+ (1,0) [0|4095] \"\" XXX\n SG_ CONTROL_ON : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 545 XXX_16: 6 SCM\n SG_ ECON_ON : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_MODE : 37|2@0+ (1,0) [0|3] \"\" XXX\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 576 LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 577 LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 579 RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 580 RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 582 ADJACENT_LEFT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 583 ADJACENT_LEFT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 585 ADJACENT_RIGHT_LANE_LINE_1: 8 CAM\n SG_ LINE_DISTANCE_VISIBLE : 39|9@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_PROBABILITY : 46|6@0+ (0.015625,0) [0|1] \"\" XXX\n SG_ LINE_OFFSET : 23|12@0+ (0.004,-8.192) [0|1] \"Meters\" XXX\n SG_ LINE_ANGLE : 7|12@0+ (0.0005,-1.024) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 586 ADJACENT_RIGHT_LANE_LINE_2: 8 CAM\n SG_ LINE_FAR_EDGE_POSITION : 55|8@0+ (1,-128) [0|1] \"\" XXX\n SG_ LINE_SOLID : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_DASHED : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_CURVATURE : 23|12@0+ (0.00001,-0.02048) [0|1] \"\" XXX\n SG_ LINE_PARAMETER : 39|12@0+ (1,0) [0|1] \"\" XXX\n SG_ FRAME_INDEX : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ LONG_COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\n BO_ 662 SCM_BUTTONS: 4 SCM\n  SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n  SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n  SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n  SG_ CHECKSUM : 27|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 CAR_SPEED: 8 PCM\n SG_ ROUGH_CAR_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ CAR_SPEED : 7|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_3 : 39|16@0+ (0.01,0) [0|65535] \"kph\" XXX\n SG_ ROUGH_CAR_SPEED_2 : 31|8@0+ (1,0) [0|255] \"mph\" XXX\n SG_ LOCK_STATUS : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"kph\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ ZEROS_BOH : 7|24@0+ (0.002759506,0) [0|100] \"m/s\" BDY\n SG_ FCM_OFF : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_1 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BOH_6 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_TO_X1 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 804 CRUISE: 8 PCM\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ DRIVERS_DOOR_OPEN : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ CMBS_STATES : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 862 CAMERA_MESSAGES: 8 CAM\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ZEROS_BOH_2 : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 STALK_STATUS: 8 XXX\n SG_ AUTO_HEADLIGHTS : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_HOLD : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ HIGH_BEAM_FLASH : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ HEADLIGHTS_ON : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPER_SWITCH : 53|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 STALK_STATUS_2: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ LOW_BEAMS : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAMS : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARK_LIGHTS : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 13274 LKAS_HUD_A: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 13275 LKAS_HUD_B: 8 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 20|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" BDY\n\nCM_ SG_ 479 AEB_STATUS \"set for the duration of AEB event\";\nCM_ SG_ 479 AEB_BRAKING \"set when braking is commanded during AEB event\";\nCM_ SG_ 479 AEB_PREPARE \"set 1s before AEB\";\nCM_ SG_ 576 LINE_DISTANCE_VISIBLE \"Length of line visible, undecoded\";\nCM_ SG_ 577 LINE_FAR_EDGE_POSITION \"Appears to be a measure of line thickness, indicates location of the portion of the line furthest from the car, undecoded\";\nCM_ SG_ 577 LINE_PARAMETER \"Unclear if this is low quality line curvature rate or if this is something else, but it is correlated with line curvature, undecoded\";\nCM_ SG_ 577 LINE_DASHED \"1 = line is dashed\";\nCM_ SG_ 577 LINE_SOLID \"1 = line is solid\";\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\n\nCM_ \"honda_insight_ex_2019_can.dbc starts here\";\n\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n \nBO_ 419 GEARBOX: 8 PCM\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ BRAKE_ERROR_1 : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 927 RADAR_HUD: 8 RADAR\n SG_ ZEROS_BOH : 7|10@0+ (1,0) [0|127] \"\" BDY\n SG_ CMBS_OFF : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_1 : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ZEROS_BOH2 : 11|4@0+ (1,0) [0|1] \"\" XXX\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_TO_0 : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HUD_LEAD : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_TO_64 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZEROS_BOH3 : 47|7@0+ (1,0) [0|127] \"\" XXX\n SG_ ZEROS_BOH4 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\n VAL_ 419 GEAR  10 \"R\" 1 \"D\" 0 \"P\";\n VAL_ 419 GEAR_SHIFTER  32 \"D\" 16 \"N\" 8 \"R\" 4 \"P\" ;\n\nCM_ \"CHFFR_METRIC 330 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_odyssey_exl_2018_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_odyssey_exl_2018.dbc starts here\";\n\n\n\nBO_ 228 STEERING_CONTROL: 5 ADAS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-3840|3840] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 316 GAS_PEDAL: 8 PCM\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ GEAR : 7|8@0+ (1,0) [0|256] \"\" EON\n SG_ GEAR_SHIFTER : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 XXX\n SG_ EPB_BRAKE_AND_PULL : 6|1@0+ (1,0) [0|1] \"\" XXX\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 662 SCM_BUTTONS: 4 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ CRUISE_SETTING : 3|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 29|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 806 SCM_FEEDBACK: 8 SCM\n SG_ CMBS_BUTTON : 22|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ RIGHT_BLINKER : 27|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 26|1@0+ (1,0) [0|1] \"\" EON\n SG_ REVERSE_LIGHT : 18|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 891 WIPERS: 8 XXX\n SG_ WIPERS : 17|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 862 HIGHBEAM_CONTROL: 8 ADAS\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ ZEROS_BOH_2 : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 927 RADAR_HUD: 8 ADAS\n SG_ ZEROS_BOH : 7|17@0+ (1,0) [0|127] \"\" BDY\n SG_ APPLY_BRAKES_FOR_CANC : 23|1@0+ (1,0) [0|15] \"\" BDY\n SG_ ZEROS_BOH2 : 31|8@0+ (1,0) [0|127] \"\" BDY\n SG_ RESUME_INSTRUCTION : 21|1@0+ (1,0) [0|15] \"\" BDY\n SG_ ACC_ALERTS : 20|5@0+ (1,0) [0|15] \"\" BDY\n SG_ LEAD_SPEED : 39|9@0+ (1,0) [0|127] \"\" BDY\n SG_ LEAD_STATE : 46|3@0+ (1,0) [0|127] \"\" BDY\n SG_ LEAD_DISTANCE : 43|5@0+ (1,0) [0|31] \"\" BDY\n SG_ ZEROS_BOH3 : 54|7@0+ (1,0) [0|127] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 419 GEAR \"10 = reverse, 11 = transition\";\nCM_ SG_ 420 BRAKE_HOLD_RELATED \"On when Brake Hold engaged\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 806 REVERSE_LIGHT \"Might be reverse gear selected and not the lights\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnings etc...\";\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 419 GEAR_SHIFTER 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 450 EPB_STATE 3 \"engaged\" 2 \"disengaging\" 1 \"engaging\" 0 \"disengaged\" ;\nVAL_ 662 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 662 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\nVAL_ 780 HUD_LEAD 3 \"no_car\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\nVAL_ 891 WIPERS 4 \"High\" 2 \"Low\" 0 \"Off\" ;\nVAL_ 927 ACC_ALERTS 29 \"esp_active_acc_canceled\" 10 \"b_pedal_applied\" 9 \"speed_too_low\" 8 \"speed_too_high\" 7 \"p_brake_applied\" 6 \"gear_no_d\" 5 \"seatbelt\" 4 \"too_steep_downhill\" 3 \"too_steep_uphill\" 2 \"too_close\" 1 \"no_vehicle_ahead\" ;\nVAL_ 806 CMBS_BUTTON 3 \"pressed\" 0 \"released\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_odyssey_extreme_edition_2018_china_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_odyssey_extreme_edition_2018_china_can.dbc starts here\";\n\n\n\nBO_ 316 GAS_PEDAL: 8 PCM\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE_RATE : 23|16@0- (1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-2985|2985] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 401 GEARBOX: 8 PCM\n SG_ GEAR_SHIFTER : 5|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 404 STEERING_CONTROL: 4 EON\n SG_ SET_ME_X00 : 22|7@0+ (1,0) [0|127] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ COUNTER : 29|2@0+ (1,0) [0|15] \"\" EPS\n SG_ CHECKSUM : 27|4@0+ (1,0) [0|3] \"\" EPS\n SG_ STEER_TORQUE : 7|16@0- (-1,0) [-32767|32767] \"\" EPS\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ DRIVERS_DOOR_OPEN : 63|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 450 EPB_STATUS: 8 XXX\n SG_ EPB_BRAKE_AND_PULL : 6|1@0+ (1,0) [0|1] \"\" XXX\n SG_ EPB_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ EPB_STATE : 29|2@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 862 HIGHBEAM_CONTROL: 8 ADAS\n SG_ ZEROS_BOH : 7|50@0+ (1,0) [0|127] \"\" BDY\n SG_ ZEROS_BOH_2 : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ HIGHBEAMS_ON : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AUTO_HIGHBEAMS_ACTIVE : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1302 ODOMETER: 8 XXX\n SG_ ODOMETER : 7|24@0+ (1,0) [0|16777215] \"km\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 401 GEAR \"10 = reverse, 11 = transition\";\nVAL_ 399 STEER_STATUS 5 \"fault\" 4 \"no_torque_alert_2\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 401 GEAR_SHIFTER 32 \"L\" 16 \"S\" 8 \"D\" 4 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 401 GEAR 7 \"L\" 10 \"S\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\n"
  },
  {
    "path": "opendbc/honda_pilot_touring_2017_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_pilot_touring_2017_can.dbc starts here\";\n\n\n\nBO_ 145 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (0.02,-512) [-20|20] \"m/s2\" EON\n\nBO_ 228 STEERING_CONTROL: 5 ADAS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-3840|3840] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 304 GAS_PEDAL_2: 8 PCM\n SG_ ENGINE_TORQUE_ESTIMATE : 7|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ ENGINE_TORQUE_REQUEST : 23|16@0- (1,0) [-1000|1000] \"Nm\" EON\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 316 GAS_PEDAL: 8 PCM\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 419 GEAR_SHIFTER  32 \"D\" 8 \"R\" 4 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/honda_ridgeline_black_edition_2017_can_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _honda_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBU_: EBCM ADAS PCM EPS VSA SCM BDY XXX EPB EON\n\nBO_ 344 ENGINE_DATA: 8 PCM\n SG_ XMISSION_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ XMISSION_SPEED2 : 39|16@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ ODOMETER : 55|8@0+ (10,0) [0|2550] \"m\" XXX\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 380 POWERTRAIN_DATA: 8 PCM\n SG_ PEDAL_GAS : 7|8@0+ (1,0) [0|255] \"\" EON\n SG_ ENGINE_RPM : 23|16@0+ (1,0) [0|15000] \"rpm\" EON\n SG_ GAS_PRESSED : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ ACC_STATUS : 38|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH_17C : 37|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_SWITCH : 32|1@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BOH2_17C : 47|10@0+ (1,0) [0|1] \"rpm\" EON\n SG_ BRAKE_PRESSED : 53|1@0+ (1,0) [0|1] \"\" EON\n SG_ BOH3_17C : 52|5@0+ (1,0) [0|1] \"rpm\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 420 VSA_STATUS: 8 VSA\n SG_ USER_BRAKE : 7|16@0+ (0.015625,-1.609375) [0|1000] \"\" EON\n SG_ COMPUTER_BRAKING : 23|1@0+ (1,0) [0|1] \"\" EON\n SG_ ESP_DISABLED : 28|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_RELATED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_HOLD_ACTIVE : 46|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_HOLD_ENABLED : 45|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 427 STEER_MOTOR_TORQUE: 3 EPS\n SG_ CONFIG_VALID : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ MOTOR_TORQUE : 1|10@0+ (1,0) [0|256] \"\" EON\n SG_ OUTPUT_DISABLED : 22|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 21|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 19|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 432 STANDSTILL: 7 VSA\n SG_ CONTROLLED_STANDSTILL : 0|1@0+ (1,0) [0|1] \"\" EON\n SG_ WHEELS_MOVING : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_1 : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ BRAKE_ERROR_2 : 9|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 464 WHEEL_SPEEDS: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_FR : 8|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RL : 25|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ WHEEL_SPEED_RR : 42|15@0+ (0.01,0) [0|250] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 490 VEHICLE_DYNAMICS: 8 VSA\n SG_ LONG_ACCEL : 23|16@0- (0.0015384,0) [-20|20] \"m/s2\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 506 BRAKE_COMMAND: 8 ADAS\n SG_ COMPUTER_BRAKE : 7|10@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00 : 13|5@0+ (1,0) [0|1] \"\" EBCM\n SG_ BRAKE_PUMP_REQUEST : 8|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_2 : 23|3@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_OVERRIDE : 20|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_X00_3 : 19|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_FAULT_CMD : 18|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_CANCEL_CMD : 17|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ COMPUTER_BRAKE_REQUEST : 16|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ SET_ME_1 : 31|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ AEB_REQ_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ AEB_REQ_2 : 26|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_LIGHTS : 39|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ CRUISE_STATES : 38|7@0+ (1,0) [0|1] \"\" EBCM\n SG_ CHIME : 47|3@0+ (1,0) [0|7] \"\" EBCM\n SG_ SET_ME_X00_4 : 44|1@0+ (1,0) [0|1] \"\" EBCM\n SG_ FCW : 43|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ AEB_STATUS : 41|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X00_5 : 55|8@0+ (1,0) [0|0] \"\" EBCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EBCM\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EBCM\n\nBO_ 597 ROUGH_WHEEL_SPEED: 8 VSA\n SG_ WHEEL_SPEED_FL : 7|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_FR : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RL : 23|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ WHEEL_SPEED_RR : 31|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ SET_TO_X55 : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ SET_TO_X55_2 : 47|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|15] \"\" EON\n\nBO_ 773 SEATBELT_STATUS: 7 BDY\n SG_ SEATBELT_DRIVER_LAMP : 7|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_UNLATCHED : 10|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_PASS_LATCHED : 11|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_UNLATCHED : 12|1@0+ (1,0) [0|1] \"\" EON\n SG_ SEATBELT_DRIVER_LATCHED : 13|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_OFF : 14|1@0+ (1,0) [0|1] \"\" EON\n SG_ PASS_AIRBAG_ON : 15|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 777 LOCK_STATUS: 8 XXX\n SG_ DOORS_UNLOCKED : 54|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOORS_LOCKED : 55|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 780 ACC_HUD: 8 ADAS\n SG_ PCM_SPEED : 7|16@0+ (0.01,0) [0|250] \"kph\" BDY\n SG_ PCM_GAS : 23|8@0+ (1,0) [0|127] \"\" BDY\n SG_ CRUISE_SPEED : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ DTC_MODE : 39|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 38|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ACC_PROBLEM : 37|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF : 36|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_OFF_2 : 35|1@0+ (1,0) [0|1] \"\" BDY\n SG_ FCM_PROBLEM : 34|1@0+ (1,0) [0|1] \"\" BDY\n SG_ RADAR_OBSTRUCTED : 33|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ENABLE_MINI_CAR : 32|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE : 47|2@0+ (1,0) [0|3] \"\" BDY\n SG_ HUD_LEAD : 45|2@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_3 : 43|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_4 : 42|1@0+ (1,0) [0|3] \"\" BDY\n SG_ BOH_5 : 41|1@0+ (1,0) [0|3] \"\" BDY\n SG_ CRUISE_CONTROL_LABEL : 40|1@0+ (1,0) [0|3] \"\" BDY\n SG_ SET_ME_X01_2 : 55|1@0+ (1,0) [0|1] \"\" BDY\n SG_ IMPERIAL_UNIT : 54|1@0+ (1,0) [0|1] \"\" BDY\n SG_ HUD_DISTANCE_3 : 52|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CHIME : 51|3@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X01 : 48|1@0+ (1,0) [0|1] \"\" BDY\n SG_ ICONS : 63|2@0+ (1,0) [0|1] \"\" BDY\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" BDY\n\nBO_ 804 CRUISE: 8 PCM\n SG_ HUD_SPEED_KPH : 7|8@0+ (1,0) [0|255] \"kph\" EON\n SG_ HUD_SPEED_MPH : 15|8@0+ (1,0) [0|255] \"mph\" EON\n SG_ TRIP_FUEL_CONSUMED : 23|16@0+ (1,0) [0|255] \"\" EON\n SG_ CRUISE_SPEED_PCM : 39|8@0+ (1,0) [0|255] \"\" EON\n SG_ BOH2 : 47|8@0- (1,0) [0|255] \"\" EON\n SG_ BOH3 : 55|8@0+ (1,0) [0|255] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 829 LKAS_HUD: 5 ADAS\n SG_ CAM_TEMP_HIGH : 7|1@0+ (1,0) [0|255] \"\" BDY\n SG_ SET_ME_X41 : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ BOH : 6|7@0+ (1,0) [0|127] \"\" BDY\n SG_ DASHED_LANES : 14|1@0+ (1,0) [0|1] \"\" BDY\n SG_ DTC : 13|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_PROBLEM : 12|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LKAS_OFF : 11|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SOLID_LANES : 10|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_RIGHT : 9|1@0+ (1,0) [0|1] \"\" BDY\n SG_ STEERING_REQUIRED : 8|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BOH : 23|2@0+ (1,0) [0|4] \"\" BDY\n SG_ LDW_PROBLEM : 21|1@0+ (1,0) [0|1] \"\" BDY\n SG_ BEEP : 17|2@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_ON : 28|1@0+ (1,0) [0|1] \"\" BDY\n SG_ LDW_OFF : 27|1@0+ (1,0) [0|1] \"\" BDY\n SG_ CLEAN_WINDSHIELD : 26|1@0+ (1,0) [0|1] \"\" BDY\n SG_ SET_ME_X48 : 31|8@0+ (1,0) [0|255] \"\" BDY\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" BDY\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|15] \"\" BDY\n\nBO_ 892 CRUISE_PARAMS: 8 PCM\n SG_ CRUISE_SPEED_OFFSET : 31|8@0- (0.1,0) [-128|127] \"kph\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n\nBO_ 1029 DOORS_STATUS: 8 BDY\n SG_ DOOR_OPEN_FL : 37|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_FR : 38|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RL : 39|1@0+ (1,0) [0|1] \"\" EON\n SG_ DOOR_OPEN_RR : 40|1@0+ (1,0) [0|1] \"\" EON\n SG_ TRUNK_OPEN : 41|1@0+ (1,0) [0|1] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nCM_ SG_ 490 LONG_ACCEL \"wheel speed derivative, noisy and zero snapping\";\nCM_ SG_ 506 AEB_REQ_1 \"set for duration of suspected AEB event\";\nCM_ SG_ 773 PASS_AIRBAG_ON \"Might just be indicator light\";\nCM_ SG_ 773 PASS_AIRBAG_OFF \"Might just be indicator light\";\nCM_ SG_ 780 CRUISE_SPEED \"255 = no speed\";\nCM_ SG_ 804 CRUISE_SPEED_PCM \"255 = no speed\";\nCM_ SG_ 829 BEEP \"beeps are pleasant, chimes are for warnngs etc...\";\n\n\nVAL_ 506 FCW 3 \"fcw\" 2 \"fcw\" 1 \"fcw\" 0 \"no_fcw\" ;\nVAL_ 506 CHIME 4 \"double_chime\" 3 \"single_chime\" 2 \"continuous_chime\" 1 \"repeating_chime\" 0 \"no_chime\" ;\nVAL_ 506 AEB_STATUS 3 \"aeb_prepare\" 2 \"aeb_ready\" 1 \"aeb_braking\" 0 \"no_aeb\" ;\nVAL_ 780 CRUISE_SPEED 255 \"no_speed\" 252 \"stopped\" ;\nVAL_ 780 HUD_LEAD 3 \"acc_off\" 2 \"solid_car\" 1 \"dashed_car\" 0 \"no_car\" ;\nVAL_ 829 BEEP 3 \"single_beep\" 2 \"triple_beep\" 1 \"repeated_beep\" 0 \"no_beep\" ;\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 512 GAS_COMMAND: 6 EON\n SG_ GAS_COMMAND : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ GAS_COMMAND2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" INTERCEPTOR\n SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\nBO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n SG_ INTERCEPTOR_GAS : 7|16@0+ (0.253984064,-83.3) [0|1] \"\" EON\n SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.126992032,-83.3) [0|1] \"\" EON\n SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\nVAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nCM_ \"honda_ridgeline_black_edition_2017_can.dbc starts here\";\n\n\n\nBO_ 145 KINEMATICS: 8 XXX\n SG_ LAT_ACCEL : 7|10@0+ (0.02,-512) [-20|20] \"m/s2\" EON\n\nBO_ 228 STEERING_CONTROL: 5 ADAS\n SG_ STEER_TORQUE : 7|16@0- (1,0) [-3840|3840] \"\" EPS\n SG_ STEER_TORQUE_REQUEST : 23|1@0+ (1,0) [0|1] \"\" EPS\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|0] \"\" EPS\n SG_ COUNTER : 37|2@0+ (1,0) [0|3] \"\" EPS\n SG_ CHECKSUM : 35|4@0+ (1,0) [0|3] \"\" EPS\n\nBO_ 316 GAS_PEDAL: 8 PCM\n SG_ CAR_GAS : 39|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 342 STEERING_SENSORS: 6 EPS\n SG_ STEER_ANGLE : 7|16@0- (-0.1,0) [-500|500] \"deg\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-1,0) [-3000|3000] \"deg/s\" EON\n SG_ COUNTER : 45|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 43|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 399 STEER_STATUS: 7 EPS\n SG_ STEER_TORQUE_SENSOR : 7|16@0- (-1,0) [-31000|31000] \"tbd\" EON\n SG_ STEER_ANGLE_RATE : 23|16@0- (-0.1,0) [-31000|31000] \"deg/s\" EON\n SG_ STEER_STATUS : 39|4@0+ (1,0) [0|15] \"\" EON\n SG_ STEER_CONTROL_ACTIVE : 35|1@0+ (1,0) [0|1] \"\" EON\n SG_ STEER_CONFIG_INDEX : 43|4@0+ (1,0) [0|15] \"\" EON\n SG_ COUNTER : 53|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 51|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 419 GEARBOX: 8 PCM\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n SG_ GEAR_SHIFTER : 29|6@0+ (1,0) [0|63] \"\" EON\n SG_ GEAR : 7|8@0+ (1,0) [0|255] \"\" EON\n\nBO_ 422 SCM_BUTTONS: 8 SCM\n SG_ CRUISE_BUTTONS : 7|3@0+ (1,0) [0|7] \"\" EON\n SG_ LIGHTS_SETTING : 1|2@0+ (1,0) [0|3] \"\" EON\n SG_ MAIN_ON : 47|1@0+ (1,0) [0|1] \"\" EON\n SG_ CRUISE_SETTING : 43|2@0+ (1,0) [0|3] \"\" EON\n SG_ COUNTER : 61|2@0+ (1,0) [0|3] \"\" EON\n SG_ CHECKSUM : 59|4@0+ (1,0) [0|3] \"\" EON\n\nBO_ 660 SCM_FEEDBACK: 8 SCM\n SG_ RIGHT_BLINKER : 6|1@0+ (1,0) [0|1] \"\" EON\n SG_ LEFT_BLINKER : 5|1@0+ (1,0) [0|1] \"\" EON\n SG_ WIPERS_SPEED : 4|2@0+ (1,0) [0|3] \"\" EON\n\nVAL_ 399 STEER_STATUS 6 \"tmp_fault\" 5 \"fault_1\" 4 \"no_torque_alert_2\" 3 \"low_speed_lockout\" 2 \"no_torque_alert_1\" 0 \"normal\" ;\nVAL_ 419 GEAR_SHIFTER  32 \"D\" 8 \"R\" 4 \"P\" ;\nVAL_ 422 CRUISE_BUTTONS 7 \"tbd\" 6 \"tbd\" 5 \"tbd\" 4 \"accel_res\" 3 \"decel_set\" 2 \"cancel\" 1 \"main\" 0 \"none\" ;\nVAL_ 422 LIGHTS_SETTING 3 \"high_beam\" 2 \"low_beam\" 1 \"position\" 0 \"no_lights\" ;\nVAL_ 422 CRUISE_SETTING 3 \"distance_adj\" 2 \"tbd\" 1 \"lkas_button\" 0 \"none\" ;\n\nCM_ \"CHFFR_METRIC 342 STEER_ANGLE STEER_ANGLE 0.36 180; CHFFR_METRIC 380 ENGINE_RPM ENGINE_RPM 1 0; CHFFR_METRIC 804 ENGINE_TEMPERATURE ENGINE_TEMPERATURE 1 0\";\n"
  },
  {
    "path": "opendbc/hyundai_kia_generic.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n NS_DESC_\n CM_\n BA_DEF_\n BA_\n VAL_\n CAT_DEF_\n CAT_\n FILTER\n BA_DEF_DEF_\n EV_DATA_\n ENVVAR_DATA_\n SGTYPE_\n SGTYPE_VAL_\n BA_DEF_SGTYPE_\n BA_SGTYPE_\n SIG_TYPE_REF_\n VAL_TABLE_\n SIG_GROUP_\n SIG_VALTYPE_\n SIGTYPE_VALTYPE_\n BO_TX_BU_\n BA_DEF_REL_\n BA_REL_\n BA_DEF_DEF_REL_\n BU_SG_REL_\n BU_EV_REL_\n BU_BO_REL_\n SG_MUL_VAL_\n\nBS_:\n\nBU_: IAP ODS _4WD BCM HUD DATC MDPS AAF_Tester AEMC SMK _4WD EPB CUBIS MTS TMU EVP CGW TPMS LPI DI_BOX SPAS EMS LCA TCU IBOX FATC AFLS FPCM SCC AHLS AVM ABS SNV OPI PGS SAS AAF Dummy LDWS_LKAS LVR ESC PSB CLU ECS ACU REA\n\nBO_ 1532 ODS13: 5 ODS\n SG_ CR_Ods_ID : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_Chksum_H : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  Dummy\n SG_ CR_Ods_Chksum_L : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  Dummy\n SG_ CR_Ods_RomID_H : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  Dummy\n SG_ CR_Ods_RomID_L : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  Dummy\n\nBO_ 1531 ODS12: 8 ODS\n SG_ CR_Ods_SerNum0 : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum1 : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum2 : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum3 : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum4 : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum5 : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum6 : 48|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n SG_ CR_Ods_SerNum7 : 56|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ACU\n\nBO_ 1530 ODS11: 8 ODS\n SG_ CF_Ods_PrcCmd : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  Dummy\n SG_ CF_Ods_BtsFail : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  Dummy\n SG_ CF_Ods_AcuRcvSN : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ACU\n SG_ CF_Ods_EolCal : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ACU\n SG_ CF_Ods_PsFail : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ACU\n SG_ CF_Ods_EcuFail : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ACU\n SG_ CF_Ods_WgtStat : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ACU\n SG_ CF_Ods_OccStat : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ACU\n SG_ CR_Wcs_ErrStat : 32|8@1+ (1.0,0.0) [0.0|63.0] \"\"  ACU\n SG_ CR_Wcs_ClassStat : 40|8@1+ (1.0,0.0) [0.0|4.0] \"\"  ACU,BCM\n\nBO_ 1017 ECS12: 4 ECS\n SG_ Height_FL : 0|8@1+ (1.0,-128.0) [-128.0|127.0] \"mm\"  AFLS\n SG_ Height_FR : 8|8@1+ (1.0,-128.0) [-128.0|127.0] \"mm\"  AFLS\n SG_ Height_RL : 16|8@1+ (1.0,-128.0) [-128.0|127.0] \"mm\"  AFLS\n SG_ Height_RR : 24|8@1+ (1.0,-128.0) [-128.0|127.0] \"mm\"  AFLS\n\nBO_ 1268 SPAS12: 8 SPAS\n SG_ CF_Spas_HMI_Stat : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ CF_Spas_Disp : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,EMS\n SG_ CF_Spas_FIL_Ind : 10|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_FIR_Ind : 13|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_FOL_Ind : 16|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_FOR_Ind : 19|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_VolDown : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_RIL_Ind : 24|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_RIR_Ind : 27|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_FLS_Alarm : 30|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_ROL_Ind : 32|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_ROR_Ind : 35|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_FCS_Alarm : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_FI_Ind : 40|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_RI_Ind : 43|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU\n SG_ CF_Spas_FRS_Alarm : 46|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_FR_Alarm : 48|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_Spas_RR_Alarm : 50|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_Spas_BEEP_Alarm : 52|4@1+ (1.0,0.0) [0.0|15.0] \"\"  BCM,CLU\n SG_ CF_Spas_StatAlarm : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Spas_RLS_Alarm : 57|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_RCS_Alarm : 59|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_RRS_Alarm : 61|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1265 CLU11: 4 CLU\n SG_ CF_Clu_CruiseSwState : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  EMS,LDWS_LKAS,SCC\n SG_ CF_Clu_CruiseSwMain : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,LDWS_LKAS,SCC\n SG_ CF_Clu_SldMainSW : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Clu_ParityBit1 : 5|1@1+ (1.0,0.0) [0.0|1.0] \"pulse count\"  EMS\n SG_ CF_Clu_VanzDecimal : 6|2@1+ (0.125,0.0) [0.0|0.375] \"\"  EMS\n SG_ CF_Clu_Vanz : 8|9@1+ (0.5,0.0) [0.0|255.5] \"km/h or MPH\"  BCM,CUBIS,EMS,IBOX,LDWS_LKAS,MDPS,SCC\n SG_ CF_Clu_SPEED_UNIT : 17|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CUBIS,EMS,IBOX,LDWS_LKAS,MDPS,SCC\n SG_ CF_Clu_DetentOut : 18|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AVM,BCM,LCA,PGS,SPAS\n SG_ CF_Clu_RheostatLevel : 19|5@1+ (1.0,0.0) [0.0|31.0] \"\"  AVM,BCM,LCA,PGS,SPAS\n SG_ CF_Clu_CluInfo : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM\n SG_ CF_Clu_AmpInfo : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM\n SG_ CF_Clu_AliveCnt1 : 28|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AHLS,EMS,EPB,LDWS_LKAS,MDPS,SCC\n\nBO_ 1492 TMU_GW_PE_01: 8 CLU\n SG_ TMU_IVRActivity : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n SG_ TMU_PhoneActivity : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n\nBO_ 1491 HU_DATC_PE_00: 8 CLU\n SG_ HU_VRActivity : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n SG_ HU_PhoneActivity : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n SG_ BlowerNoiseControl : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n\nBO_ 1490 HU_DATC_E_02: 8 CLU\n SG_ HU_DATC_RearOnOffSet : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n SG_ HU_DATC_ADSOnOffSet : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n\nBO_ 1479 EMS21: 8 EMS\n SG_ SCR_LEVEL_WARN_LAMP : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ SCR_LEVEL_WARN : 1|3@1+ (1.0,0.0) [0.0|4.0] \"\"  CLU\n SG_ SCR_SYS_ERROR_WARN : 4|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ SCR_SYSTEM_WARN_LAMP : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ SCR_INDUCEMENT_EXIT_COND : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ SCR_UREA_LEVEL : 16|8@1+ (0.5,0.0) [0.0|100.0] \"%\"  CLU\n SG_ SCR_NO_REMAINING_RESTARTS : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ SCR_REMAINING_DISTANCE : 32|16@1+ (1.0,0.0) [0.0|25000.0] \"km\"  CLU\n\nBO_ 1472 GW_Warning_PE: 8 BCM\n SG_ Audio_VolumeDown : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ Pas_Spkr_Flh_Alarm : 48|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ Pas_Spkr_Fcnt_Alarm : 50|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ Pas_Spkr_Frh_Alarm : 52|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ Pas_Spkr_Rlh_Alarm : 56|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,PGS\n SG_ Pas_Spkr_Rcnt_Alarm : 58|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ Pas_Spkr_Rrh_Alarm : 60|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,PGS\n\nBO_ 1984 CAL_SAS11: 2 ESC\n SG_ CCW : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  SAS\n SG_ SAS_CID : 4|11@1+ (1.0,0.0) [0.0|2047.0] \"\"  SAS\n\nBO_ 1456 CLU12: 4 CLU\n SG_ CF_Clu_Odometer : 0|24@1+ (0.1,0.0) [0.0|1677721.4] \"km\"  _4WD,AAF,BCM,CUBIS,EMS,EPB,IBOX,LDWS_LKAS,SCC,TPMS\n\nBO_ 688 SAS11: 5 MDPS\n SG_ SAS_Angle : 0|16@1- (0.1,0.0) [-3276.8|3276.7] \"Deg\"  _4WD,ACU,AFLS,AVM,CLU,ECS,EMS,ESC,IBOX,LCA,LDWS_LKAS,PGS,PSB,SCC,SPAS,TCU,_4WD,ACU,AFLS,AVM,BCM,CLU,ECS,EMS,ESC,IBOX,LCA,LDWS_LKAS,PGS,PSB,SCC,SPAS,TCU\n SG_ SAS_Speed : 16|8@1+ (4.0,0.0) [0.0|1016.0] \"\"  AFLS,ECS,ESC,IBOX,LDWS_LKAS,SCC,SPAS,TCU,AFLS,ECS,ESC,IBOX,LDWS_LKAS,SCC,SPAS,TCU\n SG_ SAS_Stat : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ECS,ESC,IBOX,LDWS_LKAS,PSB,SCC,SPAS,TCU,ECS,ESC,IBOX,LDWS_LKAS,PSB,SCC,SPAS,TCU\n SG_ MsgCount : 32|4@1+ (1.0,0.0) [0.0|15.0] \"\"  ECS,ESC,IBOX,LDWS_LKAS,PSB,SCC,SPAS,ECS,ESC,IBOX,LDWS_LKAS,PSB,SCC,SPAS\n SG_ CheckSum : 36|4@1+ (1.0,0.0) [0.0|15.0] \"\"  ECS,EMS,ESC,IBOX,LDWS_LKAS,PSB,SCC,SPAS,ECS,EMS,ESC,IBOX,LDWS_LKAS,PSB,SCC,SPAS\n\nBO_ 1441 ACU12: 8 ACU\n SG_ CR_Acu_SN : 0|64@1+ (1.0,0.0) [0.0|0.0] \"\"  ODS\n\nBO_ 1440 ACU11: 8 ACU\n SG_ CF_Ods_SNRcv : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS\n SG_ CF_Ods_IDRcv : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS\n SG_ CF_Ods_RZReq : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS\n SG_ CF_Abg_DepInhEnt : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS\n SG_ CF_Abg_DepEnt : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS\n SG_ CF_PasBkl_FltStat : 28|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS,PSB\n SG_ CF_DriBkl_FltStat : 29|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS,PSB\n SG_ CF_PasBkl_Stat : 30|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,ODS,PSB,TMU\n SG_ CF_DriBkl_Stat : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ODS,PSB\n SG_ CF_SWL_Ind : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CUBIS,IBOX\n SG_ CF_Acu_FltStat : 34|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CUBIS,IBOX\n SG_ CF_Acu_ExtOfSab : 36|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU,CUBIS,IBOX\n SG_ CF_Acu_Dtc : 40|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  CUBIS,IBOX\n SG_ CF_Acu_NumOfFlt : 56|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CUBIS,IBOX\n\nBO_ 1437 AHLS11: 8 AHLS\n SG_ CF_Ahls_WarnLamp : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Ahls_WarnMsg : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1434 PSB11: 2 PSB\n SG_ PSB_LH_FAIL : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ PSB_LH_TGL : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ PSB_LH_ACT : 3|4@1+ (1.0,0.0) [0.0|4.0] \"\"  Dummy\n SG_ PSB_RH_FAIL : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ PSB_RH_TGL : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ PSB_RH_ACT : 11|4@1+ (1.0,0.0) [0.0|4.0] \"\"  Dummy\n\nBO_ 916 TCS13: 8 ESC\n SG_ aBasis : 0|11@1+ (0.01,-10.23) [-10.23|10.24] \"m/s^2\"  EMS,SCC\n SG_ BrakeLight : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,SCC\n SG_ DCEnable : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,SCC\n SG_ AliveCounterTCS : 13|3@1+ (1.0,0.0) [0.0|7.0] \"\"  EMS,SCC\n SG_ Pre_TCS_CTL : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  Vector__XXX\n SG_ EBA_ACK : 17|1@1+ (1.0,0.0) [0.0|1.0] \"\"  Vector__XXX\n SG_ FCA_ACK : 18|1@1+ (1.0,0.0) [0.0|1.0] \"\"  Vector__XXX\n SG_ DF_BF_STAT : 19|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCW\n SG_ SCCReqLim : 21|2@1+ (1.0,0.0) [0.0|3.0] \"\"  SCC\n SG_ TQI_SCC : 23|9@1+ (0.390625,0.0) [0.0|199.609375] \"%\"  Vector__XXX\n SG_ ACCEL_REF_ACC : 32|11@1+ (0.01,-10.23) [-10.23|10.24] \"m/s^2\"  EMS,SCC\n SG_ ACCEnable : 43|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,SCC\n SG_ DriverOverride : 45|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,SCC\n SG_ StandStill : 47|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,SCC\n SG_ CheckSum_TCS3 : 48|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS,SCC\n SG_ ACC_EQUIP : 52|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,SCC\n SG_ PBRAKE_ACT : 53|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,SCC\n SG_ ACC_REQ : 54|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ DriverBraking : 55|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,SCC\n SG_ CF_VSM_Coded : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  SCC\n SG_ CF_VSM_Avail : 57|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,SCC\n SG_ CF_VSM_Handshake : 59|1@1+ (1.0,0.0) [0.0|1.0] \"\"  SCC\n SG_ CF_DriBkeStat : 60|1@1+ (1.0,0.0) [0.0|1.0] \"\"  SCC\n SG_ CF_VSM_ConfSwi : 61|2@1+ (1.0,0.0) [0.0|3.0] \"\"  SCC\n SG_ AEB_EQUIP : 63|1@1+ (1.0,0.0) [0.0|1.0] \"\"  SCC\n\nBO_ 1427 TPMS11: 6 BCM\n SG_ TPMS_W_LAMP : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,CUBIS,HUD,IBOX,CLU,CUBIS,HUD,IBOX\n SG_ TREAD_W_LAMP : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,CUBIS,HUD,IBOX,CLU,CUBIS,HUD,IBOX\n SG_ POS_FL_W_LAMP : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,CUBIS,HUD,IBOX\n SG_ POS_FR_W_LAMP : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,CUBIS,HUD,IBOX\n SG_ POS_RL_W_LAMP : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,CUBIS,HUD,IBOX\n SG_ POS_RR_W_LAMP : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,CUBIS,HUD,IBOX\n SG_ STATUS_TPMS : 8|3@1+ (1.0,0.0) [0.0|0.0] \"\"  CLU\n SG_ UNIT : 11|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ PRESSURE_FL : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ PRESSURE_FR : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ PRESSURE_RL : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ PRESSURE_RR : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n\nBO_ 915 TCS12: 4 ESC\n SG_ SA_COUNT : 0|16@1+ (2.0,-32768.0) [-32768.0|98302.0] \"\"  _4WD,ACU,MDPS\n SG_ SA_Z_COUNT : 16|15@1+ (2.0,-32768.0) [-32768.0|32766.0] \"\"  _4WD,ACU,MDPS\n SG_ SA_Z_FLAG : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,MDPS\n\nBO_ 1170 EMS19: 8 EMS\n SG_ CF_Ems_BrkReq : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX,TCU\n SG_ CF_Ems_DnShftReq : 1|4@1+ (1.0,0.0) [0.0|14.0] \"\"  IBOX,TCU\n SG_ CF_Ems_RepModChk : 5|2@1+ (1.0,0.0) [0.0|3.0] \"\"  IBOX\n SG_ CF_Ems_AAFOpenReq : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AAF,IBOX\n SG_ CF_Ems_DecelReq : 8|12@1+ (0.0010,-4.094) [-4.094|0.0] \"m/s^2\"  ESC,IBOX,TCU\n SG_ CR_Ems_BstPre : 20|12@1+ (1.322,0.0) [0.0|4094.0] \"hPa\"  CLU,IBOX\n SG_ CR_Ems_EngOilTemp : 32|8@1+ (0.75,-40.0) [0.0|254.0] \"deg\"  CLU,IBOX\n SG_ DPF_LAMP_STAT : 40|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,IBOX\n SG_ BAT_LAMP_STAT : 42|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_ModeledAmbTemp : 48|8@1+ (0.5,-41.0) [-41.0|85.5] \"deg\"  AAF,IBOX\n SG_ CF_Ems_OPSFail : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_AliveCounterEMS9 : 58|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AAF,ABS,CUBIS,ECS,EPB,IBOX,MDPS,REA,SCC,SMK,TCU\n SG_ CF_Ems_ChecksumEMS9 : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AAF,ABS,CUBIS,ECS,EPB,IBOX,MDPS,REA,SCC,SMK,TCU\n\nBO_ 1425 AFLS11: 2 AFLS\n SG_ AFLS_STAT : 1|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Afls_TrfChgStat : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Afls_LedHLStat : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 912 SPAS11: 7 SPAS\n SG_ CF_Spas_Stat : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  ESC,MDPS\n SG_ CF_Spas_TestMode : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  MDPS\n SG_ CR_Spas_StrAngCmd : 8|16@1- (0.1,0.0) [-3276.8|3276.7] \"\"  MDPS\n SG_ CF_Spas_BeepAlarm : 24|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ CF_Spas_Mode_Seq : 28|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Spas_AliveCnt : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  MDPS\n SG_ CF_Spas_Chksum : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  MDPS\n SG_ CF_Spas_PasVol : 48|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CGW,CLU\n\nBO_ 1168 EPB11: 7 EPB\n SG_ EPB_I_LAMP : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  BCM,CLU,CUBIS,ESC,IBOX\n SG_ EPB_F_LAMP : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,CUBIS,ESC,IBOX\n SG_ EPB_ALARM : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,ESC\n SG_ EPB_CLU : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU,ESC\n SG_ EPB_SWITCH : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  ESC,SCC\n SG_ EPB_RBL : 18|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,ESC\n SG_ EPB_STATUS : 19|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,EMS,ESC,SCC,TCU\n SG_ EPB_FRC_ERR : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,ESC,SCC,TCU\n SG_ EPB_DBF_STAT : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC\n SG_ ESP_ACK : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC\n SG_ EPB_DBF_REQ : 26|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC\n SG_ EPB_FAIL : 29|3@1+ (1.0,0.0) [0.0|7.0] \"\"  ESC,SCC\n SG_ EPB_FORCE : 32|12@1+ (1.0,-1000.0) [-1000.0|3000.0] \"\"  ESC\n SG_ EPB_DBF_DECEL : 48|8@1+ (0.01,0.0) [0.0|2.54] \"g\"  ESC\n\nBO_ 399 EMS_H12: 8 EMS\n SG_ R_TqAcnApvC : 0|8@1+ (0.2,0.0) [0.0|51.0] \"Nm\"  DATC,IBOX\n SG_ R_PAcnC : 8|8@1+ (125.0,0.0) [0.0|31875.0] \"hPa\"  DATC,IBOX\n SG_ TQI_B : 16|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  ABS,ESC,IBOX\n SG_ SLD_VS : 24|8@1+ (1.0,0.0) [0.0|255.0] \"km/h\"  CLU,IBOX\n SG_ CF_CdaStat : 32|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AEMC,IBOX,TCU\n SG_ CF_Ems_IsgStat : 35|3@1+ (1.0,0.0) [0.0|7.0] \"\"  ABS,BCM,CLU,DATC,EPB,ESC,IBOX,LDWS_LKAS,MDPS,SMK,TCU\n SG_ CF_Ems_OilChg : 38|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_EtcLimpMod : 39|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ R_NEngIdlTgC : 40|8@1+ (10.0,0.0) [0.0|2550.0] \"rpm\"  DATC,IBOX,TCU\n SG_ CF_Ems_UpTarGr : 48|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_DownTarGr : 49|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_DesCurGr : 50|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,IBOX\n SG_ CF_Ems_SldAct : 54|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_SldPosAct : 55|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_HPresStat : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,TCU\n SG_ CF_Ems_IsgBuz : 57|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_IdlStpFCO : 58|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_FCopen : 59|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Ems_ActEcoAct : 60|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX,TCU\n SG_ CF_Ems_EngRunNorm : 61|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,ESC,IBOX,TCU\n SG_ CF_Ems_IsgStat2 : 62|2@1+ (2.0,0.0) [0.0|3.0] \"\"  CLU,IBOX,TCU\n\nBO_ 1419 LCA11: 8 LCA\n SG_ CF_Lca_Stat : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  BCM,CLU\n SG_ CF_Rcta_Stat : 4|4@1+ (1.0,0.0) [0.0|15.0] \"\"  BCM,CLU\n SG_ CF_Lca_IndLeft : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_Rcw_Stat : 10|4@1+ (1.0,0.0) [0.0|15.0] \"\"  BCM,CLU\n SG_ CF_RCW_Warning : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_Lca_IndRight : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_Lca_SndWan_Stat : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_FR_SndWan : 20|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU\n SG_ CF_FL_SndWan : 21|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU\n SG_ CF_RR_SndWan : 22|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU\n SG_ CF_RL_SndWan : 23|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU\n SG_ CF_Lca_IndBriLeft : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  BCM,CLU\n SG_ CF_Lca_IndBriRight : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  BCM,CLU\n SG_ CF_RCTA_IndBriLeft : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  BCM,CLU\n SG_ CF_RCTA_IndBriRight : 48|8@1+ (1.0,0.0) [0.0|255.0] \"\"  BCM,CLU\n SG_ CF_RCTA_IndLeft : 56|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_RCTA_IndRight : 58|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n SG_ CF_SndWarnForClu : 60|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n\nBO_ 906 ABS11: 8 ABS\n SG_ ABS_DEF : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,EMS,SPAS,TCU\n SG_ EBD_DEF : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,SPAS,TCU\n SG_ ABS_ACT : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,EPB,SPAS,TCU\n SG_ ABS_W_LAMP : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,CUBIS,MTS,TMU\n SG_ EBD_W_LAMP : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU\n SG_ ABS_DIAG : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU\n SG_ ESS_STAT : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,BCM,CLU,EMS\n\nBO_ 903 WHL_PUL11: 6 ABS\n SG_ WHL_PUL_FL : 0|8@1+ (0.5,0.0) [0.0|127.5] \"pulse count\"  CUBIS,EPB,IBOX,SPAS,TMU,TPMS,CUBIS,EPB,IBOX,LDWS_LKAS,SPAS,TMU,TPMS\n SG_ WHL_PUL_FR : 8|8@1+ (0.5,0.0) [0.0|127.5] \"pulse count\"  CUBIS,EPB,IBOX,SPAS,TMU,TPMS,CUBIS,EPB,IBOX,LDWS_LKAS,SPAS,TMU,TPMS\n SG_ WHL_PUL_RL : 16|8@1+ (0.5,0.0) [0.0|127.5] \"pulse count\"  CUBIS,EPB,IBOX,SPAS,TMU,TPMS,CUBIS,EPB,IBOX,LDWS_LKAS,SPAS,TMU,TPMS\n SG_ WHL_PUL_RR : 24|8@1+ (0.5,0.0) [0.0|127.5] \"pulse count\"  CUBIS,EPB,IBOX,SPAS,TMU,TPMS,CUBIS,EPB,IBOX,LDWS_LKAS,SPAS,TMU,TPMS\n SG_ WHL_DIR_FL : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EPB,SPAS,TPMS,EPB,LCA,SPAS,TPMS\n SG_ WHL_DIR_FR : 34|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EPB,SPAS,TPMS,EPB,LCA,SPAS,TPMS\n SG_ WHL_DIR_RL : 36|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EPB,SPAS,TPMS,EPB,LCA,SPAS,TPMS\n SG_ WHL_DIR_RR : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EPB,SPAS,TPMS,EPB,LCA,SPAS,TPMS\n SG_ WHL_PUL_Chksum : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EPB,SPAS,TPMS,EPB,LCA,LDWS_LKAS,SPAS,TPMS\n\nBO_ 1415 TMU11: 8 IBOX\n SG_ CF_Tmu_VehSld : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Tmu_VehImmo : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Tmu_ReqRepCnd : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS\n SG_ CF_Tmu_AirconCtr : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DATC\n SG_ CF_Tmu_TempMd : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DATC\n SG_ CF_Tmu_TempSet : 6|16@1+ (1.0,0.0) [0.0|20.0] \"\"  DATC\n SG_ CF_Tmu_DefrostCtr : 22|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DATC,FATC\n SG_ CF_Tmu_AliveCnt1 : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS\n\nBO_ 902 WHL_SPD11: 8 ABS\n SG_ WHL_SPD_FL : 0|14@1+ (0.03125,0.0) [0.0|511.96875] \"km/h\"  _4WD,AFLS,AHLS,AVM,CLU,CUBIS,ECS,EMS,EPB,IBOX,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS,_4WD,ACU,AFLS,AHLS,AVM,CLU,ECS,EMS,EPB,IBOX,LCA,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS\n SG_ WHL_SPD_FR : 16|14@1+ (0.03125,0.0) [0.0|511.96875] \"km/h\"  _4WD,ACU,AFLS,AHLS,AVM,CLU,CUBIS,ECS,EMS,EPB,IBOX,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS,_4WD,ACU,AFLS,AHLS,AVM,CLU,ECS,EMS,EPB,IBOX,LCA,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS\n SG_ WHL_SPD_RL : 32|14@1+ (0.03125,0.0) [0.0|511.96875] \"km/h\"  _4WD,AFLS,AHLS,AVM,BCM,CLU,CUBIS,ECS,EMS,EPB,IBOX,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS,_4WD,ACU,AFLS,AHLS,AVM,BCM,CLU,ECS,EMS,EPB,IBOX,LCA,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS\n SG_ WHL_SPD_RR : 48|14@1+ (0.03125,0.0) [0.0|511.96875] \"km/h\"  _4WD,AFLS,AHLS,AVM,CLU,CUBIS,ECS,EMS,EPB,IBOX,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS,_4WD,ACU,AFLS,AHLS,AVM,CLU,ECS,EMS,EPB,IBOX,LCA,LDWS_LKAS,PGS,PSB,SCC,SMK,SPAS,TCU,TPMS\n SG_ WHL_SPD_AliveCounter_LSB : 14|2@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,LPI,TCU,TMU\n SG_ WHL_SPD_AliveCounter_MSB : 30|2@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,LPI,TCU,TMU\n SG_ WHL_SPD_Checksum_LSB : 46|2@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,LPI,TCU,TMU\n SG_ WHL_SPD_Checksum_MSB : 62|2@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,LPI,TCU,TMU\n\nBO_ 1414 EVP11: 3 EVP\n SG_ CF_Evp_Stat : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n\nBO_ 1412 AAF11: 8 AAF\n SG_ CF_Aaf_ActFlapStatus : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AAF_Tester\n SG_ CF_Aaf_ModeStatus : 2|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AAF_Tester\n SG_ CF_Aaf_WrnLamp : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Aaf_ErrStatus : 6|10@1+ (1.0,0.0) [0.0|1023.0] \"\"  AAF_Tester,EMS\n SG_ CF_Aaf_OpenRqSysAct : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  AAF_Tester\n SG_ CF_Aaf_PStatus : 24|8@1+ (1.0,0.0) [0.0|100.0] \"%\"  AAF_Tester\n SG_ CF_Aaf_OpenRqSysSol : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  AAF_Tester\n SG_ CF_Aaf_SolFlapStatus : 40|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AAF_Tester\n SG_ CF_Aaf_MilOnReq : 42|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n\nBO_ 900 EMS17: 8 EMS\n SG_ CF_Ems_PkpCurMSV : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  DI_BOX\n SG_ CF_Ems_HolCurMSV : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  DI_BOX\n SG_ CF_Ems_InjVBnkAct : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  DI_BOX\n SG_ CF_Ems_InjVActSet : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  DI_BOX\n SG_ CF_Ems_DiagFulHDEV : 32|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DI_BOX\n SG_ CF_Ems_SwiOffIC1 : 33|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DI_BOX\n SG_ CF_Ems_SwiOffIC2 : 34|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DI_BOX\n SG_ CF_Ems_DiagReqHDEV : 38|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DI_BOX\n SG_ CR_Ems_DutyCycMSV : 40|8@1+ (0.3921568627,0.0) [0.0|100.0] \"%\"  DI_BOX\n SG_ CR_Ems_BatVolRly : 48|8@1+ (0.1,0.0) [0.0|25.5] \"V\"  DI_BOX\n\nBO_ 387 REA11: 8 REA\n SG_ CF_EndBst_PwmDuH : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_PwmDuL : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_PwmFqOutRng : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_HbriOverCur : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_HbriOverTemp : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_PosSnsKOR : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_PosSnsOSOR : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_EepFlt : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_RomFlt : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_RamFlt : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_CanFlt : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_AgH : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_AgL : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_EndBst_ORVol : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CR_EndBst_ActPos : 16|16@1+ (0.117,0.0) [1.989|118.053] \"\"  EMS\n SG_ CR_EndBst_DemPos : 32|16@1+ (0.117,0.0) [0.0|119.691] \"\"  EMS\n SG_ CR_EndBst_HbriPwr : 48|16@1+ (0.045,0.0) [0.0|99.99] \"%\"  EMS\n\nBO_ 1411 CUBIS11: 8 CUBIS\n SG_ CF_Cubis_HUDisp : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n\nBO_ 899 FATC11: 8 DATC\n SG_ CR_Fatc_TqAcnOut : 0|8@1+ (0.2,0.0) [0.0|50.8] \"Nm\"  EMS,IBOX\n SG_ CF_Fatc_AcnRqSwi : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AAF,EMS,IBOX\n SG_ CF_Fatc_AcnCltEnRq : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_EcvFlt : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_BlwrOn : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_FATC_Iden : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_BlwrMax : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX\n SG_ CF_Fatc_EngStartReq : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_IsgStopReq : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_CtrInf : 17|3@1+ (1.0,0.0) [0.0|7.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_MsgCnt : 20|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS,IBOX\n SG_ CR_Fatc_OutTemp : 24|8@1+ (0.5,-40.0) [-40.0|60.0] \"deg\"  BCM,CLU,EMS,IBOX,SPAS,TCU,TPMS\n SG_ CR_Fatc_OutTempSns : 32|8@1+ (0.5,-40.0) [-40.0|60.0] \"deg\"  AAF,AHLS,CLU,EMS,IBOX,SPAS,TCU\n SG_ CF_Fatc_Compload : 40|3@1+ (1.0,0.0) [0.0|7.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_ActiveEco : 43|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Fatc_AutoActivation : 44|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX\n SG_ CF_Fatc_DefSw : 45|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,IBOX\n SG_ CF_Fatc_PtcRlyStat : 46|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Fatc_ChkSum : 56|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS,IBOX,SPAS\n\nBO_ 129 EMS_DCT12: 8 EMS\n SG_ CR_Ems_SoakTimeExt : 0|6@1+ (5.0,0.0) [0.0|315.0] \"Min\"  TCU\n SG_ BRAKE_ACT : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  TCU\n SG_ CF_Ems_EngOperStat : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  TCU\n SG_ CR_Ems_IndAirTemp : 16|8@1+ (0.75,-48.0) [-48.0|143.25] \"deg\"  TCU\n SG_ CF_Ems_Alive2 : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n SG_ CF_Ems_ChkSum2 : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n\nBO_ 897 MDPS11: 8 MDPS\n SG_ CF_Mdps_WLmp : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,CUBIS,EMS,IBOX,SPAS\n SG_ CF_Mdps_Flex : 2|3@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,LDWS_LKAS\n SG_ CF_Mdps_FlexDisp : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Mdps_Stat : 7|4@1+ (1.0,0.0) [0.0|15.0] \"\"  SPAS\n SG_ CR_Mdps_DrvTq : 11|12@1+ (1.0,-2048.0) [-2048.0|2046.0] \"\"  SPAS\n SG_ CF_Mdps_ALTRequest : 23|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CR_Mdps_StrAng : 24|16@1- (0.1,0.0) [-3276.8|3276.7] \"Deg\"  SPAS\n SG_ CF_Mdps_AliveCnt : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  LDWS_LKAS,SPAS\n SG_ CF_Mdps_Chksum : 48|8@1+ (1.0,0.0) [0.0|255.0] \"\"  LDWS_LKAS,SPAS\n SG_ CF_Mdps_SPAS_FUNC : 57|1@1+ (1.0,0.0) [0.0|1.0] \"flag\"  SPAS\n SG_ CF_Mdps_LKAS_FUNC : 58|1@1+ (1.0,0.0) [0.0|1.0] \"flag\"  LDWS_LKAS\n SG_ CF_Mdps_CurrMode : 59|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LDWS_LKAS\n SG_ CF_Mdps_Type : 61|2@1+ (1.0,0.0) [0.0|2.0] \"\"  LDWS_LKAS,SPAS\n SG_ CF_MDPS_VSM_FUNC : 56|1@0+ (1.0,0.0) [0.0|1.0] \"\" XXX\n\nBO_ 896 DI_BOX13: 8 DI_BOX\n SG_ CF_DiBox_HPreInjVConfStat : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_HPreInjVStat1 : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_HPreInjVStat2 : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_HPreInjVPkp : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_HPreInjVBpt : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_ErrRegFrtMSV : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_ErrRegSedMSV : 48|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_SPIErrSedMSV : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_SPIErrFrtMSV : 57|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_IDErrSedMSV : 58|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_IDErrFrtMSV : 59|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_IniStatMSV : 60|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n\nBO_ 640 EMS13: 8 EMS\n SG_ LV_FUEL_TYPE_ECU : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU,LPI,SMK\n SG_ LV_BFS_CFIRM : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LPI\n SG_ LV_CRASH : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LPI\n SG_ LV_VB_OFF_ACT : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LPI\n SG_ LV_GSL_MAP M : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LPI\n SG_ LV_ENG_TURN : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LPI\n SG_ ERR_FUEL : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  LPI\n SG_ EOS : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  LPI\n SG_ TCO : 24|8@1+ (0.75,-48.0) [-48.0|143.25] \"deg\"  LPI\n SG_ N_32 : 32|8@1+ (32.0,0.0) [0.0|8160.0] \"rpm\"  LPI\n SG_ MAF : 40|8@1+ (5.447,0.0) [0.0|1388.985] \"mg/TDC\"  LPI\n SG_ TIA : 48|8@1+ (0.75,-48.0) [-48.0|143.25] \"deg\"  LPI\n SG_ MAP m1 : 56|8@1+ (0.47058,0.0) [0.0|119.9979] \"kPa\"  LPI\n SG_ AMP m0 : 56|8@1+ (21.22,0.0) [0.0|5411.1] \"hPa\"  LPI\n\nBO_ 128 EMS_DCT11: 8 EMS\n SG_ PV_AV_CAN : 0|8@1+ (0.3906,0.0) [0.0|99.603] \"%\"  TCU\n SG_ TQ_STND : 8|6@1+ (10.0,0.0) [0.0|630.0] \"Nm\"  TCU\n SG_ F_N_ENG : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  TCU\n SG_ F_SUB_TQI : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  TCU\n SG_ N : 16|16@1+ (0.25,0.0) [0.0|16383.75] \"rpm\"  TCU\n SG_ TQI_ACOR : 32|8@1+ (0.390625,0.0) [0.0|99.6094] \"%\"  IBOX,TCU\n SG_ TQFR : 40|8@1+ (0.390625,0.0) [0.0|99.6094] \"%\"  TCU\n SG_ TQI : 48|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  TCU\n SG_ CF_Ems_Alive : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n SG_ CF_Ems_ChkSum : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n\nBO_ 1407 HU_MON_PE_01: 8 CLU\n SG_ HU_Type : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  AVM,PGS\n\nBO_ 127 CGW5: 8 BCM\n SG_ C_StopLampLhOpenSts : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_StopLampRhOpenSts : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_HMSLOpenSts : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_HLampLowLhOpenSts : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_HLampLowRhOpenSts : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_HLampHighLhOpenSts : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_HLampHighRhOpenSts : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_DRLLampLhOpenSts : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_DRLLampRhOpenSts : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_RearFOGLhOpenSts : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_RearFOGRhOpenSts : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_FrontFOGLhOpenSts : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_FrontFOGRhOpenSts : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_RearEXTTailLhOpenSts : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_RearEXTTailRhOpenSts : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_FrontEXTTailLhOpenSts : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_FrontEXTTailRhOpenSts : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_RearTSIGLhOpenSts : 17|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_RearTSIGRhOpenSts : 18|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_FrontTSIGLhOpenSts : 19|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_FrontTSIGRhOpenSts : 20|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_SBendingLhOpenSts : 21|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_SBendingRhOpenSts : 22|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_LicensePlateLhOpenSts : 23|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_LicensePlateRhOpenSts : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n\nBO_ 1151 ESP11: 6 ESC\n SG_ AVH_STAT : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,EPB,TCU\n SG_ LDM_STAT : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EPB,TCU\n SG_ REQ_EPB_ACT : 3|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EPB,TCU\n SG_ REQ_EPB_STAT : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EPB\n SG_ ECD_ACT : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EPB\n SG_ _4WD_LIM_REQ : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS\n SG_ ROL_CNT_ESP : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EPB,TCU\n SG_ _4WD_TQC_LIM : 16|16@1+ (1.0,0.0) [0.0|65535.0] \"Nm\"  _4WD,EMS\n SG_ _4WD_CLU_LIM : 32|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  _4WD,EMS\n SG_ _4WD_OPEN : 40|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,EMS\n SG_ _4WD_LIM_MODE : 42|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD\n\nBO_ 1397 HU_AVM_E_00: 8 CLU\n SG_ HU_AVM_Cal_Cmd : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_Cal_Method : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AVM,PGS\n SG_ HU_AVM_Save_Controlpoint : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AVM,PGS\n SG_ HU_AVM_PT_X : 8|12@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_RearViewPointOpt : 20|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_PT_Y : 24|12@1+ (1.0,0.0) [0.0|4095.0] \"\"  AVM,PGS\n SG_ HU_AVM_FrontViewPointOpt : 36|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_SelectedMenu : 40|5@1+ (1.0,0.0) [0.0|31.0] \"\"  AVM,PGS\n SG_ HU_AVM_CameraOff : 45|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AVM,PGS\n SG_ HU_AVM_Option : 48|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_CrossLineMove_Cmd : 52|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_RearView_Option : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_FrontView_Option : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n\nBO_ 1395 HU_AVM_E_01: 8 CLU\n SG_ HU_PGSSelectedMenu : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_PGSOption : 8|5@1+ (1.0,0.0) [0.0|31.0] \"\"  AVM,PGS\n SG_ HU_AVM_ParkingAssistMenu : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n SG_ HU_AVM_ParkingAssistSB : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  AVM,PGS\n\nBO_ 1393 OPI11: 5 OPI\n SG_ CR_Opi_Spd_Rpm : 0|8@1+ (20.0,0.0) [0.0|3500.0] \"rpm\"  TCU\n SG_ CF_Opi_Over_Temp : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  TCU\n SG_ CF_Opi_Over_Cur : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,TCU\n SG_ CF_Opi_Over_Vol : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  TCU\n SG_ CF_Opi_Hall_Fail : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,TCU\n SG_ CF_Opi_Flt : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,TCU\n SG_ CF_Opi_Motor_Dir : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  TCU\n SG_ CF_Opi_Romver : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  TCU\n SG_ CF_Opi_PWM_Rate : 24|12@1+ (1.0,0.0) [0.0|100.0] \"%\"  TCU\n\nBO_ 625 LPI11: 8 LPI\n SG_ FUP_LPG_MMV : 0|8@1+ (128.0,0.0) [0.0|32640.0] \"hPa\"  EMS\n SG_ LV_FUEL_TYPE_BOX : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ LV_BFS_IN_PROGRESS : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ LV_GAS_OK : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ LV_FUP_ENA_THD : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU,EMS,SMK\n SG_ LPI_OBD : 12|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS\n SG_ ERR_GAS : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ FAC_TI_GAS_COR : 24|16@1+ (3.05E-5,0.0) [0.0|1.9988175] \"\"  EMS\n SG_ FTL_AFU : 40|8@1+ (0.392,0.0) [0.0|99.96] \"%\"  EMS\n SG_ BFS_CYL : 48|8@1+ (1.0,0.0) [0.0|6.0] \"Cyl Nr.\"  EMS\n SG_ LV_PRE_CDN_LEAK : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ LV_CONF_INJECTION_DELAY : 57|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ LV_LPG_SW_DRIVER_REQ : 58|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n\nBO_ 356 VSM11: 4 ESC\n SG_ CR_Esc_StrTqReq : 0|12@1+ (0.01,-20.48) [-20.48|20.47] \"Nm\"  MDPS\n SG_ CF_Esc_Act : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS,MDPS\n SG_ CF_Esc_CtrMode : 13|3@1+ (1.0,0.0) [0.0|7.0] \"\"  MDPS\n SG_ CF_Esc_Def : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  MDPS\n SG_ CF_Esc_AliveCnt : 17|4@1+ (1.0,0.0) [0.0|15.0] \"\"  LDWS_LKAS,MDPS\n SG_ CF_Esc_Chksum : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  LDWS_LKAS,MDPS\n\nBO_ 1379 PGS_HU_PE_01: 8 PGS\n SG_ PGS_State : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ PGS_ParkGuideState : 8|5@1+ (1.0,0.0) [0.0|31.0] \"\"  CLU\n SG_ PGS_Option : 16|5@1+ (1.0,0.0) [0.0|31.0] \"\"  CLU\n SG_ PGS_Version : 32|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  CLU\n\nBO_ 354 TCU_DCT13: 3 TCU\n SG_ Clutch_Driving_Tq : 0|10@1+ (1.0,-512.0) [0.0|0.0] \"Nm\"  ESC\n SG_ Cluster_Engine_RPM : 10|13@1+ (0.9766,0.0) [0.0|0.0] \"\"  CLU\n SG_ Cluster_Engine_RPM_Flag : 23|1@1+ (1.0,0.0) [0.0|0.0] \"\"  CLU\n\nBO_ 1378 HUD11: 4 HUD\n SG_ CF_Hud_HeightStaus : 0|5@1+ (1.0,0.0) [0.0|31.0] \"\"  CLU\n SG_ CF_Hud_PBackStatus : 6|2@1+ (1.0,0.0) [0.0|0.0] \"\"  BCM,CLU\n SG_ CF_Hud_Brightness : 8|5@1+ (1.0,0.0) [0.0|31.0] \"\"  CLU\n\nBO_ 608 EMS16: 8 EMS\n SG_ TQI_MIN : 0|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  ESC,IBOX,TCU\n SG_ TQI : 8|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  ESC,IBOX,TCU\n SG_ TQI_TARGET : 16|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  EPB,ESC,IBOX,TCU\n SG_ GLOW_STAT : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU,IBOX,SMK\n SG_ CRUISE_LAMP_M : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX,TCU\n SG_ CRUISE_LAMP_S : 26|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX,TCU\n SG_ PRE_FUEL_CUT_IN : 27|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,TCU\n SG_ ENG_STAT : 28|3@1+ (1.0,0.0) [0.0|7.0] \"\"  ABS,AHLS,AVM,BCM,CLU,EPB,ESC,EVP,FPCM,IBOX,LCA,LDWS_LKAS,MDPS,SCC,SMK,TCU\n SG_ SOAK_TIME_ERROR : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DATC,EPB,IBOX,TCU\n SG_ SOAK_TIME : 32|8@1+ (1.0,0.0) [0.0|255.0] \"Min\"  _4WD,DATC,EPB,IBOX,TCU\n SG_ TQI_MAX : 40|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  ESC,IBOX,TCU\n SG_ SPK_TIME_CUR : 48|8@1+ (0.375,-35.625) [-35.625|60.0] \"\"  IBOX,TCU\n SG_ Checksum : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  ECS,IBOX,LDWS_LKAS,MDPS,SCC\n SG_ AliveCounter : 60|2@1+ (1.0,0.0) [0.0|3.0] \"\"  IBOX,LDWS_LKAS,MDPS,SCC\n SG_ CF_Ems_AclAct : 62|2@1+ (1.0,0.0) [0.0|3.0] \"\"  IBOX,SCC\n\nBO_ 1371 AVM_HU_PE_00: 8 AVM\n SG_ AVM_View : 0|5@1+ (1.0,0.0) [0.0|31.0] \"\"  CLU\n SG_ AVM_ParkingAssist_BtnSts : 5|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ AVM_Display_Message : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ AVM_Popup_Msg : 16|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_Ready : 20|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_ParkingAssist_Step : 24|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_FrontBtn_Type : 28|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_Option : 32|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_HU_FrontViewPointOpt : 36|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_HU_RearView_Option : 40|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_HU_FrontView_Option : 44|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ AVM_Version : 48|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  CLU\n\nBO_ 1370 HU_AVM_PE_00: 8 CLU\n SG_ HU_AVM_Status : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AVM,PGS\n\nBO_ 1369 CGW4: 8 BCM\n SG_ CF_Gway_MemoryP1Cmd : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_MemoryP2Cmd : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_PBackP1Cmd : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_PBackP2Cmd : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_StrgWhlHeatedState : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_PBackStopCmd : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,HUD\n SG_ CF_Gway_StaticBendLhAct : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_StaticBendRhAct : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_DrvWdwStat : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_RLWdwState : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_RRWdwState : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_AstWdwStat : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_MemoryEnable : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_PBACKStopCmd : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_PBACKStop : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,HUD\n SG_ CF_Gway_IMSBuzzer : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_DrvSeatBeltInd : 36|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_AstSeatBeltInd : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_RCSeatBeltInd : 40|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_RLSeatBeltInd : 42|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_RRSeatBeltInd : 44|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_RrWiperHighSw : 46|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_RrWiperLowSw : 47|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n\nBO_ 1367 EngFrzFrm12: 8 EMS\n SG_ PID_06h : 0|8@1+ (0.78125,-100.0) [-100.0|99.22] \"%\"  AAF,IBOX,TCU\n SG_ PID_07h : 8|8@1+ (0.78125,-100.0) [-100.0|99.22] \"%\"  AAF,IBOX,TCU\n SG_ PID_08h : 16|8@1+ (0.78125,-100.0) [-100.0|99.22] \"%\"  AAF,IBOX,TCU\n SG_ PID_09h : 24|8@1+ (0.78125,-100.0) [-100.0|99.22] \"%\"  AAF,IBOX,TCU\n SG_ PID_0Bh : 32|8@1+ (1.0,0.0) [0.0|255.0] \"kPa\"  AAF,IBOX,TCU\n SG_ PID_23h : 40|16@1+ (10.0,0.0) [0.0|655350.0] \"kPa\"  AAF,IBOX,TCU\n\nBO_ 1366 EngFrzFrm11: 8 EMS\n SG_ PID_04h : 0|8@1+ (0.3921568627,0.0) [0.0|100.0] \"%\"  AAF,TCU\n SG_ PID_05h : 8|8@1+ (1.0,-40.0) [-40.0|215.0] \"deg\"  AAF,TCU\n SG_ PID_0Ch : 16|16@1+ (0.25,0.0) [0.0|16383.75] \"rpm\"  AAF,TCU\n SG_ PID_0Dh : 32|8@1+ (1.0,0.0) [0.0|255.0] \"km/h\"  AAF,TCU\n SG_ PID_11h : 40|8@1+ (0.3921568627,0.0) [0.0|100.0] \"%\"  AAF,TCU\n SG_ PID_03h : 48|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  AAF,TCU\n\nBO_ 1365 FPCM11: 8 FPCM\n SG_ CR_Fpcm_LPActPre : 0|8@1+ (3.137254902,0.0) [0.0|800.0] \"kPa\"  EMS\n SG_ CF_Fpcm_LPPumpOverCur : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_PreSnrHi : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_PreSnrDisc : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_PreSnrShort : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_LPPumpDiscShort : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_LP_System_Error : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_PreSnrSigErr : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Fpcm_LPCtrCirFlt : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n\nBO_ 871 LVR12: 8 LVR\n SG_ CF_Lvr_CruiseSet : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\" CLU,TCU\n SG_ CF_Lvr_Gear : 32|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,TCU\n\nBO_ 872 LVR11: 8 LVR\n SG_ CF_Lvr_GearInf : 0|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,TCU\n SG_ CF_Lvr_PRelStat : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU,SMK,TCU\n SG_ CF_Lvr_BkeAct : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  TCU\n SG_ CF_Lvr_NFnStat : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Lvr_PosInf : 8|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n SG_ CF_Lvr_PosCpl : 12|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n SG_ CF_Lvr_UlkButStat : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  TCU\n SG_ CF_Lvr_PNStat : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Lvr_ShtLkStat : 24|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n SG_ CF_Lvr_ShfErrInf : 28|20@1+ (1.0,0.0) [0.0|8191.0] \"\"  CLU,TCU\n SG_ CF_Lvr_AC : 48|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n SG_ CF_Lvr_CS : 52|4@1+ (1.0,0.0) [0.0|15.0] \"\"  TCU\n\nBO_ 1363 CGW2: 8 BCM\n SG_ CF_Gway_GwayDiagState : 0|1@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_DDMDiagState : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_SCMDiagState : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_PSMDiagState : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_SJBDiagState : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_IPMDiagState : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_LDMFail : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,LDWS_LKAS,LDWS_LKAS\n SG_ CF_Gway_CLUSwGuiCtrl : 10|3@1+ (1.0,0.0) [0.0|63.0] \"\"  CLU,Dummy\n SG_ CF_Gway_CLUSwGroup : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_CLUSwMode : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_CLUSwEnter : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_AutoLightValue : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LCA,LCA\n SG_ CF_Gway_BrakeFluidSw : 17|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_DrvSeatBeltInd : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_AvTail : 20|1@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,SNV,SNV\n SG_ CF_Gway_RearFogAct : 21|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_ExtTailAct : 22|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AVM,CLU,LCA,PGS,SPAS,AVM,LCA,PGS,SPAS\n SG_ CF_Gway_RRDrSw : 23|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_RLDrSw : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_IntTailAct : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_CountryCfg : 26|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,PGS,Dummy\n SG_ CF_Gway_WiperParkPosition : 32|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AFLS,EMS,LDWS_LKAS,AFLS,EMS,LDWS_LKAS\n SG_ CF_Gway_HLLowLHFail : 33|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS,SNV,LDWS_LKAS,SNV\n SG_ CF_Gway_HLLowRHFail : 34|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS,SNV,LDWS_LKAS,SNV\n SG_ CF_Gway_ESCLFailWarn : 35|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_ESCLNotLockedWarn : 36|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_ESCLNotUnlockWarn : 37|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_IDoutWarn : 38|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_ImmoLp : 40|1@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_BCMRKEID : 41|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,Dummy\n SG_ CF_Gway_VehicleNotPWarn : 44|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_DeactivationWarn : 45|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_KeyBATDischargeWarn : 46|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_SSBWarn : 47|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_SMKFobID : 48|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,Dummy\n SG_ CF_Gway_SMKRKECmd : 51|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,Dummy\n SG_ CF_Gway_AutoLightOption : 54|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_SJBDeliveryMode : 55|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_KeyoutLp : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,Dummy\n SG_ CF_Gway_SMKDispWarn : 57|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,Dummy\n SG_ CF_Gway_WngBuz : 61|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,Dummy\n\nBO_ 339 TCS11: 8 ESC\n SG_ TCS_REQ : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,TCU\n SG_ MSR_C_REQ : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,EPB,SCC,TCU\n SG_ TCS_PAS : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,EMS,SCC,SPAS,TCU\n SG_ TCS_GSC : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,TCU\n SG_ CF_Esc_LimoInfo : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,SCC\n SG_ ABS_DIAG : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,EMS,EPB\n SG_ ABS_DEF : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,ECS,EMS,EPB,SCC,SPAS,TCU\n SG_ TCS_DEF : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,SCC,SPAS,TCU\n SG_ TCS_CTL : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,SCC,SPAS,TCU\n SG_ ABS_ACT : 10|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,ECS,EMS,EPB,LDWS_LKAS,SCC,SPAS,TCU\n SG_ EBD_DEF : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,SPAS,TCU\n SG_ ESP_PAS : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,CLU,EMS,EPB,LDWS_LKAS,SCC,TCU\n SG_ ESP_DEF : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,ECS,EMS,EPB,LDWS_LKAS,SCC,TCU\n SG_ ESP_CTL : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,ECS,EMS,EPB,LDWS_LKAS,SCC,SPAS,TCU\n SG_ TCS_MFRN : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,EPB,TCU\n SG_ DBC_CTL : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB\n SG_ DBC_PAS : 17|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB\n SG_ DBC_DEF : 18|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB\n SG_ HAC_CTL : 19|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,EMS,EPB,TCU\n SG_ HAC_PAS : 20|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,EMS,EPB,TCU\n SG_ HAC_DEF : 21|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,EMS,EPB,TCU\n SG_ ESS_STAT : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,BCM,CLU,EMS,EPB\n SG_ TQI_TCS : 24|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  EMS,EPB,TCU\n SG_ TQI_MSR : 32|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  EMS,EPB,TCU\n SG_ TQI_SLW_TCS : 40|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  EMS,EPB,TCU\n SG_ CF_Esc_BrkCtl : 48|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ BLA_CTL : 49|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CGW,CLU\n SG_ AliveCounter_TCS1 : 52|4@1+ (1.0,0.0) [0.0|14.0] \"\"  EMS,EPB,LDWS_LKAS\n SG_ CheckSum_TCS1 : 56|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS,EPB,LDWS_LKAS\n\nBO_ 1362 SNV11: 4 SNV\n SG_ CF_SNV_DisplayControl : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,HUD\n SG_ CF_Snv_BeepWarning : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,HUD\n SG_ CF_Snv_WarningMessage : 4|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,HUD\n SG_ CF_Snv_DetectionEnable : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CLU,HUD\n SG_ CF_Snv_PedestrianDetect : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU,HUD\n SG_ CF_Snv_IRLampControl : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU,HUD\n\nBO_ 593 MDPS12: 8 MDPS\n SG_ CR_Mdps_StrColTq : 0|11@1+ (1.0,-1024.0) [-1024.0|1024.0] \"\"  LDWS_LKAS\n SG_ CF_Mdps_Def : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC\n SG_ CF_Mdps_ToiUnavail : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS\n SG_ CF_Mdps_ToiActive : 13|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS\n SG_ CF_Mdps_ToiFlt : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS\n SG_ CF_Mdps_FailStat : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS\n SG_ CF_Mdps_MsgCount2 : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ESC,LDWS_LKAS\n SG_ CF_Mdps_Chksum2 : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  ESC,LDWS_LKAS\n SG_ CF_Mdps_SErr : 37|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC\n SG_ CR_Mdps_StrTq : 40|12@1+ (0.01,-20.48) [-20.48|20.47] \"Nm\"  ESC\n SG_ CR_Mdps_OutTq : 52|12@1+ (0.1,-204.8) [-204.8|204.7] \"\"  ESC,LDWS_LKAS\n\nBO_ 1360 IAP11: 3 IAP\n SG_ CF_Iap_EcoPmodSwi : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Iap_EcoPmodAct : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Iap_ReqWarn : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1356 TCU_DCT14: 8 TCU\n SG_ Vehicle_Stop_Time : 0|5@1+ (1.0,0.0) [0.0|0.0] \"\"  CLU\n SG_ HILL_HOLD_WARNING : 5|1@1+ (1.0,0.0) [0.0|0.0] \"\"  CLU\n\nBO_ 1353 BAT11: 8 EMS\n SG_ BAT_SNSR_I : 0|16@1+ (0.01,-327.0) [-327.0|328.0] \"A\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SOC : 16|8@1+ (1.0,0.0) [0.0|100.0] \"%\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SNSR_V : 24|14@1+ (0.0010,6.0) [6.0|18.0] \"V\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SNSR_Temp : 38|9@1- (0.5,-40.0) [-40.0|125.0] \"deg\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SNSR_State : 47|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SOH : 48|7@1+ (1.0,0.0) [0.0|100.0] \"%\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SNSR_Invalid : 55|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SOF : 56|7@1+ (0.1,0.0) [0.0|12.0] \"V\"  CGW,CUBIS,IBOX,TMU\n SG_ BAT_SNSR_Error : 63|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CGW,CUBIS,IBOX,TMU\n\nBO_ 1351 EMS15: 8 EMS\n SG_ ECGPOvrd : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX,SCC\n SG_ QECACC : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX\n SG_ ECFail : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX\n SG_ SwitchOffCondExt : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX\n SG_ BLECFail : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX\n SG_ CF_Ems_IsaAct : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ FA_PV_CAN : 8|8@1+ (0.3906,0.0) [0.0|99.2] \"%\"  IBOX,LDWS_LKAS,TCU\n SG_ IntAirTemp : 16|8@1+ (0.75,-48.0) [-48.0|143.25] \"deg\"  _4WD,ECS,EPB,IBOX,TCU\n SG_ STATE_DC_OBD : 24|7@1+ (1.0,0.0) [0.0|127.0] \"\"  IBOX,TCU\n SG_ INH_DC_OBD : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,TCU\n SG_ CTR_IG_CYC_OBD : 32|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  ACU,IBOX,TCU\n SG_ CTR_CDN_OBD : 48|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  IBOX,TCU\n\nBO_ 1350 DI_BOX12: 8 DI_BOX\n SG_ CF_DiBox_FrtInjVDiagReg0 : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_FrtInjVDiagReg1 : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_FrtInjVDiagReg2 : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_SedInjVDiagReg0 : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_SedInjVDiagReg1 : 32|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CF_DiBox_SedInjVDiagReg2 : 40|8@1+ (1.0,0.0) [0.0|255.0] \"\"  EMS\n SG_ CR_DiBox_BatVol : 48|8@1+ (0.1,0.0) [0.0|25.5] \"V\"  EMS\n SG_ CF_DiBox_SedInjVChg : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_FrtInjVChg : 57|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_SedInjVErrSPI : 58|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_DiBox_FrtInjVErrSPI : 59|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n\nBO_ 1349 EMS14: 8 EMS\n SG_ IMMO_LAMP_STAT : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ L_MIL : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,CUBIS,IBOX\n SG_ IM_STAT : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ AMP_CAN : 3|5@1+ (10.731613,458.98) [458.98|791.660003] \"mmHg\"  CLU,IBOX,TCU,TPMS\n SG_ BAT_Alt_FR_Duty : 8|8@1+ (0.4,0.0) [0.0|100.0] \"%\"  CGW,CUBIS,IBOX,TMU\n SG_ VB : 24|8@1+ (0.1015625,0.0) [0.0|25.8984375] \"V\"  CLU,CUBIS,DATC,EPB,FPCM,IBOX\n SG_ EMS_VS : 32|12@1+ (0.0625,0.0) [0.0|255.875] \"km/h\"  CLU\n SG_ TEMP_FUEL : 56|8@1+ (0.75,-48.0) [-48.0|143.25] \"deg\"  FPCM\n\nBO_ 68 DATC11: 8 DATC\n SG_ CF_Datc_Type : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ CF_Datc_VerMaj : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ CF_Datc_VerMin : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ CR_Datc_OutTempC : 24|8@1+ (0.5,-41.0) [-41.0|86.5] \"deg\"  CLU,FPCM\n SG_ CR_Datc_OutTempF : 32|8@1+ (1.0,-42.0) [-42.0|213.0] \"deg\"  CLU\n SG_ CF_Datc_IncarTemp : 40|8@1+ (0.5,-40.0) [-40.0|60.0] \"deg\"  BCM,CLU\n\nBO_ 67 DATC13: 8 DATC\n SG_ CF_Datc_TempDispUnit : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,IBOX\n SG_ CF_Datc_ModDisp : 2|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ CF_Datc_IonClean : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_ChgReqDisp : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_IntakeDisp : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_AutoDisp : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_FrDefLed : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,IBOX\n SG_ CF_Datc_AutoDefogBlink : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_ClmScanDisp : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_AqsDisp : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_AcDisp : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_OpSts : 25|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Mtc_MaxAcDisp : 28|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_DualDisp : 30|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_PwrInf : 32|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ CF_Datc_RearManual : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_RearAutoDisp : 40|2@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Datc_RearOffDisp : 42|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_RearClimateScnDisp : 44|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_RearChgReqDisp : 46|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_RearModDisp : 48|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ CF_Datc_RearBlwDisp : 52|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ CF_Datc_PSModDisp : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ CF_Datc_FrontBlwDisp : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,IBOX\n\nBO_ 66 DATC12: 8 DATC\n SG_ CR_Datc_DrTempDispC : 0|8@1+ (0.5,14.0) [15.0|32.0] \"deg\"  CLU,IBOX\n SG_ CR_Datc_DrTempDispF : 8|8@1+ (1.0,56.0) [58.0|90.0] \"deg\"  CLU,IBOX\n SG_ CR_Datc_PsTempDispC : 16|8@1+ (0.5,14.0) [15.0|32.0] \"deg\"  CLU,IBOX\n SG_ CR_Datc_PsTempDispF : 24|8@1+ (1.0,56.0) [58.0|90.0] \"deg\"  CLU,IBOX\n SG_ CR_Datc_RearDrTempDispC : 40|8@1+ (0.5,14.0) [15.0|32.0] \"deg\"  CLU\n SG_ CR_Datc_RearDrTempDispF : 48|8@1+ (1.0,58.0) [58.0|90.0] \"deg\"  CLU\n SG_ CF_Datc_CO2_Warning : 56|8@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1345 CGW1: 8 BCM\n SG_ CF_Gway_IGNSw : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,ECS,EMS,EPB,ESC,IBOX,LVR,MDPS,SAS,SCC,ECS,EMS,EPB,ESC,IBOX,LVR,MDPS,SAS,SCC\n SG_ CF_Gway_RKECmd : 3|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,ECS,EMS,IBOX,ECS,EMS,IBOX\n SG_ CF_Gway_DrvKeyLockSw : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ECS,EMS,IBOX,ECS,EMS,IBOX\n SG_ CF_Gway_DrvKeyUnlockSw : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ECS,EMS,IBOX,ECS,EMS,IBOX\n SG_ CF_Gway_DrvDrSw : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,ECS,EMS,EPB,ESC,IBOX,SCC,TCU,ECS,EMS,EPB,ESC,IBOX,SCC,TCU\n SG_ CF_Gway_DrvSeatBeltSw : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,EPB,ESC,IBOX,PSB,TCU,EMS,EPB,ESC,IBOX,PSB,TCU\n SG_ CF_Gway_TrunkTgSw : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,ECS,EMS,EPB,ESC,IBOX,ECS,EMS,EPB,ESC,IBOX\n SG_ CF_Gway_AstSeatBeltSw : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  IBOX,PSB,IBOX,PSB\n SG_ CF_Gway_SMKOption : 16|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX,EMS,IBOX,SMK\n SG_ CF_Gway_HoodSw : 17|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,EMS,EPB,ESC,IBOX,EMS,EPB,ESC,IBOX\n SG_ CF_Gway_TurnSigLh : 19|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,EMS,IBOX,LCA,LDWS_LKAS,SCC,EMS,IBOX,LCA,LDWS_LKAS,SCC\n SG_ CF_Gway_WiperIntT : 21|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,EMS,IBOX,LDWS_LKAS,EMS,ESC,IBOX,LDWS_LKAS\n SG_ CF_Gway_WiperIntSw : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX,LDWS_LKAS,EMS,ESC,IBOX,LDWS_LKAS\n SG_ CF_Gway_WiperLowSw : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX,LDWS_LKAS,EMS,ESC,IBOX,LDWS_LKAS\n SG_ CF_Gway_WiperHighSw : 26|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX,LDWS_LKAS,EMS,ESC,IBOX,LDWS_LKAS\n SG_ CF_Gway_WiperAutoSw : 27|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX,LDWS_LKAS,EMS,ESC,IBOX,LDWS_LKAS\n SG_ CF_Gway_RainSnsState : 28|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AFLS,EMS,IBOX,LDWS_LKAS,AFLS,EMS,ESC,IBOX,LDWS_LKAS\n SG_ CF_Gway_HeadLampLow : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AFLS,CLU,EMS,IBOX,LDWS_LKAS,SNV,AFLS,EMS,IBOX,LDWS_LKAS,SNV\n SG_ CF_Gway_HeadLampHigh : 32|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AFLS,CLU,EMS,IBOX,LDWS_LKAS,AFLS,EMS,IBOX,LDWS_LKAS\n SG_ CF_Gway_HazardSw : 33|2@1+ (1.0,0.0) [0.0|3.0] \"\"  ABS,EMS,ESC,IBOX,LCA,LDWS_LKAS,ABS,EMS,ESC,IBOX,LCA,LDWS_LKAS\n SG_ CF_Gway_AstDrSw : 35|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX,IBOX\n SG_ CF_Gway_DefoggerRly : 36|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX,EMS,IBOX\n SG_ CF_Gway_ALightStat : 37|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AFLS,IBOX,LDWS_LKAS,AFLS,IBOX,LDWS_LKAS\n SG_ CF_Gway_LightSwState : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AFLS,IBOX,LDWS_LKAS,AFLS,IBOX,LDWS_LKAS\n SG_ CF_Gway_Frt_Fog_Act : 40|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AFLS,CLU,IBOX,LDWS_LKAS,AFLS,IBOX,LDWS_LKAS\n SG_ CF_Gway_TSigRHSw : 41|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,LDWS_LKAS,IBOX,LDWS_LKAS\n SG_ CF_Gway_TSigLHSw : 42|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,LDWS_LKAS,IBOX,LDWS_LKAS\n SG_ CF_Gway_DriveTypeOption : 43|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX,LDWS_LKAS,IBOX,LDWS_LKAS\n SG_ CF_Gway_StarterRlyState : 44|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX,EMS,IBOX,SMK\n SG_ CF_Gway_PassiveAccessLock : 45|2@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,ECS,EMS,IBOX,ECS,EMS,IBOX,SMK\n SG_ CF_Gway_WiperMistSw : 47|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,IBOX,LDWS_LKAS\n SG_ CF_Gway_PassiveAccessUnlock : 48|2@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,ECS,EMS,IBOX,ECS,EMS,IBOX,SMK\n SG_ CF_Gway_RrSunRoofOpenState : 50|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,DATC,IBOX\n SG_ CF_Gway_PassingSW : 51|1@1+ (1.0,0.0) [0.0|1.0] \"\"  AFLS,IBOX,LDWS_LKAS,AFLS,IBOX,LDWS_LKAS\n SG_ CF_Gway_HBAControlMode : 52|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,LDWS_LKAS,IBOX,LDWS_LKAS\n SG_ CF_Gway_HLpHighSw : 53|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,LDWS_LKAS,IBOX,LDWS_LKAS\n SG_ CF_Gway_InhibitRMT : 54|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,EPB,ESC,IBOX,LCA,LDWS_LKAS,MDPS,PGS,SCC,SPAS,TPMS,EPB,ESC,IBOX,LCA,LDWS_LKAS,PGS,SCC,SPAS,TPMS\n SG_ CF_Gway_RainSnsOption : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ C_SunRoofOpenState : 57|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,DATC,IBOX,DATC,IBOX\n SG_ CF_Gway_Ign1 : 58|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_Ign2 : 59|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Gway_ParkBrakeSw : 60|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,ESC,IBOX,SCC,ESC,IBOX,SCC\n SG_ CF_Gway_TurnSigRh : 62|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,EMS,IBOX,LCA,LDWS_LKAS,SCC,EMS,IBOX,LCA,LDWS_LKAS,SCC\n\nBO_ 64 DATC14: 8 DATC\n SG_ CF_Datc_AqsLevelOut : 0|4@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Datc_DiagMode : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CR_Datc_SelfDiagCode : 8|8@1+ (1.0,-1.0) [0.0|254.0] \"\"  CLU\n SG_ DATC_SyncDisp : 16|4@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ DATC_OffDisp : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ DATC_SmartVentDisp : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ DATC_SmartVentOnOffStatus : 24|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ DATC_AutoDefogSysOff_Disp : 26|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ DATC_ADSDisp : 28|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 832 LKAS11: 8 LDWS_LKAS\n SG_ CF_Lkas_LdwsActivemode : 0|2@1+ (1,0) [0|3] \"\" CLU,IBOX,PSB\n SG_ CF_Lkas_LdwsSysState : 2|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,IBOX,PSB\n SG_ CF_Lkas_SysWarning : 6|4@1+ (1.0,0.0) [0.0|15.0] \"\"  BCM,CLU\n SG_ CF_Lkas_LdwsLHWarning : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU,PSB\n SG_ CF_Lkas_LdwsRHWarning : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU,PSB\n SG_ CF_Lkas_HbaLamp : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Lkas_FcwBasReq : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,ESC\n SG_ CR_Lkas_StrToqReq : 16|11@1+ (1.0,-1024.0) [-1024.0|1024.0] \"\"  MDPS\n SG_ CF_Lkas_ActToi : 27|1@1+ (1.0,0.0) [0.0|1.0] \"\"  MDPS\n SG_ CF_Lkas_ToiFlt : 28|1@1+ (1.0,0.0) [0.0|1.0] \"\"  MDPS\n SG_ CF_Lkas_HbaSysState : 29|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM,CLU\n SG_ CF_Lkas_FcwOpt : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Lkas_HbaOpt : 34|2@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,CGW\n SG_ CF_Lkas_MsgCount : 36|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,MDPS\n SG_ CF_Lkas_FcwSysState : 40|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Lkas_FcwCollisionWarning : 43|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Lkas_FusionState : 45|2@1+ (1.0,0.0) [0.0|3.0] \"\"  SCC\n SG_ CF_Lkas_Unknown1 : 47|1@1+ (1.0,0.0) [0.0|1.0] \"\" XXX\n SG_ CF_Lkas_Chksum : 48|8@1+ (1.0,0.0) [0.0|255.0] \"\"  MDPS\n SG_ CF_Lkas_FcwOpt_USM : 56|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Lkas_LdwsOpt_USM : 59|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,MDPS\n SG_ CF_Lkas_Unknown2 : 62|2@1+ (1.0,0.0) [0.0|1.0] \"\" XXX\n\nBO_ 1342 LKAS12: 6 LDWS_LKAS\n SG_ CF_Lkas_TsrSlifOpt : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_LkasTsrStatus : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Lkas_TsrSpeed_Display_Clu : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU\n SG_ CF_LkasTsrSpeed_Display_Navi : 24|8@1+ (1.0,0.0) [0.0|255.0] \"\"  BCM,CLU\n SG_ CF_Lkas_TsrAddinfo_Display : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_LkasDawStatus : 40|3@1+ (1,0) [0|7] \"\" CLU\n SG_ CF_Lkas_Daw_USM : 37|3@1+ (1,0) [0|7] \"\" CLU\n\nBO_ 1338 TMU_GW_E_01: 8 CLU\n SG_ CF_Gway_TeleReqDrLock : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Gway_TeleReqDrUnlock : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Gway_TeleReqHazard : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Gway_TeleReqHorn : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Gway_TeleReqEngineOperate : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n\nBO_ 1078 PAS11: 4 BCM\n SG_ CF_Gway_PASDisplayFLH : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,AVM\n SG_ CF_Gway_PASDisplayFRH : 3|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,AVM\n SG_ CF_Gway_PASRsound : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_PASDisplayFCTR : 8|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,AVM\n SG_ CF_Gway_PASDisplayRCTR : 11|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,PGS,AVM\n SG_ CF_Gway_PASFsound : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_PASDisplayRLH : 16|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,PGS,AVM\n SG_ CF_Gway_PASDisplayRRH : 19|3@1+ (1.0,0.0) [0.0|7.0] \"\"  AVM,CLU,PGS,AVM\n SG_ CF_Gway_PASCheckSound : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_PASSystemOn : 24|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,Dummy\n SG_ CF_Gway_PASOption : 26|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_PASDistance : 28|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n\nBO_ 48 EMS18: 6 EMS\n SG_ CF_Ems_DC1NumPerMSV : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  DI_BOX\n SG_ CF_Ems_DC2NumPerMSV : 8|16@1+ (1.0,0.0) [0.0|65535.0] \"\"  DI_BOX\n SG_ CR_Ems_DutyCyc1MSV : 24|8@1+ (0.1953,0.0) [0.0|49.8] \"%\"  DI_BOX\n SG_ CR_Ems_DutyCyc2MSV : 32|8@1+ (0.13725,0.0) [0.0|35.0] \"%\"  DI_BOX\n SG_ CR_Ems_DutyCyc3MSV : 40|8@1+ (0.392,0.0) [0.0|100.0] \"%\"  DI_BOX\n\nBO_ 1322 CLU15: 8 CLU\n SG_ CF_Clu_VehicleSpeed : 0|8@1+ (1.0,0.0) [0.0|255.0] \"\"  BCM\n SG_ CF_Clu_Gear : 9|4@1+ (1,0) [0|15] \"\" BCM\n SG_ CF_Clu_HudInfoSet : 13|7@1+ (1.0,0.0) [0.0|127.0] \"\"  HUD\n SG_ CF_Clu_HudFontColorSet : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  HUD\n SG_ CF_Clu_HudBrightUpSW : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  HUD\n SG_ CF_Clu_HudBrightDnSW : 24|2@1+ (1.0,0.0) [0.0|3.0] \"\"  HUD\n SG_ CF_Clu_HudHeightUpSW : 26|2@1+ (1.0,0.0) [0.0|3.0] \"\"  HUD\n SG_ CF_Clu_HudHeightDnSW : 28|2@1+ (1.0,0.0) [0.0|3.0] \"\"  HUD\n SG_ CF_Clu_HudSet : 30|1@1+ (1.0,0.0) [0.0|1.0] \"\"  HUD\n SG_ CF_Clu_HudFontSizeSet : 31|2@1+ (1.0,0.0) [0.0|3.0] \"\"  HUD\n SG_ CF_Clu_LanguageInfo : 33|5@1+ (1.0,0.0) [0.0|31.0] \"\"  BCM,PGS\n SG_ CF_Clu_ClusterSound : 38|1@1- (1.0,0.0) [0.0|0.0] \"\"  BCM,CGW,FATC\n SG_ CF_Clu_VehicleSpeed2 : 48|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 1066 _4WD13: 6 _4WD\n SG_ _4WD_CURRENT : 0|8@1+ (0.390625,0.0) [-50.0|50.0] \"A\"  TCU\n SG_ _4WD_POSITION : 8|16@1+ (0.015625,0.0) [-180.0|180.0] \"Deg\"  TCU\n SG_ _4WD_CLU_THERM_STR : 24|8@1+ (1.0,0.0) [0.0|100.0] \"%\"  TCU\n SG_ _4WD_STATUS : 32|8@1+ (1.0,0.0) [0.0|15.0] \"\"  ESC,TCU\n\nBO_ 1065 _4WD12: 8 _4WD\n SG_ Ster_Pos : 0|16@1+ (1.0,-600.0) [-600.0|600.0] \"Deg\"  ESC\n SG_ FRSS : 16|8@1+ (1.0,0.0) [0.0|254.0] \"km/h\"  ESC\n SG_ FLSS : 24|8@1+ (1.0,0.0) [0.0|254.0] \"km/h\"  ESC\n SG_ RRSS : 32|8@1+ (1.0,0.0) [0.0|254.0] \"km/h\"  ESC\n SG_ RLSS : 40|8@1+ (1.0,0.0) [0.0|254.0] \"km/h\"  ESC\n SG_ CLU_PRES : 48|16@1+ (0.0625,-50.0) [-50.0|50.0] \"Bar\"  ESC\n\nBO_ 809 EMS12: 8 EMS\n SG_ CONF_TCU m1 : 0|6@1+ (1.0,0.0) [0.0|63.0] \"\"  _4WD,ACU,BCM,CLU,DATC,EPB,ESC,IBOX,LCA,SMK\n SG_ CAN_VERS m0 : 0|6@1+ (1.0,0.0) [0.0|7.7] \"\"  _4WD,ABS,ESC,IBOX\n SG_ TQ_STND m3 : 0|6@1+ (10.0,0.0) [0.0|630.0] \"Nm\"  _4WD,DATC,ECS,EPB,ESC,FATC,IBOX\n SG_ OBD_FRF_ACK m2 : 0|6@1+ (1.0,0.0) [0.0|63.0] \"\"  _4WD,ESC,IBOX\n SG_ MUL_CODE M : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,ABS,ACU,BCM,CLU,DATC,ECS,EPB,ESC,IBOX,LCA,SMK,TCU\n SG_ TEMP_ENG : 8|8@1+ (0.75,-48.0) [-48.0|143.25] \"deg\"  _4WD,BCM,CLU,DATC,EPB,ESC,IBOX,SMK,TCU\n SG_ MAF_FAC_ALTI_MMV : 16|8@1+ (0.00781,0.0) [0.0|1.99155] \"\"  IBOX,TCU\n SG_ VB_OFF_ACT : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,TCU\n SG_ ACK_ES : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,IBOX\n SG_ CONF_MIL_FMY : 26|3@1+ (1.0,0.0) [0.0|7.0] \"\"  ESC,IBOX,TCU\n SG_ OD_OFF_REQ : 29|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,TCU\n SG_ ACC_ACT : 30|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ABS,CLU,ESC,IAP,IBOX,SCC,TCU\n SG_ CLU_ACK : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EPB,ESC,IBOX\n SG_ BRAKE_ACT : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,ABS,ACU,AFLS,CLU,DATC,ECS,EPB,ESC,IBOX,LDWS_LKAS,TCU\n SG_ ENG_CHR : 34|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,ABS,ACU,CLU,DATC,EPB,ESC,FATC,IBOX,SCC,SMK,TCU\n SG_ GP_CTL : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  IBOX\n SG_ TPS : 40|8@1+ (0.4694836,-15.0234742) [-15.0234742|104.6948357] \"%\"  _4WD,ABS,ACU,CLU,DATC,ECS,EPB,ESC,IBOX,TCU\n SG_ PV_AV_CAN : 48|8@1+ (0.3906,0.0) [0.0|99.603] \"%\"  _4WD,AAF,ABS,ACU,AFLS,CLU,DATC,EPB,ESC,IAP,IBOX,LDWS_LKAS,SCC,TCU\n SG_ ENG_VOL : 56|8@1+ (0.1,0.0) [0.0|25.5] \"liter\"  _4WD,ABS,ACU,BCM,CLU,DATC,EPB,ESC,IBOX,LDWS_LKAS,SCC,SMK\n\nBO_ 1064 _4WD11: 8 _4WD\n SG_ _4WD_TYPE : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  ACU,ESC,TPMS\n SG_ _4WD_SUPPORT : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  ABS,ESC,TPMS\n SG_ _4WD_ERR : 8|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU,ESC\n SG_ CLU_DUTY : 16|8@1+ (1.0,0.0) [0.0|64.0] \"%\"  ABS,ESC\n SG_ R_TIRE : 24|8@1+ (1.0,200.0) [200.0|455.0] \"mm\"  ABS,ESC,TPMS\n SG_ _4WD_SW : 32|8@1+ (1.0,0.0) [0.0|9.9] \"\"  ESC\n SG_ _2H_ACT : 40|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,ESC\n SG_ _4H_ACT : 41|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,CLU,ESC,TPMS\n SG_ LOW_ACT : 42|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,ESC,TCU,TPMS\n SG_ AUTO_ACT : 43|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,ESC,TPMS\n SG_ LOCK_ACT : 44|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ABS,CLU,ESC,TPMS\n SG_ _4WD_TQC_CUR : 48|16@1+ (1.0,0.0) [0.0|65535.0] \"Nm\"  ABS,ESC\n\nBO_ 1319 HU_GW_E_01: 8 CLU\n SG_ C_ADrLNValueSet : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ C_ADrUNValueSet : 4|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ C_TwUnNValueSet : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_ABuzzerNValueSet : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_ArmWKeyNValueSet : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_PSMNValueSet : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_SCMNValueSet : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_HLEscortNValueSet : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_WELNValueSet : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_TriTurnLNValueSet : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_SNVWarnNValueSet : 24|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_LkasWarnNValueSet : 26|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n\nBO_ 1318 HU_GW_E_00: 8 CLU\n SG_ C_ADrLURValueReq : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_TwUnRValueReq : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_AlarmRValueReq : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_IMSRValueReq : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_HLEscortRValueReq : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_WELRValueReq : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_TriTurnLRValueReq : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_SNVWarnRValueReq : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ C_LkasWarnRValueReq : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n\nBO_ 1317 GW_HU_E_01: 8 BCM\n SG_ C_ADrLRValue : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ C_ADrURValue : 4|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ C_TwUnRValue : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_ABuzzerRValue : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_ArmWKeyRValue : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_PSMRValue : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SCMRValue : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_HLEscortRValue : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_WELRValue : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_TriTurnLRValue : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1316 GW_HU_E_00: 8 BCM\n SG_ C_ADrLUNValueConf : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_TwUnNValueConf : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_AlarmNValueConf : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_PSMNValueConf : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SCMNValueConf : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_HLEscortNValueConf : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_WELNValueConf : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_TriTurnLNValueConf : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1315 GW_SWRC_PE: 8 BCM\n SG_ C_ModeSW : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_MuteSW : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SeekDnSW : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SeekUpSW : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_BTPhoneCallSW : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_BTPhoneHangUpSW : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_DISCDownSW : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_DISCUpSW : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SdsSW : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_MTSSW : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_VolDnSW : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_VolUpSW : 24|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1314 GW_IPM_PE_1: 8 BCM\n SG_ C_AV_Tail : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_ParkingBrakeSW : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_RKECMD : 4|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ C_BAState : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_IGNSW : 12|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ C_CountryCfg : 16|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ C_TailLampActivity : 26|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ RearSW_RSELockOnOff : 28|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SMKTeleCrankingState : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_SMKTeleCrankingFailRes : 34|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1057 SCC12: 8 SCC\n SG_ CF_VSM_Prefill : 0|1@1+ (1,0) [0|1] \"\" ESC\n SG_ CF_VSM_DecCmdAct : 1|1@1+ (1,0) [0|1] \"\" ESC\n SG_ CF_VSM_HBACmd : 2|2@1+ (1,0) [0|3] \"\" ESC\n SG_ CF_VSM_Warn : 4|2@1+ (1,0) [0|3] \"\" CLU,ESC,IAP\n SG_ CF_VSM_Stat : 6|2@1+ (1,0) [0|3] \"\" CLU,ESC,PSB\n SG_ CF_VSM_BeltCmd : 8|3@1+ (1,0) [0|7] \"\" ESC,PSB\n SG_ ACCFailInfo : 11|2@1+ (1,0) [0|3] \"\" CLU,CUBIS,ESC,IBOX\n SG_ ACCMode : 13|2@1+ (1,0) [0|3] \"\" CLU,ESC,IBOX,TCU\n SG_ StopReq : 15|1@1+ (1,0) [0|1] \"\" EPB,ESC\n SG_ CR_VSM_DecCmd : 16|8@1+ (0.01,0) [0|2.55] \"g\" ESC\n SG_ TakeOverReq : 35|1@1+ (1,0) [0|1] \"\" CLU,ESC,TCU\n SG_ PreFill : 36|1@1+ (1,0) [0|1] \"\" ESC,TCU\n SG_ CF_VSM_ConfMode : 48|2@1+ (1,0) [0|3] \"\" CLU,ESC\n SG_ AEB_Failinfo : 50|2@1+ (1,0) [0|3] \"\" CLU,ESC\n SG_ AEB_Status : 52|2@1+ (1,0) [0|3] \"\" CLU,ESC\n SG_ AEB_CmdAct : 54|1@1+ (1,0) [0|1] \"\" ESC\n SG_ AEB_StopReq : 55|1@1+ (1,0) [0|1] \"\" CLU,ESC\n SG_ CR_VSM_Alive : 56|4@1+ (1,0) [0|15] \"\" ESC,PSB\n SG_ CR_VSM_ChkSum : 60|4@1+ (1,0) [0|15] \"\" ESC,PSB\n SG_ aReqValue : 37|11@1+ (0.01,-10.23) [-10.23|10.24] \"m/s^2\" Vector__XXX\n SG_ aReqRaw : 24|11@1+ (0.01,-10.23) [-10.23|10.24] \"m/s^2\" Vector__XXX\n\nBO_ 1313 GW_DDM_PE: 8 BCM\n SG_ C_DRVDoorStatus : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_ASTDoorStatus : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_RLDoorStatus : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_RRDoorStatus : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_TrunkStatus : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ C_OSMirrorStatus : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n\nBO_ 1056 SCC11: 8 SCC\n SG_ MainMode_ACC : 0|1@1+ (1,0) [0|1] \"\" CLU,EMS,ESC\n SG_ SCCInfoDisplay : 1|3@1+ (1,0) [0|7] \"\" CLU,ESC\n SG_ AliveCounterACC : 4|4@1+ (1,0) [0|15] \"\" CLU,EMS,ESC,TCU\n SG_ VSetDis : 8|8@1+ (1,0) [0|255] \"km/h or MPH\" CLU,ESC,TCU\n SG_ ObjValid : 16|1@1+ (1,0) [0|1] \"\" CLU,ESC,TCU\n SG_ DriverAlertDisplay : 17|2@1+ (1,0) [0|3] \"\" CLU,ESC\n SG_ TauGapSet : 19|3@1+ (1,0) [0|7] \"\" CLU,ESC,TCU\n SG_ Navi_SCC_Curve_Status : 56|2@1+ (1,0) [0|3] \"\" CLU\n SG_ Navi_SCC_Curve_Act : 58|2@1+ (1,0) [0|3] \"\" CLU\n SG_ Navi_SCC_Camera_Act : 60|2@1+ (1,0) [0|3] \"\" CLU\n SG_ Navi_SCC_Camera_Status : 62|2@1+ (1,0) [0|3] \"\" CLU\n SG_ ACC_ObjStatus : 22|2@1+ (1,0) [0|3] \"\" ABS,ESC\n SG_ ACC_ObjLatPos : 24|9@1+ (0.1,-20) [-20|31.1] \"m\" ABS,ESC\n SG_ ACC_ObjRelSpd : 44|12@1+ (0.1,-170) [-170|239.5] \"m/s\" ABS,ESC\n SG_ ACC_ObjDist : 33|11@1+ (0.1,0) [0|204.7] \"m\" ABS,ESC\n\nBO_ 1312 CGW3: 8 BCM\n SG_ CR_Photosensor_LH : 0|8@1+ (78.125,0.0) [0.0|20000.0] \"\"  DATC,DATC\n SG_ CR_Photosensor_RH : 10|8@1+ (78.125,0.0) [0.0|20000.0] \"\"  DATC,DATC\n SG_ CF_Hoodsw_memory : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,EMS\n SG_ C_MirOutTempSns : 24|8@1+ (0.5,-40.5) [-40.0|60.0] \"deg\"  AAF,CLU,DATC,EMS,SPAS,AAF,DATC,EMS,SPAS\n\nBO_ 544 ESP12: 8 ESC\n SG_ LAT_ACCEL : 0|11@1+ (0.01,-10.23) [-10.23|10.24] \"m/s^2\"  _4WD,ECS,IBOX,LCA,LDWS_LKAS,MDPS,PSB,SCC,TCU\n SG_ LAT_ACCEL_STAT : 11|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,IBOX,LDWS_LKAS,MDPS,PSB,SCC,TCU\n SG_ LAT_ACCEL_DIAG : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,IBOX,LDWS_LKAS,MDPS,PSB,SCC,TCU\n SG_ LONG_ACCEL : 13|11@1+ (0.01,-10.23) [-10.23|10.24] \"m/s^2\"  _4WD,ECS,EMS,EPB,IBOX,LCA,LDWS_LKAS,PSB,SCC,SPAS,TCU\n SG_ LONG_ACCEL_STAT : 24|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,IBOX,LDWS_LKAS,PSB,SCC,SPAS,TCU\n SG_ LONG_ACCEL_DIAG : 25|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,IBOX,LDWS_LKAS,PSB,SCC,SPAS,TCU\n SG_ CYL_PRES : 26|12@1+ (0.1,0.0) [0.0|409.5] \"Bar\"  _4WD,ECS,EMS,EPB,IBOX,LDWS_LKAS,PSB,SCC,TCU\n SG_ CYL_PRES_STAT : 38|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ECS,EMS,EPB,IBOX,LDWS_LKAS,PSB,SCC,TCU\n SG_ CYL_PRESS_DIAG : 39|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ECS,EMS,EPB,IBOX,PSB,SCC,TCU\n SG_ YAW_RATE : 40|13@1+ (0.01,-40.95) [-40.95|40.96] \"\"  _4WD,AFLS,IBOX,LCA,LDWS_LKAS,MDPS,PSB,SCC,SPAS,TCU\n SG_ YAW_RATE_STAT : 53|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,AFLS,IBOX,LCA,LDWS_LKAS,MDPS,PSB,SCC,SPAS,TCU\n SG_ YAW_RATE_DIAG : 54|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,AFLS,IBOX,LCA,LDWS_LKAS,MDPS,PSB,SCC,SPAS,TCU\n SG_ ESP12_Checksum : 56|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,LPI,TCU,TMU\n SG_ ESP12_AliveCounter : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,LPI,TCU,TMU\n\nBO_ 1307 CLU16: 8 CLU\n SG_ CF_Clu_TirePressUnitNValueSet : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  TPMS\n SG_ CF_Clu_SlifNValueSet : 3|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LDWS_LKAS\n SG_ CF_Clu_RearWiperNValueSet : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n\nBO_ 790 EMS11: 8 EMS\n SG_ SWI_IGK : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ABS,ACU,AHLS,CUBIS,DI_BOX,ECS,EPB,ESC,IBOX,LDWS_LKAS,MDPS,REA,SAS,SCC,TCU\n SG_ F_N_ENG : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,AFLS,CLU,CUBIS,DATC,ECS,EPB,ESC,IBOX,MDPS,SCC,TCU\n SG_ ACK_TCS : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,IBOX\n SG_ PUC_STAT : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,DATC,IBOX,TCU\n SG_ TQ_COR_STAT : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,ESC,IBOX,TCU\n SG_ RLY_AC : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DATC,IBOX,TCU\n SG_ F_SUB_TQI : 7|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ECS,EPB,ESC,IBOX,TCU\n SG_ TQI_ACOR : 8|8@1+ (0.390625,0.0) [0.0|99.6094] \"%\"  _4WD,EPB,ESC,IBOX,TCU\n SG_ N : 16|16@1+ (0.25,0.0) [0.0|16383.75] \"rpm\"  _4WD,ACU,AFLS,CLU,CUBIS,DATC,ECS,EPB,ESC,FPCM,IBOX,MDPS,SCC,TCU\n SG_ TQI : 32|8@1+ (0.390625,0.0) [0.0|99.6094] \"%\"  _4WD,ECS,EPB,ESC,IBOX,TCU\n SG_ TQFR : 40|8@1+ (0.390625,0.0) [0.0|99.6094] \"%\"  _4WD,EPB,ESC,IBOX,TCU\n SG_ VS : 48|8@1+ (1.0,0.0) [0.0|254.0] \"km/h\"  _4WD,AAF,ACU,AHLS,BCM,CLU,DATC,ECS,EPB,IBOX,LCA,LDWS_LKAS,LVR,MDPS,ODS,SCC,SMK,SPAS,TCU,TPMS\n SG_ RATIO_TQI_BAS_MAX_STND : 56|8@1+ (0.0078,0.0) [0.0|2.0] \"\"  _4WD,IBOX,TCU\n\nBO_ 1301 CLU14: 8 CLU\n SG_ CF_Clu_ADrUNValueSet : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_ADrLNValueSet : 3|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_EscortHLNValueSet : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Clu_DoorLSNValueSet : 8|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_PSMNValueSet : 11|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_TTUnlockNValueSet : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Clu_PTGMNValueSet : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Clu_SCMNValueSet : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Clu_WlightNValueSet : 20|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Clu_TempUnitNValueSet : 22|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,DATC\n SG_ CF_Clu_MoodLpNValueSet : 24|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_TrfChgSet : 27|2@1+ (1.0,0.0) [0.0|3.0] \"\"  AFLS\n SG_ CF_Clu_OTTurnNValueSet : 29|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_LcaNValueSet : 32|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LCA\n SG_ CF_Clu_RctaNValueSet : 34|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LCA\n SG_ CF_Clu_RcwNValueSet : 36|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LCA\n SG_ CF_Clu_EscOffNValueSet : 38|3@1+ (1.0,0.0) [0.0|7.0] \"\"  ESC\n SG_ CF_Clu_SccNaviCrvNValueSet : 41|2@1+ (1.0,0.0) [0.0|3.0] \"\"  SCC\n SG_ CF_Clu_SccNaviCamNValueSet : 43|2@1+ (1.0,0.0) [0.0|3.0] \"\"  SCC\n SG_ CF_Clu_SccAebNValueSet : 45|2@1+ (1.0,0.0) [0.0|3.0] \"\"  SCC\n SG_ CF_Clu_LkasModeNValueSet : 47|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LDWS_LKAS\n SG_ CF_Clu_FcwNValueSet : 51|2@1+ (1.0,0.0) [0.0|3.0] \"\"  LDWS_LKAS\n SG_ CF_Clu_PasSpkrLvNValueSet : 53|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n SG_ CF_Clu_SccDrvModeNValueSet : 56|3@1+ (1.0,0.0) [0.0|7.0] \"\"  SCC\n SG_ CF_Clu_HAnBNValueSet : 59|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM\n SG_ CF_Clu_HfreeTrunkTgNValueSet : 61|3@1+ (1.0,0.0) [0.0|7.0] \"\"  BCM\n\nBO_ 275 TCU13: 8 TCU\n SG_ N_TGT_LUP : 0|8@1+ (10.0,500.0) [500.0|3040.0] \"rpm\"  EMS,IBOX\n SG_ SLOPE_TCU : 8|6@1+ (0.5,-16.0) [-16.0|15.5] \"%\"  CLU,CUBIS,EMS,IBOX\n SG_ CF_Tcu_InhCda : 14|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_IsgInhib : 15|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_BkeOnReq : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_NCStat : 18|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_TarGr : 20|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,CLU,DATC,EMS,EPB,ESC,IBOX,SCC\n SG_ CF_Tcu_ShfPatt : 24|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU,CUBIS,EMS,IBOX\n SG_ CF_Tcu_InhVis : 28|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_PRelReq : 29|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX,LVR\n SG_ CF_Tcu_ITPhase : 30|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_ActEcoRdy : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_TqGrdLim : 32|8@1+ (10.0,0.0) [0.0|2540.0] \"Nm/s\"  EMS,IBOX\n SG_ CR_Tcu_IsgTgtRPM : 40|8@1+ (20.0,0.0) [0.0|3500.0] \"rpm\"  EMS,IBOX\n SG_ CF_Tcu_SptRdy : 48|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,IBOX\n SG_ CF_Tcu_SbwPInfo : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_Alive3 : 58|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_ChkSum3 : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS,IBOX\n\nBO_ 274 TCU12: 8 TCU\n SG_ ETL_TCU : 0|8@1+ (2.0,0.0) [0.0|508.0] \"Nm\"  EMS,IBOX\n SG_ CUR_GR : 8|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,EMS,ESC,IBOX,SCC,TPMS\n SG_ CF_Tcu_Alive : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,ESC,IBOX,SCC\n SG_ CF_Tcu_ChkSum : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,ESC,IBOX,SCC\n SG_ VS_TCU : 16|8@1+ (1.0,0.0) [0.0|254.0] \"km/h\"  BCM,CLU,DATC,EMS,IBOX,LCA,LVR,PGS,SMK,SNV\n SG_ FUEL_CUT_TCU : 28|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ INH_FUEL_CUT : 29|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ IDLE_UP_TCU : 30|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ N_INC_TCU : 31|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS,IBOX\n SG_ SPK_RTD_TCU : 32|8@1+ (0.375,-23.625) [-15.0|15.0] \"\"  EMS,IBOX\n SG_ N_TC_RAW : 40|16@1+ (0.25,0.0) [0.0|16383.5] \"rpm\"  EMS,IBOX\n SG_ VS_TCU_DECIMAL : 56|8@1+ (0.0078125,0.0) [0.0|0.9921875] \"km/h\"  CLU,EMS,IBOX,LCA\n\nBO_ 273 TCU11: 8 TCU\n SG_ TQI_TCU_INC : 0|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  EMS,ESC,IBOX\n SG_ G_SEL_DISP : 8|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,AFLS,AVM,BCM,CGW,CLU,CUBIS,ECS,EMS,EPB,ESC,IAP,IBOX,LCA,LDWS_LKAS,LVR,MDPS,PGS,SCC,SMK,SNV,SPAS,TPMS\n SG_ F_TCU : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,ESC,IBOX\n SG_ TCU_TYPE : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,EMS,ESC,IBOX\n SG_ TCU_OBD : 16|3@1+ (1.0,0.0) [0.0|7.0] \"\"  EMS,ESC,IBOX\n SG_ SWI_GS : 19|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,EMS,EPB,ESC,IBOX,SCC\n SG_ GEAR_TYPE : 20|4@1+ (1.0,0.0) [0.0|15.0] \"\"  _4WD,CLU,EMS,ESC,IBOX,SCC\n SG_ TQI_TCU : 24|8@1+ (0.390625,0.0) [0.0|99.609375] \"%\"  EMS,ESC,IBOX\n SG_ TEMP_AT : 32|8@1+ (1.0,-40.0) [-40.0|214.0] \"deg\"  AAF,CLU,CUBIS,EMS,ESC,IBOX\n SG_ N_TC : 40|16@1+ (0.25,0.0) [0.0|16383.5] \"rpm\"  _4WD,EMS,EPB,ESC,IBOX\n SG_ SWI_CC : 56|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,CLU,EMS,ESC,IBOX\n SG_ CF_Tcu_Alive1 : 58|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EMS,IBOX\n SG_ CF_Tcu_ChkSum1 : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS,IBOX\n\nBO_ 16 ACU13: 8 ACU\n SG_ CF_Acu_CshAct : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CUBIS,IBOX,ODS\n\nBO_ 1040 CGW_USM1: 8 BCM\n SG_ CF_Gway_ATTurnRValue : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_PTGMRValue : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_EscortHLRValue : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_TTUnlockRValue : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_ADrLRValue : 8|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_ADrURValue : 11|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_SCMRValue : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_WlightRValue : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_PSMRValue : 18|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_OTTurnRValue : 21|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_DrLockSoundRValue : 24|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_HAnBRValue : 27|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_MoodLpRValue : 30|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_HfreeTrunkRValue : 32|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_AutoLightRValue : 35|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_Gway_RearWiperRValue : 38|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_Gway_PasSpkrLvRValue : 40|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n\nBO_ 1292 CLU13: 8 CLU\n SG_ CF_Clu_LowfuelWarn : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,FPCM,IBOX\n SG_ CF_Clu_RefDetMod : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  IBOX\n SG_ CF_Clu_AvgFCU : 3|2@1+ (1.0,0.0) [0.0|3.0] \"\"  IBOX\n SG_ CF_Clu_AvsmCur : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  ESC,SCC\n SG_ CF_Clu_AvgFCI : 6|10@1+ (0.1,0.0) [0.0|102.2] \"\"  IBOX\n SG_ CF_Clu_DrivingModeSwi : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC,ECS,EMS,ESC,IAP,MDPS,TCU\n SG_ CF_Clu_FuelDispLvl : 18|5@1+ (1.0,0.0) [0.0|31.0] \"\"  CGW,IBOX\n SG_ CF_Clu_FlexSteerSW : 23|1@1+ (1.0,0.0) [0.0|1.0] \"\"  MDPS\n SG_ CF_Clu_DTE : 24|10@1+ (1.0,0.0) [0.0|1023.0] \"\"  DATC\n SG_ CF_Clu_TripUnit : 34|2@1+ (1.0,0.0) [0.0|3.0] \"\"  DATC\n SG_ CF_Clu_SWL_Stat : 36|3@1+ (1.0,0.0) [0.0|7.0] \"\"  ACU,EMS\n SG_ CF_Clu_ActiveEcoSW : 39|1@1+ (1.0,0.0) [0.0|1.0] \"\"  DATC,EMS,TCU\n SG_ CF_Clu_EcoDriveInf : 40|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CUBIS,EMS,IAP,IBOX\n SG_ CF_Clu_IsaMainSW : 43|1@1+ (1.0,0.0) [0.0|1.0] \"\"  EMS\n SG_ CF_Clu_LdwsLkasSW : 56|1@1+ (1.0,0.0) [0.0|1.0] \"\"  LDWS_LKAS\n SG_ CF_Clu_AltLStatus : 59|1@1+ (1.0,0.0) [0.0|1.0] \"\"  BCM,DATC,EMS\n SG_ CF_Clu_AliveCnt2 : 60|4@1+ (1.0,0.0) [0.0|15.0] \"\"  EMS,LDWS_LKAS\n\nBO_ 1290 SCC13: 8 SCC\n SG_ SCCDrvModeRValue : 0|3@1+ (1,0) [0|7] \"\" CLU\n SG_ SCC_Equip : 3|1@1+ (1,0) [0|1] \"\" ESC\n SG_ AebDrvSetStatus : 4|3@1+ (1,0) [0|7] \"\" CLU,ESC\n SG_ Lead_Veh_Dep_Alert_USM : 13|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 1287 TCS15: 4 ESC\n SG_ ABS_W_LAMP : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU,CUBIS,IBOX\n SG_ TCS_OFF_LAMP : 1|2@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,ACU,CLU\n SG_ TCS_LAMP : 3|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,ACU,CLU,CUBIS,IBOX,SCC\n SG_ DBC_W_LAMP : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU\n SG_ DBC_F_LAMP : 6|2@1+ (1.0,0.0) [0.0|3.0] \"\"  _4WD,CLU\n SG_ ESC_Off_Step : 8|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ AVH_CLU : 16|8@1+ (1.0,0.0) [0.0|255.0] \"\"  CLU,EPB\n SG_ AVH_I_LAMP : 24|2@1+ (1.0,0.0) [0.0|3.0] \"\"  EPB\n SG_ EBD_W_LAMP : 26|1@1+ (1.0,0.0) [0.0|1.0] \"\"  _4WD,CLU\n SG_ AVH_ALARM : 27|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ AVH_LAMP : 29|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,EPB,SPAS\n\nBO_ 1282 TCU14: 4 TCU\n SG_ CF_TCU_WarnMsg : 0|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU\n SG_ CF_TCU_WarnImg : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_TCU_WarnSnd : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ CF_Tcu_GSel_BlinkReq : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,LVR\n SG_ CF_Tcu_StRelStat : 12|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,EMS,ESC\n SG_ CF_Tcu_DriWarn1 : 13|3@1+ (1.0,0.0) [0.0|7.0] \"\"  CLU,EMS,ESC\n SG_ CF_Tcu_DriWarn2 : 16|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU,EMS,ESC\n\nBO_ 1281 ECS11: 3 ECS\n SG_ ECS_W_LAMP : 0|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU,CUBIS,IBOX\n SG_ SYS_NA : 1|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ ECS_DEF : 2|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ ECS_DIAG : 3|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ L_CHG_NA : 4|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ Leveling_Off : 5|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ LC_overheat : 6|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ Lifting : 8|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ Lowering : 9|1@1+ (1.0,0.0) [0.0|1.0] \"\"  CLU\n SG_ Damping_Mode : 10|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ REQ_Damping : 12|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ REQ_Height : 14|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ REQ_level : 16|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n SG_ ACT_Height : 20|4@1+ (1.0,0.0) [0.0|15.0] \"\"  CLU\n\nBO_ 1024 CLU_CFG11: 2 CLU\n SG_ Vehicle_Type : 0|16@1+ (1.0,0.0) [0.0|65536.0] \"\"  _4WD\n\nBO_ 1280 ACU14: 1 ACU\n SG_ CF_SWL_Ind : 0|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_TTL_Ind : 2|2@1+ (1.0,0.0) [0.0|3.0] \"\"  CLU\n SG_ CF_SBR_Ind : 4|2@1+ (1.0,0.0) [0.0|3.0] \"\"  BCM,CLU\n\nBO_ 512 EMS20: 6 EMS\n SG_ FCO : 0|16@1+ (0.128,0.0) [0.0|8388.48] \"ul\"  CLU,CUBIS,FPCM,IBOX\n SG_ CF_Ems_PumpTPres : 16|8@1+ (3.137254902,0.0) [0.0|800.0] \"kPa\"  FPCM,IBOX\n SG_ Split_Stat : 32|1@1+ (1.0,0.0) [0.0|1.0] \"\"  FPCM\n\nBO_ 909 FCA11: 8 FCA\n SG_ CF_VSM_Prefill : 0|1@1+ (1,0) [0|1] \"\" ESC\n SG_ CF_VSM_HBACmd : 1|2@1+ (1,0) [0|3] \"\" ESC\n SG_ CF_VSM_Warn : 3|2@1+ (1,0) [0|3] \"\" ACU,CLU,ESC\n SG_ CF_VSM_BeltCmd : 5|3@1+ (1,0) [0|7] \"\" ESC\n SG_ CR_VSM_DecCmd : 8|8@1+ (0.01,0) [0|2.55] \"g\" ESC\n SG_ FCA_Status : 18|2@1+ (1,0) [0|3] \"\" ACU,CLU,ESC\n SG_ FCA_CmdAct : 20|1@1+ (1,0) [0|1] \"\" ESC\n SG_ FCA_StopReq : 21|1@1+ (1,0) [0|1] \"\" CLU,ESC\n SG_ FCA_DrvSetStatus : 22|3@1+ (1,0) [0|7] \"\" CLU,ESC\n SG_ CF_VSM_DecCmdAct : 31|1@1+ (1,0) [0|1] \"\" ESC\n SG_ FCA_Failinfo : 32|3@1+ (1,0) [0|7] \"\" ACU,CLU,ESC\n SG_ FCA_RelativeVelocity : 39|9@1+ (0.1,-25.5) [-25.5|25.5] \"m/s\" iBAU\n SG_ FCA_TimetoCollision : 48|8@1+ (10,0) [0|2540] \"ms\" iBAU\n SG_ CR_FCA_Alive : 56|4@1+ (1,0) [0|15] \"\" ESC\n SG_ CR_FCA_ChkSum : 60|4@1+ (1,0) [0|15] \"\" ESC\n SG_ Supplemental_Counter : 35|4@1+ (1,0) [0|15] \"\" XXX\n SG_ PAINT1_Status : 16|2@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 1156 HDA11_MFC: 8 XXX\n SG_ Counter : 5|4@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_1 : 1|2@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_3 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 16|2@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_5 : 18|14@1+ (1,0) [0|63] \"\" XXX\n SG_ NEW_SIGNAL_6 : 33|2@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 34|14@1+ (1,0) [0|16383] \"\" XXX\n SG_ NEW_SIGNAL_8 : 49|2@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_9 : 50|14@1- (1,-4095) [0|16383] \"\" XXX\n\nBO_ 1155 FCA12: 8 FCA\n SG_ FCA_USM : 0|3@1+ (1,0) [0|7] \"\" CGW,CLU,ESC\n SG_ FCA_DrvSetState : 3|3@1+ (1,0) [0|7] \"\" CGW\n\nBO_ 1186 FRT_RADAR11: 2 FCA\n SG_ CF_FCA_Equip_Front_Radar : 0|3@1+ (1,0) [0|7] \"\" LDWS_LKAS,LDW_LKA,ESC\n\nBO_ 905 SCC14: 8 SCC\n SG_ ComfortBandUpper : 0|6@1+ (0.02,0) [0|1.26] \"m/s^2\" ESC\n SG_ ComfortBandLower : 6|6@1+ (0.02,0) [0|1.26] \"m/s^2\" ESC\n SG_ JerkUpperLimit : 12|7@1+ (0.1,0) [0|12.7] \"m/s^3\" ESC\n SG_ JerkLowerLimit : 19|7@1+ (0.1,0) [0|12.7] \"m/s^3\" ESC\n SG_ ACCMode : 32|3@1+ (1,0) [0|7] \"\" CLU,HUD,LDWS_LKAS,ESC\n SG_ ObjGap : 56|8@1+ (1,0) [0|255] \"\" CLU,HUD,ESC\n\nBO_ 1157 LFAHDA_MFC: 4 XXX\n SG_ HDA_USM : 0|2@1+ (1,0) [0|3] \"\" XXX\n SG_ HDA_Active : 2|1@1+ (1,0) [0|1] \"\" XXX\n SG_ HDA_Icon_State : 3|2@1+ (1,0) [0|3] \"\" XXX\n SG_ HDA_Chime : 7|1@1+ (1,0) [0|1] \"\" XXX\n SG_ HDA_VSetReq : 8|8@1+ (1,0) [0|255] \"km/h\" XXX\n SG_ LFA_SysWarning : 16|3@1+ (1,0) [0|7] \"\" XXX\n SG_ NEW_SIGNAL_1 : 20|3@1+ (1,0) [0|7] \"\" XXX\n SG_ LFA_Icon_State : 24|2@1+ (1,0) [0|3] \"\" XXX\n SG_ LFA_USM : 27|2@1+ (1,0) [0|3] \"\" XXX\n SG_ HDA_SysWarning : 29|2@1+ (1,0) [0|3] \"\" XXX\n\nBO_ 913 BCM_PO_11: 8 Vector__XXX\n SG_ BCM_Door_Dri_Status : 5|1@0+ (1,0) [0|1] \"\" PT_ESC_ABS\n SG_ BCM_Shift_R_MT_SW_Status : 39|2@0+ (1,0) [0|3] \"\" PT_ESC_ABS\n SG_ LFA_Pressed : 4|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1426 LABEL11: 8 XXX\n SG_ CC_React : 34|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 910 WHL_SPD12_FS: 5 iBAU\n SG_ CRC : 0|8@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ WHL_SPD12_AliveCounter : 8|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ WHL_SPD_FL : 12|14@1+ (0.03125,0) [0|511.96875] \"km/h\" Vector__XXX\n SG_ WHL_SPD_FR : 26|14@1+ (0.03125,0) [0|511.96875] \"km/h\" Vector__XXX\n\nBO_ 911 WHL_SPD13_FS: 5 iBAU\n SG_ CRC : 0|8@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ WHL_SPD13_AliveCounter : 8|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ WHL_SPD_RL : 12|14@1+ (0.03125,0) [0|511.96875] \"km/h\" Vector__XXX\n SG_ WHL_SPD_RR : 26|14@1+ (0.03125,0) [0|511.96875] \"km/h\" Vector__XXX\n\nBO_ 865 ADAS_PRK_11: 8 ADAS_PRK\n SG_ CF_PCA_BrkReq : 24|1@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ CF_PCA_DclTrgtVal : 28|4@1+ (0.04,0) [0|0] \"g\" Vector__XXX\n SG_ PCA_ALIVE_CNT : 40|4@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ PCA_CHECK_SUM : 48|8@1+ (1,0) [0|0] \"\" Vector__XXX\n\nBO_ 882 ELECT_GEAR: 8 XXX\n SG_ Elect_Gear_Shifter : 16|4@1+ (1,0) [0|7] \"\"  CLU\n\nBO_ 881 E_EMS11: 8 XXX\n SG_ Brake_Pedal_Pos : 0|8@1+ (1,0) [0|127] \"\" XXX\n SG_ IG_Reactive_Stat : 8|3@1+ (1,0) [0|3] \"\" XXX\n SG_ Gear_Change : 12|1@0+ (1,0) [0|31] \"\" XXX\n SG_ Cruise_Limit_Status : 13|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Limit_Target : 23|8@1+ (1,0) [0|15] \"\" XXX\n SG_ Accel_Pedal_Pos : 31|8@1+ (1,0) [0|254] \"\" XXX\n SG_ CR_Vcu_AccPedDep_Pos : 56|8@1+ (1,0) [0|254] \"\" XXX\n\nBO_ 1355 EV_PC6: 8 CGW\n SG_ CF_Vcu_SbwWarnMsg : 16|3@1+ (1,0) [0|7] \"\" Vector__XXX\n\nBO_ 1430 EV_PC2: 8 CGW\n SG_ CR_Ldc_ActVol_LS_V : 32|8@1+ (0.1,0) [0|0] \"V\" Vector__XXX\n\nBO_ 1535 EV_PC10: 8 CGW\n SG_ CF_Vcu_EpbRequest : 37|1@1+ (1,0) [0|0] \"\" Vector__XXX\n\nBO_ 908 RSPA11: 8 RSPA\n SG_ CF_RSPA_State : 0|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CF_RSPA_Act : 4|2@1+ (1,0) [0|3] \"\" XXX\n SG_ CF_RSPA_DecCmd : 6|2@1+ (1,0) [0|3] \"\" XXX\n SG_ CF_RSPA_Trgt_Spd : 8|10@1+ (0.01,0) [0|10.23] \"km/h\" XXX\n SG_ CF_RSPA_StopReq : 18|1@1+ (1,0) [0|2] \"\" XXX\n SG_ CR_RSPA_EPB_Req : 22|2@1+ (1,0) [0|3] \"\" XXX\n SG_ CF_RSPA_ACC_ACT : 50|1@1+ (1,0) [0|2] \"\" XXX\n SG_ CF_RSPA_AliveCounter : 52|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CF_RSPA_CRC : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 914 S_MDPS11: 8 XXX\n SG_ CF_Mdps_Stat : 0|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CR_Mdps_DrvTq : 8|12@1+ (1,0) [0|15] \"\" XXX\n SG_ CR_Mdps_StrAng : 24|16@1- (1,0) [0|65535] \"\" XXX\n SG_ CF_Mdps_AliveCnt : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CF_Mdps_Chksum : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 357 S_MDPS12: 8 XXX\n SG_ NEW_SIGNAL_1 : 0|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ NEW_SIGNAL_2 : 12|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Counter : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Checksum : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 352 AHB1: 8 iBAU\n SG_ CF_Ahb_SLmp : 0|2@1+ (1,0) [0|3] \"\" CLU\n SG_ CF_Ahb_Def : 2|2@1+ (1,0) [0|3] \"\" CGW\n SG_ CF_Ahb_Act : 4|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ CF_Ahb_Diag : 6|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ CF_Ahb_WLmp : 7|1@1+ (1,0) [0|1] \"\" CLU\n SG_ CR_Ahb_StDep_mm : 8|16@1- (0.1,0) [-3276.8|3276.7] \"mm\" Vector__XXX\n SG_ CF_Ahb_SnsFail : 24|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ CF_Ahb_PedalCalStat : 25|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ CF_Ahb_Bzzr : 26|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ CF_Ahb_ChkSum : 56|8@1+ (1,0) [0|255] \"\" Vector__XXX\n\nBO_ 1191 MFC_4a7: 8 XXX\n SG_ PAINT1 : 0|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1162 BCA11: 8 BCW\n SG_ CF_BCA_State : 16|3@1+ (1,0) [0|7] \"\" CLU,iBAU\n SG_ CF_BCA_Warning : 19|2@1+ (1,0) [0|3] \"\" CLU,iBAU\n SG_ AliveCounter : 21|4@1+ (1,0) [0|15] \"\" CLU,iBAU\n SG_ RCCA_Brake_Command : 29|1@1+ (1,0) [0|1] \"\" iBAU\n SG_ Check_Sum : 56|8@1+ (1,0) [0|16] \"\" iBAU\n\nBO_ 1136 P_STS: 8 CGW\n SG_ HCU1_STS : 6|2@1+ (1,0) [0|3] \"\" BCW,EPB,FCA,MDPS,SCC,iBAU\n SG_ HCU5_STS : 8|2@1+ (1,0) [0|3] \"\" EPB,FCA,MDPS,iBAU\n SG_ Counter : 58|4@1+ (1,0) [0|15] \"\" MDPS\n SG_ Checksum : 62|2@1+ (1,0) [0|3] \"\" MDPS\n\nBO_ 304 YRS11: 8 ACU\n SG_ CR_Yrs_Yr : 0|16@1+ (0.005,-163.84) [-163.84|163.83] \"deg/s\" CGW,iBAU\n SG_ CR_Yrs_LatAc : 16|16@1+ (0.000127465,-4.17677312) [-4.17677312|4.17651819] \"g\" iBAU\n SG_ CF_Yrs_YrStat : 32|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CF_Yrs_LatAcStat : 36|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CF_Yrs_MCUStat : 40|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CR_Yrs_MsgCnt1 : 48|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CR_Yrs_Crc1 : 56|8@1+ (1,0) [0|255] \"\" iBAU\n\nBO_ 320 YRS12: 8 ACU\n SG_ CF_Yrs_LongAcStat : 16|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CF_IMU_ResetStat : 20|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ YRS_Temp : 24|8@1+ (1,-68) [-68|187] \"\" iBAU\n SG_ YRS_TempStat : 32|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CF_Yrs_Type : 36|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CR_Yrs_MsgCnt2 : 48|4@1+ (1,0) [0|15] \"\" iBAU\n SG_ CR_Yrs_Crc2 : 56|8@1+ (1,0) [0|255] \"\" iBAU\n SG_ CR_Yrs_LongAc : 0|16@1+ (0.000127465,-4.17677312) [-4.17677312|4.17651819] \"g\" CGW,iBAU\n\nBO_ 1173 YRS13: 8 ACU\n SG_ YRS_SeralNo : 16|48@1+ (1,0) [0|281474976710655] \"\" iBAU\n\nBO_ 870 EMS_366: 8 EMS\n SG_ TQI_1 : 0|8@1+ (0.390625,0) [0|99.6094] \"%\" MDPS\n SG_ N : 8|16@1+ (0.25,0.0) [0.0|16383.75] \"rpm\" MDPS\n SG_ TQI_2 : 24|8@1+ (0.390625,0) [0|99.6094] \"%\" MDPS\n SG_ VS : 40|8@1+ (1,0) [0|255] \"km/h\" MDPS\n SG_ SWI_IGK : 48|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 854 M_356: 8 XXX\n SG_ PAINT1 : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PAINT2 : 34|2@0+ (1,0) [0|1] \"\" XXX\n SG_ PAINT3 : 36|2@0+ (1,0) [0|3] \"\" XXX\n SG_ PAINT4 : 38|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 ICM_412h: 8 ICM\n SG_ T_Outside_input : 0|9@0+ (0.01,0) [0|5] \"V\" Vector__XXX\n SG_ WarningSoundOutput_1Group : 5|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ WarningSoundOutput_2Group : 6|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ WarningSoundOutput_3Group : 7|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ TRIP_A_DT_Display_clock : 22|7@0+ (1,0) [0|99] \"clock\" Vector__XXX\n SG_ TRIP_A_DT_Display_minute : 29|6@0+ (1,0) [0|59] \"minute\" Vector__XXX\n SG_ TRIP_B_DT_Display_clock : 38|7@0+ (1,0) [0|99] \"clock\" Vector__XXX\n SG_ TRIP_B_DT_Display_minute : 45|6@0+ (1,0) [0|59] \"minute\" Vector__XXX\n SG_ PopupMessageOutput_1Level : 48|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_2Level : 49|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_3Level : 50|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_4Level : 51|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_5Level : 52|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_6Level : 53|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_7Level : 54|1@0+ (1,0) [0|1] \"\" Vector__XXX\n SG_ PopupMessageOutput_8Level : 55|1@0+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 1348 Navi_HU: 8 XXX\n SG_ SpeedLim_Nav_Clu : 7|8@0+ (1,0) [0|255] \"\" XXX\n\n\n\n\nVAL_ 871 CF_Lvr_Gear 5 \"D\" 8 \"S\" 6 \"N\" 7 \"R\" 0 \"P\" ;\nVAL_ 1322 CF_Clu_Gear 1 \"P\" 2 \"R\" 4 \"N\" 8 \"D\" ;\nVAL_ 274 CUR_GR 1 \"D\" 2 \"D\" 3 \"D\" 4 \"D\" 5 \"D\" 6 \"D\" 7 \"D\" 8 \"D\" 14 \"R\" 0 \"P\" ;\nVAL_ 909 CF_VSM_Warn 2 \"FCW\" 3 \"AEB\" ;\nVAL_ 1157 HDA_Icon_State 0 \"no_hda\" 1 \"white_hda\" 2 \"green_hda\" ;\nVAL_ 1157 LFA_SysWarning 0 \"no_message\" 1 \"switching_to_hda\" 2 \"switching_to_scc\" 3 \"lfa_error\" 4 \"check_hda\" 5 \"keep_hands_on_wheel_orange\" 6 \"keep_hands_on_wheel_red\" ;\nVAL_ 1157 LFA_Icon_State 0 \"no_wheel\" 1 \"white_wheel\" 2 \"green_wheel\" 3 \"green_wheel_blink\" ;\nVAL_ 1157 HDA_SysWarning 0 \"no_message\" 1 \"driving_convenience_systems_cancelled\" 2 \"highway_drive_assist_system_cancelled\" ;\nVAL_ 882 Elect_Gear_Shifter 5 \"D\" 8 \"S\" 6 \"N\" 7 \"R\" 0 \"P\" ;\nCM_ \"BO_ E_EMS11: All (plug-in) hybrids use this gas signal: CR_Vcu_AccPedDep_Pos, and all EVs use the Accel_Pedal_Pos signal. See hyundai/values.py for a specific car list\";\nCM_ SG_ 1348 SpeedLim_Nav_Clu \"Speed limit displayed on Nav, Cluster and HUD\";"
  },
  {
    "path": "opendbc/lexus_ct200h_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"lexus_ct200h_2018_pt.dbc starts here\";\n\n\n\nBO_ 548 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 43|12@0+ (1,0) [0|4047] \"\" XXX\n SG_ BRAKE_PRESSED : 5|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (1,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/lexus_is300h_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\"\n\n\nCM_ \"Imported file _comma.dbc starts here\"\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM BO_ STEERING_IPAS_COMMA \"Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\"\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ SET_ME_X01 : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was \"SET_ME_1\" and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\"\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 129 \"no entry\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\nCM_ \"lexus_is_2018_pt.dbc starts here\"\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL_ALT: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (1.30,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nBO_ 1009 PCM_CRUISE_ALT: 8 XXX\n SG_ MAIN_ON : 13|1@0+ (1,0) [0|3] \"\" XXX\n SG_ CRUISE_STATE : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n\nBO_ 1599 LIGHT_STALK_ISH: 8 SCM\n SG_ AUTO_HIGH_BEAM : 19|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nCM_ SG_ 1009 SET_SPEED \"units seem to be whatever the car is set to\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/lexus_is_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"lexus_is_2018_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL_ALT: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.77,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nBO_ 1009 PCM_CRUISE_ALT: 8 XXX\n SG_ MAIN_ON : 13|1@0+ (1,0) [0|3] \"\" XXX\n SG_ CRUISE_STATE : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"mph\" XXX\n\nBO_ 1599 LIGHT_STALK_ISH: 8 SCM\n SG_ AUTO_HIGH_BEAM : 19|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nCM_ SG_ 1009 SET_SPEED \"units seem to be whatever the car is set to\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/lexus_nx300_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"lexus_nx300_2018_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/lexus_nx300h_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"lexus_nx300h_2018_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/lexus_rx_350_2016_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"lexus_rx_350_2016_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_PEDAL : 55|8@0+ (1,0) [0|255] \"\" XXX\n\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\" ;\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\" ;\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\" ;\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\" ;\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\" ;\n"
  },
  {
    "path": "opendbc/lexus_rx_hybrid_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"lexus_rx_hybrid_2017_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/mazda_2017.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\n\nBO_ 117 STEER_RELATED: 8 XXX\n SG_ CTR : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_2 : 49|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_5 : 50|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 54|4@0+ (1,0) [0|31] \"\" XXX\n SG_ NEW_SIGNAL_3 : 55|1@0+ (1,0) [0|63] \"\" XXX\n SG_ STEER_ANGLE_2 : 39|16@0+ (0.1,-1800) [0|131071] \"\" XXX\n SG_ STEER_TORQUE : 19|12@0+ (1,-2000) [0|255] \"\" XXX\n\nBO_ 118 RPM_RELATED: 8 XXX\n SG_ CTR : 7|8@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_2 : 19|12@0+ (1,0) [0|4095] \"\" XXX\n\nBO_ 514 ENGINE_DATA: 8 XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|127] \"\" XXX\n SG_ RPM : 7|16@0+ (0.25,0) [0|8500] \"rpm\" XXX\n SG_ SPEED : 23|16@0+ (0.01,0) [0|32767] \"kph\" XXX\n SG_ PEDAL_GAS : 39|12@0+ (1,0) [0|255] \"%\" XXX\n\nBO_ 357 PEDALS: 8 XXX\n SG_ NEW_SIGNAL_6 : 31|4@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 8|3@1+ (1,0) [0|7] \"\" XXX\n SG_ ACC_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_OFF : 2|1@1+ (1,0) [0|15] \"\" XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|15] \"\" XXX\n SG_ STANDSTILL : 26|1@0+ (1,0) [0|16777215] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NO_BRAKE : 6|1@0+ (1,0) [0|7] \"\" XXX\n SG_ BRAKE_ON_2 : 7|1@1+ (1,0) [0|255] \"\" XXX\n SG_ NO_BRAKE_2 : 15|1@0+ (1,0) [0|7] \"\" XXX\n SG_ GEAR : 48|5@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 533 WHEEL_SPEEDS: 8 XXX\n SG_ FL : 7|16@0+ (0.01,-100) [0|16383] \"kph\" XXX\n SG_ FR : 23|16@0+ (0.01,-100) [0|65535] \"kph\" XXX\n SG_ RL : 39|16@0+ (0.01,-100) [0|15] \"kph\" XXX\n SG_ RR : 55|16@0+ (0.01,-100) [0|65535] \"kph\" XXX\n\nBO_ 134 STEER2: 8 XXX\n SG_ CTR : 22|4@0+ (1,0) [0|7] \"\" XXX\n SG_ NEW_SIGNAL_4 : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CTR_2 : 28|3@1+ (1,0) [0|7] \"\" XXX\n SG_ STEER_ANGLE_ROUGH : 26|11@0+ (1,-1000) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_5 : 18|3@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_ANGLE : 7|16@0+ (0.1,-1600) [-500|500] \"deg\" XXX\n SG_ NEW_SIGNAL_1 : 63|2@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_3 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 47|8@0+ (1,0) [0|7] \"\" XXX\n\nBO_ 576 STEER_TORQUE: 8 XXX\n SG_ NEW_SIGNAL_1 : 23|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SENSOR1 : 39|8@0+ (1,-128) [0|127] \"\" XXX\n SG_ STEER_TORQUE_MOTOR : 46|15@0- (0.1,0) [-3000|3000] \"tbd\" XXX\n SG_ NEW_SIGNAL_2 : 62|4@0+ (1,0) [0|31] \"\" XXX\n SG_ NEW_SIGNAL_4 : 15|8@0+ (1,0) [0|127] \"\" XXX\n SG_ STEER_TORQUE_SENSOR : 7|8@0+ (1,-127) [-85|85] \"\" XXX\n\nBO_ 577 STEER_RATE: 8 XXX\n SG_ STEER_ANGLE_RATE : 23|16@0+ (0.25,-8192) [0|1] \"deg/s\" XXX\n SG_ CTR : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKAS_REQUEST : 3|12@0+ (1,-2048) [0|15] \"\" XXX\n SG_ LKAS_EFFECTIVE : 39|12@0+ (1,-2048) [0|255] \"\" XXX\n SG_ HANDS_OFF_5_SECONDS : 51|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_BLOCK : 50|1@1+ (1,0) [0|3] \"\" XXX\n SG_ LKAS_TRACK_STATE : 52|1@0+ (1,0) [0|3] \"\" XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 582 CAM_LANEMAYBE: 8 XXX\n SG_ NEW_SIGNAL_4 : 40|8@1+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_1 : 31|16@0- (1,0) [0|65535] \"\" XXX\n SG_ NEW_SIGNAL_2 : 55|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ CTR : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_3 : 15|16@0+ (1,0) [0|65535] \"\" XXX\n\nBO_ 541 CAM_EMPTY: 8 XXX\n\nBO_ 605 CAM_PEDESTRIAN: 8 XXX\n SG_ CTR : 17|4@0+ (1,0) [0|255] \"\" XXX\n SG_ AEB_NOT_ENGAGED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PED_WARNING : 9|1@0+ (1,0) [0|255] \"\" XXX\n SG_ PED_BRAKE : 3|3@0+ (1,0) [0|7] \"\" XXX\n SG_ RST_CTR : 23|6@0+ (1,0) [0|63] \"\" XXX\n SG_ S1 : 29|4@0+ (1,0) [0|31] \"\" XXX\n SG_ BRAKE_WARNING : 25|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 578 CAM_LANETRACK: 8 XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ZERO : 53|6@0+ (1,0) [0|63] \"\" XXX\n SG_ CTR : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LINE2 : 9|10@0+ (1,-686) [0|255] \"\" XXX\n SG_ LANE_CURVE : 31|8@0+ (1,-127) [0|255] \"\" XXX\n SG_ SIG1 : 39|8@0+ (1,-128) [0|255] \"\" XXX\n SG_ SIG2 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SIG3 : 55|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LINE1 : 3|10@0+ (1,-686) [0|1] \"\" XXX\n\nBO_ 579 CAM_LKAS: 8 XXX\n SG_ CTR : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ERR_BIT_1 : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|15] \"\" XXX\n SG_ LINE_NOT_VISIBLE : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT_1 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDW : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_REQUEST : 3|12@0+ (1,-2048) [0|2048] \"\" XXX\n SG_ ERR_BIT_2 : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ANGLE_ENABLED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEERING_ANGLE : 33|12@0+ (1,-2048) [-2048|2047] \"\" XXX\n\nBO_ 580 CAM_DISTANCE: 8 XXX\n SG_ S1 : 0|8@1+ (1,0) [0|127] \"\" XXX\n SG_ S2 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ S3 : 16|8@1+ (1,0) [0|3] \"\" XXX\n SG_ S4 : 24|8@1+ (1,0) [0|31] \"\" XXX\n SG_ S5 : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ DISTANCE : 47|8@0+ (1,0) [0|65535] \"\" XXX\n SG_ S6 : 55|16@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 581 CAM_IDK3: 8 XXX\n SG_ S1 : 0|8@1+ (1,0) [0|15] \"\" XXX\n SG_ S2 : 8|6@1+ (1,0) [0|255] \"\" XXX\n SG_ S3 : 15|2@0+ (1,0) [0|3] \"\" XXX\n SG_ S4 : 16|8@1+ (1,0) [0|15] \"\" XXX\n SG_ S5 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ S6 : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ S7 : 40|8@1+ (1,0) [0|3] \"\" XXX\n SG_ S8 : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ S9 : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 863 CAM_TRAFFIC_SIGNS: 8 XXX\n SG_ NEW_SIGNAL_3 : 55|1@0+ (1,0) [0|127] \"\" XXX\n SG_ FORWARD_COLLISION : 40|8@1+ (1,0) [0|7] \"\" XXX\n SG_ SPEED_SIGN : 4|7@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_2 : 52|5@0+ (1,0) [0|31] \"\" XXX\n SG_ SPEED_SIGN_CAM : 32|1@0+ (1,0) [0|32767] \"\" XXX\n SG_ SPEED_SIGN_ON : 12|1@0+ (1,0) [0|3] \"\" XXX\n SG_ STOP_SIGN : 31|4@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 33|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1157 CAM_SETTINGS: 8 XXX\n SG_ SBS_WARNING_DISTANCE : 25|2@0+ (1,0) [0|127] \"\" XXX\n SG_ SBS_SCBC : 28|2@0+ (1,0) [0|7] \"\" XXX\n SG_ LKAS_ASSIT_TIMING : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_SENSETIVITY : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ILKAS_NTERVENTION_ON2 : 17|1@0+ (1,0) [0|255] \"\" XXX\n SG_ LANEE_DEPARTURE_ALERT : 16|2@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_INERVENTION_ON1 : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT1 : 12|1@0+ (1,0) [0|7] \"\" XXX\n SG_ BIT2 : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT3 : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1160 CAM_Empty3: 8 XXX\n SG_ NEW_SIGNAL_1 : 47|24@0+ (1,0) [0|16777215] \"\" XXX\n\nBO_ 1088 CAM_LANEINFO: 8 XXX\n SG_ BIT3 : 62|1@0+ (1,0) [0|3] \"\" XXX\n SG_ HANDS_ON_STEER_WARN_2 : 59|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HANDS_ON_STEER_WARN : 56|1@0+ (1,0) [0|3] \"\" XXX\n SG_ S1_HBEAM : 54|1@0+ (1,0) [0|31] \"\" XXX\n SG_ S1 : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HANDS_WARN_3_BITS : 51|3@0+ (1,0) [0|7] \"\" XXX\n SG_ ERR_BIT : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NO_ERR_BIT : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT2 : 13|1@0+ (1,0) [0|15] \"\" XXX\n SG_ LANE_LINES : 10|3@0+ (1,0) [0|3] \"\" XXX\n SG_ BIT1 : 6|1@0+ (1,0) [0|65535] \"\" XXX\n SG_ LINE_NOT_VISIBLE : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LINE_VISIBLE : 0|1@0+ (1,0) [0|3] \"\" XXX\n SG_ LDW_WARN_RL : 58|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDW_WARN_LL : 57|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1479 NEW_MSG_470: 8 XXX\n\nBO_ 1456 NEW_MSG_300: 8 XXX\n\nBO_ 1446 NEW_MSG_a600: 8 XXX\n\nBO_ 1416 MSG_18: 8 XXX\n\nBO_ 1086 DOORS: 8 XXX\n SG_ LEFTGATE : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_3 : 53|1@0+ (1,0) [0|255] \"\" XXX\n SG_ KEYFOB_HORN : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ KEYFOB_LOCK : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ KEYFOB_UNLOCK : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CTR1 : 8|4@1+ (1,0) [0|3] \"\" XXX\n SG_ CTR2 : 16|4@1+ (1,0) [0|15] \"\" XXX\n SG_ BR : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BL : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FR : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FL : 37|1@0+ (1,0) [0|255] \"\" XXX\n SG_ DOORS_UNLOCKED : 30|1@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 977 TWO_STATES: 8 XXX\n SG_ NEW_SIGNAL_1 : 50|1@1+ (1,0) [0|7] \"\" XXX\n SG_ NEW_SIGNAL_2 : 56|4@1+ (1,0) [0|7] \"\" XXX\n SG_ NEW_SIGNAL_3 : 28|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 24|4@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_5 : 39|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_6 : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_8 : 51|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1085 MSG_12: 8 XXX\n SG_ NEW_SIGNAL_3 : 36|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 16|8@1+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_2 : 48|8@1+ (1,0) [0|65535] \"\" XXX\n SG_ NEW_SIGNAL_4 : 31|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 24|1@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_6 : 40|3@1+ (1,0) [0|7] \"\" XXX\n\nBO_ 159 MSG_11: 8 XXX\n SG_ NEW_SIGNAL_1 : 50|4@1+ (1,0) [0|15] \"\" XXX\n SG_ INCREASEING : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1278 NEW_MSG_3: 8 XXX\n SG_ NEW_SIGNAL_2 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ MILAGE_MAYBE : 7|16@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1277 NEW_MSG_10: 8 XXX\n SG_ NEW_SIGNAL_3 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ counter : 7|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1275 2017_5: 8 XXX\n SG_ counter : 4|5@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1274 NEW_MSG_12: 8 XXX\n SG_ NEW_SIGNAL_1 : 24|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CTR : 55|4@0+ (1,0) [0|63] \"\" XXX\n SG_ NEW_SIGNAL_2 : 35|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 32|3@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_4 : 48|4@1+ (1,0) [0|7] \"\" XXX\n\nBO_ 1180 last_byte_roughRPM: 8 XXX\n SG_ NEW_SIGNAL_1 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1078 HVAC: 8 XXX\n SG_ NEW_SIGNAL_1 : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_2 : 8|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|1@0+ (1,0) [0|65535] \"\" XXX\n SG_ NEW_SIGNAL_4 : 56|5@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1056 CHECK_AND_TEMP: 8 XXX\n SG_ NEW_SIGNAL_1 : 29|6@0+ (1,0) [0|255] \"\" XXX\n SG_ counter_or_GEAR : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STANDSTILL : 32|1@0+ (1,0) [0|255] \"\" XXX\n SG_ COOLANT_TEMP : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LOW_ENGINE_OIL_PRESSURE : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECK_FUEL_CAP : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHARGING_SYSTEM_MALFUNCTION : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ OUTDOOR_TEMP : 63|8@0+ (0.25,-63) [0|255] \"cel\" XXX\n\nBO_ 1045 TRACTION: 8 XXX\n SG_ NEW_SIGNAL_2 : 20|1@0+ (1,0) [0|3] \"\" XXX\n SG_ CTR2 : 19|4@0+ (1,0) [0|31] \"\" XXX\n SG_ CTR3 : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ IS_MOVING : 12|1@0+ (1,0) [0|3] \"\" XXX\n SG_ CTR1 : 53|6@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_WARNING : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ABS_MALFUNCTION : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ DSC_OFF : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ TCS_DCS_MALFUNCTION : 6|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LOUD_BEEP : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ TPMS_WARNING_DOUBLE_BLINK : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1034 MSG_07: 8 XXX\n SG_ NEW_SIGNAL_1 : 6|3@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_2 : 0|4@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_3 : 15|4@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_4 : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_8 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_9 : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 870 NEW_MSG_16: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 867 NEW_MSG_17: 8 XXX\n SG_ NEW_SIGNAL_1 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 130 STEER: 8 XXX\n SG_ NEW_SIGNAL_5 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 47|4@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 23|16@0+ (0.05,-1600) [500|-500] \"deg\" XXX\n SG_ CHKSUM_MAYBE : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 120 BRAKE: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PRESSURE : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 304 GEAR_RELATED: 8 XXX\n SG_ NEW_SIGNAL_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 865 NEW_MSG_5: 8 XXX\n SG_ SPEED_INVERSE : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 47|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IS_MOVING : 43|3@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_2 : 46|1@0+ (1,0) [0|7] \"\" XXX\n SG_ NEW_SIGNAL_4 : 44|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_8 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_10 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 15|3@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 56|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 836 NEW_MSG_19: 8 XXX\n SG_ CTR : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CTR2 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 832 SEATBELT: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ PASSENGER_SEATBELT : 26|1@1+ (1,0) [0|7] \"\" XXX\n SG_ CTR1 : 15|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CTR2 : 23|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 8|4@1+ (1,0) [0|3] \"\" XXX\n SG_ DRIVER_SEATBELT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 866 NEW_MSG_21: 8 XXX\n SG_ NEW_SIGNAL_2 : 7|8@0+ (1,0) [0|131071] \"\" XXX\n SG_ NEW_SIGNAL_1 : 15|8@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_3 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 27|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 158 MSG_05: 8 XXX\n SG_ NEW_SIGNAL_1 : 23|8@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_2 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 157 CRZ_BTNS: 8 XXX\n SG_ BIT1 : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT2 : 18|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT3 : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_P_INV : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CAN_OFF_INV : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CAN_OFF : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_M_INV : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_M : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_P : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RES_INV : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RES : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DISTANCE_LESS : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DISTANCE_LESS_INV : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DISTANCE_MORE : 6|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DISTANCE_MORE_INV : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MODE_Y : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MODE_X : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MODE_Y_INV : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MODE_X_INV : 31|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CTR : 29|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 154 BLINK_INFO: 8 XXX\n SG_ LEFT_BLINK : 18|1@1+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_BLINK : 19|1@0+ (1,0) [0|255] \"\" XXX\n SG_ REAR_WIPER_ON : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WIPER_LO : 33|1@1+ (1,0) [0|31] \"\" XXX\n SG_ WIPER_HI : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAMS : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HIGH_BEAMS : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LBEAM1 : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LBEAM2 : 50|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LBEAM3 : 60|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 145 TURN_SWITCH: 8 XXX\n SG_ HAZARD : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ TURN_RIGHT_SWITCH : 12|1@0+ (1,0) [0|3] \"\" XXX\n SG_ TURN_LEFT_SWITCH : 13|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 27|4@0+ (1,0) [0|255] \"\" XXX\n SG_ CHKSUM : 39|8@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 80 MSG_04: 8 XXX\n SG_ NEW_SIGNAL_1 : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIGNAL : 24|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 978 MSG_03: 8 XXX\n SG_ NEW_SIGNAL_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_8 : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 1|2@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 607 NEW_MSG_25: 8 XXX\n\nBO_ 1115 MSG_02: 8 XXX\n SG_ NEW_SIGNAL_2 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 47|16@0+ (1,0) [0|65535] \"\" XXX\n SG_ NEW_SIGNAL_3 : 63|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 2|3@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1067 NEW_MSG_27: 8 XXX\n SG_ NEW_SIGNAL_2 : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_1 : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_5 : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_3 : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_6 : 11|1@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_7 : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_8 : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_9 : 8|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 358 NEW_MSG_28: 8 XXX\n\nBO_ 608 NEW_MSG_29: 8 XXX\n SG_ NEW_SIGNAL_1 : 8|5@1+ (1,0) [0|7] \"\" XXX\n\nBO_ 606 SPEED_TBD: 8 XXX\n SG_ SPEED_TBD : 7|12@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 23|12@0- (1,0) [0|65535] \"\" XXX\n\nBO_ 552 GEAR: 8 XXX\n SG_ NEW_SIGNAL_3 : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_5 : 26|3@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 31|5@0+ (1,0) [0|31] \"\" XXX\n SG_ NEW_SIGNAL_7 : 39|1@0+ (1,0) [0|255] \"\" XXX\n SG_ MORE_GEAR : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ GEAR : 2|3@0+ (1,0) [0|7] \"\" XXX\n SG_ GEAR_BOX : 36|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 543 CRZ_EVENTS: 8 XXX\n SG_ NEW_SIGNAL_3 : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_1 : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_5 : 47|4@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_6 : 6|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_8 : 0|1@0+ (1,0) [0|31] \"\" XXX\n SG_ NEW_SIGNAL_9 : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_10 : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_12 : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_13 : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_18 : 12|1@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_19 : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_20 : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_21 : 23|1@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_24 : 31|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL_PRESSED : 32|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CRZ_STARTED : 18|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PLUS_ONE_CRZ : 17|1@0+ (1,0) [0|255] \"\" XXX\n SG_ PLUS_ONE_CRZ_2 : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_MAYBE : 22|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NONACC_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE_CAR_MOVING : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NONACC_RELATED : 11|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CAS_CMD_MAYBE : 30|7@0- (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 43|4@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 542 NEW_MSG_33: 8 XXX\n SG_ CTR : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CTR2 : 56|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 868 NEW_MSG_34: 8 XXX\n SG_ CTR : 59|4@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 869 NEW_MSG_35: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|16@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 39|16@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 55|2@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 50|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CTR : 59|4@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1114 NEW_MSG_4: 8 XXX\n\nBO_ 535 CURVE_CTRS: 8 XXX\n SG_ CTR_A_1 : 4|3@0+ (1,0) [0|31] \"\" XXX\n SG_ CTR_A_2 : 7|3@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR_B_1 : 12|3@0+ (1,0) [0|7] \"\" XXX\n SG_ CTR_B_2 : 15|3@0+ (1,0) [0|7] \"\" XXX\n SG_ CTR_C_1 : 20|3@0+ (1,0) [0|7] \"\" XXX\n SG_ CTR_C_2 : 23|3@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR_D_2 : 31|3@0+ (1,0) [0|7] \"\" XXX\n SG_ CTR_D_1 : 28|3@0+ (1,0) [0|7] \"\" XXX\n SG_ SPEED : 39|16@0+ (0.01,0) [0|7] \"kph\" XXX\n SG_ CTR : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHK_MAYBE : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_2 : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_6 : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_8 : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_MAYBE : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NO_SEATBELT_MAYBE : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 9|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 540 CRZ_CTRL: 8 XXX\n SG_ NEW_SIGNAL_3 : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_4 : 8|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_6 : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 18|3@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_9 : 31|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_10 : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_GAS_MAYBE : 23|1@0+ (1,0) [0|31] \"\" XXX\n SG_ ACC_GAS_MAYBE2 : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRZ_ACTIVE : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HANDS_OFF_STEERING : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HANDS_ON_STEER_WARN : 59|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_1 : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_2 : 45|3@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_8 : 0|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 539 CRZ_INFO: 8 XXX\n SG_ NEW_SIGNAL_1 : 17|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_5 : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_7 : 47|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 37|1@0+ (1,0) [0|255] \"\" XXX\n SG_ ACC_ACTIVE : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_CMD : 31|10@0- (1,0) [0|1] \"\" XXX\n SG_ CHKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 121 EPB: 8 XXX\n SG_ NEW_SIGNAL_1 : 4|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_3 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 25|2@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_8 : 41|2@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_9 : 47|1@0+ (1,0) [0|63] \"\" XXX\n SG_ NEW_SIGNAL_10 : 46|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_11 : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ EPB_ACTIVE : 29|1@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 1070 2017_1: 8 XXX\n\nBO_ 1183 2017_2: 8 XXX\n\nBO_ 1243 2017_3: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|64@0+ (1,0) [0|18446744073709552000] \"\" XXX\n\nBO_ 1269 MSG_2017_4: 8 XXX\n SG_ NEW_SIGNAL_1 : 55|16@0+ (1,0) [0|18446744073709552000] \"\" XXX\n\nBO_ 1178 2017_6: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|64@0+ (1,0) [0|18446744073709552000] \"\" XXX\n\nBO_ 1179 2017_7: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|64@0+ (1,0) [0|18446744073709552000] \"\" XXX\n\nBO_ 1435 2017_8: 8 XXX\n\nBO_ 253 GAS: 8 XXX\n SG_ NEW_SIGNAL_1 : 16|1@0+ (1,0) [0|65535] \"\" XXX\n SG_ CTR : 23|4@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_2 : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CRZ_NOT_ACTIVE : 61|1@0+ (1,0) [0|255] \"\" XXX\n SG_ GAS_CMD : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 359 MORE_GAS: 8 XXX\n SG_ NEW_SIGNAL_1 : 15|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR : 31|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 36|5@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 38|1@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_5 : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_6 : 47|4@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 512 NEW_MSG_30: 8 XXX\n SG_ NEW_SIGNAL_1 : 6|7@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_3 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 23|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 22|7@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_6 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_7 : 39|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_8 : 38|7@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_9 : 40|4@1+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_10 : 47|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CTR : 51|3@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_11 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 515 MSG_01: 8 XXX\n SG_ CTR : 39|4@0+ (1,0) [0|65535] \"\" XXX\n SG_ CHKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ START1 : 6|1@0+ (1,0) [0|1] \"\" XXX\n SG_ START2 : 28|5@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 529 NEW_MSG_36: 8 XXX\n SG_ NEW_SIGNAL_1 : 22|5@0+ (1,0) [0|65535] \"\" XXX\n SG_ NEW_SIGNAL_2 : 31|8@0+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_3 : 32|4@1+ (1,0) [0|3] \"\" XXX\n SG_ CTR : 39|4@0+ (1,0) [0|255] \"\" XXX\n SG_ CTR_2 : 47|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 40|4@1+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_5 : 53|1@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1242 NEW_MSG_37: 8 XXX\n\nBO_ 1266 MSG_09: 8 XXX\n SG_ NEW_SIGNAL_1 : 20|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 19|4@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_3 : 31|1@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 976 MSG_15: 8 XXX\n SG_ NEW_SIGNAL_1 : 55|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 61|6@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 155 MSG_14: 8 XXX\n\nBO_ 1267 MSG_10: 8 XXX\n SG_ NEW_SIGNAL_1 : 40|1@0+ (1,0) [0|16777215] \"\" XXX\n SG_ NEW_SIGNAL_2 : 42|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 305 NEW_MSG_6: 8 XXX\n SG_ NEW_SIGNAL_1 : 8|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_3 : 10|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1238 TEMPERATURE: 8 XXX\n SG_ TEMPERATURE_MAYBE : 47|8@0+ (1,0) [0|4294967295] \"\" XXX\n\nBO_ 1087 NEW_MSG_1: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1143 BSM: 8 XXX\n SG_ BSM_OFF : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BS_3 : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BS1 : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BS3 : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BS4 : 39|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BS_SIDE : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ IS_MOVING : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BS_BEHIND : 46|2@1+ (1,0) [0|16777215] \"\" XXX\n SG_ RIGHT_BS1 : 14|1@0+ (1,0) [0|63] \"\" XXX\n SG_ RIGHT_BS_DISTANCE : 35|3@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_1 : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REAR_CT_ALERT : 23|5@0+ (1,0) [0|63] \"\" XXX\n\nBO_ 1361 KEY_POSITION: 8 XXX\n\nBO_ 1283 KEY_POSITION2: 8 XXX\n\nBO_ 628 MSG_06: 8 XXX\n\nBO_ 1154 MSG_08: 8 XXX\n\nBO_ 1139 MSG_13: 8 XXX\n\nBO_ 1270 MSG_16: 8 XXX\n\nBO_ 1272 MSG_17: 8 XXX\n\nBO_ 1425 MSG_19: 8 XXX\n\nBO_ 70 MOB1: 8 XXX\n SG_ NEW_SIGNAL_1 : 1|3@1+ (1,0) [0|15] \"\" XXX\n SG_ NEW_SIGNAL_2 : 14|6@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_3 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 30|6@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 38|6@0+ (1,0) [0|7] \"\" XXX\n\nBO_ 64 MOB2: 8 XXX\n SG_ NEW_SIGNAL_1 : 7|2@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_2 : 10|3@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_3 : 16|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_4 : 24|1@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_5 : 35|4@0+ (1,0) [0|255] \"\" XXX\n SG_ NEW_SIGNAL_6 : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ NEW_SIGNAL_7 : 13|3@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_8 : 15|2@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_9 : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NEW_SIGNAL_10 : 31|6@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_11 : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1171 MOB3: 8 XXX\n\nBO_ 1248 MOB4: 8 XXX\n\n\n\n\nCM_ SG_ 357 GEAR \"13P, 26R, 13N, 24D\";\nCM_ SG_ 605 PED_BRAKE \"3: no brake, 4: brake\";\nCM_ SG_ 605 BRAKE_WARNING \"Flashing brake warning and audible alert for potential forward collision\";\nCM_ SG_ 579 STEERING_ANGLE \"steering angle aligns with 0.022 factor and -45.06 offset\";\nCM_ SG_ 863 SPEED_SIGN \"speed limit in MPH\";\nCM_ SG_ 863 SPEED_SIGN_CAM \"1: The speed limit is recognized by the camera. 0: speed limit is map based or is not available\";\nCM_ SG_ 863 STOP_SIGN \"value 9 when stop sign is active\";\nCM_ SG_ 1157 SBS_WARNING_DISTANCE \"1 far, 2 mid, 3 near\";\nCM_ SG_ 1157 SBS_SCBC \"1 off, 2 on\";\nCM_ SG_ 1157 LKAS_ASSIT_TIMING \"1 at, 0 before\";\nCM_ SG_ 1157 LKAS_SENSETIVITY \"0 low, 1 high\";\nCM_ SG_ 1157 LANEE_DEPARTURE_ALERT \"1 off, 2 on\";\nCM_ SG_ 1157 WARNING \"1 Rare, 0 often\";\nCM_ SG_ 1088 LANE_LINES \"0 LKAS disabled, 1 no lines, 2 two lines, 3 left line, 4 right line\";\nCM_ SG_ 1045 ABS_MALFUNCTION \"off: 0, solid: 1, slow blink: 2, fast blink: 3\";\nCM_ SG_ 157 CAN_OFF \"Disengage Cruise if enabled, if already disabled  TURN it OFF \";\nCM_ SG_ 552 MORE_GEAR \"\";\nCM_ SG_ 552 GEAR \"0 Shifting, 1 P, 2 R, 3 N, 4 D\";\nCM_ SG_ 552 GEAR_BOX \"0 P, 14 R, 1 though 6 D for speeds, 15 Shift\";\nCM_ SG_ 540 HANDS_ON_STEER_WARN \"0 no warning, b warning\";\nCM_ SG_ 1143 REAR_CT_ALERT \"Rear Cross Traffic Alert\";\nVAL_ 552 GEAR 1 \"P\" 2 \"R\" 3 \"N\" 4 \"D\" ;\n"
  },
  {
    "path": "opendbc/nissan_leaf_2018.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\n\nBO_ 2 STEER_ANGLE_SENSOR: 5 XXX\n SG_ STEER_ANGLE_RATE : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X07 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 0|16@1- (-0.1,0) [0|65535] \"\" XXX\n SG_ COUNTER : 32|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 42 SEATBELT: 8 XXX\n SG_ SEATBELT_DRIVER_LATCHED : 27|1@1+ (1,0) [0|3] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 26|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown2 : 31|4@0+ (1,0) [0|15] \"\" XXX\n SG_ unknown3 : 24|2@1+ (1,0) [0|3] \"\" XXX\n SG_ unknown1 : 7|24@0+ (1,0) [0|16777215] \"\" XXX\n SG_ unknown4 : 39|16@0+ (1,0) [0|65535] \"\" XXX\n\nBO_ 361 LKAS: 8 XXX\n SG_ MAX_TORQUE : 39|8@0+ (0.01,0) [0|255] \"Nm\" XXX\n SG_ SET_0x80 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LKA_ACTIVE : 52|1@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_0x80_2 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DESIRED_ANGLE : 7|18@0+ (-0.01,1310) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 389 STEER_TORQUE_SENSOR: 8 XXX\n SG_ LKAS_ACTIVE : 37|1@0+ (1,0) [0|3] \"\" XXX\n SG_ STEER_TORQUE_LKAS : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 23|18@0+ (-0.01,1310) [0|262143] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 7|12@0+ (-0.01,20.47) [0|4095] \"Nm\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|127] \"\" XXX\n\nBO_ 460 BRAKE_PEDAL: 8 XXX\n SG_ BRAKE_PEDAL : 7|8@0+ (1,0) [0|256] \"\" XXX\n\nBO_ 569 CRUISE_THROTTLE: 8 XXX\n SG_ GAS_PEDAL_INVERTED : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ GAS_PEDAL : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CRUISE_AVAILABLE : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unsure1 : 23|6@0+ (1,0) [0|63] \"\" XXX\n SG_ unsure2 : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unsure3 : 31|2@0+ (1,0) [0|3] \"\" XXX\n SG_ NO_BUTTON_PRESSED : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RES_BUTTON : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_BUTTON : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FOLLOW_DISTANCE_BUTTON : 26|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CANCEL_BUTTON : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_BUTTON : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unsure4 : 39|6@0+ (1,0) [0|63] \"\" XXX\n SG_ COUNTER : 32|2@1+ (1,0) [0|3] \"\" XXX\n SG_ unsure5 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ unsure6 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ unsure7 : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 640 CANCEL_MSG: 8 XXX\n  SG_ CANCEL_SEATBELT : 1|1@0+ (1,0) [0|1] \"\" XXX\n  SG_ NEW_SIGNAL_1 : 7|6@0+ (1,0) [0|63] \"\" XXX\n  SG_ NEW_SIGNAL_2 : 0|1@0+ (1,0) [0|1] \"\" XXX\n  SG_ NEW_SIGNAL_3 : 15|56@0+ (1,0) [0|72057594037927940] \"\" XXX\n\nBO_ 644 WHEEL_SPEEDS_FRONT: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n\nBO_ 645 WHEEL_SPEEDS_REAR: 8 XXX\n SG_ WHEEL_SPEED_RR : 7|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n SG_ WHEEL_SPEED_RL : 23|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n\nBO_ 689 PROPILOT_HUD: 8 XXX\n SG_ LARGE_WARNING_FLASHING : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_ERROR_FLASHING1 : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_ERROR_FLASHING2 : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_LANE_YELLOW_FLASH : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_LANE_YELLOW_FLASH : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_CAR : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_CAR_ERROR : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_ERROR : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_ERROR_FLASHING : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_LANE_GREEN : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_LANE_GREEN : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_ERROR_FLASHING3 : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_ERROR_FLASHING : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SAFETY_SHIELD_ACTIVE : 44|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LARGE_STEERING_WHEEL_ICON : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LANE_GREEN_FLASH : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_LANE_GREEN_FLASH : 63|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FOLLOW_DISTANCE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ AUDIBLE_TONE : 47|3@0+ (1,0) [0|8] \"\" XXX\n SG_ SPEED_SET_ICON : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SMALL_STEERING_WHEEL_ICON : 42|3@0+ (1,0) [0|7] \"\" XXX\n SG_ SET_SPEED : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ unknown02 : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown05 : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown08 : 8|7@0+ (1,0) [0|63] \"\" XXX\n SG_ unknown26 : 26|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown28 : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown31 : 31|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown43 : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown55 : 55|8@0+ (1,0) [0|63] \"\" XXX\n SG_ unknown59 : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 783 CRUISE_STATE: 3 XXX\n SG_ CRUISE_ENABLED : 3|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 852 ESP: 8 XXX\n SG_ ESP_DISABLED : 38|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 853 HUD_SETTINGS: 8 XXX\n SG_ SPEED_MPH : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 856 LIGHTS: 8 XXX\n SG_ LEFT_BLINKER : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BLINKER : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1057 GEARBOX: 3 XXX\n SG_ GEAR_SHIFTER : 5|3@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1228 PROPILOT_HUD_INFO_MSG: 8 XXX\n SG_ NA_HIGH_ACCEL_TEMP : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_NA_HIGH_CABIN_TEMP : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_MALFUNCTION : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_MALFUNCTION : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_MALFUNCTION : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_NA_CLEAN_REAR_CAMERA : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NA_POOR_ROAD_CONDITIONS : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CURRENTLY_UNAVAILABLE : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SAFETY_SHIELD_OFF : 18|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_COLLISION_NA_FRONT_RADAR_OBSTRUCTION : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PEDAL_MISSAPPLICATION_SYSTEM_ACTIVATED : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_IMPACT_NA_RADAR_OBSTRUCTION : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING_DO_NOT_ENTER : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_IMPACT_SYSTEM_OFF : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_IMPACT_MALFUNCTION : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_COLLISION_MALFUNCTION : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_MALFUNCTION2 : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_MALFUNCTION2 : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_MALFUNCTION2 : 39|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_NA_MSGS : 42|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BOTTOM_MSG : 45|3@0+ (1,0) [0|7] \"\" XXX\n SG_ HANDS_ON_WHEEL_WARNING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING_STEP_ON_BRAKE_NOW : 51|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_NA_FRONT_CAMERA_OBSTRUCTED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_NA_HIGH_CABIN_TEMP : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING_PROPILOT_MALFUNCTION : 54|1@0+ (1,0) [0|3] \"\" XXX\n SG_ ACC_UNAVAILABLE_HIGH_CABIN_TEMP : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_NA_FRONT_CAMERA_IMPARED : 63|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown07 : 7|7@0+ (1,0) [0|127] \"\" XXX\n SG_ unknown10 : 10|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown15 : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown23 : 23|3@0+ (1,0) [0|7] \"\" XXX\n SG_ unknown19 : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown31 : 31|6@0+ (1,0) [0|63] \"\" XXX\n SG_ unknown32 : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown46 : 46|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown50 : 50|3@0+ (1,0) [0|7] \"\" XXX\n SG_ unknown55 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown61 : 61|6@0+ (1,0) [0|63] \"\" XXX\n\nBO_ 1549 DOORS_LIGHTS: 8 XXX\n SG_ DOOR_OPEN_FL : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 6|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1227 LKAS_SETTINGS: 8 XXX\n SG_ LKAS_ENABLED : 51|1@0+ (1,0) [0|1] \"\" XXX\n\nVAL_ 1057 GEAR_SHIFTER 7 \"B\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 1228 PROPILOT_NA_MSGS 0 \"NO_MSG\" 1 \"NA_FRONT_CAMERA_IMPARED\" 2 \"STEERING_ASSIST_ON_STANDBY\" 3 \"NA_PARKING_ASSIST_ENABLED\" 4 \"STEER_ASSIST_CURRENTLY_NA\" 5 \"NA_BAD_WEATHER\" 6 \"NA_PARK_BRAKE_ON\" 7 \"NA_SEATBELT_NOT_FASTENED\" ;\nVAL_ 1228 BOTTOM_MSG 0 \"OK_STEER_ASSIST_SETTINGS\" 1 \"NO_MSG\" 2 \"PRESS_SET_TO_SET_SPEED\" 3 \"PRESS_RES_SET_TO_CHANGE_SPEED\" 4 \"PRESS_RES_TO_RESTART\" 5 \"NO_MSG\" 6 \"CRUISE_NOT_AVAIL\" 7 \"NO_MSG\" ;\nVAL_ 689 FOLLOW_DISTANCE 0 \"NO_FOLLOW_DISTANCE\" 1 \"FOLLOW_DISTANCE_1\" 2 \"FOLLOW_DISTANCE_2\" 3 \"FOLLOW_DISANCE_3\" ;\nVAL_ 689 AUDIBLE_TONE 0 \"NO_TONE\" 1 \"CONT\" 2 \"FAST_BEEP_CONT\" 3 \"TRIPLE_FAST_BEEP_CONT\" 4 \"SLOW_BEEP_CONT\" 5 \"QUAD_SLOW_BEEP_CONT\" 6 \"SINGLE_BEEP_ONCE\" 7 \"DOUBLE_BEEP_ONCE\" ;\nVAL_ 689 SMALL_STEERING_WHEEL_ICON 0 \"NO_ICON\" 1 \"GRAY_ICON\" 2 \"GRAY_ICON_FLASHING\" 3 \"GREEN_ICON\" 4 \"GREEN_ICON_FLASHING\" 5 \"RED_ICON\" 6 \"RED_ICON_FLASHING\" 7 \"YELLOW_ICON\" ;\nVAL_ 689 LARGE_STEERING_WHEEL_ICON 0 \"NO_STEERINGWHEEL\" 1 \"GRAY_STEERINGWHEEL\" 2 \"GREEN_STEERINGWHEEL\" 3 \"GREEN_STEERINGWHEEL_FLASHING\" ;\n"
  },
  {
    "path": "opendbc/nissan_x_trail_2017.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\n\nBO_ 2 STEER_ANGLE_SENSOR: 5 XXX\n SG_ STEER_ANGLE_RATE : 16|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X07 : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 0|16@1- (-0.1,0) [0|65535] \"\" XXX\n SG_ COUNTER : 32|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 348 GAS_PEDAL: 8 XXX\n SG_ GAS_PEDAL_RAW : 26|11@0+ (1,0) [0|2047] \"\" XXX\n SG_ GAS_PEDAL : 47|10@0+ (1,0) [0|1023] \"\" XXX\n\nBO_ 361 LKAS: 8 XXX\n SG_ MAX_TORQUE : 39|8@0+ (0.01,0) [0|255] \"Nm\" XXX\n SG_ SET_0x80 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LKA_ACTIVE : 52|1@0+ (1,0) [0|15] \"\" XXX\n SG_ SET_0x80_2 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DESIRED_ANGLE : 7|18@0+ (-0.01,1310) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 389 STEER_TORQUE_SENSOR: 8 XXX\n SG_ LKAS_ACTIVE : 37|1@0+ (1,0) [0|3] \"\" XXX\n SG_ STEER_TORQUE_LKAS : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 23|18@0+ (-0.01,1310) [0|262143] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 7|12@0+ (-0.01,20.47) [0|4095] \"Nm\" XXX\n SG_ COUNTER : 51|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|127] \"\" XXX\n\nBO_ 438 PRO_PILOT: 8 XXX\n SG_ COUNTER : 55|4@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X03 : 33|2@0+ (1,0) [0|15] \"\" XXX\n SG_ CRUISE_ACTIVATED : 38|1@0+ (1,0) [0|3] \"\" XXX\n SG_ CRUISE_ON : 36|1@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_STATUS : 51|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 523 CRUISE_THROTTLE: 6 XXX\n SG_ PROPILOT_BUTTON : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CANCEL_BUTTON : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL_INVERTED : 37|10@0+ (1,0) [0|1023] \"\" XXX\n SG_ SET_BUTTON : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RES_BUTTON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FOLLOW_DISTANCE_BUTTON : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NO_BUTTON_PRESSED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 31|10@0+ (1,0) [0|255] \"\" XXX\n SG_ USER_BRAKE_PRESSED : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ USER_BRAKE_PRESSED_INVERTED : 22|1@0+ (1,0) [0|3] \"\" XXX\n SG_ NEW_SIGNAL_2 : 23|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PRESSED_INVERTED : 20|1@0+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 17|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unsure1 : 7|10@0+ (1,0) [0|1023] \"\" XXX\n SG_ unsure2 : 43|4@0+ (1,0) [0|1] \"\" XXX\n SG_ unsure3 : 19|2@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 645 WHEEL_SPEEDS_REAR: 8 XXX\n SG_ WHEEL_SPEED_RR : 7|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n SG_ WHEEL_SPEED_RL : 23|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n\nBO_ 665 ESP: 8 XXX\n SG_ ESP_DISABLED : 24|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 666 WHEEL_SPEEDS_FRONT: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.005,0) [0|65535] \"KPH\" XXX\n\nBO_ 689 PROPILOT_HUD: 8 XXX\n SG_ LARGE_WARNING_FLASHING : 9|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_ERROR_FLASHING1 : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_ERROR_FLASHING2 : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_LANE_YELLOW_FLASH : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_LANE_YELLOW_FLASH : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_CAR : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEAD_CAR_ERROR : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_ERROR : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_ERROR_FLASHING : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_LANE_GREEN : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_LANE_GREEN : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_ERROR_FLASHING3 : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_ERROR_FLASHING : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SAFETY_SHIELD_ACTIVE : 44|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LARGE_STEERING_WHEEL_ICON : 61|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LANE_GREEN_FLASH : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_LANE_GREEN_FLASH : 63|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FOLLOW_DISTANCE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ AUDIBLE_TONE : 47|3@0+ (1,0) [0|8] \"\" XXX\n SG_ SPEED_SET_ICON : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SMALL_STEERING_WHEEL_ICON : 42|3@0+ (1,0) [0|7] \"\" XXX\n SG_ SET_SPEED : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ unknown02 : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown05 : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown08 : 8|7@0+ (1,0) [0|63] \"\" XXX\n SG_ unknown26 : 26|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown28 : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown31 : 31|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown43 : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown55 : 55|8@0+ (1,0) [0|63] \"\" XXX\n SG_ unknown59 : 59|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 768 STEER_TORQUE_SENSOR2: 2 XXX\n SG_ STEERING_TORQUE : 6|7@0+ (1,0) [0|127] \"\" XXX\n SG_ STEERING_PRESSED : 15|1@0+ (-1,1) [0|7] \"\" XXX\n\nBO_ 783 CRUISE_STATE: 3 XXX\n SG_ CRUISE_ENABLED : 3|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1055 GEARBOX: 2 XXX\n SG_ SPORTS_MODE : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR_SHIFTER : 5|3@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1107 LIGHTS: 8 XXX\n SG_ RIGHT_BLINKER : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BLINKER : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HEADLIGHTS : 5|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1108 DOORS_LIGHTS: 8 XXX\n SG_ DOOR_CLOSED_RR : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 41|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_CLOSED_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_CLOSED_FL : 44|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_CLOSED_FR : 46|1@0+ (1,0) [0|3] \"\" XXX\n SG_ DOOR_OPEN_FR : 47|1@0+ (1,0) [0|3] \"\" XXX\n SG_ BOOT_OPEN : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHT : 54|1@0+ (1,0) [0|1] \"\" XXX\n SG_ USER_BRAKE_PRESSED : 23|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1228 PROPILOT_HUD_INFO_MSG: 8 XXX\n SG_ NA_HIGH_ACCEL_TEMP : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_NA_HIGH_CABIN_TEMP : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_MALFUNCTION : 11|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_MALFUNCTION : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_MALFUNCTION : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_NA_CLEAN_REAR_CAMERA : 14|1@0+ (1,0) [0|1] \"\" XXX\n SG_ NA_POOR_ROAD_CONDITIONS : 16|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CURRENTLY_UNAVAILABLE : 17|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SAFETY_SHIELD_OFF : 18|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_COLLISION_NA_FRONT_RADAR_OBSTRUCTION : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PEDAL_MISSAPPLICATION_SYSTEM_ACTIVATED : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_IMPACT_NA_RADAR_OBSTRUCTION : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING_DO_NOT_ENTER : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_IMPACT_SYSTEM_OFF : 34|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_IMPACT_MALFUNCTION : 35|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_COLLISION_MALFUNCTION : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SIDE_RADAR_MALFUNCTION2 : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_MALFUNCTION2 : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_RADAR_MALFUNCTION2 : 39|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_NA_MSGS : 42|3@0+ (1,0) [0|7] \"\" XXX\n SG_ BOTTOM_MSG : 45|3@0+ (1,0) [0|7] \"\" XXX\n SG_ HANDS_ON_WHEEL_WARNING : 47|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING_STEP_ON_BRAKE_NOW : 51|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_NA_FRONT_CAMERA_OBSTRUCTED : 52|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PROPILOT_NA_HIGH_CABIN_TEMP : 53|1@0+ (1,0) [0|1] \"\" XXX\n SG_ WARNING_PROPILOT_MALFUNCTION : 54|1@0+ (1,0) [0|3] \"\" XXX\n SG_ ACC_UNAVAILABLE_HIGH_CABIN_TEMP : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACC_NA_FRONT_CAMERA_IMPARED : 63|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown07 : 7|7@0+ (1,0) [0|127] \"\" XXX\n SG_ unknown10 : 10|2@0+ (1,0) [0|3] \"\" XXX\n SG_ unknown15 : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown23 : 23|3@0+ (1,0) [0|7] \"\" XXX\n SG_ unknown19 : 19|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown31 : 31|6@0+ (1,0) [0|63] \"\" XXX\n SG_ unknown32 : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown46 : 46|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown50 : 50|3@0+ (1,0) [0|7] \"\" XXX\n SG_ unknown55 : 55|1@0+ (1,0) [0|1] \"\" XXX\n SG_ unknown61 : 61|6@0+ (1,0) [0|63] \"\" XXX\n\nBO_ 1227 LKAS_SETTINGS: 8 XXX\n SG_ LKAS_ENABLED : 51|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1273 HUD: 7 XXX\n SG_ SEATBELT_DRIVER_LATCHED : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SPEED_MPH : 5|1@0+ (1,0) [0|1] \"\" XXX\n\nVAL_ 1055 GEAR_SHIFTER 6 \"L\" 4 \"D\" 3 \"N\" 2 \"R\" 1 \"P\" ;\nVAL_ 1228 PROPILOT_NA_MSGS 0 \"NO_MSG\" 1 \"NA_FRONT_CAMERA_IMPARED\" 2 \"STEERING_ASSIST_ON_STANDBY\" 3 \"NA_PARKING_ASSIST_ENABLED\" 4 \"STEER_ASSIST_CURRENTLY_NA\" 5 \"NA_BAD_WEATHER\" 6 \"NA_PARK_BRAKE_ON\" 7 \"NA_SEATBELT_NOT_FASTENED\" ;\nVAL_ 1228 BOTTOM_MSG 0 \"OK_STEER_ASSIST_SETTINGS\" 1 \"NO_MSG\" 2 \"PRESS_SET_TO_SET_SPEED\" 3 \"PRESS_RES_SET_TO_CHANGE_SPEED\" 4 \"PRESS_RES_TO_RESTART\" 5 \"NO_MSG\" 6 \"CRUISE_NOT_AVAIL\" 7 \"NO_MSG\" ;\nVAL_ 689 FOLLOW_DISTANCE 0 \"NO_FOLLOW_DISTANCE\" 1 \"FOLLOW_DISTANCE_1\" 2 \"FOLLOW_DISTANCE_2\" 3 \"FOLLOW_DISANCE_3\" ;\nVAL_ 689 AUDIBLE_TONE 0 \"NO_TONE\" 1 \"CONT\" 2 \"FAST_BEEP_CONT\" 3 \"TRIPLE_FAST_BEEP_CONT\" 4 \"SLOW_BEEP_CONT\" 5 \"QUAD_SLOW_BEEP_CONT\" 6 \"SINGLE_BEEP_ONCE\" 7 \"DOUBLE_BEEP_ONCE\" ;\nVAL_ 689 SMALL_STEERING_WHEEL_ICON 0 \"NO_ICON\" 1 \"GRAY_ICON\" 2 \"GRAY_ICON_FLASHING\" 3 \"GREEN_ICON\" 4 \"GREEN_ICON_FLASHING\" 5 \"RED_ICON\" 6 \"RED_ICON_FLASHING\" 7 \"YELLOW_ICON\" ;\nVAL_ 689 LARGE_STEERING_WHEEL_ICON 0 \"NO_STEERINGWHEEL\" 1 \"GRAY_STEERINGWHEEL\" 2 \"GREEN_STEERINGWHEEL\" 3 \"GREEN_STEERINGWHEEL_FLASHING\" ;\n"
  },
  {
    "path": "opendbc/subaru_forester_2017_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _subaru_preglobal_2015.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX X\n\n\nBO_ 2 Steering: 8 XXX\n SG_ Steering_Angle : 7|16@0- (0.1,0) [-500|500] \"degree\" XXX\n SG_ Counter : 27|3@0+ (1,0) [0|7] \"\" XXX\n SG_ Checksum : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 208 G_Sensor: 8 XXX\n SG_ Steering_Angle : 0|16@1- (-0.1,0) [-500|500] \"\" XXX\n SG_ Lateral : 16|16@1- (-0.0035,1) [-255|255] \"\" XXX\n SG_ Longitudinal : 48|16@1- (-0.00035,0) [-255|255] \"\" XXX\n\nBO_ 209 Brake_Pedal: 8 XXX\n SG_ Speed : 0|16@1+ (0.05625,0) [0|255] \"KPH\" XXX\n SG_ Brake_Pedal : 16|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 210 Brake_2: 8 XXX\n SG_ Brake_Light : 35|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Related : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Right_Brake : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Left_Brake : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 211 Brake_Type: 8 XXX\n SG_ Brake_Light : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Speed_Counter : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Cruise_On : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal_On : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 48|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 212 Wheel_Speeds: 8 XXX\n SG_ FL : 0|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ FR : 16|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ RL : 32|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ RR : 48|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n\nBO_ 320 Throttle: 8 XXX\n SG_ Throttle_Pedal : 0|8@1+ (0.392157,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|2@1+ (1,0) [0|7] \"\" XXX\n SG_ Not_Full_Throttle : 14|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Engine_RPM : 16|14@1+ (1,0) [0|32767] \"\" XXX\n SG_ Off_Throttle : 30|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Throttle_Cruise : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Combo : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Body : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Off_Throttle_2 : 56|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal4 : 57|7@1+ (1,0) [0|127] \"\" XXX\n\nBO_ 321 Engine: 8 XXX\n SG_ Engine_Torque : 0|15@1+ (1,0) [0|255] \"\" XXX\n SG_ Engine_Stop : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Wheel_Torque : 16|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Engine_RPM : 32|12@1+ (1,0) [0|8191] \"\" XXX\n\nBO_ 324 CruiseControl: 8 XXX\n SG_ OnOffButton : 2|1@1+ (1,0) [0|1] \"\" XXX\n SG_ SET_BUTTON : 3|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RES_BUTTON : 4|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Button : 13|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_On : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal_On : 51|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 328 Transmission: 8 XXX\n SG_ Manual_Gear : 4|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Transmission_Engine : 16|15@1+ (1,0) [0|65535] \"\" XXX\n SG_ Gear : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Gear_2 : 52|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Paddle_Shift : 60|2@1+ (1,0) [0|3] \"\" XXX\n\nBO_ 329 CVT_Ratio: 8 XXX\n\nBO_ 336 Brake_Pressure: 8 XXX\n SG_ Brake_Pressure_Right : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Pressure_Left : 8|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 338 Stalk: 8 XXX\n SG_ Counter : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Brake_Light : 52|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Runlights : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Headlights : 59|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Highbeam : 60|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Wiper : 62|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 352 ES_Brake: 8 XXX\n SG_ Brake_Pressure : 0|16@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Light : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_On : 22|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 48|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 ES_CruiseThrottle: 8 XXX\n SG_ Throttle_Cruise : 0|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal1 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Cruise_Activated : 16|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 17|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Brake_On : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Distance_Swap : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Standstill : 22|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Close_Distance : 24|8@1+ (0.0196,0) [0|255] \"m\" XXX\n SG_ Signal4 : 32|9@1+ (1,0) [0|255] \"\" XXX\n SG_ Standstill_2 : 41|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal5 : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 44|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal6 : 47|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Button : 48|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal7 : 51|5@1+ (1,0) [0|31] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 354 ES_RPM: 8 XXX\n SG_ Brake : 8|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 9|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RPM : 16|16@1+ (1,0) [0|65535] \"\" XXX\n SG_ Checksum : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 48|3@1+ (1,0) [0|7] \"\" XXX\n\nBO_ 356 ES_LKAS: 8 XXX\n SG_ Counter : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ LKAS_Command : 8|13@1- (-1,0) [-4096|4096] \"\" XXX\n SG_ LKAS_Active : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 359 ES_LDW: 8 XXX\n SG_ All_depart_2015 : 0|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Right_Line_2017 : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Left_Line_2017 : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1All_Depart : 28|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig2All_Depart : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Inactive_2017 : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Active : 37|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1Right_Depart : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1Right_Depart_Front : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig2Right_Depart : 50|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Left_Depart_Front : 51|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig3All_Depart : 52|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 604 BSD_RCTA: 8 XXX\n SG_ Counter : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ State : 5|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_ADJACENT : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_ADJACENT : 33|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_APPROACHING : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_APPROACHING : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_RCTA : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_RCTA : 47|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 642 Dashlights: 8 XXX\n SG_ Counter : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ SEATBELT_FL : 40|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BLINKER : 44|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BLINKER : 45|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 880 Steering_Torque_2: 8 XXX\n SG_ Steering_Voltage_Flat : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Steer_Torque_Sensor : 29|11@1- (-1,0) [-1000|1000] \"\" XXX\n SG_ Counter : 40|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 BodyInfo: 8 XXX\n SG_ DOOR_OPEN_FR : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 26|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_Hatch : 28|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 864 Engine_Temp: 8 XXX\n SG_ Oil_Temp : 16|8@1+ (1,-40) [0|255] \"\" XXX\n SG_ Coolant_Temp : 24|8@1+ (1,-40) [0|255] \"\" XXX\n SG_ Cruise_Activated : 45|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Saved_Speed : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 866 Fuel: 8 XXX\n\nBO_ 977 Dash_State2: 8 XXX\n SG_ UNITS : 15|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 1745 Dash_State: 8 XXX\n SG_ Units : 15|1@1+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 320 Off_Throttle_2 \"Less sensitive\";\nCM_ SG_ 320 Throttle_Body \"Throttle related\";\nCM_ SG_ 328 Gear \"15 = P, 14 = R, 0 = N, 1-6=gear\";\nCM_ SG_ 328 Gear_2 \"15 = P, 14 = R, 0 = N, 1-6=gear\";\nCM_ SG_ 353 Cruise_Button \"1 = main, 2 = set shallow, 3 = set deep, 4 = resume shallow, 5 resume deep\";\nCM_ SG_ 354 RPM \"20hz version of Transmission_Engine under Transmission\";\nCM_ SG_ 359 Sig1Right_Depart \"right depart, hill steep and seatbelt disengage\";\nCM_ SG_ 359 LKAS_Inactive_2017 \"1 when not steering, 0 when lkas steering\";\nCM_ SG_ 359 Sig1Right_Depart_Front \"object in front, right depart, hill steep and seatbelt disengage alert \";\nCM_ SG_ 359 Left_Depart_Front \"warning after acceleration into car in front and left depart\";\nCM_ SG_ 359 Sig1All_Depart \"Left and right depart\";\nCM_ SG_ 359 Sig2All_Depart \"Left and right depart\";\nCM_ SG_ 359 All_depart_2015 \"always 1 on 2017\";\nCM_ SG_ 604 R_APPROACHING \"Faster car approaching in far right lane\";\nCM_ SG_ 604 L_APPROACHING \"Faster car approaching in far left lane\";\nCM_ SG_ 604 R_RCTA \"Rear cross traffic alert, only when in R gear\";\nCM_ SG_ 604 L_RCTA \"Rear cross traffic alert, only when in R gear\";\nCM_ SG_ 642 Counter \"Affected by signals\";\nCM_ SG_ 642 SEATBELT_FL \"Driver seatbelt\";\nCM_ SG_ 880 Steering_Voltage_Flat \"receives later than 371\";\nCM_ SG_ 977 UNITS \"0 = Metric, 1 = Imperial\";\n\nVAL_ 328 Gear 0 \"N\" 1 \"D\" 2 \"D\" 3 \"D\" 4 \"D\" 5 \"D\" 6 \"D\" 14 \"R\" 15 \"P\";\n\nCM_ \"subaru_forester_2017.dbc starts here\";\n\n\nBO_ 355 ES_DashStatus: 8 XXX\n SG_ Not_Ready_Startup : 4|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Cruise_On : 16|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Set_Speed : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 40|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Cruise_Activated : 54|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 881 Steering_Torque: 8 XXX\n SG_ Steering_Motor_Flat : 0|10@1+ (32,0) [0|1000] \"\" XXX\n SG_ Steer_Torque_Output : 16|11@1- (-32,0) [-1000|1000] \"\" XXX\n SG_ Steer_Error_1 : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Steer_Torque_Sensor : 29|11@1- (-1,0) [-1000|1000] \"\" XXX\n SG_ Steering_Angle : 40|16@1- (-0.033,0) [-600|600] \"\" XXX\n"
  },
  {
    "path": "opendbc/subaru_global_2017_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _subaru_global.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX X\n\n\nBO_ 2 Steering: 8 XXX\n SG_ Steering_Angle : 7|16@0- (0.1,0) [0|65535] \"\" XXX\n SG_ Counter : 25|3@1+ (1,0) [0|7] \"\" XXX\n SG_ CHECKSUM : 32|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 64 Throttle: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Engine_RPM : 16|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal2 : 28|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Throttle_Pedal : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Cruise : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Combo : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Signal3 : 56|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Off_Accel : 60|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 316 Brake_Status: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|46@1+ (1,0) [0|1] \"\" XXX\n SG_ ES_Brake : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 59|3@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake : 62|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 63|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 326 Cruise_Buttons: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|30@1+ (1,0) [0|1073741823] \"\" XXX\n SG_ Main : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Set : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Resume : 44|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 45|19@1+ (1,0) [0|524287] \"\" XXX\n\nBO_ 315 G_Sensor: 8 XXX\n SG_ Lateral : 48|8@1- (-0.1,0) [0|255] \"m/s2\" XXX\n SG_ Longitudinal : 56|8@1- (-0.1,0) [0|255] \"m/s2\" XXX\n\nBO_ 314 Wheel_Speeds: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ FR : 12|13@1+ (0.057,0) [0|255] \"kph\" XXX\n SG_ RR : 25|13@1+ (0.057,0) [0|255] \"kph\" XXX\n SG_ FL : 51|13@1+ (0.057,0) [0|255] \"kph\" XXX\n SG_ RL : 38|13@1+ (0.057,0) [0|255] \"kph\" XXX\n\nBO_ 280 STOP_START: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ State : 63|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 281 Steering_Torque: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Steer_Error_1 : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ Steer_Torque_Sensor : 16|11@1- (-1,0) [-1000|1000] \"\" XXX\n SG_ Steer_Error_2 : 28|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Steer_Warning : 29|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Steering_Angle : 32|16@1- (-0.0217,0) [-600|600] \"\" X\n SG_ Steer_Torque_Output : 48|11@1- (-1,0) [-1000|1000] \"\" XXX\n\nBO_ 312 Brake_Pressure_L_R: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Brake_1 : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_2 : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 313 Brake_Pedal: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Speed : 16|12@1+ (0.05625,0) [0|255] \"kph\" XXX\n SG_ Signal2 : 28|6@1+ (1,0) [0|63] \"\" XXX\n SG_ Brake_Lights : 34|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 35|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal : 36|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal4 : 48|16@1+ (1,0) [0|65535] \"\" XXX\n\nBO_ 290 ES_LKAS: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ SET_1 : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Output : 16|13@1- (-1,0) [-8191|8191] \"\" XXX\n SG_ LKAS_Request : 29|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 544 ES_Brake: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Brake_Pressure : 16|16@1+ (1,0) [0|65535] \"\" XXX\n SG_ Signal2 : 32|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Cruise_Brake_Lights : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Brake_Fault : 37|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Brake_Active : 38|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 39|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 40|24@1+ (1,0) [0|16777215] \"\" XXX\n\nBO_ 577 Cruise_Status: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Cruise_On : 54|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 55|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Active : 57|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 552 BSD_RCTA: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ R_ADJACENT : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_ADJACENT : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_APPROACHING : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_APPROACHING : 59|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 912 Dashlights: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ UNITS : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ ICY_ROAD : 32|2@1+ (1,0) [0|3] \"\" XXX\n SG_ SEATBELT_FL : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BLINKER : 50|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BLINKER : 51|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 940 BodyInfo: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ DOOR_OPEN_FL : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 33|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 34|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 35|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_TRUNK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE : 54|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DASH_BTN_LIGHTS : 56|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOWBEAM : 57|1@1+ (1,0) [0|1] \"\" XXX\n SG_ HIGHBEAM : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ FOG_LIGHTS : 60|1@1+ (1,0) [0|1] \"\" XXX\n SG_ WIPERS : 62|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 801 ES_DashStatus: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ PCB_Off : 12|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LDW_Off : 13|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal1 : 14|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Cruise_State_Msg : 16|4@1+ (1,0) [0|15] \"\" XXX\n SG_ LKAS_State_Msg : 20|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal2 : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Soft_Disable : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Status_Msg : 25|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Signal3 : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Distance : 28|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal4 : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Conventional_Cruise : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal5 : 33|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Cruise_Disengaged : 35|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal6 : 37|3@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Set_Speed : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Cruise_Fault : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_On : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Display_Own_Car : 50|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Lights : 51|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Car_Follow : 52|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal7 : 53|3@1+ (1,0) [0|1] \"\" XXX\n SG_ Far_Distance : 56|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Cruise_State : 60|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 802 ES_LKAS_State: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ LKAS_Alert_Msg : 12|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal1 : 15|2@1+ (1,0) [0|3] \"\" XXX\n SG_ LKAS_ACTIVE : 17|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Dash_State : 18|2@1+ (1,0) [0|2] \"\" XXX\n SG_ Signal2 : 20|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Backward_Speed_Limit_Menu : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Left_Line_Enable : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Left_Line_Light_Blink : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Right_Line_Enable : 26|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Right_Line_Light_Blink : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Left_Line_Visible : 28|2@1+ (1,0) [0|3] \"\" XXX\n SG_ LKAS_Right_Line_Visible : 30|2@1+ (1,0) [0|3] \"\" XXX\n SG_ LKAS_Alert : 32|5@1+ (1,0) [0|31] \"\" XXX\n SG_ Signal3 : 37|27@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 722 AC_State: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ AC_Mode : 37|3@1+ (1,0) [0|1] \"\" XXX\n SG_ AC_ON : 24|2@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 1677 Dash_State: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Units : 29|3@1+ (1,0) [0|7] \"\" XXX\n\nCM_ SG_ 64 Throttle_Combo \"Throttle Cruise + Pedal\";\nCM_ SG_ 313 Brake_Lights \"Driver or Cruise Brake on\";\nCM_ SG_ 544 Cruise_Brake_Lights \"1 = switch on brake lights\";\nCM_ SG_ 801 PCB_Off \"Pre-Collision Braking off\";\nCM_ SG_ 801 Brake_Lights \"Driver or Cruise brake on\";\nCM_ SG_ 801 Cruise_State \"0 = Normal, 1 = Hold+User Brake, 2 = Ready, 3 = Hold\";\nCM_ SG_ 801 Far_Distance \"1=0-5m, 2=5-10m, 3=10-15m, 4=15-20m, 5=20-25m, 6=25-30m, 7=30-35m, 8=35-40m, 9=40-45m, 10=45-50m, 11=50-55m, 12=55-60m, 13=60-65m, 14=65-70m, 15=75m+\";\nCM_ SG_ 801 LKAS_State_Msg \"1 = LKAS_Off_Sharp_Curve, 2 = Keep_Hands_On_Steering_wheel_disabled, 3 = LKAS_Off, 4 = LKAS_Off_Too_Slow, 5 = LKAS_Off_Too_Fast\";\nCM_ SG_ 801 Cruise_State_Msg \"1 = Cruise_Off_Steep_Slope, 2 = Cruise_lvl1_eco, 3 = Cruise_lvl2_comfort, 4 = Cruise_off_empty_reason, 5 = Cruise_off, 6 = Cruise_Unable_to_set, 7 = Cruise_Unable_to_set_brakes_applied, 8 = Eyesight_not_ready, 9 = Cruise_lvl3_standard, 10 = Cruise_lvl4_dynamic, 11 = Cruise_Unable_to_set_steep_slope\";\nCM_ SG_ 801 Cruise_Soft_Disable \"Eyesight soft disable (eg direct sunlight)\";\nCM_ SG_ 801 Cruise_Status_Msg \"1 = Disabled_Bad_Visibility, 2 = Disabled_Check_Manual\";\nCM_ SG_ 802 LKAS_ACTIVE \"Turns on the full LKAS dash display\";\nCM_ SG_ 802 LKAS_Alert_Msg \"1 = Keep_Hands_On_Wheel, 6 = Pre_Collision_Braking, 7 = Keep_Hands_On_Wheel_Off\";\nCM_ SG_ 802 LKAS_Alert \"1 = FCW_Cont_Beep, 2 = FCW_Repeated_Beep, 3 = Throttle_Management_Activated_Warning, 4 = Throttle_Management_Activated_Alert, 5 = Pre_Collision_Activated_Alert, 8 = Traffic_Light_Ahead, 9 = Apply_Brake_to_Hold Position, 11 = LDW_Right, 12 = LDW_Left, 13 = Stay_Alert, 14 = Lead_Vehicle_Start_Alert, 18 = Keep_Hands_On_Steering_Alert, 24 = Audio_Beep, 25 = Audio_Lead_Car_Change, 26 = Audio_ACC_Disengaged, 27 = Audio_LKAS_disabled, 28 = Audio_Ding_Ding, 30 = Audio_Repeated_Beep\";\nCM_ SG_ 802 LKAS_Left_Line_Visible \"0 = Off, 1 = White, 2 = Green, 3 = Orange\";\nCM_ SG_ 802 LKAS_Dash_State \"0 = Off, 1 = Ready, 2 = Active\";\nCM_ SG_ 802 LKAS_Right_Line_Visible \"0 = Off, 1 = White, 2 = Green, 3 = Orange\";\nCM_ SG_ 912 UNITS \"0 = Metric, 1 = Imperial\";\nCM_ SG_ 912 ICY_ROAD \"1 = DASHLIGHT ON, 2 = WARNING, 3 = OFF\";\n\nCM_ \"subaru_global_2017.dbc starts here\";\n\n\nBO_ 72 Transmission: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Gear : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ RPM : 40|16@1+ (1,0) [0|65535] \"\" XXX\n\nBO_ 73 CVT: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ CVT_Gear : 24|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 545 ES_Distance: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Cruise_Fault : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Throttle : 16|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal2 : 28|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Car_Follow : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 33|3@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Brake_Active : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Distance_Swap : 37|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_EPB : 38|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal4 : 39|1@0+ (1,0) [0|1] \"\" XXX\n SG_ Close_Distance : 40|8@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal5 : 48|8@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Cancel : 56|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Set : 57|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Resume : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal6 : 59|5@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 546 ES_Status: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|3@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_RPM : 16|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal2 : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Lights : 30|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Hold : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 32|32@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 576 CruiseControl: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|28@1+ (1,0) [0|268435455] \"\" XXX\n SG_ Cruise_On : 40|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 41|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 42|22@1+ (1,0) [0|4194303] \"\" XXX\n\nCM_ SG_ 545 Cruise_Throttle \"RPM-like output signal\";\nCM_ SG_ 545 Cruise_EPB \"1 = Electric Parking Brake set\";\nCM_ SG_ 545 Distance_Swap \"Switch from Close to Far distance\";\nCM_ SG_ 546 Cruise_RPM \"ES RPM output for ECM and TCM\";\nCM_ SG_ 546 Signal3 \"0 when cruise_activated = 1\";\nVAL_ 72 Gear 2 \"N\" 3 \"R\" 4 \"P\" 121 \"D\" 137 \"1\" 145 \"2\" 153 \"3\" 161 \"4\" 169 \"5\" 177 \"6\";\n"
  },
  {
    "path": "opendbc/subaru_outback_2015_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _subaru_preglobal_2015.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX X\n\n\nBO_ 2 Steering: 8 XXX\n SG_ Steering_Angle : 7|16@0- (0.1,0) [-500|500] \"degree\" XXX\n SG_ Counter : 27|3@0+ (1,0) [0|7] \"\" XXX\n SG_ Checksum : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 208 G_Sensor: 8 XXX\n SG_ Steering_Angle : 0|16@1- (-0.1,0) [-500|500] \"\" XXX\n SG_ Lateral : 16|16@1- (-0.0035,1) [-255|255] \"\" XXX\n SG_ Longitudinal : 48|16@1- (-0.00035,0) [-255|255] \"\" XXX\n\nBO_ 209 Brake_Pedal: 8 XXX\n SG_ Speed : 0|16@1+ (0.05625,0) [0|255] \"KPH\" XXX\n SG_ Brake_Pedal : 16|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 210 Brake_2: 8 XXX\n SG_ Brake_Light : 35|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Related : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Right_Brake : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Left_Brake : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 211 Brake_Type: 8 XXX\n SG_ Brake_Light : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Speed_Counter : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Cruise_On : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal_On : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 48|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 212 Wheel_Speeds: 8 XXX\n SG_ FL : 0|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ FR : 16|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ RL : 32|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ RR : 48|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n\nBO_ 320 Throttle: 8 XXX\n SG_ Throttle_Pedal : 0|8@1+ (0.392157,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|2@1+ (1,0) [0|7] \"\" XXX\n SG_ Not_Full_Throttle : 14|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Engine_RPM : 16|14@1+ (1,0) [0|32767] \"\" XXX\n SG_ Off_Throttle : 30|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Throttle_Cruise : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Combo : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Body : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Off_Throttle_2 : 56|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal4 : 57|7@1+ (1,0) [0|127] \"\" XXX\n\nBO_ 321 Engine: 8 XXX\n SG_ Engine_Torque : 0|15@1+ (1,0) [0|255] \"\" XXX\n SG_ Engine_Stop : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Wheel_Torque : 16|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Engine_RPM : 32|12@1+ (1,0) [0|8191] \"\" XXX\n\nBO_ 324 CruiseControl: 8 XXX\n SG_ OnOffButton : 2|1@1+ (1,0) [0|1] \"\" XXX\n SG_ SET_BUTTON : 3|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RES_BUTTON : 4|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Button : 13|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_On : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal_On : 51|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 328 Transmission: 8 XXX\n SG_ Manual_Gear : 4|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Transmission_Engine : 16|15@1+ (1,0) [0|65535] \"\" XXX\n SG_ Gear : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Gear_2 : 52|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Paddle_Shift : 60|2@1+ (1,0) [0|3] \"\" XXX\n\nBO_ 329 CVT_Ratio: 8 XXX\n\nBO_ 336 Brake_Pressure: 8 XXX\n SG_ Brake_Pressure_Right : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Pressure_Left : 8|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 338 Stalk: 8 XXX\n SG_ Counter : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Brake_Light : 52|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Runlights : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Headlights : 59|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Highbeam : 60|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Wiper : 62|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 352 ES_Brake: 8 XXX\n SG_ Brake_Pressure : 0|16@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Light : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_On : 22|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 48|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 ES_CruiseThrottle: 8 XXX\n SG_ Throttle_Cruise : 0|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal1 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Cruise_Activated : 16|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 17|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Brake_On : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Distance_Swap : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Standstill : 22|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Close_Distance : 24|8@1+ (0.0196,0) [0|255] \"m\" XXX\n SG_ Signal4 : 32|9@1+ (1,0) [0|255] \"\" XXX\n SG_ Standstill_2 : 41|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal5 : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 44|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal6 : 47|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Button : 48|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal7 : 51|5@1+ (1,0) [0|31] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 354 ES_RPM: 8 XXX\n SG_ Brake : 8|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 9|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RPM : 16|16@1+ (1,0) [0|65535] \"\" XXX\n SG_ Checksum : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 48|3@1+ (1,0) [0|7] \"\" XXX\n\nBO_ 356 ES_LKAS: 8 XXX\n SG_ Counter : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ LKAS_Command : 8|13@1- (-1,0) [-4096|4096] \"\" XXX\n SG_ LKAS_Active : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 359 ES_LDW: 8 XXX\n SG_ All_depart_2015 : 0|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Right_Line_2017 : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Left_Line_2017 : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1All_Depart : 28|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig2All_Depart : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Inactive_2017 : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Active : 37|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1Right_Depart : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1Right_Depart_Front : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig2Right_Depart : 50|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Left_Depart_Front : 51|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig3All_Depart : 52|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 604 BSD_RCTA: 8 XXX\n SG_ Counter : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ State : 5|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_ADJACENT : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_ADJACENT : 33|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_APPROACHING : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_APPROACHING : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_RCTA : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_RCTA : 47|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 642 Dashlights: 8 XXX\n SG_ Counter : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ SEATBELT_FL : 40|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BLINKER : 44|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BLINKER : 45|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 880 Steering_Torque_2: 8 XXX\n SG_ Steering_Voltage_Flat : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Steer_Torque_Sensor : 29|11@1- (-1,0) [-1000|1000] \"\" XXX\n SG_ Counter : 40|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 BodyInfo: 8 XXX\n SG_ DOOR_OPEN_FR : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 26|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_Hatch : 28|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 864 Engine_Temp: 8 XXX\n SG_ Oil_Temp : 16|8@1+ (1,-40) [0|255] \"\" XXX\n SG_ Coolant_Temp : 24|8@1+ (1,-40) [0|255] \"\" XXX\n SG_ Cruise_Activated : 45|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Saved_Speed : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 866 Fuel: 8 XXX\n\nBO_ 977 Dash_State2: 8 XXX\n SG_ UNITS : 15|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 1745 Dash_State: 8 XXX\n SG_ Units : 15|1@1+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 320 Off_Throttle_2 \"Less sensitive\";\nCM_ SG_ 320 Throttle_Body \"Throttle related\";\nCM_ SG_ 328 Gear \"15 = P, 14 = R, 0 = N, 1-6=gear\";\nCM_ SG_ 328 Gear_2 \"15 = P, 14 = R, 0 = N, 1-6=gear\";\nCM_ SG_ 353 Cruise_Button \"1 = main, 2 = set shallow, 3 = set deep, 4 = resume shallow, 5 resume deep\";\nCM_ SG_ 354 RPM \"20hz version of Transmission_Engine under Transmission\";\nCM_ SG_ 359 Sig1Right_Depart \"right depart, hill steep and seatbelt disengage\";\nCM_ SG_ 359 LKAS_Inactive_2017 \"1 when not steering, 0 when lkas steering\";\nCM_ SG_ 359 Sig1Right_Depart_Front \"object in front, right depart, hill steep and seatbelt disengage alert \";\nCM_ SG_ 359 Left_Depart_Front \"warning after acceleration into car in front and left depart\";\nCM_ SG_ 359 Sig1All_Depart \"Left and right depart\";\nCM_ SG_ 359 Sig2All_Depart \"Left and right depart\";\nCM_ SG_ 359 All_depart_2015 \"always 1 on 2017\";\nCM_ SG_ 604 R_APPROACHING \"Faster car approaching in far right lane\";\nCM_ SG_ 604 L_APPROACHING \"Faster car approaching in far left lane\";\nCM_ SG_ 604 R_RCTA \"Rear cross traffic alert, only when in R gear\";\nCM_ SG_ 604 L_RCTA \"Rear cross traffic alert, only when in R gear\";\nCM_ SG_ 642 Counter \"Affected by signals\";\nCM_ SG_ 642 SEATBELT_FL \"Driver seatbelt\";\nCM_ SG_ 880 Steering_Voltage_Flat \"receives later than 371\";\nCM_ SG_ 977 UNITS \"0 = Metric, 1 = Imperial\";\n\nVAL_ 328 Gear 0 \"N\" 1 \"D\" 2 \"D\" 3 \"D\" 4 \"D\" 5 \"D\" 6 \"D\" 14 \"R\" 15 \"P\";\n\nCM_ \"subaru_outback_2015.dbc starts here\";\n\n\nBO_ 358 ES_DashStatus: 8 XXX\n SG_ Not_Ready_Startup : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Seatbelt_Disengage : 12|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Disengage_Alert : 14|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Cruise_On : 16|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 17|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal1 : 18|1@1+ (1,0) [0|1] \"\" XXX\n SG_ WHEELS_MOVING_2015 : 19|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Driver_Input : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Distance : 21|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Cruise_Set_Speed : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Cruise_Fault : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_On_2 : 34|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 37|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Steep_Hill_Disengage : 44|1@1+ (1,0) [0|3] \"\" XXX\n SG_ Car_Follow : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Far_Distance : 48|4@1+ (5,0) [0|15] \"m\" XXX\n\nBO_ 881 Steering_Torque: 8 XXX\n SG_ Steering_Motor_Flat : 0|10@1+ (32,0) [0|1000] \"\" XXX\n SG_ Steer_Torque_Output : 16|11@1- (-32,0) [-1000|1000] \"\" XXX\n SG_ Steer_Error_1 : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Steer_Torque_Sensor : 29|11@1- (1,0) [-1000|1000] \"\" XXX\n SG_ Steering_Angle : 40|16@1- (-0.033,0) [-600|600] \"\" XXX\n\nCM_ SG_ 358 Disengage_Alert \"seatbelt and steep hill disengage\";\nCM_ SG_ 358 Cruise_Fault \"No engagement until restart\";\nCM_ SG_ 358 Car_Follow \"lead car detected\";\n"
  },
  {
    "path": "opendbc/subaru_outback_2019_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _subaru_preglobal_2015.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX X\n\n\nBO_ 2 Steering: 8 XXX\n SG_ Steering_Angle : 7|16@0- (0.1,0) [-500|500] \"degree\" XXX\n SG_ Counter : 27|3@0+ (1,0) [0|7] \"\" XXX\n SG_ Checksum : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 208 G_Sensor: 8 XXX\n SG_ Steering_Angle : 0|16@1- (-0.1,0) [-500|500] \"\" XXX\n SG_ Lateral : 16|16@1- (-0.0035,1) [-255|255] \"\" XXX\n SG_ Longitudinal : 48|16@1- (-0.00035,0) [-255|255] \"\" XXX\n\nBO_ 209 Brake_Pedal: 8 XXX\n SG_ Speed : 0|16@1+ (0.05625,0) [0|255] \"KPH\" XXX\n SG_ Brake_Pedal : 16|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 210 Brake_2: 8 XXX\n SG_ Brake_Light : 35|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Related : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Right_Brake : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Left_Brake : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 211 Brake_Type: 8 XXX\n SG_ Brake_Light : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Speed_Counter : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Cruise_On : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal_On : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 48|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 212 Wheel_Speeds: 8 XXX\n SG_ FL : 0|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ FR : 16|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ RL : 32|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n SG_ RR : 48|16@1+ (0.0592,0) [0|255] \"KPH\" XXX\n\nBO_ 320 Throttle: 8 XXX\n SG_ Throttle_Pedal : 0|8@1+ (0.392157,0) [0|255] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Signal1 : 12|2@1+ (1,0) [0|7] \"\" XXX\n SG_ Not_Full_Throttle : 14|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Engine_RPM : 16|14@1+ (1,0) [0|32767] \"\" XXX\n SG_ Off_Throttle : 30|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Throttle_Cruise : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Combo : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Throttle_Body : 48|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Off_Throttle_2 : 56|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal4 : 57|7@1+ (1,0) [0|127] \"\" XXX\n\nBO_ 321 Engine: 8 XXX\n SG_ Engine_Torque : 0|15@1+ (1,0) [0|255] \"\" XXX\n SG_ Engine_Stop : 15|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Wheel_Torque : 16|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Engine_RPM : 32|12@1+ (1,0) [0|8191] \"\" XXX\n\nBO_ 324 CruiseControl: 8 XXX\n SG_ OnOffButton : 2|1@1+ (1,0) [0|1] \"\" XXX\n SG_ SET_BUTTON : 3|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RES_BUTTON : 4|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Button : 13|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_On : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_Pedal_On : 51|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 328 Transmission: 8 XXX\n SG_ Manual_Gear : 4|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Counter : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Transmission_Engine : 16|15@1+ (1,0) [0|65535] \"\" XXX\n SG_ Gear : 48|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Gear_2 : 52|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Paddle_Shift : 60|2@1+ (1,0) [0|3] \"\" XXX\n\nBO_ 329 CVT_Ratio: 8 XXX\n\nBO_ 336 Brake_Pressure: 8 XXX\n SG_ Brake_Pressure_Right : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Pressure_Left : 8|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 338 Stalk: 8 XXX\n SG_ Counter : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Brake_Light : 52|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Runlights : 58|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Headlights : 59|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Highbeam : 60|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Wiper : 62|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 352 ES_Brake: 8 XXX\n SG_ Brake_Pressure : 0|16@1+ (1,0) [0|255] \"\" XXX\n SG_ Brake_Light : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Brake_On : 22|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 48|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 ES_CruiseThrottle: 8 XXX\n SG_ Throttle_Cruise : 0|12@1+ (1,0) [0|4095] \"\" XXX\n SG_ Signal1 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Cruise_Activated : 16|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal2 : 17|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Brake_On : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Distance_Swap : 21|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Standstill : 22|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal3 : 23|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Close_Distance : 24|8@1+ (0.0196,0) [0|255] \"m\" XXX\n SG_ Signal4 : 32|9@1+ (1,0) [0|255] \"\" XXX\n SG_ Standstill_2 : 41|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Fault : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal5 : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 44|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal6 : 47|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Button : 48|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Signal7 : 51|5@1+ (1,0) [0|31] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 354 ES_RPM: 8 XXX\n SG_ Brake : 8|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 9|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RPM : 16|16@1+ (1,0) [0|65535] \"\" XXX\n SG_ Checksum : 32|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Counter : 48|3@1+ (1,0) [0|7] \"\" XXX\n\nBO_ 356 ES_LKAS: 8 XXX\n SG_ Counter : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ LKAS_Command : 8|13@1- (-1,0) [-4096|4096] \"\" XXX\n SG_ LKAS_Active : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Checksum : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 359 ES_LDW: 8 XXX\n SG_ All_depart_2015 : 0|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Right_Line_2017 : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Left_Line_2017 : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1All_Depart : 28|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig2All_Depart : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Inactive_2017 : 36|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LKAS_Active : 37|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1Right_Depart : 48|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig1Right_Depart_Front : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig2Right_Depart : 50|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Left_Depart_Front : 51|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Sig3All_Depart : 52|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 604 BSD_RCTA: 8 XXX\n SG_ Counter : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ State : 5|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_ADJACENT : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_ADJACENT : 33|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_APPROACHING : 42|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_APPROACHING : 43|1@1+ (1,0) [0|1] \"\" XXX\n SG_ R_RCTA : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ L_RCTA : 47|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 642 Dashlights: 8 XXX\n SG_ Counter : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ SEATBELT_FL : 40|1@1+ (1,0) [0|1] \"\" XXX\n SG_ LEFT_BLINKER : 44|1@1+ (1,0) [0|1] \"\" XXX\n SG_ RIGHT_BLINKER : 45|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 880 Steering_Torque_2: 8 XXX\n SG_ Steering_Voltage_Flat : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Steer_Torque_Sensor : 29|11@1- (-1,0) [-1000|1000] \"\" XXX\n SG_ Counter : 40|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 884 BodyInfo: 8 XXX\n SG_ DOOR_OPEN_FR : 24|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 25|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 26|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_Hatch : 28|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 864 Engine_Temp: 8 XXX\n SG_ Oil_Temp : 16|8@1+ (1,-40) [0|255] \"\" XXX\n SG_ Coolant_Temp : 24|8@1+ (1,-40) [0|255] \"\" XXX\n SG_ Cruise_Activated : 45|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Saved_Speed : 56|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 866 Fuel: 8 XXX\n\nBO_ 977 Dash_State2: 8 XXX\n SG_ UNITS : 15|1@1+ (1,0) [0|1] \"\" XXX\n\nBO_ 1745 Dash_State: 8 XXX\n SG_ Units : 15|1@1+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 320 Off_Throttle_2 \"Less sensitive\";\nCM_ SG_ 320 Throttle_Body \"Throttle related\";\nCM_ SG_ 328 Gear \"15 = P, 14 = R, 0 = N, 1-6=gear\";\nCM_ SG_ 328 Gear_2 \"15 = P, 14 = R, 0 = N, 1-6=gear\";\nCM_ SG_ 353 Cruise_Button \"1 = main, 2 = set shallow, 3 = set deep, 4 = resume shallow, 5 resume deep\";\nCM_ SG_ 354 RPM \"20hz version of Transmission_Engine under Transmission\";\nCM_ SG_ 359 Sig1Right_Depart \"right depart, hill steep and seatbelt disengage\";\nCM_ SG_ 359 LKAS_Inactive_2017 \"1 when not steering, 0 when lkas steering\";\nCM_ SG_ 359 Sig1Right_Depart_Front \"object in front, right depart, hill steep and seatbelt disengage alert \";\nCM_ SG_ 359 Left_Depart_Front \"warning after acceleration into car in front and left depart\";\nCM_ SG_ 359 Sig1All_Depart \"Left and right depart\";\nCM_ SG_ 359 Sig2All_Depart \"Left and right depart\";\nCM_ SG_ 359 All_depart_2015 \"always 1 on 2017\";\nCM_ SG_ 604 R_APPROACHING \"Faster car approaching in far right lane\";\nCM_ SG_ 604 L_APPROACHING \"Faster car approaching in far left lane\";\nCM_ SG_ 604 R_RCTA \"Rear cross traffic alert, only when in R gear\";\nCM_ SG_ 604 L_RCTA \"Rear cross traffic alert, only when in R gear\";\nCM_ SG_ 642 Counter \"Affected by signals\";\nCM_ SG_ 642 SEATBELT_FL \"Driver seatbelt\";\nCM_ SG_ 880 Steering_Voltage_Flat \"receives later than 371\";\nCM_ SG_ 977 UNITS \"0 = Metric, 1 = Imperial\";\n\nVAL_ 328 Gear 0 \"N\" 1 \"D\" 2 \"D\" 3 \"D\" 4 \"D\" 5 \"D\" 6 \"D\" 14 \"R\" 15 \"P\";\n\nCM_ \"subaru_outback_2019.dbc starts here\";\n\n\nBO_ 358 ES_DashStatus: 8 XXX\n SG_ Not_Ready_Startup : 0|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Seatbelt_Disengage : 12|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Disengage_Alert : 14|2@1+ (1,0) [0|3] \"\" XXX\n SG_ Cruise_On : 16|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Activated : 17|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Signal1 : 18|1@1+ (1,0) [0|1] \"\" XXX\n SG_ WHEELS_MOVING_2015 : 19|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Driver_Input : 20|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_Distance : 21|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Cruise_Set_Speed : 24|8@1+ (1,0) [0|255] \"\" XXX\n SG_ Cruise_Fault : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Cruise_On_2 : 34|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Counter : 37|3@1+ (1,0) [0|7] \"\" XXX\n SG_ Steep_Hill_Disengage : 44|1@1+ (1,0) [0|3] \"\" XXX\n SG_ Car_Follow : 46|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Far_Distance : 48|4@1+ (5,0) [0|15] \"m\" XXX\n\nBO_ 881 Steering_Torque: 8 XXX\n SG_ Steering_Motor_Flat : 0|10@1+ (32,0) [0|1000] \"\" XXX\n SG_ Steer_Torque_Output : 16|11@1- (-32,0) [-1000|1000] \"\" XXX\n SG_ Steer_Error_1 : 27|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Steer_Torque_Sensor : 29|11@1- (-1,0) [-1000|1000] \"\" XXX\n SG_ Steering_Angle : 40|16@1- (-0.033,0) [-600|600] \"\" XXX\n\nCM_ SG_ 358 Disengage_Alert \"seatbelt and steep hill disengage\";\nCM_ SG_ 358 Cruise_Fault \"No engagement until restart\";\nCM_ SG_ 358 Car_Follow \"lead car detected\";\n"
  },
  {
    "path": "opendbc/tesla_can.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBS_:\n\nBU_:\n    NEO\n    MCU\n    GTW\n    EPAS\n    DI\n    ESP\n    SBW\n    STW\n\tAPP\n\tDAS\n\tXXX\n\nVAL_TABLE_ StW_AnglHP_Spd 16383 \"SNA\" ;\nVAL_TABLE_ DI_aebFaultReason 15 \"DI_AEB_FAULT_DAS_REQ_DI_UNAVAIL\" 14 \"DI_AEB_FAULT_ACCEL_REQ_INVALID\" 13 \"DI_AEB_FAULT_MIN_TIME_BTWN_EVENTS\" 12 \"DI_AEB_FAULT_ESP_MIA\" 11 \"DI_AEB_FAULT_ESP_FAULT\" 10 \"DI_AEB_FAULT_EPB_NOT_PARKED\" 9 \"DI_AEB_FAULT_ACCEL_OUT_OF_BOUNDS\" 8 \"DI_AEB_FAULT_PM_REQUEST\" 7 \"DI_AEB_FAULT_VEL_EST_ABNORMAL\" 6 \"DI_AEB_FAULT_DAS_SNA\" 5 \"DI_AEB_FAULT_DAS_CONTROL_MIA\" 4 \"DI_AEB_FAULT_SPEED_DELTA\" 3 \"DI_AEB_FAULT_EBR_FAULT\" 2 \"DI_AEB_FAULT_PM_MIA\" 1 \"DI_AEB_FAULT_EPB_MIA\" 0 \"DI_AEB_FAULT_NONE\" ;\nVAL_TABLE_ DI_aebLockState 3 \"AEB_LOCK_STATE_SNA\" 2 \"AEB_LOCK_STATE_UNUSED\" 1 \"AEB_LOCK_STATE_UNLOCKED\" 0 \"AEB_LOCK_STATE_LOCKED\" ;\nVAL_TABLE_ DI_aebSmState 7 \"DI_AEB_STATE_FAULT\" 6 \"DI_AEB_STATE_EXIT\" 5 \"DI_AEB_STATE_STANDSTILL\" 4 \"DI_AEB_STATE_STOPPING\" 3 \"DI_AEB_STATE_ENABLE\" 2 \"DI_AEB_STATE_ENABLE_INIT\" 1 \"DI_AEB_STATE_STANDBY\" 0 \"DI_AEB_STATE_UNAVAILABLE\" ;\nVAL_TABLE_ DI_aebState 7 \"AEB_CAN_STATE_SNA\" 4 \"AEB_CAN_STATE_FAULT\" 3 \"AEB_CAN_STATE_STANDSTILL\" 2 \"AEB_CAN_STATE_ENABLED\" 1 \"AEB_CAN_STATE_STANDBY\" 0 \"AEB_CAN_STATE_UNAVAILABLE\" ;\nVAL_TABLE_ DI_epbInterfaceReady 1 \"EPB_INTERFACE_READY\" 0 \"EPB_INTERFACE_NOT_READY\" ;\nVAL_TABLE_ DI_gear 7 \"DI_GEAR_SNA\" 4 \"DI_GEAR_D\" 3 \"DI_GEAR_N\" 2 \"DI_GEAR_R\" 1 \"DI_GEAR_P\" 0 \"DI_GEAR_INVALID\" ;\nVAL_TABLE_ DI_gpoReason 8 \"DI_GPO_NUMREASONS\" 7 \"DI_GPO_CAPACITOR_OVERTEMP\" 6 \"DI_GPO_NOT_ENOUGH_12V\" 5 \"DI_GPO_NO_BATTERY_POWER\" 4 \"DI_GPO_AMBIENT_OVERTEMP\" 3 \"DI_GPO_FLUID_DELTAT\" 2 \"DI_GPO_STATOR_OVERTEMP\" 1 \"DI_GPO_HEATSINK_OVERTEMP\" 0 \"DI_GPO_OUTLET_OVERTEMP\" ;\nVAL_TABLE_ DI_immobilizerCondition 1 \"DI_IMM_CONDITION_LEARNED\" 0 \"DI_IMM_CONDITION_VIRGIN_SNA\" ;\nVAL_TABLE_ DI_immobilizerState 7 \"DI_IMM_STATE_FAULT\" 6 \"DI_IMM_STATE_FAULTRETRY\" 5 \"DI_IMM_STATE_RESET\" 4 \"DI_IMM_STATE_LEARN\" 3 \"DI_IMM_STATE_DISARMED\" 2 \"DI_IMM_STATE_AUTHENTICATING\" 1 \"DI_IMM_STATE_REQUEST\" 0 \"DI_IMM_STATE_INIT_SNA\" ;\nVAL_TABLE_ DI_limpReason 24 \"DI_LIMP_NUMREASONS\" 23 \"DI_LIMP_CAPACITOR_OVERTEMP\" 22 \"DI_LIMP_GTW_MIA\" 21 \"DI_LIMP_TRQCMD_VALIDITY_UNKNOWN\" 20 \"DI_LIMP_DI_MIA\" 19 \"DI_LIMP_CONFIG_MISMATCH\" 18 \"DI_LIMP_HEATSINK_TEMP\" 17 \"DI_LIMP_PMREQUEST\" 16 \"DI_LIMP_PMHEARTBEAT\" 15 \"DI_LIMP_TRQ_CROSS_CHECK\" 14 \"DI_LIMP_EXTERNAL_COMMAND\" 13 \"DI_LIMP_WRONG_CS_CALIBRATION\" 12 \"DI_LIMP_STATOR_TEMP\" 11 \"DI_LIMP_DELTAT_TOO_NEGATIVE\" 10 \"DI_LIMP_DELTAT_TOO_POSITIVE\" 9 \"DI_LIMP_AMBIENT_TEMP\" 8 \"DI_LIMP_OUTLET_TEMP\" 7 \"DI_LIMP_LOW_FLOW\" 6 \"DI_LIMP_BMS_MIA\" 5 \"DI_LIMP_12V_SUPPLY_UNDERVOLTAGE\" 4 \"DI_LIMP_NO_FLUID\" 3 \"DI_LIMP_NO_FUNC_HEATSINK_SENSOR\" 2 \"DI_LIMP_NO_FUNC_STATORT_SENSOR\" 1 \"DI_LIMP_BUSV_SENSOR_IRRATIONAL\" 0 \"DI_LIMP_PHASE_IMBALANCE\" ;\nVAL_TABLE_ DI_mode 2 \"DI_MODE_DYNO\" 1 \"DI_MODE_DRIVE\" 0 \"DI_MODE_UNDEF\" ;\nVAL_TABLE_ DI_motorType 14 \"DI_MOTOR_F2AE\" 13 \"DI_MOTOR_F2AD\" 12 \"DI_MOTOR_F2AC\" 11 \"DI_MOTOR_F2AB\" 10 \"DI_MOTOR_F1AC\" 9 \"DI_MOTOR_SSR1A\" 8 \"DI_MOTOR_F1A\" 7 \"DI_MOTOR_M7M6\" 6 \"DI_MOTOR_M8A\" 5 \"DI_MOTOR_M7M5\" 4 \"DI_MOTOR_M7M4\" 3 \"DI_MOTOR_M7M3\" 2 \"DI_MOTOR_ROADSTER_SPORT\" 1 \"DI_MOTOR_ROADSTER_BASE\" 0 \"DI_MOTOR_SNA\" ;\nVAL_TABLE_ DI_speedUnits 1 \"DI_SPEED_KPH\" 0 \"DI_SPEED_MPH\" ;\nVAL_TABLE_ DI_state 4 \"DI_STATE_ENABLE\" 3 \"DI_STATE_FAULT\" 2 \"DI_STATE_CLEAR_FAULT\" 1 \"DI_STATE_STANDBY\" 0 \"DI_STATE_PREAUTH\" ;\nVAL_TABLE_ DI_velocityEstimatorState 4 \"VE_STATE_BACKUP_MOTOR\" 3 \"VE_STATE_BACKUP_WHEELS_B\" 2 \"VE_STATE_BACKUP_WHEELS_A\" 1 \"VE_STATE_WHEELS_NORMAL\" 0 \"VE_STATE_NOT_INITIALIZED\" ;\n\n\nBO_ 1160 DAS_steeringControl: 4 NEO\n SG_ DAS_steeringControlType : 23|2@0+ (1,0) [0|0] \"\" EPAS\n SG_ DAS_steeringControlChecksum : 31|8@0+ (1,0) [0|0] \"\" EPAS\n SG_ DAS_steeringControlCounter : 19|4@0+ (1,0) [0|0] \"\" EPAS\n SG_ DAS_steeringAngleRequest : 6|15@0+ (0.1,-1638.35) [-1638.35|1638.35] \"deg\" EPAS\n SG_ DAS_steeringHapticRequest : 7|1@0+ (1,0) [0|0] \"\" EPAS\n\nBO_ 257 GTW_epasControl: 3 NEO\n SG_ GTW_epasControlChecksum : 23|8@0+ (1,0) [0|255] \"\"  NEO\n SG_ GTW_epasControlCounter : 11|4@0+ (1,0) [0|15] \"\"  NEO\n SG_ GTW_epasControlType : 15|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ GTW_epasEmergencyOn : 7|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ GTW_epasLDWEnabled : 12|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ GTW_epasPowerMode : 6|4@0+ (1,0) [4|14] \"\"  NEO\n SG_ GTW_epasTuneRequest : 2|3@0+ (1,0) [-1|8] \"\"  NEO\n\nBO_ 880 EPAS_sysStatus: 8 EPAS\n SG_ EPAS_currentTuneMode : 7|4@0+ (1,0) [8|15] \"\"  NEO\n SG_ EPAS_eacErrorCode : 23|4@0+ (1,0) [-1|16] \"\"  NEO\n SG_ EPAS_eacStatus : 55|3@0+ (1,0) [5|7] \"\"  NEO\n SG_ EPAS_handsOnLevel : 39|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ EPAS_internalSAS : 37|14@0+ (0.1,-819.200012) [0|0] \"deg\"  NEO\n SG_ EPAS_steeringFault : 2|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ EPAS_steeringRackForce : 1|10@0+ (50,-25575) [0|0] \"N\" NEO\n SG_ EPAS_steeringReduced : 3|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ EPAS_sysStatusChecksum : 63|8@0+ (1,0) [0|255] \"\"  NEO\n SG_ EPAS_sysStatusCounter : 51|4@0+ (1,0) [0|15] \"\"  NEO\n SG_ EPAS_torsionBarTorque : 19|12@0+ (0.01,-20.5) [0|0] \"Nm\"  NEO\n\nBO_ 3 STW_ANGL_STAT: 8 STW\n SG_ StW_Angl : 5|14@0+ (0.5,-2048) [0|0] \"deg\"  NEO\n SG_ StW_AnglSpd : 21|14@0+ (0.5,-2048) [0|0] \"/s\"  NEO\n SG_ StW_AnglSens_Stat : 33|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ StW_AnglSens_Id : 35|2@0+ (1,0) [3|3] \"\"  NEO\n SG_ MC_STW_ANGL_STAT : 55|4@0+ (1,0) [0|15] \"\"  NEO\n SG_ CRC_STW_ANGL_STAT : 63|8@0+ (1,0) [0|255] \"\"  NEO\n\nBO_ 14 STW_ANGLHP_STAT: 8 STW\n\n SG_ StW_AnglHP : 5|14@0+ (0.1,-819.2) [-819.2|819] \"deg\"  NEO\n SG_ StW_AnglHP_Spd : 21|14@0+ (0.5,-4096) [-4096|4095.5] \"deg/s\"  NEO\n SG_ StW_AnglHP_Sens_Stat : 33|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ StW_AnglHP_Sens_Id : 35|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ MC_STW_ANGLHP_STAT : 55|4@0+ (1,0) [0|15] \"\"  NEO\n SG_ CRC_STW_ANGLHP_STAT : 63|8@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 264 DI_torque1: 8 DI\n SG_ DI_torqueDriver : 0|13@1- (0.25,0) [-750|750] \"Nm\"  NEO\n SG_ DI_torque1Counter : 13|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_torqueMotor : 16|13@1- (0.25,0) [-750|750] \"Nm\"  NEO\n SG_ DI_soptState : 29|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_motorRPM : 32|16@1- (1,0) [-17000|17000] \"RPM\"  NEO\n SG_ DI_pedalPos : 48|8@1+ (0.4,0) [0|100] \"%\"  NEO\n SG_ DI_torque1Checksum : 56|8@1+ (1,0) [0|0] \"\"  NEO\n\nBO_ 280 DI_torque2: 6 DI\n SG_ DI_torqueEstimate : 0|12@1- (0.5,0) [-750|750] \"Nm\" NEO\n SG_ DI_gear : 12|3@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_brakePedal : 15|1@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_vehicleSpeed : 16|12@1+ (0.05,-25) [-25|179.75] \"MPH\" NEO\n SG_ DI_gearRequest : 28|3@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_torqueInterfaceFailure : 31|1@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_torque2Counter : 32|4@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_brakePedalState : 36|2@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_epbParkRequest : 38|1@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_epbInterfaceReady : 39|1@1+ (1,0) [0|0] \"\" NEO\n SG_ DI_torque2Checksum : 40|8@1+ (1,0) [0|0] \"\" NEO\n\nBO_ 309 ESP_135h: 5 ESP\n SG_ ESP_135hChecksum : 23|8@0+ (1,0) [0|255] \"\"  NEO\n SG_ ESP_135hCounter : 11|4@0+ (1,0) [0|15] \"\"  NEO\n SG_ ESP_absBrakeEvent : 2|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_brakeDiscWipingActive : 4|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_brakeLamp : 3|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_espFaultLamp : 6|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_espLampFlash : 7|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_hillStartAssistActive : 1|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ ESP_messagePumpService : 24|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ ESP_messagePumpFailure : 25|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ ESP_messageEBDFailure : 26|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ ESP_absFaultLamp : 27|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_tcDisabledByFault : 28|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ ESP_messageDynoModeActive : 29|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ ESP_hydraulicBoostEnabled : 30|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ ESP_espOffLamp : 31|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_stabilityControlSts : 14|3@0+ (1,0) [6|7] \"\"  NEO\n SG_ ESP_tcLampFlash : 5|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ESP_tcOffLamp : 15|1@0+ (1,0) [0|1] \"\"  NEO\n\nBO_ 341 ESP_B: 8 ESP\n SG_ ESP_BChecksum : 39|8@0+ (1,0) [0|255] \"\"  NEO,EPAS\n SG_ ESP_BCounter : 62|4@0+ (1,0) [1|15] \"\"  NEO,EPAS\n SG_ ESP_vehicleSpeed : 47|16@0+ (0.00999999978,0) [0|0] \"kph\"  NEO,EPAS\n SG_ ESP_vehicleSpeedQF : 57|2@0+ (1,0) [1|2] \"\"  NEO,EPAS\n SG_ ESP_wheelPulseCountFrL : 7|8@0+ (1,0) [0|254] \"\"  NEO,EPAS\n SG_ ESP_wheelPulseCountFrR : 15|8@0+ (1,0) [0|254] \"\"  NEO,EPAS\n SG_ ESP_wheelPulseCountReL : 23|8@0+ (1,0) [0|254] \"\"  NEO,EPAS\n SG_ ESP_wheelPulseCountReR : 31|8@0+ (1,0) [0|254] \"\"  NEO,EPAS\n\nBO_ 513 SDM1: 5 GTW\n SG_ SDM_bcklPassStatus : 3|2@0+ (1,0) [0|3] \"\" NEO\n SG_ SDM_bcklDrivStatus : 5|2@0+ (1,0) [0|3] \"\" NEO\n\nBO_ 532 EPB_epasControl: 3 EPB\n SG_ EPB_epasControlChecksum : 23|8@0+ (1,0) [0|255] \"\"  NEO,EPAS\n SG_ EPB_epasControlCounter : 11|4@0+ (1,0) [0|15] \"\"  NEO,EPAS\n SG_ EPB_epasEACAllow : 2|3@0+ (1,0) [4|7] \"\"  NEO,EPAS\n\nBO_ 792 GTW_carState: 8 GTW\n SG_ YEAR : 0|7@1+ (1,2000) [2000|2127] \"Year\" NEO\n SG_ CERRD : 7|1@1+ (1,0) [0|1] \"\" NEO\n SG_ MONTH : 8|4@1+ (1,0) [1|12] \"Month\" NEO\n SG_ DOOR_STATE_FL : 12|2@1+ (1,0) [0|3] \"\" NEO\n SG_ DOOR_STATE_FR : 14|2@1+ (1,0) [0|3] \"\" NEO\n SG_ SECOND : 16|6@1+ (1,0) [0|59] \"s\" NEO\n SG_ DOOR_STATE_RL : 22|2@1+ (1,0) [0|3] \"\" NEO\n SG_ Hour : 24|5@1+ (1,0) [0|23] \"h\" NEO\n SG_ DOOR_STATE_RR : 29|2@1+ (1,0) [0|3] \"\" NEO\n SG_ DAY : 32|5@1+ (1,0) [0|31] \"\" NEO\n SG_ MINUTE : 40|6@1+ (1,0) [0|59] \"min\" NEO\n SG_ BOOT_STATE : 46|2@1+ (1,0) [0|3] \"\" NEO\n SG_ GTW_updateInProgress : 48|2@1+ (1,0) [0|3] \"\" NEO\n SG_ DOOR_STATE_FrontTrunk : 50|2@1+ (1,0) [0|3] \"\" NEO\n SG_ MCU_factoryMode : 52|1@1+ (1,0) [0|1] \"\" NEO\n SG_ MCU_transportModeOn : 53|1@0+ (1,0) [0|1] \"\" NEO\n SG_ BC_headLightLStatus : 55|2@0+ (1,0) [0|3] \"\" NEO\n SG_ BC_headLightRStatus : 57|2@0+ (1,0) [0|3] \"\" NEO\n SG_ BC_indicatorLStatus : 59|2@0+ (1,0) [0|3] \"\" NEO\n SG_ BC_indicatorRStatus : 61|2@0+ (1,0) [0|3] \"\" NEO\n\nBO_ 872 DI_state: 8 DI\n SG_ DI_systemState : 0|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_vehicleHoldState : 3|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_proximity : 6|1@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_driveReady : 7|1@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_regenLight : 8|1@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_state : 9|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_cruiseState : 12|4@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_analogSpeed : 16|12@1+ (0.1,0) [0|150] \"speed\"  NEO\n SG_ DI_immobilizerState : 28|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_speedUnits : 31|1@1+ (1,0) [0|1] \"\"  NEO\n SG_ DI_cruiseSet : 32|9@1+ (0.5,0) [0|255.5] \"speed\"  NEO\n SG_ DI_aebState : 41|3@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_stateCounter : 44|4@1+ (1,0) [0|0] \"\"  NEO\n SG_ DI_digitalSpeed : 48|8@1+ (1,0) [0|250] \"\"  NEO\n SG_ DI_stateChecksum : 56|8@1+ (1,0) [0|0] \"\"  NEO\n\nBO_ 109 SBW_RQ_SCCM: 4 STW\n SG_ StW_Sw_Stat3 : 0|3@1+ (1,0) [0|0] \"\" NEO\n SG_ MsgTxmtId : 6|2@1+ (1,0) [0|0] \"\" NEO\n SG_ TSL_RND_Posn_StW : 8|4@1+ (1,0) [0|0] \"\" NEO\n SG_ TSL_P_Psd_StW : 12|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MC_SBW_RQ_SCCM : 20|4@1+ (1,0) [0|15] \"\" NEO\n SG_ CRC_SBW_RQ_SCCM : 24|8@1+ (1,0) [0|0] \"\" NEO\n\nBO_ 69 STW_ACTN_RQ: 8 STW\n SG_ SpdCtrlLvr_Stat : 0|6@1+ (1,0) [0|0] \"\" NEO\n SG_ VSL_Enbl_Rq : 6|1@1+ (1,0) [0|0] \"\" NEO\n SG_ SpdCtrlLvrStat_Inv : 7|1@1+ (1,0) [0|0] \"\" NEO\n SG_ DTR_Dist_Rq : 8|8@1+ (1,0) [0|200] \"\" NEO\n SG_ TurnIndLvr_Stat : 16|2@1+ (1,0) [0|0] \"\" NEO\n SG_ HiBmLvr_Stat : 18|2@1+ (1,0) [0|0] \"\" NEO\n SG_ WprWashSw_Psd : 20|2@1+ (1,0) [0|0] \"\" NEO\n SG_ WprWash_R_Sw_Posn_V2 : 22|2@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Lvr_Stat : 24|3@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Cond_Flt : 27|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Cond_Psd : 28|2@1+ (1,0) [0|0] \"\" NEO\n SG_ HrnSw_Psd : 30|2@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw00_Psd : 32|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw01_Psd : 33|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw02_Psd : 34|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw03_Psd : 35|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw04_Psd : 36|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw05_Psd : 37|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw06_Psd : 38|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw07_Psd : 39|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw08_Psd : 40|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw09_Psd : 41|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw10_Psd : 42|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw11_Psd : 43|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw12_Psd : 44|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw13_Psd : 45|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw14_Psd : 46|1@1+ (1,0) [0|0] \"\" NEO\n SG_ StW_Sw15_Psd : 47|1@1+ (1,0) [0|0] \"\" NEO\n SG_ WprSw6Posn : 48|3@1+ (1,0) [0|0] \"\" NEO\n SG_ MC_STW_ACTN_RQ : 52|4@1+ (1,0) [0|15] \"\" NEO\n SG_ CRC_STW_ACTN_RQ : 56|8@1+ (1,0) [0|0] \"\" NEO\n\nBO_ 643 BODY_R1: 8 GTW\n SG_ AirTemp_Insd : 47|8@0+ (0.25,0) [0|63.5] \"C\"  NEO\n SG_ AirTemp_Outsd : 63|8@0+ (0.5,-40) [-40|86.5] \"C\"  NEO\n SG_ Bckl_Sw_RL_Stat_SAM_R : 49|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ Bckl_Sw_RM_Stat_SAM_R : 53|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ Bckl_Sw_RR_Stat_SAM_R : 51|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ DL_RLtch_Stat : 9|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ DrRLtch_FL_Stat : 1|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ DrRLtch_FR_Stat : 3|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ DrRLtch_RL_Stat : 5|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ DrRLtch_RR_Stat : 7|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ EngHd_Stat : 11|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ LoBm_On_Rq : 32|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ HiBm_On : 33|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ Hrn_On : 26|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ IrLmp_D_Lt_Flt : 34|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ IrLmp_P_Rt_Flt : 35|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LgtSens_Twlgt : 18|3@0+ (1,0) [0|7] \"Steps\"  NEO\n SG_ LgtSens_SNA : 19|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LgtSens_Tunnel : 20|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LgtSens_Flt : 21|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LgtSens_Night : 22|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ ADL_LoBm_On_Rq : 23|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LoBm_D_Lt_Flt : 36|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ LoBm_P_Rt_Flt : 37|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ MPkBrk_Stat : 28|1@0+ (1,0) [-1|2] \"\"  NEO\n SG_ RevGr_Engg : 39|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ StW_Cond_Stat : 55|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ Term54_Actv : 27|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ Trlr_Stat : 25|2@0+ (1,0) [-1|4] \"\"  NEO\n SG_ VTA_Alm_Actv : 13|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ WprOutsdPkPosn : 29|1@0+ (1,0) [0|1] \"\"  NEO\n\nBO_ 760 UI_gpsVehicleSpeed: 8 GTW\n SG_ UI_gpsHDOP : 0|8@1+ (0.1,0) [0|25.5] \"1\" DAS\n SG_ UI_gpsVehicleHeading : 8|16@1+ (0.0078125,0) [0|511.9921875] \"deg\" DAS\n SG_ UI_gpsVehicleSpeed : 24|16@1+ (0.00390625,0) [0|250.996] \"km/hr\" Vector__XXX\n SG_ UI_userSpeedOffset : 40|6@1+ (1,-30) [-30|33] \"kph/mph\" DAS\n SG_ UI_mapSpeedLimitUnits : 46|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_userSpeedOffsetUnits : 47|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_mppSpeedLimit : 48|5@1+ (5,0) [0|155] \"kph/mph\" DAS\n SG_ UI_gpsNmeaMIA : 53|1@1+ (1,0) [0|0] \"\" DAS\n\nBO_ 536 MCU_chassisControl: 8 GTW\n SG_ MCU_dasDebugEnable : 0|1@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_parkBrakeRequest : 1|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_trailerModeCH : 3|1@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_fcwSensitivity : 4|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_fcwEnable : 6|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_latControlEnable : 8|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_accOvertakeEnable : 10|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_ldwEnable : 12|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_aebEnable : 14|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_bsdEnable : 16|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_ahlbEnable : 18|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_parkSetting : 20|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_pedalSafetyEnable : 22|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_frontDefrostReq_das : 24|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_autoParkRequest : 26|4@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_redLightStopSignEnable : 30|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_enableCreepTorqueCH : 32|1@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_narrowGarages : 33|1@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_rebootAutopilot : 34|1@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_enableAutowipers : 35|1@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_overPaintedUSS : 38|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_selfParkTune : 40|4@1+ (1,0) [0|15] \"\" NEO\n SG_ MCU_towModeEnable : 44|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_zeroSpeedConfirmed : 46|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_aesEnable : 48|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_autoLaneChangeEnable : 50|2@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_chassisControlCounter : 52|4@1+ (1,0) [0|0] \"\" NEO\n SG_ MCU_chassisControlChecksum : 56|8@1+ (1,0) [0|0] \"\" NEO\n\nBO_ 904 MCU_clusterBacklightRequest: 3 NEO\n SG_ MCU_clusterBacklightOn : 7|1@1+ (1,0) [0|1] \"\" NEO\n SG_ MCU_clusterBrightnessLevel : 8|8@1+ (0.5,0) [0|127.5] \"%\" NEO\n SG_ MCU_clusterReadyForDrive : 6|1@1+ (1,0) [-1|2] \"\"  NEO\n SG_ MCU_clusterReadyForPowerOff : 5|1@1+ (1,0) [0|1] \"\" NEO\n\nBO_ 984 MCU_locationStatus: 8 MCU\n SG_ MCU_gpsAccuracy : 57|7@1+ (0.2,0) [0|0] \"m\" NEO\n SG_ MCU_latitude : 0|28@1- (1E-06,0) [0|0] \"deg\" NEO\n SG_ MCU_longitude : 28|29@1- (1E-06,0) [0|0] \"deg\" NEO\n\nBO_ 104 MCU_locationStatus2: 8 MCU\n SG_ MCU_elevation : 0|32@1- (0.1,0) [0|0] \"m\" GTW\n SG_ MCU_navigonExpectedSpeed : 32|7@1+ (1,0) [0|126] \"mph\" GTW\n\nBO_ 840 GTW_status: 8 GTW\n SG_ GTW_accGoingDown : 6|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_accRailReq : 8|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_brakePressed : 1|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_driveGoingDown : 7|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_driveRailReq : 0|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_driverIsLeaving : 5|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_driverPresent : 2|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_hvacGoingDown : 11|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_hvacRailReq : 9|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_icPowerOff : 4|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_notEnough12VForDrive : 3|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_preconditionRequest : 10|1@0+ (1,0) [0|1] \"\"  NEO\n SG_ GTW_statusChecksum : 63|8@0+ (1,0) [0|255] \"\"  NEO\n SG_ GTW_statusCounter : 51|4@0+ (1,0) [0|15] \"\"  NEO\n\nBO_ 920 GTW_carConfig: 8 GTW\n SG_ GTW_performanceConfig : 2|3@0+ (1,0) [0|0] \"\" NEO\n SG_ GTW_fourWheelDrive : 4|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_unknown1 : 5|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_dasHw : 7|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_parkAssistInstalled : 9|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_forwardRadarHw : 11|2@0+ (1,0) [0|0] \"\" NEO\n SG_ GTW_airSuspensionInstalled : 14|3@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_unknown2 : 15|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_country : 23|16@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_parkSensorGeometryType : 33|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_rhd : 34|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_bodyControlsType : 35|1@0+ (1,0) [0|0] \"\" NEO\n SG_ GTW_radarPosition : 39|4@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_rearCornerRadarHw : 41|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_frontCornerRadarHw : 43|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_epasType : 45|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_chassisType : 47|2@0+ (1,0) [0|2] \"\"  NEO\n SG_ GTW_wheelType : 52|5@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_rearSeatControllerMask : 55|3@0+ (1,0) [0|7] \"\"  NEO\n SG_ GTW_euVehicle : 56|1@0+ (1,0) [0|0] \"\" NEO\n SG_ GTW_foldingMirrorsInstalled : 57|1@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_brakeHwType : 59|2@0+ (1,0) [0|2] \"\"  NEO\n SG_ GTW_autopilot : 61|2@0+ (1,0) [0|0] \"\"  NEO\n SG_ GTW_unknown3 : 63|2@0+ (1,0) [0|0] \"\"  NEO\n\nBO_ 1006 UI_autopilotControl: 8 GTW\n SG_ UI_autopilotControlIndex M : 0|3@1+ (1,0) [0|7] \"\" APP,APS\n SG_ UI_hovEnabled m0 : 3|1@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donDisableAutoWiperDuration m0 : 4|3@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donDisableOnAutoWiperSpeed m0 : 7|4@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_blindspotMinSpeed m0 : 11|4@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_blindspotDistance m0 : 15|3@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_blindspotTTC m0 : 18|3@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donStopEndOfRampBuffer m0 : 21|3@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donDisableCutin m0 : 24|1@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donMinGoreWidthForAbortMap m0 : 25|4@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donAlcProgGoreAbortThres m0 : 29|4@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_donMinGoreWidthForAbortNotMap m0 : 33|4@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcDisableUltrasonicCheck m0 : 37|1@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcUltrasonicDistance m0 : 38|4@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcUltrasonicWaitTime m0 : 42|3@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcEgoLeadingReactionAccel m0 : 48|2@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcMergIntervalRearDHyst m0 : 50|2@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcMergingIntervalHeadwayHyst m0 : 52|2@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcAssertivenessRate m0 : 54|2@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_alcViewRangeSensitivity m0 : 56|2@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_camBlockLaneCheckDisable m1 : 3|1@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_camBlockLaneCheckThreshold m1 : 4|6@1+ (0.01587,0) [0|1] \"%\" APP,APS\n SG_ UI_camBlockBlurDisable m1 : 10|1@1+ (1,0) [0|0] \"\" APP,APS\n SG_ UI_camBlockBlurThreshold m1 : 11|6@1+ (0.01587,0) [0|1] \"%\" APP,APS\n\nBO_ 728 UI_csaOfframpCurvature: 8 GTW\n SG_ UI_csaOfframpCurvC2 : 0|16@1- (1E-06,0) [-0.032768|0.032767] \"1/m\" DAS\n SG_ UI_csaOfframpCurvC3 : 16|16@1- (4E-09,0) [-0.000131072|0.000131068] \"1/m2\" DAS\n SG_ UI_csaOfframpCurvRange : 32|8@1+ (2,0) [0|510] \"m\" DAS\n SG_ UI_csaOfframpCurvCounter : 40|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ UI_csaOfframpCurvUsingTspline : 48|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_csaOfframpCurvReserved : 49|7@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_csaOfframpCurvChecksum : 56|8@1+ (1,0) [0|0] \"\" Vector__XXX\n\nBO_ 744 UI_csaRoadCurvature: 8 GTW\n SG_ UI_csaRoadCurvC2 : 0|16@1- (1E-06,0) [-0.032768|0.032767] \"1/m\" DAS\n SG_ UI_csaRoadCurvC3 : 16|16@1- (4E-09,0) [-0.000131072|0.000131068] \"1/m2\" DAS\n SG_ UI_csaRoadCurvRange : 32|8@1+ (2,0) [0|510] \"m\" DAS\n SG_ UI_csaRoadCurvCounter : 40|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ UI_csaRoadCurvUsingTspline : 48|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_csaRoadCurvReserved : 49|7@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_csaRoadCurvChecksum : 56|8@1+ (1,0) [0|0] \"\" Vector__XXX\n\nBO_ 1080 UI_driverAssistAnonDebugParams: 8 GTW\n SG_ UI_anonDebugParam1 : 0|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_anonDebugFlag1 : 7|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_anonDebugParam2 : 8|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_anonDebugFlag2 : 15|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_anonDebugParam3 : 16|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_anonDebugFlag3 : 23|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_anonDebugParam4 : 24|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_anonDebugFlag4 : 31|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_anonDebugParam5 : 32|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_anonDebugParam6 : 40|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_anonDebugParam7 : 48|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_visionSpeedSlider : 56|7@1+ (1,0) [0|100] \"\" DAS\n\nBO_ 1000 UI_driverAssistControl: 8 GTW\n SG_ UI_autopilotControlRequest : 0|1@1+ (1,0) [1|0] \"\" DAS\n SG_ UI_ulcStalkConfirm : 1|1@1+ (1,0) [1|0] \"\" DAS\n SG_ UI_summonHeartbeat : 2|2@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_curvSpeedAdaptDisable : 4|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_dasDeveloper : 5|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_enableVinAssociation : 6|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_lssLkaEnabled : 7|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_lssLdwEnabled : 8|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_autoSummonEnable : 10|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_exceptionListEnable : 11|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_roadCheckDisable : 12|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_driveOnMapsEnable : 13|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_handsOnRequirementDisable : 14|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_forksEnable : 15|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_fuseLanesDisable : 16|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_fuseHPPDisable : 17|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_fuseVehiclesDisable : 18|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_enableNextGenACC : 19|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_visionSpeedType : 20|2@1+ (1,0) [0|0] \"\" APP\n SG_ UI_curvatureDatabaseOnly : 22|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_lssElkEnabled : 23|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_summonExitType : 24|2@1+ (1,0) [0|3] \"\" DAS\n SG_ UI_summonEntryType : 26|2@1+ (1,0) [0|3] \"\" DAS\n SG_ UI_selfParkRequest : 28|4@1+ (1,0) [0|15] \"\" DAS,PARK\n SG_ UI_summonReverseDist : 32|6@1+ (1,0) [0|63] \"\" DAS\n SG_ UI_undertakeAssistEnable : 38|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_adaptiveSetSpeedEnable : 39|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_drivingSide : 40|2@1+ (1,0) [0|3] \"\" DAS\n SG_ UI_enableClipTelemetry : 42|1@1+ (1,0) [0|0] \"\" APP\n SG_ UI_enableTripTelemetry : 43|1@1+ (1,0) [0|0] \"\" APP\n SG_ UI_enableRoadSegmentTelemetry : 44|1@1+ (1,0) [0|0] \"\" APP\n SG_ UI_followNavRouteEnable : 46|1@1+ (1,0) [0|0] \"\" APP\n SG_ UI_ulcSpeedConfig : 48|2@1+ (1,0) [0|3] \"\" APP\n SG_ UI_ulcBlindSpotConfig : 50|2@1+ (1,0) [0|3] \"\" APP\n SG_ UI_autopilotAlwaysOn : 52|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_accFromZero : 53|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_alcOffHighwayEnable : 54|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_validationLoop : 55|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_ulcOffHighway : 56|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_enableNavRouteCSA : 57|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_enableCutinExperiments : 58|1@1+ (1,0) [0|1] \"\" APP\n SG_ UI_source3D : 60|3@1+ (1,0) [0|7] \"\" APP\n SG_ UI_enableVisionOnlyStops : 63|1@1+ (1,0) [0|1] \"\" APP\n\nBO_ 968 UI_driverAssistMapData: 8 GTW\n SG_ UI_mapSpeedLimitDependency : 0|3@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_roadClass : 3|3@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_inSuperchargerGeofence : 6|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_mapSpeedUnits : 7|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_mapSpeedLimit : 8|5@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_mapSpeedLimitType : 13|3@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_countryCode : 16|10@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_streetCount : 26|2@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_gpsRoadMatch : 28|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_navRouteActive : 29|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_parallelAutoparkEnabled : 30|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_perpendicularAutoparkEnabled : 31|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_nextBranchDist : 32|5@1+ (10,0) [0|300] \"m\" DAS\n SG_ UI_controlledAccess : 37|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_nextBranchLeftOffRamp : 38|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_nextBranchRightOffRamp : 39|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectLeftLane : 40|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectRightLane : 41|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectHPP : 42|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectNav : 43|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectLeftFreeSpace : 44|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectRightFreeSpace : 45|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectAutosteer : 46|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_rejectHandsOn : 47|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_acceptBottsDots : 48|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_autosteerRestricted : 49|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_pmmEnabled : 50|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_scaEnabled : 51|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_mapDataCounter : 52|4@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_mapDataChecksum : 56|8@1+ (1,0) [0|0] \"\" DAS\n\nBO_ 568 UI_driverAssistRoadSign: 8 GTW\n SG_ UI_roadSign M : 0|8@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_splineLocConfidence : 40|7@1+ (1,0) [0|100] \"\" DAS\n SG_ UI_splineID : 48|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ UI_roadSignCounter : 52|4@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_roadSignChecksum : 56|8@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_dummyData m0 : 8|1@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_stopSignStopLineDist m1 : 8|10@1+ (0.25,-8) [-8|247.5] \"m\" Vector__XXX\n SG_ UI_stopSignStopLineConf m1 : 18|7@1+ (1,0) [0|100] \"\" Vector__XXX\n SG_ UI_trafficLightStopLineDist m2 : 8|10@1+ (0.25,-8) [-8|247.5] \"m\" Vector__XXX\n SG_ UI_trafficLightStopLineConf m2 : 18|7@1+ (1,0) [0|100] \"\" Vector__XXX\n SG_ UI_baseMapSpeedLimitMPS m3 : 8|8@1+ (0.25,0) [0|63.75] \"m/s\" DAS\n SG_ UI_bottomQrtlFleetSpeedMPS m3 : 16|8@1+ (0.25,0) [0|63.75] \"m/s\" DAS\n SG_ UI_topQrtlFleetSpeedMPS m3 : 24|8@1+ (0.25,0) [0|63.75] \"m/s\" DAS\n SG_ UI_meanFleetSplineSpeedMPS m4 : 8|8@1+ (0.25,0) [0|63.75] \"m/s\" DAS\n SG_ UI_medianFleetSpeedMPS m4 : 16|8@1+ (0.25,0) [0|63.75] \"m/s\" DAS\n SG_ UI_meanFleetSplineAccelMPS2 m4 : 24|8@1+ (0.05,-6.35) [-6.35|6.4] \"m/s^2\" DAS\n SG_ UI_rampType m4 : 32|3@1+ (1,0) [0|7] \"\" DAS\n SG_ UI_currSplineIdFull m5 : 8|32@1+ (1,0) [0|1] \"\" APP\n\n\nBO_ 696 UI_radarMapData: 8 GTW\n SG_ UI_radarTargetDx : 0|8@1+ (1,-95) [-95|160] \"m\" DAS\n SG_ UI_radarTargetDxEnd : 8|8@1+ (1,0) [0|255] \"m\" DAS\n SG_ UI_radarTargetTrustMap : 16|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_radarEnableBraking : 17|1@1+ (1,0) [0|1] \"\" DAS\n SG_ UI_radarMapDataCounter : 52|4@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_radarMapDataChecksum : 56|8@1+ (1,0) [0|0] \"\" DAS\n\nBO_ 712 UI_roadCurvature: 8 GTW\n SG_ UI_roadCurvC0 : 0|11@1- (0.02,0) [-20.48|20.46] \"m\" DAS\n SG_ UI_roadCurvC1 : 11|10@1- (0.00075,0) [-0.384|0.38325] \"1\" DAS\n SG_ UI_roadCurvC2 : 21|14@1- (7.5E-06,0) [-0.03072|0.03071625] \"1/m\" DAS\n SG_ UI_roadCurvC3 : 35|13@1- (3E-08,0) [-0.00012288|0.00012285] \"1/m2\" DAS\n SG_ UI_roadCurvRange : 48|6@1+ (4,0) [0|252] \"m\" DAS\n SG_ UI_roadCurvHealth : 54|2@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_roadCurvChecksum : 56|8@1+ (1,0) [0|0] \"\" Vector__XXX\n\nBO_ 582 UI_solarData: 5 GTW\n SG_ UI_solarAzimuthAngle : 0|16@1- (1,0) [0|360] \"deg\" APP\n SG_ UI_solarAzimuthAngleCarRef : 16|9@1- (1,0) [-180|180] \"deg\" APP\n SG_ UI_isSunUp : 25|1@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_solarElevationAngle : 32|8@1- (1,0) [-90|90] \"deg\" APP\n\nBO_ 824 UI_status: 8 GTW\n SG_ UI_touchActive : 0|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_audioActive : 1|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_bluetoothActive : 2|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_cellActive : 3|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_displayReady : 4|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_gpsActive : 5|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_wifiConnected : 6|1@1+ (1,0) [0|0] \"\" IC,APP\n SG_ UI_systemActive : 7|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_xmActive : 8|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_displayOn : 9|1@1+ (1,0) [0|0] \"\" IC,APP\n SG_ UI_readyForDrive : 10|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_cellConnected : 11|1@1+ (1,0) [0|0] \"\" IC,APP\n SG_ UI_vpnActive : 12|1@1+ (1,0) [0|0] \"\" IC,APP\n SG_ UI_wifiActive : 13|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_cameraActive : 14|1@1+ (1,0) [0|0] \"\" IC,APP\n SG_ UI_usbActive : 15|1@1+ (1,0) [0|0] \"\" IC\n SG_ UI_screenshotActive : 16|1@1+ (1,0) [0|0] \"\" IC,APP\n SG_ UI_monitorModemPower : 17|1@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_factoryReset : 18|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ UI_cellNetworkTechnology : 20|4@1+ (1,0) [0|15] \"\" APP\n SG_ UI_tegraCoreTemperature : 24|8@1+ (1,-64) [0|0] \"deg C\" IC\n SG_ UI_tegraAmbientTemperature : 32|8@1+ (1,-64) [0|0] \"deg C\" IC\n SG_ UI_googleWifiUsages : 40|8@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_autopilotTrial : 48|2@1+ (1,0) [0|0] \"\" APP\n SG_ UI_cellSignalBars : 50|3@1+ (1,0) [0|7] \"\" APP\n SG_ UI_hardwareType : 53|2@1+ (1,0) [0|3] \"\" APP\n SG_ UI_developmentCar : 55|1@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_cellReceiverPower : 56|8@1+ (1,-128) [-128|127] \"dB\" APP\n\nBO_ 1064 UI_telemetryControl: 8 GTW\n SG_ UI_TCR_enable : 0|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_moveStateStanding : 1|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_moveStateStopped : 2|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_moveStateMoving : 3|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_moveStateIndeterm : 4|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_classConstElem : 5|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_classMovingPed : 6|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_classMovingTwoWheel : 7|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_classMovingFourWheel : 8|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_classUnknown : 9|1@1+ (1,0) [0|0] \"\" DAS\n SG_ UI_TCR_downSampleFactor : 16|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ UI_TCR_wExist : 24|5@1+ (1,0) [0|31] \"\" Vector__XXX\n SG_ UI_TCR_vehSpeed : 32|8@1+ (1,0) [0|0] \"\" Vector__XXX\n SG_ UI_TCR_minRCS : 40|8@1+ (0.25,-14) [-14|49.75] \"dB\" Vector__XXX\n SG_ UI_TCR_maxDy : 48|5@1+ (0.5,0) [0|15.5] \"m\" Vector__XXX\n SG_ UI_TCR_maxObjects : 56|5@1+ (1,0) [0|31] \"\" Vector__XXX\n SG_ UI_TCR_maxRoadClass : 61|3@1+ (1,0) [0|7] \"\" Vector__XXX\n\nBO_ 522 BrakeMessage: 8 XXX\n SG_ driverBrakeStatus : 2|2@1+ (1,0) [0|3] \"\" XXX\n\nBO_ 921 AutopilotStatus: 8 XXX\n SG_ autopilotStatus : 0|4@1+ (1,0) [0|0] \"\" XXX\n\nVAL_ 3 StW_Angl 16383 \"SNA\" ;\nVAL_ 3 StW_AnglSens_Id 2 \"MUST\" 0 \"PSBL\" 1 \"SELF\" ;\nVAL_ 3 StW_AnglSens_Stat 2 \"ERR\" 3 \"ERR_INI\" 1 \"INI\" 0 \"OK\" ;\nVAL_ 3 StW_AnglSpd 16383 \"SNA\" ;\nVAL_ 14 StW_AnglHP 16383 \"SNA\" ;\nVAL_ 14 StW_AnglHP_Spd 16383 \"SNA\" ;\nVAL_ 14 StW_AnglHP_Sens_Stat 3 \"SNA\" 2 \"ERR\" 1 \"INI\" 0 \"OK\" ;\nVAL_ 14 StW_AnglHP_Sens_Id 3 \"SNA\" 2 \"KOSTAL\" 1 \"DELPHI\" 0 \"TEST\" ;\nVAL_ 69 SpdCtrlLvr_Stat 32 \"DN_1ST\" 16 \"UP_1ST\" 8 \"DN_2ND\" 4 \"UP_2ND\" 2 \"RWD\" 1 \"FWD\" 0 \"IDLE\" ;\nVAL_ 69 DTR_Dist_Rq 255 \"SNA\" 200 \"ACC_DIST_7\" 166 \"ACC_DIST_6\" 133 \"ACC_DIST_5\" 100 \"ACC_DIST_4\" 66 \"ACC_DIST_3\" 33 \"ACC_DIST_2\" 0 \"ACC_DIST_1\" ;\nVAL_ 69 TurnIndLvr_Stat 3 \"SNA\" 2 \"RIGHT\" 1 \"LEFT\" 0 \"IDLE\" ;\nVAL_ 69 HiBmLvr_Stat 3 \"SNA\" 2 \"HIBM_FLSH_ON_PSD\" 1 \"HIBM_ON_PSD\" 0 \"IDLE\" ;\nVAL_ 69 WprWashSw_Psd 3 \"SNA\" 2 \"WASH\" 1 \"TIPWIPE\" 0 \"NPSD\" ;\nVAL_ 69 WprWash_R_Sw_Posn_V2 3 \"SNA\" 2 \"WASH\" 1 \"INTERVAL\" 0 \"OFF\" ;\nVAL_ 69 StW_Lvr_Stat 4 \"STW_BACK\" 3 \"STW_FWD\" 2 \"STW_DOWN\" 1 \"STW_UP\" 0 \"NPSD\" ;\nVAL_ 69 StW_Cond_Psd 3 \"SNA\" 2 \"DOWN\" 1 \"UP\" 0 \"NPSD\" ;\nVAL_ 69 HrnSw_Psd 3 \"SNA\" 2 \"NDEF2\" 1 \"PSD\" 0 \"NPSD\" ;\nVAL_ 69 StW_Sw00_Psd 1 \"PRESSED\" 0 \"NOT_PRESSED_SNA\" ;\nVAL_ 69 StW_Sw01_Psd 1 \"PRESSED\" 0 \"NOT_PRESSED_SNA\" ;\nVAL_ 69 StW_Sw03_Psd 1 \"PRESSED\" 0 \"NOT_PRESSED_SNA\" ;\nVAL_ 69 StW_Sw04_Psd 1 \"PRESSED\" 0 \"NOT_PRESSED_SNA\" ;\nVAL_ 69 WprSw6Posn 7 \"SNA\" 6 \"STAGE2\" 5 \"STAGE1\" 4 \"INTERVAL4\" 3 \"INTERVAL3\" 2 \"INTERVAL2\" 1 \"INTERVAL1\" 0 \"OFF\" ;\nVAL_ 257 GTW_epasControlType 0 \"WITHOUT\" 1 \"WITH_ANGLE\" 3 \"WITH_BOTH\" 2 \"WITH_TORQUE\" ;\nVAL_ 109 StW_Sw_Stat3 7 \"SNA\" 6 \"NDEF6\" 5 \"NDEF5\" 4 \"NDEF4\" 3 \"PLUS_MINUS\" 2 \"MINUS\" 1 \"PLUS\" 0 \"NPSD\" ;\nVAL_ 109 MsgTxmtId 3 \"NDEF3\" 2 \"NDEF2\" 1 \"SCCM\" 0 \"EWM\" ;\nVAL_ 109 TSL_RND_Posn_StW 15 \"SNA\" 8 \"D\" 6 \"INI\" 4 \"N_DOWN\" 2 \"N_UP\" 1 \"R\" 0 \"IDLE\" ;\nVAL_ 109 TSL_P_Psd_StW 3 \"SNA\" 2 \"INI\" 1 \"PSD\" 0 \"IDLE\" ;\nVAL_ 257 GTW_epasEmergencyOn 1 \"EMERGENCY_POWER\" 0 \"NONE\" ;\nVAL_ 257 GTW_epasLDWEnabled 1 \"ALLOWED\" 0 \"INHIBITED\" ;\nVAL_ 257 GTW_epasPowerMode 0 \"DRIVE_OFF\" 1 \"DRIVE_ON\" 3 \"LOAD_SHED\" 2 \"SHUTTING_DOWN\" 15 \"SNA\" ;\nVAL_ 257 GTW_epasTuneRequest 1 \"DM_COMFORT\" 3 \"DM_SPORT\" 2 \"DM_STANDARD\" 0 \"FAIL_SAFE_DEFAULT\" 4 \"RWD_COMFORT\" 6 \"RWD_SPORT\" 5 \"RWD_STANDARD\" 7 \"SNA\" ;\nVAL_ 264 DI_torqueDriver -4096 \"SNA\" ;\nVAL_ 264 DI_torqueMotor -4096 \"SNA\" ;\nVAL_ 264 DI_soptState 7 \"SOPT_TEST_SNA\" 4 \"SOPT_TEST_NOT_RUN\" 3 \"SOPT_TEST_PASSED\" 2 \"SOPT_TEST_FAILED\" 1 \"SOPT_TEST_IN_PROGRESS\" 0 \"SOPT_PRE_TEST\" ;\nVAL_ 264 DI_motorRPM -32768 \"SNA\" ;\nVAL_ 264 DI_pedalPos 255 \"SNA\" ;\nVAL_ 280 DI_torqueEstimate -2048 \"SNA\" ;\nVAL_ 280 DI_gear 7 \"DI_GEAR_SNA\" 4 \"DI_GEAR_D\" 3 \"DI_GEAR_N\" 2 \"DI_GEAR_R\" 1 \"DI_GEAR_P\" 0 \"DI_GEAR_INVALID\" ;\nVAL_ 280 DI_brakePedal 1 \"Applied\" 0 \"Not_applied\" ;\nVAL_ 280 DI_vehicleSpeed 4095 \"SNA\" ;\nVAL_ 280 DI_gearRequest 7 \"DI_GEAR_SNA\" 4 \"DI_GEAR_D\" 3 \"DI_GEAR_N\" 2 \"DI_GEAR_R\" 1 \"DI_GEAR_P\" 0 \"DI_GEAR_INVALID\" ;\nVAL_ 280 DI_torqueInterfaceFailure 1 \"TORQUE_INTERFACE_FAILED\" 0 \"TORQUE_INTERFACE_NORMAL\" ;\nVAL_ 280 DI_brakePedalState 3 \"SNA\" 2 \"INVALID\" 1 \"ON\" 0 \"OFF\" ;\nVAL_ 280 DI_epbParkRequest 1 \"Park_requested\" 0 \"No_request\" ;\nVAL_ 280 DI_epbInterfaceReady 1 \"EPB_INTERFACE_READY\" 0 \"EPB_INTERFACE_NOT_READY\" ;\nVAL_ 309 ESP_absBrakeEvent 1 \"ACTIVE\" 0 \"NOT_ACTIVE\" ;\nVAL_ 309 ESP_brakeDiscWipingActive 1 \"ACTIVE\" 0 \"INACTIVE\" ;\nVAL_ 309 ESP_brakeLamp 0 \"OFF\" 1 \"ON\" ;\nVAL_ 309 ESP_espFaultLamp 0 \"OFF\" 1 \"ON\" ;\nVAL_ 309 ESP_espLampFlash 1 \"FLASH\" 0 \"OFF\" ;\nVAL_ 309 ESP_hillStartAssistActive 1 \"ACTIVE\" 0 \"INACTIVE\" 2 \"NOT_AVAILABLE\" 3 \"SNA\" ;\nVAL_ 309 ESP_absFaultLamp 0 \"OFF\" 1 \"ON\" ;\nVAL_ 309 ESP_espOffLamp 0 \"OFF\" 1 \"ON\" ;\nVAL_ 309 ESP_stabilityControlSts 2 \"ENGAGED\" 3 \"FAULTED\" 5 \"INIT\" 4 \"NOT_CONFIGURED\" 0 \"OFF\" 1 \"ON\" ;\nVAL_ 309 ESP_tcLampFlash 1 \"FLASH\" 0 \"OFF\" ;\nVAL_ 568 UI_mapSpeedLimit 31 \"SNA\" 30 \"UNLIMITED\" 29 \"LESS_OR_EQ_160\" 28 \"LESS_OR_EQ_150\" 27 \"LESS_OR_EQ_140\" 26 \"LESS_OR_EQ_130\" 25 \"LESS_OR_EQ_120\" 24 \"LESS_OR_EQ_115\" 23 \"LESS_OR_EQ_110\" 22 \"LESS_OR_EQ_105\" 21 \"LESS_OR_EQ_100\" 20 \"LESS_OR_EQ_95\" 19 \"LESS_OR_EQ_90\" 18 \"LESS_OR_EQ_85\" 17 \"LESS_OR_EQ_80\" 16 \"LESS_OR_EQ_75\" 15 \"LESS_OR_EQ_70\" 14 \"LESS_OR_EQ_65\" 13 \"LESS_OR_EQ_60\" 12 \"LESS_OR_EQ_55\" 11 \"LESS_OR_EQ_50\" 10 \"LESS_OR_EQ_45\" 9 \"LESS_OR_EQ_40\" 8 \"LESS_OR_EQ_35\" 7 \"LESS_OR_EQ_30\" 6 \"LESS_OR_EQ_25\" 5 \"LESS_OR_EQ_20\" 4 \"LESS_OR_EQ_15\" 3 \"LESS_OR_EQ_10\" 2 \"LESS_OR_EQ_7\" 1 \"LESS_OR_EQ_5\" 0 \"UNKNOWN\" ;\nVAL_ 522 driverBrakeStatus 2 \"APPLIED\" 1 \"NOT_APPLIED\" ;\nVAL_ 760 UI_mapSpeedLimitUnits 1 \"KPH\" 0 \"MPH\" ;\nVAL_ 760 UI_userSpeedOffsetUnits 1 \"KPH\" 0 \"MPH\" ;\nVAL_ 643 AirTemp_Insd 255 \"SNA\" ;\nVAL_ 643 AirTemp_Outsd 254 \"INIT\" 255 \"SNA\" ;\nVAL_ 643 Bckl_Sw_RL_Stat_SAM_R 2 \"FLT\" 1 \"NOT\" 0 \"OK\" 3 \"SNA\" ;\nVAL_ 643 Bckl_Sw_RM_Stat_SAM_R 2 \"FLT\" 1 \"NOT\" 0 \"OK\" 3 \"SNA\" ;\nVAL_ 643 Bckl_Sw_RR_Stat_SAM_R 2 \"FLT\" 1 \"NOT\" 0 \"OK\" 3 \"SNA\" ;\nVAL_ 643 DL_RLtch_Stat 1 \"CLS\" 0 \"NDEF0\" 2 \"OPN\" 3 \"SNA\" ;\nVAL_ 643 DrRLtch_FL_Stat 1 \"CLS\" 0 \"NDEF0\" 2 \"OPN\" 3 \"SNA\" ;\nVAL_ 643 DrRLtch_FR_Stat 1 \"CLS\" 0 \"NDEF0\" 2 \"OPN\" 3 \"SNA\" ;\nVAL_ 643 DrRLtch_RL_Stat 1 \"CLS\" 0 \"NDEF0\" 2 \"OPN\" 3 \"SNA\" ;\nVAL_ 643 DrRLtch_RR_Stat 1 \"CLS\" 0 \"NDEF0\" 2 \"OPN\" 3 \"SNA\" ;\nVAL_ 643 EngHd_Stat 1 \"CLS\" 0 \"NDEF0\" 2 \"OPN\" 3 \"SNA\" ;\nVAL_ 643 LgtSens_Night 0 \"DAY\" 1 \"NIGHT\" ;\nVAL_ 643 MPkBrk_Stat 1 \"ENGG\" 0 \"RELS\" ;\nVAL_ 643 RevGr_Engg 0 \"DISENGG\" 1 \"ENGG\" 2 \"NDEF2\" 3 \"SNA\" ;\nVAL_ 643 StW_Cond_Stat 3 \"BLINK\" 1 \"NDEF1\" 0 \"OFF\" 2 \"ON\" ;\nVAL_ 643 Trlr_Stat 2 \"NDEF2\" 0 \"NONE\" 1 \"OK\" 3 \"SNA\" ;\nVAL_ 792 BOOT_STATE 2 \"Init\" 3 \"SNA\" 0 \"closed\" 1 \"open\" ;\nVAL_ 792 CERRD 1 \"CAN error detect\" 0 \"no Can error detected\" ;\nVAL_ 792 DAY 1 \"Init\" 0 \"SNA\" ;\nVAL_ 792 DOOR_STATE_FL 2 \"Init\" 3 \"SNA\" 0 \"closed\" 1 \"open\" ;\nVAL_ 792 DOOR_STATE_FR 2 \"Init\" 3 \"SNA\" 0 \"closed\" 1 \"open\" ;\nVAL_ 792 DOOR_STATE_FrontTrunk 2 \"Init\" 3 \"SNA\" 0 \"closed\" 1 \"open\" ;\nVAL_ 792 DOOR_STATE_RL 2 \"Init\" 3 \"SNA\" 0 \"closed\" 1 \"open\" ;\nVAL_ 792 DOOR_STATE_RR 2 \"Init\" 3 \"SNA\" 0 \"closed\" 1 \"open\" ;\nVAL_ 792 GTW_updateInProgress 1 \"IN_PROGRESS\" 2 \"IN_PROGRESS_NOT_USED\" 3 \"IN_PROGRESS_SNA\" 0 \"NOT_IN_PROGRESS\" ;\nVAL_ 792 Hour 30 \"Init\" 31 \"SNA\" ;\nVAL_ 792 MCU_factoryMode 1 \"FACTORY_MODE\" 0 \"NORMAL_MODE\" ;\nVAL_ 792 MCU_transportModeOn 0 \"NORMAL_MODE\" ;\nVAL_ 792 MINUTE 62 \"Init\" 63 \"SNA\" ;\nVAL_ 792 MONTH 1 \"Init\" 15 \"SNA\" ;\nVAL_ 792 SECOND 62 \"Init\" 63 \"SNA\" ;\nVAL_ 792 YEAR 126 \"Init\" 127 \"SNA\" ;\nVAL_ 872 DI_aebState 2 \"ENABLED\" 4 \"FAULT\" 7 \"SNA\" 1 \"STANDBY\" 3 \"STANDSTILL\" 0 \"UNAVAILABLE\" ;\nVAL_ 872 DI_analogSpeed 4095 \"SNA\" ;\nVAL_ 872 DI_cruiseState 2 \"ENABLED\" 5 \"FAULT\" 0 \"OFF\" 4 \"OVERRIDE\" 7 \"PRE_CANCEL\" 6 \"PRE_FAULT\" 1 \"STANDBY\" 3 \"STANDSTILL\" ;\nVAL_ 872 DI_digitalSpeed 255 \"SNA\" ;\nVAL_ 872 DI_immobilizerState 2 \"AUTHENTICATING\" 3 \"DISARMED\" 6 \"FAULT\" 4 \"IDLE\" 0 \"INIT_SNA\" 1 \"REQUEST\" 5 \"RESET\" ;\nVAL_ 872 DI_speedUnits 1 \"KPH\" 0 \"MPH\" ;\nVAL_ 872 DI_state 3 \"ABORT\" 4 \"ENABLE\" 2 \"FAULT\" 1 \"STANDBY\" 0 \"UNAVAILABLE\" ;\nVAL_ 872 DI_systemState 3 \"ABORT\" 4 \"ENABLE\" 2 \"FAULT\" 1 \"STANDBY\" 0 \"UNAVAILABLE\" ;\nVAL_ 872 DI_vehicleHoldState 2 \"BLEND_IN\" 4 \"BLEND_OUT\" 6 \"FAULT\" 7 \"INIT\" 5 \"PARK\" 1 \"STANDBY\" 3 \"STANDSTILL\" 0 \"UNAVAILABLE\" ;\nVAL_ 880 EPAS_currentTuneMode 1 \"DM_COMFORT\" 3 \"DM_SPORT\" 2 \"DM_STANDARD\" 0 \"FAIL_SAFE_DEFAULT\" 4 \"RWD_COMFORT\" 6 \"RWD_SPORT\" 5 \"RWD_STANDARD\" 7 \"UNAVAILABLE\" ;\nVAL_ 880 EPAS_eacErrorCode 14 \"EAC_ERROR_EPB_INHIBIT\" 3 \"EAC_ERROR_HANDS_ON\" 7 \"EAC_ERROR_HIGH_ANGLE_RATE_REQ\" 9 \"EAC_ERROR_HIGH_ANGLE_RATE_SAFETY\" 6 \"EAC_ERROR_HIGH_ANGLE_REQ\" 8 \"EAC_ERROR_HIGH_ANGLE_SAFETY\" 10 \"EAC_ERROR_HIGH_MMOT_SAFETY\" 11 \"EAC_ERROR_HIGH_TORSION_SAFETY\" 0 \"EAC_ERROR_IDLE\" 12 \"EAC_ERROR_LOW_ASSIST\" 2 \"EAC_ERROR_MAX_SPEED\" 1 \"EAC_ERROR_MIN_SPEED\" 13 \"EAC_ERROR_PINION_VEL_DIFF\" 4 \"EAC_ERROR_TMP_FAULT\" 5 \"EAR_ERROR_MAX_STEER_DELTA\" 15 \"SNA\" ;\nVAL_ 880 EPAS_eacStatus 2 \"EAC_ACTIVE\" 1 \"EAC_AVAILABLE\" 3 \"EAC_FAULT\" 0 \"EAC_INHIBITED\" 4 \"SNA\" ;\nVAL_ 880 EPAS_handsOnLevel 0 \"0\" 1 \"1\" 2 \"2\" 3 \"3\" ;\nVAL_ 880 EPAS_steeringFault 1 \"FAULT\" 0 \"NO_FAULT\" ;\nVAL_ 880 EPAS_steeringRackForce 1022 \"NOT_IN_SPEC\" 1023 \"SNA\" ;\nVAL_ 880 EPAS_steeringReduced 0 \"NORMAL_ASSIST\" 1 \"REDUCED_ASSIST\" ;\nVAL_ 880 EPAS_torsionBarTorque 0 \"SEE_SPECIFICATION\" 4095 \"SNA\" 4094 \"UNDEFINABLE_DATA\" ;\nVAL_ 904 MCU_clusterReadyForDrive 0 \"NO_SNA\" 1 \"YES\" ;\nVAL_ 921 autopilotStatus 5 \"ACTIVE_NAVIGATE_ON_AUTOPILOT\" 4 \"ACTIVE_2\" 3 \"ACTIVE_1\" 2 \"AVAILABLE\" 1 \"UNAVAILABLE\" 0 \"DISABLED\" ;\nVAL_ 1160 DAS_steeringAngleRequest 16384 \"ZERO_ANGLE\" ;\nVAL_ 1160 DAS_steeringControlType 1 \"ANGLE_CONTROL\" 3 \"DISABLED\" 0 \"NONE\" 2 \"RESERVED\" ;\nVAL_ 1160 DAS_steeringHapticRequest 1 \"ACTIVE\" 0 \"IDLE\" ;\n\n\nCM_ \"CHFFR_METRIC 1160 DAS_steeringAngleRequest STEER_ANGLE 0.1098666 180; CHFFR_METRIC 264 DI_motorRPM ENGINE_RPM 1 0\";\n"
  },
  {
    "path": "opendbc/tesla_radar.dbc",
    "content": "VERSION \"\"\n\n\nNS_ : \n\tNS_DESC_\n\tCM_\n\tBA_DEF_\n\tBA_\n\tVAL_\n\tCAT_DEF_\n\tCAT_\n\tFILTER\n\tBA_DEF_DEF_\n\tEV_DATA_\n\tENVVAR_DATA_\n\tSGTYPE_\n\tSGTYPE_VAL_\n\tBA_DEF_SGTYPE_\n\tBA_SGTYPE_\n\tSIG_TYPE_REF_\n\tVAL_TABLE_\n\tSIG_GROUP_\n\tSIG_VALTYPE_\n\tSIGTYPE_VALTYPE_\n\tBO_TX_BU_\n\tBA_DEF_REL_\n\tBA_REL_\n\tBA_DEF_DEF_REL_\n\tBU_SG_REL_\n\tBU_EV_REL_\n\tBU_BO_REL_\n\tSG_MUL_VAL_\n\nBS_:\n\nBU_:  FrontCamera Radar\n\n\nBO_ 769 TeslaRadarSguInfo: 8 Radar\n SG_ RADC_VerticalMisalignment : 0|8@1+ (1,0) [0|255] \"\"  FrontCamera\n SG_ RADC_SCUTemperature : 8|8@1+ (1,-128) [-128|127] \"\"  FrontCamera\n SG_ RADC_VMA_Plaus : 16|8@1+ (1,0) [0|255] \"\"  FrontCamera\n SG_ RADC_SGU_ITC : 24|8@1+ (1,0) [0|255] \"\"  FrontCamera\n SG_ RADC_HorizontMisalignment : 32|12@1+ (1,0) [0|4096] \"\"  FrontCamera\n SG_ RADC_SensorDirty : 44|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_HWFail : 45|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_SGUFail : 46|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_SGUInfoConsistBit : 47|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 770 TeslaRadarTguInfo: 8 Radar\n SG_ RADC_ACCTargObj1_sguIndex : 0|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ RADC_ACCTargObj2_sguIndex : 6|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ RADC_ACCTargObj3_sguIndex : 12|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ RADC_ACCTargObj4_sguIndex : 18|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ RADC_ACCTargObj5_sguIndex : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ unused30 : 30|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_TGUInfoConsistBit : 31|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_ACCTargObj1_dBPower : 32|16@1+ (1,0) [0|65535] \"\"  FrontCamera\n SG_ RADC_ACCTargObj5_dBPower : 48|16@1+ (1,0) [0|65535] \"\"  FrontCamera\n\nBO_ 1281 TeslaRadarAlertMatrix: 8 Radar\n SG_ RADC_a001_ecuInternalPerf : 0|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a002_flashPerformance : 1|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a003_vBatHigh : 2|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a004_adjustmentNotDone : 3|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a005_adjustmentReq : 4|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a006_adjustmentNotOk : 5|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a007_sensorBlinded : 6|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a008_plantModeActive : 7|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a009_configMismatch : 8|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a010_canBusOff : 9|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a011_bdyMIA : 10|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a012_espMIA : 11|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a013_gtwMIA : 12|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a014_sccmMIA : 13|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a015_adasMIA : 14|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a016_bdyInvalidCount : 15|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a017_adasInvalidCount : 16|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a018_espInvalidCount : 17|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a019_sccmInvalidCount : 18|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a020_bdyInvalidChkSm : 19|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a021_espInvalidChkSm : 20|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a022_sccmInvalidChkSm : 21|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a023_sccmInvalidChkSm : 22|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a024_absValidity : 23|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a025_ambTValidity : 24|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a026_brakeValidity : 25|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a027_CntryCdValidity : 26|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a028_espValidity : 27|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a029_longAccOffValidity : 28|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a030_longAccValidity : 29|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a031_odoValidity : 30|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a032_gearValidity : 31|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a033_steerAngValidity : 32|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a034_steerAngSpdValidity : 33|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a035_indctrValidity : 34|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a036_vehStandStillValidity : 35|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a037_vinValidity : 36|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a038_whlRotValidity : 37|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a039_whlSpdValidity : 38|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a040_whlStandStillValidity : 39|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a041_wiperValidity : 40|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a042_xwdValidity : 41|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a043_yawOffValidity : 42|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a044_yawValidity : 43|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a045_bsdSanity : 44|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a046_rctaSanity : 45|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a047_lcwSanity : 46|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a048_steerAngOffSanity : 47|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a049_tireSizeSanity : 48|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a050_velocitySanity : 49|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a051_yawSanity : 50|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a052_radomeHtrInop : 51|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a053_espmodValidity : 52|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a054_gtwmodValidity : 53|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a055_stwmodValidity : 54|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a056_bcmodValidity : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a057_dimodValidity : 56|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a058_opmodValidity : 57|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a059_drmiInvalidChkSm : 58|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a060_drmiInvalidCount : 59|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a061_radPositionMismatch : 60|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ RADC_a062_strRackMismatch : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ unused62 : 62|2@1+ (1,0) [0|3] \"\"  FrontCamera\n\nBO_ 784 M_310hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 785 M_310hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 787 M_313hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 788 M_313hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 790 M_316hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 791 M_316hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 793 M_319hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 794 M_319hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 796 M_31Chex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 797 M_31Chex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 799 M_31Fhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 800 M_31Fhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 802 M_322hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 803 M_322hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 805 M_325hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 806 M_325hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 808 M_328hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 809 M_328hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 811 M_32Bhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 812 M_32Bhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 814 M_32Ehex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 815 M_32Ehex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 817 M_331hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 818 M_331hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 820 M_334hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 821 M_334hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 823 M_337hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 824 M_337hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 826 M_33Ahex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 827 M_33Ahex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 829 M_33Dhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 830 M_33Dhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 832 M_340hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 833 M_340hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 835 M_343hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 836 M_343hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 838 M_346hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 839 M_346hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 841 M_349hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 842 M_349hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 844 M_34Chex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 845 M_34Chex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 847 M_34Fhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 848 M_34Fhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 850 M_352hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 851 M_352hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 853 M_355hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 854 M_355hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 856 M_358hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 857 M_358hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 859 M_35Bhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 860 M_35Bhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 862 M_35Ehex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 863 M_35Ehex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 865 M_361hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 866 M_361hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 868 M_364hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 869 M_364hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 871 M_367hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 872 M_367hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 874 M_36Ahex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 875 M_36Ahex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 877 M_36Dhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 878 M_36Dhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 881 L_1_371hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 882 L_1_371hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 884 L_2_374hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 885 L_2_375hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 887 L_3_377hex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 888 L_3_378hex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 890 L_4_37ahex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 891 L_4_37ahex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 893 L_5_37dhex: 8 Radar\n SG_ LongDist : 0|12@1+ (0.0625,0) [0|255.9] \"meters\"  FrontCamera\n SG_ LongSpeed : 12|12@1+ (0.0625,-128) [-128|128] \"meters/sec\"  FrontCamera\n SG_ LatDist : 24|11@1+ (0.125,-128) [-128|128] \"meters\"  FrontCamera\n SG_ ProbExist : 35|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ LongAccel : 40|10@1+ (0.03125,-16) [-16|16] \"meters/sec/sec\"  FrontCamera\n SG_ ProbObstacle : 50|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Valid : 55|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ ProbNonObstacle : 56|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Meas : 61|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Tracked : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 894 L_5_37dhex2: 8 Radar\n SG_ LatSpeed : 0|10@1+ (0.125,-64) [-64|64] \"meters/sec\"  FrontCamera\n SG_ Length : 10|6@1+ (0.125,0) [0|7.875] \"m\"  FrontCamera\n SG_ dZ : 16|6@1+ (0.25,-5) [-5|10.75] \"m\"  FrontCamera\n SG_ MovingState : 22|2@1+ (1,0) [0|3] \"\"  FrontCamera\n SG_ dxSigma : 24|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ vxSigma : 30|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ axSigma : 36|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ dySigma : 42|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ ProbClass : 48|5@1+ (3.125,0) [0|96.875] \"%\"  FrontCamera\n SG_ Class : 53|3@1+ (1,0) [0|7] \"\"  FrontCamera\n SG_ dxRearEndLoss : 56|6@1+ (1,0) [0|63] \"\"  FrontCamera\n SG_ NotUsed : 62|1@1+ (1,0) [0|1] \"\"  FrontCamera\n SG_ Index2 : 63|1@1+ (1,0) [0|1] \"\"  FrontCamera\n\nBO_ 697 VIN_VIP_405HS: 8 FrontCamera\n SG_ VIN_MuxID M : 0|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ VIN_Part1 m16 : 47|24@0+ (1,0) [0|16777215] \"\" Radar\n SG_ VIN_Part2 m17 : 15|56@0+ (1,0) [0|7.2057594038E+16] \"\" Radar\n SG_ VIN_Part3 m18 : 15|56@0+ (1,0) [0|7.2057594038E+16] \"\" Radar\n\nBO_ 681 Msg2A9_GTW_carConfig: 8 FrontCamera\n SG_ Msg2A9_Always0x02 : 48|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2A9_Always0x10 : 56|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2A9_Always0x16 : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2A9_Always0x41 : 24|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2A9_Value1_0x02 : 0|3@1+ (1,0) [0|0] \"\" Radar\n SG_ Msg2A9_FourWheelDrive : 3|2@1+ (1,0) [0|0] \"\" Radar  \n SG_ Msg2A9_Value2_0x02 : 5|3@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2A9_Always0x43 : 16|8@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 409 Msg199_STW_ANGLHP_STAT: 8 FrontCamera\n SG_ Msg199Always0x04 : 32|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg199Always0x20 : 16|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg199Always0x2F : 0|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg199Always0x67 : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg199Always0xFF : 40|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg199Checksum : 56|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg199Counter : 52|4@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 361 Msg169_ESP_wheelSpeeds: 8 FrontCamera\n SG_ ESP_wheelSpeedFrL_HS : 0|13@1+ (0.04,0) [0|327.64] \"km/h\" Radar\n SG_ ESP_wheelSpeedFrR_HS : 13|13@1+ (0.04,0) [0|327.64] \"km/h\" Radar\n SG_ ESP_wheelSpeedReL_HS : 26|13@1+ (0.04,0) [0|327.64] \"km/h\" Radar\n SG_ ESP_wheelSpeedReR_HS : 39|13@1+ (0.04,0) [0|327.64] \"km/h\" Radar\n SG_ Msg169Checksum : 56|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg169Counter : 52|4@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 345 Msg159_ESP_C: 8 FrontCamera\n SG_ Msg159Always0x3A : 16|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg159Always0xA5 : 0|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg159Always0xCF : 32|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg159Always0xF4 : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg159Counter : 44|4@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg159Checksum : 24|8@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 329 Msg149_ESP_145h: 8 FrontCamera\n SG_ Msg149Always0x02 : 16|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Always0x04 : 40|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Always0x26 : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Always0x6A : 24|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Always0xAA : 32|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Always0xF : 48|4@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Checksum : 56|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg149Counter : 52|4@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 297 Msg129_ESP_115h: 6 FrontCamera\n SG_ Msg129Always0x20 : 24|8@1+ (1,0) [0|0] \"\" Radar\n SG_ Msg129Checksum : 40|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg129Counter : 36|4@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 281 Msg119_DI_torque2: 6 FrontCamera\n SG_ Msg119Always0x11 : 24|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg119Always0x1F : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg119Always0x8 : 36|4@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg119Always0xF4 : 16|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg119Always0xFF : 0|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg119Checksum : 40|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg119Counter : 32|4@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 265 Msg109_DI_torque1: 8 FrontCamera\n SG_ Msg109Always0x80 : 24|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg109Checksum : 56|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg109Counter : 13|3@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 521 Msg209_GTW_odo: 8 FrontCamera\n SG_ Msg209Always0x61 : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg209Always0x94 : 16|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg209Always0x52 : 24|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg209Always0x13 : 32|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg209Always0x03 : 40|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg209Always0x80 : 48|8@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 537 Msg219_STW_ACTN_RQ: 8 FrontCamera\n SG_ Msg219Counter : 52|4@1+ (1,0) [0|15] \"\" Radar\n SG_ Msg219CRC : 56|8@1+ (1,0) [0|0] \"\" Radar\n\nBO_ 425 Msg1A9_DI_espControl: 5 FrontCamera\n SG_ Msg1A9Always0x0C : 16|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg1A9Counter : 28|4@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg1A9Checksum : 32|8@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 729 Msg2D9_BC_status : 8 FrontCamera\n SG_ Msg2D9Always0x80 : 0|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2D9Always0x40 : 8|8@1+ (1,0) [0|0] \"\"  Radar\n SG_ Msg2D9Always0x83 : 16|8@1+ (1,0) [0|0] \"\"  Radar\n\nBO_ 1601 UDS_radarRequest: 8 FrontCamera\n SG_ UDS_radarRequestData : 7|64@0+ (1,0) [0|0] \"\" Radar\n\nBO_ 1617 Radar_udsResponse: 8 Radar\n SG_ Radar_udsResponseData : 7|64@0+ (1,0) [0|0] \"\" FrontCamera\n\nCM_ BO_ 697 \"Start with MuxID 0x12, then 0x11 and finally 0x10 (VIN is then transmitted in the reverse order)\";\nCM_ BO_ 681 \"Message sent every 1000 ms. All fixed bytes, no checksum, the byte for RWD or AWD needs to match VIN config\";\nCM_ BO_ 409 \"Message sent every 10ms. Checksum : use all first 7 bytes with the SAE J1850 CRC algo\";\nCM_ BO_ 361 \"Message sent every 10ms. Checksum : Sum of all first 7 bytes + 0x76\";\nCM_ BO_ 345 \"Message sent every 20ms. Checksum : Sum of all first bytes + 0xc; place checksum in 4th octet\";\nCM_ BO_ 329 \"Message sent every 20ms. Checksum : Sum of all first 7 bytes + 0x46\";\nCM_ BO_ 297 \"Message sent every 20ms. Checksum : Sum of all first 5 bytes + 0x16\";\nCM_ BO_ 281 \"Message sent every 10ms. Checksum : Sum of all first 5 bytes + 0x17\";\nCM_ BO_ 265 \"Message sent every 10ms. Checksum : Sum of all first 7 bytes + 0x7\";\nCM_ BO_ 521 \"Message sent every 100ms. All fixed bytes, no checksum.\";\nCM_ BO_ 537 \"Message sent every 100ms. Checksum : use all first 7 bytes with the SAE J1850 CRC algo\";\nCM_ BO_ 425 \"Message sent every 20ms. Checksum : Sum of all first 4 bytes + 0x38\";\nCM_ BO_ 729 \"Message sent every 1000ms. All fixed bytes, no checksum.\";\n\nBA_DEF_ \"BusType\" STRING ;\nBA_DEF_ BO_ \"GenMsgCycleTime\" INT 0 0;\nBA_DEF_ SG_ \"FieldType\" STRING ;\n\nBA_DEF_DEF_ \"BusType\" \"CAN\";\nBA_DEF_DEF_ \"FieldType\" \"\";\nBA_DEF_DEF_ \"GenMsgCycleTime\" 0;\n\nBA_ \"GenMsgCycleTime\" BO_ 697 250;\nBA_ \"GenMsgCycleTime\" BO_ 681 1000;\nBA_ \"GenMsgCycleTime\" BO_ 409 10;\nBA_ \"GenMsgCycleTime\" BO_ 361 10;\nBA_ \"GenMsgCycleTime\" BO_ 345 20;\nBA_ \"GenMsgCycleTime\" BO_ 329 20;\nBA_ \"GenMsgCycleTime\" BO_ 297 20;\nBA_ \"GenMsgCycleTime\" BO_ 281 10;\nBA_ \"GenMsgCycleTime\" BO_ 265 10;\nBA_ \"GenMsgCycleTime\" BO_ 521 100;\nBA_ \"GenMsgCycleTime\" BO_ 537 100;\nBA_ \"GenMsgCycleTime\" BO_ 425 20;\nBA_ \"GenMsgCycleTime\" BO_ 729 1000;\n\nVAL_ 681 Msg2A9_FourWheelDrive 3 \"SNA\" 2 \"UNUSED\" 1 \"4WD\" 0 \"2WD\" ;\nVAL_ 785 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 785 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 788 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 788 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 791 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 791 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 794 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 794 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 797 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 797 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 800 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 800 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 803 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 803 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 806 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 806 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 809 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 809 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 812 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 812 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 815 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 815 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 818 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 818 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 821 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 821 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 824 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 824 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 827 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 827 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 830 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 830 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 833 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 833 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 836 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 836 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 839 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 839 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 842 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 842 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 845 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 845 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 848 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 848 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 851 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 851 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 854 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 854 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 857 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 857 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 860 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 860 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 863 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 863 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 866 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 866 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 869 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 869 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 872 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 872 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 875 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 875 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 878 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 878 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 882 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 882 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 885 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 885 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 888 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 888 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 891 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 891 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\nVAL_ 894 MovingState 3 \"RADAR_MOVESTATE_STANDING\" 2 \"RADAR_MOVESTATE_STOPPED\" 1 \"RADAR_MOVESTATE_MOVING\" 0 \"RADAR_MOVESTATE_INDETERMINATE\" ;\nVAL_ 894 Class 4 \"RADAR_CLASS_CONSTRUCTION_ELEMENT\" 3 \"RADAR_CLASS_MOVING_PEDESTRIAN\" 2 \"RADAR_CLASS_MOVING_TWO_WHEEL_VEHICLE\" 1 \"RADAR_CLASS_MOVING_FOUR_WHEEL_VEHICLE\" 0 \"RADAR_CLASS_UNKNOWN\" ;\n\n"
  },
  {
    "path": "opendbc/toyota_adas.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\nBO_ 528 TRACK_A_0: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 529 TRACK_A_1: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 530 TRACK_A_2: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 531 TRACK_A_3: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 532 TRACK_A_4: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 533 TRACK_A_5: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 534 TRACK_A_6: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 535 TRACK_A_7: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 536 TRACK_A_8: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 537 TRACK_A_9: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 538 TRACK_A_10: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 539 TRACK_A_11: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 540 TRACK_A_12: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 541 TRACK_A_13: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 542 TRACK_A_14: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 543 TRACK_A_15: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 544 TRACK_B_0: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 545 TRACK_B_1: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 546 TRACK_B_2: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 547 TRACK_B_3: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 548 TRACK_B_4: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 549 TRACK_B_5: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 550 TRACK_B_6: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 551 TRACK_B_7: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 TRACK_B_8: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 553 TRACK_B_9: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 554 TRACK_B_10: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 555 TRACK_B_11: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 556 TRACK_B_12: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 557 TRACK_B_13: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 558 TRACK_B_14: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 559 TRACK_B_15: 6 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 47|8@0+ (1,0) [0|255] \"\" XXX\n"
  },
  {
    "path": "opendbc/toyota_avalon_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_avalon_2017_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|65535] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_camry_hybrid_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_camry_hybrid_2018_pt.dbc starts here\";\n\n\n\nBO_ 295 GEAR_PACKET: 8 XXX\n SG_ CAR_MOVEMENT : 39|8@0- (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ GEAR : 47|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 8 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 8 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 295 GEAR 0 \"P\" 1 \"R\" 2 \"N\" 3 \"D\" 4 \"B\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_corolla_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_corolla_2017_pt.dbc starts here\";\n\n\n\nBO_ 548 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 43|12@0+ (1,0) [0|4047] \"\" XXX\n SG_ BRAKE_PRESSED : 5|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.88,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SPORT_ON : 3|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_highlander_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_highlander_2017_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|65535] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_highlander_hybrid_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_highlander_hybrid_2018_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\n"
  },
  {
    "path": "opendbc/toyota_nodsu_hybrid_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 956 GEAR_PACKET2: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SPORT_GEAR_ON : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SPORT_GEAR : 38|3@0+ (1,0) [0|7] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_ENGAGED : 47|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 36 \"speed sign mph\" 1 \"speed sign kph\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 6 \"snow\" 5 \"rain\" 4 \"wet road\" 5 \"rain\" 3 \"left\" 2 \"right\" 1 \"time\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\n\nCM_ \"Imported file _toyota_nodsu_common.dbc starts here\";\nBO_ 401 STEERING_LTA: 8 XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SETME_X3 : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ PERCENTAGE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SETME_X64 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ANGLE : 55|8@0- (0.5,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE_CMD : 15|16@0- (0.0573,0) [-540|540] \"\" XXX\n SG_ STEER_REQUEST : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST_2 : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SETME_X1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1014 BSM: 8 XXX\n SG_ L_ADJACENT : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ L_APPROACHING : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ R_ADJACENT : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ R_APPROACHING : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJACENT_ENABLED : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ APPROACHING_ENABLED : 15|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 1014 L_ADJACENT \"vehicle adjacent left side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 L_APPROACHING \"vehicle approaching from left side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 R_ADJACENT \"vehicle adjacent right side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 R_APPROACHING \"vehicle approaching from right side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 ADJACENT_ENABLED \"when BSM is enabled in settings, this is on along with APPROACHING_ENABLED. this controls bsm alert visibility\";\nCM_ SG_ 1014 APPROACHING_ENABLED \"when BSM is enabled in settings, this is on along with ADJACENT_ENABLED. this controls bsm alert visibility\";\n\nCM_ \"toyota_nodsu_hybrid_pt.dbc starts here\";\n\n\n\n\nBO_ 295 GEAR_PACKET: 8 XXX\n SG_ CAR_MOVEMENT : 39|8@0- (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ GEAR : 47|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 8 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 8 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nVAL_ 295 GEAR 0 \"P\" 1 \"R\" 2 \"N\" 3 \"D\" 4 \"B\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_nodsu_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\n\nCM_ \"Imported file _toyota_nodsu_common.dbc starts here\";\nBO_ 401 STEERING_LTA: 8 XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SETME_X3 : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ PERCENTAGE : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SETME_X64 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ANGLE : 55|8@0- (0.5,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE_CMD : 15|16@0- (0.0573,0) [-540|540] \"\" XXX\n SG_ STEER_REQUEST : 25|1@0+ (1,0) [0|1] \"\" XXX\n SG_ BIT : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST_2 : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SETME_X1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1014 BSM: 8 XXX\n SG_ L_ADJACENT : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ L_APPROACHING : 8|1@0+ (1,0) [0|1] \"\" XXX\n SG_ R_ADJACENT : 1|1@0+ (1,0) [0|1] \"\" XXX\n SG_ R_APPROACHING : 10|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJACENT_ENABLED : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ APPROACHING_ENABLED : 15|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 1014 L_ADJACENT \"vehicle adjacent left side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 L_APPROACHING \"vehicle approaching from left side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 R_ADJACENT \"vehicle adjacent right side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 R_APPROACHING \"vehicle approaching from right side of car. enabled above 10mph, regardless of ADJACENT_ENABLED or APPROACHING_ENABLED\";\nCM_ SG_ 1014 ADJACENT_ENABLED \"when BSM is enabled in settings, this is on along with APPROACHING_ENABLED. this controls bsm alert visibility\";\nCM_ SG_ 1014 APPROACHING_ENABLED \"when BSM is enabled in settings, this is on along with ADJACENT_ENABLED. this controls bsm alert visibility\";\n\nCM_ \"toyota_nodsu_pt.dbc starts here\";\n\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 8 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SPORT_ON_2 : 55|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\nVAL_ 956 SPORT_ON_2 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/toyota_prius_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_prius_2017_pt.dbc starts here\";\n\n\n\nBO_ 295 GEAR_PACKET: 8 XXX\n SG_ CAR_MOVEMENT : 39|8@0- (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ GEAR : 47|4@0+ (1,0) [0|15] \"\" XXX\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 8 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.66,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX \n\nBO_ 610 EPS_STATUS: 8 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 1083 AUTOPARK_STATUS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nCM_ SG_ 1083 STATE \"when the dashboard button is pressed, the value changes from zero to non-zero\";\nVAL_ 295 GEAR 0 \"P\" 1 \"R\" 2 \"N\" 3 \"D\" 4 \"B\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_prius_alpha_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_prius_alpha_2017_pt_generated.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/toyota_rav4_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_rav4_2017_pt.dbc starts here\";\n\n\n\nBO_ 548 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 43|12@0+ (1,0) [0|4047] \"\" XXX\n SG_ BRAKE_PRESSED : 5|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\n"
  },
  {
    "path": "opendbc/toyota_rav4_hybrid_2017_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_rav4_hybrid_2017_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|511] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 581 GAS_PEDAL: 5 XXX\n SG_ GAS_PEDAL : 23|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ SPORT_ON : 2|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SPORT_GEAR_ON : 33|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SPORT_GEAR : 38|3@0+ (1,0) [0|7] \"\" XXX\n SG_ ECON_ON : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DRIVE_ENGAGED : 47|1@0+ (1,0) [0|1] \"\" XXX\n\n\n\nCM_ SG_ 550 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 550 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 581 GAS_PEDAL \"it seems slightly filtered\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\";\nVAL_ 956 SPORT_ON 0 \"off\" 1 \"on\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 956 SPORT_GEAR_ON 0 \"off\" 1 \"on\";\nVAL_ 956 SPORT_GEAR 1 \"S1\" 2 \"S2\" 3 \"S3\" 4 \"S4\" 5 \"S5\" 6 \"S6\";\nVAL_ 956 ECON_ON 0 \"off\" 1 \"on\";\nVAL_ 956 DRIVE_ENGAGED 0 \"off\" 1 \"on\";\n"
  },
  {
    "path": "opendbc/toyota_sienna_xle_2018_pt_generated.dbc",
    "content": "CM_ \"AUTOGENERATED FILE, DO NOT EDIT\";\n\n\nCM_ \"Imported file _toyota_2017.dbc starts here\";\nVERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX DSU HCU EPS IPAS CGW\n\nBO_ 36 KINEMATICS: 8 XXX\n SG_ ACCEL_Y : 33|10@0+ (0.03589,-18.375) [0|65535] \"m/s^2\" XXX\n SG_ YAW_RATE : 1|10@0+ (0.244,-125) [0|65535] \"deg/sec\" XXX\n SG_ STEERING_TORQUE : 17|10@0+ (1,-512) [0|65535] \"\" XXX\n\nBO_ 37 STEER_ANGLE_SENSOR: 8 XXX\n SG_ STEER_ANGLE : 3|12@0- (1.5,0) [-500|500] \"deg\" XXX\n SG_ STEER_FRACTION : 39|4@0- (0.1,0) [-0.7|0.7] \"deg\" XXX\n SG_ STEER_RATE : 35|12@0- (1,0) [-2000|2000] \"deg/s\" XXX\n\nBO_ 166 BRAKE: 8 XXX\n SG_ BRAKE_AMOUNT : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_PEDAL : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 170 WHEEL_SPEEDS: 8 XXX\n SG_ WHEEL_SPEED_FR : 7|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_FL : 23|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RR : 39|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n SG_ WHEEL_SPEED_RL : 55|16@0+ (0.01,-67.67) [0|250] \"kph\" XXX\n\nBO_ 180 SPEED: 8 XXX\n SG_ ENCODER : 39|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SPEED : 47|16@0+ (0.01,0) [0|250] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 353 DSU_SPEED: 7 XXX\n SG_ FORWARD_SPEED : 15|16@0- (0.00390625,-30) [0|255] \"kph\" XXX\n\nBO_ 452 ENGINE_RPM: 8 CGW\n SG_ RPM : 7|16@0- (0.78125,0) [0|0] \"rpm\" SCS\n\nBO_ 466 PCM_CRUISE: 8 XXX\n SG_ GAS_RELEASED : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_ACTIVE : 5|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STANDSTILL_ON : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ACCEL_NET : 23|16@0- (0.001,0) [-20|20] \"m/s2\" XXX\n SG_ CRUISE_STATE : 55|4@0+ (1,0) [0|15] \"\" XXX\n SG_ CANCEL_REQ : 49|1@1+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 467 PCM_CRUISE_2: 8 XXX\n SG_ MAIN_ON : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_SPEED_LOCKOUT : 14|2@0+ (1,0) [0|3] \"kph\" XXX\n SG_ SET_SPEED : 23|8@0+ (1,0) [0|255] \"kph\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 552 ACCELEROMETER: 8 XXX\n SG_ ACCEL_Z : 22|15@0- (1,0) [0|32767] \"\" XXX\n SG_ ACCEL_X : 6|15@0- (0.001,0) [-20|20] \"m/s2\" XXX\n\nBO_ 560 BRAKE_MODULE2: 7 XXX\n SG_ BRAKE_PRESSED : 26|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 614 STEERING_IPAS: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 643 PRE_COLLISION: 7 DSU\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 15|8@0+ (1,0) [0|255] \"\" XXX\n SG_ FORCE : 23|16@0- (2,0) [0|255] \"N\" XXX\n SG_ SET_ME_X002 : 33|8@0+ (1,0) [0|3] \"\" XXX\n SG_ BRAKE_STATUS : 39|3@0+ (1,0) [0|255] \"\" XXX\n SG_ STATE : 36|3@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X003 : 40|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PRECOLLISION_ACTIVE : 41|1@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 55|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 740 STEERING_LKA: 5 XXX\n SG_ LKA_STATE : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_REQUEST : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ COUNTER : 6|6@0+ (1,0) [0|63] \"\" XXX\n SG_ SET_ME_1 : 7|1@0+ (1,0) [0|1] \"\" XXX\n SG_ STEER_TORQUE_CMD : 15|16@0- (1,0) [0|65535] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 742 LEAD_INFO: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" HCU\n SG_ LEAD_REL_SPEED : 23|12@0- (0.025,0) [-100|100] \"m/s\" HCU\n SG_ LEAD_LONG_DIST : 7|13@0+ (0.05,0) [0|300] \"m\" HCU\n\nBO_ 835 ACC_CONTROL: 8 DSU\n SG_ ACCEL_CMD : 7|16@0- (0.001,0) [-20|20] \"m/s2\" HCU\n SG_ ACC_TYPE : 23|2@0+ (1,0) [0|3] \"\" HCU\n SG_ DISTANCE : 20|1@0+ (1,0) [0|1] \"\" XXX\n SG_ MINI_CAR : 21|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X3 : 19|4@0+ (1,0) [0|15] \"\" XXX\n SG_ PERMIT_BRAKING : 30|1@0+ (1,0) [0|1] \"\" HCU\n SG_ RELEASE_STANDSTILL : 31|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CANCEL_REQ : 24|1@0+ (1,0) [0|1] \"\" HCU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ ACCEL_CMD_ALT : 47|8@0- (0.05,0) [0|0] \"m/s^2\" XXX\n\nBO_ 836 PRE_COLLISION_2: 8 DSU\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 869 DSU_CRUISE : 7 DSU\n SG_ RES_BTN : 3|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_BTN : 2|1@0+ (1,0) [0|0] \"\" XXX\n SG_ CANCEL_BTN : 1|1@0+ (1,0) [0|0] \"\" XXX\n SG_ MAIN_ON : 0|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SET_SPEED : 15|8@0+ (1,0) [0|0] \"km/h\" XXX\n SG_ CRUISE_REQUEST : 31|8@0+ (100,-12800) [0|0] \"N\" XXX\n SG_ LEAD_DISTANCE : 39|8@0+ (1,0) [0|0] \"m\" XXX\n\nBO_ 921 PCM_CRUISE_SM: 8 XXX\n SG_ MAIN_ON : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CRUISE_CONTROL_STATE : 11|4@0+ (1,0) [0|15] \"\" XXX\n SG_ DISTANCE_LINES : 14|2@0+ (1,0) [0|3] \"\" XXX\n SG_ UI_SET_SPEED : 31|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 951 ESP_CONTROL: 8 ESP\n SG_ TC_DISABLED : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ VSC_DISABLED : 12|2@0+ (1,0) [0|1] \"\" XXX\n SG_ BRAKE_LIGHTS_ACC : 18|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1020 SOLAR_SENSOR: 8 XXX\n SG_ LUX_SENSOR : 55|13@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1041 ACC_HUD: 8 DSU\n SG_ FCW : 4|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X20 : 15|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X10 : 39|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X80 : 55|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1042 LKAS_HUD: 8 XXX\n SG_ BARRIERS : 1|2@0+ (1,0) [0|3] \"\" XXX\n SG_ RIGHT_LINE : 3|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LEFT_LINE : 5|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01 : 7|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X01_2 : 11|2@0+ (1,0) [0|3] \"\" XXX\n SG_ LDA_ALERT : 9|2@0+ (1,0) [0|3] \"\" XXX\n SG_ TWO_BEEPS : 12|1@0+ (1,0) [0|1] \"\" XXX\n SG_ ADJUSTING_CAMERA : 13|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LDA_MALFUNCTION : 15|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REPEATED_BEEPS : 32|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X0C : 23|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X2C : 47|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X38 : 55|8@0+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_X02 : 63|8@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1043 TIME : 8 CGW\n SG_ YEAR : 7|8@0+ (1,0) [0|0] \"year\" XXX\n SG_ MONTH : 15|8@0+ (1,0) [0|0] \"month\" XXX\n SG_ DAY : 23|8@0+ (1,0) [0|0] \"day\" XXX\n SG_ HOUR : 31|8@0+ (1,0) [0|0] \"hour\" XXX\n SG_ MINUTE : 39|8@0+ (1,0) [0|0] \"minute\" XXX\n SG_ GMT_DIFF : 55|1@0+ (1,0) [0|0] \"\" XXX\n SG_ GMTDIFF_HOURS : 54|4@0+ (1,0) [0|0] \"hours\" XXX\n SG_ GMTDIFF_MINUTES : 50|6@0+ (1,0) [0|0] \"minutes\" XXX\n SG_ SUMMER : 60|1@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1408 VIN_PART_1: 8 CGW\n SG_ VIN_1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_2 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_3 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_4 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_5 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_6 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_7 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_8 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1409 VIN_PART_2: 8 CGW\n SG_ VIN_9 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_10 : 15|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_11 : 23|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_12 : 31|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_13 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_14 : 47|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_15 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ VIN_16 : 63|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1410 VIN_PART_3: 8 CGW\n SG_ VIN_17 : 7|8@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1553 UI_SETTING: 8 XXX\n SG_ UNITS : 26|2@0+ (1,0) [0|3] \"\" XXX\n SG_ ODOMETER : 43|20@0+ (1,0) [0|1048575] \"\" XXX\n\nBO_ 1556 STEERING_LEVERS: 8 XXX\n SG_ TURN_SIGNALS : 29|2@0+ (1,0) [0|3] \"\" XXX\n SG_ HAZARD_LIGHT : 27|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1568 SEATS_DOORS: 8 XXX\n SG_ METER_DIMMED : 38|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_BRAKE : 60|1@0+ (1,0) [0|1] \"\" XXX\n SG_ SEATBELT_DRIVER_UNLATCHED : 62|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FL : 45|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RL : 42|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_RR : 43|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DOOR_OPEN_FR : 44|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1570 LIGHT_STALK: 8 SCM\n SG_ AUTO_HIGH_BEAM : 37|1@0+ (1,0) [0|1] \"\" XXX\n SG_ FRONT_FOG : 27|1@0+ (1,0) [0|1] \"\" XXX\n SG_ PARKING_LIGHT : 28|1@0+ (1,0) [0|1] \"\" XXX\n SG_ LOW_BEAM : 29|1@0+ (1,0) [0|1] \"\" XXX\n SG_ HIGH_BEAM : 30|1@0+ (1,0) [0|1] \"\" XXX\n SG_ DAYTIME_RUNNING_LIGHT : 31|1@0+ (1,0) [0|1] \"\" XXX\n\nBO_ 1161 RSA1: 8 FCM\n SG_ TSGN1 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY1 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT1 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL1 : 23|8@0+ (1,0) [0|0] \"kph\" XXX\n SG_ SPLSGN1 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN2 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN2 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY2 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT2 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDVAL2 : 55|8@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_P : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ BZRRQ_A : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID1 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1162 RSA2: 8 FCM\n SG_ TSGN3 : 7|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY3 : 12|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT3 : 9|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN3 : 31|4@0+ (1,0) [0|0] \"\" XXX\n SG_ SPLSGN4 : 27|4@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGN4 : 39|8@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNGRY4 : 44|3@0+ (1,0) [0|0] \"\" XXX\n SG_ TSGNHLT4 : 41|2@0+ (1,0) [0|0] \"\" XXX\n SG_ DPSGNREQ : 54|1@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMP : 53|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SGNNUMA : 50|3@0+ (1,0) [0|0] \"\" XXX\n SG_ SPDUNT : 63|2@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRWMSG : 61|2@0+ (1,0) [0|0] \"\" XXX\n SG_ SYNCID2 : 59|4@0+ (1,0) [0|0] \"\" XXX\n\nBO_ 1163 RSA3: 8 FCM\n SG_ TSREQPD : 7|1@0+ (1,0) [0|0] \"\" XXX\n SG_ TSRMSW : 6|1@0+ (1,0) [0|0] \"\" XXX\n SG_ OTSGNNTM : 5|2@0+ (1,0) [0|0] \"\" XXX\n SG_ NTLVLSPD : 3|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPNTM : 1|2@0+ (1,0) [0|0] \"\" XXX\n SG_ OVSPVALL : 11|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALM : 19|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ OVSPVALH : 27|4@0+ (1,-5) [0|0] \"\" XXX\n SG_ TSRSPU : 33|2@0+ (1,0) [0|0] \"\" XXX\n \nBO_ 1571 CENTRAL_GATEWAY_UNIT: 8 CGW\n SG_ DOOR_LOCK_FEEDBACK_LIGHT : 15|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_LOCKING_FEEDBACK_LIGHT : 61|1@0+ (1,0) [0|0] \"\" XXX\n SG_ KEYFOB_UNLOCKING_FEEDBACK_LIGHT : 62|1@0+ (1,0) [0|0] \"\" XXX\n\nCM_ SG_ 36 ACCEL_Y \"unit is tbd\";\nCM_ SG_ 36 YAW_RATE \"verify\";\nCM_ SG_ 36 STEERING_TORQUE \"does not seem the steer torque, tbd\";\nCM_ SG_ 37 STEER_FRACTION \"1/15th of the signal STEER_ANGLE, which is 1.5 deg; note that 0x8 is never set\";\nCM_ SG_ 37 STEER_RATE \"factor is tbd\";\nCM_ SG_ 466 ACCEL_NET \"net acceleration produced by the system, given ACCEL_CMD, road grade and other factors\";\nCM_ SG_ 466 CRUISE_STATE \"Active state is 8, if standstill is requested will switch to state 11(3 sec timer), after timer is elapsed will switch into state 7(standstill). If plus button was pressed - status 9, minus button pressed - status 10\";\nCM_ SG_ 467 SET_SPEED \"43 kph are shown as 28mph, so conversion isn't perfect\";\nCM_ SG_ 467 LOW_SPEED_LOCKOUT \"in low speed lockout, system would always disengage below 28mph\";\nCM_ SG_ 560 BRAKE_PRESSED \"another brake pressed?\";\nCM_ SG_ 608 STEER_TORQUE_DRIVER \"driver torque\";\nCM_ SG_ 608 STEER_OVERRIDE \"set when driver torque exceeds a certain value\";\nCM_ SG_ 614 ANGLE \"set to measured angle when ipas control isn't active\";\nCM_ SG_ 643 COUNTER \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 BRAKE_STATUS \"only used on cars that use this msg for cruise control\";\nCM_ SG_ 643 PRECOLLISION_ACTIVE \"set 0.5s before any braking\";\nCM_ SG_ 835 ACC_TYPE \"if 2, car is likely to have a permanent low speed lockout. 1 is ok\";\nCM_ SG_ 835 PERMIT_BRAKING \"Original ACC has this going high when a car in front is detected. In openpilot and before the PERMIT_BRAKING name, this was 'SET_ME_1' and is hardcoded to be high. Unsure if only informational or has an effect though existing usage in openpilot is to always set it to 1. Originally 'PMTBRKG' in the leaked toyota_2017_ref_pt.dbc file and name expansion speculated to be PerMiT BRaKinG.\";\nCM_ SG_ 835 ACCEL_CMD_ALT \"Copy of main ACCEL_CMD, but across 8 bits instead of 16 bits like ACCEL_CMD. Unsure if only informational or has an effect. Likely informational as existing openpilot sets this to 0 and no loss of functionality observed. Originally 'AT_RAW' in leaked toyota_2017_ref_pt.dbc file.\";\nCM_ SG_ 921 UI_SET_SPEED \"set speed shown in UI with user set unit\";\nCM_ SG_ 951 BRAKE_LIGHTS_ACC \"brake lights when ACC commands decel\";\nCM_ SG_ 1042 SET_ME_1 \"unclear what this is, but it's always 1 in drive traces\";\nCM_ SG_ 1042 REPEATED_BEEPS \"recommended for fcw and other important alerts\";\nCM_ SG_ 1161 SPDVAL1 \"Numbers 0-199 is displayed, 200-254 displays circle without number and 255 is for no limit.\";\nCM_ SG_ 1161 SYNCID1 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1161 SPDVAL2 \"conditional speed value 70\";\nCM_ SG_ 1162 SGNNUMP \"1 if SPDVAL1 is set, otherwise 0\";\nCM_ SG_ 1162 SYNCID2 \"counter from 1 to f at 1 Hz\";\nCM_ SG_ 1163 TSREQPD \"always 1\";\nCM_ SG_ 1163 TSRMSW \"always 1\";\nCM_ SG_ 1163 OTSGNNTM \"always 3\";\nCM_ SG_ 1163 NTLVLSPD \"always 3\";\nCM_ SG_ 1163 OVSPNTM \"always 3\";\nCM_ SG_ 1163 OVSPVALL \"-5 at start then 2 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALM \"-5 at start then 5 after 2 seconds\";\nCM_ SG_ 1163 OVSPVALH \"-5 at start then 10 after 2 seconds\";\nCM_ SG_ 1163 TSRSPU \"always 1\";\nCM_ SG_ 1553 ODOMETER \"Unit is dependent upon units signal\";\n\nVAL_ 466 CRUISE_STATE 11 \"timer_3sec\" 10 \"adaptive click down\" 9 \"adaptive click up\" 8 \"adaptive engaged\" 7 \"standstill\" 6 \"non-adaptive click up\" 5 \"non-adaptive click down\" 4 \"non-adaptive hold down\" 3 \"non-adaptive hold up\" 2 \"non-adaptive being engaged\" 1 \"non-adaptive engaged\" 0 \"off\";\nVAL_ 467 LOW_SPEED_LOCKOUT 2 \"low speed locked\" 1 \"ok\";\nVAL_ 614 STATE 3 \"enabled\" 1 \"disabled\";\nVAL_ 614 DIRECTION_CMD 3 \"right\" 2 \"center\" 1 \"left\";\nVAL_ 643 STATE 0 \"normal\" 1 \"adaptive_cruise_control\" 3 \"emergency_braking\";\nVAL_ 835 ACC_TYPE 2 \"permanent low speed lockout\" 1 \"ok\";\nVAL_ 921 CRUISE_CONTROL_STATE 2 \"disabled\" 11 \"hold\" 10 \"hold_waiting_user_cmd\" 6 \"enabled\" 5 \"faulted\";\nVAL_ 1042 LDA_ALERT 3 \"hold with continuous beep\" 2 \"LDA unavailable\" 1 \"hold\" 0 \"none\";\nVAL_ 1042 BARRIERS 3 \"both\" 2 \"right\" 1 \"left\" 0 \"none\";\nVAL_ 1042 RIGHT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1042 LEFT_LINE 3 \"orange\" 2 \"faded\" 1 \"solid\" 0 \"none\";\nVAL_ 1553 UNITS 1 \"km\" 2 \"miles\";\nVAL_ 1556 TURN_SIGNALS 3 \"none\" 2 \"right\" 1 \"left\";\nVAL_ 1161 TSGN1 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 TSGN2 1 \"speed sign\" 0 \"none\";\nVAL_ 1161 SPLSGN2 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\nVAL_ 1162 TSGN3 0 \"none\" 1 \"speed sign\" 2 \"0 unlimited\" 7 \"unlimited\" 16 \"highway\" 17 \"no highway\" 18 \"motorway\" 19 \"no motorway\" 20 \"in city\" 21 \"outside city\" 22 \"pedestrian area\" 23 \"no pedestrian area\" 65 \"no overtaking left\" 66 \"no overtaking right\" 67 \"overtaking allowed again\" 81 \"no right turn\" 97 \"stop\" 105 \"yield\" 113 \"stop\" 114 \"yield us\" 129 \"no entry\" 138 \"no entry tss2\" 145 \"do not enter\";\nVAL_ 1162 SPLSGN3 15 \"conditional blank\" 4 \"wet road\" 5 \"rain\" 0 \"none\";\n\n\nCM_ \"CHFFR_METRIC 37 STEER_ANGLE STEER_ANGLE 0.36 180\";\n\n\nCM_ \"Imported file _comma.dbc starts here\";\nBO_ 359 STEERING_IPAS_COMMA: 8 IPAS\n SG_ STATE : 7|4@0+ (1,0) [0|15] \"\" XXX\n SG_ ANGLE : 3|12@0- (1.5,0) [-510|510] \"deg\" XXX\n SG_ SET_ME_X10 : 23|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00 : 31|8@0+ (1,0) [0|255] \"\" XXX\n SG_ DIRECTION_CMD : 38|2@0+ (1,0) [0|3] \"\" XXX\n SG_ SET_ME_X40 : 47|8@0+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_X00_1 : 55|8@0+ (1,0) [0|255] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nCM_ \"BO_ STEERING_IPAS_COMMA: Copy of msg 614 so we can do angle control while the Park Assist ECU is connected (Panda spoofs 614 with 359 on connector J70). Note that addresses 0x266 and 0x167 are checksum-invariant\";\n\n BO_ 512 GAS_COMMAND: 6 EON\n  SG_ GAS_COMMAND : 7|16@0+ (0.159375,-75.555) [0|1] \"\" INTERCEPTOR\n  SG_ GAS_COMMAND2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" INTERCEPTOR\n  SG_ ENABLE : 39|1@0+ (1,0) [0|1] \"\" INTERCEPTOR\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" INTERCEPTOR\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" INTERCEPTOR\n\n BO_ 513 GAS_SENSOR: 6 INTERCEPTOR\n  SG_ INTERCEPTOR_GAS : 7|16@0+ (0.159375,-75.555) [0|1] \"\" EON\n  SG_ INTERCEPTOR_GAS2 : 23|16@0+ (0.159375,-151.111) [0|1] \"\" EON\n  SG_ STATE : 39|4@0+ (1,0) [0|15] \"\" EON\n  SG_ COUNTER_PEDAL : 35|4@0+ (1,0) [0|15] \"\" EON\n  SG_ CHECKSUM_PEDAL : 47|8@0+ (1,0) [0|255] \"\" EON\n\n VAL_ 513 STATE 5 \"FAULT_TIMEOUT\" 4 \"FAULT_STARTUP\" 3 \"FAULT_SCE\" 2 \"FAULT_SEND\" 1 \"FAULT_BAD_CHECKSUM\" 0 \"NO_FAULT\" ;\n\nBO_ 35 SECONDARY_STEER_ANGLE: 8 XXX\n SG_ ZORRO_STEER : 7|24@0- (0.004901594652,0) [-500|500] \"\" XXX\n\nCM_ \"BO_ SECONDARY_STEER_ANGLE: ZSS is a high-precision steering angle sensor that can replace the lower resolution sensor in most TSS1 Toyotas. Learn more: https://github.com/commaai/openpilot/wiki/Toyota-Lexus#zorro-steering-sensor-zss\";\n\nCM_ \"toyota_sienna_xle_2018_pt.dbc starts here\";\n\n\n\nBO_ 550 BRAKE_MODULE: 8 XXX\n SG_ BRAKE_PRESSURE : 0|9@0+ (1,0) [0|255] \"\" XXX\n SG_ BRAKE_POSITION : 16|9@0+ (1,0) [0|65535] \"\" XXX\n SG_ BRAKE_PRESSED : 37|1@0+ (1,0) [0|3] \"\" XXX\n\nBO_ 705 GAS_PEDAL: 8 XXX\n SG_ GAS_RELEASED : 3|1@0+ (1,0) [0|1] \"\" XXX\n SG_ GAS_PEDAL : 55|8@0+ (0.005,0) [0|1] \"\" XXX\n\nBO_ 608 STEER_TORQUE_SENSOR: 8 XXX\n SG_ STEER_TORQUE_EPS : 47|16@0- (0.73,0) [-20000|20000] \"\" XXX\n SG_ STEER_TORQUE_DRIVER : 15|16@0- (1,0) [-32768|32767] \"\" XXX\n SG_ STEER_OVERRIDE : 0|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n SG_ STEER_ANGLE : 31|16@0- (0.0573,0) [-500|500] \"\" XXX\n\nBO_ 610 EPS_STATUS: 5 EPS\n SG_ IPAS_STATE : 3|4@0+ (1,0) [0|15] \"\" XXX\n SG_ LKA_STATE : 31|7@0+ (1,0) [0|127] \"\" XXX\n SG_ TYPE : 24|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 39|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 956 GEAR_PACKET: 8 XXX\n SG_ GEAR : 13|6@0+ (1,0) [0|63] \"\" XXX\n\nCM_ SG_ 548 BRAKE_PRESSURE \"seems prop to pedal force\";\nCM_ SG_ 548 BRAKE_POSITION \"seems proportional to pedal displacement, unclear the max value of 0x1c8\";\nCM_ SG_ 610 TYPE \"seems 1 on Corolla, 0 on all others\";\nVAL_ 956 GEAR 0 \"D\" 1 \"S\" 8 \"N\" 16 \"R\" 32 \"P\";\nVAL_ 610 IPAS_STATE 5 \"override\" 3 \"enabled\" 1 \"disabled\";\nVAL_ 610 LKA_STATE 25 \"temporary_fault\" 9 \"temporary_fault2\" 5 \"active\" 1 \"standby\"\n"
  },
  {
    "path": "opendbc/toyota_tss2_adas.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: XXX\n\n\nBO_ 384 TRACK_A_0: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 385 TRACK_A_1: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 386 TRACK_A_2: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 387 TRACK_A_3: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 388 TRACK_A_4: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 389 TRACK_A_5: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 390 TRACK_A_6: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 391 TRACK_A_7: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 392 TRACK_A_8: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 393 TRACK_A_9: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 394 TRACK_A_10: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 395 TRACK_A_11: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 396 TRACK_A_12: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 397 TRACK_A_13: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 398 TRACK_A_14: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 399 TRACK_A_15: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ LAT_DIST : 31|11@0- (0.04,0) [-50|50] \"m\" XXX\n SG_ LONG_DIST : 15|13@0+ (0.04,0) [0|300] \"m\" XXX\n SG_ NEW_TRACK : 36|1@0+ (1,0) [0|1] \"\" XXX\n SG_ REL_SPEED : 47|12@0- (0.025,0) [-100|100] \"m/s\" XXX\n SG_ VALID : 48|1@0+ (1,0) [0|1] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 400 TRACK_B_0: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 401 TRACK_B_1: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 402 TRACK_B_2: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 403 TRACK_B_3: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 404 TRACK_B_4: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 405 TRACK_B_5: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 406 TRACK_B_6: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 407 TRACK_B_7: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 408 TRACK_B_8: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 409 TRACK_B_9: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 410 TRACK_B_10: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 411 TRACK_B_11: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 412 TRACK_B_12: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 413 TRACK_B_13: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 414 TRACK_B_14: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 415 TRACK_B_15: 8 XXX\n SG_ COUNTER : 7|8@0+ (1,0) [0|255] \"\" XXX\n SG_ REL_ACCEL : 15|7@0- (1,0) [-64|63] \"\" XXX\n SG_ SCORE : 23|8@0+ (1,0) [0|100] \"\" XXX\n SG_ CHECKSUM : 63|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 576 NEW_MSG_1: 8 XXX\n SG_ NEW_SIGNAL_1 : 15|7@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_2 : 23|8@0+ (1,0) [0|255] \"\" XXX\n\nBO_ 577 NEW_MSG_2: 8 XXX\n SG_ NEW_SIGNAL_1 : 15|7@0+ (1,0) [0|127] \"\" XXX\n SG_ NEW_SIGNAL_2 : 23|8@0+ (1,0) [0|255] \"\" XXX\n"
  },
  {
    "path": "opendbc/vw_mqb_2010.dbc",
    "content": "VERSION \"\"\n\n\nNS_ :\n    NS_DESC_\n    CM_\n    BA_DEF_\n    BA_\n    VAL_\n    CAT_DEF_\n    CAT_\n    FILTER\n    BA_DEF_DEF_\n    EV_DATA_\n    ENVVAR_DATA_\n    SGTYPE_\n    SGTYPE_VAL_\n    BA_DEF_SGTYPE_\n    BA_SGTYPE_\n    SIG_TYPE_REF_\n    VAL_TABLE_\n    SIG_GROUP_\n    SIG_VALTYPE_\n    SIGTYPE_VALTYPE_\n    BO_TX_BU_\n    BA_DEF_REL_\n    BA_REL_\n    BA_DEF_DEF_REL_\n    BU_SG_REL_\n    BU_EV_REL_\n    BU_BO_REL_\n    SG_MUL_VAL_\n\nBS_:\n\nBU_: Airbag_MQB BAP_Tester_MQB BMS_MQB Datenlogger_MQB Gateway_MQB Getriebe_DQ_Hybrid_MQB Getriebe_DQ_MQB LEH_MQB Motor_Diesel_MQB Motor_Hybrid_MQB Motor_Otto_MQB SAK_MQB Waehlhebel_MQB Vector__XXX 9 l c i XXX\n\n\nBO_ 290 ACC_06: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_limitierte_Anfahrdyn : 12|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_zul_Regelabw_unten : 16|6@1+ (0.024,0) [0|1.512] \"Unit_MeterPerSeconSquar\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_StartStopp_Info : 22|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ ACC_Sollbeschleunigung_02 : 24|11@1+ (0.005,-7.22) [-7.22|3.005] \"Unit_MeterPerSeconSquar\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_zul_Regelabw_oben : 35|5@1+ (0.0625,0) [0|1.9375] \"Unit_MeterPerSeconSquar\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_neg_Sollbeschl_Grad_02 : 40|8@1+ (0.05,0) [0|12.75] \"Unit_MeterPerCubicSecon\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_pos_Sollbeschl_Grad_02 : 48|8@1+ (0.05,0) [0|12.75] \"Unit_MeterPerCubicSecon\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_Anfahren : 56|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_Anhalten : 57|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_Typ : 58|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_Status_ACC : 60|3@1+ (1,0) [0|7] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ACC_Minimale_Bremsung : 63|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 279 ACC_10: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB\n SG_ AWV1_Anf_Prefill : 16|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ANB_CM_Info : 17|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AWV2_Freigabe : 18|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ AWV1_HBA_Param : 19|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ AWV2_Ruckprofil : 21|3@1+ (1,0) [0|7] \"\" Vector__XXX\n SG_ AWV2_Priowarnung : 24|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ANB_CM_Anforderung : 25|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ANB_Info_Teilbremsung : 26|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ANB_Notfallblinken : 27|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ANB_Teilbremsung_Freigabe : 28|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ANB_Zielbrems_Teilbrems_Verz_Anf : 29|10@1+ (0.024,-20.016) [-20.016|4.536] \"Unit_MeterPerSeconSquar\" Airbag_MQB\n SG_ ANB_Zielbremsung_Freigabe : 39|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ AWV_Vorstufe : 40|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AWV_Halten : 41|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 64 Airbag_01: 8 Airbag_MQB\n SG_ Airbag_01_CRC : 0|8@1+ (1,0) [0|255] \"\" BMS_MQB,Gateway_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ Airbag_01_BZ : 8|4@1+ (1,0) [0|15] \"\" BMS_MQB,Gateway_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AB_RGS_Anst : 12|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ AB_Front_Crash : 16|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Heck_Crash : 17|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_SF_Crash : 18|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_SB_Crash : 19|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Rollover_Crash : 20|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Crash_Int : 21|3@1+ (1,0) [0|7] \"\" BMS_MQB,Gateway_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AB_Lampe : 24|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Deaktiviert : 25|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_VB_deaktiviert : 26|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Systemfehler : 27|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB,LEH_MQB\n SG_ AB_Diagnose : 28|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Stellgliedtest : 29|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AB_Erh_Auf_VB : 30|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtwarn_VF : 32|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Gurtwarn_VB : 33|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Anzeige_Fussg : 34|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Texte_AKS : 36|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_PAO_Leuchte_Anf : 38|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_MKB_gueltig : 39|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_MKB_Anforderung : 40|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ AB_Versorgungsspannung : 41|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 1312 Airbag_02: 8 Airbag_MQB\n SG_ AB_Belegung_VB : 26|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_FA : 40|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ AB_Gurtschloss_BF : 42|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_Reihe2_FA : 44|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_Reihe2_MI : 46|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_Reihe2_BF : 48|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_Reihe3_FA : 50|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_Reihe3_MI : 52|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Gurtschloss_Reihe3_BF : 54|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Sitzpos_Sens_FA : 56|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ AB_Sitzpos_Sens_BF : 58|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n\nBO_ 65 Airbag_03: 8 Airbag_MQB\n SG_ Airbag_03_CRC : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n SG_ Airbag_03_BZ : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ AB_MKB_Safing : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 1633 Anhaenger_01: 8 Gateway_MQB\n SG_ AAG_BZ : 0|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AAG_Bremsl_durch_ECD : 5|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AAG_Anhaenger_abgesteckt : 6|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_NSL_aktiv : 7|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_Anhaenger_erkannt : 8|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AAG_Blinker_H_aktiv : 9|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_Blinker_HL_def : 10|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_Blinker_HR_def : 11|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_Bremslicht_H_def : 12|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AAG_Schlusslicht_HL_def : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_Schlusslicht_HR_def : 14|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_AVS_Fehler_02 : 18|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ AAG_AVS_Stati : 20|4@1+ (1,0) [0|15] \"\" Vector__XXX\n\nBO_ 1626 BCM_01: 8 Gateway_MQB\n SG_ BCM_Bremsbelag_Sensor : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM_Bremsfluessigkeit_Sensor : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM1_Licht_Warn : 14|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM_Waschwasser_Sensor : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM_Kuehlmittel_Sensor : 16|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ BCM1_Kl_15_HW_erkannt : 17|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM_Eis_Offroad_Taste : 18|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ ZZH_Endlage_oben : 19|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZZH_Endlage_unten : 20|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZZH_Endlage_unplausibel : 21|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM2_EZS_gedrueckt : 22|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM2_SST_gedrueckt : 23|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM_Hybrid_StartStopp_Taste : 24|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM1_Warnblink_Taster : 25|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM1_Valet_Parking_Taster : 26|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM_Remotestart_Betrieb : 27|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ BCM1_HSK_Taster : 28|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM1_Heckrollo_Taster : 29|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM1_Rueckfahrlicht_Schalter : 30|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM1_MH_Schalter : 31|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ BCM1_MH_WIV_Schalter : 32|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM_Eco_Charisma_Taste : 33|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ BCM_Thermomanagement : 34|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM_Thermomanagement_Fehler : 36|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM_Thermomanagement_gueltig : 37|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM1_Lichtwarn_Texte : 38|2@1+ (1,0) [0|3] \"\" Vector__XXX\n\nBO_ 869 BEM_05: 8 Gateway_MQB\n SG_ BEM_P_Generator : 16|8@1+ (50,0) [0|12700] \"Unit_Watt\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_n_LLA : 24|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_01_Abschaltstufen : 26|3@1+ (1,0) [0|7] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_Anf_KL : 29|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_StartStopp_Info : 30|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ BEM_DFM : 32|5@1+ (3.225,0.025) [0.025|100] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_EMLIN_ungueltig : 37|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_Batt_Ab : 38|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_Segel_Info : 48|2@1+ (1,0) [0|3] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BEM_HYB_DC_uSollLV : 50|6@1+ (0.1,10.6) [10.6|16] \"Unit_Volt\" LEH_MQB\n SG_ BEM_HYB_DC_uMinLV : 56|8@1+ (0.1,0) [0|25.3] \"Unit_Volt\" LEH_MQB\n\nBO_ 1628 BMS_Hybrid_01: 8 BMS_MQB\n SG_ BMS_HYB_ASV_hinten_Status : 13|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ BMS_HYB_ASV_vorne_Status : 14|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ BMS_HYB_KD_Fehler : 15|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ BMS_HYB_BattFanSpd : 16|4@1+ (10,0) [0|100] \"Unit_PerCent\" Gateway_MQB\n SG_ BMS_HYB_VentilationReq : 20|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ BMS_HYB_Spuelbetrieb_Status : 21|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ BMS_HYB_Kuehlung_Anf : 22|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ BMS_HYB_Temp_vor_Verd : 24|8@1+ (0.5,-40) [-40|86.5] \"Unit_DegreCelsi\" Gateway_MQB\n SG_ BMS_HYB_Temp_nach_Verd : 32|8@1+ (0.5,-40) [-40|86.5] \"Unit_DegreCelsi\" Gateway_MQB\n SG_ BMS_Temperatur : 40|8@1+ (0.5,-40) [-40|86.5] \"Unit_DegreCelsi\" Gateway_MQB\n SG_ BMS_Temperatur_Ansaugluft : 48|8@1+ (0.5,-40) [-40|86.5] \"Unit_DegreCelsi\" Gateway_MQB\n SG_ BMS_IstSpannung_HV : 56|8@1+ (1,100) [100|350] \"Unit_Volt\" Gateway_MQB\n\nBO_ 901 Charisma_01: 8 Gateway_MQB\n SG_ CHA_Ziel_FahrPr_ALR : 0|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_ESP : 4|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_FL : 8|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Fahrer_Umschaltung : 14|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ CHA_Ziel_FahrPr_MO : 16|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ CHA_Ziel_FahrPr_GE : 20|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ CHA_Ziel_FahrPr_ST : 24|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_SCU : 28|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_DR : 32|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_QS : 36|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_AFS : 40|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_RGS : 44|4@1+ (1,0) [0|15] \"\" Airbag_MQB\n SG_ CHA_Ziel_FahrPr_EPS : 48|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_ACC : 52|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ CHA_Ziel_FahrPr_SAK : 56|4@1+ (1,0) [0|15] \"\" SAK_MQB\n SG_ CHA_Ziel_FahrPr_MStSt : 60|4@1+ (1,0) [0|15] \"\" Vector__XXX\n\nBO_ 945 DC_Hybrid_01: 8 LEH_MQB\n SG_ DC_HYB_iAktLV : 12|10@1+ (1,-511) [-511|510] \"Unit_Amper\" Gateway_MQB\n SG_ DC_HYB_iAktReserveLV : 22|10@1+ (1,-511) [-511|510] \"Unit_Amper\" Gateway_MQB\n SG_ DC_HYB_uAktLV : 32|8@1+ (0.1,0) [0|25.3] \"Unit_Volt\" Gateway_MQB\n SG_ DC_HYB_LangsRegelung : 40|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ DC_HYB_Abregelung_Temperatur : 41|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ DC_HYB_Fehler_RedLeistung : 42|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ DC_HYB_Fehler_intern : 43|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ DC_HYB_Fehler_Spannung : 44|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ DC_HYB_Auslastungsgrad : 56|8@1+ (0.4,0) [0|100] \"Unit_PerCent\" Gateway_MQB\n\nBO_ 1714 Diagnose_01: 8 Gateway_MQB\n SG_ DGN_Verlernzaehler : 0|8@1+ (1,0) [0|254] \"\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,SAK_MQB\n SG_ KBI_Kilometerstand : 8|20@1+ (1,0) [0|1048573] \"Unit_KiloMeter\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ UH_Jahr : 28|7@1+ (1,2000) [2000|2127] \"Unit_Year\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ UH_Monat : 35|4@1+ (1,0) [1|12] \"Unit_Month\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ UH_Tag : 39|5@1+ (1,0) [1|31] \"Unit_Day\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ UH_Stunde : 44|5@1+ (1,0) [0|23] \"Unit_Hours\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ UH_Minute : 49|6@1+ (1,0) [0|59] \"Unit_Minut\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ UH_Sekunde : 55|6@1+ (1,0) [0|59] \"Unit_Secon\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ Kombi_02_alt : 62|1@1+ (1,0) [0|1] \"\" Airbag_MQB,BMS_MQB,LEH_MQB\n SG_ Uhrzeit_01_alt : 63|1@1+ (1,0) [0|1] \"\" Airbag_MQB,BMS_MQB,LEH_MQB\n\nBO_ 1520 Dimmung_01: 8 Gateway_MQB\n SG_ DI_KL_58xd : 0|8@1+ (1,0) [0|253] \"\" Airbag_MQB\n SG_ DI_KL_58xs : 8|7@1+ (1,0) [0|100] \"Unit_PerCent\" Vector__XXX\n SG_ DI_Display_Nachtdesign : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ DI_KL_58xt : 16|7@1+ (1,0) [0|100] \"Unit_PerCent\" Vector__XXX\n SG_ DI_Fotosensor : 24|16@1+ (1,0) [0|65535] \"\" Vector__XXX\n\nBO_ 1603 Einheiten_01: 8 Gateway_MQB\n SG_ KBI_Einheit_Datum : 0|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KBI_Einheit_Druck : 2|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KBI_Einheit_Streckenanz : 4|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB\n SG_ KBI_MFA_v_Einheit_02 : 5|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Einheit_Temp : 6|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Einheit_Uhrzeit : 7|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Einheit_Verbrauch : 8|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KBI_Einheit_Volumen : 10|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KBI_Einheit_Sprache : 16|8@1+ (1,0) [0|255] \"\" Vector__XXX\n\nBO_ 260 EPB_01: 8 Gateway_MQB\n SG_ EPB_01_CRC : 0|8@1+ (1,0) [0|255] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EPB_01_BZ : 8|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EPB_QBit_Laengsbeschleunigung : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EPB_QBit_Pedalweg_Kuppl : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EPB_BCM2_Motor_Wakeup : 14|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EPB_Freig_Verzoeg_Anf : 15|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EPB_Verzoeg_Anf : 16|8@1+ (0.048,-7.968) [-7.968|4.224] \"Unit_MeterPerSeconSquar\" Vector__XXX\n SG_ EPB_Laengsbeschleunigung : 24|8@1+ (1,-128) [-128|126] \"Unit_PerCentOfForceOfGravi\" Vector__XXX\n SG_ EPB_Pedalweg_Kuppl : 32|8@1+ (0.4,0) [8|92] \"Unit_PerCent\" Vector__XXX\n SG_ EPB_Anfahrwunsch_erkannt : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EPB_DAA_Randbed_erf : 49|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ EPB_Fehlerstatus : 50|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ EPB_Schalterposition : 52|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EPB_QBit_Schalterpos : 54|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EPB_Konsistenz_ACC : 55|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EPB_Spannkraft : 56|5@1+ (1,0) [0|29] \"Unit_KiloNewto\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ EPB_Status : 61|2@1+ (1,0) [0|3] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 257 ESP_02: 8 Gateway_MQB\n SG_ ESP_02_CRC : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_02_BZ : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Gierrate : 12|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_QBit_Laengsbeschl : 13|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Querb : 14|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Stillstandsflag : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Querbeschleunigung : 16|8@1+ (0.01,-1.27) [-1.27|1.27] \"Unit_ForceOfGravi\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Laengsbeschl : 24|10@1+ (0.03125,-16) [-16|15.90625] \"Unit_MeterPerSeconSquar\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Verteil_Wankmom : 34|5@1+ (0.1,-1) [-1|1] \"\" Vector__XXX\n SG_ ESP_QBit_Anf_Vert_Wank : 39|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Gierrate : 40|14@1+ (0.01,0) [0|163.82] \"Unit_DegreOfArcPerSecon\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_VZ_Gierrate : 54|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_Notbremsanzeige : 55|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ESP_SpannungsAnf : 56|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_PLA_Abbruch : 57|3@1+ (1,0) [0|7] \"\" Vector__XXX\n SG_ ESP_Status_ESP_PLA : 60|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 262 ESP_05: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Bremsdruck : 12|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Fahrer_bremst : 13|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Schwelle_Unterdruck : 14|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Bremsdruck : 16|10@1+ (0.3,-30) [-30|276.6] \"Unit_Bar\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Fahrer_bremst : 26|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Verz_TSK_aktiv : 27|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Lenkeingriff_ADS : 28|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Konsistenz_TSK : 29|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Bremsruck_AWV2 : 30|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Konsistenz_AWV2 : 31|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ECD_Fehler : 32|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ECD_nicht_verfuegbar : 33|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Status_Bremsentemp : 34|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Autohold_Standby : 35|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_HDC_Standby : 36|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_HBA_aktiv : 37|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Prefill_ausgeloest : 38|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Rueckwaertsfahrt_erkannt : 39|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Status_Anfahrhilfe : 40|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_HDC_aktiv : 41|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_StartStopp_Info : 42|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ ESP_Eingr_HL : 44|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Eingr_HR : 45|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Eingr_VL : 46|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Eingr_VR : 47|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_BKV_Unterdruck : 48|8@1+ (4,0) [0|1012] \"Unit_MilliBar\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Autohold_aktiv : 56|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_FStatus_Anfahrhilfe : 57|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_Verz_EPB_aktiv : 58|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ECD_Bremslicht : 59|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Verzoeg_EPB_verf : 60|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Status_Bremsdruck : 61|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Anforderung_EPB : 62|2@1+ (1,0) [0|3] \"\" Vector__XXX\n\nBO_ 914 ESP_07: 8 Gateway_MQB\n SG_ ESP_07_CRC : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_07_BZ : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_ACC_LDE : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Quattro_Antrieb : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Codierung_ADS : 14|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ ESP_RTA_HL : 16|8@1+ (0.048828125,-6.20117) [-6.20117|6.152345625] \"Unit_PerCent\" Vector__XXX\n SG_ ESP_RTA_HR : 24|8@1+ (0.048828125,-6.20117) [-6.20117|6.152345625] \"Unit_PerCent\" Vector__XXX\n SG_ ESP_RTA_VR : 32|8@1+ (0.048828125,-6.20117) [-6.20117|6.152345625] \"Unit_PerCent\" Vector__XXX\n SG_ OBD_Fehler_Radsensor_HL : 40|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_Fehler_Radsensor_HR : 44|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_Fehler_Radsensor_VL : 48|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_Fehler_Radsensor_VR : 52|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Qualifizierung_Antriebsart : 56|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_Offroad_Modus : 57|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_MKB_ausloesbar : 58|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ESP_MKB_Status : 59|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ESP_CM_Variante : 60|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ESP_OBD_Status : 61|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 278 ESP_10: 8 Gateway_MQB\n SG_ ESP_10_CRC : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_10_BZ : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Wegimpuls_VL : 12|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Wegimpuls_VR : 13|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Wegimpuls_HL : 14|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_Wegimpuls_HR : 15|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Wegimpuls_VL : 16|10@1+ (1,0) [0|1000] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Wegimpuls_VR : 26|10@1+ (1,0) [0|1000] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Wegimpuls_HL : 36|10@1+ (1,0) [0|1000] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Wegimpuls_HR : 46|10@1+ (1,0) [0|1000] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_VL_Fahrtrichtung : 56|2@1+ (1,0) [0|3] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_VR_Fahrtrichtung : 58|2@1+ (1,0) [0|3] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_HL_Fahrtrichtung : 60|2@1+ (1,0) [0|3] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_HR_Fahrtrichtung : 62|2@1+ (1,0) [0|3] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 178 ESP_19: 8 Gateway_MQB\n SG_ ESP_HL_Radgeschw_02 : 0|16@1+ (0.0075,0) [0|491.49] \"Unit_KiloMeterPerHour\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_HR_Radgeschw_02 : 16|16@1+ (0.0075,0) [0|491.49] \"Unit_KiloMeterPerHour\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_VL_Radgeschw_02 : 32|16@1+ (0.0075,0) [0|491.49] \"Unit_KiloMeterPerHour\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_VR_Radgeschw_02 : 48|16@1+ (0.0075,0) [0|491.49] \"Unit_KiloMeterPerHour\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 1629 ESP_20: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ BR_Systemart : 12|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ ESP_Zaehnezahl : 16|8@1+ (1,0) [0|255] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_Charisma_FahrPr : 24|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ ESP_Charisma_Status : 28|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ BR_QBit_Reifenumfang : 51|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ BR_Reifenumfang : 52|12@1+ (1,0) [0|4095] \"Unit_MilliMeter\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 253 ESP_21: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BR_Eingriffsmoment : 12|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_v_Signal : 32|16@1+ (0.01,0) [0|655.32] \"Unit_KiloMeterPerHour\" Airbag_MQB,BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB,SAK_MQB\n SG_ ASR_Tastung_passiv : 48|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Tastung_passiv : 49|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Systemstatus : 50|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ASR_Schalteingriff : 51|2@1+ (1,0) [0|3] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ ESP_Haltebestaetigung : 53|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_QBit_v_Signal : 55|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ABS_Bremsung : 56|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ASR_Anf : 57|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ MSR_Anf : 58|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EBV_Eingriff : 59|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ EDS_Eingriff : 60|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Eingriff : 61|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_ASP : 62|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ESP_Anhaltevorgang_ACC_aktiv : 63|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 987 Gateway_72: 8 Gateway_MQB\n SG_ BCM_01_alt : 0|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ SMLS_01_alt : 1|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ ZV_02_alt : 2|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ Wischer_01_alt : 3|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ Anhaenger_01_alt : 4|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ Klima_Sensor_02_alt : 5|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ VSG_01_alt : 6|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ Klima_01_alt : 7|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ WFS_01_alt : 8|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Licht_Anf_01_alt : 9|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZV_HFS_offen : 20|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZV_HBFS_offen : 21|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ VS_VD_offen_ver : 22|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ VS_VD_zu_ver : 23|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZV_BT_offen : 24|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM1_Rueckfahrlicht_Schalter : 25|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ ZV_FT_offen : 26|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ Wischer_vorne_aktiv : 27|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ AAG_Anhaenger_erkannt : 28|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ BCM1_MH_Schalter : 29|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZV_HD_offen : 30|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Waschen_vorne_aktiv : 31|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KL_Thermomanagement : 32|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ WFS_Schluessel_Fahrberecht : 34|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ BCM1_RFahrlicht_Fzg_Anf : 38|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BCM1_RFahrlicht_Ahg_Anf : 39|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BH_Fernlicht : 49|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ BH_Blinker_li : 50|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ BH_Blinker_re : 51|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ BCM1_OBD_FStatus_ATemp : 52|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM1_Aussen_Temp_ungef : 56|8@1+ (0.5,-50) [-50|76] \"Unit_DegreCelsi\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 989 Gateway_74: 8 Gateway_MQB\n SG_ LH_EPS_01_alt : 0|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB\n SG_ Kessy_04_alt : 1|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ LIN_2_alt : 2|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MFG_01_alt : 3|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ GW_74_va_14 : 4|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Klima_02_alt : 5|1@1+ (1,0) [0|1] \"\" BMS_MQB\n SG_ Parkhilfe_01_alt : 6|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ ELV_01_alt : 7|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KY_StartStopp_Info : 16|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ PH_StartStopp_Info : 18|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ EPS_Lenkerposition : 20|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB\n SG_ ELV_Anf_Klemme_50 : 22|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ MF_StartStopp_Info : 25|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ KL_Geblaesespannung_Soll : 40|8@1+ (0.05,0.5) [2|13] \"Unit_Volt\" BMS_MQB\n SG_ KL_Umluftklappe_Status : 48|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ MFL_Tip_Down : 56|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MFL_Tip_Up : 57|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ LS_Tiptronic_Fehler : 58|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 296 Getriebe_06: 3 Getriebe_DQ_Hybrid_MQB\n SG_ GE_WH_Sperre : 0|1@1+ (1,0) [0|1] \"\" Waehlhebel_MQB\n SG_ GE_Ausleuchtungsmode : 1|1@1+ (1,0) [0|1] \"\" Waehlhebel_MQB\n SG_ GE_Test_Freigabe : 2|1@1+ (1,0) [0|1] \"\" Waehlhebel_MQB\n SG_ GE_Ist_Fahrstufe : 4|4@1+ (1,0) [0|15] \"\" Waehlhebel_MQB\n SG_ GE_Testparameter_1 : 8|8@1+ (1,0) [0|255] \"\" Waehlhebel_MQB\n SG_ GE_Testparameter_2 : 16|8@1+ (1,0) [0|255] \"\" Waehlhebel_MQB\n\nBO_ 173 Getriebe_11: 8 Getriebe_DQ_Hybrid_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTERXX : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_MMom_Soll_02 : 12|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_MMom_Vorhalt_02 : 22|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Uefkt : 32|10@1+ (0.1,0) [0|102.2] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Fahrstufe : 42|5@1+ (1,0) [0|31] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Schaltvorgang : 47|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Status_Kupplung : 54|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_MMom_Status : 56|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Freig_MMom_Vorhalt : 58|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Verbot_Ausblendung : 59|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Zielgang : 60|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 174 Getriebe_12: 8 Getriebe_DQ_Hybrid_MQB\n SG_ Getriebe_12_CRC : 0|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ Getriebe_12_BZ : 8|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Drehzahlmesser_Daempfung : 12|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Schubabschalt_Unt : 13|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Freigabe_Synchro : 14|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Synchro_Wunschdrehz : 15|9@1+ (25,0) [0|12750] \"Unit_MinutInver\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Synchro_Zeit : 24|8@1+ (20,0) [0|5080] \"Unit_MilliSecon\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Mom_Begr_Gradient : 32|8@1+ (10,0) [0|2540] \"Unit_NewtoMeterPerSecon\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Anheb_Solldrehz_Leerlauf : 40|8@1+ (10,0) [0|2540] \"Unit_MinutInver\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Aufnahmemoment : 48|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Anf_Zylabsch : 58|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ GE_HYB_DZ_Eingriff : 62|2@1+ (1,0) [0|3] \"\" Motor_Hybrid_MQB\n\nBO_ 301 Getriebe_13: 8 Getriebe_DQ_Hybrid_MQB\n SG_ Getriebe_13_CRC : 0|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ Getriebe_13_BZ : 8|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_StartStopp_Info : 12|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ GE_Langfr_Schutzmom_02 : 14|9@1+ (1,0) [0|509] \"Unit_NewtoMeter\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Eingangsdrehz : 48|14@1+ (1,0) [0|16381] \"Unit_MinutInver\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Notlauf : 62|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Freig_Langfr_Schutzmom : 63|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 968 Getriebe_14: 8 Getriebe_DQ_Hybrid_MQB\n SG_ GE_OBD_AbsperrVent : 12|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_amax_moeglich : 16|9@1+ (0.024,-2.016) [-2.016|10.224] \"Unit_MeterPerSeconSquar\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Charisma_FahrPr : 25|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ GE_Charisma_Status : 29|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ GE_Verlustmoment : 32|8@1+ (1,0) [0|254] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Freigabe_Verfallsinfo_WFS : 49|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ GE_Codierung_MSG : 50|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ GE_LaunchControl : 51|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ GE_Heizwunsch : 52|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_OBD_Status : 54|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_LFR_Adaption : 55|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GE_Sumpftemperatur : 56|8@1+ (1,-58) [-58|196] \"Unit_DegreCelsi\" Gateway_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 158 Getriebe_Hybrid_01: 8 Getriebe_DQ_Hybrid_MQB\n SG_ Getriebe_Hybrid_01_CRC : 0|8@1+ (1,0) [0|255] \"\" Motor_Hybrid_MQB\n SG_ Getriebe_Hybrid_01_BZ : 8|4@1+ (1,0) [0|15] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Fehlerstatus : 12|2@1+ (1,0) [0|3] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Freigabe_K0 : 16|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Freigabe_LL_Reg : 17|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Freig_sSchl_K0 : 18|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Freig_VM_EM_Stop : 19|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Wiederstart : 20|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_Filt_MomAufbau : 21|3@1+ (1,0) [0|7] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_nK0 : 24|8@1+ (25,0) [0|6350] \"Unit_MinutInver\" Vector__XXX\n SG_ GE_HYB_MomEingriff_EM : 32|6@1+ (0.5,0) [0|31.5] \"Unit_NewtoMeter\" LEH_MQB\n SG_ GE_HYB_VZ_MomEingriff_EM : 38|1@1+ (1,0) [0|1] \"\" LEH_MQB\n SG_ GE_HYB_Sportfaktor : 56|4@1+ (1,0) [0|15] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_VM_akt_halten : 61|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_StartAnf : 62|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n SG_ GE_HYB_VM_Startkontr : 63|1@1+ (1,0) [0|1] \"\" Motor_Hybrid_MQB\n\nBO_ 299 GRA_ACC_01: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Hauptschalter : 12|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Abbrechen : 13|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Typ_Hauptschalter : 14|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Limiter : 15|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Tip_Setzen : 16|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Tip_Hoch : 17|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Tip_Runter : 18|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Tip_Wiederaufnahme : 19|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Verstellung_Zeitluecke : 20|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Codierung : 22|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Fehler : 24|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Typ468 : 25|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_Tip_Stufe_2 : 27|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ GRA_ButtonTypeInfo : 28|2@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 960 Klemmen_Status_01: 4 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,BMS_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,BMS_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ZAS_Kl_S : 16|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZAS_Kl_15 : 17|1@1+ (1,0) [0|1] \"\" Airbag_MQB,BMS_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ ZAS_Kl_X : 18|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ ZAS_Kl_50 : 19|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 949 Klima_11: 8 Gateway_MQB\n SG_ KL_Drehz_Anh : 0|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_Vorwarn_Komp_ein : 1|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_AC_Schalter : 2|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KL_Komp_Moment_alt : 3|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KL_Zonen : 4|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_Vorwarn_Zuheizer_ein : 6|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KL_Zustand : 7|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_Comp_rev_rq : 8|8@1+ (50,0) [0|8600] \"Unit_MinutInver\" Vector__XXX\n SG_ KL_Charisma_FahrPr : 16|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ KL_Charisma_Status : 20|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KL_Comp_enable : 23|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KL_Last_Kompr : 24|8@1+ (0.25,0) [0|63.5] \"Unit_NewtoMeter\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_Spannungs_Anf : 32|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KL_Thermomanagement : 34|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_StartStopp_Info : 36|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ KL_Anf_KL : 40|8@1+ (0.4,0) [0|101.6] \"Unit_PerCent\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KL_el_Zuheizer_Stufe : 48|3@1+ (1,0) [0|7] \"\" Motor_Diesel_MQB\n\nBO_ 1625 Klimakomp_01: 8 Gateway_MQB\n SG_ EKL_KD_Fehler : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EKL_Comp_SCI_com_stat : 16|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ EKL_Comp_output_stat : 18|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ EKL_Comp_main_stat : 20|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EKL_Comp_ovld_stat : 21|3@1+ (1,0) [0|7] \"\" Vector__XXX\n SG_ EKL_Comp_Inv_stat : 24|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ EKL_Comp_photo_temp_stat : 30|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ EKL_Comp_photo_temp : 32|8@1+ (1,0) [0|254] \"Unit_DegreCelsi\" Vector__XXX\n SG_ EKL_Comp_current : 40|8@1+ (0.1,0) [0|25.4] \"Unit_Amper\" Motor_Hybrid_MQB\n SG_ EKL_Comp_rev_stat : 48|8@1+ (50,0) [0|8600] \"Unit_MinutInver\" Vector__XXX\n\nBO_ 2549088277 KN_Airbag_01: 8 Airbag_MQB\n SG_ Airbag_01_KompSchutz : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Airbag_01_Nachlauftyp : 4|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ AB_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 2549088380 KN_EMotor_01: 8 LEH_MQB\n SG_ EMotor_KompSchutz : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ EMotor_Nachlauftyp : 4|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ EM_HYB_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 2549088375 KN_Getriebe_01: 8 Getriebe_DQ_Hybrid_MQB\n SG_ Getriebe_KompSchutz : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Getriebe_Nachlauftyp : 4|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ GE_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 2549088379 KN_Hybrid_01: 8 BMS_MQB\n SG_ Hybrid_KompSchutz : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Hybrid_Nachlauftyp : 4|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ BMS_HYB_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 2549088374 KN_MO_01: 8 Motor_Diesel_MQB\n SG_ Motor_KompSchutz : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Motor_Nachlauftyp : 4|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 2549088284 KN_SAK: 8 SAK_MQB\n SG_ SAK_KompSchutz : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SAK_Nachlauftyp : 4|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ SAK_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 779 Kombi_01: 8 Gateway_MQB\n SG_ KBI_ABS_Lampe : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_ESP_Lampe : 1|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_BKL_Lampe : 2|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Airbag_Lampe : 3|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ KBI_SILA_gueltig : 4|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ KBI_Lenkung_Lampe : 5|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Vorglueh_System_Lampe : 6|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB\n SG_ KBI_NV_in_Anzeige : 7|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ Kombi_01_BZ : 8|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_Anzeigestatus_ACC : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Anzeigestatus_GRA : 13|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_Oeldruck_Schalter : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Tankwarnung : 16|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_MFA_v_Einheit_01 : 17|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_im_Stellgliedtest : 18|1@1+ (1,0) [0|1] \"\" Airbag_MQB\n SG_ KBI_Anzeigefehler_LDW : 19|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ KBI_Variante_USA : 21|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Oeldruckwarnung : 22|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Handbremse : 23|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ KBI_V_Digital : 24|9@1+ (1,0) [0|511] \"\" Vector__XXX\n SG_ KBI_PLA_in_Anzeige : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Anzeigefehler_NV : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Anzeigestatus_LIM : 35|2@1+ (1,0) [0|3] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_angez_Geschw : 48|10@1+ (0.32,0) [0|325.12] \"Unit_KiloMeterPerHour\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_Einheit_Tacho : 58|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_Konsistenz_ACC : 59|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Fehler_Anzeige_ACC : 60|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ KBI_Anzeigefehler_SWA : 61|2@1+ (1,0) [0|3] \"\" Vector__XXX\n\nBO_ 1719 Kombi_02: 8 Gateway_MQB\n SG_ KBI_Kilometerstand : 0|20@1+ (1,0) [0|1048573] \"Unit_KiloMeter\" Vector__XXX\n SG_ KBI_Standzeit_02 : 20|17@1+ (1,0) [0|131068] \"Unit_Secon\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_Inhalt_Tank : 40|7@1+ (1,0) [0|125] \"Unit_Liter\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_FStatus_Tank : 47|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_QBit_Aussen_Temp_gef : 55|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ KBI_Aussen_Temp_gef : 56|8@1+ (0.5,-50) [-50|75] \"Unit_DegreCelsi\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 982 Licht_hinten_01: 8 Gateway_MQB\n SG_ Licht_hinten_01_BZ : 0|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ BCM2_Bremsl_durch_ECD : 5|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LH_Aussenlicht_def : 7|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Standlicht_H_aktiv : 8|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Parklicht_HL_aktiv : 9|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Parklicht_HR_aktiv : 10|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Bremslicht_H_aktiv : 11|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Nebelschluss_aktiv : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Rueckfahrlicht_aktiv : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Blinker_HL_akt : 14|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Blinker_HR_akt : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Blinker_li_def : 16|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Bremsl_li_def : 17|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schlusslicht_li_def : 18|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Rueckf_li_def : 19|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Nebel_li_def : 20|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schluss_Brems_Nebel_li_def : 21|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schluss_Brems_Nebel_re_def : 22|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schluss_Brems_li_def : 24|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schluss_Nebel_li_def : 25|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_SL_BRL_BLK_li_def : 26|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Brems_Blk_li_def : 27|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Blinker_re_def : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Bremsl_re_def : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schlusslicht_re_def : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Rueckf_re_def : 35|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Nebel_re_def : 36|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schluss_Brems_re_def : 40|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Schluss_Nebel_re_def : 41|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_SL_BRL_BLK_re_def : 42|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Brems_Blk_re_def : 43|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Kennzl_def : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_3_Bremsl_def : 49|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LH_Nebel_mi_def : 50|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Rueckf_mi_def : 51|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LH_Bremsl_li_ges_def : 54|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LH_Bremsl_re_ges_def : 55|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 134 LWI_01: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LWI_Sensorstatus : 12|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LWI_QBit_Sub_Daten : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LWI_QBit_Lenkradwinkel : 15|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LWI_Lenkradwinkel : 16|13@1+ (0.1,0) [0|800] \"Unit_DegreOfArc\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LWI_VZ_Lenkradwinkel : 29|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ LWI_VZ_Lenkradw_Geschw : 30|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ LWI_Lenkradw_Geschw : 31|9@1+ (5,0) [0|2500] \"Unit_DegreOfArcPerSecon\" Vector__XXX\n SG_ LWI_Sub_Daten : 40|16@1+ (1,0) [0|65535] \"\" Vector__XXX\n\nBO_ 263 Motor_04: 8 Motor_Diesel_MQB\n SG_ MO_Istgang : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_Sollgang : 12|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_Oeldruck : 16|8@1+ (0.04,0) [0|10] \"Unit_Bar\" Gateway_MQB\n SG_ MO_Anzeigedrehz : 24|12@1+ (3,0) [0|12282] \"Unit_MinutInver\" Gateway_MQB\n SG_ MO_Schaltempf_verfbar : 38|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Ladedruck : 39|9@1+ (0.01,0) [0|5.1] \"Unit_Bar\" Gateway_MQB\n SG_ MO_KVS : 48|15@1+ (1,0) [0|32767] \"Unit_MicroLiter\" Gateway_MQB\n SG_ MO_KVS_Ueberlauf : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 1600 Motor_07: 8 Motor_Diesel_MQB\n SG_ MO_QBit_Ansaugluft_Temp : 0|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_QBit_Oel_Temp : 1|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_QBit_Kuehlmittel_Temp : 2|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ MO_Stellgliedtest_Soundaktuator : 3|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Fehler_HV_Netz : 4|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_aktives_Getriebeheizen : 5|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Absperrventil_oeffnen : 6|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Ansaugluft_Temp : 8|8@1+ (0.75,-48) [-48|141.75] \"Unit_DegreCelsi\" Gateway_MQB\n SG_ MO_Oel_Temp : 16|8@1+ (1,-60) [-60|192] \"Unit_DegreCelsi\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Kuehlmittel_Temp : 24|8@1+ (0.75,-48) [-48|141.75] \"Unit_DegreCelsi\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ MO_Hoeheninfo : 32|8@1+ (0.00781,0) [0|1.98374] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Kennfeldk : 40|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Versionsinfo : 41|6@1+ (1,0) [0|63] \"\" Gateway_MQB\n SG_ MO_Getriebe_kuehlen : 47|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Mom_Traegheit_02 : 48|5@1+ (0.01,0) [0|0.31] \"Unit_KiloGramMeterSquar\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Heizungspumpenansteuerung : 53|4@1+ (10,0) [0|100] \"Unit_PerCent\" Gateway_MQB\n SG_ MO_SpannungsAnf : 57|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Nachlaufzeit_Heizungspumpe : 58|6@1+ (15,0) [0|945] \"Unit_Secon\" Gateway_MQB\n\nBO_ 1607 Motor_09: 8 Motor_Diesel_MQB\n SG_ MO_ITM_Kuehlmittel_Temp : 0|8@1+ (0.75,-48) [-45.75|143.25] \"Unit_DegreCelsi\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_E85_Sensor : 8|4@1+ (10,0) [0|100] \"Unit_PerCent\" Gateway_MQB\n SG_ SCR_Anz_Motorstarts : 12|4@1+ (1,0) [0|8] \"\" Gateway_MQB\n SG_ SCR_Reichweite : 16|15@1+ (1,0) [0|32766] \"\" Gateway_MQB\n SG_ SCR_Warnstufe_1 : 32|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ SCR_Warnstufe_2 : 33|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ SCR_Text : 34|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n SG_ SCR_Akustik : 37|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Kraftstofffilter_Wasser : 40|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ SCR_Systemfehler : 41|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ SCR_Inducement_Strategie : 42|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_CO2_Faktor : 44|12@1+ (1,0) [1|4094] \"Unit_GramPerLiter\" Gateway_MQB\n\nBO_ 167 Motor_11: 8 Motor_Diesel_MQB\n SG_ Motor_11_CRC : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ Motor_11_BZ : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Mom_Soll_Roh : 12|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Mom_Ist_Summe : 22|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,SAK_MQB\n SG_ MO_Mom_Traegheit_Summe : 32|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Mom_Soll_gefiltert : 42|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Mom_Schub : 52|9@1+ (1,-509) [-509|0] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Status_Normalbetrieb_01 : 61|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_erste_Ungenauschwelle : 62|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_QBit_Motormomente : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 168 Motor_12: 8 Motor_Diesel_MQB\n SG_ Motor_12_CRC : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ Motor_12_BZ : 8|4@1+ (1,0) [0|15] \"\" BMS_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ MO_Mom_neg_verfuegbar : 12|9@1+ (1,-509) [-509|0] \"Unit_NewtoMeter\" Gateway_MQB\n SG_ MO_Mom_Begr_stat : 21|9@1+ (1,0) [0|509] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Mom_Begr_dyn : 30|10@1+ (1,-509) [-509|509] \"Unit_NewtoMeter\" Gateway_MQB\n SG_ MO_Momentenintegral_02 : 40|7@1+ (1,0) [0|100] \"Unit_PerCent\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_QBit_Drehzahl_01 : 47|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ MO_Drehzahl_01 : 48|16@1+ (0.25,0) [0|16383] \"Unit_MinutInver\" BMS_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,SAK_MQB\n\nBO_ 958 Motor_14: 8 Motor_Diesel_MQB\n SG_ MO_StartStopp_Status : 12|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_StartStopp_Wiederstart : 14|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_StartStopp_Motorstopp : 15|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Freig_Reku : 16|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Kl_75 : 18|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Kl_50 : 19|1@1+ (1,0) [0|1] \"\" Gateway_MQB,LEH_MQB\n SG_ MO_Gangposition : 20|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_StartStopp_Fahrerwunsch : 24|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_HYB_Fahrbereitschaft : 26|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB\n SG_ MO_Ext_E_Fahrt_aktiv : 27|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Fahrer_bremst : 28|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_QBit_Fahrer_bremst : 29|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_BLS : 30|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Konsistenz_Bremsped : 31|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Timeout_ESP : 32|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Klima_Eingr : 33|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Aussp_Anlass : 35|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Freig_Anlass : 36|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Kuppl_schalter : 37|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Interlock : 38|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Motor_laeuft : 39|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Kickdown : 40|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Status_Zylabschalt_01 : 41|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_EKlKomLeiRed : 42|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Handshake_STH : 44|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_BKV_Unterdruckwarnung : 45|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Freigabe_Segeln : 46|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_PTC_Status : 47|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n SG_ MO_QBit_Gangposition : 50|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Signalquelle_Gangposition : 51|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Remotestart_Betrieb : 52|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 1631 Motor_16: 8 Motor_Diesel_MQB\n SG_ TSK_QBit_Steigung : 12|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_QBit_Fahrzeugmasse : 13|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_SpannungsAnf_02 : 14|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_DPF_reg : 16|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Heizstrom_EKAT : 17|7@1+ (1,0) [0|126] \"Unit_Amper\" Gateway_MQB\n SG_ MO_Heizstrom_SCR : 24|6@1+ (1,0) [0|62] \"Unit_Amper\" Gateway_MQB\n SG_ TSK_Fahrzeugmasse_02 : 48|8@1+ (32,0) [0|8128] \"Unit_KiloGram\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_Steigung : 56|8@1+ (0.8,-101.6) [-101.6|101.6] \"Unit_PerCent\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 812 Motor_17: 8 Motor_Diesel_MQB\n SG_ MO_Prio_MAX_Wunschdrehzahl : 12|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Prio_MIN_Wunschdrehzahl : 13|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Luftpfad_aktiv : 14|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ MO_v_Begrenz_Aktivierbar : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ MO_Drehzahlbeeinflussung : 16|8@1+ (0.39,0) [0|99.45] \"Unit_PerCent\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_MIN_Wunschdrehzahl : 24|8@1+ (25,0) [0|6350] \"Unit_MinutInver\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_MAX_Wunschdrehzahl : 32|9@1+ (25,0) [0|12750] \"Unit_MinutInver\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Charisma_FahrPr : 41|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_Charisma_Status : 45|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n\nBO_ 1648 Motor_18: 8 Motor_Diesel_MQB\n SG_ MO_Hybrid_StartStopp_LED : 43|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Eis_Offroad_LED : 45|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Anzahl_Abgesch_Zyl : 47|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n SG_ MO_Zylabsch_Texte : 50|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_E85_BS_Texte : 52|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n SG_ MO_Drehzahl_Warnung : 55|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_obere_Drehzahlgrenze : 56|8@1+ (50,0) [50|12750] \"Unit_MinutInver\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 289 Motor_20: 8 Motor_Diesel_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|255] \"\" XXX\n SG_ MO_Fahrpedalrohwert_01 : 12|8@1+ (0.4,0) [0|101.6] \"Unit_PerCent\" Airbag_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_QBit_Fahrpedalwerte_01 : 20|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Fahrpedalgradient : 21|8@1+ (25,0) [0|6350] \"Unit_PerCentPerSecon\" Airbag_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Sig_Fahrpedalgradient : 29|1@1+ (1,0) [0|1] \"\" Airbag_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_rel_Saugrohrdruck : 30|6@1+ (18,0) [0|1116] \"Unit_MilliBar\" Gateway_MQB\n SG_ MO_rel_Saugrohrdruck_gem_err : 36|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Moment_im_Leerlauf : 37|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Schubabschaltung : 38|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Solldrehz_Leerlauf : 40|8@1+ (10,0) [0|2540] \"Unit_MinutInver\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 967 Motor_26: 8 Motor_Diesel_MQB\n SG_ MO_HYB_Status_HV_Ladung : 8|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n SG_ WIV_Anzeige_aktiv : 12|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Oelmin_Warn : 13|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Sensorfehler : 14|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Schieflage : 15|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Oelstand : 16|4@1+ (12.5,0) [0|100] \"Unit_PerCent\" Gateway_MQB\n SG_ MO_Zustand_HWP : 20|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ WIV_Oelsystem_aktiv : 24|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_nicht_betriebswarm : 25|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Ueberfuell_Warn : 26|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_laufender_Motor : 27|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Text_1 : 28|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Text_2 : 29|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Text_3 : 30|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Text_4 : 31|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Text_Motorstart : 32|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_HYB_Text_5 : 36|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Text_6 : 37|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_HYB_Text_7 : 38|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Text_Partikelfil_Reg : 41|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Oelmenge : 43|5@1+ (125,0) [0|3875] \"Unit_MilliLiter\" Gateway_MQB\n SG_ MO_Systemlampe : 48|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_OBD2_Lampe : 49|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Heissleuchte : 50|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Partikel_Lampe : 51|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Winterfahrprog : 52|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WIV_Oelstand_nicht_vorhanden : 53|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_nachfuellanzeige_ein : 54|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Ueberfuell_deaktiv : 55|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Unterfuell_Warn : 56|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Tankdeckel_Lampe : 57|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Text_Tankdeckelwarn : 58|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WIV_Oeldr_Warn_Motor : 60|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 1601 Motor_Code_01: 8 Motor_Diesel_MQB\n SG_ Motor_Code_01_CRC : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n SG_ Motor_Code_01_BZ : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_Faktor_Momente_02 : 12|2@1+ (1,0) [0|3] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Hybridfahrzeug : 14|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ MO_Code : 16|8@1+ (1,0) [0|255] \"\" Gateway_MQB,SAK_MQB\n SG_ MO_Getriebe_Code : 24|6@1+ (1,0) [0|63] \"\" Gateway_MQB\n SG_ MO_StartStopp_Codiert : 30|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Anzahl_Zyl : 32|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ MO_Kraftstoffart : 36|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Hubraum : 40|7@1+ (0.1,0) [0|12.7] \"Unit_Liter\" Gateway_MQB\n SG_ MO_Ansaugsystem : 47|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ MO_Leistung : 48|9@1+ (1,0) [0|511] \"Unit_KiloWatt\" Gateway_MQB\n SG_ MO_Abgastyp_EOBD : 57|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB,LEH_MQB\n SG_ MO_Abgastyp_OBD : 58|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB,LEH_MQB\n SG_ MO_DPF_verbaut : 59|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ TSK_Codierung : 60|3@1+ (1,0) [0|7] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ MO_Einspritzart : 63|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n\nBO_ 157 Motor_Hybrid_01: 8 Motor_Hybrid_MQB\n SG_ Motor_Hybrid_01_CRC : 0|8@1+ (1,0) [0|255] \"\" Getriebe_DQ_Hybrid_MQB\n SG_ Motor_Hybrid_01_BZ : 8|4@1+ (1,0) [0|15] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_IstStatusK0 : 12|2@1+ (1,0) [0|3] \"\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_max_ind_VM_Mom : 16|10@1+ (1,0) [0|1021] \"Unit_NewtoMeter\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_Zielzustand : 26|3@1+ (1,0) [0|7] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_Startmodus : 29|3@1+ (1,0) [0|7] \"\" Vector__XXX\n SG_ MO_HYB_Startmodus_PQ3x : 32|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_Stoppmodus : 33|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_VM_Mom_oE : 40|10@1+ (1,-100) [-100|922] \"Unit_NewtoMeter\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_VM_aktiv : 50|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_Schaltverhinderung : 51|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB\n\nBO_ 811 Motor_Hybrid_02: 8 Motor_Hybrid_MQB\n SG_ MO_HYB_E_Faktor : 12|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_Drehzahl_VM : 16|16@1+ (0.25,0) [0|16256] \"Unit_MinutInver\" Getriebe_DQ_Hybrid_MQB\n SG_ MO_HYB_LowSpeedModus : 32|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB\n\nBO_ 2600468501 NMH_Airbag_01: 8 Airbag_MQB\n SG_ NM_Airbag_01_SNI : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Airbag_01_NM_State : 16|6@1+ (1,0) [0|63] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ NM_Airbag_01_Car_Wakeup : 22|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ NM_Airbag_01_Wakeup : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Airbag_01_NM_aktiv_KL15 : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Airbag_01_NM_aktiv_Diagnose : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Airbag_01_NM_aktiv_Tmin : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Airbag_01_UDS_CC : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 2600468604 NMH_EMotor_01: 8 LEH_MQB\n SG_ NM_EMotor_01_SNI : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_EMotor_01_NM_State : 16|6@1+ (1,0) [0|63] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ NM_EMotor_01_Car_Wakeup : 22|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ NM_EMotor_01_Wakeup : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_EMotor_01_NM_aktiv_KL15 : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_EMotor_01_NM_aktiv_Diagnose : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_EMotor_01_NM_aktiv_Tmin : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_EMotor_01_NL_Daten_EEPROM : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_EMotor_01_UDS_CC : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 2600468496 NMH_Gateway: 8 Gateway_MQB\n SG_ NM_Gateway_SNI : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Gateway_NM_State : 16|6@1+ (1,0) [0|63] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ NM_Gateway_Car_Wakeup : 22|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_Wakeup : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Gateway_NM_aktiv_KL15 : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_NM_aktiv_Diagnose : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_NM_aktiv_Tmin : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_ACAN_Aktivitaet : 35|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_FCAN_Aktivitaet : 36|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_KCAN_Aktivitaet : 37|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_ICAN_Aktivitaet : 38|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_DiagCAN_Aktivitaet : 39|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_ECAN_Aktivitaet : 40|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_Energie_LIN_Aktivi000 : 41|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_Bedien_LIN_Aktivitaet : 42|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_EM_Aktivitaet : 43|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_NL_EM : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_NL_Shutdown : 49|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_NL_Spg_Messung : 50|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_NL_Wakeup_Monitor : 51|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Gateway_UDS_CC : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 2600468599 NMH_Getriebe_01: 8 Getriebe_DQ_Hybrid_MQB\n SG_ NM_Getriebe_01_SNI : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_State : 16|6@1+ (1,0) [0|63] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ NM_Getriebe_01_Car_Wakeup : 22|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ NM_Getriebe_01_Wakeup : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_aktiv_KL15 : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_aktiv_Diagnose : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_aktiv_Tmin : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_aktiv_v_gr_0 : 35|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_aktiv_Pos_Erk : 36|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NM_aktiv_Umg_Bed : 37|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_NL_Daten_EEPROM : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Getriebe_01_UDS_CC : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 2600468603 NMH_Hybrid_01: 8 BMS_MQB\n SG_ NM_Hybrid_01_SNI : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Hybrid_01_NM_State : 16|6@1+ (1,0) [0|63] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ NM_Hybrid_01_Car_Wakeup : 22|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ NM_Hybrid_01_Wakeup : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_Hybrid_01_NM_aktiv_KL15 : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Hybrid_01_NM_aktiv_Diagnose : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Hybrid_01_NM_aktiv_Tmin : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Hybrid_01_NL_Daten_EEPROM : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Hybrid_01_NL_Luefter : 49|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_Hybrid_01_UDS_CC : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 2600468598 NMH_MO_01: 8 Motor_Diesel_MQB\n SG_ NM_MO_01_SNI : 0|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_MO_01_NM_State : 16|6@1+ (1,0) [0|63] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB,Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ NM_MO_01_Car_Wakeup : 22|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ NM_MO_01_Wakeup : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ NM_MO_01_NM_aktiv_KL15 : 32|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NM_aktiv_Diagnose : 33|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NM_aktiv_Tmin : 34|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NM_aktiv_HV_Abschaltung : 35|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NM_aktiv_EKP_Vorlauf : 36|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NM_aktiv_STH_Betrieb : 37|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NL_Kuehlerluefter : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NL_Diagnose : 49|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NL_WFS : 50|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NL_EEPROM : 51|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_NL_Sonstige : 52|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ NM_MO_01_UDS_CC : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 913 OBD_01: 8 Motor_Diesel_MQB\n SG_ OBD_Calc_Load_Val : 0|8@1+ (0.39215686275,0) [0|100] \"Unit_PerCent\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Eng_Cool_Temp : 8|8@1+ (1,-40) [-40|215] \"Unit_DegreCelsi\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Abs_Throttle_Pos : 16|8@1+ (0.39215686275,0) [0|100] \"Unit_PerCent\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Abs_Load_Val : 24|16@1+ (0.39215686275,0) [0|25700] \"Unit_PerCent\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Abs_Pedal_Pos : 40|8@1+ (0.39215686275,0) [0|100] \"Unit_PerCent\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Kaltstart_Denominator : 59|1@1+ (1,0) [0|1] \"\" BMS_MQB,LEH_MQB\n SG_ OBD_Minimum_Trip : 60|1@1+ (1,0) [0|1] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Driving_Cycle : 61|1@1+ (1,0) [0|1] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Warm_Up_Cycle : 62|1@1+ (1,0) [0|1] \"\" BMS_MQB,Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n SG_ OBD_Normed_Trip : 63|1@1+ (1,0) [0|1] \"\" BMS_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB,LEH_MQB\n\nBO_ 1630 OBD_Tankgeber_01: 8 Gateway_MQB\n SG_ OBD_TG_F_Status_1 : 0|4@1+ (1,0) [0|15] \"\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_F_Status_2 : 4|4@1+ (1,0) [0|15] \"\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_F_Status_3 : 8|4@1+ (1,0) [0|15] \"\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_F_Status_4 : 12|4@1+ (1,0) [0|15] \"\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_Sens_Rohwert_1 : 16|12@1+ (0.5,0) [0|2047.5] \"Unit_Ohm\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_Sens_Rohwert_2 : 28|12@1+ (0.5,0) [0|2047.5] \"Unit_Ohm\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_Sens_Rohwert_3 : 40|12@1+ (0.5,0) [0|2047.5] \"Unit_Ohm\" Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ OBD_TG_Sens_Rohwert_4 : 52|12@1+ (0.5,0) [0|2047.5] \"Unit_Ohm\" Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 1437 Remotestart_FFB: 8 Gateway_MQB\n SG_ RSF_Tastencode_1 : 0|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ RSF_Tastencode_2 : 8|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ RSF_Tastencode_Maske : 16|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Otto_MQB\n\nBO_ 984 RGS_VL_01: 8 Airbag_MQB\n SG_ RGS_VL_Texte : 12|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ RGS_VL_Charisma_FahrPr : 14|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ RGS_VL_Charisma_Status : 18|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n SG_ RGS_VL_aktiv : 21|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ RGS_VL_PC_Aktuator_Sitz : 25|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ RGS_VL_PC_Aktuator_Schiebedach : 26|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ RGS_VL_PC_Aktuator_Fenster : 27|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ RGS_VL_PC_Aktuator_Warnblinken : 28|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ RGS_VL_Precrash_Basis : 32|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n SG_ RGS_VL_Precrash_Front : 40|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n SG_ RGS_VL_Precrash_Rear : 48|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n\nBO_ 1528 SAK_01: 8 SAK_MQB\n SG_ SAK_Charisma_FahrPr : 16|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ SAK_Charisma_Status : 20|2@1+ (1,0) [0|3] \"\" Gateway_MQB\n\nBO_ 1313 STH_01: 8 Gateway_MQB\n SG_ STH_Funk_ein : 0|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_Funk_aus : 1|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_Zusatzheizung : 2|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_LED : 3|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ STH_Pumpe_ein : 4|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_Geblaese : 5|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_EKP_Anst : 6|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ STH_Start_folgt : 7|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_Ventiloeffnungszeit : 8|6@1+ (1,0) [0|63] \"Unit_Minut\" Vector__XXX\n SG_ STH_Ventil_Status : 14|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_Waermeeintrag : 16|6@1+ (1,0) [0|63] \"\" Vector__XXX\n SG_ STH_KVS : 24|13@1+ (1,0) [0|8191] \"Unit_MilliLiter\" Vector__XXX\n SG_ STH_Fehlerstatus : 37|3@1+ (1,0) [0|7] \"\" Vector__XXX\n SG_ STH_Heizleistung : 40|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ STH_Wassertemp : 48|8@1+ (0.75,-40) [-40|142.25] \"Unit_DegreCelsi\" Vector__XXX\n SG_ STH_Motorvorwaermung : 59|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ STH_Servicemode : 60|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_war_aktiv : 61|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ STH_KVS_Ueberlauf : 62|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STH_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 1172 STS_01: 8 Gateway_MQB\n SG_ STS_01_CRC : 0|8@1+ (1,0) [0|255] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ STS_01_BZ : 8|4@1+ (1,0) [0|15] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ STS_Car_not_under_theft : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Car_under_theft : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Anlassersperre : 15|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Typencodierung : 16|5@1+ (1,0) [0|31] \"\" Vector__XXX\n SG_ STS_LIN_aktiv : 23|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Standlicht : 24|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Fahrlicht : 25|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Alarm_still : 26|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Texte : 27|4@1+ (1,0) [0|15] \"\" Vector__XXX\n SG_ STS_Laderelais : 38|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Summer : 48|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Alarm_Blinker : 50|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Notstart : 51|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Signalhorn : 55|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ STS_Leerlaufschaltung : 56|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n\nBO_ 1413 Systeminfo_01: 8 Gateway_MQB\n SG_ SI_Sammel_SG_Fehler : 0|6@1+ (1,0) [0|60] \"\" Vector__XXX\n SG_ SI_Rollenmode : 6|2@1+ (1,0) [0|3] \"\" Vector__XXX\n SG_ SI_QRS_Mode : 8|1@1+ (1,0) [0|1] \"\" Motor_Diesel_MQB,Motor_Hybrid_MQB,Motor_Otto_MQB\n SG_ SI_T_Mode : 9|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_NWDF : 10|1@1+ (1,0) [0|1] \"\" SAK_MQB\n SG_ SI_NWDF_gueltig : 11|1@1+ (1,0) [0|1] \"\" SAK_MQB\n SG_ SI_Sammelfehler : 12|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ GW_KD_Fehler : 13|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_01 : 16|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_02 : 17|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_03 : 18|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_04 : 19|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_05 : 20|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_06 : 21|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_07 : 22|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_08 : 23|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_09 : 24|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_10 : 25|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_11 : 26|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_12 : 27|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_13 : 28|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_14 : 29|1@1+ (1,0) [0|1] \"\" Vector__XXX\n SG_ SI_BUS_15 : 30|1@1+ (1,0) [0|1] \"\" Vector__XXX\n\nBO_ 288 TSK_06: 8 Motor_Diesel_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_Radbremsmom : 12|12@1+ (8,0) [0|32760] \"Unit_NewtoMeter\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_Status : 24|3@1+ (1,0) [0|7] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_v_Begrenzung_aktiv : 27|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_Standby_Anf_ESP : 28|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ TSK_Freig_Verzoeg_Anf : 30|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_Limiter_ausgewaehlt : 31|1@1+ (1,0) [0|1] \"\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_ax_Getriebe_02 : 48|9@1+ (0.024,-2.016) [-2.016|10.224] \"Unit_MeterPerSeconSquar\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ TSK_Zwangszusch_ESP : 57|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ TSK_zul_Regelabw : 58|6@1+ (0.024,0) [0|1.512] \"Unit_MeterPerSeconSquar\" Gateway_MQB,Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 798 TSK_07: 8 Motor_Diesel_MQB\n SG_ TSK_07_CRC : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n SG_ TSK_07_BZ : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ TSK_Wunschgeschw : 12|10@1+ (0.32,0) [0|326.72] \"Unit_KiloMeterPerHour\" Gateway_MQB\n SG_ TSK_Texte_Primaeranz : 48|5@1+ (1,0) [0|31] \"\" Gateway_MQB\n SG_ TSK_Limiter_Anzeige : 55|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ TSK_Status_Anzeige : 61|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n\nBO_ 1716 VIN_01: 8 Gateway_MQB\n SG_ VIN_01_MUX M : 0|2@1+ (1,0) [0|3] \"\"  Airbag_MQB\n SG_ KS_Geheimnis_1 m0 : 8|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ VIN_4 m1 : 8|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_11 m2 : 8|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ KS_Geheimnis_2 m0 : 16|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ VIN_5 m1 : 16|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_12 m2 : 16|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ KS_Geheimnis_3 m0 : 24|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ VIN_6 m1 : 24|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_13 m2 : 24|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ KS_Geheimnis_4 m0 : 32|8@1+ (1,0) [0|255] \"\" Vector__XXX\n SG_ VIN_7 m1 : 32|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_14 m2 : 32|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_1 m0 : 40|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_8 m1 : 40|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_15 m2 : 40|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_2 m0 : 48|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_9 m1 : 48|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_16 m2 : 48|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_3 m0 : 56|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_10 m1 : 56|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n SG_ VIN_17 m2 : 56|8@1+ (1,0) [0|255] \"\"  Airbag_MQB\n\nBO_ 175 Waehlhebel_03: 4 Waehlhebel_MQB\n SG_ WH_Status_Sperre : 0|3@1+ (1,0) [0|7] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_Initialisierung : 3|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_SensorPos_roh : 4|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_03_BZ : 8|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_SensorPos_roh_inv : 12|4@1+ (1,0) [0|15] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_Testergebnis : 16|8@1+ (1,0) [0|255] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_Test_Aktiv : 24|1@1+ (1,0) [0|1] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n SG_ WH_Status : 25|7@1+ (1,0) [0|127] \"\" Getriebe_DQ_Hybrid_MQB,Getriebe_DQ_MQB\n\nBO_ 916 WBA_03: 8 Getriebe_DQ_Hybrid_MQB\n SG_ WBA_03_CRC : 0|8@1+ (1,0) [0|255] \"\" Gateway_MQB\n SG_ WBA_03_BZ : 8|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ WBA_Fahrstufe_02 : 12|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ WBA_ZielFahrstufe : 16|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ WBA_GE_Warnung_02 : 20|4@1+ (1,0) [0|15] \"\" Gateway_MQB\n SG_ WBA_eing_Gang_02 : 24|4@1+ (1,0) [0|15] \"\" Gateway_MQB,Motor_Diesel_MQB,Motor_Otto_MQB\n SG_ WBA_GE_Texte : 28|3@1+ (1,0) [0|7] \"\" Gateway_MQB\n SG_ WBA_Segeln_aktiv : 31|1@1+ (1,0) [0|1] \"\" Gateway_MQB\n SG_ WBA_Schaltschema : 32|5@1+ (1,0) [0|31] \"\" Gateway_MQB\n\nBO_ 1602 WIV_01: 8 Motor_Diesel_MQB\n SG_ WIV_Verschleissindex : 0|16@1+ (2e-8,0) [0|0.00131068] \"\" Gateway_MQB\n SG_ WIV_Russindex : 16|16@1+ (2e-8,0) [0|0.00131068] \"\" Gateway_MQB\n SG_ WIV_t_min : 32|6@1+ (1,0) [0|63] \"Unit_Month\" Gateway_MQB\n SG_ WIV_t_max : 40|6@1+ (1,0) [0|63] \"Unit_Month\" Gateway_MQB\n SG_ WIV_W_min : 48|7@1+ (1000,0) [0|127000] \"Unit_KiloMeter\" Gateway_MQB\n SG_ WIV_W_max : 56|7@1+ (1000,0) [0|127000] \"Unit_KiloMeter\" Gateway_MQB\n\nBO_ 294 HCA_01: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_0X3 : 12|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Assist_Torque : 16|14@1+ (1,0) [0|300] \"Nm\" XXX\n SG_ Assist_Requested : 30|1@1+ (1,0) [0|1] \"\" XXX\n SG_ Assist_VZ : 31|1@1+ (1,0) [0|1] \"\" XXX\n SG_ HCA_Available : 32|1@1+ (1,0) [0|1] \"\" XXX\n SG_ HCA_Standby : 33|1@1+ (1,0) [0|1] \"\" XXX\n SG_ HCA_Active : 34|1@1+ (1,0) [0|1] \"\" XXX\n SG_ SET_ME_0XFE : 40|8@1+ (1,0) [0|255] \"\" XXX\n SG_ SET_ME_0X07 : 48|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 159 LH_EPS_03: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\"  XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ EPS_DSR_Status : 12|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ EPS_Berechneter_LW : 16|12@1+ (0.15,0) [0|613.95] \"Unit_DegreOfArc\"  XXX\n SG_ EPS_BLW_QBit : 30|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ EPS_VZ_BLW : 31|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ EPS_HCA_Status : 32|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ EPS_Lenkmoment : 40|10@1+ (1,0) [0|8] \"Unit_centiNewtoMeter\"  XXX\n SG_ EPS_Lenkmoment_QBit : 54|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ EPS_VZ_Lenkmoment : 55|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ EPS_Lenkungstyp : 60|4@1+ (1,0) [0|15] \"\"  XXX\n\nBO_ 286 VehicleSpeed: 8 XXX\n SG_ VehicleSpeed_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ VehicleSpeed_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Speed : 52|12@1+ (0.125,0) [0|1] \"\" XXX\n\nBO_ 919 LDW_02: 8 XXX\n SG_ LDW_Gong : 12|2@1+ (1,0) [0|3] \"\"  XXX\n SG_ LDW_SW_Warnung_links : 14|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_SW_Warnung_rechts : 15|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_Texte : 16|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ LDW_Seite_DLCTLC : 20|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_Lernmodus : 21|3@1+ (1,0) [0|7] \"\"  XXX\n SG_ LDW_Anlaufsp_VLR : 24|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ LDW_Vib_Amp_VLR : 28|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ LDW_Anlaufzeit_VLR : 32|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ LDW_Lernmodus_rechts : 36|2@1+ (1,0) [0|3] \"\"  XXX\n SG_ LDW_Lernmodus_links : 38|2@1+ (1,0) [0|3] \"\"  XXX\n SG_ LDW_DLC : 40|8@1+ (0.01,-1.25) [-1.25|1.25] \"Unit_Meter\"  XXX\n SG_ LDW_TLC : 48|5@1+ (0.1,0) [0|3] \"Unit_Secon\"  XXX\n SG_ LDW_Warnung_links : 56|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_Warnung_rechts : 57|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_Codierinfo_fuer_VLR : 58|2@1+ (1,0) [0|3] \"\"  XXX\n SG_ LDW_Frontscheibenheizung_aktiv : 60|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_Status_LED_gelb : 61|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_Status_LED_gruen : 62|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ LDW_KD_Fehler : 63|1@1+ (1,0) [0|1] \"\"  XXX\n\nBO_ 780 ACC_02: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\"  XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ ACC_Wunschgeschw : 12|10@1+ (0.32,0) [0.00|326.72] \"Unit_KiloMeterPerHour\"  XXX\n SG_ ACC_Status_Prim_Anz : 22|2@1+ (1.0,0.0) [0.0|3] \"\"  XXX\n SG_ ACC_Abstandsindex : 24|10@1+ (1,0) [1|1021] \"\"  XXX\n SG_ ACC_Akustik : 34|3@1+ (1.0,0.0) [0.0|7] \"\"  XXX\n SG_ ACC_Gesetzte_Zeitluecke : 37|3@1+ (1.0,0.0) [0.0|7] \"\"  XXX\n SG_ ACC_Optischer_Fahrerhinweis : 40|1@1+ (1.0,0.0) [0.0|1] \"\"  XXX\n SG_ ACC_Typ_Tachokranz : 41|1@1+ (1.0,0.0) [0.0|1] \"\"  XXX\n SG_ ACC_Anzeige_Zeitluecke : 42|1@1+ (1.0,0.0) [0.0|1] \"\"  XXX\n SG_ ACC_Tachokranz : 43|1@1+ (1.0,0.0) [0.0|1] \"\"  XXX\n SG_ ACC_Display_Prio : 44|2@1+ (1.0,0.0) [0.0|3] \"\"  XXX\n SG_ ACC_Relevantes_Objekt : 46|2@1+ (1.0,0.0) [0.0|3] \"\"  XXX\n SG_ ACC_Texte_Primaeranz : 48|7@1+ (1.0,0.0) [0.0|127] \"\"  XXX\n SG_ ACC_Wunschgeschw_erreicht : 55|1@1+ (1.0,0.0) [0.0|1] \"\"  XXX\n SG_ ACC_Status_Anzeige : 61|3@1+ (1.0,0.0) [0.0|7] \"\"  XXX\n\nBO_ 302 ACC_07: 8 XXX\n SG_ ACC_07_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ ACC_07_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 264 Fahrwerk_01: 8 XXX\n SG_ Fahrwerk_01_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ Fahrwerk_01_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 695 RCTA_01: 8 XXX\n SG_ RCTA_01_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ RCTA_01_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 783 SWA_01: 8 Gateway_MQB\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\"  Vector__XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\"  Vector__XXX\n SG_ SWA_Anzeigen : 12|4@1+ (1,0) [0|15] \"\"  Kombi_D4\n SG_ SWA_Blindheit_erkannt : 16|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_rel_Nichtverf : 17|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_rel_Fehler : 18|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Sta_aktiv : 19|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Sta_passiv : 20|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Standziele_li : 24|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Kolonne_li : 25|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Infostufe_SWA_li : 26|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Warnung_SWA_li : 27|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Kolonne_mi : 33|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Standziele_re : 40|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Kolonne_re : 41|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Infostufe_SWA_re : 42|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Warnung_SWA_re : 43|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n SG_ SWA_Gischtzaehler : 48|7@1+ (1,0) [0|100] \"Unit_PerCent\"  Vector__XXX\n SG_ SWA_KD_Fehler : 59|1@1+ (1,0) [0|1] \"\"  Vector__XXX\n\nBO_ 804 ACC_04: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\"  XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\"  XXX\n SG_ ACC_Texte_Zusatzanz : 16|6@1+ (1.0,0.0) [0.0|63] \"\"  XXX\n SG_ ACC_Status_Zusatzanz : 22|5@1+ (1.0,0.0) [0.0|31] \"\"  XXX\n SG_ ACC_Texte : 27|5@1+ (1.0,0.0) [0.0|31] \"\"  XXX\n SG_ ACC_Texte_braking_guard : 32|3@1+ (1.0,0.0) [0.0|7] \"\"  XXX\n SG_ ACC_Warnhinweis : 35|1@1+ (1.0,0.0) [0.0|1] \"\"  XXX\n SG_ ACC_Geschw_Zielfahrzeug : 40|10@1+ (0.32,0) [0.00|326.72] \"Unit_KiloMeterPerHour\"  XXX\n SG_ ACC_Charisma_FahrPr : 56|3@1+ (1.0,0.0) [0.0|7] \"\"  XXX\n SG_ ACC_Charisma_Status : 59|2@1+ (1.0,0.0) [0.0|3] \"\"  XXX\n SG_ ACC_Charisma_Umschaltung : 61|2@1+ (1.0,0.0) [0.0|3] \"\"  XXX\n\nBO_ 917 LWR_AFS_01: 8 XXX\n\nBO_ 991 Gateway_76: 8 XXX\n\nBO_ 997 TSG_FT_02: 8 XXX\n SG_ TSG_FT_02_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ TSG_FT_02_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 1175 Parkhilfe_01: 8 XXX\n\nBO_ 427 ESP_33: 8 XXX\n SG_ ESP_33_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ ESP_33_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n\nBO_ 418 ESP_15: 8 XXX\n SG_ ESP_15_CRC : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ ESP_15_BZ : 8|4@1+ (1,0) [0|15] \"\" XXX\n\nBO_ 1122 PSD_04: 8 XXX\n SG_ PSD_Object_Index : 0|6@1+ (1,0) [0|63] \"\" XXX\n\nBO_ 1123 PSD_05: 8 XXX\n SG_ PSD_Current_Route_Index : 0|6@1+ (1,0) [0|63] \"\" XXX\n SG_ Route_Distance_Remaining : 8|5@1+ (1,0) [0|31] \"\" XXX\n\nBO_ 1124 PSD_06: 8 XXX\n\nBO_ 988 Gateway_73: 8 XXX\n\nBO_ 792 Kamera_Status: 8 XXX\n\nBO_ 981 Licht_Anf_01: 8 XXX\n\nBO_ 1440 RLS_01: 8 XXX\n\nBO_ 870 Blinkmodi_02: 8 XXX\n SG_ Hazard_Switch : 20|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Comfort_Signal_Left : 23|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Comfort_Signal_Right : 24|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Left_Turn_Exterior_Bulb_1 : 25|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Right_Turn_Exterior_Bulb_1 : 26|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Left_Turn_Exterior_Bulb_2 : 27|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Right_Turn_Exterior_Bulb_2 : 28|1@1+ (1,0) [0|1] \"\"  XXX\n SG_ Fast_Send_Rate_Active : 37|1@1+ (1,0) [0|1] \"\"  XXX\n\nBO_ 1385 HVEM_04: 8 XXX\n\nBO_ 1605 FLA_01: 8 XXX\n\nBO_ 1624 Licht_vorne_01: 8 XXX\n\nBO_ 1646 Klima_03: 8 XXX\n\nBO_ 1720 Kombi_03: 8 XXX\n\nBO_ 391 EV_Gearshift: 8 XXX\n SG_ CHECKSUM : 0|8@1+ (1,0) [0|255] \"\" XXX\n SG_ COUNTER : 8|4@1+ (1,0) [0|15] \"\" XXX\n SG_ GearPosition : 16|4@1+ (1,0) [0|255] \"\" XXX\n SG_ RegenBrakingMode : 12|2@1+ (1,0) [0|3] \"\" XXX\n\nCM_ SG_ 134 LWI_Lenkradwinkel \"Steering angle WITH variable ratio effect included\";\nCM_ SG_ 159 EPS_HCA_Status \"Status of Heading Control Assist feature\"\nCM_ SG_ 159 EPS_Lenkmoment \"Steering input by driver, torque\";\nCM_ SG_ 159 EPS_VZ_Lenkmoment \"Steering input by driver, direction\";\nCM_ SG_ 159 EPS_Berechneter_LW \"Raw steering angle, degrees\";\nCM_ SG_ 159 EPS_VZ_BLW \"Raw steering angle, direction\"\nCM_ SG_ 173 COUNTERXX \"Message not renamed to COUNTER because J533 rate-limiting makes it look like messages are being lost\";\nCM_ SG_ 294 3 \"May be zero when sent by older cameras\";\nCM_ SG_ 294 7 \"May be zero when sent by older cameras\";\nCM_ SG_ 294 254 \"May be zero when sent by older cameras\";\nCM_ SG_ 294 Assist_Torque \"Heading control input, torque\";\nCM_ SG_ 294 Assist_VZ \"Heading control input, direction (sign)\";\nCM_ SG_ 294 HCA_Available \"Must be 1 for steering rack to accept HCA commands\";\nCM_ SG_ 870 Hazard_Switch \"Four-way flashers active\";\nCM_ SG_ 870 Comfort_Signal_Left \"Comfort turn signal active, left\";\nCM_ SG_ 870 Comfort_Signal_Right \"Comfort turn signal active, right\";\nCM_ SG_ 870 Left_Turn_Exterior_Bulb_1 \"Probably front\";\nCM_ SG_ 870 Right_Turn_Exterior_Bulb_1 \"Probably front\";\nCM_ SG_ 870 Left_Turn_Exterior_Bulb_2 \"Probably rear\";\nCM_ SG_ 870 Right_Turn_Exterior_Bulb_2 \"Probably rear\";\nCM_ SG_ 870 Fast_Send_Rate_Active \"CAN message send rate\";\nCM_ SG_ 919 LDW_DLC \"Probable DLC (distance to line crossing)\";\nCM_ SG_ 919 LDW_TLC \"Probable TLC (time to line crossing)\";\nCM_ SG_ 919 LDW_Unknown \"Might be a steering pressed / driver active flag\";\nCM_ SG_ 919 Alert_Message \"Static table of alert messages to be invoked in the instrument cluster, some with or without beeps, 0 = no current message\";\nCM_ SG_ 919 LDW_Direction \"Left/right indicator for DLC and TLC\";\nCM_ SG_ 919 Right_Lane_Status \"Display brightness range, 0 = no lane, 3 = full brightness\";\nCM_ SG_ 919 Left_Lane_Status \"Display brightness range, 0 = no lane, 3 = full brightness\";\nCM_ SG_ 919 Kombi_Lamp_Orange \"Enables orange LDW light in instrument cluster\";\nCM_ SG_ 919 Kombi_Lamp_Green \"Enables green LDW light in instrument cluster\";\nCM_ SG_ 780 Folgefahrt \"Following another vehicle\";\nCM_ SG_ 780 SetAbstand \"Set following distance\";\nCM_ SG_ 780 Abstand \"Following distance\";\nCM_ SG_ 780 SetSpeed \"ACC set speed\";\nCM_ SG_ 391 GearPosition \"Traditional PRND plus B-mode aggressive regen, B-mode mapped to Drive\";\nCM_ SG_ 960 ZAS_Kl_15 \"Indicates ignition on\";\nVAL_ 159 EPS_HCA_Status 0 \"disabled\" 1 \"initializing\" 2 \"fault\" 3 \"ready\" 4 \"rejected\" 5 \"active\";\nVAL_ 173 GE_Fahrstufe 5 \"P\" 6 \"R\" 7 \"N\" 8 \"D\" 9 \"S\" 10 \"E\" 14 \"T\";\nVAL_ 391 GearPosition 2 \"P\" 3 \"R\" 4 \"N\" 5 \"D\" 6 \"D\";\nVAL_ 391 RegenBrakingMode 0 \"default\" 1 \"B1\" 2 \"B2\" 3 \"B3\";\nVAL_ 870 Fast_Send_Rate_Active 0 \"1 Hz\" 1 \"50 Hz\";\n"
  },
  {
    "path": "panda/.gitignore",
    "content": "*.pyc\n.*.swp\n.*.swo\n*.o\n*.so\n*.os\n*.d\n*.dump\na.out\n*~\n.#*\ndist/\npandacan.egg-info/\nboard/obj/\nexamples/output.csv\n.DS_Store\n.vscode*\nnosetests.xml\n.mypy_cache/\n.sconsign.dblite\n"
  },
  {
    "path": "panda/__init__.py",
    "content": "# flake8: noqa\n# pylint: skip-file\nfrom .python import Panda, PandaWifiStreaming, PandaDFU, flash_release, \\\n                    BASEDIR, ensure_st_up_to_date, PandaSerial, \\\n                    DEFAULT_FW_FN, DEFAULT_H7_FW_FN, MCU_TYPE_H7, MCU_TYPE_F4\n\nfrom .python.config import BOOTSTUB_ADDRESS, BLOCK_SIZE_FX, APP_ADDRESS_FX, \\\n                           BLOCK_SIZE_H7, APP_ADDRESS_H7, DEVICE_SERIAL_NUMBER_ADDR_H7, \\\n                           DEVICE_SERIAL_NUMBER_ADDR_FX\n"
  },
  {
    "path": "panda/board/Makefile",
    "content": ""
  },
  {
    "path": "panda/board/README.md",
    "content": "Dependencies\n--------\n\n**Mac**\n\n```\nxcode-select --install\n./get_sdk_mac.sh\n```\n\n**Debian / Ubuntu**\n\n```\n./get_sdk.sh\n```\n\n\nProgramming\n----\n\n**Panda**\n\n```\nscons -u # Compile\n./flash.sh # Compile & Flash\n```\n\nTroubleshooting\n----\n\nIf your panda will not flash and is quickly blinking a single Green LED, use:\n```\n./recover.sh\n```\n\n\n[dfu-util](http://github.com/dsigma/dfu-util.git) for flashing\n"
  },
  {
    "path": "panda/board/SConscript",
    "content": "import os\nimport subprocess\n\nPREFIX = \"arm-none-eabi-\"\nBUILDER = \"DEV\"\n\nif os.getenv(\"PEDAL\"):\n  PROJECT = \"pedal\"\n  STARTUP_FILE = \"stm32fx/startup_stm32f205xx.s\"\n  LINKER_SCRIPT = \"stm32fx/stm32fx_flash.ld\"\n  APP_START_ADDRESS = \"0x8004000\"\n  MAIN = \"pedal/main.c\"\n  PROJECT_FLAGS = [\n    \"-mcpu=cortex-m3\",\n    \"-msoft-float\",\n    \"-DSTM32F2\",\n    \"-DSTM32F205xx\",\n    \"-O2\",\n    \"-DPEDAL\",\n  ]\n  if os.getenv(\"PEDAL_USB\"):\n    PROJECT = \"pedal_usb\"\n    PROJECT_FLAGS.append(\"-DPEDAL_USB\")\n\nelif os.getenv(\"PANDA_H7\"):\n  PROJECT = \"panda_h7\"\n  STARTUP_FILE = \"stm32h7/startup_stm32h7x5xx.s\"\n  LINKER_SCRIPT = \"stm32h7/stm32h7x5_flash.ld\"\n  APP_START_ADDRESS = \"0x8020000\"\n  MAIN = \"main.c\"\n  PROJECT_FLAGS = [\n    \"-mcpu=cortex-m7\",\n    \"-mhard-float\",\n    \"-DSTM32H7\",\n    \"-DSTM32H725xx\",\n    \"-mfpu=fpv5-d16\",\n    \"-fsingle-precision-constant\",\n    \"-Os\",\n    \"-g\",\n    \"-DPANDA\",\n  ]\n\nelse:\n  PROJECT = \"panda\"\n  STARTUP_FILE = \"stm32fx/startup_stm32f413xx.s\"\n  LINKER_SCRIPT = \"stm32fx/stm32fx_flash.ld\"\n  APP_START_ADDRESS = \"0x8004000\"\n  MAIN = \"main.c\"\n  PROJECT_FLAGS = [\n    \"-mcpu=cortex-m4\",\n    \"-mhard-float\",\n    \"-DSTM32F4\",\n    \"-DSTM32F413xx\",\n    \"-mfpu=fpv4-sp-d16\",\n    \"-fsingle-precision-constant\",\n    \"-Os\",\n    \"-g\",\n    \"-DPANDA\",\n  ]\n\n  if FindFile('dp_vw_panda', '/data/params/d') != None:\n    with open('/data/params/d/dp_vw_panda') as f:\n      if (int(f.read().strip())) == 1:\n        PROJECT_FLAGS += ['-Dvw']\n\ndef get_version(builder, build_type):\n  try:\n    git = subprocess.check_output([\"git\", \"rev-parse\", \"--short=8\", \"HEAD\"], encoding='utf8').strip()\n  except subprocess.CalledProcessError:\n    git = \"unknown\"\n  return f\"{builder}-{git}-{build_type}\"\n\n\ndef to_c_uint32(x):\n  nums = []\n  for _ in range(0x20):\n    nums.append(x % (2**32))\n    x //= (2**32)\n  return \"{\" + 'U,'.join(map(str, nums)) + \"U}\"\n\n\ndef get_key_header(name):\n  from Crypto.PublicKey import RSA\n\n  public_fn = File(f'../certs/{name}.pub').srcnode().abspath\n  rsa = RSA.importKey(open(public_fn).read())\n  assert(rsa.size_in_bits() == 1024)\n\n  rr = pow(2**1024, 2, rsa.n)\n  n0inv = 2**32 - pow(rsa.n, -1, 2**32)\n\n  r = [\n    f\"RSAPublicKey {name}_rsa_key = {{\",\n    f\"  .len = 0x20,\",\n    f\"  .n0inv = {n0inv}U,\",\n    f\"  .n = {to_c_uint32(rsa.n)},\",\n    f\"  .rr = {to_c_uint32(rr)},\",\n    f\"  .exponent = {rsa.e},\",\n    f\"}};\",\n  ]\n  return r\n\n\ndef objcopy(source, target, env, for_signature):\n    return '$OBJCOPY -O binary %s %s' % (source[0], target[0])\n\n\nlinkerscript_fn = File(LINKER_SCRIPT).srcnode().abspath\n\nflags = [\n  \"-Wall\",\n  \"-Wextra\",\n  \"-Wstrict-prototypes\",\n  \"-Werror\",\n  \"-mlittle-endian\",\n  \"-mthumb\",\n  \"-nostdlib\",\n  \"-fno-builtin\",\n  f\"-T{linkerscript_fn}\",\n  \"-std=gnu11\",\n] + PROJECT_FLAGS\n\n\nif os.getenv(\"RELEASE\"):\n  BUILD_TYPE = \"RELEASE\"\n  cert_fn = os.getenv(\"CERT\")\n  assert cert_fn is not None, 'No certificate file specified. Please set CERT env variable'\n  assert os.path.exists(cert_fn), 'Certificate file not found. Please specify absolute path'\nelse:\n  BUILD_TYPE = \"DEBUG\"\n  cert_fn = File(\"../certs/debug\").srcnode().abspath\n  flags += [\"-DALLOW_DEBUG\"]\n\nincludes = [\n  \"stm32fx/inc\",\n  \"stm32h7/inc\",\n  \"..\",\n  \".\",\n]\n\npanda_env = Environment(\n  ENV=os.environ,\n  CC=PREFIX + 'gcc',\n  AS=PREFIX + 'gcc',\n  OBJCOPY=PREFIX + 'objcopy',\n  OBJDUMP=PREFIX + 'objdump',\n  ASCOM=\"$AS $ASFLAGS -o $TARGET -c $SOURCES\",\n  CFLAGS=flags,\n  ASFLAGS=flags,\n  LINKFLAGS=flags,\n  CPPPATH=includes,\n  BUILDERS={\n    'Objcopy': Builder(generator=objcopy, suffix='.bin', src_suffix='.elf')\n  }\n)\n\n# Common autogenerated includes\nversion = f'const uint8_t gitversion[] = \"{get_version(BUILDER, BUILD_TYPE)}\";'\ngitversion = panda_env.Textfile(\"obj/gitversion.h\", [version, \"\"])\nIgnore('bootstub.o', gitversion)\nRequires('bootstub.o', gitversion)\nIgnore('main.o', gitversion)\nRequires('main.o', gitversion)\n\ncerts = [get_key_header(n) for n in [\"debug\", \"release\"]]\ncertheader = panda_env.Textfile(\"obj/cert.h\", certs + [\"\"])\n\nstartup = panda_env.Object(STARTUP_FILE)\n\n# Bootstub\ncrypto = [\"../crypto/rsa.c\", \"../crypto/sha.c\"]\nbootstub_elf = panda_env.Program(f\"obj/bootstub.{PROJECT}.elf\", [startup] + crypto + [\"bootstub.c\"])\nbootstub_bin = panda_env.Objcopy(f\"obj/bootstub.{PROJECT}.bin\", bootstub_elf)\n\n# Build main\nmain_elf = panda_env.Program(f\"obj/{PROJECT}.elf\", [startup, MAIN],\n  LINKFLAGS=[f\"-Wl,--section-start,.isr_vector={APP_START_ADDRESS}\"] + flags)\nmain_bin = panda_env.Objcopy(f\"obj/{PROJECT}.bin\", main_elf)\n\n# Sign main\nsign_py = File(\"../crypto/sign.py\").srcnode().abspath\npanda_bin_signed = panda_env.Command(f\"obj/{PROJECT}.bin.signed\", main_bin, f\"SETLEN=1 {sign_py} $SOURCE $TARGET {cert_fn}\")\n"
  },
  {
    "path": "panda/board/__init__.py",
    "content": ""
  },
  {
    "path": "panda/board/boards/black.h",
    "content": "// ///////////////////// //\n// Black Panda + Harness //\n// ///////////////////// //\n\nvoid black_enable_can_transceiver(uint8_t transceiver, bool enabled) {\n  switch (transceiver){\n    case 1U:\n      set_gpio_output(GPIOC, 1, !enabled);\n      break;\n    case 2U:\n      set_gpio_output(GPIOC, 13, !enabled);\n      break;\n    case 3U:\n      set_gpio_output(GPIOA, 0, !enabled);\n      break;\n    case 4U:\n      set_gpio_output(GPIOB, 10, !enabled);\n      break;\n    default:\n      puts(\"Invalid CAN transceiver (\"); puth(transceiver); puts(\"): enabling failed\\n\");\n      break;\n  }\n}\n\nvoid black_enable_can_transceivers(bool enabled) {\n  for(uint8_t i=1U; i<=4U; i++){\n    // Leave main CAN always on for CAN-based ignition detection\n    if((car_harness_status == HARNESS_STATUS_FLIPPED) ? (i == 3U) : (i == 1U)){\n      black_enable_can_transceiver(i, true);\n    } else {\n      black_enable_can_transceiver(i, enabled);\n    }\n  }\n}\n\nvoid black_set_led(uint8_t color, bool enabled) {\n  switch (color){\n    case LED_RED:\n      set_gpio_output(GPIOC, 9, !enabled);\n      break;\n     case LED_GREEN:\n      set_gpio_output(GPIOC, 7, !enabled);\n      break;\n    case LED_BLUE:\n      set_gpio_output(GPIOC, 6, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid black_set_gps_load_switch(bool enabled) {\n  set_gpio_output(GPIOC, 12, enabled);\n}\n\nvoid black_set_usb_load_switch(bool enabled) {\n  set_gpio_output(GPIOB, 1, !enabled);\n}\n\nvoid black_set_usb_power_mode(uint8_t mode) {\n  bool valid = false;\n  switch (mode) {\n    case USB_POWER_CLIENT:\n      black_set_usb_load_switch(false);\n      valid = true;\n      break;\n    case USB_POWER_CDP:\n      black_set_usb_load_switch(true);\n      valid = true;\n      break;\n    default:\n      puts(\"Invalid USB power mode\\n\");\n      break;\n  }\n  if (valid) {\n    usb_power_mode = mode;\n  }\n}\n\nvoid black_set_gps_mode(uint8_t mode) {\n  switch (mode) {\n    case GPS_DISABLED:\n      // GPS OFF\n      set_gpio_output(GPIOC, 14, 0);\n      set_gpio_output(GPIOC, 5, 0);\n      break;\n    case GPS_ENABLED:\n      // GPS ON\n      set_gpio_output(GPIOC, 14, 1);\n      set_gpio_output(GPIOC, 5, 1);\n      break;\n    case GPS_BOOTMODE:\n      set_gpio_output(GPIOC, 14, 1);\n      set_gpio_output(GPIOC, 5, 0);\n      break;\n    default:\n      puts(\"Invalid GPS mode\\n\");\n      break;\n  }\n}\n\nvoid black_set_can_mode(uint8_t mode){\n  switch (mode) {\n    case CAN_MODE_NORMAL:\n    case CAN_MODE_OBD_CAN2:\n      if ((bool)(mode == CAN_MODE_NORMAL) != (bool)(car_harness_status == HARNESS_STATUS_FLIPPED)) {\n        // B12,B13: disable OBD mode\n        set_gpio_mode(GPIOB, 12, MODE_INPUT);\n        set_gpio_mode(GPIOB, 13, MODE_INPUT);\n\n        // B5,B6: normal CAN2 mode\n        set_gpio_alternate(GPIOB, 5, GPIO_AF9_CAN2);\n        set_gpio_alternate(GPIOB, 6, GPIO_AF9_CAN2);\n      } else {\n        // B5,B6: disable normal CAN2 mode\n        set_gpio_mode(GPIOB, 5, MODE_INPUT);\n        set_gpio_mode(GPIOB, 6, MODE_INPUT);\n\n        // B12,B13: OBD mode\n        set_gpio_alternate(GPIOB, 12, GPIO_AF9_CAN2);\n        set_gpio_alternate(GPIOB, 13, GPIO_AF9_CAN2);\n      }\n      break;\n    default:\n      puts(\"Tried to set unsupported CAN mode: \"); puth(mode); puts(\"\\n\");\n      break;\n  }\n}\n\nbool black_check_ignition(void){\n  // ignition is checked through harness\n  return harness_check_ignition();\n}\n\nvoid black_init(void) {\n  common_init_gpio();\n\n  // A8,A15: normal CAN3 mode\n  set_gpio_alternate(GPIOA, 8, GPIO_AF11_CAN3);\n  set_gpio_alternate(GPIOA, 15, GPIO_AF11_CAN3);\n\n  // C0: OBD_SBU1 (orientation detection)\n  // C3: OBD_SBU2 (orientation detection)\n  set_gpio_mode(GPIOC, 0, MODE_ANALOG);\n  set_gpio_mode(GPIOC, 3, MODE_ANALOG);\n\n  // Set default state of GPS\n  current_board->set_gps_mode(GPS_ENABLED);\n\n  // C10: OBD_SBU1_RELAY (harness relay driving output)\n  // C11: OBD_SBU2_RELAY (harness relay driving output)\n  set_gpio_mode(GPIOC, 10, MODE_OUTPUT);\n  set_gpio_mode(GPIOC, 11, MODE_OUTPUT);\n  set_gpio_output_type(GPIOC, 10, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_output_type(GPIOC, 11, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_output(GPIOC, 10, 1);\n  set_gpio_output(GPIOC, 11, 1);\n\n  // Turn on GPS load switch.\n  black_set_gps_load_switch(true);\n\n  // Turn on USB load switch.\n  black_set_usb_load_switch(true);\n\n  // Set right power mode\n  black_set_usb_power_mode(USB_POWER_CDP);\n\n  // Initialize harness\n  harness_init();\n\n  // Enable CAN transceivers\n  black_enable_can_transceivers(true);\n\n  // Disable LEDs\n  black_set_led(LED_RED, false);\n  black_set_led(LED_GREEN, false);\n  black_set_led(LED_BLUE, false);\n\n  // Set normal CAN mode\n  black_set_can_mode(CAN_MODE_NORMAL);\n\n  // flip CAN0 and CAN2 if we are flipped\n  if (car_harness_status == HARNESS_STATUS_FLIPPED) {\n    can_flip_buses(0, 2);\n  }\n}\n\nconst harness_configuration black_harness_config = {\n  .has_harness = true,\n  .GPIO_SBU1 = GPIOC,\n  .GPIO_SBU2 = GPIOC,\n  .GPIO_relay_SBU1 = GPIOC,\n  .GPIO_relay_SBU2 = GPIOC,\n  .pin_SBU1 = 0,\n  .pin_SBU2 = 3,\n  .pin_relay_SBU1 = 10,\n  .pin_relay_SBU2 = 11,\n  .adc_channel_SBU1 = 10,\n  .adc_channel_SBU2 = 13\n};\n\nconst board board_black = {\n  .board_type = \"Black\",\n  .harness_config = &black_harness_config,\n  .has_gps = true,\n  .has_hw_gmlan = false,\n  .has_obd = true,\n  .has_lin = false,\n  .has_rtc = false,\n  .init = black_init,\n  .enable_can_transceiver = black_enable_can_transceiver,\n  .enable_can_transceivers = black_enable_can_transceivers,\n  .set_led = black_set_led,\n  .set_usb_power_mode = black_set_usb_power_mode,\n  .set_gps_mode = black_set_gps_mode,\n  .set_can_mode = black_set_can_mode,\n  .usb_power_mode_tick = unused_usb_power_mode_tick,\n  .check_ignition = black_check_ignition,\n  .read_current = unused_read_current,\n  .set_fan_power = unused_set_fan_power,\n  .set_ir_power = unused_set_ir_power,\n  .set_phone_power = unused_set_phone_power,\n  .set_clock_source_mode = unused_set_clock_source_mode,\n  .set_siren = unused_set_siren\n};\n"
  },
  {
    "path": "panda/board/boards/board_declarations.h",
    "content": "// ******************** Prototypes ********************\ntypedef void (*board_init)(void);\ntypedef void (*board_enable_can_transceiver)(uint8_t transceiver, bool enabled);\ntypedef void (*board_enable_can_transceivers)(bool enabled);\ntypedef void (*board_set_led)(uint8_t color, bool enabled);\ntypedef void (*board_set_usb_power_mode)(uint8_t mode);\ntypedef void (*board_set_gps_mode)(uint8_t mode);\ntypedef void (*board_set_can_mode)(uint8_t mode);\ntypedef void (*board_usb_power_mode_tick)(uint32_t uptime);\ntypedef bool (*board_check_ignition)(void);\ntypedef uint32_t (*board_read_current)(void);\ntypedef void (*board_set_ir_power)(uint8_t percentage);\ntypedef void (*board_set_fan_power)(uint8_t percentage);\ntypedef void (*board_set_phone_power)(bool enabled);\ntypedef void (*board_set_clock_source_mode)(uint8_t mode);\ntypedef void (*board_set_siren)(bool enabled);\n\nstruct board {\n  const char *board_type;\n  const harness_configuration *harness_config;\n  const bool has_gps;\n  const bool has_hw_gmlan;\n  const bool has_obd;\n  const bool has_lin;\n  const bool has_rtc;\n  board_init init;\n  board_enable_can_transceiver enable_can_transceiver;\n  board_enable_can_transceivers enable_can_transceivers;\n  board_set_led set_led;\n  board_set_usb_power_mode set_usb_power_mode;\n  board_set_gps_mode set_gps_mode;\n  board_set_can_mode set_can_mode;\n  board_usb_power_mode_tick usb_power_mode_tick;\n  board_check_ignition check_ignition;\n  board_read_current read_current;\n  board_set_ir_power set_ir_power;\n  board_set_fan_power set_fan_power;\n  board_set_phone_power set_phone_power;\n  board_set_clock_source_mode set_clock_source_mode;\n  board_set_siren set_siren;\n};\n\n// ******************* Definitions ********************\n// These should match the enums in cereal/log.capnp and __init__.py\n#define HW_TYPE_UNKNOWN 0U\n#define HW_TYPE_WHITE_PANDA 1U\n#define HW_TYPE_GREY_PANDA 2U\n#define HW_TYPE_BLACK_PANDA 3U\n#define HW_TYPE_PEDAL 4U\n#define HW_TYPE_UNO 5U\n#define HW_TYPE_DOS 6U\n#define HW_TYPE_RED_PANDA 7U\n\n// LED colors\n#define LED_RED 0U\n#define LED_GREEN 1U\n#define LED_BLUE 2U\n\n// USB power modes (from cereal.log.health)\n#define USB_POWER_NONE 0U\n#define USB_POWER_CLIENT 1U\n#define USB_POWER_CDP 2U\n#define USB_POWER_DCP 3U\n\n// GPS modes\n#define GPS_DISABLED 0U\n#define GPS_ENABLED 1U\n#define GPS_BOOTMODE 2U\n\n// CAN modes\n#define CAN_MODE_NORMAL 0U\n#define CAN_MODE_GMLAN_CAN2 1U\n#define CAN_MODE_GMLAN_CAN3 2U\n#define CAN_MODE_OBD_CAN2 3U\n\n// ********************* Globals **********************\nuint8_t usb_power_mode = USB_POWER_NONE;\n"
  },
  {
    "path": "panda/board/boards/dos.h",
    "content": "// ///////////// //\n// Dos + Harness //\n// ///////////// //\n\nvoid dos_enable_can_transceiver(uint8_t transceiver, bool enabled) {\n  switch (transceiver){\n    case 1U:\n      set_gpio_output(GPIOC, 1, !enabled);\n      break;\n    case 2U:\n      set_gpio_output(GPIOC, 13, !enabled);\n      break;\n    case 3U:\n      set_gpio_output(GPIOA, 0, !enabled);\n      break;\n    case 4U:\n      set_gpio_output(GPIOB, 10, !enabled);\n      break;\n    default:\n      puts(\"Invalid CAN transceiver (\"); puth(transceiver); puts(\"): enabling failed\\n\");\n      break;\n  }\n}\n\nvoid dos_enable_can_transceivers(bool enabled) {\n  for(uint8_t i=1U; i<=4U; i++){\n    // Leave main CAN always on for CAN-based ignition detection\n    if((car_harness_status == HARNESS_STATUS_FLIPPED) ? (i == 3U) : (i == 1U)){\n      dos_enable_can_transceiver(i, true);\n    } else {\n      dos_enable_can_transceiver(i, enabled);\n    }\n  }\n}\n\nvoid dos_set_led(uint8_t color, bool enabled) {\n  switch (color){\n    case LED_RED:\n      set_gpio_output(GPIOC, 9, !enabled);\n      break;\n     case LED_GREEN:\n      set_gpio_output(GPIOC, 7, !enabled);\n      break;\n    case LED_BLUE:\n      set_gpio_output(GPIOC, 6, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid dos_set_bootkick(bool enabled){\n  set_gpio_output(GPIOC, 4, !enabled);\n}\n\nvoid dos_set_usb_power_mode(uint8_t mode) {\n  bool valid = false;\n  switch (mode) {\n    case USB_POWER_CLIENT:\n      dos_set_bootkick(false);\n      valid = true;\n      break;\n    case USB_POWER_CDP:\n      dos_set_bootkick(true);\n      valid = true;\n      break;\n    default:\n      puts(\"Invalid USB power mode\\n\");\n      break;\n  }\n  if (valid) {\n    usb_power_mode = mode;\n  }\n}\n\nvoid dos_set_can_mode(uint8_t mode){\n  switch (mode) {\n    case CAN_MODE_NORMAL:\n    case CAN_MODE_OBD_CAN2:\n      if ((bool)(mode == CAN_MODE_NORMAL) != (bool)(car_harness_status == HARNESS_STATUS_FLIPPED)) {\n        // B12,B13: disable OBD mode\n        set_gpio_mode(GPIOB, 12, MODE_INPUT);\n        set_gpio_mode(GPIOB, 13, MODE_INPUT);\n\n        // B5,B6: normal CAN2 mode\n        set_gpio_alternate(GPIOB, 5, GPIO_AF9_CAN2);\n        set_gpio_alternate(GPIOB, 6, GPIO_AF9_CAN2);\n      } else {\n        // B5,B6: disable normal CAN2 mode\n        set_gpio_mode(GPIOB, 5, MODE_INPUT);\n        set_gpio_mode(GPIOB, 6, MODE_INPUT);\n\n        // B12,B13: OBD mode\n        set_gpio_alternate(GPIOB, 12, GPIO_AF9_CAN2);\n        set_gpio_alternate(GPIOB, 13, GPIO_AF9_CAN2);\n      }\n      break;\n    default:\n      puts(\"Tried to set unsupported CAN mode: \"); puth(mode); puts(\"\\n\");\n      break;\n  }\n}\n\nbool dos_check_ignition(void){\n  // ignition is checked through harness\n  return harness_check_ignition();\n}\n\nvoid dos_set_usb_switch(bool phone){\n  set_gpio_output(GPIOB, 3, phone);\n}\n\nvoid dos_set_ir_power(uint8_t percentage){\n  pwm_set(TIM4, 2, percentage);\n}\n\nvoid dos_set_fan_power(uint8_t percentage){\n  // Enable fan power only if percentage is non-zero.\n  set_gpio_output(GPIOA, 1, (percentage != 0U));\n  fan_set_power(percentage);\n}\n\nvoid dos_set_clock_source_mode(uint8_t mode){\n  clock_source_init(mode);\n}\n\nvoid dos_set_siren(bool enabled){\n  set_gpio_output(GPIOC, 12, enabled);\n}\n\nvoid dos_init(void) {\n  common_init_gpio();\n\n  // A8,A15: normal CAN3 mode\n  set_gpio_alternate(GPIOA, 8, GPIO_AF11_CAN3);\n  set_gpio_alternate(GPIOA, 15, GPIO_AF11_CAN3);\n\n  // C0: OBD_SBU1 (orientation detection)\n  // C3: OBD_SBU2 (orientation detection)\n  set_gpio_mode(GPIOC, 0, MODE_ANALOG);\n  set_gpio_mode(GPIOC, 3, MODE_ANALOG);\n\n  // C10: OBD_SBU1_RELAY (harness relay driving output)\n  // C11: OBD_SBU2_RELAY (harness relay driving output)\n  set_gpio_mode(GPIOC, 10, MODE_OUTPUT);\n  set_gpio_mode(GPIOC, 11, MODE_OUTPUT);\n  set_gpio_output_type(GPIOC, 10, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_output_type(GPIOC, 11, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_output(GPIOC, 10, 1);\n  set_gpio_output(GPIOC, 11, 1);\n\n  // C8: FAN PWM aka TIM3_CH3\n  set_gpio_alternate(GPIOC, 8, GPIO_AF2_TIM3);\n\n  // Initialize IR PWM and set to 0%\n  set_gpio_alternate(GPIOB, 7, GPIO_AF2_TIM4);\n  pwm_init(TIM4, 2);\n  dos_set_ir_power(0U);\n\n  // Initialize fan and set to 0%\n  fan_init();\n  dos_set_fan_power(0U);\n\n  // Initialize harness\n  harness_init();\n\n  // Initialize RTC\n  rtc_init();\n\n  // Enable CAN transceivers\n  dos_enable_can_transceivers(true);\n\n  // Disable LEDs\n  dos_set_led(LED_RED, false);\n  dos_set_led(LED_GREEN, false);\n  dos_set_led(LED_BLUE, false);\n\n  // Set normal CAN mode\n  dos_set_can_mode(CAN_MODE_NORMAL);\n\n  // flip CAN0 and CAN2 if we are flipped\n  if (car_harness_status == HARNESS_STATUS_FLIPPED) {\n    can_flip_buses(0, 2);\n  }\n\n  // Init clock source as internal free running\n  dos_set_clock_source_mode(CLOCK_SOURCE_MODE_FREE_RUNNING);\n}\n\nconst harness_configuration dos_harness_config = {\n  .has_harness = true,\n  .GPIO_SBU1 = GPIOC,\n  .GPIO_SBU2 = GPIOC,\n  .GPIO_relay_SBU1 = GPIOC,\n  .GPIO_relay_SBU2 = GPIOC,\n  .pin_SBU1 = 0,\n  .pin_SBU2 = 3,\n  .pin_relay_SBU1 = 10,\n  .pin_relay_SBU2 = 11,\n  .adc_channel_SBU1 = 10,\n  .adc_channel_SBU2 = 13\n};\n\nconst board board_dos = {\n  .board_type = \"Dos\",\n  .harness_config = &dos_harness_config,\n  .has_gps = false,\n  .has_hw_gmlan = false,\n  .has_obd = true,\n  .has_lin = false,\n  .has_rtc = true,\n  .init = dos_init,\n  .enable_can_transceiver = dos_enable_can_transceiver,\n  .enable_can_transceivers = dos_enable_can_transceivers,\n  .set_led = dos_set_led,\n  .set_usb_power_mode = dos_set_usb_power_mode,\n  .set_gps_mode = unused_set_gps_mode,\n  .set_can_mode = dos_set_can_mode,\n  .usb_power_mode_tick = unused_usb_power_mode_tick,\n  .check_ignition = dos_check_ignition,\n  .read_current = unused_read_current,\n  .set_fan_power = dos_set_fan_power,\n  .set_ir_power = dos_set_ir_power,\n  .set_phone_power = unused_set_phone_power,\n  .set_clock_source_mode = dos_set_clock_source_mode,\n  .set_siren = dos_set_siren\n};\n"
  },
  {
    "path": "panda/board/boards/grey.h",
    "content": "// ////////// //\n// Grey Panda //\n// ////////// //\n\n// Most hardware functionality is similar to white panda\n\nvoid grey_init(void) {\n  white_grey_common_init();\n\n  // Set default state of GPS\n  current_board->set_gps_mode(GPS_ENABLED);\n}\n\nvoid grey_set_gps_mode(uint8_t mode) {\n  switch (mode) {\n    case GPS_DISABLED:\n      // GPS OFF\n      set_gpio_output(GPIOC, 14, 0);\n      set_gpio_output(GPIOC, 5, 0);\n      break;\n    case GPS_ENABLED:\n      // GPS ON\n      set_gpio_output(GPIOC, 14, 1);\n      set_gpio_output(GPIOC, 5, 1);\n      break;\n    case GPS_BOOTMODE:\n      set_gpio_output(GPIOC, 14, 1);\n      set_gpio_output(GPIOC, 5, 0);\n      break;\n    default:\n      puts(\"Invalid ESP/GPS mode\\n\");\n      break;\n  }\n}\n\nconst board board_grey = {\n  .board_type = \"Grey\",\n  .harness_config = &white_harness_config,\n  .has_gps = true,\n  .has_hw_gmlan = true,\n  .has_obd = false,\n  .has_lin = true,\n  .has_rtc = false,\n  .init = grey_init,\n  .enable_can_transceiver = white_enable_can_transceiver,\n  .enable_can_transceivers = white_enable_can_transceivers,\n  .set_led = white_set_led,\n  .set_usb_power_mode = white_set_usb_power_mode,\n  .set_gps_mode = grey_set_gps_mode,\n  .set_can_mode = white_set_can_mode,\n  .usb_power_mode_tick = unused_usb_power_mode_tick,\n  .check_ignition = white_check_ignition,\n  .read_current = white_read_current,\n  .set_fan_power = unused_set_fan_power,\n  .set_ir_power = unused_set_ir_power,\n  .set_phone_power = unused_set_phone_power,\n  .set_clock_source_mode = unused_set_clock_source_mode,\n  .set_siren = unused_set_siren\n};\n"
  },
  {
    "path": "panda/board/boards/pedal.h",
    "content": "// ///// //\n// Pedal //\n// ///// //\n\nvoid pedal_enable_can_transceiver(uint8_t transceiver, bool enabled) {\n  switch (transceiver){\n    case 1:\n      set_gpio_output(GPIOB, 3, !enabled);\n      break;\n    default:\n      puts(\"Invalid CAN transceiver (\"); puth(transceiver); puts(\"): enabling failed\\n\");\n      break;\n  }\n}\n\nvoid pedal_enable_can_transceivers(bool enabled) {\n  pedal_enable_can_transceiver(1U, enabled);\n}\n\nvoid pedal_set_led(uint8_t color, bool enabled) {\n  switch (color){\n    case LED_RED:\n      set_gpio_output(GPIOB, 10, !enabled);\n      break;\n     case LED_GREEN:\n      set_gpio_output(GPIOB, 11, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid pedal_set_usb_power_mode(uint8_t mode){\n  usb_power_mode = mode;\n  puts(\"Trying to set USB power mode on pedal. This is not supported.\\n\");\n}\n\nvoid pedal_set_gps_mode(uint8_t mode) {\n  UNUSED(mode);\n  puts(\"Trying to set ESP/GPS mode on pedal. This is not supported.\\n\");\n}\n\nvoid pedal_set_can_mode(uint8_t mode){\n  switch (mode) {\n    case CAN_MODE_NORMAL:\n      break;\n    default:\n      puts(\"Tried to set unsupported CAN mode: \"); puth(mode); puts(\"\\n\");\n      break;\n  }\n}\n\nbool pedal_check_ignition(void){\n  // not supported on pedal\n  return false;\n}\n\nvoid pedal_init(void) {\n  common_init_gpio();\n\n  // C0, C1: Throttle inputs\n  set_gpio_mode(GPIOC, 0, MODE_ANALOG);\n  set_gpio_mode(GPIOC, 1, MODE_ANALOG);\n  // DAC outputs on A4 and A5\n  //   apparently they don't need GPIO setup\n\n  // Enable transceiver\n  pedal_enable_can_transceivers(true);\n\n  // Disable LEDs\n  pedal_set_led(LED_RED, false);\n  pedal_set_led(LED_GREEN, false);\n}\n\nconst harness_configuration pedal_harness_config = {\n  .has_harness = false\n};\n\nconst board board_pedal = {\n  .board_type = \"Pedal\",\n  .harness_config = &pedal_harness_config,\n  .has_gps = false,\n  .has_hw_gmlan = false,\n  .has_obd = false,\n  .has_lin = false,\n  .has_rtc = false,\n  .init = pedal_init,\n  .enable_can_transceiver = pedal_enable_can_transceiver,\n  .enable_can_transceivers = pedal_enable_can_transceivers,\n  .set_led = pedal_set_led,\n  .set_usb_power_mode = pedal_set_usb_power_mode,\n  .set_gps_mode = pedal_set_gps_mode,\n  .set_can_mode = pedal_set_can_mode,\n  .usb_power_mode_tick = unused_usb_power_mode_tick,\n  .check_ignition = pedal_check_ignition,\n  .read_current = unused_read_current,\n  .set_fan_power = unused_set_fan_power,\n  .set_ir_power = unused_set_ir_power,\n  .set_phone_power = unused_set_phone_power,\n  .set_clock_source_mode = unused_set_clock_source_mode,\n  .set_siren = unused_set_siren\n};\n"
  },
  {
    "path": "panda/board/boards/red.h",
    "content": "// ///////////////////// //\n// Red Panda + Harness //\n// ///////////////////// //\n\nvoid red_enable_can_transceiver(uint8_t transceiver, bool enabled) {\n  switch (transceiver) {\n    case 1U:\n      set_gpio_output(GPIOG, 11, !enabled);\n      break;\n    case 2U:\n      set_gpio_output(GPIOB, 3, !enabled);\n      break;\n    case 3U:\n      set_gpio_output(GPIOD, 7, !enabled);\n      break;\n    case 4U:\n      set_gpio_output(GPIOB, 4, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid red_enable_can_transceivers(bool enabled) {\n  uint8_t main_bus = (car_harness_status == HARNESS_STATUS_FLIPPED) ? 3U : 1U;\n  for (uint8_t i=1U; i<=4U; i++) {\n    // Leave main CAN always on for CAN-based ignition detection\n    if (i == main_bus) {\n      red_enable_can_transceiver(i, true);\n    } else {\n      red_enable_can_transceiver(i, enabled);\n    }\n  }\n}\n\nvoid red_set_led(uint8_t color, bool enabled) {\n  switch (color) {\n    case LED_RED:\n      set_gpio_output(GPIOE, 4, !enabled);\n      break;\n     case LED_GREEN:\n      set_gpio_output(GPIOE, 3, !enabled);\n      break;\n    case LED_BLUE:\n      set_gpio_output(GPIOE, 2, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid red_set_usb_load_switch(bool enabled) {\n  set_gpio_output(GPIOB, 14, !enabled);\n}\n\nvoid red_set_usb_power_mode(uint8_t mode) {\n  bool valid = false;\n  switch (mode) {\n    case USB_POWER_CLIENT:\n      red_set_usb_load_switch(false);\n      valid = true;\n      break;\n    case USB_POWER_CDP:\n      red_set_usb_load_switch(true);\n      valid = true;\n      break;\n    default:\n      break;\n  }\n  if (valid) {\n    usb_power_mode = mode;\n  }\n}\n\nvoid red_set_can_mode(uint8_t mode) {\n  switch (mode) {\n    case CAN_MODE_NORMAL:\n    case CAN_MODE_OBD_CAN2:\n      if ((bool)(mode == CAN_MODE_NORMAL) != (bool)(car_harness_status == HARNESS_STATUS_FLIPPED)) {\n        // B12,B13: disable normal mode\n        set_gpio_pullup(GPIOB, 12, PULL_NONE);\n        set_gpio_mode(GPIOB, 12, MODE_ANALOG);\n\n        set_gpio_pullup(GPIOB, 13, PULL_NONE);\n        set_gpio_mode(GPIOB, 13, MODE_ANALOG);\n        \n        // B5,B6: FDCAN2 mode\n        set_gpio_pullup(GPIOB, 5, PULL_NONE);\n        set_gpio_alternate(GPIOB, 5, GPIO_AF9_FDCAN2);\n\n        set_gpio_pullup(GPIOB, 6, PULL_NONE);\n        set_gpio_alternate(GPIOB, 6, GPIO_AF9_FDCAN2);\n      } else {\n        // B5,B6: disable normal mode\n        set_gpio_pullup(GPIOB, 5, PULL_NONE);\n        set_gpio_mode(GPIOB, 5, MODE_ANALOG);\n\n        set_gpio_pullup(GPIOB, 6, PULL_NONE);\n        set_gpio_mode(GPIOB, 6, MODE_ANALOG);\n        // B12,B13: FDCAN2 mode\n        set_gpio_pullup(GPIOB, 12, PULL_NONE);\n        set_gpio_alternate(GPIOB, 12, GPIO_AF9_FDCAN2);\n\n        set_gpio_pullup(GPIOB, 13, PULL_NONE);\n        set_gpio_alternate(GPIOB, 13, GPIO_AF9_FDCAN2);\n      }\n      break;\n    default:\n      break;\n  }\n}\n\nbool red_check_ignition(void) {\n  // ignition is checked through harness\n  return harness_check_ignition();\n}\n\nvoid red_init(void) {\n  common_init_gpio();\n\n  //C4,A1: OBD_SBU1, OBD_SBU2\n  set_gpio_pullup(GPIOC, 4, PULL_NONE);\n  set_gpio_mode(GPIOC, 4, MODE_ANALOG);\n\n  set_gpio_pullup(GPIOA, 1, PULL_NONE);\n  set_gpio_mode(GPIOA, 1, MODE_ANALOG);\n\n  //C10,C11 : OBD_SBU1_RELAY, OBD_SBU2_RELAY\n  set_gpio_output_type(GPIOC, 10, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_pullup(GPIOC, 10, PULL_NONE);\n  set_gpio_mode(GPIOC, 10, MODE_OUTPUT);\n  set_gpio_output(GPIOC, 10, 1);\n\n  set_gpio_output_type(GPIOC, 11, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_pullup(GPIOC, 11, PULL_NONE);\n  set_gpio_mode(GPIOC, 11, MODE_OUTPUT);\n  set_gpio_output(GPIOC, 11, 1);\n\n  // Turn on USB load switch.\n  red_set_usb_load_switch(true);\n\n  // Set right power mode\n  red_set_usb_power_mode(USB_POWER_CDP);\n\n  // Initialize harness\n  harness_init();\n\n  // Enable CAN transceivers\n  red_enable_can_transceivers(true);\n\n  // Disable LEDs\n  red_set_led(LED_RED, false);\n  red_set_led(LED_GREEN, false);\n  red_set_led(LED_BLUE, false);\n\n  // Set normal CAN mode\n  red_set_can_mode(CAN_MODE_NORMAL);\n\n  // flip CAN0 and CAN2 if we are flipped\n  if (car_harness_status == HARNESS_STATUS_FLIPPED) {\n    can_flip_buses(0, 2);\n  }\n}\n\nconst harness_configuration red_harness_config = {\n  .has_harness = true,\n  .GPIO_SBU1 = GPIOC,\n  .GPIO_SBU2 = GPIOA,\n  .GPIO_relay_SBU1 = GPIOC,\n  .GPIO_relay_SBU2 = GPIOC,\n  .pin_SBU1 = 4,\n  .pin_SBU2 = 1,\n  .pin_relay_SBU1 = 10,\n  .pin_relay_SBU2 = 11,\n  .adc_channel_SBU1 = 4, //ADC12_INP4\n  .adc_channel_SBU2 = 17 //ADC1_INP17\n};\n\nconst board board_red = {\n  .board_type = \"Red\",\n  .harness_config = &red_harness_config,\n  .has_gps = false,\n  .has_hw_gmlan = false,\n  .has_obd = true,\n  .has_lin = false,\n  .has_rtc = false,\n  .init = red_init,\n  .enable_can_transceiver = red_enable_can_transceiver,\n  .enable_can_transceivers = red_enable_can_transceivers,\n  .set_led = red_set_led,\n  .set_usb_power_mode = red_set_usb_power_mode,\n  .set_gps_mode = unused_set_gps_mode,\n  .set_can_mode = red_set_can_mode,\n  .usb_power_mode_tick = unused_usb_power_mode_tick,\n  .check_ignition = red_check_ignition,\n  .read_current = unused_read_current,\n  .set_fan_power = unused_set_fan_power,\n  .set_ir_power = unused_set_ir_power,\n  .set_phone_power = unused_set_phone_power,\n  .set_clock_source_mode = unused_set_clock_source_mode,\n  .set_siren = unused_set_siren\n};\n"
  },
  {
    "path": "panda/board/boards/uno.h",
    "content": "// ///////////// //\n// Uno + Harness //\n// ///////////// //\n#define BOOTKICK_TIME 3U\nuint8_t bootkick_timer = 0U;\n\nvoid uno_enable_can_transceiver(uint8_t transceiver, bool enabled) {\n  switch (transceiver){\n    case 1U:\n      set_gpio_output(GPIOC, 1, !enabled);\n      break;\n    case 2U:\n      set_gpio_output(GPIOC, 13, !enabled);\n      break;\n    case 3U:\n      set_gpio_output(GPIOA, 0, !enabled);\n      break;\n    case 4U:\n      set_gpio_output(GPIOB, 10, !enabled);\n      break;\n    default:\n      puts(\"Invalid CAN transceiver (\"); puth(transceiver); puts(\"): enabling failed\\n\");\n      break;\n  }\n}\n\nvoid uno_enable_can_transceivers(bool enabled) {\n  for(uint8_t i=1U; i<=4U; i++){\n    // Leave main CAN always on for CAN-based ignition detection\n    if((car_harness_status == HARNESS_STATUS_FLIPPED) ? (i == 3U) : (i == 1U)){\n      uno_enable_can_transceiver(i, true);\n    } else {\n      uno_enable_can_transceiver(i, enabled);\n    }\n  }\n}\n\nvoid uno_set_led(uint8_t color, bool enabled) {\n  switch (color){\n    case LED_RED:\n      set_gpio_output(GPIOC, 9, !enabled);\n      break;\n     case LED_GREEN:\n      set_gpio_output(GPIOC, 7, !enabled);\n      break;\n    case LED_BLUE:\n      set_gpio_output(GPIOC, 6, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid uno_set_gps_load_switch(bool enabled) {\n  set_gpio_output(GPIOC, 12, enabled);\n}\n\nvoid uno_set_bootkick(bool enabled){\n  set_gpio_output(GPIOB, 14, !enabled);\n}\n\nvoid uno_bootkick(void) {\n  bootkick_timer = BOOTKICK_TIME;\n  uno_set_bootkick(true);\n}\n\nvoid uno_set_phone_power(bool enabled){\n  set_gpio_output(GPIOB, 4, enabled);\n}\n\nvoid uno_set_usb_power_mode(uint8_t mode) {\n  bool valid = false;\n  switch (mode) {\n    case USB_POWER_CLIENT:\n      uno_set_phone_power(false);\n      valid = true;\n      break;\n    case USB_POWER_CDP:\n      uno_set_phone_power(true);\n      uno_bootkick();\n      valid = true;\n      break;\n    default:\n      puts(\"Invalid USB power mode\\n\");\n      break;\n  }\n  if (valid) {\n    usb_power_mode = mode;\n  }\n}\n\nvoid uno_set_gps_mode(uint8_t mode) {\n  switch (mode) {\n    case GPS_DISABLED:\n      // GPS OFF\n      set_gpio_output(GPIOB, 1, 0);\n      set_gpio_output(GPIOC, 5, 0);\n      uno_set_gps_load_switch(false);\n      break;\n    case GPS_ENABLED:\n      // GPS ON\n      set_gpio_output(GPIOB, 1, 1);\n      set_gpio_output(GPIOC, 5, 1);\n      uno_set_gps_load_switch(true);\n      break;\n    case GPS_BOOTMODE:\n      set_gpio_output(GPIOB, 1, 1);\n      set_gpio_output(GPIOC, 5, 0);\n      uno_set_gps_load_switch(true);\n      break;\n    default:\n      puts(\"Invalid ESP/GPS mode\\n\");\n      break;\n  }\n}\n\nvoid uno_set_can_mode(uint8_t mode){\n  switch (mode) {\n    case CAN_MODE_NORMAL:\n    case CAN_MODE_OBD_CAN2:\n      if ((bool)(mode == CAN_MODE_NORMAL) != (bool)(car_harness_status == HARNESS_STATUS_FLIPPED)) {\n        // B12,B13: disable OBD mode\n        set_gpio_mode(GPIOB, 12, MODE_INPUT);\n        set_gpio_mode(GPIOB, 13, MODE_INPUT);\n\n        // B5,B6: normal CAN2 mode\n        set_gpio_alternate(GPIOB, 5, GPIO_AF9_CAN2);\n        set_gpio_alternate(GPIOB, 6, GPIO_AF9_CAN2);\n      } else {\n        // B5,B6: disable normal CAN2 mode\n        set_gpio_mode(GPIOB, 5, MODE_INPUT);\n        set_gpio_mode(GPIOB, 6, MODE_INPUT);\n\n        // B12,B13: OBD mode\n        set_gpio_alternate(GPIOB, 12, GPIO_AF9_CAN2);\n        set_gpio_alternate(GPIOB, 13, GPIO_AF9_CAN2);\n      }\n      break;\n    default:\n      puts(\"Tried to set unsupported CAN mode: \"); puth(mode); puts(\"\\n\");\n      break;\n  }\n}\n\nvoid uno_usb_power_mode_tick(uint32_t uptime){\n  UNUSED(uptime);\n  if(bootkick_timer != 0U){\n    bootkick_timer--;\n  } else {\n    uno_set_bootkick(false);\n  }\n}\n\nbool uno_check_ignition(void){\n  // ignition is checked through harness\n  return harness_check_ignition();\n}\n\nvoid uno_set_usb_switch(bool phone){\n  set_gpio_output(GPIOB, 3, phone);\n}\n\nvoid uno_set_ir_power(uint8_t percentage){\n  pwm_set(TIM4, 2, percentage);\n}\n\nvoid uno_set_fan_power(uint8_t percentage){\n  // Enable fan power only if percentage is non-zero.\n  set_gpio_output(GPIOA, 1, (percentage != 0U));\n  fan_set_power(percentage);\n}\n\nvoid uno_init(void) {\n  common_init_gpio();\n\n  // A8,A15: normal CAN3 mode\n  set_gpio_alternate(GPIOA, 8, GPIO_AF11_CAN3);\n  set_gpio_alternate(GPIOA, 15, GPIO_AF11_CAN3);\n\n  // C0: OBD_SBU1 (orientation detection)\n  // C3: OBD_SBU2 (orientation detection)\n  set_gpio_mode(GPIOC, 0, MODE_ANALOG);\n  set_gpio_mode(GPIOC, 3, MODE_ANALOG);\n\n  // Set default state of GPS\n  current_board->set_gps_mode(GPS_ENABLED);\n\n  // C10: OBD_SBU1_RELAY (harness relay driving output)\n  // C11: OBD_SBU2_RELAY (harness relay driving output)\n  set_gpio_mode(GPIOC, 10, MODE_OUTPUT);\n  set_gpio_mode(GPIOC, 11, MODE_OUTPUT);\n  set_gpio_output_type(GPIOC, 10, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_output_type(GPIOC, 11, OUTPUT_TYPE_OPEN_DRAIN);\n  set_gpio_output(GPIOC, 10, 1);\n  set_gpio_output(GPIOC, 11, 1);\n\n  // C8: FAN PWM aka TIM3_CH3\n  set_gpio_alternate(GPIOC, 8, GPIO_AF2_TIM3);\n\n  // Turn on GPS load switch.\n  uno_set_gps_load_switch(true);\n\n  // Turn on phone regulator\n  uno_set_phone_power(true);\n\n  // Initialize IR PWM and set to 0%\n  set_gpio_alternate(GPIOB, 7, GPIO_AF2_TIM4);\n  pwm_init(TIM4, 2);\n  uno_set_ir_power(0U);\n\n  // Initialize fan and set to 0%\n  fan_init();\n  uno_set_fan_power(0U);\n\n  // Initialize harness\n  harness_init();\n\n  // Initialize RTC\n  rtc_init();\n\n  // Enable CAN transceivers\n  uno_enable_can_transceivers(true);\n\n  // Disable LEDs\n  uno_set_led(LED_RED, false);\n  uno_set_led(LED_GREEN, false);\n  uno_set_led(LED_BLUE, false);\n\n  // Set normal CAN mode\n  uno_set_can_mode(CAN_MODE_NORMAL);\n\n  // flip CAN0 and CAN2 if we are flipped\n  if (car_harness_status == HARNESS_STATUS_FLIPPED) {\n    can_flip_buses(0, 2);\n  }\n\n  // Switch to phone usb mode if harness connection is powered by less than 7V\n  if(adc_get_voltage() < 7000U){\n    uno_set_usb_switch(true);\n  } else {\n    uno_set_usb_switch(false);\n  }\n\n  // Bootkick phone\n  uno_bootkick();\n}\n\nconst harness_configuration uno_harness_config = {\n  .has_harness = true,\n  .GPIO_SBU1 = GPIOC,\n  .GPIO_SBU2 = GPIOC,\n  .GPIO_relay_SBU1 = GPIOC,\n  .GPIO_relay_SBU2 = GPIOC,\n  .pin_SBU1 = 0,\n  .pin_SBU2 = 3,\n  .pin_relay_SBU1 = 10,\n  .pin_relay_SBU2 = 11,\n  .adc_channel_SBU1 = 10,\n  .adc_channel_SBU2 = 13\n};\n\nconst board board_uno = {\n  .board_type = \"Uno\",\n  .harness_config = &uno_harness_config,\n  .has_gps = true,\n  .has_hw_gmlan = false,\n  .has_obd = true,\n  .has_lin = false,\n  .has_rtc = true,\n  .init = uno_init,\n  .enable_can_transceiver = uno_enable_can_transceiver,\n  .enable_can_transceivers = uno_enable_can_transceivers,\n  .set_led = uno_set_led,\n  .set_usb_power_mode = uno_set_usb_power_mode,\n  .set_gps_mode = uno_set_gps_mode,\n  .set_can_mode = uno_set_can_mode,\n  .usb_power_mode_tick = uno_usb_power_mode_tick,\n  .check_ignition = uno_check_ignition,\n  .read_current = unused_read_current,\n  .set_fan_power = uno_set_fan_power,\n  .set_ir_power = uno_set_ir_power,\n  .set_phone_power = uno_set_phone_power,\n  .set_clock_source_mode = unused_set_clock_source_mode,\n  .set_siren = unused_set_siren\n};\n"
  },
  {
    "path": "panda/board/boards/unused_funcs.h",
    "content": "void unused_set_gps_mode(uint8_t mode) {\n  UNUSED(mode);\n}\n\nvoid unused_usb_power_mode_tick(uint32_t uptime) {\n  UNUSED(uptime);\n}\n\nvoid unused_set_ir_power(uint8_t percentage) {\n  UNUSED(percentage);\n}\n\nvoid unused_set_fan_power(uint8_t percentage) {\n  UNUSED(percentage);\n}\n\nvoid unused_set_phone_power(bool enabled) {\n  UNUSED(enabled);\n}\n\nvoid unused_set_clock_source_mode(uint8_t mode) {\n  UNUSED(mode);\n}\n\nvoid unused_set_siren(bool enabled) {\n  UNUSED(enabled);\n}\n\nuint32_t unused_read_current(void) {\n  return 0U;\n}\n"
  },
  {
    "path": "panda/board/boards/white.h",
    "content": "// /////////// //\n// White Panda //\n// /////////// //\n\nvoid white_enable_can_transceiver(uint8_t transceiver, bool enabled) {\n  switch (transceiver){\n    case 1U:\n      set_gpio_output(GPIOC, 1, !enabled);\n      break;\n    case 2U:\n      set_gpio_output(GPIOC, 13, !enabled);\n      break;\n    case 3U:\n      set_gpio_output(GPIOA, 0, !enabled);\n      break;\n    default:\n      puts(\"Invalid CAN transceiver (\"); puth(transceiver); puts(\"): enabling failed\\n\");\n      break;\n  }\n}\n\nvoid white_enable_can_transceivers(bool enabled) {\n  uint8_t t1 = enabled ? 1U : 2U;  // leave transceiver 1 enabled to detect CAN ignition\n  for(uint8_t i=t1; i<=3U; i++) {\n    white_enable_can_transceiver(i, enabled);\n  }\n}\n\nvoid white_set_led(uint8_t color, bool enabled) {\n  switch (color){\n    case LED_RED:\n      set_gpio_output(GPIOC, 9, !enabled);\n      break;\n     case LED_GREEN:\n      set_gpio_output(GPIOC, 7, !enabled);\n      break;\n    case LED_BLUE:\n      set_gpio_output(GPIOC, 6, !enabled);\n      break;\n    default:\n      break;\n  }\n}\n\nvoid white_set_usb_power_mode(uint8_t mode){\n  bool valid_mode = true;\n  switch (mode) {\n    case USB_POWER_CLIENT:\n      // B2,A13: set client mode\n      set_gpio_output(GPIOB, 2, 0);\n      set_gpio_output(GPIOA, 13, 1);\n      break;\n    case USB_POWER_CDP:\n      // B2,A13: set CDP mode\n      set_gpio_output(GPIOB, 2, 1);\n      set_gpio_output(GPIOA, 13, 1);\n      break;\n    case USB_POWER_DCP:\n      // B2,A13: set DCP mode on the charger (breaks USB!)\n      set_gpio_output(GPIOB, 2, 0);\n      set_gpio_output(GPIOA, 13, 0);\n      break;\n    default:\n      valid_mode = false;\n      puts(\"Invalid usb power mode\\n\");\n      break;\n  }\n\n  if (valid_mode) {\n    usb_power_mode = mode;\n  }\n}\n\nvoid white_set_gps_mode(uint8_t mode) {\n  switch (mode) {\n    case GPS_DISABLED:\n      // ESP OFF\n      set_gpio_output(GPIOC, 14, 0);\n      set_gpio_output(GPIOC, 5, 0);\n      break;\n    case GPS_BOOTMODE:\n      set_gpio_output(GPIOC, 14, 1);\n      set_gpio_output(GPIOC, 5, 0);\n      break;\n    default:\n      puts(\"Invalid ESP/GPS mode\\n\");\n      break;\n  }\n}\n\nvoid white_set_can_mode(uint8_t mode){\n  switch (mode) {\n    case CAN_MODE_NORMAL:\n      // B12,B13: disable GMLAN mode\n      set_gpio_mode(GPIOB, 12, MODE_INPUT);\n      set_gpio_mode(GPIOB, 13, MODE_INPUT);\n\n      // B3,B4: disable GMLAN mode\n      set_gpio_mode(GPIOB, 3, MODE_INPUT);\n      set_gpio_mode(GPIOB, 4, MODE_INPUT);\n\n      // B5,B6: normal CAN2 mode\n      set_gpio_alternate(GPIOB, 5, GPIO_AF9_CAN2);\n      set_gpio_alternate(GPIOB, 6, GPIO_AF9_CAN2);\n\n      // A8,A15: normal CAN3 mode\n      set_gpio_alternate(GPIOA, 8, GPIO_AF11_CAN3);\n      set_gpio_alternate(GPIOA, 15, GPIO_AF11_CAN3);\n      break;\n    case CAN_MODE_GMLAN_CAN2:\n      // B5,B6: disable CAN2 mode\n      set_gpio_mode(GPIOB, 5, MODE_INPUT);\n      set_gpio_mode(GPIOB, 6, MODE_INPUT);\n\n      // B3,B4: disable GMLAN mode\n      set_gpio_mode(GPIOB, 3, MODE_INPUT);\n      set_gpio_mode(GPIOB, 4, MODE_INPUT);\n\n      // B12,B13: GMLAN mode\n      set_gpio_alternate(GPIOB, 12, GPIO_AF9_CAN2);\n      set_gpio_alternate(GPIOB, 13, GPIO_AF9_CAN2);\n\n      // A8,A15: normal CAN3 mode\n      set_gpio_alternate(GPIOA, 8, GPIO_AF11_CAN3);\n      set_gpio_alternate(GPIOA, 15, GPIO_AF11_CAN3);\n      break;\n    case CAN_MODE_GMLAN_CAN3:\n      // A8,A15: disable CAN3 mode\n      set_gpio_mode(GPIOA, 8, MODE_INPUT);\n      set_gpio_mode(GPIOA, 15, MODE_INPUT);\n\n      // B12,B13: disable GMLAN mode\n      set_gpio_mode(GPIOB, 12, MODE_INPUT);\n      set_gpio_mode(GPIOB, 13, MODE_INPUT);\n\n      // B3,B4: GMLAN mode\n      set_gpio_alternate(GPIOB, 3, GPIO_AF11_CAN3);\n      set_gpio_alternate(GPIOB, 4, GPIO_AF11_CAN3);\n\n      // B5,B6: normal CAN2 mode\n      set_gpio_alternate(GPIOB, 5, GPIO_AF9_CAN2);\n      set_gpio_alternate(GPIOB, 6, GPIO_AF9_CAN2);\n      break;\n    default:\n      puts(\"Tried to set unsupported CAN mode: \"); puth(mode); puts(\"\\n\");\n      break;\n  }\n}\n\nuint32_t white_read_current(void){\n  return adc_get(ADCCHAN_CURRENT);\n}\n\nbool white_check_ignition(void){\n  // ignition is on PA1\n  return !get_gpio_input(GPIOA, 1);\n}\n\nvoid white_grey_common_init(void) {\n  common_init_gpio();\n\n  // C3: current sense\n  set_gpio_mode(GPIOC, 3, MODE_ANALOG);\n\n  // A1: started_alt\n  set_gpio_pullup(GPIOA, 1, PULL_UP);\n\n  // A2, A3: USART 2 for debugging\n  set_gpio_alternate(GPIOA, 2, GPIO_AF7_USART2);\n  set_gpio_alternate(GPIOA, 3, GPIO_AF7_USART2);\n\n  // A4, A5, A6, A7: SPI\n  set_gpio_alternate(GPIOA, 4, GPIO_AF5_SPI1);\n  set_gpio_alternate(GPIOA, 5, GPIO_AF5_SPI1);\n  set_gpio_alternate(GPIOA, 6, GPIO_AF5_SPI1);\n  set_gpio_alternate(GPIOA, 7, GPIO_AF5_SPI1);\n\n  // B12: GMLAN, ignition sense, pull up\n  set_gpio_pullup(GPIOB, 12, PULL_UP);\n\n  /* GMLAN mode pins:\n      M0(B15)  M1(B14)  mode\n      =======================\n      0        0        sleep\n      1        0        100kbit\n      0        1        high voltage wakeup\n      1        1        33kbit (normal)\n  */\n  set_gpio_output(GPIOB, 14, 1);\n  set_gpio_output(GPIOB, 15, 1);\n\n  // B7: K-line enable\n  set_gpio_output(GPIOB, 7, 1);\n\n  // C12, D2: Setup K-line (UART5)\n  set_gpio_alternate(GPIOC, 12, GPIO_AF8_UART5);\n  set_gpio_alternate(GPIOD, 2, GPIO_AF8_UART5);\n  set_gpio_pullup(GPIOD, 2, PULL_UP);\n\n  // L-line enable\n  set_gpio_output(GPIOA, 14, 1);\n\n  // C10, C11: L-Line setup (USART3)\n  set_gpio_alternate(GPIOC, 10, GPIO_AF7_USART3);\n  set_gpio_alternate(GPIOC, 11, GPIO_AF7_USART3);\n  set_gpio_pullup(GPIOC, 11, PULL_UP);\n\n  // Enable CAN transceivers\n  white_enable_can_transceivers(true);\n\n  // Disable LEDs\n  white_set_led(LED_RED, false);\n  white_set_led(LED_GREEN, false);\n  white_set_led(LED_BLUE, false);\n\n  // Set normal CAN mode\n  white_set_can_mode(CAN_MODE_NORMAL);\n\n  // Init usb power mode\n  uint32_t voltage = adc_get_voltage();\n  // Init in CDP mode only if panda is powered by 12V.\n  // Otherwise a PC would not be able to flash a standalone panda\n  if (voltage > 8000U) {  // 8V threshold\n    white_set_usb_power_mode(USB_POWER_CDP);\n  } else {\n    white_set_usb_power_mode(USB_POWER_CLIENT);\n  }\n}\n\nvoid white_init(void) {\n  white_grey_common_init();\n\n  // Set ESP off by default\n  current_board->set_gps_mode(GPS_DISABLED);\n}\n\nconst harness_configuration white_harness_config = {\n  .has_harness = false\n};\n\nconst board board_white = {\n  .board_type = \"White\",\n  .harness_config = &white_harness_config,\n  .has_gps = false,\n  .has_hw_gmlan = true,\n  .has_obd = false,\n  .has_lin = true,\n  .has_rtc = false,\n  .init = white_init,\n  .enable_can_transceiver = white_enable_can_transceiver,\n  .enable_can_transceivers = white_enable_can_transceivers,\n  .set_led = white_set_led,\n  .set_usb_power_mode = white_set_usb_power_mode,\n  .set_gps_mode = white_set_gps_mode,\n  .set_can_mode = white_set_can_mode,\n  .usb_power_mode_tick = unused_usb_power_mode_tick,\n  .check_ignition = white_check_ignition,\n  .read_current = white_read_current,\n  .set_fan_power = unused_set_fan_power,\n  .set_ir_power = unused_set_ir_power,\n  .set_phone_power = unused_set_phone_power,\n  .set_clock_source_mode = unused_set_clock_source_mode,\n  .set_siren = unused_set_siren\n};\n"
  },
  {
    "path": "panda/board/bootstub.c",
    "content": "#define BOOTSTUB\n\n#define VERS_TAG 0x53524556\n#define MIN_VERSION 2\n\n// ********************* Includes *********************\n#include \"config.h\"\n\n#include \"drivers/pwm.h\"\n#include \"drivers/usb.h\"\n\n#include \"early_init.h\"\n#include \"provision.h\"\n\n#include \"crypto/rsa.h\"\n#include \"crypto/sha.h\"\n\n#include \"obj/cert.h\"\n#include \"obj/gitversion.h\"\n#include \"flasher.h\"\n\nvoid __initialize_hardware_early(void) {\n  early_initialization();\n}\n\nvoid fail(void) {\n  soft_flasher_start();\n}\n\n// know where to sig check\nextern void *_app_start[];\n\n// FIXME: sometimes your panda will fail flashing and will quickly blink a single Green LED\n// BOUNTY: $200 coupon on shop.comma.ai or $100 check.\n\nint main(void) {\n  // Init interrupt table\n  init_interrupts(true);\n\n  disable_interrupts();\n  clock_init();\n  detect_external_debug_serial();\n  detect_board_type();\n\n  if (enter_bootloader_mode == ENTER_SOFTLOADER_MAGIC) {\n    enter_bootloader_mode = 0;\n    soft_flasher_start();\n  }\n\n  // validate length\n  int len = (int)_app_start[0];\n  if ((len < 8) || (len > (0x1000000 - 0x4000 - 4 - RSANUMBYTES))) goto fail;\n\n  // compute SHA hash\n  uint8_t digest[SHA_DIGEST_SIZE];\n  SHA_hash(&_app_start[1], len-4, digest);\n\n  // verify version, last bytes in the signed area\n  uint32_t vers[2] = {0};\n  memcpy(&vers, ((void*)&_app_start[0]) + len - sizeof(vers), sizeof(vers));\n  if (vers[0] != VERS_TAG || vers[1] < MIN_VERSION) {\n    goto fail;\n  }\n\n  // verify RSA signature\n  if (RSA_verify(&release_rsa_key, ((void*)&_app_start[0]) + len, RSANUMBYTES, digest, SHA_DIGEST_SIZE)) {\n    goto good;\n  }\n\n  // allow debug if built from source\n#ifdef ALLOW_DEBUG\n  if (RSA_verify(&debug_rsa_key, ((void*)&_app_start[0]) + len, RSANUMBYTES, digest, SHA_DIGEST_SIZE)) {\n    goto good;\n  }\n#endif\n\n// here is a failure\nfail:\n  fail();\n  return 0;\ngood:\n  // jump to flash\n  ((void(*)(void)) _app_start[1])();\n  return 0;\n}\n"
  },
  {
    "path": "panda/board/bootstub_declarations.h",
    "content": "// ******************** Prototypes ********************\nvoid puts(const char *a){ UNUSED(a); }\nvoid puth(uint8_t i){ UNUSED(i); }\nvoid puth2(uint8_t i){ UNUSED(i); }\ntypedef struct board board;\ntypedef struct harness_configuration harness_configuration;\n// No CAN support on bootloader\nvoid can_flip_buses(uint8_t bus1, uint8_t bus2){UNUSED(bus1); UNUSED(bus2);}\nvoid pwm_init(TIM_TypeDef *TIM, uint8_t channel);\nvoid pwm_set(TIM_TypeDef *TIM, uint8_t channel, uint8_t percentage);\n\n// ********************* Globals **********************\nuint8_t hw_type = 0;\nconst board *current_board;\n"
  },
  {
    "path": "panda/board/build_all.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\nscons -u\nPANDA_H7=1 scons -u\nPEDAL=1 scons -u\nPEDAL=1 PEDAL_USB=1 scons -u\n"
  },
  {
    "path": "panda/board/config.h",
    "content": "#ifndef PANDA_CONFIG_H\n#define PANDA_CONFIG_H\n\n//#define DEBUG\n//#define DEBUG_UART\n//#define DEBUG_USB\n//#define DEBUG_SPI\n//#define DEBUG_FAULTS\n\n#define USB_VID 0xbbaaU\n\n#ifdef BOOTSTUB\n  #define USB_PID 0xddeeU\n#else\n  #define USB_PID 0xddccU\n#endif\n\n#define NULL ((void*)0)\n#define COMPILE_TIME_ASSERT(pred) ((void)sizeof(char[1 - (2 * ((int)(!(pred))))]))\n\n#define MIN(a,b) \\\n ({ __typeof__ (a) _a = (a); \\\n     __typeof__ (b) _b = (b); \\\n   (_a < _b) ? _a : _b; })\n\n#define MAX(a,b) \\\n ({ __typeof__ (a) _a = (a); \\\n     __typeof__ (b) _b = (b); \\\n   (_a > _b) ? _a : _b; })\n\n#define ABS(a) \\\n ({ __typeof__ (a) _a = (a); \\\n   (_a > 0) ? _a : (-_a); })\n\n#define MAX_RESP_LEN 0x40U\n\n#define GET_BUS(msg) (((msg)->RDTR >> 4) & 0xFF)\n#define GET_LEN(msg) ((msg)->RDTR & 0xF)\n#define GET_ADDR(msg) ((((msg)->RIR & 4) != 0) ? ((msg)->RIR >> 3) : ((msg)->RIR >> 21))\n#define GET_BYTE(msg, b) (((int)(b) > 3) ? (((msg)->RDHR >> (8U * ((unsigned int)(b) % 4U))) & 0xFFU) : (((msg)->RDLR >> (8U * (unsigned int)(b))) & 0xFFU))\n#define GET_BYTES_04(msg) ((msg)->RDLR)\n#define GET_BYTES_48(msg) ((msg)->RDHR)\n#define GET_FLAG(value, mask) (((__typeof__(mask))(value) & (mask)) == (mask))\n\n#define CAN_INIT_TIMEOUT_MS 500U\n\n#include <stdbool.h>\n#ifdef STM32H7\n  #include \"stm32h7/stm32h7_config.h\"\n#else\n  #include \"stm32fx/stm32fx_config.h\"\n#endif\n\n#endif\n"
  },
  {
    "path": "panda/board/crc.h",
    "content": "uint8_t crc_checksum(uint8_t *dat, int len, const uint8_t poly) {\n  uint8_t crc = 0xFFU;\n  int i;\n  int j;\n  for (i = len - 1; i >= 0; i--) {\n    crc ^= dat[i];\n    for (j = 0; j < 8; j++) {\n      if ((crc & 0x80U) != 0U) {\n        crc = (uint8_t)((crc << 1) ^ poly);\n      }\n      else {\n        crc <<= 1;\n      }\n    }\n  }\n  return crc;\n}\n"
  },
  {
    "path": "panda/board/critical.h",
    "content": "// ********************* Critical section helpers *********************\nvolatile bool interrupts_enabled = false;\n\nvoid enable_interrupts(void) {\n  interrupts_enabled = true;\n  __enable_irq();\n}\n\nvoid disable_interrupts(void) {\n  interrupts_enabled = false;\n  __disable_irq();\n}\n\nuint8_t global_critical_depth = 0U;\n#define ENTER_CRITICAL()                                      \\\n  __disable_irq();                                            \\\n  global_critical_depth += 1U;\n\n#define EXIT_CRITICAL()                                       \\\n  global_critical_depth -= 1U;                                \\\n  if ((global_critical_depth == 0U) && interrupts_enabled) {  \\\n    __enable_irq();                                           \\\n  }\n"
  },
  {
    "path": "panda/board/drivers/bxcan.h",
    "content": "// IRQs: CAN1_TX, CAN1_RX0, CAN1_SCE\n//       CAN2_TX, CAN2_RX0, CAN2_SCE\n//       CAN3_TX, CAN3_RX0, CAN3_SCE\n\nCAN_TypeDef *cans[] = {CAN1, CAN2, CAN3};\n\nbool can_set_speed(uint8_t can_number) {\n  bool ret = true;\n  CAN_TypeDef *CAN = CANIF_FROM_CAN_NUM(can_number);\n  uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);\n\n  ret &= llcan_set_speed(CAN, can_speed[bus_number], can_loopback, (unsigned int)(can_silent) & (1U << can_number));\n  return ret;\n}\n\n// TODO: Cleanup with new abstraction\nvoid can_set_gmlan(uint8_t bus) {\n  if(current_board->has_hw_gmlan){\n    // first, disable GMLAN on prev bus\n    uint8_t prev_bus = can_num_lookup[3];\n    if (bus != prev_bus) {\n      switch (prev_bus) {\n        case 1:\n        case 2:\n          puts(\"Disable GMLAN on CAN\");\n          puth(prev_bus + 1U);\n          puts(\"\\n\");\n          current_board->set_can_mode(CAN_MODE_NORMAL);\n          bus_lookup[prev_bus] = prev_bus;\n          can_num_lookup[prev_bus] = prev_bus;\n          can_num_lookup[3] = -1;\n          bool ret = can_init(prev_bus);\n          UNUSED(ret);\n          break;\n        default:\n          // GMLAN was not set on either BUS 1 or 2\n          break;\n      }\n    }\n\n    // now enable GMLAN on the new bus\n    switch (bus) {\n      case 1:\n      case 2:\n        puts(\"Enable GMLAN on CAN\");\n        puth(bus + 1U);\n        puts(\"\\n\");\n        current_board->set_can_mode((bus == 1U) ? CAN_MODE_GMLAN_CAN2 : CAN_MODE_GMLAN_CAN3);\n        bus_lookup[bus] = 3;\n        can_num_lookup[bus] = -1;\n        can_num_lookup[3] = bus;\n        bool ret = can_init(bus);\n        UNUSED(ret);\n        break;\n      case 0xFF:  //-1 unsigned\n        break;\n      default:\n        puts(\"GMLAN can only be set on CAN2 or CAN3\\n\");\n        break;\n    }\n  } else {\n    puts(\"GMLAN not available on black panda\\n\");\n  }\n}\n\n// CAN error\nvoid can_sce(CAN_TypeDef *CAN) {\n  ENTER_CRITICAL();\n\n  #ifdef DEBUG\n    if (CAN==CAN1) puts(\"CAN1:  \");\n    if (CAN==CAN2) puts(\"CAN2:  \");\n    #ifdef CAN3\n      if (CAN==CAN3) puts(\"CAN3:  \");\n    #endif\n    puts(\"MSR:\");\n    puth(CAN->MSR);\n    puts(\" TSR:\");\n    puth(CAN->TSR);\n    puts(\" RF0R:\");\n    puth(CAN->RF0R);\n    puts(\" RF1R:\");\n    puth(CAN->RF1R);\n    puts(\" ESR:\");\n    puth(CAN->ESR);\n    puts(\"\\n\");\n  #endif\n\n  can_err_cnt += 1;\n  llcan_clear_send(CAN);\n  EXIT_CRITICAL();\n}\n\n// ***************************** CAN *****************************\nvoid process_can(uint8_t can_number) {\n  if (can_number != 0xffU) {\n\n    ENTER_CRITICAL();\n\n    CAN_TypeDef *CAN = CANIF_FROM_CAN_NUM(can_number);\n    uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);\n\n    // check for empty mailbox\n    CAN_FIFOMailBox_TypeDef to_send;\n    if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {\n      // add successfully transmitted message to my fifo\n      if ((CAN->TSR & CAN_TSR_RQCP0) == CAN_TSR_RQCP0) {\n        can_txd_cnt += 1;\n\n        if ((CAN->TSR & CAN_TSR_TXOK0) == CAN_TSR_TXOK0) {\n          CAN_FIFOMailBox_TypeDef to_push;\n          to_push.RIR = CAN->sTxMailBox[0].TIR;\n          to_push.RDTR = (CAN->sTxMailBox[0].TDTR & 0xFFFF000FU) | ((CAN_BUS_RET_FLAG | bus_number) << 4);\n          to_push.RDLR = CAN->sTxMailBox[0].TDLR;\n          to_push.RDHR = CAN->sTxMailBox[0].TDHR;\n          can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;\n        }\n\n        if ((CAN->TSR & CAN_TSR_TERR0) == CAN_TSR_TERR0) {\n          #ifdef DEBUG\n            puts(\"CAN TX ERROR!\\n\");\n          #endif\n        }\n\n        if ((CAN->TSR & CAN_TSR_ALST0) == CAN_TSR_ALST0) {\n          #ifdef DEBUG\n            puts(\"CAN TX ARBITRATION LOST!\\n\");\n          #endif\n        }\n\n        // clear interrupt\n        // careful, this can also be cleared by requesting a transmission\n        CAN->TSR |= CAN_TSR_RQCP0;\n      }\n\n      if (can_pop(can_queues[bus_number], &to_send)) {\n        can_tx_cnt += 1;\n        // only send if we have received a packet\n        CAN->sTxMailBox[0].TDLR = to_send.RDLR;\n        CAN->sTxMailBox[0].TDHR = to_send.RDHR;\n        CAN->sTxMailBox[0].TDTR = to_send.RDTR;\n        CAN->sTxMailBox[0].TIR = to_send.RIR;\n\n        if (can_tx_check_min_slots_free(MAX_CAN_MSGS_PER_BULK_TRANSFER)) {\n          usb_outep3_resume_if_paused();\n        }\n      }\n    }\n\n    EXIT_CRITICAL();\n  }\n}\n\n// CAN receive handlers\n// blink blue when we are receiving CAN messages\nvoid can_rx(uint8_t can_number) {\n  CAN_TypeDef *CAN = CANIF_FROM_CAN_NUM(can_number);\n  uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);\n  while ((CAN->RF0R & CAN_RF0R_FMP0) != 0) {\n    can_rx_cnt += 1;\n\n    // can is live\n    pending_can_live = 1;\n\n    // add to my fifo\n    CAN_FIFOMailBox_TypeDef to_push;\n    to_push.RIR = CAN->sFIFOMailBox[0].RIR;\n    to_push.RDTR = CAN->sFIFOMailBox[0].RDTR;\n    to_push.RDLR = CAN->sFIFOMailBox[0].RDLR;\n    to_push.RDHR = CAN->sFIFOMailBox[0].RDHR;\n\n    // modify RDTR for our API\n    to_push.RDTR = (to_push.RDTR & 0xFFFF000F) | (bus_number << 4);\n\n    // forwarding (panda only)\n    int bus_fwd_num = (can_forwarding[bus_number] != -1) ? can_forwarding[bus_number] : safety_fwd_hook(bus_number, &to_push);\n    if (bus_fwd_num != -1) {\n      CAN_FIFOMailBox_TypeDef to_send;\n      to_send.RIR = to_push.RIR | 1; // TXRQ\n      to_send.RDTR = to_push.RDTR;\n      to_send.RDLR = to_push.RDLR;\n      to_send.RDHR = to_push.RDHR;\n      can_send(&to_send, bus_fwd_num, true);\n    }\n\n    can_rx_errs += safety_rx_hook(&to_push) ? 0U : 1U;\n    ignition_can_hook(&to_push);\n\n    current_board->set_led(LED_BLUE, true);\n    can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;\n\n    // next\n    CAN->RF0R |= CAN_RF0R_RFOM0;\n  }\n}\n\nvoid CAN1_TX_IRQ_Handler(void) { process_can(0); }\nvoid CAN1_RX0_IRQ_Handler(void) { can_rx(0); }\nvoid CAN1_SCE_IRQ_Handler(void) { can_sce(CAN1); }\n\nvoid CAN2_TX_IRQ_Handler(void) { process_can(1); }\nvoid CAN2_RX0_IRQ_Handler(void) { can_rx(1); }\nvoid CAN2_SCE_IRQ_Handler(void) { can_sce(CAN2); }\n\nvoid CAN3_TX_IRQ_Handler(void) { process_can(2); }\nvoid CAN3_RX0_IRQ_Handler(void) { can_rx(2); }\nvoid CAN3_SCE_IRQ_Handler(void) { can_sce(CAN3); }\n\nbool can_init(uint8_t can_number) {\n  bool ret = false;\n\n  REGISTER_INTERRUPT(CAN1_TX_IRQn, CAN1_TX_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(CAN1_RX0_IRQn, CAN1_RX0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(CAN1_SCE_IRQn, CAN1_SCE_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(CAN2_TX_IRQn, CAN2_TX_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)\n  REGISTER_INTERRUPT(CAN2_RX0_IRQn, CAN2_RX0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)\n  REGISTER_INTERRUPT(CAN2_SCE_IRQn, CAN2_SCE_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)\n  REGISTER_INTERRUPT(CAN3_TX_IRQn, CAN3_TX_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)\n  REGISTER_INTERRUPT(CAN3_RX0_IRQn, CAN3_RX0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)\n  REGISTER_INTERRUPT(CAN3_SCE_IRQn, CAN3_SCE_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)\n\n  if (can_number != 0xffU) {\n    CAN_TypeDef *CAN = CANIF_FROM_CAN_NUM(can_number);\n    ret &= can_set_speed(can_number);\n    ret &= llcan_init(CAN);\n    // in case there are queued up messages\n    process_can(can_number);\n  }\n  return ret;\n}\n"
  },
  {
    "path": "panda/board/drivers/can_common.h",
    "content": "typedef struct {\n  volatile uint32_t w_ptr;\n  volatile uint32_t r_ptr;\n  uint32_t fifo_size;\n  CAN_FIFOMailBox_TypeDef *elems;\n} can_ring;\n\n#define CAN_BUS_RET_FLAG 0x80U\n#define CAN_BUS_NUM_MASK 0x7FU\n\n#define BUS_MAX 4U\n\nuint32_t can_rx_errs = 0;\nuint32_t can_send_errs = 0;\nuint32_t can_fwd_errs = 0;\nuint32_t gmlan_send_errs = 0;\n\nextern int can_live;\nextern int pending_can_live;\n\n// must reinit after changing these\nextern int can_loopback;\nextern int can_silent;\nextern uint32_t can_speed[4];\nextern uint32_t can_data_speed[3];\n\n// Ignition detected from CAN meessages\nbool ignition_can = false;\nbool ignition_cadillac = false;\nuint32_t ignition_can_cnt = 0U;\n\n#define ALL_CAN_SILENT 0xFF\n#define ALL_CAN_LIVE 0\n\nint can_live = 0;\nint pending_can_live = 0;\nint can_loopback = 0;\nint can_silent = ALL_CAN_SILENT;\n\n// ******************* functions prototypes *********************\nbool can_init(uint8_t can_number);\nvoid process_can(uint8_t can_number);\n\n// ********************* instantiate queues *********************\n#define can_buffer(x, size) \\\n  CAN_FIFOMailBox_TypeDef elems_##x[size]; \\\n  can_ring can_##x = { .w_ptr = 0, .r_ptr = 0, .fifo_size = (size), .elems = (CAN_FIFOMailBox_TypeDef *)&(elems_##x) };\n\ncan_buffer(rx_q, 0x1000)\ncan_buffer(tx1_q, 0x100)\ncan_buffer(tx2_q, 0x100)\ncan_buffer(tx3_q, 0x100)\ncan_buffer(txgmlan_q, 0x100)\n// FIXME:\n// cppcheck-suppress misra-c2012-9.3\ncan_ring *can_queues[] = {&can_tx1_q, &can_tx2_q, &can_tx3_q, &can_txgmlan_q};\n\n// global CAN stats\nint can_rx_cnt = 0;\nint can_tx_cnt = 0;\nint can_txd_cnt = 0;\nint can_err_cnt = 0;\nint can_overflow_cnt = 0;\n\n// ********************* interrupt safe queue *********************\nbool can_pop(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {\n  bool ret = 0;\n\n  ENTER_CRITICAL();\n  if (q->w_ptr != q->r_ptr) {\n    *elem = q->elems[q->r_ptr];\n    if ((q->r_ptr + 1U) == q->fifo_size) {\n      q->r_ptr = 0;\n    } else {\n      q->r_ptr += 1U;\n    }\n    ret = 1;\n  }\n  EXIT_CRITICAL();\n\n  return ret;\n}\n\nbool can_push(can_ring *q, CAN_FIFOMailBox_TypeDef *elem) {\n  bool ret = false;\n  uint32_t next_w_ptr;\n\n  ENTER_CRITICAL();\n  if ((q->w_ptr + 1U) == q->fifo_size) {\n    next_w_ptr = 0;\n  } else {\n    next_w_ptr = q->w_ptr + 1U;\n  }\n  if (next_w_ptr != q->r_ptr) {\n    q->elems[q->w_ptr] = *elem;\n    q->w_ptr = next_w_ptr;\n    ret = true;\n  }\n  EXIT_CRITICAL();\n  if (!ret) {\n    can_overflow_cnt++;\n    #ifdef DEBUG\n      puts(\"can_push failed!\\n\");\n    #endif\n  }\n  return ret;\n}\n\nuint32_t can_slots_empty(can_ring *q) {\n  uint32_t ret = 0;\n\n  ENTER_CRITICAL();\n  if (q->w_ptr >= q->r_ptr) {\n    ret = q->fifo_size - 1U - q->w_ptr + q->r_ptr;\n  } else {\n    ret = q->r_ptr - q->w_ptr - 1U;\n  }\n  EXIT_CRITICAL();\n\n  return ret;\n}\n\nvoid can_clear(can_ring *q) {\n  ENTER_CRITICAL();\n  q->w_ptr = 0;\n  q->r_ptr = 0;\n  EXIT_CRITICAL();\n}\n\n// assign CAN numbering\n// bus num: Can bus number on ODB connector. Sent to/from USB\n//    Min: 0; Max: 127; Bit 7 marks message as receipt (bus 129 is receipt for but 1)\n// cans: Look up MCU can interface from bus number\n// can number: numeric lookup for MCU CAN interfaces (0 = CAN1, 1 = CAN2, etc);\n// bus_lookup: Translates from 'can number' to 'bus number'.\n// can_num_lookup: Translates from 'bus number' to 'can number'.\n// can_forwarding: Given a bus num, lookup bus num to forward to. -1 means no forward.\n\n// Helpers\n// Panda:       Bus 0=CAN1   Bus 1=CAN2   Bus 2=CAN3\nuint8_t bus_lookup[] = {0,1,2};\nuint8_t can_num_lookup[] = {0,1,2,-1};\nint8_t can_forwarding[] = {-1,-1,-1,-1};\nuint32_t can_speed[] = {5000, 5000, 5000, 333};\nuint32_t can_data_speed[] = {5000, 5000, 5000}; //For CAN FD with BRS only\n#define CAN_MAX 3U\n\n#define CANIF_FROM_CAN_NUM(num) (cans[num])\n#define BUS_NUM_FROM_CAN_NUM(num) (bus_lookup[num])\n#define CAN_NUM_FROM_BUS_NUM(num) (can_num_lookup[num])\n\nvoid can_init_all(void) {\n  bool ret = true;\n  for (uint8_t i=0U; i < CAN_MAX; i++) {\n    can_clear(can_queues[i]);\n    ret &= can_init(i);\n  }\n  UNUSED(ret);\n}\n\nvoid can_flip_buses(uint8_t bus1, uint8_t bus2){\n  bus_lookup[bus1] = bus2;\n  bus_lookup[bus2] = bus1;\n  can_num_lookup[bus1] = bus2;\n  can_num_lookup[bus2] = bus1;\n}\n\nvoid ignition_can_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n  int bus = GET_BUS(to_push);\n  int addr = GET_ADDR(to_push);\n  int len = GET_LEN(to_push);\n\n  ignition_can_cnt = 0U;  // reset counter\n\n  if (bus == 0) {\n    // TODO: verify on all supported GM models that we can reliably detect ignition using only this signal,\n    // since the 0x1F1 signal can briefly go low immediately after ignition\n    if ((addr == 0x160) && (len == 5)) {\n      // this message isn't all zeros when ignition is on\n      ignition_cadillac = GET_BYTES_04(to_push) != 0;\n    }\n    // GM exception\n    if ((addr == 0x1F1) && (len == 8)) {\n      // Bit 5 is ignition \"on\"\n      bool ignition_gm = ((GET_BYTE(to_push, 0) & 0x20) != 0);\n      ignition_can = ignition_gm || ignition_cadillac;\n    }\n    // Tesla exception\n    if ((addr == 0x348) && (len == 8)) {\n      // GTW_status\n      ignition_can = (GET_BYTE(to_push, 0) & 0x1) != 0;\n    }\n  }\n}\n\nbool can_tx_check_min_slots_free(uint32_t min) {\n  return\n    (can_slots_empty(&can_tx1_q) >= min) &&\n    (can_slots_empty(&can_tx2_q) >= min) &&\n    (can_slots_empty(&can_tx3_q) >= min) &&\n    (can_slots_empty(&can_txgmlan_q) >= min);\n}\n\nvoid can_send(CAN_FIFOMailBox_TypeDef *to_push, uint8_t bus_number, bool skip_tx_hook) {\n  if (skip_tx_hook || safety_tx_hook(to_push) != 0) {\n    if (bus_number < BUS_MAX) {\n      // add CAN packet to send queue\n      // bus number isn't passed through\n      to_push->RDTR &= 0xF;\n      if ((bus_number == 3U) && (can_num_lookup[3] == 0xFFU)) {\n        gmlan_send_errs += bitbang_gmlan(to_push) ? 0U : 1U;\n      } else {\n        can_fwd_errs += can_push(can_queues[bus_number], to_push) ? 0U : 1U;\n        process_can(CAN_NUM_FROM_BUS_NUM(bus_number));\n      }\n    }\n  }\n}\n\nvoid can_set_forwarding(int from, int to) {\n  can_forwarding[from] = to;\n}\n"
  },
  {
    "path": "panda/board/drivers/fan.h",
    "content": "uint16_t fan_tach_counter = 0U;\nuint16_t fan_rpm = 0U;\n\nvoid fan_set_power(uint8_t percentage){\n  pwm_set(TIM3, 3, percentage);\n}\n\n// Can be way more acurate than this, but this is probably good enough for our purposes.\n// Call this every second\nvoid fan_tick(void){\n    // 4 interrupts per rotation\n    fan_rpm = fan_tach_counter * 15U;\n    fan_tach_counter = 0U;\n}\n"
  },
  {
    "path": "panda/board/drivers/fdcan.h",
    "content": "// IRQs: FDCAN1_IT0, FDCAN1_IT1\n//       FDCAN2_IT0, FDCAN2_IT1\n//       FDCAN3_IT0, FDCAN3_IT1\n\n#define BUS_OFF_FAIL_LIMIT 2U\nuint8_t bus_off_err[] = {0U, 0U, 0U};\n\nFDCAN_GlobalTypeDef *cans[] = {FDCAN1, FDCAN2, FDCAN3};\n\nbool can_set_speed(uint8_t can_number) {\n  bool ret = true;\n  FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);\n  uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);\n\n  ret &= llcan_set_speed(CANx, can_speed[bus_number], can_data_speed[bus_number], can_loopback, (unsigned int)(can_silent) & (1U << can_number));\n  return ret;\n}\n\nvoid can_set_gmlan(uint8_t bus) {\n  UNUSED(bus);\n  puts(\"GMLAN not available on red panda\\n\");\n}\n\nvoid cycle_transceiver(uint8_t can_number) {\n  // FDCAN1 = trans 1, FDCAN3 = trans 3, FDCAN2 = trans 2 normal or 4 flipped harness\n  uint8_t transceiver_number = can_number;\n  if (can_number == 2U) {\n    uint8_t flip = (car_harness_status == HARNESS_STATUS_FLIPPED) ? 2U : 0U;\n    transceiver_number += flip;\n  }\n  current_board->enable_can_transceiver(transceiver_number, false);\n  delay(20000);\n  current_board->enable_can_transceiver(transceiver_number, true);\n  bus_off_err[can_number] = 0U;\n  puts(\"Cycled transceiver number: \"); puth(transceiver_number); puts(\"\\n\");\n}\n\n// ***************************** CAN *****************************\nvoid process_can(uint8_t can_number) {\n  if (can_number != 0xffU) {\n    ENTER_CRITICAL();\n\n    FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);\n    uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);\n    \n    CANx->IR |= FDCAN_IR_TFE; // Clear Tx FIFO Empty flag\n\n    if ((CANx->TXFQS & FDCAN_TXFQS_TFQF) == 0) {\n      CAN_FIFOMailBox_TypeDef to_send;\n      if (can_pop(can_queues[bus_number], &to_send)) {\n        can_tx_cnt += 1;\n        uint32_t TxFIFOSA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET) + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);\n        uint8_t tx_index = (CANx->TXFQS >> FDCAN_TXFQS_TFQPI_Pos) & 0x1F;\n        // only send if we have received a packet\n        CAN_FIFOMailBox_TypeDef *fifo;\n        fifo = (CAN_FIFOMailBox_TypeDef *)(TxFIFOSA + (tx_index * FDCAN_TX_FIFO_EL_SIZE));\n\n        // Convert from \"mailbox type\"\n        fifo->RIR = ((to_send.RIR & 0x6) << 28) | (to_send.RIR >> 3);  // identifier format and frame type | identifier\n        //REDEBUG: enable CAN FD and BRS for test purposes\n        //fifo->RDTR = ((to_send.RDTR & 0xF) << 16) | ((to_send.RDTR) >> 16) | (1U << 21) | (1U << 20); // DLC (length) | timestamp | enable CAN FD | enable BRS\n        fifo->RDTR = ((to_send.RDTR & 0xF) << 16) | ((to_send.RDTR) >> 16); // DLC (length) | timestamp\n        fifo->RDLR = to_send.RDLR;\n        fifo->RDHR = to_send.RDHR;\n        \n        CANx->TXBAR = (1UL << tx_index); \n\n        // Send back to USB\n        can_txd_cnt += 1;\n        CAN_FIFOMailBox_TypeDef to_push;\n        to_push.RIR = to_send.RIR;\n        to_push.RDTR = (to_send.RDTR & 0xFFFF000FU) | ((CAN_BUS_RET_FLAG | bus_number) << 4);\n        to_push.RDLR = to_send.RDLR;\n        to_push.RDHR = to_send.RDHR;\n        can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;\n\n        if (can_tx_check_min_slots_free(MAX_CAN_MSGS_PER_BULK_TRANSFER)) {\n          usb_outep3_resume_if_paused();\n        }\n      }\n    }\n\n    // Recover after Bus-off state\n    if (((CANx->PSR & FDCAN_PSR_BO) != 0) && ((CANx->CCCR & FDCAN_CCCR_INIT) != 0)) {\n      bus_off_err[can_number] += 1U;\n      puts(\"CAN is in Bus_Off state! Resetting... CAN number: \"); puth(can_number); puts(\"\\n\");\n      if (bus_off_err[can_number] > BUS_OFF_FAIL_LIMIT) {\n        cycle_transceiver(can_number);\n      }\n      CANx->IR = 0xFFC60000U; // Reset all flags(Only errors!)\n      CANx->CCCR &= ~(FDCAN_CCCR_INIT);\n      uint32_t timeout_counter = 0U;\n      while((CANx->CCCR & FDCAN_CCCR_INIT) != 0) {\n        // Delay for about 1ms\n        delay(10000);\n        timeout_counter++;\n\n        if(timeout_counter >= CAN_INIT_TIMEOUT_MS){\n          puts(CAN_NAME_FROM_CANIF(CANx)); puts(\" Bus_Off reset timed out!\\n\");\n          break;\n        }\n      }\n    }\n    EXIT_CRITICAL();\n  }\n}\n\n// CAN receive handlers\n// blink blue when we are receiving CAN messages\nvoid can_rx(uint8_t can_number) {\n  FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);\n  uint8_t bus_number = BUS_NUM_FROM_CAN_NUM(can_number);\n  uint8_t rx_fifo_idx;\n\n  // Rx FIFO 0 new message\n  if((CANx->IR & FDCAN_IR_RF0N) != 0) {\n    CANx->IR |= FDCAN_IR_RF0N;\n    while((CANx->RXF0S & FDCAN_RXF0S_F0FL) != 0) {\n      can_rx_cnt += 1;\n\n      // can is live\n      pending_can_live = 1;\n\n      // getting new message index (0 to 63)\n      rx_fifo_idx = (uint8_t)((CANx->RXF0S >> FDCAN_RXF0S_F0GI_Pos) & 0x3F);\n\n      uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);\n      CAN_FIFOMailBox_TypeDef to_push;\n      CAN_FIFOMailBox_TypeDef *fifo;\n\n      // getting address\n      fifo = (CAN_FIFOMailBox_TypeDef *)(RxFIFO0SA + (rx_fifo_idx * FDCAN_RX_FIFO_0_EL_SIZE));\n\n      // Need to convert real CAN frame format to mailbox \"type\"\n      to_push.RIR = ((fifo->RIR >> 28) & 0x6) | (fifo->RIR << 3); // identifier format and frame type | identifier\n      to_push.RDTR = ((fifo->RDTR >> 16) & 0xF) | (fifo->RDTR << 16); // DLC (length) | timestamp\n      to_push.RDLR = fifo->RDLR;\n      to_push.RDHR = fifo->RDHR;\n\n      // modify RDTR for our API\n      to_push.RDTR = (to_push.RDTR & 0xFFFF000F) | (bus_number << 4);\n\n      // forwarding (panda only)\n      int bus_fwd_num = (can_forwarding[bus_number] != -1) ? can_forwarding[bus_number] : safety_fwd_hook(bus_number, &to_push);\n      if (bus_fwd_num != -1) {\n        CAN_FIFOMailBox_TypeDef to_send;\n        to_send.RIR = to_push.RIR;\n        to_send.RDTR = to_push.RDTR;\n        to_send.RDLR = to_push.RDLR;\n        to_send.RDHR = to_push.RDHR;\n        can_send(&to_send, bus_fwd_num, true);\n      }\n\n      can_rx_errs += safety_rx_hook(&to_push) ? 0U : 1U;\n      ignition_can_hook(&to_push);\n\n      current_board->set_led(LED_BLUE, true);\n      can_send_errs += can_push(&can_rx_q, &to_push) ? 0U : 1U;\n\n      // update read index \n      CANx->RXF0A = rx_fifo_idx;\n    }\n\n  } else if((CANx->IR & (FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_EW | FDCAN_IR_MRAF | FDCAN_IR_TOO)) != 0) {\n    #ifdef DEBUG\n      puts(\"FDCAN error, FDCAN_IR: \");puth(CANx->IR);puts(\"\\n\");\n    #endif\n    CANx->IR |= (FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_EW | FDCAN_IR_MRAF | FDCAN_IR_TOO); // Clean all error flags\n    can_err_cnt += 1;\n  } else { \n    \n  }\n  \n}\n\nvoid FDCAN1_IT0_IRQ_Handler(void) { can_rx(0); }\nvoid FDCAN1_IT1_IRQ_Handler(void) { process_can(0); }\n\nvoid FDCAN2_IT0_IRQ_Handler(void) { can_rx(1); }\nvoid FDCAN2_IT1_IRQ_Handler(void) { process_can(1); }\n\nvoid FDCAN3_IT0_IRQ_Handler(void) { can_rx(2);  }\nvoid FDCAN3_IT1_IRQ_Handler(void) { process_can(2); }\n\nbool can_init(uint8_t can_number) {\n  bool ret = false;\n\n  REGISTER_INTERRUPT(FDCAN1_IT0_IRQn, FDCAN1_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(FDCAN1_IT1_IRQn, FDCAN1_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(FDCAN2_IT0_IRQn, FDCAN2_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)\n  REGISTER_INTERRUPT(FDCAN2_IT1_IRQn, FDCAN2_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_2)\n  REGISTER_INTERRUPT(FDCAN3_IT0_IRQn, FDCAN3_IT0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)\n  REGISTER_INTERRUPT(FDCAN3_IT1_IRQn, FDCAN3_IT1_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_3)\n\n  if (can_number != 0xffU) {\n    FDCAN_GlobalTypeDef *CANx = CANIF_FROM_CAN_NUM(can_number);\n    ret &= can_set_speed(can_number);\n    ret &= llcan_init(CANx);\n    // in case there are queued up messages\n    process_can(can_number);\n  }\n  return ret;\n}\n"
  },
  {
    "path": "panda/board/drivers/gmlan_alt.h",
    "content": "#define GMLAN_TICKS_PER_SECOND 33300 //1sec @ 33.3kbps\n#define GMLAN_TICKS_PER_TIMEOUT_TICKLE 500 //15ms @ 33.3kbps\n#define GMLAN_HIGH 0 //0 is high on bus (dominant)\n#define GMLAN_LOW 1 //1 is low on bus\n\n#define DISABLED -1\n#define BITBANG 0\n#define GPIO_SWITCH 1\n\n#define MAX_BITS_CAN_PACKET (200)\n\nint gmlan_alt_mode = DISABLED;\n\n// returns out_len\nint do_bitstuff(char *out, char *in, int in_len) {\n  int last_bit = -1;\n  int bit_cnt = 0;\n  int j = 0;\n  for (int i = 0; i < in_len; i++) {\n    char bit = in[i];\n    out[j] = bit;\n    j++;\n\n    // do the stuffing\n    if (bit == last_bit) {\n      bit_cnt++;\n      if (bit_cnt == 5) {\n        // 5 in a row the same, do stuff\n        last_bit = !bit;\n        out[j] = last_bit;\n        j++;\n        bit_cnt = 1;\n      }\n    } else {\n      // this is a new bit\n      last_bit = bit;\n      bit_cnt = 1;\n    }\n  }\n  return j;\n}\n\nint append_crc(char *in, int in_len) {\n  unsigned int crc = 0;\n  for (int i = 0; i < in_len; i++) {\n    crc <<= 1;\n    if (((unsigned int)(in[i]) ^ ((crc >> 15) & 1U)) != 0U) {\n      crc = crc ^ 0x4599U;\n    }\n    crc &= 0x7fffU;\n  }\n  int in_len_copy = in_len;\n  for (int i = 14; i >= 0; i--) {\n    in[in_len_copy] = (crc >> (unsigned int)(i)) & 1U;\n    in_len_copy++;\n  }\n  return in_len_copy;\n}\n\nint append_bits(char *in, int in_len, char *app, int app_len) {\n  int in_len_copy = in_len;\n  for (int i = 0; i < app_len; i++) {\n    in[in_len_copy] = app[i];\n    in_len_copy++;\n  }\n  return in_len_copy;\n}\n\nint append_int(char *in, int in_len, int val, int val_len) {\n  int in_len_copy = in_len;\n  for (int i = val_len - 1; i >= 0; i--) {\n    in[in_len_copy] = ((unsigned int)(val) & (1U << (unsigned int)(i))) != 0U;\n    in_len_copy++;\n  }\n  return in_len_copy;\n}\n\nint get_bit_message(char *out, CAN_FIFOMailBox_TypeDef *to_bang) {\n  char pkt[MAX_BITS_CAN_PACKET];\n  char footer[] = {\n    1,  // CRC delimiter\n    1,  // ACK\n    1,  // ACK delimiter\n    1,1,1,1,1,1,1, // EOF\n    1,1,1, // IFS\n  };\n\n  int len = 0;\n\n  // test packet\n  int dlc_len = to_bang->RDTR & 0xF;\n  len = append_int(pkt, len, 0, 1);    // Start-of-frame\n\n  if ((to_bang->RIR & 4) != 0) {\n    // extended identifier\n    len = append_int(pkt, len, to_bang->RIR >> 21, 11);  // Identifier\n    len = append_int(pkt, len, 3, 2);    // SRR+IDE\n    len = append_int(pkt, len, (to_bang->RIR >> 3) & ((1U << 18) - 1U), 18);  // Identifier\n    len = append_int(pkt, len, 0, 3);    // RTR+r1+r0\n  } else {\n    // standard identifier\n    len = append_int(pkt, len, to_bang->RIR >> 21, 11);  // Identifier\n    len = append_int(pkt, len, 0, 3);    // RTR+IDE+reserved\n  }\n\n  len = append_int(pkt, len, dlc_len, 4);    // Data length code\n\n  // append data\n  for (int i = 0; i < dlc_len; i++) {\n    unsigned char dat = ((unsigned char *)(&(to_bang->RDLR)))[i];\n    len = append_int(pkt, len, dat, 8);\n  }\n\n  // append crc\n  len = append_crc(pkt, len);\n\n  // do bitstuffing\n  len = do_bitstuff(out, pkt, len);\n\n  // append footer\n  len = append_bits(out, len, footer, sizeof(footer));\n  return len;\n}\n\nvoid TIM12_IRQ_Handler(void);\n\nvoid setup_timer(void) {\n  // register interrupt\n  REGISTER_INTERRUPT(TIM8_BRK_TIM12_IRQn, TIM12_IRQ_Handler, 40000U, FAULT_INTERRUPT_RATE_GMLAN)\n\n  // setup\n  register_set(&(TIM12->PSC), (48-1), 0xFFFFU);    // Tick on 1 us\n  register_set(&(TIM12->CR1), TIM_CR1_CEN, 0x3FU); // Enable\n  register_set(&(TIM12->ARR), (30-1), 0xFFFFU);   // 33.3 kbps\n\n  // in case it's disabled\n  NVIC_EnableIRQ(TIM8_BRK_TIM12_IRQn);\n\n  // run the interrupt\n  register_set(&(TIM12->DIER), TIM_DIER_UIE, 0x5F5FU); // Update interrupt\n  TIM12->SR = 0;\n}\n\nint gmlan_timeout_counter = GMLAN_TICKS_PER_TIMEOUT_TICKLE; //GMLAN transceiver times out every 17ms held high; tickle every 15ms\nint can_timeout_counter = GMLAN_TICKS_PER_SECOND; //1 second\n\nint inverted_bit_to_send = GMLAN_HIGH;\nint gmlan_switch_below_timeout = -1;\nint gmlan_switch_timeout_enable = 0;\n\nvoid gmlan_switch_init(int timeout_enable) {\n  gmlan_switch_timeout_enable = timeout_enable;\n  gmlan_alt_mode = GPIO_SWITCH;\n  gmlan_switch_below_timeout = 1;\n  set_gpio_mode(GPIOB, 13, MODE_OUTPUT);\n\n  setup_timer();\n\n  inverted_bit_to_send = GMLAN_LOW; //We got initialized, set the output low\n}\n\nvoid set_gmlan_digital_output(int to_set) {\n  inverted_bit_to_send = to_set;\n  /*\n  puts(\"Writing \");\n  puth(inverted_bit_to_send);\n  puts(\"\\n\");\n  */\n}\n\nvoid reset_gmlan_switch_timeout(void) {\n  can_timeout_counter = GMLAN_TICKS_PER_SECOND;\n  gmlan_switch_below_timeout = 1;\n  gmlan_alt_mode = GPIO_SWITCH;\n}\n\nvoid set_bitbanged_gmlan(int val) {\n  if (val != 0) {\n    register_set_bits(&(GPIOB->ODR), (1U << 13));\n  } else {\n    register_clear_bits(&(GPIOB->ODR), (1U << 13));\n  }\n}\n\nchar pkt_stuffed[MAX_BITS_CAN_PACKET];\nint gmlan_sending = -1;\nint gmlan_sendmax = -1;\nbool gmlan_send_ok = true;\n\nint gmlan_silent_count = 0;\nint gmlan_fail_count = 0;\n#define REQUIRED_SILENT_TIME 10\n#define MAX_FAIL_COUNT 10\n\nvoid TIM12_IRQ_Handler(void) {\n  if (gmlan_alt_mode == BITBANG) {\n    if ((TIM12->SR & TIM_SR_UIF) && (gmlan_sendmax != -1)) {\n      int read = get_gpio_input(GPIOB, 12);\n      if (gmlan_silent_count < REQUIRED_SILENT_TIME) {\n        if (read == 0) {\n          gmlan_silent_count = 0;\n        } else {\n          gmlan_silent_count++;\n        }\n      } else {\n        bool retry = 0;\n        // in send loop\n        if ((gmlan_sending > 0) &&  // not first bit\n           ((read == 0) && (pkt_stuffed[gmlan_sending-1] == 1)) &&  // bus wrongly dominant\n           (gmlan_sending != (gmlan_sendmax - 11))) {    //not ack bit\n          puts(\"GMLAN ERR: bus driven at \");\n          puth(gmlan_sending);\n          puts(\"\\n\");\n          retry = 1;\n        } else if ((read == 1) && (gmlan_sending == (gmlan_sendmax - 11))) {    // recessive during ACK\n          puts(\"GMLAN ERR: didn't recv ACK\\n\");\n          retry = 1;\n        } else {\n          // do not retry\n        }\n        if (retry) {\n          // reset sender (retry after 7 silent)\n          set_bitbanged_gmlan(1); // recessive\n          gmlan_silent_count = 0;\n          gmlan_sending = 0;\n          gmlan_fail_count++;\n          if (gmlan_fail_count == MAX_FAIL_COUNT) {\n            puts(\"GMLAN ERR: giving up send\\n\");\n            gmlan_send_ok = false;\n          }\n        } else {\n          set_bitbanged_gmlan(pkt_stuffed[gmlan_sending]);\n          gmlan_sending++;\n        }\n      }\n      if ((gmlan_sending == gmlan_sendmax) || (gmlan_fail_count == MAX_FAIL_COUNT)) {\n        set_bitbanged_gmlan(1); // recessive\n        set_gpio_mode(GPIOB, 13, MODE_INPUT);\n        register_clear_bits(&(TIM12->DIER), TIM_DIER_UIE); // No update interrupt\n        register_set(&(TIM12->CR1), 0U, 0x3FU); // Disable timer\n        gmlan_sendmax = -1;   // exit\n      }\n    }\n  } else if (gmlan_alt_mode == GPIO_SWITCH) {\n    if ((TIM12->SR & TIM_SR_UIF) && (gmlan_switch_below_timeout != -1)) {\n      if ((can_timeout_counter == 0) && gmlan_switch_timeout_enable) {\n        //it has been more than 1 second since timeout was reset; disable timer and restore the GMLAN output\n        set_gpio_output(GPIOB, 13, GMLAN_LOW);\n        gmlan_switch_below_timeout = -1;\n        gmlan_timeout_counter = GMLAN_TICKS_PER_TIMEOUT_TICKLE;\n        gmlan_alt_mode = DISABLED;\n      }\n      else {\n        can_timeout_counter--;\n        if (gmlan_timeout_counter == 0) {\n          //Send a 1 (bus low) every 15ms to reset the GMLAN transceivers timeout\n          gmlan_timeout_counter = GMLAN_TICKS_PER_TIMEOUT_TICKLE;\n          set_gpio_output(GPIOB, 13, GMLAN_LOW);\n        }\n        else {\n          set_gpio_output(GPIOB, 13, inverted_bit_to_send);\n          gmlan_timeout_counter--;\n        }\n      }\n    }\n  } else {\n    // Invalid GMLAN mode. Do not put a print statement here, way too fast to keep up with\n  }\n  TIM12->SR = 0;\n}\n\nbool bitbang_gmlan(CAN_FIFOMailBox_TypeDef *to_bang) {\n  gmlan_send_ok = true;\n  gmlan_alt_mode = BITBANG;\n\n  if (gmlan_sendmax == -1) {\n    int len = get_bit_message(pkt_stuffed, to_bang);\n    gmlan_fail_count = 0;\n    gmlan_silent_count = 0;\n    gmlan_sending = 0;\n    gmlan_sendmax = len;\n    // setup for bitbang loop\n    set_bitbanged_gmlan(1); // recessive\n    set_gpio_mode(GPIOB, 13, MODE_OUTPUT);\n\n    // 33kbps\n    setup_timer();\n  }\n  return gmlan_send_ok;\n}\n"
  },
  {
    "path": "panda/board/drivers/gpio.h",
    "content": "#define MODE_INPUT 0\n#define MODE_OUTPUT 1\n#define MODE_ALTERNATE 2\n#define MODE_ANALOG 3\n\n#define PULL_NONE 0\n#define PULL_UP 1\n#define PULL_DOWN 2\n\n#define OUTPUT_TYPE_PUSH_PULL 0U\n#define OUTPUT_TYPE_OPEN_DRAIN 1U\n\nvoid set_gpio_mode(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int mode) {\n  ENTER_CRITICAL();\n  uint32_t tmp = GPIO->MODER;\n  tmp &= ~(3U << (pin * 2U));\n  tmp |= (mode << (pin * 2U));\n  register_set(&(GPIO->MODER), tmp, 0xFFFFFFFFU);\n  EXIT_CRITICAL();\n}\n\nvoid set_gpio_output(GPIO_TypeDef *GPIO, unsigned int pin, bool enabled) {\n  ENTER_CRITICAL();\n  if (enabled) {\n    register_set_bits(&(GPIO->ODR), (1U << pin));\n  } else {\n    register_clear_bits(&(GPIO->ODR), (1U << pin));\n  }\n  set_gpio_mode(GPIO, pin, MODE_OUTPUT);\n  EXIT_CRITICAL();\n}\n\nvoid set_gpio_output_type(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int output_type){\n  ENTER_CRITICAL();\n  if(output_type == OUTPUT_TYPE_OPEN_DRAIN) {\n    register_set_bits(&(GPIO->OTYPER), (1U << pin));\n  } else {\n    register_clear_bits(&(GPIO->OTYPER), (1U << pin));\n  }\n  EXIT_CRITICAL();\n}\n\nvoid set_gpio_alternate(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int mode) {\n  ENTER_CRITICAL();\n  uint32_t tmp = GPIO->AFR[pin >> 3U];\n  tmp &= ~(0xFU << ((pin & 7U) * 4U));\n  tmp |= mode << ((pin & 7U) * 4U);\n  register_set(&(GPIO->AFR[pin >> 3]), tmp, 0xFFFFFFFFU);\n  set_gpio_mode(GPIO, pin, MODE_ALTERNATE);\n  EXIT_CRITICAL();\n}\n\nvoid set_gpio_pullup(GPIO_TypeDef *GPIO, unsigned int pin, unsigned int mode) {\n  ENTER_CRITICAL();\n  uint32_t tmp = GPIO->PUPDR;\n  tmp &= ~(3U << (pin * 2U));\n  tmp |= (mode << (pin * 2U));\n  register_set(&(GPIO->PUPDR), tmp, 0xFFFFFFFFU);\n  EXIT_CRITICAL();\n}\n\nint get_gpio_input(GPIO_TypeDef *GPIO, unsigned int pin) {\n  return (GPIO->IDR & (1U << pin)) == (1U << pin);\n}\n\n// Detection with internal pullup\n#define PULL_EFFECTIVE_DELAY 4096\nbool detect_with_pull(GPIO_TypeDef *GPIO, int pin, int mode) {\n  set_gpio_mode(GPIO, pin, MODE_INPUT);\n  set_gpio_pullup(GPIO, pin, mode);\n  for (volatile int i=0; i<PULL_EFFECTIVE_DELAY; i++);\n  bool ret = get_gpio_input(GPIO, pin);\n  set_gpio_pullup(GPIO, pin, PULL_NONE);\n  return ret;\n}\n"
  },
  {
    "path": "panda/board/drivers/harness.h",
    "content": "uint8_t car_harness_status = 0U;\n#define HARNESS_STATUS_NC 0U\n#define HARNESS_STATUS_NORMAL 1U\n#define HARNESS_STATUS_FLIPPED 2U\n\nstruct harness_configuration {\n  const bool has_harness;\n  GPIO_TypeDef *GPIO_SBU1;\n  GPIO_TypeDef *GPIO_SBU2;\n  GPIO_TypeDef *GPIO_relay_SBU1;\n  GPIO_TypeDef *GPIO_relay_SBU2;\n  uint8_t pin_SBU1;\n  uint8_t pin_SBU2;\n  uint8_t pin_relay_SBU1;\n  uint8_t pin_relay_SBU2;\n  uint8_t adc_channel_SBU1;\n  uint8_t adc_channel_SBU2;\n};\n\n// this function will be the API for tici\nvoid set_intercept_relay(bool intercept) {\n  if (car_harness_status != HARNESS_STATUS_NC) {\n    if (intercept) {\n      puts(\"switching harness to intercept (relay on)\\n\");\n    } else {\n      puts(\"switching harness to passthrough (relay off)\\n\");\n    }\n\n    if(car_harness_status == HARNESS_STATUS_NORMAL){\n      set_gpio_output(current_board->harness_config->GPIO_relay_SBU2, current_board->harness_config->pin_relay_SBU2, !intercept);\n    } else {\n      set_gpio_output(current_board->harness_config->GPIO_relay_SBU1, current_board->harness_config->pin_relay_SBU1, !intercept);\n    }\n  }\n}\n\nbool harness_check_ignition(void) {\n  bool ret = false;\n  switch(car_harness_status){\n    case HARNESS_STATUS_NORMAL:\n      ret = !get_gpio_input(current_board->harness_config->GPIO_SBU1, current_board->harness_config->pin_SBU1);\n      break;\n    case HARNESS_STATUS_FLIPPED:\n      ret = !get_gpio_input(current_board->harness_config->GPIO_SBU2, current_board->harness_config->pin_SBU2);\n      break;\n    default:\n      break;\n  }\n  return ret;\n}\n\nuint8_t harness_detect_orientation(void) {\n  uint8_t ret = HARNESS_STATUS_NC;\n\n  #ifndef BOOTSTUB\n  uint32_t sbu1_voltage = adc_get(current_board->harness_config->adc_channel_SBU1);\n  uint32_t sbu2_voltage = adc_get(current_board->harness_config->adc_channel_SBU2);\n\n  // Detect connection and orientation\n  if((sbu1_voltage < HARNESS_CONNECTED_THRESHOLD) || (sbu2_voltage < HARNESS_CONNECTED_THRESHOLD)){\n    if (sbu1_voltage < sbu2_voltage) {\n      // orientation flipped (PANDA_SBU1->HARNESS_SBU1(relay), PANDA_SBU2->HARNESS_SBU2(ign))\n      ret = HARNESS_STATUS_FLIPPED;\n    } else {\n      // orientation normal (PANDA_SBU2->HARNESS_SBU1(relay), PANDA_SBU1->HARNESS_SBU2(ign))\n      ret = HARNESS_STATUS_NORMAL;\n    }\n  }\n  #endif\n\n  return ret;\n}\n\nvoid harness_init(void) {\n  // delay such that the connection is fully made before trying orientation detection\n  current_board->set_led(LED_BLUE, true);\n  delay(10000000);\n  current_board->set_led(LED_BLUE, false);\n\n  // try to detect orientation\n  uint8_t ret = harness_detect_orientation();\n  if (ret != HARNESS_STATUS_NC) {\n    puts(\"detected car harness with orientation \"); puth2(ret); puts(\"\\n\");\n    car_harness_status = ret;\n\n    // set the SBU lines to be inputs before using the relay. The lines are not 5V tolerant in ADC mode!\n    set_gpio_mode(current_board->harness_config->GPIO_SBU1, current_board->harness_config->pin_SBU1, MODE_INPUT);\n    set_gpio_mode(current_board->harness_config->GPIO_SBU2, current_board->harness_config->pin_SBU2, MODE_INPUT);\n\n    // keep busses connected by default\n    set_intercept_relay(false);\n  } else {\n    puts(\"failed to detect car harness!\\n\");\n  }\n}\n"
  },
  {
    "path": "panda/board/drivers/interrupts.h",
    "content": "typedef struct interrupt {\n  IRQn_Type irq_type;\n  void (*handler)(void);\n  uint32_t call_counter;\n  uint32_t max_call_rate;   // Call rate is defined as the amount of calls each second\n  uint32_t call_rate_fault;\n} interrupt;\n\nvoid interrupt_timer_init(void);\n\nvoid unused_interrupt_handler(void) {\n  // Something is wrong if this handler is called!\n  puts(\"Unused interrupt handler called!\\n\");\n  fault_occurred(FAULT_UNUSED_INTERRUPT_HANDLED);\n}\n\ninterrupt interrupts[NUM_INTERRUPTS];\n\n#define REGISTER_INTERRUPT(irq_num, func_ptr, call_rate, rate_fault) \\\n  interrupts[irq_num].irq_type = (irq_num); \\\n  interrupts[irq_num].handler = (func_ptr);  \\\n  interrupts[irq_num].call_counter = 0U;   \\\n  interrupts[irq_num].max_call_rate = (call_rate); \\\n  interrupts[irq_num].call_rate_fault = (rate_fault);\n\nbool check_interrupt_rate = false;\n\nvoid handle_interrupt(IRQn_Type irq_type){\n  interrupts[irq_type].call_counter++;\n  interrupts[irq_type].handler();\n\n  // Check that the interrupts don't fire too often\n  if(check_interrupt_rate && (interrupts[irq_type].call_counter > interrupts[irq_type].max_call_rate)){\n    puts(\"Interrupt 0x\"); puth(irq_type); puts(\" fired too often (0x\"); puth(interrupts[irq_type].call_counter); puts(\"/s)!\\n\");\n    fault_occurred(interrupts[irq_type].call_rate_fault);\n  }\n}\n\n// Reset interrupt counter every second\nvoid interrupt_timer_handler(void) {\n  if (INTERRUPT_TIMER->SR != 0) {\n    for(uint16_t i=0U; i<NUM_INTERRUPTS; i++){\n      interrupts[i].call_counter = 0U;\n    }\n  }\n  INTERRUPT_TIMER->SR = 0;\n}\n\nvoid init_interrupts(bool check_rate_limit){\n  check_interrupt_rate = check_rate_limit;\n\n  for(uint16_t i=0U; i<NUM_INTERRUPTS; i++){\n    interrupts[i].handler = unused_interrupt_handler;\n  }\n\n  // Init interrupt timer for a 1s interval\n  interrupt_timer_init();\n}\n"
  },
  {
    "path": "panda/board/drivers/kline_init.h",
    "content": "void TIM5_IRQ_Handler(void);\n\nvoid setup_timer5(void) {\n  // register interrupt\n  REGISTER_INTERRUPT(TIM5_IRQn, TIM5_IRQ_Handler, 1050000U, FAULT_INTERRUPT_RATE_KLINE_INIT)\n\n  // setup\n  register_set(&(TIM5->PSC), (48-1), 0xFFFFU);        // Tick on 1 us\n  register_set(&(TIM5->CR1), TIM_CR1_CEN, 0x3FU);     // Enable\n  register_set(&(TIM5->ARR), (5000-1), 0xFFFFFFFFU);  // Reset every 5 ms\n\n  // in case it's disabled\n  NVIC_EnableIRQ(TIM5_IRQn);\n\n  // run the interrupt\n  register_set(&(TIM5->DIER), TIM_DIER_UIE, 0x5F5FU); // Update interrupt\n  TIM5->SR = 0;\n}\n\nbool k_init = false;\nbool l_init = false;\nvoid setup_kline(bool bitbang) {\n  if (bitbang) {\n    if (k_init) {\n      set_gpio_output(GPIOC, 12, true);\n    }\n    if (l_init) {\n      set_gpio_output(GPIOC, 10, true);\n    }\n  } else {\n    if (k_init) {\n      set_gpio_mode(GPIOC, 12, MODE_ALTERNATE);\n    }\n    if (l_init) {\n      set_gpio_mode(GPIOC, 10, MODE_ALTERNATE);\n    }\n  }\n}\n\nvoid set_bitbanged_kline(bool marking) {\n  // tickle needs to be super fast (so logic level doesn't change)\n  ENTER_CRITICAL();\n  if (k_init) {\n    register_set_bits(&(GPIOC->ODR), (1U << 12));\n    if (!marking) {\n      register_clear_bits(&(GPIOC->ODR), (1U << 12));\n    }\n  }\n  if (l_init) {\n    register_set_bits(&(GPIOC->ODR), (1U << 10));\n    if (!marking) {\n      register_clear_bits(&(GPIOC->ODR), (1U << 10));\n    }\n  }\n  EXIT_CRITICAL();\n  // blink blue LED each time line is pulled low\n  current_board->set_led(LED_BLUE, marking);\n}\n\nuint16_t kline_data = 0;\nuint16_t kline_data_len = 0;\nuint16_t kline_bit_count = 0;\nuint16_t kline_tick_count = 0;\nuint16_t kline_ticks_per_bit = 0;\n\nvoid TIM5_IRQ_Handler(void) {\n  if ((TIM5->SR & TIM_SR_UIF) && (kline_data != 0U)) {\n    if (kline_bit_count < kline_data_len) {\n      bool marking = (kline_data & (1U << kline_bit_count)) != 0U;\n      set_bitbanged_kline(marking);\n    } else {\n      register_clear_bits(&(TIM5->DIER), TIM_DIER_UIE); // No update interrupt\n      register_set(&(TIM5->CR1), 0U, 0x3FU); // Disable timer\n      setup_kline(false);\n      kline_data = 0U;\n      USB_WritePacket(NULL, 0, 0); // required call (so send nothing)\n      USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n    }\n    kline_tick_count++;\n    if ((kline_tick_count % kline_ticks_per_bit) == 0U) {\n      kline_bit_count++;\n    }\n  }\n  TIM5->SR = 0;\n}\n\nbool bitbang_five_baud_addr(bool k, bool l, uint8_t addr) {\n  bool result = false;\n  if (kline_data == 0U) {\n    k_init = k;\n    l_init = l;\n    kline_data = (addr << 1) + 0x200U; // add start/stop bits\n    kline_data_len = 10U;\n    kline_bit_count = 0;\n    kline_tick_count = 0;\n    kline_ticks_per_bit = 40U; // 200ms == 5bps\n    setup_kline(true);\n    setup_timer5();\n    result = true;\n  }\n  return result;\n}\n\nbool bitbang_wakeup(bool k, bool l) {\n  bool result = false;\n  if (kline_data == 0U) {\n    k_init = k;\n    l_init = l;\n    kline_data = 2U; // low then high\n    kline_data_len = 2U;\n    kline_bit_count = 0;\n    kline_tick_count = 0;\n    kline_ticks_per_bit = 5U; // 25ms == 40bps\n    setup_kline(true);\n    setup_timer5();\n    result = true;\n  }\n  return result;\n}\n"
  },
  {
    "path": "panda/board/drivers/pwm.h",
    "content": "#define PWM_COUNTER_OVERFLOW 2000U // To get ~50kHz\n\n// TODO: Implement for 32-bit timers\n\nvoid pwm_init(TIM_TypeDef *TIM, uint8_t channel){\n    // Enable timer and auto-reload\n    register_set(&(TIM->CR1), TIM_CR1_CEN | TIM_CR1_ARPE, 0x3FU);\n\n    // Set channel as PWM mode 1 and enable output\n    switch(channel){\n        case 1U:\n            register_set_bits(&(TIM->CCMR1), (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE));\n            register_set_bits(&(TIM->CCER), TIM_CCER_CC1E);\n            break;\n        case 2U:\n            register_set_bits(&(TIM->CCMR1), (TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE));\n            register_set_bits(&(TIM->CCER), TIM_CCER_CC2E);\n            break;\n        case 3U:\n            register_set_bits(&(TIM->CCMR2), (TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE));\n            register_set_bits(&(TIM->CCER), TIM_CCER_CC3E);\n            break;\n        case 4U:\n            register_set_bits(&(TIM->CCMR2), (TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE));\n            register_set_bits(&(TIM->CCER), TIM_CCER_CC4E);\n            break;\n        default:\n            break;\n    }\n\n    // Set max counter value\n    register_set(&(TIM->ARR), PWM_COUNTER_OVERFLOW, 0xFFFFU);\n\n    // Update registers and clear counter\n    TIM->EGR |= TIM_EGR_UG;\n}\n\nvoid pwm_set(TIM_TypeDef *TIM, uint8_t channel, uint8_t percentage){\n    uint16_t comp_value = (((uint16_t) percentage * PWM_COUNTER_OVERFLOW) / 100U);\n    switch(channel){\n        case 1U:\n            register_set(&(TIM->CCR1), comp_value, 0xFFFFU);\n            break;\n        case 2U:\n            register_set(&(TIM->CCR2), comp_value, 0xFFFFU);\n            break;\n        case 3U:\n            register_set(&(TIM->CCR3), comp_value, 0xFFFFU);\n            break;\n        case 4U:\n            register_set(&(TIM->CCR4), comp_value, 0xFFFFU);\n            break;\n        default:\n            break;\n    }\n}\n"
  },
  {
    "path": "panda/board/drivers/registers.h",
    "content": "\ntypedef struct reg {\n  volatile uint32_t *address;\n  uint32_t value;\n  uint32_t check_mask;\n} reg;\n\n// 10 bit hash with 23 as a prime\n#define REGISTER_MAP_SIZE 0x3FFU\n#define HASHING_PRIME 23U\n#define CHECK_COLLISION(hash, addr) (((uint32_t) register_map[hash].address != 0U) && (register_map[hash].address != (addr)))\n\nreg register_map[REGISTER_MAP_SIZE];\n\n// Hash spread in first and second iterations seems to be reasonable.\n// See: tests/development/register_hashmap_spread.py\n// Also, check the collision warnings in the debug output, and minimize those.\nuint16_t hash_addr(uint32_t input){\n  return (((input >> 16U) ^ ((((input + 1U) & 0xFFFFU) * HASHING_PRIME) & 0xFFFFU)) & REGISTER_MAP_SIZE);\n}\n\n// Do not put bits in the check mask that get changed by the hardware\nvoid register_set(volatile uint32_t *addr, uint32_t val, uint32_t mask){\n  ENTER_CRITICAL()\n  // Set bits in register that are also in the mask\n  (*addr) = ((*addr) & (~mask)) | (val & mask);\n\n  // Add these values to the map\n  uint16_t hash = hash_addr((uint32_t) addr);\n  uint16_t tries = REGISTER_MAP_SIZE;\n  while(CHECK_COLLISION(hash, addr) && (tries > 0U)) { hash = hash_addr((uint32_t) hash); tries--;}\n  if (tries != 0U){\n    register_map[hash].address = addr;\n    register_map[hash].value = (register_map[hash].value & (~mask)) | (val & mask);\n    register_map[hash].check_mask |= mask;\n  } else {\n    #ifdef DEBUG_FAULTS\n      puts(\"Hash collision: address 0x\"); puth((uint32_t) addr); puts(\"!\\n\");\n    #endif\n  }\n  EXIT_CRITICAL()\n}\n\n// Set individual bits. Also add them to the check_mask.\n// Do not use this to change bits that get reset by the hardware\nvoid register_set_bits(volatile uint32_t *addr, uint32_t val) {\n  return register_set(addr, val, val);\n}\n\n// Clear individual bits. Also add them to the check_mask.\n// Do not use this to clear bits that get set by the hardware\nvoid register_clear_bits(volatile uint32_t *addr, uint32_t val) {\n  return register_set(addr, (~val), val);\n}\n\n// To be called periodically\nvoid check_registers(void){\n  for(uint16_t i=0U; i<REGISTER_MAP_SIZE; i++){\n    if((uint32_t) register_map[i].address != 0U){\n      ENTER_CRITICAL()\n      if((*(register_map[i].address) & register_map[i].check_mask) != (register_map[i].value & register_map[i].check_mask)){\n        #ifdef DEBUG_FAULTS\n          puts(\"Register at address 0x\"); puth((uint32_t) register_map[i].address); puts(\" is divergent!\");\n          puts(\"   Map: 0x\"); puth(register_map[i].value);\n          puts(\"   Register: 0x\"); puth(*(register_map[i].address));\n          puts(\"   Mask: 0x\"); puth(register_map[i].check_mask);\n          puts(\"\\n\");\n        #endif\n        fault_occurred(FAULT_REGISTER_DIVERGENT);\n      }\n      EXIT_CRITICAL()\n    }\n  }\n}\n\nvoid init_registers(void) {\n  for(uint16_t i=0U; i<REGISTER_MAP_SIZE; i++){\n    register_map[i].address = (volatile uint32_t *) 0U;\n    register_map[i].check_mask = 0U;\n  }\n}\n"
  },
  {
    "path": "panda/board/drivers/rtc.h",
    "content": "#define RCC_BDCR_OPTIONS (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL_0 | RCC_BDCR_LSEON)\n\n#define YEAR_OFFSET 2000U\n\ntypedef struct __attribute__((packed)) timestamp_t {\n  uint16_t year;\n  uint8_t month;\n  uint8_t day;\n  uint8_t weekday;\n  uint8_t hour;\n  uint8_t minute;\n  uint8_t second;\n} timestamp_t;\n\nuint8_t to_bcd(uint16_t value){\n  return (((value / 10U) & 0x0FU) << 4U) | ((value % 10U) & 0x0FU);\n}\n\nuint16_t from_bcd(uint8_t value){\n  return (((value & 0xF0U) >> 4U) * 10U) + (value & 0x0FU);\n}\n\nvoid rtc_init(void){\n  if(current_board->has_rtc){\n    // Initialize RTC module and clock if not done already.\n    if((RCC->BDCR & RCC_BDCR_MASK) != RCC_BDCR_OPTIONS){\n      puts(\"Initializing RTC\\n\");\n      // Reset backup domain\n      register_set_bits(&(RCC->BDCR), RCC_BDCR_BDRST);\n\n      // Disable write protection\n      disable_bdomain_protection();\n\n      // Clear backup domain reset\n      register_clear_bits(&(RCC->BDCR), RCC_BDCR_BDRST);\n\n      // Set RTC options\n      register_set(&(RCC->BDCR), RCC_BDCR_OPTIONS, RCC_BDCR_MASK);\n\n      // Enable write protection\n      enable_bdomain_protection();\n    }\n  }\n}\n\nvoid rtc_set_time(timestamp_t time){\n  if(current_board->has_rtc){\n    puts(\"Setting RTC time\\n\");\n\n    // Disable write protection\n    disable_bdomain_protection();\n    RTC->WPR = 0xCA;\n    RTC->WPR = 0x53;\n\n    // Enable initialization mode\n    register_set_bits(&(RTC->ISR), RTC_ISR_INIT);\n    while((RTC->ISR & RTC_ISR_INITF) == 0){}\n\n    // Set time\n    RTC->TR = (to_bcd(time.hour) << RTC_TR_HU_Pos) | (to_bcd(time.minute) << RTC_TR_MNU_Pos) | (to_bcd(time.second) << RTC_TR_SU_Pos);\n    RTC->DR = (to_bcd(time.year - YEAR_OFFSET) << RTC_DR_YU_Pos) | (time.weekday << RTC_DR_WDU_Pos) | (to_bcd(time.month) << RTC_DR_MU_Pos) | (to_bcd(time.day) << RTC_DR_DU_Pos);\n\n    // Set options\n    register_set(&(RTC->CR), 0U, 0xFCFFFFU);\n\n    // Disable initalization mode\n    register_clear_bits(&(RTC->ISR), RTC_ISR_INIT);\n\n    // Wait for synchronization\n    while((RTC->ISR & RTC_ISR_RSF) == 0){}\n\n    // Re-enable write protection\n    RTC->WPR = 0x00;\n    enable_bdomain_protection();\n  }\n}\n\ntimestamp_t rtc_get_time(void){\n  timestamp_t result;\n  // Init with zero values in case there is no RTC running\n  result.year = 0U;\n  result.month = 0U;\n  result.day = 0U;\n  result.weekday = 0U;\n  result.hour = 0U;\n  result.minute = 0U;\n  result.second = 0U;\n\n  if(current_board->has_rtc){\n    // Wait until the register sync flag is set\n    while((RTC->ISR & RTC_ISR_RSF) == 0){}\n\n    // Read time and date registers. Since our HSE > 7*LSE, this should be fine.\n    uint32_t time = RTC->TR;\n    uint32_t date = RTC->DR;\n\n    // Parse values\n    result.year = from_bcd((date & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos) + YEAR_OFFSET;\n    result.month = from_bcd((date & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);\n    result.day = from_bcd((date & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);\n    result.weekday = ((date & RTC_DR_WDU) >> RTC_DR_WDU_Pos);\n    result.hour = from_bcd((time & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);\n    result.minute = from_bcd((time & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);\n    result.second = from_bcd((time & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);\n  }\n  return result;\n}\n"
  },
  {
    "path": "panda/board/drivers/timers.h",
    "content": "void timer_init(TIM_TypeDef *TIM, int psc) {\n  register_set(&(TIM->PSC), (psc-1), 0xFFFFU);\n  register_set(&(TIM->DIER), TIM_DIER_UIE, 0x5F5FU);\n  register_set(&(TIM->CR1), TIM_CR1_CEN, 0x3FU);\n  TIM->SR = 0;\n}\n\nvoid microsecond_timer_init(void) {\n  MICROSECOND_TIMER->PSC = (APB1_FREQ)-1U;\n  MICROSECOND_TIMER->CR1 = TIM_CR1_CEN;\n  MICROSECOND_TIMER->EGR = TIM_EGR_UG;\n}\n\nuint32_t microsecond_timer_get(void) {\n  return MICROSECOND_TIMER->CNT;\n}\n\nvoid interrupt_timer_init(void) {\n  enable_interrupt_timer();\n  REGISTER_INTERRUPT(INTERRUPT_TIMER_IRQ, interrupt_timer_handler, 1, FAULT_INTERRUPT_RATE_INTERRUPTS)\n  register_set(&(INTERRUPT_TIMER->PSC), ((uint16_t)(15.25*APB1_FREQ)-1U), 0xFFFFU);\n  register_set(&(INTERRUPT_TIMER->DIER), TIM_DIER_UIE, 0x5F5FU);\n  register_set(&(INTERRUPT_TIMER->CR1), TIM_CR1_CEN, 0x3FU);\n  INTERRUPT_TIMER->SR = 0;\n  NVIC_EnableIRQ(INTERRUPT_TIMER_IRQ);\n}\n\nvoid tick_timer_init(void) {\n  timer_init(TICK_TIMER, (uint16_t)((15.25*APB2_FREQ)/8U));\n  NVIC_EnableIRQ(TICK_TIMER_IRQ);\n}\n"
  },
  {
    "path": "panda/board/drivers/uart.h",
    "content": "// IRQs: USART1, USART2, USART3, UART5\n\n// ***************************** Definitions *****************************\n#define FIFO_SIZE_INT 0x400U\n#define FIFO_SIZE_DMA 0x1000U\n\ntypedef struct uart_ring {\n  volatile uint16_t w_ptr_tx;\n  volatile uint16_t r_ptr_tx;\n  uint8_t *elems_tx;\n  uint32_t tx_fifo_size;\n  volatile uint16_t w_ptr_rx;\n  volatile uint16_t r_ptr_rx;\n  uint8_t *elems_rx;\n  uint32_t rx_fifo_size;\n  USART_TypeDef *uart;\n  void (*callback)(struct uart_ring*);\n  bool dma_rx;\n} uart_ring;\n\n#define UART_BUFFER(x, size_rx, size_tx, uart_ptr, callback_ptr, rx_dma) \\\n  uint8_t elems_rx_##x[size_rx]; \\\n  uint8_t elems_tx_##x[size_tx]; \\\n  uart_ring uart_ring_##x = {  \\\n    .w_ptr_tx = 0, \\\n    .r_ptr_tx = 0, \\\n    .elems_tx = ((uint8_t *)&(elems_tx_##x)), \\\n    .tx_fifo_size = (size_tx), \\\n    .w_ptr_rx = 0, \\\n    .r_ptr_rx = 0, \\\n    .elems_rx = ((uint8_t *)&(elems_rx_##x)), \\\n    .rx_fifo_size = (size_rx), \\\n    .uart = (uart_ptr), \\\n    .callback = (callback_ptr), \\\n    .dma_rx = (rx_dma) \\\n  };\n\n// ***************************** Function prototypes *****************************\nvoid debug_ring_callback(uart_ring *ring);\nvoid uart_tx_ring(uart_ring *q);\nvoid uart_send_break(uart_ring *u);\n\n// ******************************** UART buffers ********************************\n\n// gps = USART1\nUART_BUFFER(gps, FIFO_SIZE_DMA, FIFO_SIZE_INT, USART1, NULL, true)\n\n// lin1, K-LINE = UART5\n// lin2, L-LINE = USART3\nUART_BUFFER(lin1, FIFO_SIZE_INT, FIFO_SIZE_INT, UART5, NULL, false)\nUART_BUFFER(lin2, FIFO_SIZE_INT, FIFO_SIZE_INT, USART3, NULL, false)\n\n// debug = USART2\nUART_BUFFER(debug, FIFO_SIZE_INT, FIFO_SIZE_INT, USART2, debug_ring_callback, false)\n\nuart_ring *get_ring_by_number(int a) {\n  uart_ring *ring = NULL;\n  switch(a) {\n    case 0:\n      ring = &uart_ring_debug;\n      break;\n    case 1:\n      ring = &uart_ring_gps;\n      break;\n    case 2:\n      ring = &uart_ring_lin1;\n      break;\n    case 3:\n      ring = &uart_ring_lin2;\n      break;\n    default:\n      ring = NULL;\n      break;\n  }\n  return ring;\n}\n\n// ************************* Low-level buffer functions *************************\nbool getc(uart_ring *q, char *elem) {\n  bool ret = false;\n\n  ENTER_CRITICAL();\n  if (q->w_ptr_rx != q->r_ptr_rx) {\n    if (elem != NULL) *elem = q->elems_rx[q->r_ptr_rx];\n    q->r_ptr_rx = (q->r_ptr_rx + 1U) % q->rx_fifo_size;\n    ret = true;\n  }\n  EXIT_CRITICAL();\n\n  return ret;\n}\n\nbool injectc(uart_ring *q, char elem) {\n  int ret = false;\n  uint16_t next_w_ptr;\n\n  ENTER_CRITICAL();\n  next_w_ptr = (q->w_ptr_rx + 1U) % q->tx_fifo_size;\n  if (next_w_ptr != q->r_ptr_rx) {\n    q->elems_rx[q->w_ptr_rx] = elem;\n    q->w_ptr_rx = next_w_ptr;\n    ret = true;\n  }\n  EXIT_CRITICAL();\n\n  return ret;\n}\n\nbool putc(uart_ring *q, char elem) {\n  bool ret = false;\n  uint16_t next_w_ptr;\n\n  ENTER_CRITICAL();\n  next_w_ptr = (q->w_ptr_tx + 1U) % q->tx_fifo_size;\n  if (next_w_ptr != q->r_ptr_tx) {\n    q->elems_tx[q->w_ptr_tx] = elem;\n    q->w_ptr_tx = next_w_ptr;\n    ret = true;\n  }\n  EXIT_CRITICAL();\n\n  uart_tx_ring(q);\n\n  return ret;\n}\n\n// Seems dangerous to use (might lock CPU if called with interrupts disabled f.e.)\n// TODO: Remove? Not used anyways\nvoid uart_flush(uart_ring *q) {\n  while (q->w_ptr_tx != q->r_ptr_tx) {\n    __WFI();\n  }\n}\n\nvoid uart_flush_sync(uart_ring *q) {\n  // empty the TX buffer\n  while (q->w_ptr_tx != q->r_ptr_tx) {\n    uart_tx_ring(q);\n  }\n}\n\nvoid clear_uart_buff(uart_ring *q) {\n  ENTER_CRITICAL();\n  q->w_ptr_tx = 0;\n  q->r_ptr_tx = 0;\n  q->w_ptr_rx = 0;\n  q->r_ptr_rx = 0;\n  EXIT_CRITICAL();\n}\n\n// ************************ High-level debug functions **********************\nvoid putch(const char a) {\n  if (has_external_debug_serial) {\n    // assuming debugging is important if there's external serial connected\n    while (!putc(&uart_ring_debug, a));\n\n  } else {\n    // misra-c2012-17.7: serial debug function, ok to ignore output\n    (void)injectc(&uart_ring_debug, a);\n  }\n}\n\nvoid puts(const char *a) {\n  for (const char *in = a; *in; in++) {\n    if (*in == '\\n') putch('\\r');\n    putch(*in);\n  }\n}\n\nvoid putui(uint32_t i) {\n  uint32_t i_copy = i;\n  char str[11];\n  uint8_t idx = 10;\n  str[idx] = '\\0';\n  idx--;\n  do {\n    str[idx] = (i_copy % 10U) + 0x30U;\n    idx--;\n    i_copy /= 10;\n  } while (i_copy != 0U);\n  puts(&str[idx + 1U]);\n}\n\nvoid puth(unsigned int i) {\n  const char c[] = \"0123456789abcdef\";\n  for (int pos = 28; pos != -4; pos -= 4) {\n    putch(c[(i >> (unsigned int)(pos)) & 0xFU]);\n  }\n}\n\nvoid puth2(unsigned int i) {\n  const char c[] = \"0123456789abcdef\";\n  for (int pos = 4; pos != -4; pos -= 4) {\n    putch(c[(i >> (unsigned int)(pos)) & 0xFU]);\n  }\n}\n\nvoid hexdump(const void *a, int l) {\n  if (a != NULL) {\n    for (int i=0; i < l; i++) {\n      if ((i != 0) && ((i & 0xf) == 0)) puts(\"\\n\");\n      puth2(((const unsigned char*)a)[i]);\n      puts(\" \");\n    }\n  }\n  puts(\"\\n\");\n}\n"
  },
  {
    "path": "panda/board/drivers/usb.h",
    "content": "// IRQs: OTG_FS\n\ntypedef union {\n  uint16_t w;\n  struct BW {\n    uint8_t msb;\n    uint8_t lsb;\n  }\n  bw;\n}\nuint16_t_uint8_t;\n\ntypedef union _USB_Setup {\n  uint32_t d8[2];\n  struct _SetupPkt_Struc\n  {\n    uint8_t           bmRequestType;\n    uint8_t           bRequest;\n    uint16_t_uint8_t  wValue;\n    uint16_t_uint8_t  wIndex;\n    uint16_t_uint8_t  wLength;\n  } b;\n}\nUSB_Setup_TypeDef;\n\n#define MAX_CAN_MSGS_PER_BULK_TRANSFER 4U\n\nbool usb_eopf_detected = false;\n\nvoid usb_init(void);\nint usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired);\nint usb_cb_ep1_in(void *usbdata, int len, bool hardwired);\nvoid usb_cb_ep2_out(void *usbdata, int len, bool hardwired);\nvoid usb_cb_ep3_out(void *usbdata, int len, bool hardwired);\nvoid usb_cb_ep3_out_complete(void);\nvoid usb_cb_enumeration_complete(void);\nvoid usb_outep3_resume_if_paused(void);\n\n// **** supporting defines ****\n\n#define  USB_REQ_GET_STATUS                             0x00\n#define  USB_REQ_CLEAR_FEATURE                          0x01\n#define  USB_REQ_SET_FEATURE                            0x03\n#define  USB_REQ_SET_ADDRESS                            0x05\n#define  USB_REQ_GET_DESCRIPTOR                         0x06\n#define  USB_REQ_SET_DESCRIPTOR                         0x07\n#define  USB_REQ_GET_CONFIGURATION                      0x08\n#define  USB_REQ_SET_CONFIGURATION                      0x09\n#define  USB_REQ_GET_INTERFACE                          0x0A\n#define  USB_REQ_SET_INTERFACE                          0x0B\n#define  USB_REQ_SYNCH_FRAME                            0x0C\n\n#define  USB_DESC_TYPE_DEVICE                           0x01\n#define  USB_DESC_TYPE_CONFIGURATION                    0x02\n#define  USB_DESC_TYPE_STRING                           0x03\n#define  USB_DESC_TYPE_INTERFACE                        0x04\n#define  USB_DESC_TYPE_ENDPOINT                         0x05\n#define  USB_DESC_TYPE_DEVICE_QUALIFIER                 0x06\n#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION        0x07\n#define  USB_DESC_TYPE_BINARY_OBJECT_STORE              0x0f\n\n// offsets for configuration strings\n#define  STRING_OFFSET_LANGID                           0x00\n#define  STRING_OFFSET_IMANUFACTURER                    0x01\n#define  STRING_OFFSET_IPRODUCT                         0x02\n#define  STRING_OFFSET_ISERIAL                          0x03\n#define  STRING_OFFSET_ICONFIGURATION                   0x04\n#define  STRING_OFFSET_IINTERFACE                       0x05\n\n// WebUSB requests\n#define  WEBUSB_REQ_GET_URL                             0x02\n\n// WebUSB types\n#define  WEBUSB_DESC_TYPE_URL                           0x03\n#define  WEBUSB_URL_SCHEME_HTTPS                        0x01\n#define  WEBUSB_URL_SCHEME_HTTP                         0x00\n\n// WinUSB requests\n#define  WINUSB_REQ_GET_COMPATID_DESCRIPTOR             0x04\n#define  WINUSB_REQ_GET_EXT_PROPS_OS                    0x05\n#define  WINUSB_REQ_GET_DESCRIPTOR                      0x07\n\n#define STS_GOUT_NAK                           1\n#define STS_DATA_UPDT                          2\n#define STS_XFER_COMP                          3\n#define STS_SETUP_COMP                         4\n#define STS_SETUP_UPDT                         6\n\nuint8_t resp[MAX_RESP_LEN];\n\n// for the repeating interfaces\n#define DSCR_INTERFACE_LEN 9\n#define DSCR_ENDPOINT_LEN 7\n#define DSCR_CONFIG_LEN 9\n#define DSCR_DEVICE_LEN 18\n\n// endpoint types\n#define ENDPOINT_TYPE_CONTROL 0\n#define ENDPOINT_TYPE_ISO 1\n#define ENDPOINT_TYPE_BULK 2\n#define ENDPOINT_TYPE_INT 3\n\n// These are arbitrary values used in bRequest\n#define  MS_VENDOR_CODE 0x20\n#define  WEBUSB_VENDOR_CODE 0x30\n\n// BOS constants\n#define BINARY_OBJECT_STORE_DESCRIPTOR_LENGTH   0x05\n#define BINARY_OBJECT_STORE_DESCRIPTOR          0x0F\n#define WINUSB_PLATFORM_DESCRIPTOR_LENGTH       0x9E\n\n// Convert machine byte order to USB byte order\n#define TOUSBORDER(num)\\\n  ((num) & 0xFFU), (((num) >> 8) & 0xFFU)\n\n// take in string length and return the first 2 bytes of a string descriptor\n#define STRING_DESCRIPTOR_HEADER(size)\\\n  (((((size) * 2) + 2) & 0xFF) | 0x0300)\n\nuint8_t device_desc[] = {\n  DSCR_DEVICE_LEN, USB_DESC_TYPE_DEVICE, //Length, Type\n  0x10, 0x02, // bcdUSB max version of USB supported (2.1)\n  0xFF, 0xFF, 0xFF, 0x40, // Class, Subclass, Protocol, Max Packet Size\n  TOUSBORDER(USB_VID), // idVendor\n  TOUSBORDER(USB_PID), // idProduct\n  0x00, 0x00, // bcdDevice\n  0x01, 0x02, // Manufacturer, Product\n  0x03, 0x01 // Serial Number, Num Configurations\n};\n\nuint8_t device_qualifier[] = {\n  0x0a, USB_DESC_TYPE_DEVICE_QUALIFIER, //Length, Type\n  0x10, 0x02, // bcdUSB max version of USB supported (2.1)\n  0xFF, 0xFF, 0xFF, 0x40, // bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0\n  0x01, 0x00 // bNumConfigurations, bReserved\n};\n\n#define ENDPOINT_RCV 0x80\n#define ENDPOINT_SND 0x00\n\nuint8_t configuration_desc[] = {\n  DSCR_CONFIG_LEN, USB_DESC_TYPE_CONFIGURATION, // Length, Type,\n  TOUSBORDER(0x0045U), // Total Len (uint16)\n  0x01, 0x01, STRING_OFFSET_ICONFIGURATION, // Num Interface, Config Value, Configuration\n  0xc0, 0x32, // Attributes, Max Power\n  // interface 0 ALT 0\n  DSCR_INTERFACE_LEN, USB_DESC_TYPE_INTERFACE, // Length, Type\n  0x00, 0x00, 0x03, // Index, Alt Index idx, Endpoint count\n  0XFF, 0xFF, 0xFF, // Class, Subclass, Protocol\n  0x00, // Interface\n    // endpoint 1, read CAN\n    DSCR_ENDPOINT_LEN, USB_DESC_TYPE_ENDPOINT, // Length, Type\n    ENDPOINT_RCV | 1, ENDPOINT_TYPE_BULK, // Endpoint Num/Direction, Type\n    TOUSBORDER(0x0040U), // Max Packet (0x0040)\n    0x00, // Polling Interval (NA)\n    // endpoint 2, send serial\n    DSCR_ENDPOINT_LEN, USB_DESC_TYPE_ENDPOINT, // Length, Type\n    ENDPOINT_SND | 2, ENDPOINT_TYPE_BULK, // Endpoint Num/Direction, Type\n    TOUSBORDER(0x0040U), // Max Packet (0x0040)\n    0x00, // Polling Interval\n    // endpoint 3, send CAN\n    DSCR_ENDPOINT_LEN, USB_DESC_TYPE_ENDPOINT, // Length, Type\n    ENDPOINT_SND | 3, ENDPOINT_TYPE_BULK, // Endpoint Num/Direction, Type\n    TOUSBORDER(0x0040U), // Max Packet (0x0040)\n    0x00, // Polling Interval\n  // interface 0 ALT 1\n  DSCR_INTERFACE_LEN, USB_DESC_TYPE_INTERFACE, // Length, Type\n  0x00, 0x01, 0x03, // Index, Alt Index idx, Endpoint count\n  0XFF, 0xFF, 0xFF, // Class, Subclass, Protocol\n  0x00, // Interface\n    // endpoint 1, read CAN\n    DSCR_ENDPOINT_LEN, USB_DESC_TYPE_ENDPOINT, // Length, Type\n    ENDPOINT_RCV | 1, ENDPOINT_TYPE_INT, // Endpoint Num/Direction, Type\n    TOUSBORDER(0x0040U), // Max Packet (0x0040)\n    0x05, // Polling Interval (5 frames)\n    // endpoint 2, send serial\n    DSCR_ENDPOINT_LEN, USB_DESC_TYPE_ENDPOINT, // Length, Type\n    ENDPOINT_SND | 2, ENDPOINT_TYPE_BULK, // Endpoint Num/Direction, Type\n    TOUSBORDER(0x0040U), // Max Packet (0x0040)\n    0x00, // Polling Interval\n    // endpoint 3, send CAN\n    DSCR_ENDPOINT_LEN, USB_DESC_TYPE_ENDPOINT, // Length, Type\n    ENDPOINT_SND | 3, ENDPOINT_TYPE_BULK, // Endpoint Num/Direction, Type\n    TOUSBORDER(0x0040U), // Max Packet (0x0040)\n    0x00, // Polling Interval\n};\n\n// STRING_DESCRIPTOR_HEADER is for uint16 string descriptors\n// it takes in a string length, which is bytes/2 because unicode\nuint16_t string_language_desc[] = {\n  STRING_DESCRIPTOR_HEADER(1),\n  0x0409 // american english\n};\n\n// these strings are all uint16's so that we don't need to spam ,0 after every character\nuint16_t string_manufacturer_desc[] = {\n  STRING_DESCRIPTOR_HEADER(8),\n  'c', 'o', 'm', 'm', 'a', '.', 'a', 'i'\n};\n\nuint16_t string_product_desc[] = {\n  STRING_DESCRIPTOR_HEADER(5),\n  'p', 'a', 'n', 'd', 'a'\n};\n\n// default serial number when we're not a panda\nuint16_t string_serial_desc[] = {\n  STRING_DESCRIPTOR_HEADER(4),\n  'n', 'o', 'n', 'e'\n};\n\n// a string containing the default configuration index\nuint16_t string_configuration_desc[] = {\n  STRING_DESCRIPTOR_HEADER(2),\n  '0', '1' // \"01\"\n};\n\n// WCID (auto install WinUSB driver)\n// https://github.com/pbatard/libwdi/wiki/WCID-Devices\n// https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/winusb-installation#automatic-installation-of--winusb-without-an-inf-file\n// WinUSB 1.0 descriptors, this is mostly used by Windows XP\nuint8_t string_238_desc[] = {\n  0x12, USB_DESC_TYPE_STRING, // bLength, bDescriptorType\n  'M',0, 'S',0, 'F',0, 'T',0, '1',0, '0',0, '0',0, // qwSignature (MSFT100)\n  MS_VENDOR_CODE, 0x00 // bMS_VendorCode, bPad\n};\nuint8_t winusb_ext_compatid_os_desc[] = {\n  0x28, 0x00, 0x00, 0x00, // dwLength\n  0x00, 0x01, // bcdVersion\n  0x04, 0x00, // wIndex\n  0x01, // bCount\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved\n  0x00, // bFirstInterfaceNumber\n  0x00, // Reserved\n  'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, // compatible ID (WINUSB)\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // subcompatible ID (none)\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // Reserved\n};\nuint8_t winusb_ext_prop_os_desc[] = {\n  0x8e, 0x00, 0x00, 0x00, // dwLength\n  0x00, 0x01, // bcdVersion\n  0x05, 0x00, // wIndex\n  0x01, 0x00, // wCount\n  // first property\n  0x84, 0x00, 0x00, 0x00, // dwSize\n  0x01, 0x00, 0x00, 0x00, // dwPropertyDataType\n  0x28, 0x00, // wPropertyNameLength\n  'D',0, 'e',0, 'v',0, 'i',0, 'c',0, 'e',0, 'I',0, 'n',0, 't',0, 'e',0, 'r',0, 'f',0, 'a',0, 'c',0, 'e',0, 'G',0, 'U',0, 'I',0, 'D',0, 0, 0, // bPropertyName (DeviceInterfaceGUID)\n  0x4e, 0x00, 0x00, 0x00, // dwPropertyDataLength\n  '{',0, 'c',0, 'c',0, 'e',0, '5',0, '2',0, '9',0, '1',0, 'c',0, '-',0, 'a',0, '6',0, '9',0, 'f',0, '-',0, '4',0 ,'9',0 ,'9',0 ,'5',0 ,'-',0, 'a',0, '4',0, 'c',0, '2',0, '-',0, '2',0, 'a',0, 'e',0, '5',0, '7',0, 'a',0, '5',0, '1',0, 'a',0, 'd',0, 'e',0, '9',0, '}',0, 0, 0, // bPropertyData ({CCE5291C-A69F-4995-A4C2-2AE57A51ADE9})\n};\n\n/*\nBinary Object Store descriptor used to expose WebUSB (and more WinUSB) metadata\ncomments are from the wicg spec\nReferences used:\n  https://wicg.github.io/webusb/#webusb-platform-capability-descriptor\n  https://github.com/sowbug/weblight/blob/192ad7a0e903542e2aa28c607d98254a12a6399d/firmware/webusb.c\n  https://os.mbed.com/users/larsgk/code/USBDevice_WebUSB/file/1d8a6665d607/WebUSBDevice/\n\n*/\nuint8_t binary_object_store_desc[] = {\n  // BOS header\n  BINARY_OBJECT_STORE_DESCRIPTOR_LENGTH, // bLength, this is only the length of the header\n  BINARY_OBJECT_STORE_DESCRIPTOR, // bDescriptorType\n  0x39, 0x00, // wTotalLength (LSB, MSB)\n  0x02, // bNumDeviceCaps (WebUSB + WinUSB)\n\n  // -------------------------------------------------\n  // WebUSB descriptor\n  // header\n    0x18, // bLength, Size of this descriptor. Must be set to 24.\n    0x10, // bDescriptorType, DEVICE CAPABILITY descriptor\n    0x05, // bDevCapabilityType, PLATFORM capability\n    0x00, // bReserved, This field is reserved and shall be set to zero.\n\n  // PlatformCapabilityUUID, Must be set to {3408b638-09a9-47a0-8bfd-a0768815b665}.\n    0x38, 0xB6, 0x08, 0x34,\n    0xA9, 0x09, 0xA0, 0x47,\n    0x8B, 0xFD, 0xA0, 0x76,\n    0x88, 0x15, 0xB6, 0x65,\n  // </PlatformCapabilityUUID>\n\n  0x00, 0x01, // bcdVersion, Protocol version supported. Must be set to 0x0100.\n  WEBUSB_VENDOR_CODE, // bVendorCode, bRequest value used for issuing WebUSB requests.\n  // there used to be a concept of \"allowed origins\", but it was removed from the spec\n  // it was intended to be a security feature, but then the entire security model relies on domain ownership\n  // https://github.com/WICG/webusb/issues/49\n  // other implementations use various other indexed to leverate this no-longer-valid feature. we wont.\n  // the spec says we *must* reply to index 0x03 with the url, so we'll hint that that's the right index\n  0x03, // iLandingPage, URL descriptor index of the device’s landing page.\n\n  // -------------------------------------------------\n  // WinUSB descriptor\n  // header\n    0x1C, // Descriptor size (28 bytes)\n    0x10, // Descriptor type (Device Capability)\n    0x05, // Capability type (Platform)\n    0x00, // Reserved\n\n  // MS OS 2.0 Platform Capability ID (D8DD60DF-4589-4CC7-9CD2-659D9E648A9F)\n  // Indicates the device supports the Microsoft OS 2.0 descriptor\n    0xDF, 0x60, 0xDD, 0xD8,\n    0x89, 0x45, 0xC7, 0x4C,\n    0x9C, 0xD2, 0x65, 0x9D,\n    0x9E, 0x64, 0x8A, 0x9F,\n\n  0x00, 0x00, 0x03, 0x06, // Windows version, currently set to 8.1 (0x06030000)\n\n  WINUSB_PLATFORM_DESCRIPTOR_LENGTH, 0x00, // MS OS 2.0 descriptor size (word)\n  MS_VENDOR_CODE, 0x00 // vendor code, no alternate enumeration\n};\n\nuint8_t webusb_url_descriptor[] = {\n  0x14,                  /* bLength */\n  WEBUSB_DESC_TYPE_URL, // bDescriptorType\n  WEBUSB_URL_SCHEME_HTTPS, // bScheme\n  'u', 's', 'b', 'p', 'a', 'n', 'd', 'a', '.', 'c', 'o', 'm', 'm', 'a', '.', 'a', 'i'\n};\n\n// WinUSB 2.0 descriptor. This is what modern systems use\n// https://github.com/sowbug/weblight/blob/192ad7a0e903542e2aa28c607d98254a12a6399d/firmware/webusb.c\n// http://janaxelson.com/files/ms_os_20_descriptors.c\n// https://books.google.com/books?id=pkefBgAAQBAJ&pg=PA353&lpg=PA353\nuint8_t winusb_20_desc[WINUSB_PLATFORM_DESCRIPTOR_LENGTH] = {\n  // Microsoft OS 2.0 descriptor set header (table 10)\n  0x0A, 0x00, // Descriptor size (10 bytes)\n  0x00, 0x00, // MS OS 2.0 descriptor set header\n\n  0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000)\n  WINUSB_PLATFORM_DESCRIPTOR_LENGTH, 0x00, // Total size of MS OS 2.0 descriptor set\n\n  // Microsoft OS 2.0 compatible ID descriptor\n    0x14, 0x00, // Descriptor size (20 bytes)\n    0x03, 0x00, // MS OS 2.0 compatible ID descriptor\n    'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, // compatible ID (WINUSB)\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,     // Sub-compatible ID\n\n  // Registry property descriptor\n  0x80, 0x00, // Descriptor size (130 bytes)\n  0x04, 0x00, // Registry Property descriptor\n  0x01, 0x00, // Strings are null-terminated Unicode\n  0x28, 0x00, // Size of Property Name (40 bytes) \"DeviceInterfaceGUID\"\n\n  // bPropertyName (DeviceInterfaceGUID)\n    'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00,\n    't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00,\n    'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00,\n\n  0x4E, 0x00, // Size of Property Data (78 bytes)\n\n  // Vendor-defined property data: {CCE5291C-A69F-4995-A4C2-2AE57A51ADE9}\n    '{', 0x00, 'c', 0x00, 'c', 0x00, 'e', 0x00, '5', 0x00, '2', 0x00, '9', 0x00, '1', 0x00, // 16\n    'c', 0x00, '-', 0x00, 'a', 0x00, '6', 0x00, '9', 0x00, 'f', 0x00, '-', 0x00, '4', 0x00, // 32\n    '9', 0x00, '9', 0x00, '5', 0x00, '-', 0x00, 'a', 0x00, '4', 0x00, 'c', 0x00, '2', 0x00, // 48\n    '-', 0x00, '2', 0x00, 'a', 0x00, 'e', 0x00, '5', 0x00, '7', 0x00, 'a', 0x00, '5', 0x00, // 64\n    '1', 0x00, 'a', 0x00, 'd', 0x00, 'e', 0x00, '9', 0x00, '}', 0x00, 0x00, 0x00 // 78 bytes\n};\n\n// current packet\nUSB_Setup_TypeDef setup;\nuint8_t usbdata[0x100];\nuint8_t* ep0_txdata = NULL;\nuint16_t ep0_txlen = 0;\nbool outep3_processing = false;\n\n// Store the current interface alt setting.\nint current_int0_alt_setting = 0;\n\n// packet read and write\n\nvoid *USB_ReadPacket(void *dest, uint16_t len) {\n  uint32_t *dest_copy = (uint32_t *)dest;\n  uint32_t count32b = (len + 3U) / 4U;\n\n  for (uint32_t i = 0; i < count32b; i++) {\n    *dest_copy = USBx_DFIFO(0);\n    dest_copy++;\n  }\n  return ((void *)dest_copy);\n}\n\nvoid USB_WritePacket(const void *src, uint16_t len, uint32_t ep) {\n  #ifdef DEBUG_USB\n  puts(\"writing \");\n  hexdump(src, len);\n  #endif\n\n  uint32_t numpacket = (len + (MAX_RESP_LEN - 1U)) / MAX_RESP_LEN;\n  uint32_t count32b = 0;\n  count32b = (len + 3U) / 4U;\n\n  // TODO: revisit this\n  USBx_INEP(ep)->DIEPTSIZ = ((numpacket << 19) & USB_OTG_DIEPTSIZ_PKTCNT) |\n                            (len               & USB_OTG_DIEPTSIZ_XFRSIZ);\n  USBx_INEP(ep)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\n\n  // load the FIFO\n  if (src != NULL) {\n    const uint32_t *src_copy = (const uint32_t *)src;\n    for (uint32_t i = 0; i < count32b; i++) {\n      USBx_DFIFO(ep) = *src_copy;\n      src_copy++;\n    }\n  }\n}\n\n// IN EP 0 TX FIFO has a max size of 127 bytes (much smaller than the rest)\n// so use TX FIFO empty interrupt to send larger amounts of data\nvoid USB_WritePacket_EP0(uint8_t *src, uint16_t len) {\n  #ifdef DEBUG_USB\n  puts(\"writing \");\n  hexdump(src, len);\n  #endif\n\n  uint16_t wplen = MIN(len, 0x40);\n  USB_WritePacket(src, wplen, 0);\n\n  if (wplen < len) {\n    ep0_txdata = &src[wplen];\n    ep0_txlen = len - wplen;\n    USBx_DEVICE->DIEPEMPMSK |= 1;\n  } else {\n    USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n  }\n}\n\nvoid usb_reset(void) {\n  // unmask endpoint interrupts, so many sets\n  USBx_DEVICE->DAINT = 0xFFFFFFFF;\n  USBx_DEVICE->DAINTMSK = 0xFFFFFFFF;\n  //USBx_DEVICE->DOEPMSK = (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);\n  //USBx_DEVICE->DIEPMSK = (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM | USB_OTG_DIEPMSK_ITTXFEMSK);\n  //USBx_DEVICE->DIEPMSK = (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);\n\n  // all interrupts for debugging\n  USBx_DEVICE->DIEPMSK = 0xFFFFFFFF;\n  USBx_DEVICE->DOEPMSK = 0xFFFFFFFF;\n\n  // clear interrupts\n  USBx_INEP(0)->DIEPINT = 0xFF;\n  USBx_OUTEP(0)->DOEPINT = 0xFF;\n\n  // unset the address\n  USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\n\n  // set up USB FIFOs\n  // RX start address is fixed to 0\n  USBx->GRXFSIZ = 0x40;\n\n  // 0x100 to offset past GRXFSIZ\n  USBx->DIEPTXF0_HNPTXFSIZ = (0x40U << 16) | 0x40U;\n\n  // EP1, massive\n  USBx->DIEPTXF[0] = (0x40U << 16) | 0x80U;\n\n  // flush TX fifo\n  USBx->GRSTCTL = USB_OTG_GRSTCTL_TXFFLSH | USB_OTG_GRSTCTL_TXFNUM_4;\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\n  // flush RX FIFO\n  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\n\n  // no global NAK\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\n\n  // ready to receive setup packets\n  USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)) | (3U << 3);\n}\n\nchar to_hex_char(int a) {\n  char ret;\n  if (a < 10) {\n    ret = '0' + a;\n  } else {\n    ret = 'a' + (a - 10);\n  }\n  return ret;\n}\n\nvoid usb_setup(void) {\n  int resp_len;\n  // setup packet is ready\n  switch (setup.b.bRequest) {\n    case USB_REQ_SET_CONFIGURATION:\n      // enable other endpoints, has to be here?\n      USBx_INEP(1)->DIEPCTL = (0x40U & USB_OTG_DIEPCTL_MPSIZ) | (2U << 18) | (1U << 22) |\n                              USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_USBAEP;\n      USBx_INEP(1)->DIEPINT = 0xFF;\n\n      USBx_OUTEP(2)->DOEPTSIZ = (1U << 19) | 0x40U;\n      USBx_OUTEP(2)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2U << 18) |\n                               USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP;\n      USBx_OUTEP(2)->DOEPINT = 0xFF;\n\n      USBx_OUTEP(3)->DOEPTSIZ = (1U << 19) | 0x40U;\n      USBx_OUTEP(3)->DOEPCTL = (0x40U & USB_OTG_DOEPCTL_MPSIZ) | (2U << 18) |\n                               USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP;\n      USBx_OUTEP(3)->DOEPINT = 0xFF;\n\n      // mark ready to receive\n      USBx_OUTEP(2)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;\n      USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;\n\n      USB_WritePacket(0, 0, 0);\n      USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n      break;\n    case USB_REQ_SET_ADDRESS:\n      // set now?\n      USBx_DEVICE->DCFG |= ((setup.b.wValue.w & 0x7fU) << 4);\n\n      #ifdef DEBUG_USB\n        puts(\" set address\\n\");\n      #endif\n\n      // TODO: this isn't enumeration complete\n      // moved here to work better on OS X\n      usb_cb_enumeration_complete();\n\n      USB_WritePacket(0, 0, 0);\n      USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n\n      break;\n    case USB_REQ_GET_DESCRIPTOR:\n      switch (setup.b.wValue.bw.lsb) {\n        case USB_DESC_TYPE_DEVICE:\n          //puts(\"    writing device descriptor\\n\");\n\n          // set bcdDevice to hardware type\n          device_desc[13] = hw_type;\n          // setup transfer\n          USB_WritePacket(device_desc, MIN(sizeof(device_desc), setup.b.wLength.w), 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n\n          //puts(\"D\");\n          break;\n        case USB_DESC_TYPE_CONFIGURATION:\n          USB_WritePacket(configuration_desc, MIN(sizeof(configuration_desc), setup.b.wLength.w), 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n        case USB_DESC_TYPE_DEVICE_QUALIFIER:\n          USB_WritePacket(device_qualifier, MIN(sizeof(device_qualifier), setup.b.wLength.w), 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n        case USB_DESC_TYPE_STRING:\n          switch (setup.b.wValue.bw.msb) {\n            case STRING_OFFSET_LANGID:\n              USB_WritePacket((uint8_t*)string_language_desc, MIN(sizeof(string_language_desc), setup.b.wLength.w), 0);\n              break;\n            case STRING_OFFSET_IMANUFACTURER:\n              USB_WritePacket((uint8_t*)string_manufacturer_desc, MIN(sizeof(string_manufacturer_desc), setup.b.wLength.w), 0);\n              break;\n            case STRING_OFFSET_IPRODUCT:\n              USB_WritePacket((uint8_t*)string_product_desc, MIN(sizeof(string_product_desc), setup.b.wLength.w), 0);\n              break;\n            case STRING_OFFSET_ISERIAL:\n              #ifdef UID_BASE\n                resp[0] = 0x02 + (12 * 4);\n                resp[1] = 0x03;\n\n                // 96 bits = 12 bytes\n                for (int i = 0; i < 12; i++){\n                  uint8_t cc = ((uint8_t *)UID_BASE)[i];\n                  resp[2 + (i * 4) + 0] = to_hex_char((cc >> 4) & 0xFU);\n                  resp[2 + (i * 4) + 1] = '\\0';\n                  resp[2 + (i * 4) + 2] = to_hex_char((cc >> 0) & 0xFU);\n                  resp[2 + (i * 4) + 3] = '\\0';\n                }\n\n                USB_WritePacket(resp, MIN(resp[0], setup.b.wLength.w), 0);\n              #else\n                USB_WritePacket((const uint8_t *)string_serial_desc, MIN(sizeof(string_serial_desc), setup.b.wLength.w), 0);\n              #endif\n              break;\n            case STRING_OFFSET_ICONFIGURATION:\n              USB_WritePacket((uint8_t*)string_configuration_desc, MIN(sizeof(string_configuration_desc), setup.b.wLength.w), 0);\n              break;\n            case 238:\n              USB_WritePacket((uint8_t*)string_238_desc, MIN(sizeof(string_238_desc), setup.b.wLength.w), 0);\n              break;\n            default:\n              // nothing\n              USB_WritePacket(0, 0, 0);\n              break;\n          }\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n        case USB_DESC_TYPE_BINARY_OBJECT_STORE:\n          USB_WritePacket(binary_object_store_desc, MIN(sizeof(binary_object_store_desc), setup.b.wLength.w), 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n        default:\n          // nothing here?\n          USB_WritePacket(0, 0, 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n      }\n      break;\n    case USB_REQ_GET_STATUS:\n      // empty resp?\n      resp[0] = 0;\n      resp[1] = 0;\n      USB_WritePacket((void*)&resp, 2, 0);\n      USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n      break;\n    case USB_REQ_SET_INTERFACE:\n      // Store the alt setting number for IN EP behavior.\n      current_int0_alt_setting = setup.b.wValue.w;\n      USB_WritePacket(0, 0, 0);\n      USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n      break;\n    case WEBUSB_VENDOR_CODE:\n      switch (setup.b.wIndex.w) {\n        case WEBUSB_REQ_GET_URL:\n          USB_WritePacket(webusb_url_descriptor, MIN(sizeof(webusb_url_descriptor), setup.b.wLength.w), 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n        default:\n          // probably asking for allowed origins, which was removed from the spec\n          USB_WritePacket(0, 0, 0);\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n          break;\n      }\n      break;\n    case MS_VENDOR_CODE:\n      switch (setup.b.wIndex.w) {\n        // winusb 2.0 descriptor from BOS\n        case WINUSB_REQ_GET_DESCRIPTOR:\n          USB_WritePacket_EP0((uint8_t*)winusb_20_desc, MIN(sizeof(winusb_20_desc), setup.b.wLength.w));\n          break;\n        // Extended Compat ID OS Descriptor\n        case WINUSB_REQ_GET_COMPATID_DESCRIPTOR:\n          USB_WritePacket_EP0((uint8_t*)winusb_ext_compatid_os_desc, MIN(sizeof(winusb_ext_compatid_os_desc), setup.b.wLength.w));\n          break;\n        // Extended Properties OS Descriptor\n        case WINUSB_REQ_GET_EXT_PROPS_OS:\n          USB_WritePacket_EP0((uint8_t*)winusb_ext_prop_os_desc, MIN(sizeof(winusb_ext_prop_os_desc), setup.b.wLength.w));\n          break;\n        default:\n          USB_WritePacket_EP0(0, 0);\n      }\n      break;\n    default:\n      resp_len = usb_cb_control_msg(&setup, resp, 1);\n      // response pending if -1 was returned\n      if (resp_len != -1) {\n        USB_WritePacket(resp, MIN(resp_len, setup.b.wLength.w), 0);\n        USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n      }\n  }\n}\n\n\n\n// ***************************** USB port *****************************\n\nvoid usb_irqhandler(void) {\n  //USBx->GINTMSK = 0;\n\n  unsigned int gintsts = USBx->GINTSTS;\n  unsigned int gotgint = USBx->GOTGINT;\n  unsigned int daint = USBx_DEVICE->DAINT;\n\n  // gintsts SUSPEND? 04008428\n  #ifdef DEBUG_USB\n    puth(gintsts);\n    puts(\" \");\n    /*puth(USBx->GCCFG);\n    puts(\" \");*/\n    puth(gotgint);\n    puts(\" ep \");\n    puth(daint);\n    puts(\" USB interrupt!\\n\");\n  #endif\n\n  if ((gintsts & USB_OTG_GINTSTS_CIDSCHG) != 0) {\n    puts(\"connector ID status change\\n\");\n  }\n\n  if ((gintsts & USB_OTG_GINTSTS_ESUSP) != 0) {\n    puts(\"ESUSP detected\\n\");\n  }\n\n  if ((gintsts & USB_OTG_GINTSTS_EOPF) != 0) {\n    usb_eopf_detected = true;\n  }\n\n  if ((gintsts & USB_OTG_GINTSTS_USBRST) != 0) {\n    puts(\"USB reset\\n\");\n    usb_reset();\n  }\n\n  if ((gintsts & USB_OTG_GINTSTS_ENUMDNE) != 0) {\n    puts(\"enumeration done\");\n    // Full speed, ENUMSPD\n    //puth(USBx_DEVICE->DSTS);\n    puts(\"\\n\");\n  }\n\n  if ((gintsts & USB_OTG_GINTSTS_OTGINT) != 0) {\n    puts(\"OTG int:\");\n    puth(USBx->GOTGINT);\n    puts(\"\\n\");\n\n    // getting ADTOCHG\n    //USBx->GOTGINT = USBx->GOTGINT;\n  }\n\n  // RX FIFO first\n  if ((gintsts & USB_OTG_GINTSTS_RXFLVL) != 0) {\n    // 1. Read the Receive status pop register\n    volatile unsigned int rxst = USBx->GRXSTSP;\n    int status = (rxst & USB_OTG_GRXSTSP_PKTSTS) >> 17;\n\n    #ifdef DEBUG_USB\n      puts(\" RX FIFO:\");\n      puth(rxst);\n      puts(\" status: \");\n      puth(status);\n      puts(\" len: \");\n      puth((rxst & USB_OTG_GRXSTSP_BCNT) >> 4);\n      puts(\"\\n\");\n    #endif\n\n    if (status == STS_DATA_UPDT) {\n      int endpoint = (rxst & USB_OTG_GRXSTSP_EPNUM);\n      int len = (rxst & USB_OTG_GRXSTSP_BCNT) >> 4;\n      (void)USB_ReadPacket(&usbdata, len);\n      #ifdef DEBUG_USB\n        puts(\"  data \");\n        puth(len);\n        puts(\"\\n\");\n        hexdump(&usbdata, len);\n      #endif\n\n      if (endpoint == 2) {\n        usb_cb_ep2_out(usbdata, len, 1);\n      }\n\n      if (endpoint == 3) {\n        outep3_processing = true;\n        usb_cb_ep3_out(usbdata, len, 1);\n      }\n    } else if (status == STS_SETUP_UPDT) {\n      (void)USB_ReadPacket(&setup, 8);\n      #ifdef DEBUG_USB\n        puts(\"  setup \");\n        hexdump(&setup, 8);\n        puts(\"\\n\");\n      #endif\n    } else {\n      // status is neither STS_DATA_UPDT or STS_SETUP_UPDT, skip\n    }\n  }\n\n  /*if (gintsts & USB_OTG_GINTSTS_HPRTINT) {\n    // host\n    puts(\"HPRT:\");\n    puth(USBx_HOST_PORT->HPRT);\n    puts(\"\\n\");\n    if (USBx_HOST_PORT->HPRT & USB_OTG_HPRT_PCDET) {\n      USBx_HOST_PORT->HPRT |= USB_OTG_HPRT_PRST;\n      USBx_HOST_PORT->HPRT |= USB_OTG_HPRT_PCDET;\n    }\n\n  }*/\n\n  if ((gintsts & USB_OTG_GINTSTS_BOUTNAKEFF) || (gintsts & USB_OTG_GINTSTS_GINAKEFF)) {\n    // no global NAK, why is this getting set?\n    #ifdef DEBUG_USB\n      puts(\"GLOBAL NAK\\n\");\n    #endif\n    USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK | USB_OTG_DCTL_CGINAK;\n  }\n\n  if ((gintsts & USB_OTG_GINTSTS_SRQINT) != 0) {\n    // we want to do \"A-device host negotiation protocol\" since we are the A-device\n    /*puts(\"start request\\n\");\n    puth(USBx->GOTGCTL);\n    puts(\"\\n\");*/\n    //USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\n    //USBx_HOST_PORT->HPRT = USB_OTG_HPRT_PPWR | USB_OTG_HPRT_PENA;\n    //USBx->GOTGCTL |= USB_OTG_GOTGCTL_SRQ;\n  }\n\n  // out endpoint hit\n  if ((gintsts & USB_OTG_GINTSTS_OEPINT) != 0) {\n    #ifdef DEBUG_USB\n      puts(\"  0:\");\n      puth(USBx_OUTEP(0)->DOEPINT);\n      puts(\" 2:\");\n      puth(USBx_OUTEP(2)->DOEPINT);\n      puts(\" 3:\");\n      puth(USBx_OUTEP(3)->DOEPINT);\n      puts(\" \");\n      puth(USBx_OUTEP(3)->DOEPCTL);\n      puts(\" 4:\");\n      puth(USBx_OUTEP(4)->DOEPINT);\n      puts(\" OUT ENDPOINT\\n\");\n    #endif\n\n    if ((USBx_OUTEP(2)->DOEPINT & USB_OTG_DOEPINT_XFRC) != 0) {\n      #ifdef DEBUG_USB\n        puts(\"  OUT2 PACKET XFRC\\n\");\n      #endif\n      USBx_OUTEP(2)->DOEPTSIZ = (1U << 19) | 0x40U;\n      USBx_OUTEP(2)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;\n    }\n\n    if ((USBx_OUTEP(3)->DOEPINT & USB_OTG_DOEPINT_XFRC) != 0) {\n      #ifdef DEBUG_USB\n        puts(\"  OUT3 PACKET XFRC\\n\");\n      #endif\n      // NAK cleared by process_can (if tx buffers have room)\n      outep3_processing = false;\n      usb_cb_ep3_out_complete();\n    } else if ((USBx_OUTEP(3)->DOEPINT & 0x2000) != 0) {\n      #ifdef DEBUG_USB\n        puts(\"  OUT3 PACKET WTF\\n\");\n      #endif\n      // if NAK was set trigger this, unknown interrupt\n      // TODO: why was this here? fires when TX buffers when we can't clear NAK\n      // USBx_OUTEP(3)->DOEPTSIZ = (1U << 19) | 0x40U;\n      // USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n    } else if ((USBx_OUTEP(3)->DOEPINT) != 0) {\n      puts(\"OUTEP3 error \");\n      puth(USBx_OUTEP(3)->DOEPINT);\n      puts(\"\\n\");\n    } else {\n      // USBx_OUTEP(3)->DOEPINT is 0, ok to skip\n    }\n\n    if ((USBx_OUTEP(0)->DOEPINT & USB_OTG_DIEPINT_XFRC) != 0) {\n      // ready for next packet\n      USBx_OUTEP(0)->DOEPTSIZ = USB_OTG_DOEPTSIZ_STUPCNT | (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)) | (1U << 3);\n    }\n\n    // respond to setup packets\n    if ((USBx_OUTEP(0)->DOEPINT & USB_OTG_DOEPINT_STUP) != 0) {\n      usb_setup();\n    }\n\n    USBx_OUTEP(0)->DOEPINT = USBx_OUTEP(0)->DOEPINT;\n    USBx_OUTEP(2)->DOEPINT = USBx_OUTEP(2)->DOEPINT;\n    USBx_OUTEP(3)->DOEPINT = USBx_OUTEP(3)->DOEPINT;\n  }\n\n  // interrupt endpoint hit (Page 1221)\n  if ((gintsts & USB_OTG_GINTSTS_IEPINT) != 0) {\n    #ifdef DEBUG_USB\n      puts(\"  \");\n      puth(USBx_INEP(0)->DIEPINT);\n      puts(\" \");\n      puth(USBx_INEP(1)->DIEPINT);\n      puts(\" IN ENDPOINT\\n\");\n    #endif\n\n    // Should likely check the EP of the IN request even if there is\n    // only one IN endpoint.\n\n    // No need to set NAK in OTG_DIEPCTL0 when nothing to send,\n    // Appears USB core automatically sets NAK. WritePacket clears it.\n\n    // Handle the two interface alternate settings. Setting 0 has EP1\n    // as bulk. Setting 1 has EP1 as interrupt. The code to handle\n    // these two EP variations are very similar and can be\n    // restructured for smaller code footprint. Keeping split out for\n    // now for clarity.\n\n    //TODO add default case. Should it NAK?\n    switch (current_int0_alt_setting) {\n      case 0: ////// Bulk config\n        // *** IN token received when TxFIFO is empty\n        if ((USBx_INEP(1)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0) {\n          #ifdef DEBUG_USB\n          puts(\"  IN PACKET QUEUE\\n\");\n          #endif\n          // TODO: always assuming max len, can we get the length?\n          USB_WritePacket((void *)resp, usb_cb_ep1_in(resp, 0x40, 1), 1);\n        }\n        break;\n\n      case 1: ////// Interrupt config\n        // *** IN token received when TxFIFO is empty\n        if ((USBx_INEP(1)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0) {\n          #ifdef DEBUG_USB\n          puts(\"  IN PACKET QUEUE\\n\");\n          #endif\n          // TODO: always assuming max len, can we get the length?\n          int len = usb_cb_ep1_in(resp, 0x40, 1);\n          if (len > 0) {\n            USB_WritePacket((void *)resp, len, 1);\n          }\n        }\n        break;\n      default:\n        puts(\"current_int0_alt_setting value invalid\\n\");\n        break;\n    }\n\n    if ((USBx_INEP(0)->DIEPINT & USB_OTG_DIEPMSK_ITTXFEMSK) != 0) {\n      #ifdef DEBUG_USB\n      puts(\"  IN PACKET QUEUE\\n\");\n      #endif\n\n      if ((ep0_txlen != 0U) && ((USBx_INEP(0)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= 0x40U)) {\n        uint16_t len = MIN(ep0_txlen, 0x40);\n        USB_WritePacket(ep0_txdata, len, 0);\n        ep0_txdata = &ep0_txdata[len];\n        ep0_txlen -= len;\n        if (ep0_txlen == 0U) {\n          ep0_txdata = NULL;\n          USBx_DEVICE->DIEPEMPMSK &= ~1;\n          USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK;\n        }\n      }\n    }\n\n    // clear interrupts\n    USBx_INEP(0)->DIEPINT = USBx_INEP(0)->DIEPINT; // Why ep0?\n    USBx_INEP(1)->DIEPINT = USBx_INEP(1)->DIEPINT;\n  }\n\n  // clear all interrupts we handled\n  USBx_DEVICE->DAINT = daint;\n  USBx->GOTGINT = gotgint;\n  USBx->GINTSTS = gintsts;\n\n  //USBx->GINTMSK = 0xFFFFFFFF & ~(USB_OTG_GINTMSK_NPTXFEM | USB_OTG_GINTMSK_PTXFEM | USB_OTG_GINTSTS_SOF | USB_OTG_GINTSTS_EOPF);\n}\n\nvoid usb_outep3_resume_if_paused(void) {\n  ENTER_CRITICAL();\n  if (!outep3_processing && (USBx_OUTEP(3)->DOEPCTL & USB_OTG_DOEPCTL_NAKSTS) != 0) {\n    USBx_OUTEP(3)->DOEPTSIZ = (1U << 19) | 0x40U;\n    USBx_OUTEP(3)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;\n  }\n  EXIT_CRITICAL();\n}\n\nbool usb_enumerated(void) {\n  // This relies on the USB being suspended after no activity for 3ms.\n  // Seems pretty stable in combination with the EOPF to reject noise.\n  bool ret = false;\n  if(!(USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS)){\n    // Check to see if an end of periodic frame is detected\n    ret = usb_eopf_detected;\n  }\n  usb_eopf_detected = false;\n  return ret;\n}\n"
  },
  {
    "path": "panda/board/early_init.h",
    "content": "// Early bringup\n#define ENTER_BOOTLOADER_MAGIC 0xdeadbeefU\n#define ENTER_SOFTLOADER_MAGIC 0xdeadc0deU\n#define BOOT_NORMAL 0xdeadb111U\n\nextern void *g_pfnVectors;\nextern uint32_t enter_bootloader_mode;\n\nvoid jump_to_bootloader(void) {\n  // do enter bootloader\n  enter_bootloader_mode = 0;\n  void (*bootloader)(void) = (void (*)(void)) (*((uint32_t *)BOOTLOADER_ADDRESS));\n\n  // jump to bootloader\n  enable_interrupts();\n  bootloader();\n\n  // reset on exit\n  enter_bootloader_mode = BOOT_NORMAL;\n  NVIC_SystemReset();\n}\n\nvoid early_initialization(void) {\n  // Reset global critical depth\n  disable_interrupts();\n  global_critical_depth = 0;\n\n  // Init register and interrupt tables\n  init_registers();\n\n  // after it's been in the bootloader, things are initted differently, so we reset\n  if ((enter_bootloader_mode != BOOT_NORMAL) &&\n      (enter_bootloader_mode != ENTER_BOOTLOADER_MAGIC) &&\n      (enter_bootloader_mode != ENTER_SOFTLOADER_MAGIC)) {\n    enter_bootloader_mode = BOOT_NORMAL;\n    NVIC_SystemReset();\n  }\n\n  // if wrong chip, reboot\n  volatile unsigned int id = DBGMCU->IDCODE;\n    if ((id & 0xFFFU) != MCU_IDCODE) {\n      enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;\n    }\n\n  // setup interrupt table\n  SCB->VTOR = (uint32_t)&g_pfnVectors;\n\n  // early GPIOs float everything\n  early_gpio_float();\n\n  detect_external_debug_serial();\n  detect_board_type();\n\n  if (enter_bootloader_mode == ENTER_BOOTLOADER_MAGIC) {\n  #ifdef PANDA\n    current_board->set_gps_mode(GPS_DISABLED);\n  #endif\n    current_board->set_led(LED_GREEN, 1);\n    jump_to_bootloader();\n  }\n}\n"
  },
  {
    "path": "panda/board/faults.h",
    "content": "#define FAULT_STATUS_NONE 0U\n#define FAULT_STATUS_TEMPORARY 1U\n#define FAULT_STATUS_PERMANENT 2U\n\n// Fault types\n#define FAULT_RELAY_MALFUNCTION             (1U << 0)\n#define FAULT_UNUSED_INTERRUPT_HANDLED      (1U << 1)\n#define FAULT_INTERRUPT_RATE_CAN_1          (1U << 2)\n#define FAULT_INTERRUPT_RATE_CAN_2          (1U << 3)\n#define FAULT_INTERRUPT_RATE_CAN_3          (1U << 4)\n#define FAULT_INTERRUPT_RATE_TACH           (1U << 5)\n#define FAULT_INTERRUPT_RATE_GMLAN          (1U << 6)\n#define FAULT_INTERRUPT_RATE_INTERRUPTS     (1U << 7)\n#define FAULT_INTERRUPT_RATE_SPI_DMA        (1U << 8)\n#define FAULT_INTERRUPT_RATE_SPI_CS         (1U << 9)\n#define FAULT_INTERRUPT_RATE_UART_1         (1U << 10)\n#define FAULT_INTERRUPT_RATE_UART_2         (1U << 11)\n#define FAULT_INTERRUPT_RATE_UART_3         (1U << 12)\n#define FAULT_INTERRUPT_RATE_UART_5         (1U << 13)\n#define FAULT_INTERRUPT_RATE_UART_DMA       (1U << 14)\n#define FAULT_INTERRUPT_RATE_USB            (1U << 15)\n#define FAULT_INTERRUPT_RATE_TIM1           (1U << 16)\n#define FAULT_INTERRUPT_RATE_TIM3           (1U << 17)\n#define FAULT_REGISTER_DIVERGENT            (1U << 18)\n#define FAULT_INTERRUPT_RATE_KLINE_INIT     (1U << 19)\n#define FAULT_INTERRUPT_RATE_CLOCK_SOURCE   (1U << 20)\n#define FAULT_INTERRUPT_RATE_TICK           (1U << 21)\n\n// Permanent faults\n#define PERMANENT_FAULTS 0U\n\nuint8_t fault_status = FAULT_STATUS_NONE;\nuint32_t faults = 0U;\n\nvoid fault_occurred(uint32_t fault) {\n  faults |= fault;\n  if((PERMANENT_FAULTS & fault) != 0U){\n    puts(\"Permanent fault occurred: 0x\"); puth(fault); puts(\"\\n\");\n    fault_status = FAULT_STATUS_PERMANENT;\n  } else {\n    puts(\"Temporary fault occurred: 0x\"); puth(fault); puts(\"\\n\");\n    fault_status = FAULT_STATUS_TEMPORARY;\n  }\n}\n\nvoid fault_recovered(uint32_t fault) {\n  if((PERMANENT_FAULTS & fault) == 0U){\n    faults &= ~fault;\n  } else {\n    puts(\"Cannot recover from a permanent fault!\\n\");\n  }\n}\n"
  },
  {
    "path": "panda/board/flash.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\nscons -u\nPYTHONPATH=.. python3 -c \"from python import Panda; Panda().flash('obj/panda.bin.signed')\"\n"
  },
  {
    "path": "panda/board/flash_h7.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\nPANDA_GEN3=1 scons -u\nPYTHONPATH=.. python3 -c \"from python import Panda; Panda().flash('obj/panda_h7.bin.signed')\"\n"
  },
  {
    "path": "panda/board/flasher.h",
    "content": "// flasher state variables\nuint32_t *prog_ptr = NULL;\nbool unlocked = false;\n\n#ifdef uart_ring\nvoid debug_ring_callback(uart_ring *ring) {}\n#endif\n\nint usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired) {\n  int resp_len = 0;\n\n  // flasher machine\n  memset(resp, 0, 4);\n  memcpy(resp+4, \"\\xde\\xad\\xd0\\x0d\", 4);\n  resp[0] = 0xff;\n  resp[2] = setup->b.bRequest;\n  resp[3] = ~setup->b.bRequest;\n  *((uint32_t **)&resp[8]) = prog_ptr;\n  resp_len = 0xc;\n\n  int sec;\n  switch (setup->b.bRequest) {\n    // **** 0xb0: flasher echo\n    case 0xb0:\n      resp[1] = 0xff;\n      break;\n    // **** 0xb1: unlock flash\n    case 0xb1:\n      if (flash_is_locked()) {\n        flash_unlock();\n        resp[1] = 0xff;\n      }\n      current_board->set_led(LED_GREEN, 1);\n      unlocked = true;\n      prog_ptr = (uint32_t *)APP_START_ADDRESS;\n      break;\n    // **** 0xb2: erase sector\n    case 0xb2:\n      sec = setup->b.wValue.w;\n      if (flash_erase_sector(sec, unlocked)) {\n        resp[1] = 0xff;\n      }\n      break;\n    // **** 0xd0: fetch serial number\n    case 0xd0:\n      #ifndef STM32F2\n        // addresses are OTP\n        if (setup->b.wValue.w == 1) {\n          memcpy(resp, (void *)DEVICE_SERIAL_NUMBER_ADDRESS, 0x10);\n          resp_len = 0x10;\n        } else {\n          get_provision_chunk(resp);\n          resp_len = PROVISION_CHUNK_LEN;\n        }\n      #endif\n      break;\n    // **** 0xd1: enter bootloader mode\n    case 0xd1:\n      // this allows reflashing of the bootstub\n      // so it's blocked over wifi\n      switch (setup->b.wValue.w) {\n        case 0:\n          // TODO: put this back when it's no longer a \"devkit\"\n          //#ifdef ALLOW_DEBUG\n          #if 1\n          if (hardwired) {\n          #else\n          // no more bootstub on UNO once OTP block is flashed\n          if (hardwired && ((hw_type != HW_TYPE_UNO) || (!is_provisioned()))) {\n          #endif\n            puts(\"-> entering bootloader\\n\");\n            enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;\n            NVIC_SystemReset();\n          }\n          break;\n        case 1:\n          puts(\"-> entering softloader\\n\");\n          enter_bootloader_mode = ENTER_SOFTLOADER_MAGIC;\n          NVIC_SystemReset();\n          break;\n      }\n      break;\n    // **** 0xd6: get version\n    case 0xd6:\n      COMPILE_TIME_ASSERT(sizeof(gitversion) <= MAX_RESP_LEN);\n      memcpy(resp, gitversion, sizeof(gitversion));\n      resp_len = sizeof(gitversion);\n      break;\n    // **** 0xd8: reset ST\n    case 0xd8:\n      flush_write_buffer();\n      NVIC_SystemReset();\n      break;\n  }\n  return resp_len;\n}\n\nint usb_cb_ep1_in(void *usbdata, int len, bool hardwired) {\n  UNUSED(usbdata);\n  UNUSED(len);\n  UNUSED(hardwired);\n  return 0;\n}\nvoid usb_cb_ep3_out(void *usbdata, int len, bool hardwired) {\n  UNUSED(usbdata);\n  UNUSED(len);\n  UNUSED(hardwired);\n}\nvoid usb_cb_ep3_out_complete(void) {}\n\nint is_enumerated = 0;\nvoid usb_cb_enumeration_complete(void) {\n  puts(\"USB enumeration complete\\n\");\n  is_enumerated = 1;\n}\n\nvoid usb_cb_ep2_out(void *usbdata, int len, bool hardwired) {\n  UNUSED(hardwired);\n  current_board->set_led(LED_RED, 0);\n  for (int i = 0; i < len/4; i++) {\n    flash_write_word(prog_ptr, *(uint32_t*)(usbdata+(i*4)));\n\n    //*(uint64_t*)(&spi_tx_buf[0x30+(i*4)]) = *prog_ptr;\n    prog_ptr++;\n  }\n  current_board->set_led(LED_RED, 1);\n}\n\n\nint spi_cb_rx(uint8_t *data, int len, uint8_t *data_out) {\n  UNUSED(len);\n  int resp_len = 0;\n  switch (data[0]) {\n    case 0:\n      // control transfer\n      resp_len = usb_cb_control_msg((USB_Setup_TypeDef *)(data+4), data_out, 0);\n      break;\n    case 2:\n      // ep 2, flash!\n      usb_cb_ep2_out(data+4, data[2], 0);\n      break;\n  }\n  return resp_len;\n}\n\n#ifdef PEDAL\n\n#include \"stm32fx/llbxcan.h\"\n#define CAN CAN1\n\n#define CAN_BL_INPUT 0x1\n#define CAN_BL_OUTPUT 0x2\n\nvoid CAN1_TX_IRQ_Handler(void) {\n  // clear interrupt\n  CAN->TSR |= CAN_TSR_RQCP0;\n}\n\n#define ISOTP_BUF_SIZE 0x110\n\nuint8_t isotp_buf[ISOTP_BUF_SIZE];\nuint8_t *isotp_buf_ptr = NULL;\nint isotp_buf_remain = 0;\n\nuint8_t isotp_buf_out[ISOTP_BUF_SIZE];\nuint8_t *isotp_buf_out_ptr = NULL;\nint isotp_buf_out_remain = 0;\nint isotp_buf_out_idx = 0;\n\nvoid bl_can_send(uint8_t *odat) {\n  // wait for send\n  while (!(CAN->TSR & CAN_TSR_TME0));\n\n  // send continue\n  CAN->sTxMailBox[0].TDLR = ((uint32_t*)odat)[0];\n  CAN->sTxMailBox[0].TDHR = ((uint32_t*)odat)[1];\n  CAN->sTxMailBox[0].TDTR = 8;\n  CAN->sTxMailBox[0].TIR = (CAN_BL_OUTPUT << 21) | 1;\n}\n\nvoid CAN1_RX0_IRQ_Handler(void) {\n  while (CAN->RF0R & CAN_RF0R_FMP0) {\n    if ((CAN->sFIFOMailBox[0].RIR>>21) == CAN_BL_INPUT) {\n      uint8_t dat[8];\n      for (int i = 0; i < 8; i++) {\n        dat[i] = GET_BYTE(&CAN->sFIFOMailBox[0], i);\n      }\n      uint8_t odat[8];\n      uint8_t type = dat[0] & 0xF0;\n      if (type == 0x30) {\n        // continue\n        while (isotp_buf_out_remain > 0) {\n          // wait for send\n          while (!(CAN->TSR & CAN_TSR_TME0));\n\n          odat[0] = 0x20 | isotp_buf_out_idx;\n          memcpy(odat+1, isotp_buf_out_ptr, 7);\n          isotp_buf_out_remain -= 7;\n          isotp_buf_out_ptr += 7;\n          isotp_buf_out_idx++;\n\n          bl_can_send(odat);\n        }\n      } else if (type == 0x20) {\n        if (isotp_buf_remain > 0) {\n          memcpy(isotp_buf_ptr, dat+1, 7);\n          isotp_buf_ptr += 7;\n          isotp_buf_remain -= 7;\n        }\n        if (isotp_buf_remain <= 0) {\n          int len = isotp_buf_ptr - isotp_buf + isotp_buf_remain;\n\n          // call the function\n          memset(isotp_buf_out, 0, ISOTP_BUF_SIZE);\n          isotp_buf_out_remain = spi_cb_rx(isotp_buf, len, isotp_buf_out);\n          isotp_buf_out_ptr = isotp_buf_out;\n          isotp_buf_out_idx = 0;\n\n          // send initial\n          if (isotp_buf_out_remain <= 7) {\n            odat[0] = isotp_buf_out_remain;\n            memcpy(odat+1, isotp_buf_out_ptr, isotp_buf_out_remain);\n          } else {\n            odat[0] = 0x10 | (isotp_buf_out_remain>>8);\n            odat[1] = isotp_buf_out_remain & 0xFF;\n            memcpy(odat+2, isotp_buf_out_ptr, 6);\n            isotp_buf_out_remain -= 6;\n            isotp_buf_out_ptr += 6;\n            isotp_buf_out_idx++;\n          }\n\n          bl_can_send(odat);\n        }\n      } else if (type == 0x10) {\n        int len = ((dat[0]&0xF)<<8) | dat[1];\n\n        // setup buffer\n        isotp_buf_ptr = isotp_buf;\n        memcpy(isotp_buf_ptr, dat+2, 6);\n\n        if (len < (ISOTP_BUF_SIZE-0x10)) {\n          isotp_buf_ptr += 6;\n          isotp_buf_remain = len-6;\n        }\n\n        memset(odat, 0, 8);\n        odat[0] = 0x30;\n        bl_can_send(odat);\n      }\n    }\n    // next\n    CAN->RF0R |= CAN_RF0R_RFOM0;\n  }\n}\n\nvoid CAN1_SCE_IRQ_Handler(void) {\n  llcan_clear_send(CAN);\n}\n\n#endif\n\nvoid soft_flasher_start(void) {\n  #ifdef PEDAL\n    REGISTER_INTERRUPT(CAN1_TX_IRQn, CAN1_TX_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n    REGISTER_INTERRUPT(CAN1_RX0_IRQn, CAN1_RX0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n    REGISTER_INTERRUPT(CAN1_SCE_IRQn, CAN1_SCE_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  #endif\n\n  puts(\"\\n\\n\\n************************ FLASHER START ************************\\n\");\n\n  enter_bootloader_mode = 0;\n\n  flasher_peripherals_init();\n\n// pedal has the canloader\n#ifdef PEDAL\n  RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;\n\n  // B8,B9: CAN 1\n  set_gpio_alternate(GPIOB, 8, GPIO_AF9_CAN1);\n  set_gpio_alternate(GPIOB, 9, GPIO_AF9_CAN1);\n  current_board->enable_can_transceiver(1, true);\n\n  // init can\n  llcan_set_speed(CAN1, 5000, false, false);\n  llcan_init(CAN1);\n#endif\n\n  gpio_usart2_init();\n  gpio_usb_init();\n\n  // enable USB\n  usb_init();\n\n  // green LED on for flashing\n  current_board->set_led(LED_GREEN, 1);\n\n  enable_interrupts();\n\n  uint64_t cnt = 0;\n\n  for (cnt=0;;cnt++) {\n    if (cnt == 35 && !is_enumerated && usb_power_mode == USB_POWER_CLIENT) {\n      // if you are connected through a hub to the phone\n      // you need power to be able to see the device\n      puts(\"USBP: didn't enumerate, switching to CDP mode\\n\");\n      current_board->set_usb_power_mode(USB_POWER_CDP);\n      current_board->set_led(LED_BLUE, 1);\n    }\n    // blink the green LED fast\n    current_board->set_led(LED_GREEN, 0);\n    delay(500000);\n    current_board->set_led(LED_GREEN, 1);\n    delay(500000);\n  }\n}\n"
  },
  {
    "path": "panda/board/get_sdk.sh",
    "content": "#!/bin/bash\nsudo apt-get install gcc-arm-none-eabi python-pip\nsudo pip install libusb1 pycryptodome requests\n"
  },
  {
    "path": "panda/board/get_sdk_mac.sh",
    "content": "#!/bin/bash\n# Need formula for gcc\nsudo easy_install pip\n/usr/bin/ruby -e \"$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)\"\nbrew tap ArmMbed/homebrew-formulae\nbrew install python dfu-util arm-none-eabi-gcc\npip install --user libusb1 pycryptodome requests\n"
  },
  {
    "path": "panda/board/libc.h",
    "content": "// **** libc ****\n\nvoid delay(uint32_t a) {\n  volatile uint32_t i;\n  for (i = 0; i < a; i++);\n}\n\nvoid *memset(void *str, int c, unsigned int n) {\n  uint8_t *s = str;\n  for (unsigned int i = 0; i < n; i++) {\n    *s = c;\n    s++;\n  }\n  return str;\n}\n\nvoid *memcpy(void *dest, const void *src, unsigned int n) {\n  uint8_t *d = dest;\n  const uint8_t *s = src;\n  for (unsigned int i = 0; i < n; i++) {\n    *d = *s;\n    d++;\n    s++;\n  }\n  return dest;\n}\n\nint memcmp(const void * ptr1, const void * ptr2, unsigned int num) {\n  int ret = 0;\n  const uint8_t *p1 = ptr1;\n  const uint8_t *p2 = ptr2;\n  for (unsigned int i = 0; i < num; i++) {\n    if (*p1 != *p2) {\n      ret = -1;\n      break;\n    }\n    p1++;\n    p2++;\n  }\n  return ret;\n}\n"
  },
  {
    "path": "panda/board/main.c",
    "content": "// ********************* Includes *********************\n#include \"config.h\"\n\n#include \"drivers/pwm.h\"\n#include \"drivers/usb.h\"\n#include \"drivers/gmlan_alt.h\"\n#include \"drivers/kline_init.h\"\n\n#include \"early_init.h\"\n#include \"provision.h\"\n\n#include \"power_saving.h\"\n#include \"safety.h\"\n\n#include \"drivers/can_common.h\"\n\n#ifdef STM32H7\n  #include \"drivers/fdcan.h\"\n#else\n  #include \"drivers/bxcan.h\"\n#endif\n\n#include \"obj/gitversion.h\"\n\nextern int _app_start[0xc000]; // Only first 3 sectors of size 0x4000 are used\n\n// When changing this struct, boardd and python/__init__.py needs to be kept up to date!\nstruct __attribute__((packed)) health_t {\n  uint32_t uptime_pkt;\n  uint32_t voltage_pkt;\n  uint32_t current_pkt;\n  uint32_t can_rx_errs_pkt;\n  uint32_t can_send_errs_pkt;\n  uint32_t can_fwd_errs_pkt;\n  uint32_t gmlan_send_errs_pkt;\n  uint32_t faults_pkt;\n  uint8_t ignition_line_pkt;\n  uint8_t ignition_can_pkt;\n  uint8_t controls_allowed_pkt;\n  uint8_t gas_interceptor_detected_pkt;\n  uint8_t car_harness_status_pkt;\n  uint8_t usb_power_mode_pkt;\n  uint8_t safety_mode_pkt;\n  int16_t safety_param_pkt;\n  uint8_t fault_status_pkt;\n  uint8_t power_save_enabled_pkt;\n  uint8_t heartbeat_lost_pkt;\n};\n\n\n// ********************* Serial debugging *********************\n\nbool check_started(void) {\n  return current_board->check_ignition() || ignition_can;\n}\n\nvoid debug_ring_callback(uart_ring *ring) {\n  char rcv;\n  while (getc(ring, &rcv)) {\n    (void)putc(ring, rcv);  // misra-c2012-17.7: cast to void is ok: debug function\n\n    // only allow bootloader entry on debug builds\n    #ifdef ALLOW_DEBUG\n      // jump to DFU flash\n      if (rcv == 'z') {\n        enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;\n        NVIC_SystemReset();\n      }\n    #endif\n\n    // normal reset\n    if (rcv == 'x') {\n      NVIC_SystemReset();\n    }\n\n    // enable CDP mode\n    if (rcv == 'C') {\n      puts(\"switching USB to CDP mode\\n\");\n      current_board->set_usb_power_mode(USB_POWER_CDP);\n    }\n    if (rcv == 'c') {\n      puts(\"switching USB to client mode\\n\");\n      current_board->set_usb_power_mode(USB_POWER_CLIENT);\n    }\n    if (rcv == 'D') {\n      puts(\"switching USB to DCP mode\\n\");\n      current_board->set_usb_power_mode(USB_POWER_DCP);\n    }\n  }\n}\n\n// ****************************** safety mode ******************************\n\n// this is the only way to leave silent mode\nvoid set_safety_mode(uint16_t mode, int16_t param) {\n  uint16_t mode_copy = mode;\n  int err = set_safety_hooks(mode_copy, param);\n  if (err == -1) {\n    puts(\"Error: safety set mode failed. Falling back to SILENT\\n\");\n    mode_copy = SAFETY_SILENT;\n    err = set_safety_hooks(mode_copy, 0);\n    if (err == -1) {\n      puts(\"Error: Failed setting SILENT mode. Hanging\\n\");\n      while (true) {\n        // TERMINAL ERROR: we can't continue if SILENT safety mode isn't succesfully set\n      }\n    }\n  }\n  switch (mode_copy) {\n    case SAFETY_SILENT:\n      set_intercept_relay(false);\n      #ifdef vw\n      // Volkswagen community port:\n      // J533 integrations with White/Grey Panda really need Panda to respond\n      // at all times. Let the CAN transceivers ACK traffic unless this is\n      // BP/Uno where the physical relay makes it irrelevant. This makes\n      // SILENT identical to NOOUTPUT for White/Grey Panda.\n      if (current_board->has_obd) {\n        current_board->set_can_mode(CAN_MODE_NORMAL);\n        can_silent = ALL_CAN_SILENT;\n      } else {\n        can_silent = ALL_CAN_LIVE;\n      }\n      #else\n      if (current_board->has_obd) {\n        current_board->set_can_mode(CAN_MODE_NORMAL);\n      }\n      can_silent = ALL_CAN_SILENT;\n      #endif\n      break;\n    case SAFETY_NOOUTPUT:\n      set_intercept_relay(false);\n      if (current_board->has_obd) {\n        current_board->set_can_mode(CAN_MODE_NORMAL);\n      }\n      can_silent = ALL_CAN_LIVE;\n      break;\n    case SAFETY_ELM327:\n      set_intercept_relay(false);\n      heartbeat_counter = 0U;\n      heartbeat_lost = false;\n      if (current_board->has_obd) {\n        if (param == 0) {\n          current_board->set_can_mode(CAN_MODE_OBD_CAN2);\n        } else {\n          current_board->set_can_mode(CAN_MODE_NORMAL);\n        }\n      }\n      can_silent = ALL_CAN_LIVE;\n      break;\n    default:\n      set_intercept_relay(true);\n      heartbeat_counter = 0U;\n      heartbeat_lost = false;\n      if (current_board->has_obd) {\n        current_board->set_can_mode(CAN_MODE_NORMAL);\n      }\n      can_silent = ALL_CAN_LIVE;\n      break;\n  }\n  can_init_all();\n}\n\nbool is_car_safety_mode(uint16_t mode) {\n  return (mode != SAFETY_SILENT) &&\n         (mode != SAFETY_NOOUTPUT) &&\n         (mode != SAFETY_ELM327);\n}\n\n// ***************************** USB port *****************************\n\nint get_health_pkt(void *dat) {\n  COMPILE_TIME_ASSERT(sizeof(struct health_t) <= MAX_RESP_LEN);\n  struct health_t * health = (struct health_t*)dat;\n\n  health->uptime_pkt = uptime_cnt;\n  health->voltage_pkt = adc_get_voltage();\n  health->current_pkt = current_board->read_current();\n\n  //Use the GPIO pin to determine ignition or use a CAN based logic\n  health->ignition_line_pkt = (uint8_t)(current_board->check_ignition());\n  health->ignition_can_pkt = (uint8_t)(ignition_can);\n\n  health->controls_allowed_pkt = controls_allowed;\n  health->gas_interceptor_detected_pkt = gas_interceptor_detected;\n  health->can_rx_errs_pkt = can_rx_errs;\n  health->can_send_errs_pkt = can_send_errs;\n  health->can_fwd_errs_pkt = can_fwd_errs;\n  health->gmlan_send_errs_pkt = gmlan_send_errs;\n  health->car_harness_status_pkt = car_harness_status;\n  health->usb_power_mode_pkt = usb_power_mode;\n  health->safety_mode_pkt = (uint8_t)(current_safety_mode);\n  health->safety_param_pkt = current_safety_param;\n  health->power_save_enabled_pkt = (uint8_t)(power_save_status == POWER_SAVE_STATUS_ENABLED);\n  health->heartbeat_lost_pkt = (uint8_t)(heartbeat_lost);\n\n  health->fault_status_pkt = fault_status;\n  health->faults_pkt = faults;\n\n  return sizeof(*health);\n}\n\nint get_rtc_pkt(void *dat) {\n  timestamp_t t = rtc_get_time();\n  (void)memcpy(dat, &t, sizeof(t));\n  return sizeof(t);\n}\n\nint usb_cb_ep1_in(void *usbdata, int len, bool hardwired) {\n  UNUSED(hardwired);\n  CAN_FIFOMailBox_TypeDef *reply = (CAN_FIFOMailBox_TypeDef *)usbdata;\n  int ilen = 0;\n  while (ilen < MIN(len/0x10, 4) && can_pop(&can_rx_q, &reply[ilen])) {\n    ilen++;\n  }\n  return ilen*0x10;\n}\n\n// send on serial, first byte to select the ring\nvoid usb_cb_ep2_out(void *usbdata, int len, bool hardwired) {\n  UNUSED(hardwired);\n  uint8_t *usbdata8 = (uint8_t *)usbdata;\n  uart_ring *ur = get_ring_by_number(usbdata8[0]);\n  if ((len != 0) && (ur != NULL)) {\n    if ((usbdata8[0] < 2U) || safety_tx_lin_hook(usbdata8[0] - 2U, &usbdata8[1], len - 1)) {\n      for (int i = 1; i < len; i++) {\n        while (!putc(ur, usbdata8[i])) {\n          // wait\n        }\n      }\n    }\n  }\n}\n\n// send on CAN\nvoid usb_cb_ep3_out(void *usbdata, int len, bool hardwired) {\n  UNUSED(hardwired);\n  int dpkt = 0;\n  uint32_t *d32 = (uint32_t *)usbdata;\n  for (dpkt = 0; dpkt < (len / 4); dpkt += 4) {\n    CAN_FIFOMailBox_TypeDef to_push;\n    to_push.RDHR = d32[dpkt + 3];\n    to_push.RDLR = d32[dpkt + 2];\n    to_push.RDTR = d32[dpkt + 1];\n    to_push.RIR = d32[dpkt];\n\n    uint8_t bus_number = (to_push.RDTR >> 4) & CAN_BUS_NUM_MASK;\n    can_send(&to_push, bus_number, false);\n  }\n}\n\nvoid usb_cb_ep3_out_complete(void) {\n  if (can_tx_check_min_slots_free(MAX_CAN_MSGS_PER_BULK_TRANSFER)) {\n    usb_outep3_resume_if_paused();\n  }\n}\n\nvoid usb_cb_enumeration_complete(void) {\n  puts(\"USB enumeration complete\\n\");\n  is_enumerated = 1;\n}\n\nint usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired) {\n  unsigned int resp_len = 0;\n  uart_ring *ur = NULL;\n  timestamp_t t;\n  switch (setup->b.bRequest) {\n    // **** 0xa0: get rtc time\n    case 0xa0:\n      resp_len = get_rtc_pkt(resp);\n      break;\n    // **** 0xa1: set rtc year\n    case 0xa1:\n      t = rtc_get_time();\n      t.year = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xa2: set rtc month\n    case 0xa2:\n      t = rtc_get_time();\n      t.month = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xa3: set rtc day\n    case 0xa3:\n      t = rtc_get_time();\n      t.day = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xa4: set rtc weekday\n    case 0xa4:\n      t = rtc_get_time();\n      t.weekday = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xa5: set rtc hour\n    case 0xa5:\n      t = rtc_get_time();\n      t.hour = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xa6: set rtc minute\n    case 0xa6:\n      t = rtc_get_time();\n      t.minute = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xa7: set rtc second\n    case 0xa7:\n      t = rtc_get_time();\n      t.second = setup->b.wValue.w;\n      rtc_set_time(t);\n      break;\n    // **** 0xb0: set IR power\n    case 0xb0:\n      current_board->set_ir_power(setup->b.wValue.w);\n      break;\n    // **** 0xb1: set fan power\n    case 0xb1:\n      current_board->set_fan_power(setup->b.wValue.w);\n      break;\n    // **** 0xb2: get fan rpm\n    case 0xb2:\n      resp[0] = (fan_rpm & 0x00FFU);\n      resp[1] = ((fan_rpm & 0xFF00U) >> 8U);\n      resp_len = 2;\n      break;\n    // **** 0xb3: set phone power\n    case 0xb3:\n      current_board->set_phone_power(setup->b.wValue.w > 0U);\n      break;\n    // **** 0xc0: get CAN debug info\n    case 0xc0:\n      puts(\"can tx: \"); puth(can_tx_cnt);\n      puts(\" txd: \"); puth(can_txd_cnt);\n      puts(\" rx: \"); puth(can_rx_cnt);\n      puts(\" err: \"); puth(can_err_cnt);\n      puts(\"\\n\");\n      break;\n    // **** 0xc1: get hardware type\n    case 0xc1:\n      resp[0] = hw_type;\n      resp_len = 1;\n      break;\n    // **** 0xd0: fetch serial number\n    case 0xd0:\n      // addresses are OTP\n      if (setup->b.wValue.w == 1U) {\n        (void)memcpy(resp, (uint8_t *)DEVICE_SERIAL_NUMBER_ADDRESS, 0x10);\n        resp_len = 0x10;\n      } else {\n        get_provision_chunk(resp);\n        resp_len = PROVISION_CHUNK_LEN;\n      }\n      break;\n    // **** 0xd1: enter bootloader mode\n    case 0xd1:\n      // this allows reflashing of the bootstub\n      // so it's blocked over wifi\n      switch (setup->b.wValue.w) {\n        case 0:\n          // only allow bootloader entry on debug builds\n          #ifdef ALLOW_DEBUG\n            if (hardwired) {\n              puts(\"-> entering bootloader\\n\");\n              enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;\n              NVIC_SystemReset();\n            }\n          #endif\n          break;\n        case 1:\n          puts(\"-> entering softloader\\n\");\n          enter_bootloader_mode = ENTER_SOFTLOADER_MAGIC;\n          NVIC_SystemReset();\n          break;\n        default:\n          puts(\"Bootloader mode invalid\\n\");\n          break;\n      }\n      break;\n    // **** 0xd2: get health packet\n    case 0xd2:\n      resp_len = get_health_pkt(resp);\n      break;\n    // **** 0xd3: get first 64 bytes of signature\n    case 0xd3:\n      {\n        resp_len = 64;\n        char * code = (char*)_app_start;\n        int code_len = _app_start[0];\n        (void)memcpy(resp, &code[code_len], resp_len);\n      }\n      break;\n    // **** 0xd4: get second 64 bytes of signature\n    case 0xd4:\n      {\n        resp_len = 64;\n        char * code = (char*)_app_start;\n        int code_len = _app_start[0];\n        (void)memcpy(resp, &code[code_len + 64], resp_len);\n      }\n      break;\n    // **** 0xd6: get version\n    case 0xd6:\n      COMPILE_TIME_ASSERT(sizeof(gitversion) <= MAX_RESP_LEN);\n      (void)memcpy(resp, gitversion, sizeof(gitversion));\n      resp_len = sizeof(gitversion) - 1U;\n      break;\n    // **** 0xd8: reset ST\n    case 0xd8:\n      NVIC_SystemReset();\n      break;\n    // **** 0xd9: set ESP power\n    case 0xd9:\n      if (setup->b.wValue.w == 1U) {\n        current_board->set_gps_mode(GPS_ENABLED);\n      } else if (setup->b.wValue.w == 2U) {\n        current_board->set_gps_mode(GPS_BOOTMODE);\n      } else {\n        current_board->set_gps_mode(GPS_DISABLED);\n      }\n      break;\n    // **** 0xda: reset ESP, with optional boot mode\n    case 0xda:\n      current_board->set_gps_mode(GPS_DISABLED);\n      delay(1000000);\n      if (setup->b.wValue.w == 1U) {\n        current_board->set_gps_mode(GPS_BOOTMODE);\n      } else {\n        current_board->set_gps_mode(GPS_ENABLED);\n      }\n      delay(1000000);\n      current_board->set_gps_mode(GPS_ENABLED);\n      break;\n    // **** 0xdb: set GMLAN (white/grey) or OBD CAN (black) multiplexing mode\n    case 0xdb:\n      if(current_board->has_obd){\n        if (setup->b.wValue.w == 1U) {\n          // Enable OBD CAN\n          current_board->set_can_mode(CAN_MODE_OBD_CAN2);\n        } else {\n          // Disable OBD CAN\n          current_board->set_can_mode(CAN_MODE_NORMAL);\n        }\n      } else {\n        if (setup->b.wValue.w == 1U) {\n          // GMLAN ON\n          if (setup->b.wIndex.w == 1U) {\n            can_set_gmlan(1);\n          } else if (setup->b.wIndex.w == 2U) {\n            can_set_gmlan(2);\n          } else {\n            puts(\"Invalid bus num for GMLAN CAN set\\n\");\n          }\n        } else {\n          can_set_gmlan(-1);\n        }\n      }\n      break;\n\n    // **** 0xdc: set safety mode\n    case 0xdc:\n      // Blocked over WiFi.\n      // Allow SILENT, NOOUTPUT and ELM security mode to be set over wifi.\n      if (hardwired || (setup->b.wValue.w == SAFETY_SILENT) ||\n                       (setup->b.wValue.w == SAFETY_NOOUTPUT) ||\n                       (setup->b.wValue.w == SAFETY_ELM327)) {\n        set_safety_mode(setup->b.wValue.w, (uint16_t) setup->b.wIndex.w);\n      }\n      break;\n    // **** 0xdd: enable can forwarding\n    case 0xdd:\n      // wValue = Can Bus Num to forward from\n      // wIndex = Can Bus Num to forward to\n      if ((setup->b.wValue.w < BUS_MAX) && (setup->b.wIndex.w < BUS_MAX) &&\n          (setup->b.wValue.w != setup->b.wIndex.w)) { // set forwarding\n        can_set_forwarding(setup->b.wValue.w, setup->b.wIndex.w & CAN_BUS_NUM_MASK);\n      } else if((setup->b.wValue.w < BUS_MAX) && (setup->b.wIndex.w == 0xFFU)){ //Clear Forwarding\n        can_set_forwarding(setup->b.wValue.w, -1);\n      } else {\n        puts(\"Invalid CAN bus forwarding\\n\");\n      }\n      break;\n    // **** 0xde: set can bitrate\n    case 0xde:\n      if (setup->b.wValue.w < BUS_MAX) {\n        // TODO: add sanity check, ideally check if value is correct(from array of correct values)\n        can_speed[setup->b.wValue.w] = setup->b.wIndex.w;\n        bool ret = can_init(CAN_NUM_FROM_BUS_NUM(setup->b.wValue.w));\n        UNUSED(ret);\n      }\n      break;\n    // **** 0xdf: set unsafe mode\n    case 0xdf:\n      // you can only set this if you are in a non car safety mode\n      if (!is_car_safety_mode(current_safety_mode)) {\n        unsafe_mode = setup->b.wValue.w;\n      }\n      break;\n    // **** 0xe0: uart read\n    case 0xe0:\n      ur = get_ring_by_number(setup->b.wValue.w);\n      if (!ur) {\n        break;\n      }\n\n      // TODO: Remove this again and fix boardd code to hande the message bursts instead of single chars\n      if (ur == &uart_ring_gps) {\n        dma_pointer_handler(ur, DMA2_Stream5->NDTR);\n      }\n\n      // read\n      while ((resp_len < MIN(setup->b.wLength.w, MAX_RESP_LEN)) &&\n                         getc(ur, (char*)&resp[resp_len])) {\n        ++resp_len;\n      }\n      break;\n    // **** 0xe1: uart set baud rate\n    case 0xe1:\n      ur = get_ring_by_number(setup->b.wValue.w);\n      if (!ur) {\n        break;\n      }\n      uart_set_baud(ur->uart, setup->b.wIndex.w);\n      break;\n    // **** 0xe2: uart set parity\n    case 0xe2:\n      ur = get_ring_by_number(setup->b.wValue.w);\n      if (!ur) {\n        break;\n      }\n      switch (setup->b.wIndex.w) {\n        case 0:\n          // disable parity, 8-bit\n          ur->uart->CR1 &= ~(USART_CR1_PCE | USART_CR1_M);\n          break;\n        case 1:\n          // even parity, 9-bit\n          ur->uart->CR1 &= ~USART_CR1_PS;\n          ur->uart->CR1 |= USART_CR1_PCE | USART_CR1_M;\n          break;\n        case 2:\n          // odd parity, 9-bit\n          ur->uart->CR1 |= USART_CR1_PS;\n          ur->uart->CR1 |= USART_CR1_PCE | USART_CR1_M;\n          break;\n        default:\n          break;\n      }\n      break;\n    // **** 0xe4: uart set baud rate extended\n    case 0xe4:\n      ur = get_ring_by_number(setup->b.wValue.w);\n      if (!ur) {\n        break;\n      }\n      uart_set_baud(ur->uart, (int)setup->b.wIndex.w*300);\n      break;\n    // **** 0xe5: set CAN loopback (for testing)\n    case 0xe5:\n      can_loopback = (setup->b.wValue.w > 0U);\n      can_init_all();\n      break;\n    // **** 0xe6: set USB power\n    case 0xe6:\n      current_board->set_usb_power_mode(setup->b.wValue.w);\n      break;\n    // **** 0xe7: set power save state\n    case 0xe7:\n      set_power_save_state(setup->b.wValue.w);\n      break;\n    // **** 0xf0: k-line/l-line wake-up pulse for KWP2000 fast initialization\n    case 0xf0:\n      if(current_board->has_lin) {\n        bool k = (setup->b.wValue.w == 0U) || (setup->b.wValue.w == 2U);\n        bool l = (setup->b.wValue.w == 1U) || (setup->b.wValue.w == 2U);\n        if (bitbang_wakeup(k, l)) {\n          resp_len = -1; // do not clear NAK yet (wait for bit banging to finish)\n        }\n      }\n      break;\n    // **** 0xf1: Clear CAN ring buffer.\n    case 0xf1:\n      if (setup->b.wValue.w == 0xFFFFU) {\n        puts(\"Clearing CAN Rx queue\\n\");\n        can_clear(&can_rx_q);\n      } else if (setup->b.wValue.w < BUS_MAX) {\n        puts(\"Clearing CAN Tx queue\\n\");\n        can_clear(can_queues[setup->b.wValue.w]);\n      } else {\n        puts(\"Clearing CAN CAN ring buffer failed: wrong bus number\\n\");\n      }\n      break;\n    // **** 0xf2: Clear UART ring buffer.\n    case 0xf2:\n      {\n        uart_ring * rb = get_ring_by_number(setup->b.wValue.w);\n        if (rb != NULL) {\n          puts(\"Clearing UART queue.\\n\");\n          clear_uart_buff(rb);\n        }\n        break;\n      }\n    // **** 0xf3: Heartbeat. Resets heartbeat counter.\n    case 0xf3:\n      {\n        heartbeat_counter = 0U;\n        heartbeat_lost = false;\n        heartbeat_disabled = false;\n        break;\n      }\n    // **** 0xf4: k-line/l-line 5 baud initialization\n    case 0xf4:\n      if(current_board->has_lin) {\n        bool k = (setup->b.wValue.w == 0U) || (setup->b.wValue.w == 2U);\n        bool l = (setup->b.wValue.w == 1U) || (setup->b.wValue.w == 2U);\n        uint8_t five_baud_addr = (setup->b.wIndex.w & 0xFFU);\n        if (bitbang_five_baud_addr(k, l, five_baud_addr)) {\n          resp_len = -1; // do not clear NAK yet (wait for bit banging to finish)\n        }\n      }\n      break;\n    // **** 0xf5: set clock source mode\n    case 0xf5:\n      current_board->set_clock_source_mode(setup->b.wValue.w);\n      break;\n    // **** 0xf6: set siren enabled\n    case 0xf6:\n      siren_enabled = (setup->b.wValue.w != 0U);\n      break;\n    // **** 0xf7: set green led enabled\n    case 0xf7:\n      green_led_enabled = (setup->b.wValue.w != 0U);\n      break;\n#ifdef ALLOW_DEBUG\n    // **** 0xf8: disable heartbeat checks\n    case 0xf8:\n      heartbeat_disabled = true;\n      break;\n#endif\n    // **** 0xde: set CAN FD data bitrate\n    case 0xf9:\n      if (setup->b.wValue.w < CAN_MAX) {\n        // TODO: add sanity check, ideally check if value is correct(from array of correct values)\n        can_data_speed[setup->b.wValue.w] = setup->b.wIndex.w;\n        bool ret = can_init(CAN_NUM_FROM_BUS_NUM(setup->b.wValue.w));\n        UNUSED(ret);\n      }\n      break;\n    default:\n      puts(\"NO HANDLER \");\n      puth(setup->b.bRequest);\n      puts(\"\\n\");\n      break;\n  }\n  return resp_len;\n}\n\n// ***************************** main code *****************************\n\n// cppcheck-suppress unusedFunction ; used in headers not included in cppcheck\nvoid __initialize_hardware_early(void) {\n  early_initialization();\n}\n\nvoid __attribute__ ((noinline)) enable_fpu(void) {\n  // enable the FPU\n  SCB->CPACR |= ((3UL << (10U * 2U)) | (3UL << (11U * 2U)));\n}\n\n// go into SILENT when heartbeat isn't received for this amount of seconds.\n#define HEARTBEAT_IGNITION_CNT_ON 5U\n#define HEARTBEAT_IGNITION_CNT_OFF 2U\n\n// called at 8Hz\nuint8_t loop_counter = 0U;\nvoid tick_handler(void) {\n  if (TICK_TIMER->SR != 0) {\n    // siren\n    current_board->set_siren((loop_counter & 1U) && (siren_enabled || (siren_countdown > 0U)));\n\n    // decimated to 1Hz\n    if (loop_counter == 0U) {\n      can_live = pending_can_live;\n\n      current_board->usb_power_mode_tick(uptime_cnt);\n\n      //puth(usart1_dma); puts(\" \"); puth(DMA2_Stream5->M0AR); puts(\" \"); puth(DMA2_Stream5->NDTR); puts(\"\\n\");\n\n      // reset this every 16th pass\n      if ((uptime_cnt & 0xFU) == 0U) {\n        pending_can_live = 0;\n      }\n      #ifdef DEBUG\n        puts(\"** blink \");\n        puth(can_rx_q.r_ptr); puts(\" \"); puth(can_rx_q.w_ptr); puts(\"  \");\n        puth(can_tx1_q.r_ptr); puts(\" \"); puth(can_tx1_q.w_ptr); puts(\"  \");\n        puth(can_tx2_q.r_ptr); puts(\" \"); puth(can_tx2_q.w_ptr); puts(\"\\n\");\n      #endif\n\n      // Tick drivers\n      fan_tick();\n\n      // set green LED to be controls allowed\n      current_board->set_led(LED_GREEN, controls_allowed | green_led_enabled);\n\n      // turn off the blue LED, turned on by CAN\n      // unless we are in power saving mode\n      current_board->set_led(LED_BLUE, (uptime_cnt & 1U) && (power_save_status == POWER_SAVE_STATUS_ENABLED));\n\n      // increase heartbeat counter and cap it at the uint32 limit\n      if (heartbeat_counter < __UINT32_MAX__) {\n        heartbeat_counter += 1U;\n      }\n\n      if (siren_countdown > 0U) {\n        siren_countdown -= 1U;\n      }\n\n      if (controls_allowed) {\n        controls_allowed_countdown = 30U;\n      } else if (controls_allowed_countdown > 0U) {\n        controls_allowed_countdown -= 1U;\n      } else {\n\n      }\n\n      if (!heartbeat_disabled) {\n        // if the heartbeat has been gone for a while, go to SILENT safety mode and enter power save\n        if (heartbeat_counter >= (check_started() ? HEARTBEAT_IGNITION_CNT_ON : HEARTBEAT_IGNITION_CNT_OFF)) {\n          puts(\"device hasn't sent a heartbeat for 0x\");\n          puth(heartbeat_counter);\n          puts(\" seconds. Safety is set to SILENT mode.\\n\");\n\n          if (controls_allowed_countdown > 0U) {\n            siren_countdown = 5U;\n            controls_allowed_countdown = 0U;\n          }\n\n          // set flag to indicate the heartbeat was lost\n          if (is_car_safety_mode(current_safety_mode)) {\n            heartbeat_lost = true;\n          }\n\n          if (current_safety_mode != SAFETY_SILENT) {\n            set_safety_mode(SAFETY_SILENT, 0U);\n          }\n          if (power_save_status != POWER_SAVE_STATUS_ENABLED) {\n            set_power_save_state(POWER_SAVE_STATUS_ENABLED);\n          }\n\n          // Also disable IR when the heartbeat goes missing\n          current_board->set_ir_power(0U);\n\n          // If enumerated but no heartbeat (phone up, boardd not running), turn the fan on to cool the device\n          if(usb_enumerated()){\n            current_board->set_fan_power(50U);\n          } else {\n            current_board->set_fan_power(0U);\n          }\n        }\n\n        // enter CDP mode when car starts to ensure we are charging a turned off EON\n        if (check_started() && (usb_power_mode != USB_POWER_CDP)) {\n          current_board->set_usb_power_mode(USB_POWER_CDP);\n        }\n      }\n\n      // check registers\n      check_registers();\n\n      // set ignition_can to false after 2s of no CAN seen\n      if (ignition_can_cnt > 2U) {\n        ignition_can = false;\n      }\n\n      // on to the next one\n      uptime_cnt += 1U;\n      safety_mode_cnt += 1U;\n      ignition_can_cnt += 1U;\n\n      // synchronous safety check\n      safety_tick(current_rx_checks);\n    }\n\n    loop_counter++;\n    loop_counter %= 8U;\n  }\n  TICK_TIMER->SR = 0;\n}\n\n\nint main(void) {\n  // Init interrupt table\n  init_interrupts(true);\n\n  // shouldn't have interrupts here, but just in case\n  disable_interrupts();\n\n  // init early devices\n  clock_init();\n  peripherals_init();\n  detect_external_debug_serial();\n  detect_board_type();\n  adc_init();\n\n  // print hello\n  puts(\"\\n\\n\\n************************ MAIN START ************************\\n\");\n\n  // check for non-supported board types\n  if(hw_type == HW_TYPE_UNKNOWN){\n    puts(\"Unsupported board type\\n\");\n    while (1) { /* hang */ }\n  }\n\n  puts(\"Config:\\n\");\n  puts(\"  Board type: \"); puts(current_board->board_type); puts(\"\\n\");\n  puts(has_external_debug_serial ? \"  Real serial\\n\" : \"  USB serial\\n\");\n\n  // init board\n  current_board->init();\n\n  // panda has an FPU, let's use it!\n  enable_fpu();\n\n  // enable main uart if it's connected\n  if (has_external_debug_serial) {\n    // WEIRDNESS: without this gate around the UART, it would \"crash\", but only if the ESP is enabled\n    // assuming it's because the lines were left floating and spurious noise was on them\n    uart_init(&uart_ring_debug, 115200);\n  }\n\n  if (current_board->has_gps) {\n    uart_init(&uart_ring_gps, 9600);\n  } else {\n    // enable ESP uart\n    uart_init(&uart_ring_gps, 115200);\n  }\n\n  if(current_board->has_lin){\n    // enable LIN\n    uart_init(&uart_ring_lin1, 10400);\n    UART5->CR2 |= USART_CR2_LINEN;\n    uart_init(&uart_ring_lin2, 10400);\n    USART3->CR2 |= USART_CR2_LINEN;\n  }\n\n  microsecond_timer_init();\n\n  // init to SILENT and can silent\n  set_safety_mode(SAFETY_SILENT, 0);\n\n  // enable CAN TXs\n  current_board->enable_can_transceivers(true);\n\n  // 8Hz timer\n  REGISTER_INTERRUPT(TICK_TIMER_IRQ, tick_handler, 10U, FAULT_INTERRUPT_RATE_TICK)\n  tick_timer_init();\n\n#ifdef DEBUG\n  puts(\"DEBUG ENABLED\\n\");\n#endif\n  // enable USB (right before interrupts or enum can fail!)\n  usb_init();\n\n  puts(\"**** INTERRUPTS ON ****\\n\");\n  enable_interrupts();\n\n  // LED should keep on blinking all the time\n  uint64_t cnt = 0;\n\n  for (cnt=0;;cnt++) {\n    if (power_save_status == POWER_SAVE_STATUS_DISABLED) {\n      #ifdef DEBUG_FAULTS\n      if(fault_status == FAULT_STATUS_NONE){\n      #endif\n        uint32_t div_mode = ((usb_power_mode == USB_POWER_DCP) ? 4U : 1U);\n\n        // useful for debugging, fade breaks = panda is overloaded\n        for(uint32_t fade = 0U; fade < MAX_LED_FADE; fade += div_mode){\n          current_board->set_led(LED_RED, true);\n          delay(fade >> 4);\n          current_board->set_led(LED_RED, false);\n          delay((MAX_LED_FADE - fade) >> 4);\n        }\n\n        for(uint32_t fade = MAX_LED_FADE; fade > 0U; fade -= div_mode){\n          current_board->set_led(LED_RED, true);\n          delay(fade >> 4);\n          current_board->set_led(LED_RED, false);\n          delay((MAX_LED_FADE - fade) >> 4);\n        }\n\n      #ifdef DEBUG_FAULTS\n      } else {\n          current_board->set_led(LED_RED, 1);\n          delay(512000U);\n          current_board->set_led(LED_RED, 0);\n          delay(512000U);\n        }\n      #endif\n    } else {\n      __WFI();\n    }\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "panda/board/main_declarations.h",
    "content": "// ******************** Prototypes ********************\nvoid puts(const char *a);\nvoid puth(unsigned int i);\nvoid puth2(unsigned int i);\ntypedef struct board board;\ntypedef struct harness_configuration harness_configuration;\nvoid can_flip_buses(uint8_t bus1, uint8_t bus2);\nvoid pwm_init(TIM_TypeDef *TIM, uint8_t channel);\nvoid pwm_set(TIM_TypeDef *TIM, uint8_t channel, uint8_t percentage);\n\n// ********************* Globals **********************\nuint8_t hw_type = 0;\nconst board *current_board;\nbool is_enumerated = 0;\nuint32_t uptime_cnt = 0;\nbool green_led_enabled = false;\n\n// heartbeat state\nuint32_t heartbeat_counter = 0;\nbool heartbeat_lost = false;\nbool heartbeat_disabled = false; // set over USB\n\n// siren state\nbool siren_enabled = false;\nuint32_t siren_countdown = 0; // siren plays while countdown > 0\nuint32_t controls_allowed_countdown = 0;\n\n"
  },
  {
    "path": "panda/board/obj/.placeholder",
    "content": ""
  },
  {
    "path": "panda/board/pedal/.gitignore",
    "content": "obj/*\n"
  },
  {
    "path": "panda/board/pedal/README",
    "content": "This is the firmware for the comma pedal. It borrows a lot from panda.\n\nThe comma pedal is a gas pedal interceptor for Honda/Acura. It allows you to \"virtually\" press the pedal.\n\nThis is the open source software. Note that it is not ready to use yet.\n\n== Test Plan ==\n\n* Startup\n** Confirm STATE_FAULT_STARTUP\n* Timeout\n** Send value\n** Confirm value is output\n** Stop sending messages\n** Confirm value is passthru after 100ms\n** Confirm STATE_FAULT_TIMEOUT\n* Random values\n** Send random 6 byte messages\n** Confirm random values cause passthru\n** Confirm STATE_FAULT_BAD_CHECKSUM\n* Same message lockout\n** Send same message repeated\n** Confirm timeout behavior\n* Don't set enable\n** Confirm no output\n* Set enable and values\n** Confirm output\n\n"
  },
  {
    "path": "panda/board/pedal/flash_can.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\ncd ..\nPEDAL=1 scons -u\ncd pedal\n\n../../tests/pedal/enter_canloader.py ../obj/pedal.bin.signed\n"
  },
  {
    "path": "panda/board/pedal/main.c",
    "content": "// ********************* Includes *********************\n//#define PEDAL_USB\n#include \"../config.h\"\n\n#include \"early_init.h\"\n#include \"crc.h\"\n\n#define CAN CAN1\n\n#ifdef PEDAL_USB\n  #include \"drivers/usb.h\"\n#else\n  // no serial either\n  void puts(const char *a) {\n    UNUSED(a);\n  }\n  void puth(unsigned int i) {\n    UNUSED(i);\n  }\n  void puth2(unsigned int i) {\n    UNUSED(i);\n  }\n#endif\n\n#define ENTER_BOOTLOADER_MAGIC 0xdeadbeefU\nuint32_t enter_bootloader_mode;\n\n// cppcheck-suppress unusedFunction ; used in headers not included in cppcheck\nvoid __initialize_hardware_early(void) {\n  early_initialization();\n}\n\n// ********************* serial debugging *********************\n\n#ifdef PEDAL_USB\n\nvoid debug_ring_callback(uart_ring *ring) {\n  char rcv;\n  while (getc(ring, &rcv) != 0) {\n    (void)putc(ring, rcv);\n  }\n}\n\nint usb_cb_ep1_in(void *usbdata, int len, bool hardwired) {\n  UNUSED(usbdata);\n  UNUSED(len);\n  UNUSED(hardwired);\n  return 0;\n}\nvoid usb_cb_ep2_out(void *usbdata, int len, bool hardwired) {\n  UNUSED(usbdata);\n  UNUSED(len);\n  UNUSED(hardwired);\n}\nvoid usb_cb_ep3_out(void *usbdata, int len, bool hardwired) {\n  UNUSED(usbdata);\n  UNUSED(len);\n  UNUSED(hardwired);\n}\nvoid usb_cb_ep3_out_complete(void) {}\nvoid usb_cb_enumeration_complete(void) {}\n\nint usb_cb_control_msg(USB_Setup_TypeDef *setup, uint8_t *resp, bool hardwired) {\n  UNUSED(hardwired);\n  unsigned int resp_len = 0;\n  uart_ring *ur = NULL;\n  switch (setup->b.bRequest) {\n    // **** 0xc1: get hardware type\n    case 0xc1:\n      resp[0] = hw_type;\n      resp_len = 1;\n      break;\n    // **** 0xe0: uart read\n    case 0xe0:\n      ur = get_ring_by_number(setup->b.wValue.w);\n      if (!ur) {\n        break;\n      }\n      // read\n      while ((resp_len < MIN(setup->b.wLength.w, MAX_RESP_LEN)) &&\n                         getc(ur, (char*)&resp[resp_len])) {\n        ++resp_len;\n      }\n      break;\n    default:\n      puts(\"NO HANDLER \");\n      puth(setup->b.bRequest);\n      puts(\"\\n\");\n      break;\n  }\n  return resp_len;\n}\n\n#endif\n\n// ***************************** can port *****************************\n\n// addresses to be used on CAN\n#define CAN_GAS_INPUT  0x200\n#define CAN_GAS_OUTPUT 0x201U\n#define CAN_GAS_SIZE 6\n#define COUNTER_CYCLE 0xFU\n\nvoid CAN1_TX_IRQ_Handler(void) {\n  // clear interrupt\n  CAN->TSR |= CAN_TSR_RQCP0;\n}\n\n// two independent values\nuint16_t gas_set_0 = 0;\nuint16_t gas_set_1 = 0;\n\n#define MAX_TIMEOUT 10U\nuint32_t timeout = 0;\nuint32_t current_index = 0;\n\n#define NO_FAULT 0U\n#define FAULT_BAD_CHECKSUM 1U\n#define FAULT_SEND 2U\n#define FAULT_SCE 3U\n#define FAULT_STARTUP 4U\n#define FAULT_TIMEOUT 5U\n#define FAULT_INVALID 6U\nuint8_t state = FAULT_STARTUP;\nconst uint8_t crc_poly = 0xD5U;  // standard crc8\n\nvoid CAN1_RX0_IRQ_Handler(void) {\n  while ((CAN->RF0R & CAN_RF0R_FMP0) != 0) {\n    #ifdef DEBUG\n      puts(\"CAN RX\\n\");\n    #endif\n    int address = CAN->sFIFOMailBox[0].RIR >> 21;\n    if (address == CAN_GAS_INPUT) {\n      // softloader entry\n      if (GET_BYTES_04(&CAN->sFIFOMailBox[0]) == 0xdeadface) {\n        if (GET_BYTES_48(&CAN->sFIFOMailBox[0]) == 0x0ab00b1e) {\n          enter_bootloader_mode = ENTER_SOFTLOADER_MAGIC;\n          NVIC_SystemReset();\n        } else if (GET_BYTES_48(&CAN->sFIFOMailBox[0]) == 0x02b00b1e) {\n          enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;\n          NVIC_SystemReset();\n        } else {\n          puts(\"Failed entering Softloader or Bootloader\\n\");\n        }\n      }\n\n      // normal packet\n      uint8_t dat[8];\n      for (int i=0; i<8; i++) {\n        dat[i] = GET_BYTE(&CAN->sFIFOMailBox[0], i);\n      }\n      uint16_t value_0 = (dat[0] << 8) | dat[1];\n      uint16_t value_1 = (dat[2] << 8) | dat[3];\n      bool enable = ((dat[4] >> 7) & 1U) != 0U;\n      uint8_t index = dat[4] & COUNTER_CYCLE;\n      if (crc_checksum(dat, CAN_GAS_SIZE - 1, crc_poly) == dat[5]) {\n        if (((current_index + 1U) & COUNTER_CYCLE) == index) {\n          #ifdef DEBUG\n            puts(\"setting gas \");\n            puth(value_0);\n            puts(\"\\n\");\n          #endif\n          if (enable) {\n            gas_set_0 = value_0;\n            gas_set_1 = value_1;\n          } else {\n            // clear the fault state if values are 0\n            if ((value_0 == 0U) && (value_1 == 0U)) {\n              state = NO_FAULT;\n            } else {\n              state = FAULT_INVALID;\n            }\n            gas_set_0 = 0;\n            gas_set_1 = 0;\n          }\n          // clear the timeout\n          timeout = 0;\n        }\n        current_index = index;\n      } else {\n        // wrong checksum = fault\n        state = FAULT_BAD_CHECKSUM;\n      }\n    }\n    // next\n    CAN->RF0R |= CAN_RF0R_RFOM0;\n  }\n}\n\nvoid CAN1_SCE_IRQ_Handler(void) {\n  state = FAULT_SCE;\n  llcan_clear_send(CAN);\n}\n\nuint32_t pdl0 = 0;\nuint32_t pdl1 = 0;\nunsigned int pkt_idx = 0;\n\nint led_value = 0;\n\nvoid TIM3_IRQ_Handler(void) {\n  #ifdef DEBUG\n    puth(TIM3->CNT);\n    puts(\" \");\n    puth(pdl0);\n    puts(\" \");\n    puth(pdl1);\n    puts(\"\\n\");\n  #endif\n\n  // check timer for sending the user pedal and clearing the CAN\n  if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {\n    uint8_t dat[8];\n    dat[0] = (pdl0 >> 8) & 0xFFU;\n    dat[1] = (pdl0 >> 0) & 0xFFU;\n    dat[2] = (pdl1 >> 8) & 0xFFU;\n    dat[3] = (pdl1 >> 0) & 0xFFU;\n    dat[4] = ((state & 0xFU) << 4) | pkt_idx;\n    dat[5] = crc_checksum(dat, CAN_GAS_SIZE - 1, crc_poly);\n    CAN->sTxMailBox[0].TDLR = dat[0] | (dat[1] << 8) | (dat[2] << 16) | (dat[3] << 24);\n    CAN->sTxMailBox[0].TDHR = dat[4] | (dat[5] << 8);\n    CAN->sTxMailBox[0].TDTR = 6;  // len of packet is 5\n    CAN->sTxMailBox[0].TIR = (CAN_GAS_OUTPUT << 21) | 1U;\n    ++pkt_idx;\n    pkt_idx &= COUNTER_CYCLE;\n  } else {\n    // old can packet hasn't sent!\n    state = FAULT_SEND;\n    #ifdef DEBUG\n      puts(\"CAN MISS\\n\");\n    #endif\n  }\n\n  // blink the LED\n  current_board->set_led(LED_GREEN, led_value);\n  led_value = !led_value;\n\n  TIM3->SR = 0;\n\n  // up timeout for gas set\n  if (timeout == MAX_TIMEOUT) {\n    state = FAULT_TIMEOUT;\n  } else {\n    timeout += 1U;\n  }\n}\n\n// ***************************** main code *****************************\n\nvoid pedal(void) {\n  // read/write\n  pdl0 = adc_get(ADCCHAN_ACCEL0);\n  pdl1 = adc_get(ADCCHAN_ACCEL1);\n\n  // write the pedal to the DAC\n  if (state == NO_FAULT) {\n    dac_set(0, MAX(gas_set_0, pdl0));\n    dac_set(1, MAX(gas_set_1, pdl1));\n  } else {\n    dac_set(0, pdl0);\n    dac_set(1, pdl1);\n  }\n\n  watchdog_feed();\n}\n\nint main(void) {\n  // Init interrupt table\n  init_interrupts(true);\n\n  REGISTER_INTERRUPT(CAN1_TX_IRQn, CAN1_TX_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(CAN1_RX0_IRQn, CAN1_RX0_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  REGISTER_INTERRUPT(CAN1_SCE_IRQn, CAN1_SCE_IRQ_Handler, CAN_INTERRUPT_RATE, FAULT_INTERRUPT_RATE_CAN_1)\n  \n  // Should run at around 732Hz (see init below)\n  REGISTER_INTERRUPT(TIM3_IRQn, TIM3_IRQ_Handler, 1000U, FAULT_INTERRUPT_RATE_TIM3)\n\n  disable_interrupts();\n\n  // init devices\n  clock_init();\n  peripherals_init();\n  detect_external_debug_serial();\n  detect_board_type();\n\n  // init board\n  current_board->init();\n\n#ifdef PEDAL_USB\n  // enable USB\n  usb_init();\n#endif\n\n  // pedal stuff\n  dac_init();\n  adc_init();\n\n  // init can\n  bool llcan_speed_set = llcan_set_speed(CAN1, 5000, false, false);\n  if (!llcan_speed_set) {\n    puts(\"Failed to set llcan speed\");\n  }\n\n  bool ret = llcan_init(CAN1);\n  UNUSED(ret);\n\n  // 48mhz / 65536 ~= 732\n  timer_init(TIM3, 15);\n  NVIC_EnableIRQ(TIM3_IRQn);\n\n  watchdog_init();\n\n  puts(\"**** INTERRUPTS ON ****\\n\");\n  enable_interrupts();\n\n  // main pedal loop\n  while (1) {\n    pedal();\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "panda/board/pedal/main_declarations.h",
    "content": "// ******************** Prototypes ********************\nvoid puts(const char *a);\nvoid puth(unsigned int i);\nvoid puth2(unsigned int i);\ntypedef struct board board;\ntypedef struct harness_configuration harness_configuration;\n\n// ********************* Globals **********************\nuint8_t hw_type = 0;\nconst board *current_board;\nbool is_enumerated = 0;\n"
  },
  {
    "path": "panda/board/pedal/recover.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\nDFU_UTIL=\"dfu-util\"\n\ncd ..\nPEDAL=1 scons -u\ncd pedal\n\n$DFU_UTIL -d 0483:df11 -a 0 -s 0x08004000 -D ../obj/pedal.bin.signed\n$DFU_UTIL -d 0483:df11 -a 0 -s 0x08000000:leave -D ../obj/bootstub.pedal.bin\n"
  },
  {
    "path": "panda/board/power_saving.h",
    "content": "// WARNING: To stay in compliance with the SIL2 rules laid out in STM UM1840, we should never implement any of the available hardware low power modes.\n// See rule: CoU_3\n\n#define POWER_SAVE_STATUS_DISABLED 0\n#define POWER_SAVE_STATUS_ENABLED 1\n\nint power_save_status = POWER_SAVE_STATUS_DISABLED;\n\nvoid set_power_save_state(int state) {\n\n  bool is_valid_state = (state == POWER_SAVE_STATUS_ENABLED) || (state == POWER_SAVE_STATUS_DISABLED);\n  if (is_valid_state && (state != power_save_status)) {\n    bool enable = false;\n    if (state == POWER_SAVE_STATUS_ENABLED) {\n      puts(\"enable power savings\\n\");\n      if (current_board->has_gps) {\n        const char UBLOX_SLEEP_MSG[] = \"\\xb5\\x62\\x06\\x04\\x04\\x00\\x01\\x00\\x08\\x00\\x17\\x78\";\n        uart_ring *ur = get_ring_by_number(1);\n        for (unsigned int i = 0; i < sizeof(UBLOX_SLEEP_MSG) - 1U; i++) while (!putc(ur, UBLOX_SLEEP_MSG[i]));\n      }\n    } else {\n      puts(\"disable power savings\\n\");\n      if (current_board->has_gps) {\n        const char UBLOX_WAKE_MSG[] = \"\\xb5\\x62\\x06\\x04\\x04\\x00\\x01\\x00\\x09\\x00\\x18\\x7a\";\n        uart_ring *ur = get_ring_by_number(1);\n        for (unsigned int i = 0; i < sizeof(UBLOX_WAKE_MSG) - 1U; i++) while (!putc(ur, UBLOX_WAKE_MSG[i]));\n      }\n      enable = true;\n    }\n\n    #ifdef vw\n    // Volkswagen community port:\n    // If this is a White or Grey Panda, always keep the CAN transceivers\n    // powered up so that transparent forwarding is maintained.\n    current_board->enable_can_transceivers(current_board->has_obd ? enable : true);\n    #else\n    current_board->enable_can_transceivers(enable);\n    #endif\n\n    // Switch EPS/GPS\n    if (enable) {\n      current_board->set_gps_mode(GPS_ENABLED);\n    } else {\n      current_board->set_gps_mode(GPS_DISABLED);\n    }\n\n    if(current_board->has_hw_gmlan){\n      // turn on GMLAN\n      set_gpio_output(GPIOB, 14, enable);\n      set_gpio_output(GPIOB, 15, enable);\n    }\n\n    if(current_board->has_lin){\n      // turn on LIN\n      set_gpio_output(GPIOB, 7, enable);\n      set_gpio_output(GPIOA, 14, enable);\n    }\n\n    // Switch off IR when in power saving\n    if(!enable){\n      current_board->set_ir_power(0U);\n    }\n\n    power_save_status = state;\n  }\n}\n"
  },
  {
    "path": "panda/board/provision.h",
    "content": "#define PROVISION_CHUNK_LEN 0x20\n\n// WiFi SSID     = 0x0  - 0x10\n// WiFi password = 0x10 - 0x1C\n// SHA1 checksum = 0x1C - 0x20\n\nvoid get_provision_chunk(uint8_t *resp) {\n  (void)memcpy(resp, (uint8_t *)PROVISION_CHUNK_ADDRESS, PROVISION_CHUNK_LEN);\n  if (memcmp(resp, \"\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\", 0x20) == 0) {\n    (void)memcpy(resp, \"unprovisioned\\x00\\x00\\x00testing123\\x00\\x00\\xa3\\xa6\\x99\\xec\", 0x20);\n  }\n}\n\nuint8_t chunk[PROVISION_CHUNK_LEN];\nbool is_provisioned(void) {\n  (void)memcpy(chunk, (uint8_t *)PROVISION_CHUNK_ADDRESS, PROVISION_CHUNK_LEN);\n  return (memcmp(chunk, \"\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\", 0x20) != 0);\n}\n"
  },
  {
    "path": "panda/board/recover.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\nDFU_UTIL=\"dfu-util\"\n\nscons -u\n\nPYTHONPATH=.. python3 -c \"from python import Panda; Panda().reset(enter_bootstub=True); Panda().reset(enter_bootloader=True)\" || true\nsleep 1\n$DFU_UTIL -d 0483:df11 -a 0 -s 0x08004000 -D obj/panda.bin.signed\n$DFU_UTIL -d 0483:df11 -a 0 -s 0x08000000:leave -D obj/bootstub.panda.bin\n"
  },
  {
    "path": "panda/board/recover_h7.sh",
    "content": "#!/usr/bin/env sh\nset -e\n\nDFU_UTIL=\"dfu-util\"\n\nPANDA_H7=1 scons -u\n\nPYTHONPATH=.. python3 -c \"from python import Panda; Panda().reset(enter_bootstub=True); Panda().reset(enter_bootloader=True)\" || true\nsleep 1\n$DFU_UTIL -d 0483:df11 -a 0 -s 0x08020000 -D obj/panda_h7.bin.signed\n$DFU_UTIL -d 0483:df11 -a 0 -s 0x08000000:leave -D obj/bootstub.panda_h7.bin\n"
  },
  {
    "path": "panda/board/safety/safety_chrysler.h",
    "content": "const int CHRYSLER_MAX_STEER = 261;\nconst int CHRYSLER_MAX_RT_DELTA = 112;        // max delta torque allowed for real time checks\nconst uint32_t CHRYSLER_RT_INTERVAL = 250000;  // 250ms between real time checks\nconst int CHRYSLER_MAX_RATE_UP = 3;\nconst int CHRYSLER_MAX_RATE_DOWN = 3;\nconst int CHRYSLER_MAX_TORQUE_ERROR = 80;    // max torque cmd in excess of torque motor\nconst int CHRYSLER_GAS_THRSLD = 30;  // 7% more than 2m/s\nconst int CHRYSLER_STANDSTILL_THRSLD = 10;  // about 1m/s\nconst CanMsg CHRYSLER_TX_MSGS[] = {{571, 0, 3}, {658, 0, 6}, {678, 0, 8}};\n\nAddrCheckStruct chrysler_addr_checks[] = {\n  {.msg = {{544, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{514, 0, 8, .check_checksum = false, .max_counter = 0U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{500, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{308, 0, 8, .check_checksum = false, .max_counter = 15U,  .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{320, 0, 8, .check_checksum = true, .max_counter = 15U,  .expected_timestep = 20000U}, { 0 }, { 0 }}},\n};\n#define CHRYSLER_ADDR_CHECK_LEN (sizeof(chrysler_addr_checks) / sizeof(chrysler_addr_checks[0]))\naddr_checks chrysler_rx_checks = {chrysler_addr_checks, CHRYSLER_ADDR_CHECK_LEN};\n\nstatic uint8_t chrysler_get_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int checksum_byte = GET_LEN(to_push) - 1;\n  return (uint8_t)(GET_BYTE(to_push, checksum_byte));\n}\n\nstatic uint8_t chrysler_compute_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  /* This function does not want the checksum byte in the input data.\n  jeep chrysler canbus checksum from http://illmatics.com/Remote%20Car%20Hacking.pdf */\n  uint8_t checksum = 0xFFU;\n  int len = GET_LEN(to_push);\n  for (int j = 0; j < (len - 1); j++) {\n    uint8_t shift = 0x80U;\n    uint8_t curr = (uint8_t)GET_BYTE(to_push, j);\n    for (int i=0; i<8; i++) {\n      uint8_t bit_sum = curr & shift;\n      uint8_t temp_chk = checksum & 0x80U;\n      if (bit_sum != 0U) {\n        bit_sum = 0x1C;\n        if (temp_chk != 0U) {\n          bit_sum = 1;\n        }\n        checksum = checksum << 1;\n        temp_chk = checksum | 1U;\n        bit_sum ^= temp_chk;\n      } else {\n        if (temp_chk != 0U) {\n          bit_sum = 0x1D;\n        }\n        checksum = checksum << 1;\n        bit_sum ^= checksum;\n      }\n      checksum = bit_sum;\n      shift = shift >> 1;\n    }\n  }\n  return ~checksum;\n}\n\nstatic uint8_t chrysler_get_counter(CAN_FIFOMailBox_TypeDef *to_push) {\n  // Well defined counter only for 8 bytes messages\n  return (uint8_t)(GET_BYTE(to_push, 6) >> 4);\n}\n\nstatic int chrysler_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &chrysler_rx_checks,\n                                 chrysler_get_checksum, chrysler_compute_checksum,\n                                 chrysler_get_counter);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n\n    // Measured eps torque\n    if (addr == 544) {\n      int torque_meas_new = ((GET_BYTE(to_push, 4) & 0x7U) << 8) + GET_BYTE(to_push, 5) - 1024U;\n\n      // update array of samples\n      update_sample(&torque_meas, torque_meas_new);\n    }\n\n    // enter controls on rising edge of ACC, exit controls on ACC off\n    if (addr == 500) {\n      int cruise_engaged = ((GET_BYTE(to_push, 2) & 0x38) >> 3) == 7;\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    // update speed\n    if (addr == 514) {\n      int speed_l = (GET_BYTE(to_push, 0) << 4) + (GET_BYTE(to_push, 1) >> 4);\n      int speed_r = (GET_BYTE(to_push, 2) << 4) + (GET_BYTE(to_push, 3) >> 4);\n      vehicle_speed = (speed_l + speed_r) / 2;\n      vehicle_moving = (int)vehicle_speed > CHRYSLER_STANDSTILL_THRSLD;\n    }\n\n    // exit controls on rising edge of gas press\n    if (addr == 308) {\n      gas_pressed = ((GET_BYTE(to_push, 5) & 0x7F) != 0) && ((int)vehicle_speed > CHRYSLER_GAS_THRSLD);\n    }\n\n    // exit controls on rising edge of brake press\n    if (addr == 320) {\n      brake_pressed = (GET_BYTE(to_push, 0) & 0x7) == 5;\n      if (brake_pressed && (!brake_pressed_prev || vehicle_moving)) {\n        controls_allowed = 0;\n      }\n      brake_pressed_prev = brake_pressed;\n    }\n\n    generic_rx_checks((addr == 0x292));\n  }\n  return valid;\n}\n\nstatic int chrysler_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n\n  if (!msg_allowed(to_send, CHRYSLER_TX_MSGS, sizeof(CHRYSLER_TX_MSGS) / sizeof(CHRYSLER_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // LKA STEER\n  if (addr == 0x292) {\n    int desired_torque = ((GET_BYTE(to_send, 0) & 0x7U) << 8) + GET_BYTE(to_send, 1) - 1024U;\n    uint32_t ts = microsecond_timer_get();\n    bool violation = 0;\n\n    if (controls_allowed) {\n\n      // *** global torque limit check ***\n      violation |= max_limit_check(desired_torque, CHRYSLER_MAX_STEER, -CHRYSLER_MAX_STEER);\n\n      // *** torque rate limit check ***\n      violation |= dist_to_meas_check(desired_torque, desired_torque_last,\n        &torque_meas, CHRYSLER_MAX_RATE_UP, CHRYSLER_MAX_RATE_DOWN, CHRYSLER_MAX_TORQUE_ERROR);\n\n      // used next time\n      desired_torque_last = desired_torque;\n\n      // *** torque real time rate limit check ***\n      violation |= rt_rate_limit_check(desired_torque, rt_torque_last, CHRYSLER_MAX_RT_DELTA);\n\n      // every RT_INTERVAL set the new limits\n      uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n      if (ts_elapsed > CHRYSLER_RT_INTERVAL) {\n        rt_torque_last = desired_torque;\n        ts_last = ts;\n      }\n    }\n\n    // no torque if controls is not allowed\n    if (!controls_allowed && (desired_torque != 0)) {\n      violation = 1;\n    }\n\n    // reset to 0 if either controls is not allowed or there's a violation\n    if (violation || !controls_allowed) {\n      desired_torque_last = 0;\n      rt_torque_last = 0;\n      ts_last = ts;\n    }\n\n    if (violation) {\n      tx = 0;\n    }\n  }\n\n  // FORCE CANCEL: only the cancel button press is allowed\n  if (addr == 571) {\n    if ((GET_BYTE(to_send, 0) != 1) || ((GET_BYTE(to_send, 1) & 1) == 1)) {\n      tx = 0;\n    }\n  }\n\n  return tx;\n}\n\nstatic int chrysler_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n\n  int bus_fwd = -1;\n  int addr = GET_ADDR(to_fwd);\n\n  if (!relay_malfunction) {\n    // forward CAN 0 -> 2 so stock LKAS camera sees messages\n    if (bus_num == 0) {\n      bus_fwd = 2;\n    }\n    // forward all messages from camera except LKAS_COMMAND and LKAS_HUD\n    if ((bus_num == 2) && (addr != 658) && (addr != 678)) {\n      bus_fwd = 0;\n    }\n  }\n  return bus_fwd;\n}\n\nstatic const addr_checks* chrysler_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  return &chrysler_rx_checks;\n}\n\nconst safety_hooks chrysler_hooks = {\n  .init = chrysler_init,\n  .rx = chrysler_rx_hook,\n  .tx = chrysler_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = chrysler_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_defaults.h",
    "content": "const addr_checks default_rx_checks = {\n  .check = NULL,\n  .len = 0,\n};\n\nint default_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n  UNUSED(to_push);\n  return true;\n}\n\n// *** no output safety mode ***\n\nstatic const addr_checks* nooutput_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  return &default_rx_checks;\n}\n\nstatic int nooutput_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  UNUSED(to_send);\n  return false;\n}\n\nstatic int nooutput_tx_lin_hook(int lin_num, uint8_t *data, int len) {\n  UNUSED(lin_num);\n  UNUSED(data);\n  UNUSED(len);\n  return false;\n}\n\nstatic int default_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  UNUSED(to_fwd);\n  #ifdef vw\n  // Volkswagen community port: Advanced Virtual Relay Technology!\n  // Make Panda fully transparent from bus 0->2 and bus 2->0 if not otherwise\n  // instructed by EON/OP, returning the car to stock behavior under NOOUTPUT.\n  // Don't do this for BP/C2, where we have Advanced Actual Relay Technology.\n  int bus_fwd = -1;\n\n  if(hw_type == HW_TYPE_WHITE_PANDA || hw_type == HW_TYPE_GREY_PANDA) {\n    switch (bus_num) {\n      case 0:\n        bus_fwd = 2;\n        break;\n      case 2:\n        bus_fwd = 0;\n        break;\n      default:\n        bus_fwd = -1;\n        break;\n    }\n  }\n  return bus_fwd;\n  #else\n  UNUSED(bus_num);\n  return -1;\n  #endif\n}\n\nconst safety_hooks nooutput_hooks = {\n  .init = nooutput_init,\n  .rx = default_rx_hook,\n  .tx = nooutput_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = default_fwd_hook,\n};\n\n// *** all output safety mode ***\n\nstatic const addr_checks* alloutput_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = true;\n  relay_malfunction_reset();\n  return &default_rx_checks;\n}\n\nstatic int alloutput_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  UNUSED(to_send);\n  return true;\n}\n\nstatic int alloutput_tx_lin_hook(int lin_num, uint8_t *data, int len) {\n  UNUSED(lin_num);\n  UNUSED(data);\n  UNUSED(len);\n  return true;\n}\n\nconst safety_hooks alloutput_hooks = {\n  .init = alloutput_init,\n  .rx = default_rx_hook,\n  .tx = alloutput_tx_hook,\n  .tx_lin = alloutput_tx_lin_hook,\n  .fwd = default_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_elm327.h",
    "content": "static int elm327_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n  int len = GET_LEN(to_send);\n\n  //All ISO 15765-4 messages must be 8 bytes long\n  if (len != 8) {\n    tx = 0;\n  }\n\n  //Check valid 29 bit send addresses for ISO 15765-4\n  //Check valid 11 bit send addresses for ISO 15765-4\n  if ((addr != 0x18DB33F1) && ((addr & 0x1FFF00FF) != 0x18DA00F1) &&\n      ((addr & 0x1FFFFF00) != 0x700)) {\n    tx = 0;\n  }\n  return tx;\n}\n\nstatic int elm327_tx_lin_hook(int lin_num, uint8_t *data, int len) {\n  int tx = 1;\n  if (lin_num != 0) {\n    tx = 0;  //Only operate on LIN 0, aka serial 2\n  }\n  if ((len < 5) || (len > 11)) {\n    tx = 0;  //Valid KWP size\n  }\n  if (!(((data[0] & 0xF8U) == 0xC0U) && ((data[0] & 0x07U) != 0U) &&\n        (data[1] == 0x33U) && (data[2] == 0xF1U))) {\n    tx = 0;  //Bad msg\n  }\n  return tx;\n}\n\n// If current_board->has_obd and safety_param == 0, bus 1 is multiplexed to the OBD-II port\nconst safety_hooks elm327_hooks = {\n  .init = nooutput_init,\n  .rx = default_rx_hook,\n  .tx = elm327_tx_hook,\n  .tx_lin = elm327_tx_lin_hook,\n  .fwd = default_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_ford.h",
    "content": "// board enforces\n//   in-state\n//      accel set/resume\n//   out-state\n//      cancel button\n//      accel rising edge\n//      brake rising edge\n//      brake > 0mph\n\n\nstatic int ford_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  int addr = GET_ADDR(to_push);\n  int bus = GET_BUS(to_push);\n  bool unsafe_allow_gas = unsafe_mode & UNSAFE_DISABLE_DISENGAGE_ON_GAS;\n\n  if (addr == 0x217) {\n    // wheel speeds are 14 bits every 16\n    vehicle_moving = false;\n    for (int i = 0; i < 8; i += 2) {\n      vehicle_moving |= GET_BYTE(to_push, i) | (GET_BYTE(to_push, (int)(i + 1)) & 0xFCU);\n    }\n  }\n\n  // state machine to enter and exit controls\n  if (addr == 0x83) {\n    bool cancel = GET_BYTE(to_push, 1) & 0x1;\n    bool set_or_resume = GET_BYTE(to_push, 3) & 0x30;\n    if (cancel) {\n      controls_allowed = 0;\n    }\n    if (set_or_resume) {\n      controls_allowed = 1;\n    }\n  }\n\n  // exit controls on rising edge of brake press or on brake press when\n  // speed > 0\n  if (addr == 0x165) {\n    brake_pressed = GET_BYTE(to_push, 0) & 0x20;\n    if (brake_pressed && (!brake_pressed_prev || vehicle_moving)) {\n      controls_allowed = 0;\n    }\n    brake_pressed_prev = brake_pressed;\n  }\n\n  // exit controls on rising edge of gas press\n  if (addr == 0x204) {\n    gas_pressed = ((GET_BYTE(to_push, 0) & 0x03) | GET_BYTE(to_push, 1)) != 0;\n    if (!unsafe_allow_gas && gas_pressed && !gas_pressed_prev) {\n      controls_allowed = 0;\n    }\n    gas_pressed_prev = gas_pressed;\n  }\n\n  if ((safety_mode_cnt > RELAY_TRNS_TIMEOUT) && (bus == 0) && (addr == 0x3CA)) {\n    relay_malfunction_set();\n  }\n  return 1;\n}\n\n// all commands: just steering\n// if controls_allowed and no pedals pressed\n//     allow all commands up to limit\n// else\n//     block all commands that produce actuation\n\nstatic int ford_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n\n  // disallow actuator commands if gas or brake (with vehicle moving) are pressed\n  // and the the latching controls_allowed flag is True\n  int pedal_pressed = brake_pressed_prev && vehicle_moving;\n  bool unsafe_allow_gas = unsafe_mode & UNSAFE_DISABLE_DISENGAGE_ON_GAS;\n  if (!unsafe_allow_gas) {\n    pedal_pressed = pedal_pressed || gas_pressed_prev;\n  }\n  bool current_controls_allowed = controls_allowed && !(pedal_pressed);\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // STEER: safety check\n  if (addr == 0x3CA) {\n    if (!current_controls_allowed) {\n      // bits 7-4 need to be 0xF to disallow lkas commands\n      if ((GET_BYTE(to_send, 0) & 0xF0) != 0xF0) {\n        tx = 0;\n      }\n    }\n  }\n\n  // FORCE CANCEL: safety check only relevant when spamming the cancel button\n  // ensuring that set and resume aren't sent\n  if (addr == 0x83) {\n    if ((GET_BYTE(to_send, 3) & 0x30) != 0) {\n      tx = 0;\n    }\n  }\n\n  // 1 allows the message through\n  return tx;\n}\n\n// TODO: keep camera on bus 2 and make a fwd_hook\n\nconst safety_hooks ford_hooks = {\n  .init = nooutput_init,\n  .rx = ford_rx_hook,\n  .tx = ford_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = default_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_gm.h",
    "content": "// board enforces\n//   in-state\n//      accel set/resume\n//   out-state\n//      cancel button\n//      regen paddle\n//      accel rising edge\n//      brake rising edge\n//      brake > 0mph\n\nconst int GM_MAX_STEER = 300;\nconst int GM_MAX_RT_DELTA = 128;          // max delta torque allowed for real time checks\nconst uint32_t GM_RT_INTERVAL = 250000;    // 250ms between real time checks\nconst int GM_MAX_RATE_UP = 7;\nconst int GM_MAX_RATE_DOWN = 17;\nconst int GM_DRIVER_TORQUE_ALLOWANCE = 50;\nconst int GM_DRIVER_TORQUE_FACTOR = 4;\nconst int GM_MAX_GAS = 3072;\nconst int GM_MAX_REGEN = 1404;\nconst int GM_MAX_BRAKE = 350;\nconst CanMsg GM_TX_MSGS[] = {{384, 0, 4}, {1033, 0, 7}, {1034, 0, 7}, {715, 0, 8}, {880, 0, 6},  // pt bus\n                             {161, 1, 7}, {774, 1, 8}, {776, 1, 7}, {784, 1, 2},   // obs bus\n                             {789, 2, 5},  // ch bus\n                             {0x104c006c, 3, 3}, {0x10400060, 3, 5}};  // gmlan\n\n// TODO: do checksum and counter checks. Add correct timestep, 0.1s for now.\nAddrCheckStruct gm_addr_checks[] = {\n  {.msg = {{388, 0, 8, .expected_timestep = 100000U}, { 0 }, { 0 }}},\n  {.msg = {{842, 0, 5, .expected_timestep = 100000U}, { 0 }, { 0 }}},\n  {.msg = {{481, 0, 7, .expected_timestep = 100000U}, { 0 }, { 0 }}},\n  {.msg = {{241, 0, 6, .expected_timestep = 100000U}, { 0 }, { 0 }}},\n  {.msg = {{417, 0, 7, .expected_timestep = 100000U}, { 0 }, { 0 }}},\n};\n#define GM_RX_CHECK_LEN (sizeof(gm_addr_checks) / sizeof(gm_addr_checks[0]))\naddr_checks gm_rx_checks = {gm_addr_checks, GM_RX_CHECK_LEN};\n\nstatic int gm_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &gm_rx_checks, NULL, NULL, NULL);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n\n    if (addr == 388) {\n      int torque_driver_new = ((GET_BYTE(to_push, 6) & 0x7) << 8) | GET_BYTE(to_push, 7);\n      torque_driver_new = to_signed(torque_driver_new, 11);\n      // update array of samples\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // sample speed, really only care if car is moving or not\n    // rear left wheel speed\n    if (addr == 842) {\n      vehicle_moving = GET_BYTE(to_push, 0) | GET_BYTE(to_push, 1);\n    }\n\n    // ACC steering wheel buttons\n    if (addr == 481) {\n      int button = (GET_BYTE(to_push, 5) & 0x70) >> 4;\n      switch (button) {\n        case 2:  // resume\n        case 3:  // set\n          controls_allowed = 1;\n          break;\n        case 6:  // cancel\n          controls_allowed = 0;\n          break;\n        default:\n          break;  // any other button is irrelevant\n      }\n    }\n\n    // speed > 0\n    if (addr == 241) {\n      // Brake pedal's potentiometer returns near-zero reading\n      // even when pedal is not pressed\n      brake_pressed = GET_BYTE(to_push, 1) >= 10;\n    }\n\n    if (addr == 417) {\n      gas_pressed = GET_BYTE(to_push, 6) != 0;\n    }\n\n    // exit controls on regen paddle\n    if (addr == 189) {\n      bool regen = GET_BYTE(to_push, 0) & 0x20;\n      if (regen) {\n        controls_allowed = 0;\n      }\n    }\n\n    // Check if ASCM or LKA camera are online\n    // on powertrain bus.\n    // 384 = ASCMLKASteeringCmd\n    // 715 = ASCMGasRegenCmd\n    generic_rx_checks(((addr == 384) || (addr == 715)));\n  }\n  return valid;\n}\n\n// all commands: gas/regen, friction brake and steering\n// if controls_allowed and no pedals pressed\n//     allow all commands up to limit\n// else\n//     block all commands that produce actuation\n\nstatic int gm_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n\n  if (!msg_allowed(to_send, GM_TX_MSGS, sizeof(GM_TX_MSGS)/sizeof(GM_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // disallow actuator commands if gas or brake (with vehicle moving) are pressed\n  // and the the latching controls_allowed flag is True\n  int pedal_pressed = brake_pressed_prev && vehicle_moving;\n  bool unsafe_allow_gas = unsafe_mode & UNSAFE_DISABLE_DISENGAGE_ON_GAS;\n  if (!unsafe_allow_gas) {\n    pedal_pressed = pedal_pressed || gas_pressed_prev;\n  }\n  bool current_controls_allowed = controls_allowed && !pedal_pressed;\n\n  // BRAKE: safety check\n  if (addr == 789) {\n    int brake = ((GET_BYTE(to_send, 0) & 0xFU) << 8) + GET_BYTE(to_send, 1);\n    brake = (0x1000 - brake) & 0xFFF;\n    if (!current_controls_allowed) {\n      if (brake != 0) {\n        tx = 0;\n      }\n    }\n    if (brake > GM_MAX_BRAKE) {\n      tx = 0;\n    }\n  }\n\n  // LKA STEER: safety check\n  if (addr == 384) {\n    int desired_torque = ((GET_BYTE(to_send, 0) & 0x7U) << 8) + GET_BYTE(to_send, 1);\n    uint32_t ts = microsecond_timer_get();\n    bool violation = 0;\n    desired_torque = to_signed(desired_torque, 11);\n\n    if (current_controls_allowed) {\n\n      // *** global torque limit check ***\n      violation |= max_limit_check(desired_torque, GM_MAX_STEER, -GM_MAX_STEER);\n\n      // *** torque rate limit check ***\n      violation |= driver_limit_check(desired_torque, desired_torque_last, &torque_driver,\n        GM_MAX_STEER, GM_MAX_RATE_UP, GM_MAX_RATE_DOWN,\n        GM_DRIVER_TORQUE_ALLOWANCE, GM_DRIVER_TORQUE_FACTOR);\n\n      // used next time\n      desired_torque_last = desired_torque;\n\n      // *** torque real time rate limit check ***\n      violation |= rt_rate_limit_check(desired_torque, rt_torque_last, GM_MAX_RT_DELTA);\n\n      // every RT_INTERVAL set the new limits\n      uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n      if (ts_elapsed > GM_RT_INTERVAL) {\n        rt_torque_last = desired_torque;\n        ts_last = ts;\n      }\n    }\n\n    // no torque if controls is not allowed\n    if (!current_controls_allowed && (desired_torque != 0)) {\n      violation = 1;\n    }\n\n    // reset to 0 if either controls is not allowed or there's a violation\n    if (violation || !current_controls_allowed) {\n      desired_torque_last = 0;\n      rt_torque_last = 0;\n      ts_last = ts;\n    }\n\n    if (violation) {\n      tx = 0;\n    }\n  }\n\n  // GAS/REGEN: safety check\n  if (addr == 715) {\n    int gas_regen = ((GET_BYTE(to_send, 2) & 0x7FU) << 5) + ((GET_BYTE(to_send, 3) & 0xF8U) >> 3);\n    // Disabled message is !engaged with gas\n    // value that corresponds to max regen.\n    if (!current_controls_allowed) {\n      bool apply = GET_BYTE(to_send, 0) & 1U;\n      if (apply || (gas_regen != GM_MAX_REGEN)) {\n        tx = 0;\n      }\n    }\n    if (gas_regen > GM_MAX_GAS) {\n      tx = 0;\n    }\n  }\n\n  // 1 allows the message through\n  return tx;\n}\n\nstatic const addr_checks* gm_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  return &gm_rx_checks;\n}\n\nconst safety_hooks gm_hooks = {\n  .init = gm_init,\n  .rx = gm_rx_hook,\n  .tx = gm_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = default_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_gm_ascm.h",
    "content": "// BUS 0 is on the LKAS module (ASCM) side\n// BUS 2 is on the actuator (EPS) side\n\nstatic int gm_ascm_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n\n  int bus_fwd = -1;\n\n  if (bus_num == 0) {\n    int addr = GET_ADDR(to_fwd);\n    bus_fwd = 2;\n    // do not propagate lkas messages from ascm to actuators, unless supercruise is on\n    // block 0x152 and 0x154, which are the lkas command from ASCM1 and ASCM2\n    // block 0x315 and 0x2cb, which are the brake and accel commands from ASCM1\n    //if ((addr == 0x152) || (addr == 0x154) || (addr == 0x315) || (addr == 0x2cb)) {\n    if ((addr == 0x152) || (addr == 0x154)) {\n      bool supercruise_on = (GET_BYTE(to_fwd, 4) & 0x10) != 0;  // bit 36\n      if (!supercruise_on) {\n        bus_fwd = -1;\n      }\n    }\n    if ((addr == 0x151) || (addr == 0x153) || (addr == 0x314)) {\n      // on the chassis bus, the OBDII port is on the module side, so we need to read\n      // the lkas messages sent by openpilot (put on unused 0x151 ane 0x153 addrs) and send it to\n      // the actuator as 0x152 and 0x154\n      uint32_t fwd_addr = addr + 1;\n      to_fwd->RIR = (fwd_addr << 21) | (to_fwd->RIR & 0x1fffff);\n    }\n  }\n\n  if (bus_num == 2) {\n    bus_fwd = 0;\n  }\n\n  return bus_fwd;\n}\n\nconst safety_hooks gm_ascm_hooks = {\n  .init = nooutput_init,\n  .rx = default_rx_hook,\n  .tx = alloutput_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = gm_ascm_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_honda.h",
    "content": "// board enforces\n//   in-state\n//      accel set/resume\n//   out-state\n//      cancel button\n//      accel rising edge\n//      brake rising edge\n//      brake > 0mph\nconst CanMsg HONDA_N_TX_MSGS[] = {{0xE4, 0, 5}, {0x194, 0, 4}, {0x1FA, 0, 8}, {0x200, 0, 6}, {0x30C, 0, 8}, {0x33D, 0, 5}};\nconst CanMsg HONDA_BG_TX_MSGS[] = {{0xE4, 2, 5}, {0xE5, 2, 8}, {0x296, 0, 4}, {0x33D, 2, 5}};  // Bosch Giraffe\nconst CanMsg HONDA_BH_TX_MSGS[] = {{0xE4, 0, 5}, {0xE5, 0, 8}, {0x296, 1, 4}, {0x33D, 0, 5}};  // Bosch Harness\nconst CanMsg HONDA_BG_LONG_TX_MSGS[] = {{0xE4, 0, 5}, {0x1DF, 0, 8}, {0x1EF, 0, 8}, {0x1FA, 0, 8}, {0x30C, 0, 8}, {0x33D, 0, 5}, {0x39F, 0, 8}, {0x18DAB0F1, 0, 8}};  // Bosch Giraffe w/ gas and brakes\nconst CanMsg HONDA_BH_LONG_TX_MSGS[] = {{0xE4, 1, 5}, {0x1DF, 1, 8}, {0x1EF, 1, 8}, {0x1FA, 1, 8}, {0x30C, 1, 8}, {0x33D, 1, 5}, {0x39F, 1, 8}, {0x18DAB0F1, 1, 8}};  // Bosch Harness w/ gas and brakes\n\n// Roughly calculated using the offsets in openpilot +5%:\n// In openpilot: ((gas1_norm + gas2_norm)/2) > 15\n// gas_norm1 = ((gain_dbc1*gas1) + offset_dbc)\n// gas_norm2 = ((gain_dbc2*gas2) + offset_dbc)\n// assuming that 2*(gain_dbc1*gas1) == (gain_dbc2*gas2)\n// In this safety: ((gas1 + (gas2/2))/2) > THRESHOLD\nconst int HONDA_GAS_INTERCEPTOR_THRESHOLD = 344;\n#define HONDA_GET_INTERCEPTOR(msg) (((GET_BYTE((msg), 0) << 8) + GET_BYTE((msg), 1) + ((GET_BYTE((msg), 2) << 8) + GET_BYTE((msg), 3)) / 2 ) / 2) // avg between 2 tracks\nconst int HONDA_BOSCH_NO_GAS_VALUE = -30000; // value sent when not requesting gas\nconst int HONDA_BOSCH_GAS_MAX = 2000;\nconst int HONDA_BOSCH_ACCEL_MIN = -350; // max braking == -3.5m/s2\n\n// Nidec and Bosch giraffe have pt on bus 0\nAddrCheckStruct honda_addr_checks[] = {\n  {.msg = {{0x1A6, 0, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 40000U},\n           {0x296, 0, 4, .check_checksum = true, .max_counter = 3U, .expected_timestep = 40000U},{ 0 }}},\n  {.msg = {{0x158, 0, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{0x17C, 0, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n};\n#define HONDA_ADDR_CHECKS_LEN (sizeof(honda_addr_checks) / sizeof(honda_addr_checks[0]))\n\n// Bosch harness has pt on bus 1\nAddrCheckStruct honda_bh_addr_checks[] = {\n  {.msg = {{0x296, 1, 4, .check_checksum = true, .max_counter = 3U, .expected_timestep = 40000U}, { 0 }, { 0 }}},\n  {.msg = {{0x158, 1, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{0x17C, 1, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 10000U},\n           {0x1BE, 1, 3, .check_checksum = true, .max_counter = 3U, .expected_timestep = 20000U}, { 0 }}},\n};\n#define HONDA_BH_ADDR_CHECKS_LEN (sizeof(honda_bh_addr_checks) / sizeof(honda_bh_addr_checks[0]))\n\nconst uint16_t HONDA_PARAM_ALT_BRAKE = 1;\nconst uint16_t HONDA_PARAM_BOSCH_LONG = 2;\n\nint honda_brake = 0;\nbool honda_alt_brake_msg = false;\nbool honda_fwd_brake = false;\nbool honda_bosch_long = false;\nenum {HONDA_N_HW, HONDA_BG_HW, HONDA_BH_HW} honda_hw = HONDA_N_HW;\naddr_checks honda_rx_checks = {honda_addr_checks, HONDA_ADDR_CHECKS_LEN};\n\n\nstatic uint8_t honda_get_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int checksum_byte = GET_LEN(to_push) - 1;\n  return (uint8_t)(GET_BYTE(to_push, checksum_byte)) & 0xFU;\n}\n\nstatic uint8_t honda_compute_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int len = GET_LEN(to_push);\n  uint8_t checksum = 0U;\n  unsigned int addr = GET_ADDR(to_push);\n  while (addr > 0U) {\n    checksum += (addr & 0xFU); addr >>= 4;\n  }\n  for (int j = 0; j < len; j++) {\n    uint8_t byte = GET_BYTE(to_push, j);\n    checksum += (byte & 0xFU) + (byte >> 4U);\n    if (j == (len - 1)) {\n      checksum -= (byte & 0xFU);  // remove checksum in message\n    }\n  }\n  return (8U - checksum) & 0xFU;\n}\n\nstatic uint8_t honda_get_counter(CAN_FIFOMailBox_TypeDef *to_push) {\n  int counter_byte = GET_LEN(to_push) - 1;\n  return ((uint8_t)(GET_BYTE(to_push, counter_byte)) >> 4U) & 0x3U;\n}\n\nstatic int honda_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &honda_rx_checks,\n                                 honda_get_checksum, honda_compute_checksum, honda_get_counter);\n\n  if (valid) {\n    int addr = GET_ADDR(to_push);\n    int len = GET_LEN(to_push);\n    int bus = GET_BUS(to_push);\n\n    // sample speed\n    if (addr == 0x158) {\n      // first 2 bytes\n      vehicle_moving = GET_BYTE(to_push, 0) | GET_BYTE(to_push, 1);\n    }\n\n    // state machine to enter and exit controls\n    // 0x1A6 for the ILX, 0x296 for the Civic Touring\n    if ((addr == 0x1A6) || (addr == 0x296)) {\n      int button = (GET_BYTE(to_push, 0) & 0xE0) >> 5;\n      switch (button) {\n        case 2:  // cancel\n          controls_allowed = 0;\n          break;\n        case 3:  // set\n        case 4:  // resume\n          controls_allowed = 1;\n          break;\n        default:\n          break; // any other button is irrelevant\n      }\n    }\n\n    // user brake signal on 0x17C reports applied brake from computer brake on accord\n    // and crv, which prevents the usual brake safety from working correctly. these\n    // cars have a signal on 0x1BE which only detects user's brake being applied so\n    // in these cases, this is used instead.\n    // most hondas: 0x17C bit 53\n    // accord, crv: 0x1BE bit 4\n    bool is_user_brake_msg = honda_alt_brake_msg ? ((addr) == 0x1BE) : ((addr) == 0x17C);\n    if (is_user_brake_msg) {\n      brake_pressed = honda_alt_brake_msg ? (GET_BYTE((to_push), 0) & 0x10) : (GET_BYTE((to_push), 6) & 0x20);\n    }\n\n    // length check because bosch hardware also uses this id (0x201 w/ len = 8)\n    if ((addr == 0x201) && (len == 6)) {\n      gas_interceptor_detected = 1;\n      int gas_interceptor = HONDA_GET_INTERCEPTOR(to_push);\n      gas_pressed = gas_interceptor > HONDA_GAS_INTERCEPTOR_THRESHOLD;\n      gas_interceptor_prev = gas_interceptor;\n    }\n\n    if (!gas_interceptor_detected) {\n      if (addr == 0x17C) {\n        gas_pressed = GET_BYTE(to_push, 0) != 0;\n      }\n    }\n\n    // disable stock Honda AEB in unsafe mode\n    if ( !(unsafe_mode & UNSAFE_DISABLE_STOCK_AEB) ) {\n      if ((bus == 2) && (addr == 0x1FA)) {\n        bool honda_stock_aeb = GET_BYTE(to_push, 3) & 0x20;\n        int honda_stock_brake = (GET_BYTE(to_push, 0) << 2) + ((GET_BYTE(to_push, 1) >> 6) & 0x3);\n\n        // Forward AEB when stock braking is higher than openpilot braking\n        // only stop forwarding when AEB event is over\n        if (!honda_stock_aeb) {\n          honda_fwd_brake = false;\n        } else if (honda_stock_brake >= honda_brake) {\n          honda_fwd_brake = true;\n        } else {\n          // Leave Honda forward brake as is\n        }\n      }\n    }\n\n    bool stock_ecu_detected = false;\n    int bus_rdr_car = (honda_hw == HONDA_BH_HW) ? 0 : 2;  // radar bus, car side\n    int pt_bus = (honda_hw == HONDA_BH_HW) ? 1 : 0;\n\n    if (safety_mode_cnt > RELAY_TRNS_TIMEOUT) {\n      // If steering controls messages are received on the destination bus, it's an indication\n      // that the relay might be malfunctioning\n      if ((addr == 0xE4) || (addr == 0x194)) {\n        if (((honda_hw != HONDA_N_HW) && (bus == bus_rdr_car)) || ((honda_hw == HONDA_N_HW) && (bus == 0))) {\n          stock_ecu_detected = true;\n        }\n      }\n      // If Honda Bosch longitudinal mode is selected we need to ensure the radar is turned off\n      // Verify this by ensuring ACC_CONTROL (0x1DF) is not received on the PT bus\n      if (honda_bosch_long && (bus == pt_bus) && (addr == 0x1DF)) {\n        stock_ecu_detected = true;\n      }\n    }\n\n    generic_rx_checks(stock_ecu_detected);\n  }\n  return valid;\n}\n\n// all commands: gas, brake and steering\n// if controls_allowed and no pedals pressed\n//     allow all commands up to limit\n// else\n//     block all commands that produce actuation\n\nstatic int honda_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n  int bus = GET_BUS(to_send);\n\n  if ((honda_hw == HONDA_BG_HW) && !honda_bosch_long) {\n    tx = msg_allowed(to_send, HONDA_BG_TX_MSGS, sizeof(HONDA_BG_TX_MSGS)/sizeof(HONDA_BG_TX_MSGS[0]));\n  } else if ((honda_hw == HONDA_BG_HW) && honda_bosch_long) {\n    tx = msg_allowed(to_send, HONDA_BG_LONG_TX_MSGS, sizeof(HONDA_BG_LONG_TX_MSGS)/sizeof(HONDA_BG_LONG_TX_MSGS[0]));\n  } else if ((honda_hw == HONDA_BH_HW) && !honda_bosch_long) {\n    tx = msg_allowed(to_send, HONDA_BH_TX_MSGS, sizeof(HONDA_BH_TX_MSGS)/sizeof(HONDA_BH_TX_MSGS[0]));\n  } else if ((honda_hw == HONDA_BH_HW) && honda_bosch_long) {\n    tx = msg_allowed(to_send, HONDA_BH_LONG_TX_MSGS, sizeof(HONDA_BH_LONG_TX_MSGS)/sizeof(HONDA_BH_LONG_TX_MSGS[0]));\n  } else {\n    tx = msg_allowed(to_send, HONDA_N_TX_MSGS, sizeof(HONDA_N_TX_MSGS)/sizeof(HONDA_N_TX_MSGS[0]));\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // disallow actuator commands if gas or brake (with vehicle moving) are pressed\n  // and the the latching controls_allowed flag is True\n  int pedal_pressed = brake_pressed_prev && vehicle_moving;\n  bool unsafe_allow_gas = unsafe_mode & UNSAFE_DISABLE_DISENGAGE_ON_GAS;\n  if (!unsafe_allow_gas) {\n    pedal_pressed = pedal_pressed || gas_pressed_prev || (gas_interceptor_prev > HONDA_GAS_INTERCEPTOR_THRESHOLD);\n  }\n  bool current_controls_allowed = controls_allowed && !(pedal_pressed);\n  int bus_pt = (honda_hw == HONDA_BH_HW)? 1 : 0;\n\n  // BRAKE: safety check (nidec)\n  if ((addr == 0x1FA) && (bus == bus_pt)) {\n    honda_brake = (GET_BYTE(to_send, 0) << 2) + ((GET_BYTE(to_send, 1) >> 6) & 0x3);\n    if (!current_controls_allowed) {\n      if (honda_brake != 0) {\n        tx = 0;\n      }\n    }\n    if (honda_brake > 255) {\n      tx = 0;\n    }\n    if (honda_fwd_brake) {\n      tx = 0;\n    }\n  }\n\n  // BRAKE/GAS: safety check (bosch)\n  if ((addr == 0x1DF) && (bus == bus_pt)) {\n    int accel = (GET_BYTE(to_send, 3) << 3) | ((GET_BYTE(to_send, 4) >> 5) & 0x7);\n    accel = to_signed(accel, 11);\n    if (!current_controls_allowed) {\n      if (accel != 0) {\n        tx = 0;\n      }\n    }\n    if (accel < HONDA_BOSCH_ACCEL_MIN) {\n      tx = 0;\n    }\n\n    int gas = (GET_BYTE(to_send, 0) << 8) | GET_BYTE(to_send, 1);\n    gas = to_signed(gas, 16);\n    if (!current_controls_allowed) {\n      if (gas != HONDA_BOSCH_NO_GAS_VALUE) {\n        tx = 0;\n      }\n    }\n    if (gas > HONDA_BOSCH_GAS_MAX) {\n      tx = 0;\n    }\n  }\n\n  // STEER: safety check\n  if ((addr == 0xE4) || (addr == 0x194)) {\n    if (!current_controls_allowed) {\n      bool steer_applied = GET_BYTE(to_send, 0) | GET_BYTE(to_send, 1);\n      if (steer_applied) {\n        tx = 0;\n      }\n    }\n  }\n\n    // Bosch supplemental control check\n  if (addr == 0xE5) {\n    if ((GET_BYTES_04(to_send) != 0x10800004) || ((GET_BYTES_48(to_send) & 0x00FFFFFF) != 0x0)) {\n      tx = 0;\n    }\n  }\n\n  // GAS: safety check (interceptor)\n  if (addr == 0x200) {\n    if (!current_controls_allowed) {\n      if (GET_BYTE(to_send, 0) || GET_BYTE(to_send, 1)) {\n        tx = 0;\n      }\n    }\n  }\n\n  // FORCE CANCEL: safety check only relevant when spamming the cancel button in Bosch HW\n  // ensuring that only the cancel button press is sent (VAL 2) when controls are off.\n  // This avoids unintended engagements while still allowing resume spam\n  if ((addr == 0x296) && !current_controls_allowed && (bus == bus_pt)) {\n    if (((GET_BYTE(to_send, 0) >> 5) & 0x7) != 2) {\n      tx = 0;\n    }\n  }\n\n  // Only tester present (\"\\x02\\x3E\\x80\\x00\\x00\\x00\\x00\\x00\") allowed on diagnostics address\n  if (addr == 0x18DAB0F1) {\n  if ((GET_BYTES_04(to_send) != 0x00803E02) || (GET_BYTES_48(to_send) != 0x0)) {\n    tx = 0;\n  }\n  }\n\n  // 1 allows the message through\n  return tx;\n}\n\nstatic const addr_checks* honda_nidec_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  gas_interceptor_detected = 0;\n  honda_hw = HONDA_N_HW;\n  honda_alt_brake_msg = false;\n  honda_bosch_long = false;\n  honda_rx_checks = (addr_checks){honda_addr_checks, HONDA_ADDR_CHECKS_LEN};\n  return &honda_rx_checks;\n}\n\nstatic const addr_checks* honda_bosch_giraffe_init(int16_t param) {\n  controls_allowed = false;\n  relay_malfunction_reset();\n  honda_hw = HONDA_BG_HW;\n  // Checking for alternate brake override from safety parameter\n  honda_alt_brake_msg = GET_FLAG(param, HONDA_PARAM_ALT_BRAKE);\n  // radar disabled so allow gas/brakes\n  honda_bosch_long = GET_FLAG(param, HONDA_PARAM_BOSCH_LONG);\n  honda_rx_checks = (addr_checks){honda_addr_checks, HONDA_ADDR_CHECKS_LEN};\n  return &honda_rx_checks;\n}\n\nstatic const addr_checks* honda_bosch_harness_init(int16_t param) {\n  controls_allowed = false;\n  relay_malfunction_reset();\n  honda_hw = HONDA_BH_HW;\n  // Checking for alternate brake override from safety parameter\n  honda_alt_brake_msg = GET_FLAG(param, HONDA_PARAM_ALT_BRAKE);\n  // radar disabled so allow gas/brakes\n  honda_bosch_long = GET_FLAG(param, HONDA_PARAM_BOSCH_LONG);\n  honda_rx_checks = (addr_checks){honda_bh_addr_checks, HONDA_BH_ADDR_CHECKS_LEN};\n  return &honda_rx_checks;\n}\n\nstatic int honda_nidec_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  // fwd from car to camera. also fwd certain msgs from camera to car\n  // 0xE4 is steering on all cars except CRV and RDX, 0x194 for CRV and RDX,\n  // 0x1FA is brake control, 0x30C is acc hud, 0x33D is lkas hud,\n  int bus_fwd = -1;\n\n  if (!relay_malfunction) {\n    if (bus_num == 0) {\n      bus_fwd = 2;\n    }\n    if (bus_num == 2) {\n      // block stock lkas messages and stock acc messages (if OP is doing ACC)\n      int addr = GET_ADDR(to_fwd);\n      bool is_lkas_msg = (addr == 0xE4) || (addr == 0x194) || (addr == 0x33D);\n      bool is_acc_hud_msg = addr == 0x30C;\n      bool is_brake_msg = addr == 0x1FA;\n      bool block_fwd = is_lkas_msg || is_acc_hud_msg || (is_brake_msg && !honda_fwd_brake);\n      if (!block_fwd) {\n        bus_fwd = 0;\n      }\n    }\n  }\n  return bus_fwd;\n}\n\nstatic int honda_bosch_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int bus_fwd = -1;\n  int bus_rdr_cam = (honda_hw == HONDA_BH_HW) ? 2 : 1;  // radar bus, camera side\n  int bus_rdr_car = (honda_hw == HONDA_BH_HW) ? 0 : 2;  // radar bus, car side\n\n  if (!relay_malfunction) {\n    if (bus_num == bus_rdr_car) {\n      bus_fwd = bus_rdr_cam;\n    }\n    if (bus_num == bus_rdr_cam)  {\n      int addr = GET_ADDR(to_fwd);\n      int is_lkas_msg = (addr == 0xE4) || (addr == 0xE5) || (addr == 0x33D);\n      if (!is_lkas_msg) {\n        bus_fwd = bus_rdr_car;\n      }\n    }\n  }\n  return bus_fwd;\n}\n\nconst safety_hooks honda_nidec_hooks = {\n  .init = honda_nidec_init,\n  .rx = honda_rx_hook,\n  .tx = honda_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = honda_nidec_fwd_hook,\n};\n\nconst safety_hooks honda_bosch_giraffe_hooks = {\n  .init = honda_bosch_giraffe_init,\n  .rx = honda_rx_hook,\n  .tx = honda_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = honda_bosch_fwd_hook,\n};\n\nconst safety_hooks honda_bosch_harness_hooks = {\n  .init = honda_bosch_harness_init,\n  .rx = honda_rx_hook,\n  .tx = honda_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = honda_bosch_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_hyundai.h",
    "content": "const int HYUNDAI_MAX_STEER = 384;             // like stock\nconst int HYUNDAI_MAX_RT_DELTA = 112;          // max delta torque allowed for real time checks\nconst uint32_t HYUNDAI_RT_INTERVAL = 250000;   // 250ms between real time checks\nconst int HYUNDAI_MAX_RATE_UP = 3;\nconst int HYUNDAI_MAX_RATE_DOWN = 7;\nconst int HYUNDAI_DRIVER_TORQUE_ALLOWANCE = 50;\nconst int HYUNDAI_DRIVER_TORQUE_FACTOR = 2;\nconst int HYUNDAI_STANDSTILL_THRSLD = 30;  // ~1kph\nconst CanMsg HYUNDAI_TX_MSGS[] = {\n  {832, 0, 8},  // LKAS11 Bus 0\n  {1265, 0, 4}, // CLU11 Bus 0\n  {1157, 0, 4}, // LFAHDA_MFC Bus 0\n  // {1056, 0, 8}, //   SCC11,  Bus 0\n  // {1057, 0, 8}, //   SCC12,  Bus 0\n  // {1290, 0, 8}, //   SCC13,  Bus 0\n  // {905, 0, 8},  //   SCC14,  Bus 0\n  // {1186, 0, 8}  //   4a2SCC, Bus 0\n };\n\nAddrCheckStruct hyundai_addr_checks[] = {\n  {.msg = {{608, 0, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 10000U},\n           {881, 0, 8, .expected_timestep = 10000U}, { 0 }}},\n  {.msg = {{902, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{916, 0, 8, .check_checksum = true, .max_counter = 7U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{1057, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n};\n#define HYUNDAI_ADDR_CHECK_LEN (sizeof(hyundai_addr_checks) / sizeof(hyundai_addr_checks[0]))\n\n// older hyundai models have less checks due to missing counters and checksums\nAddrCheckStruct hyundai_legacy_addr_checks[] = {\n  {.msg = {{608, 0, 8, .check_checksum = true, .max_counter = 3U, .expected_timestep = 10000U},\n           {881, 0, 8, .expected_timestep = 10000U}, { 0 }}},\n  {.msg = {{902, 0, 8, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{916, 0, 8, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{1057, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n};\n#define HYUNDAI_LEGACY_ADDR_CHECK_LEN (sizeof(hyundai_legacy_addr_checks) / sizeof(hyundai_legacy_addr_checks[0]))\n\nconst int HYUNDAI_PARAM_EV_GAS = 1;\nconst int HYUNDAI_PARAM_HYBRID_GAS = 2;\n\nbool hyundai_legacy = false;\nbool hyundai_ev_gas_signal = false;\nbool hyundai_hybrid_gas_signal = false;\n\naddr_checks hyundai_rx_checks = {hyundai_addr_checks, HYUNDAI_ADDR_CHECK_LEN};\n\nstatic uint8_t hyundai_get_counter(CAN_FIFOMailBox_TypeDef *to_push) {\n  int addr = GET_ADDR(to_push);\n\n  uint8_t cnt;\n  if (addr == 608) {\n    cnt = (GET_BYTE(to_push, 7) >> 4) & 0x3;\n  } else if (addr == 902) {\n    cnt = ((GET_BYTE(to_push, 3) >> 6) << 2) | (GET_BYTE(to_push, 1) >> 6);\n  } else if (addr == 916) {\n    cnt = (GET_BYTE(to_push, 1) >> 5) & 0x7;\n  } else if (addr == 1057) {\n    cnt = GET_BYTE(to_push, 7) & 0xF;\n  } else {\n    cnt = 0;\n  }\n  return cnt;\n}\n\nstatic uint8_t hyundai_get_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int addr = GET_ADDR(to_push);\n\n  uint8_t chksum;\n  if (addr == 608) {\n    chksum = GET_BYTE(to_push, 7) & 0xF;\n  } else if (addr == 902) {\n    chksum = ((GET_BYTE(to_push, 7) >> 6) << 2) | (GET_BYTE(to_push, 5) >> 6);\n  } else if (addr == 916) {\n    chksum = GET_BYTE(to_push, 6) & 0xF;\n  } else if (addr == 1057) {\n    chksum = GET_BYTE(to_push, 7) >> 4;\n  } else {\n    chksum = 0;\n  }\n  return chksum;\n}\n\nstatic uint8_t hyundai_compute_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int addr = GET_ADDR(to_push);\n\n  uint8_t chksum = 0;\n  if (addr == 902) {\n    // count the bits\n    for (int i = 0; i < 8; i++) {\n      uint8_t b = GET_BYTE(to_push, i);\n      for (int j = 0; j < 8; j++) {\n        uint8_t bit = 0;\n        // exclude checksum and counter\n        if (((i != 1) || (j < 6)) && ((i != 3) || (j < 6)) && ((i != 5) || (j < 6)) && ((i != 7) || (j < 6))) {\n          bit = (b >> (uint8_t)j) & 1U;\n        }\n        chksum += bit;\n      }\n    }\n    chksum = (chksum ^ 9U) & 15U;\n  } else {\n    // sum of nibbles\n    for (int i = 0; i < 8; i++) {\n      if ((addr == 916) && (i == 7)) {\n        continue; // exclude\n      }\n      uint8_t b = GET_BYTE(to_push, i);\n      if (((addr == 608) && (i == 7)) || ((addr == 916) && (i == 6)) || ((addr == 1057) && (i == 7))) {\n        b &= (addr == 1057) ? 0x0FU : 0xF0U; // remove checksum\n      }\n      chksum += (b % 16U) + (b / 16U);\n    }\n    chksum = (16U - (chksum %  16U)) % 16U;\n  }\n\n  return chksum;\n}\n\nstatic int hyundai_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &hyundai_rx_checks,\n                                 hyundai_get_checksum, hyundai_compute_checksum,\n                                 hyundai_get_counter);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n\n    if (addr == 593) {\n      int torque_driver_new = ((GET_BYTES_04(to_push) & 0x7ff) * 0.79) - 808; // scale down new driver torque signal to match previous one\n      // update array of samples\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // enter controls on rising edge of ACC, exit controls on ACC off\n    if (addr == 1057) {\n      // 2 bits: 13-14\n      int cruise_engaged = (GET_BYTES_04(to_push) >> 13) & 0x3;\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    // read gas pressed signal\n    if ((addr == 881) && hyundai_ev_gas_signal) {\n      gas_pressed = (((GET_BYTE(to_push, 4) & 0x7F) << 1) | GET_BYTE(to_push, 3) >> 7) != 0;\n    } else if ((addr == 881) && hyundai_hybrid_gas_signal) {\n      gas_pressed = GET_BYTE(to_push, 7) != 0;\n    } else if (addr == 608) {  // ICE\n      gas_pressed = (GET_BYTE(to_push, 7) >> 6) != 0;\n    } else {\n    }\n\n    // sample wheel speed, averaging opposite corners\n    if (addr == 902) {\n      int hyundai_speed = GET_BYTES_04(to_push) & 0x3FFF;  // FL\n      hyundai_speed += (GET_BYTES_48(to_push) >> 16) & 0x3FFF;  // RL\n      hyundai_speed /= 2;\n      vehicle_moving = hyundai_speed > HYUNDAI_STANDSTILL_THRSLD;\n    }\n\n    if (addr == 916) {\n      brake_pressed = (GET_BYTE(to_push, 6) >> 7) != 0;\n    }\n\n    generic_rx_checks((addr == 832));\n  }\n  return valid;\n}\n\nstatic int hyundai_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n\n  if (!msg_allowed(to_send, HYUNDAI_TX_MSGS, sizeof(HYUNDAI_TX_MSGS)/sizeof(HYUNDAI_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // LKA STEER: safety check\n  if (addr == 832) {\n    int desired_torque = ((GET_BYTES_04(to_send) >> 16) & 0x7ff) - 1024;\n    uint32_t ts = microsecond_timer_get();\n    bool violation = 0;\n\n    if (controls_allowed) {\n\n      // *** global torque limit check ***\n      violation |= max_limit_check(desired_torque, HYUNDAI_MAX_STEER, -HYUNDAI_MAX_STEER);\n\n      // *** torque rate limit check ***\n      violation |= driver_limit_check(desired_torque, desired_torque_last, &torque_driver,\n        HYUNDAI_MAX_STEER, HYUNDAI_MAX_RATE_UP, HYUNDAI_MAX_RATE_DOWN,\n        HYUNDAI_DRIVER_TORQUE_ALLOWANCE, HYUNDAI_DRIVER_TORQUE_FACTOR);\n\n      // used next time\n      desired_torque_last = desired_torque;\n\n      // *** torque real time rate limit check ***\n      violation |= rt_rate_limit_check(desired_torque, rt_torque_last, HYUNDAI_MAX_RT_DELTA);\n\n      // every RT_INTERVAL set the new limits\n      uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n      if (ts_elapsed > HYUNDAI_RT_INTERVAL) {\n        rt_torque_last = desired_torque;\n        ts_last = ts;\n      }\n    }\n\n    // no torque if controls is not allowed\n    if (!controls_allowed && (desired_torque != 0)) {\n      violation = 1;\n    }\n\n    // reset to 0 if either controls is not allowed or there's a violation\n    if (violation || !controls_allowed) {\n      desired_torque_last = 0;\n      rt_torque_last = 0;\n      ts_last = ts;\n    }\n\n    if (violation) {\n      tx = 0;\n    }\n  }\n\n  // FORCE CANCEL: safety check only relevant when spamming the cancel button.\n  // ensuring that only the cancel button press is sent (VAL 4) when controls are off.\n  // This avoids unintended engagements while still allowing resume spam\n  if ((addr == 1265) && !controls_allowed) {\n    if ((GET_BYTES_04(to_send) & 0x7) != 4) {\n      tx = 0;\n    }\n  }\n\n  // 1 allows the message through\n  return tx;\n}\n\nstatic int hyundai_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n\n  int bus_fwd = -1;\n  int addr = GET_ADDR(to_fwd);\n  // forward cam to ccan and viceversa, except lkas cmd\n  if (!relay_malfunction) {\n    if (bus_num == 0) {\n      bus_fwd = 2;\n    }\n    if ((bus_num == 2) && (addr != 832) && (addr != 1157)) {\n      bus_fwd = 0;\n    }\n  }\n  return bus_fwd;\n}\n\nstatic const addr_checks* hyundai_init(int16_t param) {\n  controls_allowed = false;\n  relay_malfunction_reset();\n\n  hyundai_legacy = false;\n  hyundai_ev_gas_signal = GET_FLAG(param, HYUNDAI_PARAM_EV_GAS);\n  hyundai_hybrid_gas_signal = !hyundai_ev_gas_signal && GET_FLAG(param, HYUNDAI_PARAM_HYBRID_GAS);\n  hyundai_rx_checks = (addr_checks){hyundai_addr_checks, HYUNDAI_ADDR_CHECK_LEN};\n  return &hyundai_rx_checks;\n}\n\nstatic const addr_checks* hyundai_legacy_init(int16_t param) {\n  controls_allowed = false;\n  relay_malfunction_reset();\n\n  hyundai_legacy = true;\n  hyundai_ev_gas_signal = GET_FLAG(param, HYUNDAI_PARAM_EV_GAS);\n  hyundai_hybrid_gas_signal = !hyundai_ev_gas_signal && GET_FLAG(param, HYUNDAI_PARAM_HYBRID_GAS);\n  hyundai_rx_checks = (addr_checks){hyundai_legacy_addr_checks, HYUNDAI_LEGACY_ADDR_CHECK_LEN};\n  return &hyundai_rx_checks;\n}\n\nconst safety_hooks hyundai_hooks = {\n  .init = hyundai_init,\n  .rx = hyundai_rx_hook,\n  .tx = hyundai_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = hyundai_fwd_hook,\n};\n\nconst safety_hooks hyundai_legacy_hooks = {\n  .init = hyundai_legacy_init,\n  .rx = hyundai_rx_hook,\n  .tx = hyundai_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = hyundai_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_mazda.h",
    "content": "// CAN msgs we care about\n#define MAZDA_LKAS          0x243\n#define MAZDA_CRZ_CTRL      0x21c\n#define MAZDA_CRZ_BTNS      0x09d\n#define MAZDA_STEER_TORQUE  0x240\n#define MAZDA_ENGINE_DATA   0x202\n#define MAZDA_PEDALS        0x165\n\n// CAN bus numbers\n#define MAZDA_MAIN 0\n#define MAZDA_AUX 1\n#define MAZDA_CAM 2\n\n#define MAZDA_MAX_STEER 2048\n\n// max delta torque allowed for real time checks\n#define MAZDA_MAX_RT_DELTA 940\n// 250ms between real time checks\n#define MAZDA_RT_INTERVAL 250000\n#define MAZDA_MAX_RATE_UP 10\n#define MAZDA_MAX_RATE_DOWN 25\n#define MAZDA_DRIVER_TORQUE_ALLOWANCE 15\n#define MAZDA_DRIVER_TORQUE_FACTOR 1\n#define MAZDA_MAX_TORQUE_ERROR 350\n\n// lkas enable speed 52kph, disable at 45kph\n#define MAZDA_LKAS_ENABLE_SPEED  5200\n#define MAZDA_LKAS_DISABLE_SPEED 4500\n\nconst CanMsg MAZDA_TX_MSGS[] = {{MAZDA_LKAS, 0, 8}, {MAZDA_CRZ_BTNS, 0, 8}};\nbool mazda_lkas_allowed = false;\n\nAddrCheckStruct mazda_addr_checks[] = {\n  {.msg = {{MAZDA_CRZ_CTRL,     0, 8, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{MAZDA_CRZ_BTNS,     0, 8, .expected_timestep = 100000U}, { 0 }, { 0 }}},\n  {.msg = {{MAZDA_STEER_TORQUE, 0, 8, .expected_timestep = 12000U}, { 0 }, { 0 }}},\n  {.msg = {{MAZDA_ENGINE_DATA,  0, 8, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{MAZDA_PEDALS,       0, 8, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n};\n#define MAZDA_ADDR_CHECKS_LEN (sizeof(mazda_addr_checks) / sizeof(mazda_addr_checks[0]))\naddr_checks mazda_rx_checks = {mazda_addr_checks, MAZDA_ADDR_CHECKS_LEN};\n\n// track msgs coming from OP so that we know what CAM msgs to drop and what to forward\nstatic int mazda_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n  bool valid = addr_safety_check(to_push, &mazda_rx_checks, NULL, NULL, NULL);\n  if (valid && (GET_BUS(to_push) == MAZDA_MAIN)) {\n    int addr = GET_ADDR(to_push);\n\n    if (addr == MAZDA_ENGINE_DATA) {\n      // sample speed: scale by 0.01 to get kph\n      int speed = (GET_BYTE(to_push, 2) << 8) | GET_BYTE(to_push, 3);\n\n      vehicle_moving = speed > 10; // moving when speed > 0.1 kph\n\n      // Enable LKAS at 52kph going up, disable at 45kph going down\n      if (speed > MAZDA_LKAS_ENABLE_SPEED) {\n        mazda_lkas_allowed = true;\n      } else if (speed < MAZDA_LKAS_DISABLE_SPEED) {\n        mazda_lkas_allowed = false;\n      } else {\n        // Misra-able appeasment block!\n      }\n    }\n\n    if (addr == MAZDA_STEER_TORQUE) {\n      int torque_driver_new = GET_BYTE(to_push, 0) - 127;\n      // update array of samples\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // enter controls on rising edge of ACC, exit controls on ACC off\n    if (addr == MAZDA_CRZ_CTRL) {\n      bool cruise_engaged = GET_BYTE(to_push, 0) & 8;\n      if (cruise_engaged) {\n        if (!cruise_engaged_prev) {\n          // do not engage until we hit the speed at which lkas is on\n          if (mazda_lkas_allowed) {\n            controls_allowed = 1;\n          } else {\n            controls_allowed = 0;\n            cruise_engaged = false;\n          }\n        }\n      } else {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    if (addr == MAZDA_ENGINE_DATA) {\n      gas_pressed = (GET_BYTE(to_push, 4) || (GET_BYTE(to_push, 5) & 0xF0));\n    }\n\n    if (addr == MAZDA_PEDALS) {\n      brake_pressed = (GET_BYTE(to_push, 0) & 0x10);\n    }\n\n    generic_rx_checks((addr == MAZDA_LKAS));\n  }\n  return valid;\n}\n\nstatic int mazda_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n  int bus = GET_BUS(to_send);\n\n  if (!msg_allowed(to_send, MAZDA_TX_MSGS, sizeof(MAZDA_TX_MSGS)/sizeof(MAZDA_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // Check if msg is sent on the main BUS\n  if (bus == MAZDA_MAIN) {\n\n    // steer cmd checks\n    if (addr == MAZDA_LKAS) {\n      int desired_torque = (((GET_BYTE(to_send, 0) & 0x0f) << 8) | GET_BYTE(to_send, 1)) - MAZDA_MAX_STEER;\n      bool violation = 0;\n      uint32_t ts = microsecond_timer_get();\n\n      if (controls_allowed) {\n\n        // *** global torque limit check ***\n        violation |= max_limit_check(desired_torque, MAZDA_MAX_STEER, -MAZDA_MAX_STEER);\n\n        // *** torque rate limit check ***\n        violation |= driver_limit_check(desired_torque, desired_torque_last, &torque_driver,\n                                        MAZDA_MAX_STEER, MAZDA_MAX_RATE_UP, MAZDA_MAX_RATE_DOWN,\n                                        MAZDA_DRIVER_TORQUE_ALLOWANCE, MAZDA_DRIVER_TORQUE_FACTOR);\n\n        // used next time\n        desired_torque_last = desired_torque;\n\n        // *** torque real time rate limit check ***\n        violation |= rt_rate_limit_check(desired_torque, rt_torque_last, MAZDA_MAX_RT_DELTA);\n\n        // every RT_INTERVAL set the new limits\n        uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n        if (ts_elapsed > ((uint32_t) MAZDA_RT_INTERVAL)) {\n          rt_torque_last = desired_torque;\n          ts_last = ts;\n        }\n      }\n\n      // no torque if controls is not allowed\n      if (!controls_allowed && (desired_torque != 0)) {\n        violation = 1;\n      }\n\n      // reset to 0 if either controls is not allowed or there's a violation\n      if (violation || !controls_allowed) {\n        desired_torque_last = 0;\n        rt_torque_last = 0;\n        ts_last = ts;\n      }\n\n      if (violation) {\n        tx = 0;\n      }\n    }\n  }\n  return tx;\n}\n\nstatic int mazda_fwd_hook(int bus, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int bus_fwd = -1;\n  if (!relay_malfunction) {\n    int addr = GET_ADDR(to_fwd);\n    if (bus == MAZDA_MAIN) {\n      bus_fwd = MAZDA_CAM;\n    } else if (bus == MAZDA_CAM) {\n      if (!(addr == MAZDA_LKAS)) {\n        bus_fwd = MAZDA_MAIN;\n      }\n    } else {\n      bus_fwd = -1;\n    }\n  }\n  return bus_fwd;\n}\n\nstatic const addr_checks* mazda_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  mazda_lkas_allowed = false;\n  return &mazda_rx_checks;\n}\n\nconst safety_hooks mazda_hooks = {\n  .init = mazda_init,\n  .rx = mazda_rx_hook,\n  .tx = mazda_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = mazda_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_nissan.h",
    "content": "\nconst uint32_t NISSAN_RT_INTERVAL = 250000;    // 250ms between real time checks\n\nconst struct lookup_t NISSAN_LOOKUP_ANGLE_RATE_UP = {\n  {2., 7., 17.},\n  {5., .8, .15}};\n\nconst struct lookup_t NISSAN_LOOKUP_ANGLE_RATE_DOWN = {\n  {2., 7., 17.},\n  {5., 3.5, .5}};\n\nconst int NISSAN_DEG_TO_CAN = 100;\n\nconst CanMsg NISSAN_TX_MSGS[] = {{0x169, 0, 8}, {0x2b1, 0, 8}, {0x4cc, 0, 8}, {0x20b, 2, 6}, {0x20b, 1, 6}, {0x280, 2, 8}};\n\n// Signals duplicated below due to the fact that these messages can come in on either CAN bus, depending on car model.\nAddrCheckStruct nissan_addr_checks[] = {\n  {.msg = {{0x2, 0, 5, .expected_timestep = 10000U},\n           {0x2, 1, 5, .expected_timestep = 10000U}, { 0 }}},  // STEER_ANGLE_SENSOR (100Hz)\n  {.msg = {{0x285, 0, 8, .expected_timestep = 20000U},\n           {0x285, 1, 8, .expected_timestep = 20000U}, { 0 }}}, // WHEEL_SPEEDS_REAR (50Hz)\n  {.msg = {{0x30f, 2, 3, .expected_timestep = 100000U},\n           {0x30f, 1, 3, .expected_timestep = 100000U}, { 0 }}}, // CRUISE_STATE (10Hz)\n  {.msg = {{0x15c, 0, 8, .expected_timestep = 20000U},\n           {0x15c, 1, 8, .expected_timestep = 20000U},\n           {0x239, 0, 8, .expected_timestep = 20000U}}}, // GAS_PEDAL (100Hz / 50Hz)\n  {.msg = {{0x454, 0, 8, .expected_timestep = 100000U},\n           {0x454, 1, 8, .expected_timestep = 100000U},\n           {0x1cc, 0, 4, .expected_timestep = 10000U}}}, // DOORS_LIGHTS (10Hz) / BRAKE (100Hz)\n};\n#define NISSAN_ADDR_CHECK_LEN (sizeof(nissan_addr_checks) / sizeof(nissan_addr_checks[0]))\naddr_checks nissan_rx_checks = {nissan_addr_checks, NISSAN_ADDR_CHECK_LEN};\n\n// EPS Location. false = V-CAN, true = C-CAN\nbool nissan_alt_eps = false;\n\nstatic int nissan_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &nissan_rx_checks, NULL, NULL, NULL);\n\n  if (valid) {\n    int bus = GET_BUS(to_push);\n    int addr = GET_ADDR(to_push);\n\n    if (((bus == 0) && (!nissan_alt_eps)) || ((bus == 1) && (nissan_alt_eps))) {\n      if (addr == 0x2) {\n        // Current steering angle\n        // Factor -0.1, little endian\n        int angle_meas_new = (GET_BYTES_04(to_push) & 0xFFFF);\n        // Need to multiply by 10 here as LKAS and Steering wheel are different base unit\n        angle_meas_new = to_signed(angle_meas_new, 16) * 10;\n\n        // update array of samples\n        update_sample(&angle_meas, angle_meas_new);\n      }\n\n      if (addr == 0x285) {\n        // Get current speed\n        // Factor 0.005\n        vehicle_speed = ((GET_BYTE(to_push, 2) << 8) | (GET_BYTE(to_push, 3))) * 0.005 / 3.6;\n        vehicle_moving = vehicle_speed > 0.;\n      }\n\n      // X-Trail 0x15c, Leaf 0x239\n      if ((addr == 0x15c) || (addr == 0x239)) {\n        if (addr == 0x15c){\n          gas_pressed = ((GET_BYTE(to_push, 5) << 2) | ((GET_BYTE(to_push, 6) >> 6) & 0x3)) > 3;\n        } else {\n          gas_pressed = GET_BYTE(to_push, 0) > 3;\n        }\n      }\n    }\n\n    // X-trail 0x454, Leaf  0x1cc\n    if ((addr == 0x454) || (addr == 0x1cc)) {\n      if (addr == 0x454){\n        brake_pressed = (GET_BYTE(to_push, 2) & 0x80) != 0;\n      } else {\n        brake_pressed = GET_BYTE(to_push, 0) > 3;\n      }\n    }\n\n    // Handle cruise enabled\n    if ((addr == 0x30f) && (((bus == 2) && (!nissan_alt_eps)) || ((bus == 1) && (nissan_alt_eps)))) {\n      bool cruise_engaged = (GET_BYTE(to_push, 0) >> 3) & 1;\n\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    generic_rx_checks((addr == 0x169) && (bus == 0));\n  }\n  return valid;\n}\n\n\nstatic int nissan_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n  bool violation = 0;\n\n  if (!msg_allowed(to_send, NISSAN_TX_MSGS, sizeof(NISSAN_TX_MSGS) / sizeof(NISSAN_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // steer cmd checks\n  if (addr == 0x169) {\n    int desired_angle = ((GET_BYTE(to_send, 0) << 10) | (GET_BYTE(to_send, 1) << 2) | ((GET_BYTE(to_send, 2) >> 6) & 0x3));\n    bool lka_active = (GET_BYTE(to_send, 6) >> 4) & 1;\n\n    // offeset 1310 * NISSAN_DEG_TO_CAN\n    desired_angle =  desired_angle - 131000;\n\n    if (controls_allowed && lka_active) {\n      // add 1 to not false trigger the violation\n      float delta_angle_float;\n      delta_angle_float = (interpolate(NISSAN_LOOKUP_ANGLE_RATE_UP, vehicle_speed) * NISSAN_DEG_TO_CAN) + 1.;\n      int delta_angle_up = (int)(delta_angle_float);\n      delta_angle_float =  (interpolate(NISSAN_LOOKUP_ANGLE_RATE_DOWN, vehicle_speed) * NISSAN_DEG_TO_CAN) + 1.;\n      int delta_angle_down = (int)(delta_angle_float);\n      int highest_desired_angle = desired_angle_last + ((desired_angle_last > 0) ? delta_angle_up : delta_angle_down);\n      int lowest_desired_angle = desired_angle_last - ((desired_angle_last >= 0) ? delta_angle_down : delta_angle_up);\n\n      // check for violation;\n      violation |= max_limit_check(desired_angle, highest_desired_angle, lowest_desired_angle);\n    }\n    desired_angle_last = desired_angle;\n\n    // desired steer angle should be the same as steer angle measured when controls are off\n    if ((!controls_allowed) &&\n          ((desired_angle < (angle_meas.min - 1)) ||\n          (desired_angle > (angle_meas.max + 1)))) {\n      violation = 1;\n    }\n\n    // no lka_enabled bit if controls not allowed\n    if (!controls_allowed && lka_active) {\n      violation = 1;\n    }\n  }\n\n  // acc button check, only allow cancel button to be sent\n  if (addr == 0x20b) {\n    // Violation of any button other than cancel is pressed\n    violation |= ((GET_BYTE(to_send, 1) & 0x3d) > 0);\n  }\n\n  if (violation) {\n    controls_allowed = 0;\n    tx = 0;\n  }\n\n  return tx;\n}\n\n\nstatic int nissan_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int bus_fwd = -1;\n  int addr = GET_ADDR(to_fwd);\n\n  if (bus_num == 0) {\n    int block_msg = (addr == 0x280); // CANCEL_MSG\n    if (!block_msg) {\n      bus_fwd = 2;  // ADAS\n    }\n  }\n\n  if (bus_num == 2) {\n    // 0x169 is LKAS, 0x2b1 LKAS_HUD, 0x4cc LKAS_HUD_INFO_MSG\n    int block_msg = ((addr == 0x169) || (addr == 0x2b1) || (addr == 0x4cc));\n    if (!block_msg) {\n      bus_fwd = 0;  // V-CAN\n    }\n  }\n\n  if (relay_malfunction) {\n    bus_fwd = -1;\n  }\n\n  // fallback to do not forward\n  return bus_fwd;\n}\n\nstatic const addr_checks* nissan_init(int16_t param) {\n  controls_allowed = 0;\n  nissan_alt_eps = param ? 1 : 0;\n  relay_malfunction_reset();\n  return &nissan_rx_checks;\n}\n\nconst safety_hooks nissan_hooks = {\n  .init = nissan_init,\n  .rx = nissan_rx_hook,\n  .tx = nissan_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = nissan_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_subaru.h",
    "content": "const int SUBARU_MAX_STEER = 2047; // 1s\n// real time torque limit to prevent controls spamming\n// the real time limit is 1500/sec\nconst int SUBARU_MAX_RT_DELTA = 940;          // max delta torque allowed for real time checks\nconst uint32_t SUBARU_RT_INTERVAL = 250000;    // 250ms between real time checks\nconst int SUBARU_MAX_RATE_UP = 50;\nconst int SUBARU_MAX_RATE_DOWN = 70;\nconst int SUBARU_DRIVER_TORQUE_ALLOWANCE = 60;\nconst int SUBARU_DRIVER_TORQUE_FACTOR = 10;\nconst int SUBARU_STANDSTILL_THRSLD = 20;  // about 1kph\n\nconst int SUBARU_L_DRIVER_TORQUE_ALLOWANCE = 75;\nconst int SUBARU_L_DRIVER_TORQUE_FACTOR = 10;\n\nconst CanMsg SUBARU_TX_MSGS[] = {{0x122, 0, 8}, {0x221, 0, 8}, {0x322, 0, 8}};\n#define SUBARU_TX_MSGS_LEN (sizeof(SUBARU_TX_MSGS) / sizeof(SUBARU_TX_MSGS[0]))\n\nAddrCheckStruct subaru_addr_checks[] = {\n  {.msg = {{ 0x40, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{0x119, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{0x139, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{0x13a, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{0x240, 0, 8, .check_checksum = true, .max_counter = 15U, .expected_timestep = 50000U}, { 0 }, { 0 }}},\n};\n#define SUBARU_ADDR_CHECK_LEN (sizeof(subaru_addr_checks) / sizeof(subaru_addr_checks[0]))\naddr_checks subaru_rx_checks = {subaru_addr_checks, SUBARU_ADDR_CHECK_LEN};\n\nconst CanMsg SUBARU_L_TX_MSGS[] = {{0x161, 0, 8}, {0x164, 0, 8}};\n#define SUBARU_L_TX_MSGS_LEN (sizeof(SUBARU_L_TX_MSGS) / sizeof(SUBARU_L_TX_MSGS[0]))\n\n// TODO: do checksum and counter checks after adding the signals to the outback dbc file\nAddrCheckStruct subaru_l_addr_checks[] = {\n  {.msg = {{0x140, 0, 8, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{0x371, 0, 8, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{0x144, 0, 8, .expected_timestep = 50000U}, { 0 }, { 0 }}},\n};\n#define SUBARU_L_ADDR_CHECK_LEN (sizeof(subaru_l_addr_checks) / sizeof(subaru_l_addr_checks[0]))\naddr_checks subaru_l_rx_checks = {subaru_addr_checks, SUBARU_L_ADDR_CHECK_LEN};\n\nstatic uint8_t subaru_get_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  return (uint8_t)GET_BYTE(to_push, 0);\n}\n\nstatic uint8_t subaru_get_counter(CAN_FIFOMailBox_TypeDef *to_push) {\n  return (uint8_t)(GET_BYTE(to_push, 1) & 0xF);\n}\n\nstatic uint8_t subaru_compute_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int addr = GET_ADDR(to_push);\n  int len = GET_LEN(to_push);\n  uint8_t checksum = (uint8_t)(addr) + (uint8_t)((unsigned int)(addr) >> 8U);\n  for (int i = 1; i < len; i++) {\n    checksum += (uint8_t)GET_BYTE(to_push, i);\n  }\n  return checksum;\n}\n\nstatic int subaru_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &subaru_rx_checks,\n                            subaru_get_checksum, subaru_compute_checksum, subaru_get_counter);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n    if (addr == 0x119) {\n      int torque_driver_new;\n      torque_driver_new = ((GET_BYTES_04(to_push) >> 16) & 0x7FF);\n      torque_driver_new = -1 * to_signed(torque_driver_new, 11);\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // enter controls on rising edge of ACC, exit controls on ACC off\n    if (addr == 0x240) {\n      int cruise_engaged = ((GET_BYTES_48(to_push) >> 9) & 1);\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    // sample wheel speed, averaging opposite corners\n    if (addr == 0x13a) {\n      int subaru_speed = (GET_BYTES_04(to_push) >> 12) & 0x1FFF;  // FR\n      subaru_speed += (GET_BYTES_48(to_push) >> 6) & 0x1FFF;  // RL\n      subaru_speed /= 2;\n      vehicle_moving = subaru_speed > SUBARU_STANDSTILL_THRSLD;\n    }\n\n    if (addr == 0x139) {\n      brake_pressed = (GET_BYTES_48(to_push) & 0xFFF0) > 0;\n    }\n\n    if (addr == 0x40) {\n      gas_pressed = GET_BYTE(to_push, 4) != 0;\n    }\n\n    generic_rx_checks((addr == 0x122));\n  }\n  return valid;\n}\n\nstatic int subaru_legacy_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &subaru_l_rx_checks, NULL, NULL, NULL);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n    if (addr == 0x371) {\n      int torque_driver_new;\n      torque_driver_new = (GET_BYTE(to_push, 3) >> 5) + (GET_BYTE(to_push, 4) << 3);\n      torque_driver_new = to_signed(torque_driver_new, 11);\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // enter controls on rising edge of ACC, exit controls on ACC off\n    if (addr == 0x144) {\n      int cruise_engaged = ((GET_BYTES_48(to_push) >> 17) & 1);\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    // sample wheel speed, averaging opposite corners\n    if (addr == 0xD4) {\n      int subaru_speed = (GET_BYTES_04(to_push) >> 16) & 0xFFFF;  // FR\n      subaru_speed += GET_BYTES_48(to_push) & 0xFFFF;  // RL\n      subaru_speed /= 2;\n      vehicle_moving = subaru_speed > SUBARU_STANDSTILL_THRSLD;\n    }\n\n    if (addr == 0xD1) {\n      brake_pressed = ((GET_BYTES_04(to_push) >> 16) & 0xFF) > 0;\n    }\n\n    if (addr == 0x140) {\n      gas_pressed = GET_BYTE(to_push, 0) != 0;\n    }\n\n    generic_rx_checks((addr == 0x164));\n  }\n  return valid;\n}\n\nstatic int subaru_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n\n  if (!msg_allowed(to_send, SUBARU_TX_MSGS, SUBARU_TX_MSGS_LEN)) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // steer cmd checks\n  if (addr == 0x122) {\n    int desired_torque = ((GET_BYTES_04(to_send) >> 16) & 0x1FFF);\n    bool violation = 0;\n    uint32_t ts = microsecond_timer_get();\n\n    desired_torque = -1 * to_signed(desired_torque, 13);\n\n    if (controls_allowed) {\n\n      // *** global torque limit check ***\n      violation |= max_limit_check(desired_torque, SUBARU_MAX_STEER, -SUBARU_MAX_STEER);\n\n      // *** torque rate limit check ***\n      violation |= driver_limit_check(desired_torque, desired_torque_last, &torque_driver,\n        SUBARU_MAX_STEER, SUBARU_MAX_RATE_UP, SUBARU_MAX_RATE_DOWN,\n        SUBARU_DRIVER_TORQUE_ALLOWANCE, SUBARU_DRIVER_TORQUE_FACTOR);\n\n      // used next time\n      desired_torque_last = desired_torque;\n\n      // *** torque real time rate limit check ***\n      violation |= rt_rate_limit_check(desired_torque, rt_torque_last, SUBARU_MAX_RT_DELTA);\n\n      // every RT_INTERVAL set the new limits\n      uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n      if (ts_elapsed > SUBARU_RT_INTERVAL) {\n        rt_torque_last = desired_torque;\n        ts_last = ts;\n      }\n    }\n\n    // no torque if controls is not allowed\n    if (!controls_allowed && (desired_torque != 0)) {\n      violation = 1;\n    }\n\n    // reset to 0 if either controls is not allowed or there's a violation\n    if (violation || !controls_allowed) {\n      desired_torque_last = 0;\n      rt_torque_last = 0;\n      ts_last = ts;\n    }\n\n    if (violation) {\n      tx = 0;\n    }\n\n  }\n  return tx;\n}\n\nstatic int subaru_legacy_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n\n  if (!msg_allowed(to_send, SUBARU_L_TX_MSGS, SUBARU_L_TX_MSGS_LEN)) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // steer cmd checks\n  if (addr == 0x164) {\n    int desired_torque = ((GET_BYTES_04(to_send) >> 8) & 0x1FFF);\n    bool violation = 0;\n    uint32_t ts = microsecond_timer_get();\n\n    desired_torque = -1 * to_signed(desired_torque, 13);\n\n    if (controls_allowed) {\n\n      // *** global torque limit check ***\n      violation |= max_limit_check(desired_torque, SUBARU_MAX_STEER, -SUBARU_MAX_STEER);\n\n      // *** torque rate limit check ***\n      violation |= driver_limit_check(desired_torque, desired_torque_last, &torque_driver,\n        SUBARU_MAX_STEER, SUBARU_MAX_RATE_UP, SUBARU_MAX_RATE_DOWN,\n        SUBARU_L_DRIVER_TORQUE_ALLOWANCE, SUBARU_L_DRIVER_TORQUE_FACTOR);\n\n      // used next time\n      desired_torque_last = desired_torque;\n\n      // *** torque real time rate limit check ***\n      violation |= rt_rate_limit_check(desired_torque, rt_torque_last, SUBARU_MAX_RT_DELTA);\n\n      // every RT_INTERVAL set the new limits\n      uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n      if (ts_elapsed > SUBARU_RT_INTERVAL) {\n        rt_torque_last = desired_torque;\n        ts_last = ts;\n      }\n    }\n\n    // no torque if controls is not allowed\n    if (!controls_allowed && (desired_torque != 0)) {\n      violation = 1;\n    }\n\n    // reset to 0 if either controls is not allowed or there's a violation\n    if (violation || !controls_allowed) {\n      desired_torque_last = 0;\n      rt_torque_last = 0;\n      ts_last = ts;\n    }\n\n    if (violation) {\n      tx = 0;\n    }\n\n  }\n  return tx;\n}\n\nstatic int subaru_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int bus_fwd = -1;\n\n  if (!relay_malfunction) {\n    if (bus_num == 0) {\n      bus_fwd = 2;  // Camera CAN\n    }\n    if (bus_num == 2) {\n      // Global platform\n      // 0x122 ES_LKAS\n      // 0x221 ES_Distance\n      // 0x322 ES_LKAS_State\n      int addr = GET_ADDR(to_fwd);\n      int block_msg = ((addr == 0x122) || (addr == 0x221) || (addr == 0x322));\n      if (!block_msg) {\n        bus_fwd = 0;  // Main CAN\n      }\n    }\n  }\n  // fallback to do not forward\n  return bus_fwd;\n}\n\nstatic int subaru_legacy_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int bus_fwd = -1;\n\n  if (!relay_malfunction) {\n    if (bus_num == 0) {\n      bus_fwd = 2;  // Camera CAN\n    }\n    if (bus_num == 2) {\n      // Preglobal platform\n      // 0x161 is ES_CruiseThrottle\n      // 0x164 is ES_LKAS\n      int addr = GET_ADDR(to_fwd);\n      int block_msg = ((addr == 0x161) || (addr == 0x164));\n      if (!block_msg) {\n        bus_fwd = 0;  // Main CAN\n      }\n    }\n  }\n  // fallback to do not forward\n  return bus_fwd;\n}\n\nstatic const addr_checks* subaru_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  return &subaru_rx_checks;\n}\n\nconst safety_hooks subaru_hooks = {\n  .init = subaru_init,\n  .rx = subaru_rx_hook,\n  .tx = subaru_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = subaru_fwd_hook,\n};\n\nstatic const addr_checks* subaru_legacy_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = false;\n  relay_malfunction_reset();\n  return &subaru_l_rx_checks;\n}\n\nconst safety_hooks subaru_legacy_hooks = {\n  .init = subaru_legacy_init,\n  .rx = subaru_legacy_rx_hook,\n  .tx = subaru_legacy_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = subaru_legacy_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_tesla.h",
    "content": "const struct lookup_t TESLA_LOOKUP_ANGLE_RATE_UP = {\n    {2., 7., 17.},\n    {5., .8, .25}};\n\nconst struct lookup_t TESLA_LOOKUP_ANGLE_RATE_DOWN = {\n    {2., 7., 17.},\n    {5., 3.5, .8}};\n\nconst int TESLA_DEG_TO_CAN = 10;\n\nconst CanMsg TESLA_TX_MSGS[] = {\n  {0x488, 0, 4},  // DAS_steeringControl\n  {0x45, 0, 8},   // STW_ACTN_RQ\n  {0x45, 2, 8},   // STW_ACTN_RQ\n};\n\nAddrCheckStruct tesla_addr_checks[] = {\n  {.msg = {{0x370, 0, 8, .expected_timestep = 40000U}, { 0 }, { 0 }}},   // EPAS_sysStatus (25Hz)\n  {.msg = {{0x108, 0, 8, .expected_timestep = 10000U}, { 0 }, { 0 }}},   // DI_torque1 (100Hz)\n  {.msg = {{0x118, 0, 6, .expected_timestep = 10000U}, { 0 }, { 0 }}},   // DI_torque2 (100Hz)\n  {.msg = {{0x155, 0, 8, .expected_timestep = 20000U}, { 0 }, { 0 }}},   // ESP_B (50Hz)\n  {.msg = {{0x20a, 0, 8, .expected_timestep = 20000U}, { 0 }, { 0 }}},   // BrakeMessage (50Hz)\n  {.msg = {{0x368, 0, 8, .expected_timestep = 100000U}, { 0 }, { 0 }}},  // DI_state (10Hz)\n  {.msg = {{0x318, 0, 8, .expected_timestep = 100000U}, { 0 }, { 0 }}},  // GTW_carState (10Hz)\n};\n#define TESLA_ADDR_CHECK_LEN (sizeof(tesla_addr_checks) / sizeof(tesla_addr_checks[0]))\naddr_checks tesla_rx_checks = {tesla_addr_checks, TESLA_ADDR_CHECK_LEN};\n\nbool autopilot_enabled = false;\n\nstatic int tesla_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n  bool valid = addr_safety_check(to_push, &tesla_rx_checks,\n                                 NULL, NULL, NULL);\n\n  if(valid) {\n    int bus = GET_BUS(to_push);\n    int addr = GET_ADDR(to_push);\n\n    if(bus == 0) {\n      if(addr == 0x370) {\n        // Steering angle: (0.1 * val) - 819.2 in deg.\n        // Store it 1/10 deg to match steering request\n        int angle_meas_new = (((GET_BYTE(to_push, 4) & 0x3F) << 8) | GET_BYTE(to_push, 5)) - 8192;\n        update_sample(&angle_meas, angle_meas_new);\n      }\n\n      if(addr == 0x155) {\n        // Vehicle speed: (0.01 * val) * KPH_TO_MPS\n        vehicle_speed = ((GET_BYTE(to_push, 5) << 8) | (GET_BYTE(to_push, 6))) * 0.01 / 3.6;\n        vehicle_moving = vehicle_speed > 0.;\n      }\n\n      if(addr == 0x108) {\n        // Gas pressed\n        gas_pressed = (GET_BYTE(to_push, 6) != 0);\n      }\n\n      if(addr == 0x20a) {\n        // Brake pressed\n        brake_pressed = (((GET_BYTE(to_push, 0) & 0x0C) >> 2) != 1);\n      }\n\n      if(addr == 0x368) {\n        // Cruise state\n        int cruise_state = (GET_BYTE(to_push, 1) >> 4);\n        bool cruise_engaged = (cruise_state == 2) ||  // ENABLED\n                              (cruise_state == 3) ||  // STANDSTILL\n                              (cruise_state == 4) ||  // OVERRIDE\n                              (cruise_state == 6) ||  // PRE_FAULT\n                              (cruise_state == 7);    // PRE_CANCEL\n\n        if(cruise_engaged && !cruise_engaged_prev) {\n          controls_allowed = 1;\n        }\n        if(!cruise_engaged) {\n          controls_allowed = 0;\n        }\n        cruise_engaged_prev = cruise_engaged;\n      }\n    }\n\n    if (bus == 2) {\n      if (addr == 0x399) {\n        // Autopilot status\n        int autopilot_status = (GET_BYTE(to_push, 0) & 0xF);\n        autopilot_enabled = (autopilot_status == 3) ||  // ACTIVE_1\n                            (autopilot_status == 4) ||  // ACTIVE_2\n                            (autopilot_status == 5);    // ACTIVE_NAVIGATE_ON_AUTOPILOT\n\n        if (autopilot_enabled) {\n          controls_allowed = 0;\n        }\n      }\n    }\n\n    // 0x488: DAS_steeringControl should not be received on bus 0\n    generic_rx_checks((addr == 0x488) && (bus == 0));\n  }\n\n  return valid;\n}\n\n\nstatic int tesla_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n  bool violation = false;\n\n  if(!msg_allowed(to_send, TESLA_TX_MSGS, sizeof(TESLA_TX_MSGS) / sizeof(TESLA_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if(relay_malfunction) {\n    tx = 0;\n  }\n\n  if(addr == 0x488) {\n    // Steering control: (0.1 * val) - 1638.35 in deg.\n    // We use 1/10 deg as a unit here\n    int raw_angle_can = (((GET_BYTE(to_send, 0) & 0x7F) << 8) | GET_BYTE(to_send, 1));\n    int desired_angle = raw_angle_can - 16384;\n    int steer_control_type = GET_BYTE(to_send, 2) >> 6;\n    bool steer_control_enabled = (steer_control_type != 0) &&  // NONE\n                                 (steer_control_type != 3);    // DISABLED\n\n    // Rate limit while steering\n    if(controls_allowed && steer_control_enabled) {\n      // Add 1 to not false trigger the violation\n      float delta_angle_float;\n      delta_angle_float = (interpolate(TESLA_LOOKUP_ANGLE_RATE_UP, vehicle_speed) * TESLA_DEG_TO_CAN);\n      int delta_angle_up = (int)(delta_angle_float) + 1;\n      delta_angle_float =  (interpolate(TESLA_LOOKUP_ANGLE_RATE_DOWN, vehicle_speed) * TESLA_DEG_TO_CAN);\n      int delta_angle_down = (int)(delta_angle_float) + 1;\n      int highest_desired_angle = desired_angle_last + ((desired_angle_last > 0) ? delta_angle_up : delta_angle_down);\n      int lowest_desired_angle = desired_angle_last - ((desired_angle_last >= 0) ? delta_angle_down : delta_angle_up);\n\n      // Check for violation;\n      violation |= max_limit_check(desired_angle, highest_desired_angle, lowest_desired_angle);\n    }\n    desired_angle_last = desired_angle;\n\n    // Angle should be the same as current angle while not steering\n    if(!controls_allowed && ((desired_angle < (angle_meas.min - 1)) || (desired_angle > (angle_meas.max + 1)))) {\n      violation = true;\n    }\n\n    // No angle control allowed when controls are not allowed\n    if(!controls_allowed && steer_control_enabled) {\n      violation = true;\n    }\n  }\n\n  if(addr == 0x45) {\n    // No button other than cancel can be sent by us\n    int control_lever_status = (GET_BYTE(to_send, 0) & 0x3F);\n    if((control_lever_status != 0) && (control_lever_status != 1)) {\n      violation = true;\n    }\n  }\n\n  if(violation) {\n    controls_allowed = 0;\n    tx = 0;\n  }\n\n  return tx;\n}\n\nstatic int tesla_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int bus_fwd = -1;\n  int addr = GET_ADDR(to_fwd);\n\n  if(bus_num == 0) {\n    // Chassis to autopilot\n    bus_fwd = 2;\n  }\n\n  if(bus_num == 2) {\n    // Autopilot to chassis\n    bool block_msg = ((addr == 0x488) && !autopilot_enabled);\n    if(!block_msg) {\n      bus_fwd = 0;\n    }\n  }\n\n  if(relay_malfunction) {\n    bus_fwd = -1;\n  }\n\n  return bus_fwd;\n}\n\nstatic const addr_checks* tesla_init(int16_t param) {\n  UNUSED(param);\n  controls_allowed = 0;\n  relay_malfunction_reset();\n  return &tesla_rx_checks;\n}\n\nconst safety_hooks tesla_hooks = {\n  .init = tesla_init,\n  .rx = tesla_rx_hook,\n  .tx = tesla_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = tesla_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_toyota.h",
    "content": "// global torque limit\nconst int TOYOTA_MAX_TORQUE = 1500;       // max torque cmd allowed ever\n\n// rate based torque limit + stay within actually applied\n// packet is sent at 100hz, so this limit is 1000/sec\nconst int TOYOTA_MAX_RATE_UP = 10;        // ramp up slow\nconst int TOYOTA_MAX_RATE_DOWN = 25;      // ramp down fast\nconst int TOYOTA_MAX_TORQUE_ERROR = 350;  // max torque cmd in excess of torque motor\n\n// real time torque limit to prevent controls spamming\n// the real time limit is 1500/sec\nconst int TOYOTA_MAX_RT_DELTA = 375;      // max delta torque allowed for real time checks\nconst uint32_t TOYOTA_RT_INTERVAL = 250000;    // 250ms between real time checks\n\n// longitudinal limits\nconst int TOYOTA_MAX_ACCEL = 2000;        // 2.0 m/s2\nconst int TOYOTA_MIN_ACCEL = -3500;       // -3.5 m/s2\n\nconst int TOYOTA_STANDSTILL_THRSLD = 100;  // 1kph\n\n// Roughly calculated using the offsets in openpilot +5%:\n// In openpilot: ((gas1_norm + gas2_norm)/2) > 15\n// gas_norm1 = ((gain_dbc*gas1) + offset1_dbc)\n// gas_norm2 = ((gain_dbc*gas2) + offset2_dbc)\n// In this safety: ((gas1 + gas2)/2) > THRESHOLD\nconst int TOYOTA_GAS_INTERCEPTOR_THRSLD = 845;\n#define TOYOTA_GET_INTERCEPTOR(msg) (((GET_BYTE((msg), 0) << 8) + GET_BYTE((msg), 1) + (GET_BYTE((msg), 2) << 8) + GET_BYTE((msg), 3)) / 2) // avg between 2 tracks\n\nconst CanMsg TOYOTA_TX_MSGS[] = {{0x283, 0, 7}, {0x2E6, 0, 8}, {0x2E7, 0, 8}, {0x33E, 0, 7}, {0x344, 0, 8}, {0x365, 0, 7}, {0x366, 0, 7}, {0x4CB, 0, 8},  // DSU bus 0\n                                 {0x128, 1, 6}, {0x141, 1, 4}, {0x160, 1, 8}, {0x161, 1, 7}, {0x470, 1, 4},  // DSU bus 1\n                                 {0x2E4, 0, 5}, {0x191, 0, 8}, {0x411, 0, 8}, {0x412, 0, 8}, {0x343, 0, 8}, {0x1D2, 0, 8},  // LKAS + ACC\n                                 {0x200, 0, 6}};  // interceptor\n\nAddrCheckStruct toyota_addr_checks[] = {\n  {.msg = {{ 0xaa, 0, 8, .check_checksum = false, .expected_timestep = 12000U}, { 0 }, { 0 }}},\n  {.msg = {{0x260, 0, 8, .check_checksum = true, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{0x1D2, 0, 8, .check_checksum = true, .expected_timestep = 30000U}, { 0 }, { 0 }}},\n  {.msg = {{0x224, 0, 8, .check_checksum = false, .expected_timestep = 25000U},\n           {0x226, 0, 8, .check_checksum = false, .expected_timestep = 25000U}, { 0 }}},\n};\n#define TOYOTA_ADDR_CHECKS_LEN (sizeof(toyota_addr_checks) / sizeof(toyota_addr_checks[0]))\naddr_checks toyota_rx_checks = {toyota_addr_checks, TOYOTA_ADDR_CHECKS_LEN};\n\n// global actuation limit states\nint toyota_dbc_eps_torque_factor = 100;   // conversion factor for STEER_TORQUE_EPS in %: see dbc file\n\nstatic uint8_t toyota_compute_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int addr = GET_ADDR(to_push);\n  int len = GET_LEN(to_push);\n  uint8_t checksum = (uint8_t)(addr) + (uint8_t)((unsigned int)(addr) >> 8U) + (uint8_t)(len);\n  for (int i = 0; i < (len - 1); i++) {\n    checksum += (uint8_t)GET_BYTE(to_push, i);\n  }\n  return checksum;\n}\n\nstatic uint8_t toyota_get_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int checksum_byte = GET_LEN(to_push) - 1;\n  return (uint8_t)(GET_BYTE(to_push, checksum_byte));\n}\n\nstatic int toyota_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &toyota_rx_checks,\n                                 toyota_get_checksum, toyota_compute_checksum, NULL);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n\n    // get eps motor torque (0.66 factor in dbc)\n    if (addr == 0x260) {\n      int torque_meas_new = (GET_BYTE(to_push, 5) << 8) | GET_BYTE(to_push, 6);\n      torque_meas_new = to_signed(torque_meas_new, 16);\n\n      // scale by dbc_factor\n      torque_meas_new = (torque_meas_new * toyota_dbc_eps_torque_factor) / 100;\n\n      // update array of sample\n      update_sample(&torque_meas, torque_meas_new);\n\n      // increase torque_meas by 1 to be conservative on rounding\n      torque_meas.min--;\n      torque_meas.max++;\n    }\n\n    // enter controls on rising edge of ACC, exit controls on ACC off\n    // exit controls on rising edge of gas press\n    if (addr == 0x1D2) {\n      // 5th bit is CRUISE_ACTIVE\n      int cruise_engaged = GET_BYTE(to_push, 0) & 0x20;\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      cruise_engaged_prev = cruise_engaged;\n\n      // sample gas pedal\n      if (!gas_interceptor_detected) {\n        gas_pressed = ((GET_BYTE(to_push, 0) >> 4) & 1) == 0;\n      }\n    }\n\n    // sample speed\n    if (addr == 0xaa) {\n      int speed = 0;\n      // sum 4 wheel speeds\n      for (int i=0; i<8; i+=2) {\n        int next_byte = i + 1;  // hack to deal with misra 10.8\n        speed += (GET_BYTE(to_push, i) << 8) + GET_BYTE(to_push, next_byte) - 0x1a6f;\n      }\n      vehicle_moving = ABS(speed / 4) > TOYOTA_STANDSTILL_THRSLD;\n    }\n\n    // most cars have brake_pressed on 0x226, corolla and rav4 on 0x224\n    if ((addr == 0x224) || (addr == 0x226)) {\n      int byte = (addr == 0x224) ? 0 : 4;\n      brake_pressed = ((GET_BYTE(to_push, byte) >> 5) & 1) != 0;\n    }\n\n    // sample gas interceptor\n    if (addr == 0x201) {\n      gas_interceptor_detected = 1;\n      int gas_interceptor = TOYOTA_GET_INTERCEPTOR(to_push);\n      gas_pressed = gas_interceptor > TOYOTA_GAS_INTERCEPTOR_THRSLD;\n\n      // TODO: remove this, only left in for gas_interceptor_prev test\n      gas_interceptor_prev = gas_interceptor;\n    }\n\n    generic_rx_checks((addr == 0x2E4));\n  }\n  return valid;\n}\n\nstatic int toyota_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n\n  int tx = 1;\n  int addr = GET_ADDR(to_send);\n  int bus = GET_BUS(to_send);\n\n  if (!msg_allowed(to_send, TOYOTA_TX_MSGS, sizeof(TOYOTA_TX_MSGS)/sizeof(TOYOTA_TX_MSGS[0]))) {\n    tx = 0;\n  }\n\n  if (relay_malfunction) {\n    tx = 0;\n  }\n\n  // Check if msg is sent on BUS 0\n  if (bus == 0) {\n\n    // GAS PEDAL: safety check\n    if (addr == 0x200) {\n      if (!controls_allowed) {\n        if (GET_BYTE(to_send, 0) || GET_BYTE(to_send, 1)) {\n          tx = 0;\n        }\n      }\n    }\n\n    // ACCEL: safety check on byte 1-2\n    if (addr == 0x343) {\n      int desired_accel = (GET_BYTE(to_send, 0) << 8) | GET_BYTE(to_send, 1);\n      desired_accel = to_signed(desired_accel, 16);\n      if (!controls_allowed) {\n        if (desired_accel != 0) {\n          tx = 0;\n        }\n      }\n      bool violation = max_limit_check(desired_accel, TOYOTA_MAX_ACCEL, TOYOTA_MIN_ACCEL);\n\n      if (violation) {\n        tx = 0;\n      }\n    }\n\n    // LTA steering check\n    // only sent to prevent dash errors, no actuation is accepted\n    if (addr == 0x191) {\n      // check the STEER_REQUEST, STEER_REQUEST_2, and STEER_ANGLE_CMD signals\n      bool lta_request = (GET_BYTE(to_send, 0) & 1) != 0;\n      bool lta_request2 = ((GET_BYTE(to_send, 3) >> 1) & 1) != 0;\n      int lta_angle = (GET_BYTE(to_send, 1) << 8) | GET_BYTE(to_send, 2);\n      lta_angle = to_signed(lta_angle, 16);\n\n      // block LTA msgs with actuation requests\n      if (lta_request || lta_request2 || (lta_angle != 0)) {\n        tx = 0;\n      }\n    }\n\n    // STEER: safety check on bytes 2-3\n    if (addr == 0x2E4) {\n      int desired_torque = (GET_BYTE(to_send, 1) << 8) | GET_BYTE(to_send, 2);\n      desired_torque = to_signed(desired_torque, 16);\n      bool violation = 0;\n\n      uint32_t ts = microsecond_timer_get();\n\n      if (controls_allowed) {\n\n        // *** global torque limit check ***\n        violation |= max_limit_check(desired_torque, TOYOTA_MAX_TORQUE, -TOYOTA_MAX_TORQUE);\n\n        // *** torque rate limit check ***\n        violation |= dist_to_meas_check(desired_torque, desired_torque_last,\n          &torque_meas, TOYOTA_MAX_RATE_UP, TOYOTA_MAX_RATE_DOWN, TOYOTA_MAX_TORQUE_ERROR);\n\n        // used next time\n        desired_torque_last = desired_torque;\n\n        // *** torque real time rate limit check ***\n        violation |= rt_rate_limit_check(desired_torque, rt_torque_last, TOYOTA_MAX_RT_DELTA);\n\n        // every RT_INTERVAL set the new limits\n        uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n        if (ts_elapsed > TOYOTA_RT_INTERVAL) {\n          rt_torque_last = desired_torque;\n          ts_last = ts;\n        }\n      }\n\n      // no torque if controls is not allowed\n      if (!controls_allowed && (desired_torque != 0)) {\n        violation = 1;\n      }\n\n      // reset to 0 if either controls is not allowed or there's a violation\n      if (violation || !controls_allowed) {\n        desired_torque_last = 0;\n        rt_torque_last = 0;\n        ts_last = ts;\n      }\n\n      if (violation) {\n        tx = 0;\n      }\n    }\n  }\n\n  return tx;\n}\n\nstatic const addr_checks* toyota_init(int16_t param) {\n  controls_allowed = 0;\n  relay_malfunction_reset();\n  gas_interceptor_detected = 0;\n  toyota_dbc_eps_torque_factor = param;\n  return &toyota_rx_checks;\n}\n\nstatic int toyota_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n\n  int bus_fwd = -1;\n  if (!relay_malfunction) {\n    if (bus_num == 0) {\n      bus_fwd = 2;\n    }\n    if (bus_num == 2) {\n      int addr = GET_ADDR(to_fwd);\n      // block stock lkas messages and stock acc messages (if OP is doing ACC)\n      // in TSS2, 0x191 is LTA which we need to block to avoid controls collision\n      int is_lkas_msg = ((addr == 0x2E4) || (addr == 0x412) || (addr == 0x191));\n      // in TSS2 the camera does ACC as well, so filter 0x343\n      int is_acc_msg = (addr == 0x343);\n      int block_msg = is_lkas_msg || is_acc_msg;\n      if (!block_msg) {\n        bus_fwd = 0;\n      }\n    }\n  }\n  return bus_fwd;\n}\n\nconst safety_hooks toyota_hooks = {\n  .init = toyota_init,\n  .rx = toyota_rx_hook,\n  .tx = toyota_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = toyota_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety/safety_volkswagen.h",
    "content": "// Safety-relevant steering constants for Volkswagen\nconst int VOLKSWAGEN_MAX_STEER = 300;               // 3.0 Nm (EPS side max of 3.0Nm with fault if violated)\nconst int VOLKSWAGEN_MAX_RT_DELTA = 188;            // 10 max rate up * 50Hz send rate * 250000 RT interval / 1000000 = 125 ; 125 * 1.5 for safety pad = 187.5\nconst uint32_t VOLKSWAGEN_RT_INTERVAL = 250000;     // 250ms between real time checks\nconst int VOLKSWAGEN_MAX_RATE_UP = 10;              // 5.0 Nm/s RoC limit (EPS rack has own soft-limit of 5.0 Nm/s)\nconst int VOLKSWAGEN_MAX_RATE_DOWN = 10;            // 5.0 Nm/s RoC limit (EPS rack has own soft-limit of 5.0 Nm/s)\nconst int VOLKSWAGEN_DRIVER_TORQUE_ALLOWANCE = 80;\nconst int VOLKSWAGEN_DRIVER_TORQUE_FACTOR = 3;\n\n// Safety-relevant CAN messages for the Volkswagen MQB platform\n#define MSG_ESP_19      0x0B2   // RX from ABS, for wheel speeds\n#define MSG_LH_EPS_03   0x09F   // RX from EPS, for driver steering torque\n#define MSG_ESP_05      0x106   // RX from ABS, for brake switch state\n#define MSG_TSK_06      0x120   // RX from ECU, for ACC status from drivetrain coordinator\n#define MSG_MOTOR_20    0x121   // RX from ECU, for driver throttle input\n#define MSG_HCA_01      0x126   // TX by OP, Heading Control Assist steering torque\n#define MSG_GRA_ACC_01  0x12B   // TX by OP, ACC control buttons for cancel/resume\n#define MSG_LDW_02      0x397   // TX by OP, Lane line recognition and text alerts\n\n// Transmit of GRA_ACC_01 is allowed on bus 0 and 2 to keep compatibility with gateway and camera integration\nconst CanMsg VOLKSWAGEN_MQB_TX_MSGS[] = {{MSG_HCA_01, 0, 8}, {MSG_GRA_ACC_01, 0, 8}, {MSG_GRA_ACC_01, 2, 8}, {MSG_LDW_02, 0, 8}};\n#define VOLKSWAGEN_MQB_TX_MSGS_LEN (sizeof(VOLKSWAGEN_MQB_TX_MSGS) / sizeof(VOLKSWAGEN_MQB_TX_MSGS[0]))\n\nAddrCheckStruct volkswagen_mqb_addr_checks[] = {\n  {.msg = {{MSG_ESP_19, 0, 8, .check_checksum = false, .max_counter = 0U,  .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_LH_EPS_03, 0, 8, .check_checksum = true,  .max_counter = 15U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_ESP_05, 0, 8, .check_checksum = true,  .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_TSK_06, 0, 8, .check_checksum = true,  .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_MOTOR_20, 0, 8, .check_checksum = true,  .max_counter = 15U, .expected_timestep = 20000U}, { 0 }, { 0 }}},\n};\n#define VOLKSWAGEN_MQB_ADDR_CHECKS_LEN (sizeof(volkswagen_mqb_addr_checks) / sizeof(volkswagen_mqb_addr_checks[0]))\naddr_checks volkswagen_mqb_rx_checks = {volkswagen_mqb_addr_checks, VOLKSWAGEN_MQB_ADDR_CHECKS_LEN};\n\n// Safety-relevant CAN messages for the Volkswagen PQ35/PQ46/NMS platforms\n#define MSG_LENKHILFE_3 0x0D0   // RX from EPS, for steering angle and driver steering torque\n#define MSG_HCA_1       0x0D2   // TX by OP, Heading Control Assist steering torque\n#define MSG_MOTOR_2     0x288   // RX from ECU, for CC state and brake switch state\n#define MSG_MOTOR_3     0x380   // RX from ECU, for driver throttle input\n#define MSG_GRA_NEU     0x38A   // TX by OP, ACC control buttons for cancel/resume\n#define MSG_BREMSE_3    0x4A0   // RX from ABS, for wheel speeds\n#define MSG_LDW_1       0x5BE   // TX by OP, Lane line recognition and text alerts\n\n// Transmit of GRA_Neu is allowed on bus 0 and 2 to keep compatibility with gateway and camera integration\nconst CanMsg VOLKSWAGEN_PQ_TX_MSGS[] = {{MSG_HCA_1, 0, 5}, {MSG_GRA_NEU, 0, 4}, {MSG_GRA_NEU, 2, 4}, {MSG_LDW_1, 0, 8}};\n#define VOLKSWAGEN_PQ_TX_MSGS_LEN (sizeof(VOLKSWAGEN_PQ_TX_MSGS) / sizeof(VOLKSWAGEN_PQ_TX_MSGS[0]))\n\nAddrCheckStruct volkswagen_pq_addr_checks[] = {\n  {.msg = {{MSG_LENKHILFE_3, 0, 6, .check_checksum = true,  .max_counter = 15U, .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_MOTOR_2, 0, 8, .check_checksum = false, .max_counter = 0U,  .expected_timestep = 20000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_MOTOR_3, 0, 8, .check_checksum = false, .max_counter = 0U,  .expected_timestep = 10000U}, { 0 }, { 0 }}},\n  {.msg = {{MSG_BREMSE_3, 0, 8, .check_checksum = false, .max_counter = 0U,  .expected_timestep = 10000U}, { 0 }, { 0 }}},\n};\n#define VOLKSWAGEN_PQ_ADDR_CHECKS_LEN (sizeof(volkswagen_pq_addr_checks) / sizeof(volkswagen_pq_addr_checks[0]))\naddr_checks volkswagen_pq_rx_checks = {volkswagen_pq_addr_checks, VOLKSWAGEN_PQ_ADDR_CHECKS_LEN};\n\nint volkswagen_torque_msg = 0;\nint volkswagen_lane_msg = 0;\nuint8_t volkswagen_crc8_lut_8h2f[256]; // Static lookup table for CRC8 poly 0x2F, aka 8H2F/AUTOSAR\n\n\nstatic uint8_t volkswagen_get_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  return (uint8_t)GET_BYTE(to_push, 0);\n}\n\nstatic uint8_t volkswagen_mqb_get_counter(CAN_FIFOMailBox_TypeDef *to_push) {\n  // MQB message counters are consistently found at LSB 8.\n  return (uint8_t)GET_BYTE(to_push, 1) & 0xFU;\n}\n\nstatic uint8_t volkswagen_pq_get_counter(CAN_FIFOMailBox_TypeDef *to_push) {\n  // Few PQ messages have counters, and their offsets are inconsistent. This\n  // function works only for Lenkhilfe_3 at this time.\n  return (uint8_t)(GET_BYTE(to_push, 1) & 0xF0U) >> 4;\n}\n\nstatic uint8_t volkswagen_mqb_compute_crc(CAN_FIFOMailBox_TypeDef *to_push) {\n  int addr = GET_ADDR(to_push);\n  int len = GET_LEN(to_push);\n\n  // This is CRC-8H2F/AUTOSAR with a twist. See the OpenDBC implementation\n  // of this algorithm for a version with explanatory comments.\n\n  uint8_t crc = 0xFFU;\n  for (int i = 1; i < len; i++) {\n    crc ^= (uint8_t)GET_BYTE(to_push, i);\n    crc = volkswagen_crc8_lut_8h2f[crc];\n  }\n\n  uint8_t counter = volkswagen_mqb_get_counter(to_push);\n  switch(addr) {\n    case MSG_LH_EPS_03:\n      crc ^= (uint8_t[]){0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5,0xF5}[counter];\n      break;\n    case MSG_ESP_05:\n      crc ^= (uint8_t[]){0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07}[counter];\n      break;\n    case MSG_TSK_06:\n      crc ^= (uint8_t[]){0xC4,0xE2,0x4F,0xE4,0xF8,0x2F,0x56,0x81,0x9F,0xE5,0x83,0x44,0x05,0x3F,0x97,0xDF}[counter];\n      break;\n    case MSG_MOTOR_20:\n      crc ^= (uint8_t[]){0xE9,0x65,0xAE,0x6B,0x7B,0x35,0xE5,0x5F,0x4E,0xC7,0x86,0xA2,0xBB,0xDD,0xEB,0xB4}[counter];\n      break;\n    default: // Undefined CAN message, CRC check expected to fail\n      break;\n  }\n  crc = volkswagen_crc8_lut_8h2f[crc];\n\n  return crc ^ 0xFFU;\n}\n\nstatic uint8_t volkswagen_pq_compute_checksum(CAN_FIFOMailBox_TypeDef *to_push) {\n  int len = GET_LEN(to_push);\n  uint8_t checksum = 0U;\n\n  for (int i = 1; i < len; i++) {\n    checksum ^= (uint8_t)GET_BYTE(to_push, i);\n  }\n\n  return checksum;\n}\n\nstatic const addr_checks* volkswagen_mqb_init(int16_t param) {\n  UNUSED(param);\n\n  controls_allowed = false;\n  relay_malfunction_reset();\n  volkswagen_torque_msg = MSG_HCA_01;\n  volkswagen_lane_msg = MSG_LDW_02;\n  gen_crc_lookup_table(0x2F, volkswagen_crc8_lut_8h2f);\n  return &volkswagen_mqb_rx_checks;\n}\n\nstatic const addr_checks* volkswagen_pq_init(int16_t param) {\n  UNUSED(param);\n\n  controls_allowed = false;\n  relay_malfunction_reset();\n  volkswagen_torque_msg = MSG_HCA_1;\n  volkswagen_lane_msg = MSG_LDW_1;\n  return &volkswagen_pq_rx_checks;\n}\n\nstatic int volkswagen_mqb_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &volkswagen_mqb_rx_checks,\n                                 volkswagen_get_checksum, volkswagen_mqb_compute_crc, volkswagen_mqb_get_counter);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n\n    // Update in-motion state by sampling front wheel speeds\n    // Signal: ESP_19.ESP_VL_Radgeschw_02 (front left) in scaled km/h\n    // Signal: ESP_19.ESP_VR_Radgeschw_02 (front right) in scaled km/h\n    if (addr == MSG_ESP_19) {\n      int wheel_speed_fl = GET_BYTE(to_push, 4) | (GET_BYTE(to_push, 5) << 8);\n      int wheel_speed_fr = GET_BYTE(to_push, 6) | (GET_BYTE(to_push, 7) << 8);\n      // Check for average front speed in excess of 0.3m/s, 1.08km/h\n      // DBC speed scale 0.0075: 0.3m/s = 144, sum both wheels to compare\n      vehicle_moving = (wheel_speed_fl + wheel_speed_fr) > 288;\n    }\n\n    // Update driver input torque samples\n    // Signal: LH_EPS_03.EPS_Lenkmoment (absolute torque)\n    // Signal: LH_EPS_03.EPS_VZ_Lenkmoment (direction)\n    if (addr == MSG_LH_EPS_03) {\n      int torque_driver_new = GET_BYTE(to_push, 5) | ((GET_BYTE(to_push, 6) & 0x1F) << 8);\n      int sign = (GET_BYTE(to_push, 6) & 0x80) >> 7;\n      if (sign == 1) {\n        torque_driver_new *= -1;\n      }\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // Enter controls on rising edge of stock ACC, exit controls if stock ACC disengages\n    // Signal: TSK_06.TSK_Status\n    if (addr == MSG_TSK_06) {\n      int acc_status = (GET_BYTE(to_push, 3) & 0x7);\n      int cruise_engaged = ((acc_status == 3) || (acc_status == 4) || (acc_status == 5)) ? 1 : 0;\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    // Signal: Motor_20.MO_Fahrpedalrohwert_01\n    if (addr == MSG_MOTOR_20) {\n      gas_pressed = ((GET_BYTES_04(to_push) >> 12) & 0xFF) != 0;\n    }\n\n    // Signal: ESP_05.ESP_Fahrer_bremst\n    if (addr == MSG_ESP_05) {\n      brake_pressed = (GET_BYTE(to_push, 3) & 0x4) >> 2;\n    }\n\n    generic_rx_checks((addr == MSG_HCA_01));\n  }\n  return valid;\n}\n\nstatic int volkswagen_pq_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n\n  bool valid = addr_safety_check(to_push, &volkswagen_pq_rx_checks,\n                                volkswagen_get_checksum, volkswagen_pq_compute_checksum, volkswagen_pq_get_counter);\n\n  if (valid && (GET_BUS(to_push) == 0)) {\n    int addr = GET_ADDR(to_push);\n\n    // Update in-motion state by sampling front wheel speeds\n    // Signal: Bremse_3.Radgeschw__VL_4_1 (front left)\n    // Signal: Bremse_3.Radgeschw__VR_4_1 (front right)\n    if (addr == MSG_BREMSE_3) {\n      int wheel_speed_fl = (GET_BYTE(to_push, 0) | (GET_BYTE(to_push, 1) << 8)) >> 1;\n      int wheel_speed_fr = (GET_BYTE(to_push, 2) | (GET_BYTE(to_push, 3) << 8)) >> 1;\n      // Check for average front speed in excess of 0.3m/s, 1.08km/h\n      // DBC speed scale 0.01: 0.3m/s = 108, sum both wheels to compare\n      vehicle_moving = (wheel_speed_fl + wheel_speed_fr) > 216;\n    }\n\n    // Update driver input torque samples\n    // Signal: Lenkhilfe_3.LH3_LM (absolute torque)\n    // Signal: Lenkhilfe_3.LH3_LMSign (direction)\n    if (addr == MSG_LENKHILFE_3) {\n      int torque_driver_new = GET_BYTE(to_push, 2) | ((GET_BYTE(to_push, 3) & 0x3) << 8);\n      int sign = (GET_BYTE(to_push, 3) & 0x4) >> 2;\n      if (sign == 1) {\n        torque_driver_new *= -1;\n      }\n      update_sample(&torque_driver, torque_driver_new);\n    }\n\n    // Enter controls on rising edge of stock ACC, exit controls if stock ACC disengages\n    // Signal: Motor_2.GRA_Status\n    if (addr == MSG_MOTOR_2) {\n      int acc_status = (GET_BYTE(to_push, 2) & 0xC0) >> 6;\n      int cruise_engaged = ((acc_status == 1) || (acc_status == 2)) ? 1 : 0;\n      if (cruise_engaged && !cruise_engaged_prev) {\n        controls_allowed = 1;\n      }\n      if (!cruise_engaged) {\n        controls_allowed = 0;\n      }\n      cruise_engaged_prev = cruise_engaged;\n    }\n\n    // Signal: Motor_3.Fahrpedal_Rohsignal\n    if (addr == MSG_MOTOR_3) {\n      gas_pressed = (GET_BYTE(to_push, 2));\n    }\n\n    // Signal: Motor_2.Bremslichtschalter\n    if (addr == MSG_MOTOR_2) {\n      brake_pressed = (GET_BYTE(to_push, 2) & 0x1);\n    }\n\n    generic_rx_checks((addr == MSG_HCA_1));\n  }\n  return valid;\n}\n\nstatic bool volkswagen_steering_check(int desired_torque) {\n  bool violation = false;\n  uint32_t ts = microsecond_timer_get();\n\n  if (controls_allowed) {\n    // *** global torque limit check ***\n    violation |= max_limit_check(desired_torque, VOLKSWAGEN_MAX_STEER, -VOLKSWAGEN_MAX_STEER);\n\n    // *** torque rate limit check ***\n    violation |= driver_limit_check(desired_torque, desired_torque_last, &torque_driver,\n      VOLKSWAGEN_MAX_STEER, VOLKSWAGEN_MAX_RATE_UP, VOLKSWAGEN_MAX_RATE_DOWN,\n      VOLKSWAGEN_DRIVER_TORQUE_ALLOWANCE, VOLKSWAGEN_DRIVER_TORQUE_FACTOR);\n    desired_torque_last = desired_torque;\n\n    // *** torque real time rate limit check ***\n    violation |= rt_rate_limit_check(desired_torque, rt_torque_last, VOLKSWAGEN_MAX_RT_DELTA);\n\n    // every RT_INTERVAL set the new limits\n    uint32_t ts_elapsed = get_ts_elapsed(ts, ts_last);\n    if (ts_elapsed > VOLKSWAGEN_RT_INTERVAL) {\n      rt_torque_last = desired_torque;\n      ts_last = ts;\n    }\n  }\n\n  // no torque if controls is not allowed\n  if (!controls_allowed && (desired_torque != 0)) {\n    violation = true;\n  }\n\n  // reset to 0 if either controls is not allowed or there's a violation\n  if (violation || !controls_allowed) {\n    desired_torque_last = 0;\n    rt_torque_last = 0;\n    ts_last = ts;\n  }\n\n  return violation;\n}\n\nstatic int volkswagen_mqb_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int addr = GET_ADDR(to_send);\n  int tx = 1;\n\n  if (!msg_allowed(to_send, VOLKSWAGEN_MQB_TX_MSGS, VOLKSWAGEN_MQB_TX_MSGS_LEN) || relay_malfunction) {\n    tx = 0;\n  }\n\n  // Safety check for HCA_01 Heading Control Assist torque\n  // Signal: HCA_01.Assist_Torque (absolute torque)\n  // Signal: HCA_01.Assist_VZ (direction)\n  if (addr == MSG_HCA_01) {\n    int desired_torque = GET_BYTE(to_send, 2) | ((GET_BYTE(to_send, 3) & 0x3F) << 8);\n    int sign = (GET_BYTE(to_send, 3) & 0x80) >> 7;\n    if (sign == 1) {\n      desired_torque *= -1;\n    }\n\n    if (volkswagen_steering_check(desired_torque)) {\n      tx = 0;\n    }\n  }\n\n  // FORCE CANCEL: ensuring that only the cancel button press is sent when controls are off.\n  // This avoids unintended engagements while still allowing resume spam\n  if ((addr == MSG_GRA_ACC_01) && !controls_allowed) {\n    // disallow resume and set: bits 16 and 19\n    if ((GET_BYTE(to_send, 2) & 0x9) != 0) {\n      tx = 0;\n    }\n  }\n\n  // 1 allows the message through\n  return tx;\n}\n\nstatic int volkswagen_pq_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  int addr = GET_ADDR(to_send);\n  int tx = 1;\n\n  if (!msg_allowed(to_send, VOLKSWAGEN_PQ_TX_MSGS, VOLKSWAGEN_PQ_TX_MSGS_LEN) || relay_malfunction) {\n    tx = 0;\n  }\n\n  // Safety check for HCA_1 Heading Control Assist torque\n  // Signal: HCA_1.LM_Offset (absolute torque)\n  // Signal: HCA_1.LM_Offsign (direction)\n  if (addr == MSG_HCA_1) {\n    int desired_torque = GET_BYTE(to_send, 2) | ((GET_BYTE(to_send, 3) & 0x7F) << 8);\n    desired_torque = desired_torque / 32;  // DBC scale from PQ network to centi-Nm\n    int sign = (GET_BYTE(to_send, 3) & 0x80) >> 7;\n    if (sign == 1) {\n      desired_torque *= -1;\n    }\n\n    if (volkswagen_steering_check(desired_torque)) {\n      tx = 0;\n    }\n  }\n\n  // FORCE CANCEL: ensuring that only the cancel button press is sent when controls are off.\n  // This avoids unintended engagements while still allowing resume spam\n  if ((addr == MSG_GRA_NEU) && !controls_allowed) {\n    // disallow resume and set: bits 16 and 17\n    if ((GET_BYTE(to_send, 2) & 0x3) != 0) {\n      tx = 0;\n    }\n  }\n\n  // 1 allows the message through\n  return tx;\n}\n\nstatic int volkswagen_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  int addr = GET_ADDR(to_fwd);\n  int bus_fwd = -1;\n\n  if (!relay_malfunction) {\n    switch (bus_num) {\n      case 0:\n        // Forward all traffic from the Extended CAN onward\n        bus_fwd = 2;\n        break;\n      case 2:\n        if ((addr == volkswagen_torque_msg) || (addr == volkswagen_lane_msg)) {\n          // OP takes control of the Heading Control Assist and Lane Departure Warning messages from the camera\n          bus_fwd = -1;\n        } else {\n          // Forward all remaining traffic from Extended CAN devices to J533 gateway\n          bus_fwd = 0;\n        }\n        break;\n      default:\n        // No other buses should be in use; fallback to do-not-forward\n        bus_fwd = -1;\n        break;\n    }\n  }\n  return bus_fwd;\n}\n\n// Volkswagen MQB platform\nconst safety_hooks volkswagen_mqb_hooks = {\n  .init = volkswagen_mqb_init,\n  .rx = volkswagen_mqb_rx_hook,\n  .tx = volkswagen_mqb_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = volkswagen_fwd_hook,\n};\n\n// Volkswagen PQ35/PQ46/NMS platforms\nconst safety_hooks volkswagen_pq_hooks = {\n  .init = volkswagen_pq_init,\n  .rx = volkswagen_pq_rx_hook,\n  .tx = volkswagen_pq_tx_hook,\n  .tx_lin = nooutput_tx_lin_hook,\n  .fwd = volkswagen_fwd_hook,\n};\n"
  },
  {
    "path": "panda/board/safety.h",
    "content": "// include first, needed by safety policies\n#include \"safety_declarations.h\"\n// Include the actual safety policies.\n#include \"safety/safety_defaults.h\"\n#include \"safety/safety_honda.h\"\n#include \"safety/safety_toyota.h\"\n#include \"safety/safety_tesla.h\"\n#include \"safety/safety_gm_ascm.h\"\n#include \"safety/safety_gm.h\"\n#include \"safety/safety_ford.h\"\n#include \"safety/safety_hyundai.h\"\n#include \"safety/safety_chrysler.h\"\n#include \"safety/safety_subaru.h\"\n#include \"safety/safety_mazda.h\"\n#include \"safety/safety_nissan.h\"\n#include \"safety/safety_volkswagen.h\"\n#include \"safety/safety_elm327.h\"\n\n// from cereal.car.CarParams.SafetyModel\n#define SAFETY_SILENT 0U\n#define SAFETY_HONDA_NIDEC 1U\n#define SAFETY_TOYOTA 2U\n#define SAFETY_ELM327 3U\n#define SAFETY_GM 4U\n#define SAFETY_HONDA_BOSCH_GIRAFFE 5U\n#define SAFETY_FORD 6U\n#define SAFETY_HYUNDAI 8U\n#define SAFETY_CHRYSLER 9U\n#define SAFETY_TESLA 10U\n#define SAFETY_SUBARU 11U\n#define SAFETY_MAZDA 13U\n#define SAFETY_NISSAN 14U\n#define SAFETY_VOLKSWAGEN_MQB 15U\n#define SAFETY_ALLOUTPUT 17U\n#define SAFETY_GM_ASCM 18U\n#define SAFETY_NOOUTPUT 19U\n#define SAFETY_HONDA_BOSCH_HARNESS 20U\n#define SAFETY_VOLKSWAGEN_PQ 21U\n#define SAFETY_SUBARU_LEGACY 22U\n#define SAFETY_HYUNDAI_LEGACY 23U\n#define SAFETY_HYUNDAI_COMMUNITY 24U\n\nuint16_t current_safety_mode = SAFETY_SILENT;\nint16_t current_safety_param = 0;\nconst safety_hooks *current_hooks = &nooutput_hooks;\nconst addr_checks *current_rx_checks = &default_rx_checks;\n\nint safety_rx_hook(CAN_FIFOMailBox_TypeDef *to_push) {\n  return current_hooks->rx(to_push);\n}\n\nint safety_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) {\n  return current_hooks->tx(to_send);\n}\n\nint safety_tx_lin_hook(int lin_num, uint8_t *data, int len) {\n  return current_hooks->tx_lin(lin_num, data, len);\n}\n\nint safety_fwd_hook(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd) {\n  return current_hooks->fwd(bus_num, to_fwd);\n}\n\n// Given a CRC-8 poly, generate a static lookup table to use with a fast CRC-8\n// algorithm. Called at init time for safety modes using CRC-8.\nvoid gen_crc_lookup_table(uint8_t poly, uint8_t crc_lut[]) {\n  for (int i = 0; i < 256; i++) {\n    uint8_t crc = i;\n    for (int j = 0; j < 8; j++) {\n      if ((crc & 0x80U) != 0U)\n        crc = (uint8_t)((crc << 1) ^ poly);\n      else\n        crc <<= 1;\n    }\n    crc_lut[i] = crc;\n  }\n}\n\nbool msg_allowed(CAN_FIFOMailBox_TypeDef *to_send, const CanMsg msg_list[], int len) {\n  int addr = GET_ADDR(to_send);\n  int bus = GET_BUS(to_send);\n  int length = GET_LEN(to_send);\n\n  bool allowed = false;\n  for (int i = 0; i < len; i++) {\n    if ((addr == msg_list[i].addr) && (bus == msg_list[i].bus) && (length == msg_list[i].len)) {\n      allowed = true;\n      break;\n    }\n  }\n  return allowed;\n}\n\n// compute the time elapsed (in microseconds) from 2 counter samples\n// case where ts < ts_last is ok: overflow is properly re-casted into uint32_t\nuint32_t get_ts_elapsed(uint32_t ts, uint32_t ts_last) {\n  return ts - ts_last;\n}\n\nint get_addr_check_index(CAN_FIFOMailBox_TypeDef *to_push, AddrCheckStruct addr_list[], const int len) {\n  int bus = GET_BUS(to_push);\n  int addr = GET_ADDR(to_push);\n  int length = GET_LEN(to_push);\n\n  int index = -1;\n  for (int i = 0; i < len; i++) {\n    // if multiple msgs are allowed, determine which one is present on the bus\n    if (!addr_list[i].msg_seen) {\n      for (uint8_t j = 0U; addr_list[i].msg[j].addr != 0; j++) {\n        if ((addr == addr_list[i].msg[j].addr) && (bus == addr_list[i].msg[j].bus) &&\n              (length == addr_list[i].msg[j].len)) {\n          addr_list[i].index = j;\n          addr_list[i].msg_seen = true;\n          break;\n        }\n      }\n    }\n\n    int idx = addr_list[i].index;\n    if ((addr == addr_list[i].msg[idx].addr) && (bus == addr_list[i].msg[idx].bus) &&\n        (length == addr_list[i].msg[idx].len)) {\n      index = i;\n      break;\n    }\n  }\n  return index;\n}\n\n// 1Hz safety function called by main. Now just a check for lagging safety messages\nvoid safety_tick(const addr_checks *rx_checks) {\n  uint32_t ts = microsecond_timer_get();\n  if (rx_checks != NULL) {\n    for (int i=0; i < rx_checks->len; i++) {\n      uint32_t elapsed_time = get_ts_elapsed(ts, rx_checks->check[i].last_timestamp);\n      // lag threshold is max of: 1s and MAX_MISSED_MSGS * expected timestep.\n      // Quite conservative to not risk false triggers.\n      // 2s of lag is worse case, since the function is called at 1Hz\n      bool lagging = elapsed_time > MAX(rx_checks->check[i].msg[rx_checks->check[i].index].expected_timestep * MAX_MISSED_MSGS, 1e6);\n      rx_checks->check[i].lagging = lagging;\n      if (lagging) {\n        controls_allowed = 0;\n      }\n    }\n  }\n}\n\nvoid update_counter(AddrCheckStruct addr_list[], int index, uint8_t counter) {\n  if (index != -1) {\n    uint8_t expected_counter = (addr_list[index].last_counter + 1U) % (addr_list[index].msg[addr_list[index].index].max_counter + 1U);\n    addr_list[index].wrong_counters += (expected_counter == counter) ? -1 : 1;\n    addr_list[index].wrong_counters = MAX(MIN(addr_list[index].wrong_counters, MAX_WRONG_COUNTERS), 0);\n    addr_list[index].last_counter = counter;\n  }\n}\n\nbool is_msg_valid(AddrCheckStruct addr_list[], int index) {\n  bool valid = true;\n  if (index != -1) {\n    if ((!addr_list[index].valid_checksum) || (addr_list[index].wrong_counters >= MAX_WRONG_COUNTERS)) {\n      valid = false;\n      controls_allowed = 0;\n    }\n  }\n  return valid;\n}\n\nvoid update_addr_timestamp(AddrCheckStruct addr_list[], int index) {\n  if (index != -1) {\n    uint32_t ts = microsecond_timer_get();\n    addr_list[index].last_timestamp = ts;\n  }\n}\n\nbool addr_safety_check(CAN_FIFOMailBox_TypeDef *to_push,\n                       const addr_checks *rx_checks,\n                       uint8_t (*get_checksum)(CAN_FIFOMailBox_TypeDef *to_push),\n                       uint8_t (*compute_checksum)(CAN_FIFOMailBox_TypeDef *to_push),\n                       uint8_t (*get_counter)(CAN_FIFOMailBox_TypeDef *to_push)) {\n\n  int index = get_addr_check_index(to_push, rx_checks->check, rx_checks->len);\n  update_addr_timestamp(rx_checks->check, index);\n\n  if (index != -1) {\n    // checksum check\n    if ((get_checksum != NULL) && (compute_checksum != NULL) && rx_checks->check[index].msg[rx_checks->check[index].index].check_checksum) {\n      uint8_t checksum = get_checksum(to_push);\n      uint8_t checksum_comp = compute_checksum(to_push);\n      rx_checks->check[index].valid_checksum = checksum_comp == checksum;\n    } else {\n      rx_checks->check[index].valid_checksum = true;\n    }\n\n    // counter check (max_counter == 0 means skip check)\n    if ((get_counter != NULL) && (rx_checks->check[index].msg[rx_checks->check[index].index].max_counter > 0U)) {\n      uint8_t counter = get_counter(to_push);\n      update_counter(rx_checks->check, index, counter);\n    } else {\n      rx_checks->check[index].wrong_counters = 0U;\n    }\n  }\n  return is_msg_valid(rx_checks->check, index);\n}\n\nvoid generic_rx_checks(bool stock_ecu_detected) {\n  // exit controls on rising edge of gas press\n  if (gas_pressed && !gas_pressed_prev && !(unsafe_mode & UNSAFE_DISABLE_DISENGAGE_ON_GAS)) {\n    controls_allowed = 0;\n  }\n  gas_pressed_prev = gas_pressed;\n\n  // exit controls on rising edge of brake press\n  if (brake_pressed && (!brake_pressed_prev || vehicle_moving)) {\n    controls_allowed = 0;\n  }\n  brake_pressed_prev = brake_pressed;\n\n  // check if stock ECU is on bus broken by car harness\n  if ((safety_mode_cnt > RELAY_TRNS_TIMEOUT) && stock_ecu_detected) {\n    relay_malfunction_set();\n  }\n}\n\nvoid relay_malfunction_set(void) {\n  relay_malfunction = true;\n  fault_occurred(FAULT_RELAY_MALFUNCTION);\n}\n\nvoid relay_malfunction_reset(void) {\n  relay_malfunction = false;\n  fault_recovered(FAULT_RELAY_MALFUNCTION);\n}\n\ntypedef struct {\n  uint16_t id;\n  const safety_hooks *hooks;\n} safety_hook_config;\n\nconst safety_hook_config safety_hook_registry[] = {\n  {SAFETY_SILENT, &nooutput_hooks},\n  {SAFETY_HONDA_NIDEC, &honda_nidec_hooks},\n  {SAFETY_TOYOTA, &toyota_hooks},\n  {SAFETY_ELM327, &elm327_hooks},\n  {SAFETY_GM, &gm_hooks},\n  {SAFETY_HONDA_BOSCH_GIRAFFE, &honda_bosch_giraffe_hooks},\n  {SAFETY_HONDA_BOSCH_HARNESS, &honda_bosch_harness_hooks},\n  {SAFETY_HYUNDAI, &hyundai_hooks},\n  {SAFETY_CHRYSLER, &chrysler_hooks},\n  {SAFETY_SUBARU, &subaru_hooks},\n  {SAFETY_VOLKSWAGEN_MQB, &volkswagen_mqb_hooks},\n  {SAFETY_NISSAN, &nissan_hooks},\n  {SAFETY_NOOUTPUT, &nooutput_hooks},\n  {SAFETY_HYUNDAI_LEGACY, &hyundai_legacy_hooks},\n#ifdef ALLOW_DEBUG\n  {SAFETY_TESLA, &tesla_hooks},\n  {SAFETY_MAZDA, &mazda_hooks},\n  {SAFETY_SUBARU_LEGACY, &subaru_legacy_hooks},\n  {SAFETY_VOLKSWAGEN_PQ, &volkswagen_pq_hooks},\n  {SAFETY_ALLOUTPUT, &alloutput_hooks},\n  {SAFETY_GM_ASCM, &gm_ascm_hooks},\n  {SAFETY_FORD, &ford_hooks},\n#endif\n};\n\nint set_safety_hooks(uint16_t mode, int16_t param) {\n  // reset state set by safety mode\n  safety_mode_cnt = 0U;\n  relay_malfunction = false;\n  gas_interceptor_detected = false;\n  gas_interceptor_prev = 0;\n  gas_pressed = false;\n  gas_pressed_prev = false;\n  brake_pressed = false;\n  brake_pressed_prev = false;\n  cruise_engaged_prev = false;\n  vehicle_speed = 0;\n  vehicle_moving = false;\n  desired_torque_last = 0;\n  rt_torque_last = 0;\n  ts_angle_last = 0;\n  desired_angle_last = 0;\n  ts_last = 0;\n\n  torque_meas.max = 0;\n  torque_meas.max = 0;\n  torque_driver.min = 0;\n  torque_driver.max = 0;\n  angle_meas.min = 0;\n  angle_meas.max = 0;\n\n  int set_status = -1;  // not set\n  int hook_config_count = sizeof(safety_hook_registry) / sizeof(safety_hook_config);\n  for (int i = 0; i < hook_config_count; i++) {\n    if (safety_hook_registry[i].id == mode) {\n      current_hooks = safety_hook_registry[i].hooks;\n      current_safety_mode = mode;\n      current_safety_param = param;\n      set_status = 0;  // set\n    }\n  }\n  if ((set_status == 0) && (current_hooks->init != NULL)) {\n    current_rx_checks = current_hooks->init(param);\n    // reset message index and seen flags in addr struct\n    for (int j = 0; j < current_rx_checks->len; j++) {\n      current_rx_checks->check[j].index = 0;\n      current_rx_checks->check[j].msg_seen = false;\n    }\n  }\n  return set_status;\n}\n\n// convert a trimmed integer to signed 32 bit int\nint to_signed(int d, int bits) {\n  int d_signed = d;\n  if (d >= (1 << MAX((bits - 1), 0))) {\n    d_signed = d - (1 << MAX(bits, 0));\n  }\n  return d_signed;\n}\n\n// given a new sample, update the smaple_t struct\nvoid update_sample(struct sample_t *sample, int sample_new) {\n  int sample_size = sizeof(sample->values) / sizeof(sample->values[0]);\n  for (int i = sample_size - 1; i > 0; i--) {\n    sample->values[i] = sample->values[i-1];\n  }\n  sample->values[0] = sample_new;\n\n  // get the minimum and maximum measured samples\n  sample->min = sample->values[0];\n  sample->max = sample->values[0];\n  for (int i = 1; i < sample_size; i++) {\n    if (sample->values[i] < sample->min) {\n      sample->min = sample->values[i];\n    }\n    if (sample->values[i] > sample->max) {\n      sample->max = sample->values[i];\n    }\n  }\n}\n\nbool max_limit_check(int val, const int MAX_VAL, const int MIN_VAL) {\n  return (val > MAX_VAL) || (val < MIN_VAL);\n}\n\n// check that commanded value isn't too far from measured\nbool dist_to_meas_check(int val, int val_last, struct sample_t *val_meas,\n  const int MAX_RATE_UP, const int MAX_RATE_DOWN, const int MAX_ERROR) {\n\n  // *** val rate limit check ***\n  int highest_allowed_rl = MAX(val_last, 0) + MAX_RATE_UP;\n  int lowest_allowed_rl = MIN(val_last, 0) - MAX_RATE_UP;\n\n  // if we've exceeded the meas val, we must start moving toward 0\n  int highest_allowed = MIN(highest_allowed_rl, MAX(val_last - MAX_RATE_DOWN, MAX(val_meas->max, 0) + MAX_ERROR));\n  int lowest_allowed = MAX(lowest_allowed_rl, MIN(val_last + MAX_RATE_DOWN, MIN(val_meas->min, 0) - MAX_ERROR));\n\n  // check for violation\n  return (val < lowest_allowed) || (val > highest_allowed);\n}\n\n// check that commanded value isn't fighting against driver\nbool driver_limit_check(int val, int val_last, struct sample_t *val_driver,\n  const int MAX_VAL, const int MAX_RATE_UP, const int MAX_RATE_DOWN,\n  const int MAX_ALLOWANCE, const int DRIVER_FACTOR) {\n\n  int highest_allowed_rl = MAX(val_last, 0) + MAX_RATE_UP;\n  int lowest_allowed_rl = MIN(val_last, 0) - MAX_RATE_UP;\n\n  int driver_max_limit = MAX_VAL + (MAX_ALLOWANCE + val_driver->max) * DRIVER_FACTOR;\n  int driver_min_limit = -MAX_VAL + (-MAX_ALLOWANCE + val_driver->min) * DRIVER_FACTOR;\n\n  // if we've exceeded the applied torque, we must start moving toward 0\n  int highest_allowed = MIN(highest_allowed_rl, MAX(val_last - MAX_RATE_DOWN,\n                                             MAX(driver_max_limit, 0)));\n  int lowest_allowed = MAX(lowest_allowed_rl, MIN(val_last + MAX_RATE_DOWN,\n                                           MIN(driver_min_limit, 0)));\n\n  // check for violation\n  return (val < lowest_allowed) || (val > highest_allowed);\n}\n\n\n// real time check, mainly used for steer torque rate limiter\nbool rt_rate_limit_check(int val, int val_last, const int MAX_RT_DELTA) {\n\n  // *** torque real time rate limit check ***\n  int highest_val = MAX(val_last, 0) + MAX_RT_DELTA;\n  int lowest_val = MIN(val_last, 0) - MAX_RT_DELTA;\n\n  // check for violation\n  return (val < lowest_val) || (val > highest_val);\n}\n\n\n// interp function that holds extreme values\nfloat interpolate(struct lookup_t xy, float x) {\n\n  int size = sizeof(xy.x) / sizeof(xy.x[0]);\n  float ret = xy.y[size - 1];  // default output is last point\n\n  // x is lower than the first point in the x array. Return the first point\n  if (x <= xy.x[0]) {\n    ret = xy.y[0];\n\n  } else {\n    // find the index such that (xy.x[i] <= x < xy.x[i+1]) and linearly interp\n    for (int i=0; i < (size - 1); i++) {\n      if (x < xy.x[i+1]) {\n        float x0 = xy.x[i];\n        float y0 = xy.y[i];\n        float dx = xy.x[i+1] - x0;\n        float dy = xy.y[i+1] - y0;\n        // dx should not be zero as xy.x is supposed to be monotonic\n        if (dx <= 0.) {\n          dx = 0.0001;\n        }\n        ret = (dy * (x - x0) / dx) + y0;\n        break;\n      }\n    }\n  }\n  return ret;\n}\n"
  },
  {
    "path": "panda/board/safety_declarations.h",
    "content": "const int MAX_WRONG_COUNTERS = 5;\nconst uint8_t MAX_MISSED_MSGS = 10U;\n\n// sample struct that keeps 3 samples in memory\nstruct sample_t {\n  int values[6];\n  int min;\n  int max;\n} sample_t_default = {.values = {0}, .min = 0, .max = 0};\n\n// safety code requires floats\nstruct lookup_t {\n  float x[3];\n  float y[3];\n};\n\ntypedef struct {\n  int addr;\n  int bus;\n  int len;\n} CanMsg;\n\ntypedef struct {\n  const int addr;\n  const int bus;\n  const int len;\n  const bool check_checksum;         // true is checksum check is performed\n  const uint8_t max_counter;         // maximum value of the counter. 0 means that the counter check is skipped\n  const uint32_t expected_timestep;  // expected time between message updates [us]\n} CanMsgCheck;\n\n// params and flags about checksum, counter and frequency checks for each monitored address\ntypedef struct {\n  // const params\n  const CanMsgCheck msg[3];          // check either messages (e.g. honda steer). Array MUST terminate with an empty struct to know its length.\n  // dynamic flags\n  bool msg_seen;\n  int index;                         // if multiple messages are allowed to be checked, this stores the index of the first one seen. only msg[msg_index] will be used\n  bool valid_checksum;               // true if and only if checksum check is passed\n  int wrong_counters;                // counter of wrong counters, saturated between 0 and MAX_WRONG_COUNTERS\n  uint8_t last_counter;              // last counter value\n  uint32_t last_timestamp;           // micro-s\n  bool lagging;                      // true if and only if the time between updates is excessive\n} AddrCheckStruct;\n\ntypedef struct {\n  AddrCheckStruct *check;\n  int len;\n} addr_checks;\n\nint safety_rx_hook(CAN_FIFOMailBox_TypeDef *to_push);\nint safety_tx_hook(CAN_FIFOMailBox_TypeDef *to_send);\nint safety_tx_lin_hook(int lin_num, uint8_t *data, int len);\nuint32_t get_ts_elapsed(uint32_t ts, uint32_t ts_last);\nint to_signed(int d, int bits);\nvoid update_sample(struct sample_t *sample, int sample_new);\nbool max_limit_check(int val, const int MAX, const int MIN);\nbool dist_to_meas_check(int val, int val_last, struct sample_t *val_meas,\n  const int MAX_RATE_UP, const int MAX_RATE_DOWN, const int MAX_ERROR);\nbool driver_limit_check(int val, int val_last, struct sample_t *val_driver,\n  const int MAX, const int MAX_RATE_UP, const int MAX_RATE_DOWN,\n  const int MAX_ALLOWANCE, const int DRIVER_FACTOR);\nbool rt_rate_limit_check(int val, int val_last, const int MAX_RT_DELTA);\nfloat interpolate(struct lookup_t xy, float x);\nvoid gen_crc_lookup_table(uint8_t poly, uint8_t crc_lut[]);\nbool msg_allowed(CAN_FIFOMailBox_TypeDef *to_send, const CanMsg msg_list[], int len);\nint get_addr_check_index(CAN_FIFOMailBox_TypeDef *to_push, AddrCheckStruct addr_list[], const int len);\nvoid update_counter(AddrCheckStruct addr_list[], int index, uint8_t counter);\nvoid update_addr_timestamp(AddrCheckStruct addr_list[], int index);\nbool is_msg_valid(AddrCheckStruct addr_list[], int index);\nbool addr_safety_check(CAN_FIFOMailBox_TypeDef *to_push,\n                       const addr_checks *rx_checks,\n                       uint8_t (*get_checksum)(CAN_FIFOMailBox_TypeDef *to_push),\n                       uint8_t (*compute_checksum)(CAN_FIFOMailBox_TypeDef *to_push),\n                       uint8_t (*get_counter)(CAN_FIFOMailBox_TypeDef *to_push));\nvoid generic_rx_checks(bool stock_ecu_detected);\nvoid relay_malfunction_set(void);\nvoid relay_malfunction_reset(void);\n\ntypedef const addr_checks* (*safety_hook_init)(int16_t param);\ntypedef int (*rx_hook)(CAN_FIFOMailBox_TypeDef *to_push);\ntypedef int (*tx_hook)(CAN_FIFOMailBox_TypeDef *to_send);\ntypedef int (*tx_lin_hook)(int lin_num, uint8_t *data, int len);\ntypedef int (*fwd_hook)(int bus_num, CAN_FIFOMailBox_TypeDef *to_fwd);\n\ntypedef struct {\n  safety_hook_init init;\n  rx_hook rx;\n  tx_hook tx;\n  tx_lin_hook tx_lin;\n  fwd_hook fwd;\n} safety_hooks;\n\nvoid safety_tick(const addr_checks *addr_checks);\n\n// This can be set by the safety hooks\nbool controls_allowed = false;\nbool relay_malfunction = false;\nbool gas_interceptor_detected = false;\nint gas_interceptor_prev = 0;\nbool gas_pressed = false;\nbool gas_pressed_prev = false;\nbool brake_pressed = false;\nbool brake_pressed_prev = false;\nbool cruise_engaged_prev = false;\nfloat vehicle_speed = 0;\nbool vehicle_moving = false;\n\n// for safety modes with torque steering control\nint desired_torque_last = 0;       // last desired steer torque\nint rt_torque_last = 0;            // last desired torque for real time check\nstruct sample_t torque_meas;       // last 3 motor torques produced by the eps\nstruct sample_t torque_driver;     // last 3 driver torques measured\nuint32_t ts_last = 0;\n\n// for safety modes with angle steering control\nuint32_t ts_angle_last = 0;\nint desired_angle_last = 0;\nstruct sample_t angle_meas;         // last 3 steer angles\n\n// This can be set with a USB command\n// It enables features we consider to be unsafe, but understand others may have different opinions\n// It is always 0 on mainline comma.ai openpilot\n\n// If using this flag, be very careful about what happens if your fork wants to brake while the\n//   user is pressing the gas. Tesla is careful with this.\n#define UNSAFE_DISABLE_DISENGAGE_ON_GAS 1\n\n// If using this flag, make sure to communicate to your users that a stock safety feature is now disabled.\n#define UNSAFE_DISABLE_STOCK_AEB 2\n\n// If using this flag, be aware that harder braking is more likely to lead to rear endings,\n//   and that alone this flag doesn't make braking compliant because there's also a time element.\n// Setting this flag is used for allowing the full -5.0 to +4.0 m/s^2 at lower speeds\n// See ISO 15622:2018 for more information.\n#define UNSAFE_RAISE_LONGITUDINAL_LIMITS_TO_ISO_MAX 8\n\nint unsafe_mode = 0;\n\n// time since safety mode has been changed\nuint32_t safety_mode_cnt = 0U;\n// allow 1s of transition timeout after relay changes state before assessing malfunctioning\nconst uint32_t RELAY_TRNS_TIMEOUT = 1U;\n"
  },
  {
    "path": "panda/board/stm32fx/board.h",
    "content": "// ///////////////////////////////////////////////////////////// //\n// Hardware abstraction layer for all different supported boards //\n// ///////////////////////////////////////////////////////////// //\n#include \"boards/board_declarations.h\"\n#include \"boards/unused_funcs.h\"\n\n// ///// Board definition and detection ///// //\n#include \"drivers/harness.h\"\n#ifdef PANDA\n  #include \"drivers/fan.h\"\n  #include \"stm32fx/llfan.h\"\n  #include \"stm32fx/llrtc.h\"\n  #include \"drivers/rtc.h\"\n  #include \"stm32fx/clock_source.h\"\n  #include \"boards/white.h\"\n  #include \"boards/grey.h\"\n  #include \"boards/black.h\"\n  #include \"boards/uno.h\"\n  #include \"boards/dos.h\"\n#else\n  #include \"boards/pedal.h\"\n#endif\n\nvoid detect_board_type(void) {\n  #ifdef PANDA\n    // SPI lines floating: white (TODO: is this reliable? Not really, we have to enable ESP/GPS to be able to detect this on the UART)\n    set_gpio_output(GPIOC, 14, 1);\n    set_gpio_output(GPIOC, 5, 1);\n    if(!detect_with_pull(GPIOB, 1, PULL_UP) && !detect_with_pull(GPIOB, 7, PULL_UP)){\n      hw_type = HW_TYPE_DOS;\n      current_board = &board_dos;\n    } else if((detect_with_pull(GPIOA, 4, PULL_DOWN)) || (detect_with_pull(GPIOA, 5, PULL_DOWN)) || (detect_with_pull(GPIOA, 6, PULL_DOWN)) || (detect_with_pull(GPIOA, 7, PULL_DOWN))){\n      hw_type = HW_TYPE_WHITE_PANDA;\n      current_board = &board_white;\n    } else if(detect_with_pull(GPIOA, 13, PULL_DOWN)) { // Rev AB deprecated, so no pullup means black. In REV C, A13 is pulled up to 5V with a 10K\n      hw_type = HW_TYPE_GREY_PANDA;\n      current_board = &board_grey;\n    } else if(!detect_with_pull(GPIOB, 15, PULL_UP)) {\n      hw_type = HW_TYPE_UNO;\n      current_board = &board_uno;\n    } else {\n      hw_type = HW_TYPE_BLACK_PANDA;\n      current_board = &board_black;\n    }\n  #else\n    #ifdef PEDAL\n      hw_type = HW_TYPE_PEDAL;\n      current_board = &board_pedal;\n    #else\n      hw_type = HW_TYPE_UNKNOWN;\n      puts(\"Hardware type is UNKNOWN!\\n\");\n    #endif\n  #endif\n}\n\nbool has_external_debug_serial = 0;\n\nvoid detect_external_debug_serial(void) {\n  // detect if external serial debugging is present\n  has_external_debug_serial = detect_with_pull(GPIOA, 3, PULL_DOWN);\n}\n"
  },
  {
    "path": "panda/board/stm32fx/clock.h",
    "content": "void clock_init(void) {\n  // enable external oscillator\n  register_set_bits(&(RCC->CR), RCC_CR_HSEON);\n  while ((RCC->CR & RCC_CR_HSERDY) == 0);\n\n  // divide things\n  register_set(&(RCC->CFGR), RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4, 0xFF7FFCF3U);\n\n  // 16mhz crystal\n  register_set(&(RCC->PLLCFGR), RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_5 | RCC_PLLCFGR_PLLSRC_HSE, 0x7F437FFFU);\n\n  // start PLL\n  register_set_bits(&(RCC->CR), RCC_CR_PLLON);\n  while ((RCC->CR & RCC_CR_PLLRDY) == 0);\n\n  // Configure Flash prefetch, Instruction cache, Data cache and wait state\n  // *** without this, it breaks ***\n  register_set(&(FLASH->ACR), FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS, 0x1F0FU);\n\n  // switch to PLL\n  register_set_bits(&(RCC->CFGR), RCC_CFGR_SW_PLL);\n  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);\n\n  // *** running on PLL ***\n}\n\nvoid watchdog_init(void) {\n  // setup watchdog\n  IWDG->KR = 0x5555U;\n  register_set(&(IWDG->PR), 0x0U, 0x7U);  // divider/4\n\n  // 0 = 0.125 ms, let's have a 50ms watchdog\n  register_set(&(IWDG->RLR), (400U-1U), 0xFFFU);\n  IWDG->KR = 0xCCCCU;\n}\n\nvoid watchdog_feed(void) {\n  IWDG->KR = 0xAAAAU;\n}\n"
  },
  {
    "path": "panda/board/stm32fx/clock_source.h",
    "content": "\n#define CLOCK_SOURCE_MODE_DISABLED       0U\n#define CLOCK_SOURCE_MODE_FREE_RUNNING   1U\n#define CLOCK_SOURCE_MODE_EXTERNAL_SYNC  2U\n\n#define CLOCK_SOURCE_PERIOD_MS           50U\n#define CLOCK_SOURCE_PULSE_LEN_MS        2U\n\nuint8_t clock_source_mode = CLOCK_SOURCE_MODE_DISABLED;\n\nvoid EXTI0_IRQ_Handler(void) {\n  volatile unsigned int pr = EXTI->PR & (1U << 0);\n  if (pr != 0U) {\n    if(clock_source_mode == CLOCK_SOURCE_MODE_EXTERNAL_SYNC){\n      // TODO: Implement!\n    }\n  }\n  EXTI->PR = (1U << 0);\n}\n\nvoid TIM1_UP_TIM10_IRQ_Handler(void) {\n  if((TIM1->SR & TIM_SR_UIF) != 0) {\n    if(clock_source_mode != CLOCK_SOURCE_MODE_DISABLED) {\n      // Start clock pulse\n      set_gpio_output(GPIOB, 14, true);\n      set_gpio_output(GPIOB, 15, true);\n      set_gpio_output(GPIOC, 5, true);\n    }\n\n    // Reset interrupt\n    TIM1->SR &= ~(TIM_SR_UIF);\n  }\n}\n\nvoid TIM1_CC_IRQ_Handler(void) {\n  if((TIM1->SR & TIM_SR_CC1IF) != 0) {\n    if(clock_source_mode != CLOCK_SOURCE_MODE_DISABLED) {\n      // End clock pulse\n      set_gpio_output(GPIOB, 14, false);\n      set_gpio_output(GPIOB, 15, false);\n      set_gpio_output(GPIOC, 5, false);\n    }\n\n    // Reset interrupt\n    TIM1->SR &= ~(TIM_SR_CC1IF);\n  }\n}\n\nvoid clock_source_init(uint8_t mode){\n  // Setup external clock signal interrupt\n  REGISTER_INTERRUPT(EXTI0_IRQn, EXTI0_IRQ_Handler, 110U, FAULT_INTERRUPT_RATE_CLOCK_SOURCE)\n  register_set(&(SYSCFG->EXTICR[0]), SYSCFG_EXTICR1_EXTI0_PB, 0xFU);\n  register_set_bits(&(EXTI->IMR), (1U << 0));\n  register_set_bits(&(EXTI->RTSR), (1U << 0));\n  register_clear_bits(&(EXTI->FTSR), (1U << 0));\n\n  // Setup timer\n  REGISTER_INTERRUPT(TIM1_UP_TIM10_IRQn, TIM1_UP_TIM10_IRQ_Handler, (1200U / CLOCK_SOURCE_PERIOD_MS) , FAULT_INTERRUPT_RATE_TIM1)\n  REGISTER_INTERRUPT(TIM1_CC_IRQn, TIM1_CC_IRQ_Handler, (1200U / CLOCK_SOURCE_PERIOD_MS) , FAULT_INTERRUPT_RATE_TIM1)\n  register_set(&(TIM1->PSC), ((APB2_FREQ*100U)-1U), 0xFFFFU);                   // Tick on 0.1 ms\n  register_set(&(TIM1->ARR), ((CLOCK_SOURCE_PERIOD_MS*10U) - 1U), 0xFFFFU);   // Period\n  register_set(&(TIM1->CCMR1), 0U, 0xFFFFU);                                  // No output on compare\n  register_set_bits(&(TIM1->CCER), TIM_CCER_CC1E);                            // Enable compare 1\n  register_set(&(TIM1->CCR1), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU);      // Compare 1 value\n  register_set_bits(&(TIM1->DIER), TIM_DIER_UIE | TIM_DIER_CC1IE);            // Enable interrupts\n  register_set(&(TIM1->CR1), TIM_CR1_CEN, 0x3FU);                             // Enable timer\n\n  // Set mode\n  switch(mode) {\n    case CLOCK_SOURCE_MODE_DISABLED:\n      // No clock signal\n      NVIC_DisableIRQ(EXTI0_IRQn);\n      NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);\n      NVIC_DisableIRQ(TIM1_CC_IRQn);\n\n      // Disable pulse if we were in the middle of it\n      set_gpio_output(GPIOB, 14, false);\n      set_gpio_output(GPIOB, 15, false);\n\n      clock_source_mode = CLOCK_SOURCE_MODE_DISABLED;\n      break;\n    case CLOCK_SOURCE_MODE_FREE_RUNNING:\n      // Clock signal is based on internal timer\n      NVIC_DisableIRQ(EXTI0_IRQn);\n      NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);\n      NVIC_EnableIRQ(TIM1_CC_IRQn);\n\n      clock_source_mode = CLOCK_SOURCE_MODE_FREE_RUNNING;\n      break;\n    case CLOCK_SOURCE_MODE_EXTERNAL_SYNC:\n      // Clock signal is based on external timer\n      NVIC_EnableIRQ(EXTI0_IRQn);\n      NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);\n      NVIC_EnableIRQ(TIM1_CC_IRQn);\n\n      clock_source_mode = CLOCK_SOURCE_MODE_EXTERNAL_SYNC;\n      break;\n    default:\n      puts(\"Unknown clock source mode: \"); puth(mode); puts(\"\\n\");\n      break;\n  }\n}\n"
  },
  {
    "path": "panda/board/stm32fx/inc/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.1.0\n * @date     09. October 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6.6 LTM (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)\n  #include \"cmsis_armclang_ltm.h\"\n\n  /*\n * Arm Compiler above 6.10.1 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #define __RESTRICT                             __restrict\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.2.0\n * @date     08. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n\n/**\n  \\brief   Initializes data and bss sections\n  \\details This default implementations initialized all data and additional bss\n           sections relying on .copy.table and .zero.table specified properly\n           in the used linker script.\n\n */\n__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)\n{\n  extern void _start(void) __NO_RETURN;\n\n  typedef struct {\n    uint32_t const* src;\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __copy_table_t;\n\n  typedef struct {\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __zero_table_t;\n\n  extern const __copy_table_t __copy_table_start__;\n  extern const __copy_table_t __copy_table_end__;\n  extern const __zero_table_t __zero_table_start__;\n  extern const __zero_table_t __zero_table_end__;\n\n  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = pTable->src[i];\n    }\n  }\n\n  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = 0u;\n    }\n  }\n\n  _start();\n}\n\n#define __PROGRAM_START           __cmsis_start\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              __StackTop\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             __StackLimit\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(\".vectors\")))\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n __extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.3\n * @date     24. June 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/core_cm3.h",
    "content": "/**************************************************************************//**\n * @file     core_cm3.h\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     13. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM3_H_GENERIC\n#define __CORE_CM3_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M3\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM3 definitions */\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM3_H_DEPENDANT\n#define __CORE_CM3_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM3_REV\n    #define __CM3_REV               0x0200U\n    #warning \"__CM3_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M3 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#else\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n#else\n        uint32_t RESERVED1[1U];\n#endif\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n#endif\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/core_cm4.h",
    "content": "/**************************************************************************//**\n * @file     core_cm4.h\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     13. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM4_H_GENERIC\n#define __CORE_CM4_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M4\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM4 definitions */\n#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM4_H_DEPENDANT\n#define __CORE_CM4_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM4_REV\n    #define __CM4_REV               0x0000U\n    #warning \"__CM4_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M4 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */\n#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\n  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t vectors = (uint32_t )SCB->VTOR;\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/mpu_armv7.h",
    "content": "/******************************************************************************\n * @file     mpu_armv7.h\n * @brief    CMSIS MPU API for Armv7-M MPU\n * @version  V5.1.0\n * @date     08. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_MPU_ARMV7_H\n#define ARM_MPU_ARMV7_H\n\n#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\n#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\n#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\n#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\n#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\n#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\n#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\n#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\n#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\n#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\n#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\n#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\n#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\n#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\n#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\n#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\n#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\n#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\n#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\n#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\n#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\n#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\n#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\n#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\n#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\n#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\n#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\n#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\n\n#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\n#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\n#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\n#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\n#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\n#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\n\n/** MPU Region Base Address Register Value\n*\n* \\param Region The region to be configured, number 0 to 15.\n* \\param BaseAddress The base address for the region.\n*/\n#define ARM_MPU_RBAR(Region, BaseAddress) \\\n  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\\n   ((Region) & MPU_RBAR_REGION_Msk)    |  \\\n   (MPU_RBAR_VALID_Msk))\n\n/**\n* MPU Memory Access Attributes\n*\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n*/\n#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\\n  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \\\n   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \\\n   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \\\n   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))\n\n/**\n* MPU Region Attribute and Size Register Value\n*\n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param AccessAttributes  Memory access attribution, see \\ref ARM_MPU_ACCESS_.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \\\n  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \\\n   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \\\n   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \\\n   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \\\n   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \\\n   (((MPU_RASR_ENABLE_Msk))))\n\n/**\n* MPU Region Attribute and Size Register Value\n*\n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\\n  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\n\n/**\n* MPU Memory Access Attribute for strongly ordered memory.\n*  - TEX: 000b\n*  - Shareable\n*  - Non-cacheable\n*  - Non-bufferable\n*/\n#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\n\n/**\n* MPU Memory Access Attribute for device memory.\n*  - TEX: 000b (if shareable) or 010b (if non-shareable)\n*  - Shareable or non-shareable\n*  - Non-cacheable\n*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\n*\n* \\param IsShareable Configures the device memory as shareable or non-shareable.\n*/\n#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\n\n/**\n* MPU Memory Access Attribute for normal memory.\n*  - TEX: 1BBb (reflecting outer cacheability rules)\n*  - Shareable or non-shareable\n*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\n*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\n*\n* \\param OuterCp Configures the outer cache policy.\n* \\param InnerCp Configures the inner cache policy.\n* \\param IsShareable Configures the memory as shareable or non-shareable.\n*/\n#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\n\n/**\n* MPU Memory Access Attribute non-cacheable policy.\n*/\n#define ARM_MPU_CACHEP_NOCACHE 0U\n\n/**\n* MPU Memory Access Attribute write-back, write and read allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_WRA 1U\n\n/**\n* MPU Memory Access Attribute write-through, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WT_NWA 2U\n\n/**\n* MPU Memory Access Attribute write-back, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_NWA 3U\n\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR; //!< The region base address register value (RBAR)\n  uint32_t RASR; //!< The region attribute and size register value (RASR) \\ref MPU_RASR\n} ARM_MPU_Region_t;\n\n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  MPU->RNR = rnr;\n  MPU->RASR = 0U;\n}\n\n/** Configure an MPU region.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\n{\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\n{\n  MPU->RNR = rnr;\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i)\n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)\n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  while (cnt > MPU_TYPE_RALIASES) {\n    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\n    table += MPU_TYPE_RALIASES;\n    cnt -= MPU_TYPE_RALIASES;\n  }\n  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\n}\n\n#endif\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f205xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f205xx.h\n  * @author  MCD Application Team\n  * @version V2.1.2\n  * @date    29-June-2016\n  * @brief   CMSIS STM32F205xx Device Peripheral Access Layer Header File.\n  *          This file contains :\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripherals registers declarations and bits definition\n  *           - Macros to access peripherals registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f205xx\n  * @{\n  */\n\n#ifndef __STM32F205xx_H\n#define __STM32F205xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals\n  */\n#define __CM3_REV                 0x0200U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F2XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F2XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F2XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  HASH_RNG_IRQn               = 80      /*!< Hash and RNG global interrupt                                     */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm3.h\"\n#include \"system_stm32f2xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register, Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,            Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,         Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,        Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */\n} FLASH_TypeDef;\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank2\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\n  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */\n  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */\n  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\n  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\n  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\n  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\n} FSMC_Bank2_3_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank4\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\n  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\n  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\n  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\n  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\n} FSMC_Bank4_TypeDef;\n\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  uint32_t RESERVED1;    /*!< Reserved, 0x28                                                                 */\n  uint32_t RESERVED2;    /*!< Reserved, 0x2C                                                                 */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  uint32_t RESERVED3;    /*!< Reserved, 0x38                                                                 */\n  uint32_t RESERVED4;    /*!< Reserved, 0x3C                                                                 */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  uint32_t RESERVED5;    /*!< Reserved, 0x44                                                                 */\n  uint32_t RESERVED6;    /*!< Reserved, 0x48                                                                 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;   /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;   /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;   /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;   /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;  /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;     /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT; /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n\n\n/**\n  * @brief __USB_OTG_Core_register\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */\n  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */\n  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */\n  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */\n  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */\n  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */\n  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */\n  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */\n  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */\n  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */\n  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */\n  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */\n  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */\n  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */\n  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */\n}\nUSB_OTG_GlobalTypeDef;\n\n\n\n/**\n  * @brief __device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */\n  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */\n  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */\n  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */\n  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */\n  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */\n  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */\n  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */\n  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */\n  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */\n  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */\n  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */\n  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */\n  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */\n  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */\n  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */\n  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */\n  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */\n  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */\n  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */\n}\nUSB_OTG_DeviceTypeDef;\n\n\n/**\n  * @brief __IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */\n  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */\n  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */\n  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */\n  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */\n  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */\n  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */\n  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n}\nUSB_OTG_INEndpointTypeDef;\n\n\n/**\n  * @brief __OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/\n  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/\n  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/\n  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/\n  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/\n  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/\n  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/\n}\nUSB_OTG_OUTEndpointTypeDef;\n\n\n/**\n  * @brief __Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/\n  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/\n  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/\n  uint32_t Reserved40C;           /* Reserved                       40Ch*/\n  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/\n  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/\n  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/\n}\nUSB_OTG_HostTypeDef;\n\n\n/**\n  * @brief __Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;\n  __IO uint32_t HCSPLT;\n  __IO uint32_t HCINT;\n  __IO uint32_t HCINTMSK;\n  __IO uint32_t HCTSIZ;\n  __IO uint32_t HCDMA;\n  uint32_t Reserved[2];\n}\nUSB_OTG_HostChannelTypeDef;\n\n\n/**\n  * @brief Peripheral_memory_map\n  */\n#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */\n#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */\n#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x080FFFFFU /*!< FLASH end address                                                          */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)\n#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)\n#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)\n#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)\n\n/* Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000U\n\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000U\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\n\n#define USB_OTG_GLOBAL_BASE                  0x000U\n#define USB_OTG_DEVICE_BASE                  0x800U\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\n#define USB_OTG_EP_REG_SIZE                  0x20U\n#define USB_OTG_HOST_BASE                    0x400U\n#define USB_OTG_HOST_PORT_BASE               0x440U\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\n#define USB_OTG_FIFO_BASE                    0x1000U\n#define USB_OTG_FIFO_SIZE                    0x1000U\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)\n#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\n\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for ADC_SR register  ********************/\n#define  ADC_SR_AWD                          0x00000001U       /*!<Analog watchdog flag */\n#define  ADC_SR_EOC                          0x00000002U       /*!<End of conversion */\n#define  ADC_SR_JEOC                         0x00000004U       /*!<Injected channel end of conversion */\n#define  ADC_SR_JSTRT                        0x00000008U       /*!<Injected channel Start flag */\n#define  ADC_SR_STRT                         0x00000010U       /*!<Regular channel Start flag */\n#define  ADC_SR_OVR                          0x00000020U       /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */\n#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */\n#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */\n#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */\n#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */\n#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */\n#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */\n#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */\n#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */\n#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */\n#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */\n#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */\n#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */\n#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */\n#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */\n#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */\n#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */\n#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */\n#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */\n#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */\n#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */\n#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */\n#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */\n#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */\n#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */\n#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */\n#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */\n#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */\n#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */\n#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */\n#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */\n#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */\n#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */\n#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */\n#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */\n#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */\n#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */\n#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */\n#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */\n#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */\n#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */\n#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */\n#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */\n#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */\n#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */\n#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */\n#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define  ADC_JOFR1_JOFFSET1                  0x00000FFFU        /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define  ADC_JOFR2_JOFFSET2                  0x00000FFFU        /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define  ADC_JOFR3_JOFFSET3                  0x00000FFFU        /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define  ADC_JOFR4_JOFFSET4                  0x00000FFFU        /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define  ADC_HTR_HT                          0x00000FFFU        /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define  ADC_LTR_LT                          0x00000FFFU         /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */\n#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */\n#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */\n#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */\n#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */\n#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */\n#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */\n#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */\n#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */\n#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */\n#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */\n#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */\n#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */\n#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */\n#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */\n#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */\n#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */\n#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */\n#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */\n#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */\n#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */\n#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */\n#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */\n#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */\n#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */\n#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */\n#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */\n#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */\n#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */\n#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */\n#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */\n#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */\n#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */\n#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */\n#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */\n#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */\n#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */\n#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */\n#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */\n#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */\n#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */\n#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */\n#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */\n#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */\n#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */\n#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */\n#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */\n#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */\n#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */\n#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */\n#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */\n#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */\n#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */\n#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */\n#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */\n#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */\n#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */\n#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */\n#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */\n#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */\n#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */\n#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */\n#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */\n#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */\n#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */\n#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */\n#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */\n#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */\n#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */\n#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */\n#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */\n#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */\n#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */\n#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */\n#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */\n#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */\n#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */\n#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */\n#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */\n#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */\n#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */\n#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */\n#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */\n#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */\n#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */\n#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */\n#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */\n#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */\n#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */\n#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */\n#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */\n#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */\n#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */\n#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */\n#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */\n#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */\n#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */\n#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */\n#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */\n#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */\n#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */\n#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */\n#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */\n#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */\n#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define  ADC_JDR1_JDATA                      0x0000FFFFU        /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define  ADC_JDR2_JDATA                      0x0000FFFFU        /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define  ADC_JDR3_JDATA                      0x0000FFFFU        /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define  ADC_JDR4_JDATA                      0x0000FFFFU        /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */\n#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */\n#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */\n#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */\n#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */\n#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */\n#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */\n#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */\n#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */\n#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */\n#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */\n#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */\n#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */\n#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */\n#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */\n#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */\n#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */\n#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */\n#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */\n#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */\n#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */\n#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */\n#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */\n#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */\n#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */\n#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */\n#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */\n#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */\n#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */\n#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */\n#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */\n#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */\n#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */\n#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */\n#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */\n#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */\n#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */\n#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */\n#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */\n#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */\n#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */\n#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */\n#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */\n#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge */\n#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge */\n#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt */\n#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt */\n#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */\n#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode */\n#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode */\n#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point */\n#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */\n#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */\n#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */\n#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */\n#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */\n#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */\n#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */\n#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */\n#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */\n#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */\n#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */\n#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */\n#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */\n#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */\n#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */\n#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */\n\n#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */\n#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */\n#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */\n#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */\n\n#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */\n#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */\n#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */\n#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending */\n#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full */\n#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun */\n#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define  CAN_RF1R_FMP1                       0x00000003U         /*!<FIFO 1 Message Pending */\n#define  CAN_RF1R_FULL1                      0x00000008U         /*!<FIFO 1 Full */\n#define  CAN_RF1R_FOVR1                      0x00000010U         /*!<FIFO 1 Overrun */\n#define  CAN_RF1R_RFOM1                      0x00000020U         /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */\n#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */\n#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */\n#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */\n#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */\n#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */\n#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */\n#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */\n#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */\n#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */\n#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */\n#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */\n#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */\n#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */\n#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */\n#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */\n\n#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */\n#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */\n#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */\n#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */\n\n#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */\n#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */\n#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */\n#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */\n#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */\n#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */\n#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */\n#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */\n#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */\n#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */\n#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */\n#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */\n#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */\n#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */\n#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */\n#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */\n#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */\n#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */\n#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */\n#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */\n#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */\n#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\n#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\n#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */\n#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\n#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\n#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */\n#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */\n#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */\n#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */\n#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */\n#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */\n#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */\n#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\n#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\n#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */\n#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\n#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\n#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */\n#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */\n#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */\n#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */\n#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */\n#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */\n#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */\n#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\n#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\n#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */\n#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\n#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\n#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */\n#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */\n#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */\n#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */\n#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */\n#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */\n#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\n#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\n#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */\n#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\n#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\n#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */\n#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */\n#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */\n#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */\n#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */\n#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */\n#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\n#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\n#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */\n#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\n#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\n#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define  CAN_FMR_FINIT                       0x00000001U        /*!<Filter Init Mode */\n#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */\n\n/*************  Bit definition for CAN_FM1R register  *******************/\n#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */\n#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */\n#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */\n#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */\n#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */\n#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */\n#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */\n#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */\n#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */\n#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */\n#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */\n#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */\n#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */\n#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */\n#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */\n#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */\n#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */\n#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */\n#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */\n#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */\n#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */\n#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */\n#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */\n#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */\n#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */\n#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */\n#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */\n#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */\n#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */\n#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */\n#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */\n#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */\n#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */\n#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */\n#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */\n#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */\n#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */\n#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */\n#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */\n#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */\n#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */\n#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */\n#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */\n#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */\n#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */\n#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */\n#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */\n#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */\n#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */\n#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */\n#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */\n#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */\n#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */\n#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */\n#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */\n#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */\n#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */\n#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */\n#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */\n#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */\n#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */\n#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */\n#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */\n#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */\n#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */\n#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */\n#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */\n#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */\n#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */\n#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */\n#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */\n#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */\n#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */\n#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */\n#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */\n#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */\n#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */\n#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */\n#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */\n#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */\n#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */\n#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */\n#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */\n#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */\n#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */\n#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */\n#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */\n#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */\n#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */\n#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */\n#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */\n#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */\n#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */\n#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */\n#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */\n#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */\n#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */\n#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */\n#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */\n#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */\n#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */\n#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */\n#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */\n#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */\n#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */\n#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */\n#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */\n#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */\n#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */\n#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */\n#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */\n#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */\n#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */\n#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */\n#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */\n#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */\n#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */\n#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */\n#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */\n#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */\n#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */\n#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */\n#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */\n#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */\n#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */\n#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */\n#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */\n#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */\n#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */\n#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */\n#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */\n#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */\n#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */\n#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */\n#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */\n#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */\n#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */\n#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */\n#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */\n#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */\n#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */\n#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */\n#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */\n#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define  CRC_IDR_IDR                         0x000000FFU /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define  CRC_CR_RESET                        0x00000001U /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DAC_CR register  ********************/\n#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */\n#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */\n#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */\n\n#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */\n#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */\n#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */\n\n#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */\n#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */\n\n#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */\n#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */\n#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */\n#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */\n\n#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */\n#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/\n#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */\n#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */\n#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */\n\n#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */\n#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */\n#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */\n\n#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */\n#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */\n\n#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */\n#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */\n#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */\n#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */\n\n#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */\n#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define  DAC_SWTRIGR_SWTRIG1                 0x00000001U        /*!<DAC channel1 software trigger */\n#define  DAC_SWTRIGR_SWTRIG2                 0x00000002U        /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define  DAC_DHR12R1_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define  DAC_DHR12L1_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define  DAC_DHR8R1_DACC1DHR                 0x000000FFU        /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define  DAC_DHR12R2_DACC2DHR                0x00000FFFU        /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define  DAC_DHR12L2_DACC2DHR                0x0000FFF0U        /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define  DAC_DHR8R2_DACC2DHR                 0x000000FFU        /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */\n#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */\n#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define  DAC_DHR8RD_DACC1DHR                 0x000000FFU        /*!<DAC channel1 8-bit Right aligned data */\n#define  DAC_DHR8RD_DACC2DHR                 0x0000FF00U        /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define  DAC_DOR1_DACC1DOR                   0x00000FFFU        /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define  DAC_DOR2_DACC2DOR                   0x00000FFFU        /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */\n#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 Debug MCU                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL                       0x0E000000U\n#define DMA_SxCR_CHSEL_0                     0x02000000U\n#define DMA_SxCR_CHSEL_1                     0x04000000U\n#define DMA_SxCR_CHSEL_2                     0x08000000U\n#define DMA_SxCR_MBURST                      0x01800000U\n#define DMA_SxCR_MBURST_0                    0x00800000U\n#define DMA_SxCR_MBURST_1                    0x01000000U\n#define DMA_SxCR_PBURST                      0x00600000U\n#define DMA_SxCR_PBURST_0                    0x00200000U\n#define DMA_SxCR_PBURST_1                    0x00400000U\n#define DMA_SxCR_CT                          0x00080000U\n#define DMA_SxCR_DBM                         0x00040000U\n#define DMA_SxCR_PL                          0x00030000U\n#define DMA_SxCR_PL_0                        0x00010000U\n#define DMA_SxCR_PL_1                        0x00020000U\n#define DMA_SxCR_PINCOS                      0x00008000U\n#define DMA_SxCR_MSIZE                       0x00006000U\n#define DMA_SxCR_MSIZE_0                     0x00002000U\n#define DMA_SxCR_MSIZE_1                     0x00004000U\n#define DMA_SxCR_PSIZE                       0x00001800U\n#define DMA_SxCR_PSIZE_0                     0x00000800U\n#define DMA_SxCR_PSIZE_1                     0x00001000U\n#define DMA_SxCR_MINC                        0x00000400U\n#define DMA_SxCR_PINC                        0x00000200U\n#define DMA_SxCR_CIRC                        0x00000100U\n#define DMA_SxCR_DIR                         0x000000C0U\n#define DMA_SxCR_DIR_0                       0x00000040U\n#define DMA_SxCR_DIR_1                       0x00000080U\n#define DMA_SxCR_PFCTRL                      0x00000020U\n#define DMA_SxCR_TCIE                        0x00000010U\n#define DMA_SxCR_HTIE                        0x00000008U\n#define DMA_SxCR_TEIE                        0x00000004U\n#define DMA_SxCR_DMEIE                       0x00000002U\n#define DMA_SxCR_EN                          0x00000001U\n\n/* Legacy defines */\n#define DMA_SxCR_ACK                         0x00100000U\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT                            0x0000FFFFU\n#define DMA_SxNDT_0                          0x00000001U\n#define DMA_SxNDT_1                          0x00000002U\n#define DMA_SxNDT_2                          0x00000004U\n#define DMA_SxNDT_3                          0x00000008U\n#define DMA_SxNDT_4                          0x00000010U\n#define DMA_SxNDT_5                          0x00000020U\n#define DMA_SxNDT_6                          0x00000040U\n#define DMA_SxNDT_7                          0x00000080U\n#define DMA_SxNDT_8                          0x00000100U\n#define DMA_SxNDT_9                          0x00000200U\n#define DMA_SxNDT_10                         0x00000400U\n#define DMA_SxNDT_11                         0x00000800U\n#define DMA_SxNDT_12                         0x00001000U\n#define DMA_SxNDT_13                         0x00002000U\n#define DMA_SxNDT_14                         0x00004000U\n#define DMA_SxNDT_15                         0x00008000U\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE                       0x00000080U\n#define DMA_SxFCR_FS                         0x00000038U\n#define DMA_SxFCR_FS_0                       0x00000008U\n#define DMA_SxFCR_FS_1                       0x00000010U\n#define DMA_SxFCR_FS_2                       0x00000020U\n#define DMA_SxFCR_DMDIS                      0x00000004U\n#define DMA_SxFCR_FTH                        0x00000003U\n#define DMA_SxFCR_FTH_0                      0x00000001U\n#define DMA_SxFCR_FTH_1                      0x00000002U\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3                       0x08000000U\n#define DMA_LISR_HTIF3                       0x04000000U\n#define DMA_LISR_TEIF3                       0x02000000U\n#define DMA_LISR_DMEIF3                      0x01000000U\n#define DMA_LISR_FEIF3                       0x00400000U\n#define DMA_LISR_TCIF2                       0x00200000U\n#define DMA_LISR_HTIF2                       0x00100000U\n#define DMA_LISR_TEIF2                       0x00080000U\n#define DMA_LISR_DMEIF2                      0x00040000U\n#define DMA_LISR_FEIF2                       0x00010000U\n#define DMA_LISR_TCIF1                       0x00000800U\n#define DMA_LISR_HTIF1                       0x00000400U\n#define DMA_LISR_TEIF1                       0x00000200U\n#define DMA_LISR_DMEIF1                      0x00000100U\n#define DMA_LISR_FEIF1                       0x00000040U\n#define DMA_LISR_TCIF0                       0x00000020U\n#define DMA_LISR_HTIF0                       0x00000010U\n#define DMA_LISR_TEIF0                       0x00000008U\n#define DMA_LISR_DMEIF0                      0x00000004U\n#define DMA_LISR_FEIF0                       0x00000001U\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7                       0x08000000U\n#define DMA_HISR_HTIF7                       0x04000000U\n#define DMA_HISR_TEIF7                       0x02000000U\n#define DMA_HISR_DMEIF7                      0x01000000U\n#define DMA_HISR_FEIF7                       0x00400000U\n#define DMA_HISR_TCIF6                       0x00200000U\n#define DMA_HISR_HTIF6                       0x00100000U\n#define DMA_HISR_TEIF6                       0x00080000U\n#define DMA_HISR_DMEIF6                      0x00040000U\n#define DMA_HISR_FEIF6                       0x00010000U\n#define DMA_HISR_TCIF5                       0x00000800U\n#define DMA_HISR_HTIF5                       0x00000400U\n#define DMA_HISR_TEIF5                       0x00000200U\n#define DMA_HISR_DMEIF5                      0x00000100U\n#define DMA_HISR_FEIF5                       0x00000040U\n#define DMA_HISR_TCIF4                       0x00000020U\n#define DMA_HISR_HTIF4                       0x00000010U\n#define DMA_HISR_TEIF4                       0x00000008U\n#define DMA_HISR_DMEIF4                      0x00000004U\n#define DMA_HISR_FEIF4                       0x00000001U\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3                     0x08000000U\n#define DMA_LIFCR_CHTIF3                     0x04000000U\n#define DMA_LIFCR_CTEIF3                     0x02000000U\n#define DMA_LIFCR_CDMEIF3                    0x01000000U\n#define DMA_LIFCR_CFEIF3                     0x00400000U\n#define DMA_LIFCR_CTCIF2                     0x00200000U\n#define DMA_LIFCR_CHTIF2                     0x00100000U\n#define DMA_LIFCR_CTEIF2                     0x00080000U\n#define DMA_LIFCR_CDMEIF2                    0x00040000U\n#define DMA_LIFCR_CFEIF2                     0x00010000U\n#define DMA_LIFCR_CTCIF1                     0x00000800U\n#define DMA_LIFCR_CHTIF1                     0x00000400U\n#define DMA_LIFCR_CTEIF1                     0x00000200U\n#define DMA_LIFCR_CDMEIF1                    0x00000100U\n#define DMA_LIFCR_CFEIF1                     0x00000040U\n#define DMA_LIFCR_CTCIF0                     0x00000020U\n#define DMA_LIFCR_CHTIF0                     0x00000010U\n#define DMA_LIFCR_CTEIF0                     0x00000008U\n#define DMA_LIFCR_CDMEIF0                    0x00000004U\n#define DMA_LIFCR_CFEIF0                     0x00000001U\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7                     0x08000000U\n#define DMA_HIFCR_CHTIF7                     0x04000000U\n#define DMA_HIFCR_CTEIF7                     0x02000000U\n#define DMA_HIFCR_CDMEIF7                    0x01000000U\n#define DMA_HIFCR_CFEIF7                     0x00400000U\n#define DMA_HIFCR_CTCIF6                     0x00200000U\n#define DMA_HIFCR_CHTIF6                     0x00100000U\n#define DMA_HIFCR_CTEIF6                     0x00080000U\n#define DMA_HIFCR_CDMEIF6                    0x00040000U\n#define DMA_HIFCR_CFEIF6                     0x00010000U\n#define DMA_HIFCR_CTCIF5                     0x00000800U\n#define DMA_HIFCR_CHTIF5                     0x00000400U\n#define DMA_HIFCR_CTEIF5                     0x00000200U\n#define DMA_HIFCR_CDMEIF5                    0x00000100U\n#define DMA_HIFCR_CFEIF5                     0x00000040U\n#define DMA_HIFCR_CTCIF4                     0x00000020U\n#define DMA_HIFCR_CHTIF4                     0x00000010U\n#define DMA_HIFCR_CTEIF4                     0x00000008U\n#define DMA_HIFCR_CDMEIF4                    0x00000004U\n#define DMA_HIFCR_CFEIF4                     0x00000001U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */\n#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */\n#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */\n#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */\n#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */\n#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */\n#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */\n#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */\n#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */\n#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */\n#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */\n#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */\n#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */\n#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */\n#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */\n#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */\n#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */\n#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */\n#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */\n#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */\n#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */\n#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */\n#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */\n#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */\n#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */\n#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */\n#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */\n#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */\n#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */\n#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */\n#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */\n#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */\n#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */\n#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */\n#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */\n#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */\n#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */\n#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */\n#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */\n#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */\n#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */\n#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */\n#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */\n#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */\n#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */\n#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */\n#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */\n#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */\n#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */\n#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */\n#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */\n#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */\n#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */\n#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */\n#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */\n#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */\n#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */\n#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */\n#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */\n#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */\n#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */\n#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */\n#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */\n#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */\n#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */\n#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */\n#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */\n#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */\n#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */\n#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */\n#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */\n#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */\n#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */\n#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */\n#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */\n#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */\n#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */\n#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */\n#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */\n#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */\n#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */\n#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */\n#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */\n#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */\n#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */\n#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */\n#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */\n#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */\n#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */\n#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */\n#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */\n#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */\n#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */\n#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */\n#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */\n#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */\n#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */\n#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */\n#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */\n#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */\n#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */\n#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */\n#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */\n#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */\n#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */\n#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */\n#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */\n#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */\n#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */\n#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */\n#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */\n#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */\n#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */\n#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */\n#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */\n#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */\n#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */\n#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */\n#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */\n#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */\n#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */\n#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */\n#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */\n#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */\n#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */\n#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */\n#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */\n#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */\n#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */\n#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */\n#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */\n#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */\n#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY                    0x0000000FU\n#define FLASH_ACR_LATENCY_0WS                0x00000000U\n#define FLASH_ACR_LATENCY_1WS                0x00000001U\n#define FLASH_ACR_LATENCY_2WS                0x00000002U\n#define FLASH_ACR_LATENCY_3WS                0x00000003U\n#define FLASH_ACR_LATENCY_4WS                0x00000004U\n#define FLASH_ACR_LATENCY_5WS                0x00000005U\n#define FLASH_ACR_LATENCY_6WS                0x00000006U\n#define FLASH_ACR_LATENCY_7WS                0x00000007U\n\n#define FLASH_ACR_PRFTEN                     0x00000100U\n#define FLASH_ACR_ICEN                       0x00000200U\n#define FLASH_ACR_DCEN                       0x00000400U\n#define FLASH_ACR_ICRST                      0x00000800U\n#define FLASH_ACR_DCRST                      0x00001000U\n#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U\n#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP                         0x00000001U\n#define FLASH_SR_SOP                         0x00000002U\n#define FLASH_SR_WRPERR                      0x00000010U\n#define FLASH_SR_PGAERR                      0x00000020U\n#define FLASH_SR_PGPERR                      0x00000040U\n#define FLASH_SR_PGSERR                      0x00000080U\n#define FLASH_SR_BSY                         0x00010000U\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG                          0x00000001U\n#define FLASH_CR_SER                         0x00000002U\n#define FLASH_CR_MER                         0x00000004U\n#define FLASH_CR_SNB                         0x000000F8U\n#define FLASH_CR_SNB_0                       0x00000008U\n#define FLASH_CR_SNB_1                       0x00000010U\n#define FLASH_CR_SNB_2                       0x00000020U\n#define FLASH_CR_SNB_3                       0x00000040U\n#define FLASH_CR_SNB_4                       0x00000080U\n#define FLASH_CR_PSIZE                       0x00000300U\n#define FLASH_CR_PSIZE_0                     0x00000100U\n#define FLASH_CR_PSIZE_1                     0x00000200U\n#define FLASH_CR_STRT                        0x00010000U\n#define FLASH_CR_EOPIE                       0x01000000U\n#define FLASH_CR_LOCK                        0x80000000U\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK                 0x00000001U\n#define FLASH_OPTCR_OPTSTRT                 0x00000002U\n#define FLASH_OPTCR_BOR_LEV_0               0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1               0x00000008U\n#define FLASH_OPTCR_BOR_LEV                 0x0000000CU\n\n#define FLASH_OPTCR_WDG_SW                  0x00000020U\n#define FLASH_OPTCR_nRST_STOP               0x00000040U\n#define FLASH_OPTCR_nRST_STDBY              0x00000080U\n#define FLASH_OPTCR_RDP                     0x0000FF00U\n#define FLASH_OPTCR_RDP_0                   0x00000100U\n#define FLASH_OPTCR_RDP_1                   0x00000200U\n#define FLASH_OPTCR_RDP_2                   0x00000400U\n#define FLASH_OPTCR_RDP_3                   0x00000800U\n#define FLASH_OPTCR_RDP_4                   0x00001000U\n#define FLASH_OPTCR_RDP_5                   0x00002000U\n#define FLASH_OPTCR_RDP_6                   0x00004000U\n#define FLASH_OPTCR_RDP_7                   0x00008000U\n#define FLASH_OPTCR_nWRP                    0x0FFF0000U\n#define FLASH_OPTCR_nWRP_0                  0x00010000U\n#define FLASH_OPTCR_nWRP_1                  0x00020000U\n#define FLASH_OPTCR_nWRP_2                  0x00040000U\n#define FLASH_OPTCR_nWRP_3                  0x00080000U\n#define FLASH_OPTCR_nWRP_4                  0x00100000U\n#define FLASH_OPTCR_nWRP_5                  0x00200000U\n#define FLASH_OPTCR_nWRP_6                  0x00400000U\n#define FLASH_OPTCR_nWRP_7                  0x00800000U\n#define FLASH_OPTCR_nWRP_8                  0x01000000U\n#define FLASH_OPTCR_nWRP_9                  0x02000000U\n#define FLASH_OPTCR_nWRP_10                 0x04000000U\n#define FLASH_OPTCR_nWRP_11                 0x08000000U\n\n/******************************************************************************/\n/*                                                                            */\n/*                       Flexible Static Memory Controller                    */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define  FSMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */\n#define  FSMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\n\n#define  FSMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\n#define  FSMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */\n#define  FSMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */\n\n#define  FSMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable                    */\n#define  FSMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */\n#define  FSMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */\n#define  FSMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */\n#define  FSMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */\n#define  FSMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit                       */\n#define  FSMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit                        */\n#define  FSMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */\n#define  FSMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */\n#define  FSMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define  FSMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                */\n#define  FSMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\n\n#define  FSMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\n#define  FSMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */\n#define  FSMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */\n\n#define  FSMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable                    */\n#define  FSMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */\n#define  FSMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */\n#define  FSMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */\n#define  FSMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */\n#define  FSMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit                       */\n#define  FSMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit                        */\n#define  FSMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */\n#define  FSMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */\n#define  FSMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define  FSMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */\n#define  FSMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\n\n#define  FSMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\n#define  FSMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */\n#define  FSMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */\n\n#define  FSMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable                    */\n#define  FSMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */\n#define  FSMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */\n#define  FSMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */\n#define  FSMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */\n#define  FSMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit                       */\n#define  FSMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit                        */\n#define  FSMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */\n#define  FSMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */\n#define  FSMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define  FSMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit */\n#define  FSMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\n\n#define  FSMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\n#define  FSMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */\n#define  FSMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */\n\n#define  FSMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable                    */\n#define  FSMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit                       */\n#define  FSMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit               */\n#define  FSMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support             */\n#define  FSMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration              */\n#define  FSMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit                       */\n#define  FSMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit                        */\n#define  FSMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable                   */\n#define  FSMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait                      */\n#define  FSMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define  FSMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */\n#define  FSMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */\n#define  FSMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */\n#define  FSMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\n#define  FSMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\n#define  FSMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\n#define  FSMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */\n#define  FSMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */\n#define  FSMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */\n#define  FSMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */\n#define  FSMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */\n#define  FSMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */\n#define  FSMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */\n#define  FSMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\n#define  FSMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\n#define  FSMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\n#define  FSMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\n#define  FSMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\n#define  FSMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\n#define  FSMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\n\n#define  FSMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */\n#define  FSMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */\n#define  FSMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */\n#define  FSMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */\n\n#define  FSMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\n#define  FSMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define  FSMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */\n#define  FSMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */\n#define  FSMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */\n#define  FSMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\n#define  FSMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\n#define  FSMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\n#define  FSMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */\n#define  FSMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */\n#define  FSMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */\n#define  FSMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */\n#define  FSMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */\n#define  FSMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */\n#define  FSMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */\n#define  FSMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\n#define  FSMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\n#define  FSMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\n#define  FSMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\n#define  FSMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\n#define  FSMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\n#define  FSMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\n\n#define  FSMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */\n#define  FSMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */\n#define  FSMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */\n#define  FSMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */\n\n#define  FSMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\n#define  FSMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define  FSMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */\n#define  FSMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */\n#define  FSMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */\n#define  FSMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\n#define  FSMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\n#define  FSMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\n#define  FSMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */\n#define  FSMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */\n#define  FSMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */\n#define  FSMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */\n#define  FSMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */\n#define  FSMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */\n#define  FSMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */\n#define  FSMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\n#define  FSMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\n#define  FSMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\n#define  FSMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\n#define  FSMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\n#define  FSMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\n#define  FSMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\n\n#define  FSMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */\n#define  FSMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */\n#define  FSMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */\n#define  FSMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */\n\n#define  FSMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\n#define  FSMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define  FSMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */\n#define  FSMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */\n#define  FSMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */\n#define  FSMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\n#define  FSMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\n#define  FSMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\n#define  FSMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */\n#define  FSMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */\n#define  FSMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */\n#define  FSMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */\n#define  FSMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */\n#define  FSMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */\n#define  FSMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */\n#define  FSMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\n#define  FSMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\n#define  FSMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\n#define  FSMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\n#define  FSMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\n#define  FSMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\n#define  FSMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\n\n#define  FSMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */\n#define  FSMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */\n#define  FSMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */\n#define  FSMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */\n\n#define  FSMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\n#define  FSMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define  FSMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */\n#define  FSMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */\n#define  FSMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */\n#define  FSMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\n#define  FSMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\n#define  FSMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\n#define  FSMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */\n#define  FSMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */\n#define  FSMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */\n#define  FSMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */\n#define  FSMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */\n#define  FSMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */\n#define  FSMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */\n#define  FSMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define  FSMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */\n#define  FSMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */\n#define  FSMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */\n#define  FSMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\n#define  FSMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define  FSMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */\n#define  FSMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */\n#define  FSMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */\n#define  FSMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\n#define  FSMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\n#define  FSMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\n#define  FSMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */\n#define  FSMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */\n#define  FSMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */\n#define  FSMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */\n#define  FSMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */\n#define  FSMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */\n#define  FSMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */\n#define  FSMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define  FSMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */\n#define  FSMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */\n#define  FSMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */\n#define  FSMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\n#define  FSMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define  FSMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */\n#define  FSMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */\n#define  FSMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */\n#define  FSMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\n#define  FSMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\n#define  FSMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\n#define  FSMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [7:0] bits (Data-phase duration) */\n#define  FSMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */\n#define  FSMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */\n#define  FSMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */\n#define  FSMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */\n#define  FSMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */\n#define  FSMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */\n#define  FSMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */\n#define  FSMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define  FSMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */\n#define  FSMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */\n#define  FSMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */\n#define  FSMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\n#define  FSMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define  FSMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */\n#define  FSMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */\n#define  FSMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */\n#define  FSMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */\n\n#define  FSMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\n#define  FSMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\n#define  FSMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\n#define  FSMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\n\n#define  FSMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */\n#define  FSMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */\n#define  FSMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */\n#define  FSMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */\n#define  FSMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */\n#define  FSMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */\n#define  FSMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */\n#define  FSMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define  FSMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */\n#define  FSMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */\n#define  FSMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */\n#define  FSMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */\n\n#define  FSMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\n#define  FSMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\n\n/******************  Bit definition for FSMC_PCR2 register  *******************/\n#define  FSMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */\n#define  FSMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */\n#define  FSMC_PCR2_PTYP                      0x00000008U        /*!<Memory type */\n\n#define  FSMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define  FSMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */\n\n#define  FSMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define  FSMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */\n#define  FSMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */\n#define  FSMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */\n#define  FSMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */\n\n#define  FSMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */\n#define  FSMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */\n#define  FSMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */\n#define  FSMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */\n#define  FSMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */\n\n#define  FSMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size) */\n#define  FSMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */\n#define  FSMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */\n#define  FSMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */\n\n/******************  Bit definition for FSMC_PCR3 register  *******************/\n#define  FSMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */\n#define  FSMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */\n#define  FSMC_PCR3_PTYP                      0x00000008U        /*!<Memory type */\n\n#define  FSMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define  FSMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */\n\n#define  FSMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define  FSMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */\n#define  FSMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */\n#define  FSMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */\n#define  FSMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */\n\n#define  FSMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */\n#define  FSMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */\n#define  FSMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */\n#define  FSMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */\n#define  FSMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */\n\n#define  FSMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */\n#define  FSMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */\n#define  FSMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */\n#define  FSMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */\n\n/******************  Bit definition for FSMC_PCR4 register  *******************/\n#define  FSMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit */\n#define  FSMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */\n#define  FSMC_PCR4_PTYP                      0x00000008U        /*!<Memory type */\n\n#define  FSMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define  FSMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */\n#define  FSMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */\n\n#define  FSMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit */\n\n#define  FSMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define  FSMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */\n#define  FSMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */\n#define  FSMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */\n#define  FSMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */\n\n#define  FSMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay) */\n#define  FSMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */\n#define  FSMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */\n#define  FSMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */\n#define  FSMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */\n\n#define  FSMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size) */\n#define  FSMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */\n#define  FSMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */\n#define  FSMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */\n\n/*******************  Bit definition for FSMC_SR2 register  *******************/\n#define  FSMC_SR2_IRS                        0x00000001U        /*!<Interrupt Rising Edge status */\n#define  FSMC_SR2_ILS                        0x00000002U        /*!<Interrupt Level status */\n#define  FSMC_SR2_IFS                        0x00000004U        /*!<Interrupt Falling Edge status */\n#define  FSMC_SR2_IREN                       0x00000008U        /*!<Interrupt Rising Edge detection Enable bit */\n#define  FSMC_SR2_ILEN                       0x00000010U        /*!<Interrupt Level detection Enable bit */\n#define  FSMC_SR2_IFEN                       0x00000020U        /*!<Interrupt Falling Edge detection Enable bit */\n#define  FSMC_SR2_FEMPT                      0x00000040U        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR3 register  *******************/\n#define  FSMC_SR3_IRS                        0x00000001U        /*!<Interrupt Rising Edge status */\n#define  FSMC_SR3_ILS                        0x00000002U        /*!<Interrupt Level status */\n#define  FSMC_SR3_IFS                        0x00000004U        /*!<Interrupt Falling Edge status */\n#define  FSMC_SR3_IREN                       0x00000008U        /*!<Interrupt Rising Edge detection Enable bit */\n#define  FSMC_SR3_ILEN                       0x00000010U        /*!<Interrupt Level detection Enable bit */\n#define  FSMC_SR3_IFEN                       0x00000020U        /*!<Interrupt Falling Edge detection Enable bit */\n#define  FSMC_SR3_FEMPT                      0x00000040U        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR4 register  *******************/\n#define  FSMC_SR4_IRS                        0x00000001U        /*!<Interrupt Rising Edge status */\n#define  FSMC_SR4_ILS                        0x00000002U        /*!<Interrupt Level status */\n#define  FSMC_SR4_IFS                        0x00000004U        /*!<Interrupt Falling Edge status */\n#define  FSMC_SR4_IREN                       0x00000008U        /*!<Interrupt Rising Edge detection Enable bit */\n#define  FSMC_SR4_ILEN                       0x00000010U        /*!<Interrupt Level detection Enable bit */\n#define  FSMC_SR4_IFEN                       0x00000020U        /*!<Interrupt Falling Edge detection Enable bit */\n#define  FSMC_SR4_FEMPT                      0x00000040U        /*!<FIFO empty */\n\n/******************  Bit definition for FSMC_PMEM2 register  ******************/\n#define  FSMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define  FSMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */\n#define  FSMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */\n#define  FSMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */\n#define  FSMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */\n#define  FSMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */\n#define  FSMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */\n#define  FSMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */\n#define  FSMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define  FSMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */\n#define  FSMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */\n#define  FSMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */\n#define  FSMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */\n#define  FSMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */\n#define  FSMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */\n#define  FSMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */\n#define  FSMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define  FSMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */\n#define  FSMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */\n#define  FSMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */\n#define  FSMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */\n#define  FSMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */\n#define  FSMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */\n#define  FSMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */\n#define  FSMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define  FSMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */\n#define  FSMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */\n#define  FSMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */\n#define  FSMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */\n#define  FSMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */\n#define  FSMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */\n#define  FSMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */\n#define  FSMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_PMEM3 register  ******************/\n#define  FSMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\n#define  FSMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */\n#define  FSMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */\n#define  FSMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */\n#define  FSMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */\n#define  FSMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */\n#define  FSMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */\n#define  FSMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */\n#define  FSMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\n#define  FSMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */\n#define  FSMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */\n#define  FSMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */\n#define  FSMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */\n#define  FSMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */\n#define  FSMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */\n#define  FSMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */\n#define  FSMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\n#define  FSMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */\n#define  FSMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */\n#define  FSMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */\n#define  FSMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */\n#define  FSMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */\n#define  FSMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */\n#define  FSMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */\n#define  FSMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\n#define  FSMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */\n#define  FSMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */\n#define  FSMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */\n#define  FSMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */\n#define  FSMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */\n#define  FSMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */\n#define  FSMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */\n#define  FSMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_PMEM4 register  ******************/\n#define  FSMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\n#define  FSMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */\n#define  FSMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */\n#define  FSMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */\n#define  FSMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */\n#define  FSMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */\n#define  FSMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */\n#define  FSMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */\n#define  FSMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\n#define  FSMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */\n#define  FSMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */\n#define  FSMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */\n#define  FSMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */\n#define  FSMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */\n#define  FSMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */\n#define  FSMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */\n#define  FSMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\n#define  FSMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */\n#define  FSMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */\n#define  FSMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */\n#define  FSMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */\n#define  FSMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */\n#define  FSMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */\n#define  FSMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */\n#define  FSMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\n#define  FSMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */\n#define  FSMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */\n#define  FSMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */\n#define  FSMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */\n#define  FSMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */\n#define  FSMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */\n#define  FSMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */\n#define  FSMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_PATT2 register  ******************/\n#define  FSMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define  FSMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */\n#define  FSMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */\n#define  FSMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */\n#define  FSMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */\n#define  FSMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */\n#define  FSMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */\n#define  FSMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */\n#define  FSMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define  FSMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */\n#define  FSMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */\n#define  FSMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */\n#define  FSMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */\n#define  FSMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */\n#define  FSMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */\n#define  FSMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */\n#define  FSMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define  FSMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */\n#define  FSMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */\n#define  FSMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */\n#define  FSMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */\n#define  FSMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */\n#define  FSMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */\n#define  FSMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */\n#define  FSMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define  FSMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */\n#define  FSMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */\n#define  FSMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */\n#define  FSMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */\n#define  FSMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */\n#define  FSMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */\n#define  FSMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */\n#define  FSMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_PATT3 register  ******************/\n#define  FSMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\n#define  FSMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */\n#define  FSMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */\n#define  FSMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */\n#define  FSMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */\n#define  FSMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */\n#define  FSMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */\n#define  FSMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */\n#define  FSMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\n#define  FSMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */\n#define  FSMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */\n#define  FSMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */\n#define  FSMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */\n#define  FSMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */\n#define  FSMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */\n#define  FSMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */\n#define  FSMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\n#define  FSMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */\n#define  FSMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */\n#define  FSMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */\n#define  FSMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */\n#define  FSMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */\n#define  FSMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */\n#define  FSMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */\n#define  FSMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\n#define  FSMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */\n#define  FSMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */\n#define  FSMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */\n#define  FSMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */\n#define  FSMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */\n#define  FSMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */\n#define  FSMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */\n#define  FSMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_PATT4 register  ******************/\n#define  FSMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\n#define  FSMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */\n#define  FSMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */\n#define  FSMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */\n#define  FSMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */\n#define  FSMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */\n#define  FSMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */\n#define  FSMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */\n#define  FSMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\n#define  FSMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */\n#define  FSMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */\n#define  FSMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */\n#define  FSMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */\n#define  FSMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */\n#define  FSMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */\n#define  FSMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */\n#define  FSMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\n#define  FSMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */\n#define  FSMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */\n#define  FSMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */\n#define  FSMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */\n#define  FSMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */\n#define  FSMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */\n#define  FSMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */\n#define  FSMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\n#define  FSMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */\n#define  FSMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */\n#define  FSMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */\n#define  FSMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */\n#define  FSMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */\n#define  FSMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */\n#define  FSMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */\n#define  FSMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_PIO4 register  *******************/\n#define  FSMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */\n#define  FSMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */\n#define  FSMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */\n#define  FSMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */\n#define  FSMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */\n#define  FSMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */\n#define  FSMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */\n#define  FSMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */\n#define  FSMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */\n\n#define  FSMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\n#define  FSMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */\n#define  FSMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */\n#define  FSMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */\n#define  FSMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */\n#define  FSMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */\n#define  FSMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */\n#define  FSMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */\n#define  FSMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */\n\n#define  FSMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\n#define  FSMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */\n#define  FSMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */\n#define  FSMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */\n#define  FSMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */\n#define  FSMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */\n#define  FSMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */\n#define  FSMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */\n#define  FSMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */\n\n#define  FSMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\n#define  FSMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */\n#define  FSMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */\n#define  FSMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */\n#define  FSMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */\n#define  FSMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */\n#define  FSMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */\n#define  FSMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */\n#define  FSMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */\n\n/******************  Bit definition for FSMC_ECCR2 register  ******************/\n#define  FSMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */\n\n/******************  Bit definition for FSMC_ECCR3 register  ******************/\n#define  FSMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0                    ((uint32_t)0x00000003U)\n#define GPIO_MODER_MODE0_0                  ((uint32_t)0x00000001U)\n#define GPIO_MODER_MODE0_1                  ((uint32_t)0x00000002U)\n#define GPIO_MODER_MODE1                    ((uint32_t)0x0000000CU)\n#define GPIO_MODER_MODE1_0                  ((uint32_t)0x00000004U)\n#define GPIO_MODER_MODE1_1                  ((uint32_t)0x00000008U)\n#define GPIO_MODER_MODE2                    ((uint32_t)0x00000030U)\n#define GPIO_MODER_MODE2_0                  ((uint32_t)0x00000010U)\n#define GPIO_MODER_MODE2_1                  ((uint32_t)0x00000020U)\n#define GPIO_MODER_MODE3                    ((uint32_t)0x000000C0U)\n#define GPIO_MODER_MODE3_0                  ((uint32_t)0x00000040U)\n#define GPIO_MODER_MODE3_1                  ((uint32_t)0x00000080U)\n#define GPIO_MODER_MODE4                    ((uint32_t)0x00000300U)\n#define GPIO_MODER_MODE4_0                  ((uint32_t)0x00000100U)\n#define GPIO_MODER_MODE4_1                  ((uint32_t)0x00000200U)\n#define GPIO_MODER_MODE5                    ((uint32_t)0x00000C00U)\n#define GPIO_MODER_MODE5_0                  ((uint32_t)0x00000400U)\n#define GPIO_MODER_MODE5_1                  ((uint32_t)0x00000800U)\n#define GPIO_MODER_MODE6                    ((uint32_t)0x00003000U)\n#define GPIO_MODER_MODE6_0                  ((uint32_t)0x00001000U)\n#define GPIO_MODER_MODE6_1                  ((uint32_t)0x00002000U)\n#define GPIO_MODER_MODE7                    ((uint32_t)0x0000C000U)\n#define GPIO_MODER_MODE7_0                  ((uint32_t)0x00004000U)\n#define GPIO_MODER_MODE7_1                  ((uint32_t)0x00008000U)\n#define GPIO_MODER_MODE8                    ((uint32_t)0x00030000U)\n#define GPIO_MODER_MODE8_0                  ((uint32_t)0x00010000U)\n#define GPIO_MODER_MODE8_1                  ((uint32_t)0x00020000U)\n#define GPIO_MODER_MODE9                    ((uint32_t)0x000C0000U)\n#define GPIO_MODER_MODE9_0                  ((uint32_t)0x00040000U)\n#define GPIO_MODER_MODE9_1                  ((uint32_t)0x00080000U)\n#define GPIO_MODER_MODE10                   ((uint32_t)0x00300000U)\n#define GPIO_MODER_MODE10_0                 ((uint32_t)0x00100000U)\n#define GPIO_MODER_MODE10_1                 ((uint32_t)0x00200000U)\n#define GPIO_MODER_MODE11                   ((uint32_t)0x00C00000U)\n#define GPIO_MODER_MODE11_0                 ((uint32_t)0x00400000U)\n#define GPIO_MODER_MODE11_1                 ((uint32_t)0x00800000U)\n#define GPIO_MODER_MODE12                   ((uint32_t)0x03000000U)\n#define GPIO_MODER_MODE12_0                 ((uint32_t)0x01000000U)\n#define GPIO_MODER_MODE12_1                 ((uint32_t)0x02000000U)\n#define GPIO_MODER_MODE13                   ((uint32_t)0x0C000000U)\n#define GPIO_MODER_MODE13_0                 ((uint32_t)0x04000000U)\n#define GPIO_MODER_MODE13_1                 ((uint32_t)0x08000000U)\n#define GPIO_MODER_MODE14                   ((uint32_t)0x30000000U)\n#define GPIO_MODER_MODE14_0                 ((uint32_t)0x10000000U)\n#define GPIO_MODER_MODE14_1                 ((uint32_t)0x20000000U)\n#define GPIO_MODER_MODE15                   ((uint32_t)0xC0000000U)\n#define GPIO_MODER_MODE15_0                 ((uint32_t)0x40000000U)\n#define GPIO_MODER_MODE15_1                 ((uint32_t)0x80000000U)\n/* Legacy defines */\n#define GPIO_MODER_MODER0                    0x00000003U\n#define GPIO_MODER_MODER0_0                  0x00000001U\n#define GPIO_MODER_MODER0_1                  0x00000002U\n#define GPIO_MODER_MODER1                    0x0000000CU\n#define GPIO_MODER_MODER1_0                  0x00000004U\n#define GPIO_MODER_MODER1_1                  0x00000008U\n#define GPIO_MODER_MODER2                    0x00000030U\n#define GPIO_MODER_MODER2_0                  0x00000010U\n#define GPIO_MODER_MODER2_1                  0x00000020U\n#define GPIO_MODER_MODER3                    0x000000C0U\n#define GPIO_MODER_MODER3_0                  0x00000040U\n#define GPIO_MODER_MODER3_1                  0x00000080U\n#define GPIO_MODER_MODER4                    0x00000300U\n#define GPIO_MODER_MODER4_0                  0x00000100U\n#define GPIO_MODER_MODER4_1                  0x00000200U\n#define GPIO_MODER_MODER5                    0x00000C00U\n#define GPIO_MODER_MODER5_0                  0x00000400U\n#define GPIO_MODER_MODER5_1                  0x00000800U\n#define GPIO_MODER_MODER6                    0x00003000U\n#define GPIO_MODER_MODER6_0                  0x00001000U\n#define GPIO_MODER_MODER6_1                  0x00002000U\n#define GPIO_MODER_MODER7                    0x0000C000U\n#define GPIO_MODER_MODER7_0                  0x00004000U\n#define GPIO_MODER_MODER7_1                  0x00008000U\n#define GPIO_MODER_MODER8                    0x00030000U\n#define GPIO_MODER_MODER8_0                  0x00010000U\n#define GPIO_MODER_MODER8_1                  0x00020000U\n#define GPIO_MODER_MODER9                    0x000C0000U\n#define GPIO_MODER_MODER9_0                  0x00040000U\n#define GPIO_MODER_MODER9_1                  0x00080000U\n#define GPIO_MODER_MODER10                   0x00300000U\n#define GPIO_MODER_MODER10_0                 0x00100000U\n#define GPIO_MODER_MODER10_1                 0x00200000U\n#define GPIO_MODER_MODER11                   0x00C00000U\n#define GPIO_MODER_MODER11_0                 0x00400000U\n#define GPIO_MODER_MODER11_1                 0x00800000U\n#define GPIO_MODER_MODER12                   0x03000000U\n#define GPIO_MODER_MODER12_0                 0x01000000U\n#define GPIO_MODER_MODER12_1                 0x02000000U\n#define GPIO_MODER_MODER13                   0x0C000000U\n#define GPIO_MODER_MODER13_0                 0x04000000U\n#define GPIO_MODER_MODER13_1                 0x08000000U\n#define GPIO_MODER_MODER14                   0x30000000U\n#define GPIO_MODER_MODER14_0                 0x10000000U\n#define GPIO_MODER_MODER14_1                 0x20000000U\n#define GPIO_MODER_MODER15                   0xC0000000U\n#define GPIO_MODER_MODER15_0                 0x40000000U\n#define GPIO_MODER_MODER15_1                 0x80000000U\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0                     ((uint32_t)0x00000001U)\n#define GPIO_OTYPER_OT1                     ((uint32_t)0x00000002U)\n#define GPIO_OTYPER_OT2                     ((uint32_t)0x00000004U)\n#define GPIO_OTYPER_OT3                     ((uint32_t)0x00000008U)\n#define GPIO_OTYPER_OT4                     ((uint32_t)0x00000010U)\n#define GPIO_OTYPER_OT5                     ((uint32_t)0x00000020U)\n#define GPIO_OTYPER_OT6                     ((uint32_t)0x00000040U)\n#define GPIO_OTYPER_OT7                     ((uint32_t)0x00000080U)\n#define GPIO_OTYPER_OT8                     ((uint32_t)0x00000100U)\n#define GPIO_OTYPER_OT9                     ((uint32_t)0x00000200U)\n#define GPIO_OTYPER_OT10                    ((uint32_t)0x00000400U)\n#define GPIO_OTYPER_OT11                    ((uint32_t)0x00000800U)\n#define GPIO_OTYPER_OT12                    ((uint32_t)0x00001000U)\n#define GPIO_OTYPER_OT13                    ((uint32_t)0x00002000U)\n#define GPIO_OTYPER_OT14                    ((uint32_t)0x00004000U)\n#define GPIO_OTYPER_OT15                    ((uint32_t)0x00008000U)\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0                ((uint32_t)0x00000003U)\n#define GPIO_OSPEEDR_OSPEED0_0              ((uint32_t)0x00000001U)\n#define GPIO_OSPEEDR_OSPEED0_1              ((uint32_t)0x00000002U)\n#define GPIO_OSPEEDR_OSPEED1                ((uint32_t)0x0000000CU)\n#define GPIO_OSPEEDR_OSPEED1_0              ((uint32_t)0x00000004U)\n#define GPIO_OSPEEDR_OSPEED1_1              ((uint32_t)0x00000008U)\n#define GPIO_OSPEEDR_OSPEED2                ((uint32_t)0x00000030U)\n#define GPIO_OSPEEDR_OSPEED2_0              ((uint32_t)0x00000010U)\n#define GPIO_OSPEEDR_OSPEED2_1              ((uint32_t)0x00000020U)\n#define GPIO_OSPEEDR_OSPEED3                ((uint32_t)0x000000C0U)\n#define GPIO_OSPEEDR_OSPEED3_0              ((uint32_t)0x00000040U)\n#define GPIO_OSPEEDR_OSPEED3_1              ((uint32_t)0x00000080U)\n#define GPIO_OSPEEDR_OSPEED4                ((uint32_t)0x00000300U)\n#define GPIO_OSPEEDR_OSPEED4_0              ((uint32_t)0x00000100U)\n#define GPIO_OSPEEDR_OSPEED4_1              ((uint32_t)0x00000200U)\n#define GPIO_OSPEEDR_OSPEED5                ((uint32_t)0x00000C00U)\n#define GPIO_OSPEEDR_OSPEED5_0              ((uint32_t)0x00000400U)\n#define GPIO_OSPEEDR_OSPEED5_1              ((uint32_t)0x00000800U)\n#define GPIO_OSPEEDR_OSPEED6                ((uint32_t)0x00003000U)\n#define GPIO_OSPEEDR_OSPEED6_0              ((uint32_t)0x00001000U)\n#define GPIO_OSPEEDR_OSPEED6_1              ((uint32_t)0x00002000U)\n#define GPIO_OSPEEDR_OSPEED7                ((uint32_t)0x0000C000U)\n#define GPIO_OSPEEDR_OSPEED7_0              ((uint32_t)0x00004000U)\n#define GPIO_OSPEEDR_OSPEED7_1              ((uint32_t)0x00008000U)\n#define GPIO_OSPEEDR_OSPEED8                ((uint32_t)0x00030000U)\n#define GPIO_OSPEEDR_OSPEED8_0              ((uint32_t)0x00010000U)\n#define GPIO_OSPEEDR_OSPEED8_1              ((uint32_t)0x00020000U)\n#define GPIO_OSPEEDR_OSPEED9                ((uint32_t)0x000C0000U)\n#define GPIO_OSPEEDR_OSPEED9_0              ((uint32_t)0x00040000U)\n#define GPIO_OSPEEDR_OSPEED9_1              ((uint32_t)0x00080000U)\n#define GPIO_OSPEEDR_OSPEED10               ((uint32_t)0x00300000U)\n#define GPIO_OSPEEDR_OSPEED10_0             ((uint32_t)0x00100000U)\n#define GPIO_OSPEEDR_OSPEED10_1             ((uint32_t)0x00200000U)\n#define GPIO_OSPEEDR_OSPEED11               ((uint32_t)0x00C00000U)\n#define GPIO_OSPEEDR_OSPEED11_0             ((uint32_t)0x00400000U)\n#define GPIO_OSPEEDR_OSPEED11_1             ((uint32_t)0x00800000U)\n#define GPIO_OSPEEDR_OSPEED12               ((uint32_t)0x03000000U)\n#define GPIO_OSPEEDR_OSPEED12_0             ((uint32_t)0x01000000U)\n#define GPIO_OSPEEDR_OSPEED12_1             ((uint32_t)0x02000000U)\n#define GPIO_OSPEEDR_OSPEED13               ((uint32_t)0x0C000000U)\n#define GPIO_OSPEEDR_OSPEED13_0             ((uint32_t)0x04000000U)\n#define GPIO_OSPEEDR_OSPEED13_1             ((uint32_t)0x08000000U)\n#define GPIO_OSPEEDR_OSPEED14               ((uint32_t)0x30000000U)\n#define GPIO_OSPEEDR_OSPEED14_0             ((uint32_t)0x10000000U)\n#define GPIO_OSPEEDR_OSPEED14_1             ((uint32_t)0x20000000U)\n#define GPIO_OSPEEDR_OSPEED15               ((uint32_t)0xC0000000U)\n#define GPIO_OSPEEDR_OSPEED15_0             ((uint32_t)0x40000000U)\n#define GPIO_OSPEEDR_OSPEED15_1             ((uint32_t)0x80000000U)\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0                    ((uint32_t)0x00000003U)\n#define GPIO_PUPDR_PUPD0_0                  ((uint32_t)0x00000001U)\n#define GPIO_PUPDR_PUPD0_1                  ((uint32_t)0x00000002U)\n#define GPIO_PUPDR_PUPD1                    ((uint32_t)0x0000000CU)\n#define GPIO_PUPDR_PUPD1_0                  ((uint32_t)0x00000004U)\n#define GPIO_PUPDR_PUPD1_1                  ((uint32_t)0x00000008U)\n#define GPIO_PUPDR_PUPD2                    ((uint32_t)0x00000030U)\n#define GPIO_PUPDR_PUPD2_0                  ((uint32_t)0x00000010U)\n#define GPIO_PUPDR_PUPD2_1                  ((uint32_t)0x00000020U)\n#define GPIO_PUPDR_PUPD3                    ((uint32_t)0x000000C0U)\n#define GPIO_PUPDR_PUPD3_0                  ((uint32_t)0x00000040U)\n#define GPIO_PUPDR_PUPD3_1                  ((uint32_t)0x00000080U)\n#define GPIO_PUPDR_PUPD4                    ((uint32_t)0x00000300U)\n#define GPIO_PUPDR_PUPD4_0                  ((uint32_t)0x00000100U)\n#define GPIO_PUPDR_PUPD4_1                  ((uint32_t)0x00000200U)\n#define GPIO_PUPDR_PUPD5                    ((uint32_t)0x00000C00U)\n#define GPIO_PUPDR_PUPD5_0                  ((uint32_t)0x00000400U)\n#define GPIO_PUPDR_PUPD5_1                  ((uint32_t)0x00000800U)\n#define GPIO_PUPDR_PUPD6                    ((uint32_t)0x00003000U)\n#define GPIO_PUPDR_PUPD6_0                  ((uint32_t)0x00001000U)\n#define GPIO_PUPDR_PUPD6_1                  ((uint32_t)0x00002000U)\n#define GPIO_PUPDR_PUPD7                    ((uint32_t)0x0000C000U)\n#define GPIO_PUPDR_PUPD7_0                  ((uint32_t)0x00004000U)\n#define GPIO_PUPDR_PUPD7_1                  ((uint32_t)0x00008000U)\n#define GPIO_PUPDR_PUPD8                    ((uint32_t)0x00030000U)\n#define GPIO_PUPDR_PUPD8_0                  ((uint32_t)0x00010000U)\n#define GPIO_PUPDR_PUPD8_1                  ((uint32_t)0x00020000U)\n#define GPIO_PUPDR_PUPD9                    ((uint32_t)0x000C0000U)\n#define GPIO_PUPDR_PUPD9_0                  ((uint32_t)0x00040000U)\n#define GPIO_PUPDR_PUPD9_1                  ((uint32_t)0x00080000U)\n#define GPIO_PUPDR_PUPD10                   ((uint32_t)0x00300000U)\n#define GPIO_PUPDR_PUPD10_0                 ((uint32_t)0x00100000U)\n#define GPIO_PUPDR_PUPD10_1                 ((uint32_t)0x00200000U)\n#define GPIO_PUPDR_PUPD11                   ((uint32_t)0x00C00000U)\n#define GPIO_PUPDR_PUPD11_0                 ((uint32_t)0x00400000U)\n#define GPIO_PUPDR_PUPD11_1                 ((uint32_t)0x00800000U)\n#define GPIO_PUPDR_PUPD12                   ((uint32_t)0x03000000U)\n#define GPIO_PUPDR_PUPD12_0                 ((uint32_t)0x01000000U)\n#define GPIO_PUPDR_PUPD12_1                 ((uint32_t)0x02000000U)\n#define GPIO_PUPDR_PUPD13                   ((uint32_t)0x0C000000U)\n#define GPIO_PUPDR_PUPD13_0                 ((uint32_t)0x04000000U)\n#define GPIO_PUPDR_PUPD13_1                 ((uint32_t)0x08000000U)\n#define GPIO_PUPDR_PUPD14                   ((uint32_t)0x30000000U)\n#define GPIO_PUPDR_PUPD14_0                 ((uint32_t)0x10000000U)\n#define GPIO_PUPDR_PUPD14_1                 ((uint32_t)0x20000000U)\n#define GPIO_PUPDR_PUPD15                   ((uint32_t)0xC0000000U)\n#define GPIO_PUPDR_PUPD15_0                 ((uint32_t)0x40000000U)\n#define GPIO_PUPDR_PUPD15_1                 ((uint32_t)0x80000000U)\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0                        ((uint32_t)0x00000001U)\n#define GPIO_IDR_ID1                        ((uint32_t)0x00000002U)\n#define GPIO_IDR_ID2                        ((uint32_t)0x00000004U)\n#define GPIO_IDR_ID3                        ((uint32_t)0x00000008U)\n#define GPIO_IDR_ID4                        ((uint32_t)0x00000010U)\n#define GPIO_IDR_ID5                        ((uint32_t)0x00000020U)\n#define GPIO_IDR_ID6                        ((uint32_t)0x00000040U)\n#define GPIO_IDR_ID7                        ((uint32_t)0x00000080U)\n#define GPIO_IDR_ID8                        ((uint32_t)0x00000100U)\n#define GPIO_IDR_ID9                        ((uint32_t)0x00000200U)\n#define GPIO_IDR_ID10                       ((uint32_t)0x00000400U)\n#define GPIO_IDR_ID11                       ((uint32_t)0x00000800U)\n#define GPIO_IDR_ID12                       ((uint32_t)0x00001000U)\n#define GPIO_IDR_ID13                       ((uint32_t)0x00002000U)\n#define GPIO_IDR_ID14                       ((uint32_t)0x00004000U)\n#define GPIO_IDR_ID15                       ((uint32_t)0x00008000U)\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0                        ((uint32_t)0x00000001U)\n#define GPIO_ODR_OD1                        ((uint32_t)0x00000002U)\n#define GPIO_ODR_OD2                        ((uint32_t)0x00000004U)\n#define GPIO_ODR_OD3                        ((uint32_t)0x00000008U)\n#define GPIO_ODR_OD4                        ((uint32_t)0x00000010U)\n#define GPIO_ODR_OD5                        ((uint32_t)0x00000020U)\n#define GPIO_ODR_OD6                        ((uint32_t)0x00000040U)\n#define GPIO_ODR_OD7                        ((uint32_t)0x00000080U)\n#define GPIO_ODR_OD8                        ((uint32_t)0x00000100U)\n#define GPIO_ODR_OD9                        ((uint32_t)0x00000200U)\n#define GPIO_ODR_OD10                       ((uint32_t)0x00000400U)\n#define GPIO_ODR_OD11                       ((uint32_t)0x00000800U)\n#define GPIO_ODR_OD12                       ((uint32_t)0x00001000U)\n#define GPIO_ODR_OD13                       ((uint32_t)0x00002000U)\n#define GPIO_ODR_OD14                       ((uint32_t)0x00004000U)\n#define GPIO_ODR_OD15                       ((uint32_t)0x00008000U)\n\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0                       ((uint32_t)0x00000001U)\n#define GPIO_BSRR_BS1                       ((uint32_t)0x00000002U)\n#define GPIO_BSRR_BS2                       ((uint32_t)0x00000004U)\n#define GPIO_BSRR_BS3                       ((uint32_t)0x00000008U)\n#define GPIO_BSRR_BS4                       ((uint32_t)0x00000010U)\n#define GPIO_BSRR_BS5                       ((uint32_t)0x00000020U)\n#define GPIO_BSRR_BS6                       ((uint32_t)0x00000040U)\n#define GPIO_BSRR_BS7                       ((uint32_t)0x00000080U)\n#define GPIO_BSRR_BS8                       ((uint32_t)0x00000100U)\n#define GPIO_BSRR_BS9                       ((uint32_t)0x00000200U)\n#define GPIO_BSRR_BS10                      ((uint32_t)0x00000400U)\n#define GPIO_BSRR_BS11                      ((uint32_t)0x00000800U)\n#define GPIO_BSRR_BS12                      ((uint32_t)0x00001000U)\n#define GPIO_BSRR_BS13                      ((uint32_t)0x00002000U)\n#define GPIO_BSRR_BS14                      ((uint32_t)0x00004000U)\n#define GPIO_BSRR_BS15                      ((uint32_t)0x00008000U)\n#define GPIO_BSRR_BR0                       ((uint32_t)0x00010000U)\n#define GPIO_BSRR_BR1                       ((uint32_t)0x00020000U)\n#define GPIO_BSRR_BR2                       ((uint32_t)0x00040000U)\n#define GPIO_BSRR_BR3                       ((uint32_t)0x00080000U)\n#define GPIO_BSRR_BR4                       ((uint32_t)0x00100000U)\n#define GPIO_BSRR_BR5                       ((uint32_t)0x00200000U)\n#define GPIO_BSRR_BR6                       ((uint32_t)0x00400000U)\n#define GPIO_BSRR_BR7                       ((uint32_t)0x00800000U)\n#define GPIO_BSRR_BR8                       ((uint32_t)0x01000000U)\n#define GPIO_BSRR_BR9                       ((uint32_t)0x02000000U)\n#define GPIO_BSRR_BR10                      ((uint32_t)0x04000000U)\n#define GPIO_BSRR_BR11                      ((uint32_t)0x08000000U)\n#define GPIO_BSRR_BR12                      ((uint32_t)0x10000000U)\n#define GPIO_BSRR_BR13                      ((uint32_t)0x20000000U)\n#define GPIO_BSRR_BR14                      ((uint32_t)0x40000000U)\n#define GPIO_BSRR_BR15                      ((uint32_t)0x80000000U)\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\n\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0                       0x00000001U\n#define GPIO_LCKR_LCK1                       0x00000002U\n#define GPIO_LCKR_LCK2                       0x00000004U\n#define GPIO_LCKR_LCK3                       0x00000008U\n#define GPIO_LCKR_LCK4                       0x00000010U\n#define GPIO_LCKR_LCK5                       0x00000020U\n#define GPIO_LCKR_LCK6                       0x00000040U\n#define GPIO_LCKR_LCK7                       0x00000080U\n#define GPIO_LCKR_LCK8                       0x00000100U\n#define GPIO_LCKR_LCK9                       0x00000200U\n#define GPIO_LCKR_LCK10                      0x00000400U\n#define GPIO_LCKR_LCK11                      0x00000800U\n#define GPIO_LCKR_LCK12                      0x00001000U\n#define GPIO_LCKR_LCK13                      0x00002000U\n#define GPIO_LCKR_LCK14                      0x00004000U\n#define GPIO_LCKR_LCK15                      0x00008000U\n#define GPIO_LCKR_LCKK                       0x00010000U\n\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0                    ((uint32_t)0x0000000FU)\n#define GPIO_AFRL_AFSEL0_0                  ((uint32_t)0x00000001U)\n#define GPIO_AFRL_AFSEL0_1                  ((uint32_t)0x00000002U)\n#define GPIO_AFRL_AFSEL0_2                  ((uint32_t)0x00000004U)\n#define GPIO_AFRL_AFSEL0_3                  ((uint32_t)0x00000008U)\n#define GPIO_AFRL_AFSEL1                    ((uint32_t)0x000000F0U)\n#define GPIO_AFRL_AFSEL1_0                  ((uint32_t)0x00000010U)\n#define GPIO_AFRL_AFSEL1_1                  ((uint32_t)0x00000020U)\n#define GPIO_AFRL_AFSEL1_2                  ((uint32_t)0x00000040U)\n#define GPIO_AFRL_AFSEL1_3                  ((uint32_t)0x00000080U)\n#define GPIO_AFRL_AFSEL2                    ((uint32_t)0x00000F00U)\n#define GPIO_AFRL_AFSEL2_0                  ((uint32_t)0x00000100U)\n#define GPIO_AFRL_AFSEL2_1                  ((uint32_t)0x00000200U)\n#define GPIO_AFRL_AFSEL2_2                  ((uint32_t)0x00000400U)\n#define GPIO_AFRL_AFSEL2_3                  ((uint32_t)0x00000800U)\n#define GPIO_AFRL_AFSEL3                    ((uint32_t)0x0000F000U)\n#define GPIO_AFRL_AFSEL3_0                  ((uint32_t)0x00001000U)\n#define GPIO_AFRL_AFSEL3_1                  ((uint32_t)0x00002000U)\n#define GPIO_AFRL_AFSEL3_2                  ((uint32_t)0x00004000U)\n#define GPIO_AFRL_AFSEL3_3                  ((uint32_t)0x00008000U)\n#define GPIO_AFRL_AFSEL4                    ((uint32_t)0x000F0000U)\n#define GPIO_AFRL_AFSEL4_0                  ((uint32_t)0x00010000U)\n#define GPIO_AFRL_AFSEL4_1                  ((uint32_t)0x00020000U)\n#define GPIO_AFRL_AFSEL4_2                  ((uint32_t)0x00040000U)\n#define GPIO_AFRL_AFSEL4_3                  ((uint32_t)0x00080000U)\n#define GPIO_AFRL_AFSEL5                    ((uint32_t)0x00F00000U)\n#define GPIO_AFRL_AFSEL5_0                  ((uint32_t)0x00100000U)\n#define GPIO_AFRL_AFSEL5_1                  ((uint32_t)0x00200000U)\n#define GPIO_AFRL_AFSEL5_2                  ((uint32_t)0x00400000U)\n#define GPIO_AFRL_AFSEL5_3                  ((uint32_t)0x00800000U)\n#define GPIO_AFRL_AFSEL6                    ((uint32_t)0x0F000000U)\n#define GPIO_AFRL_AFSEL6_0                  ((uint32_t)0x01000000U)\n#define GPIO_AFRL_AFSEL6_1                  ((uint32_t)0x02000000U)\n#define GPIO_AFRL_AFSEL6_2                  ((uint32_t)0x04000000U)\n#define GPIO_AFRL_AFSEL6_3                  ((uint32_t)0x08000000U)\n#define GPIO_AFRL_AFSEL7                    ((uint32_t)0xF0000000U)\n#define GPIO_AFRL_AFSEL7_0                  ((uint32_t)0x10000000U)\n#define GPIO_AFRL_AFSEL7_1                  ((uint32_t)0x20000000U)\n#define GPIO_AFRL_AFSEL7_2                  ((uint32_t)0x40000000U)\n#define GPIO_AFRL_AFSEL7_3                  ((uint32_t)0x80000000U)\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8                    ((uint32_t)0x0000000FU)\n#define GPIO_AFRH_AFSEL8_0                  ((uint32_t)0x00000001U)\n#define GPIO_AFRH_AFSEL8_1                  ((uint32_t)0x00000002U)\n#define GPIO_AFRH_AFSEL8_2                  ((uint32_t)0x00000004U)\n#define GPIO_AFRH_AFSEL8_3                  ((uint32_t)0x00000008U)\n#define GPIO_AFRH_AFSEL9                    ((uint32_t)0x000000F0U)\n#define GPIO_AFRH_AFSEL9_0                  ((uint32_t)0x00000010U)\n#define GPIO_AFRH_AFSEL9_1                  ((uint32_t)0x00000020U)\n#define GPIO_AFRH_AFSEL9_2                  ((uint32_t)0x00000040U)\n#define GPIO_AFRH_AFSEL9_3                  ((uint32_t)0x00000080U)\n#define GPIO_AFRH_AFSEL10                   ((uint32_t)0x00000F00U)\n#define GPIO_AFRH_AFSEL10_0                 ((uint32_t)0x00000100U)\n#define GPIO_AFRH_AFSEL10_1                 ((uint32_t)0x00000200U)\n#define GPIO_AFRH_AFSEL10_2                 ((uint32_t)0x00000400U)\n#define GPIO_AFRH_AFSEL10_3                 ((uint32_t)0x00000800U)\n#define GPIO_AFRH_AFSEL11                   ((uint32_t)0x0000F000U)\n#define GPIO_AFRH_AFSEL11_0                 ((uint32_t)0x00001000U)\n#define GPIO_AFRH_AFSEL11_1                 ((uint32_t)0x00002000U)\n#define GPIO_AFRH_AFSEL11_2                 ((uint32_t)0x00004000U)\n#define GPIO_AFRH_AFSEL11_3                 ((uint32_t)0x00008000U)\n#define GPIO_AFRH_AFSEL12                   ((uint32_t)0x000F0000U)\n#define GPIO_AFRH_AFSEL12_0                 ((uint32_t)0x00010000U)\n#define GPIO_AFRH_AFSEL12_1                 ((uint32_t)0x00020000U)\n#define GPIO_AFRH_AFSEL12_2                 ((uint32_t)0x00040000U)\n#define GPIO_AFRH_AFSEL12_3                 ((uint32_t)0x00080000U)\n#define GPIO_AFRH_AFSEL13                   ((uint32_t)0x00F00000U)\n#define GPIO_AFRH_AFSEL13_0                 ((uint32_t)0x00100000U)\n#define GPIO_AFRH_AFSEL13_1                 ((uint32_t)0x00200000U)\n#define GPIO_AFRH_AFSEL13_2                 ((uint32_t)0x00400000U)\n#define GPIO_AFRH_AFSEL13_3                 ((uint32_t)0x00800000U)\n#define GPIO_AFRH_AFSEL14                   ((uint32_t)0x0F000000U)\n#define GPIO_AFRH_AFSEL14_0                 ((uint32_t)0x01000000U)\n#define GPIO_AFRH_AFSEL14_1                 ((uint32_t)0x02000000U)\n#define GPIO_AFRH_AFSEL14_2                 ((uint32_t)0x04000000U)\n#define GPIO_AFRH_AFSEL14_3                 ((uint32_t)0x08000000U)\n#define GPIO_AFRH_AFSEL15                   ((uint32_t)0xF0000000U)\n#define GPIO_AFRH_AFSEL15_0                 ((uint32_t)0x10000000U)\n#define GPIO_AFRH_AFSEL15_1                 ((uint32_t)0x20000000U)\n#define GPIO_AFRH_AFSEL15_2                 ((uint32_t)0x40000000U)\n#define GPIO_AFRH_AFSEL15_3                 ((uint32_t)0x80000000U)\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0                        ((uint32_t)0x00000001U)\n#define GPIO_BRR_BR1                        ((uint32_t)0x00000002U)\n#define GPIO_BRR_BR2                        ((uint32_t)0x00000004U)\n#define GPIO_BRR_BR3                        ((uint32_t)0x00000008U)\n#define GPIO_BRR_BR4                        ((uint32_t)0x00000010U)\n#define GPIO_BRR_BR5                        ((uint32_t)0x00000020U)\n#define GPIO_BRR_BR6                        ((uint32_t)0x00000040U)\n#define GPIO_BRR_BR7                        ((uint32_t)0x00000080U)\n#define GPIO_BRR_BR8                        ((uint32_t)0x00000100U)\n#define GPIO_BRR_BR9                        ((uint32_t)0x00000200U)\n#define GPIO_BRR_BR10                       ((uint32_t)0x00000400U)\n#define GPIO_BRR_BR11                       ((uint32_t)0x00000800U)\n#define GPIO_BRR_BR12                       ((uint32_t)0x00001000U)\n#define GPIO_BRR_BR13                       ((uint32_t)0x00002000U)\n#define GPIO_BRR_BR14                       ((uint32_t)0x00004000U)\n#define GPIO_BRR_BR15                       ((uint32_t)0x00008000U)\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */\n#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */\n#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */\n#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */\n#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */\n#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */\n#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */\n#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */\n#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */\n#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */\n#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */\n#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */\n#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */\n#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */\n#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */\n#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */\n#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */\n#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */\n#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */\n\n#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */\n#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */\n#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */\n#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */\n#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */\n#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */\n\n#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */\n#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */\n#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */\n#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */\n#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */\n#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */\n#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */\n#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */\n#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */\n#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */\n\n#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */\n#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */\n#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */\n#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */\n#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */\n#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */\n#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */\n#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */\n#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */\n#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */\n#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */\n#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */\n#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */\n#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */\n#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */\n#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */\n#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */\n#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */\n#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */\n#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */\n#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */\n#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */\n#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define  IWDG_KR_KEY                         0x0000FFFFU        /*!<Key value (write only, read 0000h) */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define  IWDG_PR_PR                          0x00000007U        /*!<PR[2:0] (Prescaler divider) */\n#define  IWDG_PR_PR_0                        0x00000001U        /*!<Bit 0 */\n#define  IWDG_PR_PR_1                        0x00000002U        /*!<Bit 1 */\n#define  IWDG_PR_PR_2                        0x00000004U        /*!<Bit 2 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define  IWDG_RLR_RL                         0x00000FFFU        /*!<Watchdog counter reload value */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define  IWDG_SR_PVU                         0x00000001U        /*!<Watchdog prescaler value update */\n#define  IWDG_SR_RVU                         0x00000002U        /*!<Watchdog counter reload value update */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */\n#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */\n#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */\n#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */\n#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */\n\n#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */\n#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */\n#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */\n#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */\n\n/*!< PVD level configuration */\n#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */\n#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */\n#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */\n#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */\n#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */\n#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */\n#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */\n#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */\n\n#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */\n#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */\n#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */\n#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */\n#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */\n#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */\n#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define  RCC_CR_HSION                        0x00000001U\n#define  RCC_CR_HSIRDY                       0x00000002U\n\n#define  RCC_CR_HSITRIM                      0x000000F8U\n#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */\n#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */\n#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */\n#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */\n#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */\n\n#define  RCC_CR_HSICAL                       0x0000FF00U\n#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */\n#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */\n#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */\n#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */\n#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */\n#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */\n#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */\n#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */\n\n#define  RCC_CR_HSEON                        0x00010000U\n#define  RCC_CR_HSERDY                       0x00020000U\n#define  RCC_CR_HSEBYP                       0x00040000U\n#define  RCC_CR_CSSON                        0x00080000U\n#define  RCC_CR_PLLON                        0x01000000U\n#define  RCC_CR_PLLRDY                       0x02000000U\n#define  RCC_CR_PLLI2SON                     0x04000000U\n#define  RCC_CR_PLLI2SRDY                    0x08000000U\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define  RCC_PLLCFGR_PLLM                    0x0000003FU\n#define  RCC_PLLCFGR_PLLM_0                  0x00000001U\n#define  RCC_PLLCFGR_PLLM_1                  0x00000002U\n#define  RCC_PLLCFGR_PLLM_2                  0x00000004U\n#define  RCC_PLLCFGR_PLLM_3                  0x00000008U\n#define  RCC_PLLCFGR_PLLM_4                  0x00000010U\n#define  RCC_PLLCFGR_PLLM_5                  0x00000020U\n\n#define  RCC_PLLCFGR_PLLN                     0x00007FC0U\n#define  RCC_PLLCFGR_PLLN_0                   0x00000040U\n#define  RCC_PLLCFGR_PLLN_1                   0x00000080U\n#define  RCC_PLLCFGR_PLLN_2                   0x00000100U\n#define  RCC_PLLCFGR_PLLN_3                   0x00000200U\n#define  RCC_PLLCFGR_PLLN_4                   0x00000400U\n#define  RCC_PLLCFGR_PLLN_5                   0x00000800U\n#define  RCC_PLLCFGR_PLLN_6                   0x00001000U\n#define  RCC_PLLCFGR_PLLN_7                   0x00002000U\n#define  RCC_PLLCFGR_PLLN_8                   0x00004000U\n\n#define  RCC_PLLCFGR_PLLP                    0x00030000U\n#define  RCC_PLLCFGR_PLLP_0                  0x00010000U\n#define  RCC_PLLCFGR_PLLP_1                  0x00020000U\n\n#define  RCC_PLLCFGR_PLLSRC                  0x00400000U\n#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U\n#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U\n\n#define  RCC_PLLCFGR_PLLQ                    0x0F000000U\n#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U\n#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U\n#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U\n#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */\n#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */\n#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */\n\n#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */\n#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */\n#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */\n#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */\n\n#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */\n#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */\n#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */\n\n/*!< HPRE configuration */\n#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */\n#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */\n#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */\n#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */\n#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */\n\n#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */\n#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */\n#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */\n#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */\n#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */\n#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */\n#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */\n#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */\n#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */\n#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */\n#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */\n\n#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */\n#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */\n#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */\n#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */\n#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */\n#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */\n#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */\n\n#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */\n#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */\n#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */\n#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */\n#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define  RCC_CFGR_RTCPRE                     0x001F0000U\n#define  RCC_CFGR_RTCPRE_0                   0x00010000U\n#define  RCC_CFGR_RTCPRE_1                   0x00020000U\n#define  RCC_CFGR_RTCPRE_2                   0x00040000U\n#define  RCC_CFGR_RTCPRE_3                   0x00080000U\n#define  RCC_CFGR_RTCPRE_4                   0x00100000U\n\n/*!< MCO1 configuration */\n#define  RCC_CFGR_MCO1                       0x00600000U\n#define  RCC_CFGR_MCO1_0                     0x00200000U\n#define  RCC_CFGR_MCO1_1                     0x00400000U\n\n#define  RCC_CFGR_I2SSRC                     0x00800000U\n\n#define  RCC_CFGR_MCO1PRE                    0x07000000U\n#define  RCC_CFGR_MCO1PRE_0                  0x01000000U\n#define  RCC_CFGR_MCO1PRE_1                  0x02000000U\n#define  RCC_CFGR_MCO1PRE_2                  0x04000000U\n\n#define  RCC_CFGR_MCO2PRE                    0x38000000U\n#define  RCC_CFGR_MCO2PRE_0                  0x08000000U\n#define  RCC_CFGR_MCO2PRE_1                  0x10000000U\n#define  RCC_CFGR_MCO2PRE_2                  0x20000000U\n\n#define  RCC_CFGR_MCO2                       0xC0000000U\n#define  RCC_CFGR_MCO2_0                     0x40000000U\n#define  RCC_CFGR_MCO2_1                     0x80000000U\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define  RCC_CIR_LSIRDYF                     0x00000001U\n#define  RCC_CIR_LSERDYF                     0x00000002U\n#define  RCC_CIR_HSIRDYF                     0x00000004U\n#define  RCC_CIR_HSERDYF                     0x00000008U\n#define  RCC_CIR_PLLRDYF                     0x00000010U\n#define  RCC_CIR_PLLI2SRDYF                  0x00000020U\n\n#define  RCC_CIR_CSSF                        0x00000080U\n#define  RCC_CIR_LSIRDYIE                    0x00000100U\n#define  RCC_CIR_LSERDYIE                    0x00000200U\n#define  RCC_CIR_HSIRDYIE                    0x00000400U\n#define  RCC_CIR_HSERDYIE                    0x00000800U\n#define  RCC_CIR_PLLRDYIE                    0x00001000U\n#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U\n\n#define  RCC_CIR_LSIRDYC                     0x00010000U\n#define  RCC_CIR_LSERDYC                     0x00020000U\n#define  RCC_CIR_HSIRDYC                     0x00040000U\n#define  RCC_CIR_HSERDYC                     0x00080000U\n#define  RCC_CIR_PLLRDYC                     0x00100000U\n#define  RCC_CIR_PLLI2SRDYC                  0x00200000U\n\n#define  RCC_CIR_CSSC                        0x00800000U\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define  RCC_AHB1RSTR_GPIOARST               0x00000001U\n#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U\n#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U\n#define  RCC_AHB1RSTR_GPIODRST               0x00000008U\n#define  RCC_AHB1RSTR_GPIOERST               0x00000010U\n#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U\n#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U\n#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U\n#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U\n#define  RCC_AHB1RSTR_CRCRST                 0x00001000U\n#define  RCC_AHB1RSTR_DMA1RST                0x00200000U\n#define  RCC_AHB1RSTR_DMA2RST                0x00400000U\n#define  RCC_AHB1RSTR_OTGHRST                0x20000000U\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define  RCC_AHB2RSTR_RNGRST                 0x00000040U\n#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U\n\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n\n#define  RCC_AHB3RSTR_FSMCRST                0x00000001U\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define  RCC_APB1RSTR_TIM2RST                0x00000001U\n#define  RCC_APB1RSTR_TIM3RST                0x00000002U\n#define  RCC_APB1RSTR_TIM4RST                0x00000004U\n#define  RCC_APB1RSTR_TIM5RST                0x00000008U\n#define  RCC_APB1RSTR_TIM6RST                0x00000010U\n#define  RCC_APB1RSTR_TIM7RST                0x00000020U\n#define  RCC_APB1RSTR_TIM12RST               0x00000040U\n#define  RCC_APB1RSTR_TIM13RST               0x00000080U\n#define  RCC_APB1RSTR_TIM14RST               0x00000100U\n#define  RCC_APB1RSTR_WWDGRST                0x00000800U\n#define  RCC_APB1RSTR_SPI2RST                0x00004000U\n#define  RCC_APB1RSTR_SPI3RST                0x00008000U\n#define  RCC_APB1RSTR_USART2RST              0x00020000U\n#define  RCC_APB1RSTR_USART3RST              0x00040000U\n#define  RCC_APB1RSTR_UART4RST               0x00080000U\n#define  RCC_APB1RSTR_UART5RST               0x00100000U\n#define  RCC_APB1RSTR_I2C1RST                0x00200000U\n#define  RCC_APB1RSTR_I2C2RST                0x00400000U\n#define  RCC_APB1RSTR_I2C3RST                0x00800000U\n#define  RCC_APB1RSTR_CAN1RST                0x02000000U\n#define  RCC_APB1RSTR_CAN2RST                0x04000000U\n#define  RCC_APB1RSTR_PWRRST                 0x10000000U\n#define  RCC_APB1RSTR_DACRST                 0x20000000U\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define  RCC_APB2RSTR_TIM1RST                0x00000001U\n#define  RCC_APB2RSTR_TIM8RST                0x00000002U\n#define  RCC_APB2RSTR_USART1RST              0x00000010U\n#define  RCC_APB2RSTR_USART6RST              0x00000020U\n#define  RCC_APB2RSTR_ADCRST                 0x00000100U\n#define  RCC_APB2RSTR_SDIORST                0x00000800U\n#define  RCC_APB2RSTR_SPI1RST                0x00001000U\n#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U\n#define  RCC_APB2RSTR_TIM9RST                0x00010000U\n#define  RCC_APB2RSTR_TIM10RST               0x00020000U\n#define  RCC_APB2RSTR_TIM11RST               0x00040000U\n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U\n#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U\n#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U\n#define  RCC_AHB1ENR_GPIODEN                 0x00000008U\n#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U\n#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U\n#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U\n#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U\n#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U\n#define  RCC_AHB1ENR_CRCEN                   0x00001000U\n#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U\n#define  RCC_AHB1ENR_DMA1EN                  0x00200000U\n#define  RCC_AHB1ENR_DMA2EN                  0x00400000U\n\n#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U\n#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U\n\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n#define  RCC_AHB2ENR_RNGEN                   0x00000040U\n#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n\n#define  RCC_AHB3ENR_FSMCEN                  0x00000001U\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define  RCC_APB1ENR_TIM2EN                  0x00000001U\n#define  RCC_APB1ENR_TIM3EN                  0x00000002U\n#define  RCC_APB1ENR_TIM4EN                  0x00000004U\n#define  RCC_APB1ENR_TIM5EN                  0x00000008U\n#define  RCC_APB1ENR_TIM6EN                  0x00000010U\n#define  RCC_APB1ENR_TIM7EN                  0x00000020U\n#define  RCC_APB1ENR_TIM12EN                 0x00000040U\n#define  RCC_APB1ENR_TIM13EN                 0x00000080U\n#define  RCC_APB1ENR_TIM14EN                 0x00000100U\n#define  RCC_APB1ENR_WWDGEN                  0x00000800U\n#define  RCC_APB1ENR_SPI2EN                  0x00004000U\n#define  RCC_APB1ENR_SPI3EN                  0x00008000U\n#define  RCC_APB1ENR_USART2EN                0x00020000U\n#define  RCC_APB1ENR_USART3EN                0x00040000U\n#define  RCC_APB1ENR_UART4EN                 0x00080000U\n#define  RCC_APB1ENR_UART5EN                 0x00100000U\n#define  RCC_APB1ENR_I2C1EN                  0x00200000U\n#define  RCC_APB1ENR_I2C2EN                  0x00400000U\n#define  RCC_APB1ENR_I2C3EN                  0x00800000U\n#define  RCC_APB1ENR_CAN1EN                  0x02000000U\n#define  RCC_APB1ENR_CAN2EN                  0x04000000U\n#define  RCC_APB1ENR_PWREN                   0x10000000U\n#define  RCC_APB1ENR_DACEN                   0x20000000U\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define  RCC_APB2ENR_TIM1EN                  0x00000001U\n#define  RCC_APB2ENR_TIM8EN                  0x00000002U\n#define  RCC_APB2ENR_USART1EN                0x00000010U\n#define  RCC_APB2ENR_USART6EN                0x00000020U\n#define  RCC_APB2ENR_ADC1EN                  0x00000100U\n#define  RCC_APB2ENR_ADC2EN                  0x00000200U\n#define  RCC_APB2ENR_ADC3EN                  0x00000400U\n#define  RCC_APB2ENR_SDIOEN                  0x00000800U\n#define  RCC_APB2ENR_SPI1EN                  0x00001000U\n#define  RCC_APB2ENR_SYSCFGEN                0x00004000U\n#define  RCC_APB2ENR_TIM9EN                  0x00010000U\n#define  RCC_APB2ENR_TIM10EN                 0x00020000U\n#define  RCC_APB2ENR_TIM11EN                 0x00040000U\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U\n#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U\n#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U\n#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U\n#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U\n#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U\n#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U\n#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U\n#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U\n#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U\n#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U\n#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U\n#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U\n#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U\n#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U\n#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U\n#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U\n#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U\n#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n\n#define  RCC_AHB3LPENR_FSMCLPEN              0x00000001U\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U\n#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U\n#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U\n#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U\n#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U\n#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U\n#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U\n#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U\n#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U\n#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U\n#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U\n#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U\n#define  RCC_APB1LPENR_USART2LPEN            0x00020000U\n#define  RCC_APB1LPENR_USART3LPEN            0x00040000U\n#define  RCC_APB1LPENR_UART4LPEN             0x00080000U\n#define  RCC_APB1LPENR_UART5LPEN             0x00100000U\n#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U\n#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U\n#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U\n#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U\n#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U\n#define  RCC_APB1LPENR_PWRLPEN               0x10000000U\n#define  RCC_APB1LPENR_DACLPEN               0x20000000U\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U\n#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U\n#define  RCC_APB2LPENR_USART1LPEN            0x00000010U\n#define  RCC_APB2LPENR_USART6LPEN            0x00000020U\n#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U\n#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U\n#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U\n#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U\n#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U\n#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U\n#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U\n#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U\n#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define  RCC_BDCR_LSEON                      0x00000001U\n#define  RCC_BDCR_LSERDY                     0x00000002U\n#define  RCC_BDCR_LSEBYP                     0x00000004U\n\n#define  RCC_BDCR_RTCSEL                    0x00000300U\n#define  RCC_BDCR_RTCSEL_0                  0x00000100U\n#define  RCC_BDCR_RTCSEL_1                  0x00000200U\n\n#define  RCC_BDCR_RTCEN                      0x00008000U\n#define  RCC_BDCR_BDRST                      0x00010000U\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define  RCC_CSR_LSION                       0x00000001U\n#define  RCC_CSR_LSIRDY                      0x00000002U\n#define  RCC_CSR_RMVF                        0x01000000U\n#define  RCC_CSR_BORRSTF                     0x02000000U\n#define  RCC_CSR_PADRSTF                     0x04000000U\n#define  RCC_CSR_PORRSTF                     0x08000000U\n#define  RCC_CSR_SFTRSTF                     0x10000000U\n#define  RCC_CSR_WDGRSTF                     0x20000000U\n#define  RCC_CSR_WWDGRSTF                    0x40000000U\n#define  RCC_CSR_LPWRRSTF                    0x80000000U\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define  RCC_SSCGR_MODPER                    0x00001FFFU\n#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U\n#define  RCC_SSCGR_SPREADSEL                 0x40000000U\n#define  RCC_SSCGR_SSCGEN                    0x80000000U\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U\n#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U\n#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U\n#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U\n#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U\n#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U\n#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U\n#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U\n#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U\n#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U\n\n#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U\n#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U\n#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U\n#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN                         0x00000004U\n#define RNG_CR_IE                            0x00000008U\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY                          0x00000001U\n#define RNG_SR_CECS                          0x00000002U\n#define RNG_SR_SECS                          0x00000004U\n#define RNG_SR_CEIS                          0x00000020U\n#define RNG_SR_SEIS                          0x00000040U\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM                            0x00400000U\n#define RTC_TR_HT                            0x00300000U\n#define RTC_TR_HT_0                          0x00100000U\n#define RTC_TR_HT_1                          0x00200000U\n#define RTC_TR_HU                            0x000F0000U\n#define RTC_TR_HU_0                          0x00010000U\n#define RTC_TR_HU_1                          0x00020000U\n#define RTC_TR_HU_2                          0x00040000U\n#define RTC_TR_HU_3                          0x00080000U\n#define RTC_TR_MNT                           0x00007000U\n#define RTC_TR_MNT_0                         0x00001000U\n#define RTC_TR_MNT_1                         0x00002000U\n#define RTC_TR_MNT_2                         0x00004000U\n#define RTC_TR_MNU                           0x00000F00U\n#define RTC_TR_MNU_0                         0x00000100U\n#define RTC_TR_MNU_1                         0x00000200U\n#define RTC_TR_MNU_2                         0x00000400U\n#define RTC_TR_MNU_3                         0x00000800U\n#define RTC_TR_ST                            0x00000070U\n#define RTC_TR_ST_0                          0x00000010U\n#define RTC_TR_ST_1                          0x00000020U\n#define RTC_TR_ST_2                          0x00000040U\n#define RTC_TR_SU                            0x0000000FU\n#define RTC_TR_SU_0                          0x00000001U\n#define RTC_TR_SU_1                          0x00000002U\n#define RTC_TR_SU_2                          0x00000004U\n#define RTC_TR_SU_3                          0x00000008U\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT                            0x00F00000U\n#define RTC_DR_YT_0                          0x00100000U\n#define RTC_DR_YT_1                          0x00200000U\n#define RTC_DR_YT_2                          0x00400000U\n#define RTC_DR_YT_3                          0x00800000U\n#define RTC_DR_YU                            0x000F0000U\n#define RTC_DR_YU_0                          0x00010000U\n#define RTC_DR_YU_1                          0x00020000U\n#define RTC_DR_YU_2                          0x00040000U\n#define RTC_DR_YU_3                          0x00080000U\n#define RTC_DR_WDU                           0x0000E000U\n#define RTC_DR_WDU_0                         0x00002000U\n#define RTC_DR_WDU_1                         0x00004000U\n#define RTC_DR_WDU_2                         0x00008000U\n#define RTC_DR_MT                            0x00001000U\n#define RTC_DR_MU                            0x00000F00U\n#define RTC_DR_MU_0                          0x00000100U\n#define RTC_DR_MU_1                          0x00000200U\n#define RTC_DR_MU_2                          0x00000400U\n#define RTC_DR_MU_3                          0x00000800U\n#define RTC_DR_DT                            0x00000030U\n#define RTC_DR_DT_0                          0x00000010U\n#define RTC_DR_DT_1                          0x00000020U\n#define RTC_DR_DU                            0x0000000FU\n#define RTC_DR_DU_0                          0x00000001U\n#define RTC_DR_DU_1                          0x00000002U\n#define RTC_DR_DU_2                          0x00000004U\n#define RTC_DR_DU_3                          0x00000008U\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE                           0x00800000U\n#define RTC_CR_OSEL                          0x00600000U\n#define RTC_CR_OSEL_0                        0x00200000U\n#define RTC_CR_OSEL_1                        0x00400000U\n#define RTC_CR_POL                           0x00100000U\n#define RTC_CR_BCK                           0x00040000U\n#define RTC_CR_SUB1H                         0x00020000U\n#define RTC_CR_ADD1H                         0x00010000U\n#define RTC_CR_TSIE                          0x00008000U\n#define RTC_CR_WUTIE                         0x00004000U\n#define RTC_CR_ALRBIE                        0x00002000U\n#define RTC_CR_ALRAIE                        0x00001000U\n#define RTC_CR_TSE                           0x00000800U\n#define RTC_CR_WUTE                          0x00000400U\n#define RTC_CR_ALRBE                         0x00000200U\n#define RTC_CR_ALRAE                         0x00000100U\n#define RTC_CR_DCE                           0x00000080U\n#define RTC_CR_FMT                           0x00000040U\n#define RTC_CR_REFCKON                       0x00000010U\n#define RTC_CR_TSEDGE                        0x00000008U\n#define RTC_CR_WUCKSEL                       0x00000007U\n#define RTC_CR_WUCKSEL_0                     0x00000001U\n#define RTC_CR_WUCKSEL_1                     0x00000002U\n#define RTC_CR_WUCKSEL_2                     0x00000004U\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_TAMP1F                       0x00002000U\n#define RTC_ISR_TSOVF                        0x00001000U\n#define RTC_ISR_TSF                          0x00000800U\n#define RTC_ISR_WUTF                         0x00000400U\n#define RTC_ISR_ALRBF                        0x00000200U\n#define RTC_ISR_ALRAF                        0x00000100U\n#define RTC_ISR_INIT                         0x00000080U\n#define RTC_ISR_INITF                        0x00000040U\n#define RTC_ISR_RSF                          0x00000020U\n#define RTC_ISR_INITS                        0x00000010U\n#define RTC_ISR_WUTWF                        0x00000004U\n#define RTC_ISR_ALRBWF                       0x00000002U\n#define RTC_ISR_ALRAWF                       0x00000001U\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A                    0x007F0000U\n#define RTC_PRER_PREDIV_S                    0x00001FFFU\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT                         0x0000FFFFU\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS                       0x00000080U\n#define RTC_CALIBR_DC                        0x0000001FU\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4                      0x80000000U\n#define RTC_ALRMAR_WDSEL                     0x40000000U\n#define RTC_ALRMAR_DT                        0x30000000U\n#define RTC_ALRMAR_DT_0                      0x10000000U\n#define RTC_ALRMAR_DT_1                      0x20000000U\n#define RTC_ALRMAR_DU                        0x0F000000U\n#define RTC_ALRMAR_DU_0                      0x01000000U\n#define RTC_ALRMAR_DU_1                      0x02000000U\n#define RTC_ALRMAR_DU_2                      0x04000000U\n#define RTC_ALRMAR_DU_3                      0x08000000U\n#define RTC_ALRMAR_MSK3                      0x00800000U\n#define RTC_ALRMAR_PM                        0x00400000U\n#define RTC_ALRMAR_HT                        0x00300000U\n#define RTC_ALRMAR_HT_0                      0x00100000U\n#define RTC_ALRMAR_HT_1                      0x00200000U\n#define RTC_ALRMAR_HU                        0x000F0000U\n#define RTC_ALRMAR_HU_0                      0x00010000U\n#define RTC_ALRMAR_HU_1                      0x00020000U\n#define RTC_ALRMAR_HU_2                      0x00040000U\n#define RTC_ALRMAR_HU_3                      0x00080000U\n#define RTC_ALRMAR_MSK2                      0x00008000U\n#define RTC_ALRMAR_MNT                       0x00007000U\n#define RTC_ALRMAR_MNT_0                     0x00001000U\n#define RTC_ALRMAR_MNT_1                     0x00002000U\n#define RTC_ALRMAR_MNT_2                     0x00004000U\n#define RTC_ALRMAR_MNU                       0x00000F00U\n#define RTC_ALRMAR_MNU_0                     0x00000100U\n#define RTC_ALRMAR_MNU_1                     0x00000200U\n#define RTC_ALRMAR_MNU_2                     0x00000400U\n#define RTC_ALRMAR_MNU_3                     0x00000800U\n#define RTC_ALRMAR_MSK1                      0x00000080U\n#define RTC_ALRMAR_ST                        0x00000070U\n#define RTC_ALRMAR_ST_0                      0x00000010U\n#define RTC_ALRMAR_ST_1                      0x00000020U\n#define RTC_ALRMAR_ST_2                      0x00000040U\n#define RTC_ALRMAR_SU                        0x0000000FU\n#define RTC_ALRMAR_SU_0                      0x00000001U\n#define RTC_ALRMAR_SU_1                      0x00000002U\n#define RTC_ALRMAR_SU_2                      0x00000004U\n#define RTC_ALRMAR_SU_3                      0x00000008U\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4                      0x80000000U\n#define RTC_ALRMBR_WDSEL                     0x40000000U\n#define RTC_ALRMBR_DT                        0x30000000U\n#define RTC_ALRMBR_DT_0                      0x10000000U\n#define RTC_ALRMBR_DT_1                      0x20000000U\n#define RTC_ALRMBR_DU                        0x0F000000U\n#define RTC_ALRMBR_DU_0                      0x01000000U\n#define RTC_ALRMBR_DU_1                      0x02000000U\n#define RTC_ALRMBR_DU_2                      0x04000000U\n#define RTC_ALRMBR_DU_3                      0x08000000U\n#define RTC_ALRMBR_MSK3                      0x00800000U\n#define RTC_ALRMBR_PM                        0x00400000U\n#define RTC_ALRMBR_HT                        0x00300000U\n#define RTC_ALRMBR_HT_0                      0x00100000U\n#define RTC_ALRMBR_HT_1                      0x00200000U\n#define RTC_ALRMBR_HU                        0x000F0000U\n#define RTC_ALRMBR_HU_0                      0x00010000U\n#define RTC_ALRMBR_HU_1                      0x00020000U\n#define RTC_ALRMBR_HU_2                      0x00040000U\n#define RTC_ALRMBR_HU_3                      0x00080000U\n#define RTC_ALRMBR_MSK2                      0x00008000U\n#define RTC_ALRMBR_MNT                       0x00007000U\n#define RTC_ALRMBR_MNT_0                     0x00001000U\n#define RTC_ALRMBR_MNT_1                     0x00002000U\n#define RTC_ALRMBR_MNT_2                     0x00004000U\n#define RTC_ALRMBR_MNU                       0x00000F00U\n#define RTC_ALRMBR_MNU_0                     0x00000100U\n#define RTC_ALRMBR_MNU_1                     0x00000200U\n#define RTC_ALRMBR_MNU_2                     0x00000400U\n#define RTC_ALRMBR_MNU_3                     0x00000800U\n#define RTC_ALRMBR_MSK1                      0x00000080U\n#define RTC_ALRMBR_ST                        0x00000070U\n#define RTC_ALRMBR_ST_0                      0x00000010U\n#define RTC_ALRMBR_ST_1                      0x00000020U\n#define RTC_ALRMBR_ST_2                      0x00000040U\n#define RTC_ALRMBR_SU                        0x0000000FU\n#define RTC_ALRMBR_SU_0                      0x00000001U\n#define RTC_ALRMBR_SU_1                      0x00000002U\n#define RTC_ALRMBR_SU_2                      0x00000004U\n#define RTC_ALRMBR_SU_3                      0x00000008U\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY                          0x000000FFU\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM                          0x00400000U\n#define RTC_TSTR_HT                          0x00300000U\n#define RTC_TSTR_HT_0                        0x00100000U\n#define RTC_TSTR_HT_1                        0x00200000U\n#define RTC_TSTR_HU                          0x000F0000U\n#define RTC_TSTR_HU_0                        0x00010000U\n#define RTC_TSTR_HU_1                        0x00020000U\n#define RTC_TSTR_HU_2                        0x00040000U\n#define RTC_TSTR_HU_3                        0x00080000U\n#define RTC_TSTR_MNT                         0x00007000U\n#define RTC_TSTR_MNT_0                       0x00001000U\n#define RTC_TSTR_MNT_1                       0x00002000U\n#define RTC_TSTR_MNT_2                       0x00004000U\n#define RTC_TSTR_MNU                         0x00000F00U\n#define RTC_TSTR_MNU_0                       0x00000100U\n#define RTC_TSTR_MNU_1                       0x00000200U\n#define RTC_TSTR_MNU_2                       0x00000400U\n#define RTC_TSTR_MNU_3                       0x00000800U\n#define RTC_TSTR_ST                          0x00000070U\n#define RTC_TSTR_ST_0                        0x00000010U\n#define RTC_TSTR_ST_1                        0x00000020U\n#define RTC_TSTR_ST_2                        0x00000040U\n#define RTC_TSTR_SU                          0x0000000FU\n#define RTC_TSTR_SU_0                        0x00000001U\n#define RTC_TSTR_SU_1                        0x00000002U\n#define RTC_TSTR_SU_2                        0x00000004U\n#define RTC_TSTR_SU_3                        0x00000008U\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU                         0x0000E000U\n#define RTC_TSDR_WDU_0                       0x00002000U\n#define RTC_TSDR_WDU_1                       0x00004000U\n#define RTC_TSDR_WDU_2                       0x00008000U\n#define RTC_TSDR_MT                          0x00001000U\n#define RTC_TSDR_MU                          0x00000F00U\n#define RTC_TSDR_MU_0                        0x00000100U\n#define RTC_TSDR_MU_1                        0x00000200U\n#define RTC_TSDR_MU_2                        0x00000400U\n#define RTC_TSDR_MU_3                        0x00000800U\n#define RTC_TSDR_DT                          0x00000030U\n#define RTC_TSDR_DT_0                        0x00000010U\n#define RTC_TSDR_DT_1                        0x00000020U\n#define RTC_TSDR_DU                          0x0000000FU\n#define RTC_TSDR_DU_0                        0x00000001U\n#define RTC_TSDR_DU_1                        0x00000002U\n#define RTC_TSDR_DU_2                        0x00000004U\n#define RTC_TSDR_DU_3                        0x00000008U\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U\n#define RTC_TAFCR_TSINSEL                    0x00020000U\n#define RTC_TAFCR_TAMPINSEL                  0x00010000U\n#define RTC_TAFCR_TAMPIE                     0x00000004U\n#define RTC_TAFCR_TAMP1TRG                   0x00000002U\n#define RTC_TAFCR_TAMP1E                     0x00000001U\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R                            0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R                           0xFFFFFFFFU\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R                           0xFFFFFFFFU\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define  SDIO_POWER_PWRCTRL                  0x00000003U        /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define  SDIO_POWER_PWRCTRL_0                0x00000001U        /*!<Bit 0 */\n#define  SDIO_POWER_PWRCTRL_1                0x00000002U        /*!<Bit 1 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define  SDIO_CLKCR_CLKDIV                   0x000000FFU        /*!<Clock divide factor */\n#define  SDIO_CLKCR_CLKEN                    0x00000100U        /*!<Clock enable bit */\n#define  SDIO_CLKCR_PWRSAV                   0x00000200U        /*!<Power saving configuration bit */\n#define  SDIO_CLKCR_BYPASS                   0x00000400U        /*!<Clock divider bypass enable bit */\n\n#define  SDIO_CLKCR_WIDBUS                   0x00001800U        /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define  SDIO_CLKCR_WIDBUS_0                 0x00000800U        /*!<Bit 0 */\n#define  SDIO_CLKCR_WIDBUS_1                 0x00001000U        /*!<Bit 1 */\n\n#define  SDIO_CLKCR_NEGEDGE                  0x00002000U        /*!<SDIO_CK dephasing selection bit */\n#define  SDIO_CLKCR_HWFC_EN                  0x00004000U        /*!<HW Flow Control enable */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define  SDIO_CMD_CMDINDEX                   0x0000003FU        /*!<Command Index */\n\n#define  SDIO_CMD_WAITRESP                   0x000000C0U        /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define  SDIO_CMD_WAITRESP_0                 0x00000040U        /*!< Bit 0 */\n#define  SDIO_CMD_WAITRESP_1                 0x00000080U        /*!< Bit 1 */\n\n#define  SDIO_CMD_WAITINT                    0x00000100U        /*!<CPSM Waits for Interrupt Request */\n#define  SDIO_CMD_WAITPEND                   0x00000200U        /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define  SDIO_CMD_CPSMEN                     0x00000400U        /*!<Command path state machine (CPSM) Enable bit */\n#define  SDIO_CMD_SDIOSUSPEND                0x00000800U        /*!<SD I/O suspend command */\n#define  SDIO_CMD_ENCMDCOMPL                 0x00001000U        /*!<Enable CMD completion */\n#define  SDIO_CMD_NIEN                       0x00002000U        /*!<Not Interrupt Enable */\n#define  SDIO_CMD_CEATACMD                   0x00004000U        /*!<CE-ATA command */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define  SDIO_RESPCMD_RESPCMD                0x0000003FU        /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define  SDIO_DCTRL_DTEN                     0x00000001U        /*!<Data transfer enabled bit */\n#define  SDIO_DCTRL_DTDIR                    0x00000002U        /*!<Data transfer direction selection */\n#define  SDIO_DCTRL_DTMODE                   0x00000004U        /*!<Data transfer mode selection */\n#define  SDIO_DCTRL_DMAEN                    0x00000008U        /*!<DMA enabled bit */\n\n#define  SDIO_DCTRL_DBLOCKSIZE               0x000000F0U        /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define  SDIO_DCTRL_DBLOCKSIZE_0             0x00000010U        /*!<Bit 0 */\n#define  SDIO_DCTRL_DBLOCKSIZE_1             0x00000020U        /*!<Bit 1 */\n#define  SDIO_DCTRL_DBLOCKSIZE_2             0x00000040U        /*!<Bit 2 */\n#define  SDIO_DCTRL_DBLOCKSIZE_3             0x00000080U        /*!<Bit 3 */\n\n#define  SDIO_DCTRL_RWSTART                  0x00000100U        /*!<Read wait start */\n#define  SDIO_DCTRL_RWSTOP                   0x00000200U        /*!<Read wait stop */\n#define  SDIO_DCTRL_RWMOD                    0x00000400U        /*!<Read wait mode */\n#define  SDIO_DCTRL_SDIOEN                   0x00000800U        /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */\n#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */\n#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */\n#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */\n#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */\n#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */\n#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */\n#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */\n#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */\n#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */\n#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */\n#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */\n#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */\n#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */\n#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */\n#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */\n#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */\n#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */\n#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */\n#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */\n#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */\n#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */\n#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */\n#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */\n#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */\n#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */\n#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */\n#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */\n#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */\n#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */\n#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */\n#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */\n#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */\n#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */\n#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */\n#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */\n#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */\n#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */\n#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */\n#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */\n#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */\n#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */\n#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */\n#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */\n#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */\n#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */\n#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */\n#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */\n#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */\n#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */\n#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */\n#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */\n#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */\n#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */\n#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */\n#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */\n\n#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */\n#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */\n#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */\n#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */\n\n#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */\n#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */\n#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */\n#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */\n#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */\n#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */\n#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */\n#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */\n#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */\n#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */\n#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */\n#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */\n#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */\n#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */\n#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */\n#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */\n#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */\n#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */\n#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */\n#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */\n#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */\n#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */\n#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */\n#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */\n\n#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */\n#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */\n\n#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */\n\n#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */\n#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */\n\n#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */\n\n#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */\n#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */\n\n#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */\n#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */\n#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */\n#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE          0x00000003U /*!<SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U\n#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0            0x0000000FU /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1            0x000000F0U /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2            0x00000F00U /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3            0x0000F000U /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA         0x00000000U /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB         0x00000001U /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC         0x00000002U /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD         0x00000003U /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE         0x00000004U /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF         0x00000005U /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG         0x00000006U /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH         0x00000007U /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI         0x00000008U /*!<PI[0] pin */\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA         0x00000000U /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB         0x00000010U /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC         0x00000020U /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD         0x00000030U /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE         0x00000040U /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF         0x00000050) /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG         0x00000060U /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH         0x00000070U /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI         0x00000080U /*!<PI[1] pin */\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA         0x00000000U /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB         0x00000100U /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC         0x00000200U /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD         0x00000300U /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE         0x00000400U /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF         0x00000500) /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG         0x00000600) /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH         0x00000700U /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI         0x00000800U /*!<PI[2] pin */\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA         0x00000000U /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB         0x00001000U /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC         0x00002000U /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD         0x00003000U /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE         0x00004000U /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF         0x00005000) /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG         0x00006000U /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH         0x00007000U /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI         0x00008000U /*!<PI[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4            0x0000000FU /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5            0x000000F0U /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6            0x00000F00U /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7            0x0000F000U /*!<EXTI 7 configuration */\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA         0x00000000U /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB         0x00000001U /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC         0x00000002U /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD         0x00000003U /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE         0x00000004U /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF         0x00000005U /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG         0x00000006U /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH         0x00000007U /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI         0x00000008U /*!<PI[4] pin */\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA         0x00000000U /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB         0x00000010U /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC         0x00000020U /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD         0x00000030U /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE         0x00000040U /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF         0x00000050) /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG         0x00000060U /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH         0x00000070U /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI         0x00000080U /*!<PI[5] pin */\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA         0x00000000U /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB         0x00000100U /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC         0x00000200U /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD         0x00000300U /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE         0x00000400U /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF         0x00000500) /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG         0x00000600) /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH         0x00000700U /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI         0x00000800U /*!<PI[6] pin */\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA         0x00000000U /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB         0x00001000U /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC         0x00002000U /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD         0x00003000U /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE         0x00004000U /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF         0x00005000) /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG         0x00006000U /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH         0x00007000U /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI         0x00008000U /*!<PI[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8            0x0000000FU /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9            0x000000F0U /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10           0x00000F00U /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11           0x0000F000U /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA         0x00000000U /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB         0x00000001U /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC         0x00000002U /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD         0x00000003U /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE         0x00000004U /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF         0x00000005U /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG         0x00000006U /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH         0x00000007U /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI         0x00000008U /*!<PI[8] pin */\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA         0x00000000U /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB         0x00000010U /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC         0x00000020U /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD         0x00000030U /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE         0x00000040U /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF         0x00000050) /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG         0x00000060U /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH         0x00000070U /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI         0x00000080U /*!<PI[9] pin */\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA        0x00000000U /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB        0x00000100U /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC        0x00000200U /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD        0x00000300U /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE        0x00000400U /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF        0x00000500) /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG        0x00000600) /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH        0x00000700U /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI        0x00000800U /*!<PI[10] pin */\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA        0x00000000U /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB        0x00001000U /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC        0x00002000U /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD        0x00003000U /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE        0x00004000U /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF        0x00005000) /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG        0x00006000U /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH        0x00007000U /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI        0x00008000U /*!<PI[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12           0x0000000FU /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13           0x000000F0U /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14           0x00000F00U /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15           0x0000F000U /*!<EXTI 15 configuration */\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA        0x00000000U /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB        0x00000001U /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC        0x00000002U /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD        0x00000003U /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE        0x00000004U /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF        0x00000005U /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG        0x00000006U /*!<PG[12] pin */\n#define SYSCFG_EXTICR3_EXTI12_PH        0x00000007U /*!<PH[12] pin */\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA        0x00000000U /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB        0x00000010U /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC        0x00000020U /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD        0x00000030U /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE        0x00000040U /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF        0x00000050) /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG        0x00000060U /*!<PG[13] pin */\n#define SYSCFG_EXTICR3_EXTI13_PH        0x00000070U /*!<PH[13] pin */\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA        0x00000000U /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB        0x00000100U /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC        0x00000200U /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD        0x00000300U /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE        0x00000400U /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF        0x00000500) /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG        0x00000600) /*!<PG[14] pin */\n#define SYSCFG_EXTICR3_EXTI14_PH        0x00000700U /*!<PH[14] pin */\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA        0x00000000U /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB        0x00001000U /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC        0x00002000U /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD        0x00003000U /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE        0x00004000U /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF        0x00005000) /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG        0x00006000U /*!<PG[15] pin */\n#define SYSCFG_EXTICR3_EXTI15_PH        0x00007000U /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define  TIM_CR1_CEN                         0x00000001U            /*!<Counter enable */\n#define  TIM_CR1_UDIS                        0x00000002U            /*!<Update disable */\n#define  TIM_CR1_URS                         0x00000004U            /*!<Update request source */\n#define  TIM_CR1_OPM                         0x00000008U            /*!<One pulse mode */\n#define  TIM_CR1_DIR                         0x00000010U            /*!<Direction */\n\n#define  TIM_CR1_CMS                         0x00000060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define  TIM_CR1_CMS_0                       0x00000020U            /*!<Bit 0 */\n#define  TIM_CR1_CMS_1                       0x00000040U            /*!<Bit 1 */\n\n#define  TIM_CR1_ARPE                        0x00000080U            /*!<Auto-reload preload enable */\n\n#define  TIM_CR1_CKD                         0x00000300U            /*!<CKD[1:0] bits (clock division) */\n#define  TIM_CR1_CKD_0                       0x00000100U            /*!<Bit 0 */\n#define  TIM_CR1_CKD_1                       0x00000200U            /*!<Bit 1 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control */\n#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */\n#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection */\n\n#define  TIM_CR2_MMS                         0x00000070U            /*!<MMS[2:0] bits (Master Mode Selection) */\n#define  TIM_CR2_MMS_0                       0x00000010U            /*!<Bit 0 */\n#define  TIM_CR2_MMS_1                       0x00000020U            /*!<Bit 1 */\n#define  TIM_CR2_MMS_2                       0x00000040U            /*!<Bit 2 */\n\n#define  TIM_CR2_TI1S                        0x00000080U            /*!<TI1 Selection */\n#define  TIM_CR2_OIS1                        0x00000100U            /*!<Output Idle state 1 (OC1 output) */\n#define  TIM_CR2_OIS1N                       0x00000200U            /*!<Output Idle state 1 (OC1N output) */\n#define  TIM_CR2_OIS2                        0x00000400U            /*!<Output Idle state 2 (OC2 output) */\n#define  TIM_CR2_OIS2N                       0x00000800U            /*!<Output Idle state 2 (OC2N output) */\n#define  TIM_CR2_OIS3                        0x00001000U            /*!<Output Idle state 3 (OC3 output) */\n#define  TIM_CR2_OIS3N                       0x00002000U            /*!<Output Idle state 3 (OC3N output) */\n#define  TIM_CR2_OIS4                        0x00004000U            /*!<Output Idle state 4 (OC4 output) */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define  TIM_SMCR_SMS                        0x00000007U            /*!<SMS[2:0] bits (Slave mode selection) */\n#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */\n#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */\n#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */\n\n#define  TIM_SMCR_TS                         0x00000070U            /*!<TS[2:0] bits (Trigger selection) */\n#define  TIM_SMCR_TS_0                       0x00000010U            /*!<Bit 0 */\n#define  TIM_SMCR_TS_1                       0x00000020U            /*!<Bit 1 */\n#define  TIM_SMCR_TS_2                       0x00000040U            /*!<Bit 2 */\n\n#define  TIM_SMCR_MSM                        0x00000080U            /*!<Master/slave mode */\n\n#define  TIM_SMCR_ETF                        0x00000F00U            /*!<ETF[3:0] bits (External trigger filter) */\n#define  TIM_SMCR_ETF_0                      0x00000100U            /*!<Bit 0 */\n#define  TIM_SMCR_ETF_1                      0x00000200U            /*!<Bit 1 */\n#define  TIM_SMCR_ETF_2                      0x00000400U            /*!<Bit 2 */\n#define  TIM_SMCR_ETF_3                      0x00000800U            /*!<Bit 3 */\n\n#define  TIM_SMCR_ETPS                       0x00003000U            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define  TIM_SMCR_ETPS_0                     0x00001000U            /*!<Bit 0 */\n#define  TIM_SMCR_ETPS_1                     0x00002000U            /*!<Bit 1 */\n\n#define  TIM_SMCR_ECE                        0x00004000U            /*!<External clock enable */\n#define  TIM_SMCR_ETP                        0x00008000U            /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define  TIM_DIER_UIE                        0x00000001U            /*!<Update interrupt enable */\n#define  TIM_DIER_CC1IE                      0x00000002U            /*!<Capture/Compare 1 interrupt enable */\n#define  TIM_DIER_CC2IE                      0x00000004U            /*!<Capture/Compare 2 interrupt enable */\n#define  TIM_DIER_CC3IE                      0x00000008U            /*!<Capture/Compare 3 interrupt enable */\n#define  TIM_DIER_CC4IE                      0x00000010U            /*!<Capture/Compare 4 interrupt enable */\n#define  TIM_DIER_COMIE                      0x00000020U            /*!<COM interrupt enable */\n#define  TIM_DIER_TIE                        0x00000040U            /*!<Trigger interrupt enable */\n#define  TIM_DIER_BIE                        0x00000080U            /*!<Break interrupt enable */\n#define  TIM_DIER_UDE                        0x00000100U            /*!<Update DMA request enable */\n#define  TIM_DIER_CC1DE                      0x00000200U            /*!<Capture/Compare 1 DMA request enable */\n#define  TIM_DIER_CC2DE                      0x00000400U            /*!<Capture/Compare 2 DMA request enable */\n#define  TIM_DIER_CC3DE                      0x00000800U            /*!<Capture/Compare 3 DMA request enable */\n#define  TIM_DIER_CC4DE                      0x00001000U            /*!<Capture/Compare 4 DMA request enable */\n#define  TIM_DIER_COMDE                      0x00002000U            /*!<COM DMA request enable */\n#define  TIM_DIER_TDE                        0x00004000U            /*!<Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define  TIM_SR_UIF                          0x00000001U            /*!<Update interrupt Flag */\n#define  TIM_SR_CC1IF                        0x00000002U            /*!<Capture/Compare 1 interrupt Flag */\n#define  TIM_SR_CC2IF                        0x00000004U            /*!<Capture/Compare 2 interrupt Flag */\n#define  TIM_SR_CC3IF                        0x00000008U            /*!<Capture/Compare 3 interrupt Flag */\n#define  TIM_SR_CC4IF                        0x00000010U            /*!<Capture/Compare 4 interrupt Flag */\n#define  TIM_SR_COMIF                        0x00000020U            /*!<COM interrupt Flag */\n#define  TIM_SR_TIF                          0x00000040U            /*!<Trigger interrupt Flag */\n#define  TIM_SR_BIF                          0x00000080U            /*!<Break interrupt Flag */\n#define  TIM_SR_CC1OF                        0x00000200U            /*!<Capture/Compare 1 Overcapture Flag */\n#define  TIM_SR_CC2OF                        0x00000400U            /*!<Capture/Compare 2 Overcapture Flag */\n#define  TIM_SR_CC3OF                        0x00000800U            /*!<Capture/Compare 3 Overcapture Flag */\n#define  TIM_SR_CC4OF                        0x00001000U            /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation */\n#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation */\n#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation */\n#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation */\n#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation */\n#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */\n#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation */\n#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */\n#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */\n\n#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable */\n#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable */\n\n#define  TIM_CCMR1_OC1M                      0x00000070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\n#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */\n#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */\n#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */\n\n#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable */\n\n#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */\n#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */\n\n#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable */\n#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable */\n\n#define  TIM_CCMR1_OC2M                      0x00007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\n#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */\n#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */\n#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */\n\n#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define  TIM_CCMR1_IC1PSC                    0x0000000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define  TIM_CCMR1_IC1PSC_0                  0x00000004U            /*!<Bit 0 */\n#define  TIM_CCMR1_IC1PSC_1                  0x00000008U            /*!<Bit 1 */\n\n#define  TIM_CCMR1_IC1F                      0x000000F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\n#define  TIM_CCMR1_IC1F_0                    0x00000010U            /*!<Bit 0 */\n#define  TIM_CCMR1_IC1F_1                    0x00000020U            /*!<Bit 1 */\n#define  TIM_CCMR1_IC1F_2                    0x00000040U            /*!<Bit 2 */\n#define  TIM_CCMR1_IC1F_3                    0x00000080U            /*!<Bit 3 */\n\n#define  TIM_CCMR1_IC2PSC                    0x00000C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define  TIM_CCMR1_IC2PSC_0                  0x00000400U            /*!<Bit 0 */\n#define  TIM_CCMR1_IC2PSC_1                  0x00000800U            /*!<Bit 1 */\n\n#define  TIM_CCMR1_IC2F                      0x0000F000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\n#define  TIM_CCMR1_IC2F_0                    0x00001000U            /*!<Bit 0 */\n#define  TIM_CCMR1_IC2F_1                    0x00002000U            /*!<Bit 1 */\n#define  TIM_CCMR1_IC2F_2                    0x00004000U            /*!<Bit 2 */\n#define  TIM_CCMR1_IC2F_3                    0x00008000U            /*!<Bit 3 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define  TIM_CCMR2_CC3S                      0x00000003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define  TIM_CCMR2_CC3S_0                    0x00000001U            /*!<Bit 0 */\n#define  TIM_CCMR2_CC3S_1                    0x00000002U            /*!<Bit 1 */\n\n#define  TIM_CCMR2_OC3FE                     0x00000004U            /*!<Output Compare 3 Fast enable */\n#define  TIM_CCMR2_OC3PE                     0x00000008U            /*!<Output Compare 3 Preload enable */\n\n#define  TIM_CCMR2_OC3M                      0x00000070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define  TIM_CCMR2_OC3M_0                    0x00000010U            /*!<Bit 0 */\n#define  TIM_CCMR2_OC3M_1                    0x00000020U            /*!<Bit 1 */\n#define  TIM_CCMR2_OC3M_2                    0x00000040U            /*!<Bit 2 */\n\n#define  TIM_CCMR2_OC3CE                     0x00000080U            /*!<Output Compare 3 Clear Enable */\n\n#define  TIM_CCMR2_CC4S                      0x00000300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define  TIM_CCMR2_CC4S_0                    0x00000100U            /*!<Bit 0 */\n#define  TIM_CCMR2_CC4S_1                    0x00000200U            /*!<Bit 1 */\n\n#define  TIM_CCMR2_OC4FE                     0x00000400U            /*!<Output Compare 4 Fast enable */\n#define  TIM_CCMR2_OC4PE                     0x00000800U            /*!<Output Compare 4 Preload enable */\n\n#define  TIM_CCMR2_OC4M                      0x00007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define  TIM_CCMR2_OC4M_0                    0x00001000U            /*!<Bit 0 */\n#define  TIM_CCMR2_OC4M_1                    0x00002000U            /*!<Bit 1 */\n#define  TIM_CCMR2_OC4M_2                    0x00004000U            /*!<Bit 2 */\n\n#define  TIM_CCMR2_OC4CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define  TIM_CCMR2_IC3PSC                    0x0000000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define  TIM_CCMR2_IC3PSC_0                  0x00000004U            /*!<Bit 0 */\n#define  TIM_CCMR2_IC3PSC_1                  0x00000008U            /*!<Bit 1 */\n\n#define  TIM_CCMR2_IC3F                      0x000000F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define  TIM_CCMR2_IC3F_0                    0x00000010U            /*!<Bit 0 */\n#define  TIM_CCMR2_IC3F_1                    0x00000020U            /*!<Bit 1 */\n#define  TIM_CCMR2_IC3F_2                    0x00000040U            /*!<Bit 2 */\n#define  TIM_CCMR2_IC3F_3                    0x00000080U            /*!<Bit 3 */\n\n#define  TIM_CCMR2_IC4PSC                    0x00000C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define  TIM_CCMR2_IC4PSC_0                  0x00000400U            /*!<Bit 0 */\n#define  TIM_CCMR2_IC4PSC_1                  0x00000800U            /*!<Bit 1 */\n\n#define  TIM_CCMR2_IC4F                      0x0000F000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define  TIM_CCMR2_IC4F_0                    0x00001000U            /*!<Bit 0 */\n#define  TIM_CCMR2_IC4F_1                    0x00002000U            /*!<Bit 1 */\n#define  TIM_CCMR2_IC4F_2                    0x00004000U            /*!<Bit 2 */\n#define  TIM_CCMR2_IC4F_3                    0x00008000U            /*!<Bit 3 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */\n#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */\n#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */\n#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */\n#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */\n#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */\n#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */\n#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */\n#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */\n#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */\n#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */\n#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */\n#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */\n#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */\n#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define  TIM_CNT_CNT                         0x0000FFFFU            /*!<Counter Value */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define  TIM_PSC_PSC                         0x0000FFFFU            /*!<Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define  TIM_ARR_ARR                         0x0000FFFFU            /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define  TIM_RCR_REP                         0x000000FF               /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define  TIM_CCR1_CCR1                       0x0000FFFFU            /*!<Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define  TIM_CCR2_CCR2                       0x0000FFFFU            /*!<Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define  TIM_CCR3_CCR3                       0x0000FFFFU            /*!<Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define  TIM_CCR4_CCR4                       0x0000FFFFU            /*!<Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */\n#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */\n#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */\n#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */\n#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */\n#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */\n#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */\n#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */\n\n#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */\n#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */\n\n#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */\n#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode */\n#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable */\n#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity */\n#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable */\n#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define  TIM_DCR_DBA                         0x0000001FU            /*!<DBA[4:0] bits (DMA Base Address) */\n#define  TIM_DCR_DBA_0                       0x00000001U            /*!<Bit 0 */\n#define  TIM_DCR_DBA_1                       0x00000002U            /*!<Bit 1 */\n#define  TIM_DCR_DBA_2                       0x00000004U            /*!<Bit 2 */\n#define  TIM_DCR_DBA_3                       0x00000008U            /*!<Bit 3 */\n#define  TIM_DCR_DBA_4                       0x00000010U            /*!<Bit 4 */\n\n#define  TIM_DCR_DBL                         0x00001F00U            /*!<DBL[4:0] bits (DMA Burst Length) */\n#define  TIM_DCR_DBL_0                       0x00000100U            /*!<Bit 0 */\n#define  TIM_DCR_DBL_1                       0x00000200U            /*!<Bit 1 */\n#define  TIM_DCR_DBL_2                       0x00000400U            /*!<Bit 2 */\n#define  TIM_DCR_DBL_3                       0x00000800U            /*!<Bit 3 */\n#define  TIM_DCR_DBL_4                       0x00001000U            /*!<Bit 4 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define  TIM_DMAR_DMAB                       0x0000FFFFU            /*!<DMA register for burst accesses */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI4_RMP                       0x000000C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\n#define TIM_OR_TI4_RMP_0                     0x00000040U            /*!<Bit 0 */\n#define TIM_OR_TI4_RMP_1                     0x00000080U            /*!<Bit 1 */\n#define TIM_OR_ITR1_RMP                      0x00000C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0                    0x00000400U            /*!<Bit 0 */\n#define TIM_OR_ITR1_RMP_1                    0x00000800U            /*!<Bit 1 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define  USART_SR_PE                         0x00000001U            /*!<Parity Error */\n#define  USART_SR_FE                         0x00000002U            /*!<Framing Error */\n#define  USART_SR_NE                         0x00000004U            /*!<Noise Error Flag */\n#define  USART_SR_ORE                        0x00000008U            /*!<OverRun Error */\n#define  USART_SR_IDLE                       0x00000010U            /*!<IDLE line detected */\n#define  USART_SR_RXNE                       0x00000020U            /*!<Read Data Register Not Empty */\n#define  USART_SR_TC                         0x00000040U            /*!<Transmission Complete */\n#define  USART_SR_TXE                        0x00000080U            /*!<Transmit Data Register Empty */\n#define  USART_SR_LBD                        0x00000100U            /*!<LIN Break Detection Flag */\n#define  USART_SR_CTS                        0x00000200U            /*!<CTS Flag */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define  USART_DR_DR                         0x000001FFU            /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define  USART_BRR_DIV_Fraction              0x0000000FU            /*!<Fraction of USARTDIV */\n#define  USART_BRR_DIV_Mantissa              0x0000FFF0U            /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define  USART_CR1_SBK                       0x00000001U            /*!<Send Break */\n#define  USART_CR1_RWU                       0x00000002U            /*!<Receiver wakeup */\n#define  USART_CR1_RE                        0x00000004U            /*!<Receiver Enable */\n#define  USART_CR1_TE                        0x00000008U            /*!<Transmitter Enable */\n#define  USART_CR1_IDLEIE                    0x00000010U            /*!<IDLE Interrupt Enable */\n#define  USART_CR1_RXNEIE                    0x00000020U            /*!<RXNE Interrupt Enable */\n#define  USART_CR1_TCIE                      0x00000040U            /*!<Transmission Complete Interrupt Enable */\n#define  USART_CR1_TXEIE                     0x00000080U            /*!<PE Interrupt Enable */\n#define  USART_CR1_PEIE                      0x00000100U            /*!<PE Interrupt Enable */\n#define  USART_CR1_PS                        0x00000200U            /*!<Parity Selection */\n#define  USART_CR1_PCE                       0x00000400U            /*!<Parity Control Enable */\n#define  USART_CR1_WAKE                      0x00000800U            /*!<Wakeup method */\n#define  USART_CR1_M                         0x00001000U            /*!<Word length */\n#define  USART_CR1_UE                        0x00002000U            /*!<USART Enable */\n#define  USART_CR1_OVER8                     0x00008000U            /*!<USART Oversampling by 8 enable */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define  USART_CR2_ADD                       0x0000000FU            /*!<Address of the USART node */\n#define  USART_CR2_LBDL                      0x00000020U            /*!<LIN Break Detection Length */\n#define  USART_CR2_LBDIE                     0x00000040U            /*!<LIN Break Detection Interrupt Enable */\n#define  USART_CR2_LBCL                      0x00000100U            /*!<Last Bit Clock pulse */\n#define  USART_CR2_CPHA                      0x00000200U            /*!<Clock Phase */\n#define  USART_CR2_CPOL                      0x00000400U            /*!<Clock Polarity */\n#define  USART_CR2_CLKEN                     0x00000800U            /*!<Clock Enable */\n\n#define  USART_CR2_STOP                      0x00003000U            /*!<STOP[1:0] bits (STOP bits) */\n#define  USART_CR2_STOP_0                    0x00001000U            /*!<Bit 0 */\n#define  USART_CR2_STOP_1                    0x00002000U            /*!<Bit 1 */\n\n#define  USART_CR2_LINEN                     0x00004000U            /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define  USART_CR3_EIE                       0x00000001U            /*!<Error Interrupt Enable */\n#define  USART_CR3_IREN                      0x00000002U            /*!<IrDA mode Enable */\n#define  USART_CR3_IRLP                      0x00000004U            /*!<IrDA Low-Power */\n#define  USART_CR3_HDSEL                     0x00000008U            /*!<Half-Duplex Selection */\n#define  USART_CR3_NACK                      0x00000010U            /*!<Smartcard NACK enable */\n#define  USART_CR3_SCEN                      0x00000020U            /*!<Smartcard mode enable */\n#define  USART_CR3_DMAR                      0x00000040U            /*!<DMA Enable Receiver */\n#define  USART_CR3_DMAT                      0x00000080U            /*!<DMA Enable Transmitter */\n#define  USART_CR3_RTSE                      0x00000100U            /*!<RTS Enable */\n#define  USART_CR3_CTSE                      0x00000200U            /*!<CTS Enable */\n#define  USART_CR3_CTSIE                     0x00000400U            /*!<CTS Interrupt Enable */\n#define  USART_CR3_ONEBIT                    0x00000800U            /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define  USART_GTPR_PSC                      0x000000FFU            /*!<PSC[7:0] bits (Prescaler value) */\n#define  USART_GTPR_PSC_0                    0x00000001U            /*!<Bit 0 */\n#define  USART_GTPR_PSC_1                    0x00000002U            /*!<Bit 1 */\n#define  USART_GTPR_PSC_2                    0x00000004U            /*!<Bit 2 */\n#define  USART_GTPR_PSC_3                    0x00000008U            /*!<Bit 3 */\n#define  USART_GTPR_PSC_4                    0x00000010U            /*!<Bit 4 */\n#define  USART_GTPR_PSC_5                    0x00000020U            /*!<Bit 5 */\n#define  USART_GTPR_PSC_6                    0x00000040U            /*!<Bit 6 */\n#define  USART_GTPR_PSC_7                    0x00000080U            /*!<Bit 7 */\n\n#define  USART_GTPR_GT                       0x0000FF00U            /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define  WWDG_CR_T                           0x0000007FU            /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define  WWDG_CR_T_0                         0x00000001U            /*!<Bit 0 */\n#define  WWDG_CR_T_1                         0x00000002U            /*!<Bit 1 */\n#define  WWDG_CR_T_2                         0x00000004U            /*!<Bit 2 */\n#define  WWDG_CR_T_3                         0x00000008U            /*!<Bit 3 */\n#define  WWDG_CR_T_4                         0x00000010U            /*!<Bit 4 */\n#define  WWDG_CR_T_5                         0x00000020U            /*!<Bit 5 */\n#define  WWDG_CR_T_6                         0x00000040U            /*!<Bit 6 */\n\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n#define  WWDG_CR_WDGA                        0x00000080U            /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define  WWDG_CFR_W                          0x0000007FU            /*!<W[6:0] bits (7-bit window value) */\n#define  WWDG_CFR_W_0                        0x00000001U            /*!<Bit 0 */\n#define  WWDG_CFR_W_1                        0x00000002U            /*!<Bit 1 */\n#define  WWDG_CFR_W_2                        0x00000004U            /*!<Bit 2 */\n#define  WWDG_CFR_W_3                        0x00000008U            /*!<Bit 3 */\n#define  WWDG_CFR_W_4                        0x00000010U            /*!<Bit 4 */\n#define  WWDG_CFR_W_5                        0x00000020U            /*!<Bit 5 */\n#define  WWDG_CFR_W_6                        0x00000040U            /*!<Bit 6 */\n\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define  WWDG_CFR_WDGTB                      0x00000180U            /*!<WDGTB[1:0] bits (Timer Base) */\n#define  WWDG_CFR_WDGTB_0                    0x00000080U            /*!<Bit 0 */\n#define  WWDG_CFR_WDGTB_1                    0x00000100U            /*!<Bit 1 */\n\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define  WWDG_CFR_EWI                        0x00000200U            /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define  WWDG_SR_EWIF                        0x00000001U            /*!<Early Wakeup Interrupt Flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU\n#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U\n#define  DBGMCU_CR_DBG_STOP                  0x00000002U\n#define  DBGMCU_CR_DBG_STANDBY               0x00000004U\n#define  DBGMCU_CR_TRACE_IOEN                0x00000020U\n\n#define  DBGMCU_CR_TRACE_MODE                0x000000C0U\n#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */\n#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U\n#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U\n#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U\n#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U\n#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U\n#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U\n#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U\n#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U\n#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U\n#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U\n#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U\n#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U\n#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U\n#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U\n#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U\n#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U\n#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U\n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U\n#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U\n#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U\n#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U\n#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG\t\t\t                        */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/\n#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request */\n#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */\n#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid */\n#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select */\n#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */\n#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */\n#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */\n\n/********************  Bit definition forUSB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */\n#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */\n#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */\n#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */\n#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */\n#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */\n#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */\n#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */\n#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */\n\n#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */\n#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */\n\n#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */\n#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */\n\n/********************  Bit definition forUSB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */\n\n/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected */\n#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change */\n#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected */\n#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change */\n#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done */\n\n/********************  Bit definition forUSB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect */\n#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status */\n#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status */\n\n#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */\n#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */\n#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */\n#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK */\n#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK */\n#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK */\n#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK */\n#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */\n\n/********************  Bit definition forUSB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */\n\n/********************  Bit definition forUSB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number */\n#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */\n\n/********************  Bit definition forUSB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status */\n\n#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */\n#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */\n#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error */\n#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */\n\n/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */\n\n#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */\n#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */\n#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */\n#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */\n#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */\n#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */\n#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */\n\n#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */\n#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */\n#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */\n#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */\n#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select */\n#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume */\n#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator */\n#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement */\n#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through */\n#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable */\n#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode */\n#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode */\n#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet */\n\n/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset */\n#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset */\n#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush */\n#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush */\n\n#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */\n#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */\n\n/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */\n#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask */\n#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask */\n\n/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available */\n\n#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */\n\n/********************  Bit definition forUSB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */\n\n/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask */\n#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask */\n#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask */\n#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask */\n\n/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation */\n#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt */\n#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt */\n#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame */\n#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty */\n#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty */\n#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */\n#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective */\n#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend */\n#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend */\n#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset */\n#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done */\n#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */\n#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt */\n#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt */\n#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt */\n#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer */\n#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended */\n#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt */\n#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt */\n#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty */\n#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change */\n#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt */\n#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt */\n\n/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask */\n#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask */\n#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask */\n#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask */\n#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask */\n#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask */\n#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask */\n#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask */\n#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask */\n#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask */\n#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask */\n#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask */\n#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask */\n#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask */\n#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask */\n#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask */\n#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask */\n#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask */\n#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask */\n#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask */\n#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask */\n#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask */\n#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask */\n#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask */\n\n/********************  Bit definition forUSB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits */\n#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */\n#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */\n#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */\n#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */\n#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */\n#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */\n\n#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */\n#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */\n#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */\n\n#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */\n#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */\n#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */\n#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */\n\n#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */\n#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */\n#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */\n#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */\n\n#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */\n#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */\n#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */\n#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */\n#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */\n#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */\n#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */\n#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */\n#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */\n\n#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */\n#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */\n#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */\n\n#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */\n#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */\n#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */\n#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */\n\n#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */\n#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */\n#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */\n#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */\n\n#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */\n#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */\n#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */\n#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */\n\n/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD                    0x0000FFFFU            /*!< RxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT                  0x0000FFFFU            /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth */\n#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address */\n#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */\n\n/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */\n\n/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */\n#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */\n#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */\n\n/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit */\n#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition forUSB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */\n#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */\n#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable */\n#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit */\n#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition forUSB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */\n\n/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */\n#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */\n\n/********************  Bit definition forUSB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status */\n#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected */\n#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable */\n#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active */\n#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change */\n#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume */\n#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend */\n#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset */\n\n#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */\n#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */\n#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */\n#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */\n\n#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */\n#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */\n#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */\n#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */\n#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */\n\n#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */\n#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */\n#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */\n\n/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */\n#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */\n\n/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */\n#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */\n#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */\n#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */\n#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */\n\n#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */\n#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */\n#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */\n#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */\n\n#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */\n#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */\n#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */\n#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */\n#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */\n#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */\n#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */\n\n/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */\n#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */\n#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */\n#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */\n#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */\n#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */\n\n#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */\n#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */\n\n#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */\n#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */\n#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */\n#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */\n#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */\n#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */\n#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */\n#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */\n\n/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */\n#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */\n#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */\n#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */\n#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */\n#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */\n#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */\n\n#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */\n#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */\n#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */\n#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */\n#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */\n#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */\n#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */\n\n#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */\n#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */\n#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */\n\n/********************  Bit definition forUSB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */\n#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */\n\n/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */\n/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */\n#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */\n\n/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */\n\n/********************  Bit definition forUSB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */\n\n/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space avail */\n\n/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */\n#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */\n\n/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */\n\n/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3))\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                   ((INSTANCE) == TIM2)   || \\\n                                   ((INSTANCE) == TIM3)   || \\\n                                   ((INSTANCE) == TIM4)   || \\\n                                   ((INSTANCE) == TIM5)   || \\\n                                   ((INSTANCE) == TIM6)   || \\\n                                   ((INSTANCE) == TIM7)   || \\\n                                   ((INSTANCE) == TIM8)   || \\\n                                   ((INSTANCE) == TIM9)   || \\\n                                   ((INSTANCE) == TIM10)  || \\\n                                   ((INSTANCE) == TIM11)  || \\\n                                   ((INSTANCE) == TIM12)  || \\\n                                   ((INSTANCE) == TIM13)  || \\\n                                   ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                            ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM6) || \\\n                                          ((INSTANCE) == TIM7) || \\\n                                          ((INSTANCE) == TIM8) || \\\n                                          ((INSTANCE) == TIM9) || \\\n                                          ((INSTANCE) == TIM12))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input available ***********/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6))\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                        ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F205xx_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f2xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f2xx.h\n  * @author  MCD Application Team\n  * @version V2.1.2\n  * @date    29-June-2016\n  * @brief   CMSIS STM32F2xx Device Peripheral Access Layer Header File.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32F2xx device used in the target application\n  *              - To use or not the peripheral’s drivers in application code(i.e.\n  *                code will be based on direct access to peripheral’s registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f2xx\n  * @{\n  */\n\n#ifndef __STM32F2xx_H\n#define __STM32F2xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined (STM32F2)\n#define STM32F2\n#endif /* STM32F2 */\n\n/* Uncomment the line below according to the target STM32 device used in your\n   application\n  */\n/* #if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx) */\n\n  /* #define STM32F205xx */   /*!< STM32F205RG, STM32F205VG, STM32F205ZG, STM32F205RF, STM32F205VF, STM32F205ZF,\n                                   STM32F205RE, STM32F205VE, STM32F205ZE, STM32F205RC, STM32F205VC, STM32F205ZC,\n                                   STM32F205RB and STM32F205VB Devices */\n  /* #define STM32F215xx */   /*!< STM32F215RG, STM32F215VG, STM32F215ZG, STM32F215RE, STM32F215VE and STM32F215ZE Devices */\n  /* #define STM32F207xx */   /*!< STM32F207VG, STM32F207ZG, STM32F207IG, STM32F207VF, STM32F207ZF, STM32F207IF,\n                                   STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC and STM32F207IC Devices */\n  /* #define STM32F217xx */   /*!< STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE and STM32F217IE Devices */\n\n//#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS Device version number V2.1.2\n  */\n#define __STM32F2xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */\n#define __STM32F2xx_CMSIS_VERSION_SUB1   (0x01U) /*!< [23:16] sub1 version */\n#define __STM32F2xx_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */\n#define __STM32F2xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32F2xx_CMSIS_VERSION        ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\\\n                                         |(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\\\n                                         |(__STM32F2xx_CMSIS_VERSION_SUB2 << 8 )\\\n                                         |(__STM32F2xx_CMSIS_VERSION))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32F215xx)\n  #include \"stm32f215xx.h\"\n#elif defined(STM32F205xx)\n  #include \"stm32f205xx.h\"\n// #elif defined(STM32F207xx)\n//   #include \"stm32f207xx.h\"\n// #elif defined(STM32F217xx)\n//   #include \"stm32f217xx.h\"\n#else\n #error \"Please select first the target STM32F2xx device used in your application (in stm32f2xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  ERROR = 0,\n  SUCCESS = !ERROR\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f2xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F2xx_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f2xx_hal_def.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f2xx_hal_def.h\n  * @author  MCD Application Team\n  * @version V1.1.3\n  * @date    29-June-2016\n  * @brief   This file contains HAL common defines, enumeration, macros and\n  *          structures definitions.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F2xx_HAL_DEF\n#define __STM32F2xx_HAL_DEF\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f2xx.h\"\n//#include \"Legacy/stm32_hal_legacy.h\"\n//#include <stdio.h>\n\n/* Exported types ------------------------------------------------------------*/\n\n/**\n  * @brief  HAL Status structures definition\n  */\ntypedef enum\n{\n  HAL_OK       = 0x00U,\n  HAL_ERROR    = 0x01U,\n  HAL_BUSY     = 0x02U,\n  HAL_TIMEOUT  = 0x03U\n} HAL_StatusTypeDef;\n\n/**\n  * @brief  HAL Lock structures definition\n  */\ntypedef enum\n{\n  HAL_UNLOCKED = 0x00U,\n  HAL_LOCKED   = 0x01U\n} HAL_LockTypeDef;\n\n/* Exported macro ------------------------------------------------------------*/\n#define HAL_MAX_DELAY      0xFFFFFFFFU\n\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)\n\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_)               \\\n                        do{                                                      \\\n                              (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \\\n                              (__DMA_HANDLE_).Parent = (__HANDLE__);             \\\n                          } while(0)\n\n#define UNUSED(x) ((void)(x))\n\n/** @brief Reset the Handle's State field.\n  * @param __HANDLE__: specifies the Peripheral Handle.\n  * @note  This macro can be used for the following purpose:\n  *          - When the Handle is declared as local variable; before passing it as parameter\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro\n  *            to set to 0 the Handle's \"State\" field.\n  *            Otherwise, \"State\" field may have any random value and the first time the function\n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\n  * @retval None\n  */\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\n\n#if (USE_RTOS == 1)\n  /* Reserved for future use */\n  #error \" USE_RTOS should be 0 in the current HAL release \"\n#else\n  #define __HAL_LOCK(__HANDLE__)                                           \\\n                                do{                                        \\\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\n                                    {                                      \\\n                                       return HAL_BUSY;                    \\\n                                    }                                      \\\n                                    else                                   \\\n                                    {                                      \\\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\n                                    }                                      \\\n                                  }while (0)\n\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\n                                  do{                                       \\\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\n                                    }while (0)\n#endif /* USE_RTOS */\n\n#if  defined ( __GNUC__ )\n  #ifndef __weak\n    #define __weak   __attribute__((weak))\n  #endif /* __weak */\n  #ifndef __packed\n    #define __packed __attribute__((__packed__))\n  #endif /* __packed */\n#endif /* __GNUC__ */\n\n\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\n#if defined   (__GNUC__)        /* GNU Compiler */\n  #ifndef __ALIGN_END\n    #define __ALIGN_END    __attribute__ ((aligned (4)))\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN\n    #define __ALIGN_BEGIN\n  #endif /* __ALIGN_BEGIN */\n#else\n  #ifndef __ALIGN_END\n    #define __ALIGN_END\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN\n    #if defined   (__CC_ARM)      /* ARM Compiler */\n      #define __ALIGN_BEGIN    __align(4)\n    #elif defined (__ICCARM__)    /* IAR Compiler */\n      #define __ALIGN_BEGIN\n    #endif /* __CC_ARM */\n  #endif /* __ALIGN_BEGIN */\n#endif /* __GNUC__ */\n\n/**\n  * @brief  __NOINLINE definition\n  */\n#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\n/* ARM & GNUCompiler\n   ----------------\n*/\n#define __NOINLINE __attribute__ ( (noinline) )\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n*/\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ___STM32F2xx_HAL_DEF */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f2xx_hal_gpio_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f2xx_hal_gpio_ex.h\n  * @author  MCD Application Team\n  * @version V1.1.3\n  * @date    29-June-2016\n  * @brief   Header file of GPIO HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F2xx_HAL_GPIO_EX_H\n#define __STM32F2xx_HAL_GPIO_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f2xx_hal_def.h\"\n\n/** @addtogroup STM32F2xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup GPIOEx GPIOEx\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\n  * @{\n  */\n\n/** @defgroup GPIO_Alternate_function_selection GPIO Alternate function selection\n  * @{\n  */\n\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */\n\n/**\n  * @brief   AF 11 selection\n  */\n#if defined(STM32F207xx) || defined(STM32F217xx)\n#define GPIO_AF11_ETH             ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\n#endif /* STM32F207xx || STM32F217xx */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FSMC          ((uint8_t)0xCU)  /* FSMC Alternate Function mapping                     */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0xCU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 13 selection\n  */\n#if defined(STM32F207xx) || defined(STM32F217xx)\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\n#endif /* STM32F207xx || STM32F217xx */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\n  * @{\n  */\n/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\n  * @{\n  */\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U :\\\n                                               ((__GPIOx__) == (GPIOH))? 7U :\\\n                                               ((__GPIOx__) == (GPIOI))? 8U : 9U)\n/**\n  * @}\n  */\n\n/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\n  * @{\n  */\n#if defined(STM32F207xx) || defined(STM32F217xx)\n\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))\n#else /* STM32F207xx || STM32F217xx */\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \\\n                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))\n#endif /* STM32F207xx || STM32F217xx */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F2xx_HAL_GPIO_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f413xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f413xx.h\n  * @author  MCD Application Team\n  * @version V2.6.0\n  * @date    04-November-2016\n  * @brief   CMSIS STM32F413xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral’s registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f413xx\n  * @{\n  */\n\n#ifndef __STM32F413xx_H\n#define __STM32F413xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\n  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  CAN3_TX_IRQn                = 74,     /*!< CAN3 TX Interrupt                                                 */\n  CAN3_RX0_IRQn               = 75,     /*!< CAN3 RX0 Interrupt                                                */\n  CAN3_RX1_IRQn               = 76,     /*!< CAN3 RX1 Interrupt                                                */\n  CAN3_SCE_IRQn               = 77,     /*!< CAN3 SCE Interrupt                                                */\n  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\n  UART9_IRQn                  = 88,     /*!< UART9 global Interrupt                                            */\n  UART10_IRQn                 = 89,     /*!< UART10 global Interrupt                                           */\n  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */\n  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */\n  FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                           */\n  LPTIM1_IRQn                 = 97,     /*!< LP TIM1 interrupt                                                 */\n  DFSDM2_FLT0_IRQn            = 98,     /*!< DFSDM2 Filter 0 global Interrupt                                  */\n  DFSDM2_FLT1_IRQn            = 99,     /*!< DFSDM2 Filter 1 global Interrupt                                  */\n  DFSDM2_FLT2_IRQn            = 100,    /*!< DFSDM2 Filter 2 global Interrupt                                  */\n  DFSDM2_FLT3_IRQn            = 101     /*!< DFSDM2 Filter 3 global Interrupt                                  */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief DFSDM module registers\n  */\ntypedef struct\n{\n  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\n  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\n  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\n  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\n  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\n  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\n  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\n  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\n  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\n  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\n  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\n  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\n  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\n  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\n  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\n} DFSDM_Filter_TypeDef;\n\n/**\n  * @brief DFSDM channel configuration registers\n  */\ntypedef struct\n{\n  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\n  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\n  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\n                                  short circuit detector register,                  Address offset: 0x08 */\n  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\n  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\n} DFSDM_Channel_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */\n  __IO uint32_t CFGR2;        /*!< SYSCFG Configuration register2,                    Address offset: 0x1C      */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */\n  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */\n  __IO uint32_t MCHDLYCR;     /*!< SYSCFG multi-channel delay register,               Address offset: 0x30      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */\n} FMPI2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n  __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                            Address offset: 0x90 */\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief Serial Audio Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  uint32_t  Reserved;                 /*!< Reserved                                     058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @brief LPTIMER\n  */\ntypedef struct\n{\n  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\n  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\n  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\n  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */\n  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */\n  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */\n  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\n  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */\n  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */\n} LPTIM_TypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000U /*!< FLASH (up to 1.5 MB) base address in the alias region                      */\n#define SRAM1_BASE            0x20000000U /*!< SRAM1(256 KB) base address in the alias region                             */\n#define SRAM2_BASE            0x20040000U /*!< SRAM2(64 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */\n#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */\n#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                             */\n#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22800000U /*!< SRAM2(64 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */\n#define FLASH_END             0x0817FFFFU /*!< FLASH end address                                                          */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\n#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\n#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000U)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\n#define CAN3_BASE             (APB1PERIPH_BASE + 0x6C00U)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\n#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)\n#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\n#define UART9_BASE            (APB2PERIPH_BASE + 0x1800U)\n#define UART10_BASE           (APB2PERIPH_BASE + 0x1C00U)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\n#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)\n#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)\n#define DFSDM2_BASE           (APB2PERIPH_BASE + 0x6400U)\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00U)\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20U)\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40U)\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60U)\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100U)\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180U)\n#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00U)\n#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20U)\n#define DFSDM2_Channel2_BASE  (DFSDM2_BASE + 0x40U)\n#define DFSDM2_Channel3_BASE  (DFSDM2_BASE + 0x60U)\n#define DFSDM2_Channel4_BASE  (DFSDM2_BASE + 0x80U)\n#define DFSDM2_Channel5_BASE  (DFSDM2_BASE + 0xA0U)\n#define DFSDM2_Channel6_BASE  (DFSDM2_BASE + 0xC0U)\n#define DFSDM2_Channel7_BASE  (DFSDM2_BASE + 0xE0U)\n#define DFSDM2_Filter0_BASE   (DFSDM2_BASE + 0x100U)\n#define DFSDM2_Filter1_BASE   (DFSDM2_BASE + 0x180U)\n#define DFSDM2_Filter2_BASE   (DFSDM2_BASE + 0x200U)\n#define DFSDM2_Filter3_BASE   (DFSDM2_BASE + 0x280U)\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\n\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000U\n/*!< USB registers base address */\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\n\n#define USB_OTG_GLOBAL_BASE                  0x000U\n#define USB_OTG_DEVICE_BASE                  0x800U\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\n#define USB_OTG_EP_REG_SIZE                  0x20U\n#define USB_OTG_HOST_BASE                    0x400U\n#define USB_OTG_HOST_PORT_BASE               0x440U\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\n#define USB_OTG_FIFO_BASE                    0x1000U\n#define USB_OTG_FIFO_SIZE                    0x1000U\n\n#define UID_BASE                     0x1FFF7A10U           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22U           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0U           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define CAN3                ((CAN_TypeDef *) CAN3_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define UART7               ((USART_TypeDef *) UART7_BASE)\n#define UART8               ((USART_TypeDef *) UART8_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define UART9               ((USART_TypeDef *) UART9_BASE)\n#define UART10              ((USART_TypeDef *) UART10_BASE)\n#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\n#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)\n#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)\n#define DFSDM2_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)\n#define DFSDM2_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)\n#define DFSDM2_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)\n#define DFSDM2_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)\n#define DFSDM2_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)\n#define DFSDM2_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)\n#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)\n#define DFSDM2_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)\n#define DFSDM2_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)\n#define DFSDM2_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1U << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1U << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1U << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1U << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1U << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1U << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FU << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1U << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1U << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1U << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1U << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1U << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1U << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1U << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1U << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7U << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1U << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1U << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3U << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1U << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2U << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1U << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1U << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1U << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1U << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1U << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1U << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1U << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFU << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1U << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFU << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3U << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1U << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2U << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1U << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7U << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7U << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7U << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1U << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2U << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4U << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFU << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFU << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FU << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FU << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FU << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FU << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFU << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1U << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2U << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4U << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8U << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FU << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FU << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FU << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FU << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FU << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10U << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FU << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01U << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02U << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04U << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08U << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10U << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FU << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FU << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FU << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FU << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FU << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10U << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FU << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01U << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02U << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04U << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08U << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10U << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FU << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FU << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FU << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FU << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3U << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1U << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2U << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFU << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFU << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFU << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFU << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFU << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1U << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1U << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1U << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1U << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1U << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1U << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FU << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFU << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1U << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3U << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1U << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2U << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1U << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1U << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFU << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFU << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1U << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error warning interrupt enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error passive interrupt enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-off interrupt enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last error code interrupt enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error interrupt enable */\n\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFU << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1U << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1U << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1U << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1U << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1U << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1U << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1U << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1U << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1U << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1U << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1U << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1U << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1U << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1U << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFU << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1U << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1U << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1U << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1U << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1U << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1U << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1U << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1U << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1U << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1U << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1U << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1U << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1U << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1U << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFU << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1U << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1U << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1U << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1U << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1U << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1U << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1U << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1U << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1U << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1U << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1U << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1U << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1U << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1U << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFU << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1U << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1U << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1U << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1U << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1U << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1U << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1U << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1U << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1U << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1U << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1U << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1U << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1U << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1U << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFU << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFU << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1U << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)\n#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)\n#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital Filter for Sigma Delta Modulators                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************   DFSDM channel configuration registers  ********************/\n\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\n#define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\n#define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\n\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\n\n/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\n\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\n\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\n\n/************************   DFSDM module registers  ****************************/\n\n/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\n#define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\n#define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\n\n/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\n\n/*****************  Bit definition for DFSDM_FLTISR register *******************/\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\n#define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\n#define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\n#define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\n#define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\n#define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\n#define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\n\n/*****************  Bit definition for DFSDM_FLTICR register *******************/\n#define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)\n#define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */\n#define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\n\n/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\n\n/*****************  Bit definition for DFSDM_FLTFCR register *******************/\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\n#define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\n#define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\n#define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\n#define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\n\n/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWSR register *******************/\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\n\n\n/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\n\n/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\n\n/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\n\n/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0xFU << DMA_SxCR_CHSEL_Pos)                  /*!< 0x1E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_CHSEL_3         0x10000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1U << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1U << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n#define EXTI_IMR_MR23_Pos         (23U)\n#define EXTI_IMR_MR23_Msk         (0x1U << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */\n#define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define  EXTI_IMR_IM23                       EXTI_IMR_MR23\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0xFFFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x00FFFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1U << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n#define EXTI_EMR_MR23_Pos         (23U)\n#define EXTI_EMR_MR23_Msk         (0x1U << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */\n#define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n#define  EXTI_EMR_EM23                       EXTI_EMR_MR23\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1U << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1U << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n#define EXTI_RTSR_TR23_Pos        (23U)\n#define EXTI_RTSR_TR23_Msk        (0x1U << EXTI_RTSR_TR23_Pos)                 /*!< 0x00800000 */\n#define EXTI_RTSR_TR23            EXTI_RTSR_TR23_Msk                           /*!< Rising trigger event configuration bit of line 23 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1U << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1U << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n#define EXTI_FTSR_TR23_Pos        (23U)\n#define EXTI_FTSR_TR23_Msk        (0x1U << EXTI_FTSR_TR23_Pos)                 /*!< 0x00800000 */\n#define EXTI_FTSR_TR23            EXTI_FTSR_TR23_Msk                           /*!< Falling trigger event configuration bit of line 23 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1U << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1U << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n#define EXTI_SWIER_SWIER23_Pos    (23U)\n#define EXTI_SWIER_SWIER23_Msk    (0x1U << EXTI_SWIER_SWIER23_Pos)             /*!< 0x00800000 */\n#define EXTI_SWIER_SWIER23        EXTI_SWIER_SWIER23_Msk                       /*!< Software Interrupt on line 23 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1U << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1U << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n#define EXTI_PR_PR23_Pos          (23U)\n#define EXTI_PR_PR23_Msk          (0x1U << EXTI_PR_PR23_Pos)                   /*!< 0x00800000 */\n#define EXTI_PR_PR23              EXTI_PR_PR23_Msk                             /*!< Pending bit for line 23 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFU << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1U << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1U << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1U << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1U << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1U << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1U << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1U << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1U << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1U << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1U << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1U << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1U << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1U << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1U << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1U << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FU << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01U << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02U << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04U << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08U << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10U << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1U << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1U << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1U << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1U << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1U << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3U << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1U << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1U << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1U << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFU << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0x7FFFU << FLASH_OPTCR_nWRP_Pos)       /*!< 0x7FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n#define FLASH_OPTCR_nWRP_12            0x10000000U\n#define FLASH_OPTCR_nWRP_13            0x20000000U\n#define FLASH_OPTCR_nWRP_14            0x40000000U\n#define FLASH_OPTCR_nWRP_15            0x40000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFU << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)\n#define FSMC_BCR1_MBKEN_Msk          (0x1U << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)\n#define FSMC_BCR1_MUXEN_Msk          (0x1U << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)\n#define FSMC_BCR1_MTYP_Msk           (0x3U << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1U << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2U << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)\n#define FSMC_BCR1_MWID_Msk           (0x3U << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1U << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2U << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)\n#define FSMC_BCR1_FACCEN_Msk         (0x1U << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)\n#define FSMC_BCR1_BURSTEN_Msk        (0x1U << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)\n#define FSMC_BCR1_WAITPOL_Msk        (0x1U << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)\n#define FSMC_BCR1_WAITCFG_Msk        (0x1U << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)\n#define FSMC_BCR1_WREN_Msk           (0x1U << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)\n#define FSMC_BCR1_WAITEN_Msk         (0x1U << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)\n#define FSMC_BCR1_EXTMOD_Msk         (0x1U << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1U << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)\n#define FSMC_BCR1_CPSIZE_Msk         (0x7U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)\n#define FSMC_BCR1_CBURSTRW_Msk       (0x1U << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n#define FSMC_BCR1_CCLKEN_Pos         (20U)\n#define FSMC_BCR1_CCLKEN_Msk         (0x1U << FSMC_BCR1_CCLKEN_Pos)            /*!< 0x00100000 */\n#define FSMC_BCR1_CCLKEN             FSMC_BCR1_CCLKEN_Msk                      /*!<Continous clock enable     */\n#define FSMC_BCR1_WFDIS_Pos          (21U)\n#define FSMC_BCR1_WFDIS_Msk          (0x1U << FSMC_BCR1_WFDIS_Pos)             /*!< 0x00200000 */\n#define FSMC_BCR1_WFDIS              FSMC_BCR1_WFDIS_Msk                       /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)\n#define FSMC_BCR2_MBKEN_Msk          (0x1U << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)\n#define FSMC_BCR2_MUXEN_Msk          (0x1U << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)\n#define FSMC_BCR2_MTYP_Msk           (0x3U << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1U << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2U << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)\n#define FSMC_BCR2_MWID_Msk           (0x3U << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1U << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2U << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)\n#define FSMC_BCR2_FACCEN_Msk         (0x1U << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)\n#define FSMC_BCR2_BURSTEN_Msk        (0x1U << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)\n#define FSMC_BCR2_WAITPOL_Msk        (0x1U << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)\n#define FSMC_BCR2_WAITCFG_Msk        (0x1U << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)\n#define FSMC_BCR2_WREN_Msk           (0x1U << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)\n#define FSMC_BCR2_WAITEN_Msk         (0x1U << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)\n#define FSMC_BCR2_EXTMOD_Msk         (0x1U << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1U << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)\n#define FSMC_BCR2_CPSIZE_Msk         (0x7U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)\n#define FSMC_BCR2_CBURSTRW_Msk       (0x1U << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)\n#define FSMC_BCR3_MBKEN_Msk          (0x1U << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)\n#define FSMC_BCR3_MUXEN_Msk          (0x1U << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)\n#define FSMC_BCR3_MTYP_Msk           (0x3U << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1U << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2U << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)\n#define FSMC_BCR3_MWID_Msk           (0x3U << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1U << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2U << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)\n#define FSMC_BCR3_FACCEN_Msk         (0x1U << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)\n#define FSMC_BCR3_BURSTEN_Msk        (0x1U << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)\n#define FSMC_BCR3_WAITPOL_Msk        (0x1U << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)\n#define FSMC_BCR3_WAITCFG_Msk        (0x1U << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)\n#define FSMC_BCR3_WREN_Msk           (0x1U << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)\n#define FSMC_BCR3_WAITEN_Msk         (0x1U << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)\n#define FSMC_BCR3_EXTMOD_Msk         (0x1U << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1U << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)\n#define FSMC_BCR3_CPSIZE_Msk         (0x7U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)\n#define FSMC_BCR3_CBURSTRW_Msk       (0x1U << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)\n#define FSMC_BCR4_MBKEN_Msk          (0x1U << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)\n#define FSMC_BCR4_MUXEN_Msk          (0x1U << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)\n#define FSMC_BCR4_MTYP_Msk           (0x3U << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1U << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2U << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)\n#define FSMC_BCR4_MWID_Msk           (0x3U << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1U << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2U << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)\n#define FSMC_BCR4_FACCEN_Msk         (0x1U << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)\n#define FSMC_BCR4_BURSTEN_Msk        (0x1U << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)\n#define FSMC_BCR4_WAITPOL_Msk        (0x1U << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)\n#define FSMC_BCR4_WAITCFG_Msk        (0x1U << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)\n#define FSMC_BCR4_WREN_Msk           (0x1U << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)\n#define FSMC_BCR4_WAITEN_Msk         (0x1U << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)\n#define FSMC_BCR4_EXTMOD_Msk         (0x1U << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1U << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)\n#define FSMC_BCR4_CPSIZE_Msk         (0x7U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)\n#define FSMC_BCR4_CBURSTRW_Msk       (0x1U << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)\n#define FSMC_BTR1_ADDSET_Msk         (0xFU << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)\n#define FSMC_BTR1_ADDHLD_Msk         (0xFU << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)\n#define FSMC_BTR1_DATAST_Msk         (0xFFU << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)\n#define FSMC_BTR1_BUSTURN_Msk        (0xFU << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)\n#define FSMC_BTR1_CLKDIV_Msk         (0xFU << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)\n#define FSMC_BTR1_DATLAT_Msk         (0xFU << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)\n#define FSMC_BTR1_ACCMOD_Msk         (0x3U << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1U << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2U << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)\n#define FSMC_BTR2_ADDSET_Msk         (0xFU << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)\n#define FSMC_BTR2_ADDHLD_Msk         (0xFU << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)\n#define FSMC_BTR2_DATAST_Msk         (0xFFU << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)\n#define FSMC_BTR2_BUSTURN_Msk        (0xFU << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)\n#define FSMC_BTR2_CLKDIV_Msk         (0xFU << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)\n#define FSMC_BTR2_DATLAT_Msk         (0xFU << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)\n#define FSMC_BTR2_ACCMOD_Msk         (0x3U << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1U << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2U << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)\n#define FSMC_BTR3_ADDSET_Msk         (0xFU << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)\n#define FSMC_BTR3_ADDHLD_Msk         (0xFU << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)\n#define FSMC_BTR3_DATAST_Msk         (0xFFU << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)\n#define FSMC_BTR3_BUSTURN_Msk        (0xFU << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)\n#define FSMC_BTR3_CLKDIV_Msk         (0xFU << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)\n#define FSMC_BTR3_DATLAT_Msk         (0xFU << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)\n#define FSMC_BTR3_ACCMOD_Msk         (0x3U << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1U << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2U << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)\n#define FSMC_BTR4_ADDSET_Msk         (0xFU << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)\n#define FSMC_BTR4_ADDHLD_Msk         (0xFU << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)\n#define FSMC_BTR4_DATAST_Msk         (0xFFU << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)\n#define FSMC_BTR4_BUSTURN_Msk        (0xFU << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)\n#define FSMC_BTR4_CLKDIV_Msk         (0xFU << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)\n#define FSMC_BTR4_DATLAT_Msk         (0xFU << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)\n#define FSMC_BTR4_ACCMOD_Msk         (0x3U << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1U << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2U << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)\n#define FSMC_BWTR1_ADDSET_Msk        (0xFU << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)\n#define FSMC_BWTR1_ADDHLD_Msk        (0xFU << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)\n#define FSMC_BWTR1_DATAST_Msk        (0xFFU << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)\n#define FSMC_BWTR1_BUSTURN_Msk       (0xFU << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)\n#define FSMC_BWTR1_ACCMOD_Msk        (0x3U << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1U << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2U << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)\n#define FSMC_BWTR2_ADDSET_Msk        (0xFU << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)\n#define FSMC_BWTR2_ADDHLD_Msk        (0xFU << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)\n#define FSMC_BWTR2_DATAST_Msk        (0xFFU << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)\n#define FSMC_BWTR2_BUSTURN_Msk       (0xFU << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)\n#define FSMC_BWTR2_ACCMOD_Msk        (0x3U << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1U << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2U << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)\n#define FSMC_BWTR3_ADDSET_Msk        (0xFU << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)\n#define FSMC_BWTR3_ADDHLD_Msk        (0xFU << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)\n#define FSMC_BWTR3_DATAST_Msk        (0xFFU << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)\n#define FSMC_BWTR3_BUSTURN_Msk       (0xFU << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)\n#define FSMC_BWTR3_ACCMOD_Msk        (0x3U << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1U << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2U << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)\n#define FSMC_BWTR4_ADDSET_Msk        (0xFU << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)\n#define FSMC_BWTR4_ADDHLD_Msk        (0xFU << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)\n#define FSMC_BWTR4_DATAST_Msk        (0xFFU << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)\n#define FSMC_BWTR4_BUSTURN_Msk       (0xFU << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)\n#define FSMC_BWTR4_ACCMOD_Msk        (0x3U << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1U << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2U << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT_0                 0x00000001U\n#define GPIO_OTYPER_OT_1                 0x00000002U\n#define GPIO_OTYPER_OT_2                 0x00000004U\n#define GPIO_OTYPER_OT_3                 0x00000008U\n#define GPIO_OTYPER_OT_4                 0x00000010U\n#define GPIO_OTYPER_OT_5                 0x00000020U\n#define GPIO_OTYPER_OT_6                 0x00000040U\n#define GPIO_OTYPER_OT_7                 0x00000080U\n#define GPIO_OTYPER_OT_8                 0x00000100U\n#define GPIO_OTYPER_OT_9                 0x00000200U\n#define GPIO_OTYPER_OT_10                0x00000400U\n#define GPIO_OTYPER_OT_11                0x00000800U\n#define GPIO_OTYPER_OT_12                0x00001000U\n#define GPIO_OTYPER_OT_13                0x00002000U\n#define GPIO_OTYPER_OT_14                0x00004000U\n#define GPIO_OTYPER_OT_15                0x00008000U\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDER_OSPEEDR0_Pos       (0U)\n#define GPIO_OSPEEDER_OSPEEDR0_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000003 */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDER_OSPEEDR0_Msk\n#define GPIO_OSPEEDER_OSPEEDR0_0         (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000001 */\n#define GPIO_OSPEEDER_OSPEEDR0_1         (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000002 */\n\n#define GPIO_OSPEEDER_OSPEEDR1_Pos       (2U)\n#define GPIO_OSPEEDER_OSPEEDR1_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x0000000C */\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDER_OSPEEDR1_Msk\n#define GPIO_OSPEEDER_OSPEEDR1_0         (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000004 */\n#define GPIO_OSPEEDER_OSPEEDR1_1         (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000008 */\n\n#define GPIO_OSPEEDER_OSPEEDR2_Pos       (4U)\n#define GPIO_OSPEEDER_OSPEEDR2_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000030 */\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDER_OSPEEDR2_Msk\n#define GPIO_OSPEEDER_OSPEEDR2_0         (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000010 */\n#define GPIO_OSPEEDER_OSPEEDR2_1         (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000020 */\n\n#define GPIO_OSPEEDER_OSPEEDR3_Pos       (6U)\n#define GPIO_OSPEEDER_OSPEEDR3_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x000000C0 */\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDER_OSPEEDR3_Msk\n#define GPIO_OSPEEDER_OSPEEDR3_0         (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000040 */\n#define GPIO_OSPEEDER_OSPEEDR3_1         (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000080 */\n\n#define GPIO_OSPEEDER_OSPEEDR4_Pos       (8U)\n#define GPIO_OSPEEDER_OSPEEDR4_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000300 */\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDER_OSPEEDR4_Msk\n#define GPIO_OSPEEDER_OSPEEDR4_0         (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000100 */\n#define GPIO_OSPEEDER_OSPEEDR4_1         (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000200 */\n\n#define GPIO_OSPEEDER_OSPEEDR5_Pos       (10U)\n#define GPIO_OSPEEDER_OSPEEDR5_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000C00 */\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDER_OSPEEDR5_Msk\n#define GPIO_OSPEEDER_OSPEEDR5_0         (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000400 */\n#define GPIO_OSPEEDER_OSPEEDR5_1         (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000800 */\n\n#define GPIO_OSPEEDER_OSPEEDR6_Pos       (12U)\n#define GPIO_OSPEEDER_OSPEEDR6_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00003000 */\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDER_OSPEEDR6_Msk\n#define GPIO_OSPEEDER_OSPEEDR6_0         (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00001000 */\n#define GPIO_OSPEEDER_OSPEEDR6_1         (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00002000 */\n\n#define GPIO_OSPEEDER_OSPEEDR7_Pos       (14U)\n#define GPIO_OSPEEDER_OSPEEDR7_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x0000C000 */\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDER_OSPEEDR7_Msk\n#define GPIO_OSPEEDER_OSPEEDR7_0         (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00004000 */\n#define GPIO_OSPEEDER_OSPEEDR7_1         (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00008000 */\n\n#define GPIO_OSPEEDER_OSPEEDR8_Pos       (16U)\n#define GPIO_OSPEEDER_OSPEEDR8_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00030000 */\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDER_OSPEEDR8_Msk\n#define GPIO_OSPEEDER_OSPEEDR8_0         (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00010000 */\n#define GPIO_OSPEEDER_OSPEEDR8_1         (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00020000 */\n\n#define GPIO_OSPEEDER_OSPEEDR9_Pos       (18U)\n#define GPIO_OSPEEDER_OSPEEDR9_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x000C0000 */\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDER_OSPEEDR9_Msk\n#define GPIO_OSPEEDER_OSPEEDR9_0         (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00040000 */\n#define GPIO_OSPEEDER_OSPEEDR9_1         (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00080000 */\n\n#define GPIO_OSPEEDER_OSPEEDR10_Pos      (20U)\n#define GPIO_OSPEEDER_OSPEEDR10_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDER_OSPEEDR10_Msk\n#define GPIO_OSPEEDER_OSPEEDR10_0        (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */\n#define GPIO_OSPEEDER_OSPEEDR10_1        (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */\n\n#define GPIO_OSPEEDER_OSPEEDR11_Pos      (22U)\n#define GPIO_OSPEEDER_OSPEEDR11_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDER_OSPEEDR11_Msk\n#define GPIO_OSPEEDER_OSPEEDR11_0        (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */\n#define GPIO_OSPEEDER_OSPEEDR11_1        (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */\n\n#define GPIO_OSPEEDER_OSPEEDR12_Pos      (24U)\n#define GPIO_OSPEEDER_OSPEEDR12_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDER_OSPEEDR12_Msk\n#define GPIO_OSPEEDER_OSPEEDR12_0        (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */\n#define GPIO_OSPEEDER_OSPEEDR12_1        (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */\n\n#define GPIO_OSPEEDER_OSPEEDR13_Pos      (26U)\n#define GPIO_OSPEEDER_OSPEEDR13_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDER_OSPEEDR13_Msk\n#define GPIO_OSPEEDER_OSPEEDR13_0        (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */\n#define GPIO_OSPEEDER_OSPEEDR13_1        (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */\n\n#define GPIO_OSPEEDER_OSPEEDR14_Pos      (28U)\n#define GPIO_OSPEEDER_OSPEEDR14_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDER_OSPEEDR14_Msk\n#define GPIO_OSPEEDER_OSPEEDR14_0        (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */\n#define GPIO_OSPEEDER_OSPEEDR14_1        (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */\n\n#define GPIO_OSPEEDER_OSPEEDR15_Pos      (30U)\n#define GPIO_OSPEEDER_OSPEEDR15_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDER_OSPEEDR15_Msk\n#define GPIO_OSPEEDER_OSPEEDR15_0        (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */\n#define GPIO_OSPEEDER_OSPEEDR15_1        (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPDR0_Pos            (0U)\n#define GPIO_PUPDR_PUPDR0_Msk            (0x3U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk\n#define GPIO_PUPDR_PUPDR0_0              (0x1U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPDR0_1              (0x2U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */\n\n#define GPIO_PUPDR_PUPDR1_Pos            (2U)\n#define GPIO_PUPDR_PUPDR1_Msk            (0x3U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk\n#define GPIO_PUPDR_PUPDR1_0              (0x1U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPDR1_1              (0x2U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */\n\n#define GPIO_PUPDR_PUPDR2_Pos            (4U)\n#define GPIO_PUPDR_PUPDR2_Msk            (0x3U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk\n#define GPIO_PUPDR_PUPDR2_0              (0x1U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPDR2_1              (0x2U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */\n\n#define GPIO_PUPDR_PUPDR3_Pos            (6U)\n#define GPIO_PUPDR_PUPDR3_Msk            (0x3U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk\n#define GPIO_PUPDR_PUPDR3_0              (0x1U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPDR3_1              (0x2U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */\n\n#define GPIO_PUPDR_PUPDR4_Pos            (8U)\n#define GPIO_PUPDR_PUPDR4_Msk            (0x3U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk\n#define GPIO_PUPDR_PUPDR4_0              (0x1U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPDR4_1              (0x2U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */\n\n#define GPIO_PUPDR_PUPDR5_Pos            (10U)\n#define GPIO_PUPDR_PUPDR5_Msk            (0x3U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk\n#define GPIO_PUPDR_PUPDR5_0              (0x1U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPDR5_1              (0x2U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */\n\n#define GPIO_PUPDR_PUPDR6_Pos            (12U)\n#define GPIO_PUPDR_PUPDR6_Msk            (0x3U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk\n#define GPIO_PUPDR_PUPDR6_0              (0x1U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPDR6_1              (0x2U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */\n\n#define GPIO_PUPDR_PUPDR7_Pos            (14U)\n#define GPIO_PUPDR_PUPDR7_Msk            (0x3U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk\n#define GPIO_PUPDR_PUPDR7_0              (0x1U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPDR7_1              (0x2U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */\n\n#define GPIO_PUPDR_PUPDR8_Pos            (16U)\n#define GPIO_PUPDR_PUPDR8_Msk            (0x3U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk\n#define GPIO_PUPDR_PUPDR8_0              (0x1U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPDR8_1              (0x2U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */\n\n#define GPIO_PUPDR_PUPDR9_Pos            (18U)\n#define GPIO_PUPDR_PUPDR9_Msk            (0x3U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk\n#define GPIO_PUPDR_PUPDR9_0              (0x1U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPDR9_1              (0x2U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */\n\n#define GPIO_PUPDR_PUPDR10_Pos           (20U)\n#define GPIO_PUPDR_PUPDR10_Msk           (0x3U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk\n#define GPIO_PUPDR_PUPDR10_0             (0x1U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPDR10_1             (0x2U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */\n\n#define GPIO_PUPDR_PUPDR11_Pos           (22U)\n#define GPIO_PUPDR_PUPDR11_Msk           (0x3U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk\n#define GPIO_PUPDR_PUPDR11_0             (0x1U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPDR11_1             (0x2U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */\n\n#define GPIO_PUPDR_PUPDR12_Pos           (24U)\n#define GPIO_PUPDR_PUPDR12_Msk           (0x3U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk\n#define GPIO_PUPDR_PUPDR12_0             (0x1U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPDR12_1             (0x2U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */\n\n#define GPIO_PUPDR_PUPDR13_Pos           (26U)\n#define GPIO_PUPDR_PUPDR13_Msk           (0x3U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk\n#define GPIO_PUPDR_PUPDR13_0             (0x1U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPDR13_1             (0x2U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */\n\n#define GPIO_PUPDR_PUPDR14_Pos           (28U)\n#define GPIO_PUPDR_PUPDR14_Msk           (0x3U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk\n#define GPIO_PUPDR_PUPDR14_0             (0x1U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPDR14_1             (0x2U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */\n\n#define GPIO_PUPDR_PUPDR15_Pos           (30U)\n#define GPIO_PUPDR_PUPDR15_Msk           (0x3U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk\n#define GPIO_PUPDR_PUPDR15_0             (0x1U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPDR15_1             (0x2U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_IDR_0                   0x00000001U\n#define GPIO_IDR_IDR_1                   0x00000002U\n#define GPIO_IDR_IDR_2                   0x00000004U\n#define GPIO_IDR_IDR_3                   0x00000008U\n#define GPIO_IDR_IDR_4                   0x00000010U\n#define GPIO_IDR_IDR_5                   0x00000020U\n#define GPIO_IDR_IDR_6                   0x00000040U\n#define GPIO_IDR_IDR_7                   0x00000080U\n#define GPIO_IDR_IDR_8                   0x00000100U\n#define GPIO_IDR_IDR_9                   0x00000200U\n#define GPIO_IDR_IDR_10                  0x00000400U\n#define GPIO_IDR_IDR_11                  0x00000800U\n#define GPIO_IDR_IDR_12                  0x00001000U\n#define GPIO_IDR_IDR_13                  0x00002000U\n#define GPIO_IDR_IDR_14                  0x00004000U\n#define GPIO_IDR_IDR_15                  0x00008000U\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_ODR_0                   0x00000001U\n#define GPIO_ODR_ODR_1                   0x00000002U\n#define GPIO_ODR_ODR_2                   0x00000004U\n#define GPIO_ODR_ODR_3                   0x00000008U\n#define GPIO_ODR_ODR_4                   0x00000010U\n#define GPIO_ODR_ODR_5                   0x00000020U\n#define GPIO_ODR_ODR_6                   0x00000040U\n#define GPIO_ODR_ODR_7                   0x00000080U\n#define GPIO_ODR_ODR_8                   0x00000100U\n#define GPIO_ODR_ODR_9                   0x00000200U\n#define GPIO_ODR_ODR_10                  0x00000400U\n#define GPIO_ODR_ODR_11                  0x00000800U\n#define GPIO_ODR_ODR_12                  0x00001000U\n#define GPIO_ODR_ODR_13                  0x00002000U\n#define GPIO_ODR_ODR_14                  0x00004000U\n#define GPIO_ODR_ODR_15                  0x00008000U\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS_0                   0x00000001U\n#define GPIO_BSRR_BS_1                   0x00000002U\n#define GPIO_BSRR_BS_2                   0x00000004U\n#define GPIO_BSRR_BS_3                   0x00000008U\n#define GPIO_BSRR_BS_4                   0x00000010U\n#define GPIO_BSRR_BS_5                   0x00000020U\n#define GPIO_BSRR_BS_6                   0x00000040U\n#define GPIO_BSRR_BS_7                   0x00000080U\n#define GPIO_BSRR_BS_8                   0x00000100U\n#define GPIO_BSRR_BS_9                   0x00000200U\n#define GPIO_BSRR_BS_10                  0x00000400U\n#define GPIO_BSRR_BS_11                  0x00000800U\n#define GPIO_BSRR_BS_12                  0x00001000U\n#define GPIO_BSRR_BS_13                  0x00002000U\n#define GPIO_BSRR_BS_14                  0x00004000U\n#define GPIO_BSRR_BS_15                  0x00008000U\n#define GPIO_BSRR_BR_0                   0x00010000U\n#define GPIO_BSRR_BR_1                   0x00020000U\n#define GPIO_BSRR_BR_2                   0x00040000U\n#define GPIO_BSRR_BR_3                   0x00080000U\n#define GPIO_BSRR_BR_4                   0x00100000U\n#define GPIO_BSRR_BR_5                   0x00200000U\n#define GPIO_BSRR_BR_6                   0x00400000U\n#define GPIO_BSRR_BR_7                   0x00800000U\n#define GPIO_BSRR_BR_8                   0x01000000U\n#define GPIO_BSRR_BR_9                   0x02000000U\n#define GPIO_BSRR_BR_10                  0x04000000U\n#define GPIO_BSRR_BR_11                  0x08000000U\n#define GPIO_BSRR_BR_12                  0x10000000U\n#define GPIO_BSRR_BR_13                  0x20000000U\n#define GPIO_BSRR_BR_14                  0x40000000U\n#define GPIO_BSRR_BR_15                  0x80000000U\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFU << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFU << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFU << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFU << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFU << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFU << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFU << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFU << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFU << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFU << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFU << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFU << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFU << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFU << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFU << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFU << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0_Pos                 (0U)\n#define GPIO_BRR_BR0_Msk                 (0x1U << GPIO_BRR_BR0_Pos)            /*!< 0x00000001 */\n#define GPIO_BRR_BR0                     GPIO_BRR_BR0_Msk\n#define GPIO_BRR_BR1_Pos                 (1U)\n#define GPIO_BRR_BR1_Msk                 (0x1U << GPIO_BRR_BR1_Pos)            /*!< 0x00000002 */\n#define GPIO_BRR_BR1                     GPIO_BRR_BR1_Msk\n#define GPIO_BRR_BR2_Pos                 (2U)\n#define GPIO_BRR_BR2_Msk                 (0x1U << GPIO_BRR_BR2_Pos)            /*!< 0x00000004 */\n#define GPIO_BRR_BR2                     GPIO_BRR_BR2_Msk\n#define GPIO_BRR_BR3_Pos                 (3U)\n#define GPIO_BRR_BR3_Msk                 (0x1U << GPIO_BRR_BR3_Pos)            /*!< 0x00000008 */\n#define GPIO_BRR_BR3                     GPIO_BRR_BR3_Msk\n#define GPIO_BRR_BR4_Pos                 (4U)\n#define GPIO_BRR_BR4_Msk                 (0x1U << GPIO_BRR_BR4_Pos)            /*!< 0x00000010 */\n#define GPIO_BRR_BR4                     GPIO_BRR_BR4_Msk\n#define GPIO_BRR_BR5_Pos                 (5U)\n#define GPIO_BRR_BR5_Msk                 (0x1U << GPIO_BRR_BR5_Pos)            /*!< 0x00000020 */\n#define GPIO_BRR_BR5                     GPIO_BRR_BR5_Msk\n#define GPIO_BRR_BR6_Pos                 (6U)\n#define GPIO_BRR_BR6_Msk                 (0x1U << GPIO_BRR_BR6_Pos)            /*!< 0x00000040 */\n#define GPIO_BRR_BR6                     GPIO_BRR_BR6_Msk\n#define GPIO_BRR_BR7_Pos                 (7U)\n#define GPIO_BRR_BR7_Msk                 (0x1U << GPIO_BRR_BR7_Pos)            /*!< 0x00000080 */\n#define GPIO_BRR_BR7                     GPIO_BRR_BR7_Msk\n#define GPIO_BRR_BR8_Pos                 (8U)\n#define GPIO_BRR_BR8_Msk                 (0x1U << GPIO_BRR_BR8_Pos)            /*!< 0x00000100 */\n#define GPIO_BRR_BR8                     GPIO_BRR_BR8_Msk\n#define GPIO_BRR_BR9_Pos                 (9U)\n#define GPIO_BRR_BR9_Msk                 (0x1U << GPIO_BRR_BR9_Pos)            /*!< 0x00000200 */\n#define GPIO_BRR_BR9                     GPIO_BRR_BR9_Msk\n#define GPIO_BRR_BR10_Pos                (10U)\n#define GPIO_BRR_BR10_Msk                (0x1U << GPIO_BRR_BR10_Pos)           /*!< 0x00000400 */\n#define GPIO_BRR_BR10                    GPIO_BRR_BR10_Msk\n#define GPIO_BRR_BR11_Pos                (11U)\n#define GPIO_BRR_BR11_Msk                (0x1U << GPIO_BRR_BR11_Pos)           /*!< 0x00000800 */\n#define GPIO_BRR_BR11                    GPIO_BRR_BR11_Msk\n#define GPIO_BRR_BR12_Pos                (12U)\n#define GPIO_BRR_BR12_Msk                (0x1U << GPIO_BRR_BR12_Pos)           /*!< 0x00001000 */\n#define GPIO_BRR_BR12                    GPIO_BRR_BR12_Msk\n#define GPIO_BRR_BR13_Pos                (13U)\n#define GPIO_BRR_BR13_Msk                (0x1U << GPIO_BRR_BR13_Pos)           /*!< 0x00002000 */\n#define GPIO_BRR_BR13                    GPIO_BRR_BR13_Msk\n#define GPIO_BRR_BR14_Pos                (14U)\n#define GPIO_BRR_BR14_Msk                (0x1U << GPIO_BRR_BR14_Pos)           /*!< 0x00004000 */\n#define GPIO_BRR_BR14                    GPIO_BRR_BR14_Msk\n#define GPIO_BRR_BR15_Pos                (15U)\n#define GPIO_BRR_BR15_Msk                (0x1U << GPIO_BRR_BR15_Pos)           /*!< 0x00008000 */\n#define GPIO_BRR_BR15                    GPIO_BRR_BR15_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1U << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1U << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1U << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1U << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1U << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1U << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1U << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1U << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1U << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1U << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1U << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1U << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1U << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1U << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FU << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1U << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1U << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1U << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1U << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1U << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1U << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1U << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1U << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1U << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1U << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1U << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1U << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1U << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1U << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1U << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1U << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1U << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FU << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1U << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1U << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1U << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1U << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1U << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1U << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1U << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1U << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1U << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1U << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1U << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1U << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1U << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1U << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1U << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1U << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1U << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1U << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1U << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1U << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1U << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFU << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFU << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1U << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1U << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FU << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFU << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1U << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define FMPI2C_CR1_PE_Pos               (0U)\n#define FMPI2C_CR1_PE_Msk               (0x1U << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */\n#define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */\n#define FMPI2C_CR1_TXIE_Pos             (1U)\n#define FMPI2C_CR1_TXIE_Msk             (0x1U << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */\n#define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */\n#define FMPI2C_CR1_RXIE_Pos             (2U)\n#define FMPI2C_CR1_RXIE_Msk             (0x1U << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */\n#define FMPI2C_CR1_ADDRIE_Pos           (3U)\n#define FMPI2C_CR1_ADDRIE_Msk           (0x1U << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */\n#define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */\n#define FMPI2C_CR1_NACKIE_Pos           (4U)\n#define FMPI2C_CR1_NACKIE_Msk           (0x1U << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */\n#define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */\n#define FMPI2C_CR1_STOPIE_Pos           (5U)\n#define FMPI2C_CR1_STOPIE_Msk           (0x1U << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */\n#define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */\n#define FMPI2C_CR1_TCIE_Pos             (6U)\n#define FMPI2C_CR1_TCIE_Msk             (0x1U << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */\n#define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */\n#define FMPI2C_CR1_ERRIE_Pos            (7U)\n#define FMPI2C_CR1_ERRIE_Msk            (0x1U << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */\n#define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */\n#define FMPI2C_CR1_DFN_Pos              (8U)\n#define FMPI2C_CR1_DFN_Msk              (0xFU << FMPI2C_CR1_DFN_Pos)           /*!< 0x00000F00 */\n#define FMPI2C_CR1_DFN                  FMPI2C_CR1_DFN_Msk                     /*!< Digital noise filter                */\n#define FMPI2C_CR1_ANFOFF_Pos           (12U)\n#define FMPI2C_CR1_ANFOFF_Msk           (0x1U << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */\n#define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */\n#define FMPI2C_CR1_TXDMAEN_Pos          (14U)\n#define FMPI2C_CR1_TXDMAEN_Msk          (0x1U << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */\n#define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */\n#define FMPI2C_CR1_RXDMAEN_Pos          (15U)\n#define FMPI2C_CR1_RXDMAEN_Msk          (0x1U << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */\n#define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */\n#define FMPI2C_CR1_SBC_Pos              (16U)\n#define FMPI2C_CR1_SBC_Msk              (0x1U << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */\n#define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */\n#define FMPI2C_CR1_NOSTRETCH_Pos        (17U)\n#define FMPI2C_CR1_NOSTRETCH_Msk        (0x1U << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */\n#define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */\n#define FMPI2C_CR1_GCEN_Pos             (19U)\n#define FMPI2C_CR1_GCEN_Msk             (0x1U << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */\n#define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */\n#define FMPI2C_CR1_SMBHEN_Pos           (20U)\n#define FMPI2C_CR1_SMBHEN_Msk           (0x1U << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */\n#define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */\n#define FMPI2C_CR1_SMBDEN_Pos           (21U)\n#define FMPI2C_CR1_SMBDEN_Msk           (0x1U << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */\n#define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */\n#define FMPI2C_CR1_ALERTEN_Pos          (22U)\n#define FMPI2C_CR1_ALERTEN_Msk          (0x1U << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */\n#define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */\n#define FMPI2C_CR1_PECEN_Pos            (23U)\n#define FMPI2C_CR1_PECEN_Msk            (0x1U << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */\n#define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */\n\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define FMPI2C_CR2_SADD_Pos             (0U)\n#define FMPI2C_CR2_SADD_Msk             (0x3FFU << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */\n#define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */\n#define FMPI2C_CR2_RD_WRN_Pos           (10U)\n#define FMPI2C_CR2_RD_WRN_Msk           (0x1U << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */\n#define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */\n#define FMPI2C_CR2_ADD10_Pos            (11U)\n#define FMPI2C_CR2_ADD10_Msk            (0x1U << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */\n#define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */\n#define FMPI2C_CR2_HEAD10R_Pos          (12U)\n#define FMPI2C_CR2_HEAD10R_Msk          (0x1U << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */\n#define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */\n#define FMPI2C_CR2_START_Pos            (13U)\n#define FMPI2C_CR2_START_Msk            (0x1U << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */\n#define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */\n#define FMPI2C_CR2_STOP_Pos             (14U)\n#define FMPI2C_CR2_STOP_Msk             (0x1U << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */\n#define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */\n#define FMPI2C_CR2_NACK_Pos             (15U)\n#define FMPI2C_CR2_NACK_Msk             (0x1U << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */\n#define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */\n#define FMPI2C_CR2_NBYTES_Pos           (16U)\n#define FMPI2C_CR2_NBYTES_Msk           (0xFFU << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */\n#define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */\n#define FMPI2C_CR2_RELOAD_Pos           (24U)\n#define FMPI2C_CR2_RELOAD_Msk           (0x1U << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */\n#define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */\n#define FMPI2C_CR2_AUTOEND_Pos          (25U)\n#define FMPI2C_CR2_AUTOEND_Msk          (0x1U << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */\n#define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */\n#define FMPI2C_CR2_PECBYTE_Pos          (26U)\n#define FMPI2C_CR2_PECBYTE_Msk          (0x1U << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */\n#define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define FMPI2C_OAR1_OA1_Pos             (0U)\n#define FMPI2C_OAR1_OA1_Msk             (0x3FFU << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */\n#define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */\n#define FMPI2C_OAR1_OA1MODE_Pos         (10U)\n#define FMPI2C_OAR1_OA1MODE_Msk         (0x1U << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */\n#define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */\n#define FMPI2C_OAR1_OA1EN_Pos           (15U)\n#define FMPI2C_OAR1_OA1EN_Msk           (0x1U << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define FMPI2C_OAR2_OA2_Pos             (1U)\n#define FMPI2C_OAR2_OA2_Msk             (0x7FU << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */\n#define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */\n#define FMPI2C_OAR2_OA2MSK_Pos          (8U)\n#define FMPI2C_OAR2_OA2MSK_Msk          (0x7U << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */\n#define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */\n#define FMPI2C_OAR2_OA2EN_Pos           (15U)\n#define FMPI2C_OAR2_OA2EN_Msk           (0x1U << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define FMPI2C_TIMINGR_SCLL_Pos         (0U)\n#define FMPI2C_TIMINGR_SCLL_Msk         (0xFFU << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */\n#define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */\n#define FMPI2C_TIMINGR_SCLH_Pos         (8U)\n#define FMPI2C_TIMINGR_SCLH_Msk         (0xFFU << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */\n#define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */\n#define FMPI2C_TIMINGR_SDADEL_Pos       (16U)\n#define FMPI2C_TIMINGR_SDADEL_Msk       (0xFU << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */\n#define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */\n#define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)\n#define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */\n#define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */\n#define FMPI2C_TIMINGR_PRESC_Pos        (28U)\n#define FMPI2C_TIMINGR_PRESC_Msk        (0xFU << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */\n#define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\n#define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */\n#define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */\n#define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\n#define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\n#define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */\n#define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */\n#define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define FMPI2C_ISR_TXE_Pos              (0U)\n#define FMPI2C_ISR_TXE_Msk              (0x1U << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */\n#define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */\n#define FMPI2C_ISR_TXIS_Pos             (1U)\n#define FMPI2C_ISR_TXIS_Msk             (0x1U << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */\n#define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */\n#define FMPI2C_ISR_RXNE_Pos             (2U)\n#define FMPI2C_ISR_RXNE_Msk             (0x1U << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */\n#define FMPI2C_ISR_ADDR_Pos             (3U)\n#define FMPI2C_ISR_ADDR_Msk             (0x1U << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */\n#define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */\n#define FMPI2C_ISR_NACKF_Pos            (4U)\n#define FMPI2C_ISR_NACKF_Msk            (0x1U << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */\n#define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */\n#define FMPI2C_ISR_STOPF_Pos            (5U)\n#define FMPI2C_ISR_STOPF_Msk            (0x1U << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */\n#define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */\n#define FMPI2C_ISR_TC_Pos               (6U)\n#define FMPI2C_ISR_TC_Msk               (0x1U << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */\n#define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */\n#define FMPI2C_ISR_TCR_Pos              (7U)\n#define FMPI2C_ISR_TCR_Msk              (0x1U << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */\n#define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */\n#define FMPI2C_ISR_BERR_Pos             (8U)\n#define FMPI2C_ISR_BERR_Msk             (0x1U << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */\n#define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */\n#define FMPI2C_ISR_ARLO_Pos             (9U)\n#define FMPI2C_ISR_ARLO_Msk             (0x1U << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */\n#define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */\n#define FMPI2C_ISR_OVR_Pos              (10U)\n#define FMPI2C_ISR_OVR_Msk              (0x1U << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */\n#define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */\n#define FMPI2C_ISR_PECERR_Pos           (11U)\n#define FMPI2C_ISR_PECERR_Msk           (0x1U << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */\n#define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */\n#define FMPI2C_ISR_TIMEOUT_Pos          (12U)\n#define FMPI2C_ISR_TIMEOUT_Msk          (0x1U << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */\n#define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */\n#define FMPI2C_ISR_ALERT_Pos            (13U)\n#define FMPI2C_ISR_ALERT_Msk            (0x1U << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */\n#define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */\n#define FMPI2C_ISR_BUSY_Pos             (15U)\n#define FMPI2C_ISR_BUSY_Msk             (0x1U << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */\n#define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */\n#define FMPI2C_ISR_DIR_Pos              (16U)\n#define FMPI2C_ISR_DIR_Msk              (0x1U << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */\n#define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */\n#define FMPI2C_ISR_ADDCODE_Pos          (17U)\n#define FMPI2C_ISR_ADDCODE_Msk          (0x7FU << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */\n#define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define FMPI2C_ICR_ADDRCF_Pos           (3U)\n#define FMPI2C_ICR_ADDRCF_Msk           (0x1U << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */\n#define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */\n#define FMPI2C_ICR_NACKCF_Pos           (4U)\n#define FMPI2C_ICR_NACKCF_Msk           (0x1U << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */\n#define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */\n#define FMPI2C_ICR_STOPCF_Pos           (5U)\n#define FMPI2C_ICR_STOPCF_Msk           (0x1U << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */\n#define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */\n#define FMPI2C_ICR_BERRCF_Pos           (8U)\n#define FMPI2C_ICR_BERRCF_Msk           (0x1U << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */\n#define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */\n#define FMPI2C_ICR_ARLOCF_Pos           (9U)\n#define FMPI2C_ICR_ARLOCF_Msk           (0x1U << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */\n#define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */\n#define FMPI2C_ICR_OVRCF_Pos            (10U)\n#define FMPI2C_ICR_OVRCF_Msk            (0x1U << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */\n#define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */\n#define FMPI2C_ICR_PECCF_Pos            (11U)\n#define FMPI2C_ICR_PECCF_Msk            (0x1U << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */\n#define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */\n#define FMPI2C_ICR_TIMOUTCF_Pos         (12U)\n#define FMPI2C_ICR_TIMOUTCF_Msk         (0x1U << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */\n#define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */\n#define FMPI2C_ICR_ALERTCF_Pos          (13U)\n#define FMPI2C_ICR_ALERTCF_Msk          (0x1U << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */\n#define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define FMPI2C_PECR_PEC_Pos             (0U)\n#define FMPI2C_PECR_PEC_Msk             (0xFFU << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */\n#define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define FMPI2C_RXDR_RXDATA_Pos          (0U)\n#define FMPI2C_RXDR_RXDATA_Msk          (0xFFU << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define FMPI2C_TXDR_TXDATA_Pos          (0U)\n#define FMPI2C_TXDR_TXDATA_Msk          (0xFFU << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFU << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7U << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1U << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2U << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4U << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFU << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1U << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1U << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1U << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1U << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1U << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1U << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1U << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7U << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1U << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2U << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4U << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1U << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1U << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1U << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1U << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1U << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3U << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_FMSSR_Pos       (20U)\n#define PWR_CR_FMSSR_Msk       (0x1U << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */\n#define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */\n#define PWR_CR_FISSR_Pos       (21U)\n#define PWR_CR_FISSR_Msk       (0x1U << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */\n#define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */\n\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1U << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1U << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1U << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1U << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP_Pos       (8U)\n#define PWR_CSR_EWUP_Msk       (0x1U << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1U << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1U << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1U << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1U << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1U << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1U << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1U << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1U << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1U << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0x1FU << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */\n#define QUADSPI_CR_FTHRES_0              (0x01U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x02U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x04U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x08U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_FTHRES_4              (0x10U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1U << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1U << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1U << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1U << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1U << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1U << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1U << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFU << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\n#define QUADSPI_CR_PRESCALER_0           (0x01U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1U << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FU << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\n#define QUADSPI_DCR_FSIZE_0              (0x01U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1U << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1U << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1U << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1U << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1U << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1U << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FU << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_FLEVEL_0              (0x01U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1U << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1U << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1U << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1U << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */\n#define QUADSPI_CCR_IMODE_0              (0x1U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */\n#define QUADSPI_CCR_ADMODE_0             (0x1U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */\n#define QUADSPI_CCR_ADSIZE_0             (0x1U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */\n#define QUADSPI_CCR_ABMODE_0             (0x1U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */\n#define QUADSPI_CCR_ABSIZE_0             (0x1U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FU << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */\n#define QUADSPI_CCR_DCYC_0               (0x01U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */\n#define QUADSPI_CCR_DMODE_0              (0x1U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */\n#define QUADSPI_CCR_FMODE_0              (0x1U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1U << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1U << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1U << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1U << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1U << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FU << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFU << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01U << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02U << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04U << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08U << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10U << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20U << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40U << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80U << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1U << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1U << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1U << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1U << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1U << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1U << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1U << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1U << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FU << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1U << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFU << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n#define RCC_PLLCFGR_PLLR_Pos               (28U)\n#define RCC_PLLCFGR_PLLR_Msk               (0x7U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */\n#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                 (0x1U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLR_1                 (0x2U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLR_2                 (0x4U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3U << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1U << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2U << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3U << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1U << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2U << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFU << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7U << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FU << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3U << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1U << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2U << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3U << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1U << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2U << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1U << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1U << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1U << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1U << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1U << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1U << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1U << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1U << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1U << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1U << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1U << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1U << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1U << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1U << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1U << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1U << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1U << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1U << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1U << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1U << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1U << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1U << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1U << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1U << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)\n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1U << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1U << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1U << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1U << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1U << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1U << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1U << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1U << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_LPTIM1RST_Pos         (9U)\n#define RCC_APB1RSTR_LPTIM1RST_Msk         (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\n#define RCC_APB1RSTR_LPTIM1RST             RCC_APB1RSTR_LPTIM1RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1U << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1U << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1U << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1U << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1U << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1U << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)\n#define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1U << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1U << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_CAN3RST_Pos           (27U)\n#define RCC_APB1RSTR_CAN3RST_Msk           (0x1U << RCC_APB1RSTR_CAN3RST_Pos)  /*!< 0x08000000 */\n#define RCC_APB1RSTR_CAN3RST               RCC_APB1RSTR_CAN3RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1U << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n#define RCC_APB1RSTR_DACRST_Pos            (29U)\n#define RCC_APB1RSTR_DACRST_Msk            (0x1U << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk\n#define RCC_APB1RSTR_UART7RST_Pos          (30U)\n#define RCC_APB1RSTR_UART7RST_Msk          (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\n#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk\n#define RCC_APB1RSTR_UART8RST_Pos          (31U)\n#define RCC_APB1RSTR_UART8RST_Msk          (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\n#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1U << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1U << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_UART9RST_Pos          (6U)\n#define RCC_APB2RSTR_UART9RST_Msk          (0x1U << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */\n#define RCC_APB2RSTR_UART9RST              RCC_APB2RSTR_UART9RST_Msk\n#define RCC_APB2RSTR_UART10RST_Pos         (7U)\n#define RCC_APB2RSTR_UART10RST_Msk         (0x1U << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */\n#define RCC_APB2RSTR_UART10RST             RCC_APB2RSTR_UART10RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1U << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1U << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1U << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1U << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1U << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1U << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk\n#define RCC_APB2RSTR_SAI1RST_Pos           (22U)\n#define RCC_APB2RSTR_SAI1RST_Msk           (0x1U << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk\n#define RCC_APB2RSTR_DFSDM1RST_Pos         (24U)\n#define RCC_APB2RSTR_DFSDM1RST_Msk         (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB2RSTR_DFSDM1RST             RCC_APB2RSTR_DFSDM1RST_Msk\n#define RCC_APB2RSTR_DFSDM2RST_Pos         (25U)\n#define RCC_APB2RSTR_DFSDM2RST_Msk         (0x1U << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */\n#define RCC_APB2RSTR_DFSDM2RST             RCC_APB2RSTR_DFSDM2RST_Msk\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1U << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1U << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1U << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1U << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1U << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1U << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1U << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1U << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1U << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1U << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1U << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1U << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)\n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1U << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1U << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1U << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1U << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1U << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1U << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1U << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1U << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1U << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1U << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1U << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_LPTIM1EN_Pos           (9U)\n#define RCC_APB1ENR_LPTIM1EN_Msk           (0x1U << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */\n#define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk\n#define RCC_APB1ENR_RTCAPBEN_Pos           (10U)\n#define RCC_APB1ENR_RTCAPBEN_Msk           (0x1U << RCC_APB1ENR_RTCAPBEN_Pos)  /*!< 0x00000400 */\n#define RCC_APB1ENR_RTCAPBEN               RCC_APB1ENR_RTCAPBEN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1U << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1U << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1U << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1U << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_UART4EN_Pos            (19U)\n#define RCC_APB1ENR_UART4EN_Msk            (0x1U << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk\n#define RCC_APB1ENR_UART5EN_Pos            (20U)\n#define RCC_APB1ENR_UART5EN_Msk            (0x1U << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1U << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1U << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1U << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)\n#define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */\n#define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1U << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1U << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_CAN3EN_Pos             (27U)\n#define RCC_APB1ENR_CAN3EN_Msk             (0x1U << RCC_APB1ENR_CAN3EN_Pos)    /*!< 0x08000000 */\n#define RCC_APB1ENR_CAN3EN                 RCC_APB1ENR_CAN3EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1U << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n#define RCC_APB1ENR_DACEN_Pos              (29U)\n#define RCC_APB1ENR_DACEN_Msk              (0x1U << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk\n#define RCC_APB1ENR_UART7EN_Pos            (30U)\n#define RCC_APB1ENR_UART7EN_Msk            (0x1U << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */\n#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk\n#define RCC_APB1ENR_UART8EN_Pos            (31U)\n#define RCC_APB1ENR_UART8EN_Msk            (0x1U << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */\n#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1U << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1U << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1U << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1U << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_UART9EN_Pos            (6U)\n#define RCC_APB2ENR_UART9EN_Msk            (0x1U << RCC_APB2ENR_UART9EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB2ENR_UART9EN                RCC_APB2ENR_UART9EN_Msk\n#define RCC_APB2ENR_UART10EN_Pos           (7U)\n#define RCC_APB2ENR_UART10EN_Msk           (0x1U << RCC_APB2ENR_UART10EN_Pos)  /*!< 0x00000080 */\n#define RCC_APB2ENR_UART10EN               RCC_APB2ENR_UART10EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1U << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1U << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1U << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1U << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_EXTITEN_Pos            (15U)\n#define RCC_APB2ENR_EXTITEN_Msk            (0x1U << RCC_APB2ENR_EXTITEN_Pos)   /*!< 0x00008000 */\n#define RCC_APB2ENR_EXTITEN                RCC_APB2ENR_EXTITEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1U << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1U << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1U << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1U << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk\n#define RCC_APB2ENR_SAI1EN_Pos             (22U)\n#define RCC_APB2ENR_SAI1EN_Msk             (0x1U << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk\n#define RCC_APB2ENR_DFSDM1EN_Pos           (24U)\n#define RCC_APB2ENR_DFSDM1EN_Msk           (0x1U << RCC_APB2ENR_DFSDM1EN_Pos)  /*!< 0x01000000 */\n#define RCC_APB2ENR_DFSDM1EN               RCC_APB2ENR_DFSDM1EN_Msk\n#define RCC_APB2ENR_DFSDM2EN_Pos           (25U)\n#define RCC_APB2ENR_DFSDM2EN_Msk           (0x1U << RCC_APB2ENR_DFSDM2EN_Pos)  /*!< 0x02000000 */\n#define RCC_APB2ENR_DFSDM2EN               RCC_APB2ENR_DFSDM2EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)\n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_LPTIM1LPEN_Pos       (9U)\n#define RCC_APB1LPENR_LPTIM1LPEN_Msk       (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB1LPENR_LPTIM1LPEN           RCC_APB1LPENR_LPTIM1LPEN_Msk\n#define RCC_APB1LPENR_RTCAPBLPEN_Pos       (10U)\n#define RCC_APB1LPENR_RTCAPBLPEN_Msk       (0x1U << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB1LPENR_RTCAPBLPEN           RCC_APB1LPENR_RTCAPBLPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)\n#define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_CAN3LPEN_Pos         (27U)\n#define RCC_APB1LPENR_CAN3LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */\n#define RCC_APB1LPENR_CAN3LPEN             RCC_APB1LPENR_CAN3LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk\n#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)\n#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk\n#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)\n#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\n#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_UART9LPEN_Pos        (6U)\n#define RCC_APB2LPENR_UART9LPEN_Msk        (0x1U << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB2LPENR_UART9LPEN            RCC_APB2LPENR_UART9LPEN_Msk\n#define RCC_APB2LPENR_UART10LPEN_Pos       (7U)\n#define RCC_APB2LPENR_UART10LPEN_Msk       (0x1U << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB2LPENR_UART10LPEN           RCC_APB2LPENR_UART10LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_EXTITLPEN_Pos        (15U)\n#define RCC_APB2LPENR_EXTITLPEN_Msk        (0x1U << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB2LPENR_EXTITLPEN            RCC_APB2LPENR_EXTITLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk\n#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)\n#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos       (24U)\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk       (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB2LPENR_DFSDM1LPEN           RCC_APB2LPENR_DFSDM1LPEN_Msk\n#define RCC_APB2LPENR_DFSDM2LPEN_Pos       (25U)\n#define RCC_APB2LPENR_DFSDM2LPEN_Msk       (0x1U << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB2LPENR_DFSDM2LPEN           RCC_APB2LPENR_DFSDM2LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1U << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1U << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1U << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1U << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1U << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1U << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1U << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1U << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1U << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_PADRSTF_Pos                (26U)\n#define RCC_CSR_PADRSTF_Msk                (0x1U << RCC_CSR_PADRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PADRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1U << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1U << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_WDGRSTF_Pos                (29U)\n#define RCC_CSR_WDGRSTF_Msk                (0x1U << RCC_CSR_WDGRSTF_Pos)       /*!< 0x20000000 */\n#define RCC_CSR_WDGRSTF                    RCC_CSR_WDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1U << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1U << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFU << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFU << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1U << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1U << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)\n#define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */\n#define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk\n#define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */\n#define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */\n#define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */\n#define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */\n#define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */\n#define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */\n\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos       (22U)\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk       (0x1U << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */\n#define RCC_PLLI2SCFGR_PLLI2SSRC           RCC_PLLI2SCFGR_PLLI2SSRC_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n#define RCC_DCKCFGR_PLLI2SDIVR_Pos         (0U)\n#define RCC_DCKCFGR_PLLI2SDIVR_Msk         (0x1FU << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */\n#define RCC_DCKCFGR_PLLI2SDIVR             RCC_DCKCFGR_PLLI2SDIVR_Msk\n#define RCC_DCKCFGR_PLLI2SDIVR_0           (0x01U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */\n#define RCC_DCKCFGR_PLLI2SDIVR_1           (0x02U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */\n#define RCC_DCKCFGR_PLLI2SDIVR_2           (0x04U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */\n#define RCC_DCKCFGR_PLLI2SDIVR_3           (0x08U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */\n#define RCC_DCKCFGR_PLLI2SDIVR_4           (0x10U << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */\n\n#define RCC_DCKCFGR_PLLDIVR_Pos            (8U)\n#define RCC_DCKCFGR_PLLDIVR_Msk            (0x1FU << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00001F00 */\n#define RCC_DCKCFGR_PLLDIVR                RCC_DCKCFGR_PLLDIVR_Msk\n#define RCC_DCKCFGR_PLLDIVR_0              (0x01U << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000100 */\n#define RCC_DCKCFGR_PLLDIVR_1              (0x02U << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000200 */\n#define RCC_DCKCFGR_PLLDIVR_2              (0x04U << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000400 */\n#define RCC_DCKCFGR_PLLDIVR_3              (0x08U << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000800 */\n#define RCC_DCKCFGR_PLLDIVR_4              (0x10U << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00001000 */\n\n#define RCC_DCKCFGR_CKDFSDM2ASEL_Pos       (14U)\n#define RCC_DCKCFGR_CKDFSDM2ASEL_Msk       (0x1U << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */\n#define RCC_DCKCFGR_CKDFSDM2ASEL           RCC_DCKCFGR_CKDFSDM2ASEL_Msk\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos       (15U)\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk       (0x1U << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */\n#define RCC_DCKCFGR_CKDFSDM1ASEL           RCC_DCKCFGR_CKDFSDM1ASEL_Msk\n\n#define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)\n#define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */\n#define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk\n#define RCC_DCKCFGR_SAI1ASRC_0             (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */\n#define RCC_DCKCFGR_SAI1ASRC_1             (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */\n#define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)\n#define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */\n#define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk\n#define RCC_DCKCFGR_SAI1BSRC_0             (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */\n#define RCC_DCKCFGR_SAI1BSRC_1             (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1U << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n#define RCC_DCKCFGR_I2S1SRC_Pos            (25U)\n#define RCC_DCKCFGR_I2S1SRC_Msk            (0x3U << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */\n#define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk\n#define RCC_DCKCFGR_I2S1SRC_0              (0x1U << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */\n#define RCC_DCKCFGR_I2S1SRC_1              (0x2U << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */\n\n#define RCC_DCKCFGR_I2S2SRC_Pos            (27U)\n#define RCC_DCKCFGR_I2S2SRC_Msk            (0x3U << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */\n#define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk\n#define RCC_DCKCFGR_I2S2SRC_0              (0x1U << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */\n#define RCC_DCKCFGR_I2S2SRC_1              (0x2U << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL_Pos        (31U)\n#define RCC_DCKCFGR_CKDFSDM1SEL_Msk        (0x1U << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL            RCC_DCKCFGR_CKDFSDM1SEL_Msk\n\n/********************  Bit definition for RCC_CKGATENR register  ***************/\n#define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)\n#define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */\n#define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk\n#define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)\n#define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */\n#define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk\n#define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)\n#define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */\n#define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk\n#define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)\n#define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */\n#define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk\n#define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)\n#define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */\n#define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk\n#define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)\n#define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */\n#define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk\n#define RCC_CKGATENR_RCC_CKEN_Pos          (6U)\n#define RCC_CKGATENR_RCC_CKEN_Msk          (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */\n#define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk\n#define RCC_CKGATENR_RCC_EVTCTL_Pos        (7U)\n#define RCC_CKGATENR_RCC_EVTCTL_Msk        (0x1U << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */\n#define RCC_CKGATENR_RCC_EVTCTL            RCC_CKGATENR_RCC_EVTCTL_Msk\n\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\n#define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)\n#define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk\n#define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */\n#define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)\n#define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\n#define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk\n#define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)\n#define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */\n#define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk\n#define RCC_DCKCFGR2_LPTIM1SEL_Pos         (30U)\n#define RCC_DCKCFGR2_LPTIM1SEL_Msk         (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */\n#define RCC_DCKCFGR2_LPTIM1SEL             RCC_DCKCFGR2_LPTIM1SEL_Msk\n#define RCC_DCKCFGR2_LPTIM1SEL_0           (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */\n#define RCC_DCKCFGR2_LPTIM1SEL_1           (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1U << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3U << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1U << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2U << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFU << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1U << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2U << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4U << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8U << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7U << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1U << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2U << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4U << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFU << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1U << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2U << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4U << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8U << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7U << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1U << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2U << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4U << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFU << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1U << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2U << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4U << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8U << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFU << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1U << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2U << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4U << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8U << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFU << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1U << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2U << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4U << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8U << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7U << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1U << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2U << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4U << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1U << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFU << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1U << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2U << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4U << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8U << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3U << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1U << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2U << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFU << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1U << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2U << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4U << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8U << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1U << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3U << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1U << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2U << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1U << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1U << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BCK_Pos                (18U)\n#define RTC_CR_BCK_Msk                (0x1U << RTC_CR_BCK_Pos)                 /*!< 0x00040000 */\n#define RTC_CR_BCK                    RTC_CR_BCK_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1U << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1U << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1U << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1U << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1U << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1U << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1U << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1U << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1U << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1U << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1U << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1U << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1U << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1U << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1U << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1U << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1U << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1U << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1U << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1U << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1U << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1U << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1U << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1U << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1U << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1U << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1U << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1U << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1U << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1U << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1U << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FU << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFU << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFU << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1U << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FU << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1U << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1U << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3U << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1U << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2U << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFU << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1U << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2U << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4U << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8U << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1U << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1U << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3U << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1U << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2U << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFU << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1U << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2U << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4U << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8U << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1U << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFU << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1U << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFU << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1U << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1U << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3U << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1U << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2U << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFU << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1U << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2U << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4U << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8U << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1U << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1U << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3U << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1U << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2U << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFU << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1U << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2U << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4U << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8U << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1U << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFU << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1U << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFU << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFU << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFU << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1U << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1U << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3U << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1U << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2U << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFU << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1U << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2U << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4U << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8U << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7U << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1U << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2U << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4U << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFU << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1U << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2U << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4U << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8U << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7U << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1U << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2U << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4U << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFU << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1U << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2U << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4U << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8U << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7U << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1U << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2U << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4U << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1U << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFU << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1U << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2U << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4U << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8U << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3U << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1U << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2U << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFU << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1U << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2U << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4U << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8U << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFU << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1U << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1U << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1U << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFU << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001U << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002U << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004U << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008U << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010U << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020U << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040U << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080U << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100U << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1U << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMPINSEL_Pos       (16U)\n#define RTC_TAFCR_TAMPINSEL_Msk       (0x1U << RTC_TAFCR_TAMPINSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMPINSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1U << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1U << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1U << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1U << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1U << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1U << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFU << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFU << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFU << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFU << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFU << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFU << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFU << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFU << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFU << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFU << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFU << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFU << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFU << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFU << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFU << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFU << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFU << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFU << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFU << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFU << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFU << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFU << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFU << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFU << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)\n#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)\n#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)\n#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)\n#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)\n#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\n#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)\n#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)\n#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)\n#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\n#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)\n#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)\n#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)\n#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)\n#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x1U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */\n#define SAI_xCR1_MCKDIV_1          (0x2U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */\n#define SAI_xCR1_MCKDIV_2          (0x4U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */\n#define SAI_xCR1_MCKDIV_3          (0x8U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)\n#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)\n#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)\n#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)\n#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\n#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)\n#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)\n#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\n\n#define SAI_xCR2_COMP_Pos          (14U)\n#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)\n#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[1:0](Frame length)  */\n#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)\n#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[1:0] (Frame synchronization active level length)  */\n#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)\n#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\n#define SAI_xFRCR_FSPOL_Pos        (17U)\n#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)\n#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n/* Legacy defines */\n#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)\n#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\n#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\n#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\n#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)\n#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)\n#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)\n#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)\n#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)\n#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)\n#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)\n#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)\n#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\n#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  ******************/\n#define SAI_xDR_DATA_Pos           (0U)\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFU << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1U << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1U << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1U << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1U << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1U << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FU << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1U << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1U << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1U << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1U << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FU << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1U << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1U << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1U << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1U << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1U << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1U << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1U << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1U << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1U << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1U << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1U << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1U << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1U << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1U << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1U << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1U << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1U << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1U << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1U << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1U << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1U << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1U << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1U << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1U << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1U << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1U << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1U << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1U << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1U << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1U << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1U << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1U << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1U << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1U << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1U << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1U << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1U << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1U << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1U << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1U << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1U << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1U << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1U << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1U << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1U << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1U << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1U << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1U << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1U << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1U << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1U << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1U << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1U << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1U << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1U << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1U << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1U << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1U << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1U << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1U << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1U << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1U << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1U << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1U << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1U << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1U << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n/******************  Bit definition for SYSCFG_CFGR register  *****************/\n#define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)\n#define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */\n#define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)\n#define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */\n#define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */\n\n/******************  Bit definition for SYSCFG_CFGR2 register  *****************/\n#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)\n#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!<Core Lockup lock */\n#define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)\n#define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */\n#define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!<PVD Lock         */\n/******************  Bit definition for SYSCFG_MCHDLYCR register  *****************/\n#define SYSCFG_MCHDLYCR_BSCKSEL_Pos          (0U)\n#define SYSCFG_MCHDLYCR_BSCKSEL_Msk          (0x1U << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */\n#define SYSCFG_MCHDLYCR_BSCKSEL              SYSCFG_MCHDLYCR_BSCKSEL_Msk       /*!<Bitstream clock source selection                     */\n#define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos        (1U)\n#define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk        (0x1U << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */\n#define SYSCFG_MCHDLYCR_MCHDLY1EN            SYSCFG_MCHDLYCR_MCHDLY1EN_Msk     /*!<MCHDLY clock enable for DFSDM1                       */\n#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos      (2U)\n#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk      (0x1U << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */\n#define SYSCFG_MCHDLYCR_DFSDM1D0SEL          SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk   /*!<Source selection for DatIn0 for DFSDM1               */\n#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos      (3U)\n#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk      (0x1U << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */\n#define SYSCFG_MCHDLYCR_DFSDM1D2SEL          SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk   /*!<Source selection for DatIn2 for DFSDM1               */\n#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos    (4U)\n#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk    (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */\n#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL        SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */\n#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos    (5U)\n#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk    (0x1U << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */\n#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL        SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */\n#define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos        (6U)\n#define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk        (0x1U << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */\n#define SYSCFG_MCHDLYCR_DFSDM1CFG            SYSCFG_MCHDLYCR_DFSDM1CFG_Msk     /*!<Source selection for DFSDM1                          */\n#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos     (7U)\n#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk     (0x1U << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */\n#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL         SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk  /*!<Source selection for 1_CKOUT                         */\n#define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos        (8U)\n#define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk        (0x1U << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */\n#define SYSCFG_MCHDLYCR_MCHDLY2EN            SYSCFG_MCHDLYCR_MCHDLY2EN_Msk     /*!<MCHDLY clock enable for DFSDM2                       */\n#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos      (9U)\n#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk      (0x1U << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */\n#define SYSCFG_MCHDLYCR_DFSDM2D0SEL          SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk   /*!<Source selection for DatIn0 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos      (10U)\n#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk      (0x1U << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */\n#define SYSCFG_MCHDLYCR_DFSDM2D2SEL          SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk   /*!<Source selection for DatIn2 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos      (11U)\n#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk      (0x1U << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */\n#define SYSCFG_MCHDLYCR_DFSDM2D4SEL          SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk   /*!<Source selection for DatIn4 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos      (12U)\n#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk      (0x1U << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */\n#define SYSCFG_MCHDLYCR_DFSDM2D6SEL          SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk   /*!<Source selection for DatIn6 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos    (13U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk    (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL        SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos    (14U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk    (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL        SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos    (15U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk    (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL        SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2  */\n#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos    (16U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk    (0x1U << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL        SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */\n#define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos        (17U)\n#define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk        (0x1U << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CFG            SYSCFG_MCHDLYCR_DFSDM2CFG_Msk     /*!<Source selection for DFSDM2                          */\n#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos     (18U)\n#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk     (0x1U << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL         SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk  /*!<Source selection for 2_CKOUT                         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFU << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFU << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Low Power Timer (LPTIM)                            */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for LPTIM_ISR register  *******************/\n#define LPTIM_ISR_CMPM_Pos            (0U)\n#define LPTIM_ISR_CMPM_Msk            (0x1U << LPTIM_ISR_CMPM_Pos)             /*!< 0x00000001 */\n#define LPTIM_ISR_CMPM                LPTIM_ISR_CMPM_Msk                       /*!< Compare match                       */\n#define LPTIM_ISR_ARRM_Pos            (1U)\n#define LPTIM_ISR_ARRM_Msk            (0x1U << LPTIM_ISR_ARRM_Pos)             /*!< 0x00000002 */\n#define LPTIM_ISR_ARRM                LPTIM_ISR_ARRM_Msk                       /*!< Autoreload match                    */\n#define LPTIM_ISR_EXTTRIG_Pos         (2U)\n#define LPTIM_ISR_EXTTRIG_Msk         (0x1U << LPTIM_ISR_EXTTRIG_Pos)          /*!< 0x00000004 */\n#define LPTIM_ISR_EXTTRIG             LPTIM_ISR_EXTTRIG_Msk                    /*!< External trigger edge event         */\n#define LPTIM_ISR_CMPOK_Pos           (3U)\n#define LPTIM_ISR_CMPOK_Msk           (0x1U << LPTIM_ISR_CMPOK_Pos)            /*!< 0x00000008 */\n#define LPTIM_ISR_CMPOK               LPTIM_ISR_CMPOK_Msk                      /*!< Compare register update OK          */\n#define LPTIM_ISR_ARROK_Pos           (4U)\n#define LPTIM_ISR_ARROK_Msk           (0x1U << LPTIM_ISR_ARROK_Pos)            /*!< 0x00000010 */\n#define LPTIM_ISR_ARROK               LPTIM_ISR_ARROK_Msk                      /*!< Autoreload register update OK       */\n#define LPTIM_ISR_UP_Pos              (5U)\n#define LPTIM_ISR_UP_Msk              (0x1U << LPTIM_ISR_UP_Pos)               /*!< 0x00000020 */\n#define LPTIM_ISR_UP                  LPTIM_ISR_UP_Msk                         /*!< Counter direction change down to up */\n#define LPTIM_ISR_DOWN_Pos            (6U)\n#define LPTIM_ISR_DOWN_Msk            (0x1U << LPTIM_ISR_DOWN_Pos)             /*!< 0x00000040 */\n#define LPTIM_ISR_DOWN                LPTIM_ISR_DOWN_Msk                       /*!< Counter direction change up to down */\n\n/******************  Bit definition for LPTIM_ICR register  *******************/\n#define LPTIM_ICR_CMPMCF_Pos          (0U)\n#define LPTIM_ICR_CMPMCF_Msk          (0x1U << LPTIM_ICR_CMPMCF_Pos)           /*!< 0x00000001 */\n#define LPTIM_ICR_CMPMCF              LPTIM_ICR_CMPMCF_Msk                     /*!< Compare match Clear Flag                       */\n#define LPTIM_ICR_ARRMCF_Pos          (1U)\n#define LPTIM_ICR_ARRMCF_Msk          (0x1U << LPTIM_ICR_ARRMCF_Pos)           /*!< 0x00000002 */\n#define LPTIM_ICR_ARRMCF              LPTIM_ICR_ARRMCF_Msk                     /*!< Autoreload match Clear Flag                    */\n#define LPTIM_ICR_EXTTRIGCF_Pos       (2U)\n#define LPTIM_ICR_EXTTRIGCF_Msk       (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)        /*!< 0x00000004 */\n#define LPTIM_ICR_EXTTRIGCF           LPTIM_ICR_EXTTRIGCF_Msk                  /*!< External trigger edge event Clear Flag         */\n#define LPTIM_ICR_CMPOKCF_Pos         (3U)\n#define LPTIM_ICR_CMPOKCF_Msk         (0x1U << LPTIM_ICR_CMPOKCF_Pos)          /*!< 0x00000008 */\n#define LPTIM_ICR_CMPOKCF             LPTIM_ICR_CMPOKCF_Msk                    /*!< Compare register update OK Clear Flag          */\n#define LPTIM_ICR_ARROKCF_Pos         (4U)\n#define LPTIM_ICR_ARROKCF_Msk         (0x1U << LPTIM_ICR_ARROKCF_Pos)          /*!< 0x00000010 */\n#define LPTIM_ICR_ARROKCF             LPTIM_ICR_ARROKCF_Msk                    /*!< Autoreload register update OK Clear Flag       */\n#define LPTIM_ICR_UPCF_Pos            (5U)\n#define LPTIM_ICR_UPCF_Msk            (0x1U << LPTIM_ICR_UPCF_Pos)             /*!< 0x00000020 */\n#define LPTIM_ICR_UPCF                LPTIM_ICR_UPCF_Msk                       /*!< Counter direction change down to up Clear Flag */\n#define LPTIM_ICR_DOWNCF_Pos          (6U)\n#define LPTIM_ICR_DOWNCF_Msk          (0x1U << LPTIM_ICR_DOWNCF_Pos)           /*!< 0x00000040 */\n#define LPTIM_ICR_DOWNCF              LPTIM_ICR_DOWNCF_Msk                     /*!< Counter direction change up to down Clear Flag */\n\n/******************  Bit definition for LPTIM_IER register ********************/\n#define LPTIM_IER_CMPMIE_Pos          (0U)\n#define LPTIM_IER_CMPMIE_Msk          (0x1U << LPTIM_IER_CMPMIE_Pos)           /*!< 0x00000001 */\n#define LPTIM_IER_CMPMIE              LPTIM_IER_CMPMIE_Msk                     /*!< Compare match Interrupt Enable                       */\n#define LPTIM_IER_ARRMIE_Pos          (1U)\n#define LPTIM_IER_ARRMIE_Msk          (0x1U << LPTIM_IER_ARRMIE_Pos)           /*!< 0x00000002 */\n#define LPTIM_IER_ARRMIE              LPTIM_IER_ARRMIE_Msk                     /*!< Autoreload match Interrupt Enable                    */\n#define LPTIM_IER_EXTTRIGIE_Pos       (2U)\n#define LPTIM_IER_EXTTRIGIE_Msk       (0x1U << LPTIM_IER_EXTTRIGIE_Pos)        /*!< 0x00000004 */\n#define LPTIM_IER_EXTTRIGIE           LPTIM_IER_EXTTRIGIE_Msk                  /*!< External trigger edge event Interrupt Enable         */\n#define LPTIM_IER_CMPOKIE_Pos         (3U)\n#define LPTIM_IER_CMPOKIE_Msk         (0x1U << LPTIM_IER_CMPOKIE_Pos)          /*!< 0x00000008 */\n#define LPTIM_IER_CMPOKIE             LPTIM_IER_CMPOKIE_Msk                    /*!< Compare register update OK Interrupt Enable          */\n#define LPTIM_IER_ARROKIE_Pos         (4U)\n#define LPTIM_IER_ARROKIE_Msk         (0x1U << LPTIM_IER_ARROKIE_Pos)          /*!< 0x00000010 */\n#define LPTIM_IER_ARROKIE             LPTIM_IER_ARROKIE_Msk                    /*!< Autoreload register update OK Interrupt Enable       */\n#define LPTIM_IER_UPIE_Pos            (5U)\n#define LPTIM_IER_UPIE_Msk            (0x1U << LPTIM_IER_UPIE_Pos)             /*!< 0x00000020 */\n#define LPTIM_IER_UPIE                LPTIM_IER_UPIE_Msk                       /*!< Counter direction change down to up Interrupt Enable */\n#define LPTIM_IER_DOWNIE_Pos          (6U)\n#define LPTIM_IER_DOWNIE_Msk          (0x1U << LPTIM_IER_DOWNIE_Pos)           /*!< 0x00000040 */\n#define LPTIM_IER_DOWNIE              LPTIM_IER_DOWNIE_Msk                     /*!< Counter direction change up to down Interrupt Enable */\n\n/******************  Bit definition for LPTIM_CFGR register *******************/\n#define LPTIM_CFGR_CKSEL_Pos          (0U)\n#define LPTIM_CFGR_CKSEL_Msk          (0x1U << LPTIM_CFGR_CKSEL_Pos)           /*!< 0x00000001 */\n#define LPTIM_CFGR_CKSEL              LPTIM_CFGR_CKSEL_Msk                     /*!< Clock selector */\n\n#define LPTIM_CFGR_CKPOL_Pos          (1U)\n#define LPTIM_CFGR_CKPOL_Msk          (0x3U << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000006 */\n#define LPTIM_CFGR_CKPOL              LPTIM_CFGR_CKPOL_Msk                     /*!< CKPOL[1:0] bits (Clock polarity) */\n#define LPTIM_CFGR_CKPOL_0            (0x1U << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000002 */\n#define LPTIM_CFGR_CKPOL_1            (0x2U << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000004 */\n\n#define LPTIM_CFGR_CKFLT_Pos          (3U)\n#define LPTIM_CFGR_CKFLT_Msk          (0x3U << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000018 */\n#define LPTIM_CFGR_CKFLT              LPTIM_CFGR_CKFLT_Msk                     /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\n#define LPTIM_CFGR_CKFLT_0            (0x1U << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000008 */\n#define LPTIM_CFGR_CKFLT_1            (0x2U << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000010 */\n\n#define LPTIM_CFGR_TRGFLT_Pos         (6U)\n#define LPTIM_CFGR_TRGFLT_Msk         (0x3U << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x000000C0 */\n#define LPTIM_CFGR_TRGFLT             LPTIM_CFGR_TRGFLT_Msk                    /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\n#define LPTIM_CFGR_TRGFLT_0           (0x1U << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000040 */\n#define LPTIM_CFGR_TRGFLT_1           (0x2U << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000080 */\n\n#define LPTIM_CFGR_PRESC_Pos          (9U)\n#define LPTIM_CFGR_PRESC_Msk          (0x7U << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000E00 */\n#define LPTIM_CFGR_PRESC              LPTIM_CFGR_PRESC_Msk                     /*!< PRESC[2:0] bits (Clock prescaler) */\n#define LPTIM_CFGR_PRESC_0            (0x1U << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000200 */\n#define LPTIM_CFGR_PRESC_1            (0x2U << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000400 */\n#define LPTIM_CFGR_PRESC_2            (0x4U << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000800 */\n\n#define LPTIM_CFGR_TRIGSEL_Pos        (13U)\n#define LPTIM_CFGR_TRIGSEL_Msk        (0x7U << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x0000E000 */\n#define LPTIM_CFGR_TRIGSEL            LPTIM_CFGR_TRIGSEL_Msk                   /*!< TRIGSEL[2:0]] bits (Trigger selector) */\n#define LPTIM_CFGR_TRIGSEL_0          (0x1U << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00002000 */\n#define LPTIM_CFGR_TRIGSEL_1          (0x2U << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00004000 */\n#define LPTIM_CFGR_TRIGSEL_2          (0x4U << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00008000 */\n\n#define LPTIM_CFGR_TRIGEN_Pos         (17U)\n#define LPTIM_CFGR_TRIGEN_Msk         (0x3U << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00060000 */\n#define LPTIM_CFGR_TRIGEN             LPTIM_CFGR_TRIGEN_Msk                    /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\n#define LPTIM_CFGR_TRIGEN_0           (0x1U << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00020000 */\n#define LPTIM_CFGR_TRIGEN_1           (0x2U << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00040000 */\n\n#define LPTIM_CFGR_TIMOUT_Pos         (19U)\n#define LPTIM_CFGR_TIMOUT_Msk         (0x1U << LPTIM_CFGR_TIMOUT_Pos)          /*!< 0x00080000 */\n#define LPTIM_CFGR_TIMOUT             LPTIM_CFGR_TIMOUT_Msk                    /*!< Timout enable           */\n#define LPTIM_CFGR_WAVE_Pos           (20U)\n#define LPTIM_CFGR_WAVE_Msk           (0x1U << LPTIM_CFGR_WAVE_Pos)            /*!< 0x00100000 */\n#define LPTIM_CFGR_WAVE               LPTIM_CFGR_WAVE_Msk                      /*!< Waveform shape          */\n#define LPTIM_CFGR_WAVPOL_Pos         (21U)\n#define LPTIM_CFGR_WAVPOL_Msk         (0x1U << LPTIM_CFGR_WAVPOL_Pos)          /*!< 0x00200000 */\n#define LPTIM_CFGR_WAVPOL             LPTIM_CFGR_WAVPOL_Msk                    /*!< Waveform shape polarity */\n#define LPTIM_CFGR_PRELOAD_Pos        (22U)\n#define LPTIM_CFGR_PRELOAD_Msk        (0x1U << LPTIM_CFGR_PRELOAD_Pos)         /*!< 0x00400000 */\n#define LPTIM_CFGR_PRELOAD            LPTIM_CFGR_PRELOAD_Msk                   /*!< Reg update mode         */\n#define LPTIM_CFGR_COUNTMODE_Pos      (23U)\n#define LPTIM_CFGR_COUNTMODE_Msk      (0x1U << LPTIM_CFGR_COUNTMODE_Pos)       /*!< 0x00800000 */\n#define LPTIM_CFGR_COUNTMODE          LPTIM_CFGR_COUNTMODE_Msk                 /*!< Counter mode enable     */\n#define LPTIM_CFGR_ENC_Pos            (24U)\n#define LPTIM_CFGR_ENC_Msk            (0x1U << LPTIM_CFGR_ENC_Pos)             /*!< 0x01000000 */\n#define LPTIM_CFGR_ENC                LPTIM_CFGR_ENC_Msk                       /*!< Encoder mode enable     */\n\n/******************  Bit definition for LPTIM_CR register  ********************/\n#define LPTIM_CR_ENABLE_Pos           (0U)\n#define LPTIM_CR_ENABLE_Msk           (0x1U << LPTIM_CR_ENABLE_Pos)            /*!< 0x00000001 */\n#define LPTIM_CR_ENABLE               LPTIM_CR_ENABLE_Msk                      /*!< LPTIMer enable                 */\n#define LPTIM_CR_SNGSTRT_Pos          (1U)\n#define LPTIM_CR_SNGSTRT_Msk          (0x1U << LPTIM_CR_SNGSTRT_Pos)           /*!< 0x00000002 */\n#define LPTIM_CR_SNGSTRT              LPTIM_CR_SNGSTRT_Msk                     /*!< Timer start in single mode     */\n#define LPTIM_CR_CNTSTRT_Pos          (2U)\n#define LPTIM_CR_CNTSTRT_Msk          (0x1U << LPTIM_CR_CNTSTRT_Pos)           /*!< 0x00000004 */\n#define LPTIM_CR_CNTSTRT              LPTIM_CR_CNTSTRT_Msk                     /*!< Timer start in continuous mode */\n\n/******************  Bit definition for LPTIM_CMP register  *******************/\n#define LPTIM_CMP_CMP_Pos             (0U)\n#define LPTIM_CMP_CMP_Msk             (0xFFFFU << LPTIM_CMP_CMP_Pos)           /*!< 0x0000FFFF */\n#define LPTIM_CMP_CMP                 LPTIM_CMP_CMP_Msk                        /*!< Compare register     */\n\n/******************  Bit definition for LPTIM_ARR register  *******************/\n#define LPTIM_ARR_ARR_Pos             (0U)\n#define LPTIM_ARR_ARR_Msk             (0xFFFFU << LPTIM_ARR_ARR_Pos)           /*!< 0x0000FFFF */\n#define LPTIM_ARR_ARR                 LPTIM_ARR_ARR_Msk                        /*!< Auto reload register */\n\n/******************  Bit definition for LPTIM_CNT register  *******************/\n#define LPTIM_CNT_CNT_Pos             (0U)\n#define LPTIM_CNT_CNT_Msk             (0xFFFFU << LPTIM_CNT_CNT_Pos)           /*!< 0x0000FFFF */\n#define LPTIM_CNT_CNT                 LPTIM_CNT_CNT_Msk                        /*!< Counter register     */\n\n/******************  Bit definition for LPTIM_OR register  *******************/\n#define LPTIM_OR_LPT_IN1_RMP_Pos      (0U)\n#define LPTIM_OR_LPT_IN1_RMP_Msk      (0x3U << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000003 */\n#define LPTIM_OR_LPT_IN1_RMP          LPTIM_OR_LPT_IN1_RMP_Msk                 /*!< LPTIMER[1:0] bits (Remap selection) */\n#define LPTIM_OR_LPT_IN1_RMP_0        (0x1U << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000001 */\n#define LPTIM_OR_LPT_IN1_RMP_1        (0x2U << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000002 */\n#define LPTIM_OR_TIM1_ITR2_RMP_Pos    (2U)\n#define LPTIM_OR_TIM1_ITR2_RMP_Msk    (0x1U << LPTIM_OR_TIM1_ITR2_RMP_Pos)     /*!< 0x00000004 */\n#define LPTIM_OR_TIM1_ITR2_RMP        LPTIM_OR_TIM1_ITR2_RMP_Msk               /*!< Bit 2 */\n#define LPTIM_OR_TIM5_ITR1_RMP_Pos    (3U)\n#define LPTIM_OR_TIM5_ITR1_RMP_Msk    (0x1U << LPTIM_OR_TIM5_ITR1_RMP_Pos)     /*!< 0x00000008 */\n#define LPTIM_OR_TIM5_ITR1_RMP        LPTIM_OR_TIM5_ITR1_RMP_Msk               /*!< Bit 3 */\n#define LPTIM_OR_TIM9_ITR1_RMP_Pos    (4U)\n#define LPTIM_OR_TIM9_ITR1_RMP_Msk    (0x1U << LPTIM_OR_TIM9_ITR1_RMP_Pos)     /*!< 0x00000010 */\n#define LPTIM_OR_TIM9_ITR1_RMP        LPTIM_OR_TIM9_ITR1_RMP_Msk               /*!< Bit 4 */\n\n/* Legacy Defines */\n#define  LPTIM_OR_OR                           LPTIM_OR_LPT_IN1_RMP\n#define  LPTIM_OR_OR_0                         LPTIM_OR_LPT_IN1_RMP_0\n#define  LPTIM_OR_OR_1                         LPTIM_OR_LPT_IN1_RMP_1\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1U << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1U << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1U << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1U << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1U << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1U << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1U << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1U << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1U << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1U << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFU << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFU << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFU << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1U << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1U << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<PE Interrupt Enable                    */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1U << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFU << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01U << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02U << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04U << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08U << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10U << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20U << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40U << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80U << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos            (9U)\n#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */\n#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP                DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos             (27U)\n#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN3_STOP                 DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDETM_Pos              (23U)\n#define USB_OTG_GINTMSK_RSTDETM_Msk              (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDETM                  USB_OTG_GINTMSK_RSTDETM_Msk   /*!< Reset detected interrupt mask */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2) || \\\n                                       ((INSTANCE) == CAN3))\n\n/****************************** DFSDM Instances *******************************/\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\n                                                ((INSTANCE) == DFSDM1_Filter1) || \\\n                                                ((INSTANCE) == DFSDM2_Filter0) || \\\n                                                ((INSTANCE) == DFSDM2_Filter1) || \\\n                                                ((INSTANCE) == DFSDM2_Filter2) || \\\n                                                ((INSTANCE) == DFSDM2_Filter3))\n\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel3) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel3) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel4) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel5) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel6) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel7))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \\\n                                        ((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3) || \\\n                                        ((INSTANCE) == SPI4) || \\\n                                        ((INSTANCE) == SPI5))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI2)    || \\\n                                          ((INSTANCE) == SPI3)    || \\\n                                          ((INSTANCE) == I2S2ext) || \\\n                                          ((INSTANCE) == I2S3ext))\n\n/******************************* LPTIM Instances ******************************/\n#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4) || \\\n                                       ((INSTANCE) == SPI5))\n\n\n/*************************** SPI Extended Instances ***************************/\n#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \\\n                                           ((INSTANCE) == SPI2)    || \\\n                                           ((INSTANCE) == SPI3)    || \\\n                                           ((INSTANCE) == SPI4)    || \\\n                                           ((INSTANCE) == SPI5)    || \\\n                                           ((INSTANCE) == I2S2ext) || \\\n                                           ((INSTANCE) == I2S3ext))\n/******************************* SAI Instances ********************************/\n#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \\\n                                     ((PERIPH) == SAI1_Block_B))\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM6)   || \\\n                                         ((INSTANCE) == TIM7)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM9)   || \\\n                                         ((INSTANCE) == TIM12))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM1))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8)  || \\\n                                    ((INSTANCE) == UART9)  || \\\n                                    ((INSTANCE) == UART10))\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8)  || \\\n                                    ((INSTANCE) == UART9)  || \\\n                                    ((INSTANCE) == UART10))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n\n/***************************** FMPI2C Instances *******************************/\n#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)\n\n/****************************** QSPI Instances ********************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n/****************************** USB Instances ********************************/\n#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n\n#define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F413xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx.h\n  * @author  MCD Application Team\n  * @version V2.6.0\n  * @date    04-November-2016\n  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32F4xx device used in the target application\n  *              - To use or not the peripheral’s drivers in application code(i.e.\n  *                code will be based on direct access to peripheral’s registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx\n  * @{\n  */\n\n#ifndef __STM32F4xx_H\n#define __STM32F4xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined  (STM32F4)\n#define STM32F4\n#endif /* STM32F4 */\n\n/* Uncomment the line below according to the target STM32 device used in your\n   application\n  */\n/* #if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \\\n    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \\\n    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \\\n    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \\\n    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \\\n    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) */\n  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */\n  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */\n  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */\n  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */\n  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */\n  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */\n  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,\n                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */\n  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,\n                                   STM32F439NI, STM32F439IG and STM32F439II Devices */\n  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */\n  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */\n  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */\n  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */\n  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */\n  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */\n  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,\n                                   and STM32F446ZE Devices */\n  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,\n                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */\n  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG\n                                   and STM32F479NG Devices */\n  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */\n  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */\n  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */\n  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */\n  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,\n                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */\n  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */\n//#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS version number V2.6.0\n  */\n#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */\n#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */\n#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */\n#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\\\n                                         |(__STM32F4xx_CMSIS_VERSION))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n// #if defined(STM32F405xx)\n//   #include \"stm32f405xx.h\"\n// #elif defined(STM32F415xx)\n//   #include \"stm32f415xx.h\"\n// #elif defined(STM32F407xx)\n//   #include \"stm32f407xx.h\"\n// #elif defined(STM32F417xx)\n//   #include \"stm32f417xx.h\"\n// #elif defined(STM32F427xx)\n//   #include \"stm32f427xx.h\"\n// #elif defined(STM32F437xx)\n//   #include \"stm32f437xx.h\"\n// #elif defined(STM32F429xx)\n//   #include \"stm32f429xx.h\"\n// #elif defined(STM32F439xx)\n//   #include \"stm32f439xx.h\"\n// #elif defined(STM32F401xC)\n//   #include \"stm32f401xc.h\"\n// #elif defined(STM32F401xE)\n//   #include \"stm32f401xe.h\"\n// #elif defined(STM32F410Tx)\n//   #include \"stm32f410tx.h\"\n// #elif defined(STM32F410Cx)\n//   #include \"stm32f410cx.h\"\n// #elif defined(STM32F410Rx)\n//   #include \"stm32f410rx.h\"\n// #elif defined(STM32F411xE)\n//   #include \"stm32f411xe.h\"\n// #elif defined(STM32F446xx)\n//   #include \"stm32f446xx.h\"\n// #elif defined(STM32F469xx)\n//   #include \"stm32f469xx.h\"\n// #elif defined(STM32F479xx)\n//   #include \"stm32f479xx.h\"\n// #elif defined(STM32F412Cx)\n//   #include \"stm32f412cx.h\"\n// #elif defined(STM32F412Zx)\n//   #include \"stm32f412zx.h\"\n// #elif defined(STM32F412Rx)\n//   #include \"stm32f412rx.h\"\n// #elif defined(STM32F412Vx)\n//   #include \"stm32f412vx.h\"\n#if defined(STM32F413xx)\n  #include \"stm32f413xx.h\"\n #elif defined(STM32F423xx)\n  #include \"stm32f423xx.h\"\n#else\n #error \"Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0U,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0U,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  ERROR = 0U,\n  SUCCESS = !ERROR\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f4xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F4xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f4xx_hal_def.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_def.h\n  * @author  MCD Application Team\n  * @version V1.6.0\n  * @date    04-November-2016\n  * @brief   This file contains HAL common defines, enumeration, macros and\n  *          structures definitions.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_DEF\n#define __STM32F4xx_HAL_DEF\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n//#include \"Legacy/stm32_hal_legacy.h\"\n//#include <stdio.h>\n\n/* Exported types ------------------------------------------------------------*/\n\n/**\n  * @brief  HAL Status structures definition\n  */\ntypedef enum\n{\n  HAL_OK       = 0x00U,\n  HAL_ERROR    = 0x01U,\n  HAL_BUSY     = 0x02U,\n  HAL_TIMEOUT  = 0x03U\n} HAL_StatusTypeDef;\n\n/**\n  * @brief  HAL Lock structures definition\n  */\ntypedef enum\n{\n  HAL_UNLOCKED = 0x00U,\n  HAL_LOCKED   = 0x01U\n} HAL_LockTypeDef;\n\n/* Exported macro ------------------------------------------------------------*/\n#define HAL_MAX_DELAY      0xFFFFFFFFU\n\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)\n\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \\\n                        do{                                                      \\\n                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\\n                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \\\n                          } while(0)\n\n#define UNUSED(x) ((void)(x))\n\n/** @brief Reset the Handle's State field.\n  * @param __HANDLE__: specifies the Peripheral Handle.\n  * @note  This macro can be used for the following purpose:\n  *          - When the Handle is declared as local variable; before passing it as parameter\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro\n  *            to set to 0 the Handle's \"State\" field.\n  *            Otherwise, \"State\" field may have any random value and the first time the function\n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\n  * @retval None\n  */\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\n\n#if (USE_RTOS == 1)\n  /* Reserved for future use */\n  #error \"USE_RTOS should be 0 in the current HAL release\"\n#else\n  #define __HAL_LOCK(__HANDLE__)                                           \\\n                                do{                                        \\\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\n                                    {                                      \\\n                                       return HAL_BUSY;                    \\\n                                    }                                      \\\n                                    else                                   \\\n                                    {                                      \\\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\n                                    }                                      \\\n                                  }while (0)\n\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\n                                  do{                                       \\\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\n                                    }while (0)\n#endif /* USE_RTOS */\n\n#if  defined ( __GNUC__ )\n  #ifndef __weak\n    #define __weak   __attribute__((weak))\n  #endif /* __weak */\n  #ifndef __packed\n    #define __packed __attribute__((__packed__))\n  #endif /* __packed */\n#endif /* __GNUC__ */\n\n\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\n#if defined   (__GNUC__)        /* GNU Compiler */\n  #ifndef __ALIGN_END\n    #define __ALIGN_END    __attribute__ ((aligned (4)))\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN\n    #define __ALIGN_BEGIN\n  #endif /* __ALIGN_BEGIN */\n#else\n  #ifndef __ALIGN_END\n    #define __ALIGN_END\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN\n    #if defined   (__CC_ARM)      /* ARM Compiler */\n      #define __ALIGN_BEGIN    __align(4)\n    #elif defined (__ICCARM__)    /* IAR Compiler */\n      #define __ALIGN_BEGIN\n    #endif /* __CC_ARM */\n  #endif /* __ALIGN_BEGIN */\n#endif /* __GNUC__ */\n\n\n/**\n  * @brief  __RAM_FUNC definition\n  */\n#if defined ( __CC_ARM   )\n/* ARM Compiler\n   ------------\n   RAM functions are defined using the toolchain options.\n   Functions that are executed in RAM should reside in a separate source module.\n   Using the 'Options for File' dialog you can simply change the 'Code / Const'\n   area of a module to a memory space in physical RAM.\n   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\n   dialog.\n*/\n#define __RAM_FUNC HAL_StatusTypeDef\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n   RAM functions are defined using a specific toolchain keyword \"__ramfunc\".\n*/\n#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\n\n#elif defined   (  __GNUC__  )\n/* GNU Compiler\n   ------------\n  RAM functions are defined using a specific toolchain attribute\n   \"__attribute__((section(\".RamFunc\")))\".\n*/\n#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(\".RamFunc\")))\n\n#endif\n\n/**\n  * @brief  __NOINLINE definition\n  */\n#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\n/* ARM & GNUCompiler\n   ----------------\n*/\n#define __NOINLINE __attribute__ ( (noinline) )\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n*/\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ___STM32F4xx_HAL_DEF */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/stm32f4xx_hal_gpio_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_gpio_ex.h\n  * @author  MCD Application Team\n  * @version V1.6.0\n  * @date    04-November-2016\n  * @brief   Header file of GPIO HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_GPIO_EX_H\n#define __STM32F4xx_HAL_GPIO_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup GPIOEx GPIOEx\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\n  * @{\n  */\n\n/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\n  * @{\n  */\n\n/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/\n#if defined(STM32F429xx) || defined(STM32F439xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */\n#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */\n\n/**\n  * @brief   AF 11 selection\n  */\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 13 selection\n  */\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\n\n/**\n  * @brief   AF 14 selection\n  */\n#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F429xx || STM32F439xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F427xx/STM32F437xx------------------*/\n#if defined(STM32F427xx) || defined(STM32F437xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */\n#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */\n/** @brief  GPIO_Legacy\n  */\n#define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3    /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */\n\n/**\n  * @brief   AF 11 selection\n  */\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 13 selection\n  */\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F427xx || STM32F437xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F407xx/STM32F417xx------------------*/\n#if defined(STM32F407xx) || defined(STM32F417xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */\n\n/**\n  * @brief   AF 11 selection\n  */\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FSMC Alternate Function mapping                     */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 13 selection\n  */\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F407xx || STM32F417xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F405xx/STM32F415xx------------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FSMC Alternate Function mapping                     */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F405xx || STM32F415xx */\n\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------------- STM32F401xx------------------------*/\n#if defined(STM32F401xC) || defined(STM32F401xE)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping   */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping  */\n\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F401xC || STM32F401xE */\n/*----------------------------------------------------------------------------*/\n\n/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4/I2S4 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_USART3        ((uint8_t)0x08U)  /* USART3 Alternate Function mapping */\n#define GPIO_AF8_DFSDM1        ((uint8_t)0x08U)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF8_CAN1          ((uint8_t)0x08U)  /* CAN1 Alternate Function mapping   */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_DFSDM1        ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */\n#define GPIO_AF10_FMC           ((uint8_t)0x0AU)  /* FMC Alternate Function mapping    */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */\n#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FMC Alternate Function mapping   */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n#define GPIO_AF3_DFSDM2        ((uint8_t)0x03U)  /* DFSDM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping    */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4/I2S4 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */\n#define GPIO_AF6_DFSDM2        ((uint8_t)0x06U)  /* DFSDM2 Alternate Function mapping     */\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_SAI1          ((uint8_t)0x07U)  /* SAI1 Alternate Function mapping       */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n#define GPIO_AF7_DFSDM2        ((uint8_t)0x07U)  /* DFSDM2 Alternate Function mapping     */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_USART3        ((uint8_t)0x08U)  /* USART3 Alternate Function mapping */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\n#define GPIO_AF8_DFSDM1        ((uint8_t)0x08U)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF8_CAN1          ((uint8_t)0x08U)  /* CAN1 Alternate Function mapping   */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_SAI1          ((uint8_t)0x0AU)  /* SAI1 Alternate Function mapping   */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_DFSDM1        ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF10_DFSDM2        ((uint8_t)0x0AU)  /* DFSDM2 Alternate Function mapping */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */\n#define GPIO_AF10_FSMC          ((uint8_t)0x0AU)  /* FSMC Alternate Function mapping   */\n\n/**\n  * @brief   AF 11 selection\n  */\n#define GPIO_AF11_UART4         ((uint8_t)0x0BU)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF11_UART5         ((uint8_t)0x0BU)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF11_UART9         ((uint8_t)0x0BU)  /* UART9 Alternate Function mapping  */\n#define GPIO_AF11_UART10        ((uint8_t)0x0BU)  /* UART10 Alternate Function mapping */\n#define GPIO_AF11_CAN3          ((uint8_t)0x0BU)  /* CAN3 Alternate Function mapping   */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */\n#define GPIO_AF12_FSMC          ((uint8_t)0x0CU)  /* FMC Alternate Function mapping   */\n\n/**\n  * @brief   AF 14 selection\n  */\n#define GPIO_AF14_RNG           ((uint8_t)0x0EU)  /* RNG Alternate Function mapping  */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F413xx || STM32F423xx */\n\n/*---------------------------------------- STM32F411xx------------------------*/\n#if defined(STM32F411xE)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4/I2S4 Alternate Function mapping  */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09U)  /* I2C3 Alternate Function mapping  */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping  */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F411xE */\n\n/*---------------------------------------- STM32F410xx------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_LPTIM1        ((uint8_t)0x01U)  /* LPTIM1 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */\n#if defined(STM32F410Cx) || defined(STM32F410Rx)\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#endif /* STM32F410Cx || STM32F410Rx */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI1          ((uint8_t)0x06U)  /* SPI1 Alternate Function mapping  */\n#if defined(STM32F410Cx) || defined(STM32F410Rx)\n#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* I2S2 Alternate Function mapping       */\n#endif /* STM32F410Cx || STM32F410Rx */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06U)  /* SPI5/I2S5 Alternate Function mapping  */\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09U)  /* I2C2 Alternate Function mapping  */\n#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09U)  /* FMPI2C1 Alternate Function mapping */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/*---------------------------------------- STM32F446xx -----------------------*/\n#if defined(STM32F446xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n#define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping   */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04U)  /* FMPI2C1 Alternate Function mapping */\n#define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping  */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06U)  /* SPI2/I2S2 Alternate Function mapping  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06U)  /* SPI4 Alternate Function mapping       */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */\n#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2/I2S2 Alternate Function mapping  */\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIFRX Alternate Function mapping      */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPDIFRX Alternate Function mapping  */\n#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping  */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */\n#define GPIO_AF10_SAI2          ((uint8_t)0x0AU)  /* SAI2 Alternate Function mapping   */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping  */\n\n/**\n  * @brief   AF 11 selection\n  */\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 13 selection\n  */\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n\n#endif /* STM32F446xx */\n/*----------------------------------------------------------------------------*/\n\n/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/\n#if defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief   AF 0 selection\n  */\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00U)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\n\n/**\n  * @brief   AF 1 selection\n  */\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\n\n/**\n  * @brief   AF 2 selection\n  */\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\n\n/**\n  * @brief   AF 3 selection\n  */\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\n\n/**\n  * @brief   AF 4 selection\n  */\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\n\n/**\n  * @brief   AF 5 selection\n  */\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */\n#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05U)  /* I2S3ext_SD Alternate Function mapping  */\n\n/**\n  * @brief   AF 6 selection\n  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06U)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\n\n/**\n  * @brief   AF 7 selection\n  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07U)  /* I2S3ext_SD Alternate Function mapping */\n\n/**\n  * @brief   AF 8 selection\n  */\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\n\n/**\n  * @brief   AF 9 selection\n  */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09U)  /* QSPI Alternate Function mapping    */\n\n/**\n  * @brief   AF 10 selection\n  */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0AU)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0AU)  /* OTG_HS Alternate Function mapping */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0AU)  /* QSPI Alternate Function mapping   */\n\n/**\n  * @brief   AF 11 selection\n  */\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\n\n/**\n  * @brief   AF 12 selection\n  */\n#define GPIO_AF12_FMC           ((uint8_t)0x0CU)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0CU)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0CU)  /* SDIO Alternate Function mapping                     */\n\n/**\n  * @brief   AF 13 selection\n  */\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\n#define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */\n\n/**\n  * @brief   AF 14 selection\n  */\n#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */\n\n/**\n  * @brief   AF 15 selection\n  */\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\n\n#endif /* STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\n  * @{\n  */\n/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\n  * @{\n  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U :\\\n                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U :\\\n                                               ((__GPIOx__) == (GPIOH))? 7U :\\\n                                               ((__GPIOx__) == (GPIOI))? 8U :\\\n                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */\n\n#if defined(STM32F446xx) || defined(STM32F412Zx) ||defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  || defined(STM32F413xx) || defined(STM32F423xx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U : 7U)\n#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\n  * @{\n  */\n/*------------------------- STM32F429xx/STM32F439xx---------------------------*/\n#if defined(STM32F429xx) || defined(STM32F439xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\n                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \\\n                          ((AF) == GPIO_AF14_LTDC))\n\n#endif /* STM32F429xx || STM32F439xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F427xx/STM32F437xx------------------*/\n#if defined(STM32F427xx) || defined(STM32F437xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\n                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))\n\n#endif /* STM32F427xx || STM32F437xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F407xx/STM32F417xx------------------*/\n#if defined(STM32F407xx) || defined(STM32F417xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F407xx || STM32F417xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F405xx/STM32F415xx------------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \\\n                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F405xx || STM32F415xx */\n\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------------- STM32F401xx------------------------*/\n#if defined(STM32F401xC) || defined(STM32F401xE)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \\\n                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \\\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \\\n                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F401xC || STM32F401xE */\n/*----------------------------------------------------------------------------*/\n/*---------------------------------------- STM32F410xx------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/*---------------------------------------- STM32F411xx------------------------*/\n#if defined(STM32F411xE)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \\\n                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \\\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \\\n                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F411xE */\n/*----------------------------------------------------------------------------*/\n\n/*----------------------------------------------- STM32F446xx ----------------*/\n#if defined(STM32F446xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \\\n                          ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \\\n                          ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \\\n                          ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \\\n                          ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \\\n                          ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \\\n                          ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \\\n                          ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))\n\n#endif /* STM32F446xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------------------------------- STM32F469xx/STM32F479xx --------*/\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \\\n                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \\\n                          ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))\n\n#endif /* STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)\n#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------STM32F413xx/STM32F423xx-----------------------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 13U))\n#endif /* STM32F413xx || STM32F423xx */\n/*----------------------------------------------------------------------------*/\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_GPIO_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/system_stm32f2xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f2xx.h\n  * @author  MCD Application Team\n  * @version V2.1.2\n  * @date    29-June-2016\n  * @brief   CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.\n******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f2xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F2XX_H\n#define __SYSTEM_STM32F2XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32F2xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F2xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F2xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F2xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F2xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F2XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/inc/system_stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.h\n  * @author  MCD Application Team\n  * @version V2.6.0\n  * @date    04-November-2016\n  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F4XX_H\n#define __SYSTEM_STM32F4XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32F4xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F4xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F4XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/interrupt_handlers.h",
    "content": "// ********************* Bare interrupt handlers *********************\n// Only implemented the STM32F413 interrupts for now, the STM32F203 specific ones do not fall into the scope of SIL2\n\nvoid WWDG_IRQHandler(void) {handle_interrupt(WWDG_IRQn);}\nvoid PVD_IRQHandler(void) {handle_interrupt(PVD_IRQn);}\nvoid TAMP_STAMP_IRQHandler(void) {handle_interrupt(TAMP_STAMP_IRQn);}\nvoid RTC_WKUP_IRQHandler(void) {handle_interrupt(RTC_WKUP_IRQn);}\nvoid FLASH_IRQHandler(void) {handle_interrupt(FLASH_IRQn);}\nvoid RCC_IRQHandler(void) {handle_interrupt(RCC_IRQn);}\nvoid EXTI0_IRQHandler(void) {handle_interrupt(EXTI0_IRQn);}\nvoid EXTI1_IRQHandler(void) {handle_interrupt(EXTI1_IRQn);}\nvoid EXTI2_IRQHandler(void) {handle_interrupt(EXTI2_IRQn);}\nvoid EXTI3_IRQHandler(void) {handle_interrupt(EXTI3_IRQn);}\nvoid EXTI4_IRQHandler(void) {handle_interrupt(EXTI4_IRQn);}\nvoid DMA1_Stream0_IRQHandler(void) {handle_interrupt(DMA1_Stream0_IRQn);}\nvoid DMA1_Stream1_IRQHandler(void) {handle_interrupt(DMA1_Stream1_IRQn);}\nvoid DMA1_Stream2_IRQHandler(void) {handle_interrupt(DMA1_Stream2_IRQn);}\nvoid DMA1_Stream3_IRQHandler(void) {handle_interrupt(DMA1_Stream3_IRQn);}\nvoid DMA1_Stream4_IRQHandler(void) {handle_interrupt(DMA1_Stream4_IRQn);}\nvoid DMA1_Stream5_IRQHandler(void) {handle_interrupt(DMA1_Stream5_IRQn);}\nvoid DMA1_Stream6_IRQHandler(void) {handle_interrupt(DMA1_Stream6_IRQn);}\nvoid ADC_IRQHandler(void) {handle_interrupt(ADC_IRQn);}\nvoid CAN1_TX_IRQHandler(void) {handle_interrupt(CAN1_TX_IRQn);}\nvoid CAN1_RX0_IRQHandler(void) {handle_interrupt(CAN1_RX0_IRQn);}\nvoid CAN1_RX1_IRQHandler(void) {handle_interrupt(CAN1_RX1_IRQn);}\nvoid CAN1_SCE_IRQHandler(void) {handle_interrupt(CAN1_SCE_IRQn);}\nvoid EXTI9_5_IRQHandler(void) {handle_interrupt(EXTI9_5_IRQn);}\nvoid TIM1_BRK_TIM9_IRQHandler(void) {handle_interrupt(TIM1_BRK_TIM9_IRQn);}\nvoid TIM1_UP_TIM10_IRQHandler(void) {handle_interrupt(TIM1_UP_TIM10_IRQn);}\nvoid TIM1_TRG_COM_TIM11_IRQHandler(void) {handle_interrupt(TIM1_TRG_COM_TIM11_IRQn);}\nvoid TIM1_CC_IRQHandler(void) {handle_interrupt(TIM1_CC_IRQn);}\nvoid TIM2_IRQHandler(void) {handle_interrupt(TIM2_IRQn);}\nvoid TIM3_IRQHandler(void) {handle_interrupt(TIM3_IRQn);}\nvoid TIM4_IRQHandler(void) {handle_interrupt(TIM4_IRQn);}\nvoid I2C1_EV_IRQHandler(void) {handle_interrupt(I2C1_EV_IRQn);}\nvoid I2C1_ER_IRQHandler(void) {handle_interrupt(I2C1_ER_IRQn);}\nvoid I2C2_EV_IRQHandler(void) {handle_interrupt(I2C2_EV_IRQn);}\nvoid I2C2_ER_IRQHandler(void) {handle_interrupt(I2C2_ER_IRQn);}\nvoid SPI1_IRQHandler(void) {handle_interrupt(SPI1_IRQn);}\nvoid SPI2_IRQHandler(void) {handle_interrupt(SPI2_IRQn);}\nvoid USART1_IRQHandler(void) {handle_interrupt(USART1_IRQn);}\nvoid USART2_IRQHandler(void) {handle_interrupt(USART2_IRQn);}\nvoid USART3_IRQHandler(void) {handle_interrupt(USART3_IRQn);}\nvoid EXTI15_10_IRQHandler(void) {handle_interrupt(EXTI15_10_IRQn);}\nvoid RTC_Alarm_IRQHandler(void) {handle_interrupt(RTC_Alarm_IRQn);}\nvoid OTG_FS_WKUP_IRQHandler(void) {handle_interrupt(OTG_FS_WKUP_IRQn);}\nvoid TIM8_BRK_TIM12_IRQHandler(void) {handle_interrupt(TIM8_BRK_TIM12_IRQn);}\nvoid TIM8_UP_TIM13_IRQHandler(void) {handle_interrupt(TIM8_UP_TIM13_IRQn);}\nvoid TIM8_TRG_COM_TIM14_IRQHandler(void) {handle_interrupt(TIM8_TRG_COM_TIM14_IRQn);}\nvoid TIM8_CC_IRQHandler(void) {handle_interrupt(TIM8_CC_IRQn);}\nvoid DMA1_Stream7_IRQHandler(void) {handle_interrupt(DMA1_Stream7_IRQn);}\nvoid FSMC_IRQHandler(void) {handle_interrupt(FSMC_IRQn);}\nvoid SDIO_IRQHandler(void) {handle_interrupt(SDIO_IRQn);}\nvoid TIM5_IRQHandler(void) {handle_interrupt(TIM5_IRQn);}\nvoid SPI3_IRQHandler(void) {handle_interrupt(SPI3_IRQn);}\nvoid UART4_IRQHandler(void) {handle_interrupt(UART4_IRQn);}\nvoid UART5_IRQHandler(void) {handle_interrupt(UART5_IRQn);}\nvoid TIM6_DAC_IRQHandler(void) {handle_interrupt(TIM6_DAC_IRQn);}\nvoid TIM7_IRQHandler(void) {handle_interrupt(TIM7_IRQn);}\nvoid DMA2_Stream0_IRQHandler(void) {handle_interrupt(DMA2_Stream0_IRQn);}\nvoid DMA2_Stream1_IRQHandler(void) {handle_interrupt(DMA2_Stream1_IRQn);}\nvoid DMA2_Stream2_IRQHandler(void) {handle_interrupt(DMA2_Stream2_IRQn);}\nvoid DMA2_Stream3_IRQHandler(void) {handle_interrupt(DMA2_Stream3_IRQn);}\nvoid DMA2_Stream4_IRQHandler(void) {handle_interrupt(DMA2_Stream4_IRQn);}\nvoid CAN2_TX_IRQHandler(void) {handle_interrupt(CAN2_TX_IRQn);}\nvoid CAN2_RX0_IRQHandler(void) {handle_interrupt(CAN2_RX0_IRQn);}\nvoid CAN2_RX1_IRQHandler(void) {handle_interrupt(CAN2_RX1_IRQn);}\nvoid CAN2_SCE_IRQHandler(void) {handle_interrupt(CAN2_SCE_IRQn);}\nvoid OTG_FS_IRQHandler(void) {handle_interrupt(OTG_FS_IRQn);}\nvoid DMA2_Stream5_IRQHandler(void) {handle_interrupt(DMA2_Stream5_IRQn);}\nvoid DMA2_Stream6_IRQHandler(void) {handle_interrupt(DMA2_Stream6_IRQn);}\nvoid DMA2_Stream7_IRQHandler(void) {handle_interrupt(DMA2_Stream7_IRQn);}\nvoid USART6_IRQHandler(void) {handle_interrupt(USART6_IRQn);}\nvoid I2C3_EV_IRQHandler(void) {handle_interrupt(I2C3_EV_IRQn);}\nvoid I2C3_ER_IRQHandler(void) {handle_interrupt(I2C3_ER_IRQn);}\n#ifdef STM32F4\n  void DFSDM1_FLT0_IRQHandler(void) {handle_interrupt(DFSDM1_FLT0_IRQn);}\n  void DFSDM1_FLT1_IRQHandler(void) {handle_interrupt(DFSDM1_FLT1_IRQn);}\n  void CAN3_TX_IRQHandler(void) {handle_interrupt(CAN3_TX_IRQn);}\n  void CAN3_RX0_IRQHandler(void) {handle_interrupt(CAN3_RX0_IRQn);}\n  void CAN3_RX1_IRQHandler(void) {handle_interrupt(CAN3_RX1_IRQn);}\n  void CAN3_SCE_IRQHandler(void) {handle_interrupt(CAN3_SCE_IRQn);}\n  void RNG_IRQHandler(void) {handle_interrupt(RNG_IRQn);}\n  void FPU_IRQHandler(void) {handle_interrupt(FPU_IRQn);}\n  void UART7_IRQHandler(void) {handle_interrupt(UART7_IRQn);}\n  void UART8_IRQHandler(void) {handle_interrupt(UART8_IRQn);}\n  void SPI4_IRQHandler(void) {handle_interrupt(SPI4_IRQn);}\n  void SPI5_IRQHandler(void) {handle_interrupt(SPI5_IRQn);}\n  void SAI1_IRQHandler(void) {handle_interrupt(SAI1_IRQn);}\n  void UART9_IRQHandler(void) {handle_interrupt(UART9_IRQn);}\n  void UART10_IRQHandler(void) {handle_interrupt(UART10_IRQn);}\n  void QUADSPI_IRQHandler(void) {handle_interrupt(QUADSPI_IRQn);}\n  void FMPI2C1_EV_IRQHandler(void) {handle_interrupt(FMPI2C1_EV_IRQn);}\n  void FMPI2C1_ER_IRQHandler(void) {handle_interrupt(FMPI2C1_ER_IRQn);}\n  void LPTIM1_IRQHandler(void) {handle_interrupt(LPTIM1_IRQn);}\n  void DFSDM2_FLT0_IRQHandler(void) {handle_interrupt(DFSDM2_FLT0_IRQn);}\n  void DFSDM2_FLT1_IRQHandler(void) {handle_interrupt(DFSDM2_FLT1_IRQn);}\n  void DFSDM2_FLT2_IRQHandler(void) {handle_interrupt(DFSDM2_FLT2_IRQn);}\n  void DFSDM2_FLT3_IRQHandler(void) {handle_interrupt(DFSDM2_FLT3_IRQn);}\n#endif\n"
  },
  {
    "path": "panda/board/stm32fx/lladc.h",
    "content": "// ACCEL1 = ADC10\n// ACCEL2 = ADC11\n// VOLT_S = ADC12\n// CURR_S = ADC13\n\n#define ADCCHAN_ACCEL0 10\n#define ADCCHAN_ACCEL1 11\n#define ADCCHAN_VOLTAGE 12\n#define ADCCHAN_CURRENT 13\n\nvoid register_set(volatile uint32_t *addr, uint32_t val, uint32_t mask);\n\nvoid adc_init(void) {\n  register_set(&(ADC->CCR), ADC_CCR_TSVREFE | ADC_CCR_VBATE, 0xC30000U);\n  register_set(&(ADC1->CR2), ADC_CR2_ADON, 0xFF7F0F03U);\n  register_set(&(ADC1->SMPR1), ADC_SMPR1_SMP12 | ADC_SMPR1_SMP13, 0x7FFFFFFU);\n}\n\nuint32_t adc_get(unsigned int channel) {\n  // Select channel\n  register_set(&(ADC1->JSQR), (channel << 15U), 0x3FFFFFU);\n\n  // Start conversion\n  ADC1->SR &= ~(ADC_SR_JEOC);\n  ADC1->CR2 |= ADC_CR2_JSWSTART;\n  while (!(ADC1->SR & ADC_SR_JEOC));\n\n  return ADC1->JDR1;\n}\n\nuint32_t adc_get_voltage(void) {\n  // REVC has a 10, 1 (1/11) voltage divider\n  // Here is the calculation for the scale (s)\n  // ADCV = VIN_S * (1/11) * (4095/3.3)\n  // RETVAL = ADCV * s = VIN_S*1000\n  // s = 1000/((4095/3.3)*(1/11)) = 8.8623046875\n\n  // Avoid needing floating point math, so output in mV\n  return (adc_get(ADCCHAN_VOLTAGE) * 8862U) / 1000U;\n}\n"
  },
  {
    "path": "panda/board/stm32fx/llbxcan.h",
    "content": "// this is needed for 1 mbps support\n#define CAN_QUANTA 8U\n#define CAN_SEQ1 6 // roundf(quanta * 0.875f) - 1;\n#define CAN_SEQ2 1 // roundf(quanta * 0.125f);\n\n#define CAN_PCLK 24000U\n// 333 = 33.3 kbps\n// 5000 = 500 kbps\n#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))\n\n#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==CAN1) ? \"CAN1\" : (((CAN_DEV) == CAN2) ? \"CAN2\" : \"CAN3\"))\n\nvoid puts(const char *a);\n\nbool llcan_set_speed(CAN_TypeDef *CAN_obj, uint32_t speed, bool loopback, bool silent) {\n  bool ret = true;\n\n  // initialization mode\n  register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_INRQ, 0x180FFU);\n  uint32_t timeout_counter = 0U;\n  while((CAN_obj->MSR & CAN_MSR_INAK) != CAN_MSR_INAK){\n    // Delay for about 1ms\n    delay(10000);\n    timeout_counter++;\n\n    if(timeout_counter >= CAN_INIT_TIMEOUT_MS){\n      puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(\" set_speed timed out (1)!\\n\");\n      ret = false;\n      break;\n    }\n  }\n\n  if(ret){\n    // set time quanta from defines\n    register_set(&(CAN_obj->BTR), ((CAN_BTR_TS1_0 * (CAN_SEQ1-1)) |\n              (CAN_BTR_TS2_0 * (CAN_SEQ2-1)) |\n              (can_speed_to_prescaler(speed) - 1U)), 0xC37F03FFU);\n\n    // silent loopback mode for debugging\n    if (loopback) {\n      register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM | CAN_BTR_LBKM);\n    }\n    if (silent) {\n      register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM);\n    }\n\n    // reset\n    register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_ABOM, 0x180FFU);\n\n    timeout_counter = 0U;\n    while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {\n      // Delay for about 1ms\n      delay(10000);\n      timeout_counter++;\n\n      if(timeout_counter >= CAN_INIT_TIMEOUT_MS){\n        puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(\" set_speed timed out (2)!\\n\");\n        ret = false;\n        break;\n      }\n    }\n  }\n\n  return ret;\n}\n\nbool llcan_init(CAN_TypeDef *CAN_obj) {\n  bool ret = true;\n\n  // Enter init mode\n  register_set_bits(&(CAN_obj->FMR), CAN_FMR_FINIT);\n\n  // Wait for INAK bit to be set\n  uint32_t timeout_counter = 0U;\n  while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {\n    // Delay for about 1ms\n    delay(10000);\n    timeout_counter++;\n\n    if(timeout_counter >= CAN_INIT_TIMEOUT_MS){\n      puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(\" initialization timed out!\\n\");\n      ret = false;\n      break;\n    }\n  }\n\n  if(ret){\n    // no mask\n    // For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters.\n    CAN_obj->sFilterRegister[0].FR1 = 0U;\n    CAN_obj->sFilterRegister[0].FR2 = 0U;\n    CAN_obj->sFilterRegister[14].FR1 = 0U;\n    CAN_obj->sFilterRegister[14].FR2 = 0U;\n    CAN_obj->FA1R |= 1U | (1U << 14);\n\n    // Exit init mode, do not wait\n    register_clear_bits(&(CAN_obj->FMR), CAN_FMR_FINIT);\n\n    // enable certain CAN interrupts\n    register_set_bits(&(CAN_obj->IER), CAN_IER_TMEIE | CAN_IER_FMPIE0 |  CAN_IER_WKUIE);\n\n    if (CAN_obj == CAN1) {\n      NVIC_EnableIRQ(CAN1_TX_IRQn);\n      NVIC_EnableIRQ(CAN1_RX0_IRQn);\n      NVIC_EnableIRQ(CAN1_SCE_IRQn);\n    } else if (CAN_obj == CAN2) {\n      NVIC_EnableIRQ(CAN2_TX_IRQn);\n      NVIC_EnableIRQ(CAN2_RX0_IRQn);\n      NVIC_EnableIRQ(CAN2_SCE_IRQn);\n    #ifdef CAN3\n      } else if (CAN_obj == CAN3) {\n        NVIC_EnableIRQ(CAN3_TX_IRQn);\n        NVIC_EnableIRQ(CAN3_RX0_IRQn);\n        NVIC_EnableIRQ(CAN3_SCE_IRQn);\n    #endif\n    } else {\n      puts(\"Invalid CAN: initialization failed\\n\");\n    }\n  }\n  return ret;\n}\n\nvoid llcan_clear_send(CAN_TypeDef *CAN_obj) {\n  CAN_obj->TSR |= CAN_TSR_ABRQ0;\n  register_clear_bits(&(CAN_obj->MSR), CAN_MSR_ERRI);\n  // cppcheck-suppress selfAssignment ; needed to clear the register\n  CAN_obj->MSR = CAN_obj->MSR;\n}\n"
  },
  {
    "path": "panda/board/stm32fx/lldac.h",
    "content": "void dac_init(void) {\n  // No buffers required since we have an opamp\n  register_set(&(DAC->DHR12R1), 0U, 0xFFFU);\n  register_set(&(DAC->DHR12R2), 0U, 0xFFFU);\n  register_set(&(DAC->CR), DAC_CR_EN1 | DAC_CR_EN2, 0x3FFF3FFFU);\n}\n\nvoid dac_set(int channel, uint32_t value) {\n  if (channel == 0) {\n    register_set(&(DAC->DHR12R1), value, 0xFFFU);\n  } else if (channel == 1) {\n    register_set(&(DAC->DHR12R2), value, 0xFFFU);\n  } else {\n    puts(\"Failed to set DAC: invalid channel value: 0x\"); puth(value); puts(\"\\n\");\n  }\n}\n"
  },
  {
    "path": "panda/board/stm32fx/llfan.h",
    "content": "// TACH interrupt handler\nvoid EXTI2_IRQ_Handler(void) {\n    volatile unsigned int pr = EXTI->PR & (1U << 2);\n    if ((pr & (1U << 2)) != 0U) {\n        fan_tach_counter++;\n    }\n    EXTI->PR = (1U << 2);\n}\n\nvoid fan_init(void){\n    // 5000RPM * 4 tach edges / 60 seconds\n    REGISTER_INTERRUPT(EXTI2_IRQn, EXTI2_IRQ_Handler, 700U, FAULT_INTERRUPT_RATE_TACH)\n\n    // Init PWM speed control\n    pwm_init(TIM3, 3);\n\n    // Init TACH interrupt\n    register_set(&(SYSCFG->EXTICR[0]), SYSCFG_EXTICR1_EXTI2_PD, 0xF00U);\n    register_set_bits(&(EXTI->IMR), (1U << 2));\n    register_set_bits(&(EXTI->RTSR), (1U << 2));\n    register_set_bits(&(EXTI->FTSR), (1U << 2));\n    NVIC_EnableIRQ(EXTI2_IRQn);\n}\n"
  },
  {
    "path": "panda/board/stm32fx/llflash.h",
    "content": "bool flash_is_locked(void) {\n  return (FLASH->CR & FLASH_CR_LOCK);\n}\n\nvoid flash_unlock(void) {\n  FLASH->KEYR = 0x45670123;\n  FLASH->KEYR = 0xCDEF89AB;\n}\n\nbool flash_erase_sector(uint8_t sector, bool unlocked) {\n  // don't erase the bootloader(sector 0)\n  if (sector != 0 && sector < 12 && unlocked) {\n    FLASH->CR = (sector << 3) | FLASH_CR_SER;\n    FLASH->CR |= FLASH_CR_STRT;\n    while (FLASH->SR & FLASH_SR_BSY);\n    return true;\n  }\n  return false;\n}\n\nvoid flash_write_word(void *prog_ptr, uint32_t data) {\n  uint32_t *pp = prog_ptr;\n  FLASH->CR = FLASH_CR_PSIZE_1 | FLASH_CR_PG;\n  *pp = data;\n  while (FLASH->SR & FLASH_SR_BSY);\n}\n\nvoid flush_write_buffer(void) { }\n"
  },
  {
    "path": "panda/board/stm32fx/llrtc.h",
    "content": "#define RCC_BDCR_MASK (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL | RCC_BDCR_LSEMOD | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)\n\nvoid enable_bdomain_protection(void) {\n  register_clear_bits(&(PWR->CR), PWR_CR_DBP);\n}\n\nvoid disable_bdomain_protection(void) {\n  register_set_bits(&(PWR->CR), PWR_CR_DBP);\n}\n"
  },
  {
    "path": "panda/board/stm32fx/llspi.h",
    "content": "// IRQs: DMA2_Stream2, DMA2_Stream3, EXTI4\n\nvoid spi_init(void);\nint spi_cb_rx(uint8_t *data, int len, uint8_t *data_out);\n\n// end API\n\n#define SPI_BUF_SIZE 256\nuint8_t spi_buf[SPI_BUF_SIZE];\nint spi_buf_count = 0;\nint spi_total_count = 0;\n\nvoid spi_tx_dma(void *addr, int len) {\n  // disable DMA\n  register_clear_bits(&(SPI1->CR2), SPI_CR2_TXDMAEN);\n  register_clear_bits(&(DMA2_Stream3->CR), DMA_SxCR_EN);\n\n  // DMA2, stream 3, channel 3\n  register_set(&(DMA2_Stream3->M0AR), (uint32_t)addr, 0xFFFFFFFFU);\n  DMA2_Stream3->NDTR = len;\n  register_set(&(DMA2_Stream3->PAR), (uint32_t)&(SPI1->DR), 0xFFFFFFFFU);\n\n  // channel3, increment memory, memory -> periph, enable\n  register_set(&(DMA2_Stream3->CR), (DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_EN), 0x1E077EFEU);\n  delay(0);\n  register_set_bits(&(DMA2_Stream3->CR), DMA_SxCR_TCIE);\n\n  register_set_bits(&(SPI1->CR2), SPI_CR2_TXDMAEN);\n\n  // signal data is ready by driving low\n  // esp must be configured as input by this point\n  set_gpio_output(GPIOB, 0, 0);\n}\n\nvoid spi_rx_dma(void *addr, int len) {\n  // disable DMA\n  register_clear_bits(&(SPI1->CR2), SPI_CR2_RXDMAEN);\n  register_clear_bits(&(DMA2_Stream2->CR), DMA_SxCR_EN);\n\n  // drain the bus\n  volatile uint8_t dat = SPI1->DR;\n  (void)dat;\n\n  // DMA2, stream 2, channel 3\n  register_set(&(DMA2_Stream2->M0AR), (uint32_t)addr, 0xFFFFFFFFU);\n  DMA2_Stream2->NDTR = len;\n  register_set(&(DMA2_Stream2->PAR), (uint32_t)&(SPI1->DR), 0xFFFFFFFFU);\n\n  // channel3, increment memory, periph -> memory, enable\n  register_set(&(DMA2_Stream2->CR), (DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 | DMA_SxCR_MINC | DMA_SxCR_EN), 0x1E077EFEU);\n  delay(0);\n  register_set_bits(&(DMA2_Stream2->CR), DMA_SxCR_TCIE);\n\n  register_set_bits(&(SPI1->CR2), SPI_CR2_RXDMAEN);\n}\n\n// ***************************** SPI IRQs *****************************\n// can't go on the stack cause it's DMAed\nuint8_t spi_tx_buf[0x44];\n\n// SPI RX\nvoid DMA2_Stream2_IRQ_Handler(void) {\n  int *resp_len = (int*)spi_tx_buf;\n  (void)memset(spi_tx_buf, 0xaa, 0x44);\n  *resp_len = spi_cb_rx(spi_buf, 0x14, spi_tx_buf+4);\n  #ifdef DEBUG_SPI\n    puts(\"SPI write: \");\n    puth(*resp_len);\n    puts(\"\\n\");\n  #endif\n  spi_tx_dma(spi_tx_buf, *resp_len + 4);\n\n  // ack\n  DMA2->LIFCR = DMA_LIFCR_CTCIF2;\n}\n\n// SPI TX\nvoid DMA2_Stream3_IRQ_Handler(void) {\n  #ifdef DEBUG_SPI\n    puts(\"SPI handshake\\n\");\n  #endif\n\n  // reset handshake back to pull up\n  set_gpio_mode(GPIOB, 0, MODE_INPUT);\n  set_gpio_pullup(GPIOB, 0, PULL_UP);\n\n  // ack\n  DMA2->LIFCR = DMA_LIFCR_CTCIF3;\n}\n\nvoid EXTI4_IRQ_Handler(void) {\n  volatile unsigned int pr = EXTI->PR & (1U << 4);\n  #ifdef DEBUG_SPI\n    puts(\"exti4\\n\");\n  #endif\n  // SPI CS falling\n  if ((pr & (1U << 4)) != 0U) {\n    spi_total_count = 0;\n    spi_rx_dma(spi_buf, 0x14);\n  }\n  EXTI->PR = pr;\n}\n\n// ***************************** SPI init *****************************\nvoid spi_init(void) {\n  // Max SPI clock the ESP can produce is 80MHz. At buffer size of 256 bytes, that's a max of about 40k buffers per second\n  REGISTER_INTERRUPT(DMA2_Stream2_IRQn, DMA2_Stream2_IRQ_Handler, 50000U, FAULT_INTERRUPT_RATE_SPI_DMA)\n  REGISTER_INTERRUPT(DMA2_Stream3_IRQn, DMA2_Stream3_IRQ_Handler, 50000U, FAULT_INTERRUPT_RATE_SPI_DMA)\n  REGISTER_INTERRUPT(EXTI4_IRQn, EXTI4_IRQ_Handler, 50000U, FAULT_INTERRUPT_RATE_SPI_CS) // TODO: Figure out if this is a reasonable limit\n\n  //puts(\"SPI init\\n\");\n  register_set(&(SPI1->CR1), SPI_CR1_SPE, 0xFFFFU);\n\n  // enable SPI interrupts\n  //SPI1->CR2 = SPI_CR2_RXNEIE | SPI_CR2_ERRIE | SPI_CR2_TXEIE;\n  register_set(&(SPI1->CR2), SPI_CR2_RXNEIE, 0xF7U);\n\n  NVIC_EnableIRQ(DMA2_Stream2_IRQn);\n  NVIC_EnableIRQ(DMA2_Stream3_IRQn);\n  //NVIC_EnableIRQ(SPI1_IRQn);\n\n  // reset handshake back to pull up\n  set_gpio_mode(GPIOB, 0, MODE_INPUT);\n  set_gpio_pullup(GPIOB, 0, PULL_UP);\n\n  // setup interrupt on falling edge of SPI enable (on PA4)\n  register_set(&(SYSCFG->EXTICR[2]), SYSCFG_EXTICR2_EXTI4_PA, 0xFFFFU);\n  register_set_bits(&(EXTI->IMR), (1U << 4));\n  register_set_bits(&(EXTI->FTSR), (1U << 4));\n  NVIC_EnableIRQ(EXTI4_IRQn);\n}\n"
  },
  {
    "path": "panda/board/stm32fx/lluart.h",
    "content": "// ***************************** Interrupt handlers *****************************\n\nvoid uart_tx_ring(uart_ring *q){\n  ENTER_CRITICAL();\n  // Send out next byte of TX buffer\n  if (q->w_ptr_tx != q->r_ptr_tx) {\n    // Only send if transmit register is empty (aka last byte has been sent)\n    if ((q->uart->SR & USART_SR_TXE) != 0) {\n      q->uart->DR = q->elems_tx[q->r_ptr_tx];   // This clears TXE\n      q->r_ptr_tx = (q->r_ptr_tx + 1U) % q->tx_fifo_size;\n    }\n\n    // Enable TXE interrupt if there is still data to be sent\n    if(q->r_ptr_tx != q->w_ptr_tx){\n      q->uart->CR1 |= USART_CR1_TXEIE;\n    } else {\n      q->uart->CR1 &= ~USART_CR1_TXEIE;\n    }\n  }\n  EXIT_CRITICAL();\n}\n\nvoid uart_rx_ring(uart_ring *q){\n  // Do not read out directly if DMA enabled\n  if (q->dma_rx == false) {\n    ENTER_CRITICAL();\n\n    // Read out RX buffer\n    uint8_t c = q->uart->DR;  // This read after reading SR clears a bunch of interrupts\n\n    uint16_t next_w_ptr = (q->w_ptr_rx + 1U) % q->rx_fifo_size;\n    // Do not overwrite buffer data\n    if (next_w_ptr != q->r_ptr_rx) {\n      q->elems_rx[q->w_ptr_rx] = c;\n      q->w_ptr_rx = next_w_ptr;\n      if (q->callback != NULL) {\n        q->callback(q);\n      }\n    }\n\n    EXIT_CRITICAL();\n  }\n}\n\nvoid uart_send_break(uart_ring *u) {\n  while ((u->uart->CR1 & USART_CR1_SBK) != 0);\n  u->uart->CR1 |= USART_CR1_SBK;\n}\n\n// This function should be called on:\n// * Half-transfer DMA interrupt\n// * Full-transfer DMA interrupt\n// * UART IDLE detection\nuint32_t prev_w_index = 0;\nvoid dma_pointer_handler(uart_ring *q, uint32_t dma_ndtr) {\n  ENTER_CRITICAL();\n  uint32_t w_index = (q->rx_fifo_size - dma_ndtr);\n\n  // Check for new data\n  if (w_index != prev_w_index){\n    // Check for overflow\n    if (\n      ((prev_w_index < q->r_ptr_rx) && (q->r_ptr_rx <= w_index)) ||                               // No rollover\n      ((w_index < prev_w_index) && ((q->r_ptr_rx <= w_index) || (prev_w_index < q->r_ptr_rx)))    // Rollover\n    ){\n      // We lost data. Set the new read pointer to the oldest byte still available\n      q->r_ptr_rx = (w_index + 1U) % q->rx_fifo_size;\n    }\n\n    // Set write pointer\n    q->w_ptr_rx = w_index;\n  }\n\n  prev_w_index = w_index;\n  EXIT_CRITICAL();\n}\n\n// This read after reading SR clears all error interrupts. We don't want compiler warnings, nor optimizations\n#define UART_READ_DR(uart) volatile uint8_t t = (uart)->DR; UNUSED(t);\n\nvoid uart_interrupt_handler(uart_ring *q) {\n  ENTER_CRITICAL();\n\n  // Read UART status. This is also the first step necessary in clearing most interrupts\n  uint32_t status = q->uart->SR;\n\n  // If RXNE is set, perform a read. This clears RXNE, ORE, IDLE, NF and FE\n  if((status & USART_SR_RXNE) != 0U){\n    uart_rx_ring(q);\n  }\n\n  // Detect errors and clear them\n  uint32_t err = (status & USART_SR_ORE) | (status & USART_SR_NE) | (status & USART_SR_FE) | (status & USART_SR_PE);\n  if(err != 0U){\n    #ifdef DEBUG_UART\n      puts(\"Encountered UART error: \"); puth(err); puts(\"\\n\");\n    #endif\n    UART_READ_DR(q->uart)\n  }\n  // Send if necessary\n  uart_tx_ring(q);\n\n  // Run DMA pointer handler if the line is idle\n  if(q->dma_rx && (status & USART_SR_IDLE)){\n    // Reset IDLE flag\n    UART_READ_DR(q->uart)\n\n    if(q == &uart_ring_gps){\n      dma_pointer_handler(&uart_ring_gps, DMA2_Stream5->NDTR);\n    } else {\n      #ifdef DEBUG_UART\n        puts(\"No IDLE dma_pointer_handler implemented for this UART.\");\n      #endif\n    }\n  }\n\n  EXIT_CRITICAL();\n}\n\nvoid USART1_IRQ_Handler(void) { uart_interrupt_handler(&uart_ring_gps); }\nvoid USART2_IRQ_Handler(void) { uart_interrupt_handler(&uart_ring_debug); }\nvoid USART3_IRQ_Handler(void) { uart_interrupt_handler(&uart_ring_lin2); }\nvoid UART5_IRQ_Handler(void) { uart_interrupt_handler(&uart_ring_lin1); }\n\nvoid DMA2_Stream5_IRQ_Handler(void) {\n  ENTER_CRITICAL();\n\n  // Handle errors\n  if((DMA2->HISR & DMA_HISR_TEIF5) || (DMA2->HISR & DMA_HISR_DMEIF5) || (DMA2->HISR & DMA_HISR_FEIF5)){\n    #ifdef DEBUG_UART\n      puts(\"Encountered UART DMA error. Clearing and restarting DMA...\\n\");\n    #endif\n\n    // Clear flags\n    DMA2->HIFCR = DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5;\n\n    // Re-enable the DMA if necessary\n    DMA2_Stream5->CR |= DMA_SxCR_EN;\n  }\n\n  // Re-calculate write pointer and reset flags\n  dma_pointer_handler(&uart_ring_gps, DMA2_Stream5->NDTR);\n  DMA2->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5;\n\n  EXIT_CRITICAL();\n}\n\n// ***************************** Hardware setup *****************************\n\nvoid dma_rx_init(uart_ring *q) {\n  // Initialization is UART-dependent\n  if(q == &uart_ring_gps){\n    // DMA2, stream 5, channel 4\n\n    // Disable FIFO mode (enable direct)\n    DMA2_Stream5->FCR &= ~DMA_SxFCR_DMDIS;\n\n    // Setup addresses\n    DMA2_Stream5->PAR = (uint32_t)&(USART1->DR);    // Source\n    DMA2_Stream5->M0AR = (uint32_t)q->elems_rx;     // Destination\n    DMA2_Stream5->NDTR = q->rx_fifo_size;           // Number of bytes to copy\n\n    // Circular, Increment memory, byte size, periph -> memory, enable\n    // Transfer complete, half transfer, transfer error and direct mode error interrupt enable\n    DMA2_Stream5->CR = DMA_SxCR_CHSEL_2 | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_HTIE | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE | DMA_SxCR_EN;\n\n    // Enable DMA receiver in UART\n    q->uart->CR3 |= USART_CR3_DMAR;\n\n    // Enable UART IDLE interrupt\n    q->uart->CR1 |= USART_CR1_IDLEIE;\n\n    // Enable interrupt\n    NVIC_EnableIRQ(DMA2_Stream5_IRQn);\n  } else {\n    puts(\"Tried to initialize RX DMA for an unsupported UART\\n\");\n  }\n}\n\n#define __DIV(_PCLK_, _BAUD_)                    (((_PCLK_) * 25U) / (4U * (_BAUD_)))\n#define __DIVMANT(_PCLK_, _BAUD_)                (__DIV((_PCLK_), (_BAUD_)) / 100U)\n#define __DIVFRAQ(_PCLK_, _BAUD_)                ((((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)\n#define __USART_BRR(_PCLK_, _BAUD_)              ((__DIVMANT((_PCLK_), (_BAUD_)) << 4) | (__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))\n\nvoid uart_set_baud(USART_TypeDef *u, unsigned int baud) {\n  if (u == USART1) {\n    // USART1 is on APB2\n    u->BRR = __USART_BRR(48000000U, baud);\n  } else {\n    u->BRR = __USART_BRR(24000000U, baud);\n  }\n}\n\nvoid uart_init(uart_ring *q, int baud) {\n  // Register interrupts (max data rate: 115200 baud)\n  if(q->uart == USART1){\n    REGISTER_INTERRUPT(USART1_IRQn, USART1_IRQ_Handler, 150000U, FAULT_INTERRUPT_RATE_UART_1)\n  } else if (q->uart == USART2){\n    REGISTER_INTERRUPT(USART2_IRQn, USART2_IRQ_Handler, 150000U, FAULT_INTERRUPT_RATE_UART_2)\n  } else if (q->uart == USART3){\n    REGISTER_INTERRUPT(USART3_IRQn, USART3_IRQ_Handler, 150000U, FAULT_INTERRUPT_RATE_UART_3)\n  } else if (q->uart == UART5){\n    REGISTER_INTERRUPT(UART5_IRQn, UART5_IRQ_Handler, 150000U, FAULT_INTERRUPT_RATE_UART_5)\n  } else {\n    // UART not used. Skip registering interrupts\n  }\n  if(q->dma_rx){\n    REGISTER_INTERRUPT(DMA2_Stream5_IRQn, DMA2_Stream5_IRQ_Handler, 100U, FAULT_INTERRUPT_RATE_UART_DMA)   // Called twice per buffer\n  }\n\n  // Set baud and enable peripheral with TX and RX mode\n  uart_set_baud(q->uart, baud);\n  q->uart->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;\n  if ((q->uart == USART2) || (q->uart == USART3) || (q->uart == UART5)) {\n    q->uart->CR1 |= USART_CR1_RXNEIE;\n  }\n\n  // Enable UART interrupts\n  if(q->uart == USART1){\n    NVIC_EnableIRQ(USART1_IRQn);\n  } else if (q->uart == USART2){\n    NVIC_EnableIRQ(USART2_IRQn);\n  } else if (q->uart == USART3){\n    NVIC_EnableIRQ(USART3_IRQn);\n  } else if (q->uart == UART5){\n    NVIC_EnableIRQ(UART5_IRQn);\n  } else {\n    // UART not used. Skip enabling interrupts\n  }\n\n  // Initialise RX DMA if used\n  if(q->dma_rx){\n    dma_rx_init(q);\n  }\n}\n"
  },
  {
    "path": "panda/board/stm32fx/llusb.h",
    "content": "typedef struct\n{\n  __IO uint32_t HPRT;\n}\nUSB_OTG_HostPortTypeDef;\n\nUSB_OTG_GlobalTypeDef *USBx = USB_OTG_FS;\n\n#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t)USBx + USB_OTG_HOST_BASE))\n#define USBx_HOST_PORT  ((USB_OTG_HostPortTypeDef *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE))\n#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t)USBx + USB_OTG_DEVICE_BASE))\n#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\n#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\n#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))\n#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)\n\n#define USBD_FS_TRDT_VALUE           5U\n#define USB_OTG_SPEED_FULL 3\n\n\nvoid usb_irqhandler(void);\n\nvoid OTG_FS_IRQ_Handler(void) {\n  NVIC_DisableIRQ(OTG_FS_IRQn);\n  //__disable_irq();\n  usb_irqhandler();\n  //__enable_irq();\n  NVIC_EnableIRQ(OTG_FS_IRQn);\n}\n\nvoid usb_init(void) {\n  REGISTER_INTERRUPT(OTG_FS_IRQn, OTG_FS_IRQ_Handler, 1500000U, FAULT_INTERRUPT_RATE_USB) //TODO: Find out a better rate limit for USB. Now it's the 1.5MB/s rate\n\n  // full speed PHY, do reset and remove power down\n  /*puth(USBx->GRSTCTL);\n  puts(\" resetting PHY\\n\");*/\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);\n  //puts(\"AHB idle\\n\");\n\n  // reset PHY here\n  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\n  //puts(\"reset done\\n\");\n\n  // internal PHY, force device mode\n  USBx->GUSBCFG = USB_OTG_GUSBCFG_PHYSEL | USB_OTG_GUSBCFG_FDMOD;\n\n  // slowest timings\n  USBx->GUSBCFG |= ((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\n\n  // power up the PHY\n#ifdef STM32F4\n  USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;\n\n  //USBx->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_SDEN |USB_OTG_GCCFG_PDEN | USB_OTG_GCCFG_DCDEN;\n\n  /* B-peripheral session valid override enable*/\n  USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\n  USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\n#else\n  USBx->GCCFG = USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS;\n#endif\n\n  // be a device, slowest timings\n  //USBx->GUSBCFG = USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL | USB_OTG_GUSBCFG_TRDT | USB_OTG_GUSBCFG_TOCAL;\n  //USBx->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\n  //USBx->GUSBCFG = USB_OTG_GUSBCFG_PHYSEL | USB_OTG_GUSBCFG_TRDT | USB_OTG_GUSBCFG_TOCAL;\n\n  // **** for debugging, doesn't seem to work ****\n  //USBx->GUSBCFG |= USB_OTG_GUSBCFG_CTXPKT;\n\n  // reset PHY clock\n  USBx_PCGCCTL = 0;\n\n  // enable the fancy OTG things\n  // DCFG_FRAME_INTERVAL_80 is 0\n  //USBx->GUSBCFG |= USB_OTG_GUSBCFG_HNPCAP | USB_OTG_GUSBCFG_SRPCAP;\n  USBx_DEVICE->DCFG |= USB_OTG_SPEED_FULL | USB_OTG_DCFG_NZLSOHSK;\n\n  //USBx_DEVICE->DCFG = USB_OTG_DCFG_NZLSOHSK | USB_OTG_DCFG_DSPD;\n  //USBx_DEVICE->DCFG = USB_OTG_DCFG_DSPD;\n\n  // clear pending interrupts\n  USBx->GINTSTS = 0xBFFFFFFFU;\n\n  // setup USB interrupts\n  // all interrupts except TXFIFO EMPTY\n  //USBx->GINTMSK = 0xFFFFFFFF & ~(USB_OTG_GINTMSK_NPTXFEM | USB_OTG_GINTMSK_PTXFEM | USB_OTG_GINTSTS_SOF | USB_OTG_GINTSTS_EOPF);\n  //USBx->GINTMSK = 0xFFFFFFFF & ~(USB_OTG_GINTMSK_NPTXFEM | USB_OTG_GINTMSK_PTXFEM);\n  USBx->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_OTGINT |\n                  USB_OTG_GINTMSK_RXFLVLM | USB_OTG_GINTMSK_GONAKEFFM | USB_OTG_GINTMSK_GINAKEFFM |\n                  USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_USBSUSPM |\n                  USB_OTG_GINTMSK_CIDSCHGM | USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_MMISM | USB_OTG_GINTMSK_EOPFM;\n\n  USBx->GAHBCFG = USB_OTG_GAHBCFG_GINT;\n\n  // DCTL startup value is 2 on new chip, 0 on old chip\n  USBx_DEVICE->DCTL = 0;\n\n  // enable the IRQ\n  NVIC_EnableIRQ(OTG_FS_IRQn);\n}\n"
  },
  {
    "path": "panda/board/stm32fx/peripherals.h",
    "content": "void gpio_usb_init(void) {\n  // A11,A12: USB\n  set_gpio_alternate(GPIOA, 11, GPIO_AF10_OTG_FS);\n  set_gpio_alternate(GPIOA, 12, GPIO_AF10_OTG_FS);\n  GPIOA->OSPEEDR = GPIO_OSPEEDER_OSPEEDR11 | GPIO_OSPEEDER_OSPEEDR12;\n}\n\nvoid gpio_usart2_init(void) {\n  // A2,A3: USART 2 for debugging\n  set_gpio_alternate(GPIOA, 2, GPIO_AF7_USART2);\n  set_gpio_alternate(GPIOA, 3, GPIO_AF7_USART2);\n}\n\n// Common GPIO initialization\nvoid common_init_gpio(void) {\n  // TODO: Is this block actually doing something???\n  // pull low to hold ESP in reset??\n  // enable OTG out tied to ground\n  GPIOA->ODR = 0;\n  GPIOB->ODR = 0;\n  GPIOA->PUPDR = 0;\n  GPIOB->AFR[0] = 0;\n  GPIOB->AFR[1] = 0;\n\n  // C2: Voltage sense line\n  set_gpio_mode(GPIOC, 2, MODE_ANALOG);\n\n  gpio_usb_init();\n\n  // A9,A10: USART 1 for talking to the GPS\n  set_gpio_alternate(GPIOA, 9, GPIO_AF7_USART1);\n  set_gpio_alternate(GPIOA, 10, GPIO_AF7_USART1);\n\n   // B8,B9: CAN 1\n  #ifdef STM32F4\n    set_gpio_alternate(GPIOB, 8, GPIO_AF8_CAN1);\n    set_gpio_alternate(GPIOB, 9, GPIO_AF8_CAN1);\n  #else\n    set_gpio_alternate(GPIOB, 8, GPIO_AF9_CAN1);\n    set_gpio_alternate(GPIOB, 9, GPIO_AF9_CAN1);\n  #endif\n}\n\nvoid flasher_peripherals_init(void) {\n  RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;\n  RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;\n  RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;\n  RCC->APB1ENR |= RCC_APB1ENR_USART2EN;\n}\n\n// Peripheral initialization\nvoid peripherals_init(void) {\n  // enable GPIOB, UART2, CAN, USB clock\n  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;\n  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;\n  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;\n  RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN;\n\n  RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;\n  RCC->APB1ENR |= RCC_APB1ENR_USART2EN;\n  RCC->APB1ENR |= RCC_APB1ENR_USART3EN;\n  #ifdef PANDA\n    RCC->APB1ENR |= RCC_APB1ENR_UART5EN;\n  #endif\n  RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;\n  RCC->APB1ENR |= RCC_APB1ENR_CAN2EN;\n  #ifdef CAN3\n    RCC->APB1ENR |= RCC_APB1ENR_CAN3EN;\n  #endif\n  RCC->APB1ENR |= RCC_APB1ENR_DACEN;\n  RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;  // main counter\n  RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;  // pedal and fan PWM\n  RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;  // IR PWM\n  RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;  // k-line init\n  RCC->APB1ENR |= RCC_APB1ENR_TIM6EN;  // interrupt timer\n  RCC->APB1ENR |= RCC_APB1ENR_TIM12EN; // gmlan_alt\n  RCC->APB1ENR |= RCC_APB1ENR_PWREN;   // for RTC config\n  RCC->APB2ENR |= RCC_APB2ENR_USART1EN;\n  RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;\n  RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;  // clock source timer\n  RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;\n  RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;\n  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;\n  RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;  // slow loop\n}\n\nvoid enable_interrupt_timer(void) {\n  register_set_bits(&(RCC->APB1ENR), RCC_APB1ENR_TIM6EN);  // Enable interrupt timer peripheral\n}\n"
  },
  {
    "path": "panda/board/stm32fx/startup_stm32f205xx.s",
    "content": "/**\n  ******************************************************************************\n  * @file      startup_stm32f205xx.s\n  * @author    MCD Application Team\n  * @version   V2.1.2\n  * @date      29-June-2016\n  * @brief     STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain.\n  *            This module performs:\n  *                - Set the initial SP\n  *                - Set the initial PC == Reset_Handler,\n  *                - Set the vector table entries with the exceptions ISR address\n  *                - Branches to main in the C library (which eventually\n  *                  calls main()).\n  *            After Reset the Cortex-M3 processor is in Thread mode,\n  *            priority is Privileged, and the Stack is set to Main.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n  .syntax unified\n  .cpu cortex-m3\n  .thumb\n\n.global  g_pfnVectors\n.global  Default_Handler\n\n/* start address for the initialization values of the .data section.\ndefined in linker script */\n.word  _sidata\n/* start address for the .data section. defined in linker script */\n.word  _sdata\n/* end address for the .data section. defined in linker script */\n.word  _edata\n/* start address for the .bss section. defined in linker script */\n.word  _sbss\n/* end address for the .bss section. defined in linker script */\n.word  _ebss\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\n\n/**\n * @brief  This is the code that gets called when the processor first\n *          starts execution following a reset event. Only the absolutely\n *          necessary set is performed, after which the application\n *          supplied main() routine is called.\n * @param  None\n * @retval : None\n*/\n\n    .section  .text.Reset_Handler\n  .weak  Reset_Handler\n  .type  Reset_Handler, %function\nReset_Handler:\n  ldr   sp, =_estack     /* set stack pointer */\n  bl __initialize_hardware_early\n\n/* Copy the data segment initializers from flash to SRAM */\n  movs  r1, #0\n  b  LoopCopyDataInit\n\nCopyDataInit:\n  ldr  r3, =_sidata\n  ldr  r3, [r3, r1]\n  str  r3, [r0, r1]\n  adds  r1, r1, #4\n\nLoopCopyDataInit:\n  ldr  r0, =_sdata\n  ldr  r3, =_edata\n  adds  r2, r0, r1\n  cmp  r2, r3\n  bcc  CopyDataInit\n  ldr  r2, =_sbss\n  b  LoopFillZerobss\n/* Zero fill the bss segment. */\nFillZerobss:\n  movs  r3, #0\n  str  r3, [r2], #4\n\nLoopFillZerobss:\n  ldr  r3, = _ebss\n  cmp  r2, r3\n  bcc  FillZerobss\n\n/* Call the clock system initialization function.*/\n  /*bl  SystemInit   */\n/* Call static constructors */\n    /*bl __libc_init_array*/\n/* Call the application's entry point.*/\n  bl  main\n  bx  lr\n.size  Reset_Handler, .-Reset_Handler\n\n/**\n * @brief  This is the code that gets called when the processor receives an\n *         unexpected interrupt.  This simply enters an infinite loop, preserving\n *         the system state for examination by a debugger.\n * @param  None\n * @retval None\n*/\n    .section  .text.Default_Handler,\"ax\",%progbits\nDefault_Handler:\nInfinite_Loop:\n  b  Infinite_Loop\n  .size  Default_Handler, .-Default_Handler\n/******************************************************************************\n*\n* The minimal vector table for a Cortex M3. Note that the proper constructs\n* must be placed on this to ensure that it ends up at physical address\n* 0x0000.0000.\n*\n*******************************************************************************/\n   .section  .isr_vector,\"a\",%progbits\n  .type  g_pfnVectors, %object\n  .size  g_pfnVectors, .-g_pfnVectors\n\n\n\ng_pfnVectors:\n  .word  _estack\n  .word  Reset_Handler\n\n  .word  NMI_Handler\n  .word  HardFault_Handler\n  .word  MemManage_Handler\n  .word  BusFault_Handler\n  .word  UsageFault_Handler\n  .word  0\n  .word  0\n  .word  0\n  .word  0\n  .word  SVC_Handler\n  .word  DebugMon_Handler\n  .word  0\n  .word  PendSV_Handler\n  .word  SysTick_Handler\n\n  /* External Interrupts */\n  .word     WWDG_IRQHandler                   /* Window WatchDog              */\n  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */\n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */\n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */\n  .word     FLASH_IRQHandler                  /* FLASH                        */\n  .word     RCC_IRQHandler                    /* RCC                          */\n  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */\n  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */\n  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */\n  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */\n  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */\n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */\n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */\n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */\n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */\n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */\n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */\n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */\n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */\n  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */\n  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */\n  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */\n  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */\n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */\n  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */\n  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */\n  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */\n  .word     TIM2_IRQHandler                   /* TIM2                         */\n  .word     TIM3_IRQHandler                   /* TIM3                         */\n  .word     TIM4_IRQHandler                   /* TIM4                         */\n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */\n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */\n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */\n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */\n  .word     SPI1_IRQHandler                   /* SPI1                         */\n  .word     SPI2_IRQHandler                   /* SPI2                         */\n  .word     USART1_IRQHandler                 /* USART1                       */\n  .word     USART2_IRQHandler                 /* USART2                       */\n  .word     USART3_IRQHandler                 /* USART3                       */\n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */\n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */\n  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */\n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */\n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */\n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */\n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */\n  .word     FSMC_IRQHandler                   /* FSMC                         */\n  .word     SDIO_IRQHandler                   /* SDIO                         */\n  .word     TIM5_IRQHandler                   /* TIM5                         */\n  .word     SPI3_IRQHandler                   /* SPI3                         */\n  .word     UART4_IRQHandler                  /* UART4                        */\n  .word     UART5_IRQHandler                  /* UART5                        */\n  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */\n  .word     TIM7_IRQHandler                   /* TIM7                         */\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */\n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */\n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */\n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */\n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */\n  .word     0                                 /* Reserved                     */\n  .word     0                                 /* Reserved                     */\n  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */\n  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */\n  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */\n  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */\n  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */\n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */\n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */\n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */\n  .word     USART6_IRQHandler                 /* USART6                       */\n  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */\n  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */\n  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */\n  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */\n  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */\n  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */\n  .word     0                                 /* Reserved                         */\n  .word     0                                 /* Reserved                  */\n  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */\n\n/*******************************************************************************\n*\n* Provide weak aliases for each Exception handler to the Default_Handler.\n* As they are weak aliases, any function with the same name will override\n* this definition.\n*\n*******************************************************************************/\n   .weak      NMI_Handler\n   .thumb_set NMI_Handler,Default_Handler\n\n   .weak      HardFault_Handler\n   .thumb_set HardFault_Handler,Default_Handler\n\n   .weak      MemManage_Handler\n   .thumb_set MemManage_Handler,Default_Handler\n\n   .weak      BusFault_Handler\n   .thumb_set BusFault_Handler,Default_Handler\n\n   .weak      UsageFault_Handler\n   .thumb_set UsageFault_Handler,Default_Handler\n\n   .weak      SVC_Handler\n   .thumb_set SVC_Handler,Default_Handler\n\n   .weak      DebugMon_Handler\n   .thumb_set DebugMon_Handler,Default_Handler\n\n   .weak      PendSV_Handler\n   .thumb_set PendSV_Handler,Default_Handler\n\n   .weak      SysTick_Handler\n   .thumb_set SysTick_Handler,Default_Handler\n\n   .weak      WWDG_IRQHandler\n   .thumb_set WWDG_IRQHandler,Default_Handler\n\n   .weak      PVD_IRQHandler\n   .thumb_set PVD_IRQHandler,Default_Handler\n\n   .weak      TAMP_STAMP_IRQHandler\n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\n\n   .weak      RTC_WKUP_IRQHandler\n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\n\n   .weak      FLASH_IRQHandler\n   .thumb_set FLASH_IRQHandler,Default_Handler\n\n   .weak      RCC_IRQHandler\n   .thumb_set RCC_IRQHandler,Default_Handler\n\n   .weak      EXTI0_IRQHandler\n   .thumb_set EXTI0_IRQHandler,Default_Handler\n\n   .weak      EXTI1_IRQHandler\n   .thumb_set EXTI1_IRQHandler,Default_Handler\n\n   .weak      EXTI2_IRQHandler\n   .thumb_set EXTI2_IRQHandler,Default_Handler\n\n   .weak      EXTI3_IRQHandler\n   .thumb_set EXTI3_IRQHandler,Default_Handler\n\n   .weak      EXTI4_IRQHandler\n   .thumb_set EXTI4_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream0_IRQHandler\n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream1_IRQHandler\n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream2_IRQHandler\n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream3_IRQHandler\n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream4_IRQHandler\n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream5_IRQHandler\n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream6_IRQHandler\n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\n\n   .weak      ADC_IRQHandler\n   .thumb_set ADC_IRQHandler,Default_Handler\n\n   .weak      CAN1_TX_IRQHandler\n   .thumb_set CAN1_TX_IRQHandler,Default_Handler\n\n   .weak      CAN1_RX0_IRQHandler\n   .thumb_set CAN1_RX0_IRQHandler,Default_Handler\n\n   .weak      CAN1_RX1_IRQHandler\n   .thumb_set CAN1_RX1_IRQHandler,Default_Handler\n\n   .weak      CAN1_SCE_IRQHandler\n   .thumb_set CAN1_SCE_IRQHandler,Default_Handler\n\n   .weak      EXTI9_5_IRQHandler\n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\n\n   .weak      TIM1_BRK_TIM9_IRQHandler\n   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\n\n   .weak      TIM1_UP_TIM10_IRQHandler\n   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\n\n   .weak      TIM1_TRG_COM_TIM11_IRQHandler\n   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\n\n   .weak      TIM1_CC_IRQHandler\n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\n\n   .weak      TIM2_IRQHandler\n   .thumb_set TIM2_IRQHandler,Default_Handler\n\n   .weak      TIM3_IRQHandler\n   .thumb_set TIM3_IRQHandler,Default_Handler\n\n   .weak      TIM4_IRQHandler\n   .thumb_set TIM4_IRQHandler,Default_Handler\n\n   .weak      I2C1_EV_IRQHandler\n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\n\n   .weak      I2C1_ER_IRQHandler\n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\n\n   .weak      I2C2_EV_IRQHandler\n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\n\n   .weak      I2C2_ER_IRQHandler\n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\n\n   .weak      SPI1_IRQHandler\n   .thumb_set SPI1_IRQHandler,Default_Handler\n\n   .weak      SPI2_IRQHandler\n   .thumb_set SPI2_IRQHandler,Default_Handler\n\n   .weak      USART1_IRQHandler\n   .thumb_set USART1_IRQHandler,Default_Handler\n\n   .weak      USART2_IRQHandler\n   .thumb_set USART2_IRQHandler,Default_Handler\n\n   .weak      USART3_IRQHandler\n   .thumb_set USART3_IRQHandler,Default_Handler\n\n   .weak      EXTI15_10_IRQHandler\n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\n\n   .weak      RTC_Alarm_IRQHandler\n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\n\n   .weak      OTG_FS_WKUP_IRQHandler\n   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\n\n   .weak      TIM8_BRK_TIM12_IRQHandler\n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\n\n   .weak      TIM8_UP_TIM13_IRQHandler\n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\n\n   .weak      TIM8_TRG_COM_TIM14_IRQHandler\n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\n\n   .weak      TIM8_CC_IRQHandler\n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream7_IRQHandler\n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\n\n   .weak      FSMC_IRQHandler\n   .thumb_set FSMC_IRQHandler,Default_Handler\n\n   .weak      SDIO_IRQHandler\n   .thumb_set SDIO_IRQHandler,Default_Handler\n\n   .weak      TIM5_IRQHandler\n   .thumb_set TIM5_IRQHandler,Default_Handler\n\n   .weak      SPI3_IRQHandler\n   .thumb_set SPI3_IRQHandler,Default_Handler\n\n   .weak      UART4_IRQHandler\n   .thumb_set UART4_IRQHandler,Default_Handler\n\n   .weak      UART5_IRQHandler\n   .thumb_set UART5_IRQHandler,Default_Handler\n\n   .weak      TIM6_DAC_IRQHandler\n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\n\n   .weak      TIM7_IRQHandler\n   .thumb_set TIM7_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream0_IRQHandler\n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream1_IRQHandler\n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream2_IRQHandler\n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream3_IRQHandler\n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream4_IRQHandler\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\n\n   .weak      CAN2_TX_IRQHandler\n   .thumb_set CAN2_TX_IRQHandler,Default_Handler\n\n   .weak      CAN2_RX0_IRQHandler\n   .thumb_set CAN2_RX0_IRQHandler,Default_Handler\n\n   .weak      CAN2_RX1_IRQHandler\n   .thumb_set CAN2_RX1_IRQHandler,Default_Handler\n\n   .weak      CAN2_SCE_IRQHandler\n   .thumb_set CAN2_SCE_IRQHandler,Default_Handler\n\n   .weak      OTG_FS_IRQHandler\n   .thumb_set OTG_FS_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream5_IRQHandler\n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream6_IRQHandler\n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream7_IRQHandler\n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\n\n   .weak      USART6_IRQHandler\n   .thumb_set USART6_IRQHandler,Default_Handler\n\n   .weak      I2C3_EV_IRQHandler\n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\n\n   .weak      I2C3_ER_IRQHandler\n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\n\n   .weak      OTG_HS_EP1_OUT_IRQHandler\n   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\n\n   .weak      OTG_HS_EP1_IN_IRQHandler\n   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\n\n   .weak      OTG_HS_WKUP_IRQHandler\n   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\n\n   .weak      OTG_HS_IRQHandler\n   .thumb_set OTG_HS_IRQHandler,Default_Handler\n\n   .weak      HASH_RNG_IRQHandler\n   .thumb_set HASH_RNG_IRQHandler,Default_Handler\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/startup_stm32f413xx.s",
    "content": "/**\n  ******************************************************************************\n  * @file      startup_stm32f413xx.s\n  * @author    MCD Application Team\n  * @version   V2.6.0\n  * @date      04-November-2016\n  * @brief     STM32F413xx Devices vector table for GCC based toolchains.\n  *            This module performs:\n  *                - Set the initial SP\n  *                - Set the initial PC == Reset_Handler,\n  *                - Set the vector table entries with the exceptions ISR address\n  *                - Branches to main in the C library (which eventually\n  *                  calls main()).\n  *            After Reset the Cortex-M4 processor is in Thread mode,\n  *            priority is Privileged, and the Stack is set to Main.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n  .syntax unified\n  .cpu cortex-m4\n  .fpu softvfp\n  .thumb\n\n.global  g_pfnVectors\n.global  Default_Handler\n\n/* start address for the initialization values of the .data section.\ndefined in linker script */\n.word  _sidata\n/* start address for the .data section. defined in linker script */\n.word  _sdata\n/* end address for the .data section. defined in linker script */\n.word  _edata\n/* start address for the .bss section. defined in linker script */\n.word  _sbss\n/* end address for the .bss section. defined in linker script */\n.word  _ebss\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\n\n/**\n * @brief  This is the code that gets called when the processor first\n *          starts execution following a reset event. Only the absolutely\n *          necessary set is performed, after which the application\n *          supplied main() routine is called.\n * @param  None\n * @retval : None\n*/\n\n    .section  .text.Reset_Handler\n  .weak  Reset_Handler\n  .type  Reset_Handler, %function\nReset_Handler:\n  ldr   sp, =_estack       /* set stack pointer */\n  bl __initialize_hardware_early\n\n/* Copy the data segment initializers from flash to SRAM */\n  movs  r1, #0\n  b  LoopCopyDataInit\n\nCopyDataInit:\n  ldr  r3, =_sidata\n  ldr  r3, [r3, r1]\n  str  r3, [r0, r1]\n  adds  r1, r1, #4\n\nLoopCopyDataInit:\n  ldr  r0, =_sdata\n  ldr  r3, =_edata\n  adds  r2, r0, r1\n  cmp  r2, r3\n  bcc  CopyDataInit\n  ldr  r2, =_sbss\n  b  LoopFillZerobss\n/* Zero fill the bss segment. */\nFillZerobss:\n  movs  r3, #0\n  str  r3, [r2], #4\n\nLoopFillZerobss:\n  ldr  r3, = _ebss\n  cmp  r2, r3\n  bcc  FillZerobss\n\n/* Call the clock system intitialization function.*/\n  /* bl  SystemInit    */\n/* Call static constructors */\n    /* bl __libc_init_array */\n/* Call the application's entry point.*/\n  bl  main\n  bx  lr\n.size  Reset_Handler, .-Reset_Handler\n\n/**\n * @brief  This is the code that gets called when the processor receives an\n *         unexpected interrupt.  This simply enters an infinite loop, preserving\n *         the system state for examination by a debugger.\n * @param  None\n * @retval None\n*/\n    .section  .text.Default_Handler,\"ax\",%progbits\nDefault_Handler:\nInfinite_Loop:\n  b  Infinite_Loop\n  .size  Default_Handler, .-Default_Handler\n/******************************************************************************\n*\n* The minimal vector table for a Cortex M3. Note that the proper constructs\n* must be placed on this to ensure that it ends up at physical address\n* 0x0000.0000.\n*\n*******************************************************************************/\n   .section  .isr_vector,\"a\",%progbits\n  .type  g_pfnVectors, %object\n  .size  g_pfnVectors, .-g_pfnVectors\n\ng_pfnVectors:\n  .word  _estack\n  .word  Reset_Handler\n  .word  NMI_Handler\n  .word  HardFault_Handler\n  .word  MemManage_Handler\n  .word  BusFault_Handler\n  .word  UsageFault_Handler\n  .word  0\n  .word  0\n  .word  0\n  .word  0\n  .word  SVC_Handler\n  .word  DebugMon_Handler\n  .word  0\n  .word  PendSV_Handler\n  .word  SysTick_Handler\n\n  /* External Interrupts */\n  .word     WWDG_IRQHandler                   /* Window WatchDog                             */\n  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection             */\n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */\n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line            */\n  .word     FLASH_IRQHandler                  /* FLASH                                       */\n  .word     RCC_IRQHandler                    /* RCC                                         */\n  .word     EXTI0_IRQHandler                  /* EXTI Line0                                  */\n  .word     EXTI1_IRQHandler                  /* EXTI Line1                                  */\n  .word     EXTI2_IRQHandler                  /* EXTI Line2                                  */\n  .word     EXTI3_IRQHandler                  /* EXTI Line3                                  */\n  .word     EXTI4_IRQHandler                  /* EXTI Line4                                  */\n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                               */\n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                               */\n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                               */\n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                               */\n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                               */\n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                               */\n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                               */\n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s                        */\n  .word     CAN1_TX_IRQHandler                /* CAN1 TX                                     */\n  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                                    */\n  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                                    */\n  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                                    */\n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s                         */\n  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9                         */\n  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10                       */\n  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11      */\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare                        */\n  .word     TIM2_IRQHandler                   /* TIM2                                        */\n  .word     TIM3_IRQHandler                   /* TIM3                                        */\n  .word     TIM4_IRQHandler                   /* TIM4                                        */\n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                                  */\n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                                  */\n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                                  */\n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                                  */\n  .word     SPI1_IRQHandler                   /* SPI1                                        */\n  .word     SPI2_IRQHandler                   /* SPI2                                        */\n  .word     USART1_IRQHandler                 /* USART1                                      */\n  .word     USART2_IRQHandler                 /* USART2                                      */\n  .word     USART3_IRQHandler                 /* USART3                                      */\n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s                       */\n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line       */\n  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line         */\n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12                        */\n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13                       */\n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14      */\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare                        */\n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                                */\n  .word     FSMC_IRQHandler                   /* FSMC                                        */\n  .word     SDIO_IRQHandler                   /* SDIO                                        */\n  .word     TIM5_IRQHandler                   /* TIM5                                        */\n  .word     SPI3_IRQHandler                   /* SPI3                                        */\n  .word     UART4_IRQHandler                  /* UART4                                       */\n  .word     UART5_IRQHandler                  /* UART5                                       */\n  .word     TIM6_DAC_IRQHandler               /* TIM6, DAC1 and DAC2                         */\n  .word     TIM7_IRQHandler                   /* TIM7                                        */\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                               */\n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                               */\n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                               */\n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                               */\n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                               */\n  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM1 Filter0                              */\n  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM1 Filter1                              */\n  .word     CAN2_TX_IRQHandler                /* CAN2 TX                                     */\n  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                                    */\n  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                                    */\n  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                                    */\n  .word     OTG_FS_IRQHandler                 /* USB OTG FS                                  */\n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                               */\n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                               */\n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                               */\n  .word     USART6_IRQHandler                 /* USART6                                      */\n  .word     I2C3_EV_IRQHandler                /* I2C3 event                                  */\n  .word     I2C3_ER_IRQHandler                /* I2C3 error                                  */\n  .word     CAN3_TX_IRQHandler                /* CAN3 TX                                     */\n  .word     CAN3_RX0_IRQHandler               /* CAN3 RX0                                    */\n  .word     CAN3_RX1_IRQHandler               /* CAN3 RX1                                    */\n  .word     CAN3_SCE_IRQHandler               /* CAN3 SCE                                    */\n  .word     0                                 /* Reserved                                    */\n  .word     0                                 /* Reserved                                    */\n  .word     RNG_IRQHandler                    /* RNG                                         */\n  .word     FPU_IRQHandler                    /* FPU                                         */\n  .word     UART7_IRQHandler                  /* UART7                                       */\n  .word     UART8_IRQHandler                  /* UART8                                       */\n  .word     SPI4_IRQHandler                   /* SPI4                                        */\n  .word     SPI5_IRQHandler                   /* SPI5                                        */\n  .word     0                                 /* Reserved                                    */\n  .word     SAI1_IRQHandler                   /* SAI1                                        */\n  .word     UART9_IRQHandler                  /* UART9                                       */\n  .word     UART10_IRQHandler                 /* UART10                                      */\n  .word     0                                 /* Reserved                                    */\n  .word     0                                 /* Reserved                                    */\n  .word     QUADSPI_IRQHandler                /* QuadSPI                                     */\n  .word     0                                 /* Reserved                                    */\n  .word     0                                 /* Reserved                                    */\n  .word     FMPI2C1_EV_IRQHandler             /* FMPI2C1 Event                               */\n  .word     FMPI2C1_ER_IRQHandler             /* FMPI2C1 Error                               */\n  .word     LPTIM1_IRQHandler                 /* LPTIM1                                      */\n  .word     DFSDM2_FLT0_IRQHandler            /* DFSDM2 Filter0                              */\n  .word     DFSDM2_FLT1_IRQHandler            /* DFSDM2 Filter1                              */\n  .word     DFSDM2_FLT2_IRQHandler            /* DFSDM2 Filter2                              */\n  .word     DFSDM2_FLT3_IRQHandler            /* DFSDM2 Filter3                              */\n\n/*******************************************************************************\n*\n* Provide weak aliases for each Exception handler to the Default_Handler.\n* As they are weak aliases, any function with the same name will override\n* this definition.\n*\n*******************************************************************************/\n   .weak      NMI_Handler\n   .thumb_set NMI_Handler,Default_Handler\n\n   .weak      HardFault_Handler\n   .thumb_set HardFault_Handler,Default_Handler\n\n   .weak      MemManage_Handler\n   .thumb_set MemManage_Handler,Default_Handler\n\n   .weak      BusFault_Handler\n   .thumb_set BusFault_Handler,Default_Handler\n\n   .weak      UsageFault_Handler\n   .thumb_set UsageFault_Handler,Default_Handler\n\n   .weak      SVC_Handler\n   .thumb_set SVC_Handler,Default_Handler\n\n   .weak      DebugMon_Handler\n   .thumb_set DebugMon_Handler,Default_Handler\n\n   .weak      PendSV_Handler\n   .thumb_set PendSV_Handler,Default_Handler\n\n   .weak      SysTick_Handler\n   .thumb_set SysTick_Handler,Default_Handler\n\n   .weak      WWDG_IRQHandler\n   .thumb_set WWDG_IRQHandler,Default_Handler\n\n   .weak      PVD_IRQHandler\n   .thumb_set PVD_IRQHandler,Default_Handler\n\n   .weak      TAMP_STAMP_IRQHandler\n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\n\n   .weak      RTC_WKUP_IRQHandler\n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\n\n   .weak      FLASH_IRQHandler\n   .thumb_set FLASH_IRQHandler,Default_Handler\n\n   .weak      RCC_IRQHandler\n   .thumb_set RCC_IRQHandler,Default_Handler\n\n   .weak      EXTI0_IRQHandler\n   .thumb_set EXTI0_IRQHandler,Default_Handler\n\n   .weak      EXTI1_IRQHandler\n   .thumb_set EXTI1_IRQHandler,Default_Handler\n\n   .weak      EXTI2_IRQHandler\n   .thumb_set EXTI2_IRQHandler,Default_Handler\n\n   .weak      EXTI3_IRQHandler\n   .thumb_set EXTI3_IRQHandler,Default_Handler\n\n   .weak      EXTI4_IRQHandler\n   .thumb_set EXTI4_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream0_IRQHandler\n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream1_IRQHandler\n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream2_IRQHandler\n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream3_IRQHandler\n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream4_IRQHandler\n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream5_IRQHandler\n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream6_IRQHandler\n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\n\n   .weak      ADC_IRQHandler\n   .thumb_set ADC_IRQHandler,Default_Handler\n\n   .weak      CAN1_TX_IRQHandler\n   .thumb_set CAN1_TX_IRQHandler,Default_Handler\n\n   .weak      CAN1_RX0_IRQHandler\n   .thumb_set CAN1_RX0_IRQHandler,Default_Handler\n\n   .weak      CAN1_RX1_IRQHandler\n   .thumb_set CAN1_RX1_IRQHandler,Default_Handler\n\n   .weak      CAN1_SCE_IRQHandler\n   .thumb_set CAN1_SCE_IRQHandler,Default_Handler\n\n   .weak      EXTI9_5_IRQHandler\n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\n\n   .weak      TIM1_BRK_TIM9_IRQHandler\n   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\n\n   .weak      TIM1_UP_TIM10_IRQHandler\n   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\n\n   .weak      TIM1_TRG_COM_TIM11_IRQHandler\n   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\n\n   .weak      TIM1_CC_IRQHandler\n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\n\n   .weak      TIM2_IRQHandler\n   .thumb_set TIM2_IRQHandler,Default_Handler\n\n   .weak      TIM3_IRQHandler\n   .thumb_set TIM3_IRQHandler,Default_Handler\n\n   .weak      TIM4_IRQHandler\n   .thumb_set TIM4_IRQHandler,Default_Handler\n\n   .weak      I2C1_EV_IRQHandler\n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\n\n   .weak      I2C1_ER_IRQHandler\n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\n\n   .weak      I2C2_EV_IRQHandler\n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\n\n   .weak      I2C2_ER_IRQHandler\n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\n\n   .weak      SPI1_IRQHandler\n   .thumb_set SPI1_IRQHandler,Default_Handler\n\n   .weak      SPI2_IRQHandler\n   .thumb_set SPI2_IRQHandler,Default_Handler\n\n   .weak      USART1_IRQHandler\n   .thumb_set USART1_IRQHandler,Default_Handler\n\n   .weak      USART2_IRQHandler\n   .thumb_set USART2_IRQHandler,Default_Handler\n\n   .weak      USART3_IRQHandler\n   .thumb_set USART3_IRQHandler,Default_Handler\n\n   .weak      EXTI15_10_IRQHandler\n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\n\n   .weak      RTC_Alarm_IRQHandler\n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\n\n   .weak      OTG_FS_WKUP_IRQHandler\n   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\n\n   .weak      TIM8_BRK_TIM12_IRQHandler\n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\n\n   .weak      TIM8_UP_TIM13_IRQHandler\n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\n\n   .weak      TIM8_TRG_COM_TIM14_IRQHandler\n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\n\n   .weak      TIM8_CC_IRQHandler\n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\n\n   .weak      DMA1_Stream7_IRQHandler\n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\n\n   .weak      FSMC_IRQHandler\n   .thumb_set FSMC_IRQHandler,Default_Handler\n\n   .weak      SDIO_IRQHandler\n   .thumb_set SDIO_IRQHandler,Default_Handler\n\n   .weak      TIM5_IRQHandler\n   .thumb_set TIM5_IRQHandler,Default_Handler\n\n   .weak      SPI3_IRQHandler\n   .thumb_set SPI3_IRQHandler,Default_Handler\n\n   .weak      UART4_IRQHandler\n   .thumb_set UART4_IRQHandler,Default_Handler\n\n   .weak      UART5_IRQHandler\n   .thumb_set UART5_IRQHandler,Default_Handler\n\n   .weak      TIM6_DAC_IRQHandler\n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\n\n   .weak      TIM7_IRQHandler\n   .thumb_set TIM7_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream0_IRQHandler\n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream1_IRQHandler\n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream2_IRQHandler\n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream3_IRQHandler\n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream4_IRQHandler\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\n\n   .weak      DFSDM1_FLT0_IRQHandler\n   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler\n\n   .weak      DFSDM1_FLT1_IRQHandler\n   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler\n\n   .weak      CAN2_TX_IRQHandler\n   .thumb_set CAN2_TX_IRQHandler,Default_Handler\n\n   .weak      CAN2_RX0_IRQHandler\n   .thumb_set CAN2_RX0_IRQHandler,Default_Handler\n\n   .weak      CAN2_RX1_IRQHandler\n   .thumb_set CAN2_RX1_IRQHandler,Default_Handler\n\n   .weak      CAN2_SCE_IRQHandler\n   .thumb_set CAN2_SCE_IRQHandler,Default_Handler\n\n   .weak      OTG_FS_IRQHandler\n   .thumb_set OTG_FS_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream5_IRQHandler\n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream6_IRQHandler\n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\n\n   .weak      DMA2_Stream7_IRQHandler\n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\n\n   .weak      USART6_IRQHandler\n   .thumb_set USART6_IRQHandler,Default_Handler\n\n   .weak      I2C3_EV_IRQHandler\n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\n\n   .weak      I2C3_ER_IRQHandler\n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\n\n   .weak      CAN3_TX_IRQHandler\n   .thumb_set CAN3_TX_IRQHandler,Default_Handler\n\n   .weak      CAN3_RX0_IRQHandler\n   .thumb_set CAN3_RX0_IRQHandler,Default_Handler\n\n   .weak      CAN3_RX1_IRQHandler\n   .thumb_set CAN3_RX1_IRQHandler,Default_Handler\n\n   .weak      CAN3_SCE_IRQHandler\n   .thumb_set CAN3_SCE_IRQHandler,Default_Handler\n\n   .weak      RNG_IRQHandler\n   .thumb_set RNG_IRQHandler,Default_Handler\n\n   .weak      FPU_IRQHandler\n   .thumb_set FPU_IRQHandler,Default_Handler\n\n   .weak      UART7_IRQHandler\n   .thumb_set UART7_IRQHandler,Default_Handler\n\n   .weak      UART8_IRQHandler\n   .thumb_set UART8_IRQHandler,Default_Handler\n\n   .weak      SPI4_IRQHandler\n   .thumb_set SPI4_IRQHandler,Default_Handler\n\n   .weak      SPI5_IRQHandler\n   .thumb_set SPI5_IRQHandler,Default_Handler\n\n   .weak      SAI1_IRQHandler\n   .thumb_set SAI1_IRQHandler,Default_Handler\n\n   .weak      UART9_IRQHandler\n   .thumb_set UART9_IRQHandler,Default_Handler\n\n   .weak      UART10_IRQHandler\n   .thumb_set UART10_IRQHandler,Default_Handler\n\n   .weak      QUADSPI_IRQHandler\n   .thumb_set QUADSPI_IRQHandler,Default_Handler\n\n    .weak     FMPI2C1_EV_IRQHandler\n   .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler\n\n   .weak      FMPI2C1_ER_IRQHandler\n   .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler\n\n   .weak      LPTIM1_IRQHandler\n   .thumb_set LPTIM1_IRQHandler,Default_Handler\n\n   .weak      DFSDM2_FLT0_IRQHandler\n   .thumb_set DFSDM2_FLT0_IRQHandler,Default_Handler\n\n   .weak      DFSDM2_FLT1_IRQHandler\n   .thumb_set DFSDM2_FLT1_IRQHandler,Default_Handler\n\n   .weak      DFSDM2_FLT2_IRQHandler\n   .thumb_set DFSDM2_FLT2_IRQHandler,Default_Handler\n\n   .weak      DFSDM2_FLT3_IRQHandler\n   .thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "panda/board/stm32fx/stm32fx_config.h",
    "content": "#ifdef STM32F4\n  #include \"stm32fx/inc/stm32f4xx.h\"\n  #include \"stm32fx/inc/stm32f4xx_hal_gpio_ex.h\"\n  #define MCU_IDCODE 0x463U\n#else\n  #include \"stm32fx/inc/stm32f2xx.h\"\n  #include \"stm32fx/inc/stm32f2xx_hal_gpio_ex.h\"\n  #define MCU_IDCODE 0x411U\n#endif\n// from the linker script\n#define APP_START_ADDRESS 0x8004000U\n\n#define CORE_FREQ 96U // in Mhz\n//APB1 - 48Mhz, APB2 - 96Mhz\n#define APB1_FREQ CORE_FREQ/2U \n#define APB2_FREQ CORE_FREQ/1U\n\n#define BOOTLOADER_ADDRESS 0x1FFF0004U\n\n// Around (1Mbps / 8 bits/byte / 12 bytes per message)\n#define CAN_INTERRUPT_RATE 12000U\n\n#define MAX_LED_FADE 8192U\n\n// Threshold voltage (mV) for either of the SBUs to be below before deciding harness is connected\n#define HARNESS_CONNECTED_THRESHOLD 2500U\n\n#define NUM_INTERRUPTS 102U                // There are 102 external interrupt sources (see stm32f413.h)\n\n#define TICK_TIMER_IRQ TIM1_BRK_TIM9_IRQn\n#define TICK_TIMER TIM9\n\n#define MICROSECOND_TIMER TIM2\n\n#define INTERRUPT_TIMER_IRQ TIM6_DAC_IRQn\n#define INTERRUPT_TIMER TIM6\n\n#define PROVISION_CHUNK_ADDRESS 0x1FFF79E0U\n#define DEVICE_SERIAL_NUMBER_ADDRESS 0x1FFF79C0U\n\n#ifndef BOOTSTUB\n  #ifdef PANDA\n    #include \"main_declarations.h\"\n  #else\n    #include \"pedal/main_declarations.h\"\n  #endif\n#else\n  #include \"bootstub_declarations.h\"\n#endif\n\n#include \"libc.h\"\n#include \"critical.h\"\n#include \"faults.h\"\n\n#include \"drivers/registers.h\"\n#include \"drivers/interrupts.h\"\n#include \"drivers/gpio.h\"\n#include \"stm32fx/peripherals.h\"\n#include \"stm32fx/interrupt_handlers.h\"\n#include \"drivers/timers.h\"\n#include \"stm32fx/lladc.h\"\n#include \"stm32fx/board.h\"\n#include \"stm32fx/clock.h\"\n\n#if !defined (BOOTSTUB) && (defined(PANDA) || defined(PEDAL_USB))\n  #include \"drivers/uart.h\"\n  #include \"stm32fx/lluart.h\"\n#endif\n\n#ifdef BOOTSTUB\n  #include \"stm32fx/llflash.h\"\n#else\n  #include \"stm32fx/llbxcan.h\"\n#endif\n\n#if defined(PANDA) || defined(BOOTSTUB) || defined(PEDAL_USB)\n  #include \"stm32fx/llusb.h\"\n#endif\n\n#ifdef PEDAL\n  #include \"stm32fx/lldac.h\"\n#endif\n\nvoid early_gpio_float(void) {\n  RCC->AHB1ENR = RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;\n\n  GPIOA->MODER = 0; GPIOB->MODER = 0; GPIOC->MODER = 0;\n  GPIOA->ODR = 0; GPIOB->ODR = 0; GPIOC->ODR = 0;\n  GPIOA->PUPDR = 0; GPIOB->PUPDR = 0; GPIOC->PUPDR = 0;\n}\n"
  },
  {
    "path": "panda/board/stm32fx/stm32fx_flash.ld",
    "content": "/*\n*****************************************************************************\n**\n**  File        : stm32f4_flash.ld\n**\n**  Abstract    : Linker script for STM32F407VG Device with\n**                1024KByte FLASH, 192KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed \"as is,\" without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*/\n\n/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\nenter_bootloader_mode = 0x2001FFFC;\n_estack = 0x2001FFFC;    /* end of 128K RAM on AHB bus*/\n_app_start = 0x08004000; /* Reserve Sector 0(16K) for bootloader */\n\n/* Generate a link error if heap and stack don't fit into RAM */\n_Min_Heap_Size = 0;      /* required amount of heap  */\n_Min_Stack_Size = 0x400; /* required amount of stack */\n\n/* Specify the memory areas */\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n/* Define output sections */\nSECTIONS\n{\n  /* The startup code goes first into FLASH */\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) /* Startup code */\n    . = ALIGN(4);\n  } >FLASH\n\n  /* The program code and other data goes into FLASH */\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           /* .text sections (code) */\n    *(.text*)          /* .text* sections (code) */\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n    *(.glue_7)         /* glue arm to thumb code */\n    *(.glue_7t)        /* glue thumb to arm code */\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        /* define a global symbols at end of code */\n    _exit = .;\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  /* used by the startup to initialize data */\n  _sidata = .;\n\n  /* Initialized data sections goes into RAM, load LMA copy after code */\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        /* create a global symbol at data start */\n    *(.data)           /* .data sections */\n    *(.data*)          /* .data* sections */\n\n    . = ALIGN(4);\n    _edata = .;        /* define a global symbol at data end */\n  } >RAM\n\n  /* Uninitialized data section */\n  . = ALIGN(4);\n  .bss :\n  {\n    /* This is used by the startup in order to initialize the .bss secion */\n    _sbss = .;         /* define a global symbol at bss start */\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         /* define a global symbol at bss end */\n    __bss_end__ = _ebss;\n  } >RAM\n\n  /* User_heap_stack section, used to check that there is enough RAM left */\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  /* MEMORY_bank1 section, code must be located here explicitly            */\n  /* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); */\n  .memory_b1_text :\n  {\n    *(.mb1text)        /* .mb1text sections (code) */\n    *(.mb1text*)       /* .mb1text* sections (code)  */\n    *(.mb1rodata)      /* read-only data (constants) */\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n"
  },
  {
    "path": "panda/board/stm32h7/board.h",
    "content": "// ///////////////////////////////////////////////////////////// //\n// Hardware abstraction layer for all different supported boards //\n// ///////////////////////////////////////////////////////////// //\n#include \"boards/board_declarations.h\"\n#include \"boards/unused_funcs.h\"\n\n// ///// Board definition and detection ///// //\n#include \"drivers/harness.h\"\n#include \"drivers/fan.h\"\n#include \"stm32h7/llfan.h\"\n#include \"stm32h7/llrtc.h\"\n#include \"drivers/rtc.h\"\n#include \"boards/red.h\"\n\nuint8_t board_id(void) {\n  return detect_with_pull(GPIOF, 7, PULL_UP) |\n        (detect_with_pull(GPIOF, 8, PULL_UP) << 1U) |\n        (detect_with_pull(GPIOF, 9, PULL_UP) << 2U) |\n        (detect_with_pull(GPIOF, 10, PULL_UP) << 3U);\n}\n\nvoid detect_board_type(void) {\n  if(board_id() == 0U){\n    hw_type = HW_TYPE_RED_PANDA;\n    current_board = &board_red;\n  } else {\n    hw_type = HW_TYPE_UNKNOWN;\n    puts(\"Hardware type is UNKNOWN!\\n\");\n  }\n}\n\nbool has_external_debug_serial = 0;\nvoid detect_external_debug_serial(void) {\n  // detect if external serial debugging is present\n  has_external_debug_serial = detect_with_pull(GPIOA, 3, PULL_DOWN);\n}\n"
  },
  {
    "path": "panda/board/stm32h7/clock.h",
    "content": "void clock_init(void) {\n  //Set power mode to direct SMPS power supply(depends on the board layout)\n  register_set(&(PWR->CR3), PWR_CR3_SMPSEN, 0xFU); // powered only by SMPS\n  //Set VOS level to VOS0. (VOS3 to 170Mhz, VOS2 to 300Mhz, VOS1 to 400Mhz, VOS0 to 550Mhz)\n  register_set(&(PWR->D3CR), PWR_D3CR_VOS_1, 0xC000U); //VOS2\n  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0);\n  while ((PWR->CSR1 & PWR_CSR1_ACTVOS) != (PWR->D3CR & PWR_D3CR_VOS)); // check that VOS level was actually set\n  // Configure Flash ACR register LATENCY and WRHIGHFREQ (VOS0 range!)\n  register_set(&(FLASH->ACR), FLASH_ACR_LATENCY_2WS | 0x20U, 0x3FU); // VOS2, AXI 100MHz-150MHz\n  // enable external oscillator HSE\n  register_set_bits(&(RCC->CR), RCC_CR_HSEON);\n  while ((RCC->CR & RCC_CR_HSERDY) == 0);\n  // Specify the frequency source for PLL1, divider for DIVM1, divider for DIVM2 : HSE, 5, 5\n  register_set(&(RCC->PLLCKSELR), RCC_PLLCKSELR_PLLSRC_HSE | RCC_PLLCKSELR_DIVM1_0 | RCC_PLLCKSELR_DIVM1_2 | RCC_PLLCKSELR_DIVM2_0 | RCC_PLLCKSELR_DIVM2_2, 0x3F3F3U);\n\n  // *** PLL1 start ***\n  // Specify multiplier N and dividers P, Q, R for PLL1 : 48, 1, 5, 2\n  register_set(&(RCC->PLL1DIVR), 0x104002FU, 0x7F7FFFFFU);\n  // Specify the input and output frequency ranges, enable dividers for PLL1\n  register_set(&(RCC->PLLCFGR), RCC_PLLCFGR_PLL1RGE_2 | RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | RCC_PLLCFGR_DIVR1EN, 0x7000CU);\n  // Enable PLL1\n  register_set_bits(&(RCC->CR), RCC_CR_PLL1ON);\n  while((RCC->CR & RCC_CR_PLL1RDY) == 0);\n  // *** PLL1 end ***\n\n  //////////////OTHER CLOCKS////////////////////\n  // RCC HCLK Clock Source / RCC APB3 Clock Source / RCC SYS Clock Source\n  register_set(&(RCC->D1CFGR), RCC_D1CFGR_HPRE_DIV2 | RCC_D1CFGR_D1PPRE_DIV2 | RCC_D1CFGR_D1CPRE_DIV1, 0xF7FU);\n  // RCC APB1 Clock Source / RCC APB2 Clock Source\n  register_set(&(RCC->D2CFGR), RCC_D2CFGR_D2PPRE1_DIV2 | RCC_D2CFGR_D2PPRE2_DIV2, 0x770U);\n  // RCC APB4 Clock Source\n  register_set(&(RCC->D3CFGR), RCC_D3CFGR_D3PPRE_DIV2, 0x70U);\n  // PLL2P for ADC\n  register_clear_bits(&(RCC->D3CFGR), RCC_D3CCIPR_ADCSEL);\n\n  // Set SysClock source to PLL\n  register_set(&(RCC->CFGR), RCC_CFGR_SW_PLL1, 0x7U);\n  while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1);\n\n  // SYSCFG peripheral clock enable\n  register_set_bits(&(RCC->AHB4ENR), RCC_APB4ENR_SYSCFGEN);\n  //////////////END OTHER CLOCKS////////////////////\n\n  // Configure clock source for USB\n  register_set(&(RCC->D2CCIP2R), RCC_D2CCIP2R_USBSEL_0, RCC_D2CCIP2R_USBSEL); //PLL1Q\n  // Configure clock source for FDCAN\n  register_set(&(RCC->D2CCIP1R), RCC_D2CCIP1R_FDCANSEL_0, RCC_D2CCIP1R_FDCANSEL); //PLL1Q\n  // Configure clock source for ADC1,2,3\n  register_set(&(RCC->D3CCIPR), RCC_D3CCIPR_ADCSEL_1, RCC_D3CCIPR_ADCSEL); //per_ck(currently HSE)\n  //Enable the Clock Security System\n  register_set_bits(&(RCC->CR), RCC_CR_CSSHSEON);\n  //Enable Vdd33usb supply level detector\n  register_set_bits(&(PWR->CR3), PWR_CR3_USB33DEN);\n}\n"
  },
  {
    "path": "panda/board/stm32h7/inc/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.1.0\n * @date     09. October 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6.6 LTM (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)\n  #include \"cmsis_armclang_ltm.h\"\n\n  /*\n * Arm Compiler above 6.10.1 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #define __RESTRICT                             __restrict\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n\n"
  },
  {
    "path": "panda/board/stm32h7/inc/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.2.0\n * @date     08. May 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n\n/**\n  \\brief   Initializes data and bss sections\n  \\details This default implementations initialized all data and additional bss\n           sections relying on .copy.table and .zero.table specified properly\n           in the used linker script.\n\n */\n__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)\n{\n  extern void _start(void) __NO_RETURN;\n\n  typedef struct {\n    uint32_t const* src;\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __copy_table_t;\n\n  typedef struct {\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __zero_table_t;\n\n  extern const __copy_table_t __copy_table_start__;\n  extern const __copy_table_t __copy_table_end__;\n  extern const __zero_table_t __zero_table_start__;\n  extern const __zero_table_t __zero_table_end__;\n\n  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = pTable->src[i];\n    }\n  }\n\n  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = 0u;\n    }\n  }\n\n  _start();\n}\n\n#define __PROGRAM_START           __cmsis_start\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              __StackTop\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             __StackLimit\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(\".vectors\")))\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n __extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n\n"
  },
  {
    "path": "panda/board/stm32h7/inc/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.3\n * @date     24. June 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n\n"
  },
  {
    "path": "panda/board/stm32h7/inc/core_cm7.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm7.h\r\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r\n * @version  V5.1.1\r\n * @date     28. March 2019\r\n ******************************************************************************/\r\n/*\r\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\r\n *\r\n * SPDX-License-Identifier: Apache-2.0\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the License); you may\r\n * not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n * www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#if   defined ( __ICCARM__ )\r\n  #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined (__clang__)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM7_H_GENERIC\r\n#define __CORE_CM7_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M7\r\n  @{\r\n */\r\n\r\n#include \"cmsis_version.h\"\r\n\r\n/* CMSIS CM7 definitions */\r\n#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\r\n#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \\deprecated [15:0]  CMSIS HAL sub version */\r\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r\n*/\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_FP\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TI_ARM__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM7_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM7_H_DEPENDANT\r\n#define __CORE_CM7_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM7_REV\r\n    #define __CM7_REV               0x0000U\r\n    #warning \"__CM7_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __FPU_PRESENT\r\n    #define __FPU_PRESENT             0U\r\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __ICACHE_PRESENT\r\n    #define __ICACHE_PRESENT          0U\r\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __DCACHE_PRESENT\r\n    #define __DCACHE_PRESENT          0U\r\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __DTCM_PRESENT\r\n    #define __DTCM_PRESENT            0U\r\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          3U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M7 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n  - Core FPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\r\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\r\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\r\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r\n\r\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\r\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r\n\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RESERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n        uint32_t RESERVED3[93U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r\n        uint32_t RESERVED4[15U];\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\r\n        uint32_t RESERVED5[1U];\r\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r\n        uint32_t RESERVED6[1U];\r\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r\n        uint32_t RESERVED7[6U];\r\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r\n        uint32_t RESERVED8[1U];\r\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\r\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\r\n\r\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\r\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\r\n\r\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\r\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\r\n\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\r\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r\n\r\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\r\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r\n\r\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\r\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r\n\r\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r\n\r\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r\n\r\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r\n\r\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\r\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\r\n\r\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\r\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\r\n\r\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\r\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\r\n\r\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\r\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r\n\r\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r\n\r\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\r\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\r\n\r\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\r\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\r\n\r\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r\n\r\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\r\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r\n\r\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\r\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\r\n\r\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\r\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\r\n\r\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\r\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\r\n\r\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/* SCB Cache Level ID Register Definitions */\r\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r\n\r\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r\n\r\n/* SCB Cache Type Register Definitions */\r\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r\n\r\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r\n\r\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r\n\r\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r\n\r\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r\n\r\n/* SCB Cache Size ID Register Definitions */\r\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r\n\r\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r\n\r\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r\n\r\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r\n\r\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r\n\r\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r\n\r\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r\n\r\n/* SCB Cache Size Selection Register Definitions */\r\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r\n\r\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r\n\r\n/* SCB Software Triggered Interrupt Register Definitions */\r\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r\n\r\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\r\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r\n\r\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r\n\r\n/* SCB D-Cache Clean by Set-way Register Definitions */\r\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r\n\r\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r\n\r\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r\n\r\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r\n\r\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\r\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r\n\r\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r\n\r\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r\n\r\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r\n\r\n/* Data Tightly-Coupled Memory Control Register Definitions */\r\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r\n\r\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r\n\r\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r\n\r\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r\n\r\n/* AHBP Control Register Definitions */\r\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r\n\r\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r\n\r\n/* L1 Cache Control Register Definitions */\r\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r\n\r\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r\n\r\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r\n\r\n/* AHBS Control Register Definitions */\r\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r\n\r\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r\n\r\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r\n\r\n/* Auxiliary Bus Fault Status Register Definitions */\r\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r\n\r\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r\n\r\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r\n\r\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r\n\r\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r\n\r\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISDYNADD_Pos         26U                                         /*!< ACTLR: DISDYNADD Position */\r\n#define SCnSCB_ACTLR_DISDYNADD_Msk         (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)         /*!< ACTLR: DISDYNADD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISISSCH1_Pos         21U                                         /*!< ACTLR: DISISSCH1 Position */\r\n#define SCnSCB_ACTLR_DISISSCH1_Msk         (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)      /*!< ACTLR: DISISSCH1 Mask */\r\n\r\n#define SCnSCB_ACTLR_DISDI_Pos             16U                                         /*!< ACTLR: DISDI Position */\r\n#define SCnSCB_ACTLR_DISDI_Msk             (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)          /*!< ACTLR: DISDI Mask */\r\n\r\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos     15U                                         /*!< ACTLR: DISCRITAXIRUR Position */\r\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk     (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)     /*!< ACTLR: DISCRITAXIRUR Mask */\r\n\r\n#define SCnSCB_ACTLR_DISBTACALLOC_Pos      14U                                         /*!< ACTLR: DISBTACALLOC Position */\r\n#define SCnSCB_ACTLR_DISBTACALLOC_Msk      (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)      /*!< ACTLR: DISBTACALLOC Mask */\r\n\r\n#define SCnSCB_ACTLR_DISBTACREAD_Pos       13U                                         /*!< ACTLR: DISBTACREAD Position */\r\n#define SCnSCB_ACTLR_DISBTACREAD_Msk       (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)       /*!< ACTLR: DISBTACREAD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\r\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\r\n\r\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\r\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\r\n\r\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\r\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[32U];\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n        uint32_t RESERVED3[981U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\r\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\r\n\r\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\r\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\r\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\r\n\r\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\r\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n#define MPU_TYPE_RALIASES                  4U\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\r\n  \\brief    Type definitions for the Floating Point Unit (FPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Floating Point Unit (FPU).\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\r\n} FPU_Type;\r\n\r\n/* Floating-Point Context Control Register Definitions */\r\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r\n\r\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r\n\r\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r\n\r\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r\n\r\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r\n\r\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r\n\r\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r\n\r\n/* Floating-Point Context Address Register Definitions */\r\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r\n\r\n/* Floating-Point Default Status Control Register Definitions */\r\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r\n\r\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r\n\r\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r\n\r\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r\n\r\n/* Media and FP Feature Register 0 Definitions */\r\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r\n\r\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r\n\r\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r\n\r\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r\n\r\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r\n\r\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r\n\r\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r\n\r\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r\n\r\n/* Media and FP Feature Register 1 Definitions */\r\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r\n\r\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r\n\r\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r\n\r\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r\n\r\n/* Media and FP Feature Register 2 Definitions */\r\n\r\n#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */\r\n#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */\r\n\r\n/*@} end of group CMSIS_FPU */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Core Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n#ifdef CMSIS_NVIC_VIRTUAL\r\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\r\n  #endif\r\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r\n#else\r\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\r\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\r\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\r\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\r\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\r\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\r\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\r\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\r\n  #define NVIC_GetActive              __NVIC_GetActive\r\n  #define NVIC_SetPriority            __NVIC_SetPriority\r\n  #define NVIC_GetPriority            __NVIC_GetPriority\r\n  #define NVIC_SystemReset            __NVIC_SystemReset\r\n#endif /* CMSIS_NVIC_VIRTUAL */\r\n\r\n#ifdef CMSIS_VECTAB_VIRTUAL\r\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\r\n  #endif\r\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r\n#else\r\n  #define NVIC_SetVector              __NVIC_SetVector\r\n  #define NVIC_GetVector              __NVIC_GetVector\r\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\r\n\r\n#define NVIC_USER_IRQ_OFFSET          16\r\n\r\n\r\n/* The following EXC_RETURN values are saved the LR on exception entry */\r\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\r\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\r\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\r\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\r\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\r\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable Interrupt\r\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    __COMPILER_BARRIER();\r\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r\n    __COMPILER_BARRIER();\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Enable status\r\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\return             0  Interrupt is not enabled.\r\n  \\return             1  Interrupt is enabled.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n  }\r\n  else\r\n  {\r\n    return(0U);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable Interrupt\r\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r\n    __DSB();\r\n    __ISB();\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n  }\r\n  else\r\n  {\r\n    return(0U);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r\n  \\param [in]      IRQn  Device specific interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n  \\note    IRQn must not be negative.\r\n */\r\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n  }\r\n  else\r\n  {\r\n    return(0U);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of a device specific interrupt or a processor exception.\r\n           The interrupt number can be positive to specify a device specific interrupt,\r\n           or negative to specify a processor exception.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n  \\note    The priority cannot be set for every processor exception.\r\n */\r\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of a device specific interrupt or a processor exception.\r\n           The interrupt number can be positive to specify a device specific interrupt,\r\n           or negative to specify a processor exception.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) >= 0)\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Vector\r\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\r\n           The interrupt number can be positive to specify a device specific interrupt,\r\n           or negative to specify a processor exception.\r\n           VTOR must been relocated to SRAM before.\r\n  \\param [in]   IRQn      Interrupt number\r\n  \\param [in]   vector    Address of interrupt handler function\r\n */\r\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r\n{\r\n  uint32_t vectors = (uint32_t )SCB->VTOR;\r\n  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;\r\n  __DSB();\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Vector\r\n  \\details Reads an interrupt vector from interrupt vector table.\r\n           The interrupt number can be positive to specify a device specific interrupt,\r\n           or negative to specify a processor exception.\r\n  \\param [in]   IRQn      Interrupt number.\r\n  \\return                 Address of interrupt handler function\r\n */\r\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r\n{\r\n  uint32_t vectors = (uint32_t )SCB->VTOR;\r\n  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n/* ##########################  MPU functions  #################################### */\r\n\r\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r\n\r\n#include \"mpu_armv7.h\"\r\n\r\n#endif\r\n\r\n\r\n/* ##########################  FPU functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\r\n  \\brief    Function that provides FPU type.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   get FPU type\r\n  \\details returns the FPU type\r\n  \\returns\r\n   - \\b  0: No FPU\r\n   - \\b  1: Single precision FPU\r\n   - \\b  2: Double + Single precision FPU\r\n */\r\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r\n{\r\n  uint32_t mvfr0;\r\n\r\n  mvfr0 = SCB->MVFR0;\r\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r\n  {\r\n    return 2U;           /* Double + Single precision FPU */\r\n  }\r\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r\n  {\r\n    return 1U;           /* Single precision FPU */\r\n  }\r\n  else\r\n  {\r\n    return 0U;           /* No FPU */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_FpuFunctions */\r\n\r\n\r\n\r\n/* ##########################  Cache functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\r\n  \\brief    Functions that configure Instruction and Data cache.\r\n  @{\r\n */\r\n\r\n/* Cache Size ID Register Macros */\r\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\r\n\r\n#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\r\n#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\r\n\r\n/**\r\n  \\brief   Enable I-Cache\r\n  \\details Turns on I-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_EnableICache (void)\r\n{\r\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r\n    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */\r\n\r\n    __DSB();\r\n    __ISB();\r\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable I-Cache\r\n  \\details Turns off I-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_DisableICache (void)\r\n{\r\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\r\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Invalidate I-Cache\r\n  \\details Invalidates I-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_InvalidateICache (void)\r\n{\r\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->ICIALLU = 0UL;\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   I-Cache Invalidate by address\r\n  \\details Invalidates I-Cache for the given address.\r\n           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\r\n           I-Cache memory blocks which are part of given address + given size are invalidated.\r\n  \\param[in]   addr    address\r\n  \\param[in]   isize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)\r\n{\r\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r\n    if ( isize > 0 ) {\r\n       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));\r\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;\r\n\r\n      __DSB();\r\n\r\n      do {\r\n        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\r\n        op_addr += __SCB_ICACHE_LINE_SIZE;\r\n        op_size -= __SCB_ICACHE_LINE_SIZE;\r\n      } while ( op_size > 0 );\r\n\r\n      __DSB();\r\n      __ISB();\r\n    }\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable D-Cache\r\n  \\details Turns on D-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_EnableDCache (void)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */\r\n\r\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways-- != 0U);\r\n    } while(sets-- != 0U);\r\n    __DSB();\r\n\r\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable D-Cache\r\n  \\details Turns off D-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_DisableDCache (void)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\r\n    __DSB();\r\n\r\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean & invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways-- != 0U);\r\n    } while(sets-- != 0U);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Invalidate D-Cache\r\n  \\details Invalidates D-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways-- != 0U);\r\n    } while(sets-- != 0U);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clean D-Cache\r\n  \\details Cleans D-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_CleanDCache (void)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways-- != 0U);\r\n    } while(sets-- != 0U);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clean & Invalidate D-Cache\r\n  \\details Cleans and Invalidates D-Cache\r\n  */\r\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean & invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways-- != 0U);\r\n    } while(sets-- != 0U);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Invalidate by address\r\n  \\details Invalidates D-Cache for the given address.\r\n           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\r\n           D-Cache memory blocks which are part of given address + given size are invalidated.\r\n  \\param[in]   addr    address\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    if ( dsize > 0 ) { \r\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\r\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\r\n    \r\n      __DSB();\r\n\r\n      do {\r\n        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\r\n        op_addr += __SCB_DCACHE_LINE_SIZE;\r\n        op_size -= __SCB_DCACHE_LINE_SIZE;\r\n      } while ( op_size > 0 );\r\n\r\n      __DSB();\r\n      __ISB();\r\n    }\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Clean by address\r\n  \\details Cleans D-Cache for the given address\r\n           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.\r\n           D-Cache memory blocks which are part of given address + given size are cleaned.\r\n  \\param[in]   addr    address\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    if ( dsize > 0 ) { \r\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\r\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\r\n    \r\n      __DSB();\r\n\r\n      do {\r\n        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\r\n        op_addr += __SCB_DCACHE_LINE_SIZE;\r\n        op_size -= __SCB_DCACHE_LINE_SIZE;\r\n      } while ( op_size > 0 );\r\n\r\n      __DSB();\r\n      __ISB();\r\n    }\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Clean and Invalidate by address\r\n  \\details Cleans and invalidates D_Cache for the given address\r\n           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.\r\n           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r\n    if ( dsize > 0 ) { \r\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\r\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\r\n    \r\n      __DSB();\r\n\r\n      do {\r\n        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */\r\n        op_addr +=          __SCB_DCACHE_LINE_SIZE;\r\n        op_size -=          __SCB_DCACHE_LINE_SIZE;\r\n      } while ( op_size > 0 );\r\n\r\n      __DSB();\r\n      __ISB();\r\n    }\r\n  #endif\r\n}\r\n\r\n/*@} end of CMSIS_Core_CacheFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM7_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/mpu_armv8.h",
    "content": "/******************************************************************************\r\n * @file     mpu_armv8.h\r\n * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU\r\n * @version  V5.1.0\r\n * @date     08. March 2019\r\n ******************************************************************************/\r\n/*\r\n * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\r\n *\r\n * SPDX-License-Identifier: Apache-2.0\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the License); you may\r\n * not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n * www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#if   defined ( __ICCARM__ )\r\n  #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined (__clang__)\r\n  #pragma clang system_header    /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef ARM_MPU_ARMV8_H\r\n#define ARM_MPU_ARMV8_H\r\n\r\n/** \\brief Attribute for device memory (outer only) */\r\n#define ARM_MPU_ATTR_DEVICE                           ( 0U )\r\n\r\n/** \\brief Attribute for non-cacheable, normal memory */\r\n#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\r\n\r\n/** \\brief Attribute for normal memory (outer and inner)\r\n* \\param NT Non-Transient: Set to 1 for non-transient data.\r\n* \\param WB Write-Back: Set to 1 to use write-back update policy.\r\n* \\param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r\n* \\param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r\n*/\r\n#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\\r\n  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r\n\r\n/** \\brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r\n#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r\n\r\n/** \\brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r\n#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\r\n\r\n/** \\brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r\n#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\r\n\r\n/** \\brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r\n#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\r\n\r\n/** \\brief Memory Attribute\r\n* \\param O Outer memory attributes\r\n* \\param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r\n*/\r\n#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r\n\r\n/** \\brief Normal memory non-shareable  */\r\n#define ARM_MPU_SH_NON   (0U)\r\n\r\n/** \\brief Normal memory outer shareable  */\r\n#define ARM_MPU_SH_OUTER (2U)\r\n\r\n/** \\brief Normal memory inner shareable  */\r\n#define ARM_MPU_SH_INNER (3U)\r\n\r\n/** \\brief Memory access permissions\r\n* \\param RO Read-Only: Set to 1 for read-only memory.\r\n* \\param NP Non-Privileged: Set to 1 for non-privileged memory.\r\n*/\r\n#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r\n\r\n/** \\brief Region Base Address Register value\r\n* \\param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r\n* \\param SH Defines the Shareability domain for this memory region.\r\n* \\param RO Read-Only: Set to 1 for a read-only memory region.\r\n* \\param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r\n* \\oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r\n*/\r\n#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\\r\n  ((BASE & MPU_RBAR_BASE_Msk) | \\\r\n  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\\r\n  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\\r\n  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r\n\r\n/** \\brief Region Limit Address Register value\r\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r\n* \\param IDX The attribute index to be associated with this memory region.\r\n*/\r\n#define ARM_MPU_RLAR(LIMIT, IDX) \\\r\n  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\\r\n  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\r\n  (MPU_RLAR_EN_Msk))\r\n\r\n#if defined(MPU_RLAR_PXN_Pos)\r\n  \r\n/** \\brief Region Limit Address Register with PXN value\r\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r\n* \\param PXN Privileged execute never. Defines whether code can be executed from this privileged region.\r\n* \\param IDX The attribute index to be associated with this memory region.\r\n*/\r\n#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \\\r\n  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\\r\n  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \\\r\n  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\r\n  (MPU_RLAR_EN_Msk))\r\n  \r\n#endif\r\n\r\n/**\r\n* Struct for a single MPU Region\r\n*/\r\ntypedef struct {\r\n  uint32_t RBAR;                   /*!< Region Base Address Register value */\r\n  uint32_t RLAR;                   /*!< Region Limit Address Register value */\r\n} ARM_MPU_Region_t;\r\n    \r\n/** Enable the MPU.\r\n* \\param MPU_Control Default access permissions for unconfigured regions.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r\n{\r\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r\n#endif\r\n  __DSB();\r\n  __ISB();\r\n}\r\n\r\n/** Disable the MPU.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_Disable(void)\r\n{\r\n  __DMB();\r\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r\n#endif\r\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r\n}\r\n\r\n#ifdef MPU_NS\r\n/** Enable the Non-secure MPU.\r\n* \\param MPU_Control Default access permissions for unconfigured regions.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r\n{\r\n  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r\n  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r\n#endif\r\n  __DSB();\r\n  __ISB();\r\n}\r\n\r\n/** Disable the Non-secure MPU.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r\n{\r\n  __DMB();\r\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r\n  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r\n#endif\r\n  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r\n}\r\n#endif\r\n\r\n/** Set the memory attribute encoding to the given MPU.\r\n* \\param mpu Pointer to the MPU to be configured.\r\n* \\param idx The attribute index to be set [0-7]\r\n* \\param attr The attribute value to be set.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r\n{\r\n  const uint8_t reg = idx / 4U;\r\n  const uint32_t pos = ((idx % 4U) * 8U);\r\n  const uint32_t mask = 0xFFU << pos;\r\n  \r\n  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r\n    return; // invalid index\r\n  }\r\n  \r\n  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r\n}\r\n\r\n/** Set the memory attribute encoding.\r\n* \\param idx The attribute index to be set [0-7]\r\n* \\param attr The attribute value to be set.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r\n{\r\n  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r\n}\r\n\r\n#ifdef MPU_NS\r\n/** Set the memory attribute encoding to the Non-secure MPU.\r\n* \\param idx The attribute index to be set [0-7]\r\n* \\param attr The attribute value to be set.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r\n{\r\n  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r\n}\r\n#endif\r\n\r\n/** Clear and disable the given MPU region of the given MPU.\r\n* \\param mpu Pointer to MPU to be used.\r\n* \\param rnr Region number to be cleared.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r\n{\r\n  mpu->RNR = rnr;\r\n  mpu->RLAR = 0U;\r\n}\r\n\r\n/** Clear and disable the given MPU region.\r\n* \\param rnr Region number to be cleared.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r\n{\r\n  ARM_MPU_ClrRegionEx(MPU, rnr);\r\n}\r\n\r\n#ifdef MPU_NS\r\n/** Clear and disable the given Non-secure MPU region.\r\n* \\param rnr Region number to be cleared.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r\n{  \r\n  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r\n}\r\n#endif\r\n\r\n/** Configure the given MPU region of the given MPU.\r\n* \\param mpu Pointer to MPU to be used.\r\n* \\param rnr Region number to be configured.\r\n* \\param rbar Value for RBAR register.\r\n* \\param rlar Value for RLAR register.\r\n*/   \r\n__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r\n{\r\n  mpu->RNR = rnr;\r\n  mpu->RBAR = rbar;\r\n  mpu->RLAR = rlar;\r\n}\r\n\r\n/** Configure the given MPU region.\r\n* \\param rnr Region number to be configured.\r\n* \\param rbar Value for RBAR register.\r\n* \\param rlar Value for RLAR register.\r\n*/   \r\n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r\n{\r\n  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r\n}\r\n\r\n#ifdef MPU_NS\r\n/** Configure the given Non-secure MPU region.\r\n* \\param rnr Region number to be configured.\r\n* \\param rbar Value for RBAR register.\r\n* \\param rlar Value for RLAR register.\r\n*/   \r\n__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r\n{\r\n  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  \r\n}\r\n#endif\r\n\r\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\r\n* \\param dst Destination data is copied to.\r\n* \\param src Source data is copied from.\r\n* \\param len Amount of data words to be copied.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r\n{\r\n  uint32_t i;\r\n  for (i = 0U; i < len; ++i) \r\n  {\r\n    dst[i] = src[i];\r\n  }\r\n}\r\n\r\n/** Load the given number of MPU regions from a table to the given MPU.\r\n* \\param mpu Pointer to the MPU registers to be used.\r\n* \\param rnr First region number to be configured.\r\n* \\param table Pointer to the MPU configuration table.\r\n* \\param cnt Amount of regions to be configured.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r\n{\r\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r\n  if (cnt == 1U) {\r\n    mpu->RNR = rnr;\r\n    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r\n  } else {\r\n    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\r\n    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r\n    \r\n    mpu->RNR = rnrBase;\r\n    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r\n      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r\n      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r\n      table += c;\r\n      cnt -= c;\r\n      rnrOffset = 0U;\r\n      rnrBase += MPU_TYPE_RALIASES;\r\n      mpu->RNR = rnrBase;\r\n    }\r\n    \r\n    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r\n  }\r\n}\r\n\r\n/** Load the given number of MPU regions from a table.\r\n* \\param rnr First region number to be configured.\r\n* \\param table Pointer to the MPU configuration table.\r\n* \\param cnt Amount of regions to be configured.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r\n{\r\n  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r\n}\r\n\r\n#ifdef MPU_NS\r\n/** Load the given number of MPU regions from a table to the Non-secure MPU.\r\n* \\param rnr First region number to be configured.\r\n* \\param table Pointer to the MPU configuration table.\r\n* \\param cnt Amount of regions to be configured.\r\n*/\r\n__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r\n{\r\n  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/stm32h725xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32h735xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS STM32H735xx Device Peripheral Access Layer Header File.\r\n  *\r\n  *          This file contains:\r\n  *           - Data structures and the address mapping for all peripherals\r\n  *           - Peripheral's registers declarations and bits definition\r\n  *           - Macros to access peripheral's registers hardware\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS_Device\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32h735xx\r\n  * @{\r\n  */\r\n\r\n#ifndef STM32H735xx_H\r\n#define STM32H735xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n\r\n/** @addtogroup Peripheral_interrupt_number_definition\r\n  * @{\r\n  */\r\n\r\n/**\r\n * @brief STM32H7XX Interrupt Number Definition, according to the selected device\r\n *        in @ref Library_configuration_section\r\n */\r\ntypedef enum\r\n{\r\n/******  Cortex-M Processor Exceptions Numbers *****************************************************************/\r\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\r\n  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */\r\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */\r\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */\r\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */\r\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */\r\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */\r\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */\r\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */\r\n/******  STM32 specific Interrupt Numbers **********************************************************************/\r\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */\r\n  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */\r\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\r\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\r\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\r\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\r\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\r\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\r\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\r\n  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */\r\n  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */\r\n  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */\r\n  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */\r\n  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */\r\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */\r\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */\r\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */\r\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\r\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\r\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\r\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\r\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r\n  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\r\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r\n  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */\r\n  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */\r\n  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */\r\n  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */\r\n  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */\r\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\r\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\r\n  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */\r\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\r\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\r\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\r\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\r\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\r\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\r\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\r\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\r\n  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */\r\n  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */\r\n  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */\r\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\r\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\r\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\r\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\r\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\r\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\r\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\r\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */\r\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */\r\n  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */\r\n  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */\r\n  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */\r\n  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */\r\n  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */\r\n  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */\r\n  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */\r\n  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */\r\n  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */\r\n  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */\r\n  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */\r\n  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */\r\n  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */\r\n  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */\r\n  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */\r\n  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */\r\n  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */\r\n  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */\r\n  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */\r\n  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */\r\n  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */\r\n  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */\r\n  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */\r\n  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */\r\n  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */\r\n  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */\r\n  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */\r\n  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */\r\n  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */\r\n  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */\r\n  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */\r\n  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */\r\n  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */\r\n  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */\r\n  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */\r\n  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */\r\n  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */\r\n  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */\r\n  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */\r\n  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */\r\n  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */\r\n  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */\r\n  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */\r\n  OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */\r\n  OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */\r\n  FMAC_IRQn                   = 153,    /*!< FMAC global interrupt                                             */\r\n  CORDIC_IRQn                 = 154,    /*!< CORDIC global interrupt                                           */\r\n  UART9_IRQn                  = 155,    /*!< UART9 global Interrupt                                            */\r\n  USART10_IRQn                = 156,    /*!< USART10 global interrupt                                          */\r\n  I2C5_EV_IRQn                = 157,    /*!< I2C5 event interrupt                                              */\r\n  I2C5_ER_IRQn                = 158,    /*!< I2C5 error interrupt                                              */\r\n  FDCAN3_IT0_IRQn             = 159,    /*!< FDCAN3 Interrupt line 0                                           */\r\n  FDCAN3_IT1_IRQn             = 160,    /*!< FDCAN3 Interrupt line 1                                           */\r\n  TIM23_IRQn                  = 161,    /*!< TIM23 global interrupt                                            */\r\n  TIM24_IRQn                  = 162,    /*!< TIM24 global interrupt                                            */\r\n} IRQn_Type;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Configuration_section_for_CMSIS\r\n  * @{\r\n  */\r\n\r\n#define SMPS       /*!< Switched mode power supply feature */\r\n\r\n\r\n\r\n/**\r\n  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals\r\n   */\r\n#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */\r\n#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */\r\n#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */\r\n#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r\n#define __FPU_PRESENT             1       /*!< FPU present                                   */\r\n#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */\r\n#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */\r\n#include \"core_cm7.h\"                     /*!< Cortex-M7 processor and core peripherals      */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n\r\n#include \"system_stm32h7xx.h\"\r\n#include <stdint.h>\r\n\r\n/** @addtogroup Peripheral_registers_structures\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Analog to Digital Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */\r\n  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */\r\n  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */\r\n  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */\r\n  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */\r\n  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */\r\n  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */\r\n  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */\r\n  __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */\r\n  __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */\r\n  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */\r\n  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */\r\n  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */\r\n  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */\r\n  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */\r\n  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */\r\n  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */\r\n  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */\r\n  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */\r\n  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */\r\n  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */\r\n  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */\r\n  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */\r\n  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */\r\n  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */\r\n  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */\r\n  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */\r\n  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */\r\n  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */\r\n  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */\r\n  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */\r\n  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */\r\n  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */\r\n  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */\r\n  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */\r\n  __IO uint32_t LTR2_DIFSEL;      /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3,   Address offset: 0xB0 */\r\n  __IO uint32_t HTR2_CALFACT;     /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */\r\n  __IO uint32_t LTR3_RES10;       /*!< ADC watchdog Lower threshold register 3, specific ADC1/2,   Address offset: 0xB8 */\r\n  __IO uint32_t HTR3_RES11;       /*!< ADC watchdog Higher threshold register 3, specific ADC1/2,  Address offset: 0xBC */\r\n  __IO uint32_t DIFSEL_RES12;     /*!< ADC Differential Mode Selection Register specific ADC1/2,   Address offset: 0xC0 */\r\n  __IO uint32_t CALFACT_RES13;    /*!< ADC Calibration Factors specific ADC1/2,                    Address offset: 0xC4 */\r\n  __IO uint32_t CALFACT2_RES14;   /*!< ADC Linearity Calibration Factors specific ADC1/2,          Address offset: 0xC8 */\r\n} ADC_TypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */\r\nuint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */\r\n__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */\r\n__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */\r\n__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */\r\n\r\n} ADC_Common_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief VREFBUF\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */\r\n  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */\r\n} VREFBUF_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief FD Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */\r\n  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */\r\n  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */\r\n  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */\r\n  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */\r\n  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */\r\n  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */\r\n  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */\r\n  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */\r\n  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */\r\n  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */\r\n  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */\r\n  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */\r\n  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */\r\n  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */\r\n  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */\r\n  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */\r\n  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */\r\n  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */\r\n  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */\r\n  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */\r\n  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */\r\n  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */\r\n  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */\r\n  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */\r\n  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */\r\n  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */\r\n  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */\r\n  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */\r\n  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */\r\n  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */\r\n  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */\r\n  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */\r\n  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */\r\n  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */\r\n  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */\r\n  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */\r\n  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */\r\n  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */\r\n  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */\r\n  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */\r\n  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */\r\n  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */\r\n  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */\r\n  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */\r\n  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */\r\n  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */\r\n  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */\r\n  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */\r\n  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */\r\n  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */\r\n  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */\r\n  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */\r\n} FDCAN_GlobalTypeDef;\r\n\r\n/**\r\n  * @brief TTFD Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */\r\n  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */\r\n  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */\r\n  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */\r\n  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */\r\n  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */\r\n  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */\r\n  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */\r\n  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */\r\n  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */\r\n  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */\r\n  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */\r\n  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */\r\n  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */\r\n  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */\r\n  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */\r\n  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */\r\n  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */\r\n  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */\r\n} TTCAN_TypeDef;\r\n\r\n/**\r\n  * @brief FD Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */\r\n  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */\r\n  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */\r\n  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */\r\n  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */\r\n  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */\r\n} FDCAN_ClockCalibrationUnit_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Consumer Electronics Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */\r\n  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */\r\n  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */\r\n  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */\r\n  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r\n  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */\r\n}CEC_TypeDef;\r\n\r\n/**\r\n  * @brief COordincate Rotation DIgital Computer\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */\r\n  __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */\r\n  __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */\r\n} CORDIC_TypeDef;\r\n\r\n/**\r\n  * @brief CRC calculation unit\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\r\n  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\r\n  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\r\n  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\r\n  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\r\n  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\r\n} CRC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Clock Recovery System\r\n  */\r\ntypedef struct\r\n{\r\n__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */\r\n__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */\r\n__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */\r\n__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */\r\n} CRS_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Digital to Analog Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\r\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\r\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\r\n  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */\r\n  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */\r\n  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */\r\n  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */\r\n  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */\r\n  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */\r\n} DAC_TypeDef;\r\n\r\n/**\r\n  * @brief DFSDM module registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */\r\n  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */\r\n  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\r\n  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\r\n  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\r\n  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */\r\n  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */\r\n  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */\r\n  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\r\n  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\r\n  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\r\n  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\r\n  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\r\n  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\r\n  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */\r\n} DFSDM_Filter_TypeDef;\r\n\r\n/**\r\n  * @brief DFSDM channel configuration registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\r\n  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\r\n  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and\r\n                                   short circuit detector register,                  Address offset: 0x08 */\r\n  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\r\n  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */\r\n} DFSDM_Channel_TypeDef;\r\n\r\n/**\r\n  * @brief Debug MCU\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */\r\n  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */\r\n  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */\r\n  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */\r\n  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */\r\n  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */\r\n  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */\r\n  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */\r\n  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */\r\n  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */\r\n  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */\r\n  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */\r\n  __IO uint32_t RESERVED9[990]; /*!< Reserved,                         Address offset: 0x58-0xFCC */\r\n  __IO uint32_t PIDR4;       /*!< Debug MCU peripheral identity register 4,  Address offset: 0xFD0 */\r\n  __IO uint32_t RESERVED10[3];/*!< Reserved,                            Address offset: 0xFD4-0xFDC */\r\n  __IO uint32_t PIDR0;       /*!< Debug MCU peripheral identity register 0,  Address offset: 0xFE0 */\r\n  __IO uint32_t PIDR1;       /*!< Debug MCU peripheral identity register 1,  Address offset: 0xFE4 */\r\n  __IO uint32_t PIDR2;       /*!< Debug MCU peripheral identity register 2,  Address offset: 0xFE8 */\r\n  __IO uint32_t PIDR3;       /*!< Debug MCU peripheral identity register 3,  Address offset: 0xFEC */\r\n  __IO uint32_t CIDR0;       /*!< Debug MCU component identity register 0,   Address offset: 0xFF0 */\r\n  __IO uint32_t CIDR1;       /*!< Debug MCU component identity register 1,   Address offset: 0xFF4 */\r\n  __IO uint32_t CIDR2;       /*!< Debug MCU component identity register 2,   Address offset: 0xFF8 */\r\n  __IO uint32_t CIDR3;       /*!< Debug MCU component identity register 3,   Address offset: 0xFFC */\r\n}DBGMCU_TypeDef;\r\n/**\r\n  * @brief DCMI\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\r\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\r\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\r\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\r\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\r\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\r\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\r\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\r\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\r\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\r\n} DCMI_TypeDef;\r\n\r\n/**\r\n  * @brief PSSI\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */\r\n  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */\r\n  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */\r\n  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */\r\n  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */\r\n  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */\r\n  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */\r\n  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */\r\n  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */\r\n  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */\r\n  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */\r\n  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */\r\n  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */\r\n} PSSI_TypeDef;\r\n\r\n/**\r\n  * @brief DMA Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\r\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\r\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\r\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\r\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\r\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\r\n} DMA_Stream_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\r\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\r\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\r\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r\n} DMA_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */\r\n  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */\r\n  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */\r\n  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */\r\n  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */\r\n} BDMA_Channel_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */\r\n  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */\r\n} BDMA_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */\r\n}DMAMUX_Channel_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */\r\n  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */\r\n}DMAMUX_ChannelStatus_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */\r\n}DMAMUX_RequestGen_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */\r\n  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */\r\n}DMAMUX_RequestGenStatus_TypeDef;\r\n\r\n/**\r\n  * @brief MDMA Controller\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */\r\n}MDMA_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */\r\n  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */\r\n  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */\r\n  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */\r\n  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */\r\n  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */\r\n  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */\r\n  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */\r\n  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */\r\n  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */\r\n  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */\r\n  uint32_t       RESERVED0; /*!< Reserved, 0x6C                                                             */\r\n  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */\r\n  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */\r\n}MDMA_Channel_TypeDef;\r\n\r\n/**\r\n  * @brief DMA2D Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\r\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\r\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\r\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\r\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\r\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\r\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\r\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\r\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\r\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\r\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\r\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\r\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\r\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\r\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\r\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\r\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\r\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\r\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\r\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\r\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\r\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\r\n} DMA2D_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Ethernet MAC\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t MACCR;\r\n  __IO uint32_t MACECR;\r\n  __IO uint32_t MACPFR;\r\n  __IO uint32_t MACWTR;\r\n  __IO uint32_t MACHT0R;\r\n  __IO uint32_t MACHT1R;\r\n  uint32_t      RESERVED1[14];\r\n  __IO uint32_t MACVTR;\r\n  uint32_t      RESERVED2;\r\n  __IO uint32_t MACVHTR;\r\n  uint32_t      RESERVED3;\r\n  __IO uint32_t MACVIR;\r\n  __IO uint32_t MACIVIR;\r\n  uint32_t      RESERVED4[2];\r\n  __IO uint32_t MACTFCR;\r\n  uint32_t      RESERVED5[7];\r\n  __IO uint32_t MACRFCR;\r\n  uint32_t      RESERVED6[7];\r\n  __IO uint32_t MACISR;\r\n  __IO uint32_t MACIER;\r\n  __IO uint32_t MACRXTXSR;\r\n  uint32_t      RESERVED7;\r\n  __IO uint32_t MACPCSR;\r\n  __IO uint32_t MACRWKPFR;\r\n  uint32_t      RESERVED8[2];\r\n  __IO uint32_t MACLCSR;\r\n  __IO uint32_t MACLTCR;\r\n  __IO uint32_t MACLETR;\r\n  __IO uint32_t MAC1USTCR;\r\n  uint32_t      RESERVED9[12];\r\n  __IO uint32_t MACVR;\r\n  __IO uint32_t MACDR;\r\n  uint32_t      RESERVED10;\r\n  __IO uint32_t MACHWF0R;\r\n  __IO uint32_t MACHWF1R;\r\n  __IO uint32_t MACHWF2R;\r\n  uint32_t      RESERVED11[54];\r\n  __IO uint32_t MACMDIOAR;\r\n  __IO uint32_t MACMDIODR;\r\n  uint32_t      RESERVED12[2];\r\n  __IO uint32_t MACARPAR;\r\n  uint32_t      RESERVED13[59];\r\n  __IO uint32_t MACA0HR;\r\n  __IO uint32_t MACA0LR;\r\n  __IO uint32_t MACA1HR;\r\n  __IO uint32_t MACA1LR;\r\n  __IO uint32_t MACA2HR;\r\n  __IO uint32_t MACA2LR;\r\n  __IO uint32_t MACA3HR;\r\n  __IO uint32_t MACA3LR;\r\n  uint32_t      RESERVED14[248];\r\n  __IO uint32_t MMCCR;\r\n  __IO uint32_t MMCRIR;\r\n  __IO uint32_t MMCTIR;\r\n  __IO uint32_t MMCRIMR;\r\n  __IO uint32_t MMCTIMR;\r\n  uint32_t      RESERVED15[14];\r\n  __IO uint32_t MMCTSCGPR;\r\n  __IO uint32_t MMCTMCGPR;\r\n  uint32_t      RESERVED16[5];\r\n  __IO uint32_t MMCTPCGR;\r\n  uint32_t      RESERVED17[10];\r\n  __IO uint32_t MMCRCRCEPR;\r\n  __IO uint32_t MMCRAEPR;\r\n  uint32_t      RESERVED18[10];\r\n  __IO uint32_t MMCRUPGR;\r\n  uint32_t      RESERVED19[9];\r\n  __IO uint32_t MMCTLPIMSTR;\r\n  __IO uint32_t MMCTLPITCR;\r\n  __IO uint32_t MMCRLPIMSTR;\r\n  __IO uint32_t MMCRLPITCR;\r\n  uint32_t      RESERVED20[65];\r\n  __IO uint32_t MACL3L4C0R;\r\n  __IO uint32_t MACL4A0R;\r\n  uint32_t      RESERVED21[2];\r\n  __IO uint32_t MACL3A0R0R;\r\n  __IO uint32_t MACL3A1R0R;\r\n  __IO uint32_t MACL3A2R0R;\r\n  __IO uint32_t MACL3A3R0R;\r\n  uint32_t      RESERVED22[4];\r\n  __IO uint32_t MACL3L4C1R;\r\n  __IO uint32_t MACL4A1R;\r\n  uint32_t      RESERVED23[2];\r\n  __IO uint32_t MACL3A0R1R;\r\n  __IO uint32_t MACL3A1R1R;\r\n  __IO uint32_t MACL3A2R1R;\r\n  __IO uint32_t MACL3A3R1R;\r\n  uint32_t      RESERVED24[108];\r\n  __IO uint32_t MACTSCR;\r\n  __IO uint32_t MACSSIR;\r\n  __IO uint32_t MACSTSR;\r\n  __IO uint32_t MACSTNR;\r\n  __IO uint32_t MACSTSUR;\r\n  __IO uint32_t MACSTNUR;\r\n  __IO uint32_t MACTSAR;\r\n  uint32_t      RESERVED25;\r\n  __IO uint32_t MACTSSR;\r\n  uint32_t      RESERVED26[3];\r\n  __IO uint32_t MACTTSSNR;\r\n  __IO uint32_t MACTTSSSR;\r\n  uint32_t      RESERVED27[2];\r\n  __IO uint32_t MACACR;\r\n  uint32_t      RESERVED28;\r\n  __IO uint32_t MACATSNR;\r\n  __IO uint32_t MACATSSR;\r\n  __IO uint32_t MACTSIACR;\r\n  __IO uint32_t MACTSEACR;\r\n  __IO uint32_t MACTSICNR;\r\n  __IO uint32_t MACTSECNR;\r\n  uint32_t      RESERVED29[4];\r\n  __IO uint32_t MACPPSCR;\r\n  uint32_t      RESERVED30[3];\r\n  __IO uint32_t MACPPSTTSR;\r\n  __IO uint32_t MACPPSTTNR;\r\n  __IO uint32_t MACPPSIR;\r\n  __IO uint32_t MACPPSWR;\r\n  uint32_t      RESERVED31[12];\r\n  __IO uint32_t MACPOCR;\r\n  __IO uint32_t MACSPI0R;\r\n  __IO uint32_t MACSPI1R;\r\n  __IO uint32_t MACSPI2R;\r\n  __IO uint32_t MACLMIR;\r\n  uint32_t      RESERVED32[11];\r\n  __IO uint32_t MTLOMR;\r\n  uint32_t      RESERVED33[7];\r\n  __IO uint32_t MTLISR;\r\n  uint32_t      RESERVED34[55];\r\n  __IO uint32_t MTLTQOMR;\r\n  __IO uint32_t MTLTQUR;\r\n  __IO uint32_t MTLTQDR;\r\n  uint32_t      RESERVED35[8];\r\n  __IO uint32_t MTLQICSR;\r\n  __IO uint32_t MTLRQOMR;\r\n  __IO uint32_t MTLRQMPOCR;\r\n  __IO uint32_t MTLRQDR;\r\n  uint32_t      RESERVED36[177];\r\n  __IO uint32_t DMAMR;\r\n  __IO uint32_t DMASBMR;\r\n  __IO uint32_t DMAISR;\r\n  __IO uint32_t DMADSR;\r\n  uint32_t      RESERVED37[60];\r\n  __IO uint32_t DMACCR;\r\n  __IO uint32_t DMACTCR;\r\n  __IO uint32_t DMACRCR;\r\n  uint32_t      RESERVED38[2];\r\n  __IO uint32_t DMACTDLAR;\r\n  uint32_t      RESERVED39;\r\n  __IO uint32_t DMACRDLAR;\r\n  __IO uint32_t DMACTDTPR;\r\n  uint32_t      RESERVED40;\r\n  __IO uint32_t DMACRDTPR;\r\n  __IO uint32_t DMACTDRLR;\r\n  __IO uint32_t DMACRDRLR;\r\n  __IO uint32_t DMACIER;\r\n  __IO uint32_t DMACRIWTR;\r\n__IO uint32_t DMACSFCSR;\r\n  uint32_t      RESERVED41;\r\n  __IO uint32_t DMACCATDR;\r\n  uint32_t      RESERVED42;\r\n  __IO uint32_t DMACCARDR;\r\n  uint32_t      RESERVED43;\r\n  __IO uint32_t DMACCATBR;\r\n  uint32_t      RESERVED44;\r\n  __IO uint32_t DMACCARBR;\r\n  __IO uint32_t DMACSR;\r\nuint32_t      RESERVED45[2];\r\n__IO uint32_t DMACMFCR;\r\n}ETH_TypeDef;\r\n/**\r\n  * @brief External Interrupt/Event Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */\r\n__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */\r\n__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */\r\n__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */\r\n__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */\r\n__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */\r\nuint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */\r\n__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */\r\n__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */\r\n__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */\r\n__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */\r\n__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */\r\n__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */\r\nuint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */\r\n__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */\r\n__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */\r\n__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */\r\n__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */\r\n__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */\r\n__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */\r\nuint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */\r\n__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */\r\n__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */\r\n__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */\r\nuint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */\r\n__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */\r\n__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */\r\n__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */\r\nuint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */\r\n__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */\r\n__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */\r\n__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */\r\n}EXTI_TypeDef;\r\n\r\n/**\r\n  * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2\r\n  *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.\r\n  *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:\r\n  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)\r\n  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)\r\n  *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only\r\n  */\r\n\r\ntypedef struct\r\n{\r\n__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */\r\n__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */\r\n__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */\r\nuint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */\r\n__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */\r\n__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */\r\n__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */\r\nuint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */\r\n__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */\r\n__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */\r\n__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */\r\n}EXTI_Core_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief FLASH Registers\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */\r\n  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */\r\n  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */\r\n  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */\r\n  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */\r\n  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */\r\n  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */\r\n  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */\r\n  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */\r\n  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */\r\n  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */\r\n  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */\r\n  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */\r\n  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */\r\n  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */\r\n  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */\r\n  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */\r\n  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */\r\n  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */\r\n  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */\r\n  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */\r\n  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */\r\n  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */\r\n  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */\r\n  uint32_t      RESERVED[3];     /*!< Reserved, 0x64 to 0x6C                                                          */\r\n  __IO uint32_t OPTSR2_CUR;      /*!< Flash Option Status Current Register 2,                   Address offset: 0x70  */\r\n  __IO uint32_t OPTSR2_PRG;      /*!< Flash Option Status to Program Register 2,                Address offset: 0x74  */\r\n} FLASH_TypeDef;\r\n\r\n/**\r\n  * @brief Filter and Mathematical ACcelerator\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */\r\n  __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */\r\n  __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */\r\n  __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */\r\n  __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */\r\n  __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */\r\n  __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */\r\n  __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */\r\n} FMAC_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r\n} FMC_Bank1_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank1E\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r\n} FMC_Bank1E_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank2\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\r\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\r\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\r\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\r\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\r\n} FMC_Bank2_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank3\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\r\n  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\r\n  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\r\n  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r\n  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */\r\n  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\r\n} FMC_Bank3_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank5 and 6\r\n  */\r\n\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\r\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\r\n  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */\r\n  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */\r\n  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */\r\n} FMC_Bank5_6_TypeDef;\r\n\r\n/**\r\n  * @brief General Purpose I/O\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\r\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\r\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\r\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\r\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\r\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */\r\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r\n} GPIO_TypeDef;\r\n\r\n/**\r\n  * @brief Operational Amplifier (OPAMP)\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */\r\n  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */\r\n  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */\r\n} OPAMP_TypeDef;\r\n\r\n/**\r\n  * @brief System configuration controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */\r\n __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */\r\n __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */\r\n __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */\r\n uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */\r\n __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */\r\n __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */\r\n __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */\r\n uint32_t     RESERVED3;       /*!< Reserved,                                           Address offset: 0x2C        */\r\n __IO uint32_t ADC2ALT;        /*!< ADC2 internal input alternate connection register,  Address offset: 0x30        */\r\n uint32_t     RESERVED4[60];   /*!< Reserved, 0x34-0x120                                                            */\r\n  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */\r\n  uint32_t     RESERVED5[118]; /*!< Reserved, 0x128-0x2FC                                                           */\r\n __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */\r\n __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */\r\n __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */\r\n __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */\r\n __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */\r\n __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */\r\n __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */\r\n __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */\r\n uint32_t     RESERVED6[3];    /*!< Reserved,                                           Address offset: 0x320-0x328 */\r\n __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */\r\n __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */\r\n __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */\r\n __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */\r\n __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */\r\n __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */\r\n __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */\r\n __IO uint32_t UR18;           /*!< SYSCFG user register 18,                            Address offset: 0x348       */\r\n\r\n} SYSCFG_TypeDef;\r\n\r\n/**\r\n  * @brief Inter-integrated Circuit Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */\r\n  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */\r\n  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */\r\n  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */\r\n  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */\r\n  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */\r\n  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */\r\n  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */\r\n  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */\r\n  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */\r\n  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */\r\n} I2C_TypeDef;\r\n\r\n/**\r\n  * @brief Independent WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\r\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\r\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\r\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\r\n  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */\r\n} IWDG_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief LCD-TFT Display Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */\r\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\r\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\r\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\r\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\r\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\r\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */\r\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\r\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */\r\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\r\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */\r\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\r\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\r\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\r\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\r\n  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */\r\n} LTDC_TypeDef;\r\n\r\n/**\r\n  * @brief LCD-TFT Display layer x Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\r\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\r\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\r\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\r\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\r\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\r\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\r\n  uint32_t      RESERVED0[2];  /*!< Reserved */\r\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\r\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\r\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\r\n  uint32_t      RESERVED1[3];  /*!< Reserved */\r\n  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */\r\n\r\n} LTDC_Layer_TypeDef;\r\n\r\n/**\r\n  * @brief Power Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */\r\n  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */\r\n  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */\r\n  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */\r\n  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */\r\n       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */\r\n  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */\r\n       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */\r\n  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */\r\n  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */\r\n  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */\r\n} PWR_TypeDef;\r\n\r\n/**\r\n  * @brief Reset and Clock Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */\r\n __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */\r\n __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */\r\n __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */\r\n __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */\r\n uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */\r\n __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */\r\n __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */\r\n __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */\r\n uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */\r\n __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */\r\n __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */\r\n __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */\r\n __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */\r\n __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */\r\n __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */\r\n __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */\r\n __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */\r\n uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */\r\n __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */\r\n __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */\r\n __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */\r\n __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */\r\n uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */\r\n __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */\r\n __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */\r\n __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */\r\n uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */\r\n __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */\r\n __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */\r\n uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */\r\n __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */\r\n __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */\r\n __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */\r\n __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */\r\n __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */\r\n __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */\r\n __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */\r\n __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */\r\n __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */\r\n __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */\r\n uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */\r\n __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */\r\n uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */\r\n __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */\r\n __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */\r\n __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */\r\n __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */\r\n __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */\r\n __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */\r\n __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */\r\n __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */\r\n __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */\r\n __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */\r\n uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */\r\n __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */\r\n __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */\r\n __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */\r\n __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */\r\n __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */\r\n __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */\r\n __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */\r\n __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */\r\n __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */\r\n uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */\r\n\r\n} RCC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Real-Time Clock\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */\r\n  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */\r\n  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */\r\n  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */\r\n  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */\r\n  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\r\n       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */\r\n  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */\r\n  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */\r\n  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */\r\n  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */\r\n  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */\r\n  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */\r\n  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */\r\n  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\r\n  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */\r\n  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */\r\n  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\r\n  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\r\n  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */\r\n  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */\r\n  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */\r\n  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */\r\n  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */\r\n  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */\r\n  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */\r\n  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */\r\n  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */\r\n  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */\r\n  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */\r\n  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */\r\n  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */\r\n  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */\r\n  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */\r\n  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */\r\n  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */\r\n  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */\r\n  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */\r\n  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */\r\n  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */\r\n  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */\r\n  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */\r\n  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */\r\n  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */\r\n  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */\r\n  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */\r\n  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */\r\n  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */\r\n  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */\r\n  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */\r\n  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */\r\n  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */\r\n} RTC_TypeDef;\r\n\r\n/**\r\n  * @brief Serial Audio Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */\r\n  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */\r\n  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */\r\n  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */\r\n} SAI_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\r\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\r\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\r\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\r\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\r\n} SAI_Block_TypeDef;\r\n\r\n/**\r\n  * @brief SPDIF-RX Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */\r\n  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */\r\n  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */\r\n  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */\r\n  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */\r\n  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */\r\n  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */\r\n  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */\r\n} SPDIFRX_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Secure digital input/output Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */\r\n  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */\r\n  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */\r\n  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */\r\n  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */\r\n  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */\r\n  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */\r\n  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */\r\n  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */\r\n  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */\r\n  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */\r\n  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */\r\n  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */\r\n  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */\r\n  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */\r\n  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */\r\n  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */\r\n  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */\r\n  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */\r\n  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */\r\n  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */\r\n  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */\r\n  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */\r\n  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */\r\n  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */\r\n  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */\r\n} SDMMC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Delay Block DLYB\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */\r\n  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */\r\n} DLYB_TypeDef;\r\n\r\n/**\r\n  * @brief HW Semaphore HSEM\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */\r\n  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */\r\n  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */\r\n  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */\r\n  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */\r\n  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */\r\n  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */\r\n  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */\r\n  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */\r\n\r\n} HSEM_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */\r\n  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */\r\n  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */\r\n  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */\r\n} HSEM_Common_TypeDef;\r\n\r\n/**\r\n  * @brief Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */\r\n  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */\r\n  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */\r\n  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */\r\n  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */\r\n  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */\r\n  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */\r\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */\r\n  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */\r\n  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */\r\n  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */\r\n  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */\r\n  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */\r\n  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */\r\n  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */\r\n  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */\r\n  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */\r\n\r\n} SPI_TypeDef;\r\n\r\n/**\r\n  * @brief DTS\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */\r\n  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */\r\n  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */\r\n  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */\r\n  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */\r\n  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */\r\n  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */\r\n  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */\r\n  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */\r\n  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */\r\n  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */\r\n  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */\r\n}\r\nDTS_TypeDef;\r\n\r\n/**\r\n  * @brief TIM\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\r\n  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\r\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\r\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\r\n  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\r\n  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\r\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\r\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\r\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\r\n  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\r\n  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */\r\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\r\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\r\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\r\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\r\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\r\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\r\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\r\n  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\r\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\r\n  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */\r\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\r\n  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\r\n  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\r\n  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */\r\n  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */\r\n  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */\r\n} TIM_TypeDef;\r\n\r\n/**\r\n  * @brief LPTIMIMER\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */\r\n  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */\r\n  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */\r\n  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */\r\n  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */\r\n  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */\r\n  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */\r\n  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */\r\n  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */\r\n  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */\r\n} LPTIM_TypeDef;\r\n\r\n/**\r\n  * @brief Comparator\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */\r\n  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */\r\n  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */\r\n} COMPOPT_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */\r\n} COMP_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\r\n} COMP_Common_TypeDef;\r\n/**\r\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */\r\n  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */\r\n  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */\r\n  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */\r\n  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\r\n  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */\r\n  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */\r\n  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */\r\n  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\r\n  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */\r\n  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */\r\n  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */\r\n} USART_TypeDef;\r\n\r\n/**\r\n  * @brief Single Wire Protocol Master Interface SPWMI\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */\r\n  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */\r\n    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */\r\n  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */\r\n  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */\r\n  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */\r\n  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */\r\n  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */\r\n  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */\r\n  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */\r\n} SWPMI_TypeDef;\r\n\r\n/**\r\n  * @brief Window WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\r\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\r\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\r\n} WWDG_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief RAM_ECC_Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */\r\n  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */\r\n  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */\r\n  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */\r\n  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */\r\n  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */\r\n} RAMECC_MonitorTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */\r\n} RAMECC_TypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @brief Crypto Processor\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */\r\n  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */\r\n  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */\r\n  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */\r\n  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */\r\n  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */\r\n  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */\r\n  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */\r\n  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */\r\n  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */\r\n  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */\r\n  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */\r\n  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */\r\n  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */\r\n  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */\r\n  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */\r\n  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */\r\n  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */\r\n  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */\r\n  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */\r\n  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */\r\n  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */\r\n  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */\r\n  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */\r\n  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */\r\n  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */\r\n  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */\r\n  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */\r\n  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */\r\n  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */\r\n  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */\r\n  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */\r\n  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */\r\n  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */\r\n  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */\r\n  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */\r\n} CRYP_TypeDef;\r\n\r\n/**\r\n  * @brief HASH\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */\r\n  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */\r\n  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */\r\n  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */\r\n  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */\r\n  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */\r\n       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */\r\n  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */\r\n} HASH_TypeDef;\r\n\r\n/**\r\n  * @brief HASH_DIGEST\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */\r\n} HASH_DIGEST_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief RNG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r\n  uint32_t RESERVED;\r\n  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */\r\n} RNG_TypeDef;\r\n\r\n/**\r\n  * @brief MDIOS\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;\r\n  __IO uint32_t WRFR;\r\n  __IO uint32_t CWRFR;\r\n  __IO uint32_t RDFR;\r\n  __IO uint32_t CRDFR;\r\n  __IO uint32_t SR;\r\n  __IO uint32_t CLRFR;\r\n  uint32_t RESERVED[57];\r\n  __IO uint32_t DINR0;\r\n  __IO uint32_t DINR1;\r\n  __IO uint32_t DINR2;\r\n  __IO uint32_t DINR3;\r\n  __IO uint32_t DINR4;\r\n  __IO uint32_t DINR5;\r\n  __IO uint32_t DINR6;\r\n  __IO uint32_t DINR7;\r\n  __IO uint32_t DINR8;\r\n  __IO uint32_t DINR9;\r\n  __IO uint32_t DINR10;\r\n  __IO uint32_t DINR11;\r\n  __IO uint32_t DINR12;\r\n  __IO uint32_t DINR13;\r\n  __IO uint32_t DINR14;\r\n  __IO uint32_t DINR15;\r\n  __IO uint32_t DINR16;\r\n  __IO uint32_t DINR17;\r\n  __IO uint32_t DINR18;\r\n  __IO uint32_t DINR19;\r\n  __IO uint32_t DINR20;\r\n  __IO uint32_t DINR21;\r\n  __IO uint32_t DINR22;\r\n  __IO uint32_t DINR23;\r\n  __IO uint32_t DINR24;\r\n  __IO uint32_t DINR25;\r\n  __IO uint32_t DINR26;\r\n  __IO uint32_t DINR27;\r\n  __IO uint32_t DINR28;\r\n  __IO uint32_t DINR29;\r\n  __IO uint32_t DINR30;\r\n  __IO uint32_t DINR31;\r\n  __IO uint32_t DOUTR0;\r\n  __IO uint32_t DOUTR1;\r\n  __IO uint32_t DOUTR2;\r\n  __IO uint32_t DOUTR3;\r\n  __IO uint32_t DOUTR4;\r\n  __IO uint32_t DOUTR5;\r\n  __IO uint32_t DOUTR6;\r\n  __IO uint32_t DOUTR7;\r\n  __IO uint32_t DOUTR8;\r\n  __IO uint32_t DOUTR9;\r\n  __IO uint32_t DOUTR10;\r\n  __IO uint32_t DOUTR11;\r\n  __IO uint32_t DOUTR12;\r\n  __IO uint32_t DOUTR13;\r\n  __IO uint32_t DOUTR14;\r\n  __IO uint32_t DOUTR15;\r\n  __IO uint32_t DOUTR16;\r\n  __IO uint32_t DOUTR17;\r\n  __IO uint32_t DOUTR18;\r\n  __IO uint32_t DOUTR19;\r\n  __IO uint32_t DOUTR20;\r\n  __IO uint32_t DOUTR21;\r\n  __IO uint32_t DOUTR22;\r\n  __IO uint32_t DOUTR23;\r\n  __IO uint32_t DOUTR24;\r\n  __IO uint32_t DOUTR25;\r\n  __IO uint32_t DOUTR26;\r\n  __IO uint32_t DOUTR27;\r\n  __IO uint32_t DOUTR28;\r\n  __IO uint32_t DOUTR29;\r\n  __IO uint32_t DOUTR30;\r\n  __IO uint32_t DOUTR31;\r\n} MDIOS_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_Core_Registers\r\n  */\r\ntypedef struct\r\n{\r\n __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */\r\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\r\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\r\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\r\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\r\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\r\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\r\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\r\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\r\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\r\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\r\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\r\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\r\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\r\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\r\n  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/\r\n  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/\r\n  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/\r\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\r\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\r\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\r\n  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */\r\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\r\n   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */\r\n    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */\r\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\r\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */\r\n} USB_OTG_GlobalTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_device_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\r\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\r\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\r\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\r\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\r\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\r\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\r\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\r\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\r\n  uint32_t Reserved9;            /*!< Reserved                     824h */\r\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\r\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\r\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\r\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\r\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\r\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\r\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\r\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\r\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\r\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\r\n} USB_OTG_DeviceTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\r\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r\n} USB_OTG_INEndpointTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\r\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r\n} USB_OTG_OUTEndpointTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_Host_Mode_Register_Structures\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\r\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\r\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\r\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\r\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\r\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\r\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\r\n} USB_OTG_HostTypeDef;\r\n\r\n/**\r\n  * @brief USB_OTG_Host_Channel_Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\r\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\r\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\r\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\r\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\r\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\r\n  uint32_t Reserved[2];           /*!< Reserved                                      */\r\n} USB_OTG_HostChannelTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief OCTO Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */\r\n  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */\r\n  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */\r\n  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */\r\n  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */\r\n  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */\r\n  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */\r\n  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */\r\n  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */\r\n  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */\r\n  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */\r\n  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */\r\n  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */\r\n  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */\r\n  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */\r\n  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */\r\n  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */\r\n  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */\r\n  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */\r\n  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */\r\n  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */\r\n  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */\r\n  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */\r\n  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */\r\n  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */\r\n  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */\r\n  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */\r\n  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */\r\n  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */\r\n  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */\r\n  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */\r\n  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */\r\n  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */\r\n  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */\r\n  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */\r\n  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */\r\n  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */\r\n  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */\r\n  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */\r\n  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */\r\n  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */\r\n  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */\r\n  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */\r\n  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */\r\n  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */\r\n  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */\r\n  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */\r\n  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */\r\n  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */\r\n  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */\r\n  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */\r\n  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */\r\n  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */\r\n  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */\r\n} OCTOSPI_TypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @brief OCTO Serial Peripheral Interface IO Manager\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */\r\n  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */\r\n} OCTOSPIM_TypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief OTFD register\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t REG_CONFIGR;\r\n  __IO uint32_t REG_START_ADDR;\r\n  __IO uint32_t REG_END_ADDR;\r\n  __IO uint32_t REG_NONCER0;\r\n  __IO uint32_t REG_NONCER1;\r\n  __IO uint32_t REG_KEYR0;\r\n  __IO uint32_t REG_KEYR1;\r\n  __IO uint32_t REG_KEYR2;\r\n  __IO uint32_t REG_KEYR3;\r\n} OTFDEC_Region_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;\r\n  uint32_t RESERVED1[191];\r\n  __IO uint32_t ISR;\r\n  __IO uint32_t ICR;\r\n  __IO uint32_t IER;\r\n  uint32_t RESERVED2[56];\r\n  __IO uint32_t HWCFGR2;\r\n  __IO uint32_t HWCFGR1;\r\n  __IO uint32_t VERR;\r\n  __IO uint32_t IPIDR;\r\n  __IO uint32_t SIDR;\r\n} OTFDEC_TypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief Global Programmer View\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t      RESERVED0[2036];     /*!< Reserved,                                                                           Address offset: 0x00-0x1FCC     */\r\n  __IO uint32_t AXI_PERIPH_ID_4;     /*!< AXI interconnect - peripheral ID4 register,                                         Address offset: 0x1FD0          */\r\n  uint32_t      AXI_PERIPH_ID_5;     /*!< Reserved,                                                                           Address offset: 0x1FD4          */\r\n  uint32_t      AXI_PERIPH_ID_6;     /*!< Reserved,                                                                           Address offset: 0x1FD8          */\r\n  uint32_t      AXI_PERIPH_ID_7;     /*!< Reserved,                                                                           Address offset: 0x1FDC          */\r\n  __IO uint32_t AXI_PERIPH_ID_0;     /*!< AXI interconnect - peripheral ID0 register,                                         Address offset: 0x1FE0          */\r\n  __IO uint32_t AXI_PERIPH_ID_1;     /*!< AXI interconnect - peripheral ID1 register,                                         Address offset: 0x1FE4          */\r\n  __IO uint32_t AXI_PERIPH_ID_2;     /*!< AXI interconnect - peripheral ID2 register,                                         Address offset: 0x1FE8          */\r\n  __IO uint32_t AXI_PERIPH_ID_3;     /*!< AXI interconnect - peripheral ID3 register,                                         Address offset: 0x1FEC          */\r\n  __IO uint32_t AXI_COMP_ID_0;       /*!< AXI interconnect - component ID0 register,                                          Address offset: 0x1FF0          */\r\n  __IO uint32_t AXI_COMP_ID_1;       /*!< AXI interconnect - component ID1 register,                                          Address offset: 0x1FF4          */\r\n  __IO uint32_t AXI_COMP_ID_2;       /*!< AXI interconnect - component ID2 register,                                          Address offset: 0x1FF8          */\r\n  __IO uint32_t AXI_COMP_ID_3;       /*!< AXI interconnect - component ID3 register,                                          Address offset: 0x1FFC          */\r\n  uint32_t      RESERVED1[2];        /*!< Reserved,                                                                           Address offset: 0x2000-0x2004   */\r\n  __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register,           Address offset: 0x2008          */\r\n  uint32_t      RESERVED2[6];        /*!< Reserved,                                                                           Address offset: 0x200C-0x2020   */\r\n  __IO uint32_t AXI_TARG1_FN_MOD2;   /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register,                      Address offset: 0x2024          */\r\n  uint32_t      RESERVED3;           /*!< Reserved,                                                                           Address offset: 0x2028          */\r\n  __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register,           Address offset: 0x202C          */\r\n  uint32_t      RESERVED4[54];       /*!< Reserved,                                                                           Address offset: 0x2030-0x2104   */\r\n  __IO uint32_t AXI_TARG1_FN_MOD;    /*!< AXI interconnect - TARG 1 issuing functionality modification register,              Address offset: 0x2108          */\r\n  uint32_t      RESERVED5[959];      /*!< Reserved,                                                                           Address offset: 0x210C-0x3004   */\r\n  __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register,           Address offset: 0x3008          */\r\n  uint32_t      RESERVED6[6];        /*!< Reserved,                                                                           Address offset: 0x300C-0x3020   */\r\n  __IO uint32_t AXI_TARG2_FN_MOD2;   /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register,                      Address offset: 0x3024          */\r\n  uint32_t      RESERVED7;           /*!< Reserved,                                                                           Address offset: 0x3028          */\r\n  __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register,           Address offset: 0x302C          */\r\n  uint32_t      RESERVED8[54];       /*!< Reserved,                                                                           Address offset: 0x3030-0x3104   */\r\n  __IO uint32_t AXI_TARG2_FN_MOD;    /*!< AXI interconnect - TARG 2 issuing functionality modification register,              Address offset: 0x3108          */\r\n  uint32_t      RESERVED9[959];      /*!< Reserved,                                                                           Address offset: 0x310C-0x4004   */\r\n  __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;   /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register,          Address offset: 0x4008          */\r\n  uint32_t      RESERVED10[1023];    /*!< Reserved,                                                                           Address offset: 0x400C-0x5004   */\r\n  __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register,           Address offset: 0x5008          */\r\n  uint32_t      RESERVED11[1023];    /*!< Reserved,                                                                           Address offset: 0x500C-0x6004   */\r\n  __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register,           Address offset: 0x6008          */\r\n  uint32_t      RESERVED12[1023];    /*!< Reserved,                                                                           Address offset: 0x600C-0x7004   */\r\n  __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register,           Address offset: 0x7008          */\r\n  uint32_t      RESERVED13[1023];    /*!< Reserved,                                                                           Address offset: 0x700C-0x8004   */\r\n  __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register,           Address offset: 0x8008          */\r\n  uint32_t      RESERVED14[6];       /*!< Reserved,                                                                           Address offset: 0x800C-0x8020   */\r\n  __IO uint32_t AXI_TARG7_FN_MOD2;   /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register,                      Address offset: 0x8024          */\r\n  uint32_t      RESERVED15;          /*!< Reserved,                                                                           Address offset: 0x8028          */\r\n  __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register,           Address offset: 0x802C          */\r\n  uint32_t      RESERVED16[54];      /*!< Reserved,                                                                           Address offset: 0x8030-0x8104   */\r\n  __IO uint32_t AXI_TARG7_FN_MOD;    /*!< AXI interconnect - TARG 7 issuing functionality modification register,              Address offset: 0x8108          */\r\n  uint32_t      RESERVED17[959];     /*!< Reserved,                                                                           Address offset: 0x810C-0x9004   */\r\n  __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register,           Address offset: 0x9008          */\r\n  uint32_t      RESERVED117[6];      /*!< Reserved,                                                                           Address offset: 0x900C-0x9020   */\r\n  __IO uint32_t AXI_TARG8_FN_MOD2;   /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register,                      Address offset: 0x9024          */\r\n  uint32_t      RESERVED118[56];     /*!< Reserved,                                                                           Address offset: 0x9028-0x9104   */\r\n  __IO uint32_t AXI_TARG8_FN_MOD;    /*!< AXI interconnect - TARG 8 issuing functionality modification register,              Address offset: 0x9108          */\r\n  uint32_t      RESERVED119[58310];  /*!< Reserved,                                                                           Address offset: 0x910C-0x42020  */\r\n  __IO uint32_t AXI_INI1_FN_MOD2;    /*!< AXI interconnect - INI 1 functionality modification 2 register,                     Address offset: 0x42024         */\r\n  __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register,                   Address offset: 0x42028         */\r\n  uint32_t      RESERVED18[53];      /*!< Reserved,                                                                           Address offset: 0x4202C-0x420FC */\r\n  __IO uint32_t AXI_INI1_READ_QOS;   /*!< AXI interconnect - INI 1 read QoS register,                                         Address offset: 0x42100         */\r\n  __IO uint32_t AXI_INI1_WRITE_QOS;  /*!< AXI interconnect - INI 1 write QoS register,                                        Address offset: 0x42104         */\r\n  __IO uint32_t AXI_INI1_FN_MOD;     /*!< AXI interconnect - INI 1 issuing functionality modification register,               Address offset: 0x42108         */\r\n  uint32_t      RESERVED19[1021];    /*!< Reserved,                                                                           Address offset: 0x4210C-0x430FC */\r\n  __IO uint32_t AXI_INI2_READ_QOS;   /*!< AXI interconnect - INI 2 read QoS register,                                         Address offset: 0x43100         */\r\n  __IO uint32_t AXI_INI2_WRITE_QOS;  /*!< AXI interconnect - INI 2 write QoS register,                                        Address offset: 0x43104         */\r\n  __IO uint32_t AXI_INI2_FN_MOD;     /*!< AXI interconnect - INI 2 issuing functionality modification register,               Address offset: 0x43108         */\r\n  uint32_t      RESERVED20[966];     /*!< Reserved,                                                                           Address offset: 0x4310C-0x44020 */\r\n  __IO uint32_t AXI_INI3_FN_MOD2;    /*!< AXI interconnect - INI 3 functionality modification 2 register,                     Address offset: 0x44024         */\r\n  __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register,                   Address offset: 0x44028         */\r\n  uint32_t      RESERVED21[53];      /*!< Reserved,                                                                           Address offset: 0x4402C-0x440FC */\r\n  __IO uint32_t AXI_INI3_READ_QOS;   /*!< AXI interconnect - INI 3 read QoS register,                                         Address offset: 0x44100         */\r\n  __IO uint32_t AXI_INI3_WRITE_QOS;  /*!< AXI interconnect - INI 3 write QoS register,                                        Address offset: 0x44104         */\r\n  __IO uint32_t AXI_INI3_FN_MOD;     /*!< AXI interconnect - INI 3 issuing functionality modification register,               Address offset: 0x44108         */\r\n  uint32_t      RESERVED22[1021];    /*!< Reserved,                                                                           Address offset: 0x4410C-0x450FC */\r\n  __IO uint32_t AXI_INI4_READ_QOS;   /*!< AXI interconnect - INI 4 read QoS register,                                         Address offset: 0x45100         */\r\n  __IO uint32_t AXI_INI4_WRITE_QOS;  /*!< AXI interconnect - INI 4 write QoS register,                                        Address offset: 0x45104         */\r\n  __IO uint32_t AXI_INI4_FN_MOD;     /*!< AXI interconnect - INI 4 issuing functionality modification register,               Address offset: 0x45108         */\r\n  uint32_t      RESERVED23[1021];    /*!< Reserved,                                                                           Address offset: 0x4510C-0x460FC */\r\n  __IO uint32_t AXI_INI5_READ_QOS;   /*!< AXI interconnect - INI 5 read QoS register,                                         Address offset: 0x46100         */\r\n  __IO uint32_t AXI_INI5_WRITE_QOS;  /*!< AXI interconnect - INI 5 write QoS register,                                        Address offset: 0x46104         */\r\n  __IO uint32_t AXI_INI5_FN_MOD;     /*!< AXI interconnect - INI 5 issuing functionality modification register,               Address offset: 0x46108         */\r\n  uint32_t      RESERVED24[1021];    /*!< Reserved,                                                                           Address offset: 0x4610C-0x470FC */\r\n  __IO uint32_t AXI_INI6_READ_QOS;   /*!< AXI interconnect - INI 6 read QoS register,                                         Address offset: 0x47100         */\r\n  __IO uint32_t AXI_INI6_WRITE_QOS;  /*!< AXI interconnect - INI 6 write QoS register,                                        Address offset: 0x47104         */\r\n  __IO uint32_t AXI_INI6_FN_MOD;     /*!< AXI interconnect - INI 6 issuing functionality modification register,               Address offset: 0x47108         */\r\n\r\n} GPV_TypeDef;\r\n\r\n/** @addtogroup Peripheral_memory_map\r\n  * @{\r\n  */\r\n#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */\r\n#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */\r\n#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */\r\n#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */\r\n#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */\r\n#define D1_AXISRAM1_BASE           (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI                */\r\n#define D1_AXISRAM2_BASE           (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity)  */\r\n#define D1_AXISRAM_BASE            D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI             */\r\n\r\n#define D2_AHBSRAM1_BASE          (0x30000000UL)   /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge    */\r\n#define D2_AHBSRAM2_BASE          (0x30004000UL)   /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge    */\r\n#define D2_AHBSRAM_BASE           D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */\r\n\r\n#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */\r\n#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge                               */\r\n\r\n#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */\r\n#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */\r\n#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */\r\n\r\n#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */\r\n#define FLASH_END                 (0x080FFFFFUL) /*!< FLASH end address                                                                       */\r\n\r\n\r\n/* Legacy define */\r\n#define FLASH_BASE                FLASH_BANK1_BASE\r\n\r\n/*!< Device electronic signature memory map */\r\n#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */\r\n#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */\r\n\r\n\r\n/*!< Peripheral memory map */\r\n#define D2_APB1PERIPH_BASE        PERIPH_BASE\r\n#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r\n#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r\n#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)\r\n\r\n#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\r\n#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)\r\n\r\n#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)\r\n#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)\r\n\r\n/*!< Legacy Peripheral memory map */\r\n#define APB1PERIPH_BASE        PERIPH_BASE\r\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)\r\n\r\n\r\n/*!< D1_AHB1PERIPH peripherals */\r\n\r\n#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)\r\n#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)\r\n#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)\r\n#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)\r\n#define OCTOSPI1_R_BASE       (D1_AHB1PERIPH_BASE + 0x5000UL)\r\n#define DLYB_OCTOSPI1_BASE    (D1_AHB1PERIPH_BASE + 0x6000UL)\r\n#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)\r\n#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)\r\n#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)\r\n#define OCTOSPI2_R_BASE       (D1_AHB1PERIPH_BASE + 0xA000UL)\r\n#define DLYB_OCTOSPI2_BASE    (D1_AHB1PERIPH_BASE + 0xB000UL)\r\n#define OCTOSPIM_BASE         (D1_AHB1PERIPH_BASE + 0xB400UL)\r\n\r\n#define OTFDEC1_BASE          (D1_AHB1PERIPH_BASE + 0xB800UL)\r\n#define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)\r\n#define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)\r\n#define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)\r\n#define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)\r\n#define OTFDEC2_BASE          (D1_AHB1PERIPH_BASE + 0xBC00UL)\r\n#define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)\r\n#define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)\r\n#define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)\r\n#define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)\r\n\r\n/*!< D2_AHB1PERIPH peripherals */\r\n\r\n#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)\r\n#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)\r\n#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)\r\n#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)\r\n#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)\r\n#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)\r\n#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)\r\n#define ETH_MAC_BASE            (ETH_BASE)\r\n\r\n/*!< USB registers base address */\r\n#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)\r\n#define USB_OTG_GLOBAL_BASE                  (0x000UL)\r\n#define USB_OTG_DEVICE_BASE                  (0x800UL)\r\n#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)\r\n#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)\r\n#define USB_OTG_EP_REG_SIZE                  (0x20UL)\r\n#define USB_OTG_HOST_BASE                    (0x400UL)\r\n#define USB_OTG_HOST_PORT_BASE               (0x440UL)\r\n#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)\r\n#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)\r\n#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)\r\n#define USB_OTG_FIFO_BASE                    (0x1000UL)\r\n#define USB_OTG_FIFO_SIZE                    (0x1000UL)\r\n\r\n/*!< D2_AHB2PERIPH peripherals */\r\n\r\n#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)\r\n#define PSSI_BASE              (D2_AHB2PERIPH_BASE + 0x0400UL)\r\n#define CRYP_BASE              (D2_AHB2PERIPH_BASE + 0x1000UL)\r\n#define HASH_BASE              (D2_AHB2PERIPH_BASE + 0x1400UL)\r\n#define HASH_DIGEST_BASE       (D2_AHB2PERIPH_BASE + 0x1710UL)\r\n#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)\r\n#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)\r\n#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)\r\n#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)\r\n#define FMAC_BASE              (D2_AHB2PERIPH_BASE + 0x4000UL)\r\n#define CORDIC_BASE            (D2_AHB2PERIPH_BASE + 0x4400UL)\r\n\r\n/*!< D3_AHB1PERIPH peripherals */\r\n#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)\r\n#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)\r\n#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)\r\n#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)\r\n#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)\r\n#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)\r\n#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)\r\n#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)\r\n#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)\r\n#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)\r\n#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)\r\n#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)\r\n#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)\r\n#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)\r\n#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)\r\n#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)\r\n#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)\r\n#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)\r\n#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)\r\n\r\n/*!< D1_APB1PERIPH peripherals */\r\n#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)\r\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)\r\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)\r\n#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)\r\n\r\n/*!< D2_APB1PERIPH peripherals */\r\n#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)\r\n#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)\r\n#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)\r\n#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)\r\n#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)\r\n#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)\r\n#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)\r\n#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)\r\n#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)\r\n#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)\r\n\r\n\r\n#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)\r\n#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)\r\n#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)\r\n#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)\r\n#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)\r\n#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)\r\n#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)\r\n#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)\r\n#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)\r\n#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)\r\n#define I2C5_BASE             (D2_APB1PERIPH_BASE + 0x6400UL)\r\n#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)\r\n#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)\r\n#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)\r\n#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)\r\n#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)\r\n#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)\r\n#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)\r\n#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)\r\n#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)\r\n#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)\r\n#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)\r\n#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)\r\n#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)\r\n#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)\r\n#define FDCAN3_BASE           (D2_APB1PERIPH_BASE + 0xD400UL)\r\n#define TIM23_BASE            (D2_APB1PERIPH_BASE + 0xE000UL)\r\n#define TIM24_BASE            (D2_APB1PERIPH_BASE + 0xE400UL)\r\n\r\n/*!< D2_APB2PERIPH peripherals */\r\n\r\n#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)\r\n#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)\r\n#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)\r\n#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)\r\n#define UART9_BASE            (D2_APB2PERIPH_BASE + 0x1800UL)\r\n#define USART10_BASE          (D2_APB2PERIPH_BASE + 0x1C00UL)\r\n#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)\r\n#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)\r\n#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)\r\n#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)\r\n#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)\r\n#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)\r\n#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)\r\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)\r\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)\r\n#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7800UL)\r\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)\r\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)\r\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)\r\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)\r\n#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)\r\n#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)\r\n#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)\r\n#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)\r\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)\r\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)\r\n#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)\r\n#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)\r\n\r\n\r\n/*!< D3_APB1PERIPH peripherals */\r\n#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)\r\n#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)\r\n#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)\r\n#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)\r\n#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)\r\n#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)\r\n#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)\r\n#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)\r\n#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)\r\n#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)\r\n#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)\r\n#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)\r\n#define COMP1_BASE            (COMP12_BASE + 0x0CUL)\r\n#define COMP2_BASE            (COMP12_BASE + 0x10UL)\r\n#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)\r\n#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)\r\n#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)\r\n\r\n\r\n#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)\r\n#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)\r\n#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)\r\n\r\n#define DTS_BASE              (D3_APB1PERIPH_BASE + 0x6800UL)\r\n\r\n\r\n\r\n#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)\r\n#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)\r\n#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)\r\n#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)\r\n#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)\r\n#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)\r\n#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)\r\n#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)\r\n\r\n#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)\r\n#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)\r\n#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)\r\n#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)\r\n#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)\r\n#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)\r\n#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)\r\n#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)\r\n\r\n#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)\r\n#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)\r\n#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)\r\n#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)\r\n#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)\r\n#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)\r\n#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)\r\n#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)\r\n\r\n#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)\r\n#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)\r\n\r\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\r\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\r\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\r\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\r\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\r\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\r\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\r\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\r\n\r\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\r\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\r\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\r\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\r\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\r\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\r\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\r\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\r\n\r\n#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)\r\n#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)\r\n#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)\r\n#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)\r\n#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)\r\n#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)\r\n#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)\r\n#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)\r\n#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)\r\n#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)\r\n#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)\r\n#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)\r\n#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)\r\n#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)\r\n#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)\r\n#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)\r\n\r\n#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)\r\n#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)\r\n#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)\r\n#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)\r\n#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)\r\n#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)\r\n#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)\r\n#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)\r\n\r\n#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)\r\n#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)\r\n\r\n/*!< FMC Banks registers base  address */\r\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)\r\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)\r\n#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)\r\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)\r\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)\r\n\r\n/* Debug MCU registers base address */\r\n#define DBGMCU_BASE           (0x5C001000UL)\r\n\r\n#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)\r\n#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)\r\n#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)\r\n#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)\r\n#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)\r\n#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)\r\n#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)\r\n#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)\r\n#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)\r\n#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)\r\n#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)\r\n#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)\r\n#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)\r\n#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)\r\n#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)\r\n#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)\r\n\r\n#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)\r\n#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)\r\n#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)\r\n#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)\r\n#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)\r\n#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL)\r\n\r\n#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)\r\n#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)\r\n#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)\r\n\r\n#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)\r\n#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)\r\n\r\n\r\n\r\n#define GPV_BASE       (PERIPH_BASE + 0x11000000UL)   /*!<  GPV_BASE       (PERIPH_BASE + 0x11000000UL)                    */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Peripheral_declaration\r\n  * @{\r\n  */\r\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\r\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\r\n#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)\r\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r\n#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)\r\n\r\n\r\n#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)\r\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\r\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\r\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\r\n#define USART2              ((USART_TypeDef *) USART2_BASE)\r\n#define USART3              ((USART_TypeDef *) USART3_BASE)\r\n#define USART6              ((USART_TypeDef *) USART6_BASE)\r\n#define USART10             ((USART_TypeDef *) USART10_BASE)\r\n#define UART7               ((USART_TypeDef *) UART7_BASE)\r\n#define UART8               ((USART_TypeDef *) UART8_BASE)\r\n#define UART9               ((USART_TypeDef *) UART9_BASE)\r\n#define CRS                 ((CRS_TypeDef *) CRS_BASE)\r\n#define UART4               ((USART_TypeDef *) UART4_BASE)\r\n#define UART5               ((USART_TypeDef *) UART5_BASE)\r\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r\n#define I2C4                ((I2C_TypeDef *) I2C4_BASE)\r\n#define I2C5                ((I2C_TypeDef *) I2C5_BASE)\r\n#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\r\n#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)\r\n#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)\r\n#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)\r\n#define TIM23               ((TIM_TypeDef *) TIM23_BASE)\r\n#define TIM24               ((TIM_TypeDef *) TIM24_BASE)\r\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\r\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\r\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r\n#define DAC1                ((DAC_TypeDef *) DAC1_BASE)\r\n#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\r\n#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)\r\n#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)\r\n#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)\r\n#define DTS                 ((DTS_TypeDef *) DTS_BASE)\r\n#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)\r\n#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)\r\n\r\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r\n#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)\r\n#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\r\n#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\r\n#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)\r\n#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)\r\n#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)\r\n#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)\r\n\r\n\r\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r\n#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)\r\n#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)\r\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\r\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r\n#define USART1              ((USART_TypeDef *) USART1_BASE)\r\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\r\n#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\r\n#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\r\n#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\r\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r\n#define SAI4                ((SAI_TypeDef *) SAI4_BASE)\r\n#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)\r\n#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)\r\n\r\n#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\r\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r\n#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r\n#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r\n#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r\n#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r\n#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r\n#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r\n#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)\r\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\r\n#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)\r\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r\n\r\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\r\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\r\n\r\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r\n#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)\r\n#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\r\n\r\n#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)\r\n#define HASH                ((HASH_TypeDef *) HASH_BASE)\r\n#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)\r\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r\n#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)\r\n#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)\r\n#define FMAC                ((FMAC_TypeDef *) FMAC_BASE)\r\n#define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)\r\n\r\n#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)\r\n#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)\r\n#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)\r\n#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)\r\n#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)\r\n#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)\r\n#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)\r\n#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)\r\n#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)\r\n\r\n#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)\r\n#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)\r\n#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)\r\n#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)\r\n#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)\r\n#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)\r\n#define RAMECC1_Monitor6     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)\r\n\r\n#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)\r\n#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)\r\n#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)\r\n#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)\r\n\r\n#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)\r\n#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)\r\n#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)\r\n\r\n#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)\r\n#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)\r\n#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)\r\n#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)\r\n#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)\r\n#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)\r\n#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)\r\n#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)\r\n#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)\r\n\r\n\r\n#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)\r\n#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)\r\n#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)\r\n#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)\r\n#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)\r\n#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)\r\n#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)\r\n#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)\r\n\r\n#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)\r\n#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)\r\n\r\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r\n\r\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r\n\r\n\r\n#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\r\n#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\r\n#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\r\n#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\r\n#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\r\n#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\r\n#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\r\n#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\r\n#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\r\n#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\r\n#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\r\n#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\r\n#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\r\n#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)\r\n#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)\r\n#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)\r\n#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)\r\n\r\n#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\r\n#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\r\n#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\r\n#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\r\n#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)\r\n#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)\r\n#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)\r\n#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)\r\n\r\n#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)\r\n#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\r\n\r\n\r\n#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r\n#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r\n#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\r\n#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r\n#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r\n\r\n#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)\r\n#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)\r\n#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)\r\n#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)\r\n#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)\r\n\r\n#define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)\r\n#define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)\r\n#define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)\r\n#define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)\r\n#define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)\r\n\r\n#define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)\r\n#define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)\r\n#define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)\r\n#define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)\r\n#define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)\r\n\r\n#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)\r\n#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)\r\n\r\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r\n\r\n#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)\r\n#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))\r\n\r\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\r\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r\n\r\n#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)\r\n\r\n#define ETH                 ((ETH_TypeDef *)ETH_BASE)\r\n#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)\r\n#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)\r\n#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)\r\n#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)\r\n#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)\r\n#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)\r\n#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)\r\n#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)\r\n#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)\r\n#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)\r\n#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)\r\n#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)\r\n#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)\r\n#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)\r\n#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)\r\n#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)\r\n#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)\r\n\r\n\r\n#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)\r\n\r\n/* Legacy defines */\r\n#define USB_OTG_HS                   USB1_OTG_HS\r\n#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE\r\n\r\n#define GPV                ((GPV_TypeDef *) GPV_BASE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_constants\r\n  * @{\r\n  */\r\n\r\n  /** @addtogroup Peripheral_Registers_Bits_Definition\r\n  * @{\r\n  */\r\n\r\n/******************************************************************************/\r\n/*                         Peripheral Registers_Bits_Definition               */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Analog to Digital Converter                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************************  ADC VERSION  ********************************/\r\n#define ADC_VER_V5_V90\r\n/********************  Bit definition for ADC_ISR register  ********************/\r\n#define ADC_ISR_ADRDY_Pos                 (0U)\r\n#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */\r\n#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */\r\n#define ADC_ISR_EOSMP_Pos                 (1U)\r\n#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */\r\n#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */\r\n#define ADC_ISR_EOC_Pos                   (2U)\r\n#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */\r\n#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */\r\n#define ADC_ISR_EOS_Pos                   (3U)\r\n#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */\r\n#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */\r\n#define ADC_ISR_OVR_Pos                   (4U)\r\n#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */\r\n#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */\r\n#define ADC_ISR_JEOC_Pos                  (5U)\r\n#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */\r\n#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */\r\n#define ADC_ISR_JEOS_Pos                  (6U)\r\n#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */\r\n#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */\r\n#define ADC_ISR_AWD1_Pos                  (7U)\r\n#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */\r\n#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */\r\n#define ADC_ISR_AWD2_Pos                  (8U)\r\n#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */\r\n#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */\r\n#define ADC_ISR_AWD3_Pos                  (9U)\r\n#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */\r\n#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */\r\n#define ADC_ISR_JQOVF_Pos                 (10U)\r\n#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */\r\n#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */\r\n#define ADC_ISR_LDORDY_Pos                 (12U)\r\n#define ADC_ISR_LDORDY_Msk                 (0x1UL << ADC_ISR_LDORDY_Pos)         /*!< 0x00001000 */\r\n#define ADC_ISR_LDORDY                     ADC_ISR_LDORDY_Msk                    /*!< ADC LDO Ready (LDORDY) flag  */\r\n\r\n/********************  Bit definition for ADC_IER register  ********************/\r\n#define ADC_IER_ADRDYIE_Pos               (0U)\r\n#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */\r\n#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */\r\n#define ADC_IER_EOSMPIE_Pos               (1U)\r\n#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */\r\n#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */\r\n#define ADC_IER_EOCIE_Pos                 (2U)\r\n#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */\r\n#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */\r\n#define ADC_IER_EOSIE_Pos                 (3U)\r\n#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */\r\n#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */\r\n#define ADC_IER_OVRIE_Pos                 (4U)\r\n#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */\r\n#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */\r\n#define ADC_IER_JEOCIE_Pos                (5U)\r\n#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */\r\n#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */\r\n#define ADC_IER_JEOSIE_Pos                (6U)\r\n#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */\r\n#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */\r\n#define ADC_IER_AWD1IE_Pos                (7U)\r\n#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */\r\n#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */\r\n#define ADC_IER_AWD2IE_Pos                (8U)\r\n#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */\r\n#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */\r\n#define ADC_IER_AWD3IE_Pos                (9U)\r\n#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */\r\n#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */\r\n#define ADC_IER_JQOVFIE_Pos               (10U)\r\n#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */\r\n#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */\r\n\r\n/********************  Bit definition for ADC_CR register  ********************/\r\n#define ADC_CR_ADEN_Pos                   (0U)\r\n#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */\r\n#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */\r\n#define ADC_CR_ADDIS_Pos                  (1U)\r\n#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */\r\n#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */\r\n#define ADC_CR_ADSTART_Pos                (2U)\r\n#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */\r\n#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */\r\n#define ADC_CR_JADSTART_Pos               (3U)\r\n#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */\r\n#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */\r\n#define ADC_CR_ADSTP_Pos                  (4U)\r\n#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */\r\n#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */\r\n#define ADC_CR_JADSTP_Pos                 (5U)\r\n#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */\r\n#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */\r\n#define ADC_CR_BOOST_Pos                  (8U)\r\n#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */\r\n#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */\r\n#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */\r\n#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */\r\n#define ADC_CR_ADCALLIN_Pos               (16U)\r\n#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */\r\n#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */\r\n#define ADC_CR_LINCALRDYW1_Pos            (22U)\r\n#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */\r\n#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */\r\n#define ADC_CR_LINCALRDYW2_Pos            (23U)\r\n#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */\r\n#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */\r\n#define ADC_CR_LINCALRDYW3_Pos            (24U)\r\n#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */\r\n#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */\r\n#define ADC_CR_LINCALRDYW4_Pos            (25U)\r\n#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */\r\n#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */\r\n#define ADC_CR_LINCALRDYW5_Pos            (26U)\r\n#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */\r\n#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */\r\n#define ADC_CR_LINCALRDYW6_Pos            (27U)\r\n#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */\r\n#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */\r\n#define ADC_CR_ADVREGEN_Pos               (28U)\r\n#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */\r\n#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */\r\n#define ADC_CR_DEEPPWD_Pos                (29U)\r\n#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */\r\n#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */\r\n#define ADC_CR_ADCALDIF_Pos               (30U)\r\n#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */\r\n#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */\r\n#define ADC_CR_ADCAL_Pos                  (31U)\r\n#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */\r\n#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */\r\n\r\n/********************  Bit definition for ADC_CFGR register  ********************/\r\n#define ADC_CFGR_DMNGT_Pos                (0U)\r\n#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */\r\n#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */\r\n#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */\r\n#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */\r\n\r\n#define ADC_CFGR_RES_Pos                  (2U)\r\n#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */\r\n#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */\r\n#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */\r\n#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */\r\n#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */\r\n\r\n#define ADC_CFGR_EXTSEL_Pos               (5U)\r\n#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */\r\n#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */\r\n#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */\r\n#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */\r\n#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */\r\n#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */\r\n#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */\r\n\r\n#define ADC_CFGR_EXTEN_Pos                (10U)\r\n#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */\r\n#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */\r\n#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */\r\n#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */\r\n\r\n#define ADC_CFGR_OVRMOD_Pos               (12U)\r\n#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */\r\n#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */\r\n#define ADC_CFGR_CONT_Pos                 (13U)\r\n#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */\r\n#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */\r\n#define ADC_CFGR_AUTDLY_Pos               (14U)\r\n#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */\r\n#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */\r\n\r\n#define ADC_CFGR_DISCEN_Pos               (16U)\r\n#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */\r\n#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */\r\n\r\n#define ADC_CFGR_DISCNUM_Pos              (17U)\r\n#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */\r\n#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */\r\n#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */\r\n#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */\r\n#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */\r\n\r\n#define ADC_CFGR_JDISCEN_Pos              (20U)\r\n#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */\r\n#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */\r\n#define ADC_CFGR_JQM_Pos                  (21U)\r\n#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */\r\n#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */\r\n#define ADC_CFGR_AWD1SGL_Pos              (22U)\r\n#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */\r\n#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */\r\n#define ADC_CFGR_AWD1EN_Pos               (23U)\r\n#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */\r\n#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */\r\n#define ADC_CFGR_JAWD1EN_Pos              (24U)\r\n#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */\r\n#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */\r\n#define ADC_CFGR_JAUTO_Pos                (25U)\r\n#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */\r\n#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */\r\n\r\n#define ADC_CFGR_AWD1CH_Pos               (26U)\r\n#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */\r\n#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */\r\n#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */\r\n#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */\r\n#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */\r\n#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */\r\n#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */\r\n\r\n#define ADC_CFGR_JQDIS_Pos                (31U)\r\n#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */\r\n#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */\r\n\r\n#define ADC3_CFGR_DMAEN_Pos             (0U)\r\n#define ADC3_CFGR_DMAEN_Msk             (0x1UL << ADC3_CFGR_DMAEN_Pos)           /*!< 0x00000001 */\r\n#define ADC3_CFGR_DMAEN                 ADC3_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */\r\n#define ADC3_CFGR_DMACFG_Pos            (1U)\r\n#define ADC3_CFGR_DMACFG_Msk            (0x1UL << ADC3_CFGR_DMACFG_Pos)          /*!< 0x00000002 */\r\n#define ADC3_CFGR_DMACFG                ADC3_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */\r\n\r\n#define ADC3_CFGR_RES_Pos               (3U)\r\n#define ADC3_CFGR_RES_Msk               (0x3UL << ADC3_CFGR_RES_Pos)             /*!< 0x00000018 */\r\n#define ADC3_CFGR_RES                   ADC3_CFGR_RES_Msk                        /*!< ADC data resolution */\r\n#define ADC3_CFGR_RES_0                 (0x1UL << ADC3_CFGR_RES_Pos)             /*!< 0x00000008 */\r\n#define ADC3_CFGR_RES_1                 (0x2UL << ADC3_CFGR_RES_Pos)             /*!< 0x00000010 */\r\n\r\n#define ADC3_CFGR_ALIGN_Pos             (15U)\r\n#define ADC3_CFGR_ALIGN_Msk             (0x1UL << ADC3_CFGR_ALIGN_Pos)           /*!< 0x00008000 */\r\n#define ADC3_CFGR_ALIGN                 ADC3_CFGR_ALIGN_Msk                      /*!< ADC data alignment */\r\n/********************  Bit definition for ADC_CFGR2 register  ********************/\r\n#define ADC_CFGR2_ROVSE_Pos               (0U)\r\n#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */\r\n#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */\r\n#define ADC_CFGR2_JOVSE_Pos               (1U)\r\n#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */\r\n#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */\r\n\r\n#define ADC_CFGR2_OVSS_Pos                (5U)\r\n#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */\r\n#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */\r\n#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */\r\n#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */\r\n#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */\r\n#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */\r\n\r\n#define ADC_CFGR2_TROVS_Pos               (9U)\r\n#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */\r\n#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */\r\n#define ADC_CFGR2_ROVSM_Pos               (10U)\r\n#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */\r\n#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */\r\n\r\n#define ADC_CFGR2_RSHIFT1_Pos             (11U)\r\n#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */\r\n#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */\r\n#define ADC_CFGR2_RSHIFT2_Pos             (12U)\r\n#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */\r\n#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */\r\n#define ADC_CFGR2_RSHIFT3_Pos             (13U)\r\n#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */\r\n#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */\r\n#define ADC_CFGR2_RSHIFT4_Pos             (14U)\r\n#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */\r\n#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */\r\n\r\n#define ADC_CFGR2_OVSR_Pos                (16U)\r\n#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */\r\n#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */\r\n#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */\r\n#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */\r\n#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */\r\n#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */\r\n#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */\r\n#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */\r\n#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */\r\n#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */\r\n#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */\r\n#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */\r\n\r\n#define ADC_CFGR2_LSHIFT_Pos              (28U)\r\n#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */\r\n#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */\r\n#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */\r\n#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */\r\n#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */\r\n#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */\r\n\r\n#define ADC3_CFGR2_OVSR_Pos             (2U)\r\n#define ADC3_CFGR2_OVSR_Msk             (0x7UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x0000001C */\r\n#define ADC3_CFGR2_OVSR                 ADC3_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */\r\n#define ADC3_CFGR2_OVSR_0               (0x1UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x00000004 */\r\n#define ADC3_CFGR2_OVSR_1               (0x2UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x00000008 */\r\n#define ADC3_CFGR2_OVSR_2               (0x4UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x00000010 */\r\n\r\n#define ADC3_CFGR2_SWTRIG_Pos           (25U)\r\n#define ADC3_CFGR2_SWTRIG_Msk           (0x1UL << ADC3_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */\r\n#define ADC3_CFGR2_SWTRIG               ADC3_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */\r\n#define ADC3_CFGR2_BULB_Pos             (26U)\r\n#define ADC3_CFGR2_BULB_Msk             (0x1UL << ADC3_CFGR2_BULB_Pos)           /*!< 0x04000000 */\r\n#define ADC3_CFGR2_BULB                 ADC3_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */\r\n#define ADC3_CFGR2_SMPTRIG_Pos          (27U)\r\n#define ADC3_CFGR2_SMPTRIG_Msk          (0x1UL << ADC3_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */\r\n#define ADC3_CFGR2_SMPTRIG              ADC3_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */\r\n/********************  Bit definition for ADC_SMPR1 register  ********************/\r\n#define ADC_SMPR1_SMP0_Pos                (0U)\r\n#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */\r\n#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */\r\n#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */\r\n#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */\r\n#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */\r\n\r\n#define ADC_SMPR1_SMP1_Pos                (3U)\r\n#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */\r\n#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */\r\n#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */\r\n#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */\r\n#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */\r\n\r\n#define ADC_SMPR1_SMP2_Pos                (6U)\r\n#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */\r\n#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */\r\n#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */\r\n#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */\r\n#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */\r\n\r\n#define ADC_SMPR1_SMP3_Pos                (9U)\r\n#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */\r\n#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */\r\n#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */\r\n#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */\r\n#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */\r\n\r\n#define ADC_SMPR1_SMP4_Pos                (12U)\r\n#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */\r\n#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */\r\n#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */\r\n#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */\r\n#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */\r\n\r\n#define ADC_SMPR1_SMP5_Pos                (15U)\r\n#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */\r\n#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */\r\n#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */\r\n#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */\r\n#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */\r\n\r\n#define ADC_SMPR1_SMP6_Pos                (18U)\r\n#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */\r\n#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */\r\n#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */\r\n#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */\r\n#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */\r\n\r\n#define ADC_SMPR1_SMP7_Pos                (21U)\r\n#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */\r\n#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */\r\n#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */\r\n#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */\r\n#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */\r\n\r\n#define ADC_SMPR1_SMP8_Pos                (24U)\r\n#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */\r\n#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */\r\n#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */\r\n#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */\r\n#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */\r\n\r\n#define ADC_SMPR1_SMP9_Pos                (27U)\r\n#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */\r\n#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */\r\n#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */\r\n#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */\r\n#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for ADC_SMPR2 register  ********************/\r\n#define ADC_SMPR2_SMP10_Pos               (0U)\r\n#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */\r\n#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */\r\n#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */\r\n#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */\r\n#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */\r\n\r\n#define ADC_SMPR2_SMP11_Pos               (3U)\r\n#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */\r\n#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */\r\n#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */\r\n#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */\r\n#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */\r\n\r\n#define ADC_SMPR2_SMP12_Pos               (6U)\r\n#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */\r\n#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */\r\n#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */\r\n#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */\r\n#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */\r\n\r\n#define ADC_SMPR2_SMP13_Pos               (9U)\r\n#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */\r\n#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */\r\n#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */\r\n#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */\r\n#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */\r\n\r\n#define ADC_SMPR2_SMP14_Pos               (12U)\r\n#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */\r\n#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */\r\n#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */\r\n#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */\r\n#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */\r\n\r\n#define ADC_SMPR2_SMP15_Pos               (15U)\r\n#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */\r\n#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */\r\n#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */\r\n#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */\r\n#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */\r\n\r\n#define ADC_SMPR2_SMP16_Pos               (18U)\r\n#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */\r\n#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */\r\n#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */\r\n#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */\r\n#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */\r\n\r\n#define ADC_SMPR2_SMP17_Pos               (21U)\r\n#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */\r\n#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */\r\n#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */\r\n#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */\r\n#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */\r\n\r\n#define ADC_SMPR2_SMP18_Pos               (24U)\r\n#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */\r\n#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */\r\n#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */\r\n#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */\r\n#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */\r\n\r\n#define ADC_SMPR2_SMP19_Pos               (27U)\r\n#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */\r\n#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */\r\n#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */\r\n#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */\r\n#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for ADC_PCSEL register  ********************/\r\n#define ADC_PCSEL_PCSEL_Pos               (0U)\r\n#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */\r\n#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */\r\n#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */\r\n#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */\r\n#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */\r\n#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */\r\n#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */\r\n#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */\r\n#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */\r\n#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */\r\n#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */\r\n#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */\r\n#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */\r\n#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */\r\n#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */\r\n#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */\r\n#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */\r\n#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */\r\n#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */\r\n#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */\r\n#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */\r\n#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */\r\n\r\n/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/\r\n#define ADC_LTR_LT_Pos                    (0U)\r\n#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */\r\n#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */\r\n\r\n/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/\r\n#define ADC_HTR_HT_Pos                    (0U)\r\n#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */\r\n#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */\r\n\r\n/********************  Bit definition for ADC3_TR1 register  *******************/\r\n#define ADC3_TR1_LT1_Pos                (0U)\r\n#define ADC3_TR1_LT1_Msk                (0xFFFUL << ADC3_TR1_LT1_Pos)            /*!< 0x00000FFF */\r\n#define ADC3_TR1_LT1                    ADC3_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */\r\n\r\n#define ADC3_TR1_AWDFILT_Pos            (12U)\r\n#define ADC3_TR1_AWDFILT_Msk            (0x7UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00007000 */\r\n#define ADC3_TR1_AWDFILT                ADC3_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */\r\n#define ADC3_TR1_AWDFILT_0              (0x1UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00001000 */\r\n#define ADC3_TR1_AWDFILT_1              (0x2UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00002000 */\r\n#define ADC3_TR1_AWDFILT_2              (0x4UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00004000 */\r\n\r\n#define ADC3_TR1_HT1_Pos                (16U)\r\n#define ADC3_TR1_HT1_Msk                (0xFFFUL << ADC3_TR1_HT1_Pos)            /*!< 0x0FFF0000 */\r\n#define ADC3_TR1_HT1                    ADC3_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */\r\n\r\n/********************  Bit definition for ADC3_TR2 register  *******************/\r\n#define ADC3_TR2_LT2_Pos                (0U)\r\n#define ADC3_TR2_LT2_Msk                (0xFFUL << ADC3_TR2_LT2_Pos)             /*!< 0x000000FF */\r\n#define ADC3_TR2_LT2                    ADC3_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */\r\n\r\n#define ADC3_TR2_HT2_Pos                (16U)\r\n#define ADC3_TR2_HT2_Msk                (0xFFUL << ADC3_TR2_HT2_Pos)             /*!< 0x00FF0000 */\r\n#define ADC3_TR2_HT2                    ADC3_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */\r\n\r\n/********************  Bit definition for ADC3_TR3 register  *******************/\r\n#define ADC3_TR3_LT3_Pos                (0U)\r\n#define ADC3_TR3_LT3_Msk                (0xFFUL << ADC3_TR3_LT3_Pos)             /*!< 0x000000FF */\r\n#define ADC3_TR3_LT3                    ADC3_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */\r\n\r\n#define ADC3_TR3_HT3_Pos                (16U)\r\n#define ADC3_TR3_HT3_Msk                (0xFFUL << ADC3_TR3_HT3_Pos)             /*!< 0x00FF0000 */\r\n#define ADC3_TR3_HT3                    ADC3_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */\r\n\r\n/********************  Bit definition for ADC_SQR1 register  ********************/\r\n#define ADC_SQR1_L_Pos                    (0U)\r\n#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */\r\n#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence length */\r\n#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */\r\n#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */\r\n#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */\r\n#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */\r\n\r\n#define ADC_SQR1_SQ1_Pos                  (6U)\r\n#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */\r\n#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */\r\n#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */\r\n#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */\r\n#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */\r\n#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */\r\n#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */\r\n\r\n#define ADC_SQR1_SQ2_Pos                  (12U)\r\n#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */\r\n#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */\r\n#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */\r\n#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */\r\n#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */\r\n#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */\r\n#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */\r\n\r\n#define ADC_SQR1_SQ3_Pos                  (18U)\r\n#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */\r\n#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */\r\n#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */\r\n#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */\r\n#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */\r\n#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */\r\n#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */\r\n\r\n#define ADC_SQR1_SQ4_Pos                  (24U)\r\n#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */\r\n#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */\r\n#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */\r\n#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */\r\n#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */\r\n#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */\r\n#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */\r\n\r\n/********************  Bit definition for ADC_SQR2 register  ********************/\r\n#define ADC_SQR2_SQ5_Pos                  (0U)\r\n#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */\r\n#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */\r\n#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */\r\n#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */\r\n#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */\r\n#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */\r\n#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */\r\n\r\n#define ADC_SQR2_SQ6_Pos                  (6U)\r\n#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */\r\n#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */\r\n#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */\r\n#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */\r\n#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */\r\n#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */\r\n#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */\r\n\r\n#define ADC_SQR2_SQ7_Pos                  (12U)\r\n#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */\r\n#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */\r\n#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */\r\n#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */\r\n#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */\r\n#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */\r\n#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */\r\n\r\n#define ADC_SQR2_SQ8_Pos                  (18U)\r\n#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */\r\n#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */\r\n#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */\r\n#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */\r\n#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */\r\n#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */\r\n#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */\r\n\r\n#define ADC_SQR2_SQ9_Pos                  (24U)\r\n#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */\r\n#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */\r\n#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */\r\n#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */\r\n#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */\r\n#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */\r\n#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */\r\n\r\n/********************  Bit definition for ADC_SQR3 register  ********************/\r\n#define ADC_SQR3_SQ10_Pos                 (0U)\r\n#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */\r\n#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */\r\n#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */\r\n#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */\r\n#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */\r\n#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */\r\n#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */\r\n\r\n#define ADC_SQR3_SQ11_Pos                 (6U)\r\n#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */\r\n#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */\r\n#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */\r\n#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */\r\n#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */\r\n#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */\r\n#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */\r\n\r\n#define ADC_SQR3_SQ12_Pos                 (12U)\r\n#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */\r\n#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */\r\n#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */\r\n#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */\r\n#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */\r\n#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */\r\n#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */\r\n\r\n#define ADC_SQR3_SQ13_Pos                 (18U)\r\n#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */\r\n#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */\r\n#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */\r\n#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */\r\n#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */\r\n#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */\r\n#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */\r\n\r\n#define ADC_SQR3_SQ14_Pos                 (24U)\r\n#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */\r\n#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */\r\n#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */\r\n#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */\r\n#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */\r\n#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */\r\n#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */\r\n\r\n/********************  Bit definition for ADC_SQR4 register  ********************/\r\n#define ADC_SQR4_SQ15_Pos                 (0U)\r\n#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */\r\n#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */\r\n#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */\r\n#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */\r\n#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */\r\n#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */\r\n#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */\r\n\r\n#define ADC_SQR4_SQ16_Pos                 (6U)\r\n#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */\r\n#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */\r\n#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */\r\n#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */\r\n#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */\r\n#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */\r\n#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */\r\n/********************  Bit definition for ADC_DR register  ********************/\r\n#define ADC_DR_RDATA_Pos                  (0U)\r\n#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */\r\n#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */\r\n\r\n/********************  Bit definition for ADC_JSQR register  ********************/\r\n#define ADC_JSQR_JL_Pos                   (0U)\r\n#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */\r\n#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */\r\n#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */\r\n#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */\r\n\r\n#define ADC_JSQR_JEXTSEL_Pos              (2U)\r\n#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */\r\n#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */\r\n#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */\r\n#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */\r\n#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */\r\n#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */\r\n#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */\r\n\r\n#define ADC_JSQR_JEXTEN_Pos               (7U)\r\n#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */\r\n#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */\r\n#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */\r\n#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */\r\n\r\n#define ADC_JSQR_JSQ1_Pos                 (9U)\r\n#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */\r\n#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */\r\n#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */\r\n#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */\r\n#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */\r\n#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */\r\n#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */\r\n\r\n#define ADC_JSQR_JSQ2_Pos                 (15U)\r\n#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */\r\n#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */\r\n#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */\r\n#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */\r\n#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */\r\n#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */\r\n#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */\r\n\r\n#define ADC_JSQR_JSQ3_Pos                 (21U)\r\n#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */\r\n#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */\r\n#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */\r\n#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */\r\n#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */\r\n#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */\r\n#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */\r\n\r\n#define ADC_JSQR_JSQ4_Pos                 (27U)\r\n#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */\r\n#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */\r\n#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */\r\n#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */\r\n#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */\r\n#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */\r\n#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_OFR1 register  ********************/\r\n#define ADC_OFR1_OFFSET1_Pos              (0U)\r\n#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */\r\n#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR1_OFFSET1_CH_Pos           (26U)\r\n#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */\r\n#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR1_SSATE_Pos                (31U)\r\n#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR1_OFFSET1_Pos              (0U)\r\n#define ADC3_OFR1_OFFSET1_Msk              (0xFFFUL << ADC3_OFR1_OFFSET1_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR1_OFFSET1                  ADC3_OFR1_OFFSET1_Msk                /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR1_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR1_OFFSETPOS_Msk         (0x1UL << ADC3_OFR1_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR1_OFFSETPOS             ADC3_OFR1_OFFSETPOS_Msk                 /*!< ADC offset number 1 positive */\r\n#define ADC3_OFR1_SATEN_Pos             (25U)\r\n#define ADC3_OFR1_SATEN_Msk             (0x1UL << ADC3_OFR1_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR1_SATEN                 ADC3_OFR1_SATEN_Msk                     /*!< ADC offset number 1 saturation enable */\r\n\r\n#define ADC3_OFR1_OFFSET1_EN_Pos        (31U)\r\n#define ADC3_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR1_OFFSET1_EN            ADC3_OFR1_OFFSET1_EN_Msk                /*!< ADC offset number 1 enable */\r\n\r\n/********************  Bit definition for ADC_OFR2 register  ********************/\r\n#define ADC_OFR2_OFFSET2_Pos              (0U)\r\n#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */\r\n#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR2_OFFSET2_CH_Pos           (26U)\r\n#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */\r\n#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR2_SSATE_Pos                (31U)\r\n#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR2_OFFSET2_Pos              (0U)\r\n#define ADC3_OFR2_OFFSET2_Msk              (0xFFFUL << ADC3_OFR2_OFFSET2_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR2_OFFSET2                  ADC3_OFR2_OFFSET2_Msk                /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR2_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR2_OFFSETPOS_Msk         (0x1UL << ADC3_OFR2_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR2_OFFSETPOS             ADC3_OFR2_OFFSETPOS_Msk                 /*!< ADC offset number 2 positive */\r\n#define ADC3_OFR2_SATEN_Pos             (25U)\r\n#define ADC3_OFR2_SATEN_Msk             (0x1UL << ADC3_OFR2_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR2_SATEN                 ADC3_OFR2_SATEN_Msk                     /*!< ADC offset number 2 saturation enable */\r\n\r\n#define ADC3_OFR2_OFFSET2_EN_Pos        (31U)\r\n#define ADC3_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR2_OFFSET2_EN            ADC3_OFR2_OFFSET2_EN_Msk                /*!< ADC offset number 2 enable */\r\n\r\n/********************  Bit definition for ADC_OFR3 register  ********************/\r\n#define ADC_OFR3_OFFSET3_Pos              (0U)\r\n#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */\r\n#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR3_OFFSET3_CH_Pos           (26U)\r\n#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */\r\n#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR3_SSATE_Pos                (31U)\r\n#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR3_OFFSET3_Pos              (0U)\r\n#define ADC3_OFR3_OFFSET3_Msk              (0xFFFUL << ADC3_OFR3_OFFSET3_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR3_OFFSET3                  ADC3_OFR3_OFFSET3_Msk                /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR3_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR3_OFFSETPOS_Msk         (0x1UL << ADC3_OFR3_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR3_OFFSETPOS             ADC3_OFR3_OFFSETPOS_Msk                 /*!< ADC offset number 3 positive */\r\n#define ADC3_OFR3_SATEN_Pos             (25U)\r\n#define ADC3_OFR3_SATEN_Msk             (0x1UL << ADC3_OFR3_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR3_SATEN                 ADC3_OFR3_SATEN_Msk                     /*!< ADC offset number 3 saturation enable */\r\n\r\n#define ADC3_OFR3_OFFSET3_EN_Pos        (31U)\r\n#define ADC3_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR3_OFFSET3_EN            ADC3_OFR3_OFFSET3_EN_Msk                /*!< ADC offset number 3 enable */\r\n\r\n/********************  Bit definition for ADC_OFR4 register  ********************/\r\n#define ADC_OFR4_OFFSET4_Pos              (0U)\r\n#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */\r\n#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR4_OFFSET4_CH_Pos           (26U)\r\n#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */\r\n#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR4_SSATE_Pos                (31U)\r\n#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR4_OFFSET4_Pos              (0U)\r\n#define ADC3_OFR4_OFFSET4_Msk              (0xFFFUL << ADC3_OFR4_OFFSET4_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR4_OFFSET4                  ADC3_OFR4_OFFSET4_Msk                /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR4_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR4_OFFSETPOS_Msk         (0x1UL << ADC3_OFR4_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR4_OFFSETPOS             ADC3_OFR4_OFFSETPOS_Msk                 /*!< ADC offset number 4 positive */\r\n#define ADC3_OFR4_SATEN_Pos             (25U)\r\n#define ADC3_OFR4_SATEN_Msk             (0x1UL << ADC3_OFR4_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR4_SATEN                 ADC3_OFR4_SATEN_Msk                     /*!< ADC offset number 4 saturation enable */\r\n\r\n#define ADC3_OFR4_OFFSET4_EN_Pos        (31U)\r\n#define ADC3_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR4_OFFSET4_EN            ADC3_OFR4_OFFSET4_EN_Msk                /*!< ADC offset number 4 enable */\r\n\r\n/********************  Bit definition for ADC_JDR1 register  ********************/\r\n#define ADC_JDR1_JDATA_Pos                (0U)\r\n#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_JDR2 register  ********************/\r\n#define ADC_JDR2_JDATA_Pos                (0U)\r\n#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_JDR3 register  ********************/\r\n#define ADC_JDR3_JDATA_Pos                (0U)\r\n#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_JDR4 register  ********************/\r\n#define ADC_JDR4_JDATA_Pos                (0U)\r\n#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_AWD2CR register  ********************/\r\n#define ADC_AWD2CR_AWD2CH_Pos             (0U)\r\n#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */\r\n#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */\r\n#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */\r\n#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */\r\n#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */\r\n#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */\r\n#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */\r\n#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */\r\n#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */\r\n#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */\r\n#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */\r\n#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */\r\n#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */\r\n#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */\r\n#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */\r\n#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */\r\n#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */\r\n#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */\r\n#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */\r\n#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */\r\n#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */\r\n#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */\r\n\r\n/********************  Bit definition for ADC_AWD3CR register  ********************/\r\n#define ADC_AWD3CR_AWD3CH_Pos             (0U)\r\n#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */\r\n#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */\r\n#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */\r\n#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */\r\n#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */\r\n#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */\r\n#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */\r\n#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */\r\n#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */\r\n#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */\r\n#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */\r\n#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */\r\n#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */\r\n#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */\r\n#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */\r\n#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */\r\n#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */\r\n#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */\r\n#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */\r\n#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */\r\n#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */\r\n#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */\r\n\r\n/********************  Bit definition for ADC_DIFSEL register  ********************/\r\n#define ADC_DIFSEL_DIFSEL_Pos             (0U)\r\n#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */\r\n#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */\r\n#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */\r\n#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */\r\n#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */\r\n#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */\r\n#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */\r\n#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */\r\n#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */\r\n#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */\r\n#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */\r\n#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */\r\n#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */\r\n#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */\r\n#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */\r\n#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */\r\n#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */\r\n#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */\r\n#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */\r\n#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */\r\n#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */\r\n#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */\r\n\r\n/********************  Bit definition for ADC_CALFACT register  ********************/\r\n#define ADC_CALFACT_CALFACT_S_Pos         (0U)\r\n#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */\r\n#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */\r\n#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\r\n#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\r\n#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\r\n#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\r\n#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\r\n#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\r\n#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */\r\n#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */\r\n#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */\r\n#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */\r\n#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */\r\n#define ADC_CALFACT_CALFACT_D_Pos         (16U)\r\n#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */\r\n#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */\r\n#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\r\n#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\r\n#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\r\n#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\r\n#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\r\n#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\r\n#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */\r\n#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */\r\n#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */\r\n#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */\r\n#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */\r\n\r\n/********************  Bit definition for ADC_CALFACT2 register  ********************/\r\n#define ADC_CALFACT2_LINCALFACT_Pos       (0U)\r\n#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */\r\n#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */\r\n#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */\r\n#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */\r\n#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */\r\n#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */\r\n#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */\r\n#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */\r\n#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */\r\n#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */\r\n#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */\r\n#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */\r\n#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */\r\n#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */\r\n#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */\r\n#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */\r\n#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */\r\n#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */\r\n#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */\r\n#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */\r\n#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */\r\n#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */\r\n#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */\r\n#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */\r\n#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */\r\n#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */\r\n#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */\r\n#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */\r\n#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */\r\n#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */\r\n#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */\r\n#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */\r\n\r\n/*************************  ADC Common registers  *****************************/\r\n/********************  Bit definition for ADC_CSR register  ********************/\r\n#define ADC_CSR_ADRDY_MST_Pos             (0U)\r\n#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */\r\n#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */\r\n#define ADC_CSR_EOSMP_MST_Pos             (1U)\r\n#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */\r\n#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */\r\n#define ADC_CSR_EOC_MST_Pos               (2U)\r\n#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */\r\n#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */\r\n#define ADC_CSR_EOS_MST_Pos               (3U)\r\n#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */\r\n#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */\r\n#define ADC_CSR_OVR_MST_Pos               (4U)\r\n#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */\r\n#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */\r\n#define ADC_CSR_JEOC_MST_Pos              (5U)\r\n#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */\r\n#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */\r\n#define ADC_CSR_JEOS_MST_Pos              (6U)\r\n#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */\r\n#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */\r\n#define ADC_CSR_AWD1_MST_Pos              (7U)\r\n#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */\r\n#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */\r\n#define ADC_CSR_AWD2_MST_Pos              (8U)\r\n#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */\r\n#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */\r\n#define ADC_CSR_AWD3_MST_Pos              (9U)\r\n#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */\r\n#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */\r\n#define ADC_CSR_JQOVF_MST_Pos             (10U)\r\n#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */\r\n#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */\r\n#define ADC_CSR_ADRDY_SLV_Pos             (16U)\r\n#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */\r\n#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */\r\n#define ADC_CSR_EOSMP_SLV_Pos             (17U)\r\n#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */\r\n#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */\r\n#define ADC_CSR_EOC_SLV_Pos               (18U)\r\n#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */\r\n#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */\r\n#define ADC_CSR_EOS_SLV_Pos               (19U)\r\n#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */\r\n#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */\r\n#define ADC_CSR_OVR_SLV_Pos               (20U)\r\n#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */\r\n#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */\r\n#define ADC_CSR_JEOC_SLV_Pos              (21U)\r\n#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */\r\n#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */\r\n#define ADC_CSR_JEOS_SLV_Pos              (22U)\r\n#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */\r\n#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */\r\n#define ADC_CSR_AWD1_SLV_Pos              (23U)\r\n#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */\r\n#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */\r\n#define ADC_CSR_AWD2_SLV_Pos              (24U)\r\n#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */\r\n#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */\r\n#define ADC_CSR_AWD3_SLV_Pos              (25U)\r\n#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */\r\n#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */\r\n#define ADC_CSR_JQOVF_SLV_Pos             (26U)\r\n#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */\r\n#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */\r\n\r\n/********************  Bit definition for ADC_CCR register  ********************/\r\n#define ADC_CCR_DUAL_Pos                  (0U)\r\n#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */\r\n#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */\r\n#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */\r\n#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */\r\n#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */\r\n#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */\r\n#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */\r\n\r\n#define ADC_CCR_DELAY_Pos                 (8U)\r\n#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */\r\n#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */\r\n#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */\r\n#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */\r\n#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */\r\n#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */\r\n\r\n\r\n#define ADC_CCR_DAMDF_Pos                 (14U)\r\n#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */\r\n#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */\r\n#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */\r\n#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */\r\n\r\n#define ADC_CCR_CKMODE_Pos                (16U)\r\n#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */\r\n#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */\r\n#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */\r\n#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */\r\n\r\n#define ADC_CCR_PRESC_Pos                 (18U)\r\n#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */\r\n#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */\r\n#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */\r\n#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */\r\n#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */\r\n#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */\r\n\r\n#define ADC_CCR_VREFEN_Pos                (22U)\r\n#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */\r\n#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */\r\n#define ADC_CCR_TSEN_Pos                  (23U)\r\n#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */\r\n#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */\r\n#define ADC_CCR_VBATEN_Pos                (24U)\r\n#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */\r\n#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */\r\n\r\n/********************  Bit definition for ADC_CDR register  *******************/\r\n#define ADC_CDR_RDATA_MST_Pos             (0U)\r\n#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */\r\n#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */\r\n\r\n#define ADC_CDR_RDATA_SLV_Pos             (16U)\r\n#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */\r\n#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */\r\n\r\n/********************  Bit definition for ADC_CDR2 register  ******************/\r\n#define ADC_CDR2_RDATA_ALT_Pos            (0U)\r\n#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */\r\n#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                   VREFBUF                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for VREFBUF_CSR register  ****************/\r\n#define VREFBUF_CSR_ENVR_Pos        (0U)\r\n#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */\r\n#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */\r\n#define VREFBUF_CSR_HIZ_Pos         (1U)\r\n#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */\r\n#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */\r\n#define VREFBUF_CSR_VRR_Pos         (3U)\r\n#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */\r\n#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */\r\n#define VREFBUF_CSR_VRS_Pos         (4U)\r\n#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */\r\n#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */\r\n\r\n#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */\r\n#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)\r\n#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */\r\n#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */\r\n#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)\r\n#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */\r\n#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */\r\n#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)\r\n#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */\r\n#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */\r\n\r\n/*******************  Bit definition for VREFBUF_CCR register  ****************/\r\n#define VREFBUF_CCR_TRIM_Pos        (0U)\r\n#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */\r\n#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                 Flexible Datarate Controller Area Network                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*!<FDCAN control and status registers */\r\n/*****************  Bit definition for FDCAN_CREL register  *******************/\r\n#define FDCAN_CREL_DAY_Pos        (0U)\r\n#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */\r\n#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */\r\n#define FDCAN_CREL_MON_Pos        (8U)\r\n#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */\r\n#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */\r\n#define FDCAN_CREL_YEAR_Pos       (16U)\r\n#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */\r\n#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */\r\n#define FDCAN_CREL_SUBSTEP_Pos    (20U)\r\n#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */\r\n#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */\r\n#define FDCAN_CREL_STEP_Pos       (24U)\r\n#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */\r\n#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */\r\n#define FDCAN_CREL_REL_Pos        (28U)\r\n#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */\r\n#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */\r\n\r\n/*****************  Bit definition for FDCAN_ENDN register  *******************/\r\n#define FDCAN_ENDN_ETV_Pos        (0U)\r\n#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */\r\n\r\n/*****************  Bit definition for FDCAN_DBTP register  *******************/\r\n#define FDCAN_DBTP_DSJW_Pos       (0U)\r\n#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */\r\n#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */\r\n#define FDCAN_DBTP_DTSEG2_Pos     (4U)\r\n#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */\r\n#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */\r\n#define FDCAN_DBTP_DTSEG1_Pos     (8U)\r\n#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */\r\n#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */\r\n#define FDCAN_DBTP_DBRP_Pos       (16U)\r\n#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */\r\n#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */\r\n#define FDCAN_DBTP_TDC_Pos        (23U)\r\n#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */\r\n#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */\r\n\r\n/*****************  Bit definition for FDCAN_TEST register  *******************/\r\n#define FDCAN_TEST_LBCK_Pos       (4U)\r\n#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */\r\n#define FDCAN_TEST_TX_Pos         (5U)\r\n#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */\r\n#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */\r\n#define FDCAN_TEST_RX_Pos         (7U)\r\n#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */\r\n#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */\r\n\r\n/*****************  Bit definition for FDCAN_RWD register  ********************/\r\n#define FDCAN_RWD_WDC_Pos         (0U)\r\n#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */\r\n#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */\r\n#define FDCAN_RWD_WDV_Pos         (8U)\r\n#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */\r\n#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */\r\n\r\n/*****************  Bit definition for FDCAN_CCCR register  ********************/\r\n#define FDCAN_CCCR_INIT_Pos       (0U)\r\n#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */\r\n#define FDCAN_CCCR_CCE_Pos        (1U)\r\n#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */\r\n#define FDCAN_CCCR_ASM_Pos        (2U)\r\n#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */\r\n#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */\r\n#define FDCAN_CCCR_CSA_Pos        (3U)\r\n#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */\r\n#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */\r\n#define FDCAN_CCCR_CSR_Pos        (4U)\r\n#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */\r\n#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */\r\n#define FDCAN_CCCR_MON_Pos        (5U)\r\n#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */\r\n#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */\r\n#define FDCAN_CCCR_DAR_Pos        (6U)\r\n#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */\r\n#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */\r\n#define FDCAN_CCCR_TEST_Pos       (7U)\r\n#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */\r\n#define FDCAN_CCCR_FDOE_Pos       (8U)\r\n#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */\r\n#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */\r\n#define FDCAN_CCCR_BRSE_Pos       (9U)\r\n#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */\r\n#define FDCAN_CCCR_PXHD_Pos       (12U)\r\n#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */\r\n#define FDCAN_CCCR_EFBI_Pos       (13U)\r\n#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */\r\n#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */\r\n#define FDCAN_CCCR_TXP_Pos        (14U)\r\n#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */\r\n#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */\r\n#define FDCAN_CCCR_NISO_Pos       (15U)\r\n#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */\r\n\r\n/*****************  Bit definition for FDCAN_NBTP register  ********************/\r\n#define FDCAN_NBTP_NTSEG2_Pos     (0U)\r\n#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */\r\n#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */\r\n#define FDCAN_NBTP_NTSEG1_Pos     (8U)\r\n#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */\r\n#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */\r\n#define FDCAN_NBTP_NBRP_Pos       (16U)\r\n#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */\r\n#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */\r\n#define FDCAN_NBTP_NSJW_Pos       (25U)\r\n#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */\r\n#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */\r\n\r\n/*****************  Bit definition for FDCAN_TSCC register  ********************/\r\n#define FDCAN_TSCC_TSS_Pos        (0U)\r\n#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */\r\n#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */\r\n#define FDCAN_TSCC_TCP_Pos        (16U)\r\n#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */\r\n#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */\r\n\r\n/*****************  Bit definition for FDCAN_TSCV register  ********************/\r\n#define FDCAN_TSCV_TSC_Pos        (0U)\r\n#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */\r\n\r\n/*****************  Bit definition for FDCAN_TOCC register  ********************/\r\n#define FDCAN_TOCC_ETOC_Pos       (0U)\r\n#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */\r\n#define FDCAN_TOCC_TOS_Pos        (1U)\r\n#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */\r\n#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */\r\n#define FDCAN_TOCC_TOP_Pos        (16U)\r\n#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */\r\n#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */\r\n\r\n/*****************  Bit definition for FDCAN_TOCV register  ********************/\r\n#define FDCAN_TOCV_TOC_Pos        (0U)\r\n#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */\r\n\r\n/*****************  Bit definition for FDCAN_ECR register  *********************/\r\n#define FDCAN_ECR_TEC_Pos         (0U)\r\n#define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x000000FF */\r\n#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */\r\n#define FDCAN_ECR_REC_Pos         (8U)\r\n#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */\r\n#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */\r\n#define FDCAN_ECR_RP_Pos          (15U)\r\n#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */\r\n#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */\r\n#define FDCAN_ECR_CEL_Pos         (16U)\r\n#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */\r\n#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */\r\n\r\n/*****************  Bit definition for FDCAN_PSR register  *********************/\r\n#define FDCAN_PSR_LEC_Pos         (0U)\r\n#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */\r\n#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */\r\n#define FDCAN_PSR_ACT_Pos         (3U)\r\n#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */\r\n#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */\r\n#define FDCAN_PSR_EP_Pos          (5U)\r\n#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */\r\n#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */\r\n#define FDCAN_PSR_EW_Pos          (6U)\r\n#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */\r\n#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */\r\n#define FDCAN_PSR_BO_Pos          (7U)\r\n#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */\r\n#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */\r\n#define FDCAN_PSR_DLEC_Pos        (8U)\r\n#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */\r\n#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */\r\n#define FDCAN_PSR_RESI_Pos        (11U)\r\n#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */\r\n#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */\r\n#define FDCAN_PSR_RBRS_Pos        (12U)\r\n#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */\r\n#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */\r\n#define FDCAN_PSR_REDL_Pos        (13U)\r\n#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */\r\n#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */\r\n#define FDCAN_PSR_PXE_Pos         (14U)\r\n#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */\r\n#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */\r\n#define FDCAN_PSR_TDCV_Pos        (16U)\r\n#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */\r\n#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */\r\n\r\n/*****************  Bit definition for FDCAN_TDCR register  ********************/\r\n#define FDCAN_TDCR_TDCF_Pos       (0U)\r\n#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */\r\n#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */\r\n#define FDCAN_TDCR_TDCO_Pos       (8U)\r\n#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */\r\n#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */\r\n\r\n/*****************  Bit definition for FDCAN_IR register  **********************/\r\n#define FDCAN_IR_RF0N_Pos         (0U)\r\n#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */\r\n#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */\r\n#define FDCAN_IR_RF0W_Pos         (1U)\r\n#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */\r\n#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */\r\n#define FDCAN_IR_RF0F_Pos         (2U)\r\n#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */\r\n#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */\r\n#define FDCAN_IR_RF0L_Pos         (3U)\r\n#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */\r\n#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */\r\n#define FDCAN_IR_RF1N_Pos         (4U)\r\n#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */\r\n#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */\r\n#define FDCAN_IR_RF1W_Pos         (5U)\r\n#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */\r\n#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */\r\n#define FDCAN_IR_RF1F_Pos         (6U)\r\n#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */\r\n#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */\r\n#define FDCAN_IR_RF1L_Pos         (7U)\r\n#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */\r\n#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */\r\n#define FDCAN_IR_HPM_Pos          (8U)\r\n#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */\r\n#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */\r\n#define FDCAN_IR_TC_Pos           (9U)\r\n#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */\r\n#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */\r\n#define FDCAN_IR_TCF_Pos          (10U)\r\n#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */\r\n#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */\r\n#define FDCAN_IR_TFE_Pos          (11U)\r\n#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */\r\n#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */\r\n#define FDCAN_IR_TEFN_Pos         (12U)\r\n#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */\r\n#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */\r\n#define FDCAN_IR_TEFW_Pos         (13U)\r\n#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */\r\n#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */\r\n#define FDCAN_IR_TEFF_Pos         (14U)\r\n#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */\r\n#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */\r\n#define FDCAN_IR_TEFL_Pos         (15U)\r\n#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */\r\n#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */\r\n#define FDCAN_IR_TSW_Pos          (16U)\r\n#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */\r\n#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */\r\n#define FDCAN_IR_MRAF_Pos         (17U)\r\n#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */\r\n#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */\r\n#define FDCAN_IR_TOO_Pos          (18U)\r\n#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */\r\n#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */\r\n#define FDCAN_IR_DRX_Pos          (19U)\r\n#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */\r\n#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */\r\n#define FDCAN_IR_ELO_Pos          (22U)\r\n#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */\r\n#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */\r\n#define FDCAN_IR_EP_Pos           (23U)\r\n#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */\r\n#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */\r\n#define FDCAN_IR_EW_Pos           (24U)\r\n#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */\r\n#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */\r\n#define FDCAN_IR_BO_Pos           (25U)\r\n#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */\r\n#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */\r\n#define FDCAN_IR_WDI_Pos          (26U)\r\n#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */\r\n#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */\r\n#define FDCAN_IR_PEA_Pos          (27U)\r\n#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */\r\n#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */\r\n#define FDCAN_IR_PED_Pos          (28U)\r\n#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */\r\n#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */\r\n#define FDCAN_IR_ARA_Pos          (29U)\r\n#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */\r\n#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */\r\n\r\n/*****************  Bit definition for FDCAN_IE register  **********************/\r\n#define FDCAN_IE_RF0NE_Pos        (0U)\r\n#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */\r\n#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */\r\n#define FDCAN_IE_RF0WE_Pos        (1U)\r\n#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */\r\n#define FDCAN_IE_RF0FE_Pos        (2U)\r\n#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */\r\n#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */\r\n#define FDCAN_IE_RF0LE_Pos        (3U)\r\n#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */\r\n#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */\r\n#define FDCAN_IE_RF1NE_Pos        (4U)\r\n#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */\r\n#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */\r\n#define FDCAN_IE_RF1WE_Pos        (5U)\r\n#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */\r\n#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */\r\n#define FDCAN_IE_RF1FE_Pos        (6U)\r\n#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */\r\n#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */\r\n#define FDCAN_IE_RF1LE_Pos        (7U)\r\n#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */\r\n#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */\r\n#define FDCAN_IE_HPME_Pos         (8U)\r\n#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */\r\n#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */\r\n#define FDCAN_IE_TCE_Pos          (9U)\r\n#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */\r\n#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */\r\n#define FDCAN_IE_TCFE_Pos         (10U)\r\n#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */\r\n#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */\r\n#define FDCAN_IE_TFEE_Pos         (11U)\r\n#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */\r\n#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */\r\n#define FDCAN_IE_TEFNE_Pos        (12U)\r\n#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */\r\n#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */\r\n#define FDCAN_IE_TEFWE_Pos        (13U)\r\n#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */\r\n#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */\r\n#define FDCAN_IE_TEFFE_Pos        (14U)\r\n#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */\r\n#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */\r\n#define FDCAN_IE_TEFLE_Pos        (15U)\r\n#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */\r\n#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */\r\n#define FDCAN_IE_TSWE_Pos         (16U)\r\n#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */\r\n#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */\r\n#define FDCAN_IE_MRAFE_Pos        (17U)\r\n#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */\r\n#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */\r\n#define FDCAN_IE_TOOE_Pos         (18U)\r\n#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */\r\n#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */\r\n#define FDCAN_IE_DRXE_Pos         (19U)\r\n#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */\r\n#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */\r\n#define FDCAN_IE_BECE_Pos         (20U)\r\n#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */\r\n#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */\r\n#define FDCAN_IE_BEUE_Pos         (21U)\r\n#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */\r\n#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */\r\n#define FDCAN_IE_ELOE_Pos         (22U)\r\n#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */\r\n#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */\r\n#define FDCAN_IE_EPE_Pos          (23U)\r\n#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */\r\n#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */\r\n#define FDCAN_IE_EWE_Pos          (24U)\r\n#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */\r\n#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */\r\n#define FDCAN_IE_BOE_Pos          (25U)\r\n#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */\r\n#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */\r\n#define FDCAN_IE_WDIE_Pos         (26U)\r\n#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */\r\n#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */\r\n#define FDCAN_IE_PEAE_Pos         (27U)\r\n#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */\r\n#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */\r\n#define FDCAN_IE_PEDE_Pos         (28U)\r\n#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */\r\n#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */\r\n#define FDCAN_IE_ARAE_Pos         (29U)\r\n#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */\r\n#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */\r\n\r\n/*****************  Bit definition for FDCAN_ILS register  **********************/\r\n#define FDCAN_ILS_RF0NL_Pos       (0U)\r\n#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */\r\n#define FDCAN_ILS_RF0WL_Pos       (1U)\r\n#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */\r\n#define FDCAN_ILS_RF0FL_Pos       (2U)\r\n#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */\r\n#define FDCAN_ILS_RF0LL_Pos       (3U)\r\n#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */\r\n#define FDCAN_ILS_RF1NL_Pos       (4U)\r\n#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */\r\n#define FDCAN_ILS_RF1WL_Pos       (5U)\r\n#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */\r\n#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */\r\n#define FDCAN_ILS_RF1FL_Pos       (6U)\r\n#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */\r\n#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */\r\n#define FDCAN_ILS_RF1LL_Pos       (7U)\r\n#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */\r\n#define FDCAN_ILS_HPML_Pos        (8U)\r\n#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */\r\n#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */\r\n#define FDCAN_ILS_TCL_Pos         (9U)\r\n#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */\r\n#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */\r\n#define FDCAN_ILS_TCFL_Pos        (10U)\r\n#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */\r\n#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */\r\n#define FDCAN_ILS_TFEL_Pos        (11U)\r\n#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */\r\n#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */\r\n#define FDCAN_ILS_TEFNL_Pos       (12U)\r\n#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */\r\n#define FDCAN_ILS_TEFWL_Pos       (13U)\r\n#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */\r\n#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */\r\n#define FDCAN_ILS_TEFFL_Pos       (14U)\r\n#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */\r\n#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */\r\n#define FDCAN_ILS_TEFLL_Pos       (15U)\r\n#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */\r\n#define FDCAN_ILS_TSWL_Pos        (16U)\r\n#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */\r\n#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */\r\n#define FDCAN_ILS_MRAFE_Pos       (17U)\r\n#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */\r\n#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */\r\n#define FDCAN_ILS_TOOE_Pos        (18U)\r\n#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */\r\n#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */\r\n#define FDCAN_ILS_DRXE_Pos        (19U)\r\n#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */\r\n#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */\r\n#define FDCAN_ILS_BECE_Pos        (20U)\r\n#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */\r\n#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */\r\n#define FDCAN_ILS_BEUE_Pos        (21U)\r\n#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */\r\n#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */\r\n#define FDCAN_ILS_ELOE_Pos        (22U)\r\n#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */\r\n#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */\r\n#define FDCAN_ILS_EPE_Pos         (23U)\r\n#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */\r\n#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */\r\n#define FDCAN_ILS_EWE_Pos         (24U)\r\n#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */\r\n#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */\r\n#define FDCAN_ILS_BOE_Pos         (25U)\r\n#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */\r\n#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */\r\n#define FDCAN_ILS_WDIE_Pos        (26U)\r\n#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */\r\n#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */\r\n#define FDCAN_ILS_PEAE_Pos        (27U)\r\n#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */\r\n#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */\r\n#define FDCAN_ILS_PEDE_Pos        (28U)\r\n#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */\r\n#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */\r\n#define FDCAN_ILS_ARAE_Pos        (29U)\r\n#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */\r\n#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */\r\n\r\n/*****************  Bit definition for FDCAN_ILE register  **********************/\r\n#define FDCAN_ILE_EINT0_Pos       (0U)\r\n#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */\r\n#define FDCAN_ILE_EINT1_Pos       (1U)\r\n#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */\r\n\r\n/*****************  Bit definition for FDCAN_GFC register  **********************/\r\n#define FDCAN_GFC_RRFE_Pos        (0U)\r\n#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */\r\n#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */\r\n#define FDCAN_GFC_RRFS_Pos        (1U)\r\n#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */\r\n#define FDCAN_GFC_ANFE_Pos        (2U)\r\n#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */\r\n#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */\r\n#define FDCAN_GFC_ANFS_Pos        (4U)\r\n#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */\r\n#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */\r\n\r\n/*****************  Bit definition for FDCAN_SIDFC register  ********************/\r\n#define FDCAN_SIDFC_FLSSA_Pos     (2U)\r\n#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */\r\n#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */\r\n#define FDCAN_SIDFC_LSS_Pos       (16U)\r\n#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */\r\n#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */\r\n\r\n/*****************  Bit definition for FDCAN_XIDFC register  ********************/\r\n#define FDCAN_XIDFC_FLESA_Pos     (2U)\r\n#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */\r\n#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */\r\n#define FDCAN_XIDFC_LSE_Pos       (16U)\r\n#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */\r\n\r\n/*****************  Bit definition for FDCAN_XIDAM register  ********************/\r\n#define FDCAN_XIDAM_EIDM_Pos      (0U)\r\n#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */\r\n#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */\r\n\r\n/*****************  Bit definition for FDCAN_HPMS register  *********************/\r\n#define FDCAN_HPMS_BIDX_Pos       (0U)\r\n#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */\r\n#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */\r\n#define FDCAN_HPMS_MSI_Pos        (6U)\r\n#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */\r\n#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */\r\n#define FDCAN_HPMS_FIDX_Pos       (8U)\r\n#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */\r\n#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */\r\n#define FDCAN_HPMS_FLST_Pos       (15U)\r\n#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */\r\n\r\n/*****************  Bit definition for FDCAN_NDAT1 register  ********************/\r\n#define FDCAN_NDAT1_ND0_Pos       (0U)\r\n#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */\r\n#define FDCAN_NDAT1_ND1_Pos       (1U)\r\n#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */\r\n#define FDCAN_NDAT1_ND2_Pos       (2U)\r\n#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */\r\n#define FDCAN_NDAT1_ND3_Pos       (3U)\r\n#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */\r\n#define FDCAN_NDAT1_ND4_Pos       (4U)\r\n#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */\r\n#define FDCAN_NDAT1_ND5_Pos       (5U)\r\n#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */\r\n#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */\r\n#define FDCAN_NDAT1_ND6_Pos       (6U)\r\n#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */\r\n#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */\r\n#define FDCAN_NDAT1_ND7_Pos       (7U)\r\n#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */\r\n#define FDCAN_NDAT1_ND8_Pos       (8U)\r\n#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */\r\n#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */\r\n#define FDCAN_NDAT1_ND9_Pos       (9U)\r\n#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */\r\n#define FDCAN_NDAT1_ND10_Pos      (10U)\r\n#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */\r\n#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */\r\n#define FDCAN_NDAT1_ND11_Pos      (11U)\r\n#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */\r\n#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */\r\n#define FDCAN_NDAT1_ND12_Pos      (12U)\r\n#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */\r\n#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */\r\n#define FDCAN_NDAT1_ND13_Pos      (13U)\r\n#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */\r\n#define FDCAN_NDAT1_ND14_Pos      (14U)\r\n#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */\r\n#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */\r\n#define FDCAN_NDAT1_ND15_Pos      (15U)\r\n#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */\r\n#define FDCAN_NDAT1_ND16_Pos      (16U)\r\n#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */\r\n#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */\r\n#define FDCAN_NDAT1_ND17_Pos      (17U)\r\n#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */\r\n#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */\r\n#define FDCAN_NDAT1_ND18_Pos      (18U)\r\n#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */\r\n#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */\r\n#define FDCAN_NDAT1_ND19_Pos      (19U)\r\n#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */\r\n#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */\r\n#define FDCAN_NDAT1_ND20_Pos      (20U)\r\n#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */\r\n#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */\r\n#define FDCAN_NDAT1_ND21_Pos      (21U)\r\n#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */\r\n#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */\r\n#define FDCAN_NDAT1_ND22_Pos      (22U)\r\n#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */\r\n#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */\r\n#define FDCAN_NDAT1_ND23_Pos      (23U)\r\n#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */\r\n#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */\r\n#define FDCAN_NDAT1_ND24_Pos      (24U)\r\n#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */\r\n#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */\r\n#define FDCAN_NDAT1_ND25_Pos      (25U)\r\n#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */\r\n#define FDCAN_NDAT1_ND26_Pos      (26U)\r\n#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */\r\n#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */\r\n#define FDCAN_NDAT1_ND27_Pos      (27U)\r\n#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */\r\n#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */\r\n#define FDCAN_NDAT1_ND28_Pos      (28U)\r\n#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */\r\n#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */\r\n#define FDCAN_NDAT1_ND29_Pos      (29U)\r\n#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */\r\n#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */\r\n#define FDCAN_NDAT1_ND30_Pos      (30U)\r\n#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */\r\n#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */\r\n#define FDCAN_NDAT1_ND31_Pos      (31U)\r\n#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */\r\n\r\n/*****************  Bit definition for FDCAN_NDAT2 register  ********************/\r\n#define FDCAN_NDAT2_ND32_Pos      (0U)\r\n#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */\r\n#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */\r\n#define FDCAN_NDAT2_ND33_Pos      (1U)\r\n#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */\r\n#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */\r\n#define FDCAN_NDAT2_ND34_Pos      (2U)\r\n#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */\r\n#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */\r\n#define FDCAN_NDAT2_ND35_Pos      (3U)\r\n#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */\r\n#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */\r\n#define FDCAN_NDAT2_ND36_Pos      (4U)\r\n#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */\r\n#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */\r\n#define FDCAN_NDAT2_ND37_Pos      (5U)\r\n#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */\r\n#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */\r\n#define FDCAN_NDAT2_ND38_Pos      (6U)\r\n#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */\r\n#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */\r\n#define FDCAN_NDAT2_ND39_Pos      (7U)\r\n#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */\r\n#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */\r\n#define FDCAN_NDAT2_ND40_Pos      (8U)\r\n#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */\r\n#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */\r\n#define FDCAN_NDAT2_ND41_Pos      (9U)\r\n#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */\r\n#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */\r\n#define FDCAN_NDAT2_ND42_Pos      (10U)\r\n#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */\r\n#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */\r\n#define FDCAN_NDAT2_ND43_Pos      (11U)\r\n#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */\r\n#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */\r\n#define FDCAN_NDAT2_ND44_Pos      (12U)\r\n#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */\r\n#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */\r\n#define FDCAN_NDAT2_ND45_Pos      (13U)\r\n#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */\r\n#define FDCAN_NDAT2_ND46_Pos      (14U)\r\n#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */\r\n#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */\r\n#define FDCAN_NDAT2_ND47_Pos      (15U)\r\n#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */\r\n#define FDCAN_NDAT2_ND48_Pos      (16U)\r\n#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */\r\n#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */\r\n#define FDCAN_NDAT2_ND49_Pos      (17U)\r\n#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */\r\n#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */\r\n#define FDCAN_NDAT2_ND50_Pos      (18U)\r\n#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */\r\n#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */\r\n#define FDCAN_NDAT2_ND51_Pos      (19U)\r\n#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */\r\n#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */\r\n#define FDCAN_NDAT2_ND52_Pos      (20U)\r\n#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */\r\n#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */\r\n#define FDCAN_NDAT2_ND53_Pos      (21U)\r\n#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */\r\n#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */\r\n#define FDCAN_NDAT2_ND54_Pos      (22U)\r\n#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */\r\n#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */\r\n#define FDCAN_NDAT2_ND55_Pos      (23U)\r\n#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */\r\n#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */\r\n#define FDCAN_NDAT2_ND56_Pos      (24U)\r\n#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */\r\n#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */\r\n#define FDCAN_NDAT2_ND57_Pos      (25U)\r\n#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */\r\n#define FDCAN_NDAT2_ND58_Pos      (26U)\r\n#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */\r\n#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */\r\n#define FDCAN_NDAT2_ND59_Pos      (27U)\r\n#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */\r\n#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */\r\n#define FDCAN_NDAT2_ND60_Pos      (28U)\r\n#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */\r\n#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */\r\n#define FDCAN_NDAT2_ND61_Pos      (29U)\r\n#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */\r\n#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */\r\n#define FDCAN_NDAT2_ND62_Pos      (30U)\r\n#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */\r\n#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */\r\n#define FDCAN_NDAT2_ND63_Pos      (31U)\r\n#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */\r\n\r\n/*****************  Bit definition for FDCAN_RXF0C register  ********************/\r\n#define FDCAN_RXF0C_F0SA_Pos      (2U)\r\n#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */\r\n#define FDCAN_RXF0C_F0S_Pos       (16U)\r\n#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */\r\n#define FDCAN_RXF0C_F0WM_Pos      (24U)\r\n#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */\r\n#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */\r\n#define FDCAN_RXF0C_F0OM_Pos      (31U)\r\n#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */\r\n\r\n/*****************  Bit definition for FDCAN_RXF0S register  ********************/\r\n#define FDCAN_RXF0S_F0FL_Pos      (0U)\r\n#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */\r\n#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */\r\n#define FDCAN_RXF0S_F0GI_Pos      (8U)\r\n#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */\r\n#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */\r\n#define FDCAN_RXF0S_F0PI_Pos      (16U)\r\n#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */\r\n#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */\r\n#define FDCAN_RXF0S_F0F_Pos       (24U)\r\n#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */\r\n#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */\r\n#define FDCAN_RXF0S_RF0L_Pos      (25U)\r\n#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */\r\n\r\n/*****************  Bit definition for FDCAN_RXF0A register  ********************/\r\n#define FDCAN_RXF0A_F0AI_Pos      (0U)\r\n#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */\r\n\r\n/*****************  Bit definition for FDCAN_RXBC register  ********************/\r\n#define FDCAN_RXBC_RBSA_Pos       (2U)\r\n#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */\r\n#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */\r\n\r\n/*****************  Bit definition for FDCAN_RXF1C register  ********************/\r\n#define FDCAN_RXF1C_F1SA_Pos      (2U)\r\n#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */\r\n#define FDCAN_RXF1C_F1S_Pos       (16U)\r\n#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */\r\n#define FDCAN_RXF1C_F1WM_Pos      (24U)\r\n#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */\r\n#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */\r\n#define FDCAN_RXF1C_F1OM_Pos      (31U)\r\n#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */\r\n\r\n/*****************  Bit definition for FDCAN_RXF1S register  ********************/\r\n#define FDCAN_RXF1S_F1FL_Pos      (0U)\r\n#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */\r\n#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */\r\n#define FDCAN_RXF1S_F1GI_Pos      (8U)\r\n#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */\r\n#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */\r\n#define FDCAN_RXF1S_F1PI_Pos      (16U)\r\n#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */\r\n#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */\r\n#define FDCAN_RXF1S_F1F_Pos       (24U)\r\n#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */\r\n#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */\r\n#define FDCAN_RXF1S_RF1L_Pos      (25U)\r\n#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */\r\n\r\n/*****************  Bit definition for FDCAN_RXF1A register  ********************/\r\n#define FDCAN_RXF1A_F1AI_Pos      (0U)\r\n#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */\r\n\r\n/*****************  Bit definition for FDCAN_RXESC register  ********************/\r\n#define FDCAN_RXESC_F0DS_Pos      (0U)\r\n#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */\r\n#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */\r\n#define FDCAN_RXESC_F1DS_Pos      (4U)\r\n#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */\r\n#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */\r\n#define FDCAN_RXESC_RBDS_Pos      (8U)\r\n#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */\r\n#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */\r\n\r\n/*****************  Bit definition for FDCAN_TXBC register  *********************/\r\n#define FDCAN_TXBC_TBSA_Pos       (2U)\r\n#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */\r\n#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */\r\n#define FDCAN_TXBC_NDTB_Pos       (16U)\r\n#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */\r\n#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */\r\n#define FDCAN_TXBC_TFQS_Pos       (24U)\r\n#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */\r\n#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */\r\n#define FDCAN_TXBC_TFQM_Pos       (30U)\r\n#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */\r\n#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */\r\n\r\n/*****************  Bit definition for FDCAN_TXFQS register  *********************/\r\n#define FDCAN_TXFQS_TFFL_Pos      (0U)\r\n#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */\r\n#define FDCAN_TXFQS_TFGI_Pos      (8U)\r\n#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */\r\n#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */\r\n#define FDCAN_TXFQS_TFQPI_Pos     (16U)\r\n#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */\r\n#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */\r\n#define FDCAN_TXFQS_TFQF_Pos      (21U)\r\n#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */\r\n#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */\r\n\r\n/*****************  Bit definition for FDCAN_TXESC register  *********************/\r\n#define FDCAN_TXESC_TBDS_Pos      (0U)\r\n#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */\r\n#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */\r\n\r\n/*****************  Bit definition for FDCAN_TXBRP register  *********************/\r\n#define FDCAN_TXBRP_TRP_Pos       (0U)\r\n#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */\r\n\r\n/*****************  Bit definition for FDCAN_TXBAR register  *********************/\r\n#define FDCAN_TXBAR_AR_Pos        (0U)\r\n#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */\r\n\r\n/*****************  Bit definition for FDCAN_TXBCR register  *********************/\r\n#define FDCAN_TXBCR_CR_Pos        (0U)\r\n#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */\r\n\r\n/*****************  Bit definition for FDCAN_TXBTO register  *********************/\r\n#define FDCAN_TXBTO_TO_Pos        (0U)\r\n#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */\r\n\r\n/*****************  Bit definition for FDCAN_TXBCF register  *********************/\r\n#define FDCAN_TXBCF_CF_Pos        (0U)\r\n#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */\r\n\r\n/*****************  Bit definition for FDCAN_TXBTIE register  ********************/\r\n#define FDCAN_TXBTIE_TIE_Pos      (0U)\r\n#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */\r\n\r\n/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/\r\n#define FDCAN_TXBCIE_CFIE_Pos     (0U)\r\n#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */\r\n\r\n/*****************  Bit definition for FDCAN_TXEFC register  *********************/\r\n#define FDCAN_TXEFC_EFSA_Pos      (2U)\r\n#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */\r\n#define FDCAN_TXEFC_EFS_Pos       (16U)\r\n#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */\r\n#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */\r\n#define FDCAN_TXEFC_EFWM_Pos      (24U)\r\n#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */\r\n#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */\r\n\r\n/*****************  Bit definition for FDCAN_TXEFS register  *********************/\r\n#define FDCAN_TXEFS_EFFL_Pos      (0U)\r\n#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */\r\n#define FDCAN_TXEFS_EFGI_Pos      (8U)\r\n#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */\r\n#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */\r\n#define FDCAN_TXEFS_EFPI_Pos      (16U)\r\n#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */\r\n#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */\r\n#define FDCAN_TXEFS_EFF_Pos       (24U)\r\n#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */\r\n#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */\r\n#define FDCAN_TXEFS_TEFL_Pos      (25U)\r\n#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */\r\n\r\n/*****************  Bit definition for FDCAN_TXEFA register  *********************/\r\n#define FDCAN_TXEFA_EFAI_Pos      (0U)\r\n#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */\r\n#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */\r\n\r\n/*****************  Bit definition for FDCAN_TTTMC register  *********************/\r\n#define FDCAN_TTTMC_TMSA_Pos      (2U)\r\n#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */\r\n#define FDCAN_TTTMC_TME_Pos       (16U)\r\n#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */\r\n\r\n/*****************  Bit definition for FDCAN_TTRMC register  *********************/\r\n#define FDCAN_TTRMC_RID_Pos       (0U)\r\n#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */\r\n#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */\r\n#define FDCAN_TTRMC_XTD_Pos       (30U)\r\n#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */\r\n#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */\r\n#define FDCAN_TTRMC_RMPS_Pos      (31U)\r\n#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */\r\n\r\n/*****************  Bit definition for FDCAN_TTOCF register  *********************/\r\n#define FDCAN_TTOCF_OM_Pos        (0U)\r\n#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */\r\n#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */\r\n#define FDCAN_TTOCF_GEN_Pos       (3U)\r\n#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */\r\n#define FDCAN_TTOCF_TM_Pos        (4U)\r\n#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */\r\n#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */\r\n#define FDCAN_TTOCF_LDSDL_Pos     (5U)\r\n#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */\r\n#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */\r\n#define FDCAN_TTOCF_IRTO_Pos      (8U)\r\n#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */\r\n#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */\r\n#define FDCAN_TTOCF_EECS_Pos      (15U)\r\n#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */\r\n#define FDCAN_TTOCF_AWL_Pos       (16U)\r\n#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */\r\n#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */\r\n#define FDCAN_TTOCF_EGTF_Pos      (24U)\r\n#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */\r\n#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */\r\n#define FDCAN_TTOCF_ECC_Pos       (25U)\r\n#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */\r\n#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */\r\n#define FDCAN_TTOCF_EVTP_Pos      (26U)\r\n#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */\r\n#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */\r\n\r\n/*****************  Bit definition for FDCAN_TTMLM register  *********************/\r\n#define FDCAN_TTMLM_CCM_Pos       (0U)\r\n#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */\r\n#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */\r\n#define FDCAN_TTMLM_CSS_Pos       (6U)\r\n#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */\r\n#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */\r\n#define FDCAN_TTMLM_TXEW_Pos      (8U)\r\n#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */\r\n#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */\r\n#define FDCAN_TTMLM_ENTT_Pos      (16U)\r\n#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */\r\n#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */\r\n\r\n/*****************  Bit definition for FDCAN_TURCF register  *********************/\r\n#define FDCAN_TURCF_NCL_Pos       (0U)\r\n#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */\r\n#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */\r\n#define FDCAN_TURCF_DC_Pos        (16U)\r\n#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */\r\n#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */\r\n#define FDCAN_TURCF_ELT_Pos       (31U)\r\n#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */\r\n#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */\r\n\r\n/*****************  Bit definition for FDCAN_TTOCN register  ********************/\r\n#define FDCAN_TTOCN_SGT_Pos       (0U)\r\n#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */\r\n#define FDCAN_TTOCN_ECS_Pos       (1U)\r\n#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */\r\n#define FDCAN_TTOCN_SWP_Pos       (2U)\r\n#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */\r\n#define FDCAN_TTOCN_SWS_Pos       (3U)\r\n#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */\r\n#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */\r\n#define FDCAN_TTOCN_RTIE_Pos      (5U)\r\n#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */\r\n#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */\r\n#define FDCAN_TTOCN_TMC_Pos       (6U)\r\n#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */\r\n#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */\r\n#define FDCAN_TTOCN_TTIE_Pos      (8U)\r\n#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */\r\n#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */\r\n#define FDCAN_TTOCN_GCS_Pos       (9U)\r\n#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */\r\n#define FDCAN_TTOCN_FGP_Pos       (10U)\r\n#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */\r\n#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */\r\n#define FDCAN_TTOCN_TMG_Pos       (11U)\r\n#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */\r\n#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */\r\n#define FDCAN_TTOCN_NIG_Pos       (12U)\r\n#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */\r\n#define FDCAN_TTOCN_ESCN_Pos      (13U)\r\n#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */\r\n#define FDCAN_TTOCN_LCKC_Pos      (15U)\r\n#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */\r\n\r\n/*****************  Bit definition for FDCAN_TTGTP register  ********************/\r\n#define FDCAN_TTGTP_TP_Pos        (0U)\r\n#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */\r\n#define FDCAN_TTGTP_CTP_Pos       (16U)\r\n#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */\r\n#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */\r\n\r\n/*****************  Bit definition for FDCAN_TTTMK register  ********************/\r\n#define FDCAN_TTTMK_TM_Pos        (0U)\r\n#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */\r\n#define FDCAN_TTTMK_TICC_Pos      (16U)\r\n#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */\r\n#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */\r\n#define FDCAN_TTTMK_LCKM_Pos      (31U)\r\n#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */\r\n\r\n/*****************  Bit definition for FDCAN_TTIR register  ********************/\r\n#define FDCAN_TTIR_SBC_Pos        (0U)\r\n#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */\r\n#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */\r\n#define FDCAN_TTIR_SMC_Pos        (1U)\r\n#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */\r\n#define FDCAN_TTIR_CSM_Pos        (2U)\r\n#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */\r\n#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */\r\n#define FDCAN_TTIR_SOG_Pos        (3U)\r\n#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */\r\n#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */\r\n#define FDCAN_TTIR_RTMI_Pos       (4U)\r\n#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */\r\n#define FDCAN_TTIR_TTMI_Pos       (5U)\r\n#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */\r\n#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */\r\n#define FDCAN_TTIR_SWE_Pos        (6U)\r\n#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */\r\n#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */\r\n#define FDCAN_TTIR_GTW_Pos        (7U)\r\n#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */\r\n#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */\r\n#define FDCAN_TTIR_GTD_Pos        (8U)\r\n#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */\r\n#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */\r\n#define FDCAN_TTIR_GTE_Pos        (9U)\r\n#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */\r\n#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */\r\n#define FDCAN_TTIR_TXU_Pos        (10U)\r\n#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */\r\n#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */\r\n#define FDCAN_TTIR_TXO_Pos        (11U)\r\n#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */\r\n#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */\r\n#define FDCAN_TTIR_SE1_Pos        (12U)\r\n#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */\r\n#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */\r\n#define FDCAN_TTIR_SE2_Pos        (13U)\r\n#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */\r\n#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */\r\n#define FDCAN_TTIR_ELC_Pos        (14U)\r\n#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */\r\n#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */\r\n#define FDCAN_TTIR_IWT_Pos        (15U)\r\n#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */\r\n#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */\r\n#define FDCAN_TTIR_WT_Pos         (16U)\r\n#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */\r\n#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */\r\n#define FDCAN_TTIR_AW_Pos         (17U)\r\n#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */\r\n#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */\r\n#define FDCAN_TTIR_CER_Pos        (18U)\r\n#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */\r\n#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */\r\n\r\n/*****************  Bit definition for FDCAN_TTIE register  ********************/\r\n#define FDCAN_TTIE_SBCE_Pos       (0U)\r\n#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */\r\n#define FDCAN_TTIE_SMCE_Pos       (1U)\r\n#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */\r\n#define FDCAN_TTIE_CSME_Pos       (2U)\r\n#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */\r\n#define FDCAN_TTIE_SOGE_Pos       (3U)\r\n#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */\r\n#define FDCAN_TTIE_RTMIE_Pos      (4U)\r\n#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */\r\n#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */\r\n#define FDCAN_TTIE_TTMIE_Pos      (5U)\r\n#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */\r\n#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */\r\n#define FDCAN_TTIE_SWEE_Pos       (6U)\r\n#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */\r\n#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */\r\n#define FDCAN_TTIE_GTWE_Pos       (7U)\r\n#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */\r\n#define FDCAN_TTIE_GTDE_Pos       (8U)\r\n#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */\r\n#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */\r\n#define FDCAN_TTIE_GTEE_Pos       (9U)\r\n#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */\r\n#define FDCAN_TTIE_TXUE_Pos       (10U)\r\n#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */\r\n#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */\r\n#define FDCAN_TTIE_TXOE_Pos       (11U)\r\n#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */\r\n#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */\r\n#define FDCAN_TTIE_SE1E_Pos       (12U)\r\n#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */\r\n#define FDCAN_TTIE_SE2E_Pos       (13U)\r\n#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */\r\n#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */\r\n#define FDCAN_TTIE_ELCE_Pos       (14U)\r\n#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */\r\n#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */\r\n#define FDCAN_TTIE_IWTE_Pos       (15U)\r\n#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */\r\n#define FDCAN_TTIE_WTE_Pos        (16U)\r\n#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */\r\n#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */\r\n#define FDCAN_TTIE_AWE_Pos        (17U)\r\n#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */\r\n#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */\r\n#define FDCAN_TTIE_CERE_Pos       (18U)\r\n#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */\r\n#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */\r\n\r\n/*****************  Bit definition for FDCAN_TTILS register  ********************/\r\n#define FDCAN_TTILS_SBCS_Pos      (0U)\r\n#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */\r\n#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */\r\n#define FDCAN_TTILS_SMCS_Pos      (1U)\r\n#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */\r\n#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */\r\n#define FDCAN_TTILS_CSMS_Pos      (2U)\r\n#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */\r\n#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */\r\n#define FDCAN_TTILS_SOGS_Pos      (3U)\r\n#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */\r\n#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */\r\n#define FDCAN_TTILS_RTMIS_Pos     (4U)\r\n#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */\r\n#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */\r\n#define FDCAN_TTILS_TTMIS_Pos     (5U)\r\n#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */\r\n#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */\r\n#define FDCAN_TTILS_SWES_Pos      (6U)\r\n#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */\r\n#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */\r\n#define FDCAN_TTILS_GTWS_Pos      (7U)\r\n#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */\r\n#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */\r\n#define FDCAN_TTILS_GTDS_Pos      (8U)\r\n#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */\r\n#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */\r\n#define FDCAN_TTILS_GTES_Pos      (9U)\r\n#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */\r\n#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */\r\n#define FDCAN_TTILS_TXUS_Pos      (10U)\r\n#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */\r\n#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */\r\n#define FDCAN_TTILS_TXOS_Pos      (11U)\r\n#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */\r\n#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */\r\n#define FDCAN_TTILS_SE1S_Pos      (12U)\r\n#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */\r\n#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */\r\n#define FDCAN_TTILS_SE2S_Pos      (13U)\r\n#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */\r\n#define FDCAN_TTILS_ELCS_Pos      (14U)\r\n#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */\r\n#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */\r\n#define FDCAN_TTILS_IWTS_Pos      (15U)\r\n#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */\r\n#define FDCAN_TTILS_WTS_Pos       (16U)\r\n#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */\r\n#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */\r\n#define FDCAN_TTILS_AWS_Pos       (17U)\r\n#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */\r\n#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */\r\n#define FDCAN_TTILS_CERS_Pos      (18U)\r\n#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */\r\n#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */\r\n\r\n/*****************  Bit definition for FDCAN_TTOST register  ********************/\r\n#define FDCAN_TTOST_EL_Pos        (0U)\r\n#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */\r\n#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */\r\n#define FDCAN_TTOST_MS_Pos        (2U)\r\n#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */\r\n#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */\r\n#define FDCAN_TTOST_SYS_Pos       (4U)\r\n#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */\r\n#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */\r\n#define FDCAN_TTOST_QGTP_Pos      (6U)\r\n#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */\r\n#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */\r\n#define FDCAN_TTOST_QCS_Pos       (7U)\r\n#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */\r\n#define FDCAN_TTOST_RTO_Pos       (8U)\r\n#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */\r\n#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */\r\n#define FDCAN_TTOST_WGTD_Pos      (22U)\r\n#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */\r\n#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */\r\n#define FDCAN_TTOST_GFI_Pos       (23U)\r\n#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */\r\n#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */\r\n#define FDCAN_TTOST_TMP_Pos       (24U)\r\n#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */\r\n#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */\r\n#define FDCAN_TTOST_GSI_Pos       (27U)\r\n#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */\r\n#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */\r\n#define FDCAN_TTOST_WFE_Pos       (28U)\r\n#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */\r\n#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */\r\n#define FDCAN_TTOST_AWE_Pos       (29U)\r\n#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */\r\n#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */\r\n#define FDCAN_TTOST_WECS_Pos      (30U)\r\n#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */\r\n#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */\r\n#define FDCAN_TTOST_SPL_Pos       (31U)\r\n#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */\r\n#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */\r\n\r\n/*****************  Bit definition for FDCAN_TURNA register  ********************/\r\n#define FDCAN_TURNA_NAV_Pos       (0U)\r\n#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */\r\n#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */\r\n\r\n/*****************  Bit definition for FDCAN_TTLGT register  ********************/\r\n#define FDCAN_TTLGT_LT_Pos        (0U)\r\n#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */\r\n#define FDCAN_TTLGT_GT_Pos        (16U)\r\n#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */\r\n#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */\r\n\r\n/*****************  Bit definition for FDCAN_TTCTC register  ********************/\r\n#define FDCAN_TTCTC_CT_Pos        (0U)\r\n#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */\r\n#define FDCAN_TTCTC_CC_Pos        (16U)\r\n#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */\r\n#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */\r\n\r\n/*****************  Bit definition for FDCAN_TTCPT register  ********************/\r\n#define FDCAN_TTCPT_CCV_Pos       (0U)\r\n#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */\r\n#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */\r\n#define FDCAN_TTCPT_SWV_Pos       (16U)\r\n#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */\r\n#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */\r\n\r\n/*****************  Bit definition for FDCAN_TTCSM register  ********************/\r\n#define FDCAN_TTCSM_CSM_Pos       (0U)\r\n#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */\r\n#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */\r\n\r\n/*****************  Bit definition for FDCAN_TTTS register  *********************/\r\n#define FDCAN_TTTS_SWTSEL_Pos     (0U)\r\n#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */\r\n#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */\r\n#define FDCAN_TTTS_EVTSEL_Pos     (4U)\r\n#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */\r\n#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */\r\n\r\n/********************************************************************************/\r\n/*                                                                              */\r\n/*                      FDCANCCU (Clock Calibration unit)                       */\r\n/*                                                                              */\r\n/********************************************************************************/\r\n\r\n/*****************  Bit definition for FDCANCCU_CREL register  ******************/\r\n#define FDCANCCU_CREL_DAY_Pos        (0U)\r\n#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */\r\n#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */\r\n#define FDCANCCU_CREL_MON_Pos        (8U)\r\n#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */\r\n#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */\r\n#define FDCANCCU_CREL_YEAR_Pos       (16U)\r\n#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */\r\n#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */\r\n#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)\r\n#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */\r\n#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */\r\n#define FDCANCCU_CREL_STEP_Pos       (24U)\r\n#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */\r\n#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */\r\n#define FDCANCCU_CREL_REL_Pos        (28U)\r\n#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */\r\n#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */\r\n\r\n/*****************  Bit definition for FDCANCCU_CCFG register  ******************/\r\n#define FDCANCCU_CCFG_TQBT_Pos       (0U)\r\n#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */\r\n#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */\r\n#define FDCANCCU_CCFG_BCC_Pos        (6U)\r\n#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */\r\n#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */\r\n#define FDCANCCU_CCFG_CFL_Pos        (7U)\r\n#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */\r\n#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */\r\n#define FDCANCCU_CCFG_OCPM_Pos       (8U)\r\n#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */\r\n#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */\r\n#define FDCANCCU_CCFG_CDIV_Pos       (16U)\r\n#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */\r\n#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */\r\n#define FDCANCCU_CCFG_SWR_Pos        (31U)\r\n#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */\r\n#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */\r\n\r\n/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/\r\n#define FDCANCCU_CSTAT_OCPC_Pos      (0U)\r\n#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */\r\n#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */\r\n#define FDCANCCU_CSTAT_TQC_Pos       (18U)\r\n#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */\r\n#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */\r\n#define FDCANCCU_CSTAT_CALS_Pos      (30U)\r\n#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */\r\n#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */\r\n\r\n/******************  Bit definition for FDCANCCU_CWD register  ******************/\r\n#define FDCANCCU_CWD_WDC_Pos         (0U)\r\n#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */\r\n#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */\r\n#define FDCANCCU_CWD_WDV_Pos         (16U)\r\n#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */\r\n#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */\r\n\r\n/******************  Bit definition for FDCANCCU_IR register  *******************/\r\n#define FDCANCCU_IR_CWE_Pos          (0U)\r\n#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */\r\n#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */\r\n#define FDCANCCU_IR_CSC_Pos          (1U)\r\n#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */\r\n#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */\r\n\r\n/******************  Bit definition for FDCANCCU_IE register  *******************/\r\n#define FDCANCCU_IE_CWEE_Pos         (0U)\r\n#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */\r\n#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */\r\n#define FDCANCCU_IE_CSCE_Pos         (1U)\r\n#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */\r\n#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          HDMI-CEC (CEC)                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for CEC_CR register  *********************/\r\n#define CEC_CR_CECEN_Pos         (0U)\r\n#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */\r\n#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */\r\n#define CEC_CR_TXSOM_Pos         (1U)\r\n#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */\r\n#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */\r\n#define CEC_CR_TXEOM_Pos         (2U)\r\n#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */\r\n#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */\r\n\r\n/*******************  Bit definition for CEC_CFGR register  *******************/\r\n#define CEC_CFGR_SFT_Pos         (0U)\r\n#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */\r\n#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */\r\n#define CEC_CFGR_RXTOL_Pos       (3U)\r\n#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */\r\n#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */\r\n#define CEC_CFGR_BRESTP_Pos      (4U)\r\n#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */\r\n#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */\r\n#define CEC_CFGR_BREGEN_Pos      (5U)\r\n#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */\r\n#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */\r\n#define CEC_CFGR_LBPEGEN_Pos     (6U)\r\n#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */\r\n#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */\r\n#define CEC_CFGR_SFTOPT_Pos      (8U)\r\n#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */\r\n#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */\r\n#define CEC_CFGR_BRDNOGEN_Pos    (7U)\r\n#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */\r\n#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */\r\n#define CEC_CFGR_OAR_Pos         (16U)\r\n#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */\r\n#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */\r\n#define CEC_CFGR_LSTN_Pos        (31U)\r\n#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */\r\n#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */\r\n\r\n/*******************  Bit definition for CEC_TXDR register  *******************/\r\n#define CEC_TXDR_TXD_Pos         (0U)\r\n#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */\r\n#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */\r\n\r\n/*******************  Bit definition for CEC_RXDR register  *******************/\r\n#define CEC_RXDR_RXD_Pos         (0U)\r\n#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */\r\n#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */\r\n\r\n/*******************  Bit definition for CEC_ISR register  ********************/\r\n#define CEC_ISR_RXBR_Pos         (0U)\r\n#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */\r\n#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */\r\n#define CEC_ISR_RXEND_Pos        (1U)\r\n#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */\r\n#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */\r\n#define CEC_ISR_RXOVR_Pos        (2U)\r\n#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */\r\n#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */\r\n#define CEC_ISR_BRE_Pos          (3U)\r\n#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */\r\n#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */\r\n#define CEC_ISR_SBPE_Pos         (4U)\r\n#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */\r\n#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */\r\n#define CEC_ISR_LBPE_Pos         (5U)\r\n#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */\r\n#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */\r\n#define CEC_ISR_RXACKE_Pos       (6U)\r\n#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */\r\n#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */\r\n#define CEC_ISR_ARBLST_Pos       (7U)\r\n#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */\r\n#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */\r\n#define CEC_ISR_TXBR_Pos         (8U)\r\n#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */\r\n#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */\r\n#define CEC_ISR_TXEND_Pos        (9U)\r\n#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */\r\n#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */\r\n#define CEC_ISR_TXUDR_Pos        (10U)\r\n#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */\r\n#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */\r\n#define CEC_ISR_TXERR_Pos        (11U)\r\n#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */\r\n#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */\r\n#define CEC_ISR_TXACKE_Pos       (12U)\r\n#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */\r\n#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */\r\n\r\n/*******************  Bit definition for CEC_IER register  ********************/\r\n#define CEC_IER_RXBRIE_Pos       (0U)\r\n#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */\r\n#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */\r\n#define CEC_IER_RXENDIE_Pos      (1U)\r\n#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */\r\n#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */\r\n#define CEC_IER_RXOVRIE_Pos      (2U)\r\n#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */\r\n#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */\r\n#define CEC_IER_BREIE_Pos        (3U)\r\n#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */\r\n#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */\r\n#define CEC_IER_SBPEIE_Pos       (4U)\r\n#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */\r\n#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */\r\n#define CEC_IER_LBPEIE_Pos       (5U)\r\n#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */\r\n#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */\r\n#define CEC_IER_RXACKEIE_Pos     (6U)\r\n#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */\r\n#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */\r\n#define CEC_IER_ARBLSTIE_Pos     (7U)\r\n#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */\r\n#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */\r\n#define CEC_IER_TXBRIE_Pos       (8U)\r\n#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */\r\n#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */\r\n#define CEC_IER_TXENDIE_Pos      (9U)\r\n#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */\r\n#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */\r\n#define CEC_IER_TXUDRIE_Pos      (10U)\r\n#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */\r\n#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */\r\n#define CEC_IER_TXERRIE_Pos      (11U)\r\n#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */\r\n#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */\r\n#define CEC_IER_TXACKEIE_Pos     (12U)\r\n#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */\r\n#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CORDIC calculation unit                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for CORDIC_CSR register  *****************/\r\n#define CORDIC_CSR_FUNC_Pos      (0U)\r\n#define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */\r\n#define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */\r\n#define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */\r\n#define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */\r\n#define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */\r\n#define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */\r\n#define CORDIC_CSR_PRECISION_Pos (4U)\r\n#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */\r\n#define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */\r\n#define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */\r\n#define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */\r\n#define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */\r\n#define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */\r\n#define CORDIC_CSR_SCALE_Pos     (8U)\r\n#define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */\r\n#define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */\r\n#define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */\r\n#define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */\r\n#define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */\r\n#define CORDIC_CSR_IEN_Pos       (16U)\r\n#define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */\r\n#define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */\r\n#define CORDIC_CSR_DMAREN_Pos    (17U)\r\n#define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */\r\n#define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */\r\n#define CORDIC_CSR_DMAWEN_Pos    (18U)\r\n#define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */\r\n#define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */\r\n#define CORDIC_CSR_NRES_Pos      (19U)\r\n#define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */\r\n#define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */\r\n#define CORDIC_CSR_NARGS_Pos     (20U)\r\n#define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */\r\n#define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */\r\n#define CORDIC_CSR_RESSIZE_Pos   (21U)\r\n#define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */\r\n#define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */\r\n#define CORDIC_CSR_ARGSIZE_Pos   (22U)\r\n#define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */\r\n#define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */\r\n#define CORDIC_CSR_RRDY_Pos      (31U)\r\n#define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */\r\n#define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */\r\n\r\n/*******************  Bit definition for CORDIC_WDATA register  ***************/\r\n#define CORDIC_WDATA_ARG_Pos     (0U)\r\n#define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */\r\n#define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */\r\n\r\n/*******************  Bit definition for CORDIC_RDATA register  ***************/\r\n#define CORDIC_RDATA_RES_Pos     (0U)\r\n#define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */\r\n#define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CRC calculation unit                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for CRC_DR register  *********************/\r\n#define CRC_DR_DR_Pos            (0U)\r\n#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */\r\n#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\r\n\r\n/*******************  Bit definition for CRC_IDR register  ********************/\r\n#define CRC_IDR_IDR_Pos          (0U)\r\n#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */\r\n#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */\r\n\r\n/********************  Bit definition for CRC_CR register  ********************/\r\n#define CRC_CR_RESET_Pos         (0U)\r\n#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */\r\n#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\r\n#define CRC_CR_POLYSIZE_Pos      (3U)\r\n#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */\r\n#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */\r\n#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */\r\n#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */\r\n#define CRC_CR_REV_IN_Pos        (5U)\r\n#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */\r\n#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */\r\n#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */\r\n#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */\r\n#define CRC_CR_REV_OUT_Pos       (7U)\r\n#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */\r\n#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */\r\n\r\n/*******************  Bit definition for CRC_INIT register  *******************/\r\n#define CRC_INIT_INIT_Pos        (0U)\r\n#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */\r\n#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */\r\n\r\n/*******************  Bit definition for CRC_POL register  ********************/\r\n#define CRC_POL_POL_Pos          (0U)\r\n#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */\r\n#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CRS Clock Recovery System                         */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for CRS_CR register  *********************/\r\n#define CRS_CR_SYNCOKIE_Pos       (0U)\r\n#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */\r\n#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */\r\n#define CRS_CR_SYNCWARNIE_Pos     (1U)\r\n#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */\r\n#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */\r\n#define CRS_CR_ERRIE_Pos          (2U)\r\n#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */\r\n#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */\r\n#define CRS_CR_ESYNCIE_Pos        (3U)\r\n#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */\r\n#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */\r\n#define CRS_CR_CEN_Pos            (5U)\r\n#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */\r\n#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */\r\n#define CRS_CR_AUTOTRIMEN_Pos     (6U)\r\n#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */\r\n#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */\r\n#define CRS_CR_SWSYNC_Pos         (7U)\r\n#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */\r\n#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */\r\n#define CRS_CR_TRIM_Pos           (8U)\r\n#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */\r\n#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */\r\n\r\n/*******************  Bit definition for CRS_CFGR register  *********************/\r\n#define CRS_CFGR_RELOAD_Pos       (0U)\r\n#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */\r\n#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */\r\n#define CRS_CFGR_FELIM_Pos        (16U)\r\n#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */\r\n#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */\r\n\r\n#define CRS_CFGR_SYNCDIV_Pos      (24U)\r\n#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */\r\n#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */\r\n#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */\r\n#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */\r\n#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */\r\n\r\n#define CRS_CFGR_SYNCSRC_Pos      (28U)\r\n#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */\r\n#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */\r\n#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */\r\n#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */\r\n\r\n#define CRS_CFGR_SYNCPOL_Pos      (31U)\r\n#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */\r\n#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */\r\n\r\n/*******************  Bit definition for CRS_ISR register  *********************/\r\n#define CRS_ISR_SYNCOKF_Pos       (0U)\r\n#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */\r\n#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */\r\n#define CRS_ISR_SYNCWARNF_Pos     (1U)\r\n#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */\r\n#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */\r\n#define CRS_ISR_ERRF_Pos          (2U)\r\n#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */\r\n#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */\r\n#define CRS_ISR_ESYNCF_Pos        (3U)\r\n#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */\r\n#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */\r\n#define CRS_ISR_SYNCERR_Pos       (8U)\r\n#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */\r\n#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */\r\n#define CRS_ISR_SYNCMISS_Pos      (9U)\r\n#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */\r\n#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */\r\n#define CRS_ISR_TRIMOVF_Pos       (10U)\r\n#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */\r\n#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */\r\n#define CRS_ISR_FEDIR_Pos         (15U)\r\n#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */\r\n#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */\r\n#define CRS_ISR_FECAP_Pos         (16U)\r\n#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */\r\n#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */\r\n\r\n/*******************  Bit definition for CRS_ICR register  *********************/\r\n#define CRS_ICR_SYNCOKC_Pos       (0U)\r\n#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */\r\n#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */\r\n#define CRS_ICR_SYNCWARNC_Pos     (1U)\r\n#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */\r\n#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */\r\n#define CRS_ICR_ERRC_Pos          (2U)\r\n#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */\r\n#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */\r\n#define CRS_ICR_ESYNCC_Pos        (3U)\r\n#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */\r\n#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            Crypto Processor                                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************************  CRYP VER  **********************************/\r\n#define  CRYP_VER_2_2\r\n/******************* Bits definition for CRYP_CR register  ********************/\r\n#define CRYP_CR_ALGODIR_Pos              (2U)\r\n#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */\r\n#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk\r\n\r\n#define CRYP_CR_ALGOMODE_Pos             (3U)\r\n#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */\r\n#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk\r\n#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */\r\n#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */\r\n#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */\r\n#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */\r\n#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk\r\n#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)\r\n#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */\r\n#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk\r\n#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */\r\n#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk\r\n#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)\r\n#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */\r\n#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk\r\n#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */\r\n#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk\r\n#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)\r\n#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */\r\n#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk\r\n#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */\r\n#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk\r\n#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)\r\n#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */\r\n#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk\r\n#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */\r\n#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk\r\n\r\n#define CRYP_CR_DATATYPE_Pos             (6U)\r\n#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */\r\n#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk\r\n#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */\r\n#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */\r\n#define CRYP_CR_KEYSIZE_Pos              (8U)\r\n#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */\r\n#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk\r\n#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */\r\n#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */\r\n#define CRYP_CR_FFLUSH_Pos               (14U)\r\n#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */\r\n#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk\r\n#define CRYP_CR_CRYPEN_Pos               (15U)\r\n#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */\r\n#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk\r\n\r\n#define CRYP_CR_GCM_CCMPH_Pos            (16U)\r\n#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */\r\n#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk\r\n#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */\r\n#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */\r\n#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)\r\n#define CRYP_CR_NPBLB_Pos                (20U)\r\n#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */\r\n#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk\r\n\r\n/****************** Bits definition for CRYP_SR register  *********************/\r\n#define CRYP_SR_IFEM_Pos                 (0U)\r\n#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */\r\n#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk\r\n#define CRYP_SR_IFNF_Pos                 (1U)\r\n#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */\r\n#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk\r\n#define CRYP_SR_OFNE_Pos                 (2U)\r\n#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */\r\n#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk\r\n#define CRYP_SR_OFFU_Pos                 (3U)\r\n#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */\r\n#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk\r\n#define CRYP_SR_BUSY_Pos                 (4U)\r\n#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */\r\n#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk\r\n/****************** Bits definition for CRYP_DMACR register  ******************/\r\n#define CRYP_DMACR_DIEN_Pos              (0U)\r\n#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */\r\n#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk\r\n#define CRYP_DMACR_DOEN_Pos              (1U)\r\n#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */\r\n#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk\r\n/*****************  Bits definition for CRYP_IMSCR register  ******************/\r\n#define CRYP_IMSCR_INIM_Pos              (0U)\r\n#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */\r\n#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk\r\n#define CRYP_IMSCR_OUTIM_Pos             (1U)\r\n#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */\r\n#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk\r\n/****************** Bits definition for CRYP_RISR register  *******************/\r\n#define CRYP_RISR_INRIS_Pos              (0U)\r\n#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */\r\n#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk\r\n#define CRYP_RISR_OUTRIS_Pos             (1U)\r\n#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */\r\n#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk\r\n/****************** Bits definition for CRYP_MISR register  *******************/\r\n#define CRYP_MISR_INMIS_Pos              (0U)\r\n#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */\r\n#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk\r\n#define CRYP_MISR_OUTMIS_Pos             (1U)\r\n#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */\r\n#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Digital to Analog Converter                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DAC_CR register  ********************/\r\n#define DAC_CR_EN1_Pos              (0U)\r\n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */\r\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\r\n#define DAC_CR_TEN1_Pos             (1U)\r\n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */\r\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\r\n\r\n#define DAC_CR_TSEL1_Pos            (2U)\r\n#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */\r\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */\r\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\r\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\r\n#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\r\n\r\n\r\n#define DAC_CR_WAVE1_Pos            (6U)\r\n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */\r\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\r\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\r\n\r\n#define DAC_CR_MAMP1_Pos            (8U)\r\n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */\r\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\r\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\r\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\r\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\r\n\r\n#define DAC_CR_DMAEN1_Pos           (12U)\r\n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */\r\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\r\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\r\n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */\r\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/\r\n#define DAC_CR_CEN1_Pos             (14U)\r\n#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */\r\n#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/\r\n\r\n#define DAC_CR_EN2_Pos              (16U)\r\n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */\r\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\r\n#define DAC_CR_TEN2_Pos             (17U)\r\n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */\r\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\r\n\r\n#define DAC_CR_TSEL2_Pos            (18U)\r\n#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */\r\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */\r\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\r\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\r\n#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\r\n\r\n\r\n#define DAC_CR_WAVE2_Pos            (22U)\r\n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */\r\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\r\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\r\n\r\n#define DAC_CR_MAMP2_Pos            (24U)\r\n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */\r\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\r\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\r\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\r\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\r\n\r\n#define DAC_CR_DMAEN2_Pos           (28U)\r\n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */\r\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\r\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\r\n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */\r\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/\r\n#define DAC_CR_CEN2_Pos             (30U)\r\n#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */\r\n#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/\r\n\r\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\r\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */\r\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\r\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\r\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */\r\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\r\n\r\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\r\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */\r\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\r\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\r\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\r\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */\r\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\r\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */\r\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\r\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */\r\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\r\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\r\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */\r\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\r\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\r\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */\r\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\r\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */\r\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\r\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\r\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\r\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */\r\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8RD register  ******************/\r\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\r\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */\r\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\r\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */\r\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*******************  Bit definition for DAC_DOR1 register  *******************/\r\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\r\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */\r\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\r\n\r\n/*******************  Bit definition for DAC_DOR2 register  *******************/\r\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\r\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */\r\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\r\n\r\n/********************  Bit definition for DAC_SR register  ********************/\r\n#define DAC_SR_DMAUDR1_Pos          (13U)\r\n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */\r\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\r\n#define DAC_SR_CAL_FLAG1_Pos        (14U)\r\n#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */\r\n#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */\r\n#define DAC_SR_BWST1_Pos            (15U)\r\n#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */\r\n#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */\r\n\r\n#define DAC_SR_DMAUDR2_Pos          (29U)\r\n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */\r\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\r\n#define DAC_SR_CAL_FLAG2_Pos        (30U)\r\n#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */\r\n#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */\r\n#define DAC_SR_BWST2_Pos            (31U)\r\n#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */\r\n#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */\r\n\r\n/*******************  Bit definition for DAC_CCR register  ********************/\r\n#define DAC_CCR_OTRIM1_Pos          (0U)\r\n#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */\r\n#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */\r\n#define DAC_CCR_OTRIM2_Pos          (16U)\r\n#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */\r\n#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */\r\n\r\n/*******************  Bit definition for DAC_MCR register  *******************/\r\n#define DAC_MCR_MODE1_Pos           (0U)\r\n#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */\r\n#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */\r\n#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */\r\n#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */\r\n#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */\r\n\r\n#define DAC_MCR_MODE2_Pos           (16U)\r\n#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */\r\n#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */\r\n#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */\r\n#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */\r\n#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */\r\n\r\n/******************  Bit definition for DAC_SHSR1 register  ******************/\r\n#define DAC_SHSR1_TSAMPLE1_Pos      (0U)\r\n#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */\r\n#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */\r\n\r\n/******************  Bit definition for DAC_SHSR2 register  ******************/\r\n#define DAC_SHSR2_TSAMPLE2_Pos      (0U)\r\n#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */\r\n#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */\r\n\r\n/******************  Bit definition for DAC_SHHR register  ******************/\r\n#define DAC_SHHR_THOLD1_Pos         (0U)\r\n#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */\r\n#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */\r\n#define DAC_SHHR_THOLD2_Pos         (16U)\r\n#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */\r\n#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */\r\n\r\n/******************  Bit definition for DAC_SHRR register  ******************/\r\n#define DAC_SHRR_TREFRESH1_Pos      (0U)\r\n#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */\r\n#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */\r\n#define DAC_SHRR_TREFRESH2_Pos      (16U)\r\n#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */\r\n#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    DCMI                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DCMI_CR register  ******************/\r\n#define DCMI_CR_CAPTURE_Pos        (0U)\r\n#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */\r\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk\r\n#define DCMI_CR_CM_Pos             (1U)\r\n#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */\r\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk\r\n#define DCMI_CR_CROP_Pos           (2U)\r\n#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */\r\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk\r\n#define DCMI_CR_JPEG_Pos           (3U)\r\n#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */\r\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk\r\n#define DCMI_CR_ESS_Pos            (4U)\r\n#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */\r\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk\r\n#define DCMI_CR_PCKPOL_Pos         (5U)\r\n#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */\r\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk\r\n#define DCMI_CR_HSPOL_Pos          (6U)\r\n#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */\r\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk\r\n#define DCMI_CR_VSPOL_Pos          (7U)\r\n#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */\r\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk\r\n#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)\r\n#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)\r\n#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)\r\n#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)\r\n#define DCMI_CR_CRE_Pos            (12U)\r\n#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */\r\n#define DCMI_CR_CRE                DCMI_CR_CRE_Msk\r\n#define DCMI_CR_ENABLE_Pos         (14U)\r\n#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */\r\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk\r\n#define DCMI_CR_BSM_Pos            (16U)\r\n#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */\r\n#define DCMI_CR_BSM                DCMI_CR_BSM_Msk\r\n#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */\r\n#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */\r\n#define DCMI_CR_OEBS_Pos           (18U)\r\n#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */\r\n#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk\r\n#define DCMI_CR_LSM_Pos            (19U)\r\n#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */\r\n#define DCMI_CR_LSM                DCMI_CR_LSM_Msk\r\n#define DCMI_CR_OELS_Pos           (20U)\r\n#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */\r\n#define DCMI_CR_OELS               DCMI_CR_OELS_Msk\r\n\r\n/********************  Bits definition for DCMI_SR register  ******************/\r\n#define DCMI_SR_HSYNC_Pos          (0U)\r\n#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */\r\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk\r\n#define DCMI_SR_VSYNC_Pos          (1U)\r\n#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */\r\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk\r\n#define DCMI_SR_FNE_Pos            (2U)\r\n#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */\r\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk\r\n\r\n/********************  Bits definition for DCMI_RIS register   ****************/\r\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)\r\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */\r\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk\r\n#define DCMI_RIS_OVR_RIS_Pos       (1U)\r\n#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */\r\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk\r\n#define DCMI_RIS_ERR_RIS_Pos       (2U)\r\n#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */\r\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk\r\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)\r\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */\r\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk\r\n#define DCMI_RIS_LINE_RIS_Pos      (4U)\r\n#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */\r\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk\r\n\r\n/********************  Bits definition for DCMI_IER register  *****************/\r\n#define DCMI_IER_FRAME_IE_Pos      (0U)\r\n#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */\r\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk\r\n#define DCMI_IER_OVR_IE_Pos        (1U)\r\n#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */\r\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk\r\n#define DCMI_IER_ERR_IE_Pos        (2U)\r\n#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */\r\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk\r\n#define DCMI_IER_VSYNC_IE_Pos      (3U)\r\n#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */\r\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk\r\n#define DCMI_IER_LINE_IE_Pos       (4U)\r\n#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */\r\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk\r\n\r\n\r\n/********************  Bits definition for DCMI_MIS register  *****************/\r\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)\r\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */\r\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk\r\n#define DCMI_MIS_OVR_MIS_Pos       (1U)\r\n#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */\r\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk\r\n#define DCMI_MIS_ERR_MIS_Pos       (2U)\r\n#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */\r\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk\r\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)\r\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */\r\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk\r\n#define DCMI_MIS_LINE_MIS_Pos      (4U)\r\n#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */\r\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk\r\n\r\n\r\n/********************  Bits definition for DCMI_ICR register  *****************/\r\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)\r\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */\r\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk\r\n#define DCMI_ICR_OVR_ISC_Pos       (1U)\r\n#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */\r\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk\r\n#define DCMI_ICR_ERR_ISC_Pos       (2U)\r\n#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */\r\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk\r\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)\r\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */\r\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk\r\n#define DCMI_ICR_LINE_ISC_Pos      (4U)\r\n#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */\r\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk\r\n\r\n\r\n/********************  Bits definition for DCMI_ESCR register  ******************/\r\n#define DCMI_ESCR_FSC_Pos          (0U)\r\n#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */\r\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk\r\n#define DCMI_ESCR_LSC_Pos          (8U)\r\n#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */\r\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk\r\n#define DCMI_ESCR_LEC_Pos          (16U)\r\n#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */\r\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk\r\n#define DCMI_ESCR_FEC_Pos          (24U)\r\n#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */\r\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk\r\n\r\n/********************  Bits definition for DCMI_ESUR register  ******************/\r\n#define DCMI_ESUR_FSU_Pos          (0U)\r\n#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */\r\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk\r\n#define DCMI_ESUR_LSU_Pos          (8U)\r\n#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */\r\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk\r\n#define DCMI_ESUR_LEU_Pos          (16U)\r\n#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */\r\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk\r\n#define DCMI_ESUR_FEU_Pos          (24U)\r\n#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */\r\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk\r\n\r\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\r\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)\r\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */\r\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk\r\n#define DCMI_CWSTRT_VST_Pos        (16U)\r\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */\r\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk\r\n\r\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\r\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)\r\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */\r\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk\r\n#define DCMI_CWSIZE_VLINE_Pos      (16U)\r\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */\r\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk\r\n\r\n/********************  Bits definition for DCMI_DR register  ******************/\r\n#define DCMI_DR_BYTE0_Pos          (0U)\r\n#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */\r\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk\r\n#define DCMI_DR_BYTE1_Pos          (8U)\r\n#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */\r\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk\r\n#define DCMI_DR_BYTE2_Pos          (16U)\r\n#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */\r\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk\r\n#define DCMI_DR_BYTE3_Pos          (24U)\r\n#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */\r\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                 Digital Filter for Sigma Delta Modulators                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/****************   DFSDM channel configuration registers  ********************/\r\n\r\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\r\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\r\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */\r\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\r\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\r\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */\r\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\r\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\r\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\r\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\r\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\r\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */\r\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\r\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\r\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\r\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\r\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */\r\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\r\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\r\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\r\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\r\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */\r\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\r\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\r\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */\r\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\r\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\r\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */\r\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\r\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\r\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */\r\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\r\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\r\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */\r\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\r\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\r\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\r\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\r\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */\r\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\r\n#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\r\n#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\r\n\r\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\r\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\r\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\r\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */\r\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\r\n\r\n/******************  Bit definition for DFSDM_CHAWSCDR register *****************/\r\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\r\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */\r\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\r\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\r\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\r\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */\r\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\r\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */\r\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\r\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */\r\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r\n\r\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\r\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\r\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */\r\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\r\n\r\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\r\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\r\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\r\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\r\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\r\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\r\n\r\n/************************   DFSDM module registers  ****************************/\r\n\r\n/********************  Bit definition for DFSDM_FLTCR1 register *******************/\r\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\r\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */\r\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\r\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\r\n#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */\r\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\r\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\r\n#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */\r\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\r\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\r\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */\r\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\r\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\r\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */\r\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\r\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\r\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */\r\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\r\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\r\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */\r\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\r\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\r\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */\r\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\r\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\r\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\r\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */\r\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */\r\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */\r\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */\r\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */\r\n#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */\r\n#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */\r\n\r\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\r\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */\r\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\r\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\r\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */\r\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\r\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\r\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */\r\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\r\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\r\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */\r\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\r\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\r\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */\r\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\r\n\r\n/********************  Bit definition for DFSDM_FLTCR2 register *******************/\r\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\r\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */\r\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\r\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\r\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */\r\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\r\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\r\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */\r\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\r\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\r\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */\r\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\r\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\r\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */\r\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\r\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\r\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */\r\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\r\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\r\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */\r\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\r\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\r\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */\r\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\r\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\r\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */\r\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\r\n\r\n/********************  Bit definition for DFSDM_FLTISR register *******************/\r\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\r\n#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */\r\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\r\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\r\n#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */\r\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\r\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\r\n#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */\r\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\r\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\r\n#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */\r\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\r\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\r\n#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */\r\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\r\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\r\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */\r\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\r\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\r\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */\r\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\r\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\r\n#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */\r\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\r\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\r\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */\r\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\r\n\r\n/********************  Bit definition for DFSDM_FLTICR register *******************/\r\n#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)\r\n#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */\r\n#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\r\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\r\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */\r\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\r\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\r\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */\r\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\r\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\r\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */\r\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\r\n\r\n/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/\r\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\r\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */\r\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\r\n\r\n/********************  Bit definition for DFSDM_FLTFCR register *******************/\r\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\r\n#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */\r\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\r\n#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\r\n#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\r\n#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\r\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\r\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */\r\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\r\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */\r\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r\n\r\n/******************  Bit definition for DFSDM_FLTJDATAR register *****************/\r\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\r\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\r\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\r\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\r\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\r\n\r\n/******************  Bit definition for DFSDM_FLTRDATAR register *****************/\r\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\r\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\r\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\r\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */\r\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\r\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\r\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\r\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWHTR register ******************/\r\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\r\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\r\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\r\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */\r\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWLTR register ******************/\r\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\r\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */\r\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\r\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */\r\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWSR register ******************/\r\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\r\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */\r\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\r\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */\r\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/\r\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\r\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\r\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\r\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\r\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r\n\r\n/******************  Bit definition for DFSDM_FLTEXMAX register ******************/\r\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\r\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\r\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\r\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */\r\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r\n\r\n/******************  Bit definition for DFSDM_FLTEXMIN register ******************/\r\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\r\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\r\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\r\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */\r\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r\n\r\n/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/\r\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\r\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\r\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           BDMA Controller                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for BDMA_ISR register  ********************/\r\n#define BDMA_ISR_GIF0_Pos       (0U)\r\n#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */\r\n#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */\r\n#define BDMA_ISR_TCIF0_Pos      (1U)\r\n#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */\r\n#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF0_Pos      (2U)\r\n#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */\r\n#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */\r\n#define BDMA_ISR_TEIF0_Pos      (3U)\r\n#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */\r\n#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */\r\n#define BDMA_ISR_GIF1_Pos       (4U)\r\n#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */\r\n#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */\r\n#define BDMA_ISR_TCIF1_Pos      (5U)\r\n#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */\r\n#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF1_Pos      (6U)\r\n#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */\r\n#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */\r\n#define BDMA_ISR_TEIF1_Pos      (7U)\r\n#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */\r\n#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */\r\n#define BDMA_ISR_GIF2_Pos       (8U)\r\n#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */\r\n#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */\r\n#define BDMA_ISR_TCIF2_Pos      (9U)\r\n#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */\r\n#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF2_Pos      (10U)\r\n#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */\r\n#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */\r\n#define BDMA_ISR_TEIF2_Pos      (11U)\r\n#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */\r\n#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */\r\n#define BDMA_ISR_GIF3_Pos       (12U)\r\n#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */\r\n#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */\r\n#define BDMA_ISR_TCIF3_Pos      (13U)\r\n#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */\r\n#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF3_Pos      (14U)\r\n#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */\r\n#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */\r\n#define BDMA_ISR_TEIF3_Pos      (15U)\r\n#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */\r\n#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */\r\n#define BDMA_ISR_GIF4_Pos       (16U)\r\n#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */\r\n#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */\r\n#define BDMA_ISR_TCIF4_Pos      (17U)\r\n#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */\r\n#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF4_Pos      (18U)\r\n#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */\r\n#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */\r\n#define BDMA_ISR_TEIF4_Pos      (19U)\r\n#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */\r\n#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */\r\n#define BDMA_ISR_GIF5_Pos       (20U)\r\n#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */\r\n#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */\r\n#define BDMA_ISR_TCIF5_Pos      (21U)\r\n#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */\r\n#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF5_Pos      (22U)\r\n#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */\r\n#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */\r\n#define BDMA_ISR_TEIF5_Pos      (23U)\r\n#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */\r\n#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */\r\n#define BDMA_ISR_GIF6_Pos       (24U)\r\n#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */\r\n#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */\r\n#define BDMA_ISR_TCIF6_Pos      (25U)\r\n#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */\r\n#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF6_Pos      (26U)\r\n#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */\r\n#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */\r\n#define BDMA_ISR_TEIF6_Pos      (27U)\r\n#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */\r\n#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */\r\n#define BDMA_ISR_GIF7_Pos       (28U)\r\n#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */\r\n#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */\r\n#define BDMA_ISR_TCIF7_Pos      (29U)\r\n#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */\r\n#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF7_Pos      (30U)\r\n#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */\r\n#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */\r\n#define BDMA_ISR_TEIF7_Pos      (31U)\r\n#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */\r\n#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */\r\n\r\n/*******************  Bit definition for BDMA_IFCR register  *******************/\r\n#define BDMA_IFCR_CGIF0_Pos     (0U)\r\n#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */\r\n#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */\r\n#define BDMA_IFCR_CTCIF0_Pos    (1U)\r\n#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */\r\n#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF0_Pos    (2U)\r\n#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */\r\n#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF0_Pos    (3U)\r\n#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */\r\n#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF1_Pos     (4U)\r\n#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */\r\n#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF1_Pos    (5U)\r\n#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */\r\n#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF1_Pos    (6U)\r\n#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */\r\n#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF1_Pos    (7U)\r\n#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */\r\n#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF2_Pos     (8U)\r\n#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */\r\n#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF2_Pos    (9U)\r\n#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */\r\n#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF2_Pos    (10U)\r\n#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */\r\n#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF2_Pos    (11U)\r\n#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */\r\n#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF3_Pos     (12U)\r\n#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */\r\n#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF3_Pos    (13U)\r\n#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */\r\n#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF3_Pos    (14U)\r\n#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */\r\n#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF3_Pos    (15U)\r\n#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */\r\n#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF4_Pos     (16U)\r\n#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */\r\n#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF4_Pos    (17U)\r\n#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */\r\n#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF4_Pos    (18U)\r\n#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */\r\n#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF4_Pos    (19U)\r\n#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */\r\n#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF5_Pos     (20U)\r\n#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */\r\n#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF5_Pos    (21U)\r\n#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */\r\n#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF5_Pos    (22U)\r\n#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */\r\n#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF5_Pos    (23U)\r\n#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */\r\n#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF6_Pos     (24U)\r\n#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */\r\n#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF6_Pos    (25U)\r\n#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */\r\n#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF6_Pos    (26U)\r\n#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */\r\n#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF6_Pos    (27U)\r\n#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */\r\n#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF7_Pos     (28U)\r\n#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */\r\n#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF7_Pos    (29U)\r\n#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */\r\n#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF7_Pos    (30U)\r\n#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */\r\n#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF7_Pos    (31U)\r\n#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */\r\n#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */\r\n\r\n/*******************  Bit definition for BDMA_CCR register  ********************/\r\n#define BDMA_CCR_EN_Pos         (0U)\r\n#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */\r\n#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */\r\n#define BDMA_CCR_TCIE_Pos       (1U)\r\n#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */\r\n#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */\r\n#define BDMA_CCR_HTIE_Pos       (2U)\r\n#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */\r\n#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */\r\n#define BDMA_CCR_TEIE_Pos       (3U)\r\n#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */\r\n#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */\r\n#define BDMA_CCR_DIR_Pos        (4U)\r\n#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */\r\n#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */\r\n#define BDMA_CCR_CIRC_Pos       (5U)\r\n#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */\r\n#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */\r\n#define BDMA_CCR_PINC_Pos       (6U)\r\n#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */\r\n#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */\r\n#define BDMA_CCR_MINC_Pos       (7U)\r\n#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */\r\n#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */\r\n\r\n#define BDMA_CCR_PSIZE_Pos      (8U)\r\n#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */\r\n#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */\r\n#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */\r\n#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */\r\n\r\n#define BDMA_CCR_MSIZE_Pos      (10U)\r\n#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */\r\n#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */\r\n#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */\r\n#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */\r\n\r\n#define BDMA_CCR_PL_Pos         (12U)\r\n#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */\r\n#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/\r\n#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */\r\n#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */\r\n\r\n#define BDMA_CCR_MEM2MEM_Pos    (14U)\r\n#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */\r\n#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */\r\n#define BDMA_CCR_DBM_Pos        (15U)\r\n#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */\r\n#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */\r\n#define BDMA_CCR_CT_Pos         (16U)\r\n#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */\r\n#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */\r\n\r\n/******************  Bit definition for BDMA_CNDTR register  *******************/\r\n#define BDMA_CNDTR_NDT_Pos      (0U)\r\n#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */\r\n#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */\r\n\r\n/******************  Bit definition for BDMA_CPAR register  ********************/\r\n#define BDMA_CPAR_PA_Pos        (0U)\r\n#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */\r\n#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */\r\n\r\n/******************  Bit definition for BDMA_CM0AR register  ********************/\r\n#define BDMA_CM0AR_MA_Pos        (0U)\r\n#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */\r\n#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */\r\n\r\n/******************  Bit definition for BDMA_CM1AR register  ********************/\r\n#define BDMA_CM1AR_MA_Pos        (0U)\r\n#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */\r\n#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Ethernet MAC Registers bits definitions                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/* Bit definition for Ethernet MAC Configuration Register register */\r\n#define ETH_MACCR_ARP_Pos                             (31U)\r\n#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */\r\n#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */\r\n#define ETH_MACCR_SARC_Pos                            (28U)\r\n#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */\r\n#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */\r\n#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */\r\n#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)\r\n#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */\r\n#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)\r\n#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */\r\n#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)\r\n#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */\r\n#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)\r\n#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */\r\n#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_IPC_Pos                             (27U)\r\n#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */\r\n#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */\r\n#define ETH_MACCR_IPG_Pos                             (24U)\r\n#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */\r\n#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */\r\n#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */\r\n#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */\r\n#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */\r\n#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */\r\n#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */\r\n#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */\r\n#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */\r\n#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */\r\n#define ETH_MACCR_GPSLCE_Pos                          (23U)\r\n#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */\r\n#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */\r\n#define ETH_MACCR_S2KP_Pos                            (22U)\r\n#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */\r\n#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */\r\n#define ETH_MACCR_CST_Pos                             (21U)\r\n#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */\r\n#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */\r\n#define ETH_MACCR_ACS_Pos                             (20U)\r\n#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */\r\n#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */\r\n#define ETH_MACCR_WD_Pos                              (19U)\r\n#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */\r\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\r\n#define ETH_MACCR_JD_Pos                              (17U)\r\n#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */\r\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\r\n#define ETH_MACCR_JE_Pos                              (16U)\r\n#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */\r\n#define ETH_MACCR_FES_Pos                             (14U)\r\n#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\r\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\r\n#define ETH_MACCR_DM_Pos                              (13U)\r\n#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */\r\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\r\n#define ETH_MACCR_LM_Pos                              (12U)\r\n#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\r\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\r\n#define ETH_MACCR_ECRSFD_Pos                          (11U)\r\n#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */\r\n#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */\r\n#define ETH_MACCR_DO_Pos                              (10U)\r\n#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */\r\n#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */\r\n#define ETH_MACCR_DCRS_Pos                            (9U)\r\n#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */\r\n#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */\r\n#define ETH_MACCR_DR_Pos                              (8U)\r\n#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */\r\n#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */\r\n#define ETH_MACCR_BL_Pos                              (5U)\r\n#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */\r\n#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */\r\n#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */\r\n#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */\r\n#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r\n#define ETH_MACCR_DC_Pos                              (4U)\r\n#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\r\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\r\n#define ETH_MACCR_PRELEN_Pos                          (2U)\r\n#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */\r\n#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */\r\n#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */\r\n#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */\r\n#define ETH_MACCR_TE_Pos                              (1U)\r\n#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */\r\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\r\n#define ETH_MACCR_RE_Pos                              (0U)\r\n#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */\r\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\r\n\r\n/* Bit definition for Ethernet MAC Extended Configuration Register register */\r\n#define ETH_MACECR_EIPG_Pos                           (25U)\r\n#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */\r\n#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */\r\n#define ETH_MACECR_EIPGEN_Pos                         (24U)\r\n#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */\r\n#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */\r\n#define ETH_MACECR_USP_Pos                            (18U)\r\n#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */\r\n#define ETH_MACECR_SPEN_Pos                           (17U)\r\n#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */\r\n#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */\r\n#define ETH_MACECR_DCRCC_Pos                          (16U)\r\n#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */\r\n#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */\r\n#define ETH_MACECR_GPSL_Pos                           (0U)\r\n#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */\r\n#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */\r\n\r\n/* Bit definition for Ethernet MAC Packet Filter Register */\r\n#define ETH_MACPFR_RA_Pos                             (31U)\r\n#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */\r\n#define ETH_MACPFR_DNTU_Pos                           (21U)\r\n#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */\r\n#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */\r\n#define ETH_MACPFR_IPFE_Pos                           (20U)\r\n#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */\r\n#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */\r\n#define ETH_MACPFR_VTFE_Pos                           (16U)\r\n#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */\r\n#define ETH_MACPFR_HPF_Pos                            (10U)\r\n#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */\r\n#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */\r\n#define ETH_MACPFR_SAF_Pos                            (9U)\r\n#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */\r\n#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */\r\n#define ETH_MACPFR_SAIF_Pos                           (8U)\r\n#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */\r\n#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */\r\n#define ETH_MACPFR_PCF_Pos                            (6U)\r\n#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */\r\n#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */\r\n#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */\r\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)\r\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */\r\n#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)\r\n#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */\r\n#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\r\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)\r\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */\r\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */\r\n#define ETH_MACPFR_DBF_Pos                            (5U)\r\n#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */\r\n#define ETH_MACPFR_PM_Pos                             (4U)\r\n#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */\r\n#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */\r\n#define ETH_MACPFR_DAIF_Pos                           (3U)\r\n#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */\r\n#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */\r\n#define ETH_MACPFR_HMC_Pos                            (2U)\r\n#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */\r\n#define ETH_MACPFR_HUC_Pos                            (1U)\r\n#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */\r\n#define ETH_MACPFR_PR_Pos                             (0U)\r\n#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */\r\n\r\n/* Bit definition for Ethernet MAC Watchdog Timeout Register */\r\n#define ETH_MACWTR_PWE_Pos                            (8U)\r\n#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */\r\n#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */\r\n#define ETH_MACWTR_WTO_Pos                            (0U)\r\n#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */\r\n#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */\r\n#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/\r\n#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */\r\n#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */\r\n#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */\r\n#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */\r\n#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */\r\n#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */\r\n#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */\r\n#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */\r\n#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */\r\n#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */\r\n#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */\r\n#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */\r\n#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */\r\n#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table High Register */\r\n#define ETH_MACHTHR_HTH_Pos                           (0U)\r\n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table Low Register */\r\n#define ETH_MACHTLR_HTL_Pos                           (0U)\r\n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Tag Register */\r\n#define ETH_MACVTR_EIVLRXS_Pos                        (31U)\r\n#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */\r\n#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */\r\n#define ETH_MACVTR_EIVLS_Pos                          (28U)\r\n#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */\r\n#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */\r\n#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */\r\n#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)\r\n#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */\r\n#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\r\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)\r\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */\r\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\r\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)\r\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */\r\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */\r\n#define ETH_MACVTR_ERIVLT_Pos                         (27U)\r\n#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */\r\n#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */\r\n#define ETH_MACVTR_EDVLP_Pos                          (26U)\r\n#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */\r\n#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */\r\n#define ETH_MACVTR_VTHM_Pos                           (25U)\r\n#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */\r\n#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */\r\n#define ETH_MACVTR_EVLRXS_Pos                         (24U)\r\n#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */\r\n#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */\r\n#define ETH_MACVTR_EVLS_Pos                           (21U)\r\n#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */\r\n#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */\r\n#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */\r\n#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)\r\n#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */\r\n#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\r\n#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)\r\n#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */\r\n#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\r\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)\r\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */\r\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */\r\n#define ETH_MACVTR_DOVLTC_Pos                         (20U)\r\n#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */\r\n#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */\r\n#define ETH_MACVTR_ERSVLM_Pos                         (19U)\r\n#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */\r\n#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */\r\n#define ETH_MACVTR_ESVL_Pos                           (18U)\r\n#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */\r\n#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */\r\n#define ETH_MACVTR_VTIM_Pos                           (17U)\r\n#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */\r\n#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */\r\n#define ETH_MACVTR_ETV_Pos                            (16U)\r\n#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */\r\n#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */\r\n#define ETH_MACVTR_VL_Pos                             (0U)\r\n#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */\r\n#define ETH_MACVTR_VL_UP_Pos                          (13U)\r\n#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */\r\n#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)\r\n#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */\r\n#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r\n#define ETH_MACVTR_VL_VID_Pos                         (0U)\r\n#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */\r\n#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Hash Table Register */\r\n#define ETH_MACVHTR_VLHT_Pos                          (0U)\r\n#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Incl Register */\r\n#define ETH_MACVIR_VLTI_Pos                           (20U)\r\n#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */\r\n#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */\r\n#define ETH_MACVIR_CSVL_Pos                           (19U)\r\n#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */\r\n#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */\r\n#define ETH_MACVIR_VLP_Pos                            (18U)\r\n#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */\r\n#define ETH_MACVIR_VLC_Pos                            (16U)\r\n#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */\r\n#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */\r\n#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */\r\n#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)\r\n#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\r\n#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)\r\n#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\r\n#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\r\n#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)\r\n#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\r\n#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\r\n#define ETH_MACVIR_VLT_Pos                            (0U)\r\n#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */\r\n#define ETH_MACVIR_VLT_UP_Pos                         (13U)\r\n#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */\r\n#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)\r\n#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\r\n#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r\n#define ETH_MACVIR_VLT_VID_Pos                        (0U)\r\n#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */\r\n#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */\r\n\r\n/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */\r\n#define ETH_MACIVIR_VLTI_Pos                          (20U)\r\n#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */\r\n#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */\r\n#define ETH_MACIVIR_CSVL_Pos                          (19U)\r\n#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */\r\n#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */\r\n#define ETH_MACIVIR_VLP_Pos                           (18U)\r\n#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */\r\n#define ETH_MACIVIR_VLC_Pos                           (16U)\r\n#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */\r\n#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */\r\n#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */\r\n#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)\r\n#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\r\n#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)\r\n#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\r\n#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\r\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)\r\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\r\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\r\n#define ETH_MACIVIR_VLT_Pos                           (0U)\r\n#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */\r\n#define ETH_MACIVIR_VLT_UP_Pos                        (13U)\r\n#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */\r\n#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)\r\n#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\r\n#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r\n#define ETH_MACIVIR_VLT_VID_Pos                       (0U)\r\n#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */\r\n#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */\r\n\r\n/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */\r\n#define ETH_MACTFCR_PT_Pos                            (16U)\r\n#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */\r\n#define ETH_MACTFCR_DZPQ_Pos                          (7U)\r\n#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */\r\n#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */\r\n#define ETH_MACTFCR_PLT_Pos                           (4U)\r\n#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */\r\n#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */\r\n#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)\r\n#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */\r\n#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)\r\n#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */\r\n#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)\r\n#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */\r\n#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)\r\n#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */\r\n#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)\r\n#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */\r\n#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */\r\n#define ETH_MACTFCR_TFE_Pos                           (1U)\r\n#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */\r\n#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */\r\n#define ETH_MACTFCR_FCB_Pos                           (0U)\r\n#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */\r\n#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */\r\n\r\n/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */\r\n#define ETH_MACRFCR_UP_Pos                            (1U)\r\n#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */\r\n#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */\r\n#define ETH_MACRFCR_RFE_Pos                           (0U)\r\n#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */\r\n#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */\r\n\r\n/* Bit definition for Ethernet MAC Interrupt Status Register */\r\n#define ETH_MACISR_RXSTSIS_Pos                        (14U)\r\n#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */\r\n#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */\r\n#define ETH_MACISR_TXSTSIS_Pos                        (13U)\r\n#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */\r\n#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */\r\n#define ETH_MACISR_TSIS_Pos                           (12U)\r\n#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */\r\n#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */\r\n#define ETH_MACISR_MMCTXIS_Pos                        (10U)\r\n#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */\r\n#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */\r\n#define ETH_MACISR_MMCRXIS_Pos                        (9U)\r\n#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */\r\n#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */\r\n#define ETH_MACISR_MMCIS_Pos                          (8U)\r\n#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */\r\n#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */\r\n#define ETH_MACISR_LPIIS_Pos                          (5U)\r\n#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */\r\n#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */\r\n#define ETH_MACISR_PMTIS_Pos                          (4U)\r\n#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */\r\n#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */\r\n#define ETH_MACISR_PHYIS_Pos                          (3U)\r\n#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */\r\n#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */\r\n\r\n/* Bit definition for Ethernet MAC Interrupt Enable Register */\r\n#define ETH_MACIER_RXSTSIE_Pos                        (14U)\r\n#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */\r\n#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */\r\n#define ETH_MACIER_TXSTSIE_Pos                        (13U)\r\n#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */\r\n#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */\r\n#define ETH_MACIER_TSIE_Pos                           (12U)\r\n#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */\r\n#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */\r\n#define ETH_MACIER_LPIIE_Pos                          (5U)\r\n#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */\r\n#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */\r\n#define ETH_MACIER_PMTIE_Pos                          (4U)\r\n#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */\r\n#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */\r\n#define ETH_MACIER_PHYIE_Pos                          (3U)\r\n#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */\r\n#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */\r\n\r\n/* Bit definition for Ethernet MAC Rx Tx Status Register */\r\n#define ETH_MACRXTXSR_RWT_Pos                         (8U)\r\n#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */\r\n#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */\r\n#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)\r\n#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */\r\n#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */\r\n#define ETH_MACRXTXSR_LCOL_Pos                        (4U)\r\n#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */\r\n#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */\r\n#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)\r\n#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */\r\n#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */\r\n#define ETH_MACRXTXSR_LCARR_Pos                       (2U)\r\n#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */\r\n#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */\r\n#define ETH_MACRXTXSR_NCARR_Pos                       (1U)\r\n#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */\r\n#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */\r\n#define ETH_MACRXTXSR_TJT_Pos                         (0U)\r\n#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */\r\n#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */\r\n\r\n/* Bit definition for Ethernet MAC PMT Control Status Register */\r\n#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)\r\n#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */\r\n#define ETH_MACPCSR_RWKPTR_Pos                        (24U)\r\n#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */\r\n#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */\r\n#define ETH_MACPCSR_RWKPFE_Pos                        (10U)\r\n#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */\r\n#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */\r\n#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)\r\n#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */\r\n#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */\r\n#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)\r\n#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */\r\n#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)\r\n#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */\r\n#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)\r\n#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */\r\n#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)\r\n#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */\r\n#define ETH_MACPCSR_PWRDWN_Pos                        (0U)\r\n#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */\r\n\r\n/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */\r\n#define ETH_MACRWUPFR_D_Pos                           (0U)\r\n#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */\r\n\r\n/* Bit definition for Ethernet MAC LPI Control Status Register */\r\n#define ETH_MACLCSR_LPITCSE_Pos                       (21U)\r\n#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */\r\n#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */\r\n#define ETH_MACLCSR_LPITE_Pos                         (20U)\r\n#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */\r\n#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */\r\n#define ETH_MACLCSR_LPITXA_Pos                        (19U)\r\n#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */\r\n#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */\r\n#define ETH_MACLCSR_PLS_Pos                           (17U)\r\n#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */\r\n#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */\r\n#define ETH_MACLCSR_LPIEN_Pos                         (16U)\r\n#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */\r\n#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */\r\n#define ETH_MACLCSR_RLPIST_Pos                        (9U)\r\n#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */\r\n#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */\r\n#define ETH_MACLCSR_TLPIST_Pos                        (8U)\r\n#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */\r\n#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */\r\n#define ETH_MACLCSR_RLPIEX_Pos                        (3U)\r\n#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */\r\n#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */\r\n#define ETH_MACLCSR_RLPIEN_Pos                        (2U)\r\n#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */\r\n#define ETH_MACLCSR_TLPIEX_Pos                        (1U)\r\n#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */\r\n#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */\r\n#define ETH_MACLCSR_TLPIEN_Pos                        (0U)\r\n#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */\r\n\r\n/* Bit definition for Ethernet MAC LPI Timers Control Register */\r\n#define ETH_MACLTCR_LST_Pos                           (16U)\r\n#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */\r\n#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */\r\n#define ETH_MACLTCR_TWT_Pos                           (0U)\r\n#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */\r\n\r\n/* Bit definition for Ethernet MAC LPI Entry Timer Register */\r\n#define ETH_MACLETR_LPIET_Pos                         (0U)\r\n#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */\r\n#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */\r\n\r\n/* Bit definition for Ethernet MAC 1US Tic Counter Register */\r\n#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)\r\n#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */\r\n#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */\r\n\r\n/* Bit definition for Ethernet MAC Version Register */\r\n#define ETH_MACVR_USERVER_Pos                         (8U)\r\n#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */\r\n#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */\r\n#define ETH_MACVR_SNPSVER_Pos                         (0U)\r\n#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */\r\n#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */\r\n\r\n/* Bit definition for Ethernet MAC Debug Register */\r\n#define ETH_MACDR_TFCSTS_Pos                          (17U)\r\n#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */\r\n#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */\r\n#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */\r\n#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)\r\n#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */\r\n#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */\r\n#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)\r\n#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */\r\n#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)\r\n#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */\r\n#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */\r\n#define ETH_MACDR_TPESTS_Pos                          (16U)\r\n#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */\r\n#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */\r\n#define ETH_MACDR_RFCFCSTS_Pos                        (1U)\r\n#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */\r\n#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */\r\n#define ETH_MACDR_RPESTS_Pos                          (0U)\r\n#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */\r\n#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */\r\n\r\n/* Bit definition for Ethernet MAC HW Feature0 Register */\r\n#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)\r\n#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */\r\n#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */\r\n#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */\r\n#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)\r\n#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */\r\n#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */\r\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)\r\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */\r\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */\r\n#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)\r\n#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */\r\n#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */\r\n#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)\r\n#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */\r\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)\r\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */\r\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)\r\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */\r\n#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)\r\n#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */\r\n#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)\r\n#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */\r\n#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */\r\n#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)\r\n#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */\r\n#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */\r\n#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)\r\n#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */\r\n#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */\r\n#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)\r\n#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */\r\n#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */\r\n#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)\r\n#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */\r\n#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */\r\n#define ETH_MACHWF0R_EEESEL_Pos                       (13U)\r\n#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */\r\n#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */\r\n#define ETH_MACHWF0R_TSSEL_Pos                        (12U)\r\n#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */\r\n#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */\r\n#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)\r\n#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */\r\n#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */\r\n#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)\r\n#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */\r\n#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */\r\n#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)\r\n#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */\r\n#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */\r\n#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)\r\n#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */\r\n#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */\r\n#define ETH_MACHWF0R_SMASEL_Pos                       (5U)\r\n#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */\r\n#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */\r\n#define ETH_MACHWF0R_VLHASH_Pos                       (4U)\r\n#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */\r\n#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */\r\n#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)\r\n#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */\r\n#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */\r\n#define ETH_MACHWF0R_HDSEL_Pos                        (2U)\r\n#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */\r\n#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */\r\n#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)\r\n#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */\r\n#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */\r\n#define ETH_MACHWF0R_MIISEL_Pos                       (0U)\r\n#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */\r\n#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */\r\n\r\n/* Bit definition for Ethernet MAC HW Feature1 Register */\r\n#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)\r\n#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */\r\n#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */\r\n#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)\r\n#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */\r\n#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */\r\n#define ETH_MACHWF1R_AVSEL_Pos                        (20U)\r\n#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */\r\n#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */\r\n#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)\r\n#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */\r\n#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */\r\n#define ETH_MACHWF1R_TSOEN_Pos                        (18U)\r\n#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */\r\n#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */\r\n#define ETH_MACHWF1R_SPHEN_Pos                        (17U)\r\n#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */\r\n#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */\r\n#define ETH_MACHWF1R_DCBEN_Pos                        (16U)\r\n#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */\r\n#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */\r\n#define ETH_MACHWF1R_ADDR64_Pos                       (14U)\r\n#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */\r\n#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */\r\n#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */\r\n#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */\r\n#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */\r\n#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)\r\n#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */\r\n#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */\r\n#define ETH_MACHWF1R_PTOEN_Pos                        (12U)\r\n#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */\r\n#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */\r\n#define ETH_MACHWF1R_OSTEN_Pos                        (11U)\r\n#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */\r\n#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */\r\n#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)\r\n#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */\r\n#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */\r\n#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)\r\n#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */\r\n#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */\r\n\r\n/* Bit definition for Ethernet MAC HW Feature2 Register */\r\n#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)\r\n#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */\r\n#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */\r\n#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)\r\n#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */\r\n#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */\r\n#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)\r\n#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */\r\n#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */\r\n#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)\r\n#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */\r\n#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)\r\n#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */\r\n#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */\r\n#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)\r\n#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */\r\n#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */\r\n\r\n/* Bit definition for Ethernet MAC MDIO Address Register */\r\n#define ETH_MACMDIOAR_PSE_Pos                         (27U)\r\n#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */\r\n#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */\r\n#define ETH_MACMDIOAR_BTB_Pos                         (26U)\r\n#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */\r\n#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */\r\n#define ETH_MACMDIOAR_PA_Pos                          (21U)\r\n#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */\r\n#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */\r\n#define ETH_MACMDIOAR_RDA_Pos                         (16U)\r\n#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */\r\n#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */\r\n#define ETH_MACMDIOAR_NTC_Pos                         (12U)\r\n#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */\r\n#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */\r\n#define ETH_MACMDIOAR_CR_Pos                          (8U)\r\n#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */\r\n#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */\r\n#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */\r\n#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)\r\n#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */\r\n#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */\r\n#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)\r\n#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */\r\n#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */\r\n#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)\r\n#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */\r\n#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */\r\n#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)\r\n#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */\r\n#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */\r\n#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)\r\n#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */\r\n#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */\r\n#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)\r\n#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */\r\n#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)\r\n#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */\r\n#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)\r\n#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */\r\n#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)\r\n#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */\r\n#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)\r\n#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */\r\n#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)\r\n#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */\r\n#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)\r\n#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */\r\n#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)\r\n#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */\r\n#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_SKAP_Pos                        (4U)\r\n#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */\r\n#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */\r\n#define ETH_MACMDIOAR_MOC_Pos                         (2U)\r\n#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */\r\n#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */\r\n#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)\r\n#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */\r\n#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */\r\n#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)\r\n#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */\r\n#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */\r\n#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)\r\n#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */\r\n#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */\r\n#define ETH_MACMDIOAR_C45E_Pos                        (1U)\r\n#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */\r\n#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */\r\n#define ETH_MACMDIOAR_MB_Pos                          (0U)\r\n#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */\r\n#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */\r\n\r\n/* Bit definition for Ethernet MAC MDIO Data Register */\r\n#define ETH_MACMDIODR_RA_Pos                          (16U)\r\n#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */\r\n#define ETH_MACMDIODR_MD_Pos                          (0U)\r\n#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */\r\n\r\n/* Bit definition for Ethernet ARP Address Register */\r\n#define ETH_MACARPAR_ARPPA_Pos                         (0U)\r\n#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */\r\n\r\n/* Bit definition for Ethernet MAC Address 0 High Register */\r\n#define ETH_MACA0HR_AE_Pos                            (31U)\r\n#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA0HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/\r\n\r\n/* Bit definition for Ethernet MAC Address 0 Low Register */\r\n#define ETH_MACA0LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/\r\n\r\n/* Bit definition for Ethernet MAC Address 1 High Register */\r\n#define ETH_MACA1HR_AE_Pos                            (31U)\r\n#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA1HR_SA_Pos                            (30U)\r\n#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */\r\n#define ETH_MACA1HR_MBC_Pos                           (24U)\r\n#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */\r\n#define ETH_MACA1HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 1 Low Register */\r\n#define ETH_MACA1LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 2 High Register */\r\n#define ETH_MACA2HR_AE_Pos                            (31U)\r\n#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA2HR_SA_Pos                            (30U)\r\n#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */\r\n#define ETH_MACA2HR_MBC_Pos                           (24U)\r\n#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */\r\n#define ETH_MACA2HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 2 Low Register */\r\n#define ETH_MACA2LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/\r\n\r\n/* Bit definition for Ethernet MAC Address 3 High Register */\r\n#define ETH_MACA3HR_AE_Pos                            (31U)\r\n#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA3HR_SA_Pos                            (30U)\r\n#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */\r\n#define ETH_MACA3HR_MBC_Pos                           (24U)\r\n#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */\r\n#define ETH_MACA3HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 3 Low Register */\r\n#define ETH_MACA3LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/\r\n\r\n/* Bit definition for Ethernet MAC Address High Register */\r\n#define ETH_MACAHR_AE_Pos                             (31U)\r\n#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */\r\n#define ETH_MACAHR_SA_Pos                             (30U)\r\n#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */\r\n#define ETH_MACAHR_MBC_Pos                            (24U)\r\n#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r\n#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */\r\n#define ETH_MACAHR_MACAH_Pos                          (0U)\r\n#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */\r\n\r\n/* Bit definition for Ethernet MAC Address Low Register */\r\n#define ETH_MACALR_MACAL_Pos                          (0U)\r\n#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */\r\n\r\n/* Bit definition for Ethernet MMC Control Register */\r\n#define ETH_MMCCR_UCDBC_Pos                           (8U)\r\n#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */\r\n#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */\r\n#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)\r\n#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */\r\n#define ETH_MMCCR_CNTPRST_Pos                         (4U)\r\n#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */\r\n#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */\r\n#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)\r\n#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */\r\n#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */\r\n#define ETH_MMCCR_RSTONRD_Pos                         (2U)\r\n#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */\r\n#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */\r\n#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)\r\n#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */\r\n#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */\r\n#define ETH_MMCCR_CNTRST_Pos                          (0U)\r\n#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */\r\n#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */\r\n\r\n/* Bit definition for Ethernet MMC Rx Interrupt Register */\r\n#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)\r\n#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */\r\n#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)\r\n#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */\r\n#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)\r\n#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */\r\n#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */\r\n#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)\r\n#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */\r\n#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */\r\n#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)\r\n#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */\r\n\r\n/* Bit definition for Ethernet MMC Tx Interrupt Register */\r\n#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)\r\n#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */\r\n#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)\r\n#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */\r\n#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)\r\n#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */\r\n#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */\r\n#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)\r\n#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */\r\n#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */\r\n#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)\r\n#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */\r\n#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */\r\n\r\n/* Bit definition for Ethernet MMC Rx interrupt Mask register */\r\n#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)\r\n#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */\r\n#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)\r\n#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */\r\n#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)\r\n#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */\r\n#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */\r\n#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)\r\n#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */\r\n#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */\r\n#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)\r\n#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */\r\n\r\n/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */\r\n#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)\r\n#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/\r\n#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)\r\n#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/\r\n#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)\r\n#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */\r\n#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/\r\n#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)\r\n#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */\r\n#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */\r\n#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)\r\n#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */\r\n#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */\r\n\r\n/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */\r\n#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)\r\n#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */\r\n\r\n/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */\r\n#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)\r\n#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */\r\n\r\n/* Bit definition for Ethernet MMC Tx Packet Count Good Register */\r\n#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)\r\n#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */\r\n\r\n/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */\r\n#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)\r\n#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */\r\n\r\n/* Bit definition for Ethernet MMC Rx alignment error packets register */\r\n#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)\r\n#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */\r\n\r\n/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */\r\n#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)\r\n#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */\r\n\r\n/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */\r\n#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)\r\n#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */\r\n\r\n/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */\r\n#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)\r\n#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */\r\n\r\n/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */\r\n#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)\r\n#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */\r\n\r\n/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */\r\n#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)\r\n#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */\r\n\r\n/* Bit definition for Ethernet MAC L3 L4 Control Register */\r\n#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)\r\n#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */\r\n#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)\r\n#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */\r\n#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */\r\n#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)\r\n#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */\r\n#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)\r\n#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */\r\n#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */\r\n#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)\r\n#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */\r\n#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */\r\n#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)\r\n#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */\r\n#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */\r\n#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)\r\n#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */\r\n#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */\r\n#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)\r\n#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */\r\n#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)\r\n#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */\r\n#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */\r\n#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)\r\n#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */\r\n#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)\r\n#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */\r\n#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/\r\n#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)\r\n#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address Register */\r\n#define ETH_MACL4AR_L4DP_Pos                          (16U)\r\n#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */\r\n#define ETH_MACL4AR_L4SP_Pos                          (0U)\r\n#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */\r\n\r\n/* Bit definition for Ethernet MAC L3 Address0 Register */\r\n#define ETH_MACL3A0R_L3A0_Pos                         (0U)\r\n#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address1 Register */\r\n#define ETH_MACL3A1R_L3A1_Pos                         (0U)\r\n#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address2 Register */\r\n#define ETH_MACL3A2R_L3A2_Pos                         (0U)\r\n#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address3 Register */\r\n#define ETH_MACL3A3R_L3A3_Pos                         (0U)\r\n#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Control Register */\r\n#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)\r\n#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */\r\n#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */\r\n#define ETH_MACTSCR_CSC_Pos                           (19U)\r\n#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */\r\n#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */\r\n#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)\r\n#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */\r\n#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */\r\n#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)\r\n#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */\r\n#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */\r\n#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)\r\n#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */\r\n#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */\r\n#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)\r\n#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */\r\n#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */\r\n#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)\r\n#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */\r\n#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */\r\n#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)\r\n#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */\r\n#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */\r\n#define ETH_MACTSCR_TSIPENA_Pos                       (11U)\r\n#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */\r\n#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */\r\n#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)\r\n#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */\r\n#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */\r\n#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)\r\n#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */\r\n#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */\r\n#define ETH_MACTSCR_TSENALL_Pos                       (8U)\r\n#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */\r\n#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */\r\n#define ETH_MACTSCR_TSADDREG_Pos                      (5U)\r\n#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */\r\n#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */\r\n#define ETH_MACTSCR_TSUPDT_Pos                        (3U)\r\n#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */\r\n#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */\r\n#define ETH_MACTSCR_TSINIT_Pos                        (2U)\r\n#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */\r\n#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */\r\n#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)\r\n#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */\r\n#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/\r\n#define ETH_MACTSCR_TSENA_Pos                         (0U)\r\n#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */\r\n#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */\r\n\r\n/* Bit definition for Ethernet MAC Sub-second Increment Register */\r\n#define ETH_MACMACSSIR_SSINC_Pos                      (16U)\r\n#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */\r\n#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */\r\n#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)\r\n#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */\r\n#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */\r\n\r\n/* Bit definition for Ethernet MAC System Time Seconds Register */\r\n#define ETH_MACSTSR_TSS_Pos                           (0U)\r\n#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */\r\n\r\n/* Bit definition for Ethernet MAC System Time Nanoseconds Register */\r\n#define ETH_MACSTNR_TSSS_Pos                          (0U)\r\n#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */\r\n\r\n/* Bit definition for Ethernet MAC System Time Seconds Update Register */\r\n#define ETH_MACSTSUR_TSS_Pos                          (0U)\r\n#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */\r\n\r\n/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */\r\n#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)\r\n#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */\r\n#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */\r\n#define ETH_MACSTNUR_TSSS_Pos                         (0U)\r\n#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Addend Register */\r\n#define ETH_MACTSAR_TSAR_Pos                          (0U)\r\n#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Status Register */\r\n#define ETH_MACTSSR_ATSNS_Pos                         (25U)\r\n#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */\r\n#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */\r\n#define ETH_MACTSSR_ATSSTM_Pos                        (24U)\r\n#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */\r\n#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */\r\n#define ETH_MACTSSR_ATSSTN_Pos                        (16U)\r\n#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */\r\n#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */\r\n#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)\r\n#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */\r\n#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */\r\n#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)\r\n#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */\r\n#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */\r\n#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)\r\n#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */\r\n#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/\r\n#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)\r\n#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */\r\n#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */\r\n#define ETH_MACTSSR_TSSOVF_Pos                        (0U)\r\n#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */\r\n#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */\r\n\r\n/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */\r\n#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)\r\n#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */\r\n#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */\r\n#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)\r\n#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */\r\n\r\n/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */\r\n#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)\r\n#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */\r\n\r\n/* Bit definition for Ethernet MAC Auxiliary Control Register*/\r\n#define ETH_MACACR_ATSEN3_Pos                         (7U)\r\n#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */\r\n#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */\r\n#define ETH_MACACR_ATSEN2_Pos                         (6U)\r\n#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */\r\n#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */\r\n#define ETH_MACACR_ATSEN1_Pos                         (5U)\r\n#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */\r\n#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */\r\n#define ETH_MACACR_ATSEN0_Pos                         (4U)\r\n#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */\r\n#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */\r\n#define ETH_MACACR_ATSFC_Pos                          (0U)\r\n#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */\r\n#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */\r\n\r\n/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */\r\n#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)\r\n#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */\r\n\r\n/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */\r\n#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)\r\n#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */\r\n#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)\r\n#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */\r\n#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)\r\n#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */\r\n#define ETH_MACTSICNR_TSIC_Pos                        (0U)\r\n#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */\r\n#define ETH_MACTSECNR_TSEC_Pos                        (0U)\r\n#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */\r\n\r\n/* Bit definition for Ethernet MAC PPS Control Register */\r\n#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)\r\n#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */\r\n#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */\r\n#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)\r\n#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */\r\n#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */\r\n#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)\r\n#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */\r\n#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */\r\n\r\n/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */\r\n#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)\r\n#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */\r\n\r\n/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */\r\n#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)\r\n#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */\r\n#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)\r\n#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */\r\n\r\n/* Bit definition for Ethernet MAC PPS Interval Register */\r\n#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)\r\n#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */\r\n\r\n/* Bit definition for Ethernet MAC PPS Width Register */\r\n#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)\r\n#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */\r\n\r\n/* Bit definition for Ethernet MAC PTP Offload Control Register */\r\n#define ETH_MACPOCR_DN_Pos                            (8U)\r\n#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */\r\n#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */\r\n#define ETH_MACPOCR_DRRDIS_Pos                        (6U)\r\n#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */\r\n#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)\r\n#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */\r\n#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)\r\n#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */\r\n#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */\r\n#define ETH_MACPOCR_APDREQEN_Pos                      (2U)\r\n#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */\r\n#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)\r\n#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */\r\n#define ETH_MACPOCR_PTOEN_Pos                         (0U)\r\n#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */\r\n\r\n/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */\r\n#define ETH_MACSPI0R_SPI0_Pos                         (0U)\r\n#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */\r\n\r\n/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */\r\n#define ETH_MACSPI1R_SPI1_Pos                         (0U)\r\n#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */\r\n\r\n/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */\r\n#define ETH_MACSPI2R_SPI2_Pos                         (0U)\r\n#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */\r\n\r\n/* Bit definition for Ethernet MAC Log Message Interval Register */\r\n#define ETH_MACLMIR_LMPDRI_Pos                        (24U)\r\n#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */\r\n#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */\r\n#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)\r\n#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */\r\n#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */\r\n#define ETH_MACLMIR_LSI_Pos                           (0U)\r\n#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */\r\n#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */\r\n\r\n/* Bit definition for Ethernet MTL Operation Mode Register */\r\n#define ETH_MTLOMR_CNTCLR_Pos                         (9U)\r\n#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */\r\n#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */\r\n#define ETH_MTLOMR_CNTPRST_Pos                        (8U)\r\n#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */\r\n#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */\r\n#define ETH_MTLOMR_DTXSTS_Pos                         (1U)\r\n#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */\r\n#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */\r\n\r\n/* Bit definition for Ethernet MTL Interrupt Status Register */\r\n#define ETH_MTLISR_MACIS_Pos                          (16U)\r\n#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */\r\n#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */\r\n#define ETH_MTLISR_QIS_Pos                            (0U)\r\n#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */\r\n\r\n/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */\r\n#define ETH_MTLTQOMR_TTC_Pos                          (4U)\r\n#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */\r\n#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */\r\n#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */\r\n#define ETH_MTLTQOMR_TSF_Pos                          (1U)\r\n#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */\r\n#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */\r\n#define ETH_MTLTQOMR_FTQ_Pos                          (0U)\r\n#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */\r\n\r\n/* Bit definition for Ethernet MTL Tx Queue Underflow Register */\r\n#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)\r\n#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */\r\n#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */\r\n#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)\r\n#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */\r\n#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */\r\n\r\n/* Bit definition for Ethernet MTL Tx Queue Debug Register */\r\n#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)\r\n#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */\r\n#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */\r\n#define ETH_MTLTQDR_PTXQ_Pos                          (16U)\r\n#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */\r\n#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */\r\n#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)\r\n#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */\r\n#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */\r\n#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)\r\n#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */\r\n#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */\r\n#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)\r\n#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */\r\n#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */\r\n#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)\r\n#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */\r\n#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */\r\n#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */\r\n#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */\r\n#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */\r\n#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */\r\n#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)\r\n#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */\r\n\r\n/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */\r\n#define ETH_MTLQICSR_RXOIE_Pos                        (24U)\r\n#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */\r\n#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */\r\n#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)\r\n#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */\r\n#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */\r\n#define ETH_MTLQICSR_TXUIE_Pos                        (8U)\r\n#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */\r\n#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */\r\n#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)\r\n#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */\r\n#define ETH_MTLRQOMR_RQS_Pos                          (20U)\r\n#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */\r\n#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */\r\n#define ETH_MTLRQOMR_RFD_Pos                          (14U)\r\n#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */\r\n#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */\r\n#define ETH_MTLRQOMR_RFA_Pos                          (8U)\r\n#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */\r\n#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */\r\n#define ETH_MTLRQOMR_EHFC_Pos                         (7U)\r\n#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */\r\n#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */\r\n#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)\r\n#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */\r\n#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */\r\n#define ETH_MTLRQOMR_RSF_Pos                          (5U)\r\n#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */\r\n#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */\r\n#define ETH_MTLRQOMR_FEP_Pos                          (4U)\r\n#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */\r\n#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */\r\n#define ETH_MTLRQOMR_FUP_Pos                          (3U)\r\n#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */\r\n#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */\r\n#define ETH_MTLRQOMR_RTC_Pos                          (0U)\r\n#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */\r\n#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */\r\n#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */\r\n#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */\r\n#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */\r\n#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */\r\n#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)\r\n#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */\r\n#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */\r\n#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)\r\n#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */\r\n#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */\r\n#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)\r\n#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */\r\n#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */\r\n#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)\r\n#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */\r\n#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Debug Register */\r\n#define ETH_MTLRQDR_PRXQ_Pos                          (16U)\r\n#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */\r\n#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */\r\n#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)\r\n#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */\r\n#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */\r\n#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */\r\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)\r\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */\r\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */\r\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)\r\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */\r\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */\r\n#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)\r\n#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */\r\n#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */\r\n#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)\r\n#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */\r\n#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */\r\n#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */\r\n#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)\r\n#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */\r\n#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */\r\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)\r\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */\r\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */\r\n#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)\r\n#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */\r\n#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */\r\n#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)\r\n#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Control Register */\r\n#define ETH_MTLRQCR_RQPA_Pos                          (3U)\r\n#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */\r\n#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */\r\n#define ETH_MTLRQCR_RQW_Pos                           (0U)\r\n#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */\r\n#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */\r\n\r\n/* Bit definition for Ethernet DMA Mode Register */\r\n#define ETH_DMAMR_INTM_Pos                            (16U)\r\n#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */\r\n#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */\r\n#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */\r\n#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */\r\n#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */\r\n#define ETH_DMAMR_PR_Pos                              (12U)\r\n#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */\r\n#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */\r\n#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */\r\n#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */\r\n#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */\r\n#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */\r\n#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */\r\n#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */\r\n#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */\r\n#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */\r\n#define ETH_DMAMR_TXPR_Pos                            (11U)\r\n#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */\r\n#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */\r\n#define ETH_DMAMR_DA_Pos                              (1U)\r\n#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */\r\n#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */\r\n#define ETH_DMAMR_SWR_Pos                             (0U)\r\n#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */\r\n#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */\r\n\r\n/* Bit definition for Ethernet DMA SysBus Mode Register */\r\n#define ETH_DMASBMR_RB_Pos                            (15U)\r\n#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */\r\n#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */\r\n#define ETH_DMASBMR_MB_Pos                            (14U)\r\n#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */\r\n#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */\r\n#define ETH_DMASBMR_AAL_Pos                           (12U)\r\n#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */\r\n#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */\r\n#define ETH_DMASBMR_FB_Pos                            (0U)\r\n#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */\r\n#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */\r\n\r\n/* Bit definition for Ethernet DMA Interrupt Status Register */\r\n#define ETH_DMAISR_MACIS_Pos                          (17U)\r\n#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */\r\n#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */\r\n#define ETH_DMAISR_MTLIS_Pos                          (16U)\r\n#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */\r\n#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */\r\n#define ETH_DMAISR_DMACIS_Pos                         (0U)\r\n#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */\r\n#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */\r\n\r\n/* Bit definition for Ethernet DMA Debug Status Register */\r\n#define ETH_DMADSR_TPS_Pos                            (12U)\r\n#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */\r\n#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */\r\n#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */\r\n#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)\r\n#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */\r\n#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */\r\n#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)\r\n#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */\r\n#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */\r\n#define ETH_DMADSR_TPS_READING_Pos                    (12U)\r\n#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */\r\n#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */\r\n#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)\r\n#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */\r\n#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */\r\n#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)\r\n#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */\r\n#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */\r\n#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)\r\n#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */\r\n#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */\r\n#define ETH_DMADSR_RPS_Pos                            (8U)\r\n#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */\r\n#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */\r\n#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */\r\n#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)\r\n#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */\r\n#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */\r\n#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)\r\n#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */\r\n#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */\r\n#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)\r\n#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */\r\n#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */\r\n#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)\r\n#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */\r\n#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */\r\n#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)\r\n#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */\r\n#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */\r\n#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)\r\n#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */\r\n#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */\r\n\r\n/* Bit definition for Ethernet DMA Channel Control Register */\r\n#define ETH_DMACCR_DSL_Pos                            (18U)\r\n#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */\r\n#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */\r\n#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)\r\n#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)\r\n#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)\r\n#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)\r\n#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */\r\n#define ETH_DMACCR_MSS_Pos                            (0U)\r\n#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */\r\n#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */\r\n\r\n/* Bit definition for Ethernet DMA Channel Tx Control Register */\r\n#define ETH_DMACTCR_TPBL_Pos                          (16U)\r\n#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */\r\n#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */\r\n#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */\r\n#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */\r\n#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */\r\n#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */\r\n#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */\r\n#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */\r\n#define ETH_DMACTCR_TSE_Pos                           (12U)\r\n#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */\r\n#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */\r\n#define ETH_DMACTCR_OSP_Pos                           (4U)\r\n#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */\r\n#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */\r\n#define ETH_DMACTCR_ST_Pos                            (0U)\r\n#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */\r\n\r\n/* Bit definition for Ethernet DMA Channel Rx Control Register */\r\n#define ETH_DMACRCR_RPF_Pos                           (31U)\r\n#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */\r\n#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */\r\n#define ETH_DMACRCR_RPBL_Pos                          (16U)\r\n#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */\r\n#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */\r\n#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */\r\n#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */\r\n#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */\r\n#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */\r\n#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */\r\n#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */\r\n#define ETH_DMACRCR_RBSZ_Pos                          (1U)\r\n#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */\r\n#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */\r\n#define ETH_DMACRCR_SR_Pos                            (0U)\r\n#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */\r\n\r\n/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */\r\n#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)\r\n#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */\r\n\r\n/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */\r\n#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)\r\n#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */\r\n\r\n/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */\r\n#define ETH_DMACTDTPR_TDT_Pos                         (2U)\r\n#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */\r\n\r\n/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */\r\n#define ETH_DMACRDTPR_RDT_Pos                         (2U)\r\n#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */\r\n\r\n/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */\r\n#define ETH_DMACTDRLR_TDRL_Pos                        (0U)\r\n#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */\r\n#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */\r\n\r\n/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */\r\n#define ETH_DMACRDRLR_RDRL_Pos                        (0U)\r\n#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */\r\n#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */\r\n\r\n/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */\r\n#define ETH_DMACIER_NIE_Pos                           (15U)\r\n#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */\r\n#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */\r\n#define ETH_DMACIER_AIE_Pos                           (14U)\r\n#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */\r\n#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */\r\n#define ETH_DMACIER_CDEE_Pos                          (13U)\r\n#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */\r\n#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */\r\n#define ETH_DMACIER_FBEE_Pos                          (12U)\r\n#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */\r\n#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */\r\n#define ETH_DMACIER_ERIE_Pos                          (11U)\r\n#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */\r\n#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */\r\n#define ETH_DMACIER_ETIE_Pos                          (10U)\r\n#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */\r\n#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */\r\n#define ETH_DMACIER_RWTE_Pos                          (9U)\r\n#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */\r\n#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */\r\n#define ETH_DMACIER_RSE_Pos                           (8U)\r\n#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */\r\n#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */\r\n#define ETH_DMACIER_RBUE_Pos                          (7U)\r\n#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */\r\n#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */\r\n#define ETH_DMACIER_RIE_Pos                           (6U)\r\n#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */\r\n#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */\r\n#define ETH_DMACIER_TBUE_Pos                          (2U)\r\n#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */\r\n#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */\r\n#define ETH_DMACIER_TXSE_Pos                          (1U)\r\n#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */\r\n#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */\r\n#define ETH_DMACIER_TIE_Pos                           (0U)\r\n#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */\r\n\r\n/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */\r\n#define ETH_DMACRIWTR_RWT_Pos                         (0U)\r\n#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */\r\n#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */\r\n#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)\r\n#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */\r\n#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)\r\n#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */\r\n#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)\r\n#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */\r\n#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)\r\n#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Status Register */\r\n#define ETH_DMACSR_REB_Pos                            (19U)\r\n#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */\r\n#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */\r\n#define ETH_DMACSR_TEB_Pos                            (16U)\r\n#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */\r\n#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */\r\n#define ETH_DMACSR_NIS_Pos                            (15U)\r\n#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */\r\n#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */\r\n#define ETH_DMACSR_AIS_Pos                            (14U)\r\n#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */\r\n#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */\r\n#define ETH_DMACSR_CDE_Pos                            (13U)\r\n#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */\r\n#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */\r\n#define ETH_DMACSR_FBE_Pos                            (12U)\r\n#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */\r\n#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */\r\n#define ETH_DMACSR_ERI_Pos                            (11U)\r\n#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */\r\n#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */\r\n#define ETH_DMACSR_ETI_Pos                            (10U)\r\n#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */\r\n#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */\r\n#define ETH_DMACSR_RWT_Pos                            (9U)\r\n#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */\r\n#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */\r\n#define ETH_DMACSR_RPS_Pos                            (8U)\r\n#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */\r\n#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */\r\n#define ETH_DMACSR_RBU_Pos                            (7U)\r\n#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */\r\n#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */\r\n#define ETH_DMACSR_RI_Pos                             (6U)\r\n#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */\r\n#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */\r\n#define ETH_DMACSR_TBU_Pos                            (2U)\r\n#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */\r\n#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */\r\n#define ETH_DMACSR_TPS_Pos                            (1U)\r\n#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */\r\n#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */\r\n#define ETH_DMACSR_TI_Pos                             (0U)\r\n#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */\r\n\r\n/* Bit definition for Ethernet DMA Channel missed frame count register */\r\n#define ETH_DMACMFCR_MFCO_Pos                         (15U)\r\n#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */\r\n#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */\r\n#define ETH_DMACMFCR_MFC_Pos                          (0U)\r\n#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */\r\n#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             DMA Controller                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DMA_SxCR register  *****************/\r\n#define DMA_SxCR_MBURST_Pos      (23U)\r\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */\r\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */\r\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\r\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\r\n#define DMA_SxCR_PBURST_Pos      (21U)\r\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */\r\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */\r\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\r\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\r\n#define DMA_SxCR_TRBUFF_Pos      (20U)\r\n#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */\r\n#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */\r\n#define DMA_SxCR_CT_Pos          (19U)\r\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */\r\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */\r\n#define DMA_SxCR_DBM_Pos         (18U)\r\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */\r\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */\r\n#define DMA_SxCR_PL_Pos          (16U)\r\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */\r\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */\r\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\r\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\r\n#define DMA_SxCR_PINCOS_Pos      (15U)\r\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */\r\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */\r\n#define DMA_SxCR_MSIZE_Pos       (13U)\r\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */\r\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */\r\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\r\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\r\n#define DMA_SxCR_PSIZE_Pos       (11U)\r\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */\r\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */\r\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\r\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\r\n#define DMA_SxCR_MINC_Pos        (10U)\r\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */\r\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */\r\n#define DMA_SxCR_PINC_Pos        (9U)\r\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */\r\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */\r\n#define DMA_SxCR_CIRC_Pos        (8U)\r\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */\r\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */\r\n#define DMA_SxCR_DIR_Pos         (6U)\r\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */\r\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */\r\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\r\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\r\n#define DMA_SxCR_PFCTRL_Pos      (5U)\r\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */\r\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */\r\n#define DMA_SxCR_TCIE_Pos        (4U)\r\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */\r\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */\r\n#define DMA_SxCR_HTIE_Pos        (3U)\r\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */\r\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */\r\n#define DMA_SxCR_TEIE_Pos        (2U)\r\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */\r\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */\r\n#define DMA_SxCR_DMEIE_Pos       (1U)\r\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */\r\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */\r\n#define DMA_SxCR_EN_Pos          (0U)\r\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */\r\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */\r\n\r\n/********************  Bits definition for DMA_SxCNDTR register  **************/\r\n#define DMA_SxNDT_Pos            (0U)\r\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */\r\n#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */\r\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\r\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\r\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\r\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\r\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\r\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\r\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\r\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\r\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\r\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\r\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\r\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\r\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\r\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\r\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\r\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\r\n\r\n/********************  Bits definition for DMA_SxFCR register  ****************/\r\n#define DMA_SxFCR_FEIE_Pos       (7U)\r\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */\r\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */\r\n#define DMA_SxFCR_FS_Pos         (3U)\r\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */\r\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */\r\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\r\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\r\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\r\n#define DMA_SxFCR_DMDIS_Pos      (2U)\r\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */\r\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */\r\n#define DMA_SxFCR_FTH_Pos        (0U)\r\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */\r\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */\r\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\r\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\r\n\r\n/********************  Bits definition for DMA_LISR register  *****************/\r\n#define DMA_LISR_TCIF3_Pos       (27U)\r\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */\r\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF3_Pos       (26U)\r\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */\r\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF3_Pos       (25U)\r\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */\r\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF3_Pos      (24U)\r\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */\r\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF3_Pos       (22U)\r\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */\r\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */\r\n#define DMA_LISR_TCIF2_Pos       (21U)\r\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */\r\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF2_Pos       (20U)\r\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */\r\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF2_Pos       (19U)\r\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */\r\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF2_Pos      (18U)\r\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */\r\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF2_Pos       (16U)\r\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */\r\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */\r\n#define DMA_LISR_TCIF1_Pos       (11U)\r\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */\r\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF1_Pos       (10U)\r\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */\r\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF1_Pos       (9U)\r\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */\r\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF1_Pos      (8U)\r\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */\r\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF1_Pos       (6U)\r\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */\r\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */\r\n#define DMA_LISR_TCIF0_Pos       (5U)\r\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */\r\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF0_Pos       (4U)\r\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */\r\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF0_Pos       (3U)\r\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */\r\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF0_Pos      (2U)\r\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */\r\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF0_Pos       (0U)\r\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */\r\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */\r\n\r\n/********************  Bits definition for DMA_HISR register  *****************/\r\n#define DMA_HISR_TCIF7_Pos       (27U)\r\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */\r\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF7_Pos       (26U)\r\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */\r\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF7_Pos       (25U)\r\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */\r\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF7_Pos      (24U)\r\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */\r\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF7_Pos       (22U)\r\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */\r\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */\r\n#define DMA_HISR_TCIF6_Pos       (21U)\r\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */\r\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF6_Pos       (20U)\r\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */\r\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF6_Pos       (19U)\r\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */\r\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF6_Pos      (18U)\r\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */\r\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF6_Pos       (16U)\r\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */\r\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */\r\n#define DMA_HISR_TCIF5_Pos       (11U)\r\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */\r\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF5_Pos       (10U)\r\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */\r\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF5_Pos       (9U)\r\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */\r\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF5_Pos      (8U)\r\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */\r\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF5_Pos       (6U)\r\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */\r\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */\r\n#define DMA_HISR_TCIF4_Pos       (5U)\r\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */\r\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF4_Pos       (4U)\r\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */\r\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF4_Pos       (3U)\r\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */\r\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF4_Pos      (2U)\r\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */\r\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF4_Pos       (0U)\r\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */\r\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */\r\n\r\n/********************  Bits definition for DMA_LIFCR register  ****************/\r\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\r\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */\r\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\r\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */\r\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\r\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */\r\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\r\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */\r\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\r\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */\r\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */\r\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\r\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */\r\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\r\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */\r\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\r\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */\r\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\r\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */\r\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\r\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */\r\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */\r\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\r\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */\r\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\r\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */\r\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\r\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */\r\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\r\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */\r\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\r\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */\r\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */\r\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\r\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */\r\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\r\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */\r\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\r\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */\r\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\r\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */\r\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\r\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */\r\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */\r\n\r\n/********************  Bits definition for DMA_HIFCR  register  ****************/\r\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\r\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */\r\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\r\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */\r\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\r\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */\r\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\r\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */\r\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\r\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */\r\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */\r\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\r\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */\r\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\r\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */\r\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\r\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */\r\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\r\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */\r\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\r\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */\r\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */\r\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\r\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */\r\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\r\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */\r\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\r\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */\r\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\r\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */\r\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\r\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */\r\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */\r\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\r\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */\r\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\r\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */\r\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\r\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */\r\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\r\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */\r\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\r\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */\r\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */\r\n\r\n/******************  Bit definition for DMA_SxPAR register  ********************/\r\n#define DMA_SxPAR_PA_Pos         (0U)\r\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */\r\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\r\n\r\n/******************  Bit definition for DMA_SxM0AR register  ********************/\r\n#define DMA_SxM0AR_M0A_Pos       (0U)\r\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */\r\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */\r\n\r\n/******************  Bit definition for DMA_SxM1AR register  ********************/\r\n#define DMA_SxM1AR_M1A_Pos       (0U)\r\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */\r\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             DMAMUX Controller                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DMAMUX_CxCR register  **************/\r\n#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)\r\n#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */\r\n#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */\r\n#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */\r\n#define DMAMUX_CxCR_SOIE_Pos           (8U)\r\n#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */\r\n#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */\r\n#define DMAMUX_CxCR_EGE_Pos            (9U)\r\n#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */\r\n#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */\r\n#define DMAMUX_CxCR_SE_Pos             (16U)\r\n#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */\r\n#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */\r\n#define DMAMUX_CxCR_SPOL_Pos           (17U)\r\n#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */\r\n#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */\r\n#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */\r\n#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */\r\n#define DMAMUX_CxCR_NBREQ_Pos          (19U)\r\n#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */\r\n#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */\r\n#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */\r\n#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */\r\n#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */\r\n#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */\r\n#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */\r\n#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)\r\n#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */\r\n#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */\r\n#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */\r\n\r\n/********************  Bits definition for DMAMUX_CSR register  **************/\r\n#define DMAMUX_CSR_SOF0_Pos            (0U)\r\n#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */\r\n#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF1_Pos            (1U)\r\n#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */\r\n#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF2_Pos            (2U)\r\n#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */\r\n#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF3_Pos            (3U)\r\n#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */\r\n#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF4_Pos            (4U)\r\n#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */\r\n#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF5_Pos            (5U)\r\n#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */\r\n#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF6_Pos            (6U)\r\n#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */\r\n#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF7_Pos            (7U)\r\n#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */\r\n#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF8_Pos            (8U)\r\n#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */\r\n#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF9_Pos            (9U)\r\n#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */\r\n#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF10_Pos           (10U)\r\n#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */\r\n#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF11_Pos           (11U)\r\n#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */\r\n#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF12_Pos           (12U)\r\n#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */\r\n#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF13_Pos           (13U)\r\n#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */\r\n#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF14_Pos           (14U)\r\n#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */\r\n#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF15_Pos           (15U)\r\n#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */\r\n#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */\r\n\r\n/********************  Bits definition for DMAMUX_CFR register  **************/\r\n#define DMAMUX_CFR_CSOF0_Pos           (0U)\r\n#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */\r\n#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF1_Pos           (1U)\r\n#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */\r\n#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF2_Pos           (2U)\r\n#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */\r\n#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF3_Pos           (3U)\r\n#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */\r\n#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF4_Pos           (4U)\r\n#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */\r\n#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF5_Pos           (5U)\r\n#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */\r\n#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF6_Pos           (6U)\r\n#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */\r\n#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF7_Pos           (7U)\r\n#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */\r\n#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF8_Pos           (8U)\r\n#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */\r\n#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF9_Pos           (9U)\r\n#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */\r\n#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF10_Pos          (10U)\r\n#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */\r\n#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF11_Pos          (11U)\r\n#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */\r\n#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF12_Pos          (12U)\r\n#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */\r\n#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF13_Pos          (13U)\r\n#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */\r\n#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF14_Pos          (14U)\r\n#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */\r\n#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF15_Pos          (15U)\r\n#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */\r\n#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */\r\n\r\n/********************  Bits definition for DMAMUX_RGxCR register  ************/\r\n#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)\r\n#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */\r\n#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */\r\n#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */\r\n#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */\r\n#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */\r\n#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */\r\n#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */\r\n#define DMAMUX_RGxCR_OIE_Pos           (8U)\r\n#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */\r\n#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */\r\n#define DMAMUX_RGxCR_GE_Pos            (16U)\r\n#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */\r\n#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */\r\n#define DMAMUX_RGxCR_GPOL_Pos          (17U)\r\n#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */\r\n#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */\r\n#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */\r\n#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */\r\n#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)\r\n#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */\r\n#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */\r\n#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */\r\n#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */\r\n#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */\r\n#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */\r\n#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */\r\n\r\n/********************  Bits definition for DMAMUX_RGSR register  **************/\r\n#define DMAMUX_RGSR_OF0_Pos            (0U)\r\n#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */\r\n#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF1_Pos            (1U)\r\n#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */\r\n#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF2_Pos            (2U)\r\n#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */\r\n#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF3_Pos            (3U)\r\n#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */\r\n#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF4_Pos            (4U)\r\n#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */\r\n#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF5_Pos            (5U)\r\n#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */\r\n#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF6_Pos            (6U)\r\n#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */\r\n#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF7_Pos            (7U)\r\n#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */\r\n#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */\r\n\r\n/********************  Bits definition for DMAMUX_RGCFR register  **************/\r\n#define DMAMUX_RGCFR_COF0_Pos          (0U)\r\n#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */\r\n#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF1_Pos          (1U)\r\n#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */\r\n#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF2_Pos          (2U)\r\n#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */\r\n#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF3_Pos          (3U)\r\n#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */\r\n#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF4_Pos          (4U)\r\n#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */\r\n#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF5_Pos          (5U)\r\n#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */\r\n#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF6_Pos          (6U)\r\n#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */\r\n#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF7_Pos          (7U)\r\n#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */\r\n#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         AHB Master DMA2D Controller (DMA2D)                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for DMA2D_CR register  ******************/\r\n\r\n#define DMA2D_CR_START_Pos         (0U)\r\n#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */\r\n#define DMA2D_CR_SUSP_Pos          (1U)\r\n#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */\r\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */\r\n#define DMA2D_CR_ABORT_Pos         (2U)\r\n#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */\r\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */\r\n#define DMA2D_CR_LOM_Pos           (6U)\r\n#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */\r\n#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */\r\n#define DMA2D_CR_TEIE_Pos          (8U)\r\n#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */\r\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */\r\n#define DMA2D_CR_TCIE_Pos          (9U)\r\n#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */\r\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */\r\n#define DMA2D_CR_TWIE_Pos          (10U)\r\n#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */\r\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */\r\n#define DMA2D_CR_CAEIE_Pos         (11U)\r\n#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */\r\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */\r\n#define DMA2D_CR_CTCIE_Pos         (12U)\r\n#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */\r\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\r\n#define DMA2D_CR_CEIE_Pos          (13U)\r\n#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */\r\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */\r\n#define DMA2D_CR_MODE_Pos          (16U)\r\n#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */\r\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */\r\n#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\r\n#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\r\n#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */\r\n\r\n/********************  Bit definition for DMA2D_ISR register  *****************/\r\n\r\n#define DMA2D_ISR_TEIF_Pos         (0U)\r\n#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */\r\n#define DMA2D_ISR_TCIF_Pos         (1U)\r\n#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */\r\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */\r\n#define DMA2D_ISR_TWIF_Pos         (2U)\r\n#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */\r\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_ISR_CAEIF_Pos        (3U)\r\n#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_ISR_CTCIF_Pos        (4U)\r\n#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */\r\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_ISR_CEIF_Pos         (5U)\r\n#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */\r\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_IFCR register  ****************/\r\n\r\n#define DMA2D_IFCR_CTEIF_Pos       (0U)\r\n#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */\r\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */\r\n#define DMA2D_IFCR_CTCIF_Pos       (1U)\r\n#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */\r\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */\r\n#define DMA2D_IFCR_CTWIF_Pos       (2U)\r\n#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */\r\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_IFCR_CAECIF_Pos      (3U)\r\n#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */\r\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)\r\n#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */\r\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_IFCR_CCEIF_Pos       (5U)\r\n#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */\r\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\r\n\r\n#define DMA2D_FGMAR_MA_Pos         (0U)\r\n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */\r\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_FGOR register  ****************/\r\n\r\n#define DMA2D_FGOR_LO_Pos          (0U)\r\n#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */\r\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\r\n\r\n#define DMA2D_BGMAR_MA_Pos         (0U)\r\n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */\r\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGOR register  ****************/\r\n\r\n#define DMA2D_BGOR_LO_Pos          (0U)\r\n#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */\r\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\r\n\r\n#define DMA2D_FGPFCCR_CM_Pos       (0U)\r\n#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */\r\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\r\n#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)\r\n#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */\r\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\r\n#define DMA2D_FGPFCCR_START_Pos    (5U)\r\n#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */\r\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\r\n#define DMA2D_FGPFCCR_CS_Pos       (8U)\r\n#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */\r\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\r\n#define DMA2D_FGPFCCR_AM_Pos       (16U)\r\n#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */\r\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\r\n#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\r\n#define DMA2D_FGPFCCR_CSS_Pos      (18U)\r\n#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */\r\n#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */\r\n#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */\r\n#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */\r\n#define DMA2D_FGPFCCR_AI_Pos       (20U)\r\n#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */\r\n#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */\r\n#define DMA2D_FGPFCCR_RBS_Pos      (21U)\r\n#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */\r\n#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */\r\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)\r\n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */\r\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\r\n\r\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)\r\n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */\r\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */\r\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)\r\n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */\r\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */\r\n#define DMA2D_FGCOLR_RED_Pos       (16U)\r\n#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */\r\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */\r\n\r\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\r\n\r\n#define DMA2D_BGPFCCR_CM_Pos       (0U)\r\n#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */\r\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\r\n#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)\r\n#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */\r\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\r\n#define DMA2D_BGPFCCR_START_Pos    (5U)\r\n#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */\r\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\r\n#define DMA2D_BGPFCCR_CS_Pos       (8U)\r\n#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */\r\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\r\n#define DMA2D_BGPFCCR_AM_Pos       (16U)\r\n#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */\r\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\r\n#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\r\n#define DMA2D_BGPFCCR_AI_Pos       (20U)\r\n#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */\r\n#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */\r\n#define DMA2D_BGPFCCR_RBS_Pos      (21U)\r\n#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */\r\n#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */\r\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)\r\n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */\r\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\r\n\r\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)\r\n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */\r\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */\r\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)\r\n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */\r\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */\r\n#define DMA2D_BGCOLR_RED_Pos       (16U)\r\n#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */\r\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */\r\n\r\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\r\n\r\n#define DMA2D_FGCMAR_MA_Pos        (0U)\r\n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */\r\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\r\n\r\n#define DMA2D_BGCMAR_MA_Pos        (0U)\r\n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */\r\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\r\n\r\n#define DMA2D_OPFCCR_CM_Pos        (0U)\r\n#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */\r\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */\r\n#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_OPFCCR_SB_Pos        (8U)\r\n#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */\r\n#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */\r\n#define DMA2D_OPFCCR_AI_Pos        (20U)\r\n#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */\r\n#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */\r\n#define DMA2D_OPFCCR_RBS_Pos       (21U)\r\n#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */\r\n#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */\r\n\r\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\r\n\r\n/*!<Mode_ARGB8888/RGB888 */\r\n\r\n#define DMA2D_OCOLR_BLUE_1_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/\r\n#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_1_Pos    (8U)\r\n#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/\r\n#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_1_Pos      (16U)\r\n#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */\r\n#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */\r\n#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)\r\n#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/\r\n#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */\r\n\r\n/*!<Mode_RGB565 */\r\n#define DMA2D_OCOLR_BLUE_2_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/\r\n#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_2_Pos    (5U)\r\n#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */\r\n#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_2_Pos      (11U)\r\n#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/\r\n#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */\r\n\r\n/*!<Mode_ARGB1555 */\r\n#define DMA2D_OCOLR_BLUE_3_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/\r\n#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_3_Pos    (5U)\r\n#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/\r\n#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_3_Pos      (10U)\r\n#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/\r\n#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */\r\n#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)\r\n#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/\r\n#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */\r\n\r\n/*!<Mode_ARGB4444 */\r\n#define DMA2D_OCOLR_BLUE_4_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/\r\n#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_4_Pos    (4U)\r\n#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/\r\n#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_4_Pos      (8U)\r\n#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/\r\n#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */\r\n#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)\r\n#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/\r\n#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */\r\n\r\n/********************  Bit definition for DMA2D_OMAR register  ****************/\r\n\r\n#define DMA2D_OMAR_MA_Pos          (0U)\r\n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */\r\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OOR register  *****************/\r\n\r\n#define DMA2D_OOR_LO_Pos           (0U)\r\n#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */\r\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_NLR register  *****************/\r\n\r\n#define DMA2D_NLR_NL_Pos           (0U)\r\n#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */\r\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\r\n#define DMA2D_NLR_PL_Pos           (16U)\r\n#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */\r\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\r\n\r\n/********************  Bit definition for DMA2D_LWR register  *****************/\r\n\r\n#define DMA2D_LWR_LW_Pos           (0U)\r\n#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */\r\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\r\n\r\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\r\n\r\n#define DMA2D_AMTCR_EN_Pos         (0U)\r\n#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\r\n#define DMA2D_AMTCR_DT_Pos         (8U)\r\n#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */\r\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\r\n\r\n\r\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\r\n\r\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                    External Interrupt/Event Controller                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for EXTI_RTSR1 register  *******************/\r\n#define EXTI_RTSR1_TR_Pos          (0U)\r\n#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */\r\n#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */\r\n#define EXTI_RTSR1_TR0_Pos         (0U)\r\n#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */\r\n#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */\r\n#define EXTI_RTSR1_TR1_Pos         (1U)\r\n#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */\r\n#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */\r\n#define EXTI_RTSR1_TR2_Pos         (2U)\r\n#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */\r\n#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */\r\n#define EXTI_RTSR1_TR3_Pos         (3U)\r\n#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */\r\n#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */\r\n#define EXTI_RTSR1_TR4_Pos         (4U)\r\n#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */\r\n#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */\r\n#define EXTI_RTSR1_TR5_Pos         (5U)\r\n#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */\r\n#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */\r\n#define EXTI_RTSR1_TR6_Pos         (6U)\r\n#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */\r\n#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */\r\n#define EXTI_RTSR1_TR7_Pos         (7U)\r\n#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */\r\n#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */\r\n#define EXTI_RTSR1_TR8_Pos         (8U)\r\n#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */\r\n#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */\r\n#define EXTI_RTSR1_TR9_Pos         (9U)\r\n#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */\r\n#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */\r\n#define EXTI_RTSR1_TR10_Pos        (10U)\r\n#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */\r\n#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */\r\n#define EXTI_RTSR1_TR11_Pos        (11U)\r\n#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */\r\n#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */\r\n#define EXTI_RTSR1_TR12_Pos        (12U)\r\n#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */\r\n#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */\r\n#define EXTI_RTSR1_TR13_Pos        (13U)\r\n#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */\r\n#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */\r\n#define EXTI_RTSR1_TR14_Pos        (14U)\r\n#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */\r\n#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */\r\n#define EXTI_RTSR1_TR15_Pos        (15U)\r\n#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */\r\n#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */\r\n#define EXTI_RTSR1_TR16_Pos        (16U)\r\n#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */\r\n#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */\r\n#define EXTI_RTSR1_TR17_Pos        (17U)\r\n#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */\r\n#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */\r\n#define EXTI_RTSR1_TR18_Pos        (18U)\r\n#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */\r\n#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */\r\n#define EXTI_RTSR1_TR19_Pos        (19U)\r\n#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */\r\n#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */\r\n#define EXTI_RTSR1_TR20_Pos        (20U)\r\n#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */\r\n#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */\r\n#define EXTI_RTSR1_TR21_Pos        (21U)\r\n#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */\r\n#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */\r\n\r\n/******************  Bit definition for EXTI_FTSR1 register  *******************/\r\n#define EXTI_FTSR1_TR_Pos          (0U)\r\n#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */\r\n#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */\r\n#define EXTI_FTSR1_TR0_Pos         (0U)\r\n#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */\r\n#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */\r\n#define EXTI_FTSR1_TR1_Pos         (1U)\r\n#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */\r\n#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */\r\n#define EXTI_FTSR1_TR2_Pos         (2U)\r\n#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */\r\n#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */\r\n#define EXTI_FTSR1_TR3_Pos         (3U)\r\n#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */\r\n#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */\r\n#define EXTI_FTSR1_TR4_Pos         (4U)\r\n#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */\r\n#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */\r\n#define EXTI_FTSR1_TR5_Pos         (5U)\r\n#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */\r\n#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */\r\n#define EXTI_FTSR1_TR6_Pos         (6U)\r\n#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */\r\n#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */\r\n#define EXTI_FTSR1_TR7_Pos         (7U)\r\n#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */\r\n#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */\r\n#define EXTI_FTSR1_TR8_Pos         (8U)\r\n#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */\r\n#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */\r\n#define EXTI_FTSR1_TR9_Pos         (9U)\r\n#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */\r\n#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */\r\n#define EXTI_FTSR1_TR10_Pos        (10U)\r\n#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */\r\n#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */\r\n#define EXTI_FTSR1_TR11_Pos        (11U)\r\n#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */\r\n#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */\r\n#define EXTI_FTSR1_TR12_Pos        (12U)\r\n#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */\r\n#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */\r\n#define EXTI_FTSR1_TR13_Pos        (13U)\r\n#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */\r\n#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */\r\n#define EXTI_FTSR1_TR14_Pos        (14U)\r\n#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */\r\n#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */\r\n#define EXTI_FTSR1_TR15_Pos        (15U)\r\n#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */\r\n#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */\r\n#define EXTI_FTSR1_TR16_Pos        (16U)\r\n#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */\r\n#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */\r\n#define EXTI_FTSR1_TR17_Pos        (17U)\r\n#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */\r\n#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */\r\n#define EXTI_FTSR1_TR18_Pos        (18U)\r\n#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */\r\n#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */\r\n#define EXTI_FTSR1_TR19_Pos        (19U)\r\n#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */\r\n#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */\r\n#define EXTI_FTSR1_TR20_Pos        (20U)\r\n#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */\r\n#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */\r\n#define EXTI_FTSR1_TR21_Pos        (21U)\r\n#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */\r\n#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */\r\n\r\n/******************  Bit definition for EXTI_SWIER1 register  ******************/\r\n#define EXTI_SWIER1_SWIER0_Pos     (0U)\r\n#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */\r\n#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */\r\n#define EXTI_SWIER1_SWIER1_Pos     (1U)\r\n#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */\r\n#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */\r\n#define EXTI_SWIER1_SWIER2_Pos     (2U)\r\n#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */\r\n#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */\r\n#define EXTI_SWIER1_SWIER3_Pos     (3U)\r\n#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */\r\n#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */\r\n#define EXTI_SWIER1_SWIER4_Pos     (4U)\r\n#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */\r\n#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */\r\n#define EXTI_SWIER1_SWIER5_Pos     (5U)\r\n#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */\r\n#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */\r\n#define EXTI_SWIER1_SWIER6_Pos     (6U)\r\n#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */\r\n#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */\r\n#define EXTI_SWIER1_SWIER7_Pos     (7U)\r\n#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */\r\n#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */\r\n#define EXTI_SWIER1_SWIER8_Pos     (8U)\r\n#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */\r\n#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */\r\n#define EXTI_SWIER1_SWIER9_Pos     (9U)\r\n#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */\r\n#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */\r\n#define EXTI_SWIER1_SWIER10_Pos    (10U)\r\n#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */\r\n#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */\r\n#define EXTI_SWIER1_SWIER11_Pos    (11U)\r\n#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */\r\n#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */\r\n#define EXTI_SWIER1_SWIER12_Pos    (12U)\r\n#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */\r\n#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */\r\n#define EXTI_SWIER1_SWIER13_Pos    (13U)\r\n#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */\r\n#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */\r\n#define EXTI_SWIER1_SWIER14_Pos    (14U)\r\n#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */\r\n#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */\r\n#define EXTI_SWIER1_SWIER15_Pos    (15U)\r\n#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */\r\n#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */\r\n#define EXTI_SWIER1_SWIER16_Pos    (16U)\r\n#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */\r\n#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */\r\n#define EXTI_SWIER1_SWIER17_Pos    (17U)\r\n#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */\r\n#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */\r\n#define EXTI_SWIER1_SWIER18_Pos    (18U)\r\n#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */\r\n#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */\r\n#define EXTI_SWIER1_SWIER19_Pos    (19U)\r\n#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */\r\n#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */\r\n#define EXTI_SWIER1_SWIER20_Pos    (20U)\r\n#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */\r\n#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */\r\n#define EXTI_SWIER1_SWIER21_Pos    (21U)\r\n#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */\r\n#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */\r\n\r\n/******************  Bit definition for EXTI_D3PMR1 register  ******************/\r\n#define EXTI_D3PMR1_MR0_Pos        (0U)\r\n#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */\r\n#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */\r\n#define EXTI_D3PMR1_MR1_Pos        (1U)\r\n#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */\r\n#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */\r\n#define EXTI_D3PMR1_MR2_Pos        (2U)\r\n#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */\r\n#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */\r\n#define EXTI_D3PMR1_MR3_Pos        (3U)\r\n#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */\r\n#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */\r\n#define EXTI_D3PMR1_MR4_Pos        (4U)\r\n#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */\r\n#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */\r\n#define EXTI_D3PMR1_MR5_Pos        (5U)\r\n#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */\r\n#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */\r\n#define EXTI_D3PMR1_MR6_Pos        (6U)\r\n#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */\r\n#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */\r\n#define EXTI_D3PMR1_MR7_Pos        (7U)\r\n#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */\r\n#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */\r\n#define EXTI_D3PMR1_MR8_Pos        (8U)\r\n#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */\r\n#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */\r\n#define EXTI_D3PMR1_MR9_Pos        (9U)\r\n#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */\r\n#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */\r\n#define EXTI_D3PMR1_MR10_Pos       (10U)\r\n#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */\r\n#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */\r\n#define EXTI_D3PMR1_MR11_Pos       (11U)\r\n#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */\r\n#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */\r\n#define EXTI_D3PMR1_MR12_Pos       (12U)\r\n#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */\r\n#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */\r\n#define EXTI_D3PMR1_MR13_Pos       (13U)\r\n#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */\r\n#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */\r\n#define EXTI_D3PMR1_MR14_Pos       (14U)\r\n#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */\r\n#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */\r\n#define EXTI_D3PMR1_MR15_Pos       (15U)\r\n#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */\r\n#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */\r\n#define EXTI_D3PMR1_MR19_Pos       (19U)\r\n#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */\r\n#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */\r\n#define EXTI_D3PMR1_MR20_Pos       (20U)\r\n#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */\r\n#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */\r\n#define EXTI_D3PMR1_MR21_Pos       (21U)\r\n#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */\r\n#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */\r\n#define EXTI_D3PMR1_MR25_Pos       (24U)\r\n#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */\r\n#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */\r\n\r\n/*******************  Bit definition for EXTI_D3PCR1L register  ****************/\r\n#define EXTI_D3PCR1L_PCS0_Pos       (0U)\r\n#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */\r\n#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */\r\n#define EXTI_D3PCR1L_PCS1_Pos       (2U)\r\n#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */\r\n#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */\r\n#define EXTI_D3PCR1L_PCS2_Pos       (4U)\r\n#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */\r\n#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */\r\n#define EXTI_D3PCR1L_PCS3_Pos       (6U)\r\n#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */\r\n#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */\r\n#define EXTI_D3PCR1L_PCS4_Pos       (8U)\r\n#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */\r\n#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */\r\n#define EXTI_D3PCR1L_PCS5_Pos       (10U)\r\n#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */\r\n#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */\r\n#define EXTI_D3PCR1L_PCS6_Pos       (12U)\r\n#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */\r\n#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */\r\n#define EXTI_D3PCR1L_PCS7_Pos       (14U)\r\n#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */\r\n#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */\r\n#define EXTI_D3PCR1L_PCS8_Pos       (16U)\r\n#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */\r\n#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */\r\n#define EXTI_D3PCR1L_PCS9_Pos       (18U)\r\n#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */\r\n#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */\r\n#define EXTI_D3PCR1L_PCS10_Pos      (20U)\r\n#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */\r\n#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/\r\n#define EXTI_D3PCR1L_PCS11_Pos      (22U)\r\n#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */\r\n#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/\r\n#define EXTI_D3PCR1L_PCS12_Pos      (24U)\r\n#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */\r\n#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/\r\n#define EXTI_D3PCR1L_PCS13_Pos      (26U)\r\n#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */\r\n#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/\r\n#define EXTI_D3PCR1L_PCS14_Pos      (28U)\r\n#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */\r\n#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/\r\n#define EXTI_D3PCR1L_PCS15_Pos      (30U)\r\n#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */\r\n#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/\r\n\r\n/*******************  Bit definition for EXTI_D3PCR1H register  ****************/\r\n#define EXTI_D3PCR1H_PCS19_Pos       (6U)\r\n#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */\r\n#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */\r\n#define EXTI_D3PCR1H_PCS20_Pos       (8U)\r\n#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */\r\n#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */\r\n#define EXTI_D3PCR1H_PCS21_Pos       (10U)\r\n#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */\r\n#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */\r\n#define EXTI_D3PCR1H_PCS25_Pos       (18U)\r\n#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */\r\n#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */\r\n\r\n/******************  Bit definition for EXTI_RTSR2 register  *******************/\r\n#define EXTI_RTSR2_TR_Pos          (17U)\r\n#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */\r\n#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */\r\n#define EXTI_RTSR2_TR49_Pos        (17U)\r\n#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */\r\n#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */\r\n#define EXTI_RTSR2_TR51_Pos        (19U)\r\n#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */\r\n#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */\r\n\r\n/******************  Bit definition for EXTI_FTSR2 register  *******************/\r\n#define EXTI_FTSR2_TR_Pos          (17U)\r\n#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */\r\n#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */\r\n#define EXTI_FTSR2_TR49_Pos        (17U)\r\n#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */\r\n#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */\r\n#define EXTI_FTSR2_TR51_Pos        (19U)\r\n#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */\r\n#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */\r\n\r\n/******************  Bit definition for EXTI_SWIER2 register  ******************/\r\n#define EXTI_SWIER2_SWIER49_Pos    (17U)\r\n#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */\r\n#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */\r\n#define EXTI_SWIER2_SWIER51_Pos    (19U)\r\n#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */\r\n#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */\r\n\r\n/******************  Bit definition for EXTI_D3PMR2 register  ******************/\r\n#define EXTI_D3PMR2_MR34_Pos       (2U)\r\n#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */\r\n#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */\r\n#define EXTI_D3PMR2_MR35_Pos       (3U)\r\n#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */\r\n#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */\r\n#define EXTI_D3PMR2_MR41_Pos       (9U)\r\n#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */\r\n#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */\r\n#define EXTI_D3PMR2_MR48_Pos       (16U)\r\n#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */\r\n#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */\r\n#define EXTI_D3PMR2_MR49_Pos       (17U)\r\n#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */\r\n#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */\r\n#define EXTI_D3PMR2_MR50_Pos       (18U)\r\n#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */\r\n#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */\r\n#define EXTI_D3PMR2_MR51_Pos       (19U)\r\n#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */\r\n#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */\r\n#define EXTI_D3PMR2_MR52_Pos       (20U)\r\n#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */\r\n#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */\r\n#define EXTI_D3PMR2_MR53_Pos       (21U)\r\n#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */\r\n#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */\r\n/*******************  Bit definition for EXTI_D3PCR2L register  ****************/\r\n#define EXTI_D3PCR2L_PCS34_Pos       (4U)\r\n#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */\r\n#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */\r\n#define EXTI_D3PCR2L_PCS35_Pos       (6U)\r\n#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */\r\n#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */\r\n#define EXTI_D3PCR2L_PCS41_Pos       (18U)\r\n#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */\r\n#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */\r\n\r\n\r\n/*******************  Bit definition for EXTI_D3PCR2H register  ****************/\r\n#define EXTI_D3PCR2H_PCS48_Pos       (0U)\r\n#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */\r\n#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */\r\n#define EXTI_D3PCR2H_PCS49_Pos       (2U)\r\n#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */\r\n#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */\r\n#define EXTI_D3PCR2H_PCS50_Pos       (4U)\r\n#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */\r\n#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */\r\n#define EXTI_D3PCR2H_PCS51_Pos       (6U)\r\n#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */\r\n#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */\r\n#define EXTI_D3PCR2H_PCS52_Pos       (8U)\r\n#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */\r\n#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */\r\n#define EXTI_D3PCR2H_PCS53_Pos       (10U)\r\n#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */\r\n#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */\r\n/******************  Bit definition for EXTI_RTSR3 register  *******************/\r\n#define EXTI_RTSR3_TR_Pos          (21U)\r\n#define EXTI_RTSR3_TR_Msk          (0x3UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00600000 */\r\n#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */\r\n#define EXTI_RTSR3_TR85_Pos        (21U)\r\n#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */\r\n#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */\r\n#define EXTI_RTSR3_TR86_Pos        (22U)\r\n#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */\r\n#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */\r\n\r\n/******************  Bit definition for EXTI_FTSR3 register  *******************/\r\n#define EXTI_FTSR3_TR_Pos          (21U)\r\n#define EXTI_FTSR3_TR_Msk          (0x3UL << EXTI_FTSR3_TR_Pos)               /*!< 0x00600000 */\r\n#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */\r\n#define EXTI_FTSR3_TR85_Pos        (21U)\r\n#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */\r\n#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */\r\n#define EXTI_FTSR3_TR86_Pos        (22U)\r\n#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */\r\n#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */\r\n\r\n/******************  Bit definition for EXTI_SWIER3 register  ******************/\r\n#define EXTI_SWIER3_SWI_Pos        (21U)\r\n#define EXTI_SWIER3_SWI_Msk        (0x3UL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00600000 */\r\n#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */\r\n#define EXTI_SWIER3_SWIER85_Pos    (21U)\r\n#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */\r\n#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */\r\n#define EXTI_SWIER3_SWIER86_Pos    (22U)\r\n#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */\r\n#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */\r\n\r\n/******************  Bit definition for EXTI_D3PMR3 register  ******************/\r\n#define EXTI_D3PMR3_MR88_Pos       (24U)\r\n#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */\r\n#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */\r\n\r\n/*******************  Bit definition for EXTI_D3PCR3H register  ****************/\r\n#define EXTI_D3PCR3H_PCS88_Pos       (16U)\r\n#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */\r\n#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */\r\n\r\n/*******************  Bit definition for EXTI_IMR1 register  *******************/\r\n#define EXTI_IMR1_IM_Pos           (0U)\r\n#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */\r\n#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */\r\n#define EXTI_IMR1_IM0_Pos          (0U)\r\n#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */\r\n#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */\r\n#define EXTI_IMR1_IM1_Pos          (1U)\r\n#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */\r\n#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */\r\n#define EXTI_IMR1_IM2_Pos          (2U)\r\n#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */\r\n#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */\r\n#define EXTI_IMR1_IM3_Pos          (3U)\r\n#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */\r\n#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */\r\n#define EXTI_IMR1_IM4_Pos          (4U)\r\n#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */\r\n#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */\r\n#define EXTI_IMR1_IM5_Pos          (5U)\r\n#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */\r\n#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */\r\n#define EXTI_IMR1_IM6_Pos          (6U)\r\n#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */\r\n#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */\r\n#define EXTI_IMR1_IM7_Pos          (7U)\r\n#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */\r\n#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */\r\n#define EXTI_IMR1_IM8_Pos          (8U)\r\n#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */\r\n#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */\r\n#define EXTI_IMR1_IM9_Pos          (9U)\r\n#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */\r\n#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */\r\n#define EXTI_IMR1_IM10_Pos         (10U)\r\n#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */\r\n#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */\r\n#define EXTI_IMR1_IM11_Pos         (11U)\r\n#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */\r\n#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */\r\n#define EXTI_IMR1_IM12_Pos         (12U)\r\n#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */\r\n#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */\r\n#define EXTI_IMR1_IM13_Pos         (13U)\r\n#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */\r\n#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */\r\n#define EXTI_IMR1_IM14_Pos         (14U)\r\n#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */\r\n#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */\r\n#define EXTI_IMR1_IM15_Pos         (15U)\r\n#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */\r\n#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */\r\n#define EXTI_IMR1_IM16_Pos         (16U)\r\n#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */\r\n#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */\r\n#define EXTI_IMR1_IM17_Pos         (17U)\r\n#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */\r\n#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */\r\n#define EXTI_IMR1_IM18_Pos         (18U)\r\n#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */\r\n#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */\r\n#define EXTI_IMR1_IM19_Pos         (19U)\r\n#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */\r\n#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */\r\n#define EXTI_IMR1_IM20_Pos         (20U)\r\n#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */\r\n#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */\r\n#define EXTI_IMR1_IM21_Pos         (21U)\r\n#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */\r\n#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */\r\n#define EXTI_IMR1_IM22_Pos         (22U)\r\n#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */\r\n#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */\r\n#define EXTI_IMR1_IM23_Pos         (23U)\r\n#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */\r\n#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */\r\n#define EXTI_IMR1_IM24_Pos         (24U)\r\n#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */\r\n#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */\r\n#define EXTI_IMR1_IM25_Pos         (25U)\r\n#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */\r\n#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */\r\n#define EXTI_IMR1_IM26_Pos         (26U)\r\n#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */\r\n#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */\r\n#define EXTI_IMR1_IM27_Pos         (27U)\r\n#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */\r\n#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */\r\n#define EXTI_IMR1_IM28_Pos         (28U)\r\n#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */\r\n#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */\r\n#define EXTI_IMR1_IM29_Pos         (29U)\r\n#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */\r\n#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */\r\n#define EXTI_IMR1_IM30_Pos         (30U)\r\n#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */\r\n#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */\r\n#define EXTI_IMR1_IM31_Pos         (31U)\r\n#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */\r\n#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */\r\n\r\n/*******************  Bit definition for EXTI_EMR1 register  *******************/\r\n#define EXTI_EMR1_EM_Pos           (0U)\r\n#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */\r\n#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */\r\n#define EXTI_EMR1_EM0_Pos          (0U)\r\n#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */\r\n#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */\r\n#define EXTI_EMR1_EM1_Pos          (1U)\r\n#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */\r\n#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */\r\n#define EXTI_EMR1_EM2_Pos          (2U)\r\n#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */\r\n#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */\r\n#define EXTI_EMR1_EM3_Pos          (3U)\r\n#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */\r\n#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */\r\n#define EXTI_EMR1_EM4_Pos          (4U)\r\n#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */\r\n#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */\r\n#define EXTI_EMR1_EM5_Pos          (5U)\r\n#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */\r\n#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */\r\n#define EXTI_EMR1_EM6_Pos          (6U)\r\n#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */\r\n#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */\r\n#define EXTI_EMR1_EM7_Pos          (7U)\r\n#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */\r\n#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */\r\n#define EXTI_EMR1_EM8_Pos          (8U)\r\n#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */\r\n#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */\r\n#define EXTI_EMR1_EM9_Pos          (9U)\r\n#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */\r\n#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */\r\n#define EXTI_EMR1_EM10_Pos         (10U)\r\n#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */\r\n#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */\r\n#define EXTI_EMR1_EM11_Pos         (11U)\r\n#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */\r\n#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */\r\n#define EXTI_EMR1_EM12_Pos         (12U)\r\n#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */\r\n#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */\r\n#define EXTI_EMR1_EM13_Pos         (13U)\r\n#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */\r\n#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */\r\n#define EXTI_EMR1_EM14_Pos         (14U)\r\n#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */\r\n#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */\r\n#define EXTI_EMR1_EM15_Pos         (15U)\r\n#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */\r\n#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */\r\n#define EXTI_EMR1_EM16_Pos         (16U)\r\n#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */\r\n#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */\r\n#define EXTI_EMR1_EM17_Pos         (17U)\r\n#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */\r\n#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */\r\n#define EXTI_EMR1_EM18_Pos         (18U)\r\n#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */\r\n#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */\r\n#define EXTI_EMR1_EM20_Pos         (20U)\r\n#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */\r\n#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */\r\n#define EXTI_EMR1_EM21_Pos         (21U)\r\n#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */\r\n#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */\r\n#define EXTI_EMR1_EM22_Pos         (22U)\r\n#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */\r\n#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */\r\n#define EXTI_EMR1_EM23_Pos         (23U)\r\n#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */\r\n#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */\r\n#define EXTI_EMR1_EM24_Pos         (24U)\r\n#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */\r\n#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */\r\n#define EXTI_EMR1_EM25_Pos         (25U)\r\n#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */\r\n#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */\r\n#define EXTI_EMR1_EM26_Pos         (26U)\r\n#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */\r\n#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */\r\n#define EXTI_EMR1_EM27_Pos         (27U)\r\n#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */\r\n#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */\r\n#define EXTI_EMR1_EM28_Pos         (28U)\r\n#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */\r\n#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */\r\n#define EXTI_EMR1_EM29_Pos         (29U)\r\n#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */\r\n#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */\r\n#define EXTI_EMR1_EM30_Pos         (30U)\r\n#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */\r\n#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */\r\n#define EXTI_EMR1_EM31_Pos         (31U)\r\n#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */\r\n#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */\r\n\r\n/*******************  Bit definition for EXTI_PR1 register  ********************/\r\n#define EXTI_PR1_PR_Pos            (0U)\r\n#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */\r\n#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */\r\n#define EXTI_PR1_PR0_Pos           (0U)\r\n#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */\r\n#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */\r\n#define EXTI_PR1_PR1_Pos           (1U)\r\n#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */\r\n#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */\r\n#define EXTI_PR1_PR2_Pos           (2U)\r\n#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */\r\n#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */\r\n#define EXTI_PR1_PR3_Pos           (3U)\r\n#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */\r\n#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */\r\n#define EXTI_PR1_PR4_Pos           (4U)\r\n#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */\r\n#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */\r\n#define EXTI_PR1_PR5_Pos           (5U)\r\n#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */\r\n#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */\r\n#define EXTI_PR1_PR6_Pos           (6U)\r\n#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */\r\n#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */\r\n#define EXTI_PR1_PR7_Pos           (7U)\r\n#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */\r\n#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */\r\n#define EXTI_PR1_PR8_Pos           (8U)\r\n#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */\r\n#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */\r\n#define EXTI_PR1_PR9_Pos           (9U)\r\n#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */\r\n#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */\r\n#define EXTI_PR1_PR10_Pos          (10U)\r\n#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */\r\n#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */\r\n#define EXTI_PR1_PR11_Pos          (11U)\r\n#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */\r\n#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */\r\n#define EXTI_PR1_PR12_Pos          (12U)\r\n#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */\r\n#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */\r\n#define EXTI_PR1_PR13_Pos          (13U)\r\n#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */\r\n#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */\r\n#define EXTI_PR1_PR14_Pos          (14U)\r\n#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */\r\n#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */\r\n#define EXTI_PR1_PR15_Pos          (15U)\r\n#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */\r\n#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */\r\n#define EXTI_PR1_PR16_Pos          (16U)\r\n#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */\r\n#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */\r\n#define EXTI_PR1_PR17_Pos          (17U)\r\n#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */\r\n#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */\r\n#define EXTI_PR1_PR18_Pos          (18U)\r\n#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */\r\n#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */\r\n#define EXTI_PR1_PR19_Pos          (19U)\r\n#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */\r\n#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */\r\n#define EXTI_PR1_PR20_Pos          (20U)\r\n#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */\r\n#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */\r\n#define EXTI_PR1_PR21_Pos          (21U)\r\n#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */\r\n#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */\r\n\r\n/*******************  Bit definition for EXTI_IMR2 register  *******************/\r\n#define EXTI_IMR2_IM_Pos           (0U)\r\n#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */\r\n#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */\r\n#define EXTI_IMR2_IM32_Pos         (0U)\r\n#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */\r\n#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */\r\n#define EXTI_IMR2_IM33_Pos         (1U)\r\n#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */\r\n#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */\r\n#define EXTI_IMR2_IM34_Pos         (2U)\r\n#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */\r\n#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */\r\n#define EXTI_IMR2_IM35_Pos         (3U)\r\n#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */\r\n#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */\r\n#define EXTI_IMR2_IM36_Pos         (4U)\r\n#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */\r\n#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */\r\n#define EXTI_IMR2_IM37_Pos         (5U)\r\n#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */\r\n#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */\r\n#define EXTI_IMR2_IM38_Pos         (6U)\r\n#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */\r\n#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */\r\n#define EXTI_IMR2_IM39_Pos         (7U)\r\n#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */\r\n#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */\r\n#define EXTI_IMR2_IM40_Pos         (8U)\r\n#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */\r\n#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */\r\n#define EXTI_IMR2_IM41_Pos         (9U)\r\n#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */\r\n#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */\r\n#define EXTI_IMR2_IM42_Pos         (10U)\r\n#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */\r\n#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */\r\n#define EXTI_IMR2_IM43_Pos         (11U)\r\n#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */\r\n#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */\r\n#define EXTI_IMR2_IM47_Pos         (15U)\r\n#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */\r\n#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */\r\n#define EXTI_IMR2_IM48_Pos         (16U)\r\n#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */\r\n#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */\r\n#define EXTI_IMR2_IM49_Pos         (17U)\r\n#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */\r\n#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */\r\n#define EXTI_IMR2_IM50_Pos         (18U)\r\n#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */\r\n#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */\r\n#define EXTI_IMR2_IM51_Pos         (19U)\r\n#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */\r\n#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */\r\n#define EXTI_IMR2_IM52_Pos         (20U)\r\n#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */\r\n#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */\r\n#define EXTI_IMR2_IM53_Pos         (21U)\r\n#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */\r\n#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */\r\n#define EXTI_IMR2_IM54_Pos         (22U)\r\n#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */\r\n#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */\r\n#define EXTI_IMR2_IM55_Pos         (23U)\r\n#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */\r\n#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */\r\n#define EXTI_IMR2_IM56_Pos         (24U)\r\n#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */\r\n#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */\r\n#define EXTI_IMR2_IM58_Pos         (26U)\r\n#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */\r\n#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */\r\n#define EXTI_IMR2_IM60_Pos         (28U)\r\n#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */\r\n#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */\r\n#define EXTI_IMR2_IM61_Pos         (29U)\r\n#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */\r\n#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */\r\n#define EXTI_IMR2_IM62_Pos         (30U)\r\n#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */\r\n#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */\r\n#define EXTI_IMR2_IM63_Pos         (31U)\r\n#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */\r\n#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */\r\n\r\n/*******************  Bit definition for EXTI_EMR2 register  *******************/\r\n#define EXTI_EMR2_EM_Pos           (0U)\r\n#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */\r\n#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */\r\n#define EXTI_EMR2_EM32_Pos         (0U)\r\n#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */\r\n#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/\r\n#define EXTI_EMR2_EM33_Pos         (1U)\r\n#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */\r\n#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/\r\n#define EXTI_EMR2_EM34_Pos         (2U)\r\n#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */\r\n#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/\r\n#define EXTI_EMR2_EM35_Pos         (3U)\r\n#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */\r\n#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/\r\n#define EXTI_EMR2_EM36_Pos         (4U)\r\n#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */\r\n#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/\r\n#define EXTI_EMR2_EM37_Pos         (5U)\r\n#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */\r\n#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/\r\n#define EXTI_EMR2_EM38_Pos         (6U)\r\n#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */\r\n#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/\r\n#define EXTI_EMR2_EM39_Pos         (7U)\r\n#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */\r\n#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/\r\n#define EXTI_EMR2_EM40_Pos         (8U)\r\n#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */\r\n#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/\r\n#define EXTI_EMR2_EM41_Pos         (9U)\r\n#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */\r\n#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/\r\n#define EXTI_EMR2_EM42_Pos         (10U)\r\n#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */\r\n#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */\r\n#define EXTI_EMR2_EM43_Pos         (11U)\r\n#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */\r\n#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */\r\n#define EXTI_EMR2_EM47_Pos         (15U)\r\n#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */\r\n#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */\r\n#define EXTI_EMR2_EM48_Pos         (16U)\r\n#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */\r\n#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */\r\n#define EXTI_EMR2_EM49_Pos         (17U)\r\n#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */\r\n#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */\r\n#define EXTI_EMR2_EM50_Pos         (18U)\r\n#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */\r\n#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */\r\n#define EXTI_EMR2_EM51_Pos         (19U)\r\n#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */\r\n#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */\r\n#define EXTI_EMR2_EM52_Pos         (20U)\r\n#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */\r\n#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */\r\n#define EXTI_EMR2_EM53_Pos         (21U)\r\n#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */\r\n#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */\r\n#define EXTI_EMR2_EM54_Pos         (22U)\r\n#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */\r\n#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */\r\n#define EXTI_EMR2_EM55_Pos         (23U)\r\n#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */\r\n#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */\r\n#define EXTI_EMR2_EM56_Pos         (24U)\r\n#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */\r\n#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */\r\n#define EXTI_EMR2_EM58_Pos         (26U)\r\n#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */\r\n#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */\r\n#define EXTI_EMR2_EM60_Pos         (28U)\r\n#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */\r\n#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */\r\n#define EXTI_EMR2_EM61_Pos         (29U)\r\n#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */\r\n#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */\r\n#define EXTI_EMR2_EM62_Pos         (30U)\r\n#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */\r\n#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */\r\n#define EXTI_EMR2_EM63_Pos         (31U)\r\n#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */\r\n#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */\r\n\r\n/*******************  Bit definition for EXTI_PR2 register  ********************/\r\n#define EXTI_PR2_PR_Pos            (17U)\r\n#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */\r\n#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */\r\n#define EXTI_PR2_PR49_Pos          (17U)\r\n#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */\r\n#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */\r\n#define EXTI_PR2_PR51_Pos          (19U)\r\n#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */\r\n#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */\r\n\r\n/*******************  Bit definition for EXTI_IMR3 register  *******************/\r\n#define EXTI_IMR3_IM_Pos           (0U)\r\n#define EXTI_IMR3_IM_Msk           (0x0FE17FFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x0FE17FFF */\r\n#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */\r\n#define EXTI_IMR3_IM64_Pos         (0U)\r\n#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */\r\n#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */\r\n#define EXTI_IMR3_IM65_Pos         (1U)\r\n#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */\r\n#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */\r\n#define EXTI_IMR3_IM66_Pos         (2U)\r\n#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */\r\n#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */\r\n#define EXTI_IMR3_IM67_Pos         (3U)\r\n#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */\r\n#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */\r\n#define EXTI_IMR3_IM68_Pos         (4U)\r\n#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */\r\n#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */\r\n#define EXTI_IMR3_IM69_Pos         (5U)\r\n#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */\r\n#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */\r\n#define EXTI_IMR3_IM70_Pos         (6U)\r\n#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */\r\n#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */\r\n#define EXTI_IMR3_IM71_Pos         (7U)\r\n#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */\r\n#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */\r\n#define EXTI_IMR3_IM72_Pos         (8U)\r\n#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */\r\n#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */\r\n#define EXTI_IMR3_IM73_Pos         (9U)\r\n#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */\r\n#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */\r\n#define EXTI_IMR3_IM74_Pos         (10U)\r\n#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */\r\n#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */\r\n#define EXTI_IMR3_IM75_Pos         (11U)\r\n#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */\r\n#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */\r\n#define EXTI_IMR3_IM76_Pos         (12U)\r\n#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */\r\n#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */\r\n#define EXTI_IMR3_IM77_Pos         (13U)\r\n#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */\r\n#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */\r\n#define EXTI_IMR3_IM78_Pos         (14U)\r\n#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */\r\n#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */\r\n#define EXTI_IMR3_IM80_Pos         (16U)\r\n#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */\r\n#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */\r\n#define EXTI_IMR3_IM85_Pos         (21U)\r\n#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */\r\n#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */\r\n#define EXTI_IMR3_IM86_Pos         (22U)\r\n#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */\r\n#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */\r\n#define EXTI_IMR3_IM87_Pos         (23U)\r\n#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */\r\n#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */\r\n\r\n\r\n#define EXTI_IMR3_IM88_Pos         (24U)\r\n#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */\r\n#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */\r\n\r\n#define EXTI_IMR3_IM89_Pos         (25U)\r\n#define EXTI_IMR3_IM89_Msk         (0x1UL << EXTI_IMR3_IM89_Pos)               /*!< 0x0200000 */\r\n#define EXTI_IMR3_IM89             EXTI_IMR3_IM89_Msk                          /*!< Interrupt Mask on line 89 */\r\n#define EXTI_IMR3_IM90_Pos         (26U)\r\n#define EXTI_IMR3_IM90_Msk         (0x1UL << EXTI_IMR3_IM90_Pos)               /*!< 0x0400000 */\r\n#define EXTI_IMR3_IM90             EXTI_IMR3_IM90_Msk                          /*!< Interrupt Mask on line 90 */\r\n#define EXTI_IMR3_IM91_Pos         (27U)\r\n#define EXTI_IMR3_IM91_Msk         (0x1UL << EXTI_IMR3_IM91_Pos)               /*!< 0x0800000 */\r\n#define EXTI_IMR3_IM91             EXTI_IMR3_IM91_Msk                          /*!< Interrupt Mask on line 91 */\r\n\r\n/*******************  Bit definition for EXTI_EMR3 register  *******************/\r\n#define EXTI_EMR3_EM_Pos           (0U)\r\n#define EXTI_EMR3_EM_Msk           (0x0FE17FFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x0FE17FFF */\r\n#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Interrupt Mask            */\r\n#define EXTI_EMR3_EM64_Pos         (0U)\r\n#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */\r\n#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/\r\n#define EXTI_EMR3_EM65_Pos         (1U)\r\n#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */\r\n#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/\r\n#define EXTI_EMR3_EM66_Pos         (2U)\r\n#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */\r\n#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/\r\n#define EXTI_EMR3_EM67_Pos         (3U)\r\n#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */\r\n#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/\r\n#define EXTI_EMR3_EM68_Pos         (4U)\r\n#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */\r\n#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/\r\n#define EXTI_EMR3_EM69_Pos         (5U)\r\n#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */\r\n#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/\r\n#define EXTI_EMR3_EM70_Pos         (6U)\r\n#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */\r\n#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/\r\n#define EXTI_EMR3_EM71_Pos         (7U)\r\n#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */\r\n#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/\r\n#define EXTI_EMR3_EM72_Pos         (8U)\r\n#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */\r\n#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/\r\n#define EXTI_EMR3_EM73_Pos         (9U)\r\n#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */\r\n#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/\r\n#define EXTI_EMR3_EM74_Pos         (10U)\r\n#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */\r\n#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */\r\n#define EXTI_EMR3_EM75_Pos         (11U)\r\n#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */\r\n#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */\r\n#define EXTI_EMR3_EM76_Pos         (12U)\r\n#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */\r\n#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */\r\n#define EXTI_EMR3_EM77_Pos         (13U)\r\n#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */\r\n#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */\r\n#define EXTI_EMR3_EM78_Pos         (14U)\r\n#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */\r\n#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */\r\n#define EXTI_EMR3_EM80_Pos         (16U)\r\n#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */\r\n#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */\r\n#define EXTI_EMR3_EM85_Pos         (21U)\r\n#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */\r\n#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */\r\n#define EXTI_EMR3_EM86_Pos         (22U)\r\n#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */\r\n#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */\r\n#define EXTI_EMR3_EM87_Pos         (23U)\r\n#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */\r\n#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */\r\n\r\n#define EXTI_EMR3_EM88_Pos         (24U)\r\n#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */\r\n#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */\r\n\r\n#define EXTI_EMR3_EM89_Pos         (25U)\r\n#define EXTI_EMR3_EM89_Msk         (0x1UL << EXTI_EMR3_EM89_Pos)               /*!< 0x0200000 */\r\n#define EXTI_EMR3_EM89             EXTI_EMR3_EM89_Msk                          /*!< Interrupt Mask on line 89 */\r\n#define EXTI_EMR3_EM90_Pos         (26U)\r\n#define EXTI_EMR3_EM90_Msk         (0x1UL << EXTI_EMR3_EM90_Pos)               /*!< 0x0400000 */\r\n#define EXTI_EMR3_EM90             EXTI_EMR3_EM90_Msk                          /*!< Interrupt Mask on line 90 */\r\n#define EXTI_EMR3_EM91_Pos         (27U)\r\n#define EXTI_EMR3_EM91_Msk         (0x1UL << EXTI_EMR3_EM91_Pos)               /*!< 0x0800000 */\r\n#define EXTI_EMR3_EM91             EXTI_EMR3_EM91_Msk                          /*!< Interrupt Mask on line 91 */\r\n\r\n/*******************  Bit definition for EXTI_PR3 register  ********************/\r\n#define EXTI_PR3_PR_Pos            (20U)\r\n#define EXTI_PR3_PR_Msk            (0x7UL << EXTI_PR3_PR_Pos)                  /*!< 0x00700000 */\r\n#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */\r\n#define EXTI_PR3_PR84_Pos          (20U)\r\n#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */\r\n#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */\r\n#define EXTI_PR3_PR85_Pos          (21U)\r\n#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */\r\n#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */\r\n#define EXTI_PR3_PR86_Pos          (22U)\r\n#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */\r\n#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    FLASH                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*\r\n* @brief FLASH Global Defines\r\n*/\r\n#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U\r\n#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */\r\n#define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \\\r\n                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \\\r\n                                             (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 1 MB   */\r\n#define FLASH_BANK_SIZE                      FLASH_SIZE            /* 1 MB   */\r\n#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB   */\r\n#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */\r\n#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */\r\n\r\n/*******************  Bits definition for FLASH_ACR register  **********************/\r\n#define FLASH_ACR_LATENCY_Pos                (0U)\r\n#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */\r\n#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */\r\n#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)\r\n#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)\r\n#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)\r\n#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)\r\n#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)\r\n#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)\r\n#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)\r\n#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)\r\n#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)\r\n#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)\r\n#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)\r\n#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)\r\n#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)\r\n#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)\r\n#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)\r\n#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)\r\n#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)\r\n#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */\r\n#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */\r\n#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */\r\n#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */\r\n\r\n/*******************  Bits definition for FLASH_CR register  ***********************/\r\n#define FLASH_CR_LOCK_Pos                    (0U)\r\n#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */\r\n#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */\r\n#define FLASH_CR_PG_Pos                      (1U)\r\n#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */\r\n#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */\r\n#define FLASH_CR_SER_Pos                     (2U)\r\n#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */\r\n#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */\r\n#define FLASH_CR_BER_Pos                     (3U)\r\n#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */\r\n#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */\r\n#define FLASH_CR_PSIZE_Pos                   (4U)\r\n#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */\r\n#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */\r\n#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */\r\n#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */\r\n#define FLASH_CR_FW_Pos                      (6U)\r\n#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */\r\n#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */\r\n#define FLASH_CR_START_Pos                   (7U)\r\n#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */\r\n#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */\r\n#define FLASH_CR_SNB_Pos                     (8U)\r\n#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */\r\n#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */\r\n#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */\r\n#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */\r\n#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */\r\n#define FLASH_CR_CRC_EN_Pos                  (15U)\r\n#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */\r\n#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */\r\n#define FLASH_CR_EOPIE_Pos                   (16U)\r\n#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */\r\n#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */\r\n#define FLASH_CR_WRPERRIE_Pos                (17U)\r\n#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */\r\n#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */\r\n#define FLASH_CR_PGSERRIE_Pos                (18U)\r\n#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */\r\n#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */\r\n#define FLASH_CR_STRBERRIE_Pos               (19U)\r\n#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */\r\n#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */\r\n#define FLASH_CR_INCERRIE_Pos                (21U)\r\n#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */\r\n#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */\r\n#define FLASH_CR_OPERRIE_Pos                 (22U)\r\n#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */\r\n#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */\r\n#define FLASH_CR_RDPERRIE_Pos                (23U)\r\n#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */\r\n#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */\r\n#define FLASH_CR_RDSERRIE_Pos                (24U)\r\n#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */\r\n#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */\r\n#define FLASH_CR_SNECCERRIE_Pos              (25U)\r\n#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */\r\n#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */\r\n#define FLASH_CR_DBECCERRIE_Pos              (26U)\r\n#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */\r\n#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */\r\n#define FLASH_CR_CRCENDIE_Pos                (27U)\r\n#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */\r\n#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */\r\n#define FLASH_CR_CRCRDERRIE_Pos              (28U)\r\n#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */\r\n#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */\r\n\r\n/*******************  Bits definition for FLASH_SR register  ***********************/\r\n#define FLASH_SR_BSY_Pos                     (0U)\r\n#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */\r\n#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */\r\n#define FLASH_SR_WBNE_Pos                    (1U)\r\n#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */\r\n#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */\r\n#define FLASH_SR_QW_Pos                      (2U)\r\n#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */\r\n#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */\r\n#define FLASH_SR_CRC_BUSY_Pos                (3U)\r\n#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */\r\n#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */\r\n#define FLASH_SR_EOP_Pos                     (16U)\r\n#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */\r\n#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */\r\n#define FLASH_SR_WRPERR_Pos                  (17U)\r\n#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */\r\n#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */\r\n#define FLASH_SR_PGSERR_Pos                  (18U)\r\n#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */\r\n#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */\r\n#define FLASH_SR_STRBERR_Pos                 (19U)\r\n#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */\r\n#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */\r\n#define FLASH_SR_INCERR_Pos                  (21U)\r\n#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */\r\n#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */\r\n#define FLASH_SR_OPERR_Pos                   (22U)\r\n#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */\r\n#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */\r\n#define FLASH_SR_RDPERR_Pos                  (23U)\r\n#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */\r\n#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */\r\n#define FLASH_SR_RDSERR_Pos                  (24U)\r\n#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */\r\n#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */\r\n#define FLASH_SR_SNECCERR_Pos                (25U)\r\n#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */\r\n#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */\r\n#define FLASH_SR_DBECCERR_Pos                (26U)\r\n#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */\r\n#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */\r\n#define FLASH_SR_CRCEND_Pos                  (27U)\r\n#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */\r\n#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */\r\n#define FLASH_SR_CRCRDERR_Pos                (28U)\r\n#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */\r\n#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */\r\n\r\n/*******************  Bits definition for FLASH_CCR register  *******************/\r\n#define FLASH_CCR_CLR_EOP_Pos                (16U)\r\n#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */\r\n#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */\r\n#define FLASH_CCR_CLR_WRPERR_Pos             (17U)\r\n#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */\r\n#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */\r\n#define FLASH_CCR_CLR_PGSERR_Pos             (18U)\r\n#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */\r\n#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */\r\n#define FLASH_CCR_CLR_STRBERR_Pos            (19U)\r\n#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */\r\n#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */\r\n#define FLASH_CCR_CLR_INCERR_Pos             (21U)\r\n#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */\r\n#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */\r\n#define FLASH_CCR_CLR_OPERR_Pos              (22U)\r\n#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */\r\n#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */\r\n#define FLASH_CCR_CLR_RDPERR_Pos             (23U)\r\n#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */\r\n#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */\r\n#define FLASH_CCR_CLR_RDSERR_Pos             (24U)\r\n#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */\r\n#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */\r\n#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)\r\n#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */\r\n#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */\r\n#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)\r\n#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */\r\n#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */\r\n#define FLASH_CCR_CLR_CRCEND_Pos             (27U)\r\n#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */\r\n#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */\r\n#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)\r\n#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */\r\n#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */\r\n\r\n/*******************  Bits definition for FLASH_OPTCR register  *******************/\r\n#define FLASH_OPTCR_OPTLOCK_Pos              (0U)\r\n#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */\r\n#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */\r\n#define FLASH_OPTCR_OPTSTART_Pos             (1U)\r\n#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */\r\n#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */\r\n#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)\r\n#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */\r\n#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */\r\n\r\n/*******************  Bits definition for FLASH_OPTSR register  ***************/\r\n#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)\r\n#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */\r\n#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */\r\n#define FLASH_OPTSR_BOR_LEV_Pos              (2U)\r\n#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */\r\n#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */\r\n#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */\r\n#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */\r\n#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)\r\n#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */\r\n#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */\r\n#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)\r\n#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */\r\n#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */\r\n#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)\r\n#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */\r\n#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */\r\n#define FLASH_OPTSR_RDP_Pos                  (8U)\r\n#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */\r\n#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */\r\n#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)\r\n#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */\r\n#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */\r\n#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)\r\n#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */\r\n#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */\r\n#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)\r\n#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */\r\n#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */\r\n#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */\r\n#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */\r\n#define FLASH_OPTSR_SECURITY_Pos             (21U)\r\n#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */\r\n#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */\r\n#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)\r\n#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */\r\n#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */\r\n#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)\r\n#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */\r\n#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */\r\n#define FLASH_OPTSR_IO_HSLV_Pos              (29U)\r\n#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */\r\n#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */\r\n#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)\r\n#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\r\n#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */\r\n\r\n/*******************  Bits definition for FLASH_OPTCCR register  *******************/\r\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)\r\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\r\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */\r\n\r\n/*******************  Bits definition for FLASH_PRAR register  *********************/\r\n#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)\r\n#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */\r\n#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */\r\n#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)\r\n#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */\r\n#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */\r\n#define FLASH_PRAR_DMEP_Pos                  (31U)\r\n#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */\r\n#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */\r\n\r\n/*******************  Bits definition for FLASH_SCAR register  *********************/\r\n#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)\r\n#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */\r\n#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */\r\n#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)\r\n#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */\r\n#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */\r\n#define FLASH_SCAR_DMES_Pos                  (31U)\r\n#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */\r\n#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */\r\n\r\n/*******************  Bits definition for FLASH_WPSN register  *********************/\r\n#define FLASH_WPSN_WRPSN_Pos                 (0U)\r\n#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */\r\n#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */\r\n\r\n/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/\r\n#define FLASH_BOOT_ADD0_Pos                  (0U)\r\n#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */\r\n#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */\r\n#define FLASH_BOOT_ADD1_Pos                  (16U)\r\n#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */\r\n#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */\r\n\r\n\r\n/*******************  Bits definition for FLASH_CRCCR register  ********************/\r\n#define FLASH_CRCCR_CRC_SECT_Pos             (0U)\r\n#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */\r\n#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */\r\n#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)\r\n#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */\r\n#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */\r\n#define FLASH_CRCCR_ADD_SECT_Pos             (9U)\r\n#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */\r\n#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */\r\n#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)\r\n#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */\r\n#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */\r\n#define FLASH_CRCCR_START_CRC_Pos            (16U)\r\n#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */\r\n#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */\r\n#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)\r\n#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */\r\n#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */\r\n#define FLASH_CRCCR_CRC_BURST_Pos            (20U)\r\n#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */\r\n#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */\r\n#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */\r\n#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */\r\n#define FLASH_CRCCR_ALL_BANK_Pos             (22U)\r\n#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */\r\n#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */\r\n\r\n/*******************  Bits definition for FLASH_CRCSADD register  ****************/\r\n#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)\r\n#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */\r\n\r\n/*******************  Bits definition for FLASH_CRCEADD register  ****************/\r\n#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)\r\n#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */\r\n\r\n/*******************  Bits definition for FLASH_CRCDATA register  ***************/\r\n#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)\r\n#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */\r\n#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */\r\n\r\n/*******************  Bits definition for FLASH_ECC_FA register  *******************/\r\n#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)\r\n#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */\r\n#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */\r\n\r\n/*******************  Bits definition for FLASH_OPTSR2 register  *******************/\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_Pos      (0U)\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_Msk      (0x3UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos) /*!< 0x00000003 */\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED          FLASH_OPTSR2_TCM_AXI_SHARED_Msk            /*!< TCM RAM shared */\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_0        (0x1UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos) /*!< 0x00000001 */\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_1        (0x2UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos) /*!< 0x00000002 */\r\n#define FLASH_OPTSR2_CPUFREQ_BOOST_Pos       (2U)\r\n#define FLASH_OPTSR2_CPUFREQ_BOOST_Msk       (0x1UL << FLASH_OPTSR2_CPUFREQ_BOOST_Pos) /*!< 0x00000004 */\r\n#define FLASH_OPTSR2_CPUFREQ_BOOST           FLASH_OPTSR2_CPUFREQ_BOOST_Msk            /*!< CPU frequency boost */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Filter Mathematical ACcelerator unit (FMAC)                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*****************  Bit definition for FMAC_X1BUFCFG register  ****************/\r\n#define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)\r\n#define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */\r\n#define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */\r\n#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)\r\n#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */\r\n#define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */\r\n#define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)\r\n#define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */\r\n#define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */\r\n/*****************  Bit definition for FMAC_X2BUFCFG register  ****************/\r\n#define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)\r\n#define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */\r\n#define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */\r\n#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)\r\n#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */\r\n#define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */\r\n/*****************  Bit definition for FMAC_YBUFCFG register  *****************/\r\n#define FMAC_YBUFCFG_Y_BASE_Pos       (0U)\r\n#define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */\r\n#define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */\r\n#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)\r\n#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */\r\n#define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */\r\n#define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)\r\n#define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */\r\n#define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */\r\n/******************  Bit definition for FMAC_PARAM register  ******************/\r\n#define FMAC_PARAM_P_Pos              (0U)\r\n#define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */\r\n#define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */\r\n#define FMAC_PARAM_Q_Pos              (8U)\r\n#define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */\r\n#define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */\r\n#define FMAC_PARAM_R_Pos              (16U)\r\n#define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */\r\n#define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */\r\n#define FMAC_PARAM_FUNC_Pos           (24U)\r\n#define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */\r\n#define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */\r\n#define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */\r\n#define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */\r\n#define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */\r\n#define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */\r\n#define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */\r\n#define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */\r\n#define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */\r\n#define FMAC_PARAM_START_Pos          (31U)\r\n#define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */\r\n#define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */\r\n/********************  Bit definition for FMAC_CR register  *******************/\r\n#define FMAC_CR_RIEN_Pos              (0U)\r\n#define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */\r\n#define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */\r\n#define FMAC_CR_WIEN_Pos              (1U)\r\n#define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */\r\n#define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */\r\n#define FMAC_CR_OVFLIEN_Pos           (2U)\r\n#define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */\r\n#define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */\r\n#define FMAC_CR_UNFLIEN_Pos           (3U)\r\n#define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */\r\n#define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */\r\n#define FMAC_CR_SATIEN_Pos            (4U)\r\n#define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */\r\n#define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */\r\n#define FMAC_CR_DMAREN_Pos            (8U)\r\n#define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */\r\n#define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */\r\n#define FMAC_CR_DMAWEN_Pos            (9U)\r\n#define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */\r\n#define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */\r\n#define FMAC_CR_CLIPEN_Pos            (15U)\r\n#define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */\r\n#define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */\r\n#define FMAC_CR_RESET_Pos             (16U)\r\n#define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */\r\n#define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */\r\n/*******************  Bit definition for FMAC_SR register  ********************/\r\n#define FMAC_SR_YEMPTY_Pos            (0U)\r\n#define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */\r\n#define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */\r\n#define FMAC_SR_X1FULL_Pos            (1U)\r\n#define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */\r\n#define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */\r\n#define FMAC_SR_OVFL_Pos              (8U)\r\n#define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */\r\n#define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */\r\n#define FMAC_SR_UNFL_Pos              (9U)\r\n#define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */\r\n#define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */\r\n#define FMAC_SR_SAT_Pos               (10U)\r\n#define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */\r\n#define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */\r\n/******************  Bit definition for FMAC_WDATA register  ******************/\r\n#define FMAC_WDATA_WDATA_Pos          (0U)\r\n#define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */\r\n#define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */\r\n/******************  Bit definition for FMACX_RDATA register  *****************/\r\n#define FMAC_RDATA_RDATA_Pos          (0U)\r\n#define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */\r\n#define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Flexible Memory Controller                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for FMC_BCR1 register  *******************/\r\n#define FMC_BCR1_CCLKEN_Pos        (20U)\r\n#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\r\n#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */\r\n#define FMC_BCR1_WFDIS_Pos         (21U)\r\n#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */\r\n#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */\r\n\r\n#define FMC_BCR1_BMAP_Pos          (24U)\r\n#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */\r\n#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */\r\n#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */\r\n#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */\r\n\r\n#define FMC_BCR1_FMCEN_Pos         (31U)\r\n#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */\r\n#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */\r\n/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/\r\n#define FMC_BCRx_MBKEN_Pos         (0U)\r\n#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */\r\n#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r\n#define FMC_BCRx_MUXEN_Pos         (1U)\r\n#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */\r\n#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r\n\r\n#define FMC_BCRx_MTYP_Pos          (2U)\r\n#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */\r\n#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r\n#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */\r\n#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */\r\n\r\n#define FMC_BCRx_MWID_Pos          (4U)\r\n#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */\r\n#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */\r\n#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */\r\n\r\n#define FMC_BCRx_FACCEN_Pos        (6U)\r\n#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */\r\n#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */\r\n#define FMC_BCRx_BURSTEN_Pos       (8U)\r\n#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */\r\n#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */\r\n#define FMC_BCRx_WAITPOL_Pos       (9U)\r\n#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */\r\n#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r\n#define FMC_BCRx_WAITCFG_Pos       (11U)\r\n#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */\r\n#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */\r\n#define FMC_BCRx_WREN_Pos          (12U)\r\n#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */\r\n#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */\r\n#define FMC_BCRx_WAITEN_Pos        (13U)\r\n#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */\r\n#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */\r\n#define FMC_BCRx_EXTMOD_Pos        (14U)\r\n#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */\r\n#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */\r\n#define FMC_BCRx_ASYNCWAIT_Pos     (15U)\r\n#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */\r\n#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r\n\r\n#define FMC_BCRx_CPSIZE_Pos        (16U)\r\n#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */\r\n#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */\r\n#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */\r\n#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */\r\n#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */\r\n\r\n#define FMC_BCRx_CBURSTRW_Pos      (19U)\r\n#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */\r\n#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/\r\n#define FMC_BTRx_ADDSET_Pos        (0U)\r\n#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */\r\n#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */\r\n#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */\r\n#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */\r\n#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */\r\n\r\n#define FMC_BTRx_ADDHLD_Pos        (4U)\r\n#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */\r\n#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r\n#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */\r\n#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */\r\n#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */\r\n#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */\r\n\r\n#define FMC_BTRx_DATAST_Pos        (8U)\r\n#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */\r\n#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */\r\n#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */\r\n#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */\r\n#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */\r\n#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */\r\n#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */\r\n#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */\r\n#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */\r\n\r\n#define FMC_BTRx_BUSTURN_Pos       (16U)\r\n#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */\r\n#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */\r\n#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */\r\n#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */\r\n#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */\r\n\r\n#define FMC_BTRx_CLKDIV_Pos        (20U)\r\n#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */\r\n#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */\r\n#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */\r\n#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */\r\n#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */\r\n\r\n#define FMC_BTRx_DATLAT_Pos        (24U)\r\n#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */\r\n#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\r\n#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */\r\n#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */\r\n#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */\r\n#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */\r\n\r\n#define FMC_BTRx_ACCMOD_Pos        (28U)\r\n#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */\r\n#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */\r\n#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/\r\n#define FMC_BWTRx_ADDSET_Pos       (0U)\r\n#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */\r\n#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */\r\n#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */\r\n#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */\r\n#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */\r\n\r\n#define FMC_BWTRx_ADDHLD_Pos       (4U)\r\n#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */\r\n#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */\r\n#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */\r\n#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */\r\n#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */\r\n\r\n#define FMC_BWTRx_DATAST_Pos       (8U)\r\n#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */\r\n#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */\r\n#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */\r\n#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */\r\n#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */\r\n#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */\r\n#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */\r\n#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */\r\n#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */\r\n\r\n#define FMC_BWTRx_BUSTURN_Pos      (16U)\r\n#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */\r\n#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */\r\n#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */\r\n#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */\r\n#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */\r\n\r\n#define FMC_BWTRx_ACCMOD_Pos       (28U)\r\n#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */\r\n#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */\r\n#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_PCR register  *******************/\r\n#define FMC_PCR_PWAITEN_Pos        (1U)\r\n#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\r\n#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\r\n#define FMC_PCR_PBKEN_Pos          (2U)\r\n#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\r\n#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */\r\n\r\n#define FMC_PCR_PWID_Pos           (4U)\r\n#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\r\n#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\r\n#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */\r\n#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */\r\n\r\n#define FMC_PCR_ECCEN_Pos          (6U)\r\n#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\r\n#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\r\n\r\n#define FMC_PCR_TCLR_Pos           (9U)\r\n#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\r\n#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\r\n#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */\r\n#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */\r\n#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */\r\n#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */\r\n\r\n#define FMC_PCR_TAR_Pos            (13U)\r\n#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\r\n#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\r\n#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */\r\n#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */\r\n#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */\r\n#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */\r\n\r\n#define FMC_PCR_ECCPS_Pos          (17U)\r\n#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\r\n#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */\r\n#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */\r\n#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */\r\n#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */\r\n\r\n/*******************  Bit definition for FMC_SR register  *******************/\r\n#define FMC_SR_IRS_Pos             (0U)\r\n#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\r\n#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\r\n#define FMC_SR_ILS_Pos             (1U)\r\n#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\r\n#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\r\n#define FMC_SR_IFS_Pos             (2U)\r\n#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\r\n#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\r\n#define FMC_SR_IREN_Pos            (3U)\r\n#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\r\n#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\r\n#define FMC_SR_ILEN_Pos            (4U)\r\n#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\r\n#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\r\n#define FMC_SR_IFEN_Pos            (5U)\r\n#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\r\n#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\r\n#define FMC_SR_FEMPT_Pos           (6U)\r\n#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\r\n#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\r\n\r\n/******************  Bit definition for FMC_PMEM register  ******************/\r\n#define FMC_PMEM_MEMSET_Pos       (0U)\r\n#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */\r\n#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */\r\n#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */\r\n#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */\r\n#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */\r\n#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */\r\n#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */\r\n#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */\r\n#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */\r\n#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */\r\n\r\n#define FMC_PMEM_MEMWAIT_Pos      (8U)\r\n#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */\r\n#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */\r\n#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */\r\n#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */\r\n#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */\r\n#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */\r\n#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */\r\n#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */\r\n#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */\r\n#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */\r\n\r\n#define FMC_PMEM_MEMHOLD_Pos      (16U)\r\n#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */\r\n#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */\r\n#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */\r\n#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */\r\n#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */\r\n#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */\r\n#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */\r\n#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */\r\n#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */\r\n#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */\r\n\r\n#define FMC_PMEM_MEMHIZ_Pos       (24U)\r\n#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */\r\n#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\r\n#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */\r\n#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */\r\n#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */\r\n#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */\r\n#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */\r\n#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */\r\n#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */\r\n#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for FMC_PATT register  ******************/\r\n#define FMC_PATT_ATTSET_Pos       (0U)\r\n#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */\r\n#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */\r\n#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */\r\n#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */\r\n#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */\r\n#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */\r\n#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */\r\n#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */\r\n#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */\r\n#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */\r\n\r\n#define FMC_PATT_ATTWAIT_Pos      (8U)\r\n#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */\r\n#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\r\n#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */\r\n#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */\r\n#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */\r\n#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */\r\n#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */\r\n#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */\r\n#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */\r\n#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */\r\n\r\n#define FMC_PATT_ATTHOLD_Pos      (16U)\r\n#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */\r\n#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\r\n#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */\r\n#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */\r\n#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */\r\n#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */\r\n#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */\r\n#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */\r\n#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */\r\n#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */\r\n\r\n#define FMC_PATT_ATTHIZ_Pos       (24U)\r\n#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */\r\n#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\r\n#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */\r\n#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */\r\n#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */\r\n#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */\r\n#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */\r\n#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */\r\n#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */\r\n#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for FMC_ECCR3 register  ******************/\r\n#define FMC_ECCR3_ECC3_Pos         (0U)\r\n#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */\r\n#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */\r\n\r\n/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/\r\n#define FMC_SDCRx_NC_Pos           (0U)\r\n#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */\r\n#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */\r\n#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */\r\n#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */\r\n\r\n#define FMC_SDCRx_NR_Pos           (2U)\r\n#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */\r\n#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */\r\n#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */\r\n\r\n#define FMC_SDCRx_MWID_Pos         (4U)\r\n#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */\r\n#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */\r\n\r\n#define FMC_SDCRx_NB_Pos           (6U)\r\n#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */\r\n#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */\r\n\r\n#define FMC_SDCRx_CAS_Pos          (7U)\r\n#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */\r\n#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */\r\n#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */\r\n#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */\r\n\r\n#define FMC_SDCRx_WP_Pos           (9U)\r\n#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */\r\n#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */\r\n\r\n#define FMC_SDCRx_SDCLK_Pos        (10U)\r\n#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */\r\n#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */\r\n#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */\r\n#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */\r\n\r\n#define FMC_SDCRx_RBURST_Pos       (12U)\r\n#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */\r\n#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */\r\n\r\n#define FMC_SDCRx_RPIPE_Pos        (13U)\r\n#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */\r\n#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */\r\n#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */\r\n#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */\r\n\r\n/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/\r\n#define FMC_SDTRx_TMRD_Pos         (0U)\r\n#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */\r\n#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */\r\n#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */\r\n#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */\r\n\r\n#define FMC_SDTRx_TXSR_Pos         (4U)\r\n#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */\r\n#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */\r\n#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */\r\n\r\n#define FMC_SDTRx_TRAS_Pos         (8U)\r\n#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */\r\n#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */\r\n#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */\r\n#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */\r\n#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */\r\n#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */\r\n\r\n#define FMC_SDTRx_TRC_Pos          (12U)\r\n#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */\r\n#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */\r\n#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */\r\n#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */\r\n#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */\r\n\r\n#define FMC_SDTRx_TWR_Pos          (16U)\r\n#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */\r\n#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */\r\n#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */\r\n#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */\r\n#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */\r\n\r\n#define FMC_SDTRx_TRP_Pos          (20U)\r\n#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */\r\n#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */\r\n#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */\r\n#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */\r\n#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */\r\n\r\n#define FMC_SDTRx_TRCD_Pos         (24U)\r\n#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */\r\n#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */\r\n#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */\r\n#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */\r\n#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */\r\n\r\n/******************  Bit definition for FMC_SDCMR register  ******************/\r\n#define FMC_SDCMR_MODE_Pos         (0U)\r\n#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */\r\n#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */\r\n#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */\r\n\r\n#define FMC_SDCMR_CTB2_Pos         (3U)\r\n#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */\r\n#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */\r\n\r\n#define FMC_SDCMR_CTB1_Pos         (4U)\r\n#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */\r\n#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */\r\n\r\n#define FMC_SDCMR_NRFS_Pos         (5U)\r\n#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */\r\n#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */\r\n#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */\r\n#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */\r\n\r\n#define FMC_SDCMR_MRD_Pos          (9U)\r\n#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */\r\n#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */\r\n\r\n/******************  Bit definition for FMC_SDRTR register  ******************/\r\n#define FMC_SDRTR_CRE_Pos          (0U)\r\n#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */\r\n\r\n#define FMC_SDRTR_COUNT_Pos        (1U)\r\n#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */\r\n#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */\r\n\r\n#define FMC_SDRTR_REIE_Pos         (14U)\r\n#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */\r\n#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */\r\n\r\n/******************  Bit definition for FMC_SDSR register  ******************/\r\n#define FMC_SDSR_RE_Pos            (0U)\r\n#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */\r\n#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */\r\n\r\n#define FMC_SDSR_MODES1_Pos        (1U)\r\n#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */\r\n#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */\r\n#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */\r\n#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */\r\n\r\n#define FMC_SDSR_MODES2_Pos        (3U)\r\n#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */\r\n#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */\r\n#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */\r\n#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            General Purpose I/O                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bits definition for GPIO_MODER register  *****************/\r\n#define GPIO_MODER_MODE0_Pos           (0U)\r\n#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */\r\n#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\r\n#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */\r\n\r\n#define GPIO_MODER_MODE1_Pos           (2U)\r\n#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */\r\n#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\r\n#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */\r\n#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */\r\n\r\n#define GPIO_MODER_MODE2_Pos           (4U)\r\n#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */\r\n#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\r\n#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */\r\n#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */\r\n\r\n#define GPIO_MODER_MODE3_Pos           (6U)\r\n#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */\r\n#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\r\n#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */\r\n#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */\r\n\r\n#define GPIO_MODER_MODE4_Pos           (8U)\r\n#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */\r\n#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\r\n#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */\r\n#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */\r\n\r\n#define GPIO_MODER_MODE5_Pos           (10U)\r\n#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */\r\n#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\r\n#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */\r\n#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */\r\n\r\n#define GPIO_MODER_MODE6_Pos           (12U)\r\n#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */\r\n#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\r\n#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */\r\n#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */\r\n\r\n#define GPIO_MODER_MODE7_Pos           (14U)\r\n#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */\r\n#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\r\n#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */\r\n#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */\r\n\r\n#define GPIO_MODER_MODE8_Pos           (16U)\r\n#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */\r\n#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\r\n#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */\r\n#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */\r\n\r\n#define GPIO_MODER_MODE9_Pos           (18U)\r\n#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */\r\n#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\r\n#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */\r\n#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */\r\n\r\n#define GPIO_MODER_MODE10_Pos          (20U)\r\n#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */\r\n#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\r\n#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */\r\n#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */\r\n\r\n#define GPIO_MODER_MODE11_Pos          (22U)\r\n#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */\r\n#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\r\n#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */\r\n#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */\r\n\r\n#define GPIO_MODER_MODE12_Pos          (24U)\r\n#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */\r\n#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\r\n#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */\r\n#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */\r\n\r\n#define GPIO_MODER_MODE13_Pos          (26U)\r\n#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */\r\n#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\r\n#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */\r\n#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */\r\n\r\n#define GPIO_MODER_MODE14_Pos          (28U)\r\n#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */\r\n#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\r\n#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */\r\n#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */\r\n\r\n#define GPIO_MODER_MODE15_Pos          (30U)\r\n#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */\r\n#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\r\n#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */\r\n#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_OTYPER register  ****************/\r\n#define GPIO_OTYPER_OT0_Pos            (0U)\r\n#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\r\n#define GPIO_OTYPER_OT1_Pos            (1U)\r\n#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */\r\n#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\r\n#define GPIO_OTYPER_OT2_Pos            (2U)\r\n#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */\r\n#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\r\n#define GPIO_OTYPER_OT3_Pos            (3U)\r\n#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */\r\n#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\r\n#define GPIO_OTYPER_OT4_Pos            (4U)\r\n#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */\r\n#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\r\n#define GPIO_OTYPER_OT5_Pos            (5U)\r\n#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */\r\n#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\r\n#define GPIO_OTYPER_OT6_Pos            (6U)\r\n#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */\r\n#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\r\n#define GPIO_OTYPER_OT7_Pos            (7U)\r\n#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */\r\n#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\r\n#define GPIO_OTYPER_OT8_Pos            (8U)\r\n#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */\r\n#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\r\n#define GPIO_OTYPER_OT9_Pos            (9U)\r\n#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */\r\n#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\r\n#define GPIO_OTYPER_OT10_Pos           (10U)\r\n#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */\r\n#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\r\n#define GPIO_OTYPER_OT11_Pos           (11U)\r\n#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */\r\n#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\r\n#define GPIO_OTYPER_OT12_Pos           (12U)\r\n#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */\r\n#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\r\n#define GPIO_OTYPER_OT13_Pos           (13U)\r\n#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */\r\n#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\r\n#define GPIO_OTYPER_OT14_Pos           (14U)\r\n#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */\r\n#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\r\n#define GPIO_OTYPER_OT15_Pos           (15U)\r\n#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */\r\n#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\r\n\r\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r\n#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\r\n#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */\r\n#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\r\n#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */\r\n#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\r\n#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */\r\n#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\r\n#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */\r\n#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\r\n#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */\r\n#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\r\n#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */\r\n#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\r\n#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */\r\n#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\r\n#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */\r\n#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\r\n#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */\r\n#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\r\n#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */\r\n#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\r\n#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */\r\n#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\r\n#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */\r\n#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\r\n#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */\r\n#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\r\n#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */\r\n#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\r\n#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */\r\n#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\r\n#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */\r\n#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\r\n#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */\r\n#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\r\n#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */\r\n#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\r\n#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */\r\n#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\r\n#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */\r\n#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\r\n#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */\r\n#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\r\n#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */\r\n#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\r\n#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */\r\n#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\r\n#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */\r\n#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\r\n#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */\r\n#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\r\n#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */\r\n#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\r\n#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */\r\n#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\r\n#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */\r\n#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\r\n#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */\r\n#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\r\n#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */\r\n#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\r\n#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */\r\n#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\r\n#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */\r\n#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_PUPDR register  *****************/\r\n#define GPIO_PUPDR_PUPD0_Pos           (0U)\r\n#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */\r\n#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\r\n#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */\r\n\r\n#define GPIO_PUPDR_PUPD1_Pos           (2U)\r\n#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */\r\n#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\r\n#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */\r\n#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */\r\n\r\n#define GPIO_PUPDR_PUPD2_Pos           (4U)\r\n#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */\r\n#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\r\n#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */\r\n#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */\r\n\r\n#define GPIO_PUPDR_PUPD3_Pos           (6U)\r\n#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */\r\n#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\r\n#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */\r\n#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */\r\n\r\n#define GPIO_PUPDR_PUPD4_Pos           (8U)\r\n#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */\r\n#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\r\n#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */\r\n#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */\r\n\r\n#define GPIO_PUPDR_PUPD5_Pos           (10U)\r\n#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */\r\n#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\r\n#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */\r\n#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */\r\n\r\n#define GPIO_PUPDR_PUPD6_Pos           (12U)\r\n#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */\r\n#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\r\n#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */\r\n#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */\r\n\r\n#define GPIO_PUPDR_PUPD7_Pos           (14U)\r\n#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */\r\n#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\r\n#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */\r\n#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */\r\n\r\n#define GPIO_PUPDR_PUPD8_Pos           (16U)\r\n#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */\r\n#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\r\n#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */\r\n#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */\r\n\r\n#define GPIO_PUPDR_PUPD9_Pos           (18U)\r\n#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */\r\n#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\r\n#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */\r\n#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */\r\n\r\n#define GPIO_PUPDR_PUPD10_Pos          (20U)\r\n#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */\r\n#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\r\n#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */\r\n#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */\r\n\r\n#define GPIO_PUPDR_PUPD11_Pos          (22U)\r\n#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */\r\n#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\r\n#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */\r\n#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */\r\n\r\n#define GPIO_PUPDR_PUPD12_Pos          (24U)\r\n#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */\r\n#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\r\n#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */\r\n#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */\r\n\r\n#define GPIO_PUPDR_PUPD13_Pos          (26U)\r\n#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */\r\n#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\r\n#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */\r\n#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */\r\n\r\n#define GPIO_PUPDR_PUPD14_Pos          (28U)\r\n#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */\r\n#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\r\n#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */\r\n#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */\r\n\r\n#define GPIO_PUPDR_PUPD15_Pos          (30U)\r\n#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */\r\n#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\r\n#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */\r\n#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_IDR register  *******************/\r\n#define GPIO_IDR_ID0_Pos               (0U)\r\n#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */\r\n#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\r\n#define GPIO_IDR_ID1_Pos               (1U)\r\n#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */\r\n#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\r\n#define GPIO_IDR_ID2_Pos               (2U)\r\n#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */\r\n#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\r\n#define GPIO_IDR_ID3_Pos               (3U)\r\n#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */\r\n#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\r\n#define GPIO_IDR_ID4_Pos               (4U)\r\n#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */\r\n#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\r\n#define GPIO_IDR_ID5_Pos               (5U)\r\n#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */\r\n#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\r\n#define GPIO_IDR_ID6_Pos               (6U)\r\n#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */\r\n#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\r\n#define GPIO_IDR_ID7_Pos               (7U)\r\n#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */\r\n#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\r\n#define GPIO_IDR_ID8_Pos               (8U)\r\n#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */\r\n#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\r\n#define GPIO_IDR_ID9_Pos               (9U)\r\n#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */\r\n#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\r\n#define GPIO_IDR_ID10_Pos              (10U)\r\n#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */\r\n#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\r\n#define GPIO_IDR_ID11_Pos              (11U)\r\n#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */\r\n#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\r\n#define GPIO_IDR_ID12_Pos              (12U)\r\n#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */\r\n#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\r\n#define GPIO_IDR_ID13_Pos              (13U)\r\n#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */\r\n#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\r\n#define GPIO_IDR_ID14_Pos              (14U)\r\n#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */\r\n#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\r\n#define GPIO_IDR_ID15_Pos              (15U)\r\n#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */\r\n#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\r\n\r\n/******************  Bits definition for GPIO_ODR register  *******************/\r\n#define GPIO_ODR_OD0_Pos               (0U)\r\n#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */\r\n#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\r\n#define GPIO_ODR_OD1_Pos               (1U)\r\n#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */\r\n#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\r\n#define GPIO_ODR_OD2_Pos               (2U)\r\n#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */\r\n#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\r\n#define GPIO_ODR_OD3_Pos               (3U)\r\n#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */\r\n#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\r\n#define GPIO_ODR_OD4_Pos               (4U)\r\n#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */\r\n#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\r\n#define GPIO_ODR_OD5_Pos               (5U)\r\n#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */\r\n#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\r\n#define GPIO_ODR_OD6_Pos               (6U)\r\n#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */\r\n#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\r\n#define GPIO_ODR_OD7_Pos               (7U)\r\n#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */\r\n#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\r\n#define GPIO_ODR_OD8_Pos               (8U)\r\n#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */\r\n#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\r\n#define GPIO_ODR_OD9_Pos               (9U)\r\n#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */\r\n#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\r\n#define GPIO_ODR_OD10_Pos              (10U)\r\n#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */\r\n#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\r\n#define GPIO_ODR_OD11_Pos              (11U)\r\n#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */\r\n#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\r\n#define GPIO_ODR_OD12_Pos              (12U)\r\n#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */\r\n#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\r\n#define GPIO_ODR_OD13_Pos              (13U)\r\n#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */\r\n#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\r\n#define GPIO_ODR_OD14_Pos              (14U)\r\n#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */\r\n#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\r\n#define GPIO_ODR_OD15_Pos              (15U)\r\n#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */\r\n#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\r\n\r\n/******************  Bits definition for GPIO_BSRR register  ******************/\r\n#define GPIO_BSRR_BS0_Pos              (0U)\r\n#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */\r\n#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\r\n#define GPIO_BSRR_BS1_Pos              (1U)\r\n#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */\r\n#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\r\n#define GPIO_BSRR_BS2_Pos              (2U)\r\n#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */\r\n#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\r\n#define GPIO_BSRR_BS3_Pos              (3U)\r\n#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */\r\n#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\r\n#define GPIO_BSRR_BS4_Pos              (4U)\r\n#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */\r\n#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\r\n#define GPIO_BSRR_BS5_Pos              (5U)\r\n#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */\r\n#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\r\n#define GPIO_BSRR_BS6_Pos              (6U)\r\n#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */\r\n#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\r\n#define GPIO_BSRR_BS7_Pos              (7U)\r\n#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */\r\n#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\r\n#define GPIO_BSRR_BS8_Pos              (8U)\r\n#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */\r\n#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\r\n#define GPIO_BSRR_BS9_Pos              (9U)\r\n#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */\r\n#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\r\n#define GPIO_BSRR_BS10_Pos             (10U)\r\n#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */\r\n#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\r\n#define GPIO_BSRR_BS11_Pos             (11U)\r\n#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */\r\n#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\r\n#define GPIO_BSRR_BS12_Pos             (12U)\r\n#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */\r\n#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\r\n#define GPIO_BSRR_BS13_Pos             (13U)\r\n#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */\r\n#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\r\n#define GPIO_BSRR_BS14_Pos             (14U)\r\n#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */\r\n#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\r\n#define GPIO_BSRR_BS15_Pos             (15U)\r\n#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */\r\n#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\r\n#define GPIO_BSRR_BR0_Pos              (16U)\r\n#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */\r\n#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\r\n#define GPIO_BSRR_BR1_Pos              (17U)\r\n#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */\r\n#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\r\n#define GPIO_BSRR_BR2_Pos              (18U)\r\n#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */\r\n#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\r\n#define GPIO_BSRR_BR3_Pos              (19U)\r\n#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */\r\n#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\r\n#define GPIO_BSRR_BR4_Pos              (20U)\r\n#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */\r\n#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\r\n#define GPIO_BSRR_BR5_Pos              (21U)\r\n#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */\r\n#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\r\n#define GPIO_BSRR_BR6_Pos              (22U)\r\n#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */\r\n#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\r\n#define GPIO_BSRR_BR7_Pos              (23U)\r\n#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */\r\n#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\r\n#define GPIO_BSRR_BR8_Pos              (24U)\r\n#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */\r\n#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\r\n#define GPIO_BSRR_BR9_Pos              (25U)\r\n#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */\r\n#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\r\n#define GPIO_BSRR_BR10_Pos             (26U)\r\n#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */\r\n#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\r\n#define GPIO_BSRR_BR11_Pos             (27U)\r\n#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */\r\n#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\r\n#define GPIO_BSRR_BR12_Pos             (28U)\r\n#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */\r\n#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\r\n#define GPIO_BSRR_BR13_Pos             (29U)\r\n#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */\r\n#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\r\n#define GPIO_BSRR_BR14_Pos             (30U)\r\n#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */\r\n#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\r\n#define GPIO_BSRR_BR15_Pos             (31U)\r\n#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */\r\n#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\r\n\r\n/****************** Bit definition for GPIO_LCKR register *********************/\r\n#define GPIO_LCKR_LCK0_Pos             (0U)\r\n#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */\r\n#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\r\n#define GPIO_LCKR_LCK1_Pos             (1U)\r\n#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */\r\n#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\r\n#define GPIO_LCKR_LCK2_Pos             (2U)\r\n#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */\r\n#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\r\n#define GPIO_LCKR_LCK3_Pos             (3U)\r\n#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */\r\n#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\r\n#define GPIO_LCKR_LCK4_Pos             (4U)\r\n#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */\r\n#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\r\n#define GPIO_LCKR_LCK5_Pos             (5U)\r\n#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */\r\n#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\r\n#define GPIO_LCKR_LCK6_Pos             (6U)\r\n#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */\r\n#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\r\n#define GPIO_LCKR_LCK7_Pos             (7U)\r\n#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */\r\n#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\r\n#define GPIO_LCKR_LCK8_Pos             (8U)\r\n#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */\r\n#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\r\n#define GPIO_LCKR_LCK9_Pos             (9U)\r\n#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */\r\n#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\r\n#define GPIO_LCKR_LCK10_Pos            (10U)\r\n#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */\r\n#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\r\n#define GPIO_LCKR_LCK11_Pos            (11U)\r\n#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */\r\n#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\r\n#define GPIO_LCKR_LCK12_Pos            (12U)\r\n#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */\r\n#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\r\n#define GPIO_LCKR_LCK13_Pos            (13U)\r\n#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */\r\n#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\r\n#define GPIO_LCKR_LCK14_Pos            (14U)\r\n#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */\r\n#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\r\n#define GPIO_LCKR_LCK15_Pos            (15U)\r\n#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */\r\n#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\r\n#define GPIO_LCKR_LCKK_Pos             (16U)\r\n#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */\r\n#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\r\n\r\n/****************** Bit definition for GPIO_AFRL register  ********************/\r\n#define GPIO_AFRL_AFSEL0_Pos           (0U)\r\n#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */\r\n#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\r\n#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */\r\n#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */\r\n#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */\r\n#define GPIO_AFRL_AFSEL1_Pos           (4U)\r\n#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */\r\n#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\r\n#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */\r\n#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */\r\n#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */\r\n#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */\r\n#define GPIO_AFRL_AFSEL2_Pos           (8U)\r\n#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */\r\n#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\r\n#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */\r\n#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */\r\n#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */\r\n#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */\r\n#define GPIO_AFRL_AFSEL3_Pos           (12U)\r\n#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */\r\n#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\r\n#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */\r\n#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */\r\n#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */\r\n#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */\r\n#define GPIO_AFRL_AFSEL4_Pos           (16U)\r\n#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */\r\n#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\r\n#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */\r\n#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */\r\n#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */\r\n#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */\r\n#define GPIO_AFRL_AFSEL5_Pos           (20U)\r\n#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */\r\n#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\r\n#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */\r\n#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */\r\n#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */\r\n#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */\r\n#define GPIO_AFRL_AFSEL6_Pos           (24U)\r\n#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */\r\n#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\r\n#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */\r\n#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */\r\n#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */\r\n#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */\r\n#define GPIO_AFRL_AFSEL7_Pos           (28U)\r\n#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */\r\n#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\r\n#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */\r\n#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */\r\n#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */\r\n#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */\r\n\r\n/* Legacy defines */\r\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\r\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\r\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\r\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\r\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\r\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\r\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\r\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\r\n\r\n/****************** Bit definition for GPIO_AFRH register  ********************/\r\n#define GPIO_AFRH_AFSEL8_Pos           (0U)\r\n#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */\r\n#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\r\n#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */\r\n#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */\r\n#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */\r\n#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */\r\n#define GPIO_AFRH_AFSEL9_Pos           (4U)\r\n#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */\r\n#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\r\n#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */\r\n#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */\r\n#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */\r\n#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */\r\n#define GPIO_AFRH_AFSEL10_Pos          (8U)\r\n#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */\r\n#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\r\n#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */\r\n#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */\r\n#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */\r\n#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */\r\n#define GPIO_AFRH_AFSEL11_Pos          (12U)\r\n#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */\r\n#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\r\n#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */\r\n#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */\r\n#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */\r\n#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */\r\n#define GPIO_AFRH_AFSEL12_Pos          (16U)\r\n#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */\r\n#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\r\n#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */\r\n#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */\r\n#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */\r\n#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */\r\n#define GPIO_AFRH_AFSEL13_Pos          (20U)\r\n#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */\r\n#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\r\n#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */\r\n#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */\r\n#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */\r\n#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */\r\n#define GPIO_AFRH_AFSEL14_Pos          (24U)\r\n#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */\r\n#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\r\n#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */\r\n#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */\r\n#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */\r\n#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */\r\n#define GPIO_AFRH_AFSEL15_Pos          (28U)\r\n#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */\r\n#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\r\n#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */\r\n#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */\r\n#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */\r\n#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */\r\n\r\n/* Legacy defines */\r\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\r\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\r\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\r\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\r\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\r\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\r\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\r\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        HSEM HW Semaphore                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for HSEM_R register  ********************/\r\n#define HSEM_R_PROCID_Pos         (0U)\r\n#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */\r\n#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */\r\n#define HSEM_R_COREID_Pos         (8U)\r\n#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */\r\n#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */\r\n#define HSEM_R_LOCK_Pos           (31U)\r\n#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */\r\n#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */\r\n\r\n/********************  Bit definition for HSEM_RLR register  ******************/\r\n#define HSEM_RLR_PROCID_Pos       (0U)\r\n#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */\r\n#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */\r\n#define HSEM_RLR_COREID_Pos       (8U)\r\n#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */\r\n#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */\r\n#define HSEM_RLR_LOCK_Pos         (31U)\r\n#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */\r\n#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */\r\n\r\n/********************  Bit definition for HSEM_C1IER register  *****************/\r\n#define HSEM_C1IER_ISE0_Pos       (0U)\r\n#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */\r\n#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE1_Pos       (1U)\r\n#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */\r\n#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE2_Pos       (2U)\r\n#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */\r\n#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE3_Pos       (3U)\r\n#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */\r\n#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE4_Pos       (4U)\r\n#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */\r\n#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE5_Pos       (5U)\r\n#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */\r\n#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE6_Pos       (6U)\r\n#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */\r\n#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE7_Pos       (7U)\r\n#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */\r\n#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE8_Pos       (8U)\r\n#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */\r\n#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE9_Pos       (9U)\r\n#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */\r\n#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE10_Pos      (10U)\r\n#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */\r\n#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE11_Pos      (11U)\r\n#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */\r\n#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE12_Pos      (12U)\r\n#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */\r\n#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE13_Pos      (13U)\r\n#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */\r\n#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE14_Pos      (14U)\r\n#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */\r\n#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE15_Pos      (15U)\r\n#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */\r\n#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE16_Pos      (16U)\r\n#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */\r\n#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE17_Pos      (17U)\r\n#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */\r\n#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE18_Pos      (18U)\r\n#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */\r\n#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE19_Pos      (19U)\r\n#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */\r\n#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE20_Pos      (20U)\r\n#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */\r\n#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE21_Pos      (21U)\r\n#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */\r\n#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE22_Pos      (22U)\r\n#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */\r\n#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE23_Pos      (23U)\r\n#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */\r\n#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE24_Pos      (24U)\r\n#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */\r\n#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE25_Pos      (25U)\r\n#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */\r\n#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE26_Pos      (26U)\r\n#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */\r\n#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE27_Pos      (27U)\r\n#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */\r\n#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE28_Pos      (28U)\r\n#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */\r\n#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE29_Pos      (29U)\r\n#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */\r\n#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE30_Pos      (30U)\r\n#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */\r\n#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE31_Pos      (31U)\r\n#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */\r\n#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */\r\n\r\n/********************  Bit definition for HSEM_C1ICR register  *****************/\r\n#define HSEM_C1ICR_ISC0_Pos       (0U)\r\n#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */\r\n#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC1_Pos       (1U)\r\n#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */\r\n#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC2_Pos       (2U)\r\n#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */\r\n#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC3_Pos       (3U)\r\n#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */\r\n#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC4_Pos       (4U)\r\n#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */\r\n#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC5_Pos       (5U)\r\n#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */\r\n#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC6_Pos       (6U)\r\n#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */\r\n#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC7_Pos       (7U)\r\n#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */\r\n#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC8_Pos       (8U)\r\n#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */\r\n#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC9_Pos       (9U)\r\n#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */\r\n#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC10_Pos      (10U)\r\n#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */\r\n#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC11_Pos      (11U)\r\n#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */\r\n#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC12_Pos      (12U)\r\n#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */\r\n#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC13_Pos      (13U)\r\n#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */\r\n#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC14_Pos      (14U)\r\n#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */\r\n#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC15_Pos      (15U)\r\n#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */\r\n#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC16_Pos      (16U)\r\n#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */\r\n#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC17_Pos      (17U)\r\n#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */\r\n#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC18_Pos      (18U)\r\n#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */\r\n#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC19_Pos      (19U)\r\n#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */\r\n#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC20_Pos      (20U)\r\n#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */\r\n#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC21_Pos      (21U)\r\n#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */\r\n#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC22_Pos      (22U)\r\n#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */\r\n#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC23_Pos      (23U)\r\n#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */\r\n#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC24_Pos      (24U)\r\n#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */\r\n#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC25_Pos      (25U)\r\n#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */\r\n#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC26_Pos      (26U)\r\n#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */\r\n#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC27_Pos      (27U)\r\n#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */\r\n#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC28_Pos      (28U)\r\n#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */\r\n#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC29_Pos      (29U)\r\n#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */\r\n#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC30_Pos      (30U)\r\n#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */\r\n#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC31_Pos      (31U)\r\n#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */\r\n#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */\r\n\r\n/********************  Bit definition for HSEM_C1ISR register  *****************/\r\n#define HSEM_C1ISR_ISF0_Pos       (0U)\r\n#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */\r\n#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF1_Pos       (1U)\r\n#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */\r\n#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF2_Pos       (2U)\r\n#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */\r\n#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF3_Pos       (3U)\r\n#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */\r\n#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF4_Pos       (4U)\r\n#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */\r\n#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF5_Pos       (5U)\r\n#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */\r\n#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF6_Pos       (6U)\r\n#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */\r\n#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF7_Pos       (7U)\r\n#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */\r\n#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF8_Pos       (8U)\r\n#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */\r\n#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF9_Pos       (9U)\r\n#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */\r\n#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF10_Pos      (10U)\r\n#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */\r\n#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF11_Pos      (11U)\r\n#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */\r\n#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF12_Pos      (12U)\r\n#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */\r\n#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF13_Pos      (13U)\r\n#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */\r\n#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF14_Pos      (14U)\r\n#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */\r\n#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF15_Pos      (15U)\r\n#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */\r\n#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF16_Pos      (16U)\r\n#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */\r\n#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF17_Pos      (17U)\r\n#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */\r\n#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF18_Pos      (18U)\r\n#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */\r\n#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF19_Pos      (19U)\r\n#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */\r\n#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF20_Pos      (20U)\r\n#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */\r\n#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF21_Pos      (21U)\r\n#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */\r\n#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF22_Pos      (22U)\r\n#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */\r\n#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF23_Pos      (23U)\r\n#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */\r\n#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF24_Pos      (24U)\r\n#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */\r\n#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF25_Pos      (25U)\r\n#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */\r\n#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF26_Pos      (26U)\r\n#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */\r\n#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF27_Pos      (27U)\r\n#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */\r\n#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF28_Pos      (28U)\r\n#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */\r\n#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF29_Pos      (29U)\r\n#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */\r\n#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF30_Pos      (30U)\r\n#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */\r\n#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF31_Pos      (31U)\r\n#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */\r\n#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */\r\n\r\n/********************  Bit definition for HSEM_C1MISR register  *****************/\r\n#define HSEM_C1MISR_MISF0_Pos     (0U)\r\n#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */\r\n#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF1_Pos     (1U)\r\n#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */\r\n#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF2_Pos     (2U)\r\n#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */\r\n#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF3_Pos     (3U)\r\n#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */\r\n#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF4_Pos     (4U)\r\n#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */\r\n#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF5_Pos     (5U)\r\n#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */\r\n#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF6_Pos     (6U)\r\n#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */\r\n#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF7_Pos     (7U)\r\n#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */\r\n#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF8_Pos     (8U)\r\n#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */\r\n#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF9_Pos     (9U)\r\n#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */\r\n#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF10_Pos    (10U)\r\n#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */\r\n#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF11_Pos    (11U)\r\n#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */\r\n#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF12_Pos    (12U)\r\n#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */\r\n#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF13_Pos    (13U)\r\n#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */\r\n#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF14_Pos    (14U)\r\n#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */\r\n#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF15_Pos    (15U)\r\n#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */\r\n#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF16_Pos    (16U)\r\n#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */\r\n#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF17_Pos    (17U)\r\n#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */\r\n#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF18_Pos    (18U)\r\n#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */\r\n#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF19_Pos    (19U)\r\n#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */\r\n#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF20_Pos    (20U)\r\n#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */\r\n#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF21_Pos    (21U)\r\n#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */\r\n#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF22_Pos    (22U)\r\n#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */\r\n#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF23_Pos    (23U)\r\n#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */\r\n#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF24_Pos    (24U)\r\n#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */\r\n#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF25_Pos    (25U)\r\n#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */\r\n#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF26_Pos    (26U)\r\n#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */\r\n#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF27_Pos    (27U)\r\n#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */\r\n#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF28_Pos    (28U)\r\n#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */\r\n#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF29_Pos    (29U)\r\n#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */\r\n#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF30_Pos    (30U)\r\n#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */\r\n#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF31_Pos    (31U)\r\n#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */\r\n#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */\r\n\r\n/********************  Bit definition for HSEM_CR register  *****************/\r\n#define HSEM_CR_COREID_Pos        (8U)\r\n#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */\r\n#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */\r\n#define HSEM_CR_KEY_Pos           (16U)\r\n#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */\r\n#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */\r\n\r\n/********************  Bit definition for HSEM_KEYR register  *****************/\r\n#define HSEM_KEYR_KEY_Pos         (16U)\r\n#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */\r\n#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    HASH                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bits definition for HASH_CR register  ********************/\r\n#define HASH_CR_INIT_Pos          (2U)\r\n#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */\r\n#define HASH_CR_INIT              HASH_CR_INIT_Msk\r\n#define HASH_CR_DMAE_Pos          (3U)\r\n#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */\r\n#define HASH_CR_DMAE              HASH_CR_DMAE_Msk\r\n#define HASH_CR_DATATYPE_Pos      (4U)\r\n#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */\r\n#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk\r\n#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */\r\n#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */\r\n#define HASH_CR_MODE_Pos          (6U)\r\n#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */\r\n#define HASH_CR_MODE              HASH_CR_MODE_Msk\r\n#define HASH_CR_ALGO_Pos          (7U)\r\n#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */\r\n#define HASH_CR_ALGO              HASH_CR_ALGO_Msk\r\n#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */\r\n#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */\r\n#define HASH_CR_NBW_Pos           (8U)\r\n#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */\r\n#define HASH_CR_NBW               HASH_CR_NBW_Msk\r\n#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */\r\n#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */\r\n#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */\r\n#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */\r\n#define HASH_CR_DINNE_Pos         (12U)\r\n#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */\r\n#define HASH_CR_DINNE             HASH_CR_DINNE_Msk\r\n#define HASH_CR_MDMAT_Pos         (13U)\r\n#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */\r\n#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk\r\n#define HASH_CR_LKEY_Pos          (16U)\r\n#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */\r\n#define HASH_CR_LKEY              HASH_CR_LKEY_Msk\r\n\r\n/******************  Bits definition for HASH_STR register  *******************/\r\n#define HASH_STR_NBLW_Pos         (0U)\r\n#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */\r\n#define HASH_STR_NBLW             HASH_STR_NBLW_Msk\r\n#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */\r\n#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */\r\n#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */\r\n#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */\r\n#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */\r\n#define HASH_STR_DCAL_Pos         (8U)\r\n#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */\r\n#define HASH_STR_DCAL             HASH_STR_DCAL_Msk\r\n\r\n/******************  Bits definition for HASH_IMR register  *******************/\r\n#define HASH_IMR_DINIE_Pos        (0U)\r\n#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */\r\n#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk\r\n#define HASH_IMR_DCIE_Pos         (1U)\r\n#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */\r\n#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk\r\n\r\n/******************  Bits definition for HASH_SR register  ********************/\r\n#define HASH_SR_DINIS_Pos         (0U)\r\n#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */\r\n#define HASH_SR_DINIS             HASH_SR_DINIS_Msk\r\n#define HASH_SR_DCIS_Pos          (1U)\r\n#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */\r\n#define HASH_SR_DCIS              HASH_SR_DCIS_Msk\r\n#define HASH_SR_DMAS_Pos          (2U)\r\n#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */\r\n#define HASH_SR_DMAS              HASH_SR_DMAS_Msk\r\n#define HASH_SR_BUSY_Pos          (3U)\r\n#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */\r\n#define HASH_SR_BUSY              HASH_SR_BUSY_Msk\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Inter-integrated Circuit Interface (I2C)              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for I2C_CR1 register  *******************/\r\n#define I2C_CR1_PE_Pos               (0U)\r\n#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */\r\n#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */\r\n#define I2C_CR1_TXIE_Pos             (1U)\r\n#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */\r\n#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */\r\n#define I2C_CR1_RXIE_Pos             (2U)\r\n#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */\r\n#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */\r\n#define I2C_CR1_ADDRIE_Pos           (3U)\r\n#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */\r\n#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */\r\n#define I2C_CR1_NACKIE_Pos           (4U)\r\n#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */\r\n#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */\r\n#define I2C_CR1_STOPIE_Pos           (5U)\r\n#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */\r\n#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */\r\n#define I2C_CR1_TCIE_Pos             (6U)\r\n#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */\r\n#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */\r\n#define I2C_CR1_ERRIE_Pos            (7U)\r\n#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */\r\n#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */\r\n#define I2C_CR1_DNF_Pos              (8U)\r\n#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */\r\n#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */\r\n#define I2C_CR1_ANFOFF_Pos           (12U)\r\n#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */\r\n#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */\r\n#define I2C_CR1_TXDMAEN_Pos          (14U)\r\n#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */\r\n#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */\r\n#define I2C_CR1_RXDMAEN_Pos          (15U)\r\n#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */\r\n#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */\r\n#define I2C_CR1_SBC_Pos              (16U)\r\n#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */\r\n#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */\r\n#define I2C_CR1_NOSTRETCH_Pos        (17U)\r\n#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */\r\n#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */\r\n#define I2C_CR1_WUPEN_Pos            (18U)\r\n#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */\r\n#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */\r\n#define I2C_CR1_GCEN_Pos             (19U)\r\n#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */\r\n#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */\r\n#define I2C_CR1_SMBHEN_Pos           (20U)\r\n#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */\r\n#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */\r\n#define I2C_CR1_SMBDEN_Pos           (21U)\r\n#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */\r\n#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\r\n#define I2C_CR1_ALERTEN_Pos          (22U)\r\n#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */\r\n#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */\r\n#define I2C_CR1_PECEN_Pos            (23U)\r\n#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */\r\n#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */\r\n\r\n/******************  Bit definition for I2C_CR2 register  ********************/\r\n#define I2C_CR2_SADD_Pos             (0U)\r\n#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */\r\n#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */\r\n#define I2C_CR2_RD_WRN_Pos           (10U)\r\n#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */\r\n#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */\r\n#define I2C_CR2_ADD10_Pos            (11U)\r\n#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */\r\n#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */\r\n#define I2C_CR2_HEAD10R_Pos          (12U)\r\n#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */\r\n#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\r\n#define I2C_CR2_START_Pos            (13U)\r\n#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */\r\n#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */\r\n#define I2C_CR2_STOP_Pos             (14U)\r\n#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */\r\n#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */\r\n#define I2C_CR2_NACK_Pos             (15U)\r\n#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */\r\n#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */\r\n#define I2C_CR2_NBYTES_Pos           (16U)\r\n#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */\r\n#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */\r\n#define I2C_CR2_RELOAD_Pos           (24U)\r\n#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */\r\n#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */\r\n#define I2C_CR2_AUTOEND_Pos          (25U)\r\n#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */\r\n#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */\r\n#define I2C_CR2_PECBYTE_Pos          (26U)\r\n#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */\r\n#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */\r\n\r\n/*******************  Bit definition for I2C_OAR1 register  ******************/\r\n#define I2C_OAR1_OA1_Pos             (0U)\r\n#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */\r\n#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */\r\n#define I2C_OAR1_OA1MODE_Pos         (10U)\r\n#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */\r\n#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\r\n#define I2C_OAR1_OA1EN_Pos           (15U)\r\n#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */\r\n#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */\r\n\r\n/*******************  Bit definition for I2C_OAR2 register  ******************/\r\n#define I2C_OAR2_OA2_Pos             (1U)\r\n#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */\r\n#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */\r\n#define I2C_OAR2_OA2MSK_Pos          (8U)\r\n#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */\r\n#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */\r\n#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */\r\n#define I2C_OAR2_OA2MASK01_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */\r\n#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r\n#define I2C_OAR2_OA2MASK02_Pos       (9U)\r\n#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */\r\n#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r\n#define I2C_OAR2_OA2MASK03_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */\r\n#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r\n#define I2C_OAR2_OA2MASK04_Pos       (10U)\r\n#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */\r\n#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r\n#define I2C_OAR2_OA2MASK05_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */\r\n#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r\n#define I2C_OAR2_OA2MASK06_Pos       (9U)\r\n#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */\r\n#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r\n#define I2C_OAR2_OA2MASK07_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */\r\n#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */\r\n#define I2C_OAR2_OA2EN_Pos           (15U)\r\n#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */\r\n#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */\r\n\r\n/*******************  Bit definition for I2C_TIMINGR register *******************/\r\n#define I2C_TIMINGR_SCLL_Pos         (0U)\r\n#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */\r\n#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */\r\n#define I2C_TIMINGR_SCLH_Pos         (8U)\r\n#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */\r\n#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\r\n#define I2C_TIMINGR_SDADEL_Pos       (16U)\r\n#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */\r\n#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */\r\n#define I2C_TIMINGR_SCLDEL_Pos       (20U)\r\n#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */\r\n#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */\r\n#define I2C_TIMINGR_PRESC_Pos        (28U)\r\n#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */\r\n#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */\r\n\r\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\r\n#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\r\n#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */\r\n#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */\r\n#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\r\n#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */\r\n#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */\r\n#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\r\n#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */\r\n#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */\r\n#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\r\n#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */\r\n#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/\r\n#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\r\n#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */\r\n#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\r\n\r\n/******************  Bit definition for I2C_ISR register  *********************/\r\n#define I2C_ISR_TXE_Pos              (0U)\r\n#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */\r\n#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */\r\n#define I2C_ISR_TXIS_Pos             (1U)\r\n#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */\r\n#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */\r\n#define I2C_ISR_RXNE_Pos             (2U)\r\n#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */\r\n#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\r\n#define I2C_ISR_ADDR_Pos             (3U)\r\n#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */\r\n#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/\r\n#define I2C_ISR_NACKF_Pos            (4U)\r\n#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */\r\n#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */\r\n#define I2C_ISR_STOPF_Pos            (5U)\r\n#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */\r\n#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */\r\n#define I2C_ISR_TC_Pos               (6U)\r\n#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */\r\n#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\r\n#define I2C_ISR_TCR_Pos              (7U)\r\n#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */\r\n#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */\r\n#define I2C_ISR_BERR_Pos             (8U)\r\n#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */\r\n#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */\r\n#define I2C_ISR_ARLO_Pos             (9U)\r\n#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */\r\n#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */\r\n#define I2C_ISR_OVR_Pos              (10U)\r\n#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */\r\n#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */\r\n#define I2C_ISR_PECERR_Pos           (11U)\r\n#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */\r\n#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */\r\n#define I2C_ISR_TIMEOUT_Pos          (12U)\r\n#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */\r\n#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */\r\n#define I2C_ISR_ALERT_Pos            (13U)\r\n#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */\r\n#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */\r\n#define I2C_ISR_BUSY_Pos             (15U)\r\n#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */\r\n#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */\r\n#define I2C_ISR_DIR_Pos              (16U)\r\n#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */\r\n#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\r\n#define I2C_ISR_ADDCODE_Pos          (17U)\r\n#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */\r\n#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\r\n\r\n/******************  Bit definition for I2C_ICR register  *********************/\r\n#define I2C_ICR_ADDRCF_Pos           (3U)\r\n#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */\r\n#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */\r\n#define I2C_ICR_NACKCF_Pos           (4U)\r\n#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */\r\n#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */\r\n#define I2C_ICR_STOPCF_Pos           (5U)\r\n#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */\r\n#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */\r\n#define I2C_ICR_BERRCF_Pos           (8U)\r\n#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */\r\n#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */\r\n#define I2C_ICR_ARLOCF_Pos           (9U)\r\n#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */\r\n#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\r\n#define I2C_ICR_OVRCF_Pos            (10U)\r\n#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */\r\n#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\r\n#define I2C_ICR_PECCF_Pos            (11U)\r\n#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */\r\n#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */\r\n#define I2C_ICR_TIMOUTCF_Pos         (12U)\r\n#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */\r\n#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */\r\n#define I2C_ICR_ALERTCF_Pos          (13U)\r\n#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */\r\n#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */\r\n\r\n/******************  Bit definition for I2C_PECR register  *********************/\r\n#define I2C_PECR_PEC_Pos             (0U)\r\n#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */\r\n#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\r\n\r\n/******************  Bit definition for I2C_RXDR register  *********************/\r\n#define I2C_RXDR_RXDATA_Pos          (0U)\r\n#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */\r\n#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\r\n\r\n/******************  Bit definition for I2C_TXDR register  *********************/\r\n#define I2C_TXDR_TXDATA_Pos          (0U)\r\n#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */\r\n#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Independent WATCHDOG                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define IWDG_KR_KEY_Pos      (0U)\r\n#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */\r\n#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\r\n\r\n/*******************  Bit definition for IWDG_PR register  ********************/\r\n#define IWDG_PR_PR_Pos       (0U)\r\n#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */\r\n#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\r\n#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */\r\n#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */\r\n#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */\r\n\r\n/*******************  Bit definition for IWDG_RLR register  *******************/\r\n#define IWDG_RLR_RL_Pos      (0U)\r\n#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */\r\n#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\r\n\r\n/*******************  Bit definition for IWDG_SR register  ********************/\r\n#define IWDG_SR_PVU_Pos      (0U)\r\n#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */\r\n#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\r\n#define IWDG_SR_RVU_Pos      (1U)\r\n#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */\r\n#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\r\n#define IWDG_SR_WVU_Pos      (2U)\r\n#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */\r\n#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\r\n\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define IWDG_WINR_WIN_Pos    (0U)\r\n#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */\r\n#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      LCD-TFT Display Controller (LTDC)                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for LTDC_SSCR register  *****************/\r\n\r\n#define LTDC_SSCR_VSH_Pos            (0U)\r\n#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */\r\n#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */\r\n#define LTDC_SSCR_HSW_Pos            (16U)\r\n#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */\r\n#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */\r\n\r\n/********************  Bit definition for LTDC_BPCR register  *****************/\r\n\r\n#define LTDC_BPCR_AVBP_Pos           (0U)\r\n#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */\r\n#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */\r\n#define LTDC_BPCR_AHBP_Pos           (16U)\r\n#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */\r\n#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */\r\n\r\n/********************  Bit definition for LTDC_AWCR register  *****************/\r\n\r\n#define LTDC_AWCR_AAH_Pos            (0U)\r\n#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */\r\n#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */\r\n#define LTDC_AWCR_AAW_Pos            (16U)\r\n#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */\r\n#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */\r\n\r\n/********************  Bit definition for LTDC_TWCR register  *****************/\r\n\r\n#define LTDC_TWCR_TOTALH_Pos         (0U)\r\n#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */\r\n#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total height */\r\n#define LTDC_TWCR_TOTALW_Pos         (16U)\r\n#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */\r\n#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */\r\n\r\n/********************  Bit definition for LTDC_GCR register  ******************/\r\n\r\n#define LTDC_GCR_LTDCEN_Pos          (0U)\r\n#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */\r\n#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */\r\n#define LTDC_GCR_DBW_Pos             (4U)\r\n#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */\r\n#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */\r\n#define LTDC_GCR_DGW_Pos             (8U)\r\n#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */\r\n#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */\r\n#define LTDC_GCR_DRW_Pos             (12U)\r\n#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */\r\n#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */\r\n#define LTDC_GCR_DEN_Pos             (16U)\r\n#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */\r\n#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */\r\n#define LTDC_GCR_PCPOL_Pos           (28U)\r\n#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */\r\n#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */\r\n#define LTDC_GCR_DEPOL_Pos           (29U)\r\n#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */\r\n#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */\r\n#define LTDC_GCR_VSPOL_Pos           (30U)\r\n#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */\r\n#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */\r\n#define LTDC_GCR_HSPOL_Pos           (31U)\r\n#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */\r\n#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */\r\n\r\n\r\n/********************  Bit definition for LTDC_SRCR register  *****************/\r\n\r\n#define LTDC_SRCR_IMR_Pos            (0U)\r\n#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */\r\n#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */\r\n#define LTDC_SRCR_VBR_Pos            (1U)\r\n#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */\r\n#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */\r\n\r\n/********************  Bit definition for LTDC_BCCR register  *****************/\r\n\r\n#define LTDC_BCCR_BCBLUE_Pos         (0U)\r\n#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */\r\n#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */\r\n#define LTDC_BCCR_BCGREEN_Pos        (8U)\r\n#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */\r\n#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */\r\n#define LTDC_BCCR_BCRED_Pos          (16U)\r\n#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */\r\n#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */\r\n\r\n/********************  Bit definition for LTDC_IER register  ******************/\r\n\r\n#define LTDC_IER_LIE_Pos             (0U)\r\n#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */\r\n#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */\r\n#define LTDC_IER_FUIE_Pos            (1U)\r\n#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */\r\n#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */\r\n#define LTDC_IER_TERRIE_Pos          (2U)\r\n#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */\r\n#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */\r\n#define LTDC_IER_RRIE_Pos            (3U)\r\n#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */\r\n#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */\r\n\r\n/********************  Bit definition for LTDC_ISR register  ******************/\r\n\r\n#define LTDC_ISR_LIF_Pos             (0U)\r\n#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */\r\n#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */\r\n#define LTDC_ISR_FUIF_Pos            (1U)\r\n#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */\r\n#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */\r\n#define LTDC_ISR_TERRIF_Pos          (2U)\r\n#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */\r\n#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */\r\n#define LTDC_ISR_RRIF_Pos            (3U)\r\n#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */\r\n#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_ICR register  ******************/\r\n\r\n#define LTDC_ICR_CLIF_Pos            (0U)\r\n#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */\r\n#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */\r\n#define LTDC_ICR_CFUIF_Pos           (1U)\r\n#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */\r\n#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */\r\n#define LTDC_ICR_CTERRIF_Pos         (2U)\r\n#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */\r\n#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */\r\n#define LTDC_ICR_CRRIF_Pos           (3U)\r\n#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */\r\n#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_LIPCR register  ****************/\r\n\r\n#define LTDC_LIPCR_LIPOS_Pos         (0U)\r\n#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */\r\n#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */\r\n\r\n/********************  Bit definition for LTDC_CPSR register  *****************/\r\n\r\n#define LTDC_CPSR_CYPOS_Pos          (0U)\r\n#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */\r\n#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */\r\n#define LTDC_CPSR_CXPOS_Pos          (16U)\r\n#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */\r\n#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */\r\n\r\n/********************  Bit definition for LTDC_CDSR register  *****************/\r\n\r\n#define LTDC_CDSR_VDES_Pos           (0U)\r\n#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */\r\n#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */\r\n#define LTDC_CDSR_HDES_Pos           (1U)\r\n#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */\r\n#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */\r\n#define LTDC_CDSR_VSYNCS_Pos         (2U)\r\n#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */\r\n#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */\r\n#define LTDC_CDSR_HSYNCS_Pos         (3U)\r\n#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */\r\n#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */\r\n\r\n/********************  Bit definition for LTDC_LxCR register  *****************/\r\n\r\n#define LTDC_LxCR_LEN_Pos            (0U)\r\n#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */\r\n#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */\r\n#define LTDC_LxCR_COLKEN_Pos         (1U)\r\n#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */\r\n#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */\r\n#define LTDC_LxCR_CLUTEN_Pos         (4U)\r\n#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */\r\n#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */\r\n\r\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\r\n\r\n#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)\r\n#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */\r\n#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */\r\n#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)\r\n#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */\r\n#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\r\n\r\n#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)\r\n#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */\r\n#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */\r\n#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)\r\n#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */\r\n#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\r\n\r\n#define LTDC_LxCKCR_CKBLUE_Pos       (0U)\r\n#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */\r\n#define LTDC_LxCKCR_CKGREEN_Pos      (8U)\r\n#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */\r\n#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */\r\n#define LTDC_LxCKCR_CKRED_Pos        (16U)\r\n#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */\r\n#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */\r\n\r\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\r\n\r\n#define LTDC_LxPFCR_PF_Pos           (0U)\r\n#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */\r\n#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */\r\n\r\n/********************  Bit definition for LTDC_LxCACR register  ***************/\r\n\r\n#define LTDC_LxCACR_CONSTA_Pos       (0U)\r\n#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\r\n\r\n#define LTDC_LxDCCR_DCBLUE_Pos       (0U)\r\n#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */\r\n#define LTDC_LxDCCR_DCGREEN_Pos      (8U)\r\n#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */\r\n#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */\r\n#define LTDC_LxDCCR_DCRED_Pos        (16U)\r\n#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */\r\n#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */\r\n#define LTDC_LxDCCR_DCALPHA_Pos      (24U)\r\n#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */\r\n#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxBFCR register  ***************/\r\n\r\n#define LTDC_LxBFCR_BF2_Pos          (0U)\r\n#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */\r\n#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */\r\n#define LTDC_LxBFCR_BF1_Pos          (8U)\r\n#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */\r\n#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */\r\n\r\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\r\n\r\n#define LTDC_LxCFBAR_CFBADD_Pos      (0U)\r\n#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */\r\n#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\r\n\r\n#define LTDC_LxCFBLR_CFBLL_Pos       (0U)\r\n#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */\r\n#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */\r\n#define LTDC_LxCFBLR_CFBP_Pos        (16U)\r\n#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */\r\n#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\r\n\r\n#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)\r\n#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */\r\n#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */\r\n\r\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\r\n\r\n#define LTDC_LxCLUTWR_BLUE_Pos       (0U)\r\n#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */\r\n#define LTDC_LxCLUTWR_GREEN_Pos      (8U)\r\n#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */\r\n#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */\r\n#define LTDC_LxCLUTWR_RED_Pos        (16U)\r\n#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */\r\n#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */\r\n#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)\r\n#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */\r\n#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                     MDMA                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for MDMA_GISR0 register  ****************/\r\n#define MDMA_GISR0_GIF0_Pos       (0U)\r\n#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */\r\n#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */\r\n#define MDMA_GISR0_GIF1_Pos       (1U)\r\n#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */\r\n#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */\r\n#define MDMA_GISR0_GIF2_Pos       (2U)\r\n#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */\r\n#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */\r\n#define MDMA_GISR0_GIF3_Pos       (3U)\r\n#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */\r\n#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */\r\n#define MDMA_GISR0_GIF4_Pos       (4U)\r\n#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */\r\n#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */\r\n#define MDMA_GISR0_GIF5_Pos       (5U)\r\n#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */\r\n#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */\r\n#define MDMA_GISR0_GIF6_Pos       (6U)\r\n#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */\r\n#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */\r\n#define MDMA_GISR0_GIF7_Pos       (7U)\r\n#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */\r\n#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */\r\n#define MDMA_GISR0_GIF8_Pos       (8U)\r\n#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */\r\n#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */\r\n#define MDMA_GISR0_GIF9_Pos       (9U)\r\n#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */\r\n#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */\r\n#define MDMA_GISR0_GIF10_Pos      (10U)\r\n#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */\r\n#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */\r\n#define MDMA_GISR0_GIF11_Pos      (11U)\r\n#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */\r\n#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */\r\n#define MDMA_GISR0_GIF12_Pos      (12U)\r\n#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */\r\n#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */\r\n#define MDMA_GISR0_GIF13_Pos      (13U)\r\n#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */\r\n#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */\r\n#define MDMA_GISR0_GIF14_Pos      (14U)\r\n#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */\r\n#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */\r\n#define MDMA_GISR0_GIF15_Pos      (15U)\r\n#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */\r\n#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */\r\n\r\n/********************  Bit definition for MDMA_CxISR register  ****************/\r\n#define MDMA_CISR_TEIF_Pos        (0U)\r\n#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */\r\n#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */\r\n#define MDMA_CISR_CTCIF_Pos       (1U)\r\n#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */\r\n#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */\r\n#define MDMA_CISR_BRTIF_Pos       (2U)\r\n#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */\r\n#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */\r\n#define MDMA_CISR_BTIF_Pos        (3U)\r\n#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */\r\n#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */\r\n#define MDMA_CISR_TCIF_Pos        (4U)\r\n#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */\r\n#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */\r\n#define MDMA_CISR_CRQA_Pos        (16U)\r\n#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */\r\n#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x request Active flag */\r\n\r\n/********************  Bit definition for MDMA_CxIFCR register  ****************/\r\n#define MDMA_CIFCR_CTEIF_Pos      (0U)\r\n#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */\r\n#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */\r\n#define MDMA_CIFCR_CCTCIF_Pos     (1U)\r\n#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */\r\n#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */\r\n#define MDMA_CIFCR_CBRTIF_Pos     (2U)\r\n#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */\r\n#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */\r\n#define MDMA_CIFCR_CBTIF_Pos      (3U)\r\n#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */\r\n#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */\r\n#define MDMA_CIFCR_CLTCIF_Pos     (4U)\r\n#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */\r\n#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */\r\n\r\n/********************  Bit definition for MDMA_CxESR register  ****************/\r\n#define MDMA_CESR_TEA_Pos         (0U)\r\n#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */\r\n#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */\r\n#define MDMA_CESR_TED_Pos         (7U)\r\n#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */\r\n#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */\r\n#define MDMA_CESR_TELD_Pos        (8U)\r\n#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */\r\n#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */\r\n#define MDMA_CESR_TEMD_Pos        (9U)\r\n#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */\r\n#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */\r\n#define MDMA_CESR_ASE_Pos         (10U)\r\n#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */\r\n#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */\r\n#define MDMA_CESR_BSE_Pos         (11U)\r\n#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */\r\n#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */\r\n\r\n/********************  Bit definition for MDMA_CxCR register  ****************/\r\n#define MDMA_CCR_EN_Pos           (0U)\r\n#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */\r\n#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */\r\n#define MDMA_CCR_TEIE_Pos         (1U)\r\n#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */\r\n#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */\r\n#define MDMA_CCR_CTCIE_Pos        (2U)\r\n#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */\r\n#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */\r\n#define MDMA_CCR_BRTIE_Pos        (3U)\r\n#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */\r\n#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */\r\n#define MDMA_CCR_BTIE_Pos         (4U)\r\n#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */\r\n#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */\r\n#define MDMA_CCR_TCIE_Pos         (5U)\r\n#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */\r\n#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */\r\n#define MDMA_CCR_PL_Pos           (6U)\r\n#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */\r\n#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */\r\n#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */\r\n#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */\r\n#define MDMA_CCR_BEX_Pos          (12U)\r\n#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */\r\n#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianness eXchange */\r\n#define MDMA_CCR_HEX_Pos          (13U)\r\n#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */\r\n#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianness eXchange */\r\n#define MDMA_CCR_WEX_Pos          (14U)\r\n#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */\r\n#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianness eXchange */\r\n#define MDMA_CCR_SWRQ_Pos         (16U)\r\n#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */\r\n#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */\r\n\r\n/********************  Bit definition for MDMA_CxTCR register  ****************/\r\n#define MDMA_CTCR_SINC_Pos        (0U)\r\n#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */\r\n#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */\r\n#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */\r\n#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */\r\n#define MDMA_CTCR_DINC_Pos        (2U)\r\n#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */\r\n#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */\r\n#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */\r\n#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */\r\n#define MDMA_CTCR_SSIZE_Pos       (4U)\r\n#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */\r\n#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */\r\n#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */\r\n#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */\r\n#define MDMA_CTCR_DSIZE_Pos       (6U)\r\n#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */\r\n#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */\r\n#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */\r\n#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */\r\n#define MDMA_CTCR_SINCOS_Pos      (8U)\r\n#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */\r\n#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */\r\n#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */\r\n#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */\r\n#define MDMA_CTCR_DINCOS_Pos      (10U)\r\n#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */\r\n#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */\r\n#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */\r\n#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */\r\n#define MDMA_CTCR_SBURST_Pos      (12U)\r\n#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */\r\n#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */\r\n#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */\r\n#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */\r\n#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */\r\n#define MDMA_CTCR_DBURST_Pos      (15U)\r\n#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */\r\n#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */\r\n#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */\r\n#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */\r\n#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */\r\n#define MDMA_CTCR_TLEN_Pos        (18U)\r\n#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */\r\n#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */\r\n#define MDMA_CTCR_PKE_Pos         (25U)\r\n#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */\r\n#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */\r\n#define MDMA_CTCR_PAM_Pos         (26U)\r\n#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */\r\n#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignment Mode */\r\n#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */\r\n#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */\r\n#define MDMA_CTCR_TRGM_Pos        (28U)\r\n#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */\r\n#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */\r\n#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */\r\n#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */\r\n#define MDMA_CTCR_SWRM_Pos        (30U)\r\n#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */\r\n#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */\r\n#define MDMA_CTCR_BWM_Pos         (31U)\r\n#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */\r\n#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */\r\n\r\n/********************  Bit definition for MDMA_CxBNDTR register  ****************/\r\n#define MDMA_CBNDTR_BNDT_Pos      (0U)\r\n#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */\r\n#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */\r\n#define MDMA_CBNDTR_BRSUM_Pos     (18U)\r\n#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */\r\n#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */\r\n#define MDMA_CBNDTR_BRDUM_Pos     (19U)\r\n#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */\r\n#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */\r\n#define MDMA_CBNDTR_BRC_Pos       (20U)\r\n#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */\r\n#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */\r\n\r\n/********************  Bit definition for MDMA_CxSAR register  ****************/\r\n#define MDMA_CSAR_SAR_Pos         (0U)\r\n#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */\r\n\r\n/********************  Bit definition for MDMA_CxDAR register  ****************/\r\n#define MDMA_CDAR_DAR_Pos         (0U)\r\n#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */\r\n\r\n/********************  Bit definition for MDMA_CxBRUR  ************************/\r\n#define MDMA_CBRUR_SUV_Pos        (0U)\r\n#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */\r\n#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */\r\n#define MDMA_CBRUR_DUV_Pos        (16U)\r\n#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */\r\n#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */\r\n\r\n/********************  Bit definition for MDMA_CxLAR  *************************/\r\n#define MDMA_CLAR_LAR_Pos         (0U)\r\n#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */\r\n\r\n/********************  Bit definition for MDMA_CxTBR)  ************************/\r\n#define MDMA_CTBR_TSEL_Pos        (0U)\r\n#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */\r\n#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */\r\n#define MDMA_CTBR_SBUS_Pos        (16U)\r\n#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */\r\n#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */\r\n#define MDMA_CTBR_DBUS_Pos        (17U)\r\n#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */\r\n#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */\r\n\r\n/********************  Bit definition for MDMA_CxMAR)  ************************/\r\n#define MDMA_CMAR_MAR_Pos         (0U)\r\n#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */\r\n\r\n/********************  Bit definition for MDMA_CxMDR)  ************************/\r\n#define MDMA_CMDR_MDR_Pos         (0U)\r\n#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Operational Amplifier (OPAMP)                      */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*********************  Bit definition for OPAMPx_CSR register  ***************/\r\n#define OPAMP_CSR_OPAMPxEN_Pos           (0U)\r\n#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */\r\n#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */\r\n#define OPAMP_CSR_FORCEVP_Pos            (1U)\r\n#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */\r\n#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */\r\n\r\n#define OPAMP_CSR_VPSEL_Pos              (2U)\r\n#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */\r\n#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */\r\n#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */\r\n#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */\r\n\r\n#define OPAMP_CSR_VMSEL_Pos              (5U)\r\n#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */\r\n#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */\r\n#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */\r\n#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */\r\n\r\n#define OPAMP_CSR_OPAHSM_Pos             (8U)\r\n#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */\r\n#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */\r\n#define OPAMP_CSR_CALON_Pos              (11U)\r\n#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */\r\n#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */\r\n\r\n#define OPAMP_CSR_CALSEL_Pos             (12U)\r\n#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */\r\n#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */\r\n#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */\r\n#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */\r\n\r\n#define OPAMP_CSR_PGGAIN_Pos             (14U)\r\n#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */\r\n#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */\r\n#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */\r\n#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */\r\n#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */\r\n#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */\r\n\r\n#define OPAMP_CSR_USERTRIM_Pos           (18U)\r\n#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */\r\n#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */\r\n#define OPAMP_CSR_TSTREF_Pos             (29U)\r\n#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */\r\n#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */\r\n#define OPAMP_CSR_CALOUT_Pos             (30U)\r\n#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */\r\n#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */\r\n\r\n/*********************  Bit definition for OPAMP1_CSR register  ***************/\r\n#define OPAMP1_CSR_OPAEN_Pos              (0U)\r\n#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r\n#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */\r\n#define OPAMP1_CSR_FORCEVP_Pos            (1U)\r\n#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */\r\n#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */\r\n\r\n#define OPAMP1_CSR_VPSEL_Pos              (2U)\r\n#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */\r\n#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r\n#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */\r\n#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */\r\n\r\n#define OPAMP1_CSR_VMSEL_Pos              (5U)\r\n#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */\r\n#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r\n#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */\r\n#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */\r\n\r\n#define OPAMP1_CSR_OPAHSM_Pos             (8U)\r\n#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */\r\n#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */\r\n#define OPAMP1_CSR_CALON_Pos              (11U)\r\n#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */\r\n#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */\r\n\r\n#define OPAMP1_CSR_CALSEL_Pos             (12U)\r\n#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */\r\n#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */\r\n#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */\r\n#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */\r\n\r\n#define OPAMP1_CSR_PGGAIN_Pos             (14U)\r\n#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */\r\n#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */\r\n#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */\r\n#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */\r\n#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */\r\n#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */\r\n\r\n#define OPAMP1_CSR_USERTRIM_Pos           (18U)\r\n#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */\r\n#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */\r\n#define OPAMP1_CSR_TSTREF_Pos             (29U)\r\n#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */\r\n#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */\r\n#define OPAMP1_CSR_CALOUT_Pos             (30U)\r\n#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */\r\n#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */\r\n\r\n/*********************  Bit definition for OPAMP2_CSR register  ***************/\r\n#define OPAMP2_CSR_OPAEN_Pos              (0U)\r\n#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r\n#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */\r\n#define OPAMP2_CSR_FORCEVP_Pos            (1U)\r\n#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */\r\n#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */\r\n\r\n#define OPAMP2_CSR_VPSEL_Pos              (2U)\r\n#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */\r\n#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r\n#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */\r\n#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */\r\n\r\n#define OPAMP2_CSR_VMSEL_Pos              (5U)\r\n#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */\r\n#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r\n#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */\r\n#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */\r\n\r\n#define OPAMP2_CSR_OPAHSM_Pos             (8U)\r\n#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */\r\n#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */\r\n#define OPAMP2_CSR_CALON_Pos              (11U)\r\n#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */\r\n#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */\r\n\r\n#define OPAMP2_CSR_CALSEL_Pos             (12U)\r\n#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */\r\n#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */\r\n#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */\r\n#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */\r\n\r\n#define OPAMP2_CSR_PGGAIN_Pos             (14U)\r\n#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */\r\n#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */\r\n#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */\r\n#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */\r\n#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */\r\n#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */\r\n\r\n#define OPAMP2_CSR_USERTRIM_Pos           (18U)\r\n#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */\r\n#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */\r\n#define OPAMP2_CSR_TSTREF_Pos             (29U)\r\n#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */\r\n#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */\r\n#define OPAMP2_CSR_CALOUT_Pos             (30U)\r\n#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */\r\n#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */\r\n\r\n/*******************  Bit definition for OPAMP_OTR register  ******************/\r\n#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)\r\n#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */\r\n#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)\r\n#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP1_OTR register  ******************/\r\n#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)\r\n#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r\n#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)\r\n#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP2_OTR register  ******************/\r\n#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)\r\n#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r\n#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)\r\n#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP_HSOTR register  ****************/\r\n#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)\r\n#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */\r\n#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)\r\n#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP1_HSOTR register  ****************/\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP2_HSOTR register  ****************/\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Parallel Synchronous Slave Interface (PSSI )                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for PSSI_CR register  *******************/\r\n#define PSSI_CR_OUTEN_Pos               (31U)\r\n#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */\r\n#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */\r\n#define PSSI_CR_DMAEN_Pos               (30U)\r\n#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */\r\n#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */\r\n#define PSSI_CR_DERDYCFG_Pos            (18U)\r\n#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */\r\n#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */\r\n#define PSSI_CR_ENABLE_Pos              (14U)\r\n#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */\r\n#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */\r\n#define PSSI_CR_EDM_Pos                 (10U)\r\n#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */\r\n#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */\r\n#define PSSI_CR_RDYPOL_Pos              (8U)\r\n#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */\r\n#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */\r\n#define PSSI_CR_DEPOL_Pos               (6U)\r\n#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */\r\n#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */\r\n#define PSSI_CR_CKPOL_Pos               (5U)\r\n#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */\r\n#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */\r\n/********************  Bit definition for PSSI_SR register  *******************/\r\n#define PSSI_SR_RTT1B_Pos               (3U)\r\n#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */\r\n#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */\r\n#define PSSI_SR_RTT4B_Pos               (2U)\r\n#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */\r\n#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */\r\n/********************  Bit definition for PSSI_RIS register  *******************/\r\n#define PSSI_RIS_OVR_RIS_Pos            (1U)\r\n#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */\r\n#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */\r\n/********************  Bit definition for PSSI_IER register  *******************/\r\n#define PSSI_IER_OVR_IE_Pos             (1U)\r\n#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */\r\n#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */\r\n/********************  Bit definition for PSSI_MIS register  *******************/\r\n#define PSSI_MIS_OVR_MIS_Pos            (1U)\r\n#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */\r\n#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */\r\n/********************  Bit definition for PSSI_ICR register  *******************/\r\n#define PSSI_ICR_OVR_ISC_Pos            (1U)\r\n#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */\r\n#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */\r\n/********************  Bit definition for PSSI_DR register  *******************/\r\n#define PSSI_DR_DR_Pos                  (0U)\r\n#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */\r\n#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                              On The Fly Decryption                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for OTFDEC_CR register  ******************/\r\n#define OTFDEC_CR_ENC_Pos                      (0U)\r\n#define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */\r\n#define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */\r\n\r\n/******************  Bit definition for OTFDEC_PRIVCFGR register  ************/\r\n#define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)\r\n#define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */\r\n#define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */\r\n\r\n/******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/\r\n#define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)\r\n#define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */\r\n#define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */\r\n\r\n#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)\r\n#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */\r\n#define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */\r\n\r\n#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)\r\n#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */\r\n#define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */\r\n\r\n#define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)\r\n#define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */\r\n#define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */\r\n#define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */\r\n#define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */\r\n\r\n#define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)\r\n#define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */\r\n#define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */\r\n\r\n#define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)\r\n#define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */\r\n#define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */\r\n\r\n/******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/\r\n#define OTFDEC_REG_START_ADDR_Pos              (0U)\r\n#define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */\r\n\r\n/******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/\r\n#define OTFDEC_REG_END_ADDR_Pos                (0U)\r\n#define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */\r\n\r\n/******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/\r\n#define OTFDEC_REG_NONCER0_Pos                 (0U)\r\n#define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/\r\n#define OTFDEC_REG_NONCER1_Pos                 (0U)\r\n#define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/\r\n#define OTFDEC_REG_KEYR0_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/\r\n#define OTFDEC_REG_KEYR1_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/\r\n#define OTFDEC_REG_KEYR2_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/\r\n#define OTFDEC_REG_KEYR3_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */\r\n\r\n/******************  Bit definition for OTFDEC_ISR register  *****************/\r\n#define OTFDEC_ISR_SEIF_Pos                    (0U)\r\n#define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */\r\n#define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */\r\n\r\n#define OTFDEC_ISR_XONEIF_Pos                  (1U)\r\n#define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */\r\n#define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */\r\n\r\n#define OTFDEC_ISR_KEIF_Pos                    (2U)\r\n#define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */\r\n#define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */\r\n\r\n/******************  Bit definition  for OTFDEC_ICR register  *****************/\r\n#define OTFDEC_ICR_SEIF_Pos                    (0U)\r\n#define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */\r\n#define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */\r\n\r\n#define OTFDEC_ICR_XONEIF_Pos                  (1U)\r\n#define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */\r\n#define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */\r\n\r\n#define OTFDEC_ICR_KEIF_Pos                    (2U)\r\n#define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */\r\n#define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */\r\n\r\n/******************  Bit definition for OTFDEC_IER register  *****************/\r\n#define OTFDEC_IER_SEIE_Pos                    (0U)\r\n#define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */\r\n#define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */\r\n\r\n#define OTFDEC_IER_XONEIE_Pos                  (1U)\r\n#define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */\r\n#define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */\r\n\r\n#define OTFDEC_IER_KEIE_Pos                    (2U)\r\n#define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */\r\n#define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             Power Control                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*************************  NUMBER OF POWER DOMAINS  **************************/\r\n#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */\r\n\r\n/********************  Bit definition for PWR_CR1 register  *******************/\r\n#define PWR_CR1_ALS_Pos                (17U)\r\n#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */\r\n#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */\r\n#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */\r\n#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */\r\n#define PWR_CR1_AVDEN_Pos              (16U)\r\n#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */\r\n#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */\r\n#define PWR_CR1_SVOS_Pos               (14U)\r\n#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */\r\n#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */\r\n#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */\r\n#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */\r\n#define PWR_CR1_FLPS_Pos               (9U)\r\n#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */\r\n#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */\r\n#define PWR_CR1_DBP_Pos                (8U)\r\n#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */\r\n#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */\r\n#define PWR_CR1_PLS_Pos                (5U)\r\n#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */\r\n#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */\r\n#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */\r\n#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */\r\n#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */\r\n#define PWR_CR1_PVDEN_Pos              (4U)\r\n#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */\r\n#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */\r\n#define PWR_CR1_LPDS_Pos               (0U)\r\n#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */\r\n#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */\r\n\r\n/*!< PVD level configuration */\r\n#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */\r\n#define PWR_CR1_PLS_LEV1_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */\r\n#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */\r\n#define PWR_CR1_PLS_LEV2_Pos           (6U)\r\n#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */\r\n#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */\r\n#define PWR_CR1_PLS_LEV3_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */\r\n#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */\r\n#define PWR_CR1_PLS_LEV4_Pos           (7U)\r\n#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */\r\n#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */\r\n#define PWR_CR1_PLS_LEV5_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */\r\n#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */\r\n#define PWR_CR1_PLS_LEV6_Pos           (6U)\r\n#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */\r\n#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */\r\n#define PWR_CR1_PLS_LEV7_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */\r\n#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */\r\n\r\n/*!< AVD level configuration */\r\n#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */\r\n#define PWR_CR1_ALS_LEV1_Pos           (17U)\r\n#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */\r\n#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */\r\n#define PWR_CR1_ALS_LEV2_Pos           (18U)\r\n#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */\r\n#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */\r\n#define PWR_CR1_ALS_LEV3_Pos           (17U)\r\n#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */\r\n#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */\r\n\r\n/********************  Bit definition for PWR_CSR1 register  ******************/\r\n#define PWR_CSR1_AVDO_Pos              (16U)\r\n#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */\r\n#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */\r\n#define PWR_CSR1_ACTVOS_Pos            (14U)\r\n#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */\r\n#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */\r\n#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */\r\n#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */\r\n#define PWR_CSR1_ACTVOSRDY_Pos         (13U)\r\n#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */\r\n#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */\r\n#define PWR_CSR1_PVDO_Pos              (4U)\r\n#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */\r\n#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */\r\n\r\n/********************  Bit definition for PWR_CR2 register  *******************/\r\n#define PWR_CR2_TEMPH_Pos              (23U)\r\n#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */\r\n#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */\r\n#define PWR_CR2_TEMPL_Pos              (22U)\r\n#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */\r\n#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */\r\n#define PWR_CR2_VBATH_Pos              (21U)\r\n#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */\r\n#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */\r\n#define PWR_CR2_VBATL_Pos              (20U)\r\n#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */\r\n#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */\r\n#define PWR_CR2_BRRDY_Pos              (16U)\r\n#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */\r\n#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */\r\n#define PWR_CR2_MONEN_Pos              (4U)\r\n#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */\r\n#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */\r\n#define PWR_CR2_BREN_Pos               (0U)\r\n#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */\r\n#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */\r\n\r\n/********************  Bit definition for PWR_CR3 register  *******************/\r\n#define PWR_CR3_USB33RDY_Pos           (26U)\r\n#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */\r\n#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */\r\n#define PWR_CR3_USBREGEN_Pos           (25U)\r\n#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */\r\n#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */\r\n#define PWR_CR3_USB33DEN_Pos           (24U)\r\n#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */\r\n#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */\r\n#define PWR_CR3_SMPSEXTRDY_Pos         (16U)\r\n#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */\r\n#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */\r\n#define PWR_CR3_VBRS_Pos               (9U)\r\n#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */\r\n#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */\r\n#define PWR_CR3_VBE_Pos                (8U)\r\n#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */\r\n#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */\r\n#define PWR_CR3_SMPSLEVEL_Pos          (4U)\r\n#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */\r\n#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */\r\n#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */\r\n#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */\r\n#define PWR_CR3_SMPSEXTHP_Pos          (3U)\r\n#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */\r\n#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */\r\n#define PWR_CR3_SMPSEN_Pos             (2U)\r\n#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */\r\n#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */\r\n#define PWR_CR3_LDOEN_Pos              (1U)\r\n#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */\r\n#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */\r\n#define PWR_CR3_BYPASS_Pos             (0U)\r\n#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */\r\n#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */\r\n\r\n/********************  Bit definition for PWR_CPUCR register  *****************/\r\n#define PWR_CPUCR_RUN_D3_Pos           (11U)\r\n#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */\r\n#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */\r\n#define PWR_CPUCR_CSSF_Pos             (9U)\r\n#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */\r\n#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */\r\n#define PWR_CPUCR_SBF_D2_Pos           (8U)\r\n#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */\r\n#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */\r\n#define PWR_CPUCR_SBF_D1_Pos           (7U)\r\n#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */\r\n#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */\r\n#define PWR_CPUCR_SBF_Pos              (6U)\r\n#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */\r\n#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */\r\n#define PWR_CPUCR_STOPF_Pos            (5U)\r\n#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */\r\n#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */\r\n#define PWR_CPUCR_PDDS_D3_Pos          (2U)\r\n#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */\r\n#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */\r\n#define PWR_CPUCR_PDDS_D2_Pos          (1U)\r\n#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */\r\n#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */\r\n#define PWR_CPUCR_PDDS_D1_Pos          (0U)\r\n#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */\r\n#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */\r\n\r\n\r\n/********************  Bit definition for PWR_D3CR register  ******************/\r\n#define PWR_D3CR_VOS_Pos               (14U)\r\n#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */\r\n#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */\r\n#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */\r\n#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */\r\n#define PWR_D3CR_VOSRDY_Pos            (13U)\r\n#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */\r\n#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */\r\n\r\n/******************  Bit definition for PWR_WKUPCR register  ******************/\r\n#define PWR_WKUPCR_WKUPC6_Pos          (5U)\r\n#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */\r\n#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */\r\n#define PWR_WKUPCR_WKUPC4_Pos          (3U)\r\n#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */\r\n#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */\r\n#define PWR_WKUPCR_WKUPC2_Pos          (1U)\r\n#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */\r\n#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */\r\n#define PWR_WKUPCR_WKUPC1_Pos          (0U)\r\n#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */\r\n#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */\r\n\r\n/********************  Bit definition for PWR_WKUPFR register  ****************/\r\n#define PWR_WKUPFR_WKUPF6_Pos          (5U)\r\n#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */\r\n#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */\r\n#define PWR_WKUPFR_WKUPF4_Pos          (3U)\r\n#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */\r\n#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */\r\n#define PWR_WKUPFR_WKUPF2_Pos          (1U)\r\n#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */\r\n#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */\r\n#define PWR_WKUPFR_WKUPF1_Pos          (0U)\r\n#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */\r\n#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */\r\n\r\n/******************  Bit definition for PWR_WKUPEPR register  *****************/\r\n#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)\r\n#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */\r\n#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */\r\n#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */\r\n#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */\r\n#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)\r\n#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */\r\n#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */\r\n#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */\r\n#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */\r\n#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)\r\n#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */\r\n#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */\r\n#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */\r\n#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */\r\n#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)\r\n#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */\r\n#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */\r\n#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */\r\n#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */\r\n#define PWR_WKUPEPR_WKUPP6_Pos         (13U)\r\n#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */\r\n#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */\r\n#define PWR_WKUPEPR_WKUPP4_Pos         (11U)\r\n#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */\r\n#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */\r\n#define PWR_WKUPEPR_WKUPP2_Pos         (9U)\r\n#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */\r\n#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */\r\n#define PWR_WKUPEPR_WKUPP1_Pos         (8U)\r\n#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */\r\n#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */\r\n#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)\r\n#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */\r\n#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */\r\n#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)\r\n#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */\r\n#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */\r\n#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)\r\n#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */\r\n#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */\r\n#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)\r\n#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */\r\n#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */\r\n#define PWR_WKUPEPR_WKUPEN_Pos         (0U)\r\n#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */\r\n#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Reset and Clock Control                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************************  RCC VERSION  ********************************/\r\n#define RCC_VER_3_0\r\n\r\n/********************  Bit definition for RCC_CR register  ********************/\r\n#define RCC_CR_HSION_Pos                       (0U)\r\n#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */\r\n#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */\r\n#define RCC_CR_HSIKERON_Pos                    (1U)\r\n#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */\r\n#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */\r\n#define RCC_CR_HSIRDY_Pos                      (2U)\r\n#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */\r\n#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */\r\n#define RCC_CR_HSIDIV_Pos                      (3U)\r\n#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */\r\n#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */\r\n#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */\r\n#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */\r\n#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */\r\n#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */\r\n\r\n#define RCC_CR_HSIDIVF_Pos                     (5U)\r\n#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */\r\n#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */\r\n#define RCC_CR_CSION_Pos                       (7U)\r\n#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */\r\n#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */\r\n#define RCC_CR_CSIRDY_Pos                      (8U)\r\n#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */\r\n#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */\r\n#define RCC_CR_CSIKERON_Pos                    (9U)\r\n#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */\r\n#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */\r\n#define RCC_CR_HSI48ON_Pos                     (12U)\r\n#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */\r\n#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */\r\n#define RCC_CR_HSI48RDY_Pos                    (13U)\r\n#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */\r\n#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */\r\n\r\n#define RCC_CR_D1CKRDY_Pos                     (14U)\r\n#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */\r\n#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */\r\n#define RCC_CR_D2CKRDY_Pos                     (15U)\r\n#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */\r\n#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */\r\n\r\n#define RCC_CR_HSEON_Pos                       (16U)\r\n#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */\r\n#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */\r\n#define RCC_CR_HSERDY_Pos                      (17U)\r\n#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */\r\n#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */\r\n#define RCC_CR_HSEBYP_Pos                      (18U)\r\n#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */\r\n#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */\r\n#define RCC_CR_CSSHSEON_Pos                    (19U)\r\n#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */\r\n#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */\r\n\r\n\r\n#define RCC_CR_PLL1ON_Pos                      (24U)\r\n#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */\r\n#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */\r\n#define RCC_CR_PLL1RDY_Pos                     (25U)\r\n#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */\r\n#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */\r\n#define RCC_CR_PLL2ON_Pos                      (26U)\r\n#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */\r\n#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */\r\n#define RCC_CR_PLL2RDY_Pos                     (27U)\r\n#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */\r\n#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */\r\n#define RCC_CR_PLL3ON_Pos                      (28U)\r\n#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */\r\n#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */\r\n#define RCC_CR_PLL3RDY_Pos                     (29U)\r\n#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */\r\n#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */\r\n\r\n/*Legacy */\r\n#define RCC_CR_PLLON_Pos                       (24U)\r\n#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */\r\n#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */\r\n#define RCC_CR_PLLRDY_Pos                      (25U)\r\n#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */\r\n#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */\r\n\r\n/********************  Bit definition for RCC_HSICFGR register  ***************/\r\n/*!< HSICAL configuration */\r\n#define RCC_HSICFGR_HSICAL_Pos                 (0U)\r\n#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */\r\n#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */\r\n#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */\r\n#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */\r\n#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */\r\n#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */\r\n#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */\r\n#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */\r\n#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */\r\n#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */\r\n#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */\r\n#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */\r\n#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */\r\n#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */\r\n\r\n/*!< HSITRIM configuration */\r\n#define RCC_HSICFGR_HSITRIM_Pos                (24U)\r\n#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */\r\n#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */\r\n#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */\r\n#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */\r\n#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */\r\n#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */\r\n#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */\r\n#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */\r\n#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */\r\n\r\n\r\n/********************  Bit definition for RCC_CRRCR register  *****************/\r\n\r\n/*!< HSI48CAL configuration */\r\n#define RCC_CRRCR_HSI48CAL_Pos                 (0U)\r\n#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */\r\n#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */\r\n#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */\r\n#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */\r\n#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */\r\n#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */\r\n#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */\r\n#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */\r\n#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */\r\n#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */\r\n#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */\r\n#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */\r\n\r\n\r\n/********************  Bit definition for RCC_CSICFGR register  *****************/\r\n/*!< CSICAL configuration */\r\n#define RCC_CSICFGR_CSICAL_Pos                 (0U)\r\n#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */\r\n#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */\r\n#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */\r\n#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */\r\n#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */\r\n#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */\r\n#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */\r\n#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */\r\n#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */\r\n#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */\r\n\r\n/*!< CSITRIM configuration */\r\n#define RCC_CSICFGR_CSITRIM_Pos                (24U)\r\n#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */\r\n#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */\r\n#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */\r\n#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */\r\n#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */\r\n#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */\r\n#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */\r\n#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for RCC_CFGR register  ******************/\r\n/*!< SW configuration */\r\n#define RCC_CFGR_SW_Pos                        (0U)\r\n#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */\r\n#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */\r\n#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\r\n#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\r\n#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */\r\n\r\n#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */\r\n#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */\r\n#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */\r\n#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */\r\n\r\n/*!< SWS configuration */\r\n#define RCC_CFGR_SWS_Pos                       (3U)\r\n#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */\r\n#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */\r\n#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\r\n#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */\r\n#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */\r\n\r\n#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */\r\n#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */\r\n#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */\r\n#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */\r\n\r\n#define RCC_CFGR_STOPWUCK_Pos                  (6U)\r\n#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */\r\n#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */\r\n\r\n#define RCC_CFGR_STOPKERWUCK_Pos               (7U)\r\n#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */\r\n#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */\r\n\r\n/*!< RTCPRE configuration */\r\n#define RCC_CFGR_RTCPRE_Pos                    (8U)\r\n#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)\r\n#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */\r\n#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */\r\n#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */\r\n#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */\r\n#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */\r\n#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */\r\n#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */\r\n\r\n\r\n/*!< TIMPRE configuration */\r\n#define RCC_CFGR_TIMPRE_Pos                    (15U)\r\n#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)\r\n#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */\r\n\r\n/*!< MCO1 configuration */\r\n#define RCC_CFGR_MCO1_Pos                      (22U)\r\n#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)\r\n#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */\r\n#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */\r\n#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */\r\n#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */\r\n\r\n#define RCC_CFGR_MCO1PRE_Pos                   (18U)\r\n#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)\r\n#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */\r\n#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */\r\n#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */\r\n#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */\r\n#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */\r\n\r\n#define RCC_CFGR_MCO2PRE_Pos                   (25U)\r\n#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)\r\n#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */\r\n#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */\r\n#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */\r\n#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */\r\n#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */\r\n\r\n#define RCC_CFGR_MCO2_Pos                      (29U)\r\n#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)\r\n#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */\r\n#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */\r\n#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */\r\n#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for RCC_D1CFGR register  ******************/\r\n/*!< D1HPRE configuration */\r\n#define RCC_D1CFGR_HPRE_Pos                    (0U)\r\n#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */\r\n#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */\r\n#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */\r\n#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */\r\n#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */\r\n#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */\r\n\r\n\r\n#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */\r\n#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)\r\n#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */\r\n#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */\r\n#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)\r\n#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */\r\n#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */\r\n#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)\r\n#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */\r\n#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */\r\n#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)\r\n#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */\r\n#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */\r\n#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)\r\n#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */\r\n#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */\r\n#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)\r\n#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */\r\n#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */\r\n#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)\r\n#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */\r\n#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */\r\n#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)\r\n#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */\r\n#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */\r\n\r\n/*!< D1PPRE configuration */\r\n#define RCC_D1CFGR_D1PPRE_Pos                  (4U)\r\n#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */\r\n#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */\r\n#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */\r\n#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */\r\n#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */\r\n\r\n#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */\r\n#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)\r\n#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */\r\n#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */\r\n#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)\r\n#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */\r\n#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */\r\n#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)\r\n#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */\r\n#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */\r\n#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)\r\n#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */\r\n#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */\r\n\r\n#define RCC_D1CFGR_D1CPRE_Pos                  (8U)\r\n#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */\r\n#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */\r\n#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */\r\n#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */\r\n#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */\r\n#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */\r\n\r\n#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */\r\n#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)\r\n#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */\r\n#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */\r\n#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */\r\n#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */\r\n#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)\r\n#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */\r\n#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */\r\n#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)\r\n#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */\r\n#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */\r\n#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)\r\n#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */\r\n#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */\r\n\r\n/********************  Bit definition for RCC_D2CFGR register  ******************/\r\n/*!< D2PPRE1 configuration */\r\n#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)\r\n#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */\r\n#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */\r\n#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */\r\n#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */\r\n#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */\r\n\r\n#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */\r\n#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */\r\n\r\n/*!< D2PPRE2 configuration */\r\n#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)\r\n#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */\r\n#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */\r\n#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */\r\n#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */\r\n#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */\r\n\r\n#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */\r\n#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */\r\n\r\n/********************  Bit definition for RCC_D3CFGR register  ******************/\r\n/*!< D3PPRE configuration */\r\n#define RCC_D3CFGR_D3PPRE_Pos                  (4U)\r\n#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */\r\n#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */\r\n#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */\r\n#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */\r\n#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */\r\n\r\n#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */\r\n#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)\r\n#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */\r\n#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */\r\n#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)\r\n#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */\r\n#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */\r\n#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)\r\n#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */\r\n#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */\r\n#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)\r\n#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */\r\n#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */\r\n\r\n/********************  Bit definition for RCC_PLLCKSELR register  *************/\r\n\r\n#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)\r\n#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */\r\n#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk\r\n\r\n#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */\r\n#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)\r\n#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */\r\n#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */\r\n#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)\r\n#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */\r\n#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */\r\n#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)\r\n#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */\r\n#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */\r\n\r\n#define RCC_PLLCKSELR_DIVM1_Pos                (4U)\r\n#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */\r\n#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk\r\n#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */\r\n#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */\r\n#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */\r\n#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */\r\n#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */\r\n#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */\r\n\r\n#define RCC_PLLCKSELR_DIVM2_Pos                (12U)\r\n#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */\r\n#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk\r\n#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */\r\n#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */\r\n#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */\r\n#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */\r\n#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */\r\n#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */\r\n\r\n#define RCC_PLLCKSELR_DIVM3_Pos                (20U)\r\n#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */\r\n#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk\r\n#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */\r\n#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */\r\n#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */\r\n#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */\r\n#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */\r\n#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */\r\n\r\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\r\n\r\n#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)\r\n#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */\r\n#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk\r\n#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)\r\n#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */\r\n#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk\r\n#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)\r\n#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\r\n#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk\r\n#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */\r\n#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */\r\n#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */\r\n#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\r\n\r\n#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)\r\n#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */\r\n#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk\r\n#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)\r\n#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */\r\n#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk\r\n#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)\r\n#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\r\n#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk\r\n#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */\r\n#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */\r\n#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */\r\n#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\r\n\r\n#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)\r\n#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */\r\n#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk\r\n#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)\r\n#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */\r\n#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk\r\n#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)\r\n#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\r\n#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk\r\n#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */\r\n#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */\r\n#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */\r\n#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\r\n\r\n#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)\r\n#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */\r\n#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk\r\n#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)\r\n#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */\r\n#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk\r\n#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)\r\n#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */\r\n#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk\r\n\r\n#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)\r\n#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */\r\n#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk\r\n#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)\r\n#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */\r\n#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk\r\n#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)\r\n#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */\r\n#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk\r\n\r\n#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)\r\n#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */\r\n#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk\r\n#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)\r\n#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */\r\n#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk\r\n#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)\r\n#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */\r\n#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_PLL1DIVR register  ***************/\r\n#define RCC_PLL1DIVR_N1_Pos                    (0U)\r\n#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */\r\n#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk\r\n#define RCC_PLL1DIVR_P1_Pos                    (9U)\r\n#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */\r\n#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk\r\n#define RCC_PLL1DIVR_Q1_Pos                    (16U)\r\n#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */\r\n#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk\r\n#define RCC_PLL1DIVR_R1_Pos                    (24U)\r\n#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */\r\n#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk\r\n\r\n/********************  Bit definition for RCC_PLL1FRACR register  ***************/\r\n#define RCC_PLL1FRACR_FRACN1_Pos               (3U)\r\n#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */\r\n#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk\r\n\r\n/********************  Bit definition for RCC_PLL2DIVR register  ***************/\r\n#define RCC_PLL2DIVR_N2_Pos                    (0U)\r\n#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */\r\n#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk\r\n#define RCC_PLL2DIVR_P2_Pos                    (9U)\r\n#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */\r\n#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk\r\n#define RCC_PLL2DIVR_Q2_Pos                    (16U)\r\n#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */\r\n#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk\r\n#define RCC_PLL2DIVR_R2_Pos                    (24U)\r\n#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */\r\n#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk\r\n\r\n/********************  Bit definition for RCC_PLL2FRACR register  ***************/\r\n#define RCC_PLL2FRACR_FRACN2_Pos               (3U)\r\n#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */\r\n#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk\r\n\r\n/********************  Bit definition for RCC_PLL3DIVR register  ***************/\r\n#define RCC_PLL3DIVR_N3_Pos                    (0U)\r\n#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */\r\n#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk\r\n#define RCC_PLL3DIVR_P3_Pos                    (9U)\r\n#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */\r\n#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk\r\n#define RCC_PLL3DIVR_Q3_Pos                    (16U)\r\n#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */\r\n#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk\r\n#define RCC_PLL3DIVR_R3_Pos                    (24U)\r\n#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */\r\n#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk\r\n\r\n/********************  Bit definition for RCC_PLL3FRACR register  ***************/\r\n#define RCC_PLL3FRACR_FRACN3_Pos               (3U)\r\n#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */\r\n#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk\r\n\r\n/********************  Bit definition for RCC_D1CCIPR register  ***************/\r\n#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)\r\n#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */\r\n#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk\r\n#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D1CCIPR_OCTOSPISEL_Pos             (4U)\r\n#define RCC_D1CCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_D1CCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */\r\n#define RCC_D1CCIPR_OCTOSPISEL                 RCC_D1CCIPR_OCTOSPISEL_Msk\r\n#define RCC_D1CCIPR_OCTOSPISEL_0               (0x1UL << RCC_D1CCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */\r\n#define RCC_D1CCIPR_OCTOSPISEL_1               (0x2UL << RCC_D1CCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */\r\n#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)\r\n#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */\r\n#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk\r\n#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)\r\n#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */\r\n#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk\r\n#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for RCC_D2CCIP1R register  ***************/\r\n#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)\r\n#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */\r\n#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk\r\n#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */\r\n\r\n\r\n#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)\r\n#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */\r\n#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk\r\n#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */\r\n#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */\r\n#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */\r\n\r\n#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)\r\n#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */\r\n#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk\r\n#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */\r\n#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */\r\n#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */\r\n\r\n#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)\r\n#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */\r\n#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk\r\n#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */\r\n#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */\r\n\r\n#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)\r\n#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */\r\n#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk\r\n\r\n#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)\r\n#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */\r\n#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk\r\n#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */\r\n\r\n#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)\r\n#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */\r\n#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk\r\n\r\n/********************  Bit definition for RCC_D2CCIP2R register  ***************/\r\n#define RCC_D2CCIP2R_USART16910SEL_Pos         (3U)\r\n#define RCC_D2CCIP2R_USART16910SEL_Msk         (0x7UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000038 */\r\n#define RCC_D2CCIP2R_USART16910SEL             RCC_D2CCIP2R_USART16910SEL_Msk\r\n#define RCC_D2CCIP2R_USART16910SEL_0           (0x1UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000008 */\r\n#define RCC_D2CCIP2R_USART16910SEL_1           (0x2UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000010 */\r\n#define RCC_D2CCIP2R_USART16910SEL_2           (0x4UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000020 */\r\n\r\n#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)\r\n#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */\r\n#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk\r\n#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */\r\n\r\n#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)\r\n#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */\r\n#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk\r\n#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */\r\n#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */\r\n\r\n#define RCC_D2CCIP2R_I2C1235SEL_Pos            (12U)\r\n#define RCC_D2CCIP2R_I2C1235SEL_Msk            (0x3UL << RCC_D2CCIP2R_I2C1235SEL_Pos) /*!< 0x00003000 */\r\n#define RCC_D2CCIP2R_I2C1235SEL                RCC_D2CCIP2R_I2C1235SEL_Msk\r\n#define RCC_D2CCIP2R_I2C1235SEL_0              (0x1UL << RCC_D2CCIP2R_I2C1235SEL_Pos) /*!< 0x00001000 */\r\n#define RCC_D2CCIP2R_I2C1235SEL_1              (0x2UL << RCC_D2CCIP2R_I2C1235SEL_Pos) /*!< 0x00002000 */\r\n\r\n#define RCC_D2CCIP2R_USBSEL_Pos                (20U)\r\n#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */\r\n#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk\r\n#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */\r\n#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */\r\n\r\n#define RCC_D2CCIP2R_CECSEL_Pos                (22U)\r\n#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */\r\n#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk\r\n#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */\r\n#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */\r\n\r\n#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)\r\n#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */\r\n#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk\r\n#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */\r\n#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for RCC_D3CCIPR register  ***************/\r\n#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)\r\n#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */\r\n#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk\r\n#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */\r\n\r\n#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)\r\n#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */\r\n#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk\r\n#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */\r\n#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */\r\n\r\n#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)\r\n#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */\r\n#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk\r\n#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */\r\n#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */\r\n#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */\r\n\r\n#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)\r\n#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */\r\n#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk\r\n#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */\r\n#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */\r\n#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */\r\n\r\n#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)\r\n#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */\r\n#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk\r\n#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */\r\n#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */\r\n#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */\r\n\r\n#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)\r\n#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */\r\n#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk\r\n#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */\r\n#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */\r\n#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */\r\n\r\n#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)\r\n#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */\r\n#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk\r\n#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */\r\n#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */\r\n\r\n#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)\r\n#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */\r\n#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk\r\n#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */\r\n#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */\r\n/********************  Bit definition for RCC_CIER register  ******************/\r\n#define RCC_CIER_LSIRDYIE_Pos                  (0U)\r\n#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */\r\n#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk\r\n#define RCC_CIER_LSERDYIE_Pos                  (1U)\r\n#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */\r\n#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk\r\n#define RCC_CIER_HSIRDYIE_Pos                  (2U)\r\n#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */\r\n#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk\r\n#define RCC_CIER_HSERDYIE_Pos                  (3U)\r\n#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */\r\n#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk\r\n#define RCC_CIER_CSIRDYIE_Pos                  (4U)\r\n#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */\r\n#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk\r\n#define RCC_CIER_HSI48RDYIE_Pos                (5U)\r\n#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */\r\n#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk\r\n#define RCC_CIER_PLL1RDYIE_Pos                 (6U)\r\n#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */\r\n#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk\r\n#define RCC_CIER_PLL2RDYIE_Pos                 (7U)\r\n#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */\r\n#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk\r\n#define RCC_CIER_PLL3RDYIE_Pos                 (8U)\r\n#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */\r\n#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk\r\n#define RCC_CIER_LSECSSIE_Pos                  (9U)\r\n#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */\r\n#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk\r\n\r\n/********************  Bit definition for RCC_CIFR register  ******************/\r\n#define RCC_CIFR_LSIRDYF_Pos                   (0U)\r\n#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */\r\n#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk\r\n#define RCC_CIFR_LSERDYF_Pos                   (1U)\r\n#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */\r\n#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk\r\n#define RCC_CIFR_HSIRDYF_Pos                   (2U)\r\n#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */\r\n#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk\r\n#define RCC_CIFR_HSERDYF_Pos                   (3U)\r\n#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */\r\n#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk\r\n#define RCC_CIFR_CSIRDYF_Pos                   (4U)\r\n#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */\r\n#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk\r\n#define RCC_CIFR_HSI48RDYF_Pos                 (5U)\r\n#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */\r\n#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk\r\n#define RCC_CIFR_PLLRDYF_Pos                   (6U)\r\n#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */\r\n#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk\r\n#define RCC_CIFR_PLL2RDYF_Pos                  (7U)\r\n#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */\r\n#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk\r\n#define RCC_CIFR_PLL3RDYF_Pos                  (8U)\r\n#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */\r\n#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk\r\n#define RCC_CIFR_LSECSSF_Pos                   (9U)\r\n#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */\r\n#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk\r\n#define RCC_CIFR_HSECSSF_Pos                   (10U)\r\n#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */\r\n#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk\r\n\r\n/********************  Bit definition for RCC_CICR register  ******************/\r\n#define RCC_CICR_LSIRDYC_Pos                   (0U)\r\n#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */\r\n#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk\r\n#define RCC_CICR_LSERDYC_Pos                   (1U)\r\n#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */\r\n#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk\r\n#define RCC_CICR_HSIRDYC_Pos                   (2U)\r\n#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */\r\n#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk\r\n#define RCC_CICR_HSERDYC_Pos                   (3U)\r\n#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */\r\n#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk\r\n#define RCC_CICR_CSIRDYC_Pos                   (4U)\r\n#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */\r\n#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk\r\n#define RCC_CICR_HSI48RDYC_Pos                 (5U)\r\n#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */\r\n#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk\r\n#define RCC_CICR_PLLRDYC_Pos                   (6U)\r\n#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */\r\n#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk\r\n#define RCC_CICR_PLL2RDYC_Pos                  (7U)\r\n#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */\r\n#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk\r\n#define RCC_CICR_PLL3RDYC_Pos                  (8U)\r\n#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */\r\n#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk\r\n#define RCC_CICR_LSECSSC_Pos                   (9U)\r\n#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */\r\n#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk\r\n#define RCC_CICR_HSECSSC_Pos                   (10U)\r\n#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */\r\n#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk\r\n\r\n/********************  Bit definition for RCC_BDCR register  ******************/\r\n#define RCC_BDCR_LSEON_Pos                     (0U)\r\n#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */\r\n#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk\r\n#define RCC_BDCR_LSERDY_Pos                    (1U)\r\n#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */\r\n#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk\r\n#define RCC_BDCR_LSEBYP_Pos                    (2U)\r\n#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */\r\n#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk\r\n\r\n#define RCC_BDCR_LSEDRV_Pos                    (3U)\r\n#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */\r\n#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk\r\n#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */\r\n#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */\r\n\r\n#define RCC_BDCR_LSECSSON_Pos                  (5U)\r\n#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */\r\n#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk\r\n#define RCC_BDCR_LSECSSD_Pos                   (6U)\r\n#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */\r\n#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk\r\n\r\n#define RCC_BDCR_RTCSEL_Pos                    (8U)\r\n#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */\r\n#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk\r\n#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */\r\n#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */\r\n\r\n#define RCC_BDCR_RTCEN_Pos                     (15U)\r\n#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */\r\n#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk\r\n#define RCC_BDCR_VSWRST_Pos                    (16U)\r\n#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */\r\n#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk\r\n/* Legacy define */\r\n#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos\r\n#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk\r\n#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST\r\n/********************  Bit definition for RCC_CSR register  *******************/\r\n#define RCC_CSR_LSION_Pos                      (0U)\r\n#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */\r\n#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk\r\n#define RCC_CSR_LSIRDY_Pos                     (1U)\r\n#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */\r\n#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_AHB3ENR register  **************/\r\n#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)\r\n#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */\r\n#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk\r\n#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)\r\n#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */\r\n#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk\r\n#define RCC_AHB3ENR_FMCEN_Pos                  (12U)\r\n#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */\r\n#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk\r\n#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)\r\n#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */\r\n#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk\r\n#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)\r\n#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */\r\n#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk\r\n#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)\r\n#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */\r\n#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk\r\n#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)\r\n#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */\r\n#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk\r\n#define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)\r\n#define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */\r\n#define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk\r\n#define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)\r\n#define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */\r\n#define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\r\n#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)\r\n#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */\r\n#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk\r\n#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)\r\n#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */\r\n#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk\r\n#define RCC_AHB1ENR_ADC12EN_Pos                (5U)\r\n#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */\r\n#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk\r\n#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)\r\n#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */\r\n#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk\r\n#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)\r\n#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */\r\n#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk\r\n#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)\r\n#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */\r\n#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk\r\n#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)\r\n#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */\r\n#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk\r\n#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)\r\n#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */\r\n#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\r\n#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)\r\n#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */\r\n#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk\r\n#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)\r\n#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */\r\n#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk\r\n#define RCC_AHB2ENR_HASHEN_Pos                 (5U)\r\n#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */\r\n#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk\r\n#define RCC_AHB2ENR_RNGEN_Pos                  (6U)\r\n#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */\r\n#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk\r\n#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)\r\n#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */\r\n#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk\r\n#define RCC_AHB2ENR_FMACEN_Pos                 (16U)\r\n#define RCC_AHB2ENR_FMACEN_Msk                 (0x1UL << RCC_AHB2ENR_FMACEN_Pos)          /*!< 0x00010000 */\r\n#define RCC_AHB2ENR_FMACEN                     RCC_AHB2ENR_FMACEN_Msk\r\n#define RCC_AHB2ENR_CORDICEN_Pos               (17U)\r\n#define RCC_AHB2ENR_CORDICEN_Msk               (0x1UL << RCC_AHB2ENR_CORDICEN_Pos)        /*!< 0x00020000 */\r\n#define RCC_AHB2ENR_CORDICEN                   RCC_AHB2ENR_CORDICEN_Msk\r\n#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)\r\n#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */\r\n#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk\r\n#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)\r\n#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */\r\n#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos\r\n#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk\r\n#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN\r\n/* Legacy define */\r\n#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos\r\n#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk\r\n#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN\r\n#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos\r\n#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk\r\n#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN\r\n\r\n/********************  Bit definition for RCC_AHB4ENR register  ******************/\r\n#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)\r\n#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */\r\n#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk\r\n#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)\r\n#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */\r\n#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk\r\n#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)\r\n#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */\r\n#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk\r\n#define RCC_AHB4ENR_GPIODEN_Pos                (3U)\r\n#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */\r\n#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk\r\n#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)\r\n#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */\r\n#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk\r\n#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)\r\n#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */\r\n#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk\r\n#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)\r\n#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */\r\n#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk\r\n#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)\r\n#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */\r\n#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk\r\n#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)\r\n#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */\r\n#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk\r\n#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)\r\n#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */\r\n#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk\r\n#define RCC_AHB4ENR_CRCEN_Pos                  (19U)\r\n#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */\r\n#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk\r\n#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)\r\n#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */\r\n#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk\r\n#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)\r\n#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */\r\n#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk\r\n#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)\r\n#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */\r\n#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk\r\n#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)\r\n#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */\r\n#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB3ENR register  ******************/\r\n#define RCC_APB3ENR_LTDCEN_Pos                 (3U)\r\n#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk\r\n#define RCC_APB3ENR_WWDG1EN_Pos                (6U)\r\n#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk\r\n\r\n/********************  Bit definition for RCC_APB1LENR register  ******************/\r\n\r\n#define RCC_APB1LENR_TIM2EN_Pos                (0U)\r\n#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk\r\n#define RCC_APB1LENR_TIM3EN_Pos                (1U)\r\n#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk\r\n#define RCC_APB1LENR_TIM4EN_Pos                (2U)\r\n#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk\r\n#define RCC_APB1LENR_TIM5EN_Pos                (3U)\r\n#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk\r\n#define RCC_APB1LENR_TIM6EN_Pos                (4U)\r\n#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk\r\n#define RCC_APB1LENR_TIM7EN_Pos                (5U)\r\n#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk\r\n#define RCC_APB1LENR_TIM12EN_Pos               (6U)\r\n#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk\r\n#define RCC_APB1LENR_TIM13EN_Pos               (7U)\r\n#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk\r\n#define RCC_APB1LENR_TIM14EN_Pos               (8U)\r\n#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk\r\n#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)\r\n#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk\r\n\r\n\r\n#define RCC_APB1LENR_SPI2EN_Pos                (14U)\r\n#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk\r\n#define RCC_APB1LENR_SPI3EN_Pos                (15U)\r\n#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk\r\n#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)\r\n#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk\r\n#define RCC_APB1LENR_USART2EN_Pos              (17U)\r\n#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk\r\n#define RCC_APB1LENR_USART3EN_Pos              (18U)\r\n#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk\r\n#define RCC_APB1LENR_UART4EN_Pos               (19U)\r\n#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk\r\n#define RCC_APB1LENR_UART5EN_Pos               (20U)\r\n#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk\r\n#define RCC_APB1LENR_I2C1EN_Pos                (21U)\r\n#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk\r\n#define RCC_APB1LENR_I2C2EN_Pos                (22U)\r\n#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk\r\n#define RCC_APB1LENR_I2C3EN_Pos                (23U)\r\n#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk\r\n#define RCC_APB1LENR_I2C5EN_Pos                (25U)\r\n#define RCC_APB1LENR_I2C5EN_Msk                (0x1UL << RCC_APB1LENR_I2C5EN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LENR_I2C5EN                    RCC_APB1LENR_I2C5EN_Msk\r\n#define RCC_APB1LENR_CECEN_Pos                 (27U)\r\n#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk\r\n#define RCC_APB1LENR_DAC12EN_Pos               (29U)\r\n#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk\r\n#define RCC_APB1LENR_UART7EN_Pos               (30U)\r\n#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk\r\n#define RCC_APB1LENR_UART8EN_Pos               (31U)\r\n#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos\r\n#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk\r\n#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN\r\n/********************  Bit definition for RCC_APB1HENR register  ******************/\r\n#define RCC_APB1HENR_CRSEN_Pos                 (1U)\r\n#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk\r\n#define RCC_APB1HENR_SWPMIEN_Pos               (2U)\r\n#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk\r\n#define RCC_APB1HENR_OPAMPEN_Pos               (4U)\r\n#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk\r\n#define RCC_APB1HENR_MDIOSEN_Pos               (5U)\r\n#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk\r\n#define RCC_APB1HENR_FDCANEN_Pos               (8U)\r\n#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk\r\n#define RCC_APB1HENR_TIM23EN_Pos               (24U)\r\n#define RCC_APB1HENR_TIM23EN_Msk               (0x1UL << RCC_APB1HENR_TIM23EN_Pos) /*!< 0x01000000 */\r\n#define RCC_APB1HENR_TIM23EN                   RCC_APB1HENR_TIM23EN_Msk\r\n#define RCC_APB1HENR_TIM24EN_Pos               (25U)\r\n#define RCC_APB1HENR_TIM24EN_Msk               (0x1UL << RCC_APB1HENR_TIM24EN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1HENR_TIM24EN                   RCC_APB1HENR_TIM24EN_Msk\r\n\r\n/********************  Bit definition for RCC_APB2ENR register  ******************/\r\n#define RCC_APB2ENR_TIM1EN_Pos                 (0U)\r\n#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk\r\n#define RCC_APB2ENR_TIM8EN_Pos                 (1U)\r\n#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk\r\n#define RCC_APB2ENR_USART1EN_Pos               (4U)\r\n#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk\r\n#define RCC_APB2ENR_USART6EN_Pos               (5U)\r\n#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk\r\n#define RCC_APB2ENR_UART9EN_Pos                (6U)\r\n#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk\r\n#define RCC_APB2ENR_USART10EN_Pos              (7U)\r\n#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk\r\n#define RCC_APB2ENR_SPI1EN_Pos                 (12U)\r\n#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk\r\n#define RCC_APB2ENR_SPI4EN_Pos                 (13U)\r\n#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk\r\n#define RCC_APB2ENR_TIM15EN_Pos                (16U)\r\n#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk\r\n#define RCC_APB2ENR_TIM16EN_Pos                (17U)\r\n#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk\r\n#define RCC_APB2ENR_TIM17EN_Pos                (18U)\r\n#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk\r\n#define RCC_APB2ENR_SPI5EN_Pos                 (20U)\r\n#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk\r\n#define RCC_APB2ENR_SAI1EN_Pos                 (22U)\r\n#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk\r\n#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)\r\n#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk\r\n\r\n/********************  Bit definition for RCC_APB4ENR register  ******************/\r\n#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)\r\n#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk\r\n#define RCC_APB4ENR_LPUART1EN_Pos              (3U)\r\n#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk\r\n#define RCC_APB4ENR_SPI6EN_Pos                 (5U)\r\n#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk\r\n#define RCC_APB4ENR_I2C4EN_Pos                 (7U)\r\n#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk\r\n#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)\r\n#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk\r\n#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)\r\n#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */\r\n#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk\r\n#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)\r\n#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */\r\n#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk\r\n#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)\r\n#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk\r\n#define RCC_APB4ENR_COMP12EN_Pos               (14U)\r\n#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk\r\n#define RCC_APB4ENR_VREFEN_Pos                 (15U)\r\n#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk\r\n#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)\r\n#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk\r\n#define RCC_APB4ENR_SAI4EN_Pos                 (21U)\r\n#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk\r\n\r\n#define RCC_APB4ENR_DTSEN_Pos                  (26U)\r\n#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */\r\n#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB3RSTR register  ***************/\r\n#define RCC_AHB3RSTR_MDMARST_Pos               (0U)\r\n#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */\r\n#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk\r\n#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)\r\n#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */\r\n#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk\r\n#define RCC_AHB3RSTR_FMCRST_Pos                (12U)\r\n#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */\r\n#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk\r\n#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)\r\n#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */\r\n#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk\r\n#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)\r\n#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */\r\n#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk\r\n#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)\r\n#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */\r\n#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk\r\n#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)\r\n#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */\r\n#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk\r\n#define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)\r\n#define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */\r\n#define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk\r\n#define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)\r\n#define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */\r\n#define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk\r\n#define RCC_AHB3RSTR_CPURST_Pos                (31U)\r\n#define RCC_AHB3RSTR_CPURST_Msk                (0x1UL << RCC_AHB3RSTR_CPURST_Pos)      /*!< 0x80000000 */\r\n#define RCC_AHB3RSTR_CPURST                    RCC_AHB3RSTR_CPURST_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_AHB1RSTR register  ***************/\r\n#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)\r\n#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */\r\n#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk\r\n#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)\r\n#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */\r\n#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk\r\n#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)\r\n#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */\r\n#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk\r\n#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)\r\n#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */\r\n#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk\r\n#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)\r\n#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */\r\n#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk\r\n\r\n/********************  Bit definition for RCC_AHB2RSTR register  ***************/\r\n#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)\r\n#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */\r\n#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk\r\n#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)\r\n#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */\r\n#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk\r\n#define RCC_AHB2RSTR_HASHRST_Pos               (5U)\r\n#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */\r\n#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk\r\n#define RCC_AHB2RSTR_RNGRST_Pos                (6U)\r\n#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */\r\n#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk\r\n#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)\r\n#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */\r\n#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk\r\n#define RCC_AHB2RSTR_FMACRST_Pos               (16U)\r\n#define RCC_AHB2RSTR_FMACRST_Msk               (0x1UL << RCC_AHB2RSTR_FMACRST_Pos)       /*!< 0x00010000 */\r\n#define RCC_AHB2RSTR_FMACRST                   RCC_AHB2RSTR_FMACRST_Msk\r\n#define RCC_AHB2RSTR_CORDICRST_Pos             (17U)\r\n#define RCC_AHB2RSTR_CORDICRST_Msk             (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos)     /*!< 0x00020000 */\r\n#define RCC_AHB2RSTR_CORDICRST                 RCC_AHB2RSTR_CORDICRST_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos\r\n#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk\r\n#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST\r\n/********************  Bit definition for RCC_AHB4RSTR register  ******************/\r\n#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)\r\n#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */\r\n#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk\r\n#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)\r\n#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */\r\n#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk\r\n#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)\r\n#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */\r\n#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk\r\n#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)\r\n#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */\r\n#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk\r\n#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)\r\n#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */\r\n#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk\r\n#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)\r\n#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */\r\n#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk\r\n#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)\r\n#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */\r\n#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk\r\n#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)\r\n#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */\r\n#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk\r\n#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)\r\n#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */\r\n#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk\r\n#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)\r\n#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */\r\n#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk\r\n#define RCC_AHB4RSTR_CRCRST_Pos                (19U)\r\n#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */\r\n#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk\r\n#define RCC_AHB4RSTR_BDMARST_Pos               (21U)\r\n#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */\r\n#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk\r\n#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)\r\n#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */\r\n#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk\r\n#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)\r\n#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */\r\n#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_APB3RSTR register  ******************/\r\n#define RCC_APB3RSTR_LTDCRST_Pos               (3U)\r\n#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */\r\n#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk\r\n\r\n/********************  Bit definition for RCC_APB1LRSTR register  ******************/\r\n\r\n#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)\r\n#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk\r\n#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)\r\n#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk\r\n#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)\r\n#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk\r\n#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)\r\n#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk\r\n#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)\r\n#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk\r\n#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)\r\n#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk\r\n#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)\r\n#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk\r\n#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)\r\n#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk\r\n#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)\r\n#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk\r\n#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)\r\n#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk\r\n#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)\r\n#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk\r\n#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)\r\n#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk\r\n#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)\r\n#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk\r\n#define RCC_APB1LRSTR_USART2RST_Pos            (17U)\r\n#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk\r\n#define RCC_APB1LRSTR_USART3RST_Pos            (18U)\r\n#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk\r\n#define RCC_APB1LRSTR_UART4RST_Pos             (19U)\r\n#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk\r\n#define RCC_APB1LRSTR_UART5RST_Pos             (20U)\r\n#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk\r\n#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)\r\n#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk\r\n#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)\r\n#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk\r\n#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)\r\n#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk\r\n#define RCC_APB1LRSTR_I2C5RST_Pos              (25U)\r\n#define RCC_APB1LRSTR_I2C5RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C5RST_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LRSTR_I2C5RST                  RCC_APB1LRSTR_I2C5RST_Msk\r\n#define RCC_APB1LRSTR_CECRST_Pos               (27U)\r\n#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk\r\n#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)\r\n#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk\r\n#define RCC_APB1LRSTR_UART7RST_Pos             (30U)\r\n#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk\r\n#define RCC_APB1LRSTR_UART8RST_Pos             (31U)\r\n#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos\r\n#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk\r\n#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST\r\n/********************  Bit definition for RCC_APB1HRSTR register  ******************/\r\n#define RCC_APB1HRSTR_CRSRST_Pos               (1U)\r\n#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk\r\n#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)\r\n#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk\r\n#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)\r\n#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk\r\n#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)\r\n#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk\r\n#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)\r\n#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk\r\n#define RCC_APB1HRSTR_TIM23RST_Pos             (24U)\r\n#define RCC_APB1HRSTR_TIM23RST_Msk             (0x1UL << RCC_APB1HRSTR_TIM23RST_Pos) /*!< 0x01000000 */\r\n#define RCC_APB1HRSTR_TIM23RST                 RCC_APB1HRSTR_TIM23RST_Msk\r\n#define RCC_APB1HRSTR_TIM24RST_Pos             (25U)\r\n#define RCC_APB1HRSTR_TIM24RST_Msk             (0x1UL << RCC_APB1HRSTR_TIM24RST_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1HRSTR_TIM24RST                 RCC_APB1HRSTR_TIM24RST_Msk\r\n\r\n/********************  Bit definition for RCC_APB2RSTR register  ******************/\r\n#define RCC_APB2RSTR_TIM1RST_Pos               (0U)\r\n#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk\r\n#define RCC_APB2RSTR_TIM8RST_Pos               (1U)\r\n#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk\r\n#define RCC_APB2RSTR_USART1RST_Pos             (4U)\r\n#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk\r\n#define RCC_APB2RSTR_USART6RST_Pos             (5U)\r\n#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk\r\n#define RCC_APB2RSTR_UART9RST_Pos              (6U)\r\n#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */\r\n#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk\r\n#define RCC_APB2RSTR_USART10RST_Pos            (7U)\r\n#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk\r\n#define RCC_APB2RSTR_SPI1RST_Pos               (12U)\r\n#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk\r\n#define RCC_APB2RSTR_SPI4RST_Pos               (13U)\r\n#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk\r\n#define RCC_APB2RSTR_TIM15RST_Pos              (16U)\r\n#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk\r\n#define RCC_APB2RSTR_TIM16RST_Pos              (17U)\r\n#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk\r\n#define RCC_APB2RSTR_TIM17RST_Pos              (18U)\r\n#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk\r\n#define RCC_APB2RSTR_SPI5RST_Pos               (20U)\r\n#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk\r\n#define RCC_APB2RSTR_SAI1RST_Pos               (22U)\r\n#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk\r\n#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)\r\n#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */\r\n#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk\r\n\r\n/********************  Bit definition for RCC_APB4RSTR register  ******************/\r\n#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)\r\n#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk\r\n#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)\r\n#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */\r\n#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk\r\n#define RCC_APB4RSTR_SPI6RST_Pos               (5U)\r\n#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk\r\n#define RCC_APB4RSTR_I2C4RST_Pos               (7U)\r\n#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk\r\n#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)\r\n#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */\r\n#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk\r\n#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)\r\n#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */\r\n#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk\r\n#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)\r\n#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */\r\n#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk\r\n#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)\r\n#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */\r\n#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk\r\n#define RCC_APB4RSTR_COMP12RST_Pos             (14U)\r\n#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */\r\n#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk\r\n#define RCC_APB4RSTR_VREFRST_Pos               (15U)\r\n#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */\r\n#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk\r\n#define RCC_APB4RSTR_SAI4RST_Pos               (21U)\r\n#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */\r\n#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk\r\n\r\n#define RCC_APB4RSTR_DTSRST_Pos                (26U)\r\n#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */\r\n#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk\r\n\r\n/********************  Bit definition for RCC_GCR register  ********************/\r\n#define RCC_GCR_WW1RSC_Pos                     (0U)\r\n#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */\r\n#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk\r\n\r\n/********************  Bit definition for RCC_D3AMR register  ********************/\r\n#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)\r\n#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */\r\n#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk\r\n#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)\r\n#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */\r\n#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk\r\n#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)\r\n#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */\r\n#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk\r\n#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)\r\n#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */\r\n#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk\r\n#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)\r\n#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */\r\n#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk\r\n#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)\r\n#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */\r\n#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk\r\n#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)\r\n#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */\r\n#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk\r\n#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)\r\n#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */\r\n#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk\r\n#define RCC_D3AMR_COMP12AMEN_Pos               (14U)\r\n#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */\r\n#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk\r\n#define RCC_D3AMR_VREFAMEN_Pos                 (15U)\r\n#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */\r\n#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk\r\n#define RCC_D3AMR_RTCAMEN_Pos                  (16U)\r\n#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */\r\n#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk\r\n#define RCC_D3AMR_CRCAMEN_Pos                  (19U)\r\n#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */\r\n#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk\r\n#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)\r\n#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */\r\n#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk\r\n#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)\r\n#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */\r\n#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk\r\n\r\n#define RCC_D3AMR_DTSAMEN_Pos                  (26U)\r\n#define RCC_D3AMR_DTSAMEN_Msk                  (0x1UL << RCC_D3AMR_DTSAMEN_Pos) /*!< 0x04000000 */\r\n#define RCC_D3AMR_DTSAMEN                      RCC_D3AMR_DTSAMEN_Msk\r\n\r\n#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)\r\n#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */\r\n#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk\r\n#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)\r\n#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */\r\n#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk\r\n/********************  Bit definition for RCC_AHB3LPENR register  **************/\r\n#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)\r\n#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */\r\n#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk\r\n#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)\r\n#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */\r\n#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk\r\n#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)\r\n#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */\r\n#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk\r\n#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)\r\n#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */\r\n#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk\r\n#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)\r\n#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */\r\n#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk\r\n#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)\r\n#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */\r\n#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk\r\n#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)\r\n#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */\r\n#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk\r\n#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)\r\n#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */\r\n#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk\r\n#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)\r\n#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */\r\n#define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk\r\n#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)\r\n#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */\r\n#define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk\r\n#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)\r\n#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */\r\n#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk\r\n#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)\r\n#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */\r\n#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk\r\n#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)\r\n#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */\r\n#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk\r\n#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)\r\n#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */\r\n#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_AHB1LPENR register  ***************/\r\n#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)\r\n#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk\r\n#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)\r\n#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk\r\n#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)\r\n#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk\r\n#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)\r\n#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk\r\n#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)\r\n#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk\r\n#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)\r\n#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk\r\n#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)\r\n#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */\r\n#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk\r\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)\r\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB2LPENR register  ***************/\r\n#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)\r\n#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk\r\n#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)\r\n#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk\r\n#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)\r\n#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk\r\n#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)\r\n#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk\r\n#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)\r\n#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk\r\n#define RCC_AHB2LPENR_FMACLPEN_Pos             (16U)\r\n#define RCC_AHB2LPENR_FMACLPEN_Msk             (0x1UL << RCC_AHB2LPENR_FMACLPEN_Pos)     /*!< 0x00010000 */\r\n#define RCC_AHB2LPENR_FMACLPEN                 RCC_AHB2LPENR_FMACLPEN_Msk\r\n#define RCC_AHB2LPENR_CORDICLPEN_Pos           (17U)\r\n#define RCC_AHB2LPENR_CORDICLPEN_Msk           (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos)   /*!< 0x00020000 */\r\n#define RCC_AHB2LPENR_CORDICLPEN               RCC_AHB2LPENR_CORDICLPEN_Msk\r\n#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)\r\n#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk\r\n#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)\r\n#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos\r\n#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk\r\n#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN\r\n#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos\r\n#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk\r\n#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN\r\n#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos\r\n#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk\r\n#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN\r\n\r\n/********************  Bit definition for RCC_AHB4LPENR register  ******************/\r\n#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)\r\n#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)\r\n#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)\r\n#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)\r\n#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)\r\n#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)\r\n#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)\r\n#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)\r\n#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)\r\n#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)\r\n#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\r\n#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk\r\n#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)\r\n#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */\r\n#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk\r\n#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)\r\n#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk\r\n#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)\r\n#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */\r\n#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk\r\n#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)\r\n#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */\r\n#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk\r\n#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)\r\n#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos\r\n#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk\r\n#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN\r\n/********************  Bit definition for RCC_APB3LPENR register  ******************/\r\n#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)\r\n#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk\r\n#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)\r\n#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB1LLPENR register  ******************/\r\n\r\n#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)\r\n#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)\r\n#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)\r\n#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)\r\n#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)\r\n#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)\r\n#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)\r\n#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)\r\n#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)\r\n#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk\r\n#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)\r\n#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk\r\n\r\n\r\n#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)\r\n#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk\r\n#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)\r\n#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk\r\n#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)\r\n#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk\r\n#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)\r\n#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk\r\n#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)\r\n#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk\r\n#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)\r\n#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk\r\n#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)\r\n#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)\r\n#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)\r\n#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)\r\n#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C5LPEN_Pos            (25U)\r\n#define RCC_APB1LLPENR_I2C5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C5LPEN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LLPENR_I2C5LPEN                RCC_APB1LLPENR_I2C5LPEN_Msk\r\n#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)\r\n#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk\r\n#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)\r\n#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk\r\n#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)\r\n#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk\r\n#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)\r\n#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos\r\n#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk\r\n#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN\r\n/********************  Bit definition for RCC_APB1HLPENR register  ******************/\r\n#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)\r\n#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk\r\n#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)\r\n#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk\r\n#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)\r\n#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk\r\n#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)\r\n#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk\r\n#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)\r\n#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk\r\n#define RCC_APB1HLPENR_TIM23LPEN_Pos           (24U)\r\n#define RCC_APB1HLPENR_TIM23LPEN_Msk           (0x1UL << RCC_APB1HLPENR_TIM23LPEN_Pos)   /*!< 0x01000000 */\r\n#define RCC_APB1HLPENR_TIM23LPEN                RCC_APB1HLPENR_TIM23LPEN_Msk\r\n#define RCC_APB1HLPENR_TIM24LPEN_Pos           (25U)\r\n#define RCC_APB1HLPENR_TIM24LPEN_Msk           (0x1UL << RCC_APB1HLPENR_TIM24LPEN_Pos)   /*!< 0x02000000 */\r\n#define RCC_APB1HLPENR_TIM24LPEN                RCC_APB1HLPENR_TIM24LPEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB2LPENR register  ******************/\r\n#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)\r\n#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk\r\n#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)\r\n#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk\r\n#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)\r\n#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk\r\n#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)\r\n#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk\r\n#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)\r\n#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk\r\n#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)\r\n#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk\r\n#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)\r\n#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk\r\n#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)\r\n#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk\r\n#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)\r\n#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk\r\n#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)\r\n#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk\r\n#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)\r\n#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk\r\n#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)\r\n#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk\r\n#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)\r\n#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk\r\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)\r\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB4LPENR register  ******************/\r\n#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)\r\n#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk\r\n#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)\r\n#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk\r\n#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)\r\n#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk\r\n#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)\r\n#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)\r\n#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)\r\n#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */\r\n#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)\r\n#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */\r\n#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)\r\n#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk\r\n#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)\r\n#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk\r\n#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)\r\n#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk\r\n#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)\r\n#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk\r\n#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)\r\n#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk\r\n\r\n#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)\r\n#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk\r\n\r\n/********************  Bit definition for RCC_RSR register  *******************/\r\n#define RCC_RSR_RMVF_Pos                       (16U)\r\n#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */\r\n#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk\r\n#define RCC_RSR_CPURSTF_Pos                    (17U)\r\n#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */\r\n#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk\r\n#define RCC_RSR_D1RSTF_Pos                     (19U)\r\n#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */\r\n#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk\r\n#define RCC_RSR_D2RSTF_Pos                     (20U)\r\n#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */\r\n#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk\r\n#define RCC_RSR_BORRSTF_Pos                    (21U)\r\n#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */\r\n#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk\r\n#define RCC_RSR_PINRSTF_Pos                    (22U)\r\n#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */\r\n#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk\r\n#define RCC_RSR_PORRSTF_Pos                    (23U)\r\n#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */\r\n#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk\r\n#define RCC_RSR_SFTRSTF_Pos                    (24U)\r\n#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */\r\n#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk\r\n#define RCC_RSR_IWDG1RSTF_Pos                  (26U)\r\n#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */\r\n#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk\r\n#define RCC_RSR_WWDG1RSTF_Pos                  (28U)\r\n#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */\r\n#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk\r\n\r\n#define RCC_RSR_LPWRRSTF_Pos                   (30U)\r\n#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */\r\n#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    RNG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/***************************    RNG VER  **************************************/\r\n#define RNG_VER_3_2\r\n/********************  Bits definition for RNG_CR register  *******************/\r\n#define RNG_CR_RNGEN_Pos    (2U)\r\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */\r\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\r\n#define RNG_CR_IE_Pos       (3U)\r\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */\r\n#define RNG_CR_IE           RNG_CR_IE_Msk\r\n#define RNG_CR_CED_Pos      (5U)\r\n#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */\r\n#define RNG_CR_CED          RNG_CR_CED_Msk\r\n#define RNG_CR_RNG_CONFIG3_Pos      (8U)\r\n#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */\r\n#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk\r\n#define RNG_CR_NISTC_Pos            (12U)\r\n#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */\r\n#define RNG_CR_NISTC                RNG_CR_NISTC_Msk\r\n#define RNG_CR_RNG_CONFIG2_Pos      (13U)\r\n#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */\r\n#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk\r\n#define RNG_CR_CLKDIV_Pos           (16U)\r\n#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */\r\n#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk\r\n#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */\r\n#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */\r\n#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */\r\n#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */\r\n#define RNG_CR_RNG_CONFIG1_Pos      (20U)\r\n#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */\r\n#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk\r\n#define RNG_CR_CONDRST_Pos         (30U)\r\n#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */\r\n#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk\r\n#define RNG_CR_CONFIGLOCK_Pos      (31U)\r\n#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */\r\n#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk\r\n\r\n/********************  Bits definition for RNG_SR register  *******************/\r\n#define RNG_SR_DRDY_Pos     (0U)\r\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */\r\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\r\n#define RNG_SR_CECS_Pos     (1U)\r\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */\r\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\r\n#define RNG_SR_SECS_Pos     (2U)\r\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */\r\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\r\n#define RNG_SR_CEIS_Pos     (5U)\r\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */\r\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\r\n#define RNG_SR_SEIS_Pos     (6U)\r\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */\r\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Real-Time Clock (RTC)                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for RTC_TR register  *******************/\r\n#define RTC_TR_PM_Pos                  (22U)\r\n#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */\r\n#define RTC_TR_PM                      RTC_TR_PM_Msk\r\n#define RTC_TR_HT_Pos                  (20U)\r\n#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */\r\n#define RTC_TR_HT                      RTC_TR_HT_Msk\r\n#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */\r\n#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */\r\n#define RTC_TR_HU_Pos                  (16U)\r\n#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */\r\n#define RTC_TR_HU                      RTC_TR_HU_Msk\r\n#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */\r\n#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */\r\n#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */\r\n#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */\r\n#define RTC_TR_MNT_Pos                 (12U)\r\n#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */\r\n#define RTC_TR_MNT                     RTC_TR_MNT_Msk\r\n#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */\r\n#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */\r\n#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */\r\n#define RTC_TR_MNU_Pos                 (8U)\r\n#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */\r\n#define RTC_TR_MNU                     RTC_TR_MNU_Msk\r\n#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */\r\n#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */\r\n#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */\r\n#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */\r\n#define RTC_TR_ST_Pos                  (4U)\r\n#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */\r\n#define RTC_TR_ST                      RTC_TR_ST_Msk\r\n#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */\r\n#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */\r\n#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */\r\n#define RTC_TR_SU_Pos                  (0U)\r\n#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */\r\n#define RTC_TR_SU                      RTC_TR_SU_Msk\r\n#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */\r\n#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */\r\n#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */\r\n#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_DR register  *******************/\r\n#define RTC_DR_YT_Pos                  (20U)\r\n#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */\r\n#define RTC_DR_YT                      RTC_DR_YT_Msk\r\n#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */\r\n#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */\r\n#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */\r\n#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */\r\n#define RTC_DR_YU_Pos                  (16U)\r\n#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */\r\n#define RTC_DR_YU                      RTC_DR_YU_Msk\r\n#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */\r\n#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */\r\n#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */\r\n#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */\r\n#define RTC_DR_WDU_Pos                 (13U)\r\n#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */\r\n#define RTC_DR_WDU                     RTC_DR_WDU_Msk\r\n#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */\r\n#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */\r\n#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */\r\n#define RTC_DR_MT_Pos                  (12U)\r\n#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */\r\n#define RTC_DR_MT                      RTC_DR_MT_Msk\r\n#define RTC_DR_MU_Pos                  (8U)\r\n#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */\r\n#define RTC_DR_MU                      RTC_DR_MU_Msk\r\n#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */\r\n#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */\r\n#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */\r\n#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */\r\n#define RTC_DR_DT_Pos                  (4U)\r\n#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */\r\n#define RTC_DR_DT                      RTC_DR_DT_Msk\r\n#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */\r\n#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */\r\n#define RTC_DR_DU_Pos                  (0U)\r\n#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */\r\n#define RTC_DR_DU                      RTC_DR_DU_Msk\r\n#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */\r\n#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */\r\n#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */\r\n#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_CR register  *******************/\r\n#define RTC_CR_ITSE_Pos                (24U)\r\n#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */\r\n#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk\r\n#define RTC_CR_COE_Pos                 (23U)\r\n#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */\r\n#define RTC_CR_COE                     RTC_CR_COE_Msk\r\n#define RTC_CR_OSEL_Pos                (21U)\r\n#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */\r\n#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk\r\n#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */\r\n#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */\r\n#define RTC_CR_POL_Pos                 (20U)\r\n#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */\r\n#define RTC_CR_POL                     RTC_CR_POL_Msk\r\n#define RTC_CR_COSEL_Pos               (19U)\r\n#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */\r\n#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk\r\n#define RTC_CR_BKP_Pos                 (18U)\r\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */\r\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\r\n#define RTC_CR_SUB1H_Pos               (17U)\r\n#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */\r\n#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk\r\n#define RTC_CR_ADD1H_Pos               (16U)\r\n#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */\r\n#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk\r\n#define RTC_CR_TSIE_Pos                (15U)\r\n#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */\r\n#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk\r\n#define RTC_CR_WUTIE_Pos               (14U)\r\n#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */\r\n#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk\r\n#define RTC_CR_ALRBIE_Pos              (13U)\r\n#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */\r\n#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk\r\n#define RTC_CR_ALRAIE_Pos              (12U)\r\n#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */\r\n#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk\r\n#define RTC_CR_TSE_Pos                 (11U)\r\n#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */\r\n#define RTC_CR_TSE                     RTC_CR_TSE_Msk\r\n#define RTC_CR_WUTE_Pos                (10U)\r\n#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */\r\n#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk\r\n#define RTC_CR_ALRBE_Pos               (9U)\r\n#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */\r\n#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk\r\n#define RTC_CR_ALRAE_Pos               (8U)\r\n#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */\r\n#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk\r\n#define RTC_CR_FMT_Pos                 (6U)\r\n#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */\r\n#define RTC_CR_FMT                     RTC_CR_FMT_Msk\r\n#define RTC_CR_BYPSHAD_Pos             (5U)\r\n#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */\r\n#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk\r\n#define RTC_CR_REFCKON_Pos             (4U)\r\n#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */\r\n#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk\r\n#define RTC_CR_TSEDGE_Pos              (3U)\r\n#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */\r\n#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk\r\n#define RTC_CR_WUCKSEL_Pos             (0U)\r\n#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */\r\n#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk\r\n#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */\r\n#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */\r\n#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */\r\n\r\n/********************  Bits definition for RTC_ISR register  ******************/\r\n#define RTC_ISR_ITSF_Pos               (17U)\r\n#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */\r\n#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk\r\n#define RTC_ISR_RECALPF_Pos            (16U)\r\n#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */\r\n#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk\r\n#define RTC_ISR_TAMP3F_Pos             (15U)\r\n#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */\r\n#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk\r\n#define RTC_ISR_TAMP2F_Pos             (14U)\r\n#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */\r\n#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk\r\n#define RTC_ISR_TAMP1F_Pos             (13U)\r\n#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */\r\n#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk\r\n#define RTC_ISR_TSOVF_Pos              (12U)\r\n#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */\r\n#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk\r\n#define RTC_ISR_TSF_Pos                (11U)\r\n#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */\r\n#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk\r\n#define RTC_ISR_WUTF_Pos               (10U)\r\n#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */\r\n#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk\r\n#define RTC_ISR_ALRBF_Pos              (9U)\r\n#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */\r\n#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk\r\n#define RTC_ISR_ALRAF_Pos              (8U)\r\n#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */\r\n#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk\r\n#define RTC_ISR_INIT_Pos               (7U)\r\n#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */\r\n#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk\r\n#define RTC_ISR_INITF_Pos              (6U)\r\n#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */\r\n#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk\r\n#define RTC_ISR_RSF_Pos                (5U)\r\n#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */\r\n#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk\r\n#define RTC_ISR_INITS_Pos              (4U)\r\n#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */\r\n#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk\r\n#define RTC_ISR_SHPF_Pos               (3U)\r\n#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */\r\n#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk\r\n#define RTC_ISR_WUTWF_Pos              (2U)\r\n#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */\r\n#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk\r\n#define RTC_ISR_ALRBWF_Pos             (1U)\r\n#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */\r\n#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk\r\n#define RTC_ISR_ALRAWF_Pos             (0U)\r\n#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */\r\n#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk\r\n\r\n/********************  Bits definition for RTC_PRER register  *****************/\r\n#define RTC_PRER_PREDIV_A_Pos          (16U)\r\n#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */\r\n#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk\r\n#define RTC_PRER_PREDIV_S_Pos          (0U)\r\n#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */\r\n#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk\r\n\r\n/********************  Bits definition for RTC_WUTR register  *****************/\r\n#define RTC_WUTR_WUT_Pos               (0U)\r\n#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */\r\n#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk\r\n\r\n/********************  Bits definition for RTC_ALRMAR register  ***************/\r\n#define RTC_ALRMAR_MSK4_Pos            (31U)\r\n#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */\r\n#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk\r\n#define RTC_ALRMAR_WDSEL_Pos           (30U)\r\n#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */\r\n#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk\r\n#define RTC_ALRMAR_DT_Pos              (28U)\r\n#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */\r\n#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk\r\n#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */\r\n#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */\r\n#define RTC_ALRMAR_DU_Pos              (24U)\r\n#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */\r\n#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk\r\n#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */\r\n#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */\r\n#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */\r\n#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */\r\n#define RTC_ALRMAR_MSK3_Pos            (23U)\r\n#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */\r\n#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk\r\n#define RTC_ALRMAR_PM_Pos              (22U)\r\n#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */\r\n#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk\r\n#define RTC_ALRMAR_HT_Pos              (20U)\r\n#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */\r\n#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk\r\n#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */\r\n#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */\r\n#define RTC_ALRMAR_HU_Pos              (16U)\r\n#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */\r\n#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk\r\n#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */\r\n#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */\r\n#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */\r\n#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */\r\n#define RTC_ALRMAR_MSK2_Pos            (15U)\r\n#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */\r\n#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk\r\n#define RTC_ALRMAR_MNT_Pos             (12U)\r\n#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */\r\n#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk\r\n#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */\r\n#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */\r\n#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */\r\n#define RTC_ALRMAR_MNU_Pos             (8U)\r\n#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */\r\n#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk\r\n#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */\r\n#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */\r\n#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */\r\n#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */\r\n#define RTC_ALRMAR_MSK1_Pos            (7U)\r\n#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */\r\n#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk\r\n#define RTC_ALRMAR_ST_Pos              (4U)\r\n#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */\r\n#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk\r\n#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */\r\n#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */\r\n#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */\r\n#define RTC_ALRMAR_SU_Pos              (0U)\r\n#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */\r\n#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk\r\n#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */\r\n#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */\r\n#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */\r\n#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_ALRMBR register  ***************/\r\n#define RTC_ALRMBR_MSK4_Pos            (31U)\r\n#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */\r\n#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk\r\n#define RTC_ALRMBR_WDSEL_Pos           (30U)\r\n#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */\r\n#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk\r\n#define RTC_ALRMBR_DT_Pos              (28U)\r\n#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */\r\n#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk\r\n#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */\r\n#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */\r\n#define RTC_ALRMBR_DU_Pos              (24U)\r\n#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */\r\n#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk\r\n#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */\r\n#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */\r\n#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */\r\n#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */\r\n#define RTC_ALRMBR_MSK3_Pos            (23U)\r\n#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */\r\n#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk\r\n#define RTC_ALRMBR_PM_Pos              (22U)\r\n#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */\r\n#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk\r\n#define RTC_ALRMBR_HT_Pos              (20U)\r\n#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */\r\n#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk\r\n#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */\r\n#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */\r\n#define RTC_ALRMBR_HU_Pos              (16U)\r\n#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */\r\n#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk\r\n#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */\r\n#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */\r\n#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */\r\n#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */\r\n#define RTC_ALRMBR_MSK2_Pos            (15U)\r\n#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */\r\n#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk\r\n#define RTC_ALRMBR_MNT_Pos             (12U)\r\n#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */\r\n#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk\r\n#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */\r\n#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */\r\n#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */\r\n#define RTC_ALRMBR_MNU_Pos             (8U)\r\n#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */\r\n#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk\r\n#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */\r\n#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */\r\n#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */\r\n#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */\r\n#define RTC_ALRMBR_MSK1_Pos            (7U)\r\n#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */\r\n#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk\r\n#define RTC_ALRMBR_ST_Pos              (4U)\r\n#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */\r\n#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk\r\n#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */\r\n#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */\r\n#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */\r\n#define RTC_ALRMBR_SU_Pos              (0U)\r\n#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */\r\n#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk\r\n#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */\r\n#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */\r\n#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */\r\n#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_WPR register  ******************/\r\n#define RTC_WPR_KEY_Pos                (0U)\r\n#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */\r\n#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk\r\n\r\n/********************  Bits definition for RTC_SSR register  ******************/\r\n#define RTC_SSR_SS_Pos                 (0U)\r\n#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */\r\n#define RTC_SSR_SS                     RTC_SSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_SHIFTR register  ***************/\r\n#define RTC_SHIFTR_SUBFS_Pos           (0U)\r\n#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */\r\n#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk\r\n#define RTC_SHIFTR_ADD1S_Pos           (31U)\r\n#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */\r\n#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk\r\n\r\n/********************  Bits definition for RTC_TSTR register  *****************/\r\n#define RTC_TSTR_PM_Pos                (22U)\r\n#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */\r\n#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk\r\n#define RTC_TSTR_HT_Pos                (20U)\r\n#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */\r\n#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk\r\n#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */\r\n#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */\r\n#define RTC_TSTR_HU_Pos                (16U)\r\n#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */\r\n#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk\r\n#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */\r\n#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */\r\n#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */\r\n#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */\r\n#define RTC_TSTR_MNT_Pos               (12U)\r\n#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */\r\n#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk\r\n#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */\r\n#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */\r\n#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */\r\n#define RTC_TSTR_MNU_Pos               (8U)\r\n#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */\r\n#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk\r\n#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */\r\n#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */\r\n#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */\r\n#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */\r\n#define RTC_TSTR_ST_Pos                (4U)\r\n#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */\r\n#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk\r\n#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */\r\n#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */\r\n#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */\r\n#define RTC_TSTR_SU_Pos                (0U)\r\n#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */\r\n#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk\r\n#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */\r\n#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */\r\n#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */\r\n#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_TSDR register  *****************/\r\n#define RTC_TSDR_WDU_Pos               (13U)\r\n#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */\r\n#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk\r\n#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */\r\n#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */\r\n#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */\r\n#define RTC_TSDR_MT_Pos                (12U)\r\n#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */\r\n#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk\r\n#define RTC_TSDR_MU_Pos                (8U)\r\n#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */\r\n#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk\r\n#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */\r\n#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */\r\n#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */\r\n#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */\r\n#define RTC_TSDR_DT_Pos                (4U)\r\n#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */\r\n#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk\r\n#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */\r\n#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */\r\n#define RTC_TSDR_DU_Pos                (0U)\r\n#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */\r\n#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk\r\n#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */\r\n#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */\r\n#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */\r\n#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_TSSSR register  ****************/\r\n#define RTC_TSSSR_SS_Pos               (0U)\r\n#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */\r\n#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_CALR register  *****************/\r\n#define RTC_CALR_CALP_Pos              (15U)\r\n#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */\r\n#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk\r\n#define RTC_CALR_CALW8_Pos             (14U)\r\n#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */\r\n#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk\r\n#define RTC_CALR_CALW16_Pos            (13U)\r\n#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */\r\n#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk\r\n#define RTC_CALR_CALM_Pos              (0U)\r\n#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */\r\n#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk\r\n#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */\r\n#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */\r\n#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */\r\n#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */\r\n#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */\r\n#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */\r\n#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */\r\n#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */\r\n#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */\r\n\r\n/********************  Bits definition for RTC_TAMPCR register  ***************/\r\n#define RTC_TAMPCR_TAMP3MF_Pos         (24U)\r\n#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */\r\n#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk\r\n#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)\r\n#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */\r\n#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk\r\n#define RTC_TAMPCR_TAMP3IE_Pos         (22U)\r\n#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */\r\n#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk\r\n#define RTC_TAMPCR_TAMP2MF_Pos         (21U)\r\n#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */\r\n#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk\r\n#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)\r\n#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */\r\n#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk\r\n#define RTC_TAMPCR_TAMP2IE_Pos         (19U)\r\n#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */\r\n#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk\r\n#define RTC_TAMPCR_TAMP1MF_Pos         (18U)\r\n#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */\r\n#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk\r\n#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)\r\n#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */\r\n#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk\r\n#define RTC_TAMPCR_TAMP1IE_Pos         (16U)\r\n#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */\r\n#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk\r\n#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)\r\n#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */\r\n#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk\r\n#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)\r\n#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */\r\n#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk\r\n#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */\r\n#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */\r\n#define RTC_TAMPCR_TAMPFLT_Pos         (11U)\r\n#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */\r\n#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk\r\n#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */\r\n#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */\r\n#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)\r\n#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */\r\n#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk\r\n#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */\r\n#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */\r\n#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */\r\n#define RTC_TAMPCR_TAMPTS_Pos          (7U)\r\n#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */\r\n#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk\r\n#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)\r\n#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */\r\n#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk\r\n#define RTC_TAMPCR_TAMP3E_Pos          (5U)\r\n#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */\r\n#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk\r\n#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)\r\n#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */\r\n#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk\r\n#define RTC_TAMPCR_TAMP2E_Pos          (3U)\r\n#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */\r\n#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk\r\n#define RTC_TAMPCR_TAMPIE_Pos          (2U)\r\n#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */\r\n#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk\r\n#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)\r\n#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */\r\n#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk\r\n#define RTC_TAMPCR_TAMP1E_Pos          (0U)\r\n#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */\r\n#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk\r\n\r\n/********************  Bits definition for RTC_ALRMASSR register  *************/\r\n#define RTC_ALRMASSR_MASKSS_Pos        (24U)\r\n#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */\r\n#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk\r\n#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */\r\n#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */\r\n#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */\r\n#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */\r\n#define RTC_ALRMASSR_SS_Pos            (0U)\r\n#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */\r\n#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\r\n#define RTC_ALRMBSSR_MASKSS_Pos        (24U)\r\n#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */\r\n#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk\r\n#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */\r\n#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */\r\n#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */\r\n#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */\r\n#define RTC_ALRMBSSR_SS_Pos            (0U)\r\n#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */\r\n#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_OR register  *******************/\r\n#define RTC_OR_OUT_RMP_Pos             (1U)\r\n#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */\r\n#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk\r\n#define RTC_OR_ALARMOUTTYPE_Pos        (0U)\r\n#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */\r\n#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\r\n\r\n/********************  Bits definition for RTC_BKP0R register  ****************/\r\n#define RTC_BKP0R_Pos                  (0U)\r\n#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP0R                      RTC_BKP0R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP1R register  ****************/\r\n#define RTC_BKP1R_Pos                  (0U)\r\n#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP1R                      RTC_BKP1R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP2R register  ****************/\r\n#define RTC_BKP2R_Pos                  (0U)\r\n#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP2R                      RTC_BKP2R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP3R register  ****************/\r\n#define RTC_BKP3R_Pos                  (0U)\r\n#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP3R                      RTC_BKP3R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP4R register  ****************/\r\n#define RTC_BKP4R_Pos                  (0U)\r\n#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP4R                      RTC_BKP4R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP5R register  ****************/\r\n#define RTC_BKP5R_Pos                  (0U)\r\n#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP5R                      RTC_BKP5R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP6R register  ****************/\r\n#define RTC_BKP6R_Pos                  (0U)\r\n#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP6R                      RTC_BKP6R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP7R register  ****************/\r\n#define RTC_BKP7R_Pos                  (0U)\r\n#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP7R                      RTC_BKP7R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP8R register  ****************/\r\n#define RTC_BKP8R_Pos                  (0U)\r\n#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP8R                      RTC_BKP8R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP9R register  ****************/\r\n#define RTC_BKP9R_Pos                  (0U)\r\n#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP9R                      RTC_BKP9R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP10R register  ***************/\r\n#define RTC_BKP10R_Pos                 (0U)\r\n#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP10R                     RTC_BKP10R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP11R register  ***************/\r\n#define RTC_BKP11R_Pos                 (0U)\r\n#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP11R                     RTC_BKP11R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP12R register  ***************/\r\n#define RTC_BKP12R_Pos                 (0U)\r\n#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP12R                     RTC_BKP12R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP13R register  ***************/\r\n#define RTC_BKP13R_Pos                 (0U)\r\n#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP13R                     RTC_BKP13R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP14R register  ***************/\r\n#define RTC_BKP14R_Pos                 (0U)\r\n#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP14R                     RTC_BKP14R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP15R register  ***************/\r\n#define RTC_BKP15R_Pos                 (0U)\r\n#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP15R                     RTC_BKP15R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP16R register  ***************/\r\n#define RTC_BKP16R_Pos                 (0U)\r\n#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP16R                     RTC_BKP16R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP17R register  ***************/\r\n#define RTC_BKP17R_Pos                 (0U)\r\n#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP17R                     RTC_BKP17R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP18R register  ***************/\r\n#define RTC_BKP18R_Pos                 (0U)\r\n#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP18R                     RTC_BKP18R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP19R register  ***************/\r\n#define RTC_BKP19R_Pos                 (0U)\r\n#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP19R                     RTC_BKP19R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP20R register  ***************/\r\n#define RTC_BKP20R_Pos                 (0U)\r\n#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP20R                     RTC_BKP20R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP21R register  ***************/\r\n#define RTC_BKP21R_Pos                 (0U)\r\n#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP21R                     RTC_BKP21R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP22R register  ***************/\r\n#define RTC_BKP22R_Pos                 (0U)\r\n#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP22R                     RTC_BKP22R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP23R register  ***************/\r\n#define RTC_BKP23R_Pos                 (0U)\r\n#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP23R                     RTC_BKP23R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP24R register  ***************/\r\n#define RTC_BKP24R_Pos                 (0U)\r\n#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP24R                     RTC_BKP24R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP25R register  ***************/\r\n#define RTC_BKP25R_Pos                 (0U)\r\n#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP25R                     RTC_BKP25R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP26R register  ***************/\r\n#define RTC_BKP26R_Pos                 (0U)\r\n#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP26R                     RTC_BKP26R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP27R register  ***************/\r\n#define RTC_BKP27R_Pos                 (0U)\r\n#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP27R                     RTC_BKP27R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP28R register  ***************/\r\n#define RTC_BKP28R_Pos                 (0U)\r\n#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP28R                     RTC_BKP28R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP29R register  ***************/\r\n#define RTC_BKP29R_Pos                 (0U)\r\n#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP29R                     RTC_BKP29R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP30R register  ***************/\r\n#define RTC_BKP30R_Pos                 (0U)\r\n#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP30R                     RTC_BKP30R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP31R register  ***************/\r\n#define RTC_BKP31R_Pos                 (0U)\r\n#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP31R                     RTC_BKP31R_Msk\r\n\r\n/******************** Number of backup registers ******************************/\r\n#define RTC_BKP_NUMBER_Pos             (5U)\r\n#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */\r\n#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                              SPDIF-RX Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for SPDIF_CR register  ******************/\r\n#define SPDIFRX_CR_SPDIFEN_Pos      (0U)\r\n#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */\r\n#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */\r\n#define SPDIFRX_CR_RXDMAEN_Pos      (2U)\r\n#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */\r\n#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */\r\n#define SPDIFRX_CR_RXSTEO_Pos       (3U)\r\n#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */\r\n#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */\r\n#define SPDIFRX_CR_DRFMT_Pos        (4U)\r\n#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */\r\n#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */\r\n#define SPDIFRX_CR_PMSK_Pos         (6U)\r\n#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */\r\n#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */\r\n#define SPDIFRX_CR_VMSK_Pos         (7U)\r\n#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */\r\n#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */\r\n#define SPDIFRX_CR_CUMSK_Pos        (8U)\r\n#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */\r\n#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */\r\n#define SPDIFRX_CR_PTMSK_Pos        (9U)\r\n#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */\r\n#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */\r\n#define SPDIFRX_CR_CBDMAEN_Pos      (10U)\r\n#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */\r\n#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */\r\n#define SPDIFRX_CR_CHSEL_Pos        (11U)\r\n#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */\r\n#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */\r\n#define SPDIFRX_CR_NBTR_Pos         (12U)\r\n#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */\r\n#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */\r\n#define SPDIFRX_CR_WFA_Pos          (14U)\r\n#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */\r\n#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */\r\n#define SPDIFRX_CR_INSEL_Pos        (16U)\r\n#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */\r\n#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */\r\n#define SPDIFRX_CR_CKSEN_Pos        (20U)\r\n#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */\r\n#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */\r\n#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)\r\n#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */\r\n#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */\r\n\r\n/*******************  Bit definition for SPDIFRX_IMR register  *******************/\r\n#define SPDIFRX_IMR_RXNEIE_Pos      (0U)\r\n#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */\r\n#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */\r\n#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)\r\n#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */\r\n#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */\r\n#define SPDIFRX_IMR_PERRIE_Pos      (2U)\r\n#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */\r\n#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */\r\n#define SPDIFRX_IMR_OVRIE_Pos       (3U)\r\n#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */\r\n#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */\r\n#define SPDIFRX_IMR_SBLKIE_Pos      (4U)\r\n#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */\r\n#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */\r\n#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)\r\n#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */\r\n#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */\r\n#define SPDIFRX_IMR_IFEIE_Pos       (6U)\r\n#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */\r\n#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */\r\n\r\n/*******************  Bit definition for SPDIFRX_SR register  *******************/\r\n#define SPDIFRX_SR_RXNE_Pos         (0U)\r\n#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */\r\n#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */\r\n#define SPDIFRX_SR_CSRNE_Pos        (1U)\r\n#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */\r\n#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */\r\n#define SPDIFRX_SR_PERR_Pos         (2U)\r\n#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */\r\n#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */\r\n#define SPDIFRX_SR_OVR_Pos          (3U)\r\n#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */\r\n#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */\r\n#define SPDIFRX_SR_SBD_Pos          (4U)\r\n#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */\r\n#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */\r\n#define SPDIFRX_SR_SYNCD_Pos        (5U)\r\n#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */\r\n#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */\r\n#define SPDIFRX_SR_FERR_Pos         (6U)\r\n#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */\r\n#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */\r\n#define SPDIFRX_SR_SERR_Pos         (7U)\r\n#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */\r\n#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */\r\n#define SPDIFRX_SR_TERR_Pos         (8U)\r\n#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */\r\n#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */\r\n#define SPDIFRX_SR_WIDTH5_Pos       (16U)\r\n#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */\r\n#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */\r\n\r\n/*******************  Bit definition for SPDIFRX_IFCR register  *******************/\r\n#define SPDIFRX_IFCR_PERRCF_Pos     (2U)\r\n#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */\r\n#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */\r\n#define SPDIFRX_IFCR_OVRCF_Pos      (3U)\r\n#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */\r\n#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */\r\n#define SPDIFRX_IFCR_SBDCF_Pos      (4U)\r\n#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */\r\n#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */\r\n#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)\r\n#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */\r\n#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/\r\n#define SPDIFRX_DR0_DR_Pos          (0U)\r\n#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */\r\n#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */\r\n#define SPDIFRX_DR0_PE_Pos          (24U)\r\n#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */\r\n#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */\r\n#define SPDIFRX_DR0_V_Pos           (25U)\r\n#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */\r\n#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */\r\n#define SPDIFRX_DR0_U_Pos           (26U)\r\n#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */\r\n#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */\r\n#define SPDIFRX_DR0_C_Pos           (27U)\r\n#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */\r\n#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */\r\n#define SPDIFRX_DR0_PT_Pos          (28U)\r\n#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */\r\n#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/\r\n#define SPDIFRX_DR1_DR_Pos          (8U)\r\n#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */\r\n#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */\r\n#define SPDIFRX_DR1_PT_Pos          (4U)\r\n#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */\r\n#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */\r\n#define SPDIFRX_DR1_C_Pos           (3U)\r\n#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */\r\n#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */\r\n#define SPDIFRX_DR1_U_Pos           (2U)\r\n#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */\r\n#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */\r\n#define SPDIFRX_DR1_V_Pos           (1U)\r\n#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */\r\n#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */\r\n#define SPDIFRX_DR1_PE_Pos          (0U)\r\n#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */\r\n#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/\r\n#define SPDIFRX_DR1_DRNL1_Pos       (16U)\r\n#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */\r\n#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */\r\n#define SPDIFRX_DR1_DRNL2_Pos       (0U)\r\n#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */\r\n#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */\r\n\r\n/*******************  Bit definition for SPDIFRX_CSR register   *******************/\r\n#define SPDIFRX_CSR_USR_Pos         (0U)\r\n#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */\r\n#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */\r\n#define SPDIFRX_CSR_CS_Pos          (16U)\r\n#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */\r\n#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */\r\n#define SPDIFRX_CSR_SOB_Pos         (24U)\r\n#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */\r\n#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */\r\n\r\n/*******************  Bit definition for SPDIFRX_DIR register    *******************/\r\n#define SPDIFRX_DIR_THI_Pos         (0U)\r\n#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */\r\n#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */\r\n#define SPDIFRX_DIR_TLO_Pos         (16U)\r\n#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */\r\n#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */\r\n\r\n/*******************  Bit definition for SPDIFRX_VERR register    *******************/\r\n#define SPDIFRX_VERR_MINREV_Pos     (0U)\r\n#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */\r\n#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */\r\n#define SPDIFRX_VERR_MAJREV_Pos     (4U)\r\n#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */\r\n#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */\r\n\r\n/*******************  Bit definition for SPDIFRX_IDR register    *******************/\r\n#define SPDIFRX_IDR_ID_Pos          (0U)\r\n#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */\r\n#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */\r\n\r\n/*******************  Bit definition for SPDIFRX_SIDR register    *******************/\r\n#define SPDIFRX_SIDR_SID_Pos        (0U)\r\n#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */\r\n#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Serial Audio Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************************  SAI VERSION  ********************************/\r\n#define SAI_VER_V2_1\r\n\r\n/********************  Bit definition for SAI_GCR register  *******************/\r\n#define SAI_GCR_SYNCIN_Pos         (0U)\r\n#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */\r\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r\n#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\r\n#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\r\n\r\n#define SAI_GCR_SYNCOUT_Pos        (4U)\r\n#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */\r\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r\n#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\r\n#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\r\n\r\n/*******************  Bit definition for SAI_xCR1 register  *******************/\r\n#define SAI_xCR1_MODE_Pos          (0U)\r\n#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */\r\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\r\n#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\r\n#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\r\n\r\n#define SAI_xCR1_PRTCFG_Pos        (2U)\r\n#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */\r\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r\n#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\r\n#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\r\n\r\n#define SAI_xCR1_DS_Pos            (5U)\r\n#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */\r\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\r\n#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\r\n#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\r\n#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\r\n\r\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\r\n#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */\r\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\r\n#define SAI_xCR1_CKSTR_Pos         (9U)\r\n#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */\r\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\r\n\r\n#define SAI_xCR1_SYNCEN_Pos        (10U)\r\n#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */\r\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\r\n#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\r\n#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\r\n\r\n#define SAI_xCR1_MONO_Pos          (12U)\r\n#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */\r\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\r\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\r\n#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */\r\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\r\n#define SAI_xCR1_SAIEN_Pos         (16U)\r\n#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */\r\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\r\n#define SAI_xCR1_DMAEN_Pos         (17U)\r\n#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */\r\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\r\n#define SAI_xCR1_NODIV_Pos         (19U)\r\n#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */\r\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\r\n\r\n#define SAI_xCR1_MCKDIV_Pos        (20U)\r\n#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */\r\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */\r\n#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */\r\n#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */\r\n#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */\r\n#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */\r\n#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */\r\n#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */\r\n\r\n#define SAI_xCR1_MCKEN_Pos         (27U)\r\n#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */\r\n#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */\r\n\r\n#define SAI_xCR1_OSR_Pos           (26U)\r\n#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */\r\n#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */\r\n\r\n/* Legacy define */\r\n#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV\r\n\r\n/*******************  Bit definition for SAI_xCR2 register  *******************/\r\n#define SAI_xCR2_FTH_Pos           (0U)\r\n#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */\r\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\r\n#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\r\n#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\r\n#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\r\n\r\n#define SAI_xCR2_FFLUSH_Pos        (3U)\r\n#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */\r\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\r\n#define SAI_xCR2_TRIS_Pos          (4U)\r\n#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */\r\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\r\n#define SAI_xCR2_MUTE_Pos          (5U)\r\n#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */\r\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\r\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\r\n#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */\r\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\r\n\r\n#define SAI_xCR2_MUTECNT_Pos       (7U)\r\n#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */\r\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\r\n#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\r\n#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\r\n#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\r\n#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\r\n#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\r\n#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\r\n\r\n#define SAI_xCR2_CPL_Pos           (13U)\r\n#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */\r\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\r\n\r\n#define SAI_xCR2_COMP_Pos          (14U)\r\n#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */\r\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\r\n#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\r\n#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\r\n\r\n/******************  Bit definition for SAI_xFRCR register  *******************/\r\n#define SAI_xFRCR_FRL_Pos          (0U)\r\n#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */\r\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */\r\n#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\r\n#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\r\n#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\r\n#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\r\n#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\r\n#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\r\n#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\r\n#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\r\n\r\n#define SAI_xFRCR_FSALL_Pos        (8U)\r\n#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */\r\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */\r\n#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\r\n#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\r\n#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\r\n#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\r\n#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\r\n#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\r\n#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\r\n\r\n#define SAI_xFRCR_FSDEF_Pos        (16U)\r\n#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */\r\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */\r\n#define SAI_xFRCR_FSPOL_Pos        (17U)\r\n#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */\r\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\r\n#define SAI_xFRCR_FSOFF_Pos        (18U)\r\n#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */\r\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\r\n\r\n/* Legacy define */\r\n#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL\r\n\r\n/******************  Bit definition for SAI_xSLOTR register  *******************/\r\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\r\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */\r\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */\r\n#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\r\n#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\r\n#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\r\n#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\r\n#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\r\n\r\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\r\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */\r\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\r\n#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\r\n#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\r\n\r\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\r\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */\r\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r\n#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\r\n#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\r\n#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\r\n#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\r\n\r\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\r\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */\r\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\r\n\r\n/*******************  Bit definition for SAI_xIMR register  *******************/\r\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\r\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */\r\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\r\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\r\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */\r\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\r\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\r\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */\r\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\r\n#define SAI_xIMR_FREQIE_Pos        (3U)\r\n#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */\r\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\r\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\r\n#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */\r\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\r\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\r\n#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */\r\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\r\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\r\n#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */\r\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\r\n\r\n/********************  Bit definition for SAI_xSR register  *******************/\r\n#define SAI_xSR_OVRUDR_Pos         (0U)\r\n#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */\r\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\r\n#define SAI_xSR_MUTEDET_Pos        (1U)\r\n#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */\r\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\r\n#define SAI_xSR_WCKCFG_Pos         (2U)\r\n#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */\r\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\r\n#define SAI_xSR_FREQ_Pos           (3U)\r\n#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */\r\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\r\n#define SAI_xSR_CNRDY_Pos          (4U)\r\n#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */\r\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\r\n#define SAI_xSR_AFSDET_Pos         (5U)\r\n#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */\r\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\r\n#define SAI_xSR_LFSDET_Pos         (6U)\r\n#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */\r\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\r\n\r\n#define SAI_xSR_FLVL_Pos           (16U)\r\n#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */\r\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\r\n#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\r\n#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\r\n#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\r\n\r\n/******************  Bit definition for SAI_xCLRFR register  ******************/\r\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\r\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */\r\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\r\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\r\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */\r\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\r\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\r\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */\r\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\r\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\r\n#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */\r\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\r\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\r\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */\r\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\r\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\r\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */\r\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\r\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\r\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */\r\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\r\n\r\n/******************  Bit definition for SAI_xDR register  *********************/\r\n#define SAI_xDR_DATA_Pos           (0U)\r\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */\r\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\r\n\r\n/*******************  Bit definition for SAI_PDMCR register  ******************/\r\n#define SAI_PDMCR_PDMEN_Pos        (0U)\r\n#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */\r\n#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */\r\n\r\n#define SAI_PDMCR_MICNBR_Pos       (4U)\r\n#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */\r\n#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */\r\n#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */\r\n#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */\r\n\r\n#define SAI_PDMCR_CKEN1_Pos        (8U)\r\n#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */\r\n#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */\r\n#define SAI_PDMCR_CKEN2_Pos        (9U)\r\n#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */\r\n#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */\r\n#define SAI_PDMCR_CKEN3_Pos        (10U)\r\n#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */\r\n#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */\r\n#define SAI_PDMCR_CKEN4_Pos        (11U)\r\n#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */\r\n#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */\r\n\r\n/******************  Bit definition for SAI_PDMDLY register  ******************/\r\n#define SAI_PDMDLY_DLYM1L_Pos      (0U)\r\n#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */\r\n#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */\r\n#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */\r\n#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */\r\n#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */\r\n\r\n#define SAI_PDMDLY_DLYM1R_Pos      (4U)\r\n#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */\r\n#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */\r\n#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */\r\n#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */\r\n#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */\r\n\r\n#define SAI_PDMDLY_DLYM2L_Pos      (8U)\r\n#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */\r\n#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */\r\n#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */\r\n#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */\r\n#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */\r\n\r\n#define SAI_PDMDLY_DLYM2R_Pos      (12U)\r\n#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */\r\n#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/\r\n#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */\r\n#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */\r\n#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */\r\n\r\n#define SAI_PDMDLY_DLYM3L_Pos      (16U)\r\n#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */\r\n#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/\r\n#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */\r\n#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */\r\n#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */\r\n\r\n#define SAI_PDMDLY_DLYM3R_Pos      (20U)\r\n#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */\r\n#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/\r\n#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */\r\n#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */\r\n#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */\r\n\r\n#define SAI_PDMDLY_DLYM4L_Pos      (24U)\r\n#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */\r\n#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/\r\n#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */\r\n#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */\r\n#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */\r\n\r\n#define SAI_PDMDLY_DLYM4R_Pos      (28U)\r\n#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */\r\n#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/\r\n#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */\r\n#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */\r\n#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           SDMMC Interface                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for SDMMC_POWER register  ******************/\r\n#define SDMMC_POWER_PWRCTRL_Pos          (0U)\r\n#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */\r\n#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r\n#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */\r\n#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */\r\n#define SDMMC_POWER_VSWITCH_Pos          (2U)\r\n#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */\r\n#define SDMMC_POWER_VSWITCHEN_Pos        (3U)\r\n#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */\r\n#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */\r\n#define SDMMC_POWER_DIRPOL_Pos           (4U)\r\n#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */\r\n#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */\r\n\r\n/******************  Bit definition for SDMMC_CLKCR register  ******************/\r\n#define SDMMC_CLKCR_CLKDIV_Pos           (0U)\r\n#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */\r\n#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */\r\n#define SDMMC_CLKCR_PWRSAV_Pos           (12U)\r\n#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */\r\n#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */\r\n\r\n#define SDMMC_CLKCR_WIDBUS_Pos           (14U)\r\n#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */\r\n#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r\n#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */\r\n#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */\r\n\r\n#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)\r\n#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */\r\n#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */\r\n#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)\r\n#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */\r\n#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */\r\n#define SDMMC_CLKCR_DDR_Pos              (18U)\r\n#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */\r\n#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */\r\n#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)\r\n#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */\r\n#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */\r\n#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)\r\n#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */\r\n#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */\r\n#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */\r\n#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */\r\n\r\n/*******************  Bit definition for SDMMC_ARG register  *******************/\r\n#define SDMMC_ARG_CMDARG_Pos             (0U)\r\n#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */\r\n\r\n/*******************  Bit definition for SDMMC_CMD register  *******************/\r\n#define SDMMC_CMD_CMDINDEX_Pos           (0U)\r\n#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */\r\n#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */\r\n#define SDMMC_CMD_CMDTRANS_Pos           (6U)\r\n#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */\r\n#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */\r\n#define SDMMC_CMD_CMDSTOP_Pos            (7U)\r\n#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */\r\n#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */\r\n\r\n#define SDMMC_CMD_WAITRESP_Pos           (8U)\r\n#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */\r\n#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */\r\n#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */\r\n#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */\r\n\r\n#define SDMMC_CMD_WAITINT_Pos            (10U)\r\n#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */\r\n#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */\r\n#define SDMMC_CMD_WAITPEND_Pos           (11U)\r\n#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */\r\n#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r\n#define SDMMC_CMD_CPSMEN_Pos             (12U)\r\n#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */\r\n#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */\r\n#define SDMMC_CMD_DTHOLD_Pos             (13U)\r\n#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */\r\n#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */\r\n#define SDMMC_CMD_BOOTMODE_Pos           (14U)\r\n#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */\r\n#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */\r\n#define SDMMC_CMD_BOOTEN_Pos             (15U)\r\n#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */\r\n#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */\r\n#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)\r\n#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */\r\n#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */\r\n\r\n/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\r\n#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)\r\n#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\r\n#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */\r\n\r\n/******************  Bit definition for SDMMC_RESP0 register  ******************/\r\n#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)\r\n#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP1 register  ******************/\r\n#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)\r\n#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP2 register  ******************/\r\n#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)\r\n#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP3 register  ******************/\r\n#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)\r\n#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP4 register  ******************/\r\n#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)\r\n#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_DTIMER register  *****************/\r\n#define SDMMC_DTIMER_DATATIME_Pos        (0U)\r\n#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */\r\n\r\n/******************  Bit definition for SDMMC_DLEN register  *******************/\r\n#define SDMMC_DLEN_DATALENGTH_Pos        (0U)\r\n#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */\r\n\r\n/******************  Bit definition for SDMMC_DCTRL register  ******************/\r\n#define SDMMC_DCTRL_DTEN_Pos             (0U)\r\n#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */\r\n#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */\r\n#define SDMMC_DCTRL_DTDIR_Pos            (1U)\r\n#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */\r\n#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */\r\n#define SDMMC_DCTRL_DTMODE_Pos           (2U)\r\n#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */\r\n#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */\r\n#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */\r\n#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */\r\n\r\n#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)\r\n#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */\r\n\r\n#define SDMMC_DCTRL_RWSTART_Pos          (8U)\r\n#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */\r\n#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */\r\n#define SDMMC_DCTRL_RWSTOP_Pos           (9U)\r\n#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */\r\n#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */\r\n#define SDMMC_DCTRL_RWMOD_Pos            (10U)\r\n#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */\r\n#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */\r\n#define SDMMC_DCTRL_SDIOEN_Pos           (11U)\r\n#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */\r\n#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */\r\n#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)\r\n#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */\r\n#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */\r\n#define SDMMC_DCTRL_FIFORST_Pos          (13U)\r\n#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */\r\n#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */\r\n\r\n/******************  Bit definition for SDMMC_DCOUNT register  *****************/\r\n#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)\r\n#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */\r\n\r\n/******************  Bit definition for SDMMC_STA register  ********************/\r\n#define SDMMC_STA_CCRCFAIL_Pos           (0U)\r\n#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */\r\n#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */\r\n#define SDMMC_STA_DCRCFAIL_Pos           (1U)\r\n#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */\r\n#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */\r\n#define SDMMC_STA_CTIMEOUT_Pos           (2U)\r\n#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */\r\n#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */\r\n#define SDMMC_STA_DTIMEOUT_Pos           (3U)\r\n#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */\r\n#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */\r\n#define SDMMC_STA_TXUNDERR_Pos           (4U)\r\n#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */\r\n#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */\r\n#define SDMMC_STA_RXOVERR_Pos            (5U)\r\n#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */\r\n#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */\r\n#define SDMMC_STA_CMDREND_Pos            (6U)\r\n#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */\r\n#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */\r\n#define SDMMC_STA_CMDSENT_Pos            (7U)\r\n#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */\r\n#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */\r\n#define SDMMC_STA_DATAEND_Pos            (8U)\r\n#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */\r\n#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r\n#define SDMMC_STA_DHOLD_Pos              (9U)\r\n#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */\r\n#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */\r\n#define SDMMC_STA_DBCKEND_Pos            (10U)\r\n#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */\r\n#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */\r\n#define SDMMC_STA_DABORT_Pos             (11U)\r\n#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */\r\n#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */\r\n#define SDMMC_STA_DPSMACT_Pos            (12U)\r\n#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */\r\n#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */\r\n#define SDMMC_STA_CPSMACT_Pos            (13U)\r\n#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */\r\n#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */\r\n#define SDMMC_STA_TXFIFOHE_Pos           (14U)\r\n#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */\r\n#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r\n#define SDMMC_STA_RXFIFOHF_Pos           (15U)\r\n#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */\r\n#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r\n#define SDMMC_STA_TXFIFOF_Pos            (16U)\r\n#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */\r\n#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */\r\n#define SDMMC_STA_RXFIFOF_Pos            (17U)\r\n#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */\r\n#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */\r\n#define SDMMC_STA_TXFIFOE_Pos            (18U)\r\n#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */\r\n#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */\r\n#define SDMMC_STA_RXFIFOE_Pos            (19U)\r\n#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */\r\n#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */\r\n#define SDMMC_STA_BUSYD0_Pos             (20U)\r\n#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */\r\n#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */\r\n#define SDMMC_STA_BUSYD0END_Pos          (21U)\r\n#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */\r\n#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */\r\n#define SDMMC_STA_SDIOIT_Pos             (22U)\r\n#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */\r\n#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */\r\n#define SDMMC_STA_ACKFAIL_Pos            (23U)\r\n#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */\r\n#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */\r\n#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)\r\n#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */\r\n#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */\r\n#define SDMMC_STA_VSWEND_Pos             (25U)\r\n#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */\r\n#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */\r\n#define SDMMC_STA_CKSTOP_Pos             (26U)\r\n#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */\r\n#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */\r\n#define SDMMC_STA_IDMATE_Pos             (27U)\r\n#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */\r\n#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */\r\n#define SDMMC_STA_IDMABTC_Pos            (28U)\r\n#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */\r\n#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */\r\n\r\n/*******************  Bit definition for SDMMC_ICR register  *******************/\r\n#define SDMMC_ICR_CCRCFAILC_Pos          (0U)\r\n#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */\r\n#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */\r\n#define SDMMC_ICR_DCRCFAILC_Pos          (1U)\r\n#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */\r\n#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */\r\n#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)\r\n#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */\r\n#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)\r\n#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */\r\n#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */\r\n#define SDMMC_ICR_TXUNDERRC_Pos          (4U)\r\n#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */\r\n#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */\r\n#define SDMMC_ICR_RXOVERRC_Pos           (5U)\r\n#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */\r\n#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */\r\n#define SDMMC_ICR_CMDRENDC_Pos           (6U)\r\n#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */\r\n#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */\r\n#define SDMMC_ICR_CMDSENTC_Pos           (7U)\r\n#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */\r\n#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */\r\n#define SDMMC_ICR_DATAENDC_Pos           (8U)\r\n#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */\r\n#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */\r\n#define SDMMC_ICR_DHOLDC_Pos             (9U)\r\n#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */\r\n#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */\r\n#define SDMMC_ICR_DBCKENDC_Pos           (10U)\r\n#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */\r\n#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */\r\n#define SDMMC_ICR_DABORTC_Pos            (11U)\r\n#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */\r\n#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */\r\n#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)\r\n#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */\r\n#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */\r\n#define SDMMC_ICR_SDIOITC_Pos            (22U)\r\n#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */\r\n#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */\r\n#define SDMMC_ICR_ACKFAILC_Pos           (23U)\r\n#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */\r\n#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */\r\n#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)\r\n#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */\r\n#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */\r\n#define SDMMC_ICR_VSWENDC_Pos            (25U)\r\n#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */\r\n#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */\r\n#define SDMMC_ICR_CKSTOPC_Pos            (26U)\r\n#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */\r\n#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */\r\n#define SDMMC_ICR_IDMATEC_Pos            (27U)\r\n#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */\r\n#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */\r\n#define SDMMC_ICR_IDMABTCC_Pos           (28U)\r\n#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */\r\n#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */\r\n\r\n/******************  Bit definition for SDMMC_MASK register  *******************/\r\n#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)\r\n#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */\r\n#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */\r\n#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)\r\n#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */\r\n#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */\r\n#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)\r\n#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */\r\n#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */\r\n#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)\r\n#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */\r\n#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */\r\n#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)\r\n#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */\r\n#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r\n#define SDMMC_MASK_RXOVERRIE_Pos         (5U)\r\n#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */\r\n#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */\r\n#define SDMMC_MASK_CMDRENDIE_Pos         (6U)\r\n#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */\r\n#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */\r\n#define SDMMC_MASK_CMDSENTIE_Pos         (7U)\r\n#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */\r\n#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */\r\n#define SDMMC_MASK_DATAENDIE_Pos         (8U)\r\n#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */\r\n#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */\r\n#define SDMMC_MASK_DHOLDIE_Pos           (9U)\r\n#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */\r\n#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */\r\n#define SDMMC_MASK_DBCKENDIE_Pos         (10U)\r\n#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */\r\n#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */\r\n#define SDMMC_MASK_DABORTIE_Pos          (11U)\r\n#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */\r\n#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */\r\n\r\n#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)\r\n#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */\r\n#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */\r\n#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)\r\n#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */\r\n#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */\r\n\r\n#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)\r\n#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */\r\n#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */\r\n#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)\r\n#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */\r\n#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */\r\n\r\n#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)\r\n#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */\r\n#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */\r\n#define SDMMC_MASK_SDIOITIE_Pos           (22U)\r\n#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */\r\n#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */\r\n#define SDMMC_MASK_ACKFAILIE_Pos         (23U)\r\n#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */\r\n#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */\r\n#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)\r\n#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */\r\n#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */\r\n#define SDMMC_MASK_VSWENDIE_Pos          (25U)\r\n#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */\r\n#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */\r\n#define SDMMC_MASK_CKSTOPIE_Pos          (26U)\r\n#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */\r\n#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */\r\n#define SDMMC_MASK_IDMABTCIE_Pos         (28U)\r\n#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */\r\n#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */\r\n\r\n/*****************  Bit definition for SDMMC_ACKTIME register  *****************/\r\n#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)\r\n#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */\r\n\r\n/******************  Bit definition for SDMMC_FIFO register  *******************/\r\n#define SDMMC_FIFO_FIFODATA_Pos          (0U)\r\n#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */\r\n\r\n/******************  Bit definition for SDMMC_IDMACTRL register ****************/\r\n#define SDMMC_IDMA_IDMAEN_Pos            (0U)\r\n#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */\r\n#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */\r\n#define SDMMC_IDMA_IDMABMODE_Pos         (1U)\r\n#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */\r\n#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */\r\n#define SDMMC_IDMA_IDMABACT_Pos          (2U)\r\n#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */\r\n\r\n/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/\r\n#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)\r\n#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */\r\n#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */\r\n\r\n/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/\r\n#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */\r\n\r\n/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/\r\n#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Delay Block Interface (DLYB)                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for DLYB_CR register  ********************/\r\n#define DLYB_CR_DEN_Pos         (0U)\r\n#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */\r\n#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */\r\n#define DLYB_CR_SEN_Pos         (1U)\r\n#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */\r\n#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */\r\n\r\n\r\n/*******************  Bit definition for DLYB_CFGR register  ********************/\r\n#define DLYB_CFGR_SEL_Pos       (0U)\r\n#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */\r\n#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */\r\n#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */\r\n#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */\r\n#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */\r\n#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */\r\n\r\n#define DLYB_CFGR_UNIT_Pos      (8U)\r\n#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */\r\n#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */\r\n#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */\r\n#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */\r\n#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */\r\n#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */\r\n#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */\r\n#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */\r\n#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */\r\n\r\n#define DLYB_CFGR_LNG_Pos       (16U)\r\n#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */\r\n#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */\r\n#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */\r\n#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */\r\n#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */\r\n#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */\r\n#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */\r\n#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */\r\n#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */\r\n#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */\r\n#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */\r\n#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */\r\n#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */\r\n#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */\r\n\r\n#define DLYB_CFGR_LNGF_Pos      (31U)\r\n#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */\r\n#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                   Serial Peripheral Interface (SPI/I2S)                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for SPI_CR1 register  ********************/\r\n#define SPI_CR1_SPE_Pos             (0U)\r\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */\r\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */\r\n#define SPI_CR1_MASRX_Pos           (8U)\r\n#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */\r\n#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */\r\n#define SPI_CR1_CSTART_Pos          (9U)\r\n#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */\r\n#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */\r\n#define SPI_CR1_CSUSP_Pos           (10U)\r\n#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */\r\n#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */\r\n#define SPI_CR1_HDDIR_Pos           (11U)\r\n#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */\r\n#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */\r\n#define SPI_CR1_SSI_Pos             (12U)\r\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */\r\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */\r\n#define SPI_CR1_CRC33_17_Pos        (13U)\r\n#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */\r\n#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */\r\n#define SPI_CR1_RCRCINI_Pos         (14U)\r\n#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */\r\n#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */\r\n#define SPI_CR1_TCRCINI_Pos         (15U)\r\n#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */\r\n#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */\r\n#define SPI_CR1_IOLOCK_Pos          (16U)\r\n#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */\r\n#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */\r\n\r\n/*******************  Bit definition for SPI_CR2 register  ********************/\r\n#define SPI_CR2_TSER_Pos            (16U)\r\n#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */\r\n#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */\r\n#define SPI_CR2_TSIZE_Pos           (0U)\r\n#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */\r\n#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */\r\n\r\n/*******************  Bit definition for SPI_CFG1 register  ********************/\r\n#define SPI_CFG1_DSIZE_Pos          (0U)\r\n#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */\r\n#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */\r\n#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */\r\n#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */\r\n#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */\r\n#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */\r\n#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */\r\n\r\n#define SPI_CFG1_FTHLV_Pos          (5U)\r\n#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */\r\n#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/\r\n#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */\r\n#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */\r\n#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */\r\n#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */\r\n\r\n#define SPI_CFG1_UDRCFG_Pos         (9U)\r\n#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */\r\n#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */\r\n#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */\r\n#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */\r\n\r\n\r\n#define SPI_CFG1_UDRDET_Pos         (11U)\r\n#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */\r\n#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */\r\n#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */\r\n#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */\r\n\r\n#define SPI_CFG1_RXDMAEN_Pos        (14U)\r\n#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */\r\n#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */\r\n#define SPI_CFG1_TXDMAEN_Pos        (15U)\r\n#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */\r\n#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */\r\n\r\n#define SPI_CFG1_CRCSIZE_Pos        (16U)\r\n#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */\r\n#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/\r\n#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */\r\n#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */\r\n#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */\r\n#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */\r\n#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */\r\n\r\n#define SPI_CFG1_CRCEN_Pos          (22U)\r\n#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */\r\n#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */\r\n\r\n#define SPI_CFG1_MBR_Pos            (28U)\r\n#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */\r\n#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */\r\n#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */\r\n#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */\r\n#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */\r\n\r\n/*******************  Bit definition for SPI_CFG2 register  ********************/\r\n#define SPI_CFG2_MSSI_Pos           (0U)\r\n#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */\r\n#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */\r\n#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */\r\n#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */\r\n#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */\r\n#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */\r\n\r\n#define SPI_CFG2_MIDI_Pos           (4U)\r\n#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */\r\n#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */\r\n#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */\r\n#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */\r\n#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */\r\n#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */\r\n\r\n#define SPI_CFG2_IOSWP_Pos          (15U)\r\n#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */\r\n#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */\r\n\r\n#define SPI_CFG2_COMM_Pos           (17U)\r\n#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */\r\n#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/\r\n#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */\r\n#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */\r\n\r\n#define SPI_CFG2_SP_Pos             (19U)\r\n#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */\r\n#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */\r\n#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */\r\n#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */\r\n#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */\r\n\r\n#define SPI_CFG2_MASTER_Pos         (22U)\r\n#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */\r\n#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */\r\n#define SPI_CFG2_LSBFRST_Pos        (23U)\r\n#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */\r\n#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */\r\n#define SPI_CFG2_CPHA_Pos           (24U)\r\n#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */\r\n#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */\r\n#define SPI_CFG2_CPOL_Pos           (25U)\r\n#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */\r\n#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */\r\n#define SPI_CFG2_SSM_Pos            (26U)\r\n#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */\r\n#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */\r\n\r\n#define SPI_CFG2_SSIOP_Pos          (28U)\r\n#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */\r\n#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */\r\n#define SPI_CFG2_SSOE_Pos           (29U)\r\n#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */\r\n#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */\r\n#define SPI_CFG2_SSOM_Pos           (30U)\r\n#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */\r\n#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */\r\n\r\n#define SPI_CFG2_AFCNTR_Pos         (31U)\r\n#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */\r\n#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */\r\n\r\n/*******************  Bit definition for SPI_IER register  ********************/\r\n#define SPI_IER_RXPIE_Pos           (0U)\r\n#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */\r\n#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */\r\n#define SPI_IER_TXPIE_Pos           (1U)\r\n#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */\r\n#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */\r\n#define SPI_IER_DXPIE_Pos           (2U)\r\n#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */\r\n#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */\r\n#define SPI_IER_EOTIE_Pos           (3U)\r\n#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */\r\n#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */\r\n#define SPI_IER_TXTFIE_Pos          (4U)\r\n#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */\r\n#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */\r\n#define SPI_IER_UDRIE_Pos           (5U)\r\n#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */\r\n#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */\r\n#define SPI_IER_OVRIE_Pos           (6U)\r\n#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */\r\n#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */\r\n#define SPI_IER_CRCEIE_Pos          (7U)\r\n#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */\r\n#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */\r\n#define SPI_IER_TIFREIE_Pos         (8U)\r\n#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */\r\n#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */\r\n#define SPI_IER_MODFIE_Pos          (9U)\r\n#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */\r\n#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */\r\n#define SPI_IER_TSERFIE_Pos         (10U)\r\n#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */\r\n#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */\r\n\r\n/*******************  Bit definition for SPI_SR register  ********************/\r\n#define SPI_SR_RXP_Pos              (0U)\r\n#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */\r\n#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */\r\n#define SPI_SR_TXP_Pos              (1U)\r\n#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */\r\n#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */\r\n#define SPI_SR_DXP_Pos              (2U)\r\n#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */\r\n#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */\r\n#define SPI_SR_EOT_Pos              (3U)\r\n#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */\r\n#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */\r\n#define SPI_SR_TXTF_Pos             (4U)\r\n#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */\r\n#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */\r\n#define SPI_SR_UDR_Pos              (5U)\r\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */\r\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */\r\n#define SPI_SR_OVR_Pos              (6U)\r\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */\r\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */\r\n#define SPI_SR_CRCE_Pos             (7U)\r\n#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */\r\n#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */\r\n#define SPI_SR_TIFRE_Pos            (8U)\r\n#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */\r\n#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */\r\n#define SPI_SR_MODF_Pos             (9U)\r\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */\r\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */\r\n#define SPI_SR_TSERF_Pos            (10U)\r\n#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */\r\n#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */\r\n#define SPI_SR_SUSP_Pos             (11U)\r\n#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */\r\n#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */\r\n#define SPI_SR_TXC_Pos              (12U)\r\n#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */\r\n#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */\r\n#define SPI_SR_RXPLVL_Pos           (13U)\r\n#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */\r\n#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */\r\n#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */\r\n#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */\r\n#define SPI_SR_RXWNE_Pos            (15U)\r\n#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */\r\n#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */\r\n#define SPI_SR_CTSIZE_Pos           (16U)\r\n#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */\r\n#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */\r\n\r\n/*******************  Bit definition for SPI_IFCR register  ********************/\r\n#define SPI_IFCR_EOTC_Pos           (3U)\r\n#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */\r\n#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */\r\n#define SPI_IFCR_TXTFC_Pos          (4U)\r\n#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */\r\n#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */\r\n#define SPI_IFCR_UDRC_Pos           (5U)\r\n#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */\r\n#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */\r\n#define SPI_IFCR_OVRC_Pos           (6U)\r\n#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */\r\n#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */\r\n#define SPI_IFCR_CRCEC_Pos          (7U)\r\n#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */\r\n#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */\r\n#define SPI_IFCR_TIFREC_Pos         (8U)\r\n#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */\r\n#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */\r\n#define SPI_IFCR_MODFC_Pos          (9U)\r\n#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */\r\n#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */\r\n#define SPI_IFCR_TSERFC_Pos         (10U)\r\n#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */\r\n#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */\r\n#define SPI_IFCR_SUSPC_Pos          (11U)\r\n#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */\r\n#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */\r\n\r\n/*******************  Bit definition for SPI_TXDR register  ********************/\r\n#define SPI_TXDR_TXDR_Pos           (0U)\r\n#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */\r\n#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */\r\n\r\n/*******************  Bit definition for SPI_RXDR register  ********************/\r\n#define SPI_RXDR_RXDR_Pos           (0U)\r\n#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */\r\n#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */\r\n\r\n/*******************  Bit definition for SPI_CRCPOLY register  ********************/\r\n#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)\r\n#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */\r\n#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */\r\n\r\n/*******************  Bit definition for SPI_TXCRC register  ********************/\r\n#define SPI_TXCRC_TXCRC_Pos         (0U)\r\n#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */\r\n#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */\r\n\r\n/*******************  Bit definition for SPI_RXCRC register  ********************/\r\n#define SPI_RXCRC_RXCRC_Pos         (0U)\r\n#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */\r\n#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */\r\n\r\n/*******************  Bit definition for SPI_UDRDR register  ********************/\r\n#define SPI_UDRDR_UDRDR_Pos         (0U)\r\n#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */\r\n#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */\r\n\r\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\r\n#define SPI_I2SCFGR_I2SMOD_Pos      (0U)\r\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */\r\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\r\n#define SPI_I2SCFGR_I2SCFG_Pos      (1U)\r\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */\r\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */\r\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */\r\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */\r\n#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */\r\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\r\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */\r\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */\r\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\r\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\r\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\r\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */\r\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */\r\n#define SPI_I2SCFGR_DATLEN_Pos      (8U)\r\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */\r\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */\r\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */\r\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */\r\n#define SPI_I2SCFGR_CHLEN_Pos       (10U)\r\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */\r\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\r\n#define SPI_I2SCFGR_CKPOL_Pos       (11U)\r\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */\r\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */\r\n#define SPI_I2SCFGR_FIXCH_Pos       (12U)\r\n#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */\r\n#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */\r\n#define SPI_I2SCFGR_WSINV_Pos       (13U)\r\n#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */\r\n#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */\r\n#define SPI_I2SCFGR_DATFMT_Pos      (14U)\r\n#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */\r\n#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */\r\n#define SPI_I2SCFGR_I2SDIV_Pos      (16U)\r\n#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */\r\n#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */\r\n#define SPI_I2SCFGR_ODD_Pos         (24U)\r\n#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */\r\n#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */\r\n#define SPI_I2SCFGR_MCKOE_Pos       (25U)\r\n#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */\r\n#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */\r\n\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 SYSCFG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/******************  Bit definition for SYSCFG_PMCR register  ******************/\r\n#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)\r\n#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */\r\n#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)\r\n#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */\r\n#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)\r\n#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */\r\n#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)\r\n#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */\r\n#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)\r\n#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */\r\n#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)\r\n#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */\r\n#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)\r\n#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */\r\n#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)\r\n#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */\r\n#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */\r\n#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)\r\n#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */\r\n#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */\r\n\r\n#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)\r\n#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */\r\n#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */\r\n\r\n#define SYSCFG_PMCR_I2C5_FMP_Pos        (10U)\r\n#define SYSCFG_PMCR_I2C5_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C5_FMP_Pos)    /*!< 0x00000400 */\r\n#define SYSCFG_PMCR_I2C5_FMP            SYSCFG_PMCR_I2C5_FMP_Msk               /*!< I2C5 Fast mode plus */\r\n\r\n#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)\r\n#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */\r\n#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */\r\n#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */\r\n#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */\r\n#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */\r\n#define SYSCFG_PMCR_PA0SO_Pos           (24U)\r\n#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */\r\n#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */\r\n#define SYSCFG_PMCR_PA1SO_Pos           (25U)\r\n#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */\r\n#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */\r\n#define SYSCFG_PMCR_PC2SO_Pos           (26U)\r\n#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */\r\n#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */\r\n#define SYSCFG_PMCR_PC3SO_Pos           (27U)\r\n#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */\r\n#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r\n#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)\r\n#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\r\n#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)\r\n#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\r\n#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)\r\n#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\r\n#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)\r\n#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\r\n/**\r\n  * @brief   EXTI0 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */\r\n\r\n/**\r\n  * @brief   EXTI1 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */\r\n/**\r\n  * @brief   EXTI2 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */\r\n\r\n/**\r\n  * @brief   EXTI3 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r\n#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)\r\n#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\r\n#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)\r\n#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\r\n#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)\r\n#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\r\n#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)\r\n#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\r\n/**\r\n  * @brief   EXTI4 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */\r\n/**\r\n  * @brief   EXTI5 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */\r\n/**\r\n  * @brief   EXTI6 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */\r\n\r\n/**\r\n  * @brief   EXTI7 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r\n#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)\r\n#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\r\n#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)\r\n#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\r\n#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)\r\n#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\r\n#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)\r\n#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\r\n\r\n/**\r\n  * @brief   EXTI8 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */\r\n\r\n/**\r\n  * @brief   EXTI9 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */\r\n\r\n/**\r\n  * @brief   EXTI10 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */\r\n\r\n/**\r\n  * @brief   EXTI11 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r\n#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)\r\n#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\r\n#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)\r\n#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\r\n#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)\r\n#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\r\n#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)\r\n#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\r\n/**\r\n  * @brief   EXTI12 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */\r\n/**\r\n  * @brief   EXTI13 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */\r\n/**\r\n  * @brief   EXTI14 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */\r\n/**\r\n  * @brief   EXTI15 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */\r\n\r\n/******************  Bit definition for SYSCFG_CFGR register  ******************/\r\n#define SYSCFG_CFGR_PVDL_Pos            (2U)\r\n#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */\r\n#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */\r\n#define SYSCFG_CFGR_FLASHL_Pos          (3U)\r\n#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */\r\n#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */\r\n#define SYSCFG_CFGR_CM7L_Pos            (6U)\r\n#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */\r\n#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */\r\n#define SYSCFG_CFGR_BKRAML_Pos          (7U)\r\n#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */\r\n#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */\r\n#define SYSCFG_CFGR_SRAM4L_Pos          (9U)\r\n#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */\r\n#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */\r\n#define SYSCFG_CFGR_SRAM2L_Pos          (11U)\r\n#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */\r\n#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */\r\n#define SYSCFG_CFGR_SRAM1L_Pos          (12U)\r\n#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */\r\n#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */\r\n#define SYSCFG_CFGR_DTCML_Pos           (13U)\r\n#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */\r\n#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */\r\n#define SYSCFG_CFGR_ITCML_Pos           (14U)\r\n#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */\r\n#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */\r\n#define SYSCFG_CFGR_AXISRAML_Pos        (15U)\r\n#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */\r\n#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */\r\n\r\n/******************  Bit definition for SYSCFG_CCCSR register  ******************/\r\n#define SYSCFG_CCCSR_EN_Pos             (0U)\r\n#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */\r\n#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */\r\n#define SYSCFG_CCCSR_CS_Pos             (1U)\r\n#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */\r\n#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */\r\n#define SYSCFG_CCCSR_READY_Pos          (8U)\r\n#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */\r\n#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */\r\n#define SYSCFG_CCCSR_HSLV_Pos           (16U)\r\n#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */\r\n#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */\r\n\r\n/******************  Bit definition for SYSCFG_CCVR register  *******************/\r\n#define SYSCFG_CCVR_NCV_Pos             (0U)\r\n#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */\r\n#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */\r\n#define SYSCFG_CCVR_PCV_Pos             (4U)\r\n#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */\r\n#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */\r\n\r\n/******************  Bit definition for SYSCFG_CCCR register  *******************/\r\n#define SYSCFG_CCCR_NCC_Pos             (0U)\r\n#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */\r\n#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */\r\n#define SYSCFG_CCCR_PCC_Pos             (4U)\r\n#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */\r\n#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */\r\n/******************  Bit definition for SYSCFG_ADC2ALT register  *******************/\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT0_Pos   (0U)\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT0_Msk   (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT0_Pos) /*!< 0x00000001 */\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT0       SYSCFG_ADC2ALT_ADC2_ROUT0_Msk            /*!< VBAT/4 connected to ADC2 V_INP[16] */\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT1_Pos   (1U)\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT1_Msk   (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT1_Pos) /*!< 0x00000002 */\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT1       SYSCFG_ADC2ALT_ADC2_ROUT1_Msk            /*!< Internal reference voltage (V_REFINT) connected to ADC2 V_INP[17] */\r\n\r\n/******************  Bit definition for SYSCFG_PKGR register  *******************/\r\n#define SYSCFG_PKGR_PKG_Pos             (0U)\r\n#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */\r\n#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */\r\n\r\n/******************  Bit definition for SYSCFG_UR0 register  *******************/\r\n#define SYSCFG_UR0_RDP_Pos              (16U)\r\n#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */\r\n#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */\r\n\r\n/******************  Bit definition for SYSCFG_UR2 register  *******************/\r\n#define SYSCFG_UR2_BORH_Pos             (0U)\r\n#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */\r\n#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */\r\n#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */\r\n#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */\r\n#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)\r\n#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */\r\n#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */\r\n/******************  Bit definition for SYSCFG_UR3 register  *******************/\r\n#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)\r\n#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */\r\n#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */\r\n\r\n  /******************  Bit definition for SYSCFG_UR4 register  *******************/\r\n\r\n#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)\r\n#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */\r\n#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */\r\n\r\n/******************  Bit definition for SYSCFG_UR5 register  *******************/\r\n#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)\r\n#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */\r\n#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */\r\n#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)\r\n#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */\r\n#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */\r\n\r\n/******************  Bit definition for SYSCFG_UR6 register  *******************/\r\n#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)\r\n#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */\r\n#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */\r\n#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)\r\n#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */\r\n#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */\r\n\r\n/******************  Bit definition for SYSCFG_UR7 register  *******************/\r\n#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)\r\n#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */\r\n#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */\r\n#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)\r\n#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */\r\n#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */\r\n\r\n\r\n/******************  Bit definition for SYSCFG_UR11 register  *******************/\r\n#define SYSCFG_UR11_IWDG1M_Pos          (16U)\r\n#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */\r\n#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */\r\n\r\n/******************  Bit definition for SYSCFG_UR12 register  *******************/\r\n\r\n#define SYSCFG_UR12_SECURE_Pos          (16U)\r\n#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */\r\n#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */\r\n\r\n/******************  Bit definition for SYSCFG_UR13 register  *******************/\r\n#define SYSCFG_UR13_SDRS_Pos            (0U)\r\n#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */\r\n#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */\r\n#define SYSCFG_UR13_D1SBRST_Pos         (16U)\r\n#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */\r\n#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */\r\n\r\n/******************  Bit definition for SYSCFG_UR14 register  *******************/\r\n#define SYSCFG_UR14_D1STPRST_Pos        (0U)\r\n#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */\r\n#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */\r\n\r\n/******************  Bit definition for SYSCFG_UR15 register  *******************/\r\n#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)\r\n#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */\r\n#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */\r\n\r\n/******************  Bit definition for SYSCFG_UR16 register  *******************/\r\n#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)\r\n#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */\r\n#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */\r\n#define SYSCFG_UR16_PKP_Pos             (16U)\r\n#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */\r\n#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */\r\n\r\n/******************  Bit definition for SYSCFG_UR17 register  *******************/\r\n#define SYSCFG_UR17_IOHSLV_Pos          (0U)\r\n#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */\r\n#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */\r\n#define SYSCFG_UR17_TCM_AXI_CFG_Pos     (16U)\r\n#define SYSCFG_UR17_TCM_AXI_CFG_Msk     (0x3UL << SYSCFG_UR17_TCM_AXI_CFG_Pos) /*!< 0x00030000 */\r\n#define SYSCFG_UR17_TCM_AXI_CFG         SYSCFG_UR17_TCM_AXI_CFG_Msk            /*!< ITCM-RAM / AXI-SRAM size */\r\n\r\n/******************  Bit definition for SYSCFG_UR18 register  *******************/\r\n#define SYSCFG_UR18_CPU_FREQ_BOOST_Pos  (0U)\r\n#define SYSCFG_UR18_CPU_FREQ_BOOST_Msk  (0x1UL << SYSCFG_UR18_CPU_FREQ_BOOST_Pos)  /*!< 0x00000001 */\r\n#define SYSCFG_UR18_CPU_FREQ_BOOST       SYSCFG_UR18_CPU_FREQ_BOOST_Msk            /*!< CPU maximum frequency boost enable */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                    Digital Temperature Sensor (DTS)                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/******************  Bit definition for DTS_CFGR1 register  ******************/\r\n#define DTS_CFGR1_TS1_EN_Pos               (0U)\r\n#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */\r\n#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */\r\n#define DTS_CFGR1_TS1_START_Pos            (4U)\r\n#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */\r\n#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)\r\n#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */\r\n#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */\r\n#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)\r\n#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */\r\n#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */\r\n#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)\r\n#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */\r\n#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */\r\n#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)\r\n#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */\r\n#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/\r\n\r\n/******************  Bit definition for DTS_T0VALR1 register  ******************/\r\n#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)\r\n#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */\r\n#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */\r\n#define DTS_T0VALR1_TS1_T0_Pos             (16U)\r\n#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */\r\n#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */\r\n\r\n/******************  Bit definition for DTS_RAMPVALR register  ******************/\r\n#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)\r\n#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */\r\n#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */\r\n\r\n/******************  Bit definition for DTS_ITR1 register      ******************/\r\n#define DTS_ITR1_TS1_LITTHD_Pos            (0U)\r\n#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */\r\n#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */\r\n#define DTS_ITR1_TS1_HITTHD_Pos            (16U)\r\n#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */\r\n#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */\r\n\r\n/******************  Bit definition for DTS_DR register        ******************/\r\n#define DTS_DR_TS1_MFREQ_Pos               (0U)\r\n#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */\r\n#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */\r\n\r\n/******************  Bit definition for DTS_SR register        ******************/\r\n#define DTS_SR_TS1_ITEF_Pos                (0U)\r\n#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */\r\n#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */\r\n#define DTS_SR_TS1_ITLF_Pos                (1U)\r\n#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */\r\n#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */\r\n#define DTS_SR_TS1_ITHF_Pos                (2U)\r\n#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */\r\n#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */\r\n#define DTS_SR_TS1_AITEF_Pos               (4U)\r\n#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */\r\n#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */\r\n#define DTS_SR_TS1_AITLF_Pos               (5U)\r\n#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */\r\n#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */\r\n#define DTS_SR_TS1_AITHF_Pos               (6U)\r\n#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */\r\n#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */\r\n#define DTS_SR_TS1_RDY_Pos                 (15U)\r\n#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */\r\n#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */\r\n\r\n/******************  Bit definition for DTS_ITENR register      ******************/\r\n#define DTS_ITENR_TS1_ITEEN_Pos            (0U)\r\n#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */\r\n#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */\r\n#define DTS_ITENR_TS1_ITLEN_Pos            (1U)\r\n#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */\r\n#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */\r\n#define DTS_ITENR_TS1_ITHEN_Pos            (2U)\r\n#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */\r\n#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */\r\n#define DTS_ITENR_TS1_AITEEN_Pos           (4U)\r\n#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */\r\n#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */\r\n#define DTS_ITENR_TS1_AITLEN_Pos           (5U)\r\n#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */\r\n#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */\r\n#define DTS_ITENR_TS1_AITHEN_Pos           (6U)\r\n#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */\r\n#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */\r\n\r\n/******************  Bit definition for DTS_ICIFR register      ******************/\r\n#define DTS_ICIFR_TS1_CITEF_Pos            (0U)\r\n#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */\r\n#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */\r\n#define DTS_ICIFR_TS1_CITLF_Pos            (1U)\r\n#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */\r\n#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */\r\n#define DTS_ICIFR_TS1_CITHF_Pos            (2U)\r\n#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */\r\n#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */\r\n#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)\r\n#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */\r\n#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */\r\n#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)\r\n#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */\r\n#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */\r\n#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)\r\n#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */\r\n#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    TIM                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */\r\n\r\n/*******************  Bit definition for TIM_CR1 register  ********************/\r\n#define TIM_CR1_CEN_Pos           (0U)\r\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */\r\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\r\n#define TIM_CR1_UDIS_Pos          (1U)\r\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */\r\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\r\n#define TIM_CR1_URS_Pos           (2U)\r\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */\r\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\r\n#define TIM_CR1_OPM_Pos           (3U)\r\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */\r\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\r\n#define TIM_CR1_DIR_Pos           (4U)\r\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */\r\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\r\n\r\n#define TIM_CR1_CMS_Pos           (5U)\r\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */\r\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\r\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */\r\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */\r\n\r\n#define TIM_CR1_ARPE_Pos          (7U)\r\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */\r\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\r\n\r\n#define TIM_CR1_CKD_Pos           (8U)\r\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */\r\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\r\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */\r\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */\r\n\r\n#define TIM_CR1_UIFREMAP_Pos      (11U)\r\n#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */\r\n#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\r\n\r\n/*******************  Bit definition for TIM_CR2 register  ********************/\r\n#define TIM_CR2_CCPC_Pos          (0U)\r\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */\r\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\r\n#define TIM_CR2_CCUS_Pos          (2U)\r\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */\r\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\r\n#define TIM_CR2_CCDS_Pos          (3U)\r\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */\r\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\r\n\r\n#define TIM_CR2_MMS_Pos           (4U)\r\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */\r\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */\r\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */\r\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */\r\n\r\n#define TIM_CR2_TI1S_Pos          (7U)\r\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */\r\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\r\n#define TIM_CR2_OIS1_Pos          (8U)\r\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */\r\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\r\n#define TIM_CR2_OIS1N_Pos         (9U)\r\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */\r\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\r\n#define TIM_CR2_OIS2_Pos          (10U)\r\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */\r\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\r\n#define TIM_CR2_OIS2N_Pos         (11U)\r\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */\r\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\r\n#define TIM_CR2_OIS3_Pos          (12U)\r\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */\r\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\r\n#define TIM_CR2_OIS3N_Pos         (13U)\r\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\r\n#define TIM_CR2_OIS4_Pos          (14U)\r\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */\r\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n#define TIM_CR2_OIS5_Pos          (16U)\r\n#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */\r\n#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n#define TIM_CR2_OIS6_Pos          (17U)\r\n#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */\r\n#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n\r\n#define TIM_CR2_MMS2_Pos          (20U)\r\n#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */\r\n#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */\r\n#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */\r\n#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */\r\n#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */\r\n\r\n/*******************  Bit definition for TIM_SMCR register  *******************/\r\n#define TIM_SMCR_SMS_Pos          (0U)\r\n#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */\r\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\r\n#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */\r\n#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */\r\n#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */\r\n#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */\r\n\r\n#define TIM_SMCR_TS_Pos           (4U)\r\n#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */\r\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */\r\n#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */\r\n#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */\r\n#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */\r\n#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */\r\n#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */\r\n\r\n#define TIM_SMCR_MSM_Pos          (7U)\r\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */\r\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\r\n\r\n#define TIM_SMCR_ETF_Pos          (8U)\r\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */\r\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\r\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */\r\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */\r\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */\r\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */\r\n\r\n#define TIM_SMCR_ETPS_Pos         (12U)\r\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */\r\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\r\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */\r\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */\r\n\r\n#define TIM_SMCR_ECE_Pos          (14U)\r\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */\r\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\r\n#define TIM_SMCR_ETP_Pos          (15U)\r\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */\r\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\r\n\r\n/*******************  Bit definition for TIM_DIER register  *******************/\r\n#define TIM_DIER_UIE_Pos          (0U)\r\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */\r\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\r\n#define TIM_DIER_CC1IE_Pos        (1U)\r\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */\r\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\r\n#define TIM_DIER_CC2IE_Pos        (2U)\r\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */\r\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\r\n#define TIM_DIER_CC3IE_Pos        (3U)\r\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */\r\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\r\n#define TIM_DIER_CC4IE_Pos        (4U)\r\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */\r\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\r\n#define TIM_DIER_COMIE_Pos        (5U)\r\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */\r\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\r\n#define TIM_DIER_TIE_Pos          (6U)\r\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */\r\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\r\n#define TIM_DIER_BIE_Pos          (7U)\r\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */\r\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\r\n#define TIM_DIER_UDE_Pos          (8U)\r\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */\r\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\r\n#define TIM_DIER_CC1DE_Pos        (9U)\r\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */\r\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\r\n#define TIM_DIER_CC2DE_Pos        (10U)\r\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */\r\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\r\n#define TIM_DIER_CC3DE_Pos        (11U)\r\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */\r\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\r\n#define TIM_DIER_CC4DE_Pos        (12U)\r\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */\r\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\r\n#define TIM_DIER_COMDE_Pos        (13U)\r\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */\r\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\r\n#define TIM_DIER_TDE_Pos          (14U)\r\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */\r\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\r\n\r\n/********************  Bit definition for TIM_SR register  ********************/\r\n#define TIM_SR_UIF_Pos            (0U)\r\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */\r\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\r\n#define TIM_SR_CC1IF_Pos          (1U)\r\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */\r\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\r\n#define TIM_SR_CC2IF_Pos          (2U)\r\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */\r\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\r\n#define TIM_SR_CC3IF_Pos          (3U)\r\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */\r\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\r\n#define TIM_SR_CC4IF_Pos          (4U)\r\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */\r\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\r\n#define TIM_SR_COMIF_Pos          (5U)\r\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */\r\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\r\n#define TIM_SR_TIF_Pos            (6U)\r\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */\r\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\r\n#define TIM_SR_BIF_Pos            (7U)\r\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */\r\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\r\n#define TIM_SR_B2IF_Pos           (8U)\r\n#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */\r\n#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */\r\n#define TIM_SR_CC1OF_Pos          (9U)\r\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */\r\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\r\n#define TIM_SR_CC2OF_Pos          (10U)\r\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */\r\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\r\n#define TIM_SR_CC3OF_Pos          (11U)\r\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */\r\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\r\n#define TIM_SR_CC4OF_Pos          (12U)\r\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */\r\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\r\n#define TIM_SR_CC5IF_Pos          (16U)\r\n#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */\r\n#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\r\n#define TIM_SR_CC6IF_Pos          (17U)\r\n#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */\r\n#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\r\n#define TIM_SR_SBIF_Pos           (13U)\r\n#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */\r\n#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */\r\n\r\n/*******************  Bit definition for TIM_EGR register  ********************/\r\n#define TIM_EGR_UG_Pos            (0U)\r\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */\r\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\r\n#define TIM_EGR_CC1G_Pos          (1U)\r\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */\r\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\r\n#define TIM_EGR_CC2G_Pos          (2U)\r\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */\r\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\r\n#define TIM_EGR_CC3G_Pos          (3U)\r\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */\r\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\r\n#define TIM_EGR_CC4G_Pos          (4U)\r\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */\r\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\r\n#define TIM_EGR_COMG_Pos          (5U)\r\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */\r\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\r\n#define TIM_EGR_TG_Pos            (6U)\r\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */\r\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\r\n#define TIM_EGR_BG_Pos            (7U)\r\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */\r\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\r\n#define TIM_EGR_B2G_Pos           (8U)\r\n#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */\r\n#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */\r\n\r\n\r\n/******************  Bit definition for TIM_CCMR1 register  *******************/\r\n#define TIM_CCMR1_CC1S_Pos        (0U)\r\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */\r\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */\r\n\r\n#define TIM_CCMR1_OC1FE_Pos       (2U)\r\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\r\n#define TIM_CCMR1_OC1PE_Pos       (3U)\r\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */\r\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\r\n\r\n#define TIM_CCMR1_OC1M_Pos        (4U)\r\n#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */\r\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r\n#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */\r\n#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */\r\n#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */\r\n#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR1_OC1CE_Pos       (7U)\r\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */\r\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */\r\n\r\n#define TIM_CCMR1_CC2S_Pos        (8U)\r\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */\r\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */\r\n\r\n#define TIM_CCMR1_OC2FE_Pos       (10U)\r\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\r\n#define TIM_CCMR1_OC2PE_Pos       (11U)\r\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */\r\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\r\n\r\n#define TIM_CCMR1_OC2M_Pos        (12U)\r\n#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */\r\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r\n#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */\r\n#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */\r\n#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */\r\n#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */\r\n\r\n#define TIM_CCMR1_OC2CE_Pos       (15U)\r\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */\r\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\r\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */\r\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */\r\n\r\n#define TIM_CCMR1_IC1F_Pos        (4U)\r\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */\r\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */\r\n\r\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\r\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */\r\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */\r\n\r\n#define TIM_CCMR1_IC2F_Pos        (12U)\r\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */\r\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */\r\n\r\n/******************  Bit definition for TIM_CCMR2 register  *******************/\r\n#define TIM_CCMR2_CC3S_Pos        (0U)\r\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */\r\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */\r\n\r\n#define TIM_CCMR2_OC3FE_Pos       (2U)\r\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\r\n#define TIM_CCMR2_OC3PE_Pos       (3U)\r\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */\r\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\r\n\r\n#define TIM_CCMR2_OC3M_Pos        (4U)\r\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */\r\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR2_OC3CE_Pos       (7U)\r\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */\r\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\r\n\r\n#define TIM_CCMR2_CC4S_Pos        (8U)\r\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */\r\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */\r\n\r\n#define TIM_CCMR2_OC4FE_Pos       (10U)\r\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\r\n#define TIM_CCMR2_OC4PE_Pos       (11U)\r\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */\r\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\r\n\r\n#define TIM_CCMR2_OC4M_Pos        (12U)\r\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */\r\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */\r\n\r\n#define TIM_CCMR2_OC4CE_Pos       (15U)\r\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */\r\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\r\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */\r\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */\r\n\r\n#define TIM_CCMR2_IC3F_Pos        (4U)\r\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */\r\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */\r\n\r\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\r\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */\r\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */\r\n\r\n#define TIM_CCMR2_IC4F_Pos        (12U)\r\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */\r\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */\r\n\r\n/*******************  Bit definition for TIM_CCER register  *******************/\r\n#define TIM_CCER_CC1E_Pos         (0U)\r\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\r\n#define TIM_CCER_CC1P_Pos         (1U)\r\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */\r\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\r\n#define TIM_CCER_CC1NE_Pos        (2U)\r\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */\r\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\r\n#define TIM_CCER_CC1NP_Pos        (3U)\r\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */\r\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\r\n#define TIM_CCER_CC2E_Pos         (4U)\r\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\r\n#define TIM_CCER_CC2P_Pos         (5U)\r\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\r\n#define TIM_CCER_CC2NE_Pos        (6U)\r\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */\r\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\r\n#define TIM_CCER_CC2NP_Pos        (7U)\r\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */\r\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\r\n#define TIM_CCER_CC3E_Pos         (8U)\r\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\r\n#define TIM_CCER_CC3P_Pos         (9U)\r\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */\r\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\r\n#define TIM_CCER_CC3NE_Pos        (10U)\r\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */\r\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\r\n#define TIM_CCER_CC3NP_Pos        (11U)\r\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */\r\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\r\n#define TIM_CCER_CC4E_Pos         (12U)\r\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\r\n#define TIM_CCER_CC4P_Pos         (13U)\r\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\r\n#define TIM_CCER_CC4NP_Pos        (15U)\r\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */\r\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\r\n#define TIM_CCER_CC5E_Pos         (16U)\r\n#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */\r\n#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\r\n#define TIM_CCER_CC5P_Pos         (17U)\r\n#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */\r\n#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\r\n#define TIM_CCER_CC6E_Pos         (20U)\r\n#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */\r\n#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\r\n#define TIM_CCER_CC6P_Pos         (21U)\r\n#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */\r\n#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\r\n/*******************  Bit definition for TIM_CNT register  ********************/\r\n#define TIM_CNT_CNT_Pos           (0U)\r\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */\r\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\r\n#define TIM_CNT_UIFCPY_Pos        (31U)\r\n#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */\r\n#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */\r\n/*******************  Bit definition for TIM_PSC register  ********************/\r\n#define TIM_PSC_PSC_Pos           (0U)\r\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */\r\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\r\n\r\n/*******************  Bit definition for TIM_ARR register  ********************/\r\n#define TIM_ARR_ARR_Pos           (0U)\r\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */\r\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\r\n\r\n/*******************  Bit definition for TIM_RCR register  ********************/\r\n#define TIM_RCR_REP_Pos           (0U)\r\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */\r\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\r\n\r\n/*******************  Bit definition for TIM_CCR1 register  *******************/\r\n#define TIM_CCR1_CCR1_Pos         (0U)\r\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR2 register  *******************/\r\n#define TIM_CCR2_CCR2_Pos         (0U)\r\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR3 register  *******************/\r\n#define TIM_CCR3_CCR3_Pos         (0U)\r\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR4 register  *******************/\r\n#define TIM_CCR4_CCR4_Pos         (0U)\r\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR5 register  *******************/\r\n#define TIM_CCR5_CCR5_Pos         (0U)\r\n#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */\r\n#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\r\n#define TIM_CCR5_GC5C1_Pos        (29U)\r\n#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */\r\n#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\r\n#define TIM_CCR5_GC5C2_Pos        (30U)\r\n#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */\r\n#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\r\n#define TIM_CCR5_GC5C3_Pos        (31U)\r\n#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */\r\n#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\r\n\r\n/*******************  Bit definition for TIM_CCR6 register  *******************/\r\n#define TIM_CCR6_CCR6_Pos         (0U)\r\n#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\r\n\r\n/*******************  Bit definition for TIM_BDTR register  *******************/\r\n#define TIM_BDTR_DTG_Pos          (0U)\r\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */\r\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */\r\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */\r\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */\r\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */\r\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */\r\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */\r\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */\r\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */\r\n\r\n#define TIM_BDTR_LOCK_Pos         (8U)\r\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */\r\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\r\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */\r\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */\r\n\r\n#define TIM_BDTR_OSSI_Pos         (10U)\r\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */\r\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\r\n#define TIM_BDTR_OSSR_Pos         (11U)\r\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */\r\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\r\n#define TIM_BDTR_BKE_Pos          (12U)\r\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */\r\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */\r\n#define TIM_BDTR_BKP_Pos          (13U)\r\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */\r\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */\r\n#define TIM_BDTR_AOE_Pos          (14U)\r\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */\r\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\r\n#define TIM_BDTR_MOE_Pos          (15U)\r\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */\r\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\r\n\r\n#define TIM_BDTR_BKF_Pos          (16U)\r\n#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */\r\n#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */\r\n#define TIM_BDTR_BK2F_Pos         (20U)\r\n#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */\r\n#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */\r\n\r\n#define TIM_BDTR_BK2E_Pos         (24U)\r\n#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */\r\n#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */\r\n#define TIM_BDTR_BK2P_Pos         (25U)\r\n#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */\r\n#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */\r\n\r\n/*******************  Bit definition for TIM_DCR register  ********************/\r\n#define TIM_DCR_DBA_Pos           (0U)\r\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */\r\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\r\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */\r\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */\r\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */\r\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */\r\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */\r\n\r\n#define TIM_DCR_DBL_Pos           (8U)\r\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */\r\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\r\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */\r\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */\r\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */\r\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */\r\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */\r\n\r\n/*******************  Bit definition for TIM_DMAR register  *******************/\r\n#define TIM_DMAR_DMAB_Pos         (0U)\r\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\r\n\r\n/******************  Bit definition for TIM_CCMR3 register  *******************/\r\n#define TIM_CCMR3_OC5FE_Pos       (2U)\r\n#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\r\n#define TIM_CCMR3_OC5PE_Pos       (3U)\r\n#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */\r\n#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\r\n\r\n#define TIM_CCMR3_OC5M_Pos        (4U)\r\n#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */\r\n#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r\n#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR3_OC5CE_Pos       (7U)\r\n#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */\r\n#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\r\n\r\n#define TIM_CCMR3_OC6FE_Pos       (10U)\r\n#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */\r\n#define TIM_CCMR3_OC6PE_Pos       (11U)\r\n#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */\r\n#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */\r\n\r\n#define TIM_CCMR3_OC6M_Pos        (12U)\r\n#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */\r\n#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */\r\n\r\n#define TIM_CCMR3_OC6CE_Pos       (15U)\r\n#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */\r\n#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */\r\n/*******************  Bit definition for TIM1_AF1 register  *********************/\r\n#define TIM1_AF1_BKINE_Pos        (0U)\r\n#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */\r\n#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */\r\n#define TIM1_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\r\n#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM1_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\r\n#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */\r\n#define TIM1_AF1_BKDF1BK0E_Pos    (8U)\r\n#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */\r\n#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */\r\n#define TIM1_AF1_BKINP_Pos        (9U)\r\n#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */\r\n#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */\r\n#define TIM1_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\r\n#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM1_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\r\n#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n#define TIM1_AF1_ETRSEL_Pos       (14U)\r\n#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\r\n#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */\r\n#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */\r\n#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */\r\n#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */\r\n#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM1_AF2 register  *********************/\r\n#define TIM1_AF2_BK2INE_Pos       (0U)\r\n#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */\r\n#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */\r\n#define TIM1_AF2_BK2CMP1E_Pos     (1U)\r\n#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\r\n#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */\r\n#define TIM1_AF2_BK2CMP2E_Pos     (2U)\r\n#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\r\n#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */\r\n#define TIM1_AF2_BK2DFBK1E_Pos    (8U)\r\n#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */\r\n#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */\r\n#define TIM1_AF2_BK2INP_Pos       (9U)\r\n#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */\r\n#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */\r\n#define TIM1_AF2_BK2CMP1P_Pos     (10U)\r\n#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\r\n#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */\r\n#define TIM1_AF2_BK2CMP2P_Pos     (11U)\r\n#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\r\n#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM_TISEL register  *********************/\r\n#define TIM_TISEL_TI1SEL_Pos      (0U)\r\n#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */\r\n#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/\r\n#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */\r\n#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */\r\n#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */\r\n#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */\r\n\r\n#define TIM_TISEL_TI2SEL_Pos      (8U)\r\n#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */\r\n#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/\r\n#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */\r\n#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */\r\n#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */\r\n#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */\r\n\r\n#define TIM_TISEL_TI3SEL_Pos      (16U)\r\n#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */\r\n#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/\r\n#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */\r\n#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */\r\n#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */\r\n#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */\r\n\r\n#define TIM_TISEL_TI4SEL_Pos      (24U)\r\n#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */\r\n#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/\r\n#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */\r\n#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */\r\n#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */\r\n#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */\r\n\r\n/*******************  Bit definition for TIM8_AF1 register  *********************/\r\n#define TIM8_AF1_BKINE_Pos        (0U)\r\n#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */\r\n#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */\r\n#define TIM8_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\r\n#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM8_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\r\n#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM8_AF1_BKDFBK2E_Pos     (8U)\r\n#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */\r\n#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */\r\n#define TIM8_AF1_BKINP_Pos        (9U)\r\n#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */\r\n#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */\r\n#define TIM8_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\r\n#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM8_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\r\n#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n#define TIM8_AF1_ETRSEL_Pos       (14U)\r\n#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\r\n#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */\r\n#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */\r\n#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */\r\n#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */\r\n#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */\r\n/*******************  Bit definition for TIM8_AF2 register  *********************/\r\n#define TIM8_AF2_BK2INE_Pos       (0U)\r\n#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */\r\n#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */\r\n#define TIM8_AF2_BK2CMP1E_Pos     (1U)\r\n#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\r\n#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */\r\n#define TIM8_AF2_BK2CMP2E_Pos     (2U)\r\n#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\r\n#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */\r\n#define TIM8_AF2_BK2DFBK3E_Pos    (8U)\r\n#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */\r\n#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */\r\n#define TIM8_AF2_BK2INP_Pos       (9U)\r\n#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */\r\n#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */\r\n#define TIM8_AF2_BK2CMP1P_Pos     (10U)\r\n#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\r\n#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */\r\n#define TIM8_AF2_BK2CMP2P_Pos     (11U)\r\n#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\r\n#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM2_AF1 register  *********************/\r\n#define TIM2_AF1_ETRSEL_Pos      (14U)\r\n#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\r\n#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */\r\n#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\r\n#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\r\n#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\r\n#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM3_AF1 register  *********************/\r\n#define TIM3_AF1_ETRSEL_Pos      (14U)\r\n#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\r\n#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */\r\n#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\r\n#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\r\n#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\r\n#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM5_AF1 register  *********************/\r\n#define TIM5_AF1_ETRSEL_Pos      (14U)\r\n#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\r\n#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */\r\n#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\r\n#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\r\n#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\r\n#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM15_AF1 register  *********************/\r\n#define TIM15_AF1_BKINE_Pos        (0U)\r\n#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */\r\n#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\r\n#define TIM15_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\r\n#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM15_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\r\n#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM15_AF1_BKDF1BK2E_Pos    (8U)\r\n#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r\n#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */\r\n#define TIM15_AF1_BKINP_Pos        (9U)\r\n#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */\r\n#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\r\n#define TIM15_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\r\n#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM15_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\r\n#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM16_ register  *********************/\r\n#define TIM16_AF1_BKINE_Pos        (0U)\r\n#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */\r\n#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\r\n#define TIM16_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\r\n#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM16_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\r\n#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM16_AF1_BKDF1BK2E_Pos    (8U)\r\n#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r\n#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */\r\n#define TIM16_AF1_BKINP_Pos        (9U)\r\n#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */\r\n#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\r\n#define TIM16_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\r\n#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM16_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\r\n#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM17_AF1 register  *********************/\r\n#define TIM17_AF1_BKINE_Pos        (0U)\r\n#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */\r\n#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\r\n#define TIM17_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\r\n#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM17_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\r\n#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM17_AF1_BKDF1BK2E_Pos    (8U)\r\n#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r\n#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */\r\n#define TIM17_AF1_BKINP_Pos        (9U)\r\n#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */\r\n#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\r\n#define TIM17_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\r\n#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM17_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\r\n#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Low Power Timer (LPTTIM)                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for LPTIM_ISR register  *******************/\r\n#define LPTIM_ISR_CMPM_Pos          (0U)\r\n#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */\r\n#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */\r\n#define LPTIM_ISR_ARRM_Pos          (1U)\r\n#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */\r\n#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */\r\n#define LPTIM_ISR_EXTTRIG_Pos       (2U)\r\n#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */\r\n#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */\r\n#define LPTIM_ISR_CMPOK_Pos         (3U)\r\n#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */\r\n#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */\r\n#define LPTIM_ISR_ARROK_Pos         (4U)\r\n#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */\r\n#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */\r\n#define LPTIM_ISR_UP_Pos            (5U)\r\n#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */\r\n#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\r\n#define LPTIM_ISR_DOWN_Pos          (6U)\r\n#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */\r\n#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\r\n\r\n/******************  Bit definition for LPTIM_ICR register  *******************/\r\n#define LPTIM_ICR_CMPMCF_Pos        (0U)\r\n#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */\r\n#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */\r\n#define LPTIM_ICR_ARRMCF_Pos        (1U)\r\n#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */\r\n#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */\r\n#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)\r\n#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */\r\n#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */\r\n#define LPTIM_ICR_CMPOKCF_Pos       (3U)\r\n#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */\r\n#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */\r\n#define LPTIM_ICR_ARROKCF_Pos       (4U)\r\n#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */\r\n#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */\r\n#define LPTIM_ICR_UPCF_Pos          (5U)\r\n#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */\r\n#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\r\n#define LPTIM_ICR_DOWNCF_Pos        (6U)\r\n#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\r\n\r\n/******************  Bit definition for LPTIM_IER register ********************/\r\n#define LPTIM_IER_CMPMIE_Pos        (0U)\r\n#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */\r\n#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */\r\n#define LPTIM_IER_ARRMIE_Pos        (1U)\r\n#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */\r\n#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */\r\n#define LPTIM_IER_EXTTRIGIE_Pos     (2U)\r\n#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */\r\n#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */\r\n#define LPTIM_IER_CMPOKIE_Pos       (3U)\r\n#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */\r\n#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */\r\n#define LPTIM_IER_ARROKIE_Pos       (4U)\r\n#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */\r\n#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */\r\n#define LPTIM_IER_UPIE_Pos          (5U)\r\n#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */\r\n#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\r\n#define LPTIM_IER_DOWNIE_Pos        (6U)\r\n#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\r\n\r\n/******************  Bit definition for LPTIM_CFGR register *******************/\r\n#define LPTIM_CFGR_CKSEL_Pos        (0U)\r\n#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */\r\n#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\r\n\r\n#define LPTIM_CFGR_CKPOL_Pos        (1U)\r\n#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */\r\n#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\r\n#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */\r\n#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */\r\n\r\n#define LPTIM_CFGR_CKFLT_Pos        (3U)\r\n#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */\r\n#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r\n#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */\r\n#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */\r\n\r\n#define LPTIM_CFGR_TRGFLT_Pos       (6U)\r\n#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */\r\n#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r\n#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */\r\n\r\n#define LPTIM_CFGR_PRESC_Pos        (9U)\r\n#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */\r\n#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\r\n#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */\r\n#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */\r\n#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */\r\n\r\n#define LPTIM_CFGR_TRIGSEL_Pos      (13U)\r\n#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */\r\n#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r\n#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */\r\n#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */\r\n#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */\r\n\r\n#define LPTIM_CFGR_TRIGEN_Pos       (17U)\r\n#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */\r\n#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r\n#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */\r\n#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */\r\n\r\n#define LPTIM_CFGR_TIMOUT_Pos       (19U)\r\n#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */\r\n#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */\r\n#define LPTIM_CFGR_WAVE_Pos         (20U)\r\n#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */\r\n#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */\r\n#define LPTIM_CFGR_WAVPOL_Pos       (21U)\r\n#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */\r\n#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\r\n#define LPTIM_CFGR_PRELOAD_Pos      (22U)\r\n#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */\r\n#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */\r\n#define LPTIM_CFGR_COUNTMODE_Pos    (23U)\r\n#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */\r\n#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */\r\n#define LPTIM_CFGR_ENC_Pos          (24U)\r\n#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */\r\n#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */\r\n\r\n/******************  Bit definition for LPTIM_CR register  ********************/\r\n#define LPTIM_CR_ENABLE_Pos         (0U)\r\n#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */\r\n#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */\r\n#define LPTIM_CR_SNGSTRT_Pos        (1U)\r\n#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */\r\n#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */\r\n#define LPTIM_CR_CNTSTRT_Pos        (2U)\r\n#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */\r\n#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\r\n#define LPTIM_CR_COUNTRST_Pos       (3U)\r\n#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */\r\n#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/\r\n#define LPTIM_CR_RSTARE_Pos         (4U)\r\n#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */\r\n#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/\r\n\r\n\r\n/******************  Bit definition for LPTIM_CMP register  *******************/\r\n#define LPTIM_CMP_CMP_Pos           (0U)\r\n#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */\r\n#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */\r\n\r\n/******************  Bit definition for LPTIM_ARR register  *******************/\r\n#define LPTIM_ARR_ARR_Pos           (0U)\r\n#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */\r\n#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\r\n\r\n/******************  Bit definition for LPTIM_CNT register  *******************/\r\n#define LPTIM_CNT_CNT_Pos           (0U)\r\n#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */\r\n#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */\r\n\r\n/******************  Bit definition for LPTIM_CFGR2 register  *****************/\r\n#define LPTIM_CFGR2_IN1SEL_Pos      (0U)\r\n#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */\r\n#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */\r\n#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */\r\n#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */\r\n#define LPTIM_CFGR2_IN2SEL_Pos      (4U)\r\n#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */\r\n#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */\r\n#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */\r\n#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    OCTOSPI                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*****************  Bit definition for OCTOSPI_CR register  *******************/\r\n#define OCTOSPI_CR_EN_Pos              (0U)\r\n#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */\r\n#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */\r\n#define OCTOSPI_CR_ABORT_Pos           (1U)\r\n#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */\r\n#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */\r\n#define OCTOSPI_CR_DMAEN_Pos           (2U)\r\n#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */\r\n#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */\r\n#define OCTOSPI_CR_TCEN_Pos            (3U)\r\n#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */\r\n#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */\r\n#define OCTOSPI_CR_DQM_Pos             (6U)\r\n#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */\r\n#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */\r\n#define OCTOSPI_CR_FSEL_Pos            (7U)\r\n#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */\r\n#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */\r\n#define OCTOSPI_CR_FTHRES_Pos          (8U)\r\n#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */\r\n#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */\r\n#define OCTOSPI_CR_TEIE_Pos            (16U)\r\n#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */\r\n#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */\r\n#define OCTOSPI_CR_TCIE_Pos            (17U)\r\n#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */\r\n#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */\r\n#define OCTOSPI_CR_FTIE_Pos            (18U)\r\n#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */\r\n#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */\r\n#define OCTOSPI_CR_SMIE_Pos            (19U)\r\n#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */\r\n#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */\r\n#define OCTOSPI_CR_TOIE_Pos            (20U)\r\n#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */\r\n#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */\r\n#define OCTOSPI_CR_APMS_Pos            (22U)\r\n#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */\r\n#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */\r\n#define OCTOSPI_CR_PMM_Pos             (23U)\r\n#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */\r\n#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */\r\n#define OCTOSPI_CR_FMODE_Pos           (28U)\r\n#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */\r\n#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */\r\n#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */\r\n#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR1 register  ******************/\r\n#define OCTOSPI_DCR1_CKMODE_Pos        (0U)\r\n#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */\r\n#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */\r\n#define OCTOSPI_DCR1_FRCK_Pos          (1U)\r\n#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */\r\n#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */\r\n#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)\r\n#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */\r\n#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */\r\n#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)\r\n#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */\r\n#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */\r\n#define OCTOSPI_DCR1_CSHT_Pos          (8U)\r\n#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */\r\n#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */\r\n#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)\r\n#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */\r\n#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */\r\n#define OCTOSPI_DCR1_MTYP_Pos          (24U)\r\n#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */\r\n#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */\r\n#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */\r\n#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */\r\n#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR2 register  ******************/\r\n#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)\r\n#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */\r\n#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */\r\n#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)\r\n#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */\r\n#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */\r\n#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */\r\n#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */\r\n#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR3 register  ******************/\r\n#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)\r\n#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */\r\n#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */\r\n#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)\r\n#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */\r\n#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR4 register  ******************/\r\n#define OCTOSPI_DCR4_REFRESH_Pos       (0U)\r\n#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */\r\n\r\n/*****************  Bit definition for OCTOSPI_SR register  *******************/\r\n#define OCTOSPI_SR_TEF_Pos             (0U)\r\n#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */\r\n#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */\r\n#define OCTOSPI_SR_TCF_Pos             (1U)\r\n#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */\r\n#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */\r\n#define OCTOSPI_SR_FTF_Pos             (2U)\r\n#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */\r\n#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */\r\n#define OCTOSPI_SR_SMF_Pos             (3U)\r\n#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */\r\n#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */\r\n#define OCTOSPI_SR_TOF_Pos             (4U)\r\n#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */\r\n#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */\r\n#define OCTOSPI_SR_BUSY_Pos            (5U)\r\n#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */\r\n#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */\r\n#define OCTOSPI_SR_FLEVEL_Pos          (8U)\r\n#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */\r\n#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */\r\n\r\n/****************  Bit definition for OCTOSPI_FCR register  *******************/\r\n#define OCTOSPI_FCR_CTEF_Pos           (0U)\r\n#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */\r\n#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */\r\n#define OCTOSPI_FCR_CTCF_Pos           (1U)\r\n#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */\r\n#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */\r\n#define OCTOSPI_FCR_CSMF_Pos           (3U)\r\n#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */\r\n#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */\r\n#define OCTOSPI_FCR_CTOF_Pos           (4U)\r\n#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */\r\n#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */\r\n\r\n/****************  Bit definition for OCTOSPI_DLR register  *******************/\r\n#define OCTOSPI_DLR_DL_Pos             (0U)\r\n#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */\r\n\r\n/*****************  Bit definition for OCTOSPI_AR register  *******************/\r\n#define OCTOSPI_AR_ADDRESS_Pos         (0U)\r\n#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */\r\n\r\n/*****************  Bit definition for OCTOSPI_DR register  *******************/\r\n#define OCTOSPI_DR_DATA_Pos            (0U)\r\n#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */\r\n\r\n/***************  Bit definition for OCTOSPI_PSMKR register  ******************/\r\n#define OCTOSPI_PSMKR_MASK_Pos         (0U)\r\n#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */\r\n\r\n/***************  Bit definition for OCTOSPI_PSMAR register  ******************/\r\n#define OCTOSPI_PSMAR_MATCH_Pos        (0U)\r\n#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */\r\n\r\n/****************  Bit definition for OCTOSPI_PIR register  *******************/\r\n#define OCTOSPI_PIR_INTERVAL_Pos       (0U)\r\n#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */\r\n#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */\r\n\r\n/****************  Bit definition for OCTOSPI_CCR register  *******************/\r\n#define OCTOSPI_CCR_IMODE_Pos          (0U)\r\n#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */\r\n#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */\r\n#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */\r\n#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */\r\n#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */\r\n#define OCTOSPI_CCR_IDTR_Pos           (3U)\r\n#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */\r\n#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */\r\n#define OCTOSPI_CCR_ISIZE_Pos          (4U)\r\n#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */\r\n#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */\r\n#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */\r\n#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */\r\n#define OCTOSPI_CCR_ADMODE_Pos         (8U)\r\n#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */\r\n#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */\r\n#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */\r\n#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */\r\n#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */\r\n#define OCTOSPI_CCR_ADDTR_Pos          (11U)\r\n#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */\r\n#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */\r\n#define OCTOSPI_CCR_ADSIZE_Pos         (12U)\r\n#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */\r\n#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */\r\n#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */\r\n#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */\r\n#define OCTOSPI_CCR_ABMODE_Pos         (16U)\r\n#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */\r\n#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */\r\n#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */\r\n#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */\r\n#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */\r\n#define OCTOSPI_CCR_ABDTR_Pos          (19U)\r\n#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */\r\n#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */\r\n#define OCTOSPI_CCR_ABSIZE_Pos         (20U)\r\n#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */\r\n#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */\r\n#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */\r\n#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */\r\n#define OCTOSPI_CCR_DMODE_Pos          (24U)\r\n#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */\r\n#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */\r\n#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */\r\n#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */\r\n#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */\r\n#define OCTOSPI_CCR_DDTR_Pos           (27U)\r\n#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */\r\n#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */\r\n#define OCTOSPI_CCR_DQSE_Pos           (29U)\r\n#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */\r\n#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */\r\n#define OCTOSPI_CCR_SIOO_Pos           (31U)\r\n#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */\r\n#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */\r\n\r\n/****************  Bit definition for OCTOSPI_TCR register  *******************/\r\n#define OCTOSPI_TCR_DCYC_Pos           (0U)\r\n#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */\r\n#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */\r\n#define OCTOSPI_TCR_DHQC_Pos           (28U)\r\n#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */\r\n#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */\r\n#define OCTOSPI_TCR_SSHIFT_Pos         (30U)\r\n#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */\r\n#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */\r\n\r\n/*****************  Bit definition for OCTOSPI_IR register  *******************/\r\n#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)\r\n#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */\r\n\r\n/****************  Bit definition for OCTOSPI_ABR register  *******************/\r\n#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)\r\n#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */\r\n\r\n/****************  Bit definition for OCTOSPI_LPTR register  ******************/\r\n#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)\r\n#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */\r\n#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */\r\n\r\n/****************  Bit definition for OCTOSPI_WPCCR register  *******************/\r\n#define OCTOSPI_WPCCR_IMODE_Pos        (0U)\r\n#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */\r\n#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */\r\n#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */\r\n#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */\r\n#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */\r\n#define OCTOSPI_WPCCR_IDTR_Pos         (3U)\r\n#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */\r\n#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)\r\n#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */\r\n#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */\r\n#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */\r\n#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */\r\n#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)\r\n#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */\r\n#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */\r\n#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */\r\n#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */\r\n#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */\r\n#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)\r\n#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */\r\n#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)\r\n#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */\r\n#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */\r\n#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */\r\n#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */\r\n#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)\r\n#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */\r\n#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */\r\n#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */\r\n#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */\r\n#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */\r\n#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)\r\n#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */\r\n#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)\r\n#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */\r\n#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */\r\n#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */\r\n#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */\r\n#define OCTOSPI_WPCCR_DMODE_Pos        (24U)\r\n#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */\r\n#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */\r\n#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */\r\n#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */\r\n#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */\r\n#define OCTOSPI_WPCCR_DDTR_Pos         (27U)\r\n#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */\r\n#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_DQSE_Pos         (29U)\r\n#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */\r\n#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */\r\n#define OCTOSPI_WPCCR_SIOO_Pos         (31U)\r\n#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */\r\n#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */\r\n\r\n/****************  Bit definition for OCTOSPI_WPTCR register  *******************/\r\n#define OCTOSPI_WPTCR_DCYC_Pos         (0U)\r\n#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */\r\n#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */\r\n#define OCTOSPI_WPTCR_DHQC_Pos         (28U)\r\n#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */\r\n#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */\r\n#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)\r\n#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */\r\n#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */\r\n\r\n/*****************  Bit definition for OCTOSPI_WPIR register  *******************/\r\n#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)\r\n#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */\r\n\r\n/****************  Bit definition for OCTOSPI_WPABR register  *******************/\r\n#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)\r\n#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */\r\n\r\n/****************  Bit definition for OCTOSPI_WCCR register  ******************/\r\n#define OCTOSPI_WCCR_IMODE_Pos         (0U)\r\n#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */\r\n#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */\r\n#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */\r\n#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */\r\n#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */\r\n#define OCTOSPI_WCCR_IDTR_Pos          (3U)\r\n#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */\r\n#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */\r\n#define OCTOSPI_WCCR_ISIZE_Pos         (4U)\r\n#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */\r\n#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */\r\n#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */\r\n#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */\r\n#define OCTOSPI_WCCR_ADMODE_Pos        (8U)\r\n#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */\r\n#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */\r\n#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */\r\n#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */\r\n#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */\r\n#define OCTOSPI_WCCR_ADDTR_Pos         (11U)\r\n#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */\r\n#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */\r\n#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)\r\n#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */\r\n#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */\r\n#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */\r\n#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */\r\n#define OCTOSPI_WCCR_ABMODE_Pos        (16U)\r\n#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */\r\n#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */\r\n#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */\r\n#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */\r\n#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */\r\n#define OCTOSPI_WCCR_ABDTR_Pos         (19U)\r\n#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */\r\n#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */\r\n#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)\r\n#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */\r\n#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */\r\n#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */\r\n#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */\r\n#define OCTOSPI_WCCR_DMODE_Pos         (24U)\r\n#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */\r\n#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */\r\n#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */\r\n#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */\r\n#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */\r\n#define OCTOSPI_WCCR_DDTR_Pos          (27U)\r\n#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */\r\n#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */\r\n#define OCTOSPI_WCCR_DQSE_Pos          (29U)\r\n#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */\r\n#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */\r\n#define OCTOSPI_WCCR_SIOO_Pos          (31U)\r\n#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */\r\n#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */\r\n\r\n/****************  Bit definition for OCTOSPI_WTCR register  ******************/\r\n#define OCTOSPI_WTCR_DCYC_Pos          (0U)\r\n#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */\r\n#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */\r\n\r\n/****************  Bit definition for OCTOSPI_WIR register  *******************/\r\n#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)\r\n#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */\r\n\r\n/****************  Bit definition for OCTOSPI_WABR register  ******************/\r\n#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)\r\n#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */\r\n\r\n/****************  Bit definition for OCTOSPI_HLCR register  ******************/\r\n#define OCTOSPI_HLCR_LM_Pos            (0U)\r\n#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */\r\n#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */\r\n#define OCTOSPI_HLCR_WZL_Pos           (1U)\r\n#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */\r\n#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */\r\n#define OCTOSPI_HLCR_TACC_Pos          (8U)\r\n#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */\r\n#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */\r\n#define OCTOSPI_HLCR_TRWR_Pos          (16U)\r\n#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */\r\n#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */\r\n\r\n/****************  Bit definition for OCTOSPI_VER register  *******************/\r\n#define OCTOSPI_VER_VER_Pos            (0U)\r\n#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */\r\n#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */\r\n\r\n/*****************  Bit definition for OCTOSPI_ID register  *******************/\r\n#define OCTOSPI_ID_ID_Pos              (0U)\r\n#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */\r\n\r\n/****************  Bit definition for OCTOSPI_MID register  *******************/\r\n#define OCTOSPI_MID_MID_Pos            (0U)\r\n#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                  OCTOSPIM                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/***************  Bit definition for OCTOSPIM_CR register  ********************/\r\n#define OCTOSPIM_CR_MUXEN_Pos          (0U)\r\n#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */\r\n#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */\r\n#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)\r\n#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */\r\n#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */\r\n\r\n/***************  Bit definition for OCTOSPIM_PCR register  *******************/\r\n#define OCTOSPIM_PCR_CLKEN_Pos         (0U)\r\n#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */\r\n#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */\r\n#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)\r\n#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */\r\n#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */\r\n#define OCTOSPIM_PCR_DQSEN_Pos         (4U)\r\n#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */\r\n#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */\r\n#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)\r\n#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */\r\n#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */\r\n#define OCTOSPIM_PCR_NCSEN_Pos         (8U)\r\n#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */\r\n#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */\r\n#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)\r\n#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */\r\n#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */\r\n#define OCTOSPIM_PCR_IOLEN_Pos         (16U)\r\n#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */\r\n#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */\r\n#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)\r\n#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */\r\n#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */\r\n#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */\r\n#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */\r\n#define OCTOSPIM_PCR_IOHEN_Pos         (24U)\r\n#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */\r\n#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */\r\n#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)\r\n#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */\r\n#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */\r\n#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */\r\n#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Analog Comparators (COMP)                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for COMP_SR register  ********************/\r\n#define COMP_SR_C1VAL_Pos            (0U)\r\n#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */\r\n#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk\r\n#define COMP_SR_C2VAL_Pos            (1U)\r\n#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */\r\n#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk\r\n#define COMP_SR_C1IF_Pos             (16U)\r\n#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */\r\n#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk\r\n#define COMP_SR_C2IF_Pos             (17U)\r\n#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */\r\n#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk\r\n/*******************  Bit definition for COMP_ICFR register  ********************/\r\n#define COMP_ICFR_C1IF_Pos           (16U)\r\n#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */\r\n#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk\r\n#define COMP_ICFR_C2IF_Pos           (17U)\r\n#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */\r\n#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk\r\n/*******************  Bit definition for COMP_OR register  ********************/\r\n#define COMP_OR_AFOPA6_Pos           (0U)\r\n#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */\r\n#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk\r\n#define COMP_OR_AFOPA8_Pos           (1U)\r\n#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */\r\n#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk\r\n#define COMP_OR_AFOPB12_Pos          (2U)\r\n#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */\r\n#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk\r\n#define COMP_OR_AFOPE6_Pos           (3U)\r\n#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */\r\n#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk\r\n#define COMP_OR_AFOPE15_Pos          (4U)\r\n#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */\r\n#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk\r\n#define COMP_OR_AFOPG2_Pos           (5U)\r\n#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */\r\n#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk\r\n#define COMP_OR_AFOPG3_Pos           (6U)\r\n#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */\r\n#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk\r\n#define COMP_OR_AFOPG4_Pos           (7U)\r\n#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */\r\n#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk\r\n#define COMP_OR_AFOPI1_Pos           (8U)\r\n#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */\r\n#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk\r\n#define COMP_OR_AFOPI4_Pos           (9U)\r\n#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */\r\n#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk\r\n#define COMP_OR_AFOPK2_Pos           (10U)\r\n#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */\r\n#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk\r\n\r\n/*!< ******************  Bit definition for COMP_CFGRx register  ********************/\r\n#define COMP_CFGRx_EN_Pos            (0U)\r\n#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */\r\n#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */\r\n#define COMP_CFGRx_BRGEN_Pos         (1U)\r\n#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */\r\n#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */\r\n#define COMP_CFGRx_SCALEN_Pos        (2U)\r\n#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */\r\n#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */\r\n#define COMP_CFGRx_POLARITY_Pos      (3U)\r\n#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */\r\n#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */\r\n#define COMP_CFGRx_WINMODE_Pos       (4U)\r\n#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */\r\n#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */\r\n#define COMP_CFGRx_ITEN_Pos          (6U)\r\n#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */\r\n#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */\r\n#define COMP_CFGRx_HYST_Pos          (8U)\r\n#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */\r\n#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */\r\n#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */\r\n#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */\r\n#define COMP_CFGRx_PWRMODE_Pos       (12U)\r\n#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */\r\n#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */\r\n#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */\r\n#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */\r\n#define COMP_CFGRx_INMSEL_Pos        (16U)\r\n#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */\r\n#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */\r\n#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */\r\n#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */\r\n#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */\r\n#define COMP_CFGRx_INPSEL_Pos        (20U)\r\n#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */\r\n#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */\r\n#define COMP_CFGRx_BLANKING_Pos      (24U)\r\n#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */\r\n#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */\r\n#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */\r\n#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */\r\n#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */\r\n#define COMP_CFGRx_LOCK_Pos          (31U)\r\n#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */\r\n#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for USART_CR1 register  *******************/\r\n#define USART_CR1_UE_Pos                (0U)\r\n#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */\r\n#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */\r\n#define USART_CR1_UESM_Pos              (1U)\r\n#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */\r\n#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */\r\n#define USART_CR1_RE_Pos                (2U)\r\n#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */\r\n#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */\r\n#define USART_CR1_TE_Pos                (3U)\r\n#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */\r\n#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */\r\n#define USART_CR1_IDLEIE_Pos            (4U)\r\n#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */\r\n#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */\r\n#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)\r\n#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */\r\n#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */\r\n#define USART_CR1_TCIE_Pos              (6U)\r\n#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */\r\n#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */\r\n#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)\r\n#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */\r\n#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */\r\n#define USART_CR1_PEIE_Pos              (8U)\r\n#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */\r\n#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */\r\n#define USART_CR1_PS_Pos                (9U)\r\n#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */\r\n#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */\r\n#define USART_CR1_PCE_Pos               (10U)\r\n#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */\r\n#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */\r\n#define USART_CR1_WAKE_Pos              (11U)\r\n#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */\r\n#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */\r\n#define USART_CR1_M_Pos                 (12U)\r\n#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */\r\n#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */\r\n#define USART_CR1_M0_Pos                (12U)\r\n#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */\r\n#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */\r\n#define USART_CR1_MME_Pos               (13U)\r\n#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */\r\n#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */\r\n#define USART_CR1_CMIE_Pos              (14U)\r\n#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */\r\n#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */\r\n#define USART_CR1_OVER8_Pos             (15U)\r\n#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */\r\n#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */\r\n#define USART_CR1_DEDT_Pos              (16U)\r\n#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */\r\n#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r\n#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */\r\n#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */\r\n#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */\r\n#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */\r\n#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */\r\n#define USART_CR1_DEAT_Pos              (21U)\r\n#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */\r\n#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r\n#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */\r\n#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */\r\n#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */\r\n#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */\r\n#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */\r\n#define USART_CR1_RTOIE_Pos             (26U)\r\n#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */\r\n#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */\r\n#define USART_CR1_EOBIE_Pos             (27U)\r\n#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */\r\n#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */\r\n#define USART_CR1_M1_Pos                (28U)\r\n#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */\r\n#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */\r\n#define USART_CR1_FIFOEN_Pos            (29U)\r\n#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */\r\n#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */\r\n#define USART_CR1_TXFEIE_Pos            (30U)\r\n#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */\r\n#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */\r\n#define USART_CR1_RXFFIE_Pos            (31U)\r\n#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */\r\n#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */\r\n\r\n/* Legacy define */\r\n#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE\r\n#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE\r\n\r\n/******************  Bit definition for USART_CR2 register  *******************/\r\n#define USART_CR2_SLVEN_Pos             (0U)\r\n#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */\r\n#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */\r\n#define USART_CR2_DIS_NSS_Pos           (3U)\r\n#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */\r\n#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */\r\n#define USART_CR2_ADDM7_Pos             (4U)\r\n#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */\r\n#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */\r\n#define USART_CR2_LBDL_Pos              (5U)\r\n#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */\r\n#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */\r\n#define USART_CR2_LBDIE_Pos             (6U)\r\n#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */\r\n#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */\r\n#define USART_CR2_LBCL_Pos              (8U)\r\n#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */\r\n#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */\r\n#define USART_CR2_CPHA_Pos              (9U)\r\n#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */\r\n#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */\r\n#define USART_CR2_CPOL_Pos              (10U)\r\n#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */\r\n#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */\r\n#define USART_CR2_CLKEN_Pos             (11U)\r\n#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */\r\n#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */\r\n#define USART_CR2_STOP_Pos              (12U)\r\n#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */\r\n#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */\r\n#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */\r\n#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */\r\n#define USART_CR2_LINEN_Pos             (14U)\r\n#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */\r\n#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */\r\n#define USART_CR2_SWAP_Pos              (15U)\r\n#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */\r\n#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */\r\n#define USART_CR2_RXINV_Pos             (16U)\r\n#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */\r\n#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */\r\n#define USART_CR2_TXINV_Pos             (17U)\r\n#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */\r\n#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */\r\n#define USART_CR2_DATAINV_Pos           (18U)\r\n#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */\r\n#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */\r\n#define USART_CR2_MSBFIRST_Pos          (19U)\r\n#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */\r\n#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */\r\n#define USART_CR2_ABREN_Pos             (20U)\r\n#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */\r\n#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/\r\n#define USART_CR2_ABRMODE_Pos           (21U)\r\n#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */\r\n#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r\n#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */\r\n#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */\r\n#define USART_CR2_RTOEN_Pos             (23U)\r\n#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */\r\n#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */\r\n#define USART_CR2_ADD_Pos               (24U)\r\n#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */\r\n#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */\r\n\r\n/******************  Bit definition for USART_CR3 register  *******************/\r\n#define USART_CR3_EIE_Pos               (0U)\r\n#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */\r\n#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */\r\n#define USART_CR3_IREN_Pos              (1U)\r\n#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */\r\n#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */\r\n#define USART_CR3_IRLP_Pos              (2U)\r\n#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */\r\n#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */\r\n#define USART_CR3_HDSEL_Pos             (3U)\r\n#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */\r\n#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */\r\n#define USART_CR3_NACK_Pos              (4U)\r\n#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */\r\n#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */\r\n#define USART_CR3_SCEN_Pos              (5U)\r\n#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */\r\n#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */\r\n#define USART_CR3_DMAR_Pos              (6U)\r\n#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */\r\n#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */\r\n#define USART_CR3_DMAT_Pos              (7U)\r\n#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */\r\n#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */\r\n#define USART_CR3_RTSE_Pos              (8U)\r\n#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */\r\n#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */\r\n#define USART_CR3_CTSE_Pos              (9U)\r\n#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */\r\n#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */\r\n#define USART_CR3_CTSIE_Pos             (10U)\r\n#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */\r\n#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */\r\n#define USART_CR3_ONEBIT_Pos            (11U)\r\n#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */\r\n#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */\r\n#define USART_CR3_OVRDIS_Pos            (12U)\r\n#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */\r\n#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */\r\n#define USART_CR3_DDRE_Pos              (13U)\r\n#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */\r\n#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */\r\n#define USART_CR3_DEM_Pos               (14U)\r\n#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */\r\n#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */\r\n#define USART_CR3_DEP_Pos               (15U)\r\n#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */\r\n#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */\r\n#define USART_CR3_SCARCNT_Pos           (17U)\r\n#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */\r\n#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r\n#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */\r\n#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */\r\n#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */\r\n#define USART_CR3_WUS_Pos               (20U)\r\n#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */\r\n#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\r\n#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */\r\n#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */\r\n#define USART_CR3_WUFIE_Pos             (22U)\r\n#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */\r\n#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */\r\n#define USART_CR3_TXFTIE_Pos            (23U)\r\n#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */\r\n#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */\r\n#define USART_CR3_TCBGTIE_Pos           (24U)\r\n#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */\r\n#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */\r\n#define USART_CR3_RXFTCFG_Pos           (25U)\r\n#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */\r\n#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */\r\n#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */\r\n#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */\r\n#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */\r\n#define USART_CR3_RXFTIE_Pos            (28U)\r\n#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */\r\n#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */\r\n#define USART_CR3_TXFTCFG_Pos           (29U)\r\n#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */\r\n#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */\r\n#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */\r\n#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */\r\n#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for USART_BRR register  *******************/\r\n#define USART_BRR_DIV_FRACTION_Pos      (0U)\r\n#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */\r\n#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */\r\n#define USART_BRR_DIV_MANTISSA_Pos      (4U)\r\n#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\r\n#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */\r\n\r\n/******************  Bit definition for USART_GTPR register  ******************/\r\n#define USART_GTPR_PSC_Pos              (0U)\r\n#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */\r\n#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */\r\n#define USART_GTPR_GT_Pos               (8U)\r\n#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */\r\n#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */\r\n\r\n/*******************  Bit definition for USART_RTOR register  *****************/\r\n#define USART_RTOR_RTO_Pos              (0U)\r\n#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */\r\n#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */\r\n#define USART_RTOR_BLEN_Pos             (24U)\r\n#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */\r\n#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */\r\n\r\n/*******************  Bit definition for USART_RQR register  ******************/\r\n#define USART_RQR_ABRRQ_Pos             (0U)\r\n#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */\r\n#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */\r\n#define USART_RQR_SBKRQ_Pos             (1U)\r\n#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */\r\n#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */\r\n#define USART_RQR_MMRQ_Pos              (2U)\r\n#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */\r\n#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */\r\n#define USART_RQR_RXFRQ_Pos             (3U)\r\n#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */\r\n#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */\r\n#define USART_RQR_TXFRQ_Pos             (4U)\r\n#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */\r\n#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */\r\n\r\n/*******************  Bit definition for USART_ISR register  ******************/\r\n#define USART_ISR_PE_Pos                (0U)\r\n#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */\r\n#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */\r\n#define USART_ISR_FE_Pos                (1U)\r\n#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */\r\n#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */\r\n#define USART_ISR_NE_Pos                (2U)\r\n#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */\r\n#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */\r\n#define USART_ISR_ORE_Pos               (3U)\r\n#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */\r\n#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */\r\n#define USART_ISR_IDLE_Pos              (4U)\r\n#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */\r\n#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */\r\n#define USART_ISR_RXNE_RXFNE_Pos        (5U)\r\n#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */\r\n#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */\r\n#define USART_ISR_TC_Pos                (6U)\r\n#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */\r\n#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */\r\n#define USART_ISR_TXE_TXFNF_Pos         (7U)\r\n#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */\r\n#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */\r\n#define USART_ISR_LBDF_Pos              (8U)\r\n#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */\r\n#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */\r\n#define USART_ISR_CTSIF_Pos             (9U)\r\n#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */\r\n#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */\r\n#define USART_ISR_CTS_Pos               (10U)\r\n#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */\r\n#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */\r\n#define USART_ISR_RTOF_Pos              (11U)\r\n#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */\r\n#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */\r\n#define USART_ISR_EOBF_Pos              (12U)\r\n#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */\r\n#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */\r\n#define USART_ISR_UDR_Pos               (13U)\r\n#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */\r\n#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */\r\n#define USART_ISR_ABRE_Pos              (14U)\r\n#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */\r\n#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */\r\n#define USART_ISR_ABRF_Pos              (15U)\r\n#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */\r\n#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */\r\n#define USART_ISR_BUSY_Pos              (16U)\r\n#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */\r\n#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */\r\n#define USART_ISR_CMF_Pos               (17U)\r\n#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */\r\n#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */\r\n#define USART_ISR_SBKF_Pos              (18U)\r\n#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */\r\n#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */\r\n#define USART_ISR_RWU_Pos               (19U)\r\n#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */\r\n#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */\r\n#define USART_ISR_WUF_Pos               (20U)\r\n#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */\r\n#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */\r\n#define USART_ISR_TEACK_Pos             (21U)\r\n#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */\r\n#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */\r\n#define USART_ISR_REACK_Pos             (22U)\r\n#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */\r\n#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */\r\n#define USART_ISR_TXFE_Pos              (23U)\r\n#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */\r\n#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */\r\n#define USART_ISR_RXFF_Pos              (24U)\r\n#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */\r\n#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */\r\n#define USART_ISR_TCBGT_Pos             (25U)\r\n#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */\r\n#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */\r\n#define USART_ISR_RXFT_Pos              (26U)\r\n#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */\r\n#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */\r\n#define USART_ISR_TXFT_Pos              (27U)\r\n#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */\r\n#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */\r\n\r\n/*******************  Bit definition for USART_ICR register  ******************/\r\n#define USART_ICR_PECF_Pos              (0U)\r\n#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */\r\n#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */\r\n#define USART_ICR_FECF_Pos              (1U)\r\n#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */\r\n#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */\r\n#define USART_ICR_NECF_Pos              (2U)\r\n#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */\r\n#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */\r\n#define USART_ICR_ORECF_Pos             (3U)\r\n#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */\r\n#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */\r\n#define USART_ICR_IDLECF_Pos            (4U)\r\n#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */\r\n#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */\r\n#define USART_ICR_TXFECF_Pos            (5U)\r\n#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */\r\n#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */\r\n#define USART_ICR_TCCF_Pos              (6U)\r\n#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */\r\n#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */\r\n#define USART_ICR_TCBGTCF_Pos           (7U)\r\n#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */\r\n#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */\r\n#define USART_ICR_LBDCF_Pos             (8U)\r\n#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */\r\n#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */\r\n#define USART_ICR_CTSCF_Pos             (9U)\r\n#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */\r\n#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */\r\n#define USART_ICR_RTOCF_Pos             (11U)\r\n#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */\r\n#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */\r\n#define USART_ICR_EOBCF_Pos             (12U)\r\n#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */\r\n#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */\r\n#define USART_ICR_UDRCF_Pos             (13U)\r\n#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */\r\n#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */\r\n#define USART_ICR_CMCF_Pos              (17U)\r\n#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */\r\n#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */\r\n#define USART_ICR_WUCF_Pos              (20U)\r\n#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */\r\n#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */\r\n\r\n/*******************  Bit definition for USART_RDR register  ******************/\r\n#define USART_RDR_RDR_Pos               (0U)\r\n#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */\r\n#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */\r\n\r\n/*******************  Bit definition for USART_TDR register  ******************/\r\n#define USART_TDR_TDR_Pos               (0U)\r\n#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */\r\n#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */\r\n\r\n/*******************  Bit definition for USART_PRESC register  ******************/\r\n#define USART_PRESC_PRESCALER_Pos       (0U)\r\n#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */\r\n#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */\r\n#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */\r\n#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */\r\n#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */\r\n#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*           Single Wire Protocol Master Interface (SWPMI)                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for SWPMI_CR register   ********************/\r\n#define SWPMI_CR_RXDMA_Pos       (0U)\r\n#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */\r\n#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */\r\n#define SWPMI_CR_TXDMA_Pos       (1U)\r\n#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */\r\n#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */\r\n#define SWPMI_CR_RXMODE_Pos      (2U)\r\n#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */\r\n#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */\r\n#define SWPMI_CR_TXMODE_Pos      (3U)\r\n#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */\r\n#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */\r\n#define SWPMI_CR_LPBK_Pos        (4U)\r\n#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */\r\n#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */\r\n#define SWPMI_CR_SWPACT_Pos      (5U)\r\n#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */\r\n#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */\r\n#define SWPMI_CR_DEACT_Pos       (10U)\r\n#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */\r\n#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */\r\n#define SWPMI_CR_SWPEN_Pos       (11U)\r\n#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */\r\n#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */\r\n\r\n/*******************  Bit definition for SWPMI_BRR register  ********************/\r\n#define SWPMI_BRR_BR_Pos         (0U)\r\n#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */\r\n#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */\r\n\r\n/*******************  Bit definition for SWPMI_ISR register  ********************/\r\n#define SWPMI_ISR_RXBFF_Pos      (0U)\r\n#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */\r\n#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */\r\n#define SWPMI_ISR_TXBEF_Pos      (1U)\r\n#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */\r\n#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */\r\n#define SWPMI_ISR_RXBERF_Pos     (2U)\r\n#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */\r\n#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */\r\n#define SWPMI_ISR_RXOVRF_Pos     (3U)\r\n#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */\r\n#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */\r\n#define SWPMI_ISR_TXUNRF_Pos     (4U)\r\n#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */\r\n#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */\r\n#define SWPMI_ISR_RXNE_Pos       (5U)\r\n#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */\r\n#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */\r\n#define SWPMI_ISR_TXE_Pos        (6U)\r\n#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */\r\n#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */\r\n#define SWPMI_ISR_TCF_Pos        (7U)\r\n#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */\r\n#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */\r\n#define SWPMI_ISR_SRF_Pos        (8U)\r\n#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */\r\n#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */\r\n#define SWPMI_ISR_SUSP_Pos       (9U)\r\n#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */\r\n#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */\r\n#define SWPMI_ISR_DEACTF_Pos     (10U)\r\n#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */\r\n#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */\r\n#define SWPMI_ISR_RDYF_Pos       (11U)\r\n#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */\r\n#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */\r\n\r\n/*******************  Bit definition for SWPMI_ICR register  ********************/\r\n#define SWPMI_ICR_CRXBFF_Pos     (0U)\r\n#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */\r\n#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */\r\n#define SWPMI_ICR_CTXBEF_Pos     (1U)\r\n#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */\r\n#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */\r\n#define SWPMI_ICR_CRXBERF_Pos    (2U)\r\n#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */\r\n#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */\r\n#define SWPMI_ICR_CRXOVRF_Pos    (3U)\r\n#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */\r\n#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */\r\n#define SWPMI_ICR_CTXUNRF_Pos    (4U)\r\n#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */\r\n#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */\r\n#define SWPMI_ICR_CTCF_Pos       (7U)\r\n#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */\r\n#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */\r\n#define SWPMI_ICR_CSRF_Pos       (8U)\r\n#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */\r\n#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */\r\n#define SWPMI_ICR_CRDYF_Pos      (11U)\r\n#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */\r\n#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */\r\n\r\n/*******************  Bit definition for SWPMI_IER register  ********************/\r\n#define SWPMI_IER_RXBFIE_Pos     (0U)\r\n#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */\r\n#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */\r\n#define SWPMI_IER_TXBEIE_Pos     (1U)\r\n#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */\r\n#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */\r\n#define SWPMI_IER_RXBERIE_Pos    (2U)\r\n#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */\r\n#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */\r\n#define SWPMI_IER_RXOVRIE_Pos    (3U)\r\n#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */\r\n#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */\r\n#define SWPMI_IER_TXUNRIE_Pos    (4U)\r\n#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */\r\n#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */\r\n#define SWPMI_IER_RIE_Pos        (5U)\r\n#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */\r\n#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */\r\n#define SWPMI_IER_TIE_Pos        (6U)\r\n#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */\r\n#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */\r\n#define SWPMI_IER_TCIE_Pos       (7U)\r\n#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */\r\n#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */\r\n#define SWPMI_IER_SRIE_Pos       (8U)\r\n#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */\r\n#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */\r\n#define SWPMI_IER_RDYIE_Pos      (11U)\r\n#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */\r\n#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */\r\n\r\n/*******************  Bit definition for SWPMI_RFL register  ********************/\r\n#define SWPMI_RFL_RFL_Pos        (0U)\r\n#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */\r\n#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */\r\n#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\r\n\r\n/*******************  Bit definition for SWPMI_TDR register  ********************/\r\n#define SWPMI_TDR_TD_Pos         (0U)\r\n#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */\r\n#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */\r\n\r\n/*******************  Bit definition for SWPMI_RDR register  ********************/\r\n#define SWPMI_RDR_RD_Pos         (0U)\r\n#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */\r\n#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */\r\n\r\n\r\n/*******************  Bit definition for SWPMI_OR register  ********************/\r\n#define SWPMI_OR_TBYP_Pos        (0U)\r\n#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */\r\n#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */\r\n#define SWPMI_OR_CLASS_Pos       (1U)\r\n#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */\r\n#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            Window WATCHDOG                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for WWDG_CR register  ********************/\r\n#define WWDG_CR_T_Pos           (0U)\r\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */\r\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */\r\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */\r\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */\r\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */\r\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */\r\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */\r\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */\r\n\r\n#define WWDG_CR_WDGA_Pos        (7U)\r\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */\r\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\r\n\r\n/*******************  Bit definition for WWDG_CFR register  *******************/\r\n#define WWDG_CFR_W_Pos          (0U)\r\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */\r\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\r\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */\r\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */\r\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */\r\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */\r\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */\r\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */\r\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */\r\n\r\n#define WWDG_CFR_EWI_Pos        (9U)\r\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */\r\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\r\n\r\n#define WWDG_CFR_WDGTB_Pos      (11U)\r\n#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */\r\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */\r\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */\r\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */\r\n#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */\r\n\r\n/*******************  Bit definition for WWDG_SR register  ********************/\r\n#define WWDG_SR_EWIF_Pos        (0U)\r\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */\r\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                DBG                                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*********************************  DEVICE ID  ********************************/\r\n#define STM32H7_DEV_ID           0x483UL\r\n\r\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\r\n#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)\r\n#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r\n#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk\r\n#define DBGMCU_IDCODE_REV_ID_Pos          (16U)\r\n#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r\n#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk\r\n\r\n/********************  Bit definition for DBGMCU_CR register  *****************/\r\n#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)\r\n#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk\r\n#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)\r\n#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */\r\n#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk\r\n#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)\r\n#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */\r\n#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk\r\n#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)\r\n#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */\r\n#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk\r\n#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)\r\n#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */\r\n#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk\r\n#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)\r\n#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */\r\n#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk\r\n#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)\r\n#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */\r\n#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk\r\n#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)\r\n#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */\r\n#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk\r\n#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)\r\n#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */\r\n#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk\r\n\r\n/********************  Bit definition for APB3FZ1 register  ************/\r\n#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)\r\n#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */\r\n#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk\r\n/********************  Bit definition for APB1LFZ1 register  ************/\r\n#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)\r\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */\r\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C5_Pos      (25U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C5_Pos) /*!< 0x02000000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C5          DBGMCU_APB1LFZ1_DBG_I2C5_Msk\r\n\r\n/********************  Bit definition for APB1HFZ1 register  ************/\r\n#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)\r\n#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */\r\n#define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk\r\n#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)\r\n#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */\r\n#define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk\r\n/********************  Bit definition for APB2FZ1 register  ************/\r\n#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk\r\n/********************  Bit definition for APB4FZ1 register  ************/\r\n#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)\r\n#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */\r\n#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk\r\n#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)\r\n#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */\r\n#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk\r\n#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)\r\n#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */\r\n#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk\r\n/********************  Bit definition for DBGMCU_PIDR4 register  ************/\r\n#define DBGMCU_PIDR4_JEP106CON_Pos        (0U)\r\n#define DBGMCU_PIDR4_JEP106CON_Msk        (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */\r\n#define DBGMCU_PIDR4_JEP106CON            DBGMCU_PIDR4_JEP106CON_Msk\r\n#define DBGMCU_PIDR4_4KCOUNT_Pos          (4U)\r\n#define DBGMCU_PIDR4_4KCOUNT_Msk          (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)   /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR4_4KCOUNT              DBGMCU_PIDR4_4KCOUNT_Msk\r\n/********************  Bit definition for DBGMCU_PIDR0 register  ************/\r\n#define DBGMCU_PIDR0_PARTNUM_Pos        (0U)\r\n#define DBGMCU_PIDR0_PARTNUM_Msk        (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_PIDR0_PARTNUM            DBGMCU_PIDR0_PARTNUM_Msk\r\n/********************  Bit definition for DBGMCU_PIDR1 register  ************/\r\n#define DBGMCU_PIDR1_PARTNUM_Pos        (0U)\r\n#define DBGMCU_PIDR1_PARTNUM_Msk        (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)  /*!< 0x0000000F */\r\n#define DBGMCU_PIDR1_PARTNUM            DBGMCU_PIDR1_PARTNUM_Msk\r\n#define DBGMCU_PIDR1_JEP106ID_Pos       (4U)\r\n#define DBGMCU_PIDR1_JEP106ID_Msk       (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR1_JEP106ID           DBGMCU_PIDR1_JEP106ID_Msk\r\n/********************  Bit definition for DBGMCU_PIDR2 register  ************/\r\n#define DBGMCU_PIDR2_JEP106ID_Pos        (0U)\r\n#define DBGMCU_PIDR2_JEP106ID_Msk        (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)  /*!< 0x00000007 */\r\n#define DBGMCU_PIDR2_JEP106ID            DBGMCU_PIDR2_JEP106ID_Msk\r\n#define DBGMCU_PIDR2_JEDEC_Pos           (3U)\r\n#define DBGMCU_PIDR2_JEDEC_Msk           (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)  /*!< 0x00000008 */\r\n#define DBGMCU_PIDR2_JEDEC               DBGMCU_PIDR2_JEDEC_Msk\r\n#define DBGMCU_PIDR2_REVISION_Pos        (4U)\r\n#define DBGMCU_PIDR2_REVISION_Msk        (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR2_REVISION            DBGMCU_PIDR2_REVISION_Msk\r\n/********************  Bit definition for DBGMCU_PIDR3 register  ************/\r\n#define DBGMCU_PIDR3_CMOD_Pos            (0U)\r\n#define DBGMCU_PIDR3_CMOD_Msk            (0xFUL << DBGMCU_PIDR3_CMOD_Pos)  /*!< 0x0000000F */\r\n#define DBGMCU_PIDR3_CMOD                DBGMCU_PIDR3_CMOD_Msk\r\n#define DBGMCU_PIDR3_REVAND_Pos          (4U)\r\n#define DBGMCU_PIDR3_REVAND_Msk          (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR3_REVAND              DBGMCU_PIDR3_REVAND_Msk\r\n/********************  Bit definition for DBGMCU_CIDR0 register  ************/\r\n#define DBGMCU_CIR0_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR0_PREAMBLE_Msk         (0xFFUL << DBGMCU_CIR0_PREAMBLE_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_CIR0_PREAMBLE             DBGMCU_CIR0_PREAMBLE_Msk\r\n/********************  Bit definition for DBGMCU_CIDR1 register  ************/\r\n#define DBGMCU_CIR1_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR1_PREAMBLE_Msk         (0xFUL << DBGMCU_CIR1_PREAMBLE_Pos)  /*!< 0x0000000F */\r\n#define DBGMCU_CIR1_PREAMBLE             DBGMCU_CIR1_PREAMBLE_Msk\r\n#define DBGMCU_CIR1_CLASS_Pos            (4U)\r\n#define DBGMCU_CIR1_CLASS_Msk            (0xFUL << DBGMCU_CIR1_CLASS_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_CIR1_CLASS                DBGMCU_CIR1_CLASS_Msk\r\n/********************  Bit definition for DBGMCU_CIDR2 register  ************/\r\n#define DBGMCU_CIR2_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR2_PREAMBLE_Msk         (0xFFUL << DBGMCU_CIR2_PREAMBLE_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_CIR2_PREAMBLE             DBGMCU_CIR2_PREAMBLE_Msk\r\n/********************  Bit definition for DBGMCU_CIDR3 register  ************/\r\n#define DBGMCU_CIR3_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR3_PREAMBLE_Msk         (0xFFUL << DBGMCU_CIR3_PREAMBLE_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_CIR3_PREAMBLE             DBGMCU_CIR3_PREAMBLE_Msk\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             RAM ECC monitoring                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for RAMECC_IER register  ******************/\r\n#define RAMECC_IER_GECCDEBWIE_Pos         (3U)\r\n#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */\r\n#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */\r\n#define RAMECC_IER_GECCDEIE_Pos           (2U)\r\n#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */\r\n#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */\r\n#define RAMECC_IER_GECCSEIE_Pos           (1U)\r\n#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */\r\n#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */\r\n#define RAMECC_IER_GIE_Pos                (0U)\r\n#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */\r\n#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */\r\n\r\n/*******************  Bit definition for RAMECC_CR register  ******************/\r\n#define RAMECC_CR_ECCELEN_Pos             (5U)\r\n#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */\r\n#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */\r\n#define RAMECC_CR_ECCDEBWIE_Pos           (4U)\r\n#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */\r\n#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */\r\n#define RAMECC_CR_ECCDEIE_Pos             (3U)\r\n#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */\r\n#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */\r\n#define RAMECC_CR_ECCSEIE_Pos             (2U)\r\n#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */\r\n#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */\r\n\r\n/*******************  Bit definition for RAMECC_SR register  ******************/\r\n#define RAMECC_SR_DEBWDF_Pos             (2U)\r\n#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */\r\n#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */\r\n#define RAMECC_SR_DEDF_Pos               (1U)\r\n#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */\r\n#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */\r\n#define RAMECC_SR_SEDCF_Pos              (0U)\r\n#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */\r\n#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */\r\n\r\n/******************  Bit definition for RAMECC_FAR register  ******************/\r\n#define RAMECC_FAR_FADD_Pos              (0U)\r\n#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */\r\n#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */\r\n\r\n/******************  Bit definition for RAMECC_FDRL register  *****************/\r\n#define RAMECC_FAR_FDATAL_Pos            (0U)\r\n#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */\r\n#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */\r\n\r\n/******************  Bit definition for RAMECC_FDRH register  *****************/\r\n#define RAMECC_FAR_FDATAH_Pos            (0U)\r\n#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */\r\n#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */\r\n\r\n/*****************  Bit definition for RAMECC_FECR register  ******************/\r\n#define RAMECC_FECR_FEC_Pos              (0U)\r\n#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */\r\n#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                MDIOS                                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for MDIOS_CR register  *******************/\r\n#define MDIOS_CR_EN_Pos                (0U)\r\n#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */\r\n#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */\r\n#define MDIOS_CR_WRIE_Pos              (1U)\r\n#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */\r\n#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */\r\n#define MDIOS_CR_RDIE_Pos              (2U)\r\n#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */\r\n#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */\r\n#define MDIOS_CR_EIE_Pos               (3U)\r\n#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */\r\n#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */\r\n#define MDIOS_CR_DPC_Pos               (7U)\r\n#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */\r\n#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */\r\n#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)\r\n#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */\r\n#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */\r\n#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */\r\n#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */\r\n#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */\r\n#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */\r\n#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */\r\n\r\n/********************  Bit definition for MDIOS_SR register  *******************/\r\n#define MDIOS_SR_PERF_Pos              (0U)\r\n#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */\r\n#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/\r\n#define MDIOS_SR_SERF_Pos              (1U)\r\n#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */\r\n#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */\r\n#define MDIOS_SR_TERF_Pos              (2U)\r\n#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */\r\n#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */\r\n\r\n/********************  Bit definition for MDIOS_CLRFR register  *******************/\r\n#define MDIOS_SR_CPERF_Pos             (0U)\r\n#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */\r\n#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */\r\n#define MDIOS_SR_CSERF_Pos             (1U)\r\n#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */\r\n#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */\r\n#define MDIOS_SR_CTERF_Pos             (2U)\r\n#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */\r\n#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                       USB_OTG                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/\r\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\r\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\r\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\r\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\r\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\r\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\r\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\r\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\r\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\r\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\r\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\r\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\r\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\r\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\r\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\r\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\r\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\r\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\r\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\r\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\r\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\r\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\r\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\r\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\r\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\r\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\r\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\r\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\r\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\r\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\r\n\r\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\r\n\r\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\r\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\r\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\r\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\r\n\r\n/********************  Bit definition forUSB_OTG_DCFG register  ********************/\r\n\r\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\r\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\r\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\r\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\r\n\r\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\r\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\r\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r\n\r\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\r\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\r\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r\n\r\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\r\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\r\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_PCGCR register  ********************/\r\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\r\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\r\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\r\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\r\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\r\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\r\n\r\n/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/\r\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\r\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\r\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\r\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\r\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\r\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\r\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\r\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\r\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\r\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\r\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\r\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\r\n\r\n/********************  Bit definition forUSB_OTG_DCTL register  ********************/\r\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\r\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\r\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\r\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\r\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\r\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\r\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\r\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\r\n\r\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\r\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\r\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\r\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\r\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\r\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\r\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\r\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\r\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\r\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\r\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\r\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\r\n\r\n/********************  Bit definition forUSB_OTG_HFIR register  ********************/\r\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\r\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\r\n\r\n/********************  Bit definition forUSB_OTG_HFNUM register  ********************/\r\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\r\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\r\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\r\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\r\n\r\n/********************  Bit definition forUSB_OTG_DSTS register  ********************/\r\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\r\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\r\n\r\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\r\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\r\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\r\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\r\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\r\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\r\n\r\n/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/\r\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\r\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\r\n\r\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\r\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\r\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\r\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\r\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\r\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\r\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\r\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\r\n\r\n/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/\r\n\r\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\r\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\r\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\r\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\r\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\r\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\r\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\r\n\r\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\r\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\r\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\r\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\r\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\r\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\r\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\r\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\r\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\r\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\r\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\r\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\r\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\r\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\r\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\r\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\r\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\r\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\r\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\r\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\r\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\r\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\r\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\r\n\r\n/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/\r\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\r\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\r\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\r\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\r\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\r\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\r\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\r\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\r\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\r\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\r\n\r\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\r\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\r\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\r\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\r\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\r\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/\r\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\r\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\r\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\r\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\r\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\r\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\r\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\r\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\r\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\r\n\r\n/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/\r\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\r\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\r\n\r\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\r\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r\n\r\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\r\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_HAINT register  ********************/\r\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\r\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/\r\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\r\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\r\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\r\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\r\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */\r\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\r\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\r\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\r\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\r\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\r\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\r\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\r\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\r\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\r\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\r\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\r\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\r\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */\r\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\r\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */\r\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\r\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */\r\n\r\n/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/\r\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\r\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\r\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\r\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\r\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\r\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\r\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\r\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\r\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\r\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\r\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\r\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\r\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\r\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\r\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\r\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\r\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\r\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\r\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\r\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\r\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\r\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\r\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\r\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\r\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\r\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\r\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\r\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\r\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\r\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\r\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\r\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\r\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\r\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\r\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\r\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\r\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\r\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\r\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\r\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\r\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\r\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\r\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\r\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\r\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\r\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\r\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\r\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\r\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\r\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\r\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\r\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\r\n\r\n/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/\r\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\r\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\r\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\r\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\r\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\r\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\r\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\r\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\r\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\r\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\r\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\r\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\r\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\r\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\r\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\r\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\r\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\r\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\r\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\r\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\r\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\r\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\r\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\r\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\r\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\r\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\r\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\r\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\r\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\r\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\r\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\r\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\r\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\r\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\r\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\r\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\r\n#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)\r\n#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */\r\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\r\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\r\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\r\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\r\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\r\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\r\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\r\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\r\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\r\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\r\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\r\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\r\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\r\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\r\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\r\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\r\n\r\n/********************  Bit definition forUSB_OTG_DAINT register  ********************/\r\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\r\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\r\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\r\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\r\n\r\n/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/\r\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\r\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\r\n\r\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\r\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\r\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\r\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\r\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\r\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\r\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/\r\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\r\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\r\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\r\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n\r\n#define USB_OTG_CHNUM_Pos                        (0U)\r\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */\r\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\r\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\r\n#define USB_OTG_BCNT_Pos                         (4U)\r\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\r\n\r\n#define USB_OTG_DPID_Pos                         (15U)\r\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */\r\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\r\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\r\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\r\n\r\n#define USB_OTG_PKTSTS_Pos                       (17U)\r\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\r\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\r\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\r\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\r\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\r\n\r\n#define USB_OTG_EPNUM_Pos                        (0U)\r\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */\r\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\r\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\r\n\r\n#define USB_OTG_FRMNUM_Pos                       (21U)\r\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\r\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\r\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\r\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\r\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/\r\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\r\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\r\n\r\n/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/\r\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\r\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n#define USB_OTG_NPTXFSA_Pos                      (0U)\r\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\r\n#define USB_OTG_NPTXFD_Pos                       (16U)\r\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\r\n#define USB_OTG_TX0FSA_Pos                       (0U)\r\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\r\n#define USB_OTG_TX0FD_Pos                        (16U)\r\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\r\n\r\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\r\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\r\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r\n\r\n/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/\r\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\r\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\r\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\r\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\r\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r\n\r\n/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/\r\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\r\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\r\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\r\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\r\n\r\n/********************  Bit definition forUSB_OTG_GCCFG register  ********************/\r\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\r\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\r\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\r\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\r\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\r\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\r\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\r\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\r\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\r\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\r\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\r\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\r\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\r\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\r\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\r\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\r\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\r\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\r\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\r\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */\r\n\r\n/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/\r\n#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)\r\n#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */\r\n#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)\r\n#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */\r\n\r\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r\n\r\n/********************  Bit definition forUSB_OTG_CID register  ********************/\r\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\r\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\r\n\r\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\r\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\r\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\r\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\r\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\r\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\r\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\r\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\r\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\r\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\r\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\r\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\r\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\r\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\r\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\r\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\r\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\r\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\r\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\r\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\r\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\r\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\r\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\r\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\r\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\r\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\r\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\r\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\r\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\r\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\r\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\r\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\r\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\r\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r\n\r\n/********************  Bit definition forUSB_OTG_HPRT register  ********************/\r\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\r\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\r\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\r\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\r\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\r\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\r\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\r\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\r\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\r\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\r\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\r\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\r\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\r\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */\r\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\r\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */\r\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\r\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */\r\n\r\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\r\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */\r\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\r\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */\r\n\r\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\r\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */\r\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r\n\r\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\r\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */\r\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\r\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\r\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\r\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\r\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\r\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\r\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\r\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r\n\r\n/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/\r\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\r\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */\r\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\r\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/\r\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\r\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */\r\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\r\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\r\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\r\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */\r\n\r\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\r\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */\r\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\r\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */\r\n\r\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\r\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */\r\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\r\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */\r\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\r\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\r\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\r\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\r\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */\r\n\r\n/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/\r\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\r\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\r\n\r\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\r\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\r\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\r\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\r\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\r\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\r\n\r\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\r\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\r\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r\n\r\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\r\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\r\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r\n\r\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\r\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\r\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\r\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\r\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\r\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\r\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\r\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\r\n\r\n/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/\r\n\r\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\r\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\r\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r\n\r\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\r\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\r\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r\n\r\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\r\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\r\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\r\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\r\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\r\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\r\n\r\n/********************  Bit definition forUSB_OTG_HCINT register  ********************/\r\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\r\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\r\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\r\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\r\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\r\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\r\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\r\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\r\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\r\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\r\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\r\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\r\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\r\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\r\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\r\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\r\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\r\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\r\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\r\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\r\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\r\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/\r\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\r\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\r\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\r\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\r\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\r\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\r\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\r\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\r\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\r\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\r\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\r\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\r\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\r\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\r\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\r\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\r\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\r\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\r\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\r\n\r\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\r\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\r\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\r\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\r\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\r\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\r\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\r\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\r\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\r\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\r\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\r\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\r\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\r\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\r\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\r\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\r\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\r\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\r\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\r\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\r\n\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\r\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\r\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\r\n/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/\r\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\r\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\r\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\r\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\r\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\r\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\r\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\r\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\r\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/\r\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\r\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\r\n\r\n/********************  Bit definition forUSB_OTG_HCDMA register  ********************/\r\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\r\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\r\n\r\n/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/\r\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\r\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/\r\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\r\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\r\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\r\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/\r\n\r\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\r\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\r\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\r\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\r\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\r\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\r\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\r\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\r\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\r\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\r\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\r\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\r\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\r\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\r\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\r\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\r\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\r\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/\r\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\r\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\r\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\r\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\r\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\r\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\r\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\r\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\r\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\r\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */\r\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\r\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\r\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\r\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\r\n#define USB_OTG_DOEPINT_BNA_Pos                  (9U)\r\n#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */\r\n#define USB_OTG_DOEPINT_BERR_Pos                 (12U)\r\n#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */\r\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\r\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\r\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\r\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\r\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\r\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/\r\n\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\r\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r\n\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for PCGCCTL register  ********************/\r\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\r\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\r\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\r\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\r\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_macros\r\n  * @{\r\n  */\r\n\r\n/******************************* ADC Instances ********************************/\r\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\r\n                                       ((INSTANCE) == ADC2) || \\\r\n                                       ((INSTANCE) == ADC3))\r\n\r\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r\n\r\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\\\r\n                                          ((INSTANCE) == ADC3_COMMON))\r\n\r\n/******************************* CORDIC Instances *****************************/\r\n#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)\r\n\r\n/******************************** FMAC Instances ******************************/\r\n#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)\r\n\r\n/******************************** COMP Instances ******************************/\r\n#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\\r\n                                       ((INSTANCE) == COMP2))\r\n\r\n#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)\r\n/******************** COMP Instances with window mode capability **************/\r\n#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\r\n\r\n/******************************** DTS Instances ******************************/\r\n#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)\r\n\r\n/******************************* CRC Instances ********************************/\r\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r\n\r\n/******************************* DAC Instances ********************************/\r\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\r\n/******************************* DCMI Instances *******************************/\r\n#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r\n\r\n/******************************* DELAYBLOCK Instances *******************************/\r\n#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \\\r\n                                         ((INSTANCE) == DLYB_SDMMC2) || \\\r\n                                         ((INSTANCE) == DLYB_OCTOSPI1) || \\\r\n                                         ((INSTANCE) == DLYB_OCTOSPI2) )\r\n/****************************** DFSDM Instances *******************************/\r\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\r\n                                               ((INSTANCE) == DFSDM1_Filter1) || \\\r\n                                               ((INSTANCE) == DFSDM1_Filter2) || \\\r\n                                               ((INSTANCE) == DFSDM1_Filter3))\r\n\r\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel3) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel4) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel5) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel6) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel7))\r\n/****************************** RAMECC Instances ******************************/\r\n#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor6)   || \\\r\n                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \\\r\n                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \\\r\n                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \\\r\n                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \\\r\n                                                  ((INSTANCE) == RAMECC3_Monitor2))\r\n\r\n/******************************** DMA Instances *******************************/\r\n#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream1)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream2)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream3)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream4)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream5)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream6)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream7)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream0)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream1)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream2)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream3)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream4)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream5)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream6)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream7)   || \\\r\n                                       ((INSTANCE) == BDMA_Channel0) || \\\r\n                                       ((INSTANCE) == BDMA_Channel1) || \\\r\n                                       ((INSTANCE) == BDMA_Channel2) || \\\r\n                                       ((INSTANCE) == BDMA_Channel3) || \\\r\n                                       ((INSTANCE) == BDMA_Channel4) || \\\r\n                                       ((INSTANCE) == BDMA_Channel5) || \\\r\n                                       ((INSTANCE) == BDMA_Channel6) || \\\r\n                                       ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** BDMA CHANNEL Instances ***************************/\r\n#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \\\r\n                                            ((INSTANCE) == BDMA_Channel1) || \\\r\n                                            ((INSTANCE) == BDMA_Channel2) || \\\r\n                                            ((INSTANCE) == BDMA_Channel3) || \\\r\n                                            ((INSTANCE) == BDMA_Channel4) || \\\r\n                                            ((INSTANCE) == BDMA_Channel5) || \\\r\n                                            ((INSTANCE) == BDMA_Channel6) || \\\r\n                                            ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** DMA DMAMUX ALL Instances ***************************/\r\n#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream1)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream2)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream3)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream4)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream5)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream6)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream7)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream0)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream1)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream2)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream3)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream4)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream5)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream6)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream7)    || \\\r\n                                               ((INSTANCE) == BDMA_Channel0)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel1)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel2)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel3)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel4)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel5)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel6)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** BDMA DMAMUX Instances ***************************/\r\n#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel1) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel2) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel3) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel4) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel5) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel6) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** DMA STREAM Instances ***************************/\r\n#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream1)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream2)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream3)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream4)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream5)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream6)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream7)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream0)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream1)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream2)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream3)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream4)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream5)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream6)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream7))\r\n\r\n/****************************** DMA DMAMUX Instances ***************************/\r\n#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream1)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream2)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream3)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream4)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream5)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream6)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream7)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream0)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream1)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream2)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream3)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream4)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream5)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream6)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream7))\r\n\r\n/******************************** DMA Request Generator Instances **************/\r\n#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))\r\n\r\n/******************************* DMA2D Instances *******************************/\r\n#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r\n\r\n/******************************* OTFDEC Instances ******************************/\r\n#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \\\r\n                                              ((__INSTANCE__) == OTFDEC2))\r\n\r\n/****************************** PSSI Instance *********************************/\r\n#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)\r\n\r\n/******************************** MDMA Request Generator Instances **************/\r\n#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel1)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel2)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel3)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel4)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel5)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel6)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel7)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel8)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel9)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel10) || \\\r\n                                               ((INSTANCE) == MDMA_Channel11) || \\\r\n                                               ((INSTANCE) == MDMA_Channel12) || \\\r\n                                               ((INSTANCE) == MDMA_Channel13) || \\\r\n                                               ((INSTANCE) == MDMA_Channel14) || \\\r\n                                               ((INSTANCE) == MDMA_Channel15))\r\n\r\n\r\n/******************************* FDCAN Instances ******************************/\r\n#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \\\r\n                                             ((__INSTANCE__) == FDCAN2) || \\\r\n                                             ((__INSTANCE__) == FDCAN3))\r\n\r\n#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)\r\n\r\n/******************************* GPIO Instances *******************************/\r\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\r\n                                        ((INSTANCE) == GPIOB) || \\\r\n                                        ((INSTANCE) == GPIOC) || \\\r\n                                        ((INSTANCE) == GPIOD) || \\\r\n                                        ((INSTANCE) == GPIOE) || \\\r\n                                        ((INSTANCE) == GPIOF) || \\\r\n                                        ((INSTANCE) == GPIOG) || \\\r\n                                        ((INSTANCE) == GPIOH) || \\\r\n                                        ((INSTANCE) == GPIOJ) || \\\r\n                                        ((INSTANCE) == GPIOK))\r\n\r\n/******************************* GPIO AF Instances ****************************/\r\n#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\r\n\r\n/**************************** GPIO Lock Instances *****************************/\r\n/* On H7, all GPIO Bank support the Lock mechanism */\r\n#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r\n\r\n/******************************** HSEM Instances *******************************/\r\n#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)\r\n#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */\r\n#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\r\n#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\r\n\r\n#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/\r\n#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */\r\n\r\n#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */\r\n#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */\r\n\r\n#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */\r\n#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */\r\n\r\n/******************************** I2C Instances *******************************/\r\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\r\n                                       ((INSTANCE) == I2C2) || \\\r\n                                       ((INSTANCE) == I2C3) || \\\r\n                                       ((INSTANCE) == I2C4) || \\\r\n                                       ((INSTANCE) == I2C5))\r\n\r\n/****************************** SMBUS Instances *******************************/\r\n#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\r\n                                         ((INSTANCE) == I2C2) || \\\r\n                                         ((INSTANCE) == I2C3) || \\\r\n                                         ((INSTANCE) == I2C4) || \\\r\n                                         ((INSTANCE) == I2C5))\r\n\r\n/************** I2C Instances : wakeup capability from stop modes *************/\r\n#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\r\n\r\n/******************************** I2S Instances *******************************/\r\n#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \\\r\n                                         ((INSTANCE) == SPI2) || \\\r\n                                         ((INSTANCE) == SPI3))\r\n\r\n/****************************** LTDC Instances ********************************/\r\n#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)\r\n\r\n/******************************* RNG Instances ********************************/\r\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\r\n\r\n/****************************** RTC Instances *********************************/\r\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\r\n\r\n/****************************** SDMMC Instances *********************************/\r\n#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \\\r\n                                           ((_INSTANCE_) == SDMMC2))\r\n\r\n/******************************** SPI Instances *******************************/\r\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\r\n                                       ((INSTANCE) == SPI2) || \\\r\n                                       ((INSTANCE) == SPI3) || \\\r\n                                       ((INSTANCE) == SPI4) || \\\r\n                                       ((INSTANCE) == SPI5) || \\\r\n                                       ((INSTANCE) == SPI6))\r\n\r\n#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\r\n                                           ((INSTANCE) == SPI2) || \\\r\n                                           ((INSTANCE) == SPI3))\r\n\r\n/******************************** SWPMI Instances *****************************/\r\n#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)\r\n\r\n/****************** LPTIM Instances : All supported instances *****************/\r\n#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\r\n                                         ((INSTANCE) == LPTIM2) || \\\r\n                                         ((INSTANCE) == LPTIM3) || \\\r\n                                         ((INSTANCE) == LPTIM4) || \\\r\n                                         ((INSTANCE) == LPTIM5))\r\n\r\n/****************** LPTIM Instances : supporting encoder interface **************/\r\n#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\r\n                                                           ((INSTANCE) == LPTIM2))\r\n\r\n/****************** TIM Instances : All supported instances *******************/\r\n#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM6)   || \\\r\n                                         ((INSTANCE) == TIM7)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM12)  || \\\r\n                                         ((INSTANCE) == TIM13)  || \\\r\n                                         ((INSTANCE) == TIM14)  || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM16)  || \\\r\n                                         ((INSTANCE) == TIM17)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************* TIM Instances : at least 1 capture/compare channel *************/\r\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM12)  || \\\r\n                                         ((INSTANCE) == TIM13)  || \\\r\n                                         ((INSTANCE) == TIM14)  || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM16)  || \\\r\n                                         ((INSTANCE) == TIM17)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 2 capture/compare channels *************/\r\n#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM12)  || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 3 capture/compare channels *************/\r\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 4 capture/compare channels *************/\r\n#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 5 capture/compare channels *************/\r\n#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM8))\r\n/************ TIM Instances : at least 6 capture/compare channels *************/\r\n#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM8))\r\n\r\n/******************** TIM Instances : Advanced-control timers *****************/\r\n#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                                ((__INSTANCE__) == TIM8))\r\n\r\n/******************** TIM Instances : Advanced-control timers *****************/\r\n\r\n/******************* TIM Instances : Timer input XOR function *****************/\r\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : DMA requests generation (UDE) *************/\r\n#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM2)   || \\\r\n                                           ((INSTANCE) == TIM3)   || \\\r\n                                           ((INSTANCE) == TIM4)   || \\\r\n                                           ((INSTANCE) == TIM5)   || \\\r\n                                           ((INSTANCE) == TIM6)   || \\\r\n                                           ((INSTANCE) == TIM7)   || \\\r\n                                           ((INSTANCE) == TIM8)   || \\\r\n                                           ((INSTANCE) == TIM15)  || \\\r\n                                           ((INSTANCE) == TIM16)  || \\\r\n                                           ((INSTANCE) == TIM17)  || \\\r\n                                           ((INSTANCE) == TIM23)  || \\\r\n                                           ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM8)   || \\\r\n                                            ((INSTANCE) == TIM15)  || \\\r\n                                            ((INSTANCE) == TIM16)  || \\\r\n                                            ((INSTANCE) == TIM17)  || \\\r\n                                            ((INSTANCE) == TIM23)  || \\\r\n                                            ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\r\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM8)   || \\\r\n                                            ((INSTANCE) == TIM15))\r\n\r\n/******************** TIM Instances : DMA burst feature ***********************/\r\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM8))\r\n\r\n/*************** TIM Instances : external trigger reamp input available *******/\r\n#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM2)   || \\\r\n                                           ((INSTANCE) == TIM3)   || \\\r\n                                           ((INSTANCE) == TIM4)   || \\\r\n                                           ((INSTANCE) == TIM5)   || \\\r\n                                           ((INSTANCE) == TIM8)   || \\\r\n                                           ((INSTANCE) == TIM23)   || \\\r\n                                           ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : remapping capability **********************/\r\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\r\n                                         ((INSTANCE) == TIM2)  || \\\r\n                                         ((INSTANCE) == TIM3)  || \\\r\n                                         ((INSTANCE) == TIM5)  || \\\r\n                                         ((INSTANCE) == TIM8)  || \\\r\n                                         ((INSTANCE) == TIM16) || \\\r\n                                         ((INSTANCE) == TIM17) || \\\r\n                                         ((INSTANCE) == TIM23) || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/*************** TIM Instances : external trigger reamp input available *******/\r\n#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)  || \\\r\n                                              ((INSTANCE) == TIM2)  || \\\r\n                                              ((INSTANCE) == TIM3)  || \\\r\n                                              ((INSTANCE) == TIM5)  || \\\r\n                                              ((INSTANCE) == TIM8)  || \\\r\n                                              ((INSTANCE) == TIM23) || \\\r\n                                              ((INSTANCE) == TIM24)))\r\n\r\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM6)   || \\\r\n                                            ((INSTANCE) == TIM7)   || \\\r\n                                            ((INSTANCE) == TIM8)   || \\\r\n                                            ((INSTANCE) == TIM12)  || \\\r\n                                            ((INSTANCE) == TIM15)  || \\\r\n                                            ((INSTANCE) == TIM23)  || \\\r\n                                            ((INSTANCE) == TIM24))\r\n\r\n/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/\r\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM2)   || \\\r\n                                           ((INSTANCE) == TIM3)   || \\\r\n                                           ((INSTANCE) == TIM4)   || \\\r\n                                           ((INSTANCE) == TIM5)   || \\\r\n                                           ((INSTANCE) == TIM8)   || \\\r\n                                           ((INSTANCE) == TIM12)  || \\\r\n                                           ((INSTANCE) == TIM15)  || \\\r\n                                           ((INSTANCE) == TIM23)  || \\\r\n                                           ((INSTANCE) == TIM24))\r\n\r\n/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/\r\n#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM8))\r\n\r\n/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/\r\n#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \\\r\n                                          ((INSTANCE) == TIM2)   || \\\r\n                                          ((INSTANCE) == TIM3)   || \\\r\n                                          ((INSTANCE) == TIM4)   || \\\r\n                                          ((INSTANCE) == TIM5)   || \\\r\n                                          ((INSTANCE) == TIM8)   || \\\r\n                                          ((INSTANCE) == TIM15)  || \\\r\n                                          ((INSTANCE) == TIM16)  || \\\r\n                                          ((INSTANCE) == TIM17)  || \\\r\n                                          ((INSTANCE) == TIM23)  || \\\r\n                                          ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting commutation event *************/\r\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \\\r\n                                                     ((INSTANCE) == TIM8)    || \\\r\n                                                     ((INSTANCE) == TIM15)   || \\\r\n                                                     ((INSTANCE) == TIM16)   || \\\r\n                                                     ((INSTANCE) == TIM17))\r\n\r\n/****************** TIM Instances : supporting encoder interface **************/\r\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \\\r\n                                                      ((__INSTANCE__) == TIM2)      || \\\r\n                                                      ((__INSTANCE__) == TIM3)      || \\\r\n                                                      ((__INSTANCE__) == TIM4)      || \\\r\n                                                      ((__INSTANCE__) == TIM5)      || \\\r\n                                                      ((__INSTANCE__) == TIM8)      || \\\r\n                                                      ((__INSTANCE__) == TIM23)      || \\\r\n                                                      ((__INSTANCE__) == TIM24))\r\n\r\n/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/\r\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                                       ((INSTANCE) == TIM8))\r\n/******************* TIM Instances : output(s) available **********************/\r\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\r\n    ((((INSTANCE) == TIM1) &&                  \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\r\n     ||                                        \\\r\n     (((INSTANCE) == TIM2) &&                  \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM3) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1)||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM4) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM5) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM8) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM12) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM13) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM14) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM15) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n     ((CHANNEL) == TIM_CHANNEL_2)))            \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM16) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM17) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n     ||                                        \\\r\n     (((INSTANCE) == TIM23) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n     ||                                        \\\r\n     (((INSTANCE) == TIM24) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4))))\r\n\r\n/****************** TIM Instances : supporting the break function *************/\r\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)\\\r\n      (((INSTANCE) == TIM1)    || \\\r\n      ((INSTANCE) == TIM8)     || \\\r\n       ((INSTANCE) == TIM15)   || \\\r\n       ((INSTANCE) == TIM16)   || \\\r\n       ((INSTANCE) == TIM17))\r\n\r\n/************** TIM Instances : supporting Break source selection *************/\r\n#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\r\n                                               ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting complementary output(s) ********/\r\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\r\n   ((((INSTANCE) == TIM1) &&                    \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\r\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\r\n ||                                             \\\r\n      (((INSTANCE) == TIM8) &&                  \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\r\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\r\n    ||                                          \\\r\n    (((INSTANCE) == TIM15) &&                   \\\r\n      ((CHANNEL) == TIM_CHANNEL_1))             \\\r\n    ||                                          \\\r\n    (((INSTANCE) == TIM16) &&                   \\\r\n     ((CHANNEL) == TIM_CHANNEL_1))              \\\r\n    ||                                          \\\r\n    (((INSTANCE) == TIM17) &&                   \\\r\n     ((CHANNEL) == TIM_CHANNEL_1)))\r\n\r\n/****************** TIM Instances : supporting counting mode selection ********/\r\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting repetition counter *************/\r\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM16)   || \\\r\n   ((INSTANCE) == TIM17))\r\n\r\n/****************** TIM Instances : supporting synchronization ****************/\r\n#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\\r\n    (((__INSTANCE__) == TIM1)    || \\\r\n     ((__INSTANCE__) == TIM2)    || \\\r\n     ((__INSTANCE__) == TIM3)    || \\\r\n     ((__INSTANCE__) == TIM4)    || \\\r\n     ((__INSTANCE__) == TIM5)    || \\\r\n     ((__INSTANCE__) == TIM6)    || \\\r\n     ((__INSTANCE__) == TIM8)    || \\\r\n     ((__INSTANCE__) == TIM12)   || \\\r\n     ((__INSTANCE__) == TIM15)   || \\\r\n     ((__INSTANCE__) == TIM23)   || \\\r\n     ((__INSTANCE__) == TIM24))\r\n\r\n/****************** TIM Instances : supporting clock division *****************/\r\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM16)   || \\\r\n   ((INSTANCE) == TIM17)   || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting external clock mode 1 for ETRF input */\r\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting external clock mode 2 **********/\r\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\\\r\n (((INSTANCE) == TIM1)     || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting OCxREF clear *******************/\r\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3))\r\n\r\n/****************** TIM Instances : TIM_32B_COUNTER ***************************/\r\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : TIM_BKIN2 ***************************/\r\n#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting Hall sensor interface **********/\r\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \\\r\n                                                             ((__INSTANCE__) == TIM2)  || \\\r\n                                                             ((__INSTANCE__) == TIM3)  || \\\r\n                                                             ((__INSTANCE__) == TIM4)  || \\\r\n                                                             ((__INSTANCE__) == TIM5)  || \\\r\n                                                             ((__INSTANCE__) == TIM15) || \\\r\n                                                             ((__INSTANCE__) == TIM8)  || \\\r\n                                                             ((__INSTANCE__) == TIM23) || \\\r\n                                                             ((__INSTANCE__) == TIM24))\r\n\r\n/******************** USART Instances : Synchronous mode **********************/\r\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                     ((INSTANCE) == USART2) || \\\r\n                                     ((INSTANCE) == USART3) || \\\r\n                                     ((INSTANCE) == USART6) || \\\r\n                                     ((INSTANCE) == USART10))\r\n\r\n/******************** USART Instances : SPI slave mode ************************/\r\n#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                              ((INSTANCE) == USART2) || \\\r\n                                              ((INSTANCE) == USART3) || \\\r\n                                              ((INSTANCE) == USART6) || \\\r\n                                              ((INSTANCE) == USART10))\r\n\r\n/******************** UART Instances : Asynchronous mode **********************/\r\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                    ((INSTANCE) == USART2) || \\\r\n                                    ((INSTANCE) == USART3) || \\\r\n                                    ((INSTANCE) == UART4)  || \\\r\n                                    ((INSTANCE) == UART5)  || \\\r\n                                    ((INSTANCE) == USART6) || \\\r\n                                    ((INSTANCE) == UART7)  || \\\r\n                                    ((INSTANCE) == UART8)  || \\\r\n                                    ((INSTANCE) == UART9)  || \\\r\n                                    ((INSTANCE) == USART10))\r\n\r\n/******************** UART Instances : FIFO mode.******************************/\r\n#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                         ((INSTANCE) == USART2) || \\\r\n                                         ((INSTANCE) == USART3) || \\\r\n                                         ((INSTANCE) == UART4)  || \\\r\n                                         ((INSTANCE) == UART5)  || \\\r\n                                         ((INSTANCE) == USART6) || \\\r\n                                         ((INSTANCE) == UART7)  || \\\r\n                                         ((INSTANCE) == UART8)  || \\\r\n                                         ((INSTANCE) == UART9)  || \\\r\n                                         ((INSTANCE) == USART10)|| \\\r\n                                         ((INSTANCE) == LPUART1))\r\n\r\n/****************** UART Instances : Auto Baud Rate detection *****************/\r\n#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                                            ((INSTANCE) == USART2) || \\\r\n                                                            ((INSTANCE) == USART3) || \\\r\n                                                            ((INSTANCE) == UART4)  || \\\r\n                                                            ((INSTANCE) == UART5)  || \\\r\n                                                            ((INSTANCE) == USART6) || \\\r\n                                                            ((INSTANCE) == UART7)  || \\\r\n                                                            ((INSTANCE) == UART8)  || \\\r\n                                                            ((INSTANCE) == UART9)  || \\\r\n                                                            ((INSTANCE) == USART10))\r\n\r\n/*********************** UART Instances : Driver Enable ***********************/\r\n#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                                  ((INSTANCE) == USART2) || \\\r\n                                                  ((INSTANCE) == USART3) || \\\r\n                                                  ((INSTANCE) == UART4)  || \\\r\n                                                  ((INSTANCE) == UART5)  || \\\r\n                                                  ((INSTANCE) == USART6) || \\\r\n                                                  ((INSTANCE) == UART7)  || \\\r\n                                                  ((INSTANCE) == UART8)  || \\\r\n                                                  ((INSTANCE) == UART9)  || \\\r\n                                                  ((INSTANCE) == USART10)|| \\\r\n                                                  ((INSTANCE) == LPUART1))\r\n\r\n/********************* UART Instances : Half-Duplex mode **********************/\r\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                               ((INSTANCE) == USART2) || \\\r\n                                               ((INSTANCE) == USART3) || \\\r\n                                               ((INSTANCE) == UART4)  || \\\r\n                                               ((INSTANCE) == UART5)  || \\\r\n                                               ((INSTANCE) == USART6) || \\\r\n                                               ((INSTANCE) == UART7)  || \\\r\n                                               ((INSTANCE) == UART8)  || \\\r\n                                               ((INSTANCE) == UART9)  || \\\r\n                                               ((INSTANCE) == USART10)|| \\\r\n                                               ((INSTANCE) == LPUART1))\r\n\r\n/******************* UART Instances : Hardware Flow control *******************/\r\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                           ((INSTANCE) == USART2) || \\\r\n                                           ((INSTANCE) == USART3) || \\\r\n                                           ((INSTANCE) == UART4)  || \\\r\n                                           ((INSTANCE) == UART5)  || \\\r\n                                           ((INSTANCE) == USART6) || \\\r\n                                           ((INSTANCE) == UART7)  || \\\r\n                                           ((INSTANCE) == UART8)  || \\\r\n                                           ((INSTANCE) == UART9)  || \\\r\n                                           ((INSTANCE) == USART10)|| \\\r\n                                           ((INSTANCE) == LPUART1))\r\n\r\n/************************* UART Instances : LIN mode **************************/\r\n#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                        ((INSTANCE) == USART2) || \\\r\n                                        ((INSTANCE) == USART3) || \\\r\n                                        ((INSTANCE) == UART4)  || \\\r\n                                        ((INSTANCE) == UART5)  || \\\r\n                                        ((INSTANCE) == USART6) || \\\r\n                                        ((INSTANCE) == UART7)  || \\\r\n                                        ((INSTANCE) == UART8)  || \\\r\n                                        ((INSTANCE) == UART9)  || \\\r\n                                        ((INSTANCE) == USART10))\r\n\r\n/****************** UART Instances : Wake-up from Stop mode *******************/\r\n#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                                    ((INSTANCE) == USART2) || \\\r\n                                                    ((INSTANCE) == USART3) || \\\r\n                                                    ((INSTANCE) == UART4)  || \\\r\n                                                    ((INSTANCE) == UART5)  || \\\r\n                                                    ((INSTANCE) == USART6) || \\\r\n                                                    ((INSTANCE) == UART7)  || \\\r\n                                                    ((INSTANCE) == UART8)  || \\\r\n                                                    ((INSTANCE) == UART9)  || \\\r\n                                                    ((INSTANCE) == USART10)|| \\\r\n                                                    ((INSTANCE) == LPUART1))\r\n\r\n/************************* UART Instances : IRDA mode *************************/\r\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                    ((INSTANCE) == USART2) || \\\r\n                                    ((INSTANCE) == USART3) || \\\r\n                                    ((INSTANCE) == UART4)  || \\\r\n                                    ((INSTANCE) == UART5)  || \\\r\n                                    ((INSTANCE) == USART6) || \\\r\n                                    ((INSTANCE) == UART7)  || \\\r\n                                    ((INSTANCE) == UART8)  || \\\r\n                                    ((INSTANCE) == UART9)  || \\\r\n                                    ((INSTANCE) == USART10))\r\n\r\n/********************* USART Instances : Smard card mode **********************/\r\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                         ((INSTANCE) == USART2) || \\\r\n                                         ((INSTANCE) == USART3) || \\\r\n                                         ((INSTANCE) == USART6) ||\\\r\n                                         ((INSTANCE) == USART10))\r\n\r\n/****************************** LPUART Instance *******************************/\r\n#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)\r\n\r\n/****************************** IWDG Instances ********************************/\r\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)\r\n/****************************** USB Instances ********************************/\r\n#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\r\n\r\n/****************************** WWDG Instances ********************************/\r\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)\r\n/****************************** MDIOS Instances ********************************/\r\n#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)\r\n\r\n/****************************** CEC Instances *********************************/\r\n#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r\n\r\n/****************************** SAI Instances ********************************/\r\n#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\\r\n                                       ((INSTANCE) == SAI1_Block_B) || \\\r\n                                       ((INSTANCE) == SAI4_Block_A) || \\\r\n                                       ((INSTANCE) == SAI4_Block_B))\r\n\r\n/****************************** SPDIFRX Instances ********************************/\r\n#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)\r\n\r\n/****************************** OPAMP Instances *******************************/\r\n#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\\r\n                                         ((INSTANCE) == OPAMP2))\r\n\r\n#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\r\n\r\n/*********************** USB OTG PCD Instances ********************************/\r\n#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)\r\n\r\n/*********************** USB OTG HCD Instances ********************************/\r\n#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)\r\n\r\n/******************************************************************************/\r\n/*  For a painless codes migration between the STM32H7xx device product       */\r\n/*  lines, or with STM32F7xx devices the aliases defined below are put        */\r\n/*   in place to overcome the differences in the interrupt handlers and IRQn  */\r\n/*   definitions. No need to update developed interrupt code when moving      */\r\n/*  across product lines within the same STM32H7 Family                       */\r\n/******************************************************************************/\r\n\r\n/* Aliases for __IRQn */\r\n//#define  HASH_RNG_IRQn                  RNG_IRQn\r\n//#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn\r\n#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn\r\n//#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn\r\n//#define  PVD_IRQn                       PVD_AVD_IRQn\r\n\r\n\r\n/* Aliases for DCMI/PSSI __IRQn */\r\n#define  DCMI_IRQn                      DCMI_PSSI_IRQn\r\n\r\n/* Aliases for __IRQHandler */\r\n//#define  HASH_RNG_IRQHandler           RNG_IRQHandler\r\n//#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler\r\n#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler\r\n//#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler\r\n//#define PVD_IRQHandler                 PVD_AVD_IRQHandler\r\n\r\n/* Aliases for COMP __IRQHandler */\r\n#define COMP_IRQHandler                COMP1_IRQHandler\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* STM32H735xx_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/stm32h735xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32h735xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS STM32H735xx Device Peripheral Access Layer Header File.\r\n  *\r\n  *          This file contains:\r\n  *           - Data structures and the address mapping for all peripherals\r\n  *           - Peripheral's registers declarations and bits definition\r\n  *           - Macros to access peripheral's registers hardware\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS_Device\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32h735xx\r\n  * @{\r\n  */\r\n\r\n#ifndef STM32H735xx_H\r\n#define STM32H735xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n\r\n/** @addtogroup Peripheral_interrupt_number_definition\r\n  * @{\r\n  */\r\n\r\n/**\r\n * @brief STM32H7XX Interrupt Number Definition, according to the selected device\r\n *        in @ref Library_configuration_section\r\n */\r\ntypedef enum\r\n{\r\n/******  Cortex-M Processor Exceptions Numbers *****************************************************************/\r\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\r\n  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */\r\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */\r\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */\r\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */\r\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */\r\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */\r\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */\r\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */\r\n/******  STM32 specific Interrupt Numbers **********************************************************************/\r\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */\r\n  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */\r\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\r\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\r\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\r\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\r\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\r\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\r\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\r\n  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */\r\n  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */\r\n  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */\r\n  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */\r\n  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */\r\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */\r\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */\r\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */\r\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\r\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\r\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\r\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\r\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r\n  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\r\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r\n  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */\r\n  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */\r\n  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */\r\n  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */\r\n  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */\r\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\r\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\r\n  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */\r\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\r\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\r\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\r\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\r\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\r\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\r\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\r\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\r\n  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */\r\n  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */\r\n  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */\r\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\r\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\r\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\r\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\r\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\r\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\r\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\r\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */\r\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */\r\n  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */\r\n  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */\r\n  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */\r\n  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */\r\n  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */\r\n  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */\r\n  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */\r\n  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */\r\n  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */\r\n  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */\r\n  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */\r\n  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */\r\n  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */\r\n  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */\r\n  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */\r\n  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */\r\n  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */\r\n  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */\r\n  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */\r\n  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */\r\n  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */\r\n  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */\r\n  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */\r\n  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */\r\n  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */\r\n  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */\r\n  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */\r\n  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */\r\n  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */\r\n  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */\r\n  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */\r\n  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */\r\n  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */\r\n  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */\r\n  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */\r\n  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */\r\n  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */\r\n  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */\r\n  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */\r\n  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */\r\n  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */\r\n  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */\r\n  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */\r\n  OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */\r\n  OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */\r\n  FMAC_IRQn                   = 153,    /*!< FMAC global interrupt                                             */\r\n  CORDIC_IRQn                 = 154,    /*!< CORDIC global interrupt                                           */\r\n  UART9_IRQn                  = 155,    /*!< UART9 global Interrupt                                            */\r\n  USART10_IRQn                = 156,    /*!< USART10 global interrupt                                          */\r\n  I2C5_EV_IRQn                = 157,    /*!< I2C5 event interrupt                                              */\r\n  I2C5_ER_IRQn                = 158,    /*!< I2C5 error interrupt                                              */\r\n  FDCAN3_IT0_IRQn             = 159,    /*!< FDCAN3 Interrupt line 0                                           */\r\n  FDCAN3_IT1_IRQn             = 160,    /*!< FDCAN3 Interrupt line 1                                           */\r\n  TIM23_IRQn                  = 161,    /*!< TIM23 global interrupt                                            */\r\n  TIM24_IRQn                  = 162,    /*!< TIM24 global interrupt                                            */\r\n} IRQn_Type;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Configuration_section_for_CMSIS\r\n  * @{\r\n  */\r\n\r\n#define SMPS       /*!< Switched mode power supply feature */\r\n\r\n\r\n\r\n/**\r\n  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals\r\n   */\r\n#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */\r\n#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */\r\n#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */\r\n#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r\n#define __FPU_PRESENT             1       /*!< FPU present                                   */\r\n#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */\r\n#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */\r\n#include \"core_cm7.h\"                     /*!< Cortex-M7 processor and core peripherals      */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n\r\n#include \"system_stm32h7xx.h\"\r\n#include <stdint.h>\r\n\r\n/** @addtogroup Peripheral_registers_structures\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Analog to Digital Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */\r\n  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */\r\n  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */\r\n  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */\r\n  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */\r\n  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */\r\n  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */\r\n  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */\r\n  __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */\r\n  __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */\r\n  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */\r\n  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */\r\n  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */\r\n  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */\r\n  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */\r\n  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */\r\n  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */\r\n  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */\r\n  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */\r\n  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */\r\n  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */\r\n  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */\r\n  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */\r\n  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */\r\n  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */\r\n  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */\r\n  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */\r\n  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */\r\n  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */\r\n  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */\r\n  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */\r\n  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */\r\n  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */\r\n  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */\r\n  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */\r\n  __IO uint32_t LTR2_DIFSEL;      /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3,   Address offset: 0xB0 */\r\n  __IO uint32_t HTR2_CALFACT;     /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */\r\n  __IO uint32_t LTR3_RES10;       /*!< ADC watchdog Lower threshold register 3, specific ADC1/2,   Address offset: 0xB8 */\r\n  __IO uint32_t HTR3_RES11;       /*!< ADC watchdog Higher threshold register 3, specific ADC1/2,  Address offset: 0xBC */\r\n  __IO uint32_t DIFSEL_RES12;     /*!< ADC Differential Mode Selection Register specific ADC1/2,   Address offset: 0xC0 */\r\n  __IO uint32_t CALFACT_RES13;    /*!< ADC Calibration Factors specific ADC1/2,                    Address offset: 0xC4 */\r\n  __IO uint32_t CALFACT2_RES14;   /*!< ADC Linearity Calibration Factors specific ADC1/2,          Address offset: 0xC8 */\r\n} ADC_TypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */\r\nuint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */\r\n__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */\r\n__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */\r\n__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */\r\n\r\n} ADC_Common_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief VREFBUF\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */\r\n  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */\r\n} VREFBUF_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief FD Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */\r\n  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */\r\n  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */\r\n  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */\r\n  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */\r\n  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */\r\n  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */\r\n  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */\r\n  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */\r\n  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */\r\n  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */\r\n  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */\r\n  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */\r\n  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */\r\n  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */\r\n  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */\r\n  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */\r\n  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */\r\n  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */\r\n  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */\r\n  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */\r\n  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */\r\n  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */\r\n  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */\r\n  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */\r\n  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */\r\n  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */\r\n  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */\r\n  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */\r\n  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */\r\n  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */\r\n  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */\r\n  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */\r\n  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */\r\n  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */\r\n  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */\r\n  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */\r\n  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */\r\n  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */\r\n  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */\r\n  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */\r\n  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */\r\n  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */\r\n  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */\r\n  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */\r\n  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */\r\n  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */\r\n  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */\r\n  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */\r\n  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */\r\n  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */\r\n  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */\r\n  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */\r\n} FDCAN_GlobalTypeDef;\r\n\r\n/**\r\n  * @brief TTFD Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */\r\n  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */\r\n  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */\r\n  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */\r\n  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */\r\n  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */\r\n  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */\r\n  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */\r\n  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */\r\n  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */\r\n  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */\r\n  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */\r\n  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */\r\n  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */\r\n  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */\r\n  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */\r\n  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */\r\n  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */\r\n  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */\r\n} TTCAN_TypeDef;\r\n\r\n/**\r\n  * @brief FD Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */\r\n  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */\r\n  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */\r\n  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */\r\n  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */\r\n  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */\r\n} FDCAN_ClockCalibrationUnit_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Consumer Electronics Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */\r\n  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */\r\n  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */\r\n  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */\r\n  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r\n  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */\r\n}CEC_TypeDef;\r\n\r\n/**\r\n  * @brief COordincate Rotation DIgital Computer\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */\r\n  __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */\r\n  __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */\r\n} CORDIC_TypeDef;\r\n\r\n/**\r\n  * @brief CRC calculation unit\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\r\n  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\r\n  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\r\n  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\r\n  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\r\n  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\r\n} CRC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Clock Recovery System\r\n  */\r\ntypedef struct\r\n{\r\n__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */\r\n__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */\r\n__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */\r\n__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */\r\n} CRS_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Digital to Analog Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\r\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\r\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\r\n  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */\r\n  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */\r\n  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */\r\n  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */\r\n  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */\r\n  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */\r\n} DAC_TypeDef;\r\n\r\n/**\r\n  * @brief DFSDM module registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */\r\n  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */\r\n  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\r\n  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\r\n  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\r\n  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */\r\n  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */\r\n  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */\r\n  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\r\n  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\r\n  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\r\n  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\r\n  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\r\n  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\r\n  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */\r\n} DFSDM_Filter_TypeDef;\r\n\r\n/**\r\n  * @brief DFSDM channel configuration registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\r\n  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\r\n  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and\r\n                                   short circuit detector register,                  Address offset: 0x08 */\r\n  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\r\n  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */\r\n} DFSDM_Channel_TypeDef;\r\n\r\n/**\r\n  * @brief Debug MCU\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */\r\n  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */\r\n  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */\r\n  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */\r\n  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */\r\n  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */\r\n  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */\r\n  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */\r\n  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */\r\n  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */\r\n  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */\r\n  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */\r\n  __IO uint32_t RESERVED9[990]; /*!< Reserved,                         Address offset: 0x58-0xFCC */\r\n  __IO uint32_t PIDR4;       /*!< Debug MCU peripheral identity register 4,  Address offset: 0xFD0 */\r\n  __IO uint32_t RESERVED10[3];/*!< Reserved,                            Address offset: 0xFD4-0xFDC */\r\n  __IO uint32_t PIDR0;       /*!< Debug MCU peripheral identity register 0,  Address offset: 0xFE0 */\r\n  __IO uint32_t PIDR1;       /*!< Debug MCU peripheral identity register 1,  Address offset: 0xFE4 */\r\n  __IO uint32_t PIDR2;       /*!< Debug MCU peripheral identity register 2,  Address offset: 0xFE8 */\r\n  __IO uint32_t PIDR3;       /*!< Debug MCU peripheral identity register 3,  Address offset: 0xFEC */\r\n  __IO uint32_t CIDR0;       /*!< Debug MCU component identity register 0,   Address offset: 0xFF0 */\r\n  __IO uint32_t CIDR1;       /*!< Debug MCU component identity register 1,   Address offset: 0xFF4 */\r\n  __IO uint32_t CIDR2;       /*!< Debug MCU component identity register 2,   Address offset: 0xFF8 */\r\n  __IO uint32_t CIDR3;       /*!< Debug MCU component identity register 3,   Address offset: 0xFFC */\r\n}DBGMCU_TypeDef;\r\n/**\r\n  * @brief DCMI\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\r\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\r\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\r\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\r\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\r\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\r\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\r\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\r\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\r\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\r\n} DCMI_TypeDef;\r\n\r\n/**\r\n  * @brief PSSI\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */\r\n  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */\r\n  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */\r\n  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */\r\n  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */\r\n  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */\r\n  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */\r\n  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */\r\n  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */\r\n  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */\r\n  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */\r\n  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */\r\n  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */\r\n} PSSI_TypeDef;\r\n\r\n/**\r\n  * @brief DMA Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\r\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\r\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\r\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\r\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\r\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\r\n} DMA_Stream_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\r\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\r\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\r\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r\n} DMA_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */\r\n  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */\r\n  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */\r\n  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */\r\n  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */\r\n} BDMA_Channel_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */\r\n  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */\r\n} BDMA_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */\r\n}DMAMUX_Channel_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */\r\n  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */\r\n}DMAMUX_ChannelStatus_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */\r\n}DMAMUX_RequestGen_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */\r\n  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */\r\n}DMAMUX_RequestGenStatus_TypeDef;\r\n\r\n/**\r\n  * @brief MDMA Controller\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */\r\n}MDMA_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */\r\n  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */\r\n  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */\r\n  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */\r\n  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */\r\n  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */\r\n  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */\r\n  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */\r\n  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */\r\n  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */\r\n  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */\r\n  uint32_t       RESERVED0; /*!< Reserved, 0x6C                                                             */\r\n  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */\r\n  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */\r\n}MDMA_Channel_TypeDef;\r\n\r\n/**\r\n  * @brief DMA2D Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\r\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\r\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\r\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\r\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\r\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\r\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\r\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\r\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\r\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\r\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\r\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\r\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\r\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\r\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\r\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\r\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\r\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\r\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\r\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\r\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\r\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\r\n} DMA2D_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Ethernet MAC\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t MACCR;\r\n  __IO uint32_t MACECR;\r\n  __IO uint32_t MACPFR;\r\n  __IO uint32_t MACWTR;\r\n  __IO uint32_t MACHT0R;\r\n  __IO uint32_t MACHT1R;\r\n  uint32_t      RESERVED1[14];\r\n  __IO uint32_t MACVTR;\r\n  uint32_t      RESERVED2;\r\n  __IO uint32_t MACVHTR;\r\n  uint32_t      RESERVED3;\r\n  __IO uint32_t MACVIR;\r\n  __IO uint32_t MACIVIR;\r\n  uint32_t      RESERVED4[2];\r\n  __IO uint32_t MACTFCR;\r\n  uint32_t      RESERVED5[7];\r\n  __IO uint32_t MACRFCR;\r\n  uint32_t      RESERVED6[7];\r\n  __IO uint32_t MACISR;\r\n  __IO uint32_t MACIER;\r\n  __IO uint32_t MACRXTXSR;\r\n  uint32_t      RESERVED7;\r\n  __IO uint32_t MACPCSR;\r\n  __IO uint32_t MACRWKPFR;\r\n  uint32_t      RESERVED8[2];\r\n  __IO uint32_t MACLCSR;\r\n  __IO uint32_t MACLTCR;\r\n  __IO uint32_t MACLETR;\r\n  __IO uint32_t MAC1USTCR;\r\n  uint32_t      RESERVED9[12];\r\n  __IO uint32_t MACVR;\r\n  __IO uint32_t MACDR;\r\n  uint32_t      RESERVED10;\r\n  __IO uint32_t MACHWF0R;\r\n  __IO uint32_t MACHWF1R;\r\n  __IO uint32_t MACHWF2R;\r\n  uint32_t      RESERVED11[54];\r\n  __IO uint32_t MACMDIOAR;\r\n  __IO uint32_t MACMDIODR;\r\n  uint32_t      RESERVED12[2];\r\n  __IO uint32_t MACARPAR;\r\n  uint32_t      RESERVED13[59];\r\n  __IO uint32_t MACA0HR;\r\n  __IO uint32_t MACA0LR;\r\n  __IO uint32_t MACA1HR;\r\n  __IO uint32_t MACA1LR;\r\n  __IO uint32_t MACA2HR;\r\n  __IO uint32_t MACA2LR;\r\n  __IO uint32_t MACA3HR;\r\n  __IO uint32_t MACA3LR;\r\n  uint32_t      RESERVED14[248];\r\n  __IO uint32_t MMCCR;\r\n  __IO uint32_t MMCRIR;\r\n  __IO uint32_t MMCTIR;\r\n  __IO uint32_t MMCRIMR;\r\n  __IO uint32_t MMCTIMR;\r\n  uint32_t      RESERVED15[14];\r\n  __IO uint32_t MMCTSCGPR;\r\n  __IO uint32_t MMCTMCGPR;\r\n  uint32_t      RESERVED16[5];\r\n  __IO uint32_t MMCTPCGR;\r\n  uint32_t      RESERVED17[10];\r\n  __IO uint32_t MMCRCRCEPR;\r\n  __IO uint32_t MMCRAEPR;\r\n  uint32_t      RESERVED18[10];\r\n  __IO uint32_t MMCRUPGR;\r\n  uint32_t      RESERVED19[9];\r\n  __IO uint32_t MMCTLPIMSTR;\r\n  __IO uint32_t MMCTLPITCR;\r\n  __IO uint32_t MMCRLPIMSTR;\r\n  __IO uint32_t MMCRLPITCR;\r\n  uint32_t      RESERVED20[65];\r\n  __IO uint32_t MACL3L4C0R;\r\n  __IO uint32_t MACL4A0R;\r\n  uint32_t      RESERVED21[2];\r\n  __IO uint32_t MACL3A0R0R;\r\n  __IO uint32_t MACL3A1R0R;\r\n  __IO uint32_t MACL3A2R0R;\r\n  __IO uint32_t MACL3A3R0R;\r\n  uint32_t      RESERVED22[4];\r\n  __IO uint32_t MACL3L4C1R;\r\n  __IO uint32_t MACL4A1R;\r\n  uint32_t      RESERVED23[2];\r\n  __IO uint32_t MACL3A0R1R;\r\n  __IO uint32_t MACL3A1R1R;\r\n  __IO uint32_t MACL3A2R1R;\r\n  __IO uint32_t MACL3A3R1R;\r\n  uint32_t      RESERVED24[108];\r\n  __IO uint32_t MACTSCR;\r\n  __IO uint32_t MACSSIR;\r\n  __IO uint32_t MACSTSR;\r\n  __IO uint32_t MACSTNR;\r\n  __IO uint32_t MACSTSUR;\r\n  __IO uint32_t MACSTNUR;\r\n  __IO uint32_t MACTSAR;\r\n  uint32_t      RESERVED25;\r\n  __IO uint32_t MACTSSR;\r\n  uint32_t      RESERVED26[3];\r\n  __IO uint32_t MACTTSSNR;\r\n  __IO uint32_t MACTTSSSR;\r\n  uint32_t      RESERVED27[2];\r\n  __IO uint32_t MACACR;\r\n  uint32_t      RESERVED28;\r\n  __IO uint32_t MACATSNR;\r\n  __IO uint32_t MACATSSR;\r\n  __IO uint32_t MACTSIACR;\r\n  __IO uint32_t MACTSEACR;\r\n  __IO uint32_t MACTSICNR;\r\n  __IO uint32_t MACTSECNR;\r\n  uint32_t      RESERVED29[4];\r\n  __IO uint32_t MACPPSCR;\r\n  uint32_t      RESERVED30[3];\r\n  __IO uint32_t MACPPSTTSR;\r\n  __IO uint32_t MACPPSTTNR;\r\n  __IO uint32_t MACPPSIR;\r\n  __IO uint32_t MACPPSWR;\r\n  uint32_t      RESERVED31[12];\r\n  __IO uint32_t MACPOCR;\r\n  __IO uint32_t MACSPI0R;\r\n  __IO uint32_t MACSPI1R;\r\n  __IO uint32_t MACSPI2R;\r\n  __IO uint32_t MACLMIR;\r\n  uint32_t      RESERVED32[11];\r\n  __IO uint32_t MTLOMR;\r\n  uint32_t      RESERVED33[7];\r\n  __IO uint32_t MTLISR;\r\n  uint32_t      RESERVED34[55];\r\n  __IO uint32_t MTLTQOMR;\r\n  __IO uint32_t MTLTQUR;\r\n  __IO uint32_t MTLTQDR;\r\n  uint32_t      RESERVED35[8];\r\n  __IO uint32_t MTLQICSR;\r\n  __IO uint32_t MTLRQOMR;\r\n  __IO uint32_t MTLRQMPOCR;\r\n  __IO uint32_t MTLRQDR;\r\n  uint32_t      RESERVED36[177];\r\n  __IO uint32_t DMAMR;\r\n  __IO uint32_t DMASBMR;\r\n  __IO uint32_t DMAISR;\r\n  __IO uint32_t DMADSR;\r\n  uint32_t      RESERVED37[60];\r\n  __IO uint32_t DMACCR;\r\n  __IO uint32_t DMACTCR;\r\n  __IO uint32_t DMACRCR;\r\n  uint32_t      RESERVED38[2];\r\n  __IO uint32_t DMACTDLAR;\r\n  uint32_t      RESERVED39;\r\n  __IO uint32_t DMACRDLAR;\r\n  __IO uint32_t DMACTDTPR;\r\n  uint32_t      RESERVED40;\r\n  __IO uint32_t DMACRDTPR;\r\n  __IO uint32_t DMACTDRLR;\r\n  __IO uint32_t DMACRDRLR;\r\n  __IO uint32_t DMACIER;\r\n  __IO uint32_t DMACRIWTR;\r\n__IO uint32_t DMACSFCSR;\r\n  uint32_t      RESERVED41;\r\n  __IO uint32_t DMACCATDR;\r\n  uint32_t      RESERVED42;\r\n  __IO uint32_t DMACCARDR;\r\n  uint32_t      RESERVED43;\r\n  __IO uint32_t DMACCATBR;\r\n  uint32_t      RESERVED44;\r\n  __IO uint32_t DMACCARBR;\r\n  __IO uint32_t DMACSR;\r\nuint32_t      RESERVED45[2];\r\n__IO uint32_t DMACMFCR;\r\n}ETH_TypeDef;\r\n/**\r\n  * @brief External Interrupt/Event Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */\r\n__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */\r\n__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */\r\n__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */\r\n__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */\r\n__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */\r\nuint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */\r\n__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */\r\n__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */\r\n__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */\r\n__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */\r\n__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */\r\n__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */\r\nuint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */\r\n__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */\r\n__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */\r\n__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */\r\n__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */\r\n__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */\r\n__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */\r\nuint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */\r\n__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */\r\n__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */\r\n__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */\r\nuint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */\r\n__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */\r\n__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */\r\n__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */\r\nuint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */\r\n__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */\r\n__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */\r\n__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */\r\n}EXTI_TypeDef;\r\n\r\n/**\r\n  * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2\r\n  *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.\r\n  *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:\r\n  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)\r\n  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)\r\n  *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only\r\n  */\r\n\r\ntypedef struct\r\n{\r\n__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */\r\n__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */\r\n__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */\r\nuint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */\r\n__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */\r\n__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */\r\n__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */\r\nuint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */\r\n__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */\r\n__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */\r\n__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */\r\n}EXTI_Core_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief FLASH Registers\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */\r\n  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */\r\n  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */\r\n  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */\r\n  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */\r\n  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */\r\n  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */\r\n  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */\r\n  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */\r\n  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */\r\n  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */\r\n  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */\r\n  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */\r\n  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */\r\n  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */\r\n  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */\r\n  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */\r\n  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */\r\n  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */\r\n  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */\r\n  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */\r\n  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */\r\n  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */\r\n  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */\r\n  uint32_t      RESERVED[3];     /*!< Reserved, 0x64 to 0x6C                                                          */\r\n  __IO uint32_t OPTSR2_CUR;      /*!< Flash Option Status Current Register 2,                   Address offset: 0x70  */\r\n  __IO uint32_t OPTSR2_PRG;      /*!< Flash Option Status to Program Register 2,                Address offset: 0x74  */\r\n} FLASH_TypeDef;\r\n\r\n/**\r\n  * @brief Filter and Mathematical ACcelerator\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */\r\n  __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */\r\n  __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */\r\n  __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */\r\n  __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */\r\n  __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */\r\n  __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */\r\n  __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */\r\n} FMAC_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r\n} FMC_Bank1_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank1E\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r\n} FMC_Bank1E_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank2\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\r\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\r\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\r\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\r\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\r\n} FMC_Bank2_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank3\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\r\n  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\r\n  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\r\n  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r\n  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */\r\n  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\r\n} FMC_Bank3_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank5 and 6\r\n  */\r\n\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\r\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\r\n  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */\r\n  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */\r\n  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */\r\n} FMC_Bank5_6_TypeDef;\r\n\r\n/**\r\n  * @brief General Purpose I/O\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\r\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\r\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\r\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\r\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\r\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */\r\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r\n} GPIO_TypeDef;\r\n\r\n/**\r\n  * @brief Operational Amplifier (OPAMP)\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */\r\n  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */\r\n  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */\r\n} OPAMP_TypeDef;\r\n\r\n/**\r\n  * @brief System configuration controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */\r\n __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */\r\n __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */\r\n __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */\r\n uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */\r\n __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */\r\n __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */\r\n __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */\r\n uint32_t     RESERVED3;       /*!< Reserved,                                           Address offset: 0x2C        */\r\n __IO uint32_t ADC2ALT;        /*!< ADC2 internal input alternate connection register,  Address offset: 0x30        */\r\n uint32_t     RESERVED4[60];   /*!< Reserved, 0x34-0x120                                                            */\r\n  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */\r\n  uint32_t     RESERVED5[118]; /*!< Reserved, 0x128-0x2FC                                                           */\r\n __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */\r\n __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */\r\n __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */\r\n __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */\r\n __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */\r\n __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */\r\n __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */\r\n __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */\r\n uint32_t     RESERVED6[3];    /*!< Reserved,                                           Address offset: 0x320-0x328 */\r\n __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */\r\n __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */\r\n __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */\r\n __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */\r\n __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */\r\n __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */\r\n __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */\r\n __IO uint32_t UR18;           /*!< SYSCFG user register 18,                            Address offset: 0x348       */\r\n\r\n} SYSCFG_TypeDef;\r\n\r\n/**\r\n  * @brief Inter-integrated Circuit Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */\r\n  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */\r\n  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */\r\n  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */\r\n  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */\r\n  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */\r\n  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */\r\n  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */\r\n  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */\r\n  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */\r\n  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */\r\n} I2C_TypeDef;\r\n\r\n/**\r\n  * @brief Independent WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\r\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\r\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\r\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\r\n  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */\r\n} IWDG_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief LCD-TFT Display Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */\r\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\r\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\r\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\r\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\r\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\r\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */\r\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\r\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */\r\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\r\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */\r\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\r\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\r\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\r\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\r\n  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */\r\n} LTDC_TypeDef;\r\n\r\n/**\r\n  * @brief LCD-TFT Display layer x Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\r\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\r\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\r\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\r\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\r\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\r\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\r\n  uint32_t      RESERVED0[2];  /*!< Reserved */\r\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\r\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\r\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\r\n  uint32_t      RESERVED1[3];  /*!< Reserved */\r\n  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */\r\n\r\n} LTDC_Layer_TypeDef;\r\n\r\n/**\r\n  * @brief Power Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */\r\n  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */\r\n  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */\r\n  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */\r\n  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */\r\n       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */\r\n  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */\r\n       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */\r\n  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */\r\n  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */\r\n  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */\r\n} PWR_TypeDef;\r\n\r\n/**\r\n  * @brief Reset and Clock Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */\r\n __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */\r\n __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */\r\n __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */\r\n __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */\r\n uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */\r\n __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */\r\n __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */\r\n __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */\r\n uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */\r\n __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */\r\n __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */\r\n __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */\r\n __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */\r\n __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */\r\n __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */\r\n __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */\r\n __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */\r\n uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */\r\n __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */\r\n __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */\r\n __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */\r\n __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */\r\n uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */\r\n __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */\r\n __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */\r\n __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */\r\n uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */\r\n __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */\r\n __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */\r\n uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */\r\n __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */\r\n __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */\r\n __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */\r\n __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */\r\n __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */\r\n __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */\r\n __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */\r\n __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */\r\n __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */\r\n __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */\r\n uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */\r\n __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */\r\n uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */\r\n __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */\r\n __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */\r\n __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */\r\n __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */\r\n __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */\r\n __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */\r\n __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */\r\n __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */\r\n __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */\r\n __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */\r\n uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */\r\n __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */\r\n __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */\r\n __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */\r\n __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */\r\n __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */\r\n __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */\r\n __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */\r\n __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */\r\n __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */\r\n uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */\r\n\r\n} RCC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Real-Time Clock\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */\r\n  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */\r\n  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */\r\n  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */\r\n  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */\r\n  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\r\n       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */\r\n  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */\r\n  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */\r\n  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */\r\n  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */\r\n  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */\r\n  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */\r\n  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */\r\n  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\r\n  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */\r\n  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */\r\n  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\r\n  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\r\n  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */\r\n  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */\r\n  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */\r\n  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */\r\n  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */\r\n  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */\r\n  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */\r\n  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */\r\n  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */\r\n  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */\r\n  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */\r\n  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */\r\n  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */\r\n  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */\r\n  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */\r\n  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */\r\n  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */\r\n  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */\r\n  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */\r\n  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */\r\n  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */\r\n  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */\r\n  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */\r\n  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */\r\n  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */\r\n  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */\r\n  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */\r\n  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */\r\n  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */\r\n  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */\r\n  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */\r\n  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */\r\n  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */\r\n} RTC_TypeDef;\r\n\r\n/**\r\n  * @brief Serial Audio Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */\r\n  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */\r\n  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */\r\n  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */\r\n} SAI_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\r\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\r\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\r\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\r\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\r\n} SAI_Block_TypeDef;\r\n\r\n/**\r\n  * @brief SPDIF-RX Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */\r\n  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */\r\n  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */\r\n  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */\r\n  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */\r\n  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */\r\n  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */\r\n  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */\r\n} SPDIFRX_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Secure digital input/output Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */\r\n  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */\r\n  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */\r\n  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */\r\n  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */\r\n  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */\r\n  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */\r\n  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */\r\n  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */\r\n  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */\r\n  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */\r\n  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */\r\n  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */\r\n  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */\r\n  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */\r\n  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */\r\n  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */\r\n  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */\r\n  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */\r\n  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */\r\n  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */\r\n  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */\r\n  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */\r\n  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */\r\n  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */\r\n  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */\r\n} SDMMC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Delay Block DLYB\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */\r\n  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */\r\n} DLYB_TypeDef;\r\n\r\n/**\r\n  * @brief HW Semaphore HSEM\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */\r\n  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */\r\n  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */\r\n  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */\r\n  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */\r\n  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */\r\n  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */\r\n  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */\r\n  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */\r\n\r\n} HSEM_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */\r\n  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */\r\n  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */\r\n  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */\r\n} HSEM_Common_TypeDef;\r\n\r\n/**\r\n  * @brief Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */\r\n  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */\r\n  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */\r\n  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */\r\n  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */\r\n  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */\r\n  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */\r\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */\r\n  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */\r\n  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */\r\n  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */\r\n  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */\r\n  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */\r\n  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */\r\n  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */\r\n  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */\r\n  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */\r\n\r\n} SPI_TypeDef;\r\n\r\n/**\r\n  * @brief DTS\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */\r\n  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */\r\n  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */\r\n  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */\r\n  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */\r\n  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */\r\n  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */\r\n  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */\r\n  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */\r\n  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */\r\n  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */\r\n  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */\r\n}\r\nDTS_TypeDef;\r\n\r\n/**\r\n  * @brief TIM\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\r\n  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\r\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\r\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\r\n  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\r\n  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\r\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\r\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\r\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\r\n  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\r\n  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */\r\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\r\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\r\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\r\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\r\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\r\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\r\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\r\n  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\r\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\r\n  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */\r\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\r\n  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\r\n  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\r\n  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */\r\n  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */\r\n  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */\r\n} TIM_TypeDef;\r\n\r\n/**\r\n  * @brief LPTIMIMER\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */\r\n  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */\r\n  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */\r\n  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */\r\n  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */\r\n  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */\r\n  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */\r\n  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */\r\n  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */\r\n  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */\r\n} LPTIM_TypeDef;\r\n\r\n/**\r\n  * @brief Comparator\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */\r\n  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */\r\n  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */\r\n} COMPOPT_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */\r\n} COMP_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\r\n} COMP_Common_TypeDef;\r\n/**\r\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */\r\n  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */\r\n  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */\r\n  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */\r\n  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\r\n  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */\r\n  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */\r\n  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */\r\n  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\r\n  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */\r\n  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */\r\n  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */\r\n} USART_TypeDef;\r\n\r\n/**\r\n  * @brief Single Wire Protocol Master Interface SPWMI\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */\r\n  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */\r\n    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */\r\n  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */\r\n  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */\r\n  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */\r\n  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */\r\n  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */\r\n  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */\r\n  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */\r\n} SWPMI_TypeDef;\r\n\r\n/**\r\n  * @brief Window WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\r\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\r\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\r\n} WWDG_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief RAM_ECC_Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */\r\n  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */\r\n  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */\r\n  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */\r\n  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */\r\n  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */\r\n} RAMECC_MonitorTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */\r\n} RAMECC_TypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @brief Crypto Processor\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */\r\n  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */\r\n  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */\r\n  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */\r\n  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */\r\n  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */\r\n  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */\r\n  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */\r\n  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */\r\n  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */\r\n  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */\r\n  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */\r\n  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */\r\n  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */\r\n  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */\r\n  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */\r\n  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */\r\n  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */\r\n  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */\r\n  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */\r\n  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */\r\n  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */\r\n  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */\r\n  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */\r\n  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */\r\n  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */\r\n  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */\r\n  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */\r\n  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */\r\n  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */\r\n  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */\r\n  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */\r\n  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */\r\n  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */\r\n  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */\r\n  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */\r\n} CRYP_TypeDef;\r\n\r\n/**\r\n  * @brief HASH\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */\r\n  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */\r\n  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */\r\n  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */\r\n  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */\r\n  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */\r\n       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */\r\n  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */\r\n} HASH_TypeDef;\r\n\r\n/**\r\n  * @brief HASH_DIGEST\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */\r\n} HASH_DIGEST_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief RNG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r\n  uint32_t RESERVED;\r\n  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */\r\n} RNG_TypeDef;\r\n\r\n/**\r\n  * @brief MDIOS\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;\r\n  __IO uint32_t WRFR;\r\n  __IO uint32_t CWRFR;\r\n  __IO uint32_t RDFR;\r\n  __IO uint32_t CRDFR;\r\n  __IO uint32_t SR;\r\n  __IO uint32_t CLRFR;\r\n  uint32_t RESERVED[57];\r\n  __IO uint32_t DINR0;\r\n  __IO uint32_t DINR1;\r\n  __IO uint32_t DINR2;\r\n  __IO uint32_t DINR3;\r\n  __IO uint32_t DINR4;\r\n  __IO uint32_t DINR5;\r\n  __IO uint32_t DINR6;\r\n  __IO uint32_t DINR7;\r\n  __IO uint32_t DINR8;\r\n  __IO uint32_t DINR9;\r\n  __IO uint32_t DINR10;\r\n  __IO uint32_t DINR11;\r\n  __IO uint32_t DINR12;\r\n  __IO uint32_t DINR13;\r\n  __IO uint32_t DINR14;\r\n  __IO uint32_t DINR15;\r\n  __IO uint32_t DINR16;\r\n  __IO uint32_t DINR17;\r\n  __IO uint32_t DINR18;\r\n  __IO uint32_t DINR19;\r\n  __IO uint32_t DINR20;\r\n  __IO uint32_t DINR21;\r\n  __IO uint32_t DINR22;\r\n  __IO uint32_t DINR23;\r\n  __IO uint32_t DINR24;\r\n  __IO uint32_t DINR25;\r\n  __IO uint32_t DINR26;\r\n  __IO uint32_t DINR27;\r\n  __IO uint32_t DINR28;\r\n  __IO uint32_t DINR29;\r\n  __IO uint32_t DINR30;\r\n  __IO uint32_t DINR31;\r\n  __IO uint32_t DOUTR0;\r\n  __IO uint32_t DOUTR1;\r\n  __IO uint32_t DOUTR2;\r\n  __IO uint32_t DOUTR3;\r\n  __IO uint32_t DOUTR4;\r\n  __IO uint32_t DOUTR5;\r\n  __IO uint32_t DOUTR6;\r\n  __IO uint32_t DOUTR7;\r\n  __IO uint32_t DOUTR8;\r\n  __IO uint32_t DOUTR9;\r\n  __IO uint32_t DOUTR10;\r\n  __IO uint32_t DOUTR11;\r\n  __IO uint32_t DOUTR12;\r\n  __IO uint32_t DOUTR13;\r\n  __IO uint32_t DOUTR14;\r\n  __IO uint32_t DOUTR15;\r\n  __IO uint32_t DOUTR16;\r\n  __IO uint32_t DOUTR17;\r\n  __IO uint32_t DOUTR18;\r\n  __IO uint32_t DOUTR19;\r\n  __IO uint32_t DOUTR20;\r\n  __IO uint32_t DOUTR21;\r\n  __IO uint32_t DOUTR22;\r\n  __IO uint32_t DOUTR23;\r\n  __IO uint32_t DOUTR24;\r\n  __IO uint32_t DOUTR25;\r\n  __IO uint32_t DOUTR26;\r\n  __IO uint32_t DOUTR27;\r\n  __IO uint32_t DOUTR28;\r\n  __IO uint32_t DOUTR29;\r\n  __IO uint32_t DOUTR30;\r\n  __IO uint32_t DOUTR31;\r\n} MDIOS_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_Core_Registers\r\n  */\r\ntypedef struct\r\n{\r\n __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */\r\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\r\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\r\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\r\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\r\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\r\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\r\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\r\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\r\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\r\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\r\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\r\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\r\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\r\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\r\n  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/\r\n  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/\r\n  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/\r\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\r\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\r\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\r\n  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */\r\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\r\n   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */\r\n    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */\r\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\r\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */\r\n} USB_OTG_GlobalTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_device_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\r\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\r\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\r\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\r\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\r\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\r\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\r\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\r\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\r\n  uint32_t Reserved9;            /*!< Reserved                     824h */\r\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\r\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\r\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\r\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\r\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\r\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\r\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\r\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\r\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\r\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\r\n} USB_OTG_DeviceTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\r\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r\n} USB_OTG_INEndpointTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\r\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r\n} USB_OTG_OUTEndpointTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_Host_Mode_Register_Structures\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\r\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\r\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\r\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\r\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\r\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\r\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\r\n} USB_OTG_HostTypeDef;\r\n\r\n/**\r\n  * @brief USB_OTG_Host_Channel_Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\r\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\r\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\r\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\r\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\r\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\r\n  uint32_t Reserved[2];           /*!< Reserved                                      */\r\n} USB_OTG_HostChannelTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief OCTO Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */\r\n  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */\r\n  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */\r\n  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */\r\n  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */\r\n  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */\r\n  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */\r\n  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */\r\n  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */\r\n  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */\r\n  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */\r\n  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */\r\n  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */\r\n  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */\r\n  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */\r\n  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */\r\n  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */\r\n  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */\r\n  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */\r\n  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */\r\n  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */\r\n  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */\r\n  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */\r\n  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */\r\n  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */\r\n  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */\r\n  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */\r\n  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */\r\n  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */\r\n  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */\r\n  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */\r\n  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */\r\n  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */\r\n  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */\r\n  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */\r\n  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */\r\n  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */\r\n  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */\r\n  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */\r\n  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */\r\n  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */\r\n  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */\r\n  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */\r\n  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */\r\n  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */\r\n  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */\r\n  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */\r\n  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */\r\n  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */\r\n  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */\r\n  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */\r\n  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */\r\n  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */\r\n  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */\r\n} OCTOSPI_TypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @brief OCTO Serial Peripheral Interface IO Manager\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */\r\n  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */\r\n} OCTOSPIM_TypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief OTFD register\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t REG_CONFIGR;\r\n  __IO uint32_t REG_START_ADDR;\r\n  __IO uint32_t REG_END_ADDR;\r\n  __IO uint32_t REG_NONCER0;\r\n  __IO uint32_t REG_NONCER1;\r\n  __IO uint32_t REG_KEYR0;\r\n  __IO uint32_t REG_KEYR1;\r\n  __IO uint32_t REG_KEYR2;\r\n  __IO uint32_t REG_KEYR3;\r\n} OTFDEC_Region_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;\r\n  uint32_t RESERVED1[191];\r\n  __IO uint32_t ISR;\r\n  __IO uint32_t ICR;\r\n  __IO uint32_t IER;\r\n  uint32_t RESERVED2[56];\r\n  __IO uint32_t HWCFGR2;\r\n  __IO uint32_t HWCFGR1;\r\n  __IO uint32_t VERR;\r\n  __IO uint32_t IPIDR;\r\n  __IO uint32_t SIDR;\r\n} OTFDEC_TypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief Global Programmer View\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t      RESERVED0[2036];     /*!< Reserved,                                                                           Address offset: 0x00-0x1FCC     */\r\n  __IO uint32_t AXI_PERIPH_ID_4;     /*!< AXI interconnect - peripheral ID4 register,                                         Address offset: 0x1FD0          */\r\n  uint32_t      AXI_PERIPH_ID_5;     /*!< Reserved,                                                                           Address offset: 0x1FD4          */\r\n  uint32_t      AXI_PERIPH_ID_6;     /*!< Reserved,                                                                           Address offset: 0x1FD8          */\r\n  uint32_t      AXI_PERIPH_ID_7;     /*!< Reserved,                                                                           Address offset: 0x1FDC          */\r\n  __IO uint32_t AXI_PERIPH_ID_0;     /*!< AXI interconnect - peripheral ID0 register,                                         Address offset: 0x1FE0          */\r\n  __IO uint32_t AXI_PERIPH_ID_1;     /*!< AXI interconnect - peripheral ID1 register,                                         Address offset: 0x1FE4          */\r\n  __IO uint32_t AXI_PERIPH_ID_2;     /*!< AXI interconnect - peripheral ID2 register,                                         Address offset: 0x1FE8          */\r\n  __IO uint32_t AXI_PERIPH_ID_3;     /*!< AXI interconnect - peripheral ID3 register,                                         Address offset: 0x1FEC          */\r\n  __IO uint32_t AXI_COMP_ID_0;       /*!< AXI interconnect - component ID0 register,                                          Address offset: 0x1FF0          */\r\n  __IO uint32_t AXI_COMP_ID_1;       /*!< AXI interconnect - component ID1 register,                                          Address offset: 0x1FF4          */\r\n  __IO uint32_t AXI_COMP_ID_2;       /*!< AXI interconnect - component ID2 register,                                          Address offset: 0x1FF8          */\r\n  __IO uint32_t AXI_COMP_ID_3;       /*!< AXI interconnect - component ID3 register,                                          Address offset: 0x1FFC          */\r\n  uint32_t      RESERVED1[2];        /*!< Reserved,                                                                           Address offset: 0x2000-0x2004   */\r\n  __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register,           Address offset: 0x2008          */\r\n  uint32_t      RESERVED2[6];        /*!< Reserved,                                                                           Address offset: 0x200C-0x2020   */\r\n  __IO uint32_t AXI_TARG1_FN_MOD2;   /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register,                      Address offset: 0x2024          */\r\n  uint32_t      RESERVED3;           /*!< Reserved,                                                                           Address offset: 0x2028          */\r\n  __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register,           Address offset: 0x202C          */\r\n  uint32_t      RESERVED4[54];       /*!< Reserved,                                                                           Address offset: 0x2030-0x2104   */\r\n  __IO uint32_t AXI_TARG1_FN_MOD;    /*!< AXI interconnect - TARG 1 issuing functionality modification register,              Address offset: 0x2108          */\r\n  uint32_t      RESERVED5[959];      /*!< Reserved,                                                                           Address offset: 0x210C-0x3004   */\r\n  __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register,           Address offset: 0x3008          */\r\n  uint32_t      RESERVED6[6];        /*!< Reserved,                                                                           Address offset: 0x300C-0x3020   */\r\n  __IO uint32_t AXI_TARG2_FN_MOD2;   /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register,                      Address offset: 0x3024          */\r\n  uint32_t      RESERVED7;           /*!< Reserved,                                                                           Address offset: 0x3028          */\r\n  __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register,           Address offset: 0x302C          */\r\n  uint32_t      RESERVED8[54];       /*!< Reserved,                                                                           Address offset: 0x3030-0x3104   */\r\n  __IO uint32_t AXI_TARG2_FN_MOD;    /*!< AXI interconnect - TARG 2 issuing functionality modification register,              Address offset: 0x3108          */\r\n  uint32_t      RESERVED9[959];      /*!< Reserved,                                                                           Address offset: 0x310C-0x4004   */\r\n  __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;   /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register,          Address offset: 0x4008          */\r\n  uint32_t      RESERVED10[1023];    /*!< Reserved,                                                                           Address offset: 0x400C-0x5004   */\r\n  __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register,           Address offset: 0x5008          */\r\n  uint32_t      RESERVED11[1023];    /*!< Reserved,                                                                           Address offset: 0x500C-0x6004   */\r\n  __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register,           Address offset: 0x6008          */\r\n  uint32_t      RESERVED12[1023];    /*!< Reserved,                                                                           Address offset: 0x600C-0x7004   */\r\n  __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register,           Address offset: 0x7008          */\r\n  uint32_t      RESERVED13[1023];    /*!< Reserved,                                                                           Address offset: 0x700C-0x8004   */\r\n  __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register,           Address offset: 0x8008          */\r\n  uint32_t      RESERVED14[6];       /*!< Reserved,                                                                           Address offset: 0x800C-0x8020   */\r\n  __IO uint32_t AXI_TARG7_FN_MOD2;   /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register,                      Address offset: 0x8024          */\r\n  uint32_t      RESERVED15;          /*!< Reserved,                                                                           Address offset: 0x8028          */\r\n  __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register,           Address offset: 0x802C          */\r\n  uint32_t      RESERVED16[54];      /*!< Reserved,                                                                           Address offset: 0x8030-0x8104   */\r\n  __IO uint32_t AXI_TARG7_FN_MOD;    /*!< AXI interconnect - TARG 7 issuing functionality modification register,              Address offset: 0x8108          */\r\n  uint32_t      RESERVED17[959];     /*!< Reserved,                                                                           Address offset: 0x810C-0x9004   */\r\n  __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register,           Address offset: 0x9008          */\r\n  uint32_t      RESERVED117[6];      /*!< Reserved,                                                                           Address offset: 0x900C-0x9020   */\r\n  __IO uint32_t AXI_TARG8_FN_MOD2;   /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register,                      Address offset: 0x9024          */\r\n  uint32_t      RESERVED118[56];     /*!< Reserved,                                                                           Address offset: 0x9028-0x9104   */\r\n  __IO uint32_t AXI_TARG8_FN_MOD;    /*!< AXI interconnect - TARG 8 issuing functionality modification register,              Address offset: 0x9108          */\r\n  uint32_t      RESERVED119[58310];  /*!< Reserved,                                                                           Address offset: 0x910C-0x42020  */\r\n  __IO uint32_t AXI_INI1_FN_MOD2;    /*!< AXI interconnect - INI 1 functionality modification 2 register,                     Address offset: 0x42024         */\r\n  __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register,                   Address offset: 0x42028         */\r\n  uint32_t      RESERVED18[53];      /*!< Reserved,                                                                           Address offset: 0x4202C-0x420FC */\r\n  __IO uint32_t AXI_INI1_READ_QOS;   /*!< AXI interconnect - INI 1 read QoS register,                                         Address offset: 0x42100         */\r\n  __IO uint32_t AXI_INI1_WRITE_QOS;  /*!< AXI interconnect - INI 1 write QoS register,                                        Address offset: 0x42104         */\r\n  __IO uint32_t AXI_INI1_FN_MOD;     /*!< AXI interconnect - INI 1 issuing functionality modification register,               Address offset: 0x42108         */\r\n  uint32_t      RESERVED19[1021];    /*!< Reserved,                                                                           Address offset: 0x4210C-0x430FC */\r\n  __IO uint32_t AXI_INI2_READ_QOS;   /*!< AXI interconnect - INI 2 read QoS register,                                         Address offset: 0x43100         */\r\n  __IO uint32_t AXI_INI2_WRITE_QOS;  /*!< AXI interconnect - INI 2 write QoS register,                                        Address offset: 0x43104         */\r\n  __IO uint32_t AXI_INI2_FN_MOD;     /*!< AXI interconnect - INI 2 issuing functionality modification register,               Address offset: 0x43108         */\r\n  uint32_t      RESERVED20[966];     /*!< Reserved,                                                                           Address offset: 0x4310C-0x44020 */\r\n  __IO uint32_t AXI_INI3_FN_MOD2;    /*!< AXI interconnect - INI 3 functionality modification 2 register,                     Address offset: 0x44024         */\r\n  __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register,                   Address offset: 0x44028         */\r\n  uint32_t      RESERVED21[53];      /*!< Reserved,                                                                           Address offset: 0x4402C-0x440FC */\r\n  __IO uint32_t AXI_INI3_READ_QOS;   /*!< AXI interconnect - INI 3 read QoS register,                                         Address offset: 0x44100         */\r\n  __IO uint32_t AXI_INI3_WRITE_QOS;  /*!< AXI interconnect - INI 3 write QoS register,                                        Address offset: 0x44104         */\r\n  __IO uint32_t AXI_INI3_FN_MOD;     /*!< AXI interconnect - INI 3 issuing functionality modification register,               Address offset: 0x44108         */\r\n  uint32_t      RESERVED22[1021];    /*!< Reserved,                                                                           Address offset: 0x4410C-0x450FC */\r\n  __IO uint32_t AXI_INI4_READ_QOS;   /*!< AXI interconnect - INI 4 read QoS register,                                         Address offset: 0x45100         */\r\n  __IO uint32_t AXI_INI4_WRITE_QOS;  /*!< AXI interconnect - INI 4 write QoS register,                                        Address offset: 0x45104         */\r\n  __IO uint32_t AXI_INI4_FN_MOD;     /*!< AXI interconnect - INI 4 issuing functionality modification register,               Address offset: 0x45108         */\r\n  uint32_t      RESERVED23[1021];    /*!< Reserved,                                                                           Address offset: 0x4510C-0x460FC */\r\n  __IO uint32_t AXI_INI5_READ_QOS;   /*!< AXI interconnect - INI 5 read QoS register,                                         Address offset: 0x46100         */\r\n  __IO uint32_t AXI_INI5_WRITE_QOS;  /*!< AXI interconnect - INI 5 write QoS register,                                        Address offset: 0x46104         */\r\n  __IO uint32_t AXI_INI5_FN_MOD;     /*!< AXI interconnect - INI 5 issuing functionality modification register,               Address offset: 0x46108         */\r\n  uint32_t      RESERVED24[1021];    /*!< Reserved,                                                                           Address offset: 0x4610C-0x470FC */\r\n  __IO uint32_t AXI_INI6_READ_QOS;   /*!< AXI interconnect - INI 6 read QoS register,                                         Address offset: 0x47100         */\r\n  __IO uint32_t AXI_INI6_WRITE_QOS;  /*!< AXI interconnect - INI 6 write QoS register,                                        Address offset: 0x47104         */\r\n  __IO uint32_t AXI_INI6_FN_MOD;     /*!< AXI interconnect - INI 6 issuing functionality modification register,               Address offset: 0x47108         */\r\n\r\n} GPV_TypeDef;\r\n\r\n/** @addtogroup Peripheral_memory_map\r\n  * @{\r\n  */\r\n#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */\r\n#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */\r\n#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */\r\n#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */\r\n#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */\r\n#define D1_AXISRAM1_BASE           (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI                */\r\n#define D1_AXISRAM2_BASE           (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity)  */\r\n#define D1_AXISRAM_BASE            D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI             */\r\n\r\n#define D2_AHBSRAM1_BASE          (0x30000000UL)   /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge    */\r\n#define D2_AHBSRAM2_BASE          (0x30004000UL)   /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge    */\r\n#define D2_AHBSRAM_BASE           D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */\r\n\r\n#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */\r\n#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge                               */\r\n\r\n#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */\r\n#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */\r\n#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */\r\n\r\n#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */\r\n#define FLASH_END                 (0x080FFFFFUL) /*!< FLASH end address                                                                       */\r\n\r\n\r\n/* Legacy define */\r\n#define FLASH_BASE                FLASH_BANK1_BASE\r\n\r\n/*!< Device electronic signature memory map */\r\n#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */\r\n#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */\r\n\r\n\r\n/*!< Peripheral memory map */\r\n#define D2_APB1PERIPH_BASE        PERIPH_BASE\r\n#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r\n#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r\n#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)\r\n\r\n#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\r\n#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)\r\n\r\n#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)\r\n#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)\r\n\r\n/*!< Legacy Peripheral memory map */\r\n#define APB1PERIPH_BASE        PERIPH_BASE\r\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)\r\n\r\n\r\n/*!< D1_AHB1PERIPH peripherals */\r\n\r\n#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)\r\n#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)\r\n#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)\r\n#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)\r\n#define OCTOSPI1_R_BASE       (D1_AHB1PERIPH_BASE + 0x5000UL)\r\n#define DLYB_OCTOSPI1_BASE    (D1_AHB1PERIPH_BASE + 0x6000UL)\r\n#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)\r\n#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)\r\n#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)\r\n#define OCTOSPI2_R_BASE       (D1_AHB1PERIPH_BASE + 0xA000UL)\r\n#define DLYB_OCTOSPI2_BASE    (D1_AHB1PERIPH_BASE + 0xB000UL)\r\n#define OCTOSPIM_BASE         (D1_AHB1PERIPH_BASE + 0xB400UL)\r\n\r\n#define OTFDEC1_BASE          (D1_AHB1PERIPH_BASE + 0xB800UL)\r\n#define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)\r\n#define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)\r\n#define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)\r\n#define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)\r\n#define OTFDEC2_BASE          (D1_AHB1PERIPH_BASE + 0xBC00UL)\r\n#define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)\r\n#define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)\r\n#define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)\r\n#define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)\r\n\r\n/*!< D2_AHB1PERIPH peripherals */\r\n\r\n#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)\r\n#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)\r\n#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)\r\n#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)\r\n#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)\r\n#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)\r\n#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)\r\n#define ETH_MAC_BASE            (ETH_BASE)\r\n\r\n/*!< USB registers base address */\r\n#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)\r\n#define USB_OTG_GLOBAL_BASE                  (0x000UL)\r\n#define USB_OTG_DEVICE_BASE                  (0x800UL)\r\n#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)\r\n#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)\r\n#define USB_OTG_EP_REG_SIZE                  (0x20UL)\r\n#define USB_OTG_HOST_BASE                    (0x400UL)\r\n#define USB_OTG_HOST_PORT_BASE               (0x440UL)\r\n#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)\r\n#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)\r\n#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)\r\n#define USB_OTG_FIFO_BASE                    (0x1000UL)\r\n#define USB_OTG_FIFO_SIZE                    (0x1000UL)\r\n\r\n/*!< D2_AHB2PERIPH peripherals */\r\n\r\n#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)\r\n#define PSSI_BASE              (D2_AHB2PERIPH_BASE + 0x0400UL)\r\n#define CRYP_BASE              (D2_AHB2PERIPH_BASE + 0x1000UL)\r\n#define HASH_BASE              (D2_AHB2PERIPH_BASE + 0x1400UL)\r\n#define HASH_DIGEST_BASE       (D2_AHB2PERIPH_BASE + 0x1710UL)\r\n#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)\r\n#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)\r\n#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)\r\n#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)\r\n#define FMAC_BASE              (D2_AHB2PERIPH_BASE + 0x4000UL)\r\n#define CORDIC_BASE            (D2_AHB2PERIPH_BASE + 0x4400UL)\r\n\r\n/*!< D3_AHB1PERIPH peripherals */\r\n#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)\r\n#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)\r\n#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)\r\n#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)\r\n#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)\r\n#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)\r\n#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)\r\n#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)\r\n#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)\r\n#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)\r\n#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)\r\n#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)\r\n#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)\r\n#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)\r\n#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)\r\n#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)\r\n#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)\r\n#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)\r\n#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)\r\n\r\n/*!< D1_APB1PERIPH peripherals */\r\n#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)\r\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)\r\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)\r\n#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)\r\n\r\n/*!< D2_APB1PERIPH peripherals */\r\n#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)\r\n#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)\r\n#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)\r\n#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)\r\n#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)\r\n#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)\r\n#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)\r\n#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)\r\n#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)\r\n#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)\r\n\r\n\r\n#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)\r\n#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)\r\n#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)\r\n#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)\r\n#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)\r\n#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)\r\n#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)\r\n#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)\r\n#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)\r\n#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)\r\n#define I2C5_BASE             (D2_APB1PERIPH_BASE + 0x6400UL)\r\n#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)\r\n#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)\r\n#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)\r\n#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)\r\n#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)\r\n#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)\r\n#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)\r\n#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)\r\n#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)\r\n#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)\r\n#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)\r\n#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)\r\n#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)\r\n#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)\r\n#define FDCAN3_BASE           (D2_APB1PERIPH_BASE + 0xD400UL)\r\n#define TIM23_BASE            (D2_APB1PERIPH_BASE + 0xE000UL)\r\n#define TIM24_BASE            (D2_APB1PERIPH_BASE + 0xE400UL)\r\n\r\n/*!< D2_APB2PERIPH peripherals */\r\n\r\n#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)\r\n#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)\r\n#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)\r\n#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)\r\n#define UART9_BASE            (D2_APB2PERIPH_BASE + 0x1800UL)\r\n#define USART10_BASE          (D2_APB2PERIPH_BASE + 0x1C00UL)\r\n#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)\r\n#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)\r\n#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)\r\n#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)\r\n#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)\r\n#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)\r\n#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)\r\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)\r\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)\r\n#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7800UL)\r\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)\r\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)\r\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)\r\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)\r\n#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)\r\n#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)\r\n#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)\r\n#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)\r\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)\r\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)\r\n#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)\r\n#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)\r\n\r\n\r\n/*!< D3_APB1PERIPH peripherals */\r\n#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)\r\n#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)\r\n#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)\r\n#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)\r\n#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)\r\n#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)\r\n#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)\r\n#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)\r\n#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)\r\n#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)\r\n#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)\r\n#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)\r\n#define COMP1_BASE            (COMP12_BASE + 0x0CUL)\r\n#define COMP2_BASE            (COMP12_BASE + 0x10UL)\r\n#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)\r\n#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)\r\n#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)\r\n\r\n\r\n#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)\r\n#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)\r\n#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)\r\n\r\n#define DTS_BASE              (D3_APB1PERIPH_BASE + 0x6800UL)\r\n\r\n\r\n\r\n#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)\r\n#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)\r\n#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)\r\n#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)\r\n#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)\r\n#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)\r\n#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)\r\n#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)\r\n\r\n#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)\r\n#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)\r\n#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)\r\n#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)\r\n#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)\r\n#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)\r\n#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)\r\n#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)\r\n\r\n#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)\r\n#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)\r\n#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)\r\n#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)\r\n#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)\r\n#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)\r\n#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)\r\n#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)\r\n\r\n#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)\r\n#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)\r\n\r\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\r\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\r\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\r\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\r\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\r\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\r\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\r\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\r\n\r\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\r\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\r\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\r\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\r\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\r\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\r\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\r\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\r\n\r\n#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)\r\n#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)\r\n#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)\r\n#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)\r\n#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)\r\n#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)\r\n#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)\r\n#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)\r\n#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)\r\n#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)\r\n#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)\r\n#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)\r\n#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)\r\n#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)\r\n#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)\r\n#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)\r\n\r\n#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)\r\n#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)\r\n#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)\r\n#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)\r\n#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)\r\n#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)\r\n#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)\r\n#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)\r\n\r\n#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)\r\n#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)\r\n\r\n/*!< FMC Banks registers base  address */\r\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)\r\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)\r\n#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)\r\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)\r\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)\r\n\r\n/* Debug MCU registers base address */\r\n#define DBGMCU_BASE           (0x5C001000UL)\r\n\r\n#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)\r\n#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)\r\n#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)\r\n#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)\r\n#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)\r\n#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)\r\n#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)\r\n#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)\r\n#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)\r\n#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)\r\n#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)\r\n#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)\r\n#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)\r\n#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)\r\n#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)\r\n#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)\r\n\r\n#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)\r\n#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)\r\n#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)\r\n#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)\r\n#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)\r\n#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL)\r\n\r\n#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)\r\n#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)\r\n#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)\r\n\r\n#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)\r\n#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)\r\n\r\n\r\n\r\n#define GPV_BASE       (PERIPH_BASE + 0x11000000UL)   /*!<  GPV_BASE       (PERIPH_BASE + 0x11000000UL)                    */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Peripheral_declaration\r\n  * @{\r\n  */\r\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\r\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\r\n#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)\r\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r\n#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)\r\n\r\n\r\n#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)\r\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\r\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\r\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\r\n#define USART2              ((USART_TypeDef *) USART2_BASE)\r\n#define USART3              ((USART_TypeDef *) USART3_BASE)\r\n#define USART6              ((USART_TypeDef *) USART6_BASE)\r\n#define USART10             ((USART_TypeDef *) USART10_BASE)\r\n#define UART7               ((USART_TypeDef *) UART7_BASE)\r\n#define UART8               ((USART_TypeDef *) UART8_BASE)\r\n#define UART9               ((USART_TypeDef *) UART9_BASE)\r\n#define CRS                 ((CRS_TypeDef *) CRS_BASE)\r\n#define UART4               ((USART_TypeDef *) UART4_BASE)\r\n#define UART5               ((USART_TypeDef *) UART5_BASE)\r\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r\n#define I2C4                ((I2C_TypeDef *) I2C4_BASE)\r\n#define I2C5                ((I2C_TypeDef *) I2C5_BASE)\r\n#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\r\n#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)\r\n#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)\r\n#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)\r\n#define TIM23               ((TIM_TypeDef *) TIM23_BASE)\r\n#define TIM24               ((TIM_TypeDef *) TIM24_BASE)\r\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\r\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\r\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r\n#define DAC1                ((DAC_TypeDef *) DAC1_BASE)\r\n#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\r\n#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)\r\n#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)\r\n#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)\r\n#define DTS                 ((DTS_TypeDef *) DTS_BASE)\r\n#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)\r\n#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)\r\n\r\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r\n#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)\r\n#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\r\n#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\r\n#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)\r\n#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)\r\n#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)\r\n#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)\r\n\r\n\r\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r\n#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)\r\n#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)\r\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\r\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r\n#define USART1              ((USART_TypeDef *) USART1_BASE)\r\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\r\n#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\r\n#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\r\n#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\r\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r\n#define SAI4                ((SAI_TypeDef *) SAI4_BASE)\r\n#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)\r\n#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)\r\n\r\n#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\r\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r\n#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r\n#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r\n#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r\n#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r\n#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r\n#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r\n#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)\r\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\r\n#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)\r\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r\n\r\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\r\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\r\n\r\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r\n#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)\r\n#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\r\n\r\n#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)\r\n#define HASH                ((HASH_TypeDef *) HASH_BASE)\r\n#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)\r\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r\n#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)\r\n#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)\r\n#define FMAC                ((FMAC_TypeDef *) FMAC_BASE)\r\n#define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)\r\n\r\n#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)\r\n#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)\r\n#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)\r\n#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)\r\n#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)\r\n#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)\r\n#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)\r\n#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)\r\n#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)\r\n\r\n#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)\r\n#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)\r\n#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)\r\n#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)\r\n#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)\r\n#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)\r\n#define RAMECC1_Monitor6     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)\r\n\r\n#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)\r\n#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)\r\n#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)\r\n#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)\r\n\r\n#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)\r\n#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)\r\n#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)\r\n\r\n#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)\r\n#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)\r\n#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)\r\n#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)\r\n#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)\r\n#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)\r\n#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)\r\n#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)\r\n#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)\r\n\r\n\r\n#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)\r\n#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)\r\n#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)\r\n#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)\r\n#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)\r\n#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)\r\n#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)\r\n#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)\r\n\r\n#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)\r\n#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)\r\n\r\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r\n\r\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r\n\r\n\r\n#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\r\n#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\r\n#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\r\n#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\r\n#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\r\n#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\r\n#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\r\n#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\r\n#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\r\n#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\r\n#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\r\n#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\r\n#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\r\n#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)\r\n#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)\r\n#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)\r\n#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)\r\n\r\n#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\r\n#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\r\n#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\r\n#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\r\n#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)\r\n#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)\r\n#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)\r\n#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)\r\n\r\n#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)\r\n#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\r\n\r\n\r\n#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r\n#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r\n#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\r\n#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r\n#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r\n\r\n#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)\r\n#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)\r\n#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)\r\n#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)\r\n#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)\r\n\r\n#define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)\r\n#define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)\r\n#define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)\r\n#define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)\r\n#define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)\r\n\r\n#define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)\r\n#define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)\r\n#define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)\r\n#define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)\r\n#define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)\r\n\r\n#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)\r\n#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)\r\n\r\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r\n\r\n#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)\r\n#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))\r\n\r\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\r\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r\n\r\n#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)\r\n\r\n#define ETH                 ((ETH_TypeDef *)ETH_BASE)\r\n#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)\r\n#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)\r\n#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)\r\n#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)\r\n#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)\r\n#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)\r\n#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)\r\n#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)\r\n#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)\r\n#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)\r\n#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)\r\n#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)\r\n#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)\r\n#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)\r\n#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)\r\n#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)\r\n#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)\r\n\r\n\r\n#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)\r\n\r\n/* Legacy defines */\r\n#define USB_OTG_HS                   USB1_OTG_HS\r\n#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE\r\n\r\n#define GPV                ((GPV_TypeDef *) GPV_BASE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_constants\r\n  * @{\r\n  */\r\n\r\n  /** @addtogroup Peripheral_Registers_Bits_Definition\r\n  * @{\r\n  */\r\n\r\n/******************************************************************************/\r\n/*                         Peripheral Registers_Bits_Definition               */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Analog to Digital Converter                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************************  ADC VERSION  ********************************/\r\n#define ADC_VER_V5_V90\r\n/********************  Bit definition for ADC_ISR register  ********************/\r\n#define ADC_ISR_ADRDY_Pos                 (0U)\r\n#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */\r\n#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */\r\n#define ADC_ISR_EOSMP_Pos                 (1U)\r\n#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */\r\n#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */\r\n#define ADC_ISR_EOC_Pos                   (2U)\r\n#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */\r\n#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */\r\n#define ADC_ISR_EOS_Pos                   (3U)\r\n#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */\r\n#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */\r\n#define ADC_ISR_OVR_Pos                   (4U)\r\n#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */\r\n#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */\r\n#define ADC_ISR_JEOC_Pos                  (5U)\r\n#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */\r\n#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */\r\n#define ADC_ISR_JEOS_Pos                  (6U)\r\n#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */\r\n#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */\r\n#define ADC_ISR_AWD1_Pos                  (7U)\r\n#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */\r\n#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */\r\n#define ADC_ISR_AWD2_Pos                  (8U)\r\n#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */\r\n#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */\r\n#define ADC_ISR_AWD3_Pos                  (9U)\r\n#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */\r\n#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */\r\n#define ADC_ISR_JQOVF_Pos                 (10U)\r\n#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */\r\n#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */\r\n#define ADC_ISR_LDORDY_Pos                 (12U)\r\n#define ADC_ISR_LDORDY_Msk                 (0x1UL << ADC_ISR_LDORDY_Pos)         /*!< 0x00001000 */\r\n#define ADC_ISR_LDORDY                     ADC_ISR_LDORDY_Msk                    /*!< ADC LDO Ready (LDORDY) flag  */\r\n\r\n/********************  Bit definition for ADC_IER register  ********************/\r\n#define ADC_IER_ADRDYIE_Pos               (0U)\r\n#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */\r\n#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */\r\n#define ADC_IER_EOSMPIE_Pos               (1U)\r\n#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */\r\n#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */\r\n#define ADC_IER_EOCIE_Pos                 (2U)\r\n#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */\r\n#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */\r\n#define ADC_IER_EOSIE_Pos                 (3U)\r\n#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */\r\n#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */\r\n#define ADC_IER_OVRIE_Pos                 (4U)\r\n#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */\r\n#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */\r\n#define ADC_IER_JEOCIE_Pos                (5U)\r\n#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */\r\n#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */\r\n#define ADC_IER_JEOSIE_Pos                (6U)\r\n#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */\r\n#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */\r\n#define ADC_IER_AWD1IE_Pos                (7U)\r\n#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */\r\n#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */\r\n#define ADC_IER_AWD2IE_Pos                (8U)\r\n#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */\r\n#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */\r\n#define ADC_IER_AWD3IE_Pos                (9U)\r\n#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */\r\n#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */\r\n#define ADC_IER_JQOVFIE_Pos               (10U)\r\n#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */\r\n#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */\r\n\r\n/********************  Bit definition for ADC_CR register  ********************/\r\n#define ADC_CR_ADEN_Pos                   (0U)\r\n#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */\r\n#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */\r\n#define ADC_CR_ADDIS_Pos                  (1U)\r\n#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */\r\n#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */\r\n#define ADC_CR_ADSTART_Pos                (2U)\r\n#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */\r\n#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */\r\n#define ADC_CR_JADSTART_Pos               (3U)\r\n#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */\r\n#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */\r\n#define ADC_CR_ADSTP_Pos                  (4U)\r\n#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */\r\n#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */\r\n#define ADC_CR_JADSTP_Pos                 (5U)\r\n#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */\r\n#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */\r\n#define ADC_CR_BOOST_Pos                  (8U)\r\n#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */\r\n#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */\r\n#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */\r\n#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */\r\n#define ADC_CR_ADCALLIN_Pos               (16U)\r\n#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */\r\n#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */\r\n#define ADC_CR_LINCALRDYW1_Pos            (22U)\r\n#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */\r\n#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */\r\n#define ADC_CR_LINCALRDYW2_Pos            (23U)\r\n#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */\r\n#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */\r\n#define ADC_CR_LINCALRDYW3_Pos            (24U)\r\n#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */\r\n#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */\r\n#define ADC_CR_LINCALRDYW4_Pos            (25U)\r\n#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */\r\n#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */\r\n#define ADC_CR_LINCALRDYW5_Pos            (26U)\r\n#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */\r\n#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */\r\n#define ADC_CR_LINCALRDYW6_Pos            (27U)\r\n#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */\r\n#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */\r\n#define ADC_CR_ADVREGEN_Pos               (28U)\r\n#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */\r\n#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */\r\n#define ADC_CR_DEEPPWD_Pos                (29U)\r\n#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */\r\n#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */\r\n#define ADC_CR_ADCALDIF_Pos               (30U)\r\n#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */\r\n#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */\r\n#define ADC_CR_ADCAL_Pos                  (31U)\r\n#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */\r\n#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */\r\n\r\n/********************  Bit definition for ADC_CFGR register  ********************/\r\n#define ADC_CFGR_DMNGT_Pos                (0U)\r\n#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */\r\n#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */\r\n#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */\r\n#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */\r\n\r\n#define ADC_CFGR_RES_Pos                  (2U)\r\n#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */\r\n#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */\r\n#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */\r\n#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */\r\n#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */\r\n\r\n#define ADC_CFGR_EXTSEL_Pos               (5U)\r\n#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */\r\n#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */\r\n#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */\r\n#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */\r\n#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */\r\n#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */\r\n#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */\r\n\r\n#define ADC_CFGR_EXTEN_Pos                (10U)\r\n#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */\r\n#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */\r\n#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */\r\n#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */\r\n\r\n#define ADC_CFGR_OVRMOD_Pos               (12U)\r\n#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */\r\n#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */\r\n#define ADC_CFGR_CONT_Pos                 (13U)\r\n#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */\r\n#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */\r\n#define ADC_CFGR_AUTDLY_Pos               (14U)\r\n#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */\r\n#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */\r\n\r\n#define ADC_CFGR_DISCEN_Pos               (16U)\r\n#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */\r\n#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */\r\n\r\n#define ADC_CFGR_DISCNUM_Pos              (17U)\r\n#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */\r\n#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */\r\n#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */\r\n#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */\r\n#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */\r\n\r\n#define ADC_CFGR_JDISCEN_Pos              (20U)\r\n#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */\r\n#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */\r\n#define ADC_CFGR_JQM_Pos                  (21U)\r\n#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */\r\n#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */\r\n#define ADC_CFGR_AWD1SGL_Pos              (22U)\r\n#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */\r\n#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */\r\n#define ADC_CFGR_AWD1EN_Pos               (23U)\r\n#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */\r\n#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */\r\n#define ADC_CFGR_JAWD1EN_Pos              (24U)\r\n#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */\r\n#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */\r\n#define ADC_CFGR_JAUTO_Pos                (25U)\r\n#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */\r\n#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */\r\n\r\n#define ADC_CFGR_AWD1CH_Pos               (26U)\r\n#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */\r\n#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */\r\n#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */\r\n#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */\r\n#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */\r\n#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */\r\n#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */\r\n\r\n#define ADC_CFGR_JQDIS_Pos                (31U)\r\n#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */\r\n#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */\r\n\r\n#define ADC3_CFGR_DMAEN_Pos             (0U)\r\n#define ADC3_CFGR_DMAEN_Msk             (0x1UL << ADC3_CFGR_DMAEN_Pos)           /*!< 0x00000001 */\r\n#define ADC3_CFGR_DMAEN                 ADC3_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */\r\n#define ADC3_CFGR_DMACFG_Pos            (1U)\r\n#define ADC3_CFGR_DMACFG_Msk            (0x1UL << ADC3_CFGR_DMACFG_Pos)          /*!< 0x00000002 */\r\n#define ADC3_CFGR_DMACFG                ADC3_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */\r\n\r\n#define ADC3_CFGR_RES_Pos               (3U)\r\n#define ADC3_CFGR_RES_Msk               (0x3UL << ADC3_CFGR_RES_Pos)             /*!< 0x00000018 */\r\n#define ADC3_CFGR_RES                   ADC3_CFGR_RES_Msk                        /*!< ADC data resolution */\r\n#define ADC3_CFGR_RES_0                 (0x1UL << ADC3_CFGR_RES_Pos)             /*!< 0x00000008 */\r\n#define ADC3_CFGR_RES_1                 (0x2UL << ADC3_CFGR_RES_Pos)             /*!< 0x00000010 */\r\n\r\n#define ADC3_CFGR_ALIGN_Pos             (15U)\r\n#define ADC3_CFGR_ALIGN_Msk             (0x1UL << ADC3_CFGR_ALIGN_Pos)           /*!< 0x00008000 */\r\n#define ADC3_CFGR_ALIGN                 ADC3_CFGR_ALIGN_Msk                      /*!< ADC data alignment */\r\n/********************  Bit definition for ADC_CFGR2 register  ********************/\r\n#define ADC_CFGR2_ROVSE_Pos               (0U)\r\n#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */\r\n#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */\r\n#define ADC_CFGR2_JOVSE_Pos               (1U)\r\n#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */\r\n#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */\r\n\r\n#define ADC_CFGR2_OVSS_Pos                (5U)\r\n#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */\r\n#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */\r\n#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */\r\n#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */\r\n#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */\r\n#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */\r\n\r\n#define ADC_CFGR2_TROVS_Pos               (9U)\r\n#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */\r\n#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */\r\n#define ADC_CFGR2_ROVSM_Pos               (10U)\r\n#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */\r\n#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */\r\n\r\n#define ADC_CFGR2_RSHIFT1_Pos             (11U)\r\n#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */\r\n#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */\r\n#define ADC_CFGR2_RSHIFT2_Pos             (12U)\r\n#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */\r\n#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */\r\n#define ADC_CFGR2_RSHIFT3_Pos             (13U)\r\n#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */\r\n#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */\r\n#define ADC_CFGR2_RSHIFT4_Pos             (14U)\r\n#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */\r\n#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */\r\n\r\n#define ADC_CFGR2_OVSR_Pos                (16U)\r\n#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */\r\n#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */\r\n#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */\r\n#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */\r\n#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */\r\n#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */\r\n#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */\r\n#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */\r\n#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */\r\n#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */\r\n#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */\r\n#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */\r\n\r\n#define ADC_CFGR2_LSHIFT_Pos              (28U)\r\n#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */\r\n#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */\r\n#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */\r\n#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */\r\n#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */\r\n#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */\r\n\r\n#define ADC3_CFGR2_OVSR_Pos             (2U)\r\n#define ADC3_CFGR2_OVSR_Msk             (0x7UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x0000001C */\r\n#define ADC3_CFGR2_OVSR                 ADC3_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */\r\n#define ADC3_CFGR2_OVSR_0               (0x1UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x00000004 */\r\n#define ADC3_CFGR2_OVSR_1               (0x2UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x00000008 */\r\n#define ADC3_CFGR2_OVSR_2               (0x4UL << ADC3_CFGR2_OVSR_Pos)           /*!< 0x00000010 */\r\n\r\n#define ADC3_CFGR2_SWTRIG_Pos           (25U)\r\n#define ADC3_CFGR2_SWTRIG_Msk           (0x1UL << ADC3_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */\r\n#define ADC3_CFGR2_SWTRIG               ADC3_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */\r\n#define ADC3_CFGR2_BULB_Pos             (26U)\r\n#define ADC3_CFGR2_BULB_Msk             (0x1UL << ADC3_CFGR2_BULB_Pos)           /*!< 0x04000000 */\r\n#define ADC3_CFGR2_BULB                 ADC3_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */\r\n#define ADC3_CFGR2_SMPTRIG_Pos          (27U)\r\n#define ADC3_CFGR2_SMPTRIG_Msk          (0x1UL << ADC3_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */\r\n#define ADC3_CFGR2_SMPTRIG              ADC3_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */\r\n/********************  Bit definition for ADC_SMPR1 register  ********************/\r\n#define ADC_SMPR1_SMP0_Pos                (0U)\r\n#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */\r\n#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */\r\n#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */\r\n#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */\r\n#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */\r\n\r\n#define ADC_SMPR1_SMP1_Pos                (3U)\r\n#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */\r\n#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */\r\n#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */\r\n#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */\r\n#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */\r\n\r\n#define ADC_SMPR1_SMP2_Pos                (6U)\r\n#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */\r\n#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */\r\n#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */\r\n#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */\r\n#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */\r\n\r\n#define ADC_SMPR1_SMP3_Pos                (9U)\r\n#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */\r\n#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */\r\n#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */\r\n#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */\r\n#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */\r\n\r\n#define ADC_SMPR1_SMP4_Pos                (12U)\r\n#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */\r\n#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */\r\n#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */\r\n#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */\r\n#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */\r\n\r\n#define ADC_SMPR1_SMP5_Pos                (15U)\r\n#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */\r\n#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */\r\n#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */\r\n#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */\r\n#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */\r\n\r\n#define ADC_SMPR1_SMP6_Pos                (18U)\r\n#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */\r\n#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */\r\n#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */\r\n#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */\r\n#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */\r\n\r\n#define ADC_SMPR1_SMP7_Pos                (21U)\r\n#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */\r\n#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */\r\n#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */\r\n#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */\r\n#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */\r\n\r\n#define ADC_SMPR1_SMP8_Pos                (24U)\r\n#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */\r\n#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */\r\n#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */\r\n#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */\r\n#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */\r\n\r\n#define ADC_SMPR1_SMP9_Pos                (27U)\r\n#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */\r\n#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */\r\n#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */\r\n#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */\r\n#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for ADC_SMPR2 register  ********************/\r\n#define ADC_SMPR2_SMP10_Pos               (0U)\r\n#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */\r\n#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */\r\n#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */\r\n#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */\r\n#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */\r\n\r\n#define ADC_SMPR2_SMP11_Pos               (3U)\r\n#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */\r\n#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */\r\n#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */\r\n#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */\r\n#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */\r\n\r\n#define ADC_SMPR2_SMP12_Pos               (6U)\r\n#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */\r\n#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */\r\n#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */\r\n#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */\r\n#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */\r\n\r\n#define ADC_SMPR2_SMP13_Pos               (9U)\r\n#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */\r\n#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */\r\n#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */\r\n#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */\r\n#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */\r\n\r\n#define ADC_SMPR2_SMP14_Pos               (12U)\r\n#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */\r\n#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */\r\n#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */\r\n#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */\r\n#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */\r\n\r\n#define ADC_SMPR2_SMP15_Pos               (15U)\r\n#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */\r\n#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */\r\n#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */\r\n#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */\r\n#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */\r\n\r\n#define ADC_SMPR2_SMP16_Pos               (18U)\r\n#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */\r\n#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */\r\n#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */\r\n#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */\r\n#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */\r\n\r\n#define ADC_SMPR2_SMP17_Pos               (21U)\r\n#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */\r\n#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */\r\n#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */\r\n#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */\r\n#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */\r\n\r\n#define ADC_SMPR2_SMP18_Pos               (24U)\r\n#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */\r\n#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */\r\n#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */\r\n#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */\r\n#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */\r\n\r\n#define ADC_SMPR2_SMP19_Pos               (27U)\r\n#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */\r\n#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */\r\n#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */\r\n#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */\r\n#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for ADC_PCSEL register  ********************/\r\n#define ADC_PCSEL_PCSEL_Pos               (0U)\r\n#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */\r\n#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */\r\n#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */\r\n#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */\r\n#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */\r\n#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */\r\n#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */\r\n#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */\r\n#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */\r\n#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */\r\n#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */\r\n#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */\r\n#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */\r\n#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */\r\n#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */\r\n#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */\r\n#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */\r\n#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */\r\n#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */\r\n#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */\r\n#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */\r\n#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */\r\n\r\n/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/\r\n#define ADC_LTR_LT_Pos                    (0U)\r\n#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */\r\n#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */\r\n\r\n/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/\r\n#define ADC_HTR_HT_Pos                    (0U)\r\n#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */\r\n#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */\r\n\r\n/********************  Bit definition for ADC3_TR1 register  *******************/\r\n#define ADC3_TR1_LT1_Pos                (0U)\r\n#define ADC3_TR1_LT1_Msk                (0xFFFUL << ADC3_TR1_LT1_Pos)            /*!< 0x00000FFF */\r\n#define ADC3_TR1_LT1                    ADC3_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */\r\n\r\n#define ADC3_TR1_AWDFILT_Pos            (12U)\r\n#define ADC3_TR1_AWDFILT_Msk            (0x7UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00007000 */\r\n#define ADC3_TR1_AWDFILT                ADC3_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */\r\n#define ADC3_TR1_AWDFILT_0              (0x1UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00001000 */\r\n#define ADC3_TR1_AWDFILT_1              (0x2UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00002000 */\r\n#define ADC3_TR1_AWDFILT_2              (0x4UL << ADC3_TR1_AWDFILT_Pos)          /*!< 0x00004000 */\r\n\r\n#define ADC3_TR1_HT1_Pos                (16U)\r\n#define ADC3_TR1_HT1_Msk                (0xFFFUL << ADC3_TR1_HT1_Pos)            /*!< 0x0FFF0000 */\r\n#define ADC3_TR1_HT1                    ADC3_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */\r\n\r\n/********************  Bit definition for ADC3_TR2 register  *******************/\r\n#define ADC3_TR2_LT2_Pos                (0U)\r\n#define ADC3_TR2_LT2_Msk                (0xFFUL << ADC3_TR2_LT2_Pos)             /*!< 0x000000FF */\r\n#define ADC3_TR2_LT2                    ADC3_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */\r\n\r\n#define ADC3_TR2_HT2_Pos                (16U)\r\n#define ADC3_TR2_HT2_Msk                (0xFFUL << ADC3_TR2_HT2_Pos)             /*!< 0x00FF0000 */\r\n#define ADC3_TR2_HT2                    ADC3_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */\r\n\r\n/********************  Bit definition for ADC3_TR3 register  *******************/\r\n#define ADC3_TR3_LT3_Pos                (0U)\r\n#define ADC3_TR3_LT3_Msk                (0xFFUL << ADC3_TR3_LT3_Pos)             /*!< 0x000000FF */\r\n#define ADC3_TR3_LT3                    ADC3_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */\r\n\r\n#define ADC3_TR3_HT3_Pos                (16U)\r\n#define ADC3_TR3_HT3_Msk                (0xFFUL << ADC3_TR3_HT3_Pos)             /*!< 0x00FF0000 */\r\n#define ADC3_TR3_HT3                    ADC3_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */\r\n\r\n/********************  Bit definition for ADC_SQR1 register  ********************/\r\n#define ADC_SQR1_L_Pos                    (0U)\r\n#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */\r\n#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence length */\r\n#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */\r\n#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */\r\n#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */\r\n#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */\r\n\r\n#define ADC_SQR1_SQ1_Pos                  (6U)\r\n#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */\r\n#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */\r\n#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */\r\n#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */\r\n#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */\r\n#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */\r\n#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */\r\n\r\n#define ADC_SQR1_SQ2_Pos                  (12U)\r\n#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */\r\n#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */\r\n#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */\r\n#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */\r\n#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */\r\n#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */\r\n#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */\r\n\r\n#define ADC_SQR1_SQ3_Pos                  (18U)\r\n#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */\r\n#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */\r\n#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */\r\n#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */\r\n#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */\r\n#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */\r\n#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */\r\n\r\n#define ADC_SQR1_SQ4_Pos                  (24U)\r\n#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */\r\n#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */\r\n#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */\r\n#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */\r\n#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */\r\n#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */\r\n#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */\r\n\r\n/********************  Bit definition for ADC_SQR2 register  ********************/\r\n#define ADC_SQR2_SQ5_Pos                  (0U)\r\n#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */\r\n#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */\r\n#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */\r\n#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */\r\n#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */\r\n#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */\r\n#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */\r\n\r\n#define ADC_SQR2_SQ6_Pos                  (6U)\r\n#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */\r\n#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */\r\n#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */\r\n#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */\r\n#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */\r\n#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */\r\n#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */\r\n\r\n#define ADC_SQR2_SQ7_Pos                  (12U)\r\n#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */\r\n#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */\r\n#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */\r\n#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */\r\n#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */\r\n#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */\r\n#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */\r\n\r\n#define ADC_SQR2_SQ8_Pos                  (18U)\r\n#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */\r\n#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */\r\n#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */\r\n#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */\r\n#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */\r\n#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */\r\n#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */\r\n\r\n#define ADC_SQR2_SQ9_Pos                  (24U)\r\n#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */\r\n#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */\r\n#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */\r\n#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */\r\n#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */\r\n#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */\r\n#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */\r\n\r\n/********************  Bit definition for ADC_SQR3 register  ********************/\r\n#define ADC_SQR3_SQ10_Pos                 (0U)\r\n#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */\r\n#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */\r\n#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */\r\n#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */\r\n#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */\r\n#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */\r\n#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */\r\n\r\n#define ADC_SQR3_SQ11_Pos                 (6U)\r\n#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */\r\n#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */\r\n#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */\r\n#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */\r\n#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */\r\n#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */\r\n#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */\r\n\r\n#define ADC_SQR3_SQ12_Pos                 (12U)\r\n#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */\r\n#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */\r\n#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */\r\n#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */\r\n#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */\r\n#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */\r\n#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */\r\n\r\n#define ADC_SQR3_SQ13_Pos                 (18U)\r\n#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */\r\n#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */\r\n#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */\r\n#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */\r\n#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */\r\n#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */\r\n#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */\r\n\r\n#define ADC_SQR3_SQ14_Pos                 (24U)\r\n#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */\r\n#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */\r\n#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */\r\n#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */\r\n#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */\r\n#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */\r\n#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */\r\n\r\n/********************  Bit definition for ADC_SQR4 register  ********************/\r\n#define ADC_SQR4_SQ15_Pos                 (0U)\r\n#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */\r\n#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */\r\n#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */\r\n#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */\r\n#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */\r\n#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */\r\n#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */\r\n\r\n#define ADC_SQR4_SQ16_Pos                 (6U)\r\n#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */\r\n#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */\r\n#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */\r\n#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */\r\n#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */\r\n#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */\r\n#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */\r\n/********************  Bit definition for ADC_DR register  ********************/\r\n#define ADC_DR_RDATA_Pos                  (0U)\r\n#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */\r\n#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */\r\n\r\n/********************  Bit definition for ADC_JSQR register  ********************/\r\n#define ADC_JSQR_JL_Pos                   (0U)\r\n#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */\r\n#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */\r\n#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */\r\n#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */\r\n\r\n#define ADC_JSQR_JEXTSEL_Pos              (2U)\r\n#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */\r\n#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */\r\n#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */\r\n#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */\r\n#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */\r\n#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */\r\n#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */\r\n\r\n#define ADC_JSQR_JEXTEN_Pos               (7U)\r\n#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */\r\n#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */\r\n#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */\r\n#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */\r\n\r\n#define ADC_JSQR_JSQ1_Pos                 (9U)\r\n#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */\r\n#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */\r\n#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */\r\n#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */\r\n#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */\r\n#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */\r\n#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */\r\n\r\n#define ADC_JSQR_JSQ2_Pos                 (15U)\r\n#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */\r\n#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */\r\n#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */\r\n#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */\r\n#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */\r\n#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */\r\n#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */\r\n\r\n#define ADC_JSQR_JSQ3_Pos                 (21U)\r\n#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */\r\n#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */\r\n#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */\r\n#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */\r\n#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */\r\n#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */\r\n#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */\r\n\r\n#define ADC_JSQR_JSQ4_Pos                 (27U)\r\n#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */\r\n#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */\r\n#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */\r\n#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */\r\n#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */\r\n#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */\r\n#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_OFR1 register  ********************/\r\n#define ADC_OFR1_OFFSET1_Pos              (0U)\r\n#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */\r\n#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR1_OFFSET1_CH_Pos           (26U)\r\n#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */\r\n#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR1_SSATE_Pos                (31U)\r\n#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR1_OFFSET1_Pos              (0U)\r\n#define ADC3_OFR1_OFFSET1_Msk              (0xFFFUL << ADC3_OFR1_OFFSET1_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR1_OFFSET1                  ADC3_OFR1_OFFSET1_Msk                /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR1_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR1_OFFSETPOS_Msk         (0x1UL << ADC3_OFR1_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR1_OFFSETPOS             ADC3_OFR1_OFFSETPOS_Msk                 /*!< ADC offset number 1 positive */\r\n#define ADC3_OFR1_SATEN_Pos             (25U)\r\n#define ADC3_OFR1_SATEN_Msk             (0x1UL << ADC3_OFR1_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR1_SATEN                 ADC3_OFR1_SATEN_Msk                     /*!< ADC offset number 1 saturation enable */\r\n\r\n#define ADC3_OFR1_OFFSET1_EN_Pos        (31U)\r\n#define ADC3_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR1_OFFSET1_EN            ADC3_OFR1_OFFSET1_EN_Msk                /*!< ADC offset number 1 enable */\r\n\r\n/********************  Bit definition for ADC_OFR2 register  ********************/\r\n#define ADC_OFR2_OFFSET2_Pos              (0U)\r\n#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */\r\n#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR2_OFFSET2_CH_Pos           (26U)\r\n#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */\r\n#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR2_SSATE_Pos                (31U)\r\n#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR2_OFFSET2_Pos              (0U)\r\n#define ADC3_OFR2_OFFSET2_Msk              (0xFFFUL << ADC3_OFR2_OFFSET2_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR2_OFFSET2                  ADC3_OFR2_OFFSET2_Msk                /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR2_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR2_OFFSETPOS_Msk         (0x1UL << ADC3_OFR2_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR2_OFFSETPOS             ADC3_OFR2_OFFSETPOS_Msk                 /*!< ADC offset number 2 positive */\r\n#define ADC3_OFR2_SATEN_Pos             (25U)\r\n#define ADC3_OFR2_SATEN_Msk             (0x1UL << ADC3_OFR2_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR2_SATEN                 ADC3_OFR2_SATEN_Msk                     /*!< ADC offset number 2 saturation enable */\r\n\r\n#define ADC3_OFR2_OFFSET2_EN_Pos        (31U)\r\n#define ADC3_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR2_OFFSET2_EN            ADC3_OFR2_OFFSET2_EN_Msk                /*!< ADC offset number 2 enable */\r\n\r\n/********************  Bit definition for ADC_OFR3 register  ********************/\r\n#define ADC_OFR3_OFFSET3_Pos              (0U)\r\n#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */\r\n#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR3_OFFSET3_CH_Pos           (26U)\r\n#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */\r\n#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR3_SSATE_Pos                (31U)\r\n#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR3_OFFSET3_Pos              (0U)\r\n#define ADC3_OFR3_OFFSET3_Msk              (0xFFFUL << ADC3_OFR3_OFFSET3_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR3_OFFSET3                  ADC3_OFR3_OFFSET3_Msk                /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR3_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR3_OFFSETPOS_Msk         (0x1UL << ADC3_OFR3_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR3_OFFSETPOS             ADC3_OFR3_OFFSETPOS_Msk                 /*!< ADC offset number 3 positive */\r\n#define ADC3_OFR3_SATEN_Pos             (25U)\r\n#define ADC3_OFR3_SATEN_Msk             (0x1UL << ADC3_OFR3_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR3_SATEN                 ADC3_OFR3_SATEN_Msk                     /*!< ADC offset number 3 saturation enable */\r\n\r\n#define ADC3_OFR3_OFFSET3_EN_Pos        (31U)\r\n#define ADC3_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR3_OFFSET3_EN            ADC3_OFR3_OFFSET3_EN_Msk                /*!< ADC offset number 3 enable */\r\n\r\n/********************  Bit definition for ADC_OFR4 register  ********************/\r\n#define ADC_OFR4_OFFSET4_Pos              (0U)\r\n#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */\r\n#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */\r\n#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */\r\n#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */\r\n#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */\r\n#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */\r\n#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */\r\n#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */\r\n#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */\r\n#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */\r\n#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */\r\n#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */\r\n#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */\r\n#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */\r\n#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */\r\n#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */\r\n#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */\r\n#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */\r\n#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */\r\n#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */\r\n#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */\r\n#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */\r\n#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */\r\n#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */\r\n#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */\r\n#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */\r\n#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */\r\n#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */\r\n\r\n#define ADC_OFR4_OFFSET4_CH_Pos           (26U)\r\n#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */\r\n#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */\r\n#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */\r\n#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */\r\n#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */\r\n#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */\r\n#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */\r\n\r\n#define ADC_OFR4_SSATE_Pos                (31U)\r\n#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */\r\n#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */\r\n\r\n#define ADC3_OFR4_OFFSET4_Pos              (0U)\r\n#define ADC3_OFR4_OFFSET4_Msk              (0xFFFUL << ADC3_OFR4_OFFSET4_Pos)   /*!< 0x00000FFF */\r\n#define ADC3_OFR4_OFFSET4                  ADC3_OFR4_OFFSET4_Msk                /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */\r\n\r\n#define ADC3_OFR4_OFFSETPOS_Pos         (24U)\r\n#define ADC3_OFR4_OFFSETPOS_Msk         (0x1UL << ADC3_OFR4_OFFSETPOS_Pos)      /*!< 0x01000000 */\r\n#define ADC3_OFR4_OFFSETPOS             ADC3_OFR4_OFFSETPOS_Msk                 /*!< ADC offset number 4 positive */\r\n#define ADC3_OFR4_SATEN_Pos             (25U)\r\n#define ADC3_OFR4_SATEN_Msk             (0x1UL << ADC3_OFR4_SATEN_Pos)          /*!< 0x02000000 */\r\n#define ADC3_OFR4_SATEN                 ADC3_OFR4_SATEN_Msk                     /*!< ADC offset number 4 saturation enable */\r\n\r\n#define ADC3_OFR4_OFFSET4_EN_Pos        (31U)\r\n#define ADC3_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos)     /*!< 0x80000000 */\r\n#define ADC3_OFR4_OFFSET4_EN            ADC3_OFR4_OFFSET4_EN_Msk                /*!< ADC offset number 4 enable */\r\n\r\n/********************  Bit definition for ADC_JDR1 register  ********************/\r\n#define ADC_JDR1_JDATA_Pos                (0U)\r\n#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_JDR2 register  ********************/\r\n#define ADC_JDR2_JDATA_Pos                (0U)\r\n#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_JDR3 register  ********************/\r\n#define ADC_JDR3_JDATA_Pos                (0U)\r\n#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_JDR4 register  ********************/\r\n#define ADC_JDR4_JDATA_Pos                (0U)\r\n#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */\r\n#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */\r\n#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */\r\n#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */\r\n#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */\r\n#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */\r\n#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */\r\n#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */\r\n#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */\r\n#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */\r\n#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */\r\n#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */\r\n#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */\r\n#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */\r\n#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */\r\n#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */\r\n#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */\r\n#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */\r\n#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */\r\n#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */\r\n#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */\r\n#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */\r\n#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */\r\n#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */\r\n#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */\r\n#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */\r\n#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */\r\n#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */\r\n#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */\r\n#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */\r\n#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */\r\n#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */\r\n#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for ADC_AWD2CR register  ********************/\r\n#define ADC_AWD2CR_AWD2CH_Pos             (0U)\r\n#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */\r\n#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */\r\n#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */\r\n#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */\r\n#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */\r\n#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */\r\n#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */\r\n#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */\r\n#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */\r\n#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */\r\n#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */\r\n#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */\r\n#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */\r\n#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */\r\n#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */\r\n#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */\r\n#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */\r\n#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */\r\n#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */\r\n#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */\r\n#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */\r\n#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */\r\n\r\n/********************  Bit definition for ADC_AWD3CR register  ********************/\r\n#define ADC_AWD3CR_AWD3CH_Pos             (0U)\r\n#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */\r\n#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */\r\n#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */\r\n#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */\r\n#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */\r\n#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */\r\n#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */\r\n#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */\r\n#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */\r\n#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */\r\n#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */\r\n#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */\r\n#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */\r\n#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */\r\n#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */\r\n#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */\r\n#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */\r\n#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */\r\n#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */\r\n#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */\r\n#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */\r\n#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */\r\n\r\n/********************  Bit definition for ADC_DIFSEL register  ********************/\r\n#define ADC_DIFSEL_DIFSEL_Pos             (0U)\r\n#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */\r\n#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */\r\n#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */\r\n#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */\r\n#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */\r\n#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */\r\n#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */\r\n#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */\r\n#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */\r\n#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */\r\n#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */\r\n#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */\r\n#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */\r\n#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */\r\n#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */\r\n#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */\r\n#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */\r\n#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */\r\n#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */\r\n#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */\r\n#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */\r\n#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */\r\n\r\n/********************  Bit definition for ADC_CALFACT register  ********************/\r\n#define ADC_CALFACT_CALFACT_S_Pos         (0U)\r\n#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */\r\n#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */\r\n#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\r\n#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\r\n#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\r\n#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\r\n#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\r\n#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\r\n#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */\r\n#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */\r\n#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */\r\n#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */\r\n#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */\r\n#define ADC_CALFACT_CALFACT_D_Pos         (16U)\r\n#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */\r\n#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */\r\n#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\r\n#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\r\n#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\r\n#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\r\n#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\r\n#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\r\n#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */\r\n#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */\r\n#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */\r\n#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */\r\n#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */\r\n\r\n/********************  Bit definition for ADC_CALFACT2 register  ********************/\r\n#define ADC_CALFACT2_LINCALFACT_Pos       (0U)\r\n#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */\r\n#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */\r\n#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */\r\n#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */\r\n#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */\r\n#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */\r\n#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */\r\n#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */\r\n#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */\r\n#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */\r\n#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */\r\n#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */\r\n#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */\r\n#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */\r\n#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */\r\n#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */\r\n#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */\r\n#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */\r\n#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */\r\n#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */\r\n#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */\r\n#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */\r\n#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */\r\n#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */\r\n#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */\r\n#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */\r\n#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */\r\n#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */\r\n#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */\r\n#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */\r\n#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */\r\n#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */\r\n\r\n/*************************  ADC Common registers  *****************************/\r\n/********************  Bit definition for ADC_CSR register  ********************/\r\n#define ADC_CSR_ADRDY_MST_Pos             (0U)\r\n#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */\r\n#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */\r\n#define ADC_CSR_EOSMP_MST_Pos             (1U)\r\n#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */\r\n#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */\r\n#define ADC_CSR_EOC_MST_Pos               (2U)\r\n#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */\r\n#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */\r\n#define ADC_CSR_EOS_MST_Pos               (3U)\r\n#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */\r\n#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */\r\n#define ADC_CSR_OVR_MST_Pos               (4U)\r\n#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */\r\n#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */\r\n#define ADC_CSR_JEOC_MST_Pos              (5U)\r\n#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */\r\n#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */\r\n#define ADC_CSR_JEOS_MST_Pos              (6U)\r\n#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */\r\n#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */\r\n#define ADC_CSR_AWD1_MST_Pos              (7U)\r\n#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */\r\n#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */\r\n#define ADC_CSR_AWD2_MST_Pos              (8U)\r\n#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */\r\n#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */\r\n#define ADC_CSR_AWD3_MST_Pos              (9U)\r\n#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */\r\n#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */\r\n#define ADC_CSR_JQOVF_MST_Pos             (10U)\r\n#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */\r\n#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */\r\n#define ADC_CSR_ADRDY_SLV_Pos             (16U)\r\n#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */\r\n#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */\r\n#define ADC_CSR_EOSMP_SLV_Pos             (17U)\r\n#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */\r\n#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */\r\n#define ADC_CSR_EOC_SLV_Pos               (18U)\r\n#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */\r\n#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */\r\n#define ADC_CSR_EOS_SLV_Pos               (19U)\r\n#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */\r\n#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */\r\n#define ADC_CSR_OVR_SLV_Pos               (20U)\r\n#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */\r\n#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */\r\n#define ADC_CSR_JEOC_SLV_Pos              (21U)\r\n#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */\r\n#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */\r\n#define ADC_CSR_JEOS_SLV_Pos              (22U)\r\n#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */\r\n#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */\r\n#define ADC_CSR_AWD1_SLV_Pos              (23U)\r\n#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */\r\n#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */\r\n#define ADC_CSR_AWD2_SLV_Pos              (24U)\r\n#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */\r\n#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */\r\n#define ADC_CSR_AWD3_SLV_Pos              (25U)\r\n#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */\r\n#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */\r\n#define ADC_CSR_JQOVF_SLV_Pos             (26U)\r\n#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */\r\n#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */\r\n\r\n/********************  Bit definition for ADC_CCR register  ********************/\r\n#define ADC_CCR_DUAL_Pos                  (0U)\r\n#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */\r\n#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */\r\n#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */\r\n#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */\r\n#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */\r\n#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */\r\n#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */\r\n\r\n#define ADC_CCR_DELAY_Pos                 (8U)\r\n#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */\r\n#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */\r\n#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */\r\n#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */\r\n#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */\r\n#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */\r\n\r\n\r\n#define ADC_CCR_DAMDF_Pos                 (14U)\r\n#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */\r\n#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */\r\n#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */\r\n#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */\r\n\r\n#define ADC_CCR_CKMODE_Pos                (16U)\r\n#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */\r\n#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */\r\n#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */\r\n#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */\r\n\r\n#define ADC_CCR_PRESC_Pos                 (18U)\r\n#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */\r\n#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */\r\n#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */\r\n#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */\r\n#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */\r\n#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */\r\n\r\n#define ADC_CCR_VREFEN_Pos                (22U)\r\n#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */\r\n#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */\r\n#define ADC_CCR_TSEN_Pos                  (23U)\r\n#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */\r\n#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */\r\n#define ADC_CCR_VBATEN_Pos                (24U)\r\n#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */\r\n#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */\r\n\r\n/********************  Bit definition for ADC_CDR register  *******************/\r\n#define ADC_CDR_RDATA_MST_Pos             (0U)\r\n#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */\r\n#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */\r\n\r\n#define ADC_CDR_RDATA_SLV_Pos             (16U)\r\n#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */\r\n#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */\r\n\r\n/********************  Bit definition for ADC_CDR2 register  ******************/\r\n#define ADC_CDR2_RDATA_ALT_Pos            (0U)\r\n#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */\r\n#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                   VREFBUF                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for VREFBUF_CSR register  ****************/\r\n#define VREFBUF_CSR_ENVR_Pos        (0U)\r\n#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */\r\n#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */\r\n#define VREFBUF_CSR_HIZ_Pos         (1U)\r\n#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */\r\n#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */\r\n#define VREFBUF_CSR_VRR_Pos         (3U)\r\n#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */\r\n#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */\r\n#define VREFBUF_CSR_VRS_Pos         (4U)\r\n#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */\r\n#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */\r\n\r\n#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */\r\n#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)\r\n#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */\r\n#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */\r\n#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)\r\n#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */\r\n#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */\r\n#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)\r\n#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */\r\n#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */\r\n\r\n/*******************  Bit definition for VREFBUF_CCR register  ****************/\r\n#define VREFBUF_CCR_TRIM_Pos        (0U)\r\n#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */\r\n#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                 Flexible Datarate Controller Area Network                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*!<FDCAN control and status registers */\r\n/*****************  Bit definition for FDCAN_CREL register  *******************/\r\n#define FDCAN_CREL_DAY_Pos        (0U)\r\n#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */\r\n#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */\r\n#define FDCAN_CREL_MON_Pos        (8U)\r\n#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */\r\n#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */\r\n#define FDCAN_CREL_YEAR_Pos       (16U)\r\n#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */\r\n#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */\r\n#define FDCAN_CREL_SUBSTEP_Pos    (20U)\r\n#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */\r\n#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */\r\n#define FDCAN_CREL_STEP_Pos       (24U)\r\n#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */\r\n#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */\r\n#define FDCAN_CREL_REL_Pos        (28U)\r\n#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */\r\n#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */\r\n\r\n/*****************  Bit definition for FDCAN_ENDN register  *******************/\r\n#define FDCAN_ENDN_ETV_Pos        (0U)\r\n#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */\r\n\r\n/*****************  Bit definition for FDCAN_DBTP register  *******************/\r\n#define FDCAN_DBTP_DSJW_Pos       (0U)\r\n#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */\r\n#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */\r\n#define FDCAN_DBTP_DTSEG2_Pos     (4U)\r\n#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */\r\n#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */\r\n#define FDCAN_DBTP_DTSEG1_Pos     (8U)\r\n#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */\r\n#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */\r\n#define FDCAN_DBTP_DBRP_Pos       (16U)\r\n#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */\r\n#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */\r\n#define FDCAN_DBTP_TDC_Pos        (23U)\r\n#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */\r\n#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */\r\n\r\n/*****************  Bit definition for FDCAN_TEST register  *******************/\r\n#define FDCAN_TEST_LBCK_Pos       (4U)\r\n#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */\r\n#define FDCAN_TEST_TX_Pos         (5U)\r\n#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */\r\n#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */\r\n#define FDCAN_TEST_RX_Pos         (7U)\r\n#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */\r\n#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */\r\n\r\n/*****************  Bit definition for FDCAN_RWD register  ********************/\r\n#define FDCAN_RWD_WDC_Pos         (0U)\r\n#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */\r\n#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */\r\n#define FDCAN_RWD_WDV_Pos         (8U)\r\n#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */\r\n#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */\r\n\r\n/*****************  Bit definition for FDCAN_CCCR register  ********************/\r\n#define FDCAN_CCCR_INIT_Pos       (0U)\r\n#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */\r\n#define FDCAN_CCCR_CCE_Pos        (1U)\r\n#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */\r\n#define FDCAN_CCCR_ASM_Pos        (2U)\r\n#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */\r\n#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */\r\n#define FDCAN_CCCR_CSA_Pos        (3U)\r\n#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */\r\n#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */\r\n#define FDCAN_CCCR_CSR_Pos        (4U)\r\n#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */\r\n#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */\r\n#define FDCAN_CCCR_MON_Pos        (5U)\r\n#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */\r\n#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */\r\n#define FDCAN_CCCR_DAR_Pos        (6U)\r\n#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */\r\n#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */\r\n#define FDCAN_CCCR_TEST_Pos       (7U)\r\n#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */\r\n#define FDCAN_CCCR_FDOE_Pos       (8U)\r\n#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */\r\n#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */\r\n#define FDCAN_CCCR_BRSE_Pos       (9U)\r\n#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */\r\n#define FDCAN_CCCR_PXHD_Pos       (12U)\r\n#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */\r\n#define FDCAN_CCCR_EFBI_Pos       (13U)\r\n#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */\r\n#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */\r\n#define FDCAN_CCCR_TXP_Pos        (14U)\r\n#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */\r\n#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */\r\n#define FDCAN_CCCR_NISO_Pos       (15U)\r\n#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */\r\n\r\n/*****************  Bit definition for FDCAN_NBTP register  ********************/\r\n#define FDCAN_NBTP_NTSEG2_Pos     (0U)\r\n#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */\r\n#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */\r\n#define FDCAN_NBTP_NTSEG1_Pos     (8U)\r\n#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */\r\n#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */\r\n#define FDCAN_NBTP_NBRP_Pos       (16U)\r\n#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */\r\n#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */\r\n#define FDCAN_NBTP_NSJW_Pos       (25U)\r\n#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */\r\n#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */\r\n\r\n/*****************  Bit definition for FDCAN_TSCC register  ********************/\r\n#define FDCAN_TSCC_TSS_Pos        (0U)\r\n#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */\r\n#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */\r\n#define FDCAN_TSCC_TCP_Pos        (16U)\r\n#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */\r\n#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */\r\n\r\n/*****************  Bit definition for FDCAN_TSCV register  ********************/\r\n#define FDCAN_TSCV_TSC_Pos        (0U)\r\n#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */\r\n\r\n/*****************  Bit definition for FDCAN_TOCC register  ********************/\r\n#define FDCAN_TOCC_ETOC_Pos       (0U)\r\n#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */\r\n#define FDCAN_TOCC_TOS_Pos        (1U)\r\n#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */\r\n#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */\r\n#define FDCAN_TOCC_TOP_Pos        (16U)\r\n#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */\r\n#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */\r\n\r\n/*****************  Bit definition for FDCAN_TOCV register  ********************/\r\n#define FDCAN_TOCV_TOC_Pos        (0U)\r\n#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */\r\n\r\n/*****************  Bit definition for FDCAN_ECR register  *********************/\r\n#define FDCAN_ECR_TEC_Pos         (0U)\r\n#define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x000000FF */\r\n#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */\r\n#define FDCAN_ECR_REC_Pos         (8U)\r\n#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */\r\n#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */\r\n#define FDCAN_ECR_RP_Pos          (15U)\r\n#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */\r\n#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */\r\n#define FDCAN_ECR_CEL_Pos         (16U)\r\n#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */\r\n#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */\r\n\r\n/*****************  Bit definition for FDCAN_PSR register  *********************/\r\n#define FDCAN_PSR_LEC_Pos         (0U)\r\n#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */\r\n#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */\r\n#define FDCAN_PSR_ACT_Pos         (3U)\r\n#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */\r\n#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */\r\n#define FDCAN_PSR_EP_Pos          (5U)\r\n#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */\r\n#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */\r\n#define FDCAN_PSR_EW_Pos          (6U)\r\n#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */\r\n#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */\r\n#define FDCAN_PSR_BO_Pos          (7U)\r\n#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */\r\n#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */\r\n#define FDCAN_PSR_DLEC_Pos        (8U)\r\n#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */\r\n#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */\r\n#define FDCAN_PSR_RESI_Pos        (11U)\r\n#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */\r\n#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */\r\n#define FDCAN_PSR_RBRS_Pos        (12U)\r\n#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */\r\n#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */\r\n#define FDCAN_PSR_REDL_Pos        (13U)\r\n#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */\r\n#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */\r\n#define FDCAN_PSR_PXE_Pos         (14U)\r\n#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */\r\n#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */\r\n#define FDCAN_PSR_TDCV_Pos        (16U)\r\n#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */\r\n#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */\r\n\r\n/*****************  Bit definition for FDCAN_TDCR register  ********************/\r\n#define FDCAN_TDCR_TDCF_Pos       (0U)\r\n#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */\r\n#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */\r\n#define FDCAN_TDCR_TDCO_Pos       (8U)\r\n#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */\r\n#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */\r\n\r\n/*****************  Bit definition for FDCAN_IR register  **********************/\r\n#define FDCAN_IR_RF0N_Pos         (0U)\r\n#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */\r\n#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */\r\n#define FDCAN_IR_RF0W_Pos         (1U)\r\n#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */\r\n#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */\r\n#define FDCAN_IR_RF0F_Pos         (2U)\r\n#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */\r\n#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */\r\n#define FDCAN_IR_RF0L_Pos         (3U)\r\n#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */\r\n#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */\r\n#define FDCAN_IR_RF1N_Pos         (4U)\r\n#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */\r\n#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */\r\n#define FDCAN_IR_RF1W_Pos         (5U)\r\n#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */\r\n#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */\r\n#define FDCAN_IR_RF1F_Pos         (6U)\r\n#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */\r\n#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */\r\n#define FDCAN_IR_RF1L_Pos         (7U)\r\n#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */\r\n#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */\r\n#define FDCAN_IR_HPM_Pos          (8U)\r\n#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */\r\n#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */\r\n#define FDCAN_IR_TC_Pos           (9U)\r\n#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */\r\n#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */\r\n#define FDCAN_IR_TCF_Pos          (10U)\r\n#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */\r\n#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */\r\n#define FDCAN_IR_TFE_Pos          (11U)\r\n#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */\r\n#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */\r\n#define FDCAN_IR_TEFN_Pos         (12U)\r\n#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */\r\n#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */\r\n#define FDCAN_IR_TEFW_Pos         (13U)\r\n#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */\r\n#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */\r\n#define FDCAN_IR_TEFF_Pos         (14U)\r\n#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */\r\n#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */\r\n#define FDCAN_IR_TEFL_Pos         (15U)\r\n#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */\r\n#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */\r\n#define FDCAN_IR_TSW_Pos          (16U)\r\n#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */\r\n#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */\r\n#define FDCAN_IR_MRAF_Pos         (17U)\r\n#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */\r\n#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */\r\n#define FDCAN_IR_TOO_Pos          (18U)\r\n#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */\r\n#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */\r\n#define FDCAN_IR_DRX_Pos          (19U)\r\n#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */\r\n#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */\r\n#define FDCAN_IR_ELO_Pos          (22U)\r\n#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */\r\n#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */\r\n#define FDCAN_IR_EP_Pos           (23U)\r\n#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */\r\n#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */\r\n#define FDCAN_IR_EW_Pos           (24U)\r\n#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */\r\n#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */\r\n#define FDCAN_IR_BO_Pos           (25U)\r\n#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */\r\n#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */\r\n#define FDCAN_IR_WDI_Pos          (26U)\r\n#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */\r\n#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */\r\n#define FDCAN_IR_PEA_Pos          (27U)\r\n#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */\r\n#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */\r\n#define FDCAN_IR_PED_Pos          (28U)\r\n#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */\r\n#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */\r\n#define FDCAN_IR_ARA_Pos          (29U)\r\n#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */\r\n#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */\r\n\r\n/*****************  Bit definition for FDCAN_IE register  **********************/\r\n#define FDCAN_IE_RF0NE_Pos        (0U)\r\n#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */\r\n#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */\r\n#define FDCAN_IE_RF0WE_Pos        (1U)\r\n#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */\r\n#define FDCAN_IE_RF0FE_Pos        (2U)\r\n#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */\r\n#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */\r\n#define FDCAN_IE_RF0LE_Pos        (3U)\r\n#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */\r\n#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */\r\n#define FDCAN_IE_RF1NE_Pos        (4U)\r\n#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */\r\n#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */\r\n#define FDCAN_IE_RF1WE_Pos        (5U)\r\n#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */\r\n#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */\r\n#define FDCAN_IE_RF1FE_Pos        (6U)\r\n#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */\r\n#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */\r\n#define FDCAN_IE_RF1LE_Pos        (7U)\r\n#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */\r\n#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */\r\n#define FDCAN_IE_HPME_Pos         (8U)\r\n#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */\r\n#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */\r\n#define FDCAN_IE_TCE_Pos          (9U)\r\n#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */\r\n#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */\r\n#define FDCAN_IE_TCFE_Pos         (10U)\r\n#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */\r\n#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */\r\n#define FDCAN_IE_TFEE_Pos         (11U)\r\n#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */\r\n#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */\r\n#define FDCAN_IE_TEFNE_Pos        (12U)\r\n#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */\r\n#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */\r\n#define FDCAN_IE_TEFWE_Pos        (13U)\r\n#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */\r\n#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */\r\n#define FDCAN_IE_TEFFE_Pos        (14U)\r\n#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */\r\n#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */\r\n#define FDCAN_IE_TEFLE_Pos        (15U)\r\n#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */\r\n#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */\r\n#define FDCAN_IE_TSWE_Pos         (16U)\r\n#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */\r\n#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */\r\n#define FDCAN_IE_MRAFE_Pos        (17U)\r\n#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */\r\n#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */\r\n#define FDCAN_IE_TOOE_Pos         (18U)\r\n#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */\r\n#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */\r\n#define FDCAN_IE_DRXE_Pos         (19U)\r\n#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */\r\n#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */\r\n#define FDCAN_IE_BECE_Pos         (20U)\r\n#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */\r\n#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */\r\n#define FDCAN_IE_BEUE_Pos         (21U)\r\n#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */\r\n#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */\r\n#define FDCAN_IE_ELOE_Pos         (22U)\r\n#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */\r\n#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */\r\n#define FDCAN_IE_EPE_Pos          (23U)\r\n#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */\r\n#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */\r\n#define FDCAN_IE_EWE_Pos          (24U)\r\n#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */\r\n#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */\r\n#define FDCAN_IE_BOE_Pos          (25U)\r\n#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */\r\n#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */\r\n#define FDCAN_IE_WDIE_Pos         (26U)\r\n#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */\r\n#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */\r\n#define FDCAN_IE_PEAE_Pos         (27U)\r\n#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */\r\n#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */\r\n#define FDCAN_IE_PEDE_Pos         (28U)\r\n#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */\r\n#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */\r\n#define FDCAN_IE_ARAE_Pos         (29U)\r\n#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */\r\n#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */\r\n\r\n/*****************  Bit definition for FDCAN_ILS register  **********************/\r\n#define FDCAN_ILS_RF0NL_Pos       (0U)\r\n#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */\r\n#define FDCAN_ILS_RF0WL_Pos       (1U)\r\n#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */\r\n#define FDCAN_ILS_RF0FL_Pos       (2U)\r\n#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */\r\n#define FDCAN_ILS_RF0LL_Pos       (3U)\r\n#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */\r\n#define FDCAN_ILS_RF1NL_Pos       (4U)\r\n#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */\r\n#define FDCAN_ILS_RF1WL_Pos       (5U)\r\n#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */\r\n#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */\r\n#define FDCAN_ILS_RF1FL_Pos       (6U)\r\n#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */\r\n#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */\r\n#define FDCAN_ILS_RF1LL_Pos       (7U)\r\n#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */\r\n#define FDCAN_ILS_HPML_Pos        (8U)\r\n#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */\r\n#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */\r\n#define FDCAN_ILS_TCL_Pos         (9U)\r\n#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */\r\n#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */\r\n#define FDCAN_ILS_TCFL_Pos        (10U)\r\n#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */\r\n#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */\r\n#define FDCAN_ILS_TFEL_Pos        (11U)\r\n#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */\r\n#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */\r\n#define FDCAN_ILS_TEFNL_Pos       (12U)\r\n#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */\r\n#define FDCAN_ILS_TEFWL_Pos       (13U)\r\n#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */\r\n#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */\r\n#define FDCAN_ILS_TEFFL_Pos       (14U)\r\n#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */\r\n#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */\r\n#define FDCAN_ILS_TEFLL_Pos       (15U)\r\n#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */\r\n#define FDCAN_ILS_TSWL_Pos        (16U)\r\n#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */\r\n#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */\r\n#define FDCAN_ILS_MRAFE_Pos       (17U)\r\n#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */\r\n#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */\r\n#define FDCAN_ILS_TOOE_Pos        (18U)\r\n#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */\r\n#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */\r\n#define FDCAN_ILS_DRXE_Pos        (19U)\r\n#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */\r\n#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */\r\n#define FDCAN_ILS_BECE_Pos        (20U)\r\n#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */\r\n#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */\r\n#define FDCAN_ILS_BEUE_Pos        (21U)\r\n#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */\r\n#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */\r\n#define FDCAN_ILS_ELOE_Pos        (22U)\r\n#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */\r\n#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */\r\n#define FDCAN_ILS_EPE_Pos         (23U)\r\n#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */\r\n#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */\r\n#define FDCAN_ILS_EWE_Pos         (24U)\r\n#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */\r\n#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */\r\n#define FDCAN_ILS_BOE_Pos         (25U)\r\n#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */\r\n#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */\r\n#define FDCAN_ILS_WDIE_Pos        (26U)\r\n#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */\r\n#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */\r\n#define FDCAN_ILS_PEAE_Pos        (27U)\r\n#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */\r\n#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */\r\n#define FDCAN_ILS_PEDE_Pos        (28U)\r\n#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */\r\n#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */\r\n#define FDCAN_ILS_ARAE_Pos        (29U)\r\n#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */\r\n#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */\r\n\r\n/*****************  Bit definition for FDCAN_ILE register  **********************/\r\n#define FDCAN_ILE_EINT0_Pos       (0U)\r\n#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */\r\n#define FDCAN_ILE_EINT1_Pos       (1U)\r\n#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */\r\n\r\n/*****************  Bit definition for FDCAN_GFC register  **********************/\r\n#define FDCAN_GFC_RRFE_Pos        (0U)\r\n#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */\r\n#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */\r\n#define FDCAN_GFC_RRFS_Pos        (1U)\r\n#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */\r\n#define FDCAN_GFC_ANFE_Pos        (2U)\r\n#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */\r\n#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */\r\n#define FDCAN_GFC_ANFS_Pos        (4U)\r\n#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */\r\n#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */\r\n\r\n/*****************  Bit definition for FDCAN_SIDFC register  ********************/\r\n#define FDCAN_SIDFC_FLSSA_Pos     (2U)\r\n#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */\r\n#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */\r\n#define FDCAN_SIDFC_LSS_Pos       (16U)\r\n#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */\r\n#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */\r\n\r\n/*****************  Bit definition for FDCAN_XIDFC register  ********************/\r\n#define FDCAN_XIDFC_FLESA_Pos     (2U)\r\n#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */\r\n#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */\r\n#define FDCAN_XIDFC_LSE_Pos       (16U)\r\n#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */\r\n\r\n/*****************  Bit definition for FDCAN_XIDAM register  ********************/\r\n#define FDCAN_XIDAM_EIDM_Pos      (0U)\r\n#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */\r\n#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */\r\n\r\n/*****************  Bit definition for FDCAN_HPMS register  *********************/\r\n#define FDCAN_HPMS_BIDX_Pos       (0U)\r\n#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */\r\n#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */\r\n#define FDCAN_HPMS_MSI_Pos        (6U)\r\n#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */\r\n#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */\r\n#define FDCAN_HPMS_FIDX_Pos       (8U)\r\n#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */\r\n#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */\r\n#define FDCAN_HPMS_FLST_Pos       (15U)\r\n#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */\r\n\r\n/*****************  Bit definition for FDCAN_NDAT1 register  ********************/\r\n#define FDCAN_NDAT1_ND0_Pos       (0U)\r\n#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */\r\n#define FDCAN_NDAT1_ND1_Pos       (1U)\r\n#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */\r\n#define FDCAN_NDAT1_ND2_Pos       (2U)\r\n#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */\r\n#define FDCAN_NDAT1_ND3_Pos       (3U)\r\n#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */\r\n#define FDCAN_NDAT1_ND4_Pos       (4U)\r\n#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */\r\n#define FDCAN_NDAT1_ND5_Pos       (5U)\r\n#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */\r\n#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */\r\n#define FDCAN_NDAT1_ND6_Pos       (6U)\r\n#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */\r\n#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */\r\n#define FDCAN_NDAT1_ND7_Pos       (7U)\r\n#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */\r\n#define FDCAN_NDAT1_ND8_Pos       (8U)\r\n#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */\r\n#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */\r\n#define FDCAN_NDAT1_ND9_Pos       (9U)\r\n#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */\r\n#define FDCAN_NDAT1_ND10_Pos      (10U)\r\n#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */\r\n#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */\r\n#define FDCAN_NDAT1_ND11_Pos      (11U)\r\n#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */\r\n#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */\r\n#define FDCAN_NDAT1_ND12_Pos      (12U)\r\n#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */\r\n#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */\r\n#define FDCAN_NDAT1_ND13_Pos      (13U)\r\n#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */\r\n#define FDCAN_NDAT1_ND14_Pos      (14U)\r\n#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */\r\n#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */\r\n#define FDCAN_NDAT1_ND15_Pos      (15U)\r\n#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */\r\n#define FDCAN_NDAT1_ND16_Pos      (16U)\r\n#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */\r\n#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */\r\n#define FDCAN_NDAT1_ND17_Pos      (17U)\r\n#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */\r\n#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */\r\n#define FDCAN_NDAT1_ND18_Pos      (18U)\r\n#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */\r\n#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */\r\n#define FDCAN_NDAT1_ND19_Pos      (19U)\r\n#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */\r\n#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */\r\n#define FDCAN_NDAT1_ND20_Pos      (20U)\r\n#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */\r\n#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */\r\n#define FDCAN_NDAT1_ND21_Pos      (21U)\r\n#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */\r\n#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */\r\n#define FDCAN_NDAT1_ND22_Pos      (22U)\r\n#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */\r\n#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */\r\n#define FDCAN_NDAT1_ND23_Pos      (23U)\r\n#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */\r\n#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */\r\n#define FDCAN_NDAT1_ND24_Pos      (24U)\r\n#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */\r\n#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */\r\n#define FDCAN_NDAT1_ND25_Pos      (25U)\r\n#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */\r\n#define FDCAN_NDAT1_ND26_Pos      (26U)\r\n#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */\r\n#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */\r\n#define FDCAN_NDAT1_ND27_Pos      (27U)\r\n#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */\r\n#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */\r\n#define FDCAN_NDAT1_ND28_Pos      (28U)\r\n#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */\r\n#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */\r\n#define FDCAN_NDAT1_ND29_Pos      (29U)\r\n#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */\r\n#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */\r\n#define FDCAN_NDAT1_ND30_Pos      (30U)\r\n#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */\r\n#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */\r\n#define FDCAN_NDAT1_ND31_Pos      (31U)\r\n#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */\r\n\r\n/*****************  Bit definition for FDCAN_NDAT2 register  ********************/\r\n#define FDCAN_NDAT2_ND32_Pos      (0U)\r\n#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */\r\n#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */\r\n#define FDCAN_NDAT2_ND33_Pos      (1U)\r\n#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */\r\n#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */\r\n#define FDCAN_NDAT2_ND34_Pos      (2U)\r\n#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */\r\n#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */\r\n#define FDCAN_NDAT2_ND35_Pos      (3U)\r\n#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */\r\n#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */\r\n#define FDCAN_NDAT2_ND36_Pos      (4U)\r\n#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */\r\n#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */\r\n#define FDCAN_NDAT2_ND37_Pos      (5U)\r\n#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */\r\n#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */\r\n#define FDCAN_NDAT2_ND38_Pos      (6U)\r\n#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */\r\n#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */\r\n#define FDCAN_NDAT2_ND39_Pos      (7U)\r\n#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */\r\n#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */\r\n#define FDCAN_NDAT2_ND40_Pos      (8U)\r\n#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */\r\n#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */\r\n#define FDCAN_NDAT2_ND41_Pos      (9U)\r\n#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */\r\n#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */\r\n#define FDCAN_NDAT2_ND42_Pos      (10U)\r\n#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */\r\n#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */\r\n#define FDCAN_NDAT2_ND43_Pos      (11U)\r\n#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */\r\n#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */\r\n#define FDCAN_NDAT2_ND44_Pos      (12U)\r\n#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */\r\n#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */\r\n#define FDCAN_NDAT2_ND45_Pos      (13U)\r\n#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */\r\n#define FDCAN_NDAT2_ND46_Pos      (14U)\r\n#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */\r\n#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */\r\n#define FDCAN_NDAT2_ND47_Pos      (15U)\r\n#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */\r\n#define FDCAN_NDAT2_ND48_Pos      (16U)\r\n#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */\r\n#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */\r\n#define FDCAN_NDAT2_ND49_Pos      (17U)\r\n#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */\r\n#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */\r\n#define FDCAN_NDAT2_ND50_Pos      (18U)\r\n#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */\r\n#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */\r\n#define FDCAN_NDAT2_ND51_Pos      (19U)\r\n#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */\r\n#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */\r\n#define FDCAN_NDAT2_ND52_Pos      (20U)\r\n#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */\r\n#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */\r\n#define FDCAN_NDAT2_ND53_Pos      (21U)\r\n#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */\r\n#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */\r\n#define FDCAN_NDAT2_ND54_Pos      (22U)\r\n#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */\r\n#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */\r\n#define FDCAN_NDAT2_ND55_Pos      (23U)\r\n#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */\r\n#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */\r\n#define FDCAN_NDAT2_ND56_Pos      (24U)\r\n#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */\r\n#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */\r\n#define FDCAN_NDAT2_ND57_Pos      (25U)\r\n#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */\r\n#define FDCAN_NDAT2_ND58_Pos      (26U)\r\n#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */\r\n#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */\r\n#define FDCAN_NDAT2_ND59_Pos      (27U)\r\n#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */\r\n#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */\r\n#define FDCAN_NDAT2_ND60_Pos      (28U)\r\n#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */\r\n#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */\r\n#define FDCAN_NDAT2_ND61_Pos      (29U)\r\n#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */\r\n#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */\r\n#define FDCAN_NDAT2_ND62_Pos      (30U)\r\n#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */\r\n#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */\r\n#define FDCAN_NDAT2_ND63_Pos      (31U)\r\n#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */\r\n\r\n/*****************  Bit definition for FDCAN_RXF0C register  ********************/\r\n#define FDCAN_RXF0C_F0SA_Pos      (2U)\r\n#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */\r\n#define FDCAN_RXF0C_F0S_Pos       (16U)\r\n#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */\r\n#define FDCAN_RXF0C_F0WM_Pos      (24U)\r\n#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */\r\n#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */\r\n#define FDCAN_RXF0C_F0OM_Pos      (31U)\r\n#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */\r\n\r\n/*****************  Bit definition for FDCAN_RXF0S register  ********************/\r\n#define FDCAN_RXF0S_F0FL_Pos      (0U)\r\n#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */\r\n#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */\r\n#define FDCAN_RXF0S_F0GI_Pos      (8U)\r\n#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */\r\n#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */\r\n#define FDCAN_RXF0S_F0PI_Pos      (16U)\r\n#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */\r\n#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */\r\n#define FDCAN_RXF0S_F0F_Pos       (24U)\r\n#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */\r\n#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */\r\n#define FDCAN_RXF0S_RF0L_Pos      (25U)\r\n#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */\r\n\r\n/*****************  Bit definition for FDCAN_RXF0A register  ********************/\r\n#define FDCAN_RXF0A_F0AI_Pos      (0U)\r\n#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */\r\n\r\n/*****************  Bit definition for FDCAN_RXBC register  ********************/\r\n#define FDCAN_RXBC_RBSA_Pos       (2U)\r\n#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */\r\n#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */\r\n\r\n/*****************  Bit definition for FDCAN_RXF1C register  ********************/\r\n#define FDCAN_RXF1C_F1SA_Pos      (2U)\r\n#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */\r\n#define FDCAN_RXF1C_F1S_Pos       (16U)\r\n#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */\r\n#define FDCAN_RXF1C_F1WM_Pos      (24U)\r\n#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */\r\n#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */\r\n#define FDCAN_RXF1C_F1OM_Pos      (31U)\r\n#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */\r\n\r\n/*****************  Bit definition for FDCAN_RXF1S register  ********************/\r\n#define FDCAN_RXF1S_F1FL_Pos      (0U)\r\n#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */\r\n#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */\r\n#define FDCAN_RXF1S_F1GI_Pos      (8U)\r\n#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */\r\n#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */\r\n#define FDCAN_RXF1S_F1PI_Pos      (16U)\r\n#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */\r\n#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */\r\n#define FDCAN_RXF1S_F1F_Pos       (24U)\r\n#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */\r\n#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */\r\n#define FDCAN_RXF1S_RF1L_Pos      (25U)\r\n#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */\r\n\r\n/*****************  Bit definition for FDCAN_RXF1A register  ********************/\r\n#define FDCAN_RXF1A_F1AI_Pos      (0U)\r\n#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */\r\n\r\n/*****************  Bit definition for FDCAN_RXESC register  ********************/\r\n#define FDCAN_RXESC_F0DS_Pos      (0U)\r\n#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */\r\n#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */\r\n#define FDCAN_RXESC_F1DS_Pos      (4U)\r\n#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */\r\n#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */\r\n#define FDCAN_RXESC_RBDS_Pos      (8U)\r\n#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */\r\n#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */\r\n\r\n/*****************  Bit definition for FDCAN_TXBC register  *********************/\r\n#define FDCAN_TXBC_TBSA_Pos       (2U)\r\n#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */\r\n#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */\r\n#define FDCAN_TXBC_NDTB_Pos       (16U)\r\n#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */\r\n#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */\r\n#define FDCAN_TXBC_TFQS_Pos       (24U)\r\n#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */\r\n#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */\r\n#define FDCAN_TXBC_TFQM_Pos       (30U)\r\n#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */\r\n#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */\r\n\r\n/*****************  Bit definition for FDCAN_TXFQS register  *********************/\r\n#define FDCAN_TXFQS_TFFL_Pos      (0U)\r\n#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */\r\n#define FDCAN_TXFQS_TFGI_Pos      (8U)\r\n#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */\r\n#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */\r\n#define FDCAN_TXFQS_TFQPI_Pos     (16U)\r\n#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */\r\n#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */\r\n#define FDCAN_TXFQS_TFQF_Pos      (21U)\r\n#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */\r\n#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */\r\n\r\n/*****************  Bit definition for FDCAN_TXESC register  *********************/\r\n#define FDCAN_TXESC_TBDS_Pos      (0U)\r\n#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */\r\n#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */\r\n\r\n/*****************  Bit definition for FDCAN_TXBRP register  *********************/\r\n#define FDCAN_TXBRP_TRP_Pos       (0U)\r\n#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */\r\n\r\n/*****************  Bit definition for FDCAN_TXBAR register  *********************/\r\n#define FDCAN_TXBAR_AR_Pos        (0U)\r\n#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */\r\n\r\n/*****************  Bit definition for FDCAN_TXBCR register  *********************/\r\n#define FDCAN_TXBCR_CR_Pos        (0U)\r\n#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */\r\n\r\n/*****************  Bit definition for FDCAN_TXBTO register  *********************/\r\n#define FDCAN_TXBTO_TO_Pos        (0U)\r\n#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */\r\n\r\n/*****************  Bit definition for FDCAN_TXBCF register  *********************/\r\n#define FDCAN_TXBCF_CF_Pos        (0U)\r\n#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */\r\n\r\n/*****************  Bit definition for FDCAN_TXBTIE register  ********************/\r\n#define FDCAN_TXBTIE_TIE_Pos      (0U)\r\n#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */\r\n\r\n/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/\r\n#define FDCAN_TXBCIE_CFIE_Pos     (0U)\r\n#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */\r\n#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */\r\n\r\n/*****************  Bit definition for FDCAN_TXEFC register  *********************/\r\n#define FDCAN_TXEFC_EFSA_Pos      (2U)\r\n#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */\r\n#define FDCAN_TXEFC_EFS_Pos       (16U)\r\n#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */\r\n#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */\r\n#define FDCAN_TXEFC_EFWM_Pos      (24U)\r\n#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */\r\n#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */\r\n\r\n/*****************  Bit definition for FDCAN_TXEFS register  *********************/\r\n#define FDCAN_TXEFS_EFFL_Pos      (0U)\r\n#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */\r\n#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */\r\n#define FDCAN_TXEFS_EFGI_Pos      (8U)\r\n#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */\r\n#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */\r\n#define FDCAN_TXEFS_EFPI_Pos      (16U)\r\n#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */\r\n#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */\r\n#define FDCAN_TXEFS_EFF_Pos       (24U)\r\n#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */\r\n#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */\r\n#define FDCAN_TXEFS_TEFL_Pos      (25U)\r\n#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */\r\n#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */\r\n\r\n/*****************  Bit definition for FDCAN_TXEFA register  *********************/\r\n#define FDCAN_TXEFA_EFAI_Pos      (0U)\r\n#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */\r\n#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */\r\n\r\n/*****************  Bit definition for FDCAN_TTTMC register  *********************/\r\n#define FDCAN_TTTMC_TMSA_Pos      (2U)\r\n#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */\r\n#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */\r\n#define FDCAN_TTTMC_TME_Pos       (16U)\r\n#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */\r\n#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */\r\n\r\n/*****************  Bit definition for FDCAN_TTRMC register  *********************/\r\n#define FDCAN_TTRMC_RID_Pos       (0U)\r\n#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */\r\n#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */\r\n#define FDCAN_TTRMC_XTD_Pos       (30U)\r\n#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */\r\n#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */\r\n#define FDCAN_TTRMC_RMPS_Pos      (31U)\r\n#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */\r\n\r\n/*****************  Bit definition for FDCAN_TTOCF register  *********************/\r\n#define FDCAN_TTOCF_OM_Pos        (0U)\r\n#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */\r\n#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */\r\n#define FDCAN_TTOCF_GEN_Pos       (3U)\r\n#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */\r\n#define FDCAN_TTOCF_TM_Pos        (4U)\r\n#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */\r\n#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */\r\n#define FDCAN_TTOCF_LDSDL_Pos     (5U)\r\n#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */\r\n#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */\r\n#define FDCAN_TTOCF_IRTO_Pos      (8U)\r\n#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */\r\n#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */\r\n#define FDCAN_TTOCF_EECS_Pos      (15U)\r\n#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */\r\n#define FDCAN_TTOCF_AWL_Pos       (16U)\r\n#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */\r\n#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */\r\n#define FDCAN_TTOCF_EGTF_Pos      (24U)\r\n#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */\r\n#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */\r\n#define FDCAN_TTOCF_ECC_Pos       (25U)\r\n#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */\r\n#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */\r\n#define FDCAN_TTOCF_EVTP_Pos      (26U)\r\n#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */\r\n#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */\r\n\r\n/*****************  Bit definition for FDCAN_TTMLM register  *********************/\r\n#define FDCAN_TTMLM_CCM_Pos       (0U)\r\n#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */\r\n#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */\r\n#define FDCAN_TTMLM_CSS_Pos       (6U)\r\n#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */\r\n#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */\r\n#define FDCAN_TTMLM_TXEW_Pos      (8U)\r\n#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */\r\n#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */\r\n#define FDCAN_TTMLM_ENTT_Pos      (16U)\r\n#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */\r\n#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */\r\n\r\n/*****************  Bit definition for FDCAN_TURCF register  *********************/\r\n#define FDCAN_TURCF_NCL_Pos       (0U)\r\n#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */\r\n#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */\r\n#define FDCAN_TURCF_DC_Pos        (16U)\r\n#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */\r\n#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */\r\n#define FDCAN_TURCF_ELT_Pos       (31U)\r\n#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */\r\n#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */\r\n\r\n/*****************  Bit definition for FDCAN_TTOCN register  ********************/\r\n#define FDCAN_TTOCN_SGT_Pos       (0U)\r\n#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */\r\n#define FDCAN_TTOCN_ECS_Pos       (1U)\r\n#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */\r\n#define FDCAN_TTOCN_SWP_Pos       (2U)\r\n#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */\r\n#define FDCAN_TTOCN_SWS_Pos       (3U)\r\n#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */\r\n#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */\r\n#define FDCAN_TTOCN_RTIE_Pos      (5U)\r\n#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */\r\n#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */\r\n#define FDCAN_TTOCN_TMC_Pos       (6U)\r\n#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */\r\n#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */\r\n#define FDCAN_TTOCN_TTIE_Pos      (8U)\r\n#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */\r\n#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */\r\n#define FDCAN_TTOCN_GCS_Pos       (9U)\r\n#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */\r\n#define FDCAN_TTOCN_FGP_Pos       (10U)\r\n#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */\r\n#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */\r\n#define FDCAN_TTOCN_TMG_Pos       (11U)\r\n#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */\r\n#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */\r\n#define FDCAN_TTOCN_NIG_Pos       (12U)\r\n#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */\r\n#define FDCAN_TTOCN_ESCN_Pos      (13U)\r\n#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */\r\n#define FDCAN_TTOCN_LCKC_Pos      (15U)\r\n#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */\r\n\r\n/*****************  Bit definition for FDCAN_TTGTP register  ********************/\r\n#define FDCAN_TTGTP_TP_Pos        (0U)\r\n#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */\r\n#define FDCAN_TTGTP_CTP_Pos       (16U)\r\n#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */\r\n#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */\r\n\r\n/*****************  Bit definition for FDCAN_TTTMK register  ********************/\r\n#define FDCAN_TTTMK_TM_Pos        (0U)\r\n#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */\r\n#define FDCAN_TTTMK_TICC_Pos      (16U)\r\n#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */\r\n#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */\r\n#define FDCAN_TTTMK_LCKM_Pos      (31U)\r\n#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */\r\n#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */\r\n\r\n/*****************  Bit definition for FDCAN_TTIR register  ********************/\r\n#define FDCAN_TTIR_SBC_Pos        (0U)\r\n#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */\r\n#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */\r\n#define FDCAN_TTIR_SMC_Pos        (1U)\r\n#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */\r\n#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */\r\n#define FDCAN_TTIR_CSM_Pos        (2U)\r\n#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */\r\n#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */\r\n#define FDCAN_TTIR_SOG_Pos        (3U)\r\n#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */\r\n#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */\r\n#define FDCAN_TTIR_RTMI_Pos       (4U)\r\n#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */\r\n#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */\r\n#define FDCAN_TTIR_TTMI_Pos       (5U)\r\n#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */\r\n#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */\r\n#define FDCAN_TTIR_SWE_Pos        (6U)\r\n#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */\r\n#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */\r\n#define FDCAN_TTIR_GTW_Pos        (7U)\r\n#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */\r\n#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */\r\n#define FDCAN_TTIR_GTD_Pos        (8U)\r\n#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */\r\n#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */\r\n#define FDCAN_TTIR_GTE_Pos        (9U)\r\n#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */\r\n#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */\r\n#define FDCAN_TTIR_TXU_Pos        (10U)\r\n#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */\r\n#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */\r\n#define FDCAN_TTIR_TXO_Pos        (11U)\r\n#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */\r\n#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */\r\n#define FDCAN_TTIR_SE1_Pos        (12U)\r\n#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */\r\n#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */\r\n#define FDCAN_TTIR_SE2_Pos        (13U)\r\n#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */\r\n#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */\r\n#define FDCAN_TTIR_ELC_Pos        (14U)\r\n#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */\r\n#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */\r\n#define FDCAN_TTIR_IWT_Pos        (15U)\r\n#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */\r\n#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */\r\n#define FDCAN_TTIR_WT_Pos         (16U)\r\n#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */\r\n#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */\r\n#define FDCAN_TTIR_AW_Pos         (17U)\r\n#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */\r\n#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */\r\n#define FDCAN_TTIR_CER_Pos        (18U)\r\n#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */\r\n#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */\r\n\r\n/*****************  Bit definition for FDCAN_TTIE register  ********************/\r\n#define FDCAN_TTIE_SBCE_Pos       (0U)\r\n#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */\r\n#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */\r\n#define FDCAN_TTIE_SMCE_Pos       (1U)\r\n#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */\r\n#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */\r\n#define FDCAN_TTIE_CSME_Pos       (2U)\r\n#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */\r\n#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */\r\n#define FDCAN_TTIE_SOGE_Pos       (3U)\r\n#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */\r\n#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */\r\n#define FDCAN_TTIE_RTMIE_Pos      (4U)\r\n#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */\r\n#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */\r\n#define FDCAN_TTIE_TTMIE_Pos      (5U)\r\n#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */\r\n#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */\r\n#define FDCAN_TTIE_SWEE_Pos       (6U)\r\n#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */\r\n#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */\r\n#define FDCAN_TTIE_GTWE_Pos       (7U)\r\n#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */\r\n#define FDCAN_TTIE_GTDE_Pos       (8U)\r\n#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */\r\n#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */\r\n#define FDCAN_TTIE_GTEE_Pos       (9U)\r\n#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */\r\n#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */\r\n#define FDCAN_TTIE_TXUE_Pos       (10U)\r\n#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */\r\n#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */\r\n#define FDCAN_TTIE_TXOE_Pos       (11U)\r\n#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */\r\n#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */\r\n#define FDCAN_TTIE_SE1E_Pos       (12U)\r\n#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */\r\n#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */\r\n#define FDCAN_TTIE_SE2E_Pos       (13U)\r\n#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */\r\n#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */\r\n#define FDCAN_TTIE_ELCE_Pos       (14U)\r\n#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */\r\n#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */\r\n#define FDCAN_TTIE_IWTE_Pos       (15U)\r\n#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */\r\n#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */\r\n#define FDCAN_TTIE_WTE_Pos        (16U)\r\n#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */\r\n#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */\r\n#define FDCAN_TTIE_AWE_Pos        (17U)\r\n#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */\r\n#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */\r\n#define FDCAN_TTIE_CERE_Pos       (18U)\r\n#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */\r\n#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */\r\n\r\n/*****************  Bit definition for FDCAN_TTILS register  ********************/\r\n#define FDCAN_TTILS_SBCS_Pos      (0U)\r\n#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */\r\n#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */\r\n#define FDCAN_TTILS_SMCS_Pos      (1U)\r\n#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */\r\n#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */\r\n#define FDCAN_TTILS_CSMS_Pos      (2U)\r\n#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */\r\n#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */\r\n#define FDCAN_TTILS_SOGS_Pos      (3U)\r\n#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */\r\n#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */\r\n#define FDCAN_TTILS_RTMIS_Pos     (4U)\r\n#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */\r\n#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */\r\n#define FDCAN_TTILS_TTMIS_Pos     (5U)\r\n#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */\r\n#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */\r\n#define FDCAN_TTILS_SWES_Pos      (6U)\r\n#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */\r\n#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */\r\n#define FDCAN_TTILS_GTWS_Pos      (7U)\r\n#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */\r\n#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */\r\n#define FDCAN_TTILS_GTDS_Pos      (8U)\r\n#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */\r\n#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */\r\n#define FDCAN_TTILS_GTES_Pos      (9U)\r\n#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */\r\n#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */\r\n#define FDCAN_TTILS_TXUS_Pos      (10U)\r\n#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */\r\n#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */\r\n#define FDCAN_TTILS_TXOS_Pos      (11U)\r\n#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */\r\n#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */\r\n#define FDCAN_TTILS_SE1S_Pos      (12U)\r\n#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */\r\n#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */\r\n#define FDCAN_TTILS_SE2S_Pos      (13U)\r\n#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */\r\n#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */\r\n#define FDCAN_TTILS_ELCS_Pos      (14U)\r\n#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */\r\n#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */\r\n#define FDCAN_TTILS_IWTS_Pos      (15U)\r\n#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */\r\n#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */\r\n#define FDCAN_TTILS_WTS_Pos       (16U)\r\n#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */\r\n#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */\r\n#define FDCAN_TTILS_AWS_Pos       (17U)\r\n#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */\r\n#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */\r\n#define FDCAN_TTILS_CERS_Pos      (18U)\r\n#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */\r\n#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */\r\n\r\n/*****************  Bit definition for FDCAN_TTOST register  ********************/\r\n#define FDCAN_TTOST_EL_Pos        (0U)\r\n#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */\r\n#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */\r\n#define FDCAN_TTOST_MS_Pos        (2U)\r\n#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */\r\n#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */\r\n#define FDCAN_TTOST_SYS_Pos       (4U)\r\n#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */\r\n#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */\r\n#define FDCAN_TTOST_QGTP_Pos      (6U)\r\n#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */\r\n#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */\r\n#define FDCAN_TTOST_QCS_Pos       (7U)\r\n#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */\r\n#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */\r\n#define FDCAN_TTOST_RTO_Pos       (8U)\r\n#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */\r\n#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */\r\n#define FDCAN_TTOST_WGTD_Pos      (22U)\r\n#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */\r\n#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */\r\n#define FDCAN_TTOST_GFI_Pos       (23U)\r\n#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */\r\n#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */\r\n#define FDCAN_TTOST_TMP_Pos       (24U)\r\n#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */\r\n#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */\r\n#define FDCAN_TTOST_GSI_Pos       (27U)\r\n#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */\r\n#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */\r\n#define FDCAN_TTOST_WFE_Pos       (28U)\r\n#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */\r\n#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */\r\n#define FDCAN_TTOST_AWE_Pos       (29U)\r\n#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */\r\n#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */\r\n#define FDCAN_TTOST_WECS_Pos      (30U)\r\n#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */\r\n#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */\r\n#define FDCAN_TTOST_SPL_Pos       (31U)\r\n#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */\r\n#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */\r\n\r\n/*****************  Bit definition for FDCAN_TURNA register  ********************/\r\n#define FDCAN_TURNA_NAV_Pos       (0U)\r\n#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */\r\n#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */\r\n\r\n/*****************  Bit definition for FDCAN_TTLGT register  ********************/\r\n#define FDCAN_TTLGT_LT_Pos        (0U)\r\n#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */\r\n#define FDCAN_TTLGT_GT_Pos        (16U)\r\n#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */\r\n#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */\r\n\r\n/*****************  Bit definition for FDCAN_TTCTC register  ********************/\r\n#define FDCAN_TTCTC_CT_Pos        (0U)\r\n#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */\r\n#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */\r\n#define FDCAN_TTCTC_CC_Pos        (16U)\r\n#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */\r\n#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */\r\n\r\n/*****************  Bit definition for FDCAN_TTCPT register  ********************/\r\n#define FDCAN_TTCPT_CCV_Pos       (0U)\r\n#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */\r\n#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */\r\n#define FDCAN_TTCPT_SWV_Pos       (16U)\r\n#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */\r\n#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */\r\n\r\n/*****************  Bit definition for FDCAN_TTCSM register  ********************/\r\n#define FDCAN_TTCSM_CSM_Pos       (0U)\r\n#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */\r\n#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */\r\n\r\n/*****************  Bit definition for FDCAN_TTTS register  *********************/\r\n#define FDCAN_TTTS_SWTSEL_Pos     (0U)\r\n#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */\r\n#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */\r\n#define FDCAN_TTTS_EVTSEL_Pos     (4U)\r\n#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */\r\n#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */\r\n\r\n/********************************************************************************/\r\n/*                                                                              */\r\n/*                      FDCANCCU (Clock Calibration unit)                       */\r\n/*                                                                              */\r\n/********************************************************************************/\r\n\r\n/*****************  Bit definition for FDCANCCU_CREL register  ******************/\r\n#define FDCANCCU_CREL_DAY_Pos        (0U)\r\n#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */\r\n#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */\r\n#define FDCANCCU_CREL_MON_Pos        (8U)\r\n#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */\r\n#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */\r\n#define FDCANCCU_CREL_YEAR_Pos       (16U)\r\n#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */\r\n#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */\r\n#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)\r\n#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */\r\n#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */\r\n#define FDCANCCU_CREL_STEP_Pos       (24U)\r\n#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */\r\n#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */\r\n#define FDCANCCU_CREL_REL_Pos        (28U)\r\n#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */\r\n#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */\r\n\r\n/*****************  Bit definition for FDCANCCU_CCFG register  ******************/\r\n#define FDCANCCU_CCFG_TQBT_Pos       (0U)\r\n#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */\r\n#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */\r\n#define FDCANCCU_CCFG_BCC_Pos        (6U)\r\n#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */\r\n#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */\r\n#define FDCANCCU_CCFG_CFL_Pos        (7U)\r\n#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */\r\n#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */\r\n#define FDCANCCU_CCFG_OCPM_Pos       (8U)\r\n#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */\r\n#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */\r\n#define FDCANCCU_CCFG_CDIV_Pos       (16U)\r\n#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */\r\n#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */\r\n#define FDCANCCU_CCFG_SWR_Pos        (31U)\r\n#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */\r\n#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */\r\n\r\n/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/\r\n#define FDCANCCU_CSTAT_OCPC_Pos      (0U)\r\n#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */\r\n#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */\r\n#define FDCANCCU_CSTAT_TQC_Pos       (18U)\r\n#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */\r\n#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */\r\n#define FDCANCCU_CSTAT_CALS_Pos      (30U)\r\n#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */\r\n#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */\r\n\r\n/******************  Bit definition for FDCANCCU_CWD register  ******************/\r\n#define FDCANCCU_CWD_WDC_Pos         (0U)\r\n#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */\r\n#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */\r\n#define FDCANCCU_CWD_WDV_Pos         (16U)\r\n#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */\r\n#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */\r\n\r\n/******************  Bit definition for FDCANCCU_IR register  *******************/\r\n#define FDCANCCU_IR_CWE_Pos          (0U)\r\n#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */\r\n#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */\r\n#define FDCANCCU_IR_CSC_Pos          (1U)\r\n#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */\r\n#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */\r\n\r\n/******************  Bit definition for FDCANCCU_IE register  *******************/\r\n#define FDCANCCU_IE_CWEE_Pos         (0U)\r\n#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */\r\n#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */\r\n#define FDCANCCU_IE_CSCE_Pos         (1U)\r\n#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */\r\n#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          HDMI-CEC (CEC)                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for CEC_CR register  *********************/\r\n#define CEC_CR_CECEN_Pos         (0U)\r\n#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */\r\n#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */\r\n#define CEC_CR_TXSOM_Pos         (1U)\r\n#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */\r\n#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */\r\n#define CEC_CR_TXEOM_Pos         (2U)\r\n#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */\r\n#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */\r\n\r\n/*******************  Bit definition for CEC_CFGR register  *******************/\r\n#define CEC_CFGR_SFT_Pos         (0U)\r\n#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */\r\n#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */\r\n#define CEC_CFGR_RXTOL_Pos       (3U)\r\n#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */\r\n#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */\r\n#define CEC_CFGR_BRESTP_Pos      (4U)\r\n#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */\r\n#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */\r\n#define CEC_CFGR_BREGEN_Pos      (5U)\r\n#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */\r\n#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */\r\n#define CEC_CFGR_LBPEGEN_Pos     (6U)\r\n#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */\r\n#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */\r\n#define CEC_CFGR_SFTOPT_Pos      (8U)\r\n#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */\r\n#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */\r\n#define CEC_CFGR_BRDNOGEN_Pos    (7U)\r\n#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */\r\n#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */\r\n#define CEC_CFGR_OAR_Pos         (16U)\r\n#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */\r\n#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */\r\n#define CEC_CFGR_LSTN_Pos        (31U)\r\n#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */\r\n#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */\r\n\r\n/*******************  Bit definition for CEC_TXDR register  *******************/\r\n#define CEC_TXDR_TXD_Pos         (0U)\r\n#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */\r\n#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */\r\n\r\n/*******************  Bit definition for CEC_RXDR register  *******************/\r\n#define CEC_RXDR_RXD_Pos         (0U)\r\n#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */\r\n#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */\r\n\r\n/*******************  Bit definition for CEC_ISR register  ********************/\r\n#define CEC_ISR_RXBR_Pos         (0U)\r\n#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */\r\n#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */\r\n#define CEC_ISR_RXEND_Pos        (1U)\r\n#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */\r\n#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */\r\n#define CEC_ISR_RXOVR_Pos        (2U)\r\n#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */\r\n#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */\r\n#define CEC_ISR_BRE_Pos          (3U)\r\n#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */\r\n#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */\r\n#define CEC_ISR_SBPE_Pos         (4U)\r\n#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */\r\n#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */\r\n#define CEC_ISR_LBPE_Pos         (5U)\r\n#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */\r\n#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */\r\n#define CEC_ISR_RXACKE_Pos       (6U)\r\n#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */\r\n#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */\r\n#define CEC_ISR_ARBLST_Pos       (7U)\r\n#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */\r\n#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */\r\n#define CEC_ISR_TXBR_Pos         (8U)\r\n#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */\r\n#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */\r\n#define CEC_ISR_TXEND_Pos        (9U)\r\n#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */\r\n#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */\r\n#define CEC_ISR_TXUDR_Pos        (10U)\r\n#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */\r\n#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */\r\n#define CEC_ISR_TXERR_Pos        (11U)\r\n#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */\r\n#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */\r\n#define CEC_ISR_TXACKE_Pos       (12U)\r\n#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */\r\n#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */\r\n\r\n/*******************  Bit definition for CEC_IER register  ********************/\r\n#define CEC_IER_RXBRIE_Pos       (0U)\r\n#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */\r\n#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */\r\n#define CEC_IER_RXENDIE_Pos      (1U)\r\n#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */\r\n#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */\r\n#define CEC_IER_RXOVRIE_Pos      (2U)\r\n#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */\r\n#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */\r\n#define CEC_IER_BREIE_Pos        (3U)\r\n#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */\r\n#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */\r\n#define CEC_IER_SBPEIE_Pos       (4U)\r\n#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */\r\n#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */\r\n#define CEC_IER_LBPEIE_Pos       (5U)\r\n#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */\r\n#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */\r\n#define CEC_IER_RXACKEIE_Pos     (6U)\r\n#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */\r\n#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */\r\n#define CEC_IER_ARBLSTIE_Pos     (7U)\r\n#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */\r\n#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */\r\n#define CEC_IER_TXBRIE_Pos       (8U)\r\n#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */\r\n#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */\r\n#define CEC_IER_TXENDIE_Pos      (9U)\r\n#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */\r\n#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */\r\n#define CEC_IER_TXUDRIE_Pos      (10U)\r\n#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */\r\n#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */\r\n#define CEC_IER_TXERRIE_Pos      (11U)\r\n#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */\r\n#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */\r\n#define CEC_IER_TXACKEIE_Pos     (12U)\r\n#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */\r\n#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CORDIC calculation unit                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for CORDIC_CSR register  *****************/\r\n#define CORDIC_CSR_FUNC_Pos      (0U)\r\n#define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */\r\n#define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */\r\n#define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */\r\n#define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */\r\n#define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */\r\n#define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */\r\n#define CORDIC_CSR_PRECISION_Pos (4U)\r\n#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */\r\n#define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */\r\n#define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */\r\n#define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */\r\n#define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */\r\n#define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */\r\n#define CORDIC_CSR_SCALE_Pos     (8U)\r\n#define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */\r\n#define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */\r\n#define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */\r\n#define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */\r\n#define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */\r\n#define CORDIC_CSR_IEN_Pos       (16U)\r\n#define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */\r\n#define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */\r\n#define CORDIC_CSR_DMAREN_Pos    (17U)\r\n#define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */\r\n#define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */\r\n#define CORDIC_CSR_DMAWEN_Pos    (18U)\r\n#define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */\r\n#define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */\r\n#define CORDIC_CSR_NRES_Pos      (19U)\r\n#define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */\r\n#define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */\r\n#define CORDIC_CSR_NARGS_Pos     (20U)\r\n#define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */\r\n#define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */\r\n#define CORDIC_CSR_RESSIZE_Pos   (21U)\r\n#define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */\r\n#define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */\r\n#define CORDIC_CSR_ARGSIZE_Pos   (22U)\r\n#define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */\r\n#define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */\r\n#define CORDIC_CSR_RRDY_Pos      (31U)\r\n#define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */\r\n#define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */\r\n\r\n/*******************  Bit definition for CORDIC_WDATA register  ***************/\r\n#define CORDIC_WDATA_ARG_Pos     (0U)\r\n#define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */\r\n#define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */\r\n\r\n/*******************  Bit definition for CORDIC_RDATA register  ***************/\r\n#define CORDIC_RDATA_RES_Pos     (0U)\r\n#define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */\r\n#define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CRC calculation unit                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for CRC_DR register  *********************/\r\n#define CRC_DR_DR_Pos            (0U)\r\n#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */\r\n#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\r\n\r\n/*******************  Bit definition for CRC_IDR register  ********************/\r\n#define CRC_IDR_IDR_Pos          (0U)\r\n#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */\r\n#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */\r\n\r\n/********************  Bit definition for CRC_CR register  ********************/\r\n#define CRC_CR_RESET_Pos         (0U)\r\n#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */\r\n#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\r\n#define CRC_CR_POLYSIZE_Pos      (3U)\r\n#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */\r\n#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */\r\n#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */\r\n#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */\r\n#define CRC_CR_REV_IN_Pos        (5U)\r\n#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */\r\n#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */\r\n#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */\r\n#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */\r\n#define CRC_CR_REV_OUT_Pos       (7U)\r\n#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */\r\n#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */\r\n\r\n/*******************  Bit definition for CRC_INIT register  *******************/\r\n#define CRC_INIT_INIT_Pos        (0U)\r\n#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */\r\n#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */\r\n\r\n/*******************  Bit definition for CRC_POL register  ********************/\r\n#define CRC_POL_POL_Pos          (0U)\r\n#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */\r\n#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CRS Clock Recovery System                         */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for CRS_CR register  *********************/\r\n#define CRS_CR_SYNCOKIE_Pos       (0U)\r\n#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */\r\n#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */\r\n#define CRS_CR_SYNCWARNIE_Pos     (1U)\r\n#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */\r\n#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */\r\n#define CRS_CR_ERRIE_Pos          (2U)\r\n#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */\r\n#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */\r\n#define CRS_CR_ESYNCIE_Pos        (3U)\r\n#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */\r\n#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */\r\n#define CRS_CR_CEN_Pos            (5U)\r\n#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */\r\n#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */\r\n#define CRS_CR_AUTOTRIMEN_Pos     (6U)\r\n#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */\r\n#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */\r\n#define CRS_CR_SWSYNC_Pos         (7U)\r\n#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */\r\n#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */\r\n#define CRS_CR_TRIM_Pos           (8U)\r\n#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */\r\n#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */\r\n\r\n/*******************  Bit definition for CRS_CFGR register  *********************/\r\n#define CRS_CFGR_RELOAD_Pos       (0U)\r\n#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */\r\n#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */\r\n#define CRS_CFGR_FELIM_Pos        (16U)\r\n#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */\r\n#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */\r\n\r\n#define CRS_CFGR_SYNCDIV_Pos      (24U)\r\n#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */\r\n#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */\r\n#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */\r\n#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */\r\n#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */\r\n\r\n#define CRS_CFGR_SYNCSRC_Pos      (28U)\r\n#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */\r\n#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */\r\n#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */\r\n#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */\r\n\r\n#define CRS_CFGR_SYNCPOL_Pos      (31U)\r\n#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */\r\n#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */\r\n\r\n/*******************  Bit definition for CRS_ISR register  *********************/\r\n#define CRS_ISR_SYNCOKF_Pos       (0U)\r\n#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */\r\n#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */\r\n#define CRS_ISR_SYNCWARNF_Pos     (1U)\r\n#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */\r\n#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */\r\n#define CRS_ISR_ERRF_Pos          (2U)\r\n#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */\r\n#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */\r\n#define CRS_ISR_ESYNCF_Pos        (3U)\r\n#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */\r\n#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */\r\n#define CRS_ISR_SYNCERR_Pos       (8U)\r\n#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */\r\n#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */\r\n#define CRS_ISR_SYNCMISS_Pos      (9U)\r\n#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */\r\n#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */\r\n#define CRS_ISR_TRIMOVF_Pos       (10U)\r\n#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */\r\n#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */\r\n#define CRS_ISR_FEDIR_Pos         (15U)\r\n#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */\r\n#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */\r\n#define CRS_ISR_FECAP_Pos         (16U)\r\n#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */\r\n#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */\r\n\r\n/*******************  Bit definition for CRS_ICR register  *********************/\r\n#define CRS_ICR_SYNCOKC_Pos       (0U)\r\n#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */\r\n#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */\r\n#define CRS_ICR_SYNCWARNC_Pos     (1U)\r\n#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */\r\n#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */\r\n#define CRS_ICR_ERRC_Pos          (2U)\r\n#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */\r\n#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */\r\n#define CRS_ICR_ESYNCC_Pos        (3U)\r\n#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */\r\n#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            Crypto Processor                                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************************  CRYP VER  **********************************/\r\n#define  CRYP_VER_2_2\r\n/******************* Bits definition for CRYP_CR register  ********************/\r\n#define CRYP_CR_ALGODIR_Pos              (2U)\r\n#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */\r\n#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk\r\n\r\n#define CRYP_CR_ALGOMODE_Pos             (3U)\r\n#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */\r\n#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk\r\n#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */\r\n#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */\r\n#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */\r\n#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */\r\n#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk\r\n#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)\r\n#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */\r\n#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk\r\n#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */\r\n#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk\r\n#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)\r\n#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */\r\n#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk\r\n#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */\r\n#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk\r\n#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)\r\n#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */\r\n#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk\r\n#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */\r\n#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk\r\n#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)\r\n#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */\r\n#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk\r\n#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)\r\n#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */\r\n#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk\r\n\r\n#define CRYP_CR_DATATYPE_Pos             (6U)\r\n#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */\r\n#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk\r\n#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */\r\n#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */\r\n#define CRYP_CR_KEYSIZE_Pos              (8U)\r\n#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */\r\n#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk\r\n#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */\r\n#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */\r\n#define CRYP_CR_FFLUSH_Pos               (14U)\r\n#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */\r\n#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk\r\n#define CRYP_CR_CRYPEN_Pos               (15U)\r\n#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */\r\n#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk\r\n\r\n#define CRYP_CR_GCM_CCMPH_Pos            (16U)\r\n#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */\r\n#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk\r\n#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */\r\n#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */\r\n#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)\r\n#define CRYP_CR_NPBLB_Pos                (20U)\r\n#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */\r\n#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk\r\n\r\n/****************** Bits definition for CRYP_SR register  *********************/\r\n#define CRYP_SR_IFEM_Pos                 (0U)\r\n#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */\r\n#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk\r\n#define CRYP_SR_IFNF_Pos                 (1U)\r\n#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */\r\n#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk\r\n#define CRYP_SR_OFNE_Pos                 (2U)\r\n#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */\r\n#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk\r\n#define CRYP_SR_OFFU_Pos                 (3U)\r\n#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */\r\n#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk\r\n#define CRYP_SR_BUSY_Pos                 (4U)\r\n#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */\r\n#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk\r\n/****************** Bits definition for CRYP_DMACR register  ******************/\r\n#define CRYP_DMACR_DIEN_Pos              (0U)\r\n#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */\r\n#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk\r\n#define CRYP_DMACR_DOEN_Pos              (1U)\r\n#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */\r\n#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk\r\n/*****************  Bits definition for CRYP_IMSCR register  ******************/\r\n#define CRYP_IMSCR_INIM_Pos              (0U)\r\n#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */\r\n#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk\r\n#define CRYP_IMSCR_OUTIM_Pos             (1U)\r\n#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */\r\n#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk\r\n/****************** Bits definition for CRYP_RISR register  *******************/\r\n#define CRYP_RISR_INRIS_Pos              (0U)\r\n#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */\r\n#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk\r\n#define CRYP_RISR_OUTRIS_Pos             (1U)\r\n#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */\r\n#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk\r\n/****************** Bits definition for CRYP_MISR register  *******************/\r\n#define CRYP_MISR_INMIS_Pos              (0U)\r\n#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */\r\n#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk\r\n#define CRYP_MISR_OUTMIS_Pos             (1U)\r\n#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */\r\n#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Digital to Analog Converter                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DAC_CR register  ********************/\r\n#define DAC_CR_EN1_Pos              (0U)\r\n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */\r\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\r\n#define DAC_CR_TEN1_Pos             (1U)\r\n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */\r\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\r\n\r\n#define DAC_CR_TSEL1_Pos            (2U)\r\n#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */\r\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */\r\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\r\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\r\n#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\r\n\r\n\r\n#define DAC_CR_WAVE1_Pos            (6U)\r\n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */\r\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\r\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\r\n\r\n#define DAC_CR_MAMP1_Pos            (8U)\r\n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */\r\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\r\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\r\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\r\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\r\n\r\n#define DAC_CR_DMAEN1_Pos           (12U)\r\n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */\r\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\r\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\r\n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */\r\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/\r\n#define DAC_CR_CEN1_Pos             (14U)\r\n#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */\r\n#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/\r\n\r\n#define DAC_CR_EN2_Pos              (16U)\r\n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */\r\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\r\n#define DAC_CR_TEN2_Pos             (17U)\r\n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */\r\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\r\n\r\n#define DAC_CR_TSEL2_Pos            (18U)\r\n#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */\r\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */\r\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\r\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\r\n#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\r\n\r\n\r\n#define DAC_CR_WAVE2_Pos            (22U)\r\n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */\r\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\r\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\r\n\r\n#define DAC_CR_MAMP2_Pos            (24U)\r\n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */\r\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\r\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\r\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\r\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\r\n\r\n#define DAC_CR_DMAEN2_Pos           (28U)\r\n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */\r\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\r\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\r\n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */\r\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/\r\n#define DAC_CR_CEN2_Pos             (30U)\r\n#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */\r\n#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/\r\n\r\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\r\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */\r\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\r\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\r\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */\r\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\r\n\r\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\r\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */\r\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\r\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\r\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\r\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */\r\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\r\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */\r\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\r\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */\r\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\r\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\r\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */\r\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\r\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\r\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */\r\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\r\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */\r\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\r\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\r\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */\r\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\r\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */\r\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8RD register  ******************/\r\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\r\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */\r\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\r\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */\r\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*******************  Bit definition for DAC_DOR1 register  *******************/\r\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\r\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */\r\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\r\n\r\n/*******************  Bit definition for DAC_DOR2 register  *******************/\r\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\r\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */\r\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\r\n\r\n/********************  Bit definition for DAC_SR register  ********************/\r\n#define DAC_SR_DMAUDR1_Pos          (13U)\r\n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */\r\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\r\n#define DAC_SR_CAL_FLAG1_Pos        (14U)\r\n#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */\r\n#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */\r\n#define DAC_SR_BWST1_Pos            (15U)\r\n#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */\r\n#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */\r\n\r\n#define DAC_SR_DMAUDR2_Pos          (29U)\r\n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */\r\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\r\n#define DAC_SR_CAL_FLAG2_Pos        (30U)\r\n#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */\r\n#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */\r\n#define DAC_SR_BWST2_Pos            (31U)\r\n#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */\r\n#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */\r\n\r\n/*******************  Bit definition for DAC_CCR register  ********************/\r\n#define DAC_CCR_OTRIM1_Pos          (0U)\r\n#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */\r\n#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */\r\n#define DAC_CCR_OTRIM2_Pos          (16U)\r\n#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */\r\n#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */\r\n\r\n/*******************  Bit definition for DAC_MCR register  *******************/\r\n#define DAC_MCR_MODE1_Pos           (0U)\r\n#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */\r\n#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */\r\n#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */\r\n#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */\r\n#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */\r\n\r\n#define DAC_MCR_MODE2_Pos           (16U)\r\n#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */\r\n#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */\r\n#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */\r\n#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */\r\n#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */\r\n\r\n/******************  Bit definition for DAC_SHSR1 register  ******************/\r\n#define DAC_SHSR1_TSAMPLE1_Pos      (0U)\r\n#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */\r\n#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */\r\n\r\n/******************  Bit definition for DAC_SHSR2 register  ******************/\r\n#define DAC_SHSR2_TSAMPLE2_Pos      (0U)\r\n#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */\r\n#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */\r\n\r\n/******************  Bit definition for DAC_SHHR register  ******************/\r\n#define DAC_SHHR_THOLD1_Pos         (0U)\r\n#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */\r\n#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */\r\n#define DAC_SHHR_THOLD2_Pos         (16U)\r\n#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */\r\n#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */\r\n\r\n/******************  Bit definition for DAC_SHRR register  ******************/\r\n#define DAC_SHRR_TREFRESH1_Pos      (0U)\r\n#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */\r\n#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */\r\n#define DAC_SHRR_TREFRESH2_Pos      (16U)\r\n#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */\r\n#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    DCMI                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DCMI_CR register  ******************/\r\n#define DCMI_CR_CAPTURE_Pos        (0U)\r\n#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */\r\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk\r\n#define DCMI_CR_CM_Pos             (1U)\r\n#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */\r\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk\r\n#define DCMI_CR_CROP_Pos           (2U)\r\n#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */\r\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk\r\n#define DCMI_CR_JPEG_Pos           (3U)\r\n#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */\r\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk\r\n#define DCMI_CR_ESS_Pos            (4U)\r\n#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */\r\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk\r\n#define DCMI_CR_PCKPOL_Pos         (5U)\r\n#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */\r\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk\r\n#define DCMI_CR_HSPOL_Pos          (6U)\r\n#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */\r\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk\r\n#define DCMI_CR_VSPOL_Pos          (7U)\r\n#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */\r\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk\r\n#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)\r\n#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)\r\n#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)\r\n#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)\r\n#define DCMI_CR_CRE_Pos            (12U)\r\n#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */\r\n#define DCMI_CR_CRE                DCMI_CR_CRE_Msk\r\n#define DCMI_CR_ENABLE_Pos         (14U)\r\n#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */\r\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk\r\n#define DCMI_CR_BSM_Pos            (16U)\r\n#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */\r\n#define DCMI_CR_BSM                DCMI_CR_BSM_Msk\r\n#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */\r\n#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */\r\n#define DCMI_CR_OEBS_Pos           (18U)\r\n#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */\r\n#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk\r\n#define DCMI_CR_LSM_Pos            (19U)\r\n#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */\r\n#define DCMI_CR_LSM                DCMI_CR_LSM_Msk\r\n#define DCMI_CR_OELS_Pos           (20U)\r\n#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */\r\n#define DCMI_CR_OELS               DCMI_CR_OELS_Msk\r\n\r\n/********************  Bits definition for DCMI_SR register  ******************/\r\n#define DCMI_SR_HSYNC_Pos          (0U)\r\n#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */\r\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk\r\n#define DCMI_SR_VSYNC_Pos          (1U)\r\n#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */\r\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk\r\n#define DCMI_SR_FNE_Pos            (2U)\r\n#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */\r\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk\r\n\r\n/********************  Bits definition for DCMI_RIS register   ****************/\r\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)\r\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */\r\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk\r\n#define DCMI_RIS_OVR_RIS_Pos       (1U)\r\n#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */\r\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk\r\n#define DCMI_RIS_ERR_RIS_Pos       (2U)\r\n#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */\r\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk\r\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)\r\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */\r\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk\r\n#define DCMI_RIS_LINE_RIS_Pos      (4U)\r\n#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */\r\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk\r\n\r\n/********************  Bits definition for DCMI_IER register  *****************/\r\n#define DCMI_IER_FRAME_IE_Pos      (0U)\r\n#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */\r\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk\r\n#define DCMI_IER_OVR_IE_Pos        (1U)\r\n#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */\r\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk\r\n#define DCMI_IER_ERR_IE_Pos        (2U)\r\n#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */\r\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk\r\n#define DCMI_IER_VSYNC_IE_Pos      (3U)\r\n#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */\r\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk\r\n#define DCMI_IER_LINE_IE_Pos       (4U)\r\n#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */\r\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk\r\n\r\n\r\n/********************  Bits definition for DCMI_MIS register  *****************/\r\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)\r\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */\r\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk\r\n#define DCMI_MIS_OVR_MIS_Pos       (1U)\r\n#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */\r\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk\r\n#define DCMI_MIS_ERR_MIS_Pos       (2U)\r\n#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */\r\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk\r\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)\r\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */\r\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk\r\n#define DCMI_MIS_LINE_MIS_Pos      (4U)\r\n#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */\r\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk\r\n\r\n\r\n/********************  Bits definition for DCMI_ICR register  *****************/\r\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)\r\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */\r\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk\r\n#define DCMI_ICR_OVR_ISC_Pos       (1U)\r\n#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */\r\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk\r\n#define DCMI_ICR_ERR_ISC_Pos       (2U)\r\n#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */\r\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk\r\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)\r\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */\r\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk\r\n#define DCMI_ICR_LINE_ISC_Pos      (4U)\r\n#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */\r\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk\r\n\r\n\r\n/********************  Bits definition for DCMI_ESCR register  ******************/\r\n#define DCMI_ESCR_FSC_Pos          (0U)\r\n#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */\r\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk\r\n#define DCMI_ESCR_LSC_Pos          (8U)\r\n#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */\r\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk\r\n#define DCMI_ESCR_LEC_Pos          (16U)\r\n#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */\r\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk\r\n#define DCMI_ESCR_FEC_Pos          (24U)\r\n#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */\r\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk\r\n\r\n/********************  Bits definition for DCMI_ESUR register  ******************/\r\n#define DCMI_ESUR_FSU_Pos          (0U)\r\n#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */\r\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk\r\n#define DCMI_ESUR_LSU_Pos          (8U)\r\n#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */\r\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk\r\n#define DCMI_ESUR_LEU_Pos          (16U)\r\n#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */\r\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk\r\n#define DCMI_ESUR_FEU_Pos          (24U)\r\n#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */\r\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk\r\n\r\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\r\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)\r\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */\r\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk\r\n#define DCMI_CWSTRT_VST_Pos        (16U)\r\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */\r\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk\r\n\r\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\r\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)\r\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */\r\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk\r\n#define DCMI_CWSIZE_VLINE_Pos      (16U)\r\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */\r\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk\r\n\r\n/********************  Bits definition for DCMI_DR register  ******************/\r\n#define DCMI_DR_BYTE0_Pos          (0U)\r\n#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */\r\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk\r\n#define DCMI_DR_BYTE1_Pos          (8U)\r\n#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */\r\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk\r\n#define DCMI_DR_BYTE2_Pos          (16U)\r\n#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */\r\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk\r\n#define DCMI_DR_BYTE3_Pos          (24U)\r\n#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */\r\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                 Digital Filter for Sigma Delta Modulators                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/****************   DFSDM channel configuration registers  ********************/\r\n\r\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\r\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\r\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */\r\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\r\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\r\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */\r\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\r\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\r\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\r\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\r\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\r\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */\r\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\r\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\r\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\r\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\r\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */\r\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\r\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\r\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\r\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\r\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */\r\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\r\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\r\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */\r\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\r\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\r\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */\r\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\r\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\r\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */\r\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\r\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\r\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */\r\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\r\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\r\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\r\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\r\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */\r\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\r\n#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\r\n#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\r\n\r\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\r\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\r\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\r\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */\r\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\r\n\r\n/******************  Bit definition for DFSDM_CHAWSCDR register *****************/\r\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\r\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */\r\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\r\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\r\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\r\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */\r\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\r\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */\r\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\r\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */\r\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r\n\r\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\r\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\r\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */\r\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\r\n\r\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\r\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\r\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\r\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\r\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\r\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\r\n\r\n/************************   DFSDM module registers  ****************************/\r\n\r\n/********************  Bit definition for DFSDM_FLTCR1 register *******************/\r\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\r\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */\r\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\r\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\r\n#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */\r\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\r\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\r\n#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */\r\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\r\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\r\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */\r\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\r\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\r\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */\r\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\r\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\r\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */\r\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\r\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\r\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */\r\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\r\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\r\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */\r\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\r\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\r\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\r\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */\r\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */\r\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */\r\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */\r\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */\r\n#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */\r\n#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */\r\n\r\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\r\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */\r\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\r\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\r\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */\r\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\r\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\r\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */\r\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\r\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\r\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */\r\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\r\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\r\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */\r\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\r\n\r\n/********************  Bit definition for DFSDM_FLTCR2 register *******************/\r\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\r\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */\r\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\r\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\r\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */\r\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\r\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\r\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */\r\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\r\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\r\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */\r\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\r\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\r\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */\r\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\r\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\r\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */\r\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\r\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\r\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */\r\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\r\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\r\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */\r\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\r\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\r\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */\r\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\r\n\r\n/********************  Bit definition for DFSDM_FLTISR register *******************/\r\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\r\n#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */\r\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\r\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\r\n#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */\r\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\r\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\r\n#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */\r\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\r\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\r\n#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */\r\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\r\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\r\n#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */\r\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\r\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\r\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */\r\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\r\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\r\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */\r\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\r\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\r\n#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */\r\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\r\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\r\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */\r\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\r\n\r\n/********************  Bit definition for DFSDM_FLTICR register *******************/\r\n#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)\r\n#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */\r\n#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\r\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\r\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */\r\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\r\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\r\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */\r\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\r\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\r\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */\r\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\r\n\r\n/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/\r\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\r\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */\r\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\r\n\r\n/********************  Bit definition for DFSDM_FLTFCR register *******************/\r\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\r\n#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */\r\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\r\n#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\r\n#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\r\n#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\r\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\r\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */\r\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\r\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */\r\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r\n\r\n/******************  Bit definition for DFSDM_FLTJDATAR register *****************/\r\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\r\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\r\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\r\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\r\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\r\n\r\n/******************  Bit definition for DFSDM_FLTRDATAR register *****************/\r\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\r\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\r\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\r\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */\r\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\r\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\r\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\r\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWHTR register ******************/\r\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\r\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\r\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\r\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */\r\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWLTR register ******************/\r\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\r\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */\r\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\r\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */\r\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWSR register ******************/\r\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\r\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */\r\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\r\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */\r\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r\n\r\n/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/\r\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\r\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\r\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\r\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\r\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r\n\r\n/******************  Bit definition for DFSDM_FLTEXMAX register ******************/\r\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\r\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\r\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\r\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */\r\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r\n\r\n/******************  Bit definition for DFSDM_FLTEXMIN register ******************/\r\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\r\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\r\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\r\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\r\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */\r\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r\n\r\n/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/\r\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\r\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\r\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           BDMA Controller                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for BDMA_ISR register  ********************/\r\n#define BDMA_ISR_GIF0_Pos       (0U)\r\n#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */\r\n#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */\r\n#define BDMA_ISR_TCIF0_Pos      (1U)\r\n#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */\r\n#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF0_Pos      (2U)\r\n#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */\r\n#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */\r\n#define BDMA_ISR_TEIF0_Pos      (3U)\r\n#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */\r\n#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */\r\n#define BDMA_ISR_GIF1_Pos       (4U)\r\n#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */\r\n#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */\r\n#define BDMA_ISR_TCIF1_Pos      (5U)\r\n#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */\r\n#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF1_Pos      (6U)\r\n#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */\r\n#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */\r\n#define BDMA_ISR_TEIF1_Pos      (7U)\r\n#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */\r\n#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */\r\n#define BDMA_ISR_GIF2_Pos       (8U)\r\n#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */\r\n#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */\r\n#define BDMA_ISR_TCIF2_Pos      (9U)\r\n#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */\r\n#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF2_Pos      (10U)\r\n#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */\r\n#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */\r\n#define BDMA_ISR_TEIF2_Pos      (11U)\r\n#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */\r\n#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */\r\n#define BDMA_ISR_GIF3_Pos       (12U)\r\n#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */\r\n#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */\r\n#define BDMA_ISR_TCIF3_Pos      (13U)\r\n#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */\r\n#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF3_Pos      (14U)\r\n#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */\r\n#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */\r\n#define BDMA_ISR_TEIF3_Pos      (15U)\r\n#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */\r\n#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */\r\n#define BDMA_ISR_GIF4_Pos       (16U)\r\n#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */\r\n#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */\r\n#define BDMA_ISR_TCIF4_Pos      (17U)\r\n#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */\r\n#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF4_Pos      (18U)\r\n#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */\r\n#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */\r\n#define BDMA_ISR_TEIF4_Pos      (19U)\r\n#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */\r\n#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */\r\n#define BDMA_ISR_GIF5_Pos       (20U)\r\n#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */\r\n#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */\r\n#define BDMA_ISR_TCIF5_Pos      (21U)\r\n#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */\r\n#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF5_Pos      (22U)\r\n#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */\r\n#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */\r\n#define BDMA_ISR_TEIF5_Pos      (23U)\r\n#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */\r\n#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */\r\n#define BDMA_ISR_GIF6_Pos       (24U)\r\n#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */\r\n#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */\r\n#define BDMA_ISR_TCIF6_Pos      (25U)\r\n#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */\r\n#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF6_Pos      (26U)\r\n#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */\r\n#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */\r\n#define BDMA_ISR_TEIF6_Pos      (27U)\r\n#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */\r\n#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */\r\n#define BDMA_ISR_GIF7_Pos       (28U)\r\n#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */\r\n#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */\r\n#define BDMA_ISR_TCIF7_Pos      (29U)\r\n#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */\r\n#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */\r\n#define BDMA_ISR_HTIF7_Pos      (30U)\r\n#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */\r\n#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */\r\n#define BDMA_ISR_TEIF7_Pos      (31U)\r\n#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */\r\n#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */\r\n\r\n/*******************  Bit definition for BDMA_IFCR register  *******************/\r\n#define BDMA_IFCR_CGIF0_Pos     (0U)\r\n#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */\r\n#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */\r\n#define BDMA_IFCR_CTCIF0_Pos    (1U)\r\n#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */\r\n#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF0_Pos    (2U)\r\n#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */\r\n#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF0_Pos    (3U)\r\n#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */\r\n#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF1_Pos     (4U)\r\n#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */\r\n#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF1_Pos    (5U)\r\n#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */\r\n#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF1_Pos    (6U)\r\n#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */\r\n#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF1_Pos    (7U)\r\n#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */\r\n#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF2_Pos     (8U)\r\n#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */\r\n#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF2_Pos    (9U)\r\n#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */\r\n#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF2_Pos    (10U)\r\n#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */\r\n#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF2_Pos    (11U)\r\n#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */\r\n#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF3_Pos     (12U)\r\n#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */\r\n#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF3_Pos    (13U)\r\n#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */\r\n#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF3_Pos    (14U)\r\n#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */\r\n#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF3_Pos    (15U)\r\n#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */\r\n#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF4_Pos     (16U)\r\n#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */\r\n#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF4_Pos    (17U)\r\n#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */\r\n#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF4_Pos    (18U)\r\n#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */\r\n#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF4_Pos    (19U)\r\n#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */\r\n#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF5_Pos     (20U)\r\n#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */\r\n#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF5_Pos    (21U)\r\n#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */\r\n#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF5_Pos    (22U)\r\n#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */\r\n#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF5_Pos    (23U)\r\n#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */\r\n#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF6_Pos     (24U)\r\n#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */\r\n#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF6_Pos    (25U)\r\n#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */\r\n#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF6_Pos    (26U)\r\n#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */\r\n#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF6_Pos    (27U)\r\n#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */\r\n#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */\r\n#define BDMA_IFCR_CGIF7_Pos     (28U)\r\n#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */\r\n#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */\r\n#define BDMA_IFCR_CTCIF7_Pos    (29U)\r\n#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */\r\n#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */\r\n#define BDMA_IFCR_CHTIF7_Pos    (30U)\r\n#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */\r\n#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */\r\n#define BDMA_IFCR_CTEIF7_Pos    (31U)\r\n#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */\r\n#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */\r\n\r\n/*******************  Bit definition for BDMA_CCR register  ********************/\r\n#define BDMA_CCR_EN_Pos         (0U)\r\n#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */\r\n#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */\r\n#define BDMA_CCR_TCIE_Pos       (1U)\r\n#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */\r\n#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */\r\n#define BDMA_CCR_HTIE_Pos       (2U)\r\n#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */\r\n#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */\r\n#define BDMA_CCR_TEIE_Pos       (3U)\r\n#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */\r\n#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */\r\n#define BDMA_CCR_DIR_Pos        (4U)\r\n#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */\r\n#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */\r\n#define BDMA_CCR_CIRC_Pos       (5U)\r\n#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */\r\n#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */\r\n#define BDMA_CCR_PINC_Pos       (6U)\r\n#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */\r\n#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */\r\n#define BDMA_CCR_MINC_Pos       (7U)\r\n#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */\r\n#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */\r\n\r\n#define BDMA_CCR_PSIZE_Pos      (8U)\r\n#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */\r\n#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */\r\n#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */\r\n#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */\r\n\r\n#define BDMA_CCR_MSIZE_Pos      (10U)\r\n#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */\r\n#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */\r\n#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */\r\n#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */\r\n\r\n#define BDMA_CCR_PL_Pos         (12U)\r\n#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */\r\n#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/\r\n#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */\r\n#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */\r\n\r\n#define BDMA_CCR_MEM2MEM_Pos    (14U)\r\n#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */\r\n#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */\r\n#define BDMA_CCR_DBM_Pos        (15U)\r\n#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */\r\n#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */\r\n#define BDMA_CCR_CT_Pos         (16U)\r\n#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */\r\n#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */\r\n\r\n/******************  Bit definition for BDMA_CNDTR register  *******************/\r\n#define BDMA_CNDTR_NDT_Pos      (0U)\r\n#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */\r\n#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */\r\n\r\n/******************  Bit definition for BDMA_CPAR register  ********************/\r\n#define BDMA_CPAR_PA_Pos        (0U)\r\n#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */\r\n#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */\r\n\r\n/******************  Bit definition for BDMA_CM0AR register  ********************/\r\n#define BDMA_CM0AR_MA_Pos        (0U)\r\n#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */\r\n#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */\r\n\r\n/******************  Bit definition for BDMA_CM1AR register  ********************/\r\n#define BDMA_CM1AR_MA_Pos        (0U)\r\n#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */\r\n#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Ethernet MAC Registers bits definitions                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/* Bit definition for Ethernet MAC Configuration Register register */\r\n#define ETH_MACCR_ARP_Pos                             (31U)\r\n#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */\r\n#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */\r\n#define ETH_MACCR_SARC_Pos                            (28U)\r\n#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */\r\n#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */\r\n#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */\r\n#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)\r\n#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */\r\n#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)\r\n#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */\r\n#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)\r\n#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */\r\n#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)\r\n#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */\r\n#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */\r\n#define ETH_MACCR_IPC_Pos                             (27U)\r\n#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */\r\n#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */\r\n#define ETH_MACCR_IPG_Pos                             (24U)\r\n#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */\r\n#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */\r\n#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */\r\n#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */\r\n#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */\r\n#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */\r\n#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */\r\n#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */\r\n#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */\r\n#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */\r\n#define ETH_MACCR_GPSLCE_Pos                          (23U)\r\n#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */\r\n#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */\r\n#define ETH_MACCR_S2KP_Pos                            (22U)\r\n#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */\r\n#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */\r\n#define ETH_MACCR_CST_Pos                             (21U)\r\n#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */\r\n#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */\r\n#define ETH_MACCR_ACS_Pos                             (20U)\r\n#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */\r\n#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */\r\n#define ETH_MACCR_WD_Pos                              (19U)\r\n#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */\r\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\r\n#define ETH_MACCR_JD_Pos                              (17U)\r\n#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */\r\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\r\n#define ETH_MACCR_JE_Pos                              (16U)\r\n#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */\r\n#define ETH_MACCR_FES_Pos                             (14U)\r\n#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\r\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\r\n#define ETH_MACCR_DM_Pos                              (13U)\r\n#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */\r\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\r\n#define ETH_MACCR_LM_Pos                              (12U)\r\n#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\r\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\r\n#define ETH_MACCR_ECRSFD_Pos                          (11U)\r\n#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */\r\n#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */\r\n#define ETH_MACCR_DO_Pos                              (10U)\r\n#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */\r\n#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */\r\n#define ETH_MACCR_DCRS_Pos                            (9U)\r\n#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */\r\n#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */\r\n#define ETH_MACCR_DR_Pos                              (8U)\r\n#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */\r\n#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */\r\n#define ETH_MACCR_BL_Pos                              (5U)\r\n#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */\r\n#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */\r\n#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */\r\n#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */\r\n#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r\n#define ETH_MACCR_DC_Pos                              (4U)\r\n#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\r\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\r\n#define ETH_MACCR_PRELEN_Pos                          (2U)\r\n#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */\r\n#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */\r\n#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */\r\n#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */\r\n#define ETH_MACCR_TE_Pos                              (1U)\r\n#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */\r\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\r\n#define ETH_MACCR_RE_Pos                              (0U)\r\n#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */\r\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\r\n\r\n/* Bit definition for Ethernet MAC Extended Configuration Register register */\r\n#define ETH_MACECR_EIPG_Pos                           (25U)\r\n#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */\r\n#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */\r\n#define ETH_MACECR_EIPGEN_Pos                         (24U)\r\n#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */\r\n#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */\r\n#define ETH_MACECR_USP_Pos                            (18U)\r\n#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */\r\n#define ETH_MACECR_SPEN_Pos                           (17U)\r\n#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */\r\n#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */\r\n#define ETH_MACECR_DCRCC_Pos                          (16U)\r\n#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */\r\n#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */\r\n#define ETH_MACECR_GPSL_Pos                           (0U)\r\n#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */\r\n#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */\r\n\r\n/* Bit definition for Ethernet MAC Packet Filter Register */\r\n#define ETH_MACPFR_RA_Pos                             (31U)\r\n#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */\r\n#define ETH_MACPFR_DNTU_Pos                           (21U)\r\n#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */\r\n#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */\r\n#define ETH_MACPFR_IPFE_Pos                           (20U)\r\n#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */\r\n#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */\r\n#define ETH_MACPFR_VTFE_Pos                           (16U)\r\n#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */\r\n#define ETH_MACPFR_HPF_Pos                            (10U)\r\n#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */\r\n#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */\r\n#define ETH_MACPFR_SAF_Pos                            (9U)\r\n#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */\r\n#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */\r\n#define ETH_MACPFR_SAIF_Pos                           (8U)\r\n#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */\r\n#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */\r\n#define ETH_MACPFR_PCF_Pos                            (6U)\r\n#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */\r\n#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */\r\n#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */\r\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)\r\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */\r\n#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)\r\n#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */\r\n#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\r\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)\r\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */\r\n#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */\r\n#define ETH_MACPFR_DBF_Pos                            (5U)\r\n#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */\r\n#define ETH_MACPFR_PM_Pos                             (4U)\r\n#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */\r\n#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */\r\n#define ETH_MACPFR_DAIF_Pos                           (3U)\r\n#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */\r\n#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */\r\n#define ETH_MACPFR_HMC_Pos                            (2U)\r\n#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */\r\n#define ETH_MACPFR_HUC_Pos                            (1U)\r\n#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */\r\n#define ETH_MACPFR_PR_Pos                             (0U)\r\n#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */\r\n\r\n/* Bit definition for Ethernet MAC Watchdog Timeout Register */\r\n#define ETH_MACWTR_PWE_Pos                            (8U)\r\n#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */\r\n#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */\r\n#define ETH_MACWTR_WTO_Pos                            (0U)\r\n#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */\r\n#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */\r\n#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/\r\n#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */\r\n#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */\r\n#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */\r\n#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */\r\n#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */\r\n#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */\r\n#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */\r\n#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */\r\n#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */\r\n#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */\r\n#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */\r\n#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */\r\n#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */\r\n#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table High Register */\r\n#define ETH_MACHTHR_HTH_Pos                           (0U)\r\n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table Low Register */\r\n#define ETH_MACHTLR_HTL_Pos                           (0U)\r\n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Tag Register */\r\n#define ETH_MACVTR_EIVLRXS_Pos                        (31U)\r\n#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */\r\n#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */\r\n#define ETH_MACVTR_EIVLS_Pos                          (28U)\r\n#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */\r\n#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */\r\n#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */\r\n#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)\r\n#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */\r\n#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\r\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)\r\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */\r\n#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\r\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)\r\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */\r\n#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */\r\n#define ETH_MACVTR_ERIVLT_Pos                         (27U)\r\n#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */\r\n#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */\r\n#define ETH_MACVTR_EDVLP_Pos                          (26U)\r\n#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */\r\n#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */\r\n#define ETH_MACVTR_VTHM_Pos                           (25U)\r\n#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */\r\n#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */\r\n#define ETH_MACVTR_EVLRXS_Pos                         (24U)\r\n#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */\r\n#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */\r\n#define ETH_MACVTR_EVLS_Pos                           (21U)\r\n#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */\r\n#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */\r\n#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */\r\n#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)\r\n#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */\r\n#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */\r\n#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)\r\n#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */\r\n#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */\r\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)\r\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */\r\n#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */\r\n#define ETH_MACVTR_DOVLTC_Pos                         (20U)\r\n#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */\r\n#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */\r\n#define ETH_MACVTR_ERSVLM_Pos                         (19U)\r\n#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */\r\n#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */\r\n#define ETH_MACVTR_ESVL_Pos                           (18U)\r\n#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */\r\n#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */\r\n#define ETH_MACVTR_VTIM_Pos                           (17U)\r\n#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */\r\n#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */\r\n#define ETH_MACVTR_ETV_Pos                            (16U)\r\n#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */\r\n#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */\r\n#define ETH_MACVTR_VL_Pos                             (0U)\r\n#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */\r\n#define ETH_MACVTR_VL_UP_Pos                          (13U)\r\n#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */\r\n#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)\r\n#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */\r\n#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r\n#define ETH_MACVTR_VL_VID_Pos                         (0U)\r\n#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */\r\n#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Hash Table Register */\r\n#define ETH_MACVHTR_VLHT_Pos                          (0U)\r\n#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Incl Register */\r\n#define ETH_MACVIR_VLTI_Pos                           (20U)\r\n#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */\r\n#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */\r\n#define ETH_MACVIR_CSVL_Pos                           (19U)\r\n#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */\r\n#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */\r\n#define ETH_MACVIR_VLP_Pos                            (18U)\r\n#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */\r\n#define ETH_MACVIR_VLC_Pos                            (16U)\r\n#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */\r\n#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */\r\n#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */\r\n#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)\r\n#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\r\n#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)\r\n#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\r\n#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\r\n#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)\r\n#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\r\n#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\r\n#define ETH_MACVIR_VLT_Pos                            (0U)\r\n#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */\r\n#define ETH_MACVIR_VLT_UP_Pos                         (13U)\r\n#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */\r\n#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)\r\n#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\r\n#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r\n#define ETH_MACVIR_VLT_VID_Pos                        (0U)\r\n#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */\r\n#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */\r\n\r\n/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */\r\n#define ETH_MACIVIR_VLTI_Pos                          (20U)\r\n#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */\r\n#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */\r\n#define ETH_MACIVIR_CSVL_Pos                          (19U)\r\n#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */\r\n#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */\r\n#define ETH_MACIVIR_VLP_Pos                           (18U)\r\n#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */\r\n#define ETH_MACIVIR_VLC_Pos                           (16U)\r\n#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */\r\n#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */\r\n#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */\r\n#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)\r\n#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */\r\n#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */\r\n#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)\r\n#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */\r\n#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */\r\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)\r\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */\r\n#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */\r\n#define ETH_MACIVIR_VLT_Pos                           (0U)\r\n#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */\r\n#define ETH_MACIVIR_VLT_UP_Pos                        (13U)\r\n#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */\r\n#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)\r\n#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */\r\n#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */\r\n#define ETH_MACIVIR_VLT_VID_Pos                       (0U)\r\n#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */\r\n#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */\r\n\r\n/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */\r\n#define ETH_MACTFCR_PT_Pos                            (16U)\r\n#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */\r\n#define ETH_MACTFCR_DZPQ_Pos                          (7U)\r\n#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */\r\n#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */\r\n#define ETH_MACTFCR_PLT_Pos                           (4U)\r\n#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */\r\n#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */\r\n#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)\r\n#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */\r\n#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)\r\n#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */\r\n#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)\r\n#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */\r\n#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)\r\n#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */\r\n#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */\r\n#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)\r\n#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */\r\n#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */\r\n#define ETH_MACTFCR_TFE_Pos                           (1U)\r\n#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */\r\n#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */\r\n#define ETH_MACTFCR_FCB_Pos                           (0U)\r\n#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */\r\n#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */\r\n\r\n/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */\r\n#define ETH_MACRFCR_UP_Pos                            (1U)\r\n#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */\r\n#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */\r\n#define ETH_MACRFCR_RFE_Pos                           (0U)\r\n#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */\r\n#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */\r\n\r\n/* Bit definition for Ethernet MAC Interrupt Status Register */\r\n#define ETH_MACISR_RXSTSIS_Pos                        (14U)\r\n#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */\r\n#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */\r\n#define ETH_MACISR_TXSTSIS_Pos                        (13U)\r\n#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */\r\n#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */\r\n#define ETH_MACISR_TSIS_Pos                           (12U)\r\n#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */\r\n#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */\r\n#define ETH_MACISR_MMCTXIS_Pos                        (10U)\r\n#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */\r\n#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */\r\n#define ETH_MACISR_MMCRXIS_Pos                        (9U)\r\n#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */\r\n#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */\r\n#define ETH_MACISR_MMCIS_Pos                          (8U)\r\n#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */\r\n#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */\r\n#define ETH_MACISR_LPIIS_Pos                          (5U)\r\n#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */\r\n#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */\r\n#define ETH_MACISR_PMTIS_Pos                          (4U)\r\n#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */\r\n#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */\r\n#define ETH_MACISR_PHYIS_Pos                          (3U)\r\n#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */\r\n#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */\r\n\r\n/* Bit definition for Ethernet MAC Interrupt Enable Register */\r\n#define ETH_MACIER_RXSTSIE_Pos                        (14U)\r\n#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */\r\n#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */\r\n#define ETH_MACIER_TXSTSIE_Pos                        (13U)\r\n#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */\r\n#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */\r\n#define ETH_MACIER_TSIE_Pos                           (12U)\r\n#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */\r\n#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */\r\n#define ETH_MACIER_LPIIE_Pos                          (5U)\r\n#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */\r\n#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */\r\n#define ETH_MACIER_PMTIE_Pos                          (4U)\r\n#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */\r\n#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */\r\n#define ETH_MACIER_PHYIE_Pos                          (3U)\r\n#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */\r\n#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */\r\n\r\n/* Bit definition for Ethernet MAC Rx Tx Status Register */\r\n#define ETH_MACRXTXSR_RWT_Pos                         (8U)\r\n#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */\r\n#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */\r\n#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)\r\n#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */\r\n#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */\r\n#define ETH_MACRXTXSR_LCOL_Pos                        (4U)\r\n#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */\r\n#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */\r\n#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)\r\n#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */\r\n#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */\r\n#define ETH_MACRXTXSR_LCARR_Pos                       (2U)\r\n#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */\r\n#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */\r\n#define ETH_MACRXTXSR_NCARR_Pos                       (1U)\r\n#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */\r\n#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */\r\n#define ETH_MACRXTXSR_TJT_Pos                         (0U)\r\n#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */\r\n#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */\r\n\r\n/* Bit definition for Ethernet MAC PMT Control Status Register */\r\n#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)\r\n#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */\r\n#define ETH_MACPCSR_RWKPTR_Pos                        (24U)\r\n#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */\r\n#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */\r\n#define ETH_MACPCSR_RWKPFE_Pos                        (10U)\r\n#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */\r\n#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */\r\n#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)\r\n#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */\r\n#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */\r\n#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)\r\n#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */\r\n#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)\r\n#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */\r\n#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)\r\n#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */\r\n#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)\r\n#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */\r\n#define ETH_MACPCSR_PWRDWN_Pos                        (0U)\r\n#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */\r\n\r\n/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */\r\n#define ETH_MACRWUPFR_D_Pos                           (0U)\r\n#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */\r\n\r\n/* Bit definition for Ethernet MAC LPI Control Status Register */\r\n#define ETH_MACLCSR_LPITCSE_Pos                       (21U)\r\n#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */\r\n#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */\r\n#define ETH_MACLCSR_LPITE_Pos                         (20U)\r\n#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */\r\n#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */\r\n#define ETH_MACLCSR_LPITXA_Pos                        (19U)\r\n#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */\r\n#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */\r\n#define ETH_MACLCSR_PLS_Pos                           (17U)\r\n#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */\r\n#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */\r\n#define ETH_MACLCSR_LPIEN_Pos                         (16U)\r\n#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */\r\n#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */\r\n#define ETH_MACLCSR_RLPIST_Pos                        (9U)\r\n#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */\r\n#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */\r\n#define ETH_MACLCSR_TLPIST_Pos                        (8U)\r\n#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */\r\n#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */\r\n#define ETH_MACLCSR_RLPIEX_Pos                        (3U)\r\n#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */\r\n#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */\r\n#define ETH_MACLCSR_RLPIEN_Pos                        (2U)\r\n#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */\r\n#define ETH_MACLCSR_TLPIEX_Pos                        (1U)\r\n#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */\r\n#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */\r\n#define ETH_MACLCSR_TLPIEN_Pos                        (0U)\r\n#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */\r\n\r\n/* Bit definition for Ethernet MAC LPI Timers Control Register */\r\n#define ETH_MACLTCR_LST_Pos                           (16U)\r\n#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */\r\n#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */\r\n#define ETH_MACLTCR_TWT_Pos                           (0U)\r\n#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */\r\n\r\n/* Bit definition for Ethernet MAC LPI Entry Timer Register */\r\n#define ETH_MACLETR_LPIET_Pos                         (0U)\r\n#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */\r\n#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */\r\n\r\n/* Bit definition for Ethernet MAC 1US Tic Counter Register */\r\n#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)\r\n#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */\r\n#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */\r\n\r\n/* Bit definition for Ethernet MAC Version Register */\r\n#define ETH_MACVR_USERVER_Pos                         (8U)\r\n#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */\r\n#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */\r\n#define ETH_MACVR_SNPSVER_Pos                         (0U)\r\n#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */\r\n#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */\r\n\r\n/* Bit definition for Ethernet MAC Debug Register */\r\n#define ETH_MACDR_TFCSTS_Pos                          (17U)\r\n#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */\r\n#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */\r\n#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */\r\n#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)\r\n#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */\r\n#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */\r\n#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)\r\n#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */\r\n#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */\r\n#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)\r\n#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */\r\n#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */\r\n#define ETH_MACDR_TPESTS_Pos                          (16U)\r\n#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */\r\n#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */\r\n#define ETH_MACDR_RFCFCSTS_Pos                        (1U)\r\n#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */\r\n#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */\r\n#define ETH_MACDR_RPESTS_Pos                          (0U)\r\n#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */\r\n#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */\r\n\r\n/* Bit definition for Ethernet MAC HW Feature0 Register */\r\n#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)\r\n#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */\r\n#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */\r\n#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */\r\n#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)\r\n#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */\r\n#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */\r\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)\r\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */\r\n#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */\r\n#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)\r\n#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */\r\n#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */\r\n#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)\r\n#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */\r\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)\r\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */\r\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)\r\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */\r\n#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)\r\n#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */\r\n#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */\r\n#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)\r\n#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */\r\n#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */\r\n#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)\r\n#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */\r\n#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */\r\n#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)\r\n#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */\r\n#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */\r\n#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)\r\n#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */\r\n#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */\r\n#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)\r\n#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */\r\n#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */\r\n#define ETH_MACHWF0R_EEESEL_Pos                       (13U)\r\n#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */\r\n#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */\r\n#define ETH_MACHWF0R_TSSEL_Pos                        (12U)\r\n#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */\r\n#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */\r\n#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)\r\n#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */\r\n#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */\r\n#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)\r\n#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */\r\n#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */\r\n#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)\r\n#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */\r\n#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */\r\n#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)\r\n#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */\r\n#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */\r\n#define ETH_MACHWF0R_SMASEL_Pos                       (5U)\r\n#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */\r\n#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */\r\n#define ETH_MACHWF0R_VLHASH_Pos                       (4U)\r\n#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */\r\n#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */\r\n#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)\r\n#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */\r\n#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */\r\n#define ETH_MACHWF0R_HDSEL_Pos                        (2U)\r\n#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */\r\n#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */\r\n#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)\r\n#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */\r\n#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */\r\n#define ETH_MACHWF0R_MIISEL_Pos                       (0U)\r\n#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */\r\n#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */\r\n\r\n/* Bit definition for Ethernet MAC HW Feature1 Register */\r\n#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)\r\n#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */\r\n#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */\r\n#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)\r\n#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */\r\n#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */\r\n#define ETH_MACHWF1R_AVSEL_Pos                        (20U)\r\n#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */\r\n#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */\r\n#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)\r\n#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */\r\n#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */\r\n#define ETH_MACHWF1R_TSOEN_Pos                        (18U)\r\n#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */\r\n#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */\r\n#define ETH_MACHWF1R_SPHEN_Pos                        (17U)\r\n#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */\r\n#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */\r\n#define ETH_MACHWF1R_DCBEN_Pos                        (16U)\r\n#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */\r\n#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */\r\n#define ETH_MACHWF1R_ADDR64_Pos                       (14U)\r\n#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */\r\n#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */\r\n#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */\r\n#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */\r\n#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */\r\n#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)\r\n#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */\r\n#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */\r\n#define ETH_MACHWF1R_PTOEN_Pos                        (12U)\r\n#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */\r\n#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */\r\n#define ETH_MACHWF1R_OSTEN_Pos                        (11U)\r\n#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */\r\n#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */\r\n#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)\r\n#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */\r\n#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */\r\n#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)\r\n#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */\r\n#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */\r\n\r\n/* Bit definition for Ethernet MAC HW Feature2 Register */\r\n#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)\r\n#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */\r\n#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */\r\n#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)\r\n#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */\r\n#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */\r\n#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)\r\n#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */\r\n#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */\r\n#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)\r\n#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */\r\n#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */\r\n#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)\r\n#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */\r\n#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */\r\n#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)\r\n#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */\r\n#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */\r\n\r\n/* Bit definition for Ethernet MAC MDIO Address Register */\r\n#define ETH_MACMDIOAR_PSE_Pos                         (27U)\r\n#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */\r\n#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */\r\n#define ETH_MACMDIOAR_BTB_Pos                         (26U)\r\n#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */\r\n#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */\r\n#define ETH_MACMDIOAR_PA_Pos                          (21U)\r\n#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */\r\n#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */\r\n#define ETH_MACMDIOAR_RDA_Pos                         (16U)\r\n#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */\r\n#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */\r\n#define ETH_MACMDIOAR_NTC_Pos                         (12U)\r\n#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */\r\n#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */\r\n#define ETH_MACMDIOAR_CR_Pos                          (8U)\r\n#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */\r\n#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */\r\n#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */\r\n#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)\r\n#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */\r\n#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */\r\n#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)\r\n#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */\r\n#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */\r\n#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)\r\n#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */\r\n#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */\r\n#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)\r\n#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */\r\n#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */\r\n#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)\r\n#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */\r\n#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */\r\n#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)\r\n#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */\r\n#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)\r\n#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */\r\n#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)\r\n#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */\r\n#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)\r\n#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */\r\n#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)\r\n#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */\r\n#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)\r\n#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */\r\n#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)\r\n#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */\r\n#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)\r\n#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */\r\n#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */\r\n#define ETH_MACMDIOAR_SKAP_Pos                        (4U)\r\n#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */\r\n#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */\r\n#define ETH_MACMDIOAR_MOC_Pos                         (2U)\r\n#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */\r\n#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */\r\n#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)\r\n#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */\r\n#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */\r\n#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)\r\n#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */\r\n#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */\r\n#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)\r\n#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */\r\n#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */\r\n#define ETH_MACMDIOAR_C45E_Pos                        (1U)\r\n#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */\r\n#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */\r\n#define ETH_MACMDIOAR_MB_Pos                          (0U)\r\n#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */\r\n#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */\r\n\r\n/* Bit definition for Ethernet MAC MDIO Data Register */\r\n#define ETH_MACMDIODR_RA_Pos                          (16U)\r\n#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */\r\n#define ETH_MACMDIODR_MD_Pos                          (0U)\r\n#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */\r\n\r\n/* Bit definition for Ethernet ARP Address Register */\r\n#define ETH_MACARPAR_ARPPA_Pos                         (0U)\r\n#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */\r\n\r\n/* Bit definition for Ethernet MAC Address 0 High Register */\r\n#define ETH_MACA0HR_AE_Pos                            (31U)\r\n#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA0HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/\r\n\r\n/* Bit definition for Ethernet MAC Address 0 Low Register */\r\n#define ETH_MACA0LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/\r\n\r\n/* Bit definition for Ethernet MAC Address 1 High Register */\r\n#define ETH_MACA1HR_AE_Pos                            (31U)\r\n#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA1HR_SA_Pos                            (30U)\r\n#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */\r\n#define ETH_MACA1HR_MBC_Pos                           (24U)\r\n#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */\r\n#define ETH_MACA1HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 1 Low Register */\r\n#define ETH_MACA1LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 2 High Register */\r\n#define ETH_MACA2HR_AE_Pos                            (31U)\r\n#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA2HR_SA_Pos                            (30U)\r\n#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */\r\n#define ETH_MACA2HR_MBC_Pos                           (24U)\r\n#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */\r\n#define ETH_MACA2HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 2 Low Register */\r\n#define ETH_MACA2LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/\r\n\r\n/* Bit definition for Ethernet MAC Address 3 High Register */\r\n#define ETH_MACA3HR_AE_Pos                            (31U)\r\n#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/\r\n#define ETH_MACA3HR_SA_Pos                            (30U)\r\n#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */\r\n#define ETH_MACA3HR_MBC_Pos                           (24U)\r\n#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */\r\n#define ETH_MACA3HR_ADDRHI_Pos                        (0U)\r\n#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/\r\n\r\n/* Bit definition for Ethernet MAC Address 3 Low Register */\r\n#define ETH_MACA3LR_ADDRLO_Pos                        (0U)\r\n#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/\r\n\r\n/* Bit definition for Ethernet MAC Address High Register */\r\n#define ETH_MACAHR_AE_Pos                             (31U)\r\n#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */\r\n#define ETH_MACAHR_SA_Pos                             (30U)\r\n#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */\r\n#define ETH_MACAHR_MBC_Pos                            (24U)\r\n#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r\n#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */\r\n#define ETH_MACAHR_MACAH_Pos                          (0U)\r\n#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */\r\n\r\n/* Bit definition for Ethernet MAC Address Low Register */\r\n#define ETH_MACALR_MACAL_Pos                          (0U)\r\n#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */\r\n\r\n/* Bit definition for Ethernet MMC Control Register */\r\n#define ETH_MMCCR_UCDBC_Pos                           (8U)\r\n#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */\r\n#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */\r\n#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)\r\n#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */\r\n#define ETH_MMCCR_CNTPRST_Pos                         (4U)\r\n#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */\r\n#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */\r\n#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)\r\n#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */\r\n#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */\r\n#define ETH_MMCCR_RSTONRD_Pos                         (2U)\r\n#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */\r\n#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */\r\n#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)\r\n#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */\r\n#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */\r\n#define ETH_MMCCR_CNTRST_Pos                          (0U)\r\n#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */\r\n#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */\r\n\r\n/* Bit definition for Ethernet MMC Rx Interrupt Register */\r\n#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)\r\n#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */\r\n#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)\r\n#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */\r\n#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)\r\n#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */\r\n#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */\r\n#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)\r\n#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */\r\n#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */\r\n#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)\r\n#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */\r\n\r\n/* Bit definition for Ethernet MMC Tx Interrupt Register */\r\n#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)\r\n#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */\r\n#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)\r\n#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */\r\n#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)\r\n#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */\r\n#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */\r\n#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)\r\n#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */\r\n#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */\r\n#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)\r\n#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */\r\n#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */\r\n\r\n/* Bit definition for Ethernet MMC Rx interrupt Mask register */\r\n#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)\r\n#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */\r\n#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)\r\n#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */\r\n#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)\r\n#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */\r\n#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */\r\n#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)\r\n#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */\r\n#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */\r\n#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)\r\n#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */\r\n\r\n/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */\r\n#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)\r\n#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */\r\n#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/\r\n#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)\r\n#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */\r\n#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/\r\n#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)\r\n#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */\r\n#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/\r\n#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)\r\n#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */\r\n#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */\r\n#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)\r\n#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */\r\n#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */\r\n\r\n/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */\r\n#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)\r\n#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */\r\n\r\n/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */\r\n#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)\r\n#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */\r\n\r\n/* Bit definition for Ethernet MMC Tx Packet Count Good Register */\r\n#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)\r\n#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */\r\n\r\n/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */\r\n#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)\r\n#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */\r\n\r\n/* Bit definition for Ethernet MMC Rx alignment error packets register */\r\n#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)\r\n#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */\r\n\r\n/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */\r\n#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)\r\n#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */\r\n\r\n/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */\r\n#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)\r\n#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */\r\n\r\n/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */\r\n#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)\r\n#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */\r\n\r\n/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */\r\n#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)\r\n#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */\r\n\r\n/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */\r\n#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)\r\n#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */\r\n\r\n/* Bit definition for Ethernet MAC L3 L4 Control Register */\r\n#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)\r\n#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */\r\n#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)\r\n#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */\r\n#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */\r\n#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)\r\n#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */\r\n#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)\r\n#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */\r\n#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */\r\n#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)\r\n#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */\r\n#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */\r\n#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)\r\n#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */\r\n#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */\r\n#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)\r\n#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */\r\n#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */\r\n#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)\r\n#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */\r\n#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)\r\n#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */\r\n#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */\r\n#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)\r\n#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */\r\n#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */\r\n#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)\r\n#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */\r\n#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/\r\n#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)\r\n#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address Register */\r\n#define ETH_MACL4AR_L4DP_Pos                          (16U)\r\n#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */\r\n#define ETH_MACL4AR_L4SP_Pos                          (0U)\r\n#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */\r\n\r\n/* Bit definition for Ethernet MAC L3 Address0 Register */\r\n#define ETH_MACL3A0R_L3A0_Pos                         (0U)\r\n#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address1 Register */\r\n#define ETH_MACL3A1R_L3A1_Pos                         (0U)\r\n#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address2 Register */\r\n#define ETH_MACL3A2R_L3A2_Pos                         (0U)\r\n#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */\r\n\r\n/* Bit definition for Ethernet MAC L4 Address3 Register */\r\n#define ETH_MACL3A3R_L3A3_Pos                         (0U)\r\n#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Control Register */\r\n#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)\r\n#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */\r\n#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */\r\n#define ETH_MACTSCR_CSC_Pos                           (19U)\r\n#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */\r\n#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */\r\n#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)\r\n#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */\r\n#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */\r\n#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)\r\n#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */\r\n#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */\r\n#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)\r\n#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */\r\n#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */\r\n#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)\r\n#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */\r\n#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */\r\n#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)\r\n#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */\r\n#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */\r\n#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)\r\n#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */\r\n#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */\r\n#define ETH_MACTSCR_TSIPENA_Pos                       (11U)\r\n#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */\r\n#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */\r\n#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)\r\n#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */\r\n#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */\r\n#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)\r\n#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */\r\n#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */\r\n#define ETH_MACTSCR_TSENALL_Pos                       (8U)\r\n#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */\r\n#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */\r\n#define ETH_MACTSCR_TSADDREG_Pos                      (5U)\r\n#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */\r\n#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */\r\n#define ETH_MACTSCR_TSUPDT_Pos                        (3U)\r\n#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */\r\n#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */\r\n#define ETH_MACTSCR_TSINIT_Pos                        (2U)\r\n#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */\r\n#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */\r\n#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)\r\n#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */\r\n#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/\r\n#define ETH_MACTSCR_TSENA_Pos                         (0U)\r\n#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */\r\n#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */\r\n\r\n/* Bit definition for Ethernet MAC Sub-second Increment Register */\r\n#define ETH_MACMACSSIR_SSINC_Pos                      (16U)\r\n#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */\r\n#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */\r\n#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)\r\n#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */\r\n#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */\r\n\r\n/* Bit definition for Ethernet MAC System Time Seconds Register */\r\n#define ETH_MACSTSR_TSS_Pos                           (0U)\r\n#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */\r\n\r\n/* Bit definition for Ethernet MAC System Time Nanoseconds Register */\r\n#define ETH_MACSTNR_TSSS_Pos                          (0U)\r\n#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */\r\n\r\n/* Bit definition for Ethernet MAC System Time Seconds Update Register */\r\n#define ETH_MACSTSUR_TSS_Pos                          (0U)\r\n#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */\r\n\r\n/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */\r\n#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)\r\n#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */\r\n#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */\r\n#define ETH_MACSTNUR_TSSS_Pos                         (0U)\r\n#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Addend Register */\r\n#define ETH_MACTSAR_TSAR_Pos                          (0U)\r\n#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Status Register */\r\n#define ETH_MACTSSR_ATSNS_Pos                         (25U)\r\n#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */\r\n#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */\r\n#define ETH_MACTSSR_ATSSTM_Pos                        (24U)\r\n#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */\r\n#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */\r\n#define ETH_MACTSSR_ATSSTN_Pos                        (16U)\r\n#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */\r\n#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */\r\n#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)\r\n#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */\r\n#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */\r\n#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)\r\n#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */\r\n#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */\r\n#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)\r\n#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */\r\n#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/\r\n#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)\r\n#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */\r\n#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */\r\n#define ETH_MACTSSR_TSSOVF_Pos                        (0U)\r\n#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */\r\n#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */\r\n\r\n/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */\r\n#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)\r\n#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */\r\n#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */\r\n#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)\r\n#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */\r\n\r\n/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */\r\n#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)\r\n#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */\r\n\r\n/* Bit definition for Ethernet MAC Auxiliary Control Register*/\r\n#define ETH_MACACR_ATSEN3_Pos                         (7U)\r\n#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */\r\n#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */\r\n#define ETH_MACACR_ATSEN2_Pos                         (6U)\r\n#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */\r\n#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */\r\n#define ETH_MACACR_ATSEN1_Pos                         (5U)\r\n#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */\r\n#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */\r\n#define ETH_MACACR_ATSEN0_Pos                         (4U)\r\n#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */\r\n#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */\r\n#define ETH_MACACR_ATSFC_Pos                          (0U)\r\n#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */\r\n#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */\r\n\r\n/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */\r\n#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)\r\n#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */\r\n\r\n/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */\r\n#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)\r\n#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */\r\n#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)\r\n#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */\r\n#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)\r\n#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */\r\n#define ETH_MACTSICNR_TSIC_Pos                        (0U)\r\n#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */\r\n\r\n/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */\r\n#define ETH_MACTSECNR_TSEC_Pos                        (0U)\r\n#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */\r\n\r\n/* Bit definition for Ethernet MAC PPS Control Register */\r\n#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)\r\n#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */\r\n#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */\r\n#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)\r\n#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */\r\n#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */\r\n#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)\r\n#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */\r\n#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */\r\n\r\n/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */\r\n#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)\r\n#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */\r\n\r\n/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */\r\n#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)\r\n#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */\r\n#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)\r\n#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */\r\n\r\n/* Bit definition for Ethernet MAC PPS Interval Register */\r\n#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)\r\n#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */\r\n\r\n/* Bit definition for Ethernet MAC PPS Width Register */\r\n#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)\r\n#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */\r\n\r\n/* Bit definition for Ethernet MAC PTP Offload Control Register */\r\n#define ETH_MACPOCR_DN_Pos                            (8U)\r\n#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */\r\n#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */\r\n#define ETH_MACPOCR_DRRDIS_Pos                        (6U)\r\n#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */\r\n#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)\r\n#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */\r\n#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)\r\n#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */\r\n#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */\r\n#define ETH_MACPOCR_APDREQEN_Pos                      (2U)\r\n#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */\r\n#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)\r\n#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */\r\n#define ETH_MACPOCR_PTOEN_Pos                         (0U)\r\n#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */\r\n\r\n/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */\r\n#define ETH_MACSPI0R_SPI0_Pos                         (0U)\r\n#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */\r\n\r\n/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */\r\n#define ETH_MACSPI1R_SPI1_Pos                         (0U)\r\n#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */\r\n\r\n/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */\r\n#define ETH_MACSPI2R_SPI2_Pos                         (0U)\r\n#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */\r\n\r\n/* Bit definition for Ethernet MAC Log Message Interval Register */\r\n#define ETH_MACLMIR_LMPDRI_Pos                        (24U)\r\n#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */\r\n#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */\r\n#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)\r\n#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */\r\n#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */\r\n#define ETH_MACLMIR_LSI_Pos                           (0U)\r\n#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */\r\n#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */\r\n\r\n/* Bit definition for Ethernet MTL Operation Mode Register */\r\n#define ETH_MTLOMR_CNTCLR_Pos                         (9U)\r\n#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */\r\n#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */\r\n#define ETH_MTLOMR_CNTPRST_Pos                        (8U)\r\n#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */\r\n#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */\r\n#define ETH_MTLOMR_DTXSTS_Pos                         (1U)\r\n#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */\r\n#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */\r\n\r\n/* Bit definition for Ethernet MTL Interrupt Status Register */\r\n#define ETH_MTLISR_MACIS_Pos                          (16U)\r\n#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */\r\n#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */\r\n#define ETH_MTLISR_QIS_Pos                            (0U)\r\n#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */\r\n\r\n/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */\r\n#define ETH_MTLTQOMR_TTC_Pos                          (4U)\r\n#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */\r\n#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */\r\n#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */\r\n#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */\r\n#define ETH_MTLTQOMR_TSF_Pos                          (1U)\r\n#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */\r\n#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */\r\n#define ETH_MTLTQOMR_FTQ_Pos                          (0U)\r\n#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */\r\n\r\n/* Bit definition for Ethernet MTL Tx Queue Underflow Register */\r\n#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)\r\n#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */\r\n#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */\r\n#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)\r\n#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */\r\n#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */\r\n\r\n/* Bit definition for Ethernet MTL Tx Queue Debug Register */\r\n#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)\r\n#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */\r\n#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */\r\n#define ETH_MTLTQDR_PTXQ_Pos                          (16U)\r\n#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */\r\n#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */\r\n#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)\r\n#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */\r\n#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */\r\n#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)\r\n#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */\r\n#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */\r\n#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)\r\n#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */\r\n#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */\r\n#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)\r\n#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */\r\n#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */\r\n#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */\r\n#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */\r\n#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */\r\n#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */\r\n#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)\r\n#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */\r\n\r\n/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */\r\n#define ETH_MTLQICSR_RXOIE_Pos                        (24U)\r\n#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */\r\n#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */\r\n#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)\r\n#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */\r\n#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */\r\n#define ETH_MTLQICSR_TXUIE_Pos                        (8U)\r\n#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */\r\n#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */\r\n#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)\r\n#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */\r\n#define ETH_MTLRQOMR_RQS_Pos                          (20U)\r\n#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */\r\n#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */\r\n#define ETH_MTLRQOMR_RFD_Pos                          (14U)\r\n#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */\r\n#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */\r\n#define ETH_MTLRQOMR_RFA_Pos                          (8U)\r\n#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */\r\n#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */\r\n#define ETH_MTLRQOMR_EHFC_Pos                         (7U)\r\n#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */\r\n#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */\r\n#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)\r\n#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */\r\n#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */\r\n#define ETH_MTLRQOMR_RSF_Pos                          (5U)\r\n#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */\r\n#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */\r\n#define ETH_MTLRQOMR_FEP_Pos                          (4U)\r\n#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */\r\n#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */\r\n#define ETH_MTLRQOMR_FUP_Pos                          (3U)\r\n#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */\r\n#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */\r\n#define ETH_MTLRQOMR_RTC_Pos                          (0U)\r\n#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */\r\n#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */\r\n#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */\r\n#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */\r\n#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */\r\n#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */\r\n#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)\r\n#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */\r\n#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */\r\n#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)\r\n#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */\r\n#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */\r\n#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)\r\n#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */\r\n#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */\r\n#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)\r\n#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */\r\n#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Debug Register */\r\n#define ETH_MTLRQDR_PRXQ_Pos                          (16U)\r\n#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */\r\n#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */\r\n#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)\r\n#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */\r\n#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */\r\n#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */\r\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)\r\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */\r\n#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */\r\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)\r\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */\r\n#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */\r\n#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)\r\n#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */\r\n#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */\r\n#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)\r\n#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */\r\n#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */\r\n#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */\r\n#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)\r\n#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */\r\n#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */\r\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)\r\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */\r\n#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */\r\n#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)\r\n#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */\r\n#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */\r\n#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)\r\n#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */\r\n#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */\r\n\r\n/* Bit definition for Ethernet MTL Rx Queue Control Register */\r\n#define ETH_MTLRQCR_RQPA_Pos                          (3U)\r\n#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */\r\n#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */\r\n#define ETH_MTLRQCR_RQW_Pos                           (0U)\r\n#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */\r\n#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */\r\n\r\n/* Bit definition for Ethernet DMA Mode Register */\r\n#define ETH_DMAMR_INTM_Pos                            (16U)\r\n#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */\r\n#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */\r\n#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */\r\n#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */\r\n#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */\r\n#define ETH_DMAMR_PR_Pos                              (12U)\r\n#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */\r\n#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */\r\n#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */\r\n#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */\r\n#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */\r\n#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */\r\n#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */\r\n#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */\r\n#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */\r\n#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */\r\n#define ETH_DMAMR_TXPR_Pos                            (11U)\r\n#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */\r\n#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */\r\n#define ETH_DMAMR_DA_Pos                              (1U)\r\n#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */\r\n#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */\r\n#define ETH_DMAMR_SWR_Pos                             (0U)\r\n#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */\r\n#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */\r\n\r\n/* Bit definition for Ethernet DMA SysBus Mode Register */\r\n#define ETH_DMASBMR_RB_Pos                            (15U)\r\n#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */\r\n#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */\r\n#define ETH_DMASBMR_MB_Pos                            (14U)\r\n#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */\r\n#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */\r\n#define ETH_DMASBMR_AAL_Pos                           (12U)\r\n#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */\r\n#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */\r\n#define ETH_DMASBMR_FB_Pos                            (0U)\r\n#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */\r\n#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */\r\n\r\n/* Bit definition for Ethernet DMA Interrupt Status Register */\r\n#define ETH_DMAISR_MACIS_Pos                          (17U)\r\n#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */\r\n#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */\r\n#define ETH_DMAISR_MTLIS_Pos                          (16U)\r\n#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */\r\n#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */\r\n#define ETH_DMAISR_DMACIS_Pos                         (0U)\r\n#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */\r\n#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */\r\n\r\n/* Bit definition for Ethernet DMA Debug Status Register */\r\n#define ETH_DMADSR_TPS_Pos                            (12U)\r\n#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */\r\n#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */\r\n#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */\r\n#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)\r\n#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */\r\n#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */\r\n#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)\r\n#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */\r\n#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */\r\n#define ETH_DMADSR_TPS_READING_Pos                    (12U)\r\n#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */\r\n#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */\r\n#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)\r\n#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */\r\n#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */\r\n#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)\r\n#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */\r\n#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */\r\n#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)\r\n#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */\r\n#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */\r\n#define ETH_DMADSR_RPS_Pos                            (8U)\r\n#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */\r\n#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */\r\n#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */\r\n#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)\r\n#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */\r\n#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */\r\n#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)\r\n#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */\r\n#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */\r\n#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)\r\n#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */\r\n#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */\r\n#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)\r\n#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */\r\n#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */\r\n#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)\r\n#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */\r\n#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */\r\n#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)\r\n#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */\r\n#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */\r\n\r\n/* Bit definition for Ethernet DMA Channel Control Register */\r\n#define ETH_DMACCR_DSL_Pos                            (18U)\r\n#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */\r\n#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */\r\n#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)\r\n#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)\r\n#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)\r\n#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)\r\n#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */\r\n#define ETH_DMACCR_MSS_Pos                            (0U)\r\n#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */\r\n#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */\r\n\r\n/* Bit definition for Ethernet DMA Channel Tx Control Register */\r\n#define ETH_DMACTCR_TPBL_Pos                          (16U)\r\n#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */\r\n#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */\r\n#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */\r\n#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */\r\n#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */\r\n#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */\r\n#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */\r\n#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */\r\n#define ETH_DMACTCR_TSE_Pos                           (12U)\r\n#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */\r\n#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */\r\n#define ETH_DMACTCR_OSP_Pos                           (4U)\r\n#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */\r\n#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */\r\n#define ETH_DMACTCR_ST_Pos                            (0U)\r\n#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */\r\n\r\n/* Bit definition for Ethernet DMA Channel Rx Control Register */\r\n#define ETH_DMACRCR_RPF_Pos                           (31U)\r\n#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */\r\n#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */\r\n#define ETH_DMACRCR_RPBL_Pos                          (16U)\r\n#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */\r\n#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */\r\n#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */\r\n#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */\r\n#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */\r\n#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */\r\n#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */\r\n#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */\r\n#define ETH_DMACRCR_RBSZ_Pos                          (1U)\r\n#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */\r\n#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */\r\n#define ETH_DMACRCR_SR_Pos                            (0U)\r\n#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */\r\n\r\n/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */\r\n#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)\r\n#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */\r\n\r\n/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */\r\n#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)\r\n#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */\r\n\r\n/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */\r\n#define ETH_DMACTDTPR_TDT_Pos                         (2U)\r\n#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */\r\n\r\n/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */\r\n#define ETH_DMACRDTPR_RDT_Pos                         (2U)\r\n#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */\r\n#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */\r\n\r\n/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */\r\n#define ETH_DMACTDRLR_TDRL_Pos                        (0U)\r\n#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */\r\n#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */\r\n\r\n/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */\r\n#define ETH_DMACRDRLR_RDRL_Pos                        (0U)\r\n#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */\r\n#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */\r\n\r\n/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */\r\n#define ETH_DMACIER_NIE_Pos                           (15U)\r\n#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */\r\n#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */\r\n#define ETH_DMACIER_AIE_Pos                           (14U)\r\n#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */\r\n#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */\r\n#define ETH_DMACIER_CDEE_Pos                          (13U)\r\n#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */\r\n#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */\r\n#define ETH_DMACIER_FBEE_Pos                          (12U)\r\n#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */\r\n#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */\r\n#define ETH_DMACIER_ERIE_Pos                          (11U)\r\n#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */\r\n#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */\r\n#define ETH_DMACIER_ETIE_Pos                          (10U)\r\n#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */\r\n#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */\r\n#define ETH_DMACIER_RWTE_Pos                          (9U)\r\n#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */\r\n#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */\r\n#define ETH_DMACIER_RSE_Pos                           (8U)\r\n#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */\r\n#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */\r\n#define ETH_DMACIER_RBUE_Pos                          (7U)\r\n#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */\r\n#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */\r\n#define ETH_DMACIER_RIE_Pos                           (6U)\r\n#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */\r\n#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */\r\n#define ETH_DMACIER_TBUE_Pos                          (2U)\r\n#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */\r\n#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */\r\n#define ETH_DMACIER_TXSE_Pos                          (1U)\r\n#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */\r\n#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */\r\n#define ETH_DMACIER_TIE_Pos                           (0U)\r\n#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */\r\n\r\n/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */\r\n#define ETH_DMACRIWTR_RWT_Pos                         (0U)\r\n#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */\r\n#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */\r\n#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)\r\n#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */\r\n#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)\r\n#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */\r\n#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)\r\n#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */\r\n#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)\r\n#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */\r\n\r\n/* Bit definition for Ethernet DMA Channel Status Register */\r\n#define ETH_DMACSR_REB_Pos                            (19U)\r\n#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */\r\n#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */\r\n#define ETH_DMACSR_TEB_Pos                            (16U)\r\n#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */\r\n#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */\r\n#define ETH_DMACSR_NIS_Pos                            (15U)\r\n#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */\r\n#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */\r\n#define ETH_DMACSR_AIS_Pos                            (14U)\r\n#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */\r\n#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */\r\n#define ETH_DMACSR_CDE_Pos                            (13U)\r\n#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */\r\n#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */\r\n#define ETH_DMACSR_FBE_Pos                            (12U)\r\n#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */\r\n#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */\r\n#define ETH_DMACSR_ERI_Pos                            (11U)\r\n#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */\r\n#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */\r\n#define ETH_DMACSR_ETI_Pos                            (10U)\r\n#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */\r\n#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */\r\n#define ETH_DMACSR_RWT_Pos                            (9U)\r\n#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */\r\n#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */\r\n#define ETH_DMACSR_RPS_Pos                            (8U)\r\n#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */\r\n#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */\r\n#define ETH_DMACSR_RBU_Pos                            (7U)\r\n#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */\r\n#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */\r\n#define ETH_DMACSR_RI_Pos                             (6U)\r\n#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */\r\n#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */\r\n#define ETH_DMACSR_TBU_Pos                            (2U)\r\n#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */\r\n#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */\r\n#define ETH_DMACSR_TPS_Pos                            (1U)\r\n#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */\r\n#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */\r\n#define ETH_DMACSR_TI_Pos                             (0U)\r\n#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */\r\n#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */\r\n\r\n/* Bit definition for Ethernet DMA Channel missed frame count register */\r\n#define ETH_DMACMFCR_MFCO_Pos                         (15U)\r\n#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */\r\n#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */\r\n#define ETH_DMACMFCR_MFC_Pos                          (0U)\r\n#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */\r\n#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             DMA Controller                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DMA_SxCR register  *****************/\r\n#define DMA_SxCR_MBURST_Pos      (23U)\r\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */\r\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */\r\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\r\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\r\n#define DMA_SxCR_PBURST_Pos      (21U)\r\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */\r\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */\r\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\r\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\r\n#define DMA_SxCR_TRBUFF_Pos      (20U)\r\n#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */\r\n#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */\r\n#define DMA_SxCR_CT_Pos          (19U)\r\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */\r\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */\r\n#define DMA_SxCR_DBM_Pos         (18U)\r\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */\r\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */\r\n#define DMA_SxCR_PL_Pos          (16U)\r\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */\r\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */\r\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\r\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\r\n#define DMA_SxCR_PINCOS_Pos      (15U)\r\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */\r\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */\r\n#define DMA_SxCR_MSIZE_Pos       (13U)\r\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */\r\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */\r\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\r\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\r\n#define DMA_SxCR_PSIZE_Pos       (11U)\r\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */\r\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */\r\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\r\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\r\n#define DMA_SxCR_MINC_Pos        (10U)\r\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */\r\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */\r\n#define DMA_SxCR_PINC_Pos        (9U)\r\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */\r\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */\r\n#define DMA_SxCR_CIRC_Pos        (8U)\r\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */\r\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */\r\n#define DMA_SxCR_DIR_Pos         (6U)\r\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */\r\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */\r\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\r\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\r\n#define DMA_SxCR_PFCTRL_Pos      (5U)\r\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */\r\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */\r\n#define DMA_SxCR_TCIE_Pos        (4U)\r\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */\r\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */\r\n#define DMA_SxCR_HTIE_Pos        (3U)\r\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */\r\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */\r\n#define DMA_SxCR_TEIE_Pos        (2U)\r\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */\r\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */\r\n#define DMA_SxCR_DMEIE_Pos       (1U)\r\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */\r\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */\r\n#define DMA_SxCR_EN_Pos          (0U)\r\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */\r\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */\r\n\r\n/********************  Bits definition for DMA_SxCNDTR register  **************/\r\n#define DMA_SxNDT_Pos            (0U)\r\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */\r\n#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */\r\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\r\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\r\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\r\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\r\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\r\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\r\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\r\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\r\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\r\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\r\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\r\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\r\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\r\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\r\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\r\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\r\n\r\n/********************  Bits definition for DMA_SxFCR register  ****************/\r\n#define DMA_SxFCR_FEIE_Pos       (7U)\r\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */\r\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */\r\n#define DMA_SxFCR_FS_Pos         (3U)\r\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */\r\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */\r\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\r\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\r\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\r\n#define DMA_SxFCR_DMDIS_Pos      (2U)\r\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */\r\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */\r\n#define DMA_SxFCR_FTH_Pos        (0U)\r\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */\r\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */\r\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\r\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\r\n\r\n/********************  Bits definition for DMA_LISR register  *****************/\r\n#define DMA_LISR_TCIF3_Pos       (27U)\r\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */\r\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF3_Pos       (26U)\r\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */\r\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF3_Pos       (25U)\r\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */\r\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF3_Pos      (24U)\r\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */\r\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF3_Pos       (22U)\r\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */\r\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */\r\n#define DMA_LISR_TCIF2_Pos       (21U)\r\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */\r\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF2_Pos       (20U)\r\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */\r\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF2_Pos       (19U)\r\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */\r\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF2_Pos      (18U)\r\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */\r\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF2_Pos       (16U)\r\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */\r\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */\r\n#define DMA_LISR_TCIF1_Pos       (11U)\r\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */\r\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF1_Pos       (10U)\r\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */\r\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF1_Pos       (9U)\r\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */\r\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF1_Pos      (8U)\r\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */\r\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF1_Pos       (6U)\r\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */\r\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */\r\n#define DMA_LISR_TCIF0_Pos       (5U)\r\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */\r\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */\r\n#define DMA_LISR_HTIF0_Pos       (4U)\r\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */\r\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */\r\n#define DMA_LISR_TEIF0_Pos       (3U)\r\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */\r\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */\r\n#define DMA_LISR_DMEIF0_Pos      (2U)\r\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */\r\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */\r\n#define DMA_LISR_FEIF0_Pos       (0U)\r\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */\r\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */\r\n\r\n/********************  Bits definition for DMA_HISR register  *****************/\r\n#define DMA_HISR_TCIF7_Pos       (27U)\r\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */\r\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF7_Pos       (26U)\r\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */\r\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF7_Pos       (25U)\r\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */\r\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF7_Pos      (24U)\r\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */\r\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF7_Pos       (22U)\r\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */\r\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */\r\n#define DMA_HISR_TCIF6_Pos       (21U)\r\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */\r\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF6_Pos       (20U)\r\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */\r\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF6_Pos       (19U)\r\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */\r\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF6_Pos      (18U)\r\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */\r\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF6_Pos       (16U)\r\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */\r\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */\r\n#define DMA_HISR_TCIF5_Pos       (11U)\r\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */\r\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF5_Pos       (10U)\r\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */\r\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF5_Pos       (9U)\r\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */\r\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF5_Pos      (8U)\r\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */\r\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF5_Pos       (6U)\r\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */\r\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */\r\n#define DMA_HISR_TCIF4_Pos       (5U)\r\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */\r\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */\r\n#define DMA_HISR_HTIF4_Pos       (4U)\r\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */\r\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */\r\n#define DMA_HISR_TEIF4_Pos       (3U)\r\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */\r\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */\r\n#define DMA_HISR_DMEIF4_Pos      (2U)\r\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */\r\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */\r\n#define DMA_HISR_FEIF4_Pos       (0U)\r\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */\r\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */\r\n\r\n/********************  Bits definition for DMA_LIFCR register  ****************/\r\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\r\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */\r\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\r\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */\r\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\r\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */\r\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\r\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */\r\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\r\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */\r\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */\r\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\r\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */\r\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\r\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */\r\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\r\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */\r\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\r\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */\r\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\r\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */\r\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */\r\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\r\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */\r\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\r\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */\r\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\r\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */\r\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\r\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */\r\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\r\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */\r\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */\r\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\r\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */\r\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */\r\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\r\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */\r\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */\r\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\r\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */\r\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */\r\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\r\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */\r\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */\r\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\r\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */\r\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */\r\n\r\n/********************  Bits definition for DMA_HIFCR  register  ****************/\r\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\r\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */\r\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\r\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */\r\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\r\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */\r\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\r\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */\r\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\r\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */\r\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */\r\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\r\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */\r\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\r\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */\r\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\r\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */\r\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\r\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */\r\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\r\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */\r\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */\r\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\r\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */\r\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\r\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */\r\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\r\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */\r\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\r\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */\r\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\r\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */\r\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */\r\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\r\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */\r\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */\r\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\r\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */\r\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */\r\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\r\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */\r\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */\r\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\r\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */\r\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */\r\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\r\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */\r\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */\r\n\r\n/******************  Bit definition for DMA_SxPAR register  ********************/\r\n#define DMA_SxPAR_PA_Pos         (0U)\r\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */\r\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\r\n\r\n/******************  Bit definition for DMA_SxM0AR register  ********************/\r\n#define DMA_SxM0AR_M0A_Pos       (0U)\r\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */\r\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */\r\n\r\n/******************  Bit definition for DMA_SxM1AR register  ********************/\r\n#define DMA_SxM1AR_M1A_Pos       (0U)\r\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */\r\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             DMAMUX Controller                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DMAMUX_CxCR register  **************/\r\n#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)\r\n#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */\r\n#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */\r\n#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */\r\n#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */\r\n#define DMAMUX_CxCR_SOIE_Pos           (8U)\r\n#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */\r\n#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */\r\n#define DMAMUX_CxCR_EGE_Pos            (9U)\r\n#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */\r\n#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */\r\n#define DMAMUX_CxCR_SE_Pos             (16U)\r\n#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */\r\n#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */\r\n#define DMAMUX_CxCR_SPOL_Pos           (17U)\r\n#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */\r\n#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */\r\n#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */\r\n#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */\r\n#define DMAMUX_CxCR_NBREQ_Pos          (19U)\r\n#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */\r\n#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */\r\n#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */\r\n#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */\r\n#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */\r\n#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */\r\n#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */\r\n#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)\r\n#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */\r\n#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */\r\n#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */\r\n#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */\r\n\r\n/********************  Bits definition for DMAMUX_CSR register  **************/\r\n#define DMAMUX_CSR_SOF0_Pos            (0U)\r\n#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */\r\n#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF1_Pos            (1U)\r\n#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */\r\n#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF2_Pos            (2U)\r\n#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */\r\n#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF3_Pos            (3U)\r\n#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */\r\n#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF4_Pos            (4U)\r\n#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */\r\n#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF5_Pos            (5U)\r\n#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */\r\n#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF6_Pos            (6U)\r\n#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */\r\n#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF7_Pos            (7U)\r\n#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */\r\n#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF8_Pos            (8U)\r\n#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */\r\n#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF9_Pos            (9U)\r\n#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */\r\n#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF10_Pos           (10U)\r\n#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */\r\n#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF11_Pos           (11U)\r\n#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */\r\n#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF12_Pos           (12U)\r\n#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */\r\n#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF13_Pos           (13U)\r\n#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */\r\n#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF14_Pos           (14U)\r\n#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */\r\n#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */\r\n#define DMAMUX_CSR_SOF15_Pos           (15U)\r\n#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */\r\n#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */\r\n\r\n/********************  Bits definition for DMAMUX_CFR register  **************/\r\n#define DMAMUX_CFR_CSOF0_Pos           (0U)\r\n#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */\r\n#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF1_Pos           (1U)\r\n#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */\r\n#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF2_Pos           (2U)\r\n#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */\r\n#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF3_Pos           (3U)\r\n#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */\r\n#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF4_Pos           (4U)\r\n#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */\r\n#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF5_Pos           (5U)\r\n#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */\r\n#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF6_Pos           (6U)\r\n#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */\r\n#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF7_Pos           (7U)\r\n#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */\r\n#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF8_Pos           (8U)\r\n#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */\r\n#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF9_Pos           (9U)\r\n#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */\r\n#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF10_Pos          (10U)\r\n#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */\r\n#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF11_Pos          (11U)\r\n#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */\r\n#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF12_Pos          (12U)\r\n#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */\r\n#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF13_Pos          (13U)\r\n#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */\r\n#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF14_Pos          (14U)\r\n#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */\r\n#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */\r\n#define DMAMUX_CFR_CSOF15_Pos          (15U)\r\n#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */\r\n#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */\r\n\r\n/********************  Bits definition for DMAMUX_RGxCR register  ************/\r\n#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)\r\n#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */\r\n#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */\r\n#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */\r\n#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */\r\n#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */\r\n#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */\r\n#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */\r\n#define DMAMUX_RGxCR_OIE_Pos           (8U)\r\n#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */\r\n#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */\r\n#define DMAMUX_RGxCR_GE_Pos            (16U)\r\n#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */\r\n#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */\r\n#define DMAMUX_RGxCR_GPOL_Pos          (17U)\r\n#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */\r\n#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */\r\n#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */\r\n#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */\r\n#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)\r\n#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */\r\n#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */\r\n#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */\r\n#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */\r\n#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */\r\n#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */\r\n#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */\r\n\r\n/********************  Bits definition for DMAMUX_RGSR register  **************/\r\n#define DMAMUX_RGSR_OF0_Pos            (0U)\r\n#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */\r\n#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF1_Pos            (1U)\r\n#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */\r\n#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF2_Pos            (2U)\r\n#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */\r\n#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF3_Pos            (3U)\r\n#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */\r\n#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF4_Pos            (4U)\r\n#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */\r\n#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF5_Pos            (5U)\r\n#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */\r\n#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF6_Pos            (6U)\r\n#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */\r\n#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */\r\n#define DMAMUX_RGSR_OF7_Pos            (7U)\r\n#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */\r\n#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */\r\n\r\n/********************  Bits definition for DMAMUX_RGCFR register  **************/\r\n#define DMAMUX_RGCFR_COF0_Pos          (0U)\r\n#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */\r\n#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF1_Pos          (1U)\r\n#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */\r\n#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF2_Pos          (2U)\r\n#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */\r\n#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF3_Pos          (3U)\r\n#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */\r\n#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF4_Pos          (4U)\r\n#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */\r\n#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF5_Pos          (5U)\r\n#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */\r\n#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF6_Pos          (6U)\r\n#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */\r\n#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */\r\n#define DMAMUX_RGCFR_COF7_Pos          (7U)\r\n#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */\r\n#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         AHB Master DMA2D Controller (DMA2D)                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for DMA2D_CR register  ******************/\r\n\r\n#define DMA2D_CR_START_Pos         (0U)\r\n#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */\r\n#define DMA2D_CR_SUSP_Pos          (1U)\r\n#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */\r\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */\r\n#define DMA2D_CR_ABORT_Pos         (2U)\r\n#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */\r\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */\r\n#define DMA2D_CR_LOM_Pos           (6U)\r\n#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */\r\n#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */\r\n#define DMA2D_CR_TEIE_Pos          (8U)\r\n#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */\r\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */\r\n#define DMA2D_CR_TCIE_Pos          (9U)\r\n#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */\r\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */\r\n#define DMA2D_CR_TWIE_Pos          (10U)\r\n#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */\r\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */\r\n#define DMA2D_CR_CAEIE_Pos         (11U)\r\n#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */\r\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */\r\n#define DMA2D_CR_CTCIE_Pos         (12U)\r\n#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */\r\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\r\n#define DMA2D_CR_CEIE_Pos          (13U)\r\n#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */\r\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */\r\n#define DMA2D_CR_MODE_Pos          (16U)\r\n#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */\r\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */\r\n#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\r\n#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\r\n#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */\r\n\r\n/********************  Bit definition for DMA2D_ISR register  *****************/\r\n\r\n#define DMA2D_ISR_TEIF_Pos         (0U)\r\n#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */\r\n#define DMA2D_ISR_TCIF_Pos         (1U)\r\n#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */\r\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */\r\n#define DMA2D_ISR_TWIF_Pos         (2U)\r\n#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */\r\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_ISR_CAEIF_Pos        (3U)\r\n#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_ISR_CTCIF_Pos        (4U)\r\n#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */\r\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_ISR_CEIF_Pos         (5U)\r\n#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */\r\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_IFCR register  ****************/\r\n\r\n#define DMA2D_IFCR_CTEIF_Pos       (0U)\r\n#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */\r\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */\r\n#define DMA2D_IFCR_CTCIF_Pos       (1U)\r\n#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */\r\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */\r\n#define DMA2D_IFCR_CTWIF_Pos       (2U)\r\n#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */\r\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_IFCR_CAECIF_Pos      (3U)\r\n#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */\r\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)\r\n#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */\r\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_IFCR_CCEIF_Pos       (5U)\r\n#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */\r\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\r\n\r\n#define DMA2D_FGMAR_MA_Pos         (0U)\r\n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */\r\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_FGOR register  ****************/\r\n\r\n#define DMA2D_FGOR_LO_Pos          (0U)\r\n#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */\r\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\r\n\r\n#define DMA2D_BGMAR_MA_Pos         (0U)\r\n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */\r\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGOR register  ****************/\r\n\r\n#define DMA2D_BGOR_LO_Pos          (0U)\r\n#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */\r\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\r\n\r\n#define DMA2D_FGPFCCR_CM_Pos       (0U)\r\n#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */\r\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\r\n#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)\r\n#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */\r\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\r\n#define DMA2D_FGPFCCR_START_Pos    (5U)\r\n#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */\r\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\r\n#define DMA2D_FGPFCCR_CS_Pos       (8U)\r\n#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */\r\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\r\n#define DMA2D_FGPFCCR_AM_Pos       (16U)\r\n#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */\r\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\r\n#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\r\n#define DMA2D_FGPFCCR_CSS_Pos      (18U)\r\n#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */\r\n#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */\r\n#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */\r\n#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */\r\n#define DMA2D_FGPFCCR_AI_Pos       (20U)\r\n#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */\r\n#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */\r\n#define DMA2D_FGPFCCR_RBS_Pos      (21U)\r\n#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */\r\n#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */\r\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)\r\n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */\r\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\r\n\r\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)\r\n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */\r\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */\r\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)\r\n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */\r\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */\r\n#define DMA2D_FGCOLR_RED_Pos       (16U)\r\n#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */\r\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */\r\n\r\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\r\n\r\n#define DMA2D_BGPFCCR_CM_Pos       (0U)\r\n#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */\r\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\r\n#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)\r\n#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */\r\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\r\n#define DMA2D_BGPFCCR_START_Pos    (5U)\r\n#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */\r\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\r\n#define DMA2D_BGPFCCR_CS_Pos       (8U)\r\n#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */\r\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\r\n#define DMA2D_BGPFCCR_AM_Pos       (16U)\r\n#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */\r\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\r\n#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\r\n#define DMA2D_BGPFCCR_AI_Pos       (20U)\r\n#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */\r\n#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */\r\n#define DMA2D_BGPFCCR_RBS_Pos      (21U)\r\n#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */\r\n#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */\r\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)\r\n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */\r\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\r\n\r\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)\r\n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */\r\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */\r\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)\r\n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */\r\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */\r\n#define DMA2D_BGCOLR_RED_Pos       (16U)\r\n#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */\r\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */\r\n\r\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\r\n\r\n#define DMA2D_FGCMAR_MA_Pos        (0U)\r\n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */\r\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\r\n\r\n#define DMA2D_BGCMAR_MA_Pos        (0U)\r\n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */\r\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\r\n\r\n#define DMA2D_OPFCCR_CM_Pos        (0U)\r\n#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */\r\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */\r\n#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_OPFCCR_SB_Pos        (8U)\r\n#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */\r\n#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */\r\n#define DMA2D_OPFCCR_AI_Pos        (20U)\r\n#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */\r\n#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */\r\n#define DMA2D_OPFCCR_RBS_Pos       (21U)\r\n#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */\r\n#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */\r\n\r\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\r\n\r\n/*!<Mode_ARGB8888/RGB888 */\r\n\r\n#define DMA2D_OCOLR_BLUE_1_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/\r\n#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_1_Pos    (8U)\r\n#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/\r\n#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_1_Pos      (16U)\r\n#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */\r\n#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */\r\n#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)\r\n#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/\r\n#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */\r\n\r\n/*!<Mode_RGB565 */\r\n#define DMA2D_OCOLR_BLUE_2_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/\r\n#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_2_Pos    (5U)\r\n#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */\r\n#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_2_Pos      (11U)\r\n#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/\r\n#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */\r\n\r\n/*!<Mode_ARGB1555 */\r\n#define DMA2D_OCOLR_BLUE_3_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/\r\n#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_3_Pos    (5U)\r\n#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/\r\n#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_3_Pos      (10U)\r\n#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/\r\n#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */\r\n#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)\r\n#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/\r\n#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */\r\n\r\n/*!<Mode_ARGB4444 */\r\n#define DMA2D_OCOLR_BLUE_4_Pos     (0U)\r\n#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/\r\n#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_4_Pos    (4U)\r\n#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/\r\n#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */\r\n#define DMA2D_OCOLR_RED_4_Pos      (8U)\r\n#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/\r\n#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */\r\n#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)\r\n#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/\r\n#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */\r\n\r\n/********************  Bit definition for DMA2D_OMAR register  ****************/\r\n\r\n#define DMA2D_OMAR_MA_Pos          (0U)\r\n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */\r\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OOR register  *****************/\r\n\r\n#define DMA2D_OOR_LO_Pos           (0U)\r\n#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */\r\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_NLR register  *****************/\r\n\r\n#define DMA2D_NLR_NL_Pos           (0U)\r\n#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */\r\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\r\n#define DMA2D_NLR_PL_Pos           (16U)\r\n#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */\r\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\r\n\r\n/********************  Bit definition for DMA2D_LWR register  *****************/\r\n\r\n#define DMA2D_LWR_LW_Pos           (0U)\r\n#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */\r\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\r\n\r\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\r\n\r\n#define DMA2D_AMTCR_EN_Pos         (0U)\r\n#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\r\n#define DMA2D_AMTCR_DT_Pos         (8U)\r\n#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */\r\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\r\n\r\n\r\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\r\n\r\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                    External Interrupt/Event Controller                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for EXTI_RTSR1 register  *******************/\r\n#define EXTI_RTSR1_TR_Pos          (0U)\r\n#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */\r\n#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */\r\n#define EXTI_RTSR1_TR0_Pos         (0U)\r\n#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */\r\n#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */\r\n#define EXTI_RTSR1_TR1_Pos         (1U)\r\n#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */\r\n#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */\r\n#define EXTI_RTSR1_TR2_Pos         (2U)\r\n#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */\r\n#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */\r\n#define EXTI_RTSR1_TR3_Pos         (3U)\r\n#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */\r\n#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */\r\n#define EXTI_RTSR1_TR4_Pos         (4U)\r\n#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */\r\n#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */\r\n#define EXTI_RTSR1_TR5_Pos         (5U)\r\n#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */\r\n#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */\r\n#define EXTI_RTSR1_TR6_Pos         (6U)\r\n#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */\r\n#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */\r\n#define EXTI_RTSR1_TR7_Pos         (7U)\r\n#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */\r\n#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */\r\n#define EXTI_RTSR1_TR8_Pos         (8U)\r\n#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */\r\n#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */\r\n#define EXTI_RTSR1_TR9_Pos         (9U)\r\n#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */\r\n#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */\r\n#define EXTI_RTSR1_TR10_Pos        (10U)\r\n#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */\r\n#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */\r\n#define EXTI_RTSR1_TR11_Pos        (11U)\r\n#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */\r\n#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */\r\n#define EXTI_RTSR1_TR12_Pos        (12U)\r\n#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */\r\n#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */\r\n#define EXTI_RTSR1_TR13_Pos        (13U)\r\n#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */\r\n#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */\r\n#define EXTI_RTSR1_TR14_Pos        (14U)\r\n#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */\r\n#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */\r\n#define EXTI_RTSR1_TR15_Pos        (15U)\r\n#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */\r\n#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */\r\n#define EXTI_RTSR1_TR16_Pos        (16U)\r\n#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */\r\n#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */\r\n#define EXTI_RTSR1_TR17_Pos        (17U)\r\n#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */\r\n#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */\r\n#define EXTI_RTSR1_TR18_Pos        (18U)\r\n#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */\r\n#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */\r\n#define EXTI_RTSR1_TR19_Pos        (19U)\r\n#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */\r\n#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */\r\n#define EXTI_RTSR1_TR20_Pos        (20U)\r\n#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */\r\n#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */\r\n#define EXTI_RTSR1_TR21_Pos        (21U)\r\n#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */\r\n#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */\r\n\r\n/******************  Bit definition for EXTI_FTSR1 register  *******************/\r\n#define EXTI_FTSR1_TR_Pos          (0U)\r\n#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */\r\n#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */\r\n#define EXTI_FTSR1_TR0_Pos         (0U)\r\n#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */\r\n#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */\r\n#define EXTI_FTSR1_TR1_Pos         (1U)\r\n#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */\r\n#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */\r\n#define EXTI_FTSR1_TR2_Pos         (2U)\r\n#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */\r\n#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */\r\n#define EXTI_FTSR1_TR3_Pos         (3U)\r\n#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */\r\n#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */\r\n#define EXTI_FTSR1_TR4_Pos         (4U)\r\n#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */\r\n#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */\r\n#define EXTI_FTSR1_TR5_Pos         (5U)\r\n#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */\r\n#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */\r\n#define EXTI_FTSR1_TR6_Pos         (6U)\r\n#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */\r\n#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */\r\n#define EXTI_FTSR1_TR7_Pos         (7U)\r\n#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */\r\n#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */\r\n#define EXTI_FTSR1_TR8_Pos         (8U)\r\n#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */\r\n#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */\r\n#define EXTI_FTSR1_TR9_Pos         (9U)\r\n#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */\r\n#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */\r\n#define EXTI_FTSR1_TR10_Pos        (10U)\r\n#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */\r\n#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */\r\n#define EXTI_FTSR1_TR11_Pos        (11U)\r\n#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */\r\n#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */\r\n#define EXTI_FTSR1_TR12_Pos        (12U)\r\n#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */\r\n#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */\r\n#define EXTI_FTSR1_TR13_Pos        (13U)\r\n#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */\r\n#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */\r\n#define EXTI_FTSR1_TR14_Pos        (14U)\r\n#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */\r\n#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */\r\n#define EXTI_FTSR1_TR15_Pos        (15U)\r\n#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */\r\n#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */\r\n#define EXTI_FTSR1_TR16_Pos        (16U)\r\n#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */\r\n#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */\r\n#define EXTI_FTSR1_TR17_Pos        (17U)\r\n#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */\r\n#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */\r\n#define EXTI_FTSR1_TR18_Pos        (18U)\r\n#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */\r\n#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */\r\n#define EXTI_FTSR1_TR19_Pos        (19U)\r\n#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */\r\n#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */\r\n#define EXTI_FTSR1_TR20_Pos        (20U)\r\n#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */\r\n#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */\r\n#define EXTI_FTSR1_TR21_Pos        (21U)\r\n#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */\r\n#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */\r\n\r\n/******************  Bit definition for EXTI_SWIER1 register  ******************/\r\n#define EXTI_SWIER1_SWIER0_Pos     (0U)\r\n#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */\r\n#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */\r\n#define EXTI_SWIER1_SWIER1_Pos     (1U)\r\n#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */\r\n#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */\r\n#define EXTI_SWIER1_SWIER2_Pos     (2U)\r\n#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */\r\n#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */\r\n#define EXTI_SWIER1_SWIER3_Pos     (3U)\r\n#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */\r\n#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */\r\n#define EXTI_SWIER1_SWIER4_Pos     (4U)\r\n#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */\r\n#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */\r\n#define EXTI_SWIER1_SWIER5_Pos     (5U)\r\n#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */\r\n#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */\r\n#define EXTI_SWIER1_SWIER6_Pos     (6U)\r\n#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */\r\n#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */\r\n#define EXTI_SWIER1_SWIER7_Pos     (7U)\r\n#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */\r\n#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */\r\n#define EXTI_SWIER1_SWIER8_Pos     (8U)\r\n#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */\r\n#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */\r\n#define EXTI_SWIER1_SWIER9_Pos     (9U)\r\n#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */\r\n#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */\r\n#define EXTI_SWIER1_SWIER10_Pos    (10U)\r\n#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */\r\n#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */\r\n#define EXTI_SWIER1_SWIER11_Pos    (11U)\r\n#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */\r\n#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */\r\n#define EXTI_SWIER1_SWIER12_Pos    (12U)\r\n#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */\r\n#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */\r\n#define EXTI_SWIER1_SWIER13_Pos    (13U)\r\n#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */\r\n#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */\r\n#define EXTI_SWIER1_SWIER14_Pos    (14U)\r\n#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */\r\n#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */\r\n#define EXTI_SWIER1_SWIER15_Pos    (15U)\r\n#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */\r\n#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */\r\n#define EXTI_SWIER1_SWIER16_Pos    (16U)\r\n#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */\r\n#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */\r\n#define EXTI_SWIER1_SWIER17_Pos    (17U)\r\n#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */\r\n#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */\r\n#define EXTI_SWIER1_SWIER18_Pos    (18U)\r\n#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */\r\n#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */\r\n#define EXTI_SWIER1_SWIER19_Pos    (19U)\r\n#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */\r\n#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */\r\n#define EXTI_SWIER1_SWIER20_Pos    (20U)\r\n#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */\r\n#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */\r\n#define EXTI_SWIER1_SWIER21_Pos    (21U)\r\n#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */\r\n#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */\r\n\r\n/******************  Bit definition for EXTI_D3PMR1 register  ******************/\r\n#define EXTI_D3PMR1_MR0_Pos        (0U)\r\n#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */\r\n#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */\r\n#define EXTI_D3PMR1_MR1_Pos        (1U)\r\n#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */\r\n#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */\r\n#define EXTI_D3PMR1_MR2_Pos        (2U)\r\n#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */\r\n#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */\r\n#define EXTI_D3PMR1_MR3_Pos        (3U)\r\n#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */\r\n#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */\r\n#define EXTI_D3PMR1_MR4_Pos        (4U)\r\n#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */\r\n#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */\r\n#define EXTI_D3PMR1_MR5_Pos        (5U)\r\n#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */\r\n#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */\r\n#define EXTI_D3PMR1_MR6_Pos        (6U)\r\n#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */\r\n#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */\r\n#define EXTI_D3PMR1_MR7_Pos        (7U)\r\n#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */\r\n#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */\r\n#define EXTI_D3PMR1_MR8_Pos        (8U)\r\n#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */\r\n#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */\r\n#define EXTI_D3PMR1_MR9_Pos        (9U)\r\n#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */\r\n#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */\r\n#define EXTI_D3PMR1_MR10_Pos       (10U)\r\n#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */\r\n#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */\r\n#define EXTI_D3PMR1_MR11_Pos       (11U)\r\n#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */\r\n#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */\r\n#define EXTI_D3PMR1_MR12_Pos       (12U)\r\n#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */\r\n#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */\r\n#define EXTI_D3PMR1_MR13_Pos       (13U)\r\n#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */\r\n#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */\r\n#define EXTI_D3PMR1_MR14_Pos       (14U)\r\n#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */\r\n#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */\r\n#define EXTI_D3PMR1_MR15_Pos       (15U)\r\n#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */\r\n#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */\r\n#define EXTI_D3PMR1_MR19_Pos       (19U)\r\n#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */\r\n#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */\r\n#define EXTI_D3PMR1_MR20_Pos       (20U)\r\n#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */\r\n#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */\r\n#define EXTI_D3PMR1_MR21_Pos       (21U)\r\n#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */\r\n#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */\r\n#define EXTI_D3PMR1_MR25_Pos       (24U)\r\n#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */\r\n#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */\r\n\r\n/*******************  Bit definition for EXTI_D3PCR1L register  ****************/\r\n#define EXTI_D3PCR1L_PCS0_Pos       (0U)\r\n#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */\r\n#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */\r\n#define EXTI_D3PCR1L_PCS1_Pos       (2U)\r\n#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */\r\n#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */\r\n#define EXTI_D3PCR1L_PCS2_Pos       (4U)\r\n#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */\r\n#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */\r\n#define EXTI_D3PCR1L_PCS3_Pos       (6U)\r\n#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */\r\n#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */\r\n#define EXTI_D3PCR1L_PCS4_Pos       (8U)\r\n#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */\r\n#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */\r\n#define EXTI_D3PCR1L_PCS5_Pos       (10U)\r\n#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */\r\n#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */\r\n#define EXTI_D3PCR1L_PCS6_Pos       (12U)\r\n#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */\r\n#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */\r\n#define EXTI_D3PCR1L_PCS7_Pos       (14U)\r\n#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */\r\n#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */\r\n#define EXTI_D3PCR1L_PCS8_Pos       (16U)\r\n#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */\r\n#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */\r\n#define EXTI_D3PCR1L_PCS9_Pos       (18U)\r\n#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */\r\n#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */\r\n#define EXTI_D3PCR1L_PCS10_Pos      (20U)\r\n#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */\r\n#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/\r\n#define EXTI_D3PCR1L_PCS11_Pos      (22U)\r\n#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */\r\n#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/\r\n#define EXTI_D3PCR1L_PCS12_Pos      (24U)\r\n#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */\r\n#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/\r\n#define EXTI_D3PCR1L_PCS13_Pos      (26U)\r\n#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */\r\n#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/\r\n#define EXTI_D3PCR1L_PCS14_Pos      (28U)\r\n#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */\r\n#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/\r\n#define EXTI_D3PCR1L_PCS15_Pos      (30U)\r\n#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */\r\n#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/\r\n\r\n/*******************  Bit definition for EXTI_D3PCR1H register  ****************/\r\n#define EXTI_D3PCR1H_PCS19_Pos       (6U)\r\n#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */\r\n#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */\r\n#define EXTI_D3PCR1H_PCS20_Pos       (8U)\r\n#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */\r\n#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */\r\n#define EXTI_D3PCR1H_PCS21_Pos       (10U)\r\n#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */\r\n#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */\r\n#define EXTI_D3PCR1H_PCS25_Pos       (18U)\r\n#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */\r\n#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */\r\n\r\n/******************  Bit definition for EXTI_RTSR2 register  *******************/\r\n#define EXTI_RTSR2_TR_Pos          (17U)\r\n#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */\r\n#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */\r\n#define EXTI_RTSR2_TR49_Pos        (17U)\r\n#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */\r\n#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */\r\n#define EXTI_RTSR2_TR51_Pos        (19U)\r\n#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */\r\n#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */\r\n\r\n/******************  Bit definition for EXTI_FTSR2 register  *******************/\r\n#define EXTI_FTSR2_TR_Pos          (17U)\r\n#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */\r\n#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */\r\n#define EXTI_FTSR2_TR49_Pos        (17U)\r\n#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */\r\n#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */\r\n#define EXTI_FTSR2_TR51_Pos        (19U)\r\n#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */\r\n#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */\r\n\r\n/******************  Bit definition for EXTI_SWIER2 register  ******************/\r\n#define EXTI_SWIER2_SWIER49_Pos    (17U)\r\n#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */\r\n#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */\r\n#define EXTI_SWIER2_SWIER51_Pos    (19U)\r\n#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */\r\n#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */\r\n\r\n/******************  Bit definition for EXTI_D3PMR2 register  ******************/\r\n#define EXTI_D3PMR2_MR34_Pos       (2U)\r\n#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */\r\n#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */\r\n#define EXTI_D3PMR2_MR35_Pos       (3U)\r\n#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */\r\n#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */\r\n#define EXTI_D3PMR2_MR41_Pos       (9U)\r\n#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */\r\n#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */\r\n#define EXTI_D3PMR2_MR48_Pos       (16U)\r\n#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */\r\n#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */\r\n#define EXTI_D3PMR2_MR49_Pos       (17U)\r\n#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */\r\n#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */\r\n#define EXTI_D3PMR2_MR50_Pos       (18U)\r\n#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */\r\n#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */\r\n#define EXTI_D3PMR2_MR51_Pos       (19U)\r\n#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */\r\n#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */\r\n#define EXTI_D3PMR2_MR52_Pos       (20U)\r\n#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */\r\n#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */\r\n#define EXTI_D3PMR2_MR53_Pos       (21U)\r\n#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */\r\n#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */\r\n/*******************  Bit definition for EXTI_D3PCR2L register  ****************/\r\n#define EXTI_D3PCR2L_PCS34_Pos       (4U)\r\n#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */\r\n#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */\r\n#define EXTI_D3PCR2L_PCS35_Pos       (6U)\r\n#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */\r\n#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */\r\n#define EXTI_D3PCR2L_PCS41_Pos       (18U)\r\n#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */\r\n#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */\r\n\r\n\r\n/*******************  Bit definition for EXTI_D3PCR2H register  ****************/\r\n#define EXTI_D3PCR2H_PCS48_Pos       (0U)\r\n#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */\r\n#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */\r\n#define EXTI_D3PCR2H_PCS49_Pos       (2U)\r\n#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */\r\n#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */\r\n#define EXTI_D3PCR2H_PCS50_Pos       (4U)\r\n#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */\r\n#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */\r\n#define EXTI_D3PCR2H_PCS51_Pos       (6U)\r\n#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */\r\n#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */\r\n#define EXTI_D3PCR2H_PCS52_Pos       (8U)\r\n#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */\r\n#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */\r\n#define EXTI_D3PCR2H_PCS53_Pos       (10U)\r\n#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */\r\n#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */\r\n/******************  Bit definition for EXTI_RTSR3 register  *******************/\r\n#define EXTI_RTSR3_TR_Pos          (21U)\r\n#define EXTI_RTSR3_TR_Msk          (0x3UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00600000 */\r\n#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */\r\n#define EXTI_RTSR3_TR85_Pos        (21U)\r\n#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */\r\n#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */\r\n#define EXTI_RTSR3_TR86_Pos        (22U)\r\n#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */\r\n#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */\r\n\r\n/******************  Bit definition for EXTI_FTSR3 register  *******************/\r\n#define EXTI_FTSR3_TR_Pos          (21U)\r\n#define EXTI_FTSR3_TR_Msk          (0x3UL << EXTI_FTSR3_TR_Pos)               /*!< 0x00600000 */\r\n#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */\r\n#define EXTI_FTSR3_TR85_Pos        (21U)\r\n#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */\r\n#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */\r\n#define EXTI_FTSR3_TR86_Pos        (22U)\r\n#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */\r\n#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */\r\n\r\n/******************  Bit definition for EXTI_SWIER3 register  ******************/\r\n#define EXTI_SWIER3_SWI_Pos        (21U)\r\n#define EXTI_SWIER3_SWI_Msk        (0x3UL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00600000 */\r\n#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */\r\n#define EXTI_SWIER3_SWIER85_Pos    (21U)\r\n#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */\r\n#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */\r\n#define EXTI_SWIER3_SWIER86_Pos    (22U)\r\n#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */\r\n#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */\r\n\r\n/******************  Bit definition for EXTI_D3PMR3 register  ******************/\r\n#define EXTI_D3PMR3_MR88_Pos       (24U)\r\n#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */\r\n#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */\r\n\r\n/*******************  Bit definition for EXTI_D3PCR3H register  ****************/\r\n#define EXTI_D3PCR3H_PCS88_Pos       (16U)\r\n#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */\r\n#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */\r\n\r\n/*******************  Bit definition for EXTI_IMR1 register  *******************/\r\n#define EXTI_IMR1_IM_Pos           (0U)\r\n#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */\r\n#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */\r\n#define EXTI_IMR1_IM0_Pos          (0U)\r\n#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */\r\n#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */\r\n#define EXTI_IMR1_IM1_Pos          (1U)\r\n#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */\r\n#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */\r\n#define EXTI_IMR1_IM2_Pos          (2U)\r\n#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */\r\n#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */\r\n#define EXTI_IMR1_IM3_Pos          (3U)\r\n#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */\r\n#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */\r\n#define EXTI_IMR1_IM4_Pos          (4U)\r\n#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */\r\n#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */\r\n#define EXTI_IMR1_IM5_Pos          (5U)\r\n#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */\r\n#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */\r\n#define EXTI_IMR1_IM6_Pos          (6U)\r\n#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */\r\n#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */\r\n#define EXTI_IMR1_IM7_Pos          (7U)\r\n#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */\r\n#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */\r\n#define EXTI_IMR1_IM8_Pos          (8U)\r\n#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */\r\n#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */\r\n#define EXTI_IMR1_IM9_Pos          (9U)\r\n#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */\r\n#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */\r\n#define EXTI_IMR1_IM10_Pos         (10U)\r\n#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */\r\n#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */\r\n#define EXTI_IMR1_IM11_Pos         (11U)\r\n#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */\r\n#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */\r\n#define EXTI_IMR1_IM12_Pos         (12U)\r\n#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */\r\n#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */\r\n#define EXTI_IMR1_IM13_Pos         (13U)\r\n#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */\r\n#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */\r\n#define EXTI_IMR1_IM14_Pos         (14U)\r\n#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */\r\n#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */\r\n#define EXTI_IMR1_IM15_Pos         (15U)\r\n#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */\r\n#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */\r\n#define EXTI_IMR1_IM16_Pos         (16U)\r\n#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */\r\n#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */\r\n#define EXTI_IMR1_IM17_Pos         (17U)\r\n#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */\r\n#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */\r\n#define EXTI_IMR1_IM18_Pos         (18U)\r\n#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */\r\n#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */\r\n#define EXTI_IMR1_IM19_Pos         (19U)\r\n#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */\r\n#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */\r\n#define EXTI_IMR1_IM20_Pos         (20U)\r\n#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */\r\n#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */\r\n#define EXTI_IMR1_IM21_Pos         (21U)\r\n#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */\r\n#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */\r\n#define EXTI_IMR1_IM22_Pos         (22U)\r\n#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */\r\n#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */\r\n#define EXTI_IMR1_IM23_Pos         (23U)\r\n#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */\r\n#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */\r\n#define EXTI_IMR1_IM24_Pos         (24U)\r\n#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */\r\n#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */\r\n#define EXTI_IMR1_IM25_Pos         (25U)\r\n#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */\r\n#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */\r\n#define EXTI_IMR1_IM26_Pos         (26U)\r\n#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */\r\n#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */\r\n#define EXTI_IMR1_IM27_Pos         (27U)\r\n#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */\r\n#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */\r\n#define EXTI_IMR1_IM28_Pos         (28U)\r\n#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */\r\n#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */\r\n#define EXTI_IMR1_IM29_Pos         (29U)\r\n#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */\r\n#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */\r\n#define EXTI_IMR1_IM30_Pos         (30U)\r\n#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */\r\n#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */\r\n#define EXTI_IMR1_IM31_Pos         (31U)\r\n#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */\r\n#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */\r\n\r\n/*******************  Bit definition for EXTI_EMR1 register  *******************/\r\n#define EXTI_EMR1_EM_Pos           (0U)\r\n#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */\r\n#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */\r\n#define EXTI_EMR1_EM0_Pos          (0U)\r\n#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */\r\n#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */\r\n#define EXTI_EMR1_EM1_Pos          (1U)\r\n#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */\r\n#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */\r\n#define EXTI_EMR1_EM2_Pos          (2U)\r\n#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */\r\n#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */\r\n#define EXTI_EMR1_EM3_Pos          (3U)\r\n#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */\r\n#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */\r\n#define EXTI_EMR1_EM4_Pos          (4U)\r\n#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */\r\n#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */\r\n#define EXTI_EMR1_EM5_Pos          (5U)\r\n#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */\r\n#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */\r\n#define EXTI_EMR1_EM6_Pos          (6U)\r\n#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */\r\n#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */\r\n#define EXTI_EMR1_EM7_Pos          (7U)\r\n#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */\r\n#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */\r\n#define EXTI_EMR1_EM8_Pos          (8U)\r\n#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */\r\n#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */\r\n#define EXTI_EMR1_EM9_Pos          (9U)\r\n#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */\r\n#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */\r\n#define EXTI_EMR1_EM10_Pos         (10U)\r\n#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */\r\n#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */\r\n#define EXTI_EMR1_EM11_Pos         (11U)\r\n#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */\r\n#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */\r\n#define EXTI_EMR1_EM12_Pos         (12U)\r\n#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */\r\n#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */\r\n#define EXTI_EMR1_EM13_Pos         (13U)\r\n#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */\r\n#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */\r\n#define EXTI_EMR1_EM14_Pos         (14U)\r\n#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */\r\n#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */\r\n#define EXTI_EMR1_EM15_Pos         (15U)\r\n#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */\r\n#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */\r\n#define EXTI_EMR1_EM16_Pos         (16U)\r\n#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */\r\n#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */\r\n#define EXTI_EMR1_EM17_Pos         (17U)\r\n#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */\r\n#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */\r\n#define EXTI_EMR1_EM18_Pos         (18U)\r\n#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */\r\n#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */\r\n#define EXTI_EMR1_EM20_Pos         (20U)\r\n#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */\r\n#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */\r\n#define EXTI_EMR1_EM21_Pos         (21U)\r\n#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */\r\n#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */\r\n#define EXTI_EMR1_EM22_Pos         (22U)\r\n#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */\r\n#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */\r\n#define EXTI_EMR1_EM23_Pos         (23U)\r\n#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */\r\n#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */\r\n#define EXTI_EMR1_EM24_Pos         (24U)\r\n#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */\r\n#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */\r\n#define EXTI_EMR1_EM25_Pos         (25U)\r\n#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */\r\n#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */\r\n#define EXTI_EMR1_EM26_Pos         (26U)\r\n#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */\r\n#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */\r\n#define EXTI_EMR1_EM27_Pos         (27U)\r\n#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */\r\n#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */\r\n#define EXTI_EMR1_EM28_Pos         (28U)\r\n#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */\r\n#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */\r\n#define EXTI_EMR1_EM29_Pos         (29U)\r\n#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */\r\n#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */\r\n#define EXTI_EMR1_EM30_Pos         (30U)\r\n#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */\r\n#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */\r\n#define EXTI_EMR1_EM31_Pos         (31U)\r\n#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */\r\n#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */\r\n\r\n/*******************  Bit definition for EXTI_PR1 register  ********************/\r\n#define EXTI_PR1_PR_Pos            (0U)\r\n#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */\r\n#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */\r\n#define EXTI_PR1_PR0_Pos           (0U)\r\n#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */\r\n#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */\r\n#define EXTI_PR1_PR1_Pos           (1U)\r\n#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */\r\n#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */\r\n#define EXTI_PR1_PR2_Pos           (2U)\r\n#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */\r\n#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */\r\n#define EXTI_PR1_PR3_Pos           (3U)\r\n#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */\r\n#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */\r\n#define EXTI_PR1_PR4_Pos           (4U)\r\n#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */\r\n#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */\r\n#define EXTI_PR1_PR5_Pos           (5U)\r\n#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */\r\n#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */\r\n#define EXTI_PR1_PR6_Pos           (6U)\r\n#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */\r\n#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */\r\n#define EXTI_PR1_PR7_Pos           (7U)\r\n#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */\r\n#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */\r\n#define EXTI_PR1_PR8_Pos           (8U)\r\n#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */\r\n#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */\r\n#define EXTI_PR1_PR9_Pos           (9U)\r\n#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */\r\n#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */\r\n#define EXTI_PR1_PR10_Pos          (10U)\r\n#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */\r\n#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */\r\n#define EXTI_PR1_PR11_Pos          (11U)\r\n#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */\r\n#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */\r\n#define EXTI_PR1_PR12_Pos          (12U)\r\n#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */\r\n#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */\r\n#define EXTI_PR1_PR13_Pos          (13U)\r\n#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */\r\n#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */\r\n#define EXTI_PR1_PR14_Pos          (14U)\r\n#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */\r\n#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */\r\n#define EXTI_PR1_PR15_Pos          (15U)\r\n#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */\r\n#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */\r\n#define EXTI_PR1_PR16_Pos          (16U)\r\n#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */\r\n#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */\r\n#define EXTI_PR1_PR17_Pos          (17U)\r\n#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */\r\n#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */\r\n#define EXTI_PR1_PR18_Pos          (18U)\r\n#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */\r\n#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */\r\n#define EXTI_PR1_PR19_Pos          (19U)\r\n#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */\r\n#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */\r\n#define EXTI_PR1_PR20_Pos          (20U)\r\n#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */\r\n#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */\r\n#define EXTI_PR1_PR21_Pos          (21U)\r\n#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */\r\n#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */\r\n\r\n/*******************  Bit definition for EXTI_IMR2 register  *******************/\r\n#define EXTI_IMR2_IM_Pos           (0U)\r\n#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */\r\n#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */\r\n#define EXTI_IMR2_IM32_Pos         (0U)\r\n#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */\r\n#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */\r\n#define EXTI_IMR2_IM33_Pos         (1U)\r\n#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */\r\n#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */\r\n#define EXTI_IMR2_IM34_Pos         (2U)\r\n#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */\r\n#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */\r\n#define EXTI_IMR2_IM35_Pos         (3U)\r\n#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */\r\n#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */\r\n#define EXTI_IMR2_IM36_Pos         (4U)\r\n#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */\r\n#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */\r\n#define EXTI_IMR2_IM37_Pos         (5U)\r\n#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */\r\n#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */\r\n#define EXTI_IMR2_IM38_Pos         (6U)\r\n#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */\r\n#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */\r\n#define EXTI_IMR2_IM39_Pos         (7U)\r\n#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */\r\n#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */\r\n#define EXTI_IMR2_IM40_Pos         (8U)\r\n#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */\r\n#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */\r\n#define EXTI_IMR2_IM41_Pos         (9U)\r\n#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */\r\n#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */\r\n#define EXTI_IMR2_IM42_Pos         (10U)\r\n#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */\r\n#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */\r\n#define EXTI_IMR2_IM43_Pos         (11U)\r\n#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */\r\n#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */\r\n#define EXTI_IMR2_IM47_Pos         (15U)\r\n#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */\r\n#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */\r\n#define EXTI_IMR2_IM48_Pos         (16U)\r\n#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */\r\n#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */\r\n#define EXTI_IMR2_IM49_Pos         (17U)\r\n#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */\r\n#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */\r\n#define EXTI_IMR2_IM50_Pos         (18U)\r\n#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */\r\n#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */\r\n#define EXTI_IMR2_IM51_Pos         (19U)\r\n#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */\r\n#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */\r\n#define EXTI_IMR2_IM52_Pos         (20U)\r\n#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */\r\n#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */\r\n#define EXTI_IMR2_IM53_Pos         (21U)\r\n#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */\r\n#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */\r\n#define EXTI_IMR2_IM54_Pos         (22U)\r\n#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */\r\n#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */\r\n#define EXTI_IMR2_IM55_Pos         (23U)\r\n#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */\r\n#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */\r\n#define EXTI_IMR2_IM56_Pos         (24U)\r\n#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */\r\n#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */\r\n#define EXTI_IMR2_IM58_Pos         (26U)\r\n#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */\r\n#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */\r\n#define EXTI_IMR2_IM60_Pos         (28U)\r\n#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */\r\n#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */\r\n#define EXTI_IMR2_IM61_Pos         (29U)\r\n#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */\r\n#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */\r\n#define EXTI_IMR2_IM62_Pos         (30U)\r\n#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */\r\n#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */\r\n#define EXTI_IMR2_IM63_Pos         (31U)\r\n#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */\r\n#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */\r\n\r\n/*******************  Bit definition for EXTI_EMR2 register  *******************/\r\n#define EXTI_EMR2_EM_Pos           (0U)\r\n#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */\r\n#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */\r\n#define EXTI_EMR2_EM32_Pos         (0U)\r\n#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */\r\n#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/\r\n#define EXTI_EMR2_EM33_Pos         (1U)\r\n#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */\r\n#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/\r\n#define EXTI_EMR2_EM34_Pos         (2U)\r\n#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */\r\n#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/\r\n#define EXTI_EMR2_EM35_Pos         (3U)\r\n#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */\r\n#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/\r\n#define EXTI_EMR2_EM36_Pos         (4U)\r\n#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */\r\n#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/\r\n#define EXTI_EMR2_EM37_Pos         (5U)\r\n#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */\r\n#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/\r\n#define EXTI_EMR2_EM38_Pos         (6U)\r\n#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */\r\n#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/\r\n#define EXTI_EMR2_EM39_Pos         (7U)\r\n#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */\r\n#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/\r\n#define EXTI_EMR2_EM40_Pos         (8U)\r\n#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */\r\n#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/\r\n#define EXTI_EMR2_EM41_Pos         (9U)\r\n#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */\r\n#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/\r\n#define EXTI_EMR2_EM42_Pos         (10U)\r\n#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */\r\n#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */\r\n#define EXTI_EMR2_EM43_Pos         (11U)\r\n#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */\r\n#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */\r\n#define EXTI_EMR2_EM47_Pos         (15U)\r\n#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */\r\n#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */\r\n#define EXTI_EMR2_EM48_Pos         (16U)\r\n#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */\r\n#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */\r\n#define EXTI_EMR2_EM49_Pos         (17U)\r\n#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */\r\n#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */\r\n#define EXTI_EMR2_EM50_Pos         (18U)\r\n#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */\r\n#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */\r\n#define EXTI_EMR2_EM51_Pos         (19U)\r\n#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */\r\n#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */\r\n#define EXTI_EMR2_EM52_Pos         (20U)\r\n#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */\r\n#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */\r\n#define EXTI_EMR2_EM53_Pos         (21U)\r\n#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */\r\n#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */\r\n#define EXTI_EMR2_EM54_Pos         (22U)\r\n#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */\r\n#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */\r\n#define EXTI_EMR2_EM55_Pos         (23U)\r\n#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */\r\n#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */\r\n#define EXTI_EMR2_EM56_Pos         (24U)\r\n#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */\r\n#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */\r\n#define EXTI_EMR2_EM58_Pos         (26U)\r\n#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */\r\n#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */\r\n#define EXTI_EMR2_EM60_Pos         (28U)\r\n#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */\r\n#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */\r\n#define EXTI_EMR2_EM61_Pos         (29U)\r\n#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */\r\n#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */\r\n#define EXTI_EMR2_EM62_Pos         (30U)\r\n#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */\r\n#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */\r\n#define EXTI_EMR2_EM63_Pos         (31U)\r\n#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */\r\n#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */\r\n\r\n/*******************  Bit definition for EXTI_PR2 register  ********************/\r\n#define EXTI_PR2_PR_Pos            (17U)\r\n#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */\r\n#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */\r\n#define EXTI_PR2_PR49_Pos          (17U)\r\n#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */\r\n#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */\r\n#define EXTI_PR2_PR51_Pos          (19U)\r\n#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */\r\n#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */\r\n\r\n/*******************  Bit definition for EXTI_IMR3 register  *******************/\r\n#define EXTI_IMR3_IM_Pos           (0U)\r\n#define EXTI_IMR3_IM_Msk           (0x0FE17FFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x0FE17FFF */\r\n#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */\r\n#define EXTI_IMR3_IM64_Pos         (0U)\r\n#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */\r\n#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */\r\n#define EXTI_IMR3_IM65_Pos         (1U)\r\n#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */\r\n#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */\r\n#define EXTI_IMR3_IM66_Pos         (2U)\r\n#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */\r\n#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */\r\n#define EXTI_IMR3_IM67_Pos         (3U)\r\n#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */\r\n#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */\r\n#define EXTI_IMR3_IM68_Pos         (4U)\r\n#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */\r\n#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */\r\n#define EXTI_IMR3_IM69_Pos         (5U)\r\n#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */\r\n#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */\r\n#define EXTI_IMR3_IM70_Pos         (6U)\r\n#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */\r\n#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */\r\n#define EXTI_IMR3_IM71_Pos         (7U)\r\n#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */\r\n#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */\r\n#define EXTI_IMR3_IM72_Pos         (8U)\r\n#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */\r\n#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */\r\n#define EXTI_IMR3_IM73_Pos         (9U)\r\n#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */\r\n#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */\r\n#define EXTI_IMR3_IM74_Pos         (10U)\r\n#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */\r\n#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */\r\n#define EXTI_IMR3_IM75_Pos         (11U)\r\n#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */\r\n#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */\r\n#define EXTI_IMR3_IM76_Pos         (12U)\r\n#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */\r\n#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */\r\n#define EXTI_IMR3_IM77_Pos         (13U)\r\n#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */\r\n#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */\r\n#define EXTI_IMR3_IM78_Pos         (14U)\r\n#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */\r\n#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */\r\n#define EXTI_IMR3_IM80_Pos         (16U)\r\n#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */\r\n#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */\r\n#define EXTI_IMR3_IM85_Pos         (21U)\r\n#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */\r\n#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */\r\n#define EXTI_IMR3_IM86_Pos         (22U)\r\n#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */\r\n#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */\r\n#define EXTI_IMR3_IM87_Pos         (23U)\r\n#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */\r\n#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */\r\n\r\n\r\n#define EXTI_IMR3_IM88_Pos         (24U)\r\n#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */\r\n#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */\r\n\r\n#define EXTI_IMR3_IM89_Pos         (25U)\r\n#define EXTI_IMR3_IM89_Msk         (0x1UL << EXTI_IMR3_IM89_Pos)               /*!< 0x0200000 */\r\n#define EXTI_IMR3_IM89             EXTI_IMR3_IM89_Msk                          /*!< Interrupt Mask on line 89 */\r\n#define EXTI_IMR3_IM90_Pos         (26U)\r\n#define EXTI_IMR3_IM90_Msk         (0x1UL << EXTI_IMR3_IM90_Pos)               /*!< 0x0400000 */\r\n#define EXTI_IMR3_IM90             EXTI_IMR3_IM90_Msk                          /*!< Interrupt Mask on line 90 */\r\n#define EXTI_IMR3_IM91_Pos         (27U)\r\n#define EXTI_IMR3_IM91_Msk         (0x1UL << EXTI_IMR3_IM91_Pos)               /*!< 0x0800000 */\r\n#define EXTI_IMR3_IM91             EXTI_IMR3_IM91_Msk                          /*!< Interrupt Mask on line 91 */\r\n\r\n/*******************  Bit definition for EXTI_EMR3 register  *******************/\r\n#define EXTI_EMR3_EM_Pos           (0U)\r\n#define EXTI_EMR3_EM_Msk           (0x0FE17FFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x0FE17FFF */\r\n#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Interrupt Mask            */\r\n#define EXTI_EMR3_EM64_Pos         (0U)\r\n#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */\r\n#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/\r\n#define EXTI_EMR3_EM65_Pos         (1U)\r\n#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */\r\n#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/\r\n#define EXTI_EMR3_EM66_Pos         (2U)\r\n#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */\r\n#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/\r\n#define EXTI_EMR3_EM67_Pos         (3U)\r\n#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */\r\n#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/\r\n#define EXTI_EMR3_EM68_Pos         (4U)\r\n#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */\r\n#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/\r\n#define EXTI_EMR3_EM69_Pos         (5U)\r\n#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */\r\n#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/\r\n#define EXTI_EMR3_EM70_Pos         (6U)\r\n#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */\r\n#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/\r\n#define EXTI_EMR3_EM71_Pos         (7U)\r\n#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */\r\n#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/\r\n#define EXTI_EMR3_EM72_Pos         (8U)\r\n#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */\r\n#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/\r\n#define EXTI_EMR3_EM73_Pos         (9U)\r\n#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */\r\n#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/\r\n#define EXTI_EMR3_EM74_Pos         (10U)\r\n#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */\r\n#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */\r\n#define EXTI_EMR3_EM75_Pos         (11U)\r\n#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */\r\n#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */\r\n#define EXTI_EMR3_EM76_Pos         (12U)\r\n#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */\r\n#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */\r\n#define EXTI_EMR3_EM77_Pos         (13U)\r\n#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */\r\n#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */\r\n#define EXTI_EMR3_EM78_Pos         (14U)\r\n#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */\r\n#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */\r\n#define EXTI_EMR3_EM80_Pos         (16U)\r\n#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */\r\n#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */\r\n#define EXTI_EMR3_EM85_Pos         (21U)\r\n#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */\r\n#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */\r\n#define EXTI_EMR3_EM86_Pos         (22U)\r\n#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */\r\n#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */\r\n#define EXTI_EMR3_EM87_Pos         (23U)\r\n#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */\r\n#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */\r\n\r\n#define EXTI_EMR3_EM88_Pos         (24U)\r\n#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */\r\n#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */\r\n\r\n#define EXTI_EMR3_EM89_Pos         (25U)\r\n#define EXTI_EMR3_EM89_Msk         (0x1UL << EXTI_EMR3_EM89_Pos)               /*!< 0x0200000 */\r\n#define EXTI_EMR3_EM89             EXTI_EMR3_EM89_Msk                          /*!< Interrupt Mask on line 89 */\r\n#define EXTI_EMR3_EM90_Pos         (26U)\r\n#define EXTI_EMR3_EM90_Msk         (0x1UL << EXTI_EMR3_EM90_Pos)               /*!< 0x0400000 */\r\n#define EXTI_EMR3_EM90             EXTI_EMR3_EM90_Msk                          /*!< Interrupt Mask on line 90 */\r\n#define EXTI_EMR3_EM91_Pos         (27U)\r\n#define EXTI_EMR3_EM91_Msk         (0x1UL << EXTI_EMR3_EM91_Pos)               /*!< 0x0800000 */\r\n#define EXTI_EMR3_EM91             EXTI_EMR3_EM91_Msk                          /*!< Interrupt Mask on line 91 */\r\n\r\n/*******************  Bit definition for EXTI_PR3 register  ********************/\r\n#define EXTI_PR3_PR_Pos            (20U)\r\n#define EXTI_PR3_PR_Msk            (0x7UL << EXTI_PR3_PR_Pos)                  /*!< 0x00700000 */\r\n#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */\r\n#define EXTI_PR3_PR84_Pos          (20U)\r\n#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */\r\n#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */\r\n#define EXTI_PR3_PR85_Pos          (21U)\r\n#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */\r\n#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */\r\n#define EXTI_PR3_PR86_Pos          (22U)\r\n#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */\r\n#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    FLASH                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*\r\n* @brief FLASH Global Defines\r\n*/\r\n#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U\r\n#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */\r\n#define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \\\r\n                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \\\r\n                                             (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 1 MB   */\r\n#define FLASH_BANK_SIZE                      FLASH_SIZE            /* 1 MB   */\r\n#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB   */\r\n#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */\r\n#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */\r\n\r\n/*******************  Bits definition for FLASH_ACR register  **********************/\r\n#define FLASH_ACR_LATENCY_Pos                (0U)\r\n#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */\r\n#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */\r\n#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)\r\n#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)\r\n#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)\r\n#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)\r\n#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)\r\n#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)\r\n#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)\r\n#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)\r\n#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)\r\n#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)\r\n#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)\r\n#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)\r\n#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)\r\n#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)\r\n#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)\r\n#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)\r\n#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)\r\n#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */\r\n#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */\r\n#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */\r\n#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */\r\n\r\n/*******************  Bits definition for FLASH_CR register  ***********************/\r\n#define FLASH_CR_LOCK_Pos                    (0U)\r\n#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */\r\n#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */\r\n#define FLASH_CR_PG_Pos                      (1U)\r\n#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */\r\n#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */\r\n#define FLASH_CR_SER_Pos                     (2U)\r\n#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */\r\n#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */\r\n#define FLASH_CR_BER_Pos                     (3U)\r\n#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */\r\n#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */\r\n#define FLASH_CR_PSIZE_Pos                   (4U)\r\n#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */\r\n#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */\r\n#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */\r\n#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */\r\n#define FLASH_CR_FW_Pos                      (6U)\r\n#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */\r\n#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */\r\n#define FLASH_CR_START_Pos                   (7U)\r\n#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */\r\n#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */\r\n#define FLASH_CR_SNB_Pos                     (8U)\r\n#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */\r\n#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */\r\n#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */\r\n#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */\r\n#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */\r\n#define FLASH_CR_CRC_EN_Pos                  (15U)\r\n#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */\r\n#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */\r\n#define FLASH_CR_EOPIE_Pos                   (16U)\r\n#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */\r\n#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */\r\n#define FLASH_CR_WRPERRIE_Pos                (17U)\r\n#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */\r\n#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */\r\n#define FLASH_CR_PGSERRIE_Pos                (18U)\r\n#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */\r\n#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */\r\n#define FLASH_CR_STRBERRIE_Pos               (19U)\r\n#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */\r\n#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */\r\n#define FLASH_CR_INCERRIE_Pos                (21U)\r\n#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */\r\n#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */\r\n#define FLASH_CR_OPERRIE_Pos                 (22U)\r\n#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */\r\n#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */\r\n#define FLASH_CR_RDPERRIE_Pos                (23U)\r\n#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */\r\n#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */\r\n#define FLASH_CR_RDSERRIE_Pos                (24U)\r\n#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */\r\n#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */\r\n#define FLASH_CR_SNECCERRIE_Pos              (25U)\r\n#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */\r\n#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */\r\n#define FLASH_CR_DBECCERRIE_Pos              (26U)\r\n#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */\r\n#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */\r\n#define FLASH_CR_CRCENDIE_Pos                (27U)\r\n#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */\r\n#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */\r\n#define FLASH_CR_CRCRDERRIE_Pos              (28U)\r\n#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */\r\n#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */\r\n\r\n/*******************  Bits definition for FLASH_SR register  ***********************/\r\n#define FLASH_SR_BSY_Pos                     (0U)\r\n#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */\r\n#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */\r\n#define FLASH_SR_WBNE_Pos                    (1U)\r\n#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */\r\n#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */\r\n#define FLASH_SR_QW_Pos                      (2U)\r\n#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */\r\n#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */\r\n#define FLASH_SR_CRC_BUSY_Pos                (3U)\r\n#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */\r\n#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */\r\n#define FLASH_SR_EOP_Pos                     (16U)\r\n#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */\r\n#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */\r\n#define FLASH_SR_WRPERR_Pos                  (17U)\r\n#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */\r\n#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */\r\n#define FLASH_SR_PGSERR_Pos                  (18U)\r\n#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */\r\n#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */\r\n#define FLASH_SR_STRBERR_Pos                 (19U)\r\n#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */\r\n#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */\r\n#define FLASH_SR_INCERR_Pos                  (21U)\r\n#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */\r\n#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */\r\n#define FLASH_SR_OPERR_Pos                   (22U)\r\n#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */\r\n#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */\r\n#define FLASH_SR_RDPERR_Pos                  (23U)\r\n#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */\r\n#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */\r\n#define FLASH_SR_RDSERR_Pos                  (24U)\r\n#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */\r\n#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */\r\n#define FLASH_SR_SNECCERR_Pos                (25U)\r\n#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */\r\n#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */\r\n#define FLASH_SR_DBECCERR_Pos                (26U)\r\n#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */\r\n#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */\r\n#define FLASH_SR_CRCEND_Pos                  (27U)\r\n#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */\r\n#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */\r\n#define FLASH_SR_CRCRDERR_Pos                (28U)\r\n#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */\r\n#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */\r\n\r\n/*******************  Bits definition for FLASH_CCR register  *******************/\r\n#define FLASH_CCR_CLR_EOP_Pos                (16U)\r\n#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */\r\n#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */\r\n#define FLASH_CCR_CLR_WRPERR_Pos             (17U)\r\n#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */\r\n#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */\r\n#define FLASH_CCR_CLR_PGSERR_Pos             (18U)\r\n#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */\r\n#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */\r\n#define FLASH_CCR_CLR_STRBERR_Pos            (19U)\r\n#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */\r\n#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */\r\n#define FLASH_CCR_CLR_INCERR_Pos             (21U)\r\n#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */\r\n#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */\r\n#define FLASH_CCR_CLR_OPERR_Pos              (22U)\r\n#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */\r\n#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */\r\n#define FLASH_CCR_CLR_RDPERR_Pos             (23U)\r\n#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */\r\n#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */\r\n#define FLASH_CCR_CLR_RDSERR_Pos             (24U)\r\n#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */\r\n#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */\r\n#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)\r\n#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */\r\n#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */\r\n#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)\r\n#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */\r\n#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */\r\n#define FLASH_CCR_CLR_CRCEND_Pos             (27U)\r\n#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */\r\n#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */\r\n#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)\r\n#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */\r\n#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */\r\n\r\n/*******************  Bits definition for FLASH_OPTCR register  *******************/\r\n#define FLASH_OPTCR_OPTLOCK_Pos              (0U)\r\n#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */\r\n#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */\r\n#define FLASH_OPTCR_OPTSTART_Pos             (1U)\r\n#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */\r\n#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */\r\n#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)\r\n#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */\r\n#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */\r\n\r\n/*******************  Bits definition for FLASH_OPTSR register  ***************/\r\n#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)\r\n#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */\r\n#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */\r\n#define FLASH_OPTSR_BOR_LEV_Pos              (2U)\r\n#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */\r\n#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */\r\n#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */\r\n#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */\r\n#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)\r\n#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */\r\n#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */\r\n#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)\r\n#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */\r\n#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */\r\n#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)\r\n#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */\r\n#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */\r\n#define FLASH_OPTSR_RDP_Pos                  (8U)\r\n#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */\r\n#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */\r\n#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)\r\n#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */\r\n#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */\r\n#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)\r\n#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */\r\n#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */\r\n#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)\r\n#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */\r\n#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */\r\n#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */\r\n#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */\r\n#define FLASH_OPTSR_SECURITY_Pos             (21U)\r\n#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */\r\n#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */\r\n#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)\r\n#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */\r\n#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */\r\n#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)\r\n#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */\r\n#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */\r\n#define FLASH_OPTSR_IO_HSLV_Pos              (29U)\r\n#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */\r\n#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */\r\n#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)\r\n#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\r\n#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */\r\n\r\n/*******************  Bits definition for FLASH_OPTCCR register  *******************/\r\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)\r\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */\r\n#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */\r\n\r\n/*******************  Bits definition for FLASH_PRAR register  *********************/\r\n#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)\r\n#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */\r\n#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */\r\n#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)\r\n#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */\r\n#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */\r\n#define FLASH_PRAR_DMEP_Pos                  (31U)\r\n#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */\r\n#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */\r\n\r\n/*******************  Bits definition for FLASH_SCAR register  *********************/\r\n#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)\r\n#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */\r\n#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */\r\n#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)\r\n#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */\r\n#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */\r\n#define FLASH_SCAR_DMES_Pos                  (31U)\r\n#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */\r\n#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */\r\n\r\n/*******************  Bits definition for FLASH_WPSN register  *********************/\r\n#define FLASH_WPSN_WRPSN_Pos                 (0U)\r\n#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */\r\n#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */\r\n\r\n/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/\r\n#define FLASH_BOOT_ADD0_Pos                  (0U)\r\n#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */\r\n#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */\r\n#define FLASH_BOOT_ADD1_Pos                  (16U)\r\n#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */\r\n#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */\r\n\r\n\r\n/*******************  Bits definition for FLASH_CRCCR register  ********************/\r\n#define FLASH_CRCCR_CRC_SECT_Pos             (0U)\r\n#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */\r\n#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */\r\n#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)\r\n#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */\r\n#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */\r\n#define FLASH_CRCCR_ADD_SECT_Pos             (9U)\r\n#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */\r\n#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */\r\n#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)\r\n#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */\r\n#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */\r\n#define FLASH_CRCCR_START_CRC_Pos            (16U)\r\n#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */\r\n#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */\r\n#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)\r\n#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */\r\n#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */\r\n#define FLASH_CRCCR_CRC_BURST_Pos            (20U)\r\n#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */\r\n#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */\r\n#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */\r\n#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */\r\n#define FLASH_CRCCR_ALL_BANK_Pos             (22U)\r\n#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */\r\n#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */\r\n\r\n/*******************  Bits definition for FLASH_CRCSADD register  ****************/\r\n#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)\r\n#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */\r\n\r\n/*******************  Bits definition for FLASH_CRCEADD register  ****************/\r\n#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)\r\n#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */\r\n\r\n/*******************  Bits definition for FLASH_CRCDATA register  ***************/\r\n#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)\r\n#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */\r\n#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */\r\n\r\n/*******************  Bits definition for FLASH_ECC_FA register  *******************/\r\n#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)\r\n#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */\r\n#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */\r\n\r\n/*******************  Bits definition for FLASH_OPTSR2 register  *******************/\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_Pos      (0U)\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_Msk      (0x3UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos) /*!< 0x00000003 */\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED          FLASH_OPTSR2_TCM_AXI_SHARED_Msk            /*!< TCM RAM shared */\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_0        (0x1UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos) /*!< 0x00000001 */\r\n#define FLASH_OPTSR2_TCM_AXI_SHARED_1        (0x2UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos) /*!< 0x00000002 */\r\n#define FLASH_OPTSR2_CPUFREQ_BOOST_Pos       (2U)\r\n#define FLASH_OPTSR2_CPUFREQ_BOOST_Msk       (0x1UL << FLASH_OPTSR2_CPUFREQ_BOOST_Pos) /*!< 0x00000004 */\r\n#define FLASH_OPTSR2_CPUFREQ_BOOST           FLASH_OPTSR2_CPUFREQ_BOOST_Msk            /*!< CPU frequency boost */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Filter Mathematical ACcelerator unit (FMAC)                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*****************  Bit definition for FMAC_X1BUFCFG register  ****************/\r\n#define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)\r\n#define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */\r\n#define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */\r\n#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)\r\n#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */\r\n#define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */\r\n#define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)\r\n#define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */\r\n#define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */\r\n/*****************  Bit definition for FMAC_X2BUFCFG register  ****************/\r\n#define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)\r\n#define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */\r\n#define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */\r\n#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)\r\n#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */\r\n#define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */\r\n/*****************  Bit definition for FMAC_YBUFCFG register  *****************/\r\n#define FMAC_YBUFCFG_Y_BASE_Pos       (0U)\r\n#define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */\r\n#define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */\r\n#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)\r\n#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */\r\n#define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */\r\n#define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)\r\n#define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */\r\n#define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */\r\n/******************  Bit definition for FMAC_PARAM register  ******************/\r\n#define FMAC_PARAM_P_Pos              (0U)\r\n#define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */\r\n#define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */\r\n#define FMAC_PARAM_Q_Pos              (8U)\r\n#define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */\r\n#define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */\r\n#define FMAC_PARAM_R_Pos              (16U)\r\n#define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */\r\n#define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */\r\n#define FMAC_PARAM_FUNC_Pos           (24U)\r\n#define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */\r\n#define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */\r\n#define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */\r\n#define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */\r\n#define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */\r\n#define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */\r\n#define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */\r\n#define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */\r\n#define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */\r\n#define FMAC_PARAM_START_Pos          (31U)\r\n#define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */\r\n#define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */\r\n/********************  Bit definition for FMAC_CR register  *******************/\r\n#define FMAC_CR_RIEN_Pos              (0U)\r\n#define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */\r\n#define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */\r\n#define FMAC_CR_WIEN_Pos              (1U)\r\n#define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */\r\n#define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */\r\n#define FMAC_CR_OVFLIEN_Pos           (2U)\r\n#define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */\r\n#define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */\r\n#define FMAC_CR_UNFLIEN_Pos           (3U)\r\n#define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */\r\n#define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */\r\n#define FMAC_CR_SATIEN_Pos            (4U)\r\n#define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */\r\n#define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */\r\n#define FMAC_CR_DMAREN_Pos            (8U)\r\n#define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */\r\n#define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */\r\n#define FMAC_CR_DMAWEN_Pos            (9U)\r\n#define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */\r\n#define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */\r\n#define FMAC_CR_CLIPEN_Pos            (15U)\r\n#define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */\r\n#define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */\r\n#define FMAC_CR_RESET_Pos             (16U)\r\n#define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */\r\n#define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */\r\n/*******************  Bit definition for FMAC_SR register  ********************/\r\n#define FMAC_SR_YEMPTY_Pos            (0U)\r\n#define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */\r\n#define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */\r\n#define FMAC_SR_X1FULL_Pos            (1U)\r\n#define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */\r\n#define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */\r\n#define FMAC_SR_OVFL_Pos              (8U)\r\n#define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */\r\n#define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */\r\n#define FMAC_SR_UNFL_Pos              (9U)\r\n#define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */\r\n#define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */\r\n#define FMAC_SR_SAT_Pos               (10U)\r\n#define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */\r\n#define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */\r\n/******************  Bit definition for FMAC_WDATA register  ******************/\r\n#define FMAC_WDATA_WDATA_Pos          (0U)\r\n#define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */\r\n#define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */\r\n/******************  Bit definition for FMACX_RDATA register  *****************/\r\n#define FMAC_RDATA_RDATA_Pos          (0U)\r\n#define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */\r\n#define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Flexible Memory Controller                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for FMC_BCR1 register  *******************/\r\n#define FMC_BCR1_CCLKEN_Pos        (20U)\r\n#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\r\n#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */\r\n#define FMC_BCR1_WFDIS_Pos         (21U)\r\n#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */\r\n#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */\r\n\r\n#define FMC_BCR1_BMAP_Pos          (24U)\r\n#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */\r\n#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */\r\n#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */\r\n#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */\r\n\r\n#define FMC_BCR1_FMCEN_Pos         (31U)\r\n#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */\r\n#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */\r\n/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/\r\n#define FMC_BCRx_MBKEN_Pos         (0U)\r\n#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */\r\n#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r\n#define FMC_BCRx_MUXEN_Pos         (1U)\r\n#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */\r\n#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r\n\r\n#define FMC_BCRx_MTYP_Pos          (2U)\r\n#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */\r\n#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r\n#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */\r\n#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */\r\n\r\n#define FMC_BCRx_MWID_Pos          (4U)\r\n#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */\r\n#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */\r\n#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */\r\n\r\n#define FMC_BCRx_FACCEN_Pos        (6U)\r\n#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */\r\n#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */\r\n#define FMC_BCRx_BURSTEN_Pos       (8U)\r\n#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */\r\n#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */\r\n#define FMC_BCRx_WAITPOL_Pos       (9U)\r\n#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */\r\n#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r\n#define FMC_BCRx_WAITCFG_Pos       (11U)\r\n#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */\r\n#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */\r\n#define FMC_BCRx_WREN_Pos          (12U)\r\n#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */\r\n#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */\r\n#define FMC_BCRx_WAITEN_Pos        (13U)\r\n#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */\r\n#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */\r\n#define FMC_BCRx_EXTMOD_Pos        (14U)\r\n#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */\r\n#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */\r\n#define FMC_BCRx_ASYNCWAIT_Pos     (15U)\r\n#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */\r\n#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r\n\r\n#define FMC_BCRx_CPSIZE_Pos        (16U)\r\n#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */\r\n#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */\r\n#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */\r\n#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */\r\n#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */\r\n\r\n#define FMC_BCRx_CBURSTRW_Pos      (19U)\r\n#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */\r\n#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/\r\n#define FMC_BTRx_ADDSET_Pos        (0U)\r\n#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */\r\n#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */\r\n#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */\r\n#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */\r\n#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */\r\n\r\n#define FMC_BTRx_ADDHLD_Pos        (4U)\r\n#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */\r\n#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r\n#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */\r\n#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */\r\n#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */\r\n#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */\r\n\r\n#define FMC_BTRx_DATAST_Pos        (8U)\r\n#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */\r\n#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */\r\n#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */\r\n#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */\r\n#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */\r\n#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */\r\n#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */\r\n#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */\r\n#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */\r\n\r\n#define FMC_BTRx_BUSTURN_Pos       (16U)\r\n#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */\r\n#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */\r\n#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */\r\n#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */\r\n#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */\r\n\r\n#define FMC_BTRx_CLKDIV_Pos        (20U)\r\n#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */\r\n#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */\r\n#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */\r\n#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */\r\n#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */\r\n\r\n#define FMC_BTRx_DATLAT_Pos        (24U)\r\n#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */\r\n#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\r\n#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */\r\n#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */\r\n#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */\r\n#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */\r\n\r\n#define FMC_BTRx_ACCMOD_Pos        (28U)\r\n#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */\r\n#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */\r\n#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/\r\n#define FMC_BWTRx_ADDSET_Pos       (0U)\r\n#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */\r\n#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */\r\n#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */\r\n#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */\r\n#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */\r\n\r\n#define FMC_BWTRx_ADDHLD_Pos       (4U)\r\n#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */\r\n#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */\r\n#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */\r\n#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */\r\n#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */\r\n\r\n#define FMC_BWTRx_DATAST_Pos       (8U)\r\n#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */\r\n#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */\r\n#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */\r\n#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */\r\n#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */\r\n#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */\r\n#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */\r\n#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */\r\n#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */\r\n\r\n#define FMC_BWTRx_BUSTURN_Pos      (16U)\r\n#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */\r\n#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */\r\n#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */\r\n#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */\r\n#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */\r\n\r\n#define FMC_BWTRx_ACCMOD_Pos       (28U)\r\n#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */\r\n#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */\r\n#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_PCR register  *******************/\r\n#define FMC_PCR_PWAITEN_Pos        (1U)\r\n#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\r\n#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\r\n#define FMC_PCR_PBKEN_Pos          (2U)\r\n#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\r\n#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */\r\n\r\n#define FMC_PCR_PWID_Pos           (4U)\r\n#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\r\n#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\r\n#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */\r\n#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */\r\n\r\n#define FMC_PCR_ECCEN_Pos          (6U)\r\n#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\r\n#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\r\n\r\n#define FMC_PCR_TCLR_Pos           (9U)\r\n#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\r\n#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\r\n#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */\r\n#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */\r\n#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */\r\n#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */\r\n\r\n#define FMC_PCR_TAR_Pos            (13U)\r\n#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\r\n#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\r\n#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */\r\n#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */\r\n#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */\r\n#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */\r\n\r\n#define FMC_PCR_ECCPS_Pos          (17U)\r\n#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\r\n#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */\r\n#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */\r\n#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */\r\n#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */\r\n\r\n/*******************  Bit definition for FMC_SR register  *******************/\r\n#define FMC_SR_IRS_Pos             (0U)\r\n#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\r\n#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\r\n#define FMC_SR_ILS_Pos             (1U)\r\n#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\r\n#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\r\n#define FMC_SR_IFS_Pos             (2U)\r\n#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\r\n#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\r\n#define FMC_SR_IREN_Pos            (3U)\r\n#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\r\n#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\r\n#define FMC_SR_ILEN_Pos            (4U)\r\n#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\r\n#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\r\n#define FMC_SR_IFEN_Pos            (5U)\r\n#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\r\n#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\r\n#define FMC_SR_FEMPT_Pos           (6U)\r\n#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\r\n#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\r\n\r\n/******************  Bit definition for FMC_PMEM register  ******************/\r\n#define FMC_PMEM_MEMSET_Pos       (0U)\r\n#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */\r\n#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */\r\n#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */\r\n#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */\r\n#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */\r\n#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */\r\n#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */\r\n#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */\r\n#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */\r\n#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */\r\n\r\n#define FMC_PMEM_MEMWAIT_Pos      (8U)\r\n#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */\r\n#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */\r\n#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */\r\n#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */\r\n#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */\r\n#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */\r\n#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */\r\n#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */\r\n#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */\r\n#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */\r\n\r\n#define FMC_PMEM_MEMHOLD_Pos      (16U)\r\n#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */\r\n#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */\r\n#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */\r\n#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */\r\n#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */\r\n#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */\r\n#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */\r\n#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */\r\n#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */\r\n#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */\r\n\r\n#define FMC_PMEM_MEMHIZ_Pos       (24U)\r\n#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */\r\n#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\r\n#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */\r\n#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */\r\n#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */\r\n#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */\r\n#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */\r\n#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */\r\n#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */\r\n#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for FMC_PATT register  ******************/\r\n#define FMC_PATT_ATTSET_Pos       (0U)\r\n#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */\r\n#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */\r\n#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */\r\n#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */\r\n#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */\r\n#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */\r\n#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */\r\n#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */\r\n#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */\r\n#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */\r\n\r\n#define FMC_PATT_ATTWAIT_Pos      (8U)\r\n#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */\r\n#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\r\n#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */\r\n#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */\r\n#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */\r\n#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */\r\n#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */\r\n#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */\r\n#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */\r\n#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */\r\n\r\n#define FMC_PATT_ATTHOLD_Pos      (16U)\r\n#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */\r\n#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\r\n#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */\r\n#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */\r\n#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */\r\n#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */\r\n#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */\r\n#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */\r\n#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */\r\n#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */\r\n\r\n#define FMC_PATT_ATTHIZ_Pos       (24U)\r\n#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */\r\n#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\r\n#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */\r\n#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */\r\n#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */\r\n#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */\r\n#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */\r\n#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */\r\n#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */\r\n#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for FMC_ECCR3 register  ******************/\r\n#define FMC_ECCR3_ECC3_Pos         (0U)\r\n#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */\r\n#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */\r\n\r\n/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/\r\n#define FMC_SDCRx_NC_Pos           (0U)\r\n#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */\r\n#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */\r\n#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */\r\n#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */\r\n\r\n#define FMC_SDCRx_NR_Pos           (2U)\r\n#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */\r\n#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */\r\n#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */\r\n\r\n#define FMC_SDCRx_MWID_Pos         (4U)\r\n#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */\r\n#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */\r\n\r\n#define FMC_SDCRx_NB_Pos           (6U)\r\n#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */\r\n#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */\r\n\r\n#define FMC_SDCRx_CAS_Pos          (7U)\r\n#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */\r\n#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */\r\n#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */\r\n#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */\r\n\r\n#define FMC_SDCRx_WP_Pos           (9U)\r\n#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */\r\n#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */\r\n\r\n#define FMC_SDCRx_SDCLK_Pos        (10U)\r\n#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */\r\n#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */\r\n#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */\r\n#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */\r\n\r\n#define FMC_SDCRx_RBURST_Pos       (12U)\r\n#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */\r\n#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */\r\n\r\n#define FMC_SDCRx_RPIPE_Pos        (13U)\r\n#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */\r\n#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */\r\n#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */\r\n#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */\r\n\r\n/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/\r\n#define FMC_SDTRx_TMRD_Pos         (0U)\r\n#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */\r\n#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */\r\n#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */\r\n#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */\r\n\r\n#define FMC_SDTRx_TXSR_Pos         (4U)\r\n#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */\r\n#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */\r\n#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */\r\n\r\n#define FMC_SDTRx_TRAS_Pos         (8U)\r\n#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */\r\n#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */\r\n#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */\r\n#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */\r\n#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */\r\n#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */\r\n\r\n#define FMC_SDTRx_TRC_Pos          (12U)\r\n#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */\r\n#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */\r\n#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */\r\n#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */\r\n#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */\r\n\r\n#define FMC_SDTRx_TWR_Pos          (16U)\r\n#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */\r\n#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */\r\n#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */\r\n#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */\r\n#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */\r\n\r\n#define FMC_SDTRx_TRP_Pos          (20U)\r\n#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */\r\n#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */\r\n#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */\r\n#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */\r\n#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */\r\n\r\n#define FMC_SDTRx_TRCD_Pos         (24U)\r\n#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */\r\n#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */\r\n#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */\r\n#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */\r\n#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */\r\n\r\n/******************  Bit definition for FMC_SDCMR register  ******************/\r\n#define FMC_SDCMR_MODE_Pos         (0U)\r\n#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */\r\n#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */\r\n#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */\r\n\r\n#define FMC_SDCMR_CTB2_Pos         (3U)\r\n#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */\r\n#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */\r\n\r\n#define FMC_SDCMR_CTB1_Pos         (4U)\r\n#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */\r\n#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */\r\n\r\n#define FMC_SDCMR_NRFS_Pos         (5U)\r\n#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */\r\n#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */\r\n#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */\r\n#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */\r\n\r\n#define FMC_SDCMR_MRD_Pos          (9U)\r\n#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */\r\n#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */\r\n\r\n/******************  Bit definition for FMC_SDRTR register  ******************/\r\n#define FMC_SDRTR_CRE_Pos          (0U)\r\n#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */\r\n\r\n#define FMC_SDRTR_COUNT_Pos        (1U)\r\n#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */\r\n#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */\r\n\r\n#define FMC_SDRTR_REIE_Pos         (14U)\r\n#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */\r\n#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */\r\n\r\n/******************  Bit definition for FMC_SDSR register  ******************/\r\n#define FMC_SDSR_RE_Pos            (0U)\r\n#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */\r\n#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */\r\n\r\n#define FMC_SDSR_MODES1_Pos        (1U)\r\n#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */\r\n#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */\r\n#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */\r\n#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */\r\n\r\n#define FMC_SDSR_MODES2_Pos        (3U)\r\n#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */\r\n#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */\r\n#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */\r\n#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            General Purpose I/O                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bits definition for GPIO_MODER register  *****************/\r\n#define GPIO_MODER_MODE0_Pos           (0U)\r\n#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */\r\n#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\r\n#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */\r\n\r\n#define GPIO_MODER_MODE1_Pos           (2U)\r\n#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */\r\n#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\r\n#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */\r\n#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */\r\n\r\n#define GPIO_MODER_MODE2_Pos           (4U)\r\n#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */\r\n#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\r\n#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */\r\n#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */\r\n\r\n#define GPIO_MODER_MODE3_Pos           (6U)\r\n#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */\r\n#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\r\n#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */\r\n#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */\r\n\r\n#define GPIO_MODER_MODE4_Pos           (8U)\r\n#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */\r\n#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\r\n#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */\r\n#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */\r\n\r\n#define GPIO_MODER_MODE5_Pos           (10U)\r\n#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */\r\n#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\r\n#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */\r\n#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */\r\n\r\n#define GPIO_MODER_MODE6_Pos           (12U)\r\n#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */\r\n#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\r\n#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */\r\n#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */\r\n\r\n#define GPIO_MODER_MODE7_Pos           (14U)\r\n#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */\r\n#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\r\n#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */\r\n#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */\r\n\r\n#define GPIO_MODER_MODE8_Pos           (16U)\r\n#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */\r\n#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\r\n#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */\r\n#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */\r\n\r\n#define GPIO_MODER_MODE9_Pos           (18U)\r\n#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */\r\n#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\r\n#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */\r\n#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */\r\n\r\n#define GPIO_MODER_MODE10_Pos          (20U)\r\n#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */\r\n#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\r\n#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */\r\n#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */\r\n\r\n#define GPIO_MODER_MODE11_Pos          (22U)\r\n#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */\r\n#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\r\n#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */\r\n#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */\r\n\r\n#define GPIO_MODER_MODE12_Pos          (24U)\r\n#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */\r\n#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\r\n#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */\r\n#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */\r\n\r\n#define GPIO_MODER_MODE13_Pos          (26U)\r\n#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */\r\n#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\r\n#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */\r\n#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */\r\n\r\n#define GPIO_MODER_MODE14_Pos          (28U)\r\n#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */\r\n#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\r\n#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */\r\n#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */\r\n\r\n#define GPIO_MODER_MODE15_Pos          (30U)\r\n#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */\r\n#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\r\n#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */\r\n#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_OTYPER register  ****************/\r\n#define GPIO_OTYPER_OT0_Pos            (0U)\r\n#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\r\n#define GPIO_OTYPER_OT1_Pos            (1U)\r\n#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */\r\n#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\r\n#define GPIO_OTYPER_OT2_Pos            (2U)\r\n#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */\r\n#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\r\n#define GPIO_OTYPER_OT3_Pos            (3U)\r\n#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */\r\n#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\r\n#define GPIO_OTYPER_OT4_Pos            (4U)\r\n#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */\r\n#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\r\n#define GPIO_OTYPER_OT5_Pos            (5U)\r\n#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */\r\n#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\r\n#define GPIO_OTYPER_OT6_Pos            (6U)\r\n#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */\r\n#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\r\n#define GPIO_OTYPER_OT7_Pos            (7U)\r\n#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */\r\n#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\r\n#define GPIO_OTYPER_OT8_Pos            (8U)\r\n#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */\r\n#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\r\n#define GPIO_OTYPER_OT9_Pos            (9U)\r\n#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */\r\n#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\r\n#define GPIO_OTYPER_OT10_Pos           (10U)\r\n#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */\r\n#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\r\n#define GPIO_OTYPER_OT11_Pos           (11U)\r\n#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */\r\n#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\r\n#define GPIO_OTYPER_OT12_Pos           (12U)\r\n#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */\r\n#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\r\n#define GPIO_OTYPER_OT13_Pos           (13U)\r\n#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */\r\n#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\r\n#define GPIO_OTYPER_OT14_Pos           (14U)\r\n#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */\r\n#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\r\n#define GPIO_OTYPER_OT15_Pos           (15U)\r\n#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */\r\n#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\r\n\r\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r\n#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\r\n#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */\r\n#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\r\n#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */\r\n#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\r\n#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */\r\n#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\r\n#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */\r\n#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\r\n#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */\r\n#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\r\n#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */\r\n#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\r\n#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */\r\n#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\r\n#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */\r\n#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\r\n#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */\r\n#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\r\n#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */\r\n#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\r\n#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */\r\n#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\r\n#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */\r\n#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\r\n#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */\r\n#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\r\n#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */\r\n#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\r\n#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */\r\n#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\r\n#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */\r\n#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\r\n#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */\r\n#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\r\n#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */\r\n#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\r\n#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */\r\n#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\r\n#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */\r\n#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\r\n#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */\r\n#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\r\n#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */\r\n#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\r\n#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */\r\n#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\r\n#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */\r\n#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\r\n#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */\r\n#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\r\n#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */\r\n#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\r\n#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */\r\n#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\r\n#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */\r\n#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\r\n#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */\r\n#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\r\n#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */\r\n#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */\r\n\r\n#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\r\n#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */\r\n#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\r\n#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */\r\n#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_PUPDR register  *****************/\r\n#define GPIO_PUPDR_PUPD0_Pos           (0U)\r\n#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */\r\n#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\r\n#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */\r\n\r\n#define GPIO_PUPDR_PUPD1_Pos           (2U)\r\n#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */\r\n#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\r\n#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */\r\n#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */\r\n\r\n#define GPIO_PUPDR_PUPD2_Pos           (4U)\r\n#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */\r\n#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\r\n#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */\r\n#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */\r\n\r\n#define GPIO_PUPDR_PUPD3_Pos           (6U)\r\n#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */\r\n#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\r\n#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */\r\n#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */\r\n\r\n#define GPIO_PUPDR_PUPD4_Pos           (8U)\r\n#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */\r\n#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\r\n#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */\r\n#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */\r\n\r\n#define GPIO_PUPDR_PUPD5_Pos           (10U)\r\n#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */\r\n#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\r\n#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */\r\n#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */\r\n\r\n#define GPIO_PUPDR_PUPD6_Pos           (12U)\r\n#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */\r\n#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\r\n#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */\r\n#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */\r\n\r\n#define GPIO_PUPDR_PUPD7_Pos           (14U)\r\n#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */\r\n#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\r\n#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */\r\n#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */\r\n\r\n#define GPIO_PUPDR_PUPD8_Pos           (16U)\r\n#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */\r\n#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\r\n#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */\r\n#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */\r\n\r\n#define GPIO_PUPDR_PUPD9_Pos           (18U)\r\n#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */\r\n#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\r\n#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */\r\n#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */\r\n\r\n#define GPIO_PUPDR_PUPD10_Pos          (20U)\r\n#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */\r\n#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\r\n#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */\r\n#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */\r\n\r\n#define GPIO_PUPDR_PUPD11_Pos          (22U)\r\n#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */\r\n#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\r\n#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */\r\n#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */\r\n\r\n#define GPIO_PUPDR_PUPD12_Pos          (24U)\r\n#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */\r\n#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\r\n#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */\r\n#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */\r\n\r\n#define GPIO_PUPDR_PUPD13_Pos          (26U)\r\n#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */\r\n#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\r\n#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */\r\n#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */\r\n\r\n#define GPIO_PUPDR_PUPD14_Pos          (28U)\r\n#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */\r\n#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\r\n#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */\r\n#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */\r\n\r\n#define GPIO_PUPDR_PUPD15_Pos          (30U)\r\n#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */\r\n#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\r\n#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */\r\n#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_IDR register  *******************/\r\n#define GPIO_IDR_ID0_Pos               (0U)\r\n#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */\r\n#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\r\n#define GPIO_IDR_ID1_Pos               (1U)\r\n#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */\r\n#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\r\n#define GPIO_IDR_ID2_Pos               (2U)\r\n#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */\r\n#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\r\n#define GPIO_IDR_ID3_Pos               (3U)\r\n#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */\r\n#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\r\n#define GPIO_IDR_ID4_Pos               (4U)\r\n#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */\r\n#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\r\n#define GPIO_IDR_ID5_Pos               (5U)\r\n#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */\r\n#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\r\n#define GPIO_IDR_ID6_Pos               (6U)\r\n#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */\r\n#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\r\n#define GPIO_IDR_ID7_Pos               (7U)\r\n#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */\r\n#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\r\n#define GPIO_IDR_ID8_Pos               (8U)\r\n#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */\r\n#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\r\n#define GPIO_IDR_ID9_Pos               (9U)\r\n#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */\r\n#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\r\n#define GPIO_IDR_ID10_Pos              (10U)\r\n#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */\r\n#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\r\n#define GPIO_IDR_ID11_Pos              (11U)\r\n#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */\r\n#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\r\n#define GPIO_IDR_ID12_Pos              (12U)\r\n#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */\r\n#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\r\n#define GPIO_IDR_ID13_Pos              (13U)\r\n#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */\r\n#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\r\n#define GPIO_IDR_ID14_Pos              (14U)\r\n#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */\r\n#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\r\n#define GPIO_IDR_ID15_Pos              (15U)\r\n#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */\r\n#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\r\n\r\n/******************  Bits definition for GPIO_ODR register  *******************/\r\n#define GPIO_ODR_OD0_Pos               (0U)\r\n#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */\r\n#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\r\n#define GPIO_ODR_OD1_Pos               (1U)\r\n#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */\r\n#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\r\n#define GPIO_ODR_OD2_Pos               (2U)\r\n#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */\r\n#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\r\n#define GPIO_ODR_OD3_Pos               (3U)\r\n#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */\r\n#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\r\n#define GPIO_ODR_OD4_Pos               (4U)\r\n#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */\r\n#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\r\n#define GPIO_ODR_OD5_Pos               (5U)\r\n#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */\r\n#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\r\n#define GPIO_ODR_OD6_Pos               (6U)\r\n#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */\r\n#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\r\n#define GPIO_ODR_OD7_Pos               (7U)\r\n#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */\r\n#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\r\n#define GPIO_ODR_OD8_Pos               (8U)\r\n#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */\r\n#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\r\n#define GPIO_ODR_OD9_Pos               (9U)\r\n#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */\r\n#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\r\n#define GPIO_ODR_OD10_Pos              (10U)\r\n#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */\r\n#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\r\n#define GPIO_ODR_OD11_Pos              (11U)\r\n#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */\r\n#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\r\n#define GPIO_ODR_OD12_Pos              (12U)\r\n#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */\r\n#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\r\n#define GPIO_ODR_OD13_Pos              (13U)\r\n#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */\r\n#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\r\n#define GPIO_ODR_OD14_Pos              (14U)\r\n#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */\r\n#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\r\n#define GPIO_ODR_OD15_Pos              (15U)\r\n#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */\r\n#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\r\n\r\n/******************  Bits definition for GPIO_BSRR register  ******************/\r\n#define GPIO_BSRR_BS0_Pos              (0U)\r\n#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */\r\n#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\r\n#define GPIO_BSRR_BS1_Pos              (1U)\r\n#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */\r\n#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\r\n#define GPIO_BSRR_BS2_Pos              (2U)\r\n#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */\r\n#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\r\n#define GPIO_BSRR_BS3_Pos              (3U)\r\n#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */\r\n#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\r\n#define GPIO_BSRR_BS4_Pos              (4U)\r\n#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */\r\n#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\r\n#define GPIO_BSRR_BS5_Pos              (5U)\r\n#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */\r\n#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\r\n#define GPIO_BSRR_BS6_Pos              (6U)\r\n#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */\r\n#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\r\n#define GPIO_BSRR_BS7_Pos              (7U)\r\n#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */\r\n#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\r\n#define GPIO_BSRR_BS8_Pos              (8U)\r\n#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */\r\n#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\r\n#define GPIO_BSRR_BS9_Pos              (9U)\r\n#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */\r\n#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\r\n#define GPIO_BSRR_BS10_Pos             (10U)\r\n#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */\r\n#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\r\n#define GPIO_BSRR_BS11_Pos             (11U)\r\n#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */\r\n#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\r\n#define GPIO_BSRR_BS12_Pos             (12U)\r\n#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */\r\n#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\r\n#define GPIO_BSRR_BS13_Pos             (13U)\r\n#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */\r\n#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\r\n#define GPIO_BSRR_BS14_Pos             (14U)\r\n#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */\r\n#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\r\n#define GPIO_BSRR_BS15_Pos             (15U)\r\n#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */\r\n#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\r\n#define GPIO_BSRR_BR0_Pos              (16U)\r\n#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */\r\n#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\r\n#define GPIO_BSRR_BR1_Pos              (17U)\r\n#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */\r\n#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\r\n#define GPIO_BSRR_BR2_Pos              (18U)\r\n#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */\r\n#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\r\n#define GPIO_BSRR_BR3_Pos              (19U)\r\n#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */\r\n#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\r\n#define GPIO_BSRR_BR4_Pos              (20U)\r\n#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */\r\n#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\r\n#define GPIO_BSRR_BR5_Pos              (21U)\r\n#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */\r\n#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\r\n#define GPIO_BSRR_BR6_Pos              (22U)\r\n#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */\r\n#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\r\n#define GPIO_BSRR_BR7_Pos              (23U)\r\n#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */\r\n#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\r\n#define GPIO_BSRR_BR8_Pos              (24U)\r\n#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */\r\n#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\r\n#define GPIO_BSRR_BR9_Pos              (25U)\r\n#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */\r\n#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\r\n#define GPIO_BSRR_BR10_Pos             (26U)\r\n#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */\r\n#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\r\n#define GPIO_BSRR_BR11_Pos             (27U)\r\n#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */\r\n#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\r\n#define GPIO_BSRR_BR12_Pos             (28U)\r\n#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */\r\n#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\r\n#define GPIO_BSRR_BR13_Pos             (29U)\r\n#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */\r\n#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\r\n#define GPIO_BSRR_BR14_Pos             (30U)\r\n#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */\r\n#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\r\n#define GPIO_BSRR_BR15_Pos             (31U)\r\n#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */\r\n#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\r\n\r\n/****************** Bit definition for GPIO_LCKR register *********************/\r\n#define GPIO_LCKR_LCK0_Pos             (0U)\r\n#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */\r\n#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\r\n#define GPIO_LCKR_LCK1_Pos             (1U)\r\n#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */\r\n#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\r\n#define GPIO_LCKR_LCK2_Pos             (2U)\r\n#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */\r\n#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\r\n#define GPIO_LCKR_LCK3_Pos             (3U)\r\n#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */\r\n#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\r\n#define GPIO_LCKR_LCK4_Pos             (4U)\r\n#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */\r\n#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\r\n#define GPIO_LCKR_LCK5_Pos             (5U)\r\n#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */\r\n#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\r\n#define GPIO_LCKR_LCK6_Pos             (6U)\r\n#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */\r\n#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\r\n#define GPIO_LCKR_LCK7_Pos             (7U)\r\n#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */\r\n#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\r\n#define GPIO_LCKR_LCK8_Pos             (8U)\r\n#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */\r\n#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\r\n#define GPIO_LCKR_LCK9_Pos             (9U)\r\n#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */\r\n#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\r\n#define GPIO_LCKR_LCK10_Pos            (10U)\r\n#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */\r\n#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\r\n#define GPIO_LCKR_LCK11_Pos            (11U)\r\n#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */\r\n#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\r\n#define GPIO_LCKR_LCK12_Pos            (12U)\r\n#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */\r\n#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\r\n#define GPIO_LCKR_LCK13_Pos            (13U)\r\n#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */\r\n#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\r\n#define GPIO_LCKR_LCK14_Pos            (14U)\r\n#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */\r\n#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\r\n#define GPIO_LCKR_LCK15_Pos            (15U)\r\n#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */\r\n#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\r\n#define GPIO_LCKR_LCKK_Pos             (16U)\r\n#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */\r\n#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\r\n\r\n/****************** Bit definition for GPIO_AFRL register  ********************/\r\n#define GPIO_AFRL_AFSEL0_Pos           (0U)\r\n#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */\r\n#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\r\n#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */\r\n#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */\r\n#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */\r\n#define GPIO_AFRL_AFSEL1_Pos           (4U)\r\n#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */\r\n#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\r\n#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */\r\n#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */\r\n#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */\r\n#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */\r\n#define GPIO_AFRL_AFSEL2_Pos           (8U)\r\n#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */\r\n#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\r\n#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */\r\n#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */\r\n#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */\r\n#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */\r\n#define GPIO_AFRL_AFSEL3_Pos           (12U)\r\n#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */\r\n#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\r\n#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */\r\n#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */\r\n#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */\r\n#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */\r\n#define GPIO_AFRL_AFSEL4_Pos           (16U)\r\n#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */\r\n#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\r\n#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */\r\n#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */\r\n#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */\r\n#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */\r\n#define GPIO_AFRL_AFSEL5_Pos           (20U)\r\n#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */\r\n#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\r\n#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */\r\n#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */\r\n#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */\r\n#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */\r\n#define GPIO_AFRL_AFSEL6_Pos           (24U)\r\n#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */\r\n#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\r\n#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */\r\n#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */\r\n#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */\r\n#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */\r\n#define GPIO_AFRL_AFSEL7_Pos           (28U)\r\n#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */\r\n#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\r\n#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */\r\n#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */\r\n#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */\r\n#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */\r\n\r\n/* Legacy defines */\r\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\r\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\r\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\r\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\r\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\r\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\r\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\r\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\r\n\r\n/****************** Bit definition for GPIO_AFRH register  ********************/\r\n#define GPIO_AFRH_AFSEL8_Pos           (0U)\r\n#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */\r\n#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\r\n#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */\r\n#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */\r\n#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */\r\n#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */\r\n#define GPIO_AFRH_AFSEL9_Pos           (4U)\r\n#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */\r\n#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\r\n#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */\r\n#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */\r\n#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */\r\n#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */\r\n#define GPIO_AFRH_AFSEL10_Pos          (8U)\r\n#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */\r\n#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\r\n#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */\r\n#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */\r\n#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */\r\n#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */\r\n#define GPIO_AFRH_AFSEL11_Pos          (12U)\r\n#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */\r\n#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\r\n#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */\r\n#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */\r\n#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */\r\n#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */\r\n#define GPIO_AFRH_AFSEL12_Pos          (16U)\r\n#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */\r\n#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\r\n#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */\r\n#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */\r\n#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */\r\n#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */\r\n#define GPIO_AFRH_AFSEL13_Pos          (20U)\r\n#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */\r\n#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\r\n#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */\r\n#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */\r\n#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */\r\n#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */\r\n#define GPIO_AFRH_AFSEL14_Pos          (24U)\r\n#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */\r\n#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\r\n#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */\r\n#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */\r\n#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */\r\n#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */\r\n#define GPIO_AFRH_AFSEL15_Pos          (28U)\r\n#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */\r\n#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\r\n#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */\r\n#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */\r\n#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */\r\n#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */\r\n\r\n/* Legacy defines */\r\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\r\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\r\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\r\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\r\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\r\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\r\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\r\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        HSEM HW Semaphore                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for HSEM_R register  ********************/\r\n#define HSEM_R_PROCID_Pos         (0U)\r\n#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */\r\n#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */\r\n#define HSEM_R_COREID_Pos         (8U)\r\n#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */\r\n#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */\r\n#define HSEM_R_LOCK_Pos           (31U)\r\n#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */\r\n#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */\r\n\r\n/********************  Bit definition for HSEM_RLR register  ******************/\r\n#define HSEM_RLR_PROCID_Pos       (0U)\r\n#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */\r\n#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */\r\n#define HSEM_RLR_COREID_Pos       (8U)\r\n#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */\r\n#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */\r\n#define HSEM_RLR_LOCK_Pos         (31U)\r\n#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */\r\n#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */\r\n\r\n/********************  Bit definition for HSEM_C1IER register  *****************/\r\n#define HSEM_C1IER_ISE0_Pos       (0U)\r\n#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */\r\n#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE1_Pos       (1U)\r\n#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */\r\n#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE2_Pos       (2U)\r\n#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */\r\n#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE3_Pos       (3U)\r\n#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */\r\n#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE4_Pos       (4U)\r\n#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */\r\n#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */\r\n#define HSEM_C1IER_ISE5_Pos       (5U)\r\n#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */\r\n#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE6_Pos       (6U)\r\n#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */\r\n#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE7_Pos       (7U)\r\n#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */\r\n#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE8_Pos       (8U)\r\n#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */\r\n#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE9_Pos       (9U)\r\n#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */\r\n#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */\r\n#define HSEM_C1IER_ISE10_Pos      (10U)\r\n#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */\r\n#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE11_Pos      (11U)\r\n#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */\r\n#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE12_Pos      (12U)\r\n#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */\r\n#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE13_Pos      (13U)\r\n#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */\r\n#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE14_Pos      (14U)\r\n#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */\r\n#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */\r\n#define HSEM_C1IER_ISE15_Pos      (15U)\r\n#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */\r\n#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE16_Pos      (16U)\r\n#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */\r\n#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE17_Pos      (17U)\r\n#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */\r\n#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE18_Pos      (18U)\r\n#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */\r\n#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE19_Pos      (19U)\r\n#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */\r\n#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE20_Pos      (20U)\r\n#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */\r\n#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE21_Pos      (21U)\r\n#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */\r\n#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE22_Pos      (22U)\r\n#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */\r\n#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE23_Pos      (23U)\r\n#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */\r\n#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE24_Pos      (24U)\r\n#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */\r\n#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE25_Pos      (25U)\r\n#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */\r\n#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE26_Pos      (26U)\r\n#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */\r\n#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE27_Pos      (27U)\r\n#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */\r\n#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE28_Pos      (28U)\r\n#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */\r\n#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE29_Pos      (29U)\r\n#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */\r\n#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE30_Pos      (30U)\r\n#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */\r\n#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */\r\n#define HSEM_C1IER_ISE31_Pos      (31U)\r\n#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */\r\n#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */\r\n\r\n/********************  Bit definition for HSEM_C1ICR register  *****************/\r\n#define HSEM_C1ICR_ISC0_Pos       (0U)\r\n#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */\r\n#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC1_Pos       (1U)\r\n#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */\r\n#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC2_Pos       (2U)\r\n#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */\r\n#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC3_Pos       (3U)\r\n#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */\r\n#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC4_Pos       (4U)\r\n#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */\r\n#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC5_Pos       (5U)\r\n#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */\r\n#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC6_Pos       (6U)\r\n#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */\r\n#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC7_Pos       (7U)\r\n#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */\r\n#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC8_Pos       (8U)\r\n#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */\r\n#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC9_Pos       (9U)\r\n#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */\r\n#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */\r\n#define HSEM_C1ICR_ISC10_Pos      (10U)\r\n#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */\r\n#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC11_Pos      (11U)\r\n#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */\r\n#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC12_Pos      (12U)\r\n#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */\r\n#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC13_Pos      (13U)\r\n#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */\r\n#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC14_Pos      (14U)\r\n#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */\r\n#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC15_Pos      (15U)\r\n#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */\r\n#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC16_Pos      (16U)\r\n#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */\r\n#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC17_Pos      (17U)\r\n#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */\r\n#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC18_Pos      (18U)\r\n#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */\r\n#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC19_Pos      (19U)\r\n#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */\r\n#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC20_Pos      (20U)\r\n#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */\r\n#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC21_Pos      (21U)\r\n#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */\r\n#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC22_Pos      (22U)\r\n#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */\r\n#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC23_Pos      (23U)\r\n#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */\r\n#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC24_Pos      (24U)\r\n#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */\r\n#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC25_Pos      (25U)\r\n#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */\r\n#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC26_Pos      (26U)\r\n#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */\r\n#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC27_Pos      (27U)\r\n#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */\r\n#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC28_Pos      (28U)\r\n#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */\r\n#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC29_Pos      (29U)\r\n#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */\r\n#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC30_Pos      (30U)\r\n#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */\r\n#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */\r\n#define HSEM_C1ICR_ISC31_Pos      (31U)\r\n#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */\r\n#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */\r\n\r\n/********************  Bit definition for HSEM_C1ISR register  *****************/\r\n#define HSEM_C1ISR_ISF0_Pos       (0U)\r\n#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */\r\n#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF1_Pos       (1U)\r\n#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */\r\n#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF2_Pos       (2U)\r\n#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */\r\n#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF3_Pos       (3U)\r\n#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */\r\n#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF4_Pos       (4U)\r\n#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */\r\n#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF5_Pos       (5U)\r\n#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */\r\n#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF6_Pos       (6U)\r\n#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */\r\n#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF7_Pos       (7U)\r\n#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */\r\n#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF8_Pos       (8U)\r\n#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */\r\n#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF9_Pos       (9U)\r\n#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */\r\n#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */\r\n#define HSEM_C1ISR_ISF10_Pos      (10U)\r\n#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */\r\n#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF11_Pos      (11U)\r\n#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */\r\n#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF12_Pos      (12U)\r\n#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */\r\n#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF13_Pos      (13U)\r\n#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */\r\n#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF14_Pos      (14U)\r\n#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */\r\n#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF15_Pos      (15U)\r\n#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */\r\n#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF16_Pos      (16U)\r\n#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */\r\n#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF17_Pos      (17U)\r\n#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */\r\n#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF18_Pos      (18U)\r\n#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */\r\n#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF19_Pos      (19U)\r\n#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */\r\n#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF20_Pos      (20U)\r\n#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */\r\n#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF21_Pos      (21U)\r\n#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */\r\n#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF22_Pos      (22U)\r\n#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */\r\n#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF23_Pos      (23U)\r\n#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */\r\n#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF24_Pos      (24U)\r\n#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */\r\n#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF25_Pos      (25U)\r\n#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */\r\n#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF26_Pos      (26U)\r\n#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */\r\n#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF27_Pos      (27U)\r\n#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */\r\n#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF28_Pos      (28U)\r\n#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */\r\n#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF29_Pos      (29U)\r\n#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */\r\n#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF30_Pos      (30U)\r\n#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */\r\n#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */\r\n#define HSEM_C1ISR_ISF31_Pos      (31U)\r\n#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */\r\n#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */\r\n\r\n/********************  Bit definition for HSEM_C1MISR register  *****************/\r\n#define HSEM_C1MISR_MISF0_Pos     (0U)\r\n#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */\r\n#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF1_Pos     (1U)\r\n#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */\r\n#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF2_Pos     (2U)\r\n#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */\r\n#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF3_Pos     (3U)\r\n#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */\r\n#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF4_Pos     (4U)\r\n#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */\r\n#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF5_Pos     (5U)\r\n#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */\r\n#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF6_Pos     (6U)\r\n#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */\r\n#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF7_Pos     (7U)\r\n#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */\r\n#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF8_Pos     (8U)\r\n#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */\r\n#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF9_Pos     (9U)\r\n#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */\r\n#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */\r\n#define HSEM_C1MISR_MISF10_Pos    (10U)\r\n#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */\r\n#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF11_Pos    (11U)\r\n#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */\r\n#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF12_Pos    (12U)\r\n#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */\r\n#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF13_Pos    (13U)\r\n#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */\r\n#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF14_Pos    (14U)\r\n#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */\r\n#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF15_Pos    (15U)\r\n#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */\r\n#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF16_Pos    (16U)\r\n#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */\r\n#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF17_Pos    (17U)\r\n#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */\r\n#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF18_Pos    (18U)\r\n#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */\r\n#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF19_Pos    (19U)\r\n#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */\r\n#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF20_Pos    (20U)\r\n#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */\r\n#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF21_Pos    (21U)\r\n#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */\r\n#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF22_Pos    (22U)\r\n#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */\r\n#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF23_Pos    (23U)\r\n#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */\r\n#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF24_Pos    (24U)\r\n#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */\r\n#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF25_Pos    (25U)\r\n#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */\r\n#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF26_Pos    (26U)\r\n#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */\r\n#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF27_Pos    (27U)\r\n#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */\r\n#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF28_Pos    (28U)\r\n#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */\r\n#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF29_Pos    (29U)\r\n#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */\r\n#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF30_Pos    (30U)\r\n#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */\r\n#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */\r\n#define HSEM_C1MISR_MISF31_Pos    (31U)\r\n#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */\r\n#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */\r\n\r\n/********************  Bit definition for HSEM_CR register  *****************/\r\n#define HSEM_CR_COREID_Pos        (8U)\r\n#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */\r\n#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */\r\n#define HSEM_CR_KEY_Pos           (16U)\r\n#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */\r\n#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */\r\n\r\n/********************  Bit definition for HSEM_KEYR register  *****************/\r\n#define HSEM_KEYR_KEY_Pos         (16U)\r\n#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */\r\n#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    HASH                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bits definition for HASH_CR register  ********************/\r\n#define HASH_CR_INIT_Pos          (2U)\r\n#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */\r\n#define HASH_CR_INIT              HASH_CR_INIT_Msk\r\n#define HASH_CR_DMAE_Pos          (3U)\r\n#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */\r\n#define HASH_CR_DMAE              HASH_CR_DMAE_Msk\r\n#define HASH_CR_DATATYPE_Pos      (4U)\r\n#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */\r\n#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk\r\n#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */\r\n#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */\r\n#define HASH_CR_MODE_Pos          (6U)\r\n#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */\r\n#define HASH_CR_MODE              HASH_CR_MODE_Msk\r\n#define HASH_CR_ALGO_Pos          (7U)\r\n#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */\r\n#define HASH_CR_ALGO              HASH_CR_ALGO_Msk\r\n#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */\r\n#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */\r\n#define HASH_CR_NBW_Pos           (8U)\r\n#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */\r\n#define HASH_CR_NBW               HASH_CR_NBW_Msk\r\n#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */\r\n#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */\r\n#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */\r\n#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */\r\n#define HASH_CR_DINNE_Pos         (12U)\r\n#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */\r\n#define HASH_CR_DINNE             HASH_CR_DINNE_Msk\r\n#define HASH_CR_MDMAT_Pos         (13U)\r\n#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */\r\n#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk\r\n#define HASH_CR_LKEY_Pos          (16U)\r\n#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */\r\n#define HASH_CR_LKEY              HASH_CR_LKEY_Msk\r\n\r\n/******************  Bits definition for HASH_STR register  *******************/\r\n#define HASH_STR_NBLW_Pos         (0U)\r\n#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */\r\n#define HASH_STR_NBLW             HASH_STR_NBLW_Msk\r\n#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */\r\n#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */\r\n#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */\r\n#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */\r\n#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */\r\n#define HASH_STR_DCAL_Pos         (8U)\r\n#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */\r\n#define HASH_STR_DCAL             HASH_STR_DCAL_Msk\r\n\r\n/******************  Bits definition for HASH_IMR register  *******************/\r\n#define HASH_IMR_DINIE_Pos        (0U)\r\n#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */\r\n#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk\r\n#define HASH_IMR_DCIE_Pos         (1U)\r\n#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */\r\n#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk\r\n\r\n/******************  Bits definition for HASH_SR register  ********************/\r\n#define HASH_SR_DINIS_Pos         (0U)\r\n#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */\r\n#define HASH_SR_DINIS             HASH_SR_DINIS_Msk\r\n#define HASH_SR_DCIS_Pos          (1U)\r\n#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */\r\n#define HASH_SR_DCIS              HASH_SR_DCIS_Msk\r\n#define HASH_SR_DMAS_Pos          (2U)\r\n#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */\r\n#define HASH_SR_DMAS              HASH_SR_DMAS_Msk\r\n#define HASH_SR_BUSY_Pos          (3U)\r\n#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */\r\n#define HASH_SR_BUSY              HASH_SR_BUSY_Msk\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Inter-integrated Circuit Interface (I2C)              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for I2C_CR1 register  *******************/\r\n#define I2C_CR1_PE_Pos               (0U)\r\n#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */\r\n#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */\r\n#define I2C_CR1_TXIE_Pos             (1U)\r\n#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */\r\n#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */\r\n#define I2C_CR1_RXIE_Pos             (2U)\r\n#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */\r\n#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */\r\n#define I2C_CR1_ADDRIE_Pos           (3U)\r\n#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */\r\n#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */\r\n#define I2C_CR1_NACKIE_Pos           (4U)\r\n#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */\r\n#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */\r\n#define I2C_CR1_STOPIE_Pos           (5U)\r\n#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */\r\n#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */\r\n#define I2C_CR1_TCIE_Pos             (6U)\r\n#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */\r\n#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */\r\n#define I2C_CR1_ERRIE_Pos            (7U)\r\n#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */\r\n#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */\r\n#define I2C_CR1_DNF_Pos              (8U)\r\n#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */\r\n#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */\r\n#define I2C_CR1_ANFOFF_Pos           (12U)\r\n#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */\r\n#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */\r\n#define I2C_CR1_TXDMAEN_Pos          (14U)\r\n#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */\r\n#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */\r\n#define I2C_CR1_RXDMAEN_Pos          (15U)\r\n#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */\r\n#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */\r\n#define I2C_CR1_SBC_Pos              (16U)\r\n#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */\r\n#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */\r\n#define I2C_CR1_NOSTRETCH_Pos        (17U)\r\n#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */\r\n#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */\r\n#define I2C_CR1_WUPEN_Pos            (18U)\r\n#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */\r\n#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */\r\n#define I2C_CR1_GCEN_Pos             (19U)\r\n#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */\r\n#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */\r\n#define I2C_CR1_SMBHEN_Pos           (20U)\r\n#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */\r\n#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */\r\n#define I2C_CR1_SMBDEN_Pos           (21U)\r\n#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */\r\n#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\r\n#define I2C_CR1_ALERTEN_Pos          (22U)\r\n#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */\r\n#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */\r\n#define I2C_CR1_PECEN_Pos            (23U)\r\n#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */\r\n#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */\r\n\r\n/******************  Bit definition for I2C_CR2 register  ********************/\r\n#define I2C_CR2_SADD_Pos             (0U)\r\n#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */\r\n#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */\r\n#define I2C_CR2_RD_WRN_Pos           (10U)\r\n#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */\r\n#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */\r\n#define I2C_CR2_ADD10_Pos            (11U)\r\n#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */\r\n#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */\r\n#define I2C_CR2_HEAD10R_Pos          (12U)\r\n#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */\r\n#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\r\n#define I2C_CR2_START_Pos            (13U)\r\n#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */\r\n#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */\r\n#define I2C_CR2_STOP_Pos             (14U)\r\n#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */\r\n#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */\r\n#define I2C_CR2_NACK_Pos             (15U)\r\n#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */\r\n#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */\r\n#define I2C_CR2_NBYTES_Pos           (16U)\r\n#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */\r\n#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */\r\n#define I2C_CR2_RELOAD_Pos           (24U)\r\n#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */\r\n#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */\r\n#define I2C_CR2_AUTOEND_Pos          (25U)\r\n#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */\r\n#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */\r\n#define I2C_CR2_PECBYTE_Pos          (26U)\r\n#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */\r\n#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */\r\n\r\n/*******************  Bit definition for I2C_OAR1 register  ******************/\r\n#define I2C_OAR1_OA1_Pos             (0U)\r\n#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */\r\n#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */\r\n#define I2C_OAR1_OA1MODE_Pos         (10U)\r\n#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */\r\n#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\r\n#define I2C_OAR1_OA1EN_Pos           (15U)\r\n#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */\r\n#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */\r\n\r\n/*******************  Bit definition for I2C_OAR2 register  ******************/\r\n#define I2C_OAR2_OA2_Pos             (1U)\r\n#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */\r\n#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */\r\n#define I2C_OAR2_OA2MSK_Pos          (8U)\r\n#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */\r\n#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */\r\n#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */\r\n#define I2C_OAR2_OA2MASK01_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */\r\n#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r\n#define I2C_OAR2_OA2MASK02_Pos       (9U)\r\n#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */\r\n#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r\n#define I2C_OAR2_OA2MASK03_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */\r\n#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r\n#define I2C_OAR2_OA2MASK04_Pos       (10U)\r\n#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */\r\n#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r\n#define I2C_OAR2_OA2MASK05_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */\r\n#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r\n#define I2C_OAR2_OA2MASK06_Pos       (9U)\r\n#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */\r\n#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r\n#define I2C_OAR2_OA2MASK07_Pos       (8U)\r\n#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */\r\n#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */\r\n#define I2C_OAR2_OA2EN_Pos           (15U)\r\n#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */\r\n#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */\r\n\r\n/*******************  Bit definition for I2C_TIMINGR register *******************/\r\n#define I2C_TIMINGR_SCLL_Pos         (0U)\r\n#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */\r\n#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */\r\n#define I2C_TIMINGR_SCLH_Pos         (8U)\r\n#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */\r\n#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\r\n#define I2C_TIMINGR_SDADEL_Pos       (16U)\r\n#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */\r\n#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */\r\n#define I2C_TIMINGR_SCLDEL_Pos       (20U)\r\n#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */\r\n#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */\r\n#define I2C_TIMINGR_PRESC_Pos        (28U)\r\n#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */\r\n#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */\r\n\r\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\r\n#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\r\n#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */\r\n#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */\r\n#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\r\n#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */\r\n#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */\r\n#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\r\n#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */\r\n#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */\r\n#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\r\n#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */\r\n#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/\r\n#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\r\n#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */\r\n#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\r\n\r\n/******************  Bit definition for I2C_ISR register  *********************/\r\n#define I2C_ISR_TXE_Pos              (0U)\r\n#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */\r\n#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */\r\n#define I2C_ISR_TXIS_Pos             (1U)\r\n#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */\r\n#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */\r\n#define I2C_ISR_RXNE_Pos             (2U)\r\n#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */\r\n#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\r\n#define I2C_ISR_ADDR_Pos             (3U)\r\n#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */\r\n#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/\r\n#define I2C_ISR_NACKF_Pos            (4U)\r\n#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */\r\n#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */\r\n#define I2C_ISR_STOPF_Pos            (5U)\r\n#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */\r\n#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */\r\n#define I2C_ISR_TC_Pos               (6U)\r\n#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */\r\n#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\r\n#define I2C_ISR_TCR_Pos              (7U)\r\n#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */\r\n#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */\r\n#define I2C_ISR_BERR_Pos             (8U)\r\n#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */\r\n#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */\r\n#define I2C_ISR_ARLO_Pos             (9U)\r\n#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */\r\n#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */\r\n#define I2C_ISR_OVR_Pos              (10U)\r\n#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */\r\n#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */\r\n#define I2C_ISR_PECERR_Pos           (11U)\r\n#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */\r\n#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */\r\n#define I2C_ISR_TIMEOUT_Pos          (12U)\r\n#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */\r\n#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */\r\n#define I2C_ISR_ALERT_Pos            (13U)\r\n#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */\r\n#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */\r\n#define I2C_ISR_BUSY_Pos             (15U)\r\n#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */\r\n#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */\r\n#define I2C_ISR_DIR_Pos              (16U)\r\n#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */\r\n#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\r\n#define I2C_ISR_ADDCODE_Pos          (17U)\r\n#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */\r\n#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\r\n\r\n/******************  Bit definition for I2C_ICR register  *********************/\r\n#define I2C_ICR_ADDRCF_Pos           (3U)\r\n#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */\r\n#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */\r\n#define I2C_ICR_NACKCF_Pos           (4U)\r\n#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */\r\n#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */\r\n#define I2C_ICR_STOPCF_Pos           (5U)\r\n#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */\r\n#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */\r\n#define I2C_ICR_BERRCF_Pos           (8U)\r\n#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */\r\n#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */\r\n#define I2C_ICR_ARLOCF_Pos           (9U)\r\n#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */\r\n#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\r\n#define I2C_ICR_OVRCF_Pos            (10U)\r\n#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */\r\n#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\r\n#define I2C_ICR_PECCF_Pos            (11U)\r\n#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */\r\n#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */\r\n#define I2C_ICR_TIMOUTCF_Pos         (12U)\r\n#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */\r\n#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */\r\n#define I2C_ICR_ALERTCF_Pos          (13U)\r\n#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */\r\n#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */\r\n\r\n/******************  Bit definition for I2C_PECR register  *********************/\r\n#define I2C_PECR_PEC_Pos             (0U)\r\n#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */\r\n#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\r\n\r\n/******************  Bit definition for I2C_RXDR register  *********************/\r\n#define I2C_RXDR_RXDATA_Pos          (0U)\r\n#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */\r\n#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\r\n\r\n/******************  Bit definition for I2C_TXDR register  *********************/\r\n#define I2C_TXDR_TXDATA_Pos          (0U)\r\n#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */\r\n#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Independent WATCHDOG                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define IWDG_KR_KEY_Pos      (0U)\r\n#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */\r\n#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\r\n\r\n/*******************  Bit definition for IWDG_PR register  ********************/\r\n#define IWDG_PR_PR_Pos       (0U)\r\n#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */\r\n#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\r\n#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */\r\n#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */\r\n#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */\r\n\r\n/*******************  Bit definition for IWDG_RLR register  *******************/\r\n#define IWDG_RLR_RL_Pos      (0U)\r\n#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */\r\n#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\r\n\r\n/*******************  Bit definition for IWDG_SR register  ********************/\r\n#define IWDG_SR_PVU_Pos      (0U)\r\n#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */\r\n#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\r\n#define IWDG_SR_RVU_Pos      (1U)\r\n#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */\r\n#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\r\n#define IWDG_SR_WVU_Pos      (2U)\r\n#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */\r\n#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\r\n\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define IWDG_WINR_WIN_Pos    (0U)\r\n#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */\r\n#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      LCD-TFT Display Controller (LTDC)                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for LTDC_SSCR register  *****************/\r\n\r\n#define LTDC_SSCR_VSH_Pos            (0U)\r\n#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */\r\n#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */\r\n#define LTDC_SSCR_HSW_Pos            (16U)\r\n#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */\r\n#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */\r\n\r\n/********************  Bit definition for LTDC_BPCR register  *****************/\r\n\r\n#define LTDC_BPCR_AVBP_Pos           (0U)\r\n#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */\r\n#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */\r\n#define LTDC_BPCR_AHBP_Pos           (16U)\r\n#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */\r\n#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */\r\n\r\n/********************  Bit definition for LTDC_AWCR register  *****************/\r\n\r\n#define LTDC_AWCR_AAH_Pos            (0U)\r\n#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */\r\n#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */\r\n#define LTDC_AWCR_AAW_Pos            (16U)\r\n#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */\r\n#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */\r\n\r\n/********************  Bit definition for LTDC_TWCR register  *****************/\r\n\r\n#define LTDC_TWCR_TOTALH_Pos         (0U)\r\n#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */\r\n#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total height */\r\n#define LTDC_TWCR_TOTALW_Pos         (16U)\r\n#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */\r\n#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */\r\n\r\n/********************  Bit definition for LTDC_GCR register  ******************/\r\n\r\n#define LTDC_GCR_LTDCEN_Pos          (0U)\r\n#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */\r\n#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */\r\n#define LTDC_GCR_DBW_Pos             (4U)\r\n#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */\r\n#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */\r\n#define LTDC_GCR_DGW_Pos             (8U)\r\n#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */\r\n#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */\r\n#define LTDC_GCR_DRW_Pos             (12U)\r\n#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */\r\n#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */\r\n#define LTDC_GCR_DEN_Pos             (16U)\r\n#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */\r\n#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */\r\n#define LTDC_GCR_PCPOL_Pos           (28U)\r\n#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */\r\n#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */\r\n#define LTDC_GCR_DEPOL_Pos           (29U)\r\n#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */\r\n#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */\r\n#define LTDC_GCR_VSPOL_Pos           (30U)\r\n#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */\r\n#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */\r\n#define LTDC_GCR_HSPOL_Pos           (31U)\r\n#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */\r\n#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */\r\n\r\n\r\n/********************  Bit definition for LTDC_SRCR register  *****************/\r\n\r\n#define LTDC_SRCR_IMR_Pos            (0U)\r\n#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */\r\n#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */\r\n#define LTDC_SRCR_VBR_Pos            (1U)\r\n#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */\r\n#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */\r\n\r\n/********************  Bit definition for LTDC_BCCR register  *****************/\r\n\r\n#define LTDC_BCCR_BCBLUE_Pos         (0U)\r\n#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */\r\n#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */\r\n#define LTDC_BCCR_BCGREEN_Pos        (8U)\r\n#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */\r\n#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */\r\n#define LTDC_BCCR_BCRED_Pos          (16U)\r\n#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */\r\n#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */\r\n\r\n/********************  Bit definition for LTDC_IER register  ******************/\r\n\r\n#define LTDC_IER_LIE_Pos             (0U)\r\n#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */\r\n#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */\r\n#define LTDC_IER_FUIE_Pos            (1U)\r\n#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */\r\n#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */\r\n#define LTDC_IER_TERRIE_Pos          (2U)\r\n#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */\r\n#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */\r\n#define LTDC_IER_RRIE_Pos            (3U)\r\n#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */\r\n#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */\r\n\r\n/********************  Bit definition for LTDC_ISR register  ******************/\r\n\r\n#define LTDC_ISR_LIF_Pos             (0U)\r\n#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */\r\n#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */\r\n#define LTDC_ISR_FUIF_Pos            (1U)\r\n#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */\r\n#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */\r\n#define LTDC_ISR_TERRIF_Pos          (2U)\r\n#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */\r\n#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */\r\n#define LTDC_ISR_RRIF_Pos            (3U)\r\n#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */\r\n#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_ICR register  ******************/\r\n\r\n#define LTDC_ICR_CLIF_Pos            (0U)\r\n#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */\r\n#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */\r\n#define LTDC_ICR_CFUIF_Pos           (1U)\r\n#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */\r\n#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */\r\n#define LTDC_ICR_CTERRIF_Pos         (2U)\r\n#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */\r\n#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */\r\n#define LTDC_ICR_CRRIF_Pos           (3U)\r\n#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */\r\n#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_LIPCR register  ****************/\r\n\r\n#define LTDC_LIPCR_LIPOS_Pos         (0U)\r\n#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */\r\n#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */\r\n\r\n/********************  Bit definition for LTDC_CPSR register  *****************/\r\n\r\n#define LTDC_CPSR_CYPOS_Pos          (0U)\r\n#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */\r\n#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */\r\n#define LTDC_CPSR_CXPOS_Pos          (16U)\r\n#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */\r\n#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */\r\n\r\n/********************  Bit definition for LTDC_CDSR register  *****************/\r\n\r\n#define LTDC_CDSR_VDES_Pos           (0U)\r\n#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */\r\n#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */\r\n#define LTDC_CDSR_HDES_Pos           (1U)\r\n#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */\r\n#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */\r\n#define LTDC_CDSR_VSYNCS_Pos         (2U)\r\n#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */\r\n#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */\r\n#define LTDC_CDSR_HSYNCS_Pos         (3U)\r\n#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */\r\n#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */\r\n\r\n/********************  Bit definition for LTDC_LxCR register  *****************/\r\n\r\n#define LTDC_LxCR_LEN_Pos            (0U)\r\n#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */\r\n#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */\r\n#define LTDC_LxCR_COLKEN_Pos         (1U)\r\n#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */\r\n#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */\r\n#define LTDC_LxCR_CLUTEN_Pos         (4U)\r\n#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */\r\n#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */\r\n\r\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\r\n\r\n#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)\r\n#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */\r\n#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */\r\n#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)\r\n#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */\r\n#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\r\n\r\n#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)\r\n#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */\r\n#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */\r\n#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)\r\n#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */\r\n#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\r\n\r\n#define LTDC_LxCKCR_CKBLUE_Pos       (0U)\r\n#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */\r\n#define LTDC_LxCKCR_CKGREEN_Pos      (8U)\r\n#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */\r\n#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */\r\n#define LTDC_LxCKCR_CKRED_Pos        (16U)\r\n#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */\r\n#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */\r\n\r\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\r\n\r\n#define LTDC_LxPFCR_PF_Pos           (0U)\r\n#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */\r\n#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */\r\n\r\n/********************  Bit definition for LTDC_LxCACR register  ***************/\r\n\r\n#define LTDC_LxCACR_CONSTA_Pos       (0U)\r\n#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\r\n\r\n#define LTDC_LxDCCR_DCBLUE_Pos       (0U)\r\n#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */\r\n#define LTDC_LxDCCR_DCGREEN_Pos      (8U)\r\n#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */\r\n#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */\r\n#define LTDC_LxDCCR_DCRED_Pos        (16U)\r\n#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */\r\n#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */\r\n#define LTDC_LxDCCR_DCALPHA_Pos      (24U)\r\n#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */\r\n#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxBFCR register  ***************/\r\n\r\n#define LTDC_LxBFCR_BF2_Pos          (0U)\r\n#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */\r\n#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */\r\n#define LTDC_LxBFCR_BF1_Pos          (8U)\r\n#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */\r\n#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */\r\n\r\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\r\n\r\n#define LTDC_LxCFBAR_CFBADD_Pos      (0U)\r\n#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */\r\n#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\r\n\r\n#define LTDC_LxCFBLR_CFBLL_Pos       (0U)\r\n#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */\r\n#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */\r\n#define LTDC_LxCFBLR_CFBP_Pos        (16U)\r\n#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */\r\n#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\r\n\r\n#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)\r\n#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */\r\n#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */\r\n\r\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\r\n\r\n#define LTDC_LxCLUTWR_BLUE_Pos       (0U)\r\n#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */\r\n#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */\r\n#define LTDC_LxCLUTWR_GREEN_Pos      (8U)\r\n#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */\r\n#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */\r\n#define LTDC_LxCLUTWR_RED_Pos        (16U)\r\n#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */\r\n#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */\r\n#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)\r\n#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */\r\n#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                     MDMA                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for MDMA_GISR0 register  ****************/\r\n#define MDMA_GISR0_GIF0_Pos       (0U)\r\n#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */\r\n#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */\r\n#define MDMA_GISR0_GIF1_Pos       (1U)\r\n#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */\r\n#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */\r\n#define MDMA_GISR0_GIF2_Pos       (2U)\r\n#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */\r\n#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */\r\n#define MDMA_GISR0_GIF3_Pos       (3U)\r\n#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */\r\n#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */\r\n#define MDMA_GISR0_GIF4_Pos       (4U)\r\n#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */\r\n#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */\r\n#define MDMA_GISR0_GIF5_Pos       (5U)\r\n#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */\r\n#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */\r\n#define MDMA_GISR0_GIF6_Pos       (6U)\r\n#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */\r\n#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */\r\n#define MDMA_GISR0_GIF7_Pos       (7U)\r\n#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */\r\n#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */\r\n#define MDMA_GISR0_GIF8_Pos       (8U)\r\n#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */\r\n#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */\r\n#define MDMA_GISR0_GIF9_Pos       (9U)\r\n#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */\r\n#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */\r\n#define MDMA_GISR0_GIF10_Pos      (10U)\r\n#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */\r\n#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */\r\n#define MDMA_GISR0_GIF11_Pos      (11U)\r\n#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */\r\n#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */\r\n#define MDMA_GISR0_GIF12_Pos      (12U)\r\n#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */\r\n#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */\r\n#define MDMA_GISR0_GIF13_Pos      (13U)\r\n#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */\r\n#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */\r\n#define MDMA_GISR0_GIF14_Pos      (14U)\r\n#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */\r\n#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */\r\n#define MDMA_GISR0_GIF15_Pos      (15U)\r\n#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */\r\n#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */\r\n\r\n/********************  Bit definition for MDMA_CxISR register  ****************/\r\n#define MDMA_CISR_TEIF_Pos        (0U)\r\n#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */\r\n#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */\r\n#define MDMA_CISR_CTCIF_Pos       (1U)\r\n#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */\r\n#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */\r\n#define MDMA_CISR_BRTIF_Pos       (2U)\r\n#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */\r\n#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */\r\n#define MDMA_CISR_BTIF_Pos        (3U)\r\n#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */\r\n#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */\r\n#define MDMA_CISR_TCIF_Pos        (4U)\r\n#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */\r\n#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */\r\n#define MDMA_CISR_CRQA_Pos        (16U)\r\n#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */\r\n#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x request Active flag */\r\n\r\n/********************  Bit definition for MDMA_CxIFCR register  ****************/\r\n#define MDMA_CIFCR_CTEIF_Pos      (0U)\r\n#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */\r\n#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */\r\n#define MDMA_CIFCR_CCTCIF_Pos     (1U)\r\n#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */\r\n#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */\r\n#define MDMA_CIFCR_CBRTIF_Pos     (2U)\r\n#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */\r\n#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */\r\n#define MDMA_CIFCR_CBTIF_Pos      (3U)\r\n#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */\r\n#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */\r\n#define MDMA_CIFCR_CLTCIF_Pos     (4U)\r\n#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */\r\n#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */\r\n\r\n/********************  Bit definition for MDMA_CxESR register  ****************/\r\n#define MDMA_CESR_TEA_Pos         (0U)\r\n#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */\r\n#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */\r\n#define MDMA_CESR_TED_Pos         (7U)\r\n#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */\r\n#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */\r\n#define MDMA_CESR_TELD_Pos        (8U)\r\n#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */\r\n#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */\r\n#define MDMA_CESR_TEMD_Pos        (9U)\r\n#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */\r\n#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */\r\n#define MDMA_CESR_ASE_Pos         (10U)\r\n#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */\r\n#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */\r\n#define MDMA_CESR_BSE_Pos         (11U)\r\n#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */\r\n#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */\r\n\r\n/********************  Bit definition for MDMA_CxCR register  ****************/\r\n#define MDMA_CCR_EN_Pos           (0U)\r\n#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */\r\n#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */\r\n#define MDMA_CCR_TEIE_Pos         (1U)\r\n#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */\r\n#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */\r\n#define MDMA_CCR_CTCIE_Pos        (2U)\r\n#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */\r\n#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */\r\n#define MDMA_CCR_BRTIE_Pos        (3U)\r\n#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */\r\n#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */\r\n#define MDMA_CCR_BTIE_Pos         (4U)\r\n#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */\r\n#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */\r\n#define MDMA_CCR_TCIE_Pos         (5U)\r\n#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */\r\n#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */\r\n#define MDMA_CCR_PL_Pos           (6U)\r\n#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */\r\n#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */\r\n#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */\r\n#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */\r\n#define MDMA_CCR_BEX_Pos          (12U)\r\n#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */\r\n#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianness eXchange */\r\n#define MDMA_CCR_HEX_Pos          (13U)\r\n#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */\r\n#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianness eXchange */\r\n#define MDMA_CCR_WEX_Pos          (14U)\r\n#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */\r\n#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianness eXchange */\r\n#define MDMA_CCR_SWRQ_Pos         (16U)\r\n#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */\r\n#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */\r\n\r\n/********************  Bit definition for MDMA_CxTCR register  ****************/\r\n#define MDMA_CTCR_SINC_Pos        (0U)\r\n#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */\r\n#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */\r\n#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */\r\n#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */\r\n#define MDMA_CTCR_DINC_Pos        (2U)\r\n#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */\r\n#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */\r\n#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */\r\n#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */\r\n#define MDMA_CTCR_SSIZE_Pos       (4U)\r\n#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */\r\n#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */\r\n#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */\r\n#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */\r\n#define MDMA_CTCR_DSIZE_Pos       (6U)\r\n#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */\r\n#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */\r\n#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */\r\n#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */\r\n#define MDMA_CTCR_SINCOS_Pos      (8U)\r\n#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */\r\n#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */\r\n#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */\r\n#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */\r\n#define MDMA_CTCR_DINCOS_Pos      (10U)\r\n#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */\r\n#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */\r\n#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */\r\n#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */\r\n#define MDMA_CTCR_SBURST_Pos      (12U)\r\n#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */\r\n#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */\r\n#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */\r\n#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */\r\n#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */\r\n#define MDMA_CTCR_DBURST_Pos      (15U)\r\n#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */\r\n#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */\r\n#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */\r\n#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */\r\n#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */\r\n#define MDMA_CTCR_TLEN_Pos        (18U)\r\n#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */\r\n#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */\r\n#define MDMA_CTCR_PKE_Pos         (25U)\r\n#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */\r\n#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */\r\n#define MDMA_CTCR_PAM_Pos         (26U)\r\n#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */\r\n#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignment Mode */\r\n#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */\r\n#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */\r\n#define MDMA_CTCR_TRGM_Pos        (28U)\r\n#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */\r\n#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */\r\n#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */\r\n#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */\r\n#define MDMA_CTCR_SWRM_Pos        (30U)\r\n#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */\r\n#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */\r\n#define MDMA_CTCR_BWM_Pos         (31U)\r\n#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */\r\n#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */\r\n\r\n/********************  Bit definition for MDMA_CxBNDTR register  ****************/\r\n#define MDMA_CBNDTR_BNDT_Pos      (0U)\r\n#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */\r\n#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */\r\n#define MDMA_CBNDTR_BRSUM_Pos     (18U)\r\n#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */\r\n#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */\r\n#define MDMA_CBNDTR_BRDUM_Pos     (19U)\r\n#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */\r\n#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */\r\n#define MDMA_CBNDTR_BRC_Pos       (20U)\r\n#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */\r\n#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */\r\n\r\n/********************  Bit definition for MDMA_CxSAR register  ****************/\r\n#define MDMA_CSAR_SAR_Pos         (0U)\r\n#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */\r\n\r\n/********************  Bit definition for MDMA_CxDAR register  ****************/\r\n#define MDMA_CDAR_DAR_Pos         (0U)\r\n#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */\r\n\r\n/********************  Bit definition for MDMA_CxBRUR  ************************/\r\n#define MDMA_CBRUR_SUV_Pos        (0U)\r\n#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */\r\n#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */\r\n#define MDMA_CBRUR_DUV_Pos        (16U)\r\n#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */\r\n#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */\r\n\r\n/********************  Bit definition for MDMA_CxLAR  *************************/\r\n#define MDMA_CLAR_LAR_Pos         (0U)\r\n#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */\r\n\r\n/********************  Bit definition for MDMA_CxTBR)  ************************/\r\n#define MDMA_CTBR_TSEL_Pos        (0U)\r\n#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */\r\n#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */\r\n#define MDMA_CTBR_SBUS_Pos        (16U)\r\n#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */\r\n#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */\r\n#define MDMA_CTBR_DBUS_Pos        (17U)\r\n#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */\r\n#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */\r\n\r\n/********************  Bit definition for MDMA_CxMAR)  ************************/\r\n#define MDMA_CMAR_MAR_Pos         (0U)\r\n#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */\r\n\r\n/********************  Bit definition for MDMA_CxMDR)  ************************/\r\n#define MDMA_CMDR_MDR_Pos         (0U)\r\n#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */\r\n#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Operational Amplifier (OPAMP)                      */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*********************  Bit definition for OPAMPx_CSR register  ***************/\r\n#define OPAMP_CSR_OPAMPxEN_Pos           (0U)\r\n#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */\r\n#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */\r\n#define OPAMP_CSR_FORCEVP_Pos            (1U)\r\n#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */\r\n#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */\r\n\r\n#define OPAMP_CSR_VPSEL_Pos              (2U)\r\n#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */\r\n#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */\r\n#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */\r\n#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */\r\n\r\n#define OPAMP_CSR_VMSEL_Pos              (5U)\r\n#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */\r\n#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */\r\n#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */\r\n#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */\r\n\r\n#define OPAMP_CSR_OPAHSM_Pos             (8U)\r\n#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */\r\n#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */\r\n#define OPAMP_CSR_CALON_Pos              (11U)\r\n#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */\r\n#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */\r\n\r\n#define OPAMP_CSR_CALSEL_Pos             (12U)\r\n#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */\r\n#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */\r\n#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */\r\n#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */\r\n\r\n#define OPAMP_CSR_PGGAIN_Pos             (14U)\r\n#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */\r\n#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */\r\n#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */\r\n#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */\r\n#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */\r\n#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */\r\n\r\n#define OPAMP_CSR_USERTRIM_Pos           (18U)\r\n#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */\r\n#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */\r\n#define OPAMP_CSR_TSTREF_Pos             (29U)\r\n#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */\r\n#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */\r\n#define OPAMP_CSR_CALOUT_Pos             (30U)\r\n#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */\r\n#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */\r\n\r\n/*********************  Bit definition for OPAMP1_CSR register  ***************/\r\n#define OPAMP1_CSR_OPAEN_Pos              (0U)\r\n#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r\n#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */\r\n#define OPAMP1_CSR_FORCEVP_Pos            (1U)\r\n#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */\r\n#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */\r\n\r\n#define OPAMP1_CSR_VPSEL_Pos              (2U)\r\n#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */\r\n#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r\n#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */\r\n#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */\r\n\r\n#define OPAMP1_CSR_VMSEL_Pos              (5U)\r\n#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */\r\n#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r\n#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */\r\n#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */\r\n\r\n#define OPAMP1_CSR_OPAHSM_Pos             (8U)\r\n#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */\r\n#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */\r\n#define OPAMP1_CSR_CALON_Pos              (11U)\r\n#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */\r\n#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */\r\n\r\n#define OPAMP1_CSR_CALSEL_Pos             (12U)\r\n#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */\r\n#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */\r\n#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */\r\n#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */\r\n\r\n#define OPAMP1_CSR_PGGAIN_Pos             (14U)\r\n#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */\r\n#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */\r\n#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */\r\n#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */\r\n#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */\r\n#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */\r\n\r\n#define OPAMP1_CSR_USERTRIM_Pos           (18U)\r\n#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */\r\n#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */\r\n#define OPAMP1_CSR_TSTREF_Pos             (29U)\r\n#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */\r\n#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */\r\n#define OPAMP1_CSR_CALOUT_Pos             (30U)\r\n#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */\r\n#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */\r\n\r\n/*********************  Bit definition for OPAMP2_CSR register  ***************/\r\n#define OPAMP2_CSR_OPAEN_Pos              (0U)\r\n#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */\r\n#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */\r\n#define OPAMP2_CSR_FORCEVP_Pos            (1U)\r\n#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */\r\n#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */\r\n\r\n#define OPAMP2_CSR_VPSEL_Pos              (2U)\r\n#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */\r\n#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\r\n#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */\r\n#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */\r\n\r\n#define OPAMP2_CSR_VMSEL_Pos              (5U)\r\n#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */\r\n#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */\r\n#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */\r\n#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */\r\n\r\n#define OPAMP2_CSR_OPAHSM_Pos             (8U)\r\n#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */\r\n#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */\r\n#define OPAMP2_CSR_CALON_Pos              (11U)\r\n#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */\r\n#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */\r\n\r\n#define OPAMP2_CSR_CALSEL_Pos             (12U)\r\n#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */\r\n#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */\r\n#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */\r\n#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */\r\n\r\n#define OPAMP2_CSR_PGGAIN_Pos             (14U)\r\n#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */\r\n#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */\r\n#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */\r\n#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */\r\n#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */\r\n#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */\r\n\r\n#define OPAMP2_CSR_USERTRIM_Pos           (18U)\r\n#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */\r\n#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */\r\n#define OPAMP2_CSR_TSTREF_Pos             (29U)\r\n#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */\r\n#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */\r\n#define OPAMP2_CSR_CALOUT_Pos             (30U)\r\n#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */\r\n#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */\r\n\r\n/*******************  Bit definition for OPAMP_OTR register  ******************/\r\n#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)\r\n#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */\r\n#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)\r\n#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP1_OTR register  ******************/\r\n#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)\r\n#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r\n#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)\r\n#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP2_OTR register  ******************/\r\n#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)\r\n#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\r\n#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)\r\n#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP_HSOTR register  ****************/\r\n#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)\r\n#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */\r\n#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)\r\n#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP1_HSOTR register  ****************/\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r\n\r\n/*******************  Bit definition for OPAMP2_HSOTR register  ****************/\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */\r\n#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Parallel Synchronous Slave Interface (PSSI )                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for PSSI_CR register  *******************/\r\n#define PSSI_CR_OUTEN_Pos               (31U)\r\n#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */\r\n#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */\r\n#define PSSI_CR_DMAEN_Pos               (30U)\r\n#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */\r\n#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */\r\n#define PSSI_CR_DERDYCFG_Pos            (18U)\r\n#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */\r\n#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */\r\n#define PSSI_CR_ENABLE_Pos              (14U)\r\n#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */\r\n#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */\r\n#define PSSI_CR_EDM_Pos                 (10U)\r\n#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */\r\n#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */\r\n#define PSSI_CR_RDYPOL_Pos              (8U)\r\n#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */\r\n#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */\r\n#define PSSI_CR_DEPOL_Pos               (6U)\r\n#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */\r\n#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */\r\n#define PSSI_CR_CKPOL_Pos               (5U)\r\n#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */\r\n#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */\r\n/********************  Bit definition for PSSI_SR register  *******************/\r\n#define PSSI_SR_RTT1B_Pos               (3U)\r\n#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */\r\n#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */\r\n#define PSSI_SR_RTT4B_Pos               (2U)\r\n#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */\r\n#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */\r\n/********************  Bit definition for PSSI_RIS register  *******************/\r\n#define PSSI_RIS_OVR_RIS_Pos            (1U)\r\n#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */\r\n#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */\r\n/********************  Bit definition for PSSI_IER register  *******************/\r\n#define PSSI_IER_OVR_IE_Pos             (1U)\r\n#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */\r\n#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */\r\n/********************  Bit definition for PSSI_MIS register  *******************/\r\n#define PSSI_MIS_OVR_MIS_Pos            (1U)\r\n#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */\r\n#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */\r\n/********************  Bit definition for PSSI_ICR register  *******************/\r\n#define PSSI_ICR_OVR_ISC_Pos            (1U)\r\n#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */\r\n#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */\r\n/********************  Bit definition for PSSI_DR register  *******************/\r\n#define PSSI_DR_DR_Pos                  (0U)\r\n#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */\r\n#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                              On The Fly Decryption                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for OTFDEC_CR register  ******************/\r\n#define OTFDEC_CR_ENC_Pos                      (0U)\r\n#define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */\r\n#define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */\r\n\r\n/******************  Bit definition for OTFDEC_PRIVCFGR register  ************/\r\n#define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)\r\n#define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */\r\n#define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */\r\n\r\n/******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/\r\n#define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)\r\n#define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */\r\n#define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */\r\n\r\n#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)\r\n#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */\r\n#define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */\r\n\r\n#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)\r\n#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */\r\n#define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */\r\n\r\n#define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)\r\n#define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */\r\n#define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */\r\n#define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */\r\n#define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */\r\n\r\n#define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)\r\n#define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */\r\n#define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */\r\n\r\n#define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)\r\n#define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */\r\n#define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */\r\n\r\n/******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/\r\n#define OTFDEC_REG_START_ADDR_Pos              (0U)\r\n#define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */\r\n\r\n/******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/\r\n#define OTFDEC_REG_END_ADDR_Pos                (0U)\r\n#define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */\r\n\r\n/******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/\r\n#define OTFDEC_REG_NONCER0_Pos                 (0U)\r\n#define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/\r\n#define OTFDEC_REG_NONCER1_Pos                 (0U)\r\n#define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/\r\n#define OTFDEC_REG_KEYR0_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/\r\n#define OTFDEC_REG_KEYR1_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/\r\n#define OTFDEC_REG_KEYR2_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */\r\n\r\n/******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/\r\n#define OTFDEC_REG_KEYR3_Pos                   (0U)\r\n#define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */\r\n#define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */\r\n\r\n/******************  Bit definition for OTFDEC_ISR register  *****************/\r\n#define OTFDEC_ISR_SEIF_Pos                    (0U)\r\n#define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */\r\n#define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */\r\n\r\n#define OTFDEC_ISR_XONEIF_Pos                  (1U)\r\n#define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */\r\n#define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */\r\n\r\n#define OTFDEC_ISR_KEIF_Pos                    (2U)\r\n#define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */\r\n#define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */\r\n\r\n/******************  Bit definition  for OTFDEC_ICR register  *****************/\r\n#define OTFDEC_ICR_SEIF_Pos                    (0U)\r\n#define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */\r\n#define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */\r\n\r\n#define OTFDEC_ICR_XONEIF_Pos                  (1U)\r\n#define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */\r\n#define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */\r\n\r\n#define OTFDEC_ICR_KEIF_Pos                    (2U)\r\n#define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */\r\n#define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */\r\n\r\n/******************  Bit definition for OTFDEC_IER register  *****************/\r\n#define OTFDEC_IER_SEIE_Pos                    (0U)\r\n#define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */\r\n#define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */\r\n\r\n#define OTFDEC_IER_XONEIE_Pos                  (1U)\r\n#define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */\r\n#define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */\r\n\r\n#define OTFDEC_IER_KEIE_Pos                    (2U)\r\n#define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */\r\n#define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             Power Control                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*************************  NUMBER OF POWER DOMAINS  **************************/\r\n#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */\r\n\r\n/********************  Bit definition for PWR_CR1 register  *******************/\r\n#define PWR_CR1_ALS_Pos                (17U)\r\n#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */\r\n#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */\r\n#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */\r\n#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */\r\n#define PWR_CR1_AVDEN_Pos              (16U)\r\n#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */\r\n#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */\r\n#define PWR_CR1_SVOS_Pos               (14U)\r\n#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */\r\n#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */\r\n#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */\r\n#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */\r\n#define PWR_CR1_FLPS_Pos               (9U)\r\n#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */\r\n#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */\r\n#define PWR_CR1_DBP_Pos                (8U)\r\n#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */\r\n#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */\r\n#define PWR_CR1_PLS_Pos                (5U)\r\n#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */\r\n#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */\r\n#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */\r\n#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */\r\n#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */\r\n#define PWR_CR1_PVDEN_Pos              (4U)\r\n#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */\r\n#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */\r\n#define PWR_CR1_LPDS_Pos               (0U)\r\n#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */\r\n#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */\r\n\r\n/*!< PVD level configuration */\r\n#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */\r\n#define PWR_CR1_PLS_LEV1_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */\r\n#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */\r\n#define PWR_CR1_PLS_LEV2_Pos           (6U)\r\n#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */\r\n#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */\r\n#define PWR_CR1_PLS_LEV3_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */\r\n#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */\r\n#define PWR_CR1_PLS_LEV4_Pos           (7U)\r\n#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */\r\n#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */\r\n#define PWR_CR1_PLS_LEV5_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */\r\n#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */\r\n#define PWR_CR1_PLS_LEV6_Pos           (6U)\r\n#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */\r\n#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */\r\n#define PWR_CR1_PLS_LEV7_Pos           (5U)\r\n#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */\r\n#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */\r\n\r\n/*!< AVD level configuration */\r\n#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */\r\n#define PWR_CR1_ALS_LEV1_Pos           (17U)\r\n#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */\r\n#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */\r\n#define PWR_CR1_ALS_LEV2_Pos           (18U)\r\n#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */\r\n#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */\r\n#define PWR_CR1_ALS_LEV3_Pos           (17U)\r\n#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */\r\n#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */\r\n\r\n/********************  Bit definition for PWR_CSR1 register  ******************/\r\n#define PWR_CSR1_AVDO_Pos              (16U)\r\n#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */\r\n#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */\r\n#define PWR_CSR1_ACTVOS_Pos            (14U)\r\n#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */\r\n#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */\r\n#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */\r\n#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */\r\n#define PWR_CSR1_ACTVOSRDY_Pos         (13U)\r\n#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */\r\n#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */\r\n#define PWR_CSR1_PVDO_Pos              (4U)\r\n#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */\r\n#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */\r\n\r\n/********************  Bit definition for PWR_CR2 register  *******************/\r\n#define PWR_CR2_TEMPH_Pos              (23U)\r\n#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */\r\n#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */\r\n#define PWR_CR2_TEMPL_Pos              (22U)\r\n#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */\r\n#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */\r\n#define PWR_CR2_VBATH_Pos              (21U)\r\n#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */\r\n#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */\r\n#define PWR_CR2_VBATL_Pos              (20U)\r\n#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */\r\n#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */\r\n#define PWR_CR2_BRRDY_Pos              (16U)\r\n#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */\r\n#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */\r\n#define PWR_CR2_MONEN_Pos              (4U)\r\n#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */\r\n#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */\r\n#define PWR_CR2_BREN_Pos               (0U)\r\n#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */\r\n#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */\r\n\r\n/********************  Bit definition for PWR_CR3 register  *******************/\r\n#define PWR_CR3_USB33RDY_Pos           (26U)\r\n#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */\r\n#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */\r\n#define PWR_CR3_USBREGEN_Pos           (25U)\r\n#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */\r\n#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */\r\n#define PWR_CR3_USB33DEN_Pos           (24U)\r\n#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */\r\n#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */\r\n#define PWR_CR3_SMPSEXTRDY_Pos         (16U)\r\n#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */\r\n#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */\r\n#define PWR_CR3_VBRS_Pos               (9U)\r\n#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */\r\n#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */\r\n#define PWR_CR3_VBE_Pos                (8U)\r\n#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */\r\n#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */\r\n#define PWR_CR3_SMPSLEVEL_Pos          (4U)\r\n#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */\r\n#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */\r\n#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */\r\n#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */\r\n#define PWR_CR3_SMPSEXTHP_Pos          (3U)\r\n#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */\r\n#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */\r\n#define PWR_CR3_SMPSEN_Pos             (2U)\r\n#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */\r\n#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */\r\n#define PWR_CR3_LDOEN_Pos              (1U)\r\n#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */\r\n#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */\r\n#define PWR_CR3_BYPASS_Pos             (0U)\r\n#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */\r\n#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */\r\n\r\n/********************  Bit definition for PWR_CPUCR register  *****************/\r\n#define PWR_CPUCR_RUN_D3_Pos           (11U)\r\n#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */\r\n#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */\r\n#define PWR_CPUCR_CSSF_Pos             (9U)\r\n#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */\r\n#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */\r\n#define PWR_CPUCR_SBF_D2_Pos           (8U)\r\n#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */\r\n#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */\r\n#define PWR_CPUCR_SBF_D1_Pos           (7U)\r\n#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */\r\n#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */\r\n#define PWR_CPUCR_SBF_Pos              (6U)\r\n#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */\r\n#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */\r\n#define PWR_CPUCR_STOPF_Pos            (5U)\r\n#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */\r\n#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */\r\n#define PWR_CPUCR_PDDS_D3_Pos          (2U)\r\n#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */\r\n#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */\r\n#define PWR_CPUCR_PDDS_D2_Pos          (1U)\r\n#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */\r\n#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */\r\n#define PWR_CPUCR_PDDS_D1_Pos          (0U)\r\n#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */\r\n#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */\r\n\r\n\r\n/********************  Bit definition for PWR_D3CR register  ******************/\r\n#define PWR_D3CR_VOS_Pos               (14U)\r\n#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */\r\n#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */\r\n#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */\r\n#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */\r\n#define PWR_D3CR_VOSRDY_Pos            (13U)\r\n#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */\r\n#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */\r\n\r\n/******************  Bit definition for PWR_WKUPCR register  ******************/\r\n#define PWR_WKUPCR_WKUPC6_Pos          (5U)\r\n#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */\r\n#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */\r\n#define PWR_WKUPCR_WKUPC4_Pos          (3U)\r\n#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */\r\n#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */\r\n#define PWR_WKUPCR_WKUPC2_Pos          (1U)\r\n#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */\r\n#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */\r\n#define PWR_WKUPCR_WKUPC1_Pos          (0U)\r\n#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */\r\n#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */\r\n\r\n/********************  Bit definition for PWR_WKUPFR register  ****************/\r\n#define PWR_WKUPFR_WKUPF6_Pos          (5U)\r\n#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */\r\n#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */\r\n#define PWR_WKUPFR_WKUPF4_Pos          (3U)\r\n#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */\r\n#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */\r\n#define PWR_WKUPFR_WKUPF2_Pos          (1U)\r\n#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */\r\n#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */\r\n#define PWR_WKUPFR_WKUPF1_Pos          (0U)\r\n#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */\r\n#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */\r\n\r\n/******************  Bit definition for PWR_WKUPEPR register  *****************/\r\n#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)\r\n#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */\r\n#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */\r\n#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */\r\n#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */\r\n#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)\r\n#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */\r\n#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */\r\n#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */\r\n#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */\r\n#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)\r\n#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */\r\n#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */\r\n#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */\r\n#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */\r\n#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)\r\n#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */\r\n#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */\r\n#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */\r\n#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */\r\n#define PWR_WKUPEPR_WKUPP6_Pos         (13U)\r\n#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */\r\n#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */\r\n#define PWR_WKUPEPR_WKUPP4_Pos         (11U)\r\n#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */\r\n#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */\r\n#define PWR_WKUPEPR_WKUPP2_Pos         (9U)\r\n#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */\r\n#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */\r\n#define PWR_WKUPEPR_WKUPP1_Pos         (8U)\r\n#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */\r\n#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */\r\n#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)\r\n#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */\r\n#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */\r\n#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)\r\n#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */\r\n#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */\r\n#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)\r\n#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */\r\n#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */\r\n#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)\r\n#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */\r\n#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */\r\n#define PWR_WKUPEPR_WKUPEN_Pos         (0U)\r\n#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */\r\n#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Reset and Clock Control                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************************  RCC VERSION  ********************************/\r\n#define RCC_VER_3_0\r\n\r\n/********************  Bit definition for RCC_CR register  ********************/\r\n#define RCC_CR_HSION_Pos                       (0U)\r\n#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */\r\n#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */\r\n#define RCC_CR_HSIKERON_Pos                    (1U)\r\n#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */\r\n#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */\r\n#define RCC_CR_HSIRDY_Pos                      (2U)\r\n#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */\r\n#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */\r\n#define RCC_CR_HSIDIV_Pos                      (3U)\r\n#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */\r\n#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */\r\n#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */\r\n#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */\r\n#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */\r\n#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */\r\n\r\n#define RCC_CR_HSIDIVF_Pos                     (5U)\r\n#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */\r\n#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */\r\n#define RCC_CR_CSION_Pos                       (7U)\r\n#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */\r\n#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */\r\n#define RCC_CR_CSIRDY_Pos                      (8U)\r\n#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */\r\n#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */\r\n#define RCC_CR_CSIKERON_Pos                    (9U)\r\n#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */\r\n#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */\r\n#define RCC_CR_HSI48ON_Pos                     (12U)\r\n#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */\r\n#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */\r\n#define RCC_CR_HSI48RDY_Pos                    (13U)\r\n#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */\r\n#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */\r\n\r\n#define RCC_CR_D1CKRDY_Pos                     (14U)\r\n#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */\r\n#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */\r\n#define RCC_CR_D2CKRDY_Pos                     (15U)\r\n#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */\r\n#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */\r\n\r\n#define RCC_CR_HSEON_Pos                       (16U)\r\n#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */\r\n#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */\r\n#define RCC_CR_HSERDY_Pos                      (17U)\r\n#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */\r\n#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */\r\n#define RCC_CR_HSEBYP_Pos                      (18U)\r\n#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */\r\n#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */\r\n#define RCC_CR_CSSHSEON_Pos                    (19U)\r\n#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */\r\n#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */\r\n\r\n\r\n#define RCC_CR_PLL1ON_Pos                      (24U)\r\n#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */\r\n#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */\r\n#define RCC_CR_PLL1RDY_Pos                     (25U)\r\n#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */\r\n#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */\r\n#define RCC_CR_PLL2ON_Pos                      (26U)\r\n#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */\r\n#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */\r\n#define RCC_CR_PLL2RDY_Pos                     (27U)\r\n#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */\r\n#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */\r\n#define RCC_CR_PLL3ON_Pos                      (28U)\r\n#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */\r\n#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */\r\n#define RCC_CR_PLL3RDY_Pos                     (29U)\r\n#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */\r\n#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */\r\n\r\n/*Legacy */\r\n#define RCC_CR_PLLON_Pos                       (24U)\r\n#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */\r\n#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */\r\n#define RCC_CR_PLLRDY_Pos                      (25U)\r\n#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */\r\n#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */\r\n\r\n/********************  Bit definition for RCC_HSICFGR register  ***************/\r\n/*!< HSICAL configuration */\r\n#define RCC_HSICFGR_HSICAL_Pos                 (0U)\r\n#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */\r\n#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */\r\n#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */\r\n#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */\r\n#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */\r\n#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */\r\n#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */\r\n#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */\r\n#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */\r\n#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */\r\n#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */\r\n#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */\r\n#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */\r\n#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */\r\n\r\n/*!< HSITRIM configuration */\r\n#define RCC_HSICFGR_HSITRIM_Pos                (24U)\r\n#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */\r\n#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */\r\n#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */\r\n#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */\r\n#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */\r\n#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */\r\n#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */\r\n#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */\r\n#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */\r\n\r\n\r\n/********************  Bit definition for RCC_CRRCR register  *****************/\r\n\r\n/*!< HSI48CAL configuration */\r\n#define RCC_CRRCR_HSI48CAL_Pos                 (0U)\r\n#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */\r\n#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */\r\n#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */\r\n#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */\r\n#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */\r\n#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */\r\n#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */\r\n#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */\r\n#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */\r\n#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */\r\n#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */\r\n#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */\r\n\r\n\r\n/********************  Bit definition for RCC_CSICFGR register  *****************/\r\n/*!< CSICAL configuration */\r\n#define RCC_CSICFGR_CSICAL_Pos                 (0U)\r\n#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */\r\n#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */\r\n#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */\r\n#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */\r\n#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */\r\n#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */\r\n#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */\r\n#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */\r\n#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */\r\n#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */\r\n\r\n/*!< CSITRIM configuration */\r\n#define RCC_CSICFGR_CSITRIM_Pos                (24U)\r\n#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */\r\n#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */\r\n#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */\r\n#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */\r\n#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */\r\n#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */\r\n#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */\r\n#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for RCC_CFGR register  ******************/\r\n/*!< SW configuration */\r\n#define RCC_CFGR_SW_Pos                        (0U)\r\n#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */\r\n#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */\r\n#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\r\n#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\r\n#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */\r\n\r\n#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */\r\n#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */\r\n#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */\r\n#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */\r\n\r\n/*!< SWS configuration */\r\n#define RCC_CFGR_SWS_Pos                       (3U)\r\n#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */\r\n#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */\r\n#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\r\n#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */\r\n#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */\r\n\r\n#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */\r\n#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */\r\n#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */\r\n#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */\r\n\r\n#define RCC_CFGR_STOPWUCK_Pos                  (6U)\r\n#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */\r\n#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */\r\n\r\n#define RCC_CFGR_STOPKERWUCK_Pos               (7U)\r\n#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */\r\n#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */\r\n\r\n/*!< RTCPRE configuration */\r\n#define RCC_CFGR_RTCPRE_Pos                    (8U)\r\n#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)\r\n#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */\r\n#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */\r\n#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */\r\n#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */\r\n#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */\r\n#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */\r\n#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */\r\n\r\n\r\n/*!< TIMPRE configuration */\r\n#define RCC_CFGR_TIMPRE_Pos                    (15U)\r\n#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)\r\n#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */\r\n\r\n/*!< MCO1 configuration */\r\n#define RCC_CFGR_MCO1_Pos                      (22U)\r\n#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)\r\n#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */\r\n#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */\r\n#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */\r\n#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */\r\n\r\n#define RCC_CFGR_MCO1PRE_Pos                   (18U)\r\n#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)\r\n#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */\r\n#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */\r\n#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */\r\n#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */\r\n#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */\r\n\r\n#define RCC_CFGR_MCO2PRE_Pos                   (25U)\r\n#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)\r\n#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */\r\n#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */\r\n#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */\r\n#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */\r\n#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */\r\n\r\n#define RCC_CFGR_MCO2_Pos                      (29U)\r\n#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)\r\n#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */\r\n#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */\r\n#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */\r\n#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for RCC_D1CFGR register  ******************/\r\n/*!< D1HPRE configuration */\r\n#define RCC_D1CFGR_HPRE_Pos                    (0U)\r\n#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */\r\n#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */\r\n#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */\r\n#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */\r\n#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */\r\n#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */\r\n\r\n\r\n#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */\r\n#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)\r\n#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */\r\n#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */\r\n#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)\r\n#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */\r\n#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */\r\n#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)\r\n#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */\r\n#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */\r\n#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)\r\n#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */\r\n#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */\r\n#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)\r\n#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */\r\n#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */\r\n#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)\r\n#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */\r\n#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */\r\n#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)\r\n#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */\r\n#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */\r\n#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)\r\n#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */\r\n#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */\r\n\r\n/*!< D1PPRE configuration */\r\n#define RCC_D1CFGR_D1PPRE_Pos                  (4U)\r\n#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */\r\n#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */\r\n#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */\r\n#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */\r\n#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */\r\n\r\n#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */\r\n#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)\r\n#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */\r\n#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */\r\n#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)\r\n#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */\r\n#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */\r\n#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)\r\n#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */\r\n#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */\r\n#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)\r\n#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */\r\n#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */\r\n\r\n#define RCC_D1CFGR_D1CPRE_Pos                  (8U)\r\n#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */\r\n#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */\r\n#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */\r\n#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */\r\n#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */\r\n#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */\r\n\r\n#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */\r\n#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)\r\n#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */\r\n#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */\r\n#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */\r\n#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */\r\n#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)\r\n#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */\r\n#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */\r\n#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)\r\n#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */\r\n#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */\r\n#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)\r\n#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */\r\n#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)\r\n#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */\r\n#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */\r\n\r\n/********************  Bit definition for RCC_D2CFGR register  ******************/\r\n/*!< D2PPRE1 configuration */\r\n#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)\r\n#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */\r\n#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */\r\n#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */\r\n#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */\r\n#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */\r\n\r\n#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */\r\n#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)\r\n#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */\r\n#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */\r\n\r\n/*!< D2PPRE2 configuration */\r\n#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)\r\n#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */\r\n#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */\r\n#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */\r\n#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */\r\n#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */\r\n\r\n#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */\r\n#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)\r\n#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */\r\n#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */\r\n\r\n/********************  Bit definition for RCC_D3CFGR register  ******************/\r\n/*!< D3PPRE configuration */\r\n#define RCC_D3CFGR_D3PPRE_Pos                  (4U)\r\n#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */\r\n#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */\r\n#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */\r\n#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */\r\n#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */\r\n\r\n#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */\r\n#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)\r\n#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */\r\n#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */\r\n#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)\r\n#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */\r\n#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */\r\n#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)\r\n#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */\r\n#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */\r\n#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)\r\n#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */\r\n#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */\r\n\r\n/********************  Bit definition for RCC_PLLCKSELR register  *************/\r\n\r\n#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)\r\n#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */\r\n#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk\r\n\r\n#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */\r\n#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)\r\n#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */\r\n#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */\r\n#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)\r\n#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */\r\n#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */\r\n#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)\r\n#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */\r\n#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */\r\n\r\n#define RCC_PLLCKSELR_DIVM1_Pos                (4U)\r\n#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */\r\n#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk\r\n#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */\r\n#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */\r\n#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */\r\n#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */\r\n#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */\r\n#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */\r\n\r\n#define RCC_PLLCKSELR_DIVM2_Pos                (12U)\r\n#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */\r\n#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk\r\n#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */\r\n#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */\r\n#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */\r\n#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */\r\n#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */\r\n#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */\r\n\r\n#define RCC_PLLCKSELR_DIVM3_Pos                (20U)\r\n#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */\r\n#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk\r\n#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */\r\n#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */\r\n#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */\r\n#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */\r\n#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */\r\n#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */\r\n\r\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\r\n\r\n#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)\r\n#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */\r\n#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk\r\n#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)\r\n#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */\r\n#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk\r\n#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)\r\n#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\r\n#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk\r\n#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */\r\n#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */\r\n#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */\r\n#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */\r\n\r\n#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)\r\n#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */\r\n#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk\r\n#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)\r\n#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */\r\n#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk\r\n#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)\r\n#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\r\n#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk\r\n#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */\r\n#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */\r\n#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */\r\n#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */\r\n\r\n#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)\r\n#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */\r\n#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk\r\n#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)\r\n#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */\r\n#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk\r\n#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)\r\n#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\r\n#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk\r\n#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */\r\n#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */\r\n#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */\r\n#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */\r\n\r\n#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)\r\n#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */\r\n#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk\r\n#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)\r\n#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */\r\n#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk\r\n#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)\r\n#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */\r\n#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk\r\n\r\n#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)\r\n#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */\r\n#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk\r\n#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)\r\n#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */\r\n#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk\r\n#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)\r\n#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */\r\n#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk\r\n\r\n#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)\r\n#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */\r\n#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk\r\n#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)\r\n#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */\r\n#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk\r\n#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)\r\n#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */\r\n#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_PLL1DIVR register  ***************/\r\n#define RCC_PLL1DIVR_N1_Pos                    (0U)\r\n#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */\r\n#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk\r\n#define RCC_PLL1DIVR_P1_Pos                    (9U)\r\n#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */\r\n#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk\r\n#define RCC_PLL1DIVR_Q1_Pos                    (16U)\r\n#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */\r\n#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk\r\n#define RCC_PLL1DIVR_R1_Pos                    (24U)\r\n#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */\r\n#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk\r\n\r\n/********************  Bit definition for RCC_PLL1FRACR register  ***************/\r\n#define RCC_PLL1FRACR_FRACN1_Pos               (3U)\r\n#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */\r\n#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk\r\n\r\n/********************  Bit definition for RCC_PLL2DIVR register  ***************/\r\n#define RCC_PLL2DIVR_N2_Pos                    (0U)\r\n#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */\r\n#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk\r\n#define RCC_PLL2DIVR_P2_Pos                    (9U)\r\n#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */\r\n#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk\r\n#define RCC_PLL2DIVR_Q2_Pos                    (16U)\r\n#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */\r\n#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk\r\n#define RCC_PLL2DIVR_R2_Pos                    (24U)\r\n#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */\r\n#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk\r\n\r\n/********************  Bit definition for RCC_PLL2FRACR register  ***************/\r\n#define RCC_PLL2FRACR_FRACN2_Pos               (3U)\r\n#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */\r\n#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk\r\n\r\n/********************  Bit definition for RCC_PLL3DIVR register  ***************/\r\n#define RCC_PLL3DIVR_N3_Pos                    (0U)\r\n#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */\r\n#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk\r\n#define RCC_PLL3DIVR_P3_Pos                    (9U)\r\n#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */\r\n#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk\r\n#define RCC_PLL3DIVR_Q3_Pos                    (16U)\r\n#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */\r\n#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk\r\n#define RCC_PLL3DIVR_R3_Pos                    (24U)\r\n#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */\r\n#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk\r\n\r\n/********************  Bit definition for RCC_PLL3FRACR register  ***************/\r\n#define RCC_PLL3FRACR_FRACN3_Pos               (3U)\r\n#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */\r\n#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk\r\n\r\n/********************  Bit definition for RCC_D1CCIPR register  ***************/\r\n#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)\r\n#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */\r\n#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk\r\n#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D1CCIPR_OCTOSPISEL_Pos             (4U)\r\n#define RCC_D1CCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_D1CCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */\r\n#define RCC_D1CCIPR_OCTOSPISEL                 RCC_D1CCIPR_OCTOSPISEL_Msk\r\n#define RCC_D1CCIPR_OCTOSPISEL_0               (0x1UL << RCC_D1CCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */\r\n#define RCC_D1CCIPR_OCTOSPISEL_1               (0x2UL << RCC_D1CCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */\r\n#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)\r\n#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */\r\n#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk\r\n#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)\r\n#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */\r\n#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk\r\n#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */\r\n\r\n/********************  Bit definition for RCC_D2CCIP1R register  ***************/\r\n#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)\r\n#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */\r\n#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk\r\n#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */\r\n\r\n\r\n#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)\r\n#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */\r\n#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk\r\n#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */\r\n#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */\r\n#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */\r\n\r\n#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)\r\n#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */\r\n#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk\r\n#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */\r\n#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */\r\n#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */\r\n\r\n#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)\r\n#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */\r\n#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk\r\n#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */\r\n#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */\r\n\r\n#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)\r\n#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */\r\n#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk\r\n\r\n#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)\r\n#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */\r\n#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk\r\n#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */\r\n\r\n#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)\r\n#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */\r\n#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk\r\n\r\n/********************  Bit definition for RCC_D2CCIP2R register  ***************/\r\n#define RCC_D2CCIP2R_USART16910SEL_Pos         (3U)\r\n#define RCC_D2CCIP2R_USART16910SEL_Msk         (0x7UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000038 */\r\n#define RCC_D2CCIP2R_USART16910SEL             RCC_D2CCIP2R_USART16910SEL_Msk\r\n#define RCC_D2CCIP2R_USART16910SEL_0           (0x1UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000008 */\r\n#define RCC_D2CCIP2R_USART16910SEL_1           (0x2UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000010 */\r\n#define RCC_D2CCIP2R_USART16910SEL_2           (0x4UL << RCC_D2CCIP2R_USART16910SEL_Pos) /*!< 0x00000020 */\r\n\r\n#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)\r\n#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */\r\n#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk\r\n#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */\r\n\r\n#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)\r\n#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */\r\n#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk\r\n#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */\r\n#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */\r\n\r\n#define RCC_D2CCIP2R_I2C1235SEL_Pos            (12U)\r\n#define RCC_D2CCIP2R_I2C1235SEL_Msk            (0x3UL << RCC_D2CCIP2R_I2C1235SEL_Pos) /*!< 0x00003000 */\r\n#define RCC_D2CCIP2R_I2C1235SEL                RCC_D2CCIP2R_I2C1235SEL_Msk\r\n#define RCC_D2CCIP2R_I2C1235SEL_0              (0x1UL << RCC_D2CCIP2R_I2C1235SEL_Pos) /*!< 0x00001000 */\r\n#define RCC_D2CCIP2R_I2C1235SEL_1              (0x2UL << RCC_D2CCIP2R_I2C1235SEL_Pos) /*!< 0x00002000 */\r\n\r\n#define RCC_D2CCIP2R_USBSEL_Pos                (20U)\r\n#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */\r\n#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk\r\n#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */\r\n#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */\r\n\r\n#define RCC_D2CCIP2R_CECSEL_Pos                (22U)\r\n#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */\r\n#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk\r\n#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */\r\n#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */\r\n\r\n#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)\r\n#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */\r\n#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk\r\n#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */\r\n#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for RCC_D3CCIPR register  ***************/\r\n#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)\r\n#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */\r\n#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk\r\n#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */\r\n\r\n#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)\r\n#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */\r\n#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk\r\n#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */\r\n#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */\r\n\r\n#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)\r\n#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */\r\n#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk\r\n#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */\r\n#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */\r\n#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */\r\n\r\n#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)\r\n#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */\r\n#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk\r\n#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */\r\n#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */\r\n#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */\r\n\r\n#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)\r\n#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */\r\n#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk\r\n#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */\r\n#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */\r\n#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */\r\n\r\n#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)\r\n#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */\r\n#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk\r\n#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */\r\n#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */\r\n#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */\r\n\r\n#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)\r\n#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */\r\n#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk\r\n#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */\r\n#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */\r\n\r\n#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)\r\n#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */\r\n#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk\r\n#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */\r\n#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */\r\n#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */\r\n/********************  Bit definition for RCC_CIER register  ******************/\r\n#define RCC_CIER_LSIRDYIE_Pos                  (0U)\r\n#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */\r\n#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk\r\n#define RCC_CIER_LSERDYIE_Pos                  (1U)\r\n#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */\r\n#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk\r\n#define RCC_CIER_HSIRDYIE_Pos                  (2U)\r\n#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */\r\n#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk\r\n#define RCC_CIER_HSERDYIE_Pos                  (3U)\r\n#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */\r\n#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk\r\n#define RCC_CIER_CSIRDYIE_Pos                  (4U)\r\n#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */\r\n#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk\r\n#define RCC_CIER_HSI48RDYIE_Pos                (5U)\r\n#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */\r\n#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk\r\n#define RCC_CIER_PLL1RDYIE_Pos                 (6U)\r\n#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */\r\n#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk\r\n#define RCC_CIER_PLL2RDYIE_Pos                 (7U)\r\n#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */\r\n#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk\r\n#define RCC_CIER_PLL3RDYIE_Pos                 (8U)\r\n#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */\r\n#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk\r\n#define RCC_CIER_LSECSSIE_Pos                  (9U)\r\n#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */\r\n#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk\r\n\r\n/********************  Bit definition for RCC_CIFR register  ******************/\r\n#define RCC_CIFR_LSIRDYF_Pos                   (0U)\r\n#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */\r\n#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk\r\n#define RCC_CIFR_LSERDYF_Pos                   (1U)\r\n#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */\r\n#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk\r\n#define RCC_CIFR_HSIRDYF_Pos                   (2U)\r\n#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */\r\n#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk\r\n#define RCC_CIFR_HSERDYF_Pos                   (3U)\r\n#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */\r\n#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk\r\n#define RCC_CIFR_CSIRDYF_Pos                   (4U)\r\n#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */\r\n#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk\r\n#define RCC_CIFR_HSI48RDYF_Pos                 (5U)\r\n#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */\r\n#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk\r\n#define RCC_CIFR_PLLRDYF_Pos                   (6U)\r\n#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */\r\n#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk\r\n#define RCC_CIFR_PLL2RDYF_Pos                  (7U)\r\n#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */\r\n#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk\r\n#define RCC_CIFR_PLL3RDYF_Pos                  (8U)\r\n#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */\r\n#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk\r\n#define RCC_CIFR_LSECSSF_Pos                   (9U)\r\n#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */\r\n#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk\r\n#define RCC_CIFR_HSECSSF_Pos                   (10U)\r\n#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */\r\n#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk\r\n\r\n/********************  Bit definition for RCC_CICR register  ******************/\r\n#define RCC_CICR_LSIRDYC_Pos                   (0U)\r\n#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */\r\n#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk\r\n#define RCC_CICR_LSERDYC_Pos                   (1U)\r\n#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */\r\n#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk\r\n#define RCC_CICR_HSIRDYC_Pos                   (2U)\r\n#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */\r\n#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk\r\n#define RCC_CICR_HSERDYC_Pos                   (3U)\r\n#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */\r\n#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk\r\n#define RCC_CICR_CSIRDYC_Pos                   (4U)\r\n#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */\r\n#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk\r\n#define RCC_CICR_HSI48RDYC_Pos                 (5U)\r\n#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */\r\n#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk\r\n#define RCC_CICR_PLLRDYC_Pos                   (6U)\r\n#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */\r\n#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk\r\n#define RCC_CICR_PLL2RDYC_Pos                  (7U)\r\n#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */\r\n#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk\r\n#define RCC_CICR_PLL3RDYC_Pos                  (8U)\r\n#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */\r\n#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk\r\n#define RCC_CICR_LSECSSC_Pos                   (9U)\r\n#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */\r\n#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk\r\n#define RCC_CICR_HSECSSC_Pos                   (10U)\r\n#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */\r\n#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk\r\n\r\n/********************  Bit definition for RCC_BDCR register  ******************/\r\n#define RCC_BDCR_LSEON_Pos                     (0U)\r\n#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */\r\n#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk\r\n#define RCC_BDCR_LSERDY_Pos                    (1U)\r\n#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */\r\n#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk\r\n#define RCC_BDCR_LSEBYP_Pos                    (2U)\r\n#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */\r\n#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk\r\n\r\n#define RCC_BDCR_LSEDRV_Pos                    (3U)\r\n#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */\r\n#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk\r\n#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */\r\n#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */\r\n\r\n#define RCC_BDCR_LSECSSON_Pos                  (5U)\r\n#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */\r\n#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk\r\n#define RCC_BDCR_LSECSSD_Pos                   (6U)\r\n#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */\r\n#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk\r\n\r\n#define RCC_BDCR_RTCSEL_Pos                    (8U)\r\n#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */\r\n#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk\r\n#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */\r\n#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */\r\n\r\n#define RCC_BDCR_RTCEN_Pos                     (15U)\r\n#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */\r\n#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk\r\n#define RCC_BDCR_VSWRST_Pos                    (16U)\r\n#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */\r\n#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk\r\n/* Legacy define */\r\n#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos\r\n#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk\r\n#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST\r\n/********************  Bit definition for RCC_CSR register  *******************/\r\n#define RCC_CSR_LSION_Pos                      (0U)\r\n#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */\r\n#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk\r\n#define RCC_CSR_LSIRDY_Pos                     (1U)\r\n#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */\r\n#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_AHB3ENR register  **************/\r\n#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)\r\n#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */\r\n#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk\r\n#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)\r\n#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */\r\n#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk\r\n#define RCC_AHB3ENR_FMCEN_Pos                  (12U)\r\n#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */\r\n#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk\r\n#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)\r\n#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */\r\n#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk\r\n#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)\r\n#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */\r\n#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk\r\n#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)\r\n#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */\r\n#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk\r\n#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)\r\n#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */\r\n#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk\r\n#define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)\r\n#define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */\r\n#define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk\r\n#define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)\r\n#define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */\r\n#define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\r\n#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)\r\n#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */\r\n#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk\r\n#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)\r\n#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */\r\n#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk\r\n#define RCC_AHB1ENR_ADC12EN_Pos                (5U)\r\n#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */\r\n#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk\r\n#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)\r\n#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */\r\n#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk\r\n#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)\r\n#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */\r\n#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk\r\n#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)\r\n#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */\r\n#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk\r\n#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)\r\n#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */\r\n#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk\r\n#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)\r\n#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */\r\n#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\r\n#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)\r\n#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */\r\n#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk\r\n#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)\r\n#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */\r\n#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk\r\n#define RCC_AHB2ENR_HASHEN_Pos                 (5U)\r\n#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */\r\n#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk\r\n#define RCC_AHB2ENR_RNGEN_Pos                  (6U)\r\n#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */\r\n#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk\r\n#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)\r\n#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */\r\n#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk\r\n#define RCC_AHB2ENR_FMACEN_Pos                 (16U)\r\n#define RCC_AHB2ENR_FMACEN_Msk                 (0x1UL << RCC_AHB2ENR_FMACEN_Pos)          /*!< 0x00010000 */\r\n#define RCC_AHB2ENR_FMACEN                     RCC_AHB2ENR_FMACEN_Msk\r\n#define RCC_AHB2ENR_CORDICEN_Pos               (17U)\r\n#define RCC_AHB2ENR_CORDICEN_Msk               (0x1UL << RCC_AHB2ENR_CORDICEN_Pos)        /*!< 0x00020000 */\r\n#define RCC_AHB2ENR_CORDICEN                   RCC_AHB2ENR_CORDICEN_Msk\r\n#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)\r\n#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */\r\n#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk\r\n#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)\r\n#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */\r\n#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos\r\n#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk\r\n#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN\r\n/* Legacy define */\r\n#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos\r\n#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk\r\n#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN\r\n#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos\r\n#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk\r\n#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN\r\n\r\n/********************  Bit definition for RCC_AHB4ENR register  ******************/\r\n#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)\r\n#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */\r\n#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk\r\n#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)\r\n#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */\r\n#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk\r\n#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)\r\n#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */\r\n#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk\r\n#define RCC_AHB4ENR_GPIODEN_Pos                (3U)\r\n#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */\r\n#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk\r\n#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)\r\n#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */\r\n#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk\r\n#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)\r\n#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */\r\n#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk\r\n#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)\r\n#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */\r\n#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk\r\n#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)\r\n#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */\r\n#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk\r\n#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)\r\n#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */\r\n#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk\r\n#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)\r\n#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */\r\n#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk\r\n#define RCC_AHB4ENR_CRCEN_Pos                  (19U)\r\n#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */\r\n#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk\r\n#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)\r\n#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */\r\n#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk\r\n#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)\r\n#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */\r\n#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk\r\n#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)\r\n#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */\r\n#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk\r\n#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)\r\n#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */\r\n#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB3ENR register  ******************/\r\n#define RCC_APB3ENR_LTDCEN_Pos                 (3U)\r\n#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk\r\n#define RCC_APB3ENR_WWDG1EN_Pos                (6U)\r\n#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk\r\n\r\n/********************  Bit definition for RCC_APB1LENR register  ******************/\r\n\r\n#define RCC_APB1LENR_TIM2EN_Pos                (0U)\r\n#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk\r\n#define RCC_APB1LENR_TIM3EN_Pos                (1U)\r\n#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk\r\n#define RCC_APB1LENR_TIM4EN_Pos                (2U)\r\n#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk\r\n#define RCC_APB1LENR_TIM5EN_Pos                (3U)\r\n#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk\r\n#define RCC_APB1LENR_TIM6EN_Pos                (4U)\r\n#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk\r\n#define RCC_APB1LENR_TIM7EN_Pos                (5U)\r\n#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk\r\n#define RCC_APB1LENR_TIM12EN_Pos               (6U)\r\n#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk\r\n#define RCC_APB1LENR_TIM13EN_Pos               (7U)\r\n#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk\r\n#define RCC_APB1LENR_TIM14EN_Pos               (8U)\r\n#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk\r\n#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)\r\n#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk\r\n\r\n\r\n#define RCC_APB1LENR_SPI2EN_Pos                (14U)\r\n#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk\r\n#define RCC_APB1LENR_SPI3EN_Pos                (15U)\r\n#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk\r\n#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)\r\n#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk\r\n#define RCC_APB1LENR_USART2EN_Pos              (17U)\r\n#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk\r\n#define RCC_APB1LENR_USART3EN_Pos              (18U)\r\n#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk\r\n#define RCC_APB1LENR_UART4EN_Pos               (19U)\r\n#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk\r\n#define RCC_APB1LENR_UART5EN_Pos               (20U)\r\n#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk\r\n#define RCC_APB1LENR_I2C1EN_Pos                (21U)\r\n#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk\r\n#define RCC_APB1LENR_I2C2EN_Pos                (22U)\r\n#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk\r\n#define RCC_APB1LENR_I2C3EN_Pos                (23U)\r\n#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk\r\n#define RCC_APB1LENR_I2C5EN_Pos                (25U)\r\n#define RCC_APB1LENR_I2C5EN_Msk                (0x1UL << RCC_APB1LENR_I2C5EN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LENR_I2C5EN                    RCC_APB1LENR_I2C5EN_Msk\r\n#define RCC_APB1LENR_CECEN_Pos                 (27U)\r\n#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk\r\n#define RCC_APB1LENR_DAC12EN_Pos               (29U)\r\n#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk\r\n#define RCC_APB1LENR_UART7EN_Pos               (30U)\r\n#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk\r\n#define RCC_APB1LENR_UART8EN_Pos               (31U)\r\n#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos\r\n#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk\r\n#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN\r\n/********************  Bit definition for RCC_APB1HENR register  ******************/\r\n#define RCC_APB1HENR_CRSEN_Pos                 (1U)\r\n#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk\r\n#define RCC_APB1HENR_SWPMIEN_Pos               (2U)\r\n#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk\r\n#define RCC_APB1HENR_OPAMPEN_Pos               (4U)\r\n#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk\r\n#define RCC_APB1HENR_MDIOSEN_Pos               (5U)\r\n#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk\r\n#define RCC_APB1HENR_FDCANEN_Pos               (8U)\r\n#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk\r\n#define RCC_APB1HENR_TIM23EN_Pos               (24U)\r\n#define RCC_APB1HENR_TIM23EN_Msk               (0x1UL << RCC_APB1HENR_TIM23EN_Pos) /*!< 0x01000000 */\r\n#define RCC_APB1HENR_TIM23EN                   RCC_APB1HENR_TIM23EN_Msk\r\n#define RCC_APB1HENR_TIM24EN_Pos               (25U)\r\n#define RCC_APB1HENR_TIM24EN_Msk               (0x1UL << RCC_APB1HENR_TIM24EN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1HENR_TIM24EN                   RCC_APB1HENR_TIM24EN_Msk\r\n\r\n/********************  Bit definition for RCC_APB2ENR register  ******************/\r\n#define RCC_APB2ENR_TIM1EN_Pos                 (0U)\r\n#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk\r\n#define RCC_APB2ENR_TIM8EN_Pos                 (1U)\r\n#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk\r\n#define RCC_APB2ENR_USART1EN_Pos               (4U)\r\n#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk\r\n#define RCC_APB2ENR_USART6EN_Pos               (5U)\r\n#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk\r\n#define RCC_APB2ENR_UART9EN_Pos                (6U)\r\n#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk\r\n#define RCC_APB2ENR_USART10EN_Pos              (7U)\r\n#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk\r\n#define RCC_APB2ENR_SPI1EN_Pos                 (12U)\r\n#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk\r\n#define RCC_APB2ENR_SPI4EN_Pos                 (13U)\r\n#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk\r\n#define RCC_APB2ENR_TIM15EN_Pos                (16U)\r\n#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk\r\n#define RCC_APB2ENR_TIM16EN_Pos                (17U)\r\n#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk\r\n#define RCC_APB2ENR_TIM17EN_Pos                (18U)\r\n#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk\r\n#define RCC_APB2ENR_SPI5EN_Pos                 (20U)\r\n#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk\r\n#define RCC_APB2ENR_SAI1EN_Pos                 (22U)\r\n#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk\r\n#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)\r\n#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk\r\n\r\n/********************  Bit definition for RCC_APB4ENR register  ******************/\r\n#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)\r\n#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk\r\n#define RCC_APB4ENR_LPUART1EN_Pos              (3U)\r\n#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk\r\n#define RCC_APB4ENR_SPI6EN_Pos                 (5U)\r\n#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk\r\n#define RCC_APB4ENR_I2C4EN_Pos                 (7U)\r\n#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk\r\n#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)\r\n#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk\r\n#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)\r\n#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */\r\n#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk\r\n#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)\r\n#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */\r\n#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk\r\n#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)\r\n#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk\r\n#define RCC_APB4ENR_COMP12EN_Pos               (14U)\r\n#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk\r\n#define RCC_APB4ENR_VREFEN_Pos                 (15U)\r\n#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk\r\n#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)\r\n#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk\r\n#define RCC_APB4ENR_SAI4EN_Pos                 (21U)\r\n#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk\r\n\r\n#define RCC_APB4ENR_DTSEN_Pos                  (26U)\r\n#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */\r\n#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB3RSTR register  ***************/\r\n#define RCC_AHB3RSTR_MDMARST_Pos               (0U)\r\n#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */\r\n#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk\r\n#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)\r\n#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */\r\n#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk\r\n#define RCC_AHB3RSTR_FMCRST_Pos                (12U)\r\n#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */\r\n#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk\r\n#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)\r\n#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */\r\n#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk\r\n#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)\r\n#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */\r\n#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk\r\n#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)\r\n#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */\r\n#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk\r\n#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)\r\n#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */\r\n#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk\r\n#define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)\r\n#define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */\r\n#define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk\r\n#define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)\r\n#define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */\r\n#define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk\r\n#define RCC_AHB3RSTR_CPURST_Pos                (31U)\r\n#define RCC_AHB3RSTR_CPURST_Msk                (0x1UL << RCC_AHB3RSTR_CPURST_Pos)      /*!< 0x80000000 */\r\n#define RCC_AHB3RSTR_CPURST                    RCC_AHB3RSTR_CPURST_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_AHB1RSTR register  ***************/\r\n#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)\r\n#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */\r\n#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk\r\n#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)\r\n#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */\r\n#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk\r\n#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)\r\n#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */\r\n#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk\r\n#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)\r\n#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */\r\n#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk\r\n#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)\r\n#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */\r\n#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk\r\n\r\n/********************  Bit definition for RCC_AHB2RSTR register  ***************/\r\n#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)\r\n#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */\r\n#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk\r\n#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)\r\n#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */\r\n#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk\r\n#define RCC_AHB2RSTR_HASHRST_Pos               (5U)\r\n#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */\r\n#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk\r\n#define RCC_AHB2RSTR_RNGRST_Pos                (6U)\r\n#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */\r\n#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk\r\n#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)\r\n#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */\r\n#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk\r\n#define RCC_AHB2RSTR_FMACRST_Pos               (16U)\r\n#define RCC_AHB2RSTR_FMACRST_Msk               (0x1UL << RCC_AHB2RSTR_FMACRST_Pos)       /*!< 0x00010000 */\r\n#define RCC_AHB2RSTR_FMACRST                   RCC_AHB2RSTR_FMACRST_Msk\r\n#define RCC_AHB2RSTR_CORDICRST_Pos             (17U)\r\n#define RCC_AHB2RSTR_CORDICRST_Msk             (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos)     /*!< 0x00020000 */\r\n#define RCC_AHB2RSTR_CORDICRST                 RCC_AHB2RSTR_CORDICRST_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos\r\n#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk\r\n#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST\r\n/********************  Bit definition for RCC_AHB4RSTR register  ******************/\r\n#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)\r\n#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */\r\n#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk\r\n#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)\r\n#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */\r\n#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk\r\n#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)\r\n#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */\r\n#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk\r\n#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)\r\n#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */\r\n#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk\r\n#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)\r\n#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */\r\n#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk\r\n#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)\r\n#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */\r\n#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk\r\n#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)\r\n#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */\r\n#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk\r\n#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)\r\n#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */\r\n#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk\r\n#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)\r\n#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */\r\n#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk\r\n#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)\r\n#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */\r\n#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk\r\n#define RCC_AHB4RSTR_CRCRST_Pos                (19U)\r\n#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */\r\n#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk\r\n#define RCC_AHB4RSTR_BDMARST_Pos               (21U)\r\n#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */\r\n#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk\r\n#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)\r\n#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */\r\n#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk\r\n#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)\r\n#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */\r\n#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_APB3RSTR register  ******************/\r\n#define RCC_APB3RSTR_LTDCRST_Pos               (3U)\r\n#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */\r\n#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk\r\n\r\n/********************  Bit definition for RCC_APB1LRSTR register  ******************/\r\n\r\n#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)\r\n#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk\r\n#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)\r\n#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk\r\n#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)\r\n#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk\r\n#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)\r\n#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk\r\n#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)\r\n#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk\r\n#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)\r\n#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk\r\n#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)\r\n#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk\r\n#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)\r\n#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk\r\n#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)\r\n#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk\r\n#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)\r\n#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk\r\n#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)\r\n#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk\r\n#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)\r\n#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk\r\n#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)\r\n#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk\r\n#define RCC_APB1LRSTR_USART2RST_Pos            (17U)\r\n#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk\r\n#define RCC_APB1LRSTR_USART3RST_Pos            (18U)\r\n#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk\r\n#define RCC_APB1LRSTR_UART4RST_Pos             (19U)\r\n#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk\r\n#define RCC_APB1LRSTR_UART5RST_Pos             (20U)\r\n#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk\r\n#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)\r\n#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk\r\n#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)\r\n#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk\r\n#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)\r\n#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk\r\n#define RCC_APB1LRSTR_I2C5RST_Pos              (25U)\r\n#define RCC_APB1LRSTR_I2C5RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C5RST_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LRSTR_I2C5RST                  RCC_APB1LRSTR_I2C5RST_Msk\r\n#define RCC_APB1LRSTR_CECRST_Pos               (27U)\r\n#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk\r\n#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)\r\n#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk\r\n#define RCC_APB1LRSTR_UART7RST_Pos             (30U)\r\n#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk\r\n#define RCC_APB1LRSTR_UART8RST_Pos             (31U)\r\n#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos\r\n#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk\r\n#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST\r\n/********************  Bit definition for RCC_APB1HRSTR register  ******************/\r\n#define RCC_APB1HRSTR_CRSRST_Pos               (1U)\r\n#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk\r\n#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)\r\n#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk\r\n#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)\r\n#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk\r\n#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)\r\n#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk\r\n#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)\r\n#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk\r\n#define RCC_APB1HRSTR_TIM23RST_Pos             (24U)\r\n#define RCC_APB1HRSTR_TIM23RST_Msk             (0x1UL << RCC_APB1HRSTR_TIM23RST_Pos) /*!< 0x01000000 */\r\n#define RCC_APB1HRSTR_TIM23RST                 RCC_APB1HRSTR_TIM23RST_Msk\r\n#define RCC_APB1HRSTR_TIM24RST_Pos             (25U)\r\n#define RCC_APB1HRSTR_TIM24RST_Msk             (0x1UL << RCC_APB1HRSTR_TIM24RST_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1HRSTR_TIM24RST                 RCC_APB1HRSTR_TIM24RST_Msk\r\n\r\n/********************  Bit definition for RCC_APB2RSTR register  ******************/\r\n#define RCC_APB2RSTR_TIM1RST_Pos               (0U)\r\n#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk\r\n#define RCC_APB2RSTR_TIM8RST_Pos               (1U)\r\n#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk\r\n#define RCC_APB2RSTR_USART1RST_Pos             (4U)\r\n#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk\r\n#define RCC_APB2RSTR_USART6RST_Pos             (5U)\r\n#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk\r\n#define RCC_APB2RSTR_UART9RST_Pos              (6U)\r\n#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */\r\n#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk\r\n#define RCC_APB2RSTR_USART10RST_Pos            (7U)\r\n#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk\r\n#define RCC_APB2RSTR_SPI1RST_Pos               (12U)\r\n#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk\r\n#define RCC_APB2RSTR_SPI4RST_Pos               (13U)\r\n#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk\r\n#define RCC_APB2RSTR_TIM15RST_Pos              (16U)\r\n#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk\r\n#define RCC_APB2RSTR_TIM16RST_Pos              (17U)\r\n#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk\r\n#define RCC_APB2RSTR_TIM17RST_Pos              (18U)\r\n#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk\r\n#define RCC_APB2RSTR_SPI5RST_Pos               (20U)\r\n#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk\r\n#define RCC_APB2RSTR_SAI1RST_Pos               (22U)\r\n#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk\r\n#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)\r\n#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */\r\n#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk\r\n\r\n/********************  Bit definition for RCC_APB4RSTR register  ******************/\r\n#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)\r\n#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */\r\n#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk\r\n#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)\r\n#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */\r\n#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk\r\n#define RCC_APB4RSTR_SPI6RST_Pos               (5U)\r\n#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk\r\n#define RCC_APB4RSTR_I2C4RST_Pos               (7U)\r\n#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk\r\n#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)\r\n#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */\r\n#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk\r\n#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)\r\n#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */\r\n#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk\r\n#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)\r\n#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */\r\n#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk\r\n#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)\r\n#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */\r\n#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk\r\n#define RCC_APB4RSTR_COMP12RST_Pos             (14U)\r\n#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */\r\n#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk\r\n#define RCC_APB4RSTR_VREFRST_Pos               (15U)\r\n#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */\r\n#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk\r\n#define RCC_APB4RSTR_SAI4RST_Pos               (21U)\r\n#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */\r\n#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk\r\n\r\n#define RCC_APB4RSTR_DTSRST_Pos                (26U)\r\n#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */\r\n#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk\r\n\r\n/********************  Bit definition for RCC_GCR register  ********************/\r\n#define RCC_GCR_WW1RSC_Pos                     (0U)\r\n#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */\r\n#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk\r\n\r\n/********************  Bit definition for RCC_D3AMR register  ********************/\r\n#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)\r\n#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */\r\n#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk\r\n#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)\r\n#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */\r\n#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk\r\n#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)\r\n#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */\r\n#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk\r\n#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)\r\n#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */\r\n#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk\r\n#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)\r\n#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */\r\n#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk\r\n#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)\r\n#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */\r\n#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk\r\n#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)\r\n#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */\r\n#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk\r\n#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)\r\n#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */\r\n#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk\r\n#define RCC_D3AMR_COMP12AMEN_Pos               (14U)\r\n#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */\r\n#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk\r\n#define RCC_D3AMR_VREFAMEN_Pos                 (15U)\r\n#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */\r\n#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk\r\n#define RCC_D3AMR_RTCAMEN_Pos                  (16U)\r\n#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */\r\n#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk\r\n#define RCC_D3AMR_CRCAMEN_Pos                  (19U)\r\n#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */\r\n#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk\r\n#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)\r\n#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */\r\n#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk\r\n#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)\r\n#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */\r\n#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk\r\n\r\n#define RCC_D3AMR_DTSAMEN_Pos                  (26U)\r\n#define RCC_D3AMR_DTSAMEN_Msk                  (0x1UL << RCC_D3AMR_DTSAMEN_Pos) /*!< 0x04000000 */\r\n#define RCC_D3AMR_DTSAMEN                      RCC_D3AMR_DTSAMEN_Msk\r\n\r\n#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)\r\n#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */\r\n#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk\r\n#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)\r\n#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */\r\n#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk\r\n/********************  Bit definition for RCC_AHB3LPENR register  **************/\r\n#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)\r\n#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */\r\n#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk\r\n#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)\r\n#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */\r\n#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk\r\n#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)\r\n#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */\r\n#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk\r\n#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)\r\n#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */\r\n#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk\r\n#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)\r\n#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */\r\n#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk\r\n#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)\r\n#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */\r\n#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk\r\n#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)\r\n#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */\r\n#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk\r\n#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)\r\n#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */\r\n#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk\r\n#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)\r\n#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */\r\n#define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk\r\n#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)\r\n#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */\r\n#define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk\r\n#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)\r\n#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */\r\n#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk\r\n#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)\r\n#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */\r\n#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk\r\n#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)\r\n#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */\r\n#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk\r\n#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)\r\n#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */\r\n#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk\r\n\r\n\r\n/********************  Bit definition for RCC_AHB1LPENR register  ***************/\r\n#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)\r\n#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk\r\n#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)\r\n#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk\r\n#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)\r\n#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk\r\n#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)\r\n#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk\r\n#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)\r\n#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk\r\n#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)\r\n#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk\r\n#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)\r\n#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */\r\n#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk\r\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)\r\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk\r\n\r\n/********************  Bit definition for RCC_AHB2LPENR register  ***************/\r\n#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)\r\n#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk\r\n#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)\r\n#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk\r\n#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)\r\n#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk\r\n#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)\r\n#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk\r\n#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)\r\n#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk\r\n#define RCC_AHB2LPENR_FMACLPEN_Pos             (16U)\r\n#define RCC_AHB2LPENR_FMACLPEN_Msk             (0x1UL << RCC_AHB2LPENR_FMACLPEN_Pos)     /*!< 0x00010000 */\r\n#define RCC_AHB2LPENR_FMACLPEN                 RCC_AHB2LPENR_FMACLPEN_Msk\r\n#define RCC_AHB2LPENR_CORDICLPEN_Pos           (17U)\r\n#define RCC_AHB2LPENR_CORDICLPEN_Msk           (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos)   /*!< 0x00020000 */\r\n#define RCC_AHB2LPENR_CORDICLPEN               RCC_AHB2LPENR_CORDICLPEN_Msk\r\n#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)\r\n#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk\r\n#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)\r\n#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos\r\n#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk\r\n#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN\r\n#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos\r\n#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk\r\n#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN\r\n#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos\r\n#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk\r\n#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN\r\n\r\n/********************  Bit definition for RCC_AHB4LPENR register  ******************/\r\n#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)\r\n#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)\r\n#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)\r\n#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)\r\n#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)\r\n#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)\r\n#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)\r\n#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)\r\n#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)\r\n#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk\r\n#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)\r\n#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\r\n#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk\r\n#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)\r\n#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */\r\n#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk\r\n#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)\r\n#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk\r\n#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)\r\n#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */\r\n#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk\r\n#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)\r\n#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */\r\n#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk\r\n#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)\r\n#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos\r\n#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk\r\n#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN\r\n/********************  Bit definition for RCC_APB3LPENR register  ******************/\r\n#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)\r\n#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk\r\n#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)\r\n#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB1LLPENR register  ******************/\r\n\r\n#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)\r\n#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)\r\n#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)\r\n#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)\r\n#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)\r\n#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)\r\n#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)\r\n#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)\r\n#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk\r\n#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)\r\n#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk\r\n#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)\r\n#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk\r\n\r\n\r\n#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)\r\n#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk\r\n#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)\r\n#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk\r\n#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)\r\n#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk\r\n#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)\r\n#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk\r\n#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)\r\n#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk\r\n#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)\r\n#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk\r\n#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)\r\n#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)\r\n#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)\r\n#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)\r\n#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk\r\n#define RCC_APB1LLPENR_I2C5LPEN_Pos            (25U)\r\n#define RCC_APB1LLPENR_I2C5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C5LPEN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LLPENR_I2C5LPEN                RCC_APB1LLPENR_I2C5LPEN_Msk\r\n#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)\r\n#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk\r\n#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)\r\n#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk\r\n#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)\r\n#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk\r\n#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)\r\n#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk\r\n\r\n/* Legacy define */\r\n#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos\r\n#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk\r\n#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN\r\n/********************  Bit definition for RCC_APB1HLPENR register  ******************/\r\n#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)\r\n#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk\r\n#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)\r\n#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk\r\n#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)\r\n#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk\r\n#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)\r\n#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk\r\n#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)\r\n#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk\r\n#define RCC_APB1HLPENR_TIM23LPEN_Pos           (24U)\r\n#define RCC_APB1HLPENR_TIM23LPEN_Msk           (0x1UL << RCC_APB1HLPENR_TIM23LPEN_Pos)   /*!< 0x01000000 */\r\n#define RCC_APB1HLPENR_TIM23LPEN                RCC_APB1HLPENR_TIM23LPEN_Msk\r\n#define RCC_APB1HLPENR_TIM24LPEN_Pos           (25U)\r\n#define RCC_APB1HLPENR_TIM24LPEN_Msk           (0x1UL << RCC_APB1HLPENR_TIM24LPEN_Pos)   /*!< 0x02000000 */\r\n#define RCC_APB1HLPENR_TIM24LPEN                RCC_APB1HLPENR_TIM24LPEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB2LPENR register  ******************/\r\n#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)\r\n#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk\r\n#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)\r\n#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk\r\n#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)\r\n#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk\r\n#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)\r\n#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk\r\n#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)\r\n#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk\r\n#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)\r\n#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk\r\n#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)\r\n#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk\r\n#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)\r\n#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk\r\n#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)\r\n#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk\r\n#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)\r\n#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk\r\n#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)\r\n#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk\r\n#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)\r\n#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk\r\n#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)\r\n#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk\r\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)\r\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk\r\n\r\n/********************  Bit definition for RCC_APB4LPENR register  ******************/\r\n#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)\r\n#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk\r\n#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)\r\n#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk\r\n#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)\r\n#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk\r\n#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)\r\n#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)\r\n#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)\r\n#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */\r\n#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)\r\n#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */\r\n#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk\r\n#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)\r\n#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk\r\n#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)\r\n#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk\r\n#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)\r\n#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk\r\n#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)\r\n#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk\r\n#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)\r\n#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk\r\n\r\n#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)\r\n#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk\r\n\r\n/********************  Bit definition for RCC_RSR register  *******************/\r\n#define RCC_RSR_RMVF_Pos                       (16U)\r\n#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */\r\n#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk\r\n#define RCC_RSR_CPURSTF_Pos                    (17U)\r\n#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */\r\n#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk\r\n#define RCC_RSR_D1RSTF_Pos                     (19U)\r\n#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */\r\n#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk\r\n#define RCC_RSR_D2RSTF_Pos                     (20U)\r\n#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */\r\n#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk\r\n#define RCC_RSR_BORRSTF_Pos                    (21U)\r\n#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */\r\n#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk\r\n#define RCC_RSR_PINRSTF_Pos                    (22U)\r\n#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */\r\n#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk\r\n#define RCC_RSR_PORRSTF_Pos                    (23U)\r\n#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */\r\n#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk\r\n#define RCC_RSR_SFTRSTF_Pos                    (24U)\r\n#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */\r\n#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk\r\n#define RCC_RSR_IWDG1RSTF_Pos                  (26U)\r\n#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */\r\n#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk\r\n#define RCC_RSR_WWDG1RSTF_Pos                  (28U)\r\n#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */\r\n#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk\r\n\r\n#define RCC_RSR_LPWRRSTF_Pos                   (30U)\r\n#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */\r\n#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    RNG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/***************************    RNG VER  **************************************/\r\n#define RNG_VER_3_2\r\n/********************  Bits definition for RNG_CR register  *******************/\r\n#define RNG_CR_RNGEN_Pos    (2U)\r\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */\r\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\r\n#define RNG_CR_IE_Pos       (3U)\r\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */\r\n#define RNG_CR_IE           RNG_CR_IE_Msk\r\n#define RNG_CR_CED_Pos      (5U)\r\n#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */\r\n#define RNG_CR_CED          RNG_CR_CED_Msk\r\n#define RNG_CR_RNG_CONFIG3_Pos      (8U)\r\n#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */\r\n#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk\r\n#define RNG_CR_NISTC_Pos            (12U)\r\n#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */\r\n#define RNG_CR_NISTC                RNG_CR_NISTC_Msk\r\n#define RNG_CR_RNG_CONFIG2_Pos      (13U)\r\n#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */\r\n#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk\r\n#define RNG_CR_CLKDIV_Pos           (16U)\r\n#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */\r\n#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk\r\n#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */\r\n#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */\r\n#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */\r\n#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */\r\n#define RNG_CR_RNG_CONFIG1_Pos      (20U)\r\n#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */\r\n#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk\r\n#define RNG_CR_CONDRST_Pos         (30U)\r\n#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */\r\n#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk\r\n#define RNG_CR_CONFIGLOCK_Pos      (31U)\r\n#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */\r\n#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk\r\n\r\n/********************  Bits definition for RNG_SR register  *******************/\r\n#define RNG_SR_DRDY_Pos     (0U)\r\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */\r\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\r\n#define RNG_SR_CECS_Pos     (1U)\r\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */\r\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\r\n#define RNG_SR_SECS_Pos     (2U)\r\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */\r\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\r\n#define RNG_SR_CEIS_Pos     (5U)\r\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */\r\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\r\n#define RNG_SR_SEIS_Pos     (6U)\r\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */\r\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Real-Time Clock (RTC)                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for RTC_TR register  *******************/\r\n#define RTC_TR_PM_Pos                  (22U)\r\n#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */\r\n#define RTC_TR_PM                      RTC_TR_PM_Msk\r\n#define RTC_TR_HT_Pos                  (20U)\r\n#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */\r\n#define RTC_TR_HT                      RTC_TR_HT_Msk\r\n#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */\r\n#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */\r\n#define RTC_TR_HU_Pos                  (16U)\r\n#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */\r\n#define RTC_TR_HU                      RTC_TR_HU_Msk\r\n#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */\r\n#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */\r\n#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */\r\n#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */\r\n#define RTC_TR_MNT_Pos                 (12U)\r\n#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */\r\n#define RTC_TR_MNT                     RTC_TR_MNT_Msk\r\n#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */\r\n#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */\r\n#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */\r\n#define RTC_TR_MNU_Pos                 (8U)\r\n#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */\r\n#define RTC_TR_MNU                     RTC_TR_MNU_Msk\r\n#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */\r\n#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */\r\n#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */\r\n#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */\r\n#define RTC_TR_ST_Pos                  (4U)\r\n#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */\r\n#define RTC_TR_ST                      RTC_TR_ST_Msk\r\n#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */\r\n#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */\r\n#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */\r\n#define RTC_TR_SU_Pos                  (0U)\r\n#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */\r\n#define RTC_TR_SU                      RTC_TR_SU_Msk\r\n#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */\r\n#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */\r\n#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */\r\n#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_DR register  *******************/\r\n#define RTC_DR_YT_Pos                  (20U)\r\n#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */\r\n#define RTC_DR_YT                      RTC_DR_YT_Msk\r\n#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */\r\n#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */\r\n#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */\r\n#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */\r\n#define RTC_DR_YU_Pos                  (16U)\r\n#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */\r\n#define RTC_DR_YU                      RTC_DR_YU_Msk\r\n#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */\r\n#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */\r\n#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */\r\n#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */\r\n#define RTC_DR_WDU_Pos                 (13U)\r\n#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */\r\n#define RTC_DR_WDU                     RTC_DR_WDU_Msk\r\n#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */\r\n#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */\r\n#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */\r\n#define RTC_DR_MT_Pos                  (12U)\r\n#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */\r\n#define RTC_DR_MT                      RTC_DR_MT_Msk\r\n#define RTC_DR_MU_Pos                  (8U)\r\n#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */\r\n#define RTC_DR_MU                      RTC_DR_MU_Msk\r\n#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */\r\n#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */\r\n#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */\r\n#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */\r\n#define RTC_DR_DT_Pos                  (4U)\r\n#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */\r\n#define RTC_DR_DT                      RTC_DR_DT_Msk\r\n#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */\r\n#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */\r\n#define RTC_DR_DU_Pos                  (0U)\r\n#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */\r\n#define RTC_DR_DU                      RTC_DR_DU_Msk\r\n#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */\r\n#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */\r\n#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */\r\n#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_CR register  *******************/\r\n#define RTC_CR_ITSE_Pos                (24U)\r\n#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */\r\n#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk\r\n#define RTC_CR_COE_Pos                 (23U)\r\n#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */\r\n#define RTC_CR_COE                     RTC_CR_COE_Msk\r\n#define RTC_CR_OSEL_Pos                (21U)\r\n#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */\r\n#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk\r\n#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */\r\n#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */\r\n#define RTC_CR_POL_Pos                 (20U)\r\n#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */\r\n#define RTC_CR_POL                     RTC_CR_POL_Msk\r\n#define RTC_CR_COSEL_Pos               (19U)\r\n#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */\r\n#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk\r\n#define RTC_CR_BKP_Pos                 (18U)\r\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */\r\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\r\n#define RTC_CR_SUB1H_Pos               (17U)\r\n#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */\r\n#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk\r\n#define RTC_CR_ADD1H_Pos               (16U)\r\n#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */\r\n#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk\r\n#define RTC_CR_TSIE_Pos                (15U)\r\n#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */\r\n#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk\r\n#define RTC_CR_WUTIE_Pos               (14U)\r\n#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */\r\n#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk\r\n#define RTC_CR_ALRBIE_Pos              (13U)\r\n#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */\r\n#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk\r\n#define RTC_CR_ALRAIE_Pos              (12U)\r\n#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */\r\n#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk\r\n#define RTC_CR_TSE_Pos                 (11U)\r\n#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */\r\n#define RTC_CR_TSE                     RTC_CR_TSE_Msk\r\n#define RTC_CR_WUTE_Pos                (10U)\r\n#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */\r\n#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk\r\n#define RTC_CR_ALRBE_Pos               (9U)\r\n#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */\r\n#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk\r\n#define RTC_CR_ALRAE_Pos               (8U)\r\n#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */\r\n#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk\r\n#define RTC_CR_FMT_Pos                 (6U)\r\n#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */\r\n#define RTC_CR_FMT                     RTC_CR_FMT_Msk\r\n#define RTC_CR_BYPSHAD_Pos             (5U)\r\n#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */\r\n#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk\r\n#define RTC_CR_REFCKON_Pos             (4U)\r\n#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */\r\n#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk\r\n#define RTC_CR_TSEDGE_Pos              (3U)\r\n#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */\r\n#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk\r\n#define RTC_CR_WUCKSEL_Pos             (0U)\r\n#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */\r\n#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk\r\n#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */\r\n#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */\r\n#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */\r\n\r\n/********************  Bits definition for RTC_ISR register  ******************/\r\n#define RTC_ISR_ITSF_Pos               (17U)\r\n#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */\r\n#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk\r\n#define RTC_ISR_RECALPF_Pos            (16U)\r\n#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */\r\n#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk\r\n#define RTC_ISR_TAMP3F_Pos             (15U)\r\n#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */\r\n#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk\r\n#define RTC_ISR_TAMP2F_Pos             (14U)\r\n#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */\r\n#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk\r\n#define RTC_ISR_TAMP1F_Pos             (13U)\r\n#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */\r\n#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk\r\n#define RTC_ISR_TSOVF_Pos              (12U)\r\n#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */\r\n#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk\r\n#define RTC_ISR_TSF_Pos                (11U)\r\n#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */\r\n#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk\r\n#define RTC_ISR_WUTF_Pos               (10U)\r\n#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */\r\n#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk\r\n#define RTC_ISR_ALRBF_Pos              (9U)\r\n#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */\r\n#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk\r\n#define RTC_ISR_ALRAF_Pos              (8U)\r\n#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */\r\n#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk\r\n#define RTC_ISR_INIT_Pos               (7U)\r\n#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */\r\n#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk\r\n#define RTC_ISR_INITF_Pos              (6U)\r\n#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */\r\n#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk\r\n#define RTC_ISR_RSF_Pos                (5U)\r\n#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */\r\n#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk\r\n#define RTC_ISR_INITS_Pos              (4U)\r\n#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */\r\n#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk\r\n#define RTC_ISR_SHPF_Pos               (3U)\r\n#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */\r\n#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk\r\n#define RTC_ISR_WUTWF_Pos              (2U)\r\n#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */\r\n#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk\r\n#define RTC_ISR_ALRBWF_Pos             (1U)\r\n#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */\r\n#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk\r\n#define RTC_ISR_ALRAWF_Pos             (0U)\r\n#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */\r\n#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk\r\n\r\n/********************  Bits definition for RTC_PRER register  *****************/\r\n#define RTC_PRER_PREDIV_A_Pos          (16U)\r\n#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */\r\n#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk\r\n#define RTC_PRER_PREDIV_S_Pos          (0U)\r\n#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */\r\n#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk\r\n\r\n/********************  Bits definition for RTC_WUTR register  *****************/\r\n#define RTC_WUTR_WUT_Pos               (0U)\r\n#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */\r\n#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk\r\n\r\n/********************  Bits definition for RTC_ALRMAR register  ***************/\r\n#define RTC_ALRMAR_MSK4_Pos            (31U)\r\n#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */\r\n#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk\r\n#define RTC_ALRMAR_WDSEL_Pos           (30U)\r\n#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */\r\n#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk\r\n#define RTC_ALRMAR_DT_Pos              (28U)\r\n#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */\r\n#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk\r\n#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */\r\n#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */\r\n#define RTC_ALRMAR_DU_Pos              (24U)\r\n#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */\r\n#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk\r\n#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */\r\n#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */\r\n#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */\r\n#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */\r\n#define RTC_ALRMAR_MSK3_Pos            (23U)\r\n#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */\r\n#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk\r\n#define RTC_ALRMAR_PM_Pos              (22U)\r\n#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */\r\n#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk\r\n#define RTC_ALRMAR_HT_Pos              (20U)\r\n#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */\r\n#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk\r\n#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */\r\n#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */\r\n#define RTC_ALRMAR_HU_Pos              (16U)\r\n#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */\r\n#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk\r\n#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */\r\n#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */\r\n#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */\r\n#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */\r\n#define RTC_ALRMAR_MSK2_Pos            (15U)\r\n#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */\r\n#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk\r\n#define RTC_ALRMAR_MNT_Pos             (12U)\r\n#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */\r\n#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk\r\n#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */\r\n#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */\r\n#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */\r\n#define RTC_ALRMAR_MNU_Pos             (8U)\r\n#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */\r\n#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk\r\n#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */\r\n#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */\r\n#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */\r\n#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */\r\n#define RTC_ALRMAR_MSK1_Pos            (7U)\r\n#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */\r\n#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk\r\n#define RTC_ALRMAR_ST_Pos              (4U)\r\n#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */\r\n#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk\r\n#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */\r\n#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */\r\n#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */\r\n#define RTC_ALRMAR_SU_Pos              (0U)\r\n#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */\r\n#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk\r\n#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */\r\n#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */\r\n#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */\r\n#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_ALRMBR register  ***************/\r\n#define RTC_ALRMBR_MSK4_Pos            (31U)\r\n#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */\r\n#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk\r\n#define RTC_ALRMBR_WDSEL_Pos           (30U)\r\n#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */\r\n#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk\r\n#define RTC_ALRMBR_DT_Pos              (28U)\r\n#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */\r\n#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk\r\n#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */\r\n#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */\r\n#define RTC_ALRMBR_DU_Pos              (24U)\r\n#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */\r\n#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk\r\n#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */\r\n#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */\r\n#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */\r\n#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */\r\n#define RTC_ALRMBR_MSK3_Pos            (23U)\r\n#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */\r\n#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk\r\n#define RTC_ALRMBR_PM_Pos              (22U)\r\n#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */\r\n#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk\r\n#define RTC_ALRMBR_HT_Pos              (20U)\r\n#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */\r\n#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk\r\n#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */\r\n#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */\r\n#define RTC_ALRMBR_HU_Pos              (16U)\r\n#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */\r\n#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk\r\n#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */\r\n#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */\r\n#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */\r\n#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */\r\n#define RTC_ALRMBR_MSK2_Pos            (15U)\r\n#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */\r\n#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk\r\n#define RTC_ALRMBR_MNT_Pos             (12U)\r\n#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */\r\n#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk\r\n#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */\r\n#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */\r\n#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */\r\n#define RTC_ALRMBR_MNU_Pos             (8U)\r\n#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */\r\n#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk\r\n#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */\r\n#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */\r\n#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */\r\n#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */\r\n#define RTC_ALRMBR_MSK1_Pos            (7U)\r\n#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */\r\n#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk\r\n#define RTC_ALRMBR_ST_Pos              (4U)\r\n#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */\r\n#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk\r\n#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */\r\n#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */\r\n#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */\r\n#define RTC_ALRMBR_SU_Pos              (0U)\r\n#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */\r\n#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk\r\n#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */\r\n#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */\r\n#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */\r\n#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_WPR register  ******************/\r\n#define RTC_WPR_KEY_Pos                (0U)\r\n#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */\r\n#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk\r\n\r\n/********************  Bits definition for RTC_SSR register  ******************/\r\n#define RTC_SSR_SS_Pos                 (0U)\r\n#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */\r\n#define RTC_SSR_SS                     RTC_SSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_SHIFTR register  ***************/\r\n#define RTC_SHIFTR_SUBFS_Pos           (0U)\r\n#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */\r\n#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk\r\n#define RTC_SHIFTR_ADD1S_Pos           (31U)\r\n#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */\r\n#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk\r\n\r\n/********************  Bits definition for RTC_TSTR register  *****************/\r\n#define RTC_TSTR_PM_Pos                (22U)\r\n#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */\r\n#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk\r\n#define RTC_TSTR_HT_Pos                (20U)\r\n#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */\r\n#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk\r\n#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */\r\n#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */\r\n#define RTC_TSTR_HU_Pos                (16U)\r\n#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */\r\n#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk\r\n#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */\r\n#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */\r\n#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */\r\n#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */\r\n#define RTC_TSTR_MNT_Pos               (12U)\r\n#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */\r\n#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk\r\n#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */\r\n#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */\r\n#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */\r\n#define RTC_TSTR_MNU_Pos               (8U)\r\n#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */\r\n#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk\r\n#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */\r\n#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */\r\n#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */\r\n#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */\r\n#define RTC_TSTR_ST_Pos                (4U)\r\n#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */\r\n#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk\r\n#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */\r\n#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */\r\n#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */\r\n#define RTC_TSTR_SU_Pos                (0U)\r\n#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */\r\n#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk\r\n#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */\r\n#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */\r\n#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */\r\n#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_TSDR register  *****************/\r\n#define RTC_TSDR_WDU_Pos               (13U)\r\n#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */\r\n#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk\r\n#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */\r\n#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */\r\n#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */\r\n#define RTC_TSDR_MT_Pos                (12U)\r\n#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */\r\n#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk\r\n#define RTC_TSDR_MU_Pos                (8U)\r\n#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */\r\n#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk\r\n#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */\r\n#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */\r\n#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */\r\n#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */\r\n#define RTC_TSDR_DT_Pos                (4U)\r\n#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */\r\n#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk\r\n#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */\r\n#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */\r\n#define RTC_TSDR_DU_Pos                (0U)\r\n#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */\r\n#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk\r\n#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */\r\n#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */\r\n#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */\r\n#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_TSSSR register  ****************/\r\n#define RTC_TSSSR_SS_Pos               (0U)\r\n#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */\r\n#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_CALR register  *****************/\r\n#define RTC_CALR_CALP_Pos              (15U)\r\n#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */\r\n#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk\r\n#define RTC_CALR_CALW8_Pos             (14U)\r\n#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */\r\n#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk\r\n#define RTC_CALR_CALW16_Pos            (13U)\r\n#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */\r\n#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk\r\n#define RTC_CALR_CALM_Pos              (0U)\r\n#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */\r\n#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk\r\n#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */\r\n#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */\r\n#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */\r\n#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */\r\n#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */\r\n#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */\r\n#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */\r\n#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */\r\n#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */\r\n\r\n/********************  Bits definition for RTC_TAMPCR register  ***************/\r\n#define RTC_TAMPCR_TAMP3MF_Pos         (24U)\r\n#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */\r\n#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk\r\n#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)\r\n#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */\r\n#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk\r\n#define RTC_TAMPCR_TAMP3IE_Pos         (22U)\r\n#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */\r\n#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk\r\n#define RTC_TAMPCR_TAMP2MF_Pos         (21U)\r\n#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */\r\n#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk\r\n#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)\r\n#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */\r\n#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk\r\n#define RTC_TAMPCR_TAMP2IE_Pos         (19U)\r\n#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */\r\n#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk\r\n#define RTC_TAMPCR_TAMP1MF_Pos         (18U)\r\n#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */\r\n#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk\r\n#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)\r\n#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */\r\n#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk\r\n#define RTC_TAMPCR_TAMP1IE_Pos         (16U)\r\n#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */\r\n#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk\r\n#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)\r\n#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */\r\n#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk\r\n#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)\r\n#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */\r\n#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk\r\n#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */\r\n#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */\r\n#define RTC_TAMPCR_TAMPFLT_Pos         (11U)\r\n#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */\r\n#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk\r\n#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */\r\n#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */\r\n#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)\r\n#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */\r\n#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk\r\n#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */\r\n#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */\r\n#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */\r\n#define RTC_TAMPCR_TAMPTS_Pos          (7U)\r\n#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */\r\n#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk\r\n#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)\r\n#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */\r\n#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk\r\n#define RTC_TAMPCR_TAMP3E_Pos          (5U)\r\n#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */\r\n#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk\r\n#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)\r\n#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */\r\n#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk\r\n#define RTC_TAMPCR_TAMP2E_Pos          (3U)\r\n#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */\r\n#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk\r\n#define RTC_TAMPCR_TAMPIE_Pos          (2U)\r\n#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */\r\n#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk\r\n#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)\r\n#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */\r\n#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk\r\n#define RTC_TAMPCR_TAMP1E_Pos          (0U)\r\n#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */\r\n#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk\r\n\r\n/********************  Bits definition for RTC_ALRMASSR register  *************/\r\n#define RTC_ALRMASSR_MASKSS_Pos        (24U)\r\n#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */\r\n#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk\r\n#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */\r\n#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */\r\n#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */\r\n#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */\r\n#define RTC_ALRMASSR_SS_Pos            (0U)\r\n#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */\r\n#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\r\n#define RTC_ALRMBSSR_MASKSS_Pos        (24U)\r\n#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */\r\n#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk\r\n#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */\r\n#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */\r\n#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */\r\n#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */\r\n#define RTC_ALRMBSSR_SS_Pos            (0U)\r\n#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */\r\n#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk\r\n\r\n/********************  Bits definition for RTC_OR register  *******************/\r\n#define RTC_OR_OUT_RMP_Pos             (1U)\r\n#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */\r\n#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk\r\n#define RTC_OR_ALARMOUTTYPE_Pos        (0U)\r\n#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */\r\n#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\r\n\r\n/********************  Bits definition for RTC_BKP0R register  ****************/\r\n#define RTC_BKP0R_Pos                  (0U)\r\n#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP0R                      RTC_BKP0R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP1R register  ****************/\r\n#define RTC_BKP1R_Pos                  (0U)\r\n#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP1R                      RTC_BKP1R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP2R register  ****************/\r\n#define RTC_BKP2R_Pos                  (0U)\r\n#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP2R                      RTC_BKP2R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP3R register  ****************/\r\n#define RTC_BKP3R_Pos                  (0U)\r\n#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP3R                      RTC_BKP3R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP4R register  ****************/\r\n#define RTC_BKP4R_Pos                  (0U)\r\n#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP4R                      RTC_BKP4R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP5R register  ****************/\r\n#define RTC_BKP5R_Pos                  (0U)\r\n#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP5R                      RTC_BKP5R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP6R register  ****************/\r\n#define RTC_BKP6R_Pos                  (0U)\r\n#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP6R                      RTC_BKP6R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP7R register  ****************/\r\n#define RTC_BKP7R_Pos                  (0U)\r\n#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP7R                      RTC_BKP7R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP8R register  ****************/\r\n#define RTC_BKP8R_Pos                  (0U)\r\n#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP8R                      RTC_BKP8R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP9R register  ****************/\r\n#define RTC_BKP9R_Pos                  (0U)\r\n#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP9R                      RTC_BKP9R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP10R register  ***************/\r\n#define RTC_BKP10R_Pos                 (0U)\r\n#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP10R                     RTC_BKP10R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP11R register  ***************/\r\n#define RTC_BKP11R_Pos                 (0U)\r\n#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP11R                     RTC_BKP11R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP12R register  ***************/\r\n#define RTC_BKP12R_Pos                 (0U)\r\n#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP12R                     RTC_BKP12R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP13R register  ***************/\r\n#define RTC_BKP13R_Pos                 (0U)\r\n#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP13R                     RTC_BKP13R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP14R register  ***************/\r\n#define RTC_BKP14R_Pos                 (0U)\r\n#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP14R                     RTC_BKP14R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP15R register  ***************/\r\n#define RTC_BKP15R_Pos                 (0U)\r\n#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP15R                     RTC_BKP15R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP16R register  ***************/\r\n#define RTC_BKP16R_Pos                 (0U)\r\n#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP16R                     RTC_BKP16R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP17R register  ***************/\r\n#define RTC_BKP17R_Pos                 (0U)\r\n#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP17R                     RTC_BKP17R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP18R register  ***************/\r\n#define RTC_BKP18R_Pos                 (0U)\r\n#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP18R                     RTC_BKP18R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP19R register  ***************/\r\n#define RTC_BKP19R_Pos                 (0U)\r\n#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP19R                     RTC_BKP19R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP20R register  ***************/\r\n#define RTC_BKP20R_Pos                 (0U)\r\n#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP20R                     RTC_BKP20R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP21R register  ***************/\r\n#define RTC_BKP21R_Pos                 (0U)\r\n#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP21R                     RTC_BKP21R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP22R register  ***************/\r\n#define RTC_BKP22R_Pos                 (0U)\r\n#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP22R                     RTC_BKP22R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP23R register  ***************/\r\n#define RTC_BKP23R_Pos                 (0U)\r\n#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP23R                     RTC_BKP23R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP24R register  ***************/\r\n#define RTC_BKP24R_Pos                 (0U)\r\n#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP24R                     RTC_BKP24R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP25R register  ***************/\r\n#define RTC_BKP25R_Pos                 (0U)\r\n#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP25R                     RTC_BKP25R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP26R register  ***************/\r\n#define RTC_BKP26R_Pos                 (0U)\r\n#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP26R                     RTC_BKP26R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP27R register  ***************/\r\n#define RTC_BKP27R_Pos                 (0U)\r\n#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP27R                     RTC_BKP27R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP28R register  ***************/\r\n#define RTC_BKP28R_Pos                 (0U)\r\n#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP28R                     RTC_BKP28R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP29R register  ***************/\r\n#define RTC_BKP29R_Pos                 (0U)\r\n#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP29R                     RTC_BKP29R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP30R register  ***************/\r\n#define RTC_BKP30R_Pos                 (0U)\r\n#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP30R                     RTC_BKP30R_Msk\r\n\r\n/********************  Bits definition for RTC_BKP31R register  ***************/\r\n#define RTC_BKP31R_Pos                 (0U)\r\n#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */\r\n#define RTC_BKP31R                     RTC_BKP31R_Msk\r\n\r\n/******************** Number of backup registers ******************************/\r\n#define RTC_BKP_NUMBER_Pos             (5U)\r\n#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */\r\n#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                              SPDIF-RX Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for SPDIF_CR register  ******************/\r\n#define SPDIFRX_CR_SPDIFEN_Pos      (0U)\r\n#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */\r\n#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */\r\n#define SPDIFRX_CR_RXDMAEN_Pos      (2U)\r\n#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */\r\n#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */\r\n#define SPDIFRX_CR_RXSTEO_Pos       (3U)\r\n#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */\r\n#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */\r\n#define SPDIFRX_CR_DRFMT_Pos        (4U)\r\n#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */\r\n#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */\r\n#define SPDIFRX_CR_PMSK_Pos         (6U)\r\n#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */\r\n#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */\r\n#define SPDIFRX_CR_VMSK_Pos         (7U)\r\n#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */\r\n#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */\r\n#define SPDIFRX_CR_CUMSK_Pos        (8U)\r\n#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */\r\n#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */\r\n#define SPDIFRX_CR_PTMSK_Pos        (9U)\r\n#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */\r\n#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */\r\n#define SPDIFRX_CR_CBDMAEN_Pos      (10U)\r\n#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */\r\n#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */\r\n#define SPDIFRX_CR_CHSEL_Pos        (11U)\r\n#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */\r\n#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */\r\n#define SPDIFRX_CR_NBTR_Pos         (12U)\r\n#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */\r\n#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */\r\n#define SPDIFRX_CR_WFA_Pos          (14U)\r\n#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */\r\n#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */\r\n#define SPDIFRX_CR_INSEL_Pos        (16U)\r\n#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */\r\n#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */\r\n#define SPDIFRX_CR_CKSEN_Pos        (20U)\r\n#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */\r\n#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */\r\n#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)\r\n#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */\r\n#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */\r\n\r\n/*******************  Bit definition for SPDIFRX_IMR register  *******************/\r\n#define SPDIFRX_IMR_RXNEIE_Pos      (0U)\r\n#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */\r\n#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */\r\n#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)\r\n#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */\r\n#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */\r\n#define SPDIFRX_IMR_PERRIE_Pos      (2U)\r\n#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */\r\n#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */\r\n#define SPDIFRX_IMR_OVRIE_Pos       (3U)\r\n#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */\r\n#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */\r\n#define SPDIFRX_IMR_SBLKIE_Pos      (4U)\r\n#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */\r\n#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */\r\n#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)\r\n#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */\r\n#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */\r\n#define SPDIFRX_IMR_IFEIE_Pos       (6U)\r\n#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */\r\n#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */\r\n\r\n/*******************  Bit definition for SPDIFRX_SR register  *******************/\r\n#define SPDIFRX_SR_RXNE_Pos         (0U)\r\n#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */\r\n#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */\r\n#define SPDIFRX_SR_CSRNE_Pos        (1U)\r\n#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */\r\n#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */\r\n#define SPDIFRX_SR_PERR_Pos         (2U)\r\n#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */\r\n#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */\r\n#define SPDIFRX_SR_OVR_Pos          (3U)\r\n#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */\r\n#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */\r\n#define SPDIFRX_SR_SBD_Pos          (4U)\r\n#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */\r\n#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */\r\n#define SPDIFRX_SR_SYNCD_Pos        (5U)\r\n#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */\r\n#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */\r\n#define SPDIFRX_SR_FERR_Pos         (6U)\r\n#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */\r\n#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */\r\n#define SPDIFRX_SR_SERR_Pos         (7U)\r\n#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */\r\n#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */\r\n#define SPDIFRX_SR_TERR_Pos         (8U)\r\n#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */\r\n#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */\r\n#define SPDIFRX_SR_WIDTH5_Pos       (16U)\r\n#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */\r\n#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */\r\n\r\n/*******************  Bit definition for SPDIFRX_IFCR register  *******************/\r\n#define SPDIFRX_IFCR_PERRCF_Pos     (2U)\r\n#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */\r\n#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */\r\n#define SPDIFRX_IFCR_OVRCF_Pos      (3U)\r\n#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */\r\n#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */\r\n#define SPDIFRX_IFCR_SBDCF_Pos      (4U)\r\n#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */\r\n#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */\r\n#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)\r\n#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */\r\n#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/\r\n#define SPDIFRX_DR0_DR_Pos          (0U)\r\n#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */\r\n#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */\r\n#define SPDIFRX_DR0_PE_Pos          (24U)\r\n#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */\r\n#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */\r\n#define SPDIFRX_DR0_V_Pos           (25U)\r\n#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */\r\n#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */\r\n#define SPDIFRX_DR0_U_Pos           (26U)\r\n#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */\r\n#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */\r\n#define SPDIFRX_DR0_C_Pos           (27U)\r\n#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */\r\n#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */\r\n#define SPDIFRX_DR0_PT_Pos          (28U)\r\n#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */\r\n#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/\r\n#define SPDIFRX_DR1_DR_Pos          (8U)\r\n#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */\r\n#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */\r\n#define SPDIFRX_DR1_PT_Pos          (4U)\r\n#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */\r\n#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */\r\n#define SPDIFRX_DR1_C_Pos           (3U)\r\n#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */\r\n#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */\r\n#define SPDIFRX_DR1_U_Pos           (2U)\r\n#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */\r\n#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */\r\n#define SPDIFRX_DR1_V_Pos           (1U)\r\n#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */\r\n#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */\r\n#define SPDIFRX_DR1_PE_Pos          (0U)\r\n#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */\r\n#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/\r\n#define SPDIFRX_DR1_DRNL1_Pos       (16U)\r\n#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */\r\n#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */\r\n#define SPDIFRX_DR1_DRNL2_Pos       (0U)\r\n#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */\r\n#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */\r\n\r\n/*******************  Bit definition for SPDIFRX_CSR register   *******************/\r\n#define SPDIFRX_CSR_USR_Pos         (0U)\r\n#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */\r\n#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */\r\n#define SPDIFRX_CSR_CS_Pos          (16U)\r\n#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */\r\n#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */\r\n#define SPDIFRX_CSR_SOB_Pos         (24U)\r\n#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */\r\n#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */\r\n\r\n/*******************  Bit definition for SPDIFRX_DIR register    *******************/\r\n#define SPDIFRX_DIR_THI_Pos         (0U)\r\n#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */\r\n#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */\r\n#define SPDIFRX_DIR_TLO_Pos         (16U)\r\n#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */\r\n#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */\r\n\r\n/*******************  Bit definition for SPDIFRX_VERR register    *******************/\r\n#define SPDIFRX_VERR_MINREV_Pos     (0U)\r\n#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */\r\n#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */\r\n#define SPDIFRX_VERR_MAJREV_Pos     (4U)\r\n#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */\r\n#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */\r\n\r\n/*******************  Bit definition for SPDIFRX_IDR register    *******************/\r\n#define SPDIFRX_IDR_ID_Pos          (0U)\r\n#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */\r\n#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */\r\n\r\n/*******************  Bit definition for SPDIFRX_SIDR register    *******************/\r\n#define SPDIFRX_SIDR_SID_Pos        (0U)\r\n#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */\r\n#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Serial Audio Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************************  SAI VERSION  ********************************/\r\n#define SAI_VER_V2_1\r\n\r\n/********************  Bit definition for SAI_GCR register  *******************/\r\n#define SAI_GCR_SYNCIN_Pos         (0U)\r\n#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */\r\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r\n#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\r\n#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\r\n\r\n#define SAI_GCR_SYNCOUT_Pos        (4U)\r\n#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */\r\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r\n#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\r\n#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\r\n\r\n/*******************  Bit definition for SAI_xCR1 register  *******************/\r\n#define SAI_xCR1_MODE_Pos          (0U)\r\n#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */\r\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\r\n#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\r\n#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\r\n\r\n#define SAI_xCR1_PRTCFG_Pos        (2U)\r\n#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */\r\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r\n#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\r\n#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\r\n\r\n#define SAI_xCR1_DS_Pos            (5U)\r\n#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */\r\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\r\n#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\r\n#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\r\n#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\r\n\r\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\r\n#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */\r\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\r\n#define SAI_xCR1_CKSTR_Pos         (9U)\r\n#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */\r\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\r\n\r\n#define SAI_xCR1_SYNCEN_Pos        (10U)\r\n#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */\r\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\r\n#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\r\n#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\r\n\r\n#define SAI_xCR1_MONO_Pos          (12U)\r\n#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */\r\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\r\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\r\n#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */\r\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\r\n#define SAI_xCR1_SAIEN_Pos         (16U)\r\n#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */\r\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\r\n#define SAI_xCR1_DMAEN_Pos         (17U)\r\n#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */\r\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\r\n#define SAI_xCR1_NODIV_Pos         (19U)\r\n#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */\r\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\r\n\r\n#define SAI_xCR1_MCKDIV_Pos        (20U)\r\n#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */\r\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */\r\n#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */\r\n#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */\r\n#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */\r\n#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */\r\n#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */\r\n#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */\r\n\r\n#define SAI_xCR1_MCKEN_Pos         (27U)\r\n#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */\r\n#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */\r\n\r\n#define SAI_xCR1_OSR_Pos           (26U)\r\n#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */\r\n#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */\r\n\r\n/* Legacy define */\r\n#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV\r\n\r\n/*******************  Bit definition for SAI_xCR2 register  *******************/\r\n#define SAI_xCR2_FTH_Pos           (0U)\r\n#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */\r\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\r\n#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\r\n#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\r\n#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\r\n\r\n#define SAI_xCR2_FFLUSH_Pos        (3U)\r\n#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */\r\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\r\n#define SAI_xCR2_TRIS_Pos          (4U)\r\n#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */\r\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\r\n#define SAI_xCR2_MUTE_Pos          (5U)\r\n#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */\r\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\r\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\r\n#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */\r\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\r\n\r\n#define SAI_xCR2_MUTECNT_Pos       (7U)\r\n#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */\r\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\r\n#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\r\n#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\r\n#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\r\n#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\r\n#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\r\n#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\r\n\r\n#define SAI_xCR2_CPL_Pos           (13U)\r\n#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */\r\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\r\n\r\n#define SAI_xCR2_COMP_Pos          (14U)\r\n#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */\r\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\r\n#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\r\n#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\r\n\r\n/******************  Bit definition for SAI_xFRCR register  *******************/\r\n#define SAI_xFRCR_FRL_Pos          (0U)\r\n#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */\r\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */\r\n#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\r\n#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\r\n#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\r\n#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\r\n#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\r\n#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\r\n#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\r\n#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\r\n\r\n#define SAI_xFRCR_FSALL_Pos        (8U)\r\n#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */\r\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */\r\n#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\r\n#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\r\n#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\r\n#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\r\n#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\r\n#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\r\n#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\r\n\r\n#define SAI_xFRCR_FSDEF_Pos        (16U)\r\n#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */\r\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */\r\n#define SAI_xFRCR_FSPOL_Pos        (17U)\r\n#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */\r\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\r\n#define SAI_xFRCR_FSOFF_Pos        (18U)\r\n#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */\r\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\r\n\r\n/* Legacy define */\r\n#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL\r\n\r\n/******************  Bit definition for SAI_xSLOTR register  *******************/\r\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\r\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */\r\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */\r\n#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\r\n#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\r\n#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\r\n#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\r\n#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\r\n\r\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\r\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */\r\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\r\n#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\r\n#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\r\n\r\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\r\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */\r\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r\n#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\r\n#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\r\n#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\r\n#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\r\n\r\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\r\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */\r\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\r\n\r\n/*******************  Bit definition for SAI_xIMR register  *******************/\r\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\r\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */\r\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\r\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\r\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */\r\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\r\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\r\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */\r\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\r\n#define SAI_xIMR_FREQIE_Pos        (3U)\r\n#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */\r\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\r\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\r\n#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */\r\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\r\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\r\n#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */\r\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\r\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\r\n#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */\r\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\r\n\r\n/********************  Bit definition for SAI_xSR register  *******************/\r\n#define SAI_xSR_OVRUDR_Pos         (0U)\r\n#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */\r\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\r\n#define SAI_xSR_MUTEDET_Pos        (1U)\r\n#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */\r\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\r\n#define SAI_xSR_WCKCFG_Pos         (2U)\r\n#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */\r\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\r\n#define SAI_xSR_FREQ_Pos           (3U)\r\n#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */\r\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\r\n#define SAI_xSR_CNRDY_Pos          (4U)\r\n#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */\r\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\r\n#define SAI_xSR_AFSDET_Pos         (5U)\r\n#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */\r\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\r\n#define SAI_xSR_LFSDET_Pos         (6U)\r\n#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */\r\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\r\n\r\n#define SAI_xSR_FLVL_Pos           (16U)\r\n#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */\r\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\r\n#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\r\n#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\r\n#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\r\n\r\n/******************  Bit definition for SAI_xCLRFR register  ******************/\r\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\r\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */\r\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\r\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\r\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */\r\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\r\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\r\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */\r\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\r\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\r\n#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */\r\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\r\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\r\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */\r\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\r\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\r\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */\r\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\r\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\r\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */\r\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\r\n\r\n/******************  Bit definition for SAI_xDR register  *********************/\r\n#define SAI_xDR_DATA_Pos           (0U)\r\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */\r\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\r\n\r\n/*******************  Bit definition for SAI_PDMCR register  ******************/\r\n#define SAI_PDMCR_PDMEN_Pos        (0U)\r\n#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */\r\n#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */\r\n\r\n#define SAI_PDMCR_MICNBR_Pos       (4U)\r\n#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */\r\n#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */\r\n#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */\r\n#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */\r\n\r\n#define SAI_PDMCR_CKEN1_Pos        (8U)\r\n#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */\r\n#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */\r\n#define SAI_PDMCR_CKEN2_Pos        (9U)\r\n#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */\r\n#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */\r\n#define SAI_PDMCR_CKEN3_Pos        (10U)\r\n#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */\r\n#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */\r\n#define SAI_PDMCR_CKEN4_Pos        (11U)\r\n#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */\r\n#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */\r\n\r\n/******************  Bit definition for SAI_PDMDLY register  ******************/\r\n#define SAI_PDMDLY_DLYM1L_Pos      (0U)\r\n#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */\r\n#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */\r\n#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */\r\n#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */\r\n#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */\r\n\r\n#define SAI_PDMDLY_DLYM1R_Pos      (4U)\r\n#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */\r\n#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */\r\n#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */\r\n#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */\r\n#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */\r\n\r\n#define SAI_PDMDLY_DLYM2L_Pos      (8U)\r\n#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */\r\n#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */\r\n#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */\r\n#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */\r\n#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */\r\n\r\n#define SAI_PDMDLY_DLYM2R_Pos      (12U)\r\n#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */\r\n#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/\r\n#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */\r\n#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */\r\n#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */\r\n\r\n#define SAI_PDMDLY_DLYM3L_Pos      (16U)\r\n#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */\r\n#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/\r\n#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */\r\n#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */\r\n#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */\r\n\r\n#define SAI_PDMDLY_DLYM3R_Pos      (20U)\r\n#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */\r\n#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/\r\n#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */\r\n#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */\r\n#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */\r\n\r\n#define SAI_PDMDLY_DLYM4L_Pos      (24U)\r\n#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */\r\n#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/\r\n#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */\r\n#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */\r\n#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */\r\n\r\n#define SAI_PDMDLY_DLYM4R_Pos      (28U)\r\n#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */\r\n#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/\r\n#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */\r\n#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */\r\n#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           SDMMC Interface                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for SDMMC_POWER register  ******************/\r\n#define SDMMC_POWER_PWRCTRL_Pos          (0U)\r\n#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */\r\n#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r\n#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */\r\n#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */\r\n#define SDMMC_POWER_VSWITCH_Pos          (2U)\r\n#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */\r\n#define SDMMC_POWER_VSWITCHEN_Pos        (3U)\r\n#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */\r\n#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */\r\n#define SDMMC_POWER_DIRPOL_Pos           (4U)\r\n#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */\r\n#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */\r\n\r\n/******************  Bit definition for SDMMC_CLKCR register  ******************/\r\n#define SDMMC_CLKCR_CLKDIV_Pos           (0U)\r\n#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */\r\n#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */\r\n#define SDMMC_CLKCR_PWRSAV_Pos           (12U)\r\n#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */\r\n#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */\r\n\r\n#define SDMMC_CLKCR_WIDBUS_Pos           (14U)\r\n#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */\r\n#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r\n#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */\r\n#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */\r\n\r\n#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)\r\n#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */\r\n#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */\r\n#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)\r\n#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */\r\n#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */\r\n#define SDMMC_CLKCR_DDR_Pos              (18U)\r\n#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */\r\n#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */\r\n#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)\r\n#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */\r\n#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */\r\n#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)\r\n#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */\r\n#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */\r\n#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */\r\n#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */\r\n\r\n/*******************  Bit definition for SDMMC_ARG register  *******************/\r\n#define SDMMC_ARG_CMDARG_Pos             (0U)\r\n#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */\r\n\r\n/*******************  Bit definition for SDMMC_CMD register  *******************/\r\n#define SDMMC_CMD_CMDINDEX_Pos           (0U)\r\n#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */\r\n#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */\r\n#define SDMMC_CMD_CMDTRANS_Pos           (6U)\r\n#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */\r\n#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */\r\n#define SDMMC_CMD_CMDSTOP_Pos            (7U)\r\n#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */\r\n#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */\r\n\r\n#define SDMMC_CMD_WAITRESP_Pos           (8U)\r\n#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */\r\n#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */\r\n#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */\r\n#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */\r\n\r\n#define SDMMC_CMD_WAITINT_Pos            (10U)\r\n#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */\r\n#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */\r\n#define SDMMC_CMD_WAITPEND_Pos           (11U)\r\n#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */\r\n#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r\n#define SDMMC_CMD_CPSMEN_Pos             (12U)\r\n#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */\r\n#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */\r\n#define SDMMC_CMD_DTHOLD_Pos             (13U)\r\n#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */\r\n#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */\r\n#define SDMMC_CMD_BOOTMODE_Pos           (14U)\r\n#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */\r\n#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */\r\n#define SDMMC_CMD_BOOTEN_Pos             (15U)\r\n#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */\r\n#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */\r\n#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)\r\n#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */\r\n#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */\r\n\r\n/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\r\n#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)\r\n#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\r\n#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */\r\n\r\n/******************  Bit definition for SDMMC_RESP0 register  ******************/\r\n#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)\r\n#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP1 register  ******************/\r\n#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)\r\n#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP2 register  ******************/\r\n#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)\r\n#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP3 register  ******************/\r\n#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)\r\n#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP4 register  ******************/\r\n#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)\r\n#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_DTIMER register  *****************/\r\n#define SDMMC_DTIMER_DATATIME_Pos        (0U)\r\n#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */\r\n\r\n/******************  Bit definition for SDMMC_DLEN register  *******************/\r\n#define SDMMC_DLEN_DATALENGTH_Pos        (0U)\r\n#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */\r\n\r\n/******************  Bit definition for SDMMC_DCTRL register  ******************/\r\n#define SDMMC_DCTRL_DTEN_Pos             (0U)\r\n#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */\r\n#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */\r\n#define SDMMC_DCTRL_DTDIR_Pos            (1U)\r\n#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */\r\n#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */\r\n#define SDMMC_DCTRL_DTMODE_Pos           (2U)\r\n#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */\r\n#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */\r\n#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */\r\n#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */\r\n\r\n#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)\r\n#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */\r\n\r\n#define SDMMC_DCTRL_RWSTART_Pos          (8U)\r\n#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */\r\n#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */\r\n#define SDMMC_DCTRL_RWSTOP_Pos           (9U)\r\n#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */\r\n#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */\r\n#define SDMMC_DCTRL_RWMOD_Pos            (10U)\r\n#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */\r\n#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */\r\n#define SDMMC_DCTRL_SDIOEN_Pos           (11U)\r\n#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */\r\n#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */\r\n#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)\r\n#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */\r\n#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */\r\n#define SDMMC_DCTRL_FIFORST_Pos          (13U)\r\n#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */\r\n#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */\r\n\r\n/******************  Bit definition for SDMMC_DCOUNT register  *****************/\r\n#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)\r\n#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */\r\n\r\n/******************  Bit definition for SDMMC_STA register  ********************/\r\n#define SDMMC_STA_CCRCFAIL_Pos           (0U)\r\n#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */\r\n#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */\r\n#define SDMMC_STA_DCRCFAIL_Pos           (1U)\r\n#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */\r\n#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */\r\n#define SDMMC_STA_CTIMEOUT_Pos           (2U)\r\n#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */\r\n#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */\r\n#define SDMMC_STA_DTIMEOUT_Pos           (3U)\r\n#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */\r\n#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */\r\n#define SDMMC_STA_TXUNDERR_Pos           (4U)\r\n#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */\r\n#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */\r\n#define SDMMC_STA_RXOVERR_Pos            (5U)\r\n#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */\r\n#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */\r\n#define SDMMC_STA_CMDREND_Pos            (6U)\r\n#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */\r\n#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */\r\n#define SDMMC_STA_CMDSENT_Pos            (7U)\r\n#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */\r\n#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */\r\n#define SDMMC_STA_DATAEND_Pos            (8U)\r\n#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */\r\n#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r\n#define SDMMC_STA_DHOLD_Pos              (9U)\r\n#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */\r\n#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */\r\n#define SDMMC_STA_DBCKEND_Pos            (10U)\r\n#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */\r\n#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */\r\n#define SDMMC_STA_DABORT_Pos             (11U)\r\n#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */\r\n#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */\r\n#define SDMMC_STA_DPSMACT_Pos            (12U)\r\n#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */\r\n#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */\r\n#define SDMMC_STA_CPSMACT_Pos            (13U)\r\n#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */\r\n#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */\r\n#define SDMMC_STA_TXFIFOHE_Pos           (14U)\r\n#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */\r\n#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r\n#define SDMMC_STA_RXFIFOHF_Pos           (15U)\r\n#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */\r\n#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r\n#define SDMMC_STA_TXFIFOF_Pos            (16U)\r\n#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */\r\n#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */\r\n#define SDMMC_STA_RXFIFOF_Pos            (17U)\r\n#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */\r\n#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */\r\n#define SDMMC_STA_TXFIFOE_Pos            (18U)\r\n#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */\r\n#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */\r\n#define SDMMC_STA_RXFIFOE_Pos            (19U)\r\n#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */\r\n#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */\r\n#define SDMMC_STA_BUSYD0_Pos             (20U)\r\n#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */\r\n#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */\r\n#define SDMMC_STA_BUSYD0END_Pos          (21U)\r\n#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */\r\n#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */\r\n#define SDMMC_STA_SDIOIT_Pos             (22U)\r\n#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */\r\n#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */\r\n#define SDMMC_STA_ACKFAIL_Pos            (23U)\r\n#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */\r\n#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */\r\n#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)\r\n#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */\r\n#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */\r\n#define SDMMC_STA_VSWEND_Pos             (25U)\r\n#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */\r\n#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */\r\n#define SDMMC_STA_CKSTOP_Pos             (26U)\r\n#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */\r\n#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */\r\n#define SDMMC_STA_IDMATE_Pos             (27U)\r\n#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */\r\n#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */\r\n#define SDMMC_STA_IDMABTC_Pos            (28U)\r\n#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */\r\n#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */\r\n\r\n/*******************  Bit definition for SDMMC_ICR register  *******************/\r\n#define SDMMC_ICR_CCRCFAILC_Pos          (0U)\r\n#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */\r\n#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */\r\n#define SDMMC_ICR_DCRCFAILC_Pos          (1U)\r\n#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */\r\n#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */\r\n#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)\r\n#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */\r\n#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)\r\n#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */\r\n#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */\r\n#define SDMMC_ICR_TXUNDERRC_Pos          (4U)\r\n#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */\r\n#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */\r\n#define SDMMC_ICR_RXOVERRC_Pos           (5U)\r\n#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */\r\n#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */\r\n#define SDMMC_ICR_CMDRENDC_Pos           (6U)\r\n#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */\r\n#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */\r\n#define SDMMC_ICR_CMDSENTC_Pos           (7U)\r\n#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */\r\n#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */\r\n#define SDMMC_ICR_DATAENDC_Pos           (8U)\r\n#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */\r\n#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */\r\n#define SDMMC_ICR_DHOLDC_Pos             (9U)\r\n#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */\r\n#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */\r\n#define SDMMC_ICR_DBCKENDC_Pos           (10U)\r\n#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */\r\n#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */\r\n#define SDMMC_ICR_DABORTC_Pos            (11U)\r\n#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */\r\n#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */\r\n#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)\r\n#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */\r\n#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */\r\n#define SDMMC_ICR_SDIOITC_Pos            (22U)\r\n#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */\r\n#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */\r\n#define SDMMC_ICR_ACKFAILC_Pos           (23U)\r\n#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */\r\n#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */\r\n#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)\r\n#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */\r\n#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */\r\n#define SDMMC_ICR_VSWENDC_Pos            (25U)\r\n#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */\r\n#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */\r\n#define SDMMC_ICR_CKSTOPC_Pos            (26U)\r\n#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */\r\n#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */\r\n#define SDMMC_ICR_IDMATEC_Pos            (27U)\r\n#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */\r\n#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */\r\n#define SDMMC_ICR_IDMABTCC_Pos           (28U)\r\n#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */\r\n#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */\r\n\r\n/******************  Bit definition for SDMMC_MASK register  *******************/\r\n#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)\r\n#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */\r\n#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */\r\n#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)\r\n#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */\r\n#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */\r\n#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)\r\n#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */\r\n#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */\r\n#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)\r\n#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */\r\n#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */\r\n#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)\r\n#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */\r\n#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r\n#define SDMMC_MASK_RXOVERRIE_Pos         (5U)\r\n#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */\r\n#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */\r\n#define SDMMC_MASK_CMDRENDIE_Pos         (6U)\r\n#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */\r\n#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */\r\n#define SDMMC_MASK_CMDSENTIE_Pos         (7U)\r\n#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */\r\n#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */\r\n#define SDMMC_MASK_DATAENDIE_Pos         (8U)\r\n#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */\r\n#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */\r\n#define SDMMC_MASK_DHOLDIE_Pos           (9U)\r\n#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */\r\n#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */\r\n#define SDMMC_MASK_DBCKENDIE_Pos         (10U)\r\n#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */\r\n#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */\r\n#define SDMMC_MASK_DABORTIE_Pos          (11U)\r\n#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */\r\n#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */\r\n\r\n#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)\r\n#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */\r\n#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */\r\n#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)\r\n#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */\r\n#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */\r\n\r\n#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)\r\n#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */\r\n#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */\r\n#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)\r\n#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */\r\n#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */\r\n\r\n#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)\r\n#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */\r\n#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */\r\n#define SDMMC_MASK_SDIOITIE_Pos           (22U)\r\n#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */\r\n#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */\r\n#define SDMMC_MASK_ACKFAILIE_Pos         (23U)\r\n#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */\r\n#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */\r\n#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)\r\n#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */\r\n#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */\r\n#define SDMMC_MASK_VSWENDIE_Pos          (25U)\r\n#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */\r\n#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */\r\n#define SDMMC_MASK_CKSTOPIE_Pos          (26U)\r\n#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */\r\n#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */\r\n#define SDMMC_MASK_IDMABTCIE_Pos         (28U)\r\n#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */\r\n#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */\r\n\r\n/*****************  Bit definition for SDMMC_ACKTIME register  *****************/\r\n#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)\r\n#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */\r\n\r\n/******************  Bit definition for SDMMC_FIFO register  *******************/\r\n#define SDMMC_FIFO_FIFODATA_Pos          (0U)\r\n#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */\r\n\r\n/******************  Bit definition for SDMMC_IDMACTRL register ****************/\r\n#define SDMMC_IDMA_IDMAEN_Pos            (0U)\r\n#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */\r\n#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */\r\n#define SDMMC_IDMA_IDMABMODE_Pos         (1U)\r\n#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */\r\n#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */\r\n#define SDMMC_IDMA_IDMABACT_Pos          (2U)\r\n#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */\r\n\r\n/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/\r\n#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)\r\n#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */\r\n#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */\r\n\r\n/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/\r\n#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */\r\n\r\n/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/\r\n#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Delay Block Interface (DLYB)                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for DLYB_CR register  ********************/\r\n#define DLYB_CR_DEN_Pos         (0U)\r\n#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */\r\n#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */\r\n#define DLYB_CR_SEN_Pos         (1U)\r\n#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */\r\n#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */\r\n\r\n\r\n/*******************  Bit definition for DLYB_CFGR register  ********************/\r\n#define DLYB_CFGR_SEL_Pos       (0U)\r\n#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */\r\n#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */\r\n#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */\r\n#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */\r\n#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */\r\n#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */\r\n\r\n#define DLYB_CFGR_UNIT_Pos      (8U)\r\n#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */\r\n#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */\r\n#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */\r\n#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */\r\n#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */\r\n#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */\r\n#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */\r\n#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */\r\n#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */\r\n\r\n#define DLYB_CFGR_LNG_Pos       (16U)\r\n#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */\r\n#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */\r\n#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */\r\n#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */\r\n#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */\r\n#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */\r\n#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */\r\n#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */\r\n#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */\r\n#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */\r\n#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */\r\n#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */\r\n#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */\r\n#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */\r\n\r\n#define DLYB_CFGR_LNGF_Pos      (31U)\r\n#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */\r\n#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                   Serial Peripheral Interface (SPI/I2S)                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for SPI_CR1 register  ********************/\r\n#define SPI_CR1_SPE_Pos             (0U)\r\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */\r\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */\r\n#define SPI_CR1_MASRX_Pos           (8U)\r\n#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */\r\n#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */\r\n#define SPI_CR1_CSTART_Pos          (9U)\r\n#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */\r\n#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */\r\n#define SPI_CR1_CSUSP_Pos           (10U)\r\n#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */\r\n#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */\r\n#define SPI_CR1_HDDIR_Pos           (11U)\r\n#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */\r\n#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */\r\n#define SPI_CR1_SSI_Pos             (12U)\r\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */\r\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */\r\n#define SPI_CR1_CRC33_17_Pos        (13U)\r\n#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */\r\n#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */\r\n#define SPI_CR1_RCRCINI_Pos         (14U)\r\n#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */\r\n#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */\r\n#define SPI_CR1_TCRCINI_Pos         (15U)\r\n#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */\r\n#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */\r\n#define SPI_CR1_IOLOCK_Pos          (16U)\r\n#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */\r\n#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */\r\n\r\n/*******************  Bit definition for SPI_CR2 register  ********************/\r\n#define SPI_CR2_TSER_Pos            (16U)\r\n#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */\r\n#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */\r\n#define SPI_CR2_TSIZE_Pos           (0U)\r\n#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */\r\n#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */\r\n\r\n/*******************  Bit definition for SPI_CFG1 register  ********************/\r\n#define SPI_CFG1_DSIZE_Pos          (0U)\r\n#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */\r\n#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */\r\n#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */\r\n#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */\r\n#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */\r\n#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */\r\n#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */\r\n\r\n#define SPI_CFG1_FTHLV_Pos          (5U)\r\n#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */\r\n#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/\r\n#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */\r\n#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */\r\n#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */\r\n#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */\r\n\r\n#define SPI_CFG1_UDRCFG_Pos         (9U)\r\n#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */\r\n#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */\r\n#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */\r\n#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */\r\n\r\n\r\n#define SPI_CFG1_UDRDET_Pos         (11U)\r\n#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */\r\n#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */\r\n#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */\r\n#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */\r\n\r\n#define SPI_CFG1_RXDMAEN_Pos        (14U)\r\n#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */\r\n#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */\r\n#define SPI_CFG1_TXDMAEN_Pos        (15U)\r\n#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */\r\n#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */\r\n\r\n#define SPI_CFG1_CRCSIZE_Pos        (16U)\r\n#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */\r\n#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/\r\n#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */\r\n#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */\r\n#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */\r\n#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */\r\n#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */\r\n\r\n#define SPI_CFG1_CRCEN_Pos          (22U)\r\n#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */\r\n#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */\r\n\r\n#define SPI_CFG1_MBR_Pos            (28U)\r\n#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */\r\n#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */\r\n#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */\r\n#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */\r\n#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */\r\n\r\n/*******************  Bit definition for SPI_CFG2 register  ********************/\r\n#define SPI_CFG2_MSSI_Pos           (0U)\r\n#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */\r\n#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */\r\n#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */\r\n#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */\r\n#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */\r\n#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */\r\n\r\n#define SPI_CFG2_MIDI_Pos           (4U)\r\n#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */\r\n#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */\r\n#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */\r\n#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */\r\n#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */\r\n#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */\r\n\r\n#define SPI_CFG2_IOSWP_Pos          (15U)\r\n#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */\r\n#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */\r\n\r\n#define SPI_CFG2_COMM_Pos           (17U)\r\n#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */\r\n#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/\r\n#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */\r\n#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */\r\n\r\n#define SPI_CFG2_SP_Pos             (19U)\r\n#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */\r\n#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */\r\n#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */\r\n#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */\r\n#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */\r\n\r\n#define SPI_CFG2_MASTER_Pos         (22U)\r\n#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */\r\n#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */\r\n#define SPI_CFG2_LSBFRST_Pos        (23U)\r\n#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */\r\n#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */\r\n#define SPI_CFG2_CPHA_Pos           (24U)\r\n#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */\r\n#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */\r\n#define SPI_CFG2_CPOL_Pos           (25U)\r\n#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */\r\n#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */\r\n#define SPI_CFG2_SSM_Pos            (26U)\r\n#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */\r\n#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */\r\n\r\n#define SPI_CFG2_SSIOP_Pos          (28U)\r\n#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */\r\n#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */\r\n#define SPI_CFG2_SSOE_Pos           (29U)\r\n#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */\r\n#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */\r\n#define SPI_CFG2_SSOM_Pos           (30U)\r\n#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */\r\n#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */\r\n\r\n#define SPI_CFG2_AFCNTR_Pos         (31U)\r\n#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */\r\n#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */\r\n\r\n/*******************  Bit definition for SPI_IER register  ********************/\r\n#define SPI_IER_RXPIE_Pos           (0U)\r\n#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */\r\n#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */\r\n#define SPI_IER_TXPIE_Pos           (1U)\r\n#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */\r\n#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */\r\n#define SPI_IER_DXPIE_Pos           (2U)\r\n#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */\r\n#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */\r\n#define SPI_IER_EOTIE_Pos           (3U)\r\n#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */\r\n#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */\r\n#define SPI_IER_TXTFIE_Pos          (4U)\r\n#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */\r\n#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */\r\n#define SPI_IER_UDRIE_Pos           (5U)\r\n#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */\r\n#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */\r\n#define SPI_IER_OVRIE_Pos           (6U)\r\n#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */\r\n#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */\r\n#define SPI_IER_CRCEIE_Pos          (7U)\r\n#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */\r\n#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */\r\n#define SPI_IER_TIFREIE_Pos         (8U)\r\n#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */\r\n#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */\r\n#define SPI_IER_MODFIE_Pos          (9U)\r\n#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */\r\n#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */\r\n#define SPI_IER_TSERFIE_Pos         (10U)\r\n#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */\r\n#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */\r\n\r\n/*******************  Bit definition for SPI_SR register  ********************/\r\n#define SPI_SR_RXP_Pos              (0U)\r\n#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */\r\n#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */\r\n#define SPI_SR_TXP_Pos              (1U)\r\n#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */\r\n#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */\r\n#define SPI_SR_DXP_Pos              (2U)\r\n#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */\r\n#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */\r\n#define SPI_SR_EOT_Pos              (3U)\r\n#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */\r\n#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */\r\n#define SPI_SR_TXTF_Pos             (4U)\r\n#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */\r\n#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */\r\n#define SPI_SR_UDR_Pos              (5U)\r\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */\r\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */\r\n#define SPI_SR_OVR_Pos              (6U)\r\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */\r\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */\r\n#define SPI_SR_CRCE_Pos             (7U)\r\n#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */\r\n#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */\r\n#define SPI_SR_TIFRE_Pos            (8U)\r\n#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */\r\n#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */\r\n#define SPI_SR_MODF_Pos             (9U)\r\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */\r\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */\r\n#define SPI_SR_TSERF_Pos            (10U)\r\n#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */\r\n#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */\r\n#define SPI_SR_SUSP_Pos             (11U)\r\n#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */\r\n#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */\r\n#define SPI_SR_TXC_Pos              (12U)\r\n#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */\r\n#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */\r\n#define SPI_SR_RXPLVL_Pos           (13U)\r\n#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */\r\n#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */\r\n#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */\r\n#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */\r\n#define SPI_SR_RXWNE_Pos            (15U)\r\n#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */\r\n#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */\r\n#define SPI_SR_CTSIZE_Pos           (16U)\r\n#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */\r\n#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */\r\n\r\n/*******************  Bit definition for SPI_IFCR register  ********************/\r\n#define SPI_IFCR_EOTC_Pos           (3U)\r\n#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */\r\n#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */\r\n#define SPI_IFCR_TXTFC_Pos          (4U)\r\n#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */\r\n#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */\r\n#define SPI_IFCR_UDRC_Pos           (5U)\r\n#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */\r\n#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */\r\n#define SPI_IFCR_OVRC_Pos           (6U)\r\n#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */\r\n#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */\r\n#define SPI_IFCR_CRCEC_Pos          (7U)\r\n#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */\r\n#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */\r\n#define SPI_IFCR_TIFREC_Pos         (8U)\r\n#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */\r\n#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */\r\n#define SPI_IFCR_MODFC_Pos          (9U)\r\n#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */\r\n#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */\r\n#define SPI_IFCR_TSERFC_Pos         (10U)\r\n#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */\r\n#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */\r\n#define SPI_IFCR_SUSPC_Pos          (11U)\r\n#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */\r\n#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */\r\n\r\n/*******************  Bit definition for SPI_TXDR register  ********************/\r\n#define SPI_TXDR_TXDR_Pos           (0U)\r\n#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */\r\n#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */\r\n\r\n/*******************  Bit definition for SPI_RXDR register  ********************/\r\n#define SPI_RXDR_RXDR_Pos           (0U)\r\n#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */\r\n#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */\r\n\r\n/*******************  Bit definition for SPI_CRCPOLY register  ********************/\r\n#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)\r\n#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */\r\n#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */\r\n\r\n/*******************  Bit definition for SPI_TXCRC register  ********************/\r\n#define SPI_TXCRC_TXCRC_Pos         (0U)\r\n#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */\r\n#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */\r\n\r\n/*******************  Bit definition for SPI_RXCRC register  ********************/\r\n#define SPI_RXCRC_RXCRC_Pos         (0U)\r\n#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */\r\n#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */\r\n\r\n/*******************  Bit definition for SPI_UDRDR register  ********************/\r\n#define SPI_UDRDR_UDRDR_Pos         (0U)\r\n#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */\r\n#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */\r\n\r\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\r\n#define SPI_I2SCFGR_I2SMOD_Pos      (0U)\r\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */\r\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\r\n#define SPI_I2SCFGR_I2SCFG_Pos      (1U)\r\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */\r\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */\r\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */\r\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */\r\n#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */\r\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\r\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */\r\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */\r\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\r\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\r\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\r\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */\r\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */\r\n#define SPI_I2SCFGR_DATLEN_Pos      (8U)\r\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */\r\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */\r\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */\r\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */\r\n#define SPI_I2SCFGR_CHLEN_Pos       (10U)\r\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */\r\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\r\n#define SPI_I2SCFGR_CKPOL_Pos       (11U)\r\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */\r\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */\r\n#define SPI_I2SCFGR_FIXCH_Pos       (12U)\r\n#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */\r\n#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */\r\n#define SPI_I2SCFGR_WSINV_Pos       (13U)\r\n#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */\r\n#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */\r\n#define SPI_I2SCFGR_DATFMT_Pos      (14U)\r\n#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */\r\n#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */\r\n#define SPI_I2SCFGR_I2SDIV_Pos      (16U)\r\n#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */\r\n#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */\r\n#define SPI_I2SCFGR_ODD_Pos         (24U)\r\n#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */\r\n#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */\r\n#define SPI_I2SCFGR_MCKOE_Pos       (25U)\r\n#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */\r\n#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */\r\n\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 SYSCFG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/******************  Bit definition for SYSCFG_PMCR register  ******************/\r\n#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)\r\n#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */\r\n#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)\r\n#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */\r\n#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)\r\n#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */\r\n#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)\r\n#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */\r\n#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)\r\n#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */\r\n#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)\r\n#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */\r\n#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)\r\n#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */\r\n#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */\r\n#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)\r\n#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */\r\n#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */\r\n#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)\r\n#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */\r\n#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */\r\n\r\n#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)\r\n#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */\r\n#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */\r\n\r\n#define SYSCFG_PMCR_I2C5_FMP_Pos        (10U)\r\n#define SYSCFG_PMCR_I2C5_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C5_FMP_Pos)    /*!< 0x00000400 */\r\n#define SYSCFG_PMCR_I2C5_FMP            SYSCFG_PMCR_I2C5_FMP_Msk               /*!< I2C5 Fast mode plus */\r\n\r\n#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)\r\n#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */\r\n#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */\r\n#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */\r\n#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */\r\n#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */\r\n#define SYSCFG_PMCR_PA0SO_Pos           (24U)\r\n#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */\r\n#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */\r\n#define SYSCFG_PMCR_PA1SO_Pos           (25U)\r\n#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */\r\n#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */\r\n#define SYSCFG_PMCR_PC2SO_Pos           (26U)\r\n#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */\r\n#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */\r\n#define SYSCFG_PMCR_PC3SO_Pos           (27U)\r\n#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */\r\n#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r\n#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)\r\n#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\r\n#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)\r\n#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\r\n#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)\r\n#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\r\n#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)\r\n#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\r\n/**\r\n  * @brief   EXTI0 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */\r\n\r\n/**\r\n  * @brief   EXTI1 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */\r\n/**\r\n  * @brief   EXTI2 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */\r\n\r\n/**\r\n  * @brief   EXTI3 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r\n#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)\r\n#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\r\n#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)\r\n#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\r\n#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)\r\n#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\r\n#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)\r\n#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\r\n/**\r\n  * @brief   EXTI4 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */\r\n/**\r\n  * @brief   EXTI5 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */\r\n/**\r\n  * @brief   EXTI6 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */\r\n\r\n/**\r\n  * @brief   EXTI7 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r\n#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)\r\n#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\r\n#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)\r\n#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\r\n#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)\r\n#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\r\n#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)\r\n#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\r\n\r\n/**\r\n  * @brief   EXTI8 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */\r\n\r\n/**\r\n  * @brief   EXTI9 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */\r\n\r\n/**\r\n  * @brief   EXTI10 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */\r\n\r\n/**\r\n  * @brief   EXTI11 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r\n#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)\r\n#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\r\n#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)\r\n#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\r\n#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)\r\n#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\r\n#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)\r\n#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\r\n/**\r\n  * @brief   EXTI12 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */\r\n/**\r\n  * @brief   EXTI13 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */\r\n/**\r\n  * @brief   EXTI14 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */\r\n/**\r\n  * @brief   EXTI15 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */\r\n\r\n/******************  Bit definition for SYSCFG_CFGR register  ******************/\r\n#define SYSCFG_CFGR_PVDL_Pos            (2U)\r\n#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */\r\n#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */\r\n#define SYSCFG_CFGR_FLASHL_Pos          (3U)\r\n#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */\r\n#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */\r\n#define SYSCFG_CFGR_CM7L_Pos            (6U)\r\n#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */\r\n#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */\r\n#define SYSCFG_CFGR_BKRAML_Pos          (7U)\r\n#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */\r\n#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */\r\n#define SYSCFG_CFGR_SRAM4L_Pos          (9U)\r\n#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */\r\n#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */\r\n#define SYSCFG_CFGR_SRAM2L_Pos          (11U)\r\n#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */\r\n#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */\r\n#define SYSCFG_CFGR_SRAM1L_Pos          (12U)\r\n#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */\r\n#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */\r\n#define SYSCFG_CFGR_DTCML_Pos           (13U)\r\n#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */\r\n#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */\r\n#define SYSCFG_CFGR_ITCML_Pos           (14U)\r\n#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */\r\n#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */\r\n#define SYSCFG_CFGR_AXISRAML_Pos        (15U)\r\n#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */\r\n#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */\r\n\r\n/******************  Bit definition for SYSCFG_CCCSR register  ******************/\r\n#define SYSCFG_CCCSR_EN_Pos             (0U)\r\n#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */\r\n#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */\r\n#define SYSCFG_CCCSR_CS_Pos             (1U)\r\n#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */\r\n#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */\r\n#define SYSCFG_CCCSR_READY_Pos          (8U)\r\n#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */\r\n#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */\r\n#define SYSCFG_CCCSR_HSLV_Pos           (16U)\r\n#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */\r\n#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */\r\n\r\n/******************  Bit definition for SYSCFG_CCVR register  *******************/\r\n#define SYSCFG_CCVR_NCV_Pos             (0U)\r\n#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */\r\n#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */\r\n#define SYSCFG_CCVR_PCV_Pos             (4U)\r\n#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */\r\n#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */\r\n\r\n/******************  Bit definition for SYSCFG_CCCR register  *******************/\r\n#define SYSCFG_CCCR_NCC_Pos             (0U)\r\n#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */\r\n#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */\r\n#define SYSCFG_CCCR_PCC_Pos             (4U)\r\n#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */\r\n#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */\r\n/******************  Bit definition for SYSCFG_ADC2ALT register  *******************/\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT0_Pos   (0U)\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT0_Msk   (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT0_Pos) /*!< 0x00000001 */\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT0       SYSCFG_ADC2ALT_ADC2_ROUT0_Msk            /*!< VBAT/4 connected to ADC2 V_INP[16] */\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT1_Pos   (1U)\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT1_Msk   (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT1_Pos) /*!< 0x00000002 */\r\n#define SYSCFG_ADC2ALT_ADC2_ROUT1       SYSCFG_ADC2ALT_ADC2_ROUT1_Msk            /*!< Internal reference voltage (V_REFINT) connected to ADC2 V_INP[17] */\r\n\r\n/******************  Bit definition for SYSCFG_PKGR register  *******************/\r\n#define SYSCFG_PKGR_PKG_Pos             (0U)\r\n#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */\r\n#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */\r\n\r\n/******************  Bit definition for SYSCFG_UR0 register  *******************/\r\n#define SYSCFG_UR0_RDP_Pos              (16U)\r\n#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */\r\n#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */\r\n\r\n/******************  Bit definition for SYSCFG_UR2 register  *******************/\r\n#define SYSCFG_UR2_BORH_Pos             (0U)\r\n#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */\r\n#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */\r\n#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */\r\n#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */\r\n#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)\r\n#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */\r\n#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */\r\n/******************  Bit definition for SYSCFG_UR3 register  *******************/\r\n#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)\r\n#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */\r\n#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */\r\n\r\n  /******************  Bit definition for SYSCFG_UR4 register  *******************/\r\n\r\n#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)\r\n#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */\r\n#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */\r\n\r\n/******************  Bit definition for SYSCFG_UR5 register  *******************/\r\n#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)\r\n#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */\r\n#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */\r\n#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)\r\n#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */\r\n#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */\r\n\r\n/******************  Bit definition for SYSCFG_UR6 register  *******************/\r\n#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)\r\n#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */\r\n#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */\r\n#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)\r\n#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */\r\n#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */\r\n\r\n/******************  Bit definition for SYSCFG_UR7 register  *******************/\r\n#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)\r\n#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */\r\n#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */\r\n#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)\r\n#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */\r\n#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */\r\n\r\n\r\n/******************  Bit definition for SYSCFG_UR11 register  *******************/\r\n#define SYSCFG_UR11_IWDG1M_Pos          (16U)\r\n#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */\r\n#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */\r\n\r\n/******************  Bit definition for SYSCFG_UR12 register  *******************/\r\n\r\n#define SYSCFG_UR12_SECURE_Pos          (16U)\r\n#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */\r\n#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */\r\n\r\n/******************  Bit definition for SYSCFG_UR13 register  *******************/\r\n#define SYSCFG_UR13_SDRS_Pos            (0U)\r\n#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */\r\n#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */\r\n#define SYSCFG_UR13_D1SBRST_Pos         (16U)\r\n#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */\r\n#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */\r\n\r\n/******************  Bit definition for SYSCFG_UR14 register  *******************/\r\n#define SYSCFG_UR14_D1STPRST_Pos        (0U)\r\n#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */\r\n#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */\r\n\r\n/******************  Bit definition for SYSCFG_UR15 register  *******************/\r\n#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)\r\n#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */\r\n#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */\r\n\r\n/******************  Bit definition for SYSCFG_UR16 register  *******************/\r\n#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)\r\n#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */\r\n#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */\r\n#define SYSCFG_UR16_PKP_Pos             (16U)\r\n#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */\r\n#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */\r\n\r\n/******************  Bit definition for SYSCFG_UR17 register  *******************/\r\n#define SYSCFG_UR17_IOHSLV_Pos          (0U)\r\n#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */\r\n#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */\r\n#define SYSCFG_UR17_TCM_AXI_CFG_Pos     (16U)\r\n#define SYSCFG_UR17_TCM_AXI_CFG_Msk     (0x3UL << SYSCFG_UR17_TCM_AXI_CFG_Pos) /*!< 0x00030000 */\r\n#define SYSCFG_UR17_TCM_AXI_CFG         SYSCFG_UR17_TCM_AXI_CFG_Msk            /*!< ITCM-RAM / AXI-SRAM size */\r\n\r\n/******************  Bit definition for SYSCFG_UR18 register  *******************/\r\n#define SYSCFG_UR18_CPU_FREQ_BOOST_Pos  (0U)\r\n#define SYSCFG_UR18_CPU_FREQ_BOOST_Msk  (0x1UL << SYSCFG_UR18_CPU_FREQ_BOOST_Pos)  /*!< 0x00000001 */\r\n#define SYSCFG_UR18_CPU_FREQ_BOOST       SYSCFG_UR18_CPU_FREQ_BOOST_Msk            /*!< CPU maximum frequency boost enable */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                    Digital Temperature Sensor (DTS)                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/******************  Bit definition for DTS_CFGR1 register  ******************/\r\n#define DTS_CFGR1_TS1_EN_Pos               (0U)\r\n#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */\r\n#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */\r\n#define DTS_CFGR1_TS1_START_Pos            (4U)\r\n#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */\r\n#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */\r\n#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)\r\n#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */\r\n#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */\r\n#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */\r\n#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)\r\n#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */\r\n#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */\r\n#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)\r\n#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */\r\n#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */\r\n#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)\r\n#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */\r\n#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/\r\n\r\n/******************  Bit definition for DTS_T0VALR1 register  ******************/\r\n#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)\r\n#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */\r\n#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */\r\n#define DTS_T0VALR1_TS1_T0_Pos             (16U)\r\n#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */\r\n#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */\r\n\r\n/******************  Bit definition for DTS_RAMPVALR register  ******************/\r\n#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)\r\n#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */\r\n#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */\r\n\r\n/******************  Bit definition for DTS_ITR1 register      ******************/\r\n#define DTS_ITR1_TS1_LITTHD_Pos            (0U)\r\n#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */\r\n#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */\r\n#define DTS_ITR1_TS1_HITTHD_Pos            (16U)\r\n#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */\r\n#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */\r\n\r\n/******************  Bit definition for DTS_DR register        ******************/\r\n#define DTS_DR_TS1_MFREQ_Pos               (0U)\r\n#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */\r\n#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */\r\n\r\n/******************  Bit definition for DTS_SR register        ******************/\r\n#define DTS_SR_TS1_ITEF_Pos                (0U)\r\n#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */\r\n#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */\r\n#define DTS_SR_TS1_ITLF_Pos                (1U)\r\n#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */\r\n#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */\r\n#define DTS_SR_TS1_ITHF_Pos                (2U)\r\n#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */\r\n#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */\r\n#define DTS_SR_TS1_AITEF_Pos               (4U)\r\n#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */\r\n#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */\r\n#define DTS_SR_TS1_AITLF_Pos               (5U)\r\n#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */\r\n#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */\r\n#define DTS_SR_TS1_AITHF_Pos               (6U)\r\n#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */\r\n#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */\r\n#define DTS_SR_TS1_RDY_Pos                 (15U)\r\n#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */\r\n#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */\r\n\r\n/******************  Bit definition for DTS_ITENR register      ******************/\r\n#define DTS_ITENR_TS1_ITEEN_Pos            (0U)\r\n#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */\r\n#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */\r\n#define DTS_ITENR_TS1_ITLEN_Pos            (1U)\r\n#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */\r\n#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */\r\n#define DTS_ITENR_TS1_ITHEN_Pos            (2U)\r\n#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */\r\n#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */\r\n#define DTS_ITENR_TS1_AITEEN_Pos           (4U)\r\n#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */\r\n#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */\r\n#define DTS_ITENR_TS1_AITLEN_Pos           (5U)\r\n#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */\r\n#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */\r\n#define DTS_ITENR_TS1_AITHEN_Pos           (6U)\r\n#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */\r\n#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */\r\n\r\n/******************  Bit definition for DTS_ICIFR register      ******************/\r\n#define DTS_ICIFR_TS1_CITEF_Pos            (0U)\r\n#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */\r\n#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */\r\n#define DTS_ICIFR_TS1_CITLF_Pos            (1U)\r\n#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */\r\n#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */\r\n#define DTS_ICIFR_TS1_CITHF_Pos            (2U)\r\n#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */\r\n#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */\r\n#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)\r\n#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */\r\n#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */\r\n#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)\r\n#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */\r\n#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */\r\n#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)\r\n#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */\r\n#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    TIM                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */\r\n\r\n/*******************  Bit definition for TIM_CR1 register  ********************/\r\n#define TIM_CR1_CEN_Pos           (0U)\r\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */\r\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\r\n#define TIM_CR1_UDIS_Pos          (1U)\r\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */\r\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\r\n#define TIM_CR1_URS_Pos           (2U)\r\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */\r\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\r\n#define TIM_CR1_OPM_Pos           (3U)\r\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */\r\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\r\n#define TIM_CR1_DIR_Pos           (4U)\r\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */\r\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\r\n\r\n#define TIM_CR1_CMS_Pos           (5U)\r\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */\r\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\r\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */\r\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */\r\n\r\n#define TIM_CR1_ARPE_Pos          (7U)\r\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */\r\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\r\n\r\n#define TIM_CR1_CKD_Pos           (8U)\r\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */\r\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\r\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */\r\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */\r\n\r\n#define TIM_CR1_UIFREMAP_Pos      (11U)\r\n#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */\r\n#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\r\n\r\n/*******************  Bit definition for TIM_CR2 register  ********************/\r\n#define TIM_CR2_CCPC_Pos          (0U)\r\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */\r\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\r\n#define TIM_CR2_CCUS_Pos          (2U)\r\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */\r\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\r\n#define TIM_CR2_CCDS_Pos          (3U)\r\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */\r\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\r\n\r\n#define TIM_CR2_MMS_Pos           (4U)\r\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */\r\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */\r\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */\r\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */\r\n\r\n#define TIM_CR2_TI1S_Pos          (7U)\r\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */\r\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\r\n#define TIM_CR2_OIS1_Pos          (8U)\r\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */\r\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\r\n#define TIM_CR2_OIS1N_Pos         (9U)\r\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */\r\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\r\n#define TIM_CR2_OIS2_Pos          (10U)\r\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */\r\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\r\n#define TIM_CR2_OIS2N_Pos         (11U)\r\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */\r\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\r\n#define TIM_CR2_OIS3_Pos          (12U)\r\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */\r\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\r\n#define TIM_CR2_OIS3N_Pos         (13U)\r\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\r\n#define TIM_CR2_OIS4_Pos          (14U)\r\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */\r\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n#define TIM_CR2_OIS5_Pos          (16U)\r\n#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */\r\n#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n#define TIM_CR2_OIS6_Pos          (17U)\r\n#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */\r\n#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n\r\n#define TIM_CR2_MMS2_Pos          (20U)\r\n#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */\r\n#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */\r\n#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */\r\n#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */\r\n#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */\r\n\r\n/*******************  Bit definition for TIM_SMCR register  *******************/\r\n#define TIM_SMCR_SMS_Pos          (0U)\r\n#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */\r\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\r\n#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */\r\n#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */\r\n#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */\r\n#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */\r\n\r\n#define TIM_SMCR_TS_Pos           (4U)\r\n#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */\r\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */\r\n#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */\r\n#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */\r\n#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */\r\n#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */\r\n#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */\r\n\r\n#define TIM_SMCR_MSM_Pos          (7U)\r\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */\r\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\r\n\r\n#define TIM_SMCR_ETF_Pos          (8U)\r\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */\r\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\r\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */\r\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */\r\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */\r\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */\r\n\r\n#define TIM_SMCR_ETPS_Pos         (12U)\r\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */\r\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\r\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */\r\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */\r\n\r\n#define TIM_SMCR_ECE_Pos          (14U)\r\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */\r\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\r\n#define TIM_SMCR_ETP_Pos          (15U)\r\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */\r\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\r\n\r\n/*******************  Bit definition for TIM_DIER register  *******************/\r\n#define TIM_DIER_UIE_Pos          (0U)\r\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */\r\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\r\n#define TIM_DIER_CC1IE_Pos        (1U)\r\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */\r\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\r\n#define TIM_DIER_CC2IE_Pos        (2U)\r\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */\r\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\r\n#define TIM_DIER_CC3IE_Pos        (3U)\r\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */\r\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\r\n#define TIM_DIER_CC4IE_Pos        (4U)\r\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */\r\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\r\n#define TIM_DIER_COMIE_Pos        (5U)\r\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */\r\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\r\n#define TIM_DIER_TIE_Pos          (6U)\r\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */\r\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\r\n#define TIM_DIER_BIE_Pos          (7U)\r\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */\r\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\r\n#define TIM_DIER_UDE_Pos          (8U)\r\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */\r\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\r\n#define TIM_DIER_CC1DE_Pos        (9U)\r\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */\r\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\r\n#define TIM_DIER_CC2DE_Pos        (10U)\r\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */\r\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\r\n#define TIM_DIER_CC3DE_Pos        (11U)\r\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */\r\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\r\n#define TIM_DIER_CC4DE_Pos        (12U)\r\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */\r\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\r\n#define TIM_DIER_COMDE_Pos        (13U)\r\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */\r\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\r\n#define TIM_DIER_TDE_Pos          (14U)\r\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */\r\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\r\n\r\n/********************  Bit definition for TIM_SR register  ********************/\r\n#define TIM_SR_UIF_Pos            (0U)\r\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */\r\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\r\n#define TIM_SR_CC1IF_Pos          (1U)\r\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */\r\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\r\n#define TIM_SR_CC2IF_Pos          (2U)\r\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */\r\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\r\n#define TIM_SR_CC3IF_Pos          (3U)\r\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */\r\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\r\n#define TIM_SR_CC4IF_Pos          (4U)\r\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */\r\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\r\n#define TIM_SR_COMIF_Pos          (5U)\r\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */\r\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\r\n#define TIM_SR_TIF_Pos            (6U)\r\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */\r\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\r\n#define TIM_SR_BIF_Pos            (7U)\r\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */\r\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\r\n#define TIM_SR_B2IF_Pos           (8U)\r\n#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */\r\n#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */\r\n#define TIM_SR_CC1OF_Pos          (9U)\r\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */\r\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\r\n#define TIM_SR_CC2OF_Pos          (10U)\r\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */\r\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\r\n#define TIM_SR_CC3OF_Pos          (11U)\r\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */\r\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\r\n#define TIM_SR_CC4OF_Pos          (12U)\r\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */\r\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\r\n#define TIM_SR_CC5IF_Pos          (16U)\r\n#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */\r\n#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\r\n#define TIM_SR_CC6IF_Pos          (17U)\r\n#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */\r\n#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\r\n#define TIM_SR_SBIF_Pos           (13U)\r\n#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */\r\n#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */\r\n\r\n/*******************  Bit definition for TIM_EGR register  ********************/\r\n#define TIM_EGR_UG_Pos            (0U)\r\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */\r\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\r\n#define TIM_EGR_CC1G_Pos          (1U)\r\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */\r\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\r\n#define TIM_EGR_CC2G_Pos          (2U)\r\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */\r\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\r\n#define TIM_EGR_CC3G_Pos          (3U)\r\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */\r\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\r\n#define TIM_EGR_CC4G_Pos          (4U)\r\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */\r\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\r\n#define TIM_EGR_COMG_Pos          (5U)\r\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */\r\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\r\n#define TIM_EGR_TG_Pos            (6U)\r\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */\r\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\r\n#define TIM_EGR_BG_Pos            (7U)\r\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */\r\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\r\n#define TIM_EGR_B2G_Pos           (8U)\r\n#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */\r\n#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */\r\n\r\n\r\n/******************  Bit definition for TIM_CCMR1 register  *******************/\r\n#define TIM_CCMR1_CC1S_Pos        (0U)\r\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */\r\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */\r\n\r\n#define TIM_CCMR1_OC1FE_Pos       (2U)\r\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\r\n#define TIM_CCMR1_OC1PE_Pos       (3U)\r\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */\r\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\r\n\r\n#define TIM_CCMR1_OC1M_Pos        (4U)\r\n#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */\r\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r\n#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */\r\n#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */\r\n#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */\r\n#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR1_OC1CE_Pos       (7U)\r\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */\r\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */\r\n\r\n#define TIM_CCMR1_CC2S_Pos        (8U)\r\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */\r\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */\r\n\r\n#define TIM_CCMR1_OC2FE_Pos       (10U)\r\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\r\n#define TIM_CCMR1_OC2PE_Pos       (11U)\r\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */\r\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\r\n\r\n#define TIM_CCMR1_OC2M_Pos        (12U)\r\n#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */\r\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r\n#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */\r\n#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */\r\n#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */\r\n#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */\r\n\r\n#define TIM_CCMR1_OC2CE_Pos       (15U)\r\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */\r\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\r\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */\r\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */\r\n\r\n#define TIM_CCMR1_IC1F_Pos        (4U)\r\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */\r\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */\r\n\r\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\r\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */\r\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */\r\n\r\n#define TIM_CCMR1_IC2F_Pos        (12U)\r\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */\r\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */\r\n\r\n/******************  Bit definition for TIM_CCMR2 register  *******************/\r\n#define TIM_CCMR2_CC3S_Pos        (0U)\r\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */\r\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */\r\n\r\n#define TIM_CCMR2_OC3FE_Pos       (2U)\r\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\r\n#define TIM_CCMR2_OC3PE_Pos       (3U)\r\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */\r\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\r\n\r\n#define TIM_CCMR2_OC3M_Pos        (4U)\r\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */\r\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR2_OC3CE_Pos       (7U)\r\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */\r\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\r\n\r\n#define TIM_CCMR2_CC4S_Pos        (8U)\r\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */\r\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */\r\n\r\n#define TIM_CCMR2_OC4FE_Pos       (10U)\r\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\r\n#define TIM_CCMR2_OC4PE_Pos       (11U)\r\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */\r\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\r\n\r\n#define TIM_CCMR2_OC4M_Pos        (12U)\r\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */\r\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */\r\n\r\n#define TIM_CCMR2_OC4CE_Pos       (15U)\r\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */\r\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\r\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */\r\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */\r\n\r\n#define TIM_CCMR2_IC3F_Pos        (4U)\r\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */\r\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */\r\n\r\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\r\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */\r\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */\r\n\r\n#define TIM_CCMR2_IC4F_Pos        (12U)\r\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */\r\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */\r\n\r\n/*******************  Bit definition for TIM_CCER register  *******************/\r\n#define TIM_CCER_CC1E_Pos         (0U)\r\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\r\n#define TIM_CCER_CC1P_Pos         (1U)\r\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */\r\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\r\n#define TIM_CCER_CC1NE_Pos        (2U)\r\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */\r\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\r\n#define TIM_CCER_CC1NP_Pos        (3U)\r\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */\r\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\r\n#define TIM_CCER_CC2E_Pos         (4U)\r\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\r\n#define TIM_CCER_CC2P_Pos         (5U)\r\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\r\n#define TIM_CCER_CC2NE_Pos        (6U)\r\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */\r\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\r\n#define TIM_CCER_CC2NP_Pos        (7U)\r\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */\r\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\r\n#define TIM_CCER_CC3E_Pos         (8U)\r\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\r\n#define TIM_CCER_CC3P_Pos         (9U)\r\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */\r\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\r\n#define TIM_CCER_CC3NE_Pos        (10U)\r\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */\r\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\r\n#define TIM_CCER_CC3NP_Pos        (11U)\r\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */\r\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\r\n#define TIM_CCER_CC4E_Pos         (12U)\r\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\r\n#define TIM_CCER_CC4P_Pos         (13U)\r\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\r\n#define TIM_CCER_CC4NP_Pos        (15U)\r\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */\r\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\r\n#define TIM_CCER_CC5E_Pos         (16U)\r\n#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */\r\n#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\r\n#define TIM_CCER_CC5P_Pos         (17U)\r\n#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */\r\n#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\r\n#define TIM_CCER_CC6E_Pos         (20U)\r\n#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */\r\n#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\r\n#define TIM_CCER_CC6P_Pos         (21U)\r\n#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */\r\n#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\r\n/*******************  Bit definition for TIM_CNT register  ********************/\r\n#define TIM_CNT_CNT_Pos           (0U)\r\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */\r\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\r\n#define TIM_CNT_UIFCPY_Pos        (31U)\r\n#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */\r\n#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */\r\n/*******************  Bit definition for TIM_PSC register  ********************/\r\n#define TIM_PSC_PSC_Pos           (0U)\r\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */\r\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\r\n\r\n/*******************  Bit definition for TIM_ARR register  ********************/\r\n#define TIM_ARR_ARR_Pos           (0U)\r\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */\r\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\r\n\r\n/*******************  Bit definition for TIM_RCR register  ********************/\r\n#define TIM_RCR_REP_Pos           (0U)\r\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */\r\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\r\n\r\n/*******************  Bit definition for TIM_CCR1 register  *******************/\r\n#define TIM_CCR1_CCR1_Pos         (0U)\r\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR2 register  *******************/\r\n#define TIM_CCR2_CCR2_Pos         (0U)\r\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR3 register  *******************/\r\n#define TIM_CCR3_CCR3_Pos         (0U)\r\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR4 register  *******************/\r\n#define TIM_CCR4_CCR4_Pos         (0U)\r\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\r\n\r\n/*******************  Bit definition for TIM_CCR5 register  *******************/\r\n#define TIM_CCR5_CCR5_Pos         (0U)\r\n#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */\r\n#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\r\n#define TIM_CCR5_GC5C1_Pos        (29U)\r\n#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */\r\n#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\r\n#define TIM_CCR5_GC5C2_Pos        (30U)\r\n#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */\r\n#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\r\n#define TIM_CCR5_GC5C3_Pos        (31U)\r\n#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */\r\n#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\r\n\r\n/*******************  Bit definition for TIM_CCR6 register  *******************/\r\n#define TIM_CCR6_CCR6_Pos         (0U)\r\n#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\r\n\r\n/*******************  Bit definition for TIM_BDTR register  *******************/\r\n#define TIM_BDTR_DTG_Pos          (0U)\r\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */\r\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */\r\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */\r\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */\r\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */\r\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */\r\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */\r\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */\r\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */\r\n\r\n#define TIM_BDTR_LOCK_Pos         (8U)\r\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */\r\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\r\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */\r\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */\r\n\r\n#define TIM_BDTR_OSSI_Pos         (10U)\r\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */\r\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\r\n#define TIM_BDTR_OSSR_Pos         (11U)\r\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */\r\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\r\n#define TIM_BDTR_BKE_Pos          (12U)\r\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */\r\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */\r\n#define TIM_BDTR_BKP_Pos          (13U)\r\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */\r\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */\r\n#define TIM_BDTR_AOE_Pos          (14U)\r\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */\r\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\r\n#define TIM_BDTR_MOE_Pos          (15U)\r\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */\r\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\r\n\r\n#define TIM_BDTR_BKF_Pos          (16U)\r\n#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */\r\n#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */\r\n#define TIM_BDTR_BK2F_Pos         (20U)\r\n#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */\r\n#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */\r\n\r\n#define TIM_BDTR_BK2E_Pos         (24U)\r\n#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */\r\n#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */\r\n#define TIM_BDTR_BK2P_Pos         (25U)\r\n#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */\r\n#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */\r\n\r\n/*******************  Bit definition for TIM_DCR register  ********************/\r\n#define TIM_DCR_DBA_Pos           (0U)\r\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */\r\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\r\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */\r\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */\r\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */\r\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */\r\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */\r\n\r\n#define TIM_DCR_DBL_Pos           (8U)\r\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */\r\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\r\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */\r\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */\r\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */\r\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */\r\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */\r\n\r\n/*******************  Bit definition for TIM_DMAR register  *******************/\r\n#define TIM_DMAR_DMAB_Pos         (0U)\r\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */\r\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\r\n\r\n/******************  Bit definition for TIM_CCMR3 register  *******************/\r\n#define TIM_CCMR3_OC5FE_Pos       (2U)\r\n#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */\r\n#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\r\n#define TIM_CCMR3_OC5PE_Pos       (3U)\r\n#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */\r\n#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\r\n\r\n#define TIM_CCMR3_OC5M_Pos        (4U)\r\n#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */\r\n#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r\n#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */\r\n#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */\r\n#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR3_OC5CE_Pos       (7U)\r\n#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */\r\n#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\r\n\r\n#define TIM_CCMR3_OC6FE_Pos       (10U)\r\n#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */\r\n#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */\r\n#define TIM_CCMR3_OC6PE_Pos       (11U)\r\n#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */\r\n#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */\r\n\r\n#define TIM_CCMR3_OC6M_Pos        (12U)\r\n#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */\r\n#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */\r\n#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */\r\n#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */\r\n#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */\r\n\r\n#define TIM_CCMR3_OC6CE_Pos       (15U)\r\n#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */\r\n#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */\r\n/*******************  Bit definition for TIM1_AF1 register  *********************/\r\n#define TIM1_AF1_BKINE_Pos        (0U)\r\n#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */\r\n#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */\r\n#define TIM1_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\r\n#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM1_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\r\n#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */\r\n#define TIM1_AF1_BKDF1BK0E_Pos    (8U)\r\n#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */\r\n#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */\r\n#define TIM1_AF1_BKINP_Pos        (9U)\r\n#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */\r\n#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */\r\n#define TIM1_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\r\n#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM1_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\r\n#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n#define TIM1_AF1_ETRSEL_Pos       (14U)\r\n#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\r\n#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */\r\n#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */\r\n#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */\r\n#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */\r\n#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM1_AF2 register  *********************/\r\n#define TIM1_AF2_BK2INE_Pos       (0U)\r\n#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */\r\n#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */\r\n#define TIM1_AF2_BK2CMP1E_Pos     (1U)\r\n#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\r\n#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */\r\n#define TIM1_AF2_BK2CMP2E_Pos     (2U)\r\n#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\r\n#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */\r\n#define TIM1_AF2_BK2DFBK1E_Pos    (8U)\r\n#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */\r\n#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */\r\n#define TIM1_AF2_BK2INP_Pos       (9U)\r\n#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */\r\n#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */\r\n#define TIM1_AF2_BK2CMP1P_Pos     (10U)\r\n#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\r\n#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */\r\n#define TIM1_AF2_BK2CMP2P_Pos     (11U)\r\n#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\r\n#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM_TISEL register  *********************/\r\n#define TIM_TISEL_TI1SEL_Pos      (0U)\r\n#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */\r\n#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/\r\n#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */\r\n#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */\r\n#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */\r\n#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */\r\n\r\n#define TIM_TISEL_TI2SEL_Pos      (8U)\r\n#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */\r\n#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/\r\n#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */\r\n#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */\r\n#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */\r\n#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */\r\n\r\n#define TIM_TISEL_TI3SEL_Pos      (16U)\r\n#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */\r\n#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/\r\n#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */\r\n#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */\r\n#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */\r\n#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */\r\n\r\n#define TIM_TISEL_TI4SEL_Pos      (24U)\r\n#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */\r\n#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/\r\n#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */\r\n#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */\r\n#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */\r\n#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */\r\n\r\n/*******************  Bit definition for TIM8_AF1 register  *********************/\r\n#define TIM8_AF1_BKINE_Pos        (0U)\r\n#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */\r\n#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */\r\n#define TIM8_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */\r\n#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM8_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */\r\n#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM8_AF1_BKDFBK2E_Pos     (8U)\r\n#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */\r\n#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */\r\n#define TIM8_AF1_BKINP_Pos        (9U)\r\n#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */\r\n#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */\r\n#define TIM8_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */\r\n#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM8_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */\r\n#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n#define TIM8_AF1_ETRSEL_Pos       (14U)\r\n#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */\r\n#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */\r\n#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */\r\n#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */\r\n#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */\r\n#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */\r\n/*******************  Bit definition for TIM8_AF2 register  *********************/\r\n#define TIM8_AF2_BK2INE_Pos       (0U)\r\n#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */\r\n#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */\r\n#define TIM8_AF2_BK2CMP1E_Pos     (1U)\r\n#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */\r\n#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */\r\n#define TIM8_AF2_BK2CMP2E_Pos     (2U)\r\n#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */\r\n#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */\r\n#define TIM8_AF2_BK2DFBK3E_Pos    (8U)\r\n#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */\r\n#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */\r\n#define TIM8_AF2_BK2INP_Pos       (9U)\r\n#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */\r\n#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */\r\n#define TIM8_AF2_BK2CMP1P_Pos     (10U)\r\n#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */\r\n#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */\r\n#define TIM8_AF2_BK2CMP2P_Pos     (11U)\r\n#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */\r\n#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM2_AF1 register  *********************/\r\n#define TIM2_AF1_ETRSEL_Pos      (14U)\r\n#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\r\n#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */\r\n#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\r\n#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\r\n#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\r\n#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM3_AF1 register  *********************/\r\n#define TIM3_AF1_ETRSEL_Pos      (14U)\r\n#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\r\n#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */\r\n#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\r\n#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\r\n#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\r\n#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM5_AF1 register  *********************/\r\n#define TIM5_AF1_ETRSEL_Pos      (14U)\r\n#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */\r\n#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */\r\n#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */\r\n#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */\r\n#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */\r\n#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */\r\n\r\n/*******************  Bit definition for TIM15_AF1 register  *********************/\r\n#define TIM15_AF1_BKINE_Pos        (0U)\r\n#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */\r\n#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\r\n#define TIM15_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\r\n#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM15_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\r\n#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM15_AF1_BKDF1BK2E_Pos    (8U)\r\n#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r\n#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */\r\n#define TIM15_AF1_BKINP_Pos        (9U)\r\n#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */\r\n#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\r\n#define TIM15_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\r\n#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM15_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\r\n#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM16_ register  *********************/\r\n#define TIM16_AF1_BKINE_Pos        (0U)\r\n#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */\r\n#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\r\n#define TIM16_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\r\n#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM16_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\r\n#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM16_AF1_BKDF1BK2E_Pos    (8U)\r\n#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r\n#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */\r\n#define TIM16_AF1_BKINP_Pos        (9U)\r\n#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */\r\n#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\r\n#define TIM16_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\r\n#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM16_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\r\n#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n/*******************  Bit definition for TIM17_AF1 register  *********************/\r\n#define TIM17_AF1_BKINE_Pos        (0U)\r\n#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */\r\n#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */\r\n#define TIM17_AF1_BKCMP1E_Pos      (1U)\r\n#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */\r\n#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */\r\n#define TIM17_AF1_BKCMP2E_Pos      (2U)\r\n#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */\r\n#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */\r\n#define TIM17_AF1_BKDF1BK2E_Pos    (8U)\r\n#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */\r\n#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */\r\n#define TIM17_AF1_BKINP_Pos        (9U)\r\n#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */\r\n#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */\r\n#define TIM17_AF1_BKCMP1P_Pos      (10U)\r\n#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */\r\n#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */\r\n#define TIM17_AF1_BKCMP2P_Pos      (11U)\r\n#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */\r\n#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Low Power Timer (LPTTIM)                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for LPTIM_ISR register  *******************/\r\n#define LPTIM_ISR_CMPM_Pos          (0U)\r\n#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */\r\n#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */\r\n#define LPTIM_ISR_ARRM_Pos          (1U)\r\n#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */\r\n#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */\r\n#define LPTIM_ISR_EXTTRIG_Pos       (2U)\r\n#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */\r\n#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */\r\n#define LPTIM_ISR_CMPOK_Pos         (3U)\r\n#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */\r\n#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */\r\n#define LPTIM_ISR_ARROK_Pos         (4U)\r\n#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */\r\n#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */\r\n#define LPTIM_ISR_UP_Pos            (5U)\r\n#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */\r\n#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\r\n#define LPTIM_ISR_DOWN_Pos          (6U)\r\n#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */\r\n#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\r\n\r\n/******************  Bit definition for LPTIM_ICR register  *******************/\r\n#define LPTIM_ICR_CMPMCF_Pos        (0U)\r\n#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */\r\n#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */\r\n#define LPTIM_ICR_ARRMCF_Pos        (1U)\r\n#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */\r\n#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */\r\n#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)\r\n#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */\r\n#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */\r\n#define LPTIM_ICR_CMPOKCF_Pos       (3U)\r\n#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */\r\n#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */\r\n#define LPTIM_ICR_ARROKCF_Pos       (4U)\r\n#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */\r\n#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */\r\n#define LPTIM_ICR_UPCF_Pos          (5U)\r\n#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */\r\n#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\r\n#define LPTIM_ICR_DOWNCF_Pos        (6U)\r\n#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\r\n\r\n/******************  Bit definition for LPTIM_IER register ********************/\r\n#define LPTIM_IER_CMPMIE_Pos        (0U)\r\n#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */\r\n#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */\r\n#define LPTIM_IER_ARRMIE_Pos        (1U)\r\n#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */\r\n#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */\r\n#define LPTIM_IER_EXTTRIGIE_Pos     (2U)\r\n#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */\r\n#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */\r\n#define LPTIM_IER_CMPOKIE_Pos       (3U)\r\n#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */\r\n#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */\r\n#define LPTIM_IER_ARROKIE_Pos       (4U)\r\n#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */\r\n#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */\r\n#define LPTIM_IER_UPIE_Pos          (5U)\r\n#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */\r\n#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\r\n#define LPTIM_IER_DOWNIE_Pos        (6U)\r\n#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\r\n\r\n/******************  Bit definition for LPTIM_CFGR register *******************/\r\n#define LPTIM_CFGR_CKSEL_Pos        (0U)\r\n#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */\r\n#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\r\n\r\n#define LPTIM_CFGR_CKPOL_Pos        (1U)\r\n#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */\r\n#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\r\n#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */\r\n#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */\r\n\r\n#define LPTIM_CFGR_CKFLT_Pos        (3U)\r\n#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */\r\n#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r\n#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */\r\n#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */\r\n\r\n#define LPTIM_CFGR_TRGFLT_Pos       (6U)\r\n#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */\r\n#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r\n#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */\r\n\r\n#define LPTIM_CFGR_PRESC_Pos        (9U)\r\n#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */\r\n#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\r\n#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */\r\n#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */\r\n#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */\r\n\r\n#define LPTIM_CFGR_TRIGSEL_Pos      (13U)\r\n#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */\r\n#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r\n#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */\r\n#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */\r\n#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */\r\n\r\n#define LPTIM_CFGR_TRIGEN_Pos       (17U)\r\n#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */\r\n#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r\n#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */\r\n#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */\r\n\r\n#define LPTIM_CFGR_TIMOUT_Pos       (19U)\r\n#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */\r\n#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */\r\n#define LPTIM_CFGR_WAVE_Pos         (20U)\r\n#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */\r\n#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */\r\n#define LPTIM_CFGR_WAVPOL_Pos       (21U)\r\n#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */\r\n#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\r\n#define LPTIM_CFGR_PRELOAD_Pos      (22U)\r\n#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */\r\n#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */\r\n#define LPTIM_CFGR_COUNTMODE_Pos    (23U)\r\n#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */\r\n#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */\r\n#define LPTIM_CFGR_ENC_Pos          (24U)\r\n#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */\r\n#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */\r\n\r\n/******************  Bit definition for LPTIM_CR register  ********************/\r\n#define LPTIM_CR_ENABLE_Pos         (0U)\r\n#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */\r\n#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */\r\n#define LPTIM_CR_SNGSTRT_Pos        (1U)\r\n#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */\r\n#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */\r\n#define LPTIM_CR_CNTSTRT_Pos        (2U)\r\n#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */\r\n#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\r\n#define LPTIM_CR_COUNTRST_Pos       (3U)\r\n#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */\r\n#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/\r\n#define LPTIM_CR_RSTARE_Pos         (4U)\r\n#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */\r\n#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/\r\n\r\n\r\n/******************  Bit definition for LPTIM_CMP register  *******************/\r\n#define LPTIM_CMP_CMP_Pos           (0U)\r\n#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */\r\n#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */\r\n\r\n/******************  Bit definition for LPTIM_ARR register  *******************/\r\n#define LPTIM_ARR_ARR_Pos           (0U)\r\n#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */\r\n#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\r\n\r\n/******************  Bit definition for LPTIM_CNT register  *******************/\r\n#define LPTIM_CNT_CNT_Pos           (0U)\r\n#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */\r\n#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */\r\n\r\n/******************  Bit definition for LPTIM_CFGR2 register  *****************/\r\n#define LPTIM_CFGR2_IN1SEL_Pos      (0U)\r\n#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */\r\n#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */\r\n#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */\r\n#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */\r\n#define LPTIM_CFGR2_IN2SEL_Pos      (4U)\r\n#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */\r\n#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */\r\n#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */\r\n#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    OCTOSPI                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*****************  Bit definition for OCTOSPI_CR register  *******************/\r\n#define OCTOSPI_CR_EN_Pos              (0U)\r\n#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */\r\n#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */\r\n#define OCTOSPI_CR_ABORT_Pos           (1U)\r\n#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */\r\n#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */\r\n#define OCTOSPI_CR_DMAEN_Pos           (2U)\r\n#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */\r\n#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */\r\n#define OCTOSPI_CR_TCEN_Pos            (3U)\r\n#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */\r\n#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */\r\n#define OCTOSPI_CR_DQM_Pos             (6U)\r\n#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */\r\n#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */\r\n#define OCTOSPI_CR_FSEL_Pos            (7U)\r\n#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */\r\n#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */\r\n#define OCTOSPI_CR_FTHRES_Pos          (8U)\r\n#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */\r\n#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */\r\n#define OCTOSPI_CR_TEIE_Pos            (16U)\r\n#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */\r\n#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */\r\n#define OCTOSPI_CR_TCIE_Pos            (17U)\r\n#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */\r\n#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */\r\n#define OCTOSPI_CR_FTIE_Pos            (18U)\r\n#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */\r\n#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */\r\n#define OCTOSPI_CR_SMIE_Pos            (19U)\r\n#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */\r\n#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */\r\n#define OCTOSPI_CR_TOIE_Pos            (20U)\r\n#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */\r\n#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */\r\n#define OCTOSPI_CR_APMS_Pos            (22U)\r\n#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */\r\n#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */\r\n#define OCTOSPI_CR_PMM_Pos             (23U)\r\n#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */\r\n#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */\r\n#define OCTOSPI_CR_FMODE_Pos           (28U)\r\n#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */\r\n#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */\r\n#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */\r\n#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR1 register  ******************/\r\n#define OCTOSPI_DCR1_CKMODE_Pos        (0U)\r\n#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */\r\n#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */\r\n#define OCTOSPI_DCR1_FRCK_Pos          (1U)\r\n#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */\r\n#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */\r\n#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)\r\n#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */\r\n#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */\r\n#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)\r\n#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */\r\n#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */\r\n#define OCTOSPI_DCR1_CSHT_Pos          (8U)\r\n#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */\r\n#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */\r\n#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)\r\n#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */\r\n#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */\r\n#define OCTOSPI_DCR1_MTYP_Pos          (24U)\r\n#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */\r\n#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */\r\n#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */\r\n#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */\r\n#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR2 register  ******************/\r\n#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)\r\n#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */\r\n#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */\r\n#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)\r\n#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */\r\n#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */\r\n#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */\r\n#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */\r\n#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR3 register  ******************/\r\n#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)\r\n#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */\r\n#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */\r\n#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)\r\n#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */\r\n#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */\r\n\r\n/****************  Bit definition for OCTOSPI_DCR4 register  ******************/\r\n#define OCTOSPI_DCR4_REFRESH_Pos       (0U)\r\n#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */\r\n\r\n/*****************  Bit definition for OCTOSPI_SR register  *******************/\r\n#define OCTOSPI_SR_TEF_Pos             (0U)\r\n#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */\r\n#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */\r\n#define OCTOSPI_SR_TCF_Pos             (1U)\r\n#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */\r\n#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */\r\n#define OCTOSPI_SR_FTF_Pos             (2U)\r\n#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */\r\n#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */\r\n#define OCTOSPI_SR_SMF_Pos             (3U)\r\n#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */\r\n#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */\r\n#define OCTOSPI_SR_TOF_Pos             (4U)\r\n#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */\r\n#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */\r\n#define OCTOSPI_SR_BUSY_Pos            (5U)\r\n#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */\r\n#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */\r\n#define OCTOSPI_SR_FLEVEL_Pos          (8U)\r\n#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */\r\n#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */\r\n\r\n/****************  Bit definition for OCTOSPI_FCR register  *******************/\r\n#define OCTOSPI_FCR_CTEF_Pos           (0U)\r\n#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */\r\n#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */\r\n#define OCTOSPI_FCR_CTCF_Pos           (1U)\r\n#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */\r\n#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */\r\n#define OCTOSPI_FCR_CSMF_Pos           (3U)\r\n#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */\r\n#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */\r\n#define OCTOSPI_FCR_CTOF_Pos           (4U)\r\n#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */\r\n#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */\r\n\r\n/****************  Bit definition for OCTOSPI_DLR register  *******************/\r\n#define OCTOSPI_DLR_DL_Pos             (0U)\r\n#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */\r\n\r\n/*****************  Bit definition for OCTOSPI_AR register  *******************/\r\n#define OCTOSPI_AR_ADDRESS_Pos         (0U)\r\n#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */\r\n\r\n/*****************  Bit definition for OCTOSPI_DR register  *******************/\r\n#define OCTOSPI_DR_DATA_Pos            (0U)\r\n#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */\r\n\r\n/***************  Bit definition for OCTOSPI_PSMKR register  ******************/\r\n#define OCTOSPI_PSMKR_MASK_Pos         (0U)\r\n#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */\r\n\r\n/***************  Bit definition for OCTOSPI_PSMAR register  ******************/\r\n#define OCTOSPI_PSMAR_MATCH_Pos        (0U)\r\n#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */\r\n\r\n/****************  Bit definition for OCTOSPI_PIR register  *******************/\r\n#define OCTOSPI_PIR_INTERVAL_Pos       (0U)\r\n#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */\r\n#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */\r\n\r\n/****************  Bit definition for OCTOSPI_CCR register  *******************/\r\n#define OCTOSPI_CCR_IMODE_Pos          (0U)\r\n#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */\r\n#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */\r\n#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */\r\n#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */\r\n#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */\r\n#define OCTOSPI_CCR_IDTR_Pos           (3U)\r\n#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */\r\n#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */\r\n#define OCTOSPI_CCR_ISIZE_Pos          (4U)\r\n#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */\r\n#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */\r\n#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */\r\n#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */\r\n#define OCTOSPI_CCR_ADMODE_Pos         (8U)\r\n#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */\r\n#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */\r\n#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */\r\n#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */\r\n#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */\r\n#define OCTOSPI_CCR_ADDTR_Pos          (11U)\r\n#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */\r\n#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */\r\n#define OCTOSPI_CCR_ADSIZE_Pos         (12U)\r\n#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */\r\n#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */\r\n#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */\r\n#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */\r\n#define OCTOSPI_CCR_ABMODE_Pos         (16U)\r\n#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */\r\n#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */\r\n#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */\r\n#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */\r\n#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */\r\n#define OCTOSPI_CCR_ABDTR_Pos          (19U)\r\n#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */\r\n#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */\r\n#define OCTOSPI_CCR_ABSIZE_Pos         (20U)\r\n#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */\r\n#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */\r\n#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */\r\n#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */\r\n#define OCTOSPI_CCR_DMODE_Pos          (24U)\r\n#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */\r\n#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */\r\n#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */\r\n#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */\r\n#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */\r\n#define OCTOSPI_CCR_DDTR_Pos           (27U)\r\n#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */\r\n#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */\r\n#define OCTOSPI_CCR_DQSE_Pos           (29U)\r\n#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */\r\n#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */\r\n#define OCTOSPI_CCR_SIOO_Pos           (31U)\r\n#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */\r\n#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */\r\n\r\n/****************  Bit definition for OCTOSPI_TCR register  *******************/\r\n#define OCTOSPI_TCR_DCYC_Pos           (0U)\r\n#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */\r\n#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */\r\n#define OCTOSPI_TCR_DHQC_Pos           (28U)\r\n#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */\r\n#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */\r\n#define OCTOSPI_TCR_SSHIFT_Pos         (30U)\r\n#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */\r\n#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */\r\n\r\n/*****************  Bit definition for OCTOSPI_IR register  *******************/\r\n#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)\r\n#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */\r\n\r\n/****************  Bit definition for OCTOSPI_ABR register  *******************/\r\n#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)\r\n#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */\r\n\r\n/****************  Bit definition for OCTOSPI_LPTR register  ******************/\r\n#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)\r\n#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */\r\n#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */\r\n\r\n/****************  Bit definition for OCTOSPI_WPCCR register  *******************/\r\n#define OCTOSPI_WPCCR_IMODE_Pos        (0U)\r\n#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */\r\n#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */\r\n#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */\r\n#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */\r\n#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */\r\n#define OCTOSPI_WPCCR_IDTR_Pos         (3U)\r\n#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */\r\n#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)\r\n#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */\r\n#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */\r\n#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */\r\n#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */\r\n#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)\r\n#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */\r\n#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */\r\n#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */\r\n#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */\r\n#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */\r\n#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)\r\n#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */\r\n#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)\r\n#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */\r\n#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */\r\n#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */\r\n#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */\r\n#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)\r\n#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */\r\n#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */\r\n#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */\r\n#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */\r\n#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */\r\n#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)\r\n#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */\r\n#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)\r\n#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */\r\n#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */\r\n#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */\r\n#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */\r\n#define OCTOSPI_WPCCR_DMODE_Pos        (24U)\r\n#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */\r\n#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */\r\n#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */\r\n#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */\r\n#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */\r\n#define OCTOSPI_WPCCR_DDTR_Pos         (27U)\r\n#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */\r\n#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */\r\n#define OCTOSPI_WPCCR_DQSE_Pos         (29U)\r\n#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */\r\n#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */\r\n#define OCTOSPI_WPCCR_SIOO_Pos         (31U)\r\n#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */\r\n#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */\r\n\r\n/****************  Bit definition for OCTOSPI_WPTCR register  *******************/\r\n#define OCTOSPI_WPTCR_DCYC_Pos         (0U)\r\n#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */\r\n#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */\r\n#define OCTOSPI_WPTCR_DHQC_Pos         (28U)\r\n#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */\r\n#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */\r\n#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)\r\n#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */\r\n#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */\r\n\r\n/*****************  Bit definition for OCTOSPI_WPIR register  *******************/\r\n#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)\r\n#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */\r\n\r\n/****************  Bit definition for OCTOSPI_WPABR register  *******************/\r\n#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)\r\n#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */\r\n\r\n/****************  Bit definition for OCTOSPI_WCCR register  ******************/\r\n#define OCTOSPI_WCCR_IMODE_Pos         (0U)\r\n#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */\r\n#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */\r\n#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */\r\n#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */\r\n#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */\r\n#define OCTOSPI_WCCR_IDTR_Pos          (3U)\r\n#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */\r\n#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */\r\n#define OCTOSPI_WCCR_ISIZE_Pos         (4U)\r\n#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */\r\n#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */\r\n#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */\r\n#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */\r\n#define OCTOSPI_WCCR_ADMODE_Pos        (8U)\r\n#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */\r\n#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */\r\n#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */\r\n#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */\r\n#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */\r\n#define OCTOSPI_WCCR_ADDTR_Pos         (11U)\r\n#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */\r\n#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */\r\n#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)\r\n#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */\r\n#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */\r\n#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */\r\n#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */\r\n#define OCTOSPI_WCCR_ABMODE_Pos        (16U)\r\n#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */\r\n#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */\r\n#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */\r\n#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */\r\n#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */\r\n#define OCTOSPI_WCCR_ABDTR_Pos         (19U)\r\n#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */\r\n#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */\r\n#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)\r\n#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */\r\n#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */\r\n#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */\r\n#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */\r\n#define OCTOSPI_WCCR_DMODE_Pos         (24U)\r\n#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */\r\n#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */\r\n#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */\r\n#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */\r\n#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */\r\n#define OCTOSPI_WCCR_DDTR_Pos          (27U)\r\n#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */\r\n#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */\r\n#define OCTOSPI_WCCR_DQSE_Pos          (29U)\r\n#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */\r\n#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */\r\n#define OCTOSPI_WCCR_SIOO_Pos          (31U)\r\n#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */\r\n#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */\r\n\r\n/****************  Bit definition for OCTOSPI_WTCR register  ******************/\r\n#define OCTOSPI_WTCR_DCYC_Pos          (0U)\r\n#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */\r\n#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */\r\n\r\n/****************  Bit definition for OCTOSPI_WIR register  *******************/\r\n#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)\r\n#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */\r\n\r\n/****************  Bit definition for OCTOSPI_WABR register  ******************/\r\n#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)\r\n#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */\r\n\r\n/****************  Bit definition for OCTOSPI_HLCR register  ******************/\r\n#define OCTOSPI_HLCR_LM_Pos            (0U)\r\n#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */\r\n#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */\r\n#define OCTOSPI_HLCR_WZL_Pos           (1U)\r\n#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */\r\n#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */\r\n#define OCTOSPI_HLCR_TACC_Pos          (8U)\r\n#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */\r\n#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */\r\n#define OCTOSPI_HLCR_TRWR_Pos          (16U)\r\n#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */\r\n#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */\r\n\r\n/****************  Bit definition for OCTOSPI_VER register  *******************/\r\n#define OCTOSPI_VER_VER_Pos            (0U)\r\n#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */\r\n#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */\r\n\r\n/*****************  Bit definition for OCTOSPI_ID register  *******************/\r\n#define OCTOSPI_ID_ID_Pos              (0U)\r\n#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */\r\n\r\n/****************  Bit definition for OCTOSPI_MID register  *******************/\r\n#define OCTOSPI_MID_MID_Pos            (0U)\r\n#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */\r\n#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                  OCTOSPIM                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/***************  Bit definition for OCTOSPIM_CR register  ********************/\r\n#define OCTOSPIM_CR_MUXEN_Pos          (0U)\r\n#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */\r\n#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */\r\n#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)\r\n#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */\r\n#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */\r\n\r\n/***************  Bit definition for OCTOSPIM_PCR register  *******************/\r\n#define OCTOSPIM_PCR_CLKEN_Pos         (0U)\r\n#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */\r\n#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */\r\n#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)\r\n#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */\r\n#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */\r\n#define OCTOSPIM_PCR_DQSEN_Pos         (4U)\r\n#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */\r\n#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */\r\n#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)\r\n#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */\r\n#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */\r\n#define OCTOSPIM_PCR_NCSEN_Pos         (8U)\r\n#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */\r\n#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */\r\n#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)\r\n#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */\r\n#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */\r\n#define OCTOSPIM_PCR_IOLEN_Pos         (16U)\r\n#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */\r\n#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */\r\n#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)\r\n#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */\r\n#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */\r\n#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */\r\n#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */\r\n#define OCTOSPIM_PCR_IOHEN_Pos         (24U)\r\n#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */\r\n#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */\r\n#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)\r\n#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */\r\n#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */\r\n#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */\r\n#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Analog Comparators (COMP)                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for COMP_SR register  ********************/\r\n#define COMP_SR_C1VAL_Pos            (0U)\r\n#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */\r\n#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk\r\n#define COMP_SR_C2VAL_Pos            (1U)\r\n#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */\r\n#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk\r\n#define COMP_SR_C1IF_Pos             (16U)\r\n#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */\r\n#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk\r\n#define COMP_SR_C2IF_Pos             (17U)\r\n#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */\r\n#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk\r\n/*******************  Bit definition for COMP_ICFR register  ********************/\r\n#define COMP_ICFR_C1IF_Pos           (16U)\r\n#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */\r\n#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk\r\n#define COMP_ICFR_C2IF_Pos           (17U)\r\n#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */\r\n#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk\r\n/*******************  Bit definition for COMP_OR register  ********************/\r\n#define COMP_OR_AFOPA6_Pos           (0U)\r\n#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */\r\n#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk\r\n#define COMP_OR_AFOPA8_Pos           (1U)\r\n#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */\r\n#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk\r\n#define COMP_OR_AFOPB12_Pos          (2U)\r\n#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */\r\n#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk\r\n#define COMP_OR_AFOPE6_Pos           (3U)\r\n#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */\r\n#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk\r\n#define COMP_OR_AFOPE15_Pos          (4U)\r\n#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */\r\n#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk\r\n#define COMP_OR_AFOPG2_Pos           (5U)\r\n#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */\r\n#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk\r\n#define COMP_OR_AFOPG3_Pos           (6U)\r\n#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */\r\n#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk\r\n#define COMP_OR_AFOPG4_Pos           (7U)\r\n#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */\r\n#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk\r\n#define COMP_OR_AFOPI1_Pos           (8U)\r\n#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */\r\n#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk\r\n#define COMP_OR_AFOPI4_Pos           (9U)\r\n#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */\r\n#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk\r\n#define COMP_OR_AFOPK2_Pos           (10U)\r\n#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */\r\n#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk\r\n\r\n/*!< ******************  Bit definition for COMP_CFGRx register  ********************/\r\n#define COMP_CFGRx_EN_Pos            (0U)\r\n#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */\r\n#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */\r\n#define COMP_CFGRx_BRGEN_Pos         (1U)\r\n#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */\r\n#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */\r\n#define COMP_CFGRx_SCALEN_Pos        (2U)\r\n#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */\r\n#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */\r\n#define COMP_CFGRx_POLARITY_Pos      (3U)\r\n#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */\r\n#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */\r\n#define COMP_CFGRx_WINMODE_Pos       (4U)\r\n#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */\r\n#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */\r\n#define COMP_CFGRx_ITEN_Pos          (6U)\r\n#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */\r\n#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */\r\n#define COMP_CFGRx_HYST_Pos          (8U)\r\n#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */\r\n#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */\r\n#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */\r\n#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */\r\n#define COMP_CFGRx_PWRMODE_Pos       (12U)\r\n#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */\r\n#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */\r\n#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */\r\n#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */\r\n#define COMP_CFGRx_INMSEL_Pos        (16U)\r\n#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */\r\n#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */\r\n#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */\r\n#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */\r\n#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */\r\n#define COMP_CFGRx_INPSEL_Pos        (20U)\r\n#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */\r\n#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */\r\n#define COMP_CFGRx_BLANKING_Pos      (24U)\r\n#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */\r\n#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */\r\n#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */\r\n#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */\r\n#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */\r\n#define COMP_CFGRx_LOCK_Pos          (31U)\r\n#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */\r\n#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for USART_CR1 register  *******************/\r\n#define USART_CR1_UE_Pos                (0U)\r\n#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */\r\n#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */\r\n#define USART_CR1_UESM_Pos              (1U)\r\n#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */\r\n#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */\r\n#define USART_CR1_RE_Pos                (2U)\r\n#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */\r\n#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */\r\n#define USART_CR1_TE_Pos                (3U)\r\n#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */\r\n#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */\r\n#define USART_CR1_IDLEIE_Pos            (4U)\r\n#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */\r\n#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */\r\n#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)\r\n#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */\r\n#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */\r\n#define USART_CR1_TCIE_Pos              (6U)\r\n#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */\r\n#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */\r\n#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)\r\n#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */\r\n#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */\r\n#define USART_CR1_PEIE_Pos              (8U)\r\n#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */\r\n#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */\r\n#define USART_CR1_PS_Pos                (9U)\r\n#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */\r\n#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */\r\n#define USART_CR1_PCE_Pos               (10U)\r\n#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */\r\n#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */\r\n#define USART_CR1_WAKE_Pos              (11U)\r\n#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */\r\n#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */\r\n#define USART_CR1_M_Pos                 (12U)\r\n#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */\r\n#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */\r\n#define USART_CR1_M0_Pos                (12U)\r\n#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */\r\n#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */\r\n#define USART_CR1_MME_Pos               (13U)\r\n#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */\r\n#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */\r\n#define USART_CR1_CMIE_Pos              (14U)\r\n#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */\r\n#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */\r\n#define USART_CR1_OVER8_Pos             (15U)\r\n#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */\r\n#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */\r\n#define USART_CR1_DEDT_Pos              (16U)\r\n#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */\r\n#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r\n#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */\r\n#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */\r\n#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */\r\n#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */\r\n#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */\r\n#define USART_CR1_DEAT_Pos              (21U)\r\n#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */\r\n#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r\n#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */\r\n#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */\r\n#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */\r\n#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */\r\n#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */\r\n#define USART_CR1_RTOIE_Pos             (26U)\r\n#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */\r\n#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */\r\n#define USART_CR1_EOBIE_Pos             (27U)\r\n#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */\r\n#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */\r\n#define USART_CR1_M1_Pos                (28U)\r\n#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */\r\n#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */\r\n#define USART_CR1_FIFOEN_Pos            (29U)\r\n#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */\r\n#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */\r\n#define USART_CR1_TXFEIE_Pos            (30U)\r\n#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */\r\n#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */\r\n#define USART_CR1_RXFFIE_Pos            (31U)\r\n#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */\r\n#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */\r\n\r\n/* Legacy define */\r\n#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE\r\n#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE\r\n\r\n/******************  Bit definition for USART_CR2 register  *******************/\r\n#define USART_CR2_SLVEN_Pos             (0U)\r\n#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */\r\n#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */\r\n#define USART_CR2_DIS_NSS_Pos           (3U)\r\n#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */\r\n#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */\r\n#define USART_CR2_ADDM7_Pos             (4U)\r\n#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */\r\n#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */\r\n#define USART_CR2_LBDL_Pos              (5U)\r\n#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */\r\n#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */\r\n#define USART_CR2_LBDIE_Pos             (6U)\r\n#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */\r\n#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */\r\n#define USART_CR2_LBCL_Pos              (8U)\r\n#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */\r\n#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */\r\n#define USART_CR2_CPHA_Pos              (9U)\r\n#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */\r\n#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */\r\n#define USART_CR2_CPOL_Pos              (10U)\r\n#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */\r\n#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */\r\n#define USART_CR2_CLKEN_Pos             (11U)\r\n#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */\r\n#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */\r\n#define USART_CR2_STOP_Pos              (12U)\r\n#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */\r\n#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */\r\n#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */\r\n#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */\r\n#define USART_CR2_LINEN_Pos             (14U)\r\n#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */\r\n#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */\r\n#define USART_CR2_SWAP_Pos              (15U)\r\n#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */\r\n#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */\r\n#define USART_CR2_RXINV_Pos             (16U)\r\n#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */\r\n#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */\r\n#define USART_CR2_TXINV_Pos             (17U)\r\n#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */\r\n#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */\r\n#define USART_CR2_DATAINV_Pos           (18U)\r\n#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */\r\n#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */\r\n#define USART_CR2_MSBFIRST_Pos          (19U)\r\n#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */\r\n#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */\r\n#define USART_CR2_ABREN_Pos             (20U)\r\n#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */\r\n#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/\r\n#define USART_CR2_ABRMODE_Pos           (21U)\r\n#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */\r\n#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r\n#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */\r\n#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */\r\n#define USART_CR2_RTOEN_Pos             (23U)\r\n#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */\r\n#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */\r\n#define USART_CR2_ADD_Pos               (24U)\r\n#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */\r\n#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */\r\n\r\n/******************  Bit definition for USART_CR3 register  *******************/\r\n#define USART_CR3_EIE_Pos               (0U)\r\n#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */\r\n#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */\r\n#define USART_CR3_IREN_Pos              (1U)\r\n#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */\r\n#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */\r\n#define USART_CR3_IRLP_Pos              (2U)\r\n#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */\r\n#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */\r\n#define USART_CR3_HDSEL_Pos             (3U)\r\n#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */\r\n#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */\r\n#define USART_CR3_NACK_Pos              (4U)\r\n#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */\r\n#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */\r\n#define USART_CR3_SCEN_Pos              (5U)\r\n#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */\r\n#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */\r\n#define USART_CR3_DMAR_Pos              (6U)\r\n#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */\r\n#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */\r\n#define USART_CR3_DMAT_Pos              (7U)\r\n#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */\r\n#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */\r\n#define USART_CR3_RTSE_Pos              (8U)\r\n#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */\r\n#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */\r\n#define USART_CR3_CTSE_Pos              (9U)\r\n#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */\r\n#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */\r\n#define USART_CR3_CTSIE_Pos             (10U)\r\n#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */\r\n#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */\r\n#define USART_CR3_ONEBIT_Pos            (11U)\r\n#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */\r\n#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */\r\n#define USART_CR3_OVRDIS_Pos            (12U)\r\n#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */\r\n#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */\r\n#define USART_CR3_DDRE_Pos              (13U)\r\n#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */\r\n#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */\r\n#define USART_CR3_DEM_Pos               (14U)\r\n#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */\r\n#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */\r\n#define USART_CR3_DEP_Pos               (15U)\r\n#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */\r\n#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */\r\n#define USART_CR3_SCARCNT_Pos           (17U)\r\n#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */\r\n#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r\n#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */\r\n#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */\r\n#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */\r\n#define USART_CR3_WUS_Pos               (20U)\r\n#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */\r\n#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\r\n#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */\r\n#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */\r\n#define USART_CR3_WUFIE_Pos             (22U)\r\n#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */\r\n#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */\r\n#define USART_CR3_TXFTIE_Pos            (23U)\r\n#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */\r\n#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */\r\n#define USART_CR3_TCBGTIE_Pos           (24U)\r\n#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */\r\n#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */\r\n#define USART_CR3_RXFTCFG_Pos           (25U)\r\n#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */\r\n#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */\r\n#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */\r\n#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */\r\n#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */\r\n#define USART_CR3_RXFTIE_Pos            (28U)\r\n#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */\r\n#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */\r\n#define USART_CR3_TXFTCFG_Pos           (29U)\r\n#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */\r\n#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */\r\n#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */\r\n#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */\r\n#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for USART_BRR register  *******************/\r\n#define USART_BRR_DIV_FRACTION_Pos      (0U)\r\n#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */\r\n#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */\r\n#define USART_BRR_DIV_MANTISSA_Pos      (4U)\r\n#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\r\n#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */\r\n\r\n/******************  Bit definition for USART_GTPR register  ******************/\r\n#define USART_GTPR_PSC_Pos              (0U)\r\n#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */\r\n#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */\r\n#define USART_GTPR_GT_Pos               (8U)\r\n#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */\r\n#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */\r\n\r\n/*******************  Bit definition for USART_RTOR register  *****************/\r\n#define USART_RTOR_RTO_Pos              (0U)\r\n#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */\r\n#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */\r\n#define USART_RTOR_BLEN_Pos             (24U)\r\n#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */\r\n#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */\r\n\r\n/*******************  Bit definition for USART_RQR register  ******************/\r\n#define USART_RQR_ABRRQ_Pos             (0U)\r\n#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */\r\n#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */\r\n#define USART_RQR_SBKRQ_Pos             (1U)\r\n#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */\r\n#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */\r\n#define USART_RQR_MMRQ_Pos              (2U)\r\n#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */\r\n#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */\r\n#define USART_RQR_RXFRQ_Pos             (3U)\r\n#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */\r\n#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */\r\n#define USART_RQR_TXFRQ_Pos             (4U)\r\n#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */\r\n#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */\r\n\r\n/*******************  Bit definition for USART_ISR register  ******************/\r\n#define USART_ISR_PE_Pos                (0U)\r\n#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */\r\n#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */\r\n#define USART_ISR_FE_Pos                (1U)\r\n#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */\r\n#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */\r\n#define USART_ISR_NE_Pos                (2U)\r\n#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */\r\n#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */\r\n#define USART_ISR_ORE_Pos               (3U)\r\n#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */\r\n#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */\r\n#define USART_ISR_IDLE_Pos              (4U)\r\n#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */\r\n#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */\r\n#define USART_ISR_RXNE_RXFNE_Pos        (5U)\r\n#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */\r\n#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */\r\n#define USART_ISR_TC_Pos                (6U)\r\n#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */\r\n#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */\r\n#define USART_ISR_TXE_TXFNF_Pos         (7U)\r\n#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */\r\n#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */\r\n#define USART_ISR_LBDF_Pos              (8U)\r\n#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */\r\n#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */\r\n#define USART_ISR_CTSIF_Pos             (9U)\r\n#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */\r\n#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */\r\n#define USART_ISR_CTS_Pos               (10U)\r\n#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */\r\n#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */\r\n#define USART_ISR_RTOF_Pos              (11U)\r\n#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */\r\n#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */\r\n#define USART_ISR_EOBF_Pos              (12U)\r\n#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */\r\n#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */\r\n#define USART_ISR_UDR_Pos               (13U)\r\n#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */\r\n#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */\r\n#define USART_ISR_ABRE_Pos              (14U)\r\n#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */\r\n#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */\r\n#define USART_ISR_ABRF_Pos              (15U)\r\n#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */\r\n#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */\r\n#define USART_ISR_BUSY_Pos              (16U)\r\n#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */\r\n#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */\r\n#define USART_ISR_CMF_Pos               (17U)\r\n#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */\r\n#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */\r\n#define USART_ISR_SBKF_Pos              (18U)\r\n#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */\r\n#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */\r\n#define USART_ISR_RWU_Pos               (19U)\r\n#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */\r\n#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */\r\n#define USART_ISR_WUF_Pos               (20U)\r\n#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */\r\n#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */\r\n#define USART_ISR_TEACK_Pos             (21U)\r\n#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */\r\n#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */\r\n#define USART_ISR_REACK_Pos             (22U)\r\n#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */\r\n#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */\r\n#define USART_ISR_TXFE_Pos              (23U)\r\n#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */\r\n#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */\r\n#define USART_ISR_RXFF_Pos              (24U)\r\n#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */\r\n#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */\r\n#define USART_ISR_TCBGT_Pos             (25U)\r\n#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */\r\n#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */\r\n#define USART_ISR_RXFT_Pos              (26U)\r\n#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */\r\n#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */\r\n#define USART_ISR_TXFT_Pos              (27U)\r\n#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */\r\n#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */\r\n\r\n/*******************  Bit definition for USART_ICR register  ******************/\r\n#define USART_ICR_PECF_Pos              (0U)\r\n#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */\r\n#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */\r\n#define USART_ICR_FECF_Pos              (1U)\r\n#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */\r\n#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */\r\n#define USART_ICR_NECF_Pos              (2U)\r\n#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */\r\n#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */\r\n#define USART_ICR_ORECF_Pos             (3U)\r\n#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */\r\n#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */\r\n#define USART_ICR_IDLECF_Pos            (4U)\r\n#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */\r\n#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */\r\n#define USART_ICR_TXFECF_Pos            (5U)\r\n#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */\r\n#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */\r\n#define USART_ICR_TCCF_Pos              (6U)\r\n#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */\r\n#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */\r\n#define USART_ICR_TCBGTCF_Pos           (7U)\r\n#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */\r\n#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */\r\n#define USART_ICR_LBDCF_Pos             (8U)\r\n#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */\r\n#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */\r\n#define USART_ICR_CTSCF_Pos             (9U)\r\n#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */\r\n#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */\r\n#define USART_ICR_RTOCF_Pos             (11U)\r\n#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */\r\n#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */\r\n#define USART_ICR_EOBCF_Pos             (12U)\r\n#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */\r\n#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */\r\n#define USART_ICR_UDRCF_Pos             (13U)\r\n#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */\r\n#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */\r\n#define USART_ICR_CMCF_Pos              (17U)\r\n#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */\r\n#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */\r\n#define USART_ICR_WUCF_Pos              (20U)\r\n#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */\r\n#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */\r\n\r\n/*******************  Bit definition for USART_RDR register  ******************/\r\n#define USART_RDR_RDR_Pos               (0U)\r\n#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */\r\n#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */\r\n\r\n/*******************  Bit definition for USART_TDR register  ******************/\r\n#define USART_TDR_TDR_Pos               (0U)\r\n#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */\r\n#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */\r\n\r\n/*******************  Bit definition for USART_PRESC register  ******************/\r\n#define USART_PRESC_PRESCALER_Pos       (0U)\r\n#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */\r\n#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */\r\n#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */\r\n#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */\r\n#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */\r\n#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*           Single Wire Protocol Master Interface (SWPMI)                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for SWPMI_CR register   ********************/\r\n#define SWPMI_CR_RXDMA_Pos       (0U)\r\n#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */\r\n#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */\r\n#define SWPMI_CR_TXDMA_Pos       (1U)\r\n#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */\r\n#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */\r\n#define SWPMI_CR_RXMODE_Pos      (2U)\r\n#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */\r\n#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */\r\n#define SWPMI_CR_TXMODE_Pos      (3U)\r\n#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */\r\n#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */\r\n#define SWPMI_CR_LPBK_Pos        (4U)\r\n#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */\r\n#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */\r\n#define SWPMI_CR_SWPACT_Pos      (5U)\r\n#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */\r\n#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */\r\n#define SWPMI_CR_DEACT_Pos       (10U)\r\n#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */\r\n#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */\r\n#define SWPMI_CR_SWPEN_Pos       (11U)\r\n#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */\r\n#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */\r\n\r\n/*******************  Bit definition for SWPMI_BRR register  ********************/\r\n#define SWPMI_BRR_BR_Pos         (0U)\r\n#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */\r\n#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */\r\n\r\n/*******************  Bit definition for SWPMI_ISR register  ********************/\r\n#define SWPMI_ISR_RXBFF_Pos      (0U)\r\n#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */\r\n#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */\r\n#define SWPMI_ISR_TXBEF_Pos      (1U)\r\n#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */\r\n#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */\r\n#define SWPMI_ISR_RXBERF_Pos     (2U)\r\n#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */\r\n#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */\r\n#define SWPMI_ISR_RXOVRF_Pos     (3U)\r\n#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */\r\n#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */\r\n#define SWPMI_ISR_TXUNRF_Pos     (4U)\r\n#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */\r\n#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */\r\n#define SWPMI_ISR_RXNE_Pos       (5U)\r\n#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */\r\n#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */\r\n#define SWPMI_ISR_TXE_Pos        (6U)\r\n#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */\r\n#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */\r\n#define SWPMI_ISR_TCF_Pos        (7U)\r\n#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */\r\n#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */\r\n#define SWPMI_ISR_SRF_Pos        (8U)\r\n#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */\r\n#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */\r\n#define SWPMI_ISR_SUSP_Pos       (9U)\r\n#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */\r\n#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */\r\n#define SWPMI_ISR_DEACTF_Pos     (10U)\r\n#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */\r\n#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */\r\n#define SWPMI_ISR_RDYF_Pos       (11U)\r\n#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */\r\n#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */\r\n\r\n/*******************  Bit definition for SWPMI_ICR register  ********************/\r\n#define SWPMI_ICR_CRXBFF_Pos     (0U)\r\n#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */\r\n#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */\r\n#define SWPMI_ICR_CTXBEF_Pos     (1U)\r\n#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */\r\n#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */\r\n#define SWPMI_ICR_CRXBERF_Pos    (2U)\r\n#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */\r\n#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */\r\n#define SWPMI_ICR_CRXOVRF_Pos    (3U)\r\n#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */\r\n#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */\r\n#define SWPMI_ICR_CTXUNRF_Pos    (4U)\r\n#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */\r\n#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */\r\n#define SWPMI_ICR_CTCF_Pos       (7U)\r\n#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */\r\n#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */\r\n#define SWPMI_ICR_CSRF_Pos       (8U)\r\n#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */\r\n#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */\r\n#define SWPMI_ICR_CRDYF_Pos      (11U)\r\n#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */\r\n#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */\r\n\r\n/*******************  Bit definition for SWPMI_IER register  ********************/\r\n#define SWPMI_IER_RXBFIE_Pos     (0U)\r\n#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */\r\n#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */\r\n#define SWPMI_IER_TXBEIE_Pos     (1U)\r\n#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */\r\n#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */\r\n#define SWPMI_IER_RXBERIE_Pos    (2U)\r\n#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */\r\n#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */\r\n#define SWPMI_IER_RXOVRIE_Pos    (3U)\r\n#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */\r\n#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */\r\n#define SWPMI_IER_TXUNRIE_Pos    (4U)\r\n#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */\r\n#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */\r\n#define SWPMI_IER_RIE_Pos        (5U)\r\n#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */\r\n#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */\r\n#define SWPMI_IER_TIE_Pos        (6U)\r\n#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */\r\n#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */\r\n#define SWPMI_IER_TCIE_Pos       (7U)\r\n#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */\r\n#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */\r\n#define SWPMI_IER_SRIE_Pos       (8U)\r\n#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */\r\n#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */\r\n#define SWPMI_IER_RDYIE_Pos      (11U)\r\n#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */\r\n#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */\r\n\r\n/*******************  Bit definition for SWPMI_RFL register  ********************/\r\n#define SWPMI_RFL_RFL_Pos        (0U)\r\n#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */\r\n#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */\r\n#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\r\n\r\n/*******************  Bit definition for SWPMI_TDR register  ********************/\r\n#define SWPMI_TDR_TD_Pos         (0U)\r\n#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */\r\n#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */\r\n\r\n/*******************  Bit definition for SWPMI_RDR register  ********************/\r\n#define SWPMI_RDR_RD_Pos         (0U)\r\n#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */\r\n#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */\r\n\r\n\r\n/*******************  Bit definition for SWPMI_OR register  ********************/\r\n#define SWPMI_OR_TBYP_Pos        (0U)\r\n#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */\r\n#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */\r\n#define SWPMI_OR_CLASS_Pos       (1U)\r\n#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */\r\n#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            Window WATCHDOG                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for WWDG_CR register  ********************/\r\n#define WWDG_CR_T_Pos           (0U)\r\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */\r\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */\r\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */\r\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */\r\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */\r\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */\r\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */\r\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */\r\n\r\n#define WWDG_CR_WDGA_Pos        (7U)\r\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */\r\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\r\n\r\n/*******************  Bit definition for WWDG_CFR register  *******************/\r\n#define WWDG_CFR_W_Pos          (0U)\r\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */\r\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\r\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */\r\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */\r\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */\r\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */\r\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */\r\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */\r\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */\r\n\r\n#define WWDG_CFR_EWI_Pos        (9U)\r\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */\r\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\r\n\r\n#define WWDG_CFR_WDGTB_Pos      (11U)\r\n#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */\r\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */\r\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */\r\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */\r\n#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */\r\n\r\n/*******************  Bit definition for WWDG_SR register  ********************/\r\n#define WWDG_SR_EWIF_Pos        (0U)\r\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */\r\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                DBG                                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*********************************  DEVICE ID  ********************************/\r\n#define STM32H7_DEV_ID           0x483UL\r\n\r\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\r\n#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)\r\n#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r\n#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk\r\n#define DBGMCU_IDCODE_REV_ID_Pos          (16U)\r\n#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r\n#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk\r\n\r\n/********************  Bit definition for DBGMCU_CR register  *****************/\r\n#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)\r\n#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk\r\n#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)\r\n#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */\r\n#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk\r\n#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)\r\n#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */\r\n#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk\r\n#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)\r\n#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */\r\n#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk\r\n#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)\r\n#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */\r\n#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk\r\n#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)\r\n#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */\r\n#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk\r\n#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)\r\n#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */\r\n#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk\r\n#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)\r\n#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */\r\n#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk\r\n#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)\r\n#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */\r\n#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk\r\n\r\n/********************  Bit definition for APB3FZ1 register  ************/\r\n#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)\r\n#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */\r\n#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk\r\n/********************  Bit definition for APB1LFZ1 register  ************/\r\n#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)\r\n#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */\r\n#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)\r\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */\r\n#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk\r\n#define DBGMCU_APB1LFZ1_DBG_I2C5_Pos      (25U)\r\n#define DBGMCU_APB1LFZ1_DBG_I2C5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C5_Pos) /*!< 0x02000000 */\r\n#define DBGMCU_APB1LFZ1_DBG_I2C5          DBGMCU_APB1LFZ1_DBG_I2C5_Msk\r\n\r\n/********************  Bit definition for APB1HFZ1 register  ************/\r\n#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)\r\n#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */\r\n#define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk\r\n#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)\r\n#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */\r\n#define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk\r\n/********************  Bit definition for APB2FZ1 register  ************/\r\n#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk\r\n#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)\r\n#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */\r\n#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk\r\n/********************  Bit definition for APB4FZ1 register  ************/\r\n#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)\r\n#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */\r\n#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */\r\n#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk\r\n#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)\r\n#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */\r\n#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk\r\n#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)\r\n#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */\r\n#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk\r\n/********************  Bit definition for DBGMCU_PIDR4 register  ************/\r\n#define DBGMCU_PIDR4_JEP106CON_Pos        (0U)\r\n#define DBGMCU_PIDR4_JEP106CON_Msk        (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos) /*!< 0x0000000F */\r\n#define DBGMCU_PIDR4_JEP106CON            DBGMCU_PIDR4_JEP106CON_Msk\r\n#define DBGMCU_PIDR4_4KCOUNT_Pos          (4U)\r\n#define DBGMCU_PIDR4_4KCOUNT_Msk          (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)   /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR4_4KCOUNT              DBGMCU_PIDR4_4KCOUNT_Msk\r\n/********************  Bit definition for DBGMCU_PIDR0 register  ************/\r\n#define DBGMCU_PIDR0_PARTNUM_Pos        (0U)\r\n#define DBGMCU_PIDR0_PARTNUM_Msk        (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_PIDR0_PARTNUM            DBGMCU_PIDR0_PARTNUM_Msk\r\n/********************  Bit definition for DBGMCU_PIDR1 register  ************/\r\n#define DBGMCU_PIDR1_PARTNUM_Pos        (0U)\r\n#define DBGMCU_PIDR1_PARTNUM_Msk        (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)  /*!< 0x0000000F */\r\n#define DBGMCU_PIDR1_PARTNUM            DBGMCU_PIDR1_PARTNUM_Msk\r\n#define DBGMCU_PIDR1_JEP106ID_Pos       (4U)\r\n#define DBGMCU_PIDR1_JEP106ID_Msk       (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR1_JEP106ID           DBGMCU_PIDR1_JEP106ID_Msk\r\n/********************  Bit definition for DBGMCU_PIDR2 register  ************/\r\n#define DBGMCU_PIDR2_JEP106ID_Pos        (0U)\r\n#define DBGMCU_PIDR2_JEP106ID_Msk        (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)  /*!< 0x00000007 */\r\n#define DBGMCU_PIDR2_JEP106ID            DBGMCU_PIDR2_JEP106ID_Msk\r\n#define DBGMCU_PIDR2_JEDEC_Pos           (3U)\r\n#define DBGMCU_PIDR2_JEDEC_Msk           (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)  /*!< 0x00000008 */\r\n#define DBGMCU_PIDR2_JEDEC               DBGMCU_PIDR2_JEDEC_Msk\r\n#define DBGMCU_PIDR2_REVISION_Pos        (4U)\r\n#define DBGMCU_PIDR2_REVISION_Msk        (0xFUL << DBGMCU_PIDR2_REVISION_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR2_REVISION            DBGMCU_PIDR2_REVISION_Msk\r\n/********************  Bit definition for DBGMCU_PIDR3 register  ************/\r\n#define DBGMCU_PIDR3_CMOD_Pos            (0U)\r\n#define DBGMCU_PIDR3_CMOD_Msk            (0xFUL << DBGMCU_PIDR3_CMOD_Pos)  /*!< 0x0000000F */\r\n#define DBGMCU_PIDR3_CMOD                DBGMCU_PIDR3_CMOD_Msk\r\n#define DBGMCU_PIDR3_REVAND_Pos          (4U)\r\n#define DBGMCU_PIDR3_REVAND_Msk          (0xFUL << DBGMCU_PIDR3_REVAND_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_PIDR3_REVAND              DBGMCU_PIDR3_REVAND_Msk\r\n/********************  Bit definition for DBGMCU_CIDR0 register  ************/\r\n#define DBGMCU_CIR0_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR0_PREAMBLE_Msk         (0xFFUL << DBGMCU_CIR0_PREAMBLE_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_CIR0_PREAMBLE             DBGMCU_CIR0_PREAMBLE_Msk\r\n/********************  Bit definition for DBGMCU_CIDR1 register  ************/\r\n#define DBGMCU_CIR1_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR1_PREAMBLE_Msk         (0xFUL << DBGMCU_CIR1_PREAMBLE_Pos)  /*!< 0x0000000F */\r\n#define DBGMCU_CIR1_PREAMBLE             DBGMCU_CIR1_PREAMBLE_Msk\r\n#define DBGMCU_CIR1_CLASS_Pos            (4U)\r\n#define DBGMCU_CIR1_CLASS_Msk            (0xFUL << DBGMCU_CIR1_CLASS_Pos) /*!< 0x000000F0 */\r\n#define DBGMCU_CIR1_CLASS                DBGMCU_CIR1_CLASS_Msk\r\n/********************  Bit definition for DBGMCU_CIDR2 register  ************/\r\n#define DBGMCU_CIR2_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR2_PREAMBLE_Msk         (0xFFUL << DBGMCU_CIR2_PREAMBLE_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_CIR2_PREAMBLE             DBGMCU_CIR2_PREAMBLE_Msk\r\n/********************  Bit definition for DBGMCU_CIDR3 register  ************/\r\n#define DBGMCU_CIR3_PREAMBLE_Pos         (0U)\r\n#define DBGMCU_CIR3_PREAMBLE_Msk         (0xFFUL << DBGMCU_CIR3_PREAMBLE_Pos) /*!< 0x000000FF */\r\n#define DBGMCU_CIR3_PREAMBLE             DBGMCU_CIR3_PREAMBLE_Msk\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             RAM ECC monitoring                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for RAMECC_IER register  ******************/\r\n#define RAMECC_IER_GECCDEBWIE_Pos         (3U)\r\n#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */\r\n#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */\r\n#define RAMECC_IER_GECCDEIE_Pos           (2U)\r\n#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */\r\n#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */\r\n#define RAMECC_IER_GECCSEIE_Pos           (1U)\r\n#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */\r\n#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */\r\n#define RAMECC_IER_GIE_Pos                (0U)\r\n#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */\r\n#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */\r\n\r\n/*******************  Bit definition for RAMECC_CR register  ******************/\r\n#define RAMECC_CR_ECCELEN_Pos             (5U)\r\n#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */\r\n#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */\r\n#define RAMECC_CR_ECCDEBWIE_Pos           (4U)\r\n#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */\r\n#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */\r\n#define RAMECC_CR_ECCDEIE_Pos             (3U)\r\n#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */\r\n#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */\r\n#define RAMECC_CR_ECCSEIE_Pos             (2U)\r\n#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */\r\n#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */\r\n\r\n/*******************  Bit definition for RAMECC_SR register  ******************/\r\n#define RAMECC_SR_DEBWDF_Pos             (2U)\r\n#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */\r\n#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */\r\n#define RAMECC_SR_DEDF_Pos               (1U)\r\n#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */\r\n#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */\r\n#define RAMECC_SR_SEDCF_Pos              (0U)\r\n#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */\r\n#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */\r\n\r\n/******************  Bit definition for RAMECC_FAR register  ******************/\r\n#define RAMECC_FAR_FADD_Pos              (0U)\r\n#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */\r\n#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */\r\n\r\n/******************  Bit definition for RAMECC_FDRL register  *****************/\r\n#define RAMECC_FAR_FDATAL_Pos            (0U)\r\n#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */\r\n#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */\r\n\r\n/******************  Bit definition for RAMECC_FDRH register  *****************/\r\n#define RAMECC_FAR_FDATAH_Pos            (0U)\r\n#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */\r\n#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */\r\n\r\n/*****************  Bit definition for RAMECC_FECR register  ******************/\r\n#define RAMECC_FECR_FEC_Pos              (0U)\r\n#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */\r\n#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                MDIOS                                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for MDIOS_CR register  *******************/\r\n#define MDIOS_CR_EN_Pos                (0U)\r\n#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */\r\n#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */\r\n#define MDIOS_CR_WRIE_Pos              (1U)\r\n#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */\r\n#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */\r\n#define MDIOS_CR_RDIE_Pos              (2U)\r\n#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */\r\n#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */\r\n#define MDIOS_CR_EIE_Pos               (3U)\r\n#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */\r\n#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */\r\n#define MDIOS_CR_DPC_Pos               (7U)\r\n#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */\r\n#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */\r\n#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)\r\n#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */\r\n#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */\r\n#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */\r\n#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */\r\n#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */\r\n#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */\r\n#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */\r\n\r\n/********************  Bit definition for MDIOS_SR register  *******************/\r\n#define MDIOS_SR_PERF_Pos              (0U)\r\n#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */\r\n#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/\r\n#define MDIOS_SR_SERF_Pos              (1U)\r\n#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */\r\n#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */\r\n#define MDIOS_SR_TERF_Pos              (2U)\r\n#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */\r\n#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */\r\n\r\n/********************  Bit definition for MDIOS_CLRFR register  *******************/\r\n#define MDIOS_SR_CPERF_Pos             (0U)\r\n#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */\r\n#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */\r\n#define MDIOS_SR_CSERF_Pos             (1U)\r\n#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */\r\n#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */\r\n#define MDIOS_SR_CTERF_Pos             (2U)\r\n#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */\r\n#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                       USB_OTG                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/\r\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\r\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\r\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\r\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\r\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\r\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\r\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\r\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\r\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\r\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\r\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\r\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\r\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\r\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\r\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\r\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\r\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\r\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\r\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\r\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\r\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\r\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\r\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\r\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\r\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\r\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\r\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\r\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\r\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\r\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\r\n\r\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\r\n\r\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\r\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\r\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\r\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\r\n\r\n/********************  Bit definition forUSB_OTG_DCFG register  ********************/\r\n\r\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\r\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\r\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\r\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\r\n\r\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\r\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\r\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r\n\r\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\r\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\r\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r\n\r\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\r\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\r\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_PCGCR register  ********************/\r\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\r\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\r\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\r\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\r\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\r\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\r\n\r\n/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/\r\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\r\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\r\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\r\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\r\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\r\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\r\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\r\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\r\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\r\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\r\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\r\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\r\n\r\n/********************  Bit definition forUSB_OTG_DCTL register  ********************/\r\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\r\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\r\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\r\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\r\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\r\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\r\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\r\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\r\n\r\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\r\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\r\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\r\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\r\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\r\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\r\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\r\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\r\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\r\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\r\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\r\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\r\n\r\n/********************  Bit definition forUSB_OTG_HFIR register  ********************/\r\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\r\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\r\n\r\n/********************  Bit definition forUSB_OTG_HFNUM register  ********************/\r\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\r\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\r\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\r\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\r\n\r\n/********************  Bit definition forUSB_OTG_DSTS register  ********************/\r\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\r\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\r\n\r\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\r\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\r\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\r\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\r\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\r\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\r\n\r\n/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/\r\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\r\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\r\n\r\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\r\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\r\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\r\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\r\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\r\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\r\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\r\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\r\n\r\n/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/\r\n\r\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\r\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\r\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\r\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\r\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\r\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\r\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\r\n\r\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\r\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\r\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\r\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\r\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\r\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\r\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\r\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\r\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\r\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\r\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\r\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\r\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\r\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\r\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\r\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\r\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\r\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\r\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\r\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\r\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\r\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\r\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\r\n\r\n/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/\r\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\r\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\r\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\r\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\r\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\r\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\r\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\r\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\r\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\r\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\r\n\r\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\r\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\r\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\r\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\r\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\r\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/\r\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\r\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\r\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\r\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\r\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\r\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\r\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\r\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\r\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\r\n\r\n/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/\r\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\r\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\r\n\r\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\r\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r\n\r\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\r\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_HAINT register  ********************/\r\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\r\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/\r\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\r\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\r\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\r\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\r\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */\r\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\r\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\r\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\r\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\r\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\r\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\r\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\r\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\r\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\r\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\r\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\r\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\r\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */\r\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\r\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */\r\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\r\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */\r\n\r\n/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/\r\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\r\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\r\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\r\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\r\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\r\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\r\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\r\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\r\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\r\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\r\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\r\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\r\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\r\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\r\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\r\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\r\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\r\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\r\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\r\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\r\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\r\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\r\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\r\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\r\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\r\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\r\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\r\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\r\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\r\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\r\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\r\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\r\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\r\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\r\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\r\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\r\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\r\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\r\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\r\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\r\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\r\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\r\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\r\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\r\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\r\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\r\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\r\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\r\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\r\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\r\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\r\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\r\n\r\n/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/\r\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\r\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\r\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\r\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\r\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\r\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\r\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\r\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\r\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\r\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\r\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\r\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\r\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\r\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\r\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\r\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\r\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\r\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\r\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\r\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\r\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\r\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\r\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\r\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\r\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\r\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\r\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\r\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\r\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\r\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\r\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\r\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\r\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\r\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\r\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\r\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\r\n#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)\r\n#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */\r\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\r\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\r\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\r\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\r\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\r\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\r\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\r\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\r\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\r\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\r\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\r\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\r\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\r\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\r\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\r\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\r\n\r\n/********************  Bit definition forUSB_OTG_DAINT register  ********************/\r\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\r\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\r\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\r\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\r\n\r\n/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/\r\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\r\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\r\n\r\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\r\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\r\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\r\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\r\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\r\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\r\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/\r\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\r\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\r\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\r\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n\r\n#define USB_OTG_CHNUM_Pos                        (0U)\r\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */\r\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\r\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\r\n#define USB_OTG_BCNT_Pos                         (4U)\r\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\r\n\r\n#define USB_OTG_DPID_Pos                         (15U)\r\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */\r\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\r\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\r\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\r\n\r\n#define USB_OTG_PKTSTS_Pos                       (17U)\r\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\r\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\r\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\r\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\r\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\r\n\r\n#define USB_OTG_EPNUM_Pos                        (0U)\r\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */\r\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\r\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\r\n\r\n#define USB_OTG_FRMNUM_Pos                       (21U)\r\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\r\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\r\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\r\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\r\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/\r\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\r\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\r\n\r\n/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/\r\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\r\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n#define USB_OTG_NPTXFSA_Pos                      (0U)\r\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\r\n#define USB_OTG_NPTXFD_Pos                       (16U)\r\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\r\n#define USB_OTG_TX0FSA_Pos                       (0U)\r\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\r\n#define USB_OTG_TX0FD_Pos                        (16U)\r\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\r\n\r\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\r\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\r\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r\n\r\n/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/\r\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\r\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\r\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\r\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\r\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r\n\r\n/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/\r\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\r\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\r\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\r\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\r\n\r\n/********************  Bit definition forUSB_OTG_GCCFG register  ********************/\r\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\r\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\r\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\r\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\r\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\r\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\r\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\r\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\r\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\r\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\r\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\r\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\r\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\r\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\r\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\r\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\r\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\r\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\r\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\r\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */\r\n\r\n/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/\r\n#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)\r\n#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */\r\n#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)\r\n#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */\r\n\r\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r\n\r\n/********************  Bit definition forUSB_OTG_CID register  ********************/\r\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\r\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\r\n\r\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\r\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\r\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\r\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\r\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\r\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\r\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\r\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\r\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\r\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\r\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\r\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\r\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\r\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\r\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\r\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\r\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\r\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\r\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\r\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\r\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\r\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\r\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\r\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\r\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\r\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\r\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\r\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\r\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\r\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\r\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\r\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\r\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\r\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r\n\r\n/********************  Bit definition forUSB_OTG_HPRT register  ********************/\r\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\r\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\r\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\r\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\r\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\r\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\r\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\r\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\r\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\r\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\r\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\r\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\r\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\r\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */\r\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\r\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */\r\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\r\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */\r\n\r\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\r\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */\r\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\r\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */\r\n\r\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\r\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */\r\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r\n\r\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\r\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */\r\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\r\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\r\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\r\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\r\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\r\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\r\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\r\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r\n\r\n/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/\r\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\r\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */\r\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\r\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/\r\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\r\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */\r\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\r\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\r\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\r\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */\r\n\r\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\r\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */\r\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\r\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */\r\n\r\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\r\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */\r\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\r\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */\r\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\r\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\r\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\r\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\r\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */\r\n\r\n/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/\r\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\r\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\r\n\r\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\r\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\r\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\r\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\r\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\r\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\r\n\r\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\r\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\r\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r\n\r\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\r\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\r\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r\n\r\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\r\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\r\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\r\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\r\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\r\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\r\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\r\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\r\n\r\n/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/\r\n\r\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\r\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\r\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r\n\r\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\r\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\r\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r\n\r\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\r\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\r\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\r\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\r\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\r\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\r\n\r\n/********************  Bit definition forUSB_OTG_HCINT register  ********************/\r\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\r\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\r\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\r\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\r\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\r\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\r\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\r\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\r\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\r\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\r\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\r\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\r\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\r\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\r\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\r\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\r\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\r\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\r\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\r\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\r\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\r\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/\r\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\r\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\r\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\r\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\r\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\r\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\r\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\r\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\r\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\r\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\r\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\r\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\r\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\r\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\r\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\r\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\r\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\r\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\r\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\r\n\r\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\r\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\r\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\r\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\r\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\r\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\r\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\r\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\r\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\r\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\r\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\r\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\r\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\r\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\r\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\r\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\r\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\r\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\r\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\r\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\r\n\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\r\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\r\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\r\n/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/\r\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\r\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\r\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\r\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\r\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\r\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\r\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\r\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\r\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/\r\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\r\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\r\n\r\n/********************  Bit definition forUSB_OTG_HCDMA register  ********************/\r\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\r\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\r\n\r\n/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/\r\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\r\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\r\n\r\n/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/\r\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\r\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\r\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\r\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/\r\n\r\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\r\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\r\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\r\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\r\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\r\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\r\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\r\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\r\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\r\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\r\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\r\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\r\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\r\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\r\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\r\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\r\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\r\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/\r\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\r\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\r\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\r\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\r\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\r\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\r\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\r\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\r\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\r\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */\r\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\r\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\r\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\r\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\r\n#define USB_OTG_DOEPINT_BNA_Pos                  (9U)\r\n#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */\r\n#define USB_OTG_DOEPINT_BERR_Pos                 (12U)\r\n#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */\r\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\r\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\r\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\r\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\r\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\r\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\r\n\r\n/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/\r\n\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\r\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r\n\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for PCGCCTL register  ********************/\r\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\r\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\r\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\r\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\r\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_macros\r\n  * @{\r\n  */\r\n\r\n/******************************* ADC Instances ********************************/\r\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\r\n                                       ((INSTANCE) == ADC2) || \\\r\n                                       ((INSTANCE) == ADC3))\r\n\r\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r\n\r\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\\\r\n                                          ((INSTANCE) == ADC3_COMMON))\r\n\r\n/******************************* CORDIC Instances *****************************/\r\n#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)\r\n\r\n/******************************** FMAC Instances ******************************/\r\n#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)\r\n\r\n/******************************** COMP Instances ******************************/\r\n#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\\r\n                                       ((INSTANCE) == COMP2))\r\n\r\n#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)\r\n/******************** COMP Instances with window mode capability **************/\r\n#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\r\n\r\n/******************************** DTS Instances ******************************/\r\n#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)\r\n\r\n/******************************* CRC Instances ********************************/\r\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\r\n\r\n/******************************* DAC Instances ********************************/\r\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\r\n/******************************* DCMI Instances *******************************/\r\n#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r\n\r\n/******************************* DELAYBLOCK Instances *******************************/\r\n#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \\\r\n                                         ((INSTANCE) == DLYB_SDMMC2) || \\\r\n                                         ((INSTANCE) == DLYB_OCTOSPI1) || \\\r\n                                         ((INSTANCE) == DLYB_OCTOSPI2) )\r\n/****************************** DFSDM Instances *******************************/\r\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\r\n                                               ((INSTANCE) == DFSDM1_Filter1) || \\\r\n                                               ((INSTANCE) == DFSDM1_Filter2) || \\\r\n                                               ((INSTANCE) == DFSDM1_Filter3))\r\n\r\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel3) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel4) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel5) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel6) || \\\r\n                                                 ((INSTANCE) == DFSDM1_Channel7))\r\n/****************************** RAMECC Instances ******************************/\r\n#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \\\r\n                                                  ((INSTANCE) == RAMECC1_Monitor6)   || \\\r\n                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \\\r\n                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \\\r\n                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \\\r\n                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \\\r\n                                                  ((INSTANCE) == RAMECC3_Monitor2))\r\n\r\n/******************************** DMA Instances *******************************/\r\n#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream1)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream2)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream3)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream4)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream5)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream6)   || \\\r\n                                       ((INSTANCE) == DMA1_Stream7)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream0)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream1)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream2)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream3)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream4)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream5)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream6)   || \\\r\n                                       ((INSTANCE) == DMA2_Stream7)   || \\\r\n                                       ((INSTANCE) == BDMA_Channel0) || \\\r\n                                       ((INSTANCE) == BDMA_Channel1) || \\\r\n                                       ((INSTANCE) == BDMA_Channel2) || \\\r\n                                       ((INSTANCE) == BDMA_Channel3) || \\\r\n                                       ((INSTANCE) == BDMA_Channel4) || \\\r\n                                       ((INSTANCE) == BDMA_Channel5) || \\\r\n                                       ((INSTANCE) == BDMA_Channel6) || \\\r\n                                       ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** BDMA CHANNEL Instances ***************************/\r\n#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \\\r\n                                            ((INSTANCE) == BDMA_Channel1) || \\\r\n                                            ((INSTANCE) == BDMA_Channel2) || \\\r\n                                            ((INSTANCE) == BDMA_Channel3) || \\\r\n                                            ((INSTANCE) == BDMA_Channel4) || \\\r\n                                            ((INSTANCE) == BDMA_Channel5) || \\\r\n                                            ((INSTANCE) == BDMA_Channel6) || \\\r\n                                            ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** DMA DMAMUX ALL Instances ***************************/\r\n#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream1)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream2)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream3)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream4)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream5)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream6)    || \\\r\n                                               ((INSTANCE) == DMA1_Stream7)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream0)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream1)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream2)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream3)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream4)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream5)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream6)    || \\\r\n                                               ((INSTANCE) == DMA2_Stream7)    || \\\r\n                                               ((INSTANCE) == BDMA_Channel0)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel1)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel2)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel3)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel4)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel5)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel6)   || \\\r\n                                               ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** BDMA DMAMUX Instances ***************************/\r\n#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel1) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel2) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel3) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel4) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel5) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel6) || \\\r\n                                                    ((INSTANCE) == BDMA_Channel7))\r\n\r\n/****************************** DMA STREAM Instances ***************************/\r\n#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream1)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream2)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream3)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream4)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream5)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream6)   || \\\r\n                                          ((INSTANCE) == DMA1_Stream7)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream0)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream1)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream2)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream3)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream4)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream5)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream6)   || \\\r\n                                          ((INSTANCE) == DMA2_Stream7))\r\n\r\n/****************************** DMA DMAMUX Instances ***************************/\r\n#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream1)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream2)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream3)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream4)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream5)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream6)   || \\\r\n                                                  ((INSTANCE) == DMA1_Stream7)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream0)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream1)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream2)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream3)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream4)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream5)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream6)   || \\\r\n                                                  ((INSTANCE) == DMA2_Stream7))\r\n\r\n/******************************** DMA Request Generator Instances **************/\r\n#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \\\r\n                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \\\r\n                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))\r\n\r\n/******************************* DMA2D Instances *******************************/\r\n#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r\n\r\n/******************************* OTFDEC Instances ******************************/\r\n#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \\\r\n                                              ((__INSTANCE__) == OTFDEC2))\r\n\r\n/****************************** PSSI Instance *********************************/\r\n#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)\r\n\r\n/******************************** MDMA Request Generator Instances **************/\r\n#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel1)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel2)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel3)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel4)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel5)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel6)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel7)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel8)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel9)  || \\\r\n                                               ((INSTANCE) == MDMA_Channel10) || \\\r\n                                               ((INSTANCE) == MDMA_Channel11) || \\\r\n                                               ((INSTANCE) == MDMA_Channel12) || \\\r\n                                               ((INSTANCE) == MDMA_Channel13) || \\\r\n                                               ((INSTANCE) == MDMA_Channel14) || \\\r\n                                               ((INSTANCE) == MDMA_Channel15))\r\n\r\n\r\n/******************************* FDCAN Instances ******************************/\r\n#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \\\r\n                                             ((__INSTANCE__) == FDCAN2) || \\\r\n                                             ((__INSTANCE__) == FDCAN3))\r\n\r\n#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)\r\n\r\n/******************************* GPIO Instances *******************************/\r\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\r\n                                        ((INSTANCE) == GPIOB) || \\\r\n                                        ((INSTANCE) == GPIOC) || \\\r\n                                        ((INSTANCE) == GPIOD) || \\\r\n                                        ((INSTANCE) == GPIOE) || \\\r\n                                        ((INSTANCE) == GPIOF) || \\\r\n                                        ((INSTANCE) == GPIOG) || \\\r\n                                        ((INSTANCE) == GPIOH) || \\\r\n                                        ((INSTANCE) == GPIOJ) || \\\r\n                                        ((INSTANCE) == GPIOK))\r\n\r\n/******************************* GPIO AF Instances ****************************/\r\n#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\r\n\r\n/**************************** GPIO Lock Instances *****************************/\r\n/* On H7, all GPIO Bank support the Lock mechanism */\r\n#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\r\n\r\n/******************************** HSEM Instances *******************************/\r\n#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)\r\n#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */\r\n#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\r\n#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)\r\n\r\n#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/\r\n#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */\r\n\r\n#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */\r\n#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */\r\n\r\n#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */\r\n#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */\r\n\r\n/******************************** I2C Instances *******************************/\r\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\r\n                                       ((INSTANCE) == I2C2) || \\\r\n                                       ((INSTANCE) == I2C3) || \\\r\n                                       ((INSTANCE) == I2C4) || \\\r\n                                       ((INSTANCE) == I2C5))\r\n\r\n/****************************** SMBUS Instances *******************************/\r\n#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\r\n                                         ((INSTANCE) == I2C2) || \\\r\n                                         ((INSTANCE) == I2C3) || \\\r\n                                         ((INSTANCE) == I2C4) || \\\r\n                                         ((INSTANCE) == I2C5))\r\n\r\n/************** I2C Instances : wakeup capability from stop modes *************/\r\n#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\r\n\r\n/******************************** I2S Instances *******************************/\r\n#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \\\r\n                                         ((INSTANCE) == SPI2) || \\\r\n                                         ((INSTANCE) == SPI3))\r\n\r\n/****************************** LTDC Instances ********************************/\r\n#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)\r\n\r\n/******************************* RNG Instances ********************************/\r\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\r\n\r\n/****************************** RTC Instances *********************************/\r\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\r\n\r\n/****************************** SDMMC Instances *********************************/\r\n#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \\\r\n                                           ((_INSTANCE_) == SDMMC2))\r\n\r\n/******************************** SPI Instances *******************************/\r\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\r\n                                       ((INSTANCE) == SPI2) || \\\r\n                                       ((INSTANCE) == SPI3) || \\\r\n                                       ((INSTANCE) == SPI4) || \\\r\n                                       ((INSTANCE) == SPI5) || \\\r\n                                       ((INSTANCE) == SPI6))\r\n\r\n#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\r\n                                           ((INSTANCE) == SPI2) || \\\r\n                                           ((INSTANCE) == SPI3))\r\n\r\n/******************************** SWPMI Instances *****************************/\r\n#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)\r\n\r\n/****************** LPTIM Instances : All supported instances *****************/\r\n#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\r\n                                         ((INSTANCE) == LPTIM2) || \\\r\n                                         ((INSTANCE) == LPTIM3) || \\\r\n                                         ((INSTANCE) == LPTIM4) || \\\r\n                                         ((INSTANCE) == LPTIM5))\r\n\r\n/****************** LPTIM Instances : supporting encoder interface **************/\r\n#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\r\n                                                           ((INSTANCE) == LPTIM2))\r\n\r\n/****************** TIM Instances : All supported instances *******************/\r\n#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM6)   || \\\r\n                                         ((INSTANCE) == TIM7)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM12)  || \\\r\n                                         ((INSTANCE) == TIM13)  || \\\r\n                                         ((INSTANCE) == TIM14)  || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM16)  || \\\r\n                                         ((INSTANCE) == TIM17)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************* TIM Instances : at least 1 capture/compare channel *************/\r\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM12)  || \\\r\n                                         ((INSTANCE) == TIM13)  || \\\r\n                                         ((INSTANCE) == TIM14)  || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM16)  || \\\r\n                                         ((INSTANCE) == TIM17)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 2 capture/compare channels *************/\r\n#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM12)  || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 3 capture/compare channels *************/\r\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 4 capture/compare channels *************/\r\n#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : at least 5 capture/compare channels *************/\r\n#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM8))\r\n/************ TIM Instances : at least 6 capture/compare channels *************/\r\n#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM8))\r\n\r\n/******************** TIM Instances : Advanced-control timers *****************/\r\n#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                                ((__INSTANCE__) == TIM8))\r\n\r\n/******************** TIM Instances : Advanced-control timers *****************/\r\n\r\n/******************* TIM Instances : Timer input XOR function *****************/\r\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                         ((INSTANCE) == TIM2)   || \\\r\n                                         ((INSTANCE) == TIM3)   || \\\r\n                                         ((INSTANCE) == TIM4)   || \\\r\n                                         ((INSTANCE) == TIM5)   || \\\r\n                                         ((INSTANCE) == TIM8)   || \\\r\n                                         ((INSTANCE) == TIM15)  || \\\r\n                                         ((INSTANCE) == TIM23)  || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : DMA requests generation (UDE) *************/\r\n#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM2)   || \\\r\n                                           ((INSTANCE) == TIM3)   || \\\r\n                                           ((INSTANCE) == TIM4)   || \\\r\n                                           ((INSTANCE) == TIM5)   || \\\r\n                                           ((INSTANCE) == TIM6)   || \\\r\n                                           ((INSTANCE) == TIM7)   || \\\r\n                                           ((INSTANCE) == TIM8)   || \\\r\n                                           ((INSTANCE) == TIM15)  || \\\r\n                                           ((INSTANCE) == TIM16)  || \\\r\n                                           ((INSTANCE) == TIM17)  || \\\r\n                                           ((INSTANCE) == TIM23)  || \\\r\n                                           ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM8)   || \\\r\n                                            ((INSTANCE) == TIM15)  || \\\r\n                                            ((INSTANCE) == TIM16)  || \\\r\n                                            ((INSTANCE) == TIM17)  || \\\r\n                                            ((INSTANCE) == TIM23)  || \\\r\n                                            ((INSTANCE) == TIM24))\r\n\r\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\r\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM8)   || \\\r\n                                            ((INSTANCE) == TIM15))\r\n\r\n/******************** TIM Instances : DMA burst feature ***********************/\r\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM8))\r\n\r\n/*************** TIM Instances : external trigger reamp input available *******/\r\n#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM2)   || \\\r\n                                           ((INSTANCE) == TIM3)   || \\\r\n                                           ((INSTANCE) == TIM4)   || \\\r\n                                           ((INSTANCE) == TIM5)   || \\\r\n                                           ((INSTANCE) == TIM8)   || \\\r\n                                           ((INSTANCE) == TIM23)   || \\\r\n                                           ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : remapping capability **********************/\r\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\r\n                                         ((INSTANCE) == TIM2)  || \\\r\n                                         ((INSTANCE) == TIM3)  || \\\r\n                                         ((INSTANCE) == TIM5)  || \\\r\n                                         ((INSTANCE) == TIM8)  || \\\r\n                                         ((INSTANCE) == TIM16) || \\\r\n                                         ((INSTANCE) == TIM17) || \\\r\n                                         ((INSTANCE) == TIM23) || \\\r\n                                         ((INSTANCE) == TIM24))\r\n\r\n/*************** TIM Instances : external trigger reamp input available *******/\r\n#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)  || \\\r\n                                              ((INSTANCE) == TIM2)  || \\\r\n                                              ((INSTANCE) == TIM3)  || \\\r\n                                              ((INSTANCE) == TIM5)  || \\\r\n                                              ((INSTANCE) == TIM8)  || \\\r\n                                              ((INSTANCE) == TIM23) || \\\r\n                                              ((INSTANCE) == TIM24)))\r\n\r\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                            ((INSTANCE) == TIM2)   || \\\r\n                                            ((INSTANCE) == TIM3)   || \\\r\n                                            ((INSTANCE) == TIM4)   || \\\r\n                                            ((INSTANCE) == TIM5)   || \\\r\n                                            ((INSTANCE) == TIM6)   || \\\r\n                                            ((INSTANCE) == TIM7)   || \\\r\n                                            ((INSTANCE) == TIM8)   || \\\r\n                                            ((INSTANCE) == TIM12)  || \\\r\n                                            ((INSTANCE) == TIM15)  || \\\r\n                                            ((INSTANCE) == TIM23)  || \\\r\n                                            ((INSTANCE) == TIM24))\r\n\r\n/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/\r\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM2)   || \\\r\n                                           ((INSTANCE) == TIM3)   || \\\r\n                                           ((INSTANCE) == TIM4)   || \\\r\n                                           ((INSTANCE) == TIM5)   || \\\r\n                                           ((INSTANCE) == TIM8)   || \\\r\n                                           ((INSTANCE) == TIM12)  || \\\r\n                                           ((INSTANCE) == TIM15)  || \\\r\n                                           ((INSTANCE) == TIM23)  || \\\r\n                                           ((INSTANCE) == TIM24))\r\n\r\n/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/\r\n#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                           ((INSTANCE) == TIM8))\r\n\r\n/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/\r\n#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \\\r\n                                          ((INSTANCE) == TIM2)   || \\\r\n                                          ((INSTANCE) == TIM3)   || \\\r\n                                          ((INSTANCE) == TIM4)   || \\\r\n                                          ((INSTANCE) == TIM5)   || \\\r\n                                          ((INSTANCE) == TIM8)   || \\\r\n                                          ((INSTANCE) == TIM15)  || \\\r\n                                          ((INSTANCE) == TIM16)  || \\\r\n                                          ((INSTANCE) == TIM17)  || \\\r\n                                          ((INSTANCE) == TIM23)  || \\\r\n                                          ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting commutation event *************/\r\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \\\r\n                                                     ((INSTANCE) == TIM8)    || \\\r\n                                                     ((INSTANCE) == TIM15)   || \\\r\n                                                     ((INSTANCE) == TIM16)   || \\\r\n                                                     ((INSTANCE) == TIM17))\r\n\r\n/****************** TIM Instances : supporting encoder interface **************/\r\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \\\r\n                                                      ((__INSTANCE__) == TIM2)      || \\\r\n                                                      ((__INSTANCE__) == TIM3)      || \\\r\n                                                      ((__INSTANCE__) == TIM4)      || \\\r\n                                                      ((__INSTANCE__) == TIM5)      || \\\r\n                                                      ((__INSTANCE__) == TIM8)      || \\\r\n                                                      ((__INSTANCE__) == TIM23)      || \\\r\n                                                      ((__INSTANCE__) == TIM24))\r\n\r\n/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/\r\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\r\n                                                       ((INSTANCE) == TIM8))\r\n/******************* TIM Instances : output(s) available **********************/\r\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\r\n    ((((INSTANCE) == TIM1) &&                  \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\r\n     ||                                        \\\r\n     (((INSTANCE) == TIM2) &&                  \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM3) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1)||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM4) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM5) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n  ||                                           \\\r\n      (((INSTANCE) == TIM8) &&                 \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||         \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM12) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM13) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM14) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM15) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n     ((CHANNEL) == TIM_CHANNEL_2)))            \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM16) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n  ||                                           \\\r\n     (((INSTANCE) == TIM17) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\r\n     ||                                        \\\r\n     (((INSTANCE) == TIM23) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\r\n     ||                                        \\\r\n     (((INSTANCE) == TIM24) &&                 \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_4))))\r\n\r\n/****************** TIM Instances : supporting the break function *************/\r\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)\\\r\n      (((INSTANCE) == TIM1)    || \\\r\n      ((INSTANCE) == TIM8)     || \\\r\n       ((INSTANCE) == TIM15)   || \\\r\n       ((INSTANCE) == TIM16)   || \\\r\n       ((INSTANCE) == TIM17))\r\n\r\n/************** TIM Instances : supporting Break source selection *************/\r\n#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\r\n                                               ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting complementary output(s) ********/\r\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\r\n   ((((INSTANCE) == TIM1) &&                    \\\r\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\r\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\r\n ||                                             \\\r\n      (((INSTANCE) == TIM8) &&                  \\\r\n      (((CHANNEL) == TIM_CHANNEL_1) ||          \\\r\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\r\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\r\n    ||                                          \\\r\n    (((INSTANCE) == TIM15) &&                   \\\r\n      ((CHANNEL) == TIM_CHANNEL_1))             \\\r\n    ||                                          \\\r\n    (((INSTANCE) == TIM16) &&                   \\\r\n     ((CHANNEL) == TIM_CHANNEL_1))              \\\r\n    ||                                          \\\r\n    (((INSTANCE) == TIM17) &&                   \\\r\n     ((CHANNEL) == TIM_CHANNEL_1)))\r\n\r\n/****************** TIM Instances : supporting counting mode selection ********/\r\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting repetition counter *************/\r\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM16)   || \\\r\n   ((INSTANCE) == TIM17))\r\n\r\n/****************** TIM Instances : supporting synchronization ****************/\r\n#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\\r\n    (((__INSTANCE__) == TIM1)    || \\\r\n     ((__INSTANCE__) == TIM2)    || \\\r\n     ((__INSTANCE__) == TIM3)    || \\\r\n     ((__INSTANCE__) == TIM4)    || \\\r\n     ((__INSTANCE__) == TIM5)    || \\\r\n     ((__INSTANCE__) == TIM6)    || \\\r\n     ((__INSTANCE__) == TIM8)    || \\\r\n     ((__INSTANCE__) == TIM12)   || \\\r\n     ((__INSTANCE__) == TIM15)   || \\\r\n     ((__INSTANCE__) == TIM23)   || \\\r\n     ((__INSTANCE__) == TIM24))\r\n\r\n/****************** TIM Instances : supporting clock division *****************/\r\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM16)   || \\\r\n   ((INSTANCE) == TIM17)   || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting external clock mode 1 for ETRF input */\r\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting external clock mode 2 **********/\r\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\\\r\n (((INSTANCE) == TIM1)     || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3)    || \\\r\n   ((INSTANCE) == TIM4)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM8)    || \\\r\n   ((INSTANCE) == TIM15)   || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : supporting OCxREF clear *******************/\r\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM3))\r\n\r\n/****************** TIM Instances : TIM_32B_COUNTER ***************************/\r\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM2)    || \\\r\n   ((INSTANCE) == TIM5)    || \\\r\n   ((INSTANCE) == TIM23)   || \\\r\n   ((INSTANCE) == TIM24))\r\n\r\n/****************** TIM Instances : TIM_BKIN2 ***************************/\r\n#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\\\r\n  (((INSTANCE) == TIM1)    || \\\r\n   ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting Hall sensor interface **********/\r\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \\\r\n                                                             ((__INSTANCE__) == TIM2)  || \\\r\n                                                             ((__INSTANCE__) == TIM3)  || \\\r\n                                                             ((__INSTANCE__) == TIM4)  || \\\r\n                                                             ((__INSTANCE__) == TIM5)  || \\\r\n                                                             ((__INSTANCE__) == TIM15) || \\\r\n                                                             ((__INSTANCE__) == TIM8)  || \\\r\n                                                             ((__INSTANCE__) == TIM23) || \\\r\n                                                             ((__INSTANCE__) == TIM24))\r\n\r\n/******************** USART Instances : Synchronous mode **********************/\r\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                     ((INSTANCE) == USART2) || \\\r\n                                     ((INSTANCE) == USART3) || \\\r\n                                     ((INSTANCE) == USART6) || \\\r\n                                     ((INSTANCE) == USART10))\r\n\r\n/******************** USART Instances : SPI slave mode ************************/\r\n#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                              ((INSTANCE) == USART2) || \\\r\n                                              ((INSTANCE) == USART3) || \\\r\n                                              ((INSTANCE) == USART6) || \\\r\n                                              ((INSTANCE) == USART10))\r\n\r\n/******************** UART Instances : Asynchronous mode **********************/\r\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                    ((INSTANCE) == USART2) || \\\r\n                                    ((INSTANCE) == USART3) || \\\r\n                                    ((INSTANCE) == UART4)  || \\\r\n                                    ((INSTANCE) == UART5)  || \\\r\n                                    ((INSTANCE) == USART6) || \\\r\n                                    ((INSTANCE) == UART7)  || \\\r\n                                    ((INSTANCE) == UART8)  || \\\r\n                                    ((INSTANCE) == UART9)  || \\\r\n                                    ((INSTANCE) == USART10))\r\n\r\n/******************** UART Instances : FIFO mode.******************************/\r\n#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                         ((INSTANCE) == USART2) || \\\r\n                                         ((INSTANCE) == USART3) || \\\r\n                                         ((INSTANCE) == UART4)  || \\\r\n                                         ((INSTANCE) == UART5)  || \\\r\n                                         ((INSTANCE) == USART6) || \\\r\n                                         ((INSTANCE) == UART7)  || \\\r\n                                         ((INSTANCE) == UART8)  || \\\r\n                                         ((INSTANCE) == UART9)  || \\\r\n                                         ((INSTANCE) == USART10)|| \\\r\n                                         ((INSTANCE) == LPUART1))\r\n\r\n/****************** UART Instances : Auto Baud Rate detection *****************/\r\n#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                                            ((INSTANCE) == USART2) || \\\r\n                                                            ((INSTANCE) == USART3) || \\\r\n                                                            ((INSTANCE) == UART4)  || \\\r\n                                                            ((INSTANCE) == UART5)  || \\\r\n                                                            ((INSTANCE) == USART6) || \\\r\n                                                            ((INSTANCE) == UART7)  || \\\r\n                                                            ((INSTANCE) == UART8)  || \\\r\n                                                            ((INSTANCE) == UART9)  || \\\r\n                                                            ((INSTANCE) == USART10))\r\n\r\n/*********************** UART Instances : Driver Enable ***********************/\r\n#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                                  ((INSTANCE) == USART2) || \\\r\n                                                  ((INSTANCE) == USART3) || \\\r\n                                                  ((INSTANCE) == UART4)  || \\\r\n                                                  ((INSTANCE) == UART5)  || \\\r\n                                                  ((INSTANCE) == USART6) || \\\r\n                                                  ((INSTANCE) == UART7)  || \\\r\n                                                  ((INSTANCE) == UART8)  || \\\r\n                                                  ((INSTANCE) == UART9)  || \\\r\n                                                  ((INSTANCE) == USART10)|| \\\r\n                                                  ((INSTANCE) == LPUART1))\r\n\r\n/********************* UART Instances : Half-Duplex mode **********************/\r\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                               ((INSTANCE) == USART2) || \\\r\n                                               ((INSTANCE) == USART3) || \\\r\n                                               ((INSTANCE) == UART4)  || \\\r\n                                               ((INSTANCE) == UART5)  || \\\r\n                                               ((INSTANCE) == USART6) || \\\r\n                                               ((INSTANCE) == UART7)  || \\\r\n                                               ((INSTANCE) == UART8)  || \\\r\n                                               ((INSTANCE) == UART9)  || \\\r\n                                               ((INSTANCE) == USART10)|| \\\r\n                                               ((INSTANCE) == LPUART1))\r\n\r\n/******************* UART Instances : Hardware Flow control *******************/\r\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                           ((INSTANCE) == USART2) || \\\r\n                                           ((INSTANCE) == USART3) || \\\r\n                                           ((INSTANCE) == UART4)  || \\\r\n                                           ((INSTANCE) == UART5)  || \\\r\n                                           ((INSTANCE) == USART6) || \\\r\n                                           ((INSTANCE) == UART7)  || \\\r\n                                           ((INSTANCE) == UART8)  || \\\r\n                                           ((INSTANCE) == UART9)  || \\\r\n                                           ((INSTANCE) == USART10)|| \\\r\n                                           ((INSTANCE) == LPUART1))\r\n\r\n/************************* UART Instances : LIN mode **************************/\r\n#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                        ((INSTANCE) == USART2) || \\\r\n                                        ((INSTANCE) == USART3) || \\\r\n                                        ((INSTANCE) == UART4)  || \\\r\n                                        ((INSTANCE) == UART5)  || \\\r\n                                        ((INSTANCE) == USART6) || \\\r\n                                        ((INSTANCE) == UART7)  || \\\r\n                                        ((INSTANCE) == UART8)  || \\\r\n                                        ((INSTANCE) == UART9)  || \\\r\n                                        ((INSTANCE) == USART10))\r\n\r\n/****************** UART Instances : Wake-up from Stop mode *******************/\r\n#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                                    ((INSTANCE) == USART2) || \\\r\n                                                    ((INSTANCE) == USART3) || \\\r\n                                                    ((INSTANCE) == UART4)  || \\\r\n                                                    ((INSTANCE) == UART5)  || \\\r\n                                                    ((INSTANCE) == USART6) || \\\r\n                                                    ((INSTANCE) == UART7)  || \\\r\n                                                    ((INSTANCE) == UART8)  || \\\r\n                                                    ((INSTANCE) == UART9)  || \\\r\n                                                    ((INSTANCE) == USART10)|| \\\r\n                                                    ((INSTANCE) == LPUART1))\r\n\r\n/************************* UART Instances : IRDA mode *************************/\r\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                    ((INSTANCE) == USART2) || \\\r\n                                    ((INSTANCE) == USART3) || \\\r\n                                    ((INSTANCE) == UART4)  || \\\r\n                                    ((INSTANCE) == UART5)  || \\\r\n                                    ((INSTANCE) == USART6) || \\\r\n                                    ((INSTANCE) == UART7)  || \\\r\n                                    ((INSTANCE) == UART8)  || \\\r\n                                    ((INSTANCE) == UART9)  || \\\r\n                                    ((INSTANCE) == USART10))\r\n\r\n/********************* USART Instances : Smard card mode **********************/\r\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\r\n                                         ((INSTANCE) == USART2) || \\\r\n                                         ((INSTANCE) == USART3) || \\\r\n                                         ((INSTANCE) == USART6) ||\\\r\n                                         ((INSTANCE) == USART10))\r\n\r\n/****************************** LPUART Instance *******************************/\r\n#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)\r\n\r\n/****************************** IWDG Instances ********************************/\r\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)\r\n/****************************** USB Instances ********************************/\r\n#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)\r\n\r\n/****************************** WWDG Instances ********************************/\r\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)\r\n/****************************** MDIOS Instances ********************************/\r\n#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)\r\n\r\n/****************************** CEC Instances *********************************/\r\n#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r\n\r\n/****************************** SAI Instances ********************************/\r\n#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\\r\n                                       ((INSTANCE) == SAI1_Block_B) || \\\r\n                                       ((INSTANCE) == SAI4_Block_A) || \\\r\n                                       ((INSTANCE) == SAI4_Block_B))\r\n\r\n/****************************** SPDIFRX Instances ********************************/\r\n#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)\r\n\r\n/****************************** OPAMP Instances *******************************/\r\n#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\\r\n                                         ((INSTANCE) == OPAMP2))\r\n\r\n#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\r\n\r\n/*********************** USB OTG PCD Instances ********************************/\r\n#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)\r\n\r\n/*********************** USB OTG HCD Instances ********************************/\r\n#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)\r\n\r\n/******************************************************************************/\r\n/*  For a painless codes migration between the STM32H7xx device product       */\r\n/*  lines, or with STM32F7xx devices the aliases defined below are put        */\r\n/*   in place to overcome the differences in the interrupt handlers and IRQn  */\r\n/*   definitions. No need to update developed interrupt code when moving      */\r\n/*  across product lines within the same STM32H7 Family                       */\r\n/******************************************************************************/\r\n\r\n/* Aliases for __IRQn */\r\n//#define  HASH_RNG_IRQn                  RNG_IRQn\r\n//#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn\r\n#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn\r\n//#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn\r\n//#define  PVD_IRQn                       PVD_AVD_IRQn\r\n\r\n\r\n/* Aliases for DCMI/PSSI __IRQn */\r\n#define  DCMI_IRQn                      DCMI_PSSI_IRQn\r\n\r\n/* Aliases for __IRQHandler */\r\n//#define  HASH_RNG_IRQHandler           RNG_IRQHandler\r\n//#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler\r\n#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler\r\n//#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler\r\n//#define PVD_IRQHandler                 PVD_AVD_IRQHandler\r\n\r\n/* Aliases for COMP __IRQHandler */\r\n#define COMP_IRQHandler                COMP1_IRQHandler\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* STM32H735xx_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/stm32h7xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32h7xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.\r\n  *\r\n  *          The file is the unique include file that the application programmer\r\n  *          is using in the C source code, usually in main.c. This file contains:\r\n  *           - Configuration section that allows to select:\r\n  *              - The STM32H7xx device used in the target application\r\n  *              - To use or not the peripheral’s drivers in application code(i.e.\r\n  *                code will be based on direct access to peripheral’s registers\r\n  *                rather than drivers API), this option is controlled by\r\n  *                \"#define USE_HAL_DRIVER\"\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32h7xx\r\n  * @{\r\n  */\r\n\r\n#ifndef STM32H7xx_H\r\n#define STM32H7xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n\r\n/** @addtogroup Library_configuration_section\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief STM32 Family\r\n  */\r\n#if !defined  (STM32H7)\r\n#define STM32H7\r\n#endif /* STM32H7 */\r\n\r\n\r\n/* Uncomment the line below according to the target STM32H7 device used in your\r\n   application\r\n  */\r\n\r\n/* #if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \\\r\n    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \\\r\n    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ) && \\\r\n    !defined (STM32H735xx) && !defined (STM32H733xx)  && !defined (STM32H730xx) && !defined (STM32H730xxQ)  && !defined (STM32H725xx) && !defined (STM32H723xx) */\r\n  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */\r\n  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */\r\n  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */\r\n  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */\r\n  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */\r\n  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */\r\n  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */\r\n  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */\r\n  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */\r\n  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */\r\n  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */\r\n  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */\r\n  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */\r\n  /* #define STM32H735xx */   /*!< STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices */\r\n  /* #define STM32H733xx */   /*!< STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices */\r\n  /* #define STM32H730xx */   /*!< STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices */\r\n  /* #define STM32H730xxQ */  /*!< STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices */\r\n  /* #define STM32H725xx */   /*!< STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6  Devices */\r\n  /* #define STM32H723xx */   /*!< STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices */\r\n/* #endif */\r\n\r\n/*  Tip: To avoid modifying this file each time you need to switch between these\r\n        devices, you can define the device in your toolchain compiler preprocessor.\r\n  */\r\n\r\n#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)\r\n #error \"Dual core device, please select CORE_CM4 or CORE_CM7\"\r\n#endif\r\n\r\n#if !defined  (USE_HAL_DRIVER)\r\n/**\r\n * @brief Comment the line below if you will not use the peripherals drivers.\r\n   In this case, these drivers will not be included and the application code will\r\n   be based on direct access to peripherals registers\r\n   */\r\n  /*#define USE_HAL_DRIVER */\r\n#endif /* USE_HAL_DRIVER */\r\n\r\n/**\r\n  * @brief CMSIS Device version number V1.10.0\r\n  */\r\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x0A) /*!< [23:16] sub1 version */\r\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */\r\n#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */\r\n#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN     << 24)\\\r\n                                      |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\\\r\n                                      |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\\\r\n                                      |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Device_Included\r\n  * @{\r\n  */\r\n\r\n#if defined(STM32H743xx)\r\n  #include \"stm32h743xx.h\"\r\n// #elif defined(STM32H753xx)\r\n//   #include \"stm32h753xx.h\"\r\n// #elif defined(STM32H750xx)\r\n//   #include \"stm32h750xx.h\"\r\n// #elif defined(STM32H742xx)\r\n//   #include \"stm32h742xx.h\"\r\n// #elif defined(STM32H745xx)\r\n//   #include \"stm32h745xx.h\"\r\n// #elif defined(STM32H755xx)\r\n//   #include \"stm32h755xx.h\"\r\n// #elif defined(STM32H747xx)\r\n//   #include \"stm32h747xx.h\"\r\n// #elif defined(STM32H757xx)\r\n//   #include \"stm32h757xx.h\"\r\n// #elif defined(STM32H7B0xx)\r\n//   #include \"stm32h7b0xx.h\"\r\n// #elif defined(STM32H7B0xxQ)\r\n//   #include \"stm32h7b0xxq.h\"\r\n// #elif defined(STM32H7A3xx)\r\n//   #include \"stm32h7a3xx.h\"\r\n// #elif defined(STM32H7B3xx)\r\n//   #include \"stm32h7b3xx.h\"\r\n// #elif defined(STM32H7A3xxQ)\r\n//   #include \"stm32h7a3xxq.h\"\r\n// #elif defined(STM32H7B3xxQ)\r\n//   #include \"stm32h7b3xxq.h\"\r\n#elif defined(STM32H735xx)\r\n  #include \"stm32h735xx.h\"\r\n// #elif defined(STM32H733xx)\r\n//   #include \"stm32h733xx.h\"\r\n// #elif defined(STM32H730xx)\r\n//   #include \"stm32h730xx.h\"\r\n// #elif defined(STM32H730xxQ)\r\n//   #include \"stm32h730xxq.h\"\r\n#elif defined(STM32H725xx)\r\n  #include \"stm32h725xx.h\"\r\n// #elif defined(STM32H723xx)\r\n//   #include \"stm32h723xx.h\"\r\n#else\r\n #error \"Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)\"\r\n#endif\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_types\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  RESET = 0,\r\n  SET = !RESET\r\n} FlagStatus, ITStatus;\r\n\r\ntypedef enum\r\n{\r\n  DISABLE = 0,\r\n  ENABLE = !DISABLE\r\n} FunctionalState;\r\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r\n\r\ntypedef enum\r\n{\r\n  SUCCESS = 0,\r\n  ERROR = !SUCCESS\r\n} ErrorStatus;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup Exported_macros\r\n  * @{\r\n  */\r\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r\n\r\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r\n\r\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r\n\r\n#define CLEAR_REG(REG)        ((REG) = (0x0))\r\n\r\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r\n\r\n#define READ_REG(REG)         ((REG))\r\n\r\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r\n\r\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (USE_HAL_DRIVER)\r\n #include \"stm32h7xx_hal.h\"\r\n#endif /* USE_HAL_DRIVER */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* STM32H7xx_H */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/stm32h7xx_hal_def.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32h7xx_hal_def.h\r\n  * @author  MCD Application Team\r\n  * @brief   This file contains HAL common defines, enumeration, macros and\r\n  *          structures definitions.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef STM32H7xx_HAL_DEF\r\n#define STM32H7xx_HAL_DEF\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32h7xx.h\"\r\n//#include \"Legacy/stm32_hal_legacy.h\"\r\n//#include <stddef.h>\r\n//#include <math.h>\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  HAL Status structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_OK       = 0x00,\r\n  HAL_ERROR    = 0x01,\r\n  HAL_BUSY     = 0x02,\r\n  HAL_TIMEOUT  = 0x03\r\n} HAL_StatusTypeDef;\r\n\r\n/**\r\n  * @brief  HAL Lock structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_UNLOCKED = 0x00,\r\n  HAL_LOCKED   = 0x01\r\n} HAL_LockTypeDef;\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n#define HAL_MAX_DELAY      0xFFFFFFFFU\r\n\r\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))\r\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)\r\n\r\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \\\r\n                        do{                                                      \\\r\n                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\\r\n                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \\\r\n                          } while(0)\r\n\r\n#define UNUSED(x) ((void)(x))\r\n\r\n/** @brief Reset the Handle's State field.\r\n  * @param __HANDLE__: specifies the Peripheral Handle.\r\n  * @note  This macro can be used for the following purpose: \r\n  *          - When the Handle is declared as local variable; before passing it as parameter\r\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro \r\n  *            to set to 0 the Handle's \"State\" field.\r\n  *            Otherwise, \"State\" field may have any random value and the first time the function \r\n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\r\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\r\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\r\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\r\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\r\n  * @retval None\r\n  */\r\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)\r\n\r\n#if (USE_RTOS == 1)\r\n  #error \" USE_RTOS should be 0 in the current HAL release \"\r\n#else\r\n  #define __HAL_LOCK(__HANDLE__)                                           \\\r\n                                do{                                        \\\r\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\r\n                                    {                                      \\\r\n                                       return HAL_BUSY;                    \\\r\n                                    }                                      \\\r\n                                    else                                   \\\r\n                                    {                                      \\\r\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\r\n                                    }                                      \\\r\n                                  }while (0)\r\n\r\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\r\n                                  do{                                       \\\r\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\r\n                                    }while (0)\r\n#endif /* USE_RTOS */\r\n\r\n\r\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */\r\n  #ifndef __weak\r\n    #define __weak  __attribute__((weak))\r\n  #endif\r\n  #ifndef __packed\r\n    #define __packed  __attribute__((packed))\r\n  #endif\r\n#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r\n  #ifndef __weak\r\n    #define __weak   __attribute__((weak))\r\n  #endif /* __weak */\r\n  #ifndef __packed\r\n    #define __packed __attribute__((__packed__))\r\n  #endif /* __packed */\r\n#endif /* __GNUC__ */\r\n\r\n\r\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\r\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */\r\n  #ifndef __ALIGN_BEGIN\r\n    #define __ALIGN_BEGIN\r\n  #endif\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END      __attribute__ ((aligned (4)))\r\n  #endif\r\n#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END    __attribute__ ((aligned (4)))\r\n  #endif /* __ALIGN_END */\r\n  #ifndef __ALIGN_BEGIN\r\n    #define __ALIGN_BEGIN\r\n  #endif /* __ALIGN_BEGIN */\r\n#else\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END\r\n  #endif /* __ALIGN_END */\r\n  #ifndef __ALIGN_BEGIN\r\n    #if defined   (__CC_ARM)      /* ARM Compiler V5 */\r\n      #define __ALIGN_BEGIN    __align(4)\r\n    #elif defined (__ICCARM__)    /* IAR Compiler */\r\n      #define __ALIGN_BEGIN\r\n    #endif /* __CC_ARM */\r\n  #endif /* __ALIGN_BEGIN */\r\n#endif /* __GNUC__ */\r\n\r\n/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */\r\n#if defined   (__GNUC__)        /* GNU Compiler */\r\n  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))                                    \r\n#elif defined (__ICCARM__)    /* IAR Compiler */\r\n  #define ALIGN_32BYTES(buf) _Pragma(\"data_alignment=32\") buf  \r\n#elif defined   (__CC_ARM)      /* ARM Compiler */\r\n  #define ALIGN_32BYTES(buf) __align(32) buf  \r\n#endif\r\n\r\n/**\r\n  * @brief  __RAM_FUNC definition\r\n  */\r\n#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r\n/* ARM Compiler V4/V5 and V6\r\n   --------------------------\r\n   RAM functions are defined using the toolchain options.\r\n   Functions that are executed in RAM should reside in a separate source module.\r\n   Using the 'Options for File' dialog you can simply change the 'Code / Const'\r\n   area of a module to a memory space in physical RAM.\r\n   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r\n   dialog.\r\n*/\r\n#define __RAM_FUNC\r\n\r\n#elif defined ( __ICCARM__ )\r\n/* ICCARM Compiler\r\n   ---------------\r\n   RAM functions are defined using a specific toolchain keyword \"__ramfunc\".\r\n*/\r\n#define __RAM_FUNC __ramfunc\r\n\r\n#elif defined   (  __GNUC__  )\r\n/* GNU Compiler\r\n   ------------\r\n  RAM functions are defined using a specific toolchain attribute\r\n   \"__attribute__((section(\".RamFunc\")))\".\r\n*/\r\n#define __RAM_FUNC __attribute__((section(\".RamFunc\")))\r\n\r\n#endif\r\n\r\n/**\r\n  * @brief  __NOINLINE definition\r\n  */\r\n#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )\r\n/* ARM V4/V5 and V6 & GNU Compiler\r\n   -------------------------------\r\n*/\r\n#define __NOINLINE __attribute__ ( (noinline) )\r\n\r\n#elif defined ( __ICCARM__ )\r\n/* ICCARM Compiler\r\n   ---------------\r\n*/\r\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\r\n\r\n#endif\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* STM32H7xx_HAL_DEF */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/stm32h7xx_hal_gpio_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32h7xx_hal_gpio_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of GPIO HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef STM32H7xx_HAL_GPIO_EX_H\r\n#define STM32H7xx_HAL_GPIO_EX_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32h7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32H7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup GPIOEx GPIOEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief   AF 0 selection\r\n  */\r\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */\r\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */\r\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */\r\n#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */\r\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */\r\n#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */\r\n#define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */\r\n#define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */\r\n#define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */\r\n#define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */\r\n#if defined(DUAL_CORE)\r\n#define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */\r\n#define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */\r\n#endif /* DUAL_CORE */\r\n#endif /* PWR_CPUCR_PDDS_D2 */\r\n\r\n/**\r\n  * @brief   AF 1 selection\r\n  */\r\n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */\r\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */\r\n#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */\r\n#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */\r\n#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\r\n#if defined(HRTIM1)\r\n#define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */\r\n#endif /* HRTIM1 */\r\n#if defined(SAI4)\r\n#define GPIO_AF1_SAI4          ((uint8_t)0x01)  /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */\r\n#endif /* SAI4 */\r\n#define GPIO_AF1_FMC           ((uint8_t)0x01)  /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */\r\n\r\n\r\n/**\r\n  * @brief   AF 2 selection\r\n  */\r\n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */\r\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */\r\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */\r\n#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */\r\n#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */\r\n#if defined(HRTIM1)\r\n#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */\r\n#endif /* HRTIM1 */\r\n#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */\r\n#if defined(FDCAN3)\r\n#define GPIO_AF2_FDCAN3        ((uint8_t)0x02)  /* FDCAN3 Alternate Function mapping */\r\n#endif /*FDCAN3*/\r\n\r\n/**\r\n  * @brief   AF 3 selection\r\n  */\r\n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */\r\n#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */\r\n#define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */\r\n#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */\r\n#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */\r\n#define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */\r\n#define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */\r\n#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */\r\n#endif /* OCTOSPIM */\r\n#if defined(HRTIM1)\r\n#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */\r\n#endif /* HRTIM1 */\r\n#define GPIO_AF3_LTDC          ((uint8_t)0x03)  /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */\r\n\r\n/**\r\n  * @brief   AF 4 selection\r\n  */\r\n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */\r\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */\r\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */\r\n#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */\r\n#if defined(I2C5)\r\n#define GPIO_AF4_I2C5          ((uint8_t)0x04)  /* I2C5 Alternate Function mapping   */\r\n#endif /* I2C5*/\r\n#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */\r\n#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */\r\n#define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */\r\n#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */\r\n#if defined(USART10)\r\n#define GPIO_AF4_USART10       ((uint8_t)0x04)  /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */\r\n#endif /*USART10*/\r\n#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */\r\n#if defined(DFSDM2_BASE)\r\n#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */\r\n#endif /* DFSDM2_BASE */\r\n#define GPIO_AF4_DCMI          ((uint8_t)0x04)   /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */\r\n#if defined(PSSI)\r\n#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */\r\n#endif /* PSSI */\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF4_OCTOSPIM_P1   ((uint8_t)0x04)  /* OCTOSPI Manager Port 1 Alternate Function mapping  : available on STM32H72xxx/STM32H73xxx */\r\n#endif /* OCTOSPIM */\r\n\r\n/**\r\n  * @brief   AF 5 selection\r\n  */\r\n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */\r\n#define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */\r\n#if defined(FDCAN3)\r\n#define GPIO_AF5_FDCAN3        ((uint8_t)0x05)  /* FDCAN3 Alternate Function mapping */\r\n#endif /*FDCAN3*/\r\n\r\n/**\r\n  * @brief   AF 6 selection\r\n  */\r\n#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */\r\n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */\r\n#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */\r\n#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */\r\n#if defined(I2C5)\r\n#define GPIO_AF6_I2C5          ((uint8_t)0x06)  /* I2C5 Alternate Function mapping   */\r\n#endif /* I2C5*/\r\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */\r\n#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */\r\n#if defined(DFSDM2_BASE)\r\n#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */\r\n#endif /* DFSDM2_BASE */\r\n#if defined(SAI3)\r\n#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */\r\n#endif /* SAI3 */\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */\r\n#endif /* OCTOSPIM */\r\n\r\n/**\r\n  * @brief   AF 7 selection\r\n  */\r\n#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */\r\n#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */\r\n#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */\r\n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */\r\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */\r\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */\r\n#define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */\r\n#define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */\r\n#define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */\r\n\r\n/**\r\n  * @brief   AF 8 selection\r\n  */\r\n#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */\r\n#if defined(SAI2)\r\n#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */\r\n#endif /*SAI2*/\r\n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\r\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\r\n#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */\r\n#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */\r\n#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */\r\n#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */\r\n#if defined(SAI4)\r\n#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */\r\n#endif /* SAI4 */\r\n\r\n/**\r\n  * @brief   AF 9 selection\r\n  */\r\n#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */\r\n#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */\r\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */\r\n#define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */\r\n#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */\r\n#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */\r\n#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */\r\n#if defined(QUADSPI)\r\n#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */\r\n#endif /* QUADSPI */\r\n#if defined(SAI4)\r\n#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */\r\n#endif /* SAI4 */\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */\r\n#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */\r\n#endif /* OCTOSPIM */\r\n\r\n/**\r\n  * @brief   AF 10 selection\r\n  */\r\n#if defined(SAI2)\r\n#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */\r\n#endif /*SAI2*/\r\n#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */\r\n#if defined(USB2_OTG_FS)\r\n#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */\r\n#endif /*USB2_OTG_FS*/\r\n#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */\r\n#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */\r\n#if defined(LTDC)\r\n#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */\r\n#endif /*LTDC*/\r\n#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */\r\n#if defined(QUADSPI)\r\n#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */\r\n#endif /* QUADSPI */\r\n#if defined(SAI4)\r\n#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */\r\n#endif /* SAI4 */\r\n#if !defined(USB2_OTG_FS)\r\n#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */\r\n#endif /* !USB2_OTG_FS */\r\n#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */\r\n#endif /* OCTOSPIM */\r\n#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */\r\n#define GPIO_AF10_FMC           ((uint8_t)0x0A)  /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */\r\n\r\n/**\r\n  * @brief   AF 11 selection\r\n  */\r\n#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */\r\n#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */\r\n#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */\r\n#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */\r\n#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */\r\n#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */\r\n#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */\r\n#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */\r\n#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */\r\n#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */\r\n#if defined(DFSDM2_BASE)\r\n#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */\r\n#endif /* DFSDM2_BASE */\r\n#if defined(USART10)\r\n#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */\r\n#endif /* USART10 */\r\n#if defined(UART9)\r\n#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */\r\n#endif /* UART9 */\r\n#if defined(ETH)\r\n#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */\r\n#endif /* ETH */\r\n#if defined(LTDC)\r\n#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */\r\n#endif /*LTDC*/\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */\r\n#endif /* OCTOSPIM */\r\n\r\n/**\r\n  * @brief   AF 12 selection\r\n  */\r\n#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */\r\n#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */\r\n#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */\r\n#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */\r\n#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */\r\n#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */\r\n#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */\r\n#if defined(LTDC)\r\n#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */\r\n#endif /*LTDC*/\r\n#if defined(USB2_OTG_FS)\r\n#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */\r\n#endif /* USB2_OTG_FS */\r\n#if defined(OCTOSPIM)\r\n#define GPIO_AF12_OCTOSPIM_P1   ((uint8_t)0x0C)  /* OCTOSPI Manager Port 1 Alternate Function mapping */\r\n#endif /* OCTOSPIM */\r\n\r\n/**\r\n  * @brief   AF 13 selection\r\n  */\r\n#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */\r\n#define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */\r\n#define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */\r\n#if defined(LTDC)\r\n#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */\r\n#endif /*LTDC*/\r\n#if defined(DSI)\r\n#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */\r\n#endif /* DSI */\r\n#if defined(PSSI)\r\n#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */\r\n#endif /* PSSI */\r\n#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */\r\n#if defined(TIM23)\r\n#define GPIO_AF13_TIM23         ((uint8_t)0x0D)    /* TIM23 Alternate Function mapping */\r\n#endif  /*TIM23*/\r\n\r\n/**\r\n  * @brief   AF 14 selection\r\n  */\r\n#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */\r\n#define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */\r\n#if defined(TIM24)\r\n#define GPIO_AF14_TIM24        ((uint8_t)0x0E)   /* TIM24 Alternate Function mapping */\r\n#endif  /*TIM24*/\r\n\r\n/**\r\n  * @brief   AF 15 selection\r\n  */\r\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\r\n\r\n#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief   GPIO pin available on the platform\r\n  */\r\n/* Defines the available pins per GPIOs */\r\n#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All\r\n#if defined(GPIOI)\r\n#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All\r\n#endif /*GPIOI*/\r\n#if defined(GPIOI)\r\n#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All\r\n#else\r\n#define GPIOJ_PIN_AVAILABLE  (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 )\r\n#endif /* GPIOI */\r\n#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All\r\n#if defined(GPIOI)\r\n#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \\\r\n                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r\n#else\r\n#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 )\r\n#endif /* GPIOI */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\r\n  * @{\r\n  */\r\n#if defined(GPIOI)\r\n#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\\\r\n                                    ((__GPIOx__) == (GPIOB))? 1UL :\\\r\n                                    ((__GPIOx__) == (GPIOC))? 2UL :\\\r\n                                    ((__GPIOx__) == (GPIOD))? 3UL :\\\r\n                                    ((__GPIOx__) == (GPIOE))? 4UL :\\\r\n                                    ((__GPIOx__) == (GPIOF))? 5UL :\\\r\n                                    ((__GPIOx__) == (GPIOG))? 6UL :\\\r\n                                    ((__GPIOx__) == (GPIOH))? 7UL :\\\r\n                                    ((__GPIOx__) == (GPIOI))? 8UL :\\\r\n                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)\r\n#else\r\n#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\\\r\n                                    ((__GPIOx__) == (GPIOB))? 1UL :\\\r\n                                    ((__GPIOx__) == (GPIOC))? 2UL :\\\r\n                                    ((__GPIOx__) == (GPIOD))? 3UL :\\\r\n                                    ((__GPIOx__) == (GPIOE))? 4UL :\\\r\n                                    ((__GPIOx__) == (GPIOF))? 5UL :\\\r\n                                    ((__GPIOx__) == (GPIOG))? 6UL :\\\r\n                                    ((__GPIOx__) == (GPIOH))? 7UL :\\\r\n                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)\r\n#endif /* GPIOI */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* STM32H7xx_HAL_GPIO_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "panda/board/stm32h7/inc/system_stm32h7xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    system_stm32h7xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32h7xx_system\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Define to prevent recursive inclusion\r\n  */\r\n#ifndef SYSTEM_STM32H7XX_H\r\n#define SYSTEM_STM32H7XX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/** @addtogroup STM32H7xx_System_Includes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup STM32H7xx_System_Exported_types\r\n  * @{\r\n  */\r\n  /* This variable is updated in three ways:\r\n      1) by calling CMSIS function SystemCoreClockUpdate()\r\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r\n         Note: If you use this function to configure the system clock; then there\r\n               is no need to call the 2 first functions listed above, since SystemCoreClock\r\n               variable is updated automatically.\r\n  */\r\nextern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */\r\nextern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */\r\nextern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32H7xx_System_Exported_Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32H7xx_System_Exported_Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32H7xx_System_Exported_Functions\r\n  * @{\r\n  */\r\n\r\nextern void SystemInit(void);\r\nextern void SystemCoreClockUpdate(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* SYSTEM_STM32H7XX_H */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "panda/board/stm32h7/interrupt_handlers.h",
    "content": "// ********************* Bare interrupt handlers *********************\n// Interrupts for STM32H7x5\n\nvoid WWDG_IRQHandler(void) {handle_interrupt(WWDG_IRQn);}\nvoid PVD_AVD_IRQHandler(void) {handle_interrupt(PVD_AVD_IRQn);}\nvoid TAMP_STAMP_IRQHandler(void) {handle_interrupt(TAMP_STAMP_IRQn);}\nvoid RTC_WKUP_IRQHandler(void) {handle_interrupt(RTC_WKUP_IRQn);}\nvoid FLASH_IRQHandler(void) {handle_interrupt(FLASH_IRQn);}\nvoid RCC_IRQHandler(void) {handle_interrupt(RCC_IRQn);}\nvoid EXTI0_IRQHandler(void) {handle_interrupt(EXTI0_IRQn);}\nvoid EXTI1_IRQHandler(void) {handle_interrupt(EXTI1_IRQn);}\nvoid EXTI2_IRQHandler(void) {handle_interrupt(EXTI2_IRQn);}\nvoid EXTI3_IRQHandler(void) {handle_interrupt(EXTI3_IRQn);}\nvoid EXTI4_IRQHandler(void) {handle_interrupt(EXTI4_IRQn);}\nvoid DMA1_Stream0_IRQHandler(void) {handle_interrupt(DMA1_Stream0_IRQn);}\nvoid DMA1_Stream1_IRQHandler(void) {handle_interrupt(DMA1_Stream1_IRQn);}\nvoid DMA1_Stream2_IRQHandler(void) {handle_interrupt(DMA1_Stream2_IRQn);}\nvoid DMA1_Stream3_IRQHandler(void) {handle_interrupt(DMA1_Stream3_IRQn);}\nvoid DMA1_Stream4_IRQHandler(void) {handle_interrupt(DMA1_Stream4_IRQn);}\nvoid DMA1_Stream5_IRQHandler(void) {handle_interrupt(DMA1_Stream5_IRQn);}\nvoid DMA1_Stream6_IRQHandler(void) {handle_interrupt(DMA1_Stream6_IRQn);}\nvoid ADC_IRQHandler(void) {handle_interrupt(ADC_IRQn);}\nvoid EXTI9_5_IRQHandler(void) {handle_interrupt(EXTI9_5_IRQn);}\nvoid TIM1_BRK_IRQHandler(void) {handle_interrupt(TIM1_BRK_IRQn);}\nvoid TIM1_UP_TIM10_IRQHandler(void) {handle_interrupt(TIM1_UP_TIM10_IRQn);}\nvoid TIM1_TRG_COM_IRQHandler(void) {handle_interrupt(TIM1_TRG_COM_IRQn);}\nvoid TIM1_CC_IRQHandler(void) {handle_interrupt(TIM1_CC_IRQn);}\nvoid TIM2_IRQHandler(void) {handle_interrupt(TIM2_IRQn);}\nvoid TIM3_IRQHandler(void) {handle_interrupt(TIM3_IRQn);}\nvoid TIM4_IRQHandler(void) {handle_interrupt(TIM4_IRQn);}\nvoid I2C1_EV_IRQHandler(void) {handle_interrupt(I2C1_EV_IRQn);}\nvoid I2C1_ER_IRQHandler(void) {handle_interrupt(I2C1_ER_IRQn);}\nvoid I2C2_EV_IRQHandler(void) {handle_interrupt(I2C2_EV_IRQn);}\nvoid I2C2_ER_IRQHandler(void) {handle_interrupt(I2C2_ER_IRQn);}\nvoid SPI1_IRQHandler(void) {handle_interrupt(SPI1_IRQn);}\nvoid SPI2_IRQHandler(void) {handle_interrupt(SPI2_IRQn);}\nvoid USART1_IRQHandler(void) {handle_interrupt(USART1_IRQn);}\nvoid USART2_IRQHandler(void) {handle_interrupt(USART2_IRQn);}\nvoid USART3_IRQHandler(void) {handle_interrupt(USART3_IRQn);}\nvoid EXTI15_10_IRQHandler(void) {handle_interrupt(EXTI15_10_IRQn);}\nvoid RTC_Alarm_IRQHandler(void) {handle_interrupt(RTC_Alarm_IRQn);}\nvoid TIM8_BRK_TIM12_IRQHandler(void) {handle_interrupt(TIM8_BRK_TIM12_IRQn);}\nvoid TIM8_UP_TIM13_IRQHandler(void) {handle_interrupt(TIM8_UP_TIM13_IRQn);}\nvoid TIM8_TRG_COM_TIM14_IRQHandler(void) {handle_interrupt(TIM8_TRG_COM_TIM14_IRQn);}\nvoid TIM8_CC_IRQHandler(void) {handle_interrupt(TIM8_CC_IRQn);}\nvoid DMA1_Stream7_IRQHandler(void) {handle_interrupt(DMA1_Stream7_IRQn);}\nvoid TIM5_IRQHandler(void) {handle_interrupt(TIM5_IRQn);}\nvoid SPI3_IRQHandler(void) {handle_interrupt(SPI3_IRQn);}\nvoid UART4_IRQHandler(void) {handle_interrupt(UART4_IRQn);}\nvoid UART5_IRQHandler(void) {handle_interrupt(UART5_IRQn);}\nvoid TIM6_DAC_IRQHandler(void) {handle_interrupt(TIM6_DAC_IRQn);}\nvoid TIM7_IRQHandler(void) {handle_interrupt(TIM7_IRQn);}\nvoid DMA2_Stream0_IRQHandler(void) {handle_interrupt(DMA2_Stream0_IRQn);}\nvoid DMA2_Stream1_IRQHandler(void) {handle_interrupt(DMA2_Stream1_IRQn);}\nvoid DMA2_Stream2_IRQHandler(void) {handle_interrupt(DMA2_Stream2_IRQn);}\nvoid DMA2_Stream3_IRQHandler(void) {handle_interrupt(DMA2_Stream3_IRQn);}\nvoid DMA2_Stream4_IRQHandler(void) {handle_interrupt(DMA2_Stream4_IRQn);}\nvoid DMA2_Stream5_IRQHandler(void) {handle_interrupt(DMA2_Stream5_IRQn);}\nvoid DMA2_Stream6_IRQHandler(void) {handle_interrupt(DMA2_Stream6_IRQn);}\nvoid DMA2_Stream7_IRQHandler(void) {handle_interrupt(DMA2_Stream7_IRQn);}\nvoid USART6_IRQHandler(void) {handle_interrupt(USART6_IRQn);}\nvoid I2C3_EV_IRQHandler(void) {handle_interrupt(I2C3_EV_IRQn);}\nvoid I2C3_ER_IRQHandler(void) {handle_interrupt(I2C3_ER_IRQn);}\nvoid FDCAN1_IT0_IRQHandler(void) {handle_interrupt(FDCAN1_IT0_IRQn);}\nvoid FDCAN1_IT1_IRQHandler(void) {handle_interrupt(FDCAN1_IT1_IRQn);}\nvoid FDCAN2_IT0_IRQHandler(void) {handle_interrupt(FDCAN2_IT0_IRQn);}\nvoid FDCAN2_IT1_IRQHandler(void) {handle_interrupt(FDCAN2_IT1_IRQn);}\nvoid FDCAN3_IT0_IRQHandler(void) {handle_interrupt(FDCAN3_IT0_IRQn);}\nvoid FDCAN3_IT1_IRQHandler(void) {handle_interrupt(FDCAN3_IT1_IRQn);}\nvoid FDCAN_CAL_IRQHandler(void) {handle_interrupt(FDCAN_CAL_IRQn);}\nvoid OTG_HS_EP1_OUT_IRQHandler(void) {handle_interrupt(OTG_HS_EP1_OUT_IRQn);}\nvoid OTG_HS_EP1_IN_IRQHandler(void) {handle_interrupt(OTG_HS_EP1_IN_IRQn);}\nvoid OTG_HS_WKUP_IRQHandler(void) {handle_interrupt(OTG_HS_WKUP_IRQn);}\nvoid OTG_HS_IRQHandler(void) {handle_interrupt(OTG_HS_IRQn);}\n"
  },
  {
    "path": "panda/board/stm32h7/lladc.h",
    "content": "// 5VOUT_S = ADC12_INP5\n// VOLT_S = ADC1_INP2\n#define ADCCHAN_VOLTAGE 2\n\nvoid adc_init(void) {\n  ADC1->CR &= ~(ADC_CR_DEEPPWD); //Reset deep-power-down mode\n  ADC1->CR |= ADC_CR_ADVREGEN; // Enable ADC regulator\n  while(!(ADC1->ISR & ADC_ISR_LDORDY));\n\n  ADC1->CR &= ~(ADC_CR_ADCALDIF); // Choose single-ended calibration\n  ADC1->CR |= ADC_CR_ADCALLIN; // Lineriality calibration\n  ADC1->CR |= ADC_CR_ADCAL; // Start calibrtation\n  while((ADC1->CR & ADC_CR_ADCAL) != 0);\n\n  ADC1->ISR |= ADC_ISR_ADRDY;\n  ADC1->CR |= ADC_CR_ADEN;\n  while(!(ADC1->ISR & ADC_ISR_ADRDY));\n}\n\nuint32_t adc_get(unsigned int channel) {\n\n  ADC1->SQR1 &= ~(ADC_SQR1_L);\n  ADC1->SQR1 = (channel << 6U);\n  \n  ADC1->SMPR1 = (0x7U << (channel * 3U) );\n  ADC1->PCSEL_RES0 = (0x1U << channel);\n\n  ADC1->CR |= ADC_CR_ADSTART;\n  while (!(ADC1->ISR & ADC_ISR_EOC));\n\n  uint16_t res = ADC1->DR;\n\n  while (!(ADC1->ISR & ADC_ISR_EOS));\n  ADC1->ISR |= ADC_ISR_EOS;\n\n  return res;\n}\n\nuint32_t adc_get_voltage(void) {\n  // REVC has a 10, 1 (1/11) voltage divider\n  // Here is the calculation for the scale (s)\n  // ADCV = VIN_S * (1/11) * (65535/3.3)\n  // RETVAL = ADCV * s = VIN_S*1000\n  // s = 1000/((65535/3.3)*(1/11)) = 0.553902494\n\n  // Avoid needing floating point math, so output in mV\n  return (adc_get(ADCCHAN_VOLTAGE) * 5539U) / 10000U;\n}\n"
  },
  {
    "path": "panda/board/stm32h7/llfan.h",
    "content": "void EXTI2_IRQ_Handler(void) { }\nvoid fan_init(void){ }\n"
  },
  {
    "path": "panda/board/stm32h7/llfdcan.h",
    "content": "#define FDCAN_MESSAGE_RAM_SIZE 0x2800UL\n#define FDCAN_START_ADDRESS 0x4000AC00UL\n#define FDCAN_OFFSET 3412UL // bytes for each FDCAN module\n#define FDCAN_OFFSET_W 853UL // words for each FDCAN module\n#define FDCAN_END_ADDRESS 0x4000D3FCUL // Message RAM has a width of 4 Bytes\n\n// With this settings we can go up to 6Mbit/s\n#define CAN_SYNC_JW     1U // 1 to 4\n#define CAN_PHASE_SEG1  6U // =(PROP_SEG + PHASE_SEG1) , 1 to 16\n#define CAN_PHASE_SEG2  1U // 1 to 8\n#define CAN_PCLK 48000U // Sourced from PLL1Q\n#define CAN_QUANTA (1U + CAN_PHASE_SEG1 + CAN_PHASE_SEG2)\n// Valid speeds in kbps and their prescalers:\n// 10=600, 20=300, 50=120, 83.333=72, 100=60, 125=48, 250=24, 500=12, 1000=6, 2000=3, 3000=2, 6000=1\n#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))\n\n// RX FIFO 0\n#define FDCAN_RX_FIFO_0_EL_CNT 32UL\n#define FDCAN_RX_FIFO_0_HEAD_SIZE 8UL // bytes\n#define FDCAN_RX_FIFO_0_DATA_SIZE 8UL // bytes\n#define FDCAN_RX_FIFO_0_EL_SIZE (FDCAN_RX_FIFO_0_HEAD_SIZE + FDCAN_RX_FIFO_0_DATA_SIZE)\n#define FDCAN_RX_FIFO_0_EL_W_SIZE (FDCAN_RX_FIFO_0_EL_SIZE / 4UL)\n#define FDCAN_RX_FIFO_0_OFFSET 0UL\n\n// TX FIFO\n#define FDCAN_TX_FIFO_EL_CNT 32UL\n#define FDCAN_TX_FIFO_HEAD_SIZE 8UL // bytes\n#define FDCAN_TX_FIFO_DATA_SIZE 8UL // bytes\n#define FDCAN_TX_FIFO_EL_SIZE (FDCAN_TX_FIFO_HEAD_SIZE + FDCAN_TX_FIFO_DATA_SIZE)\n#define FDCAN_TX_FIFO_EL_W_SIZE (FDCAN_TX_FIFO_EL_SIZE / 4UL)\n#define FDCAN_TX_FIFO_OFFSET (FDCAN_RX_FIFO_0_OFFSET + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_W_SIZE))\n\n#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==FDCAN1) ? \"FDCAN1\" : (((CAN_DEV) == FDCAN2) ? \"FDCAN2\" : \"FDCAN3\"))\n#define CAN_NUM_FROM_CANIF(CAN_DEV) (((CAN_DEV)==FDCAN1) ? 0UL : (((CAN_DEV) == FDCAN2) ? 1UL : 2UL))\n\n// For backwards compatibility with safety code\ntypedef struct {\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\nvoid puts(const char *a);\n\nbool fdcan_request_init(FDCAN_GlobalTypeDef *CANx) {\n  bool ret = true;\n  // Exit from sleep mode\n  CANx->CCCR &= ~(FDCAN_CCCR_CSR);\n  while ((CANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA);\n\n  // Request init\n  uint32_t timeout_counter = 0U;\n  CANx->CCCR |= FDCAN_CCCR_INIT;\n  while ((CANx->CCCR & FDCAN_CCCR_INIT) == 0) {\n    // Delay for about 1ms\n    delay(10000);\n    timeout_counter++;\n\n    if (timeout_counter >= CAN_INIT_TIMEOUT_MS){\n      ret = false;\n      break;\n    }\n  }\n  return ret;\n}\n\nbool fdcan_exit_init(FDCAN_GlobalTypeDef *CANx) {\n  bool ret = true;\n\n  CANx->CCCR &= ~(FDCAN_CCCR_INIT);\n  uint32_t timeout_counter = 0U;\n  while ((CANx->CCCR & FDCAN_CCCR_INIT) != 0) {\n    // Delay for about 1ms\n    delay(10000);\n    timeout_counter++;\n\n    if (timeout_counter >= CAN_INIT_TIMEOUT_MS) {\n      ret = false;\n      break;\n    }\n  }\n  return ret;\n}\n\nbool llcan_set_speed(FDCAN_GlobalTypeDef *CANx, uint32_t speed, uint32_t data_speed, bool loopback, bool silent) {\n  bool ret = fdcan_request_init(CANx);\n\n  if (ret) {\n    // Enable config change\n    CANx->CCCR |= FDCAN_CCCR_CCE;\n\n    //Reset operation mode to Normal\n    CANx->CCCR &= ~(FDCAN_CCCR_TEST);\n    CANx->TEST &= ~(FDCAN_TEST_LBCK);\n    CANx->CCCR &= ~(FDCAN_CCCR_MON);\n    CANx->CCCR &= ~(FDCAN_CCCR_ASM);\n\n    // Set the nominal bit timing register\n    CANx->NBTP = ((CAN_SYNC_JW-1U)<<FDCAN_NBTP_NSJW_Pos) | ((CAN_PHASE_SEG1-1U)<<FDCAN_NBTP_NTSEG1_Pos) | ((CAN_PHASE_SEG2-1U)<<FDCAN_NBTP_NTSEG2_Pos) | ((can_speed_to_prescaler(speed)-1U)<<FDCAN_NBTP_NBRP_Pos);\n    // Set the data bit timing register\n    CANx->DBTP = ((CAN_SYNC_JW-1U)<<FDCAN_DBTP_DSJW_Pos) | ((CAN_PHASE_SEG1-1U)<<FDCAN_DBTP_DTSEG1_Pos) | ((CAN_PHASE_SEG2-1U)<<FDCAN_DBTP_DTSEG2_Pos) | ((can_speed_to_prescaler(data_speed)-1U)<<FDCAN_DBTP_DBRP_Pos);\n    // Silent loopback is known as internal loopback in the docs\n    if (loopback) {\n      CANx->CCCR |= FDCAN_CCCR_TEST;\n      CANx->TEST |= FDCAN_TEST_LBCK;\n      CANx->CCCR |= FDCAN_CCCR_MON;\n    }\n    // Silent is known as bus monitoring in the docs\n    if (silent) {\n      CANx->CCCR |= FDCAN_CCCR_MON;\n    }\n    ret = fdcan_exit_init(CANx);\n    if (!ret) {\n      puts(CAN_NAME_FROM_CANIF(CANx)); puts(\" set_speed timed out! (2)\\n\");\n    }\n  } else {\n    puts(CAN_NAME_FROM_CANIF(CANx)); puts(\" set_speed timed out! (1)\\n\");\n  }\n  return ret;\n}\n\nbool llcan_init(FDCAN_GlobalTypeDef *CANx) {\n  uint32_t can_number = CAN_NUM_FROM_CANIF(CANx);\n  bool ret = fdcan_request_init(CANx);\n\n  if (ret) {\n    // Enable config change\n    CANx->CCCR |= FDCAN_CCCR_CCE;\n    // Enable automatic retransmission\n    CANx->CCCR &= ~(FDCAN_CCCR_DAR);\n    // Enable transmission pause feature\n    CANx->CCCR |= FDCAN_CCCR_TXP;\n    // Disable protocol exception handling\n    CANx->CCCR |= FDCAN_CCCR_PXHD;\n    // FD with BRS\n    CANx->CCCR |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE);\n\n    // Set TX mode to FIFO\n    CANx->TXBC &= ~(FDCAN_TXBC_TFQM);\n    // Configure TX element size (for now 8 bytes, no need to change)\n    //CANx->TXESC |= 0x000U;\n    //Configure RX FIFO0, FIFO1, RX buffer element sizes (no need for now, using classic 8 bytes)\n    register_set(&(CANx->RXESC), 0x0U, (FDCAN_RXESC_F0DS | FDCAN_RXESC_F1DS | FDCAN_RXESC_RBDS));\n    // Disable filtering, accept all valid frames received\n    CANx->XIDFC &= ~(FDCAN_XIDFC_LSE); // No extended filters\n    CANx->SIDFC &= ~(FDCAN_SIDFC_LSS); // No standard filters\n    CANx->GFC &= ~(FDCAN_GFC_RRFE); // Accept extended remote frames\n    CANx->GFC &= ~(FDCAN_GFC_RRFS); // Accept standard remote frames\n    CANx->GFC &= ~(FDCAN_GFC_ANFE); // Accept extended frames to FIFO 0\n    CANx->GFC &= ~(FDCAN_GFC_ANFS); // Accept standard frames to FIFO 0\n\n    uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);\n    uint32_t TxFIFOSA = RxFIFO0SA + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);\n\n    // RX FIFO 0\n    CANx->RXF0C = (FDCAN_RX_FIFO_0_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_RXF0C_F0SA_Pos;\n    CANx->RXF0C |= FDCAN_RX_FIFO_0_EL_CNT << FDCAN_RXF0C_F0S_Pos;\n    // RX FIFO 0 switch to non-blocking (overwrite) mode\n    CANx->RXF0C |= FDCAN_RXF0C_F0OM;\n\n    // TX FIFO (mode set earlier)\n    CANx->TXBC = (FDCAN_TX_FIFO_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_TXBC_TBSA_Pos;\n    CANx->TXBC |= FDCAN_TX_FIFO_EL_CNT << FDCAN_TXBC_TFQS_Pos;\n\n    // Flush allocated RAM\n    uint32_t EndAddress = TxFIFOSA + (FDCAN_TX_FIFO_EL_CNT * FDCAN_TX_FIFO_EL_SIZE);\n    for (uint32_t RAMcounter = RxFIFO0SA; RAMcounter < EndAddress; RAMcounter += 4U) {\n        *(uint32_t *)(RAMcounter) = 0x00000000;\n    }\n\n    // Enable both interrupts for each module\n    CANx->ILE = (FDCAN_ILE_EINT0 | FDCAN_ILE_EINT1);\n\n    CANx->IE &= 0x0U; // Reset all interrupts\n    // Messages for INT0\n    CANx->IE |= FDCAN_IE_RF0NE; // Rx FIFO 0 new message\n\n    // Messages for INT1 (Only TFE works??)\n    CANx->ILS |= FDCAN_ILS_TFEL;\n    CANx->IE |= FDCAN_IE_TFEE; // Tx FIFO empty\n    \n    ret = fdcan_exit_init(CANx);\n    if(!ret) {\n      puts(CAN_NAME_FROM_CANIF(CANx)); puts(\" llcan_init timed out (2)!\\n\");\n    }\n\n    if (CANx == FDCAN1) {\n      NVIC_EnableIRQ(FDCAN1_IT0_IRQn);\n      NVIC_EnableIRQ(FDCAN1_IT1_IRQn);\n    } else if (CANx == FDCAN2) {\n      NVIC_EnableIRQ(FDCAN2_IT0_IRQn);\n      NVIC_EnableIRQ(FDCAN2_IT1_IRQn);\n    } else if (CANx == FDCAN3) {\n      NVIC_EnableIRQ(FDCAN3_IT0_IRQn);\n      NVIC_EnableIRQ(FDCAN3_IT1_IRQn);\n    } else {\n      puts(\"Invalid CAN: initialization failed\\n\");\n    }\n\n  } else {\n    puts(CAN_NAME_FROM_CANIF(CANx)); puts(\" llcan_init timed out (1)!\\n\");\n  }\n  return ret;\n}\n\nvoid llcan_clear_send(FDCAN_GlobalTypeDef *CANx) {\n  // From H7 datasheet: Transmit cancellation is not intended for Tx FIFO operation.\n  UNUSED(CANx);\n}\n"
  },
  {
    "path": "panda/board/stm32h7/llflash.h",
    "content": "bool flash_is_locked(void) {\n  return (FLASH->CR1 & FLASH_CR_LOCK);\n}\n\nvoid flash_unlock(void) {\n  FLASH->KEYR1 = 0x45670123;\n  FLASH->KEYR1 = 0xCDEF89AB;\n}\n\nbool flash_erase_sector(uint8_t sector, bool unlocked) {\n  // don't erase the bootloader(sector 0)\n  if (sector != 0 && sector < 8 && unlocked) {\n    FLASH->CR1 = (sector << 8) | FLASH_CR_SER;\n    FLASH->CR1 |= FLASH_CR_START;\n    while (FLASH->SR1 & FLASH_SR_QW);\n    return true;\n  }\n  return false;\n}\n\nvoid flash_write_word(void *prog_ptr, uint32_t data) {\n  uint32_t *pp = prog_ptr;\n  FLASH->CR1 |= FLASH_CR_PG;\n  *pp = data;\n  while (FLASH->SR1 & FLASH_SR_QW);\n}\n\nvoid flush_write_buffer(void) {\n  if (FLASH->SR1 & FLASH_SR_WBNE) {\n    FLASH->CR1 |= FLASH_CR_FW;\n    while (FLASH->SR1 & FLASH_CR_FW);\n  }\n}\n"
  },
  {
    "path": "panda/board/stm32h7/llrtc.h",
    "content": "#define RCC_BDCR_MASK (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL | RCC_BDCR_LSEDRV | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)\n\nvoid enable_bdomain_protection(void) {\n  register_clear_bits(&(PWR->CR1), PWR_CR1_DBP);\n}\n\nvoid disable_bdomain_protection(void) {\n  register_set_bits(&(PWR->CR1), PWR_CR1_DBP);\n}\n"
  },
  {
    "path": "panda/board/stm32h7/lluart.h",
    "content": "void uart_init(uart_ring *q, int baud) { UNUSED(q); UNUSED(baud); }\nvoid uart_set_baud(USART_TypeDef *u, unsigned int baud) { UNUSED(u); UNUSED(baud); }\nvoid dma_pointer_handler(uart_ring *q, uint32_t dma_ndtr) { UNUSED(q); UNUSED(dma_ndtr); }\nvoid uart_rx_ring(uart_ring *q) { UNUSED(q); }\nvoid uart_tx_ring(uart_ring *q) { UNUSED(q); }\n"
  },
  {
    "path": "panda/board/stm32h7/llusb.h",
    "content": "typedef struct\n{\n  __IO uint32_t HPRT;\n}\nUSB_OTG_HostPortTypeDef;\n\nUSB_OTG_GlobalTypeDef *USBx = USB_OTG_HS;\n\n#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t)USBx + USB_OTG_HOST_BASE))\n#define USBx_HOST_PORT  ((USB_OTG_HostPortTypeDef *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE))\n#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t)USBx + USB_OTG_DEVICE_BASE))\n#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\n#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\n#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))\n#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)\n\n#define USBD_FS_TRDT_VALUE        6U\n#define USB_OTG_SPEED_FULL        3U\n#define DCFG_FRAME_INTERVAL_80    0U\n\n\nvoid usb_irqhandler(void);\n\nvoid OTG_HS_IRQ_Handler(void) {\n  NVIC_DisableIRQ(OTG_HS_IRQn);\n  usb_irqhandler();\n  NVIC_EnableIRQ(OTG_HS_IRQn);\n}\n\nvoid usb_init(void) {\n  REGISTER_INTERRUPT(OTG_HS_IRQn, OTG_HS_IRQ_Handler, 1500000U, FAULT_INTERRUPT_RATE_USB) // TODO: Find out a better rate limit for USB. Now it's the 1.5MB/s rate\n\n  // Disable global interrupt\n  USBx->GAHBCFG &= ~(USB_OTG_GAHBCFG_GINT);\n  // Select FS Embedded PHY\n  USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\n  // Force device mode\n  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);\n  USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\n  delay(250000); // Wait for about 25ms (explicitly stated in H7 ref manual)\n  // Wait for AHB master IDLE state.\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);\n  // Core Soft Reset\n  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\n  // Activate the USB Transceiver\n  USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\n\n  for (uint8_t i = 0U; i < 15U; i++) {\n    USBx->DIEPTXF[i] = 0U;\n  }\n\n  // VBUS Sensing setup\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\n  // Deactivate VBUS Sensing B\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);\n  // B-peripheral session valid override enable\n  USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\n  USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\n  // Restart the Phy Clock\n  USBx_PCGCCTL = 0U;\n  // Device mode configuration\n  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\n  USBx_DEVICE->DCFG |= USB_OTG_SPEED_FULL | USB_OTG_DCFG_NZLSOHSK;\n\n  // Flush FIFOs\n  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (0x10U << 6));\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\n\n  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\n\n  // Clear all pending Device Interrupts\n  USBx_DEVICE->DIEPMSK = 0U;\n  USBx_DEVICE->DOEPMSK = 0U;\n  USBx_DEVICE->DAINTMSK = 0U;\n  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\n\n  // Disable all interrupts.\n  USBx->GINTMSK = 0U;\n  // Clear any pending interrupts\n  USBx->GINTSTS = 0xBFFFFFFFU;\n  // Enable interrupts matching to the Device mode ONLY\n  USBx->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_OTGINT |\n                  USB_OTG_GINTMSK_RXFLVLM | USB_OTG_GINTMSK_GONAKEFFM | USB_OTG_GINTMSK_GINAKEFFM |\n                  USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_USBSUSPM |\n                  USB_OTG_GINTMSK_CIDSCHGM | USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_MMISM | USB_OTG_GINTMSK_EOPFM;\n\n  // Set USB Turnaround time\n  USBx->GUSBCFG |= ((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\n  // Enables the controller's Global Int in the AHB Config reg\n  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\n  // Soft disconnect disable:\n  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_SDIS);\n\n  // enable the IRQ\n  NVIC_EnableIRQ(OTG_HS_IRQn);\n}\n"
  },
  {
    "path": "panda/board/stm32h7/peripherals.h",
    "content": "void gpio_usb_init(void) {\n  // A11,A12: USB:\n  set_gpio_alternate(GPIOA, 11, GPIO_AF10_OTG1_FS);\n  set_gpio_alternate(GPIOA, 12, GPIO_AF10_OTG1_FS);\n  GPIOA->OSPEEDR = GPIO_OSPEEDR_OSPEED11 | GPIO_OSPEEDR_OSPEED12;\n}\n\nvoid gpio_usart2_init(void) {\n  // A2,A3: USART 2 for debugging\n  set_gpio_alternate(GPIOA, 2, GPIO_AF7_USART2);\n  set_gpio_alternate(GPIOA, 3, GPIO_AF7_USART2);\n}\n\n// Common GPIO initialization\nvoid common_init_gpio(void) {\n  /// E2,E3,E4: RGB LED\n  set_gpio_pullup(GPIOE, 2, PULL_NONE);\n  set_gpio_mode(GPIOE, 2, MODE_OUTPUT);\n\n  set_gpio_pullup(GPIOE, 3, PULL_NONE);\n  set_gpio_mode(GPIOE, 3, MODE_OUTPUT);\n\n  set_gpio_pullup(GPIOE, 4, PULL_NONE);\n  set_gpio_mode(GPIOE, 4, MODE_OUTPUT);\n\n  // F7,F8,F9,F10: BOARD ID\n  set_gpio_pullup(GPIOF, 7, PULL_NONE);\n  set_gpio_mode(GPIOF, 7, MODE_INPUT);\n\n  set_gpio_pullup(GPIOF, 8, PULL_NONE);\n  set_gpio_mode(GPIOF, 8, MODE_INPUT);\n\n  set_gpio_pullup(GPIOF, 9, PULL_NONE);\n  set_gpio_mode(GPIOF, 9, MODE_INPUT);\n\n  set_gpio_pullup(GPIOF, 10, PULL_NONE);\n  set_gpio_mode(GPIOF, 10, MODE_INPUT);\n\n  // G11,B3,D7,B4: transceiver enable\n  set_gpio_pullup(GPIOG, 11, PULL_NONE);\n  set_gpio_mode(GPIOG, 11, MODE_OUTPUT);\n\n  // Speed was set to high by default after reset, changing to low\n  GPIOB->OSPEEDR = GPIO_OSPEEDR_OSPEED3;\n  set_gpio_pullup(GPIOB, 3, PULL_NONE);\n  set_gpio_mode(GPIOB, 3, MODE_OUTPUT);\n\n  set_gpio_pullup(GPIOD, 7, PULL_NONE);\n  set_gpio_mode(GPIOD, 7, MODE_OUTPUT);\n\n  set_gpio_pullup(GPIOB, 4, PULL_NONE);\n  set_gpio_mode(GPIOB, 4, MODE_OUTPUT);\n\n  // B14: usb load switch\n  set_gpio_pullup(GPIOB, 14, PULL_NONE);\n  set_gpio_mode(GPIOB, 14, MODE_OUTPUT);\n\n  //B1,F11 5VOUT_S, VOLT_S\n  set_gpio_pullup(GPIOB, 1, PULL_NONE);\n  set_gpio_mode(GPIOB, 1, MODE_ANALOG);\n\n  set_gpio_pullup(GPIOF, 11, PULL_NONE);\n  set_gpio_mode(GPIOF, 11, MODE_ANALOG);\n\n  gpio_usb_init();\n\n  // B8,B9: FDCAN1\n  set_gpio_pullup(GPIOB, 8, PULL_NONE);\n  set_gpio_alternate(GPIOB, 8, GPIO_AF9_FDCAN1);\n\n  set_gpio_pullup(GPIOB, 9, PULL_NONE);\n  set_gpio_alternate(GPIOB, 9, GPIO_AF9_FDCAN1);\n  \n  // B5,B6 (mplex to B12,B13): FDCAN2\n  set_gpio_pullup(GPIOB, 12, PULL_NONE);\n  set_gpio_pullup(GPIOB, 13, PULL_NONE);\n\n  set_gpio_pullup(GPIOB, 5, PULL_NONE);\n  set_gpio_alternate(GPIOB, 5, GPIO_AF9_FDCAN2);\n\n  set_gpio_pullup(GPIOB, 6, PULL_NONE);\n  set_gpio_alternate(GPIOB, 6, GPIO_AF9_FDCAN2);\n  \n  // G9,G10: FDCAN3\n  set_gpio_pullup(GPIOG, 9, PULL_NONE);\n  set_gpio_alternate(GPIOG, 9, GPIO_AF2_FDCAN3);\n\n  set_gpio_pullup(GPIOG, 10, PULL_NONE);\n  set_gpio_alternate(GPIOG, 10, GPIO_AF2_FDCAN3);\n}\n\nvoid flasher_peripherals_init(void) {\n  RCC->AHB1ENR |= RCC_AHB1ENR_USB1OTGHSEN;\n}\n\n// Peripheral initialization\nvoid peripherals_init(void) {\n  // enable GPIO(A,B,C,D,E,F,G,H)\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN;\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN;\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIODEN;\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIOEEN;\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIOFEN;\n  RCC->AHB4ENR |= RCC_AHB4ENR_GPIOGEN;\n\n  RCC->APB1LENR |= RCC_APB1LENR_TIM2EN;  // main counter\n  RCC->APB1LENR |= RCC_APB1LENR_TIM6EN;  // interrupt timer\n  RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;  // clock source timer\n  RCC->APB1LENR |= RCC_APB1LENR_TIM12EN;  // slow loop\n\n  RCC->APB1HENR |= RCC_APB1HENR_FDCANEN; // FDCAN core enable\n  RCC->AHB1ENR |= RCC_AHB1ENR_ADC12EN; // Enable ADC clocks\n\n  // HS USB enable, also LP is needed for CSleep state(__WFI())\n  RCC->AHB1ENR |= RCC_AHB1ENR_USB1OTGHSEN;\n  RCC->AHB1LPENR |= RCC_AHB1LPENR_USB1OTGHSLPEN;\n  RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_USB1OTGHSULPILPEN);\n}\n\nvoid enable_interrupt_timer(void) {\n  register_set_bits(&(RCC->APB1LENR), RCC_APB1LENR_TIM6EN); // Enable interrupt timer peripheral\n}\n"
  },
  {
    "path": "panda/board/stm32h7/startup_stm32h7x5xx.s",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file      startup_stm32h735xx.s\r\n  * @author    MCD Application Team\r\n  * @brief     STM32H735xx Devices vector table for GCC based toolchain.\r\n  *            This module performs:\r\n  *                - Set the initial SP\r\n  *                - Set the initial PC == Reset_Handler,\r\n  *                - Set the vector table entries with the exceptions ISR address\r\n  *                - Branches to main in the C library (which eventually\r\n  *                  calls main()).\r\n  *            After Reset the Cortex-M processor is in Thread mode,\r\n  *            priority is Privileged, and the Stack is set to Main.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n  .syntax unified\r\n  .cpu cortex-m7\r\n  .fpu softvfp\r\n  .thumb\r\n\r\n.global  g_pfnVectors\r\n.global  Default_Handler\r\n\r\n/* start address for the initialization values of the .data section.\r\ndefined in linker script */\r\n.word  _sidata\r\n/* start address for the .data section. defined in linker script */\r\n.word  _sdata\r\n/* end address for the .data section. defined in linker script */\r\n.word  _edata\r\n/* start address for the .bss section. defined in linker script */\r\n.word  _sbss\r\n/* end address for the .bss section. defined in linker script */\r\n.word  _ebss\r\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r\n\r\n/**\r\n * @brief  This is the code that gets called when the processor first\r\n *          starts execution following a reset event. Only the absolutely\r\n *          necessary set is performed, after which the application\r\n *          supplied main() routine is called.\r\n * @param  None\r\n * @retval : None\r\n*/\r\n\r\n    .section  .text.Reset_Handler\r\n  .weak  Reset_Handler\r\n  .type  Reset_Handler, %function\r\nReset_Handler:\r\n  ldr   sp, =_estack      /* set stack pointer */\r\n  bl __initialize_hardware_early\r\n\r\n/* Copy the data segment initializers from flash to SRAM */\r\n  ldr r0, =_sdata\r\n  ldr r1, =_edata\r\n  ldr r2, =_sidata\r\n  movs r3, #0\r\n  b LoopCopyDataInit\r\n\r\nCopyDataInit:\r\n  ldr r4, [r2, r3]\r\n  str r4, [r0, r3]\r\n  adds r3, r3, #4\r\n\r\nLoopCopyDataInit:\r\n  adds r4, r0, r3\r\n  cmp r4, r1\r\n  bcc CopyDataInit\r\n/* Zero fill the bss segment. */\r\n  ldr r2, =_sbss\r\n  ldr r4, =_ebss\r\n  movs r3, #0\r\n  b LoopFillZerobss\r\n\r\nFillZerobss:\r\n  str  r3, [r2]\r\n  adds r2, r2, #4\r\n\r\nLoopFillZerobss:\r\n  cmp r2, r4\r\n  bcc FillZerobss\r\n  \r\n/* Call the clock system intitialization function.*/\r\n  /* bl  SystemInit    */\r\n/* Call static constructors */\r\n    /* bl __libc_init_array */\r\n/* Call the application's entry point.*/\r\n  bl  main\r\n  bx  lr\r\n.size  Reset_Handler, .-Reset_Handler\r\n\r\n/**\r\n * @brief  This is the code that gets called when the processor receives an\r\n *         unexpected interrupt.  This simply enters an infinite loop, preserving\r\n *         the system state for examination by a debugger.\r\n * @param  None\r\n * @retval None\r\n*/\r\n    .section  .text.Default_Handler,\"ax\",%progbits\r\nDefault_Handler:\r\nInfinite_Loop:\r\n  b  Infinite_Loop\r\n  .size  Default_Handler, .-Default_Handler\r\n/******************************************************************************\r\n*\r\n* The minimal vector table for a Cortex M. Note that the proper constructs\r\n* must be placed on this to ensure that it ends up at physical address\r\n* 0x0000.0000.\r\n*\r\n*******************************************************************************/\r\n   .section  .isr_vector,\"a\",%progbits\r\n  .type  g_pfnVectors, %object\r\n  .size  g_pfnVectors, .-g_pfnVectors\r\n\r\n\r\ng_pfnVectors:\r\n  .word  _estack\r\n  .word  Reset_Handler\r\n\r\n  .word  NMI_Handler\r\n  .word  HardFault_Handler\r\n  .word  MemManage_Handler\r\n  .word  BusFault_Handler\r\n  .word  UsageFault_Handler\r\n  .word  0\r\n  .word  0\r\n  .word  0\r\n  .word  0\r\n  .word  SVC_Handler\r\n  .word  DebugMon_Handler\r\n  .word  0\r\n  .word  PendSV_Handler\r\n  .word  SysTick_Handler\r\n\r\n  /* External Interrupts */\r\n  .word     WWDG_IRQHandler                   /* Window WatchDog              */\r\n  .word     PVD_AVD_IRQHandler                /* PVD/AVD through EXTI Line detection */\r\n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */\r\n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */\r\n  .word     FLASH_IRQHandler                  /* FLASH                        */\r\n  .word     RCC_IRQHandler                    /* RCC                          */\r\n  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */\r\n  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */\r\n  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */\r\n  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */\r\n  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */\r\n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */\r\n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */\r\n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */\r\n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */\r\n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */\r\n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */\r\n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */\r\n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */\r\n  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */\r\n  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */\r\n  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */\r\n  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */\r\n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */\r\n  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */\r\n  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */\r\n  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */\r\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */\r\n  .word     TIM2_IRQHandler                   /* TIM2                         */\r\n  .word     TIM3_IRQHandler                   /* TIM3                         */\r\n  .word     TIM4_IRQHandler                   /* TIM4                         */\r\n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */\r\n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */\r\n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */\r\n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */\r\n  .word     SPI1_IRQHandler                   /* SPI1                         */\r\n  .word     SPI2_IRQHandler                   /* SPI2                         */\r\n  .word     USART1_IRQHandler                 /* USART1                       */\r\n  .word     USART2_IRQHandler                 /* USART2                       */\r\n  .word     USART3_IRQHandler                 /* USART3                       */\r\n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */\r\n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */\r\n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */\r\n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */\r\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */\r\n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */\r\n  .word     FMC_IRQHandler                    /* FMC                          */\r\n  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */\r\n  .word     TIM5_IRQHandler                   /* TIM5                         */\r\n  .word     SPI3_IRQHandler                   /* SPI3                         */\r\n  .word     UART4_IRQHandler                  /* UART4                        */\r\n  .word     UART5_IRQHandler                  /* UART5                        */\r\n  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */\r\n  .word     TIM7_IRQHandler                   /* TIM7                         */\r\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */\r\n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */\r\n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */\r\n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */\r\n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */\r\n  .word     ETH_IRQHandler                    /* Ethernet                     */\r\n  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */\r\n  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */\r\n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */\r\n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */\r\n  .word     USART6_IRQHandler                 /* USART6                       */\r\n  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */\r\n  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */\r\n  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */\r\n  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */\r\n  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */\r\n  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */\r\n  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */\r\n  .word     CRYP_IRQHandler                   /* CRYP                         */\r\n  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */\r\n  .word     FPU_IRQHandler                    /* FPU                          */\r\n  .word     UART7_IRQHandler                  /* UART7                        */\r\n  .word     UART8_IRQHandler                  /* UART8                        */\r\n  .word     SPI4_IRQHandler                   /* SPI4                         */\r\n  .word     SPI5_IRQHandler                   /* SPI5                         */\r\n  .word     SPI6_IRQHandler                   /* SPI6                         */\r\n  .word     SAI1_IRQHandler                   /* SAI1                         */\r\n  .word     LTDC_IRQHandler                   /* LTDC                         */\r\n  .word     LTDC_ER_IRQHandler                /* LTDC error                   */\r\n  .word     DMA2D_IRQHandler                  /* DMA2D                        */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */\r\n  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */\r\n  .word     CEC_IRQHandler                    /* HDMI_CEC                     */\r\n  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */\r\n  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */\r\n  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */\r\n  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */\r\n  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */\r\n  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */\r\n  .word     0                                 /* Reserved                     */\r\n  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */\r\n  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt          */\r\n  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt          */\r\n  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt          */\r\n  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt         */\r\n  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt          */\r\n  .word     0                                 /* Reserved                        */\r\n  .word     MDMA_IRQHandler                   /* MDMA global Interrupt           */\r\n  .word     0                                 /* Reserved                        */\r\n  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt         */\r\n  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt          */\r\n  .word     0                                 /* Reserved                        */\r\n  .word     ADC3_IRQHandler                   /* ADC3 global Interrupt           */\r\n  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt        */\r\n  .word     BDMA_Channel0_IRQHandler          /* BDMA Channel 0 global Interrupt */\r\n  .word     BDMA_Channel1_IRQHandler          /* BDMA Channel 1 global Interrupt */\r\n  .word     BDMA_Channel2_IRQHandler          /* BDMA Channel 2 global Interrupt */\r\n  .word     BDMA_Channel3_IRQHandler          /* BDMA Channel 3 global Interrupt */\r\n  .word     BDMA_Channel4_IRQHandler          /* BDMA Channel 4 global Interrupt */\r\n  .word     BDMA_Channel5_IRQHandler          /* BDMA Channel 5 global Interrupt */\r\n  .word     BDMA_Channel6_IRQHandler          /* BDMA Channel 6 global Interrupt */\r\n  .word     BDMA_Channel7_IRQHandler          /* BDMA Channel 7 global Interrupt */\r\n  .word     COMP1_IRQHandler                  /* COMP1 global Interrupt          */\r\n  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt        */\r\n  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt        */\r\n  .word     LPTIM4_IRQHandler                 /* LP TIM4 global interrupt        */\r\n  .word     LPTIM5_IRQHandler                 /* LP TIM5 global interrupt        */\r\n  .word     LPUART1_IRQHandler                /* LP UART1 interrupt              */\r\n  .word     0                                 /* Reserved                        */\r\n  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */\r\n  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */\r\n  .word     SAI4_IRQHandler                   /* SAI4 global interrupt           */\r\n  .word     DTS_IRQHandler                    /* Digital Temperature Sensor  interrupt */\r\n  .word     0                                 /* Reserved                              */\r\n  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins      */\r\n  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2 Interrupt       */\r\n  .word     OTFDEC1_IRQHandler                /* OTFDEC1 Interrupt        */\r\n  .word     OTFDEC2_IRQHandler                /* OTFDEC2 Interrupt        */\r\n  .word     FMAC_IRQHandler                   /* FMAC Interrupt           */\r\n  .word     CORDIC_IRQHandler                 /* CORDIC Interrupt         */\r\n  .word     UART9_IRQHandler                  /* UART9 Interrupt          */\r\n  .word     USART10_IRQHandler                /* UART10 Interrupt         */\r\n  .word     I2C5_EV_IRQHandler                /* I2C5 Event Interrupt     */\r\n  .word     I2C5_ER_IRQHandler                /* I2C5 Error Interrupt     */\r\n  .word     FDCAN3_IT0_IRQHandler             /* FDCAN3 interrupt line 0  */\r\n  .word     FDCAN3_IT1_IRQHandler             /* FDCAN3 interrupt line 1  */\r\n  .word     TIM23_IRQHandler                  /* TIM23 global interrupt   */\r\n  .word     TIM24_IRQHandler                  /* TIM24 global interrupt   */\r\n\r\n/*******************************************************************************\r\n*\r\n* Provide weak aliases for each Exception handler to the Default_Handler.\r\n* As they are weak aliases, any function with the same name will override\r\n* this definition.\r\n*\r\n*******************************************************************************/\r\n   .weak      NMI_Handler\r\n   .thumb_set NMI_Handler,Default_Handler\r\n\r\n   .weak      HardFault_Handler\r\n   .thumb_set HardFault_Handler,Default_Handler\r\n\r\n   .weak      MemManage_Handler\r\n   .thumb_set MemManage_Handler,Default_Handler\r\n\r\n   .weak      BusFault_Handler\r\n   .thumb_set BusFault_Handler,Default_Handler\r\n\r\n   .weak      UsageFault_Handler\r\n   .thumb_set UsageFault_Handler,Default_Handler\r\n\r\n   .weak      SVC_Handler\r\n   .thumb_set SVC_Handler,Default_Handler\r\n\r\n   .weak      DebugMon_Handler\r\n   .thumb_set DebugMon_Handler,Default_Handler\r\n\r\n   .weak      PendSV_Handler\r\n   .thumb_set PendSV_Handler,Default_Handler\r\n\r\n   .weak      SysTick_Handler\r\n   .thumb_set SysTick_Handler,Default_Handler\r\n\r\n   .weak      WWDG_IRQHandler\r\n   .thumb_set WWDG_IRQHandler,Default_Handler\r\n\r\n   .weak      PVD_AVD_IRQHandler\r\n   .thumb_set PVD_AVD_IRQHandler,Default_Handler\r\n\r\n   .weak      TAMP_STAMP_IRQHandler\r\n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r\n\r\n   .weak      RTC_WKUP_IRQHandler\r\n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r\n\r\n   .weak      FLASH_IRQHandler\r\n   .thumb_set FLASH_IRQHandler,Default_Handler\r\n\r\n   .weak      RCC_IRQHandler\r\n   .thumb_set RCC_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI0_IRQHandler\r\n   .thumb_set EXTI0_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI1_IRQHandler\r\n   .thumb_set EXTI1_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI2_IRQHandler\r\n   .thumb_set EXTI2_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI3_IRQHandler\r\n   .thumb_set EXTI3_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI4_IRQHandler\r\n   .thumb_set EXTI4_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream0_IRQHandler\r\n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream1_IRQHandler\r\n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream2_IRQHandler\r\n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream3_IRQHandler\r\n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream4_IRQHandler\r\n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream5_IRQHandler\r\n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream6_IRQHandler\r\n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r\n\r\n   .weak      ADC_IRQHandler\r\n   .thumb_set ADC_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN1_IT0_IRQHandler\r\n   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN2_IT0_IRQHandler\r\n   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN1_IT1_IRQHandler\r\n   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN2_IT1_IRQHandler\r\n   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI9_5_IRQHandler\r\n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM1_BRK_IRQHandler\r\n   .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM1_UP_IRQHandler\r\n   .thumb_set TIM1_UP_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM1_TRG_COM_IRQHandler\r\n   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM1_CC_IRQHandler\r\n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM2_IRQHandler\r\n   .thumb_set TIM2_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM3_IRQHandler\r\n   .thumb_set TIM3_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM4_IRQHandler\r\n   .thumb_set TIM4_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C1_EV_IRQHandler\r\n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C1_ER_IRQHandler\r\n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C2_EV_IRQHandler\r\n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C2_ER_IRQHandler\r\n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI1_IRQHandler\r\n   .thumb_set SPI1_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI2_IRQHandler\r\n   .thumb_set SPI2_IRQHandler,Default_Handler\r\n\r\n   .weak      USART1_IRQHandler\r\n   .thumb_set USART1_IRQHandler,Default_Handler\r\n\r\n   .weak      USART2_IRQHandler\r\n   .thumb_set USART2_IRQHandler,Default_Handler\r\n\r\n   .weak      USART3_IRQHandler\r\n   .thumb_set USART3_IRQHandler,Default_Handler\r\n\r\n   .weak      EXTI15_10_IRQHandler\r\n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\r\n\r\n   .weak      RTC_Alarm_IRQHandler\r\n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM8_BRK_TIM12_IRQHandler\r\n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM8_UP_TIM13_IRQHandler\r\n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM8_TRG_COM_TIM14_IRQHandler\r\n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM8_CC_IRQHandler\r\n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA1_Stream7_IRQHandler\r\n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r\n\r\n   .weak      FMC_IRQHandler\r\n   .thumb_set FMC_IRQHandler,Default_Handler\r\n\r\n   .weak      SDMMC1_IRQHandler\r\n   .thumb_set SDMMC1_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM5_IRQHandler\r\n   .thumb_set TIM5_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI3_IRQHandler\r\n   .thumb_set SPI3_IRQHandler,Default_Handler\r\n\r\n   .weak      UART4_IRQHandler\r\n   .thumb_set UART4_IRQHandler,Default_Handler\r\n\r\n   .weak      UART5_IRQHandler\r\n   .thumb_set UART5_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM6_DAC_IRQHandler\r\n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM7_IRQHandler\r\n   .thumb_set TIM7_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream0_IRQHandler\r\n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream1_IRQHandler\r\n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream2_IRQHandler\r\n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream3_IRQHandler\r\n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream4_IRQHandler\r\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r\n\r\n   .weak      ETH_IRQHandler\r\n   .thumb_set ETH_IRQHandler,Default_Handler\r\n\r\n   .weak      ETH_WKUP_IRQHandler\r\n   .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN_CAL_IRQHandler\r\n   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream5_IRQHandler\r\n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream6_IRQHandler\r\n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2_Stream7_IRQHandler\r\n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r\n\r\n   .weak      USART6_IRQHandler\r\n   .thumb_set USART6_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C3_EV_IRQHandler\r\n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C3_ER_IRQHandler\r\n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      OTG_HS_EP1_OUT_IRQHandler\r\n   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r\n\r\n   .weak      OTG_HS_EP1_IN_IRQHandler\r\n   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r\n\r\n   .weak      OTG_HS_WKUP_IRQHandler\r\n   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r\n\r\n   .weak      OTG_HS_IRQHandler\r\n   .thumb_set OTG_HS_IRQHandler,Default_Handler\r\n\r\n   .weak      DCMI_PSSI_IRQHandler\r\n   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler\r\n\r\n   .weak      CRYP_IRQHandler\r\n   .thumb_set CRYP_IRQHandler,Default_Handler\r\n\r\n   .weak      HASH_RNG_IRQHandler\r\n   .thumb_set HASH_RNG_IRQHandler,Default_Handler\r\n\r\n   .weak      FPU_IRQHandler\r\n   .thumb_set FPU_IRQHandler,Default_Handler\r\n\r\n   .weak      UART7_IRQHandler\r\n   .thumb_set UART7_IRQHandler,Default_Handler\r\n\r\n   .weak      UART8_IRQHandler\r\n   .thumb_set UART8_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI4_IRQHandler\r\n   .thumb_set SPI4_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI5_IRQHandler\r\n   .thumb_set SPI5_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI6_IRQHandler\r\n   .thumb_set SPI6_IRQHandler,Default_Handler\r\n\r\n   .weak      SAI1_IRQHandler\r\n   .thumb_set SAI1_IRQHandler,Default_Handler\r\n\r\n   .weak      LTDC_IRQHandler\r\n   .thumb_set LTDC_IRQHandler,Default_Handler\r\n\r\n   .weak      LTDC_ER_IRQHandler\r\n   .thumb_set LTDC_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2D_IRQHandler\r\n   .thumb_set DMA2D_IRQHandler,Default_Handler\r\n\r\n   .weak      OCTOSPI1_IRQHandler\r\n   .thumb_set OCTOSPI1_IRQHandler,Default_Handler\r\n\r\n   .weak      LPTIM1_IRQHandler\r\n   .thumb_set LPTIM1_IRQHandler,Default_Handler\r\n\r\n   .weak      CEC_IRQHandler\r\n   .thumb_set CEC_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C4_EV_IRQHandler\r\n   .thumb_set I2C4_EV_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C4_ER_IRQHandler\r\n   .thumb_set I2C4_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      SPDIF_RX_IRQHandler\r\n   .thumb_set SPDIF_RX_IRQHandler,Default_Handler\r\n\r\n   .weak      DMAMUX1_OVR_IRQHandler\r\n   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler\r\n\r\n   .weak      DFSDM1_FLT0_IRQHandler\r\n   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler\r\n\r\n   .weak      DFSDM1_FLT1_IRQHandler\r\n   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler\r\n\r\n   .weak      DFSDM1_FLT2_IRQHandler\r\n   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler\r\n\r\n   .weak      DFSDM1_FLT3_IRQHandler\r\n   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler\r\n\r\n   .weak      SWPMI1_IRQHandler\r\n   .thumb_set SWPMI1_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM15_IRQHandler\r\n   .thumb_set TIM15_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM16_IRQHandler\r\n   .thumb_set TIM16_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM17_IRQHandler\r\n   .thumb_set TIM17_IRQHandler,Default_Handler\r\n\r\n   .weak      MDIOS_WKUP_IRQHandler\r\n   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler\r\n\r\n   .weak      MDIOS_IRQHandler\r\n   .thumb_set MDIOS_IRQHandler,Default_Handler\r\n\r\n   .weak      MDMA_IRQHandler\r\n   .thumb_set MDMA_IRQHandler,Default_Handler\r\n\r\n   .weak      SDMMC2_IRQHandler\r\n   .thumb_set SDMMC2_IRQHandler,Default_Handler\r\n\r\n   .weak      HSEM1_IRQHandler\r\n   .thumb_set HSEM1_IRQHandler,Default_Handler\r\n\r\n   .weak      ADC3_IRQHandler\r\n   .thumb_set ADC3_IRQHandler,Default_Handler\r\n\r\n   .weak      DMAMUX2_OVR_IRQHandler\r\n   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel0_IRQHandler\r\n   .thumb_set BDMA_Channel0_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel1_IRQHandler\r\n   .thumb_set BDMA_Channel1_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel2_IRQHandler\r\n   .thumb_set BDMA_Channel2_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel3_IRQHandler\r\n   .thumb_set BDMA_Channel3_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel4_IRQHandler\r\n   .thumb_set BDMA_Channel4_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel5_IRQHandler\r\n   .thumb_set BDMA_Channel5_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel6_IRQHandler\r\n   .thumb_set BDMA_Channel6_IRQHandler,Default_Handler\r\n\r\n   .weak      BDMA_Channel7_IRQHandler\r\n   .thumb_set BDMA_Channel7_IRQHandler,Default_Handler\r\n\r\n   .weak      COMP1_IRQHandler\r\n   .thumb_set COMP1_IRQHandler,Default_Handler\r\n\r\n   .weak      LPTIM2_IRQHandler\r\n   .thumb_set LPTIM2_IRQHandler,Default_Handler\r\n\r\n   .weak      LPTIM3_IRQHandler\r\n   .thumb_set LPTIM3_IRQHandler,Default_Handler\r\n\r\n   .weak      LPTIM4_IRQHandler\r\n   .thumb_set LPTIM4_IRQHandler,Default_Handler\r\n\r\n   .weak      LPTIM5_IRQHandler\r\n   .thumb_set LPTIM5_IRQHandler,Default_Handler\r\n\r\n   .weak      LPUART1_IRQHandler\r\n   .thumb_set LPUART1_IRQHandler,Default_Handler\r\n\r\n   .weak      CRS_IRQHandler\r\n   .thumb_set CRS_IRQHandler,Default_Handler\r\n\r\n   .weak      ECC_IRQHandler\r\n   .thumb_set ECC_IRQHandler,Default_Handler\r\n\r\n   .weak      SAI4_IRQHandler\r\n   .thumb_set SAI4_IRQHandler,Default_Handler\r\n\r\n   .weak      DTS_IRQHandler\r\n   .thumb_set DTS_IRQHandler,Default_Handler\r\n\r\n   .weak      WAKEUP_PIN_IRQHandler\r\n   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler\r\n\r\n   .weak      OCTOSPI2_IRQHandler\r\n   .thumb_set OCTOSPI2_IRQHandler,Default_Handler\r\n\r\n   .weak      OTFDEC1_IRQHandler\r\n   .thumb_set OTFDEC1_IRQHandler,Default_Handler\r\n\r\n   .weak      OTFDEC2_IRQHandler\r\n   .thumb_set OTFDEC2_IRQHandler,Default_Handler\r\n\r\n   .weak      FMAC_IRQHandler\r\n   .thumb_set FMAC_IRQHandler,Default_Handler\r\n\r\n   .weak      CORDIC_IRQHandler\r\n   .thumb_set CORDIC_IRQHandler,Default_Handler\r\n\r\n   .weak      UART9_IRQHandler\r\n   .thumb_set UART9_IRQHandler,Default_Handler\r\n\r\n   .weak      USART10_IRQHandler\r\n   .thumb_set USART10_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C5_EV_IRQHandler\r\n   .thumb_set I2C5_EV_IRQHandler,Default_Handler\r\n\r\n   .weak      I2C5_ER_IRQHandler\r\n   .thumb_set I2C5_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN3_IT0_IRQHandler\r\n   .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler\r\n\r\n   .weak      FDCAN3_IT1_IRQHandler\r\n   .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM23_IRQHandler\r\n   .thumb_set TIM23_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM24_IRQHandler\r\n   .thumb_set TIM24_IRQHandler,Default_Handler\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "panda/board/stm32h7/stm32h7_config.h",
    "content": "#include \"stm32h7/inc/stm32h7xx.h\"\n#include \"stm32h7/inc/stm32h7xx_hal_gpio_ex.h\"\n#define MCU_IDCODE 0x483U\n\n// from the linker script\n#define APP_START_ADDRESS 0x8020000U\n\n#define CORE_FREQ 240U // in Mhz\n//APB1 - 120Mhz, APB2 - 120Mhz\n#define APB1_FREQ CORE_FREQ/2U \n#define APB2_FREQ CORE_FREQ/2U\n\n#define BOOTLOADER_ADDRESS 0x1FF09804U\n\n// Around (1Mbps / 8 bits/byte / 12 bytes per message)\n#define CAN_INTERRUPT_RATE 12000U // FIXME: should raise to 16000 ?\n\n#define MAX_LED_FADE 10240U\n\n// Threshold voltage (mV) for either of the SBUs to be below before deciding harness is connected\n#define HARNESS_CONNECTED_THRESHOLD 40000U\n\n// There are 163 external interrupt sources (see stm32f735xx.h)\n#define NUM_INTERRUPTS 163U\n\n#define TICK_TIMER_IRQ TIM8_BRK_TIM12_IRQn\n#define TICK_TIMER TIM12\n\n#define MICROSECOND_TIMER TIM2\n\n#define INTERRUPT_TIMER_IRQ TIM6_DAC_IRQn\n#define INTERRUPT_TIMER TIM6\n\n#define PROVISION_CHUNK_ADDRESS 0x080FFFE0U\n#define DEVICE_SERIAL_NUMBER_ADDRESS 0x080FFFC0U\n\n#ifndef BOOTSTUB\n  #include \"main_declarations.h\"\n#else\n  #include \"bootstub_declarations.h\"\n#endif\n\n#include \"libc.h\"\n#include \"critical.h\"\n#include \"faults.h\"\n\n#include \"drivers/registers.h\"\n#include \"drivers/interrupts.h\"\n#include \"drivers/gpio.h\"\n#include \"stm32h7/peripherals.h\"\n#include \"stm32h7/interrupt_handlers.h\"\n#include \"drivers/timers.h\"\n#include \"stm32h7/lladc.h\"\n#include \"stm32h7/board.h\"\n#include \"stm32h7/clock.h\"\n\n#if !defined (BOOTSTUB) && defined(PANDA)\n  #include \"drivers/uart.h\"\n  #include \"stm32h7/lluart.h\"\n#endif\n\n#ifdef BOOTSTUB\n  #include \"stm32h7/llflash.h\"\n#else\n  #include \"stm32h7/llfdcan.h\"\n#endif\n\n#include \"stm32h7/llusb.h\"\n\nvoid early_gpio_float(void) {\n  RCC->AHB4ENR = RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN;\n  GPIOA->MODER = 0; GPIOB->MODER = 0; GPIOC->MODER = 0; GPIOD->MODER = 0; GPIOE->MODER = 0; GPIOF->MODER = 0; GPIOG->MODER = 0; GPIOH->MODER = 0;\n  GPIOA->ODR = 0; GPIOB->ODR = 0; GPIOC->ODR = 0; GPIOD->ODR = 0; GPIOE->ODR = 0; GPIOF->ODR = 0; GPIOG->ODR = 0; GPIOH->ODR = 0;\n  GPIOA->PUPDR = 0; GPIOB->PUPDR = 0; GPIOC->PUPDR = 0; GPIOD->PUPDR = 0; GPIOE->PUPDR = 0; GPIOF->PUPDR = 0; GPIOG->PUPDR = 0; GPIOH->PUPDR = 0;\n}\n"
  },
  {
    "path": "panda/board/stm32h7/stm32h7x5_flash.ld",
    "content": "/*\r\n******************************************************************************\r\n**\r\n\r\n**  File        : LinkerScript.ld\r\n**\r\n**  Author\t\t: Auto-generated by System Workbench for STM32\r\n**\r\n**  Abstract    : Linker script for STM32H735ZGTx series\r\n**                1024Kbytes FLASH and 560Kbytes RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**  Distribution: The file is distributed “as is,” without any warranty\r\n**                of any kind.\r\n**\r\n*****************************************************************************\r\n** @attention\r\n**\r\n** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\r\n**\r\n** Redistribution and use in source and binary forms, with or without modification,\r\n** are permitted provided that the following conditions are met:\r\n**   1. Redistributions of source code must retain the above copyright notice,\r\n**      this list of conditions and the following disclaimer.\r\n**   2. Redistributions in binary form must reproduce the above copyright notice,\r\n**      this list of conditions and the following disclaimer in the documentation\r\n**      and/or other materials provided with the distribution.\r\n**   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n**      may be used to endorse or promote products derived from this software\r\n**      without specific prior written permission.\r\n**\r\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n**\r\n*****************************************************************************\r\n*/\r\n\r\n/* Entry Point */\r\nENTRY(Reset_Handler)\r\n\r\n/* Highest address of the user mode stack */\r\nenter_bootloader_mode = 0x38001FFC;\r\n_estack = 0x20020000;    /* end of RAM */\r\n_app_start = 0x08020000; /* Reserve Sector 0(128K) for bootloader */\r\n\r\n/* Generate a link error if heap and stack don't fit into RAM */\r\n_Min_Heap_Size = 0x200;      /* required amount of heap  */\r\n_Min_Stack_Size = 0x400; /* required amount of stack */\r\n\r\n/* Specify the memory areas */\r\nMEMORY\r\n{\r\nDTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\r\nRAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 320K\r\nRAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 32K\r\nRAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 16K\r\nITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K\r\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\r\n}\r\n\r\n/* Define output sections */\r\nSECTIONS\r\n{\r\n  /* The startup code goes first into FLASH */\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) /* Startup code */\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  /* The program code and other data goes into FLASH */\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           /* .text sections (code) */\r\n    *(.text*)          /* .text* sections (code) */\r\n    *(.glue_7)         /* glue arm to thumb code */\r\n    *(.glue_7t)        /* glue thumb to arm code */\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        /* define a global symbols at end of code */\r\n  } >FLASH\r\n\r\n  /* Constant data goes into FLASH */\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\r\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  /* used by the startup to initialize data */\r\n  _sidata = LOADADDR(.data);\r\n\r\n  /* Initialized data sections goes into RAM, load LMA copy after code */\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        /* create a global symbol at data start */\r\n    *(.data)           /* .data sections */\r\n    *(.data*)          /* .data* sections */\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        /* define a global symbol at data end */\r\n  } >DTCMRAM AT> FLASH\r\n\r\n  \r\n  /* Uninitialized data section */\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    /* This is used by the startup in order to initialize the .bss secion */\r\n    _sbss = .;         /* define a global symbol at bss start */\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         /* define a global symbol at bss end */\r\n    __bss_end__ = _ebss;\r\n  } >DTCMRAM\r\n\r\n  /* User_heap_stack section, used to check that there is enough RAM left */\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(8);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(8);\r\n  } >DTCMRAM\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n\r\n"
  },
  {
    "path": "panda/board/tests/test_rsa.c",
    "content": "/*\ngcc -DTEST_RSA test_rsa.c ../crypto/rsa.c ../crypto/sha.c && ./a.out\n*/\n\n#include <stdio.h>\n#include <stdlib.h>\n\n#define MAX_LEN 0x40000\nchar buf[MAX_LEN];\n\n#include \"../crypto/sha.h\"\n#include \"../crypto/rsa.h\"\n#include \"../obj/cert.h\"\n\nint main() {\n  FILE *f = fopen(\"../obj/panda.bin\", \"rb\");\n  int tlen = fread(buf, 1, MAX_LEN, f);\n  fclose(f);\n  printf(\"read %d\\n\", tlen);\n  uint32_t *_app_start = (uint32_t *)buf;\n\n  int len = _app_start[0];\n  char digest[SHA_DIGEST_SIZE];\n  SHA_hash(&_app_start[1], len-4, digest);\n  printf(\"SHA hash done\\n\");\n\n  if (!RSA_verify(&rsa_key, ((void*)&_app_start[0]) + len, RSANUMBYTES, digest, SHA_DIGEST_SIZE)) {\n    printf(\"RSA fail\\n\");\n  } else {\n    printf(\"RSA match!!!\\n\");\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "panda/certs/debug",
    "content": "-----BEGIN RSA PRIVATE KEY-----\nMIICXQIBAAKBgQC948lnRo4x44Rd7Y8bQAML4aKDC4XRx958fHV8K6+FbCaP1Z42\nU2kX0yygak0LjoDutpgObmGHZA+Iz3HeUD6VGjr/teN24vPk+A95cRsjt8rgmGQ9\n6HNjaNgjR+gl1F9XxFimMzir82Xpl1ekTueJNXa7ia5HVH1nFdiksOKHGQIDAQAB\nAoGAQuPw2I6EHJLW1/eNB75e1FqhUqRGeYV8nEGDaUBCTi+wzc4kM2LijF/5QnDv\nvvht9qkfm0XK2VSoHDtnEzcVM/l1ksb68n4R/1nUooAWY6cQI7dCSk/A6yS1EJFg\nBXsgGbT/65khw9pzBW2zVtMVcVNWFayqfCO1I9WcDdA1x1kCQQDfrhoZTZNoDEUE\nJKM4fiUdWr1h3Aw8KLJFFexSWeGDwo+qqnujYcKWkHa9qaH1RG5x8Kir9s9Oi4Js\nmzKwov8fAkEA2VPJPWxJ4vVQpXle6wC1nyoL7s739yxMWFcabvkzDDhlIVBNdVJd\ngZKsFWV7QnVNdDMjn9D27FwKu3i2D+kKxwJBANp1SMojqO765MEKI1t+YDNONx6H\ncm+i85Fjuv4nCIjOEdCGVuCYDxtMFpxgO2y3HAMuHx5sm8XDnWsDHLvFRdMCQD7V\nXqWHnYUk8AAnqy2+ssQl3/VXmZG5GQmhhV74Za3u0C5ljT+SZL6FrYMyKAT67T3f\nWzllrT6BDglNyTWoZxkCQQCt0XSoGM3603GGYNt6AUlGSgtXSo/2Px7odGUtQoKA\nFH9q6FVMYpQJ38spZxIGufZJmLP8LLg6YIWJj1F+akxr\n-----END RSA PRIVATE KEY-----\n"
  },
  {
    "path": "panda/certs/debug.pub",
    "content": "ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAAAgQC948lnRo4x44Rd7Y8bQAML4aKDC4XRx958fHV8K6+FbCaP1Z42U2kX0yygak0LjoDutpgObmGHZA+Iz3HeUD6VGjr/teN24vPk+A95cRsjt8rgmGQ96HNjaNgjR+gl1F9XxFimMzir82Xpl1ekTueJNXa7ia5HVH1nFdiksOKHGQ== batman@y840\n"
  },
  {
    "path": "panda/certs/release.pub",
    "content": "ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAAAgQDGN9GU2nOc0kKq6vdZI5qUMzHt234ngqofrgCFFxL0D2Whex0zACp9gar0HZp+bvtpoSgU/Ev8wexNKr+A9QTradljiuxi5ctrOra9k+wxqNj63Wrcu4+wU5UnJEVf/buV4jCOFffMT8z3PO4imt8LzHuEIC/m/ASKVYyvuvBRQQ== batman@y840\n"
  },
  {
    "path": "panda/crypto/hash-internal.h",
    "content": "/*\n * Copyright 2007 The Android Open Source Project\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *     * Redistributions of source code must retain the above copyright\n *       notice, this list of conditions and the following disclaimer.\n *     * Redistributions in binary form must reproduce the above copyright\n *       notice, this list of conditions and the following disclaimer in the\n *       documentation and/or other materials provided with the distribution.\n *     * Neither the name of Google Inc. nor the names of its contributors may\n *       be used to endorse or promote products derived from this software\n *       without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY Google Inc. ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n * EVENT SHALL Google Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef SYSTEM_CORE_INCLUDE_MINCRYPT_HASH_INTERNAL_H_\n#define SYSTEM_CORE_INCLUDE_MINCRYPT_HASH_INTERNAL_H_\n\n#include \"stdint.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif  // __cplusplus\n\nstruct HASH_CTX;  // forward decl\n\ntypedef struct HASH_VTAB {\n  void (* const init)(struct HASH_CTX*);\n  void (* const update)(struct HASH_CTX*, const void*, int);\n  const uint8_t* (* const final)(struct HASH_CTX*);\n  const uint8_t* (* const hash)(const void*, int, uint8_t*);\n  int size;\n} HASH_VTAB;\n\ntypedef struct HASH_CTX {\n  const HASH_VTAB * f;\n  uint64_t count;\n  uint8_t buf[64];\n  uint32_t state[8];  // upto SHA2\n} HASH_CTX;\n\n#define HASH_init(ctx) (ctx)->f->init(ctx)\n#define HASH_update(ctx, data, len) (ctx)->f->update(ctx, data, len)\n#define HASH_final(ctx) (ctx)->f->final(ctx)\n#define HASH_hash(data, len, digest) (ctx)->f->hash(data, len, digest)\n#define HASH_size(ctx) (ctx)->f->size\n\n#ifdef __cplusplus\n}\n#endif  // __cplusplus\n\n#endif  // SYSTEM_CORE_INCLUDE_MINCRYPT_HASH_INTERNAL_H_\n"
  },
  {
    "path": "panda/crypto/rsa.c",
    "content": "/* rsa.c\n**\n** Copyright 2012, The Android Open Source Project\n**\n** Redistribution and use in source and binary forms, with or without\n** modification, are permitted provided that the following conditions are met:\n**     * Redistributions of source code must retain the above copyright\n**       notice, this list of conditions and the following disclaimer.\n**     * Redistributions in binary form must reproduce the above copyright\n**       notice, this list of conditions and the following disclaimer in the\n**       documentation and/or other materials provided with the distribution.\n**     * Neither the name of Google Inc. nor the names of its contributors may\n**       be used to endorse or promote products derived from this software\n**       without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY Google Inc. ``AS IS'' AND ANY EXPRESS OR\n** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n** EVENT SHALL Google Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n** SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n** PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n** OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n** OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n** ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#include \"rsa.h\"\n#include \"sha.h\"\n\n// a[] -= mod\nstatic void subM(const RSAPublicKey* key,\n                 uint32_t* a) {\n    int64_t A = 0;\n    int i;\n    for (i = 0; i < key->len; ++i) {\n        A += (uint64_t)a[i] - key->n[i];\n        a[i] = (uint32_t)A;\n        A >>= 32;\n    }\n}\n\n// return a[] >= mod\nstatic int geM(const RSAPublicKey* key,\n               const uint32_t* a) {\n    int i;\n    for (i = key->len; i;) {\n        --i;\n        if (a[i] < key->n[i]) return 0;\n        if (a[i] > key->n[i]) return 1;\n    }\n    return 1;  // equal\n}\n\n// montgomery c[] += a * b[] / R % mod\nstatic void montMulAdd(const RSAPublicKey* key,\n                       uint32_t* c,\n                       const uint32_t a,\n                       const uint32_t* b) {\n    uint64_t A = (uint64_t)a * b[0] + c[0];\n    uint32_t d0 = (uint32_t)A * key->n0inv;\n    uint64_t B = (uint64_t)d0 * key->n[0] + (uint32_t)A;\n    int i;\n\n    for (i = 1; i < key->len; ++i) {\n        A = (A >> 32) + (uint64_t)a * b[i] + c[i];\n        B = (B >> 32) + (uint64_t)d0 * key->n[i] + (uint32_t)A;\n        c[i - 1] = (uint32_t)B;\n    }\n\n    A = (A >> 32) + (B >> 32);\n\n    c[i - 1] = (uint32_t)A;\n\n    if (A >> 32) {\n        subM(key, c);\n    }\n}\n\n// montgomery c[] = a[] * b[] / R % mod\nstatic void montMul(const RSAPublicKey* key,\n                    uint32_t* c,\n                    const uint32_t* a,\n                    const uint32_t* b) {\n    int i;\n    for (i = 0; i < key->len; ++i) {\n        c[i] = 0;\n    }\n    for (i = 0; i < key->len; ++i) {\n        montMulAdd(key, c, a[i], b);\n    }\n}\n\n// In-place public exponentiation.\n// Input and output big-endian byte array in inout.\nstatic void modpow(const RSAPublicKey* key,\n                   uint8_t* inout) {\n    uint32_t a[RSANUMWORDS];\n    uint32_t aR[RSANUMWORDS];\n    uint32_t aaR[RSANUMWORDS];\n    uint32_t* aaa = 0;\n    int i;\n\n    // Convert from big endian byte array to little endian word array.\n    for (i = 0; i < key->len; ++i) {\n        uint32_t tmp =\n            (inout[((key->len - 1 - i) * 4) + 0] << 24) |\n            (inout[((key->len - 1 - i) * 4) + 1] << 16) |\n            (inout[((key->len - 1 - i) * 4) + 2] << 8) |\n            (inout[((key->len - 1 - i) * 4) + 3] << 0);\n        a[i] = tmp;\n    }\n\n    if (key->exponent == 65537) {\n        aaa = aaR;  // Re-use location.\n        montMul(key, aR, a, key->rr);  // aR = a * RR / R mod M\n        for (i = 0; i < 16; i += 2) {\n            montMul(key, aaR, aR, aR);  // aaR = aR * aR / R mod M\n            montMul(key, aR, aaR, aaR);  // aR = aaR * aaR / R mod M\n        }\n        montMul(key, aaa, aR, a);  // aaa = aR * a / R mod M\n    } else if (key->exponent == 3) {\n        aaa = aR;  // Re-use location.\n        montMul(key, aR, a, key->rr);  /* aR = a * RR / R mod M   */\n        montMul(key, aaR, aR, aR);     /* aaR = aR * aR / R mod M */\n        montMul(key, aaa, aaR, a);     /* aaa = aaR * a / R mod M */\n    }\n\n    // Make sure aaa < mod; aaa is at most 1x mod too large.\n    if (geM(key, aaa)) {\n        subM(key, aaa);\n    }\n\n    // Convert to bigendian byte array\n    for (i = key->len - 1; i >= 0; --i) {\n        uint32_t tmp = aaa[i];\n        *inout++ = tmp >> 24;\n        *inout++ = tmp >> 16;\n        *inout++ = tmp >> 8;\n        *inout++ = tmp >> 0;\n    }\n}\n\n// Expected PKCS1.5 signature padding bytes, for a keytool RSA signature.\n// Has the 0-length optional parameter encoded in the ASN1 (as opposed to the\n// other flavor which omits the optional parameter entirely). This code does not\n// accept signatures without the optional parameter.\n\n/*\nstatic const uint8_t sha_padding[RSANUMBYTES] = {\n    0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30,\n    0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a,\n    0x05, 0x00, 0x04, 0x14,\n\n    // 20 bytes of hash go here.\n    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n};\n*/\n\nstatic const uint8_t sha_padding_1024[RSANUMBYTES] = {\n    0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    0xff, 0xff, 0xff, 0x00,\n\n    // 20 bytes of hash go here.\n    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n};\n\n// SHA-1 of PKCS1.5 signature sha_padding for 2048 bit, as above.\n// At the location of the bytes of the hash all 00 are hashed.\n/*static const uint8_t kExpectedPadShaRsa2048[SHA_DIGEST_SIZE] = {\n    0xdc, 0xbd, 0xbe, 0x42, 0xd5, 0xf5, 0xa7, 0x2e,\n    0x6e, 0xfc, 0xf5, 0x5d, 0xaf, 0x9d, 0xea, 0x68,\n    0x7c, 0xfb, 0xf1, 0x67\n};*/\n\n// Verify a 2048-bit RSA PKCS1.5 signature against an expected hash.\n// Both e=3 and e=65537 are supported.  hash_len may be\n// SHA_DIGEST_SIZE (== 20) to indicate a SHA-1 hash, or\n// SHA256_DIGEST_SIZE (== 32) to indicate a SHA-256 hash.  No other\n// values are supported.\n//\n// Returns 1 on successful verification, 0 on failure.\nint RSA_verify(const RSAPublicKey *key,\n               const uint8_t *signature,\n               const int len,\n               const uint8_t *hash,\n               const int hash_len) {\n    uint8_t buf[RSANUMBYTES];\n    int i;\n    //const uint8_t* padding_hash;\n\n    if (key->len != RSANUMWORDS) {\n        return 0;  // Wrong key passed in.\n    }\n\n    if (len != sizeof(buf)) {\n        return 0;  // Wrong input length.\n    }\n\n    if (hash_len != SHA_DIGEST_SIZE) {\n        return 0;  // Unsupported hash.\n    }\n\n    if (key->exponent != 3 && key->exponent != 65537) {\n        return 0;  // Unsupported exponent.\n    }\n\n    for (i = 0; i < len; ++i) {  // Copy input to local workspace.\n        buf[i] = signature[i];\n    }\n\n    modpow(key, buf);  // In-place exponentiation.\n\n#ifdef TEST_RSA\n    printf(\"sig\\n\");\n    for (i=0;i<len;i++) { if(i!=0 && i%0x10 == 0) printf(\"\\n\"); printf(\"%02X \", signature[i]); } printf(\"\\n\");\n    printf(\"hash\\n\");\n    for (i=0;i<hash_len;i++) { if(i!=0 && i%0x10 == 0) printf(\"\\n\"); printf(\"%02X \", hash[i]); } printf(\"\\n\");\n    printf(\"out\\n\");\n    for (i=0;i<RSANUMBYTES;i++) { if(i!=0 && i%0x10 == 0) printf(\"\\n\"); printf(\"%02X \", buf[i]); } printf(\"\\n\");\n    printf(\"target\\n\");\n    for (i=0;i<RSANUMBYTES;i++) { if(i!=0 && i%0x10 == 0) printf(\"\\n\"); printf(\"%02X \", sha_padding_1024[i]); } printf(\"\\n\");\n#endif\n\n    // Xor sha portion, so it all becomes 00 iff equal.\n    for (i = len - hash_len; i < len; ++i) {\n        buf[i] ^= *hash++;\n    }\n\n    // Hash resulting buf, in-place.\n    /*switch (hash_len) {\n        case SHA_DIGEST_SIZE:\n            padding_hash = kExpectedPadShaRsa2048;\n            SHA_hash(buf, len, buf);\n            break;\n        default:\n            return 0;\n    }\n\n\n    // Compare against expected hash value.\n    for (i = 0; i < hash_len; ++i) {\n        if (buf[i] != padding_hash[i]) {\n            return 0;\n        }\n    }*/\n\n    for (i = 0; i < RSANUMBYTES; ++i) {\n        if (buf[i] != sha_padding_1024[i]) {\n            return 0;\n        }\n    }\n\n    return 1;  // All checked out OK.\n}\n"
  },
  {
    "path": "panda/crypto/rsa.h",
    "content": "/* rsa.h\n**\n** Copyright 2008, The Android Open Source Project\n**\n** Redistribution and use in source and binary forms, with or without\n** modification, are permitted provided that the following conditions are met:\n**     * Redistributions of source code must retain the above copyright\n**       notice, this list of conditions and the following disclaimer.\n**     * Redistributions in binary form must reproduce the above copyright\n**       notice, this list of conditions and the following disclaimer in the\n**       documentation and/or other materials provided with the distribution.\n**     * Neither the name of Google Inc. nor the names of its contributors may\n**       be used to endorse or promote products derived from this software\n**       without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY Google Inc. ``AS IS'' AND ANY EXPRESS OR\n** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n** EVENT SHALL Google Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n** SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n** PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n** OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n** OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n** ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef SYSTEM_CORE_INCLUDE_MINCRYPT_RSA_H_\n#define SYSTEM_CORE_INCLUDE_MINCRYPT_RSA_H_\n\n#include \"stdint.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RSANUMBYTES 128           /* 1024 bit key length */\n#define RSANUMWORDS (RSANUMBYTES / sizeof(uint32_t))\n\ntypedef struct RSAPublicKey {\n    int len;                  /* Length of n[] in number of uint32_t */\n    uint32_t n0inv;           /* -1 / n[0] mod 2^32 */\n    uint32_t n[RSANUMWORDS];  /* modulus as little endian array */\n    uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */\n    int exponent;             /* 3 or 65537 */\n} RSAPublicKey;\n\nint RSA_verify(const RSAPublicKey *key,\n               const uint8_t* signature,\n               const int len,\n               const uint8_t* hash,\n               const int hash_len);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // SYSTEM_CORE_INCLUDE_MINCRYPT_RSA_H_\n"
  },
  {
    "path": "panda/crypto/sha.c",
    "content": "/* sha.c\n**\n** Copyright 2013, The Android Open Source Project\n**\n** Redistribution and use in source and binary forms, with or without\n** modification, are permitted provided that the following conditions are met:\n**     * Redistributions of source code must retain the above copyright\n**       notice, this list of conditions and the following disclaimer.\n**     * Redistributions in binary form must reproduce the above copyright\n**       notice, this list of conditions and the following disclaimer in the\n**       documentation and/or other materials provided with the distribution.\n**     * Neither the name of Google Inc. nor the names of its contributors may\n**       be used to endorse or promote products derived from this software\n**       without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY Google Inc. ``AS IS'' AND ANY EXPRESS OR\n** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n** EVENT SHALL Google Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n** SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n** PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n** OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n** OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n** ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n// Optimized for minimal code size.\n\nvoid *memcpy(void *str1, const void *str2, unsigned int n);\n\n#include \"sha.h\"\n\n#define rol(bits, value) (((value) << (bits)) | ((value) >> (32 - (bits))))\n\nstatic void SHA1_Transform(SHA_CTX* ctx) {\n    uint32_t W[80];\n    uint32_t A, B, C, D, E;\n    uint8_t* p = ctx->buf;\n    int t;\n\n    for(t = 0; t < 16; ++t) {\n        uint32_t tmp =  *p++ << 24;\n        tmp |= *p++ << 16;\n        tmp |= *p++ << 8;\n        tmp |= *p++;\n        W[t] = tmp;\n    }\n\n    for(; t < 80; t++) {\n        W[t] = rol(1,W[t-3] ^ W[t-8] ^ W[t-14] ^ W[t-16]);\n    }\n\n    A = ctx->state[0];\n    B = ctx->state[1];\n    C = ctx->state[2];\n    D = ctx->state[3];\n    E = ctx->state[4];\n\n    for(t = 0; t < 80; t++) {\n        uint32_t tmp = rol(5,A) + E + W[t];\n\n        if (t < 20)\n            tmp += (D^(B&(C^D))) + 0x5A827999;\n        else if ( t < 40)\n            tmp += (B^C^D) + 0x6ED9EBA1;\n        else if ( t < 60)\n            tmp += ((B&C)|(D&(B|C))) + 0x8F1BBCDC;\n        else\n            tmp += (B^C^D) + 0xCA62C1D6;\n\n        E = D;\n        D = C;\n        C = rol(30,B);\n        B = A;\n        A = tmp;\n    }\n\n    ctx->state[0] += A;\n    ctx->state[1] += B;\n    ctx->state[2] += C;\n    ctx->state[3] += D;\n    ctx->state[4] += E;\n}\n\nstatic const HASH_VTAB SHA_VTAB = {\n    SHA_init,\n    SHA_update,\n    SHA_final,\n    SHA_hash,\n    SHA_DIGEST_SIZE\n};\n\nvoid SHA_init(SHA_CTX* ctx) {\n    ctx->f = &SHA_VTAB;\n    ctx->state[0] = 0x67452301;\n    ctx->state[1] = 0xEFCDAB89;\n    ctx->state[2] = 0x98BADCFE;\n    ctx->state[3] = 0x10325476;\n    ctx->state[4] = 0xC3D2E1F0;\n    ctx->count = 0;\n}\n\n\nvoid SHA_update(SHA_CTX* ctx, const void* data, int len) {\n    int i = (int) (ctx->count & 63);\n    const uint8_t* p = (const uint8_t*)data;\n\n    ctx->count += len;\n\n    while (len--) {\n        ctx->buf[i++] = *p++;\n        if (i == 64) {\n            SHA1_Transform(ctx);\n            i = 0;\n        }\n    }\n}\n\n\nconst uint8_t* SHA_final(SHA_CTX* ctx) {\n    uint8_t *p = ctx->buf;\n    uint64_t cnt = ctx->count * 8;\n    int i;\n\n    SHA_update(ctx, (uint8_t*)\"\\x80\", 1);\n    while ((ctx->count & 63) != 56) {\n        SHA_update(ctx, (uint8_t*)\"\\0\", 1);\n    }\n\n    /* Hack - right shift operator with non const argument requires\n     *        libgcc.a which is missing in EON\n     *        thus expanding for loop from\n\n              for (i = 0; i < 8; ++i) {\n                  uint8_t tmp = (uint8_t) (cnt >> ((7 - i) * 8));\n                  SHA_update(ctx, &tmp, 1);\n              }\n\n              to\n     */\n\n    uint8_t tmp = 0;\n    tmp = (uint8_t) (cnt >> ((7 - 0) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 1) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 2) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 3) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 4) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 5) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 6) * 8));\n    SHA_update(ctx, &tmp, 1);\n    tmp = (uint8_t) (cnt >> ((7 - 7) * 8));\n    SHA_update(ctx, &tmp, 1);\n\n    for (i = 0; i < 5; i++) {\n        uint32_t tmp = ctx->state[i];\n        *p++ = tmp >> 24;\n        *p++ = tmp >> 16;\n        *p++ = tmp >> 8;\n        *p++ = tmp >> 0;\n    }\n\n    return ctx->buf;\n}\n\n/* Convenience function */\nconst uint8_t* SHA_hash(const void* data, int len, uint8_t* digest) {\n    SHA_CTX ctx;\n    SHA_init(&ctx);\n    SHA_update(&ctx, data, len);\n    memcpy(digest, SHA_final(&ctx), SHA_DIGEST_SIZE);\n    return digest;\n}\n"
  },
  {
    "path": "panda/crypto/sha.h",
    "content": "/*\n * Copyright 2005 The Android Open Source Project\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *     * Redistributions of source code must retain the above copyright\n *       notice, this list of conditions and the following disclaimer.\n *     * Redistributions in binary form must reproduce the above copyright\n *       notice, this list of conditions and the following disclaimer in the\n *       documentation and/or other materials provided with the distribution.\n *     * Neither the name of Google Inc. nor the names of its contributors may\n *       be used to endorse or promote products derived from this software\n *       without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY Google Inc. ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n * EVENT SHALL Google Inc. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef SYSTEM_CORE_INCLUDE_MINCRYPT_SHA1_H_\n#define SYSTEM_CORE_INCLUDE_MINCRYPT_SHA1_H_\n\n#include \"hash-internal.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif // __cplusplus\n\ntypedef HASH_CTX SHA_CTX;\n\nvoid SHA_init(SHA_CTX* ctx);\nvoid SHA_update(SHA_CTX* ctx, const void* data, int len);\nconst uint8_t* SHA_final(SHA_CTX* ctx);\n\n// Convenience method. Returns digest address.\n// NOTE: *digest needs to hold SHA_DIGEST_SIZE bytes.\nconst uint8_t* SHA_hash(const void* data, int len, uint8_t* digest);\n\n#define SHA_DIGEST_SIZE 20\n\n#ifdef __cplusplus\n}\n#endif // __cplusplus\n\n#endif  // SYSTEM_CORE_INCLUDE_MINCRYPT_SHA1_H_\n"
  },
  {
    "path": "panda/crypto/sign.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport sys\nimport struct\nimport hashlib\nfrom Crypto.PublicKey import RSA\nimport binascii\n\n# increment this to make new hardware not run old versions\nVERSION = 2\n\nrsa = RSA.importKey(open(sys.argv[3]).read())\n\nwith open(sys.argv[1], \"rb\") as f:\n  dat = f.read()\n\nprint(\"signing\", len(dat), \"bytes\")\n\nwith open(sys.argv[2], \"wb\") as f:\n  if os.getenv(\"SETLEN\") is not None:\n    # add the version at the end\n    dat += b\"VERS\" + struct.pack(\"I\", VERSION)\n    # add the length at the beginning\n    x = struct.pack(\"I\", len(dat)) + dat[4:]\n    # mock signature of dat[4:]\n    dd = hashlib.sha1(dat[4:]).digest()\n  else:\n    x = dat\n    dd = hashlib.sha1(dat).digest()\n\n  print(\"hash:\", str(binascii.hexlify(dd), \"utf-8\"))\n  dd = b\"\\x00\\x01\" + b\"\\xff\" * 0x69 + b\"\\x00\" + dd\n  rsa_out = pow(int.from_bytes(dd, byteorder='big', signed=False), rsa.d, rsa.n)\n  sig = (hex(rsa_out)[2:].rjust(0x100, '0'))\n  x += binascii.unhexlify(sig)\n  f.write(x)\n"
  },
  {
    "path": "panda/crypto/stdint.h",
    "content": "#define uint8_t unsigned char\n#define uint32_t unsigned int\n#define int64_t long long\n#define uint64_t unsigned long long\n"
  },
  {
    "path": "panda/examples/query_fw_versions.py",
    "content": "#!/usr/bin/env python3\nimport argparse\nfrom tqdm import tqdm\nfrom panda import Panda\nfrom panda.python.uds import UdsClient, MessageTimeoutError, NegativeResponseError, SESSION_TYPE, DATA_IDENTIFIER_TYPE\n\nif __name__ == \"__main__\":\n  parser = argparse.ArgumentParser()\n  parser.add_argument('--rxoffset', default=\"0x8\")\n  parser.add_argument('--nonstandard', action='store_true')\n  parser.add_argument('--debug', action='store_true')\n  parser.add_argument('--addr')\n  args = parser.parse_args()\n\n  if args.addr:\n    addrs = [int(args.addr, base=16)]\n  else:\n    addrs = [0x700 + i for i in range(256)]\n    addrs += [0x18da0000 + (i << 8) + 0xf1 for i in range(256)]\n  results = {}\n\n  uds_data_ids = {}\n  for std_id in DATA_IDENTIFIER_TYPE:\n    uds_data_ids[std_id.value] = std_id.name\n  if args.nonstandard:\n    for uds_id in range(0xf100,0xf180):\n      uds_data_ids[uds_id] = \"IDENTIFICATION_OPTION_VEHICLE_MANUFACTURER_SPECIFIC_DATA_IDENTIFIER\"\n    for uds_id in range(0xf1a0,0xf1f0):\n      uds_data_ids[uds_id] = \"IDENTIFICATION_OPTION_VEHICLE_MANUFACTURER_SPECIFIC\"\n    for uds_id in range(0xf1f0,0xf200):\n      uds_data_ids[uds_id] = \"IDENTIFICATION_OPTION_SYSTEM_SUPPLIER_SPECIFIC\"\n\n  panda = Panda()\n  panda.set_safety_mode(Panda.SAFETY_ELM327)\n  panda.set_power_save(0)\n  print(\"querying addresses ...\")\n  with tqdm(addrs) as t:\n    for addr in t:\n      # skip functional broadcast addrs\n      if addr == 0x7df or addr == 0x18db33f1:\n        continue\n      t.set_description(hex(addr))\n\n      uds_client = UdsClient(panda, addr, addr + int(args.rxoffset, base=16), bus=1 if panda.has_obd() else 0, timeout=0.2, debug=args.debug)\n      # Check for anything alive at this address, and switch to the highest\n      # available diagnostic session without security access\n      try:\n        uds_client.tester_present()\n        uds_client.diagnostic_session_control(SESSION_TYPE.DEFAULT)\n        uds_client.diagnostic_session_control(SESSION_TYPE.EXTENDED_DIAGNOSTIC)\n      except NegativeResponseError:\n        pass\n      except MessageTimeoutError:\n        continue\n\n      # Run queries against all standard UDS data identifiers, plus selected\n      # non-standardized identifier ranges if requested\n      resp = {}\n      for uds_data_id in sorted(uds_data_ids):\n        try:\n          data = uds_client.read_data_by_identifier(uds_data_id)  # type: ignore\n          if data:\n            resp[uds_data_id] = data\n        except (NegativeResponseError, MessageTimeoutError):\n          pass\n\n      if resp.keys():\n        results[addr] = resp\n\n    if len(results.items()):\n      for addr, resp in results.items():\n        print(f\"\\n\\n*** Results for address 0x{addr:X} ***\\n\\n\")\n        for rid, dat in resp.items():\n          print(f\"0x{rid:02X} {uds_data_ids[rid]}: {dat}\")\n    else:\n      print(\"no fw versions found!\")\n"
  },
  {
    "path": "panda/python/__init__.py",
    "content": "# python library to interface with panda\nimport datetime\nimport struct\nimport hashlib\nimport socket\nimport usb1\nimport os\nimport time\nimport traceback\nimport sys\nfrom .dfu import PandaDFU, MCU_TYPE_F2, MCU_TYPE_F4, MCU_TYPE_H7  # pylint: disable=import-error\nfrom .flash_release import flash_release  # noqa pylint: disable=import-error\nfrom .update import ensure_st_up_to_date  # noqa pylint: disable=import-error\nfrom .serial import PandaSerial  # noqa pylint: disable=import-error\nfrom .isotp import isotp_send, isotp_recv  # pylint: disable=import-error\nfrom .config import DEFAULT_FW_FN, DEFAULT_H7_FW_FN  # noqa pylint: disable=import-error\n\n__version__ = '0.0.9'\n\nBASEDIR = os.path.join(os.path.dirname(os.path.realpath(__file__)), \"../\")\n\nDEBUG = os.getenv(\"PANDADEBUG\") is not None\n\ndef parse_can_buffer(dat):\n  ret = []\n  for j in range(0, len(dat), 0x10):\n    ddat = dat[j:j + 0x10]\n    f1, f2 = struct.unpack(\"II\", ddat[0:8])\n    extended = 4\n    if f1 & extended:\n      address = f1 >> 3\n    else:\n      address = f1 >> 21\n    dddat = ddat[8:8 + (f2 & 0xF)]\n    if DEBUG:\n      print(f\"  R 0x{address:x}: 0x{dddat.hex()}\")\n    ret.append((address, f2 >> 16, dddat, (f2 >> 4) & 0xFF))\n  return ret\n\nclass PandaWifiStreaming(object):\n  def __init__(self, ip=\"192.168.0.10\", port=1338):\n    self.sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)\n    self.sock.setblocking(0)\n    self.ip = ip\n    self.port = port\n    self.kick()\n\n  def kick(self):\n    # must be called at least every 5 seconds\n    self.sock.sendto(\"hello\", (self.ip, self.port))\n\n  def can_recv(self):\n    ret = []\n    while True:\n      try:\n        dat, addr = self.sock.recvfrom(0x200 * 0x10)\n        if addr == (self.ip, self.port):\n          ret += parse_can_buffer(dat)\n      except socket.error as e:\n        if e.errno != 35 and e.errno != 11:\n          traceback.print_exc()\n        break\n    return ret\n\n# stupid tunneling of USB over wifi and SPI\nclass WifiHandle(object):\n  def __init__(self, ip=\"192.168.0.10\", port=1337):\n    self.sock = socket.create_connection((ip, port))\n\n  def __recv(self):\n    ret = self.sock.recv(0x44)\n    length = struct.unpack(\"I\", ret[0:4])[0]\n    return ret[4:4 + length]\n\n  def controlWrite(self, request_type, request, value, index, data, timeout=0):\n    # ignore data in reply, panda doesn't use it\n    return self.controlRead(request_type, request, value, index, 0, timeout)\n\n  def controlRead(self, request_type, request, value, index, length, timeout=0):\n    self.sock.send(struct.pack(\"HHBBHHH\", 0, 0, request_type, request, value, index, length))\n    return self.__recv()\n\n  def bulkWrite(self, endpoint, data, timeout=0):\n    if len(data) > 0x10:\n      raise ValueError(\"Data must not be longer than 0x10\")\n    self.sock.send(struct.pack(\"HH\", endpoint, len(data)) + data)\n    self.__recv()  # to /dev/null\n\n  def bulkRead(self, endpoint, length, timeout=0):\n    self.sock.send(struct.pack(\"HH\", endpoint, 0))\n    return self.__recv()\n\n  def close(self):\n    self.sock.close()\n\n# *** normal mode ***\n\nclass Panda(object):\n\n  # matches cereal.car.CarParams.SafetyModel\n  SAFETY_SILENT = 0\n  SAFETY_HONDA_NIDEC = 1\n  SAFETY_TOYOTA = 2\n  SAFETY_ELM327 = 3\n  SAFETY_GM = 4\n  SAFETY_HONDA_BOSCH_GIRAFFE = 5\n  SAFETY_FORD = 6\n  SAFETY_HYUNDAI = 8\n  SAFETY_CHRYSLER = 9\n  SAFETY_TESLA = 10\n  SAFETY_SUBARU = 11\n  SAFETY_MAZDA = 13\n  SAFETY_NISSAN = 14\n  SAFETY_VOLKSWAGEN_MQB = 15\n  SAFETY_ALLOUTPUT = 17\n  SAFETY_GM_ASCM = 18\n  SAFETY_NOOUTPUT = 19\n  SAFETY_HONDA_BOSCH_HARNESS = 20\n  SAFETY_VOLKSWAGEN_PQ = 21\n  SAFETY_SUBARU_LEGACY = 22\n  SAFETY_HYUNDAI_LEGACY = 23\n\n  SERIAL_DEBUG = 0\n  SERIAL_ESP = 1\n  SERIAL_LIN1 = 2\n  SERIAL_LIN2 = 3\n\n  GMLAN_CAN2 = 1\n  GMLAN_CAN3 = 2\n\n  REQUEST_IN = usb1.ENDPOINT_IN | usb1.TYPE_VENDOR | usb1.RECIPIENT_DEVICE\n  REQUEST_OUT = usb1.ENDPOINT_OUT | usb1.TYPE_VENDOR | usb1.RECIPIENT_DEVICE\n\n  HW_TYPE_UNKNOWN = b'\\x00'\n  HW_TYPE_WHITE_PANDA = b'\\x01'\n  HW_TYPE_GREY_PANDA = b'\\x02'\n  HW_TYPE_BLACK_PANDA = b'\\x03'\n  HW_TYPE_PEDAL = b'\\x04'\n  HW_TYPE_UNO = b'\\x05'\n  HW_TYPE_DOS = b'\\x06'\n  HW_TYPE_RED_PANDA = b'\\x07'\n\n  F2_DEVICES = [HW_TYPE_PEDAL]\n  F4_DEVICES = [HW_TYPE_WHITE_PANDA, HW_TYPE_GREY_PANDA, HW_TYPE_BLACK_PANDA, HW_TYPE_UNO, HW_TYPE_DOS]\n  H7_DEVICES = [HW_TYPE_RED_PANDA]\n\n  CLOCK_SOURCE_MODE_DISABLED = 0\n  CLOCK_SOURCE_MODE_FREE_RUNNING = 1\n  CLOCK_SOURCE_MODE_EXTERNAL_SYNC = 2\n\n  FLAG_HONDA_ALT_BRAKE = 1\n  FLAG_HONDA_BOSCH_LONG = 2\n\n  def __init__(self, serial=None, claim=True):\n    self._serial = serial\n    self._handle = None\n    self.connect(claim)\n    self._mcu_type = self.get_mcu_type()\n\n  def close(self):\n    self._handle.close()\n    self._handle = None\n\n  def connect(self, claim=True, wait=False):\n    if self._handle is not None:\n      self.close()\n\n    if self._serial == \"WIFI\":\n      self._handle = WifiHandle()\n      print(\"opening WIFI device\")\n      self.wifi = True\n    else:\n      context = usb1.USBContext()\n      self._handle = None\n      self.wifi = False\n\n      while 1:\n        try:\n          for device in context.getDeviceList(skip_on_error=True):\n            if device.getVendorID() == 0xbbaa and device.getProductID() in [0xddcc, 0xddee]:\n              try:\n                this_serial = device.getSerialNumber()\n              except Exception:\n                continue\n              if self._serial is None or this_serial == self._serial:\n                self._serial = this_serial\n                print(\"opening device\", self._serial, hex(device.getProductID()))\n                self.bootstub = device.getProductID() == 0xddee\n                self._handle = device.open()\n                if sys.platform not in [\"win32\", \"cygwin\", \"msys\", \"darwin\"]:\n                  self._handle.setAutoDetachKernelDriver(True)\n                if claim:\n                  self._handle.claimInterface(0)\n                  # self._handle.setInterfaceAltSetting(0, 0)  # Issue in USB stack\n                break\n        except Exception as e:\n          print(\"exception\", e)\n          traceback.print_exc()\n        if not wait or self._handle is not None:\n          break\n        context = usb1.USBContext()  # New context needed so new devices show up\n    assert(self._handle is not None)\n    print(\"connected\")\n\n  def reset(self, enter_bootstub=False, enter_bootloader=False):\n    # reset\n    try:\n      if enter_bootloader:\n        self._handle.controlWrite(Panda.REQUEST_IN, 0xd1, 0, 0, b'')\n      else:\n        if enter_bootstub:\n          self._handle.controlWrite(Panda.REQUEST_IN, 0xd1, 1, 0, b'')\n        else:\n          self._handle.controlWrite(Panda.REQUEST_IN, 0xd8, 0, 0, b'')\n    except Exception:\n      pass\n    if not enter_bootloader:\n      self.reconnect()\n\n  def reconnect(self):\n    self.close()\n    time.sleep(1.0)\n    success = False\n    # wait up to 15 seconds\n    for i in range(0, 15):\n      try:\n        self.connect()\n        success = True\n        break\n      except Exception:\n        print(\"reconnecting is taking %d seconds...\" % (i + 1))\n        try:\n          dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(self._serial, self._mcu_type))\n          dfu.recover()\n        except Exception:\n          pass\n        time.sleep(1.0)\n    if not success:\n      raise Exception(\"reconnect failed\")\n\n  @staticmethod\n  def flash_static(handle, code):\n    # confirm flasher is present\n    fr = handle.controlRead(Panda.REQUEST_IN, 0xb0, 0, 0, 0xc)\n    assert fr[4:8] == b\"\\xde\\xad\\xd0\\x0d\"\n\n    # unlock flash\n    print(\"flash: unlocking\")\n    handle.controlWrite(Panda.REQUEST_IN, 0xb1, 0, 0, b'')\n\n    # erase sectors 1 through 3\n    print(\"flash: erasing\")\n    for i in range(1, 4):\n      handle.controlWrite(Panda.REQUEST_IN, 0xb2, i, 0, b'')\n\n    # flash over EP2\n    STEP = 0x10\n    print(\"flash: flashing\")\n    for i in range(0, len(code), STEP):\n      handle.bulkWrite(2, code[i:i + STEP])\n\n    # reset\n    print(\"flash: resetting\")\n    try:\n      handle.controlWrite(Panda.REQUEST_IN, 0xd8, 0, 0, b'')\n    except Exception:\n      pass\n\n  def flash(self, fn=DEFAULT_FW_FN, code=None, reconnect=True):\n    if self._mcu_type == MCU_TYPE_H7 and fn == DEFAULT_FW_FN:\n      fn = DEFAULT_H7_FW_FN\n    print(\"flash: main version is \" + self.get_version())\n    if not self.bootstub:\n      self.reset(enter_bootstub=True)\n    assert(self.bootstub)\n\n    if code is None:\n      with open(fn, \"rb\") as f:\n        code = f.read()\n\n    # get version\n    print(\"flash: bootstub version is \" + self.get_version())\n\n    # do flash\n    Panda.flash_static(self._handle, code)\n\n    # reconnect\n    if reconnect:\n      self.reconnect()\n\n  def recover(self, timeout=None):\n    self.reset(enter_bootstub=True)\n    self.reset(enter_bootloader=True)\n    t_start = time.time()\n    while len(PandaDFU.list()) == 0:\n      print(\"waiting for DFU...\")\n      time.sleep(0.1)\n      if timeout is not None and (time.time() - t_start) > timeout:\n        return False\n\n    dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(self._serial, self._mcu_type))\n    dfu.recover()\n\n    # reflash after recover\n    self.connect(True, True)\n    self.flash()\n    return True\n\n  @staticmethod\n  def flash_ota_st():\n    ret = os.system(\"cd %s && make clean && make ota\" % (os.path.join(BASEDIR, \"board\")))\n    time.sleep(1)\n    return ret == 0\n\n  @staticmethod\n  def flash_ota_wifi(release=False):\n    release_str = \"RELEASE=1\" if release else \"\"\n    ret = os.system(\"cd {} && make clean && {} make ota\".format(os.path.join(BASEDIR, \"boardesp\"), release_str))\n    time.sleep(1)\n    return ret == 0\n\n  @staticmethod\n  def list():\n    context = usb1.USBContext()\n    ret = []\n    try:\n      for device in context.getDeviceList(skip_on_error=True):\n        if device.getVendorID() == 0xbbaa and device.getProductID() in [0xddcc, 0xddee]:\n          try:\n            ret.append(device.getSerialNumber())\n          except Exception:\n            continue\n    except Exception:\n      pass\n    # TODO: detect if this is real\n    # ret += [\"WIFI\"]\n    return ret\n\n  def call_control_api(self, msg):\n    self._handle.controlWrite(Panda.REQUEST_OUT, msg, 0, 0, b'')\n\n  # ******************* health *******************\n\n  def health(self):\n    dat = self._handle.controlRead(Panda.REQUEST_IN, 0xd2, 0, 0, 44)\n    a = struct.unpack(\"<IIIIIIIIBBBBBBBHBBB\", dat)\n    return {\n      \"uptime\": a[0],\n      \"voltage\": a[1],\n      \"current\": a[2],\n      \"can_rx_errs\": a[3],\n      \"can_send_errs\": a[4],\n      \"can_fwd_errs\": a[5],\n      \"gmlan_send_errs\": a[6],\n      \"faults\": a[7],\n      \"ignition_line\": a[8],\n      \"ignition_can\": a[9],\n      \"controls_allowed\": a[10],\n      \"gas_interceptor_detected\": a[11],\n      \"car_harness_status\": a[12],\n      \"usb_power_mode\": a[13],\n      \"safety_mode\": a[14],\n      \"safety_param\": a[15],\n      \"fault_status\": a[16],\n      \"power_save_enabled\": a[17],\n      \"heartbeat_lost\": a[18],\n    }\n\n  # ******************* control *******************\n\n  def enter_bootloader(self):\n    try:\n      self._handle.controlWrite(Panda.REQUEST_OUT, 0xd1, 0, 0, b'')\n    except Exception as e:\n      print(e)\n\n  def get_version(self):\n    return self._handle.controlRead(Panda.REQUEST_IN, 0xd6, 0, 0, 0x40).decode('utf8')\n\n  @staticmethod\n  def get_signature_from_firmware(fn):\n    f = open(fn, 'rb')\n    f.seek(-128, 2)  # Seek from end of file\n    return f.read(128)\n\n  def get_signature(self):\n    part_1 = self._handle.controlRead(Panda.REQUEST_IN, 0xd3, 0, 0, 0x40)\n    part_2 = self._handle.controlRead(Panda.REQUEST_IN, 0xd4, 0, 0, 0x40)\n    return bytes(part_1 + part_2)\n\n  def get_type(self):\n    return self._handle.controlRead(Panda.REQUEST_IN, 0xc1, 0, 0, 0x40)\n\n  def is_white(self):\n    return self.get_type() == Panda.HW_TYPE_WHITE_PANDA\n\n  def is_grey(self):\n    return self.get_type() == Panda.HW_TYPE_GREY_PANDA\n\n  def is_black(self):\n    return self.get_type() == Panda.HW_TYPE_BLACK_PANDA\n\n  def is_pedal(self):\n    return self.get_type() == Panda.HW_TYPE_PEDAL\n\n  def is_uno(self):\n    return self.get_type() == Panda.HW_TYPE_UNO\n\n  def is_dos(self):\n    return self.get_type() == Panda.HW_TYPE_DOS\n  \n  def is_red(self):\n    return self.get_type() == Panda.HW_TYPE_RED_PANDA\n\n  def get_mcu_type(self):\n    hw_type = self.get_type()\n    if hw_type in Panda.F2_DEVICES:\n      return MCU_TYPE_F2\n    elif hw_type in Panda.F4_DEVICES:\n      return MCU_TYPE_F4\n    elif hw_type in Panda.H7_DEVICES:\n      return MCU_TYPE_H7\n    return None\n\n  def has_obd(self):\n    return (self.is_uno() or self.is_dos() or self.is_black() or self.is_red())\n\n  def has_canfd(self):\n    return self._mcu_type in Panda.H7_DEVICES\n\n  def get_serial(self):\n    dat = self._handle.controlRead(Panda.REQUEST_IN, 0xd0, 0, 0, 0x20)\n    hashsig, calc_hash = dat[0x1c:], hashlib.sha1(dat[0:0x1c]).digest()[0:4]\n    assert(hashsig == calc_hash)\n    return [dat[0:0x10].decode(\"utf8\"), dat[0x10:0x10 + 10].decode(\"utf8\")]\n\n  def get_secret(self):\n    return self._handle.controlRead(Panda.REQUEST_IN, 0xd0, 1, 0, 0x10)\n\n  # ******************* configuration *******************\n\n  def set_usb_power(self, on):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xe6, int(on), 0, b'')\n\n  def set_power_save(self, power_save_enabled=0):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xe7, int(power_save_enabled), 0, b'')\n\n  def set_esp_power(self, on):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xd9, int(on), 0, b'')\n\n  def esp_reset(self, bootmode=0):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xda, int(bootmode), 0, b'')\n    time.sleep(0.2)\n\n  def set_safety_mode(self, mode=SAFETY_SILENT, disable_heartbeat=True):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xdc, mode, 0, b'')\n    if disable_heartbeat:\n      self.set_heartbeat_disabled()\n\n  def set_can_forwarding(self, from_bus, to_bus):\n    # TODO: This feature may not work correctly with saturated buses\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xdd, from_bus, to_bus, b'')\n\n  def set_gmlan(self, bus=2):\n    # TODO: check panda type\n    if bus is None:\n      self._handle.controlWrite(Panda.REQUEST_OUT, 0xdb, 0, 0, b'')\n    elif bus in [Panda.GMLAN_CAN2, Panda.GMLAN_CAN3]:\n      self._handle.controlWrite(Panda.REQUEST_OUT, 0xdb, 1, bus, b'')\n\n  def set_obd(self, obd):\n    # TODO: check panda type\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xdb, int(obd), 0, b'')\n\n  def set_can_loopback(self, enable):\n    # set can loopback mode for all buses\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xe5, int(enable), 0, b'')\n\n  def set_can_enable(self, bus_num, enable):\n    # sets the can transceiver enable pin\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf4, int(bus_num), int(enable), b'')\n\n  def set_can_speed_kbps(self, bus, speed):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xde, bus, int(speed * 10), b'')\n\n  def set_can_data_speed_kbps(self, bus, speed):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf9, bus, int(speed * 10), b'')\n\n  def set_uart_baud(self, uart, rate):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xe4, uart, int(rate / 300), b'')\n\n  def set_uart_parity(self, uart, parity):\n    # parity, 0=off, 1=even, 2=odd\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xe2, uart, parity, b'')\n\n  def set_uart_callback(self, uart, install):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xe3, uart, int(install), b'')\n\n  # ******************* can *******************\n\n  # The panda will NAK CAN writes when there is CAN congestion.\n  # libusb will try to send it again, with a max timeout.\n  # Timeout is in ms. If set to 0, the timeout is infinite.\n  CAN_SEND_TIMEOUT_MS = 10\n\n  def can_send_many(self, arr, timeout=CAN_SEND_TIMEOUT_MS):\n    snds = []\n    transmit = 1\n    extended = 4\n    for addr, _, dat, bus in arr:\n      assert len(dat) <= 8\n      if DEBUG:\n        print(f\"  W 0x{addr:x}: 0x{dat.hex()}\")\n      if addr >= 0x800:\n        rir = (addr << 3) | transmit | extended\n      else:\n        rir = (addr << 21) | transmit\n      snd = struct.pack(\"II\", rir, len(dat) | (bus << 4)) + dat\n      snd = snd.ljust(0x10, b'\\x00')\n      snds.append(snd)\n\n    while True:\n      try:\n        if self.wifi:\n          for s in snds:\n            self._handle.bulkWrite(3, s)\n        else:\n          self._handle.bulkWrite(3, b''.join(snds), timeout=timeout)\n        break\n      except (usb1.USBErrorIO, usb1.USBErrorOverflow):\n        print(\"CAN: BAD SEND MANY, RETRYING\")\n\n  def can_send(self, addr, dat, bus, timeout=CAN_SEND_TIMEOUT_MS):\n    self.can_send_many([[addr, None, dat, bus]], timeout=timeout)\n\n  def can_recv(self):\n    dat = bytearray()\n    while True:\n      try:\n        dat = self._handle.bulkRead(1, 0x10 * 256)\n        break\n      except (usb1.USBErrorIO, usb1.USBErrorOverflow):\n        print(\"CAN: BAD RECV, RETRYING\")\n        time.sleep(0.1)\n    return parse_can_buffer(dat)\n\n  def can_clear(self, bus):\n    \"\"\"Clears all messages from the specified internal CAN ringbuffer as\n    though it were drained.\n\n    Args:\n      bus (int): can bus number to clear a tx queue, or 0xFFFF to clear the\n        global can rx queue.\n\n    \"\"\"\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf1, bus, 0, b'')\n\n  # ******************* isotp *******************\n\n  def isotp_send(self, addr, dat, bus, recvaddr=None, subaddr=None):\n    return isotp_send(self, dat, addr, bus, recvaddr, subaddr)\n\n  def isotp_recv(self, addr, bus=0, sendaddr=None, subaddr=None):\n    return isotp_recv(self, addr, bus, sendaddr, subaddr)\n\n  # ******************* serial *******************\n\n  def serial_read(self, port_number):\n    ret = []\n    while 1:\n      lret = bytes(self._handle.controlRead(Panda.REQUEST_IN, 0xe0, port_number, 0, 0x40))\n      if len(lret) == 0:\n        break\n      ret.append(lret)\n    return b''.join(ret)\n\n  def serial_write(self, port_number, ln):\n    ret = 0\n    for i in range(0, len(ln), 0x20):\n      ret += self._handle.bulkWrite(2, struct.pack(\"B\", port_number) + ln[i:i + 0x20])\n    return ret\n\n  def serial_clear(self, port_number):\n    \"\"\"Clears all messages (tx and rx) from the specified internal uart\n    ringbuffer as though it were drained.\n\n    Args:\n      port_number (int): port number of the uart to clear.\n\n    \"\"\"\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf2, port_number, 0, b'')\n\n  # ******************* kline *******************\n\n  # pulse low for wakeup\n  def kline_wakeup(self, k=True, l=True):\n    assert k or l, \"must specify k-line, l-line, or both\"\n    if DEBUG:\n      print(\"kline wakeup...\")\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf0, 2 if k and l else int(l), 0, b'')\n    if DEBUG:\n      print(\"kline wakeup done\")\n\n  def kline_5baud(self, addr, k=True, l=True):\n    assert k or l, \"must specify k-line, l-line, or both\"\n    if DEBUG:\n      print(\"kline 5 baud...\")\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf4, 2 if k and l else int(l), addr, b'')\n    if DEBUG:\n      print(\"kline 5 baud done\")\n\n  def kline_drain(self, bus=2):\n    # drain buffer\n    bret = bytearray()\n    while True:\n      ret = self._handle.controlRead(Panda.REQUEST_IN, 0xe0, bus, 0, 0x40)\n      if len(ret) == 0:\n        break\n      elif DEBUG:\n        print(f\"kline drain: 0x{ret.hex()}\")\n      bret += ret\n    return bytes(bret)\n\n  def kline_ll_recv(self, cnt, bus=2):\n    echo = bytearray()\n    while len(echo) != cnt:\n      ret = self._handle.controlRead(Panda.REQUEST_OUT, 0xe0, bus, 0, cnt - len(echo))\n      if DEBUG and len(ret) > 0:\n        print(f\"kline recv: 0x{ret.hex()}\")\n      echo += ret\n    return bytes(echo)\n\n  def kline_send(self, x, bus=2, checksum=True):\n    self.kline_drain(bus=bus)\n    if checksum:\n      x += bytes([sum(x) % 0x100])\n    for i in range(0, len(x), 0xf):\n      ts = x[i:i + 0xf]\n      if DEBUG:\n        print(f\"kline send: 0x{ts.hex()}\")\n      self._handle.bulkWrite(2, bytes([bus]) + ts)\n      echo = self.kline_ll_recv(len(ts), bus=bus)\n      if echo != ts:\n        print(f\"**** ECHO ERROR {i} ****\")\n        print(f\"0x{echo.hex()}\")\n        print(f\"0x{ts.hex()}\")\n    assert echo == ts\n\n  def kline_recv(self, bus=2, header_len=4):\n    # read header (last byte is length)\n    msg = self.kline_ll_recv(header_len, bus=bus)\n    # read data (add one byte to length for checksum)\n    msg += self.kline_ll_recv(msg[-1]+1, bus=bus)\n    return msg\n\n  def send_heartbeat(self):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf3, 0, 0, b'')\n\n  # disable heartbeat checks for use outside of openpilot\n  # sending a heartbeat will reenable the checks\n  def set_heartbeat_disabled(self):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf8, 0, 0, b'')\n\n  # ******************* RTC *******************\n  def set_datetime(self, dt):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa1, int(dt.year), 0, b'')\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa2, int(dt.month), 0, b'')\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa3, int(dt.day), 0, b'')\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa4, int(dt.isoweekday()), 0, b'')\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa5, int(dt.hour), 0, b'')\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa6, int(dt.minute), 0, b'')\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xa7, int(dt.second), 0, b'')\n\n  def get_datetime(self):\n    dat = self._handle.controlRead(Panda.REQUEST_IN, 0xa0, 0, 0, 8)\n    a = struct.unpack(\"HBBBBBB\", dat)\n    return datetime.datetime(a[0], a[1], a[2], a[4], a[5], a[6])\n\n  # ******************* IR *******************\n  def set_ir_power(self, percentage):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xb0, int(percentage), 0, b'')\n\n  # ******************* Fan ******************\n  def set_fan_power(self, percentage):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xb1, int(percentage), 0, b'')\n\n  def get_fan_rpm(self):\n    dat = self._handle.controlRead(Panda.REQUEST_IN, 0xb2, 0, 0, 2)\n    a = struct.unpack(\"H\", dat)\n    return a[0]\n\n  # ****************** Phone *****************\n  def set_phone_power(self, enabled):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xb3, int(enabled), 0, b'')\n\n  # ************** Clock Source **************\n  def set_clock_source_mode(self, mode):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf5, int(mode), 0, b'')\n\n  # ****************** Siren *****************\n  def set_siren(self, enabled):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf6, int(enabled), 0, b'')\n\n  # ****************** Debug *****************\n  def set_green_led(self, enabled):\n    self._handle.controlWrite(Panda.REQUEST_OUT, 0xf7, int(enabled), 0, b'')\n"
  },
  {
    "path": "panda/python/config.py",
    "content": "import os\n\n\nBASEDIR = os.path.join(os.path.dirname(os.path.realpath(__file__)), \"../\")\n\nBOOTSTUB_ADDRESS = 0x8000000\n\nBLOCK_SIZE_FX = 0x800\nAPP_ADDRESS_FX = 0x8004000\nDEVICE_SERIAL_NUMBER_ADDR_FX = 0x1FFF79C0\nDEFAULT_FW_FN = os.path.join(BASEDIR, \"board\", \"obj\", \"panda.bin.signed\")\nDEFAULT_BOOTSTUB_FN = os.path.join(BASEDIR, \"board\", \"obj\", \"bootstub.panda.bin\")\n\nBLOCK_SIZE_H7 = 0x400\nAPP_ADDRESS_H7 = 0x8020000\nDEVICE_SERIAL_NUMBER_ADDR_H7 = 0x080FFFC0\nDEFAULT_H7_FW_FN = os.path.join(BASEDIR, \"board\", \"obj\", \"panda_h7.bin.signed\")\nDEFAULT_H7_BOOTSTUB_FN = os.path.join(BASEDIR, \"board\", \"obj\", \"bootstub.panda_h7.bin\")\n"
  },
  {
    "path": "panda/python/dfu.py",
    "content": "import usb1\nimport struct\nimport binascii\nfrom .config import BOOTSTUB_ADDRESS, APP_ADDRESS_H7, APP_ADDRESS_FX, BLOCK_SIZE_H7, BLOCK_SIZE_FX, DEFAULT_H7_BOOTSTUB_FN, DEFAULT_BOOTSTUB_FN\n\n\nMCU_TYPE_F2 = 0\nMCU_TYPE_F4 = 1\nMCU_TYPE_H7 = 2\n\n# *** DFU mode ***\nDFU_DNLOAD = 1\nDFU_UPLOAD = 2\nDFU_GETSTATUS = 3\nDFU_CLRSTATUS = 4\nDFU_ABORT = 6\n\nclass PandaDFU(object):\n  def __init__(self, dfu_serial):\n    context = usb1.USBContext()\n    for device in context.getDeviceList(skip_on_error=True):\n      if device.getVendorID() == 0x0483 and device.getProductID() == 0xdf11:\n        try:\n          this_dfu_serial = device.open().getASCIIStringDescriptor(3)\n        except Exception:\n          continue\n        if this_dfu_serial == dfu_serial or dfu_serial is None:\n          self._mcu_type = self.get_mcu_type(device)\n          self._handle = device.open()\n          return\n    raise Exception(\"failed to open \" + dfu_serial if dfu_serial is not None else \"DFU device\")\n\n  @staticmethod\n  def list():\n    context = usb1.USBContext()\n    dfu_serials = []\n    try:\n      for device in context.getDeviceList(skip_on_error=True):\n        if device.getVendorID() == 0x0483 and device.getProductID() == 0xdf11:\n          try:\n            dfu_serials.append(device.open().getASCIIStringDescriptor(3))\n          except Exception:\n            pass\n    except Exception:\n      pass\n    return dfu_serials\n\n  @staticmethod\n  def st_serial_to_dfu_serial(st, mcu_type=MCU_TYPE_F4):\n    if st is None or st == \"none\":\n      return None\n    uid_base = struct.unpack(\"H\" * 6, bytes.fromhex(st))\n    if mcu_type == MCU_TYPE_H7:\n      return binascii.hexlify(struct.pack(\"!HHH\", uid_base[1] + uid_base[5], uid_base[0] + uid_base[4], uid_base[3])).upper().decode(\"utf-8\")\n    else:\n      return binascii.hexlify(struct.pack(\"!HHH\", uid_base[1] + uid_base[5], uid_base[0] + uid_base[4] + 0xA, uid_base[3])).upper().decode(\"utf-8\")\n\n  # TODO: Find a way to detect F4 vs F2\n  def get_mcu_type(self, dev):\n    return MCU_TYPE_H7 if dev.getbcdDevice() == 512 else MCU_TYPE_F4\n\n  def status(self):\n    while 1:\n      dat = self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6)\n      if dat[1] == 0:\n        break\n\n  def clear_status(self):\n    # Clear status\n    stat = self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6)\n    if stat[4] == 0xa:\n      self._handle.controlRead(0x21, DFU_CLRSTATUS, 0, 0, 0)\n    elif stat[4] == 0x9:\n      self._handle.controlWrite(0x21, DFU_ABORT, 0, 0, b\"\")\n      self.status()\n    stat = str(self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6))\n\n  def erase(self, address):\n    self._handle.controlWrite(0x21, DFU_DNLOAD, 0, 0, b\"\\x41\" + struct.pack(\"I\", address))\n    self.status()\n\n  def program(self, address, dat, block_size=None):\n    if block_size is None:\n      block_size = len(dat)\n\n    # Set Address Pointer\n    self._handle.controlWrite(0x21, DFU_DNLOAD, 0, 0, b\"\\x21\" + struct.pack(\"I\", address))\n    self.status()\n\n    # Program\n    dat += b\"\\xFF\" * ((block_size - len(dat)) % block_size)\n    for i in range(0, len(dat) // block_size):\n      ldat = dat[i * block_size:(i + 1) * block_size]\n      print(\"programming %d with length %d\" % (i, len(ldat)))\n      self._handle.controlWrite(0x21, DFU_DNLOAD, 2 + i, 0, ldat)\n      self.status()\n\n  def program_bootstub(self, code_bootstub):\n    self.clear_status()\n    self.erase(BOOTSTUB_ADDRESS)\n    if self._mcu_type == MCU_TYPE_H7:\n      self.erase(APP_ADDRESS_H7)\n      self.program(BOOTSTUB_ADDRESS, code_bootstub, BLOCK_SIZE_H7)\n    else:\n      self.erase(APP_ADDRESS_FX)\n      self.program(BOOTSTUB_ADDRESS, code_bootstub, BLOCK_SIZE_FX)\n    self.reset()\n\n  def recover(self):\n    fn = DEFAULT_H7_BOOTSTUB_FN if self._mcu_type == MCU_TYPE_H7 else DEFAULT_BOOTSTUB_FN\n\n    with open(fn, \"rb\") as f:\n      code = f.read()\n\n    self.program_bootstub(code)\n\n  def reset(self):\n    # **** Reset ****\n    self._handle.controlWrite(0x21, DFU_DNLOAD, 0, 0, b\"\\x21\" + struct.pack(\"I\", BOOTSTUB_ADDRESS))\n    self.status()\n    try:\n      self._handle.controlWrite(0x21, DFU_DNLOAD, 2, 0, b\"\")\n      _ = str(self._handle.controlRead(0x21, DFU_GETSTATUS, 0, 0, 6))\n    except Exception:\n      pass\n"
  },
  {
    "path": "panda/python/flash_release.py",
    "content": "#!/usr/bin/env python3\n\nimport sys\nimport time\nimport requests\nimport json\nimport io\n\ndef flash_release(path=None, st_serial=None):\n  from panda import Panda, PandaDFU\n  from zipfile import ZipFile\n\n  def status(x):\n    print(\"\\033[1;32;40m\" + x + \"\\033[00m\")\n\n  if st_serial is not None:\n    # look for Panda\n    panda_list = Panda.list()\n    if len(panda_list) == 0:\n      raise Exception(\"panda not found, make sure it's connected and your user can access it\")\n    elif len(panda_list) > 1:\n      raise Exception(\"Please only connect one panda\")\n    st_serial = panda_list[0]\n    print(\"Using panda with serial %s\" % st_serial)\n\n  if path is None:\n    print(\"Fetching latest firmware from github.com/commaai/panda-artifacts\")\n    r = requests.get(\"https://raw.githubusercontent.com/commaai/panda-artifacts/master/latest.json\")\n    url = json.loads(r.text)['url']\n    r = requests.get(url)\n    print(\"Fetching firmware from %s\" % url)\n    path = io.BytesIO(r.content)\n\n  zf = ZipFile(path)\n  zf.printdir()\n\n  version = zf.read(\"version\").decode()\n  status(\"0. Preparing to flash \" + str(version))\n\n  code_bootstub = zf.read(\"bootstub.panda.bin\")\n  code_panda = zf.read(\"panda.bin\")\n\n  # enter DFU mode\n  status(\"1. Entering DFU mode\")\n  panda = Panda(st_serial)\n  panda.reset(enter_bootstub=True)\n  panda.reset(enter_bootloader=True)\n  time.sleep(1)\n\n  # program bootstub\n  status(\"2. Programming bootstub\")\n  dfu = PandaDFU(PandaDFU.st_serial_to_dfu_serial(st_serial))\n  dfu.program_bootstub(code_bootstub)\n  time.sleep(1)\n\n  # flash main code\n  status(\"3. Flashing main code\")\n  panda = Panda(st_serial)\n  panda.flash(code=code_panda)\n  panda.close()\n\n  # check for connection\n  status(\"4. Verifying version\")\n  panda = Panda(st_serial)\n  my_version = panda.get_version()\n  print(\"dongle id: %s\" % panda.get_serial()[0])\n  print(my_version, \"should be\", version)\n  assert(str(version) == str(my_version))\n\n  # done!\n  status(\"6. Success!\")\n\nif __name__ == \"__main__\":\n  flash_release(*sys.argv[1:])\n"
  },
  {
    "path": "panda/python/isotp.py",
    "content": "import binascii\nimport time\n\nDEBUG = False\n\ndef msg(x):\n  if DEBUG:\n    print(\"S:\", binascii.hexlify(x))\n  if len(x) <= 7:\n    ret = bytes([len(x)]) + x\n  else:\n    assert False\n  return ret.ljust(8, b\"\\x00\")\n\nkmsgs = []\ndef recv(panda, cnt, addr, nbus):\n  global kmsgs\n  ret = []\n\n  while len(ret) < cnt:\n    kmsgs += panda.can_recv()\n    nmsgs = []\n    for ids, ts, dat, bus in kmsgs:\n      if ids == addr and bus == nbus and len(ret) < cnt:\n        ret.append(dat)\n      else:\n        # leave around\n        nmsgs.append((ids, ts, dat, bus))\n    kmsgs = nmsgs[-256:]\n  return ret\n\ndef isotp_recv_subaddr(panda, addr, bus, sendaddr, subaddr):\n  msg = recv(panda, 1, addr, bus)[0]\n\n  # TODO: handle other subaddr also communicating\n  assert msg[0] == subaddr\n\n  if msg[1] & 0xf0 == 0x10:\n    # first\n    tlen = ((msg[1] & 0xf) << 8) | msg[2]\n    dat = msg[3:]\n\n    # 0 block size?\n    CONTINUE = bytes([subaddr]) + b\"\\x30\" + b\"\\x00\" * 6\n    panda.can_send(sendaddr, CONTINUE, bus)\n\n    idx = 1\n    for mm in recv(panda, (tlen - len(dat) + 5) // 6, addr, bus):\n      assert mm[0] == subaddr\n      assert mm[1] == (0x20 | (idx & 0xF))\n      dat += mm[2:]\n      idx += 1\n  elif msg[1] & 0xf0 == 0x00:\n    # single\n    tlen = msg[1] & 0xf\n    dat = msg[2:]\n  else:\n    print(binascii.hexlify(msg))\n    assert False\n\n  return dat[0:tlen]\n\n# **** import below this line ****\n\ndef isotp_send(panda, x, addr, bus=0, recvaddr=None, subaddr=None, rate=None):\n  if recvaddr is None:\n    recvaddr = addr + 8\n\n  if len(x) <= 7 and subaddr is None:\n    panda.can_send(addr, msg(x), bus)\n  elif len(x) <= 6 and subaddr is not None:\n    panda.can_send(addr, bytes([subaddr]) + msg(x)[0:7], bus)\n  else:\n    if subaddr:\n      ss = bytes([subaddr, 0x10 + (len(x) >> 8), len(x) & 0xFF]) + x[0:5]\n      x = x[5:]\n    else:\n      ss = bytes([0x10 + (len(x) >> 8), len(x) & 0xFF]) + x[0:6]\n      x = x[6:]\n    idx = 1\n    sends = []\n    while len(x) > 0:\n      if subaddr:\n        sends.append(((bytes([subaddr, 0x20 + (idx & 0xF)]) + x[0:6]).ljust(8, b\"\\x00\")))\n        x = x[6:]\n      else:\n        sends.append(((bytes([0x20 + (idx & 0xF)]) + x[0:7]).ljust(8, b\"\\x00\")))\n        x = x[7:]\n      idx += 1\n\n    # actually send\n    panda.can_send(addr, ss, bus)\n    rr = recv(panda, 1, recvaddr, bus)[0]\n    if rr.find(b\"\\x30\\x01\") != -1:\n      for s in sends[:-1]:\n        panda.can_send(addr, s, 0)\n        rr = recv(panda, 1, recvaddr, bus)[0]\n      panda.can_send(addr, sends[-1], 0)\n    else:\n      if rate is None:\n        panda.can_send_many([(addr, None, s, bus) for s in sends])\n      else:\n        for dat in sends:\n          panda.can_send(addr, dat, bus)\n          time.sleep(rate)\n\ndef isotp_recv(panda, addr, bus=0, sendaddr=None, subaddr=None):\n  if sendaddr is None:\n    sendaddr = addr - 8\n\n  if subaddr is not None:\n    dat = isotp_recv_subaddr(panda, addr, bus, sendaddr, subaddr)\n  else:\n    msg = recv(panda, 1, addr, bus)[0]\n\n    if msg[0] & 0xf0 == 0x10:\n      # first\n      tlen = ((msg[0] & 0xf) << 8) | msg[1]\n      dat = msg[2:]\n\n      # 0 block size?\n      CONTINUE = b\"\\x30\" + b\"\\x00\" * 7\n\n      panda.can_send(sendaddr, CONTINUE, bus)\n\n      idx = 1\n      for mm in recv(panda, (tlen - len(dat) + 6) // 7, addr, bus):\n        assert mm[0] == (0x20 | (idx & 0xF))\n        dat += mm[1:]\n        idx += 1\n    elif msg[0] & 0xf0 == 0x00:\n      # single\n      tlen = msg[0] & 0xf\n      dat = msg[1:]\n    else:\n      assert False\n    dat = dat[0:tlen]\n\n  if DEBUG:\n    print(\"R:\", binascii.hexlify(dat))\n\n  return dat\n"
  },
  {
    "path": "panda/python/serial.py",
    "content": "# mimic a python serial port\nclass PandaSerial(object):\n  def __init__(self, panda, port, baud):\n    self.panda = panda\n    self.port = port\n    self.panda.set_uart_parity(self.port, 0)\n    self._baudrate = baud\n    self.panda.set_uart_baud(self.port, baud)\n    self.buf = b\"\"\n\n  def read(self, l=1):  # noqa: E741\n    tt = self.panda.serial_read(self.port)\n    if len(tt) > 0:\n      self.buf += tt\n    ret = self.buf[0:l]\n    self.buf = self.buf[l:]\n    return ret\n\n  def write(self, dat):\n    return self.panda.serial_write(self.port, dat)\n\n  def close(self):\n    pass\n\n  def flush(self):\n    pass\n\n  @property\n  def baudrate(self):\n    return self._baudrate\n\n  @baudrate.setter\n  def baudrate(self, value):\n    self.panda.set_uart_baud(self.port, value)\n    self._baudrate = value\n"
  },
  {
    "path": "panda/python/uds.py",
    "content": "#!/usr/bin/env python3\nimport time\nimport struct\nfrom collections import deque\nfrom typing import Callable, NamedTuple, Tuple, List, Deque, Generator, Optional, cast\nfrom enum import IntEnum\n\nclass SERVICE_TYPE(IntEnum):\n  DIAGNOSTIC_SESSION_CONTROL = 0x10\n  ECU_RESET = 0x11\n  SECURITY_ACCESS = 0x27\n  COMMUNICATION_CONTROL = 0x28\n  TESTER_PRESENT = 0x3E\n  ACCESS_TIMING_PARAMETER = 0x83\n  SECURED_DATA_TRANSMISSION = 0x84\n  CONTROL_DTC_SETTING = 0x85\n  RESPONSE_ON_EVENT = 0x86\n  LINK_CONTROL = 0x87\n  READ_DATA_BY_IDENTIFIER = 0x22\n  READ_MEMORY_BY_ADDRESS = 0x23\n  READ_SCALING_DATA_BY_IDENTIFIER = 0x24\n  READ_DATA_BY_PERIODIC_IDENTIFIER = 0x2A\n  DYNAMICALLY_DEFINE_DATA_IDENTIFIER = 0x2C\n  WRITE_DATA_BY_IDENTIFIER = 0x2E\n  WRITE_MEMORY_BY_ADDRESS = 0x3D\n  CLEAR_DIAGNOSTIC_INFORMATION = 0x14\n  READ_DTC_INFORMATION = 0x19\n  INPUT_OUTPUT_CONTROL_BY_IDENTIFIER = 0x2F\n  ROUTINE_CONTROL = 0x31\n  REQUEST_DOWNLOAD = 0x34\n  REQUEST_UPLOAD = 0x35\n  TRANSFER_DATA = 0x36\n  REQUEST_TRANSFER_EXIT = 0x37\n\nclass SESSION_TYPE(IntEnum):\n  DEFAULT = 1\n  PROGRAMMING = 2\n  EXTENDED_DIAGNOSTIC = 3\n  SAFETY_SYSTEM_DIAGNOSTIC = 4\n\nclass RESET_TYPE(IntEnum):\n  HARD = 1\n  KEY_OFF_ON = 2\n  SOFT = 3\n  ENABLE_RAPID_POWER_SHUTDOWN = 4\n  DISABLE_RAPID_POWER_SHUTDOWN = 5\n\nclass ACCESS_TYPE(IntEnum):\n  REQUEST_SEED = 1\n  SEND_KEY = 2\n\nclass CONTROL_TYPE(IntEnum):\n  ENABLE_RX_ENABLE_TX = 0\n  ENABLE_RX_DISABLE_TX = 1\n  DISABLE_RX_ENABLE_TX = 2\n  DISABLE_RX_DISABLE_TX = 3\n\nclass MESSAGE_TYPE(IntEnum):\n  NORMAL = 1\n  NETWORK_MANAGEMENT = 2\n  NORMAL_AND_NETWORK_MANAGEMENT = 3\n\nclass TIMING_PARAMETER_TYPE(IntEnum):\n  READ_EXTENDED_SET = 1\n  SET_TO_DEFAULT_VALUES = 2\n  READ_CURRENTLY_ACTIVE = 3\n  SET_TO_GIVEN_VALUES = 4\n\nclass DTC_SETTING_TYPE(IntEnum):\n  ON = 1\n  OFF = 2\n\nclass RESPONSE_EVENT_TYPE(IntEnum):\n  STOP_RESPONSE_ON_EVENT = 0\n  ON_DTC_STATUS_CHANGE = 1\n  ON_TIMER_INTERRUPT = 2\n  ON_CHANGE_OF_DATA_IDENTIFIER = 3\n  REPORT_ACTIVATED_EVENTS = 4\n  START_RESPONSE_ON_EVENT = 5\n  CLEAR_RESPONSE_ON_EVENT = 6\n  ON_COMPARISON_OF_VALUES = 7\n\nclass LINK_CONTROL_TYPE(IntEnum):\n  VERIFY_BAUDRATE_TRANSITION_WITH_FIXED_BAUDRATE = 1\n  VERIFY_BAUDRATE_TRANSITION_WITH_SPECIFIC_BAUDRATE = 2\n  TRANSITION_BAUDRATE = 3\n\nclass BAUD_RATE_TYPE(IntEnum):\n  PC9600 = 1\n  PC19200 = 2\n  PC38400 = 3\n  PC57600 = 4\n  PC115200 = 5\n  CAN125000 = 16\n  CAN250000 = 17\n  CAN500000 = 18\n  CAN1000000 = 19\n\nclass DATA_IDENTIFIER_TYPE(IntEnum):\n  BOOT_SOFTWARE_IDENTIFICATION = 0xF180\n  APPLICATION_SOFTWARE_IDENTIFICATION = 0xF181\n  APPLICATION_DATA_IDENTIFICATION = 0xF182\n  BOOT_SOFTWARE_FINGERPRINT = 0xF183\n  APPLICATION_SOFTWARE_FINGERPRINT = 0xF184\n  APPLICATION_DATA_FINGERPRINT = 0xF185\n  ACTIVE_DIAGNOSTIC_SESSION = 0xF186\n  VEHICLE_MANUFACTURER_SPARE_PART_NUMBER = 0xF187\n  VEHICLE_MANUFACTURER_ECU_SOFTWARE_NUMBER = 0xF188\n  VEHICLE_MANUFACTURER_ECU_SOFTWARE_VERSION_NUMBER = 0xF189\n  SYSTEM_SUPPLIER_IDENTIFIER = 0xF18A\n  ECU_MANUFACTURING_DATE = 0xF18B\n  ECU_SERIAL_NUMBER = 0xF18C\n  SUPPORTED_FUNCTIONAL_UNITS = 0xF18D\n  VEHICLE_MANUFACTURER_KIT_ASSEMBLY_PART_NUMBER = 0xF18E\n  VIN = 0xF190\n  VEHICLE_MANUFACTURER_ECU_HARDWARE_NUMBER = 0xF191\n  SYSTEM_SUPPLIER_ECU_HARDWARE_NUMBER = 0xF192\n  SYSTEM_SUPPLIER_ECU_HARDWARE_VERSION_NUMBER = 0xF193\n  SYSTEM_SUPPLIER_ECU_SOFTWARE_NUMBER = 0xF194\n  SYSTEM_SUPPLIER_ECU_SOFTWARE_VERSION_NUMBER = 0xF195\n  EXHAUST_REGULATION_OR_TYPE_APPROVAL_NUMBER = 0xF196\n  SYSTEM_NAME_OR_ENGINE_TYPE = 0xF197\n  REPAIR_SHOP_CODE_OR_TESTER_SERIAL_NUMBER = 0xF198\n  PROGRAMMING_DATE = 0xF199\n  CALIBRATION_REPAIR_SHOP_CODE_OR_CALIBRATION_EQUIPMENT_SERIAL_NUMBER = 0xF19A\n  CALIBRATION_DATE = 0xF19B\n  CALIBRATION_EQUIPMENT_SOFTWARE_NUMBER = 0xF19C\n  ECU_INSTALLATION_DATE = 0xF19D\n  ODX_FILE = 0xF19E\n  ENTITY = 0xF19F\n\nclass TRANSMISSION_MODE_TYPE(IntEnum):\n  SEND_AT_SLOW_RATE = 1\n  SEND_AT_MEDIUM_RATE = 2\n  SEND_AT_FAST_RATE = 3\n  STOP_SENDING = 4\n\nclass DYNAMIC_DEFINITION_TYPE(IntEnum):\n  DEFINE_BY_IDENTIFIER = 1\n  DEFINE_BY_MEMORY_ADDRESS = 2\n  CLEAR_DYNAMICALLY_DEFINED_DATA_IDENTIFIER = 3\n\nclass DynamicSourceDefinition(NamedTuple):\n  data_identifier: int\n  position: int\n  memory_size: int\n  memory_address: int\n\nclass DTC_GROUP_TYPE(IntEnum):\n  EMISSIONS = 0x000000\n  ALL = 0xFFFFFF\n\nclass DTC_REPORT_TYPE(IntEnum):\n  NUMBER_OF_DTC_BY_STATUS_MASK = 0x01\n  DTC_BY_STATUS_MASK = 0x02\n  DTC_SNAPSHOT_IDENTIFICATION = 0x03\n  DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER = 0x04\n  DTC_SNAPSHOT_RECORD_BY_RECORD_NUMBER = 0x05\n  DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER = 0x06\n  NUMBER_OF_DTC_BY_SEVERITY_MASK_RECORD = 0x07\n  DTC_BY_SEVERITY_MASK_RECORD = 0x08\n  SEVERITY_INFORMATION_OF_DTC = 0x09\n  SUPPORTED_DTC = 0x0A\n  FIRST_TEST_FAILED_DTC = 0x0B\n  FIRST_CONFIRMED_DTC = 0x0C\n  MOST_RECENT_TEST_FAILED_DTC = 0x0D\n  MOST_RECENT_CONFIRMED_DTC = 0x0E\n  MIRROR_MEMORY_DTC_BY_STATUS_MASK = 0x0F\n  MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER = 0x10\n  NUMBER_OF_MIRROR_MEMORY_DTC_BY_STATUS_MASK = 0x11\n  NUMBER_OF_EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK = 0x12\n  EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK = 0x13\n  DTC_FAULT_DETECTION_COUNTER = 0x14\n  DTC_WITH_PERMANENT_STATUS = 0x15\n\nclass DTC_STATUS_MASK_TYPE(IntEnum):\n  TEST_FAILED = 0x01\n  TEST_FAILED_THIS_OPERATION_CYCLE = 0x02\n  PENDING_DTC = 0x04\n  CONFIRMED_DTC = 0x08\n  TEST_NOT_COMPLETED_SINCE_LAST_CLEAR = 0x10\n  TEST_FAILED_SINCE_LAST_CLEAR = 0x20\n  TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE = 0x40\n  WARNING_INDICATOR_REQUESTED = 0x80\n  ALL = 0xFF\n\nclass DTC_SEVERITY_MASK_TYPE(IntEnum):\n  MAINTENANCE_ONLY = 0x20\n  CHECK_AT_NEXT_HALT = 0x40\n  CHECK_IMMEDIATELY = 0x80\n  ALL = 0xE0\n\nclass CONTROL_PARAMETER_TYPE(IntEnum):\n  RETURN_CONTROL_TO_ECU = 0\n  RESET_TO_DEFAULT = 1\n  FREEZE_CURRENT_STATE = 2\n  SHORT_TERM_ADJUSTMENT = 3\n\nclass ROUTINE_CONTROL_TYPE(IntEnum):\n  START = 1\n  STOP = 2\n  REQUEST_RESULTS = 3\n\nclass ROUTINE_IDENTIFIER_TYPE(IntEnum):\n  ERASE_MEMORY = 0xFF00\n  CHECK_PROGRAMMING_DEPENDENCIES = 0xFF01\n  ERASE_MIRROR_MEMORY_DTCS = 0xFF02\n\nclass MessageTimeoutError(Exception):\n  pass\n\nclass NegativeResponseError(Exception):\n  def __init__(self, message, service_id, error_code):\n    super().__init__()\n    self.message = message\n    self.service_id = service_id\n    self.error_code = error_code\n\n  def __str__(self):\n    return self.message\n\nclass InvalidServiceIdError(Exception):\n  pass\n\nclass InvalidSubFunctioneError(Exception):\n  pass\n\n_negative_response_codes = {\n    0x00: 'positive response',\n    0x10: 'general reject',\n    0x11: 'service not supported',\n    0x12: 'sub-function not supported',\n    0x13: 'incorrect message length or invalid format',\n    0x14: 'response too long',\n    0x21: 'busy repeat request',\n    0x22: 'conditions not correct',\n    0x24: 'request sequence error',\n    0x25: 'no response from subnet component',\n    0x26: 'failure prevents execution of requested action',\n    0x31: 'request out of range',\n    0x33: 'security access denied',\n    0x35: 'invalid key',\n    0x36: 'exceed number of attempts',\n    0x37: 'required time delay not expired',\n    0x70: 'upload download not accepted',\n    0x71: 'transfer data suspended',\n    0x72: 'general programming failure',\n    0x73: 'wrong block sequence counter',\n    0x78: 'request correctly received - response pending',\n    0x7e: 'sub-function not supported in active session',\n    0x7f: 'service not supported in active session',\n    0x81: 'rpm too high',\n    0x82: 'rpm too low',\n    0x83: 'engine is running',\n    0x84: 'engine is not running',\n    0x85: 'engine run time too low',\n    0x86: 'temperature too high',\n    0x87: 'temperature too low',\n    0x88: 'vehicle speed too high',\n    0x89: 'vehicle speed too low',\n    0x8a: 'throttle/pedal too high',\n    0x8b: 'throttle/pedal too low',\n    0x8c: 'transmission not in neutral',\n    0x8d: 'transmission not in gear',\n    0x8f: 'brake switch(es) not closed',\n    0x90: 'shifter lever not in park',\n    0x91: 'torque converter clutch locked',\n    0x92: 'voltage too high',\n    0x93: 'voltage too low',\n}\n\n\nclass CanClient():\n  def __init__(self, can_send: Callable[[int, bytes, int], None], can_recv: Callable[[], List[Tuple[int, int, bytes, int]]],\n               tx_addr: int, rx_addr: int, bus: int, sub_addr: int = None, debug: bool = False):\n    self.tx = can_send\n    self.rx = can_recv\n    self.tx_addr = tx_addr\n    self.rx_addr = rx_addr\n    self.rx_buff = deque()  # type: Deque[bytes]\n    self.sub_addr = sub_addr\n    self.bus = bus\n    self.debug = debug\n\n  def _recv_filter(self, bus: int, addr: int) -> bool:\n    # handle functional addresses (switch to first addr to respond)\n    if self.tx_addr == 0x7DF:\n      is_response = addr >= 0x7E8 and addr <= 0x7EF\n      if is_response:\n        if self.debug:\n          print(f\"switch to physical addr {hex(addr)}\")\n        self.tx_addr = addr - 8\n        self.rx_addr = addr\n      return is_response\n    if self.tx_addr == 0x18DB33F1:\n      is_response = addr >= 0x18DAF100 and addr <= 0x18DAF1FF\n      if is_response:\n        if self.debug:\n          print(f\"switch to physical addr {hex(addr)}\")\n        self.tx_addr = 0x18DA00F1 + (addr << 8 & 0xFF00)\n        self.rx_addr = addr\n    return bus == self.bus and addr == self.rx_addr\n\n  def _recv_buffer(self, drain: bool = False) -> None:\n    while True:\n      msgs = self.rx()\n      if drain:\n        if self.debug:\n          print(\"CAN-RX: drain - {}\".format(len(msgs)))\n        self.rx_buff.clear()\n      else:\n        for rx_addr, _, rx_data, rx_bus in msgs or []:\n          if self._recv_filter(rx_bus, rx_addr) and len(rx_data) > 0:\n            rx_data = bytes(rx_data)  # convert bytearray to bytes\n\n            if self.debug:\n              print(f\"CAN-RX: {hex(rx_addr)} - 0x{bytes.hex(rx_data)}\")\n\n            # Cut off sub addr in first byte\n            if self.sub_addr is not None:\n              rx_data = rx_data[1:]\n\n            self.rx_buff.append(rx_data)\n      # break when non-full buffer is processed\n      if len(msgs) < 254:\n        return\n\n  def recv(self, drain: bool = False) -> Generator[bytes, None, None]:\n    # buffer rx messages in case two response messages are received at once\n    # (e.g. response pending and success/failure response)\n    self._recv_buffer(drain)\n    try:\n      while True:\n        yield self.rx_buff.popleft()\n    except IndexError:\n      pass  # empty\n\n  def send(self, msgs: List[bytes], delay: float = 0) -> None:\n    for i, msg in enumerate(msgs):\n      if delay and i != 0:\n        if self.debug:\n          print(f\"CAN-TX: delay - {delay}\")\n        time.sleep(delay)\n\n      if self.sub_addr is not None:\n        msg = bytes([self.sub_addr]) + msg\n\n      if self.debug:\n        print(f\"CAN-TX: {hex(self.tx_addr)} - 0x{bytes.hex(msg)}\")\n      assert len(msg) <= 8\n\n      self.tx(self.tx_addr, msg, self.bus)\n      # prevent rx buffer from overflowing on large tx\n      if i % 10 == 9:\n        self._recv_buffer()\n\nclass IsoTpMessage():\n  def __init__(self, can_client: CanClient, timeout: float = 1, debug: bool = False, max_len: int = 8):\n    self._can_client = can_client\n    self.timeout = timeout\n    self.debug = debug\n    self.max_len = max_len\n\n  def send(self, dat: bytes) -> None:\n    # throw away any stale data\n    self._can_client.recv(drain=True)\n\n    self.tx_dat = dat\n    self.tx_len = len(dat)\n    self.tx_idx = 0\n    self.tx_done = False\n\n    self.rx_dat = b\"\"\n    self.rx_len = 0\n    self.rx_idx = 0\n    self.rx_done = False\n\n    if self.debug:\n      print(f\"ISO-TP: REQUEST - 0x{bytes.hex(self.tx_dat)}\")\n    self._tx_first_frame()\n\n  def _tx_first_frame(self) -> None:\n    if self.tx_len < self.max_len:\n      # single frame (send all bytes)\n      if self.debug:\n        print(\"ISO-TP: TX - single frame\")\n      msg = (bytes([self.tx_len]) + self.tx_dat).ljust(self.max_len, b\"\\x00\")\n      self.tx_done = True\n    else:\n      # first frame (send first 6 bytes)\n      if self.debug:\n        print(\"ISO-TP: TX - first frame\")\n      msg = (struct.pack(\"!H\", 0x1000 | self.tx_len) + self.tx_dat[:self.max_len - 2]).ljust(self.max_len - 2, b\"\\x00\")\n    self._can_client.send([msg])\n\n  def recv(self) -> Optional[bytes]:\n    start_time = time.time()\n    try:\n      while True:\n        for msg in self._can_client.recv():\n          self._isotp_rx_next(msg)\n          if self.tx_done and self.rx_done:\n            return self.rx_dat\n        # no timeout indicates non-blocking\n        if self.timeout == 0:\n          return None\n        if time.time() - start_time > self.timeout:\n          raise MessageTimeoutError(\"timeout waiting for response\")\n    finally:\n      if self.debug and self.rx_dat:\n        print(f\"ISO-TP: RESPONSE - 0x{bytes.hex(self.rx_dat)}\")\n\n  def _isotp_rx_next(self, rx_data: bytes) -> None:\n    # single rx_frame\n    if rx_data[0] >> 4 == 0x0:\n      self.rx_len = rx_data[0] & 0xFF\n      self.rx_dat = rx_data[1:1 + self.rx_len]\n      self.rx_idx = 0\n      self.rx_done = True\n      if self.debug:\n        print(f\"ISO-TP: RX - single frame - idx={self.rx_idx} done={self.rx_done}\")\n      return\n\n    # first rx_frame\n    if rx_data[0] >> 4 == 0x1:\n      self.rx_len = ((rx_data[0] & 0x0F) << 8) + rx_data[1]\n      self.rx_dat = rx_data[2:]\n      self.rx_idx = 0\n      self.rx_done = False\n      if self.debug:\n        print(f\"ISO-TP: RX - first frame - idx={self.rx_idx} done={self.rx_done}\")\n      if self.debug:\n        print(\"ISO-TP: TX - flow control continue\")\n      # send flow control message (send all bytes)\n      msg = b\"\\x30\\x00\\x00\".ljust(self.max_len, b\"\\x00\")\n      self._can_client.send([msg])\n      return\n\n    # consecutive rx frame\n    if rx_data[0] >> 4 == 0x2:\n      assert not self.rx_done, \"isotp - rx: consecutive frame with no active frame\"\n      self.rx_idx += 1\n      assert self.rx_idx & 0xF == rx_data[0] & 0xF, \"isotp - rx: invalid consecutive frame index\"\n      rx_size = self.rx_len - len(self.rx_dat)\n      self.rx_dat += rx_data[1:1 + rx_size]\n      if self.rx_len == len(self.rx_dat):\n        self.rx_done = True\n      if self.debug:\n        print(f\"ISO-TP: RX - consecutive frame - idx={self.rx_idx} done={self.rx_done}\")\n      return\n\n    # flow control\n    if rx_data[0] >> 4 == 0x3:\n      assert not self.tx_done, \"isotp - rx: flow control with no active frame\"\n      assert rx_data[0] != 0x32, \"isotp - rx: flow-control overflow/abort\"\n      assert rx_data[0] == 0x30 or rx_data[0] == 0x31, \"isotp - rx: flow-control transfer state indicator invalid\"\n      if rx_data[0] == 0x30:\n        if self.debug:\n          print(\"ISO-TP: RX - flow control continue\")\n        delay_ts = rx_data[2] & 0x7F\n        # scale is 1 milliseconds if first bit == 0, 100 micro seconds if first bit == 1\n        delay_div = 1000. if rx_data[2] & 0x80 == 0 else 10000.\n        delay_sec = delay_ts / delay_div\n\n        # first frame = 6 bytes, each consecutive frame = 7 bytes\n        num_bytes = self.max_len - 1\n        start = 6 + self.tx_idx * num_bytes\n        count = rx_data[1]\n        end = start + count * num_bytes if count > 0 else self.tx_len\n        tx_msgs = []\n        for i in range(start, end, num_bytes):\n          self.tx_idx += 1\n          # consecutive tx messages\n          msg = (bytes([0x20 | (self.tx_idx & 0xF)]) + self.tx_dat[i:i + num_bytes]).ljust(self.max_len, b\"\\x00\")\n          tx_msgs.append(msg)\n        # send consecutive tx messages\n        self._can_client.send(tx_msgs, delay=delay_sec)\n        if end >= self.tx_len:\n          self.tx_done = True\n        if self.debug:\n          print(f\"ISO-TP: TX - consecutive frame - idx={self.tx_idx} done={self.tx_done}\")\n      elif rx_data[0] == 0x31:\n        # wait (do nothing until next flow control message)\n        if self.debug:\n          print(\"ISO-TP: TX - flow control wait\")\n\nFUNCTIONAL_ADDRS = [0x7DF, 0x18DB33F1]\n\ndef get_rx_addr_for_tx_addr(tx_addr, rx_offset=0x8):\n  if tx_addr in FUNCTIONAL_ADDRS:\n    return None\n\n  if tx_addr < 0xFFF8:\n    # pseudo-standard 11 bit response addr (add 8) works for most manufacturers\n    # allow override; some manufacturers use other offsets for non-OBD2 access\n    return tx_addr + rx_offset\n\n  if tx_addr > 0x10000000 and tx_addr < 0xFFFFFFFF:\n    # standard 29 bit response addr (flip last two bytes)\n    return (tx_addr & 0xFFFF0000) + (tx_addr << 8 & 0xFF00) + (tx_addr >> 8 & 0xFF)\n\n  raise ValueError(\"invalid tx_addr: {}\".format(tx_addr))\n\n\nclass UdsClient():\n  def __init__(self, panda, tx_addr: int, rx_addr: int = None, bus: int = 0, timeout: float = 1, debug: bool = False):\n    self.bus = bus\n    self.tx_addr = tx_addr\n    self.rx_addr = rx_addr if rx_addr is not None else get_rx_addr_for_tx_addr(tx_addr)\n    self.timeout = timeout\n    self.debug = debug\n    self._can_client = CanClient(panda.can_send, panda.can_recv, self.tx_addr, self.rx_addr, self.bus, debug=self.debug)\n\n  # generic uds request\n  def _uds_request(self, service_type: SERVICE_TYPE, subfunction: int = None, data: bytes = None) -> bytes:\n    req = bytes([service_type])\n    if subfunction is not None:\n      req += bytes([subfunction])\n    if data is not None:\n      req += data\n\n    # send request, wait for response\n    isotp_msg = IsoTpMessage(self._can_client, self.timeout, self.debug)\n    isotp_msg.send(req)\n    while True:\n      resp = isotp_msg.recv()\n\n      if resp is None:\n        continue\n\n      resp_sid = resp[0] if len(resp) > 0 else None\n\n      # negative response\n      if resp_sid == 0x7F:\n        service_id = resp[1] if len(resp) > 1 else -1\n        try:\n          service_desc = SERVICE_TYPE(service_id).name\n        except BaseException:\n          service_desc = 'NON_STANDARD_SERVICE'\n        error_code = resp[2] if len(resp) > 2 else -1\n        try:\n          error_desc = _negative_response_codes[error_code]\n        except BaseException:\n          error_desc = resp[3:].hex()\n        # wait for another message if response pending\n        if error_code == 0x78:\n          if self.debug:\n            print(\"UDS-RX: response pending\")\n          continue\n        raise NegativeResponseError('{} - {}'.format(service_desc, error_desc), service_id, error_code)\n\n      # positive response\n      if service_type + 0x40 != resp_sid:\n        resp_sid_hex = hex(resp_sid) if resp_sid is not None else None\n        raise InvalidServiceIdError('invalid response service id: {}'.format(resp_sid_hex))\n\n      if subfunction is not None:\n        resp_sfn = resp[1] if len(resp) > 1 else None\n        if subfunction != resp_sfn:\n          resp_sfn_hex = hex(resp_sfn) if resp_sfn is not None else None\n          raise InvalidSubFunctioneError(f'invalid response subfunction: {resp_sfn_hex:x}')\n\n      # return data (exclude service id and sub-function id)\n      return resp[(1 if subfunction is None else 2):]\n\n  # services\n  def diagnostic_session_control(self, session_type: SESSION_TYPE):\n    self._uds_request(SERVICE_TYPE.DIAGNOSTIC_SESSION_CONTROL, subfunction=session_type)\n\n  def ecu_reset(self, reset_type: RESET_TYPE):\n    resp = self._uds_request(SERVICE_TYPE.ECU_RESET, subfunction=reset_type)\n    power_down_time = None\n    if reset_type == RESET_TYPE.ENABLE_RAPID_POWER_SHUTDOWN:\n      power_down_time = resp[0]\n      return power_down_time\n\n  def security_access(self, access_type: ACCESS_TYPE, security_key: bytes = None):\n    request_seed = access_type % 2 != 0\n    if request_seed and security_key is not None:\n      raise ValueError('security_key not allowed')\n    if not request_seed and security_key is None:\n      raise ValueError('security_key is missing')\n    resp = self._uds_request(SERVICE_TYPE.SECURITY_ACCESS, subfunction=access_type, data=security_key)\n    if request_seed:\n      security_seed = resp\n      return security_seed\n\n  def communication_control(self, control_type: CONTROL_TYPE, message_type: MESSAGE_TYPE):\n    data = bytes([message_type])\n    self._uds_request(SERVICE_TYPE.COMMUNICATION_CONTROL, subfunction=control_type, data=data)\n\n  def tester_present(self, ):\n    self._uds_request(SERVICE_TYPE.TESTER_PRESENT, subfunction=0x00)\n\n  def access_timing_parameter(self, timing_parameter_type: TIMING_PARAMETER_TYPE, parameter_values: bytes = None):\n    write_custom_values = timing_parameter_type == TIMING_PARAMETER_TYPE.SET_TO_GIVEN_VALUES\n    read_values = (timing_parameter_type == TIMING_PARAMETER_TYPE.READ_CURRENTLY_ACTIVE or\n                   timing_parameter_type == TIMING_PARAMETER_TYPE.READ_EXTENDED_SET)\n    if not write_custom_values and parameter_values is not None:\n      raise ValueError('parameter_values not allowed')\n    if write_custom_values and parameter_values is None:\n      raise ValueError('parameter_values is missing')\n    resp = self._uds_request(SERVICE_TYPE.ACCESS_TIMING_PARAMETER, subfunction=timing_parameter_type, data=parameter_values)\n    if read_values:\n      # TODO: parse response into values?\n      parameter_values = resp\n      return parameter_values\n\n  def secured_data_transmission(self, data: bytes):\n    # TODO: split data into multiple input parameters?\n    resp = self._uds_request(SERVICE_TYPE.SECURED_DATA_TRANSMISSION, subfunction=None, data=data)\n    # TODO: parse response into multiple output values?\n    return resp\n\n  def control_dtc_setting(self, dtc_setting_type: DTC_SETTING_TYPE):\n    self._uds_request(SERVICE_TYPE.CONTROL_DTC_SETTING, subfunction=dtc_setting_type)\n\n  def response_on_event(self, response_event_type: RESPONSE_EVENT_TYPE, store_event: bool, window_time: int,\n                        event_type_record: int, service_response_record: int):\n    if store_event:\n      response_event_type |= 0x20  # type: ignore\n    # TODO: split record parameters into arrays\n    data = bytes([window_time, event_type_record, service_response_record])\n    resp = self._uds_request(SERVICE_TYPE.RESPONSE_ON_EVENT, subfunction=response_event_type, data=data)\n\n    if response_event_type == RESPONSE_EVENT_TYPE.REPORT_ACTIVATED_EVENTS:\n      return {\n        \"num_of_activated_events\": resp[0],\n        \"data\": resp[1:],  # TODO: parse the reset of response\n      }\n\n    return {\n      \"num_of_identified_events\": resp[0],\n      \"event_window_time\": resp[1],\n      \"data\": resp[2:],  # TODO: parse the reset of response\n    }\n\n  def link_control(self, link_control_type: LINK_CONTROL_TYPE, baud_rate_type: BAUD_RATE_TYPE = None):\n    data: Optional[bytes]\n\n    if link_control_type == LINK_CONTROL_TYPE.VERIFY_BAUDRATE_TRANSITION_WITH_FIXED_BAUDRATE:\n      # baud_rate_type = BAUD_RATE_TYPE\n      data = bytes([cast(int, baud_rate_type)])\n    elif link_control_type == LINK_CONTROL_TYPE.VERIFY_BAUDRATE_TRANSITION_WITH_SPECIFIC_BAUDRATE:\n      # baud_rate_type = custom value (3 bytes big-endian)\n      data = struct.pack('!I', baud_rate_type)[1:]\n    else:\n      data = None\n    self._uds_request(SERVICE_TYPE.LINK_CONTROL, subfunction=link_control_type, data=data)\n\n  def read_data_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE):\n    # TODO: support list of identifiers\n    data = struct.pack('!H', data_identifier_type)\n    resp = self._uds_request(SERVICE_TYPE.READ_DATA_BY_IDENTIFIER, subfunction=None, data=data)\n    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None\n    if resp_id != data_identifier_type:\n      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))\n    return resp[2:]\n\n  def read_memory_by_address(self, memory_address: int, memory_size: int, memory_address_bytes: int = 4, memory_size_bytes: int = 1):\n    if memory_address_bytes < 1 or memory_address_bytes > 4:\n      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))\n    if memory_size_bytes < 1 or memory_size_bytes > 4:\n      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))\n    data = bytes([memory_size_bytes << 4 | memory_address_bytes])\n\n    if memory_address >= 1 << (memory_address_bytes * 8):\n      raise ValueError('invalid memory_address: {}'.format(memory_address))\n    data += struct.pack('!I', memory_address)[4 - memory_address_bytes:]\n    if memory_size >= 1 << (memory_size_bytes * 8):\n      raise ValueError('invalid memory_size: {}'.format(memory_size))\n    data += struct.pack('!I', memory_size)[4 - memory_size_bytes:]\n\n    resp = self._uds_request(SERVICE_TYPE.READ_MEMORY_BY_ADDRESS, subfunction=None, data=data)\n    return resp\n\n  def read_scaling_data_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE):\n    data = struct.pack('!H', data_identifier_type)\n    resp = self._uds_request(SERVICE_TYPE.READ_SCALING_DATA_BY_IDENTIFIER, subfunction=None, data=data)\n    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None\n    if resp_id != data_identifier_type:\n      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))\n    return resp[2:]  # TODO: parse the response\n\n  def read_data_by_periodic_identifier(self, transmission_mode_type: TRANSMISSION_MODE_TYPE, periodic_data_identifier: int):\n    # TODO: support list of identifiers\n    data = bytes([transmission_mode_type, periodic_data_identifier])\n    self._uds_request(SERVICE_TYPE.READ_DATA_BY_PERIODIC_IDENTIFIER, subfunction=None, data=data)\n\n  def dynamically_define_data_identifier(self, dynamic_definition_type: DYNAMIC_DEFINITION_TYPE, dynamic_data_identifier: int,\n                                         source_definitions: List[DynamicSourceDefinition], memory_address_bytes: int = 4, memory_size_bytes: int = 1):\n    if memory_address_bytes < 1 or memory_address_bytes > 4:\n      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))\n    if memory_size_bytes < 1 or memory_size_bytes > 4:\n      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))\n\n    data = struct.pack('!H', dynamic_data_identifier)\n    if dynamic_definition_type == DYNAMIC_DEFINITION_TYPE.DEFINE_BY_IDENTIFIER:\n      for s in source_definitions:\n        data += struct.pack('!H', s.data_identifier) + bytes([s.position, s.memory_size])\n    elif dynamic_definition_type == DYNAMIC_DEFINITION_TYPE.DEFINE_BY_MEMORY_ADDRESS:\n      data += bytes([memory_size_bytes << 4 | memory_address_bytes])\n      for s in source_definitions:\n        if s.memory_address >= 1 << (memory_address_bytes * 8):\n          raise ValueError('invalid memory_address: {}'.format(s.memory_address))\n        data += struct.pack('!I', s.memory_address)[4 - memory_address_bytes:]\n        if s.memory_size >= 1 << (memory_size_bytes * 8):\n          raise ValueError('invalid memory_size: {}'.format(s.memory_size))\n        data += struct.pack('!I', s.memory_size)[4 - memory_size_bytes:]\n    elif dynamic_definition_type == DYNAMIC_DEFINITION_TYPE.CLEAR_DYNAMICALLY_DEFINED_DATA_IDENTIFIER:\n      pass\n    else:\n      raise ValueError('invalid dynamic identifier type: {}'.format(hex(dynamic_definition_type)))\n    self._uds_request(SERVICE_TYPE.DYNAMICALLY_DEFINE_DATA_IDENTIFIER, subfunction=dynamic_definition_type, data=data)\n\n  def write_data_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE, data_record: bytes):\n    data = struct.pack('!H', data_identifier_type) + data_record\n    resp = self._uds_request(SERVICE_TYPE.WRITE_DATA_BY_IDENTIFIER, subfunction=None, data=data)\n    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None\n    if resp_id != data_identifier_type:\n      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))\n\n  def write_memory_by_address(self, memory_address: int, memory_size: int, data_record: bytes, memory_address_bytes: int = 4, memory_size_bytes: int = 1):\n    if memory_address_bytes < 1 or memory_address_bytes > 4:\n      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))\n    if memory_size_bytes < 1 or memory_size_bytes > 4:\n      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))\n    data = bytes([memory_size_bytes << 4 | memory_address_bytes])\n\n    if memory_address >= 1 << (memory_address_bytes * 8):\n      raise ValueError('invalid memory_address: {}'.format(memory_address))\n    data += struct.pack('!I', memory_address)[4 - memory_address_bytes:]\n    if memory_size >= 1 << (memory_size_bytes * 8):\n      raise ValueError('invalid memory_size: {}'.format(memory_size))\n    data += struct.pack('!I', memory_size)[4 - memory_size_bytes:]\n\n    data += data_record\n    self._uds_request(SERVICE_TYPE.WRITE_MEMORY_BY_ADDRESS, subfunction=0x00, data=data)\n\n  def clear_diagnostic_information(self, dtc_group_type: DTC_GROUP_TYPE):\n    data = struct.pack('!I', dtc_group_type)[1:]  # 3 bytes\n    self._uds_request(SERVICE_TYPE.CLEAR_DIAGNOSTIC_INFORMATION, subfunction=None, data=data)\n\n  def read_dtc_information(self, dtc_report_type: DTC_REPORT_TYPE, dtc_status_mask_type: DTC_STATUS_MASK_TYPE = DTC_STATUS_MASK_TYPE.ALL,\n                           dtc_severity_mask_type: DTC_SEVERITY_MASK_TYPE = DTC_SEVERITY_MASK_TYPE.ALL, dtc_mask_record: int = 0xFFFFFF,\n                           dtc_snapshot_record_num: int = 0xFF, dtc_extended_record_num: int = 0xFF):\n    data = b''\n    # dtc_status_mask_type\n    if dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_DTC_BY_STATUS_MASK or \\\n       dtc_report_type == DTC_REPORT_TYPE.DTC_BY_STATUS_MASK or \\\n       dtc_report_type == DTC_REPORT_TYPE.MIRROR_MEMORY_DTC_BY_STATUS_MASK or \\\n       dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_MIRROR_MEMORY_DTC_BY_STATUS_MASK or \\\n       dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK or \\\n       dtc_report_type == DTC_REPORT_TYPE.EMISSIONS_RELATED_OBD_DTC_BY_STATUS_MASK:\n       data += bytes([dtc_status_mask_type])\n    # dtc_mask_record\n    if dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_IDENTIFICATION or \\\n       dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER or \\\n       dtc_report_type == DTC_REPORT_TYPE.DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER or \\\n       dtc_report_type == DTC_REPORT_TYPE.MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER or \\\n       dtc_report_type == DTC_REPORT_TYPE.SEVERITY_INFORMATION_OF_DTC:\n       data += struct.pack('!I', dtc_mask_record)[1:]  # 3 bytes\n    # dtc_snapshot_record_num\n    if dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_IDENTIFICATION or \\\n       dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_RECORD_BY_DTC_NUMBER or \\\n       dtc_report_type == DTC_REPORT_TYPE.DTC_SNAPSHOT_RECORD_BY_RECORD_NUMBER:\n       data += bytes([dtc_snapshot_record_num])\n    # dtc_extended_record_num\n    if dtc_report_type == DTC_REPORT_TYPE.DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER or \\\n       dtc_report_type == DTC_REPORT_TYPE.MIRROR_MEMORY_DTC_EXTENDED_DATA_RECORD_BY_DTC_NUMBER:\n       data += bytes([dtc_extended_record_num])\n    # dtc_severity_mask_type\n    if dtc_report_type == DTC_REPORT_TYPE.NUMBER_OF_DTC_BY_SEVERITY_MASK_RECORD or \\\n       dtc_report_type == DTC_REPORT_TYPE.DTC_BY_SEVERITY_MASK_RECORD:\n       data += bytes([dtc_severity_mask_type, dtc_status_mask_type])\n\n    resp = self._uds_request(SERVICE_TYPE.READ_DTC_INFORMATION, subfunction=dtc_report_type, data=data)\n\n    # TODO: parse response\n    return resp\n\n  def input_output_control_by_identifier(self, data_identifier_type: DATA_IDENTIFIER_TYPE, control_parameter_type: CONTROL_PARAMETER_TYPE,\n                                         control_option_record: bytes, control_enable_mask_record: bytes = b''):\n    data = struct.pack('!H', data_identifier_type) + bytes([control_parameter_type]) + control_option_record + control_enable_mask_record\n    resp = self._uds_request(SERVICE_TYPE.INPUT_OUTPUT_CONTROL_BY_IDENTIFIER, subfunction=None, data=data)\n    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None\n    if resp_id != data_identifier_type:\n      raise ValueError('invalid response data identifier: {}'.format(hex(resp_id)))\n    return resp[2:]\n\n  def routine_control(self, routine_control_type: ROUTINE_CONTROL_TYPE, routine_identifier_type: ROUTINE_IDENTIFIER_TYPE, routine_option_record: bytes = b''):\n    data = struct.pack('!H', routine_identifier_type) + routine_option_record\n    resp = self._uds_request(SERVICE_TYPE.ROUTINE_CONTROL, subfunction=routine_control_type, data=data)\n    resp_id = struct.unpack('!H', resp[0:2])[0] if len(resp) >= 2 else None\n    if resp_id != routine_identifier_type:\n      raise ValueError('invalid response routine identifier: {}'.format(hex(resp_id)))\n    return resp[2:]\n\n  def request_download(self, memory_address: int, memory_size: int, memory_address_bytes: int = 4, memory_size_bytes: int = 4, data_format: int = 0x00):\n    data = bytes([data_format])\n\n    if memory_address_bytes < 1 or memory_address_bytes > 4:\n      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))\n    if memory_size_bytes < 1 or memory_size_bytes > 4:\n      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))\n    data += bytes([memory_size_bytes << 4 | memory_address_bytes])\n\n    if memory_address >= 1 << (memory_address_bytes * 8):\n      raise ValueError('invalid memory_address: {}'.format(memory_address))\n    data += struct.pack('!I', memory_address)[4 - memory_address_bytes:]\n    if memory_size >= 1 << (memory_size_bytes * 8):\n      raise ValueError('invalid memory_size: {}'.format(memory_size))\n    data += struct.pack('!I', memory_size)[4 - memory_size_bytes:]\n\n    resp = self._uds_request(SERVICE_TYPE.REQUEST_DOWNLOAD, subfunction=None, data=data)\n    max_num_bytes_len = resp[0] >> 4 if len(resp) > 0 else 0\n    if max_num_bytes_len >= 1 and max_num_bytes_len <= 4:\n      max_num_bytes = struct.unpack('!I', (b\"\\x00\" * (4 - max_num_bytes_len)) + resp[1:max_num_bytes_len + 1])[0]\n    else:\n      raise ValueError('invalid max_num_bytes_len: {}'.format(max_num_bytes_len))\n\n    return max_num_bytes  # max number of bytes per transfer data request\n\n  def request_upload(self, memory_address: int, memory_size: int, memory_address_bytes: int = 4, memory_size_bytes: int = 4, data_format: int = 0x00):\n    data = bytes([data_format])\n\n    if memory_address_bytes < 1 or memory_address_bytes > 4:\n      raise ValueError('invalid memory_address_bytes: {}'.format(memory_address_bytes))\n    if memory_size_bytes < 1 or memory_size_bytes > 4:\n      raise ValueError('invalid memory_size_bytes: {}'.format(memory_size_bytes))\n    data += bytes([memory_size_bytes << 4 | memory_address_bytes])\n\n    if memory_address >= 1 << (memory_address_bytes * 8):\n      raise ValueError('invalid memory_address: {}'.format(memory_address))\n    data += struct.pack('!I', memory_address)[4 - memory_address_bytes:]\n    if memory_size >= 1 << (memory_size_bytes * 8):\n      raise ValueError('invalid memory_size: {}'.format(memory_size))\n    data += struct.pack('!I', memory_size)[4 - memory_size_bytes:]\n\n    resp = self._uds_request(SERVICE_TYPE.REQUEST_UPLOAD, subfunction=None, data=data)\n    max_num_bytes_len = resp[0] >> 4 if len(resp) > 0 else 0\n    if max_num_bytes_len >= 1 and max_num_bytes_len <= 4:\n      max_num_bytes = struct.unpack('!I', (b\"\\x00\" * (4 - max_num_bytes_len)) + resp[1:max_num_bytes_len + 1])[0]\n    else:\n      raise ValueError('invalid max_num_bytes_len: {}'.format(max_num_bytes_len))\n\n    return max_num_bytes  # max number of bytes per transfer data request\n\n  def transfer_data(self, block_sequence_count: int, data: bytes = b''):\n    data = bytes([block_sequence_count]) + data\n    resp = self._uds_request(SERVICE_TYPE.TRANSFER_DATA, subfunction=None, data=data)\n    resp_id = resp[0] if len(resp) > 0 else None\n    if resp_id != block_sequence_count:\n      raise ValueError('invalid block_sequence_count: {}'.format(resp_id))\n    return resp[1:]\n\n  def request_transfer_exit(self):\n    self._uds_request(SERVICE_TYPE.REQUEST_TRANSFER_EXIT, subfunction=None)\n"
  },
  {
    "path": "panda/python/update.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport time\n\ndef ensure_st_up_to_date():\n  from panda import Panda, PandaDFU, BASEDIR\n\n  with open(os.path.join(BASEDIR, \"VERSION\")) as f:\n    repo_version = f.read()\n\n  repo_version += \"-EON\" if os.path.isfile('/EON') else \"-DEV\"\n\n  panda = None\n  panda_dfu = None\n\n  while 1:\n    # break on normal mode Panda\n    panda_list = Panda.list()\n    if len(panda_list) > 0:\n      panda = Panda(panda_list[0])\n      break\n\n    # flash on DFU mode Panda\n    panda_dfu = PandaDFU.list()\n    if len(panda_dfu) > 0:\n      panda_dfu = PandaDFU(panda_dfu[0])\n      panda_dfu.recover()\n\n    print(\"waiting for board...\")\n    time.sleep(1)\n\n  if panda.bootstub or not panda.get_version().startswith(repo_version):\n    panda.flash()\n\n  if panda.bootstub:\n    panda.recover()\n\n  assert(not panda.bootstub)\n  version = str(panda.get_version())\n  print(\"%s should be %s\" % (version, repo_version))\n  assert(version.startswith(repo_version))\n\nif __name__ == \"__main__\":\n  ensure_st_up_to_date()\n"
  },
  {
    "path": "phonelibs/SConscript",
    "content": "Import('env')\n\nenv.Library('json11', ['json11/json11.cpp'])\nenv.Append(CPPPATH=[Dir('json11')])\n\nenv.Library('kaitai', ['kaitai/kaitaistream.cpp'], CPPDEFINES=['KS_STR_ENCODING_NONE'])\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/get.txt",
    "content": "git clone https://github.com/CyanogenMod/android_frameworks_native.git && cd android_frameworks_native\ngit reset --hard b22bca465e55618a949d9cbdea665a1a3a831241\ncp -r include ~/one/phonelibs/android_frameworks_native/\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/asset_manager.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Asset\n * @{\n */\n\n/**\n * @file asset_manager.h\n */\n\n#ifndef ANDROID_ASSET_MANAGER_H\n#define ANDROID_ASSET_MANAGER_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct AAssetManager;\n/**\n * {@link AAssetManager} provides access to an application's raw assets by\n * creating {@link AAsset} objects.\n *\n * AAssetManager is a wrapper to the low-level native implementation\n * of the java {@link AAssetManager}, a pointer can be obtained using\n * AAssetManager_fromJava().\n *\n * The asset hierarchy may be examined like a filesystem, using\n * {@link AAssetDir} objects to peruse a single directory.\n *\n * A native {@link AAssetManager} pointer may be shared across multiple threads.\n */\ntypedef struct AAssetManager AAssetManager;\n\nstruct AAssetDir;\n/**\n * {@link AAssetDir} provides access to a chunk of the asset hierarchy as if\n * it were a single directory. The contents are populated by the\n * {@link AAssetManager}.\n *\n * The list of files will be sorted in ascending order by ASCII value.\n */\ntypedef struct AAssetDir AAssetDir;\n\nstruct AAsset;\n/**\n * {@link AAsset} provides access to a read-only asset.\n *\n * {@link AAsset} objects are NOT thread-safe, and should not be shared across\n * threads.\n */\ntypedef struct AAsset AAsset;\n\n/** Available access modes for opening assets with {@link AAssetManager_open} */\nenum {\n    /** No specific information about how data will be accessed. **/\n    AASSET_MODE_UNKNOWN      = 0,\n    /** Read chunks, and seek forward and backward. */\n    AASSET_MODE_RANDOM       = 1,\n    /** Read sequentially, with an occasional forward seek. */\n    AASSET_MODE_STREAMING    = 2,\n    /** Caller plans to ask for a read-only buffer with all data. */\n    AASSET_MODE_BUFFER       = 3\n};\n\n\n/**\n * Open the named directory within the asset hierarchy.  The directory can then\n * be inspected with the AAssetDir functions.  To open the top-level directory,\n * pass in \"\" as the dirName.\n *\n * The object returned here should be freed by calling AAssetDir_close().\n */\nAAssetDir* AAssetManager_openDir(AAssetManager* mgr, const char* dirName);\n\n/**\n * Open an asset.\n *\n * The object returned here should be freed by calling AAsset_close().\n */\nAAsset* AAssetManager_open(AAssetManager* mgr, const char* filename, int mode);\n\n/**\n * Iterate over the files in an asset directory.  A NULL string is returned\n * when all the file names have been returned.\n *\n * The returned file name is suitable for passing to AAssetManager_open().\n *\n * The string returned here is owned by the AssetDir implementation and is not\n * guaranteed to remain valid if any other calls are made on this AAssetDir\n * instance.\n */\nconst char* AAssetDir_getNextFileName(AAssetDir* assetDir);\n\n/**\n * Reset the iteration state of AAssetDir_getNextFileName() to the beginning.\n */\nvoid AAssetDir_rewind(AAssetDir* assetDir);\n\n/**\n * Close an opened AAssetDir, freeing any related resources.\n */\nvoid AAssetDir_close(AAssetDir* assetDir);\n\n/**\n * Attempt to read 'count' bytes of data from the current offset.\n *\n * Returns the number of bytes read, zero on EOF, or < 0 on error.\n */\nint AAsset_read(AAsset* asset, void* buf, size_t count);\n\n/**\n * Seek to the specified offset within the asset data.  'whence' uses the\n * same constants as lseek()/fseek().\n *\n * Returns the new position on success, or (off_t) -1 on error.\n */\noff_t AAsset_seek(AAsset* asset, off_t offset, int whence);\n\n/**\n * Seek to the specified offset within the asset data.  'whence' uses the\n * same constants as lseek()/fseek().\n *\n * Uses 64-bit data type for large files as opposed to the 32-bit type used\n * by AAsset_seek.\n *\n * Returns the new position on success, or (off64_t) -1 on error.\n */\noff64_t AAsset_seek64(AAsset* asset, off64_t offset, int whence);\n\n/**\n * Close the asset, freeing all associated resources.\n */\nvoid AAsset_close(AAsset* asset);\n\n/**\n * Get a pointer to a buffer holding the entire contents of the assset.\n *\n * Returns NULL on failure.\n */\nconst void* AAsset_getBuffer(AAsset* asset);\n\n/**\n * Report the total size of the asset data.\n */\noff_t AAsset_getLength(AAsset* asset);\n\n/**\n * Report the total size of the asset data. Reports the size using a 64-bit\n * number insted of 32-bit as AAsset_getLength.\n */\noff64_t AAsset_getLength64(AAsset* asset);\n\n/**\n * Report the total amount of asset data that can be read from the current position.\n */\noff_t AAsset_getRemainingLength(AAsset* asset);\n\n/**\n * Report the total amount of asset data that can be read from the current position.\n *\n * Uses a 64-bit number instead of a 32-bit number as AAsset_getRemainingLength does.\n */\noff64_t AAsset_getRemainingLength64(AAsset* asset);\n\n/**\n * Open a new file descriptor that can be used to read the asset data. If the\n * start or length cannot be represented by a 32-bit number, it will be\n * truncated. If the file is large, use AAsset_openFileDescriptor64 instead.\n *\n * Returns < 0 if direct fd access is not possible (for example, if the asset is\n * compressed).\n */\nint AAsset_openFileDescriptor(AAsset* asset, off_t* outStart, off_t* outLength);\n\n/**\n * Open a new file descriptor that can be used to read the asset data.\n *\n * Uses a 64-bit number for the offset and length instead of 32-bit instead of\n * as AAsset_openFileDescriptor does.\n *\n * Returns < 0 if direct fd access is not possible (for example, if the asset is\n * compressed).\n */\nint AAsset_openFileDescriptor64(AAsset* asset, off64_t* outStart, off64_t* outLength);\n\n/**\n * Returns whether this asset's internal buffer is allocated in ordinary RAM (i.e. not\n * mmapped).\n */\nint AAsset_isAllocated(AAsset* asset);\n\n\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif      // ANDROID_ASSET_MANAGER_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/asset_manager_jni.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Asset\n * @{\n */\n\n/**\n * @file asset_manager_jni.h\n */\n\n#ifndef ANDROID_ASSET_MANAGER_JNI_H\n#define ANDROID_ASSET_MANAGER_JNI_H\n\n#include <android/asset_manager.h>\n#include <jni.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Given a Dalvik AssetManager object, obtain the corresponding native AAssetManager\n * object.  Note that the caller is responsible for obtaining and holding a VM reference\n * to the jobject to prevent its being garbage collected while the native object is\n * in use.\n */\nAAssetManager* AAssetManager_fromJava(JNIEnv* env, jobject assetManager);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif      // ANDROID_ASSET_MANAGER_JNI_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/bitmap.h",
    "content": "/*\n * Copyright (C) 2009 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Bitmap\n * @{\n */\n\n/**\n * @file bitmap.h\n */\n\n#ifndef ANDROID_BITMAP_H\n#define ANDROID_BITMAP_H\n\n#include <stdint.h>\n#include <jni.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** AndroidBitmap functions result code. */\nenum {\n    /** Operation was successful. */\n    ANDROID_BITMAP_RESULT_SUCCESS           = 0,\n    /** Bad parameter. */\n    ANDROID_BITMAP_RESULT_BAD_PARAMETER     = -1,\n    /** JNI exception occured. */\n    ANDROID_BITMAP_RESULT_JNI_EXCEPTION     = -2,\n    /** Allocation failed. */\n    ANDROID_BITMAP_RESULT_ALLOCATION_FAILED = -3,\n};\n\n/** Backward compatibility: this macro used to be misspelled. */\n#define ANDROID_BITMAP_RESUT_SUCCESS ANDROID_BITMAP_RESULT_SUCCESS\n\n/** Bitmap pixel format. */\nenum AndroidBitmapFormat {\n    /** No format. */\n    ANDROID_BITMAP_FORMAT_NONE      = 0,\n    /** Red: 8 bits, Green: 8 bits, Blue: 8 bits, Alpha: 8 bits. **/\n    ANDROID_BITMAP_FORMAT_RGBA_8888 = 1,\n    /** Red: 5 bits, Green: 6 bits, Blue: 5 bits. **/\n    ANDROID_BITMAP_FORMAT_RGB_565   = 4,\n    /** Red: 4 bits, Green: 4 bits, Blue: 4 bits, Alpha: 4 bits. **/\n    ANDROID_BITMAP_FORMAT_RGBA_4444 = 7,\n    /** Deprecated. */\n    ANDROID_BITMAP_FORMAT_A_8       = 8,\n};\n\n/** Bitmap info, see AndroidBitmap_getInfo(). */\ntypedef struct {\n    /** The bitmap width in pixels. */\n    uint32_t    width;\n    /** The bitmap height in pixels. */\n    uint32_t    height;\n    /** The number of byte per row. */\n    uint32_t    stride;\n    /** The bitmap pixel format. See {@link AndroidBitmapFormat} */\n    int32_t     format;\n    /** Unused. */\n    uint32_t    flags;      // 0 for now\n} AndroidBitmapInfo;\n\n/**\n * Given a java bitmap object, fill out the AndroidBitmapInfo struct for it.\n * If the call fails, the info parameter will be ignored.\n */\nint AndroidBitmap_getInfo(JNIEnv* env, jobject jbitmap,\n                          AndroidBitmapInfo* info);\n\n/**\n * Given a java bitmap object, attempt to lock the pixel address.\n * Locking will ensure that the memory for the pixels will not move\n * until the unlockPixels call, and ensure that, if the pixels had been\n * previously purged, they will have been restored.\n *\n * If this call succeeds, it must be balanced by a call to\n * AndroidBitmap_unlockPixels, after which time the address of the pixels should\n * no longer be used.\n *\n * If this succeeds, *addrPtr will be set to the pixel address. If the call\n * fails, addrPtr will be ignored.\n */\nint AndroidBitmap_lockPixels(JNIEnv* env, jobject jbitmap, void** addrPtr);\n\n/**\n * Call this to balance a successful call to AndroidBitmap_lockPixels.\n */\nint AndroidBitmap_unlockPixels(JNIEnv* env, jobject jbitmap);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/configuration.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Configuration\n * @{\n */\n\n/**\n * @file configuration.h\n */\n\n#ifndef ANDROID_CONFIGURATION_H\n#define ANDROID_CONFIGURATION_H\n\n#include <android/asset_manager.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct AConfiguration;\n/**\n * {@link AConfiguration} is an opaque type used to get and set\n * various subsystem configurations.\n *\n * A {@link AConfiguration} pointer can be obtained using:\n * - AConfiguration_new()\n * - AConfiguration_fromAssetManager()\n */\ntypedef struct AConfiguration AConfiguration;\n\n\n/**\n * Define flags and constants for various subsystem configurations.\n */\nenum {\n    /** Orientation: not specified. */\n    ACONFIGURATION_ORIENTATION_ANY  = 0x0000,\n    /**\n     * Orientation: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#OrientationQualifier\">port</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_ORIENTATION_PORT = 0x0001,\n    /**\n     * Orientation: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#OrientationQualifier\">land</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_ORIENTATION_LAND = 0x0002,\n    /** @deprecated Not currently supported or used. */\n    ACONFIGURATION_ORIENTATION_SQUARE = 0x0003,\n\n    /** Touchscreen: not specified. */\n    ACONFIGURATION_TOUCHSCREEN_ANY  = 0x0000,\n    /**\n     * Touchscreen: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#TouchscreenQualifier\">notouch</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_TOUCHSCREEN_NOTOUCH  = 0x0001,\n    /** @deprecated Not currently supported or used. */\n    ACONFIGURATION_TOUCHSCREEN_STYLUS  = 0x0002,\n    /**\n     * Touchscreen: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#TouchscreenQualifier\">finger</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_TOUCHSCREEN_FINGER  = 0x0003,\n\n    /** Density: default density. */\n    ACONFIGURATION_DENSITY_DEFAULT = 0,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">ldpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_LOW = 120,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">mdpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_MEDIUM = 160,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">tvdpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_TV = 213,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">hdpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_HIGH = 240,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">xhdpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_XHIGH = 320,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">xxhdpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_XXHIGH = 480,\n    /**\n     * Density: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">xxxhdpi</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_DENSITY_XXXHIGH = 640,\n    /** Density: any density. */\n    ACONFIGURATION_DENSITY_ANY = 0xfffe,\n    /** Density: no density specified. */\n    ACONFIGURATION_DENSITY_NONE = 0xffff,\n\n    /** Keyboard: not specified. */\n    ACONFIGURATION_KEYBOARD_ANY  = 0x0000,\n    /**\n     * Keyboard: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ImeQualifier\">nokeys</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_KEYBOARD_NOKEYS  = 0x0001,\n    /**\n     * Keyboard: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ImeQualifier\">qwerty</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_KEYBOARD_QWERTY  = 0x0002,\n    /**\n     * Keyboard: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ImeQualifier\">12key</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_KEYBOARD_12KEY  = 0x0003,\n\n    /** Navigation: not specified. */\n    ACONFIGURATION_NAVIGATION_ANY  = 0x0000,\n    /**\n     * Navigation: value corresponding to the\n     * <a href=\"@@dacRoot/guide/topics/resources/providing-resources.html#NavigationQualifier\">nonav</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_NAVIGATION_NONAV  = 0x0001,\n    /**\n     * Navigation: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NavigationQualifier\">dpad</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_NAVIGATION_DPAD  = 0x0002,\n    /**\n     * Navigation: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NavigationQualifier\">trackball</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_NAVIGATION_TRACKBALL  = 0x0003,\n    /**\n     * Navigation: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NavigationQualifier\">wheel</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_NAVIGATION_WHEEL  = 0x0004,\n\n    /** Keyboard availability: not specified. */\n    ACONFIGURATION_KEYSHIDDEN_ANY = 0x0000,\n    /**\n     * Keyboard availability: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#KeyboardAvailQualifier\">keysexposed</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_KEYSHIDDEN_NO = 0x0001,\n    /**\n     * Keyboard availability: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#KeyboardAvailQualifier\">keyshidden</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_KEYSHIDDEN_YES = 0x0002,\n    /**\n     * Keyboard availability: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#KeyboardAvailQualifier\">keyssoft</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_KEYSHIDDEN_SOFT = 0x0003,\n\n    /** Navigation availability: not specified. */\n    ACONFIGURATION_NAVHIDDEN_ANY = 0x0000,\n    /**\n     * Navigation availability: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NavAvailQualifier\">navexposed</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_NAVHIDDEN_NO = 0x0001,\n    /**\n     * Navigation availability: value corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NavAvailQualifier\">navhidden</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_NAVHIDDEN_YES = 0x0002,\n\n    /** Screen size: not specified. */\n    ACONFIGURATION_SCREENSIZE_ANY  = 0x00,\n    /**\n     * Screen size: value indicating the screen is at least\n     * approximately 320x426 dp units, corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenSizeQualifier\">small</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_SCREENSIZE_SMALL = 0x01,\n    /**\n     * Screen size: value indicating the screen is at least\n     * approximately 320x470 dp units, corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenSizeQualifier\">normal</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_SCREENSIZE_NORMAL = 0x02,\n    /**\n     * Screen size: value indicating the screen is at least\n     * approximately 480x640 dp units, corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenSizeQualifier\">large</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_SCREENSIZE_LARGE = 0x03,\n    /**\n     * Screen size: value indicating the screen is at least\n     * approximately 720x960 dp units, corresponding to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenSizeQualifier\">xlarge</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_SCREENSIZE_XLARGE = 0x04,\n\n    /** Screen layout: not specified. */\n    ACONFIGURATION_SCREENLONG_ANY = 0x00,\n    /**\n     * Screen layout: value that corresponds to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenAspectQualifier\">notlong</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_SCREENLONG_NO = 0x1,\n    /**\n     * Screen layout: value that corresponds to the\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenAspectQualifier\">long</a>\n     * resource qualifier.\n     */\n    ACONFIGURATION_SCREENLONG_YES = 0x2,\n\n    ACONFIGURATION_SCREENROUND_ANY = 0x00,\n    ACONFIGURATION_SCREENROUND_NO = 0x1,\n    ACONFIGURATION_SCREENROUND_YES = 0x2,\n\n    /** UI mode: not specified. */\n    ACONFIGURATION_UI_MODE_TYPE_ANY = 0x00,\n    /**\n     * UI mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">no\n     * UI mode type</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_TYPE_NORMAL = 0x01,\n    /**\n     * UI mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">desk</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_TYPE_DESK = 0x02,\n    /**\n     * UI mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">car</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_TYPE_CAR = 0x03,\n    /**\n     * UI mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">television</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_TYPE_TELEVISION = 0x04,\n    /**\n     * UI mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">appliance</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_TYPE_APPLIANCE = 0x05,\n    /**\n     * UI mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">watch</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_TYPE_WATCH = 0x06,\n\n    /** UI night mode: not specified.*/\n    ACONFIGURATION_UI_MODE_NIGHT_ANY = 0x00,\n    /**\n     * UI night mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NightQualifier\">notnight</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_NIGHT_NO = 0x1,\n    /**\n     * UI night mode: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NightQualifier\">night</a> resource qualifier specified.\n     */\n    ACONFIGURATION_UI_MODE_NIGHT_YES = 0x2,\n\n    /** Screen width DPI: not specified. */\n    ACONFIGURATION_SCREEN_WIDTH_DP_ANY = 0x0000,\n\n    /** Screen height DPI: not specified. */\n    ACONFIGURATION_SCREEN_HEIGHT_DP_ANY = 0x0000,\n\n    /** Smallest screen width DPI: not specified.*/\n    ACONFIGURATION_SMALLEST_SCREEN_WIDTH_DP_ANY = 0x0000,\n\n    /** Layout direction: not specified. */\n    ACONFIGURATION_LAYOUTDIR_ANY  = 0x00,\n    /**\n     * Layout direction: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#LayoutDirectionQualifier\">ldltr</a> resource qualifier specified.\n     */\n    ACONFIGURATION_LAYOUTDIR_LTR  = 0x01,\n    /**\n     * Layout direction: value that corresponds to\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#LayoutDirectionQualifier\">ldrtl</a> resource qualifier specified.\n     */\n    ACONFIGURATION_LAYOUTDIR_RTL  = 0x02,\n\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#MccQualifier\">mcc</a>\n     * configuration.\n     */\n    ACONFIGURATION_MCC = 0x0001,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#MccQualifier\">mnc</a>\n     * configuration.\n     */\n    ACONFIGURATION_MNC = 0x0002,\n    /**\n     * Bit mask for\n     * <a href=\"{@docRoot}guide/topics/resources/providing-resources.html#LocaleQualifier\">locale</a>\n     * configuration.\n     */\n    ACONFIGURATION_LOCALE = 0x0004,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#TouchscreenQualifier\">touchscreen</a>\n     * configuration.\n     */\n    ACONFIGURATION_TOUCHSCREEN = 0x0008,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ImeQualifier\">keyboard</a>\n     * configuration.\n     */\n    ACONFIGURATION_KEYBOARD = 0x0010,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#KeyboardAvailQualifier\">keyboardHidden</a>\n     * configuration.\n     */\n    ACONFIGURATION_KEYBOARD_HIDDEN = 0x0020,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#NavigationQualifier\">navigation</a>\n     * configuration.\n     */\n    ACONFIGURATION_NAVIGATION = 0x0040,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#OrientationQualifier\">orientation</a>\n     * configuration.\n     */\n    ACONFIGURATION_ORIENTATION = 0x0080,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#DensityQualifier\">density</a>\n     * configuration.\n     */\n    ACONFIGURATION_DENSITY = 0x0100,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#ScreenSizeQualifier\">screen size</a>\n     * configuration.\n     */\n    ACONFIGURATION_SCREEN_SIZE = 0x0200,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#VersionQualifier\">platform version</a>\n     * configuration.\n     */\n    ACONFIGURATION_VERSION = 0x0400,\n    /**\n     * Bit mask for screen layout configuration.\n     */\n    ACONFIGURATION_SCREEN_LAYOUT = 0x0800,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#UiModeQualifier\">ui mode</a>\n     * configuration.\n     */\n    ACONFIGURATION_UI_MODE = 0x1000,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#SmallestScreenWidthQualifier\">smallest screen width</a>\n     * configuration.\n     */\n    ACONFIGURATION_SMALLEST_SCREEN_SIZE = 0x2000,\n    /**\n     * Bit mask for\n     * <a href=\"@dacRoot/guide/topics/resources/providing-resources.html#LayoutDirectionQualifier\">layout direction</a>\n     * configuration.\n     */\n    ACONFIGURATION_LAYOUTDIR = 0x4000,\n    ACONFIGURATION_SCREEN_ROUND = 0x8000,\n    /**\n     * Constant used to to represent MNC (Mobile Network Code) zero.\n     * 0 cannot be used, since it is used to represent an undefined MNC.\n     */\n    ACONFIGURATION_MNC_ZERO = 0xffff,\n};\n\n/**\n * Create a new AConfiguration, initialized with no values set.\n */\nAConfiguration* AConfiguration_new();\n\n/**\n * Free an AConfiguration that was previously created with\n * AConfiguration_new().\n */\nvoid AConfiguration_delete(AConfiguration* config);\n\n/**\n * Create and return a new AConfiguration based on the current configuration in\n * use in the given {@link AAssetManager}.\n */\nvoid AConfiguration_fromAssetManager(AConfiguration* out, AAssetManager* am);\n\n/**\n * Copy the contents of 'src' to 'dest'.\n */\nvoid AConfiguration_copy(AConfiguration* dest, AConfiguration* src);\n\n/**\n * Return the current MCC set in the configuration.  0 if not set.\n */\nint32_t AConfiguration_getMcc(AConfiguration* config);\n\n/**\n * Set the current MCC in the configuration.  0 to clear.\n */\nvoid AConfiguration_setMcc(AConfiguration* config, int32_t mcc);\n\n/**\n * Return the current MNC set in the configuration.  0 if not set.\n */\nint32_t AConfiguration_getMnc(AConfiguration* config);\n\n/**\n * Set the current MNC in the configuration.  0 to clear.\n */\nvoid AConfiguration_setMnc(AConfiguration* config, int32_t mnc);\n\n/**\n * Return the current language code set in the configuration.  The output will\n * be filled with an array of two characters.  They are not 0-terminated.  If\n * a language is not set, they will be 0.\n */\nvoid AConfiguration_getLanguage(AConfiguration* config, char* outLanguage);\n\n/**\n * Set the current language code in the configuration, from the first two\n * characters in the string.\n */\nvoid AConfiguration_setLanguage(AConfiguration* config, const char* language);\n\n/**\n * Return the current country code set in the configuration.  The output will\n * be filled with an array of two characters.  They are not 0-terminated.  If\n * a country is not set, they will be 0.\n */\nvoid AConfiguration_getCountry(AConfiguration* config, char* outCountry);\n\n/**\n * Set the current country code in the configuration, from the first two\n * characters in the string.\n */\nvoid AConfiguration_setCountry(AConfiguration* config, const char* country);\n\n/**\n * Return the current ACONFIGURATION_ORIENTATION_* set in the configuration.\n */\nint32_t AConfiguration_getOrientation(AConfiguration* config);\n\n/**\n * Set the current orientation in the configuration.\n */\nvoid AConfiguration_setOrientation(AConfiguration* config, int32_t orientation);\n\n/**\n * Return the current ACONFIGURATION_TOUCHSCREEN_* set in the configuration.\n */\nint32_t AConfiguration_getTouchscreen(AConfiguration* config);\n\n/**\n * Set the current touchscreen in the configuration.\n */\nvoid AConfiguration_setTouchscreen(AConfiguration* config, int32_t touchscreen);\n\n/**\n * Return the current ACONFIGURATION_DENSITY_* set in the configuration.\n */\nint32_t AConfiguration_getDensity(AConfiguration* config);\n\n/**\n * Set the current density in the configuration.\n */\nvoid AConfiguration_setDensity(AConfiguration* config, int32_t density);\n\n/**\n * Return the current ACONFIGURATION_KEYBOARD_* set in the configuration.\n */\nint32_t AConfiguration_getKeyboard(AConfiguration* config);\n\n/**\n * Set the current keyboard in the configuration.\n */\nvoid AConfiguration_setKeyboard(AConfiguration* config, int32_t keyboard);\n\n/**\n * Return the current ACONFIGURATION_NAVIGATION_* set in the configuration.\n */\nint32_t AConfiguration_getNavigation(AConfiguration* config);\n\n/**\n * Set the current navigation in the configuration.\n */\nvoid AConfiguration_setNavigation(AConfiguration* config, int32_t navigation);\n\n/**\n * Return the current ACONFIGURATION_KEYSHIDDEN_* set in the configuration.\n */\nint32_t AConfiguration_getKeysHidden(AConfiguration* config);\n\n/**\n * Set the current keys hidden in the configuration.\n */\nvoid AConfiguration_setKeysHidden(AConfiguration* config, int32_t keysHidden);\n\n/**\n * Return the current ACONFIGURATION_NAVHIDDEN_* set in the configuration.\n */\nint32_t AConfiguration_getNavHidden(AConfiguration* config);\n\n/**\n * Set the current nav hidden in the configuration.\n */\nvoid AConfiguration_setNavHidden(AConfiguration* config, int32_t navHidden);\n\n/**\n * Return the current SDK (API) version set in the configuration.\n */\nint32_t AConfiguration_getSdkVersion(AConfiguration* config);\n\n/**\n * Set the current SDK version in the configuration.\n */\nvoid AConfiguration_setSdkVersion(AConfiguration* config, int32_t sdkVersion);\n\n/**\n * Return the current ACONFIGURATION_SCREENSIZE_* set in the configuration.\n */\nint32_t AConfiguration_getScreenSize(AConfiguration* config);\n\n/**\n * Set the current screen size in the configuration.\n */\nvoid AConfiguration_setScreenSize(AConfiguration* config, int32_t screenSize);\n\n/**\n * Return the current ACONFIGURATION_SCREENLONG_* set in the configuration.\n */\nint32_t AConfiguration_getScreenLong(AConfiguration* config);\n\n/**\n * Set the current screen long in the configuration.\n */\nvoid AConfiguration_setScreenLong(AConfiguration* config, int32_t screenLong);\n\n/**\n * Return the current ACONFIGURATION_SCREENROUND_* set in the configuration.\n */\nint32_t AConfiguration_getScreenRound(AConfiguration* config);\n\n/**\n * Set the current screen round in the configuration.\n */\nvoid AConfiguration_setScreenRound(AConfiguration* config, int32_t screenRound);\n\n/**\n * Return the current ACONFIGURATION_UI_MODE_TYPE_* set in the configuration.\n */\nint32_t AConfiguration_getUiModeType(AConfiguration* config);\n\n/**\n * Set the current UI mode type in the configuration.\n */\nvoid AConfiguration_setUiModeType(AConfiguration* config, int32_t uiModeType);\n\n/**\n * Return the current ACONFIGURATION_UI_MODE_NIGHT_* set in the configuration.\n */\nint32_t AConfiguration_getUiModeNight(AConfiguration* config);\n\n/**\n * Set the current UI mode night in the configuration.\n */\nvoid AConfiguration_setUiModeNight(AConfiguration* config, int32_t uiModeNight);\n\n/**\n * Return the current configuration screen width in dp units, or\n * ACONFIGURATION_SCREEN_WIDTH_DP_ANY if not set.\n */\nint32_t AConfiguration_getScreenWidthDp(AConfiguration* config);\n\n/**\n * Set the configuration's current screen width in dp units.\n */\nvoid AConfiguration_setScreenWidthDp(AConfiguration* config, int32_t value);\n\n/**\n * Return the current configuration screen height in dp units, or\n * ACONFIGURATION_SCREEN_HEIGHT_DP_ANY if not set.\n */\nint32_t AConfiguration_getScreenHeightDp(AConfiguration* config);\n\n/**\n * Set the configuration's current screen width in dp units.\n */\nvoid AConfiguration_setScreenHeightDp(AConfiguration* config, int32_t value);\n\n/**\n * Return the configuration's smallest screen width in dp units, or\n * ACONFIGURATION_SMALLEST_SCREEN_WIDTH_DP_ANY if not set.\n */\nint32_t AConfiguration_getSmallestScreenWidthDp(AConfiguration* config);\n\n/**\n * Set the configuration's smallest screen width in dp units.\n */\nvoid AConfiguration_setSmallestScreenWidthDp(AConfiguration* config, int32_t value);\n\n/**\n * Return the configuration's layout direction, or\n * ACONFIGURATION_LAYOUTDIR_ANY if not set.\n */\nint32_t AConfiguration_getLayoutDirection(AConfiguration* config);\n\n/**\n * Set the configuration's layout direction.\n */\nvoid AConfiguration_setLayoutDirection(AConfiguration* config, int32_t value);\n\n/**\n * Perform a diff between two configurations.  Returns a bit mask of\n * ACONFIGURATION_* constants, each bit set meaning that configuration element\n * is different between them.\n */\nint32_t AConfiguration_diff(AConfiguration* config1, AConfiguration* config2);\n\n/**\n * Determine whether 'base' is a valid configuration for use within the\n * environment 'requested'.  Returns 0 if there are any values in 'base'\n * that conflict with 'requested'.  Returns 1 if it does not conflict.\n */\nint32_t AConfiguration_match(AConfiguration* base, AConfiguration* requested);\n\n/**\n * Determine whether the configuration in 'test' is better than the existing\n * configuration in 'base'.  If 'requested' is non-NULL, this decision is based\n * on the overall configuration given there.  If it is NULL, this decision is\n * simply based on which configuration is more specific.  Returns non-0 if\n * 'test' is better than 'base'.\n *\n * This assumes you have already filtered the configurations with\n * AConfiguration_match().\n */\nint32_t AConfiguration_isBetterThan(AConfiguration* base, AConfiguration* test,\n        AConfiguration* requested);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_CONFIGURATION_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/input.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Input\n * @{\n */\n\n/**\n * @file input.h\n */\n\n#ifndef _ANDROID_INPUT_H\n#define _ANDROID_INPUT_H\n\n/******************************************************************\n *\n * IMPORTANT NOTICE:\n *\n *   This file is part of Android's set of stable system headers\n *   exposed by the Android NDK (Native Development Kit).\n *\n *   Third-party source AND binary code relies on the definitions\n *   here to be FROZEN ON ALL UPCOMING PLATFORM RELEASES.\n *\n *   - DO NOT MODIFY ENUMS (EXCEPT IF YOU ADD NEW 32-BIT VALUES)\n *   - DO NOT MODIFY CONSTANTS OR FUNCTIONAL MACROS\n *   - DO NOT CHANGE THE SIGNATURE OF FUNCTIONS IN ANY WAY\n *   - DO NOT CHANGE THE LAYOUT OR SIZE OF STRUCTURES\n */\n\n/*\n * Structures and functions to receive and process input events in\n * native code.\n *\n * NOTE: These functions MUST be implemented by /system/lib/libui.so\n */\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <android/keycodes.h>\n#include <android/looper.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Key states (may be returned by queries about the current state of a\n * particular key code, scan code or switch).\n */\nenum {\n    /** The key state is unknown or the requested key itself is not supported. */\n    AKEY_STATE_UNKNOWN = -1,\n\n    /** The key is up. */\n    AKEY_STATE_UP = 0,\n\n    /** The key is down. */\n    AKEY_STATE_DOWN = 1,\n\n    /** The key is down but is a virtual key press that is being emulated by the system. */\n    AKEY_STATE_VIRTUAL = 2\n};\n\n/**\n * Meta key / modifer state.\n */\nenum {\n    /** No meta keys are pressed. */\n    AMETA_NONE = 0,\n\n    /** This mask is used to check whether one of the ALT meta keys is pressed. */\n    AMETA_ALT_ON = 0x02,\n\n    /** This mask is used to check whether the left ALT meta key is pressed. */\n    AMETA_ALT_LEFT_ON = 0x10,\n\n    /** This mask is used to check whether the right ALT meta key is pressed. */\n    AMETA_ALT_RIGHT_ON = 0x20,\n\n    /** This mask is used to check whether one of the SHIFT meta keys is pressed. */\n    AMETA_SHIFT_ON = 0x01,\n\n    /** This mask is used to check whether the left SHIFT meta key is pressed. */\n    AMETA_SHIFT_LEFT_ON = 0x40,\n\n    /** This mask is used to check whether the right SHIFT meta key is pressed. */\n    AMETA_SHIFT_RIGHT_ON = 0x80,\n\n    /** This mask is used to check whether the SYM meta key is pressed. */\n    AMETA_SYM_ON = 0x04,\n\n    /** This mask is used to check whether the FUNCTION meta key is pressed. */\n    AMETA_FUNCTION_ON = 0x08,\n\n    /** This mask is used to check whether one of the CTRL meta keys is pressed. */\n    AMETA_CTRL_ON = 0x1000,\n\n    /** This mask is used to check whether the left CTRL meta key is pressed. */\n    AMETA_CTRL_LEFT_ON = 0x2000,\n\n    /** This mask is used to check whether the right CTRL meta key is pressed. */\n    AMETA_CTRL_RIGHT_ON = 0x4000,\n\n    /** This mask is used to check whether one of the META meta keys is pressed. */\n    AMETA_META_ON = 0x10000,\n\n    /** This mask is used to check whether the left META meta key is pressed. */\n    AMETA_META_LEFT_ON = 0x20000,\n\n    /** This mask is used to check whether the right META meta key is pressed. */\n    AMETA_META_RIGHT_ON = 0x40000,\n\n    /** This mask is used to check whether the CAPS LOCK meta key is on. */\n    AMETA_CAPS_LOCK_ON = 0x100000,\n\n    /** This mask is used to check whether the NUM LOCK meta key is on. */\n    AMETA_NUM_LOCK_ON = 0x200000,\n\n    /** This mask is used to check whether the SCROLL LOCK meta key is on. */\n    AMETA_SCROLL_LOCK_ON = 0x400000,\n};\n\nstruct AInputEvent;\n/**\n * Input events.\n *\n * Input events are opaque structures.  Use the provided accessors functions to\n * read their properties.\n */\ntypedef struct AInputEvent AInputEvent;\n\n/**\n * Input event types.\n */\nenum {\n    /** Indicates that the input event is a key event. */\n    AINPUT_EVENT_TYPE_KEY = 1,\n\n    /** Indicates that the input event is a motion event. */\n    AINPUT_EVENT_TYPE_MOTION = 2\n};\n\n/**\n * Key event actions.\n */\nenum {\n    /** The key has been pressed down. */\n    AKEY_EVENT_ACTION_DOWN = 0,\n\n    /** The key has been released. */\n    AKEY_EVENT_ACTION_UP = 1,\n\n    /**\n     * Multiple duplicate key events have occurred in a row, or a\n     * complex string is being delivered.  The repeat_count property\n     * of the key event contains the number of times the given key\n     * code should be executed.\n     */\n    AKEY_EVENT_ACTION_MULTIPLE = 2\n};\n\n/**\n * Key event flags.\n */\nenum {\n    /** This mask is set if the device woke because of this key event. */\n    AKEY_EVENT_FLAG_WOKE_HERE = 0x1,\n\n    /** This mask is set if the key event was generated by a software keyboard. */\n    AKEY_EVENT_FLAG_SOFT_KEYBOARD = 0x2,\n\n    /** This mask is set if we don't want the key event to cause us to leave touch mode. */\n    AKEY_EVENT_FLAG_KEEP_TOUCH_MODE = 0x4,\n\n    /**\n     * This mask is set if an event was known to come from a trusted\n     * part of the system.  That is, the event is known to come from\n     * the user, and could not have been spoofed by a third party\n     * component.\n     */\n    AKEY_EVENT_FLAG_FROM_SYSTEM = 0x8,\n\n    /**\n     * This mask is used for compatibility, to identify enter keys that are\n     * coming from an IME whose enter key has been auto-labelled \"next\" or\n     * \"done\".  This allows TextView to dispatch these as normal enter keys\n     * for old applications, but still do the appropriate action when\n     * receiving them.\n     */\n    AKEY_EVENT_FLAG_EDITOR_ACTION = 0x10,\n\n    /**\n     * When associated with up key events, this indicates that the key press\n     * has been canceled.  Typically this is used with virtual touch screen\n     * keys, where the user can slide from the virtual key area on to the\n     * display: in that case, the application will receive a canceled up\n     * event and should not perform the action normally associated with the\n     * key.  Note that for this to work, the application can not perform an\n     * action for a key until it receives an up or the long press timeout has\n     * expired.\n     */\n    AKEY_EVENT_FLAG_CANCELED = 0x20,\n\n    /**\n     * This key event was generated by a virtual (on-screen) hard key area.\n     * Typically this is an area of the touchscreen, outside of the regular\n     * display, dedicated to \"hardware\" buttons.\n     */\n    AKEY_EVENT_FLAG_VIRTUAL_HARD_KEY = 0x40,\n\n    /**\n     * This flag is set for the first key repeat that occurs after the\n     * long press timeout.\n     */\n    AKEY_EVENT_FLAG_LONG_PRESS = 0x80,\n\n    /**\n     * Set when a key event has AKEY_EVENT_FLAG_CANCELED set because a long\n     * press action was executed while it was down.\n     */\n    AKEY_EVENT_FLAG_CANCELED_LONG_PRESS = 0x100,\n\n    /**\n     * Set for AKEY_EVENT_ACTION_UP when this event's key code is still being\n     * tracked from its initial down.  That is, somebody requested that tracking\n     * started on the key down and a long press has not caused\n     * the tracking to be canceled.\n     */\n    AKEY_EVENT_FLAG_TRACKING = 0x200,\n\n    /**\n     * Set when a key event has been synthesized to implement default behavior\n     * for an event that the application did not handle.\n     * Fallback key events are generated by unhandled trackball motions\n     * (to emulate a directional keypad) and by certain unhandled key presses\n     * that are declared in the key map (such as special function numeric keypad\n     * keys when numlock is off).\n     */\n    AKEY_EVENT_FLAG_FALLBACK = 0x400,\n};\n\n/**\n * Bit shift for the action bits holding the pointer index as\n * defined by AMOTION_EVENT_ACTION_POINTER_INDEX_MASK.\n */\n#define AMOTION_EVENT_ACTION_POINTER_INDEX_SHIFT 8\n\n/** Motion event actions */\nenum {\n    /** Bit mask of the parts of the action code that are the action itself. */\n    AMOTION_EVENT_ACTION_MASK = 0xff,\n\n    /**\n     * Bits in the action code that represent a pointer index, used with\n     * AMOTION_EVENT_ACTION_POINTER_DOWN and AMOTION_EVENT_ACTION_POINTER_UP.  Shifting\n     * down by AMOTION_EVENT_ACTION_POINTER_INDEX_SHIFT provides the actual pointer\n     * index where the data for the pointer going up or down can be found.\n     */\n    AMOTION_EVENT_ACTION_POINTER_INDEX_MASK  = 0xff00,\n\n    /** A pressed gesture has started, the motion contains the initial starting location. */\n    AMOTION_EVENT_ACTION_DOWN = 0,\n\n    /**\n     * A pressed gesture has finished, the motion contains the final release location\n     * as well as any intermediate points since the last down or move event.\n     */\n    AMOTION_EVENT_ACTION_UP = 1,\n\n    /**\n     * A change has happened during a press gesture (between AMOTION_EVENT_ACTION_DOWN and\n     * AMOTION_EVENT_ACTION_UP).  The motion contains the most recent point, as well as\n     * any intermediate points since the last down or move event.\n     */\n    AMOTION_EVENT_ACTION_MOVE = 2,\n\n    /**\n     * The current gesture has been aborted.\n     * You will not receive any more points in it.  You should treat this as\n     * an up event, but not perform any action that you normally would.\n     */\n    AMOTION_EVENT_ACTION_CANCEL = 3,\n\n    /**\n     * A movement has happened outside of the normal bounds of the UI element.\n     * This does not provide a full gesture, but only the initial location of the movement/touch.\n     */\n    AMOTION_EVENT_ACTION_OUTSIDE = 4,\n\n    /**\n     * A non-primary pointer has gone down.\n     * The bits in AMOTION_EVENT_ACTION_POINTER_INDEX_MASK indicate which pointer changed.\n     */\n    AMOTION_EVENT_ACTION_POINTER_DOWN = 5,\n\n    /**\n     * A non-primary pointer has gone up.\n     * The bits in AMOTION_EVENT_ACTION_POINTER_INDEX_MASK indicate which pointer changed.\n     */\n    AMOTION_EVENT_ACTION_POINTER_UP = 6,\n\n    /**\n     * A change happened but the pointer is not down (unlike AMOTION_EVENT_ACTION_MOVE).\n     * The motion contains the most recent point, as well as any intermediate points since\n     * the last hover move event.\n     */\n    AMOTION_EVENT_ACTION_HOVER_MOVE = 7,\n\n    /**\n     * The motion event contains relative vertical and/or horizontal scroll offsets.\n     * Use getAxisValue to retrieve the information from AMOTION_EVENT_AXIS_VSCROLL\n     * and AMOTION_EVENT_AXIS_HSCROLL.\n     * The pointer may or may not be down when this event is dispatched.\n     * This action is always delivered to the winder under the pointer, which\n     * may not be the window currently touched.\n     */\n    AMOTION_EVENT_ACTION_SCROLL = 8,\n\n    /** The pointer is not down but has entered the boundaries of a window or view. */\n    AMOTION_EVENT_ACTION_HOVER_ENTER = 9,\n\n    /** The pointer is not down but has exited the boundaries of a window or view. */\n    AMOTION_EVENT_ACTION_HOVER_EXIT = 10,\n\n    /* One or more buttons have been pressed. */\n    AMOTION_EVENT_ACTION_BUTTON_PRESS = 11,\n\n    /* One or more buttons have been released. */\n    AMOTION_EVENT_ACTION_BUTTON_RELEASE = 12,\n};\n\n/**\n * Motion event flags.\n */\nenum {\n    /**\n     * This flag indicates that the window that received this motion event is partly\n     * or wholly obscured by another visible window above it.  This flag is set to true\n     * even if the event did not directly pass through the obscured area.\n     * A security sensitive application can check this flag to identify situations in which\n     * a malicious application may have covered up part of its content for the purpose\n     * of misleading the user or hijacking touches.  An appropriate response might be\n     * to drop the suspect touches or to take additional precautions to confirm the user's\n     * actual intent.\n     */\n    AMOTION_EVENT_FLAG_WINDOW_IS_OBSCURED = 0x1,\n};\n\n/**\n * Motion event edge touch flags.\n */\nenum {\n    /** No edges intersected. */\n    AMOTION_EVENT_EDGE_FLAG_NONE = 0,\n\n    /** Flag indicating the motion event intersected the top edge of the screen. */\n    AMOTION_EVENT_EDGE_FLAG_TOP = 0x01,\n\n    /** Flag indicating the motion event intersected the bottom edge of the screen. */\n    AMOTION_EVENT_EDGE_FLAG_BOTTOM = 0x02,\n\n    /** Flag indicating the motion event intersected the left edge of the screen. */\n    AMOTION_EVENT_EDGE_FLAG_LEFT = 0x04,\n\n    /** Flag indicating the motion event intersected the right edge of the screen. */\n    AMOTION_EVENT_EDGE_FLAG_RIGHT = 0x08\n};\n\n/**\n * Constants that identify each individual axis of a motion event.\n * @anchor AMOTION_EVENT_AXIS\n */\nenum {\n    /**\n     * Axis constant: X axis of a motion event.\n     *\n     * - For a touch screen, reports the absolute X screen position of the center of\n     * the touch contact area.  The units are display pixels.\n     * - For a touch pad, reports the absolute X surface position of the center of the touch\n     * contact area. The units are device-dependent.\n     * - For a mouse, reports the absolute X screen position of the mouse pointer.\n     * The units are display pixels.\n     * - For a trackball, reports the relative horizontal displacement of the trackball.\n     * The value is normalized to a range from -1.0 (left) to 1.0 (right).\n     * - For a joystick, reports the absolute X position of the joystick.\n     * The value is normalized to a range from -1.0 (left) to 1.0 (right).\n     */\n    AMOTION_EVENT_AXIS_X = 0,\n    /**\n     * Axis constant: Y axis of a motion event.\n     *\n     * - For a touch screen, reports the absolute Y screen position of the center of\n     * the touch contact area.  The units are display pixels.\n     * - For a touch pad, reports the absolute Y surface position of the center of the touch\n     * contact area. The units are device-dependent.\n     * - For a mouse, reports the absolute Y screen position of the mouse pointer.\n     * The units are display pixels.\n     * - For a trackball, reports the relative vertical displacement of the trackball.\n     * The value is normalized to a range from -1.0 (up) to 1.0 (down).\n     * - For a joystick, reports the absolute Y position of the joystick.\n     * The value is normalized to a range from -1.0 (up or far) to 1.0 (down or near).\n     */\n    AMOTION_EVENT_AXIS_Y = 1,\n    /**\n     * Axis constant: Pressure axis of a motion event.\n     *\n     * - For a touch screen or touch pad, reports the approximate pressure applied to the surface\n     * by a finger or other tool.  The value is normalized to a range from\n     * 0 (no pressure at all) to 1 (normal pressure), although values higher than 1\n     * may be generated depending on the calibration of the input device.\n     * - For a trackball, the value is set to 1 if the trackball button is pressed\n     * or 0 otherwise.\n     * - For a mouse, the value is set to 1 if the primary mouse button is pressed\n     * or 0 otherwise.\n     */\n    AMOTION_EVENT_AXIS_PRESSURE = 2,\n    /**\n     * Axis constant: Size axis of a motion event.\n     *\n     * - For a touch screen or touch pad, reports the approximate size of the contact area in\n     * relation to the maximum detectable size for the device.  The value is normalized\n     * to a range from 0 (smallest detectable size) to 1 (largest detectable size),\n     * although it is not a linear scale. This value is of limited use.\n     * To obtain calibrated size information, see\n     * {@link AMOTION_EVENT_AXIS_TOUCH_MAJOR} or {@link AMOTION_EVENT_AXIS_TOOL_MAJOR}.\n     */\n    AMOTION_EVENT_AXIS_SIZE = 3,\n    /**\n     * Axis constant: TouchMajor axis of a motion event.\n     *\n     * - For a touch screen, reports the length of the major axis of an ellipse that\n     * represents the touch area at the point of contact.\n     * The units are display pixels.\n     * - For a touch pad, reports the length of the major axis of an ellipse that\n     * represents the touch area at the point of contact.\n     * The units are device-dependent.\n     */\n    AMOTION_EVENT_AXIS_TOUCH_MAJOR = 4,\n    /**\n     * Axis constant: TouchMinor axis of a motion event.\n     *\n     * - For a touch screen, reports the length of the minor axis of an ellipse that\n     * represents the touch area at the point of contact.\n     * The units are display pixels.\n     * - For a touch pad, reports the length of the minor axis of an ellipse that\n     * represents the touch area at the point of contact.\n     * The units are device-dependent.\n     *\n     * When the touch is circular, the major and minor axis lengths will be equal to one another.\n     */\n    AMOTION_EVENT_AXIS_TOUCH_MINOR = 5,\n    /**\n     * Axis constant: ToolMajor axis of a motion event.\n     *\n     * - For a touch screen, reports the length of the major axis of an ellipse that\n     * represents the size of the approaching finger or tool used to make contact.\n     * - For a touch pad, reports the length of the major axis of an ellipse that\n     * represents the size of the approaching finger or tool used to make contact.\n     * The units are device-dependent.\n     *\n     * When the touch is circular, the major and minor axis lengths will be equal to one another.\n     *\n     * The tool size may be larger than the touch size since the tool may not be fully\n     * in contact with the touch sensor.\n     */\n    AMOTION_EVENT_AXIS_TOOL_MAJOR = 6,\n    /**\n     * Axis constant: ToolMinor axis of a motion event.\n     *\n     * - For a touch screen, reports the length of the minor axis of an ellipse that\n     * represents the size of the approaching finger or tool used to make contact.\n     * - For a touch pad, reports the length of the minor axis of an ellipse that\n     * represents the size of the approaching finger or tool used to make contact.\n     * The units are device-dependent.\n     *\n     * When the touch is circular, the major and minor axis lengths will be equal to one another.\n     *\n     * The tool size may be larger than the touch size since the tool may not be fully\n     * in contact with the touch sensor.\n     */\n    AMOTION_EVENT_AXIS_TOOL_MINOR = 7,\n    /**\n     * Axis constant: Orientation axis of a motion event.\n     *\n     * - For a touch screen or touch pad, reports the orientation of the finger\n     * or tool in radians relative to the vertical plane of the device.\n     * An angle of 0 radians indicates that the major axis of contact is oriented\n     * upwards, is perfectly circular or is of unknown orientation.  A positive angle\n     * indicates that the major axis of contact is oriented to the right.  A negative angle\n     * indicates that the major axis of contact is oriented to the left.\n     * The full range is from -PI/2 radians (finger pointing fully left) to PI/2 radians\n     * (finger pointing fully right).\n     * - For a stylus, the orientation indicates the direction in which the stylus\n     * is pointing in relation to the vertical axis of the current orientation of the screen.\n     * The range is from -PI radians to PI radians, where 0 is pointing up,\n     * -PI/2 radians is pointing left, -PI or PI radians is pointing down, and PI/2 radians\n     * is pointing right.  See also {@link AMOTION_EVENT_AXIS_TILT}.\n     */\n    AMOTION_EVENT_AXIS_ORIENTATION = 8,\n    /**\n     * Axis constant: Vertical Scroll axis of a motion event.\n     *\n     * - For a mouse, reports the relative movement of the vertical scroll wheel.\n     * The value is normalized to a range from -1.0 (down) to 1.0 (up).\n     *\n     * This axis should be used to scroll views vertically.\n     */\n    AMOTION_EVENT_AXIS_VSCROLL = 9,\n    /**\n     * Axis constant: Horizontal Scroll axis of a motion event.\n     *\n     * - For a mouse, reports the relative movement of the horizontal scroll wheel.\n     * The value is normalized to a range from -1.0 (left) to 1.0 (right).\n     *\n     * This axis should be used to scroll views horizontally.\n     */\n    AMOTION_EVENT_AXIS_HSCROLL = 10,\n    /**\n     * Axis constant: Z axis of a motion event.\n     *\n     * - For a joystick, reports the absolute Z position of the joystick.\n     * The value is normalized to a range from -1.0 (high) to 1.0 (low).\n     * <em>On game pads with two analog joysticks, this axis is often reinterpreted\n     * to report the absolute X position of the second joystick instead.</em>\n     */\n    AMOTION_EVENT_AXIS_Z = 11,\n    /**\n     * Axis constant: X Rotation axis of a motion event.\n     *\n     * - For a joystick, reports the absolute rotation angle about the X axis.\n     * The value is normalized to a range from -1.0 (counter-clockwise) to 1.0 (clockwise).\n     */\n    AMOTION_EVENT_AXIS_RX = 12,\n    /**\n     * Axis constant: Y Rotation axis of a motion event.\n     *\n     * - For a joystick, reports the absolute rotation angle about the Y axis.\n     * The value is normalized to a range from -1.0 (counter-clockwise) to 1.0 (clockwise).\n     */\n    AMOTION_EVENT_AXIS_RY = 13,\n    /**\n     * Axis constant: Z Rotation axis of a motion event.\n     *\n     * - For a joystick, reports the absolute rotation angle about the Z axis.\n     * The value is normalized to a range from -1.0 (counter-clockwise) to 1.0 (clockwise).\n     * On game pads with two analog joysticks, this axis is often reinterpreted\n     * to report the absolute Y position of the second joystick instead.\n     */\n    AMOTION_EVENT_AXIS_RZ = 14,\n    /**\n     * Axis constant: Hat X axis of a motion event.\n     *\n     * - For a joystick, reports the absolute X position of the directional hat control.\n     * The value is normalized to a range from -1.0 (left) to 1.0 (right).\n     */\n    AMOTION_EVENT_AXIS_HAT_X = 15,\n    /**\n     * Axis constant: Hat Y axis of a motion event.\n     *\n     * - For a joystick, reports the absolute Y position of the directional hat control.\n     * The value is normalized to a range from -1.0 (up) to 1.0 (down).\n     */\n    AMOTION_EVENT_AXIS_HAT_Y = 16,\n    /**\n     * Axis constant: Left Trigger axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the left trigger control.\n     * The value is normalized to a range from 0.0 (released) to 1.0 (fully pressed).\n     */\n    AMOTION_EVENT_AXIS_LTRIGGER = 17,\n    /**\n     * Axis constant: Right Trigger axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the right trigger control.\n     * The value is normalized to a range from 0.0 (released) to 1.0 (fully pressed).\n     */\n    AMOTION_EVENT_AXIS_RTRIGGER = 18,\n    /**\n     * Axis constant: Throttle axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the throttle control.\n     * The value is normalized to a range from 0.0 (fully open) to 1.0 (fully closed).\n     */\n    AMOTION_EVENT_AXIS_THROTTLE = 19,\n    /**\n     * Axis constant: Rudder axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the rudder control.\n     * The value is normalized to a range from -1.0 (turn left) to 1.0 (turn right).\n     */\n    AMOTION_EVENT_AXIS_RUDDER = 20,\n    /**\n     * Axis constant: Wheel axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the steering wheel control.\n     * The value is normalized to a range from -1.0 (turn left) to 1.0 (turn right).\n     */\n    AMOTION_EVENT_AXIS_WHEEL = 21,\n    /**\n     * Axis constant: Gas axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the gas (accelerator) control.\n     * The value is normalized to a range from 0.0 (no acceleration)\n     * to 1.0 (maximum acceleration).\n     */\n    AMOTION_EVENT_AXIS_GAS = 22,\n    /**\n     * Axis constant: Brake axis of a motion event.\n     *\n     * - For a joystick, reports the absolute position of the brake control.\n     * The value is normalized to a range from 0.0 (no braking) to 1.0 (maximum braking).\n     */\n    AMOTION_EVENT_AXIS_BRAKE = 23,\n    /**\n     * Axis constant: Distance axis of a motion event.\n     *\n     * - For a stylus, reports the distance of the stylus from the screen.\n     * A value of 0.0 indicates direct contact and larger values indicate increasing\n     * distance from the surface.\n     */\n    AMOTION_EVENT_AXIS_DISTANCE = 24,\n    /**\n     * Axis constant: Tilt axis of a motion event.\n     *\n     * - For a stylus, reports the tilt angle of the stylus in radians where\n     * 0 radians indicates that the stylus is being held perpendicular to the\n     * surface, and PI/2 radians indicates that the stylus is being held flat\n     * against the surface.\n     */\n    AMOTION_EVENT_AXIS_TILT = 25,\n    /**\n     * Axis constant: Generic 1 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_1 = 32,\n    /**\n     * Axis constant: Generic 2 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_2 = 33,\n    /**\n     * Axis constant: Generic 3 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_3 = 34,\n    /**\n     * Axis constant: Generic 4 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_4 = 35,\n    /**\n     * Axis constant: Generic 5 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_5 = 36,\n    /**\n     * Axis constant: Generic 6 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_6 = 37,\n    /**\n     * Axis constant: Generic 7 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_7 = 38,\n    /**\n     * Axis constant: Generic 8 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_8 = 39,\n    /**\n     * Axis constant: Generic 9 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_9 = 40,\n    /**\n     * Axis constant: Generic 10 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_10 = 41,\n    /**\n     * Axis constant: Generic 11 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_11 = 42,\n    /**\n     * Axis constant: Generic 12 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_12 = 43,\n    /**\n     * Axis constant: Generic 13 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_13 = 44,\n    /**\n     * Axis constant: Generic 14 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_14 = 45,\n    /**\n     * Axis constant: Generic 15 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_15 = 46,\n    /**\n     * Axis constant: Generic 16 axis of a motion event.\n     * The interpretation of a generic axis is device-specific.\n     */\n    AMOTION_EVENT_AXIS_GENERIC_16 = 47,\n\n    // NOTE: If you add a new axis here you must also add it to several other files.\n    //       Refer to frameworks/base/core/java/android/view/MotionEvent.java for the full list.\n};\n\n/**\n * Constants that identify buttons that are associated with motion events.\n * Refer to the documentation on the MotionEvent class for descriptions of each button.\n */\nenum {\n    /** primary */\n    AMOTION_EVENT_BUTTON_PRIMARY = 1 << 0,\n    /** secondary */\n    AMOTION_EVENT_BUTTON_SECONDARY = 1 << 1,\n    /** tertiary */\n    AMOTION_EVENT_BUTTON_TERTIARY = 1 << 2,\n    /** back */\n    AMOTION_EVENT_BUTTON_BACK = 1 << 3,\n    /** forward */\n    AMOTION_EVENT_BUTTON_FORWARD = 1 << 4,\n    AMOTION_EVENT_BUTTON_STYLUS_PRIMARY = 1 << 5,\n    AMOTION_EVENT_BUTTON_STYLUS_SECONDARY = 1 << 6,\n};\n\n/**\n * Constants that identify tool types.\n * Refer to the documentation on the MotionEvent class for descriptions of each tool type.\n */\nenum {\n    /** unknown */\n    AMOTION_EVENT_TOOL_TYPE_UNKNOWN = 0,\n    /** finger */\n    AMOTION_EVENT_TOOL_TYPE_FINGER = 1,\n    /** stylus */\n    AMOTION_EVENT_TOOL_TYPE_STYLUS = 2,\n    /** mouse */\n    AMOTION_EVENT_TOOL_TYPE_MOUSE = 3,\n    /** eraser */\n    AMOTION_EVENT_TOOL_TYPE_ERASER = 4,\n};\n\n/**\n * Input source masks.\n *\n * Refer to the documentation on android.view.InputDevice for more details about input sources\n * and their correct interpretation.\n */\nenum {\n    /** mask */\n    AINPUT_SOURCE_CLASS_MASK = 0x000000ff,\n\n    /** none */\n    AINPUT_SOURCE_CLASS_NONE = 0x00000000,\n    /** button */\n    AINPUT_SOURCE_CLASS_BUTTON = 0x00000001,\n    /** pointer */\n    AINPUT_SOURCE_CLASS_POINTER = 0x00000002,\n    /** navigation */\n    AINPUT_SOURCE_CLASS_NAVIGATION = 0x00000004,\n    /** position */\n    AINPUT_SOURCE_CLASS_POSITION = 0x00000008,\n    /** joystick */\n    AINPUT_SOURCE_CLASS_JOYSTICK = 0x00000010,\n};\n\n/**\n * Input sources.\n */\nenum {\n    /** unknown */\n    AINPUT_SOURCE_UNKNOWN = 0x00000000,\n\n    /** keyboard */\n    AINPUT_SOURCE_KEYBOARD = 0x00000100 | AINPUT_SOURCE_CLASS_BUTTON,\n    /** dpad */\n    AINPUT_SOURCE_DPAD = 0x00000200 | AINPUT_SOURCE_CLASS_BUTTON,\n    /** gamepad */\n    AINPUT_SOURCE_GAMEPAD = 0x00000400 | AINPUT_SOURCE_CLASS_BUTTON,\n    /** touchscreen */\n    AINPUT_SOURCE_TOUCHSCREEN = 0x00001000 | AINPUT_SOURCE_CLASS_POINTER,\n    /** mouse */\n    AINPUT_SOURCE_MOUSE = 0x00002000 | AINPUT_SOURCE_CLASS_POINTER,\n    /** stylus */\n    AINPUT_SOURCE_STYLUS = 0x00004000 | AINPUT_SOURCE_CLASS_POINTER,\n    /** bluetooth stylus */\n    AINPUT_SOURCE_BLUETOOTH_STYLUS = 0x00008000 | AINPUT_SOURCE_STYLUS,\n    /** trackball */\n    AINPUT_SOURCE_TRACKBALL = 0x00010000 | AINPUT_SOURCE_CLASS_NAVIGATION,\n    /** touchpad */\n    AINPUT_SOURCE_TOUCHPAD = 0x00100000 | AINPUT_SOURCE_CLASS_POSITION,\n    /** navigation */\n    AINPUT_SOURCE_TOUCH_NAVIGATION = 0x00200000 | AINPUT_SOURCE_CLASS_NONE,\n    /** gesture sensor (?) */\n    AINPUT_SOURCE_GESTURE_SENSOR = 0x00400000 | AINPUT_SOURCE_CLASS_NONE,\n    /** joystick */\n    AINPUT_SOURCE_JOYSTICK = 0x01000000 | AINPUT_SOURCE_CLASS_JOYSTICK,\n\n    /** any */\n    AINPUT_SOURCE_ANY = 0xffffff00,\n};\n\n/**\n * Keyboard types.\n *\n * Refer to the documentation on android.view.InputDevice for more details.\n */\nenum {\n    /** none */\n    AINPUT_KEYBOARD_TYPE_NONE = 0,\n    /** non alphabetic */\n    AINPUT_KEYBOARD_TYPE_NON_ALPHABETIC = 1,\n    /** alphabetic */\n    AINPUT_KEYBOARD_TYPE_ALPHABETIC = 2,\n};\n\n/**\n * Constants used to retrieve information about the range of motion for a particular\n * coordinate of a motion event.\n *\n * Refer to the documentation on android.view.InputDevice for more details about input sources\n * and their correct interpretation.\n *\n * @deprecated These constants are deprecated. Use {@link AMOTION_EVENT_AXIS AMOTION_EVENT_AXIS_*} constants instead.\n */\nenum {\n    /** x */\n    AINPUT_MOTION_RANGE_X = AMOTION_EVENT_AXIS_X,\n    /** y */\n    AINPUT_MOTION_RANGE_Y = AMOTION_EVENT_AXIS_Y,\n    /** pressure */\n    AINPUT_MOTION_RANGE_PRESSURE = AMOTION_EVENT_AXIS_PRESSURE,\n    /** size */\n    AINPUT_MOTION_RANGE_SIZE = AMOTION_EVENT_AXIS_SIZE,\n    /** touch major */\n    AINPUT_MOTION_RANGE_TOUCH_MAJOR = AMOTION_EVENT_AXIS_TOUCH_MAJOR,\n    /** touch minor */\n    AINPUT_MOTION_RANGE_TOUCH_MINOR = AMOTION_EVENT_AXIS_TOUCH_MINOR,\n    /** tool major */\n    AINPUT_MOTION_RANGE_TOOL_MAJOR = AMOTION_EVENT_AXIS_TOOL_MAJOR,\n    /** tool minor */\n    AINPUT_MOTION_RANGE_TOOL_MINOR = AMOTION_EVENT_AXIS_TOOL_MINOR,\n    /** orientation */\n    AINPUT_MOTION_RANGE_ORIENTATION = AMOTION_EVENT_AXIS_ORIENTATION,\n};\n\n\n/**\n * Input event accessors.\n *\n * Note that most functions can only be used on input events that are of a given type.\n * Calling these functions on input events of other types will yield undefined behavior.\n */\n\n/*** Accessors for all input events. ***/\n\n/** Get the input event type. */\nint32_t AInputEvent_getType(const AInputEvent* event);\n\n/** Get the id for the device that an input event came from.\n *\n * Input events can be generated by multiple different input devices.\n * Use the input device id to obtain information about the input\n * device that was responsible for generating a particular event.\n *\n * An input device id of 0 indicates that the event didn't come from a physical device;\n * other numbers are arbitrary and you shouldn't depend on the values.\n * Use the provided input device query API to obtain information about input devices.\n */\nint32_t AInputEvent_getDeviceId(const AInputEvent* event);\n\n/** Get the input event source. */\nint32_t AInputEvent_getSource(const AInputEvent* event);\n\n/*** Accessors for key events only. ***/\n\n/** Get the key event action. */\nint32_t AKeyEvent_getAction(const AInputEvent* key_event);\n\n/** Get the key event flags. */\nint32_t AKeyEvent_getFlags(const AInputEvent* key_event);\n\n/**\n * Get the key code of the key event.\n * This is the physical key that was pressed, not the Unicode character.\n */\nint32_t AKeyEvent_getKeyCode(const AInputEvent* key_event);\n\n/**\n * Get the hardware key id of this key event.\n * These values are not reliable and vary from device to device.\n */\nint32_t AKeyEvent_getScanCode(const AInputEvent* key_event);\n\n/** Get the meta key state. */\nint32_t AKeyEvent_getMetaState(const AInputEvent* key_event);\n\n/**\n * Get the repeat count of the event.\n * For both key up an key down events, this is the number of times the key has\n * repeated with the first down starting at 0 and counting up from there.  For\n * multiple key events, this is the number of down/up pairs that have occurred.\n */\nint32_t AKeyEvent_getRepeatCount(const AInputEvent* key_event);\n\n/**\n * Get the time of the most recent key down event, in the\n * java.lang.System.nanoTime() time base.  If this is a down event,\n * this will be the same as eventTime.\n * Note that when chording keys, this value is the down time of the most recently\n * pressed key, which may not be the same physical key of this event.\n */\nint64_t AKeyEvent_getDownTime(const AInputEvent* key_event);\n\n/**\n * Get the time this event occurred, in the\n * java.lang.System.nanoTime() time base.\n */\nint64_t AKeyEvent_getEventTime(const AInputEvent* key_event);\n\n/*** Accessors for motion events only. ***/\n\n/** Get the combined motion event action code and pointer index. */\nint32_t AMotionEvent_getAction(const AInputEvent* motion_event);\n\n/** Get the motion event flags. */\nint32_t AMotionEvent_getFlags(const AInputEvent* motion_event);\n\n/**\n * Get the state of any meta / modifier keys that were in effect when the\n * event was generated.\n */\nint32_t AMotionEvent_getMetaState(const AInputEvent* motion_event);\n\n/** Get the button state of all buttons that are pressed. */\nint32_t AMotionEvent_getButtonState(const AInputEvent* motion_event);\n\n/**\n * Get a bitfield indicating which edges, if any, were touched by this motion event.\n * For touch events, clients can use this to determine if the user's finger was\n * touching the edge of the display.\n */\nint32_t AMotionEvent_getEdgeFlags(const AInputEvent* motion_event);\n\n/**\n * Get the time when the user originally pressed down to start a stream of\n * position events, in the java.lang.System.nanoTime() time base.\n */\nint64_t AMotionEvent_getDownTime(const AInputEvent* motion_event);\n\n/**\n * Get the time when this specific event was generated,\n * in the java.lang.System.nanoTime() time base.\n */\nint64_t AMotionEvent_getEventTime(const AInputEvent* motion_event);\n\n/**\n * Get the X coordinate offset.\n * For touch events on the screen, this is the delta that was added to the raw\n * screen coordinates to adjust for the absolute position of the containing windows\n * and views.\n */\nfloat AMotionEvent_getXOffset(const AInputEvent* motion_event);\n\n/**\n * Get the Y coordinate offset.\n * For touch events on the screen, this is the delta that was added to the raw\n * screen coordinates to adjust for the absolute position of the containing windows\n * and views.\n */\nfloat AMotionEvent_getYOffset(const AInputEvent* motion_event);\n\n/**\n * Get the precision of the X coordinates being reported.\n * You can multiply this number with an X coordinate sample to find the\n * actual hardware value of the X coordinate.\n */\nfloat AMotionEvent_getXPrecision(const AInputEvent* motion_event);\n\n/**\n * Get the precision of the Y coordinates being reported.\n * You can multiply this number with a Y coordinate sample to find the\n * actual hardware value of the Y coordinate.\n */\nfloat AMotionEvent_getYPrecision(const AInputEvent* motion_event);\n\n/**\n * Get the number of pointers of data contained in this event.\n * Always >= 1.\n */\nsize_t AMotionEvent_getPointerCount(const AInputEvent* motion_event);\n\n/**\n * Get the pointer identifier associated with a particular pointer\n * data index in this event.  The identifier tells you the actual pointer\n * number associated with the data, accounting for individual pointers\n * going up and down since the start of the current gesture.\n */\nint32_t AMotionEvent_getPointerId(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the tool type of a pointer for the given pointer index.\n * The tool type indicates the type of tool used to make contact such as a\n * finger or stylus, if known.\n */\nint32_t AMotionEvent_getToolType(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the original raw X coordinate of this event.\n * For touch events on the screen, this is the original location of the event\n * on the screen, before it had been adjusted for the containing window\n * and views.\n */\nfloat AMotionEvent_getRawX(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the original raw X coordinate of this event.\n * For touch events on the screen, this is the original location of the event\n * on the screen, before it had been adjusted for the containing window\n * and views.\n */\nfloat AMotionEvent_getRawY(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current X coordinate of this event for the given pointer index.\n * Whole numbers are pixels; the value may have a fraction for input devices\n * that are sub-pixel precise.\n */\nfloat AMotionEvent_getX(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current Y coordinate of this event for the given pointer index.\n * Whole numbers are pixels; the value may have a fraction for input devices\n * that are sub-pixel precise.\n */\nfloat AMotionEvent_getY(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current pressure of this event for the given pointer index.\n * The pressure generally ranges from 0 (no pressure at all) to 1 (normal pressure),\n * although values higher than 1 may be generated depending on the calibration of\n * the input device.\n */\nfloat AMotionEvent_getPressure(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current scaled value of the approximate size for the given pointer index.\n * This represents some approximation of the area of the screen being\n * pressed; the actual value in pixels corresponding to the\n * touch is normalized with the device specific range of values\n * and scaled to a value between 0 and 1.  The value of size can be used to\n * determine fat touch events.\n */\nfloat AMotionEvent_getSize(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current length of the major axis of an ellipse that describes the touch area\n * at the point of contact for the given pointer index.\n */\nfloat AMotionEvent_getTouchMajor(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current length of the minor axis of an ellipse that describes the touch area\n * at the point of contact for the given pointer index.\n */\nfloat AMotionEvent_getTouchMinor(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current length of the major axis of an ellipse that describes the size\n * of the approaching tool for the given pointer index.\n * The tool area represents the estimated size of the finger or pen that is\n * touching the device independent of its actual touch area at the point of contact.\n */\nfloat AMotionEvent_getToolMajor(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current length of the minor axis of an ellipse that describes the size\n * of the approaching tool for the given pointer index.\n * The tool area represents the estimated size of the finger or pen that is\n * touching the device independent of its actual touch area at the point of contact.\n */\nfloat AMotionEvent_getToolMinor(const AInputEvent* motion_event, size_t pointer_index);\n\n/**\n * Get the current orientation of the touch area and tool area in radians clockwise from\n * vertical for the given pointer index.\n * An angle of 0 degrees indicates that the major axis of contact is oriented\n * upwards, is perfectly circular or is of unknown orientation.  A positive angle\n * indicates that the major axis of contact is oriented to the right.  A negative angle\n * indicates that the major axis of contact is oriented to the left.\n * The full range is from -PI/2 radians (finger pointing fully left) to PI/2 radians\n * (finger pointing fully right).\n */\nfloat AMotionEvent_getOrientation(const AInputEvent* motion_event, size_t pointer_index);\n\n/** Get the value of the request axis for the given pointer index. */\nfloat AMotionEvent_getAxisValue(const AInputEvent* motion_event,\n        int32_t axis, size_t pointer_index);\n\n/**\n * Get the number of historical points in this event.  These are movements that\n * have occurred between this event and the previous event.  This only applies\n * to AMOTION_EVENT_ACTION_MOVE events -- all other actions will have a size of 0.\n * Historical samples are indexed from oldest to newest.\n */\nsize_t AMotionEvent_getHistorySize(const AInputEvent* motion_event);\n\n/**\n * Get the time that a historical movement occurred between this event and\n * the previous event, in the java.lang.System.nanoTime() time base.\n */\nint64_t AMotionEvent_getHistoricalEventTime(const AInputEvent* motion_event,\n        size_t history_index);\n\n/**\n * Get the historical raw X coordinate of this event for the given pointer index that\n * occurred between this event and the previous motion event.\n * For touch events on the screen, this is the original location of the event\n * on the screen, before it had been adjusted for the containing window\n * and views.\n * Whole numbers are pixels; the value may have a fraction for input devices\n * that are sub-pixel precise.\n */\nfloat AMotionEvent_getHistoricalRawX(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical raw Y coordinate of this event for the given pointer index that\n * occurred between this event and the previous motion event.\n * For touch events on the screen, this is the original location of the event\n * on the screen, before it had been adjusted for the containing window\n * and views.\n * Whole numbers are pixels; the value may have a fraction for input devices\n * that are sub-pixel precise.\n */\nfloat AMotionEvent_getHistoricalRawY(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical X coordinate of this event for the given pointer index that\n * occurred between this event and the previous motion event.\n * Whole numbers are pixels; the value may have a fraction for input devices\n * that are sub-pixel precise.\n */\nfloat AMotionEvent_getHistoricalX(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical Y coordinate of this event for the given pointer index that\n * occurred between this event and the previous motion event.\n * Whole numbers are pixels; the value may have a fraction for input devices\n * that are sub-pixel precise.\n */\nfloat AMotionEvent_getHistoricalY(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical pressure of this event for the given pointer index that\n * occurred between this event and the previous motion event.\n * The pressure generally ranges from 0 (no pressure at all) to 1 (normal pressure),\n * although values higher than 1 may be generated depending on the calibration of\n * the input device.\n */\nfloat AMotionEvent_getHistoricalPressure(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the current scaled value of the approximate size for the given pointer index that\n * occurred between this event and the previous motion event.\n * This represents some approximation of the area of the screen being\n * pressed; the actual value in pixels corresponding to the\n * touch is normalized with the device specific range of values\n * and scaled to a value between 0 and 1.  The value of size can be used to\n * determine fat touch events.\n */\nfloat AMotionEvent_getHistoricalSize(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical length of the major axis of an ellipse that describes the touch area\n * at the point of contact for the given pointer index that\n * occurred between this event and the previous motion event.\n */\nfloat AMotionEvent_getHistoricalTouchMajor(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical length of the minor axis of an ellipse that describes the touch area\n * at the point of contact for the given pointer index that\n * occurred between this event and the previous motion event.\n */\nfloat AMotionEvent_getHistoricalTouchMinor(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical length of the major axis of an ellipse that describes the size\n * of the approaching tool for the given pointer index that\n * occurred between this event and the previous motion event.\n * The tool area represents the estimated size of the finger or pen that is\n * touching the device independent of its actual touch area at the point of contact.\n */\nfloat AMotionEvent_getHistoricalToolMajor(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical length of the minor axis of an ellipse that describes the size\n * of the approaching tool for the given pointer index that\n * occurred between this event and the previous motion event.\n * The tool area represents the estimated size of the finger or pen that is\n * touching the device independent of its actual touch area at the point of contact.\n */\nfloat AMotionEvent_getHistoricalToolMinor(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical orientation of the touch area and tool area in radians clockwise from\n * vertical for the given pointer index that\n * occurred between this event and the previous motion event.\n * An angle of 0 degrees indicates that the major axis of contact is oriented\n * upwards, is perfectly circular or is of unknown orientation.  A positive angle\n * indicates that the major axis of contact is oriented to the right.  A negative angle\n * indicates that the major axis of contact is oriented to the left.\n * The full range is from -PI/2 radians (finger pointing fully left) to PI/2 radians\n * (finger pointing fully right).\n */\nfloat AMotionEvent_getHistoricalOrientation(const AInputEvent* motion_event, size_t pointer_index,\n        size_t history_index);\n\n/**\n * Get the historical value of the request axis for the given pointer index\n * that occurred between this event and the previous motion event.\n */\nfloat AMotionEvent_getHistoricalAxisValue(const AInputEvent* motion_event,\n        int32_t axis, size_t pointer_index, size_t history_index);\n\n\nstruct AInputQueue;\n/**\n * Input queue\n *\n * An input queue is the facility through which you retrieve input\n * events.\n */\ntypedef struct AInputQueue AInputQueue;\n\n/**\n * Add this input queue to a looper for processing.  See\n * ALooper_addFd() for information on the ident, callback, and data params.\n */\nvoid AInputQueue_attachLooper(AInputQueue* queue, ALooper* looper,\n        int ident, ALooper_callbackFunc callback, void* data);\n\n/**\n * Remove the input queue from the looper it is currently attached to.\n */\nvoid AInputQueue_detachLooper(AInputQueue* queue);\n\n/**\n * Returns true if there are one or more events available in the\n * input queue.  Returns 1 if the queue has events; 0 if\n * it does not have events; and a negative value if there is an error.\n */\nint32_t AInputQueue_hasEvents(AInputQueue* queue);\n\n/**\n * Returns the next available event from the queue.  Returns a negative\n * value if no events are available or an error has occurred.\n */\nint32_t AInputQueue_getEvent(AInputQueue* queue, AInputEvent** outEvent);\n\n/**\n * Sends the key for standard pre-dispatching -- that is, possibly deliver\n * it to the current IME to be consumed before the app.  Returns 0 if it\n * was not pre-dispatched, meaning you can process it right now.  If non-zero\n * is returned, you must abandon the current event processing and allow the\n * event to appear again in the event queue (if it does not get consumed during\n * pre-dispatching).\n */\nint32_t AInputQueue_preDispatchEvent(AInputQueue* queue, AInputEvent* event);\n\n/**\n * Report that dispatching has finished with the given event.\n * This must be called after receiving an event with AInputQueue_get_event().\n */\nvoid AInputQueue_finishEvent(AInputQueue* queue, AInputEvent* event, int handled);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // _ANDROID_INPUT_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/keycodes.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Input\n * @{\n */\n\n/**\n * @file keycodes.h\n */\n\n#ifndef _ANDROID_KEYCODES_H\n#define _ANDROID_KEYCODES_H\n\n/******************************************************************\n *\n * IMPORTANT NOTICE:\n *\n *   This file is part of Android's set of stable system headers\n *   exposed by the Android NDK (Native Development Kit).\n *\n *   Third-party source AND binary code relies on the definitions\n *   here to be FROZEN ON ALL UPCOMING PLATFORM RELEASES.\n *\n *   - DO NOT MODIFY ENUMS (EXCEPT IF YOU ADD NEW 32-BIT VALUES)\n *   - DO NOT MODIFY CONSTANTS OR FUNCTIONAL MACROS\n *   - DO NOT CHANGE THE SIGNATURE OF FUNCTIONS IN ANY WAY\n *   - DO NOT CHANGE THE LAYOUT OR SIZE OF STRUCTURES\n */\n\n#include <sys/types.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Key codes.\n */\nenum {\n    /** Unknown key code. */\n    AKEYCODE_UNKNOWN         = 0,\n    /** Soft Left key.\n     * Usually situated below the display on phones and used as a multi-function\n     * feature key for selecting a software defined function shown on the bottom left\n     * of the display. */\n    AKEYCODE_SOFT_LEFT       = 1,\n    /** Soft Right key.\n     * Usually situated below the display on phones and used as a multi-function\n     * feature key for selecting a software defined function shown on the bottom right\n     * of the display. */\n    AKEYCODE_SOFT_RIGHT      = 2,\n    /** Home key.\n     * This key is handled by the framework and is never delivered to applications. */\n    AKEYCODE_HOME            = 3,\n    /** Back key. */\n    AKEYCODE_BACK            = 4,\n    /** Call key. */\n    AKEYCODE_CALL            = 5,\n    /** End Call key. */\n    AKEYCODE_ENDCALL         = 6,\n    /** '0' key. */\n    AKEYCODE_0               = 7,\n    /** '1' key. */\n    AKEYCODE_1               = 8,\n    /** '2' key. */\n    AKEYCODE_2               = 9,\n    /** '3' key. */\n    AKEYCODE_3               = 10,\n    /** '4' key. */\n    AKEYCODE_4               = 11,\n    /** '5' key. */\n    AKEYCODE_5               = 12,\n    /** '6' key. */\n    AKEYCODE_6               = 13,\n    /** '7' key. */\n    AKEYCODE_7               = 14,\n    /** '8' key. */\n    AKEYCODE_8               = 15,\n    /** '9' key. */\n    AKEYCODE_9               = 16,\n    /** '*' key. */\n    AKEYCODE_STAR            = 17,\n    /** '#' key. */\n    AKEYCODE_POUND           = 18,\n    /** Directional Pad Up key.\n     * May also be synthesized from trackball motions. */\n    AKEYCODE_DPAD_UP         = 19,\n    /** Directional Pad Down key.\n     * May also be synthesized from trackball motions. */\n    AKEYCODE_DPAD_DOWN       = 20,\n    /** Directional Pad Left key.\n     * May also be synthesized from trackball motions. */\n    AKEYCODE_DPAD_LEFT       = 21,\n    /** Directional Pad Right key.\n     * May also be synthesized from trackball motions. */\n    AKEYCODE_DPAD_RIGHT      = 22,\n    /** Directional Pad Center key.\n     * May also be synthesized from trackball motions. */\n    AKEYCODE_DPAD_CENTER     = 23,\n    /** Volume Up key.\n     * Adjusts the speaker volume up. */\n    AKEYCODE_VOLUME_UP       = 24,\n    /** Volume Down key.\n     * Adjusts the speaker volume down. */\n    AKEYCODE_VOLUME_DOWN     = 25,\n    /** Power key. */\n    AKEYCODE_POWER           = 26,\n    /** Camera key.\n     * Used to launch a camera application or take pictures. */\n    AKEYCODE_CAMERA          = 27,\n    /** Clear key. */\n    AKEYCODE_CLEAR           = 28,\n    /** 'A' key. */\n    AKEYCODE_A               = 29,\n    /** 'B' key. */\n    AKEYCODE_B               = 30,\n    /** 'C' key. */\n    AKEYCODE_C               = 31,\n    /** 'D' key. */\n    AKEYCODE_D               = 32,\n    /** 'E' key. */\n    AKEYCODE_E               = 33,\n    /** 'F' key. */\n    AKEYCODE_F               = 34,\n    /** 'G' key. */\n    AKEYCODE_G               = 35,\n    /** 'H' key. */\n    AKEYCODE_H               = 36,\n    /** 'I' key. */\n    AKEYCODE_I               = 37,\n    /** 'J' key. */\n    AKEYCODE_J               = 38,\n    /** 'K' key. */\n    AKEYCODE_K               = 39,\n    /** 'L' key. */\n    AKEYCODE_L               = 40,\n    /** 'M' key. */\n    AKEYCODE_M               = 41,\n    /** 'N' key. */\n    AKEYCODE_N               = 42,\n    /** 'O' key. */\n    AKEYCODE_O               = 43,\n    /** 'P' key. */\n    AKEYCODE_P               = 44,\n    /** 'Q' key. */\n    AKEYCODE_Q               = 45,\n    /** 'R' key. */\n    AKEYCODE_R               = 46,\n    /** 'S' key. */\n    AKEYCODE_S               = 47,\n    /** 'T' key. */\n    AKEYCODE_T               = 48,\n    /** 'U' key. */\n    AKEYCODE_U               = 49,\n    /** 'V' key. */\n    AKEYCODE_V               = 50,\n    /** 'W' key. */\n    AKEYCODE_W               = 51,\n    /** 'X' key. */\n    AKEYCODE_X               = 52,\n    /** 'Y' key. */\n    AKEYCODE_Y               = 53,\n    /** 'Z' key. */\n    AKEYCODE_Z               = 54,\n    /** ',' key. */\n    AKEYCODE_COMMA           = 55,\n    /** '.' key. */\n    AKEYCODE_PERIOD          = 56,\n    /** Left Alt modifier key. */\n    AKEYCODE_ALT_LEFT        = 57,\n    /** Right Alt modifier key. */\n    AKEYCODE_ALT_RIGHT       = 58,\n    /** Left Shift modifier key. */\n    AKEYCODE_SHIFT_LEFT      = 59,\n    /** Right Shift modifier key. */\n    AKEYCODE_SHIFT_RIGHT     = 60,\n    /** Tab key. */\n    AKEYCODE_TAB             = 61,\n    /** Space key. */\n    AKEYCODE_SPACE           = 62,\n    /** Symbol modifier key.\n     * Used to enter alternate symbols. */\n    AKEYCODE_SYM             = 63,\n    /** Explorer special function key.\n     * Used to launch a browser application. */\n    AKEYCODE_EXPLORER        = 64,\n    /** Envelope special function key.\n     * Used to launch a mail application. */\n    AKEYCODE_ENVELOPE        = 65,\n    /** Enter key. */\n    AKEYCODE_ENTER           = 66,\n    /** Backspace key.\n     * Deletes characters before the insertion point, unlike {@link AKEYCODE_FORWARD_DEL}. */\n    AKEYCODE_DEL             = 67,\n    /** '`' (backtick) key. */\n    AKEYCODE_GRAVE           = 68,\n    /** '-'. */\n    AKEYCODE_MINUS           = 69,\n    /** '=' key. */\n    AKEYCODE_EQUALS          = 70,\n    /** '[' key. */\n    AKEYCODE_LEFT_BRACKET    = 71,\n    /** ']' key. */\n    AKEYCODE_RIGHT_BRACKET   = 72,\n    /** '\\' key. */\n    AKEYCODE_BACKSLASH       = 73,\n    /** ';' key. */\n    AKEYCODE_SEMICOLON       = 74,\n    /** ''' (apostrophe) key. */\n    AKEYCODE_APOSTROPHE      = 75,\n    /** '/' key. */\n    AKEYCODE_SLASH           = 76,\n    /** '@' key. */\n    AKEYCODE_AT              = 77,\n    /** Number modifier key.\n     * Used to enter numeric symbols.\n     * This key is not {@link AKEYCODE_NUM_LOCK}; it is more like {@link AKEYCODE_ALT_LEFT}. */\n    AKEYCODE_NUM             = 78,\n    /** Headset Hook key.\n     * Used to hang up calls and stop media. */\n    AKEYCODE_HEADSETHOOK     = 79,\n    /** Camera Focus key.\n     * Used to focus the camera. */\n    AKEYCODE_FOCUS           = 80,\n    /** '+' key. */\n    AKEYCODE_PLUS            = 81,\n    /** Menu key. */\n    AKEYCODE_MENU            = 82,\n    /** Notification key. */\n    AKEYCODE_NOTIFICATION    = 83,\n    /** Search key. */\n    AKEYCODE_SEARCH          = 84,\n    /** Play/Pause media key. */\n    AKEYCODE_MEDIA_PLAY_PAUSE= 85,\n    /** Stop media key. */\n    AKEYCODE_MEDIA_STOP      = 86,\n    /** Play Next media key. */\n    AKEYCODE_MEDIA_NEXT      = 87,\n    /** Play Previous media key. */\n    AKEYCODE_MEDIA_PREVIOUS  = 88,\n    /** Rewind media key. */\n    AKEYCODE_MEDIA_REWIND    = 89,\n    /** Fast Forward media key. */\n    AKEYCODE_MEDIA_FAST_FORWARD = 90,\n    /** Mute key.\n     * Mutes the microphone, unlike {@link AKEYCODE_VOLUME_MUTE}. */\n    AKEYCODE_MUTE            = 91,\n    /** Page Up key. */\n    AKEYCODE_PAGE_UP         = 92,\n    /** Page Down key. */\n    AKEYCODE_PAGE_DOWN       = 93,\n    /** Picture Symbols modifier key.\n     * Used to switch symbol sets (Emoji, Kao-moji). */\n    AKEYCODE_PICTSYMBOLS     = 94,\n    /** Switch Charset modifier key.\n     * Used to switch character sets (Kanji, Katakana). */\n    AKEYCODE_SWITCH_CHARSET  = 95,\n    /** A Button key.\n     * On a game controller, the A button should be either the button labeled A\n     * or the first button on the bottom row of controller buttons. */\n    AKEYCODE_BUTTON_A        = 96,\n    /** B Button key.\n     * On a game controller, the B button should be either the button labeled B\n     * or the second button on the bottom row of controller buttons. */\n    AKEYCODE_BUTTON_B        = 97,\n    /** C Button key.\n     * On a game controller, the C button should be either the button labeled C\n     * or the third button on the bottom row of controller buttons. */\n    AKEYCODE_BUTTON_C        = 98,\n    /** X Button key.\n     * On a game controller, the X button should be either the button labeled X\n     * or the first button on the upper row of controller buttons. */\n    AKEYCODE_BUTTON_X        = 99,\n    /** Y Button key.\n     * On a game controller, the Y button should be either the button labeled Y\n     * or the second button on the upper row of controller buttons. */\n    AKEYCODE_BUTTON_Y        = 100,\n    /** Z Button key.\n     * On a game controller, the Z button should be either the button labeled Z\n     * or the third button on the upper row of controller buttons. */\n    AKEYCODE_BUTTON_Z        = 101,\n    /** L1 Button key.\n     * On a game controller, the L1 button should be either the button labeled L1 (or L)\n     * or the top left trigger button. */\n    AKEYCODE_BUTTON_L1       = 102,\n    /** R1 Button key.\n     * On a game controller, the R1 button should be either the button labeled R1 (or R)\n     * or the top right trigger button. */\n    AKEYCODE_BUTTON_R1       = 103,\n    /** L2 Button key.\n     * On a game controller, the L2 button should be either the button labeled L2\n     * or the bottom left trigger button. */\n    AKEYCODE_BUTTON_L2       = 104,\n    /** R2 Button key.\n     * On a game controller, the R2 button should be either the button labeled R2\n     * or the bottom right trigger button. */\n    AKEYCODE_BUTTON_R2       = 105,\n    /** Left Thumb Button key.\n     * On a game controller, the left thumb button indicates that the left (or only)\n     * joystick is pressed. */\n    AKEYCODE_BUTTON_THUMBL   = 106,\n    /** Right Thumb Button key.\n     * On a game controller, the right thumb button indicates that the right\n     * joystick is pressed. */\n    AKEYCODE_BUTTON_THUMBR   = 107,\n    /** Start Button key.\n     * On a game controller, the button labeled Start. */\n    AKEYCODE_BUTTON_START    = 108,\n    /** Select Button key.\n     * On a game controller, the button labeled Select. */\n    AKEYCODE_BUTTON_SELECT   = 109,\n    /** Mode Button key.\n     * On a game controller, the button labeled Mode. */\n    AKEYCODE_BUTTON_MODE     = 110,\n    /** Escape key. */\n    AKEYCODE_ESCAPE          = 111,\n    /** Forward Delete key.\n     * Deletes characters ahead of the insertion point, unlike {@link AKEYCODE_DEL}. */\n    AKEYCODE_FORWARD_DEL     = 112,\n    /** Left Control modifier key. */\n    AKEYCODE_CTRL_LEFT       = 113,\n    /** Right Control modifier key. */\n    AKEYCODE_CTRL_RIGHT      = 114,\n    /** Caps Lock key. */\n    AKEYCODE_CAPS_LOCK       = 115,\n    /** Scroll Lock key. */\n    AKEYCODE_SCROLL_LOCK     = 116,\n    /** Left Meta modifier key. */\n    AKEYCODE_META_LEFT       = 117,\n    /** Right Meta modifier key. */\n    AKEYCODE_META_RIGHT      = 118,\n    /** Function modifier key. */\n    AKEYCODE_FUNCTION        = 119,\n    /** System Request / Print Screen key. */\n    AKEYCODE_SYSRQ           = 120,\n    /** Break / Pause key. */\n    AKEYCODE_BREAK           = 121,\n    /** Home Movement key.\n     * Used for scrolling or moving the cursor around to the start of a line\n     * or to the top of a list. */\n    AKEYCODE_MOVE_HOME       = 122,\n    /** End Movement key.\n     * Used for scrolling or moving the cursor around to the end of a line\n     * or to the bottom of a list. */\n    AKEYCODE_MOVE_END        = 123,\n    /** Insert key.\n     * Toggles insert / overwrite edit mode. */\n    AKEYCODE_INSERT          = 124,\n    /** Forward key.\n     * Navigates forward in the history stack.  Complement of {@link AKEYCODE_BACK}. */\n    AKEYCODE_FORWARD         = 125,\n    /** Play media key. */\n    AKEYCODE_MEDIA_PLAY      = 126,\n    /** Pause media key. */\n    AKEYCODE_MEDIA_PAUSE     = 127,\n    /** Close media key.\n     * May be used to close a CD tray, for example. */\n    AKEYCODE_MEDIA_CLOSE     = 128,\n    /** Eject media key.\n     * May be used to eject a CD tray, for example. */\n    AKEYCODE_MEDIA_EJECT     = 129,\n    /** Record media key. */\n    AKEYCODE_MEDIA_RECORD    = 130,\n    /** F1 key. */\n    AKEYCODE_F1              = 131,\n    /** F2 key. */\n    AKEYCODE_F2              = 132,\n    /** F3 key. */\n    AKEYCODE_F3              = 133,\n    /** F4 key. */\n    AKEYCODE_F4              = 134,\n    /** F5 key. */\n    AKEYCODE_F5              = 135,\n    /** F6 key. */\n    AKEYCODE_F6              = 136,\n    /** F7 key. */\n    AKEYCODE_F7              = 137,\n    /** F8 key. */\n    AKEYCODE_F8              = 138,\n    /** F9 key. */\n    AKEYCODE_F9              = 139,\n    /** F10 key. */\n    AKEYCODE_F10             = 140,\n    /** F11 key. */\n    AKEYCODE_F11             = 141,\n    /** F12 key. */\n    AKEYCODE_F12             = 142,\n    /** Num Lock key.\n     * This is the Num Lock key; it is different from {@link AKEYCODE_NUM}.\n     * This key alters the behavior of other keys on the numeric keypad. */\n    AKEYCODE_NUM_LOCK        = 143,\n    /** Numeric keypad '0' key. */\n    AKEYCODE_NUMPAD_0        = 144,\n    /** Numeric keypad '1' key. */\n    AKEYCODE_NUMPAD_1        = 145,\n    /** Numeric keypad '2' key. */\n    AKEYCODE_NUMPAD_2        = 146,\n    /** Numeric keypad '3' key. */\n    AKEYCODE_NUMPAD_3        = 147,\n    /** Numeric keypad '4' key. */\n    AKEYCODE_NUMPAD_4        = 148,\n    /** Numeric keypad '5' key. */\n    AKEYCODE_NUMPAD_5        = 149,\n    /** Numeric keypad '6' key. */\n    AKEYCODE_NUMPAD_6        = 150,\n    /** Numeric keypad '7' key. */\n    AKEYCODE_NUMPAD_7        = 151,\n    /** Numeric keypad '8' key. */\n    AKEYCODE_NUMPAD_8        = 152,\n    /** Numeric keypad '9' key. */\n    AKEYCODE_NUMPAD_9        = 153,\n    /** Numeric keypad '/' key (for division). */\n    AKEYCODE_NUMPAD_DIVIDE   = 154,\n    /** Numeric keypad '*' key (for multiplication). */\n    AKEYCODE_NUMPAD_MULTIPLY = 155,\n    /** Numeric keypad '-' key (for subtraction). */\n    AKEYCODE_NUMPAD_SUBTRACT = 156,\n    /** Numeric keypad '+' key (for addition). */\n    AKEYCODE_NUMPAD_ADD      = 157,\n    /** Numeric keypad '.' key (for decimals or digit grouping). */\n    AKEYCODE_NUMPAD_DOT      = 158,\n    /** Numeric keypad ',' key (for decimals or digit grouping). */\n    AKEYCODE_NUMPAD_COMMA    = 159,\n    /** Numeric keypad Enter key. */\n    AKEYCODE_NUMPAD_ENTER    = 160,\n    /** Numeric keypad '=' key. */\n    AKEYCODE_NUMPAD_EQUALS   = 161,\n    /** Numeric keypad '(' key. */\n    AKEYCODE_NUMPAD_LEFT_PAREN = 162,\n    /** Numeric keypad ')' key. */\n    AKEYCODE_NUMPAD_RIGHT_PAREN = 163,\n    /** Volume Mute key.\n     * Mutes the speaker, unlike {@link AKEYCODE_MUTE}.\n     * This key should normally be implemented as a toggle such that the first press\n     * mutes the speaker and the second press restores the original volume. */\n    AKEYCODE_VOLUME_MUTE     = 164,\n    /** Info key.\n     * Common on TV remotes to show additional information related to what is\n     * currently being viewed. */\n    AKEYCODE_INFO            = 165,\n    /** Channel up key.\n     * On TV remotes, increments the television channel. */\n    AKEYCODE_CHANNEL_UP      = 166,\n    /** Channel down key.\n     * On TV remotes, decrements the television channel. */\n    AKEYCODE_CHANNEL_DOWN    = 167,\n    /** Zoom in key. */\n    AKEYCODE_ZOOM_IN         = 168,\n    /** Zoom out key. */\n    AKEYCODE_ZOOM_OUT        = 169,\n    /** TV key.\n     * On TV remotes, switches to viewing live TV. */\n    AKEYCODE_TV              = 170,\n    /** Window key.\n     * On TV remotes, toggles picture-in-picture mode or other windowing functions. */\n    AKEYCODE_WINDOW          = 171,\n    /** Guide key.\n     * On TV remotes, shows a programming guide. */\n    AKEYCODE_GUIDE           = 172,\n    /** DVR key.\n     * On some TV remotes, switches to a DVR mode for recorded shows. */\n    AKEYCODE_DVR             = 173,\n    /** Bookmark key.\n     * On some TV remotes, bookmarks content or web pages. */\n    AKEYCODE_BOOKMARK        = 174,\n    /** Toggle captions key.\n     * Switches the mode for closed-captioning text, for example during television shows. */\n    AKEYCODE_CAPTIONS        = 175,\n    /** Settings key.\n     * Starts the system settings activity. */\n    AKEYCODE_SETTINGS        = 176,\n    /** TV power key.\n     * On TV remotes, toggles the power on a television screen. */\n    AKEYCODE_TV_POWER        = 177,\n    /** TV input key.\n     * On TV remotes, switches the input on a television screen. */\n    AKEYCODE_TV_INPUT        = 178,\n    /** Set-top-box power key.\n     * On TV remotes, toggles the power on an external Set-top-box. */\n    AKEYCODE_STB_POWER       = 179,\n    /** Set-top-box input key.\n     * On TV remotes, switches the input mode on an external Set-top-box. */\n    AKEYCODE_STB_INPUT       = 180,\n    /** A/V Receiver power key.\n     * On TV remotes, toggles the power on an external A/V Receiver. */\n    AKEYCODE_AVR_POWER       = 181,\n    /** A/V Receiver input key.\n     * On TV remotes, switches the input mode on an external A/V Receiver. */\n    AKEYCODE_AVR_INPUT       = 182,\n    /** Red \"programmable\" key.\n     * On TV remotes, acts as a contextual/programmable key. */\n    AKEYCODE_PROG_RED        = 183,\n    /** Green \"programmable\" key.\n     * On TV remotes, actsas a contextual/programmable key. */\n    AKEYCODE_PROG_GREEN      = 184,\n    /** Yellow \"programmable\" key.\n     * On TV remotes, acts as a contextual/programmable key. */\n    AKEYCODE_PROG_YELLOW     = 185,\n    /** Blue \"programmable\" key.\n     * On TV remotes, acts as a contextual/programmable key. */\n    AKEYCODE_PROG_BLUE       = 186,\n    /** App switch key.\n     * Should bring up the application switcher dialog. */\n    AKEYCODE_APP_SWITCH      = 187,\n    /** Generic Game Pad Button #1.*/\n    AKEYCODE_BUTTON_1        = 188,\n    /** Generic Game Pad Button #2.*/\n    AKEYCODE_BUTTON_2        = 189,\n    /** Generic Game Pad Button #3.*/\n    AKEYCODE_BUTTON_3        = 190,\n    /** Generic Game Pad Button #4.*/\n    AKEYCODE_BUTTON_4        = 191,\n    /** Generic Game Pad Button #5.*/\n    AKEYCODE_BUTTON_5        = 192,\n    /** Generic Game Pad Button #6.*/\n    AKEYCODE_BUTTON_6        = 193,\n    /** Generic Game Pad Button #7.*/\n    AKEYCODE_BUTTON_7        = 194,\n    /** Generic Game Pad Button #8.*/\n    AKEYCODE_BUTTON_8        = 195,\n    /** Generic Game Pad Button #9.*/\n    AKEYCODE_BUTTON_9        = 196,\n    /** Generic Game Pad Button #10.*/\n    AKEYCODE_BUTTON_10       = 197,\n    /** Generic Game Pad Button #11.*/\n    AKEYCODE_BUTTON_11       = 198,\n    /** Generic Game Pad Button #12.*/\n    AKEYCODE_BUTTON_12       = 199,\n    /** Generic Game Pad Button #13.*/\n    AKEYCODE_BUTTON_13       = 200,\n    /** Generic Game Pad Button #14.*/\n    AKEYCODE_BUTTON_14       = 201,\n    /** Generic Game Pad Button #15.*/\n    AKEYCODE_BUTTON_15       = 202,\n    /** Generic Game Pad Button #16.*/\n    AKEYCODE_BUTTON_16       = 203,\n    /** Language Switch key.\n     * Toggles the current input language such as switching between English and Japanese on\n     * a QWERTY keyboard.  On some devices, the same function may be performed by\n     * pressing Shift+Spacebar. */\n    AKEYCODE_LANGUAGE_SWITCH = 204,\n    /** Manner Mode key.\n     * Toggles silent or vibrate mode on and off to make the device behave more politely\n     * in certain settings such as on a crowded train.  On some devices, the key may only\n     * operate when long-pressed. */\n    AKEYCODE_MANNER_MODE     = 205,\n    /** 3D Mode key.\n     * Toggles the display between 2D and 3D mode. */\n    AKEYCODE_3D_MODE         = 206,\n    /** Contacts special function key.\n     * Used to launch an address book application. */\n    AKEYCODE_CONTACTS        = 207,\n    /** Calendar special function key.\n     * Used to launch a calendar application. */\n    AKEYCODE_CALENDAR        = 208,\n    /** Music special function key.\n     * Used to launch a music player application. */\n    AKEYCODE_MUSIC           = 209,\n    /** Calculator special function key.\n     * Used to launch a calculator application. */\n    AKEYCODE_CALCULATOR      = 210,\n    /** Japanese full-width / half-width key. */\n    AKEYCODE_ZENKAKU_HANKAKU = 211,\n    /** Japanese alphanumeric key. */\n    AKEYCODE_EISU            = 212,\n    /** Japanese non-conversion key. */\n    AKEYCODE_MUHENKAN        = 213,\n    /** Japanese conversion key. */\n    AKEYCODE_HENKAN          = 214,\n    /** Japanese katakana / hiragana key. */\n    AKEYCODE_KATAKANA_HIRAGANA = 215,\n    /** Japanese Yen key. */\n    AKEYCODE_YEN             = 216,\n    /** Japanese Ro key. */\n    AKEYCODE_RO              = 217,\n    /** Japanese kana key. */\n    AKEYCODE_KANA            = 218,\n    /** Assist key.\n     * Launches the global assist activity.  Not delivered to applications. */\n    AKEYCODE_ASSIST          = 219,\n    /** Brightness Down key.\n     * Adjusts the screen brightness down. */\n    AKEYCODE_BRIGHTNESS_DOWN = 220,\n    /** Brightness Up key.\n     * Adjusts the screen brightness up. */\n    AKEYCODE_BRIGHTNESS_UP   = 221,\n    /** Audio Track key.\n     * Switches the audio tracks. */\n    AKEYCODE_MEDIA_AUDIO_TRACK = 222,\n    /** Sleep key.\n     * Puts the device to sleep.  Behaves somewhat like {@link AKEYCODE_POWER} but it\n     * has no effect if the device is already asleep. */\n    AKEYCODE_SLEEP           = 223,\n    /** Wakeup key.\n     * Wakes up the device.  Behaves somewhat like {@link AKEYCODE_POWER} but it\n     * has no effect if the device is already awake. */\n    AKEYCODE_WAKEUP          = 224,\n    /** Pairing key.\n     * Initiates peripheral pairing mode. Useful for pairing remote control\n     * devices or game controllers, especially if no other input mode is\n     * available. */\n    AKEYCODE_PAIRING         = 225,\n    /** Media Top Menu key.\n     * Goes to the top of media menu. */\n    AKEYCODE_MEDIA_TOP_MENU  = 226,\n    /** '11' key. */\n    AKEYCODE_11              = 227,\n    /** '12' key. */\n    AKEYCODE_12              = 228,\n    /** Last Channel key.\n     * Goes to the last viewed channel. */\n    AKEYCODE_LAST_CHANNEL    = 229,\n    /** TV data service key.\n     * Displays data services like weather, sports. */\n    AKEYCODE_TV_DATA_SERVICE = 230,\n    /** Voice Assist key.\n     * Launches the global voice assist activity. Not delivered to applications. */\n    AKEYCODE_VOICE_ASSIST    = 231,\n    /** Radio key.\n     * Toggles TV service / Radio service. */\n    AKEYCODE_TV_RADIO_SERVICE = 232,\n    /** Teletext key.\n     * Displays Teletext service. */\n    AKEYCODE_TV_TELETEXT     = 233,\n    /** Number entry key.\n     * Initiates to enter multi-digit channel nubmber when each digit key is assigned\n     * for selecting separate channel. Corresponds to Number Entry Mode (0x1D) of CEC\n     * User Control Code. */\n    AKEYCODE_TV_NUMBER_ENTRY = 234,\n    /** Analog Terrestrial key.\n     * Switches to analog terrestrial broadcast service. */\n    AKEYCODE_TV_TERRESTRIAL_ANALOG = 235,\n    /** Digital Terrestrial key.\n     * Switches to digital terrestrial broadcast service. */\n    AKEYCODE_TV_TERRESTRIAL_DIGITAL = 236,\n    /** Satellite key.\n     * Switches to digital satellite broadcast service. */\n    AKEYCODE_TV_SATELLITE    = 237,\n    /** BS key.\n     * Switches to BS digital satellite broadcasting service available in Japan. */\n    AKEYCODE_TV_SATELLITE_BS = 238,\n    /** CS key.\n     * Switches to CS digital satellite broadcasting service available in Japan. */\n    AKEYCODE_TV_SATELLITE_CS = 239,\n    /** BS/CS key.\n     * Toggles between BS and CS digital satellite services. */\n    AKEYCODE_TV_SATELLITE_SERVICE = 240,\n    /** Toggle Network key.\n     * Toggles selecting broacast services. */\n    AKEYCODE_TV_NETWORK      = 241,\n    /** Antenna/Cable key.\n     * Toggles broadcast input source between antenna and cable. */\n    AKEYCODE_TV_ANTENNA_CABLE = 242,\n    /** HDMI #1 key.\n     * Switches to HDMI input #1. */\n    AKEYCODE_TV_INPUT_HDMI_1 = 243,\n    /** HDMI #2 key.\n     * Switches to HDMI input #2. */\n    AKEYCODE_TV_INPUT_HDMI_2 = 244,\n    /** HDMI #3 key.\n     * Switches to HDMI input #3. */\n    AKEYCODE_TV_INPUT_HDMI_3 = 245,\n    /** HDMI #4 key.\n     * Switches to HDMI input #4. */\n    AKEYCODE_TV_INPUT_HDMI_4 = 246,\n    /** Composite #1 key.\n     * Switches to composite video input #1. */\n    AKEYCODE_TV_INPUT_COMPOSITE_1 = 247,\n    /** Composite #2 key.\n     * Switches to composite video input #2. */\n    AKEYCODE_TV_INPUT_COMPOSITE_2 = 248,\n    /** Component #1 key.\n     * Switches to component video input #1. */\n    AKEYCODE_TV_INPUT_COMPONENT_1 = 249,\n    /** Component #2 key.\n     * Switches to component video input #2. */\n    AKEYCODE_TV_INPUT_COMPONENT_2 = 250,\n    /** VGA #1 key.\n     * Switches to VGA (analog RGB) input #1. */\n    AKEYCODE_TV_INPUT_VGA_1  = 251,\n    /** Audio description key.\n     * Toggles audio description off / on. */\n    AKEYCODE_TV_AUDIO_DESCRIPTION = 252,\n    /** Audio description mixing volume up key.\n     * Louden audio description volume as compared with normal audio volume. */\n    AKEYCODE_TV_AUDIO_DESCRIPTION_MIX_UP = 253,\n    /** Audio description mixing volume down key.\n     * Lessen audio description volume as compared with normal audio volume. */\n    AKEYCODE_TV_AUDIO_DESCRIPTION_MIX_DOWN = 254,\n    /** Zoom mode key.\n     * Changes Zoom mode (Normal, Full, Zoom, Wide-zoom, etc.) */\n    AKEYCODE_TV_ZOOM_MODE    = 255,\n    /** Contents menu key.\n     * Goes to the title list. Corresponds to Contents Menu (0x0B) of CEC User Control\n     * Code */\n    AKEYCODE_TV_CONTENTS_MENU = 256,\n    /** Media context menu key.\n     * Goes to the context menu of media contents. Corresponds to Media Context-sensitive\n     * Menu (0x11) of CEC User Control Code. */\n    AKEYCODE_TV_MEDIA_CONTEXT_MENU = 257,\n    /** Timer programming key.\n     * Goes to the timer recording menu. Corresponds to Timer Programming (0x54) of\n     * CEC User Control Code. */\n    AKEYCODE_TV_TIMER_PROGRAMMING = 258,\n    /** Help key. */\n    AKEYCODE_HELP            = 259,\n    AKEYCODE_NAVIGATE_PREVIOUS = 260,\n    AKEYCODE_NAVIGATE_NEXT   = 261,\n    AKEYCODE_NAVIGATE_IN     = 262,\n    AKEYCODE_NAVIGATE_OUT    = 263,\n    /** Primary stem key for Wear\n     * Main power/reset button on watch. */\n    AKEYCODE_STEM_PRIMARY = 264,\n    /** Generic stem key 1 for Wear */\n    AKEYCODE_STEM_1 = 265,\n    /** Generic stem key 2 for Wear */\n    AKEYCODE_STEM_2 = 266,\n    /** Generic stem key 3 for Wear */\n    AKEYCODE_STEM_3 = 267,\n    AKEYCODE_MEDIA_SKIP_FORWARD = 272,\n    AKEYCODE_MEDIA_SKIP_BACKWARD = 273,\n    AKEYCODE_MEDIA_STEP_FORWARD = 274,\n    AKEYCODE_MEDIA_STEP_BACKWARD = 275,\n    /** Put device to sleep unless a wakelock is held. */\n    AKEYCODE_SOFT_SLEEP = 276\n\n    // NOTE: If you add a new keycode here you must also add it to several other files.\n    //       Refer to frameworks/base/core/java/android/view/KeyEvent.java for the full list.\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // _ANDROID_KEYCODES_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/looper.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Looper\n * @{\n */\n\n/**\n * @file looper.h\n */\n\n#ifndef ANDROID_LOOPER_H\n#define ANDROID_LOOPER_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct ALooper;\n/**\n * ALooper\n *\n * A looper is the state tracking an event loop for a thread.\n * Loopers do not define event structures or other such things; rather\n * they are a lower-level facility to attach one or more discrete objects\n * listening for an event.  An \"event\" here is simply data available on\n * a file descriptor: each attached object has an associated file descriptor,\n * and waiting for \"events\" means (internally) polling on all of these file\n * descriptors until one or more of them have data available.\n *\n * A thread can have only one ALooper associated with it.\n */\ntypedef struct ALooper ALooper;\n\n/**\n * Returns the looper associated with the calling thread, or NULL if\n * there is not one.\n */\nALooper* ALooper_forThread();\n\n/** Option for for ALooper_prepare(). */\nenum {\n    /**\n     * This looper will accept calls to ALooper_addFd() that do not\n     * have a callback (that is provide NULL for the callback).  In\n     * this case the caller of ALooper_pollOnce() or ALooper_pollAll()\n     * MUST check the return from these functions to discover when\n     * data is available on such fds and process it.\n     */\n    ALOOPER_PREPARE_ALLOW_NON_CALLBACKS = 1<<0\n};\n\n/**\n * Prepares a looper associated with the calling thread, and returns it.\n * If the thread already has a looper, it is returned.  Otherwise, a new\n * one is created, associated with the thread, and returned.\n *\n * The opts may be ALOOPER_PREPARE_ALLOW_NON_CALLBACKS or 0.\n */\nALooper* ALooper_prepare(int opts);\n\n/** Result from ALooper_pollOnce() and ALooper_pollAll(). */\nenum {\n    /**\n     * The poll was awoken using wake() before the timeout expired\n     * and no callbacks were executed and no other file descriptors were ready.\n     */\n    ALOOPER_POLL_WAKE = -1,\n\n    /**\n     * Result from ALooper_pollOnce() and ALooper_pollAll():\n     * One or more callbacks were executed.\n     */\n    ALOOPER_POLL_CALLBACK = -2,\n\n    /**\n     * Result from ALooper_pollOnce() and ALooper_pollAll():\n     * The timeout expired.\n     */\n    ALOOPER_POLL_TIMEOUT = -3,\n\n    /**\n     * Result from ALooper_pollOnce() and ALooper_pollAll():\n     * An error occurred.\n     */\n    ALOOPER_POLL_ERROR = -4,\n};\n\n/**\n * Acquire a reference on the given ALooper object.  This prevents the object\n * from being deleted until the reference is removed.  This is only needed\n * to safely hand an ALooper from one thread to another.\n */\nvoid ALooper_acquire(ALooper* looper);\n\n/**\n * Remove a reference that was previously acquired with ALooper_acquire().\n */\nvoid ALooper_release(ALooper* looper);\n\n/**\n * Flags for file descriptor events that a looper can monitor.\n *\n * These flag bits can be combined to monitor multiple events at once.\n */\nenum {\n    /**\n     * The file descriptor is available for read operations.\n     */\n    ALOOPER_EVENT_INPUT = 1 << 0,\n\n    /**\n     * The file descriptor is available for write operations.\n     */\n    ALOOPER_EVENT_OUTPUT = 1 << 1,\n\n    /**\n     * The file descriptor has encountered an error condition.\n     *\n     * The looper always sends notifications about errors; it is not necessary\n     * to specify this event flag in the requested event set.\n     */\n    ALOOPER_EVENT_ERROR = 1 << 2,\n\n    /**\n     * The file descriptor was hung up.\n     * For example, indicates that the remote end of a pipe or socket was closed.\n     *\n     * The looper always sends notifications about hangups; it is not necessary\n     * to specify this event flag in the requested event set.\n     */\n    ALOOPER_EVENT_HANGUP = 1 << 3,\n\n    /**\n     * The file descriptor is invalid.\n     * For example, the file descriptor was closed prematurely.\n     *\n     * The looper always sends notifications about invalid file descriptors; it is not necessary\n     * to specify this event flag in the requested event set.\n     */\n    ALOOPER_EVENT_INVALID = 1 << 4,\n};\n\n/**\n * For callback-based event loops, this is the prototype of the function\n * that is called when a file descriptor event occurs.\n * It is given the file descriptor it is associated with,\n * a bitmask of the poll events that were triggered (typically ALOOPER_EVENT_INPUT),\n * and the data pointer that was originally supplied.\n *\n * Implementations should return 1 to continue receiving callbacks, or 0\n * to have this file descriptor and callback unregistered from the looper.\n */\ntypedef int (*ALooper_callbackFunc)(int fd, int events, void* data);\n\n/**\n * Waits for events to be available, with optional timeout in milliseconds.\n * Invokes callbacks for all file descriptors on which an event occurred.\n *\n * If the timeout is zero, returns immediately without blocking.\n * If the timeout is negative, waits indefinitely until an event appears.\n *\n * Returns ALOOPER_POLL_WAKE if the poll was awoken using wake() before\n * the timeout expired and no callbacks were invoked and no other file\n * descriptors were ready.\n *\n * Returns ALOOPER_POLL_CALLBACK if one or more callbacks were invoked.\n *\n * Returns ALOOPER_POLL_TIMEOUT if there was no data before the given\n * timeout expired.\n *\n * Returns ALOOPER_POLL_ERROR if an error occurred.\n *\n * Returns a value >= 0 containing an identifier (the same identifier\n * `ident` passed to ALooper_addFd()) if its file descriptor has data\n * and it has no callback function (requiring the caller here to\n * handle it).  In this (and only this) case outFd, outEvents and\n * outData will contain the poll events and data associated with the\n * fd, otherwise they will be set to NULL.\n *\n * This method does not return until it has finished invoking the appropriate callbacks\n * for all file descriptors that were signalled.\n */\nint ALooper_pollOnce(int timeoutMillis, int* outFd, int* outEvents, void** outData);\n\n/**\n * Like ALooper_pollOnce(), but performs all pending callbacks until all\n * data has been consumed or a file descriptor is available with no callback.\n * This function will never return ALOOPER_POLL_CALLBACK.\n */\nint ALooper_pollAll(int timeoutMillis, int* outFd, int* outEvents, void** outData);\n\n/**\n * Wakes the poll asynchronously.\n *\n * This method can be called on any thread.\n * This method returns immediately.\n */\nvoid ALooper_wake(ALooper* looper);\n\n/**\n * Adds a new file descriptor to be polled by the looper.\n * If the same file descriptor was previously added, it is replaced.\n *\n * \"fd\" is the file descriptor to be added.\n * \"ident\" is an identifier for this event, which is returned from ALooper_pollOnce().\n * The identifier must be >= 0, or ALOOPER_POLL_CALLBACK if providing a non-NULL callback.\n * \"events\" are the poll events to wake up on.  Typically this is ALOOPER_EVENT_INPUT.\n * \"callback\" is the function to call when there is an event on the file descriptor.\n * \"data\" is a private data pointer to supply to the callback.\n *\n * There are two main uses of this function:\n *\n * (1) If \"callback\" is non-NULL, then this function will be called when there is\n * data on the file descriptor.  It should execute any events it has pending,\n * appropriately reading from the file descriptor.  The 'ident' is ignored in this case.\n *\n * (2) If \"callback\" is NULL, the 'ident' will be returned by ALooper_pollOnce\n * when its file descriptor has data available, requiring the caller to take\n * care of processing it.\n *\n * Returns 1 if the file descriptor was added or -1 if an error occurred.\n *\n * This method can be called on any thread.\n * This method may block briefly if it needs to wake the poll.\n */\nint ALooper_addFd(ALooper* looper, int fd, int ident, int events,\n        ALooper_callbackFunc callback, void* data);\n\n/**\n * Removes a previously added file descriptor from the looper.\n *\n * When this method returns, it is safe to close the file descriptor since the looper\n * will no longer have a reference to it.  However, it is possible for the callback to\n * already be running or for it to run one last time if the file descriptor was already\n * signalled.  Calling code is responsible for ensuring that this case is safely handled.\n * For example, if the callback takes care of removing itself during its own execution either\n * by returning 0 or by calling this method, then it can be guaranteed to not be invoked\n * again at any later time unless registered anew.\n *\n * Returns 1 if the file descriptor was removed, 0 if none was previously registered\n * or -1 if an error occurred.\n *\n * This method can be called on any thread.\n * This method may block briefly if it needs to wake the poll.\n */\nint ALooper_removeFd(ALooper* looper, int fd);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_LOOPER_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/multinetwork.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_MULTINETWORK_H\n#define ANDROID_MULTINETWORK_H\n\n#include <netdb.h>\n#include <stdlib.h>\n#include <sys/cdefs.h>\n\n__BEGIN_DECLS\n\n/**\n * The corresponding C type for android.net.Network#getNetworkHandle() return\n * values.  The Java signed long value can be safely cast to a net_handle_t:\n *\n *     [C]    ((net_handle_t) java_long_network_handle)\n *     [C++]  static_cast<net_handle_t>(java_long_network_handle)\n *\n * as appropriate.\n */\ntypedef uint64_t net_handle_t;\n\n/**\n * The value NETWORK_UNSPECIFIED indicates no specific network.\n *\n * For some functions (documented below), a previous binding may be cleared\n * by an invocation with NETWORK_UNSPECIFIED.\n *\n * Depending on the context it may indicate an error.  It is expressly\n * not used to indicate some notion of the \"current default network\".\n */\n#define NETWORK_UNSPECIFIED  ((net_handle_t)0)\n\n\n/**\n * All functions below that return an int return 0 on success or -1\n * on failure with an appropriate errno value set.\n */\n\n\n/**\n * Set the network to be used by the given socket file descriptor.\n *\n * To clear a previous socket binding invoke with NETWORK_UNSPECIFIED.\n *\n * This is the equivalent of:\n *\n *     [ android.net.Network#bindSocket() ]\n *     https://developer.android.com/reference/android/net/Network.html#bindSocket(java.net.Socket)\n */\nint android_setsocknetwork(net_handle_t network, int fd);\n\n\n/**\n * Binds the current process to |network|.  All sockets created in the future\n * (and not explicitly bound via android_setsocknetwork()) will be bound to\n * |network|.  All host name resolutions will be limited to |network| as well.\n * Note that if the network identified by |network| ever disconnects, all\n * sockets created in this way will cease to work and all host name\n * resolutions will fail.  This is by design so an application doesn't\n * accidentally use sockets it thinks are still bound to a particular network.\n *\n * To clear a previous process binding invoke with NETWORK_UNSPECIFIED.\n *\n * This is the equivalent of:\n *\n *     [ android.net.ConnectivityManager#setProcessDefaultNetwork() ]\n *     https://developer.android.com/reference/android/net/ConnectivityManager.html#setProcessDefaultNetwork(android.net.Network)\n */\nint android_setprocnetwork(net_handle_t network);\n\n\n/**\n * Perform hostname resolution via the DNS servers associated with |network|.\n *\n * All arguments (apart from |network|) are used identically as those passed\n * to getaddrinfo(3).  Return and error values are identical to those of\n * getaddrinfo(3), and in particular gai_strerror(3) can be used as expected.\n * Similar to getaddrinfo(3):\n *     - |hints| may be NULL (in which case man page documented defaults apply)\n *     - either |node| or |service| may be NULL, but not both\n *     - |res| must not be NULL\n *\n * This is the equivalent of:\n *\n *     [ android.net.Network#getAllByName() ]\n *     https://developer.android.com/reference/android/net/Network.html#getAllByName(java.lang.String)\n */\nint android_getaddrinfofornetwork(net_handle_t network,\n        const char *node, const char *service,\n        const struct addrinfo *hints, struct addrinfo **res);\n\n__END_DECLS\n\n#endif  // ANDROID_MULTINETWORK_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/native_activity.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup NativeActivity Native Activity\n * @{\n */\n\n/**\n * @file native_activity.h\n */\n\n#ifndef ANDROID_NATIVE_ACTIVITY_H\n#define ANDROID_NATIVE_ACTIVITY_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <jni.h>\n\n#include <android/asset_manager.h>\n#include <android/input.h>\n#include <android/native_window.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * {@link ANativeActivityCallbacks}\n */\nstruct ANativeActivityCallbacks;\n\n/**\n * This structure defines the native side of an android.app.NativeActivity.\n * It is created by the framework, and handed to the application's native\n * code as it is being launched.\n */\ntypedef struct ANativeActivity {\n    /**\n     * Pointer to the callback function table of the native application.\n     * You can set the functions here to your own callbacks.  The callbacks\n     * pointer itself here should not be changed; it is allocated and managed\n     * for you by the framework.\n     */\n    struct ANativeActivityCallbacks* callbacks;\n\n    /**\n     * The global handle on the process's Java VM.\n     */\n    JavaVM* vm;\n\n    /**\n     * JNI context for the main thread of the app.  Note that this field\n     * can ONLY be used from the main thread of the process; that is, the\n     * thread that calls into the ANativeActivityCallbacks.\n     */\n    JNIEnv* env;\n\n    /**\n     * The NativeActivity object handle.\n     *\n     * IMPORTANT NOTE: This member is mis-named. It should really be named\n     * 'activity' instead of 'clazz', since it's a reference to the\n     * NativeActivity instance created by the system for you.\n     *\n     * We unfortunately cannot change this without breaking NDK\n     * source-compatibility.\n     */\n    jobject clazz;\n\n    /**\n     * Path to this application's internal data directory.\n     */\n    const char* internalDataPath;\n\n    /**\n     * Path to this application's external (removable/mountable) data directory.\n     */\n    const char* externalDataPath;\n\n    /**\n     * The platform's SDK version code.\n     */\n    int32_t sdkVersion;\n\n    /**\n     * This is the native instance of the application.  It is not used by\n     * the framework, but can be set by the application to its own instance\n     * state.\n     */\n    void* instance;\n\n    /**\n     * Pointer to the Asset Manager instance for the application.  The application\n     * uses this to access binary assets bundled inside its own .apk file.\n     */\n    AAssetManager* assetManager;\n\n    /**\n     * Available starting with Honeycomb: path to the directory containing\n     * the application's OBB files (if any).  If the app doesn't have any\n     * OBB files, this directory may not exist.\n     */\n    const char* obbPath;\n} ANativeActivity;\n\n/**\n * These are the callbacks the framework makes into a native application.\n * All of these callbacks happen on the main thread of the application.\n * By default, all callbacks are NULL; set to a pointer to your own function\n * to have it called.\n */\ntypedef struct ANativeActivityCallbacks {\n    /**\n     * NativeActivity has started.  See Java documentation for Activity.onStart()\n     * for more information.\n     */\n    void (*onStart)(ANativeActivity* activity);\n\n    /**\n     * NativeActivity has resumed.  See Java documentation for Activity.onResume()\n     * for more information.\n     */\n    void (*onResume)(ANativeActivity* activity);\n\n    /**\n     * Framework is asking NativeActivity to save its current instance state.\n     * See Java documentation for Activity.onSaveInstanceState() for more\n     * information.  The returned pointer needs to be created with malloc();\n     * the framework will call free() on it for you.  You also must fill in\n     * outSize with the number of bytes in the allocation.  Note that the\n     * saved state will be persisted, so it can not contain any active\n     * entities (pointers to memory, file descriptors, etc).\n     */\n    void* (*onSaveInstanceState)(ANativeActivity* activity, size_t* outSize);\n\n    /**\n     * NativeActivity has paused.  See Java documentation for Activity.onPause()\n     * for more information.\n     */\n    void (*onPause)(ANativeActivity* activity);\n\n    /**\n     * NativeActivity has stopped.  See Java documentation for Activity.onStop()\n     * for more information.\n     */\n    void (*onStop)(ANativeActivity* activity);\n\n    /**\n     * NativeActivity is being destroyed.  See Java documentation for Activity.onDestroy()\n     * for more information.\n     */\n    void (*onDestroy)(ANativeActivity* activity);\n\n    /**\n     * Focus has changed in this NativeActivity's window.  This is often used,\n     * for example, to pause a game when it loses input focus.\n     */\n    void (*onWindowFocusChanged)(ANativeActivity* activity, int hasFocus);\n\n    /**\n     * The drawing window for this native activity has been created.  You\n     * can use the given native window object to start drawing.\n     */\n    void (*onNativeWindowCreated)(ANativeActivity* activity, ANativeWindow* window);\n\n    /**\n     * The drawing window for this native activity has been resized.  You should\n     * retrieve the new size from the window and ensure that your rendering in\n     * it now matches.\n     */\n    void (*onNativeWindowResized)(ANativeActivity* activity, ANativeWindow* window);\n\n    /**\n     * The drawing window for this native activity needs to be redrawn.  To avoid\n     * transient artifacts during screen changes (such resizing after rotation),\n     * applications should not return from this function until they have finished\n     * drawing their window in its current state.\n     */\n    void (*onNativeWindowRedrawNeeded)(ANativeActivity* activity, ANativeWindow* window);\n\n    /**\n     * The drawing window for this native activity is going to be destroyed.\n     * You MUST ensure that you do not touch the window object after returning\n     * from this function: in the common case of drawing to the window from\n     * another thread, that means the implementation of this callback must\n     * properly synchronize with the other thread to stop its drawing before\n     * returning from here.\n     */\n    void (*onNativeWindowDestroyed)(ANativeActivity* activity, ANativeWindow* window);\n\n    /**\n     * The input queue for this native activity's window has been created.\n     * You can use the given input queue to start retrieving input events.\n     */\n    void (*onInputQueueCreated)(ANativeActivity* activity, AInputQueue* queue);\n\n    /**\n     * The input queue for this native activity's window is being destroyed.\n     * You should no longer try to reference this object upon returning from this\n     * function.\n     */\n    void (*onInputQueueDestroyed)(ANativeActivity* activity, AInputQueue* queue);\n\n    /**\n     * The rectangle in the window in which content should be placed has changed.\n     */\n    void (*onContentRectChanged)(ANativeActivity* activity, const ARect* rect);\n\n    /**\n     * The current device AConfiguration has changed.  The new configuration can\n     * be retrieved from assetManager.\n     */\n    void (*onConfigurationChanged)(ANativeActivity* activity);\n\n    /**\n     * The system is running low on memory.  Use this callback to release\n     * resources you do not need, to help the system avoid killing more\n     * important processes.\n     */\n    void (*onLowMemory)(ANativeActivity* activity);\n} ANativeActivityCallbacks;\n\n/**\n * This is the function that must be in the native code to instantiate the\n * application's native activity.  It is called with the activity instance (see\n * above); if the code is being instantiated from a previously saved instance,\n * the savedState will be non-NULL and point to the saved data.  You must make\n * any copy of this data you need -- it will be released after you return from\n * this function.\n */\ntypedef void ANativeActivity_createFunc(ANativeActivity* activity,\n        void* savedState, size_t savedStateSize);\n\n/**\n * The name of the function that NativeInstance looks for when launching its\n * native code.  This is the default function that is used, you can specify\n * \"android.app.func_name\" string meta-data in your manifest to use a different\n * function.\n */\nextern ANativeActivity_createFunc ANativeActivity_onCreate;\n\n/**\n * Finish the given activity.  Its finish() method will be called, causing it\n * to be stopped and destroyed.  Note that this method can be called from\n * *any* thread; it will send a message to the main thread of the process\n * where the Java finish call will take place.\n */\nvoid ANativeActivity_finish(ANativeActivity* activity);\n\n/**\n * Change the window format of the given activity.  Calls getWindow().setFormat()\n * of the given activity.  Note that this method can be called from\n * *any* thread; it will send a message to the main thread of the process\n * where the Java finish call will take place.\n */\nvoid ANativeActivity_setWindowFormat(ANativeActivity* activity, int32_t format);\n\n/**\n * Change the window flags of the given activity.  Calls getWindow().setFlags()\n * of the given activity.  Note that this method can be called from\n * *any* thread; it will send a message to the main thread of the process\n * where the Java finish call will take place.  See window.h for flag constants.\n */\nvoid ANativeActivity_setWindowFlags(ANativeActivity* activity,\n        uint32_t addFlags, uint32_t removeFlags);\n\n/**\n * Flags for ANativeActivity_showSoftInput; see the Java InputMethodManager\n * API for documentation.\n */\nenum {\n    /**\n     * Implicit request to show the input window, not as the result\n     * of a direct request by the user.\n     */\n    ANATIVEACTIVITY_SHOW_SOFT_INPUT_IMPLICIT = 0x0001,\n\n    /**\n     * The user has forced the input method open (such as by\n     * long-pressing menu) so it should not be closed until they\n     * explicitly do so.\n     */\n    ANATIVEACTIVITY_SHOW_SOFT_INPUT_FORCED = 0x0002,\n};\n\n/**\n * Show the IME while in the given activity.  Calls InputMethodManager.showSoftInput()\n * for the given activity.  Note that this method can be called from\n * *any* thread; it will send a message to the main thread of the process\n * where the Java finish call will take place.\n */\nvoid ANativeActivity_showSoftInput(ANativeActivity* activity, uint32_t flags);\n\n/**\n * Flags for ANativeActivity_hideSoftInput; see the Java InputMethodManager\n * API for documentation.\n */\nenum {\n    /**\n     * The soft input window should only be hidden if it was not\n     * explicitly shown by the user.\n     */\n    ANATIVEACTIVITY_HIDE_SOFT_INPUT_IMPLICIT_ONLY = 0x0001,\n    /**\n     * The soft input window should normally be hidden, unless it was\n     * originally shown with {@link ANATIVEACTIVITY_SHOW_SOFT_INPUT_FORCED}.\n     */\n    ANATIVEACTIVITY_HIDE_SOFT_INPUT_NOT_ALWAYS = 0x0002,\n};\n\n/**\n * Hide the IME while in the given activity.  Calls InputMethodManager.hideSoftInput()\n * for the given activity.  Note that this method can be called from\n * *any* thread; it will send a message to the main thread of the process\n * where the Java finish call will take place.\n */\nvoid ANativeActivity_hideSoftInput(ANativeActivity* activity, uint32_t flags);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_NATIVE_ACTIVITY_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/native_window.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup NativeActivity Native Activity\n * @{\n */\n\n/**\n * @file native_window.h\n */\n\n#ifndef ANDROID_NATIVE_WINDOW_H\n#define ANDROID_NATIVE_WINDOW_H\n\n#include <android/rect.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Pixel formats that a window can use.\n */\nenum {\n    /** Red: 8 bits, Green: 8 bits, Blue: 8 bits, Alpha: 8 bits. **/\n    WINDOW_FORMAT_RGBA_8888          = 1,\n    /** Red: 8 bits, Green: 8 bits, Blue: 8 bits, Unused: 8 bits. **/\n    WINDOW_FORMAT_RGBX_8888          = 2,\n    /** Red: 5 bits, Green: 6 bits, Blue: 5 bits. **/\n    WINDOW_FORMAT_RGB_565            = 4,\n};\n\nstruct ANativeWindow;\n/**\n * {@link ANativeWindow} is opaque type that provides access to a native window.\n *\n * A pointer can be obtained using ANativeWindow_fromSurface().\n */\ntypedef struct ANativeWindow ANativeWindow;\n\n/**\n * {@link ANativeWindow} is a struct that represents a windows buffer.\n *\n * A pointer can be obtained using ANativeWindow_lock().\n */\ntypedef struct ANativeWindow_Buffer {\n    // The number of pixels that are show horizontally.\n    int32_t width;\n\n    // The number of pixels that are shown vertically.\n    int32_t height;\n\n    // The number of *pixels* that a line in the buffer takes in\n    // memory.  This may be >= width.\n    int32_t stride;\n\n    // The format of the buffer.  One of WINDOW_FORMAT_*\n    int32_t format;\n\n    // The actual bits.\n    void* bits;\n\n    // Do not touch.\n    uint32_t reserved[6];\n} ANativeWindow_Buffer;\n\n/**\n * Acquire a reference on the given ANativeWindow object.  This prevents the object\n * from being deleted until the reference is removed.\n */\nvoid ANativeWindow_acquire(ANativeWindow* window);\n\n/**\n * Remove a reference that was previously acquired with ANativeWindow_acquire().\n */\nvoid ANativeWindow_release(ANativeWindow* window);\n\n/**\n * Return the current width in pixels of the window surface.  Returns a\n * negative value on error.\n */\nint32_t ANativeWindow_getWidth(ANativeWindow* window);\n\n/**\n * Return the current height in pixels of the window surface.  Returns a\n * negative value on error.\n */\nint32_t ANativeWindow_getHeight(ANativeWindow* window);\n\n/**\n * Return the current pixel format of the window surface.  Returns a\n * negative value on error.\n */\nint32_t ANativeWindow_getFormat(ANativeWindow* window);\n\n/**\n * Change the format and size of the window buffers.\n *\n * The width and height control the number of pixels in the buffers, not the\n * dimensions of the window on screen.  If these are different than the\n * window's physical size, then it buffer will be scaled to match that size\n * when compositing it to the screen.\n *\n * For all of these parameters, if 0 is supplied then the window's base\n * value will come back in force.\n *\n * width and height must be either both zero or both non-zero.\n *\n */\nint32_t ANativeWindow_setBuffersGeometry(ANativeWindow* window,\n        int32_t width, int32_t height, int32_t format);\n\n/**\n * Lock the window's next drawing surface for writing.\n * inOutDirtyBounds is used as an in/out parameter, upon entering the\n * function, it contains the dirty region, that is, the region the caller\n * intends to redraw. When the function returns, inOutDirtyBounds is updated\n * with the actual area the caller needs to redraw -- this region is often\n * extended by ANativeWindow_lock.\n */\nint32_t ANativeWindow_lock(ANativeWindow* window, ANativeWindow_Buffer* outBuffer,\n        ARect* inOutDirtyBounds);\n\n/**\n * Unlock the window's drawing surface after previously locking it,\n * posting the new buffer to the display.\n */\nint32_t ANativeWindow_unlockAndPost(ANativeWindow* window);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_NATIVE_WINDOW_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/native_window_jni.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup NativeActivity Native Activity\n * @{\n */\n\n/**\n * @file native_window_jni.h\n */\n\n#ifndef ANDROID_NATIVE_WINDOW_JNI_H\n#define ANDROID_NATIVE_WINDOW_JNI_H\n\n#include <android/native_window.h>\n\n#include <jni.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Return the ANativeWindow associated with a Java Surface object,\n * for interacting with it through native code.  This acquires a reference\n * on the ANativeWindow that is returned; be sure to use ANativeWindow_release()\n * when done with it so that it doesn't leak.\n */\nANativeWindow* ANativeWindow_fromSurface(JNIEnv* env, jobject surface);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_NATIVE_WINDOW_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/obb.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Storage\n * @{\n */\n\n/**\n * @file obb.h\n */\n\n#ifndef ANDROID_OBB_H\n#define ANDROID_OBB_H\n\n#include <sys/types.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct AObbInfo;\n/** {@link AObbInfo} is an opaque type representing information for obb storage. */\ntypedef struct AObbInfo AObbInfo;\n\n/** Flag for an obb file, returned by AObbInfo_getFlags(). */\nenum {\n    /** overlay */\n    AOBBINFO_OVERLAY = 0x0001,\n};\n\n/**\n * Scan an OBB and get information about it.\n */\nAObbInfo* AObbScanner_getObbInfo(const char* filename);\n\n/**\n * Destroy the AObbInfo object. You must call this when finished with the object.\n */\nvoid AObbInfo_delete(AObbInfo* obbInfo);\n\n/**\n * Get the package name for the OBB.\n */\nconst char* AObbInfo_getPackageName(AObbInfo* obbInfo);\n\n/**\n * Get the version of an OBB file.\n */\nint32_t AObbInfo_getVersion(AObbInfo* obbInfo);\n\n/**\n * Get the flags of an OBB file.\n */\nint32_t AObbInfo_getFlags(AObbInfo* obbInfo);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif      // ANDROID_OBB_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/rect.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup NativeActivity Native Activity\n * @{\n */\n\n/**\n * @file rect.h\n */\n\n#ifndef ANDROID_RECT_H\n#define ANDROID_RECT_H\n\n#include <stdint.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * {@link ARect} is a struct that represents a rectangular window area.\n *\n * It is used with {@link\n * ANativeActivityCallbacks::onContentRectChanged} event callback and\n * ANativeWindow_lock() function.\n */\ntypedef struct ARect {\n#ifdef __cplusplus\n    typedef int32_t value_type;\n#endif\n    /** left position */\n    int32_t left;\n    /** top position */\n    int32_t top;\n    /** left position */\n    int32_t right;\n    /** bottom position */\n    int32_t bottom;\n} ARect;\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_RECT_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/sensor.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Sensor\n * @{\n */\n\n/**\n * @file sensor.h\n */\n\n#ifndef ANDROID_SENSOR_H\n#define ANDROID_SENSOR_H\n\n/******************************************************************\n *\n * IMPORTANT NOTICE:\n *\n *   This file is part of Android's set of stable system headers\n *   exposed by the Android NDK (Native Development Kit).\n *\n *   Third-party source AND binary code relies on the definitions\n *   here to be FROZEN ON ALL UPCOMING PLATFORM RELEASES.\n *\n *   - DO NOT MODIFY ENUMS (EXCEPT IF YOU ADD NEW 32-BIT VALUES)\n *   - DO NOT MODIFY CONSTANTS OR FUNCTIONAL MACROS\n *   - DO NOT CHANGE THE SIGNATURE OF FUNCTIONS IN ANY WAY\n *   - DO NOT CHANGE THE LAYOUT OR SIZE OF STRUCTURES\n */\n\n/**\n * Structures and functions to receive and process sensor events in\n * native code.\n *\n */\n\n#include <sys/types.h>\n\n#include <android/looper.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/**\n * Sensor types.\n * (keep in sync with hardware/sensor.h)\n */\nenum {\n    /**\n     * {@link ASENSOR_TYPE_ACCELEROMETER}\n     * reporting-mode: continuous\n     *\n     *  All values are in SI units (m/s^2) and measure the acceleration of the\n     *  device minus the force of gravity.\n     */\n    ASENSOR_TYPE_ACCELEROMETER      = 1,\n    /**\n     * {@link ASENSOR_TYPE_MAGNETIC_FIELD}\n     * reporting-mode: continuous\n     *\n     *  All values are in micro-Tesla (uT) and measure the geomagnetic\n     *  field in the X, Y and Z axis.\n     */\n    ASENSOR_TYPE_MAGNETIC_FIELD     = 2,\n    /**\n     * {@link ASENSOR_TYPE_GYROSCOPE}\n     * reporting-mode: continuous\n     *\n     *  All values are in radians/second and measure the rate of rotation\n     *  around the X, Y and Z axis.\n     */\n    ASENSOR_TYPE_GYROSCOPE          = 4,\n    /**\n     * {@link ASENSOR_TYPE_LIGHT}\n     * reporting-mode: on-change\n     *\n     * The light sensor value is returned in SI lux units.\n     */\n    ASENSOR_TYPE_LIGHT              = 5,\n    /**\n     * {@link ASENSOR_TYPE_PROXIMITY}\n     * reporting-mode: on-change\n     *\n     * The proximity sensor which turns the screen off and back on during calls is the\n     * wake-up proximity sensor. Implement wake-up proximity sensor before implementing\n     * a non wake-up proximity sensor. For the wake-up proximity sensor set the flag\n     * SENSOR_FLAG_WAKE_UP.\n     * The value corresponds to the distance to the nearest object in centimeters.\n     */\n    ASENSOR_TYPE_PROXIMITY          = 8\n};\n\n/**\n * Sensor accuracy measure.\n */\nenum {\n    /** no contact */\n    ASENSOR_STATUS_NO_CONTACT       = -1,\n    /** unreliable */\n    ASENSOR_STATUS_UNRELIABLE       = 0,\n    /** low accuracy */\n    ASENSOR_STATUS_ACCURACY_LOW     = 1,\n    /** medium accuracy */\n    ASENSOR_STATUS_ACCURACY_MEDIUM  = 2,\n    /** high accuracy */\n    ASENSOR_STATUS_ACCURACY_HIGH    = 3\n};\n\n/**\n * Sensor Reporting Modes.\n */\nenum {\n    /** continuous reporting */\n    AREPORTING_MODE_CONTINUOUS = 0,\n    /** reporting on change */\n    AREPORTING_MODE_ON_CHANGE = 1,\n    /** on shot reporting */\n    AREPORTING_MODE_ONE_SHOT = 2,\n    /** special trigger reporting */\n    AREPORTING_MODE_SPECIAL_TRIGGER = 3\n};\n\n/*\n * A few useful constants\n */\n\n/** Earth's gravity in m/s^2 */\n#define ASENSOR_STANDARD_GRAVITY            (9.80665f)\n/** Maximum magnetic field on Earth's surface in uT */\n#define ASENSOR_MAGNETIC_FIELD_EARTH_MAX    (60.0f)\n/** Minimum magnetic field on Earth's surface in uT*/\n#define ASENSOR_MAGNETIC_FIELD_EARTH_MIN    (30.0f)\n\n/**\n * A sensor event.\n */\n\n/* NOTE: Must match hardware/sensors.h */\ntypedef struct ASensorVector {\n    union {\n        float v[3];\n        struct {\n            float x;\n            float y;\n            float z;\n        };\n        struct {\n            float azimuth;\n            float pitch;\n            float roll;\n        };\n    };\n    int8_t status;\n    uint8_t reserved[3];\n} ASensorVector;\n\ntypedef struct AMetaDataEvent {\n    int32_t what;\n    int32_t sensor;\n} AMetaDataEvent;\n\ntypedef struct AUncalibratedEvent {\n  union {\n    float uncalib[3];\n    struct {\n      float x_uncalib;\n      float y_uncalib;\n      float z_uncalib;\n    };\n  };\n  union {\n    float bias[3];\n    struct {\n      float x_bias;\n      float y_bias;\n      float z_bias;\n    };\n  };\n} AUncalibratedEvent;\n\ntypedef struct AHeartRateEvent {\n  float bpm;\n  int8_t status;\n} AHeartRateEvent;\n\n/* NOTE: Must match hardware/sensors.h */\ntypedef struct ASensorEvent {\n    int32_t version; /* sizeof(struct ASensorEvent) */\n    int32_t sensor;\n    int32_t type;\n    int32_t reserved0;\n    int64_t timestamp;\n    union {\n        union {\n            float           data[16];\n            ASensorVector   vector;\n            ASensorVector   acceleration;\n            ASensorVector   magnetic;\n            float           temperature;\n            float           distance;\n            float           light;\n            float           pressure;\n            float           relative_humidity;\n            AUncalibratedEvent uncalibrated_gyro;\n            AUncalibratedEvent uncalibrated_magnetic;\n            AMetaDataEvent meta_data;\n            AHeartRateEvent heart_rate;\n        };\n        union {\n            uint64_t        data[8];\n            uint64_t        step_counter;\n        } u64;\n    };\n\n    uint32_t flags;\n    int32_t reserved1[3];\n} ASensorEvent;\n\nstruct ASensorManager;\n/**\n * {@link ASensorManager} is an opaque type to manage sensors and\n * events queues.\n *\n * {@link ASensorManager} is a singleton that can be obtained using\n * ASensorManager_getInstance().\n *\n * This file provides a set of functions that uses {@link\n * ASensorManager} to access and list hardware sensors, and\n * create and destroy event queues:\n * - ASensorManager_getSensorList()\n * - ASensorManager_getDefaultSensor()\n * - ASensorManager_getDefaultSensorEx()\n * - ASensorManager_createEventQueue()\n * - ASensorManager_destroyEventQueue()\n */\ntypedef struct ASensorManager ASensorManager;\n\n\nstruct ASensorEventQueue;\n/**\n * {@link ASensorEventQueue} is an opaque type that provides access to\n * {@link ASensorEvent} from hardware sensors.\n *\n * A new {@link ASensorEventQueue} can be obtained using ASensorManager_createEventQueue().\n *\n * This file provides a set of functions to enable and disable\n * sensors, check and get events, and set event rates on a {@link\n * ASensorEventQueue}.\n * - ASensorEventQueue_enableSensor()\n * - ASensorEventQueue_disableSensor()\n * - ASensorEventQueue_hasEvents()\n * - ASensorEventQueue_getEvents()\n * - ASensorEventQueue_setEventRate()\n */\ntypedef struct ASensorEventQueue ASensorEventQueue;\n\nstruct ASensor;\n/**\n * {@link ASensor} is an opaque type that provides information about\n * an hardware sensors.\n *\n * A {@link ASensor} pointer can be obtained using\n * ASensorManager_getDefaultSensor(),\n * ASensorManager_getDefaultSensorEx() or from a {@link ASensorList}.\n *\n * This file provides a set of functions to access properties of a\n * {@link ASensor}:\n * - ASensor_getName()\n * - ASensor_getVendor()\n * - ASensor_getType()\n * - ASensor_getResolution()\n * - ASensor_getMinDelay()\n * - ASensor_getFifoMaxEventCount()\n * - ASensor_getFifoReservedEventCount()\n * - ASensor_getStringType()\n * - ASensor_getReportingMode()\n * - ASensor_isWakeUpSensor()\n */\ntypedef struct ASensor ASensor;\n/**\n * {@link ASensorRef} is a type for constant pointers to {@link ASensor}.\n *\n * This is used to define entry in {@link ASensorList} arrays.\n */\ntypedef ASensor const* ASensorRef;\n/**\n * {@link ASensorList} is an array of reference to {@link ASensor}.\n *\n * A {@link ASensorList} can be initialized using ASensorManager_getSensorList().\n */\ntypedef ASensorRef const* ASensorList;\n\n/*****************************************************************************/\n\n/**\n * Get a reference to the sensor manager. ASensorManager is a singleton\n * per package as different packages may have access to different sensors.\n *\n * Deprecated: Use ASensorManager_getInstanceForPackage(const char*) instead.\n *\n * Example:\n *\n *     ASensorManager* sensorManager = ASensorManager_getInstance();\n *\n */\n__attribute__ ((deprecated)) ASensorManager* ASensorManager_getInstance();\n\n/*\n * Get a reference to the sensor manager. ASensorManager is a singleton\n * per package as different packages may have access to different sensors.\n *\n * Example:\n *\n *    ASensorManager* sensorManager = ASensorManager_getInstanceForPackage(\"foo.bar.baz\");\n *\n */\nASensorManager* ASensorManager_getInstanceForPackage(const char* packageName);\n\n/**\n * Returns the list of available sensors.\n */\nint ASensorManager_getSensorList(ASensorManager* manager, ASensorList* list);\n\n/**\n * Returns the default sensor for the given type, or NULL if no sensor\n * of that type exists.\n */\nASensor const* ASensorManager_getDefaultSensor(ASensorManager* manager, int type);\n\n/**\n * Returns the default sensor with the given type and wakeUp properties or NULL if no sensor\n * of this type and wakeUp properties exists.\n */\nASensor const* ASensorManager_getDefaultSensorEx(ASensorManager* manager, int type,\n        bool wakeUp);\n\n/**\n * Creates a new sensor event queue and associate it with a looper.\n *\n * \"ident\" is a identifier for the events that will be returned when\n * calling ALooper_pollOnce(). The identifier must be >= 0, or\n * ALOOPER_POLL_CALLBACK if providing a non-NULL callback.\n */\nASensorEventQueue* ASensorManager_createEventQueue(ASensorManager* manager,\n        ALooper* looper, int ident, ALooper_callbackFunc callback, void* data);\n\n/**\n * Destroys the event queue and free all resources associated to it.\n */\nint ASensorManager_destroyEventQueue(ASensorManager* manager, ASensorEventQueue* queue);\n\n\n/*****************************************************************************/\n\n/**\n * Enable the selected sensor. Returns a negative error code on failure.\n */\nint ASensorEventQueue_enableSensor(ASensorEventQueue* queue, ASensor const* sensor);\n\n/**\n * Disable the selected sensor. Returns a negative error code on failure.\n */\nint ASensorEventQueue_disableSensor(ASensorEventQueue* queue, ASensor const* sensor);\n\n/**\n * Sets the delivery rate of events in microseconds for the given sensor.\n * Note that this is a hint only, generally event will arrive at a higher\n * rate. It is an error to set a rate inferior to the value returned by\n * ASensor_getMinDelay().\n * Returns a negative error code on failure.\n */\nint ASensorEventQueue_setEventRate(ASensorEventQueue* queue, ASensor const* sensor, int32_t usec);\n\n/**\n * Returns true if there are one or more events available in the\n * sensor queue.  Returns 1 if the queue has events; 0 if\n * it does not have events; and a negative value if there is an error.\n */\nint ASensorEventQueue_hasEvents(ASensorEventQueue* queue);\n\n/**\n * Returns the next available events from the queue.  Returns a negative\n * value if no events are available or an error has occurred, otherwise\n * the number of events returned.\n *\n * Examples:\n *   ASensorEvent event;\n *   ssize_t numEvent = ASensorEventQueue_getEvents(queue, &event, 1);\n *\n *   ASensorEvent eventBuffer[8];\n *   ssize_t numEvent = ASensorEventQueue_getEvents(queue, eventBuffer, 8);\n *\n */\nssize_t ASensorEventQueue_getEvents(ASensorEventQueue* queue,\n                ASensorEvent* events, size_t count);\n\n\n/*****************************************************************************/\n\n/**\n * Returns this sensor's name (non localized)\n */\nconst char* ASensor_getName(ASensor const* sensor);\n\n/**\n * Returns this sensor's vendor's name (non localized)\n */\nconst char* ASensor_getVendor(ASensor const* sensor);\n\n/**\n * Return this sensor's type\n */\nint ASensor_getType(ASensor const* sensor);\n\n/**\n * Returns this sensors's resolution\n */\nfloat ASensor_getResolution(ASensor const* sensor);\n\n/**\n * Returns the minimum delay allowed between events in microseconds.\n * A value of zero means that this sensor doesn't report events at a\n * constant rate, but rather only when a new data is available.\n */\nint ASensor_getMinDelay(ASensor const* sensor);\n\n/**\n * Returns the maximum size of batches for this sensor. Batches will often be\n * smaller, as the hardware fifo might be used for other sensors.\n */\nint ASensor_getFifoMaxEventCount(ASensor const* sensor);\n\n/**\n * Returns the hardware batch fifo size reserved to this sensor.\n */\nint ASensor_getFifoReservedEventCount(ASensor const* sensor);\n\n/**\n * Returns this sensor's string type.\n */\nconst char* ASensor_getStringType(ASensor const* sensor);\n\n/**\n * Returns the reporting mode for this sensor. One of AREPORTING_MODE_* constants.\n */\nint ASensor_getReportingMode(ASensor const* sensor);\n\n/**\n * Returns true if this is a wake up sensor, false otherwise.\n */\nbool ASensor_isWakeUpSensor(ASensor const* sensor);\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_SENSOR_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/storage_manager.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup Storage\n * @{\n */\n\n/**\n * @file storage_manager.h\n */\n\n#ifndef ANDROID_STORAGE_MANAGER_H\n#define ANDROID_STORAGE_MANAGER_H\n\n#include <stdint.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct AStorageManager;\n/**\n * {@link AStorageManager} manages application OBB storage, a pointer\n * can be obtained with AStorageManager_new().\n */\ntypedef struct AStorageManager AStorageManager;\n\n/**\n * The different states of a OBB storage passed to AStorageManager_obbCallbackFunc().\n */\nenum {\n    /**\n     * The OBB container is now mounted and ready for use. Can be returned\n     * as the status for callbacks made during asynchronous OBB actions.\n     */\n    AOBB_STATE_MOUNTED = 1,\n\n    /**\n     * The OBB container is now unmounted and not usable. Can be returned\n     * as the status for callbacks made during asynchronous OBB actions.\n     */\n    AOBB_STATE_UNMOUNTED = 2,\n\n    /**\n     * There was an internal system error encountered while trying to\n     * mount the OBB. Can be returned as the status for callbacks made\n     * during asynchronous OBB actions.\n     */\n    AOBB_STATE_ERROR_INTERNAL = 20,\n\n    /**\n     * The OBB could not be mounted by the system. Can be returned as the\n     * status for callbacks made during asynchronous OBB actions.\n     */\n    AOBB_STATE_ERROR_COULD_NOT_MOUNT = 21,\n\n    /**\n     * The OBB could not be unmounted. This most likely indicates that a\n     * file is in use on the OBB. Can be returned as the status for\n     * callbacks made during asynchronous OBB actions.\n     */\n    AOBB_STATE_ERROR_COULD_NOT_UNMOUNT = 22,\n\n    /**\n     * A call was made to unmount the OBB when it was not mounted. Can be\n     * returned as the status for callbacks made during asynchronous OBB\n     * actions.\n     */\n    AOBB_STATE_ERROR_NOT_MOUNTED = 23,\n\n    /**\n     * The OBB has already been mounted. Can be returned as the status for\n     * callbacks made during asynchronous OBB actions.\n     */\n    AOBB_STATE_ERROR_ALREADY_MOUNTED = 24,\n\n    /**\n     * The current application does not have permission to use this OBB.\n     * This could be because the OBB indicates it's owned by a different\n     * package. Can be returned as the status for callbacks made during\n     * asynchronous OBB actions.\n     */\n    AOBB_STATE_ERROR_PERMISSION_DENIED = 25,\n};\n\n/**\n * Obtains a new instance of AStorageManager.\n */\nAStorageManager* AStorageManager_new();\n\n/**\n * Release AStorageManager instance.\n */\nvoid AStorageManager_delete(AStorageManager* mgr);\n\n/**\n * Callback function for asynchronous calls made on OBB files.\n *\n * \"state\" is one of the following constants:\n * - {@link AOBB_STATE_MOUNTED}\n * - {@link AOBB_STATE_UNMOUNTED}\n * - {@link AOBB_STATE_ERROR_INTERNAL}\n * - {@link AOBB_STATE_ERROR_COULD_NOT_MOUNT}\n * - {@link AOBB_STATE_ERROR_COULD_NOT_UNMOUNT}\n * - {@link AOBB_STATE_ERROR_NOT_MOUNTED}\n * - {@link AOBB_STATE_ERROR_ALREADY_MOUNTED}\n * - {@link AOBB_STATE_ERROR_PERMISSION_DENIED}\n */\ntypedef void (*AStorageManager_obbCallbackFunc)(const char* filename, const int32_t state, void* data);\n\n/**\n * Attempts to mount an OBB file. This is an asynchronous operation.\n */\nvoid AStorageManager_mountObb(AStorageManager* mgr, const char* filename, const char* key,\n        AStorageManager_obbCallbackFunc cb, void* data);\n\n/**\n * Attempts to unmount an OBB file. This is an asynchronous operation.\n */\nvoid AStorageManager_unmountObb(AStorageManager* mgr, const char* filename, const int force,\n        AStorageManager_obbCallbackFunc cb, void* data);\n\n/**\n * Check whether an OBB is mounted.\n */\nint AStorageManager_isObbMounted(AStorageManager* mgr, const char* filename);\n\n/**\n * Get the mounted path for an OBB.\n */\nconst char* AStorageManager_getMountedObbPath(AStorageManager* mgr, const char* filename);\n\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif      // ANDROID_STORAGE_MANAGER_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/trace.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_NATIVE_TRACE_H\n#define ANDROID_NATIVE_TRACE_H\n\n#include <stdbool.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Returns true if tracing is enabled. Use this signal to avoid expensive computation only necessary\n * when tracing is enabled.\n */\nbool ATrace_isEnabled();\n\n/**\n * Writes a tracing message to indicate that the given section of code has begun. This call must be\n * followed by a corresponding call to endSection() on the same thread.\n *\n * Note: At this time the vertical bar character '|' and newline character '\\n' are used internally\n * by the tracing mechanism. If sectionName contains these characters they will be replaced with a\n * space character in the trace.\n */\nvoid ATrace_beginSection(const char* sectionName);\n\n/**\n * Writes a tracing message to indicate that a given section of code has ended. This call must be\n * preceeded by a corresponding call to beginSection(char*) on the same thread. Calling this method\n * will mark the end of the most recently begun section of code, so care must be taken to ensure\n * that beginSection / endSection pairs are properly nested and called from the same thread.\n */\nvoid ATrace_endSection();\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_NATIVE_TRACE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/android/window.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * @addtogroup NativeActivity Native Activity\n * @{\n */\n\n/**\n * @file window.h\n */\n\n#ifndef ANDROID_WINDOW_H\n#define ANDROID_WINDOW_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Window flags, as per the Java API at android.view.WindowManager.LayoutParams.\n */\nenum {\n    /**\n     * As long as this window is visible to the user, allow the lock\n     * screen to activate while the screen is on.  This can be used\n     * independently, or in combination with {@link\n     * AWINDOW_FLAG_KEEP_SCREEN_ON} and/or {@link\n     * AWINDOW_FLAG_SHOW_WHEN_LOCKED}\n     */\n    AWINDOW_FLAG_ALLOW_LOCK_WHILE_SCREEN_ON = 0x00000001,\n    /** Everything behind this window will be dimmed. */\n    AWINDOW_FLAG_DIM_BEHIND                 = 0x00000002,\n    /**\n     * Blur everything behind this window.\n     * @deprecated Blurring is no longer supported.\n     */\n    AWINDOW_FLAG_BLUR_BEHIND                = 0x00000004,\n    /**\n     * This window won't ever get key input focus, so the\n     * user can not send key or other button events to it.  Those will\n     * instead go to whatever focusable window is behind it.  This flag\n     * will also enable {@link AWINDOW_FLAG_NOT_TOUCH_MODAL} whether or not that\n     * is explicitly set.\n     *\n     * Setting this flag also implies that the window will not need to\n     * interact with\n     * a soft input method, so it will be Z-ordered and positioned\n     * independently of any active input method (typically this means it\n     * gets Z-ordered on top of the input method, so it can use the full\n     * screen for its content and cover the input method if needed.  You\n     * can use {@link AWINDOW_FLAG_ALT_FOCUSABLE_IM} to modify this behavior.\n     */\n    AWINDOW_FLAG_NOT_FOCUSABLE              = 0x00000008,\n    /** this window can never receive touch events. */\n    AWINDOW_FLAG_NOT_TOUCHABLE              = 0x00000010,\n    /**\n     * Even when this window is focusable (its\n     * {@link AWINDOW_FLAG_NOT_FOCUSABLE} is not set), allow any pointer events\n     * outside of the window to be sent to the windows behind it.  Otherwise\n     * it will consume all pointer events itself, regardless of whether they\n     * are inside of the window.\n     */\n    AWINDOW_FLAG_NOT_TOUCH_MODAL            = 0x00000020,\n    /**\n     * When set, if the device is asleep when the touch\n     * screen is pressed, you will receive this first touch event.  Usually\n     * the first touch event is consumed by the system since the user can\n     * not see what they are pressing on.\n     *\n     * @deprecated This flag has no effect.\n     */\n    AWINDOW_FLAG_TOUCHABLE_WHEN_WAKING      = 0x00000040,\n    /**\n     * As long as this window is visible to the user, keep\n     * the device's screen turned on and bright.\n     */\n    AWINDOW_FLAG_KEEP_SCREEN_ON             = 0x00000080,\n    /**\n     * Place the window within the entire screen, ignoring\n     * decorations around the border (such as the status bar).  The\n     * window must correctly position its contents to take the screen\n     * decoration into account.\n     */\n    AWINDOW_FLAG_LAYOUT_IN_SCREEN           = 0x00000100,\n    /** allow window to extend outside of the screen. */\n    AWINDOW_FLAG_LAYOUT_NO_LIMITS           = 0x00000200,\n    /**\n     * Hide all screen decorations (such as the status\n     * bar) while this window is displayed.  This allows the window to\n     * use the entire display space for itself -- the status bar will\n     * be hidden when an app window with this flag set is on the top\n     * layer. A fullscreen window will ignore a value of {@link\n     * AWINDOW_SOFT_INPUT_ADJUST_RESIZE}; the window will stay\n     * fullscreen and will not resize.\n     */\n    AWINDOW_FLAG_FULLSCREEN                 = 0x00000400,\n    /**\n     * Override {@link AWINDOW_FLAG_FULLSCREEN} and force the\n     * screen decorations (such as the status bar) to be shown.\n     */\n    AWINDOW_FLAG_FORCE_NOT_FULLSCREEN       = 0x00000800,\n    /**\n     * Turn on dithering when compositing this window to\n     * the screen.\n     * @deprecated This flag is no longer used.\n     */\n    AWINDOW_FLAG_DITHER                     = 0x00001000,\n    /**\n     * Treat the content of the window as secure, preventing\n     * it from appearing in screenshots or from being viewed on non-secure\n     * displays.\n     */\n    AWINDOW_FLAG_SECURE                     = 0x00002000,\n    /**\n     * A special mode where the layout parameters are used\n     * to perform scaling of the surface when it is composited to the\n     * screen.\n     */\n    AWINDOW_FLAG_SCALED                     = 0x00004000,\n    /**\n     * Intended for windows that will often be used when the user is\n     * holding the screen against their face, it will aggressively\n     * filter the event stream to prevent unintended presses in this\n     * situation that may not be desired for a particular window, when\n     * such an event stream is detected, the application will receive\n     * a {@link AMOTION_EVENT_ACTION_CANCEL} to indicate this so\n     * applications can handle this accordingly by taking no action on\n     * the event until the finger is released.\n     */\n    AWINDOW_FLAG_IGNORE_CHEEK_PRESSES       = 0x00008000,\n    /**\n     * A special option only for use in combination with\n     * {@link AWINDOW_FLAG_LAYOUT_IN_SCREEN}.  When requesting layout in the\n     * screen your window may appear on top of or behind screen decorations\n     * such as the status bar.  By also including this flag, the window\n     * manager will report the inset rectangle needed to ensure your\n     * content is not covered by screen decorations.\n     */\n    AWINDOW_FLAG_LAYOUT_INSET_DECOR         = 0x00010000,\n    /**\n     * Invert the state of {@link AWINDOW_FLAG_NOT_FOCUSABLE} with\n     * respect to how this window interacts with the current method.\n     * That is, if FLAG_NOT_FOCUSABLE is set and this flag is set,\n     * then the window will behave as if it needs to interact with the\n     * input method and thus be placed behind/away from it; if {@link\n     * AWINDOW_FLAG_NOT_FOCUSABLE} is not set and this flag is set,\n     * then the window will behave as if it doesn't need to interact\n     * with the input method and can be placed to use more space and\n     * cover the input method.\n     */\n    AWINDOW_FLAG_ALT_FOCUSABLE_IM           = 0x00020000,\n    /**\n     * If you have set {@link AWINDOW_FLAG_NOT_TOUCH_MODAL}, you\n     * can set this flag to receive a single special MotionEvent with\n     * the action\n     * {@link AMOTION_EVENT_ACTION_OUTSIDE} for\n     * touches that occur outside of your window.  Note that you will not\n     * receive the full down/move/up gesture, only the location of the\n     * first down as an {@link AMOTION_EVENT_ACTION_OUTSIDE}.\n     */\n    AWINDOW_FLAG_WATCH_OUTSIDE_TOUCH        = 0x00040000,\n    /**\n     * Special flag to let windows be shown when the screen\n     * is locked. This will let application windows take precedence over\n     * key guard or any other lock screens. Can be used with\n     * {@link AWINDOW_FLAG_KEEP_SCREEN_ON} to turn screen on and display windows\n     * directly before showing the key guard window.  Can be used with\n     * {@link AWINDOW_FLAG_DISMISS_KEYGUARD} to automatically fully dismisss\n     * non-secure keyguards.  This flag only applies to the top-most\n     * full-screen window.\n     */\n    AWINDOW_FLAG_SHOW_WHEN_LOCKED           = 0x00080000,\n    /**\n     * Ask that the system wallpaper be shown behind\n     * your window.  The window surface must be translucent to be able\n     * to actually see the wallpaper behind it; this flag just ensures\n     * that the wallpaper surface will be there if this window actually\n     * has translucent regions.\n     */\n    AWINDOW_FLAG_SHOW_WALLPAPER             = 0x00100000,\n    /**\n     * When set as a window is being added or made\n     * visible, once the window has been shown then the system will\n     * poke the power manager's user activity (as if the user had woken\n     * up the device) to turn the screen on.\n     */\n    AWINDOW_FLAG_TURN_SCREEN_ON             = 0x00200000,\n    /**\n     * When set the window will cause the keyguard to\n     * be dismissed, only if it is not a secure lock keyguard.  Because such\n     * a keyguard is not needed for security, it will never re-appear if\n     * the user navigates to another window (in contrast to\n     * {@link AWINDOW_FLAG_SHOW_WHEN_LOCKED}, which will only temporarily\n     * hide both secure and non-secure keyguards but ensure they reappear\n     * when the user moves to another UI that doesn't hide them).\n     * If the keyguard is currently active and is secure (requires an\n     * unlock pattern) than the user will still need to confirm it before\n     * seeing this window, unless {@link AWINDOW_FLAG_SHOW_WHEN_LOCKED} has\n     * also been set.\n     */\n    AWINDOW_FLAG_DISMISS_KEYGUARD           = 0x00400000,\n};\n\n#ifdef __cplusplus\n};\n#endif\n\n#endif // ANDROID_WINDOW_H\n\n/** @} */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/AppOpsManager.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_APP_OPS_MANAGER_H\n#define ANDROID_APP_OPS_MANAGER_H\n\n#include <binder/IAppOpsService.h>\n\n#include <utils/threads.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass AppOpsManager\n{\npublic:\n    enum {\n        MODE_ALLOWED = IAppOpsService::MODE_ALLOWED,\n        MODE_IGNORED = IAppOpsService::MODE_IGNORED,\n        MODE_ERRORED = IAppOpsService::MODE_ERRORED\n    };\n\n    enum {\n        OP_NONE = -1,\n        OP_COARSE_LOCATION = 0,\n        OP_FINE_LOCATION = 1,\n        OP_GPS = 2,\n        OP_VIBRATE = 3,\n        OP_READ_CONTACTS = 4,\n        OP_WRITE_CONTACTS = 5,\n        OP_READ_CALL_LOG = 6,\n        OP_WRITE_CALL_LOG = 7,\n        OP_READ_CALENDAR = 8,\n        OP_WRITE_CALENDAR = 9,\n        OP_WIFI_SCAN = 10,\n        OP_POST_NOTIFICATION = 11,\n        OP_NEIGHBORING_CELLS = 12,\n        OP_CALL_PHONE = 13,\n        OP_READ_SMS = 14,\n        OP_WRITE_SMS = 15,\n        OP_RECEIVE_SMS = 16,\n        OP_RECEIVE_EMERGECY_SMS = 17,\n        OP_RECEIVE_MMS = 18,\n        OP_RECEIVE_WAP_PUSH = 19,\n        OP_SEND_SMS = 20,\n        OP_READ_ICC_SMS = 21,\n        OP_WRITE_ICC_SMS = 22,\n        OP_WRITE_SETTINGS = 23,\n        OP_SYSTEM_ALERT_WINDOW = 24,\n        OP_ACCESS_NOTIFICATIONS = 25,\n        OP_CAMERA = 26,\n        OP_RECORD_AUDIO = 27,\n        OP_PLAY_AUDIO = 28,\n        OP_READ_CLIPBOARD = 29,\n        OP_WRITE_CLIPBOARD = 30,\n        OP_TAKE_MEDIA_BUTTONS = 31,\n        OP_TAKE_AUDIO_FOCUS = 32,\n        OP_AUDIO_MASTER_VOLUME = 33,\n        OP_AUDIO_VOICE_VOLUME = 34,\n        OP_AUDIO_RING_VOLUME = 35,\n        OP_AUDIO_MEDIA_VOLUME = 36,\n        OP_AUDIO_ALARM_VOLUME = 37,\n        OP_AUDIO_NOTIFICATION_VOLUME = 38,\n        OP_AUDIO_BLUETOOTH_VOLUME = 39,\n        OP_WAKE_LOCK = 40,\n        OP_MONITOR_LOCATION = 41,\n        OP_MONITOR_HIGH_POWER_LOCATION = 42,\n        OP_GET_USAGE_STATS = 43,\n        OP_MUTE_MICROPHONE = 44,\n        OP_TOAST_WINDOW = 45,\n        OP_PROJECT_MEDIA = 46,\n        OP_ACTIVATE_VPN = 47,\n        OP_WRITE_WALLPAPER = 48,\n        OP_ASSIST_STRUCTURE = 49,\n        OP_ASSIST_SCREENSHOT = 50,\n        OP_READ_PHONE_STATE = 51,\n        OP_ADD_VOICEMAIL = 52,\n        OP_USE_SIP = 53,\n        OP_PROCESS_OUTGOING_CALLS = 54,\n        OP_USE_FINGERPRINT = 55,\n        OP_BODY_SENSORS = 56,\n        OP_READ_CELL_BROADCASTS = 57,\n        OP_MOCK_LOCATION = 58,\n        OP_READ_EXTERNAL_STORAGE = 59,\n        OP_WRITE_EXTERNAL_STORAGE = 60,\n        OP_TURN_SCREEN_ON = 61,\n        OP_GET_ACCOUNTS = 62,\n        OP_WIFI_CHANGE = 63,\n        OP_BLUETOOTH_CHANGE = 64,\n        OP_BOOT_COMPLETED = 65,\n        OP_NFC_CHANGE = 66,\n        OP_DATA_CONNECT_CHANGE = 67,\n        OP_SU = 68\n    };\n\n    AppOpsManager();\n\n    int32_t checkOp(int32_t op, int32_t uid, const String16& callingPackage);\n    int32_t noteOp(int32_t op, int32_t uid, const String16& callingPackage);\n    int32_t startOp(int32_t op, int32_t uid, const String16& callingPackage);\n    void finishOp(int32_t op, int32_t uid, const String16& callingPackage);\n    void startWatchingMode(int32_t op, const String16& packageName,\n            const sp<IAppOpsCallback>& callback);\n    void stopWatchingMode(const sp<IAppOpsCallback>& callback);\n    int32_t permissionToOpCode(const String16& permission);\n\nprivate:\n    Mutex mLock;\n    sp<IAppOpsService> mService;\n\n    sp<IAppOpsService> getService();\n};\n\n\n}; // namespace android\n// ---------------------------------------------------------------------------\n#endif // ANDROID_APP_OPS_MANAGER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/Binder.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_BINDER_H\n#define ANDROID_BINDER_H\n\n#include <stdatomic.h>\n#include <stdint.h>\n#include <binder/IBinder.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass BBinder : public IBinder\n{\npublic:\n                        BBinder();\n\n    virtual const String16& getInterfaceDescriptor() const;\n    virtual bool        isBinderAlive() const;\n    virtual status_t    pingBinder();\n    virtual status_t    dump(int fd, const Vector<String16>& args);\n\n    virtual status_t    transact(   uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n\n    virtual status_t    linkToDeath(const sp<DeathRecipient>& recipient,\n                                    void* cookie = NULL,\n                                    uint32_t flags = 0);\n\n    virtual status_t    unlinkToDeath(  const wp<DeathRecipient>& recipient,\n                                        void* cookie = NULL,\n                                        uint32_t flags = 0,\n                                        wp<DeathRecipient>* outRecipient = NULL);\n\n    virtual void        attachObject(   const void* objectID,\n                                        void* object,\n                                        void* cleanupCookie,\n                                        object_cleanup_func func);\n    virtual void*       findObject(const void* objectID) const;\n    virtual void        detachObject(const void* objectID);\n\n    virtual BBinder*    localBinder();\n\nprotected:\n    virtual             ~BBinder();\n\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n\nprivate:\n                        BBinder(const BBinder& o);\n            BBinder&    operator=(const BBinder& o);\n\n    class Extras;\n\n    atomic_uintptr_t    mExtras;  // should be atomic<Extras *>\n            void*       mReserved0;\n};\n\n// ---------------------------------------------------------------------------\n\nclass BpRefBase : public virtual RefBase\n{\nprotected:\n                            BpRefBase(const sp<IBinder>& o);\n    virtual                 ~BpRefBase();\n    virtual void            onFirstRef();\n    virtual void            onLastStrongRef(const void* id);\n    virtual bool            onIncStrongAttempted(uint32_t flags, const void* id);\n\n    inline  IBinder*        remote()                { return mRemote; }\n    inline  IBinder*        remote() const          { return mRemote; }\n\nprivate:\n                            BpRefBase(const BpRefBase& o);\n    BpRefBase&              operator=(const BpRefBase& o);\n\n    IBinder* const          mRemote;\n    RefBase::weakref_type*  mRefs;\n    volatile int32_t        mState;\n};\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_BINDER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/BinderService.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_BINDER_SERVICE_H\n#define ANDROID_BINDER_SERVICE_H\n\n#include <stdint.h>\n\n#include <utils/Errors.h>\n#include <utils/String16.h>\n\n#include <binder/IServiceManager.h>\n#include <binder/IPCThreadState.h>\n#include <binder/ProcessState.h>\n#include <binder/IServiceManager.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\ntemplate<typename SERVICE>\nclass BinderService\n{\npublic:\n    static status_t publish(bool allowIsolated = false) {\n        sp<IServiceManager> sm(defaultServiceManager());\n        return sm->addService(\n                String16(SERVICE::getServiceName()),\n                new SERVICE(), allowIsolated);\n    }\n\n    static void publishAndJoinThreadPool(bool allowIsolated = false) {\n        publish(allowIsolated);\n        joinThreadPool();\n    }\n\n    static void instantiate() { publish(); }\n\n    static status_t shutdown() { return NO_ERROR; }\n\nprivate:\n    static void joinThreadPool() {\n        sp<ProcessState> ps(ProcessState::self());\n        ps->startThreadPool();\n        ps->giveThreadPoolName();\n        IPCThreadState::self()->joinThreadPool();\n    }\n};\n\n\n}; // namespace android\n// ---------------------------------------------------------------------------\n#endif // ANDROID_BINDER_SERVICE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/BpBinder.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_BPBINDER_H\n#define ANDROID_BPBINDER_H\n\n#include <binder/IBinder.h>\n#include <utils/KeyedVector.h>\n#include <utils/threads.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass BpBinder : public IBinder\n{\npublic:\n                        BpBinder(int32_t handle);\n\n    inline  int32_t     handle() const { return mHandle; }\n\n    virtual const String16&    getInterfaceDescriptor() const;\n    virtual bool        isBinderAlive() const;\n    virtual status_t    pingBinder();\n    virtual status_t    dump(int fd, const Vector<String16>& args);\n\n    virtual status_t    transact(   uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n\n    virtual status_t    linkToDeath(const sp<DeathRecipient>& recipient,\n                                    void* cookie = NULL,\n                                    uint32_t flags = 0);\n    virtual status_t    unlinkToDeath(  const wp<DeathRecipient>& recipient,\n                                        void* cookie = NULL,\n                                        uint32_t flags = 0,\n                                        wp<DeathRecipient>* outRecipient = NULL);\n\n    virtual void        attachObject(   const void* objectID,\n                                        void* object,\n                                        void* cleanupCookie,\n                                        object_cleanup_func func);\n    virtual void*       findObject(const void* objectID) const;\n    virtual void        detachObject(const void* objectID);\n\n    virtual BpBinder*   remoteBinder();\n\n            status_t    setConstantData(const void* data, size_t size);\n            void        sendObituary();\n\n    class ObjectManager\n    {\n    public:\n                    ObjectManager();\n                    ~ObjectManager();\n\n        void        attach( const void* objectID,\n                            void* object,\n                            void* cleanupCookie,\n                            IBinder::object_cleanup_func func);\n        void*       find(const void* objectID) const;\n        void        detach(const void* objectID);\n\n        void        kill();\n\n    private:\n                    ObjectManager(const ObjectManager&);\n        ObjectManager& operator=(const ObjectManager&);\n\n        struct entry_t\n        {\n            void* object;\n            void* cleanupCookie;\n            IBinder::object_cleanup_func func;\n        };\n\n        KeyedVector<const void*, entry_t> mObjects;\n    };\n\nprotected:\n    virtual             ~BpBinder();\n    virtual void        onFirstRef();\n    virtual void        onLastStrongRef(const void* id);\n    virtual bool        onIncStrongAttempted(uint32_t flags, const void* id);\n\nprivate:\n    const   int32_t             mHandle;\n\n    struct Obituary {\n        wp<DeathRecipient> recipient;\n        void* cookie;\n        uint32_t flags;\n    };\n\n            void                reportOneDeath(const Obituary& obit);\n            bool                isDescriptorCached() const;\n\n    mutable Mutex               mLock;\n            volatile int32_t    mAlive;\n            volatile int32_t    mObitsSent;\n            Vector<Obituary>*   mObituaries;\n            ObjectManager       mObjects;\n            Parcel*             mConstantData;\n    mutable String16            mDescriptorCache;\n};\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_BPBINDER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/BufferedTextOutput.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_BUFFEREDTEXTOUTPUT_H\n#define ANDROID_BUFFEREDTEXTOUTPUT_H\n\n#include <binder/TextOutput.h>\n#include <utils/threads.h>\n#include <sys/uio.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass BufferedTextOutput : public TextOutput\n{\npublic:\n    //** Flags for constructor */\n    enum {\n        MULTITHREADED = 0x0001\n    };\n    \n                        BufferedTextOutput(uint32_t flags = 0);\n    virtual             ~BufferedTextOutput();\n    \n    virtual status_t    print(const char* txt, size_t len);\n    virtual void        moveIndent(int delta);\n    \n    virtual void        pushBundle();\n    virtual void        popBundle();\n    \nprotected:\n    virtual status_t    writeLines(const struct iovec& vec, size_t N) = 0;\n\nprivate:\n    struct BufferState;\n    struct ThreadState;\n    \n    static  ThreadState*getThreadState();\n    static  void        threadDestructor(void *st);\n    \n            BufferState*getBuffer() const;\n            \n    uint32_t            mFlags;\n    const int32_t       mSeq;\n    const int32_t       mIndex;\n    \n    Mutex               mLock;\n    BufferState*        mGlobalState;\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_BUFFEREDTEXTOUTPUT_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/Debug.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_BINDER_DEBUG_H\n#define ANDROID_BINDER_DEBUG_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nconst char* stringForIndent(int32_t indentLevel);\n\ntypedef void (*debugPrintFunc)(void* cookie, const char* txt);\n\nvoid printTypeCode(uint32_t typeCode,\n    debugPrintFunc func = 0, void* cookie = 0);\n\nvoid printHexData(int32_t indent, const void *buf, size_t length,\n    size_t bytesPerLine=16, int32_t singleLineBytesCutoff=16,\n    size_t alignment=0, bool cArrayStyle=false,\n    debugPrintFunc func = 0, void* cookie = 0);\n\n#ifdef __cplusplus\n}\n#endif\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_BINDER_DEBUG_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IAppOpsCallback.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n#ifndef ANDROID_IAPP_OPS_CALLBACK_H\n#define ANDROID_IAPP_OPS_CALLBACK_H\n\n#include <binder/IInterface.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IAppOpsCallback : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(AppOpsCallback);\n\n    virtual void opChanged(int32_t op, const String16& packageName) = 0;\n\n    enum {\n        OP_CHANGED_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION\n    };\n};\n\n// ----------------------------------------------------------------------\n\nclass BnAppOpsCallback : public BnInterface<IAppOpsCallback>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_IAPP_OPS_CALLBACK_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IAppOpsService.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n#ifndef ANDROID_IAPP_OPS_SERVICE_H\n#define ANDROID_IAPP_OPS_SERVICE_H\n\n#include <binder/IAppOpsCallback.h>\n#include <binder/IInterface.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IAppOpsService : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(AppOpsService);\n\n    virtual int32_t checkOperation(int32_t code, int32_t uid, const String16& packageName) = 0;\n    virtual int32_t noteOperation(int32_t code, int32_t uid, const String16& packageName) = 0;\n    virtual int32_t startOperation(const sp<IBinder>& token, int32_t code, int32_t uid,\n            const String16& packageName) = 0;\n    virtual void finishOperation(const sp<IBinder>& token, int32_t code, int32_t uid,\n            const String16& packageName) = 0;\n    virtual void startWatchingMode(int32_t op, const String16& packageName,\n            const sp<IAppOpsCallback>& callback) = 0;\n    virtual void stopWatchingMode(const sp<IAppOpsCallback>& callback) = 0;\n    virtual sp<IBinder> getToken(const sp<IBinder>& clientToken) = 0;\n    virtual int32_t permissionToOpCode(const String16& permission) = 0;\n\n    enum {\n        CHECK_OPERATION_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION,\n        NOTE_OPERATION_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+1,\n        START_OPERATION_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+2,\n        FINISH_OPERATION_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+3,\n        START_WATCHING_MODE_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+4,\n        STOP_WATCHING_MODE_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+5,\n        GET_TOKEN_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+6,\n        PERMISSION_TO_OP_CODE_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION+7,\n    };\n\n    enum {\n        MODE_ALLOWED = 0,\n        MODE_IGNORED = 1,\n        MODE_ERRORED = 2\n    };\n};\n\n// ----------------------------------------------------------------------\n\nclass BnAppOpsService : public BnInterface<IAppOpsService>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_IAPP_OPS_SERVICE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IBatteryStats.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_IBATTERYSTATS_H\n#define ANDROID_IBATTERYSTATS_H\n\n#include <binder/IInterface.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IBatteryStats : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(BatteryStats);\n\n    virtual void noteStartSensor(int uid, int sensor) = 0;\n    virtual void noteStopSensor(int uid, int sensor) = 0;\n    virtual void noteStartVideo(int uid) = 0;\n    virtual void noteStopVideo(int uid) = 0;\n    virtual void noteStartAudio(int uid) = 0;\n    virtual void noteStopAudio(int uid) = 0;\n    virtual void noteResetVideo() = 0;\n    virtual void noteResetAudio() = 0;\n    virtual void noteFlashlightOn(int uid) = 0;\n    virtual void noteFlashlightOff(int uid) = 0;\n    virtual void noteStartCamera(int uid) = 0;\n    virtual void noteStopCamera(int uid) = 0;\n    virtual void noteResetCamera() = 0;\n    virtual void noteResetFlashlight() = 0;\n\n    enum {\n        NOTE_START_SENSOR_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION,\n        NOTE_STOP_SENSOR_TRANSACTION,\n        NOTE_START_VIDEO_TRANSACTION,\n        NOTE_STOP_VIDEO_TRANSACTION,\n        NOTE_START_AUDIO_TRANSACTION,\n        NOTE_STOP_AUDIO_TRANSACTION,\n        NOTE_RESET_VIDEO_TRANSACTION,\n        NOTE_RESET_AUDIO_TRANSACTION,\n        NOTE_FLASHLIGHT_ON_TRANSACTION,\n        NOTE_FLASHLIGHT_OFF_TRANSACTION,\n        NOTE_START_CAMERA_TRANSACTION,\n        NOTE_STOP_CAMERA_TRANSACTION,\n        NOTE_RESET_CAMERA_TRANSACTION,\n        NOTE_RESET_FLASHLIGHT_TRANSACTION\n    };\n};\n\n// ----------------------------------------------------------------------\n\nclass BnBatteryStats : public BnInterface<IBatteryStats>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_IBATTERYSTATS_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IBinder.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_IBINDER_H\n#define ANDROID_IBINDER_H\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <utils/String16.h>\n#include <utils/Vector.h>\n\n\n#define B_PACK_CHARS(c1, c2, c3, c4) \\\n    ((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4))\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass BBinder;\nclass BpBinder;\nclass IInterface;\nclass Parcel;\n\n/**\n * Base class and low-level protocol for a remotable object.\n * You can derive from this class to create an object for which other\n * processes can hold references to it.  Communication between processes\n * (method calls, property get and set) is down through a low-level\n * protocol implemented on top of the transact() API.\n */\nclass IBinder : public virtual RefBase\n{\npublic:\n    enum {\n        FIRST_CALL_TRANSACTION  = 0x00000001,\n        LAST_CALL_TRANSACTION   = 0x00ffffff,\n\n        PING_TRANSACTION        = B_PACK_CHARS('_','P','N','G'),\n        DUMP_TRANSACTION        = B_PACK_CHARS('_','D','M','P'),\n        INTERFACE_TRANSACTION   = B_PACK_CHARS('_', 'N', 'T', 'F'),\n        SYSPROPS_TRANSACTION    = B_PACK_CHARS('_', 'S', 'P', 'R'),\n\n        // Corresponds to TF_ONE_WAY -- an asynchronous call.\n        FLAG_ONEWAY             = 0x00000001\n    };\n\n                          IBinder();\n\n    /**\n     * Check if this IBinder implements the interface named by\n     * @a descriptor.  If it does, the base pointer to it is returned,\n     * which you can safely static_cast<> to the concrete C++ interface.\n     */\n    virtual sp<IInterface>  queryLocalInterface(const String16& descriptor);\n\n    /**\n     * Return the canonical name of the interface provided by this IBinder\n     * object.\n     */\n    virtual const String16& getInterfaceDescriptor() const = 0;\n\n    virtual bool            isBinderAlive() const = 0;\n    virtual status_t        pingBinder() = 0;\n    virtual status_t        dump(int fd, const Vector<String16>& args) = 0;\n\n    virtual status_t        transact(   uint32_t code,\n                                        const Parcel& data,\n                                        Parcel* reply,\n                                        uint32_t flags = 0) = 0;\n\n    class DeathRecipient : public virtual RefBase\n    {\n    public:\n        virtual void binderDied(const wp<IBinder>& who) = 0;\n    };\n\n    /**\n     * Register the @a recipient for a notification if this binder\n     * goes away.  If this binder object unexpectedly goes away\n     * (typically because its hosting process has been killed),\n     * then DeathRecipient::binderDied() will be called with a reference\n     * to this.\n     *\n     * The @a cookie is optional -- if non-NULL, it should be a\n     * memory address that you own (that is, you know it is unique).\n     *\n     * @note You will only receive death notifications for remote binders,\n     * as local binders by definition can't die without you dying as well.\n     * Trying to use this function on a local binder will result in an\n     * INVALID_OPERATION code being returned and nothing happening.\n     *\n     * @note This link always holds a weak reference to its recipient.\n     *\n     * @note You will only receive a weak reference to the dead\n     * binder.  You should not try to promote this to a strong reference.\n     * (Nor should you need to, as there is nothing useful you can\n     * directly do with it now that it has passed on.)\n     */\n    virtual status_t        linkToDeath(const sp<DeathRecipient>& recipient,\n                                        void* cookie = NULL,\n                                        uint32_t flags = 0) = 0;\n\n    /**\n     * Remove a previously registered death notification.\n     * The @a recipient will no longer be called if this object\n     * dies.  The @a cookie is optional.  If non-NULL, you can\n     * supply a NULL @a recipient, and the recipient previously\n     * added with that cookie will be unlinked.\n     */\n    virtual status_t        unlinkToDeath(  const wp<DeathRecipient>& recipient,\n                                            void* cookie = NULL,\n                                            uint32_t flags = 0,\n                                            wp<DeathRecipient>* outRecipient = NULL) = 0;\n\n    virtual bool            checkSubclass(const void* subclassID) const;\n\n    typedef void (*object_cleanup_func)(const void* id, void* obj, void* cleanupCookie);\n\n    virtual void            attachObject(   const void* objectID,\n                                            void* object,\n                                            void* cleanupCookie,\n                                            object_cleanup_func func) = 0;\n    virtual void*           findObject(const void* objectID) const = 0;\n    virtual void            detachObject(const void* objectID) = 0;\n\n    virtual BBinder*        localBinder();\n    virtual BpBinder*       remoteBinder();\n\nprotected:\n    virtual          ~IBinder();\n\nprivate:\n};\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_IBINDER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IInterface.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n#ifndef ANDROID_IINTERFACE_H\n#define ANDROID_IINTERFACE_H\n\n#include <binder/Binder.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IInterface : public virtual RefBase\n{\npublic:\n            IInterface();\n            static sp<IBinder>  asBinder(const IInterface*);\n            static sp<IBinder>  asBinder(const sp<IInterface>&);\n\nprotected:\n    virtual                     ~IInterface();\n    virtual IBinder*            onAsBinder() = 0;\n};\n\n// ----------------------------------------------------------------------\n\ntemplate<typename INTERFACE>\ninline sp<INTERFACE> interface_cast(const sp<IBinder>& obj)\n{\n    return INTERFACE::asInterface(obj);\n}\n\n// ----------------------------------------------------------------------\n\ntemplate<typename INTERFACE>\nclass BnInterface : public INTERFACE, public BBinder\n{\npublic:\n    virtual sp<IInterface>      queryLocalInterface(const String16& _descriptor);\n    virtual const String16&     getInterfaceDescriptor() const;\n\nprotected:\n    virtual IBinder*            onAsBinder();\n};\n\n// ----------------------------------------------------------------------\n\ntemplate<typename INTERFACE>\nclass BpInterface : public INTERFACE, public BpRefBase\n{\npublic:\n                                BpInterface(const sp<IBinder>& remote);\n\nprotected:\n    virtual IBinder*            onAsBinder();\n};\n\n// ----------------------------------------------------------------------\n\n#define DECLARE_META_INTERFACE(INTERFACE)                               \\\n    static const android::String16 descriptor;                          \\\n    static android::sp<I##INTERFACE> asInterface(                       \\\n            const android::sp<android::IBinder>& obj);                  \\\n    virtual const android::String16& getInterfaceDescriptor() const;    \\\n    I##INTERFACE();                                                     \\\n    virtual ~I##INTERFACE();                                            \\\n\n\n#define IMPLEMENT_META_INTERFACE(INTERFACE, NAME)                       \\\n    const android::String16 I##INTERFACE::descriptor(NAME);             \\\n    const android::String16&                                            \\\n            I##INTERFACE::getInterfaceDescriptor() const {              \\\n        return I##INTERFACE::descriptor;                                \\\n    }                                                                   \\\n    android::sp<I##INTERFACE> I##INTERFACE::asInterface(                \\\n            const android::sp<android::IBinder>& obj)                   \\\n    {                                                                   \\\n        android::sp<I##INTERFACE> intr;                                 \\\n        if (obj != NULL) {                                              \\\n            intr = static_cast<I##INTERFACE*>(                          \\\n                obj->queryLocalInterface(                               \\\n                        I##INTERFACE::descriptor).get());               \\\n            if (intr == NULL) {                                         \\\n                intr = new Bp##INTERFACE(obj);                          \\\n            }                                                           \\\n        }                                                               \\\n        return intr;                                                    \\\n    }                                                                   \\\n    I##INTERFACE::I##INTERFACE() { }                                    \\\n    I##INTERFACE::~I##INTERFACE() { }                                   \\\n\n\n#define CHECK_INTERFACE(interface, data, reply)                         \\\n    if (!data.checkInterface(this)) { return PERMISSION_DENIED; }       \\\n\n\n// ----------------------------------------------------------------------\n// No user-serviceable parts after this...\n\ntemplate<typename INTERFACE>\ninline sp<IInterface> BnInterface<INTERFACE>::queryLocalInterface(\n        const String16& _descriptor)\n{\n    if (_descriptor == INTERFACE::descriptor) return this;\n    return NULL;\n}\n\ntemplate<typename INTERFACE>\ninline const String16& BnInterface<INTERFACE>::getInterfaceDescriptor() const\n{\n    return INTERFACE::getInterfaceDescriptor();\n}\n\ntemplate<typename INTERFACE>\nIBinder* BnInterface<INTERFACE>::onAsBinder()\n{\n    return this;\n}\n\ntemplate<typename INTERFACE>\ninline BpInterface<INTERFACE>::BpInterface(const sp<IBinder>& remote)\n    : BpRefBase(remote)\n{\n}\n\ntemplate<typename INTERFACE>\ninline IBinder* BpInterface<INTERFACE>::onAsBinder()\n{\n    return remote();\n}\n    \n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_IINTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IMemory.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_IMEMORY_H\n#define ANDROID_IMEMORY_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <sys/mman.h>\n\n#include <utils/RefBase.h>\n#include <utils/Errors.h>\n#include <binder/IInterface.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------------\n\nclass IMemoryHeap : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(MemoryHeap);\n\n    // flags returned by getFlags()\n    enum {\n        READ_ONLY   = 0x00000001,\n#ifdef USE_MEMORY_HEAP_ION\n        USE_ION_FD  = 0x00008000\n#else\n        USE_ION_FD  = 0x00000008\n#endif\n    };\n\n    virtual int         getHeapID() const = 0;\n    virtual void*       getBase() const = 0;\n    virtual size_t      getSize() const = 0;\n    virtual uint32_t    getFlags() const = 0;\n    virtual uint32_t    getOffset() const = 0;\n\n    // these are there just for backward source compatibility\n    int32_t heapID() const { return getHeapID(); }\n    void*   base() const  { return getBase(); }\n    size_t  virtualSize() const { return getSize(); }\n};\n\nclass BnMemoryHeap : public BnInterface<IMemoryHeap>\n{\npublic:\n    virtual status_t onTransact( \n            uint32_t code,\n            const Parcel& data,\n            Parcel* reply,\n            uint32_t flags = 0);\n    \n    BnMemoryHeap();\nprotected:\n    virtual ~BnMemoryHeap();\n};\n\n// ----------------------------------------------------------------------------\n\nclass IMemory : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(Memory);\n\n    virtual sp<IMemoryHeap> getMemory(ssize_t* offset=0, size_t* size=0) const = 0;\n\n    // helpers\n    void* fastPointer(const sp<IBinder>& heap, ssize_t offset) const;\n    void* pointer() const;\n    size_t size() const;\n    ssize_t offset() const;\n};\n\nclass BnMemory : public BnInterface<IMemory>\n{\npublic:\n    virtual status_t onTransact(\n            uint32_t code,\n            const Parcel& data,\n            Parcel* reply,\n            uint32_t flags = 0);\n\n    BnMemory();\nprotected:\n    virtual ~BnMemory();\n};\n\n// ----------------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_IMEMORY_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IPCThreadState.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_IPC_THREAD_STATE_H\n#define ANDROID_IPC_THREAD_STATE_H\n\n#include <utils/Errors.h>\n#include <binder/Parcel.h>\n#include <binder/ProcessState.h>\n#include <utils/Vector.h>\n\n#if defined(_WIN32)\ntypedef  int  uid_t;\n#endif\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass IPCThreadState\n{\npublic:\n    static  IPCThreadState*     self();\n    static  IPCThreadState*     selfOrNull();  // self(), but won't instantiate\n    \n            sp<ProcessState>    process();\n            \n            status_t            clearLastError();\n\n            pid_t               getCallingPid() const;\n            uid_t               getCallingUid() const;\n\n            void                setStrictModePolicy(int32_t policy);\n            int32_t             getStrictModePolicy() const;\n\n            void                setLastTransactionBinderFlags(int32_t flags);\n            int32_t             getLastTransactionBinderFlags() const;\n\n            int64_t             clearCallingIdentity();\n            void                restoreCallingIdentity(int64_t token);\n            \n            int                 setupPolling(int* fd);\n            status_t            handlePolledCommands();\n            void                flushCommands();\n\n            void                joinThreadPool(bool isMain = true);\n            \n            // Stop the local process.\n            void                stopProcess(bool immediate = true);\n            \n            status_t            transact(int32_t handle,\n                                         uint32_t code, const Parcel& data,\n                                         Parcel* reply, uint32_t flags);\n\n            void                incStrongHandle(int32_t handle);\n            void                decStrongHandle(int32_t handle);\n            void                incWeakHandle(int32_t handle);\n            void                decWeakHandle(int32_t handle);\n            status_t            attemptIncStrongHandle(int32_t handle);\n    static  void                expungeHandle(int32_t handle, IBinder* binder);\n            status_t            requestDeathNotification(   int32_t handle,\n                                                            BpBinder* proxy); \n            status_t            clearDeathNotification( int32_t handle,\n                                                        BpBinder* proxy); \n\n    static  void                shutdown();\n\n    // Call this to disable switching threads to background scheduling when\n    // receiving incoming IPC calls.  This is specifically here for the\n    // Android system process, since it expects to have background apps calling\n    // in to it but doesn't want to acquire locks in its services while in\n    // the background.\n    static  void                disableBackgroundScheduling(bool disable);\n\n            // Call blocks until the number of executing binder threads is less than\n            // the maximum number of binder threads threads allowed for this process.\n            void                blockUntilThreadAvailable();\n\nprivate:\n                                IPCThreadState();\n                                ~IPCThreadState();\n\n            status_t            sendReply(const Parcel& reply, uint32_t flags);\n            status_t            waitForResponse(Parcel *reply,\n                                                status_t *acquireResult=NULL);\n            status_t            talkWithDriver(bool doReceive=true);\n            status_t            writeTransactionData(int32_t cmd,\n                                                     uint32_t binderFlags,\n                                                     int32_t handle,\n                                                     uint32_t code,\n                                                     const Parcel& data,\n                                                     status_t* statusBuffer);\n            status_t            getAndExecuteCommand();\n            status_t            executeCommand(int32_t command);\n            void                processPendingDerefs();\n\n            void                clearCaller();\n\n    static  void                threadDestructor(void *st);\n    static  void                freeBuffer(Parcel* parcel,\n                                           const uint8_t* data, size_t dataSize,\n                                           const binder_size_t* objects, size_t objectsSize,\n                                           void* cookie);\n    \n    const   sp<ProcessState>    mProcess;\n    const   pid_t               mMyThreadId;\n            Vector<BBinder*>    mPendingStrongDerefs;\n            Vector<RefBase::weakref_type*> mPendingWeakDerefs;\n\n            Parcel              mIn;\n            Parcel              mOut;\n            status_t            mLastError;\n            pid_t               mCallingPid;\n            uid_t               mCallingUid;\n            int32_t             mStrictModePolicy;\n            int32_t             mLastTransactionBinderFlags;\n};\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_IPC_THREAD_STATE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IPermissionController.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n#ifndef ANDROID_IPERMISSION_CONTROLLER_H\n#define ANDROID_IPERMISSION_CONTROLLER_H\n\n#include <binder/IInterface.h>\n#include <stdlib.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IPermissionController : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(PermissionController);\n\n    virtual bool checkPermission(const String16& permission, int32_t pid, int32_t uid) = 0;\n\n    virtual void getPackagesForUid(const uid_t uid, Vector<String16> &packages) = 0;\n\n    virtual bool isRuntimePermission(const String16& permission) = 0;\n\n    enum {\n        CHECK_PERMISSION_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION,\n        GET_PACKAGES_FOR_UID_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION + 1,\n        IS_RUNTIME_PERMISSION_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION + 2\n    };\n};\n\n// ----------------------------------------------------------------------\n\nclass BnPermissionController : public BnInterface<IPermissionController>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_IPERMISSION_CONTROLLER_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IProcessInfoService.h",
    "content": "/*\n * Copyright 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_I_PROCESS_INFO_SERVICE_H\n#define ANDROID_I_PROCESS_INFO_SERVICE_H\n\n#include <binder/IInterface.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IProcessInfoService : public IInterface {\npublic:\n    DECLARE_META_INTERFACE(ProcessInfoService);\n\n    virtual status_t    getProcessStatesFromPids( size_t length,\n                                                  /*in*/ int32_t* pids,\n                                                  /*out*/ int32_t* states) = 0;\n\n    enum {\n        GET_PROCESS_STATES_FROM_PIDS = IBinder::FIRST_CALL_TRANSACTION,\n    };\n};\n\n// ----------------------------------------------------------------------\n\nclass BnProcessInfoService : public BnInterface<IProcessInfoService> {\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_I_PROCESS_INFO_SERVICE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/IServiceManager.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n#ifndef ANDROID_ISERVICE_MANAGER_H\n#define ANDROID_ISERVICE_MANAGER_H\n\n#include <binder/IInterface.h>\n#include <binder/IPermissionController.h>\n#include <utils/Vector.h>\n#include <utils/String16.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass IServiceManager : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(ServiceManager);\n\n    /**\n     * Retrieve an existing service, blocking for a few seconds\n     * if it doesn't yet exist.\n     */\n    virtual sp<IBinder>         getService( const String16& name) const = 0;\n\n    /**\n     * Retrieve an existing service, non-blocking.\n     */\n    virtual sp<IBinder>         checkService( const String16& name) const = 0;\n\n    /**\n     * Register a service.\n     */\n    virtual status_t            addService( const String16& name,\n                                            const sp<IBinder>& service,\n                                            bool allowIsolated = false) = 0;\n\n    /**\n     * Return list of all existing services.\n     */\n    virtual Vector<String16>    listServices() = 0;\n\n    enum {\n        GET_SERVICE_TRANSACTION = IBinder::FIRST_CALL_TRANSACTION,\n        CHECK_SERVICE_TRANSACTION,\n        ADD_SERVICE_TRANSACTION,\n        LIST_SERVICES_TRANSACTION,\n    };\n};\n\nsp<IServiceManager> defaultServiceManager();\n\ntemplate<typename INTERFACE>\nstatus_t getService(const String16& name, sp<INTERFACE>* outService)\n{\n    const sp<IServiceManager> sm = defaultServiceManager();\n    if (sm != NULL) {\n        *outService = interface_cast<INTERFACE>(sm->getService(name));\n        if ((*outService) != NULL) return NO_ERROR;\n    }\n    return NAME_NOT_FOUND;\n}\n\nbool checkCallingPermission(const String16& permission);\nbool checkCallingPermission(const String16& permission,\n                            int32_t* outPid, int32_t* outUid);\nbool checkPermission(const String16& permission, pid_t pid, uid_t uid);\n\n\n// ----------------------------------------------------------------------\n\nclass BnServiceManager : public BnInterface<IServiceManager>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_ISERVICE_MANAGER_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/MemoryBase.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_MEMORY_BASE_H\n#define ANDROID_MEMORY_BASE_H\n\n#include <stdlib.h>\n#include <stdint.h>\n\n#include <binder/IMemory.h>\n\n\nnamespace android {\n\n// ---------------------------------------------------------------------------\n\nclass MemoryBase : public BnMemory \n{\npublic:\n    MemoryBase(const sp<IMemoryHeap>& heap, ssize_t offset, size_t size);\n    virtual ~MemoryBase();\n    virtual sp<IMemoryHeap> getMemory(ssize_t* offset, size_t* size) const;\n\nprotected:\n    size_t getSize() const { return mSize; }\n    ssize_t getOffset() const { return mOffset; }\n    const sp<IMemoryHeap>& getHeap() const { return mHeap; }\n\nprivate:\n    size_t          mSize;\n    ssize_t         mOffset;\n    sp<IMemoryHeap> mHeap;\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_MEMORY_BASE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/MemoryDealer.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_MEMORY_DEALER_H\n#define ANDROID_MEMORY_DEALER_H\n\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <binder/IMemory.h>\n#include <binder/MemoryHeapBase.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass SimpleBestFitAllocator;\n\n// ----------------------------------------------------------------------------\n\nclass MemoryDealer : public RefBase\n{\npublic:\n    MemoryDealer(size_t size, const char* name = 0,\n            uint32_t flags = 0 /* or bits such as MemoryHeapBase::READ_ONLY */ );\n\n    virtual sp<IMemory> allocate(size_t size);\n    virtual void        deallocate(size_t offset);\n    virtual void        dump(const char* what) const;\n\n    sp<IMemoryHeap> getMemoryHeap() const { return heap(); }\n\nprotected:\n    virtual ~MemoryDealer();\n\nprivate:\n    const sp<IMemoryHeap>&      heap() const;\n    SimpleBestFitAllocator*     allocator() const;\n\n    sp<IMemoryHeap>             mHeap;\n    SimpleBestFitAllocator*     mAllocator;\n};\n\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_MEMORY_DEALER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/MemoryHeapBase.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_MEMORY_HEAP_BASE_H\n#define ANDROID_MEMORY_HEAP_BASE_H\n\n#include <stdlib.h>\n#include <stdint.h>\n\n#include <binder/IMemory.h>\n\n\nnamespace android {\n\n// ---------------------------------------------------------------------------\n\nclass MemoryHeapBase : public virtual BnMemoryHeap\n{\npublic:\n    enum {\n        READ_ONLY = IMemoryHeap::READ_ONLY,\n        // memory won't be mapped locally, but will be mapped in the remote\n        // process.\n        DONT_MAP_LOCALLY = 0x00000100,\n        NO_CACHING = 0x00000200\n    };\n\n    /*\n     * maps the memory referenced by fd. but DOESN'T take ownership\n     * of the filedescriptor (it makes a copy with dup()\n     */\n    MemoryHeapBase(int fd, size_t size, uint32_t flags = 0, uint32_t offset = 0);\n\n    /*\n     * maps memory from the given device\n     */\n    MemoryHeapBase(const char* device, size_t size = 0, uint32_t flags = 0);\n\n    /*\n     * maps memory from ashmem, with the given name for debugging\n     */\n    MemoryHeapBase(size_t size, uint32_t flags = 0, char const* name = NULL);\n\n    virtual ~MemoryHeapBase();\n\n    /* implement IMemoryHeap interface */\n    virtual int         getHeapID() const;\n\n    /* virtual address of the heap. returns MAP_FAILED in case of error */\n    virtual void*       getBase() const;\n\n    virtual size_t      getSize() const;\n    virtual uint32_t    getFlags() const;\n    virtual uint32_t    getOffset() const;\n\n    const char*         getDevice() const;\n\n    /* this closes this heap -- use carefully */\n    void dispose();\n\n    /* this is only needed as a workaround, use only if you know\n     * what you are doing */\n    status_t setDevice(const char* device) {\n        if (mDevice == 0)\n            mDevice = device;\n        return mDevice ? NO_ERROR : ALREADY_EXISTS;\n    }\n\nprotected:\n            MemoryHeapBase();\n    // init() takes ownership of fd\n    status_t init(int fd, void *base, int size,\n            int flags = 0, const char* device = NULL);\n\nprivate:\n    status_t mapfd(int fd, size_t size, uint32_t offset = 0);\n\n    int         mFD;\n    size_t      mSize;\n    void*       mBase;\n    uint32_t    mFlags;\n    const char* mDevice;\n    bool        mNeedUnmap;\n    uint32_t    mOffset;\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_MEMORY_HEAP_BASE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/MemoryHeapIon.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n * Copyright 2011, Samsung Electronics Co. LTD\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n/*!\n * \\file MemoryHeapIon.h\n * \\brief header file for MemoryHeapIon\n * \\author MinGu, Jeon(mingu85.jeon)\n * \\date 2011/11/20\n *\n * <b>Revision History: </b>\n * - 2011/11/21 : MinGu, Jeon(mingu85.jeon)) \\n\n * Initial version\n * - 2012/11/29 : MinGu, Jeon(mingu85.jeon)) \\n\n * Change name\n */\n\n#ifndef ANDROID_MEMORY_HEAP_ION_H\n#define ANDROID_MEMORY_HEAP_ION_H\n\n#include <binder/IMemory.h>\n#include <binder/MemoryHeapBase.h>\n#include <stdlib.h>\n\n#define MHB_ION_HEAP_SYSTEM_CONTIG_MASK     (1 << 1)\n#define MHB_ION_HEAP_EXYNOS_CONTIG_MASK     (1 << 4)\n#define MHB_ION_HEAP_EXYNOS_MASK            (1 << 5)\n#define MHB_ION_HEAP_SYSTEM_MASK            (1 << 6)\n\n#define MHB_ION_FLAG_CACHED                 (1 << 16)\n#define MHB_ION_FLAG_CACHED_NEEDS_SYNC      (1 << 17)\n#define MHB_ION_FLAG_PRESERVE_KMAP          (1 << 18)\n\n#define MHB_ION_EXYNOS_VIDEO_MASK           (1 << 21)\n#define MHB_ION_EXYNOS_MFC_INPUT_MASK       (1 << 25)\n#define MHB_ION_EXYNOS_MFC_OUTPUT_MASK      (1 << 26)\n#define MHB_ION_EXYNOS_GSC_MASK             (1 << 27)\n#define MHB_ION_EXYNOS_FIMD_VIDEO_MASK      (1 << 28)\n\nnamespace android {\n\nclass MemoryHeapIon : public MemoryHeapBase\n{\npublic:\n    enum {\n        USE_ION_FD = IMemoryHeap::USE_ION_FD\n    };\n    MemoryHeapIon(size_t size, uint32_t flags = 0, char const* name = NULL);\n    MemoryHeapIon(int fd, size_t size, uint32_t flags = 0, uint32_t offset = 0);\n    ~MemoryHeapIon();\nprivate:\n    int mIonClient;\n};\n\n};\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/Parcel.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_PARCEL_H\n#define ANDROID_PARCEL_H\n\n#include <cutils/native_handle.h>\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <utils/String16.h>\n#include <utils/Vector.h>\n#include <utils/Flattenable.h>\n#include <linux/binder.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\ntemplate <typename T> class Flattenable;\ntemplate <typename T> class LightFlattenable;\nclass IBinder;\nclass IPCThreadState;\nclass ProcessState;\nclass String8;\nclass TextOutput;\n\nclass Parcel {\n    friend class IPCThreadState;\npublic:\n    class ReadableBlob;\n    class WritableBlob;\n\n                        Parcel();\n                        ~Parcel();\n    \n    const uint8_t*      data() const;\n    size_t              dataSize() const;\n    size_t              dataAvail() const;\n    size_t              dataPosition() const;\n    size_t              dataCapacity() const;\n\n    status_t            setDataSize(size_t size);\n    void                setDataPosition(size_t pos) const;\n    status_t            setDataCapacity(size_t size);\n    \n    status_t            setData(const uint8_t* buffer, size_t len);\n\n    status_t            appendFrom(const Parcel *parcel,\n                                   size_t start, size_t len);\n\n    bool                allowFds() const;\n    bool                pushAllowFds(bool allowFds);\n    void                restoreAllowFds(bool lastValue);\n\n    bool                hasFileDescriptors() const;\n\n    // Writes the RPC header.\n    status_t            writeInterfaceToken(const String16& interface);\n\n    // Parses the RPC header, returning true if the interface name\n    // in the header matches the expected interface from the caller.\n    //\n    // Additionally, enforceInterface does part of the work of\n    // propagating the StrictMode policy mask, populating the current\n    // IPCThreadState, which as an optimization may optionally be\n    // passed in.\n    bool                enforceInterface(const String16& interface,\n                                         IPCThreadState* threadState = NULL) const;\n    bool                checkInterface(IBinder*) const;\n\n    void                freeData();\n\nprivate:\n    const binder_size_t* objects() const;\n\npublic:\n    size_t              objectsCount() const;\n    \n    status_t            errorCheck() const;\n    void                setError(status_t err);\n    \n    status_t            write(const void* data, size_t len);\n    void*               writeInplace(size_t len);\n    status_t            writeUnpadded(const void* data, size_t len);\n    status_t            writeInt32(int32_t val);\n    status_t            writeUint32(uint32_t val);\n    status_t            writeInt64(int64_t val);\n    status_t            writeUint64(uint64_t val);\n    status_t            writeFloat(float val);\n    status_t            writeDouble(double val);\n    status_t            writeCString(const char* str);\n    status_t            writeString8(const String8& str);\n    status_t            writeString16(const String16& str);\n    status_t            writeString16(const char16_t* str, size_t len);\n    status_t            writeStrongBinder(const sp<IBinder>& val);\n    status_t            writeWeakBinder(const wp<IBinder>& val);\n    status_t            writeInt32Array(size_t len, const int32_t *val);\n    status_t            writeByteArray(size_t len, const uint8_t *val);\n\n    template<typename T>\n    status_t            write(const Flattenable<T>& val);\n\n    template<typename T>\n    status_t            write(const LightFlattenable<T>& val);\n\n\n    // Place a native_handle into the parcel (the native_handle's file-\n    // descriptors are dup'ed, so it is safe to delete the native_handle\n    // when this function returns). \n    // Doesn't take ownership of the native_handle.\n    status_t            writeNativeHandle(const native_handle* handle);\n    \n    // Place a file descriptor into the parcel.  The given fd must remain\n    // valid for the lifetime of the parcel.\n    // The Parcel does not take ownership of the given fd unless you ask it to.\n    status_t            writeFileDescriptor(int fd, bool takeOwnership = false);\n    \n    // Place a file descriptor into the parcel.  A dup of the fd is made, which\n    // will be closed once the parcel is destroyed.\n    status_t            writeDupFileDescriptor(int fd);\n\n    // Writes a blob to the parcel.\n    // If the blob is small, then it is stored in-place, otherwise it is\n    // transferred by way of an anonymous shared memory region.  Prefer sending\n    // immutable blobs if possible since they may be subsequently transferred between\n    // processes without further copying whereas mutable blobs always need to be copied.\n    // The caller should call release() on the blob after writing its contents.\n    status_t            writeBlob(size_t len, bool mutableCopy, WritableBlob* outBlob);\n\n    // Write an existing immutable blob file descriptor to the parcel.\n    // This allows the client to send the same blob to multiple processes\n    // as long as it keeps a dup of the blob file descriptor handy for later.\n    status_t            writeDupImmutableBlobFileDescriptor(int fd);\n\n    status_t            writeObject(const flat_binder_object& val, bool nullMetaData);\n\n    // Like Parcel.java's writeNoException().  Just writes a zero int32.\n    // Currently the native implementation doesn't do any of the StrictMode\n    // stack gathering and serialization that the Java implementation does.\n    status_t            writeNoException();\n\n    void                remove(size_t start, size_t amt);\n    \n    status_t            read(void* outData, size_t len) const;\n    const void*         readInplace(size_t len) const;\n    int32_t             readInt32() const;\n    status_t            readInt32(int32_t *pArg) const;\n    uint32_t            readUint32() const;\n    status_t            readUint32(uint32_t *pArg) const;\n    int64_t             readInt64() const;\n    status_t            readInt64(int64_t *pArg) const;\n    uint64_t            readUint64() const;\n    status_t            readUint64(uint64_t *pArg) const;\n    float               readFloat() const;\n    status_t            readFloat(float *pArg) const;\n    double              readDouble() const;\n    status_t            readDouble(double *pArg) const;\n    intptr_t            readIntPtr() const;\n    status_t            readIntPtr(intptr_t *pArg) const;\n\n    const char*         readCString() const;\n    String8             readString8() const;\n    String16            readString16() const;\n    const char16_t*     readString16Inplace(size_t* outLen) const;\n    sp<IBinder>         readStrongBinder() const;\n    wp<IBinder>         readWeakBinder() const;\n\n    template<typename T>\n    status_t            read(Flattenable<T>& val) const;\n\n    template<typename T>\n    status_t            read(LightFlattenable<T>& val) const;\n\n    // Like Parcel.java's readExceptionCode().  Reads the first int32\n    // off of a Parcel's header, returning 0 or the negative error\n    // code on exceptions, but also deals with skipping over rich\n    // response headers.  Callers should use this to read & parse the\n    // response headers rather than doing it by hand.\n    int32_t             readExceptionCode() const;\n\n    // Retrieve native_handle from the parcel. This returns a copy of the\n    // parcel's native_handle (the caller takes ownership). The caller\n    // must free the native_handle with native_handle_close() and \n    // native_handle_delete().\n    native_handle*     readNativeHandle() const;\n\n    \n    // Retrieve a file descriptor from the parcel.  This returns the raw fd\n    // in the parcel, which you do not own -- use dup() to get your own copy.\n    int                 readFileDescriptor() const;\n\n    // Reads a blob from the parcel.\n    // The caller should call release() on the blob after reading its contents.\n    status_t            readBlob(size_t len, ReadableBlob* outBlob) const;\n\n    const flat_binder_object* readObject(bool nullMetaData) const;\n\n    // Explicitly close all file descriptors in the parcel.\n    void                closeFileDescriptors();\n\n    // Debugging: get metrics on current allocations.\n    static size_t       getGlobalAllocSize();\n    static size_t       getGlobalAllocCount();\n\nprivate:\n    typedef void        (*release_func)(Parcel* parcel,\n                                        const uint8_t* data, size_t dataSize,\n                                        const binder_size_t* objects, size_t objectsSize,\n                                        void* cookie);\n                        \n    uintptr_t           ipcData() const;\n    size_t              ipcDataSize() const;\n    uintptr_t           ipcObjects() const;\n    size_t              ipcObjectsCount() const;\n    void                ipcSetDataReference(const uint8_t* data, size_t dataSize,\n                                            const binder_size_t* objects, size_t objectsCount,\n                                            release_func relFunc, void* relCookie);\n    \npublic:\n    void                print(TextOutput& to, uint32_t flags = 0) const;\n\nprivate:\n                        Parcel(const Parcel& o);\n    Parcel&             operator=(const Parcel& o);\n    \n    status_t            finishWrite(size_t len);\n    void                releaseObjects();\n    void                acquireObjects();\n    status_t            growData(size_t len);\n    status_t            restartWrite(size_t desired);\n    status_t            continueWrite(size_t desired);\n    status_t            writePointer(uintptr_t val);\n    status_t            readPointer(uintptr_t *pArg) const;\n    uintptr_t           readPointer() const;\n    void                freeDataNoInit();\n    void                initState();\n    void                scanForFds() const;\n                        \n    template<class T>\n    status_t            readAligned(T *pArg) const;\n\n    template<class T>   T readAligned() const;\n\n    template<class T>\n    status_t            writeAligned(T val);\n\n    status_t            mError;\n    uint8_t*            mData;\n    size_t              mDataSize;\n    size_t              mDataCapacity;\n    mutable size_t      mDataPos;\n    binder_size_t*      mObjects;\n    size_t              mObjectsSize;\n    size_t              mObjectsCapacity;\n    mutable size_t      mNextObjectHint;\n\n    mutable bool        mFdsKnown;\n    mutable bool        mHasFds;\n    bool                mAllowFds;\n    \n    release_func        mOwner;\n    void*               mOwnerCookie;\n\n    class Blob {\n    public:\n        Blob();\n        ~Blob();\n\n        void clear();\n        void release();\n        inline size_t size() const { return mSize; }\n        inline int fd() const { return mFd; };\n        inline bool isMutable() const { return mMutable; }\n\n    protected:\n        void init(int fd, void* data, size_t size, bool isMutable);\n\n        int mFd; // owned by parcel so not closed when released\n        void* mData;\n        size_t mSize;\n        bool mMutable;\n    };\n\n    class FlattenableHelperInterface {\n    protected:\n        ~FlattenableHelperInterface() { }\n    public:\n        virtual size_t getFlattenedSize() const = 0;\n        virtual size_t getFdCount() const = 0;\n        virtual status_t flatten(void* buffer, size_t size, int* fds, size_t count) const = 0;\n        virtual status_t unflatten(void const* buffer, size_t size, int const* fds, size_t count) = 0;\n    };\n\n    template<typename T>\n    class FlattenableHelper : public FlattenableHelperInterface {\n        friend class Parcel;\n        const Flattenable<T>& val;\n        explicit FlattenableHelper(const Flattenable<T>& val) : val(val) { }\n\n    public:\n        virtual size_t getFlattenedSize() const {\n            return val.getFlattenedSize();\n        }\n        virtual size_t getFdCount() const {\n            return val.getFdCount();\n        }\n        virtual status_t flatten(void* buffer, size_t size, int* fds, size_t count) const {\n            return val.flatten(buffer, size, fds, count);\n        }\n        virtual status_t unflatten(void const* buffer, size_t size, int const* fds, size_t count) {\n            return const_cast<Flattenable<T>&>(val).unflatten(buffer, size, fds, count);\n        }\n    };\n    status_t write(const FlattenableHelperInterface& val);\n    status_t read(FlattenableHelperInterface& val) const;\n\npublic:\n    class ReadableBlob : public Blob {\n        friend class Parcel;\n    public:\n        inline const void* data() const { return mData; }\n        inline void* mutableData() { return isMutable() ? mData : NULL; }\n    };\n\n    class WritableBlob : public Blob {\n        friend class Parcel;\n    public:\n        inline void* data() { return mData; }\n    };\n\n#ifndef DISABLE_ASHMEM_TRACKING\nprivate:\n    size_t mOpenAshmemSize;\n#endif\n\npublic:\n    // TODO: Remove once ABI can be changed.\n    size_t getBlobAshmemSize() const;\n    size_t getOpenAshmemSize() const;\n};\n\n// ---------------------------------------------------------------------------\n\ntemplate<typename T>\nstatus_t Parcel::write(const Flattenable<T>& val) {\n    const FlattenableHelper<T> helper(val);\n    return write(helper);\n}\n\ntemplate<typename T>\nstatus_t Parcel::write(const LightFlattenable<T>& val) {\n    size_t size(val.getFlattenedSize());\n    if (!val.isFixedSize()) {\n        status_t err = writeInt32(size);\n        if (err != NO_ERROR) {\n            return err;\n        }\n    }\n    if (size) {\n        void* buffer = writeInplace(size);\n        if (buffer == NULL)\n            return NO_MEMORY;\n        return val.flatten(buffer, size);\n    }\n    return NO_ERROR;\n}\n\ntemplate<typename T>\nstatus_t Parcel::read(Flattenable<T>& val) const {\n    FlattenableHelper<T> helper(val);\n    return read(helper);\n}\n\ntemplate<typename T>\nstatus_t Parcel::read(LightFlattenable<T>& val) const {\n    size_t size;\n    if (val.isFixedSize()) {\n        size = val.getFlattenedSize();\n    } else {\n        int32_t s;\n        status_t err = readInt32(&s);\n        if (err != NO_ERROR) {\n            return err;\n        }\n        size = s;\n    }\n    if (size) {\n        void const* buffer = readInplace(size);\n        return buffer == NULL ? NO_MEMORY :\n                val.unflatten(buffer, size);\n    }\n    return NO_ERROR;\n}\n\n// ---------------------------------------------------------------------------\n\ninline TextOutput& operator<<(TextOutput& to, const Parcel& parcel)\n{\n    parcel.print(to);\n    return to;\n}\n\n// ---------------------------------------------------------------------------\n\n// Generic acquire and release of objects.\nvoid acquire_object(const sp<ProcessState>& proc,\n                    const flat_binder_object& obj, const void* who);\nvoid release_object(const sp<ProcessState>& proc,\n                    const flat_binder_object& obj, const void* who);\n\nvoid flatten_binder(const sp<ProcessState>& proc,\n                    const sp<IBinder>& binder, flat_binder_object* out);\nvoid flatten_binder(const sp<ProcessState>& proc,\n                    const wp<IBinder>& binder, flat_binder_object* out);\nstatus_t unflatten_binder(const sp<ProcessState>& proc,\n                          const flat_binder_object& flat, sp<IBinder>* out);\nstatus_t unflatten_binder(const sp<ProcessState>& proc,\n                          const flat_binder_object& flat, wp<IBinder>* out);\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_PARCEL_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/PermissionCache.h",
    "content": "/*\n * Copyright (C) 2009 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef BINDER_PERMISSION_H\n#define BINDER_PERMISSION_H\n\n#include <stdint.h>\n#include <unistd.h>\n\n#include <utils/String16.h>\n#include <utils/Singleton.h>\n#include <utils/SortedVector.h>\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\n/*\n * PermissionCache caches permission checks for a given uid.\n *\n * Currently the cache is not updated when there is a permission change,\n * for instance when an application is uninstalled.\n *\n * IMPORTANT: for the reason stated above, only system permissions are safe\n * to cache. This restriction may be lifted at a later time.\n *\n */\n\nclass PermissionCache : Singleton<PermissionCache> {\n    struct Entry {\n        String16    name;\n        uid_t       uid;\n        bool        granted;\n        inline bool operator < (const Entry& e) const {\n            return (uid == e.uid) ? (name < e.name) : (uid < e.uid);\n        }\n    };\n    mutable Mutex mLock;\n    // we pool all the permission names we see, as many permissions checks\n    // will have identical names\n    SortedVector< String16 > mPermissionNamesPool;\n    // this is our cache per say. it stores pooled names.\n    SortedVector< Entry > mCache;\n\n    // free the whole cache, but keep the permission name pool\n    void purge();\n\n    status_t check(bool* granted,\n            const String16& permission, uid_t uid) const;\n\n    void cache(const String16& permission, uid_t uid, bool granted);\n\npublic:\n    PermissionCache();\n\n    static bool checkCallingPermission(const String16& permission);\n\n    static bool checkCallingPermission(const String16& permission,\n                                int32_t* outPid, int32_t* outUid);\n\n    static bool checkPermission(const String16& permission,\n            pid_t pid, uid_t uid);\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif /* BINDER_PERMISSION_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/ProcessInfoService.h",
    "content": "/*\n * Copyright 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_PROCESS_INFO_SERVICE_H\n#define ANDROID_PROCESS_INFO_SERVICE_H\n\n#include <binder/IProcessInfoService.h>\n#include <utils/Errors.h>\n#include <utils/Singleton.h>\n#include <sys/types.h>\n\nnamespace android {\n\n// ----------------------------------------------------------------------\n\nclass ProcessInfoService : public Singleton<ProcessInfoService> {\n\n    friend class Singleton<ProcessInfoService>;\n    sp<IProcessInfoService> mProcessInfoService;\n    Mutex mProcessInfoLock;\n\n    ProcessInfoService();\n\n    status_t getProcessStatesImpl(size_t length, /*in*/ int32_t* pids, /*out*/ int32_t* states);\n    void updateBinderLocked();\n\n    static const int BINDER_ATTEMPT_LIMIT = 5;\n\npublic:\n\n    /**\n     * For each PID in the given \"pids\" input array, write the current process state\n     * for that process into the \"states\" output array, or\n     * ActivityManager.PROCESS_STATE_NONEXISTENT * to indicate that no process with the given PID\n     * exists.\n     *\n     * Returns NO_ERROR if this operation was successful, or a negative error code otherwise.\n     */\n    static status_t getProcessStatesFromPids(size_t length, /*in*/ int32_t* pids,\n            /*out*/ int32_t* states) {\n        return ProcessInfoService::getInstance().getProcessStatesImpl(length, /*in*/ pids,\n                /*out*/ states);\n    }\n\n};\n\n// ----------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_PROCESS_INFO_SERVICE_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/ProcessState.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_PROCESS_STATE_H\n#define ANDROID_PROCESS_STATE_H\n\n#include <binder/IBinder.h>\n#include <utils/KeyedVector.h>\n#include <utils/String8.h>\n#include <utils/String16.h>\n\n#include <utils/threads.h>\n\n#include <pthread.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass IPCThreadState;\n\nclass ProcessState : public virtual RefBase\n{\npublic:\n    static  sp<ProcessState>    self();\n\n            void                setContextObject(const sp<IBinder>& object);\n            sp<IBinder>         getContextObject(const sp<IBinder>& caller);\n        \n            void                setContextObject(const sp<IBinder>& object,\n                                                 const String16& name);\n            sp<IBinder>         getContextObject(const String16& name,\n                                                 const sp<IBinder>& caller);\n\n            void                startThreadPool();\n                        \n    typedef bool (*context_check_func)(const String16& name,\n                                       const sp<IBinder>& caller,\n                                       void* userData);\n        \n            bool                isContextManager(void) const;\n            bool                becomeContextManager(\n                                    context_check_func checkFunc,\n                                    void* userData);\n\n            sp<IBinder>         getStrongProxyForHandle(int32_t handle);\n            wp<IBinder>         getWeakProxyForHandle(int32_t handle);\n            void                expungeHandle(int32_t handle, IBinder* binder);\n\n            void                spawnPooledThread(bool isMain);\n            \n            status_t            setThreadPoolMaxThreadCount(size_t maxThreads);\n            void                giveThreadPoolName();\n\nprivate:\n    friend class IPCThreadState;\n    \n                                ProcessState();\n                                ~ProcessState();\n\n                                ProcessState(const ProcessState& o);\n            ProcessState&       operator=(const ProcessState& o);\n            String8             makeBinderThreadName();\n\n            struct handle_entry {\n                IBinder* binder;\n                RefBase::weakref_type* refs;\n            };\n\n            handle_entry*       lookupHandleLocked(int32_t handle);\n\n            int                 mDriverFD;\n            void*               mVMStart;\n\n            // Protects thread count variable below.\n            pthread_mutex_t     mThreadCountLock;\n            pthread_cond_t      mThreadCountDecrement;\n            // Number of binder threads current executing a command.\n            size_t              mExecutingThreadsCount;\n            // Maximum number for binder threads allowed for this process.\n            size_t              mMaxThreads;\n\n    mutable Mutex               mLock;  // protects everything below.\n\n            Vector<handle_entry>mHandleToObject;\n\n            bool                mManagesContexts;\n            context_check_func  mBinderContextCheckFunc;\n            void*               mBinderContextUserData;\n\n            KeyedVector<String16, sp<IBinder> >\n                                mContexts;\n\n\n            String8             mRootDir;\n            bool                mThreadPoolStarted;\n    volatile int32_t            mThreadPoolSeq;\n};\n    \n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_PROCESS_STATE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/binder/TextOutput.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_TEXTOUTPUT_H\n#define ANDROID_TEXTOUTPUT_H\n\n#include <utils/Errors.h>\n\n#include <stdint.h>\n#include <string.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass String8;\nclass String16;\n\nclass TextOutput\n{\npublic:\n                        TextOutput();\n    virtual             ~TextOutput();\n    \n    virtual status_t    print(const char* txt, size_t len) = 0;\n    virtual void        moveIndent(int delta) = 0;\n    \n    class Bundle {\n    public:\n        inline Bundle(TextOutput& to) : mTO(to) { to.pushBundle(); }\n        inline ~Bundle() { mTO.popBundle(); }\n    private:\n        TextOutput&     mTO;\n    };\n    \n    virtual void        pushBundle() = 0;\n    virtual void        popBundle() = 0;\n};\n\n// ---------------------------------------------------------------------------\n\n// Text output stream for printing to the log (via utils/Log.h).\nextern TextOutput& alog;\n\n// Text output stream for printing to stdout.\nextern TextOutput& aout;\n\n// Text output stream for printing to stderr.\nextern TextOutput& aerr;\n\ntypedef TextOutput& (*TextOutputManipFunc)(TextOutput&);\n\nTextOutput& endl(TextOutput& to);\nTextOutput& indent(TextOutput& to);\nTextOutput& dedent(TextOutput& to);\n\nTextOutput& operator<<(TextOutput& to, const char* str);\nTextOutput& operator<<(TextOutput& to, char);     // writes raw character\nTextOutput& operator<<(TextOutput& to, bool);\nTextOutput& operator<<(TextOutput& to, int);\nTextOutput& operator<<(TextOutput& to, long);\nTextOutput& operator<<(TextOutput& to, unsigned int);\nTextOutput& operator<<(TextOutput& to, unsigned long);\nTextOutput& operator<<(TextOutput& to, long long);\nTextOutput& operator<<(TextOutput& to, unsigned long long);\nTextOutput& operator<<(TextOutput& to, float);\nTextOutput& operator<<(TextOutput& to, double);\nTextOutput& operator<<(TextOutput& to, TextOutputManipFunc func);\nTextOutput& operator<<(TextOutput& to, const void*);\nTextOutput& operator<<(TextOutput& to, const String8& val);\nTextOutput& operator<<(TextOutput& to, const String16& val);\n\nclass TypeCode \n{\npublic:\n    inline TypeCode(uint32_t code);\n    inline ~TypeCode();\n\n    inline uint32_t typeCode() const;\n    \nprivate:\n    uint32_t mCode;\n};\n\nTextOutput& operator<<(TextOutput& to, const TypeCode& val);\n\nclass HexDump\n{\npublic:\n    HexDump(const void *buf, size_t size, size_t bytesPerLine=16);\n    inline ~HexDump();\n    \n    inline HexDump& setBytesPerLine(size_t bytesPerLine);\n    inline HexDump& setSingleLineCutoff(int32_t bytes);\n    inline HexDump& setAlignment(size_t alignment);\n    inline HexDump& setCArrayStyle(bool enabled);\n    \n    inline const void* buffer() const;\n    inline size_t size() const;\n    inline size_t bytesPerLine() const;\n    inline int32_t singleLineCutoff() const;\n    inline size_t alignment() const;\n    inline bool carrayStyle() const;\n\nprivate:\n    const void* mBuffer;\n    size_t mSize;\n    size_t mBytesPerLine;\n    int32_t mSingleLineCutoff;\n    size_t mAlignment;\n    bool mCArrayStyle;\n};\n\nTextOutput& operator<<(TextOutput& to, const HexDump& val);\n\n// ---------------------------------------------------------------------------\n// No user servicable parts below.\n\ninline TextOutput& endl(TextOutput& to)\n{\n    to.print(\"\\n\", 1);\n    return to;\n}\n\ninline TextOutput& indent(TextOutput& to)\n{\n    to.moveIndent(1);\n    return to;\n}\n\ninline TextOutput& dedent(TextOutput& to)\n{\n    to.moveIndent(-1);\n    return to;\n}\n\ninline TextOutput& operator<<(TextOutput& to, const char* str)\n{\n    to.print(str, strlen(str));\n    return to;\n}\n\ninline TextOutput& operator<<(TextOutput& to, char c)\n{\n    to.print(&c, 1);\n    return to;\n}\n\ninline TextOutput& operator<<(TextOutput& to, TextOutputManipFunc func)\n{\n    return (*func)(to);\n}\n\ninline TypeCode::TypeCode(uint32_t code) : mCode(code) { }\ninline TypeCode::~TypeCode() { }\ninline uint32_t TypeCode::typeCode() const { return mCode; }\n\ninline HexDump::~HexDump() { }\n\ninline HexDump& HexDump::setBytesPerLine(size_t bytesPerLine) {\n    mBytesPerLine = bytesPerLine; return *this;\n}\ninline HexDump& HexDump::setSingleLineCutoff(int32_t bytes) {\n    mSingleLineCutoff = bytes; return *this;\n}\ninline HexDump& HexDump::setAlignment(size_t alignment) {\n    mAlignment = alignment; return *this;\n}\ninline HexDump& HexDump::setCArrayStyle(bool enabled) {\n    mCArrayStyle = enabled; return *this;\n}\n\ninline const void* HexDump::buffer() const { return mBuffer; }\ninline size_t HexDump::size() const { return mSize; }\ninline size_t HexDump::bytesPerLine() const { return mBytesPerLine; }\ninline int32_t HexDump::singleLineCutoff() const { return mSingleLineCutoff; }\ninline size_t HexDump::alignment() const { return mAlignment; }\ninline bool HexDump::carrayStyle() const { return mCArrayStyle; }\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_TEXTOUTPUT_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BitTube.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_SENSOR_CHANNEL_H\n#define ANDROID_GUI_SENSOR_CHANNEL_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <cutils/log.h>\n\n\nnamespace android {\n// ----------------------------------------------------------------------------\nclass Parcel;\n\nclass BitTube : public RefBase\n{\npublic:\n\n    // creates a BitTube with a default (4KB) send buffer\n    BitTube();\n\n    // creates a BitTube with a a specified send and receive buffer size\n    explicit BitTube(size_t bufsize);\n\n    explicit BitTube(const Parcel& data);\n    virtual ~BitTube();\n\n    // check state after construction\n    status_t initCheck() const;\n\n    // get receive file-descriptor\n    int getFd() const;\n\n    // get the send file-descriptor.\n    int getSendFd() const;\n\n    // send objects (sized blobs). All objects are guaranteed to be written or the call fails.\n    template <typename T>\n    static ssize_t sendObjects(const sp<BitTube>& tube,\n            T const* events, size_t count) {\n        return sendObjects(tube, events, count, sizeof(T));\n    }\n\n    // receive objects (sized blobs). If the receiving buffer isn't large enough,\n    // excess messages are silently discarded.\n    template <typename T>\n    static ssize_t recvObjects(const sp<BitTube>& tube,\n            T* events, size_t count) {\n        return recvObjects(tube, events, count, sizeof(T));\n    }\n\n    // parcels this BitTube\n    status_t writeToParcel(Parcel* reply) const;\n\nprivate:\n    void init(size_t rcvbuf, size_t sndbuf);\n\n    // send a message. The write is guaranteed to send the whole message or fail.\n    ssize_t write(void const* vaddr, size_t size);\n\n    // receive a message. the passed buffer must be at least as large as the\n    // write call used to send the message, excess data is silently discarded.\n    ssize_t read(void* vaddr, size_t size);\n\n    int mSendFd;\n    mutable int mReceiveFd;\n\n    static ssize_t sendObjects(const sp<BitTube>& tube,\n            void const* events, size_t count, size_t objSize);\n\n    static ssize_t recvObjects(const sp<BitTube>& tube,\n            void* events, size_t count, size_t objSize);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_SENSOR_CHANNEL_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferItem.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERITEM_H\n#define ANDROID_GUI_BUFFERITEM_H\n\n#include <EGL/egl.h>\n#include <EGL/eglext.h>\n\n#include <ui/Rect.h>\n#include <ui/Region.h>\n\n#include <system/graphics.h>\n\n#include <utils/Flattenable.h>\n#include <utils/StrongPointer.h>\n\nnamespace android {\n\nclass Fence;\nclass GraphicBuffer;\n\nclass BufferItem : public Flattenable<BufferItem> {\n    friend class Flattenable<BufferItem>;\n    size_t getPodSize() const;\n    size_t getFlattenedSize() const;\n    size_t getFdCount() const;\n    status_t flatten(void*& buffer, size_t& size, int*& fds, size_t& count) const;\n    status_t unflatten(void const*& buffer, size_t& size, int const*& fds, size_t& count);\n\n    public:\n    // The default value of mBuf, used to indicate this doesn't correspond to a slot.\n    enum { INVALID_BUFFER_SLOT = -1 };\n    BufferItem();\n    ~BufferItem();\n\n    static const char* scalingModeName(uint32_t scalingMode);\n\n    // mGraphicBuffer points to the buffer allocated for this slot, or is NULL\n    // if the buffer in this slot has been acquired in the past (see\n    // BufferSlot.mAcquireCalled).\n    sp<GraphicBuffer> mGraphicBuffer;\n\n    // mFence is a fence that will signal when the buffer is idle.\n    sp<Fence> mFence;\n\n    // mCrop is the current crop rectangle for this buffer slot.\n    Rect mCrop;\n\n    // mTransform is the current transform flags for this buffer slot.\n    // refer to NATIVE_WINDOW_TRANSFORM_* in <window.h>\n    uint32_t mTransform;\n\n    // mScalingMode is the current scaling mode for this buffer slot.\n    // refer to NATIVE_WINDOW_SCALING_* in <window.h>\n    uint32_t mScalingMode;\n\n    // mTimestamp is the current timestamp for this buffer slot. This gets\n    // to set by queueBuffer each time this slot is queued. This value\n    // is guaranteed to be monotonically increasing for each newly\n    // acquired buffer.\n    union {\n        int64_t mTimestamp;\n        struct {\n            uint32_t mTimestampLo;\n            uint32_t mTimestampHi;\n        };\n    };\n\n    // mIsAutoTimestamp indicates whether mTimestamp was generated\n    // automatically when the buffer was queued.\n    bool mIsAutoTimestamp;\n\n    // mDataSpace is the current dataSpace value for this buffer slot. This gets\n    // set by queueBuffer each time this slot is queued. The meaning of the\n    // dataSpace is format-dependent.\n    android_dataspace mDataSpace;\n\n    // mFrameNumber is the number of the queued frame for this slot.\n    union {\n        uint64_t mFrameNumber;\n        struct {\n            uint32_t mFrameNumberLo;\n            uint32_t mFrameNumberHi;\n        };\n    };\n\n    union {\n        // mSlot is the slot index of this buffer (default INVALID_BUFFER_SLOT).\n        int mSlot;\n\n        // mBuf is the former name for mSlot\n        int mBuf;\n    };\n\n    // mIsDroppable whether this buffer was queued with the\n    // property that it can be replaced by a new buffer for the purpose of\n    // making sure dequeueBuffer() won't block.\n    // i.e.: was the BufferQueue in \"mDequeueBufferCannotBlock\" when this buffer\n    // was queued.\n    bool mIsDroppable;\n\n    // Indicates whether this buffer has been seen by a consumer yet\n    bool mAcquireCalled;\n\n    // Indicates this buffer must be transformed by the inverse transform of the screen\n    // it is displayed onto. This is applied after mTransform.\n    bool mTransformToDisplayInverse;\n\n    // Describes the portion of the surface that has been modified since the\n    // previous frame\n    Region mSurfaceDamage;\n};\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferItemConsumer.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERITEMCONSUMER_H\n#define ANDROID_GUI_BUFFERITEMCONSUMER_H\n\n#include <gui/ConsumerBase.h>\n\n#include <ui/GraphicBuffer.h>\n\n#include <utils/String8.h>\n#include <utils/Vector.h>\n#include <utils/threads.h>\n\n#define ANDROID_GRAPHICS_BUFFERITEMCONSUMER_JNI_ID \"mBufferItemConsumer\"\n\nnamespace android {\n\nclass BufferQueue;\n\n/**\n * BufferItemConsumer is a BufferQueue consumer endpoint that allows clients\n * access to the whole BufferItem entry from BufferQueue. Multiple buffers may\n * be acquired at once, to be used concurrently by the client. This consumer can\n * operate either in synchronous or asynchronous mode.\n */\nclass BufferItemConsumer: public ConsumerBase\n{\n  public:\n    typedef ConsumerBase::FrameAvailableListener FrameAvailableListener;\n\n    enum { DEFAULT_MAX_BUFFERS = -1 };\n    enum { INVALID_BUFFER_SLOT = BufferQueue::INVALID_BUFFER_SLOT };\n    enum { NO_BUFFER_AVAILABLE = BufferQueue::NO_BUFFER_AVAILABLE };\n\n    // Create a new buffer item consumer. The consumerUsage parameter determines\n    // the consumer usage flags passed to the graphics allocator. The\n    // bufferCount parameter specifies how many buffers can be locked for user\n    // access at the same time.\n    // controlledByApp tells whether this consumer is controlled by the\n    // application.\n    BufferItemConsumer(const sp<IGraphicBufferConsumer>& consumer,\n            uint32_t consumerUsage, int bufferCount = DEFAULT_MAX_BUFFERS,\n            bool controlledByApp = false);\n\n    virtual ~BufferItemConsumer();\n\n    // set the name of the BufferItemConsumer that will be used to identify it in\n    // log messages.\n    void setName(const String8& name);\n\n    // Gets the next graphics buffer from the producer, filling out the\n    // passed-in BufferItem structure. Returns NO_BUFFER_AVAILABLE if the queue\n    // of buffers is empty, and INVALID_OPERATION if the maximum number of\n    // buffers is already acquired.\n    //\n    // Only a fixed number of buffers can be acquired at a time, determined by\n    // the construction-time bufferCount parameter. If INVALID_OPERATION is\n    // returned by acquireBuffer, then old buffers must be returned to the\n    // queue by calling releaseBuffer before more buffers can be acquired.\n    //\n    // If waitForFence is true, and the acquired BufferItem has a valid fence object,\n    // acquireBuffer will wait on the fence with no timeout before returning.\n    status_t acquireBuffer(BufferItem* item, nsecs_t presentWhen,\n            bool waitForFence = true);\n\n    // Returns an acquired buffer to the queue, allowing it to be reused. Since\n    // only a fixed number of buffers may be acquired at a time, old buffers\n    // must be released by calling releaseBuffer to ensure new buffers can be\n    // acquired by acquireBuffer. Once a BufferItem is released, the caller must\n    // not access any members of the BufferItem, and should immediately remove\n    // all of its references to the BufferItem itself.\n    status_t releaseBuffer(const BufferItem &item,\n            const sp<Fence>& releaseFence = Fence::NO_FENCE);\n\n};\n\n} // namespace android\n\n#endif // ANDROID_GUI_CPUCONSUMER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferQueue.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERQUEUE_H\n#define ANDROID_GUI_BUFFERQUEUE_H\n\n#include <gui/BufferItem.h>\n#include <gui/BufferQueueDefs.h>\n#include <gui/IGraphicBufferConsumer.h>\n#include <gui/IGraphicBufferProducer.h>\n#include <gui/IConsumerListener.h>\n\n// These are only required to keep other parts of the framework with incomplete\n// dependencies building successfully\n#include <gui/IGraphicBufferAlloc.h>\n\nnamespace android {\n\nclass BufferQueue {\npublic:\n    // BufferQueue will keep track of at most this value of buffers.\n    // Attempts at runtime to increase the number of buffers past this will fail.\n    enum { NUM_BUFFER_SLOTS = BufferQueueDefs::NUM_BUFFER_SLOTS };\n    // Used as a placeholder slot# when the value isn't pointing to an existing buffer.\n    enum { INVALID_BUFFER_SLOT = BufferItem::INVALID_BUFFER_SLOT };\n    // Alias to <IGraphicBufferConsumer.h> -- please scope from there in future code!\n    enum {\n        NO_BUFFER_AVAILABLE = IGraphicBufferConsumer::NO_BUFFER_AVAILABLE,\n        PRESENT_LATER = IGraphicBufferConsumer::PRESENT_LATER,\n    };\n\n    // When in async mode we reserve two slots in order to guarantee that the\n    // producer and consumer can run asynchronously.\n    enum { MAX_MAX_ACQUIRED_BUFFERS = NUM_BUFFER_SLOTS - 2 };\n\n    // for backward source compatibility\n    typedef ::android::ConsumerListener ConsumerListener;\n\n    // ProxyConsumerListener is a ConsumerListener implementation that keeps a weak\n    // reference to the actual consumer object.  It forwards all calls to that\n    // consumer object so long as it exists.\n    //\n    // This class exists to avoid having a circular reference between the\n    // BufferQueue object and the consumer object.  The reason this can't be a weak\n    // reference in the BufferQueue class is because we're planning to expose the\n    // consumer side of a BufferQueue as a binder interface, which doesn't support\n    // weak references.\n    class ProxyConsumerListener : public BnConsumerListener {\n    public:\n        ProxyConsumerListener(const wp<ConsumerListener>& consumerListener);\n        virtual ~ProxyConsumerListener();\n        virtual void onFrameAvailable(const BufferItem& item) override;\n        virtual void onFrameReplaced(const BufferItem& item) override;\n        virtual void onBuffersReleased() override;\n        virtual void onSidebandStreamChanged() override;\n    private:\n        // mConsumerListener is a weak reference to the IConsumerListener.  This is\n        // the raison d'etre of ProxyConsumerListener.\n        wp<ConsumerListener> mConsumerListener;\n    };\n\n    // BufferQueue manages a pool of gralloc memory slots to be used by\n    // producers and consumers. allocator is used to allocate all the\n    // needed gralloc buffers.\n    static void createBufferQueue(sp<IGraphicBufferProducer>* outProducer,\n            sp<IGraphicBufferConsumer>* outConsumer,\n            const sp<IGraphicBufferAlloc>& allocator = NULL);\n\nprivate:\n    BufferQueue(); // Create through createBufferQueue\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_BUFFERQUEUE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferQueueConsumer.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERQUEUECONSUMER_H\n#define ANDROID_GUI_BUFFERQUEUECONSUMER_H\n\n#include <EGL/egl.h>\n#include <EGL/eglext.h>\n\n#include <gui/BufferQueueDefs.h>\n#include <gui/IGraphicBufferConsumer.h>\n\nnamespace android {\n\nclass BufferQueueCore;\n\nclass BufferQueueConsumer : public BnGraphicBufferConsumer {\n\npublic:\n    BufferQueueConsumer(const sp<BufferQueueCore>& core);\n    virtual ~BufferQueueConsumer();\n\n    // acquireBuffer attempts to acquire ownership of the next pending buffer in\n    // the BufferQueue. If no buffer is pending then it returns\n    // NO_BUFFER_AVAILABLE. If a buffer is successfully acquired, the\n    // information about the buffer is returned in BufferItem.  If the buffer\n    // returned had previously been acquired then the BufferItem::mGraphicBuffer\n    // field of buffer is set to NULL and it is assumed that the consumer still\n    // holds a reference to the buffer.\n    //\n    // If expectedPresent is nonzero, it indicates the time when the buffer\n    // will be displayed on screen. If the buffer's timestamp is farther in the\n    // future, the buffer won't be acquired, and PRESENT_LATER will be\n    // returned.  The presentation time is in nanoseconds, and the time base\n    // is CLOCK_MONOTONIC.\n    virtual status_t acquireBuffer(BufferItem* outBuffer,\n            nsecs_t expectedPresent, uint64_t maxFrameNumber = 0) override;\n\n    // See IGraphicBufferConsumer::detachBuffer\n    virtual status_t detachBuffer(int slot);\n\n    // See IGraphicBufferConsumer::attachBuffer\n    virtual status_t attachBuffer(int* slot, const sp<GraphicBuffer>& buffer);\n\n    // releaseBuffer releases a buffer slot from the consumer back to the\n    // BufferQueue.  This may be done while the buffer's contents are still\n    // being accessed.  The fence will signal when the buffer is no longer\n    // in use. frameNumber is used to indentify the exact buffer returned.\n    //\n    // If releaseBuffer returns STALE_BUFFER_SLOT, then the consumer must free\n    // any references to the just-released buffer that it might have, as if it\n    // had received a onBuffersReleased() call with a mask set for the released\n    // buffer.\n    //\n    // Note that the dependencies on EGL will be removed once we switch to using\n    // the Android HW Sync HAL.\n    virtual status_t releaseBuffer(int slot, uint64_t frameNumber,\n            const sp<Fence>& releaseFence, EGLDisplay display,\n            EGLSyncKHR fence);\n\n    // connect connects a consumer to the BufferQueue.  Only one\n    // consumer may be connected, and when that consumer disconnects the\n    // BufferQueue is placed into the \"abandoned\" state, causing most\n    // interactions with the BufferQueue by the producer to fail.\n    // controlledByApp indicates whether the consumer is controlled by\n    // the application.\n    //\n    // consumerListener may not be NULL.\n    virtual status_t connect(const sp<IConsumerListener>& consumerListener,\n            bool controlledByApp);\n\n    // disconnect disconnects a consumer from the BufferQueue. All\n    // buffers will be freed and the BufferQueue is placed in the \"abandoned\"\n    // state, causing most interactions with the BufferQueue by the producer to\n    // fail.\n    virtual status_t disconnect();\n\n    // getReleasedBuffers sets the value pointed to by outSlotMask to a bit mask\n    // indicating which buffer slots have been released by the BufferQueue\n    // but have not yet been released by the consumer.\n    //\n    // This should be called from the onBuffersReleased() callback.\n    virtual status_t getReleasedBuffers(uint64_t* outSlotMask);\n\n    // setDefaultBufferSize is used to set the size of buffers returned by\n    // dequeueBuffer when a width and height of zero is requested.  Default\n    // is 1x1.\n    virtual status_t setDefaultBufferSize(uint32_t width, uint32_t height);\n\n    // setDefaultMaxBufferCount sets the default value for the maximum buffer\n    // count (the initial default is 2). If the producer has requested a\n    // buffer count using setBufferCount, the default buffer count will only\n    // take effect if the producer sets the count back to zero.\n    //\n    // The count must be between 2 and NUM_BUFFER_SLOTS, inclusive.\n    virtual status_t setDefaultMaxBufferCount(int bufferCount);\n\n    // disableAsyncBuffer disables the extra buffer used in async mode\n    // (when both producer and consumer have set their \"isControlledByApp\"\n    // flag) and has dequeueBuffer() return WOULD_BLOCK instead.\n    //\n    // This can only be called before connect().\n    virtual status_t disableAsyncBuffer();\n\n    // setMaxAcquiredBufferCount sets the maximum number of buffers that can\n    // be acquired by the consumer at one time (default 1).  This call will\n    // fail if a producer is connected to the BufferQueue.\n    virtual status_t setMaxAcquiredBufferCount(int maxAcquiredBuffers);\n\n    // setConsumerName sets the name used in logging\n    virtual void setConsumerName(const String8& name);\n\n    // setDefaultBufferFormat allows the BufferQueue to create\n    // GraphicBuffers of a defaultFormat if no format is specified\n    // in dequeueBuffer. The initial default is HAL_PIXEL_FORMAT_RGBA_8888.\n    virtual status_t setDefaultBufferFormat(PixelFormat defaultFormat);\n\n    // setDefaultBufferDataSpace allows the BufferQueue to create\n    // GraphicBuffers of a defaultDataSpace if no data space is specified\n    // in queueBuffer.\n    // The initial default is HAL_DATASPACE_UNKNOWN\n    virtual status_t setDefaultBufferDataSpace(\n            android_dataspace defaultDataSpace);\n\n    // setConsumerUsageBits will turn on additional usage bits for dequeueBuffer.\n    // These are merged with the bits passed to dequeueBuffer.  The values are\n    // enumerated in gralloc.h, e.g. GRALLOC_USAGE_HW_RENDER; the default is 0.\n    virtual status_t setConsumerUsageBits(uint32_t usage);\n\n    // setTransformHint bakes in rotation to buffers so overlays can be used.\n    // The values are enumerated in window.h, e.g.\n    // NATIVE_WINDOW_TRANSFORM_ROT_90.  The default is 0 (no transform).\n    virtual status_t setTransformHint(uint32_t hint);\n\n    // Retrieve the sideband buffer stream, if any.\n    virtual sp<NativeHandle> getSidebandStream() const;\n\n    // dump our state in a String\n    virtual void dump(String8& result, const char* prefix) const;\n\n    // Functions required for backwards compatibility.\n    // These will be modified/renamed in IGraphicBufferConsumer and will be\n    // removed from this class at that time. See b/13306289.\n\n    virtual status_t releaseBuffer(int buf, uint64_t frameNumber,\n            EGLDisplay display, EGLSyncKHR fence,\n            const sp<Fence>& releaseFence) {\n        return releaseBuffer(buf, frameNumber, releaseFence, display, fence);\n    }\n\n    virtual status_t consumerConnect(const sp<IConsumerListener>& consumer,\n            bool controlledByApp) {\n        return connect(consumer, controlledByApp);\n    }\n\n    virtual status_t consumerDisconnect() { return disconnect(); }\n\n    // End functions required for backwards compatibility\n\nprivate:\n    sp<BufferQueueCore> mCore;\n\n    // This references mCore->mSlots. Lock mCore->mMutex while accessing.\n    BufferQueueDefs::SlotsType& mSlots;\n\n    // This is a cached copy of the name stored in the BufferQueueCore.\n    // It's updated during setConsumerName.\n    String8 mConsumerName;\n\n}; // class BufferQueueConsumer\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferQueueCore.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERQUEUECORE_H\n#define ANDROID_GUI_BUFFERQUEUECORE_H\n\n#include <gui/BufferItem.h>\n#include <gui/BufferQueueDefs.h>\n#include <gui/BufferSlot.h>\n\n#include <utils/Condition.h>\n#include <utils/Mutex.h>\n#include <utils/NativeHandle.h>\n#include <utils/RefBase.h>\n#include <utils/String8.h>\n#include <utils/StrongPointer.h>\n#include <utils/Trace.h>\n#include <utils/Vector.h>\n\n#include <list>\n#include <set>\n\n#define BQ_LOGV(x, ...) ALOGV(\"[%s] \" x, mConsumerName.string(), ##__VA_ARGS__)\n#define BQ_LOGD(x, ...) ALOGD(\"[%s] \" x, mConsumerName.string(), ##__VA_ARGS__)\n#define BQ_LOGI(x, ...) ALOGI(\"[%s] \" x, mConsumerName.string(), ##__VA_ARGS__)\n#define BQ_LOGW(x, ...) ALOGW(\"[%s] \" x, mConsumerName.string(), ##__VA_ARGS__)\n#define BQ_LOGE(x, ...) ALOGE(\"[%s] \" x, mConsumerName.string(), ##__VA_ARGS__)\n\n#define ATRACE_BUFFER_INDEX(index)                                   \\\n    if (ATRACE_ENABLED()) {                                          \\\n        char ___traceBuf[1024];                                      \\\n        snprintf(___traceBuf, 1024, \"%s: %d\",                        \\\n                mCore->mConsumerName.string(), (index));             \\\n        android::ScopedTrace ___bufTracer(ATRACE_TAG, ___traceBuf);  \\\n    }\n\nnamespace android {\n\nclass IConsumerListener;\nclass IGraphicBufferAlloc;\nclass IProducerListener;\n\nclass BufferQueueCore : public virtual RefBase {\n\n    friend class BufferQueueProducer;\n    friend class BufferQueueConsumer;\n\npublic:\n    // Used as a placeholder slot number when the value isn't pointing to an\n    // existing buffer.\n    enum { INVALID_BUFFER_SLOT = BufferItem::INVALID_BUFFER_SLOT };\n\n    // We reserve two slots in order to guarantee that the producer and\n    // consumer can run asynchronously.\n    enum { MAX_MAX_ACQUIRED_BUFFERS = BufferQueueDefs::NUM_BUFFER_SLOTS - 2 };\n\n    // The default API number used to indicate that no producer is connected\n    enum { NO_CONNECTED_API = 0 };\n\n    typedef Vector<BufferItem> Fifo;\n\n    // BufferQueueCore manages a pool of gralloc memory slots to be used by\n    // producers and consumers. allocator is used to allocate all the needed\n    // gralloc buffers.\n    BufferQueueCore(const sp<IGraphicBufferAlloc>& allocator = NULL);\n    virtual ~BufferQueueCore();\n\nprivate:\n    // Dump our state in a string\n    void dump(String8& result, const char* prefix) const;\n\n    // getMinUndequeuedBufferCountLocked returns the minimum number of buffers\n    // that must remain in a state other than DEQUEUED. The async parameter\n    // tells whether we're in asynchronous mode.\n    int getMinUndequeuedBufferCountLocked(bool async) const;\n\n    // getMinMaxBufferCountLocked returns the minimum number of buffers allowed\n    // given the current BufferQueue state. The async parameter tells whether\n    // we're in asynchonous mode.\n    int getMinMaxBufferCountLocked(bool async) const;\n\n    // getMaxBufferCountLocked returns the maximum number of buffers that can be\n    // allocated at once. This value depends on the following member variables:\n    //\n    //     mDequeueBufferCannotBlock\n    //     mMaxAcquiredBufferCount\n    //     mDefaultMaxBufferCount\n    //     mOverrideMaxBufferCount\n    //     async parameter\n    //\n    // Any time one of these member variables is changed while a producer is\n    // connected, mDequeueCondition must be broadcast.\n    int getMaxBufferCountLocked(bool async) const;\n\n    // setDefaultMaxBufferCountLocked sets the maximum number of buffer slots\n    // that will be used if the producer does not override the buffer slot\n    // count. The count must be between 2 and NUM_BUFFER_SLOTS, inclusive. The\n    // initial default is 2.\n    status_t setDefaultMaxBufferCountLocked(int count);\n\n    // freeBufferLocked frees the GraphicBuffer and sync resources for the\n    // given slot.\n    void freeBufferLocked(int slot);\n\n    // freeAllBuffersLocked frees the GraphicBuffer and sync resources for\n    // all slots.\n    void freeAllBuffersLocked();\n\n    // stillTracking returns true iff the buffer item is still being tracked\n    // in one of the slots.\n    bool stillTracking(const BufferItem* item) const;\n\n    // waitWhileAllocatingLocked blocks until mIsAllocating is false.\n    void waitWhileAllocatingLocked() const;\n\n    // validateConsistencyLocked ensures that the free lists are in sync with\n    // the information stored in mSlots\n    void validateConsistencyLocked() const;\n\n    // mAllocator is the connection to SurfaceFlinger that is used to allocate\n    // new GraphicBuffer objects.\n    sp<IGraphicBufferAlloc> mAllocator;\n\n    // mMutex is the mutex used to prevent concurrent access to the member\n    // variables of BufferQueueCore objects. It must be locked whenever any\n    // member variable is accessed.\n    mutable Mutex mMutex;\n\n    // mIsAbandoned indicates that the BufferQueue will no longer be used to\n    // consume image buffers pushed to it using the IGraphicBufferProducer\n    // interface. It is initialized to false, and set to true in the\n    // consumerDisconnect method. A BufferQueue that is abandoned will return\n    // the NO_INIT error from all IGraphicBufferProducer methods capable of\n    // returning an error.\n    bool mIsAbandoned;\n\n    // mConsumerControlledByApp indicates whether the connected consumer is\n    // controlled by the application.\n    bool mConsumerControlledByApp;\n\n    // mConsumerName is a string used to identify the BufferQueue in log\n    // messages. It is set by the IGraphicBufferConsumer::setConsumerName\n    // method.\n    String8 mConsumerName;\n\n    // mConsumerListener is used to notify the connected consumer of\n    // asynchronous events that it may wish to react to. It is initially\n    // set to NULL and is written by consumerConnect and consumerDisconnect.\n    sp<IConsumerListener> mConsumerListener;\n\n    // mConsumerUsageBits contains flags that the consumer wants for\n    // GraphicBuffers.\n    uint32_t mConsumerUsageBits;\n\n    // mConnectedApi indicates the producer API that is currently connected\n    // to this BufferQueue. It defaults to NO_CONNECTED_API, and gets updated\n    // by the connect and disconnect methods.\n    int mConnectedApi;\n\n    // mConnectedProducerToken is used to set a binder death notification on\n    // the producer.\n    sp<IProducerListener> mConnectedProducerListener;\n\n    // mSlots is an array of buffer slots that must be mirrored on the producer\n    // side. This allows buffer ownership to be transferred between the producer\n    // and consumer without sending a GraphicBuffer over Binder. The entire\n    // array is initialized to NULL at construction time, and buffers are\n    // allocated for a slot when requestBuffer is called with that slot's index.\n    BufferQueueDefs::SlotsType mSlots;\n\n    // mQueue is a FIFO of queued buffers used in synchronous mode.\n    Fifo mQueue;\n\n    // mFreeSlots contains all of the slots which are FREE and do not currently\n    // have a buffer attached\n    std::set<int> mFreeSlots;\n\n    // mFreeBuffers contains all of the slots which are FREE and currently have\n    // a buffer attached\n    std::list<int> mFreeBuffers;\n\n    // mOverrideMaxBufferCount is the limit on the number of buffers that will\n    // be allocated at one time. This value is set by the producer by calling\n    // setBufferCount. The default is 0, which means that the producer doesn't\n    // care about the number of buffers in the pool. In that case,\n    // mDefaultMaxBufferCount is used as the limit.\n    int mOverrideMaxBufferCount;\n\n    // mDequeueCondition is a condition variable used for dequeueBuffer in\n    // synchronous mode.\n    mutable Condition mDequeueCondition;\n\n    // mUseAsyncBuffer indicates whether an extra buffer is used in async mode\n    // to prevent dequeueBuffer from blocking.\n    bool mUseAsyncBuffer;\n\n    // mDequeueBufferCannotBlock indicates whether dequeueBuffer is allowed to\n    // block. This flag is set during connect when both the producer and\n    // consumer are controlled by the application.\n    bool mDequeueBufferCannotBlock;\n\n    // mDefaultBufferFormat can be set so it will override the buffer format\n    // when it isn't specified in dequeueBuffer.\n    PixelFormat mDefaultBufferFormat;\n\n    // mDefaultWidth holds the default width of allocated buffers. It is used\n    // in dequeueBuffer if a width and height of 0 are specified.\n    uint32_t mDefaultWidth;\n\n    // mDefaultHeight holds the default height of allocated buffers. It is used\n    // in dequeueBuffer if a width and height of 0 are specified.\n    uint32_t mDefaultHeight;\n\n    // mDefaultBufferDataSpace holds the default dataSpace of queued buffers.\n    // It is used in queueBuffer if a dataspace of 0 (HAL_DATASPACE_UNKNOWN)\n    // is specified.\n    android_dataspace mDefaultBufferDataSpace;\n\n    // mDefaultMaxBufferCount is the default limit on the number of buffers that\n    // will be allocated at one time. This default limit is set by the consumer.\n    // The limit (as opposed to the default limit) may be overriden by the\n    // producer.\n    int mDefaultMaxBufferCount;\n\n    // mMaxAcquiredBufferCount is the number of buffers that the consumer may\n    // acquire at one time. It defaults to 1, and can be changed by the consumer\n    // via setMaxAcquiredBufferCount, but this may only be done while no\n    // producer is connected to the BufferQueue. This value is used to derive\n    // the value returned for the MIN_UNDEQUEUED_BUFFERS query to the producer.\n    int mMaxAcquiredBufferCount;\n\n    // mBufferHasBeenQueued is true once a buffer has been queued. It is reset\n    // when something causes all buffers to be freed (e.g., changing the buffer\n    // count).\n    bool mBufferHasBeenQueued;\n\n    // mFrameCounter is the free running counter, incremented on every\n    // successful queueBuffer call and buffer allocation.\n    uint64_t mFrameCounter;\n\n    // mTransformHint is used to optimize for screen rotations.\n    uint32_t mTransformHint;\n\n    // mSidebandStream is a handle to the sideband buffer stream, if any\n    sp<NativeHandle> mSidebandStream;\n\n    // mIsAllocating indicates whether a producer is currently trying to allocate buffers (which\n    // releases mMutex while doing the allocation proper). Producers should not modify any of the\n    // FREE slots while this is true. mIsAllocatingCondition is signaled when this value changes to\n    // false.\n    bool mIsAllocating;\n\n    // mIsAllocatingCondition is a condition variable used by producers to wait until mIsAllocating\n    // becomes false.\n    mutable Condition mIsAllocatingCondition;\n\n    // mAllowAllocation determines whether dequeueBuffer is allowed to allocate\n    // new buffers\n    bool mAllowAllocation;\n\n    // mBufferAge tracks the age of the contents of the most recently dequeued\n    // buffer as the number of frames that have elapsed since it was last queued\n    uint64_t mBufferAge;\n\n    // mGenerationNumber stores the current generation number of the attached\n    // producer. Any attempt to attach a buffer with a different generation\n    // number will fail.\n    uint32_t mGenerationNumber;\n\n}; // class BufferQueueCore\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferQueueDefs.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERQUEUECOREDEFS_H\n#define ANDROID_GUI_BUFFERQUEUECOREDEFS_H\n\n#include <gui/BufferSlot.h>\n\nnamespace android {\n    class BufferQueueCore;\n\n    namespace BufferQueueDefs {\n        // BufferQueue will keep track of at most this value of buffers.\n        // Attempts at runtime to increase the number of buffers past this\n        // will fail.\n        enum { NUM_BUFFER_SLOTS = 64 };\n\n        typedef BufferSlot SlotsType[NUM_BUFFER_SLOTS];\n    } // namespace BufferQueueDefs\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferQueueProducer.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERQUEUEPRODUCER_H\n#define ANDROID_GUI_BUFFERQUEUEPRODUCER_H\n\n#include <gui/BufferQueueDefs.h>\n#include <gui/IGraphicBufferProducer.h>\n\nnamespace android {\n\nclass BufferSlot;\n\nclass BufferQueueProducer : public BnGraphicBufferProducer,\n                            private IBinder::DeathRecipient {\npublic:\n    friend class BufferQueue; // Needed to access binderDied\n\n    BufferQueueProducer(const sp<BufferQueueCore>& core);\n    virtual ~BufferQueueProducer();\n\n    // requestBuffer returns the GraphicBuffer for slot N.\n    //\n    // In normal operation, this is called the first time slot N is returned\n    // by dequeueBuffer.  It must be called again if dequeueBuffer returns\n    // flags indicating that previously-returned buffers are no longer valid.\n    virtual status_t requestBuffer(int slot, sp<GraphicBuffer>* buf);\n\n    // setBufferCount updates the number of available buffer slots.  If this\n    // method succeeds, buffer slots will be both unallocated and owned by\n    // the BufferQueue object (i.e. they are not owned by the producer or\n    // consumer).\n    //\n    // This will fail if the producer has dequeued any buffers, or if\n    // bufferCount is invalid.  bufferCount must generally be a value\n    // between the minimum undequeued buffer count (exclusive) and NUM_BUFFER_SLOTS\n    // (inclusive).  It may also be set to zero (the default) to indicate\n    // that the producer does not wish to set a value.  The minimum value\n    // can be obtained by calling query(NATIVE_WINDOW_MIN_UNDEQUEUED_BUFFERS,\n    // ...).\n    //\n    // This may only be called by the producer.  The consumer will be told\n    // to discard buffers through the onBuffersReleased callback.\n    virtual status_t setBufferCount(int bufferCount);\n\n    // dequeueBuffer gets the next buffer slot index for the producer to use.\n    // If a buffer slot is available then that slot index is written to the\n    // location pointed to by the buf argument and a status of OK is returned.\n    // If no slot is available then a status of -EBUSY is returned and buf is\n    // unmodified.\n    //\n    // The outFence parameter will be updated to hold the fence associated with\n    // the buffer. The contents of the buffer must not be overwritten until the\n    // fence signals. If the fence is Fence::NO_FENCE, the buffer may be\n    // written immediately.\n    //\n    // The width and height parameters must be no greater than the minimum of\n    // GL_MAX_VIEWPORT_DIMS and GL_MAX_TEXTURE_SIZE (see: glGetIntegerv).\n    // An error due to invalid dimensions might not be reported until\n    // updateTexImage() is called.  If width and height are both zero, the\n    // default values specified by setDefaultBufferSize() are used instead.\n    //\n    // If the format is 0, the default format will be used.\n    //\n    // The usage argument specifies gralloc buffer usage flags.  The values\n    // are enumerated in gralloc.h, e.g. GRALLOC_USAGE_HW_RENDER.  These\n    // will be merged with the usage flags specified by setConsumerUsageBits.\n    //\n    // The return value may be a negative error value or a non-negative\n    // collection of flags.  If the flags are set, the return values are\n    // valid, but additional actions must be performed.\n    //\n    // If IGraphicBufferProducer::BUFFER_NEEDS_REALLOCATION is set, the\n    // producer must discard cached GraphicBuffer references for the slot\n    // returned in buf.\n    // If IGraphicBufferProducer::RELEASE_ALL_BUFFERS is set, the producer\n    // must discard cached GraphicBuffer references for all slots.\n    //\n    // In both cases, the producer will need to call requestBuffer to get a\n    // GraphicBuffer handle for the returned slot.\n    virtual status_t dequeueBuffer(int *outSlot, sp<Fence>* outFence,\n            bool async, uint32_t width, uint32_t height, PixelFormat format,\n            uint32_t usage);\n\n    // See IGraphicBufferProducer::detachBuffer\n    virtual status_t detachBuffer(int slot);\n\n    // See IGraphicBufferProducer::detachNextBuffer\n    virtual status_t detachNextBuffer(sp<GraphicBuffer>* outBuffer,\n            sp<Fence>* outFence);\n\n    // See IGraphicBufferProducer::attachBuffer\n    virtual status_t attachBuffer(int* outSlot, const sp<GraphicBuffer>& buffer);\n\n    // queueBuffer returns a filled buffer to the BufferQueue.\n    //\n    // Additional data is provided in the QueueBufferInput struct.  Notably,\n    // a timestamp must be provided for the buffer. The timestamp is in\n    // nanoseconds, and must be monotonically increasing. Its other semantics\n    // (zero point, etc) are producer-specific and should be documented by the\n    // producer.\n    //\n    // The caller may provide a fence that signals when all rendering\n    // operations have completed.  Alternatively, NO_FENCE may be used,\n    // indicating that the buffer is ready immediately.\n    //\n    // Some values are returned in the output struct: the current settings\n    // for default width and height, the current transform hint, and the\n    // number of queued buffers.\n    virtual status_t queueBuffer(int slot,\n            const QueueBufferInput& input, QueueBufferOutput* output);\n\n    // cancelBuffer returns a dequeued buffer to the BufferQueue, but doesn't\n    // queue it for use by the consumer.\n    //\n    // The buffer will not be overwritten until the fence signals.  The fence\n    // will usually be the one obtained from dequeueBuffer.\n    virtual void cancelBuffer(int slot, const sp<Fence>& fence);\n\n    // Query native window attributes.  The \"what\" values are enumerated in\n    // window.h (e.g. NATIVE_WINDOW_FORMAT).\n    virtual int query(int what, int* outValue);\n\n    // connect attempts to connect a producer API to the BufferQueue.  This\n    // must be called before any other IGraphicBufferProducer methods are\n    // called except for getAllocator.  A consumer must already be connected.\n    //\n    // This method will fail if connect was previously called on the\n    // BufferQueue and no corresponding disconnect call was made (i.e. if\n    // it's still connected to a producer).\n    //\n    // APIs are enumerated in window.h (e.g. NATIVE_WINDOW_API_CPU).\n    virtual status_t connect(const sp<IProducerListener>& listener,\n            int api, bool producerControlledByApp, QueueBufferOutput* output);\n\n    // disconnect attempts to disconnect a producer API from the BufferQueue.\n    // Calling this method will cause any subsequent calls to other\n    // IGraphicBufferProducer methods to fail except for getAllocator and connect.\n    // Successfully calling connect after this will allow the other methods to\n    // succeed again.\n    //\n    // This method will fail if the the BufferQueue is not currently\n    // connected to the specified producer API.\n    virtual status_t disconnect(int api);\n\n    // Attaches a sideband buffer stream to the IGraphicBufferProducer.\n    //\n    // A sideband stream is a device-specific mechanism for passing buffers\n    // from the producer to the consumer without using dequeueBuffer/\n    // queueBuffer. If a sideband stream is present, the consumer can choose\n    // whether to acquire buffers from the sideband stream or from the queued\n    // buffers.\n    //\n    // Passing NULL or a different stream handle will detach the previous\n    // handle if any.\n    virtual status_t setSidebandStream(const sp<NativeHandle>& stream);\n\n    // See IGraphicBufferProducer::allocateBuffers\n    virtual void allocateBuffers(bool async, uint32_t width, uint32_t height,\n            PixelFormat format, uint32_t usage);\n\n    // See IGraphicBufferProducer::allowAllocation\n    virtual status_t allowAllocation(bool allow);\n\n    // See IGraphicBufferProducer::setGenerationNumber\n    virtual status_t setGenerationNumber(uint32_t generationNumber);\n\n    // See IGraphicBufferProducer::getConsumerName\n    virtual String8 getConsumerName() const override;\n\nprivate:\n    // This is required by the IBinder::DeathRecipient interface\n    virtual void binderDied(const wp<IBinder>& who);\n\n    // waitForFreeSlotThenRelock finds the oldest slot in the FREE state. It may\n    // block if there are no available slots and we are not in non-blocking\n    // mode (producer and consumer controlled by the application). If it blocks,\n    // it will release mCore->mMutex while blocked so that other operations on\n    // the BufferQueue may succeed.\n    status_t waitForFreeSlotThenRelock(const char* caller, bool async,\n            int* found, status_t* returnFlags) const;\n\n    sp<BufferQueueCore> mCore;\n\n    // This references mCore->mSlots. Lock mCore->mMutex while accessing.\n    BufferQueueDefs::SlotsType& mSlots;\n\n    // This is a cached copy of the name stored in the BufferQueueCore.\n    // It's updated during connect and dequeueBuffer (which should catch\n    // most updates).\n    String8 mConsumerName;\n\n    uint32_t mStickyTransform;\n\n    // This saves the fence from the last queueBuffer, such that the\n    // next queueBuffer call can throttle buffer production. The prior\n    // queueBuffer's fence is not nessessarily available elsewhere,\n    // since the previous buffer might have already been acquired.\n    sp<Fence> mLastQueueBufferFence;\n\n    // Take-a-ticket system for ensuring that onFrame* callbacks are called in\n    // the order that frames are queued. While the BufferQueue lock\n    // (mCore->mMutex) is held, a ticket is retained by the producer. After\n    // dropping the BufferQueue lock, the producer must wait on the condition\n    // variable until the current callback ticket matches its retained ticket.\n    Mutex mCallbackMutex;\n    int mNextCallbackTicket; // Protected by mCore->mMutex\n    int mCurrentCallbackTicket; // Protected by mCallbackMutex\n    Condition mCallbackCondition;\n\n}; // class BufferQueueProducer\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/BufferSlot.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_BUFFERSLOT_H\n#define ANDROID_GUI_BUFFERSLOT_H\n\n#include <ui/Fence.h>\n#include <ui/GraphicBuffer.h>\n\n#include <EGL/egl.h>\n#include <EGL/eglext.h>\n\n#include <utils/StrongPointer.h>\n\nnamespace android {\n\nclass Fence;\n\nstruct BufferSlot {\n\n    BufferSlot()\n    : mEglDisplay(EGL_NO_DISPLAY),\n      mBufferState(BufferSlot::FREE),\n      mRequestBufferCalled(false),\n      mFrameNumber(0),\n      mEglFence(EGL_NO_SYNC_KHR),\n      mAcquireCalled(false),\n      mNeedsCleanupOnRelease(false),\n      mAttachedByConsumer(false) {\n    }\n\n    // mGraphicBuffer points to the buffer allocated for this slot or is NULL\n    // if no buffer has been allocated.\n    sp<GraphicBuffer> mGraphicBuffer;\n\n    // mEglDisplay is the EGLDisplay used to create EGLSyncKHR objects.\n    EGLDisplay mEglDisplay;\n\n    // BufferState represents the different states in which a buffer slot\n    // can be.  All slots are initially FREE.\n    enum BufferState {\n        // FREE indicates that the buffer is available to be dequeued\n        // by the producer.  The buffer may be in use by the consumer for\n        // a finite time, so the buffer must not be modified until the\n        // associated fence is signaled.\n        //\n        // The slot is \"owned\" by BufferQueue.  It transitions to DEQUEUED\n        // when dequeueBuffer is called.\n        FREE = 0,\n\n        // DEQUEUED indicates that the buffer has been dequeued by the\n        // producer, but has not yet been queued or canceled.  The\n        // producer may modify the buffer's contents as soon as the\n        // associated ready fence is signaled.\n        //\n        // The slot is \"owned\" by the producer.  It can transition to\n        // QUEUED (via queueBuffer) or back to FREE (via cancelBuffer).\n        DEQUEUED = 1,\n\n        // QUEUED indicates that the buffer has been filled by the\n        // producer and queued for use by the consumer.  The buffer\n        // contents may continue to be modified for a finite time, so\n        // the contents must not be accessed until the associated fence\n        // is signaled.\n        //\n        // The slot is \"owned\" by BufferQueue.  It can transition to\n        // ACQUIRED (via acquireBuffer) or to FREE (if another buffer is\n        // queued in asynchronous mode).\n        QUEUED = 2,\n\n        // ACQUIRED indicates that the buffer has been acquired by the\n        // consumer.  As with QUEUED, the contents must not be accessed\n        // by the consumer until the fence is signaled.\n        //\n        // The slot is \"owned\" by the consumer.  It transitions to FREE\n        // when releaseBuffer is called.\n        ACQUIRED = 3\n    };\n\n    static const char* bufferStateName(BufferState state);\n\n    // mBufferState is the current state of this buffer slot.\n    BufferState mBufferState;\n\n    // mRequestBufferCalled is used for validating that the producer did\n    // call requestBuffer() when told to do so. Technically this is not\n    // needed but useful for debugging and catching producer bugs.\n    bool mRequestBufferCalled;\n\n    // mFrameNumber is the number of the queued frame for this slot.  This\n    // is used to dequeue buffers in LRU order (useful because buffers\n    // may be released before their release fence is signaled).\n    uint64_t mFrameNumber;\n\n    // mEglFence is the EGL sync object that must signal before the buffer\n    // associated with this buffer slot may be dequeued. It is initialized\n    // to EGL_NO_SYNC_KHR when the buffer is created and may be set to a\n    // new sync object in releaseBuffer.  (This is deprecated in favor of\n    // mFence, below.)\n    EGLSyncKHR mEglFence;\n\n    // mFence is a fence which will signal when work initiated by the\n    // previous owner of the buffer is finished. When the buffer is FREE,\n    // the fence indicates when the consumer has finished reading\n    // from the buffer, or when the producer has finished writing if it\n    // called cancelBuffer after queueing some writes. When the buffer is\n    // QUEUED, it indicates when the producer has finished filling the\n    // buffer. When the buffer is DEQUEUED or ACQUIRED, the fence has been\n    // passed to the consumer or producer along with ownership of the\n    // buffer, and mFence is set to NO_FENCE.\n    sp<Fence> mFence;\n\n    // Indicates whether this buffer has been seen by a consumer yet\n    bool mAcquireCalled;\n\n    // Indicates whether this buffer needs to be cleaned up by the\n    // consumer.  This is set when a buffer in ACQUIRED state is freed.\n    // It causes releaseBuffer to return STALE_BUFFER_SLOT.\n    bool mNeedsCleanupOnRelease;\n\n    // Indicates whether the buffer was attached on the consumer side.\n    // If so, it needs to set the BUFFER_NEEDS_REALLOCATION flag when dequeued\n    // to prevent the producer from using a stale cached buffer.\n    bool mAttachedByConsumer;\n};\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/ConsumerBase.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_CONSUMERBASE_H\n#define ANDROID_GUI_CONSUMERBASE_H\n\n#include <gui/BufferQueue.h>\n\n#include <ui/GraphicBuffer.h>\n\n#include <utils/String8.h>\n#include <utils/Vector.h>\n#include <utils/threads.h>\n#include <gui/IConsumerListener.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass String8;\n\n// ConsumerBase is a base class for BufferQueue consumer end-points. It\n// handles common tasks like management of the connection to the BufferQueue\n// and the buffer pool.\nclass ConsumerBase : public virtual RefBase,\n        protected ConsumerListener {\npublic:\n    struct FrameAvailableListener : public virtual RefBase {\n        // See IConsumerListener::onFrame{Available,Replaced}\n        virtual void onFrameAvailable(const BufferItem& item) = 0;\n        virtual void onFrameReplaced(const BufferItem& /* item */) {}\n    };\n\n    virtual ~ConsumerBase();\n\n    // abandon frees all the buffers and puts the ConsumerBase into the\n    // 'abandoned' state.  Once put in this state the ConsumerBase can never\n    // leave it.  When in the 'abandoned' state, all methods of the\n    // IGraphicBufferProducer interface will fail with the NO_INIT error.\n    //\n    // Note that while calling this method causes all the buffers to be freed\n    // from the perspective of the the ConsumerBase, if there are additional\n    // references on the buffers (e.g. if a buffer is referenced by a client\n    // or by OpenGL ES as a texture) then those buffer will remain allocated.\n    void abandon();\n\n    // Returns true if the ConsumerBase is in the 'abandoned' state\n    bool isAbandoned();\n\n    // set the name of the ConsumerBase that will be used to identify it in\n    // log messages.\n    void setName(const String8& name);\n\n    // dump writes the current state to a string. Child classes should add\n    // their state to the dump by overriding the dumpLocked method, which is\n    // called by these methods after locking the mutex.\n    void dump(String8& result) const;\n    void dump(String8& result, const char* prefix) const;\n\n    // setFrameAvailableListener sets the listener object that will be notified\n    // when a new frame becomes available.\n    void setFrameAvailableListener(const wp<FrameAvailableListener>& listener);\n\n    // See IGraphicBufferConsumer::detachBuffer\n    status_t detachBuffer(int slot);\n\n    // See IGraphicBufferConsumer::setDefaultBufferSize\n    status_t setDefaultBufferSize(uint32_t width, uint32_t height);\n\n    // See IGraphicBufferConsumer::setDefaultBufferFormat\n    status_t setDefaultBufferFormat(PixelFormat defaultFormat);\n\n    // See IGraphicBufferConsumer::setDefaultBufferDataSpace\n    status_t setDefaultBufferDataSpace(android_dataspace defaultDataSpace);\n\nprivate:\n    ConsumerBase(const ConsumerBase&);\n    void operator=(const ConsumerBase&);\n\nprotected:\n    // ConsumerBase constructs a new ConsumerBase object to consume image\n    // buffers from the given IGraphicBufferConsumer.\n    // The controlledByApp flag indicates that this consumer is under the application's\n    // control.\n    ConsumerBase(const sp<IGraphicBufferConsumer>& consumer, bool controlledByApp = false);\n\n    // onLastStrongRef gets called by RefBase just before the dtor of the most\n    // derived class.  It is used to clean up the buffers so that ConsumerBase\n    // can coordinate the clean-up by calling into virtual methods implemented\n    // by the derived classes.  This would not be possible from the\n    // ConsuemrBase dtor because by the time that gets called the derived\n    // classes have already been destructed.\n    //\n    // This methods should not need to be overridden by derived classes, but\n    // if they are overridden the ConsumerBase implementation must be called\n    // from the derived class.\n    virtual void onLastStrongRef(const void* id);\n\n    // Implementation of the IConsumerListener interface.  These\n    // calls are used to notify the ConsumerBase of asynchronous events in the\n    // BufferQueue.  The onFrameAvailable, onFrameReplaced, and\n    // onBuffersReleased methods should not need to be overridden by derived\n    // classes, but if they are overridden the ConsumerBase implementation must\n    // be called from the derived class. The ConsumerBase version of\n    // onSidebandStreamChanged does nothing and can be overriden by derived\n    // classes if they want the notification.\n    virtual void onFrameAvailable(const BufferItem& item) override;\n    virtual void onFrameReplaced(const BufferItem& item) override;\n    virtual void onBuffersReleased() override;\n    virtual void onSidebandStreamChanged() override;\n\n    // freeBufferLocked frees up the given buffer slot.  If the slot has been\n    // initialized this will release the reference to the GraphicBuffer in that\n    // slot.  Otherwise it has no effect.\n    //\n    // Derived classes should override this method to clean up any state they\n    // keep per slot.  If it is overridden, the derived class's implementation\n    // must call ConsumerBase::freeBufferLocked.\n    //\n    // This method must be called with mMutex locked.\n    virtual void freeBufferLocked(int slotIndex);\n\n    // abandonLocked puts the BufferQueue into the abandoned state, causing\n    // all future operations on it to fail. This method rather than the public\n    // abandon method should be overridden by child classes to add abandon-\n    // time behavior.\n    //\n    // Derived classes should override this method to clean up any object\n    // state they keep (as opposed to per-slot state).  If it is overridden,\n    // the derived class's implementation must call ConsumerBase::abandonLocked.\n    //\n    // This method must be called with mMutex locked.\n    virtual void abandonLocked();\n\n    // dumpLocked dumps the current state of the ConsumerBase object to the\n    // result string.  Each line is prefixed with the string pointed to by the\n    // prefix argument.  The buffer argument points to a buffer that may be\n    // used for intermediate formatting data, and the size of that buffer is\n    // indicated by the size argument.\n    //\n    // Derived classes should override this method to dump their internal\n    // state.  If this method is overridden the derived class's implementation\n    // should call ConsumerBase::dumpLocked.\n    //\n    // This method must be called with mMutex locked.\n    virtual void dumpLocked(String8& result, const char* prefix) const;\n\n    // acquireBufferLocked fetches the next buffer from the BufferQueue and\n    // updates the buffer slot for the buffer returned.\n    //\n    // Derived classes should override this method to perform any\n    // initialization that must take place the first time a buffer is assigned\n    // to a slot.  If it is overridden the derived class's implementation must\n    // call ConsumerBase::acquireBufferLocked.\n    virtual status_t acquireBufferLocked(BufferItem *item, nsecs_t presentWhen,\n            uint64_t maxFrameNumber = 0);\n\n    // releaseBufferLocked relinquishes control over a buffer, returning that\n    // control to the BufferQueue.\n    //\n    // Derived classes should override this method to perform any cleanup that\n    // must take place when a buffer is released back to the BufferQueue.  If\n    // it is overridden the derived class's implementation must call\n    // ConsumerBase::releaseBufferLocked.e\n    virtual status_t releaseBufferLocked(int slot,\n            const sp<GraphicBuffer> graphicBuffer,\n            EGLDisplay display, EGLSyncKHR eglFence);\n\n    // returns true iff the slot still has the graphicBuffer in it.\n    bool stillTracking(int slot, const sp<GraphicBuffer> graphicBuffer);\n\n    // addReleaseFence* adds the sync points associated with a fence to the set\n    // of sync points that must be reached before the buffer in the given slot\n    // may be used after the slot has been released.  This should be called by\n    // derived classes each time some asynchronous work is kicked off that\n    // references the buffer.\n    status_t addReleaseFence(int slot,\n            const sp<GraphicBuffer> graphicBuffer, const sp<Fence>& fence);\n    status_t addReleaseFenceLocked(int slot,\n            const sp<GraphicBuffer> graphicBuffer, const sp<Fence>& fence);\n\n    // Slot contains the information and object references that\n    // ConsumerBase maintains about a BufferQueue buffer slot.\n    struct Slot {\n        // mGraphicBuffer is the Gralloc buffer store in the slot or NULL if\n        // no Gralloc buffer is in the slot.\n        sp<GraphicBuffer> mGraphicBuffer;\n\n        // mFence is a fence which will signal when the buffer associated with\n        // this buffer slot is no longer being used by the consumer and can be\n        // overwritten. The buffer can be dequeued before the fence signals;\n        // the producer is responsible for delaying writes until it signals.\n        sp<Fence> mFence;\n\n        // the frame number of the last acquired frame for this slot\n        uint64_t mFrameNumber;\n    };\n\n    // mSlots stores the buffers that have been allocated by the BufferQueue\n    // for each buffer slot.  It is initialized to null pointers, and gets\n    // filled in with the result of BufferQueue::acquire when the\n    // client dequeues a buffer from a\n    // slot that has not yet been used. The buffer allocated to a slot will also\n    // be replaced if the requested buffer usage or geometry differs from that\n    // of the buffer allocated to a slot.\n    Slot mSlots[BufferQueue::NUM_BUFFER_SLOTS];\n\n    // mAbandoned indicates that the BufferQueue will no longer be used to\n    // consume images buffers pushed to it using the IGraphicBufferProducer\n    // interface. It is initialized to false, and set to true in the abandon\n    // method.  A BufferQueue that has been abandoned will return the NO_INIT\n    // error from all IConsumerBase methods capable of returning an error.\n    bool mAbandoned;\n\n    // mName is a string used to identify the ConsumerBase in log messages.\n    // It can be set by the setName method.\n    String8 mName;\n\n    // mFrameAvailableListener is the listener object that will be called when a\n    // new frame becomes available. If it is not NULL it will be called from\n    // queueBuffer.\n    wp<FrameAvailableListener> mFrameAvailableListener;\n\n    // The ConsumerBase has-a BufferQueue and is responsible for creating this object\n    // if none is supplied\n    sp<IGraphicBufferConsumer> mConsumer;\n\n    // mMutex is the mutex used to prevent concurrent access to the member\n    // variables of ConsumerBase objects. It must be locked whenever the\n    // member variables are accessed or when any of the *Locked methods are\n    // called.\n    //\n    // This mutex is intended to be locked by derived classes.\n    mutable Mutex mMutex;\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_CONSUMERBASE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/CpuConsumer.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_CPUCONSUMER_H\n#define ANDROID_GUI_CPUCONSUMER_H\n\n#include <gui/ConsumerBase.h>\n\n#include <ui/GraphicBuffer.h>\n\n#include <utils/String8.h>\n#include <utils/Vector.h>\n#include <utils/threads.h>\n\n\nnamespace android {\n\nclass BufferQueue;\n\n/**\n * CpuConsumer is a BufferQueue consumer endpoint that allows direct CPU\n * access to the underlying gralloc buffers provided by BufferQueue. Multiple\n * buffers may be acquired by it at once, to be used concurrently by the\n * CpuConsumer owner. Sets gralloc usage flags to be software-read-only.\n * This queue is synchronous by default.\n */\n\nclass CpuConsumer : public ConsumerBase\n{\n  public:\n    typedef ConsumerBase::FrameAvailableListener FrameAvailableListener;\n\n    struct LockedBuffer {\n        uint8_t    *data;\n        uint32_t    width;\n        uint32_t    height;\n        PixelFormat format;\n        uint32_t    stride;\n        Rect        crop;\n        uint32_t    transform;\n        uint32_t    scalingMode;\n        int64_t     timestamp;\n        android_dataspace dataSpace;\n        uint64_t    frameNumber;\n        // this is the same as format, except for formats that are compatible with\n        // a flexible format (e.g. HAL_PIXEL_FORMAT_YCbCr_420_888). In the latter\n        // case this contains that flexible format\n        PixelFormat flexFormat;\n        // Values below are only valid when using HAL_PIXEL_FORMAT_YCbCr_420_888\n        // or compatible format, in which case LockedBuffer::data\n        // contains the Y channel, and stride is the Y channel stride. For other\n        // formats, these will all be 0.\n        uint8_t    *dataCb;\n        uint8_t    *dataCr;\n        uint32_t    chromaStride;\n        uint32_t    chromaStep;\n    };\n\n    // Create a new CPU consumer. The maxLockedBuffers parameter specifies\n    // how many buffers can be locked for user access at the same time.\n    CpuConsumer(const sp<IGraphicBufferConsumer>& bq,\n            size_t maxLockedBuffers, bool controlledByApp = false);\n\n    virtual ~CpuConsumer();\n\n    // set the name of the CpuConsumer that will be used to identify it in\n    // log messages.\n    void setName(const String8& name);\n\n    // Gets the next graphics buffer from the producer and locks it for CPU use,\n    // filling out the passed-in locked buffer structure with the native pointer\n    // and metadata. Returns BAD_VALUE if no new buffer is available, and\n    // NOT_ENOUGH_DATA if the maximum number of buffers is already locked.\n    //\n    // Only a fixed number of buffers can be locked at a time, determined by the\n    // construction-time maxLockedBuffers parameter. If INVALID_OPERATION is\n    // returned by lockNextBuffer, then old buffers must be returned to the queue\n    // by calling unlockBuffer before more buffers can be acquired.\n    status_t lockNextBuffer(LockedBuffer *nativeBuffer);\n\n    // Returns a locked buffer to the queue, allowing it to be reused. Since\n    // only a fixed number of buffers may be locked at a time, old buffers must\n    // be released by calling unlockBuffer to ensure new buffers can be acquired by\n    // lockNextBuffer.\n    status_t unlockBuffer(const LockedBuffer &nativeBuffer);\n\n  private:\n    // Maximum number of buffers that can be locked at a time\n    size_t mMaxLockedBuffers;\n\n    status_t releaseAcquiredBufferLocked(size_t lockedIdx);\n\n    virtual void freeBufferLocked(int slotIndex);\n\n    // Tracking for buffers acquired by the user\n    struct AcquiredBuffer {\n        // Need to track the original mSlot index and the buffer itself because\n        // the mSlot entry may be freed/reused before the acquired buffer is\n        // released.\n        int mSlot;\n        sp<GraphicBuffer> mGraphicBuffer;\n        void *mBufferPointer;\n\n        AcquiredBuffer() :\n                mSlot(BufferQueue::INVALID_BUFFER_SLOT),\n                mBufferPointer(NULL) {\n        }\n    };\n    Vector<AcquiredBuffer> mAcquiredBuffers;\n\n    // Count of currently locked buffers\n    size_t mCurrentLockedBuffers;\n\n};\n\n} // namespace android\n\n#endif // ANDROID_GUI_CPUCONSUMER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/DisplayEventReceiver.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_DISPLAY_EVENT_H\n#define ANDROID_GUI_DISPLAY_EVENT_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <utils/Timers.h>\n\n#include <binder/IInterface.h>\n\n// ----------------------------------------------------------------------------\n\nnamespace android {\n\n// ----------------------------------------------------------------------------\n\nclass BitTube;\nclass IDisplayEventConnection;\n\n// ----------------------------------------------------------------------------\n\nclass DisplayEventReceiver {\npublic:\n    enum {\n        DISPLAY_EVENT_VSYNC = 'vsyn',\n        DISPLAY_EVENT_HOTPLUG = 'plug'\n    };\n\n    struct Event {\n\n        struct Header {\n            uint32_t type;\n            uint32_t id;\n            nsecs_t timestamp __attribute__((aligned(8)));\n        };\n\n        struct VSync {\n            uint32_t count;\n        };\n\n        struct Hotplug {\n            bool connected;\n        };\n\n        Header header;\n        union {\n            VSync vsync;\n            Hotplug hotplug;\n        };\n    };\n\npublic:\n    /*\n     * DisplayEventReceiver creates and registers an event connection with\n     * SurfaceFlinger. VSync events are disabled by default. Call setVSyncRate\n     * or requestNextVsync to receive them.\n     * Other events start being delivered immediately.\n     */\n    DisplayEventReceiver();\n\n    /*\n     * ~DisplayEventReceiver severs the connection with SurfaceFlinger, new events\n     * stop being delivered immediately. Note that the queue could have\n     * some events pending. These will be delivered.\n     */\n    ~DisplayEventReceiver();\n\n    /*\n     * initCheck returns the state of DisplayEventReceiver after construction.\n     */\n    status_t initCheck() const;\n\n    /*\n     * getFd returns the file descriptor to use to receive events.\n     * OWNERSHIP IS RETAINED by DisplayEventReceiver. DO NOT CLOSE this\n     * file-descriptor.\n     */\n    int getFd() const;\n\n    /*\n     * getEvents reads events from the queue and returns how many events were\n     * read. Returns 0 if there are no more events or a negative error code.\n     * If NOT_ENOUGH_DATA is returned, the object has become invalid forever, it\n     * should be destroyed and getEvents() shouldn't be called again.\n     */\n    ssize_t getEvents(Event* events, size_t count);\n    static ssize_t getEvents(const sp<BitTube>& dataChannel,\n            Event* events, size_t count);\n\n    /*\n     * sendEvents write events to the queue and returns how many events were\n     * written.\n     */\n    static ssize_t sendEvents(const sp<BitTube>& dataChannel,\n            Event const* events, size_t count);\n\n    /*\n     * setVsyncRate() sets the Event::VSync delivery rate. A value of\n     * 1 returns every Event::VSync. A value of 2 returns every other event,\n     * etc... a value of 0 returns no event unless  requestNextVsync() has\n     * been called.\n     */\n    status_t setVsyncRate(uint32_t count);\n\n    /*\n     * requestNextVsync() schedules the next Event::VSync. It has no effect\n     * if the vsync rate is > 0.\n     */\n    status_t requestNextVsync();\n\nprivate:\n    sp<IDisplayEventConnection> mEventConnection;\n    sp<BitTube> mDataChannel;\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_DISPLAY_EVENT_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/GLConsumer.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_CONSUMER_H\n#define ANDROID_GUI_CONSUMER_H\n\n#include <EGL/egl.h>\n#include <EGL/eglext.h>\n\n#include <gui/IGraphicBufferProducer.h>\n#include <gui/BufferQueue.h>\n#include <gui/ConsumerBase.h>\n\n#include <ui/GraphicBuffer.h>\n\n#include <utils/String8.h>\n#include <utils/Vector.h>\n#include <utils/threads.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\n\nclass String8;\n\n/*\n * GLConsumer consumes buffers of graphics data from a BufferQueue,\n * and makes them available to OpenGL as a texture.\n *\n * A typical usage pattern is to set up the GLConsumer with the\n * desired options, and call updateTexImage() when a new frame is desired.\n * If a new frame is available, the texture will be updated.  If not,\n * the previous contents are retained.\n *\n * By default, the texture is attached to the GL_TEXTURE_EXTERNAL_OES\n * texture target, in the EGL context of the first thread that calls\n * updateTexImage().\n *\n * This class was previously called SurfaceTexture.\n */\nclass GLConsumer : public ConsumerBase {\npublic:\n    enum { TEXTURE_EXTERNAL = 0x8D65 }; // GL_TEXTURE_EXTERNAL_OES\n    typedef ConsumerBase::FrameAvailableListener FrameAvailableListener;\n\n    // GLConsumer constructs a new GLConsumer object. If the constructor with\n    // the tex parameter is used, tex indicates the name of the OpenGL ES\n    // texture to which images are to be streamed. texTarget specifies the\n    // OpenGL ES texture target to which the texture will be bound in\n    // updateTexImage. useFenceSync specifies whether fences should be used to\n    // synchronize access to buffers if that behavior is enabled at\n    // compile-time.\n    //\n    // A GLConsumer may be detached from one OpenGL ES context and then\n    // attached to a different context using the detachFromContext and\n    // attachToContext methods, respectively. The intention of these methods is\n    // purely to allow a GLConsumer to be transferred from one consumer\n    // context to another. If such a transfer is not needed there is no\n    // requirement that either of these methods be called.\n    //\n    // If the constructor with the tex parameter is used, the GLConsumer is\n    // created in a state where it is considered attached to an OpenGL ES\n    // context for the purposes of the attachToContext and detachFromContext\n    // methods. However, despite being considered \"attached\" to a context, the\n    // specific OpenGL ES context doesn't get latched until the first call to\n    // updateTexImage. After that point, all calls to updateTexImage must be\n    // made with the same OpenGL ES context current.\n    //\n    // If the constructor without the tex parameter is used, the GLConsumer is\n    // created in a detached state, and attachToContext must be called before\n    // calls to updateTexImage.\n    GLConsumer(const sp<IGraphicBufferConsumer>& bq,\n            uint32_t tex, uint32_t texureTarget, bool useFenceSync,\n            bool isControlledByApp);\n\n    GLConsumer(const sp<IGraphicBufferConsumer>& bq, uint32_t texureTarget,\n            bool useFenceSync, bool isControlledByApp);\n\n    // updateTexImage acquires the most recently queued buffer, and sets the\n    // image contents of the target texture to it.\n    //\n    // This call may only be made while the OpenGL ES context to which the\n    // target texture belongs is bound to the calling thread.\n    //\n    // This calls doGLFenceWait to ensure proper synchronization.\n    status_t updateTexImage();\n\n    // releaseTexImage releases the texture acquired in updateTexImage().\n    // This is intended to be used in single buffer mode.\n    //\n    // This call may only be made while the OpenGL ES context to which the\n    // target texture belongs is bound to the calling thread.\n    status_t releaseTexImage();\n\n    // setReleaseFence stores a fence that will signal when the current buffer\n    // is no longer being read. This fence will be returned to the producer\n    // when the current buffer is released by updateTexImage(). Multiple\n    // fences can be set for a given buffer; they will be merged into a single\n    // union fence.\n    void setReleaseFence(const sp<Fence>& fence);\n\n    // setDefaultMaxBufferCount sets the default limit on the maximum number\n    // of buffers that will be allocated at one time. The image producer may\n    // override the limit.\n    status_t setDefaultMaxBufferCount(int bufferCount);\n\n    // getTransformMatrix retrieves the 4x4 texture coordinate transform matrix\n    // associated with the texture image set by the most recent call to\n    // updateTexImage.\n    //\n    // This transform matrix maps 2D homogeneous texture coordinates of the form\n    // (s, t, 0, 1) with s and t in the inclusive range [0, 1] to the texture\n    // coordinate that should be used to sample that location from the texture.\n    // Sampling the texture outside of the range of this transform is undefined.\n    //\n    // This transform is necessary to compensate for transforms that the stream\n    // content producer may implicitly apply to the content. By forcing users of\n    // a GLConsumer to apply this transform we avoid performing an extra\n    // copy of the data that would be needed to hide the transform from the\n    // user.\n    //\n    // The matrix is stored in column-major order so that it may be passed\n    // directly to OpenGL ES via the glLoadMatrixf or glUniformMatrix4fv\n    // functions.\n    void getTransformMatrix(float mtx[16]);\n\n    // getTimestamp retrieves the timestamp associated with the texture image\n    // set by the most recent call to updateTexImage.\n    //\n    // The timestamp is in nanoseconds, and is monotonically increasing. Its\n    // other semantics (zero point, etc) are source-dependent and should be\n    // documented by the source.\n    int64_t getTimestamp();\n\n    // getFrameNumber retrieves the frame number associated with the texture\n    // image set by the most recent call to updateTexImage.\n    //\n    // The frame number is an incrementing counter set to 0 at the creation of\n    // the BufferQueue associated with this consumer.\n    uint64_t getFrameNumber();\n\n    // setDefaultBufferSize is used to set the size of buffers returned by\n    // requestBuffers when a with and height of zero is requested.\n    // A call to setDefaultBufferSize() may trigger requestBuffers() to\n    // be called from the client.\n    // The width and height parameters must be no greater than the minimum of\n    // GL_MAX_VIEWPORT_DIMS and GL_MAX_TEXTURE_SIZE (see: glGetIntegerv).\n    // An error due to invalid dimensions might not be reported until\n    // updateTexImage() is called.\n    status_t setDefaultBufferSize(uint32_t width, uint32_t height);\n\n    // setFilteringEnabled sets whether the transform matrix should be computed\n    // for use with bilinear filtering.\n    void setFilteringEnabled(bool enabled);\n\n    // getCurrentBuffer returns the buffer associated with the current image.\n    sp<GraphicBuffer> getCurrentBuffer() const;\n\n    // getCurrentTextureTarget returns the texture target of the current\n    // texture as returned by updateTexImage().\n    uint32_t getCurrentTextureTarget() const;\n\n    // getCurrentCrop returns the cropping rectangle of the current buffer.\n    Rect getCurrentCrop() const;\n\n    // getCurrentTransform returns the transform of the current buffer.\n    uint32_t getCurrentTransform() const;\n\n    // getCurrentScalingMode returns the scaling mode of the current buffer.\n    uint32_t getCurrentScalingMode() const;\n\n    // getCurrentFence returns the fence indicating when the current buffer is\n    // ready to be read from.\n    sp<Fence> getCurrentFence() const;\n\n    // doGLFenceWait inserts a wait command into the OpenGL ES command stream\n    // to ensure that it is safe for future OpenGL ES commands to access the\n    // current texture buffer.\n    status_t doGLFenceWait() const;\n\n    // set the name of the GLConsumer that will be used to identify it in\n    // log messages.\n    void setName(const String8& name);\n\n    // These functions call the corresponding BufferQueue implementation\n    // so the refactoring can proceed smoothly\n    status_t setDefaultBufferFormat(PixelFormat defaultFormat);\n    status_t setDefaultBufferDataSpace(android_dataspace defaultDataSpace);\n    status_t setConsumerUsageBits(uint32_t usage);\n    status_t setTransformHint(uint32_t hint);\n\n    // detachFromContext detaches the GLConsumer from the calling thread's\n    // current OpenGL ES context.  This context must be the same as the context\n    // that was current for previous calls to updateTexImage.\n    //\n    // Detaching a GLConsumer from an OpenGL ES context will result in the\n    // deletion of the OpenGL ES texture object into which the images were being\n    // streamed.  After a GLConsumer has been detached from the OpenGL ES\n    // context calls to updateTexImage will fail returning INVALID_OPERATION\n    // until the GLConsumer is attached to a new OpenGL ES context using the\n    // attachToContext method.\n    status_t detachFromContext();\n\n    // attachToContext attaches a GLConsumer that is currently in the\n    // 'detached' state to the current OpenGL ES context.  A GLConsumer is\n    // in the 'detached' state iff detachFromContext has successfully been\n    // called and no calls to attachToContext have succeeded since the last\n    // detachFromContext call.  Calls to attachToContext made on a\n    // GLConsumer that is not in the 'detached' state will result in an\n    // INVALID_OPERATION error.\n    //\n    // The tex argument specifies the OpenGL ES texture object name in the\n    // new context into which the image contents will be streamed.  A successful\n    // call to attachToContext will result in this texture object being bound to\n    // the texture target and populated with the image contents that were\n    // current at the time of the last call to detachFromContext.\n    status_t attachToContext(uint32_t tex);\n\nprotected:\n\n    // abandonLocked overrides the ConsumerBase method to clear\n    // mCurrentTextureImage in addition to the ConsumerBase behavior.\n    virtual void abandonLocked();\n\n    // dumpLocked overrides the ConsumerBase method to dump GLConsumer-\n    // specific info in addition to the ConsumerBase behavior.\n    virtual void dumpLocked(String8& result, const char* prefix) const;\n\n    // acquireBufferLocked overrides the ConsumerBase method to update the\n    // mEglSlots array in addition to the ConsumerBase behavior.\n    virtual status_t acquireBufferLocked(BufferItem *item, nsecs_t presentWhen,\n            uint64_t maxFrameNumber = 0) override;\n\n    // releaseBufferLocked overrides the ConsumerBase method to update the\n    // mEglSlots array in addition to the ConsumerBase.\n    virtual status_t releaseBufferLocked(int slot,\n            const sp<GraphicBuffer> graphicBuffer,\n            EGLDisplay display, EGLSyncKHR eglFence);\n\n    status_t releaseBufferLocked(int slot,\n            const sp<GraphicBuffer> graphicBuffer, EGLSyncKHR eglFence) {\n        return releaseBufferLocked(slot, graphicBuffer, mEglDisplay, eglFence);\n    }\n\n    static bool isExternalFormat(PixelFormat format);\n\n    // This releases the buffer in the slot referenced by mCurrentTexture,\n    // then updates state to refer to the BufferItem, which must be a\n    // newly-acquired buffer.\n    status_t updateAndReleaseLocked(const BufferItem& item);\n\n    // Binds mTexName and the current buffer to mTexTarget.  Uses\n    // mCurrentTexture if it's set, mCurrentTextureImage if not.  If the\n    // bind succeeds, this calls doGLFenceWait.\n    status_t bindTextureImageLocked();\n\n    // Gets the current EGLDisplay and EGLContext values, and compares them\n    // to mEglDisplay and mEglContext.  If the fields have been previously\n    // set, the values must match; if not, the fields are set to the current\n    // values.\n    // The contextCheck argument is used to ensure that a GL context is\n    // properly set; when set to false, the check is not performed.\n    status_t checkAndUpdateEglStateLocked(bool contextCheck = false);\n\nprivate:\n    // EglImage is a utility class for tracking and creating EGLImageKHRs. There\n    // is primarily just one image per slot, but there is also special cases:\n    //  - For releaseTexImage, we use a debug image (mReleasedTexImage)\n    //  - After freeBuffer, we must still keep the current image/buffer\n    // Reference counting EGLImages lets us handle all these cases easily while\n    // also only creating new EGLImages from buffers when required.\n    class EglImage : public LightRefBase<EglImage>  {\n    public:\n        EglImage(sp<GraphicBuffer> graphicBuffer);\n\n        // createIfNeeded creates an EGLImage if required (we haven't created\n        // one yet, or the EGLDisplay or crop-rect has changed).\n        status_t createIfNeeded(EGLDisplay display,\n                                const Rect& cropRect,\n                                bool forceCreate = false);\n\n        // This calls glEGLImageTargetTexture2DOES to bind the image to the\n        // texture in the specified texture target.\n        void bindToTextureTarget(uint32_t texTarget);\n\n        const sp<GraphicBuffer>& graphicBuffer() { return mGraphicBuffer; }\n        const native_handle* graphicBufferHandle() {\n            return mGraphicBuffer == NULL ? NULL : mGraphicBuffer->handle;\n        }\n\n    private:\n        // Only allow instantiation using ref counting.\n        friend class LightRefBase<EglImage>;\n        virtual ~EglImage();\n\n        // createImage creates a new EGLImage from a GraphicBuffer.\n        EGLImageKHR createImage(EGLDisplay dpy,\n                const sp<GraphicBuffer>& graphicBuffer, const Rect& crop);\n\n        // Disallow copying\n        EglImage(const EglImage& rhs);\n        void operator = (const EglImage& rhs);\n\n        // mGraphicBuffer is the buffer that was used to create this image.\n        sp<GraphicBuffer> mGraphicBuffer;\n\n        // mEglImage is the EGLImage created from mGraphicBuffer.\n        EGLImageKHR mEglImage;\n\n        // mEGLDisplay is the EGLDisplay that was used to create mEglImage.\n        EGLDisplay mEglDisplay;\n\n        // mCropRect is the crop rectangle passed to EGL when mEglImage\n        // was created.\n        Rect mCropRect;\n    };\n\n    // freeBufferLocked frees up the given buffer slot. If the slot has been\n    // initialized this will release the reference to the GraphicBuffer in that\n    // slot and destroy the EGLImage in that slot.  Otherwise it has no effect.\n    //\n    // This method must be called with mMutex locked.\n    virtual void freeBufferLocked(int slotIndex);\n\n    // computeCurrentTransformMatrixLocked computes the transform matrix for the\n    // current texture.  It uses mCurrentTransform and the current GraphicBuffer\n    // to compute this matrix and stores it in mCurrentTransformMatrix.\n    // mCurrentTextureImage must not be NULL.\n    void computeCurrentTransformMatrixLocked();\n\n    // doGLFenceWaitLocked inserts a wait command into the OpenGL ES command\n    // stream to ensure that it is safe for future OpenGL ES commands to\n    // access the current texture buffer.\n    status_t doGLFenceWaitLocked() const;\n\n    // syncForReleaseLocked performs the synchronization needed to release the\n    // current slot from an OpenGL ES context.  If needed it will set the\n    // current slot's fence to guard against a producer accessing the buffer\n    // before the outstanding accesses have completed.\n    status_t syncForReleaseLocked(EGLDisplay dpy);\n\n    // returns a graphic buffer used when the texture image has been released\n    static sp<GraphicBuffer> getDebugTexImageBuffer();\n\n    // The default consumer usage flags that GLConsumer always sets on its\n    // BufferQueue instance; these will be OR:d with any additional flags passed\n    // from the GLConsumer user. In particular, GLConsumer will always\n    // consume buffers as hardware textures.\n    static const uint32_t DEFAULT_USAGE_FLAGS = GraphicBuffer::USAGE_HW_TEXTURE;\n\n    // mCurrentTextureImage is the EglImage/buffer of the current texture. It's\n    // possible that this buffer is not associated with any buffer slot, so we\n    // must track it separately in order to support the getCurrentBuffer method.\n    sp<EglImage> mCurrentTextureImage;\n\n    // mCurrentCrop is the crop rectangle that applies to the current texture.\n    // It gets set each time updateTexImage is called.\n    Rect mCurrentCrop;\n\n    // mCurrentTransform is the transform identifier for the current texture. It\n    // gets set each time updateTexImage is called.\n    uint32_t mCurrentTransform;\n\n    // mCurrentScalingMode is the scaling mode for the current texture. It gets\n    // set each time updateTexImage is called.\n    uint32_t mCurrentScalingMode;\n\n    // mCurrentFence is the fence received from BufferQueue in updateTexImage.\n    sp<Fence> mCurrentFence;\n\n    // mCurrentTransformMatrix is the transform matrix for the current texture.\n    // It gets computed by computeTransformMatrix each time updateTexImage is\n    // called.\n    float mCurrentTransformMatrix[16];\n\n    // mCurrentTimestamp is the timestamp for the current texture. It\n    // gets set each time updateTexImage is called.\n    int64_t mCurrentTimestamp;\n\n    // mCurrentFrameNumber is the frame counter for the current texture.\n    // It gets set each time updateTexImage is called.\n    uint64_t mCurrentFrameNumber;\n\n    uint32_t mDefaultWidth, mDefaultHeight;\n\n    // mFilteringEnabled indicates whether the transform matrix is computed for\n    // use with bilinear filtering. It defaults to true and is changed by\n    // setFilteringEnabled().\n    bool mFilteringEnabled;\n\n    // mTexName is the name of the OpenGL texture to which streamed images will\n    // be bound when updateTexImage is called. It is set at construction time\n    // and can be changed with a call to attachToContext.\n    uint32_t mTexName;\n\n    // mUseFenceSync indicates whether creation of the EGL_KHR_fence_sync\n    // extension should be used to prevent buffers from being dequeued before\n    // it's safe for them to be written. It gets set at construction time and\n    // never changes.\n    const bool mUseFenceSync;\n\n    // mTexTarget is the GL texture target with which the GL texture object is\n    // associated.  It is set in the constructor and never changed.  It is\n    // almost always GL_TEXTURE_EXTERNAL_OES except for one use case in Android\n    // Browser.  In that case it is set to GL_TEXTURE_2D to allow\n    // glCopyTexSubImage to read from the texture.  This is a hack to work\n    // around a GL driver limitation on the number of FBO attachments, which the\n    // browser's tile cache exceeds.\n    const uint32_t mTexTarget;\n\n    // EGLSlot contains the information and object references that\n    // GLConsumer maintains about a BufferQueue buffer slot.\n    struct EglSlot {\n        EglSlot() : mEglFence(EGL_NO_SYNC_KHR) {}\n\n        // mEglImage is the EGLImage created from mGraphicBuffer.\n        sp<EglImage> mEglImage;\n\n        // mFence is the EGL sync object that must signal before the buffer\n        // associated with this buffer slot may be dequeued. It is initialized\n        // to EGL_NO_SYNC_KHR when the buffer is created and (optionally, based\n        // on a compile-time option) set to a new sync object in updateTexImage.\n        EGLSyncKHR mEglFence;\n    };\n\n    // mEglDisplay is the EGLDisplay with which this GLConsumer is currently\n    // associated.  It is intialized to EGL_NO_DISPLAY and gets set to the\n    // current display when updateTexImage is called for the first time and when\n    // attachToContext is called.\n    EGLDisplay mEglDisplay;\n\n    // mEglContext is the OpenGL ES context with which this GLConsumer is\n    // currently associated.  It is initialized to EGL_NO_CONTEXT and gets set\n    // to the current GL context when updateTexImage is called for the first\n    // time and when attachToContext is called.\n    EGLContext mEglContext;\n\n    // mEGLSlots stores the buffers that have been allocated by the BufferQueue\n    // for each buffer slot.  It is initialized to null pointers, and gets\n    // filled in with the result of BufferQueue::acquire when the\n    // client dequeues a buffer from a\n    // slot that has not yet been used. The buffer allocated to a slot will also\n    // be replaced if the requested buffer usage or geometry differs from that\n    // of the buffer allocated to a slot.\n    EglSlot mEglSlots[BufferQueue::NUM_BUFFER_SLOTS];\n\n    // mCurrentTexture is the buffer slot index of the buffer that is currently\n    // bound to the OpenGL texture. It is initialized to INVALID_BUFFER_SLOT,\n    // indicating that no buffer slot is currently bound to the texture. Note,\n    // however, that a value of INVALID_BUFFER_SLOT does not necessarily mean\n    // that no buffer is bound to the texture. A call to setBufferCount will\n    // reset mCurrentTexture to INVALID_BUFFER_SLOT.\n    int mCurrentTexture;\n\n    // mAttached indicates whether the ConsumerBase is currently attached to\n    // an OpenGL ES context.  For legacy reasons, this is initialized to true,\n    // indicating that the ConsumerBase is considered to be attached to\n    // whatever context is current at the time of the first updateTexImage call.\n    // It is set to false by detachFromContext, and then set to true again by\n    // attachToContext.\n    bool mAttached;\n\n    // protects static initialization\n    static Mutex sStaticInitLock;\n\n    // mReleasedTexImageBuffer is a dummy buffer used when in single buffer\n    // mode and releaseTexImage() has been called\n    static sp<GraphicBuffer> sReleasedTexImageBuffer;\n    sp<EglImage> mReleasedTexImage;\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_CONSUMER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/GraphicBufferAlloc.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_SF_GRAPHIC_BUFFER_ALLOC_H\n#define ANDROID_SF_GRAPHIC_BUFFER_ALLOC_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <gui/IGraphicBufferAlloc.h>\n#include <ui/PixelFormat.h>\n#include <utils/Errors.h>\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\nclass GraphicBuffer;\n\nclass GraphicBufferAlloc : public BnGraphicBufferAlloc {\npublic:\n    GraphicBufferAlloc();\n    virtual ~GraphicBufferAlloc();\n    virtual sp<GraphicBuffer> createGraphicBuffer(uint32_t width,\n            uint32_t height, PixelFormat format, uint32_t usage,\n            status_t* error);\n};\n\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_SF_GRAPHIC_BUFFER_ALLOC_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/GuiConfig.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_CONFIG_H\n#define ANDROID_GUI_CONFIG_H\n\n#include <utils/String8.h>\n\nnamespace android {\n\n// Append the libgui configuration details to configStr.\nvoid appendGuiConfigString(String8& configStr);\n\n}; // namespace android\n\n#endif /*ANDROID_GUI_CONFIG_H*/\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/IConsumerListener.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_ICONSUMERLISTENER_H\n#define ANDROID_GUI_ICONSUMERLISTENER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n\n#include <binder/IInterface.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass BufferItem;\n\n// ConsumerListener is the interface through which the BufferQueue notifies\n// the consumer of events that the consumer may wish to react to.  Because\n// the consumer will generally have a mutex that is locked during calls from\n// the consumer to the BufferQueue, these calls from the BufferQueue to the\n// consumer *MUST* be called only when the BufferQueue mutex is NOT locked.\n\nclass ConsumerListener : public virtual RefBase {\npublic:\n    ConsumerListener() { }\n    virtual ~ConsumerListener() { }\n\n    // onFrameAvailable is called from queueBuffer each time an additional\n    // frame becomes available for consumption. This means that frames that\n    // are queued while in asynchronous mode only trigger the callback if no\n    // previous frames are pending. Frames queued while in synchronous mode\n    // always trigger the callback. The item passed to the callback will contain\n    // all of the information about the queued frame except for its\n    // GraphicBuffer pointer, which will always be null.\n    //\n    // This is called without any lock held and can be called concurrently\n    // by multiple threads.\n    virtual void onFrameAvailable(const BufferItem& item) = 0; /* Asynchronous */\n\n    // onFrameReplaced is called from queueBuffer if the frame being queued is\n    // replacing an existing slot in the queue. Any call to queueBuffer that\n    // doesn't call onFrameAvailable will call this callback instead. The item\n    // passed to the callback will contain all of the information about the\n    // queued frame except for its GraphicBuffer pointer, which will always be\n    // null.\n    //\n    // This is called without any lock held and can be called concurrently\n    // by multiple threads.\n    virtual void onFrameReplaced(const BufferItem& /* item */) {} /* Asynchronous */\n\n    // onBuffersReleased is called to notify the buffer consumer that the\n    // BufferQueue has released its references to one or more GraphicBuffers\n    // contained in its slots.  The buffer consumer should then call\n    // BufferQueue::getReleasedBuffers to retrieve the list of buffers\n    //\n    // This is called without any lock held and can be called concurrently\n    // by multiple threads.\n    virtual void onBuffersReleased() = 0; /* Asynchronous */\n\n    // onSidebandStreamChanged is called to notify the buffer consumer that the\n    // BufferQueue's sideband buffer stream has changed. This is called when a\n    // stream is first attached and when it is either detached or replaced by a\n    // different stream.\n    virtual void onSidebandStreamChanged() = 0; /* Asynchronous */\n};\n\n\nclass IConsumerListener : public ConsumerListener, public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(ConsumerListener);\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnConsumerListener : public BnInterface<IConsumerListener>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_ICONSUMERLISTENER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/IDisplayEventConnection.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_IDISPLAY_EVENT_CONNECTION_H\n#define ANDROID_GUI_IDISPLAY_EVENT_CONNECTION_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n\n#include <binder/IInterface.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass BitTube;\n\nclass IDisplayEventConnection : public IInterface\n{\npublic:\n\n    DECLARE_META_INTERFACE(DisplayEventConnection);\n\n    /*\n     * getDataChannel() returns a BitTube where to receive the events from\n     */\n    virtual sp<BitTube> getDataChannel() const = 0;\n\n    /*\n     * setVsyncRate() sets the vsync event delivery rate. A value of\n     * 1 returns every vsync events. A value of 2 returns every other events,\n     * etc... a value of 0 returns no event unless  requestNextVsync() has\n     * been called.\n     */\n    virtual void setVsyncRate(uint32_t count) = 0;\n\n    /*\n     * requestNextVsync() schedules the next vsync event. It has no effect\n     * if the vsync rate is > 0.\n     */\n    virtual void requestNextVsync() = 0;    // asynchronous\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnDisplayEventConnection : public BnInterface<IDisplayEventConnection>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_IDISPLAY_EVENT_CONNECTION_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/IGraphicBufferAlloc.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_IGRAPHIC_BUFFER_ALLOC_H\n#define ANDROID_GUI_IGRAPHIC_BUFFER_ALLOC_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <binder/IInterface.h>\n#include <ui/PixelFormat.h>\n#include <utils/RefBase.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass GraphicBuffer;\n\nclass IGraphicBufferAlloc : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(GraphicBufferAlloc);\n\n    /* Create a new GraphicBuffer for the client to use.\n     */\n    virtual sp<GraphicBuffer> createGraphicBuffer(uint32_t w, uint32_t h,\n            PixelFormat format, uint32_t usage, status_t* error) = 0;\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnGraphicBufferAlloc : public BnInterface<IGraphicBufferAlloc>\n{\npublic:\n    virtual status_t onTransact(uint32_t code,\n                                const Parcel& data,\n                                Parcel* reply,\n                                uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_GUI_IGRAPHIC_BUFFER_ALLOC_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/IGraphicBufferConsumer.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_IGRAPHICBUFFERCONSUMER_H\n#define ANDROID_GUI_IGRAPHICBUFFERCONSUMER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <utils/Timers.h>\n\n#include <binder/IInterface.h>\n#include <ui/PixelFormat.h>\n#include <ui/Rect.h>\n\n#include <EGL/egl.h>\n#include <EGL/eglext.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass BufferItem;\nclass Fence;\nclass GraphicBuffer;\nclass IConsumerListener;\nclass NativeHandle;\n\nclass IGraphicBufferConsumer : public IInterface {\n\npublic:\n    enum {\n        // Returned by releaseBuffer, after which the consumer must\n        // free any references to the just-released buffer that it might have.\n        STALE_BUFFER_SLOT = 1,\n        // Returned by dequeueBuffer if there are no pending buffers available.\n        NO_BUFFER_AVAILABLE,\n        // Returned by dequeueBuffer if it's too early for the buffer to be acquired.\n        PRESENT_LATER,\n    };\n\n    // acquireBuffer attempts to acquire ownership of the next pending buffer in\n    // the BufferQueue.  If no buffer is pending then it returns\n    // NO_BUFFER_AVAILABLE.  If a buffer is successfully acquired, the\n    // information about the buffer is returned in BufferItem.\n    //\n    // If the buffer returned had previously been\n    // acquired then the BufferItem::mGraphicBuffer field of buffer is set to\n    // NULL and it is assumed that the consumer still holds a reference to the\n    // buffer.\n    //\n    // If presentWhen is non-zero, it indicates the time when the buffer will\n    // be displayed on screen.  If the buffer's timestamp is farther in the\n    // future, the buffer won't be acquired, and PRESENT_LATER will be\n    // returned.  The presentation time is in nanoseconds, and the time base\n    // is CLOCK_MONOTONIC.\n    //\n    // If maxFrameNumber is non-zero, it indicates that acquireBuffer should\n    // only return a buffer with a frame number less than or equal to\n    // maxFrameNumber. If no such frame is available (such as when a buffer has\n    // been replaced but the consumer has not received the onFrameReplaced\n    // callback), then PRESENT_LATER will be returned.\n    //\n    // Return of NO_ERROR means the operation completed as normal.\n    //\n    // Return of a positive value means the operation could not be completed\n    //    at this time, but the user should try again later:\n    // * NO_BUFFER_AVAILABLE - no buffer is pending (nothing queued by producer)\n    // * PRESENT_LATER - the buffer's timestamp is farther in the future\n    //\n    // Return of a negative value means an error has occurred:\n    // * INVALID_OPERATION - too many buffers have been acquired\n    virtual status_t acquireBuffer(BufferItem* buffer, nsecs_t presentWhen,\n            uint64_t maxFrameNumber = 0) = 0;\n\n    // detachBuffer attempts to remove all ownership of the buffer in the given\n    // slot from the buffer queue. If this call succeeds, the slot will be\n    // freed, and there will be no way to obtain the buffer from this interface.\n    // The freed slot will remain unallocated until either it is selected to\n    // hold a freshly allocated buffer in dequeueBuffer or a buffer is attached\n    // to the slot. The buffer must have already been acquired.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - the given slot number is invalid, either because it is\n    //               out of the range [0, NUM_BUFFER_SLOTS) or because the slot\n    //               it refers to is not currently acquired.\n    virtual status_t detachBuffer(int slot) = 0;\n\n    // attachBuffer attempts to transfer ownership of a buffer to the buffer\n    // queue. If this call succeeds, it will be as if this buffer was acquired\n    // from the returned slot number. As such, this call will fail if attaching\n    // this buffer would cause too many buffers to be simultaneously acquired.\n    //\n    // If the buffer is successfully attached, its frameNumber is initialized\n    // to 0. This must be passed into the releaseBuffer call or else the buffer\n    // will be deallocated as stale.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - outSlot or buffer were NULL, or the generation number of\n    //               the buffer did not match the buffer queue.\n    // * INVALID_OPERATION - cannot attach the buffer because it would cause too\n    //                       many buffers to be acquired.\n    // * NO_MEMORY - no free slots available\n    virtual status_t attachBuffer(int *outSlot,\n            const sp<GraphicBuffer>& buffer) = 0;\n\n    // releaseBuffer releases a buffer slot from the consumer back to the\n    // BufferQueue.  This may be done while the buffer's contents are still\n    // being accessed.  The fence will signal when the buffer is no longer\n    // in use. frameNumber is used to indentify the exact buffer returned.\n    //\n    // If releaseBuffer returns STALE_BUFFER_SLOT, then the consumer must free\n    // any references to the just-released buffer that it might have, as if it\n    // had received a onBuffersReleased() call with a mask set for the released\n    // buffer.\n    //\n    // Note that the dependencies on EGL will be removed once we switch to using\n    // the Android HW Sync HAL.\n    //\n    // Return of NO_ERROR means the operation completed as normal.\n    //\n    // Return of a positive value means the operation could not be completed\n    //    at this time, but the user should try again later:\n    // * STALE_BUFFER_SLOT - see above (second paragraph)\n    //\n    // Return of a negative value means an error has occurred:\n    // * BAD_VALUE - one of the following could've happened:\n    //               * the buffer slot was invalid\n    //               * the fence was NULL\n    //               * the buffer slot specified is not in the acquired state\n    virtual status_t releaseBuffer(int buf, uint64_t frameNumber,\n            EGLDisplay display, EGLSyncKHR fence,\n            const sp<Fence>& releaseFence) = 0;\n\n    // consumerConnect connects a consumer to the BufferQueue.  Only one\n    // consumer may be connected, and when that consumer disconnects the\n    // BufferQueue is placed into the \"abandoned\" state, causing most\n    // interactions with the BufferQueue by the producer to fail.\n    // controlledByApp indicates whether the consumer is controlled by\n    // the application.\n    //\n    // consumer may not be NULL.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned\n    // * BAD_VALUE - a NULL consumer was provided\n    virtual status_t consumerConnect(const sp<IConsumerListener>& consumer, bool controlledByApp) = 0;\n\n    // consumerDisconnect disconnects a consumer from the BufferQueue. All\n    // buffers will be freed and the BufferQueue is placed in the \"abandoned\"\n    // state, causing most interactions with the BufferQueue by the producer to\n    // fail.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - no consumer is currently connected\n    virtual status_t consumerDisconnect() = 0;\n\n    // getReleasedBuffers sets the value pointed to by slotMask to a bit set.\n    // Each bit index with a 1 corresponds to a released buffer slot with that\n    // index value.  In particular, a released buffer is one that has\n    // been released by the BufferQueue but have not yet been released by the consumer.\n    //\n    // This should be called from the onBuffersReleased() callback.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    virtual status_t getReleasedBuffers(uint64_t* slotMask) = 0;\n\n    // setDefaultBufferSize is used to set the size of buffers returned by\n    // dequeueBuffer when a width and height of zero is requested.  Default\n    // is 1x1.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - either w or h was zero\n    virtual status_t setDefaultBufferSize(uint32_t w, uint32_t h) = 0;\n\n    // setDefaultMaxBufferCount sets the default value for the maximum buffer\n    // count (the initial default is 2). If the producer has requested a\n    // buffer count using setBufferCount, the default buffer count will only\n    // take effect if the producer sets the count back to zero.\n    //\n    // The count must be between 2 and NUM_BUFFER_SLOTS, inclusive.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - bufferCount was out of range (see above).\n    virtual status_t setDefaultMaxBufferCount(int bufferCount) = 0;\n\n    // disableAsyncBuffer disables the extra buffer used in async mode\n    // (when both producer and consumer have set their \"isControlledByApp\"\n    // flag) and has dequeueBuffer() return WOULD_BLOCK instead.\n    //\n    // This can only be called before consumerConnect().\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * INVALID_OPERATION - attempting to call this after consumerConnect.\n    virtual status_t disableAsyncBuffer() = 0;\n\n    // setMaxAcquiredBufferCount sets the maximum number of buffers that can\n    // be acquired by the consumer at one time (default 1).  This call will\n    // fail if a producer is connected to the BufferQueue.\n    //\n    // maxAcquiredBuffers must be (inclusive) between 1 and MAX_MAX_ACQUIRED_BUFFERS.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - maxAcquiredBuffers was out of range (see above).\n    // * INVALID_OPERATION - attempting to call this after a producer connected.\n    virtual status_t setMaxAcquiredBufferCount(int maxAcquiredBuffers) = 0;\n\n    // setConsumerName sets the name used in logging\n    virtual void setConsumerName(const String8& name) = 0;\n\n    // setDefaultBufferFormat allows the BufferQueue to create\n    // GraphicBuffers of a defaultFormat if no format is specified\n    // in dequeueBuffer.\n    // The initial default is PIXEL_FORMAT_RGBA_8888.\n    //\n    // Return of a value other than NO_ERROR means an unknown error has occurred.\n    virtual status_t setDefaultBufferFormat(PixelFormat defaultFormat) = 0;\n\n    // setDefaultBufferDataSpace is a request to the producer to provide buffers\n    // of the indicated dataSpace. The producer may ignore this request.\n    // The initial default is HAL_DATASPACE_UNKNOWN.\n    //\n    // Return of a value other than NO_ERROR means an unknown error has occurred.\n    virtual status_t setDefaultBufferDataSpace(\n            android_dataspace defaultDataSpace) = 0;\n\n    // setConsumerUsageBits will turn on additional usage bits for dequeueBuffer.\n    // These are merged with the bits passed to dequeueBuffer.  The values are\n    // enumerated in gralloc.h, e.g. GRALLOC_USAGE_HW_RENDER; the default is 0.\n    //\n    // Return of a value other than NO_ERROR means an unknown error has occurred.\n    virtual status_t setConsumerUsageBits(uint32_t usage) = 0;\n\n    // setTransformHint bakes in rotation to buffers so overlays can be used.\n    // The values are enumerated in window.h, e.g.\n    // NATIVE_WINDOW_TRANSFORM_ROT_90.  The default is 0 (no transform).\n    //\n    // Return of a value other than NO_ERROR means an unknown error has occurred.\n    virtual status_t setTransformHint(uint32_t hint) = 0;\n\n    // Retrieve the sideband buffer stream, if any.\n    virtual sp<NativeHandle> getSidebandStream() const = 0;\n\n    // dump state into a string\n    virtual void dump(String8& result, const char* prefix) const = 0;\n\npublic:\n    DECLARE_META_INTERFACE(GraphicBufferConsumer);\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnGraphicBufferConsumer : public BnInterface<IGraphicBufferConsumer>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_IGRAPHICBUFFERCONSUMER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/IGraphicBufferProducer.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_IGRAPHICBUFFERPRODUCER_H\n#define ANDROID_GUI_IGRAPHICBUFFERPRODUCER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n\n#include <binder/IInterface.h>\n\n#include <ui/Fence.h>\n#include <ui/GraphicBuffer.h>\n#include <ui/Rect.h>\n#include <ui/Region.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass IProducerListener;\nclass NativeHandle;\nclass Surface;\n\n/*\n * This class defines the Binder IPC interface for the producer side of\n * a queue of graphics buffers.  It's used to send graphics data from one\n * component to another.  For example, a class that decodes video for\n * playback might use this to provide frames.  This is typically done\n * indirectly, through Surface.\n *\n * The underlying mechanism is a BufferQueue, which implements\n * BnGraphicBufferProducer.  In normal operation, the producer calls\n * dequeueBuffer() to get an empty buffer, fills it with data, then\n * calls queueBuffer() to make it available to the consumer.\n *\n * This class was previously called ISurfaceTexture.\n */\nclass IGraphicBufferProducer : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(GraphicBufferProducer);\n\n    enum {\n        // A flag returned by dequeueBuffer when the client needs to call\n        // requestBuffer immediately thereafter.\n        BUFFER_NEEDS_REALLOCATION = 0x1,\n        // A flag returned by dequeueBuffer when all mirrored slots should be\n        // released by the client. This flag should always be processed first.\n        RELEASE_ALL_BUFFERS       = 0x2,\n    };\n\n    // requestBuffer requests a new buffer for the given index. The server (i.e.\n    // the IGraphicBufferProducer implementation) assigns the newly created\n    // buffer to the given slot index, and the client is expected to mirror the\n    // slot->buffer mapping so that it's not necessary to transfer a\n    // GraphicBuffer for every dequeue operation.\n    //\n    // The slot must be in the range of [0, NUM_BUFFER_SLOTS).\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - one of the two conditions occurred:\n    //              * slot was out of range (see above)\n    //              * buffer specified by the slot is not dequeued\n    virtual status_t requestBuffer(int slot, sp<GraphicBuffer>* buf) = 0;\n\n    // setBufferCount sets the number of buffer slots available. Calling this\n    // will also cause all buffer slots to be emptied. The caller should empty\n    // its mirrored copy of the buffer slots when calling this method.\n    //\n    // This function should not be called when there are any dequeued buffer\n    // slots, doing so will result in a BAD_VALUE error returned.\n    //\n    // The buffer count should be at most NUM_BUFFER_SLOTS (inclusive), but at least\n    // the minimum undequeued buffer count (exclusive). The minimum value\n    // can be obtained by calling query(NATIVE_WINDOW_MIN_UNDEQUEUED_BUFFERS).\n    // In particular the range is (minUndequeudBuffers, NUM_BUFFER_SLOTS].\n    //\n    // The buffer count may also be set to 0 (the default), to indicate that\n    // the producer does not wish to set a value.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - one of the below conditions occurred:\n    //              * bufferCount was out of range (see above)\n    //              * client has one or more buffers dequeued\n    virtual status_t setBufferCount(int bufferCount) = 0;\n\n    // dequeueBuffer requests a new buffer slot for the client to use. Ownership\n    // of the slot is transfered to the client, meaning that the server will not\n    // use the contents of the buffer associated with that slot.\n    //\n    // The slot index returned may or may not contain a buffer (client-side).\n    // If the slot is empty the client should call requestBuffer to assign a new\n    // buffer to that slot.\n    //\n    // Once the client is done filling this buffer, it is expected to transfer\n    // buffer ownership back to the server with either cancelBuffer on\n    // the dequeued slot or to fill in the contents of its associated buffer\n    // contents and call queueBuffer.\n    //\n    // If dequeueBuffer returns the BUFFER_NEEDS_REALLOCATION flag, the client is\n    // expected to call requestBuffer immediately.\n    //\n    // If dequeueBuffer returns the RELEASE_ALL_BUFFERS flag, the client is\n    // expected to release all of the mirrored slot->buffer mappings.\n    //\n    // The fence parameter will be updated to hold the fence associated with\n    // the buffer. The contents of the buffer must not be overwritten until the\n    // fence signals. If the fence is Fence::NO_FENCE, the buffer may be written\n    // immediately.\n    //\n    // The async parameter sets whether we're in asynchronous mode for this\n    // dequeueBuffer() call.\n    //\n    // The width and height parameters must be no greater than the minimum of\n    // GL_MAX_VIEWPORT_DIMS and GL_MAX_TEXTURE_SIZE (see: glGetIntegerv).\n    // An error due to invalid dimensions might not be reported until\n    // updateTexImage() is called.  If width and height are both zero, the\n    // default values specified by setDefaultBufferSize() are used instead.\n    //\n    // If the format is 0, the default format will be used.\n    //\n    // The usage argument specifies gralloc buffer usage flags.  The values\n    // are enumerated in <gralloc.h>, e.g. GRALLOC_USAGE_HW_RENDER.  These\n    // will be merged with the usage flags specified by\n    // IGraphicBufferConsumer::setConsumerUsageBits.\n    //\n    // This call will block until a buffer is available to be dequeued. If\n    // both the producer and consumer are controlled by the app, then this call\n    // can never block and will return WOULD_BLOCK if no buffer is available.\n    //\n    // A non-negative value with flags set (see above) will be returned upon\n    // success.\n    //\n    // Return of a negative means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - both in async mode and buffer count was less than the\n    //               max numbers of buffers that can be allocated at once.\n    // * INVALID_OPERATION - cannot attach the buffer because it would cause\n    //                       too many buffers to be dequeued, either because\n    //                       the producer already has a single buffer dequeued\n    //                       and did not set a buffer count, or because a\n    //                       buffer count was set and this call would cause\n    //                       it to be exceeded.\n    // * WOULD_BLOCK - no buffer is currently available, and blocking is disabled\n    //                 since both the producer/consumer are controlled by app\n    // * NO_MEMORY - out of memory, cannot allocate the graphics buffer.\n    //\n    // All other negative values are an unknown error returned downstream\n    // from the graphics allocator (typically errno).\n    virtual status_t dequeueBuffer(int* slot, sp<Fence>* fence, bool async,\n            uint32_t w, uint32_t h, PixelFormat format, uint32_t usage) = 0;\n\n    // detachBuffer attempts to remove all ownership of the buffer in the given\n    // slot from the buffer queue. If this call succeeds, the slot will be\n    // freed, and there will be no way to obtain the buffer from this interface.\n    // The freed slot will remain unallocated until either it is selected to\n    // hold a freshly allocated buffer in dequeueBuffer or a buffer is attached\n    // to the slot. The buffer must have already been dequeued, and the caller\n    // must already possesses the sp<GraphicBuffer> (i.e., must have called\n    // requestBuffer).\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - the given slot number is invalid, either because it is\n    //               out of the range [0, NUM_BUFFER_SLOTS), or because the slot\n    //               it refers to is not currently dequeued and requested.\n    virtual status_t detachBuffer(int slot) = 0;\n\n    // detachNextBuffer is equivalent to calling dequeueBuffer, requestBuffer,\n    // and detachBuffer in sequence, except for two things:\n    //\n    // 1) It is unnecessary to know the dimensions, format, or usage of the\n    //    next buffer.\n    // 2) It will not block, since if it cannot find an appropriate buffer to\n    //    return, it will return an error instead.\n    //\n    // Only slots that are free but still contain a GraphicBuffer will be\n    // considered, and the oldest of those will be returned. outBuffer is\n    // equivalent to outBuffer from the requestBuffer call, and outFence is\n    // equivalent to fence from the dequeueBuffer call.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - either outBuffer or outFence were NULL.\n    // * NO_MEMORY - no slots were found that were both free and contained a\n    //               GraphicBuffer.\n    virtual status_t detachNextBuffer(sp<GraphicBuffer>* outBuffer,\n            sp<Fence>* outFence) = 0;\n\n    // attachBuffer attempts to transfer ownership of a buffer to the buffer\n    // queue. If this call succeeds, it will be as if this buffer was dequeued\n    // from the returned slot number. As such, this call will fail if attaching\n    // this buffer would cause too many buffers to be simultaneously dequeued.\n    //\n    // If attachBuffer returns the RELEASE_ALL_BUFFERS flag, the caller is\n    // expected to release all of the mirrored slot->buffer mappings.\n    //\n    // A non-negative value with flags set (see above) will be returned upon\n    // success.\n    //\n    // Return of a negative value means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - outSlot or buffer were NULL, invalid combination of\n    //               async mode and buffer count override, or the generation\n    //               number of the buffer did not match the buffer queue.\n    // * INVALID_OPERATION - cannot attach the buffer because it would cause\n    //                       too many buffers to be dequeued, either because\n    //                       the producer already has a single buffer dequeued\n    //                       and did not set a buffer count, or because a\n    //                       buffer count was set and this call would cause\n    //                       it to be exceeded.\n    // * WOULD_BLOCK - no buffer slot is currently available, and blocking is\n    //                 disabled since both the producer/consumer are\n    //                 controlled by the app.\n    virtual status_t attachBuffer(int* outSlot,\n            const sp<GraphicBuffer>& buffer) = 0;\n\n    // queueBuffer indicates that the client has finished filling in the\n    // contents of the buffer associated with slot and transfers ownership of\n    // that slot back to the server.\n    //\n    // It is not valid to call queueBuffer on a slot that is not owned\n    // by the client or one for which a buffer associated via requestBuffer\n    // (an attempt to do so will fail with a return value of BAD_VALUE).\n    //\n    // In addition, the input must be described by the client (as documented\n    // below). Any other properties (zero point, etc)\n    // are client-dependent, and should be documented by the client.\n    //\n    // The slot must be in the range of [0, NUM_BUFFER_SLOTS).\n    //\n    // Upon success, the output will be filled with meaningful values\n    // (refer to the documentation below).\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - one of the below conditions occurred:\n    //              * fence was NULL\n    //              * scaling mode was unknown\n    //              * both in async mode and buffer count was less than the\n    //                max numbers of buffers that can be allocated at once\n    //              * slot index was out of range (see above).\n    //              * the slot was not in the dequeued state\n    //              * the slot was enqueued without requesting a buffer\n    //              * crop rect is out of bounds of the buffer dimensions\n\n    struct QueueBufferInput : public Flattenable<QueueBufferInput> {\n        friend class Flattenable<QueueBufferInput>;\n        inline QueueBufferInput(const Parcel& parcel);\n        // timestamp - a monotonically increasing value in nanoseconds\n        // isAutoTimestamp - if the timestamp was synthesized at queue time\n        // dataSpace - description of the contents, interpretation depends on format\n        // crop - a crop rectangle that's used as a hint to the consumer\n        // scalingMode - a set of flags from NATIVE_WINDOW_SCALING_* in <window.h>\n        // transform - a set of flags from NATIVE_WINDOW_TRANSFORM_* in <window.h>\n        // async - if the buffer is queued in asynchronous mode\n        // fence - a fence that the consumer must wait on before reading the buffer,\n        //         set this to Fence::NO_FENCE if the buffer is ready immediately\n        // sticky - the sticky transform set in Surface (only used by the LEGACY\n        //          camera mode).\n        inline QueueBufferInput(int64_t timestamp, bool isAutoTimestamp,\n                android_dataspace dataSpace, const Rect& crop, int scalingMode,\n                uint32_t transform, bool async, const sp<Fence>& fence,\n                uint32_t sticky = 0)\n                : timestamp(timestamp), isAutoTimestamp(isAutoTimestamp),\n                  dataSpace(dataSpace), crop(crop), scalingMode(scalingMode),\n                  transform(transform), stickyTransform(sticky),\n                  async(async), fence(fence), surfaceDamage() { }\n        inline void deflate(int64_t* outTimestamp, bool* outIsAutoTimestamp,\n                android_dataspace* outDataSpace,\n                Rect* outCrop, int* outScalingMode,\n                uint32_t* outTransform, bool* outAsync, sp<Fence>* outFence,\n                uint32_t* outStickyTransform = NULL) const {\n            *outTimestamp = timestamp;\n            *outIsAutoTimestamp = bool(isAutoTimestamp);\n            *outDataSpace = dataSpace;\n            *outCrop = crop;\n            *outScalingMode = scalingMode;\n            *outTransform = transform;\n            *outAsync = bool(async);\n            *outFence = fence;\n            if (outStickyTransform != NULL) {\n                *outStickyTransform = stickyTransform;\n            }\n        }\n\n        // Flattenable protocol\n        size_t getFlattenedSize() const;\n        size_t getFdCount() const;\n        status_t flatten(void*& buffer, size_t& size, int*& fds, size_t& count) const;\n        status_t unflatten(void const*& buffer, size_t& size, int const*& fds, size_t& count);\n\n        const Region& getSurfaceDamage() const { return surfaceDamage; }\n        void setSurfaceDamage(const Region& damage) { surfaceDamage = damage; }\n\n    private:\n        int64_t timestamp;\n        int isAutoTimestamp;\n        android_dataspace dataSpace;\n        Rect crop;\n        int scalingMode;\n        uint32_t transform;\n        uint32_t stickyTransform;\n        int async;\n        sp<Fence> fence;\n        Region surfaceDamage;\n    };\n\n    // QueueBufferOutput must be a POD structure\n    struct __attribute__ ((__packed__)) QueueBufferOutput {\n        inline QueueBufferOutput() { }\n        // outWidth - filled with default width applied to the buffer\n        // outHeight - filled with default height applied to the buffer\n        // outTransformHint - filled with default transform applied to the buffer\n        // outNumPendingBuffers - num buffers queued that haven't yet been acquired\n        //                        (counting the currently queued buffer)\n        inline void deflate(uint32_t* outWidth,\n                uint32_t* outHeight,\n                uint32_t* outTransformHint,\n                uint32_t* outNumPendingBuffers) const {\n            *outWidth = width;\n            *outHeight = height;\n            *outTransformHint = transformHint;\n            *outNumPendingBuffers = numPendingBuffers;\n        }\n        inline void inflate(uint32_t inWidth, uint32_t inHeight,\n                uint32_t inTransformHint, uint32_t inNumPendingBuffers) {\n            width = inWidth;\n            height = inHeight;\n            transformHint = inTransformHint;\n            numPendingBuffers = inNumPendingBuffers;\n        }\n    private:\n        uint32_t width;\n        uint32_t height;\n        uint32_t transformHint;\n        uint32_t numPendingBuffers;\n    };\n\n    virtual status_t queueBuffer(int slot,\n            const QueueBufferInput& input, QueueBufferOutput* output) = 0;\n\n    // cancelBuffer indicates that the client does not wish to fill in the\n    // buffer associated with slot and transfers ownership of the slot back to\n    // the server.\n    //\n    // The buffer is not queued for use by the consumer.\n    //\n    // The buffer will not be overwritten until the fence signals.  The fence\n    // will usually be the one obtained from dequeueBuffer.\n    virtual void cancelBuffer(int slot, const sp<Fence>& fence) = 0;\n\n    // query retrieves some information for this surface\n    // 'what' tokens allowed are that of NATIVE_WINDOW_* in <window.h>\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - the buffer queue has been abandoned.\n    // * BAD_VALUE - what was out of range\n    virtual int query(int what, int* value) = 0;\n\n    // connect attempts to connect a client API to the IGraphicBufferProducer.\n    // This must be called before any other IGraphicBufferProducer methods are\n    // called except for getAllocator. A consumer must be already connected.\n    //\n    // This method will fail if the connect was previously called on the\n    // IGraphicBufferProducer and no corresponding disconnect call was made.\n    //\n    // The listener is an optional binder callback object that can be used if\n    // the producer wants to be notified when the consumer releases a buffer\n    // back to the BufferQueue. It is also used to detect the death of the\n    // producer. If only the latter functionality is desired, there is a\n    // DummyProducerListener class in IProducerListener.h that can be used.\n    //\n    // The api should be one of the NATIVE_WINDOW_API_* values in <window.h>\n    //\n    // The producerControlledByApp should be set to true if the producer is hosted\n    // by an untrusted process (typically app_process-forked processes). If both\n    // the producer and the consumer are app-controlled then all buffer queues\n    // will operate in async mode regardless of the async flag.\n    //\n    // Upon success, the output will be filled with meaningful data\n    // (refer to QueueBufferOutput documentation above).\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * NO_INIT - one of the following occurred:\n    //             * the buffer queue was abandoned\n    //             * no consumer has yet connected\n    // * BAD_VALUE - one of the following has occurred:\n    //             * the producer is already connected\n    //             * api was out of range (see above).\n    //             * output was NULL.\n    // * DEAD_OBJECT - the token is hosted by an already-dead process\n    //\n    // Additional negative errors may be returned by the internals, they\n    // should be treated as opaque fatal unrecoverable errors.\n    virtual status_t connect(const sp<IProducerListener>& listener,\n            int api, bool producerControlledByApp, QueueBufferOutput* output) = 0;\n\n    // disconnect attempts to disconnect a client API from the\n    // IGraphicBufferProducer.  Calling this method will cause any subsequent\n    // calls to other IGraphicBufferProducer methods to fail except for\n    // getAllocator and connect.  Successfully calling connect after this will\n    // allow the other methods to succeed again.\n    //\n    // This method will fail if the the IGraphicBufferProducer is not currently\n    // connected to the specified client API.\n    //\n    // The api should be one of the NATIVE_WINDOW_API_* values in <window.h>\n    //\n    // Disconnecting from an abandoned IGraphicBufferProducer is legal and\n    // is considered a no-op.\n    //\n    // Return of a value other than NO_ERROR means an error has occurred:\n    // * BAD_VALUE - one of the following has occurred:\n    //             * the api specified does not match the one that was connected\n    //             * api was out of range (see above).\n    // * DEAD_OBJECT - the token is hosted by an already-dead process\n    virtual status_t disconnect(int api) = 0;\n\n    // Attaches a sideband buffer stream to the IGraphicBufferProducer.\n    //\n    // A sideband stream is a device-specific mechanism for passing buffers\n    // from the producer to the consumer without using dequeueBuffer/\n    // queueBuffer. If a sideband stream is present, the consumer can choose\n    // whether to acquire buffers from the sideband stream or from the queued\n    // buffers.\n    //\n    // Passing NULL or a different stream handle will detach the previous\n    // handle if any.\n    virtual status_t setSidebandStream(const sp<NativeHandle>& stream) = 0;\n\n    // Allocates buffers based on the given dimensions/format.\n    //\n    // This function will allocate up to the maximum number of buffers\n    // permitted by the current BufferQueue configuration. It will use the\n    // given format, dimensions, and usage bits, which are interpreted in the\n    // same way as for dequeueBuffer, and the async flag must be set the same\n    // way as for dequeueBuffer to ensure that the correct number of buffers are\n    // allocated. This is most useful to avoid an allocation delay during\n    // dequeueBuffer. If there are already the maximum number of buffers\n    // allocated, this function has no effect.\n    virtual void allocateBuffers(bool async, uint32_t width, uint32_t height,\n            PixelFormat format, uint32_t usage) = 0;\n\n    // Sets whether dequeueBuffer is allowed to allocate new buffers.\n    //\n    // Normally dequeueBuffer does not discriminate between free slots which\n    // already have an allocated buffer and those which do not, and will\n    // allocate a new buffer if the slot doesn't have a buffer or if the slot's\n    // buffer doesn't match the requested size, format, or usage. This method\n    // allows the producer to restrict the eligible slots to those which already\n    // have an allocated buffer of the correct size, format, and usage. If no\n    // eligible slot is available, dequeueBuffer will block or return an error\n    // as usual.\n    virtual status_t allowAllocation(bool allow) = 0;\n\n    // Sets the current generation number of the BufferQueue.\n    //\n    // This generation number will be inserted into any buffers allocated by the\n    // BufferQueue, and any attempts to attach a buffer with a different\n    // generation number will fail. Buffers already in the queue are not\n    // affected and will retain their current generation number. The generation\n    // number defaults to 0.\n    virtual status_t setGenerationNumber(uint32_t generationNumber) = 0;\n\n    // Returns the name of the connected consumer.\n    virtual String8 getConsumerName() const = 0;\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnGraphicBufferProducer : public BnInterface<IGraphicBufferProducer>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_IGRAPHICBUFFERPRODUCER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/IProducerListener.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_IPRODUCERLISTENER_H\n#define ANDROID_GUI_IPRODUCERLISTENER_H\n\n#include <binder/IInterface.h>\n\n#include <utils/RefBase.h>\n\nnamespace android {\n\n// ProducerListener is the interface through which the BufferQueue notifies the\n// producer of events that the producer may wish to react to. Because the\n// producer will generally have a mutex that is locked during calls from the\n// producer to the BufferQueue, these calls from the BufferQueue to the\n// producer *MUST* be called only when the BufferQueue mutex is NOT locked.\n\nclass ProducerListener : public virtual RefBase\n{\npublic:\n    ProducerListener() {}\n    virtual ~ProducerListener() {}\n\n    // onBufferReleased is called from IGraphicBufferConsumer::releaseBuffer to\n    // notify the producer that a new buffer is free and ready to be dequeued.\n    //\n    // This is called without any lock held and can be called concurrently by\n    // multiple threads.\n    virtual void onBufferReleased() = 0; // Asynchronous\n};\n\nclass IProducerListener : public ProducerListener, public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(ProducerListener)\n};\n\nclass BnProducerListener : public BnInterface<IProducerListener>\n{\npublic:\n    virtual status_t onTransact(uint32_t code, const Parcel& data,\n            Parcel* reply, uint32_t flags = 0);\n};\n\nclass DummyProducerListener : public BnProducerListener\n{\npublic:\n    virtual void onBufferReleased() {}\n};\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/ISensorEventConnection.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_ISENSOR_EVENT_CONNECTION_H\n#define ANDROID_GUI_ISENSOR_EVENT_CONNECTION_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n\n#include <binder/IInterface.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass BitTube;\n\nclass ISensorEventConnection : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(SensorEventConnection);\n\n    virtual sp<BitTube> getSensorChannel() const = 0;\n    virtual status_t enableDisable(int handle, bool enabled, nsecs_t samplingPeriodNs,\n                                   nsecs_t maxBatchReportLatencyNs, int reservedFlags) = 0;\n    virtual status_t setEventRate(int handle, nsecs_t ns) = 0;\n    virtual status_t flush() = 0;\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnSensorEventConnection : public BnInterface<ISensorEventConnection>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_ISENSOR_EVENT_CONNECTION_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/ISensorServer.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_ISENSORSERVER_H\n#define ANDROID_GUI_ISENSORSERVER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n\n#include <binder/IInterface.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass Sensor;\nclass ISensorEventConnection;\nclass String8;\n\nclass ISensorServer : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(SensorServer);\n\n    virtual Vector<Sensor> getSensorList(const String16& opPackageName) = 0;\n    virtual sp<ISensorEventConnection> createSensorEventConnection(const String8& packageName,\n             int mode, const String16& opPackageName) = 0;\n    virtual int32_t isDataInjectionEnabled() = 0;\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnSensorServer : public BnInterface<ISensorServer>\n{\npublic:\n    virtual status_t    onTransact( uint32_t code,\n                                    const Parcel& data,\n                                    Parcel* reply,\n                                    uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_ISENSORSERVER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/ISurfaceComposer.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_ISURFACE_COMPOSER_H\n#define ANDROID_GUI_ISURFACE_COMPOSER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/RefBase.h>\n#include <utils/Errors.h>\n#include <utils/Timers.h>\n#include <utils/Vector.h>\n\n#include <binder/IInterface.h>\n\n#include <ui/FrameStats.h>\n\n#include <gui/IGraphicBufferAlloc.h>\n#include <gui/ISurfaceComposerClient.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass ComposerState;\nclass DisplayState;\nstruct DisplayInfo;\nstruct DisplayStatInfo;\nclass IDisplayEventConnection;\nclass IMemoryHeap;\nclass Rect;\n\n/*\n * This class defines the Binder IPC interface for accessing various\n * SurfaceFlinger features.\n */\nclass ISurfaceComposer: public IInterface {\npublic:\n    DECLARE_META_INTERFACE(SurfaceComposer);\n\n    // flags for setTransactionState()\n    enum {\n        eSynchronous = 0x01,\n        eAnimation   = 0x02,\n    };\n\n    enum {\n        eDisplayIdMain = 0,\n        eDisplayIdHdmi = 1,\n#ifdef QTI_BSP\n        eDisplayIdTertiary = 2\n#endif\n    };\n\n    enum Rotation {\n        eRotateNone = 0,\n        eRotate90   = 1,\n        eRotate180  = 2,\n        eRotate270  = 3\n    };\n\n    /* create connection with surface flinger, requires\n     * ACCESS_SURFACE_FLINGER permission\n     */\n    virtual sp<ISurfaceComposerClient> createConnection() = 0;\n\n    /* create a graphic buffer allocator\n     */\n    virtual sp<IGraphicBufferAlloc> createGraphicBufferAlloc() = 0;\n\n    /* return an IDisplayEventConnection */\n    virtual sp<IDisplayEventConnection> createDisplayEventConnection() = 0;\n\n    /* create a virtual display\n     * requires ACCESS_SURFACE_FLINGER permission.\n     */\n    virtual sp<IBinder> createDisplay(const String8& displayName,\n            bool secure) = 0;\n\n    /* destroy a virtual display\n     * requires ACCESS_SURFACE_FLINGER permission.\n     */\n    virtual void destroyDisplay(const sp<IBinder>& display) = 0;\n\n    /* get the token for the existing default displays. possible values\n     * for id are eDisplayIdMain and eDisplayIdHdmi.\n     */\n    virtual sp<IBinder> getBuiltInDisplay(int32_t id) = 0;\n\n    /* open/close transactions. requires ACCESS_SURFACE_FLINGER permission */\n    virtual void setTransactionState(const Vector<ComposerState>& state,\n            const Vector<DisplayState>& displays, uint32_t flags) = 0;\n\n    /* signal that we're done booting.\n     * Requires ACCESS_SURFACE_FLINGER permission\n     */\n    virtual void bootFinished() = 0;\n\n    /* verify that an IGraphicBufferProducer was created by SurfaceFlinger.\n     */\n    virtual bool authenticateSurfaceTexture(\n            const sp<IGraphicBufferProducer>& surface) const = 0;\n\n    /* set display power mode. depending on the mode, it can either trigger\n     * screen on, off or low power mode and wait for it to complete.\n     * requires ACCESS_SURFACE_FLINGER permission.\n     */\n    virtual void setPowerMode(const sp<IBinder>& display, int mode) = 0;\n\n    /* returns information for each configuration of the given display\n     * intended to be used to get information about built-in displays */\n    virtual status_t getDisplayConfigs(const sp<IBinder>& display,\n            Vector<DisplayInfo>* configs) = 0;\n\n    /* returns display statistics for a given display\n     * intended to be used by the media framework to properly schedule\n     * video frames */\n    virtual status_t getDisplayStats(const sp<IBinder>& display,\n            DisplayStatInfo* stats) = 0;\n\n    /* indicates which of the configurations returned by getDisplayInfo is\n     * currently active */\n    virtual int getActiveConfig(const sp<IBinder>& display) = 0;\n\n    /* specifies which configuration (of those returned by getDisplayInfo)\n     * should be used */\n    virtual status_t setActiveConfig(const sp<IBinder>& display, int id) = 0;\n\n    /* Capture the specified screen. requires READ_FRAME_BUFFER permission\n     * This function will fail if there is a secure window on screen.\n     */\n    virtual status_t captureScreen(const sp<IBinder>& display,\n            const sp<IGraphicBufferProducer>& producer,\n            Rect sourceCrop, uint32_t reqWidth, uint32_t reqHeight,\n            uint32_t minLayerZ, uint32_t maxLayerZ,\n            bool useIdentityTransform,\n            Rotation rotation = eRotateNone,\n            bool isCpuConsumer = false) = 0;\n\n    /* Clears the frame statistics for animations.\n     *\n     * Requires the ACCESS_SURFACE_FLINGER permission.\n     */\n    virtual status_t clearAnimationFrameStats() = 0;\n\n    /* Gets the frame statistics for animations.\n     *\n     * Requires the ACCESS_SURFACE_FLINGER permission.\n     */\n    virtual status_t getAnimationFrameStats(FrameStats* outStats) const = 0;\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnSurfaceComposer: public BnInterface<ISurfaceComposer> {\npublic:\n    enum {\n        // Note: BOOT_FINISHED must remain this value, it is called from\n        // Java by ActivityManagerService.\n        BOOT_FINISHED = IBinder::FIRST_CALL_TRANSACTION,\n        CREATE_CONNECTION,\n        CREATE_GRAPHIC_BUFFER_ALLOC,\n        CREATE_DISPLAY_EVENT_CONNECTION,\n        CREATE_DISPLAY,\n        DESTROY_DISPLAY,\n        GET_BUILT_IN_DISPLAY,\n        SET_TRANSACTION_STATE,\n        AUTHENTICATE_SURFACE,\n        GET_DISPLAY_CONFIGS,\n        GET_ACTIVE_CONFIG,\n        SET_ACTIVE_CONFIG,\n        CONNECT_DISPLAY,\n        CAPTURE_SCREEN,\n        CLEAR_ANIMATION_FRAME_STATS,\n        GET_ANIMATION_FRAME_STATS,\n        SET_POWER_MODE,\n        GET_DISPLAY_STATS,\n    };\n\n    virtual status_t onTransact(uint32_t code, const Parcel& data,\n            Parcel* reply, uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_GUI_ISURFACE_COMPOSER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/ISurfaceComposerClient.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_ISURFACE_COMPOSER_CLIENT_H\n#define ANDROID_GUI_ISURFACE_COMPOSER_CLIENT_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n\n#include <binder/IInterface.h>\n\n#include <ui/FrameStats.h>\n#include <ui/PixelFormat.h>\n\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass IGraphicBufferProducer;\n\nclass ISurfaceComposerClient : public IInterface\n{\npublic:\n    DECLARE_META_INTERFACE(SurfaceComposerClient);\n\n    // flags for createSurface()\n    enum { // (keep in sync with Surface.java)\n        eHidden             = 0x00000004,\n        eDestroyBackbuffer  = 0x00000020,\n        eSecure             = 0x00000080,\n        eNonPremultiplied   = 0x00000100,\n        eOpaque             = 0x00000400,\n        eProtectedByApp     = 0x00000800,\n        eProtectedByDRM     = 0x00001000,\n        eCursorWindow       = 0x00002000,\n\n        eFXSurfaceNormal    = 0x00000000,\n        eFXSurfaceBlur      = 0x00010000,\n        eFXSurfaceDim       = 0x00020000,\n        eFXSurfaceMask      = 0x000F0000,\n    };\n\n    /*\n     * Requires ACCESS_SURFACE_FLINGER permission\n     */\n    virtual status_t createSurface(\n            const String8& name, uint32_t w, uint32_t h,\n            PixelFormat format, uint32_t flags,\n            sp<IBinder>* handle,\n            sp<IGraphicBufferProducer>* gbp) = 0;\n\n    /*\n     * Requires ACCESS_SURFACE_FLINGER permission\n     */\n    virtual status_t destroySurface(const sp<IBinder>& handle) = 0;\n\n    /*\n     * Requires ACCESS_SURFACE_FLINGER permission\n     */\n    virtual status_t clearLayerFrameStats(const sp<IBinder>& handle) const = 0;\n\n    /*\n     * Requires ACCESS_SURFACE_FLINGER permission\n     */\n    virtual status_t getLayerFrameStats(const sp<IBinder>& handle, FrameStats* outStats) const = 0;\n};\n\n// ----------------------------------------------------------------------------\n\nclass BnSurfaceComposerClient: public BnInterface<ISurfaceComposerClient> {\npublic:\n    virtual status_t onTransact(uint32_t code, const Parcel& data,\n            Parcel* reply, uint32_t flags = 0);\n};\n\n// ----------------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_GUI_ISURFACE_COMPOSER_CLIENT_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/Sensor.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_SENSOR_H\n#define ANDROID_GUI_SENSOR_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/Flattenable.h>\n#include <utils/String8.h>\n#include <utils/Timers.h>\n\n#include <hardware/sensors.h>\n\n#include <android/sensor.h>\n\n// ----------------------------------------------------------------------------\n// Concrete types for the NDK\nstruct ASensor { };\n\n// ----------------------------------------------------------------------------\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass Parcel;\n\n// ----------------------------------------------------------------------------\n\nclass Sensor : public ASensor, public LightFlattenable<Sensor>\n{\npublic:\n    enum {\n        TYPE_ACCELEROMETER  = ASENSOR_TYPE_ACCELEROMETER,\n        TYPE_MAGNETIC_FIELD = ASENSOR_TYPE_MAGNETIC_FIELD,\n        TYPE_GYROSCOPE      = ASENSOR_TYPE_GYROSCOPE,\n        TYPE_LIGHT          = ASENSOR_TYPE_LIGHT,\n        TYPE_PROXIMITY      = ASENSOR_TYPE_PROXIMITY\n    };\n\n            Sensor();\n            Sensor(struct sensor_t const* hwSensor, int halVersion = 0);\n            ~Sensor();\n\n    const String8& getName() const;\n    const String8& getVendor() const;\n    int32_t getHandle() const;\n    int32_t getType() const;\n    float getMinValue() const;\n    float getMaxValue() const;\n    float getResolution() const;\n    float getPowerUsage() const;\n    int32_t getMinDelay() const;\n    nsecs_t getMinDelayNs() const;\n    int32_t getVersion() const;\n    uint32_t getFifoReservedEventCount() const;\n    uint32_t getFifoMaxEventCount() const;\n    const String8& getStringType() const;\n    const String8& getRequiredPermission() const;\n    bool isRequiredPermissionRuntime() const;\n    int32_t getRequiredAppOp() const;\n    int32_t getMaxDelay() const;\n    uint32_t getFlags() const;\n    bool isWakeUpSensor() const;\n    int32_t getReportingMode() const;\n\n    // LightFlattenable protocol\n    inline bool isFixedSize() const { return false; }\n    size_t getFlattenedSize() const;\n    status_t flatten(void* buffer, size_t size) const;\n    status_t unflatten(void const* buffer, size_t size);\n\nprivate:\n    String8 mName;\n    String8 mVendor;\n    int32_t mHandle;\n    int32_t mType;\n    float   mMinValue;\n    float   mMaxValue;\n    float   mResolution;\n    float   mPower;\n    int32_t mMinDelay;\n    int32_t mVersion;\n    uint32_t mFifoReservedEventCount;\n    uint32_t mFifoMaxEventCount;\n    String8 mStringType;\n    String8 mRequiredPermission;\n    bool mRequiredPermissionRuntime = false;\n    int32_t mRequiredAppOp;\n    int32_t mMaxDelay;\n    uint32_t mFlags;\n    static void flattenString8(void*& buffer, size_t& size, const String8& string8);\n    static bool unflattenString8(void const*& buffer, size_t& size, String8& outputString8);\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_SENSOR_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/SensorEventQueue.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_SENSOR_EVENT_QUEUE_H\n#define ANDROID_SENSOR_EVENT_QUEUE_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <utils/Timers.h>\n#include <utils/String16.h>\n\n#include <gui/BitTube.h>\n\n// ----------------------------------------------------------------------------\n#define WAKE_UP_SENSOR_EVENT_NEEDS_ACK (1U << 31)\nstruct ALooper;\nstruct ASensorEvent;\n\n// Concrete types for the NDK\nstruct ASensorEventQueue {\n    ALooper* looper;\n};\n\n// ----------------------------------------------------------------------------\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass ISensorEventConnection;\nclass Sensor;\nclass Looper;\n\n// ----------------------------------------------------------------------------\n\nclass SensorEventQueue : public ASensorEventQueue, public RefBase\n{\npublic:\n\n    enum { MAX_RECEIVE_BUFFER_EVENT_COUNT = 256 };\n\n    SensorEventQueue(const sp<ISensorEventConnection>& connection);\n    virtual ~SensorEventQueue();\n    virtual void onFirstRef();\n\n    int getFd() const;\n\n    static ssize_t write(const sp<BitTube>& tube,\n            ASensorEvent const* events, size_t numEvents);\n\n    ssize_t read(ASensorEvent* events, size_t numEvents);\n\n    status_t waitForEvent() const;\n    status_t wake() const;\n\n    status_t enableSensor(Sensor const* sensor) const;\n    status_t disableSensor(Sensor const* sensor) const;\n    status_t setEventRate(Sensor const* sensor, nsecs_t ns) const;\n\n    // these are here only to support SensorManager.java\n    status_t enableSensor(int32_t handle, int32_t samplingPeriodUs, int maxBatchReportLatencyUs,\n                          int reservedFlags) const;\n    status_t disableSensor(int32_t handle) const;\n    status_t flush() const;\n    // Send an ack for every wake_up sensor event that is set to WAKE_UP_SENSOR_EVENT_NEEDS_ACK.\n    void sendAck(const ASensorEvent* events, int count);\n\n    status_t injectSensorEvent(const ASensorEvent& event);\nprivate:\n    sp<Looper> getLooper() const;\n    sp<ISensorEventConnection> mSensorEventConnection;\n    sp<BitTube> mSensorChannel;\n    mutable Mutex mLock;\n    mutable sp<Looper> mLooper;\n    ASensorEvent* mRecBuffer;\n    size_t mAvailable;\n    size_t mConsumed;\n    uint32_t mNumAcksToSend;\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_SENSOR_EVENT_QUEUE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/SensorManager.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_SENSOR_MANAGER_H\n#define ANDROID_GUI_SENSOR_MANAGER_H\n\n#include <map>\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <binder/IBinder.h>\n#include <binder/IPCThreadState.h>\n#include <binder/IServiceManager.h>\n\n#include <utils/Errors.h>\n#include <utils/RefBase.h>\n#include <utils/Singleton.h>\n#include <utils/Vector.h>\n#include <utils/String8.h>\n\n#include <gui/SensorEventQueue.h>\n\n// ----------------------------------------------------------------------------\n// Concrete types for the NDK\nstruct ASensorManager { };\n\n// ----------------------------------------------------------------------------\nnamespace android {\n// ----------------------------------------------------------------------------\n\nclass ISensorServer;\nclass Sensor;\nclass SensorEventQueue;\n// ----------------------------------------------------------------------------\n\nclass SensorManager :\n    public ASensorManager\n{\npublic:\n    static SensorManager& getInstanceForPackage(const String16& packageName);\n    ~SensorManager();\n\n    ssize_t getSensorList(Sensor const* const** list) const;\n    Sensor const* getDefaultSensor(int type);\n    sp<SensorEventQueue> createEventQueue(String8 packageName = String8(\"\"), int mode = 0);\n    bool isDataInjectionEnabled();\n\nprivate:\n    // DeathRecipient interface\n    void sensorManagerDied();\n\n    SensorManager(const String16& opPackageName);\n    status_t assertStateLocked() const;\n\nprivate:\n    static Mutex sLock;\n    static std::map<String16, SensorManager*> sPackageInstances;\n\n    mutable Mutex mLock;\n    mutable sp<ISensorServer> mSensorServer;\n    mutable Sensor const** mSensorList;\n    mutable Vector<Sensor> mSensors;\n    mutable sp<IBinder::DeathRecipient> mDeathObserver;\n    const String16 mOpPackageName;\n};\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_SENSOR_MANAGER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/StreamSplitter.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_STREAMSPLITTER_H\n#define ANDROID_GUI_STREAMSPLITTER_H\n\n#include <gui/IConsumerListener.h>\n#include <gui/IProducerListener.h>\n\n#include <utils/Condition.h>\n#include <utils/KeyedVector.h>\n#include <utils/Mutex.h>\n#include <utils/StrongPointer.h>\n\nnamespace android {\n\nclass GraphicBuffer;\nclass IGraphicBufferConsumer;\nclass IGraphicBufferProducer;\n\n// StreamSplitter is an autonomous class that manages one input BufferQueue\n// and multiple output BufferQueues. By using the buffer attach and detach logic\n// in BufferQueue, it is able to present the illusion of a single split\n// BufferQueue, where each buffer queued to the input is available to be\n// acquired by each of the outputs, and is able to be dequeued by the input\n// again only once all of the outputs have released it.\nclass StreamSplitter : public BnConsumerListener {\npublic:\n    // createSplitter creates a new splitter, outSplitter, using inputQueue as\n    // the input BufferQueue. Output BufferQueues must be added using addOutput\n    // before queueing any buffers to the input.\n    //\n    // A return value other than NO_ERROR means that an error has occurred and\n    // outSplitter has not been modified. BAD_VALUE is returned if inputQueue or\n    // outSplitter is NULL. See IGraphicBufferConsumer::consumerConnect for\n    // explanations of other error codes.\n    static status_t createSplitter(const sp<IGraphicBufferConsumer>& inputQueue,\n            sp<StreamSplitter>* outSplitter);\n\n    // addOutput adds an output BufferQueue to the splitter. The splitter\n    // connects to outputQueue as a CPU producer, and any buffers queued\n    // to the input will be queued to each output. It is assumed that all of the\n    // outputs are added before any buffers are queued on the input. If any\n    // output is abandoned by its consumer, the splitter will abandon its input\n    // queue (see onAbandoned).\n    //\n    // A return value other than NO_ERROR means that an error has occurred and\n    // outputQueue has not been added to the splitter. BAD_VALUE is returned if\n    // outputQueue is NULL. See IGraphicBufferProducer::connect for explanations\n    // of other error codes.\n    status_t addOutput(const sp<IGraphicBufferProducer>& outputQueue);\n\n    // setName sets the consumer name of the input queue\n    void setName(const String8& name);\n\nprivate:\n    // From IConsumerListener\n    //\n    // During this callback, we store some tracking information, detach the\n    // buffer from the input, and attach it to each of the outputs. This call\n    // can block if there are too many outstanding buffers. If it blocks, it\n    // will resume when onBufferReleasedByOutput releases a buffer back to the\n    // input.\n    virtual void onFrameAvailable(const BufferItem& item);\n\n    // From IConsumerListener\n    // We don't care about released buffers because we detach each buffer as\n    // soon as we acquire it. See the comment for onBufferReleased below for\n    // some clarifying notes about the name.\n    virtual void onBuffersReleased() {}\n\n    // From IConsumerListener\n    // We don't care about sideband streams, since we won't be splitting them\n    virtual void onSidebandStreamChanged() {}\n\n    // This is the implementation of the onBufferReleased callback from\n    // IProducerListener. It gets called from an OutputListener (see below), and\n    // 'from' is which producer interface from which the callback was received.\n    //\n    // During this callback, we detach the buffer from the output queue that\n    // generated the callback, update our state tracking to see if this is the\n    // last output releasing the buffer, and if so, release it to the input.\n    // If we release the buffer to the input, we allow a blocked\n    // onFrameAvailable call to proceed.\n    void onBufferReleasedByOutput(const sp<IGraphicBufferProducer>& from);\n\n    // When this is called, the splitter disconnects from (i.e., abandons) its\n    // input queue and signals any waiting onFrameAvailable calls to wake up.\n    // It still processes callbacks from other outputs, but only detaches their\n    // buffers so they can continue operating until they run out of buffers to\n    // acquire. This must be called with mMutex locked.\n    void onAbandonedLocked();\n\n    // This is a thin wrapper class that lets us determine which BufferQueue\n    // the IProducerListener::onBufferReleased callback is associated with. We\n    // create one of these per output BufferQueue, and then pass the producer\n    // into onBufferReleasedByOutput above.\n    class OutputListener : public BnProducerListener,\n                           public IBinder::DeathRecipient {\n    public:\n        OutputListener(const sp<StreamSplitter>& splitter,\n                const sp<IGraphicBufferProducer>& output);\n        virtual ~OutputListener();\n\n        // From IProducerListener\n        virtual void onBufferReleased();\n\n        // From IBinder::DeathRecipient\n        virtual void binderDied(const wp<IBinder>& who);\n\n    private:\n        sp<StreamSplitter> mSplitter;\n        sp<IGraphicBufferProducer> mOutput;\n    };\n\n    class BufferTracker : public LightRefBase<BufferTracker> {\n    public:\n        BufferTracker(const sp<GraphicBuffer>& buffer);\n\n        const sp<GraphicBuffer>& getBuffer() const { return mBuffer; }\n        const sp<Fence>& getMergedFence() const { return mMergedFence; }\n\n        void mergeFence(const sp<Fence>& with);\n\n        // Returns the new value\n        // Only called while mMutex is held\n        size_t incrementReleaseCountLocked() { return ++mReleaseCount; }\n\n    private:\n        // Only destroy through LightRefBase\n        friend LightRefBase<BufferTracker>;\n        ~BufferTracker();\n\n        // Disallow copying\n        BufferTracker(const BufferTracker& other);\n        BufferTracker& operator=(const BufferTracker& other);\n\n        sp<GraphicBuffer> mBuffer; // One instance that holds this native handle\n        sp<Fence> mMergedFence;\n        size_t mReleaseCount;\n    };\n\n    // Only called from createSplitter\n    StreamSplitter(const sp<IGraphicBufferConsumer>& inputQueue);\n\n    // Must be accessed through RefBase\n    virtual ~StreamSplitter();\n\n    static const int MAX_OUTSTANDING_BUFFERS = 2;\n\n    // mIsAbandoned is set to true when an output dies. Once the StreamSplitter\n    // has been abandoned, it will continue to detach buffers from other\n    // outputs, but it will disconnect from the input and not attempt to\n    // communicate with it further.\n    bool mIsAbandoned;\n\n    Mutex mMutex;\n    Condition mReleaseCondition;\n    int mOutstandingBuffers;\n    sp<IGraphicBufferConsumer> mInput;\n    Vector<sp<IGraphicBufferProducer> > mOutputs;\n\n    // Map of GraphicBuffer IDs (GraphicBuffer::getId()) to buffer tracking\n    // objects (which are mostly for counting how many outputs have released the\n    // buffer, but also contain merged release fences).\n    KeyedVector<uint64_t, sp<BufferTracker> > mBuffers;\n};\n\n} // namespace android\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/Surface.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_SURFACE_H\n#define ANDROID_GUI_SURFACE_H\n\n#include <gui/IGraphicBufferProducer.h>\n#include <gui/BufferQueue.h>\n\n#include <ui/ANativeObjectBase.h>\n#include <ui/Region.h>\n\n#include <utils/RefBase.h>\n#include <utils/threads.h>\n#include <utils/KeyedVector.h>\n\nstruct ANativeWindow_Buffer;\n\nnamespace android {\n\n/*\n * An implementation of ANativeWindow that feeds graphics buffers into a\n * BufferQueue.\n *\n * This is typically used by programs that want to render frames through\n * some means (maybe OpenGL, a software renderer, or a hardware decoder)\n * and have the frames they create forwarded to SurfaceFlinger for\n * compositing.  For example, a video decoder could render a frame and call\n * eglSwapBuffers(), which invokes ANativeWindow callbacks defined by\n * Surface.  Surface then forwards the buffers through Binder IPC\n * to the BufferQueue's producer interface, providing the new frame to a\n * consumer such as GLConsumer.\n */\nclass Surface\n    : public ANativeObjectBase<ANativeWindow, Surface, RefBase>\n{\npublic:\n\n    /*\n     * creates a Surface from the given IGraphicBufferProducer (which concrete\n     * implementation is a BufferQueue).\n     *\n     * Surface is mainly state-less while it's disconnected, it can be\n     * viewed as a glorified IGraphicBufferProducer holder. It's therefore\n     * safe to create other Surfaces from the same IGraphicBufferProducer.\n     *\n     * However, once a Surface is connected, it'll prevent other Surfaces\n     * referring to the same IGraphicBufferProducer to become connected and\n     * therefore prevent them to be used as actual producers of buffers.\n     *\n     * the controlledByApp flag indicates that this Surface (producer) is\n     * controlled by the application. This flag is used at connect time.\n     */\n    Surface(const sp<IGraphicBufferProducer>& bufferProducer, bool controlledByApp = false);\n\n    /* getIGraphicBufferProducer() returns the IGraphicBufferProducer this\n     * Surface was created with. Usually it's an error to use the\n     * IGraphicBufferProducer while the Surface is connected.\n     */\n    sp<IGraphicBufferProducer> getIGraphicBufferProducer() const;\n\n    /* convenience function to check that the given surface is non NULL as\n     * well as its IGraphicBufferProducer */\n    static bool isValid(const sp<Surface>& surface) {\n        return surface != NULL && surface->getIGraphicBufferProducer() != NULL;\n    }\n\n    /* Attaches a sideband buffer stream to the Surface's IGraphicBufferProducer.\n     *\n     * A sideband stream is a device-specific mechanism for passing buffers\n     * from the producer to the consumer without using dequeueBuffer/\n     * queueBuffer. If a sideband stream is present, the consumer can choose\n     * whether to acquire buffers from the sideband stream or from the queued\n     * buffers.\n     *\n     * Passing NULL or a different stream handle will detach the previous\n     * handle if any.\n     */\n    void setSidebandStream(const sp<NativeHandle>& stream);\n\n    /* Allocates buffers based on the current dimensions/format.\n     *\n     * This function will allocate up to the maximum number of buffers\n     * permitted by the current BufferQueue configuration. It will use the\n     * default format and dimensions. This is most useful to avoid an allocation\n     * delay during dequeueBuffer. If there are already the maximum number of\n     * buffers allocated, this function has no effect.\n     */\n    void allocateBuffers();\n\n    /* Sets the generation number on the IGraphicBufferProducer and updates the\n     * generation number on any buffers attached to the Surface after this call.\n     * See IGBP::setGenerationNumber for more information. */\n    status_t setGenerationNumber(uint32_t generationNumber);\n\n    // See IGraphicBufferProducer::getConsumerName\n    String8 getConsumerName() const;\n\nprotected:\n    virtual ~Surface();\n\nprivate:\n    // can't be copied\n    Surface& operator = (const Surface& rhs);\n    Surface(const Surface& rhs);\n\n    // ANativeWindow hooks\n    static int hook_cancelBuffer(ANativeWindow* window,\n            ANativeWindowBuffer* buffer, int fenceFd);\n    static int hook_dequeueBuffer(ANativeWindow* window,\n            ANativeWindowBuffer** buffer, int* fenceFd);\n    static int hook_perform(ANativeWindow* window, int operation, ...);\n    static int hook_query(const ANativeWindow* window, int what, int* value);\n    static int hook_queueBuffer(ANativeWindow* window,\n            ANativeWindowBuffer* buffer, int fenceFd);\n    static int hook_setSwapInterval(ANativeWindow* window, int interval);\n\n    static int hook_cancelBuffer_DEPRECATED(ANativeWindow* window,\n            ANativeWindowBuffer* buffer);\n    static int hook_dequeueBuffer_DEPRECATED(ANativeWindow* window,\n            ANativeWindowBuffer** buffer);\n    static int hook_lockBuffer_DEPRECATED(ANativeWindow* window,\n            ANativeWindowBuffer* buffer);\n    static int hook_queueBuffer_DEPRECATED(ANativeWindow* window,\n            ANativeWindowBuffer* buffer);\n\n    int dispatchConnect(va_list args);\n    int dispatchDisconnect(va_list args);\n    int dispatchSetBufferCount(va_list args);\n    int dispatchSetBuffersGeometry(va_list args);\n    int dispatchSetBuffersDimensions(va_list args);\n    int dispatchSetBuffersUserDimensions(va_list args);\n    int dispatchSetBuffersFormat(va_list args);\n    int dispatchSetScalingMode(va_list args);\n    int dispatchSetBuffersTransform(va_list args);\n    int dispatchSetBuffersStickyTransform(va_list args);\n    int dispatchSetBuffersTimestamp(va_list args);\n    int dispatchSetCrop(va_list args);\n    int dispatchSetPostTransformCrop(va_list args);\n    int dispatchSetUsage(va_list args);\n    int dispatchLock(va_list args);\n    int dispatchUnlockAndPost(va_list args);\n    int dispatchSetSidebandStream(va_list args);\n    int dispatchSetBuffersDataSpace(va_list args);\n    int dispatchSetSurfaceDamage(va_list args);\n\nprotected:\n    virtual int dequeueBuffer(ANativeWindowBuffer** buffer, int* fenceFd);\n    virtual int cancelBuffer(ANativeWindowBuffer* buffer, int fenceFd);\n    virtual int queueBuffer(ANativeWindowBuffer* buffer, int fenceFd);\n    virtual int perform(int operation, va_list args);\n    virtual int query(int what, int* value) const;\n    virtual int setSwapInterval(int interval);\n\n    virtual int lockBuffer_DEPRECATED(ANativeWindowBuffer* buffer);\n\n    virtual int connect(int api);\n    virtual int disconnect(int api);\n    virtual int setBufferCount(int bufferCount);\n    virtual int setBuffersDimensions(uint32_t width, uint32_t height);\n    virtual int setBuffersUserDimensions(uint32_t width, uint32_t height);\n    virtual int setBuffersFormat(PixelFormat format);\n    virtual int setScalingMode(int mode);\n    virtual int setBuffersTransform(uint32_t transform);\n    virtual int setBuffersStickyTransform(uint32_t transform);\n    virtual int setBuffersTimestamp(int64_t timestamp);\n    virtual int setBuffersDataSpace(android_dataspace dataSpace);\n    virtual int setCrop(Rect const* rect);\n    virtual int setUsage(uint32_t reqUsage);\n    virtual void setSurfaceDamage(android_native_rect_t* rects, size_t numRects);\n\npublic:\n    virtual int lock(ANativeWindow_Buffer* outBuffer, ARect* inOutDirtyBounds);\n    virtual int unlockAndPost();\n\n    virtual int connect(int api, const sp<IProducerListener>& listener);\n    virtual int detachNextBuffer(sp<GraphicBuffer>* outBuffer,\n            sp<Fence>* outFence);\n    virtual int attachBuffer(ANativeWindowBuffer*);\n\nprotected:\n    enum { NUM_BUFFER_SLOTS = BufferQueue::NUM_BUFFER_SLOTS };\n    enum { DEFAULT_FORMAT = PIXEL_FORMAT_RGBA_8888 };\n\nprivate:\n    void freeAllBuffers();\n    int getSlotFromBufferLocked(android_native_buffer_t* buffer) const;\n\n    struct BufferSlot {\n        sp<GraphicBuffer> buffer;\n        Region dirtyRegion;\n    };\n\n    // mSurfaceTexture is the interface to the surface texture server. All\n    // operations on the surface texture client ultimately translate into\n    // interactions with the server using this interface.\n    // TODO: rename to mBufferProducer\n    sp<IGraphicBufferProducer> mGraphicBufferProducer;\n\n    // mSlots stores the buffers that have been allocated for each buffer slot.\n    // It is initialized to null pointers, and gets filled in with the result of\n    // IGraphicBufferProducer::requestBuffer when the client dequeues a buffer from a\n    // slot that has not yet been used. The buffer allocated to a slot will also\n    // be replaced if the requested buffer usage or geometry differs from that\n    // of the buffer allocated to a slot.\n    BufferSlot mSlots[NUM_BUFFER_SLOTS];\n\n    // mReqWidth is the buffer width that will be requested at the next dequeue\n    // operation. It is initialized to 1.\n    uint32_t mReqWidth;\n\n    // mReqHeight is the buffer height that will be requested at the next\n    // dequeue operation. It is initialized to 1.\n    uint32_t mReqHeight;\n\n    // mReqFormat is the buffer pixel format that will be requested at the next\n    // deuque operation. It is initialized to PIXEL_FORMAT_RGBA_8888.\n    PixelFormat mReqFormat;\n\n    // mReqUsage is the set of buffer usage flags that will be requested\n    // at the next deuque operation. It is initialized to 0.\n    uint32_t mReqUsage;\n\n    // mTimestamp is the timestamp that will be used for the next buffer queue\n    // operation. It defaults to NATIVE_WINDOW_TIMESTAMP_AUTO, which means that\n    // a timestamp is auto-generated when queueBuffer is called.\n    int64_t mTimestamp;\n\n    // mDataSpace is the buffer dataSpace that will be used for the next buffer\n    // queue operation. It defaults to HAL_DATASPACE_UNKNOWN, which\n    // means that the buffer contains some type of color data.\n    android_dataspace mDataSpace;\n\n    // mCrop is the crop rectangle that will be used for the next buffer\n    // that gets queued. It is set by calling setCrop.\n    Rect mCrop;\n\n    // mScalingMode is the scaling mode that will be used for the next\n    // buffers that get queued. It is set by calling setScalingMode.\n    int mScalingMode;\n\n    // mTransform is the transform identifier that will be used for the next\n    // buffer that gets queued. It is set by calling setTransform.\n    uint32_t mTransform;\n\n    // mStickyTransform is a transform that is applied on top of mTransform\n    // in each buffer that is queued.  This is typically used to force the\n    // compositor to apply a transform, and will prevent the transform hint\n    // from being set by the compositor.\n    uint32_t mStickyTransform;\n\n    // mDefaultWidth is default width of the buffers, regardless of the\n    // native_window_set_buffers_dimensions call.\n    uint32_t mDefaultWidth;\n\n    // mDefaultHeight is default height of the buffers, regardless of the\n    // native_window_set_buffers_dimensions call.\n    uint32_t mDefaultHeight;\n\n    // mUserWidth, if non-zero, is an application-specified override\n    // of mDefaultWidth.  This is lower priority than the width set by\n    // native_window_set_buffers_dimensions.\n    uint32_t mUserWidth;\n\n    // mUserHeight, if non-zero, is an application-specified override\n    // of mDefaultHeight.  This is lower priority than the height set\n    // by native_window_set_buffers_dimensions.\n    uint32_t mUserHeight;\n\n    // mTransformHint is the transform probably applied to buffers of this\n    // window. this is only a hint, actual transform may differ.\n    uint32_t mTransformHint;\n\n    // mProducerControlledByApp whether this buffer producer is controlled\n    // by the application\n    bool mProducerControlledByApp;\n\n    // mSwapIntervalZero set if we should drop buffers at queue() time to\n    // achieve an asynchronous swap interval\n    bool mSwapIntervalZero;\n\n    // mConsumerRunningBehind whether the consumer is running more than\n    // one buffer behind the producer.\n    mutable bool mConsumerRunningBehind;\n\n    // mMutex is the mutex used to prevent concurrent access to the member\n    // variables of Surface objects. It must be locked whenever the\n    // member variables are accessed.\n    mutable Mutex mMutex;\n\n    // must be used from the lock/unlock thread\n    sp<GraphicBuffer>           mLockedBuffer;\n    sp<GraphicBuffer>           mPostedBuffer;\n    bool                        mConnectedToCpu;\n\n    // When a CPU producer is attached, this reflects the region that the\n    // producer wished to update as well as whether the Surface was able to copy\n    // the previous buffer back to allow a partial update.\n    //\n    // When a non-CPU producer is attached, this reflects the surface damage\n    // (the change since the previous frame) passed in by the producer.\n    Region mDirtyRegion;\n\n    // Stores the current generation number. See setGenerationNumber and\n    // IGraphicBufferProducer::setGenerationNumber for more information.\n    uint32_t mGenerationNumber;\n};\n\n}; // namespace android\n\n#endif  // ANDROID_GUI_SURFACE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/SurfaceComposerClient.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_SURFACE_COMPOSER_CLIENT_H\n#define ANDROID_GUI_SURFACE_COMPOSER_CLIENT_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <binder/IBinder.h>\n#include <binder/IMemory.h>\n\n#include <utils/RefBase.h>\n#include <utils/Singleton.h>\n#include <utils/SortedVector.h>\n#include <utils/threads.h>\n\n#include <ui/FrameStats.h>\n#include <ui/PixelFormat.h>\n\n#include <gui/CpuConsumer.h>\n#include <gui/SurfaceControl.h>\n\nnamespace android {\n\n// ---------------------------------------------------------------------------\n\nclass DisplayInfo;\nclass Composer;\nclass ISurfaceComposerClient;\nclass IGraphicBufferProducer;\nclass Region;\n\n// ---------------------------------------------------------------------------\n\nclass SurfaceComposerClient : public RefBase\n{\n    friend class Composer;\npublic:\n                SurfaceComposerClient();\n    virtual     ~SurfaceComposerClient();\n\n    // Always make sure we could initialize\n    status_t    initCheck() const;\n\n    // Return the connection of this client\n    sp<IBinder> connection() const;\n\n    // Forcibly remove connection before all references have gone away.\n    void        dispose();\n\n    // callback when the composer is dies\n    status_t linkToComposerDeath(const sp<IBinder::DeathRecipient>& recipient,\n            void* cookie = NULL, uint32_t flags = 0);\n\n    // Get a list of supported configurations for a given display\n    static status_t getDisplayConfigs(const sp<IBinder>& display,\n            Vector<DisplayInfo>* configs);\n\n    // Get the DisplayInfo for the currently-active configuration\n    static status_t getDisplayInfo(const sp<IBinder>& display,\n            DisplayInfo* info);\n\n    // Get the index of the current active configuration (relative to the list\n    // returned by getDisplayInfo)\n    static int getActiveConfig(const sp<IBinder>& display);\n\n    // Set a new active configuration using an index relative to the list\n    // returned by getDisplayInfo\n    static status_t setActiveConfig(const sp<IBinder>& display, int id);\n\n    /* Triggers screen on/off or low power mode and waits for it to complete */\n    static void setDisplayPowerMode(const sp<IBinder>& display, int mode);\n\n    // ------------------------------------------------------------------------\n    // surface creation / destruction\n\n    //! Create a surface\n    sp<SurfaceControl> createSurface(\n            const String8& name,// name of the surface\n            uint32_t w,         // width in pixel\n            uint32_t h,         // height in pixel\n            PixelFormat format, // pixel-format desired\n            uint32_t flags = 0  // usage flags\n    );\n\n    //! Create a virtual display\n    static sp<IBinder> createDisplay(const String8& displayName, bool secure);\n\n    //! Destroy a virtual display\n    static void destroyDisplay(const sp<IBinder>& display);\n\n    //! Get the token for the existing default displays.\n    //! Possible values for id are eDisplayIdMain and eDisplayIdHdmi.\n    static sp<IBinder> getBuiltInDisplay(int32_t id);\n\n    // ------------------------------------------------------------------------\n    // Composer parameters\n    // All composer parameters must be changed within a transaction\n    // several surfaces can be updated in one transaction, all changes are\n    // committed at once when the transaction is closed.\n    // closeGlobalTransaction() requires an IPC with the server.\n\n    //! Open a composer transaction on all active SurfaceComposerClients.\n    static void openGlobalTransaction();\n\n    //! Close a composer transaction on all active SurfaceComposerClients.\n    static void closeGlobalTransaction(bool synchronous = false);\n\n    //! Flag the currently open transaction as an animation transaction.\n    static void setAnimationTransaction();\n\n    status_t    hide(const sp<IBinder>& id);\n    status_t    show(const sp<IBinder>& id);\n    status_t    setFlags(const sp<IBinder>& id, uint32_t flags, uint32_t mask);\n    status_t    setTransparentRegionHint(const sp<IBinder>& id, const Region& transparent);\n    status_t    setLayer(const sp<IBinder>& id, uint32_t layer);\n    status_t    setAlpha(const sp<IBinder>& id, float alpha=1.0f);\n    status_t    setMatrix(const sp<IBinder>& id, float dsdx, float dtdx, float dsdy, float dtdy);\n    status_t    setPosition(const sp<IBinder>& id, float x, float y);\n    status_t    setSize(const sp<IBinder>& id, uint32_t w, uint32_t h);\n    status_t    setCrop(const sp<IBinder>& id, const Rect& crop);\n    status_t    setLayerStack(const sp<IBinder>& id, uint32_t layerStack);\n    status_t    destroySurface(const sp<IBinder>& id);\n\n    status_t clearLayerFrameStats(const sp<IBinder>& token) const;\n    status_t getLayerFrameStats(const sp<IBinder>& token, FrameStats* outStats) const;\n\n    static status_t clearAnimationFrameStats();\n    static status_t getAnimationFrameStats(FrameStats* outStats);\n\n    static void setDisplaySurface(const sp<IBinder>& token,\n            const sp<IGraphicBufferProducer>& bufferProducer);\n    static void setDisplayLayerStack(const sp<IBinder>& token,\n            uint32_t layerStack);\n    static void setDisplaySize(const sp<IBinder>& token, uint32_t width, uint32_t height);\n\n    /* setDisplayProjection() defines the projection of layer stacks\n     * to a given display.\n     *\n     * - orientation defines the display's orientation.\n     * - layerStackRect defines which area of the window manager coordinate\n     * space will be used.\n     * - displayRect defines where on the display will layerStackRect be\n     * mapped to. displayRect is specified post-orientation, that is\n     * it uses the orientation seen by the end-user.\n     */\n    static void setDisplayProjection(const sp<IBinder>& token,\n            uint32_t orientation,\n            const Rect& layerStackRect,\n            const Rect& displayRect);\n\n    status_t    setBlur(const sp<IBinder>& id, float blur);\n    status_t    setBlurMaskSurface(const sp<IBinder>& id, const sp<IBinder>& maskSurfaceId);\n    status_t    setBlurMaskSampling(const sp<IBinder>& id, uint32_t blurMaskSampling);\n    status_t    setBlurMaskAlphaThreshold(const sp<IBinder>& id, float alpha);\n\nprivate:\n    virtual void onFirstRef();\n    Composer& getComposer();\n\n    mutable     Mutex                       mLock;\n                status_t                    mStatus;\n                sp<ISurfaceComposerClient>  mClient;\n                Composer&                   mComposer;\n};\n\n// ---------------------------------------------------------------------------\n\nclass ScreenshotClient\n{\npublic:\n    // if cropping isn't required, callers may pass in a default Rect, e.g.:\n    //   capture(display, producer, Rect(), reqWidth, ...);\n    static status_t capture(\n            const sp<IBinder>& display,\n            const sp<IGraphicBufferProducer>& producer,\n            Rect sourceCrop, uint32_t reqWidth, uint32_t reqHeight,\n            uint32_t minLayerZ, uint32_t maxLayerZ,\n            bool useIdentityTransform);\n\nprivate:\n    mutable sp<CpuConsumer> mCpuConsumer;\n    mutable sp<IGraphicBufferProducer> mProducer;\n    CpuConsumer::LockedBuffer mBuffer;\n    bool mHaveBuffer;\n\npublic:\n    ScreenshotClient();\n    ~ScreenshotClient();\n\n    // frees the previous screenshot and captures a new one\n    // if cropping isn't required, callers may pass in a default Rect, e.g.:\n    //   update(display, Rect(), useIdentityTransform);\n    status_t update(const sp<IBinder>& display,\n            Rect sourceCrop, bool useIdentityTransform);\n    status_t update(const sp<IBinder>& display,\n            Rect sourceCrop, uint32_t reqWidth, uint32_t reqHeight,\n            bool useIdentityTransform);\n    status_t update(const sp<IBinder>& display,\n            Rect sourceCrop, uint32_t reqWidth, uint32_t reqHeight,\n            uint32_t minLayerZ, uint32_t maxLayerZ,\n            bool useIdentityTransform);\n    status_t update(const sp<IBinder>& display,\n            Rect sourceCrop, uint32_t reqWidth, uint32_t reqHeight,\n            uint32_t minLayerZ, uint32_t maxLayerZ,\n            bool useIdentityTransform, uint32_t rotation);\n\n    sp<CpuConsumer> getCpuConsumer() const;\n\n    // release memory occupied by the screenshot\n    void release();\n\n    // pixels are valid until this object is freed or\n    // release() or update() is called\n    void const* getPixels() const;\n\n    uint32_t getWidth() const;\n    uint32_t getHeight() const;\n    PixelFormat getFormat() const;\n    uint32_t getStride() const;\n    // size of allocated memory in bytes\n    size_t getSize() const;\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_GUI_SURFACE_COMPOSER_CLIENT_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/gui/SurfaceControl.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GUI_SURFACE_CONTROL_H\n#define ANDROID_GUI_SURFACE_CONTROL_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/KeyedVector.h>\n#include <utils/RefBase.h>\n#include <utils/threads.h>\n\n#include <ui/FrameStats.h>\n#include <ui/PixelFormat.h>\n#include <ui/Region.h>\n\n#include <gui/ISurfaceComposerClient.h>\n\nnamespace android {\n\n// ---------------------------------------------------------------------------\n\nclass IGraphicBufferProducer;\nclass Surface;\nclass SurfaceComposerClient;\n\n// ---------------------------------------------------------------------------\n\nclass SurfaceControl : public RefBase\n{\npublic:\n    static bool isValid(const sp<SurfaceControl>& surface) {\n        return (surface != 0) && surface->isValid();\n    }\n\n    bool isValid() {\n        return mHandle!=0 && mClient!=0;\n    }\n\n    static bool isSameSurface(\n            const sp<SurfaceControl>& lhs, const sp<SurfaceControl>& rhs);\n\n    // release surface data from java\n    void        clear();\n\n    status_t    setLayerStack(uint32_t layerStack);\n    status_t    setLayer(uint32_t layer);\n    status_t    setPosition(float x, float y);\n    status_t    setSize(uint32_t w, uint32_t h);\n    status_t    hide();\n    status_t    show();\n    status_t    setFlags(uint32_t flags, uint32_t mask);\n    status_t    setTransparentRegionHint(const Region& transparent);\n    status_t    setAlpha(float alpha=1.0f);\n    status_t    setMatrix(float dsdx, float dtdx, float dsdy, float dtdy);\n    status_t    setCrop(const Rect& crop);\n\n    static status_t writeSurfaceToParcel(\n            const sp<SurfaceControl>& control, Parcel* parcel);\n\n    sp<Surface> getSurface() const;\n\n    status_t clearLayerFrameStats() const;\n    status_t getLayerFrameStats(FrameStats* outStats) const;\n\n    status_t    setBlur(float blur = 0);\n    status_t    setBlurMaskSurface(const sp<SurfaceControl>& maskSurface);\n    status_t    setBlurMaskSampling(uint32_t blurMaskSampling);\n    status_t    setBlurMaskAlphaThreshold(float alpha);\n\nprivate:\n    // can't be copied\n    SurfaceControl& operator = (SurfaceControl& rhs);\n    SurfaceControl(const SurfaceControl& rhs);\n\n    friend class SurfaceComposerClient;\n    friend class Surface;\n\n    SurfaceControl(\n            const sp<SurfaceComposerClient>& client,\n            const sp<IBinder>& handle,\n            const sp<IGraphicBufferProducer>& gbp);\n\n    ~SurfaceControl();\n\n    status_t validate() const;\n    void destroy();\n\n    sp<SurfaceComposerClient>   mClient;\n    sp<IBinder>                 mHandle;\n    sp<IGraphicBufferProducer>  mGraphicBufferProducer;\n    mutable Mutex               mLock;\n    mutable sp<Surface>         mSurfaceData;\n};\n\n}; // namespace android\n\n#endif // ANDROID_GUI_SURFACE_CONTROL_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/ANativeObjectBase.h",
    "content": "/*\n * Copyright (C) 2009 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_ANDROID_NATIVES_H\n#define ANDROID_ANDROID_NATIVES_H\n\n#include <sys/types.h>\n#include <string.h>\n\n#include <hardware/gralloc.h>\n#include <system/window.h>\n\n// ---------------------------------------------------------------------------\n\n/* FIXME: this is legacy for pixmaps */\ntypedef struct egl_native_pixmap_t\n{\n    int32_t     version;    /* must be 32 */\n    int32_t     width;\n    int32_t     height;\n    int32_t     stride;\n    uint8_t*    data;\n    uint8_t     format;\n    uint8_t     rfu[3];\n    union {\n        uint32_t    compressedFormat;\n        int32_t     vstride;\n    };\n    int32_t     reserved;\n} egl_native_pixmap_t;\n\n/*****************************************************************************/\n\n#ifdef __cplusplus\n\n#include <utils/RefBase.h>\n\nnamespace android {\n\n/*\n * This helper class turns a ANativeXXX object type into a C++\n * reference-counted object; with proper type conversions.\n */\ntemplate <typename NATIVE_TYPE, typename TYPE, typename REF>\nclass ANativeObjectBase : public NATIVE_TYPE, public REF\n{\npublic:\n    // Disambiguate between the incStrong in REF and NATIVE_TYPE\n    void incStrong(const void* id) const {\n        REF::incStrong(id);\n    }\n    void decStrong(const void* id) const {\n        REF::decStrong(id);\n    }\n\nprotected:\n    typedef ANativeObjectBase<NATIVE_TYPE, TYPE, REF> BASE;\n    ANativeObjectBase() : NATIVE_TYPE(), REF() {\n        NATIVE_TYPE::common.incRef = incRef;\n        NATIVE_TYPE::common.decRef = decRef;\n    }\n    static inline TYPE* getSelf(NATIVE_TYPE* self) {\n        return static_cast<TYPE*>(self);\n    }\n    static inline TYPE const* getSelf(NATIVE_TYPE const* self) {\n        return static_cast<TYPE const *>(self);\n    }\n    static inline TYPE* getSelf(android_native_base_t* base) {\n        return getSelf(reinterpret_cast<NATIVE_TYPE*>(base));\n    }\n    static inline TYPE const * getSelf(android_native_base_t const* base) {\n        return getSelf(reinterpret_cast<NATIVE_TYPE const*>(base));\n    }\n    static void incRef(android_native_base_t* base) {\n        ANativeObjectBase* self = getSelf(base);\n        self->incStrong(self);\n    }\n    static void decRef(android_native_base_t* base) {\n        ANativeObjectBase* self = getSelf(base);\n        self->decStrong(self);\n    }\n};\n\n} // namespace android\n#endif // __cplusplus\n\n/*****************************************************************************/\n\n#endif /* ANDROID_ANDROID_NATIVES_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/DisplayInfo.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_DISPLAY_INFO_H\n#define ANDROID_UI_DISPLAY_INFO_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <utils/Timers.h>\n\n#include <ui/PixelFormat.h>\n\nnamespace android {\n\nstruct DisplayInfo {\n    uint32_t w;\n    uint32_t h;\n    float xdpi;\n    float ydpi;\n    float fps;\n    float density;\n    uint8_t orientation;\n    bool secure;\n    nsecs_t appVsyncOffset;\n    nsecs_t presentationDeadline;\n    int colorTransform;\n};\n\n/* Display orientations as defined in Surface.java and ISurfaceComposer.h. */\nenum {\n    DISPLAY_ORIENTATION_0 = 0,\n    DISPLAY_ORIENTATION_90 = 1,\n    DISPLAY_ORIENTATION_180 = 2,\n    DISPLAY_ORIENTATION_270 = 3\n};\n\n}; // namespace android\n\n#endif // ANDROID_COMPOSER_DISPLAY_INFO_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/DisplayStatInfo.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_DISPLAY_STAT_INFO_H\n#define ANDROID_UI_DISPLAY_STAT_INFO_H\n\n#include <utils/Timers.h>\n\nnamespace android {\n\nstruct DisplayStatInfo {\n    nsecs_t vsyncTime;\n    nsecs_t vsyncPeriod;\n};\n\n}; // namespace android\n\n#endif // ANDROID_COMPOSER_DISPLAY_STAT_INFO_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/Fence.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_FENCE_H\n#define ANDROID_FENCE_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <ui/ANativeObjectBase.h>\n#include <ui/PixelFormat.h>\n#include <ui/Rect.h>\n#include <utils/Flattenable.h>\n#include <utils/String8.h>\n#include <utils/Timers.h>\n\nstruct ANativeWindowBuffer;\n\nnamespace android {\n\n// ===========================================================================\n// Fence\n// ===========================================================================\n\nclass Fence\n    : public LightRefBase<Fence>, public Flattenable<Fence>\n{\npublic:\n    static const sp<Fence> NO_FENCE;\n\n    // TIMEOUT_NEVER may be passed to the wait method to indicate that it\n    // should wait indefinitely for the fence to signal.\n    enum { TIMEOUT_NEVER = -1 };\n\n    // Construct a new Fence object with an invalid file descriptor.  This\n    // should be done when the Fence object will be set up by unflattening\n    // serialized data.\n    Fence();\n\n    // Construct a new Fence object to manage a given fence file descriptor.\n    // When the new Fence object is destructed the file descriptor will be\n    // closed.\n    Fence(int fenceFd);\n\n    // Check whether the Fence has an open fence file descriptor. Most Fence\n    // methods treat an invalid file descriptor just like a valid fence that\n    // is already signalled, so using this is usually not necessary.\n    bool isValid() const { return mFenceFd != -1; }\n\n    // wait waits for up to timeout milliseconds for the fence to signal.  If\n    // the fence signals then NO_ERROR is returned. If the timeout expires\n    // before the fence signals then -ETIME is returned.  A timeout of\n    // TIMEOUT_NEVER may be used to indicate that the call should wait\n    // indefinitely for the fence to signal.\n    status_t wait(int timeout);\n\n    // waitForever is a convenience function for waiting forever for a fence to\n    // signal (just like wait(TIMEOUT_NEVER)), but issuing an error to the\n    // system log and fence state to the kernel log if the wait lasts longer\n    // than a warning timeout.\n    // The logname argument should be a string identifying\n    // the caller and will be included in the log message.\n    status_t waitForever(const char* logname);\n\n    // merge combines two Fence objects, creating a new Fence object that\n    // becomes signaled when both f1 and f2 are signaled (even if f1 or f2 is\n    // destroyed before it becomes signaled).  The name argument specifies the\n    // human-readable name to associated with the new Fence object.\n    static sp<Fence> merge(const String8& name, const sp<Fence>& f1,\n            const sp<Fence>& f2);\n\n    // Return a duplicate of the fence file descriptor. The caller is\n    // responsible for closing the returned file descriptor. On error, -1 will\n    // be returned and errno will indicate the problem.\n    int dup() const;\n\n    // getSignalTime returns the system monotonic clock time at which the\n    // fence transitioned to the signaled state.  If the fence is not signaled\n    // then INT64_MAX is returned.  If the fence is invalid or if an error\n    // occurs then -1 is returned.\n    nsecs_t getSignalTime() const;\n\n    // Flattenable interface\n    size_t getFlattenedSize() const;\n    size_t getFdCount() const;\n    status_t flatten(void*& buffer, size_t& size, int*& fds, size_t& count) const;\n    status_t unflatten(void const*& buffer, size_t& size, int const*& fds, size_t& count);\n\nprivate:\n    // Only allow instantiation using ref counting.\n    friend class LightRefBase<Fence>;\n    ~Fence();\n\n    // Disallow copying\n    Fence(const Fence& rhs);\n    Fence& operator = (const Fence& rhs);\n    const Fence& operator = (const Fence& rhs) const;\n\n    int mFenceFd;\n};\n\n}; // namespace android\n\n#endif // ANDROID_FENCE_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/FrameStats.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_FRAME_STATS_H\n#define ANDROID_UI_FRAME_STATS_H\n\n#include <utils/Flattenable.h>\n#include <utils/Timers.h>\n#include <utils/Vector.h>\n\nnamespace android {\n\nclass FrameStats : public LightFlattenable<FrameStats> {\npublic:\n    FrameStats() : refreshPeriodNano(0) {};\n\n    /*\n     * Approximate refresh time, in nanoseconds.\n     */\n    nsecs_t refreshPeriodNano;\n\n   /*\n    * The times in nanoseconds for when the frame contents were posted by the producer (e.g.\n    * the application). They are either explicitly set or defaulted to the time when\n    * Surface::queueBuffer() was called.\n    */\n    Vector<nsecs_t> desiredPresentTimesNano;\n\n   /*\n    * The times in milliseconds for when the frame contents were presented on the screen.\n    */\n    Vector<nsecs_t> actualPresentTimesNano;\n\n   /*\n    * The times in nanoseconds for when the frame contents were ready to be presented. Note that\n    * a frame can be posted and still it contents being rendered asynchronously in GL. In such a\n    * case these are the times when the frame contents were completely rendered (i.e. their fences\n    * signaled).\n    */\n    Vector<nsecs_t> frameReadyTimesNano;\n\n    // LightFlattenable\n    bool isFixedSize() const;\n    size_t getFlattenedSize() const;\n    status_t flatten(void* buffer, size_t size) const;\n    status_t unflatten(void const* buffer, size_t size);\n};\n\n}; // namespace android\n\n#endif // ANDROID_UI_FRAME_STATS_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/FramebufferNativeWindow.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef INCLUDED_FROM_FRAMEBUFFER_NATIVE_WINDOW_CPP\n#warning \"FramebufferNativeWindow is deprecated\"\n#endif\n\n#ifndef ANDROID_FRAMEBUFFER_NATIVE_WINDOW_H\n#define ANDROID_FRAMEBUFFER_NATIVE_WINDOW_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <EGL/egl.h>\n\n#include <utils/threads.h>\n#include <utils/String8.h>\n\n#include <ui/ANativeObjectBase.h>\n#include <ui/Rect.h>\n\n#define MIN_NUM_FRAME_BUFFERS  2\n#define MAX_NUM_FRAME_BUFFERS  3\n\nextern \"C\" EGLNativeWindowType android_createDisplaySurface(void);\n\n// ---------------------------------------------------------------------------\nnamespace android {\n// ---------------------------------------------------------------------------\n\nclass Surface;\nclass NativeBuffer;\n\n// ---------------------------------------------------------------------------\n\nclass FramebufferNativeWindow \n    : public ANativeObjectBase<\n        ANativeWindow, \n        FramebufferNativeWindow, \n        LightRefBase<FramebufferNativeWindow> >\n{\npublic:\n    FramebufferNativeWindow(); \n\n    framebuffer_device_t const * getDevice() const { return fbDev; } \n\n    bool isUpdateOnDemand() const { return mUpdateOnDemand; }\n    status_t setUpdateRectangle(const Rect& updateRect);\n    status_t compositionComplete();\n\n    void dump(String8& result);\n\n    // for debugging only\n    int getCurrentBufferIndex() const;\n\nprivate:\n    friend class LightRefBase<FramebufferNativeWindow>;    \n    ~FramebufferNativeWindow(); // this class cannot be overloaded\n    static int setSwapInterval(ANativeWindow* window, int interval);\n    static int dequeueBuffer(ANativeWindow* window, ANativeWindowBuffer** buffer, int* fenceFd);\n    static int queueBuffer(ANativeWindow* window, ANativeWindowBuffer* buffer, int fenceFd);\n    static int query(const ANativeWindow* window, int what, int* value);\n    static int perform(ANativeWindow* window, int operation, ...);\n\n    static int dequeueBuffer_DEPRECATED(ANativeWindow* window, ANativeWindowBuffer** buffer);\n    static int queueBuffer_DEPRECATED(ANativeWindow* window, ANativeWindowBuffer* buffer);\n    static int lockBuffer_DEPRECATED(ANativeWindow* window, ANativeWindowBuffer* buffer);\n\n    framebuffer_device_t* fbDev;\n    alloc_device_t* grDev;\n\n    sp<NativeBuffer> buffers[MAX_NUM_FRAME_BUFFERS];\n    sp<NativeBuffer> front;\n    \n    mutable Mutex mutex;\n    Condition mCondition;\n    int32_t mNumBuffers;\n    int32_t mNumFreeBuffers;\n    int32_t mBufferHead;\n    int32_t mCurrentBufferIndex;\n    bool mUpdateOnDemand;\n};\n    \n// ---------------------------------------------------------------------------\n}; // namespace android\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_FRAMEBUFFER_NATIVE_WINDOW_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/GraphicBuffer.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_GRAPHIC_BUFFER_H\n#define ANDROID_GRAPHIC_BUFFER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <ui/ANativeObjectBase.h>\n#include <ui/PixelFormat.h>\n#include <ui/Rect.h>\n#include <utils/Flattenable.h>\n#include <utils/RefBase.h>\n\n\nstruct ANativeWindowBuffer;\n\nnamespace android {\n\nclass GraphicBufferMapper;\n\n// ===========================================================================\n// GraphicBuffer\n// ===========================================================================\n\nclass GraphicBuffer\n    : public ANativeObjectBase< ANativeWindowBuffer, GraphicBuffer, RefBase >,\n      public Flattenable<GraphicBuffer>\n{\n    friend class Flattenable<GraphicBuffer>;\npublic:\n\n    enum {\n        USAGE_SW_READ_NEVER     = GRALLOC_USAGE_SW_READ_NEVER,\n        USAGE_SW_READ_RARELY    = GRALLOC_USAGE_SW_READ_RARELY,\n        USAGE_SW_READ_OFTEN     = GRALLOC_USAGE_SW_READ_OFTEN,\n        USAGE_SW_READ_MASK      = GRALLOC_USAGE_SW_READ_MASK,\n\n        USAGE_SW_WRITE_NEVER    = GRALLOC_USAGE_SW_WRITE_NEVER,\n        USAGE_SW_WRITE_RARELY   = GRALLOC_USAGE_SW_WRITE_RARELY,\n        USAGE_SW_WRITE_OFTEN    = GRALLOC_USAGE_SW_WRITE_OFTEN,\n        USAGE_SW_WRITE_MASK     = GRALLOC_USAGE_SW_WRITE_MASK,\n\n        USAGE_SOFTWARE_MASK     = USAGE_SW_READ_MASK|USAGE_SW_WRITE_MASK,\n\n        USAGE_PROTECTED         = GRALLOC_USAGE_PROTECTED,\n\n        USAGE_HW_TEXTURE        = GRALLOC_USAGE_HW_TEXTURE,\n        USAGE_HW_RENDER         = GRALLOC_USAGE_HW_RENDER,\n        USAGE_HW_2D             = GRALLOC_USAGE_HW_2D,\n        USAGE_HW_COMPOSER       = GRALLOC_USAGE_HW_COMPOSER,\n        USAGE_HW_VIDEO_ENCODER  = GRALLOC_USAGE_HW_VIDEO_ENCODER,\n        USAGE_HW_MASK           = GRALLOC_USAGE_HW_MASK,\n\n        USAGE_CURSOR            = GRALLOC_USAGE_CURSOR,\n    };\n\n    GraphicBuffer();\n\n    // creates w * h buffer\n    GraphicBuffer(uint32_t inWidth, uint32_t inHeight, PixelFormat inFormat,\n            uint32_t inUsage);\n\n    // create a buffer from an existing handle\n    GraphicBuffer(uint32_t inWidth, uint32_t inHeight, PixelFormat inFormat,\n            uint32_t inUsage, uint32_t inStride, native_handle_t* inHandle,\n            bool keepOwnership);\n\n    // create a buffer from an existing ANativeWindowBuffer\n    GraphicBuffer(ANativeWindowBuffer* buffer, bool keepOwnership);\n\n    // return status\n    status_t initCheck() const;\n\n    uint32_t getWidth() const           { return static_cast<uint32_t>(width); }\n    uint32_t getHeight() const          { return static_cast<uint32_t>(height); }\n    uint32_t getStride() const          { return static_cast<uint32_t>(stride); }\n    uint32_t getUsage() const           { return static_cast<uint32_t>(usage); }\n    PixelFormat getPixelFormat() const  { return format; }\n    Rect getBounds() const              { return Rect(width, height); }\n    uint64_t getId() const              { return mId; }\n\n    uint32_t getGenerationNumber() const { return mGenerationNumber; }\n    void setGenerationNumber(uint32_t generation) {\n        mGenerationNumber = generation;\n    }\n\n    status_t reallocate(uint32_t inWidth, uint32_t inHeight,\n            PixelFormat inFormat, uint32_t inUsage);\n\n    bool needsReallocation(uint32_t inWidth, uint32_t inHeight,\n            PixelFormat inFormat, uint32_t inUsage);\n\n    status_t lock(uint32_t inUsage, void** vaddr);\n    status_t lock(uint32_t inUsage, const Rect& rect, void** vaddr);\n    // For HAL_PIXEL_FORMAT_YCbCr_420_888\n    status_t lockYCbCr(uint32_t inUsage, android_ycbcr *ycbcr);\n    status_t lockYCbCr(uint32_t inUsage, const Rect& rect,\n            android_ycbcr *ycbcr);\n    status_t unlock();\n    status_t lockAsync(uint32_t inUsage, void** vaddr, int fenceFd);\n    status_t lockAsync(uint32_t inUsage, const Rect& rect, void** vaddr,\n            int fenceFd);\n    status_t lockAsyncYCbCr(uint32_t inUsage, android_ycbcr *ycbcr,\n            int fenceFd);\n    status_t lockAsyncYCbCr(uint32_t inUsage, const Rect& rect,\n            android_ycbcr *ycbcr, int fenceFd);\n    status_t unlockAsync(int *fenceFd);\n\n    ANativeWindowBuffer* getNativeBuffer() const;\n\n    // for debugging\n    static void dumpAllocationsToSystemLog();\n\n    // Flattenable protocol\n    size_t getFlattenedSize() const;\n    size_t getFdCount() const;\n    status_t flatten(void*& buffer, size_t& size, int*& fds, size_t& count) const;\n    status_t unflatten(void const*& buffer, size_t& size, int const*& fds, size_t& count);\n\nprivate:\n    ~GraphicBuffer();\n\n    enum {\n        ownNone   = 0,\n        ownHandle = 1,\n        ownData   = 2,\n    };\n\n    inline const GraphicBufferMapper& getBufferMapper() const {\n        return mBufferMapper;\n    }\n    inline GraphicBufferMapper& getBufferMapper() {\n        return mBufferMapper;\n    }\n    uint8_t mOwner;\n\nprivate:\n    friend class Surface;\n    friend class BpSurface;\n    friend class BnSurface;\n    friend class LightRefBase<GraphicBuffer>;\n    GraphicBuffer(const GraphicBuffer& rhs);\n    GraphicBuffer& operator = (const GraphicBuffer& rhs);\n    const GraphicBuffer& operator = (const GraphicBuffer& rhs) const;\n\n    status_t initSize(uint32_t inWidth, uint32_t inHeight, PixelFormat inFormat,\n            uint32_t inUsage);\n\n    void free_handle();\n\n    GraphicBufferMapper& mBufferMapper;\n    ssize_t mInitCheck;\n\n    // If we're wrapping another buffer then this reference will make sure it\n    // doesn't get freed.\n    sp<ANativeWindowBuffer> mWrappedBuffer;\n\n    uint64_t mId;\n\n    // Stores the generation number of this buffer. If this number does not\n    // match the BufferQueue's internal generation number (set through\n    // IGBP::setGenerationNumber), attempts to attach the buffer will fail.\n    uint32_t mGenerationNumber;\n};\n\n}; // namespace android\n\n#endif // ANDROID_GRAPHIC_BUFFER_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/GraphicBufferAllocator.h",
    "content": "/*\n**\n** Copyright 2009, The Android Open Source Project\n**\n** Licensed under the Apache License, Version 2.0 (the \"License\");\n** you may not use this file except in compliance with the License.\n** You may obtain a copy of the License at\n**\n**     http://www.apache.org/licenses/LICENSE-2.0\n**\n** Unless required by applicable law or agreed to in writing, software\n** distributed under the License is distributed on an \"AS IS\" BASIS,\n** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n** See the License for the specific language governing permissions and\n** limitations under the License.\n*/\n\n#ifndef ANDROID_BUFFER_ALLOCATOR_H\n#define ANDROID_BUFFER_ALLOCATOR_H\n\n#include <stdint.h>\n\n#include <cutils/native_handle.h>\n\n#include <utils/Errors.h>\n#include <utils/KeyedVector.h>\n#include <utils/threads.h>\n#include <utils/Singleton.h>\n\n#include <ui/PixelFormat.h>\n\n#include <hardware/gralloc.h>\n\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\nclass String8;\n\nclass GraphicBufferAllocator : public Singleton<GraphicBufferAllocator>\n{\npublic:\n    enum {\n        USAGE_SW_READ_NEVER     = GRALLOC_USAGE_SW_READ_NEVER,\n        USAGE_SW_READ_RARELY    = GRALLOC_USAGE_SW_READ_RARELY,\n        USAGE_SW_READ_OFTEN     = GRALLOC_USAGE_SW_READ_OFTEN,\n        USAGE_SW_READ_MASK      = GRALLOC_USAGE_SW_READ_MASK,\n\n        USAGE_SW_WRITE_NEVER    = GRALLOC_USAGE_SW_WRITE_NEVER,\n        USAGE_SW_WRITE_RARELY   = GRALLOC_USAGE_SW_WRITE_RARELY,\n        USAGE_SW_WRITE_OFTEN    = GRALLOC_USAGE_SW_WRITE_OFTEN,\n        USAGE_SW_WRITE_MASK     = GRALLOC_USAGE_SW_WRITE_MASK,\n\n        USAGE_SOFTWARE_MASK     = USAGE_SW_READ_MASK|USAGE_SW_WRITE_MASK,\n\n        USAGE_HW_TEXTURE        = GRALLOC_USAGE_HW_TEXTURE,\n        USAGE_HW_RENDER         = GRALLOC_USAGE_HW_RENDER,\n        USAGE_HW_2D             = GRALLOC_USAGE_HW_2D,\n        USAGE_HW_MASK           = GRALLOC_USAGE_HW_MASK\n    };\n\n    static inline GraphicBufferAllocator& get() { return getInstance(); }\n\n    status_t alloc(uint32_t w, uint32_t h, PixelFormat format, uint32_t usage,\n            buffer_handle_t* handle, uint32_t* stride);\n\n    status_t free(buffer_handle_t handle);\n\n    void dump(String8& res) const;\n    static void dumpToSystemLog();\n\nprivate:\n    struct alloc_rec_t {\n        uint32_t width;\n        uint32_t height;\n        uint32_t stride;\n        PixelFormat format;\n        uint32_t usage;\n        size_t size;\n    };\n\n    static Mutex sLock;\n    static KeyedVector<buffer_handle_t, alloc_rec_t> sAllocList;\n\n    friend class Singleton<GraphicBufferAllocator>;\n    GraphicBufferAllocator();\n    ~GraphicBufferAllocator();\n\n    alloc_device_t  *mAllocDev;\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_BUFFER_ALLOCATOR_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/GraphicBufferMapper.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_BUFFER_MAPPER_H\n#define ANDROID_UI_BUFFER_MAPPER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Singleton.h>\n\n#include <hardware/gralloc.h>\n\n\nstruct gralloc_module_t;\n\nnamespace android {\n\n// ---------------------------------------------------------------------------\n\nclass Rect;\n\nclass GraphicBufferMapper : public Singleton<GraphicBufferMapper>\n{\npublic:\n    static inline GraphicBufferMapper& get() { return getInstance(); }\n\n    status_t registerBuffer(buffer_handle_t handle);\n\n    status_t unregisterBuffer(buffer_handle_t handle);\n\n    status_t lock(buffer_handle_t handle,\n            uint32_t usage, const Rect& bounds, void** vaddr);\n\n    status_t lockYCbCr(buffer_handle_t handle,\n            uint32_t usage, const Rect& bounds, android_ycbcr *ycbcr);\n\n    status_t unlock(buffer_handle_t handle);\n\n    status_t lockAsync(buffer_handle_t handle,\n            uint32_t usage, const Rect& bounds, void** vaddr, int fenceFd);\n\n    status_t lockAsyncYCbCr(buffer_handle_t handle,\n            uint32_t usage, const Rect& bounds, android_ycbcr *ycbcr,\n            int fenceFd);\n\n    status_t unlockAsync(buffer_handle_t handle, int *fenceFd);\n\n#ifdef EXYNOS4_ENHANCEMENTS\n    status_t getphys(buffer_handle_t handle, void** paddr);\n#endif\n\n    // dumps information about the mapping of this handle\n    void dump(buffer_handle_t handle);\n\nprivate:\n    friend class Singleton<GraphicBufferMapper>;\n    GraphicBufferMapper();\n    gralloc_module_t const *mAllocMod;\n};\n\n// ---------------------------------------------------------------------------\n\n}; // namespace android\n\n#endif // ANDROID_UI_BUFFER_MAPPER_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/PixelFormat.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n\n// Pixel formats used across the system.\n// These formats might not all be supported by all renderers, for instance\n// skia or SurfaceFlinger are not required to support all of these formats\n// (either as source or destination)\n\n\n#ifndef UI_PIXELFORMAT_H\n#define UI_PIXELFORMAT_H\n\n#include <hardware/hardware.h>\n\nnamespace android {\n\nenum {\n    //\n    // these constants need to match those\n    // in graphics/PixelFormat.java & pixelflinger/format.h\n    //\n    PIXEL_FORMAT_UNKNOWN    =   0,\n    PIXEL_FORMAT_NONE       =   0,\n\n    // logical pixel formats used by the SurfaceFlinger -----------------------\n    PIXEL_FORMAT_CUSTOM         = -4,\n        // Custom pixel-format described by a PixelFormatInfo structure\n\n    PIXEL_FORMAT_TRANSLUCENT    = -3,\n        // System chooses a format that supports translucency (many alpha bits)\n\n    PIXEL_FORMAT_TRANSPARENT    = -2,\n        // System chooses a format that supports transparency\n        // (at least 1 alpha bit)\n\n    PIXEL_FORMAT_OPAQUE         = -1,\n        // System chooses an opaque format (no alpha bits required)\n\n    // real pixel formats supported for rendering -----------------------------\n\n    PIXEL_FORMAT_RGBA_8888   = HAL_PIXEL_FORMAT_RGBA_8888,   // 4x8-bit RGBA\n    PIXEL_FORMAT_RGBX_8888   = HAL_PIXEL_FORMAT_RGBX_8888,   // 4x8-bit RGB0\n    PIXEL_FORMAT_RGB_888     = HAL_PIXEL_FORMAT_RGB_888,     // 3x8-bit RGB\n    PIXEL_FORMAT_RGB_565     = HAL_PIXEL_FORMAT_RGB_565,     // 16-bit RGB\n    PIXEL_FORMAT_BGRA_8888   = HAL_PIXEL_FORMAT_BGRA_8888,   // 4x8-bit BGRA\n    PIXEL_FORMAT_RGBA_5551   = 6,                            // 16-bit ARGB\n    PIXEL_FORMAT_RGBA_4444   = 7,                            // 16-bit ARGB\n};\n\ntypedef int32_t PixelFormat;\n\nuint32_t bytesPerPixel(PixelFormat format);\nuint32_t bitsPerPixel(PixelFormat format);\n\n}; // namespace android\n\n#endif // UI_PIXELFORMAT_H\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/Point.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_POINT\n#define ANDROID_UI_POINT\n\n#include <utils/Flattenable.h>\n#include <utils/TypeHelpers.h>\n\nnamespace android {\n\nclass Point : public LightFlattenablePod<Point>\n{\npublic:\n    int x;\n    int y;\n\n    // we don't provide copy-ctor and operator= on purpose\n    // because we want the compiler generated versions\n\n    // Default constructor doesn't initialize the Point\n    inline Point() {\n    }\n    inline Point(int x, int y) : x(x), y(y) {\n    }\n\n    inline bool operator == (const Point& rhs) const {\n        return (x == rhs.x) && (y == rhs.y);\n    }\n    inline bool operator != (const Point& rhs) const {\n        return !operator == (rhs);\n    }\n\n    inline bool isOrigin() const {\n        return !(x|y);\n    }\n\n    // operator < defines an order which allows to use points in sorted\n    // vectors.\n    bool operator < (const Point& rhs) const {\n        return y<rhs.y || (y==rhs.y && x<rhs.x);\n    }\n\n    inline Point& operator - () {\n        x = -x;\n        y = -y;\n        return *this;\n    }\n    \n    inline Point& operator += (const Point& rhs) {\n        x += rhs.x;\n        y += rhs.y;\n        return *this;\n    }\n    inline Point& operator -= (const Point& rhs) {\n        x -= rhs.x;\n        y -= rhs.y;\n        return *this;\n    }\n    \n    const Point operator + (const Point& rhs) const {\n        const Point result(x+rhs.x, y+rhs.y);\n        return result;\n    }\n    const Point operator - (const Point& rhs) const {\n        const Point result(x-rhs.x, y-rhs.y);\n        return result;\n    }    \n};\n\nANDROID_BASIC_TYPES_TRAITS(Point)\n\n}; // namespace android\n\n#endif // ANDROID_UI_POINT\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/Rect.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_RECT\n#define ANDROID_UI_RECT\n\n#include <utils/Flattenable.h>\n#include <utils/Log.h>\n#include <utils/TypeHelpers.h>\n#include <ui/Point.h>\n\n#include <android/rect.h>\n\nnamespace android {\n\nclass Rect : public ARect, public LightFlattenablePod<Rect>\n{\npublic:\n    typedef ARect::value_type value_type;\n\n    static const Rect INVALID_RECT;\n\n    // we don't provide copy-ctor and operator= on purpose\n    // because we want the compiler generated versions\n\n    inline Rect() {\n      left = right = top = bottom = 0;\n    }\n\n    inline Rect(int32_t w, int32_t h) {\n        left = top = 0;\n        right = w;\n        bottom = h;\n    }\n\n    inline Rect(uint32_t w, uint32_t h) {\n        if (w > INT32_MAX) {\n            ALOG(LOG_WARN, \"Rect\",\n                    \"Width %u too large for Rect class, clamping\", w);\n            w = INT32_MAX;\n        }\n        if (h > INT32_MAX) {\n            ALOG(LOG_WARN, \"Rect\",\n                    \"Height %u too large for Rect class, clamping\", h);\n            h = INT32_MAX;\n        }\n        left = top = 0;\n        right = w;\n        bottom = h;\n    }\n\n    inline Rect(int32_t l, int32_t t, int32_t r, int32_t b) {\n        left = l;\n        top = t;\n        right = r;\n        bottom = b;\n    }\n\n    inline Rect(const Point& lt, const Point& rb) {\n        left = lt.x;\n        top = lt.y;\n        right = rb.x;\n        bottom = rb.y;\n    }\n\n    void makeInvalid();\n\n    inline void clear() {\n        left = top = right = bottom = 0;\n    }\n\n    // a valid rectangle has a non negative width and height\n    inline bool isValid() const {\n        return (getWidth() >= 0) && (getHeight() >= 0);\n    }\n\n    // an empty rect has a zero width or height, or is invalid\n    inline bool isEmpty() const {\n        return (getWidth() <= 0) || (getHeight() <= 0);\n    }\n\n    // rectangle's width\n    inline int32_t getWidth() const {\n        return right - left;\n    }\n\n    // rectangle's height\n    inline int32_t getHeight() const {\n        return bottom - top;\n    }\n\n    inline Rect getBounds() const {\n        return Rect(right - left, bottom - top);\n    }\n\n    void setLeftTop(const Point& lt) {\n        left = lt.x;\n        top = lt.y;\n    }\n\n    void setRightBottom(const Point& rb) {\n        right = rb.x;\n        bottom = rb.y;\n    }\n    \n    // the following 4 functions return the 4 corners of the rect as Point\n    Point leftTop() const {\n        return Point(left, top);\n    }\n    Point rightBottom() const {\n        return Point(right, bottom);\n    }\n    Point rightTop() const {\n        return Point(right, top);\n    }\n    Point leftBottom() const {\n        return Point(left, bottom);\n    }\n\n    // comparisons\n    inline bool operator == (const Rect& rhs) const {\n        return (left == rhs.left) && (top == rhs.top) &&\n               (right == rhs.right) && (bottom == rhs.bottom);\n    }\n\n    inline bool operator != (const Rect& rhs) const {\n        return !operator == (rhs);\n    }\n\n    // operator < defines an order which allows to use rectangles in sorted\n    // vectors.\n    bool operator < (const Rect& rhs) const;\n\n    const Rect operator + (const Point& rhs) const;\n    const Rect operator - (const Point& rhs) const;\n\n    Rect& operator += (const Point& rhs) {\n        return offsetBy(rhs.x, rhs.y);\n    }\n    Rect& operator -= (const Point& rhs) {\n        return offsetBy(-rhs.x, -rhs.y);\n    }\n\n    Rect& offsetToOrigin() {\n        right -= left;\n        bottom -= top;\n        left = top = 0;\n        return *this;\n    }\n    Rect& offsetTo(const Point& p) {\n        return offsetTo(p.x, p.y);\n    }\n    Rect& offsetBy(const Point& dp) {\n        return offsetBy(dp.x, dp.y);\n    }\n\n    Rect& offsetTo(int32_t x, int32_t y);\n    Rect& offsetBy(int32_t x, int32_t y);\n\n    bool intersect(const Rect& with, Rect* result) const;\n\n    // Create a new Rect by transforming this one using a graphics HAL\n    // transform.  This rectangle is defined in a coordinate space starting at\n    // the origin and extending to (width, height).  If the transform includes\n    // a ROT90 then the output rectangle is defined in a space extending to\n    // (height, width).  Otherwise the output rectangle is in the same space as\n    // the input.\n    Rect transform(uint32_t xform, int32_t width, int32_t height) const;\n\n    // this calculates (Region(*this) - exclude).bounds() efficiently\n    Rect reduce(const Rect& exclude) const;\n\n\n    // for backward compatibility\n    inline int32_t width() const { return getWidth(); }\n    inline int32_t height() const { return getHeight(); }\n    inline void set(const Rect& rhs) { operator = (rhs); }\n};\n\nANDROID_BASIC_TYPES_TRAITS(Rect)\n\n}; // namespace android\n\n#endif // ANDROID_UI_RECT\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/Region.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_REGION_H\n#define ANDROID_UI_REGION_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Vector.h>\n\n#include <ui/Rect.h>\n#include <utils/Flattenable.h>\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\nclass SharedBuffer;\nclass String8;\n\n// ---------------------------------------------------------------------------\nclass Region : public LightFlattenable<Region>\n{\npublic:\n    static const Region INVALID_REGION;\n\n                        Region();\n                        Region(const Region& rhs);\n    explicit            Region(const Rect& rhs);\n                        ~Region();\n\n    static  Region      createTJunctionFreeRegion(const Region& r);\n\n        Region& operator = (const Region& rhs);\n\n    inline  bool        isEmpty() const     { return getBounds().isEmpty(); }\n    inline  bool        isRect() const      { return mStorage.size() == 1; }\n\n    inline  Rect        getBounds() const   { return mStorage[mStorage.size() - 1]; }\n    inline  Rect        bounds() const      { return getBounds(); }\n\n            bool        contains(const Point& point) const;\n            bool        contains(int x, int y) const;\n\n            // the region becomes its bounds\n            Region&     makeBoundsSelf();\n\n            void        clear();\n            void        set(const Rect& r);\n            void        set(int32_t w, int32_t h);\n            void        set(uint32_t w, uint32_t h);\n\n            Region&     orSelf(const Rect& rhs);\n            Region&     xorSelf(const Rect& rhs);\n            Region&     andSelf(const Rect& rhs);\n            Region&     subtractSelf(const Rect& rhs);\n\n            // boolean operators, applied on this\n            Region&     orSelf(const Region& rhs);\n            Region&     xorSelf(const Region& rhs);\n            Region&     andSelf(const Region& rhs);\n            Region&     subtractSelf(const Region& rhs);\n\n            // boolean operators\n    const   Region      merge(const Rect& rhs) const;\n    const   Region      mergeExclusive(const Rect& rhs) const;\n    const   Region      intersect(const Rect& rhs) const;\n    const   Region      subtract(const Rect& rhs) const;\n\n            // boolean operators\n    const   Region      merge(const Region& rhs) const;\n    const   Region      mergeExclusive(const Region& rhs) const;\n    const   Region      intersect(const Region& rhs) const;\n    const   Region      subtract(const Region& rhs) const;\n\n            // these translate rhs first\n            Region&     translateSelf(int dx, int dy);\n            Region&     orSelf(const Region& rhs, int dx, int dy);\n            Region&     xorSelf(const Region& rhs, int dx, int dy);\n            Region&     andSelf(const Region& rhs, int dx, int dy);\n            Region&     subtractSelf(const Region& rhs, int dx, int dy);\n\n            // these translate rhs first\n    const   Region      translate(int dx, int dy) const;\n    const   Region      merge(const Region& rhs, int dx, int dy) const;\n    const   Region      mergeExclusive(const Region& rhs, int dx, int dy) const;\n    const   Region      intersect(const Region& rhs, int dx, int dy) const;\n    const   Region      subtract(const Region& rhs, int dx, int dy) const;\n\n    // convenience operators overloads\n    inline  const Region      operator | (const Region& rhs) const;\n    inline  const Region      operator ^ (const Region& rhs) const;\n    inline  const Region      operator & (const Region& rhs) const;\n    inline  const Region      operator - (const Region& rhs) const;\n    inline  const Region      operator + (const Point& pt) const;\n\n    inline  Region&     operator |= (const Region& rhs);\n    inline  Region&     operator ^= (const Region& rhs);\n    inline  Region&     operator &= (const Region& rhs);\n    inline  Region&     operator -= (const Region& rhs);\n    inline  Region&     operator += (const Point& pt);\n\n\n    // returns true if the regions share the same underlying storage\n    bool isTriviallyEqual(const Region& region) const;\n\n\n    /* various ways to access the rectangle list */\n\n\n    // STL-like iterators\n    typedef Rect const* const_iterator;\n    const_iterator begin() const;\n    const_iterator end() const;\n\n    // returns an array of rect which has the same life-time has this\n    // Region object.\n    Rect const* getArray(size_t* count) const;\n\n    // returns a SharedBuffer as well as the number of rects.\n    // ownership is transfered to the caller.\n    // the caller must call SharedBuffer::release() to free the memory.\n    SharedBuffer const* getSharedBuffer(size_t* count) const;\n\n    /* no user serviceable parts here... */\n\n            // add a rectangle to the internal list. This rectangle must\n            // be sorted in Y and X and must not make the region invalid.\n            void        addRectUnchecked(int l, int t, int r, int b);\n\n    inline  bool        isFixedSize() const { return false; }\n            size_t      getFlattenedSize() const;\n            status_t    flatten(void* buffer, size_t size) const;\n            status_t    unflatten(void const* buffer, size_t size);\n\n    void        dump(String8& out, const char* what, uint32_t flags=0) const;\n    void        dump(const char* what, uint32_t flags=0) const;\n\nprivate:\n    class rasterizer;\n    friend class rasterizer;\n\n    Region& operationSelf(const Rect& r, int op);\n    Region& operationSelf(const Region& r, int op);\n    Region& operationSelf(const Region& r, int dx, int dy, int op);\n    const Region operation(const Rect& rhs, int op) const;\n    const Region operation(const Region& rhs, int op) const;\n    const Region operation(const Region& rhs, int dx, int dy, int op) const;\n\n    static void boolean_operation(int op, Region& dst,\n            const Region& lhs, const Region& rhs, int dx, int dy);\n    static void boolean_operation(int op, Region& dst,\n            const Region& lhs, const Rect& rhs, int dx, int dy);\n\n    static void boolean_operation(int op, Region& dst,\n            const Region& lhs, const Region& rhs);\n    static void boolean_operation(int op, Region& dst,\n            const Region& lhs, const Rect& rhs);\n\n    static void translate(Region& reg, int dx, int dy);\n    static void translate(Region& dst, const Region& reg, int dx, int dy);\n\n    static bool validate(const Region& reg,\n            const char* name, bool silent = false);\n\n    // mStorage is a (manually) sorted array of Rects describing the region\n    // with an extra Rect as the last element which is set to the\n    // bounds of the region. However, if the region is\n    // a simple Rect then mStorage contains only that rect.\n    Vector<Rect> mStorage;\n};\n\n\nconst Region Region::operator | (const Region& rhs) const {\n    return merge(rhs);\n}\nconst Region Region::operator ^ (const Region& rhs) const {\n    return mergeExclusive(rhs);\n}\nconst Region Region::operator & (const Region& rhs) const {\n    return intersect(rhs);\n}\nconst Region Region::operator - (const Region& rhs) const {\n    return subtract(rhs);\n}\nconst Region Region::operator + (const Point& pt) const {\n    return translate(pt.x, pt.y);\n}\n\n\nRegion& Region::operator |= (const Region& rhs) {\n    return orSelf(rhs);\n}\nRegion& Region::operator ^= (const Region& rhs) {\n    return xorSelf(rhs);\n}\nRegion& Region::operator &= (const Region& rhs) {\n    return andSelf(rhs);\n}\nRegion& Region::operator -= (const Region& rhs) {\n    return subtractSelf(rhs);\n}\nRegion& Region::operator += (const Point& pt) {\n    return translateSelf(pt.x, pt.y);\n}\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_UI_REGION_H\n\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/TMatHelpers.h",
    "content": "/*\n * Copyright 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef TMAT_IMPLEMENTATION\n#error \"Don't include TMatHelpers.h directly. use ui/mat*.h instead\"\n#else\n#undef TMAT_IMPLEMENTATION\n#endif\n\n\n#ifndef UI_TMAT_HELPERS_H\n#define UI_TMAT_HELPERS_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <math.h>\n#include <utils/Debug.h>\n#include <utils/String8.h>\n\n#define PURE __attribute__((pure))\n\nnamespace android {\n// -------------------------------------------------------------------------------------\n\n/*\n * No user serviceable parts here.\n *\n * Don't use this file directly, instead include ui/mat*.h\n */\n\n\n/*\n * Matrix utilities\n */\n\nnamespace matrix {\n\ninline int     PURE transpose(int v)    { return v; }\ninline float   PURE transpose(float v)  { return v; }\ninline double  PURE transpose(double v) { return v; }\n\ninline int     PURE trace(int v)    { return v; }\ninline float   PURE trace(float v)  { return v; }\ninline double  PURE trace(double v) { return v; }\n\ntemplate<typename MATRIX>\nMATRIX PURE inverse(const MATRIX& src) {\n\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX::COL_SIZE == MATRIX::ROW_SIZE );\n\n    typename MATRIX::value_type t;\n    const size_t N = MATRIX::col_size();\n    size_t swap;\n    MATRIX tmp(src);\n    MATRIX inverse(1);\n\n    for (size_t i=0 ; i<N ; i++) {\n        // look for largest element in column\n        swap = i;\n        for (size_t j=i+1 ; j<N ; j++) {\n            if (fabs(tmp[j][i]) > fabs(tmp[i][i])) {\n                swap = j;\n            }\n        }\n\n        if (swap != i) {\n            /* swap rows. */\n            for (size_t k=0 ; k<N ; k++) {\n                t = tmp[i][k];\n                tmp[i][k] = tmp[swap][k];\n                tmp[swap][k] = t;\n\n                t = inverse[i][k];\n                inverse[i][k] = inverse[swap][k];\n                inverse[swap][k] = t;\n            }\n        }\n\n        t = 1 / tmp[i][i];\n        for (size_t k=0 ; k<N ; k++) {\n            tmp[i][k] *= t;\n            inverse[i][k] *= t;\n        }\n        for (size_t j=0 ; j<N ; j++) {\n            if (j != i) {\n                t = tmp[j][i];\n                for (size_t k=0 ; k<N ; k++) {\n                    tmp[j][k] -= tmp[i][k] * t;\n                    inverse[j][k] -= inverse[i][k] * t;\n                }\n            }\n        }\n    }\n    return inverse;\n}\n\ntemplate<typename MATRIX_R, typename MATRIX_A, typename MATRIX_B>\nMATRIX_R PURE multiply(const MATRIX_A& lhs, const MATRIX_B& rhs) {\n    // pre-requisite:\n    //  lhs : D columns, R rows\n    //  rhs : C columns, D rows\n    //  res : C columns, R rows\n\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX_A::ROW_SIZE == MATRIX_B::COL_SIZE );\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX_R::ROW_SIZE == MATRIX_B::ROW_SIZE );\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX_R::COL_SIZE == MATRIX_A::COL_SIZE );\n\n    MATRIX_R res(MATRIX_R::NO_INIT);\n    for (size_t r=0 ; r<MATRIX_R::row_size() ; r++) {\n        res[r] = lhs * rhs[r];\n    }\n    return res;\n}\n\n// transpose. this handles matrices of matrices\ntemplate <typename MATRIX>\nMATRIX PURE transpose(const MATRIX& m) {\n    // for now we only handle square matrix transpose\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX::ROW_SIZE == MATRIX::COL_SIZE );\n    MATRIX result(MATRIX::NO_INIT);\n    for (size_t r=0 ; r<MATRIX::row_size() ; r++)\n        for (size_t c=0 ; c<MATRIX::col_size() ; c++)\n            result[c][r] = transpose(m[r][c]);\n    return result;\n}\n\n// trace. this handles matrices of matrices\ntemplate <typename MATRIX>\ntypename MATRIX::value_type PURE trace(const MATRIX& m) {\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX::ROW_SIZE == MATRIX::COL_SIZE );\n    typename MATRIX::value_type result(0);\n    for (size_t r=0 ; r<MATRIX::row_size() ; r++)\n        result += trace(m[r][r]);\n    return result;\n}\n\n// trace. this handles matrices of matrices\ntemplate <typename MATRIX>\ntypename MATRIX::col_type PURE diag(const MATRIX& m) {\n    COMPILE_TIME_ASSERT_FUNCTION_SCOPE( MATRIX::ROW_SIZE == MATRIX::COL_SIZE );\n    typename MATRIX::col_type result(MATRIX::col_type::NO_INIT);\n    for (size_t r=0 ; r<MATRIX::row_size() ; r++)\n        result[r] = m[r][r];\n    return result;\n}\n\ntemplate <typename MATRIX>\nString8 asString(const MATRIX& m) {\n    String8 s;\n    for (size_t c=0 ; c<MATRIX::col_size() ; c++) {\n        s.append(\"|  \");\n        for (size_t r=0 ; r<MATRIX::row_size() ; r++) {\n            s.appendFormat(\"%7.2f  \", m[r][c]);\n        }\n        s.append(\"|\\n\");\n    }\n    return s;\n}\n\n}; // namespace matrix\n\n// -------------------------------------------------------------------------------------\n\n/*\n * TMatProductOperators implements basic arithmetic and basic compound assignments\n * operators on a vector of type BASE<T>.\n *\n * BASE only needs to implement operator[] and size().\n * By simply inheriting from TMatProductOperators<BASE, T> BASE will automatically\n * get all the functionality here.\n */\n\ntemplate <template<typename T> class BASE, typename T>\nclass TMatProductOperators {\npublic:\n    // multiply by a scalar\n    BASE<T>& operator *= (T v) {\n        BASE<T>& lhs(static_cast< BASE<T>& >(*this));\n        for (size_t r=0 ; r<lhs.row_size() ; r++) {\n            lhs[r] *= v;\n        }\n        return lhs;\n    }\n\n    // divide by a scalar\n    BASE<T>& operator /= (T v) {\n        BASE<T>& lhs(static_cast< BASE<T>& >(*this));\n        for (size_t r=0 ; r<lhs.row_size() ; r++) {\n            lhs[r] /= v;\n        }\n        return lhs;\n    }\n\n    // matrix * matrix, result is a matrix of the same type than the lhs matrix\n    template<typename U>\n    friend BASE<T> PURE operator *(const BASE<T>& lhs, const BASE<U>& rhs) {\n        return matrix::multiply<BASE<T> >(lhs, rhs);\n    }\n};\n\n\n/*\n * TMatSquareFunctions implements functions on a matrix of type BASE<T>.\n *\n * BASE only needs to implement:\n *  - operator[]\n *  - col_type\n *  - row_type\n *  - COL_SIZE\n *  - ROW_SIZE\n *\n * By simply inheriting from TMatSquareFunctions<BASE, T> BASE will automatically\n * get all the functionality here.\n */\n\ntemplate<template<typename U> class BASE, typename T>\nclass TMatSquareFunctions {\npublic:\n    /*\n     * NOTE: the functions below ARE NOT member methods. They are friend functions\n     * with they definition inlined with their declaration. This makes these\n     * template functions available to the compiler when (and only when) this class\n     * is instantiated, at which point they're only templated on the 2nd parameter\n     * (the first one, BASE<T> being known).\n     */\n    friend BASE<T> PURE inverse(const BASE<T>& m)   { return matrix::inverse(m); }\n    friend BASE<T> PURE transpose(const BASE<T>& m) { return matrix::transpose(m); }\n    friend T       PURE trace(const BASE<T>& m)     { return matrix::trace(m); }\n};\n\ntemplate <template<typename T> class BASE, typename T>\nclass TMatDebug {\npublic:\n    String8 asString() const {\n        return matrix::asString( static_cast< const BASE<T>& >(*this) );\n    }\n};\n\n// -------------------------------------------------------------------------------------\n}; // namespace android\n\n#undef PURE\n\n#endif /* UI_TMAT_HELPERS_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/TVecHelpers.h",
    "content": "/*\n * Copyright 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef TVEC_IMPLEMENTATION\n#error \"Don't include TVecHelpers.h directly. use ui/vec*.h instead\"\n#else\n#undef TVEC_IMPLEMENTATION\n#endif\n\n\n#ifndef UI_TVEC_HELPERS_H\n#define UI_TVEC_HELPERS_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#define PURE __attribute__((pure))\n\nnamespace android {\n// -------------------------------------------------------------------------------------\n\n/*\n * No user serviceable parts here.\n *\n * Don't use this file directly, instead include ui/vec{2|3|4}.h\n */\n\n/*\n * This class casts itself into anything and assign itself from anything!\n * Use with caution!\n */\ntemplate <typename TYPE>\nstruct Impersonator {\n    Impersonator& operator = (const TYPE& rhs) {\n        reinterpret_cast<TYPE&>(*this) = rhs;\n        return *this;\n    }\n    operator TYPE& () {\n        return reinterpret_cast<TYPE&>(*this);\n    }\n    operator TYPE const& () const {\n        return reinterpret_cast<TYPE const&>(*this);\n    }\n};\n\n/*\n * TVec{Add|Product}Operators implements basic arithmetic and basic compound assignments\n * operators on a vector of type BASE<T>.\n *\n * BASE only needs to implement operator[] and size().\n * By simply inheriting from TVec{Add|Product}Operators<BASE, T> BASE will automatically\n * get all the functionality here.\n */\n\ntemplate <template<typename T> class BASE, typename T>\nclass TVecAddOperators {\npublic:\n    /* compound assignment from a another vector of the same size but different\n     * element type.\n     */\n    template <typename OTHER>\n    BASE<T>& operator += (const BASE<OTHER>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] += v[i];\n        }\n        return rhs;\n    }\n    template <typename OTHER>\n    BASE<T>& operator -= (const BASE<OTHER>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] -= v[i];\n        }\n        return rhs;\n    }\n\n    /* compound assignment from a another vector of the same type.\n     * These operators can be used for implicit conversion and  handle operations\n     * like \"vector *= scalar\" by letting the compiler implicitly convert a scalar\n     * to a vector (assuming the BASE<T> allows it).\n     */\n    BASE<T>& operator += (const BASE<T>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] += v[i];\n        }\n        return rhs;\n    }\n    BASE<T>& operator -= (const BASE<T>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] -= v[i];\n        }\n        return rhs;\n    }\n\n    /*\n     * NOTE: the functions below ARE NOT member methods. They are friend functions\n     * with they definition inlined with their declaration. This makes these\n     * template functions available to the compiler when (and only when) this class\n     * is instantiated, at which point they're only templated on the 2nd parameter\n     * (the first one, BASE<T> being known).\n     */\n\n    /* The operators below handle operation between vectors of the same side\n     * but of a different element type.\n     */\n    template<typename RT>\n    friend inline\n    BASE<T> PURE operator +(const BASE<T>& lv, const BASE<RT>& rv) {\n        return BASE<T>(lv) += rv;\n    }\n    template<typename RT>\n    friend inline\n    BASE<T> PURE operator -(const BASE<T>& lv, const BASE<RT>& rv) {\n        return BASE<T>(lv) -= rv;\n    }\n\n    /* The operators below (which are not templates once this class is instanced,\n     * i.e.: BASE<T> is known) can be used for implicit conversion on both sides.\n     * These handle operations like \"vector * scalar\" and \"scalar * vector\" by\n     * letting the compiler implicitly convert a scalar to a vector (assuming\n     * the BASE<T> allows it).\n     */\n    friend inline\n    BASE<T> PURE operator +(const BASE<T>& lv, const BASE<T>& rv) {\n        return BASE<T>(lv) += rv;\n    }\n    friend inline\n    BASE<T> PURE operator -(const BASE<T>& lv, const BASE<T>& rv) {\n        return BASE<T>(lv) -= rv;\n    }\n};\n\ntemplate <template<typename T> class BASE, typename T>\nclass TVecProductOperators {\npublic:\n    /* compound assignment from a another vector of the same size but different\n     * element type.\n     */\n    template <typename OTHER>\n    BASE<T>& operator *= (const BASE<OTHER>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] *= v[i];\n        }\n        return rhs;\n    }\n    template <typename OTHER>\n    BASE<T>& operator /= (const BASE<OTHER>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] /= v[i];\n        }\n        return rhs;\n    }\n\n    /* compound assignment from a another vector of the same type.\n     * These operators can be used for implicit conversion and  handle operations\n     * like \"vector *= scalar\" by letting the compiler implicitly convert a scalar\n     * to a vector (assuming the BASE<T> allows it).\n     */\n    BASE<T>& operator *= (const BASE<T>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] *= v[i];\n        }\n        return rhs;\n    }\n    BASE<T>& operator /= (const BASE<T>& v) {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            rhs[i] /= v[i];\n        }\n        return rhs;\n    }\n\n    /*\n     * NOTE: the functions below ARE NOT member methods. They are friend functions\n     * with they definition inlined with their declaration. This makes these\n     * template functions available to the compiler when (and only when) this class\n     * is instantiated, at which point they're only templated on the 2nd parameter\n     * (the first one, BASE<T> being known).\n     */\n\n    /* The operators below handle operation between vectors of the same side\n     * but of a different element type.\n     */\n    template<typename RT>\n    friend inline\n    BASE<T> PURE operator *(const BASE<T>& lv, const BASE<RT>& rv) {\n        return BASE<T>(lv) *= rv;\n    }\n    template<typename RT>\n    friend inline\n    BASE<T> PURE operator /(const BASE<T>& lv, const BASE<RT>& rv) {\n        return BASE<T>(lv) /= rv;\n    }\n\n    /* The operators below (which are not templates once this class is instanced,\n     * i.e.: BASE<T> is known) can be used for implicit conversion on both sides.\n     * These handle operations like \"vector * scalar\" and \"scalar * vector\" by\n     * letting the compiler implicitly convert a scalar to a vector (assuming\n     * the BASE<T> allows it).\n     */\n    friend inline\n    BASE<T> PURE operator *(const BASE<T>& lv, const BASE<T>& rv) {\n        return BASE<T>(lv) *= rv;\n    }\n    friend inline\n    BASE<T> PURE operator /(const BASE<T>& lv, const BASE<T>& rv) {\n        return BASE<T>(lv) /= rv;\n    }\n};\n\n/*\n * TVecUnaryOperators implements unary operators on a vector of type BASE<T>.\n *\n * BASE only needs to implement operator[] and size().\n * By simply inheriting from TVecUnaryOperators<BASE, T> BASE will automatically\n * get all the functionality here.\n *\n * These operators are implemented as friend functions of TVecUnaryOperators<BASE, T>\n */\ntemplate <template<typename T> class BASE, typename T>\nclass TVecUnaryOperators {\npublic:\n    BASE<T>& operator ++ () {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            ++rhs[i];\n        }\n        return rhs;\n    }\n    BASE<T>& operator -- () {\n        BASE<T>& rhs = static_cast<BASE<T>&>(*this);\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            --rhs[i];\n        }\n        return rhs;\n    }\n    BASE<T> operator - () const {\n        BASE<T> r(BASE<T>::NO_INIT);\n        BASE<T> const& rv(static_cast<BASE<T> const&>(*this));\n        for (size_t i=0 ; i<BASE<T>::size() ; i++) {\n            r[i] = -rv[i];\n        }\n        return r;\n    }\n};\n\n\n/*\n * TVecComparisonOperators implements relational/comparison operators\n * on a vector of type BASE<T>.\n *\n * BASE only needs to implement operator[] and size().\n * By simply inheriting from TVecComparisonOperators<BASE, T> BASE will automatically\n * get all the functionality here.\n */\ntemplate <template<typename T> class BASE, typename T>\nclass TVecComparisonOperators {\npublic:\n    /*\n     * NOTE: the functions below ARE NOT member methods. They are friend functions\n     * with they definition inlined with their declaration. This makes these\n     * template functions available to the compiler when (and only when) this class\n     * is instantiated, at which point they're only templated on the 2nd parameter\n     * (the first one, BASE<T> being known).\n     */\n    template<typename RT>\n    friend inline\n    bool PURE operator ==(const BASE<T>& lv, const BASE<RT>& rv) {\n        for (size_t i = 0; i < BASE<T>::size(); i++)\n            if (lv[i] != rv[i])\n                return false;\n        return true;\n    }\n\n    template<typename RT>\n    friend inline\n    bool PURE operator !=(const BASE<T>& lv, const BASE<RT>& rv) {\n        return !operator ==(lv, rv);\n    }\n\n    template<typename RT>\n    friend inline\n    bool PURE operator >(const BASE<T>& lv, const BASE<RT>& rv) {\n        for (size_t i = 0; i < BASE<T>::size(); i++)\n            if (lv[i] <= rv[i])\n                return false;\n        return true;\n    }\n\n    template<typename RT>\n    friend inline\n    bool PURE operator <=(const BASE<T>& lv, const BASE<RT>& rv) {\n        return !(lv > rv);\n    }\n\n    template<typename RT>\n    friend inline\n    bool PURE operator <(const BASE<T>& lv, const BASE<RT>& rv) {\n        for (size_t i = 0; i < BASE<T>::size(); i++)\n            if (lv[i] >= rv[i])\n                return false;\n        return true;\n    }\n\n    template<typename RT>\n    friend inline\n    bool PURE operator >=(const BASE<T>& lv, const BASE<RT>& rv) {\n        return !(lv < rv);\n    }\n};\n\n\n/*\n * TVecFunctions implements functions on a vector of type BASE<T>.\n *\n * BASE only needs to implement operator[] and size().\n * By simply inheriting from TVecFunctions<BASE, T> BASE will automatically\n * get all the functionality here.\n */\ntemplate <template<typename T> class BASE, typename T>\nclass TVecFunctions {\npublic:\n    /*\n     * NOTE: the functions below ARE NOT member methods. They are friend functions\n     * with they definition inlined with their declaration. This makes these\n     * template functions available to the compiler when (and only when) this class\n     * is instantiated, at which point they're only templated on the 2nd parameter\n     * (the first one, BASE<T> being known).\n     */\n    template<typename RT>\n    friend inline\n    T PURE dot(const BASE<T>& lv, const BASE<RT>& rv) {\n        T r(0);\n        for (size_t i = 0; i < BASE<T>::size(); i++)\n            r += lv[i]*rv[i];\n        return r;\n    }\n\n    friend inline\n    T PURE length(const BASE<T>& lv) {\n        return sqrt( dot(lv, lv) );\n    }\n\n    template<typename RT>\n    friend inline\n    T PURE distance(const BASE<T>& lv, const BASE<RT>& rv) {\n        return length(rv - lv);\n    }\n\n    friend inline\n    BASE<T> PURE normalize(const BASE<T>& lv) {\n        return lv * (1 / length(lv));\n    }\n};\n\n#undef PURE\n\n// -------------------------------------------------------------------------------------\n}; // namespace android\n\n\n#endif /* UI_TVEC_HELPERS_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/UiConfig.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UI_CONFIG_H\n#define ANDROID_UI_CONFIG_H\n\n#include <utils/String8.h>\n\nnamespace android {\n\n// Append the libui configuration details to configStr.\nvoid appendUiConfigString(String8& configStr);\n\n}; // namespace android\n\n#endif /*ANDROID_UI_CONFIG_H*/\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/mat4.h",
    "content": "/*\n * Copyright 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef UI_MAT4_H\n#define UI_MAT4_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <ui/vec4.h>\n#include <utils/String8.h>\n\n#define TMAT_IMPLEMENTATION\n#include <ui/TMatHelpers.h>\n\n#define PURE __attribute__((pure))\n\nnamespace android {\n// -------------------------------------------------------------------------------------\n\ntemplate <typename T>\nclass tmat44 :  public TVecUnaryOperators<tmat44, T>,\n                public TVecComparisonOperators<tmat44, T>,\n                public TVecAddOperators<tmat44, T>,\n                public TMatProductOperators<tmat44, T>,\n                public TMatSquareFunctions<tmat44, T>,\n                public TMatDebug<tmat44, T>\n{\npublic:\n    enum no_init { NO_INIT };\n    typedef T value_type;\n    typedef T& reference;\n    typedef T const& const_reference;\n    typedef size_t size_type;\n    typedef tvec4<T> col_type;\n    typedef tvec4<T> row_type;\n\n    // size of a column (i.e.: number of rows)\n    enum { COL_SIZE = col_type::SIZE };\n    static inline size_t col_size() { return COL_SIZE; }\n\n    // size of a row (i.e.: number of columns)\n    enum { ROW_SIZE = row_type::SIZE };\n    static inline size_t row_size() { return ROW_SIZE; }\n    static inline size_t size()     { return row_size(); }  // for TVec*<>\n\nprivate:\n\n    /*\n     *  <--  N columns  -->\n     *\n     *  a00 a10 a20 ... aN0    ^\n     *  a01 a11 a21 ... aN1    |\n     *  a02 a12 a22 ... aN2  M rows\n     *  ...                    |\n     *  a0M a1M a2M ... aNM    v\n     *\n     *  COL_SIZE = M\n     *  ROW_SIZE = N\n     *  m[0] = [a00 a01 a02 ... a01M]\n     */\n\n    col_type mValue[ROW_SIZE];\n\npublic:\n    // array access\n    inline col_type const& operator [] (size_t i) const { return mValue[i]; }\n    inline col_type&       operator [] (size_t i)       { return mValue[i]; }\n\n    T const* asArray() const { return &mValue[0][0]; }\n\n    // -----------------------------------------------------------------------\n    // we don't provide copy-ctor and operator= on purpose\n    // because we want the compiler generated versions\n\n    /*\n     *  constructors\n     */\n\n    // leaves object uninitialized. use with caution.\n    explicit tmat44(no_init) { }\n\n    // initialize to identity\n    tmat44();\n\n    // initialize to Identity*scalar.\n    template<typename U>\n    explicit tmat44(U v);\n\n    // sets the diagonal to the passed vector\n    template <typename U>\n    explicit tmat44(const tvec4<U>& rhs);\n\n    // construct from another matrix of the same size\n    template <typename U>\n    explicit tmat44(const tmat44<U>& rhs);\n\n    // construct from 4 column vectors\n    template <typename A, typename B, typename C, typename D>\n    tmat44(const tvec4<A>& v0, const tvec4<B>& v1, const tvec4<C>& v2, const tvec4<D>& v3);\n\n    // construct from 16 scalars\n    template <\n        typename A, typename B, typename C, typename D,\n        typename E, typename F, typename G, typename H,\n        typename I, typename J, typename K, typename L,\n        typename M, typename N, typename O, typename P>\n    tmat44( A m00, B m01, C m02, D m03,\n            E m10, F m11, G m12, H m13,\n            I m20, J m21, K m22, L m23,\n            M m30, N m31, O m32, P m33);\n\n    // construct from a C array\n    template <typename U>\n    explicit tmat44(U const* rawArray);\n\n    /*\n     *  helpers\n     */\n\n    static tmat44 ortho(T left, T right, T bottom, T top, T near, T far);\n\n    static tmat44 frustum(T left, T right, T bottom, T top, T near, T far);\n\n    template <typename A, typename B, typename C>\n    static tmat44 lookAt(const tvec3<A>& eye, const tvec3<B>& center, const tvec3<C>& up);\n\n    template <typename A>\n    static tmat44 translate(const tvec4<A>& t);\n\n    template <typename A>\n    static tmat44 scale(const tvec4<A>& s);\n\n    template <typename A, typename B>\n    static tmat44 rotate(A radian, const tvec3<B>& about);\n};\n\n// ----------------------------------------------------------------------------------------\n// Constructors\n// ----------------------------------------------------------------------------------------\n\n/*\n * Since the matrix code could become pretty big quickly, we don't inline most\n * operations.\n */\n\ntemplate <typename T>\ntmat44<T>::tmat44() {\n    mValue[0] = col_type(1,0,0,0);\n    mValue[1] = col_type(0,1,0,0);\n    mValue[2] = col_type(0,0,1,0);\n    mValue[3] = col_type(0,0,0,1);\n}\n\ntemplate <typename T>\ntemplate <typename U>\ntmat44<T>::tmat44(U v) {\n    mValue[0] = col_type(v,0,0,0);\n    mValue[1] = col_type(0,v,0,0);\n    mValue[2] = col_type(0,0,v,0);\n    mValue[3] = col_type(0,0,0,v);\n}\n\ntemplate<typename T>\ntemplate<typename U>\ntmat44<T>::tmat44(const tvec4<U>& v) {\n    mValue[0] = col_type(v.x,0,0,0);\n    mValue[1] = col_type(0,v.y,0,0);\n    mValue[2] = col_type(0,0,v.z,0);\n    mValue[3] = col_type(0,0,0,v.w);\n}\n\n// construct from 16 scalars\ntemplate<typename T>\ntemplate <\n    typename A, typename B, typename C, typename D,\n    typename E, typename F, typename G, typename H,\n    typename I, typename J, typename K, typename L,\n    typename M, typename N, typename O, typename P>\ntmat44<T>::tmat44(  A m00, B m01, C m02, D m03,\n                    E m10, F m11, G m12, H m13,\n                    I m20, J m21, K m22, L m23,\n                    M m30, N m31, O m32, P m33) {\n    mValue[0] = col_type(m00, m01, m02, m03);\n    mValue[1] = col_type(m10, m11, m12, m13);\n    mValue[2] = col_type(m20, m21, m22, m23);\n    mValue[3] = col_type(m30, m31, m32, m33);\n}\n\ntemplate <typename T>\ntemplate <typename U>\ntmat44<T>::tmat44(const tmat44<U>& rhs) {\n    for (size_t r=0 ; r<row_size() ; r++)\n        mValue[r] = rhs[r];\n}\n\ntemplate <typename T>\ntemplate <typename A, typename B, typename C, typename D>\ntmat44<T>::tmat44(const tvec4<A>& v0, const tvec4<B>& v1, const tvec4<C>& v2, const tvec4<D>& v3) {\n    mValue[0] = v0;\n    mValue[1] = v1;\n    mValue[2] = v2;\n    mValue[3] = v3;\n}\n\ntemplate <typename T>\ntemplate <typename U>\ntmat44<T>::tmat44(U const* rawArray) {\n    for (size_t r=0 ; r<row_size() ; r++)\n        for (size_t c=0 ; c<col_size() ; c++)\n            mValue[r][c] = *rawArray++;\n}\n\n// ----------------------------------------------------------------------------------------\n// Helpers\n// ----------------------------------------------------------------------------------------\n\ntemplate <typename T>\ntmat44<T> tmat44<T>::ortho(T left, T right, T bottom, T top, T near, T far) {\n    tmat44<T> m;\n    m[0][0] =  2 / (right - left);\n    m[1][1] =  2 / (top   - bottom);\n    m[2][2] = -2 / (far   - near);\n    m[3][0] = -(right + left)   / (right - left);\n    m[3][1] = -(top   + bottom) / (top   - bottom);\n    m[3][2] = -(far   + near)   / (far   - near);\n    return m;\n}\n\ntemplate <typename T>\ntmat44<T> tmat44<T>::frustum(T left, T right, T bottom, T top, T near, T far) {\n    tmat44<T> m;\n    T A = (right + left)   / (right - left);\n    T B = (top   + bottom) / (top   - bottom);\n    T C = (far   + near)   / (far   - near);\n    T D = (2 * far * near) / (far   - near);\n    m[0][0] = (2 * near) / (right - left);\n    m[1][1] = (2 * near) / (top   - bottom);\n    m[2][0] = A;\n    m[2][1] = B;\n    m[2][2] = C;\n    m[2][3] =-1;\n    m[3][2] = D;\n    m[3][3] = 0;\n    return m;\n}\n\ntemplate <typename T>\ntemplate <typename A, typename B, typename C>\ntmat44<T> tmat44<T>::lookAt(const tvec3<A>& eye, const tvec3<B>& center, const tvec3<C>& up) {\n    tvec3<T> L(normalize(center - eye));\n    tvec3<T> S(normalize( cross(L, up) ));\n    tvec3<T> U(cross(S, L));\n    return tmat44<T>(\n            tvec4<T>( S, 0),\n            tvec4<T>( U, 0),\n            tvec4<T>(-L, 0),\n            tvec4<T>(-eye, 1));\n}\n\ntemplate <typename T>\ntemplate <typename A>\ntmat44<T> tmat44<T>::translate(const tvec4<A>& t) {\n    tmat44<T> r;\n    r[3] = t;\n    return r;\n}\n\ntemplate <typename T>\ntemplate <typename A>\ntmat44<T> tmat44<T>::scale(const tvec4<A>& s) {\n    tmat44<T> r;\n    r[0][0] = s[0];\n    r[1][1] = s[1];\n    r[2][2] = s[2];\n    r[3][3] = s[3];\n    return r;\n}\n\ntemplate <typename T>\ntemplate <typename A, typename B>\ntmat44<T> tmat44<T>::rotate(A radian, const tvec3<B>& about) {\n    tmat44<T> rotation;\n    T* r = const_cast<T*>(rotation.asArray());\n    T c = cos(radian);\n    T s = sin(radian);\n    if (about.x==1 && about.y==0 && about.z==0) {\n        r[5] = c;   r[10]= c;\n        r[6] = s;   r[9] = -s;\n    } else if (about.x==0 && about.y==1 && about.z==0) {\n        r[0] = c;   r[10]= c;\n        r[8] = s;   r[2] = -s;\n    } else if (about.x==0 && about.y==0 && about.z==1) {\n        r[0] = c;   r[5] = c;\n        r[1] = s;   r[4] = -s;\n    } else {\n        tvec3<B> nabout = normalize(about);\n        B x = nabout.x;\n        B y = nabout.y;\n        B z = nabout.z;\n        T nc = 1 - c;\n        T xy = x * y;\n        T yz = y * z;\n        T zx = z * x;\n        T xs = x * s;\n        T ys = y * s;\n        T zs = z * s;\n        r[ 0] = x*x*nc +  c;    r[ 4] =  xy*nc - zs;    r[ 8] =  zx*nc + ys;\n        r[ 1] =  xy*nc + zs;    r[ 5] = y*y*nc +  c;    r[ 9] =  yz*nc - xs;\n        r[ 2] =  zx*nc - ys;    r[ 6] =  yz*nc + xs;    r[10] = z*z*nc +  c;\n    }\n    return rotation;\n}\n\n// ----------------------------------------------------------------------------------------\n// Arithmetic operators outside of class\n// ----------------------------------------------------------------------------------------\n\n/* We use non-friend functions here to prevent the compiler from using\n * implicit conversions, for instance of a scalar to a vector. The result would\n * not be what the caller expects.\n *\n * Also note that the order of the arguments in the inner loop is important since\n * it determines the output type (only relevant when T != U).\n */\n\n// matrix * vector, result is a vector of the same type than the input vector\ntemplate <typename T, typename U>\ntypename tmat44<U>::col_type PURE operator *(const tmat44<T>& lv, const tvec4<U>& rv) {\n    typename tmat44<U>::col_type result;\n    for (size_t r=0 ; r<tmat44<T>::row_size() ; r++)\n        result += rv[r]*lv[r];\n    return result;\n}\n\n// vector * matrix, result is a vector of the same type than the input vector\ntemplate <typename T, typename U>\ntypename tmat44<U>::row_type PURE operator *(const tvec4<U>& rv, const tmat44<T>& lv) {\n    typename tmat44<U>::row_type result(tmat44<U>::row_type::NO_INIT);\n    for (size_t r=0 ; r<tmat44<T>::row_size() ; r++)\n        result[r] = dot(rv, lv[r]);\n    return result;\n}\n\n// matrix * scalar, result is a matrix of the same type than the input matrix\ntemplate <typename T, typename U>\ntmat44<T> PURE operator *(const tmat44<T>& lv, U rv) {\n    tmat44<T> result(tmat44<T>::NO_INIT);\n    for (size_t r=0 ; r<tmat44<T>::row_size() ; r++)\n        result[r] = lv[r]*rv;\n    return result;\n}\n\n// scalar * matrix, result is a matrix of the same type than the input matrix\ntemplate <typename T, typename U>\ntmat44<T> PURE operator *(U rv, const tmat44<T>& lv) {\n    tmat44<T> result(tmat44<T>::NO_INIT);\n    for (size_t r=0 ; r<tmat44<T>::row_size() ; r++)\n        result[r] = lv[r]*rv;\n    return result;\n}\n\n// ----------------------------------------------------------------------------------------\n\n/* FIXME: this should go into TMatSquareFunctions<> but for some reason\n * BASE<T>::col_type is not accessible from there (???)\n */\ntemplate<typename T>\ntypename tmat44<T>::col_type PURE diag(const tmat44<T>& m) {\n    return matrix::diag(m);\n}\n\n// ----------------------------------------------------------------------------------------\n\ntypedef tmat44<float> mat4;\n\n// ----------------------------------------------------------------------------------------\n}; // namespace android\n\n#undef PURE\n\n#endif /* UI_MAT4_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/vec2.h",
    "content": "/*\n * Copyright 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef UI_VEC2_H\n#define UI_VEC2_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#define TVEC_IMPLEMENTATION\n#include <ui/TVecHelpers.h>\n\nnamespace android {\n// -------------------------------------------------------------------------------------\n\ntemplate <typename T>\nclass tvec2 :   public TVecProductOperators<tvec2, T>,\n                public TVecAddOperators<tvec2, T>,\n                public TVecUnaryOperators<tvec2, T>,\n                public TVecComparisonOperators<tvec2, T>,\n                public TVecFunctions<tvec2, T>\n{\npublic:\n    enum no_init { NO_INIT };\n    typedef T value_type;\n    typedef T& reference;\n    typedef T const& const_reference;\n    typedef size_t size_type;\n\n    union {\n        struct { T x, y; };\n        struct { T s, t; };\n        struct { T r, g; };\n    };\n\n    enum { SIZE = 2 };\n    inline static size_type size() { return SIZE; }\n\n    // array access\n    inline T const& operator [] (size_t i) const { return (&x)[i]; }\n    inline T&       operator [] (size_t i)       { return (&x)[i]; }\n\n    // -----------------------------------------------------------------------\n    // we don't provide copy-ctor and operator= on purpose\n    // because we want the compiler generated versions\n\n    // constructors\n\n    // leaves object uninitialized. use with caution.\n    explicit tvec2(no_init) { }\n\n    // default constructor\n    tvec2() : x(0), y(0) { }\n\n    // handles implicit conversion to a tvec4. must not be explicit.\n    template<typename A>\n    tvec2(A v) : x(v), y(v) { }\n\n    template<typename A, typename B>\n    tvec2(A x, B y) : x(x), y(y) { }\n\n    template<typename A>\n    explicit tvec2(const tvec2<A>& v) : x(v.x), y(v.y) { }\n\n    template<typename A>\n    tvec2(const Impersonator< tvec2<A> >& v)\n        : x(((const tvec2<A>&)v).x),\n          y(((const tvec2<A>&)v).y) { }\n};\n\n// ----------------------------------------------------------------------------------------\n\ntypedef tvec2<float> vec2;\n\n// ----------------------------------------------------------------------------------------\n}; // namespace android\n\n#endif /* UI_VEC4_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/vec3.h",
    "content": "/*\n * Copyright 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef UI_VEC3_H\n#define UI_VEC3_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <ui/vec2.h>\n\nnamespace android {\n// -------------------------------------------------------------------------------------\n\ntemplate <typename T>\nclass tvec3 :   public TVecProductOperators<tvec3, T>,\n                public TVecAddOperators<tvec3, T>,\n                public TVecUnaryOperators<tvec3, T>,\n                public TVecComparisonOperators<tvec3, T>,\n                public TVecFunctions<tvec3, T>\n{\npublic:\n    enum no_init { NO_INIT };\n    typedef T value_type;\n    typedef T& reference;\n    typedef T const& const_reference;\n    typedef size_t size_type;\n\n    union {\n        struct { T x, y, z; };\n        struct { T s, t, p; };\n        struct { T r, g, b; };\n        Impersonator< tvec2<T> > xy;\n        Impersonator< tvec2<T> > st;\n        Impersonator< tvec2<T> > rg;\n    };\n\n    enum { SIZE = 3 };\n    inline static size_type size() { return SIZE; }\n\n    // array access\n    inline T const& operator [] (size_t i) const { return (&x)[i]; }\n    inline T&       operator [] (size_t i)       { return (&x)[i]; }\n\n    // -----------------------------------------------------------------------\n    // we don't provide copy-ctor and operator= on purpose\n    // because we want the compiler generated versions\n\n    // constructors\n    // leaves object uninitialized. use with caution.\n    explicit tvec3(no_init) { }\n\n    // default constructor\n    tvec3() : x(0), y(0), z(0) { }\n\n    // handles implicit conversion to a tvec4. must not be explicit.\n    template<typename A>\n    tvec3(A v) : x(v), y(v), z(v) { }\n\n    template<typename A, typename B, typename C>\n    tvec3(A x, B y, C z) : x(x), y(y), z(z) { }\n\n    template<typename A, typename B>\n    tvec3(const tvec2<A>& v, B z) : x(v.x), y(v.y), z(z) { }\n\n    template<typename A>\n    explicit tvec3(const tvec3<A>& v) : x(v.x), y(v.y), z(v.z) { }\n\n    template<typename A>\n    tvec3(const Impersonator< tvec3<A> >& v)\n        : x(((const tvec3<A>&)v).x),\n          y(((const tvec3<A>&)v).y),\n          z(((const tvec3<A>&)v).z) { }\n\n    template<typename A, typename B>\n    tvec3(const Impersonator< tvec2<A> >& v, B z)\n        : x(((const tvec2<A>&)v).x),\n          y(((const tvec2<A>&)v).y),\n          z(z) { }\n\n    // cross product works only on vectors of size 3\n    template <typename RT>\n    friend inline\n    tvec3 __attribute__((pure)) cross(const tvec3& u, const tvec3<RT>& v) {\n        return tvec3(\n                u.y*v.z - u.z*v.y,\n                u.z*v.x - u.x*v.z,\n                u.x*v.y - u.y*v.x);\n    }\n};\n\n\n// ----------------------------------------------------------------------------------------\n\ntypedef tvec3<float> vec3;\n\n// ----------------------------------------------------------------------------------------\n}; // namespace android\n\n#endif /* UI_VEC4_H */\n"
  },
  {
    "path": "phonelibs/android_frameworks_native/include/ui/vec4.h",
    "content": "/*\n * Copyright 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef UI_VEC4_H\n#define UI_VEC4_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <ui/vec3.h>\n\nnamespace android {\n// -------------------------------------------------------------------------------------\n\ntemplate <typename T>\nclass tvec4 :   public TVecProductOperators<tvec4, T>,\n                public TVecAddOperators<tvec4, T>,\n                public TVecUnaryOperators<tvec4, T>,\n                public TVecComparisonOperators<tvec4, T>,\n                public TVecFunctions<tvec4, T>\n{\npublic:\n    enum no_init { NO_INIT };\n    typedef T value_type;\n    typedef T& reference;\n    typedef T const& const_reference;\n    typedef size_t size_type;\n\n    union {\n        struct { T x, y, z, w; };\n        struct { T s, t, p, q; };\n        struct { T r, g, b, a; };\n        Impersonator< tvec2<T> > xy;\n        Impersonator< tvec2<T> > st;\n        Impersonator< tvec2<T> > rg;\n        Impersonator< tvec3<T> > xyz;\n        Impersonator< tvec3<T> > stp;\n        Impersonator< tvec3<T> > rgb;\n    };\n\n    enum { SIZE = 4 };\n    inline static size_type size() { return SIZE; }\n\n    // array access\n    inline T const& operator [] (size_t i) const { return (&x)[i]; }\n    inline T&       operator [] (size_t i)       { return (&x)[i]; }\n\n    // -----------------------------------------------------------------------\n    // we don't provide copy-ctor and operator= on purpose\n    // because we want the compiler generated versions\n\n    // constructors\n\n    // leaves object uninitialized. use with caution.\n    explicit tvec4(no_init) { }\n\n    // default constructor\n    tvec4() : x(0), y(0), z(0), w(0) { }\n\n    // handles implicit conversion to a tvec4. must not be explicit.\n    template<typename A>\n    tvec4(A v) : x(v), y(v), z(v), w(v) { }\n\n    template<typename A, typename B, typename C, typename D>\n    tvec4(A x, B y, C z, D w) : x(x), y(y), z(z), w(w) { }\n\n    template<typename A, typename B, typename C>\n    tvec4(const tvec2<A>& v, B z, C w) : x(v.x), y(v.y), z(z), w(w) { }\n\n    template<typename A, typename B>\n    tvec4(const tvec3<A>& v, B w) : x(v.x), y(v.y), z(v.z), w(w) { }\n\n    template<typename A>\n    explicit tvec4(const tvec4<A>& v) : x(v.x), y(v.y), z(v.z), w(v.w) { }\n\n    template<typename A>\n    tvec4(const Impersonator< tvec4<A> >& v)\n        : x(((const tvec4<A>&)v).x),\n          y(((const tvec4<A>&)v).y),\n          z(((const tvec4<A>&)v).z),\n          w(((const tvec4<A>&)v).w) { }\n\n    template<typename A, typename B>\n    tvec4(const Impersonator< tvec3<A> >& v, B w)\n        : x(((const tvec3<A>&)v).x),\n          y(((const tvec3<A>&)v).y),\n          z(((const tvec3<A>&)v).z),\n          w(w) { }\n\n    template<typename A, typename B, typename C>\n    tvec4(const Impersonator< tvec2<A> >& v, B z, C w)\n        : x(((const tvec2<A>&)v).x),\n          y(((const tvec2<A>&)v).y),\n          z(z),\n          w(w) { }\n};\n\n// ----------------------------------------------------------------------------------------\n\ntypedef tvec4<float> vec4;\n\n// ----------------------------------------------------------------------------------------\n}; // namespace android\n\n#endif /* UI_VEC4_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/activity_recognition.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n * Activity Recognition HAL. The goal is to provide low power, low latency, always-on activity\n * recognition implemented in hardware (i.e. these activity recognition algorithms/classifers\n * should NOT be run on the AP). By low power we mean that this may be activated 24/7 without\n * impacting the battery drain speed (goal in order of 1mW including the power for sensors).\n * This HAL does not specify the input sources that are used towards detecting these activities.\n * It has one monitor interface which can be used to batch activities for always-on\n * activity_recognition and if the latency is zero, the same interface can be used for low latency\n * detection.\n */\n\n#ifndef ANDROID_ACTIVITY_RECOGNITION_INTERFACE_H\n#define ANDROID_ACTIVITY_RECOGNITION_INTERFACE_H\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define ACTIVITY_RECOGNITION_HEADER_VERSION   1\n#define ACTIVITY_RECOGNITION_API_VERSION_0_1  HARDWARE_DEVICE_API_VERSION_2(0, 1, ACTIVITY_RECOGNITION_HEADER_VERSION)\n\n#define ACTIVITY_RECOGNITION_HARDWARE_MODULE_ID \"activity_recognition\"\n#define ACTIVITY_RECOGNITION_HARDWARE_INTERFACE \"activity_recognition_hw_if\"\n\n/*\n * Define types for various activities. Multiple activities may be active at the same time and\n * sometimes none of these activities may be active.\n *\n * Each activity has a corresponding type. Only activities that are defined here should use\n * android.activity_recognition.* prefix. OEM defined activities should not use this prefix.\n * Activity type of OEM-defined activities should start with the reverse domain name of the entity\n * defining the activity.\n *\n * When android introduces a new activity type that can potentially replace an OEM-defined activity\n * type, the OEM must use the official activity type on versions of the HAL that support this new\n * official activity type.\n *\n * Example (made up): Suppose Google's Glass team wants to detect nodding activity.\n *  - Such an activity is not officially supported in android L\n *  - Glass devices launching on L can implement a custom activity with\n *    type = \"com.google.glass.nodding\"\n *  - In M android release, if android decides to define ACITIVITY_TYPE_NODDING, those types\n *    should replace the Glass-team-specific types in all future launches.\n *  - When launching glass on the M release, Google should now use the official activity type\n *  - This way, other applications can use this activity.\n */\n\n#define ACTIVITY_TYPE_IN_VEHICLE       \"android.activity_recognition.in_vehicle\"\n\n#define ACTIVITY_TYPE_ON_BICYCLE       \"android.activity_recognition.on_bicycle\"\n\n#define ACTIVITY_TYPE_WALKING          \"android.activity_recognition.walking\"\n\n#define ACTIVITY_TYPE_RUNNING          \"android.activity_recognition.running\"\n\n#define ACTIVITY_TYPE_STILL            \"android.activity_recognition.still\"\n\n#define ACTIVITY_TYPE_TILTING          \"android.activity_recognition.tilting\"\n\n/* Values for activity_event.event_types. */\nenum {\n    /*\n     * A flush_complete event which indicates that a flush() has been successfully completed. This\n     * does not correspond to any activity/event. An event of this type should be added to the end\n     * of a batch FIFO and it indicates that all the events in the batch FIFO have been successfully\n     * reported to the framework. An event of this type should be generated only if flush() has been\n     * explicitly called and if the FIFO is empty at the time flush() is called it should trivially\n     * return a flush_complete_event to indicate that the FIFO is empty.\n     *\n     * A flush complete event should have the following parameters set.\n     * activity_event_t.event_type = ACTIVITY_EVENT_FLUSH_COMPLETE\n     * activity_event_t.activity = 0\n     * activity_event_t.timestamp = 0\n     * activity_event_t.reserved = 0\n     * See (*flush)() for more details.\n     */\n    ACTIVITY_EVENT_FLUSH_COMPLETE = 0,\n\n    /* Signifies entering an activity. */\n    ACTIVITY_EVENT_ENTER = 1,\n\n    /* Signifies exiting an activity. */\n    ACTIVITY_EVENT_EXIT  = 2\n};\n\n/*\n * Each event is a separate activity with event_type indicating whether this activity has started\n * or ended. Eg event: (event_type=\"enter\", activity=\"ON_FOOT\", timestamp)\n */\ntypedef struct activity_event {\n    /* One of the ACTIVITY_EVENT_* constants defined above. */\n    uint32_t event_type;\n\n    /*\n     * Index of the activity in the list returned by get_supported_activities_list. If this event\n     * is a flush complete event, this should be set to zero.\n     */\n    uint32_t activity;\n\n    /* Time at which the transition/event has occurred in nanoseconds using elapsedRealTimeNano. */\n    int64_t timestamp;\n\n    /* Set to zero. */\n    int32_t reserved[4];\n} activity_event_t;\n\ntypedef struct activity_recognition_module {\n    /**\n     * Common methods of the activity recognition module.  This *must* be the first member of\n     * activity_recognition_module as users of this structure will cast a hw_module_t to\n     * activity_recognition_module pointer in contexts where it's known the hw_module_t\n     * references an activity_recognition_module.\n     */\n    hw_module_t common;\n\n    /*\n     * List of all activities supported by this module including OEM defined activities. Each\n     * activity is represented using a string defined above. Each string should be null terminated.\n     * The index of the activity in this array is used as a \"handle\" for enabling/disabling and\n     * event delivery.\n     * Return value is the size of this list.\n     */\n    int (*get_supported_activities_list)(struct activity_recognition_module* module,\n            char const* const* *activity_list);\n} activity_recognition_module_t;\n\nstruct activity_recognition_device;\n\ntypedef struct activity_recognition_callback_procs {\n    // Callback for activity_data. This is guaranteed to not invoke any HAL methods.\n    // Memory allocated for the events can be reused after this method returns.\n    //    events - Array of activity_event_t s that are reported.\n    //    count  - size of the array.\n    void (*activity_callback)(const struct activity_recognition_callback_procs* procs,\n            const activity_event_t* events, int count);\n} activity_recognition_callback_procs_t;\n\ntypedef struct activity_recognition_device {\n    /**\n     * Common methods of the activity recognition device.  This *must* be the first member of\n     * activity_recognition_device as users of this structure will cast a hw_device_t to\n     * activity_recognition_device pointer in contexts where it's known the hw_device_t\n     * references an activity_recognition_device.\n     */\n    hw_device_t common;\n\n    /*\n     * Sets the callback to invoke when there are events to report. This call overwrites the\n     * previously registered callback (if any).\n     */\n    void (*register_activity_callback)(const struct activity_recognition_device* dev,\n            const activity_recognition_callback_procs_t* callback);\n\n    /*\n     * Activates monitoring of activity transitions. Activities need not be reported as soon as they\n     * are detected. The detected activities are stored in a FIFO and reported in batches when the\n     * \"max_batch_report_latency\" expires or when the batch FIFO is full. The implementation should\n     * allow the AP to go into suspend mode while the activities are detected and stored in the\n     * batch FIFO. Whenever events need to be reported (like when the FIFO is full or when the\n     * max_batch_report_latency has expired for an activity, event pair), it should wake_up the AP\n     * so that no events are lost. Activities are stored as transitions and they are allowed to\n     * overlap with each other. Each (activity, event_type) pair can be activated or deactivated\n     * independently of the other. The HAL implementation needs to keep track of which pairs are\n     * currently active and needs to detect only those pairs.\n     *\n     * activity_handle - Index of the specific activity that needs to be detected in the list\n     *                   returned by get_supported_activities_list.\n     * event_type - Specific transition of the activity that needs to be detected.\n     * max_batch_report_latency_ns - a transition can be delayed by at most\n     *                               “max_batch_report_latency” nanoseconds.\n     * Return 0 on success, negative errno code otherwise.\n     */\n    int (*enable_activity_event)(const struct activity_recognition_device* dev,\n            uint32_t activity_handle, uint32_t event_type, int64_t max_batch_report_latency_ns);\n\n    /*\n     * Disables detection of a specific (activity, event_type) pair.\n     */\n    int (*disable_activity_event)(const struct activity_recognition_device* dev,\n            uint32_t activity_handle, uint32_t event_type);\n\n    /*\n     * Flush all the batch FIFOs. Report all the activities that were stored in the FIFO so far as\n     * if max_batch_report_latency had expired. This shouldn't change the latency in any way. Add\n     * a flush_complete_event to indicate the end of the FIFO after all events are delivered.\n     * See ACTIVITY_EVENT_FLUSH_COMPLETE for more details.\n     * Return 0 on success, negative errno code otherwise.\n     */\n    int (*flush)(const struct activity_recognition_device* dev);\n\n    // Must be set to NULL.\n    void (*reserved_procs[16 - 4])(void);\n} activity_recognition_device_t;\n\nstatic inline int activity_recognition_open(const hw_module_t* module,\n        activity_recognition_device_t** device) {\n    return module->methods->open(module,\n            ACTIVITY_RECOGNITION_HARDWARE_INTERFACE, (hw_device_t**)device);\n}\n\nstatic inline int activity_recognition_close(activity_recognition_device_t* device) {\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif // ANDROID_ACTIVITY_RECOGNITION_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/audio.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_AUDIO_HAL_INTERFACE_H\n#define ANDROID_AUDIO_HAL_INTERFACE_H\n\n#include <stdint.h>\n#include <strings.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <cutils/bitops.h>\n\n#include <hardware/hardware.h>\n#include <system/audio.h>\n#include <hardware/audio_effect.h>\n#ifdef AUDIO_LISTEN_ENABLED\n#include <listen_types.h>\n#endif\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define AUDIO_HARDWARE_MODULE_ID \"audio\"\n\n/**\n * Name of the audio devices to open\n */\n#define AUDIO_HARDWARE_INTERFACE \"audio_hw_if\"\n\n\n/* Use version 0.1 to be compatible with first generation of audio hw module with version_major\n * hardcoded to 1. No audio module API change.\n */\n#define AUDIO_MODULE_API_VERSION_0_1 HARDWARE_MODULE_API_VERSION(0, 1)\n#define AUDIO_MODULE_API_VERSION_CURRENT AUDIO_MODULE_API_VERSION_0_1\n\n/* First generation of audio devices had version hardcoded to 0. all devices with versions < 1.0\n * will be considered of first generation API.\n */\n#define AUDIO_DEVICE_API_VERSION_0_0 HARDWARE_DEVICE_API_VERSION(0, 0)\n#define AUDIO_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n#define AUDIO_DEVICE_API_VERSION_2_0 HARDWARE_DEVICE_API_VERSION(2, 0)\n#define AUDIO_DEVICE_API_VERSION_3_0 HARDWARE_DEVICE_API_VERSION(3, 0)\n#define AUDIO_DEVICE_API_VERSION_CURRENT AUDIO_DEVICE_API_VERSION_3_0\n/* Minimal audio HAL version supported by the audio framework */\n#define AUDIO_DEVICE_API_VERSION_MIN AUDIO_DEVICE_API_VERSION_2_0\n\n/**\n * List of known audio HAL modules. This is the base name of the audio HAL\n * library composed of the \"audio.\" prefix, one of the base names below and\n * a suffix specific to the device.\n * e.g: audio.primary.goldfish.so or audio.a2dp.default.so\n */\n\n#define AUDIO_HARDWARE_MODULE_ID_PRIMARY \"primary\"\n#define AUDIO_HARDWARE_MODULE_ID_A2DP \"a2dp\"\n#define AUDIO_HARDWARE_MODULE_ID_USB \"usb\"\n#define AUDIO_HARDWARE_MODULE_ID_REMOTE_SUBMIX \"r_submix\"\n#define AUDIO_HARDWARE_MODULE_ID_CODEC_OFFLOAD \"codec_offload\"\n\n/**************************************/\n\n/**\n *  standard audio parameters that the HAL may need to handle\n */\n\n/**\n *  audio device parameters\n */\n\n/* BT SCO Noise Reduction + Echo Cancellation parameters */\n#define AUDIO_PARAMETER_KEY_BT_NREC \"bt_headset_nrec\"\n#define AUDIO_PARAMETER_VALUE_ON \"on\"\n#define AUDIO_PARAMETER_VALUE_OFF \"off\"\n\n/* TTY mode selection */\n#define AUDIO_PARAMETER_KEY_TTY_MODE \"tty_mode\"\n#define AUDIO_PARAMETER_VALUE_TTY_OFF \"tty_off\"\n#define AUDIO_PARAMETER_VALUE_TTY_VCO \"tty_vco\"\n#define AUDIO_PARAMETER_VALUE_TTY_HCO \"tty_hco\"\n#define AUDIO_PARAMETER_VALUE_TTY_FULL \"tty_full\"\n\n/* Hearing Aid Compatibility - Telecoil (HAC-T) mode on/off\n   Strings must be in sync with CallFeaturesSetting.java */\n#define AUDIO_PARAMETER_KEY_HAC \"HACSetting\"\n#define AUDIO_PARAMETER_VALUE_HAC_ON \"ON\"\n#define AUDIO_PARAMETER_VALUE_HAC_OFF \"OFF\"\n\n/* A2DP sink address set by framework */\n#define AUDIO_PARAMETER_A2DP_SINK_ADDRESS \"a2dp_sink_address\"\n\n/* A2DP source address set by framework */\n#define AUDIO_PARAMETER_A2DP_SOURCE_ADDRESS \"a2dp_source_address\"\n\n/* Screen state */\n#define AUDIO_PARAMETER_KEY_SCREEN_STATE \"screen_state\"\n\n/* Bluetooth SCO wideband */\n#define AUDIO_PARAMETER_KEY_BT_SCO_WB \"bt_wbs\"\n\n/* Get a new HW synchronization source identifier.\n * Return a valid source (positive integer) or AUDIO_HW_SYNC_INVALID if an error occurs\n * or no HW sync is available. */\n#define AUDIO_PARAMETER_HW_AV_SYNC \"hw_av_sync\"\n\n/* Device state*/\n#define AUDIO_PARAMETER_KEY_DEV_SHUTDOWN \"dev_shutdown\"\n\n/**\n *  audio stream parameters\n */\n\n#define AUDIO_PARAMETER_STREAM_ROUTING \"routing\"             /* audio_devices_t */\n#define AUDIO_PARAMETER_STREAM_FORMAT \"format\"               /* audio_format_t */\n#define AUDIO_PARAMETER_STREAM_CHANNELS \"channels\"           /* audio_channel_mask_t */\n#define AUDIO_PARAMETER_STREAM_FRAME_COUNT \"frame_count\"     /* size_t */\n#define AUDIO_PARAMETER_STREAM_INPUT_SOURCE \"input_source\"   /* audio_source_t */\n#define AUDIO_PARAMETER_STREAM_SAMPLING_RATE \"sampling_rate\" /* uint32_t */\n\n#define AUDIO_PARAMETER_DEVICE_CONNECT \"connect\"            /* audio_devices_t */\n#define AUDIO_PARAMETER_DEVICE_DISCONNECT \"disconnect\"      /* audio_devices_t */\n\n/* Query supported formats. The response is a '|' separated list of strings from\n * audio_format_t enum e.g: \"sup_formats=AUDIO_FORMAT_PCM_16_BIT\" */\n#define AUDIO_PARAMETER_STREAM_SUP_FORMATS \"sup_formats\"\n/* Query supported channel masks. The response is a '|' separated list of strings from\n * audio_channel_mask_t enum e.g: \"sup_channels=AUDIO_CHANNEL_OUT_STEREO|AUDIO_CHANNEL_OUT_MONO\" */\n#define AUDIO_PARAMETER_STREAM_SUP_CHANNELS \"sup_channels\"\n/* Query supported sampling rates. The response is a '|' separated list of integer values e.g:\n * \"sup_sampling_rates=44100|48000\" */\n#define AUDIO_PARAMETER_STREAM_SUP_SAMPLING_RATES \"sup_sampling_rates\"\n\n/* Set the HW synchronization source for an output stream. */\n#define AUDIO_PARAMETER_STREAM_HW_AV_SYNC \"hw_av_sync\"\n\n/**\n * audio codec parameters\n */\n\n#define AUDIO_OFFLOAD_CODEC_PARAMS \"music_offload_codec_param\"\n#define AUDIO_OFFLOAD_CODEC_BIT_PER_SAMPLE \"music_offload_bit_per_sample\"\n#define AUDIO_OFFLOAD_CODEC_BIT_RATE \"music_offload_bit_rate\"\n#define AUDIO_OFFLOAD_CODEC_AVG_BIT_RATE \"music_offload_avg_bit_rate\"\n#define AUDIO_OFFLOAD_CODEC_ID \"music_offload_codec_id\"\n#define AUDIO_OFFLOAD_CODEC_BLOCK_ALIGN \"music_offload_block_align\"\n#define AUDIO_OFFLOAD_CODEC_SAMPLE_RATE \"music_offload_sample_rate\"\n#define AUDIO_OFFLOAD_CODEC_ENCODE_OPTION \"music_offload_encode_option\"\n#define AUDIO_OFFLOAD_CODEC_NUM_CHANNEL  \"music_offload_num_channels\"\n#define AUDIO_OFFLOAD_CODEC_DOWN_SAMPLING  \"music_offload_down_sampling\"\n#define AUDIO_OFFLOAD_CODEC_DELAY_SAMPLES  \"delay_samples\"\n#define AUDIO_OFFLOAD_CODEC_PADDING_SAMPLES  \"padding_samples\"\n\n/**************************************/\n\n/* common audio stream parameters and operations */\nstruct audio_stream {\n\n    /**\n     * Return the sampling rate in Hz - eg. 44100.\n     */\n    uint32_t (*get_sample_rate)(const struct audio_stream *stream);\n\n    /* currently unused - use set_parameters with key\n     *    AUDIO_PARAMETER_STREAM_SAMPLING_RATE\n     */\n    int (*set_sample_rate)(struct audio_stream *stream, uint32_t rate);\n\n    /**\n     * Return size of input/output buffer in bytes for this stream - eg. 4800.\n     * It should be a multiple of the frame size.  See also get_input_buffer_size.\n     */\n    size_t (*get_buffer_size)(const struct audio_stream *stream);\n\n    /**\n     * Return the channel mask -\n     *  e.g. AUDIO_CHANNEL_OUT_STEREO or AUDIO_CHANNEL_IN_STEREO\n     */\n    audio_channel_mask_t (*get_channels)(const struct audio_stream *stream);\n\n    /**\n     * Return the audio format - e.g. AUDIO_FORMAT_PCM_16_BIT\n     */\n    audio_format_t (*get_format)(const struct audio_stream *stream);\n\n    /* currently unused - use set_parameters with key\n     *     AUDIO_PARAMETER_STREAM_FORMAT\n     */\n    int (*set_format)(struct audio_stream *stream, audio_format_t format);\n\n    /**\n     * Put the audio hardware input/output into standby mode.\n     * Driver should exit from standby mode at the next I/O operation.\n     * Returns 0 on success and <0 on failure.\n     */\n    int (*standby)(struct audio_stream *stream);\n\n    /** dump the state of the audio input/output device */\n    int (*dump)(const struct audio_stream *stream, int fd);\n\n    /** Return the set of device(s) which this stream is connected to */\n    audio_devices_t (*get_device)(const struct audio_stream *stream);\n\n    /**\n     * Currently unused - set_device() corresponds to set_parameters() with key\n     * AUDIO_PARAMETER_STREAM_ROUTING for both input and output.\n     * AUDIO_PARAMETER_STREAM_INPUT_SOURCE is an additional information used by\n     * input streams only.\n     */\n    int (*set_device)(struct audio_stream *stream, audio_devices_t device);\n\n    /**\n     * set/get audio stream parameters. The function accepts a list of\n     * parameter key value pairs in the form: key1=value1;key2=value2;...\n     *\n     * Some keys are reserved for standard parameters (See AudioParameter class)\n     *\n     * If the implementation does not accept a parameter change while\n     * the output is active but the parameter is acceptable otherwise, it must\n     * return -ENOSYS.\n     *\n     * The audio flinger will put the stream in standby and then change the\n     * parameter value.\n     */\n    int (*set_parameters)(struct audio_stream *stream, const char *kv_pairs);\n\n    /*\n     * Returns a pointer to a heap allocated string. The caller is responsible\n     * for freeing the memory for it using free().\n     */\n    char * (*get_parameters)(const struct audio_stream *stream,\n                             const char *keys);\n    int (*add_audio_effect)(const struct audio_stream *stream,\n                             effect_handle_t effect);\n    int (*remove_audio_effect)(const struct audio_stream *stream,\n                             effect_handle_t effect);\n};\ntypedef struct audio_stream audio_stream_t;\n\n/* type of asynchronous write callback events. Mutually exclusive */\ntypedef enum {\n    STREAM_CBK_EVENT_WRITE_READY, /* non blocking write completed */\n    STREAM_CBK_EVENT_DRAIN_READY  /* drain completed */\n} stream_callback_event_t;\n\ntypedef int (*stream_callback_t)(stream_callback_event_t event, void *param, void *cookie);\n\n/* type of drain requested to audio_stream_out->drain(). Mutually exclusive */\ntypedef enum {\n    AUDIO_DRAIN_ALL,            /* drain() returns when all data has been played */\n    AUDIO_DRAIN_EARLY_NOTIFY    /* drain() returns a short time before all data\n                                   from the current track has been played to\n                                   give time for gapless track switch */\n} audio_drain_type_t;\n\n/**\n * audio_stream_out is the abstraction interface for the audio output hardware.\n *\n * It provides information about various properties of the audio output\n * hardware driver.\n */\n\nstruct audio_stream_out {\n    /**\n     * Common methods of the audio stream out.  This *must* be the first member of audio_stream_out\n     * as users of this structure will cast a audio_stream to audio_stream_out pointer in contexts\n     * where it's known the audio_stream references an audio_stream_out.\n     */\n    struct audio_stream common;\n\n    /**\n     * Return the audio hardware driver estimated latency in milliseconds.\n     */\n    uint32_t (*get_latency)(const struct audio_stream_out *stream);\n\n    /**\n     * Use this method in situations where audio mixing is done in the\n     * hardware. This method serves as a direct interface with hardware,\n     * allowing you to directly set the volume as apposed to via the framework.\n     * This method might produce multiple PCM outputs or hardware accelerated\n     * codecs, such as MP3 or AAC.\n     */\n    int (*set_volume)(struct audio_stream_out *stream, float left, float right);\n\n    /**\n     * Write audio buffer to driver. Returns number of bytes written, or a\n     * negative status_t. If at least one frame was written successfully prior to the error,\n     * it is suggested that the driver return that successful (short) byte count\n     * and then return an error in the subsequent call.\n     *\n     * If set_callback() has previously been called to enable non-blocking mode\n     * the write() is not allowed to block. It must write only the number of\n     * bytes that currently fit in the driver/hardware buffer and then return\n     * this byte count. If this is less than the requested write size the\n     * callback function must be called when more space is available in the\n     * driver/hardware buffer.\n     */\n    ssize_t (*write)(struct audio_stream_out *stream, const void* buffer,\n                     size_t bytes);\n\n    /* return the number of audio frames written by the audio dsp to DAC since\n     * the output has exited standby\n     */\n    int (*get_render_position)(const struct audio_stream_out *stream,\n                               uint32_t *dsp_frames);\n\n    /**\n     * get the local time at which the next write to the audio driver will be presented.\n     * The units are microseconds, where the epoch is decided by the local audio HAL.\n     */\n    int (*get_next_write_timestamp)(const struct audio_stream_out *stream,\n                                    int64_t *timestamp);\n\n    /**\n     * set the callback function for notifying completion of non-blocking\n     * write and drain.\n     * Calling this function implies that all future write() and drain()\n     * must be non-blocking and use the callback to signal completion.\n     */\n    int (*set_callback)(struct audio_stream_out *stream,\n            stream_callback_t callback, void *cookie);\n\n    /**\n     * Notifies to the audio driver to stop playback however the queued buffers are\n     * retained by the hardware. Useful for implementing pause/resume. Empty implementation\n     * if not supported however should be implemented for hardware with non-trivial\n     * latency. In the pause state audio hardware could still be using power. User may\n     * consider calling suspend after a timeout.\n     *\n     * Implementation of this function is mandatory for offloaded playback.\n     */\n    int (*pause)(struct audio_stream_out* stream);\n\n    /**\n     * Notifies to the audio driver to resume playback following a pause.\n     * Returns error if called without matching pause.\n     *\n     * Implementation of this function is mandatory for offloaded playback.\n     */\n    int (*resume)(struct audio_stream_out* stream);\n\n    /**\n     * Requests notification when data buffered by the driver/hardware has\n     * been played. If set_callback() has previously been called to enable\n     * non-blocking mode, the drain() must not block, instead it should return\n     * quickly and completion of the drain is notified through the callback.\n     * If set_callback() has not been called, the drain() must block until\n     * completion.\n     * If type==AUDIO_DRAIN_ALL, the drain completes when all previously written\n     * data has been played.\n     * If type==AUDIO_DRAIN_EARLY_NOTIFY, the drain completes shortly before all\n     * data for the current track has played to allow time for the framework\n     * to perform a gapless track switch.\n     *\n     * Drain must return immediately on stop() and flush() call\n     *\n     * Implementation of this function is mandatory for offloaded playback.\n     */\n    int (*drain)(struct audio_stream_out* stream, audio_drain_type_t type );\n\n    /**\n     * Notifies to the audio driver to flush the queued data. Stream must already\n     * be paused before calling flush().\n     *\n     * Implementation of this function is mandatory for offloaded playback.\n     */\n   int (*flush)(struct audio_stream_out* stream);\n\n    /**\n     * Return a recent count of the number of audio frames presented to an external observer.\n     * This excludes frames which have been written but are still in the pipeline.\n     * The count is not reset to zero when output enters standby.\n     * Also returns the value of CLOCK_MONOTONIC as of this presentation count.\n     * The returned count is expected to be 'recent',\n     * but does not need to be the most recent possible value.\n     * However, the associated time should correspond to whatever count is returned.\n     * Example:  assume that N+M frames have been presented, where M is a 'small' number.\n     * Then it is permissible to return N instead of N+M,\n     * and the timestamp should correspond to N rather than N+M.\n     * The terms 'recent' and 'small' are not defined.\n     * They reflect the quality of the implementation.\n     *\n     * 3.0 and higher only.\n     */\n    int (*get_presentation_position)(const struct audio_stream_out *stream,\n                               uint64_t *frames, struct timespec *timestamp);\n\n};\ntypedef struct audio_stream_out audio_stream_out_t;\n\nstruct audio_stream_in {\n    /**\n     * Common methods of the audio stream in.  This *must* be the first member of audio_stream_in\n     * as users of this structure will cast a audio_stream to audio_stream_in pointer in contexts\n     * where it's known the audio_stream references an audio_stream_in.\n     */\n    struct audio_stream common;\n\n    /** set the input gain for the audio driver. This method is for\n     *  for future use */\n    int (*set_gain)(struct audio_stream_in *stream, float gain);\n\n    /** Read audio buffer in from audio driver. Returns number of bytes read, or a\n     *  negative status_t. If at least one frame was read prior to the error,\n     *  read should return that byte count and then return an error in the subsequent call.\n     */\n    ssize_t (*read)(struct audio_stream_in *stream, void* buffer,\n                    size_t bytes);\n\n    /**\n     * Return the amount of input frames lost in the audio driver since the\n     * last call of this function.\n     * Audio driver is expected to reset the value to 0 and restart counting\n     * upon returning the current value by this function call.\n     * Such loss typically occurs when the user space process is blocked\n     * longer than the capacity of audio driver buffers.\n     *\n     * Unit: the number of input audio frames\n     */\n    uint32_t (*get_input_frames_lost)(struct audio_stream_in *stream);\n};\ntypedef struct audio_stream_in audio_stream_in_t;\n\n/**\n * return the frame size (number of bytes per sample).\n *\n * Deprecated: use audio_stream_out_frame_size() or audio_stream_in_frame_size() instead.\n */\n__attribute__((__deprecated__))\nstatic inline size_t audio_stream_frame_size(const struct audio_stream *s)\n{\n    size_t chan_samp_sz;\n    audio_format_t format = s->get_format(s);\n\n    if (audio_is_linear_pcm(format)) {\n        chan_samp_sz = audio_bytes_per_sample(format);\n        return popcount(s->get_channels(s)) * chan_samp_sz;\n    }\n\n    return sizeof(int8_t);\n}\n\n/**\n * return the frame size (number of bytes per sample) of an output stream.\n */\nstatic inline size_t audio_stream_out_frame_size(const struct audio_stream_out *s)\n{\n    size_t chan_samp_sz;\n    audio_format_t format = s->common.get_format(&s->common);\n\n    if (audio_is_linear_pcm(format)) {\n        chan_samp_sz = audio_bytes_per_sample(format);\n        return audio_channel_count_from_out_mask(s->common.get_channels(&s->common)) * chan_samp_sz;\n    }\n\n    return sizeof(int8_t);\n}\n\n/**\n * return the frame size (number of bytes per sample) of an input stream.\n */\nstatic inline size_t audio_stream_in_frame_size(const struct audio_stream_in *s)\n{\n    size_t chan_samp_sz;\n    audio_format_t format = s->common.get_format(&s->common);\n\n    if (audio_is_linear_pcm(format)) {\n        chan_samp_sz = audio_bytes_per_sample(format);\n        return audio_channel_count_from_in_mask(s->common.get_channels(&s->common)) * chan_samp_sz;\n    }\n\n    return sizeof(int8_t);\n}\n\n/**********************************************************************/\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\nstruct audio_module {\n    struct hw_module_t common;\n};\n\nstruct audio_hw_device {\n    /**\n     * Common methods of the audio device.  This *must* be the first member of audio_hw_device\n     * as users of this structure will cast a hw_device_t to audio_hw_device pointer in contexts\n     * where it's known the hw_device_t references an audio_hw_device.\n     */\n    struct hw_device_t common;\n\n    /**\n     * used by audio flinger to enumerate what devices are supported by\n     * each audio_hw_device implementation.\n     *\n     * Return value is a bitmask of 1 or more values of audio_devices_t\n     *\n     * NOTE: audio HAL implementations starting with\n     * AUDIO_DEVICE_API_VERSION_2_0 do not implement this function.\n     * All supported devices should be listed in audio_policy.conf\n     * file and the audio policy manager must choose the appropriate\n     * audio module based on information in this file.\n     */\n    uint32_t (*get_supported_devices)(const struct audio_hw_device *dev);\n\n    /**\n     * check to see if the audio hardware interface has been initialized.\n     * returns 0 on success, -ENODEV on failure.\n     */\n    int (*init_check)(const struct audio_hw_device *dev);\n\n    /** set the audio volume of a voice call. Range is between 0.0 and 1.0 */\n    int (*set_voice_volume)(struct audio_hw_device *dev, float volume);\n\n    /**\n     * set the audio volume for all audio activities other than voice call.\n     * Range between 0.0 and 1.0. If any value other than 0 is returned,\n     * the software mixer will emulate this capability.\n     */\n    int (*set_master_volume)(struct audio_hw_device *dev, float volume);\n\n    /**\n     * Get the current master volume value for the HAL, if the HAL supports\n     * master volume control.  AudioFlinger will query this value from the\n     * primary audio HAL when the service starts and use the value for setting\n     * the initial master volume across all HALs.  HALs which do not support\n     * this method may leave it set to NULL.\n     */\n    int (*get_master_volume)(struct audio_hw_device *dev, float *volume);\n\n    /**\n     * set_mode is called when the audio mode changes. AUDIO_MODE_NORMAL mode\n     * is for standard audio playback, AUDIO_MODE_RINGTONE when a ringtone is\n     * playing, and AUDIO_MODE_IN_CALL when a call is in progress.\n     */\n    int (*set_mode)(struct audio_hw_device *dev, audio_mode_t mode);\n\n    /* mic mute */\n    int (*set_mic_mute)(struct audio_hw_device *dev, bool state);\n    int (*get_mic_mute)(const struct audio_hw_device *dev, bool *state);\n\n    /* set/get global audio parameters */\n    int (*set_parameters)(struct audio_hw_device *dev, const char *kv_pairs);\n\n    /*\n     * Returns a pointer to a heap allocated string. The caller is responsible\n     * for freeing the memory for it using free().\n     */\n    char * (*get_parameters)(const struct audio_hw_device *dev,\n                             const char *keys);\n\n    /* Returns audio input buffer size according to parameters passed or\n     * 0 if one of the parameters is not supported.\n     * See also get_buffer_size which is for a particular stream.\n     */\n    size_t (*get_input_buffer_size)(const struct audio_hw_device *dev,\n                                    const struct audio_config *config);\n\n    /** This method creates and opens the audio hardware output stream.\n     * The \"address\" parameter qualifies the \"devices\" audio device type if needed.\n     * The format format depends on the device type:\n     * - Bluetooth devices use the MAC address of the device in the form \"00:11:22:AA:BB:CC\"\n     * - USB devices use the ALSA card and device numbers in the form  \"card=X;device=Y\"\n     * - Other devices may use a number or any other string.\n     */\n\n    int (*open_output_stream)(struct audio_hw_device *dev,\n                              audio_io_handle_t handle,\n                              audio_devices_t devices,\n                              audio_output_flags_t flags,\n                              struct audio_config *config,\n                              struct audio_stream_out **stream_out,\n                              const char *address);\n\n    void (*close_output_stream)(struct audio_hw_device *dev,\n                                struct audio_stream_out* stream_out);\n\n    /** This method creates and opens the audio hardware input stream */\n    int (*open_input_stream)(struct audio_hw_device *dev,\n                             audio_io_handle_t handle,\n                             audio_devices_t devices,\n                             struct audio_config *config,\n                             struct audio_stream_in **stream_in,\n                             audio_input_flags_t flags,\n                             const char *address,\n                             audio_source_t source);\n\n    void (*close_input_stream)(struct audio_hw_device *dev,\n                               struct audio_stream_in *stream_in);\n\n    /** This method dumps the state of the audio hardware */\n    int (*dump)(const struct audio_hw_device *dev, int fd);\n\n    /**\n     * set the audio mute status for all audio activities.  If any value other\n     * than 0 is returned, the software mixer will emulate this capability.\n     */\n    int (*set_master_mute)(struct audio_hw_device *dev, bool mute);\n\n    /**\n     * Get the current master mute status for the HAL, if the HAL supports\n     * master mute control.  AudioFlinger will query this value from the primary\n     * audio HAL when the service starts and use the value for setting the\n     * initial master mute across all HALs.  HALs which do not support this\n     * method may leave it set to NULL.\n     */\n    int (*get_master_mute)(struct audio_hw_device *dev, bool *mute);\n\n    /**\n     * Routing control\n     */\n\n    /* Creates an audio patch between several source and sink ports.\n     * The handle is allocated by the HAL and should be unique for this\n     * audio HAL module. */\n    int (*create_audio_patch)(struct audio_hw_device *dev,\n                               unsigned int num_sources,\n                               const struct audio_port_config *sources,\n                               unsigned int num_sinks,\n                               const struct audio_port_config *sinks,\n                               audio_patch_handle_t *handle);\n\n    /* Release an audio patch */\n    int (*release_audio_patch)(struct audio_hw_device *dev,\n                               audio_patch_handle_t handle);\n\n    /* Fills the list of supported attributes for a given audio port.\n     * As input, \"port\" contains the information (type, role, address etc...)\n     * needed by the HAL to identify the port.\n     * As output, \"port\" contains possible attributes (sampling rates, formats,\n     * channel masks, gain controllers...) for this port.\n     */\n    int (*get_audio_port)(struct audio_hw_device *dev,\n                          struct audio_port *port);\n\n    /* Set audio port configuration */\n    int (*set_audio_port_config)(struct audio_hw_device *dev,\n                         const struct audio_port_config *config);\n\n#ifdef AUDIO_LISTEN_ENABLED\n    /** This method creates the listen session and returns handle */\n    int (*open_listen_session)(struct audio_hw_device *dev,\n                              listen_open_params_t *params,\n                              struct listen_session** handle);\n\n    /** This method closes the listen session  */\n    int (*close_listen_session)(struct audio_hw_device *dev,\n                                struct listen_session* handle);\n\n    /** This method sets the mad observer callback  */\n    int (*set_mad_observer)(struct audio_hw_device *dev,\n                            listen_callback_t cb_func);\n\n    /**\n     *   This method is used for setting listen hal specfic parameters.\n     *  If multiple paramets are set in one call and setting any one of them\n     *  fails it will return failure.\n     */\n    int (*listen_set_parameters)(struct audio_hw_device *dev,\n                                 const char *kv_pairs);\n#endif\n};\ntypedef struct audio_hw_device audio_hw_device_t;\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int audio_hw_device_open(const struct hw_module_t* module,\n                                       struct audio_hw_device** device)\n{\n    return module->methods->open(module, AUDIO_HARDWARE_INTERFACE,\n                                 (struct hw_device_t**)device);\n}\n\nstatic inline int audio_hw_device_close(struct audio_hw_device* device)\n{\n    return device->common.close(&device->common);\n}\n\n\n__END_DECLS\n\n#endif  // ANDROID_AUDIO_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/audio_alsaops.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* This file contains shared utility functions to handle the tinyalsa\n * implementation for Android internal audio, generally in the hardware layer.\n * Some routines may log a fatal error on failure, as noted.\n */\n\n#ifndef ANDROID_AUDIO_ALSAOPS_H\n#define ANDROID_AUDIO_ALSAOPS_H\n\n#include <cutils/log.h>\n#include <system/audio.h>\n#include <tinyalsa/asoundlib.h>\n\n__BEGIN_DECLS\n\n/* Converts audio_format to pcm_format.\n * Parameters:\n *  format  the audio_format_t to convert\n *\n * Logs a fatal error if format is not a valid convertible audio_format_t.\n */\nstatic inline enum pcm_format pcm_format_from_audio_format(audio_format_t format)\n{\n    switch (format) {\n#ifdef HAVE_BIG_ENDIAN\n    case AUDIO_FORMAT_PCM_16_BIT:\n        return PCM_FORMAT_S16_BE;\n    case AUDIO_FORMAT_PCM_24_BIT_PACKED:\n        return PCM_FORMAT_S24_3BE;\n    case AUDIO_FORMAT_PCM_32_BIT:\n        return PCM_FORMAT_S32_BE;\n    case AUDIO_FORMAT_PCM_8_24_BIT:\n        return PCM_FORMAT_S24_BE;\n#else\n    case AUDIO_FORMAT_PCM_16_BIT:\n        return PCM_FORMAT_S16_LE;\n    case AUDIO_FORMAT_PCM_24_BIT_PACKED:\n        return PCM_FORMAT_S24_3LE;\n    case AUDIO_FORMAT_PCM_32_BIT:\n        return PCM_FORMAT_S32_LE;\n    case AUDIO_FORMAT_PCM_8_24_BIT:\n        return PCM_FORMAT_S24_LE;\n#endif\n    case AUDIO_FORMAT_PCM_FLOAT:  /* there is no equivalent for float */\n    default:\n        LOG_ALWAYS_FATAL(\"pcm_format_from_audio_format: invalid audio format %#x\", format);\n        return 0;\n    }\n}\n\n/* Converts pcm_format to audio_format.\n * Parameters:\n *  format  the pcm_format to convert\n *\n * Logs a fatal error if format is not a valid convertible pcm_format.\n */\nstatic inline audio_format_t audio_format_from_pcm_format(enum pcm_format format)\n{\n    switch (format) {\n#ifdef HAVE_BIG_ENDIAN\n    case PCM_FORMAT_S16_BE:\n        return AUDIO_FORMAT_PCM_16_BIT;\n    case PCM_FORMAT_S24_3BE:\n        return AUDIO_FORMAT_PCM_24_BIT_PACKED;\n    case PCM_FORMAT_S24_BE:\n        return AUDIO_FORMAT_PCM_8_24_BIT;\n    case PCM_FORMAT_S32_BE:\n        return AUDIO_FORMAT_PCM_32_BIT;\n#else\n    case PCM_FORMAT_S16_LE:\n        return AUDIO_FORMAT_PCM_16_BIT;\n    case PCM_FORMAT_S24_3LE:\n        return AUDIO_FORMAT_PCM_24_BIT_PACKED;\n    case PCM_FORMAT_S24_LE:\n        return AUDIO_FORMAT_PCM_8_24_BIT;\n    case PCM_FORMAT_S32_LE:\n        return AUDIO_FORMAT_PCM_32_BIT;\n#endif\n    default:\n        LOG_ALWAYS_FATAL(\"audio_format_from_pcm_format: invalid pcm format %#x\", format);\n        return 0;\n    }\n}\n\n__END_DECLS\n\n#endif /* ANDROID_AUDIO_ALSAOPS_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/audio_amplifier.h",
    "content": "/*\n * Copyright (C) 2015, The CyanogenMod Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef CM_AUDIO_AMPLIFIER_INTERFACE_H\n#define CM_AUDIO_AMPLIFIER_INTERFACE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/audio.h>\n#include <hardware/hardware.h>\n\n#include <system/audio.h>\n\n__BEGIN_DECLS\n\n#define AMPLIFIER_HARDWARE_MODULE_ID \"audio_amplifier\"\n\n#define AMPLIFIER_HARDWARE_INTERFACE \"audio_amplifier_hw_if\"\n\n#define AMPLIFIER_MODULE_API_VERSION_0_1 HARDWARE_MODULE_API_VERSION(0, 1)\n\n#define AMPLIFIER_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n#define AMPLIFIER_DEVICE_API_VERSION_2_0 HARDWARE_DEVICE_API_VERSION(2, 0)\n#define AMPLIFIER_DEVICE_API_VERSION_CURRENT AMPLIFIER_DEVICE_API_VERSION_2_0\n\nstruct str_parms;\n\ntypedef struct amplifier_device {\n    /**\n     * Common methods of the amplifier device. This *must* be the first member\n     * of amplifier_device as users of this structure will cast a hw_device_t\n     * to amplifier_device pointer in contexts where it's known\n     * the hw_device_t references a amplifier_device.\n     */\n    struct hw_device_t common;\n\n    /**\n     * Notify amplifier device of current input devices\n     *\n     * This function should handle only input devices.\n     */\n    int (*set_input_devices)(struct amplifier_device *device, uint32_t devices);\n\n    /**\n     * Notify amplifier device of current output devices\n     *\n     * This function should handle only output devices.\n     */\n    int (*set_output_devices)(struct amplifier_device *device, uint32_t devices);\n\n    /**\n     * Notify amplifier device of output device enable/disable\n     *\n     * This function should handle only output devices.\n     */\n    int (*enable_output_devices)(struct amplifier_device *device,\n            uint32_t devices, bool enable);\n\n    /**\n     * Notify amplifier device of input device enable/disable\n     *\n     * This function should handle only input devices.\n     */\n    int (*enable_input_devices)(struct amplifier_device *device,\n            uint32_t devices, bool enable);\n\n    /**\n     * Notify amplifier device about current audio mode\n     */\n    int (*set_mode)(struct amplifier_device *device, audio_mode_t mode);\n\n    /**\n     * Notify amplifier device that an output stream has started\n     */\n    int (*output_stream_start)(struct amplifier_device *device,\n            struct audio_stream_out *stream, bool offload);\n\n    /**\n     * Notify amplifier device that an input stream has started\n     */\n    int (*input_stream_start)(struct amplifier_device *device,\n            struct audio_stream_in *stream);\n\n    /**\n     * Notify amplifier device that an output stream has stopped\n     */\n    int (*output_stream_standby)(struct amplifier_device *device,\n            struct audio_stream_out *stream);\n\n    /**\n     * Notify amplifier device that an input stream has stopped\n     */\n    int (*input_stream_standby)(struct amplifier_device *device,\n            struct audio_stream_in *stream);\n\n    /**\n     * set/get output audio device parameters.\n     */\n    int (*set_parameters)(struct amplifier_device *device,\n        struct str_parms *parms);\n} amplifier_device_t;\n\ntypedef struct amplifier_module {\n    /**\n     * Common methods of the amplifier module. This *must* be the first member\n     * of amplifier_module as users of this structure will cast a hw_module_t\n     * to amplifier_module pointer in contexts where it's known\n     * the hw_module_t references a amplifier_module.\n     */\n    struct hw_module_t common;\n} amplifier_module_t;\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int amplifier_device_open(const struct hw_module_t *module,\n        struct amplifier_device **device)\n{\n    return module->methods->open(module, AMPLIFIER_HARDWARE_INTERFACE,\n            (struct hw_device_t **) device);\n}\n\nstatic inline int amplifier_device_close(struct amplifier_device *device)\n{\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif  // CM_AUDIO_AMPLIFIER_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/audio_effect.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_AUDIO_EFFECT_H\n#define ANDROID_AUDIO_EFFECT_H\n\n#include <errno.h>\n#include <stdint.h>\n#include <strings.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <cutils/bitops.h>\n\n#include <system/audio.h>\n\n\n__BEGIN_DECLS\n\n\n/////////////////////////////////////////////////\n//      Common Definitions\n/////////////////////////////////////////////////\n\n//\n//--- Effect descriptor structure effect_descriptor_t\n//\n\n// Unique effect ID (can be generated from the following site:\n//  http://www.itu.int/ITU-T/asn1/uuid.html)\n// This format is used for both \"type\" and \"uuid\" fields of the effect descriptor structure.\n// - When used for effect type and the engine is implementing and effect corresponding to a standard\n// OpenSL ES interface, this ID must be the one defined in OpenSLES_IID.h for that interface.\n// - When used as uuid, it should be a unique UUID for this particular implementation.\ntypedef struct effect_uuid_s {\n    uint32_t timeLow;\n    uint16_t timeMid;\n    uint16_t timeHiAndVersion;\n    uint16_t clockSeq;\n    uint8_t node[6];\n} effect_uuid_t;\n\n// Maximum length of character strings in structures defines by this API.\n#define EFFECT_STRING_LEN_MAX 64\n\n// NULL UUID definition (matches SL_IID_NULL_)\n#define EFFECT_UUID_INITIALIZER { 0xec7178ec, 0xe5e1, 0x4432, 0xa3f4, \\\n                                  { 0x46, 0x57, 0xe6, 0x79, 0x52, 0x10 } }\nstatic const effect_uuid_t EFFECT_UUID_NULL_ = EFFECT_UUID_INITIALIZER;\nstatic const effect_uuid_t * const EFFECT_UUID_NULL = &EFFECT_UUID_NULL_;\nstatic const char * const EFFECT_UUID_NULL_STR = \"ec7178ec-e5e1-4432-a3f4-4657e6795210\";\n\n\n// The effect descriptor contains necessary information to facilitate the enumeration of the effect\n// engines present in a library.\ntypedef struct effect_descriptor_s {\n    effect_uuid_t type;     // UUID of to the OpenSL ES interface implemented by this effect\n    effect_uuid_t uuid;     // UUID for this particular implementation\n    uint32_t apiVersion;    // Version of the effect control API implemented\n    uint32_t flags;         // effect engine capabilities/requirements flags (see below)\n    uint16_t cpuLoad;       // CPU load indication (see below)\n    uint16_t memoryUsage;   // Data Memory usage (see below)\n    char    name[EFFECT_STRING_LEN_MAX];   // human readable effect name\n    char    implementor[EFFECT_STRING_LEN_MAX];    // human readable effect implementor name\n} effect_descriptor_t;\n\n// CPU load and memory usage indication: each effect implementation must provide an indication of\n// its CPU and memory usage for the audio effect framework to limit the number of effects\n// instantiated at a given time on a given platform.\n// The CPU load is expressed in 0.1 MIPS units as estimated on an ARM9E core (ARMv5TE) with 0 WS.\n// The memory usage is expressed in KB and includes only dynamically allocated memory\n\n// Definitions for flags field of effect descriptor.\n//  +---------------------------+-----------+-----------------------------------\n//  | description               | bits      | values\n//  +---------------------------+-----------+-----------------------------------\n//  | connection mode           | 0..2      | 0 insert: after track process\n//  |                           |           | 1 auxiliary: connect to track auxiliary\n//  |                           |           |  output and use send level\n//  |                           |           | 2 replace: replaces track process function;\n//  |                           |           |   must implement SRC, volume and mono to stereo.\n//  |                           |           | 3 pre processing: applied below audio HAL on input\n//  |                           |           | 4 post processing: applied below audio HAL on output\n//  |                           |           | 5 - 7 reserved\n//  +---------------------------+-----------+-----------------------------------\n//  | insertion preference      | 3..5      | 0 none\n//  |                           |           | 1 first of the chain\n//  |                           |           | 2 last of the chain\n//  |                           |           | 3 exclusive (only effect in the insert chain)\n//  |                           |           | 4..7 reserved\n//  +---------------------------+-----------+-----------------------------------\n//  | Volume management         | 6..8      | 0 none\n//  |                           |           | 1 implements volume control\n//  |                           |           | 2 requires volume indication\n//  |                           |           | 4 reserved\n//  +---------------------------+-----------+-----------------------------------\n//  | Device indication         | 9..11     | 0 none\n//  |                           |           | 1 requires device updates\n//  |                           |           | 2, 4 reserved\n//  +---------------------------+-----------+-----------------------------------\n//  | Sample input mode         | 12..13    | 1 direct: process() function or EFFECT_CMD_SET_CONFIG\n//  |                           |           |   command must specify a buffer descriptor\n//  |                           |           | 2 provider: process() function uses the\n//  |                           |           |   bufferProvider indicated by the\n//  |                           |           |   EFFECT_CMD_SET_CONFIG command to request input.\n//  |                           |           |   buffers.\n//  |                           |           | 3 both: both input modes are supported\n//  +---------------------------+-----------+-----------------------------------\n//  | Sample output mode        | 14..15    | 1 direct: process() function or EFFECT_CMD_SET_CONFIG\n//  |                           |           |   command must specify a buffer descriptor\n//  |                           |           | 2 provider: process() function uses the\n//  |                           |           |   bufferProvider indicated by the\n//  |                           |           |   EFFECT_CMD_SET_CONFIG command to request output\n//  |                           |           |   buffers.\n//  |                           |           | 3 both: both output modes are supported\n//  +---------------------------+-----------+-----------------------------------\n//  | Hardware acceleration     | 16..17    | 0 No hardware acceleration\n//  |                           |           | 1 non tunneled hw acceleration: the process() function\n//  |                           |           |   reads the samples, send them to HW accelerated\n//  |                           |           |   effect processor, reads back the processed samples\n//  |                           |           |   and returns them to the output buffer.\n//  |                           |           | 2 tunneled hw acceleration: the process() function is\n//  |                           |           |   transparent. The effect interface is only used to\n//  |                           |           |   control the effect engine. This mode is relevant for\n//  |                           |           |   global effects actually applied by the audio\n//  |                           |           |   hardware on the output stream.\n//  +---------------------------+-----------+-----------------------------------\n//  | Audio Mode indication     | 18..19    | 0 none\n//  |                           |           | 1 requires audio mode updates\n//  |                           |           | 2..3 reserved\n//  +---------------------------+-----------+-----------------------------------\n//  | Audio source indication   | 20..21    | 0 none\n//  |                           |           | 1 requires audio source updates\n//  |                           |           | 2..3 reserved\n//  +---------------------------+-----------+-----------------------------------\n//  | Effect offload supported  | 22        | 0 The effect cannot be offloaded to an audio DSP\n//  |                           |           | 1 The effect can be offloaded to an audio DSP\n//  +---------------------------+-----------+-----------------------------------\n\n// Insert mode\n#define EFFECT_FLAG_TYPE_SHIFT          0\n#define EFFECT_FLAG_TYPE_SIZE           3\n#define EFFECT_FLAG_TYPE_MASK           (((1 << EFFECT_FLAG_TYPE_SIZE) -1) \\\n                                            << EFFECT_FLAG_TYPE_SHIFT)\n#define EFFECT_FLAG_TYPE_INSERT         (0 << EFFECT_FLAG_TYPE_SHIFT)\n#define EFFECT_FLAG_TYPE_AUXILIARY      (1 << EFFECT_FLAG_TYPE_SHIFT)\n#define EFFECT_FLAG_TYPE_REPLACE        (2 << EFFECT_FLAG_TYPE_SHIFT)\n#define EFFECT_FLAG_TYPE_PRE_PROC       (3 << EFFECT_FLAG_TYPE_SHIFT)\n#define EFFECT_FLAG_TYPE_POST_PROC      (4 << EFFECT_FLAG_TYPE_SHIFT)\n\n// Insert preference\n#define EFFECT_FLAG_INSERT_SHIFT        (EFFECT_FLAG_TYPE_SHIFT + EFFECT_FLAG_TYPE_SIZE)\n#define EFFECT_FLAG_INSERT_SIZE         3\n#define EFFECT_FLAG_INSERT_MASK         (((1 << EFFECT_FLAG_INSERT_SIZE) -1) \\\n                                            << EFFECT_FLAG_INSERT_SHIFT)\n#define EFFECT_FLAG_INSERT_ANY          (0 << EFFECT_FLAG_INSERT_SHIFT)\n#define EFFECT_FLAG_INSERT_FIRST        (1 << EFFECT_FLAG_INSERT_SHIFT)\n#define EFFECT_FLAG_INSERT_LAST         (2 << EFFECT_FLAG_INSERT_SHIFT)\n#define EFFECT_FLAG_INSERT_EXCLUSIVE    (3 << EFFECT_FLAG_INSERT_SHIFT)\n\n\n// Volume control\n#define EFFECT_FLAG_VOLUME_SHIFT        (EFFECT_FLAG_INSERT_SHIFT + EFFECT_FLAG_INSERT_SIZE)\n#define EFFECT_FLAG_VOLUME_SIZE         3\n#define EFFECT_FLAG_VOLUME_MASK         (((1 << EFFECT_FLAG_VOLUME_SIZE) -1) \\\n                                            << EFFECT_FLAG_VOLUME_SHIFT)\n#define EFFECT_FLAG_VOLUME_CTRL         (1 << EFFECT_FLAG_VOLUME_SHIFT)\n#define EFFECT_FLAG_VOLUME_IND          (2 << EFFECT_FLAG_VOLUME_SHIFT)\n#define EFFECT_FLAG_VOLUME_NONE         (0 << EFFECT_FLAG_VOLUME_SHIFT)\n\n// Device indication\n#define EFFECT_FLAG_DEVICE_SHIFT        (EFFECT_FLAG_VOLUME_SHIFT + EFFECT_FLAG_VOLUME_SIZE)\n#define EFFECT_FLAG_DEVICE_SIZE         3\n#define EFFECT_FLAG_DEVICE_MASK         (((1 << EFFECT_FLAG_DEVICE_SIZE) -1) \\\n                                            << EFFECT_FLAG_DEVICE_SHIFT)\n#define EFFECT_FLAG_DEVICE_IND          (1 << EFFECT_FLAG_DEVICE_SHIFT)\n#define EFFECT_FLAG_DEVICE_NONE         (0 << EFFECT_FLAG_DEVICE_SHIFT)\n\n// Sample input modes\n#define EFFECT_FLAG_INPUT_SHIFT         (EFFECT_FLAG_DEVICE_SHIFT + EFFECT_FLAG_DEVICE_SIZE)\n#define EFFECT_FLAG_INPUT_SIZE          2\n#define EFFECT_FLAG_INPUT_MASK          (((1 << EFFECT_FLAG_INPUT_SIZE) -1) \\\n                                            << EFFECT_FLAG_INPUT_SHIFT)\n#define EFFECT_FLAG_INPUT_DIRECT        (1 << EFFECT_FLAG_INPUT_SHIFT)\n#define EFFECT_FLAG_INPUT_PROVIDER      (2 << EFFECT_FLAG_INPUT_SHIFT)\n#define EFFECT_FLAG_INPUT_BOTH          (3 << EFFECT_FLAG_INPUT_SHIFT)\n\n// Sample output modes\n#define EFFECT_FLAG_OUTPUT_SHIFT        (EFFECT_FLAG_INPUT_SHIFT + EFFECT_FLAG_INPUT_SIZE)\n#define EFFECT_FLAG_OUTPUT_SIZE         2\n#define EFFECT_FLAG_OUTPUT_MASK         (((1 << EFFECT_FLAG_OUTPUT_SIZE) -1) \\\n                                            << EFFECT_FLAG_OUTPUT_SHIFT)\n#define EFFECT_FLAG_OUTPUT_DIRECT       (1 << EFFECT_FLAG_OUTPUT_SHIFT)\n#define EFFECT_FLAG_OUTPUT_PROVIDER     (2 << EFFECT_FLAG_OUTPUT_SHIFT)\n#define EFFECT_FLAG_OUTPUT_BOTH         (3 << EFFECT_FLAG_OUTPUT_SHIFT)\n\n// Hardware acceleration mode\n#define EFFECT_FLAG_HW_ACC_SHIFT        (EFFECT_FLAG_OUTPUT_SHIFT + EFFECT_FLAG_OUTPUT_SIZE)\n#define EFFECT_FLAG_HW_ACC_SIZE         2\n#define EFFECT_FLAG_HW_ACC_MASK         (((1 << EFFECT_FLAG_HW_ACC_SIZE) -1) \\\n                                            << EFFECT_FLAG_HW_ACC_SHIFT)\n#define EFFECT_FLAG_HW_ACC_SIMPLE       (1 << EFFECT_FLAG_HW_ACC_SHIFT)\n#define EFFECT_FLAG_HW_ACC_TUNNEL       (2 << EFFECT_FLAG_HW_ACC_SHIFT)\n\n// Audio mode indication\n#define EFFECT_FLAG_AUDIO_MODE_SHIFT    (EFFECT_FLAG_HW_ACC_SHIFT + EFFECT_FLAG_HW_ACC_SIZE)\n#define EFFECT_FLAG_AUDIO_MODE_SIZE     2\n#define EFFECT_FLAG_AUDIO_MODE_MASK     (((1 << EFFECT_FLAG_AUDIO_MODE_SIZE) -1) \\\n                                            << EFFECT_FLAG_AUDIO_MODE_SHIFT)\n#define EFFECT_FLAG_AUDIO_MODE_IND      (1 << EFFECT_FLAG_AUDIO_MODE_SHIFT)\n#define EFFECT_FLAG_AUDIO_MODE_NONE     (0 << EFFECT_FLAG_AUDIO_MODE_SHIFT)\n\n// Audio source indication\n#define EFFECT_FLAG_AUDIO_SOURCE_SHIFT  (EFFECT_FLAG_AUDIO_MODE_SHIFT + EFFECT_FLAG_AUDIO_MODE_SIZE)\n#define EFFECT_FLAG_AUDIO_SOURCE_SIZE   2\n#define EFFECT_FLAG_AUDIO_SOURCE_MASK   (((1 << EFFECT_FLAG_AUDIO_SOURCE_SIZE) -1) \\\n                                          << EFFECT_FLAG_AUDIO_SOURCE_SHIFT)\n#define EFFECT_FLAG_AUDIO_SOURCE_IND    (1 << EFFECT_FLAG_AUDIO_SOURCE_SHIFT)\n#define EFFECT_FLAG_AUDIO_SOURCE_NONE   (0 << EFFECT_FLAG_AUDIO_SOURCE_SHIFT)\n\n// Effect offload indication\n#define EFFECT_FLAG_OFFLOAD_SHIFT       (EFFECT_FLAG_AUDIO_SOURCE_SHIFT + \\\n                                                    EFFECT_FLAG_AUDIO_SOURCE_SIZE)\n#define EFFECT_FLAG_OFFLOAD_SIZE        1\n#define EFFECT_FLAG_OFFLOAD_MASK        (((1 << EFFECT_FLAG_OFFLOAD_SIZE) -1) \\\n                                          << EFFECT_FLAG_OFFLOAD_SHIFT)\n#define EFFECT_FLAG_OFFLOAD_SUPPORTED   (1 << EFFECT_FLAG_OFFLOAD_SHIFT)\n\n#define EFFECT_MAKE_API_VERSION(M, m)  (((M)<<16) | ((m) & 0xFFFF))\n#define EFFECT_API_VERSION_MAJOR(v)    ((v)>>16)\n#define EFFECT_API_VERSION_MINOR(v)    ((m) & 0xFFFF)\n\n\n\n/////////////////////////////////////////////////\n//      Effect control interface\n/////////////////////////////////////////////////\n\n// Effect control interface version 2.0\n#define EFFECT_CONTROL_API_VERSION EFFECT_MAKE_API_VERSION(2,0)\n\n// Effect control interface structure: effect_interface_s\n// The effect control interface is exposed by each effect engine implementation. It consists of\n// a set of functions controlling the configuration, activation and process of the engine.\n// The functions are grouped in a structure of type effect_interface_s.\n//\n// Effect control interface handle: effect_handle_t\n// The effect_handle_t serves two purposes regarding the implementation of the effect engine:\n// - 1 it is the address of a pointer to an effect_interface_s structure where the functions\n// of the effect control API for a particular effect are located.\n// - 2 it is the address of the context of a particular effect instance.\n// A typical implementation in the effect library would define a structure as follows:\n// struct effect_module_s {\n//        const struct effect_interface_s *itfe;\n//        effect_config_t config;\n//        effect_context_t context;\n// }\n// The implementation of EffectCreate() function would then allocate a structure of this\n// type and return its address as effect_handle_t\ntypedef struct effect_interface_s **effect_handle_t;\n\n\n// Forward definition of type audio_buffer_t\ntypedef struct audio_buffer_s audio_buffer_t;\n\n\n\n\n\n\n// Effect control interface definition\nstruct effect_interface_s {\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:       process\n    //\n    //    Description:    Effect process function. Takes input samples as specified\n    //          (count and location) in input buffer descriptor and output processed\n    //          samples as specified in output buffer descriptor. If the buffer descriptor\n    //          is not specified the function must use either the buffer or the\n    //          buffer provider function installed by the EFFECT_CMD_SET_CONFIG command.\n    //          The effect framework will call the process() function after the EFFECT_CMD_ENABLE\n    //          command is received and until the EFFECT_CMD_DISABLE is received. When the engine\n    //          receives the EFFECT_CMD_DISABLE command it should turn off the effect gracefully\n    //          and when done indicate that it is OK to stop calling the process() function by\n    //          returning the -ENODATA status.\n    //\n    //    NOTE: the process() function implementation should be \"real-time safe\" that is\n    //      it should not perform blocking calls: malloc/free, sleep, read/write/open/close,\n    //      pthread_cond_wait/pthread_mutex_lock...\n    //\n    //    Input:\n    //          self:       handle to the effect interface this function\n    //              is called on.\n    //          inBuffer:   buffer descriptor indicating where to read samples to process.\n    //              If NULL, use the configuration passed by EFFECT_CMD_SET_CONFIG command.\n    //\n    //          outBuffer:   buffer descriptor indicating where to write processed samples.\n    //              If NULL, use the configuration passed by EFFECT_CMD_SET_CONFIG command.\n    //\n    //    Output:\n    //        returned value:    0 successful operation\n    //                          -ENODATA the engine has finished the disable phase and the framework\n    //                                  can stop calling process()\n    //                          -EINVAL invalid interface handle or\n    //                                  invalid input/output buffer description\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*process)(effect_handle_t self,\n                       audio_buffer_t *inBuffer,\n                       audio_buffer_t *outBuffer);\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:       command\n    //\n    //    Description:    Send a command and receive a response to/from effect engine.\n    //\n    //    Input:\n    //          self:       handle to the effect interface this function\n    //              is called on.\n    //          cmdCode:    command code: the command can be a standardized command defined in\n    //              effect_command_e (see below) or a proprietary command.\n    //          cmdSize:    size of command in bytes\n    //          pCmdData:   pointer to command data\n    //          pReplyData: pointer to reply data\n    //\n    //    Input/Output:\n    //          replySize: maximum size of reply data as input\n    //                      actual size of reply data as output\n    //\n    //    Output:\n    //          returned value: 0       successful operation\n    //                          -EINVAL invalid interface handle or\n    //                                  invalid command/reply size or format according to\n    //                                  command code\n    //              The return code should be restricted to indicate problems related to this API\n    //              specification. Status related to the execution of a particular command should be\n    //              indicated as part of the reply field.\n    //\n    //          *pReplyData updated with command response\n    //\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*command)(effect_handle_t self,\n                       uint32_t cmdCode,\n                       uint32_t cmdSize,\n                       void *pCmdData,\n                       uint32_t *replySize,\n                       void *pReplyData);\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:        get_descriptor\n    //\n    //    Description:    Returns the effect descriptor\n    //\n    //    Input:\n    //          self:       handle to the effect interface this function\n    //              is called on.\n    //\n    //    Input/Output:\n    //          pDescriptor:    address where to return the effect descriptor.\n    //\n    //    Output:\n    //        returned value:    0          successful operation.\n    //                          -EINVAL     invalid interface handle or invalid pDescriptor\n    //        *pDescriptor:     updated with the effect descriptor.\n    //\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*get_descriptor)(effect_handle_t self,\n                              effect_descriptor_t *pDescriptor);\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:       process_reverse\n    //\n    //    Description:    Process reverse stream function. This function is used to pass\n    //          a reference stream to the effect engine. If the engine does not need a reference\n    //          stream, this function pointer can be set to NULL.\n    //          This function would typically implemented by an Echo Canceler.\n    //\n    //    Input:\n    //          self:       handle to the effect interface this function\n    //              is called on.\n    //          inBuffer:   buffer descriptor indicating where to read samples to process.\n    //              If NULL, use the configuration passed by EFFECT_CMD_SET_CONFIG_REVERSE command.\n    //\n    //          outBuffer:   buffer descriptor indicating where to write processed samples.\n    //              If NULL, use the configuration passed by EFFECT_CMD_SET_CONFIG_REVERSE command.\n    //              If the buffer and buffer provider in the configuration received by\n    //              EFFECT_CMD_SET_CONFIG_REVERSE are also NULL, do not return modified reverse\n    //              stream data\n    //\n    //    Output:\n    //        returned value:    0 successful operation\n    //                          -ENODATA the engine has finished the disable phase and the framework\n    //                                  can stop calling process_reverse()\n    //                          -EINVAL invalid interface handle or\n    //                                  invalid input/output buffer description\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*process_reverse)(effect_handle_t self,\n                               audio_buffer_t *inBuffer,\n                               audio_buffer_t *outBuffer);\n};\n\n\n//\n//--- Standardized command codes for command() function\n//\nenum effect_command_e {\n   EFFECT_CMD_INIT,                 // initialize effect engine\n   EFFECT_CMD_SET_CONFIG,           // configure effect engine (see effect_config_t)\n   EFFECT_CMD_RESET,                // reset effect engine\n   EFFECT_CMD_ENABLE,               // enable effect process\n   EFFECT_CMD_DISABLE,              // disable effect process\n   EFFECT_CMD_SET_PARAM,            // set parameter immediately (see effect_param_t)\n   EFFECT_CMD_SET_PARAM_DEFERRED,   // set parameter deferred\n   EFFECT_CMD_SET_PARAM_COMMIT,     // commit previous set parameter deferred\n   EFFECT_CMD_GET_PARAM,            // get parameter\n   EFFECT_CMD_SET_DEVICE,           // set audio device (see audio.h, audio_devices_t)\n   EFFECT_CMD_SET_VOLUME,           // set volume\n   EFFECT_CMD_SET_AUDIO_MODE,       // set the audio mode (normal, ring, ...)\n   EFFECT_CMD_SET_CONFIG_REVERSE,   // configure effect engine reverse stream(see effect_config_t)\n   EFFECT_CMD_SET_INPUT_DEVICE,     // set capture device (see audio.h, audio_devices_t)\n   EFFECT_CMD_GET_CONFIG,           // read effect engine configuration\n   EFFECT_CMD_GET_CONFIG_REVERSE,   // read configure effect engine reverse stream configuration\n   EFFECT_CMD_GET_FEATURE_SUPPORTED_CONFIGS,// get all supported configurations for a feature.\n   EFFECT_CMD_GET_FEATURE_CONFIG,   // get current feature configuration\n   EFFECT_CMD_SET_FEATURE_CONFIG,   // set current feature configuration\n   EFFECT_CMD_SET_AUDIO_SOURCE,     // set the audio source (see audio.h, audio_source_t)\n   EFFECT_CMD_OFFLOAD,              // set if effect thread is an offload one,\n                                    // send the ioHandle of the effect thread\n   EFFECT_CMD_FIRST_PROPRIETARY = 0x10000 // first proprietary command code\n};\n\n//==================================================================================================\n// command: EFFECT_CMD_INIT\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Initialize effect engine: All configurations return to default\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_SET_CONFIG\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Apply new audio parameters configurations for input and output buffers\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(effect_config_t)\n//  data: effect_config_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_RESET\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Reset the effect engine. Keep configuration but resets state and buffer content\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 0\n//  data: N/A\n//==================================================================================================\n// command: EFFECT_CMD_ENABLE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Enable the process. Called by the framework before the first call to process()\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_DISABLE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Disable the process. Called by the framework after the last call to process()\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_SET_PARAM\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set a parameter and apply it immediately\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(effect_param_t) + size of param and value\n//  data: effect_param_t + param + value. See effect_param_t definition below for value offset\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_SET_PARAM_DEFERRED\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set a parameter but apply it only when receiving EFFECT_CMD_SET_PARAM_COMMIT command\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(effect_param_t) + size of param and value\n//  data: effect_param_t + param + value. See effect_param_t definition below for value offset\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 0\n//  data: N/A\n//==================================================================================================\n// command: EFFECT_CMD_SET_PARAM_COMMIT\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Apply all previously received EFFECT_CMD_SET_PARAM_DEFERRED commands\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_GET_PARAM\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Get a parameter value\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(effect_param_t) + size of param\n//  data: effect_param_t + param\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(effect_param_t) + size of param and value\n//  data: effect_param_t + param + value. See effect_param_t definition below for value offset\n//==================================================================================================\n// command: EFFECT_CMD_SET_DEVICE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set the rendering device the audio output path is connected to. See audio.h, audio_devices_t\n//  for device values.\n//  The effect implementation must set EFFECT_FLAG_DEVICE_IND flag in its descriptor to receive this\n//  command when the device changes\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(uint32_t)\n//  data: uint32_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 0\n//  data: N/A\n//==================================================================================================\n// command: EFFECT_CMD_SET_VOLUME\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set and get volume. Used by audio framework to delegate volume control to effect engine.\n//  The effect implementation must set EFFECT_FLAG_VOLUME_IND or EFFECT_FLAG_VOLUME_CTRL flag in\n//  its descriptor to receive this command before every call to process() function\n//  If EFFECT_FLAG_VOLUME_CTRL flag is set in the effect descriptor, the effect engine must return\n//  the volume that should be applied before the effect is processed. The overall volume (the volume\n//  actually applied by the effect engine multiplied by the returned value) should match the value\n//  indicated in the command.\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: n * sizeof(uint32_t)\n//  data: volume for each channel defined in effect_config_t for output buffer expressed in\n//      8.24 fixed point format\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: n * sizeof(uint32_t) / 0\n//  data: - if EFFECT_FLAG_VOLUME_CTRL is set in effect descriptor:\n//              volume for each channel defined in effect_config_t for output buffer expressed in\n//              8.24 fixed point format\n//        - if EFFECT_FLAG_VOLUME_CTRL is not set in effect descriptor:\n//              N/A\n//  It is legal to receive a null pointer as pReplyData in which case the effect framework has\n//  delegated volume control to another effect\n//==================================================================================================\n// command: EFFECT_CMD_SET_AUDIO_MODE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set the audio mode. The effect implementation must set EFFECT_FLAG_AUDIO_MODE_IND flag in its\n//  descriptor to receive this command when the audio mode changes.\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(uint32_t)\n//  data: audio_mode_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 0\n//  data: N/A\n//==================================================================================================\n// command: EFFECT_CMD_SET_CONFIG_REVERSE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Apply new audio parameters configurations for input and output buffers of reverse stream.\n//  An example of reverse stream is the echo reference supplied to an Acoustic Echo Canceler.\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(effect_config_t)\n//  data: effect_config_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(int)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_SET_INPUT_DEVICE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set the capture device the audio input path is connected to. See audio.h, audio_devices_t\n//  for device values.\n//  The effect implementation must set EFFECT_FLAG_DEVICE_IND flag in its descriptor to receive this\n//  command when the device changes\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(uint32_t)\n//  data: uint32_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 0\n//  data: N/A\n//==================================================================================================\n// command: EFFECT_CMD_GET_CONFIG\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Read audio parameters configurations for input and output buffers\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(effect_config_t)\n//  data: effect_config_t\n//==================================================================================================\n// command: EFFECT_CMD_GET_CONFIG_REVERSE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Read audio parameters configurations for input and output buffers of reverse stream\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 0\n//  data: N/A\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(effect_config_t)\n//  data: effect_config_t\n//==================================================================================================\n// command: EFFECT_CMD_GET_FEATURE_SUPPORTED_CONFIGS\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Queries for supported configurations for a particular feature (e.g. get the supported\n// combinations of main and auxiliary channels for a noise suppressor).\n// The command parameter is the feature identifier (See effect_feature_e for a list of defined\n// features) followed by the maximum number of configuration descriptor to return.\n// The reply is composed of:\n//  - status (uint32_t):\n//          - 0 if feature is supported\n//          - -ENOSYS if the feature is not supported,\n//          - -ENOMEM if the feature is supported but the total number of supported configurations\n//          exceeds the maximum number indicated by the caller.\n//  - total number of supported configurations (uint32_t)\n//  - an array of configuration descriptors.\n// The actual number of descriptors returned must not exceed the maximum number indicated by\n// the caller.\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: 2 x sizeof(uint32_t)\n//  data: effect_feature_e + maximum number of configurations to return\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 2 x sizeof(uint32_t) + n x sizeof (<config descriptor>)\n//  data: status + total number of configurations supported + array of n config descriptors\n//==================================================================================================\n// command: EFFECT_CMD_GET_FEATURE_CONFIG\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Retrieves current configuration for a given feature.\n// The reply status is:\n//      - 0 if feature is supported\n//      - -ENOSYS if the feature is not supported,\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(uint32_t)\n//  data: effect_feature_e\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(uint32_t) + sizeof (<config descriptor>)\n//  data: status + config descriptor\n//==================================================================================================\n// command: EFFECT_CMD_SET_FEATURE_CONFIG\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Sets current configuration for a given feature.\n// The reply status is:\n//      - 0 if feature is supported\n//      - -ENOSYS if the feature is not supported,\n//      - -EINVAL if the configuration is invalid\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(uint32_t) + sizeof (<config descriptor>)\n//  data: effect_feature_e + config descriptor\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(uint32_t)\n//  data: status\n//==================================================================================================\n// command: EFFECT_CMD_SET_AUDIO_SOURCE\n//--------------------------------------------------------------------------------------------------\n// description:\n//  Set the audio source the capture path is configured for (Camcorder, voice recognition...).\n//  See audio.h, audio_source_t for values.\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(uint32_t)\n//  data: uint32_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: 0\n//  data: N/A\n//==================================================================================================\n// command: EFFECT_CMD_OFFLOAD\n//--------------------------------------------------------------------------------------------------\n// description:\n//  1.indicate if the playback thread the effect is attached to is offloaded or not\n//  2.update the io handle of the playback thread the effect is attached to\n//--------------------------------------------------------------------------------------------------\n// command format:\n//  size: sizeof(effect_offload_param_t)\n//  data: effect_offload_param_t\n//--------------------------------------------------------------------------------------------------\n// reply format:\n//  size: sizeof(uint32_t)\n//  data: uint32_t\n//--------------------------------------------------------------------------------------------------\n// command: EFFECT_CMD_FIRST_PROPRIETARY\n//--------------------------------------------------------------------------------------------------\n// description:\n//  All proprietary effect commands must use command codes above this value. The size and format of\n//  command and response fields is free in this case\n//==================================================================================================\n\n\n// Audio buffer descriptor used by process(), bufferProvider() functions and buffer_config_t\n// structure. Multi-channel audio is always interleaved. The channel order is from LSB to MSB with\n// regard to the channel mask definition in audio.h, audio_channel_mask_t e.g :\n// Stereo: left, right\n// 5 point 1: front left, front right, front center, low frequency, back left, back right\n// The buffer size is expressed in frame count, a frame being composed of samples for all\n// channels at a given time. Frame size for unspecified format (AUDIO_FORMAT_OTHER) is 8 bit by\n// definition\nstruct audio_buffer_s {\n    size_t   frameCount;        // number of frames in buffer\n    union {\n        void*       raw;        // raw pointer to start of buffer\n        int32_t*    s32;        // pointer to signed 32 bit data at start of buffer\n        int16_t*    s16;        // pointer to signed 16 bit data at start of buffer\n        uint8_t*    u8;         // pointer to unsigned 8 bit data at start of buffer\n    };\n};\n\n// The buffer_provider_s structure contains functions that can be used\n// by the effect engine process() function to query and release input\n// or output audio buffer.\n// The getBuffer() function is called to retrieve a buffer where data\n// should read from or written to by process() function.\n// The releaseBuffer() function MUST be called when the buffer retrieved\n// with getBuffer() is not needed anymore.\n// The process function should use the buffer provider mechanism to retrieve\n// input or output buffer if the inBuffer or outBuffer passed as argument is NULL\n// and the buffer configuration (buffer_config_t) given by the EFFECT_CMD_SET_CONFIG\n// command did not specify an audio buffer.\n\ntypedef int32_t (* buffer_function_t)(void *cookie, audio_buffer_t *buffer);\n\ntypedef struct buffer_provider_s {\n    buffer_function_t getBuffer;       // retrieve next buffer\n    buffer_function_t releaseBuffer;   // release used buffer\n    void       *cookie;                // for use by client of buffer provider functions\n} buffer_provider_t;\n\n\n// The buffer_config_s structure specifies the input or output audio format\n// to be used by the effect engine. It is part of the effect_config_t\n// structure that defines both input and output buffer configurations and is\n// passed by the EFFECT_CMD_SET_CONFIG or EFFECT_CMD_SET_CONFIG_REVERSE command.\ntypedef struct buffer_config_s {\n    audio_buffer_t  buffer;     // buffer for use by process() function if not passed explicitly\n    uint32_t   samplingRate;    // sampling rate\n    uint32_t   channels;        // channel mask (see audio_channel_mask_t in audio.h)\n    buffer_provider_t bufferProvider;   // buffer provider\n    uint8_t    format;          // Audio format (see audio_format_t in audio.h)\n    uint8_t    accessMode;      // read/write or accumulate in buffer (effect_buffer_access_e)\n    uint16_t   mask;            // indicates which of the above fields is valid\n} buffer_config_t;\n\n// Values for \"accessMode\" field of buffer_config_t:\n//   overwrite, read only, accumulate (read/modify/write)\nenum effect_buffer_access_e {\n    EFFECT_BUFFER_ACCESS_WRITE,\n    EFFECT_BUFFER_ACCESS_READ,\n    EFFECT_BUFFER_ACCESS_ACCUMULATE\n\n};\n\n// feature identifiers for EFFECT_CMD_GET_FEATURE_SUPPORTED_CONFIGS command\nenum effect_feature_e {\n    EFFECT_FEATURE_AUX_CHANNELS, // supports auxiliary channels (e.g. dual mic noise suppressor)\n    EFFECT_FEATURE_CNT\n};\n\n// EFFECT_FEATURE_AUX_CHANNELS feature configuration descriptor. Describe a combination\n// of main and auxiliary channels supported\ntypedef struct channel_config_s {\n    audio_channel_mask_t main_channels; // channel mask for main channels\n    audio_channel_mask_t aux_channels;  // channel mask for auxiliary channels\n} channel_config_t;\n\n\n// Values for bit field \"mask\" in buffer_config_t. If a bit is set, the corresponding field\n// in buffer_config_t must be taken into account when executing the EFFECT_CMD_SET_CONFIG command\n#define EFFECT_CONFIG_BUFFER    0x0001  // buffer field must be taken into account\n#define EFFECT_CONFIG_SMP_RATE  0x0002  // samplingRate field must be taken into account\n#define EFFECT_CONFIG_CHANNELS  0x0004  // channels field must be taken into account\n#define EFFECT_CONFIG_FORMAT    0x0008  // format field must be taken into account\n#define EFFECT_CONFIG_ACC_MODE  0x0010  // accessMode field must be taken into account\n#define EFFECT_CONFIG_PROVIDER  0x0020  // bufferProvider field must be taken into account\n#define EFFECT_CONFIG_ALL (EFFECT_CONFIG_BUFFER | EFFECT_CONFIG_SMP_RATE | \\\n                           EFFECT_CONFIG_CHANNELS | EFFECT_CONFIG_FORMAT | \\\n                           EFFECT_CONFIG_ACC_MODE | EFFECT_CONFIG_PROVIDER)\n\n\n// effect_config_s structure describes the format of the pCmdData argument of EFFECT_CMD_SET_CONFIG\n// command to configure audio parameters and buffers for effect engine input and output.\ntypedef struct effect_config_s {\n    buffer_config_t   inputCfg;\n    buffer_config_t   outputCfg;\n} effect_config_t;\n\n\n// effect_param_s structure describes the format of the pCmdData argument of EFFECT_CMD_SET_PARAM\n// command and pCmdData and pReplyData of EFFECT_CMD_GET_PARAM command.\n// psize and vsize represent the actual size of parameter and value.\n//\n// NOTE: the start of value field inside the data field is always on a 32 bit boundary:\n//\n//  +-----------+\n//  | status    | sizeof(int)\n//  +-----------+\n//  | psize     | sizeof(int)\n//  +-----------+\n//  | vsize     | sizeof(int)\n//  +-----------+\n//  |           |   |           |\n//  ~ parameter ~   > psize     |\n//  |           |   |           >  ((psize - 1)/sizeof(int) + 1) * sizeof(int)\n//  +-----------+               |\n//  | padding   |               |\n//  +-----------+\n//  |           |   |\n//  ~ value     ~   > vsize\n//  |           |   |\n//  +-----------+\n\ntypedef struct effect_param_s {\n    int32_t     status;     // Transaction status (unused for command, used for reply)\n    uint32_t    psize;      // Parameter size\n    uint32_t    vsize;      // Value size\n    char        data[];     // Start of Parameter + Value data\n} effect_param_t;\n\n// structure used by EFFECT_CMD_OFFLOAD command\ntypedef struct effect_offload_param_s {\n    bool isOffload;         // true if the playback thread the effect is attached to is offloaded\n    int ioHandle;           // io handle of the playback thread the effect is attached to\n} effect_offload_param_t;\n\n\n/////////////////////////////////////////////////\n//      Effect library interface\n/////////////////////////////////////////////////\n\n// Effect library interface version 3.0\n// Note that EffectsFactory.c only checks the major version component, so changes to the minor\n// number can only be used for fully backwards compatible changes\n#define EFFECT_LIBRARY_API_VERSION EFFECT_MAKE_API_VERSION(3,0)\n\n#define AUDIO_EFFECT_LIBRARY_TAG ((('A') << 24) | (('E') << 16) | (('L') << 8) | ('T'))\n\n// Every effect library must have a data structure named AUDIO_EFFECT_LIBRARY_INFO_SYM\n// and the fields of this data structure must begin with audio_effect_library_t\n\ntypedef struct audio_effect_library_s {\n    // tag must be initialized to AUDIO_EFFECT_LIBRARY_TAG\n    uint32_t tag;\n    // Version of the effect library API : 0xMMMMmmmm MMMM: Major, mmmm: minor\n    uint32_t version;\n    // Name of this library\n    const char *name;\n    // Author/owner/implementor of the library\n    const char *implementor;\n\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:        create_effect\n    //\n    //    Description:    Creates an effect engine of the specified implementation uuid and\n    //          returns an effect control interface on this engine. The function will allocate the\n    //          resources for an instance of the requested effect engine and return\n    //          a handle on the effect control interface.\n    //\n    //    Input:\n    //          uuid:    pointer to the effect uuid.\n    //          sessionId:  audio session to which this effect instance will be attached.\n    //              All effects created with the same session ID are connected in series and process\n    //              the same signal stream. Knowing that two effects are part of the same effect\n    //              chain can help the library implement some kind of optimizations.\n    //          ioId:   identifies the output or input stream this effect is directed to in\n    //              audio HAL.\n    //              For future use especially with tunneled HW accelerated effects\n    //\n    //    Input/Output:\n    //          pHandle:        address where to return the effect interface handle.\n    //\n    //    Output:\n    //        returned value:    0          successful operation.\n    //                          -ENODEV     library failed to initialize\n    //                          -EINVAL     invalid pEffectUuid or pHandle\n    //                          -ENOENT     no effect with this uuid found\n    //        *pHandle:         updated with the effect interface handle.\n    //\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*create_effect)(const effect_uuid_t *uuid,\n                             int32_t sessionId,\n                             int32_t ioId,\n                             effect_handle_t *pHandle);\n\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:        release_effect\n    //\n    //    Description:    Releases the effect engine whose handle is given as argument.\n    //          All resources allocated to this particular instance of the effect are\n    //          released.\n    //\n    //    Input:\n    //          handle:         handle on the effect interface to be released.\n    //\n    //    Output:\n    //        returned value:    0          successful operation.\n    //                          -ENODEV     library failed to initialize\n    //                          -EINVAL     invalid interface handle\n    //\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*release_effect)(effect_handle_t handle);\n\n    ////////////////////////////////////////////////////////////////////////////////\n    //\n    //    Function:        get_descriptor\n    //\n    //    Description:    Returns the descriptor of the effect engine which implementation UUID is\n    //          given as argument.\n    //\n    //    Input/Output:\n    //          uuid:           pointer to the effect uuid.\n    //          pDescriptor:    address where to return the effect descriptor.\n    //\n    //    Output:\n    //        returned value:    0          successful operation.\n    //                          -ENODEV     library failed to initialize\n    //                          -EINVAL     invalid pDescriptor or uuid\n    //        *pDescriptor:     updated with the effect descriptor.\n    //\n    ////////////////////////////////////////////////////////////////////////////////\n    int32_t (*get_descriptor)(const effect_uuid_t *uuid,\n                              effect_descriptor_t *pDescriptor);\n} audio_effect_library_t;\n\n// Name of the hal_module_info\n#define AUDIO_EFFECT_LIBRARY_INFO_SYM         AELI\n\n// Name of the hal_module_info as a string\n#define AUDIO_EFFECT_LIBRARY_INFO_SYM_AS_STR  \"AELI\"\n\n__END_DECLS\n\n#endif  // ANDROID_AUDIO_EFFECT_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/audio_policy.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_AUDIO_POLICY_INTERFACE_H\n#define ANDROID_AUDIO_POLICY_INTERFACE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n#include <system/audio.h>\n#include <system/audio_policy.h>\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define AUDIO_POLICY_HARDWARE_MODULE_ID \"audio_policy\"\n\n/**\n * Name of the audio devices to open\n */\n#define AUDIO_POLICY_INTERFACE \"policy\"\n\n/* ---------------------------------------------------------------------------- */\n\n/*\n * The audio_policy and audio_policy_service_ops structs define the\n * communication interfaces between the platform specific audio policy manager\n * and Android generic audio policy manager.\n * The platform specific audio policy manager must implement methods of the\n * audio_policy struct.\n * This implementation makes use of the audio_policy_service_ops to control\n * the activity and configuration of audio input and output streams.\n *\n * The platform specific audio policy manager is in charge of the audio\n * routing and volume control policies for a given platform.\n * The main roles of this module are:\n *   - keep track of current system state (removable device connections, phone\n *     state, user requests...).\n *   System state changes and user actions are notified to audio policy\n *   manager with methods of the audio_policy.\n *\n *   - process get_output() queries received when AudioTrack objects are\n *     created: Those queries return a handler on an output that has been\n *     selected, configured and opened by the audio policy manager and that\n *     must be used by the AudioTrack when registering to the AudioFlinger\n *     with the createTrack() method.\n *   When the AudioTrack object is released, a release_output() query\n *   is received and the audio policy manager can decide to close or\n *   reconfigure the output depending on other streams using this output and\n *   current system state.\n *\n *   - similarly process get_input() and release_input() queries received from\n *     AudioRecord objects and configure audio inputs.\n *   - process volume control requests: the stream volume is converted from\n *     an index value (received from UI) to a float value applicable to each\n *     output as a function of platform specific settings and current output\n *     route (destination device). It also make sure that streams are not\n *     muted if not allowed (e.g. camera shutter sound in some countries).\n */\n\n/* XXX: this should be defined OUTSIDE of frameworks/base */\nstruct effect_descriptor_s;\n\nstruct audio_policy {\n    /*\n     * configuration functions\n     */\n\n    /* indicate a change in device connection status */\n    int (*set_device_connection_state)(struct audio_policy *pol,\n                                       audio_devices_t device,\n                                       audio_policy_dev_state_t state,\n                                       const char *device_address);\n\n    /* retrieve a device connection status */\n    audio_policy_dev_state_t (*get_device_connection_state)(\n                                            const struct audio_policy *pol,\n                                            audio_devices_t device,\n                                            const char *device_address);\n\n    /* indicate a change in phone state. Valid phones states are defined\n     * by audio_mode_t */\n    void (*set_phone_state)(struct audio_policy *pol, audio_mode_t state);\n\n    /* deprecated, never called (was \"indicate a change in ringer mode\") */\n    void (*set_ringer_mode)(struct audio_policy *pol, uint32_t mode,\n                            uint32_t mask);\n\n    /* force using a specific device category for the specified usage */\n    void (*set_force_use)(struct audio_policy *pol,\n                          audio_policy_force_use_t usage,\n                          audio_policy_forced_cfg_t config);\n\n    /* retrieve current device category forced for a given usage */\n    audio_policy_forced_cfg_t (*get_force_use)(const struct audio_policy *pol,\n                                               audio_policy_force_use_t usage);\n\n    /* if can_mute is true, then audio streams that are marked ENFORCED_AUDIBLE\n     * can still be muted. */\n    void (*set_can_mute_enforced_audible)(struct audio_policy *pol,\n                                          bool can_mute);\n\n    /* check proper initialization */\n    int (*init_check)(const struct audio_policy *pol);\n\n    /*\n     * Audio routing query functions\n     */\n\n    /* request an output appropriate for playback of the supplied stream type and\n     * parameters */\n    audio_io_handle_t (*get_output)(struct audio_policy *pol,\n                                    audio_stream_type_t stream,\n                                    uint32_t samplingRate,\n                                    audio_format_t format,\n                                    audio_channel_mask_t channelMask,\n                                    audio_output_flags_t flags,\n                                    const audio_offload_info_t *offloadInfo);\n\n    /* indicates to the audio policy manager that the output starts being used\n     * by corresponding stream. */\n    int (*start_output)(struct audio_policy *pol,\n                        audio_io_handle_t output,\n                        audio_stream_type_t stream,\n                        int session);\n\n    /* indicates to the audio policy manager that the output stops being used\n     * by corresponding stream. */\n    int (*stop_output)(struct audio_policy *pol,\n                       audio_io_handle_t output,\n                       audio_stream_type_t stream,\n                       int session);\n\n    /* releases the output. */\n    void (*release_output)(struct audio_policy *pol, audio_io_handle_t output);\n\n    /* request an input appropriate for record from the supplied device with\n     * supplied parameters. */\n    audio_io_handle_t (*get_input)(struct audio_policy *pol, audio_source_t inputSource,\n                                   uint32_t samplingRate,\n                                   audio_format_t format,\n                                   audio_channel_mask_t channelMask,\n                                   audio_in_acoustics_t acoustics);\n\n    /* indicates to the audio policy manager that the input starts being used */\n    int (*start_input)(struct audio_policy *pol, audio_io_handle_t input);\n\n    /* indicates to the audio policy manager that the input stops being used. */\n    int (*stop_input)(struct audio_policy *pol, audio_io_handle_t input);\n\n    /* releases the input. */\n    void (*release_input)(struct audio_policy *pol, audio_io_handle_t input);\n\n    /*\n     * volume control functions\n     */\n\n    /* initialises stream volume conversion parameters by specifying volume\n     * index range. The index range for each stream is defined by AudioService. */\n    void (*init_stream_volume)(struct audio_policy *pol,\n                               audio_stream_type_t stream,\n                               int index_min,\n                               int index_max);\n\n    /* sets the new stream volume at a level corresponding to the supplied\n     * index. The index is within the range specified by init_stream_volume() */\n    int (*set_stream_volume_index)(struct audio_policy *pol,\n                                   audio_stream_type_t stream,\n                                   int index);\n\n    /* retrieve current volume index for the specified stream */\n    int (*get_stream_volume_index)(const struct audio_policy *pol,\n                                   audio_stream_type_t stream,\n                                   int *index);\n\n    /* sets the new stream volume at a level corresponding to the supplied\n     * index for the specified device.\n     * The index is within the range specified by init_stream_volume() */\n    int (*set_stream_volume_index_for_device)(struct audio_policy *pol,\n                                   audio_stream_type_t stream,\n                                   int index,\n                                   audio_devices_t device);\n\n    /* retrieve current volume index for the specified stream for the specified device */\n    int (*get_stream_volume_index_for_device)(const struct audio_policy *pol,\n                                   audio_stream_type_t stream,\n                                   int *index,\n                                   audio_devices_t device);\n\n    /* return the strategy corresponding to a given stream type */\n    uint32_t (*get_strategy_for_stream)(const struct audio_policy *pol,\n                                        audio_stream_type_t stream);\n\n    /* return the enabled output devices for the given stream type */\n    audio_devices_t (*get_devices_for_stream)(const struct audio_policy *pol,\n                                       audio_stream_type_t stream);\n\n    /* Audio effect management */\n    audio_io_handle_t (*get_output_for_effect)(struct audio_policy *pol,\n                                            const struct effect_descriptor_s *desc);\n\n    int (*register_effect)(struct audio_policy *pol,\n                           const struct effect_descriptor_s *desc,\n                           audio_io_handle_t output,\n                           uint32_t strategy,\n                           int session,\n                           int id);\n\n    int (*unregister_effect)(struct audio_policy *pol, int id);\n\n    int (*set_effect_enabled)(struct audio_policy *pol, int id, bool enabled);\n\n    bool (*is_stream_active)(const struct audio_policy *pol,\n            audio_stream_type_t stream,\n            uint32_t in_past_ms);\n\n    bool (*is_stream_active_remotely)(const struct audio_policy *pol,\n            audio_stream_type_t stream,\n            uint32_t in_past_ms);\n\n    bool (*is_source_active)(const struct audio_policy *pol,\n            audio_source_t source);\n\n    /* dump state */\n    int (*dump)(const struct audio_policy *pol, int fd);\n\n    /* check if offload is possible for given sample rate, bitrate, duration, ... */\n    bool (*is_offload_supported)(const struct audio_policy *pol,\n                                const audio_offload_info_t *info);\n};\n\n\nstruct audio_policy_service_ops {\n    /*\n     * Audio output Control functions\n     */\n\n    /* Opens an audio output with the requested parameters.\n     *\n     * The parameter values can indicate to use the default values in case the\n     * audio policy manager has no specific requirements for the output being\n     * opened.\n     *\n     * When the function returns, the parameter values reflect the actual\n     * values used by the audio hardware output stream.\n     *\n     * The audio policy manager can check if the proposed parameters are\n     * suitable or not and act accordingly.\n     */\n    audio_io_handle_t (*open_output)(void *service,\n                                     audio_devices_t *pDevices,\n                                     uint32_t *pSamplingRate,\n                                     audio_format_t *pFormat,\n                                     audio_channel_mask_t *pChannelMask,\n                                     uint32_t *pLatencyMs,\n                                     audio_output_flags_t flags);\n\n    /* creates a special output that is duplicated to the two outputs passed as\n     * arguments. The duplication is performed by\n     * a special mixer thread in the AudioFlinger.\n     */\n    audio_io_handle_t (*open_duplicate_output)(void *service,\n                                               audio_io_handle_t output1,\n                                               audio_io_handle_t output2);\n\n    /* closes the output stream */\n    int (*close_output)(void *service, audio_io_handle_t output);\n\n    /* suspends the output.\n     *\n     * When an output is suspended, the corresponding audio hardware output\n     * stream is placed in standby and the AudioTracks attached to the mixer\n     * thread are still processed but the output mix is discarded.\n     */\n    int (*suspend_output)(void *service, audio_io_handle_t output);\n\n    /* restores a suspended output. */\n    int (*restore_output)(void *service, audio_io_handle_t output);\n\n    /* */\n    /* Audio input Control functions */\n    /* */\n\n    /* opens an audio input\n     * deprecated - new implementations should use open_input_on_module,\n     * and the acoustics parameter is ignored\n     */\n    audio_io_handle_t (*open_input)(void *service,\n                                    audio_devices_t *pDevices,\n                                    uint32_t *pSamplingRate,\n                                    audio_format_t *pFormat,\n                                    audio_channel_mask_t *pChannelMask,\n                                    audio_in_acoustics_t acoustics);\n\n    /* closes an audio input */\n    int (*close_input)(void *service, audio_io_handle_t input);\n\n    /* */\n    /* misc control functions */\n    /* */\n\n    /* set a stream volume for a particular output.\n     *\n     * For the same user setting, a given stream type can have different\n     * volumes for each output (destination device) it is attached to.\n     */\n    int (*set_stream_volume)(void *service,\n                             audio_stream_type_t stream,\n                             float volume,\n                             audio_io_handle_t output,\n                             int delay_ms);\n\n    /* invalidate a stream type, causing a reroute to an unspecified new output */\n    int (*invalidate_stream)(void *service,\n                             audio_stream_type_t stream);\n\n    /* function enabling to send proprietary informations directly from audio\n     * policy manager to audio hardware interface. */\n    void (*set_parameters)(void *service,\n                           audio_io_handle_t io_handle,\n                           const char *kv_pairs,\n                           int delay_ms);\n\n    /* function enabling to receive proprietary informations directly from\n     * audio hardware interface to audio policy manager.\n     *\n     * Returns a pointer to a heap allocated string. The caller is responsible\n     * for freeing the memory for it using free().\n     */\n\n    char * (*get_parameters)(void *service, audio_io_handle_t io_handle,\n                             const char *keys);\n\n    /* request the playback of a tone on the specified stream.\n     * used for instance to replace notification sounds when playing over a\n     * telephony device during a phone call.\n     */\n    int (*start_tone)(void *service,\n                      audio_policy_tone_t tone,\n                      audio_stream_type_t stream);\n\n    int (*stop_tone)(void *service);\n\n    /* set down link audio volume. */\n    int (*set_voice_volume)(void *service,\n                            float volume,\n                            int delay_ms);\n\n    /* move effect to the specified output */\n    int (*move_effects)(void *service,\n                        int session,\n                        audio_io_handle_t src_output,\n                        audio_io_handle_t dst_output);\n\n    /* loads an audio hw module.\n     *\n     * The module name passed is the base name of the HW module library, e.g \"primary\" or \"a2dp\".\n     * The function returns a handle on the module that will be used to specify a particular\n     * module when calling open_output_on_module() or open_input_on_module()\n     */\n    audio_module_handle_t (*load_hw_module)(void *service,\n                                              const char *name);\n\n    /* Opens an audio output on a particular HW module.\n     *\n     * Same as open_output() but specifying a specific HW module on which the output must be opened.\n     */\n    audio_io_handle_t (*open_output_on_module)(void *service,\n                                     audio_module_handle_t module,\n                                     audio_devices_t *pDevices,\n                                     uint32_t *pSamplingRate,\n                                     audio_format_t *pFormat,\n                                     audio_channel_mask_t *pChannelMask,\n                                     uint32_t *pLatencyMs,\n                                     audio_output_flags_t flags,\n                                     const audio_offload_info_t *offloadInfo);\n\n    /* Opens an audio input on a particular HW module.\n     *\n     * Same as open_input() but specifying a specific HW module on which the input must be opened.\n     * Also removed deprecated acoustics parameter\n     */\n    audio_io_handle_t (*open_input_on_module)(void *service,\n                                    audio_module_handle_t module,\n                                    audio_devices_t *pDevices,\n                                    uint32_t *pSamplingRate,\n                                    audio_format_t *pFormat,\n                                    audio_channel_mask_t *pChannelMask);\n\n};\n\n/**********************************************************************/\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\ntypedef struct audio_policy_module {\n    struct hw_module_t common;\n} audio_policy_module_t;\n\nstruct audio_policy_device {\n    /**\n     * Common methods of the audio policy device.  This *must* be the first member of\n     * audio_policy_device as users of this structure will cast a hw_device_t to\n     * audio_policy_device pointer in contexts where it's known the hw_device_t references an\n     * audio_policy_device.\n     */\n    struct hw_device_t common;\n\n    int (*create_audio_policy)(const struct audio_policy_device *device,\n                               struct audio_policy_service_ops *aps_ops,\n                               void *service,\n                               struct audio_policy **ap);\n\n    int (*destroy_audio_policy)(const struct audio_policy_device *device,\n                                struct audio_policy *ap);\n};\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int audio_policy_dev_open(const hw_module_t* module,\n                                    struct audio_policy_device** device)\n{\n    return module->methods->open(module, AUDIO_POLICY_INTERFACE,\n                                 (hw_device_t**)device);\n}\n\nstatic inline int audio_policy_dev_close(struct audio_policy_device* device)\n{\n    return device->common.close(&device->common);\n}\n\n\n__END_DECLS\n\n#endif  // ANDROID_AUDIO_POLICY_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bluetooth.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BLUETOOTH_H\n#define ANDROID_INCLUDE_BLUETOOTH_H\n\n#include <stdbool.h>\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n/**\n * The Bluetooth Hardware Module ID\n */\n\n#define BT_HARDWARE_MODULE_ID \"bluetooth\"\n#define BT_STACK_MODULE_ID \"bluetooth\"\n#define BT_STACK_TEST_MODULE_ID \"bluetooth_test\"\n\n\n/* Bluetooth profile interface IDs */\n\n#define BT_PROFILE_HANDSFREE_ID \"handsfree\"\n#define BT_PROFILE_HANDSFREE_CLIENT_ID \"handsfree_client\"\n#define BT_PROFILE_ADVANCED_AUDIO_ID \"a2dp\"\n#define BT_PROFILE_ADVANCED_AUDIO_SINK_ID \"a2dp_sink\"\n#define BT_PROFILE_HEALTH_ID \"health\"\n#define BT_PROFILE_SOCKETS_ID \"socket\"\n#define BT_PROFILE_HIDHOST_ID \"hidhost\"\n#define BT_PROFILE_HIDDEV_ID \"hiddev\"\n#define BT_PROFILE_PAN_ID \"pan\"\n#define BT_PROFILE_MAP_CLIENT_ID \"map_client\"\n#define BT_PROFILE_SDP_CLIENT_ID \"sdp\"\n#define BT_PROFILE_GATT_ID \"gatt\"\n#define BT_PROFILE_AV_RC_ID \"avrcp\"\n#define WIPOWER_PROFILE_ID \"wipower\"\n#define BT_PROFILE_AV_RC_CTRL_ID \"avrcp_ctrl\"\n\n/** Bluetooth Address */\ntypedef struct {\n    uint8_t address[6];\n} __attribute__((packed))bt_bdaddr_t;\n\n/** Bluetooth Device Name */\ntypedef struct {\n    uint8_t name[249];\n} __attribute__((packed))bt_bdname_t;\n\n/** Bluetooth Adapter Visibility Modes*/\ntypedef enum {\n    BT_SCAN_MODE_NONE,\n    BT_SCAN_MODE_CONNECTABLE,\n    BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE\n} bt_scan_mode_t;\n\n/** Bluetooth Adapter State */\ntypedef enum {\n    BT_STATE_OFF,\n    BT_STATE_ON\n}   bt_state_t;\n\n/** Bluetooth Error Status */\n/** We need to build on this */\n\ntypedef enum {\n    BT_STATUS_SUCCESS,\n    BT_STATUS_FAIL,\n    BT_STATUS_NOT_READY,\n    BT_STATUS_NOMEM,\n    BT_STATUS_BUSY,\n    BT_STATUS_DONE,        /* request already completed */\n    BT_STATUS_UNSUPPORTED,\n    BT_STATUS_PARM_INVALID,\n    BT_STATUS_UNHANDLED,\n    BT_STATUS_AUTH_FAILURE,\n    BT_STATUS_RMT_DEV_DOWN,\n    BT_STATUS_AUTH_REJECTED\n\n} bt_status_t;\n\n/** Bluetooth PinKey Code */\ntypedef struct {\n    uint8_t pin[16];\n} __attribute__((packed))bt_pin_code_t;\n\ntypedef struct {\n    uint8_t status;\n    uint8_t ctrl_state;     /* stack reported state */\n    uint64_t tx_time;       /* in ms */\n    uint64_t rx_time;       /* in ms */\n    uint64_t idle_time;     /* in ms */\n    uint64_t energy_used;   /* a product of mA, V and ms */\n} __attribute__((packed))bt_activity_energy_info;\n\n/** Bluetooth Adapter Discovery state */\ntypedef enum {\n    BT_DISCOVERY_STOPPED,\n    BT_DISCOVERY_STARTED\n} bt_discovery_state_t;\n\n/** Bluetooth ACL connection state */\ntypedef enum {\n    BT_ACL_STATE_CONNECTED,\n    BT_ACL_STATE_DISCONNECTED\n} bt_acl_state_t;\n\n/** Bluetooth 128-bit UUID */\ntypedef struct {\n   uint8_t uu[16];\n} bt_uuid_t;\n\n/** Bluetooth SDP service record */\ntypedef struct\n{\n   bt_uuid_t uuid;\n   uint16_t channel;\n   char name[256]; // what's the maximum length\n} bt_service_record_t;\n\n\n/** Bluetooth Remote Version info */\ntypedef struct\n{\n   int version;\n   int sub_ver;\n   int manufacturer;\n} bt_remote_version_t;\n\ntypedef struct\n{\n    uint16_t version_supported;\n    uint8_t local_privacy_enabled;\n    uint8_t max_adv_instance;\n    uint8_t rpa_offload_supported;\n    uint8_t max_irk_list_size;\n    uint8_t max_adv_filter_supported;\n    uint8_t activity_energy_info_supported;\n    uint16_t scan_result_storage_size;\n    uint16_t total_trackable_advertisers;\n    bool extended_scan_support;\n    bool debug_logging_supported;\n}bt_local_le_features_t;\n\n/* Bluetooth Adapter and Remote Device property types */\ntypedef enum {\n    /* Properties common to both adapter and remote device */\n    /**\n     * Description - Bluetooth Device Name\n     * Access mode - Adapter name can be GET/SET. Remote device can be GET\n     * Data type   - bt_bdname_t\n     */\n    BT_PROPERTY_BDNAME = 0x1,\n    /**\n     * Description - Bluetooth Device Address\n     * Access mode - Only GET.\n     * Data type   - bt_bdaddr_t\n     */\n    BT_PROPERTY_BDADDR,\n    /**\n     * Description - Bluetooth Service 128-bit UUIDs\n     * Access mode - Only GET.\n     * Data type   - Array of bt_uuid_t (Array size inferred from property length).\n     */\n    BT_PROPERTY_UUIDS,\n    /**\n     * Description - Bluetooth Class of Device as found in Assigned Numbers\n     * Access mode - Only GET.\n     * Data type   - uint32_t.\n     */\n    BT_PROPERTY_CLASS_OF_DEVICE,\n    /**\n     * Description - Device Type - BREDR, BLE or DUAL Mode\n     * Access mode - Only GET.\n     * Data type   - bt_device_type_t\n     */\n    BT_PROPERTY_TYPE_OF_DEVICE,\n    /**\n     * Description - Bluetooth Service Record\n     * Access mode - Only GET.\n     * Data type   - bt_service_record_t\n     */\n    BT_PROPERTY_SERVICE_RECORD,\n\n    /* Properties unique to adapter */\n    /**\n     * Description - Bluetooth Adapter scan mode\n     * Access mode - GET and SET\n     * Data type   - bt_scan_mode_t.\n     */\n    BT_PROPERTY_ADAPTER_SCAN_MODE,\n    /**\n     * Description - List of bonded devices\n     * Access mode - Only GET.\n     * Data type   - Array of bt_bdaddr_t of the bonded remote devices\n     *               (Array size inferred from property length).\n     */\n    BT_PROPERTY_ADAPTER_BONDED_DEVICES,\n    /**\n     * Description - Bluetooth Adapter Discovery timeout (in seconds)\n     * Access mode - GET and SET\n     * Data type   - uint32_t\n     */\n    BT_PROPERTY_ADAPTER_DISCOVERY_TIMEOUT,\n\n    /* Properties unique to remote device */\n    /**\n     * Description - User defined friendly name of the remote device\n     * Access mode - GET and SET\n     * Data type   - bt_bdname_t.\n     */\n    BT_PROPERTY_REMOTE_FRIENDLY_NAME,\n    /**\n     * Description - RSSI value of the inquired remote device\n     * Access mode - Only GET.\n     * Data type   - int32_t.\n     */\n    BT_PROPERTY_REMOTE_RSSI,\n    /**\n     * Description - Remote version info\n     * Access mode - SET/GET.\n     * Data type   - bt_remote_version_t.\n     */\n\n    BT_PROPERTY_REMOTE_VERSION_INFO,\n\n    /**\n     * Description - Local LE features\n     * Access mode - GET.\n     * Data type   - bt_local_le_features_t.\n     */\n    BT_PROPERTY_LOCAL_LE_FEATURES,\n\n    BT_PROPERTY_REMOTE_DEVICE_TIMESTAMP = 0xFF,\n} bt_property_type_t;\n\n/** Bluetooth Adapter Property data structure */\ntypedef struct\n{\n    bt_property_type_t type;\n    int len;\n    void *val;\n} bt_property_t;\n\n\n/** Bluetooth Device Type */\ntypedef enum {\n    BT_DEVICE_DEVTYPE_BREDR = 0x1,\n    BT_DEVICE_DEVTYPE_BLE,\n    BT_DEVICE_DEVTYPE_DUAL\n} bt_device_type_t;\n/** Bluetooth Bond state */\ntypedef enum {\n    BT_BOND_STATE_NONE,\n    BT_BOND_STATE_BONDING,\n    BT_BOND_STATE_BONDED\n} bt_bond_state_t;\n\n/** Bluetooth SSP Bonding Variant */\ntypedef enum {\n    BT_SSP_VARIANT_PASSKEY_CONFIRMATION,\n    BT_SSP_VARIANT_PASSKEY_ENTRY,\n    BT_SSP_VARIANT_CONSENT,\n    BT_SSP_VARIANT_PASSKEY_NOTIFICATION\n} bt_ssp_variant_t;\n\n#define BT_MAX_NUM_UUIDS 32\n\n/** Bluetooth Interface callbacks */\n\n/** Bluetooth Enable/Disable Callback. */\ntypedef void (*adapter_state_changed_callback)(bt_state_t state);\n\n/** GET/SET Adapter Properties callback */\n/* TODO: For the GET/SET property APIs/callbacks, we may need a session\n * identifier to associate the call with the callback. This would be needed\n * whenever more than one simultaneous instance of the same adapter_type\n * is get/set.\n *\n * If this is going to be handled in the Java framework, then we do not need\n * to manage sessions here.\n */\ntypedef void (*adapter_properties_callback)(bt_status_t status,\n                                               int num_properties,\n                                               bt_property_t *properties);\n\n/** GET/SET Remote Device Properties callback */\n/** TODO: For remote device properties, do not see a need to get/set\n * multiple properties - num_properties shall be 1\n */\ntypedef void (*remote_device_properties_callback)(bt_status_t status,\n                                                       bt_bdaddr_t *bd_addr,\n                                                       int num_properties,\n                                                       bt_property_t *properties);\n\n/** New device discovered callback */\n/** If EIR data is not present, then BD_NAME and RSSI shall be NULL and -1\n * respectively */\ntypedef void (*device_found_callback)(int num_properties,\n                                         bt_property_t *properties);\n\n/** Discovery state changed callback */\ntypedef void (*discovery_state_changed_callback)(bt_discovery_state_t state);\n\n/** Bluetooth Legacy PinKey Request callback */\ntypedef void (*pin_request_callback)(bt_bdaddr_t *remote_bd_addr,\n                                        bt_bdname_t *bd_name, uint32_t cod, bool min_16_digit);\n\n/** Bluetooth SSP Request callback - Just Works & Numeric Comparison*/\n/** pass_key - Shall be 0 for BT_SSP_PAIRING_VARIANT_CONSENT &\n *  BT_SSP_PAIRING_PASSKEY_ENTRY */\n/* TODO: Passkey request callback shall not be needed for devices with display\n * capability. We still need support this in the stack for completeness */\ntypedef void (*ssp_request_callback)(bt_bdaddr_t *remote_bd_addr,\n                                        bt_bdname_t *bd_name,\n                                        uint32_t cod,\n                                        bt_ssp_variant_t pairing_variant,\n                                     uint32_t pass_key);\n\n/** Bluetooth Bond state changed callback */\n/* Invoked in response to create_bond, cancel_bond or remove_bond */\ntypedef void (*bond_state_changed_callback)(bt_status_t status,\n                                               bt_bdaddr_t *remote_bd_addr,\n                                               bt_bond_state_t state);\n\n/** Bluetooth ACL connection state changed callback */\ntypedef void (*acl_state_changed_callback)(bt_status_t status, bt_bdaddr_t *remote_bd_addr,\n                                            bt_acl_state_t state);\n\ntypedef enum {\n    ASSOCIATE_JVM,\n    DISASSOCIATE_JVM\n} bt_cb_thread_evt;\n\n/** Thread Associate/Disassociate JVM Callback */\n/* Callback that is invoked by the callback thread to allow upper layer to attach/detach to/from\n * the JVM */\ntypedef void (*callback_thread_event)(bt_cb_thread_evt evt);\n\n/** Bluetooth Test Mode Callback */\n/* Receive any HCI event from controller. Must be in DUT Mode for this callback to be received */\ntypedef void (*dut_mode_recv_callback)(uint16_t opcode, uint8_t *buf, uint8_t len);\n\n/** Bluetooth HCI event Callback */\n/* Receive any HCI event from controller for raw commands */\ntypedef void (*hci_event_recv_callback)(uint8_t event_code, uint8_t *buf, uint8_t len);\n\n/* LE Test mode callbacks\n* This callback shall be invoked whenever the le_tx_test, le_rx_test or le_test_end is invoked\n* The num_packets is valid only for le_test_end command */\ntypedef void (*le_test_mode_callback)(bt_status_t status, uint16_t num_packets);\n\n/** Callback invoked when energy details are obtained */\n/* Ctrl_state-Current controller state-Active-1,scan-2,or idle-3 state as defined by HCI spec.\n * If the ctrl_state value is 0, it means the API call failed\n * Time values-In milliseconds as returned by the controller\n * Energy used-Value as returned by the controller\n * Status-Provides the status of the read_energy_info API call */\ntypedef void (*energy_info_callback)(bt_activity_energy_info *energy_info);\n\n/** TODO: Add callbacks for Link Up/Down and other generic\n  *  notifications/callbacks */\n\n/** Bluetooth DM callback structure. */\ntypedef struct {\n    /** set to sizeof(bt_callbacks_t) */\n    size_t size;\n    adapter_state_changed_callback adapter_state_changed_cb;\n    adapter_properties_callback adapter_properties_cb;\n    remote_device_properties_callback remote_device_properties_cb;\n    device_found_callback device_found_cb;\n    discovery_state_changed_callback discovery_state_changed_cb;\n    pin_request_callback pin_request_cb;\n    ssp_request_callback ssp_request_cb;\n    bond_state_changed_callback bond_state_changed_cb;\n    acl_state_changed_callback acl_state_changed_cb;\n    callback_thread_event thread_evt_cb;\n    dut_mode_recv_callback dut_mode_recv_cb;\n    le_test_mode_callback le_test_mode_cb;\n    energy_info_callback energy_info_cb;\n    hci_event_recv_callback hci_event_recv_cb;\n} bt_callbacks_t;\n\ntypedef void (*alarm_cb)(void *data);\ntypedef bool (*set_wake_alarm_callout)(uint64_t delay_millis, bool should_wake, alarm_cb cb, void *data);\ntypedef int (*acquire_wake_lock_callout)(const char *lock_name);\ntypedef int (*release_wake_lock_callout)(const char *lock_name);\n\n/** The set of functions required by bluedroid to set wake alarms and\n  * grab wake locks. This struct is passed into the stack through the\n  * |set_os_callouts| function on |bt_interface_t|.\n  */\ntypedef struct {\n  /* set to sizeof(bt_os_callouts_t) */\n  size_t size;\n\n  set_wake_alarm_callout set_wake_alarm;\n  acquire_wake_lock_callout acquire_wake_lock;\n  release_wake_lock_callout release_wake_lock;\n} bt_os_callouts_t;\n\n/** NOTE: By default, no profiles are initialized at the time of init/enable.\n *  Whenever the application invokes the 'init' API of a profile, then one of\n *  the following shall occur:\n *\n *    1.) If Bluetooth is not enabled, then the Bluetooth core shall mark the\n *        profile as enabled. Subsequently, when the application invokes the\n *        Bluetooth 'enable', as part of the enable sequence the profile that were\n *        marked shall be enabled by calling appropriate stack APIs. The\n *        'adapter_properties_cb' shall return the list of UUIDs of the\n *        enabled profiles.\n *\n *    2.) If Bluetooth is enabled, then the Bluetooth core shall invoke the stack\n *        profile API to initialize the profile and trigger a\n *        'adapter_properties_cb' with the current list of UUIDs including the\n *        newly added profile's UUID.\n *\n *   The reverse shall occur whenever the profile 'cleanup' APIs are invoked\n */\n\n/** Represents the standard Bluetooth DM interface. */\ntypedef struct {\n    /** set to sizeof(bt_interface_t) */\n    size_t size;\n    /**\n     * Opens the interface and provides the callback routines\n     * to the implemenation of this interface.\n     */\n    int (*init)(bt_callbacks_t* callbacks );\n\n    /** Enable Bluetooth. */\n    int (*enable)(bool guest_mode);\n\n    /** Disable Bluetooth. */\n    int (*disable)(void);\n\n    /** Closes the interface. */\n    void (*cleanup)(void);\n\n    /** SSR cleanup. */\n    void (*ssrcleanup)(void);\n\n    /** Get all Bluetooth Adapter properties at init */\n    int (*get_adapter_properties)(void);\n\n    /** Get Bluetooth Adapter property of 'type' */\n    int (*get_adapter_property)(bt_property_type_t type);\n\n    /** Set Bluetooth Adapter property of 'type' */\n    /* Based on the type, val shall be one of\n     * bt_bdaddr_t or bt_bdname_t or bt_scanmode_t etc\n     */\n    int (*set_adapter_property)(const bt_property_t *property);\n\n    /** Get all Remote Device properties */\n    int (*get_remote_device_properties)(bt_bdaddr_t *remote_addr);\n\n    /** Get Remote Device property of 'type' */\n    int (*get_remote_device_property)(bt_bdaddr_t *remote_addr,\n                                      bt_property_type_t type);\n\n    /** Set Remote Device property of 'type' */\n    int (*set_remote_device_property)(bt_bdaddr_t *remote_addr,\n                                      const bt_property_t *property);\n\n    /** Get Remote Device's service record  for the given UUID */\n    int (*get_remote_service_record)(bt_bdaddr_t *remote_addr,\n                                     bt_uuid_t *uuid);\n\n    /** Start SDP to get remote services */\n    int (*get_remote_services)(bt_bdaddr_t *remote_addr);\n\n    /** Start Discovery */\n    int (*start_discovery)(void);\n\n    /** Cancel Discovery */\n    int (*cancel_discovery)(void);\n\n    /** Create Bluetooth Bonding */\n    int (*create_bond)(const bt_bdaddr_t *bd_addr, int transport);\n\n    /** Remove Bond */\n    int (*remove_bond)(const bt_bdaddr_t *bd_addr);\n\n    /** Cancel Bond */\n    int (*cancel_bond)(const bt_bdaddr_t *bd_addr);\n\n    /**\n     * Get the connection status for a given remote device.\n     * return value of 0 means the device is not connected,\n     * non-zero return status indicates an active connection.\n     */\n    int (*get_connection_state)(const bt_bdaddr_t *bd_addr);\n\n    /** BT Legacy PinKey Reply */\n    /** If accept==FALSE, then pin_len and pin_code shall be 0x0 */\n    int (*pin_reply)(const bt_bdaddr_t *bd_addr, uint8_t accept,\n                     uint8_t pin_len, bt_pin_code_t *pin_code);\n\n    /** BT SSP Reply - Just Works, Numeric Comparison and Passkey\n     * passkey shall be zero for BT_SSP_VARIANT_PASSKEY_COMPARISON &\n     * BT_SSP_VARIANT_CONSENT\n     * For BT_SSP_VARIANT_PASSKEY_ENTRY, if accept==FALSE, then passkey\n     * shall be zero */\n    int (*ssp_reply)(const bt_bdaddr_t *bd_addr, bt_ssp_variant_t variant,\n                     uint8_t accept, uint32_t passkey);\n\n    /** Get Bluetooth profile interface */\n    const void* (*get_profile_interface) (const char *profile_id);\n\n    /** Bluetooth Test Mode APIs - Bluetooth must be enabled for these APIs */\n    /* Configure DUT Mode - Use this mode to enter/exit DUT mode */\n    int (*dut_mode_configure)(uint8_t enable);\n\n    /* Send any test HCI (vendor-specific) command to the controller. Must be in DUT Mode */\n    int (*dut_mode_send)(uint16_t opcode, uint8_t *buf, uint8_t len);\n\n    /* Send any test HCI command to the controller. */\n    int (*hci_cmd_send)(uint16_t opcode, uint8_t *buf, uint8_t len);\n\n    /** BLE Test Mode APIs */\n    /* opcode MUST be one of: LE_Receiver_Test, LE_Transmitter_Test, LE_Test_End */\n    int (*le_test_mode)(uint16_t opcode, uint8_t *buf, uint8_t len);\n\n    /* enable or disable bluetooth HCI snoop log */\n    int (*config_hci_snoop_log)(uint8_t enable);\n\n    /** Sets the OS call-out functions that bluedroid needs for alarms and wake locks.\n      * This should be called immediately after a successful |init|.\n      */\n    int (*set_os_callouts)(bt_os_callouts_t *callouts);\n\n    /** Read Energy info details - return value indicates BT_STATUS_SUCCESS or BT_STATUS_NOT_READY\n      * Success indicates that the VSC command was sent to controller\n      */\n    int (*read_energy_info)();\n\n    /**\n     * Native support for dumpsys function\n     * Function is synchronous and |fd| is owned by caller.\n     */\n    void (*dump)(int fd);\n\n    /**\n     * Clear /data/misc/bt_config.conf and erase all stored connections\n     */\n    int (*config_clear)(void);\n\n    /** BT stack Test interface */\n    const void* (*get_testapp_interface)(int test_app_profile);\n\n    /**\n     * Clear (reset) the dynamic portion of the device interoperability database.\n     */\n    void (*interop_database_clear)(void);\n\n    /**\n     * Add a new device interoperability workaround for a remote device whose\n     * first |len| bytes of the its device address match |addr|.\n     * NOTE: |feature| has to match an item defined in interop_feature_t (interop.h).\n     */\n    void (*interop_database_add)(uint16_t feature, const bt_bdaddr_t *addr, size_t len);\n} bt_interface_t;\n\n/** TODO: Need to add APIs for Service Discovery, Service authorization and\n  *       connection management. Also need to add APIs for configuring\n  *       properties of remote bonded devices such as name, UUID etc. */\n\ntypedef struct {\n    struct hw_device_t common;\n    const bt_interface_t* (*get_bluetooth_interface)();\n} bluetooth_device_t;\n\ntypedef bluetooth_device_t bluetooth_module_t;\n\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BLUETOOTH_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_av.h",
    "content": "/*\n * Copyright (C) 2013-2014, The Linux Foundation. All rights reserved.\n * Not a Contribution.\n *\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_AV_H\n#define ANDROID_INCLUDE_BT_AV_H\n\n__BEGIN_DECLS\n\n/* Bluetooth AV connection states */\ntypedef enum {\n    BTAV_CONNECTION_STATE_DISCONNECTED = 0,\n    BTAV_CONNECTION_STATE_CONNECTING,\n    BTAV_CONNECTION_STATE_CONNECTED,\n    BTAV_CONNECTION_STATE_DISCONNECTING\n} btav_connection_state_t;\n\n/* Bluetooth AV datapath states */\ntypedef enum {\n    BTAV_AUDIO_STATE_REMOTE_SUSPEND = 0,\n    BTAV_AUDIO_STATE_STOPPED,\n    BTAV_AUDIO_STATE_STARTED,\n} btav_audio_state_t;\n\n\n/** Callback for connection state change.\n *  state will have one of the values from btav_connection_state_t\n */\ntypedef void (* btav_connection_state_callback)(btav_connection_state_t state, \n                                                    bt_bdaddr_t *bd_addr);\n\n/** Callback for audiopath state change.\n *  state will have one of the values from btav_audio_state_t\n */\ntypedef void (* btav_audio_state_callback)(btav_audio_state_t state, \n                                               bt_bdaddr_t *bd_addr);\n\n/** Callback for connection priority of device for incoming connection\n * btav_connection_priority_t\n */\ntypedef void (* btav_connection_priority_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for audio configuration change.\n *  Used only for the A2DP sink interface.\n *  state will have one of the values from btav_audio_state_t\n *  sample_rate: sample rate in Hz\n *  channel_count: number of channels (1 for mono, 2 for stereo)\n */\ntypedef void (* btav_audio_config_callback)(bt_bdaddr_t *bd_addr,\n                                                uint32_t sample_rate,\n                                                uint8_t channel_count);\n\n/** Callback for updating apps for A2dp multicast state.\n */\n\ntypedef void (* btav_is_multicast_enabled_callback)(int state);\n\n/*\n * Callback for audio focus request to be used only in\n * case of A2DP Sink. This is required because we are using\n * AudioTrack approach for audio data rendering.\n */\ntypedef void (* btav_audio_focus_request_callback)(bt_bdaddr_t *bd_addr);\n\n/** BT-AV callback structure. */\ntypedef struct {\n    /** set to sizeof(btav_callbacks_t) */\n    size_t      size;\n    btav_connection_state_callback  connection_state_cb;\n    btav_audio_state_callback audio_state_cb;\n    btav_audio_config_callback audio_config_cb;\n    btav_connection_priority_callback connection_priority_cb;\n    btav_is_multicast_enabled_callback multicast_state_cb;\n    btav_audio_focus_request_callback audio_focus_request_cb;\n} btav_callbacks_t;\n\n/** \n * NOTE:\n *\n * 1. AVRCP 1.0 shall be supported initially. AVRCP passthrough commands\n *    shall be handled internally via uinput \n *\n * 2. A2DP data path shall be handled via a socket pipe between the AudioFlinger\n *    android_audio_hw library and the Bluetooth stack.\n * \n */\n/** Represents the standard BT-AV interface.\n *  Used for both the A2DP source and sink interfaces.\n */\ntypedef struct {\n\n    /** set to sizeof(btav_interface_t) */\n    size_t          size;\n    /**\n     * Register the BtAv callbacks\n     */\n    bt_status_t (*init)( btav_callbacks_t* callbacks , int max_a2dp_connections,\n                        int a2dp_multicast_state);\n\n    /** connect to headset */\n    bt_status_t (*connect)( bt_bdaddr_t *bd_addr );\n\n    /** dis-connect from headset */\n    bt_status_t (*disconnect)( bt_bdaddr_t *bd_addr );\n\n    /** Closes the interface. */\n    void  (*cleanup)( void );\n\n    /** Send priority of device to stack*/\n    void (*allow_connection)( int is_valid , bt_bdaddr_t *bd_addr);\n\n    /** Sends Audio Focus State. */\n    void  (*audio_focus_state)( int focus_state );\n} btav_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_AV_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_common_types.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *   http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/******************************************************************************\n *\n *  This file contains constants and definitions that can be used commonly between JNI and stack layer\n *\n ******************************************************************************/\n#ifndef ANDROID_INCLUDE_BT_COMMON_TYPES_H\n#define ANDROID_INCLUDE_BT_COMMON_TYPES_H\n\n#include \"bluetooth.h\"\n\ntypedef struct\n{\n    uint8_t  client_if;\n    uint8_t  filt_index;\n    uint8_t  advertiser_state;\n    uint8_t  advertiser_info_present;\n    uint8_t  addr_type;\n    uint8_t  tx_power;\n    int8_t  rssi_value;\n    uint16_t time_stamp;\n    bt_bdaddr_t bd_addr;\n    uint8_t  adv_pkt_len;\n    uint8_t  *p_adv_pkt_data;\n    uint8_t  scan_rsp_len;\n    uint8_t  *p_scan_rsp_data;\n} btgatt_track_adv_info_t;\n\n#endif  /* ANDROID_INCLUDE_BT_COMMON_TYPES_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_gatt.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_INCLUDE_BT_GATT_H\n#define ANDROID_INCLUDE_BT_GATT_H\n\n#include <stdint.h>\n#include \"bt_gatt_client.h\"\n#include \"bt_gatt_server.h\"\n\n__BEGIN_DECLS\n\n/** BT-GATT callbacks */\ntypedef struct {\n    /** Set to sizeof(btgatt_callbacks_t) */\n    size_t size;\n\n    /** GATT Client callbacks */\n    const btgatt_client_callbacks_t* client;\n\n    /** GATT Server callbacks */\n    const btgatt_server_callbacks_t* server;\n} btgatt_callbacks_t;\n\n/** Represents the standard Bluetooth GATT interface. */\ntypedef struct {\n    /** Set to sizeof(btgatt_interface_t) */\n    size_t          size;\n\n    /**\n     * Initializes the interface and provides callback routines\n     */\n    bt_status_t (*init)( const btgatt_callbacks_t* callbacks );\n\n    /** Closes the interface */\n    void (*cleanup)( void );\n\n    /** Pointer to the GATT client interface methods.*/\n    const btgatt_client_interface_t* client;\n\n    /** Pointer to the GATT server interface methods.*/\n    const btgatt_server_interface_t* server;\n} btgatt_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_GATT_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_gatt_client.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_INCLUDE_BT_GATT_CLIENT_H\n#define ANDROID_INCLUDE_BT_GATT_CLIENT_H\n\n#include <stdint.h>\n#include \"bt_gatt_types.h\"\n#include \"bt_common_types.h\"\n\n__BEGIN_DECLS\n\n/**\n * Buffer sizes for maximum attribute length and maximum read/write\n * operation buffer size.\n */\n#define BTGATT_MAX_ATTR_LEN 600\n\n/** Buffer type for unformatted reads/writes */\ntypedef struct\n{\n    uint8_t             value[BTGATT_MAX_ATTR_LEN];\n    uint16_t            len;\n} btgatt_unformatted_value_t;\n\n/** Parameters for GATT read operations */\ntypedef struct\n{\n    btgatt_srvc_id_t    srvc_id;\n    btgatt_gatt_id_t    char_id;\n    btgatt_gatt_id_t    descr_id;\n    btgatt_unformatted_value_t value;\n    uint16_t            value_type;\n    uint8_t             status;\n} btgatt_read_params_t;\n\n/** Parameters for GATT write operations */\ntypedef struct\n{\n    btgatt_srvc_id_t    srvc_id;\n    btgatt_gatt_id_t    char_id;\n    btgatt_gatt_id_t    descr_id;\n    uint8_t             status;\n} btgatt_write_params_t;\n\n/** Attribute change notification parameters */\ntypedef struct\n{\n    uint8_t             value[BTGATT_MAX_ATTR_LEN];\n    bt_bdaddr_t         bda;\n    btgatt_srvc_id_t    srvc_id;\n    btgatt_gatt_id_t    char_id;\n    uint16_t            len;\n    uint8_t             is_notify;\n} btgatt_notify_params_t;\n\ntypedef struct\n{\n    uint8_t  client_if;\n    uint8_t  action;\n    uint8_t  filt_index;\n    uint16_t feat_seln;\n    uint16_t list_logic_type;\n    uint8_t  filt_logic_type;\n    uint8_t  rssi_high_thres;\n    uint8_t  rssi_low_thres;\n    uint8_t  dely_mode;\n    uint16_t found_timeout;\n    uint16_t lost_timeout;\n    uint8_t  found_timeout_cnt;\n    uint16_t  num_of_tracking_entries;\n} btgatt_filt_param_setup_t;\n\ntypedef struct\n{\n    bt_bdaddr_t        *bda1;\n    bt_uuid_t          *uuid1;\n    uint16_t            u1;\n    uint16_t            u2;\n    uint16_t            u3;\n    uint16_t            u4;\n    uint16_t            u5;\n} btgatt_test_params_t;\n\n/* BT GATT client error codes */\ntypedef enum\n{\n    BT_GATTC_COMMAND_SUCCESS = 0,    /* 0  Command succeeded                 */\n    BT_GATTC_COMMAND_STARTED,        /* 1  Command started OK.               */\n    BT_GATTC_COMMAND_BUSY,           /* 2  Device busy with another command  */\n    BT_GATTC_COMMAND_STORED,         /* 3 request is stored in control block */\n    BT_GATTC_NO_RESOURCES,           /* 4  No resources to issue command     */\n    BT_GATTC_MODE_UNSUPPORTED,       /* 5  Request for 1 or more unsupported modes */\n    BT_GATTC_ILLEGAL_VALUE,          /* 6  Illegal command /parameter value  */\n    BT_GATTC_INCORRECT_STATE,        /* 7  Device in wrong state for request  */\n    BT_GATTC_UNKNOWN_ADDR,           /* 8  Unknown remote BD address         */\n    BT_GATTC_DEVICE_TIMEOUT,         /* 9  Device timeout                    */\n    BT_GATTC_INVALID_CONTROLLER_OUTPUT,/* 10  An incorrect value was received from HCI */\n    BT_GATTC_SECURITY_ERROR,          /* 11 Authorization or security failure or not authorized  */\n    BT_GATTC_DELAYED_ENCRYPTION_CHECK, /*12 Delayed encryption check */\n    BT_GATTC_ERR_PROCESSING           /* 12 Generic error                     */\n} btgattc_error_t;\n\n/** BT-GATT Client callback structure. */\n\n/** Callback invoked in response to register_client */\ntypedef void (*register_client_callback)(int status, int client_if,\n                bt_uuid_t *app_uuid);\n\n/** Callback for scan results */\ntypedef void (*scan_result_callback)(bt_bdaddr_t* bda, int rssi, uint8_t* adv_data);\n\n/** GATT open callback invoked in response to open */\ntypedef void (*connect_callback)(int conn_id, int status, int client_if, bt_bdaddr_t* bda);\n\n/** Callback invoked in response to close */\ntypedef void (*disconnect_callback)(int conn_id, int status,\n                int client_if, bt_bdaddr_t* bda);\n\n/**\n * Invoked in response to search_service when the GATT service search\n * has been completed.\n */\ntypedef void (*search_complete_callback)(int conn_id, int status);\n\n/** Reports GATT services on a remote device */\ntypedef void (*search_result_callback)( int conn_id, btgatt_srvc_id_t *srvc_id);\n\n/** GATT characteristic enumeration result callback */\ntypedef void (*get_characteristic_callback)(int conn_id, int status,\n                btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                int char_prop);\n\n/** GATT descriptor enumeration result callback */\ntypedef void (*get_descriptor_callback)(int conn_id, int status,\n                btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                btgatt_gatt_id_t *descr_id);\n\n/** GATT included service enumeration result callback */\ntypedef void (*get_included_service_callback)(int conn_id, int status,\n                btgatt_srvc_id_t *srvc_id, btgatt_srvc_id_t *incl_srvc_id);\n\n/** Callback invoked in response to [de]register_for_notification */\ntypedef void (*register_for_notification_callback)(int conn_id,\n                int registered, int status, btgatt_srvc_id_t *srvc_id,\n                btgatt_gatt_id_t *char_id);\n\n/**\n * Remote device notification callback, invoked when a remote device sends\n * a notification or indication that a client has registered for.\n */\ntypedef void (*notify_callback)(int conn_id, btgatt_notify_params_t *p_data);\n\n/** Reports result of a GATT read operation */\ntypedef void (*read_characteristic_callback)(int conn_id, int status,\n                btgatt_read_params_t *p_data);\n\n/** GATT write characteristic operation callback */\ntypedef void (*write_characteristic_callback)(int conn_id, int status,\n                btgatt_write_params_t *p_data);\n\n/** GATT execute prepared write callback */\ntypedef void (*execute_write_callback)(int conn_id, int status);\n\n/** Callback invoked in response to read_descriptor */\ntypedef void (*read_descriptor_callback)(int conn_id, int status,\n                btgatt_read_params_t *p_data);\n\n/** Callback invoked in response to write_descriptor */\ntypedef void (*write_descriptor_callback)(int conn_id, int status,\n                btgatt_write_params_t *p_data);\n\n/** Callback triggered in response to read_remote_rssi */\ntypedef void (*read_remote_rssi_callback)(int client_if, bt_bdaddr_t* bda,\n                                          int rssi, int status);\n\n/**\n * Callback indicating the status of a listen() operation\n */\ntypedef void (*listen_callback)(int status, int server_if);\n\n/** Callback invoked when the MTU for a given connection changes */\ntypedef void (*configure_mtu_callback)(int conn_id, int status, int mtu);\n\n/** Callback invoked when a scan filter configuration command has completed */\ntypedef void (*scan_filter_cfg_callback)(int action, int client_if, int status, int filt_type,\n                                         int avbl_space);\n\n/** Callback invoked when scan param has been added, cleared, or deleted */\ntypedef void (*scan_filter_param_callback)(int action, int client_if, int status,\n                                         int avbl_space);\n\n/** Callback invoked when a scan filter configuration command has completed */\ntypedef void (*scan_filter_status_callback)(int enable, int client_if, int status);\n\n/** Callback invoked when multi-adv enable operation has completed */\ntypedef void (*multi_adv_enable_callback)(int client_if, int status);\n\n/** Callback invoked when multi-adv param update operation has completed */\ntypedef void (*multi_adv_update_callback)(int client_if, int status);\n\n/** Callback invoked when multi-adv instance data set operation has completed */\ntypedef void (*multi_adv_data_callback)(int client_if, int status);\n\n/** Callback invoked when multi-adv disable operation has completed */\ntypedef void (*multi_adv_disable_callback)(int client_if, int status);\n\n/**\n * Callback notifying an application that a remote device connection is currently congested\n * and cannot receive any more data. An application should avoid sending more data until\n * a further callback is received indicating the congestion status has been cleared.\n */\ntypedef void (*congestion_callback)(int conn_id, bool congested);\n/** Callback invoked when batchscan storage config operation has completed */\ntypedef void (*batchscan_cfg_storage_callback)(int client_if, int status);\n\n/** Callback invoked when batchscan enable / disable operation has completed */\ntypedef void (*batchscan_enable_disable_callback)(int action, int client_if, int status);\n\n/** Callback invoked when batchscan reports are obtained */\ntypedef void (*batchscan_reports_callback)(int client_if, int status, int report_format,\n                                           int num_records, int data_len, uint8_t* rep_data);\n\n/** Callback invoked when batchscan storage threshold limit is crossed */\ntypedef void (*batchscan_threshold_callback)(int client_if);\n\n/** Track ADV VSE callback invoked when tracked device is found or lost */\ntypedef void (*track_adv_event_callback)(btgatt_track_adv_info_t *p_track_adv_info);\n\n/** Callback invoked when scan parameter setup has completed */\ntypedef void (*scan_parameter_setup_completed_callback)(int client_if,\n                                                        btgattc_error_t status);\n\ntypedef struct {\n    register_client_callback            register_client_cb;\n    scan_result_callback                scan_result_cb;\n    connect_callback                    open_cb;\n    disconnect_callback                 close_cb;\n    search_complete_callback            search_complete_cb;\n    search_result_callback              search_result_cb;\n    get_characteristic_callback         get_characteristic_cb;\n    get_descriptor_callback             get_descriptor_cb;\n    get_included_service_callback       get_included_service_cb;\n    register_for_notification_callback  register_for_notification_cb;\n    notify_callback                     notify_cb;\n    read_characteristic_callback        read_characteristic_cb;\n    write_characteristic_callback       write_characteristic_cb;\n    read_descriptor_callback            read_descriptor_cb;\n    write_descriptor_callback           write_descriptor_cb;\n    execute_write_callback              execute_write_cb;\n    read_remote_rssi_callback           read_remote_rssi_cb;\n    listen_callback                     listen_cb;\n    configure_mtu_callback              configure_mtu_cb;\n    scan_filter_cfg_callback            scan_filter_cfg_cb;\n    scan_filter_param_callback          scan_filter_param_cb;\n    scan_filter_status_callback         scan_filter_status_cb;\n    multi_adv_enable_callback           multi_adv_enable_cb;\n    multi_adv_update_callback           multi_adv_update_cb;\n    multi_adv_data_callback             multi_adv_data_cb;\n    multi_adv_disable_callback          multi_adv_disable_cb;\n    congestion_callback                 congestion_cb;\n    batchscan_cfg_storage_callback      batchscan_cfg_storage_cb;\n    batchscan_enable_disable_callback   batchscan_enb_disable_cb;\n    batchscan_reports_callback          batchscan_reports_cb;\n    batchscan_threshold_callback        batchscan_threshold_cb;\n    track_adv_event_callback            track_adv_event_cb;\n    scan_parameter_setup_completed_callback scan_parameter_setup_completed_cb;\n} btgatt_client_callbacks_t;\n\n/** Represents the standard BT-GATT client interface. */\n\ntypedef struct {\n    /** Registers a GATT client application with the stack */\n    bt_status_t (*register_client)( bt_uuid_t *uuid );\n\n    /** Unregister a client application from the stack */\n    bt_status_t (*unregister_client)(int client_if );\n\n    /** Start or stop LE device scanning */\n    bt_status_t (*scan)( bool start );\n\n    /** Create a connection to a remote LE or dual-mode device */\n    bt_status_t (*connect)( int client_if, const bt_bdaddr_t *bd_addr,\n                         bool is_direct, int transport );\n\n    /** Disconnect a remote device or cancel a pending connection */\n    bt_status_t (*disconnect)( int client_if, const bt_bdaddr_t *bd_addr,\n                    int conn_id);\n\n    /** Start or stop advertisements to listen for incoming connections */\n    bt_status_t (*listen)(int client_if, bool start);\n\n    /** Clear the attribute cache for a given device */\n    bt_status_t (*refresh)( int client_if, const bt_bdaddr_t *bd_addr );\n\n    /**\n     * Enumerate all GATT services on a connected device.\n     * Optionally, the results can be filtered for a given UUID.\n     */\n    bt_status_t (*search_service)(int conn_id, bt_uuid_t *filter_uuid );\n\n    /**\n     * Enumerate included services for a given service.\n     * Set start_incl_srvc_id to NULL to get the first included service.\n     */\n    bt_status_t (*get_included_service)( int conn_id, btgatt_srvc_id_t *srvc_id,\n                                         btgatt_srvc_id_t *start_incl_srvc_id);\n\n    /**\n     * Enumerate characteristics for a given service.\n     * Set start_char_id to NULL to get the first characteristic.\n     */\n    bt_status_t (*get_characteristic)( int conn_id,\n                    btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *start_char_id);\n\n    /**\n     * Enumerate descriptors for a given characteristic.\n     * Set start_descr_id to NULL to get the first descriptor.\n     */\n    bt_status_t (*get_descriptor)( int conn_id,\n                    btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                    btgatt_gatt_id_t *start_descr_id);\n\n    /** Read a characteristic on a remote device */\n    bt_status_t (*read_characteristic)( int conn_id,\n                    btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                    int auth_req );\n\n    /** Write a remote characteristic */\n    bt_status_t (*write_characteristic)(int conn_id,\n                    btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                    int write_type, int len, int auth_req,\n                    char* p_value);\n\n    /** Read the descriptor for a given characteristic */\n    bt_status_t (*read_descriptor)(int conn_id,\n                    btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                    btgatt_gatt_id_t *descr_id, int auth_req);\n\n    /** Write a remote descriptor for a given characteristic */\n    bt_status_t (*write_descriptor)( int conn_id,\n                    btgatt_srvc_id_t *srvc_id, btgatt_gatt_id_t *char_id,\n                    btgatt_gatt_id_t *descr_id, int write_type, int len,\n                    int auth_req, char* p_value);\n\n    /** Execute a prepared write operation */\n    bt_status_t (*execute_write)(int conn_id, int execute);\n\n    /**\n     * Register to receive notifications or indications for a given\n     * characteristic\n     */\n    bt_status_t (*register_for_notification)( int client_if,\n                    const bt_bdaddr_t *bd_addr, btgatt_srvc_id_t *srvc_id,\n                    btgatt_gatt_id_t *char_id);\n\n    /** Deregister a previous request for notifications/indications */\n    bt_status_t (*deregister_for_notification)( int client_if,\n                    const bt_bdaddr_t *bd_addr, btgatt_srvc_id_t *srvc_id,\n                    btgatt_gatt_id_t *char_id);\n\n    /** Request RSSI for a given remote device */\n    bt_status_t (*read_remote_rssi)( int client_if, const bt_bdaddr_t *bd_addr);\n\n    /** Setup scan filter params */\n    bt_status_t (*scan_filter_param_setup)(btgatt_filt_param_setup_t filt_param);\n\n\n    /** Configure a scan filter condition  */\n    bt_status_t (*scan_filter_add_remove)(int client_if, int action, int filt_type,\n                                   int filt_index, int company_id,\n                                   int company_id_mask, const bt_uuid_t *p_uuid,\n                                   const bt_uuid_t *p_uuid_mask, const bt_bdaddr_t *bd_addr,\n                                   char addr_type, int data_len, char* p_data, int mask_len,\n                                   char* p_mask);\n\n    /** Clear all scan filter conditions for specific filter index*/\n    bt_status_t (*scan_filter_clear)(int client_if, int filt_index);\n\n    /** Enable / disable scan filter feature*/\n    bt_status_t (*scan_filter_enable)(int client_if, bool enable);\n\n    /** Determine the type of the remote device (LE, BR/EDR, Dual-mode) */\n    int (*get_device_type)( const bt_bdaddr_t *bd_addr );\n\n    /** Set the advertising data or scan response data */\n    bt_status_t (*set_adv_data)(int client_if, bool set_scan_rsp, bool include_name,\n                    bool include_txpower, int min_interval, int max_interval, int appearance,\n                    uint16_t manufacturer_len, char* manufacturer_data,\n                    uint16_t service_data_len, char* service_data,\n                    uint16_t service_uuid_len, char* service_uuid);\n\n    /** Configure the MTU for a given connection */\n    bt_status_t (*configure_mtu)(int conn_id, int mtu);\n\n    /** Request a connection parameter update */\n    bt_status_t (*conn_parameter_update)(const bt_bdaddr_t *bd_addr, int min_interval,\n                    int max_interval, int latency, int timeout);\n\n    /** Sets the LE scan interval and window in units of N*0.625 msec */\n    bt_status_t (*set_scan_parameters)(int client_if, int scan_interval, int scan_window);\n\n    /* Setup the parameters as per spec, user manual specified values and enable multi ADV */\n    bt_status_t (*multi_adv_enable)(int client_if, int min_interval,int max_interval,int adv_type,\n                 int chnl_map, int tx_power, int timeout_s);\n\n    /* Update the parameters as per spec, user manual specified values and restart multi ADV */\n    bt_status_t (*multi_adv_update)(int client_if, int min_interval,int max_interval,int adv_type,\n                 int chnl_map, int tx_power, int timeout_s);\n\n    /* Setup the data for the specified instance */\n    bt_status_t (*multi_adv_set_inst_data)(int client_if, bool set_scan_rsp, bool include_name,\n                    bool incl_txpower, int appearance, int manufacturer_len,\n                    char* manufacturer_data, int service_data_len,\n                    char* service_data, int service_uuid_len, char* service_uuid);\n\n    /* Disable the multi adv instance */\n    bt_status_t (*multi_adv_disable)(int client_if);\n\n    /* Configure the batchscan storage */\n    bt_status_t (*batchscan_cfg_storage)(int client_if, int batch_scan_full_max,\n        int batch_scan_trunc_max, int batch_scan_notify_threshold);\n\n    /* Enable batchscan */\n    bt_status_t (*batchscan_enb_batch_scan)(int client_if, int scan_mode,\n        int scan_interval, int scan_window, int addr_type, int discard_rule);\n\n    /* Disable batchscan */\n    bt_status_t (*batchscan_dis_batch_scan)(int client_if);\n\n    /* Read out batchscan reports */\n    bt_status_t (*batchscan_read_reports)(int client_if, int scan_mode);\n\n    /** Test mode interface */\n    bt_status_t (*test_command)( int command, btgatt_test_params_t* params);\n\n} btgatt_client_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_GATT_CLIENT_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_gatt_server.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_INCLUDE_BT_GATT_SERVER_H\n#define ANDROID_INCLUDE_BT_GATT_SERVER_H\n\n#include <stdint.h>\n\n#include \"bt_gatt_types.h\"\n\n__BEGIN_DECLS\n\n/** GATT value type used in response to remote read requests */\ntypedef struct\n{\n    uint8_t           value[BTGATT_MAX_ATTR_LEN];\n    uint16_t          handle;\n    uint16_t          offset;\n    uint16_t          len;\n    uint8_t           auth_req;\n} btgatt_value_t;\n\n/** GATT remote read request response type */\ntypedef union\n{\n    btgatt_value_t attr_value;\n    uint16_t            handle;\n} btgatt_response_t;\n\n/** BT-GATT Server callback structure. */\n\n/** Callback invoked in response to register_server */\ntypedef void (*register_server_callback)(int status, int server_if,\n                bt_uuid_t *app_uuid);\n\n/** Callback indicating that a remote device has connected or been disconnected */\ntypedef void (*connection_callback)(int conn_id, int server_if, int connected,\n                                    bt_bdaddr_t *bda);\n\n/** Callback invoked in response to create_service */\ntypedef void (*service_added_callback)(int status, int server_if,\n                btgatt_srvc_id_t *srvc_id, int srvc_handle);\n\n/** Callback indicating that an included service has been added to a service */\ntypedef void (*included_service_added_callback)(int status, int server_if,\n                int srvc_handle, int incl_srvc_handle);\n\n/** Callback invoked when a characteristic has been added to a service */\ntypedef void (*characteristic_added_callback)(int status, int server_if,\n                bt_uuid_t *uuid, int srvc_handle, int char_handle);\n\n/** Callback invoked when a descriptor has been added to a characteristic */\ntypedef void (*descriptor_added_callback)(int status, int server_if,\n                bt_uuid_t *uuid, int srvc_handle, int descr_handle);\n\n/** Callback invoked in response to start_service */\ntypedef void (*service_started_callback)(int status, int server_if,\n                                         int srvc_handle);\n\n/** Callback invoked in response to stop_service */\ntypedef void (*service_stopped_callback)(int status, int server_if,\n                                         int srvc_handle);\n\n/** Callback triggered when a service has been deleted */\ntypedef void (*service_deleted_callback)(int status, int server_if,\n                                         int srvc_handle);\n\n/**\n * Callback invoked when a remote device has requested to read a characteristic\n * or descriptor. The application must respond by calling send_response\n */\ntypedef void (*request_read_callback)(int conn_id, int trans_id, bt_bdaddr_t *bda,\n                                      int attr_handle, int offset, bool is_long);\n\n/**\n * Callback invoked when a remote device has requested to write to a\n * characteristic or descriptor.\n */\ntypedef void (*request_write_callback)(int conn_id, int trans_id, bt_bdaddr_t *bda,\n                                       int attr_handle, int offset, int length,\n                                       bool need_rsp, bool is_prep, uint8_t* value);\n\n/** Callback invoked when a previously prepared write is to be executed */\ntypedef void (*request_exec_write_callback)(int conn_id, int trans_id,\n                                            bt_bdaddr_t *bda, int exec_write);\n\n/**\n * Callback triggered in response to send_response if the remote device\n * sends a confirmation.\n */\ntypedef void (*response_confirmation_callback)(int status, int handle);\n\n/**\n * Callback confirming that a notification or indication has been sent\n * to a remote device.\n */\ntypedef void (*indication_sent_callback)(int conn_id, int status);\n\n/**\n * Callback notifying an application that a remote device connection is currently congested\n * and cannot receive any more data. An application should avoid sending more data until\n * a further callback is received indicating the congestion status has been cleared.\n */\ntypedef void (*congestion_callback)(int conn_id, bool congested);\n\n/** Callback invoked when the MTU for a given connection changes */\ntypedef void (*mtu_changed_callback)(int conn_id, int mtu);\n\ntypedef struct {\n    register_server_callback        register_server_cb;\n    connection_callback             connection_cb;\n    service_added_callback          service_added_cb;\n    included_service_added_callback included_service_added_cb;\n    characteristic_added_callback   characteristic_added_cb;\n    descriptor_added_callback       descriptor_added_cb;\n    service_started_callback        service_started_cb;\n    service_stopped_callback        service_stopped_cb;\n    service_deleted_callback        service_deleted_cb;\n    request_read_callback           request_read_cb;\n    request_write_callback          request_write_cb;\n    request_exec_write_callback     request_exec_write_cb;\n    response_confirmation_callback  response_confirmation_cb;\n    indication_sent_callback        indication_sent_cb;\n    congestion_callback             congestion_cb;\n    mtu_changed_callback            mtu_changed_cb;\n} btgatt_server_callbacks_t;\n\n/** Represents the standard BT-GATT server interface. */\ntypedef struct {\n    /** Registers a GATT server application with the stack */\n    bt_status_t (*register_server)( bt_uuid_t *uuid );\n\n    /** Unregister a server application from the stack */\n    bt_status_t (*unregister_server)(int server_if );\n\n    /** Create a connection to a remote peripheral */\n    bt_status_t (*connect)(int server_if, const bt_bdaddr_t *bd_addr,\n                            bool is_direct, int transport);\n\n    /** Disconnect an established connection or cancel a pending one */\n    bt_status_t (*disconnect)(int server_if, const bt_bdaddr_t *bd_addr,\n                    int conn_id );\n\n    /** Create a new service */\n    bt_status_t (*add_service)( int server_if, btgatt_srvc_id_t *srvc_id, int num_handles);\n\n    /** Assign an included service to it's parent service */\n    bt_status_t (*add_included_service)( int server_if, int service_handle, int included_handle);\n\n    /** Add a characteristic to a service */\n    bt_status_t (*add_characteristic)( int server_if,\n                    int service_handle, bt_uuid_t *uuid,\n                    int properties, int permissions);\n\n    /** Add a descriptor to a given service */\n    bt_status_t (*add_descriptor)(int server_if, int service_handle,\n                                  bt_uuid_t *uuid, int permissions);\n\n    /** Starts a local service */\n    bt_status_t (*start_service)(int server_if, int service_handle,\n                                 int transport);\n\n    /** Stops a local service */\n    bt_status_t (*stop_service)(int server_if, int service_handle);\n\n    /** Delete a local service */\n    bt_status_t (*delete_service)(int server_if, int service_handle);\n\n    /** Send value indication to a remote device */\n    bt_status_t (*send_indication)(int server_if, int attribute_handle,\n                                   int conn_id, int len, int confirm,\n                                   char* p_value);\n\n    /** Send a response to a read/write operation */\n    bt_status_t (*send_response)(int conn_id, int trans_id,\n                                 int status, btgatt_response_t *response);\n\n} btgatt_server_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_GATT_CLIENT_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_gatt_types.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_INCLUDE_BT_GATT_TYPES_H\n#define ANDROID_INCLUDE_BT_GATT_TYPES_H\n\n#include <stdint.h>\n#include <stdbool.h>\n\n__BEGIN_DECLS\n\n/**\n * GATT Service types\n */\n#define BTGATT_SERVICE_TYPE_PRIMARY 0\n#define BTGATT_SERVICE_TYPE_SECONDARY 1\n\n/** GATT ID adding instance id tracking to the UUID */\ntypedef struct\n{\n    bt_uuid_t           uuid;\n    uint8_t             inst_id;\n} btgatt_gatt_id_t;\n\n/** GATT Service ID also identifies the service type (primary/secondary) */\ntypedef struct\n{\n    btgatt_gatt_id_t    id;\n    uint8_t             is_primary;\n} btgatt_srvc_id_t;\n\n/** Preferred physical Transport for GATT connection */\ntypedef enum\n{\n    GATT_TRANSPORT_AUTO,\n    GATT_TRANSPORT_BREDR,\n    GATT_TRANSPORT_LE\n} btgatt_transport_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_GATT_TYPES_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_hd.h",
    "content": "/*\n * Copyright (c) 2013, The Linux Foundation. All rights reserved.\n * Not a Contribution\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_HD_H\n#define ANDROID_INCLUDE_BT_HD_H\n\n#include <stdint.h>\n\n__BEGIN_DECLS\n\ntypedef enum\n{\n    BTHD_REPORT_TYPE_OTHER = 0,\n    BTHD_REPORT_TYPE_INPUT,\n    BTHD_REPORT_TYPE_OUTPUT,\n    BTHD_REPORT_TYPE_FEATURE,\n    BTHD_REPORT_TYPE_INTRDATA // special value for reports to be sent on INTR (INPUT is assumed)\n} bthd_report_type_t;\n\ntypedef enum\n{\n    BTHD_APP_STATE_NOT_REGISTERED,\n    BTHD_APP_STATE_REGISTERED\n} bthd_application_state_t;\n\ntypedef enum\n{\n    BTHD_CONN_STATE_CONNECTED,\n    BTHD_CONN_STATE_CONNECTING,\n    BTHD_CONN_STATE_DISCONNECTED,\n    BTHD_CONN_STATE_DISCONNECTING,\n    BTHD_CONN_STATE_UNKNOWN\n} bthd_connection_state_t;\n\ntypedef struct\n{\n    const char      *name;\n    const char      *description;\n    const char      *provider;\n    uint8_t         subclass;\n    uint8_t         *desc_list;\n    int             desc_list_len;\n} bthd_app_param_t;\n\ntypedef struct\n{\n    uint8_t  service_type;\n    uint32_t token_rate;\n    uint32_t token_bucket_size;\n    uint32_t peak_bandwidth;\n    uint32_t access_latency;\n    uint32_t delay_variation;\n} bthd_qos_param_t;\n\ntypedef void (* bthd_application_state_callback)(bt_bdaddr_t *bd_addr, bthd_application_state_t state);\ntypedef void (* bthd_connection_state_callback)(bt_bdaddr_t *bd_addr, bthd_connection_state_t state);\ntypedef void (* bthd_get_report_callback)(uint8_t type, uint8_t id, uint16_t buffer_size);\ntypedef void (* bthd_set_report_callback)(uint8_t type, uint8_t id, uint16_t len, uint8_t *p_data);\ntypedef void (* bthd_set_protocol_callback)(uint8_t protocol);\ntypedef void (* bthd_intr_data_callback)(uint8_t report_id, uint16_t len, uint8_t *p_data);\ntypedef void (* bthd_vc_unplug_callback)(void);\n\n/** BT-HD callbacks */\ntypedef struct {\n    size_t      size;\n\n    bthd_application_state_callback application_state_cb;\n    bthd_connection_state_callback  connection_state_cb;\n    bthd_get_report_callback        get_report_cb;\n    bthd_set_report_callback        set_report_cb;\n    bthd_set_protocol_callback      set_protocol_cb;\n    bthd_intr_data_callback         intr_data_cb;\n    bthd_vc_unplug_callback         vc_unplug_cb;\n} bthd_callbacks_t;\n\n/** BT-HD interface */\ntypedef struct {\n\n    size_t          size;\n\n    /** init interface and register callbacks */\n    bt_status_t (*init)(bthd_callbacks_t* callbacks);\n\n    /** close interface */\n    void  (*cleanup)(void);\n\n    /** register application */\n    bt_status_t (*register_app)(bthd_app_param_t *app_param, bthd_qos_param_t *in_qos,\n                                            bthd_qos_param_t *out_qos);\n\n    /** unregister application */\n    bt_status_t (*unregister_app)(void);\n\n    /** connects to host with virtual cable */\n    bt_status_t (*connect)(void);\n\n    /** disconnects from currently connected host */\n    bt_status_t (*disconnect)(void);\n\n    /** send report */\n    bt_status_t (*send_report)(bthd_report_type_t type, uint8_t id, uint16_t len, uint8_t *p_data);\n\n    /** notifies error for invalid SET_REPORT */\n    bt_status_t (*report_error)(uint8_t error);\n\n    /** send Virtual Cable Unplug  */\n    bt_status_t (*virtual_cable_unplug)(void);\n\n} bthd_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_HD_H */\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_hf.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_HF_H\n#define ANDROID_INCLUDE_BT_HF_H\n\n__BEGIN_DECLS\n\n/* AT response code - OK/Error */\ntypedef enum {\n    BTHF_AT_RESPONSE_ERROR = 0,\n    BTHF_AT_RESPONSE_OK\n} bthf_at_response_t;\n\ntypedef enum {\n    BTHF_CONNECTION_STATE_DISCONNECTED = 0,\n    BTHF_CONNECTION_STATE_CONNECTING,\n    BTHF_CONNECTION_STATE_CONNECTED,\n    BTHF_CONNECTION_STATE_SLC_CONNECTED,\n    BTHF_CONNECTION_STATE_DISCONNECTING\n} bthf_connection_state_t;\n\ntypedef enum {\n    BTHF_AUDIO_STATE_DISCONNECTED = 0,\n    BTHF_AUDIO_STATE_CONNECTING,\n    BTHF_AUDIO_STATE_CONNECTED,\n    BTHF_AUDIO_STATE_DISCONNECTING\n} bthf_audio_state_t;\n\ntypedef enum {\n    BTHF_VR_STATE_STOPPED = 0,\n    BTHF_VR_STATE_STARTED\n} bthf_vr_state_t;\n\ntypedef enum {\n    BTHF_VOLUME_TYPE_SPK = 0,\n    BTHF_VOLUME_TYPE_MIC\n} bthf_volume_type_t;\n\n/* Noise Reduction and Echo Cancellation */\ntypedef enum\n{\n    BTHF_NREC_STOP,\n    BTHF_NREC_START\n} bthf_nrec_t;\n\n/* WBS codec setting */\ntypedef enum\n{\n   BTHF_WBS_NONE,\n   BTHF_WBS_NO,\n   BTHF_WBS_YES\n}bthf_wbs_config_t;\n\n/* BIND type*/\ntypedef enum\n{\n   BTHF_BIND_SET,\n   BTHF_BIND_READ,\n   BTHF_BIND_TEST\n}bthf_bind_type_t;\n\n\n/* CHLD - Call held handling */\ntypedef enum\n{\n    BTHF_CHLD_TYPE_RELEASEHELD,              // Terminate all held or set UDUB(\"busy\") to a waiting call\n    BTHF_CHLD_TYPE_RELEASEACTIVE_ACCEPTHELD, // Terminate all active calls and accepts a waiting/held call\n    BTHF_CHLD_TYPE_HOLDACTIVE_ACCEPTHELD,    // Hold all active calls and accepts a waiting/held call\n    BTHF_CHLD_TYPE_ADDHELDTOCONF,            // Add all held calls to a conference\n} bthf_chld_type_t;\n\n/** Callback for connection state change.\n *  state will have one of the values from BtHfConnectionState\n */\ntypedef void (* bthf_connection_state_callback)(bthf_connection_state_t state, bt_bdaddr_t *bd_addr);\n\n/** Callback for audio connection state change.\n *  state will have one of the values from BtHfAudioState\n */\ntypedef void (* bthf_audio_state_callback)(bthf_audio_state_t state, bt_bdaddr_t *bd_addr);\n\n/** Callback for VR connection state change.\n *  state will have one of the values from BtHfVRState\n */\ntypedef void (* bthf_vr_cmd_callback)(bthf_vr_state_t state, bt_bdaddr_t *bd_addr);\n\n/** Callback for answer incoming call (ATA)\n */\ntypedef void (* bthf_answer_call_cmd_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for disconnect call (AT+CHUP)\n */\ntypedef void (* bthf_hangup_call_cmd_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for disconnect call (AT+CHUP)\n *  type will denote Speaker/Mic gain (BtHfVolumeControl).\n */\ntypedef void (* bthf_volume_cmd_callback)(bthf_volume_type_t type, int volume, bt_bdaddr_t *bd_addr);\n\n/** Callback for dialing an outgoing call\n *  If number is NULL, redial\n */\ntypedef void (* bthf_dial_call_cmd_callback)(char *number, bt_bdaddr_t *bd_addr);\n\n/** Callback for sending DTMF tones\n *  tone contains the dtmf character to be sent\n */\ntypedef void (* bthf_dtmf_cmd_callback)(char tone, bt_bdaddr_t *bd_addr);\n\n/** Callback for enabling/disabling noise reduction/echo cancellation\n *  value will be 1 to enable, 0 to disable\n */\ntypedef void (* bthf_nrec_cmd_callback)(bthf_nrec_t nrec, bt_bdaddr_t *bd_addr);\n\n/** Callback for AT+BCS and event from BAC\n *  WBS enable, WBS disable\n */\ntypedef void (* bthf_wbs_callback)(bthf_wbs_config_t wbs, bt_bdaddr_t *bd_addr);\n\n/** Callback for call hold handling (AT+CHLD)\n *  value will contain the call hold command (0, 1, 2, 3)\n */\ntypedef void (* bthf_chld_cmd_callback)(bthf_chld_type_t chld, bt_bdaddr_t *bd_addr);\n\n/** Callback for CNUM (subscriber number)\n */\ntypedef void (* bthf_cnum_cmd_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for indicators (CIND)\n */\ntypedef void (* bthf_cind_cmd_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for operator selection (COPS)\n */\ntypedef void (* bthf_cops_cmd_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for call list (AT+CLCC)\n */\ntypedef void (* bthf_clcc_cmd_callback) (bt_bdaddr_t *bd_addr);\n\n/** Callback for unknown AT command recd from HF\n *  at_string will contain the unparsed AT string\n */\ntypedef void (* bthf_unknown_at_cmd_callback)(char *at_string, bt_bdaddr_t *bd_addr);\n\n/** Callback for keypressed (HSP) event.\n */\ntypedef void (* bthf_key_pressed_cmd_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for HF indicators (BIND)\n */\ntypedef void (* bthf_bind_cmd_callback)(char* hf_ind, bthf_bind_type_t type, bt_bdaddr_t *bd_addr);\n\n/** Callback for HF indicator value (BIEV)\n */\ntypedef void (* bthf_biev_cmd_callback)(char* hf_ind_val, bt_bdaddr_t *bd_addr);\n\n\n/** BT-HF callback structure. */\ntypedef struct {\n    /** set to sizeof(BtHfCallbacks) */\n    size_t      size;\n    bthf_connection_state_callback  connection_state_cb;\n    bthf_audio_state_callback       audio_state_cb;\n    bthf_vr_cmd_callback            vr_cmd_cb;\n    bthf_answer_call_cmd_callback   answer_call_cmd_cb;\n    bthf_hangup_call_cmd_callback   hangup_call_cmd_cb;\n    bthf_volume_cmd_callback        volume_cmd_cb;\n    bthf_dial_call_cmd_callback     dial_call_cmd_cb;\n    bthf_dtmf_cmd_callback          dtmf_cmd_cb;\n    bthf_nrec_cmd_callback          nrec_cmd_cb;\n    bthf_wbs_callback               wbs_cb;\n    bthf_chld_cmd_callback          chld_cmd_cb;\n    bthf_cnum_cmd_callback          cnum_cmd_cb;\n    bthf_cind_cmd_callback          cind_cmd_cb;\n    bthf_cops_cmd_callback          cops_cmd_cb;\n    bthf_clcc_cmd_callback          clcc_cmd_cb;\n    bthf_unknown_at_cmd_callback    unknown_at_cmd_cb;\n    bthf_key_pressed_cmd_callback   key_pressed_cmd_cb;\n    bthf_bind_cmd_callback          bind_cmd_cb;\n    bthf_biev_cmd_callback          biev_cmd_cb;\n} bthf_callbacks_t;\n\n/** Network Status */\ntypedef enum\n{\n    BTHF_NETWORK_STATE_NOT_AVAILABLE = 0,\n    BTHF_NETWORK_STATE_AVAILABLE\n} bthf_network_state_t;\n\n/** Service type */\ntypedef enum\n{\n    BTHF_SERVICE_TYPE_HOME = 0,\n    BTHF_SERVICE_TYPE_ROAMING\n} bthf_service_type_t;\n\ntypedef enum {\n    BTHF_CALL_STATE_ACTIVE = 0,\n    BTHF_CALL_STATE_HELD,\n    BTHF_CALL_STATE_DIALING,\n    BTHF_CALL_STATE_ALERTING,\n    BTHF_CALL_STATE_INCOMING,\n    BTHF_CALL_STATE_WAITING,\n    BTHF_CALL_STATE_IDLE\n} bthf_call_state_t;\n\ntypedef enum {\n    BTHF_CALL_DIRECTION_OUTGOING = 0,\n    BTHF_CALL_DIRECTION_INCOMING\n} bthf_call_direction_t;\n\ntypedef enum {\n    BTHF_CALL_TYPE_VOICE = 0,\n    BTHF_CALL_TYPE_DATA,\n    BTHF_CALL_TYPE_FAX\n} bthf_call_mode_t;\n\ntypedef enum {\n    BTHF_CALL_MPTY_TYPE_SINGLE = 0,\n    BTHF_CALL_MPTY_TYPE_MULTI\n} bthf_call_mpty_type_t;\n\ntypedef enum {\n    BTHF_HF_INDICATOR_STATE_DISABLED = 0,\n    BTHF_HF_INDICATOR_STATE_ENABLED\n} bthf_hf_indicator_status_t;\n\ntypedef enum {\n    BTHF_CALL_ADDRTYPE_UNKNOWN = 0x81,\n    BTHF_CALL_ADDRTYPE_INTERNATIONAL = 0x91\n} bthf_call_addrtype_t;\n\ntypedef enum {\n    BTHF_VOIP_CALL_NETWORK_TYPE_MOBILE = 0,\n    BTHF_VOIP_CALL_NETWORK_TYPE_WIFI\n} bthf_voip_call_network_type_t;\n\ntypedef enum {\n    BTHF_VOIP_STATE_STOPPED = 0,\n    BTHF_VOIP_STATE_STARTED\n} bthf_voip_state_t;\n\n/** Represents the standard BT-HF interface. */\ntypedef struct {\n\n    /** set to sizeof(BtHfInterface) */\n    size_t          size;\n    /**\n     * Register the BtHf callbacks\n     */\n    bt_status_t (*init)( bthf_callbacks_t* callbacks, int max_hf_clients);\n\n    /** connect to headset */\n    bt_status_t (*connect)( bt_bdaddr_t *bd_addr );\n\n    /** dis-connect from headset */\n    bt_status_t (*disconnect)( bt_bdaddr_t *bd_addr );\n\n    /** create an audio connection */\n    bt_status_t (*connect_audio)( bt_bdaddr_t *bd_addr );\n\n    /** close the audio connection */\n    bt_status_t (*disconnect_audio)( bt_bdaddr_t *bd_addr );\n\n    /** start voice recognition */\n    bt_status_t (*start_voice_recognition)( bt_bdaddr_t *bd_addr );\n\n    /** stop voice recognition */\n    bt_status_t (*stop_voice_recognition)( bt_bdaddr_t *bd_addr );\n\n    /** volume control */\n    bt_status_t (*volume_control) (bthf_volume_type_t type, int volume, bt_bdaddr_t *bd_addr );\n\n    /** Combined device status change notification */\n    bt_status_t (*device_status_notification)(bthf_network_state_t ntk_state, bthf_service_type_t svc_type, int signal,\n                           int batt_chg);\n\n    /** Response for COPS command */\n    bt_status_t (*cops_response)(const char *cops, bt_bdaddr_t *bd_addr );\n\n    /** Response for CIND command */\n    bt_status_t (*cind_response)(int svc, int num_active, int num_held, bthf_call_state_t call_setup_state,\n                                 int signal, int roam, int batt_chg, bt_bdaddr_t *bd_addr );\n\n    /** Pre-formatted AT response, typically in response to unknown AT cmd */\n    bt_status_t (*formatted_at_response)(const char *rsp, bt_bdaddr_t *bd_addr );\n\n    /** ok/error response\n     *  ERROR (0)\n     *  OK    (1)\n     */\n    bt_status_t (*at_response) (bthf_at_response_t response_code, int error_code, bt_bdaddr_t *bd_addr );\n\n    /** response for CLCC command \n     *  Can be iteratively called for each call index\n     *  Call index of 0 will be treated as NULL termination (Completes response)\n     */\n    bt_status_t (*clcc_response) (int index, bthf_call_direction_t dir,\n                                bthf_call_state_t state, bthf_call_mode_t mode,\n                                bthf_call_mpty_type_t mpty, const char *number,\n                                bthf_call_addrtype_t type, bt_bdaddr_t *bd_addr );\n\n    /** notify of a call state change\n     *  Each update notifies \n     *    1. Number of active/held/ringing calls\n     *    2. call_state: This denotes the state change that triggered this msg\n     *                   This will take one of the values from BtHfCallState\n     *    3. number & type: valid only for incoming & waiting call\n    */\n    bt_status_t (*phone_state_change) (int num_active, int num_held, bthf_call_state_t call_setup_state,\n                                       const char *number, bthf_call_addrtype_t type);\n\n    /** Closes the interface. */\n    void  (*cleanup)( void );\n\n    /** configureation for the SCO codec */\n    bt_status_t (*configure_wbs)( bt_bdaddr_t *bd_addr ,bthf_wbs_config_t config );\n\n    /** Response for BIND READ command and activation/deactivation of  HF indicator */\n    bt_status_t (*bind_response) (int anum, bthf_hf_indicator_status_t status,\n                                  bt_bdaddr_t *bd_addr);\n\n    /** Response for BIND TEST command */\n    bt_status_t (*bind_string_response) (const char* result, bt_bdaddr_t *bd_addr);\n\n    /** Sends connectivity network type used by Voip currently to stack */\n    bt_status_t (*voip_network_type_wifi) (bthf_voip_state_t is_voip_started,\n                                           bthf_voip_call_network_type_t is_network_wifi);\n} bthf_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_HF_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_hf_client.h",
    "content": "/*\n * Copyright (C) 2012-2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_HF_CLIENT_H\n#define ANDROID_INCLUDE_BT_HF_CLIENT_H\n\n__BEGIN_DECLS\n\ntypedef enum {\n    BTHF_CLIENT_CONNECTION_STATE_DISCONNECTED = 0,\n    BTHF_CLIENT_CONNECTION_STATE_CONNECTING,\n    BTHF_CLIENT_CONNECTION_STATE_CONNECTED,\n    BTHF_CLIENT_CONNECTION_STATE_SLC_CONNECTED,\n    BTHF_CLIENT_CONNECTION_STATE_DISCONNECTING\n} bthf_client_connection_state_t;\n\ntypedef enum {\n    BTHF_CLIENT_AUDIO_STATE_DISCONNECTED = 0,\n    BTHF_CLIENT_AUDIO_STATE_CONNECTING,\n    BTHF_CLIENT_AUDIO_STATE_CONNECTED,\n    BTHF_CLIENT_AUDIO_STATE_CONNECTED_MSBC,\n} bthf_client_audio_state_t;\n\ntypedef enum {\n    BTHF_CLIENT_VR_STATE_STOPPED = 0,\n    BTHF_CLIENT_VR_STATE_STARTED\n} bthf_client_vr_state_t;\n\ntypedef enum {\n    BTHF_CLIENT_VOLUME_TYPE_SPK = 0,\n    BTHF_CLIENT_VOLUME_TYPE_MIC\n} bthf_client_volume_type_t;\n\ntypedef enum\n{\n    BTHF_CLIENT_NETWORK_STATE_NOT_AVAILABLE = 0,\n    BTHF_CLIENT_NETWORK_STATE_AVAILABLE\n} bthf_client_network_state_t;\n\ntypedef enum\n{\n    BTHF_CLIENT_SERVICE_TYPE_HOME = 0,\n    BTHF_CLIENT_SERVICE_TYPE_ROAMING\n} bthf_client_service_type_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALL_STATE_ACTIVE = 0,\n    BTHF_CLIENT_CALL_STATE_HELD,\n    BTHF_CLIENT_CALL_STATE_DIALING,\n    BTHF_CLIENT_CALL_STATE_ALERTING,\n    BTHF_CLIENT_CALL_STATE_INCOMING,\n    BTHF_CLIENT_CALL_STATE_WAITING,\n    BTHF_CLIENT_CALL_STATE_HELD_BY_RESP_HOLD,\n} bthf_client_call_state_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALL_NO_CALLS_IN_PROGRESS = 0,\n    BTHF_CLIENT_CALL_CALLS_IN_PROGRESS\n} bthf_client_call_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALLSETUP_NONE = 0,\n    BTHF_CLIENT_CALLSETUP_INCOMING,\n    BTHF_CLIENT_CALLSETUP_OUTGOING,\n    BTHF_CLIENT_CALLSETUP_ALERTING\n\n} bthf_client_callsetup_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALLHELD_NONE = 0,\n    BTHF_CLIENT_CALLHELD_HOLD_AND_ACTIVE,\n    BTHF_CLIENT_CALLHELD_HOLD,\n} bthf_client_callheld_t;\n\ntypedef enum {\n    BTHF_CLIENT_RESP_AND_HOLD_HELD = 0,\n    BTRH_CLIENT_RESP_AND_HOLD_ACCEPT,\n    BTRH_CLIENT_RESP_AND_HOLD_REJECT,\n} bthf_client_resp_and_hold_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALL_DIRECTION_OUTGOING = 0,\n    BTHF_CLIENT_CALL_DIRECTION_INCOMING\n} bthf_client_call_direction_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALL_MPTY_TYPE_SINGLE = 0,\n    BTHF_CLIENT_CALL_MPTY_TYPE_MULTI\n} bthf_client_call_mpty_type_t;\n\ntypedef enum {\n    BTHF_CLIENT_CMD_COMPLETE_OK = 0,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR_NO_CARRIER,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR_BUSY,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR_NO_ANSWER,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR_DELAYED,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR_BLACKLISTED,\n    BTHF_CLIENT_CMD_COMPLETE_ERROR_CME\n} bthf_client_cmd_complete_t;\n\ntypedef enum {\n    BTHF_CLIENT_CALL_ACTION_CHLD_0 = 0,\n    BTHF_CLIENT_CALL_ACTION_CHLD_1,\n    BTHF_CLIENT_CALL_ACTION_CHLD_2,\n    BTHF_CLIENT_CALL_ACTION_CHLD_3,\n    BTHF_CLIENT_CALL_ACTION_CHLD_4,\n    BTHF_CLIENT_CALL_ACTION_CHLD_1x,\n    BTHF_CLIENT_CALL_ACTION_CHLD_2x,\n    BTHF_CLIENT_CALL_ACTION_ATA,\n    BTHF_CLIENT_CALL_ACTION_CHUP,\n    BTHF_CLIENT_CALL_ACTION_BTRH_0,\n    BTHF_CLIENT_CALL_ACTION_BTRH_1,\n    BTHF_CLIENT_CALL_ACTION_BTRH_2,\n} bthf_client_call_action_t;\n\ntypedef enum {\n    BTHF_CLIENT_SERVICE_UNKNOWN = 0,\n    BTHF_CLIENT_SERVICE_VOICE,\n    BTHF_CLIENT_SERVICE_FAX\n} bthf_client_subscriber_service_type_t;\n\ntypedef enum {\n    BTHF_CLIENT_IN_BAND_RINGTONE_NOT_PROVIDED = 0,\n    BTHF_CLIENT_IN_BAND_RINGTONE_PROVIDED,\n} bthf_client_in_band_ring_state_t;\n\n/* Peer features masks */\n#define BTHF_CLIENT_PEER_FEAT_3WAY   0x00000001  /* Three-way calling */\n#define BTHF_CLIENT_PEER_FEAT_ECNR   0x00000002  /* Echo cancellation and/or noise reduction */\n#define BTHF_CLIENT_PEER_FEAT_VREC   0x00000004  /* Voice recognition */\n#define BTHF_CLIENT_PEER_FEAT_INBAND 0x00000008  /* In-band ring tone */\n#define BTHF_CLIENT_PEER_FEAT_VTAG   0x00000010  /* Attach a phone number to a voice tag */\n#define BTHF_CLIENT_PEER_FEAT_REJECT 0x00000020  /* Ability to reject incoming call */\n#define BTHF_CLIENT_PEER_FEAT_ECS    0x00000040  /* Enhanced Call Status */\n#define BTHF_CLIENT_PEER_FEAT_ECC    0x00000080  /* Enhanced Call Control */\n#define BTHF_CLIENT_PEER_FEAT_EXTERR 0x00000100  /* Extended error codes */\n#define BTHF_CLIENT_PEER_FEAT_CODEC  0x00000200  /* Codec Negotiation */\n\n/* Peer call handling features masks */\n#define BTHF_CLIENT_CHLD_FEAT_REL           0x00000001  /* 0  Release waiting call or held calls */\n#define BTHF_CLIENT_CHLD_FEAT_REL_ACC       0x00000002  /* 1  Release active calls and accept other\n                                                              (waiting or held) cal */\n#define BTHF_CLIENT_CHLD_FEAT_REL_X         0x00000004  /* 1x Release specified active call only */\n#define BTHF_CLIENT_CHLD_FEAT_HOLD_ACC      0x00000008  /* 2  Active calls on hold and accept other\n                                                              (waiting or held) call */\n#define BTHF_CLIENT_CHLD_FEAT_PRIV_X        0x00000010  /* 2x Request private mode with specified\n                                                              call (put the rest on hold) */\n#define BTHF_CLIENT_CHLD_FEAT_MERGE         0x00000020  /* 3  Add held call to multiparty */\n#define BTHF_CLIENT_CHLD_FEAT_MERGE_DETACH  0x00000040  /* 4  Connect two calls and leave\n                                                              (disconnect from) multiparty */\n\n/** Callback for connection state change.\n *  state will have one of the values from BtHfConnectionState\n *  peer/chld_features are valid only for BTHF_CLIENT_CONNECTION_STATE_SLC_CONNECTED state\n */\ntypedef void (* bthf_client_connection_state_callback)(bthf_client_connection_state_t state,\n                                                       unsigned int peer_feat,\n                                                       unsigned int chld_feat,\n                                                       bt_bdaddr_t *bd_addr);\n\n/** Callback for audio connection state change.\n *  state will have one of the values from BtHfAudioState\n */\ntypedef void (* bthf_client_audio_state_callback)(bthf_client_audio_state_t state,\n                                                  bt_bdaddr_t *bd_addr);\n\n/** Callback for VR connection state change.\n *  state will have one of the values from BtHfVRState\n */\ntypedef void (* bthf_client_vr_cmd_callback)(bthf_client_vr_state_t state);\n\n/** Callback for network state change\n */\ntypedef void (* bthf_client_network_state_callback) (bthf_client_network_state_t state);\n\n/** Callback for network roaming status change\n */\ntypedef void (* bthf_client_network_roaming_callback) (bthf_client_service_type_t type);\n\n/** Callback for signal strength indication\n */\ntypedef void (* bthf_client_network_signal_callback) (int signal_strength);\n\n/** Callback for battery level indication\n */\ntypedef void (* bthf_client_battery_level_callback) (int battery_level);\n\n/** Callback for current operator name\n */\ntypedef void (* bthf_client_current_operator_callback) (const char *name);\n\n/** Callback for call indicator\n */\ntypedef void (* bthf_client_call_callback) (bthf_client_call_t call);\n\n/** Callback for callsetup indicator\n */\ntypedef void (* bthf_client_callsetup_callback) (bthf_client_callsetup_t callsetup);\n\n/** Callback for callheld indicator\n */\ntypedef void (* bthf_client_callheld_callback) (bthf_client_callheld_t callheld);\n\n/** Callback for response and hold\n */\ntypedef void (* bthf_client_resp_and_hold_callback) (bthf_client_resp_and_hold_t resp_and_hold);\n\n/** Callback for Calling Line Identification notification\n *  Will be called only when there is an incoming call and number is provided.\n */\ntypedef void (* bthf_client_clip_callback) (const char *number);\n\n/**\n * Callback for Call Waiting notification\n */\ntypedef void (* bthf_client_call_waiting_callback) (const char *number);\n\n/**\n *  Callback for listing current calls. Can be called multiple time.\n *  If number is unknown NULL is passed.\n */\ntypedef void (*bthf_client_current_calls) (int index, bthf_client_call_direction_t dir,\n                                           bthf_client_call_state_t state,\n                                           bthf_client_call_mpty_type_t mpty,\n                                           const char *number);\n\n/** Callback for audio volume change\n */\ntypedef void (*bthf_client_volume_change_callback) (bthf_client_volume_type_t type, int volume);\n\n/** Callback for command complete event\n *  cme is valid only for BTHF_CLIENT_CMD_COMPLETE_ERROR_CME type\n */\ntypedef void (*bthf_client_cmd_complete_callback) (bthf_client_cmd_complete_t type, int cme);\n\n/** Callback for subscriber information\n */\ntypedef void (* bthf_client_subscriber_info_callback) (const char *name,\n                                                       bthf_client_subscriber_service_type_t type);\n\n/** Callback for in-band ring tone settings\n */\ntypedef void (* bthf_client_in_band_ring_tone_callback) (bthf_client_in_band_ring_state_t state);\n\n/**\n * Callback for requested number from AG\n */\ntypedef void (* bthf_client_last_voice_tag_number_callback) (const char *number);\n\n/**\n * Callback for sending ring indication to app\n */\ntypedef void (* bthf_client_ring_indication_callback) (void);\n\n/**\n * Callback for sending cgmi indication to app\n */\ntypedef void (* bthf_client_cgmi_indication_callback) (const char *str);\n\n/**\n * Callback for sending cgmm indication to app\n */\ntypedef void (* bthf_client_cgmm_indication_callback) (const char *str);\n\n/** BT-HF callback structure. */\ntypedef struct {\n    /** set to sizeof(BtHfClientCallbacks) */\n    size_t      size;\n    bthf_client_connection_state_callback  connection_state_cb;\n    bthf_client_audio_state_callback       audio_state_cb;\n    bthf_client_vr_cmd_callback            vr_cmd_cb;\n    bthf_client_network_state_callback     network_state_cb;\n    bthf_client_network_roaming_callback   network_roaming_cb;\n    bthf_client_network_signal_callback    network_signal_cb;\n    bthf_client_battery_level_callback     battery_level_cb;\n    bthf_client_current_operator_callback  current_operator_cb;\n    bthf_client_call_callback              call_cb;\n    bthf_client_callsetup_callback         callsetup_cb;\n    bthf_client_callheld_callback          callheld_cb;\n    bthf_client_resp_and_hold_callback     resp_and_hold_cb;\n    bthf_client_clip_callback              clip_cb;\n    bthf_client_call_waiting_callback      call_waiting_cb;\n    bthf_client_current_calls              current_calls_cb;\n    bthf_client_volume_change_callback     volume_change_cb;\n    bthf_client_cmd_complete_callback      cmd_complete_cb;\n    bthf_client_subscriber_info_callback   subscriber_info_cb;\n    bthf_client_in_band_ring_tone_callback in_band_ring_tone_cb;\n    bthf_client_last_voice_tag_number_callback last_voice_tag_number_callback;\n    bthf_client_ring_indication_callback   ring_indication_cb;\n    bthf_client_cgmi_indication_callback   cgmi_cb;\n    bthf_client_cgmm_indication_callback   cgmm_cb;\n} bthf_client_callbacks_t;\n\n/** Represents the standard BT-HF interface. */\ntypedef struct {\n\n    /** set to sizeof(BtHfClientInterface) */\n    size_t size;\n    /**\n     * Register the BtHf callbacks\n     */\n    bt_status_t (*init)(bthf_client_callbacks_t* callbacks);\n\n    /** connect to audio gateway */\n    bt_status_t (*connect)(bt_bdaddr_t *bd_addr);\n\n    /** disconnect from audio gateway */\n    bt_status_t (*disconnect)(bt_bdaddr_t *bd_addr);\n\n    /** create an audio connection */\n    bt_status_t (*connect_audio)(bt_bdaddr_t *bd_addr);\n\n    /** close the audio connection */\n    bt_status_t (*disconnect_audio)(bt_bdaddr_t *bd_addr);\n\n    /** start voice recognition */\n    bt_status_t (*start_voice_recognition)(void);\n\n    /** stop voice recognition */\n    bt_status_t (*stop_voice_recognition)(void);\n\n    /** volume control */\n    bt_status_t (*volume_control) (bthf_client_volume_type_t type, int volume);\n\n    /** place a call with number a number\n     * if number is NULL last called number is called (aka re-dial)*/\n    bt_status_t (*dial) (const char *number);\n\n    /** place a call with number specified by location (speed dial) */\n    bt_status_t (*dial_memory) (int location);\n\n    /** perform specified call related action\n     * idx is limited only for enhanced call control related action\n     */\n    bt_status_t (*handle_call_action) (bthf_client_call_action_t action, int idx);\n\n    /** query list of current calls */\n    bt_status_t (*query_current_calls) (void);\n\n    /** query name of current selected operator */\n    bt_status_t (*query_current_operator_name) (void);\n\n    /** Retrieve subscriber information */\n    bt_status_t (*retrieve_subscriber_info) (void);\n\n    /** Send DTMF code*/\n    bt_status_t (*send_dtmf) (char code);\n\n    /** Request a phone number from AG corresponding to last voice tag recorded */\n    bt_status_t (*request_last_voice_tag_number) (void);\n\n    /** Closes the interface. */\n    void (*cleanup)(void);\n\n    /** Send AT Command. */\n    bt_status_t (*send_at_cmd) (int cmd, int val1, int val2, const char *arg);\n} bthf_client_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_HF_CLIENT_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_hh.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_HH_H\n#define ANDROID_INCLUDE_BT_HH_H\n\n#include <stdint.h>\n\n__BEGIN_DECLS\n\n#define BTHH_MAX_DSC_LEN   884\n\n/* HH connection states */\ntypedef enum\n{\n    BTHH_CONN_STATE_CONNECTED              = 0,\n    BTHH_CONN_STATE_CONNECTING,\n    BTHH_CONN_STATE_DISCONNECTED,\n    BTHH_CONN_STATE_DISCONNECTING,\n    BTHH_CONN_STATE_FAILED_MOUSE_FROM_HOST,\n    BTHH_CONN_STATE_FAILED_KBD_FROM_HOST,\n    BTHH_CONN_STATE_FAILED_TOO_MANY_DEVICES,\n    BTHH_CONN_STATE_FAILED_NO_BTHID_DRIVER,\n    BTHH_CONN_STATE_FAILED_GENERIC,\n    BTHH_CONN_STATE_UNKNOWN\n} bthh_connection_state_t;\n\ntypedef enum\n{\n    BTHH_OK                = 0,\n    BTHH_HS_HID_NOT_READY,        /* handshake error : device not ready */\n    BTHH_HS_INVALID_RPT_ID,       /* handshake error : invalid report ID */\n    BTHH_HS_TRANS_NOT_SPT,        /* handshake error : transaction not spt */\n    BTHH_HS_INVALID_PARAM,        /* handshake error : invalid paremter */\n    BTHH_HS_ERROR,                /* handshake error : unspecified HS error */\n    BTHH_ERR,                     /* general BTA HH error */\n    BTHH_ERR_SDP,                 /* SDP error */\n    BTHH_ERR_PROTO,               /* SET_Protocol error,\n                                                                only used in BTA_HH_OPEN_EVT callback */\n    BTHH_ERR_DB_FULL,             /* device database full error, used  */\n    BTHH_ERR_TOD_UNSPT,           /* type of device not supported */\n    BTHH_ERR_NO_RES,              /* out of system resources */\n    BTHH_ERR_AUTH_FAILED,         /* authentication fail */\n    BTHH_ERR_HDL\n}bthh_status_t;\n\n/* Protocol modes */\ntypedef enum {\n    BTHH_REPORT_MODE       = 0x00,\n    BTHH_BOOT_MODE         = 0x01,\n    BTHH_UNSUPPORTED_MODE  = 0xff\n}bthh_protocol_mode_t;\n\n/* Report types */\ntypedef enum {\n    BTHH_INPUT_REPORT      = 1,\n    BTHH_OUTPUT_REPORT,\n    BTHH_FEATURE_REPORT\n}bthh_report_type_t;\n\ntypedef struct\n{\n    int         attr_mask;\n    uint8_t     sub_class;\n    uint8_t     app_id;\n    int         vendor_id;\n    int         product_id;\n    int         version;\n    uint8_t     ctry_code;\n    int         dl_len;\n    uint8_t     dsc_list[BTHH_MAX_DSC_LEN];\n} bthh_hid_info_t;\n\n/** Callback for connection state change.\n *  state will have one of the values from bthh_connection_state_t\n */\ntypedef void (* bthh_connection_state_callback)(bt_bdaddr_t *bd_addr, bthh_connection_state_t state);\n\n/** Callback for vitual unplug api.\n *  the status of the vitual unplug\n */\ntypedef void (* bthh_virtual_unplug_callback)(bt_bdaddr_t *bd_addr, bthh_status_t hh_status);\n\n/** Callback for get hid info\n *  hid_info will contain attr_mask, sub_class, app_id, vendor_id, product_id, version, ctry_code, len\n */\ntypedef void (* bthh_hid_info_callback)(bt_bdaddr_t *bd_addr, bthh_hid_info_t hid_info);\n\n/** Callback for get protocol api.\n *  the protocol mode is one of the value from bthh_protocol_mode_t\n */\ntypedef void (* bthh_protocol_mode_callback)(bt_bdaddr_t *bd_addr, bthh_status_t hh_status, bthh_protocol_mode_t mode);\n\n/** Callback for get/set_idle_time api.\n */\ntypedef void (* bthh_idle_time_callback)(bt_bdaddr_t *bd_addr, bthh_status_t hh_status, int idle_rate);\n\n\n/** Callback for get report api.\n *  if staus is ok rpt_data contains the report data\n */\ntypedef void (* bthh_get_report_callback)(bt_bdaddr_t *bd_addr, bthh_status_t hh_status, uint8_t* rpt_data, int rpt_size);\n\n/** Callback for set_report/set_protocol api and if error\n *  occurs for get_report/get_protocol api.\n */\ntypedef void (* bthh_handshake_callback)(bt_bdaddr_t *bd_addr, bthh_status_t hh_status);\n\n\n/** BT-HH callback structure. */\ntypedef struct {\n    /** set to sizeof(BtHfCallbacks) */\n    size_t      size;\n    bthh_connection_state_callback  connection_state_cb;\n    bthh_hid_info_callback          hid_info_cb;\n    bthh_protocol_mode_callback     protocol_mode_cb;\n    bthh_idle_time_callback         idle_time_cb;\n    bthh_get_report_callback        get_report_cb;\n    bthh_virtual_unplug_callback    virtual_unplug_cb;\n    bthh_handshake_callback         handshake_cb;\n\n} bthh_callbacks_t;\n\n\n\n/** Represents the standard BT-HH interface. */\ntypedef struct {\n\n    /** set to sizeof(BtHhInterface) */\n    size_t          size;\n\n    /**\n     * Register the BtHh callbacks\n     */\n    bt_status_t (*init)( bthh_callbacks_t* callbacks );\n\n    /** connect to hid device */\n    bt_status_t (*connect)( bt_bdaddr_t *bd_addr);\n\n    /** dis-connect from hid device */\n    bt_status_t (*disconnect)( bt_bdaddr_t *bd_addr );\n\n    /** Virtual UnPlug (VUP) the specified HID device */\n    bt_status_t (*virtual_unplug)(bt_bdaddr_t *bd_addr);\n\n    /** Set the HID device descriptor for the specified HID device. */\n    bt_status_t (*set_info)(bt_bdaddr_t *bd_addr, bthh_hid_info_t hid_info );\n\n    /** Get the HID proto mode. */\n    bt_status_t (*get_protocol) (bt_bdaddr_t *bd_addr, bthh_protocol_mode_t protocolMode);\n\n    /** Set the HID proto mode. */\n    bt_status_t (*set_protocol)(bt_bdaddr_t *bd_addr, bthh_protocol_mode_t protocolMode);\n\n    /** Get the HID Idle Time */\n    bt_status_t (*get_idle_time)(bt_bdaddr_t *bd_addr);\n\n    /** Set the HID Idle Time */\n    bt_status_t (*set_idle_time)(bt_bdaddr_t *bd_addr, uint8_t idleTime);\n\n    /** Send a GET_REPORT to HID device. */\n    bt_status_t (*get_report)(bt_bdaddr_t *bd_addr, bthh_report_type_t reportType, uint8_t reportId, int bufferSize);\n\n    /** Send a SET_REPORT to HID device. */\n    bt_status_t (*set_report)(bt_bdaddr_t *bd_addr, bthh_report_type_t reportType, char* report);\n\n    /** Send data to HID device. */\n    bt_status_t (*send_data)(bt_bdaddr_t *bd_addr, char* data);\n\n    /** Closes the interface. */\n    void  (*cleanup)( void );\n\n} bthh_interface_t;\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_HH_H */\n\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_hl.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_HL_H\n#define ANDROID_INCLUDE_BT_HL_H\n\n__BEGIN_DECLS\n\n/* HL connection states */\n\ntypedef enum\n{\n    BTHL_MDEP_ROLE_SOURCE,\n    BTHL_MDEP_ROLE_SINK\n} bthl_mdep_role_t;\n\ntypedef enum {\n    BTHL_APP_REG_STATE_REG_SUCCESS,\n    BTHL_APP_REG_STATE_REG_FAILED,\n    BTHL_APP_REG_STATE_DEREG_SUCCESS,\n    BTHL_APP_REG_STATE_DEREG_FAILED\n} bthl_app_reg_state_t;\n\ntypedef enum\n{\n    BTHL_CHANNEL_TYPE_RELIABLE,\n    BTHL_CHANNEL_TYPE_STREAMING,\n    BTHL_CHANNEL_TYPE_ANY\n} bthl_channel_type_t;\n\n\n/* HL connection states */\ntypedef enum {\n    BTHL_CONN_STATE_CONNECTING,\n    BTHL_CONN_STATE_CONNECTED,\n    BTHL_CONN_STATE_DISCONNECTING,\n    BTHL_CONN_STATE_DISCONNECTED,\n    BTHL_CONN_STATE_DESTROYED\n} bthl_channel_state_t;\n\ntypedef struct\n{\n    bthl_mdep_role_t        mdep_role;\n    int                     data_type;\n    bthl_channel_type_t     channel_type;\n    const char                   *mdep_description; /* MDEP description to be used in the SDP (optional); null terminated */\n} bthl_mdep_cfg_t;\n\ntypedef struct\n{\n    const char      *application_name;\n    const char      *provider_name;   /* provider name to be used in the SDP (optional); null terminated */\n    const char      *srv_name;        /* service name to be used in the SDP (optional); null terminated*/\n    const char      *srv_desp;        /* service description to be used in the SDP (optional); null terminated */\n    int             number_of_mdeps;\n    bthl_mdep_cfg_t *mdep_cfg;  /* Dynamic array */\n} bthl_reg_param_t;\n\n/** Callback for application registration status.\n *  state will have one of the values from  bthl_app_reg_state_t\n */\ntypedef void (* bthl_app_reg_state_callback)(int app_id, bthl_app_reg_state_t state);\n\n/** Callback for channel connection state change.\n *  state will have one of the values from\n *  bthl_connection_state_t and fd (file descriptor)\n */\ntypedef void (* bthl_channel_state_callback)(int app_id, bt_bdaddr_t *bd_addr, int mdep_cfg_index, int channel_id, bthl_channel_state_t state, int fd);\n\n/** BT-HL callback structure. */\ntypedef struct {\n    /** set to sizeof(bthl_callbacks_t) */\n    size_t      size;\n    bthl_app_reg_state_callback     app_reg_state_cb;\n    bthl_channel_state_callback     channel_state_cb;\n} bthl_callbacks_t;\n\n\n/** Represents the standard BT-HL interface. */\ntypedef struct {\n\n    /** set to sizeof(bthl_interface_t)  */\n    size_t          size;\n\n    /**\n     * Register the Bthl callbacks\n     */\n    bt_status_t (*init)( bthl_callbacks_t* callbacks );\n\n    /** Register HL application */\n    bt_status_t (*register_application) ( bthl_reg_param_t *p_reg_param, int *app_id);\n\n    /** Unregister HL application */\n    bt_status_t (*unregister_application) (int app_id);\n\n    /** connect channel */\n    bt_status_t (*connect_channel)(int app_id, bt_bdaddr_t *bd_addr, int mdep_cfg_index, int *channel_id);\n\n    /** destroy channel */\n    bt_status_t (*destroy_channel)(int channel_id);\n\n    /** Close the  Bthl callback **/\n    void (*cleanup)(void);\n\n} bthl_interface_t;\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_HL_H */\n\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_mce.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_MCE_H\n#define ANDROID_INCLUDE_BT_MCE_H\n\n__BEGIN_DECLS\n\n/** MAS instance description */\ntypedef struct\n{\n    int  id;\n    int  scn;\n    int  msg_types;\n    char *p_name;\n} btmce_mas_instance_t;\n\n/** callback for get_remote_mas_instances */\ntypedef void (*btmce_remote_mas_instances_callback)(bt_status_t status, bt_bdaddr_t *bd_addr,\n                                                    int num_instances, btmce_mas_instance_t *instances);\n\ntypedef struct {\n    /** set to sizeof(btmce_callbacks_t) */\n    size_t      size;\n    btmce_remote_mas_instances_callback  remote_mas_instances_cb;\n} btmce_callbacks_t;\n\ntypedef struct {\n    /** set to size of this struct */\n    size_t size;\n\n    /** register BT MCE callbacks */\n    bt_status_t (*init)(btmce_callbacks_t *callbacks);\n\n    /** search for MAS instances on remote device */\n    bt_status_t (*get_remote_mas_instances)(bt_bdaddr_t *bd_addr);\n} btmce_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_MCE_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_pan.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_PAN_H\n#define ANDROID_INCLUDE_BT_PAN_H\n\n__BEGIN_DECLS\n\n#define BTPAN_ROLE_NONE      0\n#define BTPAN_ROLE_PANNAP    1\n#define BTPAN_ROLE_PANU      2\n\ntypedef enum {\n    BTPAN_STATE_CONNECTED       = 0,\n    BTPAN_STATE_CONNECTING      = 1,\n    BTPAN_STATE_DISCONNECTED    = 2,\n    BTPAN_STATE_DISCONNECTING   = 3\n} btpan_connection_state_t;\n\ntypedef enum {\n    BTPAN_STATE_ENABLED = 0,\n    BTPAN_STATE_DISABLED = 1\n} btpan_control_state_t;\n\n/**\n* Callback for pan connection state\n*/\ntypedef void (*btpan_connection_state_callback)(btpan_connection_state_t state, bt_status_t error,\n                                                const bt_bdaddr_t *bd_addr, int local_role, int remote_role);\ntypedef void (*btpan_control_state_callback)(btpan_control_state_t state, int local_role,\n                                            bt_status_t error, const char* ifname);\n\ntypedef struct {\n    size_t size;\n    btpan_control_state_callback control_state_cb;\n    btpan_connection_state_callback connection_state_cb;\n} btpan_callbacks_t;\ntypedef struct {\n    /** set to size of this struct*/\n    size_t          size;\n    /**\n     * Initialize the pan interface and register the btpan callbacks\n     */\n    bt_status_t (*init)(const btpan_callbacks_t* callbacks);\n    /*\n     * enable the pan service by specified role. The result state of\n     * enabl will be returned by btpan_control_state_callback. when pan-nap is enabled,\n     * the state of connecting panu device will be notified by btpan_connection_state_callback\n     */\n    bt_status_t (*enable)(int local_role);\n    /*\n     * get current pan local role\n     */\n    int (*get_local_role)(void);\n    /**\n     * start bluetooth pan connection to the remote device by specified pan role. The result state will be\n     * returned by btpan_connection_state_callback\n     */\n    bt_status_t (*connect)(const bt_bdaddr_t *bd_addr, int local_role, int remote_role);\n    /**\n     * stop bluetooth pan connection. The result state will be returned by btpan_connection_state_callback\n     */\n    bt_status_t (*disconnect)(const bt_bdaddr_t *bd_addr);\n\n    /**\n     * Cleanup the pan interface\n     */\n    void (*cleanup)(void);\n\n} btpan_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_PAN_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_rc.h",
    "content": "/*\n * Copyright (C) 2013-2014, The Linux Foundation. All rights reserved.\n * Not a Contribution.\n *\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_BT_RC_H\n#define ANDROID_INCLUDE_BT_RC_H\n\n__BEGIN_DECLS\n\n/* Macros */\n#define BTRC_MAX_ATTR_STR_LEN       255\n#define BTRC_UID_SIZE               8\n#define BTRC_MAX_APP_SETTINGS       8\n#define BTRC_MAX_FOLDER_DEPTH       4\n#define BTRC_MAX_APP_ATTR_SIZE      16\n#define BTRC_MAX_ELEM_ATTR_SIZE     7\n#define BTRC_CHARSET_UTF8           0x006A\n\ntypedef uint8_t btrc_uid_t[BTRC_UID_SIZE];\n\ntypedef enum {\n    BTRC_FEAT_NONE = 0x00,    /* AVRCP 1.0 */\n    BTRC_FEAT_METADATA = 0x01,    /* AVRCP 1.3 */\n    BTRC_FEAT_ABSOLUTE_VOLUME = 0x02,    /* Supports TG role and volume sync */\n    BTRC_FEAT_BROWSE = 0x04,    /* AVRCP 1.4 and up, with Browsing support */\n} btrc_remote_features_t;\n\ntypedef enum {\n    BTRC_PLAYSTATE_STOPPED = 0x00,    /* Stopped */\n    BTRC_PLAYSTATE_PLAYING = 0x01,    /* Playing */\n    BTRC_PLAYSTATE_PAUSED = 0x02,    /* Paused  */\n    BTRC_PLAYSTATE_FWD_SEEK = 0x03,    /* Fwd Seek*/\n    BTRC_PLAYSTATE_REV_SEEK = 0x04,    /* Rev Seek*/\n    BTRC_PLAYSTATE_ERROR = 0xFF,    /* Error   */\n} btrc_play_status_t;\n\ntypedef enum {\n    BTRC_EVT_PLAY_STATUS_CHANGED = 0x01,\n    BTRC_EVT_TRACK_CHANGE = 0x02,\n    BTRC_EVT_TRACK_REACHED_END = 0x03,\n    BTRC_EVT_TRACK_REACHED_START = 0x04,\n    BTRC_EVT_PLAY_POS_CHANGED = 0x05,\n    BTRC_EVT_APP_SETTINGS_CHANGED = 0x08,\n    BTRC_EVT_NOW_PLAYING_CONTENT_CHANGED = 0x09,\n    BTRC_EVT_AVAILABLE_PLAYERS_CHANGED = 0x0a,\n    BTRC_EVT_ADDRESSED_PLAYER_CHANGED = 0x0b,\n} btrc_event_id_t;\n\n//used for Scope\ntypedef enum {\n    BTRC_EVT_MEDIA_PLAYLIST = 0,\n    BTRC_EVT_MEDIA_VIRTUALFILESYST = 1,\n    BTRC_EVT_SEARCH = 2,\n    BTRC_EVT_NOWPLAYING = 3,\n    BTRC_EVT_MAX_BROWSE = 4,\n} btrc_browse_folderitem_t;\n\ntypedef enum {\n    BTRC_NOTIFICATION_TYPE_INTERIM = 0,\n    BTRC_NOTIFICATION_TYPE_CHANGED = 1,\n    BTRC_NOTIFICATION_TYPE_REJECT = 2,\n} btrc_notification_type_t;\n\ntypedef enum {\n    BTRC_PLAYER_ATTR_EQUALIZER = 0x01,\n    BTRC_PLAYER_ATTR_REPEAT = 0x02,\n    BTRC_PLAYER_ATTR_SHUFFLE = 0x03,\n    BTRC_PLAYER_ATTR_SCAN = 0x04,\n} btrc_player_attr_t;\n\ntypedef enum {\n    BTRC_MEDIA_ATTR_TITLE = 0x01,\n    BTRC_MEDIA_ATTR_ARTIST = 0x02,\n    BTRC_MEDIA_ATTR_ALBUM = 0x03,\n    BTRC_MEDIA_ATTR_TRACK_NUM = 0x04,\n    BTRC_MEDIA_ATTR_NUM_TRACKS = 0x05,\n    BTRC_MEDIA_ATTR_GENRE = 0x06,\n    BTRC_MEDIA_ATTR_PLAYING_TIME = 0x07,\n} btrc_media_attr_t;\n\ntypedef enum {\n    BTRC_PLAYER_VAL_OFF_REPEAT = 0x01,\n    BTRC_PLAYER_VAL_SINGLE_REPEAT = 0x02,\n    BTRC_PLAYER_VAL_ALL_REPEAT = 0x03,\n    BTRC_PLAYER_VAL_GROUP_REPEAT = 0x04\n} btrc_player_repeat_val_t;\n\ntypedef enum {\n    BTRC_PLAYER_VAL_OFF_SHUFFLE = 0x01,\n    BTRC_PLAYER_VAL_ALL_SHUFFLE = 0x02,\n    BTRC_PLAYER_VAL_GROUP_SHUFFLE = 0x03\n} btrc_player_shuffle_val_t;\n\ntypedef enum {\n    BTRC_STS_BAD_CMD        = 0x00, /* Invalid command */\n    BTRC_STS_BAD_PARAM      = 0x01, /* Invalid parameter */\n    BTRC_STS_NOT_FOUND      = 0x02, /* Specified parameter is wrong or not found */\n    BTRC_STS_INTERNAL_ERR   = 0x03, /* Internal Error */\n    BTRC_STS_NO_ERROR       = 0x04  /* Operation Success */\n} btrc_status_t;\n\ntypedef enum {\n    BTRC_TYPE_MEDIA_PLAYER = 0x01,\n    BTRC_TYPE_FOLDER = 0x02,\n    BTRC_TYPE_MEDIA_ELEMENT = 0x03\n} btrc_folder_list_item_type_t;\n\ntypedef struct {\n    uint8_t num_attr;\n    uint8_t attr_ids[BTRC_MAX_APP_SETTINGS];\n    uint8_t attr_values[BTRC_MAX_APP_SETTINGS];\n} btrc_player_settings_t;\n\ntypedef struct {\n    uint32_t start_item;\n    uint32_t end_item;\n    uint32_t size;\n    uint32_t attrs[BTRC_MAX_ELEM_ATTR_SIZE];\n    uint8_t  attr_count;\n}btrc_getfolderitem_t;\n\ntypedef union\n{\n    btrc_play_status_t play_status;\n    btrc_uid_t track; /* queue position in NowPlaying */\n    uint32_t song_pos;\n    btrc_player_settings_t player_setting;\n    uint16_t player_id;\n} btrc_register_notification_t;\n\ntypedef struct {\n    uint8_t id; /* can be attr_id or value_id */\n    uint8_t text[BTRC_MAX_ATTR_STR_LEN];\n} btrc_player_setting_text_t;\n\ntypedef struct {\n    uint32_t attr_id;\n    uint8_t text[BTRC_MAX_ATTR_STR_LEN];\n} btrc_element_attr_val_t;\n\n/** Callback for the controller's supported feautres */\ntypedef void (* btrc_remote_features_callback)(bt_bdaddr_t *bd_addr,\n                                                      btrc_remote_features_t features);\n#define BTRC_FEATURE_MASK_SIZE 16\n\ntypedef uint8_t btrc_feature_mask_t[BTRC_FEATURE_MASK_SIZE];\n\ntypedef struct {\n    uint16_t              charset_id;\n    uint16_t              str_len;\n    uint8_t               *p_str;\n} btrc_player_full_name_t;\n\ntypedef struct\n{\n    uint32_t              sub_type;\n    uint16_t              player_id;\n    uint8_t               major_type;\n    uint8_t               play_status;\n    btrc_feature_mask_t   features;       /* Supported feature bit mask*/\n    btrc_player_full_name_t     name;           /* The player name, name length and character set id.*/\n} btrc_folder_list_item_player_t;\n\ntypedef struct\n{\n    uint64_t                    uid;\n    uint8_t                     type;\n    uint8_t                     playable;\n    btrc_player_full_name_t     name;\n} btrc_folder_list_item_folder_t;\n\ntypedef struct\n{\n    uint32_t                    attr_id;\n    btrc_player_full_name_t     name;\n} btrc_attr_entry_t;\n\ntypedef struct\n{\n    uint64_t                    uid;\n    uint8_t                     type;\n    uint8_t                     attr_count;\n    btrc_player_full_name_t     name;\n    btrc_attr_entry_t*          p_attr_list;\n} btrc_folder_list_item_media_t;\n\ntypedef struct {\n    uint16_t              str_len;\n    uint8_t               *p_str;\n} btrc_name_t;\n\n/* SetBrowsedPlayer */\ntypedef struct\n{\n    uint32_t              num_items;\n    uint16_t              uid_counter;\n    uint16_t              charset_id;\n    uint8_t               status;\n    uint8_t               folder_depth;\n    btrc_name_t           *p_folders;\n} btrc_set_browsed_player_rsp_t;\n\ntypedef struct\n{\n    uint8_t                          item_type;\n    union\n    {\n        btrc_folder_list_item_player_t   player;\n        btrc_folder_list_item_folder_t   folder;\n        btrc_folder_list_item_media_t    media;\n    } u;\n} btrc_folder_list_item_t;\n\n/* GetFolderItems */\ntypedef struct\n{\n    uint16_t                  uid_counter;\n    uint16_t                  item_count;\n    uint8_t                   status;\n    btrc_folder_list_item_t   *p_item_list;\n} btrc_folder_list_entries_t;\n\n/** Callback for play status request */\ntypedef void (* btrc_get_play_status_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for list player application attributes (Shuffle, Repeat,...) */\ntypedef void (* btrc_list_player_app_attr_callback)(bt_bdaddr_t *bd_addr);\n\n/** Callback for list player application attributes (Shuffle, Repeat,...) */\ntypedef void (* btrc_list_player_app_values_callback)(btrc_player_attr_t attr_id,\n        bt_bdaddr_t *bd_addr);\n\n/** Callback for getting the current player application settings value\n**  num_attr: specifies the number of attribute ids contained in p_attrs\n*/\ntypedef void (* btrc_get_player_app_value_callback) (uint8_t num_attr, btrc_player_attr_t *p_attrs,\n        bt_bdaddr_t *bd_addr);\n\n/** Callback for getting the player application settings attributes' text\n**  num_attr: specifies the number of attribute ids contained in p_attrs\n*/\ntypedef void (* btrc_get_player_app_attrs_text_callback) (uint8_t num_attr,\n        btrc_player_attr_t *p_attrs, bt_bdaddr_t *bd_addr);\n\n/** Callback for getting the player application settings values' text\n**  num_attr: specifies the number of value ids contained in p_vals\n*/\ntypedef void (* btrc_get_player_app_values_text_callback) (uint8_t attr_id,\n         uint8_t num_val, uint8_t *p_vals, bt_bdaddr_t *bd_addr);\n\n/** Callback for setting the player application settings values */\ntypedef void (* btrc_set_player_app_value_callback) (btrc_player_settings_t *p_vals,\n        bt_bdaddr_t *bd_addr);\n\n/** Callback to fetch the get element attributes of the current song\n**  num_attr: specifies the number of attributes requested in p_attrs\n*/\ntypedef void (* btrc_get_element_attr_callback) (uint8_t num_attr, btrc_media_attr_t *p_attrs,\n        bt_bdaddr_t *bd_addr);\n\n/** Callback for register notification (Play state change/track change/...)\n**  param: Is only valid if event_id is BTRC_EVT_PLAY_POS_CHANGED\n*/\ntypedef void (* btrc_register_notification_callback) (btrc_event_id_t event_id, uint32_t param,\n        bt_bdaddr_t *bd_addr);\n\n/* AVRCP 1.4 Enhancements */\n/** Callback for volume change on CT\n**  volume: Current volume setting on the CT (0-127)\n*/\ntypedef void (* btrc_volume_change_callback) (uint8_t volume, uint8_t ctype, bt_bdaddr_t *bd_addr);\n\n/** Callback for passthrough commands */\ntypedef void (* btrc_passthrough_cmd_callback) (int id, int key_state, bt_bdaddr_t *bd_addr);\n\n/** BT-RC Target callback structure. */\n\ntypedef void (* btrc_get_folder_items_callback) (btrc_browse_folderitem_t id,\n                  btrc_getfolderitem_t *param, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_set_addressed_player_callback) (uint32_t player_id, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_set_browsed_player_callback) (uint32_t player_id, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_change_path_callback) (uint8_t direction, uint64_t uid, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_play_item_callback) (uint8_t scope, uint64_t uid, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_get_item_attr_callback) (uint8_t scope, uint64_t uid,\n                  uint8_t num_attr, btrc_media_attr_t *p_attrs, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_connection_state_callback) (bool state, bt_bdaddr_t *bd_addr);\n\ntypedef struct {\n    /** set to sizeof(BtRcCallbacks) */\n    size_t      size;\n    btrc_remote_features_callback               remote_features_cb;\n    btrc_get_play_status_callback               get_play_status_cb;\n    btrc_list_player_app_attr_callback          list_player_app_attr_cb;\n    btrc_list_player_app_values_callback        list_player_app_values_cb;\n    btrc_get_player_app_value_callback          get_player_app_value_cb;\n    btrc_get_player_app_attrs_text_callback     get_player_app_attrs_text_cb;\n    btrc_get_player_app_values_text_callback    get_player_app_values_text_cb;\n    btrc_set_player_app_value_callback          set_player_app_value_cb;\n    btrc_get_element_attr_callback              get_element_attr_cb;\n    btrc_register_notification_callback         register_notification_cb;\n    btrc_volume_change_callback                 volume_change_cb;\n    btrc_passthrough_cmd_callback               passthrough_cmd_cb;\n    btrc_get_folder_items_callback              get_folderitems_cb;\n    btrc_set_addressed_player_callback          set_addrplayer_cb;\n    btrc_set_browsed_player_callback            set_browsed_player_cb;\n    btrc_change_path_callback                   change_path_cb;\n    btrc_play_item_callback                     play_item_cb;\n    btrc_get_item_attr_callback                 get_item_attr_cb;\n    btrc_connection_state_callback              connection_state_cb;\n} btrc_callbacks_t;\n\n/** Represents the standard BT-RC AVRCP Target interface. */\ntypedef struct {\n\n    /** set to sizeof(BtRcInterface) */\n    size_t          size;\n    /**\n     * Register the BtRc callbacks\n     */\n    bt_status_t (*init)( btrc_callbacks_t* callbacks , int max_avrcp_connections);\n\n    /** Respose to GetPlayStatus request. Contains the current\n    **  1. Play status\n    **  2. Song duration/length\n    **  3. Song position\n    */\n    bt_status_t (*get_play_status_rsp)( btrc_play_status_t play_status, uint32_t song_len,\n                 uint32_t song_pos, bt_bdaddr_t *bd_addr);\n\n    /** Lists the support player application attributes (Shuffle/Repeat/...)\n    **  num_attr: Specifies the number of attributes contained in the pointer p_attrs\n    */\n    bt_status_t (*list_player_app_attr_rsp)( uint8_t num_attr, btrc_player_attr_t *p_attrs,\n            bt_bdaddr_t *bd_addr);\n\n    /** Lists the support player application attributes (Shuffle Off/On/Group)\n    **  num_val: Specifies the number of values contained in the pointer p_vals\n    */\n    bt_status_t (*list_player_app_value_rsp)( uint8_t num_val, uint8_t *p_vals,\n            bt_bdaddr_t *bd_addr);\n\n    /** Returns the current application attribute values for each of the specified attr_id */\n    bt_status_t (*get_player_app_value_rsp)( btrc_player_settings_t *p_vals,\n            bt_bdaddr_t *bd_addr);\n\n    /** Returns the application attributes text (\"Shuffle\"/\"Repeat\"/...)\n    **  num_attr: Specifies the number of attributes' text contained in the pointer p_attrs\n    */\n    bt_status_t (*get_player_app_attr_text_rsp)( int num_attr, btrc_player_setting_text_t *p_attrs,\n            bt_bdaddr_t *bd_addr);\n\n    /** Returns the application attributes text (\"Shuffle\"/\"Repeat\"/...)\n    **  num_attr: Specifies the number of attribute values' text contained in the pointer p_vals\n    */\n    bt_status_t (*get_player_app_value_text_rsp)( int num_val, btrc_player_setting_text_t *p_vals,\n            bt_bdaddr_t *bd_addr);\n\n    /** Returns the current songs' element attributes text (\"Title\"/\"Album\"/\"Artist\")\n    **  num_attr: Specifies the number of attributes' text contained in the pointer p_attrs\n    */\n    bt_status_t (*get_element_attr_rsp)( uint8_t num_attr, btrc_element_attr_val_t *p_attrs,\n            bt_bdaddr_t *bd_addr);\n\n    /** Response to set player attribute request (\"Shuffle\"/\"Repeat\")\n    **  rsp_status: Status of setting the player attributes for the current media player\n    */\n    bt_status_t (*set_player_app_value_rsp)(btrc_status_t rsp_status, bt_bdaddr_t *bd_addr);\n\n    /* Response to the register notification request (Play state change/track change/...).\n    ** event_id: Refers to the event_id this notification change corresponds too\n    ** type: Response type - interim/changed\n    ** p_params: Based on the event_id, this parameter should be populated\n    */\n    bt_status_t (*register_notification_rsp)(btrc_event_id_t event_id,\n                                             btrc_notification_type_t type,\n                                             btrc_register_notification_t *p_param,\n                                             bt_bdaddr_t *bd_addr);\n\n    /* AVRCP 1.4 enhancements */\n\n    /**Send current volume setting to remote side. Support limited to SetAbsoluteVolume\n    ** This can be enhanced to support Relative Volume (AVRCP 1.0).\n    ** With RelateVolume, we will send VOLUME_UP/VOLUME_DOWN opposed to absolute volume level\n    ** volume: Should be in the range 0-127. bit7 is reseved and cannot be set\n    */\n    bt_status_t (*set_volume)(uint8_t volume, bt_bdaddr_t *bd_addr);\n    bt_status_t (*get_folder_items_rsp) (btrc_folder_list_entries_t *p_param, bt_bdaddr_t *bd_addr);\n\n    bt_status_t (*set_addressed_player_rsp) (btrc_status_t status_code, bt_bdaddr_t *bd_addr);\n    bt_status_t (*set_browsed_player_rsp) (btrc_set_browsed_player_rsp_t *p_param,\n            bt_bdaddr_t *bd_addr);\n    bt_status_t (*change_path_rsp) (uint8_t status_code, uint32_t item_count,\n            bt_bdaddr_t *bd_addr);\n    bt_status_t (*play_item_rsp) (uint8_t status_code, bt_bdaddr_t *bd_addr);\n    bt_status_t (*get_item_attr_rsp)( uint8_t num_attr, btrc_element_attr_val_t *p_attrs,\n            bt_bdaddr_t *bd_addr);\n    bt_status_t (*is_device_active_in_handoff) (bt_bdaddr_t *bd_addr);\n\n    /** Closes the interface. */\n    void  (*cleanup)( void );\n} btrc_interface_t;\n\n\ntypedef void (* btrc_passthrough_rsp_callback) (int id, int key_state);\n\ntypedef void (* btrc_connection_state_callback) (bool state, bt_bdaddr_t *bd_addr);\n\ntypedef void (* btrc_ctrl_getrcfeatures_callback) (bt_bdaddr_t *bd_addr, int features);\n\ntypedef void (* btrc_ctrl_getcapability_rsp_callback) (bt_bdaddr_t *bd_addr, int cap_id,\n                                 uint32_t* supported_values, int num_supported, uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_listplayerappsettingattrib_rsp_callback) (bt_bdaddr_t *bd_addr,\n                                     uint8_t* supported_attribs, int num_attrib, uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_listplayerappsettingvalue_rsp_callback) (bt_bdaddr_t *bd_addr,\n                                        uint8_t* supported_val, uint8_t num_supported, uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_currentplayerappsetting_rsp_callback) (bt_bdaddr_t *bd_addr,uint8_t* supported_ids,\n                                                 uint8_t* supported_val, uint8_t num_attrib, uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_setplayerapplicationsetting_rsp_callback) (bt_bdaddr_t *bd_addr,uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_notification_rsp_callback) (bt_bdaddr_t *bd_addr, uint8_t rsp_type,\n                                 int rsp_len, uint8_t* notification_rsp);\n\ntypedef void (* btrc_ctrl_getelementattrib_rsp_callback) (bt_bdaddr_t *bd_addr, uint8_t num_attributes,\n                                                          int rsp_len, uint8_t* attrib_rsp, uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_getplaystatus_rsp_callback) (bt_bdaddr_t *bd_addr, int param_len, uint8_t* play_status_rsp\n                                                                           ,uint8_t rsp_type);\n\ntypedef void (* btrc_ctrl_setabsvol_cmd_callback) (bt_bdaddr_t *bd_addr, uint8_t abs_vol);\n\ntypedef void (* btrc_ctrl_registernotification_abs_vol_callback) (bt_bdaddr_t *bd_addr);\n/** BT-RC Controller callback structure. */\ntypedef struct {\n    /** set to sizeof(BtRcCallbacks) */\n    size_t      size;\n    btrc_passthrough_rsp_callback                              passthrough_rsp_cb;\n    btrc_connection_state_callback                             connection_state_cb;\n    btrc_ctrl_getrcfeatures_callback                           getrcfeatures_cb;\n    btrc_ctrl_getcapability_rsp_callback                       getcap_rsp_cb;\n    btrc_ctrl_listplayerappsettingattrib_rsp_callback          listplayerappsettingattrib_rsp_cb;\n    btrc_ctrl_listplayerappsettingvalue_rsp_callback           listplayerappsettingvalue_rsp_cb;\n    btrc_ctrl_currentplayerappsetting_rsp_callback             currentplayerappsetting_rsp_cb;\n    btrc_ctrl_setplayerapplicationsetting_rsp_callback         setplayerappsetting_rsp_cb;\n    btrc_ctrl_notification_rsp_callback                        notification_rsp_cb;\n    btrc_ctrl_getelementattrib_rsp_callback                    getelementattrib_rsp_cb;\n    btrc_ctrl_getplaystatus_rsp_callback                       getplaystatus_rsp_cb;\n    btrc_ctrl_setabsvol_cmd_callback                           setabsvol_cmd_cb;\n    btrc_ctrl_registernotification_abs_vol_callback            registernotification_absvol_cb;\n} btrc_ctrl_callbacks_t;\n\n/** Represents the standard BT-RC AVRCP Controller interface. */\ntypedef struct {\n\n    /** set to sizeof(BtRcInterface) */\n    size_t          size;\n    /**\n     * Register the BtRc callbacks\n     */\n    bt_status_t (*init)( btrc_ctrl_callbacks_t* callbacks );\n\n    /** send pass through command to target */\n    bt_status_t (*send_pass_through_cmd) ( bt_bdaddr_t *bd_addr, uint8_t key_code,\n            uint8_t key_state );\n\n    /** send get_cap command to target */\n    bt_status_t (*getcapabilities_cmd) (uint8_t cap_id);\n\n    /** send command to get supported player application settings to  target */\n    bt_status_t (*list_player_app_setting_attrib_cmd) (void);\n\n    /** send command to get supported  values of player application settings for a\n     * particular attribute to  target */\n    bt_status_t (*list_player_app_setting_value_cmd) (uint8_t attrib_id);\n\n    /** send command to get current player attributes to target */\n    bt_status_t (*get_player_app_setting_cmd) (uint8_t num_attrib, uint8_t* attrib_ids);\n\n    /** send command to set player applicaiton setting attributes to target */\n    bt_status_t (*set_player_app_setting_cmd) (uint8_t num_attrib, uint8_t* attrib_ids, uint8_t* attrib_vals);\n\n    /** send command to register for supported notificaiton events to target */\n    bt_status_t (*register_notification_cmd) (uint8_t event_id, uint32_t event_value);\n\n    /** send command to get element attribute  to target */\n    bt_status_t (*get_element_attribute_cmd) (uint8_t num_attribute, uint32_t attribute_id);\n\n    /** send command to get play status to target */\n    bt_status_t (*get_play_status_cmd) (void);\n\n    /** send rsp to set_abs_vol received from target */\n    bt_status_t (*send_abs_vol_rsp) (uint8_t abs_vol);\n\n    /** send notificaiton rsp for abs vol to target */\n    bt_status_t (*send_register_abs_vol_rsp) (uint8_t rsp_type, uint8_t abs_vol);\n\n    /** Closes the interface. */\n    void  (*cleanup)( void );\n} btrc_ctrl_interface_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_BT_RC_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_sdp.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include \"bluetooth.h\"\n\n#define SDP_OPP_SUPPORTED_FORMATS_MAX_LENGTH 15\n\n__BEGIN_DECLS\n\n/**\n * These events are handled by the state machine\n */\ntypedef enum {\n    SDP_TYPE_RAW,        // Used to carry raw SDP search data for unknown UUIDs\n    SDP_TYPE_MAP_MAS,    // Message Access Profile - Server\n    SDP_TYPE_MAP_MNS,    // Message Access Profile - Client (Notification Server)\n    SDP_TYPE_PBAP_PSE,   // Phone Book Profile - Server\n    SDP_TYPE_PBAP_PCE,   // Phone Book Profile - Client\n    SDP_TYPE_OPP_SERVER, // Object Push Profile\n    SDP_TYPE_SAP_SERVER  // SIM Access Profile\n} bluetooth_sdp_types;\n\ntypedef struct _bluetooth_sdp_hdr {\n    bluetooth_sdp_types type;\n    bt_uuid_t   uuid;\n    uint32_t    service_name_length;\n    char       *service_name;\n    int32_t     rfcomm_channel_number;\n    int32_t     l2cap_psm;\n    int32_t     profile_version;\n} bluetooth_sdp_hdr;\n\n/**\n * Some signals need additional pointers, hence we introduce a\n * generic way to handle these pointers.\n */\ntypedef struct _bluetooth_sdp_hdr_overlay {\n    bluetooth_sdp_types type;\n    bt_uuid_t   uuid;\n    uint32_t    service_name_length;\n    char       *service_name;\n    int32_t     rfcomm_channel_number;\n    int32_t     l2cap_psm;\n    int32_t     profile_version;\n\n    // User pointers, only used for some signals - see bluetooth_sdp_ops_record\n    int         user1_ptr_len;\n    uint8_t    *user1_ptr;\n    int         user2_ptr_len;\n    uint8_t    *user2_ptr;\n} bluetooth_sdp_hdr_overlay;\n\ntypedef struct _bluetooth_sdp_mas_record {\n    bluetooth_sdp_hdr_overlay hdr;\n    uint32_t    mas_instance_id;\n    uint32_t    supported_features;\n    uint32_t    supported_message_types;\n} bluetooth_sdp_mas_record;\n\ntypedef struct _bluetooth_sdp_mns_record {\n    bluetooth_sdp_hdr_overlay hdr;\n    uint32_t    supported_features;\n} bluetooth_sdp_mns_record;\n\ntypedef struct _bluetooth_sdp_pse_record {\n    bluetooth_sdp_hdr_overlay hdr;\n    uint32_t    supported_features;\n    uint32_t    supported_repositories;\n} bluetooth_sdp_pse_record;\n\ntypedef struct _bluetooth_sdp_pce_record {\n    bluetooth_sdp_hdr_overlay hdr;\n} bluetooth_sdp_pce_record;\n\ntypedef struct _bluetooth_sdp_ops_record {\n    bluetooth_sdp_hdr_overlay hdr;\n    int         supported_formats_list_len;\n    uint8_t     supported_formats_list[SDP_OPP_SUPPORTED_FORMATS_MAX_LENGTH];\n} bluetooth_sdp_ops_record;\n\ntypedef struct _bluetooth_sdp_sap_record {\n    bluetooth_sdp_hdr_overlay hdr;\n} bluetooth_sdp_sap_record;\n\ntypedef union {\n    bluetooth_sdp_hdr_overlay   hdr;\n    bluetooth_sdp_mas_record    mas;\n    bluetooth_sdp_mns_record    mns;\n    bluetooth_sdp_pse_record    pse;\n    bluetooth_sdp_pce_record    pce;\n    bluetooth_sdp_ops_record    ops;\n    bluetooth_sdp_sap_record    sap;\n} bluetooth_sdp_record;\n\n\n/** Callback for SDP search */\ntypedef void (*btsdp_search_callback)(bt_status_t status, bt_bdaddr_t *bd_addr, uint8_t* uuid, int num_records, bluetooth_sdp_record *records);\n\ntypedef struct {\n    /** Set to sizeof(btsdp_callbacks_t) */\n    size_t      size;\n    btsdp_search_callback  sdp_search_cb;\n} btsdp_callbacks_t;\n\ntypedef struct {\n    /** Set to size of this struct */\n    size_t size;\n\n    /** Register BT SDP search callbacks */\n    bt_status_t (*init)(btsdp_callbacks_t *callbacks);\n\n    /** Unregister BT SDP */\n    bt_status_t (*deinit)();\n\n    /** Search for SDP records with specific uuid on remote device */\n    bt_status_t (*sdp_search)(bt_bdaddr_t *bd_addr,  const uint8_t* uuid);\n\n    /**\n     * Use listen in the socket interface to create rfcomm and/or l2cap PSM channels,\n     * (without UUID and service_name and set the BTSOCK_FLAG_NO_SDP flag in flags).\n     * Then use createSdpRecord to create the SDP record associated with the rfcomm/l2cap channels.\n     *\n     * Returns a handle to the SDP record, which can be parsed to remove_sdp_record.\n     *\n     * record           (in) The SDP record to create\n     * record_handle    (out)The corresponding record handle will be written to this pointer.\n     */\n    bt_status_t (*create_sdp_record)(bluetooth_sdp_record *record, int* record_handle);\n\n    /** Remove a SDP record created by createSdpRecord */\n    bt_status_t (*remove_sdp_record)(int sdp_handle);\n} btsdp_interface_t;\n\n__END_DECLS\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/bt_sock.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n__BEGIN_DECLS\n\n#define BTSOCK_FLAG_ENCRYPT 1\n#define BTSOCK_FLAG_AUTH (1 << 1)\n#define BTSOCK_FLAG_NO_SDP (1 << 2)\n#define BTSOCK_FLAG_AUTH_MITM (1 << 3)\n#define BTSOCK_FLAG_AUTH_16_DIGIT (1 << 4)\n\ntypedef enum {\n    BTSOCK_RFCOMM = 1,\n    BTSOCK_SCO = 2,\n    BTSOCK_L2CAP = 3\n} btsock_type_t;\n\ntypedef enum {\n    BTSOCK_OPT_GET_MODEM_BITS = 1,\n    BTSOCK_OPT_SET_MODEM_BITS = 2,\n    BTSOCK_OPT_CLR_MODEM_BITS = 3,\n} btsock_option_type_t;\n\n/** Represents the standard BT SOCKET interface. */\ntypedef struct {\n    short size;\n    bt_bdaddr_t bd_addr;\n    int channel;\n    int status;\n\n    // The writer must make writes using a buffer of this maximum size\n    // to avoid loosing data. (L2CAP only)\n    unsigned short max_tx_packet_size;\n\n    // The reader must read using a buffer of at least this size to avoid\n    // loosing data. (L2CAP only)\n    unsigned short max_rx_packet_size;\n} __attribute__((packed)) sock_connect_signal_t;\n\ntypedef struct {\n    /** set to size of this struct*/\n    size_t          size;\n\n    /**\n     * Listen to a RFCOMM UUID or channel. It returns the socket fd from which\n     * btsock_connect_signal can be read out when a remote device connected.\n     * If neither a UUID nor a channel is provided, a channel will be allocated\n     * and a service record can be created providing the channel number to\n     * create_sdp_record(...) in bt_sdp.\n     */\n    bt_status_t (*listen)(btsock_type_t type, const char* service_name,\n            const uint8_t* service_uuid, int channel, int* sock_fd, int flags);\n\n    /**\n     * Connect to a RFCOMM UUID channel of remote device, It returns the socket fd from which\n     * the btsock_connect_signal and a new socket fd to be accepted can be read out when connected\n     */\n    bt_status_t (*connect)(const bt_bdaddr_t *bd_addr, btsock_type_t type, const uint8_t* uuid,\n            int channel, int* sock_fd, int flags);\n\n    /*\n     * get socket option of rfcomm channel socket.\n     */\n    bt_status_t (*get_sock_opt)(btsock_type_t type, int channel, btsock_option_type_t option_name,\n            void *option_value, int *option_len);\n    /*\n\n     * set socket option of rfcomm channel socket.\n     */\n    bt_status_t (*set_sock_opt)(btsock_type_t type, int channel, btsock_option_type_t option_name,\n            void *option_value, int option_len);\n\n} btsock_interface_t;\n\n__END_DECLS\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/camera.h",
    "content": "/*\n * Copyright (C) 2010-2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_CAMERA_H\n#define ANDROID_INCLUDE_CAMERA_H\n\n#include \"camera_common.h\"\n\n/**\n * Camera device HAL, initial version [ CAMERA_DEVICE_API_VERSION_1_0 ]\n *\n * DEPRECATED. New devices should use Camera HAL v3.2 or newer.\n *\n * Supports the android.hardware.Camera API, and the android.hardware.camera2\n * API in legacy mode only.\n *\n * Camera devices that support this version of the HAL must return a value in\n * the range HARDWARE_DEVICE_API_VERSION(0,0)-(1,FF) in\n * camera_device_t.common.version. CAMERA_DEVICE_API_VERSION_1_0 is the\n * recommended value.\n *\n * Camera modules that implement version 2.0 or higher of camera_module_t must\n * also return the value of camera_device_t.common.version in\n * camera_info_t.device_version.\n *\n * See camera_common.h for more details.\n */\n\n__BEGIN_DECLS\n\nstruct camera_memory;\ntypedef void (*camera_release_memory)(struct camera_memory *mem);\n\ntypedef struct camera_memory {\n    void *data;\n    size_t size;\n    void *handle;\n    camera_release_memory release;\n} camera_memory_t;\n\ntypedef camera_memory_t* (*camera_request_memory)(int fd, size_t buf_size, unsigned int num_bufs,\n                                                  void *user);\n\ntypedef void (*camera_notify_callback)(int32_t msg_type,\n        int32_t ext1,\n        int32_t ext2,\n        void *user);\n\ntypedef void (*camera_data_callback)(int32_t msg_type,\n        const camera_memory_t *data, unsigned int index,\n        camera_frame_metadata_t *metadata, void *user);\n\ntypedef void (*camera_data_timestamp_callback)(int64_t timestamp,\n        int32_t msg_type,\n        const camera_memory_t *data, unsigned int index,\n        void *user);\n\n#define HAL_CAMERA_PREVIEW_WINDOW_TAG 0xcafed00d\n\ntypedef struct preview_stream_ops {\n    int (*dequeue_buffer)(struct preview_stream_ops* w,\n                          buffer_handle_t** buffer, int *stride);\n    int (*enqueue_buffer)(struct preview_stream_ops* w,\n                buffer_handle_t* buffer);\n    int (*cancel_buffer)(struct preview_stream_ops* w,\n                buffer_handle_t* buffer);\n    int (*set_buffer_count)(struct preview_stream_ops* w, int count);\n    int (*set_buffers_geometry)(struct preview_stream_ops* pw,\n                int w, int h, int format);\n    int (*set_crop)(struct preview_stream_ops *w,\n                int left, int top, int right, int bottom);\n    int (*set_usage)(struct preview_stream_ops* w, int usage);\n    int (*set_swap_interval)(struct preview_stream_ops *w, int interval);\n    int (*get_min_undequeued_buffer_count)(const struct preview_stream_ops *w,\n                int *count);\n    int (*lock_buffer)(struct preview_stream_ops* w,\n                buffer_handle_t* buffer);\n    // Timestamps are measured in nanoseconds, and must be comparable\n    // and monotonically increasing between two frames in the same\n    // preview stream. They do not need to be comparable between\n    // consecutive or parallel preview streams, cameras, or app runs.\n    int (*set_timestamp)(struct preview_stream_ops *w, int64_t timestamp);\n} preview_stream_ops_t;\n\nstruct camera_device;\ntypedef struct camera_device_ops {\n    /** Set the ANativeWindow to which preview frames are sent */\n    int (*set_preview_window)(struct camera_device *,\n            struct preview_stream_ops *window);\n\n    /** Set the notification and data callbacks */\n    void (*set_callbacks)(struct camera_device *,\n            camera_notify_callback notify_cb,\n            camera_data_callback data_cb,\n            camera_data_timestamp_callback data_cb_timestamp,\n            camera_request_memory get_memory,\n            void *user);\n\n    /**\n     * The following three functions all take a msg_type, which is a bitmask of\n     * the messages defined in include/ui/Camera.h\n     */\n\n    /**\n     * Enable a message, or set of messages.\n     */\n    void (*enable_msg_type)(struct camera_device *, int32_t msg_type);\n\n    /**\n     * Disable a message, or a set of messages.\n     *\n     * Once received a call to disableMsgType(CAMERA_MSG_VIDEO_FRAME), camera\n     * HAL should not rely on its client to call releaseRecordingFrame() to\n     * release video recording frames sent out by the cameral HAL before and\n     * after the disableMsgType(CAMERA_MSG_VIDEO_FRAME) call. Camera HAL\n     * clients must not modify/access any video recording frame after calling\n     * disableMsgType(CAMERA_MSG_VIDEO_FRAME).\n     */\n    void (*disable_msg_type)(struct camera_device *, int32_t msg_type);\n\n    /**\n     * Query whether a message, or a set of messages, is enabled.  Note that\n     * this is operates as an AND, if any of the messages queried are off, this\n     * will return false.\n     */\n    int (*msg_type_enabled)(struct camera_device *, int32_t msg_type);\n\n    /**\n     * Start preview mode.\n     */\n    int (*start_preview)(struct camera_device *);\n\n    /**\n     * Stop a previously started preview.\n     */\n    void (*stop_preview)(struct camera_device *);\n\n    /**\n     * Returns true if preview is enabled.\n     */\n    int (*preview_enabled)(struct camera_device *);\n\n    /**\n     * Request the camera HAL to store meta data or real YUV data in the video\n     * buffers sent out via CAMERA_MSG_VIDEO_FRAME for a recording session. If\n     * it is not called, the default camera HAL behavior is to store real YUV\n     * data in the video buffers.\n     *\n     * This method should be called before startRecording() in order to be\n     * effective.\n     *\n     * If meta data is stored in the video buffers, it is up to the receiver of\n     * the video buffers to interpret the contents and to find the actual frame\n     * data with the help of the meta data in the buffer. How this is done is\n     * outside of the scope of this method.\n     *\n     * Some camera HALs may not support storing meta data in the video buffers,\n     * but all camera HALs should support storing real YUV data in the video\n     * buffers. If the camera HAL does not support storing the meta data in the\n     * video buffers when it is requested to do do, INVALID_OPERATION must be\n     * returned. It is very useful for the camera HAL to pass meta data rather\n     * than the actual frame data directly to the video encoder, since the\n     * amount of the uncompressed frame data can be very large if video size is\n     * large.\n     *\n     * @param enable if true to instruct the camera HAL to store\n     *        meta data in the video buffers; false to instruct\n     *        the camera HAL to store real YUV data in the video\n     *        buffers.\n     *\n     * @return OK on success.\n     */\n    int (*store_meta_data_in_buffers)(struct camera_device *, int enable);\n\n    /**\n     * Start record mode. When a record image is available, a\n     * CAMERA_MSG_VIDEO_FRAME message is sent with the corresponding\n     * frame. Every record frame must be released by a camera HAL client via\n     * releaseRecordingFrame() before the client calls\n     * disableMsgType(CAMERA_MSG_VIDEO_FRAME). After the client calls\n     * disableMsgType(CAMERA_MSG_VIDEO_FRAME), it is the camera HAL's\n     * responsibility to manage the life-cycle of the video recording frames,\n     * and the client must not modify/access any video recording frames.\n     */\n    int (*start_recording)(struct camera_device *);\n\n    /**\n     * Stop a previously started recording.\n     */\n    void (*stop_recording)(struct camera_device *);\n\n    /**\n     * Returns true if recording is enabled.\n     */\n    int (*recording_enabled)(struct camera_device *);\n\n    /**\n     * Release a record frame previously returned by CAMERA_MSG_VIDEO_FRAME.\n     *\n     * It is camera HAL client's responsibility to release video recording\n     * frames sent out by the camera HAL before the camera HAL receives a call\n     * to disableMsgType(CAMERA_MSG_VIDEO_FRAME). After it receives the call to\n     * disableMsgType(CAMERA_MSG_VIDEO_FRAME), it is the camera HAL's\n     * responsibility to manage the life-cycle of the video recording frames.\n     */\n    void (*release_recording_frame)(struct camera_device *,\n                    const void *opaque);\n\n    /**\n     * Start auto focus, the notification callback routine is called with\n     * CAMERA_MSG_FOCUS once when focusing is complete. autoFocus() will be\n     * called again if another auto focus is needed.\n     */\n    int (*auto_focus)(struct camera_device *);\n\n    /**\n     * Cancels auto-focus function. If the auto-focus is still in progress,\n     * this function will cancel it. Whether the auto-focus is in progress or\n     * not, this function will return the focus position to the default.  If\n     * the camera does not support auto-focus, this is a no-op.\n     */\n    int (*cancel_auto_focus)(struct camera_device *);\n\n    /**\n     * Take a picture.\n     */\n    int (*take_picture)(struct camera_device *);\n\n    /**\n     * Cancel a picture that was started with takePicture. Calling this method\n     * when no picture is being taken is a no-op.\n     */\n    int (*cancel_picture)(struct camera_device *);\n\n    /**\n     * Set the camera parameters. This returns BAD_VALUE if any parameter is\n     * invalid or not supported.\n     */\n    int (*set_parameters)(struct camera_device *, const char *parms);\n\n    /** Retrieve the camera parameters.  The buffer returned by the camera HAL\n        must be returned back to it with put_parameters, if put_parameters\n        is not NULL.\n     */\n    char *(*get_parameters)(struct camera_device *);\n\n    /** The camera HAL uses its own memory to pass us the parameters when we\n        call get_parameters.  Use this function to return the memory back to\n        the camera HAL, if put_parameters is not NULL.  If put_parameters\n        is NULL, then you have to use free() to release the memory.\n    */\n    void (*put_parameters)(struct camera_device *, char *);\n\n    /**\n     * Send command to camera driver.\n     */\n    int (*send_command)(struct camera_device *,\n                int32_t cmd, int32_t arg1, int32_t arg2);\n\n    /**\n     * Release the hardware resources owned by this object.  Note that this is\n     * *not* done in the destructor.\n     */\n    void (*release)(struct camera_device *);\n\n    /**\n     * Dump state of the camera hardware\n     */\n    int (*dump)(struct camera_device *, int fd);\n} camera_device_ops_t;\n\ntypedef struct camera_device {\n    /**\n     * camera_device.common.version must be in the range\n     * HARDWARE_DEVICE_API_VERSION(0,0)-(1,FF). CAMERA_DEVICE_API_VERSION_1_0 is\n     * recommended.\n     */\n    hw_device_t common;\n    camera_device_ops_t *ops;\n    void *priv;\n} camera_device_t;\n\n__END_DECLS\n\n#endif /* #ifdef ANDROID_INCLUDE_CAMERA_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/camera2.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_CAMERA2_H\n#define ANDROID_INCLUDE_CAMERA2_H\n\n#include \"camera_common.h\"\n#include \"system/camera_metadata.h\"\n\n/**\n * Camera device HAL 2.1 [ CAMERA_DEVICE_API_VERSION_2_0, CAMERA_DEVICE_API_VERSION_2_1 ]\n *\n * DEPRECATED. New devices should use Camera HAL v3.2 or newer.\n *\n * Supports the android.hardware.Camera API, and the android.hardware.camera2\n * API in legacy mode only.\n *\n * Camera devices that support this version of the HAL must return\n * CAMERA_DEVICE_API_VERSION_2_1 in camera_device_t.common.version and in\n * camera_info_t.device_version (from camera_module_t.get_camera_info).\n *\n * Camera modules that may contain version 2.x devices must implement at least\n * version 2.0 of the camera module interface (as defined by\n * camera_module_t.common.module_api_version).\n *\n * See camera_common.h for more versioning details.\n *\n * Version history:\n *\n * 2.0: CAMERA_DEVICE_API_VERSION_2_0. Initial release (Android 4.2):\n *      - Sufficient for implementing existing android.hardware.Camera API.\n *      - Allows for ZSL queue in camera service layer\n *      - Not tested for any new features such manual capture control,\n *        Bayer RAW capture, reprocessing of RAW data.\n *\n * 2.1: CAMERA_DEVICE_API_VERSION_2_1. Support per-device static metadata:\n *      - Add get_instance_metadata() method to retrieve metadata that is fixed\n *        after device open, but may be variable between open() calls.\n */\n\n__BEGIN_DECLS\n\nstruct camera2_device;\n\n/**********************************************************************\n *\n * Input/output stream buffer queue interface definitions\n *\n */\n\n/**\n * Output image stream queue interface. A set of these methods is provided to\n * the HAL device in allocate_stream(), and are used to interact with the\n * gralloc buffer queue for that stream. They may not be called until after\n * allocate_stream returns.\n */\ntypedef struct camera2_stream_ops {\n    /**\n     * Get a buffer to fill from the queue. The size and format of the buffer\n     * are fixed for a given stream (defined in allocate_stream), and the stride\n     * should be queried from the platform gralloc module. The gralloc buffer\n     * will have been allocated based on the usage flags provided by\n     * allocate_stream, and will be locked for use.\n     */\n    int (*dequeue_buffer)(const struct camera2_stream_ops* w,\n            buffer_handle_t** buffer);\n\n    /**\n     * Push a filled buffer to the stream to be used by the consumer.\n     *\n     * The timestamp represents the time at start of exposure of the first row\n     * of the image; it must be from a monotonic clock, and is measured in\n     * nanoseconds. The timestamps do not need to be comparable between\n     * different cameras, or consecutive instances of the same camera. However,\n     * they must be comparable between streams from the same camera. If one\n     * capture produces buffers for multiple streams, each stream must have the\n     * same timestamp for that buffer, and that timestamp must match the\n     * timestamp in the output frame metadata.\n     */\n    int (*enqueue_buffer)(const struct camera2_stream_ops* w,\n            int64_t timestamp,\n            buffer_handle_t* buffer);\n    /**\n     * Return a buffer to the queue without marking it as filled.\n     */\n    int (*cancel_buffer)(const struct camera2_stream_ops* w,\n            buffer_handle_t* buffer);\n    /**\n     * Set the crop window for subsequently enqueued buffers. The parameters are\n     * measured in pixels relative to the buffer width and height.\n     */\n    int (*set_crop)(const struct camera2_stream_ops *w,\n            int left, int top, int right, int bottom);\n\n} camera2_stream_ops_t;\n\n/**\n * Temporary definition during transition.\n *\n * These formats will be removed and replaced with\n * HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED.  To maximize forward compatibility,\n * HAL implementations are strongly recommended to treat FORMAT_OPAQUE and\n * FORMAT_ZSL as equivalent to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, and\n * return HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED in the format_actual output\n * parameter of allocate_stream, allowing the gralloc module to select the\n * specific format based on the usage flags from the camera and the stream\n * consumer.\n */\nenum {\n    CAMERA2_HAL_PIXEL_FORMAT_OPAQUE = HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED,\n    CAMERA2_HAL_PIXEL_FORMAT_ZSL = -1\n};\n\n/**\n * Transport header for compressed JPEG buffers in output streams.\n *\n * To capture JPEG images, a stream is created using the pixel format\n * HAL_PIXEL_FORMAT_BLOB, and the static metadata field android.jpeg.maxSize is\n * used as the buffer size. Since compressed JPEG images are of variable size,\n * the HAL needs to include the final size of the compressed image using this\n * structure inside the output stream buffer. The JPEG blob ID field must be set\n * to CAMERA2_JPEG_BLOB_ID.\n *\n * Transport header should be at the end of the JPEG output stream buffer.  That\n * means the jpeg_blob_id must start at byte[android.jpeg.maxSize -\n * sizeof(camera2_jpeg_blob)].  Any HAL using this transport header must\n * account for it in android.jpeg.maxSize.  The JPEG data itself starts at\n * byte[0] and should be jpeg_size bytes long.\n */\ntypedef struct camera2_jpeg_blob {\n    uint16_t jpeg_blob_id;\n    uint32_t jpeg_size;\n};\n\nenum {\n    CAMERA2_JPEG_BLOB_ID = 0x00FF\n};\n\n/**\n * Input reprocess stream queue management. A set of these methods is provided\n * to the HAL device in allocate_reprocess_stream(); they are used to interact\n * with the reprocess stream's input gralloc buffer queue.\n */\ntypedef struct camera2_stream_in_ops {\n    /**\n     * Get the next buffer of image data to reprocess. The width, height, and\n     * format of the buffer is fixed in allocate_reprocess_stream(), and the\n     * stride and other details should be queried from the platform gralloc\n     * module as needed. The buffer will already be locked for use.\n     */\n    int (*acquire_buffer)(const struct camera2_stream_in_ops *w,\n            buffer_handle_t** buffer);\n    /**\n     * Return a used buffer to the buffer queue for reuse.\n     */\n    int (*release_buffer)(const struct camera2_stream_in_ops *w,\n            buffer_handle_t* buffer);\n\n} camera2_stream_in_ops_t;\n\n/**********************************************************************\n *\n * Metadata queue management, used for requests sent to HAL module, and for\n * frames produced by the HAL.\n *\n */\n\nenum {\n    CAMERA2_REQUEST_QUEUE_IS_BOTTOMLESS = -1\n};\n\n/**\n * Request input queue protocol:\n *\n * The framework holds the queue and its contents. At start, the queue is empty.\n *\n * 1. When the first metadata buffer is placed into the queue, the framework\n *    signals the device by calling notify_request_queue_not_empty().\n *\n * 2. After receiving notify_request_queue_not_empty, the device must call\n *    dequeue() once it's ready to handle the next buffer.\n *\n * 3. Once the device has processed a buffer, and is ready for the next buffer,\n *    it must call dequeue() again instead of waiting for a notification. If\n *    there are no more buffers available, dequeue() will return NULL. After\n *    this point, when a buffer becomes available, the framework must call\n *    notify_request_queue_not_empty() again. If the device receives a NULL\n *    return from dequeue, it does not need to query the queue again until a\n *    notify_request_queue_not_empty() call is received from the source.\n *\n * 4. If the device calls buffer_count() and receives 0, this does not mean that\n *    the framework will provide a notify_request_queue_not_empty() call. The\n *    framework will only provide such a notification after the device has\n *    received a NULL from dequeue, or on initial startup.\n *\n * 5. The dequeue() call in response to notify_request_queue_not_empty() may be\n *    on the same thread as the notify_request_queue_not_empty() call, and may\n *    be performed from within the notify call.\n *\n * 6. All dequeued request buffers must be returned to the framework by calling\n *    free_request, including when errors occur, a device flush is requested, or\n *    when the device is shutting down.\n */\ntypedef struct camera2_request_queue_src_ops {\n    /**\n     * Get the count of request buffers pending in the queue. May return\n     * CAMERA2_REQUEST_QUEUE_IS_BOTTOMLESS if a repeating request (stream\n     * request) is currently configured. Calling this method has no effect on\n     * whether the notify_request_queue_not_empty() method will be called by the\n     * framework.\n     */\n    int (*request_count)(const struct camera2_request_queue_src_ops *q);\n\n    /**\n     * Get a metadata buffer from the framework. Returns OK if there is no\n     * error. If the queue is empty, returns NULL in buffer. In that case, the\n     * device must wait for a notify_request_queue_not_empty() message before\n     * attempting to dequeue again. Buffers obtained in this way must be\n     * returned to the framework with free_request().\n     */\n    int (*dequeue_request)(const struct camera2_request_queue_src_ops *q,\n            camera_metadata_t **buffer);\n    /**\n     * Return a metadata buffer to the framework once it has been used, or if\n     * an error or shutdown occurs.\n     */\n    int (*free_request)(const struct camera2_request_queue_src_ops *q,\n            camera_metadata_t *old_buffer);\n\n} camera2_request_queue_src_ops_t;\n\n/**\n * Frame output queue protocol:\n *\n * The framework holds the queue and its contents. At start, the queue is empty.\n *\n * 1. When the device is ready to fill an output metadata frame, it must dequeue\n *    a metadata buffer of the required size.\n *\n * 2. It should then fill the metadata buffer, and place it on the frame queue\n *    using enqueue_frame. The framework takes ownership of the frame.\n *\n * 3. In case of an error, a request to flush the pipeline, or shutdown, the\n *    device must return any affected dequeued frames to the framework by\n *    calling cancel_frame.\n */\ntypedef struct camera2_frame_queue_dst_ops {\n    /**\n     * Get an empty metadata buffer to fill from the framework. The new metadata\n     * buffer will have room for entries number of metadata entries, plus\n     * data_bytes worth of extra storage. Frames dequeued here must be returned\n     * to the framework with either cancel_frame or enqueue_frame.\n     */\n    int (*dequeue_frame)(const struct camera2_frame_queue_dst_ops *q,\n            size_t entries, size_t data_bytes,\n            camera_metadata_t **buffer);\n\n    /**\n     * Return a dequeued metadata buffer to the framework for reuse; do not mark it as\n     * filled. Use when encountering errors, or flushing the internal request queue.\n     */\n    int (*cancel_frame)(const struct camera2_frame_queue_dst_ops *q,\n            camera_metadata_t *buffer);\n\n    /**\n     * Place a completed metadata frame on the frame output queue.\n     */\n    int (*enqueue_frame)(const struct camera2_frame_queue_dst_ops *q,\n            camera_metadata_t *buffer);\n\n} camera2_frame_queue_dst_ops_t;\n\n/**********************************************************************\n *\n * Notification callback and message definition, and trigger definitions\n *\n */\n\n/**\n * Asynchronous notification callback from the HAL, fired for various\n * reasons. Only for information independent of frame capture, or that require\n * specific timing. The user pointer must be the same one that was passed to the\n * device in set_notify_callback().\n */\ntypedef void (*camera2_notify_callback)(int32_t msg_type,\n        int32_t ext1,\n        int32_t ext2,\n        int32_t ext3,\n        void *user);\n\n/**\n * Possible message types for camera2_notify_callback\n */\nenum {\n    /**\n     * An error has occurred. Argument ext1 contains the error code, and\n     * ext2 and ext3 contain any error-specific information.\n     */\n    CAMERA2_MSG_ERROR   = 0x0001,\n    /**\n     * The exposure of a given request has begun. Argument ext1 contains the\n     * frame number, and ext2 and ext3 contain the low-order and high-order\n     * bytes of the timestamp for when exposure began.\n     * (timestamp = (ext3 << 32 | ext2))\n     */\n    CAMERA2_MSG_SHUTTER = 0x0010,\n    /**\n     * The autofocus routine has changed state. Argument ext1 contains the new\n     * state; the values are the same as those for the metadata field\n     * android.control.afState. Ext2 contains the latest trigger ID passed to\n     * trigger_action(CAMERA2_TRIGGER_AUTOFOCUS) or\n     * trigger_action(CAMERA2_TRIGGER_CANCEL_AUTOFOCUS), or 0 if trigger has not\n     * been called with either of those actions.\n     */\n    CAMERA2_MSG_AUTOFOCUS = 0x0020,\n    /**\n     * The autoexposure routine has changed state. Argument ext1 contains the\n     * new state; the values are the same as those for the metadata field\n     * android.control.aeState. Ext2 contains the latest trigger ID value passed to\n     * trigger_action(CAMERA2_TRIGGER_PRECAPTURE_METERING), or 0 if that method\n     * has not been called.\n     */\n    CAMERA2_MSG_AUTOEXPOSURE = 0x0021,\n    /**\n     * The auto-whitebalance routine has changed state. Argument ext1 contains\n     * the new state; the values are the same as those for the metadata field\n     * android.control.awbState. Ext2 contains the latest trigger ID passed to\n     * trigger_action(CAMERA2_TRIGGER_PRECAPTURE_METERING), or 0 if that method\n     * has not been called.\n     */\n    CAMERA2_MSG_AUTOWB = 0x0022\n};\n\n/**\n * Error codes for CAMERA_MSG_ERROR\n */\nenum {\n    /**\n     * A serious failure occured. Camera device may not work without reboot, and\n     * no further frames or buffer streams will be produced by the\n     * device. Device should be treated as closed.\n     */\n    CAMERA2_MSG_ERROR_HARDWARE = 0x0001,\n    /**\n     * A serious failure occured. No further frames or buffer streams will be\n     * produced by the device. Device should be treated as closed. The client\n     * must reopen the device to use it again.\n     */\n    CAMERA2_MSG_ERROR_DEVICE,\n    /**\n     * An error has occurred in processing a request. No output (metadata or\n     * buffers) will be produced for this request. ext2 contains the frame\n     * number of the request. Subsequent requests are unaffected, and the device\n     * remains operational.\n     */\n    CAMERA2_MSG_ERROR_REQUEST,\n    /**\n     * An error has occurred in producing an output frame metadata buffer for a\n     * request, but image buffers for it will still be available. Subsequent\n     * requests are unaffected, and the device remains operational. ext2\n     * contains the frame number of the request.\n     */\n    CAMERA2_MSG_ERROR_FRAME,\n    /**\n     * An error has occurred in placing an output buffer into a stream for a\n     * request. The frame metadata and other buffers may still be\n     * available. Subsequent requests are unaffected, and the device remains\n     * operational. ext2 contains the frame number of the request, and ext3\n     * contains the stream id.\n     */\n    CAMERA2_MSG_ERROR_STREAM,\n    /**\n     * Number of error types\n     */\n    CAMERA2_MSG_NUM_ERRORS\n};\n\n/**\n * Possible trigger ids for trigger_action()\n */\nenum {\n    /**\n     * Trigger an autofocus cycle. The effect of the trigger depends on the\n     * autofocus mode in effect when the trigger is received, which is the mode\n     * listed in the latest capture request to be dequeued by the HAL. If the\n     * mode is OFF, EDOF, or FIXED, the trigger has no effect. In AUTO, MACRO,\n     * or CONTINUOUS_* modes, see below for the expected behavior. The state of\n     * the autofocus cycle can be tracked in android.control.afMode and the\n     * corresponding notifications.\n     *\n     **\n     * In AUTO or MACRO mode, the AF state transitions (and notifications)\n     * when calling with trigger ID = N with the previous ID being K are:\n     *\n     * Initial state       Transitions\n     * INACTIVE (K)         -> ACTIVE_SCAN (N) -> AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * AF_FOCUSED (K)       -> ACTIVE_SCAN (N) -> AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * AF_NOT_FOCUSED (K)   -> ACTIVE_SCAN (N) -> AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * ACTIVE_SCAN (K)      -> AF_FOCUSED(N) or AF_NOT_FOCUSED(N)\n     * PASSIVE_SCAN (K)      Not used in AUTO/MACRO mode\n     * PASSIVE_FOCUSED (K)   Not used in AUTO/MACRO mode\n     *\n     **\n     * In CONTINUOUS_PICTURE mode, triggering AF must lock the AF to the current\n     * lens position and transition the AF state to either AF_FOCUSED or\n     * NOT_FOCUSED. If a passive scan is underway, that scan must complete and\n     * then lock the lens position and change AF state. TRIGGER_CANCEL_AUTOFOCUS\n     * will allow the AF to restart its operation.\n     *\n     * Initial state      Transitions\n     * INACTIVE (K)        -> immediate AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * PASSIVE_FOCUSED (K) -> immediate AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * PASSIVE_SCAN (K)    -> AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * AF_FOCUSED (K)      no effect except to change next notification ID to N\n     * AF_NOT_FOCUSED (K)  no effect except to change next notification ID to N\n     *\n     **\n     * In CONTINUOUS_VIDEO mode, triggering AF must lock the AF to the current\n     * lens position and transition the AF state to either AF_FOCUSED or\n     * NOT_FOCUSED. If a passive scan is underway, it must immediately halt, in\n     * contrast with CONTINUOUS_PICTURE mode. TRIGGER_CANCEL_AUTOFOCUS will\n     * allow the AF to restart its operation.\n     *\n     * Initial state      Transitions\n     * INACTIVE (K)        -> immediate AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * PASSIVE_FOCUSED (K) -> immediate AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * PASSIVE_SCAN (K)    -> immediate AF_FOCUSED (N) or AF_NOT_FOCUSED (N)\n     * AF_FOCUSED (K)      no effect except to change next notification ID to N\n     * AF_NOT_FOCUSED (K)  no effect except to change next notification ID to N\n     *\n     * Ext1 is an ID that must be returned in subsequent auto-focus state change\n     * notifications through camera2_notify_callback() and stored in\n     * android.control.afTriggerId.\n     */\n    CAMERA2_TRIGGER_AUTOFOCUS = 0x0001,\n    /**\n     * Send a cancel message to the autofocus algorithm. The effect of the\n     * cancellation depends on the autofocus mode in effect when the trigger is\n     * received, which is the mode listed in the latest capture request to be\n     * dequeued by the HAL. If the AF mode is OFF or EDOF, the cancel has no\n     * effect.  For other modes, the lens should return to its default position,\n     * any current autofocus scan must be canceled, and the AF state should be\n     * set to INACTIVE.\n     *\n     * The state of the autofocus cycle can be tracked in android.control.afMode\n     * and the corresponding notification. Continuous autofocus modes may resume\n     * focusing operations thereafter exactly as if the camera had just been set\n     * to a continuous AF mode.\n     *\n     * Ext1 is an ID that must be returned in subsequent auto-focus state change\n     * notifications through camera2_notify_callback() and stored in\n     * android.control.afTriggerId.\n     */\n    CAMERA2_TRIGGER_CANCEL_AUTOFOCUS,\n    /**\n     * Trigger a pre-capture metering cycle, which may include firing the flash\n     * to determine proper capture parameters. Typically, this trigger would be\n     * fired for a half-depress of a camera shutter key, or before a snapshot\n     * capture in general. The state of the metering cycle can be tracked in\n     * android.control.aeMode and the corresponding notification.  If the\n     * auto-exposure mode is OFF, the trigger does nothing.\n     *\n     * Ext1 is an ID that must be returned in subsequent\n     * auto-exposure/auto-white balance state change notifications through\n     * camera2_notify_callback() and stored in android.control.aePrecaptureId.\n     */\n     CAMERA2_TRIGGER_PRECAPTURE_METERING\n};\n\n/**\n * Possible template types for construct_default_request()\n */\nenum {\n    /**\n     * Standard camera preview operation with 3A on auto.\n     */\n    CAMERA2_TEMPLATE_PREVIEW = 1,\n    /**\n     * Standard camera high-quality still capture with 3A and flash on auto.\n     */\n    CAMERA2_TEMPLATE_STILL_CAPTURE,\n    /**\n     * Standard video recording plus preview with 3A on auto, torch off.\n     */\n    CAMERA2_TEMPLATE_VIDEO_RECORD,\n    /**\n     * High-quality still capture while recording video. Application will\n     * include preview, video record, and full-resolution YUV or JPEG streams in\n     * request. Must not cause stuttering on video stream. 3A on auto.\n     */\n    CAMERA2_TEMPLATE_VIDEO_SNAPSHOT,\n    /**\n     * Zero-shutter-lag mode. Application will request preview and\n     * full-resolution data for each frame, and reprocess it to JPEG when a\n     * still image is requested by user. Settings should provide highest-quality\n     * full-resolution images without compromising preview frame rate. 3A on\n     * auto.\n     */\n    CAMERA2_TEMPLATE_ZERO_SHUTTER_LAG,\n\n    /* Total number of templates */\n    CAMERA2_TEMPLATE_COUNT\n};\n\n\n/**********************************************************************\n *\n * Camera device operations\n *\n */\ntypedef struct camera2_device_ops {\n\n    /**********************************************************************\n     * Request and frame queue setup and management methods\n     */\n\n    /**\n     * Pass in input request queue interface methods.\n     */\n    int (*set_request_queue_src_ops)(const struct camera2_device *,\n            const camera2_request_queue_src_ops_t *request_src_ops);\n\n    /**\n     * Notify device that the request queue is no longer empty. Must only be\n     * called when the first buffer is added a new queue, or after the source\n     * has returned NULL in response to a dequeue call.\n     */\n    int (*notify_request_queue_not_empty)(const struct camera2_device *);\n\n    /**\n     * Pass in output frame queue interface methods\n     */\n    int (*set_frame_queue_dst_ops)(const struct camera2_device *,\n            const camera2_frame_queue_dst_ops_t *frame_dst_ops);\n\n    /**\n     * Number of camera requests being processed by the device at the moment\n     * (captures/reprocesses that have had their request dequeued, but have not\n     * yet been enqueued onto output pipeline(s) ). No streams may be released\n     * by the framework until the in-progress count is 0.\n     */\n    int (*get_in_progress_count)(const struct camera2_device *);\n\n    /**\n     * Flush all in-progress captures. This includes all dequeued requests\n     * (regular or reprocessing) that have not yet placed any outputs into a\n     * stream or the frame queue. Partially completed captures must be completed\n     * normally. No new requests may be dequeued from the request queue until\n     * the flush completes.\n     */\n    int (*flush_captures_in_progress)(const struct camera2_device *);\n\n    /**\n     * Create a filled-in default request for standard camera use cases.\n     *\n     * The device must return a complete request that is configured to meet the\n     * requested use case, which must be one of the CAMERA2_TEMPLATE_*\n     * enums. All request control fields must be included, except for\n     * android.request.outputStreams.\n     *\n     * The metadata buffer returned must be allocated with\n     * allocate_camera_metadata. The framework takes ownership of the buffer.\n     */\n    int (*construct_default_request)(const struct camera2_device *,\n            int request_template,\n            camera_metadata_t **request);\n\n    /**********************************************************************\n     * Stream management\n     */\n\n    /**\n     * allocate_stream:\n     *\n     * Allocate a new output stream for use, defined by the output buffer width,\n     * height, target, and possibly the pixel format.  Returns the new stream's\n     * ID, gralloc usage flags, minimum queue buffer count, and possibly the\n     * pixel format, on success. Error conditions:\n     *\n     *  - Requesting a width/height/format combination not listed as\n     *    supported by the sensor's static characteristics\n     *\n     *  - Asking for too many streams of a given format type (2 bayer raw\n     *    streams, for example).\n     *\n     * Input parameters:\n     *\n     * - width, height, format: Specification for the buffers to be sent through\n     *   this stream. Format is a value from the HAL_PIXEL_FORMAT_* list. If\n     *   HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED is used, then the platform\n     *   gralloc module will select a format based on the usage flags provided\n     *   by the camera HAL and the consumer of the stream. The camera HAL should\n     *   inspect the buffers handed to it in the register_stream_buffers call to\n     *   obtain the implementation-specific format if necessary.\n     *\n     * - stream_ops: A structure of function pointers for obtaining and queuing\n     *   up buffers for this stream. The underlying stream will be configured\n     *   based on the usage and max_buffers outputs. The methods in this\n     *   structure may not be called until after allocate_stream returns.\n     *\n     * Output parameters:\n     *\n     * - stream_id: An unsigned integer identifying this stream. This value is\n     *   used in incoming requests to identify the stream, and in releasing the\n     *   stream.\n     *\n     * - usage: The gralloc usage mask needed by the HAL device for producing\n     *   the requested type of data. This is used in allocating new gralloc\n     *   buffers for the stream buffer queue.\n     *\n     * - max_buffers: The maximum number of buffers the HAL device may need to\n     *   have dequeued at the same time. The device may not dequeue more buffers\n     *   than this value at the same time.\n     *\n     */\n    int (*allocate_stream)(\n            const struct camera2_device *,\n            // inputs\n            uint32_t width,\n            uint32_t height,\n            int      format,\n            const camera2_stream_ops_t *stream_ops,\n            // outputs\n            uint32_t *stream_id,\n            uint32_t *format_actual, // IGNORED, will be removed\n            uint32_t *usage,\n            uint32_t *max_buffers);\n\n    /**\n     * Register buffers for a given stream. This is called after a successful\n     * allocate_stream call, and before the first request referencing the stream\n     * is enqueued. This method is intended to allow the HAL device to map or\n     * otherwise prepare the buffers for later use. num_buffers is guaranteed to\n     * be at least max_buffers (from allocate_stream), but may be larger. The\n     * buffers will already be locked for use. At the end of the call, all the\n     * buffers must be ready to be returned to the queue. If the stream format\n     * was set to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, the camera HAL should\n     * inspect the passed-in buffers here to determine any platform-private\n     * pixel format information.\n     */\n    int (*register_stream_buffers)(\n            const struct camera2_device *,\n            uint32_t stream_id,\n            int num_buffers,\n            buffer_handle_t *buffers);\n\n    /**\n     * Release a stream. Returns an error if called when get_in_progress_count\n     * is non-zero, or if the stream id is invalid.\n     */\n    int (*release_stream)(\n            const struct camera2_device *,\n            uint32_t stream_id);\n\n    /**\n     * allocate_reprocess_stream:\n     *\n     * Allocate a new input stream for use, defined by the output buffer width,\n     * height, and the pixel format.  Returns the new stream's ID, gralloc usage\n     * flags, and required simultaneously acquirable buffer count, on\n     * success. Error conditions:\n     *\n     *  - Requesting a width/height/format combination not listed as\n     *    supported by the sensor's static characteristics\n     *\n     *  - Asking for too many reprocessing streams to be configured at once.\n     *\n     * Input parameters:\n     *\n     * - width, height, format: Specification for the buffers to be sent through\n     *   this stream. Format must be a value from the HAL_PIXEL_FORMAT_* list.\n     *\n     * - reprocess_stream_ops: A structure of function pointers for acquiring\n     *   and releasing buffers for this stream. The underlying stream will be\n     *   configured based on the usage and max_buffers outputs.\n     *\n     * Output parameters:\n     *\n     * - stream_id: An unsigned integer identifying this stream. This value is\n     *   used in incoming requests to identify the stream, and in releasing the\n     *   stream. These ids are numbered separately from the input stream ids.\n     *\n     * - consumer_usage: The gralloc usage mask needed by the HAL device for\n     *   consuming the requested type of data. This is used in allocating new\n     *   gralloc buffers for the stream buffer queue.\n     *\n     * - max_buffers: The maximum number of buffers the HAL device may need to\n     *   have acquired at the same time. The device may not have more buffers\n     *   acquired at the same time than this value.\n     *\n     */\n    int (*allocate_reprocess_stream)(const struct camera2_device *,\n            uint32_t width,\n            uint32_t height,\n            uint32_t format,\n            const camera2_stream_in_ops_t *reprocess_stream_ops,\n            // outputs\n            uint32_t *stream_id,\n            uint32_t *consumer_usage,\n            uint32_t *max_buffers);\n\n    /**\n     * allocate_reprocess_stream_from_stream:\n     *\n     * Allocate a new input stream for use, which will use the buffers allocated\n     * for an existing output stream. That is, after the HAL enqueues a buffer\n     * onto the output stream, it may see that same buffer handed to it from\n     * this input reprocessing stream. After the HAL releases the buffer back to\n     * the reprocessing stream, it will be returned to the output queue for\n     * reuse.\n     *\n     * Error conditions:\n     *\n     * - Using an output stream of unsuitable size/format for the basis of the\n     *   reprocessing stream.\n     *\n     * - Attempting to allocatee too many reprocessing streams at once.\n     *\n     * Input parameters:\n     *\n     * - output_stream_id: The ID of an existing output stream which has\n     *   a size and format suitable for reprocessing.\n     *\n     * - reprocess_stream_ops: A structure of function pointers for acquiring\n     *   and releasing buffers for this stream. The underlying stream will use\n     *   the same graphics buffer handles as the output stream uses.\n     *\n     * Output parameters:\n     *\n     * - stream_id: An unsigned integer identifying this stream. This value is\n     *   used in incoming requests to identify the stream, and in releasing the\n     *   stream. These ids are numbered separately from the input stream ids.\n     *\n     * The HAL client must always release the reprocessing stream before it\n     * releases the output stream it is based on.\n     *\n     */\n    int (*allocate_reprocess_stream_from_stream)(const struct camera2_device *,\n            uint32_t output_stream_id,\n            const camera2_stream_in_ops_t *reprocess_stream_ops,\n            // outputs\n            uint32_t *stream_id);\n\n    /**\n     * Release a reprocessing stream. Returns an error if called when\n     * get_in_progress_count is non-zero, or if the stream id is not\n     * valid.\n     */\n    int (*release_reprocess_stream)(\n            const struct camera2_device *,\n            uint32_t stream_id);\n\n    /**********************************************************************\n     * Miscellaneous methods\n     */\n\n    /**\n     * Trigger asynchronous activity. This is used for triggering special\n     * behaviors of the camera 3A routines when they are in use. See the\n     * documentation for CAMERA2_TRIGGER_* above for details of the trigger ids\n     * and their arguments.\n     */\n    int (*trigger_action)(const struct camera2_device *,\n            uint32_t trigger_id,\n            int32_t ext1,\n            int32_t ext2);\n\n    /**\n     * Notification callback setup\n     */\n    int (*set_notify_callback)(const struct camera2_device *,\n            camera2_notify_callback notify_cb,\n            void *user);\n\n    /**\n     * Get methods to query for vendor extension metadata tag infomation. May\n     * set ops to NULL if no vendor extension tags are defined.\n     */\n    int (*get_metadata_vendor_tag_ops)(const struct camera2_device*,\n            vendor_tag_query_ops_t **ops);\n\n    /**\n     * Dump state of the camera hardware\n     */\n    int (*dump)(const struct camera2_device *, int fd);\n\n    /**\n     * Get device-instance-specific metadata. This metadata must be constant for\n     * a single instance of the camera device, but may be different between\n     * open() calls. The returned camera_metadata pointer must be valid until\n     * the device close() method is called.\n     *\n     * Version information:\n     *\n     * CAMERA_DEVICE_API_VERSION_2_0:\n     *\n     *   Not available. Framework may not access this function pointer.\n     *\n     * CAMERA_DEVICE_API_VERSION_2_1:\n     *\n     *   Valid. Can be called by the framework.\n     *\n     */\n    int (*get_instance_metadata)(const struct camera2_device *,\n            camera_metadata **instance_metadata);\n\n} camera2_device_ops_t;\n\n/**********************************************************************\n *\n * Camera device definition\n *\n */\ntypedef struct camera2_device {\n    /**\n     * common.version must equal CAMERA_DEVICE_API_VERSION_2_0 to identify\n     * this device as implementing version 2.0 of the camera device HAL.\n     */\n    hw_device_t common;\n    camera2_device_ops_t *ops;\n    void *priv;\n} camera2_device_t;\n\n__END_DECLS\n\n#endif /* #ifdef ANDROID_INCLUDE_CAMERA2_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/camera3.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_CAMERA3_H\n#define ANDROID_INCLUDE_CAMERA3_H\n\n#include <system/camera_metadata.h>\n#include \"camera_common.h\"\n\n/**\n * Camera device HAL 3.3 [ CAMERA_DEVICE_API_VERSION_3_3 ]\n *\n * This is the current recommended version of the camera device HAL.\n *\n * Supports the android.hardware.Camera API, and as of v3.2, the\n * android.hardware.camera2 API in LIMITED or FULL modes.\n *\n * Camera devices that support this version of the HAL must return\n * CAMERA_DEVICE_API_VERSION_3_3 in camera_device_t.common.version and in\n * camera_info_t.device_version (from camera_module_t.get_camera_info).\n *\n * CAMERA_DEVICE_API_VERSION_3_3:\n *    Camera modules that may contain version 3.3 devices must implement at\n *    least version 2.2 of the camera module interface (as defined by\n *    camera_module_t.common.module_api_version).\n *\n * CAMERA_DEVICE_API_VERSION_3_2:\n *    Camera modules that may contain version 3.2 devices must implement at\n *    least version 2.2 of the camera module interface (as defined by\n *    camera_module_t.common.module_api_version).\n *\n * <= CAMERA_DEVICE_API_VERSION_3_1:\n *    Camera modules that may contain version 3.1 (or 3.0) devices must\n *    implement at least version 2.0 of the camera module interface\n *    (as defined by camera_module_t.common.module_api_version).\n *\n * See camera_common.h for more versioning details.\n *\n * Documentation index:\n *   S1. Version history\n *   S2. Startup and operation sequencing\n *   S3. Operational modes\n *   S4. 3A modes and state machines\n *   S5. Cropping\n *   S6. Error management\n *   S7. Key Performance Indicator (KPI) glossary\n *   S8. Sample Use Cases\n *   S9. Notes on Controls and Metadata\n *   S10. Reprocessing flow and controls\n */\n\n/**\n * S1. Version history:\n *\n * 1.0: Initial Android camera HAL (Android 4.0) [camera.h]:\n *\n *   - Converted from C++ CameraHardwareInterface abstraction layer.\n *\n *   - Supports android.hardware.Camera API.\n *\n * 2.0: Initial release of expanded-capability HAL (Android 4.2) [camera2.h]:\n *\n *   - Sufficient for implementing existing android.hardware.Camera API.\n *\n *   - Allows for ZSL queue in camera service layer\n *\n *   - Not tested for any new features such manual capture control, Bayer RAW\n *     capture, reprocessing of RAW data.\n *\n * 3.0: First revision of expanded-capability HAL:\n *\n *   - Major version change since the ABI is completely different. No change to\n *     the required hardware capabilities or operational model from 2.0.\n *\n *   - Reworked input request and stream queue interfaces: Framework calls into\n *     HAL with next request and stream buffers already dequeued. Sync framework\n *     support is included, necessary for efficient implementations.\n *\n *   - Moved triggers into requests, most notifications into results.\n *\n *   - Consolidated all callbacks into framework into one structure, and all\n *     setup methods into a single initialize() call.\n *\n *   - Made stream configuration into a single call to simplify stream\n *     management. Bidirectional streams replace STREAM_FROM_STREAM construct.\n *\n *   - Limited mode semantics for older/limited hardware devices.\n *\n * 3.1: Minor revision of expanded-capability HAL:\n *\n *   - configure_streams passes consumer usage flags to the HAL.\n *\n *   - flush call to drop all in-flight requests/buffers as fast as possible.\n *\n * 3.2: Minor revision of expanded-capability HAL:\n *\n *   - Deprecates get_metadata_vendor_tag_ops.  Please use get_vendor_tag_ops\n *     in camera_common.h instead.\n *\n *   - register_stream_buffers deprecated. All gralloc buffers provided\n *     by framework to HAL in process_capture_request may be new at any time.\n *\n *   - add partial result support. process_capture_result may be called\n *     multiple times with a subset of the available result before the full\n *     result is available.\n *\n *   - add manual template to camera3_request_template. The applications may\n *     use this template to control the capture settings directly.\n *\n *   - Rework the bidirectional and input stream specifications.\n *\n *   - change the input buffer return path. The buffer is returned in\n *     process_capture_result instead of process_capture_request.\n *\n * 3.3: Minor revision of expanded-capability HAL:\n *\n *   - OPAQUE and YUV reprocessing API updates.\n *\n *   - Basic support for depth output buffers.\n *\n *   - Addition of data_space field to camera3_stream_t.\n *\n *   - Addition of rotation field to camera3_stream_t.\n *\n *   - Addition of camera3 stream configuration operation mode to camera3_stream_configuration_t\n *\n */\n\n/**\n * S2. Startup and general expected operation sequence:\n *\n * 1. Framework calls camera_module_t->common.open(), which returns a\n *    hardware_device_t structure.\n *\n * 2. Framework inspects the hardware_device_t->version field, and instantiates\n *    the appropriate handler for that version of the camera hardware device. In\n *    case the version is CAMERA_DEVICE_API_VERSION_3_0, the device is cast to\n *    a camera3_device_t.\n *\n * 3. Framework calls camera3_device_t->ops->initialize() with the framework\n *    callback function pointers. This will only be called this one time after\n *    open(), before any other functions in the ops structure are called.\n *\n * 4. The framework calls camera3_device_t->ops->configure_streams() with a list\n *    of input/output streams to the HAL device.\n *\n * 5. <= CAMERA_DEVICE_API_VERSION_3_1:\n *\n *    The framework allocates gralloc buffers and calls\n *    camera3_device_t->ops->register_stream_buffers() for at least one of the\n *    output streams listed in configure_streams. The same stream is registered\n *    only once.\n *\n *    >= CAMERA_DEVICE_API_VERSION_3_2:\n *\n *    camera3_device_t->ops->register_stream_buffers() is not called and must\n *    be NULL.\n *\n * 6. The framework requests default settings for some number of use cases with\n *    calls to camera3_device_t->ops->construct_default_request_settings(). This\n *    may occur any time after step 3.\n *\n * 7. The framework constructs and sends the first capture request to the HAL,\n *    with settings based on one of the sets of default settings, and with at\n *    least one output stream, which has been registered earlier by the\n *    framework. This is sent to the HAL with\n *    camera3_device_t->ops->process_capture_request(). The HAL must block the\n *    return of this call until it is ready for the next request to be sent.\n *\n *    >= CAMERA_DEVICE_API_VERSION_3_2:\n *\n *    The buffer_handle_t provided in the camera3_stream_buffer_t array\n *    in the camera3_capture_request_t may be new and never-before-seen\n *    by the HAL on any given new request.\n *\n * 8. The framework continues to submit requests, and call\n *    construct_default_request_settings to get default settings buffers for\n *    other use cases.\n *\n *    <= CAMERA_DEVICE_API_VERSION_3_1:\n *\n *    The framework may call register_stream_buffers() at this time for\n *    not-yet-registered streams.\n *\n * 9. When the capture of a request begins (sensor starts exposing for the\n *    capture) or processing a reprocess request begins, the HAL\n *    calls camera3_callback_ops_t->notify() with the SHUTTER event, including\n *    the frame number and the timestamp for start of exposure. For a reprocess\n *    request, the timestamp must be the start of exposure of the input image\n *    which can be looked up with android.sensor.timestamp from\n *    camera3_capture_request_t.settings when process_capture_request() is\n *    called.\n *\n *    <= CAMERA_DEVICE_API_VERSION_3_1:\n *\n *    This notify call must be made before the first call to\n *    process_capture_result() for that frame number.\n *\n *    >= CAMERA_DEVICE_API_VERSION_3_2:\n *\n *    The camera3_callback_ops_t->notify() call with the SHUTTER event should\n *    be made as early as possible since the framework will be unable to\n *    deliver gralloc buffers to the application layer (for that frame) until\n *    it has a valid timestamp for the start of exposure (or the input image's\n *    start of exposure for a reprocess request).\n *\n *    Both partial metadata results and the gralloc buffers may be sent to the\n *    framework at any time before or after the SHUTTER event.\n *\n * 10. After some pipeline delay, the HAL begins to return completed captures to\n *    the framework with camera3_callback_ops_t->process_capture_result(). These\n *    are returned in the same order as the requests were submitted. Multiple\n *    requests can be in flight at once, depending on the pipeline depth of the\n *    camera HAL device.\n *\n *    >= CAMERA_DEVICE_API_VERSION_3_2:\n *\n *    Once a buffer is returned by process_capture_result as part of the\n *    camera3_stream_buffer_t array, and the fence specified by release_fence\n *    has been signaled (this is a no-op for -1 fences), the ownership of that\n *    buffer is considered to be transferred back to the framework. After that,\n *    the HAL must no longer retain that particular buffer, and the\n *    framework may clean up the memory for it immediately.\n *\n *    process_capture_result may be called multiple times for a single frame,\n *    each time with a new disjoint piece of metadata and/or set of gralloc\n *    buffers. The framework will accumulate these partial metadata results\n *    into one result.\n *\n *    In particular, it is legal for a process_capture_result to be called\n *    simultaneously for both a frame N and a frame N+1 as long as the\n *    above rule holds for gralloc buffers (both input and output).\n *\n * 11. After some time, the framework may stop submitting new requests, wait for\n *    the existing captures to complete (all buffers filled, all results\n *    returned), and then call configure_streams() again. This resets the camera\n *    hardware and pipeline for a new set of input/output streams. Some streams\n *    may be reused from the previous configuration; if these streams' buffers\n *    had already been registered with the HAL, they will not be registered\n *    again. The framework then continues from step 7, if at least one\n *    registered output stream remains (otherwise, step 5 is required first).\n *\n * 12. Alternatively, the framework may call camera3_device_t->common->close()\n *    to end the camera session. This may be called at any time when no other\n *    calls from the framework are active, although the call may block until all\n *    in-flight captures have completed (all results returned, all buffers\n *    filled). After the close call returns, no more calls to the\n *    camera3_callback_ops_t functions are allowed from the HAL. Once the\n *    close() call is underway, the framework may not call any other HAL device\n *    functions.\n *\n * 13. In case of an error or other asynchronous event, the HAL must call\n *    camera3_callback_ops_t->notify() with the appropriate error/event\n *    message. After returning from a fatal device-wide error notification, the\n *    HAL should act as if close() had been called on it. However, the HAL must\n *    either cancel or complete all outstanding captures before calling\n *    notify(), so that once notify() is called with a fatal error, the\n *    framework will not receive further callbacks from the device. Methods\n *    besides close() should return -ENODEV or NULL after the notify() method\n *    returns from a fatal error message.\n */\n\n/**\n * S3. Operational modes:\n *\n * The camera 3 HAL device can implement one of two possible operational modes;\n * limited and full. Full support is expected from new higher-end\n * devices. Limited mode has hardware requirements roughly in line with those\n * for a camera HAL device v1 implementation, and is expected from older or\n * inexpensive devices. Full is a strict superset of limited, and they share the\n * same essential operational flow, as documented above.\n *\n * The HAL must indicate its level of support with the\n * android.info.supportedHardwareLevel static metadata entry, with 0 indicating\n * limited mode, and 1 indicating full mode support.\n *\n * Roughly speaking, limited-mode devices do not allow for application control\n * of capture settings (3A control only), high-rate capture of high-resolution\n * images, raw sensor readout, or support for YUV output streams above maximum\n * recording resolution (JPEG only for large images).\n *\n * ** Details of limited mode behavior:\n *\n * - Limited-mode devices do not need to implement accurate synchronization\n *   between capture request settings and the actual image data\n *   captured. Instead, changes to settings may take effect some time in the\n *   future, and possibly not for the same output frame for each settings\n *   entry. Rapid changes in settings may result in some settings never being\n *   used for a capture. However, captures that include high-resolution output\n *   buffers ( > 1080p ) have to use the settings as specified (but see below\n *   for processing rate).\n *\n * - Limited-mode devices do not need to support most of the\n *   settings/result/static info metadata. Specifically, only the following settings\n *   are expected to be consumed or produced by a limited-mode HAL device:\n *\n *   android.control.aeAntibandingMode (controls and dynamic)\n *   android.control.aeExposureCompensation (controls and dynamic)\n *   android.control.aeLock (controls and dynamic)\n *   android.control.aeMode (controls and dynamic)\n *   android.control.aeRegions (controls and dynamic)\n *   android.control.aeTargetFpsRange (controls and dynamic)\n *   android.control.aePrecaptureTrigger (controls and dynamic)\n *   android.control.afMode (controls and dynamic)\n *   android.control.afRegions (controls and dynamic)\n *   android.control.awbLock (controls and dynamic)\n *   android.control.awbMode (controls and dynamic)\n *   android.control.awbRegions (controls and dynamic)\n *   android.control.captureIntent (controls and dynamic)\n *   android.control.effectMode (controls and dynamic)\n *   android.control.mode (controls and dynamic)\n *   android.control.sceneMode (controls and dynamic)\n *   android.control.videoStabilizationMode (controls and dynamic)\n *   android.control.aeAvailableAntibandingModes (static)\n *   android.control.aeAvailableModes (static)\n *   android.control.aeAvailableTargetFpsRanges (static)\n *   android.control.aeCompensationRange (static)\n *   android.control.aeCompensationStep (static)\n *   android.control.afAvailableModes (static)\n *   android.control.availableEffects (static)\n *   android.control.availableSceneModes (static)\n *   android.control.availableVideoStabilizationModes (static)\n *   android.control.awbAvailableModes (static)\n *   android.control.maxRegions (static)\n *   android.control.sceneModeOverrides (static)\n *   android.control.aeState (dynamic)\n *   android.control.afState (dynamic)\n *   android.control.awbState (dynamic)\n *\n *   android.flash.mode (controls and dynamic)\n *   android.flash.info.available (static)\n *\n *   android.info.supportedHardwareLevel (static)\n *\n *   android.jpeg.gpsCoordinates (controls and dynamic)\n *   android.jpeg.gpsProcessingMethod (controls and dynamic)\n *   android.jpeg.gpsTimestamp (controls and dynamic)\n *   android.jpeg.orientation (controls and dynamic)\n *   android.jpeg.quality (controls and dynamic)\n *   android.jpeg.thumbnailQuality (controls and dynamic)\n *   android.jpeg.thumbnailSize (controls and dynamic)\n *   android.jpeg.availableThumbnailSizes (static)\n *   android.jpeg.maxSize (static)\n *\n *   android.lens.info.minimumFocusDistance (static)\n *\n *   android.request.id (controls and dynamic)\n *\n *   android.scaler.cropRegion (controls and dynamic)\n *   android.scaler.availableStreamConfigurations (static)\n *   android.scaler.availableMinFrameDurations (static)\n *   android.scaler.availableStallDurations (static)\n *   android.scaler.availableMaxDigitalZoom (static)\n *   android.scaler.maxDigitalZoom (static)\n *   android.scaler.croppingType (static)\n *\n *   android.sensor.orientation (static)\n *   android.sensor.timestamp (dynamic)\n *\n *   android.statistics.faceDetectMode (controls and dynamic)\n *   android.statistics.info.availableFaceDetectModes (static)\n *   android.statistics.faceIds (dynamic)\n *   android.statistics.faceLandmarks (dynamic)\n *   android.statistics.faceRectangles (dynamic)\n *   android.statistics.faceScores (dynamic)\n *\n *   android.sync.frameNumber (dynamic)\n *   android.sync.maxLatency (static)\n *\n * - Captures in limited mode that include high-resolution (> 1080p) output\n *   buffers may block in process_capture_request() until all the output buffers\n *   have been filled. A full-mode HAL device must process sequences of\n *   high-resolution requests at the rate indicated in the static metadata for\n *   that pixel format. The HAL must still call process_capture_result() to\n *   provide the output; the framework must simply be prepared for\n *   process_capture_request() to block until after process_capture_result() for\n *   that request completes for high-resolution captures for limited-mode\n *   devices.\n *\n * - Full-mode devices must support below additional capabilities:\n *   - 30fps at maximum resolution is preferred, more than 20fps is required.\n *   - Per frame control (android.sync.maxLatency == PER_FRAME_CONTROL).\n *   - Sensor manual control metadata. See MANUAL_SENSOR defined in\n *     android.request.availableCapabilities.\n *   - Post-processing manual control metadata. See MANUAL_POST_PROCESSING defined\n *     in android.request.availableCapabilities.\n *\n */\n\n/**\n * S4. 3A modes and state machines:\n *\n * While the actual 3A algorithms are up to the HAL implementation, a high-level\n * state machine description is defined by the HAL interface, to allow the HAL\n * device and the framework to communicate about the current state of 3A, and to\n * trigger 3A events.\n *\n * When the device is opened, all the individual 3A states must be\n * STATE_INACTIVE. Stream configuration does not reset 3A. For example, locked\n * focus must be maintained across the configure() call.\n *\n * Triggering a 3A action involves simply setting the relevant trigger entry in\n * the settings for the next request to indicate start of trigger. For example,\n * the trigger for starting an autofocus scan is setting the entry\n * ANDROID_CONTROL_AF_TRIGGER to ANDROID_CONTROL_AF_TRIGGER_START for one\n * request, and cancelling an autofocus scan is triggered by setting\n * ANDROID_CONTROL_AF_TRIGGER to ANDROID_CONTRL_AF_TRIGGER_CANCEL. Otherwise,\n * the entry will not exist, or be set to ANDROID_CONTROL_AF_TRIGGER_IDLE. Each\n * request with a trigger entry set to a non-IDLE value will be treated as an\n * independent triggering event.\n *\n * At the top level, 3A is controlled by the ANDROID_CONTROL_MODE setting, which\n * selects between no 3A (ANDROID_CONTROL_MODE_OFF), normal AUTO mode\n * (ANDROID_CONTROL_MODE_AUTO), and using the scene mode setting\n * (ANDROID_CONTROL_USE_SCENE_MODE).\n *\n * - In OFF mode, each of the individual AE/AF/AWB modes are effectively OFF,\n *   and none of the capture controls may be overridden by the 3A routines.\n *\n * - In AUTO mode, Auto-focus, auto-exposure, and auto-whitebalance all run\n *   their own independent algorithms, and have their own mode, state, and\n *   trigger metadata entries, as listed in the next section.\n *\n * - In USE_SCENE_MODE, the value of the ANDROID_CONTROL_SCENE_MODE entry must\n *   be used to determine the behavior of 3A routines. In SCENE_MODEs other than\n *   FACE_PRIORITY, the HAL must override the values of\n *   ANDROId_CONTROL_AE/AWB/AF_MODE to be the mode it prefers for the selected\n *   SCENE_MODE. For example, the HAL may prefer SCENE_MODE_NIGHT to use\n *   CONTINUOUS_FOCUS AF mode. Any user selection of AE/AWB/AF_MODE when scene\n *   must be ignored for these scene modes.\n *\n * - For SCENE_MODE_FACE_PRIORITY, the AE/AWB/AF_MODE controls work as in\n *   ANDROID_CONTROL_MODE_AUTO, but the 3A routines must bias toward metering\n *   and focusing on any detected faces in the scene.\n *\n * S4.1. Auto-focus settings and result entries:\n *\n *  Main metadata entries:\n *\n *   ANDROID_CONTROL_AF_MODE: Control for selecting the current autofocus\n *      mode. Set by the framework in the request settings.\n *\n *     AF_MODE_OFF: AF is disabled; the framework/app directly controls lens\n *         position.\n *\n *     AF_MODE_AUTO: Single-sweep autofocus. No lens movement unless AF is\n *         triggered.\n *\n *     AF_MODE_MACRO: Single-sweep up-close autofocus. No lens movement unless\n *         AF is triggered.\n *\n *     AF_MODE_CONTINUOUS_VIDEO: Smooth continuous focusing, for recording\n *         video. Triggering immediately locks focus in current\n *         position. Canceling resumes cotinuous focusing.\n *\n *     AF_MODE_CONTINUOUS_PICTURE: Fast continuous focusing, for\n *        zero-shutter-lag still capture. Triggering locks focus once currently\n *        active sweep concludes. Canceling resumes continuous focusing.\n *\n *     AF_MODE_EDOF: Advanced extended depth of field focusing. There is no\n *        autofocus scan, so triggering one or canceling one has no effect.\n *        Images are focused automatically by the HAL.\n *\n *   ANDROID_CONTROL_AF_STATE: Dynamic metadata describing the current AF\n *       algorithm state, reported by the HAL in the result metadata.\n *\n *     AF_STATE_INACTIVE: No focusing has been done, or algorithm was\n *        reset. Lens is not moving. Always the state for MODE_OFF or MODE_EDOF.\n *        When the device is opened, it must start in this state.\n *\n *     AF_STATE_PASSIVE_SCAN: A continuous focus algorithm is currently scanning\n *        for good focus. The lens is moving.\n *\n *     AF_STATE_PASSIVE_FOCUSED: A continuous focus algorithm believes it is\n *        well focused. The lens is not moving. The HAL may spontaneously leave\n *        this state.\n *\n *     AF_STATE_PASSIVE_UNFOCUSED: A continuous focus algorithm believes it is\n *        not well focused. The lens is not moving. The HAL may spontaneously\n *        leave this state.\n *\n *     AF_STATE_ACTIVE_SCAN: A scan triggered by the user is underway.\n *\n *     AF_STATE_FOCUSED_LOCKED: The AF algorithm believes it is focused. The\n *        lens is not moving.\n *\n *     AF_STATE_NOT_FOCUSED_LOCKED: The AF algorithm has been unable to\n *        focus. The lens is not moving.\n *\n *   ANDROID_CONTROL_AF_TRIGGER: Control for starting an autofocus scan, the\n *       meaning of which is mode- and state- dependent. Set by the framework in\n *       the request settings.\n *\n *     AF_TRIGGER_IDLE: No current trigger.\n *\n *     AF_TRIGGER_START: Trigger start of AF scan. Effect is mode and state\n *         dependent.\n *\n *     AF_TRIGGER_CANCEL: Cancel current AF scan if any, and reset algorithm to\n *         default.\n *\n *  Additional metadata entries:\n *\n *   ANDROID_CONTROL_AF_REGIONS: Control for selecting the regions of the FOV\n *       that should be used to determine good focus. This applies to all AF\n *       modes that scan for focus. Set by the framework in the request\n *       settings.\n *\n * S4.2. Auto-exposure settings and result entries:\n *\n *  Main metadata entries:\n *\n *   ANDROID_CONTROL_AE_MODE: Control for selecting the current auto-exposure\n *       mode. Set by the framework in the request settings.\n *\n *     AE_MODE_OFF: Autoexposure is disabled; the user controls exposure, gain,\n *         frame duration, and flash.\n *\n *     AE_MODE_ON: Standard autoexposure, with flash control disabled. User may\n *         set flash to fire or to torch mode.\n *\n *     AE_MODE_ON_AUTO_FLASH: Standard autoexposure, with flash on at HAL's\n *         discretion for precapture and still capture. User control of flash\n *         disabled.\n *\n *     AE_MODE_ON_ALWAYS_FLASH: Standard autoexposure, with flash always fired\n *         for capture, and at HAL's discretion for precapture.. User control of\n *         flash disabled.\n *\n *     AE_MODE_ON_AUTO_FLASH_REDEYE: Standard autoexposure, with flash on at\n *         HAL's discretion for precapture and still capture. Use a flash burst\n *         at end of precapture sequence to reduce redeye in the final\n *         picture. User control of flash disabled.\n *\n *   ANDROID_CONTROL_AE_STATE: Dynamic metadata describing the current AE\n *       algorithm state, reported by the HAL in the result metadata.\n *\n *     AE_STATE_INACTIVE: Initial AE state after mode switch. When the device is\n *         opened, it must start in this state.\n *\n *     AE_STATE_SEARCHING: AE is not converged to a good value, and is adjusting\n *         exposure parameters.\n *\n *     AE_STATE_CONVERGED: AE has found good exposure values for the current\n *         scene, and the exposure parameters are not changing. HAL may\n *         spontaneously leave this state to search for better solution.\n *\n *     AE_STATE_LOCKED: AE has been locked with the AE_LOCK control. Exposure\n *         values are not changing.\n *\n *     AE_STATE_FLASH_REQUIRED: The HAL has converged exposure, but believes\n *         flash is required for a sufficiently bright picture. Used for\n *         determining if a zero-shutter-lag frame can be used.\n *\n *     AE_STATE_PRECAPTURE: The HAL is in the middle of a precapture\n *         sequence. Depending on AE mode, this mode may involve firing the\n *         flash for metering, or a burst of flash pulses for redeye reduction.\n *\n *   ANDROID_CONTROL_AE_PRECAPTURE_TRIGGER: Control for starting a metering\n *       sequence before capturing a high-quality image. Set by the framework in\n *       the request settings.\n *\n *      PRECAPTURE_TRIGGER_IDLE: No current trigger.\n *\n *      PRECAPTURE_TRIGGER_START: Start a precapture sequence. The HAL should\n *         use the subsequent requests to measure good exposure/white balance\n *         for an upcoming high-resolution capture.\n *\n *  Additional metadata entries:\n *\n *   ANDROID_CONTROL_AE_LOCK: Control for locking AE controls to their current\n *       values\n *\n *   ANDROID_CONTROL_AE_EXPOSURE_COMPENSATION: Control for adjusting AE\n *       algorithm target brightness point.\n *\n *   ANDROID_CONTROL_AE_TARGET_FPS_RANGE: Control for selecting the target frame\n *       rate range for the AE algorithm. The AE routine cannot change the frame\n *       rate to be outside these bounds.\n *\n *   ANDROID_CONTROL_AE_REGIONS: Control for selecting the regions of the FOV\n *       that should be used to determine good exposure levels. This applies to\n *       all AE modes besides OFF.\n *\n * S4.3. Auto-whitebalance settings and result entries:\n *\n *  Main metadata entries:\n *\n *   ANDROID_CONTROL_AWB_MODE: Control for selecting the current white-balance\n *       mode.\n *\n *     AWB_MODE_OFF: Auto-whitebalance is disabled. User controls color matrix.\n *\n *     AWB_MODE_AUTO: Automatic white balance is enabled; 3A controls color\n *        transform, possibly using more complex transforms than a simple\n *        matrix.\n *\n *     AWB_MODE_INCANDESCENT: Fixed white balance settings good for indoor\n *        incandescent (tungsten) lighting, roughly 2700K.\n *\n *     AWB_MODE_FLUORESCENT: Fixed white balance settings good for fluorescent\n *        lighting, roughly 5000K.\n *\n *     AWB_MODE_WARM_FLUORESCENT: Fixed white balance settings good for\n *        fluorescent lighting, roughly 3000K.\n *\n *     AWB_MODE_DAYLIGHT: Fixed white balance settings good for daylight,\n *        roughly 5500K.\n *\n *     AWB_MODE_CLOUDY_DAYLIGHT: Fixed white balance settings good for clouded\n *        daylight, roughly 6500K.\n *\n *     AWB_MODE_TWILIGHT: Fixed white balance settings good for\n *        near-sunset/sunrise, roughly 15000K.\n *\n *     AWB_MODE_SHADE: Fixed white balance settings good for areas indirectly\n *        lit by the sun, roughly 7500K.\n *\n *   ANDROID_CONTROL_AWB_STATE: Dynamic metadata describing the current AWB\n *       algorithm state, reported by the HAL in the result metadata.\n *\n *     AWB_STATE_INACTIVE: Initial AWB state after mode switch. When the device\n *         is opened, it must start in this state.\n *\n *     AWB_STATE_SEARCHING: AWB is not converged to a good value, and is\n *         changing color adjustment parameters.\n *\n *     AWB_STATE_CONVERGED: AWB has found good color adjustment values for the\n *         current scene, and the parameters are not changing. HAL may\n *         spontaneously leave this state to search for better solution.\n *\n *     AWB_STATE_LOCKED: AWB has been locked with the AWB_LOCK control. Color\n *         adjustment values are not changing.\n *\n *  Additional metadata entries:\n *\n *   ANDROID_CONTROL_AWB_LOCK: Control for locking AWB color adjustments to\n *       their current values.\n *\n *   ANDROID_CONTROL_AWB_REGIONS: Control for selecting the regions of the FOV\n *       that should be used to determine good color balance. This applies only\n *       to auto-WB mode.\n *\n * S4.4. General state machine transition notes\n *\n *   Switching between AF, AE, or AWB modes always resets the algorithm's state\n *   to INACTIVE.  Similarly, switching between CONTROL_MODE or\n *   CONTROL_SCENE_MODE if CONTROL_MODE == USE_SCENE_MODE resets all the\n *   algorithm states to INACTIVE.\n *\n *   The tables below are per-mode.\n *\n * S4.5. AF state machines\n *\n *                       when enabling AF or changing AF mode\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| Any                | AF mode change| INACTIVE           |                  |\n *+--------------------+---------------+--------------------+------------------+\n *\n *                            mode = AF_MODE_OFF or AF_MODE_EDOF\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           |               | INACTIVE           | Never changes    |\n *+--------------------+---------------+--------------------+------------------+\n *\n *                            mode = AF_MODE_AUTO or AF_MODE_MACRO\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | AF_TRIGGER    | ACTIVE_SCAN        | Start AF sweep   |\n *|                    |               |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| ACTIVE_SCAN        | AF sweep done | FOCUSED_LOCKED     | If AF successful |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| ACTIVE_SCAN        | AF sweep done | NOT_FOCUSED_LOCKED | If AF successful |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| ACTIVE_SCAN        | AF_CANCEL     | INACTIVE           | Cancel/reset AF  |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| FOCUSED_LOCKED     | AF_CANCEL     | INACTIVE           | Cancel/reset AF  |\n *+--------------------+---------------+--------------------+------------------+\n *| FOCUSED_LOCKED     | AF_TRIGGER    | ACTIVE_SCAN        | Start new sweep  |\n *|                    |               |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| NOT_FOCUSED_LOCKED | AF_CANCEL     | INACTIVE           | Cancel/reset AF  |\n *+--------------------+---------------+--------------------+------------------+\n *| NOT_FOCUSED_LOCKED | AF_TRIGGER    | ACTIVE_SCAN        | Start new sweep  |\n *|                    |               |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| All states         | mode change   | INACTIVE           |                  |\n *+--------------------+---------------+--------------------+------------------+\n *\n *                            mode = AF_MODE_CONTINUOUS_VIDEO\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | HAL initiates | PASSIVE_SCAN       | Start AF scan    |\n *|                    | new scan      |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | AF_TRIGGER    | NOT_FOCUSED_LOCKED | AF state query   |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | HAL completes | PASSIVE_FOCUSED    | End AF scan      |\n *|                    | current scan  |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | HAL fails     | PASSIVE_UNFOCUSED  | End AF scan      |\n *|                    | current scan  |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | AF_TRIGGER    | FOCUSED_LOCKED     | Immediate trans. |\n *|                    |               |                    | if focus is good |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | AF_TRIGGER    | NOT_FOCUSED_LOCKED | Immediate trans. |\n *|                    |               |                    | if focus is bad  |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | AF_CANCEL     | INACTIVE           | Reset lens       |\n *|                    |               |                    | position         |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_FOCUSED    | HAL initiates | PASSIVE_SCAN       | Start AF scan    |\n *|                    | new scan      |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_UNFOCUSED  | HAL initiates | PASSIVE_SCAN       | Start AF scan    |\n *|                    | new scan      |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_FOCUSED    | AF_TRIGGER    | FOCUSED_LOCKED     | Immediate trans. |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_UNFOCUSED  | AF_TRIGGER    | NOT_FOCUSED_LOCKED | Immediate trans. |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| FOCUSED_LOCKED     | AF_TRIGGER    | FOCUSED_LOCKED     | No effect        |\n *+--------------------+---------------+--------------------+------------------+\n *| FOCUSED_LOCKED     | AF_CANCEL     | INACTIVE           | Restart AF scan  |\n *+--------------------+---------------+--------------------+------------------+\n *| NOT_FOCUSED_LOCKED | AF_TRIGGER    | NOT_FOCUSED_LOCKED | No effect        |\n *+--------------------+---------------+--------------------+------------------+\n *| NOT_FOCUSED_LOCKED | AF_CANCEL     | INACTIVE           | Restart AF scan  |\n *+--------------------+---------------+--------------------+------------------+\n *\n *                            mode = AF_MODE_CONTINUOUS_PICTURE\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | HAL initiates | PASSIVE_SCAN       | Start AF scan    |\n *|                    | new scan      |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | AF_TRIGGER    | NOT_FOCUSED_LOCKED | AF state query   |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | HAL completes | PASSIVE_FOCUSED    | End AF scan      |\n *|                    | current scan  |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | HAL fails     | PASSIVE_UNFOCUSED  | End AF scan      |\n *|                    | current scan  |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | AF_TRIGGER    | FOCUSED_LOCKED     | Eventual trans.  |\n *|                    |               |                    | once focus good  |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | AF_TRIGGER    | NOT_FOCUSED_LOCKED | Eventual trans.  |\n *|                    |               |                    | if cannot focus  |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_SCAN       | AF_CANCEL     | INACTIVE           | Reset lens       |\n *|                    |               |                    | position         |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_FOCUSED    | HAL initiates | PASSIVE_SCAN       | Start AF scan    |\n *|                    | new scan      |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_UNFOCUSED  | HAL initiates | PASSIVE_SCAN       | Start AF scan    |\n *|                    | new scan      |                    | Lens now moving  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_FOCUSED    | AF_TRIGGER    | FOCUSED_LOCKED     | Immediate trans. |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| PASSIVE_UNFOCUSED  | AF_TRIGGER    | NOT_FOCUSED_LOCKED | Immediate trans. |\n *|                    |               |                    | Lens now locked  |\n *+--------------------+---------------+--------------------+------------------+\n *| FOCUSED_LOCKED     | AF_TRIGGER    | FOCUSED_LOCKED     | No effect        |\n *+--------------------+---------------+--------------------+------------------+\n *| FOCUSED_LOCKED     | AF_CANCEL     | INACTIVE           | Restart AF scan  |\n *+--------------------+---------------+--------------------+------------------+\n *| NOT_FOCUSED_LOCKED | AF_TRIGGER    | NOT_FOCUSED_LOCKED | No effect        |\n *+--------------------+---------------+--------------------+------------------+\n *| NOT_FOCUSED_LOCKED | AF_CANCEL     | INACTIVE           | Restart AF scan  |\n *+--------------------+---------------+--------------------+------------------+\n *\n * S4.6. AE and AWB state machines\n *\n *   The AE and AWB state machines are mostly identical. AE has additional\n *   FLASH_REQUIRED and PRECAPTURE states. So rows below that refer to those two\n *   states should be ignored for the AWB state machine.\n *\n *                  when enabling AE/AWB or changing AE/AWB mode\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| Any                |  mode change  | INACTIVE           |                  |\n *+--------------------+---------------+--------------------+------------------+\n *\n *                            mode = AE_MODE_OFF / AWB mode not AUTO\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           |               | INACTIVE           | AE/AWB disabled  |\n *+--------------------+---------------+--------------------+------------------+\n *\n *                            mode = AE_MODE_ON_* / AWB_MODE_AUTO\n *| state              | trans. cause  | new state          | notes            |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | HAL initiates | SEARCHING          |                  |\n *|                    | AE/AWB scan   |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| INACTIVE           | AE/AWB_LOCK   | LOCKED             | values locked    |\n *|                    | on            |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| SEARCHING          | HAL finishes  | CONVERGED          | good values, not |\n *|                    | AE/AWB scan   |                    | changing         |\n *+--------------------+---------------+--------------------+------------------+\n *| SEARCHING          | HAL finishes  | FLASH_REQUIRED     | converged but too|\n *|                    | AE scan       |                    | dark w/o flash   |\n *+--------------------+---------------+--------------------+------------------+\n *| SEARCHING          | AE/AWB_LOCK   | LOCKED             | values locked    |\n *|                    | on            |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| CONVERGED          | HAL initiates | SEARCHING          | values locked    |\n *|                    | AE/AWB scan   |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| CONVERGED          | AE/AWB_LOCK   | LOCKED             | values locked    |\n *|                    | on            |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| FLASH_REQUIRED     | HAL initiates | SEARCHING          | values locked    |\n *|                    | AE/AWB scan   |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| FLASH_REQUIRED     | AE/AWB_LOCK   | LOCKED             | values locked    |\n *|                    | on            |                    |                  |\n *+--------------------+---------------+--------------------+------------------+\n *| LOCKED             | AE/AWB_LOCK   | SEARCHING          | values not good  |\n *|                    | off           |                    | after unlock     |\n *+--------------------+---------------+--------------------+------------------+\n *| LOCKED             | AE/AWB_LOCK   | CONVERGED          | values good      |\n *|                    | off           |                    | after unlock     |\n *+--------------------+---------------+--------------------+------------------+\n *| LOCKED             | AE_LOCK       | FLASH_REQUIRED     | exposure good,   |\n *|                    | off           |                    | but too dark     |\n *+--------------------+---------------+--------------------+------------------+\n *| All AE states      | PRECAPTURE_   | PRECAPTURE         | Start precapture |\n *|                    | START         |                    | sequence         |\n *+--------------------+---------------+--------------------+------------------+\n *| PRECAPTURE         | Sequence done.| CONVERGED          | Ready for high-  |\n *|                    | AE_LOCK off   |                    | quality capture  |\n *+--------------------+---------------+--------------------+------------------+\n *| PRECAPTURE         | Sequence done.| LOCKED             | Ready for high-  |\n *|                    | AE_LOCK on    |                    | quality capture  |\n *+--------------------+---------------+--------------------+------------------+\n *\n */\n\n/**\n * S5. Cropping:\n *\n * Cropping of the full pixel array (for digital zoom and other use cases where\n * a smaller FOV is desirable) is communicated through the\n * ANDROID_SCALER_CROP_REGION setting. This is a per-request setting, and can\n * change on a per-request basis, which is critical for implementing smooth\n * digital zoom.\n *\n * The region is defined as a rectangle (x, y, width, height), with (x, y)\n * describing the top-left corner of the rectangle. The rectangle is defined on\n * the coordinate system of the sensor active pixel array, with (0,0) being the\n * top-left pixel of the active pixel array. Therefore, the width and height\n * cannot be larger than the dimensions reported in the\n * ANDROID_SENSOR_ACTIVE_PIXEL_ARRAY static info field. The minimum allowed\n * width and height are reported by the HAL through the\n * ANDROID_SCALER_MAX_DIGITAL_ZOOM static info field, which describes the\n * maximum supported zoom factor. Therefore, the minimum crop region width and\n * height are:\n *\n * {width, height} =\n *    { floor(ANDROID_SENSOR_ACTIVE_PIXEL_ARRAY[0] /\n *        ANDROID_SCALER_MAX_DIGITAL_ZOOM),\n *      floor(ANDROID_SENSOR_ACTIVE_PIXEL_ARRAY[1] /\n *        ANDROID_SCALER_MAX_DIGITAL_ZOOM) }\n *\n * If the crop region needs to fulfill specific requirements (for example, it\n * needs to start on even coordinates, and its width/height needs to be even),\n * the HAL must do the necessary rounding and write out the final crop region\n * used in the output result metadata. Similarly, if the HAL implements video\n * stabilization, it must adjust the result crop region to describe the region\n * actually included in the output after video stabilization is applied. In\n * general, a camera-using application must be able to determine the field of\n * view it is receiving based on the crop region, the dimensions of the image\n * sensor, and the lens focal length.\n *\n * It is assumed that the cropping is applied after raw to other color space\n * conversion. Raw streams (RAW16 and RAW_OPAQUE) don't have this conversion stage,\n * and are not croppable. Therefore, the crop region must be ignored by the HAL\n * for raw streams.\n *\n * Since the crop region applies to all non-raw streams, which may have different aspect\n * ratios than the crop region, the exact sensor region used for each stream may\n * be smaller than the crop region. Specifically, each stream should maintain\n * square pixels and its aspect ratio by minimally further cropping the defined\n * crop region. If the stream's aspect ratio is wider than the crop region, the\n * stream should be further cropped vertically, and if the stream's aspect ratio\n * is narrower than the crop region, the stream should be further cropped\n * horizontally.\n *\n * In all cases, the stream crop must be centered within the full crop region,\n * and each stream is only either cropped horizontally or vertical relative to\n * the full crop region, never both.\n *\n * For example, if two streams are defined, a 640x480 stream (4:3 aspect), and a\n * 1280x720 stream (16:9 aspect), below demonstrates the expected output regions\n * for each stream for a few sample crop regions, on a hypothetical 3 MP (2000 x\n * 1500 pixel array) sensor.\n *\n * Crop region: (500, 375, 1000, 750) (4:3 aspect ratio)\n *\n *   640x480 stream crop: (500, 375, 1000, 750) (equal to crop region)\n *   1280x720 stream crop: (500, 469, 1000, 562) (marked with =)\n *\n * 0                   1000               2000\n * +---------+---------+---------+----------+\n * | Active pixel array                     |\n * |                                        |\n * |                                        |\n * +         +-------------------+          + 375\n * |         |                   |          |\n * |         O===================O          |\n * |         I 1280x720 stream   I          |\n * +         I                   I          + 750\n * |         I                   I          |\n * |         O===================O          |\n * |         |                   |          |\n * +         +-------------------+          + 1125\n * |          Crop region, 640x480 stream   |\n * |                                        |\n * |                                        |\n * +---------+---------+---------+----------+ 1500\n *\n * Crop region: (500, 375, 1333, 750) (16:9 aspect ratio)\n *\n *   640x480 stream crop: (666, 375, 1000, 750) (marked with =)\n *   1280x720 stream crop: (500, 375, 1333, 750) (equal to crop region)\n *\n * 0                   1000               2000\n * +---------+---------+---------+----------+\n * | Active pixel array                     |\n * |                                        |\n * |                                        |\n * +         +---O==================O---+   + 375\n * |         |   I 640x480 stream   I   |   |\n * |         |   I                  I   |   |\n * |         |   I                  I   |   |\n * +         |   I                  I   |   + 750\n * |         |   I                  I   |   |\n * |         |   I                  I   |   |\n * |         |   I                  I   |   |\n * +         +---O==================O---+   + 1125\n * |          Crop region, 1280x720 stream  |\n * |                                        |\n * |                                        |\n * +---------+---------+---------+----------+ 1500\n *\n * Crop region: (500, 375, 750, 750) (1:1 aspect ratio)\n *\n *   640x480 stream crop: (500, 469, 750, 562) (marked with =)\n *   1280x720 stream crop: (500, 543, 750, 414) (marged with #)\n *\n * 0                   1000               2000\n * +---------+---------+---------+----------+\n * | Active pixel array                     |\n * |                                        |\n * |                                        |\n * +         +--------------+               + 375\n * |         O==============O               |\n * |         ################               |\n * |         #              #               |\n * +         #              #               + 750\n * |         #              #               |\n * |         ################ 1280x720      |\n * |         O==============O 640x480       |\n * +         +--------------+               + 1125\n * |          Crop region                   |\n * |                                        |\n * |                                        |\n * +---------+---------+---------+----------+ 1500\n *\n * And a final example, a 1024x1024 square aspect ratio stream instead of the\n * 480p stream:\n *\n * Crop region: (500, 375, 1000, 750) (4:3 aspect ratio)\n *\n *   1024x1024 stream crop: (625, 375, 750, 750) (marked with #)\n *   1280x720 stream crop: (500, 469, 1000, 562) (marked with =)\n *\n * 0                   1000               2000\n * +---------+---------+---------+----------+\n * | Active pixel array                     |\n * |                                        |\n * |              1024x1024 stream          |\n * +         +--###############--+          + 375\n * |         |  #             #  |          |\n * |         O===================O          |\n * |         I 1280x720 stream   I          |\n * +         I                   I          + 750\n * |         I                   I          |\n * |         O===================O          |\n * |         |  #             #  |          |\n * +         +--###############--+          + 1125\n * |          Crop region                   |\n * |                                        |\n * |                                        |\n * +---------+---------+---------+----------+ 1500\n *\n */\n\n/**\n * S6. Error management:\n *\n * Camera HAL device ops functions that have a return value will all return\n * -ENODEV / NULL in case of a serious error. This means the device cannot\n * continue operation, and must be closed by the framework. Once this error is\n * returned by some method, or if notify() is called with ERROR_DEVICE, only\n * the close() method can be called successfully. All other methods will return\n * -ENODEV / NULL.\n *\n * If a device op is called in the wrong sequence, for example if the framework\n * calls configure_streams() is called before initialize(), the device must\n * return -ENOSYS from the call, and do nothing.\n *\n * Transient errors in image capture must be reported through notify() as follows:\n *\n * - The failure of an entire capture to occur must be reported by the HAL by\n *   calling notify() with ERROR_REQUEST. Individual errors for the result\n *   metadata or the output buffers must not be reported in this case.\n *\n * - If the metadata for a capture cannot be produced, but some image buffers\n *   were filled, the HAL must call notify() with ERROR_RESULT.\n *\n * - If an output image buffer could not be filled, but either the metadata was\n *   produced or some other buffers were filled, the HAL must call notify() with\n *   ERROR_BUFFER for each failed buffer.\n *\n * In each of these transient failure cases, the HAL must still call\n * process_capture_result, with valid output and input (if an input buffer was\n * submitted) buffer_handle_t. If the result metadata could not be produced, it\n * should be NULL. If some buffers could not be filled, they must be returned with\n * process_capture_result in the error state, their release fences must be set to\n * the acquire fences passed by the framework, or -1 if they have been waited on by\n * the HAL already.\n *\n * Invalid input arguments result in -EINVAL from the appropriate methods. In\n * that case, the framework must act as if that call had never been made.\n *\n */\n\n/**\n * S7. Key Performance Indicator (KPI) glossary:\n *\n * This includes some critical definitions that are used by KPI metrics.\n *\n * Pipeline Latency:\n *  For a given capture request, the duration from the framework calling\n *  process_capture_request to the HAL sending capture result and all buffers\n *  back by process_capture_result call. To make the Pipeline Latency measure\n *  independent of frame rate, it is measured by frame count.\n *\n *  For example, when frame rate is 30 (fps), the frame duration (time interval\n *  between adjacent frame capture time) is 33 (ms).\n *  If it takes 5 frames for framework to get the result and buffers back for\n *  a given request, then the Pipeline Latency is 5 (frames), instead of\n *  5 x 33 = 165 (ms).\n *\n *  The Pipeline Latency is determined by android.request.pipelineDepth and\n *  android.request.pipelineMaxDepth, see their definitions for more details.\n *\n */\n\n/**\n * S8. Sample Use Cases:\n *\n * This includes some typical use case examples the camera HAL may support.\n *\n * S8.1 Zero Shutter Lag (ZSL) with CAMERA3_STREAM_BIDIRECTIONAL stream.\n *\n *   For this use case, the bidirectional stream will be used by the framework as follows:\n *\n *   1. The framework includes a buffer from this stream as output buffer in a\n *      request as normal.\n *\n *   2. Once the HAL device returns a filled output buffer to the framework,\n *      the framework may do one of two things with the filled buffer:\n *\n *   2. a. The framework uses the filled data, and returns the now-used buffer\n *         to the stream queue for reuse. This behavior exactly matches the\n *         OUTPUT type of stream.\n *\n *   2. b. The framework wants to reprocess the filled data, and uses the\n *         buffer as an input buffer for a request. Once the HAL device has\n *         used the reprocessing buffer, it then returns it to the\n *         framework. The framework then returns the now-used buffer to the\n *         stream queue for reuse.\n *\n *   3. The HAL device will be given the buffer again as an output buffer for\n *        a request at some future point.\n *\n *   For ZSL use case, the pixel format for bidirectional stream will be\n *   HAL_PIXEL_FORMAT_RAW_OPAQUE or HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED if it\n *   is listed in android.scaler.availableInputOutputFormatsMap. When\n *   HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED is used, the gralloc\n *   usage flags for the consumer endpoint will be set to GRALLOC_USAGE_HW_CAMERA_ZSL.\n *   A configuration stream list that has BIDIRECTIONAL stream used as input, will\n *   usually also have a distinct OUTPUT stream to get the reprocessing data. For example,\n *   for the ZSL use case, the stream list might be configured with the following:\n *\n *     - A HAL_PIXEL_FORMAT_RAW_OPAQUE bidirectional stream is used\n *       as input.\n *     - And a HAL_PIXEL_FORMAT_BLOB (JPEG) output stream.\n *\n * S8.2 ZSL (OPAQUE) reprocessing with CAMERA3_STREAM_INPUT stream.\n *\n * CAMERA_DEVICE_API_VERSION_3_3:\n *   When OPAQUE_REPROCESSING capability is supported by the camera device, the INPUT stream\n *   can be used for application/framework implemented use case like Zero Shutter Lag (ZSL).\n *   This kind of stream will be used by the framework as follows:\n *\n *   1. Application/framework configures an opaque (RAW or YUV based) format output stream that is\n *      used to produce the ZSL output buffers. The stream pixel format will be\n *      HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED.\n *\n *   2. Application/framework configures an opaque format input stream that is used to\n *      send the reprocessing ZSL buffers to the HAL. The stream pixel format will\n *      also be HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED.\n *\n *   3. Application/framework configures a YUV/JPEG output stream that is used to receive the\n *      reprocessed data. The stream pixel format will be YCbCr_420/HAL_PIXEL_FORMAT_BLOB.\n *\n *   4. Application/framework picks a ZSL buffer from the ZSL output stream when a ZSL capture is\n *      issued by the application, and sends the data back as an input buffer in a\n *      reprocessing request, then sends to the HAL for reprocessing.\n *\n *   5. The HAL sends back the output YUV/JPEG result to framework.\n *\n *   The HAL can select the actual opaque buffer format and configure the ISP pipeline\n *   appropriately based on the HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED format and\n *   the gralloc usage flag GRALLOC_USAGE_HW_CAMERA_ZSL.\n\n * S8.3 YUV reprocessing with CAMERA3_STREAM_INPUT stream.\n *\n *   When YUV reprocessing is supported by the HAL, the INPUT stream\n *   can be used for the YUV reprocessing use cases like lucky-shot and image fusion.\n *   This kind of stream will be used by the framework as follows:\n *\n *   1. Application/framework configures an YCbCr_420 format output stream that is\n *      used to produce the output buffers.\n *\n *   2. Application/framework configures an YCbCr_420 format input stream that is used to\n *      send the reprocessing YUV buffers to the HAL.\n *\n *   3. Application/framework configures a YUV/JPEG output stream that is used to receive the\n *      reprocessed data. The stream pixel format will be YCbCr_420/HAL_PIXEL_FORMAT_BLOB.\n *\n *   4. Application/framework processes the output buffers (could be as simple as picking\n *      an output buffer directly) from the output stream when a capture is issued, and sends\n *      the data back as an input buffer in a reprocessing request, then sends to the HAL\n *      for reprocessing.\n *\n *   5. The HAL sends back the output YUV/JPEG result to framework.\n *\n */\n\n/**\n *   S9. Notes on Controls and Metadata\n *\n *   This section contains notes about the interpretation and usage of various metadata tags.\n *\n *   S9.1 HIGH_QUALITY and FAST modes.\n *\n *   Many camera post-processing blocks may be listed as having HIGH_QUALITY,\n *   FAST, and OFF operating modes. These blocks will typically also have an\n *   'available modes' tag representing which of these operating modes are\n *   available on a given device. The general policy regarding implementing\n *   these modes is as follows:\n *\n *   1. Operating mode controls of hardware blocks that cannot be disabled\n *      must not list OFF in their corresponding 'available modes' tags.\n *\n *   2. OFF will always be included in their corresponding 'available modes'\n *      tag if it is possible to disable that hardware block.\n *\n *   3. FAST must always be included in the 'available modes' tags for all\n *      post-processing blocks supported on the device.  If a post-processing\n *      block also has a slower and higher quality operating mode that does\n *      not meet the framerate requirements for FAST mode, HIGH_QUALITY should\n *      be included in the 'available modes' tag to represent this operating\n *      mode.\n */\n\n/**\n *   S10. Reprocessing flow and controls\n *\n *   This section describes the OPAQUE and YUV reprocessing flow and controls. OPAQUE reprocessing\n *   uses an opaque format that is not directly application-visible, and the application can\n *   only select some of the output buffers and send back to HAL for reprocessing, while YUV\n *   reprocessing gives the application opportunity to process the buffers before reprocessing.\n *\n *   S8 gives the stream configurations for the typical reprocessing uses cases,\n *   this section specifies the buffer flow and controls in more details.\n *\n *   S10.1 OPAQUE (typically for ZSL use case) reprocessing flow and controls\n *\n *   For OPAQUE reprocessing (e.g. ZSL) use case, after the application creates the specific\n *   output and input streams, runtime buffer flow and controls are specified as below:\n *\n *   1. Application starts output streaming by sending repeating requests for output\n *      opaque buffers and preview. The buffers are held by an application\n *      maintained circular buffer. The requests are based on CAMERA3_TEMPLATE_ZERO_SHUTTER_LAG\n *      capture template, which should have all necessary settings that guarantee output\n *      frame rate is not slowed down relative to sensor output frame rate.\n *\n *   2. When a capture is issued, the application selects one output buffer based\n *      on application buffer selection logic, e.g. good AE and AF statistics etc.\n *      Application then creates an reprocess request based on the capture result associated\n *      with this selected buffer. The selected output buffer is now added to this reprocess\n *      request as an input buffer, the output buffer of this reprocess request should be\n *      either JPEG output buffer or YUV output buffer, or both, depending on the application\n *      choice.\n *\n *   3. Application then alters the reprocess settings to get best image quality. The HAL must\n *      support and only support below controls if the HAL support OPAQUE_REPROCESSING capability:\n *          - android.jpeg.* (if JPEG buffer is included as one of the output)\n *          - android.noiseReduction.mode (change to HIGH_QUALITY if it is supported)\n *          - android.edge.mode (change to HIGH_QUALITY if it is supported)\n *       All other controls must be ignored by the HAL.\n *   4. HAL processed the input buffer and return the output buffers in the capture results\n *      as normal.\n *\n *   S10.2 YUV reprocessing flow and controls\n *\n *   The YUV reprocessing buffer flow is similar as OPAQUE reprocessing, with below difference:\n *\n *   1. Application may want to have finer granularity control of the intermediate YUV images\n *      (before reprocessing). For example, application may choose\n *          - android.noiseReduction.mode == MINIMAL\n *      to make sure the no YUV domain noise reduction has applied to the output YUV buffers,\n *      then it can do its own advanced noise reduction on them. For OPAQUE reprocessing case, this\n *      doesn't matter, as long as the final reprocessed image has the best quality.\n *   2. Application may modify the YUV output buffer data. For example, for image fusion use\n *      case, where multiple output images are merged together to improve the signal-to-noise\n *      ratio (SNR). The input buffer may be generated from multiple buffers by the application.\n *      To avoid excessive amount of noise reduction and insufficient amount of edge enhancement\n *      being applied to the input buffer, the application can hint the HAL  how much effective\n *      exposure time improvement has been done by the application, then the HAL can adjust the\n *      noise reduction and edge enhancement paramters to get best reprocessed image quality.\n *      Below tag can be used for this purpose:\n *          - android.reprocess.effectiveExposureFactor\n *      The value would be exposure time increase factor applied to the original output image,\n *      for example, if there are N image merged, the exposure time increase factor would be up\n *      to sqrt(N). See this tag spec for more details.\n *\n *   S10.3 Reprocessing pipeline characteristics\n *\n *   Reprocessing pipeline has below different characteristics comparing with normal output\n *   pipeline:\n *\n *   1. The reprocessing result can be returned ahead of the pending normal output results. But\n *      the FIFO ordering must be maintained for all reprocessing results. For example, there are\n *      below requests (A stands for output requests, B stands for reprocessing requests)\n *      being processed by the HAL:\n *          A1, A2, A3, A4, B1, A5, B2, A6...\n *      result of B1 can be returned before A1-A4, but result of B2 must be returned after B1.\n *   2. Single input rule: For a given reprocessing request, all output buffers must be from the\n *      input buffer, rather than sensor output. For example, if a reprocess request include both\n *      JPEG and preview buffers, all output buffers must be produced from the input buffer\n *      included by the reprocessing request, rather than sensor. The HAL must not output preview\n *      buffers from sensor, while output JPEG buffer from the input buffer.\n *   3. Input buffer will be from camera output directly (ZSL case) or indirectly(image fusion\n *      case). For the case where buffer is modified, the size will remain same. The HAL can\n *      notify CAMERA3_MSG_ERROR_REQUEST if buffer from unknown source is sent.\n *   4. Result as reprocessing request: The HAL can expect that a reprocessing request is a copy\n *      of one of the output results with minor allowed setting changes. The HAL can notify\n *      CAMERA3_MSG_ERROR_REQUEST if a request from unknown source is issued.\n *   5. Output buffers may not be used as inputs across the configure stream boundary, This is\n *      because an opaque stream like the ZSL output stream may have different actual image size\n *      inside of the ZSL buffer to save power and bandwidth for smaller resolution JPEG capture.\n *      The HAL may notify CAMERA3_MSG_ERROR_REQUEST if this case occurs.\n *   6. HAL Reprocess requests error reporting during flush should follow the same rule specified\n *      by flush() method.\n *\n */\n\n__BEGIN_DECLS\n\nstruct camera3_device;\n\n/**********************************************************************\n *\n * Camera3 stream and stream buffer definitions.\n *\n * These structs and enums define the handles and contents of the input and\n * output streams connecting the HAL to various framework and application buffer\n * consumers. Each stream is backed by a gralloc buffer queue.\n *\n */\n\n/**\n * camera3_stream_type_t:\n *\n * The type of the camera stream, which defines whether the camera HAL device is\n * the producer or the consumer for that stream, and how the buffers of the\n * stream relate to the other streams.\n */\ntypedef enum camera3_stream_type {\n    /**\n     * This stream is an output stream; the camera HAL device will be\n     * responsible for filling buffers from this stream with newly captured or\n     * reprocessed image data.\n     */\n    CAMERA3_STREAM_OUTPUT = 0,\n\n    /**\n     * This stream is an input stream; the camera HAL device will be responsible\n     * for reading buffers from this stream and sending them through the camera\n     * processing pipeline, as if the buffer was a newly captured image from the\n     * imager.\n     *\n     * The pixel format for input stream can be any format reported by\n     * android.scaler.availableInputOutputFormatsMap. The pixel format of the\n     * output stream that is used to produce the reprocessing data may be any\n     * format reported by android.scaler.availableStreamConfigurations. The\n     * supported input/output stream combinations depends the camera device\n     * capabilities, see android.scaler.availableInputOutputFormatsMap for\n     * stream map details.\n     *\n     * This kind of stream is generally used to reprocess data into higher\n     * quality images (that otherwise would cause a frame rate performance\n     * loss), or to do off-line reprocessing.\n     *\n     * CAMERA_DEVICE_API_VERSION_3_3:\n     *    The typical use cases are OPAQUE (typically ZSL) and YUV reprocessing,\n     *    see S8.2, S8.3 and S10 for more details.\n     */\n    CAMERA3_STREAM_INPUT = 1,\n\n    /**\n     * This stream can be used for input and output. Typically, the stream is\n     * used as an output stream, but occasionally one already-filled buffer may\n     * be sent back to the HAL device for reprocessing.\n     *\n     * This kind of stream is meant generally for Zero Shutter Lag (ZSL)\n     * features, where copying the captured image from the output buffer to the\n     * reprocessing input buffer would be expensive. See S8.1 for more details.\n     *\n     * Note that the HAL will always be reprocessing data it produced.\n     *\n     */\n    CAMERA3_STREAM_BIDIRECTIONAL = 2,\n\n    /**\n     * Total number of framework-defined stream types\n     */\n    CAMERA3_NUM_STREAM_TYPES\n\n} camera3_stream_type_t;\n\n/**\n * camera3_stream_rotation_t:\n *\n * The required counterclockwise rotation of camera stream.\n */\ntypedef enum camera3_stream_rotation {\n    /* No rotation */\n    CAMERA3_STREAM_ROTATION_0 = 0,\n\n    /* Rotate by 90 degree counterclockwise */\n    CAMERA3_STREAM_ROTATION_90 = 1,\n\n    /* Rotate by 180 degree counterclockwise */\n    CAMERA3_STREAM_ROTATION_180 = 2,\n\n    /* Rotate by 270 degree counterclockwise */\n    CAMERA3_STREAM_ROTATION_270 = 3\n} camera3_stream_rotation_t;\n\n/**\n * camera3_stream_configuration_mode_t:\n *\n * This defines the general operation mode for the HAL (for a given stream configuration), where\n * modes besides NORMAL have different semantics, and usually limit the generality of the API in\n * exchange for higher performance in some particular area.\n */\ntypedef enum camera3_stream_configuration_mode {\n    /**\n     * Normal stream configuration operation mode. This is the default camera operation mode,\n     * where all semantics of HAL APIs and metadata controls apply.\n     */\n    CAMERA3_STREAM_CONFIGURATION_NORMAL_MODE = 0,\n\n    /**\n     * Special constrained high speed operation mode for devices that can not support high\n     * speed output in NORMAL mode. All streams in this configuration are operating at high speed\n     * mode and have different characteristics and limitations to achieve high speed output.\n     * The NORMAL mode can still be used for high speed output if the HAL can support high speed\n     * output while satisfying all the semantics of HAL APIs and metadata controls. It is\n     * recommended for the HAL to support high speed output in NORMAL mode (by advertising the high\n     * speed FPS ranges in android.control.aeAvailableTargetFpsRanges) if possible.\n     *\n     * This mode has below limitations/requirements:\n     *\n     *   1. The HAL must support up to 2 streams with sizes reported by\n     *      android.control.availableHighSpeedVideoConfigurations.\n     *   2. In this mode, the HAL is expected to output up to 120fps or higher. This mode must\n     *      support the targeted FPS range and size configurations reported by\n     *      android.control.availableHighSpeedVideoConfigurations.\n     *   3. The HAL must support HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED output stream format.\n     *   4. To achieve efficient high speed streaming, the HAL may have to aggregate\n     *      multiple frames together and send to camera device for processing where the request\n     *      controls are same for all the frames in this batch (batch mode). The HAL must support\n     *      max batch size and the max batch size requirements defined by\n     *      android.control.availableHighSpeedVideoConfigurations.\n     *   5. In this mode, the HAL must override aeMode, awbMode, and afMode to ON, ON, and\n     *      CONTINUOUS_VIDEO, respectively. All post-processing block mode controls must be\n     *      overridden to be FAST. Therefore, no manual control of capture and post-processing\n     *      parameters is possible. All other controls operate the same as when\n     *      android.control.mode == AUTO. This means that all other android.control.* fields\n     *      must continue to work, such as\n     *\n     *      android.control.aeTargetFpsRange\n     *      android.control.aeExposureCompensation\n     *      android.control.aeLock\n     *      android.control.awbLock\n     *      android.control.effectMode\n     *      android.control.aeRegions\n     *      android.control.afRegions\n     *      android.control.awbRegions\n     *      android.control.afTrigger\n     *      android.control.aePrecaptureTrigger\n     *\n     *      Outside of android.control.*, the following controls must work:\n     *\n     *      android.flash.mode (TORCH mode only, automatic flash for still capture will not work\n     *      since aeMode is ON)\n     *      android.lens.opticalStabilizationMode (if it is supported)\n     *      android.scaler.cropRegion\n     *      android.statistics.faceDetectMode (if it is supported)\n     *\n     * For more details about high speed stream requirements, see\n     * android.control.availableHighSpeedVideoConfigurations and CONSTRAINED_HIGH_SPEED_VIDEO\n     * capability defined in android.request.availableCapabilities.\n     *\n     * This mode only needs to be supported by HALs that include CONSTRAINED_HIGH_SPEED_VIDEO in\n     * the android.request.availableCapabilities static metadata.\n     */\n    CAMERA3_STREAM_CONFIGURATION_CONSTRAINED_HIGH_SPEED_MODE = 1,\n\n    /**\n     * First value for vendor-defined stream configuration modes.\n     */\n    CAMERA3_VENDOR_STREAM_CONFIGURATION_MODE_START = 0x8000\n} camera3_stream_configuration_mode_t;\n\n/**\n * camera3_stream_t:\n *\n * A handle to a single camera input or output stream. A stream is defined by\n * the framework by its buffer resolution and format, and additionally by the\n * HAL with the gralloc usage flags and the maximum in-flight buffer count.\n *\n * The stream structures are owned by the framework, but pointers to a\n * camera3_stream passed into the HAL by configure_streams() are valid until the\n * end of the first subsequent configure_streams() call that _does not_ include\n * that camera3_stream as an argument, or until the end of the close() call.\n *\n * All camera3_stream framework-controlled members are immutable once the\n * camera3_stream is passed into configure_streams().  The HAL may only change\n * the HAL-controlled parameters during a configure_streams() call, except for\n * the contents of the private pointer.\n *\n * If a configure_streams() call returns a non-fatal error, all active streams\n * remain valid as if configure_streams() had not been called.\n *\n * The endpoint of the stream is not visible to the camera HAL device.\n * In DEVICE_API_VERSION_3_1, this was changed to share consumer usage flags\n * on streams where the camera is a producer (OUTPUT and BIDIRECTIONAL stream\n * types) see the usage field below.\n */\ntypedef struct camera3_stream {\n\n    /*****\n     * Set by framework before configure_streams()\n     */\n\n    /**\n     * The type of the stream, one of the camera3_stream_type_t values.\n     */\n    int stream_type;\n\n    /**\n     * The width in pixels of the buffers in this stream\n     */\n    uint32_t width;\n\n    /**\n     * The height in pixels of the buffers in this stream\n     */\n    uint32_t height;\n\n    /**\n     * The pixel format for the buffers in this stream. Format is a value from\n     * the HAL_PIXEL_FORMAT_* list in system/core/include/system/graphics.h, or\n     * from device-specific headers.\n     *\n     * If HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED is used, then the platform\n     * gralloc module will select a format based on the usage flags provided by\n     * the camera device and the other endpoint of the stream.\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     * The camera HAL device must inspect the buffers handed to it in the\n     * subsequent register_stream_buffers() call to obtain the\n     * implementation-specific format details, if necessary.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * register_stream_buffers() won't be called by the framework, so the HAL\n     * should configure the ISP and sensor pipeline based purely on the sizes,\n     * usage flags, and formats for the configured streams.\n     */\n    int format;\n\n    /*****\n     * Set by HAL during configure_streams().\n     */\n\n    /**\n     * The gralloc usage flags for this stream, as needed by the HAL. The usage\n     * flags are defined in gralloc.h (GRALLOC_USAGE_*), or in device-specific\n     * headers.\n     *\n     * For output streams, these are the HAL's producer usage flags. For input\n     * streams, these are the HAL's consumer usage flags. The usage flags from\n     * the producer and the consumer will be combined together and then passed\n     * to the platform gralloc HAL module for allocating the gralloc buffers for\n     * each stream.\n     *\n     * Version information:\n     *\n     * == CAMERA_DEVICE_API_VERSION_3_0:\n     *\n     *   No initial value guaranteed when passed via configure_streams().\n     *   HAL may not use this field as input, and must write over this field\n     *   with its usage flags.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     *   For stream_type OUTPUT and BIDIRECTIONAL, when passed via\n     *   configure_streams(), the initial value of this is the consumer's\n     *   usage flags.  The HAL may use these consumer flags to decide stream\n     *   configuration.\n     *   For stream_type INPUT, when passed via configure_streams(), the initial\n     *   value of this is 0.\n     *   For all streams passed via configure_streams(), the HAL must write\n     *   over this field with its usage flags.\n     */\n    uint32_t usage;\n\n    /**\n     * The maximum number of buffers the HAL device may need to have dequeued at\n     * the same time. The HAL device may not have more buffers in-flight from\n     * this stream than this value.\n     */\n    uint32_t max_buffers;\n\n    /**\n     * A handle to HAL-private information for the stream. Will not be inspected\n     * by the framework code.\n     */\n    void *priv;\n\n    /**\n     * A field that describes the contents of the buffer. The format and buffer\n     * dimensions define the memory layout and structure of the stream buffers,\n     * while dataSpace defines the meaning of the data within the buffer.\n     *\n     * For most formats, dataSpace defines the color space of the image data.\n     * In addition, for some formats, dataSpace indicates whether image- or\n     * depth-based data is requested.  See system/core/include/system/graphics.h\n     * for details of formats and valid dataSpace values for each format.\n     *\n     * Version information:\n     *\n     * < CAMERA_DEVICE_API_VERSION_3_3:\n     *\n     *   Not defined and should not be accessed. dataSpace should be assumed to\n     *   be HAL_DATASPACE_UNKNOWN, and the appropriate color space, etc, should\n     *   be determined from the usage flags and the format.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_3:\n     *\n     *   Always set by the camera service. HAL must use this dataSpace to\n     *   configure the stream to the correct colorspace, or to select between\n     *   color and depth outputs if supported.\n     */\n    android_dataspace_t data_space;\n\n    /**\n     * The required output rotation of the stream, one of\n     * the camera3_stream_rotation_t values. This must be inspected by HAL along\n     * with stream width and height. For example, if the rotation is 90 degree\n     * and the stream width and height is 720 and 1280 respectively, camera service\n     * will supply buffers of size 720x1280, and HAL should capture a 1280x720 image\n     * and rotate the image by 90 degree counterclockwise. The rotation field is\n     * no-op when the stream type is input. Camera HAL must ignore the rotation\n     * field for an input stream.\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     *    Not defined and must not be accessed. HAL must not apply any rotation\n     *    on output images.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_3:\n     *\n     *    Always set by camera service. HAL must inspect this field during stream\n     *    configuration and returns -EINVAL if HAL cannot perform such rotation.\n     *    HAL must always support CAMERA3_STREAM_ROTATION_0, so a\n     *    configure_streams() call must not fail for unsupported rotation if\n     *    rotation field of all streams is CAMERA3_STREAM_ROTATION_0.\n     *\n     */\n    int rotation;\n\n    /* reserved for future use */\n    void *reserved[7];\n\n} camera3_stream_t;\n\n/**\n * camera3_stream_configuration_t:\n *\n * A structure of stream definitions, used by configure_streams(). This\n * structure defines all the output streams and the reprocessing input\n * stream for the current camera use case.\n */\ntypedef struct camera3_stream_configuration {\n    /**\n     * The total number of streams requested by the framework.  This includes\n     * both input and output streams. The number of streams will be at least 1,\n     * and there will be at least one output-capable stream.\n     */\n    uint32_t num_streams;\n\n    /**\n     * An array of camera stream pointers, defining the input/output\n     * configuration for the camera HAL device.\n     *\n     * At most one input-capable stream may be defined (INPUT or BIDIRECTIONAL)\n     * in a single configuration.\n     *\n     * At least one output-capable stream must be defined (OUTPUT or\n     * BIDIRECTIONAL).\n     */\n    camera3_stream_t **streams;\n\n    /**\n     * >= CAMERA_DEVICE_API_VERSION_3_3:\n     *\n     * The operation mode of streams in this configuration, one of the value defined in\n     * camera3_stream_configuration_mode_t.\n     * The HAL can use this mode as an indicator to set the stream property (e.g.,\n     * camera3_stream->max_buffers) appropriately. For example, if the configuration is\n     * CAMERA3_STREAM_CONFIGURATION_CONSTRAINED_HIGH_SPEED_MODE, the HAL may want to set aside more\n     * buffers for batch mode operation (see android.control.availableHighSpeedVideoConfigurations\n     * for batch mode definition).\n     *\n     */\n    uint32_t operation_mode;\n} camera3_stream_configuration_t;\n\n/**\n * camera3_buffer_status_t:\n *\n * The current status of a single stream buffer.\n */\ntypedef enum camera3_buffer_status {\n    /**\n     * The buffer is in a normal state, and can be used after waiting on its\n     * sync fence.\n     */\n    CAMERA3_BUFFER_STATUS_OK = 0,\n\n    /**\n     * The buffer does not contain valid data, and the data in it should not be\n     * used. The sync fence must still be waited on before reusing the buffer.\n     */\n    CAMERA3_BUFFER_STATUS_ERROR = 1\n\n} camera3_buffer_status_t;\n\n/**\n * camera3_stream_buffer_t:\n *\n * A single buffer from a camera3 stream. It includes a handle to its parent\n * stream, the handle to the gralloc buffer itself, and sync fences\n *\n * The buffer does not specify whether it is to be used for input or output;\n * that is determined by its parent stream type and how the buffer is passed to\n * the HAL device.\n */\ntypedef struct camera3_stream_buffer {\n    /**\n     * The handle of the stream this buffer is associated with\n     */\n    camera3_stream_t *stream;\n\n    /**\n     * The native handle to the buffer\n     */\n    buffer_handle_t *buffer;\n\n    /**\n     * Current state of the buffer, one of the camera3_buffer_status_t\n     * values. The framework will not pass buffers to the HAL that are in an\n     * error state. In case a buffer could not be filled by the HAL, it must\n     * have its status set to CAMERA3_BUFFER_STATUS_ERROR when returned to the\n     * framework with process_capture_result().\n     */\n    int status;\n\n    /**\n     * The acquire sync fence for this buffer. The HAL must wait on this fence\n     * fd before attempting to read from or write to this buffer.\n     *\n     * The framework may be set to -1 to indicate that no waiting is necessary\n     * for this buffer.\n     *\n     * When the HAL returns an output buffer to the framework with\n     * process_capture_result(), the acquire_fence must be set to -1. If the HAL\n     * never waits on the acquire_fence due to an error in filling a buffer,\n     * when calling process_capture_result() the HAL must set the release_fence\n     * of the buffer to be the acquire_fence passed to it by the framework. This\n     * will allow the framework to wait on the fence before reusing the buffer.\n     *\n     * For input buffers, the HAL must not change the acquire_fence field during\n     * the process_capture_request() call.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * When the HAL returns an input buffer to the framework with\n     * process_capture_result(), the acquire_fence must be set to -1. If the HAL\n     * never waits on input buffer acquire fence due to an error, the sync\n     * fences should be handled similarly to the way they are handled for output\n     * buffers.\n     */\n     int acquire_fence;\n\n    /**\n     * The release sync fence for this buffer. The HAL must set this fence when\n     * returning buffers to the framework, or write -1 to indicate that no\n     * waiting is required for this buffer.\n     *\n     * For the output buffers, the fences must be set in the output_buffers\n     * array passed to process_capture_result().\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     * For the input buffer, the release fence must be set by the\n     * process_capture_request() call.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * For the input buffer, the fences must be set in the input_buffer\n     * passed to process_capture_result().\n     *\n     * After signaling the release_fence for this buffer, the HAL\n     * should not make any further attempts to access this buffer as the\n     * ownership has been fully transferred back to the framework.\n     *\n     * If a fence of -1 was specified then the ownership of this buffer\n     * is transferred back immediately upon the call of process_capture_result.\n     */\n    int release_fence;\n\n} camera3_stream_buffer_t;\n\n/**\n * camera3_stream_buffer_set_t:\n *\n * The complete set of gralloc buffers for a stream. This structure is given to\n * register_stream_buffers() to allow the camera HAL device to register/map/etc\n * newly allocated stream buffers.\n *\n * >= CAMERA_DEVICE_API_VERSION_3_2:\n *\n * Deprecated (and not used). In particular,\n * register_stream_buffers is also deprecated and will never be invoked.\n *\n */\ntypedef struct camera3_stream_buffer_set {\n    /**\n     * The stream handle for the stream these buffers belong to\n     */\n    camera3_stream_t *stream;\n\n    /**\n     * The number of buffers in this stream. It is guaranteed to be at least\n     * stream->max_buffers.\n     */\n    uint32_t num_buffers;\n\n    /**\n     * The array of gralloc buffer handles for this stream. If the stream format\n     * is set to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, the camera HAL device\n     * should inspect the passed-in buffers to determine any platform-private\n     * pixel format information.\n     */\n    buffer_handle_t **buffers;\n\n} camera3_stream_buffer_set_t;\n\n/**\n * camera3_jpeg_blob:\n *\n * Transport header for compressed JPEG buffers in output streams.\n *\n * To capture JPEG images, a stream is created using the pixel format\n * HAL_PIXEL_FORMAT_BLOB. The buffer size for the stream is calculated by the\n * framework, based on the static metadata field android.jpeg.maxSize. Since\n * compressed JPEG images are of variable size, the HAL needs to include the\n * final size of the compressed image using this structure inside the output\n * stream buffer. The JPEG blob ID field must be set to CAMERA3_JPEG_BLOB_ID.\n *\n * Transport header should be at the end of the JPEG output stream buffer. That\n * means the jpeg_blob_id must start at byte[buffer_size -\n * sizeof(camera3_jpeg_blob)], where the buffer_size is the size of gralloc buffer.\n * Any HAL using this transport header must account for it in android.jpeg.maxSize\n * The JPEG data itself starts at the beginning of the buffer and should be\n * jpeg_size bytes long.\n */\ntypedef struct camera3_jpeg_blob {\n    uint16_t jpeg_blob_id;\n    uint32_t jpeg_size;\n} camera3_jpeg_blob_t;\n\nenum {\n    CAMERA3_JPEG_BLOB_ID = 0x00FF\n};\n\n/**********************************************************************\n *\n * Message definitions for the HAL notify() callback.\n *\n * These definitions are used for the HAL notify callback, to signal\n * asynchronous events from the HAL device to the Android framework.\n *\n */\n\n/**\n * camera3_msg_type:\n *\n * Indicates the type of message sent, which specifies which member of the\n * message union is valid.\n *\n */\ntypedef enum camera3_msg_type {\n    /**\n     * An error has occurred. camera3_notify_msg.message.error contains the\n     * error information.\n     */\n    CAMERA3_MSG_ERROR = 1,\n\n    /**\n     * The exposure of a given request or processing a reprocess request has\n     * begun. camera3_notify_msg.message.shutter contains the information\n     * the capture.\n     */\n    CAMERA3_MSG_SHUTTER = 2,\n\n    /**\n     * Number of framework message types\n     */\n    CAMERA3_NUM_MESSAGES\n\n} camera3_msg_type_t;\n\n/**\n * Defined error codes for CAMERA_MSG_ERROR\n */\ntypedef enum camera3_error_msg_code {\n    /**\n     * A serious failure occured. No further frames or buffer streams will\n     * be produced by the device. Device should be treated as closed. The\n     * client must reopen the device to use it again. The frame_number field\n     * is unused.\n     */\n    CAMERA3_MSG_ERROR_DEVICE = 1,\n\n    /**\n     * An error has occurred in processing a request. No output (metadata or\n     * buffers) will be produced for this request. The frame_number field\n     * specifies which request has been dropped. Subsequent requests are\n     * unaffected, and the device remains operational.\n     */\n    CAMERA3_MSG_ERROR_REQUEST = 2,\n\n    /**\n     * An error has occurred in producing an output result metadata buffer\n     * for a request, but output stream buffers for it will still be\n     * available. Subsequent requests are unaffected, and the device remains\n     * operational.  The frame_number field specifies the request for which\n     * result metadata won't be available.\n     */\n    CAMERA3_MSG_ERROR_RESULT = 3,\n\n    /**\n     * An error has occurred in placing an output buffer into a stream for a\n     * request. The frame metadata and other buffers may still be\n     * available. Subsequent requests are unaffected, and the device remains\n     * operational. The frame_number field specifies the request for which the\n     * buffer was dropped, and error_stream contains a pointer to the stream\n     * that dropped the frame.u\n     */\n    CAMERA3_MSG_ERROR_BUFFER = 4,\n\n    /**\n     * Number of error types\n     */\n    CAMERA3_MSG_NUM_ERRORS\n\n} camera3_error_msg_code_t;\n\n/**\n * camera3_error_msg_t:\n *\n * Message contents for CAMERA3_MSG_ERROR\n */\ntypedef struct camera3_error_msg {\n    /**\n     * Frame number of the request the error applies to. 0 if the frame number\n     * isn't applicable to the error.\n     */\n    uint32_t frame_number;\n\n    /**\n     * Pointer to the stream that had a failure. NULL if the stream isn't\n     * applicable to the error.\n     */\n    camera3_stream_t *error_stream;\n\n    /**\n     * The code for this error; one of the CAMERA_MSG_ERROR enum values.\n     */\n    int error_code;\n\n} camera3_error_msg_t;\n\n/**\n * camera3_shutter_msg_t:\n *\n * Message contents for CAMERA3_MSG_SHUTTER\n */\ntypedef struct camera3_shutter_msg {\n    /**\n     * Frame number of the request that has begun exposure or reprocessing.\n     */\n    uint32_t frame_number;\n\n    /**\n     * Timestamp for the start of capture. For a reprocess request, this must\n     * be input image's start of capture. This must match the capture result\n     * metadata's sensor exposure start timestamp.\n     */\n    uint64_t timestamp;\n\n} camera3_shutter_msg_t;\n\n/**\n * camera3_notify_msg_t:\n *\n * The message structure sent to camera3_callback_ops_t.notify()\n */\ntypedef struct camera3_notify_msg {\n\n    /**\n     * The message type. One of camera3_notify_msg_type, or a private extension.\n     */\n    int type;\n\n    union {\n        /**\n         * Error message contents. Valid if type is CAMERA3_MSG_ERROR\n         */\n        camera3_error_msg_t error;\n\n        /**\n         * Shutter message contents. Valid if type is CAMERA3_MSG_SHUTTER\n         */\n        camera3_shutter_msg_t shutter;\n\n        /**\n         * Generic message contents. Used to ensure a minimum size for custom\n         * message types.\n         */\n        uint8_t generic[32];\n    } message;\n\n} camera3_notify_msg_t;\n\n/**********************************************************************\n *\n * Capture request/result definitions for the HAL process_capture_request()\n * method, and the process_capture_result() callback.\n *\n */\n\n/**\n * camera3_request_template_t:\n *\n * Available template types for\n * camera3_device_ops.construct_default_request_settings()\n */\ntypedef enum camera3_request_template {\n    /**\n     * Standard camera preview operation with 3A on auto.\n     */\n    CAMERA3_TEMPLATE_PREVIEW = 1,\n\n    /**\n     * Standard camera high-quality still capture with 3A and flash on auto.\n     */\n    CAMERA3_TEMPLATE_STILL_CAPTURE = 2,\n\n    /**\n     * Standard video recording plus preview with 3A on auto, torch off.\n     */\n    CAMERA3_TEMPLATE_VIDEO_RECORD = 3,\n\n    /**\n     * High-quality still capture while recording video. Application will\n     * include preview, video record, and full-resolution YUV or JPEG streams in\n     * request. Must not cause stuttering on video stream. 3A on auto.\n     */\n    CAMERA3_TEMPLATE_VIDEO_SNAPSHOT = 4,\n\n    /**\n     * Zero-shutter-lag mode. Application will request preview and\n     * full-resolution data for each frame, and reprocess it to JPEG when a\n     * still image is requested by user. Settings should provide highest-quality\n     * full-resolution images without compromising preview frame rate. 3A on\n     * auto.\n     */\n    CAMERA3_TEMPLATE_ZERO_SHUTTER_LAG = 5,\n\n    /**\n     * A basic template for direct application control of capture\n     * parameters. All automatic control is disabled (auto-exposure, auto-white\n     * balance, auto-focus), and post-processing parameters are set to preview\n     * quality. The manual capture parameters (exposure, sensitivity, etc.)\n     * are set to reasonable defaults, but should be overridden by the\n     * application depending on the intended use case.\n     */\n    CAMERA3_TEMPLATE_MANUAL = 6,\n\n    /* Total number of templates */\n    CAMERA3_TEMPLATE_COUNT,\n\n    /**\n     * First value for vendor-defined request templates\n     */\n    CAMERA3_VENDOR_TEMPLATE_START = 0x40000000\n\n} camera3_request_template_t;\n\n/**\n * camera3_capture_request_t:\n *\n * A single request for image capture/buffer reprocessing, sent to the Camera\n * HAL device by the framework in process_capture_request().\n *\n * The request contains the settings to be used for this capture, and the set of\n * output buffers to write the resulting image data in. It may optionally\n * contain an input buffer, in which case the request is for reprocessing that\n * input buffer instead of capturing a new image with the camera sensor. The\n * capture is identified by the frame_number.\n *\n * In response, the camera HAL device must send a camera3_capture_result\n * structure asynchronously to the framework, using the process_capture_result()\n * callback.\n */\ntypedef struct camera3_capture_request {\n    /**\n     * The frame number is an incrementing integer set by the framework to\n     * uniquely identify this capture. It needs to be returned in the result\n     * call, and is also used to identify the request in asynchronous\n     * notifications sent to camera3_callback_ops_t.notify().\n     */\n    uint32_t frame_number;\n\n    /**\n     * The settings buffer contains the capture and processing parameters for\n     * the request. As a special case, a NULL settings buffer indicates that the\n     * settings are identical to the most-recently submitted capture request. A\n     * NULL buffer cannot be used as the first submitted request after a\n     * configure_streams() call.\n     */\n    const camera_metadata_t *settings;\n\n    /**\n     * The input stream buffer to use for this request, if any.\n     *\n     * If input_buffer is NULL, then the request is for a new capture from the\n     * imager. If input_buffer is valid, the request is for reprocessing the\n     * image contained in input_buffer.\n     *\n     * In the latter case, the HAL must set the release_fence of the\n     * input_buffer to a valid sync fence, or to -1 if the HAL does not support\n     * sync, before process_capture_request() returns.\n     *\n     * The HAL is required to wait on the acquire sync fence of the input buffer\n     * before accessing it.\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     * Any input buffer included here will have been registered with the HAL\n     * through register_stream_buffers() before its inclusion in a request.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * The buffers will not have been pre-registered with the HAL.\n     * Subsequent requests may reuse buffers, or provide entirely new buffers.\n     */\n    camera3_stream_buffer_t *input_buffer;\n\n    /**\n     * The number of output buffers for this capture request. Must be at least\n     * 1.\n     */\n    uint32_t num_output_buffers;\n\n    /**\n     * An array of num_output_buffers stream buffers, to be filled with image\n     * data from this capture/reprocess. The HAL must wait on the acquire fences\n     * of each stream buffer before writing to them.\n     *\n     * The HAL takes ownership of the actual buffer_handle_t entries in\n     * output_buffers; the framework does not access them until they are\n     * returned in a camera3_capture_result_t.\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     * All the buffers included  here will have been registered with the HAL\n     * through register_stream_buffers() before their inclusion in a request.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * Any or all of the buffers included here may be brand new in this\n     * request (having never before seen by the HAL).\n     */\n    const camera3_stream_buffer_t *output_buffers;\n\n} camera3_capture_request_t;\n\n/**\n * camera3_capture_result_t:\n *\n * The result of a single capture/reprocess by the camera HAL device. This is\n * sent to the framework asynchronously with process_capture_result(), in\n * response to a single capture request sent to the HAL with\n * process_capture_request(). Multiple process_capture_result() calls may be\n * performed by the HAL for each request.\n *\n * Each call, all with the same frame\n * number, may contain some subset of the output buffers, and/or the result\n * metadata. The metadata may only be provided once for a given frame number;\n * all other calls must set the result metadata to NULL.\n *\n * The result structure contains the output metadata from this capture, and the\n * set of output buffers that have been/will be filled for this capture. Each\n * output buffer may come with a release sync fence that the framework will wait\n * on before reading, in case the buffer has not yet been filled by the HAL.\n *\n * >= CAMERA_DEVICE_API_VERSION_3_2:\n *\n * The metadata may be provided multiple times for a single frame number. The\n * framework will accumulate together the final result set by combining each\n * partial result together into the total result set.\n *\n * If an input buffer is given in a request, the HAL must return it in one of\n * the process_capture_result calls, and the call may be to just return the input\n * buffer, without metadata and output buffers; the sync fences must be handled\n * the same way they are done for output buffers.\n *\n *\n * Performance considerations:\n *\n * Applications will also receive these partial results immediately, so sending\n * partial results is a highly recommended performance optimization to avoid\n * the total pipeline latency before sending the results for what is known very\n * early on in the pipeline.\n *\n * A typical use case might be calculating the AF state halfway through the\n * pipeline; by sending the state back to the framework immediately, we get a\n * 50% performance increase and perceived responsiveness of the auto-focus.\n *\n */\ntypedef struct camera3_capture_result {\n    /**\n     * The frame number is an incrementing integer set by the framework in the\n     * submitted request to uniquely identify this capture. It is also used to\n     * identify the request in asynchronous notifications sent to\n     * camera3_callback_ops_t.notify().\n    */\n    uint32_t frame_number;\n\n    /**\n     * The result metadata for this capture. This contains information about the\n     * final capture parameters, the state of the capture and post-processing\n     * hardware, the state of the 3A algorithms, if enabled, and the output of\n     * any enabled statistics units.\n     *\n     * Only one call to process_capture_result() with a given frame_number may\n     * include the result metadata. All other calls for the same frame_number\n     * must set this to NULL.\n     *\n     * If there was an error producing the result metadata, result must be an\n     * empty metadata buffer, and notify() must be called with ERROR_RESULT.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * Multiple calls to process_capture_result() with a given frame_number\n     * may include the result metadata.\n     *\n     * Partial metadata submitted should not include any metadata key returned\n     * in a previous partial result for a given frame. Each new partial result\n     * for that frame must also set a distinct partial_result value.\n     *\n     * If notify has been called with ERROR_RESULT, all further partial\n     * results for that frame are ignored by the framework.\n     */\n    const camera_metadata_t *result;\n\n    /**\n     * The number of output buffers returned in this result structure. Must be\n     * less than or equal to the matching capture request's count. If this is\n     * less than the buffer count in the capture request, at least one more call\n     * to process_capture_result with the same frame_number must be made, to\n     * return the remaining output buffers to the framework. This may only be\n     * zero if the structure includes valid result metadata or an input buffer\n     * is returned in this result.\n     */\n    uint32_t num_output_buffers;\n\n    /**\n     * The handles for the output stream buffers for this capture. They may not\n     * yet be filled at the time the HAL calls process_capture_result(); the\n     * framework will wait on the release sync fences provided by the HAL before\n     * reading the buffers.\n     *\n     * The HAL must set the stream buffer's release sync fence to a valid sync\n     * fd, or to -1 if the buffer has already been filled.\n     *\n     * If the HAL encounters an error while processing the buffer, and the\n     * buffer is not filled, the buffer's status field must be set to\n     * CAMERA3_BUFFER_STATUS_ERROR. If the HAL did not wait on the acquire fence\n     * before encountering the error, the acquire fence should be copied into\n     * the release fence, to allow the framework to wait on the fence before\n     * reusing the buffer.\n     *\n     * The acquire fence must be set to -1 for all output buffers.  If\n     * num_output_buffers is zero, this may be NULL. In that case, at least one\n     * more process_capture_result call must be made by the HAL to provide the\n     * output buffers.\n     *\n     * When process_capture_result is called with a new buffer for a frame,\n     * all previous frames' buffers for that corresponding stream must have been\n     * already delivered (the fences need not have yet been signaled).\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * Gralloc buffers for a frame may be sent to framework before the\n     * corresponding SHUTTER-notify.\n     *\n     * Performance considerations:\n     *\n     * Buffers delivered to the framework will not be dispatched to the\n     * application layer until a start of exposure timestamp has been received\n     * via a SHUTTER notify() call. It is highly recommended to\n     * dispatch that call as early as possible.\n     */\n     const camera3_stream_buffer_t *output_buffers;\n\n     /**\n      * >= CAMERA_DEVICE_API_VERSION_3_2:\n      *\n      * The handle for the input stream buffer for this capture. It may not\n      * yet be consumed at the time the HAL calls process_capture_result(); the\n      * framework will wait on the release sync fences provided by the HAL before\n      * reusing the buffer.\n      *\n      * The HAL should handle the sync fences the same way they are done for\n      * output_buffers.\n      *\n      * Only one input buffer is allowed to be sent per request. Similarly to\n      * output buffers, the ordering of returned input buffers must be\n      * maintained by the HAL.\n      *\n      * Performance considerations:\n      *\n      * The input buffer should be returned as early as possible. If the HAL\n      * supports sync fences, it can call process_capture_result to hand it back\n      * with sync fences being set appropriately. If the sync fences are not\n      * supported, the buffer can only be returned when it is consumed, which\n      * may take long time; the HAL may choose to copy this input buffer to make\n      * the buffer return sooner.\n      */\n      const camera3_stream_buffer_t *input_buffer;\n\n     /**\n      * >= CAMERA_DEVICE_API_VERSION_3_2:\n      *\n      * In order to take advantage of partial results, the HAL must set the\n      * static metadata android.request.partialResultCount to the number of\n      * partial results it will send for each frame.\n      *\n      * Each new capture result with a partial result must set\n      * this field (partial_result) to a distinct inclusive value between\n      * 1 and android.request.partialResultCount.\n      *\n      * HALs not wishing to take advantage of this feature must not\n      * set an android.request.partialResultCount or partial_result to a value\n      * other than 1.\n      *\n      * This value must be set to 0 when a capture result contains buffers only\n      * and no metadata.\n      */\n     uint32_t partial_result;\n\n} camera3_capture_result_t;\n\n/**********************************************************************\n *\n * Callback methods for the HAL to call into the framework.\n *\n * These methods are used to return metadata and image buffers for a completed\n * or failed captures, and to notify the framework of asynchronous events such\n * as errors.\n *\n * The framework will not call back into the HAL from within these callbacks,\n * and these calls will not block for extended periods.\n *\n */\ntypedef struct camera3_callback_ops {\n\n    /**\n     * process_capture_result:\n     *\n     * Send results from a completed capture to the framework.\n     * process_capture_result() may be invoked multiple times by the HAL in\n     * response to a single capture request. This allows, for example, the\n     * metadata and low-resolution buffers to be returned in one call, and\n     * post-processed JPEG buffers in a later call, once it is available. Each\n     * call must include the frame number of the request it is returning\n     * metadata or buffers for.\n     *\n     * A component (buffer or metadata) of the complete result may only be\n     * included in one process_capture_result call. A buffer for each stream,\n     * and the result metadata, must be returned by the HAL for each request in\n     * one of the process_capture_result calls, even in case of errors producing\n     * some of the output. A call to process_capture_result() with neither\n     * output buffers or result metadata is not allowed.\n     *\n     * The order of returning metadata and buffers for a single result does not\n     * matter, but buffers for a given stream must be returned in FIFO order. So\n     * the buffer for request 5 for stream A must always be returned before the\n     * buffer for request 6 for stream A. This also applies to the result\n     * metadata; the metadata for request 5 must be returned before the metadata\n     * for request 6.\n     *\n     * However, different streams are independent of each other, so it is\n     * acceptable and expected that the buffer for request 5 for stream A may be\n     * returned after the buffer for request 6 for stream B is. And it is\n     * acceptable that the result metadata for request 6 for stream B is\n     * returned before the buffer for request 5 for stream A is.\n     *\n     * The HAL retains ownership of result structure, which only needs to be\n     * valid to access during this call. The framework will copy whatever it\n     * needs before this call returns.\n     *\n     * The output buffers do not need to be filled yet; the framework will wait\n     * on the stream buffer release sync fence before reading the buffer\n     * data. Therefore, this method should be called by the HAL as soon as\n     * possible, even if some or all of the output buffers are still in\n     * being filled. The HAL must include valid release sync fences into each\n     * output_buffers stream buffer entry, or -1 if that stream buffer is\n     * already filled.\n     *\n     * If the result buffer cannot be constructed for a request, the HAL should\n     * return an empty metadata buffer, but still provide the output buffers and\n     * their sync fences. In addition, notify() must be called with an\n     * ERROR_RESULT message.\n     *\n     * If an output buffer cannot be filled, its status field must be set to\n     * STATUS_ERROR. In addition, notify() must be called with a ERROR_BUFFER\n     * message.\n     *\n     * If the entire capture has failed, then this method still needs to be\n     * called to return the output buffers to the framework. All the buffer\n     * statuses should be STATUS_ERROR, and the result metadata should be an\n     * empty buffer. In addition, notify() must be called with a ERROR_REQUEST\n     * message. In this case, individual ERROR_RESULT/ERROR_BUFFER messages\n     * should not be sent.\n     *\n     * Performance requirements:\n     *\n     * This is a non-blocking call. The framework will return this call in 5ms.\n     *\n     * The pipeline latency (see S7 for definition) should be less than or equal to\n     * 4 frame intervals, and must be less than or equal to 8 frame intervals.\n     *\n     */\n    void (*process_capture_result)(const struct camera3_callback_ops *,\n            const camera3_capture_result_t *result);\n\n    /**\n     * notify:\n     *\n     * Asynchronous notification callback from the HAL, fired for various\n     * reasons. Only for information independent of frame capture, or that\n     * require specific timing. The ownership of the message structure remains\n     * with the HAL, and the msg only needs to be valid for the duration of this\n     * call.\n     *\n     * Multiple threads may call notify() simultaneously.\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     * The notification for the start of exposure for a given request must be\n     * sent by the HAL before the first call to process_capture_result() for\n     * that request is made.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * Buffers delivered to the framework will not be dispatched to the\n     * application layer until a start of exposure timestamp (or input image's\n     * start of exposure timestamp for a reprocess request) has been received\n     * via a SHUTTER notify() call. It is highly recommended to dispatch this\n     * call as early as possible.\n     *\n     * ------------------------------------------------------------------------\n     * Performance requirements:\n     *\n     * This is a non-blocking call. The framework will return this call in 5ms.\n     */\n    void (*notify)(const struct camera3_callback_ops *,\n            const camera3_notify_msg_t *msg);\n\n} camera3_callback_ops_t;\n\n/**********************************************************************\n *\n * Camera device operations\n *\n */\ntypedef struct camera3_device_ops {\n\n    /**\n     * initialize:\n     *\n     * One-time initialization to pass framework callback function pointers to\n     * the HAL. Will be called once after a successful open() call, before any\n     * other functions are called on the camera3_device_ops structure.\n     *\n     * Performance requirements:\n     *\n     * This should be a non-blocking call. The HAL should return from this call\n     * in 5ms, and must return from this call in 10ms.\n     *\n     * Return values:\n     *\n     *  0:     On successful initialization\n     *\n     * -ENODEV: If initialization fails. Only close() can be called successfully\n     *          by the framework after this.\n     */\n    int (*initialize)(const struct camera3_device *,\n            const camera3_callback_ops_t *callback_ops);\n\n    /**********************************************************************\n     * Stream management\n     */\n\n    /**\n     * configure_streams:\n     *\n     * CAMERA_DEVICE_API_VERSION_3_0 only:\n     *\n     * Reset the HAL camera device processing pipeline and set up new input and\n     * output streams. This call replaces any existing stream configuration with\n     * the streams defined in the stream_list. This method will be called at\n     * least once after initialize() before a request is submitted with\n     * process_capture_request().\n     *\n     * The stream_list must contain at least one output-capable stream, and may\n     * not contain more than one input-capable stream.\n     *\n     * The stream_list may contain streams that are also in the currently-active\n     * set of streams (from the previous call to configure_stream()). These\n     * streams will already have valid values for usage, max_buffers, and the\n     * private pointer.\n     *\n     * If such a stream has already had its buffers registered,\n     * register_stream_buffers() will not be called again for the stream, and\n     * buffers from the stream can be immediately included in input requests.\n     *\n     * If the HAL needs to change the stream configuration for an existing\n     * stream due to the new configuration, it may rewrite the values of usage\n     * and/or max_buffers during the configure call.\n     *\n     * The framework will detect such a change, and will then reallocate the\n     * stream buffers, and call register_stream_buffers() again before using\n     * buffers from that stream in a request.\n     *\n     * If a currently-active stream is not included in stream_list, the HAL may\n     * safely remove any references to that stream. It will not be reused in a\n     * later configure() call by the framework, and all the gralloc buffers for\n     * it will be freed after the configure_streams() call returns.\n     *\n     * The stream_list structure is owned by the framework, and may not be\n     * accessed once this call completes. The address of an individual\n     * camera3_stream_t structure will remain valid for access by the HAL until\n     * the end of the first configure_stream() call which no longer includes\n     * that camera3_stream_t in the stream_list argument. The HAL may not change\n     * values in the stream structure outside of the private pointer, except for\n     * the usage and max_buffers members during the configure_streams() call\n     * itself.\n     *\n     * If the stream is new, the usage, max_buffer, and private pointer fields\n     * of the stream structure will all be set to 0. The HAL device must set\n     * these fields before the configure_streams() call returns. These fields\n     * are then used by the framework and the platform gralloc module to\n     * allocate the gralloc buffers for each stream.\n     *\n     * Before such a new stream can have its buffers included in a capture\n     * request, the framework will call register_stream_buffers() with that\n     * stream. However, the framework is not required to register buffers for\n     * _all_ streams before submitting a request. This allows for quick startup\n     * of (for example) a preview stream, with allocation for other streams\n     * happening later or concurrently.\n     *\n     * ------------------------------------------------------------------------\n     * CAMERA_DEVICE_API_VERSION_3_1 only:\n     *\n     * Reset the HAL camera device processing pipeline and set up new input and\n     * output streams. This call replaces any existing stream configuration with\n     * the streams defined in the stream_list. This method will be called at\n     * least once after initialize() before a request is submitted with\n     * process_capture_request().\n     *\n     * The stream_list must contain at least one output-capable stream, and may\n     * not contain more than one input-capable stream.\n     *\n     * The stream_list may contain streams that are also in the currently-active\n     * set of streams (from the previous call to configure_stream()). These\n     * streams will already have valid values for usage, max_buffers, and the\n     * private pointer.\n     *\n     * If such a stream has already had its buffers registered,\n     * register_stream_buffers() will not be called again for the stream, and\n     * buffers from the stream can be immediately included in input requests.\n     *\n     * If the HAL needs to change the stream configuration for an existing\n     * stream due to the new configuration, it may rewrite the values of usage\n     * and/or max_buffers during the configure call.\n     *\n     * The framework will detect such a change, and will then reallocate the\n     * stream buffers, and call register_stream_buffers() again before using\n     * buffers from that stream in a request.\n     *\n     * If a currently-active stream is not included in stream_list, the HAL may\n     * safely remove any references to that stream. It will not be reused in a\n     * later configure() call by the framework, and all the gralloc buffers for\n     * it will be freed after the configure_streams() call returns.\n     *\n     * The stream_list structure is owned by the framework, and may not be\n     * accessed once this call completes. The address of an individual\n     * camera3_stream_t structure will remain valid for access by the HAL until\n     * the end of the first configure_stream() call which no longer includes\n     * that camera3_stream_t in the stream_list argument. The HAL may not change\n     * values in the stream structure outside of the private pointer, except for\n     * the usage and max_buffers members during the configure_streams() call\n     * itself.\n     *\n     * If the stream is new, max_buffer, and private pointer fields of the\n     * stream structure will all be set to 0. The usage will be set to the\n     * consumer usage flags. The HAL device must set these fields before the\n     * configure_streams() call returns. These fields are then used by the\n     * framework and the platform gralloc module to allocate the gralloc\n     * buffers for each stream.\n     *\n     * Before such a new stream can have its buffers included in a capture\n     * request, the framework will call register_stream_buffers() with that\n     * stream. However, the framework is not required to register buffers for\n     * _all_ streams before submitting a request. This allows for quick startup\n     * of (for example) a preview stream, with allocation for other streams\n     * happening later or concurrently.\n     *\n     * ------------------------------------------------------------------------\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * Reset the HAL camera device processing pipeline and set up new input and\n     * output streams. This call replaces any existing stream configuration with\n     * the streams defined in the stream_list. This method will be called at\n     * least once after initialize() before a request is submitted with\n     * process_capture_request().\n     *\n     * The stream_list must contain at least one output-capable stream, and may\n     * not contain more than one input-capable stream.\n     *\n     * The stream_list may contain streams that are also in the currently-active\n     * set of streams (from the previous call to configure_stream()). These\n     * streams will already have valid values for usage, max_buffers, and the\n     * private pointer.\n     *\n     * If the HAL needs to change the stream configuration for an existing\n     * stream due to the new configuration, it may rewrite the values of usage\n     * and/or max_buffers during the configure call.\n     *\n     * The framework will detect such a change, and may then reallocate the\n     * stream buffers before using buffers from that stream in a request.\n     *\n     * If a currently-active stream is not included in stream_list, the HAL may\n     * safely remove any references to that stream. It will not be reused in a\n     * later configure() call by the framework, and all the gralloc buffers for\n     * it will be freed after the configure_streams() call returns.\n     *\n     * The stream_list structure is owned by the framework, and may not be\n     * accessed once this call completes. The address of an individual\n     * camera3_stream_t structure will remain valid for access by the HAL until\n     * the end of the first configure_stream() call which no longer includes\n     * that camera3_stream_t in the stream_list argument. The HAL may not change\n     * values in the stream structure outside of the private pointer, except for\n     * the usage and max_buffers members during the configure_streams() call\n     * itself.\n     *\n     * If the stream is new, max_buffer, and private pointer fields of the\n     * stream structure will all be set to 0. The usage will be set to the\n     * consumer usage flags. The HAL device must set these fields before the\n     * configure_streams() call returns. These fields are then used by the\n     * framework and the platform gralloc module to allocate the gralloc\n     * buffers for each stream.\n     *\n     * Newly allocated buffers may be included in a capture request at any time\n     * by the framework. Once a gralloc buffer is returned to the framework\n     * with process_capture_result (and its respective release_fence has been\n     * signaled) the framework may free or reuse it at any time.\n     *\n     * ------------------------------------------------------------------------\n     *\n     * Preconditions:\n     *\n     * The framework will only call this method when no captures are being\n     * processed. That is, all results have been returned to the framework, and\n     * all in-flight input and output buffers have been returned and their\n     * release sync fences have been signaled by the HAL. The framework will not\n     * submit new requests for capture while the configure_streams() call is\n     * underway.\n     *\n     * Postconditions:\n     *\n     * The HAL device must configure itself to provide maximum possible output\n     * frame rate given the sizes and formats of the output streams, as\n     * documented in the camera device's static metadata.\n     *\n     * Performance requirements:\n     *\n     * This call is expected to be heavyweight and possibly take several hundred\n     * milliseconds to complete, since it may require resetting and\n     * reconfiguring the image sensor and the camera processing pipeline.\n     * Nevertheless, the HAL device should attempt to minimize the\n     * reconfiguration delay to minimize the user-visible pauses during\n     * application operational mode changes (such as switching from still\n     * capture to video recording).\n     *\n     * The HAL should return from this call in 500ms, and must return from this\n     * call in 1000ms.\n     *\n     * Return values:\n     *\n     *  0:      On successful stream configuration\n     *\n     * -EINVAL: If the requested stream configuration is invalid. Some examples\n     *          of invalid stream configurations include:\n     *\n     *          - Including more than 1 input-capable stream (INPUT or\n     *            BIDIRECTIONAL)\n     *\n     *          - Not including any output-capable streams (OUTPUT or\n     *            BIDIRECTIONAL)\n     *\n     *          - Including streams with unsupported formats, or an unsupported\n     *            size for that format.\n     *\n     *          - Including too many output streams of a certain format.\n     *\n     *          - Unsupported rotation configuration (only applies to\n     *            devices with version >= CAMERA_DEVICE_API_VERSION_3_3)\n     *\n     *          - Stream sizes/formats don't satisfy the\n     *            camera3_stream_configuration_t->operation_mode requirements for non-NORMAL mode,\n     *            or the requested operation_mode is not supported by the HAL.\n     *            (only applies to devices with version >= CAMERA_DEVICE_API_VERSION_3_3)\n     *\n     *          Note that the framework submitting an invalid stream\n     *          configuration is not normal operation, since stream\n     *          configurations are checked before configure. An invalid\n     *          configuration means that a bug exists in the framework code, or\n     *          there is a mismatch between the HAL's static metadata and the\n     *          requirements on streams.\n     *\n     * -ENODEV: If there has been a fatal error and the device is no longer\n     *          operational. Only close() can be called successfully by the\n     *          framework after this error is returned.\n     */\n    int (*configure_streams)(const struct camera3_device *,\n            camera3_stream_configuration_t *stream_list);\n\n    /**\n     * register_stream_buffers:\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * DEPRECATED. This will not be called and must be set to NULL.\n     *\n     * <= CAMERA_DEVICE_API_VERSION_3_1:\n     *\n     * Register buffers for a given stream with the HAL device. This method is\n     * called by the framework after a new stream is defined by\n     * configure_streams, and before buffers from that stream are included in a\n     * capture request. If the same stream is listed in a subsequent\n     * configure_streams() call, register_stream_buffers will _not_ be called\n     * again for that stream.\n     *\n     * The framework does not need to register buffers for all configured\n     * streams before it submits the first capture request. This allows quick\n     * startup for preview (or similar use cases) while other streams are still\n     * being allocated.\n     *\n     * This method is intended to allow the HAL device to map or otherwise\n     * prepare the buffers for later use. The buffers passed in will already be\n     * locked for use. At the end of the call, all the buffers must be ready to\n     * be returned to the stream.  The buffer_set argument is only valid for the\n     * duration of this call.\n     *\n     * If the stream format was set to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED,\n     * the camera HAL should inspect the passed-in buffers here to determine any\n     * platform-private pixel format information.\n     *\n     * Performance requirements:\n     *\n     * This should be a non-blocking call. The HAL should return from this call\n     * in 1ms, and must return from this call in 5ms.\n     *\n     * Return values:\n     *\n     *  0:      On successful registration of the new stream buffers\n     *\n     * -EINVAL: If the stream_buffer_set does not refer to a valid active\n     *          stream, or if the buffers array is invalid.\n     *\n     * -ENOMEM: If there was a failure in registering the buffers. The framework\n     *          must consider all the stream buffers to be unregistered, and can\n     *          try to register again later.\n     *\n     * -ENODEV: If there is a fatal error, and the device is no longer\n     *          operational. Only close() can be called successfully by the\n     *          framework after this error is returned.\n     */\n    int (*register_stream_buffers)(const struct camera3_device *,\n            const camera3_stream_buffer_set_t *buffer_set);\n\n    /**********************************************************************\n     * Request creation and submission\n     */\n\n    /**\n     * construct_default_request_settings:\n     *\n     * Create capture settings for standard camera use cases.\n     *\n     * The device must return a settings buffer that is configured to meet the\n     * requested use case, which must be one of the CAMERA3_TEMPLATE_*\n     * enums. All request control fields must be included.\n     *\n     * The HAL retains ownership of this structure, but the pointer to the\n     * structure must be valid until the device is closed. The framework and the\n     * HAL may not modify the buffer once it is returned by this call. The same\n     * buffer may be returned for subsequent calls for the same template, or for\n     * other templates.\n     *\n     * Performance requirements:\n     *\n     * This should be a non-blocking call. The HAL should return from this call\n     * in 1ms, and must return from this call in 5ms.\n     *\n     * Return values:\n     *\n     *   Valid metadata: On successful creation of a default settings\n     *                   buffer.\n     *\n     *   NULL:           In case of a fatal error. After this is returned, only\n     *                   the close() method can be called successfully by the\n     *                   framework.\n     */\n    const camera_metadata_t* (*construct_default_request_settings)(\n            const struct camera3_device *,\n            int type);\n\n    /**\n     * process_capture_request:\n     *\n     * Send a new capture request to the HAL. The HAL should not return from\n     * this call until it is ready to accept the next request to process. Only\n     * one call to process_capture_request() will be made at a time by the\n     * framework, and the calls will all be from the same thread. The next call\n     * to process_capture_request() will be made as soon as a new request and\n     * its associated buffers are available. In a normal preview scenario, this\n     * means the function will be called again by the framework almost\n     * instantly.\n     *\n     * The actual request processing is asynchronous, with the results of\n     * capture being returned by the HAL through the process_capture_result()\n     * call. This call requires the result metadata to be available, but output\n     * buffers may simply provide sync fences to wait on. Multiple requests are\n     * expected to be in flight at once, to maintain full output frame rate.\n     *\n     * The framework retains ownership of the request structure. It is only\n     * guaranteed to be valid during this call. The HAL device must make copies\n     * of the information it needs to retain for the capture processing. The HAL\n     * is responsible for waiting on and closing the buffers' fences and\n     * returning the buffer handles to the framework.\n     *\n     * The HAL must write the file descriptor for the input buffer's release\n     * sync fence into input_buffer->release_fence, if input_buffer is not\n     * NULL. If the HAL returns -1 for the input buffer release sync fence, the\n     * framework is free to immediately reuse the input buffer. Otherwise, the\n     * framework will wait on the sync fence before refilling and reusing the\n     * input buffer.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *\n     * The input/output buffers provided by the framework in each request\n     * may be brand new (having never before seen by the HAL).\n     *\n     * ------------------------------------------------------------------------\n     * Performance considerations:\n     *\n     * Handling a new buffer should be extremely lightweight and there should be\n     * no frame rate degradation or frame jitter introduced.\n     *\n     * This call must return fast enough to ensure that the requested frame\n     * rate can be sustained, especially for streaming cases (post-processing\n     * quality settings set to FAST). The HAL should return this call in 1\n     * frame interval, and must return from this call in 4 frame intervals.\n     *\n     * Return values:\n     *\n     *  0:      On a successful start to processing the capture request\n     *\n     * -EINVAL: If the input is malformed (the settings are NULL when not\n     *          allowed, there are 0 output buffers, etc) and capture processing\n     *          cannot start. Failures during request processing should be\n     *          handled by calling camera3_callback_ops_t.notify(). In case of\n     *          this error, the framework will retain responsibility for the\n     *          stream buffers' fences and the buffer handles; the HAL should\n     *          not close the fences or return these buffers with\n     *          process_capture_result.\n     *\n     * -ENODEV: If the camera device has encountered a serious error. After this\n     *          error is returned, only the close() method can be successfully\n     *          called by the framework.\n     *\n     */\n    int (*process_capture_request)(const struct camera3_device *,\n            camera3_capture_request_t *request);\n\n    /**********************************************************************\n     * Miscellaneous methods\n     */\n\n    /**\n     * get_metadata_vendor_tag_ops:\n     *\n     * Get methods to query for vendor extension metadata tag information. The\n     * HAL should fill in all the vendor tag operation methods, or leave ops\n     * unchanged if no vendor tags are defined.\n     *\n     * The definition of vendor_tag_query_ops_t can be found in\n     * system/media/camera/include/system/camera_metadata.h.\n     *\n     * >= CAMERA_DEVICE_API_VERSION_3_2:\n     *    DEPRECATED. This function has been deprecated and should be set to\n     *    NULL by the HAL.  Please implement get_vendor_tag_ops in camera_common.h\n     *    instead.\n     */\n    void (*get_metadata_vendor_tag_ops)(const struct camera3_device*,\n            vendor_tag_query_ops_t* ops);\n\n    /**\n     * dump:\n     *\n     * Print out debugging state for the camera device. This will be called by\n     * the framework when the camera service is asked for a debug dump, which\n     * happens when using the dumpsys tool, or when capturing a bugreport.\n     *\n     * The passed-in file descriptor can be used to write debugging text using\n     * dprintf() or write(). The text should be in ASCII encoding only.\n     *\n     * Performance requirements:\n     *\n     * This must be a non-blocking call. The HAL should return from this call\n     * in 1ms, must return from this call in 10ms. This call must avoid\n     * deadlocks, as it may be called at any point during camera operation.\n     * Any synchronization primitives used (such as mutex locks or semaphores)\n     * should be acquired with a timeout.\n     */\n    void (*dump)(const struct camera3_device *, int fd);\n\n    /**\n     * flush:\n     *\n     * Flush all currently in-process captures and all buffers in the pipeline\n     * on the given device. The framework will use this to dump all state as\n     * quickly as possible in order to prepare for a configure_streams() call.\n     *\n     * No buffers are required to be successfully returned, so every buffer\n     * held at the time of flush() (whether successfully filled or not) may be\n     * returned with CAMERA3_BUFFER_STATUS_ERROR. Note the HAL is still allowed\n     * to return valid (CAMERA3_BUFFER_STATUS_OK) buffers during this call,\n     * provided they are successfully filled.\n     *\n     * All requests currently in the HAL are expected to be returned as soon as\n     * possible.  Not-in-process requests should return errors immediately. Any\n     * interruptible hardware blocks should be stopped, and any uninterruptible\n     * blocks should be waited on.\n     *\n     * flush() may be called concurrently to process_capture_request(), with the expectation that\n     * process_capture_request will return quickly and the request submitted in that\n     * process_capture_request call is treated like all other in-flight requests.  Due to\n     * concurrency issues, it is possible that from the HAL's point of view, a\n     * process_capture_request() call may be started after flush has been invoked but has not\n     * returned yet. If such a call happens before flush() returns, the HAL should treat the new\n     * capture request like other in-flight pending requests (see #4 below).\n     *\n     * More specifically, the HAL must follow below requirements for various cases:\n     *\n     * 1. For captures that are too late for the HAL to cancel/stop, and will be\n     *    completed normally by the HAL; i.e. the HAL can send shutter/notify and\n     *    process_capture_result and buffers as normal.\n     *\n     * 2. For pending requests that have not done any processing, the HAL must call notify\n     *    CAMERA3_MSG_ERROR_REQUEST, and return all the output buffers with\n     *    process_capture_result in the error state (CAMERA3_BUFFER_STATUS_ERROR).\n     *    The HAL must not place the release fence into an error state, instead,\n     *    the release fences must be set to the acquire fences passed by the framework,\n     *    or -1 if they have been waited on by the HAL already. This is also the path\n     *    to follow for any captures for which the HAL already called notify() with\n     *    CAMERA3_MSG_SHUTTER but won't be producing any metadata/valid buffers for.\n     *    After CAMERA3_MSG_ERROR_REQUEST, for a given frame, only process_capture_results with\n     *    buffers in CAMERA3_BUFFER_STATUS_ERROR are allowed. No further notifys or\n     *    process_capture_result with non-null metadata is allowed.\n     *\n     * 3. For partially completed pending requests that will not have all the output\n     *    buffers or perhaps missing metadata, the HAL should follow below:\n     *\n     *    3.1. Call notify with CAMERA3_MSG_ERROR_RESULT if some of the expected result\n     *    metadata (i.e. one or more partial metadata) won't be available for the capture.\n     *\n     *    3.2. Call notify with CAMERA3_MSG_ERROR_BUFFER for every buffer that won't\n     *         be produced for the capture.\n     *\n     *    3.3  Call notify with CAMERA3_MSG_SHUTTER with the capture timestamp before\n     *         any buffers/metadata are returned with process_capture_result.\n     *\n     *    3.4 For captures that will produce some results, the HAL must not call\n     *        CAMERA3_MSG_ERROR_REQUEST, since that indicates complete failure.\n     *\n     *    3.5. Valid buffers/metadata should be passed to the framework as normal.\n     *\n     *    3.6. Failed buffers should be returned to the framework as described for case 2.\n     *         But failed buffers do not have to follow the strict ordering valid buffers do,\n     *         and may be out-of-order with respect to valid buffers. For example, if buffers\n     *         A, B, C, D, E are sent, D and E are failed, then A, E, B, D, C is an acceptable\n     *         return order.\n     *\n     *    3.7. For fully-missing metadata, calling CAMERA3_MSG_ERROR_RESULT is sufficient, no\n     *         need to call process_capture_result with NULL metadata or equivalent.\n     *\n     * 4. If a flush() is invoked while a process_capture_request() invocation is active, that\n     *    process call should return as soon as possible. In addition, if a process_capture_request()\n     *    call is made after flush() has been invoked but before flush() has returned, the\n     *    capture request provided by the late process_capture_request call should be treated like\n     *    a pending request in case #2 above.\n     *\n     * flush() should only return when there are no more outstanding buffers or\n     * requests left in the HAL. The framework may call configure_streams (as\n     * the HAL state is now quiesced) or may issue new requests.\n     *\n     * Note that it's sufficient to only support fully-succeeded and fully-failed result cases.\n     * However, it is highly desirable to support the partial failure cases as well, as it\n     * could help improve the flush call overall performance.\n     *\n     * Performance requirements:\n     *\n     * The HAL should return from this call in 100ms, and must return from this\n     * call in 1000ms. And this call must not be blocked longer than pipeline\n     * latency (see S7 for definition).\n     *\n     * Version information:\n     *\n     *   only available if device version >= CAMERA_DEVICE_API_VERSION_3_1.\n     *\n     * Return values:\n     *\n     *  0:      On a successful flush of the camera HAL.\n     *\n     * -EINVAL: If the input is malformed (the device is not valid).\n     *\n     * -ENODEV: If the camera device has encountered a serious error. After this\n     *          error is returned, only the close() method can be successfully\n     *          called by the framework.\n     */\n    int (*flush)(const struct camera3_device *);\n\n    /* reserved for future use */\n    void *reserved[8];\n} camera3_device_ops_t;\n\n/**********************************************************************\n *\n * Camera device definition\n *\n */\ntypedef struct camera3_device {\n    /**\n     * common.version must equal CAMERA_DEVICE_API_VERSION_3_0 to identify this\n     * device as implementing version 3.0 of the camera device HAL.\n     *\n     * Performance requirements:\n     *\n     * Camera open (common.module->common.methods->open) should return in 200ms, and must return\n     * in 500ms.\n     * Camera close (common.close) should return in 200ms, and must return in 500ms.\n     *\n     */\n    hw_device_t common;\n    camera3_device_ops_t *ops;\n    void *priv;\n} camera3_device_t;\n\n__END_DECLS\n\n#endif /* #ifdef ANDROID_INCLUDE_CAMERA3_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/camera_common.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n// FIXME: add well-defined names for cameras\n\n#ifndef ANDROID_INCLUDE_CAMERA_COMMON_H\n#define ANDROID_INCLUDE_CAMERA_COMMON_H\n\n#include <stdint.h>\n#include <stdbool.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <cutils/native_handle.h>\n#include <system/camera.h>\n#include <system/camera_vendor_tags.h>\n#include <hardware/hardware.h>\n#include <hardware/gralloc.h>\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define CAMERA_HARDWARE_MODULE_ID \"camera\"\n\n/**\n * Module versioning information for the Camera hardware module, based on\n * camera_module_t.common.module_api_version. The two most significant hex\n * digits represent the major version, and the two least significant represent\n * the minor version.\n *\n *******************************************************************************\n * Versions: 0.X - 1.X [CAMERA_MODULE_API_VERSION_1_0]\n *\n *   Camera modules that report these version numbers implement the initial\n *   camera module HAL interface. All camera devices openable through this\n *   module support only version 1 of the camera device HAL. The device_version\n *   and static_camera_characteristics fields of camera_info are not valid. Only\n *   the android.hardware.Camera API can be supported by this module and its\n *   devices.\n *\n *******************************************************************************\n * Version: 2.0 [CAMERA_MODULE_API_VERSION_2_0]\n *\n *   Camera modules that report this version number implement the second version\n *   of the camera module HAL interface. Camera devices openable through this\n *   module may support either version 1.0 or version 2.0 of the camera device\n *   HAL interface. The device_version field of camera_info is always valid; the\n *   static_camera_characteristics field of camera_info is valid if the\n *   device_version field is 2.0 or higher.\n *\n *******************************************************************************\n * Version: 2.1 [CAMERA_MODULE_API_VERSION_2_1]\n *\n *   This camera module version adds support for asynchronous callbacks to the\n *   framework from the camera HAL module, which is used to notify the framework\n *   about changes to the camera module state. Modules that provide a valid\n *   set_callbacks() method must report at least this version number.\n *\n *******************************************************************************\n * Version: 2.2 [CAMERA_MODULE_API_VERSION_2_2]\n *\n *   This camera module version adds vendor tag support from the module, and\n *   deprecates the old vendor_tag_query_ops that were previously only\n *   accessible with a device open.\n *\n *******************************************************************************\n * Version: 2.3 [CAMERA_MODULE_API_VERSION_2_3]\n *\n *   This camera module version adds open legacy camera HAL device support.\n *   Framework can use it to open the camera device as lower device HAL version\n *   HAL device if the same device can support multiple device API versions.\n *   The standard hardware module open call (common.methods->open) continues\n *   to open the camera device with the latest supported version, which is\n *   also the version listed in camera_info_t.device_version.\n *\n *******************************************************************************\n * Version: 2.4 [CAMERA_MODULE_API_VERSION_2_4]\n *\n * This camera module version adds below API changes:\n *\n * 1. Torch mode support. The framework can use it to turn on torch mode for\n *    any camera device that has a flash unit, without opening a camera device. The\n *    camera device has a higher priority accessing the flash unit than the camera\n *    module; opening a camera device will turn off the torch if it had been enabled\n *    through the module interface. When there are any resource conflicts, such as\n *    open() is called to open a camera device, the camera HAL module must notify the\n *    framework through the torch mode status callback that the torch mode has been\n *    turned off.\n *\n * 2. External camera (e.g. USB hot-plug camera) support. The API updates specify that\n *    the camera static info is only available when camera is connected and ready to\n *    use for external hot-plug cameras. Calls to get static info will be invalid\n *    calls when camera status is not CAMERA_DEVICE_STATUS_PRESENT. The frameworks\n *    will only count on device status change callbacks to manage the available external\n *    camera list.\n *\n * 3. Camera arbitration hints. This module version adds support for explicitly\n *    indicating the number of camera devices that can be simultaneously opened and used.\n *    To specify valid combinations of devices, the resource_cost and conflicting_devices\n *    fields should always be set in the camera_info structure returned by the\n *    get_camera_info call.\n *\n * 4. Module initialization method. This will be called by the camera service\n *    right after the HAL module is loaded, to allow for one-time initialization\n *    of the HAL. It is called before any other module methods are invoked.\n */\n\n/**\n * Predefined macros for currently-defined version numbers\n */\n\n/**\n * All module versions <= HARDWARE_MODULE_API_VERSION(1, 0xFF) must be treated\n * as CAMERA_MODULE_API_VERSION_1_0\n */\n#define CAMERA_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define CAMERA_MODULE_API_VERSION_2_0 HARDWARE_MODULE_API_VERSION(2, 0)\n#define CAMERA_MODULE_API_VERSION_2_1 HARDWARE_MODULE_API_VERSION(2, 1)\n#define CAMERA_MODULE_API_VERSION_2_2 HARDWARE_MODULE_API_VERSION(2, 2)\n#define CAMERA_MODULE_API_VERSION_2_3 HARDWARE_MODULE_API_VERSION(2, 3)\n#define CAMERA_MODULE_API_VERSION_2_4 HARDWARE_MODULE_API_VERSION(2, 4)\n\n#define CAMERA_MODULE_API_VERSION_CURRENT CAMERA_MODULE_API_VERSION_2_4\n\n/**\n * All device versions <= HARDWARE_DEVICE_API_VERSION(1, 0xFF) must be treated\n * as CAMERA_DEVICE_API_VERSION_1_0\n */\n#define CAMERA_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n#define CAMERA_DEVICE_API_VERSION_2_0 HARDWARE_DEVICE_API_VERSION(2, 0)\n#define CAMERA_DEVICE_API_VERSION_2_1 HARDWARE_DEVICE_API_VERSION(2, 1)\n#define CAMERA_DEVICE_API_VERSION_3_0 HARDWARE_DEVICE_API_VERSION(3, 0)\n#define CAMERA_DEVICE_API_VERSION_3_1 HARDWARE_DEVICE_API_VERSION(3, 1)\n#define CAMERA_DEVICE_API_VERSION_3_2 HARDWARE_DEVICE_API_VERSION(3, 2)\n#define CAMERA_DEVICE_API_VERSION_3_3 HARDWARE_DEVICE_API_VERSION(3, 3)\n\n// Device version 3.3 is current, older HAL camera device versions are not\n// recommended for new devices.\n#define CAMERA_DEVICE_API_VERSION_CURRENT CAMERA_DEVICE_API_VERSION_3_3\n\n/**\n * Defined in /system/media/camera/include/system/camera_metadata.h\n */\ntypedef struct camera_metadata camera_metadata_t;\n\ntypedef struct camera_info {\n    /**\n     * The direction that the camera faces to. See system/core/include/system/camera.h\n     * for camera facing definitions.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *   It should be CAMERA_FACING_BACK or CAMERA_FACING_FRONT.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *   It should be CAMERA_FACING_BACK, CAMERA_FACING_FRONT or\n     *   CAMERA_FACING_EXTERNAL.\n     */\n    int facing;\n\n    /**\n     * The orientation of the camera image. The value is the angle that the\n     * camera image needs to be rotated clockwise so it shows correctly on the\n     * display in its natural orientation. It should be 0, 90, 180, or 270.\n     *\n     * For example, suppose a device has a naturally tall screen. The\n     * back-facing camera sensor is mounted in landscape. You are looking at the\n     * screen. If the top side of the camera sensor is aligned with the right\n     * edge of the screen in natural orientation, the value should be 90. If the\n     * top side of a front-facing camera sensor is aligned with the right of the\n     * screen, the value should be 270.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *   Valid in all camera_module versions.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *   Valid if camera facing is CAMERA_FACING_BACK or CAMERA_FACING_FRONT,\n     *   not valid if camera facing is CAMERA_FACING_EXTERNAL.\n     */\n    int orientation;\n\n    /**\n     * The value of camera_device_t.common.version.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_1_0:\n     *\n     *    Not valid. Can be assumed to be CAMERA_DEVICE_API_VERSION_1_0. Do\n     *    not read this field.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_0 or higher:\n     *\n     *    Always valid\n     *\n     */\n    uint32_t device_version;\n\n    /**\n     * The camera's fixed characteristics, which include all static camera metadata\n     * specified in system/media/camera/docs/docs.html. This should be a sorted metadata\n     * buffer, and may not be modified or freed by the caller. The pointer should remain\n     * valid for the lifetime of the camera module, and values in it may not\n     * change after it is returned by get_camera_info().\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_1_0:\n     *\n     *    Not valid. Extra characteristics are not available. Do not read this\n     *    field.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_0 or higher:\n     *\n     *    Valid if device_version >= CAMERA_DEVICE_API_VERSION_2_0. Do not read\n     *    otherwise.\n     *\n     */\n    const camera_metadata_t *static_camera_characteristics;\n\n    /**\n     * The total resource \"cost\" of using this camera, represented as an integer\n     * value in the range [0, 100] where 100 represents total usage of the shared\n     * resource that is the limiting bottleneck of the camera subsystem.  This may\n     * be a very rough estimate, and is used as a hint to the camera service to\n     * determine when to disallow multiple applications from simultaneously\n     * opening different cameras advertised by the camera service.\n     *\n     * The camera service must be able to simultaneously open and use any\n     * combination of camera devices exposed by the HAL where the sum of\n     * the resource costs of these cameras is <= 100.  For determining cost,\n     * each camera device must be assumed to be configured and operating at\n     * the maximally resource-consuming framerate and stream size settings\n     * available in the configuration settings exposed for that device through\n     * the camera metadata.\n     *\n     * The camera service may still attempt to simultaneously open combinations\n     * of camera devices with a total resource cost > 100.  This may succeed or\n     * fail.  If this succeeds, combinations of configurations that are not\n     * supported due to resource constraints from having multiple open devices\n     * should fail during the configure calls.  If the total resource cost is\n     * <= 100, open and configure should never fail for any stream configuration\n     * settings or other device capabilities that would normally succeed for a\n     * device when it is the only open camera device.\n     *\n     * This field will be used to determine whether background applications are\n     * allowed to use this camera device while other applications are using other\n     * camera devices.  Note: multiple applications will never be allowed by the\n     * camera service to simultaneously open the same camera device.\n     *\n     * Example use cases:\n     *\n     * Ex. 1: Camera Device 0 = Back Camera\n     *        Camera Device 1 = Front Camera\n     *   - Using both camera devices causes a large framerate slowdown due to\n     *     limited ISP bandwidth.\n     *\n     *   Configuration:\n     *\n     *   Camera Device 0 - resource_cost = 51\n     *                     conflicting_devices = null\n     *   Camera Device 1 - resource_cost = 51\n     *                     conflicting_devices = null\n     *\n     *   Result:\n     *\n     *   Since the sum of the resource costs is > 100, if a higher-priority\n     *   application has either device open, no lower-priority applications will be\n     *   allowed by the camera service to open either device.  If a lower-priority\n     *   application is using a device that a higher-priority subsequently attempts\n     *   to open, the lower-priority application will be forced to disconnect the\n     *   the device.\n     *\n     *   If the highest-priority application chooses, it may still attempt to open\n     *   both devices (since these devices are not listed as conflicting in the\n     *   conflicting_devices fields), but usage of these devices may fail in the\n     *   open or configure calls.\n     *\n     * Ex. 2: Camera Device 0 = Left Back Camera\n     *        Camera Device 1 = Right Back Camera\n     *        Camera Device 2 = Combined stereo camera using both right and left\n     *                          back camera sensors used by devices 0, and 1\n     *        Camera Device 3 = Front Camera\n     *   - Due to do hardware constraints, up to two cameras may be open at once. The\n     *     combined stereo camera may never be used at the same time as either of the\n     *     two back camera devices (device 0, 1), and typically requires too much\n     *     bandwidth to use at the same time as the front camera (device 3).\n     *\n     *   Configuration:\n     *\n     *   Camera Device 0 - resource_cost = 50\n     *                     conflicting_devices = { 2 }\n     *   Camera Device 1 - resource_cost = 50\n     *                     conflicting_devices = { 2 }\n     *   Camera Device 2 - resource_cost = 100\n     *                     conflicting_devices = { 0, 1 }\n     *   Camera Device 3 - resource_cost = 50\n     *                     conflicting_devices = null\n     *\n     *   Result:\n     *\n     *   Based on the conflicting_devices fields, the camera service guarantees that\n     *   the following sets of open devices will never be allowed: { 1, 2 }, { 0, 2 }.\n     *\n     *   Based on the resource_cost fields, if a high-priority foreground application\n     *   is using camera device 0, a background application would be allowed to open\n     *   camera device 1 or 3 (but would be forced to disconnect it again if the\n     *   foreground application opened another device).\n     *\n     *   The highest priority application may still attempt to simultaneously open\n     *   devices 0, 2, and 3, but the HAL may fail in open or configure calls for\n     *   this combination.\n     *\n     * Ex. 3: Camera Device 0 = Back Camera\n     *        Camera Device 1 = Front Camera\n     *        Camera Device 2 = Low-power Front Camera that uses the same\n     *                          sensor as device 1, but only exposes image stream\n     *                          resolutions that can be used in low-power mode\n     *  - Using both front cameras (device 1, 2) at the same time is impossible due\n     *    a shared physical sensor.  Using the back and \"high-power\" front camera\n     *    (device 1) may be impossible for some stream configurations due to hardware\n     *    limitations, but the \"low-power\" front camera option may always be used as\n     *    it has special dedicated hardware.\n     *\n     *   Configuration:\n     *\n     *   Camera Device 0 - resource_cost = 100\n     *                     conflicting_devices = null\n     *   Camera Device 1 - resource_cost = 100\n     *                     conflicting_devices = { 2 }\n     *   Camera Device 2 - resource_cost = 0\n     *                     conflicting_devices = { 1 }\n     *   Result:\n     *\n     *   Based on the conflicting_devices fields, the camera service guarantees that\n     *   the following sets of open devices will never be allowed: { 1, 2 }.\n     *\n     *   Based on the resource_cost fields, only the highest priority application\n     *   may attempt to open both device 0 and 1 at the same time. If a higher-priority\n     *   application is not using device 1 or 2, a low-priority background application\n     *   may open device 2 (but will be forced to disconnect it if a higher-priority\n     *   application subsequently opens device 1 or 2).\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *    Not valid.  Can be assumed to be 100.  Do not read this field.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *    Always valid.\n     */\n    int resource_cost;\n\n    /**\n     * An array of camera device IDs represented as NULL-terminated strings\n     * indicating other devices that cannot be simultaneously opened while this\n     * camera device is in use.\n     *\n     * This field is intended to be used to indicate that this camera device\n     * is a composite of several other camera devices, or otherwise has\n     * hardware dependencies that prohibit simultaneous usage. If there are no\n     * dependencies, a NULL may be returned in this field to indicate this.\n     *\n     * The camera service will never simultaneously open any of the devices\n     * in this list while this camera device is open.\n     *\n     * The strings pointed to in this field will not be cleaned up by the camera\n     * service, and must remain while this device is plugged in.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *    Not valid.  Can be assumed to be NULL.  Do not read this field.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *    Always valid.\n     */\n    char** conflicting_devices;\n\n    /**\n     * The length of the array given in the conflicting_devices field.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *    Not valid.  Can be assumed to be 0.  Do not read this field.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *    Always valid.\n     */\n    size_t conflicting_devices_length;\n\n} camera_info_t;\n\n/**\n * camera_device_status_t:\n *\n * The current status of the camera device, as provided by the HAL through the\n * camera_module_callbacks.camera_device_status_change() call.\n *\n * At module load time, the framework will assume all camera devices are in the\n * CAMERA_DEVICE_STATUS_PRESENT state. The HAL should invoke\n * camera_module_callbacks::camera_device_status_change to inform the framework\n * of any initially NOT_PRESENT devices.\n *\n * Allowed transitions:\n *      PRESENT            -> NOT_PRESENT\n *      NOT_PRESENT        -> ENUMERATING\n *      NOT_PRESENT        -> PRESENT\n *      ENUMERATING        -> PRESENT\n *      ENUMERATING        -> NOT_PRESENT\n */\ntypedef enum camera_device_status {\n    /**\n     * The camera device is not currently connected, and opening it will return\n     * failure.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *   Calls to get_camera_info must still succeed, and provide the same information\n     *   it would if the camera were connected.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4:\n     *\n     *   The camera device at this status must return -EINVAL for get_camera_info call,\n     *   as the device is not connected.\n     */\n    CAMERA_DEVICE_STATUS_NOT_PRESENT = 0,\n\n    /**\n     * The camera device is connected, and opening it will succeed.\n     *\n     * CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *   The information returned by get_camera_info cannot change due to this status\n     *   change. By default, the framework will assume all devices are in this state.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4:\n     *\n     *   The information returned by get_camera_info will become valid after a device's\n     *   status changes to this. By default, the framework will assume all devices are in\n     *   this state.\n     */\n    CAMERA_DEVICE_STATUS_PRESENT = 1,\n\n    /**\n     * The camera device is connected, but it is undergoing an enumeration and\n     * so opening the device will return -EBUSY.\n     *\n     * CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *   Calls to get_camera_info must still succeed, as if the camera was in the\n     *   PRESENT status.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4:\n     *\n     *   The camera device at this status must return -EINVAL for get_camera_info for call,\n     *   as the device is not ready.\n     */\n    CAMERA_DEVICE_STATUS_ENUMERATING = 2,\n\n} camera_device_status_t;\n\n/**\n * torch_mode_status_t:\n *\n * The current status of the torch mode, as provided by the HAL through the\n * camera_module_callbacks.torch_mode_status_change() call.\n *\n * The torch mode status of a camera device is applicable only when the camera\n * device is present. The framework will not call set_torch_mode() to turn on\n * torch mode of a camera device if the camera device is not present. At module\n * load time, the framework will assume torch modes are in the\n * TORCH_MODE_STATUS_AVAILABLE_OFF state if the camera device is present and\n * android.flash.info.available is reported as true via get_camera_info() call.\n *\n * The behaviors of the camera HAL module that the framework expects in the\n * following situations when a camera device's status changes:\n *  1. A previously-disconnected camera device becomes connected.\n *      After camera_module_callbacks::camera_device_status_change() is invoked\n *      to inform the framework that the camera device is present, the framework\n *      will assume the camera device's torch mode is in\n *      TORCH_MODE_STATUS_AVAILABLE_OFF state. The camera HAL module does not need\n *      to invoke camera_module_callbacks::torch_mode_status_change() unless the\n *      flash unit is unavailable to use by set_torch_mode().\n *\n *  2. A previously-connected camera becomes disconnected.\n *      After camera_module_callbacks::camera_device_status_change() is invoked\n *      to inform the framework that the camera device is not present, the\n *      framework will not call set_torch_mode() for the disconnected camera\n *      device until its flash unit becomes available again. The camera HAL\n *      module does not need to invoke\n *      camera_module_callbacks::torch_mode_status_change() separately to inform\n *      that the flash unit has become unavailable.\n *\n *  3. open() is called to open a camera device.\n *      The camera HAL module must invoke\n *      camera_module_callbacks::torch_mode_status_change() for all flash units\n *      that have entered TORCH_MODE_STATUS_NOT_AVAILABLE state and can not be\n *      turned on by calling set_torch_mode() anymore due to this open() call.\n *      open() must not trigger TORCH_MODE_STATUS_AVAILABLE_OFF before\n *      TORCH_MODE_STATUS_NOT_AVAILABLE for all flash units that have become\n *      unavailable.\n *\n *  4. close() is called to close a camera device.\n *      The camera HAL module must invoke\n *      camera_module_callbacks::torch_mode_status_change() for all flash units\n *      that have entered TORCH_MODE_STATUS_AVAILABLE_OFF state and can be turned\n *      on by calling set_torch_mode() again because of enough resources freed\n *      up by this close() call.\n *\n *  Note that the framework calling set_torch_mode() successfully must trigger\n *  TORCH_MODE_STATUS_AVAILABLE_OFF or TORCH_MODE_STATUS_AVAILABLE_ON callback\n *  for the given camera device. Additionally it must trigger\n *  TORCH_MODE_STATUS_AVAILABLE_OFF callbacks for other previously-on torch\n *  modes if HAL cannot keep multiple torch modes on simultaneously.\n */\ntypedef enum torch_mode_status {\n\n    /**\n     * The flash unit is no longer available and the torch mode can not be\n     * turned on by calling set_torch_mode(). If the torch mode is on, it\n     * will be turned off by HAL before HAL calls torch_mode_status_change().\n     */\n    TORCH_MODE_STATUS_NOT_AVAILABLE = 0,\n\n    /**\n     * A torch mode has become off and available to be turned on via\n     * set_torch_mode(). This may happen in the following\n     * cases:\n     *   1. After the resources to turn on the torch mode have become available.\n     *   2. After set_torch_mode() is called to turn off the torch mode.\n     *   3. After the framework turned on the torch mode of some other camera\n     *      device and HAL had to turn off the torch modes of any camera devices\n     *      that were previously on.\n     */\n    TORCH_MODE_STATUS_AVAILABLE_OFF = 1,\n\n    /**\n     * A torch mode has become on and available to be turned off via\n     * set_torch_mode(). This can happen only after set_torch_mode() is called\n     * to turn on the torch mode.\n     */\n    TORCH_MODE_STATUS_AVAILABLE_ON = 2,\n\n} torch_mode_status_t;\n\n/**\n * Callback functions for the camera HAL module to use to inform the framework\n * of changes to the camera subsystem.\n *\n * Version information (based on camera_module_t.common.module_api_version):\n *\n * Each callback is called only by HAL modules implementing the indicated\n * version or higher of the HAL module API interface.\n *\n *  CAMERA_MODULE_API_VERSION_2_1:\n *    camera_device_status_change()\n *\n *  CAMERA_MODULE_API_VERSION_2_4:\n *    torch_mode_status_change()\n\n */\ntypedef struct camera_module_callbacks {\n\n    /**\n     * camera_device_status_change:\n     *\n     * Callback to the framework to indicate that the state of a specific camera\n     * device has changed. At module load time, the framework will assume all\n     * camera devices are in the CAMERA_DEVICE_STATUS_PRESENT state. The HAL\n     * must call this method to inform the framework of any initially\n     * NOT_PRESENT devices.\n     *\n     * This callback is added for CAMERA_MODULE_API_VERSION_2_1.\n     *\n     * camera_module_callbacks: The instance of camera_module_callbacks_t passed\n     *   to the module with set_callbacks.\n     *\n     * camera_id: The ID of the camera device that has a new status.\n     *\n     * new_status: The new status code, one of the camera_device_status_t enums,\n     *   or a platform-specific status.\n     *\n     */\n    void (*camera_device_status_change)(const struct camera_module_callbacks*,\n            int camera_id,\n            int new_status);\n\n    /**\n     * torch_mode_status_change:\n     *\n     * Callback to the framework to indicate that the state of the torch mode\n     * of the flash unit associated with a specific camera device has changed.\n     * At module load time, the framework will assume the torch modes are in\n     * the TORCH_MODE_STATUS_AVAILABLE_OFF state if android.flash.info.available\n     * is reported as true via get_camera_info() call.\n     *\n     * This callback is added for CAMERA_MODULE_API_VERSION_2_4.\n     *\n     * camera_module_callbacks: The instance of camera_module_callbacks_t\n     *   passed to the module with set_callbacks.\n     *\n     * camera_id: The ID of camera device whose flash unit has a new torch mode\n     *   status.\n     *\n     * new_status: The new status code, one of the torch_mode_status_t enums.\n     */\n    void (*torch_mode_status_change)(const struct camera_module_callbacks*,\n            const char* camera_id,\n            int new_status);\n\n\n} camera_module_callbacks_t;\n\ntypedef struct camera_module {\n    /**\n     * Common methods of the camera module.  This *must* be the first member of\n     * camera_module as users of this structure will cast a hw_module_t to\n     * camera_module pointer in contexts where it's known the hw_module_t\n     * references a camera_module.\n     *\n     * The return values for common.methods->open for camera_module are:\n     *\n     * 0:           On a successful open of the camera device.\n     *\n     * -ENODEV:     The camera device cannot be opened due to an internal\n     *              error.\n     *\n     * -EINVAL:     The input arguments are invalid, i.e. the id is invalid,\n     *              and/or the module is invalid.\n     *\n     * -EBUSY:      The camera device was already opened for this camera id\n     *              (by using this method or open_legacy),\n     *              regardless of the device HAL version it was opened as.\n     *\n     * -EUSERS:     The maximal number of camera devices that can be\n     *              opened concurrently were opened already, either by\n     *              this method or the open_legacy method.\n     *\n     * All other return values from common.methods->open will be treated as\n     * -ENODEV.\n     */\n    hw_module_t common;\n\n    /**\n     * get_number_of_cameras:\n     *\n     * Returns the number of camera devices accessible through the camera\n     * module.  The camera devices are numbered 0 through N-1, where N is the\n     * value returned by this call. The name of the camera device for open() is\n     * simply the number converted to a string. That is, \"0\" for camera ID 0,\n     * \"1\" for camera ID 1.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_2_3 or lower:\n     *\n     *   The value here must be static, and cannot change after the first call\n     *   to this method.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *   The value here must be static, and must count only built-in cameras,\n     *   which have CAMERA_FACING_BACK or CAMERA_FACING_FRONT camera facing values\n     *   (camera_info.facing). The HAL must not include the external cameras\n     *   (camera_info.facing == CAMERA_FACING_EXTERNAL) into the return value\n     *   of this call. Frameworks will use camera_device_status_change callback\n     *   to manage number of external cameras.\n     */\n    int (*get_number_of_cameras)(void);\n\n    /**\n     * get_camera_info:\n     *\n     * Return the static camera information for a given camera device. This\n     * information may not change for a camera device.\n     *\n     * Return values:\n     *\n     * 0:           On a successful operation\n     *\n     * -ENODEV:     The information cannot be provided due to an internal\n     *              error.\n     *\n     * -EINVAL:     The input arguments are invalid, i.e. the id is invalid,\n     *              and/or the module is invalid.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_2_4 or higher:\n     *\n     *   When a camera is disconnected, its camera id becomes invalid. Calling this\n     *   this method with this invalid camera id will get -EINVAL and NULL camera\n     *   static metadata (camera_info.static_camera_characteristics).\n     */\n    int (*get_camera_info)(int camera_id, struct camera_info *info);\n\n    /**\n     * set_callbacks:\n     *\n     * Provide callback function pointers to the HAL module to inform framework\n     * of asynchronous camera module events. The framework will call this\n     * function once after initial camera HAL module load, after the\n     * get_number_of_cameras() method is called for the first time, and before\n     * any other calls to the module.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_1_0, CAMERA_MODULE_API_VERSION_2_0:\n     *\n     *    Not provided by HAL module. Framework may not call this function.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_1:\n     *\n     *    Valid to be called by the framework.\n     *\n     * Return values:\n     *\n     * 0:           On a successful operation\n     *\n     * -ENODEV:     The operation cannot be completed due to an internal\n     *              error.\n     *\n     * -EINVAL:     The input arguments are invalid, i.e. the callbacks are\n     *              null\n     */\n    int (*set_callbacks)(const camera_module_callbacks_t *callbacks);\n\n    /**\n     * get_vendor_tag_ops:\n     *\n     * Get methods to query for vendor extension metadata tag information. The\n     * HAL should fill in all the vendor tag operation methods, or leave ops\n     * unchanged if no vendor tags are defined.\n     *\n     * The vendor_tag_ops structure used here is defined in:\n     * system/media/camera/include/system/vendor_tags.h\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_1_x/2_0/2_1:\n     *    Not provided by HAL module. Framework may not call this function.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_2:\n     *    Valid to be called by the framework.\n     */\n    void (*get_vendor_tag_ops)(vendor_tag_ops_t* ops);\n\n    /**\n     * open_legacy:\n     *\n     * Open a specific legacy camera HAL device if multiple device HAL API\n     * versions are supported by this camera HAL module. For example, if the\n     * camera module supports both CAMERA_DEVICE_API_VERSION_1_0 and\n     * CAMERA_DEVICE_API_VERSION_3_2 device API for the same camera id,\n     * framework can call this function to open the camera device as\n     * CAMERA_DEVICE_API_VERSION_1_0 device.\n     *\n     * This is an optional method. A Camera HAL module does not need to support\n     * more than one device HAL version per device, and such modules may return\n     * -ENOSYS for all calls to this method. For all older HAL device API\n     * versions that are not supported, it may return -EOPNOTSUPP. When above\n     * cases occur, The normal open() method (common.methods->open) will be\n     * used by the framework instead.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     *  CAMERA_MODULE_API_VERSION_1_x/2_0/2_1/2_2:\n     *    Not provided by HAL module. Framework will not call this function.\n     *\n     *  CAMERA_MODULE_API_VERSION_2_3:\n     *    Valid to be called by the framework.\n     *\n     * Return values:\n     *\n     * 0:           On a successful open of the camera device.\n     *\n     * -ENOSYS      This method is not supported.\n     *\n     * -EOPNOTSUPP: The requested HAL version is not supported by this method.\n     *\n     * -EINVAL:     The input arguments are invalid, i.e. the id is invalid,\n     *              and/or the module is invalid.\n     *\n     * -EBUSY:      The camera device was already opened for this camera id\n     *              (by using this method or common.methods->open method),\n     *              regardless of the device HAL version it was opened as.\n     *\n     * -EUSERS:     The maximal number of camera devices that can be\n     *              opened concurrently were opened already, either by\n     *              this method or common.methods->open method.\n     */\n    int (*open_legacy)(const struct hw_module_t* module, const char* id,\n            uint32_t halVersion, struct hw_device_t** device);\n\n    /**\n     * set_torch_mode:\n     *\n     * Turn on or off the torch mode of the flash unit associated with a given\n     * camera ID. If the operation is successful, HAL must notify the framework\n     * torch state by invoking\n     * camera_module_callbacks.torch_mode_status_change() with the new state.\n     *\n     * The camera device has a higher priority accessing the flash unit. When\n     * there are any resource conflicts, such as open() is called to open a\n     * camera device, HAL module must notify the framework through\n     * camera_module_callbacks.torch_mode_status_change() that the\n     * torch mode has been turned off and the torch mode state has become\n     * TORCH_MODE_STATUS_NOT_AVAILABLE. When resources to turn on torch mode\n     * become available again, HAL module must notify the framework through\n     * camera_module_callbacks.torch_mode_status_change() that the torch mode\n     * state has become TORCH_MODE_STATUS_AVAILABLE_OFF for set_torch_mode() to\n     * be called.\n     *\n     * When the framework calls set_torch_mode() to turn on the torch mode of a\n     * flash unit, if HAL cannot keep multiple torch modes on simultaneously,\n     * HAL should turn off the torch mode that was turned on by\n     * a previous set_torch_mode() call and notify the framework that the torch\n     * mode state of that flash unit has become TORCH_MODE_STATUS_AVAILABLE_OFF.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_1_x/2_0/2_1/2_2/2_3:\n     *   Not provided by HAL module. Framework will not call this function.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4:\n     *   Valid to be called by the framework.\n     *\n     * Return values:\n     *\n     * 0:           On a successful operation.\n     *\n     * -ENOSYS:     The camera device does not support this operation. It is\n     *              returned if and only if android.flash.info.available is\n     *              false.\n     *\n     * -EBUSY:      The camera device is already in use.\n     *\n     * -EUSERS:     The resources needed to turn on the torch mode are not\n     *              available, typically because other camera devices are\n     *              holding the resources to make using the flash unit not\n     *              possible.\n     *\n     * -EINVAL:     camera_id is invalid.\n     *\n     */\n    int (*set_torch_mode)(const char* camera_id, bool enabled);\n\n    /**\n     * init:\n     *\n     * This method is called by the camera service before any other methods\n     * are invoked, right after the camera HAL library has been successfully\n     * loaded. It may be left as NULL by the HAL module, if no initialization\n     * in needed.\n     *\n     * It can be used by HAL implementations to perform initialization and\n     * other one-time operations.\n     *\n     * Version information (based on camera_module_t.common.module_api_version):\n     *\n     * CAMERA_MODULE_API_VERSION_1_x/2_0/2_1/2_2/2_3:\n     *   Not provided by HAL module. Framework will not call this function.\n     *\n     * CAMERA_MODULE_API_VERSION_2_4:\n     *   If not NULL, will always be called by the framework once after the HAL\n     *   module is loaded, before any other HAL module method is called.\n     *\n     * Return values:\n     *\n     * 0:           On a successful operation.\n     *\n     * -ENODEV:     Initialization cannot be completed due to an internal\n     *              error. The HAL must be assumed to be in a nonfunctional\n     *              state.\n     *\n     */\n    int (*init)();\n\n    /* reserved for future use */\n    void* reserved[5];\n} camera_module_t;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_CAMERA_COMMON_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/consumerir.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_CONSUMERIR_H\n#define ANDROID_INCLUDE_HARDWARE_CONSUMERIR_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <hardware/hardware.h>\n#include <hardware/hwcomposer_defs.h>\n\n#define CONSUMERIR_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define CONSUMERIR_HARDWARE_MODULE_ID \"consumerir\"\n#define CONSUMERIR_TRANSMITTER \"transmitter\"\n\ntypedef struct consumerir_freq_range {\n    int min;\n    int max;\n} consumerir_freq_range_t;\n\ntypedef struct consumerir_module {\n    /**\n     * Common methods of the consumer IR module.  This *must* be the first member of\n     * consumerir_module as users of this structure will cast a hw_module_t to\n     * consumerir_module pointer in contexts where it's known the hw_module_t references a\n     * consumerir_module.\n     */\n    struct hw_module_t common;\n} consumerir_module_t;\n\ntypedef struct consumerir_device {\n    /**\n     * Common methods of the consumer IR device.  This *must* be the first member of\n     * consumerir_device as users of this structure will cast a hw_device_t to\n     * consumerir_device pointer in contexts where it's known the hw_device_t references a\n     * consumerir_device.\n     */\n    struct hw_device_t common;\n\n    /*\n     * (*transmit)() is called to by the ConsumerIrService to send an IR pattern\n     * at a given carrier_freq.\n     *\n     * The pattern is alternating series of carrier on and off periods measured in\n     * microseconds.  The carrier should be turned off at the end of a transmit\n     * even if there are and odd number of entries in the pattern array.\n     *\n     * This call should return when the transmit is complete or encounters an error.\n     *\n     * returns: 0 on success. A negative error code on error.\n     */\n    int (*transmit)(struct consumerir_device *dev, int carrier_freq,\n            const int pattern[], int pattern_len);\n\n    /*\n     * (*get_num_carrier_freqs)() is called by the ConsumerIrService to get the\n     * number of carrier freqs to allocate space for, which is then filled by\n     * a subsequent call to (*get_carrier_freqs)().\n     *\n     * returns: the number of ranges on success. A negative error code on error.\n     */\n    int (*get_num_carrier_freqs)(struct consumerir_device *dev);\n\n    /*\n     * (*get_carrier_freqs)() is called by the ConsumerIrService to enumerate\n     * which frequencies the IR transmitter supports.  The HAL implementation\n     * should fill an array of consumerir_freq_range structs with the\n     * appropriate values for the transmitter, up to len elements.\n     *\n     * returns: the number of ranges on success. A negative error code on error.\n     */\n    int (*get_carrier_freqs)(struct consumerir_device *dev,\n            size_t len, consumerir_freq_range_t *ranges);\n\n    /* Reserved for future use. Must be NULL. */\n    void* reserved[8 - 3];\n} consumerir_device_t;\n\n#endif /* ANDROID_INCLUDE_HARDWARE_CONSUMERIR_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/display_defs.h",
    "content": "/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *     * Redistributions of source code must retain the above copyright\n *       notice, this list of conditions and the following disclaimer.\n *     * Redistributions in binary form must reproduce the above\n *       copyright notice, this list of conditions and the following\n *       disclaimer in the documentation and/or other materials provided\n *       with the distribution.\n *     * Neither the name of The Linux Foundation nor the names of its\n *       contributors may be used to endorse or promote products derived\n *       from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\n * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\n * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN\n * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ANDROID_INCLUDE_DISPLAY_DEFS_H\n#define ANDROID_INCLUDE_DISPLAY_DEFS_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n\n#include <hardware/hwcomposer.h>\n\n__BEGIN_DECLS\n\n/* Will need to update below enums if hwcomposer_defs.h is updated */\n\n/* Extended events for hwc_methods::eventControl() */\nenum {\n    HWC_EVENT_ORIENTATION             = HWC_EVENT_VSYNC + 1\n};\n\n\n/* Extended hwc_layer_t::compositionType values */\nenum {\n    /* this layer will be handled in the HWC, using a blit engine */\n    HWC_BLIT                          = 0xFF\n};\n\n/* Extended hwc_layer_t::flags values\n * Flags are set by SurfaceFlinger and read by the HAL\n */\nenum {\n    /*\n     * HWC_SCREENSHOT_ANIMATOR_LAYER is set by surfaceflinger to indicate\n     * that this layer is a screenshot animating layer. HWC uses this\n     * info to disable rotation animation on External Display\n     */\n    HWC_SCREENSHOT_ANIMATOR_LAYER     = 0x00000004\n};\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_DISPLAY_DEFS_H*/\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/fb.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_FB_INTERFACE_H\n#define ANDROID_FB_INTERFACE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <cutils/native_handle.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define GRALLOC_HARDWARE_FB0 \"fb0\"\n\n/*****************************************************************************/\n\n\n/*****************************************************************************/\n\ntypedef struct framebuffer_device_t {\n    /**\n     * Common methods of the framebuffer device.  This *must* be the first member of\n     * framebuffer_device_t as users of this structure will cast a hw_device_t to\n     * framebuffer_device_t pointer in contexts where it's known the hw_device_t references a\n     * framebuffer_device_t.\n     */\n    struct hw_device_t common;\n\n    /* flags describing some attributes of the framebuffer */\n    const uint32_t  flags;\n\n    /* dimensions of the framebuffer in pixels */\n    const uint32_t  width;\n    const uint32_t  height;\n\n    /* frambuffer stride in pixels */\n    const int       stride;\n\n    /* framebuffer pixel format */\n    const int       format;\n\n    /* resolution of the framebuffer's display panel in pixel per inch*/\n    const float     xdpi;\n    const float     ydpi;\n\n    /* framebuffer's display panel refresh rate in frames per second */\n    const float     fps;\n\n    /* min swap interval supported by this framebuffer */\n    const int       minSwapInterval;\n\n    /* max swap interval supported by this framebuffer */\n    const int       maxSwapInterval;\n\n    /* Number of framebuffers supported*/\n    const int       numFramebuffers;\n\n    int reserved[7];\n\n    /*\n     * requests a specific swap-interval (same definition than EGL)\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*setSwapInterval)(struct framebuffer_device_t* window,\n            int interval);\n\n    /*\n     * This hook is OPTIONAL.\n     *\n     * It is non NULL If the framebuffer driver supports \"update-on-demand\"\n     * and the given rectangle is the area of the screen that gets\n     * updated during (*post)().\n     *\n     * This is useful on devices that are able to DMA only a portion of\n     * the screen to the display panel, upon demand -- as opposed to\n     * constantly refreshing the panel 60 times per second, for instance.\n     *\n     * Only the area defined by this rectangle is guaranteed to be valid, that\n     * is, the driver is not allowed to post anything outside of this\n     * rectangle.\n     *\n     * The rectangle evaluated during (*post)() and specifies which area\n     * of the buffer passed in (*post)() shall to be posted.\n     *\n     * return -EINVAL if width or height <=0, or if left or top < 0\n     */\n    int (*setUpdateRect)(struct framebuffer_device_t* window,\n            int left, int top, int width, int height);\n\n    /*\n     * Post <buffer> to the display (display it on the screen)\n     * The buffer must have been allocated with the\n     *   GRALLOC_USAGE_HW_FB usage flag.\n     * buffer must be the same width and height as the display and must NOT\n     * be locked.\n     *\n     * The buffer is shown during the next VSYNC.\n     *\n     * If the same buffer is posted again (possibly after some other buffer),\n     * post() will block until the the first post is completed.\n     *\n     * Internally, post() is expected to lock the buffer so that a\n     * subsequent call to gralloc_module_t::(*lock)() with USAGE_RENDER or\n     * USAGE_*_WRITE will block until it is safe; that is typically once this\n     * buffer is shown and another buffer has been posted.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*post)(struct framebuffer_device_t* dev, buffer_handle_t buffer);\n\n\n    /*\n     * The (*compositionComplete)() method must be called after the\n     * compositor has finished issuing GL commands for client buffers.\n     */\n\n    int (*compositionComplete)(struct framebuffer_device_t* dev);\n\n    /*\n     * This hook is OPTIONAL.\n     *\n     * If non NULL it will be caused by SurfaceFlinger on dumpsys\n     */\n    void (*dump)(struct framebuffer_device_t* dev, char *buff, int buff_len);\n\n    /*\n     * (*enableScreen)() is used to either blank (enable=0) or\n     * unblank (enable=1) the screen this framebuffer is attached to.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*enableScreen)(struct framebuffer_device_t* dev, int enable);\n\n    void* reserved_proc[6];\n\n} framebuffer_device_t;\n\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int framebuffer_open(const struct hw_module_t* module,\n        struct framebuffer_device_t** device) {\n    return module->methods->open(module,\n            GRALLOC_HARDWARE_FB0, (struct hw_device_t**)device);\n}\n\nstatic inline int framebuffer_close(struct framebuffer_device_t* device) {\n    return device->common.close(&device->common);\n}\n\n\n__END_DECLS\n\n#endif  // ANDROID_FB_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/fingerprint.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_FINGERPRINT_H\n#define ANDROID_INCLUDE_HARDWARE_FINGERPRINT_H\n\n#include <hardware/hw_auth_token.h>\n\n#define FINGERPRINT_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define FINGERPRINT_MODULE_API_VERSION_2_0 HARDWARE_MODULE_API_VERSION(2, 0)\n#define FINGERPRINT_HARDWARE_MODULE_ID \"fingerprint\"\n\ntypedef enum fingerprint_msg_type {\n    FINGERPRINT_ERROR = -1,\n    FINGERPRINT_ACQUIRED = 1,\n    FINGERPRINT_TEMPLATE_ENROLLING = 3,\n    FINGERPRINT_TEMPLATE_REMOVED = 4,\n    FINGERPRINT_AUTHENTICATED = 5\n} fingerprint_msg_type_t;\n\n/*\n * Fingerprint errors are meant to tell the framework to terminate the current operation and ask\n * for the user to correct the situation. These will almost always result in messaging and user\n * interaction to correct the problem.\n *\n * For example, FINGERPRINT_ERROR_CANCELED should follow any acquisition message that results in\n * a situation where the current operation can't continue without user interaction. For example,\n * if the sensor is dirty during enrollment and no further enrollment progress can be made,\n * send FINGERPRINT_ACQUIRED_IMAGER_DIRTY followed by FINGERPRINT_ERROR_CANCELED.\n */\ntypedef enum fingerprint_error {\n    FINGERPRINT_ERROR_HW_UNAVAILABLE = 1, /* The hardware has an error that can't be resolved. */\n    FINGERPRINT_ERROR_UNABLE_TO_PROCESS = 2, /* Bad data; operation can't continue */\n    FINGERPRINT_ERROR_TIMEOUT = 3, /* The operation has timed out waiting for user input. */\n    FINGERPRINT_ERROR_NO_SPACE = 4, /* No space available to store a template */\n    FINGERPRINT_ERROR_CANCELED = 5, /* The current operation can't proceed. See above. */\n    FINGERPRINT_ERROR_UNABLE_TO_REMOVE = 6, /* fingerprint with given id can't be removed */\n    FINGERPRINT_ERROR_VENDOR_BASE = 1000 /* vendor-specific error messages start here */\n} fingerprint_error_t;\n\n/*\n * Fingerprint acquisition info is meant as feedback for the current operation.  Anything but\n * FINGERPRINT_ACQUIRED_GOOD will be shown to the user as feedback on how to take action on the\n * current operation. For example, FINGERPRINT_ACQUIRED_IMAGER_DIRTY can be used to tell the user\n * to clean the sensor.  If this will cause the current operation to fail, an additional\n * FINGERPRINT_ERROR_CANCELED can be sent to stop the operation in progress (e.g. enrollment).\n * In general, these messages will result in a \"Try again\" message.\n */\ntypedef enum fingerprint_acquired_info {\n    FINGERPRINT_ACQUIRED_GOOD = 0,\n    FINGERPRINT_ACQUIRED_PARTIAL = 1, /* sensor needs more data, i.e. longer swipe. */\n    FINGERPRINT_ACQUIRED_INSUFFICIENT = 2, /* image doesn't contain enough detail for recognition*/\n    FINGERPRINT_ACQUIRED_IMAGER_DIRTY = 3, /* sensor needs to be cleaned */\n    FINGERPRINT_ACQUIRED_TOO_SLOW = 4, /* mostly swipe-type sensors; not enough data collected */\n    FINGERPRINT_ACQUIRED_TOO_FAST = 5, /* for swipe and area sensors; tell user to slow down*/\n    FINGERPRINT_ACQUIRED_VENDOR_BASE = 1000 /* vendor-specific acquisition messages start here */\n} fingerprint_acquired_info_t;\n\ntypedef struct fingerprint_finger_id {\n    uint32_t gid;\n    uint32_t fid;\n} fingerprint_finger_id_t;\n\ntypedef struct fingerprint_enroll {\n    fingerprint_finger_id_t finger;\n    /* samples_remaining goes from N (no data collected, but N scans needed)\n     * to 0 (no more data is needed to build a template). */\n    uint32_t samples_remaining;\n    uint64_t msg; /* Vendor specific message. Used for user guidance */\n} fingerprint_enroll_t;\n\ntypedef struct fingerprint_removed {\n    fingerprint_finger_id_t finger;\n} fingerprint_removed_t;\n\ntypedef struct fingerprint_acquired {\n    fingerprint_acquired_info_t acquired_info; /* information about the image */\n} fingerprint_acquired_t;\n\ntypedef struct fingerprint_authenticated {\n    fingerprint_finger_id_t finger;\n    hw_auth_token_t hat;\n} fingerprint_authenticated_t;\n\ntypedef struct fingerprint_msg {\n    fingerprint_msg_type_t type;\n    union {\n        fingerprint_error_t error;\n        fingerprint_enroll_t enroll;\n        fingerprint_removed_t removed;\n        fingerprint_acquired_t acquired;\n        fingerprint_authenticated_t authenticated;\n    } data;\n} fingerprint_msg_t;\n\n/* Callback function type */\ntypedef void (*fingerprint_notify_t)(const fingerprint_msg_t *msg);\n\n/* Synchronous operation */\ntypedef struct fingerprint_device {\n    /**\n     * Common methods of the fingerprint device. This *must* be the first member\n     * of fingerprint_device as users of this structure will cast a hw_device_t\n     * to fingerprint_device pointer in contexts where it's known\n     * the hw_device_t references a fingerprint_device.\n     */\n    struct hw_device_t common;\n\n    /*\n     * Client provided callback function to receive notifications.\n     * Do not set by hand, use the function above instead.\n     */\n    fingerprint_notify_t notify;\n\n    /*\n     * Set notification callback:\n     * Registers a user function that would receive notifications from the HAL\n     * The call will block if the HAL state machine is in busy state until HAL\n     * leaves the busy state.\n     *\n     * Function return: 0 if callback function is successfuly registered\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*set_notify)(struct fingerprint_device *dev, fingerprint_notify_t notify);\n\n    /*\n     * Fingerprint pre-enroll enroll request:\n     * Generates a unique token to upper layers to indicate the start of an enrollment transaction.\n     * This token will be wrapped by security for verification and passed to enroll() for\n     * verification before enrollment will be allowed. This is to ensure adding a new fingerprint\n     * template was preceded by some kind of credential confirmation (e.g. device password).\n     *\n     * Function return: 0 if function failed\n     *                  otherwise, a uint64_t of token\n     */\n    uint64_t (*pre_enroll)(struct fingerprint_device *dev);\n\n    /*\n     * Fingerprint enroll request:\n     * Switches the HAL state machine to collect and store a new fingerprint\n     * template. Switches back as soon as enroll is complete\n     * (fingerprint_msg.type == FINGERPRINT_TEMPLATE_ENROLLING &&\n     *  fingerprint_msg.data.enroll.samples_remaining == 0)\n     * or after timeout_sec seconds.\n     * The fingerprint template will be assigned to the group gid. User has a choice\n     * to supply the gid or set it to 0 in which case a unique group id will be generated.\n     *\n     * Function return: 0 if enrollment process can be successfully started\n     *                  or a negative number in case of error, generally from the errno.h set.\n     *                  A notify() function may be called indicating the error condition.\n     */\n    int (*enroll)(struct fingerprint_device *dev, const hw_auth_token_t *hat,\n                    uint32_t gid, uint32_t timeout_sec);\n\n    /*\n     * Finishes the enroll operation and invalidates the pre_enroll() generated challenge.\n     * This will be called at the end of a multi-finger enrollment session to indicate\n     * that no more fingers will be added.\n     *\n     * Function return: 0 if the request is accepted\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*post_enroll)(struct fingerprint_device *dev);\n\n    /*\n     * get_authenticator_id:\n     * Returns a token associated with the current fingerprint set. This value will\n     * change whenever a new fingerprint is enrolled, thus creating a new fingerprint\n     * set.\n     *\n     * Function return: current authenticator id or 0 if function failed.\n     */\n    uint64_t (*get_authenticator_id)(struct fingerprint_device *dev);\n\n    /*\n     * Cancel pending enroll or authenticate, sending FINGERPRINT_ERROR_CANCELED\n     * to all running clients. Switches the HAL state machine back to the idle state.\n     * Unlike enroll_done() doesn't invalidate the pre_enroll() challenge.\n     *\n     * Function return: 0 if cancel request is accepted\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*cancel)(struct fingerprint_device *dev);\n\n    /*\n     * Enumerate all the fingerprint templates found in the directory set by\n     * set_active_group()\n     * This is a synchronous call. The function takes:\n     * - A pointer to an array of fingerprint_finger_id_t.\n     * - The size of the array provided, in fingerprint_finger_id_t elements.\n     * Max_size is a bi-directional parameter and returns the actual number\n     * of elements copied to the caller supplied array.\n     * In the absence of errors the function returns the total number of templates\n     * in the user directory.\n     * If the caller has no good guess on the size of the array he should call this\n     * function witn *max_size == 0 and use the return value for the array allocation.\n     * The caller of this function has a complete list of the templates when *max_size\n     * is the same as the function return.\n     *\n     * Function return: Total number of fingerprint templates in the current storage directory.\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*enumerate)(struct fingerprint_device *dev, fingerprint_finger_id_t *results,\n        uint32_t *max_size);\n\n    /*\n     * Fingerprint remove request:\n     * Deletes a fingerprint template.\n     * Works only within a path set by set_active_group().\n     * notify() will be called with details on the template deleted.\n     * fingerprint_msg.type == FINGERPRINT_TEMPLATE_REMOVED and\n     * fingerprint_msg.data.removed.id indicating the template id removed.\n     *\n     * Function return: 0 if fingerprint template(s) can be successfully deleted\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*remove)(struct fingerprint_device *dev, uint32_t gid, uint32_t fid);\n\n    /*\n     * Restricts the HAL operation to a set of fingerprints belonging to a\n     * group provided.\n     * The caller must provide a path to a storage location within the user's\n     * data directory.\n     *\n     * Function return: 0 on success\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*set_active_group)(struct fingerprint_device *dev, uint32_t gid,\n                            const char *store_path);\n\n    /*\n     * Authenticates an operation identifed by operation_id\n     *\n     * Function return: 0 on success\n     *                  or a negative number in case of error, generally from the errno.h set.\n     */\n    int (*authenticate)(struct fingerprint_device *dev, uint64_t operation_id, uint32_t gid);\n\n    /* Reserved for backward binary compatibility */\n    void *reserved[4];\n} fingerprint_device_t;\n\ntypedef struct fingerprint_module {\n    /**\n     * Common methods of the fingerprint module. This *must* be the first member\n     * of fingerprint_module as users of this structure will cast a hw_module_t\n     * to fingerprint_module pointer in contexts where it's known\n     * the hw_module_t references a fingerprint_module.\n     */\n    struct hw_module_t common;\n} fingerprint_module_t;\n\n#endif  /* ANDROID_INCLUDE_HARDWARE_FINGERPRINT_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/fused_location.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_FUSED_LOCATION_H\n#define ANDROID_INCLUDE_HARDWARE_FUSED_LOCATION_H\n\n#include <hardware/hardware.h>\n\n\n/**\n * This header file defines the interface of the Fused Location Provider.\n * Fused Location Provider is designed to fuse data from various sources\n * like GPS, Wifi, Cell, Sensors, Bluetooth etc to provide a fused location to the\n * upper layers. The advantage of doing fusion in hardware is power savings.\n * The goal is to do this without waking up the AP to get additional data.\n * The software implementation of FLP will decide when to use\n * the hardware fused location. Other location features like geofencing will\n * also be implemented using fusion in hardware.\n */\n__BEGIN_DECLS\n\n#define FLP_HEADER_VERSION          1\n#define FLP_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n#define FLP_DEVICE_API_VERSION_0_1  HARDWARE_DEVICE_API_VERSION_2(0, 1, FLP_HEADER_VERSION)\n\n/**\n * The id of this module\n */\n#define FUSED_LOCATION_HARDWARE_MODULE_ID \"flp\"\n\n/**\n * Name for the FLP location interface\n */\n#define FLP_LOCATION_INTERFACE     \"flp_location\"\n\n/**\n * Name for the FLP location interface\n */\n#define FLP_DIAGNOSTIC_INTERFACE     \"flp_diagnostic\"\n\n/**\n * Name for the FLP_Geofencing interface.\n */\n#define FLP_GEOFENCING_INTERFACE   \"flp_geofencing\"\n\n/**\n * Name for the FLP_device context interface.\n */\n#define FLP_DEVICE_CONTEXT_INTERFACE   \"flp_device_context\"\n\n/**\n * Constants to indicate the various subsystems\n * that will be used.\n */\n#define FLP_TECH_MASK_GNSS      (1U<<0)\n#define FLP_TECH_MASK_WIFI      (1U<<1)\n#define FLP_TECH_MASK_SENSORS   (1U<<2)\n#define FLP_TECH_MASK_CELL      (1U<<3)\n#define FLP_TECH_MASK_BLUETOOTH (1U<<4)\n\n/**\n * Set when your implementation can produce GNNS-derived locations,\n * for use with flp_capabilities_callback.\n *\n * GNNS is a required capability for a particular feature to be used\n * (batching or geofencing).  If not supported that particular feature\n * won't be used by the upper layer.\n */\n#define CAPABILITY_GNSS         (1U<<0)\n/**\n * Set when your implementation can produce WiFi-derived locations, for\n * use with flp_capabilities_callback.\n */\n#define CAPABILITY_WIFI         (1U<<1)\n/**\n * Set when your implementation can produce cell-derived locations, for\n * use with flp_capabilities_callback.\n */\n#define CAPABILITY_CELL         (1U<<3)\n\n/**\n * Status to return in flp_status_callback when your implementation transitions\n * from being unsuccessful in determining location to being successful.\n */\n#define FLP_STATUS_LOCATION_AVAILABLE         0\n/**\n * Status to return in flp_status_callback when your implementation transitions\n * from being successful in determining location to being unsuccessful.\n */\n#define FLP_STATUS_LOCATION_UNAVAILABLE       1\n\n/**\n * This constant is used with the batched locations\n * APIs. Batching is mandatory when FLP implementation\n * is supported. If the flag is set, the hardware implementation\n * will wake up the application processor when the FIFO is full,\n * If the flag is not set, the hardware implementation will drop\n * the oldest data when the FIFO is full.\n */\n#define FLP_BATCH_WAKEUP_ON_FIFO_FULL        0x0000001\n\n/**\n * While batching, the implementation should not call the\n * flp_location_callback on every location fix. However,\n * sometimes in high power mode, the system might need\n * a location callback every single time the location\n * fix has been obtained. This flag controls that option.\n * Its the responsibility of the upper layers (caller) to switch\n * it off, if it knows that the AP might go to sleep.\n * When this bit is on amidst a batching session, batching should\n * continue while location fixes are reported in real time.\n */\n#define FLP_BATCH_CALLBACK_ON_LOCATION_FIX   0x0000002\n\n/** Flags to indicate which values are valid in a FlpLocation. */\ntypedef uint16_t FlpLocationFlags;\n\n// IMPORTANT: Note that the following values must match\n// constants in the corresponding java file.\n\n/** FlpLocation has valid latitude and longitude. */\n#define FLP_LOCATION_HAS_LAT_LONG   (1U<<0)\n/** FlpLocation has valid altitude. */\n#define FLP_LOCATION_HAS_ALTITUDE   (1U<<1)\n/** FlpLocation has valid speed. */\n#define FLP_LOCATION_HAS_SPEED      (1U<<2)\n/** FlpLocation has valid bearing. */\n#define FLP_LOCATION_HAS_BEARING    (1U<<4)\n/** FlpLocation has valid accuracy. */\n#define FLP_LOCATION_HAS_ACCURACY   (1U<<8)\n\n\ntypedef int64_t FlpUtcTime;\n\n/** Represents a location. */\ntypedef struct {\n    /** set to sizeof(FlpLocation) */\n    size_t          size;\n\n    /** Flags associated with the location object. */\n    FlpLocationFlags flags;\n\n    /** Represents latitude in degrees. */\n    double          latitude;\n\n    /** Represents longitude in degrees. */\n    double          longitude;\n\n    /**\n     * Represents altitude in meters above the WGS 84 reference\n     * ellipsoid. */\n    double          altitude;\n\n    /** Represents speed in meters per second. */\n    float           speed;\n\n    /** Represents heading in degrees. */\n    float           bearing;\n\n    /** Represents expected accuracy in meters. */\n    float           accuracy;\n\n    /** Timestamp for the location fix. */\n    FlpUtcTime      timestamp;\n\n    /** Sources used, will be Bitwise OR of the FLP_TECH_MASK bits. */\n    uint32_t         sources_used;\n} FlpLocation;\n\ntypedef enum {\n    ASSOCIATE_JVM,\n    DISASSOCIATE_JVM,\n} ThreadEvent;\n\n/**\n *  Callback with location information.\n *  Can only be called from a thread associated to JVM using set_thread_event_cb.\n *  Parameters:\n *     num_locations is the number of batched locations available.\n *     location is the pointer to an array of pointers to location objects.\n */\ntypedef void (*flp_location_callback)(int32_t num_locations, FlpLocation** location);\n\n/**\n * Callback utility for acquiring a wakelock.\n * This can be used to prevent the CPU from suspending while handling FLP events.\n */\ntypedef void (*flp_acquire_wakelock)();\n\n/**\n * Callback utility for releasing the FLP wakelock.\n */\ntypedef void (*flp_release_wakelock)();\n\n/**\n * Callback for associating a thread that can call into the Java framework code.\n * This must be used to initialize any threads that report events up to the framework.\n * Return value:\n *      FLP_RESULT_SUCCESS on success.\n *      FLP_RESULT_ERROR if the association failed in the current thread.\n */\ntypedef int (*flp_set_thread_event)(ThreadEvent event);\n\n/**\n * Callback for technologies supported by this implementation.\n *\n * Parameters: capabilities is a bitmask of FLP_CAPABILITY_* values describing\n * which features your implementation supports.  You should support\n * CAPABILITY_GNSS at a minimum for your implementation to be utilized.  You can\n * return 0 in FlpGeofenceCallbacks to indicate you don't support geofencing,\n * or 0 in FlpCallbacks to indicate you don't support location batching.\n */\ntypedef void (*flp_capabilities_callback)(int capabilities);\n\n/**\n * Callback with status information on the ability to compute location.\n * To avoid waking up the application processor you should only send\n * changes in status (you shouldn't call this method twice in a row\n * with the same status value).  As a guideline you should not call this\n * more frequently then the requested batch period set with period_ns\n * in FlpBatchOptions.  For example if period_ns is set to 5 minutes and\n * the status changes many times in that interval, you should only report\n * one status change every 5 minutes.\n *\n * Parameters:\n *     status is one of FLP_STATUS_LOCATION_AVAILABLE\n *     or FLP_STATUS_LOCATION_UNAVAILABLE.\n */\ntypedef void (*flp_status_callback)(int32_t status);\n\n/** FLP callback structure. */\ntypedef struct {\n    /** set to sizeof(FlpCallbacks) */\n    size_t      size;\n    flp_location_callback location_cb;\n    flp_acquire_wakelock acquire_wakelock_cb;\n    flp_release_wakelock release_wakelock_cb;\n    flp_set_thread_event set_thread_event_cb;\n    flp_capabilities_callback flp_capabilities_cb;\n    flp_status_callback flp_status_cb;\n} FlpCallbacks;\n\n\n/** Options with the batching FLP APIs */\ntypedef struct {\n    /**\n     * Maximum power in mW that the underlying implementation\n     * can use for this batching call.\n     * If max_power_allocation_mW is 0, only fixes that are generated\n     * at no additional cost of power shall be reported.\n     */\n    double max_power_allocation_mW;\n\n    /** Bitwise OR of the FLP_TECH_MASKS to use */\n    uint32_t sources_to_use;\n\n    /**\n     * FLP_BATCH_WAKEUP_ON_FIFO_FULL - If set the hardware\n     * will wake up the AP when the buffer is full. If not set, the\n     * hardware will drop the oldest location object.\n     *\n     * FLP_BATCH_CALLBACK_ON_LOCATION_FIX - If set the location\n     * callback will be called every time there is a location fix.\n     * Its the responsibility of the upper layers (caller) to switch\n     * it off, if it knows that the AP might go to sleep. When this\n     * bit is on amidst a batching session, batching should continue\n     * while location fixes are reported in real time.\n     *\n     * Other flags to be bitwised ORed in the future.\n     */\n    uint32_t flags;\n\n    /**\n     * Frequency with which location needs to be batched in nano\n     * seconds.\n     */\n    int64_t period_ns;\n\n    /**\n     * The smallest displacement between reported locations in meters.\n     *\n     * If set to 0, then you should report locations at the requested\n     * interval even if the device is stationary.  If positive, you\n     * can use this parameter as a hint to save power (e.g. throttling\n     * location period if the user hasn't traveled close to the displacement\n     * threshold).  Even small positive values can be interpreted to mean\n     * that you don't have to compute location when the device is stationary.\n     *\n     * There is no need to filter location delivery based on this parameter.\n     * Locations can be delivered even if they have a displacement smaller than\n     * requested. This parameter can safely be ignored at the cost of potential\n     * power savings.\n     */\n    float smallest_displacement_meters;\n} FlpBatchOptions;\n\n#define FLP_RESULT_SUCCESS                       0\n#define FLP_RESULT_ERROR                        -1\n#define FLP_RESULT_INSUFFICIENT_MEMORY          -2\n#define FLP_RESULT_TOO_MANY_GEOFENCES           -3\n#define FLP_RESULT_ID_EXISTS                    -4\n#define FLP_RESULT_ID_UNKNOWN                   -5\n#define FLP_RESULT_INVALID_GEOFENCE_TRANSITION  -6\n\n/**\n * Represents the standard FLP interface.\n */\ntypedef struct {\n    /**\n     * set to sizeof(FlpLocationInterface)\n     */\n    size_t size;\n\n    /**\n     * Opens the interface and provides the callback routines\n     * to the implementation of this interface.  Once called you should respond\n     * by calling the flp_capabilities_callback in FlpCallbacks to\n     * specify the capabilities that your implementation supports.\n     */\n    int (*init)(FlpCallbacks* callbacks );\n\n    /**\n     * Return the batch size (in number of FlpLocation objects)\n     * available in the hardware.  Note, different HW implementations\n     * may have different sample sizes.  This shall return number\n     * of samples defined in the format of FlpLocation.\n     * This will be used by the upper layer, to decide on the batching\n     * interval and whether the AP should be woken up or not.\n     */\n    int (*get_batch_size)();\n\n    /**\n     * Start batching locations. This API is primarily used when the AP is\n     * asleep and the device can batch locations in the hardware.\n     *   flp_location_callback is used to return the locations. When the buffer\n     * is full and FLP_BATCH_WAKEUP_ON_FIFO_FULL is used, the AP is woken up.\n     * When the buffer is full and FLP_BATCH_WAKEUP_ON_FIFO_FULL is not set,\n     * the oldest location object is dropped. In this case the  AP will not be\n     * woken up. The upper layer will use get_batched_location\n     * API to explicitly ask for the location.\n     *   If FLP_BATCH_CALLBACK_ON_LOCATION_FIX is set, the implementation\n     * will call the flp_location_callback every single time there is a location\n     * fix. This overrides FLP_BATCH_WAKEUP_ON_FIFO_FULL flag setting.\n     * It's the responsibility of the upper layers (caller) to switch\n     * it off, if it knows that the AP might go to sleep. This is useful\n     * for nagivational applications when the system is in high power mode.\n     * Parameters:\n     *    id - Id for the request.\n     *    options - See FlpBatchOptions struct definition.\n     * Return value:\n     *    FLP_RESULT_SUCCESS on success, FLP_RESULT_INSUFFICIENT_MEMORY,\n     *    FLP_RESULT_ID_EXISTS, FLP_RESULT_ERROR on failure.\n     */\n    int (*start_batching)(int id, FlpBatchOptions* options);\n\n    /**\n     * Update FlpBatchOptions associated with a batching request.\n     * When a batching operation is in progress and a batching option\n     * such as FLP_BATCH_WAKEUP_ON_FIFO_FULL needs to be updated, this API\n     * will be used. For instance, this can happen when the AP is awake and\n     * the maps application is being used.\n     * Parameters:\n     *    id - Id of an existing batch request.\n     *    new_options - Updated FlpBatchOptions\n     * Return value:\n     *    FLP_RESULT_SUCCESS on success, FLP_RESULT_ID_UNKNOWN,\n     *    FLP_RESULT_ERROR on error.\n     */\n    int (*update_batching_options)(int id, FlpBatchOptions* new_options);\n\n    /**\n     * Stop batching.\n     * Parameters:\n     *    id - Id for the request.\n     * Return Value:\n     *    FLP_RESULT_SUCCESS on success, FLP_RESULT_ID_UNKNOWN or\n     *    FLP_RESULT_ERROR on failure.\n     */\n    int (*stop_batching)(int id);\n\n    /**\n     * Closes the interface. If any batch operations are in progress,\n     * they should be stopped.\n     */\n    void (*cleanup)();\n\n    /**\n     * Get the fused location that was batched.\n     *   flp_location_callback is used to return the location. The location object\n     * is dropped from the buffer only when the buffer is full. Do not remove it\n     * from the buffer just because it has been returned using the callback.\n     * In other words, when there is no new location object, two calls to\n     * get_batched_location(1) should return the same location object.\n     * Parameters:\n     *      last_n_locations - Number of locations to get. This can be one or many.\n     *      If the last_n_locations is 1, you get the latest location known to the\n     *      hardware.\n     */\n    void (*get_batched_location)(int last_n_locations);\n\n    /**\n     * Injects current location from another location provider\n     * latitude and longitude are measured in degrees\n     * expected accuracy is measured in meters\n     * Parameters:\n     *      location - The location object being injected.\n     * Return value: FLP_RESULT_SUCCESS or FLP_RESULT_ERROR.\n     */\n    int  (*inject_location)(FlpLocation* location);\n\n    /**\n     * Get a pointer to extension information.\n     */\n    const void* (*get_extension)(const char* name);\n\n    /**\n     * Retrieve all batched locations currently stored and clear the buffer.\n     * flp_location_callback MUST be called in response, even if there are\n     * no locations to flush (in which case num_locations should be 0).\n     * Subsequent calls to get_batched_location or flush_batched_locations\n     * should not return any of the locations returned in this call.\n     */\n    void (*flush_batched_locations)();\n} FlpLocationInterface;\n\nstruct flp_device_t {\n    struct hw_device_t common;\n\n    /**\n     * Get a handle to the FLP Interface.\n     */\n    const FlpLocationInterface* (*get_flp_interface)(struct flp_device_t* dev);\n};\n\n/**\n * Callback for reports diagnostic data into the Java framework code.\n*/\ntypedef void (*report_data)(char* data, int length);\n\n/**\n * FLP diagnostic callback structure.\n * Currently, not used - but this for future extension.\n */\ntypedef struct {\n    /** set to sizeof(FlpDiagnosticCallbacks) */\n    size_t      size;\n\n    flp_set_thread_event set_thread_event_cb;\n\n    /** reports diagnostic data into the Java framework code */\n    report_data data_cb;\n} FlpDiagnosticCallbacks;\n\n/** Extended interface for diagnostic support. */\ntypedef struct {\n    /** set to sizeof(FlpDiagnosticInterface) */\n    size_t          size;\n\n    /**\n     * Opens the diagnostic interface and provides the callback routines\n     * to the implemenation of this interface.\n     */\n    void  (*init)(FlpDiagnosticCallbacks* callbacks);\n\n    /**\n     * Injects diagnostic data into the FLP subsystem.\n     * Return 0 on success, -1 on error.\n     **/\n    int  (*inject_data)(char* data, int length );\n} FlpDiagnosticInterface;\n\n/**\n * Context setting information.\n * All these settings shall be injected to FLP HAL at FLP init time.\n * Following that, only the changed setting need to be re-injected\n * upon changes.\n */\n\n#define FLP_DEVICE_CONTEXT_GPS_ENABLED                     (1U<<0)\n#define FLP_DEVICE_CONTEXT_AGPS_ENABLED                    (1U<<1)\n#define FLP_DEVICE_CONTEXT_NETWORK_POSITIONING_ENABLED     (1U<<2)\n#define FLP_DEVICE_CONTEXT_WIFI_CONNECTIVITY_ENABLED       (1U<<3)\n#define FLP_DEVICE_CONTEXT_WIFI_POSITIONING_ENABLED        (1U<<4)\n#define FLP_DEVICE_CONTEXT_HW_NETWORK_POSITIONING_ENABLED  (1U<<5)\n#define FLP_DEVICE_CONTEXT_AIRPLANE_MODE_ON                (1U<<6)\n#define FLP_DEVICE_CONTEXT_DATA_ENABLED                    (1U<<7)\n#define FLP_DEVICE_CONTEXT_ROAMING_ENABLED                 (1U<<8)\n#define FLP_DEVICE_CONTEXT_CURRENTLY_ROAMING               (1U<<9)\n#define FLP_DEVICE_CONTEXT_SENSOR_ENABLED                  (1U<<10)\n#define FLP_DEVICE_CONTEXT_BLUETOOTH_ENABLED               (1U<<11)\n#define FLP_DEVICE_CONTEXT_CHARGER_ON                      (1U<<12)\n\n/** Extended interface for device context support. */\ntypedef struct {\n    /** set to sizeof(FlpDeviceContextInterface) */\n    size_t          size;\n\n    /**\n     * Injects debug data into the FLP subsystem.\n     * Return 0 on success, -1 on error.\n     **/\n    int  (*inject_device_context)(uint32_t enabledMask);\n} FlpDeviceContextInterface;\n\n\n/**\n * There are 3 states associated with a Geofence: Inside, Outside, Unknown.\n * There are 3 transitions: ENTERED, EXITED, UNCERTAIN.\n *\n * An example state diagram with confidence level: 95% and Unknown time limit\n * set as 30 secs is shown below. (confidence level and Unknown time limit are\n * explained latter)\n *                         ____________________________\n *                        |       Unknown (30 secs)   |\n *                         \"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n *                            ^ |                  |  ^\n *                   UNCERTAIN| |ENTERED     EXITED|  |UNCERTAIN\n *                            | v                  v  |\n *                        ________    EXITED     _________\n *                       | Inside | -----------> | Outside |\n *                       |        | <----------- |         |\n *                        \"\"\"\"\"\"\"\"    ENTERED    \"\"\"\"\"\"\"\"\"\n *\n * Inside state: We are 95% confident that the user is inside the geofence.\n * Outside state: We are 95% confident that the user is outside the geofence\n * Unknown state: Rest of the time.\n *\n * The Unknown state is better explained with an example:\n *\n *                            __________\n *                           |         c|\n *                           |  ___     |    _______\n *                           |  |a|     |   |   b   |\n *                           |  \"\"\"     |    \"\"\"\"\"\"\"\n *                           |          |\n *                            \"\"\"\"\"\"\"\"\"\"\n * In the diagram above, \"a\" and \"b\" are 2 geofences and \"c\" is the accuracy\n * circle reported by the FLP subsystem. Now with regard to \"b\", the system is\n * confident that the user is outside. But with regard to \"a\" is not confident\n * whether it is inside or outside the geofence. If the accuracy remains the\n * same for a sufficient period of time, the UNCERTAIN transition would be\n * triggered with the state set to Unknown. If the accuracy improves later, an\n * appropriate transition should be triggered.  This \"sufficient period of time\"\n * is defined by the parameter in the add_geofence_area API.\n *     In other words, Unknown state can be interpreted as a state in which the\n * FLP subsystem isn't confident enough that the user is either inside or\n * outside the Geofence. It moves to Unknown state only after the expiry of the\n * timeout.\n *\n * The geofence callback needs to be triggered for the ENTERED and EXITED\n * transitions, when the FLP system is confident that the user has entered\n * (Inside state) or exited (Outside state) the Geofence. An implementation\n * which uses a value of 95% as the confidence is recommended. The callback\n * should be triggered only for the transitions requested by the\n * add_geofence_area call.\n *\n * Even though the diagram and explanation talks about states and transitions,\n * the callee is only interested in the transistions. The states are mentioned\n * here for illustrative purposes.\n *\n * Startup Scenario: When the device boots up, if an application adds geofences,\n * and then we get an accurate FLP location fix, it needs to trigger the\n * appropriate (ENTERED or EXITED) transition for every Geofence it knows about.\n * By default, all the Geofences will be in the Unknown state.\n *\n * When the FLP system is unavailable, flp_geofence_status_callback should be\n * called to inform the upper layers of the same. Similarly, when it becomes\n * available the callback should be called. This is a global state while the\n * UNKNOWN transition described above is per geofence.\n *\n */\n#define FLP_GEOFENCE_TRANSITION_ENTERED     (1L<<0)\n#define FLP_GEOFENCE_TRANSITION_EXITED      (1L<<1)\n#define FLP_GEOFENCE_TRANSITION_UNCERTAIN   (1L<<2)\n\n#define FLP_GEOFENCE_MONITOR_STATUS_UNAVAILABLE (1L<<0)\n#define FLP_GEOFENCE_MONITOR_STATUS_AVAILABLE   (1L<<1)\n\n/**\n * The callback associated with the geofence.\n * Parameters:\n *      geofence_id - The id associated with the add_geofence_area.\n *      location    - The current location as determined by the FLP subsystem.\n *      transition  - Can be one of FLP_GEOFENCE_TRANSITION_ENTERED, FLP_GEOFENCE_TRANSITION_EXITED,\n *                    FLP_GEOFENCE_TRANSITION_UNCERTAIN.\n *      timestamp   - Timestamp when the transition was detected; -1 if not available.\n *      sources_used - Bitwise OR of FLP_TECH_MASK flags indicating which\n *                     subsystems were used.\n *\n * The callback should only be called when the caller is interested in that\n * particular transition. For instance, if the caller is interested only in\n * ENTERED transition, then the callback should NOT be called with the EXITED\n * transition.\n *\n * IMPORTANT: If a transition is triggered resulting in this callback, the\n * subsystem will wake up the application processor, if its in suspend state.\n */\ntypedef void (*flp_geofence_transition_callback) (int32_t geofence_id,  FlpLocation* location,\n        int32_t transition, FlpUtcTime timestamp, uint32_t sources_used);\n\n/**\n * The callback associated with the availablity of one the sources used for geofence\n * monitoring by the FLP sub-system For example, if the GPS system determines that it cannot\n * monitor geofences because of lack of reliability or unavailability of the GPS signals,\n * it will call this callback with FLP_GEOFENCE_MONITOR_STATUS_UNAVAILABLE parameter and the\n * source set to FLP_TECH_MASK_GNSS.\n *\n * Parameters:\n *  status - FLP_GEOFENCE_MONITOR_STATUS_UNAVAILABLE or FLP_GEOFENCE_MONITOR_STATUS_AVAILABLE.\n *  source - One of the FLP_TECH_MASKS\n *  last_location - Last known location.\n */\ntypedef void (*flp_geofence_monitor_status_callback) (int32_t status, uint32_t source,\n                                                      FlpLocation* last_location);\n\n/**\n * The callback associated with the add_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * result - FLP_RESULT_SUCCESS\n *          FLP_RESULT_ERROR_TOO_MANY_GEOFENCES  - geofence limit has been reached.\n *          FLP_RESULT_ID_EXISTS  - geofence with id already exists\n *          FLP_RESULT_INVALID_GEOFENCE_TRANSITION - the monitorTransition contains an\n *              invalid transition\n *          FLP_RESULT_ERROR - for other errors.\n */\ntypedef void (*flp_geofence_add_callback) (int32_t geofence_id, int32_t result);\n\n/**\n * The callback associated with the remove_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * result - FLP_RESULT_SUCCESS\n *          FLP_RESULT_ID_UNKNOWN - for invalid id\n *          FLP_RESULT_ERROR for others.\n */\ntypedef void (*flp_geofence_remove_callback) (int32_t geofence_id, int32_t result);\n\n\n/**\n * The callback associated with the pause_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * result - FLP_RESULT_SUCCESS\n *          FLP_RESULT__ID_UNKNOWN - for invalid id\n *          FLP_RESULT_INVALID_TRANSITION -\n *                    when monitor_transitions is invalid\n *          FLP_RESULT_ERROR for others.\n */\ntypedef void (*flp_geofence_pause_callback) (int32_t geofence_id, int32_t result);\n\n/**\n * The callback associated with the resume_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * result - FLP_RESULT_SUCCESS\n *          FLP_RESULT_ID_UNKNOWN - for invalid id\n *          FLP_RESULT_ERROR for others.\n */\ntypedef void (*flp_geofence_resume_callback) (int32_t geofence_id, int32_t result);\n\ntypedef struct {\n    /** set to sizeof(FlpGeofenceCallbacks) */\n    size_t size;\n    flp_geofence_transition_callback geofence_transition_callback;\n    flp_geofence_monitor_status_callback geofence_status_callback;\n    flp_geofence_add_callback geofence_add_callback;\n    flp_geofence_remove_callback geofence_remove_callback;\n    flp_geofence_pause_callback geofence_pause_callback;\n    flp_geofence_resume_callback geofence_resume_callback;\n    flp_set_thread_event set_thread_event_cb;\n    flp_capabilities_callback flp_capabilities_cb;\n} FlpGeofenceCallbacks;\n\n\n/** Type of geofence */\ntypedef enum {\n    TYPE_CIRCLE = 0,\n} GeofenceType;\n\n/** Circular geofence is represented by lat / long / radius */\ntypedef struct {\n    double latitude;\n    double longitude;\n    double radius_m;\n} GeofenceCircle;\n\n/** Represents the type of geofence and data */\ntypedef struct {\n    GeofenceType type;\n    union {\n        GeofenceCircle circle;\n    } geofence;\n} GeofenceData;\n\n/** Geofence Options */\ntypedef struct {\n   /**\n    * The current state of the geofence. For example, if\n    * the system already knows that the user is inside the geofence,\n    * this will be set to FLP_GEOFENCE_TRANSITION_ENTERED. In most cases, it\n    * will be FLP_GEOFENCE_TRANSITION_UNCERTAIN. */\n    int last_transition;\n\n   /**\n    * Transitions to monitor. Bitwise OR of\n    * FLP_GEOFENCE_TRANSITION_ENTERED, FLP_GEOFENCE_TRANSITION_EXITED and\n    * FLP_GEOFENCE_TRANSITION_UNCERTAIN.\n    */\n    int monitor_transitions;\n\n   /**\n    * Defines the best-effort description\n    * of how soon should the callback be called when the transition\n    * associated with the Geofence is triggered. For instance, if set\n    * to 1000 millseconds with FLP_GEOFENCE_TRANSITION_ENTERED, the callback\n    * should be called 1000 milliseconds within entering the geofence.\n    * This parameter is defined in milliseconds.\n    * NOTE: This is not to be confused with the rate that the GPS is\n    * polled at. It is acceptable to dynamically vary the rate of\n    * sampling the GPS for power-saving reasons; thus the rate of\n    * sampling may be faster or slower than this.\n    */\n    int notification_responsivenes_ms;\n\n   /**\n    * The time limit after which the UNCERTAIN transition\n    * should be triggered. This paramter is defined in milliseconds.\n    */\n    int unknown_timer_ms;\n\n    /**\n     * The sources to use for monitoring geofences. Its a BITWISE-OR\n     * of FLP_TECH_MASK flags.\n     */\n    uint32_t sources_to_use;\n} GeofenceOptions;\n\n/** Geofence struct */\ntypedef struct {\n    int32_t geofence_id;\n    GeofenceData* data;\n    GeofenceOptions* options;\n} Geofence;\n\n/** Extended interface for FLP_Geofencing support */\ntypedef struct {\n   /** set to sizeof(FlpGeofencingInterface) */\n   size_t          size;\n\n   /**\n    * Opens the geofence interface and provides the callback routines\n    * to the implemenation of this interface.  Once called you should respond\n    * by calling the flp_capabilities_callback in FlpGeofenceCallbacks to\n    * specify the capabilities that your implementation supports.\n    */\n   void  (*init)( FlpGeofenceCallbacks* callbacks );\n\n   /**\n    * Add a list of geofences.\n    * Parameters:\n    *     number_of_geofences - The number of geofences that needed to be added.\n    *     geofences - Pointer to array of pointers to Geofence structure.\n    */\n   void (*add_geofences) (int32_t number_of_geofences, Geofence** geofences);\n\n   /**\n    * Pause monitoring a particular geofence.\n    * Parameters:\n    *   geofence_id - The id for the geofence.\n    */\n   void (*pause_geofence) (int32_t geofence_id);\n\n   /**\n    * Resume monitoring a particular geofence.\n    * Parameters:\n    *   geofence_id - The id for the geofence.\n    *   monitor_transitions - Which transitions to monitor. Bitwise OR of\n    *       FLP_GEOFENCE_TRANSITION_ENTERED, FLP_GEOFENCE_TRANSITION_EXITED and\n    *       FLP_GEOFENCE_TRANSITION_UNCERTAIN.\n    *       This supersedes the value associated provided in the\n    *       add_geofence_area call.\n    */\n   void (*resume_geofence) (int32_t geofence_id, int monitor_transitions);\n\n   /**\n    * Modify a particular geofence option.\n    * Parameters:\n    *    geofence_id - The id for the geofence.\n    *    options - Various options associated with the geofence. See\n    *        GeofenceOptions structure for details.\n    */\n   void (*modify_geofence_option) (int32_t geofence_id, GeofenceOptions* options);\n\n   /**\n    * Remove a list of geofences. After the function returns, no notifications\n    * should be sent.\n    * Parameter:\n    *     number_of_geofences - The number of geofences that needed to be added.\n    *     geofence_id - Pointer to array of geofence_ids to be removed.\n    */\n   void (*remove_geofences) (int32_t number_of_geofences, int32_t* geofence_id);\n} FlpGeofencingInterface;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_HARDWARE_FLP_H */\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/gatekeeper.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_HARDWARE_GATEKEEPER_H\n#define ANDROID_HARDWARE_GATEKEEPER_H\n\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define GATEKEEPER_HARDWARE_MODULE_ID \"gatekeeper\"\n\n#define GATEKEEPER_MODULE_API_VERSION_0_1 HARDWARE_MODULE_API_VERSION(0, 1)\n\n#define HARDWARE_GATEKEEPER \"gatekeeper\"\n\nstruct gatekeeper_module {\n    /**\n     * Comon methods of the gatekeeper module. This *must* be the first member of\n     * gatekeeper_module as users of this structure will cast a hw_module_t to\n     * a gatekeeper_module pointer in the appropriate context.\n     */\n    hw_module_t common;\n};\n\nstruct gatekeeper_device {\n    /**\n     * Common methods of the gatekeeper device. As above, this must be the first\n     * member of keymaster_device.\n     */\n    hw_device_t common;\n\n    /**\n     * Enrolls desired_password, which should be derived from a user selected pin or password,\n     * with the authentication factor private key used only for enrolling authentication\n     * factor data.\n     *\n     * If there was already a password enrolled, it should be provided in\n     * current_password_handle, along with the current password in current_password\n     * that should validate against current_password_handle.\n     *\n     * Parameters:\n     * - dev: pointer to gatekeeper_device acquired via calls to gatekeeper_open\n     * - uid: the Android user identifier\n     *\n     * - current_password_handle: the currently enrolled password handle the user\n     *   wants to replace. May be null if there's no currently enrolled password.\n     * - current_password_handle_length: the length in bytes of the buffer pointed\n     *   at by current_password_handle. Must be 0 if current_password_handle is NULL.\n     *\n     * - current_password: the user's current password in plain text. If presented,\n     *   it MUST verify against current_password_handle.\n     * - current_password_length: the size in bytes of the buffer pointed at by\n     *   current_password. Must be 0 if the current_password is NULL.\n     *\n     * - desired_password: the new password the user wishes to enroll in plain-text.\n     *   Cannot be NULL.\n     * - desired_password_length: the length in bytes of the buffer pointed at by\n     *   desired_password.\n     *\n     * - enrolled_password_handle: on success, a buffer will be allocated with the\n     *   new password handle referencing the password provided in desired_password.\n     *   This buffer can be used on subsequent calls to enroll or verify.\n     *   The caller is responsible for deallocating this buffer via a call to delete[]\n     * - enrolled_password_handle_length: pointer to the length in bytes of the buffer allocated\n     *   by this function and pointed to by *enrolled_password_handle_length.\n     *\n     * Returns:\n     * - 0 on success\n     * - An error code < 0 on failure, or\n     * - A timeout value T > 0 if the call should not be re-attempted until T milliseconds\n     *   have elapsed.\n     *\n     * On error, enrolled_password_handle will not be allocated.\n     */\n    int (*enroll)(const struct gatekeeper_device *dev, uint32_t uid,\n            const uint8_t *current_password_handle, uint32_t current_password_handle_length,\n            const uint8_t *current_password, uint32_t current_password_length,\n            const uint8_t *desired_password, uint32_t desired_password_length,\n            uint8_t **enrolled_password_handle, uint32_t *enrolled_password_handle_length);\n\n    /**\n     * Verifies provided_password matches enrolled_password_handle.\n     *\n     * Implementations of this module may retain the result of this call\n     * to attest to the recency of authentication.\n     *\n     * On success, writes the address of a verification token to auth_token,\n     * usable to attest password verification to other trusted services. Clients\n     * may pass NULL for this value.\n     *\n     * Parameters:\n     * - dev: pointer to gatekeeper_device acquired via calls to gatekeeper_open\n     * - uid: the Android user identifier\n     *\n     * - challenge: An optional challenge to authenticate against, or 0. Used when a separate\n     *              authenticator requests password verification, or for transactional\n     *              password authentication.\n     *\n     * - enrolled_password_handle: the currently enrolled password handle that the\n     *   user wishes to verify against.\n     * - enrolled_password_handle_length: the length in bytes of the buffer pointed\n     *   to by enrolled_password_handle\n     *\n     * - provided_password: the plaintext password to be verified against the\n     *   enrolled_password_handle\n     * - provided_password_length: the length in bytes of the buffer pointed to by\n     *   provided_password\n     *\n     * - auth_token: on success, a buffer containing the authentication token\n     *   resulting from this verification is assigned to *auth_token. The caller\n     *   is responsible for deallocating this memory via a call to delete[]\n     * - auth_token_length: on success, the length in bytes of the authentication\n     *   token assigned to *auth_token will be assigned to *auth_token_length\n     *\n     * - request_reenroll: a request to the upper layers to re-enroll the verified\n     *   password due to a version change. Not set if verification fails.\n     *\n     * Returns:\n     * - 0 on success\n     * - An error code < 0 on failure, or\n     * - A timeout value T > 0 if the call should not be re-attempted until T milliseconds\n     *   have elapsed.\n     * On error, auth token will not be allocated\n     */\n    int (*verify)(const struct gatekeeper_device *dev, uint32_t uid, uint64_t challenge,\n            const uint8_t *enrolled_password_handle, uint32_t enrolled_password_handle_length,\n            const uint8_t *provided_password, uint32_t provided_password_length,\n            uint8_t **auth_token, uint32_t *auth_token_length, bool *request_reenroll);\n\n    /*\n     * Deletes the enrolled_password_handle associated wth the uid. Once deleted\n     * the user cannot be verified anymore.\n     * This function is optional and should be set to NULL if it is not implemented.\n     *\n     * Parameters\n     * - dev: pointer to gatekeeper_device acquired via calls to gatekeeper_open\n     * - uid: the Android user identifier\n     *\n     * Returns:\n     * - 0 on success\n     * - An error code < 0 on failure\n     */\n    int (*delete_user)(const struct gatekeeper_device *dev,  uint32_t uid);\n\n    /*\n     * Deletes all the enrolled_password_handles for all uid's. Once called,\n     * no users will be enrolled on the device.\n     * This function is optional and should be set to NULL if it is not implemented.\n     *\n     * Parameters\n     * - dev: pointer to gatekeeper_device acquired via calls to gatekeeper_open\n     *\n     * Returns:\n     * - 0 on success\n     * - An error code < 0 on failure\n     */\n    int (*delete_all_users)(const struct gatekeeper_device *dev);\n};\n\ntypedef struct gatekeeper_device gatekeeper_device_t;\n\nstatic inline int gatekeeper_open(const struct hw_module_t *module,\n        gatekeeper_device_t **device) {\n    return module->methods->open(module, HARDWARE_GATEKEEPER,\n            (struct hw_device_t **) device);\n}\n\nstatic inline int gatekeeper_close(gatekeeper_device_t *device) {\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif // ANDROID_HARDWARE_GATEKEEPER_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/gps.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_GPS_H\n#define ANDROID_INCLUDE_HARDWARE_GPS_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <pthread.h>\n#include <sys/socket.h>\n#include <stdbool.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define GPS_HARDWARE_MODULE_ID \"gps\"\n\n\n/** Milliseconds since January 1, 1970 */\ntypedef int64_t GpsUtcTime;\n\n/** Maximum number of SVs for gps_sv_status_callback(). */\n#define GPS_MAX_SVS 32\n\n/** Maximum number of Measurements in gps_measurement_callback(). */\n#define GPS_MAX_MEASUREMENT   32\n\n/** Requested operational mode for GPS operation. */\ntypedef uint32_t GpsPositionMode;\n// IMPORTANT: Note that the following values must match\n// constants in GpsLocationProvider.java.\n/** Mode for running GPS standalone (no assistance). */\n#define GPS_POSITION_MODE_STANDALONE    0\n/** AGPS MS-Based mode. */\n#define GPS_POSITION_MODE_MS_BASED      1\n/**\n * AGPS MS-Assisted mode. This mode is not maintained by the platform anymore.\n * It is strongly recommended to use GPS_POSITION_MODE_MS_BASE instead.\n */\n#define GPS_POSITION_MODE_MS_ASSISTED   2\n\n/** Requested recurrence mode for GPS operation. */\ntypedef uint32_t GpsPositionRecurrence;\n// IMPORTANT: Note that the following values must match\n// constants in GpsLocationProvider.java.\n/** Receive GPS fixes on a recurring basis at a specified period. */\n#define GPS_POSITION_RECURRENCE_PERIODIC    0\n/** Request a single shot GPS fix. */\n#define GPS_POSITION_RECURRENCE_SINGLE      1\n\n/** GPS status event values. */\ntypedef uint16_t GpsStatusValue;\n// IMPORTANT: Note that the following values must match\n// constants in GpsLocationProvider.java.\n/** GPS status unknown. */\n#define GPS_STATUS_NONE             0\n/** GPS has begun navigating. */\n#define GPS_STATUS_SESSION_BEGIN    1\n/** GPS has stopped navigating. */\n#define GPS_STATUS_SESSION_END      2\n/** GPS has powered on but is not navigating. */\n#define GPS_STATUS_ENGINE_ON        3\n/** GPS is powered off. */\n#define GPS_STATUS_ENGINE_OFF       4\n\n/** Flags to indicate which values are valid in a GpsLocation. */\ntypedef uint16_t GpsLocationFlags;\n// IMPORTANT: Note that the following values must match\n// constants in GpsLocationProvider.java.\n/** GpsLocation has valid latitude and longitude. */\n#define GPS_LOCATION_HAS_LAT_LONG   0x0001\n/** GpsLocation has valid altitude. */\n#define GPS_LOCATION_HAS_ALTITUDE   0x0002\n/** GpsLocation has valid speed. */\n#define GPS_LOCATION_HAS_SPEED      0x0004\n/** GpsLocation has valid bearing. */\n#define GPS_LOCATION_HAS_BEARING    0x0008\n/** GpsLocation has valid accuracy. */\n#define GPS_LOCATION_HAS_ACCURACY   0x0010\n\n/** Flags for the gps_set_capabilities callback. */\n\n/** GPS HAL schedules fixes for GPS_POSITION_RECURRENCE_PERIODIC mode.\n    If this is not set, then the framework will use 1000ms for min_interval\n    and will start and call start() and stop() to schedule the GPS.\n */\n#define GPS_CAPABILITY_SCHEDULING       0x0000001\n/** GPS supports MS-Based AGPS mode */\n#define GPS_CAPABILITY_MSB              0x0000002\n/** GPS supports MS-Assisted AGPS mode */\n#define GPS_CAPABILITY_MSA              0x0000004\n/** GPS supports single-shot fixes */\n#define GPS_CAPABILITY_SINGLE_SHOT      0x0000008\n/** GPS supports on demand time injection */\n#define GPS_CAPABILITY_ON_DEMAND_TIME   0x0000010\n/** GPS supports Geofencing  */\n#define GPS_CAPABILITY_GEOFENCING       0x0000020\n/** GPS supports Measurements */\n#define GPS_CAPABILITY_MEASUREMENTS     0x0000040\n/** GPS supports Navigation Messages */\n#define GPS_CAPABILITY_NAV_MESSAGES     0x0000080\n\n/** Flags used to specify which aiding data to delete\n    when calling delete_aiding_data(). */\ntypedef uint16_t GpsAidingData;\n// IMPORTANT: Note that the following values must match\n// constants in GpsLocationProvider.java.\n#define GPS_DELETE_EPHEMERIS        0x0001\n#define GPS_DELETE_ALMANAC          0x0002\n#define GPS_DELETE_POSITION         0x0004\n#define GPS_DELETE_TIME             0x0008\n#define GPS_DELETE_IONO             0x0010\n#define GPS_DELETE_UTC              0x0020\n#define GPS_DELETE_HEALTH           0x0040\n#define GPS_DELETE_SVDIR            0x0080\n#define GPS_DELETE_SVSTEER          0x0100\n#define GPS_DELETE_SADATA           0x0200\n#define GPS_DELETE_RTI              0x0400\n#define GPS_DELETE_CELLDB_INFO      0x8000\n#define GPS_DELETE_ALL              0xFFFF\n\n/** AGPS type */\ntypedef uint16_t AGpsType;\n#define AGPS_TYPE_SUPL          1\n#define AGPS_TYPE_C2K           2\n\ntypedef uint16_t AGpsSetIDType;\n#define AGPS_SETID_TYPE_NONE    0\n#define AGPS_SETID_TYPE_IMSI    1\n#define AGPS_SETID_TYPE_MSISDN  2\n\ntypedef uint16_t ApnIpType;\n#define APN_IP_INVALID          0\n#define APN_IP_IPV4             1\n#define APN_IP_IPV6             2\n#define APN_IP_IPV4V6           3\n\n/**\n * String length constants\n */\n#define GPS_NI_SHORT_STRING_MAXLEN      256\n#define GPS_NI_LONG_STRING_MAXLEN       2048\n\n/**\n * GpsNiType constants\n */\ntypedef uint32_t GpsNiType;\n#define GPS_NI_TYPE_VOICE              1\n#define GPS_NI_TYPE_UMTS_SUPL          2\n#define GPS_NI_TYPE_UMTS_CTRL_PLANE    3\n\n/**\n * GpsNiNotifyFlags constants\n */\ntypedef uint32_t GpsNiNotifyFlags;\n/** NI requires notification */\n#define GPS_NI_NEED_NOTIFY          0x0001\n/** NI requires verification */\n#define GPS_NI_NEED_VERIFY          0x0002\n/** NI requires privacy override, no notification/minimal trace */\n#define GPS_NI_PRIVACY_OVERRIDE     0x0004\n\n/**\n * GPS NI responses, used to define the response in\n * NI structures\n */\ntypedef int GpsUserResponseType;\n#define GPS_NI_RESPONSE_ACCEPT         1\n#define GPS_NI_RESPONSE_DENY           2\n#define GPS_NI_RESPONSE_NORESP         3\n\n/**\n * NI data encoding scheme\n */\ntypedef int GpsNiEncodingType;\n#define GPS_ENC_NONE                   0\n#define GPS_ENC_SUPL_GSM_DEFAULT       1\n#define GPS_ENC_SUPL_UTF8              2\n#define GPS_ENC_SUPL_UCS2              3\n#define GPS_ENC_UNKNOWN                -1\n\n/** AGPS status event values. */\ntypedef uint16_t AGpsStatusValue;\n/** GPS requests data connection for AGPS. */\n#define GPS_REQUEST_AGPS_DATA_CONN  1\n/** GPS releases the AGPS data connection. */\n#define GPS_RELEASE_AGPS_DATA_CONN  2\n/** AGPS data connection initiated */\n#define GPS_AGPS_DATA_CONNECTED     3\n/** AGPS data connection completed */\n#define GPS_AGPS_DATA_CONN_DONE     4\n/** AGPS data connection failed */\n#define GPS_AGPS_DATA_CONN_FAILED   5\n\n#define AGPS_REF_LOCATION_TYPE_GSM_CELLID   1\n#define AGPS_REF_LOCATION_TYPE_UMTS_CELLID  2\n#define AGPS_REG_LOCATION_TYPE_MAC          3\n\n/** Network types for update_network_state \"type\" parameter */\n#define AGPS_RIL_NETWORK_TYPE_MOBILE        0\n#define AGPS_RIL_NETWORK_TYPE_WIFI          1\n#define AGPS_RIL_NETWORK_TYPE_MOBILE_MMS    2\n#define AGPS_RIL_NETWORK_TYPE_MOBILE_SUPL   3\n#define AGPS_RIL_NETWORK_TTYPE_MOBILE_DUN   4\n#define AGPS_RIL_NETWORK_TTYPE_MOBILE_HIPRI 5\n#define AGPS_RIL_NETWORK_TTYPE_WIMAX        6\n\n/**\n * Flags to indicate what fields in GpsClock are valid.\n */\ntypedef uint16_t GpsClockFlags;\n/** A valid 'leap second' is stored in the data structure. */\n#define GPS_CLOCK_HAS_LEAP_SECOND               (1<<0)\n/** A valid 'time uncertainty' is stored in the data structure. */\n#define GPS_CLOCK_HAS_TIME_UNCERTAINTY          (1<<1)\n/** A valid 'full bias' is stored in the data structure. */\n#define GPS_CLOCK_HAS_FULL_BIAS                 (1<<2)\n/** A valid 'bias' is stored in the data structure. */\n#define GPS_CLOCK_HAS_BIAS                      (1<<3)\n/** A valid 'bias uncertainty' is stored in the data structure. */\n#define GPS_CLOCK_HAS_BIAS_UNCERTAINTY          (1<<4)\n/** A valid 'drift' is stored in the data structure. */\n#define GPS_CLOCK_HAS_DRIFT                     (1<<5)\n/** A valid 'drift uncertainty' is stored in the data structure. */\n#define GPS_CLOCK_HAS_DRIFT_UNCERTAINTY         (1<<6)\n\n/**\n * Enumeration of the available values for the GPS Clock type.\n */\ntypedef uint8_t GpsClockType;\n/** The type is not available ot it is unknown. */\n#define GPS_CLOCK_TYPE_UNKNOWN                  0\n/** The source of the time value reported by GPS clock is the local hardware clock. */\n#define GPS_CLOCK_TYPE_LOCAL_HW_TIME            1\n/**\n * The source of the time value reported by GPS clock is the GPS time derived from satellites\n * (epoch = Jan 6, 1980)\n */\n#define GPS_CLOCK_TYPE_GPS_TIME                 2\n\n/**\n * Flags to indicate what fields in GpsMeasurement are valid.\n */\ntypedef uint32_t GpsMeasurementFlags;\n/** A valid 'snr' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_SNR                               (1<<0)\n/** A valid 'elevation' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_ELEVATION                         (1<<1)\n/** A valid 'elevation uncertainty' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_ELEVATION_UNCERTAINTY             (1<<2)\n/** A valid 'azimuth' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_AZIMUTH                           (1<<3)\n/** A valid 'azimuth uncertainty' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_AZIMUTH_UNCERTAINTY               (1<<4)\n/** A valid 'pseudorange' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_PSEUDORANGE                       (1<<5)\n/** A valid 'pseudorange uncertainty' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_PSEUDORANGE_UNCERTAINTY           (1<<6)\n/** A valid 'code phase' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_CODE_PHASE                        (1<<7)\n/** A valid 'code phase uncertainty' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_CODE_PHASE_UNCERTAINTY            (1<<8)\n/** A valid 'carrier frequency' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_CARRIER_FREQUENCY                 (1<<9)\n/** A valid 'carrier cycles' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_CARRIER_CYCLES                    (1<<10)\n/** A valid 'carrier phase' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_CARRIER_PHASE                     (1<<11)\n/** A valid 'carrier phase uncertainty' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_CARRIER_PHASE_UNCERTAINTY         (1<<12)\n/** A valid 'bit number' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_BIT_NUMBER                        (1<<13)\n/** A valid 'time from last bit' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_TIME_FROM_LAST_BIT                (1<<14)\n/** A valid 'doppler shift' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_DOPPLER_SHIFT                     (1<<15)\n/** A valid 'doppler shift uncertainty' is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_DOPPLER_SHIFT_UNCERTAINTY         (1<<16)\n/** A valid 'used in fix' flag is stored in the data structure. */\n#define GPS_MEASUREMENT_HAS_USED_IN_FIX                       (1<<17)\n/** The value of 'pseudorange rate' is uncorrected. */\n#define GPS_MEASUREMENT_HAS_UNCORRECTED_PSEUDORANGE_RATE      (1<<18)\n\n/**\n * Enumeration of the available values for the GPS Measurement's loss of lock.\n */\ntypedef uint8_t GpsLossOfLock;\n/** The indicator is not available or it is unknown. */\n#define GPS_LOSS_OF_LOCK_UNKNOWN                            0\n/** The measurement does not present any indication of loss of lock. */\n#define GPS_LOSS_OF_LOCK_OK                                 1\n/** Loss of lock between previous and current observation: cycle slip possible. */\n#define GPS_LOSS_OF_LOCK_CYCLE_SLIP                         2\n\n/**\n * Enumeration of available values for the GPS Measurement's multipath indicator.\n */\ntypedef uint8_t GpsMultipathIndicator;\n/** The indicator is not available or unknown. */\n#define GPS_MULTIPATH_INDICATOR_UNKNOWN                 0\n/** The measurement has been indicated to use multipath. */\n#define GPS_MULTIPATH_INDICATOR_DETECTED                1\n/** The measurement has been indicated Not to use multipath. */\n#define GPS_MULTIPATH_INDICATOR_NOT_USED                2\n\n/**\n * Flags indicating the GPS measurement state.\n * The expected behavior here is for GPS HAL to set all the flags that applies. For\n * example, if the state for a satellite is only C/A code locked and bit synchronized,\n * and there is still millisecond ambiguity, the state should be set as:\n * GPS_MEASUREMENT_STATE_CODE_LOCK|GPS_MEASUREMENT_STATE_BIT_SYNC|GPS_MEASUREMENT_STATE_MSEC_AMBIGUOUS\n * If GPS is still searching for a satellite, the corresponding state should be set to\n * GPS_MEASUREMENT_STATE_UNKNOWN(0).\n */\ntypedef uint16_t GpsMeasurementState;\n#define GPS_MEASUREMENT_STATE_UNKNOWN                   0\n#define GPS_MEASUREMENT_STATE_CODE_LOCK             (1<<0)\n#define GPS_MEASUREMENT_STATE_BIT_SYNC              (1<<1)\n#define GPS_MEASUREMENT_STATE_SUBFRAME_SYNC         (1<<2)\n#define GPS_MEASUREMENT_STATE_TOW_DECODED           (1<<3)\n#define GPS_MEASUREMENT_STATE_MSEC_AMBIGUOUS        (1<<4)\n\n/**\n * Flags indicating the Accumulated Delta Range's states.\n */\ntypedef uint16_t GpsAccumulatedDeltaRangeState;\n#define GPS_ADR_STATE_UNKNOWN                       0\n#define GPS_ADR_STATE_VALID                     (1<<0)\n#define GPS_ADR_STATE_RESET                     (1<<1)\n#define GPS_ADR_STATE_CYCLE_SLIP                (1<<2)\n\n/**\n * Enumeration of available values to indicate the available GPS Navigation message types.\n */\ntypedef uint8_t GpsNavigationMessageType;\n/** The message type is unknown. */\n#define GPS_NAVIGATION_MESSAGE_TYPE_UNKNOWN         0\n/** L1 C/A message contained in the structure.  */\n#define GPS_NAVIGATION_MESSAGE_TYPE_L1CA            1\n/** L2-CNAV message contained in the structure. */\n#define GPS_NAVIGATION_MESSAGE_TYPE_L2CNAV          2\n/** L5-CNAV message contained in the structure. */\n#define GPS_NAVIGATION_MESSAGE_TYPE_L5CNAV          3\n/** CNAV-2 message contained in the structure. */\n#define GPS_NAVIGATION_MESSAGE_TYPE_CNAV2           4\n\n/**\n * Status of Navigation Message\n * When a message is received properly without any parity error in its navigation words, the\n * status should be set to NAV_MESSAGE_STATUS_PARITY_PASSED. But if a message is received\n * with words that failed parity check, but GPS is able to correct those words, the status\n * should be set to NAV_MESSAGE_STATUS_PARITY_REBUILT.\n * No need to send any navigation message that contains words with parity error and cannot be\n * corrected.\n */\ntypedef uint16_t NavigationMessageStatus;\n#define NAV_MESSAGE_STATUS_UNKONW              0\n#define NAV_MESSAGE_STATUS_PARITY_PASSED   (1<<0)\n#define NAV_MESSAGE_STATUS_PARITY_REBUILT  (1<<1)\n\n/**\n * Name for the GPS XTRA interface.\n */\n#define GPS_XTRA_INTERFACE      \"gps-xtra\"\n\n/**\n * Name for the GPS DEBUG interface.\n */\n#define GPS_DEBUG_INTERFACE      \"gps-debug\"\n\n/**\n * Name for the AGPS interface.\n */\n#define AGPS_INTERFACE      \"agps\"\n\n/**\n * Name of the Supl Certificate interface.\n */\n#define SUPL_CERTIFICATE_INTERFACE  \"supl-certificate\"\n\n/**\n * Name for NI interface\n */\n#define GPS_NI_INTERFACE \"gps-ni\"\n\n/**\n * Name for the AGPS-RIL interface.\n */\n#define AGPS_RIL_INTERFACE      \"agps_ril\"\n\n/**\n * Name for the GPS_Geofencing interface.\n */\n#define GPS_GEOFENCING_INTERFACE   \"gps_geofencing\"\n\n/**\n * Name of the GPS Measurements interface.\n */\n#define GPS_MEASUREMENT_INTERFACE   \"gps_measurement\"\n\n/**\n * Name of the GPS navigation message interface.\n */\n#define GPS_NAVIGATION_MESSAGE_INTERFACE     \"gps_navigation_message\"\n\n/**\n * Name of the GNSS/GPS configuration interface.\n */\n#define GNSS_CONFIGURATION_INTERFACE     \"gnss_configuration\"\n\n\n/** Represents a location. */\ntypedef struct {\n    /** set to sizeof(GpsLocation) */\n    size_t          size;\n    /** Contains GpsLocationFlags bits. */\n    uint16_t        flags;\n    /** Represents latitude in degrees. */\n    double          latitude;\n    /** Represents longitude in degrees. */\n    double          longitude;\n    /** Represents altitude in meters above the WGS 84 reference\n     * ellipsoid. */\n    double          altitude;\n    /** Represents speed in meters per second. */\n    float           speed;\n    /** Represents heading in degrees. */\n    float           bearing;\n    /** Represents expected accuracy in meters. */\n    float           accuracy;\n    /** Timestamp for the location fix. */\n    GpsUtcTime      timestamp;\n} GpsLocation;\n\n/** Represents the status. */\ntypedef struct {\n    /** set to sizeof(GpsStatus) */\n    size_t          size;\n    GpsStatusValue status;\n} GpsStatus;\n\n/** Represents SV information. */\ntypedef struct {\n    /** set to sizeof(GpsSvInfo) */\n    size_t          size;\n    /** Pseudo-random number for the SV. */\n    int     prn;\n    /** Signal to noise ratio. */\n    float   snr;\n    /** Elevation of SV in degrees. */\n    float   elevation;\n    /** Azimuth of SV in degrees. */\n    float   azimuth;\n} GpsSvInfo;\n\n/** Represents SV status. */\ntypedef struct {\n    /** set to sizeof(GpsSvStatus) */\n    size_t          size;\n\n    /** Number of SVs currently visible. */\n    int         num_svs;\n\n    /** Contains an array of SV information. */\n    GpsSvInfo   sv_list[GPS_MAX_SVS];\n\n    /** Represents a bit mask indicating which SVs\n     * have ephemeris data.\n     */\n    uint32_t    ephemeris_mask;\n\n    /** Represents a bit mask indicating which SVs\n     * have almanac data.\n     */\n    uint32_t    almanac_mask;\n\n    /**\n     * Represents a bit mask indicating which SVs\n     * were used for computing the most recent position fix.\n     */\n    uint32_t    used_in_fix_mask;\n} GpsSvStatus;\n\n\n/* 2G and 3G */\n/* In 3G lac is discarded */\ntypedef struct {\n    uint16_t type;\n    uint16_t mcc;\n    uint16_t mnc;\n    uint16_t lac;\n    uint32_t cid;\n} AGpsRefLocationCellID;\n\ntypedef struct {\n    uint8_t mac[6];\n} AGpsRefLocationMac;\n\n/** Represents ref locations */\ntypedef struct {\n    uint16_t type;\n    union {\n        AGpsRefLocationCellID   cellID;\n        AGpsRefLocationMac      mac;\n    } u;\n} AGpsRefLocation;\n\n/** Callback with location information.\n *  Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (* gps_location_callback)(GpsLocation* location);\n\n/** Callback with status information.\n *  Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (* gps_status_callback)(GpsStatus* status);\n\n/**\n * Callback with SV status information.\n * Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (* gps_sv_status_callback)(GpsSvStatus* sv_info);\n\n/** Callback for reporting NMEA sentences.\n *  Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (* gps_nmea_callback)(GpsUtcTime timestamp, const char* nmea, int length);\n\n/** Callback to inform framework of the GPS engine's capabilities.\n *  Capability parameter is a bit field of GPS_CAPABILITY_* flags.\n */\ntypedef void (* gps_set_capabilities)(uint32_t capabilities);\n\n/** Callback utility for acquiring the GPS wakelock.\n *  This can be used to prevent the CPU from suspending while handling GPS events.\n */\ntypedef void (* gps_acquire_wakelock)();\n\n/** Callback utility for releasing the GPS wakelock. */\ntypedef void (* gps_release_wakelock)();\n\n/** Callback for requesting NTP time */\ntypedef void (* gps_request_utc_time)();\n\n/** Callback for creating a thread that can call into the Java framework code.\n *  This must be used to create any threads that report events up to the framework.\n */\ntypedef pthread_t (* gps_create_thread)(const char* name, void (*start)(void *), void* arg);\n\n/** GPS callback structure. */\ntypedef struct {\n    /** set to sizeof(GpsCallbacks) */\n    size_t      size;\n    gps_location_callback location_cb;\n    gps_status_callback status_cb;\n    gps_sv_status_callback sv_status_cb;\n    gps_nmea_callback nmea_cb;\n    gps_set_capabilities set_capabilities_cb;\n    gps_acquire_wakelock acquire_wakelock_cb;\n    gps_release_wakelock release_wakelock_cb;\n    gps_create_thread create_thread_cb;\n    gps_request_utc_time request_utc_time_cb;\n} GpsCallbacks;\n\n\n/** Represents the standard GPS interface. */\ntypedef struct {\n    /** set to sizeof(GpsInterface) */\n    size_t          size;\n    /**\n     * Opens the interface and provides the callback routines\n     * to the implementation of this interface.\n     */\n    int   (*init)( GpsCallbacks* callbacks );\n\n    /** Starts navigating. */\n    int   (*start)( void );\n\n    /** Stops navigating. */\n    int   (*stop)( void );\n\n    /** Closes the interface. */\n    void  (*cleanup)( void );\n\n    /** Injects the current time. */\n    int   (*inject_time)(GpsUtcTime time, int64_t timeReference,\n                         int uncertainty);\n\n    /** Injects current location from another location provider\n     *  (typically cell ID).\n     *  latitude and longitude are measured in degrees\n     *  expected accuracy is measured in meters\n     */\n    int  (*inject_location)(double latitude, double longitude, float accuracy);\n\n    /**\n     * Specifies that the next call to start will not use the\n     * information defined in the flags. GPS_DELETE_ALL is passed for\n     * a cold start.\n     */\n    void  (*delete_aiding_data)(GpsAidingData flags);\n\n    /**\n     * min_interval represents the time between fixes in milliseconds.\n     * preferred_accuracy represents the requested fix accuracy in meters.\n     * preferred_time represents the requested time to first fix in milliseconds.\n     *\n     * 'mode' parameter should be one of GPS_POSITION_MODE_MS_BASE\n     * or GPS_POSITION_MODE_STANDALONE.\n     * It is allowed by the platform (and it is recommended) to fallback to\n     * GPS_POSITION_MODE_MS_BASE if GPS_POSITION_MODE_MS_ASSISTED is passed in, and\n     * GPS_POSITION_MODE_MS_BASED is supported.\n     */\n    int   (*set_position_mode)(GpsPositionMode mode, GpsPositionRecurrence recurrence,\n            uint32_t min_interval, uint32_t preferred_accuracy, uint32_t preferred_time);\n\n    /** Get a pointer to extension information. */\n    const void* (*get_extension)(const char* name);\n} GpsInterface;\n\n/** Callback to request the client to download XTRA data.\n *  The client should download XTRA data and inject it by calling inject_xtra_data().\n *  Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (* gps_xtra_download_request)();\n\n/** Callback structure for the XTRA interface. */\ntypedef struct {\n    gps_xtra_download_request download_request_cb;\n    gps_create_thread create_thread_cb;\n} GpsXtraCallbacks;\n\n/** Extended interface for XTRA support. */\ntypedef struct {\n    /** set to sizeof(GpsXtraInterface) */\n    size_t          size;\n    /**\n     * Opens the XTRA interface and provides the callback routines\n     * to the implementation of this interface.\n     */\n    int  (*init)( GpsXtraCallbacks* callbacks );\n    /** Injects XTRA data into the GPS. */\n    int  (*inject_xtra_data)( char* data, int length );\n} GpsXtraInterface;\n\n/** Extended interface for DEBUG support. */\ntypedef struct {\n    /** set to sizeof(GpsDebugInterface) */\n    size_t          size;\n\n    /**\n     * This function should return any information that the native\n     * implementation wishes to include in a bugreport.\n     */\n    size_t (*get_internal_state)(char* buffer, size_t bufferSize);\n} GpsDebugInterface;\n\n#pragma pack(push,4)\n// We need to keep the alignment of this data structure to 4-bytes, to ensure that in 64-bit\n// environments the size of this legacy definition does not collide with _v2. Implementations should\n// be using _v2 and _v3, so it's OK to pay the 'unaligned' penalty in 64-bit if an old\n// implementation is still in use.\n\n/** Represents the status of AGPS. */\ntypedef struct {\n    /** set to sizeof(AGpsStatus_v1) */\n    size_t          size;\n\n    AGpsType        type;\n    AGpsStatusValue status;\n} AGpsStatus_v1;\n\n#pragma pack(pop)\n\n/** Represents the status of AGPS augmented with a IPv4 address field. */\ntypedef struct {\n    /** set to sizeof(AGpsStatus_v2) */\n    size_t          size;\n\n    AGpsType        type;\n    AGpsStatusValue status;\n    uint32_t        ipaddr;\n} AGpsStatus_v2;\n\n/* Represents the status of AGPS augmented to support IPv4 and IPv6. */\ntypedef struct {\n    /** set to sizeof(AGpsStatus_v3) */\n    size_t                  size;\n\n    AGpsType                type;\n    AGpsStatusValue         status;\n\n    /**\n     * Must be set to a valid IPv4 address if the field 'addr' contains an IPv4\n     * address, or set to INADDR_NONE otherwise.\n     */\n    uint32_t                ipaddr;\n\n    /**\n     * Must contain the IPv4 (AF_INET) or IPv6 (AF_INET6) address to report.\n     * Any other value of addr.ss_family will be rejected.\n     * */\n    struct sockaddr_storage addr;\n} AGpsStatus_v3;\n\ntypedef AGpsStatus_v3     AGpsStatus;\n\n/** Callback with AGPS status information.\n *  Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (* agps_status_callback)(AGpsStatus* status);\n\n/** Callback structure for the AGPS interface. */\ntypedef struct {\n    agps_status_callback status_cb;\n    gps_create_thread create_thread_cb;\n} AGpsCallbacks;\n\n\n/** Extended interface for AGPS support. */\ntypedef struct {\n    /** set to sizeof(AGpsInterface_v1) */\n    size_t          size;\n\n    /**\n     * Opens the AGPS interface and provides the callback routines\n     * to the implementation of this interface.\n     */\n    void  (*init)( AGpsCallbacks* callbacks );\n    /**\n     * Notifies that a data connection is available and sets\n     * the name of the APN to be used for SUPL.\n     */\n    int  (*data_conn_open)( const char* apn );\n    /**\n     * Notifies that the AGPS data connection has been closed.\n     */\n    int  (*data_conn_closed)();\n    /**\n     * Notifies that a data connection is not available for AGPS.\n     */\n    int  (*data_conn_failed)();\n    /**\n     * Sets the hostname and port for the AGPS server.\n     */\n    int  (*set_server)( AGpsType type, const char* hostname, int port );\n} AGpsInterface_v1;\n\n/**\n * Extended interface for AGPS support, it is augmented to enable to pass\n * extra APN data.\n */\ntypedef struct {\n    /** set to sizeof(AGpsInterface_v2) */\n    size_t size;\n\n    /**\n     * Opens the AGPS interface and provides the callback routines to the\n     * implementation of this interface.\n     */\n    void (*init)(AGpsCallbacks* callbacks);\n    /**\n     * Deprecated.\n     * If the HAL supports AGpsInterface_v2 this API will not be used, see\n     * data_conn_open_with_apn_ip_type for more information.\n     */\n    int (*data_conn_open)(const char* apn);\n    /**\n     * Notifies that the AGPS data connection has been closed.\n     */\n    int (*data_conn_closed)();\n    /**\n     * Notifies that a data connection is not available for AGPS.\n     */\n    int (*data_conn_failed)();\n    /**\n     * Sets the hostname and port for the AGPS server.\n     */\n    int (*set_server)(AGpsType type, const char* hostname, int port);\n\n    /**\n     * Notifies that a data connection is available and sets the name of the\n     * APN, and its IP type, to be used for SUPL connections.\n     */\n    int (*data_conn_open_with_apn_ip_type)(\n            const char* apn,\n            ApnIpType apnIpType);\n} AGpsInterface_v2;\n\ntypedef AGpsInterface_v2    AGpsInterface;\n\n/** Error codes associated with certificate operations */\n#define AGPS_CERTIFICATE_OPERATION_SUCCESS               0\n#define AGPS_CERTIFICATE_ERROR_GENERIC                -100\n#define AGPS_CERTIFICATE_ERROR_TOO_MANY_CERTIFICATES  -101\n\n/** A data structure that represents an X.509 certificate using DER encoding */\ntypedef struct {\n    size_t  length;\n    u_char* data;\n} DerEncodedCertificate;\n\n/**\n * A type definition for SHA1 Fingerprints used to identify X.509 Certificates\n * The Fingerprint is a digest of the DER Certificate that uniquely identifies it.\n */\ntypedef struct {\n    u_char data[20];\n} Sha1CertificateFingerprint;\n\n/** AGPS Interface to handle SUPL certificate operations */\ntypedef struct {\n    /** set to sizeof(SuplCertificateInterface) */\n    size_t size;\n\n    /**\n     * Installs a set of Certificates used for SUPL connections to the AGPS server.\n     * If needed the HAL should find out internally any certificates that need to be removed to\n     * accommodate the certificates to install.\n     * The certificates installed represent a full set of valid certificates needed to connect to\n     * AGPS SUPL servers.\n     * The list of certificates is required, and all must be available at the same time, when trying\n     * to establish a connection with the AGPS Server.\n     *\n     * Parameters:\n     *      certificates - A pointer to an array of DER encoded certificates that are need to be\n     *                     installed in the HAL.\n     *      length - The number of certificates to install.\n     * Returns:\n     *      AGPS_CERTIFICATE_OPERATION_SUCCESS if the operation is completed successfully\n     *      AGPS_CERTIFICATE_ERROR_TOO_MANY_CERTIFICATES if the HAL cannot store the number of\n     *          certificates attempted to be installed, the state of the certificates stored should\n     *          remain the same as before on this error case.\n     *\n     * IMPORTANT:\n     *      If needed the HAL should find out internally the set of certificates that need to be\n     *      removed to accommodate the certificates to install.\n     */\n    int  (*install_certificates) ( const DerEncodedCertificate* certificates, size_t length );\n\n    /**\n     * Notifies the HAL that a list of certificates used for SUPL connections are revoked. It is\n     * expected that the given set of certificates is removed from the internal store of the HAL.\n     *\n     * Parameters:\n     *      fingerprints - A pointer to an array of SHA1 Fingerprints to identify the set of\n     *                     certificates to revoke.\n     *      length - The number of fingerprints provided.\n     * Returns:\n     *      AGPS_CERTIFICATE_OPERATION_SUCCESS if the operation is completed successfully.\n     *\n     * IMPORTANT:\n     *      If any of the certificates provided (through its fingerprint) is not known by the HAL,\n     *      it should be ignored and continue revoking/deleting the rest of them.\n     */\n    int  (*revoke_certificates) ( const Sha1CertificateFingerprint* fingerprints, size_t length );\n} SuplCertificateInterface;\n\n/** Represents an NI request */\ntypedef struct {\n    /** set to sizeof(GpsNiNotification) */\n    size_t          size;\n\n    /**\n     * An ID generated by HAL to associate NI notifications and UI\n     * responses\n     */\n    int             notification_id;\n\n    /**\n     * An NI type used to distinguish different categories of NI\n     * events, such as GPS_NI_TYPE_VOICE, GPS_NI_TYPE_UMTS_SUPL, ...\n     */\n    GpsNiType       ni_type;\n\n    /**\n     * Notification/verification options, combinations of GpsNiNotifyFlags constants\n     */\n    GpsNiNotifyFlags notify_flags;\n\n    /**\n     * Timeout period to wait for user response.\n     * Set to 0 for no time out limit.\n     */\n    int             timeout;\n\n    /**\n     * Default response when time out.\n     */\n    GpsUserResponseType default_response;\n\n    /**\n     * Requestor ID\n     */\n    char            requestor_id[GPS_NI_SHORT_STRING_MAXLEN];\n\n    /**\n     * Notification message. It can also be used to store client_id in some cases\n     */\n    char            text[GPS_NI_LONG_STRING_MAXLEN];\n\n    /**\n     * Client name decoding scheme\n     */\n    GpsNiEncodingType requestor_id_encoding;\n\n    /**\n     * Client name decoding scheme\n     */\n    GpsNiEncodingType text_encoding;\n\n    /**\n     * A pointer to extra data. Format:\n     * key_1 = value_1\n     * key_2 = value_2\n     */\n    char           extras[GPS_NI_LONG_STRING_MAXLEN];\n\n} GpsNiNotification;\n\n/** Callback with NI notification.\n *  Can only be called from a thread created by create_thread_cb.\n */\ntypedef void (*gps_ni_notify_callback)(GpsNiNotification *notification);\n\n/** GPS NI callback structure. */\ntypedef struct\n{\n    /**\n     * Sends the notification request from HAL to GPSLocationProvider.\n     */\n    gps_ni_notify_callback notify_cb;\n    gps_create_thread create_thread_cb;\n} GpsNiCallbacks;\n\n/**\n * Extended interface for Network-initiated (NI) support.\n */\ntypedef struct\n{\n    /** set to sizeof(GpsNiInterface) */\n    size_t          size;\n\n   /** Registers the callbacks for HAL to use. */\n   void (*init) (GpsNiCallbacks *callbacks);\n\n   /** Sends a response to HAL. */\n   void (*respond) (int notif_id, GpsUserResponseType user_response);\n} GpsNiInterface;\n\nstruct gps_device_t {\n    struct hw_device_t common;\n\n    /**\n     * Set the provided lights to the provided values.\n     *\n     * Returns: 0 on succes, error code on failure.\n     */\n    const GpsInterface* (*get_gps_interface)(struct gps_device_t* dev);\n};\n\n#define AGPS_RIL_REQUEST_SETID_IMSI     (1<<0L)\n#define AGPS_RIL_REQUEST_SETID_MSISDN   (1<<1L)\n\n#define AGPS_RIL_REQUEST_REFLOC_CELLID  (1<<0L)\n#define AGPS_RIL_REQUEST_REFLOC_MAC     (1<<1L)\n\ntypedef void (*agps_ril_request_set_id)(uint32_t flags);\ntypedef void (*agps_ril_request_ref_loc)(uint32_t flags);\n\ntypedef struct {\n    agps_ril_request_set_id request_setid;\n    agps_ril_request_ref_loc request_refloc;\n    gps_create_thread create_thread_cb;\n} AGpsRilCallbacks;\n\n/** Extended interface for AGPS_RIL support. */\ntypedef struct {\n    /** set to sizeof(AGpsRilInterface) */\n    size_t          size;\n    /**\n     * Opens the AGPS interface and provides the callback routines\n     * to the implementation of this interface.\n     */\n    void  (*init)( AGpsRilCallbacks* callbacks );\n\n    /**\n     * Sets the reference location.\n     */\n    void (*set_ref_location) (const AGpsRefLocation *agps_reflocation, size_t sz_struct);\n    /**\n     * Sets the set ID.\n     */\n    void (*set_set_id) (AGpsSetIDType type, const char* setid);\n\n    /**\n     * Send network initiated message.\n     */\n    void (*ni_message) (uint8_t *msg, size_t len);\n\n    /**\n     * Notify GPS of network status changes.\n     * These parameters match values in the android.net.NetworkInfo class.\n     */\n    void (*update_network_state) (int connected, int type, int roaming, const char* extra_info);\n\n    /**\n     * Notify GPS of network status changes.\n     * These parameters match values in the android.net.NetworkInfo class.\n     */\n    void (*update_network_availability) (int avaiable, const char* apn);\n} AGpsRilInterface;\n\n/**\n * GPS Geofence.\n *      There are 3 states associated with a Geofence: Inside, Outside, Unknown.\n * There are 3 transitions: ENTERED, EXITED, UNCERTAIN.\n *\n * An example state diagram with confidence level: 95% and Unknown time limit\n * set as 30 secs is shown below. (confidence level and Unknown time limit are\n * explained latter)\n *                         ____________________________\n *                        |       Unknown (30 secs)   |\n *                         \"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n *                            ^ |                  |  ^\n *                   UNCERTAIN| |ENTERED     EXITED|  |UNCERTAIN\n *                            | v                  v  |\n *                        ________    EXITED     _________\n *                       | Inside | -----------> | Outside |\n *                       |        | <----------- |         |\n *                        \"\"\"\"\"\"\"\"    ENTERED    \"\"\"\"\"\"\"\"\"\n *\n * Inside state: We are 95% confident that the user is inside the geofence.\n * Outside state: We are 95% confident that the user is outside the geofence\n * Unknown state: Rest of the time.\n *\n * The Unknown state is better explained with an example:\n *\n *                            __________\n *                           |         c|\n *                           |  ___     |    _______\n *                           |  |a|     |   |   b   |\n *                           |  \"\"\"     |    \"\"\"\"\"\"\"\n *                           |          |\n *                            \"\"\"\"\"\"\"\"\"\"\n * In the diagram above, \"a\" and \"b\" are 2 geofences and \"c\" is the accuracy\n * circle reported by the GPS subsystem. Now with regard to \"b\", the system is\n * confident that the user is outside. But with regard to \"a\" is not confident\n * whether it is inside or outside the geofence. If the accuracy remains the\n * same for a sufficient period of time, the UNCERTAIN transition would be\n * triggered with the state set to Unknown. If the accuracy improves later, an\n * appropriate transition should be triggered.  This \"sufficient period of time\"\n * is defined by the parameter in the add_geofence_area API.\n *     In other words, Unknown state can be interpreted as a state in which the\n * GPS subsystem isn't confident enough that the user is either inside or\n * outside the Geofence. It moves to Unknown state only after the expiry of the\n * timeout.\n *\n * The geofence callback needs to be triggered for the ENTERED and EXITED\n * transitions, when the GPS system is confident that the user has entered\n * (Inside state) or exited (Outside state) the Geofence. An implementation\n * which uses a value of 95% as the confidence is recommended. The callback\n * should be triggered only for the transitions requested by the\n * add_geofence_area call.\n *\n * Even though the diagram and explanation talks about states and transitions,\n * the callee is only interested in the transistions. The states are mentioned\n * here for illustrative purposes.\n *\n * Startup Scenario: When the device boots up, if an application adds geofences,\n * and then we get an accurate GPS location fix, it needs to trigger the\n * appropriate (ENTERED or EXITED) transition for every Geofence it knows about.\n * By default, all the Geofences will be in the Unknown state.\n *\n * When the GPS system is unavailable, gps_geofence_status_callback should be\n * called to inform the upper layers of the same. Similarly, when it becomes\n * available the callback should be called. This is a global state while the\n * UNKNOWN transition described above is per geofence.\n *\n * An important aspect to note is that users of this API (framework), will use\n * other subsystems like wifi, sensors, cell to handle Unknown case and\n * hopefully provide a definitive state transition to the third party\n * application. GPS Geofence will just be a signal indicating what the GPS\n * subsystem knows about the Geofence.\n *\n */\n#define GPS_GEOFENCE_ENTERED     (1<<0L)\n#define GPS_GEOFENCE_EXITED      (1<<1L)\n#define GPS_GEOFENCE_UNCERTAIN   (1<<2L)\n\n#define GPS_GEOFENCE_UNAVAILABLE (1<<0L)\n#define GPS_GEOFENCE_AVAILABLE   (1<<1L)\n\n#define GPS_GEOFENCE_OPERATION_SUCCESS           0\n#define GPS_GEOFENCE_ERROR_TOO_MANY_GEOFENCES -100\n#define GPS_GEOFENCE_ERROR_ID_EXISTS          -101\n#define GPS_GEOFENCE_ERROR_ID_UNKNOWN         -102\n#define GPS_GEOFENCE_ERROR_INVALID_TRANSITION -103\n#define GPS_GEOFENCE_ERROR_GENERIC            -149\n\n/**\n * The callback associated with the geofence.\n * Parameters:\n *      geofence_id - The id associated with the add_geofence_area.\n *      location    - The current GPS location.\n *      transition  - Can be one of GPS_GEOFENCE_ENTERED, GPS_GEOFENCE_EXITED,\n *                    GPS_GEOFENCE_UNCERTAIN.\n *      timestamp   - Timestamp when the transition was detected.\n *\n * The callback should only be called when the caller is interested in that\n * particular transition. For instance, if the caller is interested only in\n * ENTERED transition, then the callback should NOT be called with the EXITED\n * transition.\n *\n * IMPORTANT: If a transition is triggered resulting in this callback, the GPS\n * subsystem will wake up the application processor, if its in suspend state.\n */\ntypedef void (*gps_geofence_transition_callback) (int32_t geofence_id,  GpsLocation* location,\n        int32_t transition, GpsUtcTime timestamp);\n\n/**\n * The callback associated with the availability of the GPS system for geofencing\n * monitoring. If the GPS system determines that it cannot monitor geofences\n * because of lack of reliability or unavailability of the GPS signals, it will\n * call this callback with GPS_GEOFENCE_UNAVAILABLE parameter.\n *\n * Parameters:\n *  status - GPS_GEOFENCE_UNAVAILABLE or GPS_GEOFENCE_AVAILABLE.\n *  last_location - Last known location.\n */\ntypedef void (*gps_geofence_status_callback) (int32_t status, GpsLocation* last_location);\n\n/**\n * The callback associated with the add_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * status - GPS_GEOFENCE_OPERATION_SUCCESS\n *          GPS_GEOFENCE_ERROR_TOO_MANY_GEOFENCES  - geofence limit has been reached.\n *          GPS_GEOFENCE_ERROR_ID_EXISTS  - geofence with id already exists\n *          GPS_GEOFENCE_ERROR_INVALID_TRANSITION - the monitorTransition contains an\n *              invalid transition\n *          GPS_GEOFENCE_ERROR_GENERIC - for other errors.\n */\ntypedef void (*gps_geofence_add_callback) (int32_t geofence_id, int32_t status);\n\n/**\n * The callback associated with the remove_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * status - GPS_GEOFENCE_OPERATION_SUCCESS\n *          GPS_GEOFENCE_ERROR_ID_UNKNOWN - for invalid id\n *          GPS_GEOFENCE_ERROR_GENERIC for others.\n */\ntypedef void (*gps_geofence_remove_callback) (int32_t geofence_id, int32_t status);\n\n\n/**\n * The callback associated with the pause_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * status - GPS_GEOFENCE_OPERATION_SUCCESS\n *          GPS_GEOFENCE_ERROR_ID_UNKNOWN - for invalid id\n *          GPS_GEOFENCE_ERROR_INVALID_TRANSITION -\n *                    when monitor_transitions is invalid\n *          GPS_GEOFENCE_ERROR_GENERIC for others.\n */\ntypedef void (*gps_geofence_pause_callback) (int32_t geofence_id, int32_t status);\n\n/**\n * The callback associated with the resume_geofence call.\n *\n * Parameter:\n * geofence_id - Id of the geofence.\n * status - GPS_GEOFENCE_OPERATION_SUCCESS\n *          GPS_GEOFENCE_ERROR_ID_UNKNOWN - for invalid id\n *          GPS_GEOFENCE_ERROR_GENERIC for others.\n */\ntypedef void (*gps_geofence_resume_callback) (int32_t geofence_id, int32_t status);\n\ntypedef struct {\n    gps_geofence_transition_callback geofence_transition_callback;\n    gps_geofence_status_callback geofence_status_callback;\n    gps_geofence_add_callback geofence_add_callback;\n    gps_geofence_remove_callback geofence_remove_callback;\n    gps_geofence_pause_callback geofence_pause_callback;\n    gps_geofence_resume_callback geofence_resume_callback;\n    gps_create_thread create_thread_cb;\n} GpsGeofenceCallbacks;\n\n/** Extended interface for GPS_Geofencing support */\ntypedef struct {\n   /** set to sizeof(GpsGeofencingInterface) */\n   size_t          size;\n\n   /**\n    * Opens the geofence interface and provides the callback routines\n    * to the implementation of this interface.\n    */\n   void  (*init)( GpsGeofenceCallbacks* callbacks );\n\n   /**\n    * Add a geofence area. This api currently supports circular geofences.\n    * Parameters:\n    *    geofence_id - The id for the geofence. If a geofence with this id\n    *       already exists, an error value (GPS_GEOFENCE_ERROR_ID_EXISTS)\n    *       should be returned.\n    *    latitude, longtitude, radius_meters - The lat, long and radius\n    *       (in meters) for the geofence\n    *    last_transition - The current state of the geofence. For example, if\n    *       the system already knows that the user is inside the geofence,\n    *       this will be set to GPS_GEOFENCE_ENTERED. In most cases, it\n    *       will be GPS_GEOFENCE_UNCERTAIN.\n    *    monitor_transition - Which transitions to monitor. Bitwise OR of\n    *       GPS_GEOFENCE_ENTERED, GPS_GEOFENCE_EXITED and\n    *       GPS_GEOFENCE_UNCERTAIN.\n    *    notification_responsiveness_ms - Defines the best-effort description\n    *       of how soon should the callback be called when the transition\n    *       associated with the Geofence is triggered. For instance, if set\n    *       to 1000 millseconds with GPS_GEOFENCE_ENTERED, the callback\n    *       should be called 1000 milliseconds within entering the geofence.\n    *       This parameter is defined in milliseconds.\n    *       NOTE: This is not to be confused with the rate that the GPS is\n    *       polled at. It is acceptable to dynamically vary the rate of\n    *       sampling the GPS for power-saving reasons; thus the rate of\n    *       sampling may be faster or slower than this.\n    *    unknown_timer_ms - The time limit after which the UNCERTAIN transition\n    *       should be triggered. This parameter is defined in milliseconds.\n    *       See above for a detailed explanation.\n    */\n   void (*add_geofence_area) (int32_t geofence_id, double latitude, double longitude,\n       double radius_meters, int last_transition, int monitor_transitions,\n       int notification_responsiveness_ms, int unknown_timer_ms);\n\n   /**\n    * Pause monitoring a particular geofence.\n    * Parameters:\n    *   geofence_id - The id for the geofence.\n    */\n   void (*pause_geofence) (int32_t geofence_id);\n\n   /**\n    * Resume monitoring a particular geofence.\n    * Parameters:\n    *   geofence_id - The id for the geofence.\n    *   monitor_transitions - Which transitions to monitor. Bitwise OR of\n    *       GPS_GEOFENCE_ENTERED, GPS_GEOFENCE_EXITED and\n    *       GPS_GEOFENCE_UNCERTAIN.\n    *       This supersedes the value associated provided in the\n    *       add_geofence_area call.\n    */\n   void (*resume_geofence) (int32_t geofence_id, int monitor_transitions);\n\n   /**\n    * Remove a geofence area. After the function returns, no notifications\n    * should be sent.\n    * Parameter:\n    *   geofence_id - The id for the geofence.\n    */\n   void (*remove_geofence_area) (int32_t geofence_id);\n} GpsGeofencingInterface;\n\n\n/**\n * Represents an estimate of the GPS clock time.\n */\ntypedef struct {\n    /** set to sizeof(GpsClock) */\n    size_t size;\n\n    /** A set of flags indicating the validity of the fields in this data structure. */\n    GpsClockFlags flags;\n\n    /**\n     * Leap second data.\n     * The sign of the value is defined by the following equation:\n     *      utc_time_ns = time_ns + (full_bias_ns + bias_ns) - leap_second * 1,000,000,000\n     *\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_LEAP_SECOND.\n     */\n    int16_t leap_second;\n\n    /**\n     * Indicates the type of time reported by the 'time_ns' field.\n     * This is a Mandatory field.\n     */\n    GpsClockType type;\n\n    /**\n     * The GPS receiver internal clock value. This can be either the local hardware clock value\n     * (GPS_CLOCK_TYPE_LOCAL_HW_TIME), or the current GPS time derived inside GPS receiver\n     * (GPS_CLOCK_TYPE_GPS_TIME). The field 'type' defines the time reported.\n     *\n     * For local hardware clock, this value is expected to be monotonically increasing during\n     * the reporting session. The real GPS time can be derived by compensating the 'full bias'\n     * (when it is available) from this value.\n     *\n     * For GPS time, this value is expected to be the best estimation of current GPS time that GPS\n     * receiver can achieve. Set the 'time uncertainty' appropriately when GPS time is specified.\n     *\n     * Sub-nanosecond accuracy can be provided by means of the 'bias' field.\n     * The value contains the 'time uncertainty' in it.\n     *\n     * This is a Mandatory field.\n     */\n    int64_t time_ns;\n\n    /**\n     * 1-Sigma uncertainty associated with the clock's time in nanoseconds.\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * This value should be set if GPS_CLOCK_TYPE_GPS_TIME is set.\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_TIME_UNCERTAINTY.\n     */\n    double time_uncertainty_ns;\n\n    /**\n     * The difference between hardware clock ('time' field) inside GPS receiver and the true GPS\n     * time since 0000Z, January 6, 1980, in nanoseconds.\n     * This value is used if and only if GPS_CLOCK_TYPE_LOCAL_HW_TIME is set, and GPS receiver\n     * has solved the clock for GPS time.\n     * The caller is responsible for using the 'bias uncertainty' field for quality check.\n     *\n     * The sign of the value is defined by the following equation:\n     *      true time (GPS time) = time_ns + (full_bias_ns + bias_ns)\n     *\n     * This value contains the 'bias uncertainty' in it.\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_FULL_BIAS.\n\n     */\n    int64_t full_bias_ns;\n\n    /**\n     * Sub-nanosecond bias.\n     * The value contains the 'bias uncertainty' in it.\n     *\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_BIAS.\n     */\n    double bias_ns;\n\n    /**\n     * 1-Sigma uncertainty associated with the clock's bias in nanoseconds.\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_BIAS_UNCERTAINTY.\n     */\n    double bias_uncertainty_ns;\n\n    /**\n     * The clock's drift in nanoseconds (per second).\n     * A positive value means that the frequency is higher than the nominal frequency.\n     *\n     * The value contains the 'drift uncertainty' in it.\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_DRIFT.\n     *\n     * If GpsMeasurement's 'flags' field contains GPS_MEASUREMENT_HAS_UNCORRECTED_PSEUDORANGE_RATE,\n     * it is encouraged that this field is also provided.\n     */\n    double drift_nsps;\n\n    /**\n     * 1-Sigma uncertainty associated with the clock's drift in nanoseconds (per second).\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * If the data is available 'flags' must contain GPS_CLOCK_HAS_DRIFT_UNCERTAINTY.\n     */\n    double drift_uncertainty_nsps;\n} GpsClock;\n\n/**\n * Represents a GPS Measurement, it contains raw and computed information.\n */\ntypedef struct {\n    /** set to sizeof(GpsMeasurement) */\n    size_t size;\n\n    /** A set of flags indicating the validity of the fields in this data structure. */\n    GpsMeasurementFlags flags;\n\n    /**\n     * Pseudo-random number in the range of [1, 32]\n     * This is a Mandatory value.\n     */\n    int8_t prn;\n\n    /**\n     * Time offset at which the measurement was taken in nanoseconds.\n     * The reference receiver's time is specified by GpsData::clock::time_ns and should be\n     * interpreted in the same way as indicated by GpsClock::type.\n     *\n     * The sign of time_offset_ns is given by the following equation:\n     *      measurement time = GpsClock::time_ns + time_offset_ns\n     *\n     * It provides an individual time-stamp for the measurement, and allows sub-nanosecond accuracy.\n     * This is a Mandatory value.\n     */\n    double time_offset_ns;\n\n    /**\n     * Per satellite sync state. It represents the current sync state for the associated satellite.\n     * Based on the sync state, the 'received GPS tow' field should be interpreted accordingly.\n     *\n     * This is a Mandatory value.\n     */\n    GpsMeasurementState state;\n\n    /**\n     * Received GPS Time-of-Week at the measurement time, in nanoseconds.\n     * The value is relative to the beginning of the current GPS week.\n     *\n     * Given the highest sync state that can be achieved, per each satellite, valid range for\n     * this field can be:\n     *     Searching       : [ 0       ]   : GPS_MEASUREMENT_STATE_UNKNOWN\n     *     C/A code lock   : [ 0   1ms ]   : GPS_MEASUREMENT_STATE_CODE_LOCK is set\n     *     Bit sync        : [ 0  20ms ]   : GPS_MEASUREMENT_STATE_BIT_SYNC is set\n     *     Subframe sync   : [ 0    6s ]   : GPS_MEASUREMENT_STATE_SUBFRAME_SYNC is set\n     *     TOW decoded     : [ 0 1week ]   : GPS_MEASUREMENT_STATE_TOW_DECODED is set\n     *\n     * However, if there is any ambiguity in integer millisecond,\n     * GPS_MEASUREMENT_STATE_MSEC_AMBIGUOUS should be set accordingly, in the 'state' field.\n     *\n     * This value must be populated if 'state' != GPS_MEASUREMENT_STATE_UNKNOWN.\n     */\n    int64_t received_gps_tow_ns;\n\n    /**\n     * 1-Sigma uncertainty of the Received GPS Time-of-Week in nanoseconds.\n     *\n     * This value must be populated if 'state' != GPS_MEASUREMENT_STATE_UNKNOWN.\n     */\n    int64_t received_gps_tow_uncertainty_ns;\n\n    /**\n     * Carrier-to-noise density in dB-Hz, in the range [0, 63].\n     * It contains the measured C/N0 value for the signal at the antenna input.\n     *\n     * This is a Mandatory value.\n     */\n    double c_n0_dbhz;\n\n    /**\n     * Pseudorange rate at the timestamp in m/s.\n     * The correction of a given Pseudorange Rate value includes corrections for receiver and\n     * satellite clock frequency errors.\n     *\n     * If GPS_MEASUREMENT_HAS_UNCORRECTED_PSEUDORANGE_RATE is set in 'flags' field, this field must\n     * be populated with the 'uncorrected' reading.\n     * If GPS_MEASUREMENT_HAS_UNCORRECTED_PSEUDORANGE_RATE is not set in 'flags' field, this field\n     * must be populated with the 'corrected' reading. This is the default behavior.\n     *\n     * It is encouraged to provide the 'uncorrected' 'pseudorange rate', and provide GpsClock's\n     * 'drift' field as well.\n     *\n     * The value includes the 'pseudorange rate uncertainty' in it.\n     * A positive 'uncorrected' value indicates that the SV is moving away from the receiver.\n     *\n     * The sign of the 'uncorrected' 'pseudorange rate' and its relation to the sign of 'doppler\n     * shift' is given by the equation:\n     *      pseudorange rate = -k * doppler shift   (where k is a constant)\n     *\n     * This is a Mandatory value.\n     */\n    double pseudorange_rate_mps;\n\n    /**\n     * 1-Sigma uncertainty of the pseudurange rate in m/s.\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * This is a Mandatory value.\n     */\n    double pseudorange_rate_uncertainty_mps;\n\n    /**\n     * Accumulated delta range's state. It indicates whether ADR is reset or there is a cycle slip\n     * (indicating loss of lock).\n     *\n     * This is a Mandatory value.\n     */\n    GpsAccumulatedDeltaRangeState accumulated_delta_range_state;\n\n    /**\n     * Accumulated delta range since the last channel reset in meters.\n     * A positive value indicates that the SV is moving away from the receiver.\n     *\n     * The sign of the 'accumulated delta range' and its relation to the sign of 'carrier phase'\n     * is given by the equation:\n     *          accumulated delta range = -k * carrier phase    (where k is a constant)\n     *\n     * This value must be populated if 'accumulated delta range state' != GPS_ADR_STATE_UNKNOWN.\n     * However, it is expected that the data is only accurate when:\n     *      'accumulated delta range state' == GPS_ADR_STATE_VALID.\n     */\n    double accumulated_delta_range_m;\n\n    /**\n     * 1-Sigma uncertainty of the accumulated delta range in meters.\n     * This value must be populated if 'accumulated delta range state' != GPS_ADR_STATE_UNKNOWN.\n     */\n    double accumulated_delta_range_uncertainty_m;\n\n    /**\n     * Best derived Pseudorange by the chip-set, in meters.\n     * The value contains the 'pseudorange uncertainty' in it.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_PSEUDORANGE.\n     */\n    double pseudorange_m;\n\n    /**\n     * 1-Sigma uncertainty of the pseudorange in meters.\n     * The value contains the 'pseudorange' and 'clock' uncertainty in it.\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_PSEUDORANGE_UNCERTAINTY.\n     */\n    double pseudorange_uncertainty_m;\n\n    /**\n     * A fraction of the current C/A code cycle, in the range [0.0, 1023.0]\n     * This value contains the time (in Chip units) since the last C/A code cycle (GPS Msec epoch).\n     *\n     * The reference frequency is given by the field 'carrier_frequency_hz'.\n     * The value contains the 'code-phase uncertainty' in it.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_CODE_PHASE.\n     */\n    double code_phase_chips;\n\n    /**\n     * 1-Sigma uncertainty of the code-phase, in a fraction of chips.\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_CODE_PHASE_UNCERTAINTY.\n     */\n    double code_phase_uncertainty_chips;\n\n    /**\n     * Carrier frequency at which codes and messages are modulated, it can be L1 or L2.\n     * If the field is not set, the carrier frequency is assumed to be L1.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_CARRIER_FREQUENCY.\n     */\n    float carrier_frequency_hz;\n\n    /**\n     * The number of full carrier cycles between the satellite and the receiver.\n     * The reference frequency is given by the field 'carrier_frequency_hz'.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_CARRIER_CYCLES.\n     */\n    int64_t carrier_cycles;\n\n    /**\n     * The RF phase detected by the receiver, in the range [0.0, 1.0].\n     * This is usually the fractional part of the complete carrier phase measurement.\n     *\n     * The reference frequency is given by the field 'carrier_frequency_hz'.\n     * The value contains the 'carrier-phase uncertainty' in it.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_CARRIER_PHASE.\n     */\n    double carrier_phase;\n\n    /**\n     * 1-Sigma uncertainty of the carrier-phase.\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_CARRIER_PHASE_UNCERTAINTY.\n     */\n    double carrier_phase_uncertainty;\n\n    /**\n     * An enumeration that indicates the 'loss of lock' state of the event.\n     */\n    GpsLossOfLock loss_of_lock;\n\n    /**\n     * The number of GPS bits transmitted since Sat-Sun midnight (GPS week).\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_BIT_NUMBER.\n     */\n    int32_t bit_number;\n\n    /**\n     * The elapsed time since the last received bit in milliseconds, in the range [0, 20]\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_TIME_FROM_LAST_BIT.\n     */\n    int16_t time_from_last_bit_ms;\n\n    /**\n     * Doppler shift in Hz.\n     * A positive value indicates that the SV is moving toward the receiver.\n     *\n     * The reference frequency is given by the field 'carrier_frequency_hz'.\n     * The value contains the 'doppler shift uncertainty' in it.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_DOPPLER_SHIFT.\n     */\n    double doppler_shift_hz;\n\n    /**\n     * 1-Sigma uncertainty of the doppler shift in Hz.\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_DOPPLER_SHIFT_UNCERTAINTY.\n     */\n    double doppler_shift_uncertainty_hz;\n\n    /**\n     * An enumeration that indicates the 'multipath' state of the event.\n     */\n    GpsMultipathIndicator multipath_indicator;\n\n    /**\n     * Signal-to-noise ratio in dB.\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_SNR.\n     */\n    double snr_db;\n\n    /**\n     * Elevation in degrees, the valid range is [-90, 90].\n     * The value contains the 'elevation uncertainty' in it.\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_ELEVATION.\n     */\n    double elevation_deg;\n\n    /**\n     * 1-Sigma uncertainty of the elevation in degrees, the valid range is [0, 90].\n     * The uncertainty is represented as the absolute (single sided) value.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_ELEVATION_UNCERTAINTY.\n     */\n    double elevation_uncertainty_deg;\n\n    /**\n     * Azimuth in degrees, in the range [0, 360).\n     * The value contains the 'azimuth uncertainty' in it.\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_AZIMUTH.\n     *  */\n    double azimuth_deg;\n\n    /**\n     * 1-Sigma uncertainty of the azimuth in degrees, the valid range is [0, 180].\n     * The uncertainty is represented as an absolute (single sided) value.\n     *\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_AZIMUTH_UNCERTAINTY.\n     */\n    double azimuth_uncertainty_deg;\n\n    /**\n     * Whether the GPS represented by the measurement was used for computing the most recent fix.\n     * If the data is available, 'flags' must contain GPS_MEASUREMENT_HAS_USED_IN_FIX.\n     */\n    bool used_in_fix;\n} GpsMeasurement;\n\n/** Represents a reading of GPS measurements. */\ntypedef struct {\n    /** set to sizeof(GpsData) */\n    size_t size;\n\n    /** Number of measurements. */\n    size_t measurement_count;\n\n    /** The array of measurements. */\n    GpsMeasurement measurements[GPS_MAX_MEASUREMENT];\n\n    /** The GPS clock time reading. */\n    GpsClock clock;\n} GpsData;\n\n/**\n * The callback for to report measurements from the HAL.\n *\n * Parameters:\n *    data - A data structure containing the measurements.\n */\ntypedef void (*gps_measurement_callback) (GpsData* data);\n\ntypedef struct {\n    /** set to sizeof(GpsMeasurementCallbacks) */\n    size_t size;\n    gps_measurement_callback measurement_callback;\n} GpsMeasurementCallbacks;\n\n#define GPS_MEASUREMENT_OPERATION_SUCCESS          0\n#define GPS_MEASUREMENT_ERROR_ALREADY_INIT      -100\n#define GPS_MEASUREMENT_ERROR_GENERIC           -101\n\n/**\n * Extended interface for GPS Measurements support.\n */\ntypedef struct {\n    /** Set to sizeof(GpsMeasurementInterface) */\n    size_t size;\n\n    /**\n     * Initializes the interface and registers the callback routines with the HAL.\n     * After a successful call to 'init' the HAL must begin to provide updates at its own phase.\n     *\n     * Status:\n     *    GPS_MEASUREMENT_OPERATION_SUCCESS\n     *    GPS_MEASUREMENT_ERROR_ALREADY_INIT - if a callback has already been registered without a\n     *              corresponding call to 'close'\n     *    GPS_MEASUREMENT_ERROR_GENERIC - if any other error occurred, it is expected that the HAL\n     *              will not generate any updates upon returning this error code.\n     */\n    int (*init) (GpsMeasurementCallbacks* callbacks);\n\n    /**\n     * Stops updates from the HAL, and unregisters the callback routines.\n     * After a call to stop, the previously registered callbacks must be considered invalid by the\n     * HAL.\n     * If stop is invoked without a previous 'init', this function should perform no work.\n     */\n    void (*close) ();\n\n} GpsMeasurementInterface;\n\n\n/** Represents a GPS navigation message (or a fragment of it). */\ntypedef struct {\n    /** set to sizeof(GpsNavigationMessage) */\n    size_t size;\n\n    /**\n     * Pseudo-random number in the range of [1, 32]\n     * This is a Mandatory value.\n     */\n    int8_t prn;\n\n    /**\n     * The type of message contained in the structure.\n     * This is a Mandatory value.\n     */\n    GpsNavigationMessageType type;\n\n    /**\n     * The status of the received navigation message.\n     * No need to send any navigation message that contains words with parity error and cannot be\n     * corrected.\n     */\n    NavigationMessageStatus status;\n\n    /**\n     * Message identifier.\n     * It provides an index so the complete Navigation Message can be assembled. i.e. fo L1 C/A\n     * subframe 4 and 5, this value corresponds to the 'frame id' of the navigation message.\n     * Subframe 1, 2, 3 does not contain a 'frame id' and this value can be set to -1.\n     */\n    int16_t message_id;\n\n    /**\n     * Sub-message identifier.\n     * If required by the message 'type', this value contains a sub-index within the current\n     * message (or frame) that is being transmitted.\n     * i.e. for L1 C/A the submessage id corresponds to the sub-frame id of the navigation message.\n     */\n    int16_t submessage_id;\n\n    /**\n     * The length of the data (in bytes) contained in the current message.\n     * If this value is different from zero, 'data' must point to an array of the same size.\n     * e.g. for L1 C/A the size of the sub-frame will be 40 bytes (10 words, 30 bits/word).\n     *\n     * This is a Mandatory value.\n     */\n    size_t data_length;\n\n    /**\n     * The data of the reported GPS message.\n     * The bytes (or words) specified using big endian format (MSB first).\n     *\n     * For L1 C/A, each subframe contains 10 30-bit GPS words. Each GPS word (30 bits) should be\n     * fitted into the last 30 bits in a 4-byte word (skip B31 and B32), with MSB first.\n     */\n    uint8_t* data;\n\n} GpsNavigationMessage;\n\n/**\n * The callback to report an available fragment of a GPS navigation messages from the HAL.\n *\n * Parameters:\n *      message - The GPS navigation submessage/subframe representation.\n */\ntypedef void (*gps_navigation_message_callback) (GpsNavigationMessage* message);\n\ntypedef struct {\n    /** set to sizeof(GpsNavigationMessageCallbacks) */\n    size_t size;\n    gps_navigation_message_callback navigation_message_callback;\n} GpsNavigationMessageCallbacks;\n\n#define GPS_NAVIGATION_MESSAGE_OPERATION_SUCCESS             0\n#define GPS_NAVIGATION_MESSAGE_ERROR_ALREADY_INIT         -100\n#define GPS_NAVIGATION_MESSAGE_ERROR_GENERIC              -101\n\n/**\n * Extended interface for GPS navigation message reporting support.\n */\ntypedef struct {\n    /** Set to sizeof(GpsNavigationMessageInterface) */\n    size_t size;\n\n    /**\n     * Initializes the interface and registers the callback routines with the HAL.\n     * After a successful call to 'init' the HAL must begin to provide updates as they become\n     * available.\n     *\n     * Status:\n     *      GPS_NAVIGATION_MESSAGE_OPERATION_SUCCESS\n     *      GPS_NAVIGATION_MESSAGE_ERROR_ALREADY_INIT - if a callback has already been registered\n     *              without a corresponding call to 'close'.\n     *      GPS_NAVIGATION_MESSAGE_ERROR_GENERIC - if any other error occurred, it is expected that\n     *              the HAL will not generate any updates upon returning this error code.\n     */\n    int (*init) (GpsNavigationMessageCallbacks* callbacks);\n\n    /**\n     * Stops updates from the HAL, and unregisters the callback routines.\n     * After a call to stop, the previously registered callbacks must be considered invalid by the\n     * HAL.\n     * If stop is invoked without a previous 'init', this function should perform no work.\n     */\n    void (*close) ();\n\n} GpsNavigationMessageInterface;\n\n/**\n * Interface for passing GNSS configuration contents from platform to HAL.\n */\ntypedef struct {\n    /** Set to sizeof(GnssConfigurationInterface) */\n    size_t size;\n\n    /**\n     * Deliver GNSS configuration contents to HAL.\n     * Parameters:\n     *     config_data - a pointer to a char array which holds what usually is expected from\n                         file(/etc/gps.conf), i.e., a sequence of UTF8 strings separated by '\\n'.\n     *     length - total number of UTF8 characters in configuraiton data.\n     *\n     * IMPORTANT:\n     *      GPS HAL should expect this function can be called multiple times. And it may be\n     *      called even when GpsLocationProvider is already constructed and enabled. GPS HAL\n     *      should maintain the existing requests for various callback regardless the change\n     *      in configuration data.\n     */\n    void (*configuration_update) (const char* config_data, int32_t length);\n} GnssConfigurationInterface;\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_HARDWARE_GPS_H */\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/gralloc.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_GRALLOC_INTERFACE_H\n#define ANDROID_GRALLOC_INTERFACE_H\n\n#include <system/window.h>\n#include <system/graphics.h>\n#include <hardware/hardware.h>\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <cutils/native_handle.h>\n\n#include <hardware/hardware.h>\n#include <hardware/fb.h>\n\n__BEGIN_DECLS\n\n/**\n * Module versioning information for the Gralloc hardware module, based on\n * gralloc_module_t.common.module_api_version.\n *\n * Version History:\n *\n * GRALLOC_MODULE_API_VERSION_0_1:\n * Initial Gralloc hardware module API.\n *\n * GRALLOC_MODULE_API_VERSION_0_2:\n * Add support for flexible YCbCr format with (*lock_ycbcr)() method.\n *\n * GRALLOC_MODULE_API_VERSION_0_3:\n * Add support for fence passing to/from lock/unlock.\n */\n\n#define GRALLOC_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n#define GRALLOC_MODULE_API_VERSION_0_2  HARDWARE_MODULE_API_VERSION(0, 2)\n#define GRALLOC_MODULE_API_VERSION_0_3  HARDWARE_MODULE_API_VERSION(0, 3)\n\n#define GRALLOC_DEVICE_API_VERSION_0_1  HARDWARE_DEVICE_API_VERSION(0, 1)\n\n/**\n * The id of this module\n */\n#define GRALLOC_HARDWARE_MODULE_ID \"gralloc\"\n\n/**\n * Name of the graphics device to open\n */\n\n#define GRALLOC_HARDWARE_GPU0 \"gpu0\"\n\nenum {\n    /* buffer is never read in software */\n    GRALLOC_USAGE_SW_READ_NEVER         = 0x00000000,\n    /* buffer is rarely read in software */\n    GRALLOC_USAGE_SW_READ_RARELY        = 0x00000002,\n    /* buffer is often read in software */\n    GRALLOC_USAGE_SW_READ_OFTEN         = 0x00000003,\n    /* mask for the software read values */\n    GRALLOC_USAGE_SW_READ_MASK          = 0x0000000F,\n\n    /* buffer is never written in software */\n    GRALLOC_USAGE_SW_WRITE_NEVER        = 0x00000000,\n    /* buffer is rarely written in software */\n    GRALLOC_USAGE_SW_WRITE_RARELY       = 0x00000020,\n    /* buffer is often written in software */\n    GRALLOC_USAGE_SW_WRITE_OFTEN        = 0x00000030,\n    /* mask for the software write values */\n    GRALLOC_USAGE_SW_WRITE_MASK         = 0x000000F0,\n\n    /* buffer will be used as an OpenGL ES texture */\n    GRALLOC_USAGE_HW_TEXTURE            = 0x00000100,\n    /* buffer will be used as an OpenGL ES render target */\n    GRALLOC_USAGE_HW_RENDER             = 0x00000200,\n    /* buffer will be used by the 2D hardware blitter */\n    GRALLOC_USAGE_HW_2D                 = 0x00000400,\n    /* buffer will be used by the HWComposer HAL module */\n    GRALLOC_USAGE_HW_COMPOSER           = 0x00000800,\n    /* buffer will be used with the framebuffer device */\n    GRALLOC_USAGE_HW_FB                 = 0x00001000,\n\n    /* buffer should be displayed full-screen on an external display when\n     * possible */\n    GRALLOC_USAGE_EXTERNAL_DISP         = 0x00002000,\n\n    /* Must have a hardware-protected path to external display sink for\n     * this buffer.  If a hardware-protected path is not available, then\n     * either don't composite only this buffer (preferred) to the\n     * external sink, or (less desirable) do not route the entire\n     * composition to the external sink.  */\n    GRALLOC_USAGE_PROTECTED             = 0x00004000,\n\n    /* buffer may be used as a cursor */\n    GRALLOC_USAGE_CURSOR                = 0x00008000,\n\n    /* buffer will be used with the HW video encoder */\n    GRALLOC_USAGE_HW_VIDEO_ENCODER      = 0x00010000,\n    /* buffer will be written by the HW camera pipeline */\n    GRALLOC_USAGE_HW_CAMERA_WRITE       = 0x00020000,\n    /* buffer will be read by the HW camera pipeline */\n    GRALLOC_USAGE_HW_CAMERA_READ        = 0x00040000,\n    /* buffer will be used as part of zero-shutter-lag queue */\n    GRALLOC_USAGE_HW_CAMERA_ZSL         = 0x00060000,\n    /* mask for the camera access values */\n    GRALLOC_USAGE_HW_CAMERA_MASK        = 0x00060000,\n    /* mask for the software usage bit-mask */\n    GRALLOC_USAGE_HW_MASK               = 0x00071F00,\n\n    /* buffer will be used as a RenderScript Allocation */\n    GRALLOC_USAGE_RENDERSCRIPT          = 0x00100000,\n\n    /* Set by the consumer to indicate to the producer that they may attach a\n     * buffer that they did not detach from the BufferQueue. Will be filtered\n     * out by GRALLOC_USAGE_ALLOC_MASK, so gralloc modules will not need to\n     * handle this flag. */\n    GRALLOC_USAGE_FOREIGN_BUFFERS       = 0x00200000,\n\n    /* Mask of all flags which could be passed to a gralloc module for buffer\n     * allocation. Any flags not in this mask do not need to be handled by\n     * gralloc modules. */\n    GRALLOC_USAGE_ALLOC_MASK            = ~(GRALLOC_USAGE_FOREIGN_BUFFERS),\n\n    /* implementation-specific private usage flags */\n    GRALLOC_USAGE_PRIVATE_0             = 0x10000000,\n    GRALLOC_USAGE_PRIVATE_1             = 0x20000000,\n    GRALLOC_USAGE_PRIVATE_2             = 0x40000000,\n    GRALLOC_USAGE_PRIVATE_3             = 0x80000000,\n    GRALLOC_USAGE_PRIVATE_MASK          = 0xF0000000,\n\n#ifdef EXYNOS4_ENHANCEMENTS\n    /* SAMSUNG */\n    GRALLOC_USAGE_PRIVATE_NONECACHE     = 0x00800000,\n\n    GRALLOC_USAGE_HW_FIMC1              = 0x01000000,\n    GRALLOC_USAGE_HW_ION                = 0x02000000,\n    GRALLOC_USAGE_YUV_ADDR              = 0x04000000,\n    GRALLOC_USAGE_CAMERA                = 0x08000000,\n\n    /* SEC Private usage , for Overlay path at HWC */\n    GRALLOC_USAGE_HWC_HWOVERLAY         = 0x20000000,\n#endif\n};\n\n/*****************************************************************************/\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\ntypedef struct gralloc_module_t {\n    struct hw_module_t common;\n    \n    /*\n     * (*registerBuffer)() must be called before a buffer_handle_t that has not\n     * been created with (*alloc_device_t::alloc)() can be used.\n     * \n     * This is intended to be used with buffer_handle_t's that have been\n     * received in this process through IPC.\n     * \n     * This function checks that the handle is indeed a valid one and prepares\n     * it for use with (*lock)() and (*unlock)().\n     * \n     * It is not necessary to call (*registerBuffer)() on a handle created \n     * with (*alloc_device_t::alloc)().\n     * \n     * returns an error if this buffer_handle_t is not valid.\n     */\n    int (*registerBuffer)(struct gralloc_module_t const* module,\n            buffer_handle_t handle);\n\n    /*\n     * (*unregisterBuffer)() is called once this handle is no longer needed in\n     * this process. After this call, it is an error to call (*lock)(),\n     * (*unlock)(), or (*registerBuffer)().\n     * \n     * This function doesn't close or free the handle itself; this is done\n     * by other means, usually through libcutils's native_handle_close() and\n     * native_handle_free(). \n     * \n     * It is an error to call (*unregisterBuffer)() on a buffer that wasn't\n     * explicitly registered first.\n     */\n    int (*unregisterBuffer)(struct gralloc_module_t const* module,\n            buffer_handle_t handle);\n    \n    /*\n     * The (*lock)() method is called before a buffer is accessed for the \n     * specified usage. This call may block, for instance if the h/w needs\n     * to finish rendering or if CPU caches need to be synchronized.\n     * \n     * The caller promises to modify only pixels in the area specified \n     * by (l,t,w,h).\n     * \n     * The content of the buffer outside of the specified area is NOT modified\n     * by this call.\n     *\n     * If usage specifies GRALLOC_USAGE_SW_*, vaddr is filled with the address\n     * of the buffer in virtual memory.\n     *\n     * Note calling (*lock)() on HAL_PIXEL_FORMAT_YCbCr_*_888 buffers will fail\n     * and return -EINVAL.  These buffers must be locked with (*lock_ycbcr)()\n     * instead.\n     *\n     * THREADING CONSIDERATIONS:\n     *\n     * It is legal for several different threads to lock a buffer from \n     * read access, none of the threads are blocked.\n     * \n     * However, locking a buffer simultaneously for write or read/write is\n     * undefined, but:\n     * - shall not result in termination of the process\n     * - shall not block the caller\n     * It is acceptable to return an error or to leave the buffer's content\n     * into an indeterminate state.\n     *\n     * If the buffer was created with a usage mask incompatible with the\n     * requested usage flags here, -EINVAL is returned. \n     * \n     */\n    \n    int (*lock)(struct gralloc_module_t const* module,\n            buffer_handle_t handle, int usage,\n            int l, int t, int w, int h,\n            void** vaddr);\n\n    \n    /*\n     * The (*unlock)() method must be called after all changes to the buffer\n     * are completed.\n     */\n    \n    int (*unlock)(struct gralloc_module_t const* module,\n            buffer_handle_t handle);\n\n#ifdef EXYNOS4_ENHANCEMENTS\n    int (*getphys) (struct gralloc_module_t const* module,\n            buffer_handle_t handle, void** paddr);\n#endif\n\n    /* reserved for future use */\n    int (*perform)(struct gralloc_module_t const* module,\n            int operation, ... );\n\n    /*\n     * The (*lock_ycbcr)() method is like the (*lock)() method, with the\n     * difference that it fills a struct ycbcr with a description of the buffer\n     * layout, and zeroes out the reserved fields.\n     *\n     * If the buffer format is not compatible with a flexible YUV format (e.g.\n     * the buffer layout cannot be represented with the ycbcr struct), it\n     * will return -EINVAL.\n     *\n     * This method must work on buffers with HAL_PIXEL_FORMAT_YCbCr_*_888\n     * if supported by the device, as well as with any other format that is\n     * requested by the multimedia codecs when they are configured with a\n     * flexible-YUV-compatible color-format with android native buffers.\n     *\n     * Note that this method may also be called on buffers of other formats,\n     * including non-YUV formats.\n     *\n     * Added in GRALLOC_MODULE_API_VERSION_0_2.\n     */\n\n    int (*lock_ycbcr)(struct gralloc_module_t const* module,\n            buffer_handle_t handle, int usage,\n            int l, int t, int w, int h,\n            struct android_ycbcr *ycbcr);\n\n    /*\n     * The (*lockAsync)() method is like the (*lock)() method except\n     * that the buffer's sync fence object is passed into the lock\n     * call instead of requiring the caller to wait for completion.\n     *\n     * The gralloc implementation takes ownership of the fenceFd and\n     * is responsible for closing it when no longer needed.\n     *\n     * Added in GRALLOC_MODULE_API_VERSION_0_3.\n     */\n    int (*lockAsync)(struct gralloc_module_t const* module,\n            buffer_handle_t handle, int usage,\n            int l, int t, int w, int h,\n            void** vaddr, int fenceFd);\n\n    /*\n     * The (*unlockAsync)() method is like the (*unlock)() method\n     * except that a buffer sync fence object is returned from the\n     * lock call, representing the completion of any pending work\n     * performed by the gralloc implementation.\n     *\n     * The caller takes ownership of the fenceFd and is responsible\n     * for closing it when no longer needed.\n     *\n     * Added in GRALLOC_MODULE_API_VERSION_0_3.\n     */\n    int (*unlockAsync)(struct gralloc_module_t const* module,\n            buffer_handle_t handle, int* fenceFd);\n\n    /*\n     * The (*lockAsync_ycbcr)() method is like the (*lock_ycbcr)()\n     * method except that the buffer's sync fence object is passed\n     * into the lock call instead of requiring the caller to wait for\n     * completion.\n     *\n     * The gralloc implementation takes ownership of the fenceFd and\n     * is responsible for closing it when no longer needed.\n     *\n     * Added in GRALLOC_MODULE_API_VERSION_0_3.\n     */\n    int (*lockAsync_ycbcr)(struct gralloc_module_t const* module,\n            buffer_handle_t handle, int usage,\n            int l, int t, int w, int h,\n            struct android_ycbcr *ycbcr, int fenceFd);\n\n    /* reserved for future use */\n    void* reserved_proc[3];\n} gralloc_module_t;\n\n/*****************************************************************************/\n\n/**\n * Every device data structure must begin with hw_device_t\n * followed by module specific public methods and attributes.\n */\n\ntypedef struct alloc_device_t {\n    struct hw_device_t common;\n\n    /* \n     * (*alloc)() Allocates a buffer in graphic memory with the requested\n     * parameters and returns a buffer_handle_t and the stride in pixels to\n     * allow the implementation to satisfy hardware constraints on the width\n     * of a pixmap (eg: it may have to be multiple of 8 pixels). \n     * The CALLER TAKES OWNERSHIP of the buffer_handle_t.\n     *\n     * If format is HAL_PIXEL_FORMAT_YCbCr_420_888, the returned stride must be\n     * 0, since the actual strides are available from the android_ycbcr\n     * structure.\n     * \n     * Returns 0 on success or -errno on error.\n     */\n    \n    int (*alloc)(struct alloc_device_t* dev,\n            int w, int h, int format, int usage,\n            buffer_handle_t* handle, int* stride);\n\n    /*\n     * (*free)() Frees a previously allocated buffer. \n     * Behavior is undefined if the buffer is still mapped in any process,\n     * but shall not result in termination of the program or security breaches\n     * (allowing a process to get access to another process' buffers).\n     * THIS FUNCTION TAKES OWNERSHIP of the buffer_handle_t which becomes\n     * invalid after the call. \n     * \n     * Returns 0 on success or -errno on error.\n     */\n    int (*free)(struct alloc_device_t* dev,\n            buffer_handle_t handle);\n\n    /* This hook is OPTIONAL.\n     *\n     * If non NULL it will be caused by SurfaceFlinger on dumpsys\n     */\n    void (*dump)(struct alloc_device_t *dev, char *buff, int buff_len);\n\n    void* reserved_proc[7];\n} alloc_device_t;\n\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int gralloc_open(const struct hw_module_t* module, \n        struct alloc_device_t** device) {\n    return module->methods->open(module, \n            GRALLOC_HARDWARE_GPU0, (struct hw_device_t**)device);\n}\n\nstatic inline int gralloc_close(struct alloc_device_t* device) {\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif  // ANDROID_GRALLOC_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/hardware.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_HARDWARE_H\n#define ANDROID_INCLUDE_HARDWARE_HARDWARE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n\n#include <cutils/native_handle.h>\n#include <system/graphics.h>\n\n__BEGIN_DECLS\n\n/*\n * Value for the hw_module_t.tag field\n */\n\n#define MAKE_TAG_CONSTANT(A,B,C,D) (((A) << 24) | ((B) << 16) | ((C) << 8) | (D))\n\n#define HARDWARE_MODULE_TAG MAKE_TAG_CONSTANT('H', 'W', 'M', 'T')\n#define HARDWARE_DEVICE_TAG MAKE_TAG_CONSTANT('H', 'W', 'D', 'T')\n\n#define HARDWARE_MAKE_API_VERSION(maj,min) \\\n            ((((maj) & 0xff) << 8) | ((min) & 0xff))\n\n#define HARDWARE_MAKE_API_VERSION_2(maj,min,hdr) \\\n            ((((maj) & 0xff) << 24) | (((min) & 0xff) << 16) | ((hdr) & 0xffff))\n#define HARDWARE_API_VERSION_2_MAJ_MIN_MASK 0xffff0000\n#define HARDWARE_API_VERSION_2_HEADER_MASK  0x0000ffff\n\n\n/*\n * The current HAL API version.\n *\n * All module implementations must set the hw_module_t.hal_api_version field\n * to this value when declaring the module with HAL_MODULE_INFO_SYM.\n *\n * Note that previous implementations have always set this field to 0.\n * Therefore, libhardware HAL API will always consider versions 0.0 and 1.0\n * to be 100% binary compatible.\n *\n */\n#define HARDWARE_HAL_API_VERSION HARDWARE_MAKE_API_VERSION(1, 0)\n\n/*\n * Helper macros for module implementors.\n *\n * The derived modules should provide convenience macros for supported\n * versions so that implementations can explicitly specify module/device\n * versions at definition time.\n *\n * Use this macro to set the hw_module_t.module_api_version field.\n */\n#define HARDWARE_MODULE_API_VERSION(maj,min) HARDWARE_MAKE_API_VERSION(maj,min)\n#define HARDWARE_MODULE_API_VERSION_2(maj,min,hdr) HARDWARE_MAKE_API_VERSION_2(maj,min,hdr)\n\n/*\n * Use this macro to set the hw_device_t.version field\n */\n#define HARDWARE_DEVICE_API_VERSION(maj,min) HARDWARE_MAKE_API_VERSION(maj,min)\n#define HARDWARE_DEVICE_API_VERSION_2(maj,min,hdr) HARDWARE_MAKE_API_VERSION_2(maj,min,hdr)\n\nstruct hw_module_t;\nstruct hw_module_methods_t;\nstruct hw_device_t;\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\ntypedef struct hw_module_t {\n    /** tag must be initialized to HARDWARE_MODULE_TAG */\n    uint32_t tag;\n\n    /**\n     * The API version of the implemented module. The module owner is\n     * responsible for updating the version when a module interface has\n     * changed.\n     *\n     * The derived modules such as gralloc and audio own and manage this field.\n     * The module user must interpret the version field to decide whether or\n     * not to inter-operate with the supplied module implementation.\n     * For example, SurfaceFlinger is responsible for making sure that\n     * it knows how to manage different versions of the gralloc-module API,\n     * and AudioFlinger must know how to do the same for audio-module API.\n     *\n     * The module API version should include a major and a minor component.\n     * For example, version 1.0 could be represented as 0x0100. This format\n     * implies that versions 0x0100-0x01ff are all API-compatible.\n     *\n     * In the future, libhardware will expose a hw_get_module_version()\n     * (or equivalent) function that will take minimum/maximum supported\n     * versions as arguments and would be able to reject modules with\n     * versions outside of the supplied range.\n     */\n    uint16_t module_api_version;\n#define version_major module_api_version\n    /**\n     * version_major/version_minor defines are supplied here for temporary\n     * source code compatibility. They will be removed in the next version.\n     * ALL clients must convert to the new version format.\n     */\n\n    /**\n     * The API version of the HAL module interface. This is meant to\n     * version the hw_module_t, hw_module_methods_t, and hw_device_t\n     * structures and definitions.\n     *\n     * The HAL interface owns this field. Module users/implementations\n     * must NOT rely on this value for version information.\n     *\n     * Presently, 0 is the only valid value.\n     */\n    uint16_t hal_api_version;\n#define version_minor hal_api_version\n\n    /** Identifier of module */\n    const char *id;\n\n    /** Name of this module */\n    const char *name;\n\n    /** Author/owner/implementor of the module */\n    const char *author;\n\n    /** Modules methods */\n    struct hw_module_methods_t* methods;\n\n    /** module's dso */\n    void* dso;\n\n#ifdef __LP64__\n    uint64_t reserved[32-7];\n#else\n    /** padding to 128 bytes, reserved for future use */\n    uint32_t reserved[32-7];\n#endif\n\n} hw_module_t;\n\ntypedef struct hw_module_methods_t {\n    /** Open a specific device */\n    int (*open)(const struct hw_module_t* module, const char* id,\n            struct hw_device_t** device);\n\n} hw_module_methods_t;\n\n/**\n * Every device data structure must begin with hw_device_t\n * followed by module specific public methods and attributes.\n */\ntypedef struct hw_device_t {\n    /** tag must be initialized to HARDWARE_DEVICE_TAG */\n    uint32_t tag;\n\n    /**\n     * Version of the module-specific device API. This value is used by\n     * the derived-module user to manage different device implementations.\n     *\n     * The module user is responsible for checking the module_api_version\n     * and device version fields to ensure that the user is capable of\n     * communicating with the specific module implementation.\n     *\n     * One module can support multiple devices with different versions. This\n     * can be useful when a device interface changes in an incompatible way\n     * but it is still necessary to support older implementations at the same\n     * time. One such example is the Camera 2.0 API.\n     *\n     * This field is interpreted by the module user and is ignored by the\n     * HAL interface itself.\n     */\n    uint32_t version;\n\n    /** reference to the module this device belongs to */\n    struct hw_module_t* module;\n\n    /** padding reserved for future use */\n#ifdef __LP64__\n    uint64_t reserved[12];\n#else\n    uint32_t reserved[12];\n#endif\n\n    /** Close this device */\n    int (*close)(struct hw_device_t* device);\n\n} hw_device_t;\n\n/**\n * Name of the hal_module_info\n */\n#define HAL_MODULE_INFO_SYM         HMI\n\n/**\n * Name of the hal_module_info as a string\n */\n#define HAL_MODULE_INFO_SYM_AS_STR  \"HMI\"\n\n/**\n * Get the module info associated with a module by id.\n *\n * @return: 0 == success, <0 == error and *module == NULL\n */\nint hw_get_module(const char *id, const struct hw_module_t **module);\n\n/**\n * Get the module info associated with a module instance by class 'class_id'\n * and instance 'inst'.\n *\n * Some modules types necessitate multiple instances. For example audio supports\n * multiple concurrent interfaces and thus 'audio' is the module class\n * and 'primary' or 'a2dp' are module interfaces. This implies that the files\n * providing these modules would be named audio.primary.<variant>.so and\n * audio.a2dp.<variant>.so\n *\n * @return: 0 == success, <0 == error and *module == NULL\n */\nint hw_get_module_by_class(const char *class_id, const char *inst,\n                           const struct hw_module_t **module);\n\n__END_DECLS\n\n#endif  /* ANDROID_INCLUDE_HARDWARE_HARDWARE_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/hdmi_cec.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_HDMI_CEC_H\n#define ANDROID_INCLUDE_HARDWARE_HDMI_CEC_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define HDMI_CEC_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define HDMI_CEC_MODULE_API_VERSION_CURRENT HDMI_MODULE_API_VERSION_1_0\n\n#define HDMI_CEC_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n#define HDMI_CEC_DEVICE_API_VERSION_CURRENT HDMI_DEVICE_API_VERSION_1_0\n\n#define HDMI_CEC_HARDWARE_MODULE_ID \"hdmi_cec\"\n#define HDMI_CEC_HARDWARE_INTERFACE \"hdmi_cec_hw_if\"\n\ntypedef enum cec_device_type {\n    CEC_DEVICE_INACTIVE = -1,\n    CEC_DEVICE_TV = 0,\n    CEC_DEVICE_RECORDER = 1,\n    CEC_DEVICE_RESERVED = 2,\n    CEC_DEVICE_TUNER = 3,\n    CEC_DEVICE_PLAYBACK = 4,\n    CEC_DEVICE_AUDIO_SYSTEM = 5,\n    CEC_DEVICE_MAX = CEC_DEVICE_AUDIO_SYSTEM\n} cec_device_type_t;\n\ntypedef enum cec_logical_address {\n    CEC_ADDR_TV = 0,\n    CEC_ADDR_RECORDER_1 = 1,\n    CEC_ADDR_RECORDER_2 = 2,\n    CEC_ADDR_TUNER_1 = 3,\n    CEC_ADDR_PLAYBACK_1 = 4,\n    CEC_ADDR_AUDIO_SYSTEM = 5,\n    CEC_ADDR_TUNER_2 = 6,\n    CEC_ADDR_TUNER_3 = 7,\n    CEC_ADDR_PLAYBACK_2 = 8,\n    CEC_ADDR_RECORDER_3 = 9,\n    CEC_ADDR_TUNER_4 = 10,\n    CEC_ADDR_PLAYBACK_3 = 11,\n    CEC_ADDR_RESERVED_1 = 12,\n    CEC_ADDR_RESERVED_2 = 13,\n    CEC_ADDR_FREE_USE = 14,\n    CEC_ADDR_UNREGISTERED = 15,\n    CEC_ADDR_BROADCAST = 15\n} cec_logical_address_t;\n\n/*\n * HDMI CEC messages\n */\nenum cec_message_type {\n    CEC_MESSAGE_FEATURE_ABORT = 0x00,\n    CEC_MESSAGE_IMAGE_VIEW_ON = 0x04,\n    CEC_MESSAGE_TUNER_STEP_INCREMENT = 0x05,\n    CEC_MESSAGE_TUNER_STEP_DECREMENT = 0x06,\n    CEC_MESSAGE_TUNER_DEVICE_STATUS = 0x07,\n    CEC_MESSAGE_GIVE_TUNER_DEVICE_STATUS = 0x08,\n    CEC_MESSAGE_RECORD_ON = 0x09,\n    CEC_MESSAGE_RECORD_STATUS = 0x0A,\n    CEC_MESSAGE_RECORD_OFF = 0x0B,\n    CEC_MESSAGE_TEXT_VIEW_ON = 0x0D,\n    CEC_MESSAGE_RECORD_TV_SCREEN = 0x0F,\n    CEC_MESSAGE_GIVE_DECK_STATUS = 0x1A,\n    CEC_MESSAGE_DECK_STATUS = 0x1B,\n    CEC_MESSAGE_SET_MENU_LANGUAGE = 0x32,\n    CEC_MESSAGE_CLEAR_ANALOG_TIMER = 0x33,\n    CEC_MESSAGE_SET_ANALOG_TIMER = 0x34,\n    CEC_MESSAGE_TIMER_STATUS = 0x35,\n    CEC_MESSAGE_STANDBY = 0x36,\n    CEC_MESSAGE_PLAY = 0x41,\n    CEC_MESSAGE_DECK_CONTROL = 0x42,\n    CEC_MESSAGE_TIMER_CLEARED_STATUS = 0x043,\n    CEC_MESSAGE_USER_CONTROL_PRESSED = 0x44,\n    CEC_MESSAGE_USER_CONTROL_RELEASED = 0x45,\n    CEC_MESSAGE_GIVE_OSD_NAME = 0x46,\n    CEC_MESSAGE_SET_OSD_NAME = 0x47,\n    CEC_MESSAGE_SET_OSD_STRING = 0x64,\n    CEC_MESSAGE_SET_TIMER_PROGRAM_TITLE = 0x67,\n    CEC_MESSAGE_SYSTEM_AUDIO_MODE_REQUEST = 0x70,\n    CEC_MESSAGE_GIVE_AUDIO_STATUS = 0x71,\n    CEC_MESSAGE_SET_SYSTEM_AUDIO_MODE = 0x72,\n    CEC_MESSAGE_REPORT_AUDIO_STATUS = 0x7A,\n    CEC_MESSAGE_GIVE_SYSTEM_AUDIO_MODE_STATUS = 0x7D,\n    CEC_MESSAGE_SYSTEM_AUDIO_MODE_STATUS = 0x7E,\n    CEC_MESSAGE_ROUTING_CHANGE = 0x80,\n    CEC_MESSAGE_ROUTING_INFORMATION = 0x81,\n    CEC_MESSAGE_ACTIVE_SOURCE = 0x82,\n    CEC_MESSAGE_GIVE_PHYSICAL_ADDRESS = 0x83,\n    CEC_MESSAGE_REPORT_PHYSICAL_ADDRESS = 0x84,\n    CEC_MESSAGE_REQUEST_ACTIVE_SOURCE = 0x85,\n    CEC_MESSAGE_SET_STREAM_PATH = 0x86,\n    CEC_MESSAGE_DEVICE_VENDOR_ID = 0x87,\n    CEC_MESSAGE_VENDOR_COMMAND = 0x89,\n    CEC_MESSAGE_VENDOR_REMOTE_BUTTON_DOWN = 0x8A,\n    CEC_MESSAGE_VENDOR_REMOTE_BUTTON_UP = 0x8B,\n    CEC_MESSAGE_GIVE_DEVICE_VENDOR_ID = 0x8C,\n    CEC_MESSAGE_MENU_REQUEST = 0x8D,\n    CEC_MESSAGE_MENU_STATUS = 0x8E,\n    CEC_MESSAGE_GIVE_DEVICE_POWER_STATUS = 0x8F,\n    CEC_MESSAGE_REPORT_POWER_STATUS = 0x90,\n    CEC_MESSAGE_GET_MENU_LANGUAGE = 0x91,\n    CEC_MESSAGE_SELECT_ANALOG_SERVICE = 0x92,\n    CEC_MESSAGE_SELECT_DIGITAL_SERVICE = 0x93,\n    CEC_MESSAGE_SET_DIGITAL_TIMER = 0x97,\n    CEC_MESSAGE_CLEAR_DIGITAL_TIMER = 0x99,\n    CEC_MESSAGE_SET_AUDIO_RATE = 0x9A,\n    CEC_MESSAGE_INACTIVE_SOURCE = 0x9D,\n    CEC_MESSAGE_CEC_VERSION = 0x9E,\n    CEC_MESSAGE_GET_CEC_VERSION = 0x9F,\n    CEC_MESSAGE_VENDOR_COMMAND_WITH_ID = 0xA0,\n    CEC_MESSAGE_CLEAR_EXTERNAL_TIMER = 0xA1,\n    CEC_MESSAGE_SET_EXTERNAL_TIMER = 0xA2,\n    CEC_MESSAGE_INITIATE_ARC = 0xC0,\n    CEC_MESSAGE_REPORT_ARC_INITIATED = 0xC1,\n    CEC_MESSAGE_REPORT_ARC_TERMINATED = 0xC2,\n    CEC_MESSAGE_REQUEST_ARC_INITIATION = 0xC3,\n    CEC_MESSAGE_REQUEST_ARC_TERMINATION = 0xC4,\n    CEC_MESSAGE_TERMINATE_ARC = 0xC5,\n    CEC_MESSAGE_ABORT = 0xFF\n};\n\n/*\n * Operand description [Abort Reason]\n */\nenum abort_reason {\n    ABORT_UNRECOGNIZED_MODE = 0,\n    ABORT_NOT_IN_CORRECT_MODE = 1,\n    ABORT_CANNOT_PROVIDE_SOURCE = 2,\n    ABORT_INVALID_OPERAND = 3,\n    ABORT_REFUSED = 4,\n    ABORT_UNABLE_TO_DETERMINE = 5\n};\n\n/*\n * HDMI event type. used for hdmi_event_t.\n */\nenum {\n    HDMI_EVENT_CEC_MESSAGE = 1,\n    HDMI_EVENT_HOT_PLUG = 2,\n};\n\n/*\n * HDMI hotplug event type. Used when the event\n * type is HDMI_EVENT_HOT_PLUG.\n */\nenum {\n    HDMI_NOT_CONNECTED = 0,\n    HDMI_CONNECTED = 1\n};\n\n/*\n * error code used for send_message.\n */\nenum {\n    HDMI_RESULT_SUCCESS = 0,\n    HDMI_RESULT_NACK = 1,        /* not acknowledged */\n    HDMI_RESULT_BUSY = 2,        /* bus is busy */\n    HDMI_RESULT_FAIL = 3,\n};\n\n/*\n * HDMI port type.\n */\ntypedef enum hdmi_port_type {\n    HDMI_INPUT = 0,\n    HDMI_OUTPUT = 1\n} hdmi_port_type_t;\n\n/*\n * Flags used for set_option()\n */\nenum {\n    /* When set to false, HAL does not wake up the system upon receiving\n     * <Image View On> or <Text View On>. Used when user changes the TV\n     * settings to disable the auto TV on functionality.\n     * True by default.\n     */\n    HDMI_OPTION_WAKEUP = 1,\n\n    /* When set to false, all the CEC commands are discarded. Used when\n     * user changes the TV settings to disable CEC functionality.\n     * True by default.\n     */\n    HDMI_OPTION_ENABLE_CEC = 2,\n\n    /* Setting this flag to false means Android system will stop handling\n     * CEC service and yield the control over to the microprocessor that is\n     * powered on through the standby mode. When set to true, the system\n     * will gain the control over, hence telling the microprocessor to stop\n     * handling the cec commands. This is called when system goes\n     * in and out of standby mode to notify the microprocessor that it should\n     * start/stop handling CEC commands on behalf of the system.\n     * False by default.\n     */\n    HDMI_OPTION_SYSTEM_CEC_CONTROL = 3,\n\n    /* Option 4 not used */\n\n    /* Passes the updated language information of Android system.\n     * Contains 3-byte ASCII code as defined in ISO/FDIS 639-2. Can be\n     * used for HAL to respond to <Get Menu Language> while in standby mode.\n     * English(eng), for example, is converted to 0x656e67.\n     */\n    HDMI_OPTION_SET_LANG = 5,\n};\n\n/*\n * Maximum length in bytes of cec message body (exclude header block),\n * should not exceed 16 (spec CEC 6 Frame Description)\n */\n#define CEC_MESSAGE_BODY_MAX_LENGTH 16\n\ntypedef struct cec_message {\n    /* logical address of sender */\n    cec_logical_address_t initiator;\n\n    /* logical address of receiver */\n    cec_logical_address_t destination;\n\n    /* Length in bytes of body, range [0, CEC_MESSAGE_BODY_MAX_LENGTH] */\n    size_t length;\n    unsigned char body[CEC_MESSAGE_BODY_MAX_LENGTH];\n} cec_message_t;\n\ntypedef struct hotplug_event {\n    /*\n     * true if the cable is connected; otherwise false.\n     */\n    int connected;\n    int port_id;\n} hotplug_event_t;\n\ntypedef struct tx_status_event {\n    int status;\n    int opcode;  /* CEC opcode */\n} tx_status_event_t;\n\n/*\n * HDMI event generated from HAL.\n */\ntypedef struct hdmi_event {\n    int type;\n    struct hdmi_cec_device* dev;\n    union {\n        cec_message_t cec;\n        hotplug_event_t hotplug;\n    };\n} hdmi_event_t;\n\n/*\n * HDMI port descriptor\n */\ntypedef struct hdmi_port_info {\n    hdmi_port_type_t type;\n    // Port ID should start from 1 which corresponds to HDMI \"port 1\".\n    int port_id;\n    int cec_supported;\n    int arc_supported;\n    uint16_t physical_address;\n} hdmi_port_info_t;\n\n/*\n * Callback function type that will be called by HAL implementation.\n * Services can not close/open the device in the callback.\n */\ntypedef void (*event_callback_t)(const hdmi_event_t* event, void* arg);\n\ntypedef struct hdmi_cec_module {\n    /**\n     * Common methods of the HDMI CEC module.  This *must* be the first member of\n     * hdmi_cec_module as users of this structure will cast a hw_module_t to hdmi_cec_module\n     * pointer in contexts where it's known the hw_module_t references a hdmi_cec_module.\n     */\n    struct hw_module_t common;\n} hdmi_module_t;\n\n/*\n * HDMI-CEC HAL interface definition.\n */\ntypedef struct hdmi_cec_device {\n    /**\n     * Common methods of the HDMI CEC device.  This *must* be the first member of\n     * hdmi_cec_device as users of this structure will cast a hw_device_t to hdmi_cec_device\n     * pointer in contexts where it's known the hw_device_t references a hdmi_cec_device.\n     */\n    struct hw_device_t common;\n\n    /*\n     * (*add_logical_address)() passes the logical address that will be used\n     * in this system.\n     *\n     * HAL may use it to configure the hardware so that the CEC commands addressed\n     * the given logical address can be filtered in. This method can be called\n     * as many times as necessary in order to support multiple logical devices.\n     * addr should be in the range of valid logical addresses for the call\n     * to succeed.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*add_logical_address)(const struct hdmi_cec_device* dev, cec_logical_address_t addr);\n\n    /*\n     * (*clear_logical_address)() tells HAL to reset all the logical addresses.\n     *\n     * It is used when the system doesn't need to process CEC command any more,\n     * hence to tell HAL to stop receiving commands from the CEC bus, and change\n     * the state back to the beginning.\n     */\n    void (*clear_logical_address)(const struct hdmi_cec_device* dev);\n\n    /*\n     * (*get_physical_address)() returns the CEC physical address. The\n     * address is written to addr.\n     *\n     * The physical address depends on the topology of the network formed\n     * by connected HDMI devices. It is therefore likely to change if the cable\n     * is plugged off and on again. It is advised to call get_physical_address\n     * to get the updated address when hot plug event takes place.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*get_physical_address)(const struct hdmi_cec_device* dev, uint16_t* addr);\n\n    /*\n     * (*send_message)() transmits HDMI-CEC message to other HDMI device.\n     *\n     * The method should be designed to return in a certain amount of time not\n     * hanging forever, which can happen if CEC signal line is pulled low for\n     * some reason. HAL implementation should take the situation into account\n     * so as not to wait forever for the message to get sent out.\n     *\n     * It should try retransmission at least once as specified in the standard.\n     *\n     * Returns error code. See HDMI_RESULT_SUCCESS, HDMI_RESULT_NACK, and\n     * HDMI_RESULT_BUSY.\n     */\n    int (*send_message)(const struct hdmi_cec_device* dev, const cec_message_t*);\n\n    /*\n     * (*register_event_callback)() registers a callback that HDMI-CEC HAL\n     * can later use for incoming CEC messages or internal HDMI events.\n     * When calling from C++, use the argument arg to pass the calling object.\n     * It will be passed back when the callback is invoked so that the context\n     * can be retrieved.\n     */\n    void (*register_event_callback)(const struct hdmi_cec_device* dev,\n            event_callback_t callback, void* arg);\n\n    /*\n     * (*get_version)() returns the CEC version supported by underlying hardware.\n     */\n    void (*get_version)(const struct hdmi_cec_device* dev, int* version);\n\n    /*\n     * (*get_vendor_id)() returns the identifier of the vendor. It is\n     * the 24-bit unique company ID obtained from the IEEE Registration\n     * Authority Committee (RAC).\n     */\n    void (*get_vendor_id)(const struct hdmi_cec_device* dev, uint32_t* vendor_id);\n\n    /*\n     * (*get_port_info)() returns the hdmi port information of underlying hardware.\n     * info is the list of HDMI port information, and 'total' is the number of\n     * HDMI ports in the system.\n     */\n    void (*get_port_info)(const struct hdmi_cec_device* dev,\n            struct hdmi_port_info* list[], int* total);\n\n    /*\n     * (*set_option)() passes flags controlling the way HDMI-CEC service works down\n     * to HAL implementation. Those flags will be used in case the feature needs\n     * update in HAL itself, firmware or microcontroller.\n     */\n    void (*set_option)(const struct hdmi_cec_device* dev, int flag, int value);\n\n    /*\n     * (*set_audio_return_channel)() configures ARC circuit in the hardware logic\n     * to start or stop the feature. Flag can be either 1 to start the feature\n     * or 0 to stop it.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    void (*set_audio_return_channel)(const struct hdmi_cec_device* dev, int port_id, int flag);\n\n    /*\n     * (*is_connected)() returns the connection status of the specified port.\n     * Returns HDMI_CONNECTED if a device is connected, otherwise HDMI_NOT_CONNECTED.\n     * The HAL should watch for +5V power signal to determine the status.\n     */\n    int (*is_connected)(const struct hdmi_cec_device* dev, int port_id);\n\n    /* Reserved for future use to maximum 16 functions. Must be NULL. */\n    void* reserved[16 - 11];\n} hdmi_cec_device_t;\n\n/** convenience API for opening and closing a device */\n\nstatic inline int hdmi_cec_open(const struct hw_module_t* module,\n        struct hdmi_cec_device** device) {\n    return module->methods->open(module,\n            HDMI_CEC_HARDWARE_INTERFACE, (struct hw_device_t**)device);\n}\n\nstatic inline int hdmi_cec_close(struct hdmi_cec_device* device) {\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_HARDWARE_HDMI_CEC_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/hw_auth_token.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdint.h>\n\n#ifndef ANDROID_HARDWARE_HW_AUTH_TOKEN_H\n#define ANDROID_HARDWARE_HW_AUTH_TOKEN_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif  // __cplusplus\n\nconst uint8_t HW_AUTH_TOKEN_VERSION = 0;\n\ntypedef enum {\n    HW_AUTH_NONE = 0,\n    HW_AUTH_PASSWORD = 1 << 0,\n    HW_AUTH_FINGERPRINT = 1 << 1,\n    // Additional entries should be powers of 2.\n    HW_AUTH_ANY = UINT32_MAX,\n} hw_authenticator_type_t;\n\n/**\n * Data format for an authentication record used to prove successful authentication.\n */\ntypedef struct __attribute__((__packed__)) {\n    uint8_t version;  // Current version is 0\n    uint64_t challenge;\n    uint64_t user_id;             // secure user ID, not Android user ID\n    uint64_t authenticator_id;    // secure authenticator ID\n    uint32_t authenticator_type;  // hw_authenticator_type_t, in network order\n    uint64_t timestamp;           // in network order\n    uint8_t hmac[32];\n} hw_auth_token_t;\n\n#ifdef __cplusplus\n}  // extern \"C\"\n#endif  // __cplusplus\n\n#endif  // ANDROID_HARDWARE_HW_AUTH_TOKEN_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/hwcomposer.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_HWCOMPOSER_H\n#define ANDROID_INCLUDE_HARDWARE_HWCOMPOSER_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n\n#include <hardware/gralloc.h>\n#include <hardware/hardware.h>\n#include <cutils/native_handle.h>\n\n#include <hardware/hwcomposer_defs.h>\n\n__BEGIN_DECLS\n\n/*****************************************************************************/\n\n/* for compatibility */\n#define HWC_MODULE_API_VERSION      HWC_MODULE_API_VERSION_0_1\n#define HWC_DEVICE_API_VERSION      HWC_DEVICE_API_VERSION_0_1\n#define HWC_API_VERSION             HWC_DEVICE_API_VERSION\n\n/*****************************************************************************/\n\n/**\n * The id of this module\n */\n#define HWC_HARDWARE_MODULE_ID \"hwcomposer\"\n\n/**\n * Name of the sensors device to open\n */\n#define HWC_HARDWARE_COMPOSER   \"composer\"\n\ntypedef struct hwc_rect {\n    int left;\n    int top;\n    int right;\n    int bottom;\n} hwc_rect_t;\n\ntypedef struct hwc_frect {\n    float left;\n    float top;\n    float right;\n    float bottom;\n} hwc_frect_t;\n\ntypedef struct hwc_region {\n    size_t numRects;\n    hwc_rect_t const* rects;\n} hwc_region_t;\n\ntypedef struct hwc_color {\n    uint8_t r;\n    uint8_t g;\n    uint8_t b;\n    uint8_t a;\n} hwc_color_t;\n\ntypedef struct hwc_layer_1 {\n    /*\n     * compositionType is used to specify this layer's type and is set by either\n     * the hardware composer implementation, or by the caller (see below).\n     *\n     *  This field is always reset to HWC_BACKGROUND or HWC_FRAMEBUFFER\n     *  before (*prepare)() is called when the HWC_GEOMETRY_CHANGED flag is\n     *  also set, otherwise, this field is preserved between (*prepare)()\n     *  calls.\n     *\n     * HWC_BACKGROUND\n     *   Always set by the caller before calling (*prepare)(), this value\n     *   indicates this is a special \"background\" layer. The only valid field\n     *   is backgroundColor.\n     *   The HWC can toggle this value to HWC_FRAMEBUFFER to indicate it CANNOT\n     *   handle the background color.\n     *\n     *\n     * HWC_FRAMEBUFFER_TARGET\n     *   Always set by the caller before calling (*prepare)(), this value\n     *   indicates this layer is the framebuffer surface used as the target of\n     *   OpenGL ES composition. If the HWC sets all other layers to HWC_OVERLAY\n     *   or HWC_BACKGROUND, then no OpenGL ES composition will be done, and\n     *   this layer should be ignored during set().\n     *\n     *   This flag (and the framebuffer surface layer) will only be used if the\n     *   HWC version is HWC_DEVICE_API_VERSION_1_1 or higher. In older versions,\n     *   the OpenGL ES target surface is communicated by the (dpy, sur) fields\n     *   in hwc_compositor_device_1_t.\n     *\n     *   This value cannot be set by the HWC implementation.\n     *\n     *\n     * HWC_FRAMEBUFFER\n     *   Set by the caller before calling (*prepare)() ONLY when the\n     *   HWC_GEOMETRY_CHANGED flag is also set.\n     *\n     *   Set by the HWC implementation during (*prepare)(), this indicates\n     *   that the layer will be drawn into the framebuffer using OpenGL ES.\n     *   The HWC can toggle this value to HWC_OVERLAY to indicate it will\n     *   handle the layer.\n     *\n     *\n     * HWC_OVERLAY\n     *   Set by the HWC implementation during (*prepare)(), this indicates\n     *   that the layer will be handled by the HWC (ie: it must not be\n     *   composited with OpenGL ES).\n     *\n     *\n     * HWC_SIDEBAND\n     *   Set by the caller before calling (*prepare)(), this value indicates\n     *   the contents of this layer come from a sideband video stream.\n     *\n     *   The h/w composer is responsible for receiving new image buffers from\n     *   the stream at the appropriate time (e.g. synchronized to a separate\n     *   audio stream), compositing them with the current contents of other\n     *   layers, and displaying the resulting image. This happens\n     *   independently of the normal prepare/set cycle. The prepare/set calls\n     *   only happen when other layers change, or when properties of the\n     *   sideband layer such as position or size change.\n     *\n     *   If the h/w composer can't handle the layer as a sideband stream for\n     *   some reason (e.g. unsupported scaling/blending/rotation, or too many\n     *   sideband layers) it can set compositionType to HWC_FRAMEBUFFER in\n     *   (*prepare)(). However, doing so will result in the layer being shown\n     *   as a solid color since the platform is not currently able to composite\n     *   sideband layers with the GPU. This may be improved in future\n     *   versions of the platform.\n     *\n     *\n     * HWC_CURSOR_OVERLAY\n     *   Set by the HWC implementation during (*prepare)(), this value\n     *   indicates the layer's composition will now be handled by the HWC.\n     *   Additionally, the client can now asynchronously update the on-screen\n     *   position of this layer using the setCursorPositionAsync() api.\n     */\n    int32_t compositionType;\n\n    /*\n     * hints is bit mask set by the HWC implementation during (*prepare)().\n     * It is preserved between (*prepare)() calls, unless the\n     * HWC_GEOMETRY_CHANGED flag is set, in which case it is reset to 0.\n     *\n     * see hwc_layer_t::hints\n     */\n    uint32_t hints;\n\n    /* see hwc_layer_t::flags */\n    uint32_t flags;\n\n    union {\n        /* color of the background.  hwc_color_t.a is ignored */\n        hwc_color_t backgroundColor;\n\n        struct {\n            union {\n                /* When compositionType is HWC_FRAMEBUFFER, HWC_OVERLAY,\n                 * HWC_FRAMEBUFFER_TARGET, this is the handle of the buffer to\n                 * compose. This handle is guaranteed to have been allocated\n                 * from gralloc using the GRALLOC_USAGE_HW_COMPOSER usage flag.\n                 * If the layer's handle is unchanged across two consecutive\n                 * prepare calls and the HWC_GEOMETRY_CHANGED flag is not set\n                 * for the second call then the HWComposer implementation may\n                 * assume that the contents of the buffer have not changed. */\n                buffer_handle_t handle;\n\n                /* When compositionType is HWC_SIDEBAND, this is the handle\n                 * of the sideband video stream to compose. */\n                const native_handle_t* sidebandStream;\n            };\n\n            /* transformation to apply to the buffer during composition */\n            uint32_t transform;\n\n            /* blending to apply during composition */\n            int32_t blending;\n\n            /* area of the source to consider, the origin is the top-left corner of\n             * the buffer. As of HWC_DEVICE_API_VERSION_1_3, sourceRect uses floats.\n             * If the h/w can't support a non-integer source crop rectangle, it should\n             * punt to OpenGL ES composition.\n             */\n            union {\n                // crop rectangle in integer (pre HWC_DEVICE_API_VERSION_1_3)\n                hwc_rect_t sourceCropi;\n                hwc_rect_t sourceCrop; // just for source compatibility\n                // crop rectangle in floats (as of HWC_DEVICE_API_VERSION_1_3)\n                hwc_frect_t sourceCropf;\n            };\n\n            /* where to composite the sourceCrop onto the display. The sourceCrop\n             * is scaled using linear filtering to the displayFrame. The origin is the\n             * top-left corner of the screen.\n             */\n            hwc_rect_t displayFrame;\n\n            /* visible region in screen space. The origin is the\n             * top-left corner of the screen.\n             * The visible region INCLUDES areas overlapped by a translucent layer.\n             */\n            hwc_region_t visibleRegionScreen;\n\n            /* Sync fence object that will be signaled when the buffer's\n             * contents are available. May be -1 if the contents are already\n             * available. This field is only valid during set(), and should be\n             * ignored during prepare(). The set() call must not wait for the\n             * fence to be signaled before returning, but the HWC must wait for\n             * all buffers to be signaled before reading from them.\n             *\n             * HWC_FRAMEBUFFER layers will never have an acquire fence, since\n             * reads from them are complete before the framebuffer is ready for\n             * display.\n             *\n             * HWC_SIDEBAND layers will never have an acquire fence, since\n             * synchronization is handled through implementation-defined\n             * sideband mechanisms.\n             *\n             * The HWC takes ownership of the acquireFenceFd and is responsible\n             * for closing it when no longer needed.\n             */\n            int acquireFenceFd;\n\n            /* During set() the HWC must set this field to a file descriptor for\n             * a sync fence object that will signal after the HWC has finished\n             * reading from the buffer. The field is ignored by prepare(). Each\n             * layer should have a unique file descriptor, even if more than one\n             * refer to the same underlying fence object; this allows each to be\n             * closed independently.\n             *\n             * If buffer reads can complete at significantly different times,\n             * then using independent fences is preferred. For example, if the\n             * HWC handles some layers with a blit engine and others with\n             * overlays, then the blit layers can be reused immediately after\n             * the blit completes, but the overlay layers can't be reused until\n             * a subsequent frame has been displayed.\n             *\n             * Since HWC doesn't read from HWC_FRAMEBUFFER layers, it shouldn't\n             * produce a release fence for them. The releaseFenceFd will be -1\n             * for these layers when set() is called.\n             *\n             * Since HWC_SIDEBAND buffers don't pass through the HWC client,\n             * the HWC shouldn't produce a release fence for them. The\n             * releaseFenceFd will be -1 for these layers when set() is called.\n             *\n             * The HWC client taks ownership of the releaseFenceFd and is\n             * responsible for closing it when no longer needed.\n             */\n            int releaseFenceFd;\n\n            /*\n             * Availability: HWC_DEVICE_API_VERSION_1_2\n             *\n             * Alpha value applied to the whole layer. The effective\n             * value of each pixel is computed as:\n             *\n             *   if (blending == HWC_BLENDING_PREMULT)\n             *      pixel.rgb = pixel.rgb * planeAlpha / 255\n             *   pixel.a = pixel.a * planeAlpha / 255\n             *\n             * Then blending proceeds as usual according to the \"blending\"\n             * field above.\n             *\n             * NOTE: planeAlpha applies to YUV layers as well:\n             *\n             *   pixel.rgb = yuv_to_rgb(pixel.yuv)\n             *   if (blending == HWC_BLENDING_PREMULT)\n             *      pixel.rgb = pixel.rgb * planeAlpha / 255\n             *   pixel.a = planeAlpha\n             *\n             *\n             * IMPLEMENTATION NOTE:\n             *\n             * If the source image doesn't have an alpha channel, then\n             * the h/w can use the HWC_BLENDING_COVERAGE equations instead of\n             * HWC_BLENDING_PREMULT and simply set the alpha channel to\n             * planeAlpha.\n             *\n             * e.g.:\n             *\n             *   if (blending == HWC_BLENDING_PREMULT)\n             *      blending = HWC_BLENDING_COVERAGE;\n             *   pixel.a = planeAlpha;\n             *\n             */\n            uint8_t planeAlpha;\n\n            /* Pad to 32 bits */\n            uint8_t _pad[3];\n\n            /*\n             * Availability: HWC_DEVICE_API_VERSION_1_5\n             *\n             * This defines the region of the source buffer that has been\n             * modified since the last frame.\n             *\n             * If surfaceDamage.numRects > 0, then it may be assumed that any\n             * portion of the source buffer not covered by one of the rects has\n             * not been modified this frame. If surfaceDamage.numRects == 0,\n             * then the whole source buffer must be treated as if it had been\n             * modified.\n             *\n             * If the layer's contents are not modified relative to the prior\n             * prepare/set cycle, surfaceDamage will contain exactly one empty\n             * rect ([0, 0, 0, 0]).\n             *\n             * The damage rects are relative to the pre-transformed buffer, and\n             * their origin is the top-left corner.\n             */\n            hwc_region_t surfaceDamage;\n        };\n    };\n\n#ifdef __LP64__\n    /*\n     * For 64-bit mode, this struct is 120 bytes (and 8-byte aligned), and needs\n     * to be padded as such to maintain binary compatibility.\n     */\n    uint8_t reserved[120 - 112];\n#else\n    /*\n     * For 32-bit mode, this struct is 96 bytes, and needs to be padded as such\n     * to maintain binary compatibility.\n     */\n    uint8_t reserved[96 - 84];\n#endif\n\n} hwc_layer_1_t;\n\n/* This represents a display, typically an EGLDisplay object */\ntypedef void* hwc_display_t;\n\n/* This represents a surface, typically an EGLSurface object  */\ntypedef void* hwc_surface_t;\n\n/*\n * hwc_display_contents_1_t::flags values\n */\nenum {\n    /*\n     * HWC_GEOMETRY_CHANGED is set by SurfaceFlinger to indicate that the list\n     * passed to (*prepare)() has changed by more than just the buffer handles\n     * and acquire fences.\n     */\n    HWC_GEOMETRY_CHANGED = 0x00000001,\n};\n\n/*\n * Description of the contents to output on a display.\n *\n * This is the top-level structure passed to the prepare and set calls to\n * negotiate and commit the composition of a display image.\n */\ntypedef struct hwc_display_contents_1 {\n    /* File descriptor referring to a Sync HAL fence object which will signal\n     * when this composition is retired. For a physical display, a composition\n     * is retired when it has been replaced on-screen by a subsequent set. For\n     * a virtual display, the composition is retired when the writes to\n     * outputBuffer are complete and can be read. The fence object is created\n     * and returned by the set call; this field will be -1 on entry to prepare\n     * and set. SurfaceFlinger will close the returned file descriptor.\n     */\n    int retireFenceFd;\n\n    union {\n        /* Fields only relevant for HWC_DEVICE_VERSION_1_0. */\n        struct {\n            /* (dpy, sur) is the target of SurfaceFlinger's OpenGL ES\n             * composition for HWC_DEVICE_VERSION_1_0. They aren't relevant to\n             * prepare. The set call should commit this surface atomically to\n             * the display along with any overlay layers.\n             */\n            hwc_display_t dpy;\n            hwc_surface_t sur;\n        };\n\n        /* These fields are used for virtual displays when the h/w composer\n         * version is at least HWC_DEVICE_VERSION_1_3. */\n        struct {\n            /* outbuf is the buffer that receives the composed image for\n             * virtual displays. Writes to the outbuf must wait until\n             * outbufAcquireFenceFd signals. A fence that will signal when\n             * writes to outbuf are complete should be returned in\n             * retireFenceFd.\n             *\n             * This field is set before prepare(), so properties of the buffer\n             * can be used to decide which layers can be handled by h/w\n             * composer.\n             *\n             * If prepare() sets all layers to FRAMEBUFFER, then GLES\n             * composition will happen directly to the output buffer. In this\n             * case, both outbuf and the FRAMEBUFFER_TARGET layer's buffer will\n             * be the same, and set() has no work to do besides managing fences.\n             *\n             * If the TARGET_FORCE_HWC_FOR_VIRTUAL_DISPLAYS board config\n             * variable is defined (not the default), then this behavior is\n             * changed: if all layers are marked for FRAMEBUFFER, GLES\n             * composition will take place to a scratch framebuffer, and\n             * h/w composer must copy it to the output buffer. This allows the\n             * h/w composer to do format conversion if there are cases where\n             * that is more desirable than doing it in the GLES driver or at the\n             * virtual display consumer.\n             *\n             * If some or all layers are marked OVERLAY, then the framebuffer\n             * and output buffer will be different. As with physical displays,\n             * the framebuffer handle will not change between frames if all\n             * layers are marked for OVERLAY.\n             */\n            buffer_handle_t outbuf;\n\n            /* File descriptor for a fence that will signal when outbuf is\n             * ready to be written. The h/w composer is responsible for closing\n             * this when no longer needed.\n             *\n             * Will be -1 whenever outbuf is NULL, or when the outbuf can be\n             * written immediately.\n             */\n            int outbufAcquireFenceFd;\n        };\n    };\n\n    /* List of layers that will be composed on the display. The buffer handles\n     * in the list will be unique. If numHwLayers is 0, all composition will be\n     * performed by SurfaceFlinger.\n     */\n    uint32_t flags;\n    size_t numHwLayers;\n    hwc_layer_1_t hwLayers[0];\n\n} hwc_display_contents_1_t;\n\n/* see hwc_composer_device::registerProcs()\n * All of the callbacks are required and non-NULL unless otherwise noted.\n */\ntypedef struct hwc_procs {\n    /*\n     * (*invalidate)() triggers a screen refresh, in particular prepare and set\n     * will be called shortly after this call is made. Note that there is\n     * NO GUARANTEE that the screen refresh will happen after invalidate()\n     * returns (in particular, it could happen before).\n     * invalidate() is GUARANTEED TO NOT CALL BACK into the h/w composer HAL and\n     * it is safe to call invalidate() from any of hwc_composer_device\n     * hooks, unless noted otherwise.\n     */\n    void (*invalidate)(const struct hwc_procs* procs);\n\n    /*\n     * (*vsync)() is called by the h/w composer HAL when a vsync event is\n     * received and HWC_EVENT_VSYNC is enabled on a display\n     * (see: hwc_event_control).\n     *\n     * the \"disp\" parameter indicates which display the vsync event is for.\n     * the \"timestamp\" parameter is the system monotonic clock timestamp in\n     *   nanosecond of when the vsync event happened.\n     *\n     * vsync() is GUARANTEED TO NOT CALL BACK into the h/w composer HAL.\n     *\n     * It is expected that vsync() is called from a thread of at least\n     * HAL_PRIORITY_URGENT_DISPLAY with as little latency as possible,\n     * typically less than 0.5 ms.\n     *\n     * It is a (silent) error to have HWC_EVENT_VSYNC enabled when calling\n     * hwc_composer_device.set(..., 0, 0, 0) (screen off). The implementation\n     * can either stop or continue to process VSYNC events, but must not\n     * crash or cause other problems.\n     */\n    void (*vsync)(const struct hwc_procs* procs, int disp, int64_t timestamp);\n\n    /*\n     * (*hotplug)() is called by the h/w composer HAL when a display is\n     * connected or disconnected. The PRIMARY display is always connected and\n     * the hotplug callback should not be called for it.\n     *\n     * The disp parameter indicates which display type this event is for.\n     * The connected parameter indicates whether the display has just been\n     *   connected (1) or disconnected (0).\n     *\n     * The hotplug() callback may call back into the h/w composer on the same\n     * thread to query refresh rate and dpi for the display. Additionally,\n     * other threads may be calling into the h/w composer while the callback\n     * is in progress.\n     *\n     * The h/w composer must serialize calls to the hotplug callback; only\n     * one thread may call it at a time.\n     *\n     * This callback will be NULL if the h/w composer is using\n     * HWC_DEVICE_API_VERSION_1_0.\n     */\n    void (*hotplug)(const struct hwc_procs* procs, int disp, int connected);\n\n} hwc_procs_t;\n\n\n/*****************************************************************************/\n\ntypedef struct hwc_module {\n    /**\n     * Common methods of the hardware composer module.  This *must* be the first member of\n     * hwc_module as users of this structure will cast a hw_module_t to\n     * hwc_module pointer in contexts where it's known the hw_module_t references a\n     * hwc_module.\n     */\n    struct hw_module_t common;\n} hwc_module_t;\n\ntypedef struct hwc_composer_device_1 {\n    /**\n     * Common methods of the hardware composer device.  This *must* be the first member of\n     * hwc_composer_device_1 as users of this structure will cast a hw_device_t to\n     * hwc_composer_device_1 pointer in contexts where it's known the hw_device_t references a\n     * hwc_composer_device_1.\n     */\n    struct hw_device_t common;\n\n    /*\n     * (*prepare)() is called for each frame before composition and is used by\n     * SurfaceFlinger to determine what composition steps the HWC can handle.\n     *\n     * (*prepare)() can be called more than once, the last call prevails.\n     *\n     * The HWC responds by setting the compositionType field in each layer to\n     * either HWC_FRAMEBUFFER, HWC_OVERLAY, or HWC_CURSOR_OVERLAY. For the\n     * HWC_FRAMEBUFFER type, composition for the layer is handled by\n     * SurfaceFlinger with OpenGL ES. For the latter two overlay types,\n     * the HWC will have to handle the layer's composition. compositionType\n     * and hints are preserved between (*prepare)() calles unless the\n     * HWC_GEOMETRY_CHANGED flag is set.\n     *\n     * (*prepare)() is called with HWC_GEOMETRY_CHANGED to indicate that the\n     * list's geometry has changed, that is, when more than just the buffer's\n     * handles have been updated. Typically this happens (but is not limited to)\n     * when a window is added, removed, resized or moved. In this case\n     * compositionType and hints are reset to their default value.\n     *\n     * For HWC 1.0, numDisplays will always be one, and displays[0] will be\n     * non-NULL.\n     *\n     * For HWC 1.1, numDisplays will always be HWC_NUM_PHYSICAL_DISPLAY_TYPES.\n     * Entries for unsupported or disabled/disconnected display types will be\n     * NULL.\n     *\n     * In HWC 1.3, numDisplays may be up to HWC_NUM_DISPLAY_TYPES. The extra\n     * entries correspond to enabled virtual displays, and will be non-NULL.\n     *\n     * returns: 0 on success. An negative error code on error. If an error is\n     * returned, SurfaceFlinger will assume that none of the layer will be\n     * handled by the HWC.\n     */\n    int (*prepare)(struct hwc_composer_device_1 *dev,\n                    size_t numDisplays, hwc_display_contents_1_t** displays);\n\n    /*\n     * (*set)() is used in place of eglSwapBuffers(), and assumes the same\n     * functionality, except it also commits the work list atomically with\n     * the actual eglSwapBuffers().\n     *\n     * The layer lists are guaranteed to be the same as the ones returned from\n     * the last call to (*prepare)().\n     *\n     * When this call returns the caller assumes that the displays will be\n     * updated in the near future with the content of their work lists, without\n     * artifacts during the transition from the previous frame.\n     *\n     * A display with zero layers indicates that the entire composition has\n     * been handled by SurfaceFlinger with OpenGL ES. In this case, (*set)()\n     * behaves just like eglSwapBuffers().\n     *\n     * For HWC 1.0, numDisplays will always be one, and displays[0] will be\n     * non-NULL.\n     *\n     * For HWC 1.1, numDisplays will always be HWC_NUM_PHYSICAL_DISPLAY_TYPES.\n     * Entries for unsupported or disabled/disconnected display types will be\n     * NULL.\n     *\n     * In HWC 1.3, numDisplays may be up to HWC_NUM_DISPLAY_TYPES. The extra\n     * entries correspond to enabled virtual displays, and will be non-NULL.\n     *\n     * IMPORTANT NOTE: There is an implicit layer containing opaque black\n     * pixels behind all the layers in the list. It is the responsibility of\n     * the hwcomposer module to make sure black pixels are output (or blended\n     * from).\n     *\n     * IMPORTANT NOTE: In the event of an error this call *MUST* still cause\n     * any fences returned in the previous call to set to eventually become\n     * signaled.  The caller may have already issued wait commands on these\n     * fences, and having set return without causing those fences to signal\n     * will likely result in a deadlock.\n     *\n     * returns: 0 on success. A negative error code on error:\n     *    HWC_EGL_ERROR: eglGetError() will provide the proper error code (only\n     *        allowed prior to HWComposer 1.1)\n     *    Another code for non EGL errors.\n     */\n    int (*set)(struct hwc_composer_device_1 *dev,\n                size_t numDisplays, hwc_display_contents_1_t** displays);\n\n    /*\n     * eventControl(..., event, enabled)\n     * Enables or disables h/w composer events for a display.\n     *\n     * eventControl can be called from any thread and takes effect\n     * immediately.\n     *\n     *  Supported events are:\n     *      HWC_EVENT_VSYNC\n     *\n     * returns -EINVAL if the \"event\" parameter is not one of the value above\n     * or if the \"enabled\" parameter is not 0 or 1.\n     */\n    int (*eventControl)(struct hwc_composer_device_1* dev, int disp,\n            int event, int enabled);\n\n    union {\n        /*\n         * For HWC 1.3 and earlier, the blank() interface is used.\n         *\n         * blank(..., blank)\n         * Blanks or unblanks a display's screen.\n         *\n         * Turns the screen off when blank is nonzero, on when blank is zero.\n         * Multiple sequential calls with the same blank value must be\n         * supported.\n         * The screen state transition must be be complete when the function\n         * returns.\n         *\n         * returns 0 on success, negative on error.\n         */\n        int (*blank)(struct hwc_composer_device_1* dev, int disp, int blank);\n\n        /*\n         * For HWC 1.4 and above, setPowerMode() will be used in place of\n         * blank().\n         *\n         * setPowerMode(..., mode)\n         * Sets the display screen's power state.\n         *\n         * Refer to the documentation of the HWC_POWER_MODE_* constants\n         * for information about each power mode.\n         *\n         * The functionality is similar to the blank() command in previous\n         * versions of HWC, but with support for more power states.\n         *\n         * The display driver is expected to retain and restore the low power\n         * state of the display while entering and exiting from suspend.\n         *\n         * Multiple sequential calls with the same mode value must be supported.\n         *\n         * The screen state transition must be be complete when the function\n         * returns.\n         *\n         * returns 0 on success, negative on error.\n         */\n        int (*setPowerMode)(struct hwc_composer_device_1* dev, int disp,\n                int mode);\n    };\n\n    /*\n     * Used to retrieve information about the h/w composer\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*query)(struct hwc_composer_device_1* dev, int what, int* value);\n\n    /*\n     * (*registerProcs)() registers callbacks that the h/w composer HAL can\n     * later use. It will be called immediately after the composer device is\n     * opened with non-NULL procs. It is FORBIDDEN to call any of the callbacks\n     * from within registerProcs(). registerProcs() must save the hwc_procs_t\n     * pointer which is needed when calling a registered callback.\n     */\n    void (*registerProcs)(struct hwc_composer_device_1* dev,\n            hwc_procs_t const* procs);\n\n    /*\n     * This field is OPTIONAL and can be NULL.\n     *\n     * If non NULL it will be called by SurfaceFlinger on dumpsys\n     */\n    void (*dump)(struct hwc_composer_device_1* dev, char *buff, int buff_len);\n\n    /*\n     * (*getDisplayConfigs)() returns handles for the configurations available\n     * on the connected display. These handles must remain valid as long as the\n     * display is connected.\n     *\n     * Configuration handles are written to configs. The number of entries\n     * allocated by the caller is passed in *numConfigs; getDisplayConfigs must\n     * not try to write more than this number of config handles. On return, the\n     * total number of configurations available for the display is returned in\n     * *numConfigs. If *numConfigs is zero on entry, then configs may be NULL.\n     *\n     * Hardware composers implementing HWC_DEVICE_API_VERSION_1_3 or prior\n     * shall choose one configuration to activate and report it as the first\n     * entry in the returned list. Reporting the inactive configurations is not\n     * required.\n     *\n     * HWC_DEVICE_API_VERSION_1_4 and later provide configuration management\n     * through SurfaceFlinger, and hardware composers implementing these APIs\n     * must also provide getActiveConfig and setActiveConfig. Hardware composers\n     * implementing these API versions may choose not to activate any\n     * configuration, leaving configuration selection to higher levels of the\n     * framework.\n     *\n     * Returns 0 on success or a negative error code on error. If disp is a\n     * hotpluggable display type and no display is connected, an error shall be\n     * returned.\n     *\n     * This field is REQUIRED for HWC_DEVICE_API_VERSION_1_1 and later.\n     * It shall be NULL for previous versions.\n     */\n    int (*getDisplayConfigs)(struct hwc_composer_device_1* dev, int disp,\n            uint32_t* configs, size_t* numConfigs);\n\n    /*\n     * (*getDisplayAttributes)() returns attributes for a specific config of a\n     * connected display. The config parameter is one of the config handles\n     * returned by getDisplayConfigs.\n     *\n     * The list of attributes to return is provided in the attributes\n     * parameter, terminated by HWC_DISPLAY_NO_ATTRIBUTE. The value for each\n     * requested attribute is written in order to the values array. The\n     * HWC_DISPLAY_NO_ATTRIBUTE attribute does not have a value, so the values\n     * array will have one less value than the attributes array.\n     *\n     * This field is REQUIRED for HWC_DEVICE_API_VERSION_1_1 and later.\n     * It shall be NULL for previous versions.\n     *\n     * If disp is a hotpluggable display type and no display is connected,\n     * or if config is not a valid configuration for the display, a negative\n     * error code shall be returned.\n     */\n    int (*getDisplayAttributes)(struct hwc_composer_device_1* dev, int disp,\n            uint32_t config, const uint32_t* attributes, int32_t* values);\n\n    /*\n     * (*getActiveConfig)() returns the index of the configuration that is\n     * currently active on the connected display. The index is relative to\n     * the list of configuration handles returned by getDisplayConfigs. If there\n     * is no active configuration, -1 shall be returned.\n     *\n     * Returns the configuration index on success or -1 on error.\n     *\n     * This field is REQUIRED for HWC_DEVICE_API_VERSION_1_4 and later.\n     * It shall be NULL for previous versions.\n     */\n    int (*getActiveConfig)(struct hwc_composer_device_1* dev, int disp);\n\n    /*\n     * (*setActiveConfig)() instructs the hardware composer to switch to the\n     * display configuration at the given index in the list of configuration\n     * handles returned by getDisplayConfigs.\n     *\n     * If this function returns without error, any subsequent calls to\n     * getActiveConfig shall return the index set by this function until one\n     * of the following occurs:\n     *   1) Another successful call of this function\n     *   2) The display is disconnected\n     *\n     * Returns 0 on success or a negative error code on error. If disp is a\n     * hotpluggable display type and no display is connected, or if index is\n     * outside of the range of hardware configurations returned by\n     * getDisplayConfigs, an error shall be returned.\n     *\n     * This field is REQUIRED for HWC_DEVICE_API_VERSION_1_4 and later.\n     * It shall be NULL for previous versions.\n     */\n    int (*setActiveConfig)(struct hwc_composer_device_1* dev, int disp,\n            int index);\n    /*\n     * Asynchronously update the location of the cursor layer.\n     *\n     * Within the standard prepare()/set() composition loop, the client\n     * (surfaceflinger) can request that a given layer uses dedicated cursor\n     * composition hardware by specifiying the HWC_IS_CURSOR_LAYER flag. Only\n     * one layer per display can have this flag set. If the layer is suitable\n     * for the platform's cursor hardware, hwcomposer will return from prepare()\n     * a composition type of HWC_CURSOR_OVERLAY for that layer. This indicates\n     * not only that the client is not responsible for compositing that layer,\n     * but also that the client can continue to update the position of that layer\n     * after a call to set(). This can reduce the visible latency of mouse\n     * movement to visible, on-screen cursor updates. Calls to\n     * setCursorPositionAsync() may be made from a different thread doing the\n     * prepare()/set() composition loop, but care must be taken to not interleave\n     * calls of setCursorPositionAsync() between calls of set()/prepare().\n     *\n     * Notes:\n     * - Only one layer per display can be specified as a cursor layer with\n     *   HWC_IS_CURSOR_LAYER.\n     * - hwcomposer will only return one layer per display as HWC_CURSOR_OVERLAY\n     * - This returns 0 on success or -errno on error.\n     * - This field is optional for HWC_DEVICE_API_VERSION_1_4 and later. It\n     *   should be null for previous versions.\n     */\n    int (*setCursorPositionAsync)(struct hwc_composer_device_1 *dev, int disp, int x_pos, int y_pos);\n\n    /*\n     * Reserved for future use. Must be NULL.\n     */\n    void* reserved_proc[1];\n\n} hwc_composer_device_1_t;\n\n/** convenience API for opening and closing a device */\n\nstatic inline int hwc_open_1(const struct hw_module_t* module,\n        hwc_composer_device_1_t** device) {\n    return module->methods->open(module,\n            HWC_HARDWARE_COMPOSER, (struct hw_device_t**)device);\n}\n\nstatic inline int hwc_close_1(hwc_composer_device_1_t* device) {\n    return device->common.close(&device->common);\n}\n\n/*****************************************************************************/\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_HARDWARE_HWCOMPOSER_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/hwcomposer_defs.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_HWCOMPOSER_DEFS_H\n#define ANDROID_INCLUDE_HARDWARE_HWCOMPOSER_DEFS_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n\n#include <hardware/gralloc.h>\n#include <hardware/hardware.h>\n#include <cutils/native_handle.h>\n\n__BEGIN_DECLS\n\n/*****************************************************************************/\n\n#define HWC_HEADER_VERSION          1\n\n#define HWC_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n\n#define HWC_DEVICE_API_VERSION_1_0  HARDWARE_DEVICE_API_VERSION_2(1, 0, HWC_HEADER_VERSION)\n#define HWC_DEVICE_API_VERSION_1_1  HARDWARE_DEVICE_API_VERSION_2(1, 1, HWC_HEADER_VERSION)\n#define HWC_DEVICE_API_VERSION_1_2  HARDWARE_DEVICE_API_VERSION_2(1, 2, HWC_HEADER_VERSION)\n#define HWC_DEVICE_API_VERSION_1_3  HARDWARE_DEVICE_API_VERSION_2(1, 3, HWC_HEADER_VERSION)\n#define HWC_DEVICE_API_VERSION_1_4  HARDWARE_DEVICE_API_VERSION_2(1, 4, HWC_HEADER_VERSION)\n#define HWC_DEVICE_API_VERSION_1_5  HARDWARE_DEVICE_API_VERSION_2(1, 5, HWC_HEADER_VERSION)\n\nenum {\n    /* hwc_composer_device_t::set failed in EGL */\n    HWC_EGL_ERROR = -1\n};\n\n/*\n * hwc_layer_t::hints values\n * Hints are set by the HAL and read by SurfaceFlinger\n */\nenum {\n    /*\n     * HWC can set the HWC_HINT_TRIPLE_BUFFER hint to indicate to SurfaceFlinger\n     * that it should triple buffer this layer. Typically HWC does this when\n     * the layer will be unavailable for use for an extended period of time,\n     * e.g. if the display will be fetching data directly from the layer and\n     * the layer can not be modified until after the next set().\n     */\n    HWC_HINT_TRIPLE_BUFFER  = 0x00000001,\n\n    /*\n     * HWC sets HWC_HINT_CLEAR_FB to tell SurfaceFlinger that it should clear the\n     * framebuffer with transparent pixels where this layer would be.\n     * SurfaceFlinger will only honor this flag when the layer has no blending\n     *\n     */\n    HWC_HINT_CLEAR_FB       = 0x00000002\n};\n\n/*\n * hwc_layer_t::flags values\n * Flags are set by SurfaceFlinger and read by the HAL\n */\nenum {\n    /*\n     * HWC_SKIP_LAYER is set by SurfaceFlnger to indicate that the HAL\n     * shall not consider this layer for composition as it will be handled\n     * by SurfaceFlinger (just as if compositionType was set to HWC_OVERLAY).\n     */\n    HWC_SKIP_LAYER = 0x00000001,\n\n    /*\n     * HWC_IS_CURSOR_LAYER is set by surfaceflinger to indicate that this\n     * layer is being used as a cursor on this particular display, and that\n     * surfaceflinger can potentially perform asynchronous position updates for\n     * this layer. If a call to prepare() returns HWC_CURSOR_OVERLAY for the\n     * composition type of this layer, then the hwcomposer will allow async\n     * position updates to this layer via setCursorPositionAsync().\n     */\n    HWC_IS_CURSOR_LAYER = 0x00000002\n};\n\n/*\n * hwc_layer_t::compositionType values\n */\nenum {\n    /* this layer is to be drawn into the framebuffer by SurfaceFlinger */\n    HWC_FRAMEBUFFER = 0,\n\n    /* this layer will be handled in the HWC */\n    HWC_OVERLAY = 1,\n\n    /* this is the background layer. it's used to set the background color.\n     * there is only a single background layer */\n    HWC_BACKGROUND = 2,\n\n    /* this layer holds the result of compositing the HWC_FRAMEBUFFER layers.\n     * Added in HWC_DEVICE_API_VERSION_1_1. */\n    HWC_FRAMEBUFFER_TARGET = 3,\n\n    /* this layer's contents are taken from a sideband buffer stream.\n     * Added in HWC_DEVICE_API_VERSION_1_4. */\n    HWC_SIDEBAND = 4,\n\n    /* this layer's composition will be handled by hwcomposer by dedicated\n       cursor overlay hardware. hwcomposer will also all async position updates\n       of this layer outside of the normal prepare()/set() loop. Added in\n       HWC_DEVICE_API_VERSION_1_4. */\n    HWC_CURSOR_OVERLAY =  5\n };\n/*\n * hwc_layer_t::blending values\n */\nenum {\n    /* no blending */\n    HWC_BLENDING_NONE     = 0x0100,\n\n    /* ONE / ONE_MINUS_SRC_ALPHA */\n    HWC_BLENDING_PREMULT  = 0x0105,\n\n    /* SRC_ALPHA / ONE_MINUS_SRC_ALPHA */\n    HWC_BLENDING_COVERAGE = 0x0405\n};\n\n/*\n * hwc_layer_t::transform values\n */\nenum {\n    /* flip source image horizontally */\n    HWC_TRANSFORM_FLIP_H = HAL_TRANSFORM_FLIP_H,\n    /* flip source image vertically */\n    HWC_TRANSFORM_FLIP_V = HAL_TRANSFORM_FLIP_V,\n    /* rotate source image 90 degrees clock-wise */\n    HWC_TRANSFORM_ROT_90 = HAL_TRANSFORM_ROT_90,\n    /* rotate source image 180 degrees */\n    HWC_TRANSFORM_ROT_180 = HAL_TRANSFORM_ROT_180,\n    /* rotate source image 270 degrees clock-wise */\n    HWC_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_270,\n};\n\n/* attributes queriable with query() */\nenum {\n    /*\n     * Must return 1 if the background layer is supported, 0 otherwise.\n     */\n    HWC_BACKGROUND_LAYER_SUPPORTED      = 0,\n\n    /*\n     * Returns the vsync period in nanoseconds.\n     *\n     * This query is not used for HWC_DEVICE_API_VERSION_1_1 and later.\n     * Instead, the per-display attribute HWC_DISPLAY_VSYNC_PERIOD is used.\n     */\n    HWC_VSYNC_PERIOD                    = 1,\n\n    /*\n     * Availability: HWC_DEVICE_API_VERSION_1_1\n     * Returns a mask of supported display types.\n     */\n    HWC_DISPLAY_TYPES_SUPPORTED         = 2,\n};\n\n/* display attributes returned by getDisplayAttributes() */\nenum {\n    /* Indicates the end of an attribute list */\n    HWC_DISPLAY_NO_ATTRIBUTE                = 0,\n\n    /* The vsync period in nanoseconds */\n    HWC_DISPLAY_VSYNC_PERIOD                = 1,\n\n    /* The number of pixels in the horizontal and vertical directions. */\n    HWC_DISPLAY_WIDTH                       = 2,\n    HWC_DISPLAY_HEIGHT                      = 3,\n\n    /* The number of pixels per thousand inches of this configuration.\n     *\n     * Scaling DPI by 1000 allows it to be stored in an int without losing\n     * too much precision.\n     *\n     * If the DPI for a configuration is unavailable or the HWC implementation\n     * considers it unreliable, it should set these attributes to zero.\n     */\n    HWC_DISPLAY_DPI_X                       = 4,\n    HWC_DISPLAY_DPI_Y                       = 5,\n\n    /* Indicates which of the vendor-defined color transforms is provided by\n     * this configuration. */\n    HWC_DISPLAY_COLOR_TRANSFORM             = 6,\n};\n\n/* Allowed events for hwc_methods::eventControl() */\nenum {\n    HWC_EVENT_VSYNC     = 0\n};\n\n/* Display types and associated mask bits. */\nenum {\n    HWC_DISPLAY_PRIMARY     = 0,\n    HWC_DISPLAY_EXTERNAL    = 1,    // HDMI, DP, etc.\n#ifdef QTI_BSP\n    HWC_DISPLAY_TERTIARY    = 2,\n    HWC_DISPLAY_VIRTUAL     = 3,\n\n    HWC_NUM_PHYSICAL_DISPLAY_TYPES = 3,\n    HWC_NUM_DISPLAY_TYPES          = 4,\n#else\n    HWC_DISPLAY_VIRTUAL     = 2,\n\n    HWC_NUM_PHYSICAL_DISPLAY_TYPES = 2,\n    HWC_NUM_DISPLAY_TYPES          = 3,\n#endif\n};\n\nenum {\n    HWC_DISPLAY_PRIMARY_BIT     = 1 << HWC_DISPLAY_PRIMARY,\n    HWC_DISPLAY_EXTERNAL_BIT    = 1 << HWC_DISPLAY_EXTERNAL,\n#ifdef QTI_BSP\n    HWC_DISPLAY_TERTIARY_BIT    = 1 << HWC_DISPLAY_TERTIARY,\n#endif\n    HWC_DISPLAY_VIRTUAL_BIT     = 1 << HWC_DISPLAY_VIRTUAL,\n};\n\n/* Display power modes */\nenum {\n    /* The display is turned off (blanked). */\n    HWC_POWER_MODE_OFF      = 0,\n    /* The display is turned on and configured in a low power state\n     * that is suitable for presenting ambient information to the user,\n     * possibly with lower fidelity than normal but greater efficiency. */\n    HWC_POWER_MODE_DOZE     = 1,\n    /* The display is turned on normally. */\n    HWC_POWER_MODE_NORMAL   = 2,\n    /* The display is configured as in HWC_POWER_MODE_DOZE but may\n     * stop applying frame buffer updates from the graphics subsystem.\n     * This power mode is effectively a hint from the doze dream to\n     * tell the hardware that it is done drawing to the display for the\n     * time being and that the display should remain on in a low power\n     * state and continue showing its current contents indefinitely\n     * until the mode changes.\n     *\n     * This mode may also be used as a signal to enable hardware-based doze\n     * functionality.  In this case, the doze dream is effectively\n     * indicating that the hardware is free to take over the display\n     * and manage it autonomously to implement low power always-on display\n     * functionality. */\n    HWC_POWER_MODE_DOZE_SUSPEND  = 3,\n};\n\n/*****************************************************************************/\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_HARDWARE_HWCOMPOSER_DEFS_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/input.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_INPUT_H\n#define ANDROID_INCLUDE_HARDWARE_INPUT_H\n\n#include <hardware/hardware.h>\n#include <stdint.h>\n\n__BEGIN_DECLS\n\n#define INPUT_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define INPUT_HARDWARE_MODULE_ID \"input\"\n\n#define INPUT_INSTANCE_EVDEV \"evdev\"\n\ntypedef enum input_bus {\n    INPUT_BUS_BT,\n    INPUT_BUS_USB,\n    INPUT_BUS_SERIAL,\n    INPUT_BUS_BUILTIN\n} input_bus_t;\n\ntypedef struct input_host input_host_t;\n\ntypedef struct input_device_handle input_device_handle_t;\n\ntypedef struct input_device_identifier input_device_identifier_t;\n\ntypedef struct input_device_definition input_device_definition_t;\n\ntypedef struct input_report_definition input_report_definition_t;\n\ntypedef struct input_report input_report_t;\n\ntypedef struct input_collection input_collection_t;\n\ntypedef struct input_property_map input_property_map_t;\n\ntypedef struct input_property input_property_t;\n\ntypedef enum {\n    // keycodes\n    INPUT_USAGE_KEYCODE_UNKNOWN,\n    INPUT_USAGE_KEYCODE_SOFT_LEFT,\n    INPUT_USAGE_KEYCODE_SOFT_RIGHT,\n    INPUT_USAGE_KEYCODE_HOME,\n    INPUT_USAGE_KEYCODE_BACK,\n    INPUT_USAGE_KEYCODE_CALL,\n    INPUT_USAGE_KEYCODE_ENDCALL,\n    INPUT_USAGE_KEYCODE_0,\n    INPUT_USAGE_KEYCODE_1,\n    INPUT_USAGE_KEYCODE_2,\n    INPUT_USAGE_KEYCODE_3,\n    INPUT_USAGE_KEYCODE_4,\n    INPUT_USAGE_KEYCODE_5,\n    INPUT_USAGE_KEYCODE_6,\n    INPUT_USAGE_KEYCODE_7,\n    INPUT_USAGE_KEYCODE_8,\n    INPUT_USAGE_KEYCODE_9,\n    INPUT_USAGE_KEYCODE_STAR,\n    INPUT_USAGE_KEYCODE_POUND,\n    INPUT_USAGE_KEYCODE_DPAD_UP,\n    INPUT_USAGE_KEYCODE_DPAD_DOWN,\n    INPUT_USAGE_KEYCODE_DPAD_LEFT,\n    INPUT_USAGE_KEYCODE_DPAD_RIGHT,\n    INPUT_USAGE_KEYCODE_DPAD_CENTER,\n    INPUT_USAGE_KEYCODE_VOLUME_UP,\n    INPUT_USAGE_KEYCODE_VOLUME_DOWN,\n    INPUT_USAGE_KEYCODE_POWER,\n    INPUT_USAGE_KEYCODE_CAMERA,\n    INPUT_USAGE_KEYCODE_CLEAR,\n    INPUT_USAGE_KEYCODE_A,\n    INPUT_USAGE_KEYCODE_B,\n    INPUT_USAGE_KEYCODE_C,\n    INPUT_USAGE_KEYCODE_D,\n    INPUT_USAGE_KEYCODE_E,\n    INPUT_USAGE_KEYCODE_F,\n    INPUT_USAGE_KEYCODE_G,\n    INPUT_USAGE_KEYCODE_H,\n    INPUT_USAGE_KEYCODE_I,\n    INPUT_USAGE_KEYCODE_J,\n    INPUT_USAGE_KEYCODE_K,\n    INPUT_USAGE_KEYCODE_L,\n    INPUT_USAGE_KEYCODE_M,\n    INPUT_USAGE_KEYCODE_N,\n    INPUT_USAGE_KEYCODE_O,\n    INPUT_USAGE_KEYCODE_P,\n    INPUT_USAGE_KEYCODE_Q,\n    INPUT_USAGE_KEYCODE_R,\n    INPUT_USAGE_KEYCODE_S,\n    INPUT_USAGE_KEYCODE_T,\n    INPUT_USAGE_KEYCODE_U,\n    INPUT_USAGE_KEYCODE_V,\n    INPUT_USAGE_KEYCODE_W,\n    INPUT_USAGE_KEYCODE_X,\n    INPUT_USAGE_KEYCODE_Y,\n    INPUT_USAGE_KEYCODE_Z,\n    INPUT_USAGE_KEYCODE_COMMA,\n    INPUT_USAGE_KEYCODE_PERIOD,\n    INPUT_USAGE_KEYCODE_ALT_LEFT,\n    INPUT_USAGE_KEYCODE_ALT_RIGHT,\n    INPUT_USAGE_KEYCODE_SHIFT_LEFT,\n    INPUT_USAGE_KEYCODE_SHIFT_RIGHT,\n    INPUT_USAGE_KEYCODE_TAB,\n    INPUT_USAGE_KEYCODE_SPACE,\n    INPUT_USAGE_KEYCODE_SYM,\n    INPUT_USAGE_KEYCODE_EXPLORER,\n    INPUT_USAGE_KEYCODE_ENVELOPE,\n    INPUT_USAGE_KEYCODE_ENTER,\n    INPUT_USAGE_KEYCODE_DEL,\n    INPUT_USAGE_KEYCODE_GRAVE,\n    INPUT_USAGE_KEYCODE_MINUS,\n    INPUT_USAGE_KEYCODE_EQUALS,\n    INPUT_USAGE_KEYCODE_LEFT_BRACKET,\n    INPUT_USAGE_KEYCODE_RIGHT_BRACKET,\n    INPUT_USAGE_KEYCODE_BACKSLASH,\n    INPUT_USAGE_KEYCODE_SEMICOLON,\n    INPUT_USAGE_KEYCODE_APOSTROPHE,\n    INPUT_USAGE_KEYCODE_SLASH,\n    INPUT_USAGE_KEYCODE_AT,\n    INPUT_USAGE_KEYCODE_NUM,\n    INPUT_USAGE_KEYCODE_HEADSETHOOK,\n    INPUT_USAGE_KEYCODE_FOCUS,   // *Camera* focus\n    INPUT_USAGE_KEYCODE_PLUS,\n    INPUT_USAGE_KEYCODE_MENU,\n    INPUT_USAGE_KEYCODE_NOTIFICATION,\n    INPUT_USAGE_KEYCODE_SEARCH,\n    INPUT_USAGE_KEYCODE_MEDIA_PLAY_PAUSE,\n    INPUT_USAGE_KEYCODE_MEDIA_STOP,\n    INPUT_USAGE_KEYCODE_MEDIA_NEXT,\n    INPUT_USAGE_KEYCODE_MEDIA_PREVIOUS,\n    INPUT_USAGE_KEYCODE_MEDIA_REWIND,\n    INPUT_USAGE_KEYCODE_MEDIA_FAST_FORWARD,\n    INPUT_USAGE_KEYCODE_MUTE,\n    INPUT_USAGE_KEYCODE_PAGE_UP,\n    INPUT_USAGE_KEYCODE_PAGE_DOWN,\n    INPUT_USAGE_KEYCODE_PICTSYMBOLS,\n    INPUT_USAGE_KEYCODE_SWITCH_CHARSET,\n    INPUT_USAGE_KEYCODE_BUTTON_A,\n    INPUT_USAGE_KEYCODE_BUTTON_B,\n    INPUT_USAGE_KEYCODE_BUTTON_C,\n    INPUT_USAGE_KEYCODE_BUTTON_X,\n    INPUT_USAGE_KEYCODE_BUTTON_Y,\n    INPUT_USAGE_KEYCODE_BUTTON_Z,\n    INPUT_USAGE_KEYCODE_BUTTON_L1,\n    INPUT_USAGE_KEYCODE_BUTTON_R1,\n    INPUT_USAGE_KEYCODE_BUTTON_L2,\n    INPUT_USAGE_KEYCODE_BUTTON_R2,\n    INPUT_USAGE_KEYCODE_BUTTON_THUMBL,\n    INPUT_USAGE_KEYCODE_BUTTON_THUMBR,\n    INPUT_USAGE_KEYCODE_BUTTON_START,\n    INPUT_USAGE_KEYCODE_BUTTON_SELECT,\n    INPUT_USAGE_KEYCODE_BUTTON_MODE,\n    INPUT_USAGE_KEYCODE_ESCAPE,\n    INPUT_USAGE_KEYCODE_FORWARD_DEL,\n    INPUT_USAGE_KEYCODE_CTRL_LEFT,\n    INPUT_USAGE_KEYCODE_CTRL_RIGHT,\n    INPUT_USAGE_KEYCODE_CAPS_LOCK,\n    INPUT_USAGE_KEYCODE_SCROLL_LOCK,\n    INPUT_USAGE_KEYCODE_META_LEFT,\n    INPUT_USAGE_KEYCODE_META_RIGHT,\n    INPUT_USAGE_KEYCODE_FUNCTION,\n    INPUT_USAGE_KEYCODE_SYSRQ,\n    INPUT_USAGE_KEYCODE_BREAK,\n    INPUT_USAGE_KEYCODE_MOVE_HOME,\n    INPUT_USAGE_KEYCODE_MOVE_END,\n    INPUT_USAGE_KEYCODE_INSERT,\n    INPUT_USAGE_KEYCODE_FORWARD,\n    INPUT_USAGE_KEYCODE_MEDIA_PLAY,\n    INPUT_USAGE_KEYCODE_MEDIA_PAUSE,\n    INPUT_USAGE_KEYCODE_MEDIA_CLOSE,\n    INPUT_USAGE_KEYCODE_MEDIA_EJECT,\n    INPUT_USAGE_KEYCODE_MEDIA_RECORD,\n    INPUT_USAGE_KEYCODE_F1,\n    INPUT_USAGE_KEYCODE_F2,\n    INPUT_USAGE_KEYCODE_F3,\n    INPUT_USAGE_KEYCODE_F4,\n    INPUT_USAGE_KEYCODE_F5,\n    INPUT_USAGE_KEYCODE_F6,\n    INPUT_USAGE_KEYCODE_F7,\n    INPUT_USAGE_KEYCODE_F8,\n    INPUT_USAGE_KEYCODE_F9,\n    INPUT_USAGE_KEYCODE_F10,\n    INPUT_USAGE_KEYCODE_F11,\n    INPUT_USAGE_KEYCODE_F12,\n    INPUT_USAGE_KEYCODE_NUM_LOCK,\n    INPUT_USAGE_KEYCODE_NUMPAD_0,\n    INPUT_USAGE_KEYCODE_NUMPAD_1,\n    INPUT_USAGE_KEYCODE_NUMPAD_2,\n    INPUT_USAGE_KEYCODE_NUMPAD_3,\n    INPUT_USAGE_KEYCODE_NUMPAD_4,\n    INPUT_USAGE_KEYCODE_NUMPAD_5,\n    INPUT_USAGE_KEYCODE_NUMPAD_6,\n    INPUT_USAGE_KEYCODE_NUMPAD_7,\n    INPUT_USAGE_KEYCODE_NUMPAD_8,\n    INPUT_USAGE_KEYCODE_NUMPAD_9,\n    INPUT_USAGE_KEYCODE_NUMPAD_DIVIDE,\n    INPUT_USAGE_KEYCODE_NUMPAD_MULTIPLY,\n    INPUT_USAGE_KEYCODE_NUMPAD_SUBTRACT,\n    INPUT_USAGE_KEYCODE_NUMPAD_ADD,\n    INPUT_USAGE_KEYCODE_NUMPAD_DOT,\n    INPUT_USAGE_KEYCODE_NUMPAD_COMMA,\n    INPUT_USAGE_KEYCODE_NUMPAD_ENTER,\n    INPUT_USAGE_KEYCODE_NUMPAD_EQUALS,\n    INPUT_USAGE_KEYCODE_NUMPAD_LEFT_PAREN,\n    INPUT_USAGE_KEYCODE_NUMPAD_RIGHT_PAREN,\n    INPUT_USAGE_KEYCODE_VOLUME_MUTE,\n    INPUT_USAGE_KEYCODE_INFO,\n    INPUT_USAGE_KEYCODE_CHANNEL_UP,\n    INPUT_USAGE_KEYCODE_CHANNEL_DOWN,\n    INPUT_USAGE_KEYCODE_ZOOM_IN,\n    INPUT_USAGE_KEYCODE_ZOOM_OUT,\n    INPUT_USAGE_KEYCODE_TV,\n    INPUT_USAGE_KEYCODE_WINDOW,\n    INPUT_USAGE_KEYCODE_GUIDE,\n    INPUT_USAGE_KEYCODE_DVR,\n    INPUT_USAGE_KEYCODE_BOOKMARK,\n    INPUT_USAGE_KEYCODE_CAPTIONS,\n    INPUT_USAGE_KEYCODE_SETTINGS,\n    INPUT_USAGE_KEYCODE_TV_POWER,\n    INPUT_USAGE_KEYCODE_TV_INPUT,\n    INPUT_USAGE_KEYCODE_STB_POWER,\n    INPUT_USAGE_KEYCODE_STB_INPUT,\n    INPUT_USAGE_KEYCODE_AVR_POWER,\n    INPUT_USAGE_KEYCODE_AVR_INPUT,\n    INPUT_USAGE_KEYCODE_PROG_RED,\n    INPUT_USAGE_KEYCODE_PROG_GREEN,\n    INPUT_USAGE_KEYCODE_PROG_YELLOW,\n    INPUT_USAGE_KEYCODE_PROG_BLUE,\n    INPUT_USAGE_KEYCODE_APP_SWITCH,\n    INPUT_USAGE_KEYCODE_BUTTON_1,\n    INPUT_USAGE_KEYCODE_BUTTON_2,\n    INPUT_USAGE_KEYCODE_BUTTON_3,\n    INPUT_USAGE_KEYCODE_BUTTON_4,\n    INPUT_USAGE_KEYCODE_BUTTON_5,\n    INPUT_USAGE_KEYCODE_BUTTON_6,\n    INPUT_USAGE_KEYCODE_BUTTON_7,\n    INPUT_USAGE_KEYCODE_BUTTON_8,\n    INPUT_USAGE_KEYCODE_BUTTON_9,\n    INPUT_USAGE_KEYCODE_BUTTON_10,\n    INPUT_USAGE_KEYCODE_BUTTON_11,\n    INPUT_USAGE_KEYCODE_BUTTON_12,\n    INPUT_USAGE_KEYCODE_BUTTON_13,\n    INPUT_USAGE_KEYCODE_BUTTON_14,\n    INPUT_USAGE_KEYCODE_BUTTON_15,\n    INPUT_USAGE_KEYCODE_BUTTON_16,\n    INPUT_USAGE_KEYCODE_LANGUAGE_SWITCH,\n    INPUT_USAGE_KEYCODE_MANNER_MODE,\n    INPUT_USAGE_KEYCODE_3D_MODE,\n    INPUT_USAGE_KEYCODE_CONTACTS,\n    INPUT_USAGE_KEYCODE_CALENDAR,\n    INPUT_USAGE_KEYCODE_MUSIC,\n    INPUT_USAGE_KEYCODE_CALCULATOR,\n    INPUT_USAGE_KEYCODE_ZENKAKU_HANKAKU,\n    INPUT_USAGE_KEYCODE_EISU,\n    INPUT_USAGE_KEYCODE_MUHENKAN,\n    INPUT_USAGE_KEYCODE_HENKAN,\n    INPUT_USAGE_KEYCODE_KATAKANA_HIRAGANA,\n    INPUT_USAGE_KEYCODE_YEN,\n    INPUT_USAGE_KEYCODE_RO,\n    INPUT_USAGE_KEYCODE_KANA,\n    INPUT_USAGE_KEYCODE_ASSIST,\n    INPUT_USAGE_KEYCODE_BRIGHTNESS_DOWN,\n    INPUT_USAGE_KEYCODE_BRIGHTNESS_UP,\n    INPUT_USAGE_KEYCODE_MEDIA_AUDIO_TRACK,\n    INPUT_USAGE_KEYCODE_SLEEP,\n    INPUT_USAGE_KEYCODE_WAKEUP,\n    INPUT_USAGE_KEYCODE_PAIRING,\n    INPUT_USAGE_KEYCODE_MEDIA_TOP_MENU,\n    INPUT_USAGE_KEYCODE_11,\n    INPUT_USAGE_KEYCODE_12,\n    INPUT_USAGE_KEYCODE_LAST_CHANNEL,\n    INPUT_USAGE_KEYCODE_TV_DATA_SERVICE,\n    INPUT_USAGE_KEYCODE_VOICE_ASSIST,\n    INPUT_USAGE_KEYCODE_TV_RADIO_SERVICE,\n    INPUT_USAGE_KEYCODE_TV_TELETEXT,\n    INPUT_USAGE_KEYCODE_TV_NUMBER_ENTRY,\n    INPUT_USAGE_KEYCODE_TV_TERRESTRIAL_ANALOG,\n    INPUT_USAGE_KEYCODE_TV_TERRESTRIAL_DIGITAL,\n    INPUT_USAGE_KEYCODE_TV_SATELLITE,\n    INPUT_USAGE_KEYCODE_TV_SATELLITE_BS,\n    INPUT_USAGE_KEYCODE_TV_SATELLITE_CS,\n    INPUT_USAGE_KEYCODE_TV_SATELLITE_SERVICE,\n    INPUT_USAGE_KEYCODE_TV_NETWORK,\n    INPUT_USAGE_KEYCODE_TV_ANTENNA_CABLE,\n    INPUT_USAGE_KEYCODE_TV_INPUT_HDMI_1,\n    INPUT_USAGE_KEYCODE_TV_INPUT_HDMI_2,\n    INPUT_USAGE_KEYCODE_TV_INPUT_HDMI_3,\n    INPUT_USAGE_KEYCODE_TV_INPUT_HDMI_4,\n    INPUT_USAGE_KEYCODE_TV_INPUT_COMPOSITE_1,\n    INPUT_USAGE_KEYCODE_TV_INPUT_COMPOSITE_2,\n    INPUT_USAGE_KEYCODE_TV_INPUT_COMPONENT_1,\n    INPUT_USAGE_KEYCODE_TV_INPUT_COMPONENT_2,\n    INPUT_USAGE_KEYCODE_TV_INPUT_VGA_1,\n    INPUT_USAGE_KEYCODE_TV_AUDIO_DESCRIPTION,\n    INPUT_USAGE_KEYCODE_TV_AUDIO_DESCRIPTION_MIX_UP,\n    INPUT_USAGE_KEYCODE_TV_AUDIO_DESCRIPTION_MIX_DOWN,\n    INPUT_USAGE_KEYCODE_TV_ZOOM_MODE,\n    INPUT_USAGE_KEYCODE_TV_CONTENTS_MENU,\n    INPUT_USAGE_KEYCODE_TV_MEDIA_CONTEXT_MENU,\n    INPUT_USAGE_KEYCODE_TV_TIMER_PROGRAMMING,\n    INPUT_USAGE_KEYCODE_HELP,\n\n    // axes\n    INPUT_USAGE_AXIS_X,\n    INPUT_USAGE_AXIS_Y,\n    INPUT_USAGE_AXIS_PRESSURE,\n    INPUT_USAGE_AXIS_SIZE,\n    INPUT_USAGE_AXIS_TOUCH_MAJOR,\n    INPUT_USAGE_AXIS_TOUCH_MINOR,\n    INPUT_USAGE_AXIS_TOOL_MAJOR,\n    INPUT_USAGE_AXIS_TOOL_MINOR,\n    INPUT_USAGE_AXIS_ORIENTATION,\n    INPUT_USAGE_AXIS_VSCROLL,\n    INPUT_USAGE_AXIS_HSCROLL,\n    INPUT_USAGE_AXIS_Z,\n    INPUT_USAGE_AXIS_RX,\n    INPUT_USAGE_AXIS_RY,\n    INPUT_USAGE_AXIS_RZ,\n    INPUT_USAGE_AXIS_HAT_X,\n    INPUT_USAGE_AXIS_HAT_Y,\n    INPUT_USAGE_AXIS_LTRIGGER,\n    INPUT_USAGE_AXIS_RTRIGGER,\n    INPUT_USAGE_AXIS_THROTTLE,\n    INPUT_USAGE_AXIS_RUDDER,\n    INPUT_USAGE_AXIS_WHEEL,\n    INPUT_USAGE_AXIS_GAS,\n    INPUT_USAGE_AXIS_BRAKE,\n    INPUT_USAGE_AXIS_DISTANCE,\n    INPUT_USAGE_AXIS_TILT,\n    INPUT_USAGE_AXIS_GENERIC_1,\n    INPUT_USAGE_AXIS_GENERIC_2,\n    INPUT_USAGE_AXIS_GENERIC_3,\n    INPUT_USAGE_AXIS_GENERIC_4,\n    INPUT_USAGE_AXIS_GENERIC_5,\n    INPUT_USAGE_AXIS_GENERIC_6,\n    INPUT_USAGE_AXIS_GENERIC_7,\n    INPUT_USAGE_AXIS_GENERIC_8,\n    INPUT_USAGE_AXIS_GENERIC_9,\n    INPUT_USAGE_AXIS_GENERIC_10,\n    INPUT_USAGE_AXIS_GENERIC_11,\n    INPUT_USAGE_AXIS_GENERIC_12,\n    INPUT_USAGE_AXIS_GENERIC_13,\n    INPUT_USAGE_AXIS_GENERIC_14,\n    INPUT_USAGE_AXIS_GENERIC_15,\n    INPUT_USAGE_AXIS_GENERIC_16,\n\n    // leds\n    INPUT_USAGE_LED_NUM_LOCK,\n    INPUT_USAGE_LED_CAPS_LOCK,\n    INPUT_USAGE_LED_SCROLL_LOCK,\n    INPUT_USAGE_LED_COMPOSE,\n    INPUT_USAGE_LED_KANA,\n    INPUT_USAGE_LED_SLEEP,\n    INPUT_USAGE_LED_SUSPEND,\n    INPUT_USAGE_LED_MUTE,\n    INPUT_USAGE_LED_MISC,\n    INPUT_USAGE_LED_MAIL,\n    INPUT_USAGE_LED_CHARGING,\n    INPUT_USAGE_LED_CONTROLLER_1,\n    INPUT_USAGE_LED_CONTROLLER_2,\n    INPUT_USAGE_LED_CONTROLLER_3,\n    INPUT_USAGE_LED_CONTROLLER_4,\n} input_usage_t;\n\ntypedef enum {\n    INPUT_COLLECTION_ID_TOUCH,\n    INPUT_COLLECTION_ID_KEYBOARD,\n    INPUT_COLLECTION_ID_MOUSE,\n    INPUT_COLLECTION_ID_TOUCHPAD,\n    // etc\n} input_collection_id_t;\n\ntypedef struct input_message input_message_t;\n\ntypedef struct input_host_callbacks {\n\n    /**\n     * Creates a device identifier with the given properties.\n     * The unique ID should be a string that precisely identifies a given piece of hardware. For\n     * example, an input device connected via Bluetooth could use its MAC address as its unique ID.\n     */\n    input_device_identifier_t* (*create_device_identifier)(input_host_t* host,\n            const char* name, int32_t product_id, int32_t vendor_id,\n            input_bus_t bus, const char* unique_id);\n\n    /**\n     * Allocates the device definition which will describe the input capabilities of a device. A\n     * device definition may be used to register as many devices as desired.\n     */\n    input_device_definition_t* (*create_device_definition)(input_host_t* host);\n\n    /**\n     * Allocate either an input report, which the HAL will use to tell the host of incoming input\n     * events, or an output report, which the host will use to tell the HAL of desired state\n     * changes (e.g. setting an LED).\n     */\n    input_report_definition_t* (*create_input_report_definition)(input_host_t* host);\n    input_report_definition_t* (*create_output_report_definition)(input_host_t* host);\n\n    /**\n     * Append the report to the given input device.\n     */\n    void (*input_device_definition_add_report)(input_host_t* host,\n            input_device_definition_t* d, input_report_definition_t* r);\n\n    /**\n     * Add a collection with the given arity and ID. A collection describes a set\n     * of logically grouped properties such as the X and Y coordinates of a single finger touch or\n     * the set of keys on a keyboard. The arity declares how many repeated instances of this\n     * collection will appear in whatever report it is attached to. The ID describes the type of\n     * grouping being represented by the collection. For example, a touchscreen capable of\n     * reporting up to 2 fingers simultaneously might have a collection with the X and Y\n     * coordinates, an arity of 2, and an ID of INPUT_COLLECTION_USAGE_TOUCHSCREEN. Any given ID\n     * may only be present once for a given report.\n     */\n    void (*input_report_definition_add_collection)(input_host_t* host,\n            input_report_definition_t* report, input_collection_id_t id, int32_t arity);\n\n    /**\n     * Declare an int usage with the given properties. The report and collection defines where the\n     * usage is being declared.\n     */\n    void (*input_report_definition_declare_usage_int)(input_host_t* host,\n            input_report_definition_t* report, input_collection_id_t id,\n            input_usage_t usage, int32_t min, int32_t max, float resolution);\n\n    /**\n     * Declare a set of boolean usages with the given properties.  The report and collection\n     * defines where the usages are being declared.\n     */\n    void (*input_report_definition_declare_usages_bool)(input_host_t* host,\n            input_report_definition_t* report, input_collection_id_t id,\n            input_usage_t* usage, size_t usage_count);\n\n\n    /**\n     * Register a given input device definition. This notifies the host that an input device has\n     * been connected and gives a description of all its capabilities.\n     */\n    input_device_handle_t* (*register_device)(input_host_t* host,\n            input_device_identifier_t* id, input_device_definition_t* d);\n\n    /** Unregister the given device */\n    void (*unregister_device)(input_host_t* host, input_device_handle_t* handle);\n\n    /**\n     * Allocate a report that will contain all of the state as described by the given report.\n     */\n    input_report_t* (*input_allocate_report)(input_host_t* host, input_report_definition_t* r);\n\n    /**\n     * Add an int usage value to a report.\n     */\n    void (*input_report_set_usage_int)(input_host_t* host, input_report_t* r,\n            input_collection_id_t id, input_usage_t usage, int32_t value, int32_t arity_index);\n\n    /**\n     * Add a boolean usage value to a report.\n     */\n    void (*input_report_set_usage_bool)(input_host_t* host, input_report_t* r,\n            input_collection_id_t id, input_usage_t usage, bool value, int32_t arity_index);\n\n    void (*report_event)(input_host_t* host, input_device_handle_t* d, input_report_t* report);\n\n    /**\n     * Retrieve the set of properties for the device. The returned\n     * input_property_map_t* may be used to query specific properties via the\n     * input_get_device_property callback.\n     */\n    input_property_map_t* (*input_get_device_property_map)(input_host_t* host,\n            input_device_identifier_t* id);\n    /**\n     * Retrieve a property for the device with the given key. Returns NULL if\n     * the key does not exist, or an input_property_t* that must be freed using\n     * input_free_device_property(). Using an input_property_t after the\n     * corresponding input_property_map_t is freed is undefined.\n     */\n    input_property_t* (*input_get_device_property)(input_host_t* host,\n            input_property_map_t* map, const char* key);\n\n    /**\n     * Get the key for the input property. Returns NULL if the property is NULL.\n     * The returned const char* is owned by the input_property_t.\n     */\n    const char* (*input_get_property_key)(input_host_t* host, input_property_t* property);\n\n    /**\n     * Get the value for the input property. Returns NULL if the property is\n     * NULL. The returned const char* is owned by the input_property_t.\n     */\n    const char* (*input_get_property_value)(input_host_t* host, input_property_t* property);\n\n    /**\n     * Frees the input_property_t*.\n     */\n    void (*input_free_device_property)(input_host_t* host, input_property_t* property);\n\n    /**\n     * Frees the input_property_map_t*.\n     */\n    void (*input_free_device_property_map)(input_host_t* host, input_property_map_t* map);\n} input_host_callbacks_t;\n\ntypedef struct input_module input_module_t;\n\nstruct input_module {\n    /**\n     * Common methods of the input module. This *must* be the first member\n     * of input_module as users of this structure will cast a hw_module_t\n     * to input_module pointer in contexts where it's known\n     * the hw_module_t references a input_module.\n     */\n    struct hw_module_t common;\n\n    /**\n     * Initialize the module with host callbacks. At this point the HAL should start up whatever\n     * infrastructure it needs to in order to process input events.\n     */\n    void (*init)(const input_module_t* module, input_host_t* host, input_host_callbacks_t cb);\n\n    /**\n     * Sends an output report with a new set of state the host would like the given device to\n     * assume.\n     */\n    void (*notify_report)(const input_module_t* module, input_report_t* report);\n};\n\nstatic inline int input_open(const struct hw_module_t** module, const char* type) {\n    return hw_get_module_by_class(INPUT_HARDWARE_MODULE_ID, type, module);\n}\n\n__END_DECLS\n\n#endif  /* ANDROID_INCLUDE_HARDWARE_INPUT_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/keymaster0.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_HARDWARE_KEYMASTER_0_H\n#define ANDROID_HARDWARE_KEYMASTER_0_H\n\n#include <hardware/keymaster_common.h>\n\n__BEGIN_DECLS\n\n/**\n * Keymaster0 device definition.\n */\nstruct keymaster0_device {\n    /**\n     * Common methods of the keymaster device.  This *must* be the first member of\n     * keymaster0_device as users of this structure will cast a hw_device_t to\n     * keymaster0_device pointer in contexts where it's known the hw_device_t references a\n     * keymaster0_device.\n     */\n    struct hw_device_t common;\n\n    /**\n     * THIS IS DEPRECATED. Use the new \"module_api_version\" and \"hal_api_version\"\n     * fields in the keymaster_module initialization instead.\n     */\n    uint32_t client_version;\n\n    /**\n     * See flags defined for keymaster0_device::flags in keymaster_common.h\n     */\n    uint32_t flags;\n\n    void* context;\n\n    /**\n     * Generates a public and private key. The key-blob returned is opaque\n     * and must subsequently provided for signing and verification.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     */\n    int (*generate_keypair)(const struct keymaster0_device* dev,\n            const keymaster_keypair_t key_type, const void* key_params,\n            uint8_t** key_blob, size_t* key_blob_length);\n\n    /**\n     * Imports a public and private key pair. The imported keys will be in\n     * PKCS#8 format with DER encoding (Java standard). The key-blob\n     * returned is opaque and will be subsequently provided for signing\n     * and verification.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     */\n    int (*import_keypair)(const struct keymaster0_device* dev,\n            const uint8_t* key, const size_t key_length,\n            uint8_t** key_blob, size_t* key_blob_length);\n\n    /**\n     * Gets the public key part of a key pair. The public key must be in\n     * X.509 format (Java standard) encoded byte array.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     * On error, x509_data should not be allocated.\n     */\n    int (*get_keypair_public)(const struct keymaster0_device* dev,\n            const uint8_t* key_blob, const size_t key_blob_length,\n            uint8_t** x509_data, size_t* x509_data_length);\n\n    /**\n     * Deletes the key pair associated with the key blob.\n     *\n     * This function is optional and should be set to NULL if it is not\n     * implemented.\n     *\n     * Returns 0 on success or an error code less than 0.\n     */\n    int (*delete_keypair)(const struct keymaster0_device* dev,\n            const uint8_t* key_blob, const size_t key_blob_length);\n\n    /**\n     * Deletes all keys in the hardware keystore. Used when keystore is\n     * reset completely.\n     *\n     * This function is optional and should be set to NULL if it is not\n     * implemented.\n     *\n     * Returns 0 on success or an error code less than 0.\n     */\n    int (*delete_all)(const struct keymaster0_device* dev);\n\n    /**\n     * Signs data using a key-blob generated before. This can use either\n     * an asymmetric key or a secret key.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     */\n    int (*sign_data)(const struct keymaster0_device* dev,\n            const void* signing_params,\n            const uint8_t* key_blob, const size_t key_blob_length,\n            const uint8_t* data, const size_t data_length,\n            uint8_t** signed_data, size_t* signed_data_length);\n\n    /**\n     * Verifies data signed with a key-blob. This can use either\n     * an asymmetric key or a secret key.\n     *\n     * Returns: 0 on successful verification or an error code less than 0.\n     */\n    int (*verify_data)(const struct keymaster0_device* dev,\n            const void* signing_params,\n            const uint8_t* key_blob, const size_t key_blob_length,\n            const uint8_t* signed_data, const size_t signed_data_length,\n            const uint8_t* signature, const size_t signature_length);\n};\ntypedef struct keymaster0_device keymaster0_device_t;\n\n\n/* Convenience API for opening and closing keymaster devices */\n\nstatic inline int keymaster0_open(const struct hw_module_t* module,\n        keymaster0_device_t** device)\n{\n    int rc = module->methods->open(module, KEYSTORE_KEYMASTER,\n            (struct hw_device_t**) device);\n\n    return rc;\n}\n\nstatic inline int keymaster0_close(keymaster0_device_t* device)\n{\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif  // ANDROID_HARDWARE_KEYMASTER_0_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/keymaster1.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_HARDWARE_KEYMASTER1_H\n#define ANDROID_HARDWARE_KEYMASTER1_H\n\n#include <hardware/keymaster_common.h>\n#include <hardware/keymaster_defs.h>\n\n__BEGIN_DECLS\n\n/**\n * Keymaster1 device definition\n */\nstruct keymaster1_device {\n    /**\n     * Common methods of the keymaster device.  This *must* be the first member of\n     * keymaster_device as users of this structure will cast a hw_device_t to\n     * keymaster_device pointer in contexts where it's known the hw_device_t references a\n     * keymaster_device.\n     */\n    struct hw_device_t common;\n\n    /**\n     * THIS IS DEPRECATED. Use the new \"module_api_version\" and \"hal_api_version\"\n     * fields in the keymaster_module initialization instead.\n     */\n    uint32_t client_version;\n\n    /**\n     * See flags defined for keymaster0_devices::flags in keymaster_common.h\n     */\n    uint32_t flags;\n\n    void* context;\n\n    /**\n     * \\deprecated Generates a public and private key. The key-blob returned is opaque and must\n     * subsequently provided for signing and verification.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     */\n    int (*generate_keypair)(const struct keymaster1_device* dev, const keymaster_keypair_t key_type,\n                            const void* key_params, uint8_t** key_blob, size_t* key_blob_length);\n\n    /**\n     * \\deprecated Imports a public and private key pair. The imported keys will be in PKCS#8 format\n     * with DER encoding (Java standard). The key-blob returned is opaque and will be subsequently\n     * provided for signing and verification.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     */\n    int (*import_keypair)(const struct keymaster1_device* dev, const uint8_t* key,\n                          const size_t key_length, uint8_t** key_blob, size_t* key_blob_length);\n\n    /**\n     * \\deprecated Gets the public key part of a key pair. The public key must be in X.509 format\n     * (Java standard) encoded byte array.\n     *\n     * Returns: 0 on success or an error code less than 0.  On error, x509_data\n     * should not be allocated.\n     */\n    int (*get_keypair_public)(const struct keymaster1_device* dev, const uint8_t* key_blob,\n                              const size_t key_blob_length, uint8_t** x509_data,\n                              size_t* x509_data_length);\n\n    /**\n     * \\deprecated Deletes the key pair associated with the key blob.\n     *\n     * This function is optional and should be set to NULL if it is not\n     * implemented.\n     *\n     * Returns 0 on success or an error code less than 0.\n     */\n    int (*delete_keypair)(const struct keymaster1_device* dev, const uint8_t* key_blob,\n                          const size_t key_blob_length);\n\n    /**\n     * \\deprecated Deletes all keys in the hardware keystore. Used when keystore is reset\n     * completely.\n     *\n     * This function is optional and should be set to NULL if it is not\n     * implemented.\n     *\n     * Returns 0 on success or an error code less than 0.\n     */\n    int (*delete_all)(const struct keymaster1_device* dev);\n\n    /**\n     * \\deprecated Signs data using a key-blob generated before. This can use either an asymmetric\n     * key or a secret key.\n     *\n     * Returns: 0 on success or an error code less than 0.\n     */\n    int (*sign_data)(const struct keymaster1_device* dev, const void* signing_params,\n                     const uint8_t* key_blob, const size_t key_blob_length, const uint8_t* data,\n                     const size_t data_length, uint8_t** signed_data, size_t* signed_data_length);\n\n    /**\n     * \\deprecated Verifies data signed with a key-blob. This can use either an asymmetric key or a\n     * secret key.\n     *\n     * Returns: 0 on successful verification or an error code less than 0.\n     */\n    int (*verify_data)(const struct keymaster1_device* dev, const void* signing_params,\n                       const uint8_t* key_blob, const size_t key_blob_length,\n                       const uint8_t* signed_data, const size_t signed_data_length,\n                       const uint8_t* signature, const size_t signature_length);\n\n    /**\n     * Gets algorithms supported.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[out] algorithms Array of algorithms supported.  The caller takes ownership of the\n     * array and must free() it.\n     *\n     * \\param[out] algorithms_length Length of \\p algorithms.\n     */\n    keymaster_error_t (*get_supported_algorithms)(const struct keymaster1_device* dev,\n                                                  keymaster_algorithm_t** algorithms,\n                                                  size_t* algorithms_length);\n\n    /**\n     * Gets the block modes supported for the specified algorithm.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] algorithm The algorithm for which supported modes will be returned.\n     *\n     * \\param[out] modes Array of modes supported.  The caller takes ownership of the array and must\n     * free() it.\n     *\n     * \\param[out] modes_length Length of \\p modes.\n     */\n    keymaster_error_t (*get_supported_block_modes)(const struct keymaster1_device* dev,\n                                                   keymaster_algorithm_t algorithm,\n                                                   keymaster_purpose_t purpose,\n                                                   keymaster_block_mode_t** modes,\n                                                   size_t* modes_length);\n\n    /**\n     * Gets the padding modes supported for the specified algorithm.  Caller assumes ownership of\n     * the allocated array.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] algorithm The algorithm for which supported padding modes will be returned.\n     *\n     * \\param[out] modes Array of padding modes supported.  The caller takes ownership of the array\n     * and must free() it.\n     *\n     * \\param[out] modes_length Length of \\p modes.\n     */\n    keymaster_error_t (*get_supported_padding_modes)(const struct keymaster1_device* dev,\n                                                     keymaster_algorithm_t algorithm,\n                                                     keymaster_purpose_t purpose,\n                                                     keymaster_padding_t** modes,\n                                                     size_t* modes_length);\n\n    /**\n     * Gets the digests supported for the specified algorithm.  Caller assumes ownership of the\n     * allocated array.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] algorithm The algorithm for which supported digests will be returned.\n     *\n     * \\param[out] digests Array of digests supported.  The caller takes ownership of the array and\n     * must free() it.\n     *\n     * \\param[out] digests_length Length of \\p digests.\n     */\n    keymaster_error_t (*get_supported_digests)(const struct keymaster1_device* dev,\n                                               keymaster_algorithm_t algorithm,\n                                               keymaster_purpose_t purpose,\n                                               keymaster_digest_t** digests,\n                                               size_t* digests_length);\n\n    /**\n     * Gets the key import formats supported for keys of the specified algorithm.  Caller assumes\n     * ownership of the allocated array.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] algorithm The algorithm for which supported formats will be returned.\n     *\n     * \\param[out] formats Array of formats supported.  The caller takes ownership of the array and\n     * must free() it.\n     *\n     * \\param[out] formats_length Length of \\p formats.\n     */\n    keymaster_error_t (*get_supported_import_formats)(const struct keymaster1_device* dev,\n                                                      keymaster_algorithm_t algorithm,\n                                                      keymaster_key_format_t** formats,\n                                                      size_t* formats_length);\n\n    /**\n     * Gets the key export formats supported for keys of the specified algorithm.  Caller assumes\n     * ownership of the allocated array.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] algorithm The algorithm for which supported formats will be returned.\n     *\n     * \\param[out] formats Array of formats supported.  The caller takes ownership of the array and\n     * must free() it.\n     *\n     * \\param[out] formats_length Length of \\p formats.\n     */\n    keymaster_error_t (*get_supported_export_formats)(const struct keymaster1_device* dev,\n                                                      keymaster_algorithm_t algorithm,\n                                                      keymaster_key_format_t** formats,\n                                                      size_t* formats_length);\n\n    /**\n     * Adds entropy to the RNG used by keymaster.  Entropy added through this method is guaranteed\n     * not to be the only source of entropy used, and the mixing function is required to be secure,\n     * in the sense that if the RNG is seeded (from any source) with any data the attacker cannot\n     * predict (or control), then the RNG output is indistinguishable from random.  Thus, if the\n     * entropy from any source is good, the output will be good.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] data Random data to be mixed in.\n     *\n     * \\param[in] data_length Length of \\p data.\n     */\n    keymaster_error_t (*add_rng_entropy)(const struct keymaster1_device* dev, const uint8_t* data,\n                                         size_t data_length);\n\n    /**\n     * Generates a key, or key pair, returning a key blob and/or a description of the key.\n     *\n     * Key generation parameters are defined as keymaster tag/value pairs, provided in \\p params.\n     * See keymaster_tag_t for the full list.  Some values that are always required for generation\n     * of useful keys are:\n     *\n     * - KM_TAG_ALGORITHM;\n     * - KM_TAG_PURPOSE; and\n     * - (KM_TAG_USER_SECURE_ID and KM_TAG_USER_AUTH_TYPE) or KM_TAG_NO_AUTH_REQUIRED.\n     *\n     * KM_TAG_AUTH_TIMEOUT should generally be specified unless KM_TAG_NO_AUTH_REQUIRED is present,\n     * or the user will have to authenticate for every use.\n     *\n     * KM_TAG_BLOCK_MODE, KM_TAG_PADDING, KM_TAG_MAC_LENGTH and KM_TAG_DIGEST must be specified for\n     * algorithms that require them.\n     *\n     * The following tags may not be specified; their values will be provided by the implementation.\n     *\n     * - KM_TAG_ORIGIN,\n     * - KM_TAG_ROLLBACK_RESISTANT,\n     * - KM_TAG_CREATION_DATETIME\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] params Array of key generation parameters.\n     *\n     * \\param[in] params_count Length of \\p params.\n     *\n     * \\param[out] key_blob returns the generated key. \\p key_blob must not be NULL.  The caller\n     * assumes ownership key_blob->key_material and must free() it.\n     *\n     * \\param[out] characteristics returns the characteristics of the key that was, generated, if\n     * non-NULL.  If non-NULL, the caller assumes ownership and must deallocate with\n     * keymaster_free_characteristics().  Note that KM_TAG_ROOT_OF_TRUST, KM_TAG_APPLICATION_ID and\n     * KM_TAG_APPLICATION_DATA are never returned.\n     */\n    keymaster_error_t (*generate_key)(const struct keymaster1_device* dev,\n                                      const keymaster_key_param_set_t* params,\n                                      keymaster_key_blob_t* key_blob,\n                                      keymaster_key_characteristics_t** characteristics);\n\n    /**\n     * Returns the characteristics of the specified key, or KM_ERROR_INVALID_KEY_BLOB if the\n     * key_blob is invalid (implementations must fully validate the integrity of the key).\n     * client_id and app_data must be the ID and data provided when the key was generated or\n     * imported, or empty if KM_TAG_APPLICATION_ID and/or KM_TAG_APPLICATION_DATA were not provided\n     * during generation.  Those values are not included in the returned characteristics.  The\n     * caller assumes ownership of the allocated characteristics object, which must be deallocated\n     * with keymaster_free_characteristics().\n     *\n     * Note that KM_TAG_ROOT_OF_TRUST, KM_TAG_APPLICATION_ID and KM_TAG_APPLICATION_DATA are never\n     * returned.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] key_blob The key to retreive characteristics from.\n     *\n     * \\param[in] client_id The client ID data, or NULL if none associated.\n     *\n     * \\param[in] app_id The app data, or NULL if none associated.\n     *\n     * \\param[out] characteristics The key characteristics.\n     */\n    keymaster_error_t (*get_key_characteristics)(const struct keymaster1_device* dev,\n                                                 const keymaster_key_blob_t* key_blob,\n                                                 const keymaster_blob_t* client_id,\n                                                 const keymaster_blob_t* app_data,\n                                                 keymaster_key_characteristics_t** characteristics);\n\n    /**\n     * Imports a key, or key pair, returning a key blob and/or a description of the key.\n     *\n     * Most key import parameters are defined as keymaster tag/value pairs, provided in \"params\".\n     * See keymaster_tag_t for the full list.  Values that are always required for import of useful\n     * keys are:\n     *\n     * - KM_TAG_ALGORITHM;\n     * - KM_TAG_PURPOSE; and\n     * - (KM_TAG_USER_SECURE_ID and KM_TAG_USER_AUTH_TYPE) or KM_TAG_NO_AUTH_REQUIRED.\n     *\n     * KM_TAG_AUTH_TIMEOUT should generally be specified. If unspecified, the user will have to\n     * authenticate for every use.\n     *\n     * The following tags will take default values if unspecified:\n     *\n     * - KM_TAG_KEY_SIZE will default to the size of the key provided.\n     * - KM_TAG_RSA_PUBLIC_EXPONENT will default to the value in the key provided (for RSA keys)\n     *\n     * The following tags may not be specified; their values will be provided by the implementation.\n     *\n     * - KM_TAG_ORIGIN,\n     * - KM_TAG_ROLLBACK_RESISTANT,\n     * - KM_TAG_CREATION_DATETIME\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] params Parameters defining the imported key.\n     *\n     * \\param[in] params_count The number of entries in \\p params.\n     *\n     * \\param[in] key_format specifies the format of the key data in key_data.\n     *\n     * \\param[out] key_blob Used to return the opaque key blob.  Must be non-NULL.  The caller\n     * assumes ownership of the contained key_material.\n     *\n     * \\param[out] characteristics Used to return the characteristics of the imported key.  May be\n     * NULL, in which case no characteristics will be returned.  If non-NULL, the caller assumes\n     * ownership and must deallocate with keymaster_free_characteristics().  Note that\n     * KM_TAG_ROOT_OF_TRUST, KM_TAG_APPLICATION_ID and\n     * KM_TAG_APPLICATION_DATA are never returned.\n     */\n    keymaster_error_t (*import_key)(const struct keymaster1_device* dev,\n                                    const keymaster_key_param_set_t* params,\n                                    keymaster_key_format_t key_format,\n                                    const keymaster_blob_t* key_data,\n                                    keymaster_key_blob_t* key_blob,\n                                    keymaster_key_characteristics_t** characteristics);\n\n    /**\n     * Exports a public key, returning a byte array in the specified format.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] export_format The format to be used for exporting the key.\n     *\n     * \\param[in] key_to_export The key to export.\n     *\n     * \\param[out] export_data The exported key material.  The caller assumes ownership.\n     *\n     * \\param[out] export_data_length The length of \\p export_data.\n     */\n    keymaster_error_t (*export_key)(const struct keymaster1_device* dev,\n                                    keymaster_key_format_t export_format,\n                                    const keymaster_key_blob_t* key_to_export,\n                                    const keymaster_blob_t* client_id,\n                                    const keymaster_blob_t* app_data,\n                                    keymaster_blob_t* export_data);\n\n    /**\n     * Deletes the key, or key pair, associated with the key blob.  After calling this function it\n     * will be impossible to use the key for any other operations.  May be applied to keys from\n     * foreign roots of trust (keys not usable under the current root of trust).\n     *\n     * This function is optional and should be set to NULL if it is not implemented.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] key The key to be deleted.\n     */\n    keymaster_error_t (*delete_key)(const struct keymaster1_device* dev,\n                                    const keymaster_key_blob_t* key);\n\n    /**\n     * Deletes all keys in the hardware keystore. Used when keystore is reset completely.  After\n     * calling this function it will be impossible to use any previously generated or imported key\n     * blobs for any operations.\n     *\n     * This function is optional and should be set to NULL if it is not implemented.\n     *\n     * \\param[in] dev The keymaster device structure.\n     */\n    keymaster_error_t (*delete_all_keys)(const struct keymaster1_device* dev);\n\n    /**\n     * Begins a cryptographic operation using the specified key.  If all is well, begin() will\n     * return KM_ERROR_OK and create an operation handle which must be passed to subsequent calls to\n     * update(), finish() or abort().\n     *\n     * It is critical that each call to begin() be paired with a subsequent call to finish() or\n     * abort(), to allow the keymaster implementation to clean up any internal operation state.\n     * Failure to do this may leak internal state space or other internal resources and may\n     * eventually cause begin() to return KM_ERROR_TOO_MANY_OPERATIONS when it runs out of space for\n     * operations.  Any result other than KM_ERROR_OK from begin(), update() or finish() implicitly\n     * aborts the operation, in which case abort() need not be called (and will return\n     * KM_ERROR_INVALID_OPERATION_HANDLE if called).\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] purpose The purpose of the operation, one of KM_PURPOSE_ENCRYPT,\n     * KM_PURPOSE_DECRYPT, KM_PURPOSE_SIGN or KM_PURPOSE_VERIFY. Note that for AEAD modes,\n     * encryption and decryption imply signing and verification, respectively, but should be\n     * specified as KM_PURPOSE_ENCRYPT and KM_PURPOSE_DECRYPT.\n     *\n     * \\param[in] key The key to be used for the operation. \\p key must have a purpose compatible\n     * with \\p purpose and all of its usage requirements must be satisfied, or begin() will return\n     * an appropriate error code.\n     *\n     * \\param[in] in_params Additional parameters for the operation.  This is typically used to\n     * provide authentication data, with KM_TAG_AUTH_TOKEN.  If KM_TAG_APPLICATION_ID or\n     * KM_TAG_APPLICATION_DATA were provided during generation, they must be provided here, or the\n     * operation will fail with KM_ERROR_INVALID_KEY_BLOB.  For operations that require a nonce or\n     * IV, on keys that were generated with KM_TAG_CALLER_NONCE, in_params may contain a tag\n     * KM_TAG_NONCE.  For AEAD operations KM_TAG_CHUNK_SIZE is specified here.\n     *\n     * \\param[out] out_params Output parameters.  Used to return additional data from the operation\n     * initialization, notably to return the IV or nonce from operations that generate an IV or\n     * nonce.  The caller takes ownership of the output parameters array and must free it with\n     * keymaster_free_param_set().  out_params may be set to NULL if no output parameters are\n     * expected.  If out_params is NULL, and output paramaters are generated, begin() will return\n     * KM_ERROR_OUTPUT_PARAMETER_NULL.\n     *\n     * \\param[out] operation_handle The newly-created operation handle which must be passed to\n     * update(), finish() or abort().  If operation_handle is NULL, begin() will return\n     * KM_ERROR_OUTPUT_PARAMETER_NULL.\n     */\n    keymaster_error_t (*begin)(const struct keymaster1_device* dev, keymaster_purpose_t purpose,\n                               const keymaster_key_blob_t* key,\n                               const keymaster_key_param_set_t* in_params,\n                               keymaster_key_param_set_t* out_params,\n                               keymaster_operation_handle_t* operation_handle);\n\n    /**\n     * Provides data to, and possibly receives output from, an ongoing cryptographic operation begun\n     * with begin().\n     *\n     * If operation_handle is invalid, update() will return KM_ERROR_INVALID_OPERATION_HANDLE.\n     *\n     * update() may not consume all of the data provided in the data buffer.  update() will return\n     * the amount consumed in *data_consumed.  The caller should provide the unconsumed data in a\n     * subsequent call.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] operation_handle The operation handle returned by begin().\n     *\n     * \\param[in] in_params Additional parameters for the operation.  For AEAD modes, this is used\n     * to specify KM_TAG_ADDITIONAL_DATA.  Note that additional data may be provided in multiple\n     * calls to update(), but only until input data has been provided.\n     *\n     * \\param[in] input Data to be processed, per the parameters established in the call to begin().\n     * Note that update() may or may not consume all of the data provided.  See \\p input_consumed.\n     *\n     * \\param[out] input_consumed Amount of data that was consumed by update().  If this is less\n     * than the amount provided, the caller should provide the remainder in a subsequent call to\n     * update().\n     *\n     * \\param[out] out_params Output parameters.  Used to return additional data from the operation\n     * The caller takes ownership of the output parameters array and must free it with\n     * keymaster_free_param_set().  out_params may be set to NULL if no output parameters are\n     * expected.  If out_params is NULL, and output paramaters are generated, begin() will return\n     * KM_ERROR_OUTPUT_PARAMETER_NULL.\n     *\n     * \\param[out] output The output data, if any.  The caller assumes ownership of the allocated\n     * buffer.  output must not be NULL.\n     *\n     * Note that update() may not provide any output, in which case output->data_length will be\n     * zero, and output->data may be either NULL or zero-length (so the caller should always free()\n     * it).\n     */\n    keymaster_error_t (*update)(const struct keymaster1_device* dev,\n                                keymaster_operation_handle_t operation_handle,\n                                const keymaster_key_param_set_t* in_params,\n                                const keymaster_blob_t* input, size_t* input_consumed,\n                                keymaster_key_param_set_t* out_params, keymaster_blob_t* output);\n\n    /**\n     * Finalizes a cryptographic operation begun with begin() and invalidates \\p operation_handle.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] operation_handle The operation handle returned by begin().  This handle will be\n     * invalidated.\n     *\n     * \\param[in] params Additional parameters for the operation.  For AEAD modes, this is used to\n     * specify KM_TAG_ADDITIONAL_DATA, but only if no input data was provided to update().\n     *\n     * \\param[in] signature The signature to be verified if the purpose specified in the begin()\n     * call was KM_PURPOSE_VERIFY.\n     *\n     * \\param[out] output The output data, if any.  The caller assumes ownership of the allocated\n     * buffer.\n     *\n     * If the operation being finished is a signature verification or an AEAD-mode decryption and\n     * verification fails then finish() will return KM_ERROR_VERIFICATION_FAILED.\n     */\n    keymaster_error_t (*finish)(const struct keymaster1_device* dev,\n                                keymaster_operation_handle_t operation_handle,\n                                const keymaster_key_param_set_t* in_params,\n                                const keymaster_blob_t* signature,\n                                keymaster_key_param_set_t* out_params, keymaster_blob_t* output);\n\n    /**\n     * Aborts a cryptographic operation begun with begin(), freeing all internal resources and\n     * invalidating \\p operation_handle.\n     */\n    keymaster_error_t (*abort)(const struct keymaster1_device* dev,\n                               keymaster_operation_handle_t operation_handle);\n\n    /**\n     * Generates a pair of ATTK defined in SOTER. Save the private key into RPMB.\n     * Note that the ATTK generated will never be touched outside the keymaster.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[in] copy_num The number of copies that will be saved in the RPMB.\n     */\n    keymaster_error_t (*generate_attk_key_pair)(const struct keymaster1_device* dev,\n                                                const uint8_t copy_num);\n\n    /**\n     * Verify the existance ATTK defined in SOTER.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * Returns: 0 if the ATTK exists.\n     */\n    keymaster_error_t (*verify_attk_key_pair)(const struct keymaster1_device* dev);\n\n    /**\n     * Export the public key of ATTK in PEM format.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[out] pub_key_data The public key data in X.509v3 format PEM encoded\n     *\n     * \\param[out] pub_key_data_length The length of the public key data.\n     */\n    keymaster_error_t (*export_attk_public_key)(const struct keymaster1_device* dev,\n                                                const uint8_t* pub_key_data,\n                                                const size_t pub_key_data_length);\n\n    /**\n     * Get Unique device ID.\n     *\n     * \\param[in] dev The keymaster device structure.\n     *\n     * \\param[out] device_id The unique id for each device, format as below:\n     * 1.bytes 0-3: Identify each silicon provider id.\n     * 2.bytes 4-7: SoC model ID, defined by each silicon provider\n     * 3.bytes 8-15: Public Chip Serial *Number of SoC, defined by each silicon provider\n     *\n     * \\param[out] device_id_length The length of the device id.\n     */\n    keymaster_error_t (*get_device_id)(const struct keymaster1_device* dev,\n                                                const uint8_t* device_id,\n                                                const size_t device_id_length);\n};\ntypedef struct keymaster1_device keymaster1_device_t;\n\n/* Convenience API for opening and closing keymaster devices */\n\nstatic inline int keymaster1_open(const struct hw_module_t* module, keymaster1_device_t** device) {\n    return module->methods->open(module, KEYSTORE_KEYMASTER, (struct hw_device_t**)device);\n}\n\nstatic inline int keymaster1_close(keymaster1_device_t* device) {\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif  // ANDROID_HARDWARE_KEYMASTER1_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/keymaster_common.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_HARDWARE_KEYMASTER_COMMON_H\n#define ANDROID_HARDWARE_KEYMASTER_COMMON_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define KEYSTORE_HARDWARE_MODULE_ID \"keystore\"\n\n#define KEYSTORE_KEYMASTER \"keymaster\"\n\n\n/**\n * Settings for \"module_api_version\" and \"hal_api_version\"\n * fields in the keymaster_module initialization.\n */\n\n/**\n * Keymaster 0.X module version provide the same APIs, but later versions add more options\n * for algorithms and flags.\n */\n#define KEYMASTER_MODULE_API_VERSION_0_2 HARDWARE_MODULE_API_VERSION(0, 2)\n#define KEYMASTER_DEVICE_API_VERSION_0_2 HARDWARE_DEVICE_API_VERSION(0, 2)\n\n#define KEYMASTER_MODULE_API_VERSION_0_3 HARDWARE_MODULE_API_VERSION(0, 3)\n#define KEYMASTER_DEVICE_API_VERSION_0_3 HARDWARE_DEVICE_API_VERSION(0, 3)\n\n/**\n * Keymaster 1.0 module version provides a completely different API, incompatible with 0.X.\n */\n#define KEYMASTER_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define KEYMASTER_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n\nstruct keystore_module {\n    /**\n     * Common methods of the keystore module.  This *must* be the first member of keystore_module as\n     * users of this structure will cast a hw_module_t to keystore_module pointer in contexts where\n     * it's known the hw_module_t references a keystore_module.\n     */\n    hw_module_t common;\n\n    /* There are no keystore module methods other than the common ones. */\n};\n\n/**\n * Flags for keymaster0_device::flags\n */\nenum {\n    /*\n     * Indicates this keymaster implementation does not have hardware that\n     * keeps private keys out of user space.\n     *\n     * This should not be implemented on anything other than the default\n     * implementation.\n     */\n    KEYMASTER_SOFTWARE_ONLY = 1 << 0,\n\n    /*\n     * This indicates that the key blobs returned via all the primitives\n     * are sufficient to operate on their own without the trusted OS\n     * querying userspace to retrieve some other data. Key blobs of\n     * this type are normally returned encrypted with a\n     * Key Encryption Key (KEK).\n     *\n     * This is currently used by \"vold\" to know whether the whole disk\n     * encryption secret can be unwrapped without having some external\n     * service started up beforehand since the \"/data\" partition will\n     * be unavailable at that point.\n     */\n    KEYMASTER_BLOBS_ARE_STANDALONE = 1 << 1,\n\n    /*\n     * Indicates that the keymaster module supports DSA keys.\n     */\n    KEYMASTER_SUPPORTS_DSA = 1 << 2,\n\n    /*\n     * Indicates that the keymaster module supports EC keys.\n     */\n    KEYMASTER_SUPPORTS_EC = 1 << 3,\n};\n\n/**\n * Asymmetric key pair types.\n */\ntypedef enum {\n    TYPE_RSA = 1,\n    TYPE_DSA = 2,\n    TYPE_EC = 3,\n} keymaster_keypair_t;\n\n/**\n * Parameters needed to generate an RSA key.\n */\ntypedef struct {\n    uint32_t modulus_size;\n    uint64_t public_exponent;\n} keymaster_rsa_keygen_params_t;\n\n/**\n * Parameters needed to generate a DSA key.\n */\ntypedef struct {\n    uint32_t key_size;\n    uint32_t generator_len;\n    uint32_t prime_p_len;\n    uint32_t prime_q_len;\n    const uint8_t* generator;\n    const uint8_t* prime_p;\n    const uint8_t* prime_q;\n} keymaster_dsa_keygen_params_t;\n\n/**\n * Parameters needed to generate an EC key.\n *\n * Field size is the only parameter in version 2. The sizes correspond to these required curves:\n *\n * 192 = NIST P-192\n * 224 = NIST P-224\n * 256 = NIST P-256\n * 384 = NIST P-384\n * 521 = NIST P-521\n *\n * The parameters for these curves are available at: http://www.nsa.gov/ia/_files/nist-routines.pdf\n * in Chapter 4.\n */\ntypedef struct {\n    uint32_t field_size;\n} keymaster_ec_keygen_params_t;\n\n\n/**\n * Digest type.\n */\ntypedef enum {\n    DIGEST_NONE,\n} keymaster_digest_algorithm_t;\n\n/**\n * Type of padding used for RSA operations.\n */\ntypedef enum {\n    PADDING_NONE,\n} keymaster_rsa_padding_t;\n\n\ntypedef struct {\n    keymaster_digest_algorithm_t digest_type;\n} keymaster_dsa_sign_params_t;\n\ntypedef struct {\n    keymaster_digest_algorithm_t digest_type;\n} keymaster_ec_sign_params_t;\n\ntypedef struct {\n    keymaster_digest_algorithm_t digest_type;\n    keymaster_rsa_padding_t padding_type;\n} keymaster_rsa_sign_params_t;\n\n__END_DECLS\n\n#endif  // ANDROID_HARDWARE_KEYMASTER_COMMON_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/keymaster_defs.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_HARDWARE_KEYMASTER_DEFS_H\n#define ANDROID_HARDWARE_KEYMASTER_DEFS_H\n\n#include <stdint.h>\n#include <stdlib.h>\n#include <string.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif  // __cplusplus\n\n/**\n * Authorization tags each have an associated type.  This enumeration facilitates tagging each with\n * a type, by using the high four bits (of an implied 32-bit unsigned enum value) to specify up to\n * 16 data types.  These values are ORed with tag IDs to generate the final tag ID values.\n */\ntypedef enum {\n    KM_INVALID = 0 << 28, /* Invalid type, used to designate a tag as uninitialized */\n    KM_ENUM = 1 << 28,\n    KM_ENUM_REP = 2 << 28, /* Repeatable enumeration value. */\n    KM_UINT = 3 << 28,\n    KM_UINT_REP = 4 << 28, /* Repeatable integer value */\n    KM_ULONG = 5 << 28,\n    KM_DATE = 6 << 28,\n    KM_BOOL = 7 << 28,\n    KM_BIGNUM = 8 << 28,\n    KM_BYTES = 9 << 28,\n    KM_ULONG_REP = 10 << 28, /* Repeatable long value */\n} keymaster_tag_type_t;\n\ntypedef enum {\n    KM_TAG_INVALID = KM_INVALID | 0,\n\n    /*\n     * Tags that must be semantically enforced by hardware and software implementations.\n     */\n\n    /* Crypto parameters */\n    KM_TAG_PURPOSE = KM_ENUM_REP | 1,     /* keymaster_purpose_t. */\n    KM_TAG_ALGORITHM = KM_ENUM | 2,       /* keymaster_algorithm_t. */\n    KM_TAG_KEY_SIZE = KM_UINT | 3,        /* Key size in bits. */\n    KM_TAG_BLOCK_MODE = KM_ENUM_REP | 4,  /* keymaster_block_mode_t. */\n    KM_TAG_DIGEST = KM_ENUM_REP | 5,      /* keymaster_digest_t. */\n    KM_TAG_PADDING = KM_ENUM_REP | 6,     /* keymaster_padding_t. */\n    KM_TAG_CALLER_NONCE = KM_BOOL | 7,    /* Allow caller to specify nonce or IV. */\n    KM_TAG_MIN_MAC_LENGTH = KM_UINT | 8,  /* Minimum length of MAC or AEAD authentication tag in\n                                           * bits. */\n\n    /* Algorithm-specific. */\n    KM_TAG_RSA_PUBLIC_EXPONENT = KM_ULONG | 200,\n\n    /* Other hardware-enforced. */\n    KM_TAG_BLOB_USAGE_REQUIREMENTS = KM_ENUM | 301, /* keymaster_key_blob_usage_requirements_t */\n    KM_TAG_BOOTLOADER_ONLY = KM_BOOL | 302,         /* Usable only by bootloader */\n\n    /*\n     * Tags that should be semantically enforced by hardware if possible and will otherwise be\n     * enforced by software (keystore).\n     */\n\n    /* Key validity period */\n    KM_TAG_ACTIVE_DATETIME = KM_DATE | 400,             /* Start of validity */\n    KM_TAG_ORIGINATION_EXPIRE_DATETIME = KM_DATE | 401, /* Date when new \"messages\" should no\n                                                           longer be created. */\n    KM_TAG_USAGE_EXPIRE_DATETIME = KM_DATE | 402,       /* Date when existing \"messages\" should no\n                                                           longer be trusted. */\n    KM_TAG_MIN_SECONDS_BETWEEN_OPS = KM_UINT | 403,     /* Minimum elapsed time between\n                                                           cryptographic operations with the key. */\n    KM_TAG_MAX_USES_PER_BOOT = KM_UINT | 404,           /* Number of times the key can be used per\n                                                           boot. */\n\n    /* User authentication */\n    KM_TAG_ALL_USERS = KM_BOOL | 500,           /* Reserved for future use -- ignore */\n    KM_TAG_USER_ID = KM_UINT | 501,             /* Reserved for future use -- ignore */\n    KM_TAG_USER_SECURE_ID = KM_ULONG_REP | 502, /* Secure ID of authorized user or authenticator(s).\n                                                   Disallowed if KM_TAG_ALL_USERS or\n                                                   KM_TAG_NO_AUTH_REQUIRED is present. */\n    KM_TAG_NO_AUTH_REQUIRED = KM_BOOL | 503,    /* If key is usable without authentication. */\n    KM_TAG_USER_AUTH_TYPE = KM_ENUM | 504,      /* Bitmask of authenticator types allowed when\n                                                 * KM_TAG_USER_SECURE_ID contains a secure user ID,\n                                                 * rather than a secure authenticator ID.  Defined in\n                                                 * hw_authenticator_type_t in hw_auth_token.h. */\n    KM_TAG_AUTH_TIMEOUT = KM_UINT | 505,        /* Required freshness of user authentication for\n                                                   private/secret key operations, in seconds.\n                                                   Public key operations require no authentication.\n                                                   If absent, authentication is required for every\n                                                   use.  Authentication state is lost when the\n                                                   device is powered off. */\n\n    /* Application access control */\n    KM_TAG_ALL_APPLICATIONS = KM_BOOL | 600, /* Reserved for future use -- ignore */\n    KM_TAG_APPLICATION_ID = KM_BYTES | 601,  /* Reserved for fugure use -- ignore */\n\n    /*\n     * Semantically unenforceable tags, either because they have no specific meaning or because\n     * they're informational only.\n     */\n    KM_TAG_APPLICATION_DATA = KM_BYTES | 700,  /* Data provided by authorized application. */\n    KM_TAG_CREATION_DATETIME = KM_DATE | 701,  /* Key creation time */\n    KM_TAG_ORIGIN = KM_ENUM | 702,             /* keymaster_key_origin_t. */\n    KM_TAG_ROLLBACK_RESISTANT = KM_BOOL | 703, /* Whether key is rollback-resistant. */\n    KM_TAG_ROOT_OF_TRUST = KM_BYTES | 704,     /* Root of trust ID. */\n\n    /* Tags used only to provide data to or receive data from operations */\n    KM_TAG_ASSOCIATED_DATA = KM_BYTES | 1000, /* Used to provide associated data for AEAD modes. */\n    KM_TAG_NONCE = KM_BYTES | 1001,           /* Nonce or Initialization Vector */\n    KM_TAG_AUTH_TOKEN = KM_BYTES | 1002,      /* Authentication token that proves secure user\n                                                 authentication has been performed.  Structure\n                                                 defined in hw_auth_token_t in hw_auth_token.h. */\n    KM_TAG_MAC_LENGTH = KM_UINT | 1003,       /* MAC or AEAD authentication tag length in bits. */\n\n    /* Tags used only for SOTER */\n    /* Tags used only to check if the key is for SOTER */\n    KM_TAG_SOTER_IS_FROM_SOTER = KM_BOOL | 11000,\n    /* Attach signature signed with ATTK[pri] while exporting public key */\n    KM_TAG_SOTER_IS_AUTO_SIGNED_WITH_ATTK_WHEN_GET_PUBLIC_KEY = KM_BOOL | 11001,\n    /* Attach signature signed with specified private key while exporting public key */\n    KM_TAG_SOTER_IS_AUTO_SIGNED_WITH_COMMON_KEY_WHEN_GET_PUBLIC_KEY = KM_BOOL | 11002,\n    /* keyalias for the keypair of KM_TAG_SOTER_IS_AUTO_SIGNED_WITH_COMMON_KEY_WHEN_GET_PUBLIC_KEY */\n    KM_TAG_SOTER_AUTO_SIGNED_COMMON_KEY_WHEN_GET_PUBLIC_KEY = KM_BYTES | 11003,\n    /* Attach counter while exporting publick key */\n    KM_TAG_SOTER_AUTO_ADD_COUNTER_WHEN_GET_PUBLIC_KEY = KM_BOOL | 11004,\n    /* Attach secmsg(TEE_Name, TEE_Version, Fingerprint_Sensor_Name, Fingerprint_Sensor_Version)\n       fingerprint_id and counter while signing */\n    KM_TAG_SOTER_IS_SECMSG_FID_COUNTER_SIGNED_WHEN_SIGN = KM_BOOL | 11005,\n    /* use and set ATTK index to next backup ATTK */\n    KM_TAG_SOTER_USE_NEXT_ATTK = KM_BOOL | 11006,\n    /* attach soter uid */\n    KM_TAG_SOTER_UID = KM_UINT | 11007,\n    /* attach key blob of KM_TAG_SOTER_AUTO_SIGNED_COMMON_KEY_WHEN_GET_PUBLIC_KEY if needed */\n    KM_TAG_SOTER_AUTO_SIGNED_COMMON_KEY_WHEN_GET_PUBLIC_KEY_BLOB = KM_BYTES | 11008,\n} keymaster_tag_t;\n\n/**\n * Algorithms that may be provided by keymaster implementations.  Those that must be provided by all\n * implementations are tagged as \"required\".\n */\ntypedef enum {\n    /* Asymmetric algorithms. */\n    KM_ALGORITHM_RSA = 1,\n    // KM_ALGORITHM_DSA = 2, -- Removed, do not re-use value 2.\n    KM_ALGORITHM_EC = 3,\n\n    /* Block ciphers algorithms */\n    KM_ALGORITHM_AES = 32,\n\n    /* MAC algorithms */\n    KM_ALGORITHM_HMAC = 128,\n} keymaster_algorithm_t;\n\n/**\n * Symmetric block cipher modes provided by keymaster implementations.\n */\ntypedef enum {\n    /* Unauthenticated modes, usable only for encryption/decryption and not generally recommended\n     * except for compatibility with existing other protocols. */\n    KM_MODE_ECB = 1,\n    KM_MODE_CBC = 2,\n    KM_MODE_CTR = 3,\n\n    /* Authenticated modes, usable for encryption/decryption and signing/verification.  Recommended\n     * over unauthenticated modes for all purposes. */\n    KM_MODE_GCM = 32,\n} keymaster_block_mode_t;\n\n/**\n * Padding modes that may be applied to plaintext for encryption operations.  This list includes\n * padding modes for both symmetric and asymmetric algorithms.  Note that implementations should not\n * provide all possible combinations of algorithm and padding, only the\n * cryptographically-appropriate pairs.\n */\ntypedef enum {\n    KM_PAD_NONE = 1, /* deprecated */\n    KM_PAD_RSA_OAEP = 2,\n    KM_PAD_RSA_PSS = 3,\n    KM_PAD_RSA_PKCS1_1_5_ENCRYPT = 4,\n    KM_PAD_RSA_PKCS1_1_5_SIGN = 5,\n    KM_PAD_PKCS7 = 64,\n} keymaster_padding_t;\n\n/**\n * Digests provided by keymaster implementations.\n */\ntypedef enum {\n    KM_DIGEST_NONE = 0,\n    KM_DIGEST_MD5 = 1, /* Optional, may not be implemented in hardware, will be handled in software\n                        * if needed. */\n    KM_DIGEST_SHA1 = 2,\n    KM_DIGEST_SHA_2_224 = 3,\n    KM_DIGEST_SHA_2_256 = 4,\n    KM_DIGEST_SHA_2_384 = 5,\n    KM_DIGEST_SHA_2_512 = 6,\n} keymaster_digest_t;\n\n/**\n * The origin of a key (or pair), i.e. where it was generated.  Note that KM_TAG_ORIGIN can be found\n * in either the hardware-enforced or software-enforced list for a key, indicating whether the key\n * is hardware or software-based.  Specifically, a key with KM_ORIGIN_GENERATED in the\n * hardware-enforced list is guaranteed never to have existed outide the secure hardware.\n */\ntypedef enum {\n    KM_ORIGIN_GENERATED = 0, /* Generated in keymaster */\n    KM_ORIGIN_IMPORTED = 2,  /* Imported, origin unknown */\n    KM_ORIGIN_UNKNOWN = 3,   /* Keymaster did not record origin.  This value can only be seen on\n                              * keys in a keymaster0 implementation.  The keymaster0 adapter uses\n                              * this value to document the fact that it is unkown whether the key\n                              * was generated inside or imported into keymaster. */\n} keymaster_key_origin_t;\n\n/**\n * Usability requirements of key blobs.  This defines what system functionality must be available\n * for the key to function.  For example, key \"blobs\" which are actually handles referencing\n * encrypted key material stored in the file system cannot be used until the file system is\n * available, and should have BLOB_REQUIRES_FILE_SYSTEM.  Other requirements entries will be added\n * as needed for implementations.  This type is new in 0_4.\n */\ntypedef enum {\n    KM_BLOB_STANDALONE = 0,\n    KM_BLOB_REQUIRES_FILE_SYSTEM = 1,\n} keymaster_key_blob_usage_requirements_t;\n\n/**\n * Possible purposes of a key (or pair). This type is new in 0_4.\n */\ntypedef enum {\n    KM_PURPOSE_ENCRYPT = 0,\n    KM_PURPOSE_DECRYPT = 1,\n    KM_PURPOSE_SIGN = 2,\n    KM_PURPOSE_VERIFY = 3,\n} keymaster_purpose_t;\n\ntypedef struct {\n    const uint8_t* data;\n    size_t data_length;\n} keymaster_blob_t;\n\ntypedef struct {\n    keymaster_tag_t tag;\n    union {\n        uint32_t enumerated;   /* KM_ENUM and KM_ENUM_REP */\n        bool boolean;          /* KM_BOOL */\n        uint32_t integer;      /* KM_INT and KM_INT_REP */\n        uint64_t long_integer; /* KM_LONG */\n        uint64_t date_time;    /* KM_DATE */\n        keymaster_blob_t blob; /* KM_BIGNUM and KM_BYTES*/\n    };\n} keymaster_key_param_t;\n\ntypedef struct {\n    keymaster_key_param_t* params; /* may be NULL if length == 0 */\n    size_t length;\n} keymaster_key_param_set_t;\n\n/**\n * Parameters that define a key's characteristics, including authorized modes of usage and access\n * control restrictions.  The parameters are divided into two categories, those that are enforced by\n * secure hardware, and those that are not.  For a software-only keymaster implementation the\n * enforced array must NULL.  Hardware implementations must enforce everything in the enforced\n * array.\n */\ntypedef struct {\n    keymaster_key_param_set_t hw_enforced;\n    keymaster_key_param_set_t sw_enforced;\n} keymaster_key_characteristics_t;\n\ntypedef struct {\n    const uint8_t* key_material;\n    size_t key_material_size;\n} keymaster_key_blob_t;\n\n/**\n * Formats for key import and export.  At present, only asymmetric key import/export is supported.\n * In the future this list will expand greatly to accommodate asymmetric key import/export.\n */\ntypedef enum {\n    KM_KEY_FORMAT_X509 = 0,  /* for public key export */\n    KM_KEY_FORMAT_PKCS8 = 1, /* for asymmetric key pair import */\n    KM_KEY_FORMAT_RAW = 3,   /* for symmetric key import */\n} keymaster_key_format_t;\n\n/**\n * The keymaster operation API consists of begin, update, finish and abort. This is the type of the\n * handle used to tie the sequence of calls together.  A 64-bit value is used because it's important\n * that handles not be predictable.  Implementations must use strong random numbers for handle\n * values.\n */\ntypedef uint64_t keymaster_operation_handle_t;\n\ntypedef enum {\n    KM_ERROR_OK = 0,\n    KM_ERROR_ROOT_OF_TRUST_ALREADY_SET = -1,\n    KM_ERROR_UNSUPPORTED_PURPOSE = -2,\n    KM_ERROR_INCOMPATIBLE_PURPOSE = -3,\n    KM_ERROR_UNSUPPORTED_ALGORITHM = -4,\n    KM_ERROR_INCOMPATIBLE_ALGORITHM = -5,\n    KM_ERROR_UNSUPPORTED_KEY_SIZE = -6,\n    KM_ERROR_UNSUPPORTED_BLOCK_MODE = -7,\n    KM_ERROR_INCOMPATIBLE_BLOCK_MODE = -8,\n    KM_ERROR_UNSUPPORTED_MAC_LENGTH = -9,\n    KM_ERROR_UNSUPPORTED_PADDING_MODE = -10,\n    KM_ERROR_INCOMPATIBLE_PADDING_MODE = -11,\n    KM_ERROR_UNSUPPORTED_DIGEST = -12,\n    KM_ERROR_INCOMPATIBLE_DIGEST = -13,\n    KM_ERROR_INVALID_EXPIRATION_TIME = -14,\n    KM_ERROR_INVALID_USER_ID = -15,\n    KM_ERROR_INVALID_AUTHORIZATION_TIMEOUT = -16,\n    KM_ERROR_UNSUPPORTED_KEY_FORMAT = -17,\n    KM_ERROR_INCOMPATIBLE_KEY_FORMAT = -18,\n    KM_ERROR_UNSUPPORTED_KEY_ENCRYPTION_ALGORITHM = -19,   /* For PKCS8 & PKCS12 */\n    KM_ERROR_UNSUPPORTED_KEY_VERIFICATION_ALGORITHM = -20, /* For PKCS8 & PKCS12 */\n    KM_ERROR_INVALID_INPUT_LENGTH = -21,\n    KM_ERROR_KEY_EXPORT_OPTIONS_INVALID = -22,\n    KM_ERROR_DELEGATION_NOT_ALLOWED = -23,\n    KM_ERROR_KEY_NOT_YET_VALID = -24,\n    KM_ERROR_KEY_EXPIRED = -25,\n    KM_ERROR_KEY_USER_NOT_AUTHENTICATED = -26,\n    KM_ERROR_OUTPUT_PARAMETER_NULL = -27,\n    KM_ERROR_INVALID_OPERATION_HANDLE = -28,\n    KM_ERROR_INSUFFICIENT_BUFFER_SPACE = -29,\n    KM_ERROR_VERIFICATION_FAILED = -30,\n    KM_ERROR_TOO_MANY_OPERATIONS = -31,\n    KM_ERROR_UNEXPECTED_NULL_POINTER = -32,\n    KM_ERROR_INVALID_KEY_BLOB = -33,\n    KM_ERROR_IMPORTED_KEY_NOT_ENCRYPTED = -34,\n    KM_ERROR_IMPORTED_KEY_DECRYPTION_FAILED = -35,\n    KM_ERROR_IMPORTED_KEY_NOT_SIGNED = -36,\n    KM_ERROR_IMPORTED_KEY_VERIFICATION_FAILED = -37,\n    KM_ERROR_INVALID_ARGUMENT = -38,\n    KM_ERROR_UNSUPPORTED_TAG = -39,\n    KM_ERROR_INVALID_TAG = -40,\n    KM_ERROR_MEMORY_ALLOCATION_FAILED = -41,\n    KM_ERROR_IMPORT_PARAMETER_MISMATCH = -44,\n    KM_ERROR_SECURE_HW_ACCESS_DENIED = -45,\n    KM_ERROR_OPERATION_CANCELLED = -46,\n    KM_ERROR_CONCURRENT_ACCESS_CONFLICT = -47,\n    KM_ERROR_SECURE_HW_BUSY = -48,\n    KM_ERROR_SECURE_HW_COMMUNICATION_FAILED = -49,\n    KM_ERROR_UNSUPPORTED_EC_FIELD = -50,\n    KM_ERROR_MISSING_NONCE = -51,\n    KM_ERROR_INVALID_NONCE = -52,\n    KM_ERROR_MISSING_MAC_LENGTH = -53,\n    KM_ERROR_KEY_RATE_LIMIT_EXCEEDED = -54,\n    KM_ERROR_CALLER_NONCE_PROHIBITED = -55,\n    KM_ERROR_KEY_MAX_OPS_EXCEEDED = -56,\n    KM_ERROR_INVALID_MAC_LENGTH = -57,\n    KM_ERROR_MISSING_MIN_MAC_LENGTH = -58,\n    KM_ERROR_UNSUPPORTED_MIN_MAC_LENGTH = -59,\n\n    KM_ERROR_UNIMPLEMENTED = -100,\n    KM_ERROR_VERSION_MISMATCH = -101,\n\n    /* Additional error codes may be added by implementations, but implementers should coordinate\n     * with Google to avoid code collision. */\n    KM_ERROR_UNKNOWN_ERROR = -1000,\n} keymaster_error_t;\n\n/* Convenience functions for manipulating keymaster tag types */\n\nstatic inline keymaster_tag_type_t keymaster_tag_get_type(keymaster_tag_t tag) {\n    return (keymaster_tag_type_t)(tag & (0xF << 28));\n}\n\nstatic inline uint32_t keymaster_tag_mask_type(keymaster_tag_t tag) {\n    return tag & 0x0FFFFFFF;\n}\n\nstatic inline bool keymaster_tag_type_repeatable(keymaster_tag_type_t type) {\n    switch (type) {\n    case KM_UINT_REP:\n    case KM_ENUM_REP:\n        return true;\n    default:\n        return false;\n    }\n}\n\nstatic inline bool keymaster_tag_repeatable(keymaster_tag_t tag) {\n    return keymaster_tag_type_repeatable(keymaster_tag_get_type(tag));\n}\n\n/* Convenience functions for manipulating keymaster_key_param_t structs */\n\ninline keymaster_key_param_t keymaster_param_enum(keymaster_tag_t tag, uint32_t value) {\n    // assert(keymaster_tag_get_type(tag) == KM_ENUM || keymaster_tag_get_type(tag) == KM_ENUM_REP);\n    keymaster_key_param_t param;\n    memset(&param, 0, sizeof(param));\n    param.tag = tag;\n    param.enumerated = value;\n    return param;\n}\n\ninline keymaster_key_param_t keymaster_param_int(keymaster_tag_t tag, uint32_t value) {\n    // assert(keymaster_tag_get_type(tag) == KM_INT || keymaster_tag_get_type(tag) == KM_INT_REP);\n    keymaster_key_param_t param;\n    memset(&param, 0, sizeof(param));\n    param.tag = tag;\n    param.integer = value;\n    return param;\n}\n\ninline keymaster_key_param_t keymaster_param_long(keymaster_tag_t tag, uint64_t value) {\n    // assert(keymaster_tag_get_type(tag) == KM_LONG);\n    keymaster_key_param_t param;\n    memset(&param, 0, sizeof(param));\n    param.tag = tag;\n    param.long_integer = value;\n    return param;\n}\n\ninline keymaster_key_param_t keymaster_param_blob(keymaster_tag_t tag, const uint8_t* bytes,\n                                                  size_t bytes_len) {\n    // assert(keymaster_tag_get_type(tag) == KM_BYTES || keymaster_tag_get_type(tag) == KM_BIGNUM);\n    keymaster_key_param_t param;\n    memset(&param, 0, sizeof(param));\n    param.tag = tag;\n    param.blob.data = (uint8_t*)bytes;\n    param.blob.data_length = bytes_len;\n    return param;\n}\n\ninline keymaster_key_param_t keymaster_param_bool(keymaster_tag_t tag) {\n    // assert(keymaster_tag_get_type(tag) == KM_BOOL);\n    keymaster_key_param_t param;\n    memset(&param, 0, sizeof(param));\n    param.tag = tag;\n    param.boolean = true;\n    return param;\n}\n\ninline keymaster_key_param_t keymaster_param_date(keymaster_tag_t tag, uint64_t value) {\n    // assert(keymaster_tag_get_type(tag) == KM_DATE);\n    keymaster_key_param_t param;\n    memset(&param, 0, sizeof(param));\n    param.tag = tag;\n    param.date_time = value;\n    return param;\n}\n\n#define KEYMASTER_SIMPLE_COMPARE(a, b) (a < b) ? -1 : ((a > b) ? 1 : 0)\ninline int keymaster_param_compare(const keymaster_key_param_t* a, const keymaster_key_param_t* b) {\n    int retval = KEYMASTER_SIMPLE_COMPARE(a->tag, b->tag);\n    if (retval != 0)\n        return retval;\n\n    switch (keymaster_tag_get_type(a->tag)) {\n    case KM_INVALID:\n    case KM_BOOL:\n        return 0;\n    case KM_ENUM:\n    case KM_ENUM_REP:\n        return KEYMASTER_SIMPLE_COMPARE(a->enumerated, b->enumerated);\n    case KM_UINT:\n    case KM_UINT_REP:\n        return KEYMASTER_SIMPLE_COMPARE(a->integer, b->integer);\n    case KM_ULONG:\n    case KM_ULONG_REP:\n        return KEYMASTER_SIMPLE_COMPARE(a->long_integer, b->long_integer);\n    case KM_DATE:\n        return KEYMASTER_SIMPLE_COMPARE(a->date_time, b->date_time);\n    case KM_BIGNUM:\n    case KM_BYTES:\n        // Handle the empty cases.\n        if (a->blob.data_length != 0 && b->blob.data_length == 0)\n            return -1;\n        if (a->blob.data_length == 0 && b->blob.data_length == 0)\n            return 0;\n        if (a->blob.data_length == 0 && b->blob.data_length > 0)\n            return 1;\n\n        retval = memcmp(a->blob.data, b->blob.data, a->blob.data_length < b->blob.data_length\n                                                        ? a->blob.data_length\n                                                        : b->blob.data_length);\n        if (retval != 0)\n            return retval;\n        else if (a->blob.data_length != b->blob.data_length) {\n            // Equal up to the common length; longer one is larger.\n            if (a->blob.data_length < b->blob.data_length)\n                return -1;\n            if (a->blob.data_length > b->blob.data_length)\n                return 1;\n        };\n    }\n\n    return 0;\n}\n#undef KEYMASTER_SIMPLE_COMPARE\n\ninline void keymaster_free_param_values(keymaster_key_param_t* param, size_t param_count) {\n    while (param_count-- > 0) {\n        switch (keymaster_tag_get_type(param->tag)) {\n        case KM_BIGNUM:\n        case KM_BYTES:\n            free((void*)param->blob.data);\n            param->blob.data = NULL;\n            break;\n        default:\n            // NOP\n            break;\n        }\n        ++param;\n    }\n}\n\ninline void keymaster_free_param_set(keymaster_key_param_set_t* set) {\n    if (set) {\n        keymaster_free_param_values(set->params, set->length);\n        free(set->params);\n        set->params = NULL;\n    }\n}\n\ninline void keymaster_free_characteristics(keymaster_key_characteristics_t* characteristics) {\n    if (characteristics) {\n        keymaster_free_param_set(&characteristics->hw_enforced);\n        keymaster_free_param_set(&characteristics->sw_enforced);\n    }\n}\n\n#ifdef __cplusplus\n}  // extern \"C\"\n#endif  // __cplusplus\n\n#endif  // ANDROID_HARDWARE_KEYMASTER_DEFS_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/lights.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_LIGHTS_INTERFACE_H\n#define ANDROID_LIGHTS_INTERFACE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define LIGHTS_HARDWARE_MODULE_ID \"lights\"\n\n/*\n * These light IDs correspond to logical lights, not physical.\n * So for example, if your INDICATOR light is in line with your\n * BUTTONS, it might make sense to also light the INDICATOR\n * light to a reasonable color when the BUTTONS are lit.\n */\n#define LIGHT_ID_BACKLIGHT          \"backlight\"\n#define LIGHT_ID_KEYBOARD           \"keyboard\"\n#define LIGHT_ID_BUTTONS            \"buttons\"\n#define LIGHT_ID_BATTERY            \"battery\"\n#define LIGHT_ID_NOTIFICATIONS      \"notifications\"\n#define LIGHT_ID_ATTENTION          \"attention\"\n\n/*\n * These lights aren't currently supported by the higher\n * layers, but could be someday, so we have the constants\n * here now.\n */\n#define LIGHT_ID_BLUETOOTH          \"bluetooth\"\n#define LIGHT_ID_WIFI               \"wifi\"\n\n/*\n * Additional hardware-specific lights\n */\n#define LIGHT_ID_CAPS               \"caps\"\n#define LIGHT_ID_FUNC               \"func\"\n\n/* ************************************************************************\n * Flash modes for the flashMode field of light_state_t.\n */\n\n#define LIGHT_FLASH_NONE            0\n\n/**\n * To flash the light at a given rate, set flashMode to LIGHT_FLASH_TIMED,\n * and then flashOnMS should be set to the number of milliseconds to turn\n * the light on, followed by the number of milliseconds to turn the light\n * off.\n */\n#define LIGHT_FLASH_TIMED           1\n\n/**\n * To flash the light using hardware assist, set flashMode to\n * the hardware mode.\n */\n#define LIGHT_FLASH_HARDWARE        2\n\n/**\n * Light brightness is managed by a user setting.\n */\n#define BRIGHTNESS_MODE_USER        0\n\n/**\n * Light brightness is managed by a light sensor.\n */\n#define BRIGHTNESS_MODE_SENSOR      1\n\n/**\n * Light mode allows multiple LEDs\n */\n#define LIGHT_MODE_MULTIPLE_LEDS    0x01\n\n/**\n * The parameters that can be set for a given light.\n *\n * Not all lights must support all parameters.  If you\n * can do something backward-compatible, you should.\n */\nstruct light_state_t {\n    /**\n     * The color of the LED in ARGB.\n     *\n     * Do your best here.\n     *   - If your light can only do red or green, if they ask for blue,\n     *     you should do green.\n     *   - If you can only do a brightness ramp, then use this formula:\n     *      unsigned char brightness = ((77*((color>>16)&0x00ff))\n     *              + (150*((color>>8)&0x00ff)) + (29*(color&0x00ff))) >> 8;\n     *   - If you can only do on or off, 0 is off, anything else is on.\n     *\n     * The high byte should be ignored.  Callers will set it to 0xff (which\n     * would correspond to 255 alpha).\n     *\n     * CyanogenMod: The high byte value can be implemented to control the LEDs\n     * Brightness from the Lights settings. The value goes from 0x01 to 0xFF.\n     */\n    unsigned int color;\n\n    /**\n     * See the LIGHT_FLASH_* constants\n     */\n    int flashMode;\n    int flashOnMS;\n    int flashOffMS;\n\n    /**\n     * Policy used by the framework to manage the light's brightness.\n     * Currently the values are BRIGHTNESS_MODE_USER and BRIGHTNESS_MODE_SENSOR.\n     */\n    int brightnessMode;\n\n    /**\n     * Define the LEDs modes (multiple, ...).\n     * See the LIGHTS_MODE_* mask constants.\n     */\n    unsigned int ledsModes;\n};\n\nstruct light_device_t {\n    struct hw_device_t common;\n\n    /**\n     * Set the provided lights to the provided values.\n     *\n     * Returns: 0 on succes, error code on failure.\n     */\n    int (*set_light)(struct light_device_t* dev,\n            struct light_state_t const* state);\n};\n\n\n__END_DECLS\n\n#endif  // ANDROID_LIGHTS_INTERFACE_H\n\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/local_time_hal.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#ifndef ANDROID_LOCAL_TIME_HAL_INTERFACE_H\n#define ANDROID_LOCAL_TIME_HAL_INTERFACE_H\n\n#include <stdint.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define LOCAL_TIME_HARDWARE_MODULE_ID \"local_time\"\n\n/**\n * Name of the local time devices to open\n */\n#define LOCAL_TIME_HARDWARE_INTERFACE \"local_time_hw_if\"\n\n/**********************************************************************/\n\n/**\n * A structure used to collect low level sync data in a lab environment.  Most\n * HAL implementations will never need this structure.\n */\nstruct local_time_debug_event {\n    int64_t local_timesync_event_id;\n    int64_t local_time;\n};\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\nstruct local_time_module {\n    struct hw_module_t common;\n};\n\nstruct local_time_hw_device {\n    /**\n     * Common methods of the local time hardware device.  This *must* be the first member of\n     * local_time_hw_device as users of this structure will cast a hw_device_t to\n     * local_time_hw_device pointer in contexts where it's known the hw_device_t references a\n     * local_time_hw_device.\n     */\n    struct hw_device_t common;\n\n    /**\n     *\n     * Returns the current value of the system wide local time counter\n     */\n    int64_t (*get_local_time)(struct local_time_hw_device* dev);\n\n    /**\n     *\n     * Returns the nominal frequency (in hertz) of the system wide local time\n     * counter\n     */\n    uint64_t (*get_local_freq)(struct local_time_hw_device* dev);\n\n    /**\n     *\n     * Sets the HW slew rate of oscillator which drives the system wide local\n     * time counter.  On success, platforms should return 0.  Platforms which\n     * do not support HW slew should leave this method set to NULL.\n     *\n     * Valid values for rate range from MIN_INT16 to MAX_INT16.  Platform\n     * implementations should attempt map this range linearly to the min/max\n     * slew rate of their hardware.\n     */\n    int (*set_local_slew)(struct local_time_hw_device* dev, int16_t rate);\n\n    /**\n     *\n     * A method used to collect low level sync data in a lab environments.\n     * Most HAL implementations will simply set this member to NULL, or return\n     * -EINVAL to indicate that this functionality is not supported.\n     * Production HALs should never support this method.\n     */\n    int (*get_debug_log)(struct local_time_hw_device* dev,\n                         struct local_time_debug_event* records,\n                         int max_records);\n};\n\ntypedef struct local_time_hw_device local_time_hw_device_t;\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int local_time_hw_device_open(\n        const struct hw_module_t* module,\n        struct local_time_hw_device** device)\n{\n    return module->methods->open(module, LOCAL_TIME_HARDWARE_INTERFACE,\n                                 (struct hw_device_t**)device);\n}\n\nstatic inline int local_time_hw_device_close(struct local_time_hw_device* device)\n{\n    return device->common.close(&device->common);\n}\n\n\n__END_DECLS\n\n#endif  // ANDROID_LOCAL_TIME_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/memtrack.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_MEMTRACK_H\n#define ANDROID_INCLUDE_HARDWARE_MEMTRACK_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define MEMTRACK_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n\n/**\n * The id of this module\n */\n#define MEMTRACK_HARDWARE_MODULE_ID \"memtrack\"\n\n/*\n * The Memory Tracker HAL is designed to return information about device-specific\n * memory usage.  The primary goal is to be able to track memory that is not\n * trackable in any other way, for example texture memory that is allocated by\n * a process, but not mapped in to that process' address space.\n * A secondary goal is to be able to categorize memory used by a process into\n * GL, graphics, etc.  All memory sizes should be in real memory usage,\n * accounting for stride, bit depth, rounding up to page size, etc.\n *\n * A process collecting memory statistics will call getMemory for each\n * combination of pid and memory type.  For each memory type that it recognizes\n * the HAL should fill out an array of memtrack_record structures breaking\n * down the statistics of that memory type as much as possible.  For example,\n * getMemory(<pid>, MEMTRACK_TYPE_GL) might return:\n * { { 4096,  ACCOUNTED | PRIVATE | SYSTEM },\n *   { 40960, UNACCOUNTED | PRIVATE | SYSTEM },\n *   { 8192,  ACCOUNTED | PRIVATE | DEDICATED },\n *   { 8192,  UNACCOUNTED | PRIVATE | DEDICATED } }\n * If the HAL could not differentiate between SYSTEM and DEDICATED memory, it\n * could return:\n * { { 12288,  ACCOUNTED | PRIVATE },\n *   { 49152,  UNACCOUNTED | PRIVATE } }\n *\n * Memory should not overlap between types.  For example, a graphics buffer\n * that has been mapped into the GPU as a surface should show up when\n * MEMTRACK_TYPE_GRAPHICS is requested, and not when MEMTRACK_TYPE_GL\n * is requested.\n */\n\nenum memtrack_type {\n    MEMTRACK_TYPE_OTHER = 0,\n    MEMTRACK_TYPE_GL = 1,\n    MEMTRACK_TYPE_GRAPHICS = 2,\n    MEMTRACK_TYPE_MULTIMEDIA = 3,\n    MEMTRACK_TYPE_CAMERA = 4,\n    MEMTRACK_NUM_TYPES,\n};\n\nstruct memtrack_record {\n    size_t size_in_bytes;\n    unsigned int flags;\n};\n\n/**\n * Flags to differentiate memory that can already be accounted for in\n * /proc/<pid>/smaps,\n * (Shared_Clean + Shared_Dirty + Private_Clean + Private_Dirty = Size).\n * In general, memory mapped in to a userspace process is accounted unless\n * it was mapped with remap_pfn_range.\n * Exactly one of these should be set.\n */\n#define MEMTRACK_FLAG_SMAPS_ACCOUNTED   (1 << 1)\n#define MEMTRACK_FLAG_SMAPS_UNACCOUNTED (1 << 2)\n\n/**\n * Flags to differentiate memory shared across multiple processes vs. memory\n * used by a single process.  Only zero or one of these may be set in a record.\n * If none are set, record is assumed to count shared + private memory.\n */\n#define MEMTRACK_FLAG_SHARED      (1 << 3)\n#define MEMTRACK_FLAG_SHARED_PSS  (1 << 4) /* shared / num_procesess */\n#define MEMTRACK_FLAG_PRIVATE     (1 << 5)\n\n/**\n * Flags to differentiate memory taken from the kernel's allocation pool vs.\n * memory that is dedicated to non-kernel allocations, for example a carveout\n * or separate video memory.  Only zero or one of these may be set in a record.\n * If none are set, record is assumed to count system + dedicated memory.\n */\n#define MEMTRACK_FLAG_SYSTEM     (1 << 6)\n#define MEMTRACK_FLAG_DEDICATED  (1 << 7)\n\n/**\n * Flags to differentiate memory accessible by the CPU in non-secure mode vs.\n * memory that is protected.  Only zero or one of these may be set in a record.\n * If none are set, record is assumed to count secure + nonsecure memory.\n */\n#define MEMTRACK_FLAG_NONSECURE  (1 << 8)\n#define MEMTRACK_FLAG_SECURE     (1 << 9)\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\ntypedef struct memtrack_module {\n    struct hw_module_t common;\n\n    /**\n     * (*init)() performs memtrack management setup actions and is called\n     * once before any calls to getMemory().\n     * Returns 0 on success, -errno on error.\n     */\n    int (*init)(const struct memtrack_module *module);\n\n    /**\n     * (*getMemory)() expects an array of record objects and populates up to\n     * *num_record structures with the sizes of memory plus associated flags for\n     * that memory.  It also updates *num_records with the total number of\n     * records it could return if *num_records was large enough when passed in.\n     * Returning records with size 0 is expected, the number of records should\n     * not vary between calls to getMemory for the same memory type, even\n     * for different pids.\n     *\n     * The caller will often call getMemory for a type and pid with\n     * *num_records == 0 to determine how many records to allocate room for,\n     * this case should be a fast-path in the HAL, returning a constant and\n     * not querying any kernel files.  If *num_records passed in is 0,\n     * then records may be NULL.\n     *\n     * This function must be thread-safe, it may get called from multiple\n     * threads at the same time.\n     *\n     * Returns 0 on success, -ENODEV if the type is not supported, -errno\n     * on other errors.\n     */\n    int (*getMemory)(const struct memtrack_module *module,\n                     pid_t pid,\n                     int type,\n                     struct memtrack_record *records,\n                     size_t *num_records);\n} memtrack_module_t;\n\n__END_DECLS\n\n#endif  // ANDROID_INCLUDE_HARDWARE_MEMTRACK_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/nfc.h",
    "content": "/*\n * Copyright (C) 2011, 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_NFC_HAL_INTERFACE_H\n#define ANDROID_NFC_HAL_INTERFACE_H\n\n#include <stdint.h>\n#include <strings.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n\n/* NFC device HAL for NCI-based NFC controllers.\n *\n * This HAL allows NCI silicon vendors to make use\n * of the core NCI stack in Android for their own silicon.\n *\n * The responibilities of the NCI HAL implementation\n * are as follows:\n *\n * - Implement the transport to the NFC controller\n * - Implement each of the HAL methods specified below as applicable to their silicon\n * - Pass up received NCI messages from the controller to the stack\n *\n * A simplified timeline of NCI HAL method calls:\n * 1) Core NCI stack calls open()\n * 2) Core NCI stack executes CORE_RESET and CORE_INIT through calls to write()\n * 3) Core NCI stack calls core_initialized() to allow HAL to do post-init configuration\n * 4) Core NCI stack calls pre_discover() to allow HAL to prepare for RF discovery\n * 5) Core NCI stack starts discovery through calls to write()\n * 6) Core NCI stack stops discovery through calls to write() (e.g. screen turns off)\n * 7) Core NCI stack calls pre_discover() to prepare for RF discovery (e.g. screen turned back on)\n * 8) Core NCI stack starts discovery through calls to write()\n * ...\n * ...\n * 9) Core NCI stack calls close()\n */\n#define NFC_NCI_HARDWARE_MODULE_ID \"nfc_nci\"\n#define NFC_NCI_BCM2079X_HARDWARE_MODULE_ID \"nfc_nci.bcm2079x\"\n#define NFC_NCI_NXP_PN54X_HARDWARE_MODULE_ID \"nfc_nci.pn54x\"\n#define NFC_NCI_CONTROLLER \"nci\"\n\n/*\n *  nfc_nci_module_t should contain module-specific parameters\n */\ntypedef struct nfc_nci_module_t {\n    /**\n     * Common methods of the NFC NCI module.  This *must* be the first member of\n     * nfc_nci_module_t as users of this structure will cast a hw_module_t to\n     * nfc_nci_module_t pointer in contexts where it's known the hw_module_t references a\n     * nfc_nci_module_t.\n     */\n    struct hw_module_t common;\n} nfc_nci_module_t;\n\n/*\n * HAL events that can be passed back to the stack\n */\ntypedef uint8_t nfc_event_t;\n\nenum {\n    HAL_NFC_OPEN_CPLT_EVT           = 0x00,\n    HAL_NFC_CLOSE_CPLT_EVT          = 0x01,\n    HAL_NFC_POST_INIT_CPLT_EVT      = 0x02,\n    HAL_NFC_PRE_DISCOVER_CPLT_EVT   = 0x03,\n    HAL_NFC_REQUEST_CONTROL_EVT     = 0x04,\n    HAL_NFC_RELEASE_CONTROL_EVT     = 0x05,\n    HAL_NFC_ERROR_EVT               = 0x06\n};\n\n/*\n * Allowed status return values for each of the HAL methods\n */\ntypedef uint8_t nfc_status_t;\n\nenum {\n    HAL_NFC_STATUS_OK               = 0x00,\n    HAL_NFC_STATUS_FAILED           = 0x01,\n    HAL_NFC_STATUS_ERR_TRANSPORT    = 0x02,\n    HAL_NFC_STATUS_ERR_CMD_TIMEOUT  = 0x03,\n    HAL_NFC_STATUS_REFUSED          = 0x04\n};\n\n/*\n * The callback passed in from the NFC stack that the HAL\n * can use to pass events back to the stack.\n */\ntypedef void (nfc_stack_callback_t) (nfc_event_t event, nfc_status_t event_status);\n\n/*\n * The callback passed in from the NFC stack that the HAL\n * can use to pass incomming data to the stack.\n */\ntypedef void (nfc_stack_data_callback_t) (uint16_t data_len, uint8_t* p_data);\n\n/* nfc_nci_device_t starts with a hw_device_t struct,\n * followed by device-specific methods and members.\n *\n * All methods in the NCI HAL are asynchronous.\n */\ntypedef struct nfc_nci_device {\n    /**\n     * Common methods of the NFC NCI device.  This *must* be the first member of\n     * nfc_nci_device_t as users of this structure will cast a hw_device_t to\n     * nfc_nci_device_t pointer in contexts where it's known the hw_device_t references a\n     * nfc_nci_device_t.\n     */\n    struct hw_device_t common;\n    /*\n     * (*open)() Opens the NFC controller device and performs initialization.\n     * This may include patch download and other vendor-specific initialization.\n     *\n     * If open completes successfully, the controller should be ready to perform\n     * NCI initialization - ie accept CORE_RESET and subsequent commands through\n     * the write() call.\n     *\n     * If open() returns 0, the NCI stack will wait for a HAL_NFC_OPEN_CPLT_EVT\n     * before continuing.\n     *\n     * If open() returns any other value, the NCI stack will stop.\n     *\n     */\n    int (*open)(const struct nfc_nci_device *p_dev, nfc_stack_callback_t *p_cback,\n            nfc_stack_data_callback_t *p_data_cback);\n\n    /*\n     * (*write)() Performs an NCI write.\n     *\n     * This method may queue writes and return immediately. The only\n     * requirement is that the writes are executed in order.\n     */\n    int (*write)(const struct nfc_nci_device *p_dev, uint16_t data_len, const uint8_t *p_data);\n\n    /*\n     * (*core_initialized)() is called after the CORE_INIT_RSP is received from the NFCC.\n     * At this time, the HAL can do any chip-specific configuration.\n     *\n     * If core_initialized() returns 0, the NCI stack will wait for a HAL_NFC_POST_INIT_CPLT_EVT\n     * before continuing.\n     *\n     * If core_initialized() returns any other value, the NCI stack will continue\n     * immediately.\n     */\n    int (*core_initialized)(const struct nfc_nci_device *p_dev, uint8_t* p_core_init_rsp_params);\n\n    /*\n     * (*pre_discover)() Is called every time before starting RF discovery.\n     * It is a good place to do vendor-specific configuration that must be\n     * performed every time RF discovery is about to be started.\n     *\n     * If pre_discover() returns 0, the NCI stack will wait for a HAL_NFC_PRE_DISCOVER_CPLT_EVT\n     * before continuing.\n     *\n     * If pre_discover() returns any other value, the NCI stack will start\n     * RF discovery immediately.\n     */\n    int (*pre_discover)(const struct nfc_nci_device *p_dev);\n\n    /*\n     * (*close)() Closed the NFC controller. Should free all resources.\n     */\n    int (*close)(const struct nfc_nci_device *p_dev);\n\n    /*\n     * (*control_granted)() Grant HAL the exclusive control to send NCI commands.\n     * Called in response to HAL_REQUEST_CONTROL_EVT.\n     * Must only be called when there are no NCI commands pending.\n     * HAL_RELEASE_CONTROL_EVT will notify when HAL no longer needs exclusive control.\n     */\n    int (*control_granted)(const struct nfc_nci_device *p_dev);\n\n    /*\n     * (*power_cycle)() Restart controller by power cyle;\n     * HAL_OPEN_CPLT_EVT will notify when operation is complete.\n     */\n    int (*power_cycle)(const struct nfc_nci_device *p_dev);\n} nfc_nci_device_t;\n\n/*\n * Convenience methods that the NFC stack can use to open\n * and close an NCI device\n */\nstatic inline int nfc_nci_open(const struct hw_module_t* module,\n        nfc_nci_device_t** dev) {\n    return module->methods->open(module, NFC_NCI_CONTROLLER,\n        (struct hw_device_t**) dev);\n}\n\nstatic inline int nfc_nci_close(nfc_nci_device_t* dev) {\n    return dev->common.close(&dev->common);\n}\n/*\n * End NFC NCI HAL\n */\n\n/*\n * This is a limited NFC HAL for NXP PN544-based devices.\n * This HAL as Android is moving to\n * an NCI-based NFC stack.\n *\n * All NCI-based NFC controllers should use the NFC-NCI\n * HAL instead.\n * Begin PN544 specific HAL\n */\n#define NFC_HARDWARE_MODULE_ID \"nfc\"\n\n#define NFC_PN544_CONTROLLER \"pn544\"\n\ntypedef struct nfc_module_t {\n    /**\n     * Common methods of the NFC NXP PN544 module.  This *must* be the first member of\n     * nfc_module_t as users of this structure will cast a hw_module_t to\n     * nfc_module_t pointer in contexts where it's known the hw_module_t references a\n     * nfc_module_t.\n     */\n    struct hw_module_t common;\n} nfc_module_t;\n\n/*\n * PN544 linktypes.\n * UART\n * I2C\n * USB (uses UART DAL)\n */\ntypedef enum {\n    PN544_LINK_TYPE_UART,\n    PN544_LINK_TYPE_I2C,\n    PN544_LINK_TYPE_USB,\n    PN544_LINK_TYPE_INVALID,\n} nfc_pn544_linktype;\n\ntypedef struct {\n    /**\n     * Common methods of the NFC NXP PN544 device.  This *must* be the first member of\n     * nfc_pn544_device_t as users of this structure will cast a hw_device_t to\n     * nfc_pn544_device_t pointer in contexts where it's known the hw_device_t references a\n     * nfc_pn544_device_t.\n     */\n    struct hw_device_t common;\n\n    /* The number of EEPROM registers to write */\n    uint32_t num_eeprom_settings;\n\n    /* The actual EEPROM settings\n     * For PN544, each EEPROM setting is a 4-byte entry,\n     * of the format [0x00, addr_msb, addr_lsb, value].\n     */\n    uint8_t* eeprom_settings;\n\n    /* The link type to which the PN544 is connected */\n    nfc_pn544_linktype linktype;\n\n    /* The device node to which the PN544 is connected */\n    const char* device_node;\n\n    /* On Crespo we had an I2C issue that would cause us to sometimes read\n     * the I2C slave address (0x57) over the bus. libnfc contains\n     * a hack to ignore this byte and try to read the length byte\n     * again.\n     * Set to 0 to disable the workaround, 1 to enable it.\n     */\n    uint8_t enable_i2c_workaround;\n    /* I2C slave address. Multiple I2C addresses are\n     * possible for PN544 module. Configure address according to\n     * board design.\n     */\n    uint8_t i2c_device_address;\n} nfc_pn544_device_t;\n\nstatic inline int nfc_pn544_open(const struct hw_module_t* module,\n        nfc_pn544_device_t** dev) {\n    return module->methods->open(module, NFC_PN544_CONTROLLER,\n        (struct hw_device_t**) dev);\n}\n\nstatic inline int nfc_pn544_close(nfc_pn544_device_t* dev) {\n    return dev->common.close(&dev->common);\n}\n/*\n * End PN544 specific HAL\n */\n\n__END_DECLS\n\n#endif // ANDROID_NFC_HAL_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/nfc_tag.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_NFC_TAG_HAL_INTERFACE_H\n#define ANDROID_NFC_TAG_HAL_INTERFACE_H\n\n#include <stdint.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n/*\n * HAL for programmable NFC tags.\n *\n */\n\n#define NFC_TAG_HARDWARE_MODULE_ID \"nfc_tag\"\n#define NFC_TAG_ID \"tag\"\n\ntypedef struct nfc_tag_module_t {\n    /**\n     * Common methods of the NFC tag module.  This *must* be the first member of\n     * nfc_tag_module_t as users of this structure will cast a hw_module_t to\n     * nfc_tag_module_t pointer in contexts where it's known the hw_module_t references a\n     * nfc_tag_module_t.\n     */\n    struct hw_module_t common;\n} nfc_tag_module_t;\n\ntypedef struct nfc_tag_device {\n    /**\n     * Common methods of the NFC tag device.  This *must* be the first member of\n     * nfc_tag_device_t as users of this structure will cast a hw_device_t to\n     * nfc_tag_device_t pointer in contexts where it's known the hw_device_t references a\n     * nfc_tag_device_t.\n     */\n    struct hw_device_t common;\n\n    /**\n     * Initialize the NFC tag.\n     *\n     * The driver must:\n     *   * Set the static lock bytes to read only\n     *   * Configure the Capability Container to disable write acess\n     *         eg: 0xE1 0x10 <size> 0x0F\n     *\n     * This function is called once before any calls to setContent().\n     *\n     * Return 0 on success or -errno on error.\n     */\n    int (*init)(const struct nfc_tag_device *dev);\n\n    /**\n     * Set the NFC tag content.\n     *\n     * The driver must write <data> in the data area of the tag starting at\n     * byte 0 of block 4 and zero the rest of the data area.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int (*setContent)(const struct nfc_tag_device *dev, const uint8_t *data, size_t len);\n\n    /**\n     * Returns the memory size of the data area.\n     */\n    int (*getMemorySize)(const struct nfc_tag_device *dev);\n} nfc_tag_device_t;\n\nstatic inline int nfc_tag_open(const struct hw_module_t* module,\n                               nfc_tag_device_t** dev) {\n    return module->methods->open(module, NFC_TAG_ID,\n                                 (struct hw_device_t**)dev);\n}\n\nstatic inline int nfc_tag_close(nfc_tag_device_t* dev) {\n    return dev->common.close(&dev->common);\n}\n\n__END_DECLS\n\n#endif // ANDROID_NFC_TAG_HAL_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/power.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_POWER_H\n#define ANDROID_INCLUDE_HARDWARE_POWER_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define POWER_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n#define POWER_MODULE_API_VERSION_0_2  HARDWARE_MODULE_API_VERSION(0, 2)\n#define POWER_MODULE_API_VERSION_0_3  HARDWARE_MODULE_API_VERSION(0, 3)\n\n/**\n * The id of this module\n */\n#define POWER_HARDWARE_MODULE_ID \"power\"\n\n/*\n * Power hint identifiers passed to (*powerHint)\n */\n\ntypedef enum {\n    POWER_HINT_VSYNC = 0x00000001,\n    POWER_HINT_INTERACTION = 0x00000002,\n    /* DO NOT USE POWER_HINT_VIDEO_ENCODE/_DECODE!  They will be removed in\n     * KLP.\n     */\n    POWER_HINT_VIDEO_ENCODE = 0x00000003,\n    POWER_HINT_VIDEO_DECODE = 0x00000004,\n    POWER_HINT_LOW_POWER = 0x00000005,\n    POWER_HINT_CAM_PREVIEW = 0x00000006,\n\n    POWER_HINT_CPU_BOOST    = 0x00000010,\n    POWER_HINT_LAUNCH_BOOST = 0x00000011,\n    POWER_HINT_AUDIO        = 0x00000020,\n    POWER_HINT_SET_PROFILE  = 0x00000030\n\n} power_hint_t;\n\ntypedef enum {\n    POWER_FEATURE_DOUBLE_TAP_TO_WAKE = 0x00000001,\n    POWER_FEATURE_SUPPORTED_PROFILES = 0x00001000\n} feature_t;\n\n/**\n * Process info, passed as an opaque handle when\n * using POWER_HINT_LAUNCH_BOOST.\n */\ntypedef struct launch_boost_info {\n    pid_t pid;\n    const char* packageName;\n} launch_boost_info_t;\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\ntypedef struct power_module {\n    struct hw_module_t common;\n\n    /*\n     * (*init)() performs power management setup actions at runtime\n     * startup, such as to set default cpufreq parameters.  This is\n     * called only by the Power HAL instance loaded by\n     * PowerManagerService.\n     */\n    void (*init)(struct power_module *module);\n\n    /*\n     * (*setInteractive)() performs power management actions upon the\n     * system entering interactive state (that is, the system is awake\n     * and ready for interaction, often with UI devices such as\n     * display and touchscreen enabled) or non-interactive state (the\n     * system appears asleep, display usually turned off).  The\n     * non-interactive state is usually entered after a period of\n     * inactivity, in order to conserve battery power during\n     * such inactive periods.\n     *\n     * Typical actions are to turn on or off devices and adjust\n     * cpufreq parameters.  This function may also call the\n     * appropriate interfaces to allow the kernel to suspend the\n     * system to low-power sleep state when entering non-interactive\n     * state, and to disallow low-power suspend when the system is in\n     * interactive state.  When low-power suspend state is allowed, the\n     * kernel may suspend the system whenever no wakelocks are held.\n     *\n     * on is non-zero when the system is transitioning to an\n     * interactive / awake state, and zero when transitioning to a\n     * non-interactive / asleep state.\n     *\n     * This function is called to enter non-interactive state after\n     * turning off the screen (if present), and called to enter\n     * interactive state prior to turning on the screen.\n     */\n    void (*setInteractive)(struct power_module *module, int on);\n\n    /*\n     * (*powerHint) is called to pass hints on power requirements, which\n     * may result in adjustment of power/performance parameters of the\n     * cpufreq governor and other controls.  The possible hints are:\n     *\n     * POWER_HINT_VSYNC\n     *\n     *     Foreground app has started or stopped requesting a VSYNC pulse\n     *     from SurfaceFlinger.  If the app has started requesting VSYNC\n     *     then CPU and GPU load is expected soon, and it may be appropriate\n     *     to raise speeds of CPU, memory bus, etc.  The data parameter is\n     *     non-zero to indicate VSYNC pulse is now requested, or zero for\n     *     VSYNC pulse no longer requested.\n     *\n     * POWER_HINT_INTERACTION\n     *\n     *     User is interacting with the device, for example, touchscreen\n     *     events are incoming.  CPU and GPU load may be expected soon,\n     *     and it may be appropriate to raise speeds of CPU, memory bus,\n     *     etc.  The data parameter is the estimated length of the interaction\n     *     in milliseconds, or 0 if unknown.\n     *\n     * POWER_HINT_LOW_POWER\n     *\n     *     Low power mode is activated or deactivated. Low power mode\n     *     is intended to save battery at the cost of performance. The data\n     *     parameter is non-zero when low power mode is activated, and zero\n     *     when deactivated.\n     *\n     * POWER_HINT_CPU_BOOST\n     *\n     *     An operation is happening where it would be ideal for the CPU to\n     *     be boosted for a specific duration. The data parameter is an\n     *     integer value of the boost duration in microseconds.\n     *\n     * A particular platform may choose to ignore any hint.\n     *\n     * availability: version 0.2\n     *\n     */\n    void (*powerHint)(struct power_module *module, power_hint_t hint,\n                      void *data);\n\n    /*\n     * (*setFeature) is called to turn on or off a particular feature\n     * depending on the state parameter. The possible features are:\n     *\n     * FEATURE_DOUBLE_TAP_TO_WAKE\n     *\n     *    Enabling/Disabling this feature will allow/disallow the system\n     *    to wake up by tapping the screen twice.\n     *\n     * availability: version 0.3\n     *\n     */\n    void (*setFeature)(struct power_module *module, feature_t feature, int state);\n\n    /*\n     * (*getFeature) is called to get the current value of a particular\n     * feature or capability from the hardware or PowerHAL\n     */\n    int (*getFeature)(struct power_module *module, feature_t feature);\n\n} power_module_t;\n\n__END_DECLS\n\n#endif  // ANDROID_INCLUDE_HARDWARE_POWER_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/qemu_pipe.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef ANDROID_INCLUDE_HARDWARE_QEMU_PIPE_H\n#define ANDROID_INCLUDE_HARDWARE_QEMU_PIPE_H\n\n#include <sys/cdefs.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <pthread.h>  /* for pthread_once() */\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <errno.h>\n\n#ifndef D\n#  define  D(...)   do{}while(0)\n#endif\n\n/* Try to open a new Qemu fast-pipe. This function returns a file descriptor\n * that can be used to communicate with a named service managed by the\n * emulator.\n *\n * This file descriptor can be used as a standard pipe/socket descriptor.\n *\n * 'pipeName' is the name of the emulator service you want to connect to.\n * E.g. 'opengles' or 'camera'.\n *\n * On success, return a valid file descriptor\n * Returns -1 on error, and errno gives the error code, e.g.:\n *\n *    EINVAL  -> unknown/unsupported pipeName\n *    ENOSYS  -> fast pipes not available in this system.\n *\n * ENOSYS should never happen, except if you're trying to run within a\n * misconfigured emulator.\n *\n * You should be able to open several pipes to the same pipe service,\n * except for a few special cases (e.g. GSM modem), where EBUSY will be\n * returned if more than one client tries to connect to it.\n */\nstatic __inline__ int\nqemu_pipe_open(const char*  pipeName)\n{\n    char  buff[256];\n    int   buffLen;\n    int   fd, ret;\n\n    if (pipeName == NULL || pipeName[0] == '\\0') {\n        errno = EINVAL;\n        return -1;\n    }\n\n    snprintf(buff, sizeof buff, \"pipe:%s\", pipeName);\n\n    fd = open(\"/dev/qemu_pipe\", O_RDWR);\n    if (fd < 0 && errno == ENOENT)\n        fd = open(\"/dev/goldfish_pipe\", O_RDWR);\n    if (fd < 0) {\n        D(\"%s: Could not open /dev/qemu_pipe: %s\", __FUNCTION__, strerror(errno));\n        //errno = ENOSYS;\n        return -1;\n    }\n\n    buffLen = strlen(buff);\n\n    ret = TEMP_FAILURE_RETRY(write(fd, buff, buffLen+1));\n    if (ret != buffLen+1) {\n        D(\"%s: Could not connect to %s pipe service: %s\", __FUNCTION__, pipeName, strerror(errno));\n        if (ret == 0) {\n            errno = ECONNRESET;\n        } else if (ret > 0) {\n            errno = EINVAL;\n        }\n        return -1;\n    }\n\n    return fd;\n}\n\n#endif /* ANDROID_INCLUDE_HARDWARE_QEMUD_PIPE_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/qemud.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_INCLUDE_HARDWARE_QEMUD_H\n#define ANDROID_INCLUDE_HARDWARE_QEMUD_H\n\n#include <cutils/sockets.h>\n#include \"qemu_pipe.h\"\n\n/* the following is helper code that is used by the QEMU-specific\n * hardware HAL modules to communicate with the emulator program\n * through the 'qemud' multiplexing daemon, or through the qemud\n * pipe.\n *\n * see the documentation comments for details in\n * development/emulator/qemud/qemud.c\n *\n * all definitions here are built into the HAL module to avoid\n * having to write a tiny shared library for this.\n */\n\n/* we expect the D macro to be defined to a function macro\n * that sends its formatted string argument(s) to the log.\n * If not, ignore the traces.\n */\n#ifndef D\n#  define  D(...)  ((void)0)\n#endif\n\nstatic __inline__ int\nqemud_fd_write(int  fd, const void*  buff, int  len)\n{\n    int  len2;\n    do {\n        len2 = write(fd, buff, len);\n    } while (len2 < 0 && errno == EINTR);\n    return len2;\n}\n\nstatic __inline__ int\nqemud_fd_read(int  fd, void*  buff, int  len)\n{\n    int  len2;\n    do {\n        len2 = read(fd, buff, len);\n    } while (len2 < 0 && errno == EINTR);\n    return len2;\n}\n\nstatic __inline__ int\nqemud_channel_open(const char*  name)\n{\n    int  fd;\n    int  namelen = strlen(name);\n    char answer[2];\n    char pipe_name[256];\n\n    /* First, try to connect to the pipe. */\n    snprintf(pipe_name, sizeof(pipe_name), \"qemud:%s\", name);\n    fd = qemu_pipe_open(pipe_name);\n    if (fd < 0) {\n        D(\"QEMUD pipe is not available for %s: %s\", name, strerror(errno));\n        /* If pipe is not available, connect to qemud control socket */\n        fd = socket_local_client( \"qemud\",\n                                  ANDROID_SOCKET_NAMESPACE_RESERVED,\n                                  SOCK_STREAM );\n        if (fd < 0) {\n            D(\"no qemud control socket: %s\", strerror(errno));\n            return -1;\n        }\n\n        /* send service name to connect */\n        if (qemud_fd_write(fd, name, namelen) != namelen) {\n            D(\"can't send service name to qemud: %s\",\n               strerror(errno));\n            close(fd);\n            return -1;\n        }\n\n        /* read answer from daemon */\n        if (qemud_fd_read(fd, answer, 2) != 2 ||\n            answer[0] != 'O' || answer[1] != 'K') {\n            D(\"cant' connect to %s service through qemud\", name);\n            close(fd);\n            return -1;\n        }\n    }\n    return fd;\n}\n\nstatic __inline__ int\nqemud_channel_send(int  fd, const void*  msg, int  msglen)\n{\n    char  header[5];\n\n    if (msglen < 0)\n        msglen = strlen((const char*)msg);\n\n    if (msglen == 0)\n        return 0;\n\n    snprintf(header, sizeof header, \"%04x\", msglen);\n    if (qemud_fd_write(fd, header, 4) != 4) {\n        D(\"can't write qemud frame header: %s\", strerror(errno));\n        return -1;\n    }\n\n    if (qemud_fd_write(fd, msg, msglen) != msglen) {\n        D(\"can4t write qemud frame payload: %s\", strerror(errno));\n        return -1;\n    }\n    return 0;\n}\n\nstatic __inline__ int\nqemud_channel_recv(int  fd, void*  msg, int  msgsize)\n{\n    char  header[5];\n    int   size, avail;\n\n    if (qemud_fd_read(fd, header, 4) != 4) {\n        D(\"can't read qemud frame header: %s\", strerror(errno));\n        return -1;\n    }\n    header[4] = 0;\n    if (sscanf(header, \"%04x\", &size) != 1) {\n        D(\"malformed qemud frame header: '%.*s'\", 4, header);\n        return -1;\n    }\n    if (size > msgsize)\n        return -1;\n\n    if (qemud_fd_read(fd, msg, size) != size) {\n        D(\"can't read qemud frame payload: %s\", strerror(errno));\n        return -1;\n    }\n    return size;\n}\n\n#endif /* ANDROID_INCLUDE_HARDWARE_QEMUD_H */\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/radio.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <system/radio.h>\n#include <hardware/hardware.h>\n\n#ifndef ANDROID_RADIO_HAL_H\n#define ANDROID_RADIO_HAL_H\n\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define RADIO_HARDWARE_MODULE_ID \"radio\"\n\n/**\n * Name of the audio devices to open\n */\n#define RADIO_HARDWARE_DEVICE \"radio_hw_device\"\n\n#define RADIO_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define RADIO_MODULE_API_VERSION_CURRENT RADIO_MODULE_API_VERSION_1_0\n\n\n#define RADIO_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n#define RADIO_DEVICE_API_VERSION_CURRENT RADIO_DEVICE_API_VERSION_1_0\n\n/**\n * List of known radio HAL modules. This is the base name of the radio HAL\n * library composed of the \"radio.\" prefix, one of the base names below and\n * a suffix specific to the device.\n * E.g: radio.fm.default.so\n */\n\n#define RADIO_HARDWARE_MODULE_ID_FM \"fm\" /* corresponds to RADIO_CLASS_AM_FM */\n#define RADIO_HARDWARE_MODULE_ID_SAT \"sat\" /* corresponds to RADIO_CLASS_SAT */\n#define RADIO_HARDWARE_MODULE_ID_DT \"dt\" /* corresponds to RADIO_CLASS_DT */\n\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\nstruct radio_module {\n    struct hw_module_t common;\n};\n\n/*\n * Callback function called by the HAL when one of the following occurs:\n * - event RADIO_EVENT_HW_FAILURE: radio chip of driver failure requiring\n * closing and reopening of the tuner interface.\n * - event RADIO_EVENT_CONFIG: new configuration applied in response to open_tuner(),\n * or set_configuration(). The event status is 0 (no error) if the configuration has been applied,\n * -EINVAL is not or -ETIMEDOUT in case of time out.\n * - event RADIO_EVENT_TUNED: tune locked on new station/frequency following scan(),\n * step(), tune() or auto AF switching. The event status is 0 (no error) if in tune,\n * -EINVAL is not tuned and data in radio_program_info is not valid or -ETIMEDOUT if scan()\n * timed out.\n * - event RADIO_EVENT_TA: at the beginning and end of traffic announcement if current\n * configuration enables TA.\n * - event RADIO_EVENT_AF: after automatic switching to alternate frequency if current\n * configuration enables AF switching.\n * - event RADIO_EVENT_ANTENNA: when the antenna is connected or disconnected.\n * - event RADIO_EVENT_METADATA: when new meta data are received from the tuned station.\n * The callback MUST NOT be called synchronously while executing a HAL function but from\n * a separate thread.\n */\ntypedef void (*radio_callback_t)(radio_hal_event_t *event, void *cookie);\n\n/* control interface for a radio tuner */\nstruct radio_tuner {\n    /*\n     * Apply current radio band configuration (band, range, channel spacing ...).\n     *\n     * arguments:\n     * - config: the band configuration to apply\n     *\n     * returns:\n     *  0 if configuration could be applied\n     *  -EINVAL if configuration requested is invalid\n     *\n     * Automatically cancels pending scan, step or tune.\n     *\n     * Callback function with event RADIO_EVENT_CONFIG MUST be called once the\n     * configuration is applied or a failure occurs or after a time out.\n     */\n    int (*set_configuration)(const struct radio_tuner *tuner,\n                             const radio_hal_band_config_t *config);\n\n    /*\n     * Retrieve current radio band configuration.\n     *\n     * arguments:\n     * - config: where to return the band configuration\n     *\n     * returns:\n     *  0 if valid configuration is returned\n     *  -EINVAL if invalid arguments are passed\n     */\n    int (*get_configuration)(const struct radio_tuner *tuner,\n                             radio_hal_band_config_t *config);\n\n    /*\n     * Start scanning up to next valid station.\n     * Must be called when a valid configuration has been applied.\n     *\n     * arguments:\n     * - direction: RADIO_DIRECTION_UP or RADIO_DIRECTION_DOWN\n     * - skip_sub_channel: valid for HD radio or digital radios only: ignore sub channels\n     *  (e.g SPS for HD radio).\n     *\n     * returns:\n     *  0 if scan successfully started\n     *  -ENOSYS if called out of sequence\n     *  -ENODEV if another error occurs\n     *\n     * Automatically cancels pending scan, step or tune.\n     *\n     *  Callback function with event RADIO_EVENT_TUNED MUST be called once\n     *  locked on a station or after a time out or full frequency scan if\n     *  no station found. The event status should indicate if a valid station\n     *  is tuned or not.\n     */\n    int (*scan)(const struct radio_tuner *tuner,\n                radio_direction_t direction, bool skip_sub_channel);\n\n    /*\n     * Move one channel spacing up or down.\n     * Must be called when a valid configuration has been applied.\n     *\n     * arguments:\n     * - direction: RADIO_DIRECTION_UP or RADIO_DIRECTION_DOWN\n     * - skip_sub_channel: valid for HD radio or digital radios only: ignore sub channels\n     *  (e.g SPS for HD radio).\n     *\n     * returns:\n     *  0 if step successfully started\n     *  -ENOSYS if called out of sequence\n     *  -ENODEV if another error occurs\n     *\n     * Automatically cancels pending scan, step or tune.\n     *\n     * Callback function with event RADIO_EVENT_TUNED MUST be called once\n     * step completed or after a time out. The event status should indicate\n     * if a valid station is tuned or not.\n     */\n    int (*step)(const struct radio_tuner *tuner,\n                radio_direction_t direction, bool skip_sub_channel);\n\n    /*\n     * Tune to specified frequency.\n     * Must be called when a valid configuration has been applied.\n     *\n     * arguments:\n     * - channel: channel to tune to. A frequency in kHz for AM/FM/HD Radio bands.\n     * - sub_channel: valid for HD radio or digital radios only: (e.g SPS number for HD radio).\n     *\n     * returns:\n     *  0 if tune successfully started\n     *  -ENOSYS if called out of sequence\n     *  -EINVAL if invalid arguments are passed\n     *  -ENODEV if another error occurs\n     *\n     * Automatically cancels pending scan, step or tune.\n     *\n     * Callback function with event RADIO_EVENT_TUNED MUST be called once\n     * tuned or after a time out. The event status should indicate\n     * if a valid station is tuned or not.\n     */\n    int (*tune)(const struct radio_tuner *tuner,\n                unsigned int channel, unsigned int sub_channel);\n\n    /*\n     * Cancel a scan, step or tune operation.\n     * Must be called while a scan, step or tune operation is pending\n     * (callback not yet sent).\n     *\n     * returns:\n     *  0 if successful\n     *  -ENOSYS if called out of sequence\n     *  -ENODEV if another error occurs\n     *\n     * The callback is not sent.\n     */\n    int (*cancel)(const struct radio_tuner *tuner);\n\n    /*\n     * Retrieve current station information.\n     *\n     * arguments:\n     * - info: where to return the program info.\n     * If info->metadata is NULL. no meta data should be returned.\n     * If meta data must be returned, they should be added to or cloned to\n     * info->metadata, not passed from a newly created meta data buffer.\n     *\n     * returns:\n     *  0 if tuned and information available\n     *  -EINVAL if invalid arguments are passed\n     *  -ENODEV if another error occurs\n     */\n    int (*get_program_information)(const struct radio_tuner *tuner,\n                                   radio_program_info_t *info);\n};\n\nstruct radio_hw_device {\n    struct hw_device_t common;\n\n    /*\n     * Retrieve implementation properties.\n     *\n     * arguments:\n     * - properties: where to return the module properties\n     *\n     * returns:\n     *  0 if no error\n     *  -EINVAL if invalid arguments are passed\n     */\n    int (*get_properties)(const struct radio_hw_device *dev,\n                          radio_hal_properties_t *properties);\n\n    /*\n     * Open a tuner interface for the requested configuration.\n     * If no other tuner is opened, this will activate the radio module.\n     *\n     * arguments:\n     * - config: the band configuration to apply\n     * - audio: this tuner will be used for live radio listening and should be connected to\n     * the radio audio source.\n     * - callback: the event callback\n     * - cookie: the cookie to pass when calling the callback\n     * - tuner: where to return the tuner interface\n     *\n     * returns:\n     *  0 if HW was powered up and configuration could be applied\n     *  -EINVAL if configuration requested is invalid\n     *  -ENOSYS if called out of sequence\n     *\n     * Callback function with event RADIO_EVENT_CONFIG MUST be called once the\n     * configuration is applied or a failure occurs or after a time out.\n     */\n    int (*open_tuner)(const struct radio_hw_device *dev,\n                    const radio_hal_band_config_t *config,\n                    bool audio,\n                    radio_callback_t callback,\n                    void *cookie,\n                    const struct radio_tuner **tuner);\n\n    /*\n     * Close a tuner interface.\n     * If the last tuner is closed, the radio module is deactivated.\n     *\n     * arguments:\n     * - tuner: the tuner interface to close\n     *\n     * returns:\n     *  0 if powered down successfully.\n     *  -EINVAL if an invalid argument is passed\n     *  -ENOSYS if called out of sequence\n     */\n    int (*close_tuner)(const struct radio_hw_device *dev, const struct radio_tuner *tuner);\n\n};\n\ntypedef struct  radio_hw_device  radio_hw_device_t;\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int radio_hw_device_open(const struct hw_module_t* module,\n                                       struct radio_hw_device** device)\n{\n    return module->methods->open(module, RADIO_HARDWARE_DEVICE,\n                                 (struct hw_device_t**)device);\n}\n\nstatic inline int radio_hw_device_close(const struct radio_hw_device* device)\n{\n    return device->common.close((struct hw_device_t *)&device->common);\n}\n\n__END_DECLS\n\n#endif  // ANDROID_RADIO_HAL_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/sensors.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_SENSORS_INTERFACE_H\n#define ANDROID_SENSORS_INTERFACE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n#include <cutils/native_handle.h>\n\n__BEGIN_DECLS\n\n/*****************************************************************************/\n\n#define SENSORS_HEADER_VERSION          1\n#define SENSORS_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n#define SENSORS_DEVICE_API_VERSION_0_1  HARDWARE_DEVICE_API_VERSION_2(0, 1, SENSORS_HEADER_VERSION)\n#define SENSORS_DEVICE_API_VERSION_1_0  HARDWARE_DEVICE_API_VERSION_2(1, 0, SENSORS_HEADER_VERSION)\n#define SENSORS_DEVICE_API_VERSION_1_1  HARDWARE_DEVICE_API_VERSION_2(1, 1, SENSORS_HEADER_VERSION)\n#define SENSORS_DEVICE_API_VERSION_1_2  HARDWARE_DEVICE_API_VERSION_2(1, 2, SENSORS_HEADER_VERSION)\n#define SENSORS_DEVICE_API_VERSION_1_3  HARDWARE_DEVICE_API_VERSION_2(1, 3, SENSORS_HEADER_VERSION)\n#define SENSORS_DEVICE_API_VERSION_1_4  HARDWARE_DEVICE_API_VERSION_2(1, 4, SENSORS_HEADER_VERSION)\n\n/**\n * Please see the Sensors section of source.android.com for an\n * introduction to and detailed descriptions of Android sensor types:\n * http://source.android.com/devices/sensors/index.html\n */\n\n/**\n * The id of this module\n */\n#define SENSORS_HARDWARE_MODULE_ID \"sensors\"\n\n/**\n * Name of the sensors device to open\n */\n#define SENSORS_HARDWARE_POLL       \"poll\"\n\n/**\n * Handles must be higher than SENSORS_HANDLE_BASE and must be unique.\n * A Handle identifies a given sensors. The handle is used to activate\n * and/or deactivate sensors.\n * In this version of the API there can only be 256 handles.\n */\n#define SENSORS_HANDLE_BASE             0\n#define SENSORS_HANDLE_BITS             8\n#define SENSORS_HANDLE_COUNT            (1<<SENSORS_HANDLE_BITS)\n\n\n/*\n * **** Deprecated *****\n * flags for (*batch)()\n * Availability: SENSORS_DEVICE_API_VERSION_1_0\n * see (*batch)() documentation for details.\n * Deprecated as of  SENSORS_DEVICE_API_VERSION_1_3.\n * WAKE_UP_* sensors replace WAKE_UPON_FIFO_FULL concept.\n */\nenum {\n    SENSORS_BATCH_DRY_RUN               = 0x00000001,\n    SENSORS_BATCH_WAKE_UPON_FIFO_FULL   = 0x00000002\n};\n\n/*\n * what field for meta_data_event_t\n */\nenum {\n    /* a previous flush operation has completed */\n    META_DATA_FLUSH_COMPLETE = 1,\n    META_DATA_VERSION   /* always last, leave auto-assigned */\n};\n\n/*\n * The permission to use for body sensors (like heart rate monitors).\n * See sensor types for more details on what sensors should require this\n * permission.\n */\n#define SENSOR_PERMISSION_BODY_SENSORS \"android.permission.BODY_SENSORS\"\n\n/*\n * Availability: SENSORS_DEVICE_API_VERSION_1_4\n * Sensor HAL modes used in set_operation_mode method\n */\nenum {\n    /*\n     * Operating modes for the HAL.\n     */\n\n    /*\n     * Normal mode operation. This is the default state of operation.\n     * The HAL shall initialize into this mode on device startup.\n     */\n    SENSOR_HAL_NORMAL_MODE        = 0,\n\n    /*\n     * Data Injection mode. In this mode, the device shall not source data from the\n     * physical sensors as it would in normal mode. Instead sensor data is\n     * injected by the sensor service.\n     */\n    SENSOR_HAL_DATA_INJECTION_MODE      = 0x1\n};\n\n/*\n * Availability: SENSORS_DEVICE_API_VERSION_1_3\n * Sensor flags used in sensor_t.flags.\n */\nenum {\n    /*\n     * Whether this sensor wakes up the AP from suspend mode when data is available.  Whenever\n     * sensor events are delivered from a wake_up sensor, the driver needs to hold a wake_lock till\n     * the events are read by the SensorService i.e till sensors_poll_device_t.poll() is called the\n     * next time. Once poll is called again it means events have been read by the SensorService, the\n     * driver can safely release the wake_lock. SensorService will continue to hold a wake_lock till\n     * the app actually reads the events.\n     */\n    SENSOR_FLAG_WAKE_UP = 1U << 0,\n    /*\n     * Reporting modes for various sensors. Each sensor will have exactly one of these modes set.\n     * The least significant 2nd, 3rd and 4th bits are used to represent four possible reporting\n     * modes.\n     */\n    SENSOR_FLAG_CONTINUOUS_MODE        = 0,    // 0000\n    SENSOR_FLAG_ON_CHANGE_MODE         = 0x2,  // 0010\n    SENSOR_FLAG_ONE_SHOT_MODE          = 0x4,  // 0100\n    SENSOR_FLAG_SPECIAL_REPORTING_MODE = 0x6,  // 0110\n\n    /*\n     * Set this flag if the sensor supports data_injection mode and allows data to be injected\n     * from the SensorService. When in data_injection ONLY sensors with this flag set are injected\n     * sensor data and only sensors with this flag set are activated. Eg: Accelerometer and Step\n     * Counter sensors can be set with this flag and SensorService will inject accelerometer data\n     * and read the corresponding step counts.\n     */\n    SENSOR_FLAG_SUPPORTS_DATA_INJECTION = 0x10  // 1 0000\n};\n\n/*\n * Mask and shift for reporting mode sensor flags defined above.\n */\n#define REPORTING_MODE_MASK              (0xE)\n#define REPORTING_MODE_SHIFT             (1)\n\n/*\n * Mask and shift for data_injection mode sensor flags defined above.\n */\n#define DATA_INJECTION_MASK              (0x10)\n#define DATA_INJECTION_SHIFT             (4)\n\n/*\n * Sensor type\n *\n * Each sensor has a type which defines what this sensor measures and how\n * measures are reported. See the Base sensors and Composite sensors lists\n * for complete descriptions:\n * http://source.android.com/devices/sensors/base_triggers.html\n * http://source.android.com/devices/sensors/composite_sensors.html\n *\n * Device manufacturers (OEMs) can define their own sensor types, for\n * their private use by applications or services provided by them. Such\n * sensor types are specific to an OEM and can't be exposed in the SDK.\n * These types must start at SENSOR_TYPE_DEVICE_PRIVATE_BASE.\n *\n * All sensors defined outside of the device private range must correspond to\n * a type defined in this file, and must satisfy the characteristics listed in\n * the description of the sensor type.\n *\n * Starting with version SENSORS_DEVICE_API_VERSION_1_2, each sensor also\n * has a stringType.\n *  - StringType of sensors inside of the device private range MUST be prefixed\n *    by the sensor provider's or OEM reverse domain name. In particular, they\n *    cannot use the \"android.sensor\" prefix.\n *  - StringType of sensors outside of the device private range MUST correspond\n *    to the one defined in this file (starting with \"android.sensor\").\n *    For example, accelerometers must have\n *      type=SENSOR_TYPE_ACCELEROMETER and\n *      stringType=SENSOR_STRING_TYPE_ACCELEROMETER\n *\n * When android introduces a new sensor type that can replace an OEM-defined\n * sensor type, the OEM must use the official sensor type and stringType on\n * versions of the HAL that support this new official sensor type.\n *\n * Example (made up): Suppose Google's Glass team wants to surface a sensor\n * detecting that Glass is on a head.\n *  - Such a sensor is not officially supported in android KitKat\n *  - Glass devices launching on KitKat can implement a sensor with\n *    type = 0x10001 and stringType = \"com.google.glass.onheaddetector\"\n *  - In L android release, if android decides to define\n *    SENSOR_TYPE_ON_HEAD_DETECTOR and STRING_SENSOR_TYPE_ON_HEAD_DETECTOR,\n *    those types should replace the Glass-team-specific types in all future\n *    launches.\n *  - When launching Glass on the L release, Google should now use the official\n *    type (SENSOR_TYPE_ON_HEAD_DETECTOR) and stringType.\n *  - This way, all applications can now use this sensor.\n */\n\n/*\n * Base for device manufacturers private sensor types.\n * These sensor types can't be exposed in the SDK.\n */\n#define SENSOR_TYPE_DEVICE_PRIVATE_BASE     0x10000\n\n/*\n * SENSOR_TYPE_META_DATA\n * reporting-mode: n/a\n * wake-up sensor: n/a\n *\n * NO SENSOR OF THAT TYPE MUST BE RETURNED (*get_sensors_list)()\n *\n * SENSOR_TYPE_META_DATA is a special token used to populate the\n * sensors_meta_data_event structure. It doesn't correspond to a physical\n * sensor. sensors_meta_data_event are special, they exist only inside\n * the HAL and are generated spontaneously, as opposed to be related to\n * a physical sensor.\n *\n *   sensors_meta_data_event_t.version must be META_DATA_VERSION\n *   sensors_meta_data_event_t.sensor must be 0\n *   sensors_meta_data_event_t.type must be SENSOR_TYPE_META_DATA\n *   sensors_meta_data_event_t.reserved must be 0\n *   sensors_meta_data_event_t.timestamp must be 0\n *\n * The payload is a meta_data_event_t, where:\n * meta_data_event_t.what can take the following values:\n *\n * META_DATA_FLUSH_COMPLETE\n *   This event indicates that a previous (*flush)() call has completed for the sensor\n *   handle specified in meta_data_event_t.sensor.\n *   see (*flush)() for more details\n *\n * All other values for meta_data_event_t.what are reserved and\n * must not be used.\n *\n */\n#define SENSOR_TYPE_META_DATA                        (0)\n\n/*\n  * Wake up sensors.\n  * Each sensor may have either or both a wake-up and a non-wake variant.\n  * When registered in batch mode, wake-up sensors will wake up the AP when\n  * their FIFOs are full or when the batch timeout expires. A separate FIFO has\n  * to be maintained for wake up sensors and non wake up sensors. The non wake-up\n  * sensors need to overwrite their FIFOs when they are full till the AP wakes up\n  * and the wake-up sensors will wake-up the AP when their FIFOs are full or when\n  * the batch timeout expires without losing events. Wake-up and non wake-up variants\n  * of each sensor can be activated at different rates independently of each other.\n  *\n  * Note: Proximity sensor and significant motion sensor which were defined in previous\n  * releases are also wake-up sensors and should be treated as such. Wake-up one-shot\n  * sensors like SIGNIFICANT_MOTION cannot be batched, hence the text about batch above\n  * doesn't apply to them. See the definitions of SENSOR_TYPE_PROXIMITY and\n  * SENSOR_TYPE_SIGNIFICANT_MOTION for more info.\n  *\n  * Set SENSOR_FLAG_WAKE_UP flag for all wake-up sensors.\n  *\n  * For example, A device can have two sensors both of SENSOR_TYPE_ACCELEROMETER and\n  * one of them can be a wake_up sensor (with SENSOR_FLAG_WAKE_UP flag set) and the other\n  * can be a regular non wake_up sensor. Both of these sensors must be activated/deactivated\n  * independently of the other.\n  */\n\n/*\n * SENSOR_TYPE_ACCELEROMETER\n * reporting-mode: continuous\n *\n *  All values are in SI units (m/s^2) and measure the acceleration of the\n *  device minus the force of gravity.\n *\n *  Implement the non-wake-up version of this sensor and implement the wake-up\n *  version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_ACCELEROMETER                    (1)\n#define SENSOR_STRING_TYPE_ACCELEROMETER             \"android.sensor.accelerometer\"\n\n/*\n * SENSOR_TYPE_GEOMAGNETIC_FIELD\n * reporting-mode: continuous\n *\n *  All values are in micro-Tesla (uT) and measure the geomagnetic\n *  field in the X, Y and Z axis.\n *\n *  Implement the non-wake-up version of this sensor and implement the wake-up\n *  version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_GEOMAGNETIC_FIELD                (2)\n#define SENSOR_TYPE_MAGNETIC_FIELD  SENSOR_TYPE_GEOMAGNETIC_FIELD\n#define SENSOR_STRING_TYPE_MAGNETIC_FIELD            \"android.sensor.magnetic_field\"\n\n/*\n * SENSOR_TYPE_ORIENTATION\n * reporting-mode: continuous\n *\n * All values are angles in degrees.\n *\n * Orientation sensors return sensor events for all 3 axes at a constant\n * rate defined by setDelay().\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_ORIENTATION                      (3)\n#define SENSOR_STRING_TYPE_ORIENTATION               \"android.sensor.orientation\"\n\n/*\n * SENSOR_TYPE_GYROSCOPE\n * reporting-mode: continuous\n *\n *  All values are in radians/second and measure the rate of rotation\n *  around the X, Y and Z axis.\n *\n *  Implement the non-wake-up version of this sensor and implement the wake-up\n *  version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_GYROSCOPE                        (4)\n#define SENSOR_STRING_TYPE_GYROSCOPE                 \"android.sensor.gyroscope\"\n\n/*\n * SENSOR_TYPE_LIGHT\n * reporting-mode: on-change\n *\n * The light sensor value is returned in SI lux units.\n *\n * Both wake-up and non wake-up versions are useful.\n */\n#define SENSOR_TYPE_LIGHT                            (5)\n#define SENSOR_STRING_TYPE_LIGHT                     \"android.sensor.light\"\n\n/*\n * SENSOR_TYPE_PRESSURE\n * reporting-mode: continuous\n *\n * The pressure sensor return the athmospheric pressure in hectopascal (hPa)\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_PRESSURE                         (6)\n#define SENSOR_STRING_TYPE_PRESSURE                  \"android.sensor.pressure\"\n\n/* SENSOR_TYPE_TEMPERATURE is deprecated in the HAL */\n#define SENSOR_TYPE_TEMPERATURE                      (7)\n#define SENSOR_STRING_TYPE_TEMPERATURE               \"android.sensor.temperature\"\n\n/*\n * SENSOR_TYPE_PROXIMITY\n * reporting-mode: on-change\n *\n * The proximity sensor which turns the screen off and back on during calls is the\n * wake-up proximity sensor. Implement wake-up proximity sensor before implementing\n * a non wake-up proximity sensor. For the wake-up proximity sensor set the flag\n * SENSOR_FLAG_WAKE_UP.\n * The value corresponds to the distance to the nearest object in centimeters.\n */\n#define SENSOR_TYPE_PROXIMITY                        (8)\n#define SENSOR_STRING_TYPE_PROXIMITY                 \"android.sensor.proximity\"\n\n/*\n * SENSOR_TYPE_GRAVITY\n * reporting-mode: continuous\n *\n * A gravity output indicates the direction of and magnitude of gravity in\n * the devices's coordinates.\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_GRAVITY                          (9)\n#define SENSOR_STRING_TYPE_GRAVITY                   \"android.sensor.gravity\"\n\n/*\n * SENSOR_TYPE_LINEAR_ACCELERATION\n * reporting-mode: continuous\n *\n * Indicates the linear acceleration of the device in device coordinates,\n * not including gravity.\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_LINEAR_ACCELERATION             (10)\n#define SENSOR_STRING_TYPE_LINEAR_ACCELERATION      \"android.sensor.linear_acceleration\"\n\n\n/*\n * SENSOR_TYPE_ROTATION_VECTOR\n * reporting-mode: continuous\n *\n * The rotation vector symbolizes the orientation of the device relative to the\n * East-North-Up coordinates frame.\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_ROTATION_VECTOR                 (11)\n#define SENSOR_STRING_TYPE_ROTATION_VECTOR          \"android.sensor.rotation_vector\"\n\n/*\n * SENSOR_TYPE_RELATIVE_HUMIDITY\n * reporting-mode: on-change\n *\n * A relative humidity sensor measures relative ambient air humidity and\n * returns a value in percent.\n *\n * Both wake-up and non wake-up versions are useful.\n */\n#define SENSOR_TYPE_RELATIVE_HUMIDITY               (12)\n#define SENSOR_STRING_TYPE_RELATIVE_HUMIDITY        \"android.sensor.relative_humidity\"\n\n/*\n * SENSOR_TYPE_AMBIENT_TEMPERATURE\n * reporting-mode: on-change\n *\n * The ambient (room) temperature in degree Celsius.\n *\n * Both wake-up and non wake-up versions are useful.\n */\n#define SENSOR_TYPE_AMBIENT_TEMPERATURE             (13)\n#define SENSOR_STRING_TYPE_AMBIENT_TEMPERATURE      \"android.sensor.ambient_temperature\"\n\n/*\n * SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED\n * reporting-mode: continuous\n *\n *  Similar to SENSOR_TYPE_MAGNETIC_FIELD, but the hard iron calibration is\n *  reported separately instead of being included in the measurement.\n *\n *  Implement the non-wake-up version of this sensor and implement the wake-up\n *  version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED     (14)\n#define SENSOR_STRING_TYPE_MAGNETIC_FIELD_UNCALIBRATED \"android.sensor.magnetic_field_uncalibrated\"\n\n/*\n * SENSOR_TYPE_GAME_ROTATION_VECTOR\n * reporting-mode: continuous\n *\n *  Similar to SENSOR_TYPE_ROTATION_VECTOR, but not using the geomagnetic\n *  field.\n *\n *  Implement the non-wake-up version of this sensor and implement the wake-up\n *  version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_GAME_ROTATION_VECTOR            (15)\n#define SENSOR_STRING_TYPE_GAME_ROTATION_VECTOR     \"android.sensor.game_rotation_vector\"\n\n/*\n * SENSOR_TYPE_GYROSCOPE_UNCALIBRATED\n * reporting-mode: continuous\n *\n *  All values are in radians/second and measure the rate of rotation\n *  around the X, Y and Z axis.\n *\n *  Implement the non-wake-up version of this sensor and implement the wake-up\n *  version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_GYROSCOPE_UNCALIBRATED          (16)\n#define SENSOR_STRING_TYPE_GYROSCOPE_UNCALIBRATED   \"android.sensor.gyroscope_uncalibrated\"\n\n/*\n * SENSOR_TYPE_SIGNIFICANT_MOTION\n * reporting-mode: one-shot\n *\n * A sensor of this type triggers an event each time significant motion\n * is detected and automatically disables itself.\n * For Significant Motion sensor to be useful, it must be defined as a\n * wake-up sensor. (set SENSOR_FLAG_WAKE_UP). Implement the wake-up significant motion\n * sensor. A non wake-up version is not useful.\n * The only allowed value to return is 1.0.\n */\n\n#define SENSOR_TYPE_SIGNIFICANT_MOTION              (17)\n#define SENSOR_STRING_TYPE_SIGNIFICANT_MOTION       \"android.sensor.significant_motion\"\n\n/*\n * SENSOR_TYPE_STEP_DETECTOR\n * reporting-mode: special\n *\n * A sensor of this type triggers an event each time a step is taken\n * by the user. The only allowed value to return is 1.0 and an event\n * is generated for each step.\n *\n * Both wake-up and non wake-up versions are useful.\n */\n\n#define SENSOR_TYPE_STEP_DETECTOR                   (18)\n#define SENSOR_STRING_TYPE_STEP_DETECTOR            \"android.sensor.step_detector\"\n\n\n/*\n * SENSOR_TYPE_STEP_COUNTER\n * reporting-mode: on-change\n *\n * A sensor of this type returns the number of steps taken by the user since\n * the last reboot while activated. The value is returned as a uint64_t and is\n * reset to zero only on a system / android reboot.\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n\n#define SENSOR_TYPE_STEP_COUNTER                    (19)\n#define SENSOR_STRING_TYPE_STEP_COUNTER             \"android.sensor.step_counter\"\n\n/*\n * SENSOR_TYPE_GEOMAGNETIC_ROTATION_VECTOR\n * reporting-mode: continuous\n *\n *  Similar to SENSOR_TYPE_ROTATION_VECTOR, but using a magnetometer instead\n *  of using a gyroscope.\n *\n * Implement the non-wake-up version of this sensor and implement the wake-up\n * version if the system possesses a wake up fifo.\n */\n#define SENSOR_TYPE_GEOMAGNETIC_ROTATION_VECTOR     (20)\n#define SENSOR_STRING_TYPE_GEOMAGNETIC_ROTATION_VECTOR \"android.sensor.geomagnetic_rotation_vector\"\n\n/*\n * SENSOR_TYPE_HEART_RATE\n * reporting-mode: on-change\n *\n *  A sensor of this type returns the current heart rate.\n *  The events contain the current heart rate in beats per minute (BPM) and the\n *  status of the sensor during the measurement. See heart_rate_event_t for more\n *  details.\n *\n *  Because this sensor is on-change, events must be generated when and only\n *  when heart_rate.bpm or heart_rate.status have changed since the last\n *  event. In particular, upon the first activation, unless the device is known\n *  to not be on the body, the status field of the first event must be set to\n *  SENSOR_STATUS_UNRELIABLE. The event should be generated no faster than every\n *  period_ns passed to setDelay() or to batch().\n *  See the definition of the on-change reporting mode for more information.\n *\n *  sensor_t.requiredPermission must be set to SENSOR_PERMISSION_BODY_SENSORS.\n *\n *  Both wake-up and non wake-up versions are useful.\n */\n#define SENSOR_TYPE_HEART_RATE                      (21)\n#define SENSOR_STRING_TYPE_HEART_RATE               \"android.sensor.heart_rate\"\n\n/*\n * SENSOR_TYPE_WAKE_UP_TILT_DETECTOR\n * reporting-mode: special (setDelay has no impact)\n *\n * A sensor of this type generates an event each time a tilt event is detected. A tilt event\n * should be generated if the direction of the 2-seconds window average gravity changed by at least\n * 35 degrees since the activation or the last trigger of the sensor.\n *     reference_estimated_gravity = average of accelerometer measurements over the first\n *                                 1 second after activation or the estimated gravity at the last\n *                                 trigger.\n *     current_estimated_gravity = average of accelerometer measurements over the last 2 seconds.\n *     trigger when angle (reference_estimated_gravity, current_estimated_gravity) > 35 degrees\n *\n * Large accelerations without a change in phone orientation should not trigger a tilt event.\n * For example, a sharp turn or strong acceleration while driving a car should not trigger a tilt\n * event, even though the angle of the average acceleration might vary by more than 35 degrees.\n *\n * Typically, this sensor is implemented with the help of only an accelerometer. Other sensors can\n * be used as well if they do not increase the power consumption significantly. This is a low power\n * sensor that should allow the AP to go into suspend mode. Do not emulate this sensor in the HAL.\n * Like other wake up sensors, the driver is expected to a hold a wake_lock with a timeout of 200 ms\n * while reporting this event. The only allowed return value is 1.0.\n *\n * Implement only the wake-up version of this sensor.\n */\n#define SENSOR_TYPE_TILT_DETECTOR                      (22)\n#define SENSOR_STRING_TYPE_TILT_DETECTOR               \"android.sensor.tilt_detector\"\n\n/*\n * SENSOR_TYPE_WAKE_GESTURE\n * reporting-mode: one-shot\n *\n * A sensor enabling waking up the device based on a device specific motion.\n *\n * When this sensor triggers, the device behaves as if the power button was\n * pressed, turning the screen on. This behavior (turning on the screen when\n * this sensor triggers) might be deactivated by the user in the device\n * settings. Changes in settings do not impact the behavior of the sensor:\n * only whether the framework turns the screen on when it triggers.\n *\n * The actual gesture to be detected is not specified, and can be chosen by\n * the manufacturer of the device.\n * This sensor must be low power, as it is likely to be activated 24/7.\n * The only allowed value to return is 1.0.\n *\n * Implement only the wake-up version of this sensor.\n */\n#define SENSOR_TYPE_WAKE_GESTURE                               (23)\n#define SENSOR_STRING_TYPE_WAKE_GESTURE                        \"android.sensor.wake_gesture\"\n\n/*\n * SENSOR_TYPE_GLANCE_GESTURE\n * reporting-mode: one-shot\n *\n * A sensor enabling briefly turning the screen on to enable the user to\n * glance content on screen based on a specific motion.  The device should\n * turn the screen off after a few moments.\n *\n * When this sensor triggers, the device turns the screen on momentarily\n * to allow the user to glance notifications or other content while the\n * device remains locked in a non-interactive state (dozing). This behavior\n * (briefly turning on the screen when this sensor triggers) might be deactivated\n * by the user in the device settings. Changes in settings do not impact the\n * behavior of the sensor: only whether the framework briefly turns the screen on\n * when it triggers.\n *\n * The actual gesture to be detected is not specified, and can be chosen by\n * the manufacturer of the device.\n * This sensor must be low power, as it is likely to be activated 24/7.\n * The only allowed value to return is 1.0.\n *\n * Implement only the wake-up version of this sensor.\n */\n#define SENSOR_TYPE_GLANCE_GESTURE                             (24)\n#define SENSOR_STRING_TYPE_GLANCE_GESTURE                      \"android.sensor.glance_gesture\"\n\n/**\n * SENSOR_TYPE_PICK_UP_GESTURE\n * reporting-mode: one-shot\n *\n * A sensor of this type triggers when the device is picked up regardless of wherever is was\n * before (desk, pocket, bag). The only allowed return value is 1.0.\n * This sensor de-activates itself immediately after it triggers.\n *\n * Implement only the wake-up version of this sensor.\n */\n#define SENSOR_TYPE_PICK_UP_GESTURE                            (25)\n#define SENSOR_STRING_TYPE_PICK_UP_GESTURE                     \"android.sensor.pick_up_gesture\"\n\n/*\n * SENSOR_TYPE_WRIST_TILT_GESTURE\n * trigger-mode: special\n * wake-up sensor: yes\n *\n * A sensor of this type triggers an event each time a tilt of the wrist-worn\n * device is detected.\n *\n * This sensor must be low power, as it is likely to be activated 24/7.\n * The only allowed value to return is 1.0.\n *\n * Implement only the wake-up version of this sensor.\n */\n#define SENSOR_TYPE_WRIST_TILT_GESTURE                         (26)\n#define SENSOR_STRING_TYPE_WRIST_TILT_GESTURE                  \"android.sensor.wrist_tilt_gesture\"\n\n/**\n * Values returned by the accelerometer in various locations in the universe.\n * all values are in SI units (m/s^2)\n */\n#define GRAVITY_SUN             (275.0f)\n#define GRAVITY_EARTH           (9.80665f)\n\n/** Maximum magnetic field on Earth's surface */\n#define MAGNETIC_FIELD_EARTH_MAX    (60.0f)\n\n/** Minimum magnetic field on Earth's surface */\n#define MAGNETIC_FIELD_EARTH_MIN    (30.0f)\n\n/**\n * Possible values of the status field of sensor events.\n */\n#define SENSOR_STATUS_NO_CONTACT        -1\n#define SENSOR_STATUS_UNRELIABLE        0\n#define SENSOR_STATUS_ACCURACY_LOW      1\n#define SENSOR_STATUS_ACCURACY_MEDIUM   2\n#define SENSOR_STATUS_ACCURACY_HIGH     3\n\n/**\n * sensor event data\n */\ntypedef struct {\n    union {\n        float v[3];\n        struct {\n            float x;\n            float y;\n            float z;\n        };\n        struct {\n            float azimuth;\n            float pitch;\n            float roll;\n        };\n    };\n    int8_t status;\n    uint8_t reserved[3];\n} sensors_vec_t;\n\n/**\n * uncalibrated gyroscope and magnetometer event data\n */\ntypedef struct {\n  union {\n    float uncalib[3];\n    struct {\n      float x_uncalib;\n      float y_uncalib;\n      float z_uncalib;\n    };\n  };\n  union {\n    float bias[3];\n    struct {\n      float x_bias;\n      float y_bias;\n      float z_bias;\n    };\n  };\n} uncalibrated_event_t;\n\n/**\n * Meta data event data\n */\ntypedef struct meta_data_event {\n    int32_t what;\n    int32_t sensor;\n} meta_data_event_t;\n\n/**\n * Heart rate event data\n */\ntypedef struct {\n  // Heart rate in beats per minute.\n  // Set to 0 when status is SENSOR_STATUS_UNRELIABLE or ..._NO_CONTACT\n  float bpm;\n  // Status of the sensor for this reading. Set to one SENSOR_STATUS_...\n  // Note that this value should only be set for sensors that explicitly define\n  // the meaning of this field. This field is not piped through the framework\n  // for other sensors.\n  int8_t status;\n} heart_rate_event_t;\n\n/**\n * Union of the various types of sensor data\n * that can be returned.\n */\ntypedef struct sensors_event_t {\n    /* must be sizeof(struct sensors_event_t) */\n    int32_t version;\n\n    /* sensor identifier */\n    int32_t sensor;\n\n    /* sensor type */\n    int32_t type;\n\n    /* reserved */\n    int32_t reserved0;\n\n    /* time is in nanosecond */\n    int64_t timestamp;\n\n    union {\n        union {\n            float           data[16];\n\n            /* acceleration values are in meter per second per second (m/s^2) */\n            sensors_vec_t   acceleration;\n\n            /* magnetic vector values are in micro-Tesla (uT) */\n            sensors_vec_t   magnetic;\n\n            /* orientation values are in degrees */\n            sensors_vec_t   orientation;\n\n            /* gyroscope values are in rad/s */\n            sensors_vec_t   gyro;\n\n            /* temperature is in degrees centigrade (Celsius) */\n            float           temperature;\n\n            /* distance in centimeters */\n            float           distance;\n\n            /* light in SI lux units */\n            float           light;\n\n            /* pressure in hectopascal (hPa) */\n            float           pressure;\n\n            /* relative humidity in percent */\n            float           relative_humidity;\n\n            /* uncalibrated gyroscope values are in rad/s */\n            uncalibrated_event_t uncalibrated_gyro;\n\n            /* uncalibrated magnetometer values are in micro-Teslas */\n            uncalibrated_event_t uncalibrated_magnetic;\n\n            /* heart rate data containing value in bpm and status */\n            heart_rate_event_t heart_rate;\n\n            /* this is a special event. see SENSOR_TYPE_META_DATA above.\n             * sensors_meta_data_event_t events are all reported with a type of\n             * SENSOR_TYPE_META_DATA. The handle is ignored and must be zero.\n             */\n            meta_data_event_t meta_data;\n        };\n\n        union {\n            uint64_t        data[8];\n\n            /* step-counter */\n            uint64_t        step_counter;\n        } u64;\n    };\n\n    /* Reserved flags for internal use. Set to zero. */\n    uint32_t flags;\n\n    uint32_t reserved1[3];\n} sensors_event_t;\n\n\n/* see SENSOR_TYPE_META_DATA */\ntypedef sensors_event_t sensors_meta_data_event_t;\n\n\nstruct sensor_t;\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\nstruct sensors_module_t {\n    struct hw_module_t common;\n\n    /**\n     * Enumerate all available sensors. The list is returned in \"list\".\n     * @return number of sensors in the list\n     */\n    int (*get_sensors_list)(struct sensors_module_t* module,\n            struct sensor_t const** list);\n\n    /**\n     *  Place the module in a specific mode. The following modes are defined\n     *\n     *  0 - Normal operation. Default state of the module.\n     *  1 - Loopback mode. Data is injected for the the supported\n     *      sensors by the sensor service in this mode.\n     * @return 0 on success\n     *         -EINVAL if requested mode is not supported\n     *         -EPERM if operation is not allowed\n     */\n    int (*set_operation_mode)(unsigned int mode);\n};\n\nstruct sensor_t {\n\n    /* Name of this sensor.\n     * All sensors of the same \"type\" must have a different \"name\".\n     */\n    const char*     name;\n\n    /* vendor of the hardware part */\n    const char*     vendor;\n\n    /* version of the hardware part + driver. The value of this field\n     * must increase when the driver is updated in a way that changes the\n     * output of this sensor. This is important for fused sensors when the\n     * fusion algorithm is updated.\n     */\n    int             version;\n\n    /* handle that identifies this sensors. This handle is used to reference\n     * this sensor throughout the HAL API.\n     */\n    int             handle;\n\n    /* this sensor's type. */\n    int             type;\n\n    /* maximum range of this sensor's value in SI units */\n    float           maxRange;\n\n    /* smallest difference between two values reported by this sensor */\n    float           resolution;\n\n    /* rough estimate of this sensor's power consumption in mA */\n    float           power;\n\n    /* this value depends on the reporting mode:\n     *\n     *   continuous: minimum sample period allowed in microseconds\n     *   on-change : 0\n     *   one-shot  :-1\n     *   special   : 0, unless otherwise noted\n     */\n    int32_t         minDelay;\n\n    /* number of events reserved for this sensor in the batch mode FIFO.\n     * If there is a dedicated FIFO for this sensor, then this is the\n     * size of this FIFO. If the FIFO is shared with other sensors,\n     * this is the size reserved for that sensor and it can be zero.\n     */\n    uint32_t        fifoReservedEventCount;\n\n    /* maximum number of events of this sensor that could be batched.\n     * This is especially relevant when the FIFO is shared between\n     * several sensors; this value is then set to the size of that FIFO.\n     */\n    uint32_t        fifoMaxEventCount;\n\n    /* type of this sensor as a string. Set to corresponding\n     * SENSOR_STRING_TYPE_*.\n     * When defining an OEM specific sensor or sensor manufacturer specific\n     * sensor, use your reserve domain name as a prefix.\n     * ex: com.google.glass.onheaddetector\n     * For sensors of known type, the android framework might overwrite this\n     * string automatically.\n     */\n    const char*    stringType;\n\n    /* permission required to see this sensor, register to it and receive data.\n     * Set to \"\" if no permission is required. Some sensor types like the\n     * heart rate monitor have a mandatory require_permission.\n     * For sensors that always require a specific permission, like the heart\n     * rate monitor, the android framework might overwrite this string\n     * automatically.\n     */\n    const char*    requiredPermission;\n\n    /* This value is defined only for continuous mode and on-change sensors. It is the delay between\n     * two sensor events corresponding to the lowest frequency that this sensor supports. When lower\n     * frequencies are requested through batch()/setDelay() the events will be generated at this\n     * frequency instead. It can be used by the framework or applications to estimate when the batch\n     * FIFO may be full.\n     *\n     * NOTE: 1) period_ns is in nanoseconds where as maxDelay/minDelay are in microseconds.\n     *              continuous, on-change: maximum sampling period allowed in microseconds.\n     *              one-shot, special : 0\n     *   2) maxDelay should always fit within a 32 bit signed integer. It is declared as 64 bit\n     *      on 64 bit architectures only for binary compatibility reasons.\n     * Availability: SENSORS_DEVICE_API_VERSION_1_3\n     */\n    #ifdef __LP64__\n       int64_t maxDelay;\n    #else\n       int32_t maxDelay;\n    #endif\n\n    /* Flags for sensor. See SENSOR_FLAG_* above. Only the least significant 32 bits are used here.\n     * It is declared as 64 bit on 64 bit architectures only for binary compatibility reasons.\n     * Availability: SENSORS_DEVICE_API_VERSION_1_3\n     */\n    #ifdef __LP64__\n       uint64_t flags;\n    #else\n       uint32_t flags;\n    #endif\n\n    /* reserved fields, must be zero */\n    void*           reserved[2];\n};\n\n\n/*\n * sensors_poll_device_t is used with SENSORS_DEVICE_API_VERSION_0_1\n * and is present for backward binary and source compatibility.\n * See the Sensors HAL interface section for complete descriptions of the\n * following functions:\n * http://source.android.com/devices/sensors/index.html#hal\n */\nstruct sensors_poll_device_t {\n    struct hw_device_t common;\n    int (*activate)(struct sensors_poll_device_t *dev,\n            int sensor_handle, int enabled);\n    int (*setDelay)(struct sensors_poll_device_t *dev,\n            int sensor_handle, int64_t sampling_period_ns);\n    int (*poll)(struct sensors_poll_device_t *dev,\n            sensors_event_t* data, int count);\n};\n\n/*\n * struct sensors_poll_device_1 is used in HAL versions >= SENSORS_DEVICE_API_VERSION_1_0\n */\ntypedef struct sensors_poll_device_1 {\n    union {\n        /* sensors_poll_device_1 is compatible with sensors_poll_device_t,\n         * and can be down-cast to it\n         */\n        struct sensors_poll_device_t v0;\n\n        struct {\n            struct hw_device_t common;\n\n            /* Activate/de-activate one sensor. Return 0 on success, negative\n             *\n             * sensor_handle is the handle of the sensor to change.\n             * enabled set to 1 to enable, or 0 to disable the sensor.\n             *\n             * Return 0 on success, negative errno code otherwise.\n             */\n            int (*activate)(struct sensors_poll_device_t *dev,\n                    int sensor_handle, int enabled);\n\n            /**\n             * Set the events's period in nanoseconds for a given sensor.\n             * If sampling_period_ns > max_delay it will be truncated to\n             * max_delay and if sampling_period_ns < min_delay it will be\n             * replaced by min_delay.\n             */\n            int (*setDelay)(struct sensors_poll_device_t *dev,\n                    int sensor_handle, int64_t sampling_period_ns);\n\n            /**\n             * Returns an array of sensor data.\n             */\n            int (*poll)(struct sensors_poll_device_t *dev,\n                    sensors_event_t* data, int count);\n        };\n    };\n\n\n    /*\n     * Sets a sensor’s parameters, including sampling frequency and maximum\n     * report latency. This function can be called while the sensor is\n     * activated, in which case it must not cause any sensor measurements to\n     * be lost: transitioning from one sampling rate to the other cannot cause\n     * lost events, nor can transitioning from a high maximum report latency to\n     * a low maximum report latency.\n     * See the Batching sensor results page for details:\n     * http://source.android.com/devices/sensors/batching.html\n     */\n    int (*batch)(struct sensors_poll_device_1* dev,\n            int sensor_handle, int flags, int64_t sampling_period_ns,\n            int64_t max_report_latency_ns);\n\n    /*\n     * Flush adds a META_DATA_FLUSH_COMPLETE event (sensors_event_meta_data_t)\n     * to the end of the \"batch mode\" FIFO for the specified sensor and flushes\n     * the FIFO.\n     * If the FIFO is empty or if the sensor doesn't support batching (FIFO size zero),\n     * it should return SUCCESS along with a trivial META_DATA_FLUSH_COMPLETE event added to the\n     * event stream. This applies to all sensors other than one-shot sensors.\n     * If the sensor is a one-shot sensor, flush must return -EINVAL and not generate\n     * any flush complete metadata.\n     * If the sensor is not active at the time flush() is called, flush() should return\n     * -EINVAL.\n     */\n    int (*flush)(struct sensors_poll_device_1* dev, int sensor_handle);\n\n    /*\n     * Inject a single sensor sample to be to this device.\n     * data points to the sensor event to be injected\n     * @return 0 on success\n     *         -EPERM if operation is not allowed\n     *         -EINVAL if sensor event cannot be injected\n     */\n    int (*inject_sensor_data)(struct sensors_poll_device_1 *dev, const sensors_event_t *data);\n\n    void (*reserved_procs[7])(void);\n\n} sensors_poll_device_1_t;\n\n\n/** convenience API for opening and closing a device */\n\nstatic inline int sensors_open(const struct hw_module_t* module,\n        struct sensors_poll_device_t** device) {\n    return module->methods->open(module,\n            SENSORS_HARDWARE_POLL, (struct hw_device_t**)device);\n}\n\nstatic inline int sensors_close(struct sensors_poll_device_t* device) {\n    return device->common.close(&device->common);\n}\n\nstatic inline int sensors_open_1(const struct hw_module_t* module,\n        sensors_poll_device_1_t** device) {\n    return module->methods->open(module,\n            SENSORS_HARDWARE_POLL, (struct hw_device_t**)device);\n}\n\nstatic inline int sensors_close_1(sensors_poll_device_1_t* device) {\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif  // ANDROID_SENSORS_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/sound_trigger.h",
    "content": "/*\n * Copyright (C) 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <system/audio.h>\n#include <system/sound_trigger.h>\n#include <hardware/hardware.h>\n\n#ifndef ANDROID_SOUND_TRIGGER_HAL_H\n#define ANDROID_SOUND_TRIGGER_HAL_H\n\n\n__BEGIN_DECLS\n\n/**\n * The id of this module\n */\n#define SOUND_TRIGGER_HARDWARE_MODULE_ID \"sound_trigger\"\n\n/**\n * Name of the audio devices to open\n */\n#define SOUND_TRIGGER_HARDWARE_INTERFACE \"sound_trigger_hw_if\"\n\n#define SOUND_TRIGGER_MODULE_API_VERSION_1_0 HARDWARE_MODULE_API_VERSION(1, 0)\n#define SOUND_TRIGGER_MODULE_API_VERSION_CURRENT SOUND_TRIGGER_MODULE_API_VERSION_1_0\n\n\n#define SOUND_TRIGGER_DEVICE_API_VERSION_1_0 HARDWARE_DEVICE_API_VERSION(1, 0)\n#define SOUND_TRIGGER_DEVICE_API_VERSION_CURRENT SOUND_TRIGGER_DEVICE_API_VERSION_1_0\n\n/**\n * List of known sound trigger HAL modules. This is the base name of the sound_trigger HAL\n * library composed of the \"sound_trigger.\" prefix, one of the base names below and\n * a suffix specific to the device.\n * e.g: sondtrigger.primary.goldfish.so or sound_trigger.primary.default.so\n */\n\n#define SOUND_TRIGGER_HARDWARE_MODULE_ID_PRIMARY \"primary\"\n\n\n/**\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\nstruct sound_trigger_module {\n    struct hw_module_t common;\n};\n\ntypedef void (*recognition_callback_t)(struct sound_trigger_recognition_event *event, void *cookie);\ntypedef void (*sound_model_callback_t)(struct sound_trigger_model_event *event, void *cookie);\n\nstruct sound_trigger_hw_device {\n    struct hw_device_t common;\n\n    /*\n     * Retrieve implementation properties.\n     */\n    int (*get_properties)(const struct sound_trigger_hw_device *dev,\n                          struct sound_trigger_properties *properties);\n\n    /*\n     * Load a sound model. Once loaded, recognition of this model can be started and stopped.\n     * Only one active recognition per model at a time. The SoundTrigger service will handle\n     * concurrent recognition requests by different users/applications on the same model.\n     * The implementation returns a unique handle used by other functions (unload_sound_model(),\n     * start_recognition(), etc...\n     */\n    int (*load_sound_model)(const struct sound_trigger_hw_device *dev,\n                            struct sound_trigger_sound_model *sound_model,\n                            sound_model_callback_t callback,\n                            void *cookie,\n                            sound_model_handle_t *handle);\n\n    /*\n     * Unload a sound model. A sound model can be unloaded to make room for a new one to overcome\n     * implementation limitations.\n     */\n    int (*unload_sound_model)(const struct sound_trigger_hw_device *dev,\n                              sound_model_handle_t handle);\n\n    /* Start recognition on a given model. Only one recognition active at a time per model.\n     * Once recognition succeeds of fails, the callback is called.\n     * TODO: group recognition configuration parameters into one struct and add key phrase options.\n     */\n    int (*start_recognition)(const struct sound_trigger_hw_device *dev,\n                             sound_model_handle_t sound_model_handle,\n                             const struct sound_trigger_recognition_config *config,\n                             recognition_callback_t callback,\n                             void *cookie);\n\n    /* Stop recognition on a given model.\n     * The implementation does not have to call the callback when stopped via this method.\n     */\n    int (*stop_recognition)(const struct sound_trigger_hw_device *dev,\n                           sound_model_handle_t sound_model_handle);\n};\n\ntypedef struct sound_trigger_hw_device sound_trigger_hw_device_t;\n\n/** convenience API for opening and closing a supported device */\n\nstatic inline int sound_trigger_hw_device_open(const struct hw_module_t* module,\n                                       struct sound_trigger_hw_device** device)\n{\n    return module->methods->open(module, SOUND_TRIGGER_HARDWARE_INTERFACE,\n                                 (struct hw_device_t**)device);\n}\n\nstatic inline int sound_trigger_hw_device_close(struct sound_trigger_hw_device* device)\n{\n    return device->common.close(&device->common);\n}\n\n__END_DECLS\n\n#endif  // ANDROID_SOUND_TRIGGER_HAL_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/tv_input.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_TV_INPUT_INTERFACE_H\n#define ANDROID_TV_INPUT_INTERFACE_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n#include <hardware/hardware.h>\n#include <system/audio.h>\n#include <system/window.h>\n\n__BEGIN_DECLS\n\n/*\n * Module versioning information for the TV input hardware module, based on\n * tv_input_module_t.common.module_api_version.\n *\n * Version History:\n *\n * TV_INPUT_MODULE_API_VERSION_0_1:\n * Initial TV input hardware module API.\n *\n */\n\n#define TV_INPUT_MODULE_API_VERSION_0_1  HARDWARE_MODULE_API_VERSION(0, 1)\n\n#define TV_INPUT_DEVICE_API_VERSION_0_1  HARDWARE_DEVICE_API_VERSION(0, 1)\n\n/*\n * The id of this module\n */\n#define TV_INPUT_HARDWARE_MODULE_ID \"tv_input\"\n\n#define TV_INPUT_DEFAULT_DEVICE \"default\"\n\n/*****************************************************************************/\n\n/*\n * Every hardware module must have a data structure named HAL_MODULE_INFO_SYM\n * and the fields of this data structure must begin with hw_module_t\n * followed by module specific information.\n */\ntypedef struct tv_input_module {\n    struct hw_module_t common;\n} tv_input_module_t;\n\n/*****************************************************************************/\n\nenum {\n    /* Generic hardware. */\n    TV_INPUT_TYPE_OTHER_HARDWARE = 1,\n    /* Tuner. (e.g. built-in terrestrial tuner) */\n    TV_INPUT_TYPE_TUNER = 2,\n    TV_INPUT_TYPE_COMPOSITE = 3,\n    TV_INPUT_TYPE_SVIDEO = 4,\n    TV_INPUT_TYPE_SCART = 5,\n    TV_INPUT_TYPE_COMPONENT = 6,\n    TV_INPUT_TYPE_VGA = 7,\n    TV_INPUT_TYPE_DVI = 8,\n    /* Physical HDMI port. (e.g. HDMI 1) */\n    TV_INPUT_TYPE_HDMI = 9,\n    TV_INPUT_TYPE_DISPLAY_PORT = 10,\n};\ntypedef uint32_t tv_input_type_t;\n\ntypedef struct tv_input_device_info {\n    /* Device ID */\n    int device_id;\n\n    /* Type of physical TV input. */\n    tv_input_type_t type;\n\n    union {\n        struct {\n            /* HDMI port ID number */\n            uint32_t port_id;\n        } hdmi;\n\n        /* TODO: add other type specific information. */\n\n        int32_t type_info_reserved[16];\n    };\n\n    /* TODO: Add capability if necessary. */\n\n    /*\n     * Audio info\n     *\n     * audio_type == AUDIO_DEVICE_NONE if this input has no audio.\n     */\n    audio_devices_t audio_type;\n    const char* audio_address;\n\n    int32_t reserved[16];\n} tv_input_device_info_t;\n\n/* See tv_input_event_t for more details. */\nenum {\n    /*\n     * Hardware notifies the framework that a device is available.\n     *\n     * Note that DEVICE_AVAILABLE and DEVICE_UNAVAILABLE events do not represent\n     * hotplug events (i.e. plugging cable into or out of the physical port).\n     * These events notify the framework whether the port is available or not.\n     * For a concrete example, when a user plugs in or pulls out the HDMI cable\n     * from a HDMI port, it does not generate DEVICE_AVAILABLE and/or\n     * DEVICE_UNAVAILABLE events. However, if a user inserts a pluggable USB\n     * tuner into the Android device, it will generate a DEVICE_AVAILABLE event\n     * and when the port is removed, it should generate a DEVICE_UNAVAILABLE\n     * event.\n     *\n     * For hotplug events, please see STREAM_CONFIGURATION_CHANGED for more\n     * details.\n     *\n     * HAL implementation should register devices by using this event when the\n     * device boots up. The framework will recognize device reported via this\n     * event only. In addition, the implementation could use this event to\n     * notify the framework that a removable TV input device (such as USB tuner\n     * as stated in the example above) is attached.\n     */\n    TV_INPUT_EVENT_DEVICE_AVAILABLE = 1,\n    /*\n     * Hardware notifies the framework that a device is unavailable.\n     *\n     * HAL implementation should generate this event when a device registered\n     * by TV_INPUT_EVENT_DEVICE_AVAILABLE is no longer available. For example,\n     * the event can indicate that a USB tuner is plugged out from the Android\n     * device.\n     *\n     * Note that this event is not for indicating cable plugged out of the port;\n     * for that purpose, the implementation should use\n     * STREAM_CONFIGURATION_CHANGED event. This event represents the port itself\n     * being no longer available.\n     */\n    TV_INPUT_EVENT_DEVICE_UNAVAILABLE = 2,\n    /*\n     * Stream configurations are changed. Client should regard all open streams\n     * at the specific device are closed, and should call\n     * get_stream_configurations() again, opening some of them if necessary.\n     *\n     * HAL implementation should generate this event when the available stream\n     * configurations change for any reason. A typical use case of this event\n     * would be to notify the framework that the input signal has changed\n     * resolution, or that the cable is plugged out so that the number of\n     * available streams is 0.\n     *\n     * The implementation may use this event to indicate hotplug status of the\n     * port. the framework regards input devices with no available streams as\n     * disconnected, so the implementation can generate this event with no\n     * available streams to indicate that this device is disconnected, and vice\n     * versa.\n     */\n    TV_INPUT_EVENT_STREAM_CONFIGURATIONS_CHANGED = 3,\n    /*\n     * Hardware is done with capture request with the buffer. Client can assume\n     * ownership of the buffer again.\n     *\n     * HAL implementation should generate this event after request_capture() if\n     * it succeeded. The event shall have the buffer with the captured image.\n     */\n    TV_INPUT_EVENT_CAPTURE_SUCCEEDED = 4,\n    /*\n     * Hardware met a failure while processing a capture request or client\n     * canceled the request. Client can assume ownership of the buffer again.\n     *\n     * The event is similar to TV_INPUT_EVENT_CAPTURE_SUCCEEDED, but HAL\n     * implementation generates this event upon a failure to process\n     * request_capture(), or a request cancellation.\n     */\n    TV_INPUT_EVENT_CAPTURE_FAILED = 5,\n};\ntypedef uint32_t tv_input_event_type_t;\n\ntypedef struct tv_input_capture_result {\n    /* Device ID */\n    int device_id;\n\n    /* Stream ID */\n    int stream_id;\n\n    /* Sequence number of the request */\n    uint32_t seq;\n\n    /*\n     * The buffer passed to hardware in request_capture(). The content of\n     * buffer is undefined (although buffer itself is valid) for\n     * TV_INPUT_CAPTURE_FAILED event.\n     */\n    buffer_handle_t buffer;\n\n    /*\n     * Error code for the request. -ECANCELED if request is cancelled; other\n     * error codes are unknown errors.\n     */\n    int error_code;\n} tv_input_capture_result_t;\n\ntypedef struct tv_input_event {\n    tv_input_event_type_t type;\n\n    union {\n        /*\n         * TV_INPUT_EVENT_DEVICE_AVAILABLE: all fields are relevant\n         * TV_INPUT_EVENT_DEVICE_UNAVAILABLE: only device_id is relevant\n         * TV_INPUT_EVENT_STREAM_CONFIGURATIONS_CHANGED: only device_id is\n         *    relevant\n         */\n        tv_input_device_info_t device_info;\n        /*\n         * TV_INPUT_EVENT_CAPTURE_SUCCEEDED: error_code is not relevant\n         * TV_INPUT_EVENT_CAPTURE_FAILED: all fields are relevant\n         */\n        tv_input_capture_result_t capture_result;\n    };\n} tv_input_event_t;\n\ntypedef struct tv_input_callback_ops {\n    /*\n     * event contains the type of the event and additional data if necessary.\n     * The event object is guaranteed to be valid only for the duration of the\n     * call.\n     *\n     * data is an object supplied at device initialization, opaque to the\n     * hardware.\n     */\n    void (*notify)(struct tv_input_device* dev,\n            tv_input_event_t* event, void* data);\n} tv_input_callback_ops_t;\n\nenum {\n    TV_STREAM_TYPE_INDEPENDENT_VIDEO_SOURCE = 1,\n    TV_STREAM_TYPE_BUFFER_PRODUCER = 2,\n};\ntypedef uint32_t tv_stream_type_t;\n\ntypedef struct tv_stream_config {\n    /*\n     * ID number of the stream. This value is used to identify the whole stream\n     * configuration.\n     */\n    int stream_id;\n\n    /* Type of the stream */\n    tv_stream_type_t type;\n\n    /* Max width/height of the stream. */\n    uint32_t max_video_width;\n    uint32_t max_video_height;\n} tv_stream_config_t;\n\ntypedef struct buffer_producer_stream {\n    /*\n     * IN/OUT: Width / height of the stream. Client may request for specific\n     * size but hardware may change it. Client must allocate buffers with\n     * specified width and height.\n     */\n    uint32_t width;\n    uint32_t height;\n\n    /* OUT: Client must set this usage when allocating buffer. */\n    uint32_t usage;\n\n    /* OUT: Client must allocate a buffer with this format. */\n    uint32_t format;\n\n    /* OUT: Client must allocate buffers based on this count. */\n    uint32_t buffer_count;\n} buffer_producer_stream_t;\n\ntypedef struct tv_stream {\n    /* IN: ID in the stream configuration */\n    int stream_id;\n\n    /* OUT: Type of the stream (for convenience) */\n    tv_stream_type_t type;\n\n    /* Data associated with the stream for client's use */\n    union {\n        /* OUT: A native handle describing the sideband stream source */\n        native_handle_t* sideband_stream_source_handle;\n\n        /* IN/OUT: Details are in buffer_producer_stream_t */\n        buffer_producer_stream_t buffer_producer;\n    };\n} tv_stream_t;\n\n/*\n * Every device data structure must begin with hw_device_t\n * followed by module specific public methods and attributes.\n */\ntypedef struct tv_input_device {\n    struct hw_device_t common;\n\n    /*\n     * initialize:\n     *\n     * Provide callbacks to the device and start operation. At first, no device\n     * is available and after initialize() completes, currently available\n     * devices including static devices should notify via callback.\n     *\n     * Framework owns callbacks object.\n     *\n     * data is a framework-owned object which would be sent back to the\n     * framework for each callback notifications.\n     *\n     * Return 0 on success.\n     */\n    int (*initialize)(struct tv_input_device* dev,\n            const tv_input_callback_ops_t* callback, void* data);\n\n    /*\n     * get_stream_configurations:\n     *\n     * Get stream configurations for a specific device. An input device may have\n     * multiple configurations.\n     *\n     * The configs object is guaranteed to be valid only until the next call to\n     * get_stream_configurations() or STREAM_CONFIGURATIONS_CHANGED event.\n     *\n     * Return 0 on success.\n     */\n    int (*get_stream_configurations)(const struct tv_input_device* dev,\n            int device_id, int* num_configurations,\n            const tv_stream_config_t** configs);\n\n    /*\n     * open_stream:\n     *\n     * Open a stream with given stream ID. Caller owns stream object, and the\n     * populated data is only valid until the stream is closed.\n     *\n     * Return 0 on success; -EBUSY if the client should close other streams to\n     * open the stream; -EEXIST if the stream with the given ID is already open;\n     * -EINVAL if device_id and/or stream_id are invalid; other non-zero value\n     * denotes unknown error.\n     */\n    int (*open_stream)(struct tv_input_device* dev, int device_id,\n            tv_stream_t* stream);\n\n    /*\n     * close_stream:\n     *\n     * Close a stream to a device. data in tv_stream_t* object associated with\n     * the stream_id is obsolete once this call finishes.\n     *\n     * Return 0 on success; -ENOENT if the stream is not open; -EINVAL if\n     * device_id and/or stream_id are invalid.\n     */\n    int (*close_stream)(struct tv_input_device* dev, int device_id,\n            int stream_id);\n\n    /*\n     * request_capture:\n     *\n     * Request buffer capture for a stream. This is only valid for buffer\n     * producer streams. The buffer should be created with size, format and\n     * usage specified in the stream. Framework provides seq in an\n     * increasing sequence per each stream. Hardware should provide the picture\n     * in a chronological order according to seq. For example, if two\n     * requests are being processed at the same time, the request with the\n     * smaller seq should get an earlier frame.\n     *\n     * The framework releases the ownership of the buffer upon calling this\n     * function. When the buffer is filled, hardware notifies the framework\n     * via TV_INPUT_EVENT_CAPTURE_FINISHED callback, and the ownership is\n     * transferred back to framework at that time.\n     *\n     * Return 0 on success; -ENOENT if the stream is not open; -EINVAL if\n     * device_id and/or stream_id are invalid; -EWOULDBLOCK if HAL cannot take\n     * additional requests until it releases a buffer.\n     */\n    int (*request_capture)(struct tv_input_device* dev, int device_id,\n            int stream_id, buffer_handle_t buffer, uint32_t seq);\n\n    /*\n     * cancel_capture:\n     *\n     * Cancel an ongoing capture. Hardware should release the buffer as soon as\n     * possible via TV_INPUT_EVENT_CAPTURE_FAILED callback.\n     *\n     * Return 0 on success; -ENOENT if the stream is not open; -EINVAL if\n     * device_id, stream_id, and/or seq are invalid.\n     */\n    int (*cancel_capture)(struct tv_input_device* dev, int device_id,\n            int stream_id, uint32_t seq);\n\n    void* reserved[16];\n} tv_input_device_t;\n\n__END_DECLS\n\n#endif  // ANDROID_TV_INPUT_INTERFACE_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/vibrator.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _HARDWARE_VIBRATOR_H\n#define _HARDWARE_VIBRATOR_H\n\n#include <hardware/hardware.h>\n\n__BEGIN_DECLS\n\n#define VIBRATOR_API_VERSION HARDWARE_MODULE_API_VERSION(1,0)\n\n/**\n * The id of this module\n */\n#define VIBRATOR_HARDWARE_MODULE_ID \"vibrator\"\n\n/**\n * The id of the main vibrator device\n */\n#define VIBRATOR_DEVICE_ID_MAIN \"main_vibrator\"\n\nstruct vibrator_device;\ntypedef struct vibrator_device {\n    /**\n     * Common methods of the vibrator device.  This *must* be the first member of\n     * vibrator_device as users of this structure will cast a hw_device_t to\n     * vibrator_device pointer in contexts where it's known the hw_device_t references a\n     * vibrator_device.\n     */\n    struct hw_device_t common;\n\n    /** Turn on vibrator\n     *\n     * What happens when this function is called while the the timeout of a\n     * previous call has not expired is implementation dependent.\n     *\n     * @param timeout_ms number of milliseconds to vibrate\n     *\n     * @return 0 in case of success, negative errno code else\n     */\n    int (*vibrator_on)(struct vibrator_device* vibradev, unsigned int timeout_ms);\n\n    /** Turn off vibrator\n     *\n     * It is not guaranteed that the vibrator will be immediately stopped: the\n     * behaviour is implementation dependent.\n     *\n     * @return 0 in case of success, negative errno code else\n     */\n    int (*vibrator_off)(struct vibrator_device* vibradev);\n} vibrator_device_t;\n\nstatic inline int vibrator_open(const struct hw_module_t* module, vibrator_device_t** device)\n{\n    return module->methods->open(module, VIBRATOR_DEVICE_ID_MAIN, (struct hw_device_t**)device);\n}\n\n__END_DECLS\n\n#endif  // _HARDWARE_VIBRATOR_H\n"
  },
  {
    "path": "phonelibs/android_hardware_libhardware/include/hardware/wipower.h",
    "content": "/*\n * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *   * Redistributions of source code must retain the above copyright\n *     notice, this list of conditions and the following disclaimer.\n *   * Redistributions in binary form must reproduce the above\n *     copyright notice, this list of conditions and the following\n *     disclaimer in the documentation and/or other materials provided\n *     with the distribution.\n *   * Neither the name of The Linux Foundation nor the names of its\n *     contributors may be used to endorse or promote products derived\n *     from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\n * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\n * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN\n * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ANDROID_INCLUDE_WIPOWER_H\n#define ANDROID_INCLUDE_WIPOWER_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <stdbool.h>\n\n#include <hardware/hardware.h>\n#include <hardware/bluetooth.h>\n\n__BEGIN_DECLS\n\ntypedef enum {\n   OFF =0,\n   ON\n} wipower_state_t;\n\n\ntypedef struct {\n\nunsigned char optional;\nunsigned short rect_voltage;\nunsigned short rect_current;\nunsigned short out_voltage;\nunsigned short out_current;\nunsigned char temp;\nunsigned short rect_voltage_min;\nunsigned short rect_voltage_set;\nunsigned short rect_voltage_max;\nunsigned char alert;\nunsigned short rfu1;\nunsigned char rfu2;\n\n}__attribute__((packed)) wipower_dyn_data_t;\n\n/** Bluetooth Enable/Disable Callback. */\ntypedef void (*wipower_state_changed_callback)(wipower_state_t state);\n\n\ntypedef void (*wipower_alerts)(unsigned char alert);\n\n\ntypedef void (*wipower_dynamic_data)(wipower_dyn_data_t* alert_data);\n\n\ntypedef void (*wipower_power_apply)(unsigned char power_flag);\n\ntypedef void (*callback_thread_event)(bt_cb_thread_evt evt);\n\n/** Bluetooth DM callback structure. */\ntypedef struct {\n    /** set to sizeof(wipower_callbacks_t) */\n    size_t size;\n    wipower_state_changed_callback wipower_state_changed_cb;\n    wipower_alerts wipower_alert;\n    wipower_dynamic_data wipower_data;\n    wipower_power_apply wipower_power_event;\n    callback_thread_event callback_thread_event;\n} wipower_callbacks_t;\n\n\n/** Represents the standard Wipower interface. */\ntypedef struct {\n    /** set to sizeof(wipower_interface_t) */\n    size_t size;\n\n    /** Initialize Wipower modules*/\n    int (*init)(wipower_callbacks_t *wp_callbacks);\n\n    /** Enable/Disable Wipower charging */\n    int (*enable)(bool enable);\n\n    int (*set_current_limit)(short value);\n\n    unsigned char (*get_current_limit)(void);\n\n    wipower_state_t (*get_state)(void);\n\n    /** Enable/Disable Wipower charging */\n    int (*enable_alerts)(bool enable);\n\n    int (*enable_data_notify)(bool enable);\n    int (*enable_power_apply)(bool enable, bool on, bool time_flag);\n} wipower_interface_t;\n\n\n__END_DECLS\n\n#endif /* ANDROID_INCLUDE_WIPOWER_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/android_reboot.h",
    "content": "/*\n * Copyright 2011, The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_ANDROID_REBOOT_H__\n#define __CUTILS_ANDROID_REBOOT_H__\n\n#include <mntent.h>\n\n__BEGIN_DECLS\n\n/* Commands */\n#define ANDROID_RB_RESTART  0xDEAD0001\n#define ANDROID_RB_POWEROFF 0xDEAD0002\n#define ANDROID_RB_RESTART2 0xDEAD0003\n\n/* Properties */\n#define ANDROID_RB_PROPERTY \"sys.powerctl\"\n\nint android_reboot(int cmd, int flags, const char *arg);\nint android_reboot_with_callback(\n    int cmd, int flags, const char *arg,\n    void (*cb_on_remount)(const struct mntent*));\n\n__END_DECLS\n\n#endif /* __CUTILS_ANDROID_REBOOT_H__ */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/aref.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _CUTILS_AREF_H_\n#define _CUTILS_AREF_H_\n\n#include <stddef.h>\n#include <sys/cdefs.h>\n\n#include <cutils/atomic.h>\n\n__BEGIN_DECLS\n\n#define AREF_TO_ITEM(aref, container, member) \\\n    (container *) (((char*) (aref)) - offsetof(container, member))\n\nstruct aref\n{\n    volatile int32_t count;\n};\n\nstatic inline void aref_init(struct aref *r)\n{\n    r->count = 1;\n}\n\nstatic inline int32_t aref_count(struct aref *r)\n{\n    return r->count;\n}\n\nstatic inline void aref_get(struct aref *r)\n{\n    android_atomic_inc(&r->count);\n}\n\nstatic inline void aref_put(struct aref *r, void (*release)(struct aref *))\n{\n    if (android_atomic_dec(&r->count) == 1)\n        release(r);\n}\n\n__END_DECLS\n\n#endif // _CUTILS_AREF_H_\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/ashmem.h",
    "content": "/* cutils/ashmem.h\n **\n ** Copyright 2008 The Android Open Source Project\n **\n ** This file is dual licensed.  It may be redistributed and/or modified\n ** under the terms of the Apache 2.0 License OR version 2 of the GNU\n ** General Public License.\n */\n\n#ifndef _CUTILS_ASHMEM_H\n#define _CUTILS_ASHMEM_H\n\n#include <stddef.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nint ashmem_create_region(const char *name, size_t size);\nint ashmem_set_prot_region(int fd, int prot);\nint ashmem_pin_region(int fd, size_t offset, size_t len);\nint ashmem_unpin_region(int fd, size_t offset, size_t len);\nint ashmem_get_size_region(int fd);\n\n#ifdef __cplusplus\n}\n#endif\n\n#ifndef __ASHMEMIOC\t/* in case someone included <linux/ashmem.h> too */\n\n#define ASHMEM_NAME_LEN\t\t256\n\n#define ASHMEM_NAME_DEF\t\t\"dev/ashmem\"\n\n/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */\n#define ASHMEM_NOT_PURGED\t0\n#define ASHMEM_WAS_PURGED\t1\n\n/* Return values from ASHMEM_UNPIN: Is the mapping now pinned or unpinned? */\n#define ASHMEM_IS_UNPINNED\t0\n#define ASHMEM_IS_PINNED\t1\n\n#endif\t/* ! __ASHMEMIOC */\n\n#endif\t/* _CUTILS_ASHMEM_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/atomic.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_CUTILS_ATOMIC_H\n#define ANDROID_CUTILS_ATOMIC_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <stdatomic.h>\n\n#ifndef ANDROID_ATOMIC_INLINE\n#define ANDROID_ATOMIC_INLINE static inline\n#endif\n\n/*\n * A handful of basic atomic operations.\n * THESE ARE HERE FOR LEGACY REASONS ONLY.  AVOID.\n *\n * PREFERRED ALTERNATIVES:\n * - Use C++/C/pthread locks/mutexes whenever there is not a\n *   convincing reason to do otherwise.  Note that very clever and\n *   complicated, but correct, lock-free code is often slower than\n *   using locks, especially where nontrivial data structures\n *   are involved.\n * - C11 stdatomic.h.\n * - Where supported, C++11 std::atomic<T> .\n *\n * PLEASE STOP READING HERE UNLESS YOU ARE TRYING TO UNDERSTAND\n * OR UPDATE OLD CODE.\n *\n * The \"acquire\" and \"release\" terms can be defined intuitively in terms\n * of the placement of memory barriers in a simple lock implementation:\n *   - wait until compare-and-swap(lock-is-free --> lock-is-held) succeeds\n *   - barrier\n *   - [do work]\n *   - barrier\n *   - store(lock-is-free)\n * In very crude terms, the initial (acquire) barrier prevents any of the\n * \"work\" from happening before the lock is held, and the later (release)\n * barrier ensures that all of the work happens before the lock is released.\n * (Think of cached writes, cache read-ahead, and instruction reordering\n * around the CAS and store instructions.)\n *\n * The barriers must apply to both the compiler and the CPU.  Note it is\n * legal for instructions that occur before an \"acquire\" barrier to be\n * moved down below it, and for instructions that occur after a \"release\"\n * barrier to be moved up above it.\n *\n * The ARM-driven implementation we use here is short on subtlety,\n * and actually requests a full barrier from the compiler and the CPU.\n * The only difference between acquire and release is in whether they\n * are issued before or after the atomic operation with which they\n * are associated.  To ease the transition to C/C++ atomic intrinsics,\n * you should not rely on this, and instead assume that only the minimal\n * acquire/release protection is provided.\n *\n * NOTE: all int32_t* values are expected to be aligned on 32-bit boundaries.\n * If they are not, atomicity is not guaranteed.\n */\n\n/*\n * Basic arithmetic and bitwise operations.  These all provide a\n * barrier with \"release\" ordering, and return the previous value.\n *\n * These have the same characteristics (e.g. what happens on overflow)\n * as the equivalent non-atomic C operations.\n */\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_inc(volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n        /* Int32_t, if it exists, is the same as int_least32_t. */\n    return atomic_fetch_add_explicit(a, 1, memory_order_release);\n}\n\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_dec(volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return atomic_fetch_sub_explicit(a, 1, memory_order_release);\n}\n\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_add(int32_t value, volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return atomic_fetch_add_explicit(a, value, memory_order_release);\n}\n\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_and(int32_t value, volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return atomic_fetch_and_explicit(a, value, memory_order_release);\n}\n\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_or(int32_t value, volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return atomic_fetch_or_explicit(a, value, memory_order_release);\n}\n\n/*\n * Perform an atomic load with \"acquire\" or \"release\" ordering.\n *\n * Note that the notion of a \"release\" ordering for a load does not\n * really fit into the C11 or C++11 memory model.  The extra ordering\n * is normally observable only by code using memory_order_relaxed\n * atomics, or data races.  In the rare cases in which such ordering\n * is called for, use memory_order_relaxed atomics and a leading\n * atomic_thread_fence (typically with memory_order_acquire,\n * not memory_order_release!) instead.  If you do not understand\n * this comment, you are in the vast majority, and should not be\n * using release loads or replacing them with anything other than\n * locks or default sequentially consistent atomics.\n */\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_acquire_load(volatile const int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return atomic_load_explicit(a, memory_order_acquire);\n}\n\nANDROID_ATOMIC_INLINE\nint32_t android_atomic_release_load(volatile const int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    atomic_thread_fence(memory_order_seq_cst);\n    /* Any reasonable clients of this interface would probably prefer   */\n    /* something weaker.  But some remaining clients seem to be         */\n    /* abusing this API in strange ways, e.g. by using it as a fence.   */\n    /* Thus we are conservative until we can get rid of remaining       */\n    /* clients (and this function).                                     */\n    return atomic_load_explicit(a, memory_order_relaxed);\n}\n\n/*\n * Perform an atomic store with \"acquire\" or \"release\" ordering.\n *\n * Note that the notion of an \"acquire\" ordering for a store does not\n * really fit into the C11 or C++11 memory model.  The extra ordering\n * is normally observable only by code using memory_order_relaxed\n * atomics, or data races.  In the rare cases in which such ordering\n * is called for, use memory_order_relaxed atomics and a trailing\n * atomic_thread_fence (typically with memory_order_release,\n * not memory_order_acquire!) instead.\n */\nANDROID_ATOMIC_INLINE\nvoid android_atomic_acquire_store(int32_t value, volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    atomic_store_explicit(a, value, memory_order_relaxed);\n    atomic_thread_fence(memory_order_seq_cst);\n    /* Again overly conservative to accomodate weird clients.   */\n}\n\nANDROID_ATOMIC_INLINE\nvoid android_atomic_release_store(int32_t value, volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    atomic_store_explicit(a, value, memory_order_release);\n}\n\n/*\n * Compare-and-set operation with \"acquire\" or \"release\" ordering.\n *\n * This returns zero if the new value was successfully stored, which will\n * only happen when *addr == oldvalue.\n *\n * (The return value is inverted from implementations on other platforms,\n * but matches the ARM ldrex/strex result.)\n *\n * Implementations that use the release CAS in a loop may be less efficient\n * than possible, because we re-issue the memory barrier on each iteration.\n */\nANDROID_ATOMIC_INLINE\nint android_atomic_acquire_cas(int32_t oldvalue, int32_t newvalue,\n                           volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return (int)(!atomic_compare_exchange_strong_explicit(\n                                          a, &oldvalue, newvalue,\n                                          memory_order_acquire,\n                                          memory_order_acquire));\n}\n\nANDROID_ATOMIC_INLINE\nint android_atomic_release_cas(int32_t oldvalue, int32_t newvalue,\n                               volatile int32_t* addr)\n{\n    volatile atomic_int_least32_t* a = (volatile atomic_int_least32_t*)addr;\n    return (int)(!atomic_compare_exchange_strong_explicit(\n                                          a, &oldvalue, newvalue,\n                                          memory_order_release,\n                                          memory_order_relaxed));\n}\n\n/*\n * Fence primitives.\n */\nANDROID_ATOMIC_INLINE\nvoid android_compiler_barrier(void)\n{\n    __asm__ __volatile__ (\"\" : : : \"memory\");\n    /* Could probably also be:                          */\n    /* atomic_signal_fence(memory_order_seq_cst);       */\n}\n\nANDROID_ATOMIC_INLINE\nvoid android_memory_barrier(void)\n{\n    atomic_thread_fence(memory_order_seq_cst);\n}\n\n/*\n * Aliases for code using an older version of this header.  These are now\n * deprecated and should not be used.  The definitions will be removed\n * in a future release.\n */\n#define android_atomic_write android_atomic_release_store\n#define android_atomic_cmpxchg android_atomic_release_cas\n\n#endif // ANDROID_CUTILS_ATOMIC_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/bitops.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_BITOPS_H\n#define __CUTILS_BITOPS_H\n\n#include <stdbool.h>\n#include <string.h>\n#include <strings.h>\n#include <sys/cdefs.h>\n\n__BEGIN_DECLS\n\n/*\n * Bitmask Operations\n *\n * Note this doesn't provide any locking/exclusion, and isn't atomic.\n * Additionally no bounds checking is done on the bitmask array.\n *\n * Example:\n *\n * int num_resources;\n * unsigned int resource_bits[BITS_TO_WORDS(num_resources)];\n * bitmask_init(resource_bits, num_resources);\n * ...\n * int bit = bitmask_ffz(resource_bits, num_resources);\n * bitmask_set(resource_bits, bit);\n * ...\n * if (bitmask_test(resource_bits, bit)) { ... }\n * ...\n * bitmask_clear(resource_bits, bit);\n *\n */\n\n#define BITS_PER_WORD    (sizeof(unsigned int) * 8)\n#define BITS_TO_WORDS(x) (((x) + BITS_PER_WORD - 1) / BITS_PER_WORD)\n#define BIT_IN_WORD(x)   ((x) % BITS_PER_WORD)\n#define BIT_WORD(x)      ((x) / BITS_PER_WORD)\n#define BIT_MASK(x)      (1 << BIT_IN_WORD(x))\n\nstatic inline void bitmask_init(unsigned int *bitmask, int num_bits)\n{\n    memset(bitmask, 0, BITS_TO_WORDS(num_bits)*sizeof(unsigned int));\n}\n\nstatic inline int bitmask_ffz(unsigned int *bitmask, int num_bits)\n{\n    int bit, result;\n    size_t i;\n\n    for (i = 0; i < BITS_TO_WORDS(num_bits); i++) {\n        bit = ffs(~bitmask[i]);\n        if (bit) {\n            // ffs is 1-indexed, return 0-indexed result\n            bit--;\n            result = BITS_PER_WORD * i + bit;\n            if (result >= num_bits)\n                return -1;\n            return result;\n        }\n    }\n    return -1;\n}\n\nstatic inline int bitmask_weight(unsigned int *bitmask, int num_bits)\n{\n    size_t i;\n    int weight = 0;\n\n    for (i = 0; i < BITS_TO_WORDS(num_bits); i++)\n        weight += __builtin_popcount(bitmask[i]);\n    return weight;\n}\n\nstatic inline void bitmask_set(unsigned int *bitmask, int bit)\n{\n    bitmask[BIT_WORD(bit)] |= BIT_MASK(bit);\n}\n\nstatic inline void bitmask_clear(unsigned int *bitmask, int bit)\n{\n    bitmask[BIT_WORD(bit)] &= ~BIT_MASK(bit);\n}\n\nstatic inline bool bitmask_test(unsigned int *bitmask, int bit)\n{\n    return bitmask[BIT_WORD(bit)] & BIT_MASK(bit);\n}\n\nstatic inline int popcount(unsigned int x)\n{\n    return __builtin_popcount(x);\n}\n\nstatic inline int popcountl(unsigned long x)\n{\n    return __builtin_popcountl(x);\n}\n\nstatic inline int popcountll(unsigned long long x)\n{\n    return __builtin_popcountll(x);\n}\n\n__END_DECLS\n\n#endif /* __CUTILS_BITOPS_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/compiler.h",
    "content": "/*\n * Copyright (C) 2009 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_CUTILS_COMPILER_H\n#define ANDROID_CUTILS_COMPILER_H\n\n/*\n * helps the compiler's optimizer predicting branches\n */\n\n#ifdef __cplusplus\n#   define CC_LIKELY( exp )    (__builtin_expect( !!(exp), true ))\n#   define CC_UNLIKELY( exp )  (__builtin_expect( !!(exp), false ))\n#else\n#   define CC_LIKELY( exp )    (__builtin_expect( !!(exp), 1 ))\n#   define CC_UNLIKELY( exp )  (__builtin_expect( !!(exp), 0 ))\n#endif\n\n/**\n * exports marked symbols\n *\n * if used on a C++ class declaration, this macro must be inserted\n * after the \"class\" keyword. For instance:\n *\n * template <typename TYPE>\n * class ANDROID_API Singleton { }\n */\n\n#define ANDROID_API __attribute__((visibility(\"default\")))\n\n#endif // ANDROID_CUTILS_COMPILER_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/config_utils.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_CONFIG_UTILS_H\n#define __CUTILS_CONFIG_UTILS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n    \ntypedef struct cnode cnode;\n\n\nstruct cnode\n{\n    cnode *next;\n    cnode *first_child;\n    cnode *last_child;\n    const char *name;\n    const char *value;\n};\n\n/* parse a text string into a config node tree */\nvoid config_load(cnode *root, char *data);\n\n/* parse a file into a config node tree */\nvoid config_load_file(cnode *root, const char *fn);\n\n/* create a single config node */\ncnode* config_node(const char *name, const char *value);\n\n/* locate a named child of a config node */\ncnode* config_find(cnode *root, const char *name);\n\n/* look up a child by name and return the boolean value */\nint config_bool(cnode *root, const char *name, int _default);\n\n/* look up a child by name and return the string value */\nconst char* config_str(cnode *root, const char *name, const char *_default);\n\n/* add a named child to a config node (or modify it if it already exists) */\nvoid config_set(cnode *root, const char *name, const char *value);\n\n/* free a config node tree */\nvoid config_free(cnode *root);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/debugger.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_DEBUGGER_H\n#define __CUTILS_DEBUGGER_H\n\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n__BEGIN_DECLS\n\n#define DEBUGGER_SOCKET_NAME \"android:debuggerd\"\n#define DEBUGGER32_SOCKET_NAME \"android:debuggerd32\"\n#define DEBUGGER64_SOCKET_NAME DEBUGGER_SOCKET_NAME\n\ntypedef enum {\n    // dump a crash\n    DEBUGGER_ACTION_CRASH,\n    // dump a tombstone file\n    DEBUGGER_ACTION_DUMP_TOMBSTONE,\n    // dump a backtrace only back to the socket\n    DEBUGGER_ACTION_DUMP_BACKTRACE,\n} debugger_action_t;\n\n// Make sure that all values have a fixed size so that this structure\n// is the same for 32 bit and 64 bit processes.\n// NOTE: Any changes to this structure must also be reflected in\n//       bionic/linker/debugger.cpp.\ntypedef struct __attribute__((packed)) {\n    int32_t action;\n    pid_t tid;\n    uint64_t abort_msg_address;\n    int32_t original_si_code;\n} debugger_msg_t;\n\n/* Dumps a process backtrace, registers, and stack to a tombstone file (requires root).\n * Stores the tombstone path in the provided buffer.\n * Returns 0 on success, -1 on error.\n */\nint dump_tombstone(pid_t tid, char* pathbuf, size_t pathlen);\n\n/* Dumps a process backtrace, registers, and stack to a tombstone file (requires root).\n * Stores the tombstone path in the provided buffer.\n * If reading debugger data from debuggerd ever takes longer than timeout_secs\n * seconds, then stop and return an error.\n * Returns 0 on success, -1 on error.\n */\nint dump_tombstone_timeout(pid_t tid, char* pathbuf, size_t pathlen, int timeout_secs);\n\n/* Dumps a process backtrace only to the specified file (requires root).\n * Returns 0 on success, -1 on error.\n */\nint dump_backtrace_to_file(pid_t tid, int fd);\n\n/* Dumps a process backtrace only to the specified file (requires root).\n * If reading debugger data from debuggerd ever takes longer than timeout_secs\n * seconds, then stop and return an error.\n * Returns 0 on success, -1 on error.\n */\nint dump_backtrace_to_file_timeout(pid_t tid, int fd, int timeout_secs);\n\n__END_DECLS\n\n#endif /* __CUTILS_DEBUGGER_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/fs.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_FS_H\n#define __CUTILS_FS_H\n\n#include <sys/types.h>\n#include <unistd.h>\n\n/*\n * TEMP_FAILURE_RETRY is defined by some, but not all, versions of\n * <unistd.h>. (Alas, it is not as standard as we'd hoped!) So, if it's\n * not already defined, then define it here.\n */\n#ifndef TEMP_FAILURE_RETRY\n/* Used to retry syscalls that can return EINTR. */\n#define TEMP_FAILURE_RETRY(exp) ({         \\\n    typeof (exp) _rc;                      \\\n    do {                                   \\\n        _rc = (exp);                       \\\n    } while (_rc == -1 && errno == EINTR); \\\n    _rc; })\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * Ensure that directory exists with given mode and owners.\n */\nextern int fs_prepare_dir(const char* path, mode_t mode, uid_t uid, gid_t gid);\n\n/*\n * Read single plaintext integer from given file, correctly handling files\n * partially written with fs_write_atomic_int().\n */\nextern int fs_read_atomic_int(const char* path, int* value);\n\n/*\n * Write single plaintext integer to given file, creating backup while\n * in progress.\n */\nextern int fs_write_atomic_int(const char* path, int value);\n\n/*\n * Ensure that all directories along given path exist, creating parent\n * directories as needed.  Validates that given path is absolute and that\n * it contains no relative \".\" or \"..\" paths or symlinks.  Last path segment\n * is treated as filename and ignored, unless the path ends with \"/\".\n */\nextern int fs_mkdirs(const char* path, mode_t mode);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_FS_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/hashmap.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * Hash map.\n */\n\n#ifndef __HASHMAP_H\n#define __HASHMAP_H\n\n#include <stdbool.h>\n#include <stdlib.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** A hash map. */\ntypedef struct Hashmap Hashmap;\n\n/**\n * Creates a new hash map. Returns NULL if memory allocation fails.\n *\n * @param initialCapacity number of expected entries\n * @param hash function which hashes keys\n * @param equals function which compares keys for equality\n */\nHashmap* hashmapCreate(size_t initialCapacity,\n        int (*hash)(void* key), bool (*equals)(void* keyA, void* keyB));\n\n/**\n * Frees the hash map. Does not free the keys or values themselves.\n */\nvoid hashmapFree(Hashmap* map);\n\n/**\n * Hashes the memory pointed to by key with the given size. Useful for\n * implementing hash functions.\n */\nint hashmapHash(void* key, size_t keySize);\n\n/**\n * Puts value for the given key in the map. Returns pre-existing value if\n * any.\n *\n * If memory allocation fails, this function returns NULL, the map's size\n * does not increase, and errno is set to ENOMEM.\n */\nvoid* hashmapPut(Hashmap* map, void* key, void* value);\n\n/**\n * Gets a value from the map. Returns NULL if no entry for the given key is\n * found or if the value itself is NULL.\n */\nvoid* hashmapGet(Hashmap* map, void* key);\n\n/**\n * Returns true if the map contains an entry for the given key.\n */\nbool hashmapContainsKey(Hashmap* map, void* key);\n\n/**\n * Gets the value for a key. If a value is not found, this function gets a \n * value and creates an entry using the given callback.\n *\n * If memory allocation fails, the callback is not called, this function\n * returns NULL, and errno is set to ENOMEM.\n */\nvoid* hashmapMemoize(Hashmap* map, void* key, \n        void* (*initialValue)(void* key, void* context), void* context);\n\n/**\n * Removes an entry from the map. Returns the removed value or NULL if no\n * entry was present.\n */\nvoid* hashmapRemove(Hashmap* map, void* key);\n\n/**\n * Gets the number of entries in this map.\n */\nsize_t hashmapSize(Hashmap* map);\n\n/**\n * Invokes the given callback on each entry in the map. Stops iterating if\n * the callback returns false.\n */\nvoid hashmapForEach(Hashmap* map, \n        bool (*callback)(void* key, void* value, void* context),\n        void* context);\n\n/**\n * Concurrency support.\n */\n\n/**\n * Locks the hash map so only the current thread can access it.\n */\nvoid hashmapLock(Hashmap* map);\n\n/**\n * Unlocks the hash map so other threads can access it.\n */\nvoid hashmapUnlock(Hashmap* map);\n\n/**\n * Key utilities.\n */\n\n/**\n * Hashes int keys. 'key' is a pointer to int.\n */\nint hashmapIntHash(void* key);\n\n/**\n * Compares two int keys for equality.\n */\nbool hashmapIntEquals(void* keyA, void* keyB);\n\n/**\n * For debugging.\n */\n\n/**\n * Gets current capacity.\n */\nsize_t hashmapCurrentCapacity(Hashmap* map);\n\n/**\n * Counts the number of entry collisions.\n */\nsize_t hashmapCountCollisions(Hashmap* map);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __HASHMAP_H */ \n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/iosched_policy.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_IOSCHED_POLICY_H\n#define __CUTILS_IOSCHED_POLICY_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n    IoSchedClass_NONE,\n    IoSchedClass_RT,\n    IoSchedClass_BE,\n    IoSchedClass_IDLE,\n} IoSchedClass;\n\nextern int android_set_ioprio(int pid, IoSchedClass clazz, int ioprio);\nextern int android_get_ioprio(int pid, IoSchedClass *clazz, int *ioprio);\n\nextern int android_set_rt_ioprio(int pid, int rt);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_IOSCHED_POLICY_H */ \n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/jstring.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_STRING16_H\n#define __CUTILS_STRING16_H\n\n#include <stdint.h>\n#include <stddef.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#if __STDC_VERSION__ < 201112L && __cplusplus < 201103L\n  typedef uint16_t char16_t;\n#endif\n  // otherwise char16_t is a keyword with the right semantics\n\nextern char * strndup16to8 (const char16_t* s, size_t n);\nextern size_t strnlen16to8 (const char16_t* s, size_t n);\nextern char * strncpy16to8 (char *dest, const char16_t*s, size_t n);\n\nextern char16_t * strdup8to16 (const char* s, size_t *out_len);\nextern size_t strlen8to16 (const char* utf8Str);\nextern char16_t * strcpy8to16 (char16_t *dest, const char*s, size_t *out_len);\nextern char16_t * strcpylen8to16 (char16_t *dest, const char*s, int length,\n    size_t *out_len);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_STRING16_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/klog.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _CUTILS_KLOG_H_\n#define _CUTILS_KLOG_H_\n\n#include <sys/cdefs.h>\n#include <sys/uio.h>\n#include <stdarg.h>\n\n__BEGIN_DECLS\n\nvoid klog_init(void);\nint  klog_get_level(void);\nvoid klog_set_level(int level);\n/* TODO: void klog_close(void); - and make klog_fd users thread safe. */\n\nvoid klog_write(int level, const char *fmt, ...)\n    __attribute__ ((format(printf, 2, 3)));\nvoid klog_writev(int level, const struct iovec* iov, int iov_count);\n\n__END_DECLS\n\n#define KLOG_ERROR_LEVEL   3\n#define KLOG_WARNING_LEVEL 4\n#define KLOG_NOTICE_LEVEL  5\n#define KLOG_INFO_LEVEL    6\n#define KLOG_DEBUG_LEVEL   7\n\n#define KLOG_ERROR(tag,x...)   klog_write(KLOG_ERROR_LEVEL, \"<3>\" tag \": \" x)\n#define KLOG_WARNING(tag,x...) klog_write(KLOG_WARNING_LEVEL, \"<4>\" tag \": \" x)\n#define KLOG_NOTICE(tag,x...)  klog_write(KLOG_NOTICE_LEVEL, \"<5>\" tag \": \" x)\n#define KLOG_INFO(tag,x...)    klog_write(KLOG_INFO_LEVEL, \"<6>\" tag \": \" x)\n#define KLOG_DEBUG(tag,x...)   klog_write(KLOG_DEBUG_LEVEL, \"<7>\" tag \": \" x)\n\n#define KLOG_DEFAULT_LEVEL  3  /* messages <= this level are logged */\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/list.h",
    "content": "/*\n * Copyright (C) 2008-2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _CUTILS_LIST_H_\n#define _CUTILS_LIST_H_\n\n#include <stddef.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nstruct listnode\n{\n    struct listnode *next;\n    struct listnode *prev;\n};\n\n#define node_to_item(node, container, member) \\\n    (container *) (((char*) (node)) - offsetof(container, member))\n\n#define list_declare(name) \\\n    struct listnode name = { \\\n        .next = &name, \\\n        .prev = &name, \\\n    }\n\n#define list_for_each(node, list) \\\n    for (node = (list)->next; node != (list); node = node->next)\n\n#define list_for_each_reverse(node, list) \\\n    for (node = (list)->prev; node != (list); node = node->prev)\n\n#define list_for_each_safe(node, n, list) \\\n    for (node = (list)->next, n = node->next; \\\n         node != (list); \\\n         node = n, n = node->next)\n\nstatic inline void list_init(struct listnode *node)\n{\n    node->next = node;\n    node->prev = node;\n}\n\nstatic inline void list_add_tail(struct listnode *head, struct listnode *item)\n{\n    item->next = head;\n    item->prev = head->prev;\n    head->prev->next = item;\n    head->prev = item;\n}\n\nstatic inline void list_add_head(struct listnode *head, struct listnode *item)\n{\n    item->next = head->next;\n    item->prev = head;\n    head->next->prev = item;\n    head->next = item;\n}\n\nstatic inline void list_remove(struct listnode *item)\n{\n    item->next->prev = item->prev;\n    item->prev->next = item->next;\n}\n\n#define list_empty(list) ((list) == (list)->next)\n#define list_head(list) ((list)->next)\n#define list_tail(list) ((list)->prev)\n\n#ifdef __cplusplus\n};\n#endif /* __cplusplus */\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/log.h",
    "content": "#include <log/log.h>\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/memory.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_CUTILS_MEMORY_H\n#define ANDROID_CUTILS_MEMORY_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* size is given in bytes and must be multiple of 2 */\nvoid android_memset16(uint16_t* dst, uint16_t value, size_t size);\n\n/* size is given in bytes and must be multiple of 4 */\nvoid android_memset32(uint32_t* dst, uint32_t value, size_t size);\n\n#if defined(__GLIBC__) || defined(_WIN32)\n/* Declaration of strlcpy() for platforms that don't already have it. */\nsize_t strlcpy(char *dst, const char *src, size_t size);\n#endif\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n#endif // ANDROID_CUTILS_MEMORY_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/misc.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_MISC_H\n#define __CUTILS_MISC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n        /* Load an entire file into a malloc'd chunk of memory\n         * that is length_of_file + 1 (null terminator).  If\n         * sz is non-zero, return the size of the file via sz.\n         * Returns 0 on failure.\n         */\nextern void *load_file(const char *fn, unsigned *sz);\n\n        /* This is the range of UIDs (and GIDs) that are reserved\n         * for assigning to applications.\n         */\n#define FIRST_APPLICATION_UID 10000\n#define LAST_APPLICATION_UID 99999\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_MISC_H */ \n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/multiuser.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_MULTIUSER_H\n#define __CUTILS_MULTIUSER_H\n\n#include <sys/types.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// NOTE: keep in sync with android.os.UserId\n\n#define MULTIUSER_APP_PER_USER_RANGE 100000\n\ntypedef uid_t userid_t;\ntypedef uid_t appid_t;\n\nextern userid_t multiuser_get_user_id(uid_t uid);\nextern appid_t multiuser_get_app_id(uid_t uid);\nextern uid_t multiuser_get_uid(userid_t userId, appid_t appId);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_MULTIUSER_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/native_handle.h",
    "content": "/*\n * Copyright (C) 2009 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef NATIVE_HANDLE_H_\n#define NATIVE_HANDLE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef struct native_handle\n{\n    int version;        /* sizeof(native_handle_t) */\n    int numFds;         /* number of file-descriptors at &data[0] */\n    int numInts;        /* number of ints at &data[numFds] */\n    int data[0];        /* numFds + numInts ints */\n} native_handle_t;\n\n/*\n * native_handle_close\n * \n * closes the file descriptors contained in this native_handle_t\n * \n * return 0 on success, or a negative error code on failure\n * \n */\nint native_handle_close(const native_handle_t* h);\n\n\n/*\n * native_handle_create\n * \n * creates a native_handle_t and initializes it. must be destroyed with\n * native_handle_delete().\n * \n */\nnative_handle_t* native_handle_create(int numFds, int numInts);\n\n/*\n * native_handle_delete\n * \n * frees a native_handle_t allocated with native_handle_create().\n * This ONLY frees the memory allocated for the native_handle_t, but doesn't\n * close the file descriptors; which can be achieved with native_handle_close().\n * \n * return 0 on success, or a negative error code on failure\n * \n */\nint native_handle_delete(native_handle_t* h);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* NATIVE_HANDLE_H_ */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/open_memstream.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_OPEN_MEMSTREAM_H__\n#define __CUTILS_OPEN_MEMSTREAM_H__\n\n#include <stdio.h>\n\n#if defined(__APPLE__)\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nFILE* open_memstream(char** bufp, size_t* sizep);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __APPLE__ */\n\n#endif /*__CUTILS_OPEN_MEMSTREAM_H__*/\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/partition_utils.h",
    "content": "/*\n * Copyright 2011, The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_PARTITION_WIPED_H__\n#define __CUTILS_PARTITION_WIPED_H__\n\n__BEGIN_DECLS\n\nint partition_wiped(char *source);\n\n__END_DECLS\n\n#endif /* __CUTILS_PARTITION_WIPED_H__ */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/process_name.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n * Gives the current process a name.\n */\n\n#ifndef __PROCESS_NAME_H\n#define __PROCESS_NAME_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Sets the current process name.\n *\n * Warning: This leaks a string every time you call it. Use judiciously!\n */\nvoid set_process_name(const char* process_name);\n\n/** Gets the current process name. */\nconst char* get_process_name(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __PROCESS_NAME_H */ \n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/properties.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_PROPERTIES_H\n#define __CUTILS_PROPERTIES_H\n\n#include <sys/cdefs.h>\n#include <stddef.h>\n#include <sys/system_properties.h>\n#include <stdint.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* System properties are *small* name value pairs managed by the\n** property service.  If your data doesn't fit in the provided\n** space it is not appropriate for a system property.\n**\n** WARNING: system/bionic/include/sys/system_properties.h also defines\n**          these, but with different names.  (TODO: fix that)\n*/\n#define PROPERTY_KEY_MAX   PROP_NAME_MAX\n#define PROPERTY_VALUE_MAX  PROP_VALUE_MAX\n\n/* property_get: returns the length of the value which will never be\n** greater than PROPERTY_VALUE_MAX - 1 and will always be zero terminated.\n** (the length does not include the terminating zero).\n**\n** If the property read fails or returns an empty value, the default\n** value is used (if nonnull).\n*/\nint property_get(const char *key, char *value, const char *default_value);\n\n/* property_get_bool: returns the value of key coerced into a\n** boolean. If the property is not set, then the default value is returned.\n**\n* The following is considered to be true (1):\n**   \"1\", \"true\", \"y\", \"yes\", \"on\"\n**\n** The following is considered to be false (0):\n**   \"0\", \"false\", \"n\", \"no\", \"off\"\n**\n** The conversion is whitespace-sensitive (e.g. \" off\" will not be false).\n**\n** If no property with this key is set (or the key is NULL) or the boolean\n** conversion fails, the default value is returned.\n**/\nint8_t property_get_bool(const char *key, int8_t default_value);\n\n/* property_get_int64: returns the value of key truncated and coerced into a\n** int64_t. If the property is not set, then the default value is used.\n**\n** The numeric conversion is identical to strtoimax with the base inferred:\n** - All digits up to the first non-digit characters are read\n** - The longest consecutive prefix of digits is converted to a long\n**\n** Valid strings of digits are:\n** - An optional sign character + or -\n** - An optional prefix indicating the base (otherwise base 10 is assumed)\n**   -- 0 prefix is octal\n**   -- 0x / 0X prefix is hex\n**\n** Leading/trailing whitespace is ignored. Overflow/underflow will cause\n** numeric conversion to fail.\n**\n** If no property with this key is set (or the key is NULL) or the numeric\n** conversion fails, the default value is returned.\n**/\nint64_t property_get_int64(const char *key, int64_t default_value);\n\n/* property_get_int32: returns the value of key truncated and coerced into an\n** int32_t. If the property is not set, then the default value is used.\n**\n** The numeric conversion is identical to strtoimax with the base inferred:\n** - All digits up to the first non-digit characters are read\n** - The longest consecutive prefix of digits is converted to a long\n**\n** Valid strings of digits are:\n** - An optional sign character + or -\n** - An optional prefix indicating the base (otherwise base 10 is assumed)\n**   -- 0 prefix is octal\n**   -- 0x / 0X prefix is hex\n**\n** Leading/trailing whitespace is ignored. Overflow/underflow will cause\n** numeric conversion to fail.\n**\n** If no property with this key is set (or the key is NULL) or the numeric\n** conversion fails, the default value is returned.\n**/\nint32_t property_get_int32(const char *key, int32_t default_value);\n\n/* property_set: returns 0 on success, < 0 on failure\n*/\nint property_set(const char *key, const char *value);\n    \nint property_list(void (*propfn)(const char *key, const char *value, void *cookie), void *cookie);    \n\n#if defined(__BIONIC_FORTIFY)\n\nextern int __property_get_real(const char *, char *, const char *)\n    __asm__(__USER_LABEL_PREFIX__ \"property_get\");\n__errordecl(__property_get_too_small_error, \"property_get() called with too small of a buffer\");\n\n__BIONIC_FORTIFY_INLINE\nint property_get(const char *key, char *value, const char *default_value) {\n    size_t bos = __bos(value);\n    if (bos < PROPERTY_VALUE_MAX) {\n        __property_get_too_small_error();\n    }\n    return __property_get_real(key, value, default_value);\n}\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/qtaguid.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_QTAGUID_H\n#define __CUTILS_QTAGUID_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <unistd.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * Set tags (and owning UIDs) for network sockets.\n*/\nextern int qtaguid_tagSocket(int sockfd, int tag, uid_t uid);\n\n/*\n * Untag a network socket before closing.\n*/\nextern int qtaguid_untagSocket(int sockfd);\n\n/*\n * For the given uid, switch counter sets.\n * The kernel only keeps a limited number of sets.\n * 2 for now.\n */\nextern int qtaguid_setCounterSet(int counterSetNum, uid_t uid);\n\n/*\n * Delete all tag info that relates to the given tag an uid.\n * If the tag is 0, then ALL info about the uid is freeded.\n * The delete data also affects active tagged socketd, which are\n * then untagged.\n * The calling process can only operate on its own tags.\n * Unless it is part of the happy AID_NET_BW_ACCT group.\n * In which case it can clobber everything.\n */\nextern int qtaguid_deleteTagData(int tag, uid_t uid);\n\n/*\n * Enable/disable qtaguid functionnality at a lower level.\n * When pacified, the kernel will accept commands but do nothing.\n */\nextern int qtaguid_setPacifier(int on);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_QTAG_UID_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/record_stream.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n * A simple utility for reading fixed records out of a stream fd\n */\n\n#ifndef _CUTILS_RECORD_STREAM_H\n#define _CUTILS_RECORD_STREAM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\ntypedef struct RecordStream RecordStream;\n\nextern RecordStream *record_stream_new(int fd, size_t maxRecordLen);\nextern void record_stream_free(RecordStream *p_rs);\n\nextern int record_stream_get_next (RecordStream *p_rs, void ** p_outRecord, \n                                    size_t *p_outRecordLen);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /*_CUTILS_RECORD_STREAM_H*/\n\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/sched_policy.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_SCHED_POLICY_H\n#define __CUTILS_SCHED_POLICY_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Keep in sync with THREAD_GROUP_* in frameworks/base/core/java/android/os/Process.java */\ntypedef enum {\n    SP_DEFAULT    = -1,\n    SP_BACKGROUND = 0,\n    SP_FOREGROUND = 1,\n    SP_SYSTEM     = 2,  // can't be used with set_sched_policy()\n    SP_AUDIO_APP  = 3,\n    SP_AUDIO_SYS  = 4,\n    SP_CNT,\n    SP_MAX        = SP_CNT - 1,\n    SP_SYSTEM_DEFAULT = SP_FOREGROUND,\n} SchedPolicy;\n\nextern int set_cpuset_policy(int tid, SchedPolicy policy);\n\n/* Assign thread tid to the cgroup associated with the specified policy.\n * If the thread is a thread group leader, that is it's gettid() == getpid(),\n * then the other threads in the same thread group are _not_ affected.\n * On platforms which support gettid(), zero tid means current thread.\n * Return value: 0 for success, or -errno for error.\n */\nextern int set_sched_policy(int tid, SchedPolicy policy);\n\n/* Return the policy associated with the cgroup of thread tid via policy pointer.\n * On platforms which support gettid(), zero tid means current thread.\n * Return value: 0 for success, or -1 for error and set errno.\n */\nextern int get_sched_policy(int tid, SchedPolicy *policy);\n\n/* Return a displayable string corresponding to policy.\n * Return value: non-NULL NUL-terminated name of unspecified length;\n * the caller is responsible for displaying the useful part of the string.\n */\nextern const char *get_sched_policy_name(SchedPolicy policy);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_SCHED_POLICY_H */ \n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/sockets.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_SOCKETS_H\n#define __CUTILS_SOCKETS_H\n\n#include <errno.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdbool.h>\n\n#ifdef HAVE_WINSOCK\n#include <winsock2.h>\ntypedef int  socklen_t;\n#else\n#include <sys/socket.h>\n#endif\n\n#define ANDROID_SOCKET_ENV_PREFIX\t\"ANDROID_SOCKET_\"\n#define ANDROID_SOCKET_DIR\t\t\"/dev/socket\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * android_get_control_socket - simple helper function to get the file\n * descriptor of our init-managed Unix domain socket. `name' is the name of the\n * socket, as given in init.rc. Returns -1 on error.\n *\n * This is inline and not in libcutils proper because we want to use this in\n * third-party daemons with minimal modification.\n */\nstatic inline int android_get_control_socket(const char *name)\n{\n\tchar key[64];\n\tsnprintf(key, sizeof(key), ANDROID_SOCKET_ENV_PREFIX \"%s\", name);\n\n\tconst char* val = getenv(key);\n\tif (!val) {\n\t\treturn -1;\n\t}\n\n\terrno = 0;\n\tint fd = strtol(val, NULL, 10);\n\tif (errno) {\n\t\treturn -1;\n\t}\n\n\treturn fd;\n}\n\n/*\n * See also android.os.LocalSocketAddress.Namespace\n */\n// Linux \"abstract\" (non-filesystem) namespace\n#define ANDROID_SOCKET_NAMESPACE_ABSTRACT 0\n// Android \"reserved\" (/dev/socket) namespace\n#define ANDROID_SOCKET_NAMESPACE_RESERVED 1\n// Normal filesystem namespace\n#define ANDROID_SOCKET_NAMESPACE_FILESYSTEM 2\n\nextern int socket_loopback_client(int port, int type);\nextern int socket_network_client(const char *host, int port, int type);\nextern int socket_network_client_timeout(const char *host, int port, int type,\n                                         int timeout);\nextern int socket_loopback_server(int port, int type);\nextern int socket_local_server(const char *name, int namespaceId, int type);\nextern int socket_local_server_bind(int s, const char *name, int namespaceId);\nextern int socket_local_client_connect(int fd, \n        const char *name, int namespaceId, int type);\nextern int socket_local_client(const char *name, int namespaceId, int type);\nextern int socket_inaddr_any_server(int port, int type);\n\n/*\n * socket_peer_is_trusted - Takes a socket which is presumed to be a\n * connected local socket (e.g. AF_LOCAL) and returns whether the peer\n * (the userid that owns the process on the other end of that socket)\n * is one of the two trusted userids, root or shell.\n *\n * Note: This only works as advertised on the Android OS and always\n * just returns true when called on other operating systems.\n */\nextern bool socket_peer_is_trusted(int fd);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_SOCKETS_H */ \n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/str_parms.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_STR_PARMS_H\n#define __CUTILS_STR_PARMS_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n\n__BEGIN_DECLS\n\nstruct str_parms;\n\nstruct str_parms *str_parms_create(void);\nstruct str_parms *str_parms_create_str(const char *_string);\nvoid str_parms_destroy(struct str_parms *str_parms);\n\nvoid str_parms_del(struct str_parms *str_parms, const char *key);\n\nint str_parms_add_str(struct str_parms *str_parms, const char *key,\n                      const char *value);\nint str_parms_add_int(struct str_parms *str_parms, const char *key, int value);\n\nint str_parms_add_float(struct str_parms *str_parms, const char *key,\n                        float value);\n\n// Returns non-zero if the str_parms contains the specified key.\nint str_parms_has_key(struct str_parms *str_parms, const char *key);\n\n// Gets value associated with the specified key (if present), placing it in the buffer\n// pointed to by the out_val parameter.  Returns the length of the returned string value.\n// If 'key' isn't in the parms, then return -ENOENT (-2) and leave 'out_val' untouched.\nint str_parms_get_str(struct str_parms *str_parms, const char *key,\n                      char *out_val, int len);\nint str_parms_get_int(struct str_parms *str_parms, const char *key,\n                      int *out_val);\nint str_parms_get_float(struct str_parms *str_parms, const char *key,\n                        float *out_val);\n\nchar *str_parms_to_str(struct str_parms *str_parms);\n\n/* debug */\nvoid str_parms_dump(struct str_parms *str_parms);\n\n__END_DECLS\n\n#endif /* __CUTILS_STR_PARMS_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/threads.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_CUTILS_THREADS_H\n#define _LIBS_CUTILS_THREADS_H\n\n#include  <sys/types.h>\n\n#if !defined(_WIN32)\n#include <pthread.h>\n#else\n#include <windows.h>\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/***********************************************************************/\n/***********************************************************************/\n/*****                                                             *****/\n/*****         local thread storage                                *****/\n/*****                                                             *****/\n/***********************************************************************/\n/***********************************************************************/\n\nextern pid_t gettid();\n\n#if !defined(_WIN32)\n\ntypedef struct {\n    pthread_mutex_t   lock;\n    int               has_tls;\n    pthread_key_t     tls;\n} thread_store_t;\n\n#define  THREAD_STORE_INITIALIZER  { PTHREAD_MUTEX_INITIALIZER, 0, 0 }\n\n#else // !defined(_WIN32)\n\ntypedef struct {\n    int               lock_init;\n    int               has_tls;\n    DWORD             tls;\n    CRITICAL_SECTION  lock;\n} thread_store_t;\n\n#define  THREAD_STORE_INITIALIZER  { 0, 0, 0, {0, 0, 0, 0, 0, 0} }\n\n#endif // !defined(_WIN32)\n\ntypedef void  (*thread_store_destruct_t)(void*  value);\n\nextern void*  thread_store_get(thread_store_t*  store);\n\nextern void   thread_store_set(thread_store_t*          store,\n                               void*                    value,\n                               thread_store_destruct_t  destroy);\n\n/***********************************************************************/\n/***********************************************************************/\n/*****                                                             *****/\n/*****         mutexes                                             *****/\n/*****                                                             *****/\n/***********************************************************************/\n/***********************************************************************/\n\n#if !defined(_WIN32)\n\ntypedef pthread_mutex_t   mutex_t;\n\n#define  MUTEX_INITIALIZER  PTHREAD_MUTEX_INITIALIZER\n\nstatic __inline__ void  mutex_lock(mutex_t*  lock)\n{\n    pthread_mutex_lock(lock);\n}\nstatic __inline__ void  mutex_unlock(mutex_t*  lock)\n{\n    pthread_mutex_unlock(lock);\n}\nstatic __inline__ int  mutex_init(mutex_t*  lock)\n{\n    return pthread_mutex_init(lock, NULL);\n}\nstatic __inline__ void mutex_destroy(mutex_t*  lock)\n{\n    pthread_mutex_destroy(lock);\n}\n\n#else // !defined(_WIN32)\n\ntypedef struct {\n    int                init;\n    CRITICAL_SECTION   lock[1];\n} mutex_t;\n\n#define  MUTEX_INITIALIZER  { 0, {{ NULL, 0, 0, NULL, NULL, 0 }} }\n\nstatic __inline__ void  mutex_lock(mutex_t*  lock)\n{\n    if (!lock->init) {\n        lock->init = 1;\n        InitializeCriticalSection( lock->lock );\n        lock->init = 2;\n    } else while (lock->init != 2)\n        Sleep(10);\n\n    EnterCriticalSection(lock->lock);\n}\n\nstatic __inline__ void  mutex_unlock(mutex_t*  lock)\n{\n    LeaveCriticalSection(lock->lock);\n}\nstatic __inline__ int  mutex_init(mutex_t*  lock)\n{\n    InitializeCriticalSection(lock->lock);\n    lock->init = 2;\n    return 0;\n}\nstatic __inline__ void  mutex_destroy(mutex_t*  lock)\n{\n    if (lock->init) {\n        lock->init = 0;\n        DeleteCriticalSection(lock->lock);\n    }\n}\n#endif // !defined(_WIN32)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _LIBS_CUTILS_THREADS_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/trace.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_CUTILS_TRACE_H\n#define _LIBS_CUTILS_TRACE_H\n\n#include <inttypes.h>\n#include <stdatomic.h>\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <unistd.h>\n\n#include <cutils/compiler.h>\n\n__BEGIN_DECLS\n\n/**\n * The ATRACE_TAG macro can be defined before including this header to trace\n * using one of the tags defined below.  It must be defined to one of the\n * following ATRACE_TAG_* macros.  The trace tag is used to filter tracing in\n * userland to avoid some of the runtime cost of tracing when it is not desired.\n *\n * Defining ATRACE_TAG to be ATRACE_TAG_ALWAYS will result in the tracing always\n * being enabled - this should ONLY be done for debug code, as userland tracing\n * has a performance cost even when the trace is not being recorded.  Defining\n * ATRACE_TAG to be ATRACE_TAG_NEVER or leaving ATRACE_TAG undefined will result\n * in the tracing always being disabled.\n *\n * ATRACE_TAG_HAL should be bitwise ORed with the relevant tags for tracing\n * within a hardware module.  For example a camera hardware module would set:\n * #define ATRACE_TAG  (ATRACE_TAG_CAMERA | ATRACE_TAG_HAL)\n *\n * Keep these in sync with frameworks/base/core/java/android/os/Trace.java.\n */\n#define ATRACE_TAG_NEVER            0       // This tag is never enabled.\n#define ATRACE_TAG_ALWAYS           (1<<0)  // This tag is always enabled.\n#define ATRACE_TAG_GRAPHICS         (1<<1)\n#define ATRACE_TAG_INPUT            (1<<2)\n#define ATRACE_TAG_VIEW             (1<<3)\n#define ATRACE_TAG_WEBVIEW          (1<<4)\n#define ATRACE_TAG_WINDOW_MANAGER   (1<<5)\n#define ATRACE_TAG_ACTIVITY_MANAGER (1<<6)\n#define ATRACE_TAG_SYNC_MANAGER     (1<<7)\n#define ATRACE_TAG_AUDIO            (1<<8)\n#define ATRACE_TAG_VIDEO            (1<<9)\n#define ATRACE_TAG_CAMERA           (1<<10)\n#define ATRACE_TAG_HAL              (1<<11)\n#define ATRACE_TAG_APP              (1<<12)\n#define ATRACE_TAG_RESOURCES        (1<<13)\n#define ATRACE_TAG_DALVIK           (1<<14)\n#define ATRACE_TAG_RS               (1<<15)\n#define ATRACE_TAG_BIONIC           (1<<16)\n#define ATRACE_TAG_POWER            (1<<17)\n#define ATRACE_TAG_LAST             ATRACE_TAG_POWER\n\n// Reserved for initialization.\n#define ATRACE_TAG_NOT_READY        (1LL<<63)\n\n#define ATRACE_TAG_VALID_MASK ((ATRACE_TAG_LAST - 1) | ATRACE_TAG_LAST)\n\n#ifndef ATRACE_TAG\n#define ATRACE_TAG ATRACE_TAG_NEVER\n#elif ATRACE_TAG > ATRACE_TAG_VALID_MASK\n#error ATRACE_TAG must be defined to be one of the tags defined in cutils/trace.h\n#endif\n\n/**\n * Opens the trace file for writing and reads the property for initial tags.\n * The atrace.tags.enableflags property sets the tags to trace.\n * This function should not be explicitly called, the first call to any normal\n * trace function will cause it to be run safely.\n */\nvoid atrace_setup();\n\n/**\n * If tracing is ready, set atrace_enabled_tags to the system property\n * debug.atrace.tags.enableflags. Can be used as a sysprop change callback.\n */\nvoid atrace_update_tags();\n\n/**\n * Set whether the process is debuggable.  By default the process is not\n * considered debuggable.  If the process is not debuggable then application-\n * level tracing is not allowed unless the ro.debuggable system property is\n * set to '1'.\n */\nvoid atrace_set_debuggable(bool debuggable);\n\n/**\n * Set whether tracing is enabled for the current process.  This is used to\n * prevent tracing within the Zygote process.\n */\nvoid atrace_set_tracing_enabled(bool enabled);\n\n/**\n * Flag indicating whether setup has been completed, initialized to 0.\n * Nonzero indicates setup has completed.\n * Note: This does NOT indicate whether or not setup was successful.\n */\nextern atomic_bool atrace_is_ready;\n\n/**\n * Set of ATRACE_TAG flags to trace for, initialized to ATRACE_TAG_NOT_READY.\n * A value of zero indicates setup has failed.\n * Any other nonzero value indicates setup has succeeded, and tracing is on.\n */\nextern uint64_t atrace_enabled_tags;\n\n/**\n * Handle to the kernel's trace buffer, initialized to -1.\n * Any other value indicates setup has succeeded, and is a valid fd for tracing.\n */\nextern int atrace_marker_fd;\n\n/**\n * atrace_init readies the process for tracing by opening the trace_marker file.\n * Calling any trace function causes this to be run, so calling it is optional.\n * This can be explicitly run to avoid setup delay on first trace function.\n */\n#define ATRACE_INIT() atrace_init()\nstatic inline void atrace_init()\n{\n    if (CC_UNLIKELY(!atomic_load_explicit(&atrace_is_ready, memory_order_acquire))) {\n        atrace_setup();\n    }\n}\n\n/**\n * Get the mask of all tags currently enabled.\n * It can be used as a guard condition around more expensive trace calculations.\n * Every trace function calls this, which ensures atrace_init is run.\n */\n#define ATRACE_GET_ENABLED_TAGS() atrace_get_enabled_tags()\nstatic inline uint64_t atrace_get_enabled_tags()\n{\n    atrace_init();\n    return atrace_enabled_tags;\n}\n\n/**\n * Test if a given tag is currently enabled.\n * Returns nonzero if the tag is enabled, otherwise zero.\n * It can be used as a guard condition around more expensive trace calculations.\n */\n#define ATRACE_ENABLED() atrace_is_tag_enabled(ATRACE_TAG)\nstatic inline uint64_t atrace_is_tag_enabled(uint64_t tag)\n{\n    return atrace_get_enabled_tags() & tag;\n}\n\n/**\n * Trace the beginning of a context.  name is used to identify the context.\n * This is often used to time function execution.\n */\n#define ATRACE_BEGIN(name) atrace_begin(ATRACE_TAG, name)\nstatic inline void atrace_begin(uint64_t tag, const char* name)\n{\n    if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {\n        void atrace_begin_body(const char*);\n        atrace_begin_body(name);\n    }\n}\n\n/**\n * Trace the end of a context.\n * This should match up (and occur after) a corresponding ATRACE_BEGIN.\n */\n#define ATRACE_END() atrace_end(ATRACE_TAG)\nstatic inline void atrace_end(uint64_t tag)\n{\n    if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {\n        char c = 'E';\n        write(atrace_marker_fd, &c, 1);\n    }\n}\n\n/**\n * Trace the beginning of an asynchronous event. Unlike ATRACE_BEGIN/ATRACE_END\n * contexts, asynchronous events do not need to be nested. The name describes\n * the event, and the cookie provides a unique identifier for distinguishing\n * simultaneous events. The name and cookie used to begin an event must be\n * used to end it.\n */\n#define ATRACE_ASYNC_BEGIN(name, cookie) \\\n    atrace_async_begin(ATRACE_TAG, name, cookie)\nstatic inline void atrace_async_begin(uint64_t tag, const char* name,\n        int32_t cookie)\n{\n    if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {\n        void atrace_async_begin_body(const char*, int32_t);\n        atrace_async_begin_body(name, cookie);\n    }\n}\n\n/**\n * Trace the end of an asynchronous event.\n * This should have a corresponding ATRACE_ASYNC_BEGIN.\n */\n#define ATRACE_ASYNC_END(name, cookie) atrace_async_end(ATRACE_TAG, name, cookie)\nstatic inline void atrace_async_end(uint64_t tag, const char* name, int32_t cookie)\n{\n    if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {\n        void atrace_async_end_body(const char*, int32_t);\n        atrace_async_end_body(name, cookie);\n    }\n}\n\n/**\n * Traces an integer counter value.  name is used to identify the counter.\n * This can be used to track how a value changes over time.\n */\n#define ATRACE_INT(name, value) atrace_int(ATRACE_TAG, name, value)\nstatic inline void atrace_int(uint64_t tag, const char* name, int32_t value)\n{\n    if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {\n        void atrace_int_body(const char*, int32_t);\n        atrace_int_body(name, value);\n    }\n}\n\n/**\n * Traces a 64-bit integer counter value.  name is used to identify the\n * counter. This can be used to track how a value changes over time.\n */\n#define ATRACE_INT64(name, value) atrace_int64(ATRACE_TAG, name, value)\nstatic inline void atrace_int64(uint64_t tag, const char* name, int64_t value)\n{\n    if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {\n        void atrace_int64_body(const char*, int64_t);\n        atrace_int64_body(name, value);\n    }\n}\n\n__END_DECLS\n\n#endif // _LIBS_CUTILS_TRACE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/cutils/uevent.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CUTILS_UEVENT_H\n#define __CUTILS_UEVENT_H\n\n#include <stdbool.h>\n#include <sys/socket.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nint uevent_open_socket(int buf_sz, bool passcred);\nssize_t uevent_kernel_multicast_recv(int socket, void *buffer, size_t length);\nssize_t uevent_kernel_multicast_uid_recv(int socket, void *buffer, size_t length, uid_t *uid);\nssize_t uevent_kernel_recv(int socket, void *buffer, size_t length, bool require_group, uid_t *uid);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CUTILS_UEVENT_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/event_tag_map.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_CUTILS_EVENTTAGMAP_H\n#define _LIBS_CUTILS_EVENTTAGMAP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define EVENT_TAG_MAP_FILE  \"/system/etc/event-log-tags\"\n\nstruct EventTagMap;\ntypedef struct EventTagMap EventTagMap;\n\n/*\n * Open the specified file as an event log tag map.\n *\n * Returns NULL on failure.\n */\nEventTagMap* android_openEventTagMap(const char* fileName);\n\n/*\n * Close the map.\n */\nvoid android_closeEventTagMap(EventTagMap* map);\n\n/*\n * Look up a tag by index.  Returns the tag string, or NULL if not found.\n */\nconst char* android_lookupEventTag(const EventTagMap* map, int tag);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*_LIBS_CUTILS_EVENTTAGMAP_H*/\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/log.h",
    "content": "/*\n * Copyright (C) 2005-2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// C/C++ logging functions.  See the logging documentation for API details.\n//\n// We'd like these to be available from C code (in case we import some from\n// somewhere), so this has a C interface.\n//\n// The output will be correct when the log file is shared between multiple\n// threads and/or multiple processes so long as the operating system\n// supports O_APPEND.  These calls have mutex-protected data structures\n// and so are NOT reentrant.  Do not use LOG in a signal handler.\n//\n#ifndef _LIBS_LOG_LOG_H\n#define _LIBS_LOG_LOG_H\n\n#include <stdarg.h>\n#include <stdio.h>\n#include <sys/types.h>\n#include <time.h>\n#include <unistd.h>\n\n#include <log/logd.h>\n#include <log/uio.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// ---------------------------------------------------------------------\n\n/*\n * Normally we strip ALOGV (VERBOSE messages) from release builds.\n * You can modify this (for example with \"#define LOG_NDEBUG 0\"\n * at the top of your source file) to change that behavior.\n */\n#ifndef LOG_NDEBUG\n#ifdef NDEBUG\n#define LOG_NDEBUG 1\n#else\n#define LOG_NDEBUG 0\n#endif\n#endif\n\n/*\n * This is the local tag used for the following simplified\n * logging macros.  You can change this preprocessor definition\n * before using the other macros to change the tag.\n */\n#ifndef LOG_TAG\n#define LOG_TAG NULL\n#endif\n\n// ---------------------------------------------------------------------\n\n#ifndef __predict_false\n#define __predict_false(exp) __builtin_expect((exp) != 0, 0)\n#endif\n\n/*\n *      -DLINT_RLOG in sources that you want to enforce that all logging\n * goes to the radio log buffer. If any logging goes to any of the other\n * log buffers, there will be a compile or link error to highlight the\n * problem. This is not a replacement for a full audit of the code since\n * this only catches compiled code, not ifdef'd debug code. Options to\n * defining this, either temporarily to do a spot check, or permanently\n * to enforce, in all the communications trees; We have hopes to ensure\n * that by supplying just the radio log buffer that the communications\n * teams will have their one-stop shop for triaging issues.\n */\n#ifndef LINT_RLOG\n\n/*\n * Simplified macro to send a verbose log message using the current LOG_TAG.\n */\n#ifndef ALOGV\n#define __ALOGV(...) ((void)ALOG(LOG_VERBOSE, LOG_TAG, __VA_ARGS__))\n#if LOG_NDEBUG\n#define ALOGV(...) do { if (0) { __ALOGV(__VA_ARGS__); } } while (0)\n#else\n#define ALOGV(...) __ALOGV(__VA_ARGS__)\n#endif\n#endif\n\n#ifndef ALOGV_IF\n#if LOG_NDEBUG\n#define ALOGV_IF(cond, ...)   ((void)0)\n#else\n#define ALOGV_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)ALOG(LOG_VERBOSE, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n#endif\n\n/*\n * Simplified macro to send a debug log message using the current LOG_TAG.\n */\n#ifndef ALOGD\n#define ALOGD(...) ((void)ALOG(LOG_DEBUG, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef ALOGD_IF\n#define ALOGD_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)ALOG(LOG_DEBUG, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send an info log message using the current LOG_TAG.\n */\n#ifndef ALOGI\n#define ALOGI(...) ((void)ALOG(LOG_INFO, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef ALOGI_IF\n#define ALOGI_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)ALOG(LOG_INFO, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send a warning log message using the current LOG_TAG.\n */\n#ifndef ALOGW\n#define ALOGW(...) ((void)ALOG(LOG_WARN, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef ALOGW_IF\n#define ALOGW_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)ALOG(LOG_WARN, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send an error log message using the current LOG_TAG.\n */\n#ifndef ALOGE\n#define ALOGE(...) ((void)ALOG(LOG_ERROR, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef ALOGE_IF\n#define ALOGE_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)ALOG(LOG_ERROR, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n// ---------------------------------------------------------------------\n\n/*\n * Conditional based on whether the current LOG_TAG is enabled at\n * verbose priority.\n */\n#ifndef IF_ALOGV\n#if LOG_NDEBUG\n#define IF_ALOGV() if (false)\n#else\n#define IF_ALOGV() IF_ALOG(LOG_VERBOSE, LOG_TAG)\n#endif\n#endif\n\n/*\n * Conditional based on whether the current LOG_TAG is enabled at\n * debug priority.\n */\n#ifndef IF_ALOGD\n#define IF_ALOGD() IF_ALOG(LOG_DEBUG, LOG_TAG)\n#endif\n\n/*\n * Conditional based on whether the current LOG_TAG is enabled at\n * info priority.\n */\n#ifndef IF_ALOGI\n#define IF_ALOGI() IF_ALOG(LOG_INFO, LOG_TAG)\n#endif\n\n/*\n * Conditional based on whether the current LOG_TAG is enabled at\n * warn priority.\n */\n#ifndef IF_ALOGW\n#define IF_ALOGW() IF_ALOG(LOG_WARN, LOG_TAG)\n#endif\n\n/*\n * Conditional based on whether the current LOG_TAG is enabled at\n * error priority.\n */\n#ifndef IF_ALOGE\n#define IF_ALOGE() IF_ALOG(LOG_ERROR, LOG_TAG)\n#endif\n\n\n// ---------------------------------------------------------------------\n\n/*\n * Simplified macro to send a verbose system log message using the current LOG_TAG.\n */\n#ifndef SLOGV\n#define __SLOGV(...) \\\n    ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_VERBOSE, LOG_TAG, __VA_ARGS__))\n#if LOG_NDEBUG\n#define SLOGV(...) do { if (0) { __SLOGV(__VA_ARGS__); } } while (0)\n#else\n#define SLOGV(...) __SLOGV(__VA_ARGS__)\n#endif\n#endif\n\n#ifndef SLOGV_IF\n#if LOG_NDEBUG\n#define SLOGV_IF(cond, ...)   ((void)0)\n#else\n#define SLOGV_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_VERBOSE, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n#endif\n\n/*\n * Simplified macro to send a debug system log message using the current LOG_TAG.\n */\n#ifndef SLOGD\n#define SLOGD(...) \\\n    ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_DEBUG, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef SLOGD_IF\n#define SLOGD_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_DEBUG, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send an info system log message using the current LOG_TAG.\n */\n#ifndef SLOGI\n#define SLOGI(...) \\\n    ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_INFO, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef SLOGI_IF\n#define SLOGI_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_INFO, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send a warning system log message using the current LOG_TAG.\n */\n#ifndef SLOGW\n#define SLOGW(...) \\\n    ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_WARN, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef SLOGW_IF\n#define SLOGW_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_WARN, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send an error system log message using the current LOG_TAG.\n */\n#ifndef SLOGE\n#define SLOGE(...) \\\n    ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_ERROR, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef SLOGE_IF\n#define SLOGE_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_SYSTEM, ANDROID_LOG_ERROR, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n#endif /* !LINT_RLOG */\n\n// ---------------------------------------------------------------------\n\n/*\n * Simplified macro to send a verbose radio log message using the current LOG_TAG.\n */\n#ifndef RLOGV\n#define __RLOGV(...) \\\n    ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_VERBOSE, LOG_TAG, __VA_ARGS__))\n#if LOG_NDEBUG\n#define RLOGV(...) do { if (0) { __RLOGV(__VA_ARGS__); } } while (0)\n#else\n#define RLOGV(...) __RLOGV(__VA_ARGS__)\n#endif\n#endif\n\n#ifndef RLOGV_IF\n#if LOG_NDEBUG\n#define RLOGV_IF(cond, ...)   ((void)0)\n#else\n#define RLOGV_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_VERBOSE, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n#endif\n\n/*\n * Simplified macro to send a debug radio log message using the current LOG_TAG.\n */\n#ifndef RLOGD\n#define RLOGD(...) \\\n    ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_DEBUG, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef RLOGD_IF\n#define RLOGD_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_DEBUG, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send an info radio log message using the current LOG_TAG.\n */\n#ifndef RLOGI\n#define RLOGI(...) \\\n    ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_INFO, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef RLOGI_IF\n#define RLOGI_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_INFO, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send a warning radio log message using the current LOG_TAG.\n */\n#ifndef RLOGW\n#define RLOGW(...) \\\n    ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_WARN, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef RLOGW_IF\n#define RLOGW_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_WARN, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n/*\n * Simplified macro to send an error radio log message using the current LOG_TAG.\n */\n#ifndef RLOGE\n#define RLOGE(...) \\\n    ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_ERROR, LOG_TAG, __VA_ARGS__))\n#endif\n\n#ifndef RLOGE_IF\n#define RLOGE_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)__android_log_buf_print(LOG_ID_RADIO, ANDROID_LOG_ERROR, LOG_TAG, __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n\n// ---------------------------------------------------------------------\n\n/*\n * Log a fatal error.  If the given condition fails, this stops program\n * execution like a normal assertion, but also generating the given message.\n * It is NOT stripped from release builds.  Note that the condition test\n * is -inverted- from the normal assert() semantics.\n */\n#ifndef LOG_ALWAYS_FATAL_IF\n#define LOG_ALWAYS_FATAL_IF(cond, ...) \\\n    ( (__predict_false(cond)) \\\n    ? ((void)android_printAssert(#cond, LOG_TAG, ## __VA_ARGS__)) \\\n    : (void)0 )\n#endif\n\n#ifndef LOG_ALWAYS_FATAL\n#define LOG_ALWAYS_FATAL(...) \\\n    ( ((void)android_printAssert(NULL, LOG_TAG, ## __VA_ARGS__)) )\n#endif\n\n/*\n * Versions of LOG_ALWAYS_FATAL_IF and LOG_ALWAYS_FATAL that\n * are stripped out of release builds.\n */\n#if LOG_NDEBUG\n\n#ifndef LOG_FATAL_IF\n#define LOG_FATAL_IF(cond, ...) ((void)0)\n#endif\n#ifndef LOG_FATAL\n#define LOG_FATAL(...) ((void)0)\n#endif\n\n#else\n\n#ifndef LOG_FATAL_IF\n#define LOG_FATAL_IF(cond, ...) LOG_ALWAYS_FATAL_IF(cond, ## __VA_ARGS__)\n#endif\n#ifndef LOG_FATAL\n#define LOG_FATAL(...) LOG_ALWAYS_FATAL(__VA_ARGS__)\n#endif\n\n#endif\n\n/*\n * Assertion that generates a log message when the assertion fails.\n * Stripped out of release builds.  Uses the current LOG_TAG.\n */\n#ifndef ALOG_ASSERT\n#define ALOG_ASSERT(cond, ...) LOG_FATAL_IF(!(cond), ## __VA_ARGS__)\n//#define ALOG_ASSERT(cond) LOG_FATAL_IF(!(cond), \"Assertion failed: \" #cond)\n#endif\n\n// ---------------------------------------------------------------------\n\n/*\n * Basic log message macro.\n *\n * Example:\n *  ALOG(LOG_WARN, NULL, \"Failed with error %d\", errno);\n *\n * The second argument may be NULL or \"\" to indicate the \"global\" tag.\n */\n#ifndef ALOG\n#define ALOG(priority, tag, ...) \\\n    LOG_PRI(ANDROID_##priority, tag, __VA_ARGS__)\n#endif\n\n/*\n * Log macro that allows you to specify a number for the priority.\n */\n#ifndef LOG_PRI\n#define LOG_PRI(priority, tag, ...) \\\n    android_printLog(priority, tag, __VA_ARGS__)\n#endif\n\n/*\n * Log macro that allows you to pass in a varargs (\"args\" is a va_list).\n */\n#ifndef LOG_PRI_VA\n#define LOG_PRI_VA(priority, tag, fmt, args) \\\n    android_vprintLog(priority, NULL, tag, fmt, args)\n#endif\n\n/*\n * Conditional given a desired logging priority and tag.\n */\n#ifndef IF_ALOG\n#define IF_ALOG(priority, tag) \\\n    if (android_testLog(ANDROID_##priority, tag))\n#endif\n\n// ---------------------------------------------------------------------\n\n/*\n * Event logging.\n */\n\n/*\n * Event log entry types.  These must match up with the declarations in\n * java/android/android/util/EventLog.java.\n */\ntypedef enum {\n    EVENT_TYPE_INT      = 0,\n    EVENT_TYPE_LONG     = 1,\n    EVENT_TYPE_STRING   = 2,\n    EVENT_TYPE_LIST     = 3,\n    EVENT_TYPE_FLOAT    = 4,\n} AndroidEventLogType;\n#define sizeof_AndroidEventLogType sizeof(typeof_AndroidEventLogType)\n#define typeof_AndroidEventLogType unsigned char\n\n#ifndef LOG_EVENT_INT\n#define LOG_EVENT_INT(_tag, _value) {                                       \\\n        int intBuf = _value;                                                \\\n        (void) android_btWriteLog(_tag, EVENT_TYPE_INT, &intBuf,            \\\n            sizeof(intBuf));                                                \\\n    }\n#endif\n#ifndef LOG_EVENT_LONG\n#define LOG_EVENT_LONG(_tag, _value) {                                      \\\n        long long longBuf = _value;                                         \\\n        (void) android_btWriteLog(_tag, EVENT_TYPE_LONG, &longBuf,          \\\n            sizeof(longBuf));                                               \\\n    }\n#endif\n#ifndef LOG_EVENT_FLOAT\n#define LOG_EVENT_FLOAT(_tag, _value) {                                     \\\n        float floatBuf = _value;                                            \\\n        (void) android_btWriteLog(_tag, EVENT_TYPE_FLOAT, &floatBuf,        \\\n            sizeof(floatBuf));                                              \\\n    }\n#endif\n#ifndef LOG_EVENT_STRING\n#define LOG_EVENT_STRING(_tag, _value)                                      \\\n        (void) __android_log_bswrite(_tag, _value);\n#endif\n/* TODO: something for LIST */\n\n/*\n * ===========================================================================\n *\n * The stuff in the rest of this file should not be used directly.\n */\n\n#define android_printLog(prio, tag, fmt...) \\\n    __android_log_print(prio, tag, fmt)\n\n#define android_vprintLog(prio, cond, tag, fmt...) \\\n    __android_log_vprint(prio, tag, fmt)\n\n/* XXX Macros to work around syntax errors in places where format string\n * arg is not passed to ALOG_ASSERT, LOG_ALWAYS_FATAL or LOG_ALWAYS_FATAL_IF\n * (happens only in debug builds).\n */\n\n/* Returns 2nd arg.  Used to substitute default value if caller's vararg list\n * is empty.\n */\n#define __android_second(dummy, second, ...)     second\n\n/* If passed multiple args, returns ',' followed by all but 1st arg, otherwise\n * returns nothing.\n */\n#define __android_rest(first, ...)               , ## __VA_ARGS__\n\n#define android_printAssert(cond, tag, fmt...) \\\n    __android_log_assert(cond, tag, \\\n        __android_second(0, ## fmt, NULL) __android_rest(fmt))\n\n#define android_writeLog(prio, tag, text) \\\n    __android_log_write(prio, tag, text)\n\n#define android_bWriteLog(tag, payload, len) \\\n    __android_log_bwrite(tag, payload, len)\n#define android_btWriteLog(tag, type, payload, len) \\\n    __android_log_btwrite(tag, type, payload, len)\n\n#define android_errorWriteLog(tag, subTag) \\\n    __android_log_error_write(tag, subTag, -1, NULL, 0)\n\n#define android_errorWriteWithInfoLog(tag, subTag, uid, data, dataLen) \\\n    __android_log_error_write(tag, subTag, uid, data, dataLen)\n\n/*\n *    IF_ALOG uses android_testLog, but IF_ALOG can be overridden.\n *    android_testLog will remain constant in its purpose as a wrapper\n *        for Android logging filter policy, and can be subject to\n *        change. It can be reused by the developers that override\n *        IF_ALOG as a convenient means to reimplement their policy\n *        over Android.\n */\n#if LOG_NDEBUG /* Production */\n#define android_testLog(prio, tag) \\\n    (__android_log_is_loggable(prio, tag, ANDROID_LOG_DEBUG) != 0)\n#else\n#define android_testLog(prio, tag) \\\n    (__android_log_is_loggable(prio, tag, ANDROID_LOG_VERBOSE) != 0)\n#endif\n\n// TODO: remove these prototypes and their users\n#define android_writevLog(vec,num) do{}while(0)\n#define android_write1Log(str,len) do{}while (0)\n#define android_setMinPriority(tag, prio) do{}while(0)\n//#define android_logToCallback(func) do{}while(0)\n#define android_logToFile(tag, file) (0)\n#define android_logToFd(tag, fd) (0)\n\n#ifndef log_id_t_defined\n#define log_id_t_defined\n\ntypedef enum log_id {\n    LOG_ID_MIN = 0,\n\n#ifndef LINT_RLOG\n    LOG_ID_MAIN = 0,\n#endif\n    LOG_ID_RADIO = 1,\n#ifndef LINT_RLOG\n    LOG_ID_EVENTS = 2,\n    LOG_ID_SYSTEM = 3,\n    LOG_ID_CRASH = 4,\n    LOG_ID_KERNEL = 5,\n#endif\n\n    LOG_ID_MAX\n} log_id_t;\n#endif\n#define sizeof_log_id_t sizeof(typeof_log_id_t)\n#define typeof_log_id_t unsigned char\n\n/*\n * Use the per-tag properties \"log.tag.<tagname>\" to generate a runtime\n * result of non-zero to expose a log.\n */\nint __android_log_is_loggable(int prio, const char *tag, int def);\n\nint __android_log_error_write(int tag, const char *subTag, int32_t uid, const char *data,\n                              uint32_t dataLen);\n\n/*\n * Send a simple string to the log.\n */\nint __android_log_buf_write(int bufID, int prio, const char *tag, const char *text);\nint __android_log_buf_print(int bufID, int prio, const char *tag, const char *fmt, ...)\n#if defined(__GNUC__)\n    __attribute__((__format__(printf, 4, 5)))\n#endif\n    ;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _LIBS_LOG_LOG_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/log_read.h",
    "content": "/*\n * Copyright (C) 2013-2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_LOG_LOG_READ_H\n#define _LIBS_LOG_LOG_READ_H\n\n#include <stdint.h>\n#include <time.h>\n\n/* struct log_time is a wire-format variant of struct timespec */\n#define NS_PER_SEC 1000000000ULL\n\n#ifdef __cplusplus\n\n// NB: do NOT define a copy constructor. This will result in structure\n// no longer being compatible with pass-by-value which is desired\n// efficient behavior. Also, pass-by-reference breaks C/C++ ABI.\nstruct log_time {\npublic:\n    uint32_t tv_sec; // good to Feb 5 2106\n    uint32_t tv_nsec;\n\n    static const uint32_t tv_sec_max = 0xFFFFFFFFUL;\n    static const uint32_t tv_nsec_max = 999999999UL;\n\n    log_time(const timespec &T)\n    {\n        tv_sec = T.tv_sec;\n        tv_nsec = T.tv_nsec;\n    }\n    log_time(uint32_t sec, uint32_t nsec)\n    {\n        tv_sec = sec;\n        tv_nsec = nsec;\n    }\n    static const timespec EPOCH;\n    log_time()\n    {\n    }\n    log_time(clockid_t id)\n    {\n        timespec T;\n        clock_gettime(id, &T);\n        tv_sec = T.tv_sec;\n        tv_nsec = T.tv_nsec;\n    }\n    log_time(const char *T)\n    {\n        const uint8_t *c = (const uint8_t *) T;\n        tv_sec = c[0] | (c[1] << 8) | (c[2] << 16) | (c[3] << 24);\n        tv_nsec = c[4] | (c[5] << 8) | (c[6] << 16) | (c[7] << 24);\n    }\n\n    // timespec\n    bool operator== (const timespec &T) const\n    {\n        return (tv_sec == static_cast<uint32_t>(T.tv_sec))\n            && (tv_nsec == static_cast<uint32_t>(T.tv_nsec));\n    }\n    bool operator!= (const timespec &T) const\n    {\n        return !(*this == T);\n    }\n    bool operator< (const timespec &T) const\n    {\n        return (tv_sec < static_cast<uint32_t>(T.tv_sec))\n            || ((tv_sec == static_cast<uint32_t>(T.tv_sec))\n                && (tv_nsec < static_cast<uint32_t>(T.tv_nsec)));\n    }\n    bool operator>= (const timespec &T) const\n    {\n        return !(*this < T);\n    }\n    bool operator> (const timespec &T) const\n    {\n        return (tv_sec > static_cast<uint32_t>(T.tv_sec))\n            || ((tv_sec == static_cast<uint32_t>(T.tv_sec))\n                && (tv_nsec > static_cast<uint32_t>(T.tv_nsec)));\n    }\n    bool operator<= (const timespec &T) const\n    {\n        return !(*this > T);\n    }\n    log_time operator-= (const timespec &T);\n    log_time operator- (const timespec &T) const\n    {\n        log_time local(*this);\n        return local -= T;\n    }\n    log_time operator+= (const timespec &T);\n    log_time operator+ (const timespec &T) const\n    {\n        log_time local(*this);\n        return local += T;\n    }\n\n    // log_time\n    bool operator== (const log_time &T) const\n    {\n        return (tv_sec == T.tv_sec) && (tv_nsec == T.tv_nsec);\n    }\n    bool operator!= (const log_time &T) const\n    {\n        return !(*this == T);\n    }\n    bool operator< (const log_time &T) const\n    {\n        return (tv_sec < T.tv_sec)\n            || ((tv_sec == T.tv_sec) && (tv_nsec < T.tv_nsec));\n    }\n    bool operator>= (const log_time &T) const\n    {\n        return !(*this < T);\n    }\n    bool operator> (const log_time &T) const\n    {\n        return (tv_sec > T.tv_sec)\n            || ((tv_sec == T.tv_sec) && (tv_nsec > T.tv_nsec));\n    }\n    bool operator<= (const log_time &T) const\n    {\n        return !(*this > T);\n    }\n    log_time operator-= (const log_time &T);\n    log_time operator- (const log_time &T) const\n    {\n        log_time local(*this);\n        return local -= T;\n    }\n    log_time operator+= (const log_time &T);\n    log_time operator+ (const log_time &T) const\n    {\n        log_time local(*this);\n        return local += T;\n    }\n\n    uint64_t nsec() const\n    {\n        return static_cast<uint64_t>(tv_sec) * NS_PER_SEC + tv_nsec;\n    }\n\n    static const char default_format[];\n\n    // Add %#q for the fraction of a second to the standard library functions\n    char *strptime(const char *s, const char *format = default_format);\n} __attribute__((__packed__));\n\n#else\n\ntypedef struct log_time {\n    uint32_t tv_sec;\n    uint32_t tv_nsec;\n} __attribute__((__packed__)) log_time;\n\n#endif\n\n#endif /* define _LIBS_LOG_LOG_READ_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/logd.h",
    "content": "/*\n * Copyright (C) 2009 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _ANDROID_CUTILS_LOGD_H\n#define _ANDROID_CUTILS_LOGD_H\n\n/* the stable/frozen log-related definitions have been\n * moved to this header, which is exposed by the NDK\n */\n#include <android/log.h>\n\n/* the rest is only used internally by the system */\n#if !defined(_WIN32)\n#include <pthread.h>\n#endif\n#include <stdarg.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <sys/types.h>\n#include <time.h>\n#include <unistd.h>\n\n#include <log/uio.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nint __android_log_bwrite(int32_t tag, const void *payload, size_t len);\nint __android_log_btwrite(int32_t tag, char type, const void *payload,\n    size_t len);\nint __android_log_bswrite(int32_t tag, const char *payload);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _LOGD_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/logger.h",
    "content": "/*\n**\n** Copyright 2007-2014, The Android Open Source Project\n**\n** This file is dual licensed.  It may be redistributed and/or modified\n** under the terms of the Apache 2.0 License OR version 2 of the GNU\n** General Public License.\n*/\n\n#ifndef _LIBS_LOG_LOGGER_H\n#define _LIBS_LOG_LOGGER_H\n\n#include <stdint.h>\n#include <log/log.h>\n#include <log/log_read.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * The userspace structure for version 1 of the logger_entry ABI.\n * This structure is returned to userspace by the kernel logger\n * driver unless an upgrade to a newer ABI version is requested.\n */\nstruct logger_entry {\n    uint16_t    len;    /* length of the payload */\n    uint16_t    __pad;  /* no matter what, we get 2 bytes of padding */\n    int32_t     pid;    /* generating process's pid */\n    int32_t     tid;    /* generating process's tid */\n    int32_t     sec;    /* seconds since Epoch */\n    int32_t     nsec;   /* nanoseconds */\n    char        msg[0]; /* the entry's payload */\n} __attribute__((__packed__));\n\n/*\n * The userspace structure for version 2 of the logger_entry ABI.\n * This structure is returned to userspace if ioctl(LOGGER_SET_VERSION)\n * is called with version==2; or used with the user space log daemon.\n */\nstruct logger_entry_v2 {\n    uint16_t    len;       /* length of the payload */\n    uint16_t    hdr_size;  /* sizeof(struct logger_entry_v2) */\n    int32_t     pid;       /* generating process's pid */\n    int32_t     tid;       /* generating process's tid */\n    int32_t     sec;       /* seconds since Epoch */\n    int32_t     nsec;      /* nanoseconds */\n    uint32_t    euid;      /* effective UID of logger */\n    char        msg[0];    /* the entry's payload */\n} __attribute__((__packed__));\n\nstruct logger_entry_v3 {\n    uint16_t    len;       /* length of the payload */\n    uint16_t    hdr_size;  /* sizeof(struct logger_entry_v3) */\n    int32_t     pid;       /* generating process's pid */\n    int32_t     tid;       /* generating process's tid */\n    int32_t     sec;       /* seconds since Epoch */\n    int32_t     nsec;      /* nanoseconds */\n    uint32_t    lid;       /* log id of the payload */\n    char        msg[0];    /* the entry's payload */\n} __attribute__((__packed__));\n\n/*\n * The maximum size of the log entry payload that can be\n * written to the logger. An attempt to write more than\n * this amount will result in a truncated log entry.\n */\n#define LOGGER_ENTRY_MAX_PAYLOAD\t4076\n\n/*\n * The maximum size of a log entry which can be read from the\n * kernel logger driver. An attempt to read less than this amount\n * may result in read() returning EINVAL.\n */\n#define LOGGER_ENTRY_MAX_LEN\t\t(5*1024)\n\n#define NS_PER_SEC 1000000000ULL\n\nstruct log_msg {\n    union {\n        unsigned char buf[LOGGER_ENTRY_MAX_LEN + 1];\n        struct logger_entry_v3 entry;\n        struct logger_entry_v3 entry_v3;\n        struct logger_entry_v2 entry_v2;\n        struct logger_entry    entry_v1;\n    } __attribute__((aligned(4)));\n#ifdef __cplusplus\n    /* Matching log_time operators */\n    bool operator== (const log_msg &T) const\n    {\n        return (entry.sec == T.entry.sec) && (entry.nsec == T.entry.nsec);\n    }\n    bool operator!= (const log_msg &T) const\n    {\n        return !(*this == T);\n    }\n    bool operator< (const log_msg &T) const\n    {\n        return (entry.sec < T.entry.sec)\n            || ((entry.sec == T.entry.sec)\n             && (entry.nsec < T.entry.nsec));\n    }\n    bool operator>= (const log_msg &T) const\n    {\n        return !(*this < T);\n    }\n    bool operator> (const log_msg &T) const\n    {\n        return (entry.sec > T.entry.sec)\n            || ((entry.sec == T.entry.sec)\n             && (entry.nsec > T.entry.nsec));\n    }\n    bool operator<= (const log_msg &T) const\n    {\n        return !(*this > T);\n    }\n    uint64_t nsec() const\n    {\n        return static_cast<uint64_t>(entry.sec) * NS_PER_SEC + entry.nsec;\n    }\n\n    /* packet methods */\n    log_id_t id()\n    {\n        return (log_id_t) entry.lid;\n    }\n    char *msg()\n    {\n        return entry.hdr_size ? (char *) buf + entry.hdr_size : entry_v1.msg;\n    }\n    unsigned int len()\n    {\n        return (entry.hdr_size ? entry.hdr_size : sizeof(entry_v1)) + entry.len;\n    }\n#endif\n};\n\nstruct logger;\n\nlog_id_t android_logger_get_id(struct logger *logger);\n\nint android_logger_clear(struct logger *logger);\nlong android_logger_get_log_size(struct logger *logger);\nint android_logger_set_log_size(struct logger *logger, unsigned long size);\nlong android_logger_get_log_readable_size(struct logger *logger);\nint android_logger_get_log_version(struct logger *logger);\n\nstruct logger_list;\n\nssize_t android_logger_get_statistics(struct logger_list *logger_list,\n                                      char *buf, size_t len);\nssize_t android_logger_get_prune_list(struct logger_list *logger_list,\n                                      char *buf, size_t len);\nint android_logger_set_prune_list(struct logger_list *logger_list,\n                                  char *buf, size_t len);\n\n#define ANDROID_LOG_RDONLY   O_RDONLY\n#define ANDROID_LOG_WRONLY   O_WRONLY\n#define ANDROID_LOG_RDWR     O_RDWR\n#define ANDROID_LOG_ACCMODE  O_ACCMODE\n#define ANDROID_LOG_NONBLOCK O_NONBLOCK\n#define ANDROID_LOG_PSTORE   0x80000000\n\nstruct logger_list *android_logger_list_alloc(int mode,\n                                              unsigned int tail,\n                                              pid_t pid);\nstruct logger_list *android_logger_list_alloc_time(int mode,\n                                                   log_time start,\n                                                   pid_t pid);\nvoid android_logger_list_free(struct logger_list *logger_list);\n/* In the purest sense, the following two are orthogonal interfaces */\nint android_logger_list_read(struct logger_list *logger_list,\n                             struct log_msg *log_msg);\n\n/* Multiple log_id_t opens */\nstruct logger *android_logger_open(struct logger_list *logger_list,\n                                   log_id_t id);\n#define android_logger_close android_logger_free\n/* Single log_id_t open */\nstruct logger_list *android_logger_list_open(log_id_t id,\n                                             int mode,\n                                             unsigned int tail,\n                                             pid_t pid);\n#define android_logger_list_close android_logger_list_free\n\n/*\n * log_id_t helpers\n */\nlog_id_t android_name_to_log_id(const char *logName);\nconst char *android_log_id_to_name(log_id_t log_id);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _LIBS_LOG_LOGGER_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/logprint.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LOGPRINT_H\n#define _LOGPRINT_H\n\n#include <log/log.h>\n#include <log/logger.h>\n#include <log/event_tag_map.h>\n#include <pthread.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n    FORMAT_OFF = 0,\n    FORMAT_BRIEF,\n    FORMAT_PROCESS,\n    FORMAT_TAG,\n    FORMAT_THREAD,\n    FORMAT_RAW,\n    FORMAT_TIME,\n    FORMAT_THREADTIME,\n    FORMAT_LONG,\n    /* The following three are modifiers to above formats */\n    FORMAT_MODIFIER_COLOR,     /* converts priority to color */\n    FORMAT_MODIFIER_TIME_USEC, /* switches from msec to usec time precision */\n    FORMAT_MODIFIER_PRINTABLE, /* converts non-printable to printable escapes */\n} AndroidLogPrintFormat;\n\ntypedef struct AndroidLogFormat_t AndroidLogFormat;\n\ntypedef struct AndroidLogEntry_t {\n    time_t tv_sec;\n    long tv_nsec;\n    android_LogPriority priority;\n    int32_t pid;\n    int32_t tid;\n    const char * tag;\n    size_t messageLen;\n    const char * message;\n} AndroidLogEntry;\n\nAndroidLogFormat *android_log_format_new();\n\nvoid android_log_format_free(AndroidLogFormat *p_format);\n\n/* currently returns 0 if format is a modifier, 1 if not */\nint android_log_setPrintFormat(AndroidLogFormat *p_format,\n        AndroidLogPrintFormat format);\n\n/**\n * Returns FORMAT_OFF on invalid string\n */\nAndroidLogPrintFormat android_log_formatFromString(const char *s);\n\n/**\n * filterExpression: a single filter expression\n * eg \"AT:d\"\n *\n * returns 0 on success and -1 on invalid expression\n *\n * Assumes single threaded execution\n *\n */\n\nint android_log_addFilterRule(AndroidLogFormat *p_format,\n        const char *filterExpression);\n\n\n/**\n * filterString: a whitespace-separated set of filter expressions\n * eg \"AT:d *:i\"\n *\n * returns 0 on success and -1 on invalid expression\n *\n * Assumes single threaded execution\n *\n */\n\nint android_log_addFilterString(AndroidLogFormat *p_format,\n        const char *filterString);\n\n\n/**\n * returns 1 if this log line should be printed based on its priority\n * and tag, and 0 if it should not\n */\nint android_log_shouldPrintLine (\n        AndroidLogFormat *p_format, const char *tag, android_LogPriority pri);\n\n\n/**\n * Splits a wire-format buffer into an AndroidLogEntry\n * entry allocated by caller. Pointers will point directly into buf\n *\n * Returns 0 on success and -1 on invalid wire format (entry will be\n * in unspecified state)\n */\nint android_log_processLogBuffer(struct logger_entry *buf,\n                                 AndroidLogEntry *entry);\n\n/**\n * Like android_log_processLogBuffer, but for binary logs.\n *\n * If \"map\" is non-NULL, it will be used to convert the log tag number\n * into a string.\n */\nint android_log_processBinaryLogBuffer(struct logger_entry *buf,\n    AndroidLogEntry *entry, const EventTagMap* map, char* messageBuf,\n    int messageBufLen);\n\n\n/**\n * Formats a log message into a buffer\n *\n * Uses defaultBuffer if it can, otherwise malloc()'s a new buffer\n * If return value != defaultBuffer, caller must call free()\n * Returns NULL on malloc error\n */\n\nchar *android_log_formatLogLine (\n    AndroidLogFormat *p_format,\n    char *defaultBuffer,\n    size_t defaultBufferSize,\n    const AndroidLogEntry *p_line,\n    size_t *p_outLength);\n\n\n/**\n * Either print or do not print log line, based on filter\n *\n * Assumes single threaded execution\n *\n */\nint android_log_printLogLine(\n    AndroidLogFormat *p_format,\n    int fd,\n    const AndroidLogEntry *entry);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /*_LOGPRINT_H*/\n"
  },
  {
    "path": "phonelibs/android_system_core/include/log/uio.h",
    "content": "/*\n * Copyright (C) 2007-2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_CUTILS_UIO_H\n#define _LIBS_CUTILS_UIO_H\n\n#if !defined(_WIN32)\n\n#include <sys/uio.h>\n\n#else\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n//\n// Implementation of sys/uio.h for Win32.\n//\n\n#include <stddef.h>\n\nstruct iovec {\n    void*  iov_base;\n    size_t iov_len;\n};\n\nextern int  readv( int  fd, struct iovec*  vecs, int  count );\nextern int  writev( int  fd, const struct iovec*  vecs, int  count );\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n\n#endif /* _LIBS_UTILS_UIO_H */\n\n"
  },
  {
    "path": "phonelibs/android_system_core/include/system/camera.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_CORE_INCLUDE_ANDROID_CAMERA_H\n#define SYSTEM_CORE_INCLUDE_ANDROID_CAMERA_H\n\n#include <stdint.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n#include <cutils/native_handle.h>\n#include <hardware/hardware.h>\n#include <hardware/gralloc.h>\n\n__BEGIN_DECLS\n\n/**\n * A set of bit masks for specifying how the received preview frames are\n * handled before the previewCallback() call.\n *\n * The least significant 3 bits of an \"int\" value are used for this purpose:\n *\n * ..... 0 0 0\n *       ^ ^ ^\n *       | | |---------> determine whether the callback is enabled or not\n *       | |-----------> determine whether the callback is one-shot or not\n *       |-------------> determine whether the frame is copied out or not\n *\n * WARNING: When a frame is sent directly without copying, it is the frame\n * receiver's responsiblity to make sure that the frame data won't get\n * corrupted by subsequent preview frames filled by the camera. This flag is\n * recommended only when copying out data brings significant performance price\n * and the handling/processing of the received frame data is always faster than\n * the preview frame rate so that data corruption won't occur.\n *\n * For instance,\n * 1. 0x00 disables the callback. In this case, copy out and one shot bits\n *    are ignored.\n * 2. 0x01 enables a callback without copying out the received frames. A\n *    typical use case is the Camcorder application to avoid making costly\n *    frame copies.\n * 3. 0x05 is enabling a callback with frame copied out repeatedly. A typical\n *    use case is the Camera application.\n * 4. 0x07 is enabling a callback with frame copied out only once. A typical\n *    use case is the Barcode scanner application.\n */\n\nenum {\n    CAMERA_FRAME_CALLBACK_FLAG_ENABLE_MASK = 0x01,\n    CAMERA_FRAME_CALLBACK_FLAG_ONE_SHOT_MASK = 0x02,\n    CAMERA_FRAME_CALLBACK_FLAG_COPY_OUT_MASK = 0x04,\n    /** Typical use cases */\n    CAMERA_FRAME_CALLBACK_FLAG_NOOP = 0x00,\n    CAMERA_FRAME_CALLBACK_FLAG_CAMCORDER = 0x01,\n    CAMERA_FRAME_CALLBACK_FLAG_CAMERA = 0x05,\n    CAMERA_FRAME_CALLBACK_FLAG_BARCODE_SCANNER = 0x07\n};\n\n/** msgType in notifyCallback and dataCallback functions */\nenum {\n    CAMERA_MSG_ERROR = 0x0001,            // notifyCallback\n    CAMERA_MSG_SHUTTER = 0x0002,          // notifyCallback\n    CAMERA_MSG_FOCUS = 0x0004,            // notifyCallback\n    CAMERA_MSG_ZOOM = 0x0008,             // notifyCallback\n    CAMERA_MSG_PREVIEW_FRAME = 0x0010,    // dataCallback\n    CAMERA_MSG_VIDEO_FRAME = 0x0020,      // data_timestamp_callback\n    CAMERA_MSG_POSTVIEW_FRAME = 0x0040,   // dataCallback\n    CAMERA_MSG_RAW_IMAGE = 0x0080,        // dataCallback\n    CAMERA_MSG_COMPRESSED_IMAGE = 0x0100, // dataCallback\n    CAMERA_MSG_RAW_IMAGE_NOTIFY = 0x0200, // dataCallback\n    // Preview frame metadata. This can be combined with\n    // CAMERA_MSG_PREVIEW_FRAME in dataCallback. For example, the apps can\n    // request FRAME and METADATA. Or the apps can request only FRAME or only\n    // METADATA.\n    CAMERA_MSG_PREVIEW_METADATA = 0x0400, // dataCallback\n    // Notify on autofocus start and stop. This is useful in continuous\n    // autofocus - FOCUS_MODE_CONTINUOUS_VIDEO and FOCUS_MODE_CONTINUOUS_PICTURE.\n    CAMERA_MSG_FOCUS_MOVE = 0x0800,       // notifyCallback\n    CAMERA_MSG_VENDOR_START = 0x1000,\n    CAMERA_MSG_STATS_DATA = CAMERA_MSG_VENDOR_START,\n    CAMERA_MSG_META_DATA = 0x2000,\n    CAMERA_MSG_VENDOR_END = 0x8000,\n    CAMERA_MSG_ALL_MSGS = 0xFFFF\n};\n\n/** meta data type in CameraMetaDataCallback */\nenum {\n    CAMERA_META_DATA_ASD = 0x001,    //ASD data\n    CAMERA_META_DATA_FD = 0x002,     //FD/FP data\n    CAMERA_META_DATA_HDR = 0x003,    //Auto HDR data\n};\n\n/** cmdType in sendCommand functions */\nenum {\n    CAMERA_CMD_START_SMOOTH_ZOOM = 1,\n    CAMERA_CMD_STOP_SMOOTH_ZOOM = 2,\n\n    /**\n     * Set the clockwise rotation of preview display (setPreviewDisplay) in\n     * degrees. This affects the preview frames and the picture displayed after\n     * snapshot. This method is useful for portrait mode applications. Note\n     * that preview display of front-facing cameras is flipped horizontally\n     * before the rotation, that is, the image is reflected along the central\n     * vertical axis of the camera sensor. So the users can see themselves as\n     * looking into a mirror.\n     *\n     * This does not affect the order of byte array of\n     * CAMERA_MSG_PREVIEW_FRAME, CAMERA_MSG_VIDEO_FRAME,\n     * CAMERA_MSG_POSTVIEW_FRAME, CAMERA_MSG_RAW_IMAGE, or\n     * CAMERA_MSG_COMPRESSED_IMAGE. This is allowed to be set during preview\n     * since API level 14.\n     */\n    CAMERA_CMD_SET_DISPLAY_ORIENTATION = 3,\n\n    /**\n     * cmdType to disable/enable shutter sound. In sendCommand passing arg1 =\n     * 0 will disable, while passing arg1 = 1 will enable the shutter sound.\n     */\n    CAMERA_CMD_ENABLE_SHUTTER_SOUND = 4,\n\n    /* cmdType to play recording sound */\n    CAMERA_CMD_PLAY_RECORDING_SOUND = 5,\n\n    /**\n     * Start the face detection. This should be called after preview is started.\n     * The camera will notify the listener of CAMERA_MSG_FACE and the detected\n     * faces in the preview frame. The detected faces may be the same as the\n     * previous ones. Apps should call CAMERA_CMD_STOP_FACE_DETECTION to stop\n     * the face detection. This method is supported if CameraParameters\n     * KEY_MAX_NUM_HW_DETECTED_FACES or KEY_MAX_NUM_SW_DETECTED_FACES is\n     * bigger than 0. Hardware and software face detection should not be running\n     * at the same time. If the face detection has started, apps should not send\n     * this again.\n     *\n     * In hardware face detection mode, CameraParameters KEY_WHITE_BALANCE,\n     * KEY_FOCUS_AREAS and KEY_METERING_AREAS have no effect.\n     *\n     * arg1 is the face detection type. It can be CAMERA_FACE_DETECTION_HW or\n     * CAMERA_FACE_DETECTION_SW. If the type of face detection requested is not\n     * supported, the HAL must return BAD_VALUE.\n     */\n    CAMERA_CMD_START_FACE_DETECTION = 6,\n\n    /**\n     * Stop the face detection.\n     */\n    CAMERA_CMD_STOP_FACE_DETECTION = 7,\n\n    /**\n     * Enable/disable focus move callback (CAMERA_MSG_FOCUS_MOVE). Passing\n     * arg1 = 0 will disable, while passing arg1 = 1 will enable the callback.\n     */\n    CAMERA_CMD_ENABLE_FOCUS_MOVE_MSG = 8,\n\n    /**\n     * Ping camera service to see if camera hardware is released.\n     *\n     * When any camera method returns error, the client can use ping command\n     * to see if the camera has been taken away by other clients. If the result\n     * is NO_ERROR, it means the camera hardware is not released. If the result\n     * is not NO_ERROR, the camera has been released and the existing client\n     * can silently finish itself or show a dialog.\n     */\n    CAMERA_CMD_PING = 9,\n\n    /**\n     * Configure the number of video buffers used for recording. The intended\n     * video buffer count for recording is passed as arg1, which must be\n     * greater than 0. This command must be sent before recording is started.\n     * This command returns INVALID_OPERATION error if it is sent after video\n     * recording is started, or the command is not supported at all. This\n     * command also returns a BAD_VALUE error if the intended video buffer\n     * count is non-positive or too big to be realized.\n     */\n    CAMERA_CMD_SET_VIDEO_BUFFER_COUNT = 10,\n\n    /**\n     * Configure an explicit format to use for video recording metadata mode.\n     * This can be used to switch the format from the\n     * default IMPLEMENTATION_DEFINED gralloc format to some other\n     * device-supported format, and the default dataspace from the BT_709 color\n     * space to some other device-supported dataspace. arg1 is the HAL pixel\n     * format, and arg2 is the HAL dataSpace. This command returns\n     * INVALID_OPERATION error if it is sent after video recording is started,\n     * or the command is not supported at all.\n     *\n     * If the gralloc format is set to a format other than\n     * IMPLEMENTATION_DEFINED, then HALv3 devices will use gralloc usage flags\n     * of SW_READ_OFTEN.\n     */\n#ifndef CAMERA_VENDOR_L_COMPAT\n    CAMERA_CMD_SET_VIDEO_FORMAT = 11,\n\n    CAMERA_CMD_VENDOR_START = 20,\n    /**\n     * Commands to enable/disable preview histogram\n     *\n     * Based on user's input to enable/disable histogram from the camera\n     * UI, send the appropriate command to the HAL to turn on/off the histogram\n     * stats and start sending the data to the application.\n     */\n    CAMERA_CMD_HISTOGRAM_ON = CAMERA_CMD_VENDOR_START,\n    CAMERA_CMD_HISTOGRAM_OFF = CAMERA_CMD_VENDOR_START + 1,\n    CAMERA_CMD_HISTOGRAM_SEND_DATA  = CAMERA_CMD_VENDOR_START + 2,\n    CAMERA_CMD_LONGSHOT_ON = CAMERA_CMD_VENDOR_START + 3,\n    CAMERA_CMD_LONGSHOT_OFF = CAMERA_CMD_VENDOR_START + 4,\n    CAMERA_CMD_STOP_LONGSHOT = CAMERA_CMD_VENDOR_START + 5,\n    CAMERA_CMD_METADATA_ON = CAMERA_CMD_VENDOR_START + 6,\n    CAMERA_CMD_METADATA_OFF = CAMERA_CMD_VENDOR_START + 7,\n    CAMERA_CMD_VENDOR_END = 200,\n#else\n\n    /**\n     * Values used by older HALs, provided as an option for compatibility\n     */\n    CAMERA_CMD_HISTOGRAM_ON     = 11,\n    CAMERA_CMD_HISTOGRAM_OFF     = 12,\n    CAMERA_CMD_HISTOGRAM_SEND_DATA  = 13,\n    CAMERA_CMD_LONGSHOT_ON = 14,\n    CAMERA_CMD_LONGSHOT_OFF = 15,\n    CAMERA_CMD_STOP_LONGSHOT = 16,\n    CAMERA_CMD_METADATA_ON = 100,\n    CAMERA_CMD_METADATA_OFF = 101,\n    CAMERA_CMD_SET_VIDEO_FORMAT = 102,\n#endif\n};\n\n/** camera fatal errors */\nenum {\n    CAMERA_ERROR_UNKNOWN = 1,\n    /**\n     * Camera was released because another client has connected to the camera.\n     * The original client should call Camera::disconnect immediately after\n     * getting this notification. Otherwise, the camera will be released by\n     * camera service in a short time. The client should not call any method\n     * (except disconnect and sending CAMERA_CMD_PING) after getting this.\n     */\n    CAMERA_ERROR_RELEASED = 2,\n    CAMERA_ERROR_SERVER_DIED = 100\n};\n\nenum {\n    /** The facing of the camera is opposite to that of the screen. */\n    CAMERA_FACING_BACK = 0,\n    /** The facing of the camera is the same as that of the screen. */\n    CAMERA_FACING_FRONT = 1,\n    /**\n     * The facing of the camera is not fixed relative to the screen.\n     * The cameras with this facing are external cameras, e.g. USB cameras.\n     */\n    CAMERA_FACING_EXTERNAL = 2\n};\n\nenum {\n    /** Hardware face detection. It does not use much CPU. */\n    CAMERA_FACE_DETECTION_HW = 0,\n    /**\n     * Software face detection. It uses some CPU. Applications must use\n     * Camera.setPreviewTexture for preview in this mode.\n     */\n    CAMERA_FACE_DETECTION_SW = 1\n};\n\n/**\n * The information of a face from camera face detection.\n */\ntypedef struct camera_face {\n    /**\n     * Bounds of the face [left, top, right, bottom]. (-1000, -1000) represents\n     * the top-left of the camera field of view, and (1000, 1000) represents the\n     * bottom-right of the field of view. The width and height cannot be 0 or\n     * negative. This is supported by both hardware and software face detection.\n     *\n     * The direction is relative to the sensor orientation, that is, what the\n     * sensor sees. The direction is not affected by the rotation or mirroring\n     * of CAMERA_CMD_SET_DISPLAY_ORIENTATION.\n     */\n    int32_t rect[4];\n\n    /**\n     * The confidence level of the face. The range is 1 to 100. 100 is the\n     * highest confidence. This is supported by both hardware and software\n     * face detection.\n     */\n    int32_t score;\n\n    /**\n     * An unique id per face while the face is visible to the tracker. If\n     * the face leaves the field-of-view and comes back, it will get a new\n     * id. If the value is 0, id is not supported.\n     */\n    int32_t id;\n\n    /**\n     * The coordinates of the center of the left eye. The range is -1000 to\n     * 1000. -2000, -2000 if this is not supported.\n     */\n    int32_t left_eye[2];\n\n    /**\n     * The coordinates of the center of the right eye. The range is -1000 to\n     * 1000. -2000, -2000 if this is not supported.\n     */\n    int32_t right_eye[2];\n\n    /**\n     * The coordinates of the center of the mouth. The range is -1000 to 1000.\n     * -2000, -2000 if this is not supported.\n     */\n    int32_t mouth[2];\n    int32_t smile_degree;\n    int32_t smile_score;\n    int32_t blink_detected;\n    int32_t face_recognised;\n    int32_t gaze_angle;\n    int32_t updown_dir;\n    int32_t leftright_dir;\n    int32_t roll_dir;\n    int32_t left_right_gaze;\n    int32_t top_bottom_gaze;\n    int32_t leye_blink;\n    int32_t reye_blink;\n\n} camera_face_t;\n\n/**\n * The information of a data type received in a camera frame.\n */\ntypedef enum {\n    /** Data buffer */\n    CAMERA_FRAME_DATA_BUF = 0x000,\n    /** File descriptor */\n    CAMERA_FRAME_DATA_FD = 0x100\n} camera_frame_data_type_t;\n\n/**\n * The metadata of the frame data.\n */\ntypedef struct camera_frame_metadata {\n    /**\n     * The number of detected faces in the frame.\n     */\n    int32_t number_of_faces;\n\n    /**\n     * An array of the detected faces. The length is number_of_faces.\n     */\n    camera_face_t *faces;\n} camera_frame_metadata_t;\n\n__END_DECLS\n\n#endif /* SYSTEM_CORE_INCLUDE_ANDROID_CAMERA_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/system/graphics.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_CORE_INCLUDE_ANDROID_GRAPHICS_H\n#define SYSTEM_CORE_INCLUDE_ANDROID_GRAPHICS_H\n\n#include <stdint.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * If the HAL needs to create service threads to handle graphics related\n * tasks, these threads need to run at HAL_PRIORITY_URGENT_DISPLAY priority\n * if they can block the main rendering thread in any way.\n *\n * the priority of the current thread can be set with:\n *\n *      #include <sys/resource.h>\n *      setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);\n *\n */\n\n#define HAL_PRIORITY_URGENT_DISPLAY     (-8)\n\n/**\n * pixel format definitions\n */\n\nenum {\n    /*\n     * \"linear\" color pixel formats:\n     *\n     * When used with ANativeWindow, the dataSpace field describes the color\n     * space of the buffer.\n     *\n     * The color space determines, for example, if the formats are linear or\n     * gamma-corrected; or whether any special operations are performed when\n     * reading or writing into a buffer in one of these formats.\n     */\n    HAL_PIXEL_FORMAT_RGBA_8888          = 1,\n    HAL_PIXEL_FORMAT_RGBX_8888          = 2,\n    HAL_PIXEL_FORMAT_RGB_888            = 3,\n    HAL_PIXEL_FORMAT_RGB_565            = 4,\n    HAL_PIXEL_FORMAT_BGRA_8888          = 5,\n\n    /*\n     * 0x100 - 0x1FF\n     *\n     * This range is reserved for pixel formats that are specific to the HAL\n     * implementation.  Implementations can use any value in this range to\n     * communicate video pixel formats between their HAL modules.  These formats\n     * must not have an alpha channel.  Additionally, an EGLimage created from a\n     * gralloc buffer of one of these formats must be supported for use with the\n     * GL_OES_EGL_image_external OpenGL ES extension.\n     */\n\n    /*\n     * Android YUV format:\n     *\n     * This format is exposed outside of the HAL to software decoders and\n     * applications.  EGLImageKHR must support it in conjunction with the\n     * OES_EGL_image_external extension.\n     *\n     * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed\n     * by (W/2) x (H/2) Cr and Cb planes.\n     *\n     * This format assumes\n     * - an even width\n     * - an even height\n     * - a horizontal stride multiple of 16 pixels\n     * - a vertical stride equal to the height\n     *\n     *   y_size = stride * height\n     *   c_stride = ALIGN(stride/2, 16)\n     *   c_size = c_stride * height/2\n     *   size = y_size + c_size * 2\n     *   cr_offset = y_size\n     *   cb_offset = y_size + c_size\n     *\n     * When used with ANativeWindow, the dataSpace field describes the color\n     * space of the buffer.\n     */\n    HAL_PIXEL_FORMAT_YV12   = 0x32315659, // YCrCb 4:2:0 Planar\n\n\n    /*\n     * Android Y8 format:\n     *\n     * This format is exposed outside of the HAL to the framework.\n     * The expected gralloc usage flags are SW_* and HW_CAMERA_*,\n     * and no other HW_ flags will be used.\n     *\n     * Y8 is a YUV planar format comprised of a WxH Y plane,\n     * with each pixel being represented by 8 bits.\n     *\n     * It is equivalent to just the Y plane from YV12.\n     *\n     * This format assumes\n     * - an even width\n     * - an even height\n     * - a horizontal stride multiple of 16 pixels\n     * - a vertical stride equal to the height\n     *\n     *   size = stride * height\n     *\n     * When used with ANativeWindow, the dataSpace field describes the color\n     * space of the buffer.\n     */\n    HAL_PIXEL_FORMAT_Y8     = 0x20203859,\n\n    /*\n     * Android Y16 format:\n     *\n     * This format is exposed outside of the HAL to the framework.\n     * The expected gralloc usage flags are SW_* and HW_CAMERA_*,\n     * and no other HW_ flags will be used.\n     *\n     * Y16 is a YUV planar format comprised of a WxH Y plane,\n     * with each pixel being represented by 16 bits.\n     *\n     * It is just like Y8, but has double the bits per pixel (little endian).\n     *\n     * This format assumes\n     * - an even width\n     * - an even height\n     * - a horizontal stride multiple of 16 pixels\n     * - a vertical stride equal to the height\n     * - strides are specified in pixels, not in bytes\n     *\n     *   size = stride * height * 2\n     *\n     * When used with ANativeWindow, the dataSpace field describes the color\n     * space of the buffer, except that dataSpace field\n     * HAL_DATASPACE_DEPTH indicates that this buffer contains a depth\n     * image where each sample is a distance value measured by a depth camera,\n     * plus an associated confidence value.\n     */\n    HAL_PIXEL_FORMAT_Y16    = 0x20363159,\n\n    /*\n     * Android RAW sensor format:\n     *\n     * This format is exposed outside of the camera HAL to applications.\n     *\n     * RAW16 is a single-channel, 16-bit, little endian format, typically\n     * representing raw Bayer-pattern images from an image sensor, with minimal\n     * processing.\n     *\n     * The exact pixel layout of the data in the buffer is sensor-dependent, and\n     * needs to be queried from the camera device.\n     *\n     * Generally, not all 16 bits are used; more common values are 10 or 12\n     * bits. If not all bits are used, the lower-order bits are filled first.\n     * All parameters to interpret the raw data (black and white points,\n     * color space, etc) must be queried from the camera device.\n     *\n     * This format assumes\n     * - an even width\n     * - an even height\n     * - a horizontal stride multiple of 16 pixels\n     * - a vertical stride equal to the height\n     * - strides are specified in pixels, not in bytes\n     *\n     *   size = stride * height * 2\n     *\n     * This format must be accepted by the gralloc module when used with the\n     * following usage flags:\n     *    - GRALLOC_USAGE_HW_CAMERA_*\n     *    - GRALLOC_USAGE_SW_*\n     *    - GRALLOC_USAGE_RENDERSCRIPT\n     *\n     * When used with ANativeWindow, the dataSpace should be\n     * HAL_DATASPACE_ARBITRARY, as raw image sensor buffers require substantial\n     * extra metadata to define.\n     */\n    HAL_PIXEL_FORMAT_RAW16 = 0x20,\n\n    /*\n     * Android RAW10 format:\n     *\n     * This format is exposed outside of the camera HAL to applications.\n     *\n     * RAW10 is a single-channel, 10-bit per pixel, densely packed in each row,\n     * unprocessed format, usually representing raw Bayer-pattern images coming from\n     * an image sensor.\n     *\n     * In an image buffer with this format, starting from the first pixel of each\n     * row, each 4 consecutive pixels are packed into 5 bytes (40 bits). Each one\n     * of the first 4 bytes contains the top 8 bits of each pixel, The fifth byte\n     * contains the 2 least significant bits of the 4 pixels, the exact layout data\n     * for each 4 consecutive pixels is illustrated below (Pi[j] stands for the jth\n     * bit of the ith pixel):\n     *\n     *          bit 7                                     bit 0\n     *          =====|=====|=====|=====|=====|=====|=====|=====|\n     * Byte 0: |P0[9]|P0[8]|P0[7]|P0[6]|P0[5]|P0[4]|P0[3]|P0[2]|\n     *         |-----|-----|-----|-----|-----|-----|-----|-----|\n     * Byte 1: |P1[9]|P1[8]|P1[7]|P1[6]|P1[5]|P1[4]|P1[3]|P1[2]|\n     *         |-----|-----|-----|-----|-----|-----|-----|-----|\n     * Byte 2: |P2[9]|P2[8]|P2[7]|P2[6]|P2[5]|P2[4]|P2[3]|P2[2]|\n     *         |-----|-----|-----|-----|-----|-----|-----|-----|\n     * Byte 3: |P3[9]|P3[8]|P3[7]|P3[6]|P3[5]|P3[4]|P3[3]|P3[2]|\n     *         |-----|-----|-----|-----|-----|-----|-----|-----|\n     * Byte 4: |P3[1]|P3[0]|P2[1]|P2[0]|P1[1]|P1[0]|P0[1]|P0[0]|\n     *          ===============================================\n     *\n     * This format assumes\n     * - a width multiple of 4 pixels\n     * - an even height\n     * - a vertical stride equal to the height\n     * - strides are specified in bytes, not in pixels\n     *\n     *   size = stride * height\n     *\n     * When stride is equal to width * (10 / 8), there will be no padding bytes at\n     * the end of each row, the entire image data is densely packed. When stride is\n     * larger than width * (10 / 8), padding bytes will be present at the end of each\n     * row (including the last row).\n     *\n     * This format must be accepted by the gralloc module when used with the\n     * following usage flags:\n     *    - GRALLOC_USAGE_HW_CAMERA_*\n     *    - GRALLOC_USAGE_SW_*\n     *    - GRALLOC_USAGE_RENDERSCRIPT\n     *\n     * When used with ANativeWindow, the dataSpace field should be\n     * HAL_DATASPACE_ARBITRARY, as raw image sensor buffers require substantial\n     * extra metadata to define.\n     */\n    HAL_PIXEL_FORMAT_RAW10 = 0x25,\n\n    /*\n     * Android RAW12 format:\n     *\n     * This format is exposed outside of camera HAL to applications.\n     *\n     * RAW12 is a single-channel, 12-bit per pixel, densely packed in each row,\n     * unprocessed format, usually representing raw Bayer-pattern images coming from\n     * an image sensor.\n     *\n     * In an image buffer with this format, starting from the first pixel of each\n     * row, each two consecutive pixels are packed into 3 bytes (24 bits). The first\n     * and second byte contains the top 8 bits of first and second pixel. The third\n     * byte contains the 4 least significant bits of the two pixels, the exact layout\n     * data for each two consecutive pixels is illustrated below (Pi[j] stands for\n     * the jth bit of the ith pixel):\n     *\n     *           bit 7                                            bit 0\n     *          ======|======|======|======|======|======|======|======|\n     * Byte 0: |P0[11]|P0[10]|P0[ 9]|P0[ 8]|P0[ 7]|P0[ 6]|P0[ 5]|P0[ 4]|\n     *         |------|------|------|------|------|------|------|------|\n     * Byte 1: |P1[11]|P1[10]|P1[ 9]|P1[ 8]|P1[ 7]|P1[ 6]|P1[ 5]|P1[ 4]|\n     *         |------|------|------|------|------|------|------|------|\n     * Byte 2: |P1[ 3]|P1[ 2]|P1[ 1]|P1[ 0]|P0[ 3]|P0[ 2]|P0[ 1]|P0[ 0]|\n     *          =======================================================\n     *\n     * This format assumes:\n     * - a width multiple of 4 pixels\n     * - an even height\n     * - a vertical stride equal to the height\n     * - strides are specified in bytes, not in pixels\n     *\n     *   size = stride * height\n     *\n     * When stride is equal to width * (12 / 8), there will be no padding bytes at\n     * the end of each row, the entire image data is densely packed. When stride is\n     * larger than width * (12 / 8), padding bytes will be present at the end of\n     * each row (including the last row).\n     *\n     * This format must be accepted by the gralloc module when used with the\n     * following usage flags:\n     *    - GRALLOC_USAGE_HW_CAMERA_*\n     *    - GRALLOC_USAGE_SW_*\n     *    - GRALLOC_USAGE_RENDERSCRIPT\n     *\n     * When used with ANativeWindow, the dataSpace field should be\n     * HAL_DATASPACE_ARBITRARY, as raw image sensor buffers require substantial\n     * extra metadata to define.\n     */\n    HAL_PIXEL_FORMAT_RAW12 = 0x26,\n\n    /*\n     * Android opaque RAW format:\n     *\n     * This format is exposed outside of the camera HAL to applications.\n     *\n     * RAW_OPAQUE is a format for unprocessed raw image buffers coming from an\n     * image sensor. The actual structure of buffers of this format is\n     * implementation-dependent.\n     *\n     * This format must be accepted by the gralloc module when used with the\n     * following usage flags:\n     *    - GRALLOC_USAGE_HW_CAMERA_*\n     *    - GRALLOC_USAGE_SW_*\n     *    - GRALLOC_USAGE_RENDERSCRIPT\n     *\n     * When used with ANativeWindow, the dataSpace field should be\n     * HAL_DATASPACE_ARBITRARY, as raw image sensor buffers require substantial\n     * extra metadata to define.\n     */\n    HAL_PIXEL_FORMAT_RAW_OPAQUE = 0x24,\n\n    /*\n     * Android binary blob graphics buffer format:\n     *\n     * This format is used to carry task-specific data which does not have a\n     * standard image structure. The details of the format are left to the two\n     * endpoints.\n     *\n     * A typical use case is for transporting JPEG-compressed images from the\n     * Camera HAL to the framework or to applications.\n     *\n     * Buffers of this format must have a height of 1, and width equal to their\n     * size in bytes.\n     *\n     * When used with ANativeWindow, the mapping of the dataSpace field to\n     * buffer contents for BLOB is as follows:\n     *\n     *  dataSpace value               | Buffer contents\n     * -------------------------------+-----------------------------------------\n     *  HAL_DATASPACE_JFIF            | An encoded JPEG image\n     *  HAL_DATASPACE_DEPTH           | An android_depth_points buffer\n     *  Other                         | Unsupported\n     *\n     */\n    HAL_PIXEL_FORMAT_BLOB = 0x21,\n\n    /*\n     * Android format indicating that the choice of format is entirely up to the\n     * device-specific Gralloc implementation.\n     *\n     * The Gralloc implementation should examine the usage bits passed in when\n     * allocating a buffer with this format, and it should derive the pixel\n     * format from those usage flags.  This format will never be used with any\n     * of the GRALLOC_USAGE_SW_* usage flags.\n     *\n     * If a buffer of this format is to be used as an OpenGL ES texture, the\n     * framework will assume that sampling the texture will always return an\n     * alpha value of 1.0 (i.e. the buffer contains only opaque pixel values).\n     *\n     * When used with ANativeWindow, the dataSpace field describes the color\n     * space of the buffer.\n     */\n    HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED = 0x22,\n\n    /*\n     * Android flexible YCbCr 4:2:0 formats\n     *\n     * This format allows platforms to use an efficient YCbCr/YCrCb 4:2:0\n     * buffer layout, while still describing the general format in a\n     * layout-independent manner.  While called YCbCr, it can be\n     * used to describe formats with either chromatic ordering, as well as\n     * whole planar or semiplanar layouts.\n     *\n     * struct android_ycbcr (below) is the the struct used to describe it.\n     *\n     * This format must be accepted by the gralloc module when\n     * USAGE_SW_WRITE_* or USAGE_SW_READ_* are set.\n     *\n     * This format is locked for use by gralloc's (*lock_ycbcr) method, and\n     * locking with the (*lock) method will return an error.\n     *\n     * When used with ANativeWindow, the dataSpace field describes the color\n     * space of the buffer.\n     */\n    HAL_PIXEL_FORMAT_YCbCr_420_888 = 0x23,\n\n    /*\n     * Android flexible YCbCr 4:2:2 formats\n     *\n     * This format allows platforms to use an efficient YCbCr/YCrCb 4:2:2\n     * buffer layout, while still describing the general format in a\n     * layout-independent manner.  While called YCbCr, it can be\n     * used to describe formats with either chromatic ordering, as well as\n     * whole planar or semiplanar layouts.\n     *\n     * This format is currently only used by SW readable buffers\n     * produced by MediaCodecs, so the gralloc module can ignore this format.\n     */\n    HAL_PIXEL_FORMAT_YCbCr_422_888 = 0x27,\n\n    /*\n     * Android flexible YCbCr 4:4:4 formats\n     *\n     * This format allows platforms to use an efficient YCbCr/YCrCb 4:4:4\n     * buffer layout, while still describing the general format in a\n     * layout-independent manner.  While called YCbCr, it can be\n     * used to describe formats with either chromatic ordering, as well as\n     * whole planar or semiplanar layouts.\n     *\n     * This format is currently only used by SW readable buffers\n     * produced by MediaCodecs, so the gralloc module can ignore this format.\n     */\n    HAL_PIXEL_FORMAT_YCbCr_444_888 = 0x28,\n\n    /*\n     * Android flexible RGB 888 formats\n     *\n     * This format allows platforms to use an efficient RGB/BGR/RGBX/BGRX\n     * buffer layout, while still describing the general format in a\n     * layout-independent manner.  While called RGB, it can be\n     * used to describe formats with either color ordering and optional\n     * padding, as well as whole planar layout.\n     *\n     * This format is currently only used by SW readable buffers\n     * produced by MediaCodecs, so the gralloc module can ignore this format.\n     */\n    HAL_PIXEL_FORMAT_FLEX_RGB_888 = 0x29,\n\n    /*\n     * Android flexible RGBA 8888 formats\n     *\n     * This format allows platforms to use an efficient RGBA/BGRA/ARGB/ABGR\n     * buffer layout, while still describing the general format in a\n     * layout-independent manner.  While called RGBA, it can be\n     * used to describe formats with any of the component orderings, as\n     * well as whole planar layout.\n     *\n     * This format is currently only used by SW readable buffers\n     * produced by MediaCodecs, so the gralloc module can ignore this format.\n     */\n    HAL_PIXEL_FORMAT_FLEX_RGBA_8888 = 0x2A,\n\n    /* Legacy formats (deprecated), used by ImageFormat.java */\n    HAL_PIXEL_FORMAT_YCbCr_422_SP       = 0x10, // NV16\n    HAL_PIXEL_FORMAT_YCrCb_420_SP       = 0x11, // NV21\n    HAL_PIXEL_FORMAT_YCbCr_422_I        = 0x14, // YUY2\n};\n\n/*\n * Structure for describing YCbCr formats for consumption by applications.\n * This is used with HAL_PIXEL_FORMAT_YCbCr_*_888.\n *\n * Buffer chroma subsampling is defined in the format.\n * e.g. HAL_PIXEL_FORMAT_YCbCr_420_888 has subsampling 4:2:0.\n *\n * Buffers must have a 8 bit depth.\n *\n * @y, @cb, and @cr point to the first byte of their respective planes.\n *\n * Stride describes the distance in bytes from the first value of one row of\n * the image to the first value of the next row.  It includes the width of the\n * image plus padding.\n * @ystride is the stride of the luma plane.\n * @cstride is the stride of the chroma planes.\n *\n * @chroma_step is the distance in bytes from one chroma pixel value to the\n * next.  This is 2 bytes for semiplanar (because chroma values are interleaved\n * and each chroma value is one byte) and 1 for planar.\n */\n\nstruct android_ycbcr {\n    void *y;\n    void *cb;\n    void *cr;\n    size_t ystride;\n    size_t cstride;\n    size_t chroma_step;\n\n    /** reserved for future use, set to 0 by gralloc's (*lock_ycbcr)() */\n    uint32_t reserved[8];\n};\n\n/**\n * Structure used to define depth point clouds for format HAL_PIXEL_FORMAT_BLOB\n * with dataSpace value of HAL_DATASPACE_DEPTH.\n * When locking a native buffer of the above format and dataSpace value,\n * the vaddr pointer can be cast to this structure.\n *\n * A variable-length list of (x,y,z, confidence) 3D points, as floats.  (x, y,\n * z) represents a measured point's position, with the coordinate system defined\n * by the data source.  Confidence represents the estimated likelihood that this\n * measurement is correct. It is between 0.f and 1.f, inclusive, with 1.f ==\n * 100% confidence.\n *\n * @num_points is the number of points in the list\n *\n * @xyz_points is the flexible array of floating-point values.\n *   It contains (num_points) * 4 floats.\n *\n *   For example:\n *     android_depth_points d = get_depth_buffer();\n *     struct {\n *       float x; float y; float z; float confidence;\n *     } firstPoint, lastPoint;\n *\n *     firstPoint.x = d.xyzc_points[0];\n *     firstPoint.y = d.xyzc_points[1];\n *     firstPoint.z = d.xyzc_points[2];\n *     firstPoint.confidence = d.xyzc_points[3];\n *     lastPoint.x = d.xyzc_points[(d.num_points - 1) * 4 + 0];\n *     lastPoint.y = d.xyzc_points[(d.num_points - 1) * 4 + 1];\n *     lastPoint.z = d.xyzc_points[(d.num_points - 1) * 4 + 2];\n *     lastPoint.confidence = d.xyzc_points[(d.num_points - 1) * 4 + 3];\n */\n\nstruct android_depth_points {\n    uint32_t num_points;\n\n    /** reserved for future use, set to 0 by gralloc's (*lock)() */\n    uint32_t reserved[8];\n\n    float xyzc_points[];\n};\n\n/**\n * Transformation definitions\n *\n * IMPORTANT NOTE:\n * HAL_TRANSFORM_ROT_90 is applied CLOCKWISE and AFTER HAL_TRANSFORM_FLIP_{H|V}.\n *\n */\n\nenum {\n    /* flip source image horizontally (around the vertical axis) */\n    HAL_TRANSFORM_FLIP_H    = 0x01,\n    /* flip source image vertically (around the horizontal axis)*/\n    HAL_TRANSFORM_FLIP_V    = 0x02,\n    /* rotate source image 90 degrees clockwise */\n    HAL_TRANSFORM_ROT_90    = 0x04,\n    /* rotate source image 180 degrees */\n    HAL_TRANSFORM_ROT_180   = 0x03,\n    /* rotate source image 270 degrees clockwise */\n    HAL_TRANSFORM_ROT_270   = 0x07,\n    /* don't use. see system/window.h */\n    HAL_TRANSFORM_RESERVED  = 0x08,\n};\n\n/**\n * Dataspace Definitions\n * ======================\n *\n * Dataspace is the definition of how pixel values should be interpreted.\n *\n * For many formats, this is the colorspace of the image data, which includes\n * primaries (including white point) and the transfer characteristic function,\n * which describes both gamma curve and numeric range (within the bit depth).\n *\n * Other dataspaces include depth measurement data from a depth camera.\n */\n\ntypedef enum android_dataspace {\n    /*\n     * Default-assumption data space, when not explicitly specified.\n     *\n     * It is safest to assume the buffer is an image with sRGB primaries and\n     * encoding ranges, but the consumer and/or the producer of the data may\n     * simply be using defaults. No automatic gamma transform should be\n     * expected, except for a possible display gamma transform when drawn to a\n     * screen.\n     */\n    HAL_DATASPACE_UNKNOWN = 0x0,\n\n    /*\n     * Arbitrary dataspace with manually defined characteristics.  Definition\n     * for colorspaces or other meaning must be communicated separately.\n     *\n     * This is used when specifying primaries, transfer characteristics,\n     * etc. separately.\n     *\n     * A typical use case is in video encoding parameters (e.g. for H.264),\n     * where a colorspace can have separately defined primaries, transfer\n     * characteristics, etc.\n     */\n    HAL_DATASPACE_ARBITRARY = 0x1,\n\n    /*\n     * RGB Colorspaces\n     * -----------------\n     *\n     * Primaries are given using (x,y) coordinates in the CIE 1931 definition\n     * of x and y specified by ISO 11664-1.\n     *\n     * Transfer characteristics are the opto-electronic transfer characteristic\n     * at the source as a function of linear optical intensity (luminance).\n     */\n\n    /*\n     * sRGB linear encoding:\n     *\n     * The red, green, and blue components are stored in sRGB space, but\n     * are linear, not gamma-encoded.\n     * The RGB primaries and the white point are the same as BT.709.\n     *\n     * The values are encoded using the full range ([0,255] for 8-bit) for all\n     * components.\n     */\n    HAL_DATASPACE_SRGB_LINEAR = 0x200,\n\n    /*\n     * sRGB gamma encoding:\n     *\n     * The red, green and blue components are stored in sRGB space, and\n     * converted to linear space when read, using the standard sRGB to linear\n     * equation:\n     *\n     * Clinear = Csrgb / 12.92                  for Csrgb <= 0.04045\n     *         = (Csrgb + 0.055 / 1.055)^2.4    for Csrgb >  0.04045\n     *\n     * When written the inverse transformation is performed:\n     *\n     * Csrgb = 12.92 * Clinear                  for Clinear <= 0.0031308\n     *       = 1.055 * Clinear^(1/2.4) - 0.055  for Clinear >  0.0031308\n     *\n     *\n     * The alpha component, if present, is always stored in linear space and\n     * is left unmodified when read or written.\n     *\n     * The RGB primaries and the white point are the same as BT.709.\n     *\n     * The values are encoded using the full range ([0,255] for 8-bit) for all\n     * components.\n     *\n     */\n    HAL_DATASPACE_SRGB = 0x201,\n\n    /*\n     * YCbCr Colorspaces\n     * -----------------\n     *\n     * Primaries are given using (x,y) coordinates in the CIE 1931 definition\n     * of x and y specified by ISO 11664-1.\n     *\n     * Transfer characteristics are the opto-electronic transfer characteristic\n     * at the source as a function of linear optical intensity (luminance).\n     */\n\n    /*\n     * JPEG File Interchange Format (JFIF)\n     *\n     * Same model as BT.601-625, but all values (Y, Cb, Cr) range from 0 to 255\n     *\n     * Transfer characteristic curve:\n     *  E = 1.099 * L ^ 0.45 - 0.099, 1.00 >= L >= 0.018\n     *  E = 4.500 L, 0.018 > L >= 0\n     *      L - luminance of image 0 <= L <= 1 for conventional colorimetry\n     *      E - corresponding electrical signal\n     *\n     * Primaries:       x       y\n     *  green           0.290   0.600\n     *  blue            0.150   0.060\n     *  red             0.640   0.330\n     *  white (D65)     0.3127  0.3290\n     */\n    HAL_DATASPACE_JFIF = 0x101,\n\n    /*\n     * ITU-R Recommendation 601 (BT.601) - 625-line\n     *\n     * Standard-definition television, 625 Lines (PAL)\n     *\n     * For 8-bit-depth formats:\n     * Luma (Y) samples should range from 16 to 235, inclusive\n     * Chroma (Cb, Cr) samples should range from 16 to 240, inclusive\n     *\n     * For 10-bit-depth formats:\n     * Luma (Y) samples should range from 64 to 940, inclusive\n     * Chroma (Cb, Cr) samples should range from 64 to 960, inclusive\n     *\n     * Transfer characteristic curve:\n     *  E = 1.099 * L ^ 0.45 - 0.099, 1.00 >= L >= 0.018\n     *  E = 4.500 L, 0.018 > L >= 0\n     *      L - luminance of image 0 <= L <= 1 for conventional colorimetry\n     *      E - corresponding electrical signal\n     *\n     * Primaries:       x       y\n     *  green           0.290   0.600\n     *  blue            0.150   0.060\n     *  red             0.640   0.330\n     *  white (D65)     0.3127  0.3290\n     */\n    HAL_DATASPACE_BT601_625 = 0x102,\n\n    /*\n     * ITU-R Recommendation 601 (BT.601) - 525-line\n     *\n     * Standard-definition television, 525 Lines (NTSC)\n     *\n     * For 8-bit-depth formats:\n     * Luma (Y) samples should range from 16 to 235, inclusive\n     * Chroma (Cb, Cr) samples should range from 16 to 240, inclusive\n     *\n     * For 10-bit-depth formats:\n     * Luma (Y) samples should range from 64 to 940, inclusive\n     * Chroma (Cb, Cr) samples should range from 64 to 960, inclusive\n     *\n     * Transfer characteristic curve:\n     *  E = 1.099 * L ^ 0.45 - 0.099, 1.00 >= L >= 0.018\n     *  E = 4.500 L, 0.018 > L >= 0\n     *      L - luminance of image 0 <= L <= 1 for conventional colorimetry\n     *      E - corresponding electrical signal\n     *\n     * Primaries:       x       y\n     *  green           0.310   0.595\n     *  blue            0.155   0.070\n     *  red             0.630   0.340\n     *  white (D65)     0.3127  0.3290\n     */\n    HAL_DATASPACE_BT601_525 = 0x103,\n\n    /*\n     * ITU-R Recommendation 709 (BT.709)\n     *\n     * High-definition television\n     *\n     * For 8-bit-depth formats:\n     * Luma (Y) samples should range from 16 to 235, inclusive\n     * Chroma (Cb, Cr) samples should range from 16 to 240, inclusive\n     *\n     * For 10-bit-depth formats:\n     * Luma (Y) samples should range from 64 to 940, inclusive\n     * Chroma (Cb, Cr) samples should range from 64 to 960, inclusive\n     *\n     * Primaries:       x       y\n     *  green           0.300   0.600\n     *  blue            0.150   0.060\n     *  red             0.640   0.330\n     *  white (D65)     0.3127  0.3290\n     */\n    HAL_DATASPACE_BT709 = 0x104,\n\n    /*\n     * The buffer contains depth ranging measurements from a depth camera.\n     * This value is valid with formats:\n     *    HAL_PIXEL_FORMAT_Y16: 16-bit samples, consisting of a depth measurement\n     *       and an associated confidence value. The 3 MSBs of the sample make\n     *       up the confidence value, and the low 13 LSBs of the sample make up\n     *       the depth measurement.\n     *       For the confidence section, 0 means 100% confidence, 1 means 0%\n     *       confidence. The mapping to a linear float confidence value between\n     *       0.f and 1.f can be obtained with\n     *         float confidence = (((depthSample >> 13) - 1) & 0x7) / 7.0f;\n     *       The depth measurement can be extracted simply with\n     *         uint16_t range = (depthSample & 0x1FFF);\n     *    HAL_PIXEL_FORMAT_BLOB: A depth point cloud, as\n     *       a variable-length float (x,y,z, confidence) coordinate point list.\n     *       The point cloud will be represented with the android_depth_points\n     *       structure.\n     */\n    HAL_DATASPACE_DEPTH = 0x1000\n\n} android_dataspace_t;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_CORE_INCLUDE_ANDROID_GRAPHICS_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/system/radio.h",
    "content": "/*\n * Copyright (C) 2015 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_RADIO_H\n#define ANDROID_RADIO_H\n\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <sys/cdefs.h>\n#include <sys/types.h>\n\n\n#define RADIO_NUM_BANDS_MAX     16\n#define RADIO_NUM_SPACINGS_MAX  16\n#define RADIO_STRING_LEN_MAX    128\n\n/*\n * Radio hardware module class. A given radio hardware module HAL is of one class\n * only. The platform can not have more than one hardware module of each class.\n * Current version of the framework only supports RADIO_CLASS_AM_FM.\n */\ntypedef enum {\n    RADIO_CLASS_AM_FM = 0,  /* FM (including HD radio) and AM */\n    RADIO_CLASS_SAT   = 1,  /* Satellite Radio */\n    RADIO_CLASS_DT    = 2,  /* Digital Radio (DAB) */\n} radio_class_t;\n\n/* value for field \"type\" of radio band described in struct radio_hal_band_config */\ntypedef enum {\n    RADIO_BAND_AM     = 0,  /* Amplitude Modulation band: LW, MW, SW */\n    RADIO_BAND_FM     = 1,  /* Frequency Modulation band: FM */\n    RADIO_BAND_FM_HD  = 2,  /* FM HD Radio / DRM (IBOC) */\n    RADIO_BAND_AM_HD  = 3,  /* AM HD Radio / DRM (IBOC) */\n} radio_band_t;\n\n/* RDS variant implemented. A struct radio_hal_fm_band_config can list none or several. */\nenum {\n    RADIO_RDS_NONE   = 0x0,\n    RADIO_RDS_WORLD  = 0x01,\n    RADIO_RDS_US     = 0x02,\n};\ntypedef unsigned int radio_rds_t;\n\n/* FM deemphasis variant implemented. A struct radio_hal_fm_band_config can list one or more. */\nenum {\n    RADIO_DEEMPHASIS_50   = 0x1,\n    RADIO_DEEMPHASIS_75   = 0x2,\n};\ntypedef unsigned int radio_deemphasis_t;\n\n/* Region a particular radio band configuration corresponds to. Not used at the HAL.\n * Derived by the framework when converting the band descriptors retrieved from the HAL to\n * individual band descriptors for each supported region. */\ntypedef enum {\n    RADIO_REGION_NONE  = -1,\n    RADIO_REGION_ITU_1 = 0,\n    RADIO_REGION_ITU_2 = 1,\n    RADIO_REGION_OIRT  = 2,\n    RADIO_REGION_JAPAN = 3,\n    RADIO_REGION_KOREA = 4,\n} radio_region_t;\n\n/* scanning direction for scan() and step() tuner APIs */\ntypedef enum {\n    RADIO_DIRECTION_UP,\n    RADIO_DIRECTION_DOWN\n} radio_direction_t;\n\n/* unique handle allocated to a radio module */\ntypedef unsigned int radio_handle_t;\n\n/* Opaque meta data structure used by radio meta data API (see system/radio_metadata.h) */\ntypedef struct radio_medtadata radio_metadata_t;\n\n\n/* Additional attributes for an FM band configuration */\ntypedef struct radio_hal_fm_band_config {\n    radio_deemphasis_t  deemphasis; /* deemphasis variant */\n    bool                stereo;     /* stereo supported */\n    radio_rds_t         rds;        /* RDS variants supported */\n    bool                ta;         /* Traffic Announcement supported */\n    bool                af;         /* Alternate Frequency supported */\n} radio_hal_fm_band_config_t;\n\n/* Additional attributes for an AM band configuration */\ntypedef struct radio_hal_am_band_config {\n    bool                stereo;     /* stereo supported */\n} radio_hal_am_band_config_t;\n\n/* Radio band configuration. Describes a given band supported by the radio module.\n * The HAL can expose only one band per type with the the maximum range supported and all options.\n * THe framework will derive the actual regions were this module can operate and expose separate\n * band configurations for applications to chose from. */\ntypedef struct radio_hal_band_config {\n    radio_band_t type;\n    bool         antenna_connected;\n    unsigned int lower_limit;\n    unsigned int upper_limit;\n    unsigned int num_spacings;\n    unsigned int spacings[RADIO_NUM_SPACINGS_MAX];\n    union {\n        radio_hal_fm_band_config_t fm;\n        radio_hal_am_band_config_t am;\n    };\n} radio_hal_band_config_t;\n\n/* Used internally by the framework to represent a band for s specific region */\ntypedef struct radio_band_config {\n    radio_region_t  region;\n    radio_hal_band_config_t band;\n} radio_band_config_t;\n\n\n/* Exposes properties of a given hardware radio module.\n * NOTE: current framework implementation supports only one audio source (num_audio_sources = 1).\n * The source corresponds to AUDIO_DEVICE_IN_FM_TUNER.\n * If more than one tuner is supported (num_tuners > 1), only one can be connected to the audio\n * source. */\ntypedef struct radio_hal_properties {\n    radio_class_t   class_id;   /* Class of this module. E.g RADIO_CLASS_AM_FM */\n    char            implementor[RADIO_STRING_LEN_MAX];  /* implementor name */\n    char            product[RADIO_STRING_LEN_MAX];  /* product name */\n    char            version[RADIO_STRING_LEN_MAX];  /* product version */\n    char            serial[RADIO_STRING_LEN_MAX];  /* serial number (for subscription services) */\n    unsigned int    num_tuners;     /* number of tuners controllable independently */\n    unsigned int    num_audio_sources; /* number of audio sources driven simultaneously */\n    bool            supports_capture; /* the hardware supports capture of audio source audio HAL */\n    unsigned int    num_bands;      /* number of band descriptors */\n    radio_hal_band_config_t bands[RADIO_NUM_BANDS_MAX]; /* band descriptors */\n} radio_hal_properties_t;\n\n/* Used internally by the framework. Same information as in struct radio_hal_properties plus a\n * unique handle and one band configuration per region. */\ntypedef struct radio_properties {\n    radio_handle_t      handle;\n    radio_class_t       class_id;\n    char                implementor[RADIO_STRING_LEN_MAX];\n    char                product[RADIO_STRING_LEN_MAX];\n    char                version[RADIO_STRING_LEN_MAX];\n    char                serial[RADIO_STRING_LEN_MAX];\n    unsigned int        num_tuners;\n    unsigned int        num_audio_sources;\n    bool                supports_capture;\n    unsigned int        num_bands;\n    radio_band_config_t bands[RADIO_NUM_BANDS_MAX];\n} radio_properties_t;\n\n/* Radio program information. Returned by the HAL with event RADIO_EVENT_TUNED.\n * Contains information on currently tuned channel.\n */\ntypedef struct radio_program_info {\n    unsigned int     channel;   /* current channel. (e.g kHz for band type RADIO_BAND_FM) */\n    unsigned int     sub_channel; /* current sub channel. (used for RADIO_BAND_FM_HD) */\n    bool             tuned;     /* tuned to a program or not */\n    bool             stereo;    /* program is stereo or not */\n    bool             digital;   /* digital program or not (e.g HD Radio program) */\n    unsigned int     signal_strength; /* signal strength from 0 to 100 */\n    radio_metadata_t *metadata; /* non null if meta data are present (e.g PTY, song title ...) */\n} radio_program_info_t;\n\n\n/* Events sent to the framework via the HAL callback. An event can notify the completion of an\n * asynchronous command (configuration, tune, scan ...) or a spontaneous change (antenna connection,\n * failure, AF switching, meta data reception... */\nenum {\n    RADIO_EVENT_HW_FAILURE  = 0,  /* hardware module failure. Requires reopening the tuner */\n    RADIO_EVENT_CONFIG      = 1,  /* configuration change completed */\n    RADIO_EVENT_ANTENNA     = 2,  /* Antenna connected, disconnected */\n    RADIO_EVENT_TUNED       = 3,  /* tune, step, scan completed */\n    RADIO_EVENT_METADATA    = 4,  /* New meta data received */\n    RADIO_EVENT_TA          = 5,  /* Traffic announcement start or stop */\n    RADIO_EVENT_AF_SWITCH   = 6,  /* Switch to Alternate Frequency */\n    // begin framework only events\n    RADIO_EVENT_CONTROL     = 100, /* loss/gain of tuner control */\n    RADIO_EVENT_SERVER_DIED = 101, /* radio service died */\n};\ntypedef unsigned int radio_event_type_t;\n\n/* Event passed to the framework by the HAL callback */\ntypedef struct radio_hal_event {\n    radio_event_type_t  type;       /* event type */\n    int                 status;     /* used by RADIO_EVENT_CONFIG, RADIO_EVENT_TUNED */\n    union {\n        bool                    on;     /* RADIO_EVENT_ANTENNA, RADIO_EVENT_TA */\n        radio_hal_band_config_t config; /* RADIO_EVENT_CONFIG */\n        radio_program_info_t    info;   /* RADIO_EVENT_TUNED, RADIO_EVENT_AF_SWITCH */\n        radio_metadata_t        *metadata; /* RADIO_EVENT_METADATA */\n    };\n} radio_hal_event_t;\n\n/* Used internally by the framework. Same information as in struct radio_hal_event */\ntypedef struct radio_event {\n    radio_event_type_t  type;\n    int                 status;\n    union {\n        bool                    on;\n        radio_band_config_t     config;\n        radio_program_info_t    info;\n        radio_metadata_t        *metadata; /* offset from start of struct when in shared memory */\n    };\n} radio_event_t;\n\n\nstatic radio_rds_t radio_rds_for_region(bool rds, radio_region_t region) {\n    if (!rds)\n        return RADIO_RDS_NONE;\n    switch(region) {\n        case RADIO_REGION_ITU_1:\n        case RADIO_REGION_OIRT:\n        case RADIO_REGION_JAPAN:\n        case RADIO_REGION_KOREA:\n            return RADIO_RDS_WORLD;\n        case RADIO_REGION_ITU_2:\n            return RADIO_RDS_US;\n        default:\n            return RADIO_REGION_NONE;\n    }\n}\n\nstatic radio_deemphasis_t radio_demephasis_for_region(radio_region_t region) {\n    switch(region) {\n        case RADIO_REGION_KOREA:\n        case RADIO_REGION_ITU_2:\n            return RADIO_DEEMPHASIS_75;\n        case RADIO_REGION_ITU_1:\n        case RADIO_REGION_OIRT:\n        case RADIO_REGION_JAPAN:\n        default:\n            return RADIO_DEEMPHASIS_50;\n    }\n}\n\n#endif  // ANDROID_RADIO_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/system/thread_defs.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_THREAD_DEFS_H\n#define ANDROID_THREAD_DEFS_H\n\n#include \"graphics.h\"\n\n#if defined(__cplusplus)\nextern \"C\" {\n#endif\n\nenum {\n    /*\n     * ***********************************************\n     * ** Keep in sync with android.os.Process.java **\n     * ***********************************************\n     *\n     * This maps directly to the \"nice\" priorities we use in Android.\n     * A thread priority should be chosen inverse-proportionally to\n     * the amount of work the thread is expected to do. The more work\n     * a thread will do, the less favorable priority it should get so that\n     * it doesn't starve the system. Threads not behaving properly might\n     * be \"punished\" by the kernel.\n     * Use the levels below when appropriate. Intermediate values are\n     * acceptable, preferably use the {MORE|LESS}_FAVORABLE constants below.\n     */\n    ANDROID_PRIORITY_LOWEST         =  19,\n\n    /* use for background tasks */\n    ANDROID_PRIORITY_BACKGROUND     =  10,\n\n    /* most threads run at normal priority */\n    ANDROID_PRIORITY_NORMAL         =   0,\n\n    /* threads currently running a UI that the user is interacting with */\n    ANDROID_PRIORITY_FOREGROUND     =  -2,\n\n    /* the main UI thread has a slightly more favorable priority */\n    ANDROID_PRIORITY_DISPLAY        =  -4,\n\n    /* ui service treads might want to run at a urgent display (uncommon) */\n    ANDROID_PRIORITY_URGENT_DISPLAY =  HAL_PRIORITY_URGENT_DISPLAY,\n\n    /* all normal audio threads */\n    ANDROID_PRIORITY_AUDIO          = -16,\n\n    /* service audio threads (uncommon) */\n    ANDROID_PRIORITY_URGENT_AUDIO   = -19,\n\n    /* should never be used in practice. regular process might not\n     * be allowed to use this level */\n    ANDROID_PRIORITY_HIGHEST        = -20,\n\n    ANDROID_PRIORITY_DEFAULT        = ANDROID_PRIORITY_NORMAL,\n    ANDROID_PRIORITY_MORE_FAVORABLE = -1,\n    ANDROID_PRIORITY_LESS_FAVORABLE = +1,\n};\n\n#if defined(__cplusplus)\n}\n#endif\n\n#endif /* ANDROID_THREAD_DEFS_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/system/window.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_CORE_INCLUDE_ANDROID_WINDOW_H\n#define SYSTEM_CORE_INCLUDE_ANDROID_WINDOW_H\n\n#include <cutils/native_handle.h>\n#include <errno.h>\n#include <limits.h>\n#include <stdint.h>\n#include <string.h>\n#include <sys/cdefs.h>\n#include <system/graphics.h>\n#include <unistd.h>\n\n#ifndef __UNUSED\n#define __UNUSED __attribute__((__unused__))\n#endif\n#ifndef __deprecated\n#define __deprecated __attribute__((__deprecated__))\n#endif\n\n__BEGIN_DECLS\n\n/*****************************************************************************/\n\n#define ANDROID_NATIVE_MAKE_CONSTANT(a,b,c,d) \\\n    (((unsigned)(a)<<24)|((unsigned)(b)<<16)|((unsigned)(c)<<8)|(unsigned)(d))\n\n#define ANDROID_NATIVE_WINDOW_MAGIC \\\n    ANDROID_NATIVE_MAKE_CONSTANT('_','w','n','d')\n\n#define ANDROID_NATIVE_BUFFER_MAGIC \\\n    ANDROID_NATIVE_MAKE_CONSTANT('_','b','f','r')\n\n// ---------------------------------------------------------------------------\n\n// This #define may be used to conditionally compile device-specific code to\n// support either the prior ANativeWindow interface, which did not pass libsync\n// fences around, or the new interface that does.  This #define is only present\n// when the ANativeWindow interface does include libsync support.\n#define ANDROID_NATIVE_WINDOW_HAS_SYNC 1\n\n// ---------------------------------------------------------------------------\n\ntypedef const native_handle_t* buffer_handle_t;\n\n// ---------------------------------------------------------------------------\n\ntypedef struct android_native_rect_t\n{\n    int32_t left;\n    int32_t top;\n    int32_t right;\n    int32_t bottom;\n} android_native_rect_t;\n\n// ---------------------------------------------------------------------------\n\ntypedef struct android_native_base_t\n{\n    /* a magic value defined by the actual EGL native type */\n    int magic;\n\n    /* the sizeof() of the actual EGL native type */\n    int version;\n\n    void* reserved[4];\n\n    /* reference-counting interface */\n    void (*incRef)(struct android_native_base_t* base);\n    void (*decRef)(struct android_native_base_t* base);\n} android_native_base_t;\n\ntypedef struct ANativeWindowBuffer\n{\n#ifdef __cplusplus\n    ANativeWindowBuffer() {\n        common.magic = ANDROID_NATIVE_BUFFER_MAGIC;\n        common.version = sizeof(ANativeWindowBuffer);\n        memset(common.reserved, 0, sizeof(common.reserved));\n    }\n\n    // Implement the methods that sp<ANativeWindowBuffer> expects so that it\n    // can be used to automatically refcount ANativeWindowBuffer's.\n    void incStrong(const void* /*id*/) const {\n        common.incRef(const_cast<android_native_base_t*>(&common));\n    }\n    void decStrong(const void* /*id*/) const {\n        common.decRef(const_cast<android_native_base_t*>(&common));\n    }\n#endif\n\n    struct android_native_base_t common;\n\n    int width;\n    int height;\n    int stride;\n    int format;\n    int usage;\n\n    void* reserved[2];\n\n    buffer_handle_t handle;\n\n    void* reserved_proc[8];\n} ANativeWindowBuffer_t;\n\n// Old typedef for backwards compatibility.\ntypedef ANativeWindowBuffer_t android_native_buffer_t;\n\n// ---------------------------------------------------------------------------\n\n/* attributes queriable with query() */\nenum {\n    NATIVE_WINDOW_WIDTH     = 0,\n    NATIVE_WINDOW_HEIGHT    = 1,\n    NATIVE_WINDOW_FORMAT    = 2,\n\n    /* The minimum number of buffers that must remain un-dequeued after a buffer\n     * has been queued.  This value applies only if set_buffer_count was used to\n     * override the number of buffers and if a buffer has since been queued.\n     * Users of the set_buffer_count ANativeWindow method should query this\n     * value before calling set_buffer_count.  If it is necessary to have N\n     * buffers simultaneously dequeued as part of the steady-state operation,\n     * and this query returns M then N+M buffers should be requested via\n     * native_window_set_buffer_count.\n     *\n     * Note that this value does NOT apply until a single buffer has been\n     * queued.  In particular this means that it is possible to:\n     *\n     * 1. Query M = min undequeued buffers\n     * 2. Set the buffer count to N + M\n     * 3. Dequeue all N + M buffers\n     * 4. Cancel M buffers\n     * 5. Queue, dequeue, queue, dequeue, ad infinitum\n     */\n    NATIVE_WINDOW_MIN_UNDEQUEUED_BUFFERS = 3,\n\n    /* Check whether queueBuffer operations on the ANativeWindow send the buffer\n     * to the window compositor.  The query sets the returned 'value' argument\n     * to 1 if the ANativeWindow DOES send queued buffers directly to the window\n     * compositor and 0 if the buffers do not go directly to the window\n     * compositor.\n     *\n     * This can be used to determine whether protected buffer content should be\n     * sent to the ANativeWindow.  Note, however, that a result of 1 does NOT\n     * indicate that queued buffers will be protected from applications or users\n     * capturing their contents.  If that behavior is desired then some other\n     * mechanism (e.g. the GRALLOC_USAGE_PROTECTED flag) should be used in\n     * conjunction with this query.\n     */\n    NATIVE_WINDOW_QUEUES_TO_WINDOW_COMPOSER = 4,\n\n    /* Get the concrete type of a ANativeWindow.  See below for the list of\n     * possible return values.\n     *\n     * This query should not be used outside the Android framework and will\n     * likely be removed in the near future.\n     */\n    NATIVE_WINDOW_CONCRETE_TYPE = 5,\n\n\n    /*\n     * Default width and height of ANativeWindow buffers, these are the\n     * dimensions of the window buffers irrespective of the\n     * NATIVE_WINDOW_SET_BUFFERS_DIMENSIONS call and match the native window\n     * size unless overridden by NATIVE_WINDOW_SET_BUFFERS_USER_DIMENSIONS.\n     */\n    NATIVE_WINDOW_DEFAULT_WIDTH = 6,\n    NATIVE_WINDOW_DEFAULT_HEIGHT = 7,\n\n    /*\n     * transformation that will most-likely be applied to buffers. This is only\n     * a hint, the actual transformation applied might be different.\n     *\n     * INTENDED USE:\n     *\n     * The transform hint can be used by a producer, for instance the GLES\n     * driver, to pre-rotate the rendering such that the final transformation\n     * in the composer is identity. This can be very useful when used in\n     * conjunction with the h/w composer HAL, in situations where it\n     * cannot handle arbitrary rotations.\n     *\n     * 1. Before dequeuing a buffer, the GL driver (or any other ANW client)\n     *    queries the ANW for NATIVE_WINDOW_TRANSFORM_HINT.\n     *\n     * 2. The GL driver overrides the width and height of the ANW to\n     *    account for NATIVE_WINDOW_TRANSFORM_HINT. This is done by querying\n     *    NATIVE_WINDOW_DEFAULT_{WIDTH | HEIGHT}, swapping the dimensions\n     *    according to NATIVE_WINDOW_TRANSFORM_HINT and calling\n     *    native_window_set_buffers_dimensions().\n     *\n     * 3. The GL driver dequeues a buffer of the new pre-rotated size.\n     *\n     * 4. The GL driver renders to the buffer such that the image is\n     *    already transformed, that is applying NATIVE_WINDOW_TRANSFORM_HINT\n     *    to the rendering.\n     *\n     * 5. The GL driver calls native_window_set_transform to apply\n     *    inverse transformation to the buffer it just rendered.\n     *    In order to do this, the GL driver needs\n     *    to calculate the inverse of NATIVE_WINDOW_TRANSFORM_HINT, this is\n     *    done easily:\n     *\n     *        int hintTransform, inverseTransform;\n     *        query(..., NATIVE_WINDOW_TRANSFORM_HINT, &hintTransform);\n     *        inverseTransform = hintTransform;\n     *        if (hintTransform & HAL_TRANSFORM_ROT_90)\n     *            inverseTransform ^= HAL_TRANSFORM_ROT_180;\n     *\n     *\n     * 6. The GL driver queues the pre-transformed buffer.\n     *\n     * 7. The composer combines the buffer transform with the display\n     *    transform.  If the buffer transform happens to cancel out the\n     *    display transform then no rotation is needed.\n     *\n     */\n    NATIVE_WINDOW_TRANSFORM_HINT = 8,\n\n    /*\n     * Boolean that indicates whether the consumer is running more than\n     * one buffer behind the producer.\n     */\n    NATIVE_WINDOW_CONSUMER_RUNNING_BEHIND = 9,\n\n    /*\n     * The consumer gralloc usage bits currently set by the consumer.\n     * The values are defined in hardware/libhardware/include/gralloc.h.\n     */\n    NATIVE_WINDOW_CONSUMER_USAGE_BITS = 10,\n\n    /**\n     * Transformation that will by applied to buffers by the hwcomposer.\n     * This must not be set or checked by producer endpoints, and will\n     * disable the transform hint set in SurfaceFlinger (see\n     * NATIVE_WINDOW_TRANSFORM_HINT).\n     *\n     * INTENDED USE:\n     * Temporary - Please do not use this.  This is intended only to be used\n     * by the camera's LEGACY mode.\n     *\n     * In situations where a SurfaceFlinger client wishes to set a transform\n     * that is not visible to the producer, and will always be applied in the\n     * hardware composer, the client can set this flag with\n     * native_window_set_buffers_sticky_transform.  This can be used to rotate\n     * and flip buffers consumed by hardware composer without actually changing\n     * the aspect ratio of the buffers produced.\n     */\n    NATIVE_WINDOW_STICKY_TRANSFORM = 11,\n\n    /**\n     * The default data space for the buffers as set by the consumer.\n     * The values are defined in graphics.h.\n     */\n    NATIVE_WINDOW_DEFAULT_DATASPACE = 12,\n\n    /*\n     * Returns the age of the contents of the most recently dequeued buffer as\n     * the number of frames that have elapsed since it was last queued. For\n     * example, if the window is double-buffered, the age of any given buffer in\n     * steady state will be 2. If the dequeued buffer has never been queued, its\n     * age will be 0.\n     */\n    NATIVE_WINDOW_BUFFER_AGE = 13,\n};\n\n/* Valid operations for the (*perform)() hook.\n *\n * Values marked as 'deprecated' are supported, but have been superceded by\n * other functionality.\n *\n * Values marked as 'private' should be considered private to the framework.\n * HAL implementation code with access to an ANativeWindow should not use these,\n * as it may not interact properly with the framework's use of the\n * ANativeWindow.\n */\nenum {\n    NATIVE_WINDOW_SET_USAGE                 =  0,\n    NATIVE_WINDOW_CONNECT                   =  1,   /* deprecated */\n    NATIVE_WINDOW_DISCONNECT                =  2,   /* deprecated */\n    NATIVE_WINDOW_SET_CROP                  =  3,   /* private */\n    NATIVE_WINDOW_SET_BUFFER_COUNT          =  4,\n    NATIVE_WINDOW_SET_BUFFERS_GEOMETRY      =  5,   /* deprecated */\n    NATIVE_WINDOW_SET_BUFFERS_TRANSFORM     =  6,\n    NATIVE_WINDOW_SET_BUFFERS_TIMESTAMP     =  7,\n    NATIVE_WINDOW_SET_BUFFERS_DIMENSIONS    =  8,\n    NATIVE_WINDOW_SET_BUFFERS_FORMAT        =  9,\n    NATIVE_WINDOW_SET_SCALING_MODE          = 10,   /* private */\n    NATIVE_WINDOW_LOCK                      = 11,   /* private */\n    NATIVE_WINDOW_UNLOCK_AND_POST           = 12,   /* private */\n    NATIVE_WINDOW_API_CONNECT               = 13,   /* private */\n    NATIVE_WINDOW_API_DISCONNECT            = 14,   /* private */\n    NATIVE_WINDOW_SET_BUFFERS_USER_DIMENSIONS = 15, /* private */\n    NATIVE_WINDOW_SET_POST_TRANSFORM_CROP   = 16,   /* private */\n    NATIVE_WINDOW_SET_BUFFERS_STICKY_TRANSFORM = 17,/* private */\n    NATIVE_WINDOW_SET_SIDEBAND_STREAM       = 18,\n    NATIVE_WINDOW_SET_BUFFERS_DATASPACE     = 19,\n    NATIVE_WINDOW_SET_SURFACE_DAMAGE        = 20,   /* private */\n};\n\n/* parameter for NATIVE_WINDOW_[API_][DIS]CONNECT */\nenum {\n    /* Buffers will be queued by EGL via eglSwapBuffers after being filled using\n     * OpenGL ES.\n     */\n    NATIVE_WINDOW_API_EGL = 1,\n\n    /* Buffers will be queued after being filled using the CPU\n     */\n    NATIVE_WINDOW_API_CPU = 2,\n\n    /* Buffers will be queued by Stagefright after being filled by a video\n     * decoder.  The video decoder can either be a software or hardware decoder.\n     */\n    NATIVE_WINDOW_API_MEDIA = 3,\n\n    /* Buffers will be queued by the the camera HAL.\n     */\n    NATIVE_WINDOW_API_CAMERA = 4,\n};\n\n/* parameter for NATIVE_WINDOW_SET_BUFFERS_TRANSFORM */\nenum {\n    /* flip source image horizontally */\n    NATIVE_WINDOW_TRANSFORM_FLIP_H = HAL_TRANSFORM_FLIP_H ,\n    /* flip source image vertically */\n    NATIVE_WINDOW_TRANSFORM_FLIP_V = HAL_TRANSFORM_FLIP_V,\n    /* rotate source image 90 degrees clock-wise, and is applied after TRANSFORM_FLIP_{H|V} */\n    NATIVE_WINDOW_TRANSFORM_ROT_90 = HAL_TRANSFORM_ROT_90,\n    /* rotate source image 180 degrees */\n    NATIVE_WINDOW_TRANSFORM_ROT_180 = HAL_TRANSFORM_ROT_180,\n    /* rotate source image 270 degrees clock-wise */\n    NATIVE_WINDOW_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_270,\n    /* transforms source by the inverse transform of the screen it is displayed onto. This\n     * transform is applied last */\n    NATIVE_WINDOW_TRANSFORM_INVERSE_DISPLAY = 0x08\n};\n\n/* parameter for NATIVE_WINDOW_SET_SCALING_MODE */\nenum {\n    /* the window content is not updated (frozen) until a buffer of\n     * the window size is received (enqueued)\n     */\n    NATIVE_WINDOW_SCALING_MODE_FREEZE           = 0,\n    /* the buffer is scaled in both dimensions to match the window size */\n    NATIVE_WINDOW_SCALING_MODE_SCALE_TO_WINDOW  = 1,\n    /* the buffer is scaled uniformly such that the smaller dimension\n     * of the buffer matches the window size (cropping in the process)\n     */\n    NATIVE_WINDOW_SCALING_MODE_SCALE_CROP       = 2,\n    /* the window is clipped to the size of the buffer's crop rectangle; pixels\n     * outside the crop rectangle are treated as if they are completely\n     * transparent.\n     */\n    NATIVE_WINDOW_SCALING_MODE_NO_SCALE_CROP    = 3,\n};\n\n/* values returned by the NATIVE_WINDOW_CONCRETE_TYPE query */\nenum {\n    NATIVE_WINDOW_FRAMEBUFFER               = 0, /* FramebufferNativeWindow */\n    NATIVE_WINDOW_SURFACE                   = 1, /* Surface */\n};\n\n/* parameter for NATIVE_WINDOW_SET_BUFFERS_TIMESTAMP\n *\n * Special timestamp value to indicate that timestamps should be auto-generated\n * by the native window when queueBuffer is called.  This is equal to INT64_MIN,\n * defined directly to avoid problems with C99/C++ inclusion of stdint.h.\n */\nstatic const int64_t NATIVE_WINDOW_TIMESTAMP_AUTO = (-9223372036854775807LL-1);\n\nstruct ANativeWindow\n{\n#ifdef __cplusplus\n    ANativeWindow()\n        : flags(0), minSwapInterval(0), maxSwapInterval(0), xdpi(0), ydpi(0)\n    {\n        common.magic = ANDROID_NATIVE_WINDOW_MAGIC;\n        common.version = sizeof(ANativeWindow);\n        memset(common.reserved, 0, sizeof(common.reserved));\n    }\n\n    /* Implement the methods that sp<ANativeWindow> expects so that it\n       can be used to automatically refcount ANativeWindow's. */\n    void incStrong(const void* /*id*/) const {\n        common.incRef(const_cast<android_native_base_t*>(&common));\n    }\n    void decStrong(const void* /*id*/) const {\n        common.decRef(const_cast<android_native_base_t*>(&common));\n    }\n#endif\n\n    struct android_native_base_t common;\n\n    /* flags describing some attributes of this surface or its updater */\n    const uint32_t flags;\n\n    /* min swap interval supported by this updated */\n    const int   minSwapInterval;\n\n    /* max swap interval supported by this updated */\n    const int   maxSwapInterval;\n\n    /* horizontal and vertical resolution in DPI */\n    const float xdpi;\n    const float ydpi;\n\n    /* Some storage reserved for the OEM's driver. */\n    intptr_t    oem[4];\n\n    /*\n     * Set the swap interval for this surface.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int     (*setSwapInterval)(struct ANativeWindow* window,\n                int interval);\n\n    /*\n     * Hook called by EGL to acquire a buffer. After this call, the buffer\n     * is not locked, so its content cannot be modified. This call may block if\n     * no buffers are available.\n     *\n     * The window holds a reference to the buffer between dequeueBuffer and\n     * either queueBuffer or cancelBuffer, so clients only need their own\n     * reference if they might use the buffer after queueing or canceling it.\n     * Holding a reference to a buffer after queueing or canceling it is only\n     * allowed if a specific buffer count has been set.\n     *\n     * Returns 0 on success or -errno on error.\n     *\n     * XXX: This function is deprecated.  It will continue to work for some\n     * time for binary compatibility, but the new dequeueBuffer function that\n     * outputs a fence file descriptor should be used in its place.\n     */\n    int     (*dequeueBuffer_DEPRECATED)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer** buffer);\n\n    /*\n     * hook called by EGL to lock a buffer. This MUST be called before modifying\n     * the content of a buffer. The buffer must have been acquired with\n     * dequeueBuffer first.\n     *\n     * Returns 0 on success or -errno on error.\n     *\n     * XXX: This function is deprecated.  It will continue to work for some\n     * time for binary compatibility, but it is essentially a no-op, and calls\n     * to it should be removed.\n     */\n    int     (*lockBuffer_DEPRECATED)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer* buffer);\n\n    /*\n     * Hook called by EGL when modifications to the render buffer are done.\n     * This unlocks and post the buffer.\n     *\n     * The window holds a reference to the buffer between dequeueBuffer and\n     * either queueBuffer or cancelBuffer, so clients only need their own\n     * reference if they might use the buffer after queueing or canceling it.\n     * Holding a reference to a buffer after queueing or canceling it is only\n     * allowed if a specific buffer count has been set.\n     *\n     * Buffers MUST be queued in the same order than they were dequeued.\n     *\n     * Returns 0 on success or -errno on error.\n     *\n     * XXX: This function is deprecated.  It will continue to work for some\n     * time for binary compatibility, but the new queueBuffer function that\n     * takes a fence file descriptor should be used in its place (pass a value\n     * of -1 for the fence file descriptor if there is no valid one to pass).\n     */\n    int     (*queueBuffer_DEPRECATED)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer* buffer);\n\n    /*\n     * hook used to retrieve information about the native window.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int     (*query)(const struct ANativeWindow* window,\n                int what, int* value);\n\n    /*\n     * hook used to perform various operations on the surface.\n     * (*perform)() is a generic mechanism to add functionality to\n     * ANativeWindow while keeping backward binary compatibility.\n     *\n     * DO NOT CALL THIS HOOK DIRECTLY.  Instead, use the helper functions\n     * defined below.\n     *\n     * (*perform)() returns -ENOENT if the 'what' parameter is not supported\n     * by the surface's implementation.\n     *\n     * See above for a list of valid operations, such as\n     * NATIVE_WINDOW_SET_USAGE or NATIVE_WINDOW_CONNECT\n     */\n    int     (*perform)(struct ANativeWindow* window,\n                int operation, ... );\n\n    /*\n     * Hook used to cancel a buffer that has been dequeued.\n     * No synchronization is performed between dequeue() and cancel(), so\n     * either external synchronization is needed, or these functions must be\n     * called from the same thread.\n     *\n     * The window holds a reference to the buffer between dequeueBuffer and\n     * either queueBuffer or cancelBuffer, so clients only need their own\n     * reference if they might use the buffer after queueing or canceling it.\n     * Holding a reference to a buffer after queueing or canceling it is only\n     * allowed if a specific buffer count has been set.\n     *\n     * XXX: This function is deprecated.  It will continue to work for some\n     * time for binary compatibility, but the new cancelBuffer function that\n     * takes a fence file descriptor should be used in its place (pass a value\n     * of -1 for the fence file descriptor if there is no valid one to pass).\n     */\n    int     (*cancelBuffer_DEPRECATED)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer* buffer);\n\n    /*\n     * Hook called by EGL to acquire a buffer. This call may block if no\n     * buffers are available.\n     *\n     * The window holds a reference to the buffer between dequeueBuffer and\n     * either queueBuffer or cancelBuffer, so clients only need their own\n     * reference if they might use the buffer after queueing or canceling it.\n     * Holding a reference to a buffer after queueing or canceling it is only\n     * allowed if a specific buffer count has been set.\n     *\n     * The libsync fence file descriptor returned in the int pointed to by the\n     * fenceFd argument will refer to the fence that must signal before the\n     * dequeued buffer may be written to.  A value of -1 indicates that the\n     * caller may access the buffer immediately without waiting on a fence.  If\n     * a valid file descriptor is returned (i.e. any value except -1) then the\n     * caller is responsible for closing the file descriptor.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int     (*dequeueBuffer)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer** buffer, int* fenceFd);\n\n    /*\n     * Hook called by EGL when modifications to the render buffer are done.\n     * This unlocks and post the buffer.\n     *\n     * The window holds a reference to the buffer between dequeueBuffer and\n     * either queueBuffer or cancelBuffer, so clients only need their own\n     * reference if they might use the buffer after queueing or canceling it.\n     * Holding a reference to a buffer after queueing or canceling it is only\n     * allowed if a specific buffer count has been set.\n     *\n     * The fenceFd argument specifies a libsync fence file descriptor for a\n     * fence that must signal before the buffer can be accessed.  If the buffer\n     * can be accessed immediately then a value of -1 should be used.  The\n     * caller must not use the file descriptor after it is passed to\n     * queueBuffer, and the ANativeWindow implementation is responsible for\n     * closing it.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int     (*queueBuffer)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer* buffer, int fenceFd);\n\n    /*\n     * Hook used to cancel a buffer that has been dequeued.\n     * No synchronization is performed between dequeue() and cancel(), so\n     * either external synchronization is needed, or these functions must be\n     * called from the same thread.\n     *\n     * The window holds a reference to the buffer between dequeueBuffer and\n     * either queueBuffer or cancelBuffer, so clients only need their own\n     * reference if they might use the buffer after queueing or canceling it.\n     * Holding a reference to a buffer after queueing or canceling it is only\n     * allowed if a specific buffer count has been set.\n     *\n     * The fenceFd argument specifies a libsync fence file decsriptor for a\n     * fence that must signal before the buffer can be accessed.  If the buffer\n     * can be accessed immediately then a value of -1 should be used.\n     *\n     * Note that if the client has not waited on the fence that was returned\n     * from dequeueBuffer, that same fence should be passed to cancelBuffer to\n     * ensure that future uses of the buffer are preceded by a wait on that\n     * fence.  The caller must not use the file descriptor after it is passed\n     * to cancelBuffer, and the ANativeWindow implementation is responsible for\n     * closing it.\n     *\n     * Returns 0 on success or -errno on error.\n     */\n    int     (*cancelBuffer)(struct ANativeWindow* window,\n                struct ANativeWindowBuffer* buffer, int fenceFd);\n};\n\n /* Backwards compatibility: use ANativeWindow (struct ANativeWindow in C).\n  * android_native_window_t is deprecated.\n  */\ntypedef struct ANativeWindow ANativeWindow;\ntypedef struct ANativeWindow android_native_window_t __deprecated;\n\n/*\n *  native_window_set_usage(..., usage)\n *  Sets the intended usage flags for the next buffers\n *  acquired with (*lockBuffer)() and on.\n *  By default (if this function is never called), a usage of\n *      GRALLOC_USAGE_HW_RENDER | GRALLOC_USAGE_HW_TEXTURE\n *  is assumed.\n *  Calling this function will usually cause following buffers to be\n *  reallocated.\n */\n\nstatic inline int native_window_set_usage(\n        struct ANativeWindow* window, int usage)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_USAGE, usage);\n}\n\n/* deprecated. Always returns 0. Don't call. */\nstatic inline int native_window_connect(\n        struct ANativeWindow* window __UNUSED, int api __UNUSED) __deprecated;\n\nstatic inline int native_window_connect(\n        struct ANativeWindow* window __UNUSED, int api __UNUSED) {\n    return 0;\n}\n\n/* deprecated. Always returns 0. Don't call. */\nstatic inline int native_window_disconnect(\n        struct ANativeWindow* window __UNUSED, int api __UNUSED) __deprecated;\n\nstatic inline int native_window_disconnect(\n        struct ANativeWindow* window __UNUSED, int api __UNUSED) {\n    return 0;\n}\n\n/*\n * native_window_set_crop(..., crop)\n * Sets which region of the next queued buffers needs to be considered.\n * Depending on the scaling mode, a buffer's crop region is scaled and/or\n * cropped to match the surface's size.  This function sets the crop in\n * pre-transformed buffer pixel coordinates.\n *\n * The specified crop region applies to all buffers queued after it is called.\n *\n * If 'crop' is NULL, subsequently queued buffers won't be cropped.\n *\n * An error is returned if for instance the crop region is invalid, out of the\n * buffer's bound or if the window is invalid.\n */\nstatic inline int native_window_set_crop(\n        struct ANativeWindow* window,\n        android_native_rect_t const * crop)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_CROP, crop);\n}\n\n/*\n * native_window_set_post_transform_crop(..., crop)\n * Sets which region of the next queued buffers needs to be considered.\n * Depending on the scaling mode, a buffer's crop region is scaled and/or\n * cropped to match the surface's size.  This function sets the crop in\n * post-transformed pixel coordinates.\n *\n * The specified crop region applies to all buffers queued after it is called.\n *\n * If 'crop' is NULL, subsequently queued buffers won't be cropped.\n *\n * An error is returned if for instance the crop region is invalid, out of the\n * buffer's bound or if the window is invalid.\n */\nstatic inline int native_window_set_post_transform_crop(\n        struct ANativeWindow* window,\n        android_native_rect_t const * crop)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_POST_TRANSFORM_CROP, crop);\n}\n\n/*\n * native_window_set_active_rect(..., active_rect)\n *\n * This function is deprecated and will be removed soon.  For now it simply\n * sets the post-transform crop for compatibility while multi-project commits\n * get checked.\n */\nstatic inline int native_window_set_active_rect(\n        struct ANativeWindow* window,\n        android_native_rect_t const * active_rect) __deprecated;\n\nstatic inline int native_window_set_active_rect(\n        struct ANativeWindow* window,\n        android_native_rect_t const * active_rect)\n{\n    return native_window_set_post_transform_crop(window, active_rect);\n}\n\n/*\n * native_window_set_buffer_count(..., count)\n * Sets the number of buffers associated with this native window.\n */\nstatic inline int native_window_set_buffer_count(\n        struct ANativeWindow* window,\n        size_t bufferCount)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFER_COUNT, bufferCount);\n}\n\n/*\n * native_window_set_buffers_geometry(..., int w, int h, int format)\n * All buffers dequeued after this call will have the dimensions and format\n * specified.  A successful call to this function has the same effect as calling\n * native_window_set_buffers_size and native_window_set_buffers_format.\n *\n * XXX: This function is deprecated.  The native_window_set_buffers_dimensions\n * and native_window_set_buffers_format functions should be used instead.\n */\nstatic inline int native_window_set_buffers_geometry(\n        struct ANativeWindow* window,\n        int w, int h, int format) __deprecated;\n\nstatic inline int native_window_set_buffers_geometry(\n        struct ANativeWindow* window,\n        int w, int h, int format)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_GEOMETRY,\n            w, h, format);\n}\n\n/*\n * native_window_set_buffers_dimensions(..., int w, int h)\n * All buffers dequeued after this call will have the dimensions specified.\n * In particular, all buffers will have a fixed-size, independent from the\n * native-window size. They will be scaled according to the scaling mode\n * (see native_window_set_scaling_mode) upon window composition.\n *\n * If w and h are 0, the normal behavior is restored. That is, dequeued buffers\n * following this call will be sized to match the window's size.\n *\n * Calling this function will reset the window crop to a NULL value, which\n * disables cropping of the buffers.\n */\nstatic inline int native_window_set_buffers_dimensions(\n        struct ANativeWindow* window,\n        int w, int h)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_DIMENSIONS,\n            w, h);\n}\n\n/*\n * native_window_set_buffers_user_dimensions(..., int w, int h)\n *\n * Sets the user buffer size for the window, which overrides the\n * window's size.  All buffers dequeued after this call will have the\n * dimensions specified unless overridden by\n * native_window_set_buffers_dimensions.  All buffers will have a\n * fixed-size, independent from the native-window size. They will be\n * scaled according to the scaling mode (see\n * native_window_set_scaling_mode) upon window composition.\n *\n * If w and h are 0, the normal behavior is restored. That is, the\n * default buffer size will match the windows's size.\n *\n * Calling this function will reset the window crop to a NULL value, which\n * disables cropping of the buffers.\n */\nstatic inline int native_window_set_buffers_user_dimensions(\n        struct ANativeWindow* window,\n        int w, int h)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_USER_DIMENSIONS,\n            w, h);\n}\n\n/*\n * native_window_set_buffers_format(..., int format)\n * All buffers dequeued after this call will have the format specified.\n *\n * If the specified format is 0, the default buffer format will be used.\n */\nstatic inline int native_window_set_buffers_format(\n        struct ANativeWindow* window,\n        int format)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_FORMAT, format);\n}\n\n/*\n * native_window_set_buffers_data_space(..., int dataSpace)\n * All buffers queued after this call will be associated with the dataSpace\n * parameter specified.\n *\n * dataSpace specifies additional information about the buffer that's dependent\n * on the buffer format and the endpoints. For example, it can be used to convey\n * the color space of the image data in the buffer, or it can be used to\n * indicate that the buffers contain depth measurement data instead of color\n * images.  The default dataSpace is 0, HAL_DATASPACE_UNKNOWN, unless it has been\n * overridden by the consumer.\n */\nstatic inline int native_window_set_buffers_data_space(\n        struct ANativeWindow* window,\n        android_dataspace_t dataSpace)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_DATASPACE,\n            dataSpace);\n}\n\n/*\n * native_window_set_buffers_transform(..., int transform)\n * All buffers queued after this call will be displayed transformed according\n * to the transform parameter specified.\n */\nstatic inline int native_window_set_buffers_transform(\n        struct ANativeWindow* window,\n        int transform)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_TRANSFORM,\n            transform);\n}\n\n/*\n * native_window_set_buffers_sticky_transform(..., int transform)\n * All buffers queued after this call will be displayed transformed according\n * to the transform parameter specified applied on top of the regular buffer\n * transform.  Setting this transform will disable the transform hint.\n *\n * Temporary - This is only intended to be used by the LEGACY camera mode, do\n *   not use this for anything else.\n */\nstatic inline int native_window_set_buffers_sticky_transform(\n        struct ANativeWindow* window,\n        int transform)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_STICKY_TRANSFORM,\n            transform);\n}\n\n/*\n * native_window_set_buffers_timestamp(..., int64_t timestamp)\n * All buffers queued after this call will be associated with the timestamp\n * parameter specified. If the timestamp is set to NATIVE_WINDOW_TIMESTAMP_AUTO\n * (the default), timestamps will be generated automatically when queueBuffer is\n * called. The timestamp is measured in nanoseconds, and is normally monotonically\n * increasing. The timestamp should be unaffected by time-of-day adjustments,\n * and for a camera should be strictly monotonic but for a media player may be\n * reset when the position is set.\n */\nstatic inline int native_window_set_buffers_timestamp(\n        struct ANativeWindow* window,\n        int64_t timestamp)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_BUFFERS_TIMESTAMP,\n            timestamp);\n}\n\n/*\n * native_window_set_scaling_mode(..., int mode)\n * All buffers queued after this call will be associated with the scaling mode\n * specified.\n */\nstatic inline int native_window_set_scaling_mode(\n        struct ANativeWindow* window,\n        int mode)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_SCALING_MODE,\n            mode);\n}\n\n/*\n * native_window_api_connect(..., int api)\n * connects an API to this window. only one API can be connected at a time.\n * Returns -EINVAL if for some reason the window cannot be connected, which\n * can happen if it's connected to some other API.\n */\nstatic inline int native_window_api_connect(\n        struct ANativeWindow* window, int api)\n{\n    return window->perform(window, NATIVE_WINDOW_API_CONNECT, api);\n}\n\n/*\n * native_window_api_disconnect(..., int api)\n * disconnect the API from this window.\n * An error is returned if for instance the window wasn't connected in the\n * first place.\n */\nstatic inline int native_window_api_disconnect(\n        struct ANativeWindow* window, int api)\n{\n    return window->perform(window, NATIVE_WINDOW_API_DISCONNECT, api);\n}\n\n/*\n * native_window_dequeue_buffer_and_wait(...)\n * Dequeue a buffer and wait on the fence associated with that buffer.  The\n * buffer may safely be accessed immediately upon this function returning.  An\n * error is returned if either of the dequeue or the wait operations fail.\n */\nstatic inline int native_window_dequeue_buffer_and_wait(ANativeWindow *anw,\n        struct ANativeWindowBuffer** anb) {\n    return anw->dequeueBuffer_DEPRECATED(anw, anb);\n}\n\n/*\n * native_window_set_sideband_stream(..., native_handle_t*)\n * Attach a sideband buffer stream to a native window.\n */\nstatic inline int native_window_set_sideband_stream(\n        struct ANativeWindow* window,\n        native_handle_t* sidebandHandle)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_SIDEBAND_STREAM,\n            sidebandHandle);\n}\n\n/*\n * native_window_set_surface_damage(..., android_native_rect_t* rects, int numRects)\n * Set the surface damage (i.e., the region of the surface that has changed\n * since the previous frame). The damage set by this call will be reset (to the\n * default of full-surface damage) after calling queue, so this must be called\n * prior to every frame with damage that does not cover the whole surface if the\n * caller desires downstream consumers to use this optimization.\n *\n * The damage region is specified as an array of rectangles, with the important\n * caveat that the origin of the surface is considered to be the bottom-left\n * corner, as in OpenGL ES.\n *\n * If numRects is set to 0, rects may be NULL, and the surface damage will be\n * set to the full surface (the same as if this function had not been called for\n * this frame).\n */\nstatic inline int native_window_set_surface_damage(\n        struct ANativeWindow* window,\n        const android_native_rect_t* rects, size_t numRects)\n{\n    return window->perform(window, NATIVE_WINDOW_SET_SURFACE_DAMAGE,\n            rects, numRects);\n}\n\n__END_DECLS\n\n#endif /* SYSTEM_CORE_INCLUDE_ANDROID_WINDOW_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/AndroidThreads.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_ANDROID_THREADS_H\n#define _LIBS_UTILS_ANDROID_THREADS_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#if !defined(_WIN32)\n# include <pthread.h>\n#endif\n\n#include <utils/ThreadDefs.h>\n\n// ---------------------------------------------------------------------------\n// C API\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Create and run a new thread.\nextern int androidCreateThread(android_thread_func_t, void *);\n\n// Create thread with lots of parameters\nextern int androidCreateThreadEtc(android_thread_func_t entryFunction,\n                                  void *userData,\n                                  const char* threadName,\n                                  int32_t threadPriority,\n                                  size_t threadStackSize,\n                                  android_thread_id_t *threadId);\n\n// Get some sort of unique identifier for the current thread.\nextern android_thread_id_t androidGetThreadId();\n\n// Low-level thread creation -- never creates threads that can\n// interact with the Java VM.\nextern int androidCreateRawThreadEtc(android_thread_func_t entryFunction,\n                                     void *userData,\n                                     const char* threadName,\n                                     int32_t threadPriority,\n                                     size_t threadStackSize,\n                                     android_thread_id_t *threadId);\n\n// set the same of the running thread\nextern void androidSetThreadName(const char* name);\n\n// Used by the Java Runtime to control how threads are created, so that\n// they can be proper and lovely Java threads.\ntypedef int (*android_create_thread_fn)(android_thread_func_t entryFunction,\n                                        void *userData,\n                                        const char* threadName,\n                                        int32_t threadPriority,\n                                        size_t threadStackSize,\n                                        android_thread_id_t *threadId);\n\nextern void androidSetCreateThreadFunc(android_create_thread_fn func);\n\n// ------------------------------------------------------------------\n// Extra functions working with raw pids.\n\n#ifdef HAVE_ANDROID_OS\n// Change the priority AND scheduling group of a particular thread.  The priority\n// should be one of the ANDROID_PRIORITY constants.  Returns INVALID_OPERATION\n// if the priority set failed, else another value if just the group set failed;\n// in either case errno is set.  Thread ID zero means current thread.\nextern int androidSetThreadPriority(pid_t tid, int prio);\n\n// Get the current priority of a particular thread. Returns one of the\n// ANDROID_PRIORITY constants or a negative result in case of error.\nextern int androidGetThreadPriority(pid_t tid);\n#endif\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n// ----------------------------------------------------------------------------\n// C++ API\n#ifdef __cplusplus\nnamespace android {\n// ----------------------------------------------------------------------------\n\n// Create and run a new thread.\ninline bool createThread(thread_func_t f, void *a) {\n    return androidCreateThread(f, a) ? true : false;\n}\n\n// Create thread with lots of parameters\ninline bool createThreadEtc(thread_func_t entryFunction,\n                            void *userData,\n                            const char* threadName = \"android:unnamed_thread\",\n                            int32_t threadPriority = PRIORITY_DEFAULT,\n                            size_t threadStackSize = 0,\n                            thread_id_t *threadId = 0)\n{\n    return androidCreateThreadEtc(entryFunction, userData, threadName,\n        threadPriority, threadStackSize, threadId) ? true : false;\n}\n\n// Get some sort of unique identifier for the current thread.\ninline thread_id_t getThreadId() {\n    return androidGetThreadId();\n}\n\n// ----------------------------------------------------------------------------\n}; // namespace android\n#endif  // __cplusplus\n// ----------------------------------------------------------------------------\n\n#endif // _LIBS_UTILS_ANDROID_THREADS_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Atomic.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UTILS_ATOMIC_H\n#define ANDROID_UTILS_ATOMIC_H\n\n#include <cutils/atomic.h>\n\n#endif // ANDROID_UTILS_ATOMIC_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/BasicHashtable.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_BASIC_HASHTABLE_H\n#define ANDROID_BASIC_HASHTABLE_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <utils/SharedBuffer.h>\n#include <utils/TypeHelpers.h>\n\nnamespace android {\n\n/* Implementation type.  Nothing to see here. */\nclass BasicHashtableImpl {\nprotected:\n    struct Bucket {\n        // The collision flag indicates that the bucket is part of a collision chain\n        // such that at least two entries both hash to this bucket.  When true, we\n        // may need to seek further along the chain to find the entry.\n        static const uint32_t COLLISION = 0x80000000UL;\n\n        // The present flag indicates that the bucket contains an initialized entry value.\n        static const uint32_t PRESENT   = 0x40000000UL;\n\n        // Mask for 30 bits worth of the hash code that are stored within the bucket to\n        // speed up lookups and rehashing by eliminating the need to recalculate the\n        // hash code of the entry's key.\n        static const uint32_t HASH_MASK = 0x3fffffffUL;\n\n        // Combined value that stores the collision and present flags as well as\n        // a 30 bit hash code.\n        uint32_t cookie;\n\n        // Storage for the entry begins here.\n        char entry[0];\n    };\n\n    BasicHashtableImpl(size_t entrySize, bool hasTrivialDestructor,\n            size_t minimumInitialCapacity, float loadFactor);\n    BasicHashtableImpl(const BasicHashtableImpl& other);\n    virtual ~BasicHashtableImpl();\n\n    void dispose();\n\n    inline void edit() {\n        if (mBuckets && !SharedBuffer::bufferFromData(mBuckets)->onlyOwner()) {\n            clone();\n        }\n    }\n\n    void setTo(const BasicHashtableImpl& other);\n    void clear();\n\n    ssize_t next(ssize_t index) const;\n    ssize_t find(ssize_t index, hash_t hash, const void* __restrict__ key) const;\n    size_t add(hash_t hash, const void* __restrict__ entry);\n    void removeAt(size_t index);\n    void rehash(size_t minimumCapacity, float loadFactor);\n\n    const size_t mBucketSize; // number of bytes per bucket including the entry\n    const bool mHasTrivialDestructor; // true if the entry type does not require destruction\n    size_t mCapacity;         // number of buckets that can be filled before exceeding load factor\n    float mLoadFactor;        // load factor\n    size_t mSize;             // number of elements actually in the table\n    size_t mFilledBuckets;    // number of buckets for which collision or present is true\n    size_t mBucketCount;      // number of slots in the mBuckets array\n    void* mBuckets;           // array of buckets, as a SharedBuffer\n\n    inline const Bucket& bucketAt(const void* __restrict__ buckets, size_t index) const {\n        return *reinterpret_cast<const Bucket*>(\n                static_cast<const uint8_t*>(buckets) + index * mBucketSize);\n    }\n\n    inline Bucket& bucketAt(void* __restrict__ buckets, size_t index) const {\n        return *reinterpret_cast<Bucket*>(static_cast<uint8_t*>(buckets) + index * mBucketSize);\n    }\n\n    virtual bool compareBucketKey(const Bucket& bucket, const void* __restrict__ key) const = 0;\n    virtual void initializeBucketEntry(Bucket& bucket, const void* __restrict__ entry) const = 0;\n    virtual void destroyBucketEntry(Bucket& bucket) const = 0;\n\nprivate:\n    void clone();\n\n    // Allocates a bucket array as a SharedBuffer.\n    void* allocateBuckets(size_t count) const;\n\n    // Releases a bucket array's associated SharedBuffer.\n    void releaseBuckets(void* __restrict__ buckets, size_t count) const;\n\n    // Destroys the contents of buckets (invokes destroyBucketEntry for each\n    // populated bucket if needed).\n    void destroyBuckets(void* __restrict__ buckets, size_t count) const;\n\n    // Copies the content of buckets (copies the cookie and invokes copyBucketEntry\n    // for each populated bucket if needed).\n    void copyBuckets(const void* __restrict__ fromBuckets,\n            void* __restrict__ toBuckets, size_t count) const;\n\n    // Determines the appropriate size of a bucket array to store a certain minimum\n    // number of entries and returns its effective capacity.\n    static void determineCapacity(size_t minimumCapacity, float loadFactor,\n            size_t* __restrict__ outBucketCount, size_t* __restrict__ outCapacity);\n\n    // Trim a hash code to 30 bits to match what we store in the bucket's cookie.\n    inline static hash_t trimHash(hash_t hash) {\n        return (hash & Bucket::HASH_MASK) ^ (hash >> 30);\n    }\n\n    // Returns the index of the first bucket that is in the collision chain\n    // for the specified hash code, given the total number of buckets.\n    // (Primary hash)\n    inline static size_t chainStart(hash_t hash, size_t count) {\n        return hash % count;\n    }\n\n    // Returns the increment to add to a bucket index to seek to the next bucket\n    // in the collision chain for the specified hash code, given the total number of buckets.\n    // (Secondary hash)\n    inline static size_t chainIncrement(hash_t hash, size_t count) {\n        return ((hash >> 7) | (hash << 25)) % (count - 1) + 1;\n    }\n\n    // Returns the index of the next bucket that is in the collision chain\n    // that is defined by the specified increment, given the total number of buckets.\n    inline static size_t chainSeek(size_t index, size_t increment, size_t count) {\n        return (index + increment) % count;\n    }\n};\n\n/*\n * A BasicHashtable stores entries that are indexed by hash code in place\n * within an array.  The basic operations are finding entries by key,\n * adding new entries and removing existing entries.\n *\n * This class provides a very limited set of operations with simple semantics.\n * It is intended to be used as a building block to construct more complex\n * and interesting data structures such as HashMap.  Think very hard before\n * adding anything extra to BasicHashtable, it probably belongs at a\n * higher level of abstraction.\n *\n * TKey: The key type.\n * TEntry: The entry type which is what is actually stored in the array.\n *\n * TKey must support the following contract:\n *     bool operator==(const TKey& other) const;  // return true if equal\n *     bool operator!=(const TKey& other) const;  // return true if unequal\n *\n * TEntry must support the following contract:\n *     const TKey& getKey() const;  // get the key from the entry\n *\n * This class supports storing entries with duplicate keys.  Of course, it can't\n * tell them apart during removal so only the first entry will be removed.\n * We do this because it means that operations like add() can't fail.\n */\ntemplate <typename TKey, typename TEntry>\nclass BasicHashtable : private BasicHashtableImpl {\npublic:\n    /* Creates a hashtable with the specified minimum initial capacity.\n     * The underlying array will be created when the first entry is added.\n     *\n     * minimumInitialCapacity: The minimum initial capacity for the hashtable.\n     *     Default is 0.\n     * loadFactor: The desired load factor for the hashtable, between 0 and 1.\n     *     Default is 0.75.\n     */\n    BasicHashtable(size_t minimumInitialCapacity = 0, float loadFactor = 0.75f);\n\n    /* Copies a hashtable.\n     * The underlying storage is shared copy-on-write.\n     */\n    BasicHashtable(const BasicHashtable& other);\n\n    /* Clears and destroys the hashtable.\n     */\n    virtual ~BasicHashtable();\n\n    /* Making this hashtable a copy of the other hashtable.\n     * The underlying storage is shared copy-on-write.\n     *\n     * other: The hashtable to copy.\n     */\n    inline BasicHashtable<TKey, TEntry>& operator =(const BasicHashtable<TKey, TEntry> & other) {\n        setTo(other);\n        return *this;\n    }\n\n    /* Returns the number of entries in the hashtable.\n     */\n    inline size_t size() const {\n        return mSize;\n    }\n\n    /* Returns the capacity of the hashtable, which is the number of elements that can\n     * added to the hashtable without requiring it to be grown.\n     */\n    inline size_t capacity() const {\n        return mCapacity;\n    }\n\n    /* Returns the number of buckets that the hashtable has, which is the size of its\n     * underlying array.\n     */\n    inline size_t bucketCount() const {\n        return mBucketCount;\n    }\n\n    /* Returns the load factor of the hashtable. */\n    inline float loadFactor() const {\n        return mLoadFactor;\n    };\n\n    /* Returns a const reference to the entry at the specified index.\n     *\n     * index:   The index of the entry to retrieve.  Must be a valid index within\n     *          the bounds of the hashtable.\n     */\n    inline const TEntry& entryAt(size_t index) const {\n        return entryFor(bucketAt(mBuckets, index));\n    }\n\n    /* Returns a non-const reference to the entry at the specified index.\n     *\n     * index: The index of the entry to edit.  Must be a valid index within\n     *        the bounds of the hashtable.\n     */\n    inline TEntry& editEntryAt(size_t index) {\n        edit();\n        return entryFor(bucketAt(mBuckets, index));\n    }\n\n    /* Clears the hashtable.\n     * All entries in the hashtable are destroyed immediately.\n     * If you need to do something special with the entries in the hashtable then iterate\n     * over them and do what you need before clearing the hashtable.\n     */\n    inline void clear() {\n        BasicHashtableImpl::clear();\n    }\n\n    /* Returns the index of the next entry in the hashtable given the index of a previous entry.\n     * If the given index is -1, then returns the index of the first entry in the hashtable,\n     * if there is one, or -1 otherwise.\n     * If the given index is not -1, then returns the index of the next entry in the hashtable,\n     * in strictly increasing order, or -1 if there are none left.\n     *\n     * index:   The index of the previous entry that was iterated, or -1 to begin\n     *          iteration at the beginning of the hashtable.\n     */\n    inline ssize_t next(ssize_t index) const {\n        return BasicHashtableImpl::next(index);\n    }\n\n    /* Finds the index of an entry with the specified key.\n     * If the given index is -1, then returns the index of the first matching entry,\n     * otherwise returns the index of the next matching entry.\n     * If the hashtable contains multiple entries with keys that match the requested\n     * key, then the sequence of entries returned is arbitrary.\n     * Returns -1 if no entry was found.\n     *\n     * index:   The index of the previous entry with the specified key, or -1 to\n     *          find the first matching entry.\n     * hash:    The hashcode of the key.\n     * key:     The key.\n     */\n    inline ssize_t find(ssize_t index, hash_t hash, const TKey& key) const {\n        return BasicHashtableImpl::find(index, hash, &key);\n    }\n\n    /* Adds the entry to the hashtable.\n     * Returns the index of the newly added entry.\n     * If an entry with the same key already exists, then a duplicate entry is added.\n     * If the entry will not fit, then the hashtable's capacity is increased and\n     * its contents are rehashed.  See rehash().\n     *\n     * hash:    The hashcode of the key.\n     * entry:   The entry to add.\n     */\n    inline size_t add(hash_t hash, const TEntry& entry) {\n        return BasicHashtableImpl::add(hash, &entry);\n    }\n\n    /* Removes the entry with the specified index from the hashtable.\n     * The entry is destroyed immediately.\n     * The index must be valid.\n     *\n     * The hashtable is not compacted after an item is removed, so it is legal\n     * to continue iterating over the hashtable using next() or find().\n     *\n     * index:   The index of the entry to remove.  Must be a valid index within the\n     *          bounds of the hashtable, and it must refer to an existing entry.\n     */\n    inline void removeAt(size_t index) {\n        BasicHashtableImpl::removeAt(index);\n    }\n\n    /* Rehashes the contents of the hashtable.\n     * Grows the hashtable to at least the specified minimum capacity or the\n     * current number of elements, whichever is larger.\n     *\n     * Rehashing causes all entries to be copied and the entry indices may change.\n     * Although the hash codes are cached by the hashtable, rehashing can be an\n     * expensive operation and should be avoided unless the hashtable's size\n     * needs to be changed.\n     *\n     * Rehashing is the only way to change the capacity or load factor of the\n     * hashtable once it has been created.  It can be used to compact the\n     * hashtable by choosing a minimum capacity that is smaller than the current\n     * capacity (such as 0).\n     *\n     * minimumCapacity: The desired minimum capacity after rehashing.\n     * loadFactor: The desired load factor after rehashing.\n     */\n    inline void rehash(size_t minimumCapacity, float loadFactor) {\n        BasicHashtableImpl::rehash(minimumCapacity, loadFactor);\n    }\n\n    /* Determines whether there is room to add another entry without rehashing.\n     * When this returns true, a subsequent add() operation is guaranteed to\n     * complete without performing a rehash.\n     */\n    inline bool hasMoreRoom() const {\n        return mCapacity > mFilledBuckets;\n    }\n\nprotected:\n    static inline const TEntry& entryFor(const Bucket& bucket) {\n        return reinterpret_cast<const TEntry&>(bucket.entry);\n    }\n\n    static inline TEntry& entryFor(Bucket& bucket) {\n        return reinterpret_cast<TEntry&>(bucket.entry);\n    }\n\n    virtual bool compareBucketKey(const Bucket& bucket, const void* __restrict__ key) const;\n    virtual void initializeBucketEntry(Bucket& bucket, const void* __restrict__ entry) const;\n    virtual void destroyBucketEntry(Bucket& bucket) const;\n\nprivate:\n    // For dumping the raw contents of a hashtable during testing.\n    friend class BasicHashtableTest;\n    inline uint32_t cookieAt(size_t index) const {\n        return bucketAt(mBuckets, index).cookie;\n    }\n};\n\ntemplate <typename TKey, typename TEntry>\nBasicHashtable<TKey, TEntry>::BasicHashtable(size_t minimumInitialCapacity, float loadFactor) :\n        BasicHashtableImpl(sizeof(TEntry), traits<TEntry>::has_trivial_dtor,\n                minimumInitialCapacity, loadFactor) {\n}\n\ntemplate <typename TKey, typename TEntry>\nBasicHashtable<TKey, TEntry>::BasicHashtable(const BasicHashtable<TKey, TEntry>& other) :\n        BasicHashtableImpl(other) {\n}\n\ntemplate <typename TKey, typename TEntry>\nBasicHashtable<TKey, TEntry>::~BasicHashtable() {\n    dispose();\n}\n\ntemplate <typename TKey, typename TEntry>\nbool BasicHashtable<TKey, TEntry>::compareBucketKey(const Bucket& bucket,\n        const void* __restrict__ key) const {\n    return entryFor(bucket).getKey() == *static_cast<const TKey*>(key);\n}\n\ntemplate <typename TKey, typename TEntry>\nvoid BasicHashtable<TKey, TEntry>::initializeBucketEntry(Bucket& bucket,\n        const void* __restrict__ entry) const {\n    if (!traits<TEntry>::has_trivial_copy) {\n        new (&entryFor(bucket)) TEntry(*(static_cast<const TEntry*>(entry)));\n    } else {\n        memcpy(&entryFor(bucket), entry, sizeof(TEntry));\n    }\n}\n\ntemplate <typename TKey, typename TEntry>\nvoid BasicHashtable<TKey, TEntry>::destroyBucketEntry(Bucket& bucket) const {\n    if (!traits<TEntry>::has_trivial_dtor) {\n        entryFor(bucket).~TEntry();\n    }\n}\n\n}; // namespace android\n\n#endif // ANDROID_BASIC_HASHTABLE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/BitSet.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef UTILS_BITSET_H\n#define UTILS_BITSET_H\n\n#include <stdint.h>\n#include <utils/TypeHelpers.h>\n\n/*\n * Contains some bit manipulation helpers.\n */\n\nnamespace android {\n\n// A simple set of 32 bits that can be individually marked or cleared.\nstruct BitSet32 {\n    uint32_t value;\n\n    inline BitSet32() : value(0UL) { }\n    explicit inline BitSet32(uint32_t value) : value(value) { }\n\n    // Gets the value associated with a particular bit index.\n    static inline uint32_t valueForBit(uint32_t n) { return 0x80000000UL >> n; }\n\n    // Clears the bit set.\n    inline void clear() { clear(value); }\n\n    static inline void clear(uint32_t& value) { value = 0UL; }\n\n    // Returns the number of marked bits in the set.\n    inline uint32_t count() const { return count(value); }\n\n    static inline uint32_t count(uint32_t value) { return __builtin_popcountl(value); }\n\n    // Returns true if the bit set does not contain any marked bits.\n    inline bool isEmpty() const { return isEmpty(value); }\n\n    static inline bool isEmpty(uint32_t value) { return ! value; }\n\n    // Returns true if the bit set does not contain any unmarked bits.\n    inline bool isFull() const { return isFull(value); }\n\n    static inline bool isFull(uint32_t value) { return value == 0xffffffffUL; }\n\n    // Returns true if the specified bit is marked.\n    inline bool hasBit(uint32_t n) const { return hasBit(value, n); }\n\n    static inline bool hasBit(uint32_t value, uint32_t n) { return value & valueForBit(n); }\n\n    // Marks the specified bit.\n    inline void markBit(uint32_t n) { markBit(value, n); }\n\n    static inline void markBit (uint32_t& value, uint32_t n) { value |= valueForBit(n); }\n\n    // Clears the specified bit.\n    inline void clearBit(uint32_t n) { clearBit(value, n); }\n\n    static inline void clearBit(uint32_t& value, uint32_t n) { value &= ~ valueForBit(n); }\n\n    // Finds the first marked bit in the set.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t firstMarkedBit() const { return firstMarkedBit(value); }\n\n    static uint32_t firstMarkedBit(uint32_t value) { return clz_checked(value); }\n\n    // Finds the first unmarked bit in the set.\n    // Result is undefined if all bits are marked.\n    inline uint32_t firstUnmarkedBit() const { return firstUnmarkedBit(value); }\n\n    static inline uint32_t firstUnmarkedBit(uint32_t value) { return clz_checked(~ value); }\n\n    // Finds the last marked bit in the set.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t lastMarkedBit() const { return lastMarkedBit(value); }\n\n    static inline uint32_t lastMarkedBit(uint32_t value) { return 31 - ctz_checked(value); }\n\n    // Finds the first marked bit in the set and clears it.  Returns the bit index.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t clearFirstMarkedBit() { return clearFirstMarkedBit(value); }\n\n    static inline uint32_t clearFirstMarkedBit(uint32_t& value) {\n        uint32_t n = firstMarkedBit(value);\n        clearBit(value, n);\n        return n;\n    }\n\n    // Finds the first unmarked bit in the set and marks it.  Returns the bit index.\n    // Result is undefined if all bits are marked.\n    inline uint32_t markFirstUnmarkedBit() { return markFirstUnmarkedBit(value); }\n\n    static inline uint32_t markFirstUnmarkedBit(uint32_t& value) {\n        uint32_t n = firstUnmarkedBit(value);\n        markBit(value, n);\n        return n;\n    }\n\n    // Finds the last marked bit in the set and clears it.  Returns the bit index.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t clearLastMarkedBit() { return clearLastMarkedBit(value); }\n\n    static inline uint32_t clearLastMarkedBit(uint32_t& value) {\n        uint32_t n = lastMarkedBit(value);\n        clearBit(value, n);\n        return n;\n    }\n\n    // Gets the index of the specified bit in the set, which is the number of\n    // marked bits that appear before the specified bit.\n    inline uint32_t getIndexOfBit(uint32_t n) const {\n        return getIndexOfBit(value, n);\n    }\n\n    static inline uint32_t getIndexOfBit(uint32_t value, uint32_t n) {\n        return __builtin_popcountl(value & ~(0xffffffffUL >> n));\n    }\n\n    inline bool operator== (const BitSet32& other) const { return value == other.value; }\n    inline bool operator!= (const BitSet32& other) const { return value != other.value; }\n    inline BitSet32 operator& (const BitSet32& other) const {\n        return BitSet32(value & other.value);\n    }\n    inline BitSet32& operator&= (const BitSet32& other) {\n        value &= other.value;\n        return *this;\n    }\n    inline BitSet32 operator| (const BitSet32& other) const {\n        return BitSet32(value | other.value);\n    }\n    inline BitSet32& operator|= (const BitSet32& other) {\n        value |= other.value;\n        return *this;\n    }\n\nprivate:\n    // We use these helpers as the signature of __builtin_c{l,t}z has \"unsigned int\" for the\n    // input, which is only guaranteed to be 16b, not 32. The compiler should optimize this away.\n    static inline uint32_t clz_checked(uint32_t value) {\n        if (sizeof(unsigned int) == sizeof(uint32_t)) {\n            return __builtin_clz(value);\n        } else {\n            return __builtin_clzl(value);\n        }\n    }\n\n    static inline uint32_t ctz_checked(uint32_t value) {\n        if (sizeof(unsigned int) == sizeof(uint32_t)) {\n            return __builtin_ctz(value);\n        } else {\n            return __builtin_ctzl(value);\n        }\n    }\n};\n\nANDROID_BASIC_TYPES_TRAITS(BitSet32)\n\n// A simple set of 64 bits that can be individually marked or cleared.\nstruct BitSet64 {\n    uint64_t value;\n\n    inline BitSet64() : value(0ULL) { }\n    explicit inline BitSet64(uint64_t value) : value(value) { }\n\n    // Gets the value associated with a particular bit index.\n    static inline uint64_t valueForBit(uint32_t n) { return 0x8000000000000000ULL >> n; }\n\n    // Clears the bit set.\n    inline void clear() { clear(value); }\n\n    static inline void clear(uint64_t& value) { value = 0ULL; }\n\n    // Returns the number of marked bits in the set.\n    inline uint32_t count() const { return count(value); }\n\n    static inline uint32_t count(uint64_t value) { return __builtin_popcountll(value); }\n\n    // Returns true if the bit set does not contain any marked bits.\n    inline bool isEmpty() const { return isEmpty(value); }\n\n    static inline bool isEmpty(uint64_t value) { return ! value; }\n\n    // Returns true if the bit set does not contain any unmarked bits.\n    inline bool isFull() const { return isFull(value); }\n\n    static inline bool isFull(uint64_t value) { return value == 0xffffffffffffffffULL; }\n\n    // Returns true if the specified bit is marked.\n    inline bool hasBit(uint32_t n) const { return hasBit(value, n); }\n\n    static inline bool hasBit(uint64_t value, uint32_t n) { return value & valueForBit(n); }\n\n    // Marks the specified bit.\n    inline void markBit(uint32_t n) { markBit(value, n); }\n\n    static inline void markBit(uint64_t& value, uint32_t n) { value |= valueForBit(n); }\n\n    // Clears the specified bit.\n    inline void clearBit(uint32_t n) { clearBit(value, n); }\n\n    static inline void clearBit(uint64_t& value, uint32_t n) { value &= ~ valueForBit(n); }\n\n    // Finds the first marked bit in the set.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t firstMarkedBit() const { return firstMarkedBit(value); }\n\n    static inline uint32_t firstMarkedBit(uint64_t value) { return __builtin_clzll(value); }\n\n    // Finds the first unmarked bit in the set.\n    // Result is undefined if all bits are marked.\n    inline uint32_t firstUnmarkedBit() const { return firstUnmarkedBit(value); }\n\n    static inline uint32_t firstUnmarkedBit(uint64_t value) { return __builtin_clzll(~ value); }\n\n    // Finds the last marked bit in the set.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t lastMarkedBit() const { return lastMarkedBit(value); }\n\n    static inline uint32_t lastMarkedBit(uint64_t value) { return 63 - __builtin_ctzll(value); }\n\n    // Finds the first marked bit in the set and clears it.  Returns the bit index.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t clearFirstMarkedBit() { return clearFirstMarkedBit(value); }\n\n    static inline uint32_t clearFirstMarkedBit(uint64_t& value) {\n        uint64_t n = firstMarkedBit(value);\n        clearBit(value, n);\n        return n;\n    }\n\n    // Finds the first unmarked bit in the set and marks it.  Returns the bit index.\n    // Result is undefined if all bits are marked.\n    inline uint32_t markFirstUnmarkedBit() { return markFirstUnmarkedBit(value); }\n\n    static inline uint32_t markFirstUnmarkedBit(uint64_t& value) {\n        uint64_t n = firstUnmarkedBit(value);\n        markBit(value, n);\n        return n;\n    }\n\n    // Finds the last marked bit in the set and clears it.  Returns the bit index.\n    // Result is undefined if all bits are unmarked.\n    inline uint32_t clearLastMarkedBit() { return clearLastMarkedBit(value); }\n\n    static inline uint32_t clearLastMarkedBit(uint64_t& value) {\n        uint64_t n = lastMarkedBit(value);\n        clearBit(value, n);\n        return n;\n    }\n\n    // Gets the index of the specified bit in the set, which is the number of\n    // marked bits that appear before the specified bit.\n    inline uint32_t getIndexOfBit(uint32_t n) const { return getIndexOfBit(value, n); }\n\n    static inline uint32_t getIndexOfBit(uint64_t value, uint32_t n) {\n        return __builtin_popcountll(value & ~(0xffffffffffffffffULL >> n));\n    }\n\n    inline bool operator== (const BitSet64& other) const { return value == other.value; }\n    inline bool operator!= (const BitSet64& other) const { return value != other.value; }\n    inline BitSet64 operator& (const BitSet64& other) const {\n        return BitSet64(value & other.value);\n    }\n    inline BitSet64& operator&= (const BitSet64& other) {\n        value &= other.value;\n        return *this;\n    }\n    inline BitSet64 operator| (const BitSet64& other) const {\n        return BitSet64(value | other.value);\n    }\n    inline BitSet64& operator|= (const BitSet64& other) {\n        value |= other.value;\n        return *this;\n    }\n};\n\nANDROID_BASIC_TYPES_TRAITS(BitSet64)\n\n} // namespace android\n\n#endif // UTILS_BITSET_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/BlobCache.h",
    "content": "/*\n ** Copyright 2011, The Android Open Source Project\n **\n ** Licensed under the Apache License, Version 2.0 (the \"License\");\n ** you may not use this file except in compliance with the License.\n ** You may obtain a copy of the License at\n **\n **     http://www.apache.org/licenses/LICENSE-2.0\n **\n ** Unless required by applicable law or agreed to in writing, software\n ** distributed under the License is distributed on an \"AS IS\" BASIS,\n ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n ** See the License for the specific language governing permissions and\n ** limitations under the License.\n */\n\n#ifndef ANDROID_BLOB_CACHE_H\n#define ANDROID_BLOB_CACHE_H\n\n#include <stddef.h>\n\n#include <utils/Flattenable.h>\n#include <utils/RefBase.h>\n#include <utils/SortedVector.h>\n#include <utils/threads.h>\n\nnamespace android {\n\n// A BlobCache is an in-memory cache for binary key/value pairs.  A BlobCache\n// does NOT provide any thread-safety guarantees.\n//\n// The cache contents can be serialized to an in-memory buffer or mmap'd file\n// and then reloaded in a subsequent execution of the program.  This\n// serialization is non-portable and the data should only be used by the device\n// that generated it.\nclass BlobCache : public RefBase {\n\npublic:\n\n    // Create an empty blob cache. The blob cache will cache key/value pairs\n    // with key and value sizes less than or equal to maxKeySize and\n    // maxValueSize, respectively. The total combined size of ALL cache entries\n    // (key sizes plus value sizes) will not exceed maxTotalSize.\n    BlobCache(size_t maxKeySize, size_t maxValueSize, size_t maxTotalSize);\n\n    // set inserts a new binary value into the cache and associates it with the\n    // given binary key.  If the key or value are too large for the cache then\n    // the cache remains unchanged.  This includes the case where a different\n    // value was previously associated with the given key - the old value will\n    // remain in the cache.  If the given key and value are small enough to be\n    // put in the cache (based on the maxKeySize, maxValueSize, and maxTotalSize\n    // values specified to the BlobCache constructor), then the key/value pair\n    // will be in the cache after set returns.  Note, however, that a subsequent\n    // call to set may evict old key/value pairs from the cache.\n    //\n    // Preconditions:\n    //   key != NULL\n    //   0 < keySize\n    //   value != NULL\n    //   0 < valueSize\n    void set(const void* key, size_t keySize, const void* value,\n            size_t valueSize);\n\n    // get retrieves from the cache the binary value associated with a given\n    // binary key.  If the key is present in the cache then the length of the\n    // binary value associated with that key is returned.  If the value argument\n    // is non-NULL and the size of the cached value is less than valueSize bytes\n    // then the cached value is copied into the buffer pointed to by the value\n    // argument.  If the key is not present in the cache then 0 is returned and\n    // the buffer pointed to by the value argument is not modified.\n    //\n    // Note that when calling get multiple times with the same key, the later\n    // calls may fail, returning 0, even if earlier calls succeeded.  The return\n    // value must be checked for each call.\n    //\n    // Preconditions:\n    //   key != NULL\n    //   0 < keySize\n    //   0 <= valueSize\n    size_t get(const void* key, size_t keySize, void* value, size_t valueSize);\n\n\n    // getFlattenedSize returns the number of bytes needed to store the entire\n    // serialized cache.\n    size_t getFlattenedSize() const;\n\n    // flatten serializes the current contents of the cache into the memory\n    // pointed to by 'buffer'.  The serialized cache contents can later be\n    // loaded into a BlobCache object using the unflatten method.  The contents\n    // of the BlobCache object will not be modified.\n    //\n    // Preconditions:\n    //   size >= this.getFlattenedSize()\n    status_t flatten(void* buffer, size_t size) const;\n\n    // unflatten replaces the contents of the cache with the serialized cache\n    // contents in the memory pointed to by 'buffer'.  The previous contents of\n    // the BlobCache will be evicted from the cache.  If an error occurs while\n    // unflattening the serialized cache contents then the BlobCache will be\n    // left in an empty state.\n    //\n    status_t unflatten(void const* buffer, size_t size);\n\nprivate:\n    // Copying is disallowed.\n    BlobCache(const BlobCache&);\n    void operator=(const BlobCache&);\n\n    // A random function helper to get around MinGW not having nrand48()\n    long int blob_random();\n\n    // clean evicts a randomly chosen set of entries from the cache such that\n    // the total size of all remaining entries is less than mMaxTotalSize/2.\n    void clean();\n\n    // isCleanable returns true if the cache is full enough for the clean method\n    // to have some effect, and false otherwise.\n    bool isCleanable() const;\n\n    // A Blob is an immutable sized unstructured data blob.\n    class Blob : public RefBase {\n    public:\n        Blob(const void* data, size_t size, bool copyData);\n        ~Blob();\n\n        bool operator<(const Blob& rhs) const;\n\n        const void* getData() const;\n        size_t getSize() const;\n\n    private:\n        // Copying is not allowed.\n        Blob(const Blob&);\n        void operator=(const Blob&);\n\n        // mData points to the buffer containing the blob data.\n        const void* mData;\n\n        // mSize is the size of the blob data in bytes.\n        size_t mSize;\n\n        // mOwnsData indicates whether or not this Blob object should free the\n        // memory pointed to by mData when the Blob gets destructed.\n        bool mOwnsData;\n    };\n\n    // A CacheEntry is a single key/value pair in the cache.\n    class CacheEntry {\n    public:\n        CacheEntry();\n        CacheEntry(const sp<Blob>& key, const sp<Blob>& value);\n        CacheEntry(const CacheEntry& ce);\n\n        bool operator<(const CacheEntry& rhs) const;\n        const CacheEntry& operator=(const CacheEntry&);\n\n        sp<Blob> getKey() const;\n        sp<Blob> getValue() const;\n\n        void setValue(const sp<Blob>& value);\n\n    private:\n\n        // mKey is the key that identifies the cache entry.\n        sp<Blob> mKey;\n\n        // mValue is the cached data associated with the key.\n        sp<Blob> mValue;\n    };\n\n    // A Header is the header for the entire BlobCache serialization format. No\n    // need to make this portable, so we simply write the struct out.\n    struct Header {\n        // mMagicNumber is the magic number that identifies the data as\n        // serialized BlobCache contents.  It must always contain 'Blb$'.\n        uint32_t mMagicNumber;\n\n        // mBlobCacheVersion is the serialization format version.\n        uint32_t mBlobCacheVersion;\n\n        // mDeviceVersion is the device-specific version of the cache.  This can\n        // be used to invalidate the cache.\n        uint32_t mDeviceVersion;\n\n        // mNumEntries is number of cache entries following the header in the\n        // data.\n        size_t mNumEntries;\n\n        // mBuildId is the build id of the device when the cache was created.\n        // When an update to the build happens (via an OTA or other update) this\n        // is used to invalidate the cache.\n        int mBuildIdLength;\n        char mBuildId[];\n    };\n\n    // An EntryHeader is the header for a serialized cache entry.  No need to\n    // make this portable, so we simply write the struct out.  Each EntryHeader\n    // is followed imediately by the key data and then the value data.\n    //\n    // The beginning of each serialized EntryHeader is 4-byte aligned, so the\n    // number of bytes that a serialized cache entry will occupy is:\n    //\n    //   ((sizeof(EntryHeader) + keySize + valueSize) + 3) & ~3\n    //\n    struct EntryHeader {\n        // mKeySize is the size of the entry key in bytes.\n        size_t mKeySize;\n\n        // mValueSize is the size of the entry value in bytes.\n        size_t mValueSize;\n\n        // mData contains both the key and value data for the cache entry.  The\n        // key comes first followed immediately by the value.\n        uint8_t mData[];\n    };\n\n    // mMaxKeySize is the maximum key size that will be cached. Calls to\n    // BlobCache::set with a keySize parameter larger than mMaxKeySize will\n    // simply not add the key/value pair to the cache.\n    const size_t mMaxKeySize;\n\n    // mMaxValueSize is the maximum value size that will be cached. Calls to\n    // BlobCache::set with a valueSize parameter larger than mMaxValueSize will\n    // simply not add the key/value pair to the cache.\n    const size_t mMaxValueSize;\n\n    // mMaxTotalSize is the maximum size that all cache entries can occupy. This\n    // includes space for both keys and values. When a call to BlobCache::set\n    // would otherwise cause this limit to be exceeded, either the key/value\n    // pair passed to BlobCache::set will not be cached or other cache entries\n    // will be evicted from the cache to make room for the new entry.\n    const size_t mMaxTotalSize;\n\n    // mTotalSize is the total combined size of all keys and values currently in\n    // the cache.\n    size_t mTotalSize;\n\n    // mRandState is the pseudo-random number generator state. It is passed to\n    // nrand48 to generate random numbers when needed.\n    unsigned short mRandState[3];\n\n    // mCacheEntries stores all the cache entries that are resident in memory.\n    // Cache entries are added to it by the 'set' method.\n    SortedVector<CacheEntry> mCacheEntries;\n};\n\n}\n\n#endif // ANDROID_BLOB_CACHE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/ByteOrder.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n\n#ifndef _LIBS_UTILS_BYTE_ORDER_H\n#define _LIBS_UTILS_BYTE_ORDER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#ifdef HAVE_WINSOCK\n#include <winsock2.h>\n#else\n#include <netinet/in.h>\n#endif\n\n/*\n * These macros are like the hton/ntoh byte swapping macros,\n * except they allow you to swap to and from the \"device\" byte\n * order.  The device byte order is the endianness of the target\n * device -- for the ARM CPUs we use today, this is little endian.\n *\n * Note that the byte swapping functions have not been optimized\n * much; performance is currently not an issue for them since the\n * intent is to allow us to avoid byte swapping on the device.\n */\n\nstatic inline uint32_t android_swap_long(uint32_t v)\n{\n    return (v<<24) | ((v<<8)&0x00FF0000) | ((v>>8)&0x0000FF00) | (v>>24);\n}\n\nstatic inline uint16_t android_swap_short(uint16_t v)\n{\n    return (v<<8) | (v>>8);\n}\n\n#define DEVICE_BYTE_ORDER LITTLE_ENDIAN\n\n#if BYTE_ORDER == DEVICE_BYTE_ORDER\n\n#define\tdtohl(x)\t(x)\n#define\tdtohs(x)\t(x)\n#define\thtodl(x)\t(x)\n#define\thtods(x)\t(x)\n\n#else\n\n#define\tdtohl(x)\t(android_swap_long(x))\n#define\tdtohs(x)\t(android_swap_short(x))\n#define\thtodl(x)\t(android_swap_long(x))\n#define\thtods(x)\t(android_swap_short(x))\n\n#endif\n\n#if BYTE_ORDER == LITTLE_ENDIAN\n#define fromlel(x) (x)\n#define fromles(x) (x)\n#define tolel(x) (x)\n#define toles(x) (x)\n#else\n#define fromlel(x) (android_swap_long(x))\n#define fromles(x) (android_swap_short(x))\n#define tolel(x) (android_swap_long(x))\n#define toles(x) (android_swap_short(x))\n#endif\n\n#endif // _LIBS_UTILS_BYTE_ORDER_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/CallStack.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_CALLSTACK_H\n#define ANDROID_CALLSTACK_H\n\n#include <android/log.h>\n#include <backtrace/backtrace_constants.h>\n#include <utils/String8.h>\n#include <utils/Vector.h>\n\n#include <stdint.h>\n#include <sys/types.h>\n\nnamespace android {\n\nclass Printer;\n\n// Collect/print the call stack (function, file, line) traces for a single thread.\nclass CallStack {\npublic:\n    // Create an empty call stack. No-op.\n    CallStack();\n    // Create a callstack with the current thread's stack trace.\n    // Immediately dump it to logcat using the given logtag.\n    CallStack(const char* logtag, int32_t ignoreDepth=1);\n    ~CallStack();\n\n    // Reset the stack frames (same as creating an empty call stack).\n    void clear() { mFrameLines.clear(); }\n\n    // Immediately collect the stack traces for the specified thread.\n    // The default is to dump the stack of the current call.\n    void update(int32_t ignoreDepth=1, pid_t tid=BACKTRACE_CURRENT_THREAD);\n\n    // Dump a stack trace to the log using the supplied logtag.\n    void log(const char* logtag,\n             android_LogPriority priority = ANDROID_LOG_DEBUG,\n             const char* prefix = 0) const;\n\n    // Dump a stack trace to the specified file descriptor.\n    void dump(int fd, int indent = 0, const char* prefix = 0) const;\n\n    // Return a string (possibly very long) containing the complete stack trace.\n    String8 toString(const char* prefix = 0) const;\n\n    // Dump a serialized representation of the stack trace to the specified printer.\n    void print(Printer& printer) const;\n\n    // Get the count of stack frames that are in this call stack.\n    size_t size() const { return mFrameLines.size(); }\n\nprivate:\n    Vector<String8> mFrameLines;\n};\n\n}; // namespace android\n\n#endif // ANDROID_CALLSTACK_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Compat.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __LIB_UTILS_COMPAT_H\n#define __LIB_UTILS_COMPAT_H\n\n#include <unistd.h>\n\n#if defined(__APPLE__)\n\n/* Mac OS has always had a 64-bit off_t, so it doesn't have off64_t. */\n\ntypedef off_t off64_t;\n\nstatic inline off64_t lseek64(int fd, off64_t offset, int whence) {\n    return lseek(fd, offset, whence);\n}\n\nstatic inline ssize_t pread64(int fd, void* buf, size_t nbytes, off64_t offset) {\n    return pread(fd, buf, nbytes, offset);\n}\n\n#endif /* __APPLE__ */\n\n#if defined(_WIN32)\n#define O_CLOEXEC O_NOINHERIT\n#define O_NOFOLLOW 0\n#define DEFFILEMODE 0666\n#endif /* _WIN32 */\n\n#if defined(_WIN32)\n#define ZD \"%ld\"\n#define ZD_TYPE long\n#else\n#define ZD \"%zd\"\n#define ZD_TYPE ssize_t\n#endif\n\n/*\n * Needed for cases where something should be constexpr if possible, but not\n * being constexpr is fine if in pre-C++11 code (such as a const static float\n * member variable).\n */\n#if __cplusplus >= 201103L\n#define CONSTEXPR constexpr\n#else\n#define CONSTEXPR\n#endif\n\n/*\n * TEMP_FAILURE_RETRY is defined by some, but not all, versions of\n * <unistd.h>. (Alas, it is not as standard as we'd hoped!) So, if it's\n * not already defined, then define it here.\n */\n#ifndef TEMP_FAILURE_RETRY\n/* Used to retry syscalls that can return EINTR. */\n#define TEMP_FAILURE_RETRY(exp) ({         \\\n    typeof (exp) _rc;                      \\\n    do {                                   \\\n        _rc = (exp);                       \\\n    } while (_rc == -1 && errno == EINTR); \\\n    _rc; })\n#endif\n\n#endif /* __LIB_UTILS_COMPAT_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Condition.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_CONDITION_H\n#define _LIBS_UTILS_CONDITION_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <time.h>\n\n#if !defined(_WIN32)\n# include <pthread.h>\n#endif\n\n#include <utils/Errors.h>\n#include <utils/Mutex.h>\n#include <utils/Timers.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n// ---------------------------------------------------------------------------\n\n/*\n * Condition variable class.  The implementation is system-dependent.\n *\n * Condition variables are paired up with mutexes.  Lock the mutex,\n * call wait(), then either re-wait() if things aren't quite what you want,\n * or unlock the mutex and continue.  All threads calling wait() must\n * use the same mutex for a given Condition.\n */\nclass Condition {\npublic:\n    enum {\n        PRIVATE = 0,\n        SHARED = 1\n    };\n\n    enum WakeUpType {\n        WAKE_UP_ONE = 0,\n        WAKE_UP_ALL = 1\n    };\n\n    Condition();\n    Condition(int type);\n    ~Condition();\n    // Wait on the condition variable.  Lock the mutex before calling.\n    status_t wait(Mutex& mutex);\n    // same with relative timeout\n    status_t waitRelative(Mutex& mutex, nsecs_t reltime);\n    // Signal the condition variable, allowing exactly one thread to continue.\n    void signal();\n    // Signal the condition variable, allowing one or all threads to continue.\n    void signal(WakeUpType type) {\n        if (type == WAKE_UP_ONE) {\n            signal();\n        } else {\n            broadcast();\n        }\n    }\n    // Signal the condition variable, allowing all threads to continue.\n    void broadcast();\n\nprivate:\n#if !defined(_WIN32)\n    pthread_cond_t mCond;\n#else\n    void*   mState;\n#endif\n};\n\n// ---------------------------------------------------------------------------\n\n#if !defined(_WIN32)\n\ninline Condition::Condition() {\n    pthread_cond_init(&mCond, NULL);\n}\ninline Condition::Condition(int type) {\n    if (type == SHARED) {\n        pthread_condattr_t attr;\n        pthread_condattr_init(&attr);\n        pthread_condattr_setpshared(&attr, PTHREAD_PROCESS_SHARED);\n        pthread_cond_init(&mCond, &attr);\n        pthread_condattr_destroy(&attr);\n    } else {\n        pthread_cond_init(&mCond, NULL);\n    }\n}\ninline Condition::~Condition() {\n    pthread_cond_destroy(&mCond);\n}\ninline status_t Condition::wait(Mutex& mutex) {\n    return -pthread_cond_wait(&mCond, &mutex.mMutex);\n}\ninline status_t Condition::waitRelative(Mutex& mutex, nsecs_t reltime) {\n#if defined(HAVE_PTHREAD_COND_TIMEDWAIT_RELATIVE)\n    struct timespec ts;\n    ts.tv_sec  = reltime/1000000000;\n    ts.tv_nsec = reltime%1000000000;\n    return -pthread_cond_timedwait_relative_np(&mCond, &mutex.mMutex, &ts);\n#else // HAVE_PTHREAD_COND_TIMEDWAIT_RELATIVE\n    struct timespec ts;\n#if defined(__linux__)\n    clock_gettime(CLOCK_REALTIME, &ts);\n#else // __APPLE__\n    // we don't support the clocks here.\n    struct timeval t;\n    gettimeofday(&t, NULL);\n    ts.tv_sec = t.tv_sec;\n    ts.tv_nsec= t.tv_usec*1000;\n#endif\n    ts.tv_sec += reltime/1000000000;\n    ts.tv_nsec+= reltime%1000000000;\n    if (ts.tv_nsec >= 1000000000) {\n        ts.tv_nsec -= 1000000000;\n        ts.tv_sec  += 1;\n    }\n    return -pthread_cond_timedwait(&mCond, &mutex.mMutex, &ts);\n#endif // HAVE_PTHREAD_COND_TIMEDWAIT_RELATIVE\n}\ninline void Condition::signal() {\n    /*\n     * POSIX says pthread_cond_signal wakes up \"one or more\" waiting threads.\n     * However bionic follows the glibc guarantee which wakes up \"exactly one\"\n     * waiting thread.\n     *\n     * man 3 pthread_cond_signal\n     *   pthread_cond_signal restarts one of the threads that are waiting on\n     *   the condition variable cond. If no threads are waiting on cond,\n     *   nothing happens. If several threads are waiting on cond, exactly one\n     *   is restarted, but it is not specified which.\n     */\n    pthread_cond_signal(&mCond);\n}\ninline void Condition::broadcast() {\n    pthread_cond_broadcast(&mCond);\n}\n\n#endif // !defined(_WIN32)\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n// ---------------------------------------------------------------------------\n\n#endif // _LIBS_UTILS_CONDITON_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Debug.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UTILS_DEBUG_H\n#define ANDROID_UTILS_DEBUG_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\n#ifdef __cplusplus\ntemplate<bool> struct CompileTimeAssert;\ntemplate<> struct CompileTimeAssert<true> {};\n#define COMPILE_TIME_ASSERT(_exp) \\\n    template class CompileTimeAssert< (_exp) >;\n#endif\n#define COMPILE_TIME_ASSERT_FUNCTION_SCOPE(_exp) \\\n    CompileTimeAssert<( _exp )>();\n\n// ---------------------------------------------------------------------------\n\n#ifdef __cplusplus\ntemplate<bool C, typename LSH, typename RHS> struct CompileTimeIfElse;\ntemplate<typename LHS, typename RHS> \nstruct CompileTimeIfElse<true,  LHS, RHS> { typedef LHS TYPE; };\ntemplate<typename LHS, typename RHS> \nstruct CompileTimeIfElse<false, LHS, RHS> { typedef RHS TYPE; };\n#endif\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_UTILS_DEBUG_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Endian.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// Android endian-ness defines.\n//\n#ifndef _LIBS_UTILS_ENDIAN_H\n#define _LIBS_UTILS_ENDIAN_H\n\n#if defined(__APPLE__) || defined(_WIN32)\n\n#define __BIG_ENDIAN 0x1000\n#define __LITTLE_ENDIAN 0x0001\n#define __BYTE_ORDER __LITTLE_ENDIAN\n\n#else\n\n#include <endian.h>\n\n#endif\n\n#endif /*_LIBS_UTILS_ENDIAN_H*/\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Errors.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_ERRORS_H\n#define ANDROID_ERRORS_H\n\n#include <sys/types.h>\n#include <errno.h>\n\nnamespace android {\n\n// use this type to return error codes\n#ifdef HAVE_MS_C_RUNTIME\ntypedef int         status_t;\n#else\ntypedef int32_t     status_t;\n#endif\n\n/* the MS C runtime lacks a few error codes */\n\n/*\n * Error codes. \n * All error codes are negative values.\n */\n\n// Win32 #defines NO_ERROR as well.  It has the same value, so there's no\n// real conflict, though it's a bit awkward.\n#ifdef _WIN32\n# undef NO_ERROR\n#endif\n\nenum {\n    OK                = 0,    // Everything's swell.\n    NO_ERROR          = 0,    // No errors.\n\n    UNKNOWN_ERROR       = (-2147483647-1), // INT32_MIN value\n\n    NO_MEMORY           = -ENOMEM,\n    INVALID_OPERATION   = -ENOSYS,\n    BAD_VALUE           = -EINVAL,\n    BAD_TYPE            = (UNKNOWN_ERROR + 1),\n    NAME_NOT_FOUND      = -ENOENT,\n    PERMISSION_DENIED   = -EPERM,\n    NO_INIT             = -ENODEV,\n    ALREADY_EXISTS      = -EEXIST,\n    DEAD_OBJECT         = -EPIPE,\n    FAILED_TRANSACTION  = (UNKNOWN_ERROR + 2),\n    JPARKS_BROKE_IT     = -EPIPE,\n#if !defined(HAVE_MS_C_RUNTIME)\n    BAD_INDEX           = -EOVERFLOW,\n    NOT_ENOUGH_DATA     = -ENODATA,\n    WOULD_BLOCK         = -EWOULDBLOCK, \n    TIMED_OUT           = -ETIMEDOUT,\n    UNKNOWN_TRANSACTION = -EBADMSG,\n#else    \n    BAD_INDEX           = -E2BIG,\n    NOT_ENOUGH_DATA     = (UNKNOWN_ERROR + 3),\n    WOULD_BLOCK         = (UNKNOWN_ERROR + 4),\n    TIMED_OUT           = (UNKNOWN_ERROR + 5),\n    UNKNOWN_TRANSACTION = (UNKNOWN_ERROR + 6),\n#endif    \n    FDS_NOT_ALLOWED     = (UNKNOWN_ERROR + 7),\n};\n\n// Restore define; enumeration is in \"android\" namespace, so the value defined\n// there won't work for Win32 code in a different namespace.\n#ifdef _WIN32\n# define NO_ERROR 0L\n#endif\n\n}; // namespace android\n    \n// ---------------------------------------------------------------------------\n    \n#endif // ANDROID_ERRORS_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/FileMap.h",
    "content": "/*\n * Copyright (C) 2006 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// Encapsulate a shared file mapping.\n//\n#ifndef __LIBS_FILE_MAP_H\n#define __LIBS_FILE_MAP_H\n\n#include <sys/types.h>\n\n#include <utils/Compat.h>\n\n#if defined(__MINGW32__)\n// Ensure that we always pull in winsock2.h before windows.h\n#ifdef HAVE_WINSOCK\n#include <winsock2.h>\n#endif\n#include <windows.h>\n#endif\n\nnamespace android {\n\n/*\n * This represents a memory-mapped file.  It might be the entire file or\n * only part of it.  This requires a little bookkeeping because the mapping\n * needs to be aligned on page boundaries, and in some cases we'd like to\n * have multiple references to the mapped area without creating additional\n * maps.\n *\n * This always uses MAP_SHARED.\n *\n * TODO: we should be able to create a new FileMap that is a subset of\n * an existing FileMap and shares the underlying mapped pages.  Requires\n * completing the refcounting stuff and possibly introducing the notion\n * of a FileMap hierarchy.\n */\nclass FileMap {\npublic:\n    FileMap(void);\n\n    /*\n     * Create a new mapping on an open file.\n     *\n     * Closing the file descriptor does not unmap the pages, so we don't\n     * claim ownership of the fd.\n     *\n     * Returns \"false\" on failure.\n     */\n    bool create(const char* origFileName, int fd,\n                off64_t offset, size_t length, bool readOnly);\n\n    ~FileMap(void);\n\n    /*\n     * Return the name of the file this map came from, if known.\n     */\n    const char* getFileName(void) const { return mFileName; }\n    \n    /*\n     * Get a pointer to the piece of the file we requested.\n     */\n    void* getDataPtr(void) const { return mDataPtr; }\n\n    /*\n     * Get the length we requested.\n     */\n    size_t getDataLength(void) const { return mDataLength; }\n\n    /*\n     * Get the data offset used to create this map.\n     */\n    off64_t getDataOffset(void) const { return mDataOffset; }\n\n    /*\n     * This maps directly to madvise() values, but allows us to avoid\n     * including <sys/mman.h> everywhere.\n     */\n    enum MapAdvice {\n        NORMAL, RANDOM, SEQUENTIAL, WILLNEED, DONTNEED\n    };\n\n    /*\n     * Apply an madvise() call to the entire file.\n     *\n     * Returns 0 on success, -1 on failure.\n     */\n    int advise(MapAdvice advice);\n\nprotected:\n\nprivate:\n    // these are not implemented\n    FileMap(const FileMap& src);\n    const FileMap& operator=(const FileMap& src);\n\n    char*       mFileName;      // original file name, if known\n    void*       mBasePtr;       // base of mmap area; page aligned\n    size_t      mBaseLength;    // length, measured from \"mBasePtr\"\n    off64_t     mDataOffset;    // offset used when map was created\n    void*       mDataPtr;       // start of requested data, offset from base\n    size_t      mDataLength;    // length, measured from \"mDataPtr\"\n#if defined(__MINGW32__)\n    HANDLE      mFileHandle;    // Win32 file handle\n    HANDLE      mFileMapping;   // Win32 file mapping handle\n#endif\n\n    static long mPageSize;\n};\n\n}; // namespace android\n\n#endif // __LIBS_FILE_MAP_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Flattenable.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UTILS_FLATTENABLE_H\n#define ANDROID_UTILS_FLATTENABLE_H\n\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <utils/Errors.h>\n#include <utils/Debug.h>\n\nnamespace android {\n\n\nclass FlattenableUtils {\npublic:\n    template<int N>\n    static size_t align(size_t size) {\n        COMPILE_TIME_ASSERT_FUNCTION_SCOPE( !(N & (N-1)) );\n        return (size + (N-1)) & ~(N-1);\n    }\n\n    template<int N>\n    static size_t align(void const*& buffer) {\n        COMPILE_TIME_ASSERT_FUNCTION_SCOPE( !(N & (N-1)) );\n        intptr_t b = intptr_t(buffer);\n        buffer = (void*)((intptr_t(buffer) + (N-1)) & ~(N-1));\n        return size_t(intptr_t(buffer) - b);\n    }\n\n    template<int N>\n    static size_t align(void*& buffer) {\n        return align<N>( const_cast<void const*&>(buffer) );\n    }\n\n    static void advance(void*& buffer, size_t& size, size_t offset) {\n        buffer = reinterpret_cast<void*>( intptr_t(buffer) + offset );\n        size -= offset;\n    }\n\n    static void advance(void const*& buffer, size_t& size, size_t offset) {\n        buffer = reinterpret_cast<void const*>( intptr_t(buffer) + offset );\n        size -= offset;\n    }\n\n    // write a POD structure\n    template<typename T>\n    static void write(void*& buffer, size_t& size, const T& value) {\n        *static_cast<T*>(buffer) = value;\n        advance(buffer, size, sizeof(T));\n    }\n\n    // read a POD structure\n    template<typename T>\n    static void read(void const*& buffer, size_t& size, T& value) {\n        value = *static_cast<T const*>(buffer);\n        advance(buffer, size, sizeof(T));\n    }\n};\n\n\n/*\n * The Flattenable protocol allows an object to serialize itself out\n * to a byte-buffer and an array of file descriptors.\n * Flattenable objects must implement this protocol.\n */\n\ntemplate <typename T>\nclass Flattenable {\npublic:\n    // size in bytes of the flattened object\n    inline size_t getFlattenedSize() const;\n\n    // number of file descriptors to flatten\n    inline size_t getFdCount() const;\n\n    // flattens the object into buffer.\n    // size should be at least of getFlattenedSize()\n    // file descriptors are written in the fds[] array but ownership is\n    // not transfered (ie: they must be dupped by the caller of\n    // flatten() if needed).\n    inline status_t flatten(void*& buffer, size_t& size, int*& fds, size_t& count) const;\n\n    // unflattens the object from buffer.\n    // size should be equal to the value of getFlattenedSize() when the\n    // object was flattened.\n    // unflattened file descriptors are found in the fds[] array and\n    // don't need to be dupped(). ie: the caller of unflatten doesn't\n    // keep ownership. If a fd is not retained by unflatten() it must be\n    // explicitly closed.\n    inline status_t unflatten(void const*& buffer, size_t& size, int const*& fds, size_t& count);\n};\n\ntemplate<typename T>\ninline size_t Flattenable<T>::getFlattenedSize() const {\n    return static_cast<T const*>(this)->T::getFlattenedSize();\n}\ntemplate<typename T>\ninline size_t Flattenable<T>::getFdCount() const {\n    return static_cast<T const*>(this)->T::getFdCount();\n}\ntemplate<typename T>\ninline status_t Flattenable<T>::flatten(\n        void*& buffer, size_t& size, int*& fds, size_t& count) const {\n    return static_cast<T const*>(this)->T::flatten(buffer, size, fds, count);\n}\ntemplate<typename T>\ninline status_t Flattenable<T>::unflatten(\n        void const*& buffer, size_t& size, int const*& fds, size_t& count) {\n    return static_cast<T*>(this)->T::unflatten(buffer, size, fds, count);\n}\n\n/*\n * LightFlattenable is a protocol allowing object to serialize themselves out\n * to a byte-buffer. Because it doesn't handle file-descriptors,\n * LightFlattenable is usually more size efficient than Flattenable.\n * LightFlattenable objects must implement this protocol.\n */\ntemplate <typename T>\nclass LightFlattenable {\npublic:\n    // returns whether this object always flatten into the same size.\n    // for efficiency, this should always be inline.\n    inline bool isFixedSize() const;\n\n    // returns size in bytes of the flattened object. must be a constant.\n    inline size_t getFlattenedSize() const;\n\n    // flattens the object into buffer.\n    inline status_t flatten(void* buffer, size_t size) const;\n\n    // unflattens the object from buffer of given size.\n    inline status_t unflatten(void const* buffer, size_t size);\n};\n\ntemplate <typename T>\ninline bool LightFlattenable<T>::isFixedSize() const {\n    return static_cast<T const*>(this)->T::isFixedSize();\n}\ntemplate <typename T>\ninline size_t LightFlattenable<T>::getFlattenedSize() const {\n    return static_cast<T const*>(this)->T::getFlattenedSize();\n}\ntemplate <typename T>\ninline status_t LightFlattenable<T>::flatten(void* buffer, size_t size) const {\n    return static_cast<T const*>(this)->T::flatten(buffer, size);\n}\ntemplate <typename T>\ninline status_t LightFlattenable<T>::unflatten(void const* buffer, size_t size) {\n    return static_cast<T*>(this)->T::unflatten(buffer, size);\n}\n\n/*\n * LightFlattenablePod is an implementation of the LightFlattenable protocol\n * for POD (plain-old-data) objects.\n * Simply derive from LightFlattenablePod<Foo> to make Foo flattenable; no\n * need to implement any methods; obviously Foo must be a POD structure.\n */\ntemplate <typename T>\nclass LightFlattenablePod : public LightFlattenable<T> {\npublic:\n    inline bool isFixedSize() const {\n        return true;\n    }\n\n    inline size_t getFlattenedSize() const {\n        return sizeof(T);\n    }\n    inline status_t flatten(void* buffer, size_t size) const {\n        if (size < sizeof(T)) return NO_MEMORY;\n        *reinterpret_cast<T*>(buffer) = *static_cast<T const*>(this);\n        return NO_ERROR;\n    }\n    inline status_t unflatten(void const* buffer, size_t) {\n        *static_cast<T*>(this) = *reinterpret_cast<T const*>(buffer);\n        return NO_ERROR;\n    }\n};\n\n\n}; // namespace android\n\n\n#endif /* ANDROID_UTILS_FLATTENABLE_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Functor.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_FUNCTOR_H\n#define ANDROID_FUNCTOR_H\n\n#include <utils/Errors.h>\n\nnamespace  android {\n\nclass Functor {\npublic:\n    Functor() {}\n    virtual ~Functor() {}\n    virtual status_t operator ()(int /*what*/, void* /*data*/) { return NO_ERROR; }\n};\n\n}; // namespace android\n\n#endif // ANDROID_FUNCTOR_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/JenkinsHash.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Implementation of Jenkins one-at-a-time hash function. These choices are\n * optimized for code size and portability, rather than raw speed. But speed\n * should still be quite good.\n **/\n\n#ifndef ANDROID_JENKINS_HASH_H\n#define ANDROID_JENKINS_HASH_H\n\n#include <utils/TypeHelpers.h>\n\nnamespace android {\n\n/* The Jenkins hash of a sequence of 32 bit words A, B, C is:\n * Whiten(Mix(Mix(Mix(0, A), B), C)) */\n\ninline uint32_t JenkinsHashMix(uint32_t hash, uint32_t data) {\n    hash += data;\n    hash += (hash << 10);\n    hash ^= (hash >> 6);\n    return hash;\n}\n\nhash_t JenkinsHashWhiten(uint32_t hash);\n\n/* Helpful utility functions for hashing data in 32 bit chunks */\nuint32_t JenkinsHashMixBytes(uint32_t hash, const uint8_t* bytes, size_t size);\n\nuint32_t JenkinsHashMixShorts(uint32_t hash, const uint16_t* shorts, size_t size);\n\n}\n\n#endif // ANDROID_JENKINS_HASH_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/KeyedVector.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_KEYED_VECTOR_H\n#define ANDROID_KEYED_VECTOR_H\n\n#include <assert.h>\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <cutils/log.h>\n\n#include <utils/SortedVector.h>\n#include <utils/TypeHelpers.h>\n#include <utils/Errors.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\ntemplate <typename KEY, typename VALUE>\nclass KeyedVector\n{\npublic:\n    typedef KEY    key_type;\n    typedef VALUE  value_type;\n\n    inline                  KeyedVector();\n\n    /*\n     * empty the vector\n     */\n\n    inline  void            clear()                     { mVector.clear(); }\n\n    /*! \n     * vector stats\n     */\n\n    //! returns number of items in the vector\n    inline  size_t          size() const                { return mVector.size(); }\n    //! returns whether or not the vector is empty\n    inline  bool            isEmpty() const             { return mVector.isEmpty(); }\n    //! returns how many items can be stored without reallocating the backing store\n    inline  size_t          capacity() const            { return mVector.capacity(); }\n    //! sets the capacity. capacity can never be reduced less than size()\n    inline ssize_t          setCapacity(size_t size)    { return mVector.setCapacity(size); }\n\n    // returns true if the arguments is known to be identical to this vector\n    inline bool isIdenticalTo(const KeyedVector& rhs) const;\n\n    /*! \n     * accessors\n     */\n            const VALUE&    valueFor(const KEY& key) const;\n            const VALUE&    valueAt(size_t index) const;\n            const KEY&      keyAt(size_t index) const;\n            ssize_t         indexOfKey(const KEY& key) const;\n            const VALUE&    operator[] (size_t index) const;\n\n    /*!\n     * modifying the array\n     */\n\n            VALUE&          editValueFor(const KEY& key);\n            VALUE&          editValueAt(size_t index);\n\n            /*! \n             * add/insert/replace items\n             */\n             \n            ssize_t         add(const KEY& key, const VALUE& item);\n            ssize_t         replaceValueFor(const KEY& key, const VALUE& item);\n            ssize_t         replaceValueAt(size_t index, const VALUE& item);\n\n    /*!\n     * remove items\n     */\n\n            ssize_t         removeItem(const KEY& key);\n            ssize_t         removeItemsAt(size_t index, size_t count = 1);\n            \nprivate:\n            SortedVector< key_value_pair_t<KEY, VALUE> >    mVector;\n};\n\n// KeyedVector<KEY, VALUE> can be trivially moved using memcpy() because its\n// underlying SortedVector can be trivially moved.\ntemplate<typename KEY, typename VALUE> struct trait_trivial_move<KeyedVector<KEY, VALUE> > {\n    enum { value = trait_trivial_move<SortedVector< key_value_pair_t<KEY, VALUE> > >::value };\n};\n\n\n// ---------------------------------------------------------------------------\n\n/**\n * Variation of KeyedVector that holds a default value to return when\n * valueFor() is called with a key that doesn't exist.\n */\ntemplate <typename KEY, typename VALUE>\nclass DefaultKeyedVector : public KeyedVector<KEY, VALUE>\n{\npublic:\n    inline                  DefaultKeyedVector(const VALUE& defValue = VALUE());\n            const VALUE&    valueFor(const KEY& key) const;\n\nprivate:\n            VALUE                                           mDefault;\n};\n\n// ---------------------------------------------------------------------------\n\ntemplate<typename KEY, typename VALUE> inline\nKeyedVector<KEY,VALUE>::KeyedVector()\n{\n}\n\ntemplate<typename KEY, typename VALUE> inline\nbool KeyedVector<KEY,VALUE>::isIdenticalTo(const KeyedVector<KEY,VALUE>& rhs) const {\n    return mVector.array() == rhs.mVector.array();\n}\n\ntemplate<typename KEY, typename VALUE> inline\nssize_t KeyedVector<KEY,VALUE>::indexOfKey(const KEY& key) const {\n    return mVector.indexOf( key_value_pair_t<KEY,VALUE>(key) );\n}\n\ntemplate<typename KEY, typename VALUE> inline\nconst VALUE& KeyedVector<KEY,VALUE>::valueFor(const KEY& key) const {\n    ssize_t i = this->indexOfKey(key);\n    LOG_ALWAYS_FATAL_IF(i<0, \"%s: key not found\", __PRETTY_FUNCTION__);\n    return mVector.itemAt(i).value;\n}\n\ntemplate<typename KEY, typename VALUE> inline\nconst VALUE& KeyedVector<KEY,VALUE>::valueAt(size_t index) const {\n    return mVector.itemAt(index).value;\n}\n\ntemplate<typename KEY, typename VALUE> inline\nconst VALUE& KeyedVector<KEY,VALUE>::operator[] (size_t index) const {\n    return valueAt(index);\n}\n\ntemplate<typename KEY, typename VALUE> inline\nconst KEY& KeyedVector<KEY,VALUE>::keyAt(size_t index) const {\n    return mVector.itemAt(index).key;\n}\n\ntemplate<typename KEY, typename VALUE> inline\nVALUE& KeyedVector<KEY,VALUE>::editValueFor(const KEY& key) {\n    ssize_t i = this->indexOfKey(key);\n    LOG_ALWAYS_FATAL_IF(i<0, \"%s: key not found\", __PRETTY_FUNCTION__);\n    return mVector.editItemAt(i).value;\n}\n\ntemplate<typename KEY, typename VALUE> inline\nVALUE& KeyedVector<KEY,VALUE>::editValueAt(size_t index) {\n    return mVector.editItemAt(index).value;\n}\n\ntemplate<typename KEY, typename VALUE> inline\nssize_t KeyedVector<KEY,VALUE>::add(const KEY& key, const VALUE& value) {\n    return mVector.add( key_value_pair_t<KEY,VALUE>(key, value) );\n}\n\ntemplate<typename KEY, typename VALUE> inline\nssize_t KeyedVector<KEY,VALUE>::replaceValueFor(const KEY& key, const VALUE& value) {\n    key_value_pair_t<KEY,VALUE> pair(key, value);\n    mVector.remove(pair);\n    return mVector.add(pair);\n}\n\ntemplate<typename KEY, typename VALUE> inline\nssize_t KeyedVector<KEY,VALUE>::replaceValueAt(size_t index, const VALUE& item) {\n    if (index<size()) {\n        mVector.editItemAt(index).value = item;\n        return index;\n    }\n    return BAD_INDEX;\n}\n\ntemplate<typename KEY, typename VALUE> inline\nssize_t KeyedVector<KEY,VALUE>::removeItem(const KEY& key) {\n    return mVector.remove(key_value_pair_t<KEY,VALUE>(key));\n}\n\ntemplate<typename KEY, typename VALUE> inline\nssize_t KeyedVector<KEY, VALUE>::removeItemsAt(size_t index, size_t count) {\n    return mVector.removeItemsAt(index, count);\n}\n\n// ---------------------------------------------------------------------------\n\ntemplate<typename KEY, typename VALUE> inline\nDefaultKeyedVector<KEY,VALUE>::DefaultKeyedVector(const VALUE& defValue)\n    : mDefault(defValue)\n{\n}\n\ntemplate<typename KEY, typename VALUE> inline\nconst VALUE& DefaultKeyedVector<KEY,VALUE>::valueFor(const KEY& key) const {\n    ssize_t i = this->indexOfKey(key);\n    return i >= 0 ? KeyedVector<KEY,VALUE>::valueAt(i) : mDefault;\n}\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_KEYED_VECTOR_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/LinearTransform.h",
    "content": "/*\n * Copyright (C) 2011 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_LINEAR_TRANSFORM_H\n#define _LIBS_UTILS_LINEAR_TRANSFORM_H\n\n#include <stdint.h>\n\nnamespace android {\n\n// LinearTransform defines a structure which hold the definition of a\n// transformation from single dimensional coordinate system A into coordinate\n// system B (and back again).  Values in A and in B are 64 bit, the linear\n// scale factor is expressed as a rational number using two 32 bit values.\n//\n// Specifically, let\n// f(a) = b\n// F(b) = f^-1(b) = a\n// then\n//\n// f(a) = (((a - a_zero) * a_to_b_numer) / a_to_b_denom) + b_zero;\n//\n// and\n//\n// F(b) = (((b - b_zero) * a_to_b_denom) / a_to_b_numer) + a_zero;\n//\nstruct LinearTransform {\n  int64_t  a_zero;\n  int64_t  b_zero;\n  int32_t  a_to_b_numer;\n  uint32_t a_to_b_denom;\n\n  // Transform from A->B\n  // Returns true on success, or false in the case of a singularity or an\n  // overflow.\n  bool doForwardTransform(int64_t a_in, int64_t* b_out) const;\n\n  // Transform from B->A\n  // Returns true on success, or false in the case of a singularity or an\n  // overflow.\n  bool doReverseTransform(int64_t b_in, int64_t* a_out) const;\n\n  // Helpers which will reduce the fraction N/D using Euclid's method.\n  template <class T> static void reduce(T* N, T* D);\n  static void reduce(int32_t* N, uint32_t* D);\n};\n\n\n}\n\n#endif  // _LIBS_UTILS_LINEAR_TRANSFORM_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/List.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// Templated list class.  Normally we'd use STL, but we don't have that.\n// This class mimics STL's interfaces.\n//\n// Objects are copied into the list with the '=' operator or with copy-\n// construction, so if the compiler's auto-generated versions won't work for\n// you, define your own.\n//\n// The only class you want to use from here is \"List\".\n//\n#ifndef _LIBS_UTILS_LIST_H\n#define _LIBS_UTILS_LIST_H\n\n#include <stddef.h>\n#include <stdint.h>\n\nnamespace android {\n\n/*\n * Doubly-linked list.  Instantiate with \"List<MyClass> myList\".\n *\n * Objects added to the list are copied using the assignment operator,\n * so this must be defined.\n */\ntemplate<typename T> \nclass List \n{\nprotected:\n    /*\n     * One element in the list.\n     */\n    class _Node {\n    public:\n        explicit _Node(const T& val) : mVal(val) {}\n        ~_Node() {}\n        inline T& getRef() { return mVal; }\n        inline const T& getRef() const { return mVal; }\n        inline _Node* getPrev() const { return mpPrev; }\n        inline _Node* getNext() const { return mpNext; }\n        inline void setVal(const T& val) { mVal = val; }\n        inline void setPrev(_Node* ptr) { mpPrev = ptr; }\n        inline void setNext(_Node* ptr) { mpNext = ptr; }\n    private:\n        friend class List;\n        friend class _ListIterator;\n        T           mVal;\n        _Node*      mpPrev;\n        _Node*      mpNext;\n    };\n\n    /*\n     * Iterator for walking through the list.\n     */\n    \n    template <typename TYPE>\n    struct CONST_ITERATOR {\n        typedef _Node const * NodePtr;\n        typedef const TYPE Type;\n    };\n    \n    template <typename TYPE>\n    struct NON_CONST_ITERATOR {\n        typedef _Node* NodePtr;\n        typedef TYPE Type;\n    };\n    \n    template<\n        typename U,\n        template <class> class Constness\n    > \n    class _ListIterator {\n        typedef _ListIterator<U, Constness>     _Iter;\n        typedef typename Constness<U>::NodePtr  _NodePtr;\n        typedef typename Constness<U>::Type     _Type;\n\n        explicit _ListIterator(_NodePtr ptr) : mpNode(ptr) {}\n\n    public:\n        _ListIterator() {}\n        _ListIterator(const _Iter& rhs) : mpNode(rhs.mpNode) {}\n        ~_ListIterator() {}\n        \n        // this will handle conversions from iterator to const_iterator\n        // (and also all convertible iterators)\n        // Here, in this implementation, the iterators can be converted\n        // if the nodes can be converted\n        template<typename V> explicit \n        _ListIterator(const V& rhs) : mpNode(rhs.mpNode) {}\n        \n\n        /*\n         * Dereference operator.  Used to get at the juicy insides.\n         */\n        _Type& operator*() const { return mpNode->getRef(); }\n        _Type* operator->() const { return &(mpNode->getRef()); }\n\n        /*\n         * Iterator comparison.\n         */\n        inline bool operator==(const _Iter& right) const { \n            return mpNode == right.mpNode; }\n        \n        inline bool operator!=(const _Iter& right) const { \n            return mpNode != right.mpNode; }\n\n        /*\n         * handle comparisons between iterator and const_iterator\n         */\n        template<typename OTHER>\n        inline bool operator==(const OTHER& right) const { \n            return mpNode == right.mpNode; }\n        \n        template<typename OTHER>\n        inline bool operator!=(const OTHER& right) const { \n            return mpNode != right.mpNode; }\n\n        /*\n         * Incr/decr, used to move through the list.\n         */\n        inline _Iter& operator++() {     // pre-increment\n            mpNode = mpNode->getNext();\n            return *this;\n        }\n        const _Iter operator++(int) {    // post-increment\n            _Iter tmp(*this);\n            mpNode = mpNode->getNext();\n            return tmp;\n        }\n        inline _Iter& operator--() {     // pre-increment\n            mpNode = mpNode->getPrev();\n            return *this;\n        }\n        const _Iter operator--(int) {   // post-increment\n            _Iter tmp(*this);\n            mpNode = mpNode->getPrev();\n            return tmp;\n        }\n\n        inline _NodePtr getNode() const { return mpNode; }\n\n        _NodePtr mpNode;    /* should be private, but older gcc fails */\n    private:\n        friend class List;\n    };\n\npublic:\n    List() {\n        prep();\n    }\n    List(const List<T>& src) {      // copy-constructor\n        prep();\n        insert(begin(), src.begin(), src.end());\n    }\n    virtual ~List() {\n        clear();\n        delete[] (unsigned char*) mpMiddle;\n    }\n\n    typedef _ListIterator<T, NON_CONST_ITERATOR> iterator;\n    typedef _ListIterator<T, CONST_ITERATOR> const_iterator;\n\n    List<T>& operator=(const List<T>& right);\n\n    /* returns true if the list is empty */\n    inline bool empty() const { return mpMiddle->getNext() == mpMiddle; }\n\n    /* return #of elements in list */\n    size_t size() const {\n        return size_t(distance(begin(), end()));\n    }\n\n    /*\n     * Return the first element or one past the last element.  The\n     * _Node* we're returning is converted to an \"iterator\" by a\n     * constructor in _ListIterator.\n     */\n    inline iterator begin() { \n        return iterator(mpMiddle->getNext()); \n    }\n    inline const_iterator begin() const { \n        return const_iterator(const_cast<_Node const*>(mpMiddle->getNext())); \n    }\n    inline iterator end() { \n        return iterator(mpMiddle); \n    }\n    inline const_iterator end() const { \n        return const_iterator(const_cast<_Node const*>(mpMiddle)); \n    }\n\n    /* add the object to the head or tail of the list */\n    void push_front(const T& val) { insert(begin(), val); }\n    void push_back(const T& val) { insert(end(), val); }\n\n    /* insert before the current node; returns iterator at new node */\n    iterator insert(iterator posn, const T& val) \n    {\n        _Node* newNode = new _Node(val);        // alloc & copy-construct\n        newNode->setNext(posn.getNode());\n        newNode->setPrev(posn.getNode()->getPrev());\n        posn.getNode()->getPrev()->setNext(newNode);\n        posn.getNode()->setPrev(newNode);\n        return iterator(newNode);\n    }\n\n    /* insert a range of elements before the current node */\n    void insert(iterator posn, const_iterator first, const_iterator last) {\n        for ( ; first != last; ++first)\n            insert(posn, *first);\n    }\n\n    /* remove one entry; returns iterator at next node */\n    iterator erase(iterator posn) {\n        _Node* pNext = posn.getNode()->getNext();\n        _Node* pPrev = posn.getNode()->getPrev();\n        pPrev->setNext(pNext);\n        pNext->setPrev(pPrev);\n        delete posn.getNode();\n        return iterator(pNext);\n    }\n\n    /* remove a range of elements */\n    iterator erase(iterator first, iterator last) {\n        while (first != last)\n            erase(first++);     // don't erase than incr later!\n        return iterator(last);\n    }\n\n    /* remove all contents of the list */\n    void clear() {\n        _Node* pCurrent = mpMiddle->getNext();\n        _Node* pNext;\n\n        while (pCurrent != mpMiddle) {\n            pNext = pCurrent->getNext();\n            delete pCurrent;\n            pCurrent = pNext;\n        }\n        mpMiddle->setPrev(mpMiddle);\n        mpMiddle->setNext(mpMiddle);\n    }\n\n    /*\n     * Measure the distance between two iterators.  On exist, \"first\"\n     * will be equal to \"last\".  The iterators must refer to the same\n     * list.\n     *\n     * FIXME: This is actually a generic iterator function. It should be a \n     * template function at the top-level with specializations for things like\n     * vector<>, which can just do pointer math). Here we limit it to\n     * _ListIterator of the same type but different constness.\n     */\n    template<\n        typename U,\n        template <class> class CL,\n        template <class> class CR\n    > \n    ptrdiff_t distance(\n            _ListIterator<U, CL> first, _ListIterator<U, CR> last) const \n    {\n        ptrdiff_t count = 0;\n        while (first != last) {\n            ++first;\n            ++count;\n        }\n        return count;\n    }\n\nprivate:\n    /*\n     * I want a _Node but don't need it to hold valid data.  More\n     * to the point, I don't want T's constructor to fire, since it\n     * might have side-effects or require arguments.  So, we do this\n     * slightly uncouth storage alloc.\n     */\n    void prep() {\n        mpMiddle = (_Node*) new unsigned char[sizeof(_Node)];\n        mpMiddle->setPrev(mpMiddle);\n        mpMiddle->setNext(mpMiddle);\n    }\n\n    /*\n     * This node plays the role of \"pointer to head\" and \"pointer to tail\".\n     * It sits in the middle of a circular list of nodes.  The iterator\n     * runs around the circle until it encounters this one.\n     */\n    _Node*      mpMiddle;\n};\n\n/*\n * Assignment operator.\n *\n * The simplest way to do this would be to clear out the target list and\n * fill it with the source.  However, we can speed things along by\n * re-using existing elements.\n */\ntemplate<class T>\nList<T>& List<T>::operator=(const List<T>& right)\n{\n    if (this == &right)\n        return *this;       // self-assignment\n    iterator firstDst = begin();\n    iterator lastDst = end();\n    const_iterator firstSrc = right.begin();\n    const_iterator lastSrc = right.end();\n    while (firstSrc != lastSrc && firstDst != lastDst)\n        *firstDst++ = *firstSrc++;\n    if (firstSrc == lastSrc)        // ran out of elements in source?\n        erase(firstDst, lastDst);   // yes, erase any extras\n    else\n        insert(lastDst, firstSrc, lastSrc);     // copy remaining over\n    return *this;\n}\n\n}; // namespace android\n\n#endif // _LIBS_UTILS_LIST_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Log.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// C/C++ logging functions.  See the logging documentation for API details.\n//\n// We'd like these to be available from C code (in case we import some from\n// somewhere), so this has a C interface.\n//\n// The output will be correct when the log file is shared between multiple\n// threads and/or multiple processes so long as the operating system\n// supports O_APPEND.  These calls have mutex-protected data structures\n// and so are NOT reentrant.  Do not use LOG in a signal handler.\n//\n#ifndef _LIBS_UTILS_LOG_H\n#define _LIBS_UTILS_LOG_H\n\n#include <cutils/log.h>\n#include <sys/types.h>\n\n#ifdef __cplusplus\n\nnamespace android {\n\n/*\n * A very simple utility that yells in the log when an operation takes too long.\n */\nclass LogIfSlow {\npublic:\n    LogIfSlow(const char* tag, android_LogPriority priority,\n            int timeoutMillis, const char* message);\n    ~LogIfSlow();\n\nprivate:\n    const char* const mTag;\n    const android_LogPriority mPriority;\n    const int mTimeoutMillis;\n    const char* const mMessage;\n    const int64_t mStart;\n};\n\n/*\n * Writes the specified debug log message if this block takes longer than the\n * specified number of milliseconds to run.  Includes the time actually taken.\n *\n * {\n *     ALOGD_IF_SLOW(50, \"Excessive delay doing something.\");\n *     doSomething();\n * }\n */\n#define ALOGD_IF_SLOW(timeoutMillis, message) \\\n    android::LogIfSlow _logIfSlow(LOG_TAG, ANDROID_LOG_DEBUG, timeoutMillis, message);\n\n} // namespace android\n\n#endif // __cplusplus\n\n#endif // _LIBS_UTILS_LOG_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Looper.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef UTILS_LOOPER_H\n#define UTILS_LOOPER_H\n\n#include <utils/threads.h>\n#include <utils/RefBase.h>\n#include <utils/KeyedVector.h>\n#include <utils/Timers.h>\n\n#include <sys/epoll.h>\n\nnamespace android {\n\n/*\n * NOTE: Since Looper is used to implement the NDK ALooper, the Looper\n * enums and the signature of Looper_callbackFunc need to align with\n * that implementation.\n */\n\n/**\n * For callback-based event loops, this is the prototype of the function\n * that is called when a file descriptor event occurs.\n * It is given the file descriptor it is associated with,\n * a bitmask of the poll events that were triggered (typically EVENT_INPUT),\n * and the data pointer that was originally supplied.\n *\n * Implementations should return 1 to continue receiving callbacks, or 0\n * to have this file descriptor and callback unregistered from the looper.\n */\ntypedef int (*Looper_callbackFunc)(int fd, int events, void* data);\n\n/**\n * A message that can be posted to a Looper.\n */\nstruct Message {\n    Message() : what(0) { }\n    Message(int what) : what(what) { }\n\n    /* The message type. (interpretation is left up to the handler) */\n    int what;\n};\n\n\n/**\n * Interface for a Looper message handler.\n *\n * The Looper holds a strong reference to the message handler whenever it has\n * a message to deliver to it.  Make sure to call Looper::removeMessages\n * to remove any pending messages destined for the handler so that the handler\n * can be destroyed.\n */\nclass MessageHandler : public virtual RefBase {\nprotected:\n    virtual ~MessageHandler() { }\n\npublic:\n    /**\n     * Handles a message.\n     */\n    virtual void handleMessage(const Message& message) = 0;\n};\n\n\n/**\n * A simple proxy that holds a weak reference to a message handler.\n */\nclass WeakMessageHandler : public MessageHandler {\nprotected:\n    virtual ~WeakMessageHandler();\n\npublic:\n    WeakMessageHandler(const wp<MessageHandler>& handler);\n    virtual void handleMessage(const Message& message);\n\nprivate:\n    wp<MessageHandler> mHandler;\n};\n\n\n/**\n * A looper callback.\n */\nclass LooperCallback : public virtual RefBase {\nprotected:\n    virtual ~LooperCallback() { }\n\npublic:\n    /**\n     * Handles a poll event for the given file descriptor.\n     * It is given the file descriptor it is associated with,\n     * a bitmask of the poll events that were triggered (typically EVENT_INPUT),\n     * and the data pointer that was originally supplied.\n     *\n     * Implementations should return 1 to continue receiving callbacks, or 0\n     * to have this file descriptor and callback unregistered from the looper.\n     */\n    virtual int handleEvent(int fd, int events, void* data) = 0;\n};\n\n/**\n * Wraps a Looper_callbackFunc function pointer.\n */\nclass SimpleLooperCallback : public LooperCallback {\nprotected:\n    virtual ~SimpleLooperCallback();\n\npublic:\n    SimpleLooperCallback(Looper_callbackFunc callback);\n    virtual int handleEvent(int fd, int events, void* data);\n\nprivate:\n    Looper_callbackFunc mCallback;\n};\n\n/**\n * A polling loop that supports monitoring file descriptor events, optionally\n * using callbacks.  The implementation uses epoll() internally.\n *\n * A looper can be associated with a thread although there is no requirement that it must be.\n */\nclass Looper : public RefBase {\nprotected:\n    virtual ~Looper();\n\npublic:\n    enum {\n        /**\n         * Result from Looper_pollOnce() and Looper_pollAll():\n         * The poll was awoken using wake() before the timeout expired\n         * and no callbacks were executed and no other file descriptors were ready.\n         */\n        POLL_WAKE = -1,\n\n        /**\n         * Result from Looper_pollOnce() and Looper_pollAll():\n         * One or more callbacks were executed.\n         */\n        POLL_CALLBACK = -2,\n\n        /**\n         * Result from Looper_pollOnce() and Looper_pollAll():\n         * The timeout expired.\n         */\n        POLL_TIMEOUT = -3,\n\n        /**\n         * Result from Looper_pollOnce() and Looper_pollAll():\n         * An error occurred.\n         */\n        POLL_ERROR = -4,\n    };\n\n    /**\n     * Flags for file descriptor events that a looper can monitor.\n     *\n     * These flag bits can be combined to monitor multiple events at once.\n     */\n    enum {\n        /**\n         * The file descriptor is available for read operations.\n         */\n        EVENT_INPUT = 1 << 0,\n\n        /**\n         * The file descriptor is available for write operations.\n         */\n        EVENT_OUTPUT = 1 << 1,\n\n        /**\n         * The file descriptor has encountered an error condition.\n         *\n         * The looper always sends notifications about errors; it is not necessary\n         * to specify this event flag in the requested event set.\n         */\n        EVENT_ERROR = 1 << 2,\n\n        /**\n         * The file descriptor was hung up.\n         * For example, indicates that the remote end of a pipe or socket was closed.\n         *\n         * The looper always sends notifications about hangups; it is not necessary\n         * to specify this event flag in the requested event set.\n         */\n        EVENT_HANGUP = 1 << 3,\n\n        /**\n         * The file descriptor is invalid.\n         * For example, the file descriptor was closed prematurely.\n         *\n         * The looper always sends notifications about invalid file descriptors; it is not necessary\n         * to specify this event flag in the requested event set.\n         */\n        EVENT_INVALID = 1 << 4,\n    };\n\n    enum {\n        /**\n         * Option for Looper_prepare: this looper will accept calls to\n         * Looper_addFd() that do not have a callback (that is provide NULL\n         * for the callback).  In this case the caller of Looper_pollOnce()\n         * or Looper_pollAll() MUST check the return from these functions to\n         * discover when data is available on such fds and process it.\n         */\n        PREPARE_ALLOW_NON_CALLBACKS = 1<<0\n    };\n\n    /**\n     * Creates a looper.\n     *\n     * If allowNonCallbaks is true, the looper will allow file descriptors to be\n     * registered without associated callbacks.  This assumes that the caller of\n     * pollOnce() is prepared to handle callback-less events itself.\n     */\n    Looper(bool allowNonCallbacks);\n\n    /**\n     * Returns whether this looper instance allows the registration of file descriptors\n     * using identifiers instead of callbacks.\n     */\n    bool getAllowNonCallbacks() const;\n\n    /**\n     * Waits for events to be available, with optional timeout in milliseconds.\n     * Invokes callbacks for all file descriptors on which an event occurred.\n     *\n     * If the timeout is zero, returns immediately without blocking.\n     * If the timeout is negative, waits indefinitely until an event appears.\n     *\n     * Returns POLL_WAKE if the poll was awoken using wake() before\n     * the timeout expired and no callbacks were invoked and no other file\n     * descriptors were ready.\n     *\n     * Returns POLL_CALLBACK if one or more callbacks were invoked.\n     *\n     * Returns POLL_TIMEOUT if there was no data before the given\n     * timeout expired.\n     *\n     * Returns POLL_ERROR if an error occurred.\n     *\n     * Returns a value >= 0 containing an identifier if its file descriptor has data\n     * and it has no callback function (requiring the caller here to handle it).\n     * In this (and only this) case outFd, outEvents and outData will contain the poll\n     * events and data associated with the fd, otherwise they will be set to NULL.\n     *\n     * This method does not return until it has finished invoking the appropriate callbacks\n     * for all file descriptors that were signalled.\n     */\n    int pollOnce(int timeoutMillis, int* outFd, int* outEvents, void** outData);\n    inline int pollOnce(int timeoutMillis) {\n        return pollOnce(timeoutMillis, NULL, NULL, NULL);\n    }\n\n    /**\n     * Like pollOnce(), but performs all pending callbacks until all\n     * data has been consumed or a file descriptor is available with no callback.\n     * This function will never return POLL_CALLBACK.\n     */\n    int pollAll(int timeoutMillis, int* outFd, int* outEvents, void** outData);\n    inline int pollAll(int timeoutMillis) {\n        return pollAll(timeoutMillis, NULL, NULL, NULL);\n    }\n\n    /**\n     * Wakes the poll asynchronously.\n     *\n     * This method can be called on any thread.\n     * This method returns immediately.\n     */\n    void wake();\n\n    /**\n     * Adds a new file descriptor to be polled by the looper.\n     * If the same file descriptor was previously added, it is replaced.\n     *\n     * \"fd\" is the file descriptor to be added.\n     * \"ident\" is an identifier for this event, which is returned from pollOnce().\n     * The identifier must be >= 0, or POLL_CALLBACK if providing a non-NULL callback.\n     * \"events\" are the poll events to wake up on.  Typically this is EVENT_INPUT.\n     * \"callback\" is the function to call when there is an event on the file descriptor.\n     * \"data\" is a private data pointer to supply to the callback.\n     *\n     * There are two main uses of this function:\n     *\n     * (1) If \"callback\" is non-NULL, then this function will be called when there is\n     * data on the file descriptor.  It should execute any events it has pending,\n     * appropriately reading from the file descriptor.  The 'ident' is ignored in this case.\n     *\n     * (2) If \"callback\" is NULL, the 'ident' will be returned by Looper_pollOnce\n     * when its file descriptor has data available, requiring the caller to take\n     * care of processing it.\n     *\n     * Returns 1 if the file descriptor was added, 0 if the arguments were invalid.\n     *\n     * This method can be called on any thread.\n     * This method may block briefly if it needs to wake the poll.\n     *\n     * The callback may either be specified as a bare function pointer or as a smart\n     * pointer callback object.  The smart pointer should be preferred because it is\n     * easier to avoid races when the callback is removed from a different thread.\n     * See removeFd() for details.\n     */\n    int addFd(int fd, int ident, int events, Looper_callbackFunc callback, void* data);\n    int addFd(int fd, int ident, int events, const sp<LooperCallback>& callback, void* data);\n\n    /**\n     * Removes a previously added file descriptor from the looper.\n     *\n     * When this method returns, it is safe to close the file descriptor since the looper\n     * will no longer have a reference to it.  However, it is possible for the callback to\n     * already be running or for it to run one last time if the file descriptor was already\n     * signalled.  Calling code is responsible for ensuring that this case is safely handled.\n     * For example, if the callback takes care of removing itself during its own execution either\n     * by returning 0 or by calling this method, then it can be guaranteed to not be invoked\n     * again at any later time unless registered anew.\n     *\n     * A simple way to avoid this problem is to use the version of addFd() that takes\n     * a sp<LooperCallback> instead of a bare function pointer.  The LooperCallback will\n     * be released at the appropriate time by the Looper.\n     *\n     * Returns 1 if the file descriptor was removed, 0 if none was previously registered.\n     *\n     * This method can be called on any thread.\n     * This method may block briefly if it needs to wake the poll.\n     */\n    int removeFd(int fd);\n\n    /**\n     * Enqueues a message to be processed by the specified handler.\n     *\n     * The handler must not be null.\n     * This method can be called on any thread.\n     */\n    void sendMessage(const sp<MessageHandler>& handler, const Message& message);\n\n    /**\n     * Enqueues a message to be processed by the specified handler after all pending messages\n     * after the specified delay.\n     *\n     * The time delay is specified in uptime nanoseconds.\n     * The handler must not be null.\n     * This method can be called on any thread.\n     */\n    void sendMessageDelayed(nsecs_t uptimeDelay, const sp<MessageHandler>& handler,\n            const Message& message);\n\n    /**\n     * Enqueues a message to be processed by the specified handler after all pending messages\n     * at the specified time.\n     *\n     * The time is specified in uptime nanoseconds.\n     * The handler must not be null.\n     * This method can be called on any thread.\n     */\n    void sendMessageAtTime(nsecs_t uptime, const sp<MessageHandler>& handler,\n            const Message& message);\n\n    /**\n     * Removes all messages for the specified handler from the queue.\n     *\n     * The handler must not be null.\n     * This method can be called on any thread.\n     */\n    void removeMessages(const sp<MessageHandler>& handler);\n\n    /**\n     * Removes all messages of a particular type for the specified handler from the queue.\n     *\n     * The handler must not be null.\n     * This method can be called on any thread.\n     */\n    void removeMessages(const sp<MessageHandler>& handler, int what);\n\n    /**\n     * Returns whether this looper's thread is currently polling for more work to do.\n     * This is a good signal that the loop is still alive rather than being stuck\n     * handling a callback.  Note that this method is intrinsically racy, since the\n     * state of the loop can change before you get the result back.\n     */\n    bool isPolling() const;\n\n    /**\n     * Prepares a looper associated with the calling thread, and returns it.\n     * If the thread already has a looper, it is returned.  Otherwise, a new\n     * one is created, associated with the thread, and returned.\n     *\n     * The opts may be PREPARE_ALLOW_NON_CALLBACKS or 0.\n     */\n    static sp<Looper> prepare(int opts);\n\n    /**\n     * Sets the given looper to be associated with the calling thread.\n     * If another looper is already associated with the thread, it is replaced.\n     *\n     * If \"looper\" is NULL, removes the currently associated looper.\n     */\n    static void setForThread(const sp<Looper>& looper);\n\n    /**\n     * Returns the looper associated with the calling thread, or NULL if\n     * there is not one.\n     */\n    static sp<Looper> getForThread();\n\nprivate:\n    struct Request {\n        int fd;\n        int ident;\n        int events;\n        int seq;\n        sp<LooperCallback> callback;\n        void* data;\n\n        void initEventItem(struct epoll_event* eventItem) const;\n    };\n\n    struct Response {\n        int events;\n        Request request;\n    };\n\n    struct MessageEnvelope {\n        MessageEnvelope() : uptime(0) { }\n\n        MessageEnvelope(nsecs_t uptime, const sp<MessageHandler> handler,\n                const Message& message) : uptime(uptime), handler(handler), message(message) {\n        }\n\n        nsecs_t uptime;\n        sp<MessageHandler> handler;\n        Message message;\n    };\n\n    const bool mAllowNonCallbacks; // immutable\n\n    int mWakeEventFd;  // immutable\n    Mutex mLock;\n\n    Vector<MessageEnvelope> mMessageEnvelopes; // guarded by mLock\n    bool mSendingMessage; // guarded by mLock\n\n    // Whether we are currently waiting for work.  Not protected by a lock,\n    // any use of it is racy anyway.\n    volatile bool mPolling;\n\n    int mEpollFd; // guarded by mLock but only modified on the looper thread\n    bool mEpollRebuildRequired; // guarded by mLock\n\n    // Locked list of file descriptor monitoring requests.\n    KeyedVector<int, Request> mRequests;  // guarded by mLock\n    int mNextRequestSeq;\n\n    // This state is only used privately by pollOnce and does not require a lock since\n    // it runs on a single thread.\n    Vector<Response> mResponses;\n    size_t mResponseIndex;\n    nsecs_t mNextMessageUptime; // set to LLONG_MAX when none\n\n    int pollInner(int timeoutMillis);\n    int removeFd(int fd, int seq);\n    void awoken();\n    void pushResponse(int events, const Request& request);\n    void rebuildEpollLocked();\n    void scheduleEpollRebuildLocked();\n\n    static void initTLSKey();\n    static void threadDestructor(void *st);\n    static void initEpollEvent(struct epoll_event* eventItem);\n};\n\n} // namespace android\n\n#endif // UTILS_LOOPER_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/LruCache.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UTILS_LRU_CACHE_H\n#define ANDROID_UTILS_LRU_CACHE_H\n\n#include <UniquePtr.h>\n#include <utils/BasicHashtable.h>\n\nnamespace android {\n\n/**\n * GenerationCache callback used when an item is removed\n */\ntemplate<typename EntryKey, typename EntryValue>\nclass OnEntryRemoved {\npublic:\n    virtual ~OnEntryRemoved() { };\n    virtual void operator()(EntryKey& key, EntryValue& value) = 0;\n}; // class OnEntryRemoved\n\ntemplate <typename TKey, typename TValue>\nclass LruCache {\npublic:\n    explicit LruCache(uint32_t maxCapacity);\n\n    enum Capacity {\n        kUnlimitedCapacity,\n    };\n\n    void setOnEntryRemovedListener(OnEntryRemoved<TKey, TValue>* listener);\n    size_t size() const;\n    const TValue& get(const TKey& key);\n    bool put(const TKey& key, const TValue& value);\n    bool remove(const TKey& key);\n    bool removeOldest();\n    void clear();\n    const TValue& peekOldestValue();\n\n    class Iterator {\n    public:\n        Iterator(const LruCache<TKey, TValue>& cache): mCache(cache), mIndex(-1) {\n        }\n\n        bool next() {\n            mIndex = mCache.mTable->next(mIndex);\n            return (ssize_t)mIndex != -1;\n        }\n\n        size_t index() const {\n            return mIndex;\n        }\n\n        const TValue& value() const {\n            return mCache.mTable->entryAt(mIndex).value;\n        }\n\n        const TKey& key() const {\n            return mCache.mTable->entryAt(mIndex).key;\n        }\n    private:\n        const LruCache<TKey, TValue>& mCache;\n        size_t mIndex;\n    };\n\nprivate:\n    LruCache(const LruCache& that);  // disallow copy constructor\n\n    struct Entry {\n        TKey key;\n        TValue value;\n        Entry* parent;\n        Entry* child;\n\n        Entry(TKey key_, TValue value_) : key(key_), value(value_), parent(NULL), child(NULL) {\n        }\n        const TKey& getKey() const { return key; }\n    };\n\n    void attachToCache(Entry& entry);\n    void detachFromCache(Entry& entry);\n    void rehash(size_t newCapacity);\n\n    UniquePtr<BasicHashtable<TKey, Entry> > mTable;\n    OnEntryRemoved<TKey, TValue>* mListener;\n    Entry* mOldest;\n    Entry* mYoungest;\n    uint32_t mMaxCapacity;\n    TValue mNullValue;\n};\n\n// Implementation is here, because it's fully templated\ntemplate <typename TKey, typename TValue>\nLruCache<TKey, TValue>::LruCache(uint32_t maxCapacity)\n    : mTable(new BasicHashtable<TKey, Entry>)\n    , mListener(NULL)\n    , mOldest(NULL)\n    , mYoungest(NULL)\n    , mMaxCapacity(maxCapacity)\n    , mNullValue(NULL) {\n};\n\ntemplate<typename K, typename V>\nvoid LruCache<K, V>::setOnEntryRemovedListener(OnEntryRemoved<K, V>* listener) {\n    mListener = listener;\n}\n\ntemplate <typename TKey, typename TValue>\nsize_t LruCache<TKey, TValue>::size() const {\n    return mTable->size();\n}\n\ntemplate <typename TKey, typename TValue>\nconst TValue& LruCache<TKey, TValue>::get(const TKey& key) {\n    hash_t hash = hash_type(key);\n    ssize_t index = mTable->find(-1, hash, key);\n    if (index == -1) {\n        return mNullValue;\n    }\n    Entry& entry = mTable->editEntryAt(index);\n    detachFromCache(entry);\n    attachToCache(entry);\n    return entry.value;\n}\n\ntemplate <typename TKey, typename TValue>\nbool LruCache<TKey, TValue>::put(const TKey& key, const TValue& value) {\n    if (mMaxCapacity != kUnlimitedCapacity && size() >= mMaxCapacity) {\n        removeOldest();\n    }\n\n    hash_t hash = hash_type(key);\n    ssize_t index = mTable->find(-1, hash, key);\n    if (index >= 0) {\n        return false;\n    }\n    if (!mTable->hasMoreRoom()) {\n        rehash(mTable->capacity() * 2);\n    }\n\n    // Would it be better to initialize a blank entry and assign key, value?\n    Entry initEntry(key, value);\n    index = mTable->add(hash, initEntry);\n    Entry& entry = mTable->editEntryAt(index);\n    attachToCache(entry);\n    return true;\n}\n\ntemplate <typename TKey, typename TValue>\nbool LruCache<TKey, TValue>::remove(const TKey& key) {\n    hash_t hash = hash_type(key);\n    ssize_t index = mTable->find(-1, hash, key);\n    if (index < 0) {\n        return false;\n    }\n    Entry& entry = mTable->editEntryAt(index);\n    if (mListener) {\n        (*mListener)(entry.key, entry.value);\n    }\n    detachFromCache(entry);\n    mTable->removeAt(index);\n    return true;\n}\n\ntemplate <typename TKey, typename TValue>\nbool LruCache<TKey, TValue>::removeOldest() {\n    if (mOldest != NULL) {\n        return remove(mOldest->key);\n        // TODO: should probably abort if false\n    }\n    return false;\n}\n\ntemplate <typename TKey, typename TValue>\nconst TValue& LruCache<TKey, TValue>::peekOldestValue() {\n    if (mOldest) {\n        return mOldest->value;\n    }\n    return mNullValue;\n}\n\ntemplate <typename TKey, typename TValue>\nvoid LruCache<TKey, TValue>::clear() {\n    if (mListener) {\n        for (Entry* p = mOldest; p != NULL; p = p->child) {\n            (*mListener)(p->key, p->value);\n        }\n    }\n    mYoungest = NULL;\n    mOldest = NULL;\n    mTable->clear();\n}\n\ntemplate <typename TKey, typename TValue>\nvoid LruCache<TKey, TValue>::attachToCache(Entry& entry) {\n    if (mYoungest == NULL) {\n        mYoungest = mOldest = &entry;\n    } else {\n        entry.parent = mYoungest;\n        mYoungest->child = &entry;\n        mYoungest = &entry;\n    }\n}\n\ntemplate <typename TKey, typename TValue>\nvoid LruCache<TKey, TValue>::detachFromCache(Entry& entry) {\n    if (entry.parent != NULL) {\n        entry.parent->child = entry.child;\n    } else {\n        mOldest = entry.child;\n    }\n    if (entry.child != NULL) {\n        entry.child->parent = entry.parent;\n    } else {\n        mYoungest = entry.parent;\n    }\n\n    entry.parent = NULL;\n    entry.child = NULL;\n}\n\ntemplate <typename TKey, typename TValue>\nvoid LruCache<TKey, TValue>::rehash(size_t newCapacity) {\n    UniquePtr<BasicHashtable<TKey, Entry> > oldTable(mTable.release());\n    Entry* oldest = mOldest;\n\n    mOldest = NULL;\n    mYoungest = NULL;\n    mTable.reset(new BasicHashtable<TKey, Entry>(newCapacity));\n    for (Entry* p = oldest; p != NULL; p = p->child) {\n        put(p->key, p->value);\n    }\n}\n\n}\n\n#endif // ANDROID_UTILS_LRU_CACHE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Mutex.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_MUTEX_H\n#define _LIBS_UTILS_MUTEX_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <time.h>\n\n#if !defined(_WIN32)\n# include <pthread.h>\n#endif\n\n#include <utils/Errors.h>\n#include <utils/Timers.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n// ---------------------------------------------------------------------------\n\nclass Condition;\n\n/*\n * Simple mutex class.  The implementation is system-dependent.\n *\n * The mutex must be unlocked by the thread that locked it.  They are not\n * recursive, i.e. the same thread can't lock it multiple times.\n */\nclass Mutex {\npublic:\n    enum {\n        PRIVATE = 0,\n        SHARED = 1\n    };\n\n                Mutex();\n                Mutex(const char* name);\n                Mutex(int type, const char* name = NULL);\n                ~Mutex();\n\n    // lock or unlock the mutex\n    status_t    lock();\n    void        unlock();\n\n    // lock if possible; returns 0 on success, error otherwise\n    status_t    tryLock();\n\n#if HAVE_ANDROID_OS\n    // lock the mutex, but don't wait longer than timeoutMilliseconds.\n    // Returns 0 on success, TIMED_OUT for failure due to timeout expiration.\n    //\n    // OSX doesn't have pthread_mutex_timedlock() or equivalent. To keep\n    // capabilities consistent across host OSes, this method is only available\n    // when building Android binaries.\n    status_t    timedLock(nsecs_t timeoutMilliseconds);\n#endif\n\n    // Manages the mutex automatically. It'll be locked when Autolock is\n    // constructed and released when Autolock goes out of scope.\n    class Autolock {\n    public:\n        inline Autolock(Mutex& mutex) : mLock(mutex)  { mLock.lock(); }\n        inline Autolock(Mutex* mutex) : mLock(*mutex) { mLock.lock(); }\n        inline ~Autolock() { mLock.unlock(); }\n    private:\n        Mutex& mLock;\n    };\n\nprivate:\n    friend class Condition;\n\n    // A mutex cannot be copied\n                Mutex(const Mutex&);\n    Mutex&      operator = (const Mutex&);\n\n#if !defined(_WIN32)\n    pthread_mutex_t mMutex;\n#else\n    void    _init();\n    void*   mState;\n#endif\n};\n\n// ---------------------------------------------------------------------------\n\n#if !defined(_WIN32)\n\ninline Mutex::Mutex() {\n    pthread_mutex_init(&mMutex, NULL);\n}\ninline Mutex::Mutex(__attribute__((unused)) const char* name) {\n    pthread_mutex_init(&mMutex, NULL);\n}\ninline Mutex::Mutex(int type, __attribute__((unused)) const char* name) {\n    if (type == SHARED) {\n        pthread_mutexattr_t attr;\n        pthread_mutexattr_init(&attr);\n        pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED);\n        pthread_mutex_init(&mMutex, &attr);\n        pthread_mutexattr_destroy(&attr);\n    } else {\n        pthread_mutex_init(&mMutex, NULL);\n    }\n}\ninline Mutex::~Mutex() {\n    pthread_mutex_destroy(&mMutex);\n}\ninline status_t Mutex::lock() {\n    return -pthread_mutex_lock(&mMutex);\n}\ninline void Mutex::unlock() {\n    pthread_mutex_unlock(&mMutex);\n}\ninline status_t Mutex::tryLock() {\n    return -pthread_mutex_trylock(&mMutex);\n}\n#if HAVE_ANDROID_OS\ninline status_t Mutex::timedLock(nsecs_t timeoutNs) {\n    const struct timespec ts = {\n        /* .tv_sec = */ static_cast<time_t>(timeoutNs / 1000000000),\n        /* .tv_nsec = */ static_cast<long>(timeoutNs % 1000000000),\n    };\n    return -pthread_mutex_timedlock(&mMutex, &ts);\n}\n#endif\n\n#endif // !defined(_WIN32)\n\n// ---------------------------------------------------------------------------\n\n/*\n * Automatic mutex.  Declare one of these at the top of a function.\n * When the function returns, it will go out of scope, and release the\n * mutex.\n */\n\ntypedef Mutex::Autolock AutoMutex;\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n// ---------------------------------------------------------------------------\n\n#endif // _LIBS_UTILS_MUTEX_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/NativeHandle.h",
    "content": "/*\n * Copyright 2014 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_NATIVE_HANDLE_H\n#define ANDROID_NATIVE_HANDLE_H\n\n#include <utils/RefBase.h>\n#include <utils/StrongPointer.h>\n\ntypedef struct native_handle native_handle_t;\n\nnamespace android {\n\nclass NativeHandle: public LightRefBase<NativeHandle> {\npublic:\n    // Create a refcounted wrapper around a native_handle_t, and declare\n    // whether the wrapper owns the handle (so that it should clean up the\n    // handle upon destruction) or not.\n    // If handle is NULL, no NativeHandle will be created.\n    static sp<NativeHandle> create(native_handle_t* handle, bool ownsHandle);\n\n    const native_handle_t* handle() const {\n        return mHandle;\n    }\n\nprivate:\n    // for access to the destructor\n    friend class LightRefBase<NativeHandle>;\n\n    NativeHandle(native_handle_t* handle, bool ownsHandle);\n    virtual ~NativeHandle();\n\n    native_handle_t* mHandle;\n    bool mOwnsHandle;\n\n    // non-copyable\n    NativeHandle(const NativeHandle&);\n    NativeHandle& operator=(const NativeHandle&);\n};\n\n} // namespace android\n\n#endif // ANDROID_NATIVE_HANDLE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Printer.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_PRINTER_H\n#define ANDROID_PRINTER_H\n\n#include <android/log.h>\n\nnamespace android {\n\n// Interface for printing to an arbitrary data stream\nclass Printer {\npublic:\n    // Print a new line specified by 'string'. \\n is appended automatically.\n    // -- Assumes that the string has no new line in it.\n    virtual void printLine(const char* string = \"\") = 0;\n\n    // Print a new line specified by the format string. \\n is appended automatically.\n    // -- Assumes that the resulting string has no new line in it.\n    virtual void printFormatLine(const char* format, ...) __attribute__((format (printf, 2, 3)));\n\nprotected:\n    Printer();\n    virtual ~Printer();\n}; // class Printer\n\n// Print to logcat\nclass LogPrinter : public Printer {\npublic:\n    // Create a printer using the specified logcat and log priority\n    // - Unless ignoreBlankLines is false, print blank lines to logcat\n    // (Note that the default ALOG behavior is to ignore blank lines)\n    LogPrinter(const char* logtag,\n               android_LogPriority priority = ANDROID_LOG_DEBUG,\n               const char* prefix = 0,\n               bool ignoreBlankLines = false);\n\n    // Print the specified line to logcat. No \\n at the end is necessary.\n    virtual void printLine(const char* string);\n\nprivate:\n    void printRaw(const char* string);\n\n    const char* mLogTag;\n    android_LogPriority mPriority;\n    const char* mPrefix;\n    bool mIgnoreBlankLines;\n}; // class LogPrinter\n\n// Print to a file descriptor\nclass FdPrinter : public Printer {\npublic:\n    // Create a printer using the specified file descriptor.\n    // - Each line will be prefixed with 'indent' number of blank spaces.\n    // - In addition, each line will be prefixed with the 'prefix' string.\n    FdPrinter(int fd, unsigned int indent = 0, const char* prefix = 0);\n\n    // Print the specified line to the file descriptor. \\n is appended automatically.\n    virtual void printLine(const char* string);\n\nprivate:\n    enum {\n        MAX_FORMAT_STRING = 20,\n    };\n\n    int mFd;\n    unsigned int mIndent;\n    const char* mPrefix;\n    char mFormatString[MAX_FORMAT_STRING];\n}; // class FdPrinter\n\nclass String8;\n\n// Print to a String8\nclass String8Printer : public Printer {\npublic:\n    // Create a printer using the specified String8 as the target.\n    // - In addition, each line will be prefixed with the 'prefix' string.\n    // - target's memory lifetime must be a superset of this String8Printer.\n    String8Printer(String8* target, const char* prefix = 0);\n\n    // Append the specified line to the String8. \\n is appended automatically.\n    virtual void printLine(const char* string);\n\nprivate:\n    String8* mTarget;\n    const char* mPrefix;\n}; // class String8Printer\n\n// Print to an existing Printer by adding a prefix to each line\nclass PrefixPrinter : public Printer {\npublic:\n    // Create a printer using the specified printer as the target.\n    PrefixPrinter(Printer& printer, const char* prefix);\n\n    // Print the line (prefixed with prefix) using the printer.\n    virtual void printLine(const char* string);\n\nprivate:\n    Printer& mPrinter;\n    const char* mPrefix;\n};\n\n}; // namespace android\n\n#endif // ANDROID_PRINTER_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/ProcessCallStack.h",
    "content": "/*\n * Copyright (C) 2013 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_PROCESS_CALLSTACK_H\n#define ANDROID_PROCESS_CALLSTACK_H\n\n#include <utils/CallStack.h>\n#include <android/log.h>\n#include <utils/KeyedVector.h>\n#include <utils/String8.h>\n\n#include <time.h>\n#include <sys/types.h>\n\nnamespace android {\n\nclass Printer;\n\n// Collect/print the call stack (function, file, line) traces for all threads in a process.\nclass ProcessCallStack {\npublic:\n    // Create an empty call stack. No-op.\n    ProcessCallStack();\n    // Copy the existing process callstack (no other side effects).\n    ProcessCallStack(const ProcessCallStack& rhs);\n    ~ProcessCallStack();\n\n    // Immediately collect the stack traces for all threads.\n    void update();\n\n    // Print all stack traces to the log using the supplied logtag.\n    void log(const char* logtag, android_LogPriority priority = ANDROID_LOG_DEBUG,\n             const char* prefix = 0) const;\n\n    // Dump all stack traces to the specified file descriptor.\n    void dump(int fd, int indent = 0, const char* prefix = 0) const;\n\n    // Return a string (possibly very long) containing all the stack traces.\n    String8 toString(const char* prefix = 0) const;\n\n    // Dump a serialized representation of all the stack traces to the specified printer.\n    void print(Printer& printer) const;\n\n    // Get the number of threads whose stack traces were collected.\n    size_t size() const;\n\nprivate:\n    void printInternal(Printer& printer, Printer& csPrinter) const;\n\n    // Reset the process's stack frames and metadata.\n    void clear();\n\n    struct ThreadInfo {\n        CallStack callStack;\n        String8 threadName;\n    };\n\n    // tid -> ThreadInfo\n    KeyedVector<pid_t, ThreadInfo> mThreadMap;\n    // Time that update() was last called\n    struct tm mTimeUpdated;\n};\n\n}; // namespace android\n\n#endif // ANDROID_PROCESS_CALLSTACK_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/PropertyMap.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _UTILS_PROPERTY_MAP_H\n#define _UTILS_PROPERTY_MAP_H\n\n#include <utils/KeyedVector.h>\n#include <utils/String8.h>\n#include <utils/Errors.h>\n#include <utils/Tokenizer.h>\n\nnamespace android {\n\n/*\n * Provides a mechanism for passing around string-based property key / value pairs\n * and loading them from property files.\n *\n * The property files have the following simple structure:\n *\n * # Comment\n * key = value\n *\n * Keys and values are any sequence of printable ASCII characters.\n * The '=' separates the key from the value.\n * The key and value may not contain whitespace.\n *\n * The '\\' character is reserved for escape sequences and is not currently supported.\n * The '\"\" character is reserved for quoting and is not currently supported.\n * Files that contain the '\\' or '\"' character will fail to parse.\n *\n * The file must not contain duplicate keys.\n *\n * TODO Support escape sequences and quoted values when needed.\n */\nclass PropertyMap {\npublic:\n    /* Creates an empty property map. */\n    PropertyMap();\n    ~PropertyMap();\n\n    /* Clears the property map. */\n    void clear();\n\n    /* Adds a property.\n     * Replaces the property with the same key if it is already present.\n     */\n    void addProperty(const String8& key, const String8& value);\n\n    /* Returns true if the property map contains the specified key. */\n    bool hasProperty(const String8& key) const;\n\n    /* Gets the value of a property and parses it.\n     * Returns true and sets outValue if the key was found and its value was parsed successfully.\n     * Otherwise returns false and does not modify outValue.  (Also logs a warning.)\n     */\n    bool tryGetProperty(const String8& key, String8& outValue) const;\n    bool tryGetProperty(const String8& key, bool& outValue) const;\n    bool tryGetProperty(const String8& key, int32_t& outValue) const;\n    bool tryGetProperty(const String8& key, float& outValue) const;\n\n    /* Adds all values from the specified property map. */\n    void addAll(const PropertyMap* map);\n\n    /* Gets the underlying property map. */\n    inline const KeyedVector<String8, String8>& getProperties() const { return mProperties; }\n\n    /* Loads a property map from a file. */\n    static status_t load(const String8& filename, PropertyMap** outMap);\n\nprivate:\n    class Parser {\n        PropertyMap* mMap;\n        Tokenizer* mTokenizer;\n\n    public:\n        Parser(PropertyMap* map, Tokenizer* tokenizer);\n        ~Parser();\n        status_t parse();\n\n    private:\n        status_t parseType();\n        status_t parseKey();\n        status_t parseKeyProperty();\n        status_t parseModifier(const String8& token, int32_t* outMetaState);\n        status_t parseCharacterLiteral(char16_t* outCharacter);\n    };\n\n    KeyedVector<String8, String8> mProperties;\n};\n\n} // namespace android\n\n#endif // _UTILS_PROPERTY_MAP_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/RWLock.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_RWLOCK_H\n#define _LIBS_UTILS_RWLOCK_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#if !defined(_WIN32)\n# include <pthread.h>\n#endif\n\n#include <utils/Errors.h>\n#include <utils/ThreadDefs.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n// ---------------------------------------------------------------------------\n\n#if !defined(_WIN32)\n\n/*\n * Simple mutex class.  The implementation is system-dependent.\n *\n * The mutex must be unlocked by the thread that locked it.  They are not\n * recursive, i.e. the same thread can't lock it multiple times.\n */\nclass RWLock {\npublic:\n    enum {\n        PRIVATE = 0,\n        SHARED = 1\n    };\n\n                RWLock();\n                RWLock(const char* name);\n                RWLock(int type, const char* name = NULL);\n                ~RWLock();\n\n    status_t    readLock();\n    status_t    tryReadLock();\n    status_t    writeLock();\n    status_t    tryWriteLock();\n    void        unlock();\n\n    class AutoRLock {\n    public:\n        inline AutoRLock(RWLock& rwlock) : mLock(rwlock)  { mLock.readLock(); }\n        inline ~AutoRLock() { mLock.unlock(); }\n    private:\n        RWLock& mLock;\n    };\n\n    class AutoWLock {\n    public:\n        inline AutoWLock(RWLock& rwlock) : mLock(rwlock)  { mLock.writeLock(); }\n        inline ~AutoWLock() { mLock.unlock(); }\n    private:\n        RWLock& mLock;\n    };\n\nprivate:\n    // A RWLock cannot be copied\n                RWLock(const RWLock&);\n   RWLock&      operator = (const RWLock&);\n\n   pthread_rwlock_t mRWLock;\n};\n\ninline RWLock::RWLock() {\n    pthread_rwlock_init(&mRWLock, NULL);\n}\ninline RWLock::RWLock(__attribute__((unused)) const char* name) {\n    pthread_rwlock_init(&mRWLock, NULL);\n}\ninline RWLock::RWLock(int type, __attribute__((unused)) const char* name) {\n    if (type == SHARED) {\n        pthread_rwlockattr_t attr;\n        pthread_rwlockattr_init(&attr);\n        pthread_rwlockattr_setpshared(&attr, PTHREAD_PROCESS_SHARED);\n        pthread_rwlock_init(&mRWLock, &attr);\n        pthread_rwlockattr_destroy(&attr);\n    } else {\n        pthread_rwlock_init(&mRWLock, NULL);\n    }\n}\ninline RWLock::~RWLock() {\n    pthread_rwlock_destroy(&mRWLock);\n}\ninline status_t RWLock::readLock() {\n    return -pthread_rwlock_rdlock(&mRWLock);\n}\ninline status_t RWLock::tryReadLock() {\n    return -pthread_rwlock_tryrdlock(&mRWLock);\n}\ninline status_t RWLock::writeLock() {\n    return -pthread_rwlock_wrlock(&mRWLock);\n}\ninline status_t RWLock::tryWriteLock() {\n    return -pthread_rwlock_trywrlock(&mRWLock);\n}\ninline void RWLock::unlock() {\n    pthread_rwlock_unlock(&mRWLock);\n}\n\n#endif // !defined(_WIN32)\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n// ---------------------------------------------------------------------------\n\n#endif // _LIBS_UTILS_RWLOCK_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/RefBase.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_REF_BASE_H\n#define ANDROID_REF_BASE_H\n\n#include <cutils/atomic.h>\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include <utils/StrongPointer.h>\n#include <utils/TypeHelpers.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\nclass TextOutput;\nTextOutput& printWeakPointer(TextOutput& to, const void* val);\n\n// ---------------------------------------------------------------------------\n\n#define COMPARE_WEAK(_op_)                                      \\\ninline bool operator _op_ (const sp<T>& o) const {              \\\n    return m_ptr _op_ o.m_ptr;                                  \\\n}                                                               \\\ninline bool operator _op_ (const T* o) const {                  \\\n    return m_ptr _op_ o;                                        \\\n}                                                               \\\ntemplate<typename U>                                            \\\ninline bool operator _op_ (const sp<U>& o) const {              \\\n    return m_ptr _op_ o.m_ptr;                                  \\\n}                                                               \\\ntemplate<typename U>                                            \\\ninline bool operator _op_ (const U* o) const {                  \\\n    return m_ptr _op_ o;                                        \\\n}\n\n// ---------------------------------------------------------------------------\n\nclass ReferenceRenamer {\nprotected:\n    // destructor is purposedly not virtual so we avoid code overhead from\n    // subclasses; we have to make it protected to guarantee that it\n    // cannot be called from this base class (and to make strict compilers\n    // happy).\n    ~ReferenceRenamer() { }\npublic:\n    virtual void operator()(size_t i) const = 0;\n};\n\n// ---------------------------------------------------------------------------\n\nclass RefBase\n{\npublic:\n            void            incStrong(const void* id) const;\n            void            decStrong(const void* id) const;\n    \n            void            forceIncStrong(const void* id) const;\n\n            //! DEBUGGING ONLY: Get current strong ref count.\n            int32_t         getStrongCount() const;\n\n    class weakref_type\n    {\n    public:\n        RefBase*            refBase() const;\n        \n        void                incWeak(const void* id);\n        void                decWeak(const void* id);\n        \n        // acquires a strong reference if there is already one.\n        bool                attemptIncStrong(const void* id);\n        \n        // acquires a weak reference if there is already one.\n        // This is not always safe. see ProcessState.cpp and BpBinder.cpp\n        // for proper use.\n        bool                attemptIncWeak(const void* id);\n\n        //! DEBUGGING ONLY: Get current weak ref count.\n        int32_t             getWeakCount() const;\n\n        //! DEBUGGING ONLY: Print references held on object.\n        void                printRefs() const;\n\n        //! DEBUGGING ONLY: Enable tracking for this object.\n        // enable -- enable/disable tracking\n        // retain -- when tracking is enable, if true, then we save a stack trace\n        //           for each reference and dereference; when retain == false, we\n        //           match up references and dereferences and keep only the \n        //           outstanding ones.\n        \n        void                trackMe(bool enable, bool retain);\n    };\n    \n            weakref_type*   createWeak(const void* id) const;\n            \n            weakref_type*   getWeakRefs() const;\n\n            //! DEBUGGING ONLY: Print references held on object.\n    inline  void            printRefs() const { getWeakRefs()->printRefs(); }\n\n            //! DEBUGGING ONLY: Enable tracking of object.\n    inline  void            trackMe(bool enable, bool retain)\n    { \n        getWeakRefs()->trackMe(enable, retain); \n    }\n\n    typedef RefBase basetype;\n\nprotected:\n                            RefBase();\n    virtual                 ~RefBase();\n    \n    //! Flags for extendObjectLifetime()\n    enum {\n        OBJECT_LIFETIME_STRONG  = 0x0000,\n        OBJECT_LIFETIME_WEAK    = 0x0001,\n        OBJECT_LIFETIME_MASK    = 0x0001\n    };\n    \n            void            extendObjectLifetime(int32_t mode);\n            \n    //! Flags for onIncStrongAttempted()\n    enum {\n        FIRST_INC_STRONG = 0x0001\n    };\n    \n    virtual void            onFirstRef();\n    virtual void            onLastStrongRef(const void* id);\n    virtual bool            onIncStrongAttempted(uint32_t flags, const void* id);\n    virtual void            onLastWeakRef(const void* id);\n\nprivate:\n    friend class weakref_type;\n    class weakref_impl;\n    \n                            RefBase(const RefBase& o);\n            RefBase&        operator=(const RefBase& o);\n\nprivate:\n    friend class ReferenceMover;\n\n    static void renameRefs(size_t n, const ReferenceRenamer& renamer);\n\n    static void renameRefId(weakref_type* ref,\n            const void* old_id, const void* new_id);\n\n    static void renameRefId(RefBase* ref,\n            const void* old_id, const void* new_id);\n\n        weakref_impl* const mRefs;\n};\n\n// ---------------------------------------------------------------------------\n\ntemplate <class T>\nclass LightRefBase\n{\npublic:\n    inline LightRefBase() : mCount(0) { }\n    inline void incStrong(__attribute__((unused)) const void* id) const {\n        android_atomic_inc(&mCount);\n    }\n    inline void decStrong(__attribute__((unused)) const void* id) const {\n        if (android_atomic_dec(&mCount) == 1) {\n            delete static_cast<const T*>(this);\n        }\n    }\n    //! DEBUGGING ONLY: Get current strong ref count.\n    inline int32_t getStrongCount() const {\n        return mCount;\n    }\n\n    typedef LightRefBase<T> basetype;\n\nprotected:\n    inline ~LightRefBase() { }\n\nprivate:\n    friend class ReferenceMover;\n    inline static void renameRefs(size_t n, const ReferenceRenamer& renamer) { }\n    inline static void renameRefId(T* ref,\n            const void* old_id, const void* new_id) { }\n\nprivate:\n    mutable volatile int32_t mCount;\n};\n\n// This is a wrapper around LightRefBase that simply enforces a virtual\n// destructor to eliminate the template requirement of LightRefBase\nclass VirtualLightRefBase : public LightRefBase<VirtualLightRefBase> {\npublic:\n    virtual ~VirtualLightRefBase() {}\n};\n\n// ---------------------------------------------------------------------------\n\ntemplate <typename T>\nclass wp\n{\npublic:\n    typedef typename RefBase::weakref_type weakref_type;\n    \n    inline wp() : m_ptr(0) { }\n\n    wp(T* other);\n    wp(const wp<T>& other);\n    wp(const sp<T>& other);\n    template<typename U> wp(U* other);\n    template<typename U> wp(const sp<U>& other);\n    template<typename U> wp(const wp<U>& other);\n\n    ~wp();\n    \n    // Assignment\n\n    wp& operator = (T* other);\n    wp& operator = (const wp<T>& other);\n    wp& operator = (const sp<T>& other);\n    \n    template<typename U> wp& operator = (U* other);\n    template<typename U> wp& operator = (const wp<U>& other);\n    template<typename U> wp& operator = (const sp<U>& other);\n    \n    void set_object_and_refs(T* other, weakref_type* refs);\n\n    // promotion to sp\n    \n    sp<T> promote() const;\n\n    // Reset\n    \n    void clear();\n\n    // Accessors\n    \n    inline  weakref_type* get_refs() const { return m_refs; }\n    \n    inline  T* unsafe_get() const { return m_ptr; }\n\n    // Operators\n\n    COMPARE_WEAK(==)\n    COMPARE_WEAK(!=)\n    COMPARE_WEAK(>)\n    COMPARE_WEAK(<)\n    COMPARE_WEAK(<=)\n    COMPARE_WEAK(>=)\n\n    inline bool operator == (const wp<T>& o) const {\n        return (m_ptr == o.m_ptr) && (m_refs == o.m_refs);\n    }\n    template<typename U>\n    inline bool operator == (const wp<U>& o) const {\n        return m_ptr == o.m_ptr;\n    }\n\n    inline bool operator > (const wp<T>& o) const {\n        return (m_ptr == o.m_ptr) ? (m_refs > o.m_refs) : (m_ptr > o.m_ptr);\n    }\n    template<typename U>\n    inline bool operator > (const wp<U>& o) const {\n        return (m_ptr == o.m_ptr) ? (m_refs > o.m_refs) : (m_ptr > o.m_ptr);\n    }\n\n    inline bool operator < (const wp<T>& o) const {\n        return (m_ptr == o.m_ptr) ? (m_refs < o.m_refs) : (m_ptr < o.m_ptr);\n    }\n    template<typename U>\n    inline bool operator < (const wp<U>& o) const {\n        return (m_ptr == o.m_ptr) ? (m_refs < o.m_refs) : (m_ptr < o.m_ptr);\n    }\n                         inline bool operator != (const wp<T>& o) const { return m_refs != o.m_refs; }\n    template<typename U> inline bool operator != (const wp<U>& o) const { return !operator == (o); }\n                         inline bool operator <= (const wp<T>& o) const { return !operator > (o); }\n    template<typename U> inline bool operator <= (const wp<U>& o) const { return !operator > (o); }\n                         inline bool operator >= (const wp<T>& o) const { return !operator < (o); }\n    template<typename U> inline bool operator >= (const wp<U>& o) const { return !operator < (o); }\n\nprivate:\n    template<typename Y> friend class sp;\n    template<typename Y> friend class wp;\n\n    T*              m_ptr;\n    weakref_type*   m_refs;\n};\n\ntemplate <typename T>\nTextOutput& operator<<(TextOutput& to, const wp<T>& val);\n\n#undef COMPARE_WEAK\n\n// ---------------------------------------------------------------------------\n// No user serviceable parts below here.\n\ntemplate<typename T>\nwp<T>::wp(T* other)\n    : m_ptr(other)\n{\n    if (other) m_refs = other->createWeak(this);\n}\n\ntemplate<typename T>\nwp<T>::wp(const wp<T>& other)\n    : m_ptr(other.m_ptr), m_refs(other.m_refs)\n{\n    if (m_ptr) m_refs->incWeak(this);\n}\n\ntemplate<typename T>\nwp<T>::wp(const sp<T>& other)\n    : m_ptr(other.m_ptr)\n{\n    if (m_ptr) {\n        m_refs = m_ptr->createWeak(this);\n    }\n}\n\ntemplate<typename T> template<typename U>\nwp<T>::wp(U* other)\n    : m_ptr(other)\n{\n    if (other) m_refs = other->createWeak(this);\n}\n\ntemplate<typename T> template<typename U>\nwp<T>::wp(const wp<U>& other)\n    : m_ptr(other.m_ptr)\n{\n    if (m_ptr) {\n        m_refs = other.m_refs;\n        m_refs->incWeak(this);\n    }\n}\n\ntemplate<typename T> template<typename U>\nwp<T>::wp(const sp<U>& other)\n    : m_ptr(other.m_ptr)\n{\n    if (m_ptr) {\n        m_refs = m_ptr->createWeak(this);\n    }\n}\n\ntemplate<typename T>\nwp<T>::~wp()\n{\n    if (m_ptr) m_refs->decWeak(this);\n}\n\ntemplate<typename T>\nwp<T>& wp<T>::operator = (T* other)\n{\n    weakref_type* newRefs =\n        other ? other->createWeak(this) : 0;\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = other;\n    m_refs = newRefs;\n    return *this;\n}\n\ntemplate<typename T>\nwp<T>& wp<T>::operator = (const wp<T>& other)\n{\n    weakref_type* otherRefs(other.m_refs);\n    T* otherPtr(other.m_ptr);\n    if (otherPtr) otherRefs->incWeak(this);\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = otherPtr;\n    m_refs = otherRefs;\n    return *this;\n}\n\ntemplate<typename T>\nwp<T>& wp<T>::operator = (const sp<T>& other)\n{\n    weakref_type* newRefs =\n        other != NULL ? other->createWeak(this) : 0;\n    T* otherPtr(other.m_ptr);\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = otherPtr;\n    m_refs = newRefs;\n    return *this;\n}\n\ntemplate<typename T> template<typename U>\nwp<T>& wp<T>::operator = (U* other)\n{\n    weakref_type* newRefs =\n        other ? other->createWeak(this) : 0;\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = other;\n    m_refs = newRefs;\n    return *this;\n}\n\ntemplate<typename T> template<typename U>\nwp<T>& wp<T>::operator = (const wp<U>& other)\n{\n    weakref_type* otherRefs(other.m_refs);\n    U* otherPtr(other.m_ptr);\n    if (otherPtr) otherRefs->incWeak(this);\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = otherPtr;\n    m_refs = otherRefs;\n    return *this;\n}\n\ntemplate<typename T> template<typename U>\nwp<T>& wp<T>::operator = (const sp<U>& other)\n{\n    weakref_type* newRefs =\n        other != NULL ? other->createWeak(this) : 0;\n    U* otherPtr(other.m_ptr);\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = otherPtr;\n    m_refs = newRefs;\n    return *this;\n}\n\ntemplate<typename T>\nvoid wp<T>::set_object_and_refs(T* other, weakref_type* refs)\n{\n    if (other) refs->incWeak(this);\n    if (m_ptr) m_refs->decWeak(this);\n    m_ptr = other;\n    m_refs = refs;\n}\n\ntemplate<typename T>\nsp<T> wp<T>::promote() const\n{\n    sp<T> result;\n    if (m_ptr && m_refs->attemptIncStrong(&result)) {\n        result.set_pointer(m_ptr);\n    }\n    return result;\n}\n\ntemplate<typename T>\nvoid wp<T>::clear()\n{\n    if (m_ptr) {\n        m_refs->decWeak(this);\n        m_ptr = 0;\n    }\n}\n\ntemplate <typename T>\ninline TextOutput& operator<<(TextOutput& to, const wp<T>& val)\n{\n    return printWeakPointer(to, val.unsafe_get());\n}\n\n// ---------------------------------------------------------------------------\n\n// this class just serves as a namespace so TYPE::moveReferences can stay\n// private.\nclass ReferenceMover {\npublic:\n    // it would be nice if we could make sure no extra code is generated\n    // for sp<TYPE> or wp<TYPE> when TYPE is a descendant of RefBase:\n    // Using a sp<RefBase> override doesn't work; it's a bit like we wanted\n    // a template<typename TYPE inherits RefBase> template...\n\n    template<typename TYPE> static inline\n    void move_references(sp<TYPE>* d, sp<TYPE> const* s, size_t n) {\n\n        class Renamer : public ReferenceRenamer {\n            sp<TYPE>* d;\n            sp<TYPE> const* s;\n            virtual void operator()(size_t i) const {\n                // The id are known to be the sp<>'s this pointer\n                TYPE::renameRefId(d[i].get(), &s[i], &d[i]);\n            }\n        public:\n            Renamer(sp<TYPE>* d, sp<TYPE> const* s) : d(d), s(s) { }\n            virtual ~Renamer() { }\n        };\n\n        memmove(d, s, n*sizeof(sp<TYPE>));\n        TYPE::renameRefs(n, Renamer(d, s));\n    }\n\n\n    template<typename TYPE> static inline\n    void move_references(wp<TYPE>* d, wp<TYPE> const* s, size_t n) {\n\n        class Renamer : public ReferenceRenamer {\n            wp<TYPE>* d;\n            wp<TYPE> const* s;\n            virtual void operator()(size_t i) const {\n                // The id are known to be the wp<>'s this pointer\n                TYPE::renameRefId(d[i].get_refs(), &s[i], &d[i]);\n            }\n        public:\n            Renamer(wp<TYPE>* d, wp<TYPE> const* s) : d(d), s(s) { }\n            virtual ~Renamer() { }\n        };\n\n        memmove(d, s, n*sizeof(wp<TYPE>));\n        TYPE::renameRefs(n, Renamer(d, s));\n    }\n};\n\n// specialization for moving sp<> and wp<> types.\n// these are used by the [Sorted|Keyed]Vector<> implementations\n// sp<> and wp<> need to be handled specially, because they do not\n// have trivial copy operation in the general case (see RefBase.cpp\n// when DEBUG ops are enabled), but can be implemented very\n// efficiently in most cases.\n\ntemplate<typename TYPE> inline\nvoid move_forward_type(sp<TYPE>* d, sp<TYPE> const* s, size_t n) {\n    ReferenceMover::move_references(d, s, n);\n}\n\ntemplate<typename TYPE> inline\nvoid move_backward_type(sp<TYPE>* d, sp<TYPE> const* s, size_t n) {\n    ReferenceMover::move_references(d, s, n);\n}\n\ntemplate<typename TYPE> inline\nvoid move_forward_type(wp<TYPE>* d, wp<TYPE> const* s, size_t n) {\n    ReferenceMover::move_references(d, s, n);\n}\n\ntemplate<typename TYPE> inline\nvoid move_backward_type(wp<TYPE>* d, wp<TYPE> const* s, size_t n) {\n    ReferenceMover::move_references(d, s, n);\n}\n\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_REF_BASE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/SharedBuffer.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_SHARED_BUFFER_H\n#define ANDROID_SHARED_BUFFER_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\nclass SharedBuffer\n{\npublic:\n\n    /* flags to use with release() */\n    enum {\n        eKeepStorage = 0x00000001\n    };\n\n    /*! allocate a buffer of size 'size' and acquire() it.\n     *  call release() to free it.\n     */\n    static          SharedBuffer*           alloc(size_t size);\n    \n    /*! free the memory associated with the SharedBuffer.\n     * Fails if there are any users associated with this SharedBuffer.\n     * In other words, the buffer must have been release by all its\n     * users.\n     */\n    static          ssize_t                 dealloc(const SharedBuffer* released);\n\n    //! access the data for read\n    inline          const void*             data() const;\n    \n    //! access the data for read/write\n    inline          void*                   data();\n\n    //! get size of the buffer\n    inline          size_t                  size() const;\n \n    //! get back a SharedBuffer object from its data\n    static  inline  SharedBuffer*           bufferFromData(void* data);\n    \n    //! get back a SharedBuffer object from its data\n    static  inline  const SharedBuffer*     bufferFromData(const void* data);\n\n    //! get the size of a SharedBuffer object from its data\n    static  inline  size_t                  sizeFromData(const void* data);\n    \n    //! edit the buffer (get a writtable, or non-const, version of it)\n                    SharedBuffer*           edit() const;\n\n    //! edit the buffer, resizing if needed\n                    SharedBuffer*           editResize(size_t size) const;\n\n    //! like edit() but fails if a copy is required\n                    SharedBuffer*           attemptEdit() const;\n    \n    //! resize and edit the buffer, loose it's content.\n                    SharedBuffer*           reset(size_t size) const;\n\n    //! acquire/release a reference on this buffer\n                    void                    acquire() const;\n                    \n    /*! release a reference on this buffer, with the option of not\n     * freeing the memory associated with it if it was the last reference\n     * returns the previous reference count\n     */     \n                    int32_t                 release(uint32_t flags = 0) const;\n    \n    //! returns wether or not we're the only owner\n    inline          bool                    onlyOwner() const;\n    \n\nprivate:\n        inline SharedBuffer() { }\n        inline ~SharedBuffer() { }\n        SharedBuffer(const SharedBuffer&);\n        SharedBuffer& operator = (const SharedBuffer&);\n \n        // 16 bytes. must be sized to preserve correct alignment.\n        mutable int32_t        mRefs;\n                size_t         mSize;\n                uint32_t       mReserved[2];\n};\n\n// ---------------------------------------------------------------------------\n\nconst void* SharedBuffer::data() const {\n    return this + 1;\n}\n\nvoid* SharedBuffer::data() {\n    return this + 1;\n}\n\nsize_t SharedBuffer::size() const {\n    return mSize;\n}\n\nSharedBuffer* SharedBuffer::bufferFromData(void* data) {\n    return data ? static_cast<SharedBuffer *>(data)-1 : 0;\n}\n    \nconst SharedBuffer* SharedBuffer::bufferFromData(const void* data) {\n    return data ? static_cast<const SharedBuffer *>(data)-1 : 0;\n}\n\nsize_t SharedBuffer::sizeFromData(const void* data) {\n    return data ? bufferFromData(data)->mSize : 0;\n}\n\nbool SharedBuffer::onlyOwner() const {\n    return (mRefs == 1);\n}\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_VECTOR_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Singleton.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UTILS_SINGLETON_H\n#define ANDROID_UTILS_SINGLETON_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <utils/threads.h>\n#include <cutils/compiler.h>\n\nnamespace android {\n// ---------------------------------------------------------------------------\n\ntemplate <typename TYPE>\nclass ANDROID_API Singleton\n{\npublic:\n    static TYPE& getInstance() {\n        Mutex::Autolock _l(sLock);\n        TYPE* instance = sInstance;\n        if (instance == 0) {\n            instance = new TYPE();\n            sInstance = instance;\n        }\n        return *instance;\n    }\n\n    static bool hasInstance() {\n        Mutex::Autolock _l(sLock);\n        return sInstance != 0;\n    }\n    \nprotected:\n    ~Singleton() { };\n    Singleton() { };\n\nprivate:\n    Singleton(const Singleton&);\n    Singleton& operator = (const Singleton&);\n    static Mutex sLock;\n    static TYPE* sInstance;\n};\n\n/*\n * use ANDROID_SINGLETON_STATIC_INSTANCE(TYPE) in your implementation file\n * (eg: <TYPE>.cpp) to create the static instance of Singleton<>'s attributes,\n * and avoid to have a copy of them in each compilation units Singleton<TYPE>\n * is used.\n * NOTE: we use a version of Mutex ctor that takes a parameter, because\n * for some unknown reason using the default ctor doesn't emit the variable!\n */\n\n#define ANDROID_SINGLETON_STATIC_INSTANCE(TYPE)                 \\\n    template<> ::android::Mutex  \\\n        (::android::Singleton< TYPE >::sLock)(::android::Mutex::PRIVATE);  \\\n    template<> TYPE* ::android::Singleton< TYPE >::sInstance(0);  \\\n    template class ::android::Singleton< TYPE >;\n\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n\n#endif // ANDROID_UTILS_SINGLETON_H\n\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/SortedVector.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_SORTED_VECTOR_H\n#define ANDROID_SORTED_VECTOR_H\n\n#include <assert.h>\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <cutils/log.h>\n\n#include <utils/Vector.h>\n#include <utils/VectorImpl.h>\n#include <utils/TypeHelpers.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\ntemplate <class TYPE>\nclass SortedVector : private SortedVectorImpl\n{\n    friend class Vector<TYPE>;\n\npublic:\n            typedef TYPE    value_type;\n    \n    /*! \n     * Constructors and destructors\n     */\n    \n                            SortedVector();\n                            SortedVector(const SortedVector<TYPE>& rhs);\n    virtual                 ~SortedVector();\n\n    /*! copy operator */\n    const SortedVector<TYPE>&   operator = (const SortedVector<TYPE>& rhs) const;    \n    SortedVector<TYPE>&         operator = (const SortedVector<TYPE>& rhs);    \n\n    /*\n     * empty the vector\n     */\n\n    inline  void            clear()             { VectorImpl::clear(); }\n\n    /*! \n     * vector stats\n     */\n\n    //! returns number of items in the vector\n    inline  size_t          size() const                { return VectorImpl::size(); }\n    //! returns whether or not the vector is empty\n    inline  bool            isEmpty() const             { return VectorImpl::isEmpty(); }\n    //! returns how many items can be stored without reallocating the backing store\n    inline  size_t          capacity() const            { return VectorImpl::capacity(); }\n    //! sets the capacity. capacity can never be reduced less than size()\n    inline  ssize_t         setCapacity(size_t size)    { return VectorImpl::setCapacity(size); }\n\n    /*! \n     * C-style array access\n     */\n     \n    //! read-only C-style access \n    inline  const TYPE*     array() const;\n\n    //! read-write C-style access. BE VERY CAREFUL when modifying the array\n    //! you must keep it sorted! You usually don't use this function.\n            TYPE*           editArray();\n\n            //! finds the index of an item\n            ssize_t         indexOf(const TYPE& item) const;\n            \n            //! finds where this item should be inserted\n            size_t          orderOf(const TYPE& item) const;\n            \n    \n    /*! \n     * accessors\n     */\n\n    //! read-only access to an item at a given index\n    inline  const TYPE&     operator [] (size_t index) const;\n    //! alternate name for operator []\n    inline  const TYPE&     itemAt(size_t index) const;\n    //! stack-usage of the vector. returns the top of the stack (last element)\n            const TYPE&     top() const;\n\n    /*!\n     * modifying the array\n     */\n\n            //! add an item in the right place (and replace the one that is there)\n            ssize_t         add(const TYPE& item);\n            \n            //! editItemAt() MUST NOT change the order of this item\n            TYPE&           editItemAt(size_t index) {\n                return *( static_cast<TYPE *>(VectorImpl::editItemLocation(index)) );\n            }\n\n            //! merges a vector into this one\n            ssize_t         merge(const Vector<TYPE>& vector);\n            ssize_t         merge(const SortedVector<TYPE>& vector);\n            \n            //! removes an item\n            ssize_t         remove(const TYPE&);\n\n    //! remove several items\n    inline  ssize_t         removeItemsAt(size_t index, size_t count = 1);\n    //! remove one item\n    inline  ssize_t         removeAt(size_t index)  { return removeItemsAt(index); }\n            \nprotected:\n    virtual void    do_construct(void* storage, size_t num) const;\n    virtual void    do_destroy(void* storage, size_t num) const;\n    virtual void    do_copy(void* dest, const void* from, size_t num) const;\n    virtual void    do_splat(void* dest, const void* item, size_t num) const;\n    virtual void    do_move_forward(void* dest, const void* from, size_t num) const;\n    virtual void    do_move_backward(void* dest, const void* from, size_t num) const;\n    virtual int     do_compare(const void* lhs, const void* rhs) const;\n};\n\n// SortedVector<T> can be trivially moved using memcpy() because moving does not\n// require any change to the underlying SharedBuffer contents or reference count.\ntemplate<typename T> struct trait_trivial_move<SortedVector<T> > { enum { value = true }; };\n\n// ---------------------------------------------------------------------------\n// No user serviceable parts from here...\n// ---------------------------------------------------------------------------\n\ntemplate<class TYPE> inline\nSortedVector<TYPE>::SortedVector()\n    : SortedVectorImpl(sizeof(TYPE),\n                ((traits<TYPE>::has_trivial_ctor   ? HAS_TRIVIAL_CTOR   : 0)\n                |(traits<TYPE>::has_trivial_dtor   ? HAS_TRIVIAL_DTOR   : 0)\n                |(traits<TYPE>::has_trivial_copy   ? HAS_TRIVIAL_COPY   : 0))\n                )\n{\n}\n\ntemplate<class TYPE> inline\nSortedVector<TYPE>::SortedVector(const SortedVector<TYPE>& rhs)\n    : SortedVectorImpl(rhs) {\n}\n\ntemplate<class TYPE> inline\nSortedVector<TYPE>::~SortedVector() {\n    finish_vector();\n}\n\ntemplate<class TYPE> inline\nSortedVector<TYPE>& SortedVector<TYPE>::operator = (const SortedVector<TYPE>& rhs) {\n    SortedVectorImpl::operator = (rhs);\n    return *this; \n}\n\ntemplate<class TYPE> inline\nconst SortedVector<TYPE>& SortedVector<TYPE>::operator = (const SortedVector<TYPE>& rhs) const {\n    SortedVectorImpl::operator = (rhs);\n    return *this; \n}\n\ntemplate<class TYPE> inline\nconst TYPE* SortedVector<TYPE>::array() const {\n    return static_cast<const TYPE *>(arrayImpl());\n}\n\ntemplate<class TYPE> inline\nTYPE* SortedVector<TYPE>::editArray() {\n    return static_cast<TYPE *>(editArrayImpl());\n}\n\n\ntemplate<class TYPE> inline\nconst TYPE& SortedVector<TYPE>::operator[](size_t index) const {\n    LOG_FATAL_IF(index>=size(),\n            \"%s: index=%u out of range (%u)\", __PRETTY_FUNCTION__,\n            int(index), int(size()));\n    return *(array() + index);\n}\n\ntemplate<class TYPE> inline\nconst TYPE& SortedVector<TYPE>::itemAt(size_t index) const {\n    return operator[](index);\n}\n\ntemplate<class TYPE> inline\nconst TYPE& SortedVector<TYPE>::top() const {\n    return *(array() + size() - 1);\n}\n\ntemplate<class TYPE> inline\nssize_t SortedVector<TYPE>::add(const TYPE& item) {\n    return SortedVectorImpl::add(&item);\n}\n\ntemplate<class TYPE> inline\nssize_t SortedVector<TYPE>::indexOf(const TYPE& item) const {\n    return SortedVectorImpl::indexOf(&item);\n}\n\ntemplate<class TYPE> inline\nsize_t SortedVector<TYPE>::orderOf(const TYPE& item) const {\n    return SortedVectorImpl::orderOf(&item);\n}\n\ntemplate<class TYPE> inline\nssize_t SortedVector<TYPE>::merge(const Vector<TYPE>& vector) {\n    return SortedVectorImpl::merge(reinterpret_cast<const VectorImpl&>(vector));\n}\n\ntemplate<class TYPE> inline\nssize_t SortedVector<TYPE>::merge(const SortedVector<TYPE>& vector) {\n    return SortedVectorImpl::merge(reinterpret_cast<const SortedVectorImpl&>(vector));\n}\n\ntemplate<class TYPE> inline\nssize_t SortedVector<TYPE>::remove(const TYPE& item) {\n    return SortedVectorImpl::remove(&item);\n}\n\ntemplate<class TYPE> inline\nssize_t SortedVector<TYPE>::removeItemsAt(size_t index, size_t count) {\n    return VectorImpl::removeItemsAt(index, count);\n}\n\n// ---------------------------------------------------------------------------\n\ntemplate<class TYPE>\nvoid SortedVector<TYPE>::do_construct(void* storage, size_t num) const {\n    construct_type( reinterpret_cast<TYPE*>(storage), num );\n}\n\ntemplate<class TYPE>\nvoid SortedVector<TYPE>::do_destroy(void* storage, size_t num) const {\n    destroy_type( reinterpret_cast<TYPE*>(storage), num );\n}\n\ntemplate<class TYPE>\nvoid SortedVector<TYPE>::do_copy(void* dest, const void* from, size_t num) const {\n    copy_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(from), num );\n}\n\ntemplate<class TYPE>\nvoid SortedVector<TYPE>::do_splat(void* dest, const void* item, size_t num) const {\n    splat_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(item), num );\n}\n\ntemplate<class TYPE>\nvoid SortedVector<TYPE>::do_move_forward(void* dest, const void* from, size_t num) const {\n    move_forward_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(from), num );\n}\n\ntemplate<class TYPE>\nvoid SortedVector<TYPE>::do_move_backward(void* dest, const void* from, size_t num) const {\n    move_backward_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(from), num );\n}\n\ntemplate<class TYPE>\nint SortedVector<TYPE>::do_compare(const void* lhs, const void* rhs) const {\n    return compare_type( *reinterpret_cast<const TYPE*>(lhs), *reinterpret_cast<const TYPE*>(rhs) );\n}\n\n}; // namespace android\n\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_SORTED_VECTOR_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/StopWatch.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_STOPWATCH_H\n#define ANDROID_STOPWATCH_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <utils/Timers.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\nclass StopWatch\n{\npublic:\n        StopWatch(  const char *name,\n                    int clock = SYSTEM_TIME_MONOTONIC,\n                    uint32_t flags = 0);\n        ~StopWatch();\n        \n        const char* name() const;\n        nsecs_t     lap();\n        nsecs_t     elapsedTime() const;\n\n        void        reset();\n        \nprivate:\n    const char*     mName;\n    int             mClock;\n    uint32_t        mFlags;\n    \n    struct lap_t {\n        nsecs_t     soFar;\n        nsecs_t     thisLap;\n    };\n    \n    nsecs_t         mStartTime;\n    lap_t           mLaps[8];\n    int             mNumLaps;\n};\n\n\n}; // namespace android\n\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_STOPWATCH_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/String16.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_STRING16_H\n#define ANDROID_STRING16_H\n\n#include <utils/Errors.h>\n#include <utils/SharedBuffer.h>\n#include <utils/Unicode.h>\n#include <utils/TypeHelpers.h>\n\n// ---------------------------------------------------------------------------\n\nextern \"C\" {\n\n}\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\n// ---------------------------------------------------------------------------\n\nclass String8;\nclass TextOutput;\n\n//! This is a string holding UTF-16 characters.\nclass String16\n{\npublic:\n    /* use String16(StaticLinkage) if you're statically linking against\n     * libutils and declaring an empty static String16, e.g.:\n     *\n     *   static String16 sAStaticEmptyString(String16::kEmptyString);\n     *   static String16 sAnotherStaticEmptyString(sAStaticEmptyString);\n     */\n    enum StaticLinkage { kEmptyString };\n\n                                String16();\n    explicit                    String16(StaticLinkage);\n                                String16(const String16& o);\n                                String16(const String16& o,\n                                         size_t len,\n                                         size_t begin=0);\n    explicit                    String16(const char16_t* o);\n    explicit                    String16(const char16_t* o, size_t len);\n    explicit                    String16(const String8& o);\n    explicit                    String16(const char* o);\n    explicit                    String16(const char* o, size_t len);\n\n                                ~String16();\n    \n    inline  const char16_t*     string() const;\n    inline  size_t              size() const;\n    \n    inline  const SharedBuffer* sharedBuffer() const;\n    \n            void                setTo(const String16& other);\n            status_t            setTo(const char16_t* other);\n            status_t            setTo(const char16_t* other, size_t len);\n            status_t            setTo(const String16& other,\n                                      size_t len,\n                                      size_t begin=0);\n    \n            status_t            append(const String16& other);\n            status_t            append(const char16_t* other, size_t len);\n            \n    inline  String16&           operator=(const String16& other);\n    \n    inline  String16&           operator+=(const String16& other);\n    inline  String16            operator+(const String16& other) const;\n\n            status_t            insert(size_t pos, const char16_t* chrs);\n            status_t            insert(size_t pos,\n                                       const char16_t* chrs, size_t len);\n\n            ssize_t             findFirst(char16_t c) const;\n            ssize_t             findLast(char16_t c) const;\n\n            bool                startsWith(const String16& prefix) const;\n            bool                startsWith(const char16_t* prefix) const;\n            \n            status_t            makeLower();\n\n            status_t            replaceAll(char16_t replaceThis,\n                                           char16_t withThis);\n\n            status_t            remove(size_t len, size_t begin=0);\n\n    inline  int                 compare(const String16& other) const;\n\n    inline  bool                operator<(const String16& other) const;\n    inline  bool                operator<=(const String16& other) const;\n    inline  bool                operator==(const String16& other) const;\n    inline  bool                operator!=(const String16& other) const;\n    inline  bool                operator>=(const String16& other) const;\n    inline  bool                operator>(const String16& other) const;\n    \n    inline  bool                operator<(const char16_t* other) const;\n    inline  bool                operator<=(const char16_t* other) const;\n    inline  bool                operator==(const char16_t* other) const;\n    inline  bool                operator!=(const char16_t* other) const;\n    inline  bool                operator>=(const char16_t* other) const;\n    inline  bool                operator>(const char16_t* other) const;\n    \n    inline                      operator const char16_t*() const;\n    \nprivate:\n            const char16_t*     mString;\n};\n\n// String16 can be trivially moved using memcpy() because moving does not\n// require any change to the underlying SharedBuffer contents or reference count.\nANDROID_TRIVIAL_MOVE_TRAIT(String16)\n\n// ---------------------------------------------------------------------------\n// No user servicable parts below.\n\ninline int compare_type(const String16& lhs, const String16& rhs)\n{\n    return lhs.compare(rhs);\n}\n\ninline int strictly_order_type(const String16& lhs, const String16& rhs)\n{\n    return compare_type(lhs, rhs) < 0;\n}\n\ninline const char16_t* String16::string() const\n{\n    return mString;\n}\n\ninline size_t String16::size() const\n{\n    return SharedBuffer::sizeFromData(mString)/sizeof(char16_t)-1;\n}\n\ninline const SharedBuffer* String16::sharedBuffer() const\n{\n    return SharedBuffer::bufferFromData(mString);\n}\n\ninline String16& String16::operator=(const String16& other)\n{\n    setTo(other);\n    return *this;\n}\n\ninline String16& String16::operator+=(const String16& other)\n{\n    append(other);\n    return *this;\n}\n\ninline String16 String16::operator+(const String16& other) const\n{\n    String16 tmp(*this);\n    tmp += other;\n    return tmp;\n}\n\ninline int String16::compare(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size());\n}\n\ninline bool String16::operator<(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size()) < 0;\n}\n\ninline bool String16::operator<=(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size()) <= 0;\n}\n\ninline bool String16::operator==(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size()) == 0;\n}\n\ninline bool String16::operator!=(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size()) != 0;\n}\n\ninline bool String16::operator>=(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size()) >= 0;\n}\n\ninline bool String16::operator>(const String16& other) const\n{\n    return strzcmp16(mString, size(), other.mString, other.size()) > 0;\n}\n\ninline bool String16::operator<(const char16_t* other) const\n{\n    return strcmp16(mString, other) < 0;\n}\n\ninline bool String16::operator<=(const char16_t* other) const\n{\n    return strcmp16(mString, other) <= 0;\n}\n\ninline bool String16::operator==(const char16_t* other) const\n{\n    return strcmp16(mString, other) == 0;\n}\n\ninline bool String16::operator!=(const char16_t* other) const\n{\n    return strcmp16(mString, other) != 0;\n}\n\ninline bool String16::operator>=(const char16_t* other) const\n{\n    return strcmp16(mString, other) >= 0;\n}\n\ninline bool String16::operator>(const char16_t* other) const\n{\n    return strcmp16(mString, other) > 0;\n}\n\ninline String16::operator const char16_t*() const\n{\n    return mString;\n}\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_STRING16_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/String8.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_STRING8_H\n#define ANDROID_STRING8_H\n\n#include <utils/Errors.h>\n#include <utils/SharedBuffer.h>\n#include <utils/Unicode.h>\n#include <utils/TypeHelpers.h>\n\n#include <string.h> // for strcmp\n#include <stdarg.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\nclass String16;\nclass TextOutput;\n\n//! This is a string holding UTF-8 characters. Does not allow the value more\n// than 0x10FFFF, which is not valid unicode codepoint.\nclass String8\n{\npublic:\n    /* use String8(StaticLinkage) if you're statically linking against\n     * libutils and declaring an empty static String8, e.g.:\n     *\n     *   static String8 sAStaticEmptyString(String8::kEmptyString);\n     *   static String8 sAnotherStaticEmptyString(sAStaticEmptyString);\n     */\n    enum StaticLinkage { kEmptyString };\n\n                                String8();\n    explicit                    String8(StaticLinkage);\n                                String8(const String8& o);\n    explicit                    String8(const char* o);\n    explicit                    String8(const char* o, size_t numChars);\n    \n    explicit                    String8(const String16& o);\n    explicit                    String8(const char16_t* o);\n    explicit                    String8(const char16_t* o, size_t numChars);\n    explicit                    String8(const char32_t* o);\n    explicit                    String8(const char32_t* o, size_t numChars);\n                                ~String8();\n\n    static inline const String8 empty();\n\n    static String8              format(const char* fmt, ...) __attribute__((format (printf, 1, 2)));\n    static String8              formatV(const char* fmt, va_list args);\n\n    inline  const char*         string() const;\n    inline  size_t              size() const;\n    inline  size_t              length() const;\n    inline  size_t              bytes() const;\n    inline  bool                isEmpty() const;\n    \n    inline  const SharedBuffer* sharedBuffer() const;\n    \n            void                clear();\n\n            void                setTo(const String8& other);\n            status_t            setTo(const char* other);\n            status_t            setTo(const char* other, size_t numChars);\n            status_t            setTo(const char16_t* other, size_t numChars);\n            status_t            setTo(const char32_t* other,\n                                      size_t length);\n\n            status_t            append(const String8& other);\n            status_t            append(const char* other);\n            status_t            append(const char* other, size_t numChars);\n\n            status_t            appendFormat(const char* fmt, ...)\n                    __attribute__((format (printf, 2, 3)));\n            status_t            appendFormatV(const char* fmt, va_list args);\n\n            // Note that this function takes O(N) time to calculate the value.\n            // No cache value is stored.\n            size_t              getUtf32Length() const;\n            int32_t             getUtf32At(size_t index,\n                                           size_t *next_index) const;\n            void                getUtf32(char32_t* dst) const;\n\n    inline  String8&            operator=(const String8& other);\n    inline  String8&            operator=(const char* other);\n    \n    inline  String8&            operator+=(const String8& other);\n    inline  String8             operator+(const String8& other) const;\n    \n    inline  String8&            operator+=(const char* other);\n    inline  String8             operator+(const char* other) const;\n\n    inline  int                 compare(const String8& other) const;\n\n    inline  bool                operator<(const String8& other) const;\n    inline  bool                operator<=(const String8& other) const;\n    inline  bool                operator==(const String8& other) const;\n    inline  bool                operator!=(const String8& other) const;\n    inline  bool                operator>=(const String8& other) const;\n    inline  bool                operator>(const String8& other) const;\n    \n    inline  bool                operator<(const char* other) const;\n    inline  bool                operator<=(const char* other) const;\n    inline  bool                operator==(const char* other) const;\n    inline  bool                operator!=(const char* other) const;\n    inline  bool                operator>=(const char* other) const;\n    inline  bool                operator>(const char* other) const;\n    \n    inline                      operator const char*() const;\n    \n            char*               lockBuffer(size_t size);\n            void                unlockBuffer();\n            status_t            unlockBuffer(size_t size);\n            \n            // return the index of the first byte of other in this at or after\n            // start, or -1 if not found\n            ssize_t             find(const char* other, size_t start = 0) const;\n\n            // return true if this string contains the specified substring\n    inline  bool                contains(const char* other) const;\n\n            // removes all occurrence of the specified substring\n            // returns true if any were found and removed\n            bool                removeAll(const char* other);\n\n            void                toLower();\n            void                toLower(size_t start, size_t numChars);\n            void                toUpper();\n            void                toUpper(size_t start, size_t numChars);\n\n\n    /*\n     * These methods operate on the string as if it were a path name.\n     */\n\n    /*\n     * Set the filename field to a specific value.\n     *\n     * Normalizes the filename, removing a trailing '/' if present.\n     */\n    void setPathName(const char* name);\n    void setPathName(const char* name, size_t numChars);\n\n    /*\n     * Get just the filename component.\n     *\n     * \"/tmp/foo/bar.c\" --> \"bar.c\"\n     */\n    String8 getPathLeaf(void) const;\n\n    /*\n     * Remove the last (file name) component, leaving just the directory\n     * name.\n     *\n     * \"/tmp/foo/bar.c\" --> \"/tmp/foo\"\n     * \"/tmp\" --> \"\" // ????? shouldn't this be \"/\" ???? XXX\n     * \"bar.c\" --> \"\"\n     */\n    String8 getPathDir(void) const;\n\n    /*\n     * Retrieve the front (root dir) component.  Optionally also return the\n     * remaining components.\n     *\n     * \"/tmp/foo/bar.c\" --> \"tmp\" (remain = \"foo/bar.c\")\n     * \"/tmp\" --> \"tmp\" (remain = \"\")\n     * \"bar.c\" --> \"bar.c\" (remain = \"\")\n     */\n    String8 walkPath(String8* outRemains = NULL) const;\n\n    /*\n     * Return the filename extension.  This is the last '.' and any number\n     * of characters that follow it.  The '.' is included in case we\n     * decide to expand our definition of what constitutes an extension.\n     *\n     * \"/tmp/foo/bar.c\" --> \".c\"\n     * \"/tmp\" --> \"\"\n     * \"/tmp/foo.bar/baz\" --> \"\"\n     * \"foo.jpeg\" --> \".jpeg\"\n     * \"foo.\" --> \"\"\n     */\n    String8 getPathExtension(void) const;\n\n    /*\n     * Return the path without the extension.  Rules for what constitutes\n     * an extension are described in the comment for getPathExtension().\n     *\n     * \"/tmp/foo/bar.c\" --> \"/tmp/foo/bar\"\n     */\n    String8 getBasePath(void) const;\n\n    /*\n     * Add a component to the pathname.  We guarantee that there is\n     * exactly one path separator between the old path and the new.\n     * If there is no existing name, we just copy the new name in.\n     *\n     * If leaf is a fully qualified path (i.e. starts with '/', it\n     * replaces whatever was there before.\n     */\n    String8& appendPath(const char* leaf);\n    String8& appendPath(const String8& leaf)  { return appendPath(leaf.string()); }\n\n    /*\n     * Like appendPath(), but does not affect this string.  Returns a new one instead.\n     */\n    String8 appendPathCopy(const char* leaf) const\n                                             { String8 p(*this); p.appendPath(leaf); return p; }\n    String8 appendPathCopy(const String8& leaf) const { return appendPathCopy(leaf.string()); }\n\n    /*\n     * Converts all separators in this string to /, the default path separator.\n     *\n     * If the default OS separator is backslash, this converts all\n     * backslashes to slashes, in-place. Otherwise it does nothing.\n     * Returns self.\n     */\n    String8& convertToResPath();\n\nprivate:\n            status_t            real_append(const char* other, size_t numChars);\n            char*               find_extension(void) const;\n\n            const char* mString;\n};\n\n// String8 can be trivially moved using memcpy() because moving does not\n// require any change to the underlying SharedBuffer contents or reference count.\nANDROID_TRIVIAL_MOVE_TRAIT(String8)\n\n// ---------------------------------------------------------------------------\n// No user servicable parts below.\n\ninline int compare_type(const String8& lhs, const String8& rhs)\n{\n    return lhs.compare(rhs);\n}\n\ninline int strictly_order_type(const String8& lhs, const String8& rhs)\n{\n    return compare_type(lhs, rhs) < 0;\n}\n\ninline const String8 String8::empty() {\n    return String8();\n}\n\ninline const char* String8::string() const\n{\n    return mString;\n}\n\ninline size_t String8::length() const\n{\n    return SharedBuffer::sizeFromData(mString)-1;\n}\n\ninline size_t String8::size() const\n{\n    return length();\n}\n\ninline bool String8::isEmpty() const\n{\n    return length() == 0;\n}\n\ninline size_t String8::bytes() const\n{\n    return SharedBuffer::sizeFromData(mString)-1;\n}\n\ninline const SharedBuffer* String8::sharedBuffer() const\n{\n    return SharedBuffer::bufferFromData(mString);\n}\n\ninline bool String8::contains(const char* other) const\n{\n    return find(other) >= 0;\n}\n\ninline String8& String8::operator=(const String8& other)\n{\n    setTo(other);\n    return *this;\n}\n\ninline String8& String8::operator=(const char* other)\n{\n    setTo(other);\n    return *this;\n}\n\ninline String8& String8::operator+=(const String8& other)\n{\n    append(other);\n    return *this;\n}\n\ninline String8 String8::operator+(const String8& other) const\n{\n    String8 tmp(*this);\n    tmp += other;\n    return tmp;\n}\n\ninline String8& String8::operator+=(const char* other)\n{\n    append(other);\n    return *this;\n}\n\ninline String8 String8::operator+(const char* other) const\n{\n    String8 tmp(*this);\n    tmp += other;\n    return tmp;\n}\n\ninline int String8::compare(const String8& other) const\n{\n    return strcmp(mString, other.mString);\n}\n\ninline bool String8::operator<(const String8& other) const\n{\n    return strcmp(mString, other.mString) < 0;\n}\n\ninline bool String8::operator<=(const String8& other) const\n{\n    return strcmp(mString, other.mString) <= 0;\n}\n\ninline bool String8::operator==(const String8& other) const\n{\n    return strcmp(mString, other.mString) == 0;\n}\n\ninline bool String8::operator!=(const String8& other) const\n{\n    return strcmp(mString, other.mString) != 0;\n}\n\ninline bool String8::operator>=(const String8& other) const\n{\n    return strcmp(mString, other.mString) >= 0;\n}\n\ninline bool String8::operator>(const String8& other) const\n{\n    return strcmp(mString, other.mString) > 0;\n}\n\ninline bool String8::operator<(const char* other) const\n{\n    return strcmp(mString, other) < 0;\n}\n\ninline bool String8::operator<=(const char* other) const\n{\n    return strcmp(mString, other) <= 0;\n}\n\ninline bool String8::operator==(const char* other) const\n{\n    return strcmp(mString, other) == 0;\n}\n\ninline bool String8::operator!=(const char* other) const\n{\n    return strcmp(mString, other) != 0;\n}\n\ninline bool String8::operator>=(const char* other) const\n{\n    return strcmp(mString, other) >= 0;\n}\n\ninline bool String8::operator>(const char* other) const\n{\n    return strcmp(mString, other) > 0;\n}\n\ninline String8::operator const char*() const\n{\n    return mString;\n}\n\n}  // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_STRING8_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/StrongPointer.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_STRONG_POINTER_H\n#define ANDROID_STRONG_POINTER_H\n\n#include <cutils/atomic.h>\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <stdlib.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n\ntemplate<typename T> class wp;\n\n// ---------------------------------------------------------------------------\n\n#define COMPARE(_op_)                                           \\\ninline bool operator _op_ (const sp<T>& o) const {              \\\n    return m_ptr _op_ o.m_ptr;                                  \\\n}                                                               \\\ninline bool operator _op_ (const T* o) const {                  \\\n    return m_ptr _op_ o;                                        \\\n}                                                               \\\ntemplate<typename U>                                            \\\ninline bool operator _op_ (const sp<U>& o) const {              \\\n    return m_ptr _op_ o.m_ptr;                                  \\\n}                                                               \\\ntemplate<typename U>                                            \\\ninline bool operator _op_ (const U* o) const {                  \\\n    return m_ptr _op_ o;                                        \\\n}                                                               \\\ninline bool operator _op_ (const wp<T>& o) const {              \\\n    return m_ptr _op_ o.m_ptr;                                  \\\n}                                                               \\\ntemplate<typename U>                                            \\\ninline bool operator _op_ (const wp<U>& o) const {              \\\n    return m_ptr _op_ o.m_ptr;                                  \\\n}\n\n// ---------------------------------------------------------------------------\n\ntemplate<typename T>\nclass sp {\npublic:\n    inline sp() : m_ptr(0) { }\n\n    sp(T* other);\n    sp(const sp<T>& other);\n    template<typename U> sp(U* other);\n    template<typename U> sp(const sp<U>& other);\n\n    ~sp();\n\n    // Assignment\n\n    sp& operator = (T* other);\n    sp& operator = (const sp<T>& other);\n\n    template<typename U> sp& operator = (const sp<U>& other);\n    template<typename U> sp& operator = (U* other);\n\n    //! Special optimization for use by ProcessState (and nobody else).\n    void force_set(T* other);\n\n    // Reset\n\n    void clear();\n\n    // Accessors\n\n    inline  T&      operator* () const  { return *m_ptr; }\n    inline  T*      operator-> () const { return m_ptr;  }\n    inline  T*      get() const         { return m_ptr; }\n\n    // Operators\n\n    COMPARE(==)\n    COMPARE(!=)\n    COMPARE(>)\n    COMPARE(<)\n    COMPARE(<=)\n    COMPARE(>=)\n\nprivate:    \n    template<typename Y> friend class sp;\n    template<typename Y> friend class wp;\n    void set_pointer(T* ptr);\n    T* m_ptr;\n};\n\n#undef COMPARE\n\n// ---------------------------------------------------------------------------\n// No user serviceable parts below here.\n\ntemplate<typename T>\nsp<T>::sp(T* other)\n        : m_ptr(other) {\n    if (other)\n        other->incStrong(this);\n}\n\ntemplate<typename T>\nsp<T>::sp(const sp<T>& other)\n        : m_ptr(other.m_ptr) {\n    if (m_ptr)\n        m_ptr->incStrong(this);\n}\n\ntemplate<typename T> template<typename U>\nsp<T>::sp(U* other)\n        : m_ptr(other) {\n    if (other)\n        ((T*) other)->incStrong(this);\n}\n\ntemplate<typename T> template<typename U>\nsp<T>::sp(const sp<U>& other)\n        : m_ptr(other.m_ptr) {\n    if (m_ptr)\n        m_ptr->incStrong(this);\n}\n\ntemplate<typename T>\nsp<T>::~sp() {\n    if (m_ptr)\n        m_ptr->decStrong(this);\n}\n\ntemplate<typename T>\nsp<T>& sp<T>::operator =(const sp<T>& other) {\n    T* otherPtr(other.m_ptr);\n    if (otherPtr)\n        otherPtr->incStrong(this);\n    if (m_ptr)\n        m_ptr->decStrong(this);\n    m_ptr = otherPtr;\n    return *this;\n}\n\ntemplate<typename T>\nsp<T>& sp<T>::operator =(T* other) {\n    if (other)\n        other->incStrong(this);\n    if (m_ptr)\n        m_ptr->decStrong(this);\n    m_ptr = other;\n    return *this;\n}\n\ntemplate<typename T> template<typename U>\nsp<T>& sp<T>::operator =(const sp<U>& other) {\n    T* otherPtr(other.m_ptr);\n    if (otherPtr)\n        otherPtr->incStrong(this);\n    if (m_ptr)\n        m_ptr->decStrong(this);\n    m_ptr = otherPtr;\n    return *this;\n}\n\ntemplate<typename T> template<typename U>\nsp<T>& sp<T>::operator =(U* other) {\n    if (other)\n        ((T*) other)->incStrong(this);\n    if (m_ptr)\n        m_ptr->decStrong(this);\n    m_ptr = other;\n    return *this;\n}\n\ntemplate<typename T>\nvoid sp<T>::force_set(T* other) {\n    other->forceIncStrong(this);\n    m_ptr = other;\n}\n\ntemplate<typename T>\nvoid sp<T>::clear() {\n    if (m_ptr) {\n        m_ptr->decStrong(this);\n        m_ptr = 0;\n    }\n}\n\ntemplate<typename T>\nvoid sp<T>::set_pointer(T* ptr) {\n    m_ptr = ptr;\n}\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_STRONG_POINTER_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/SystemClock.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UTILS_SYSTEMCLOCK_H\n#define ANDROID_UTILS_SYSTEMCLOCK_H\n\n#include <stdint.h>\n#include <sys/types.h>\n\nnamespace android {\n\nint64_t uptimeMillis();\nint64_t elapsedRealtime();\nint64_t elapsedRealtimeNano();\n\n}; // namespace android\n\n#endif // ANDROID_UTILS_SYSTEMCLOCK_H\n\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Thread.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_THREAD_H\n#define _LIBS_UTILS_THREAD_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <time.h>\n\n#if !defined(_WIN32)\n# include <pthread.h>\n#endif\n\n#include <utils/Condition.h>\n#include <utils/Errors.h>\n#include <utils/Mutex.h>\n#include <utils/RefBase.h>\n#include <utils/Timers.h>\n#include <utils/ThreadDefs.h>\n\n// ---------------------------------------------------------------------------\nnamespace android {\n// ---------------------------------------------------------------------------\n\nclass Thread : virtual public RefBase\n{\npublic:\n    // Create a Thread object, but doesn't create or start the associated\n    // thread. See the run() method.\n                        Thread(bool canCallJava = true);\n    virtual             ~Thread();\n\n    // Start the thread in threadLoop() which needs to be implemented.\n    virtual status_t    run(    const char* name = 0,\n                                int32_t priority = PRIORITY_DEFAULT,\n                                size_t stack = 0);\n    \n    // Ask this object's thread to exit. This function is asynchronous, when the\n    // function returns the thread might still be running. Of course, this\n    // function can be called from a different thread.\n    virtual void        requestExit();\n\n    // Good place to do one-time initializations\n    virtual status_t    readyToRun();\n    \n    // Call requestExit() and wait until this object's thread exits.\n    // BE VERY CAREFUL of deadlocks. In particular, it would be silly to call\n    // this function from this object's thread. Will return WOULD_BLOCK in\n    // that case.\n            status_t    requestExitAndWait();\n\n    // Wait until this object's thread exits. Returns immediately if not yet running.\n    // Do not call from this object's thread; will return WOULD_BLOCK in that case.\n            status_t    join();\n\n    // Indicates whether this thread is running or not.\n            bool        isRunning() const;\n\n#ifdef HAVE_ANDROID_OS\n    // Return the thread's kernel ID, same as the thread itself calling gettid(),\n    // or -1 if the thread is not running.\n            pid_t       getTid() const;\n#endif\n\nprotected:\n    // exitPending() returns true if requestExit() has been called.\n            bool        exitPending() const;\n    \nprivate:\n    // Derived class must implement threadLoop(). The thread starts its life\n    // here. There are two ways of using the Thread object:\n    // 1) loop: if threadLoop() returns true, it will be called again if\n    //          requestExit() wasn't called.\n    // 2) once: if threadLoop() returns false, the thread will exit upon return.\n    virtual bool        threadLoop() = 0;\n\nprivate:\n    Thread& operator=(const Thread&);\n    static  int             _threadLoop(void* user);\n    const   bool            mCanCallJava;\n    // always hold mLock when reading or writing\n            thread_id_t     mThread;\n    mutable Mutex           mLock;\n            Condition       mThreadExitedCondition;\n            status_t        mStatus;\n    // note that all accesses of mExitPending and mRunning need to hold mLock\n    volatile bool           mExitPending;\n    volatile bool           mRunning;\n            sp<Thread>      mHoldSelf;\n#ifdef HAVE_ANDROID_OS\n    // legacy for debugging, not used by getTid() as it is set by the child thread\n    // and so is not initialized until the child reaches that point\n            pid_t           mTid;\n#endif\n};\n\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n#endif // _LIBS_UTILS_THREAD_H\n// ---------------------------------------------------------------------------\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/ThreadDefs.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_THREAD_DEFS_H\n#define _LIBS_UTILS_THREAD_DEFS_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <system/graphics.h>\n#include <system/thread_defs.h>\n\n// ---------------------------------------------------------------------------\n// C API\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef void* android_thread_id_t;\n\ntypedef int (*android_thread_func_t)(void*);\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n// ---------------------------------------------------------------------------\n// C++ API\n#ifdef __cplusplus\nnamespace android {\n// ---------------------------------------------------------------------------\n\ntypedef android_thread_id_t thread_id_t;\ntypedef android_thread_func_t thread_func_t;\n\nenum {\n    PRIORITY_LOWEST         = ANDROID_PRIORITY_LOWEST,\n    PRIORITY_BACKGROUND     = ANDROID_PRIORITY_BACKGROUND,\n    PRIORITY_NORMAL         = ANDROID_PRIORITY_NORMAL,\n    PRIORITY_FOREGROUND     = ANDROID_PRIORITY_FOREGROUND,\n    PRIORITY_DISPLAY        = ANDROID_PRIORITY_DISPLAY,\n    PRIORITY_URGENT_DISPLAY = ANDROID_PRIORITY_URGENT_DISPLAY,\n    PRIORITY_AUDIO          = ANDROID_PRIORITY_AUDIO,\n    PRIORITY_URGENT_AUDIO   = ANDROID_PRIORITY_URGENT_AUDIO,\n    PRIORITY_HIGHEST        = ANDROID_PRIORITY_HIGHEST,\n    PRIORITY_DEFAULT        = ANDROID_PRIORITY_DEFAULT,\n    PRIORITY_MORE_FAVORABLE = ANDROID_PRIORITY_MORE_FAVORABLE,\n    PRIORITY_LESS_FAVORABLE = ANDROID_PRIORITY_LESS_FAVORABLE,\n};\n\n// ---------------------------------------------------------------------------\n}; // namespace android\n#endif  // __cplusplus\n// ---------------------------------------------------------------------------\n\n\n#endif // _LIBS_UTILS_THREAD_DEFS_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Timers.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// Timer functions.\n//\n#ifndef _LIBS_UTILS_TIMERS_H\n#define _LIBS_UTILS_TIMERS_H\n\n#include <stdint.h>\n#include <sys/types.h>\n#include <sys/time.h>\n\n#include <utils/Compat.h>\n\n// ------------------------------------------------------------------\n// C API\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef int64_t nsecs_t;       // nano-seconds\n\nstatic CONSTEXPR inline nsecs_t seconds_to_nanoseconds(nsecs_t secs)\n{\n    return secs*1000000000;\n}\n\nstatic CONSTEXPR inline nsecs_t milliseconds_to_nanoseconds(nsecs_t secs)\n{\n    return secs*1000000;\n}\n\nstatic CONSTEXPR inline nsecs_t microseconds_to_nanoseconds(nsecs_t secs)\n{\n    return secs*1000;\n}\n\nstatic CONSTEXPR inline nsecs_t nanoseconds_to_seconds(nsecs_t secs)\n{\n    return secs/1000000000;\n}\n\nstatic CONSTEXPR inline nsecs_t nanoseconds_to_milliseconds(nsecs_t secs)\n{\n    return secs/1000000;\n}\n\nstatic CONSTEXPR inline nsecs_t nanoseconds_to_microseconds(nsecs_t secs)\n{\n    return secs/1000;\n}\n\nstatic CONSTEXPR inline nsecs_t s2ns(nsecs_t v)  {return seconds_to_nanoseconds(v);}\nstatic CONSTEXPR inline nsecs_t ms2ns(nsecs_t v) {return milliseconds_to_nanoseconds(v);}\nstatic CONSTEXPR inline nsecs_t us2ns(nsecs_t v) {return microseconds_to_nanoseconds(v);}\nstatic CONSTEXPR inline nsecs_t ns2s(nsecs_t v)  {return nanoseconds_to_seconds(v);}\nstatic CONSTEXPR inline nsecs_t ns2ms(nsecs_t v) {return nanoseconds_to_milliseconds(v);}\nstatic CONSTEXPR inline nsecs_t ns2us(nsecs_t v) {return nanoseconds_to_microseconds(v);}\n\nstatic CONSTEXPR inline nsecs_t seconds(nsecs_t v)      { return s2ns(v); }\nstatic CONSTEXPR inline nsecs_t milliseconds(nsecs_t v) { return ms2ns(v); }\nstatic CONSTEXPR inline nsecs_t microseconds(nsecs_t v) { return us2ns(v); }\n\nenum {\n    SYSTEM_TIME_REALTIME = 0,  // system-wide realtime clock\n    SYSTEM_TIME_MONOTONIC = 1, // monotonic time since unspecified starting point\n    SYSTEM_TIME_PROCESS = 2,   // high-resolution per-process clock\n    SYSTEM_TIME_THREAD = 3,    // high-resolution per-thread clock\n    SYSTEM_TIME_BOOTTIME = 4   // same as SYSTEM_TIME_MONOTONIC, but including CPU suspend time\n};\n\n// return the system-time according to the specified clock\n#ifdef __cplusplus\nnsecs_t systemTime(int clock = SYSTEM_TIME_MONOTONIC);\n#else\nnsecs_t systemTime(int clock);\n#endif // def __cplusplus\n\n/**\n * Returns the number of milliseconds to wait between the reference time and the timeout time.\n * If the timeout is in the past relative to the reference time, returns 0.\n * If the timeout is more than INT_MAX milliseconds in the future relative to the reference time,\n * such as when timeoutTime == LLONG_MAX, returns -1 to indicate an infinite timeout delay.\n * Otherwise, returns the difference between the reference time and timeout time\n * rounded up to the next millisecond.\n */\nint toMillisecondTimeoutDelay(nsecs_t referenceTime, nsecs_t timeoutTime);\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n#endif // _LIBS_UTILS_TIMERS_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Tokenizer.h",
    "content": "/*\n * Copyright (C) 2010 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _UTILS_TOKENIZER_H\n#define _UTILS_TOKENIZER_H\n\n#include <assert.h>\n#include <utils/Errors.h>\n#include <utils/FileMap.h>\n#include <utils/String8.h>\n\nnamespace android {\n\n/**\n * A simple tokenizer for loading and parsing ASCII text files line by line.\n */\nclass Tokenizer {\n    Tokenizer(const String8& filename, FileMap* fileMap, char* buffer,\n            bool ownBuffer, size_t length);\n\npublic:\n    ~Tokenizer();\n\n    /**\n     * Opens a file and maps it into memory.\n     *\n     * Returns NO_ERROR and a tokenizer for the file, if successful.\n     * Otherwise returns an error and sets outTokenizer to NULL.\n     */\n    static status_t open(const String8& filename, Tokenizer** outTokenizer);\n\n    /**\n     * Prepares to tokenize the contents of a string.\n     *\n     * Returns NO_ERROR and a tokenizer for the string, if successful.\n     * Otherwise returns an error and sets outTokenizer to NULL.\n     */\n    static status_t fromContents(const String8& filename,\n            const char* contents, Tokenizer** outTokenizer);\n\n    /**\n     * Returns true if at the end of the file.\n     */\n    inline bool isEof() const { return mCurrent == getEnd(); }\n\n    /**\n     * Returns true if at the end of the line or end of the file.\n     */\n    inline bool isEol() const { return isEof() || *mCurrent == '\\n'; }\n\n    /**\n     * Gets the name of the file.\n     */\n    inline String8 getFilename() const { return mFilename; }\n\n    /**\n     * Gets a 1-based line number index for the current position.\n     */\n    inline int32_t getLineNumber() const { return mLineNumber; }\n\n    /**\n     * Formats a location string consisting of the filename and current line number.\n     * Returns a string like \"MyFile.txt:33\".\n     */\n    String8 getLocation() const;\n\n    /**\n     * Gets the character at the current position.\n     * Returns null at end of file.\n     */\n    inline char peekChar() const { return isEof() ? '\\0' : *mCurrent; }\n\n    /**\n     * Gets the remainder of the current line as a string, excluding the newline character.\n     */\n    String8 peekRemainderOfLine() const;\n\n    /**\n     * Gets the character at the current position and advances past it.\n     * Returns null at end of file.\n     */\n    inline char nextChar() { return isEof() ? '\\0' : *(mCurrent++); }\n\n    /**\n     * Gets the next token on this line stopping at the specified delimiters\n     * or the end of the line whichever comes first and advances past it.\n     * Also stops at embedded nulls.\n     * Returns the token or an empty string if the current character is a delimiter\n     * or is at the end of the line.\n     */\n    String8 nextToken(const char* delimiters);\n\n    /**\n     * Advances to the next line.\n     * Does nothing if already at the end of the file.\n     */\n    void nextLine();\n\n    /**\n     * Skips over the specified delimiters in the line.\n     * Also skips embedded nulls.\n     */\n    void skipDelimiters(const char* delimiters);\n\nprivate:\n    Tokenizer(const Tokenizer& other); // not copyable\n\n    String8 mFilename;\n    FileMap* mFileMap;\n    char* mBuffer;\n    bool mOwnBuffer;\n    size_t mLength;\n\n    const char* mCurrent;\n    int32_t mLineNumber;\n\n    inline const char* getEnd() const { return mBuffer + mLength; }\n\n};\n\n} // namespace android\n\n#endif // _UTILS_TOKENIZER_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Trace.h",
    "content": "/*\n * Copyright (C) 2012 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_TRACE_H\n#define ANDROID_TRACE_H\n\n#ifdef HAVE_ANDROID_OS\n\n#include <fcntl.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <string.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <unistd.h>\n\n#include <cutils/compiler.h>\n#include <utils/threads.h>\n#include <cutils/trace.h>\n\n// See <cutils/trace.h> for more ATRACE_* macros.\n\n// ATRACE_NAME traces the beginning and end of the current scope.  To trace\n// the correct start and end times this macro should be declared first in the\n// scope body.\n#define ATRACE_NAME(name) android::ScopedTrace ___tracer(ATRACE_TAG, name)\n// ATRACE_CALL is an ATRACE_NAME that uses the current function name.\n#define ATRACE_CALL() ATRACE_NAME(__FUNCTION__)\n\nnamespace android {\n\nclass ScopedTrace {\npublic:\ninline ScopedTrace(uint64_t tag, const char* name)\n    : mTag(tag) {\n    atrace_begin(mTag,name);\n}\n\ninline ~ScopedTrace() {\n    atrace_end(mTag);\n}\n\nprivate:\n    uint64_t mTag;\n};\n\n}; // namespace android\n\n#else // HAVE_ANDROID_OS\n\n#define ATRACE_NAME(...)\n#define ATRACE_CALL()\n\n#endif // HAVE_ANDROID_OS\n\n#endif // ANDROID_TRACE_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/TypeHelpers.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_TYPE_HELPERS_H\n#define ANDROID_TYPE_HELPERS_H\n\n#include <new>\n#include <stdint.h>\n#include <string.h>\n#include <sys/types.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\n/*\n * Types traits\n */\n\ntemplate <typename T> struct trait_trivial_ctor { enum { value = false }; };\ntemplate <typename T> struct trait_trivial_dtor { enum { value = false }; };\ntemplate <typename T> struct trait_trivial_copy { enum { value = false }; };\ntemplate <typename T> struct trait_trivial_move { enum { value = false }; };\ntemplate <typename T> struct trait_pointer      { enum { value = false }; };    \ntemplate <typename T> struct trait_pointer<T*>  { enum { value = true }; };\n\ntemplate <typename TYPE>\nstruct traits {\n    enum {\n        // whether this type is a pointer\n        is_pointer          = trait_pointer<TYPE>::value,\n        // whether this type's constructor is a no-op\n        has_trivial_ctor    = is_pointer || trait_trivial_ctor<TYPE>::value,\n        // whether this type's destructor is a no-op\n        has_trivial_dtor    = is_pointer || trait_trivial_dtor<TYPE>::value,\n        // whether this type type can be copy-constructed with memcpy\n        has_trivial_copy    = is_pointer || trait_trivial_copy<TYPE>::value,\n        // whether this type can be moved with memmove\n        has_trivial_move    = is_pointer || trait_trivial_move<TYPE>::value\n    };\n};\n\ntemplate <typename T, typename U>\nstruct aggregate_traits {\n    enum {\n        is_pointer          = false,\n        has_trivial_ctor    = \n            traits<T>::has_trivial_ctor && traits<U>::has_trivial_ctor,\n        has_trivial_dtor    = \n            traits<T>::has_trivial_dtor && traits<U>::has_trivial_dtor,\n        has_trivial_copy    = \n            traits<T>::has_trivial_copy && traits<U>::has_trivial_copy,\n        has_trivial_move    = \n            traits<T>::has_trivial_move && traits<U>::has_trivial_move\n    };\n};\n\n#define ANDROID_TRIVIAL_CTOR_TRAIT( T ) \\\n    template<> struct trait_trivial_ctor< T >   { enum { value = true }; };\n\n#define ANDROID_TRIVIAL_DTOR_TRAIT( T ) \\\n    template<> struct trait_trivial_dtor< T >   { enum { value = true }; };\n\n#define ANDROID_TRIVIAL_COPY_TRAIT( T ) \\\n    template<> struct trait_trivial_copy< T >   { enum { value = true }; };\n\n#define ANDROID_TRIVIAL_MOVE_TRAIT( T ) \\\n    template<> struct trait_trivial_move< T >   { enum { value = true }; };\n\n#define ANDROID_BASIC_TYPES_TRAITS( T ) \\\n    ANDROID_TRIVIAL_CTOR_TRAIT( T ) \\\n    ANDROID_TRIVIAL_DTOR_TRAIT( T ) \\\n    ANDROID_TRIVIAL_COPY_TRAIT( T ) \\\n    ANDROID_TRIVIAL_MOVE_TRAIT( T )\n\n// ---------------------------------------------------------------------------\n\n/*\n * basic types traits\n */\n\nANDROID_BASIC_TYPES_TRAITS( void )\nANDROID_BASIC_TYPES_TRAITS( bool )\nANDROID_BASIC_TYPES_TRAITS( char )\nANDROID_BASIC_TYPES_TRAITS( unsigned char )\nANDROID_BASIC_TYPES_TRAITS( short )\nANDROID_BASIC_TYPES_TRAITS( unsigned short )\nANDROID_BASIC_TYPES_TRAITS( int )\nANDROID_BASIC_TYPES_TRAITS( unsigned int )\nANDROID_BASIC_TYPES_TRAITS( long )\nANDROID_BASIC_TYPES_TRAITS( unsigned long )\nANDROID_BASIC_TYPES_TRAITS( long long )\nANDROID_BASIC_TYPES_TRAITS( unsigned long long )\nANDROID_BASIC_TYPES_TRAITS( float )\nANDROID_BASIC_TYPES_TRAITS( double )\n\n// ---------------------------------------------------------------------------\n\n\n/*\n * compare and order types\n */\n\ntemplate<typename TYPE> inline\nint strictly_order_type(const TYPE& lhs, const TYPE& rhs) {\n    return (lhs < rhs) ? 1 : 0;\n}\n\ntemplate<typename TYPE> inline\nint compare_type(const TYPE& lhs, const TYPE& rhs) {\n    return strictly_order_type(rhs, lhs) - strictly_order_type(lhs, rhs);\n}\n\n/*\n * create, destroy, copy and move types...\n */\n\ntemplate<typename TYPE> inline\nvoid construct_type(TYPE* p, size_t n) {\n    if (!traits<TYPE>::has_trivial_ctor) {\n        while (n--) {\n            new(p++) TYPE;\n        }\n    }\n}\n\ntemplate<typename TYPE> inline\nvoid destroy_type(TYPE* p, size_t n) {\n    if (!traits<TYPE>::has_trivial_dtor) {\n        while (n--) {\n            p->~TYPE();\n            p++;\n        }\n    }\n}\n\ntemplate<typename TYPE> inline\nvoid copy_type(TYPE* d, const TYPE* s, size_t n) {\n    if (!traits<TYPE>::has_trivial_copy) {\n        while (n--) {\n            new(d) TYPE(*s);\n            d++, s++;\n        }\n    } else {\n        memcpy(d,s,n*sizeof(TYPE));\n    }\n}\n\ntemplate<typename TYPE> inline\nvoid splat_type(TYPE* where, const TYPE* what, size_t n) {\n    if (!traits<TYPE>::has_trivial_copy) {\n        while (n--) {\n            new(where) TYPE(*what);\n            where++;\n        }\n    } else {\n        while (n--) {\n            *where++ = *what;\n        }\n    }\n}\n\ntemplate<typename TYPE> inline\nvoid move_forward_type(TYPE* d, const TYPE* s, size_t n = 1) {\n    if ((traits<TYPE>::has_trivial_dtor && traits<TYPE>::has_trivial_copy) \n            || traits<TYPE>::has_trivial_move) \n    {\n        memmove(d,s,n*sizeof(TYPE));\n    } else {\n        d += n;\n        s += n;\n        while (n--) {\n            --d, --s;\n            if (!traits<TYPE>::has_trivial_copy) {\n                new(d) TYPE(*s);\n            } else {\n                *d = *s;   \n            }\n            if (!traits<TYPE>::has_trivial_dtor) {\n                s->~TYPE();\n            }\n        }\n    }\n}\n\ntemplate<typename TYPE> inline\nvoid move_backward_type(TYPE* d, const TYPE* s, size_t n = 1) {\n    if ((traits<TYPE>::has_trivial_dtor && traits<TYPE>::has_trivial_copy) \n            || traits<TYPE>::has_trivial_move) \n    {\n        memmove(d,s,n*sizeof(TYPE));\n    } else {\n        while (n--) {\n            if (!traits<TYPE>::has_trivial_copy) {\n                new(d) TYPE(*s);\n            } else {\n                *d = *s;   \n            }\n            if (!traits<TYPE>::has_trivial_dtor) {\n                s->~TYPE();\n            }\n            d++, s++;\n        }\n    }\n}\n\n// ---------------------------------------------------------------------------\n\n/*\n * a key/value pair\n */\n\ntemplate <typename KEY, typename VALUE>\nstruct key_value_pair_t {\n    typedef KEY key_t;\n    typedef VALUE value_t;\n\n    KEY     key;\n    VALUE   value;\n    key_value_pair_t() { }\n    key_value_pair_t(const key_value_pair_t& o) : key(o.key), value(o.value) { }\n    key_value_pair_t(const KEY& k, const VALUE& v) : key(k), value(v)  { }\n    key_value_pair_t(const KEY& k) : key(k) { }\n    inline bool operator < (const key_value_pair_t& o) const {\n        return strictly_order_type(key, o.key);\n    }\n    inline const KEY& getKey() const {\n        return key;\n    }\n    inline const VALUE& getValue() const {\n        return value;\n    }\n};\n\ntemplate <typename K, typename V>\nstruct trait_trivial_ctor< key_value_pair_t<K, V> >\n{ enum { value = aggregate_traits<K,V>::has_trivial_ctor }; };\ntemplate <typename K, typename V>\nstruct trait_trivial_dtor< key_value_pair_t<K, V> >\n{ enum { value = aggregate_traits<K,V>::has_trivial_dtor }; };\ntemplate <typename K, typename V>\nstruct trait_trivial_copy< key_value_pair_t<K, V> >\n{ enum { value = aggregate_traits<K,V>::has_trivial_copy }; };\ntemplate <typename K, typename V>\nstruct trait_trivial_move< key_value_pair_t<K, V> >\n{ enum { value = aggregate_traits<K,V>::has_trivial_move }; };\n\n// ---------------------------------------------------------------------------\n\n/*\n * Hash codes.\n */\ntypedef uint32_t hash_t;\n\ntemplate <typename TKey>\nhash_t hash_type(const TKey& key);\n\n/* Built-in hash code specializations.\n * Assumes pointers are 32bit. */\n#define ANDROID_INT32_HASH(T) \\\n        template <> inline hash_t hash_type(const T& value) { return hash_t(value); }\n#define ANDROID_INT64_HASH(T) \\\n        template <> inline hash_t hash_type(const T& value) { \\\n                return hash_t((value >> 32) ^ value); }\n#define ANDROID_REINTERPRET_HASH(T, R) \\\n        template <> inline hash_t hash_type(const T& value) { \\\n                return hash_type(*reinterpret_cast<const R*>(&value)); }\n\nANDROID_INT32_HASH(bool)\nANDROID_INT32_HASH(int8_t)\nANDROID_INT32_HASH(uint8_t)\nANDROID_INT32_HASH(int16_t)\nANDROID_INT32_HASH(uint16_t)\nANDROID_INT32_HASH(int32_t)\nANDROID_INT32_HASH(uint32_t)\nANDROID_INT64_HASH(int64_t)\nANDROID_INT64_HASH(uint64_t)\nANDROID_REINTERPRET_HASH(float, uint32_t)\nANDROID_REINTERPRET_HASH(double, uint64_t)\n\ntemplate <typename T> inline hash_t hash_type(T* const & value) {\n    return hash_type(uintptr_t(value));\n}\n\n}; // namespace android\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_TYPE_HELPERS_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Unicode.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_UNICODE_H\n#define ANDROID_UNICODE_H\n\n#include <sys/types.h>\n#include <stdint.h>\n\nextern \"C\" {\n\n// Standard string functions on char16_t strings.\nint strcmp16(const char16_t *, const char16_t *);\nint strncmp16(const char16_t *s1, const char16_t *s2, size_t n);\nsize_t strlen16(const char16_t *);\nsize_t strnlen16(const char16_t *, size_t);\nchar16_t *strcpy16(char16_t *, const char16_t *);\nchar16_t *strncpy16(char16_t *, const char16_t *, size_t);\n\n// Version of comparison that supports embedded nulls.\n// This is different than strncmp() because we don't stop\n// at a nul character and consider the strings to be different\n// if the lengths are different (thus we need to supply the\n// lengths of both strings).  This can also be used when\n// your string is not nul-terminated as it will have the\n// equivalent result as strcmp16 (unlike strncmp16).\nint strzcmp16(const char16_t *s1, size_t n1, const char16_t *s2, size_t n2);\n\n// Version of strzcmp16 for comparing strings in different endianness.\nint strzcmp16_h_n(const char16_t *s1H, size_t n1, const char16_t *s2N, size_t n2);\n\n// Standard string functions on char32_t strings.\nsize_t strlen32(const char32_t *);\nsize_t strnlen32(const char32_t *, size_t);\n\n/**\n * Measure the length of a UTF-32 string in UTF-8. If the string is invalid\n * such as containing a surrogate character, -1 will be returned.\n */\nssize_t utf32_to_utf8_length(const char32_t *src, size_t src_len);\n\n/**\n * Stores a UTF-8 string converted from \"src\" in \"dst\", if \"dst_length\" is not\n * large enough to store the string, the part of the \"src\" string is stored\n * into \"dst\" as much as possible. See the examples for more detail.\n * Returns the size actually used for storing the string.\n * dst\" is not null-terminated when dst_len is fully used (like strncpy).\n *\n * Example 1\n * \"src\" == \\u3042\\u3044 (\\xE3\\x81\\x82\\xE3\\x81\\x84)\n * \"src_len\" == 2\n * \"dst_len\" >= 7\n * ->\n * Returned value == 6\n * \"dst\" becomes \\xE3\\x81\\x82\\xE3\\x81\\x84\\0\n * (note that \"dst\" is null-terminated)\n *\n * Example 2\n * \"src\" == \\u3042\\u3044 (\\xE3\\x81\\x82\\xE3\\x81\\x84)\n * \"src_len\" == 2\n * \"dst_len\" == 5\n * ->\n * Returned value == 3\n * \"dst\" becomes \\xE3\\x81\\x82\\0\n * (note that \"dst\" is null-terminated, but \\u3044 is not stored in \"dst\"\n * since \"dst\" does not have enough size to store the character)\n *\n * Example 3\n * \"src\" == \\u3042\\u3044 (\\xE3\\x81\\x82\\xE3\\x81\\x84)\n * \"src_len\" == 2\n * \"dst_len\" == 6\n * ->\n * Returned value == 6\n * \"dst\" becomes \\xE3\\x81\\x82\\xE3\\x81\\x84\n * (note that \"dst\" is NOT null-terminated, like strncpy)\n */\nvoid utf32_to_utf8(const char32_t* src, size_t src_len, char* dst, size_t dst_len);\n\n/**\n * Returns the unicode value at \"index\".\n * Returns -1 when the index is invalid (equals to or more than \"src_len\").\n * If returned value is positive, it is able to be converted to char32_t, which\n * is unsigned. Then, if \"next_index\" is not NULL, the next index to be used is\n * stored in \"next_index\". \"next_index\" can be NULL.\n */\nint32_t utf32_from_utf8_at(const char *src, size_t src_len, size_t index, size_t *next_index);\n\n\n/**\n * Returns the UTF-8 length of UTF-16 string \"src\".\n */\nssize_t utf16_to_utf8_length(const char16_t *src, size_t src_len);\n\n/**\n * Converts a UTF-16 string to UTF-8. The destination buffer must be large\n * enough to fit the UTF-16 as measured by utf16_to_utf8_length with an added\n * NULL terminator.\n */\nvoid utf16_to_utf8(const char16_t* src, size_t src_len, char* dst, size_t dst_len);\n\n/**\n * Returns the length of \"src\" when \"src\" is valid UTF-8 string.\n * Returns 0 if src is NULL or 0-length string. Returns -1 when the source\n * is an invalid string.\n *\n * This function should be used to determine whether \"src\" is valid UTF-8\n * characters with valid unicode codepoints. \"src\" must be null-terminated.\n *\n * If you are going to use other utf8_to_... functions defined in this header\n * with string which may not be valid UTF-8 with valid codepoint (form 0 to\n * 0x10FFFF), you should use this function before calling others, since the\n * other functions do not check whether the string is valid UTF-8 or not.\n *\n * If you do not care whether \"src\" is valid UTF-8 or not, you should use\n * strlen() as usual, which should be much faster.\n */\nssize_t utf8_length(const char *src);\n\n/**\n * Measure the length of a UTF-32 string.\n */\nsize_t utf8_to_utf32_length(const char *src, size_t src_len);\n\n/**\n * Stores a UTF-32 string converted from \"src\" in \"dst\". \"dst\" must be large\n * enough to store the entire converted string as measured by\n * utf8_to_utf32_length plus space for a NULL terminator.\n */\nvoid utf8_to_utf32(const char* src, size_t src_len, char32_t* dst);\n\n/**\n * Returns the UTF-16 length of UTF-8 string \"src\".\n */\nssize_t utf8_to_utf16_length(const uint8_t* src, size_t srcLen);\n\n/**\n * Convert UTF-8 to UTF-16 including surrogate pairs.\n * Returns a pointer to the end of the string (where a null terminator might go\n * if you wanted to add one).\n */\nchar16_t* utf8_to_utf16_no_null_terminator(const uint8_t* src, size_t srcLen, char16_t* dst);\n\n/**\n * Convert UTF-8 to UTF-16 including surrogate pairs. The destination buffer\n * must be large enough to hold the result as measured by utf8_to_utf16_length\n * plus an added NULL terminator.\n */\nvoid utf8_to_utf16(const uint8_t* src, size_t srcLen, char16_t* dst);\n\n/**\n * Like utf8_to_utf16_no_null_terminator, but you can supply a maximum length of the\n * decoded string.  The decoded string will fill up to that length; if it is longer\n * the returned pointer will be to the character after dstLen.\n */\nchar16_t* utf8_to_utf16_n(const uint8_t* src, size_t srcLen, char16_t* dst, size_t dstLen);\n\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/Vector.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_VECTOR_H\n#define ANDROID_VECTOR_H\n\n#include <new>\n#include <stdint.h>\n#include <sys/types.h>\n\n#include <cutils/log.h>\n\n#include <utils/VectorImpl.h>\n#include <utils/TypeHelpers.h>\n\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\ntemplate <typename TYPE>\nclass SortedVector;\n\n/*!\n * The main templated vector class ensuring type safety\n * while making use of VectorImpl.\n * This is the class users want to use.\n */\n\ntemplate <class TYPE>\nclass Vector : private VectorImpl\n{\npublic:\n            typedef TYPE    value_type;\n    \n    /*! \n     * Constructors and destructors\n     */\n    \n                            Vector();\n                            Vector(const Vector<TYPE>& rhs);\n    explicit                Vector(const SortedVector<TYPE>& rhs);\n    virtual                 ~Vector();\n\n    /*! copy operator */\n            const Vector<TYPE>&     operator = (const Vector<TYPE>& rhs) const;\n            Vector<TYPE>&           operator = (const Vector<TYPE>& rhs);    \n\n            const Vector<TYPE>&     operator = (const SortedVector<TYPE>& rhs) const;\n            Vector<TYPE>&           operator = (const SortedVector<TYPE>& rhs);\n\n            /*\n     * empty the vector\n     */\n\n    inline  void            clear()             { VectorImpl::clear(); }\n\n    /*! \n     * vector stats\n     */\n\n    //! returns number of items in the vector\n    inline  size_t          size() const                { return VectorImpl::size(); }\n    //! returns whether or not the vector is empty\n    inline  bool            isEmpty() const             { return VectorImpl::isEmpty(); }\n    //! returns how many items can be stored without reallocating the backing store\n    inline  size_t          capacity() const            { return VectorImpl::capacity(); }\n    //! sets the capacity. capacity can never be reduced less than size()\n    inline  ssize_t         setCapacity(size_t size)    { return VectorImpl::setCapacity(size); }\n\n    /*!\n     * set the size of the vector. items are appended with the default\n     * constructor, or removed from the end as needed.\n     */\n    inline  ssize_t         resize(size_t size)         { return VectorImpl::resize(size); }\n\n    /*!\n     * C-style array access\n     */\n     \n    //! read-only C-style access \n    inline  const TYPE*     array() const;\n    //! read-write C-style access\n            TYPE*           editArray();\n    \n    /*! \n     * accessors\n     */\n\n    //! read-only access to an item at a given index\n    inline  const TYPE&     operator [] (size_t index) const;\n    //! alternate name for operator []\n    inline  const TYPE&     itemAt(size_t index) const;\n    //! stack-usage of the vector. returns the top of the stack (last element)\n            const TYPE&     top() const;\n\n    /*!\n     * modifying the array\n     */\n\n    //! copy-on write support, grants write access to an item\n            TYPE&           editItemAt(size_t index);\n    //! grants right access to the top of the stack (last element)\n            TYPE&           editTop();\n\n            /*! \n             * append/insert another vector\n             */\n            \n    //! insert another vector at a given index\n            ssize_t         insertVectorAt(const Vector<TYPE>& vector, size_t index);\n\n    //! append another vector at the end of this one\n            ssize_t         appendVector(const Vector<TYPE>& vector);\n\n\n    //! insert an array at a given index\n            ssize_t         insertArrayAt(const TYPE* array, size_t index, size_t length);\n\n    //! append an array at the end of this vector\n            ssize_t         appendArray(const TYPE* array, size_t length);\n\n            /*! \n             * add/insert/replace items\n             */\n             \n    //! insert one or several items initialized with their default constructor\n    inline  ssize_t         insertAt(size_t index, size_t numItems = 1);\n    //! insert one or several items initialized from a prototype item\n            ssize_t         insertAt(const TYPE& prototype_item, size_t index, size_t numItems = 1);\n    //! pop the top of the stack (removes the last element). No-op if the stack's empty\n    inline  void            pop();\n    //! pushes an item initialized with its default constructor\n    inline  void            push();\n    //! pushes an item on the top of the stack\n            void            push(const TYPE& item);\n    //! same as push() but returns the index the item was added at (or an error)\n    inline  ssize_t         add();\n    //! same as push() but returns the index the item was added at (or an error)\n            ssize_t         add(const TYPE& item);            \n    //! replace an item with a new one initialized with its default constructor\n    inline  ssize_t         replaceAt(size_t index);\n    //! replace an item with a new one\n            ssize_t         replaceAt(const TYPE& item, size_t index);\n\n    /*!\n     * remove items\n     */\n\n    //! remove several items\n    inline  ssize_t         removeItemsAt(size_t index, size_t count = 1);\n    //! remove one item\n    inline  ssize_t         removeAt(size_t index)  { return removeItemsAt(index); }\n\n    /*!\n     * sort (stable) the array\n     */\n     \n     typedef int (*compar_t)(const TYPE* lhs, const TYPE* rhs);\n     typedef int (*compar_r_t)(const TYPE* lhs, const TYPE* rhs, void* state);\n     \n     inline status_t        sort(compar_t cmp);\n     inline status_t        sort(compar_r_t cmp, void* state);\n\n     // for debugging only\n     inline size_t getItemSize() const { return itemSize(); }\n\n\n     /*\n      * these inlines add some level of compatibility with STL. eventually\n      * we should probably turn things around.\n      */\n     typedef TYPE* iterator;\n     typedef TYPE const* const_iterator;\n\n     inline iterator begin() { return editArray(); }\n     inline iterator end()   { return editArray() + size(); }\n     inline const_iterator begin() const { return array(); }\n     inline const_iterator end() const   { return array() + size(); }\n     inline void reserve(size_t n) { setCapacity(n); }\n     inline bool empty() const{ return isEmpty(); }\n     inline void push_back(const TYPE& item)  { insertAt(item, size(), 1); }\n     inline void push_front(const TYPE& item) { insertAt(item, 0, 1); }\n     inline iterator erase(iterator pos) {\n         ssize_t index = removeItemsAt(pos-array());\n         return begin() + index;\n     }\n\nprotected:\n    virtual void    do_construct(void* storage, size_t num) const;\n    virtual void    do_destroy(void* storage, size_t num) const;\n    virtual void    do_copy(void* dest, const void* from, size_t num) const;\n    virtual void    do_splat(void* dest, const void* item, size_t num) const;\n    virtual void    do_move_forward(void* dest, const void* from, size_t num) const;\n    virtual void    do_move_backward(void* dest, const void* from, size_t num) const;\n};\n\n// Vector<T> can be trivially moved using memcpy() because moving does not\n// require any change to the underlying SharedBuffer contents or reference count.\ntemplate<typename T> struct trait_trivial_move<Vector<T> > { enum { value = true }; };\n\n// ---------------------------------------------------------------------------\n// No user serviceable parts from here...\n// ---------------------------------------------------------------------------\n\ntemplate<class TYPE> inline\nVector<TYPE>::Vector()\n    : VectorImpl(sizeof(TYPE),\n                ((traits<TYPE>::has_trivial_ctor   ? HAS_TRIVIAL_CTOR   : 0)\n                |(traits<TYPE>::has_trivial_dtor   ? HAS_TRIVIAL_DTOR   : 0)\n                |(traits<TYPE>::has_trivial_copy   ? HAS_TRIVIAL_COPY   : 0))\n                )\n{\n}\n\ntemplate<class TYPE> inline\nVector<TYPE>::Vector(const Vector<TYPE>& rhs)\n    : VectorImpl(rhs) {\n}\n\ntemplate<class TYPE> inline\nVector<TYPE>::Vector(const SortedVector<TYPE>& rhs)\n    : VectorImpl(static_cast<const VectorImpl&>(rhs)) {\n}\n\ntemplate<class TYPE> inline\nVector<TYPE>::~Vector() {\n    finish_vector();\n}\n\ntemplate<class TYPE> inline\nVector<TYPE>& Vector<TYPE>::operator = (const Vector<TYPE>& rhs) {\n    VectorImpl::operator = (rhs);\n    return *this; \n}\n\ntemplate<class TYPE> inline\nconst Vector<TYPE>& Vector<TYPE>::operator = (const Vector<TYPE>& rhs) const {\n    VectorImpl::operator = (static_cast<const VectorImpl&>(rhs));\n    return *this;\n}\n\ntemplate<class TYPE> inline\nVector<TYPE>& Vector<TYPE>::operator = (const SortedVector<TYPE>& rhs) {\n    VectorImpl::operator = (static_cast<const VectorImpl&>(rhs));\n    return *this;\n}\n\ntemplate<class TYPE> inline\nconst Vector<TYPE>& Vector<TYPE>::operator = (const SortedVector<TYPE>& rhs) const {\n    VectorImpl::operator = (rhs);\n    return *this; \n}\n\ntemplate<class TYPE> inline\nconst TYPE* Vector<TYPE>::array() const {\n    return static_cast<const TYPE *>(arrayImpl());\n}\n\ntemplate<class TYPE> inline\nTYPE* Vector<TYPE>::editArray() {\n    return static_cast<TYPE *>(editArrayImpl());\n}\n\n\ntemplate<class TYPE> inline\nconst TYPE& Vector<TYPE>::operator[](size_t index) const {\n    LOG_FATAL_IF(index>=size(),\n            \"%s: index=%u out of range (%u)\", __PRETTY_FUNCTION__,\n            int(index), int(size()));\n    return *(array() + index);\n}\n\ntemplate<class TYPE> inline\nconst TYPE& Vector<TYPE>::itemAt(size_t index) const {\n    return operator[](index);\n}\n\ntemplate<class TYPE> inline\nconst TYPE& Vector<TYPE>::top() const {\n    return *(array() + size() - 1);\n}\n\ntemplate<class TYPE> inline\nTYPE& Vector<TYPE>::editItemAt(size_t index) {\n    return *( static_cast<TYPE *>(editItemLocation(index)) );\n}\n\ntemplate<class TYPE> inline\nTYPE& Vector<TYPE>::editTop() {\n    return *( static_cast<TYPE *>(editItemLocation(size()-1)) );\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::insertVectorAt(const Vector<TYPE>& vector, size_t index) {\n    return VectorImpl::insertVectorAt(reinterpret_cast<const VectorImpl&>(vector), index);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::appendVector(const Vector<TYPE>& vector) {\n    return VectorImpl::appendVector(reinterpret_cast<const VectorImpl&>(vector));\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::insertArrayAt(const TYPE* array, size_t index, size_t length) {\n    return VectorImpl::insertArrayAt(array, index, length);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::appendArray(const TYPE* array, size_t length) {\n    return VectorImpl::appendArray(array, length);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::insertAt(const TYPE& item, size_t index, size_t numItems) {\n    return VectorImpl::insertAt(&item, index, numItems);\n}\n\ntemplate<class TYPE> inline\nvoid Vector<TYPE>::push(const TYPE& item) {\n    return VectorImpl::push(&item);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::add(const TYPE& item) {\n    return VectorImpl::add(&item);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::replaceAt(const TYPE& item, size_t index) {\n    return VectorImpl::replaceAt(&item, index);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::insertAt(size_t index, size_t numItems) {\n    return VectorImpl::insertAt(index, numItems);\n}\n\ntemplate<class TYPE> inline\nvoid Vector<TYPE>::pop() {\n    VectorImpl::pop();\n}\n\ntemplate<class TYPE> inline\nvoid Vector<TYPE>::push() {\n    VectorImpl::push();\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::add() {\n    return VectorImpl::add();\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::replaceAt(size_t index) {\n    return VectorImpl::replaceAt(index);\n}\n\ntemplate<class TYPE> inline\nssize_t Vector<TYPE>::removeItemsAt(size_t index, size_t count) {\n    return VectorImpl::removeItemsAt(index, count);\n}\n\ntemplate<class TYPE> inline\nstatus_t Vector<TYPE>::sort(Vector<TYPE>::compar_t cmp) {\n    return VectorImpl::sort((VectorImpl::compar_t)cmp);\n}\n\ntemplate<class TYPE> inline\nstatus_t Vector<TYPE>::sort(Vector<TYPE>::compar_r_t cmp, void* state) {\n    return VectorImpl::sort((VectorImpl::compar_r_t)cmp, state);\n}\n\n// ---------------------------------------------------------------------------\n\ntemplate<class TYPE>\nvoid Vector<TYPE>::do_construct(void* storage, size_t num) const {\n    construct_type( reinterpret_cast<TYPE*>(storage), num );\n}\n\ntemplate<class TYPE>\nvoid Vector<TYPE>::do_destroy(void* storage, size_t num) const {\n    destroy_type( reinterpret_cast<TYPE*>(storage), num );\n}\n\ntemplate<class TYPE>\nvoid Vector<TYPE>::do_copy(void* dest, const void* from, size_t num) const {\n    copy_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(from), num );\n}\n\ntemplate<class TYPE>\nvoid Vector<TYPE>::do_splat(void* dest, const void* item, size_t num) const {\n    splat_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(item), num );\n}\n\ntemplate<class TYPE>\nvoid Vector<TYPE>::do_move_forward(void* dest, const void* from, size_t num) const {\n    move_forward_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(from), num );\n}\n\ntemplate<class TYPE>\nvoid Vector<TYPE>::do_move_backward(void* dest, const void* from, size_t num) const {\n    move_backward_type( reinterpret_cast<TYPE*>(dest), reinterpret_cast<const TYPE*>(from), num );\n}\n\n}; // namespace android\n\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_VECTOR_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/VectorImpl.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ANDROID_VECTOR_IMPL_H\n#define ANDROID_VECTOR_IMPL_H\n\n#include <assert.h>\n#include <stdint.h>\n#include <sys/types.h>\n#include <utils/Errors.h>\n\n// ---------------------------------------------------------------------------\n// No user serviceable parts in here...\n// ---------------------------------------------------------------------------\n\nnamespace android {\n\n/*!\n * Implementation of the guts of the vector<> class\n * this ensures backward binary compatibility and\n * reduces code size.\n * For performance reasons, we expose mStorage and mCount\n * so these fields are set in stone.\n *\n */\n\nclass VectorImpl\n{\npublic:\n    enum { // flags passed to the ctor\n        HAS_TRIVIAL_CTOR    = 0x00000001,\n        HAS_TRIVIAL_DTOR    = 0x00000002,\n        HAS_TRIVIAL_COPY    = 0x00000004,\n    };\n\n                            VectorImpl(size_t itemSize, uint32_t flags);\n                            VectorImpl(const VectorImpl& rhs);\n    virtual                 ~VectorImpl();\n\n    /*! must be called from subclasses destructor */\n            void            finish_vector();\n\n            VectorImpl&     operator = (const VectorImpl& rhs);    \n            \n    /*! C-style array access */\n    inline  const void*     arrayImpl() const       { return mStorage; }\n            void*           editArrayImpl();\n            \n    /*! vector stats */\n    inline  size_t          size() const        { return mCount; }\n    inline  bool            isEmpty() const     { return mCount == 0; }\n            size_t          capacity() const;\n            ssize_t         setCapacity(size_t size);\n            ssize_t         resize(size_t size);\n\n            /*! append/insert another vector or array */\n            ssize_t         insertVectorAt(const VectorImpl& vector, size_t index);\n            ssize_t         appendVector(const VectorImpl& vector);\n            ssize_t         insertArrayAt(const void* array, size_t index, size_t length);\n            ssize_t         appendArray(const void* array, size_t length);\n            \n            /*! add/insert/replace items */\n            ssize_t         insertAt(size_t where, size_t numItems = 1);\n            ssize_t         insertAt(const void* item, size_t where, size_t numItems = 1);\n            void            pop();\n            void            push();\n            void            push(const void* item);\n            ssize_t         add();\n            ssize_t         add(const void* item);\n            ssize_t         replaceAt(size_t index);\n            ssize_t         replaceAt(const void* item, size_t index);\n\n            /*! remove items */\n            ssize_t         removeItemsAt(size_t index, size_t count = 1);\n            void            clear();\n\n            const void*     itemLocation(size_t index) const;\n            void*           editItemLocation(size_t index);\n\n            typedef int (*compar_t)(const void* lhs, const void* rhs);\n            typedef int (*compar_r_t)(const void* lhs, const void* rhs, void* state);\n            status_t        sort(compar_t cmp);\n            status_t        sort(compar_r_t cmp, void* state);\n\nprotected:\n            size_t          itemSize() const;\n            void            release_storage();\n\n    virtual void            do_construct(void* storage, size_t num) const = 0;\n    virtual void            do_destroy(void* storage, size_t num) const = 0;\n    virtual void            do_copy(void* dest, const void* from, size_t num) const = 0;\n    virtual void            do_splat(void* dest, const void* item, size_t num) const = 0;\n    virtual void            do_move_forward(void* dest, const void* from, size_t num) const = 0;\n    virtual void            do_move_backward(void* dest, const void* from, size_t num) const = 0;\n    \nprivate:\n        void* _grow(size_t where, size_t amount);\n        void  _shrink(size_t where, size_t amount);\n\n        inline void _do_construct(void* storage, size_t num) const;\n        inline void _do_destroy(void* storage, size_t num) const;\n        inline void _do_copy(void* dest, const void* from, size_t num) const;\n        inline void _do_splat(void* dest, const void* item, size_t num) const;\n        inline void _do_move_forward(void* dest, const void* from, size_t num) const;\n        inline void _do_move_backward(void* dest, const void* from, size_t num) const;\n\n            // These 2 fields are exposed in the inlines below,\n            // so they're set in stone.\n            void *      mStorage;   // base address of the vector\n            size_t      mCount;     // number of items\n\n    const   uint32_t    mFlags;\n    const   size_t      mItemSize;\n};\n\n\n\nclass SortedVectorImpl : public VectorImpl\n{\npublic:\n                            SortedVectorImpl(size_t itemSize, uint32_t flags);\n                            SortedVectorImpl(const VectorImpl& rhs);\n    virtual                 ~SortedVectorImpl();\n    \n    SortedVectorImpl&     operator = (const SortedVectorImpl& rhs);    \n\n    //! finds the index of an item\n            ssize_t         indexOf(const void* item) const;\n\n    //! finds where this item should be inserted\n            size_t          orderOf(const void* item) const;\n\n    //! add an item in the right place (or replaces it if there is one)\n            ssize_t         add(const void* item);\n\n    //! merges a vector into this one\n            ssize_t         merge(const VectorImpl& vector);\n            ssize_t         merge(const SortedVectorImpl& vector);\n             \n    //! removes an item\n            ssize_t         remove(const void* item);\n        \nprotected:\n    virtual int             do_compare(const void* lhs, const void* rhs) const = 0;\n\nprivate:\n            ssize_t         _indexOrderOf(const void* item, size_t* order = 0) const;\n\n            // these are made private, because they can't be used on a SortedVector\n            // (they don't have an implementation either)\n            ssize_t         add();\n            void            pop();\n            void            push();\n            void            push(const void* item);\n            ssize_t         insertVectorAt(const VectorImpl& vector, size_t index);\n            ssize_t         appendVector(const VectorImpl& vector);\n            ssize_t         insertArrayAt(const void* array, size_t index, size_t length);\n            ssize_t         appendArray(const void* array, size_t length);\n            ssize_t         insertAt(size_t where, size_t numItems = 1);\n            ssize_t         insertAt(const void* item, size_t where, size_t numItems = 1);\n            ssize_t         replaceAt(size_t index);\n            ssize_t         replaceAt(const void* item, size_t index);\n};\n\n}; // namespace android\n\n\n// ---------------------------------------------------------------------------\n\n#endif // ANDROID_VECTOR_IMPL_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/ashmem.h",
    "content": "/* utils/ashmem.h\n **\n ** Copyright 2008 The Android Open Source Project\n **\n ** This file is dual licensed.  It may be redistributed and/or modified\n ** under the terms of the Apache 2.0 License OR version 2 of the GNU\n ** General Public License.\n */\n\n#ifndef _UTILS_ASHMEM_H\n#define _UTILS_ASHMEM_H\n\n#include <linux/limits.h>\n#include <linux/ioctl.h>\n\n#define ASHMEM_NAME_LEN\t\t256\n\n#define ASHMEM_NAME_DEF\t\t\"dev/ashmem\"\n\n/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */\n#define ASHMEM_NOT_REAPED\t0\n#define ASHMEM_WAS_REAPED\t1\n\n/* Return values from ASHMEM_UNPIN: Is the mapping now pinned or unpinned? */\n#define ASHMEM_NOW_UNPINNED\t0\n#define ASHMEM_NOW_PINNED\t1\n\n#define __ASHMEMIOC\t\t0x77\n\n#define ASHMEM_SET_NAME\t\t_IOW(__ASHMEMIOC, 1, char[ASHMEM_NAME_LEN])\n#define ASHMEM_GET_NAME\t\t_IOR(__ASHMEMIOC, 2, char[ASHMEM_NAME_LEN])\n#define ASHMEM_SET_SIZE\t\t_IOW(__ASHMEMIOC, 3, size_t)\n#define ASHMEM_GET_SIZE\t\t_IO(__ASHMEMIOC, 4)\n#define ASHMEM_SET_PROT_MASK\t_IOW(__ASHMEMIOC, 5, unsigned long)\n#define ASHMEM_GET_PROT_MASK\t_IO(__ASHMEMIOC, 6)\n#define ASHMEM_PIN\t\t_IO(__ASHMEMIOC, 7)\n#define ASHMEM_UNPIN\t\t_IO(__ASHMEMIOC, 8)\n#define ASHMEM_ISPINNED\t\t_IO(__ASHMEMIOC, 9)\n#define ASHMEM_PURGE_ALL_CACHES\t_IO(__ASHMEMIOC, 10)\n\n#endif\t/* _UTILS_ASHMEM_H */\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/misc.h",
    "content": "/*\n * Copyright (C) 2005 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n//\n// Handy utility functions and portability code.\n//\n#ifndef _LIBS_UTILS_MISC_H\n#define _LIBS_UTILS_MISC_H\n\n#include <utils/Endian.h>\n\n/* get #of elements in a static array */\n#ifndef NELEM\n# define NELEM(x) ((int) (sizeof(x) / sizeof((x)[0])))\n#endif\n\nnamespace android {\n\ntypedef void (*sysprop_change_callback)(void);\nvoid add_sysprop_change_callback(sysprop_change_callback cb, int priority);\nvoid report_sysprop_change();\n\n}; // namespace android\n\n#endif // _LIBS_UTILS_MISC_H\n"
  },
  {
    "path": "phonelibs/android_system_core/include/utils/threads.h",
    "content": "/*\n * Copyright (C) 2007 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _LIBS_UTILS_THREADS_H\n#define _LIBS_UTILS_THREADS_H\n\n/*\n * Please, DO NOT USE!\n *\n * This file is here only for legacy reasons. Instead, include directly\n * the headers you need below.\n *\n */\n\n#include <utils/AndroidThreads.h>\n\n#ifdef __cplusplus\n#include <utils/Condition.h>\n#include <utils/Errors.h>\n#include <utils/Mutex.h>\n#include <utils/RWLock.h>\n#include <utils/Thread.h>\n#endif\n\n#endif // _LIBS_UTILS_THREADS_H\n"
  },
  {
    "path": "phonelibs/bzip2/LICENSE",
    "content": "\n--------------------------------------------------------------------------\n\nThis program, \"bzip2\", the associated library \"libbzip2\", and all\ndocumentation, are copyright (C) 1996-2010 Julian R Seward.  All\nrights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions\nare met:\n\n1. Redistributions of source code must retain the above copyright\n   notice, this list of conditions and the following disclaimer.\n\n2. The origin of this software must not be misrepresented; you must \n   not claim that you wrote the original software.  If you use this \n   software in a product, an acknowledgment in the product \n   documentation would be appreciated but is not required.\n\n3. Altered source versions must be plainly marked as such, and must\n   not be misrepresented as being the original software.\n\n4. The name of the author may not be used to endorse or promote \n   products derived from this software without specific prior written \n   permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\nOR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\nDAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\nGOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\nWHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\nNEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nJulian Seward, jseward@bzip.org\nbzip2/libbzip2 version 1.0.6 of 6 September 2010\n\n--------------------------------------------------------------------------\n"
  },
  {
    "path": "phonelibs/bzip2/build.txt",
    "content": "git clone https://github.com/enthought/bzip2-1.0.6.git\ncd bzip2-1.0.6\ngit reset --hard 288acf97a15d558f96c24c89f578b724d6e06b0c\n\nmake libbz2.a\ncp libbz2.a ../\n"
  },
  {
    "path": "phonelibs/bzip2/bzlib.h",
    "content": "\n/*-------------------------------------------------------------*/\n/*--- Public header file for the library.                   ---*/\n/*---                                               bzlib.h ---*/\n/*-------------------------------------------------------------*/\n\n/* ------------------------------------------------------------------\n   This file is part of bzip2/libbzip2, a program and library for\n   lossless, block-sorting data compression.\n\n   bzip2/libbzip2 version 1.0.6 of 6 September 2010\n   Copyright (C) 1996-2010 Julian Seward <jseward@bzip.org>\n\n   Please read the WARNING, DISCLAIMER and PATENTS sections in the \n   README file.\n\n   This program is released under the terms of the license contained\n   in the file LICENSE.\n   ------------------------------------------------------------------ */\n\n\n#ifndef _BZLIB_H\n#define _BZLIB_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define BZ_RUN               0\n#define BZ_FLUSH             1\n#define BZ_FINISH            2\n\n#define BZ_OK                0\n#define BZ_RUN_OK            1\n#define BZ_FLUSH_OK          2\n#define BZ_FINISH_OK         3\n#define BZ_STREAM_END        4\n#define BZ_SEQUENCE_ERROR    (-1)\n#define BZ_PARAM_ERROR       (-2)\n#define BZ_MEM_ERROR         (-3)\n#define BZ_DATA_ERROR        (-4)\n#define BZ_DATA_ERROR_MAGIC  (-5)\n#define BZ_IO_ERROR          (-6)\n#define BZ_UNEXPECTED_EOF    (-7)\n#define BZ_OUTBUFF_FULL      (-8)\n#define BZ_CONFIG_ERROR      (-9)\n\ntypedef \n   struct {\n      char *next_in;\n      unsigned int avail_in;\n      unsigned int total_in_lo32;\n      unsigned int total_in_hi32;\n\n      char *next_out;\n      unsigned int avail_out;\n      unsigned int total_out_lo32;\n      unsigned int total_out_hi32;\n\n      void *state;\n\n      void *(*bzalloc)(void *,int,int);\n      void (*bzfree)(void *,void *);\n      void *opaque;\n   } \n   bz_stream;\n\n\n#ifndef BZ_IMPORT\n#define BZ_EXPORT\n#endif\n\n#ifndef BZ_NO_STDIO\n/* Need a definitition for FILE */\n#include <stdio.h>\n#endif\n\n#ifdef _WIN32\n#   include <windows.h>\n#   ifdef small\n      /* windows.h define small to char */\n#      undef small\n#   endif\n#   ifdef BZ_EXPORT\n#   define BZ_API(func) WINAPI func\n#   define BZ_EXTERN extern\n#   else\n   /* import windows dll dynamically */\n#   define BZ_API(func) (WINAPI * func)\n#   define BZ_EXTERN\n#   endif\n#else\n#   define BZ_API(func) func\n#   define BZ_EXTERN extern\n#endif\n\n\n/*-- Core (low-level) library functions --*/\n\nBZ_EXTERN int BZ_API(BZ2_bzCompressInit) ( \n      bz_stream* strm, \n      int        blockSize100k, \n      int        verbosity, \n      int        workFactor \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzCompress) ( \n      bz_stream* strm, \n      int action \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzCompressEnd) ( \n      bz_stream* strm \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzDecompressInit) ( \n      bz_stream *strm, \n      int       verbosity, \n      int       small\n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzDecompress) ( \n      bz_stream* strm \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) ( \n      bz_stream *strm \n   );\n\n\n\n/*-- High(er) level library functions --*/\n\n#ifndef BZ_NO_STDIO\n#define BZ_MAX_UNUSED 5000\n\ntypedef void BZFILE;\n\nBZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) ( \n      int*  bzerror,   \n      FILE* f, \n      int   verbosity, \n      int   small,\n      void* unused,    \n      int   nUnused \n   );\n\nBZ_EXTERN void BZ_API(BZ2_bzReadClose) ( \n      int*    bzerror, \n      BZFILE* b \n   );\n\nBZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) ( \n      int*    bzerror, \n      BZFILE* b, \n      void**  unused,  \n      int*    nUnused \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzRead) ( \n      int*    bzerror, \n      BZFILE* b, \n      void*   buf, \n      int     len \n   );\n\nBZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) ( \n      int*  bzerror,      \n      FILE* f, \n      int   blockSize100k, \n      int   verbosity, \n      int   workFactor \n   );\n\nBZ_EXTERN void BZ_API(BZ2_bzWrite) ( \n      int*    bzerror, \n      BZFILE* b, \n      void*   buf, \n      int     len \n   );\n\nBZ_EXTERN void BZ_API(BZ2_bzWriteClose) ( \n      int*          bzerror, \n      BZFILE*       b, \n      int           abandon, \n      unsigned int* nbytes_in, \n      unsigned int* nbytes_out \n   );\n\nBZ_EXTERN void BZ_API(BZ2_bzWriteClose64) ( \n      int*          bzerror, \n      BZFILE*       b, \n      int           abandon, \n      unsigned int* nbytes_in_lo32, \n      unsigned int* nbytes_in_hi32, \n      unsigned int* nbytes_out_lo32, \n      unsigned int* nbytes_out_hi32\n   );\n#endif\n\n\n/*-- Utility functions --*/\n\nBZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) ( \n      char*         dest, \n      unsigned int* destLen,\n      char*         source, \n      unsigned int  sourceLen,\n      int           blockSize100k, \n      int           verbosity, \n      int           workFactor \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) ( \n      char*         dest, \n      unsigned int* destLen,\n      char*         source, \n      unsigned int  sourceLen,\n      int           small, \n      int           verbosity \n   );\n\n\n/*--\n   Code contributed by Yoshioka Tsuneo (tsuneo@rr.iij4u.or.jp)\n   to support better zlib compatibility.\n   This code is not _officially_ part of libbzip2 (yet);\n   I haven't tested it, documented it, or considered the\n   threading-safeness of it.\n   If this code breaks, please contact both Yoshioka and me.\n--*/\n\nBZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (\n      void\n   );\n\n#ifndef BZ_NO_STDIO\nBZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (\n      const char *path,\n      const char *mode\n   );\n\nBZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (\n      int        fd,\n      const char *mode\n   );\n         \nBZ_EXTERN int BZ_API(BZ2_bzread) (\n      BZFILE* b, \n      void* buf, \n      int len \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzwrite) (\n      BZFILE* b, \n      void*   buf, \n      int     len \n   );\n\nBZ_EXTERN int BZ_API(BZ2_bzflush) (\n      BZFILE* b\n   );\n\nBZ_EXTERN void BZ_API(BZ2_bzclose) (\n      BZFILE* b\n   );\n\nBZ_EXTERN const char * BZ_API(BZ2_bzerror) (\n      BZFILE *b, \n      int    *errnum\n   );\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n\n/*-------------------------------------------------------------*/\n/*--- end                                           bzlib.h ---*/\n/*-------------------------------------------------------------*/\n"
  },
  {
    "path": "phonelibs/json11/json11.cpp",
    "content": "/* Copyright (c) 2013 Dropbox, Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n */\n\n#include \"json11.hpp\"\n#include <cassert>\n#include <cmath>\n#include <cstdlib>\n#include <cstdio>\n#include <limits>\n\nnamespace json11 {\n\nstatic const int max_depth = 200;\n\nusing std::string;\nusing std::vector;\nusing std::map;\nusing std::make_shared;\nusing std::initializer_list;\nusing std::move;\n\n/* Helper for representing null - just a do-nothing struct, plus comparison\n * operators so the helpers in JsonValue work. We can't use nullptr_t because\n * it may not be orderable.\n */\nstruct NullStruct {\n    bool operator==(NullStruct) const { return true; }\n    bool operator<(NullStruct) const { return false; }\n};\n\n/* * * * * * * * * * * * * * * * * * * *\n * Serialization\n */\n\nstatic void dump(NullStruct, string &out) {\n    out += \"null\";\n}\n\nstatic void dump(double value, string &out) {\n    if (std::isfinite(value)) {\n        char buf[32];\n        snprintf(buf, sizeof buf, \"%.17g\", value);\n        out += buf;\n    } else {\n        out += \"null\";\n    }\n}\n\nstatic void dump(int value, string &out) {\n    char buf[32];\n    snprintf(buf, sizeof buf, \"%d\", value);\n    out += buf;\n}\n\nstatic void dump(bool value, string &out) {\n    out += value ? \"true\" : \"false\";\n}\n\nstatic void dump(const string &value, string &out) {\n    out += '\"';\n    for (size_t i = 0; i < value.length(); i++) {\n        const char ch = value[i];\n        if (ch == '\\\\') {\n            out += \"\\\\\\\\\";\n        } else if (ch == '\"') {\n            out += \"\\\\\\\"\";\n        } else if (ch == '\\b') {\n            out += \"\\\\b\";\n        } else if (ch == '\\f') {\n            out += \"\\\\f\";\n        } else if (ch == '\\n') {\n            out += \"\\\\n\";\n        } else if (ch == '\\r') {\n            out += \"\\\\r\";\n        } else if (ch == '\\t') {\n            out += \"\\\\t\";\n        } else if (static_cast<uint8_t>(ch) <= 0x1f) {\n            char buf[8];\n            snprintf(buf, sizeof buf, \"\\\\u%04x\", ch);\n            out += buf;\n        } else if (static_cast<uint8_t>(ch) == 0xe2 && static_cast<uint8_t>(value[i+1]) == 0x80\n                   && static_cast<uint8_t>(value[i+2]) == 0xa8) {\n            out += \"\\\\u2028\";\n            i += 2;\n        } else if (static_cast<uint8_t>(ch) == 0xe2 && static_cast<uint8_t>(value[i+1]) == 0x80\n                   && static_cast<uint8_t>(value[i+2]) == 0xa9) {\n            out += \"\\\\u2029\";\n            i += 2;\n        } else {\n            out += ch;\n        }\n    }\n    out += '\"';\n}\n\nstatic void dump(const Json::array &values, string &out) {\n    bool first = true;\n    out += \"[\";\n    for (const auto &value : values) {\n        if (!first)\n            out += \", \";\n        value.dump(out);\n        first = false;\n    }\n    out += \"]\";\n}\n\nstatic void dump(const Json::object &values, string &out) {\n    bool first = true;\n    out += \"{\";\n    for (const auto &kv : values) {\n        if (!first)\n            out += \", \";\n        dump(kv.first, out);\n        out += \": \";\n        kv.second.dump(out);\n        first = false;\n    }\n    out += \"}\";\n}\n\nvoid Json::dump(string &out) const {\n    m_ptr->dump(out);\n}\n\n/* * * * * * * * * * * * * * * * * * * *\n * Value wrappers\n */\n\ntemplate <Json::Type tag, typename T>\nclass Value : public JsonValue {\nprotected:\n\n    // Constructors\n    explicit Value(const T &value) : m_value(value) {}\n    explicit Value(T &&value)      : m_value(move(value)) {}\n\n    // Get type tag\n    Json::Type type() const override {\n        return tag;\n    }\n\n    // Comparisons\n    bool equals(const JsonValue * other) const override {\n        return m_value == static_cast<const Value<tag, T> *>(other)->m_value;\n    }\n    bool less(const JsonValue * other) const override {\n        return m_value < static_cast<const Value<tag, T> *>(other)->m_value;\n    }\n\n    const T m_value;\n    void dump(string &out) const override { json11::dump(m_value, out); }\n};\n\nclass JsonDouble final : public Value<Json::NUMBER, double> {\n    double number_value() const override { return m_value; }\n    int int_value() const override { return static_cast<int>(m_value); }\n    bool equals(const JsonValue * other) const override { return m_value == other->number_value(); }\n    bool less(const JsonValue * other)   const override { return m_value <  other->number_value(); }\npublic:\n    explicit JsonDouble(double value) : Value(value) {}\n};\n\nclass JsonInt final : public Value<Json::NUMBER, int> {\n    double number_value() const override { return m_value; }\n    int int_value() const override { return m_value; }\n    bool equals(const JsonValue * other) const override { return m_value == other->number_value(); }\n    bool less(const JsonValue * other)   const override { return m_value <  other->number_value(); }\npublic:\n    explicit JsonInt(int value) : Value(value) {}\n};\n\nclass JsonBoolean final : public Value<Json::BOOL, bool> {\n    bool bool_value() const override { return m_value; }\npublic:\n    explicit JsonBoolean(bool value) : Value(value) {}\n};\n\nclass JsonString final : public Value<Json::STRING, string> {\n    const string &string_value() const override { return m_value; }\npublic:\n    explicit JsonString(const string &value) : Value(value) {}\n    explicit JsonString(string &&value)      : Value(move(value)) {}\n};\n\nclass JsonArray final : public Value<Json::ARRAY, Json::array> {\n    const Json::array &array_items() const override { return m_value; }\n    const Json & operator[](size_t i) const override;\npublic:\n    explicit JsonArray(const Json::array &value) : Value(value) {}\n    explicit JsonArray(Json::array &&value)      : Value(move(value)) {}\n};\n\nclass JsonObject final : public Value<Json::OBJECT, Json::object> {\n    const Json::object &object_items() const override { return m_value; }\n    const Json & operator[](const string &key) const override;\npublic:\n    explicit JsonObject(const Json::object &value) : Value(value) {}\n    explicit JsonObject(Json::object &&value)      : Value(move(value)) {}\n};\n\nclass JsonNull final : public Value<Json::NUL, NullStruct> {\npublic:\n    JsonNull() : Value({}) {}\n};\n\n/* * * * * * * * * * * * * * * * * * * *\n * Static globals - static-init-safe\n */\nstruct Statics {\n    const std::shared_ptr<JsonValue> null = make_shared<JsonNull>();\n    const std::shared_ptr<JsonValue> t = make_shared<JsonBoolean>(true);\n    const std::shared_ptr<JsonValue> f = make_shared<JsonBoolean>(false);\n    const string empty_string;\n    const vector<Json> empty_vector;\n    const map<string, Json> empty_map;\n    Statics() {}\n};\n\nstatic const Statics & statics() {\n    static const Statics s {};\n    return s;\n}\n\nstatic const Json & static_null() {\n    // This has to be separate, not in Statics, because Json() accesses statics().null.\n    static const Json json_null;\n    return json_null;\n}\n\n/* * * * * * * * * * * * * * * * * * * *\n * Constructors\n */\n\nJson::Json() noexcept                  : m_ptr(statics().null) {}\nJson::Json(std::nullptr_t) noexcept    : m_ptr(statics().null) {}\nJson::Json(double value)               : m_ptr(make_shared<JsonDouble>(value)) {}\nJson::Json(int value)                  : m_ptr(make_shared<JsonInt>(value)) {}\nJson::Json(bool value)                 : m_ptr(value ? statics().t : statics().f) {}\nJson::Json(const string &value)        : m_ptr(make_shared<JsonString>(value)) {}\nJson::Json(string &&value)             : m_ptr(make_shared<JsonString>(move(value))) {}\nJson::Json(const char * value)         : m_ptr(make_shared<JsonString>(value)) {}\nJson::Json(const Json::array &values)  : m_ptr(make_shared<JsonArray>(values)) {}\nJson::Json(Json::array &&values)       : m_ptr(make_shared<JsonArray>(move(values))) {}\nJson::Json(const Json::object &values) : m_ptr(make_shared<JsonObject>(values)) {}\nJson::Json(Json::object &&values)      : m_ptr(make_shared<JsonObject>(move(values))) {}\n\n/* * * * * * * * * * * * * * * * * * * *\n * Accessors\n */\n\nJson::Type Json::type()                           const { return m_ptr->type();         }\ndouble Json::number_value()                       const { return m_ptr->number_value(); }\nint Json::int_value()                             const { return m_ptr->int_value();    }\nbool Json::bool_value()                           const { return m_ptr->bool_value();   }\nconst string & Json::string_value()               const { return m_ptr->string_value(); }\nconst vector<Json> & Json::array_items()          const { return m_ptr->array_items();  }\nconst map<string, Json> & Json::object_items()    const { return m_ptr->object_items(); }\nconst Json & Json::operator[] (size_t i)          const { return (*m_ptr)[i];           }\nconst Json & Json::operator[] (const string &key) const { return (*m_ptr)[key];         }\n\ndouble                    JsonValue::number_value()              const { return 0; }\nint                       JsonValue::int_value()                 const { return 0; }\nbool                      JsonValue::bool_value()                const { return false; }\nconst string &            JsonValue::string_value()              const { return statics().empty_string; }\nconst vector<Json> &      JsonValue::array_items()               const { return statics().empty_vector; }\nconst map<string, Json> & JsonValue::object_items()              const { return statics().empty_map; }\nconst Json &              JsonValue::operator[] (size_t)         const { return static_null(); }\nconst Json &              JsonValue::operator[] (const string &) const { return static_null(); }\n\nconst Json & JsonObject::operator[] (const string &key) const {\n    auto iter = m_value.find(key);\n    return (iter == m_value.end()) ? static_null() : iter->second;\n}\nconst Json & JsonArray::operator[] (size_t i) const {\n    if (i >= m_value.size()) return static_null();\n    else return m_value[i];\n}\n\n/* * * * * * * * * * * * * * * * * * * *\n * Comparison\n */\n\nbool Json::operator== (const Json &other) const {\n    if (m_ptr->type() != other.m_ptr->type())\n        return false;\n\n    return m_ptr->equals(other.m_ptr.get());\n}\n\nbool Json::operator< (const Json &other) const {\n    if (m_ptr->type() != other.m_ptr->type())\n        return m_ptr->type() < other.m_ptr->type();\n\n    return m_ptr->less(other.m_ptr.get());\n}\n\n/* * * * * * * * * * * * * * * * * * * *\n * Parsing\n */\n\n/* esc(c)\n *\n * Format char c suitable for printing in an error message.\n */\nstatic inline string esc(char c) {\n    char buf[12];\n    if (static_cast<uint8_t>(c) >= 0x20 && static_cast<uint8_t>(c) <= 0x7f) {\n        snprintf(buf, sizeof buf, \"'%c' (%d)\", c, c);\n    } else {\n        snprintf(buf, sizeof buf, \"(%d)\", c);\n    }\n    return string(buf);\n}\n\nstatic inline bool in_range(long x, long lower, long upper) {\n    return (x >= lower && x <= upper);\n}\n\nnamespace {\n/* JsonParser\n *\n * Object that tracks all state of an in-progress parse.\n */\nstruct JsonParser final {\n\n    /* State\n     */\n    const string &str;\n    size_t i;\n    string &err;\n    bool failed;\n    const JsonParse strategy;\n\n    /* fail(msg, err_ret = Json())\n     *\n     * Mark this parse as failed.\n     */\n    Json fail(string &&msg) {\n        return fail(move(msg), Json());\n    }\n\n    template <typename T>\n    T fail(string &&msg, const T err_ret) {\n        if (!failed)\n            err = std::move(msg);\n        failed = true;\n        return err_ret;\n    }\n\n    /* consume_whitespace()\n     *\n     * Advance until the current character is non-whitespace.\n     */\n    void consume_whitespace() {\n        while (str[i] == ' ' || str[i] == '\\r' || str[i] == '\\n' || str[i] == '\\t')\n            i++;\n    }\n\n    /* consume_comment()\n     *\n     * Advance comments (c-style inline and multiline).\n     */\n    bool consume_comment() {\n      bool comment_found = false;\n      if (str[i] == '/') {\n        i++;\n        if (i == str.size())\n          return fail(\"unexpected end of input after start of comment\", false);\n        if (str[i] == '/') { // inline comment\n          i++;\n          // advance until next line, or end of input\n          while (i < str.size() && str[i] != '\\n') {\n            i++;\n          }\n          comment_found = true;\n        }\n        else if (str[i] == '*') { // multiline comment\n          i++;\n          if (i > str.size()-2)\n            return fail(\"unexpected end of input inside multi-line comment\", false);\n          // advance until closing tokens\n          while (!(str[i] == '*' && str[i+1] == '/')) {\n            i++;\n            if (i > str.size()-2)\n              return fail(\n                \"unexpected end of input inside multi-line comment\", false);\n          }\n          i += 2;\n          comment_found = true;\n        }\n        else\n          return fail(\"malformed comment\", false);\n      }\n      return comment_found;\n    }\n\n    /* consume_garbage()\n     *\n     * Advance until the current character is non-whitespace and non-comment.\n     */\n    void consume_garbage() {\n      consume_whitespace();\n      if(strategy == JsonParse::COMMENTS) {\n        bool comment_found = false;\n        do {\n          comment_found = consume_comment();\n          if (failed) return;\n          consume_whitespace();\n        }\n        while(comment_found);\n      }\n    }\n\n    /* get_next_token()\n     *\n     * Return the next non-whitespace character. If the end of the input is reached,\n     * flag an error and return 0.\n     */\n    char get_next_token() {\n        consume_garbage();\n        if (failed) return (char)0;\n        if (i == str.size())\n            return fail(\"unexpected end of input\", (char)0);\n\n        return str[i++];\n    }\n\n    /* encode_utf8(pt, out)\n     *\n     * Encode pt as UTF-8 and add it to out.\n     */\n    void encode_utf8(long pt, string & out) {\n        if (pt < 0)\n            return;\n\n        if (pt < 0x80) {\n            out += static_cast<char>(pt);\n        } else if (pt < 0x800) {\n            out += static_cast<char>((pt >> 6) | 0xC0);\n            out += static_cast<char>((pt & 0x3F) | 0x80);\n        } else if (pt < 0x10000) {\n            out += static_cast<char>((pt >> 12) | 0xE0);\n            out += static_cast<char>(((pt >> 6) & 0x3F) | 0x80);\n            out += static_cast<char>((pt & 0x3F) | 0x80);\n        } else {\n            out += static_cast<char>((pt >> 18) | 0xF0);\n            out += static_cast<char>(((pt >> 12) & 0x3F) | 0x80);\n            out += static_cast<char>(((pt >> 6) & 0x3F) | 0x80);\n            out += static_cast<char>((pt & 0x3F) | 0x80);\n        }\n    }\n\n    /* parse_string()\n     *\n     * Parse a string, starting at the current position.\n     */\n    string parse_string() {\n        string out;\n        long last_escaped_codepoint = -1;\n        while (true) {\n            if (i == str.size())\n                return fail(\"unexpected end of input in string\", \"\");\n\n            char ch = str[i++];\n\n            if (ch == '\"') {\n                encode_utf8(last_escaped_codepoint, out);\n                return out;\n            }\n\n            if (in_range(ch, 0, 0x1f))\n                return fail(\"unescaped \" + esc(ch) + \" in string\", \"\");\n\n            // The usual case: non-escaped characters\n            if (ch != '\\\\') {\n                encode_utf8(last_escaped_codepoint, out);\n                last_escaped_codepoint = -1;\n                out += ch;\n                continue;\n            }\n\n            // Handle escapes\n            if (i == str.size())\n                return fail(\"unexpected end of input in string\", \"\");\n\n            ch = str[i++];\n\n            if (ch == 'u') {\n                // Extract 4-byte escape sequence\n                string esc = str.substr(i, 4);\n                // Explicitly check length of the substring. The following loop\n                // relies on std::string returning the terminating NUL when\n                // accessing str[length]. Checking here reduces brittleness.\n                if (esc.length() < 4) {\n                    return fail(\"bad \\\\u escape: \" + esc, \"\");\n                }\n                for (size_t j = 0; j < 4; j++) {\n                    if (!in_range(esc[j], 'a', 'f') && !in_range(esc[j], 'A', 'F')\n                            && !in_range(esc[j], '0', '9'))\n                        return fail(\"bad \\\\u escape: \" + esc, \"\");\n                }\n\n                long codepoint = strtol(esc.data(), nullptr, 16);\n\n                // JSON specifies that characters outside the BMP shall be encoded as a pair\n                // of 4-hex-digit \\u escapes encoding their surrogate pair components. Check\n                // whether we're in the middle of such a beast: the previous codepoint was an\n                // escaped lead (high) surrogate, and this is a trail (low) surrogate.\n                if (in_range(last_escaped_codepoint, 0xD800, 0xDBFF)\n                        && in_range(codepoint, 0xDC00, 0xDFFF)) {\n                    // Reassemble the two surrogate pairs into one astral-plane character, per\n                    // the UTF-16 algorithm.\n                    encode_utf8((((last_escaped_codepoint - 0xD800) << 10)\n                                 | (codepoint - 0xDC00)) + 0x10000, out);\n                    last_escaped_codepoint = -1;\n                } else {\n                    encode_utf8(last_escaped_codepoint, out);\n                    last_escaped_codepoint = codepoint;\n                }\n\n                i += 4;\n                continue;\n            }\n\n            encode_utf8(last_escaped_codepoint, out);\n            last_escaped_codepoint = -1;\n\n            if (ch == 'b') {\n                out += '\\b';\n            } else if (ch == 'f') {\n                out += '\\f';\n            } else if (ch == 'n') {\n                out += '\\n';\n            } else if (ch == 'r') {\n                out += '\\r';\n            } else if (ch == 't') {\n                out += '\\t';\n            } else if (ch == '\"' || ch == '\\\\' || ch == '/') {\n                out += ch;\n            } else {\n                return fail(\"invalid escape character \" + esc(ch), \"\");\n            }\n        }\n    }\n\n    /* parse_number()\n     *\n     * Parse a double.\n     */\n    Json parse_number() {\n        size_t start_pos = i;\n\n        if (str[i] == '-')\n            i++;\n\n        // Integer part\n        if (str[i] == '0') {\n            i++;\n            if (in_range(str[i], '0', '9'))\n                return fail(\"leading 0s not permitted in numbers\");\n        } else if (in_range(str[i], '1', '9')) {\n            i++;\n            while (in_range(str[i], '0', '9'))\n                i++;\n        } else {\n            return fail(\"invalid \" + esc(str[i]) + \" in number\");\n        }\n\n        if (str[i] != '.' && str[i] != 'e' && str[i] != 'E'\n                && (i - start_pos) <= static_cast<size_t>(std::numeric_limits<int>::digits10)) {\n            return std::atoi(str.c_str() + start_pos);\n        }\n\n        // Decimal part\n        if (str[i] == '.') {\n            i++;\n            if (!in_range(str[i], '0', '9'))\n                return fail(\"at least one digit required in fractional part\");\n\n            while (in_range(str[i], '0', '9'))\n                i++;\n        }\n\n        // Exponent part\n        if (str[i] == 'e' || str[i] == 'E') {\n            i++;\n\n            if (str[i] == '+' || str[i] == '-')\n                i++;\n\n            if (!in_range(str[i], '0', '9'))\n                return fail(\"at least one digit required in exponent\");\n\n            while (in_range(str[i], '0', '9'))\n                i++;\n        }\n\n        return std::strtod(str.c_str() + start_pos, nullptr);\n    }\n\n    /* expect(str, res)\n     *\n     * Expect that 'str' starts at the character that was just read. If it does, advance\n     * the input and return res. If not, flag an error.\n     */\n    Json expect(const string &expected, Json res) {\n        assert(i != 0);\n        i--;\n        if (str.compare(i, expected.length(), expected) == 0) {\n            i += expected.length();\n            return res;\n        } else {\n            return fail(\"parse error: expected \" + expected + \", got \" + str.substr(i, expected.length()));\n        }\n    }\n\n    /* parse_json()\n     *\n     * Parse a JSON object.\n     */\n    Json parse_json(int depth) {\n        if (depth > max_depth) {\n            return fail(\"exceeded maximum nesting depth\");\n        }\n\n        char ch = get_next_token();\n        if (failed)\n            return Json();\n\n        if (ch == '-' || (ch >= '0' && ch <= '9')) {\n            i--;\n            return parse_number();\n        }\n\n        if (ch == 't')\n            return expect(\"true\", true);\n\n        if (ch == 'f')\n            return expect(\"false\", false);\n\n        if (ch == 'n')\n            return expect(\"null\", Json());\n\n        if (ch == '\"')\n            return parse_string();\n\n        if (ch == '{') {\n            map<string, Json> data;\n            ch = get_next_token();\n            if (ch == '}')\n                return data;\n\n            while (1) {\n                if (ch != '\"')\n                    return fail(\"expected '\\\"' in object, got \" + esc(ch));\n\n                string key = parse_string();\n                if (failed)\n                    return Json();\n\n                ch = get_next_token();\n                if (ch != ':')\n                    return fail(\"expected ':' in object, got \" + esc(ch));\n\n                data[std::move(key)] = parse_json(depth + 1);\n                if (failed)\n                    return Json();\n\n                ch = get_next_token();\n                if (ch == '}')\n                    break;\n                if (ch != ',')\n                    return fail(\"expected ',' in object, got \" + esc(ch));\n\n                ch = get_next_token();\n            }\n            return data;\n        }\n\n        if (ch == '[') {\n            vector<Json> data;\n            ch = get_next_token();\n            if (ch == ']')\n                return data;\n\n            while (1) {\n                i--;\n                data.push_back(parse_json(depth + 1));\n                if (failed)\n                    return Json();\n\n                ch = get_next_token();\n                if (ch == ']')\n                    break;\n                if (ch != ',')\n                    return fail(\"expected ',' in list, got \" + esc(ch));\n\n                ch = get_next_token();\n                (void)ch;\n            }\n            return data;\n        }\n\n        return fail(\"expected value, got \" + esc(ch));\n    }\n};\n}//namespace {\n\nJson Json::parse(const string &in, string &err, JsonParse strategy) {\n    JsonParser parser { in, 0, err, false, strategy };\n    Json result = parser.parse_json(0);\n\n    // Check for any trailing garbage\n    parser.consume_garbage();\n    if (parser.failed)\n        return Json();\n    if (parser.i != in.size())\n        return parser.fail(\"unexpected trailing \" + esc(in[parser.i]));\n\n    return result;\n}\n\n// Documented in json11.hpp\nvector<Json> Json::parse_multi(const string &in,\n                               std::string::size_type &parser_stop_pos,\n                               string &err,\n                               JsonParse strategy) {\n    JsonParser parser { in, 0, err, false, strategy };\n    parser_stop_pos = 0;\n    vector<Json> json_vec;\n    while (parser.i != in.size() && !parser.failed) {\n        json_vec.push_back(parser.parse_json(0));\n        if (parser.failed)\n            break;\n\n        // Check for another object\n        parser.consume_garbage();\n        if (parser.failed)\n            break;\n        parser_stop_pos = parser.i;\n    }\n    return json_vec;\n}\n\n/* * * * * * * * * * * * * * * * * * * *\n * Shape-checking\n */\n\nbool Json::has_shape(const shape & types, string & err) const {\n    if (!is_object()) {\n        err = \"expected JSON object, got \" + dump();\n        return false;\n    }\n\n    for (auto & item : types) {\n        if ((*this)[item.first].type() != item.second) {\n            err = \"bad type for \" + item.first + \" in \" + dump();\n            return false;\n        }\n    }\n\n    return true;\n}\n\n} // namespace json11\n"
  },
  {
    "path": "phonelibs/json11/json11.hpp",
    "content": "/* json11\n *\n * json11 is a tiny JSON library for C++11, providing JSON parsing and serialization.\n *\n * The core object provided by the library is json11::Json. A Json object represents any JSON\n * value: null, bool, number (int or double), string (std::string), array (std::vector), or\n * object (std::map).\n *\n * Json objects act like values: they can be assigned, copied, moved, compared for equality or\n * order, etc. There are also helper methods Json::dump, to serialize a Json to a string, and\n * Json::parse (static) to parse a std::string as a Json object.\n *\n * Internally, the various types of Json object are represented by the JsonValue class\n * hierarchy.\n *\n * A note on numbers - JSON specifies the syntax of number formatting but not its semantics,\n * so some JSON implementations distinguish between integers and floating-point numbers, while\n * some don't. In json11, we choose the latter. Because some JSON implementations (namely\n * Javascript itself) treat all numbers as the same type, distinguishing the two leads\n * to JSON that will be *silently* changed by a round-trip through those implementations.\n * Dangerous! To avoid that risk, json11 stores all numbers as double internally, but also\n * provides integer helpers.\n *\n * Fortunately, double-precision IEEE754 ('double') can precisely store any integer in the\n * range +/-2^53, which includes every 'int' on most systems. (Timestamps often use int64\n * or long long to avoid the Y2038K problem; a double storing microseconds since some epoch\n * will be exact for +/- 275 years.)\n */\n\n/* Copyright (c) 2013 Dropbox, Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n */\n\n#pragma once\n\n#include <string>\n#include <vector>\n#include <map>\n#include <memory>\n#include <initializer_list>\n\n#ifdef _MSC_VER\n    #if _MSC_VER <= 1800 // VS 2013\n        #ifndef noexcept\n            #define noexcept throw()\n        #endif\n\n        #ifndef snprintf\n            #define snprintf _snprintf_s\n        #endif\n    #endif\n#endif\n\nnamespace json11 {\n\nenum JsonParse {\n    STANDARD, COMMENTS\n};\n\nclass JsonValue;\n\nclass Json final {\npublic:\n    // Types\n    enum Type {\n        NUL, NUMBER, BOOL, STRING, ARRAY, OBJECT\n    };\n\n    // Array and object typedefs\n    typedef std::vector<Json> array;\n    typedef std::map<std::string, Json> object;\n\n    // Constructors for the various types of JSON value.\n    Json() noexcept;                // NUL\n    Json(std::nullptr_t) noexcept;  // NUL\n    Json(double value);             // NUMBER\n    Json(int value);                // NUMBER\n    Json(bool value);               // BOOL\n    Json(const std::string &value); // STRING\n    Json(std::string &&value);      // STRING\n    Json(const char * value);       // STRING\n    Json(const array &values);      // ARRAY\n    Json(array &&values);           // ARRAY\n    Json(const object &values);     // OBJECT\n    Json(object &&values);          // OBJECT\n\n    // Implicit constructor: anything with a to_json() function.\n    template <class T, class = decltype(&T::to_json)>\n    Json(const T & t) : Json(t.to_json()) {}\n\n    // Implicit constructor: map-like objects (std::map, std::unordered_map, etc)\n    template <class M, typename std::enable_if<\n        std::is_constructible<std::string, typename M::key_type>::value\n        && std::is_constructible<Json, typename M::mapped_type>::value,\n            int>::type = 0>\n    Json(const M & m) : Json(object(m.begin(), m.end())) {}\n\n    // Implicit constructor: vector-like objects (std::list, std::vector, std::set, etc)\n    template <class V, typename std::enable_if<\n        std::is_constructible<Json, typename V::value_type>::value,\n            int>::type = 0>\n    Json(const V & v) : Json(array(v.begin(), v.end())) {}\n\n    // This prevents Json(some_pointer) from accidentally producing a bool. Use\n    // Json(bool(some_pointer)) if that behavior is desired.\n    Json(void *) = delete;\n\n    // Accessors\n    Type type() const;\n\n    bool is_null()   const { return type() == NUL; }\n    bool is_number() const { return type() == NUMBER; }\n    bool is_bool()   const { return type() == BOOL; }\n    bool is_string() const { return type() == STRING; }\n    bool is_array()  const { return type() == ARRAY; }\n    bool is_object() const { return type() == OBJECT; }\n\n    // Return the enclosed value if this is a number, 0 otherwise. Note that json11 does not\n    // distinguish between integer and non-integer numbers - number_value() and int_value()\n    // can both be applied to a NUMBER-typed object.\n    double number_value() const;\n    int int_value() const;\n\n    // Return the enclosed value if this is a boolean, false otherwise.\n    bool bool_value() const;\n    // Return the enclosed string if this is a string, \"\" otherwise.\n    const std::string &string_value() const;\n    // Return the enclosed std::vector if this is an array, or an empty vector otherwise.\n    const array &array_items() const;\n    // Return the enclosed std::map if this is an object, or an empty map otherwise.\n    const object &object_items() const;\n\n    // Return a reference to arr[i] if this is an array, Json() otherwise.\n    const Json & operator[](size_t i) const;\n    // Return a reference to obj[key] if this is an object, Json() otherwise.\n    const Json & operator[](const std::string &key) const;\n\n    // Serialize.\n    void dump(std::string &out) const;\n    std::string dump() const {\n        std::string out;\n        dump(out);\n        return out;\n    }\n\n    // Parse. If parse fails, return Json() and assign an error message to err.\n    static Json parse(const std::string & in,\n                      std::string & err,\n                      JsonParse strategy = JsonParse::STANDARD);\n    static Json parse(const char * in,\n                      std::string & err,\n                      JsonParse strategy = JsonParse::STANDARD) {\n        if (in) {\n            return parse(std::string(in), err, strategy);\n        } else {\n            err = \"null input\";\n            return nullptr;\n        }\n    }\n    // Parse multiple objects, concatenated or separated by whitespace\n    static std::vector<Json> parse_multi(\n        const std::string & in,\n        std::string::size_type & parser_stop_pos,\n        std::string & err,\n        JsonParse strategy = JsonParse::STANDARD);\n\n    static inline std::vector<Json> parse_multi(\n        const std::string & in,\n        std::string & err,\n        JsonParse strategy = JsonParse::STANDARD) {\n        std::string::size_type parser_stop_pos;\n        return parse_multi(in, parser_stop_pos, err, strategy);\n    }\n\n    bool operator== (const Json &rhs) const;\n    bool operator<  (const Json &rhs) const;\n    bool operator!= (const Json &rhs) const { return !(*this == rhs); }\n    bool operator<= (const Json &rhs) const { return !(rhs < *this); }\n    bool operator>  (const Json &rhs) const { return  (rhs < *this); }\n    bool operator>= (const Json &rhs) const { return !(*this < rhs); }\n\n    /* has_shape(types, err)\n     *\n     * Return true if this is a JSON object and, for each item in types, has a field of\n     * the given type. If not, return false and set err to a descriptive message.\n     */\n    typedef std::initializer_list<std::pair<std::string, Type>> shape;\n    bool has_shape(const shape & types, std::string & err) const;\n\nprivate:\n    std::shared_ptr<JsonValue> m_ptr;\n};\n\n// Internal class hierarchy - JsonValue objects are not exposed to users of this API.\nclass JsonValue {\nprotected:\n    friend class Json;\n    friend class JsonInt;\n    friend class JsonDouble;\n    virtual Json::Type type() const = 0;\n    virtual bool equals(const JsonValue * other) const = 0;\n    virtual bool less(const JsonValue * other) const = 0;\n    virtual void dump(std::string &out) const = 0;\n    virtual double number_value() const;\n    virtual int int_value() const;\n    virtual bool bool_value() const;\n    virtual const std::string &string_value() const;\n    virtual const Json::array &array_items() const;\n    virtual const Json &operator[](size_t i) const;\n    virtual const Json::object &object_items() const;\n    virtual const Json &operator[](const std::string &key) const;\n    virtual ~JsonValue() {}\n};\n\n} // namespace json11\n"
  },
  {
    "path": "phonelibs/kaitai/custom_decoder.h",
    "content": "#ifndef KAITAI_CUSTOM_DECODER_H\n#define KAITAI_CUSTOM_DECODER_H\n\n#include <string>\n\nnamespace kaitai {\n\nclass custom_decoder {\npublic:\n    virtual ~custom_decoder() {};\n    virtual std::string decode(std::string src) = 0;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/kaitai/exceptions.h",
    "content": "#ifndef KAITAI_EXCEPTIONS_H\n#define KAITAI_EXCEPTIONS_H\n\n#include <kaitai/kaitaistream.h>\n\n#include <string>\n#include <stdexcept>\n\n// We need to use \"noexcept\" in virtual destructor of our exceptions\n// subclasses. Different compilers have different ideas on how to\n// achieve that: C++98 compilers prefer `throw()`, C++11 and later\n// use `noexcept`. We define KS_NOEXCEPT macro for that.\n\n#if __cplusplus >= 201103L || (defined(_MSC_VER) && _MSC_VER >= 1900)\n#define KS_NOEXCEPT noexcept\n#else\n#define KS_NOEXCEPT throw()\n#endif\n\nnamespace kaitai {\n\n/**\n * Common ancestor for all error originating from Kaitai Struct usage.\n * Stores KSY source path, pointing to an element supposedly guilty of\n * an error.\n */\nclass kstruct_error: public std::runtime_error {\npublic:\n    kstruct_error(const std::string what, const std::string src_path):\n        std::runtime_error(src_path + \": \" + what),\n        m_src_path(src_path)\n    {\n    }\n\n    virtual ~kstruct_error() KS_NOEXCEPT {};\n\nprotected:\n    const std::string m_src_path;\n};\n\n/**\n * Error that occurs when default endianness should be decided with\n * a switch, but nothing matches (although using endianness expression\n * implies that there should be some positive result).\n */\nclass undecided_endianness_error: public kstruct_error {\npublic:\n    undecided_endianness_error(const std::string src_path):\n        kstruct_error(\"unable to decide on endianness for a type\", src_path)\n    {\n    }\n\n    virtual ~undecided_endianness_error() KS_NOEXCEPT {};\n};\n\n/**\n * Common ancestor for all validation failures. Stores pointer to\n * KaitaiStream IO object which was involved in an error.\n */\nclass validation_failed_error: public kstruct_error {\npublic:\n    validation_failed_error(const std::string what, kstream* io, const std::string src_path):\n        kstruct_error(\"at pos \" + kstream::to_string(static_cast<int>(io->pos())) + \": validation failed: \" + what, src_path),\n        m_io(io)\n    {\n    }\n\n// \"at pos #{io.pos}: validation failed: #{msg}\"\n\n    virtual ~validation_failed_error() KS_NOEXCEPT {};\n\nprotected:\n    kstream* m_io;\n};\n\n/**\n * Signals validation failure: we required \"actual\" value to be equal to\n * \"expected\", but it turned out that it's not.\n */\ntemplate<typename T>\nclass validation_not_equal_error: public validation_failed_error {\npublic:\n    validation_not_equal_error<T>(const T& expected, const T& actual, kstream* io, const std::string src_path):\n        validation_failed_error(\"not equal\", io, src_path),\n        m_expected(expected),\n        m_actual(actual)\n    {\n    }\n\n    // \"not equal, expected #{expected.inspect}, but got #{actual.inspect}\"\n\n    virtual ~validation_not_equal_error<T>() KS_NOEXCEPT {};\n\nprotected:\n    const T& m_expected;\n    const T& m_actual;\n};\n\n/**\n * Signals validation failure: we required \"actual\" value to be greater\n * than or equal to \"min\", but it turned out that it's not.\n */\ntemplate<typename T>\nclass validation_less_than_error: public validation_failed_error {\npublic:\n    validation_less_than_error<T>(const T& min, const T& actual, kstream* io, const std::string src_path):\n        validation_failed_error(\"not in range\", io, src_path),\n        m_min(min),\n        m_actual(actual)\n    {\n    }\n\n    // \"not in range, min #{min.inspect}, but got #{actual.inspect}\"\n\n    virtual ~validation_less_than_error<T>() KS_NOEXCEPT {};\n\nprotected:\n    const T& m_min;\n    const T& m_actual;\n};\n\n/**\n * Signals validation failure: we required \"actual\" value to be less\n * than or equal to \"max\", but it turned out that it's not.\n */\ntemplate<typename T>\nclass validation_greater_than_error: public validation_failed_error {\npublic:\n    validation_greater_than_error<T>(const T& max, const T& actual, kstream* io, const std::string src_path):\n        validation_failed_error(\"not in range\", io, src_path),\n        m_max(max),\n        m_actual(actual)\n    {\n    }\n\n    // \"not in range, max #{max.inspect}, but got #{actual.inspect}\"\n\n    virtual ~validation_greater_than_error<T>() KS_NOEXCEPT {};\n\nprotected:\n    const T& m_max;\n    const T& m_actual;\n};\n\n/**\n * Signals validation failure: we required \"actual\" value to be from\n * the list, but it turned out that it's not.\n */\ntemplate<typename T>\nclass validation_not_any_of_error: public validation_failed_error {\npublic:\n    validation_not_any_of_error<T>(const T& actual, kstream* io, const std::string src_path):\n        validation_failed_error(\"not any of the list\", io, src_path),\n        m_actual(actual)\n    {\n    }\n\n    // \"not any of the list, got #{actual.inspect}\"\n\n    virtual ~validation_not_any_of_error<T>() KS_NOEXCEPT {};\n\nprotected:\n    const T& m_actual;\n};\n\n/**\n * Signals validation failure: we required \"actual\" value to match\n * the expression, but it turned out that it doesn't.\n */\ntemplate<typename T>\nclass validation_expr_error: public validation_failed_error {\npublic:\n    validation_expr_error<T>(const T& actual, kstream* io, const std::string src_path):\n        validation_failed_error(\"not matching the expression\", io, src_path),\n        m_actual(actual)\n    {\n    }\n\n    // \"not matching the expression, got #{actual.inspect}\"\n\n    virtual ~validation_expr_error<T>() KS_NOEXCEPT {};\n\nprotected:\n    const T& m_actual;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/kaitai/kaitaistream.cpp",
    "content": "#include <kaitai/kaitaistream.h>\n\n#if defined(__APPLE__)\n#include <machine/endian.h>\n#include <libkern/OSByteOrder.h>\n#define bswap_16(x) OSSwapInt16(x)\n#define bswap_32(x) OSSwapInt32(x)\n#define bswap_64(x) OSSwapInt64(x)\n#define __BYTE_ORDER    BYTE_ORDER\n#define __BIG_ENDIAN    BIG_ENDIAN\n#define __LITTLE_ENDIAN LITTLE_ENDIAN\n#elif defined(_MSC_VER) // !__APPLE__\n#include <stdlib.h>\n#define __LITTLE_ENDIAN     1234\n#define __BIG_ENDIAN        4321\n#define __BYTE_ORDER        __LITTLE_ENDIAN\n#define bswap_16(x) _byteswap_ushort(x)\n#define bswap_32(x) _byteswap_ulong(x)\n#define bswap_64(x) _byteswap_uint64(x)\n#else // !__APPLE__ or !_MSC_VER\n#include <endian.h>\n#include <byteswap.h>\n#endif\n\n#include <iostream>\n#include <vector>\n#include <stdexcept>\n\nkaitai::kstream::kstream(std::istream* io) {\n    m_io = io;\n    init();\n}\n\nkaitai::kstream::kstream(std::string& data): m_io_str(data) {\n    m_io = &m_io_str;\n    init();\n}\n\nvoid kaitai::kstream::init() {\n    exceptions_enable();\n    align_to_byte();\n}\n\nvoid kaitai::kstream::close() {\n    //  m_io->close();\n}\n\nvoid kaitai::kstream::exceptions_enable() const {\n    m_io->exceptions(\n        std::istream::eofbit |\n        std::istream::failbit |\n        std::istream::badbit\n    );\n}\n\n// ========================================================================\n// Stream positioning\n// ========================================================================\n\nbool kaitai::kstream::is_eof() const {\n    if (m_bits_left > 0) {\n        return false;\n    }\n    char t;\n    m_io->exceptions(\n        std::istream::badbit\n    );\n    m_io->get(t);\n    if (m_io->eof()) {\n        m_io->clear();\n        exceptions_enable();\n        return true;\n    } else {\n        m_io->unget();\n        exceptions_enable();\n        return false;\n    }\n}\n\nvoid kaitai::kstream::seek(uint64_t pos) {\n    m_io->seekg(pos);\n}\n\nuint64_t kaitai::kstream::pos() {\n    return m_io->tellg();\n}\n\nuint64_t kaitai::kstream::size() {\n    std::iostream::pos_type cur_pos = m_io->tellg();\n    m_io->seekg(0, std::ios::end);\n    std::iostream::pos_type len = m_io->tellg();\n    m_io->seekg(cur_pos);\n    return len;\n}\n\n// ========================================================================\n// Integer numbers\n// ========================================================================\n\n// ------------------------------------------------------------------------\n// Signed\n// ------------------------------------------------------------------------\n\nint8_t kaitai::kstream::read_s1() {\n    char t;\n    m_io->get(t);\n    return t;\n}\n\n// ........................................................................\n// Big-endian\n// ........................................................................\n\nint16_t kaitai::kstream::read_s2be() {\n    int16_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 2);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_16(t);\n#endif\n    return t;\n}\n\nint32_t kaitai::kstream::read_s4be() {\n    int32_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 4);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_32(t);\n#endif\n    return t;\n}\n\nint64_t kaitai::kstream::read_s8be() {\n    int64_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 8);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_64(t);\n#endif\n    return t;\n}\n\n// ........................................................................\n// Little-endian\n// ........................................................................\n\nint16_t kaitai::kstream::read_s2le() {\n    int16_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 2);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_16(t);\n#endif\n    return t;\n}\n\nint32_t kaitai::kstream::read_s4le() {\n    int32_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 4);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_32(t);\n#endif\n    return t;\n}\n\nint64_t kaitai::kstream::read_s8le() {\n    int64_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 8);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_64(t);\n#endif\n    return t;\n}\n\n// ------------------------------------------------------------------------\n// Unsigned\n// ------------------------------------------------------------------------\n\nuint8_t kaitai::kstream::read_u1() {\n    char t;\n    m_io->get(t);\n    return t;\n}\n\n// ........................................................................\n// Big-endian\n// ........................................................................\n\nuint16_t kaitai::kstream::read_u2be() {\n    uint16_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 2);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_16(t);\n#endif\n    return t;\n}\n\nuint32_t kaitai::kstream::read_u4be() {\n    uint32_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 4);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_32(t);\n#endif\n    return t;\n}\n\nuint64_t kaitai::kstream::read_u8be() {\n    uint64_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 8);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_64(t);\n#endif\n    return t;\n}\n\n// ........................................................................\n// Little-endian\n// ........................................................................\n\nuint16_t kaitai::kstream::read_u2le() {\n    uint16_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 2);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_16(t);\n#endif\n    return t;\n}\n\nuint32_t kaitai::kstream::read_u4le() {\n    uint32_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 4);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_32(t);\n#endif\n    return t;\n}\n\nuint64_t kaitai::kstream::read_u8le() {\n    uint64_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 8);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_64(t);\n#endif\n    return t;\n}\n\n// ========================================================================\n// Floating point numbers\n// ========================================================================\n\n// ........................................................................\n// Big-endian\n// ........................................................................\n\nfloat kaitai::kstream::read_f4be() {\n    uint32_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 4);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_32(t);\n#endif\n    return reinterpret_cast<float&>(t);\n}\n\ndouble kaitai::kstream::read_f8be() {\n    uint64_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 8);\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n    t = bswap_64(t);\n#endif\n    return reinterpret_cast<double&>(t);\n}\n\n// ........................................................................\n// Little-endian\n// ........................................................................\n\nfloat kaitai::kstream::read_f4le() {\n    uint32_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 4);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_32(t);\n#endif\n    return reinterpret_cast<float&>(t);\n}\n\ndouble kaitai::kstream::read_f8le() {\n    uint64_t t;\n    m_io->read(reinterpret_cast<char *>(&t), 8);\n#if __BYTE_ORDER == __BIG_ENDIAN\n    t = bswap_64(t);\n#endif\n    return reinterpret_cast<double&>(t);\n}\n\n// ========================================================================\n// Unaligned bit values\n// ========================================================================\n\nvoid kaitai::kstream::align_to_byte() {\n    m_bits_left = 0;\n    m_bits = 0;\n}\n\nuint64_t kaitai::kstream::read_bits_int_be(int n) {\n    int bits_needed = n - m_bits_left;\n    if (bits_needed > 0) {\n        // 1 bit  => 1 byte\n        // 8 bits => 1 byte\n        // 9 bits => 2 bytes\n        int bytes_needed = ((bits_needed - 1) / 8) + 1;\n        if (bytes_needed > 8)\n            throw std::runtime_error(\"read_bits_int: more than 8 bytes requested\");\n        char buf[8];\n        m_io->read(buf, bytes_needed);\n        for (int i = 0; i < bytes_needed; i++) {\n            uint8_t b = buf[i];\n            m_bits <<= 8;\n            m_bits |= b;\n            m_bits_left += 8;\n        }\n    }\n\n    // raw mask with required number of 1s, starting from lowest bit\n    uint64_t mask = get_mask_ones(n);\n    // shift mask to align with highest bits available in @bits\n    int shift_bits = m_bits_left - n;\n    mask <<= shift_bits;\n    // derive reading result\n    uint64_t res = (m_bits & mask) >> shift_bits;\n    // clear top bits that we've just read => AND with 1s\n    m_bits_left -= n;\n    mask = get_mask_ones(m_bits_left);\n    m_bits &= mask;\n\n    return res;\n}\n\n// Deprecated, use read_bits_int_be() instead.\nuint64_t kaitai::kstream::read_bits_int(int n) {\n    return read_bits_int_be(n);\n}\n\nuint64_t kaitai::kstream::read_bits_int_le(int n) {\n    int bits_needed = n - m_bits_left;\n    if (bits_needed > 0) {\n        // 1 bit  => 1 byte\n        // 8 bits => 1 byte\n        // 9 bits => 2 bytes\n        int bytes_needed = ((bits_needed - 1) / 8) + 1;\n        if (bytes_needed > 8)\n            throw std::runtime_error(\"read_bits_int_le: more than 8 bytes requested\");\n        char buf[8];\n        m_io->read(buf, bytes_needed);\n        for (int i = 0; i < bytes_needed; i++) {\n            uint8_t b = buf[i];\n            m_bits |= (static_cast<uint64_t>(b) << m_bits_left);\n            m_bits_left += 8;\n        }\n    }\n\n    // raw mask with required number of 1s, starting from lowest bit\n    uint64_t mask = get_mask_ones(n);\n    // derive reading result\n    uint64_t res = m_bits & mask;\n    // remove bottom bits that we've just read by shifting\n    m_bits >>= n;\n    m_bits_left -= n;\n\n    return res;\n}\n\nuint64_t kaitai::kstream::get_mask_ones(int n) {\n    if (n == 64) {\n        return 0xFFFFFFFFFFFFFFFF;\n    } else {\n        return ((uint64_t) 1 << n) - 1;\n    }\n}\n\n// ========================================================================\n// Byte arrays\n// ========================================================================\n\nstd::string kaitai::kstream::read_bytes(std::streamsize len) {\n    std::vector<char> result(len);\n\n    // NOTE: streamsize type is signed, negative values are only *supposed* to not be used.\n    // http://en.cppreference.com/w/cpp/io/streamsize\n    if (len < 0) {\n        throw std::runtime_error(\"read_bytes: requested a negative amount\");\n    }\n\n    if (len > 0) {\n        m_io->read(&result[0], len);\n    }\n\n    return std::string(result.begin(), result.end());\n}\n\nstd::string kaitai::kstream::read_bytes_full() {\n    std::iostream::pos_type p1 = m_io->tellg();\n    m_io->seekg(0, std::ios::end);\n    std::iostream::pos_type p2 = m_io->tellg();\n    size_t len = p2 - p1;\n\n    // Note: this requires a std::string to be backed with a\n    // contiguous buffer. Officially, it's a only requirement since\n    // C++11 (C++98 and C++03 didn't have this requirement), but all\n    // major implementations had contiguous buffers anyway.\n    std::string result(len, ' ');\n    m_io->seekg(p1);\n    m_io->read(&result[0], len);\n\n    return result;\n}\n\nstd::string kaitai::kstream::read_bytes_term(char term, bool include, bool consume, bool eos_error) {\n    std::string result;\n    std::getline(*m_io, result, term);\n    if (m_io->eof()) {\n        // encountered EOF\n        if (eos_error) {\n            throw std::runtime_error(\"read_bytes_term: encountered EOF\");\n        }\n    } else {\n        // encountered terminator\n        if (include)\n            result.push_back(term);\n        if (!consume)\n            m_io->unget();\n    }\n    return result;\n}\n\nstd::string kaitai::kstream::ensure_fixed_contents(std::string expected) {\n    std::string actual = read_bytes(expected.length());\n\n    if (actual != expected) {\n        // NOTE: I think printing it outright is not best idea, it could contain non-ascii charactes like backspace and beeps and whatnot. It would be better to print hexlified version, and also to redirect it to stderr.\n        throw std::runtime_error(\"ensure_fixed_contents: actual data does not match expected data\");\n    }\n\n    return actual;\n}\n\nstd::string kaitai::kstream::bytes_strip_right(std::string src, char pad_byte) {\n    std::size_t new_len = src.length();\n\n    while (new_len > 0 && src[new_len - 1] == pad_byte)\n        new_len--;\n\n    return src.substr(0, new_len);\n}\n\nstd::string kaitai::kstream::bytes_terminate(std::string src, char term, bool include) {\n    std::size_t new_len = 0;\n    std::size_t max_len = src.length();\n\n    while (new_len < max_len && src[new_len] != term)\n        new_len++;\n\n    if (include && new_len < max_len)\n        new_len++;\n\n    return src.substr(0, new_len);\n}\n\n// ========================================================================\n// Byte array processing\n// ========================================================================\n\nstd::string kaitai::kstream::process_xor_one(std::string data, uint8_t key) {\n    size_t len = data.length();\n    std::string result(len, ' ');\n\n    for (size_t i = 0; i < len; i++)\n        result[i] = data[i] ^ key;\n\n    return result;\n}\n\nstd::string kaitai::kstream::process_xor_many(std::string data, std::string key) {\n    size_t len = data.length();\n    size_t kl = key.length();\n    std::string result(len, ' ');\n\n    size_t ki = 0;\n    for (size_t i = 0; i < len; i++) {\n        result[i] = data[i] ^ key[ki];\n        ki++;\n        if (ki >= kl)\n            ki = 0;\n    }\n\n    return result;\n}\n\nstd::string kaitai::kstream::process_rotate_left(std::string data, int amount) {\n    size_t len = data.length();\n    std::string result(len, ' ');\n\n    for (size_t i = 0; i < len; i++) {\n        uint8_t bits = data[i];\n        result[i] = (bits << amount) | (bits >> (8 - amount));\n    }\n\n    return result;\n}\n\n#ifdef KS_ZLIB\n#include <zlib.h>\n\nstd::string kaitai::kstream::process_zlib(std::string data) {\n    int ret;\n\n    unsigned char *src_ptr = reinterpret_cast<unsigned char*>(&data[0]);\n    std::stringstream dst_strm;\n\n    z_stream strm;\n    strm.zalloc = Z_NULL;\n    strm.zfree = Z_NULL;\n    strm.opaque = Z_NULL;\n\n    ret = inflateInit(&strm);\n    if (ret != Z_OK)\n        throw std::runtime_error(\"process_zlib: inflateInit error\");\n\n    strm.next_in = src_ptr;\n    strm.avail_in = data.length();\n\n    unsigned char outbuffer[ZLIB_BUF_SIZE];\n    std::string outstring;\n\n    // get the decompressed bytes blockwise using repeated calls to inflate\n    do {\n        strm.next_out = reinterpret_cast<Bytef*>(outbuffer);\n        strm.avail_out = sizeof(outbuffer);\n\n        ret = inflate(&strm, 0);\n\n        if (outstring.size() < strm.total_out)\n            outstring.append(reinterpret_cast<char*>(outbuffer), strm.total_out - outstring.size());\n    } while (ret == Z_OK);\n\n    if (ret != Z_STREAM_END) {          // an error occurred that was not EOF\n        std::ostringstream exc_msg;\n        exc_msg << \"process_zlib: error #\" << ret << \"): \" << strm.msg;\n        throw std::runtime_error(exc_msg.str());\n    }\n\n    if (inflateEnd(&strm) != Z_OK)\n        throw std::runtime_error(\"process_zlib: inflateEnd error\");\n\n    return outstring;\n}\n#endif\n\n// ========================================================================\n// Misc utility methods\n// ========================================================================\n\nint kaitai::kstream::mod(int a, int b) {\n    if (b <= 0)\n        throw std::invalid_argument(\"mod: divisor b <= 0\");\n    int r = a % b;\n    if (r < 0)\n        r += b;\n    return r;\n}\n\n#include <stdio.h>\nstd::string kaitai::kstream::to_string(int val) {\n    // if int is 32 bits, \"-2147483648\" is the longest string representation\n    //   => 11 chars + zero => 12 chars\n    // if int is 64 bits, \"-9223372036854775808\" is the longest\n    //   => 20 chars + zero => 21 chars\n    char buf[25];\n    int got_len = snprintf(buf, sizeof(buf), \"%d\", val);\n\n    // should never happen, but check nonetheless\n    if (got_len > sizeof(buf))\n        throw std::invalid_argument(\"to_string: integer is longer than string buffer\");\n\n    return std::string(buf);\n}\n\n#include <algorithm>\nstd::string kaitai::kstream::reverse(std::string val) {\n    std::reverse(val.begin(), val.end());\n\n    return val;\n}\n\nuint8_t kaitai::kstream::byte_array_min(const std::string val) {\n    uint8_t min = 0xff; // UINT8_MAX\n    std::string::const_iterator end = val.end();\n    for (std::string::const_iterator it = val.begin(); it != end; ++it) {\n        uint8_t cur = static_cast<uint8_t>(*it);\n        if (cur < min) {\n            min = cur;\n        }\n    }\n    return min;\n}\n\nuint8_t kaitai::kstream::byte_array_max(const std::string val) {\n    uint8_t max = 0; // UINT8_MIN\n    std::string::const_iterator end = val.end();\n    for (std::string::const_iterator it = val.begin(); it != end; ++it) {\n        uint8_t cur = static_cast<uint8_t>(*it);\n        if (cur > max) {\n            max = cur;\n        }\n    }\n    return max;\n}\n\n// ========================================================================\n// Other internal methods\n// ========================================================================\n\n#ifndef KS_STR_DEFAULT_ENCODING\n#define KS_STR_DEFAULT_ENCODING \"UTF-8\"\n#endif\n\n#ifdef KS_STR_ENCODING_ICONV\n\n#include <iconv.h>\n#include <cerrno>\n#include <stdexcept>\n\nstd::string kaitai::kstream::bytes_to_str(std::string src, std::string src_enc) {\n    iconv_t cd = iconv_open(KS_STR_DEFAULT_ENCODING, src_enc.c_str());\n\n    if (cd == (iconv_t) -1) {\n        if (errno == EINVAL) {\n            throw std::runtime_error(\"bytes_to_str: invalid encoding pair conversion requested\");\n        } else {\n            throw std::runtime_error(\"bytes_to_str: error opening iconv\");\n        }\n    }\n\n    size_t src_len = src.length();\n    size_t src_left = src_len;\n\n    // Start with a buffer length of double the source length.\n    size_t dst_len = src_len * 2;\n    std::string dst(dst_len, ' ');\n    size_t dst_left = dst_len;\n\n    char *src_ptr = &src[0];\n    char *dst_ptr = &dst[0];\n\n    while (true) {\n        size_t res = iconv(cd, &src_ptr, &src_left, &dst_ptr, &dst_left);\n\n        if (res == (size_t) -1) {\n            if (errno == E2BIG) {\n                // dst buffer is not enough to accomodate whole string\n                // enlarge the buffer and try again\n                size_t dst_used = dst_len - dst_left;\n                dst_left += dst_len;\n                dst_len += dst_len;\n                dst.resize(dst_len);\n\n                // dst.resize might have allocated destination buffer in another area\n                // of memory, thus our previous pointer \"dst\" will be invalid; re-point\n                // it using \"dst_used\".\n                dst_ptr = &dst[dst_used];\n            } else {\n                throw std::runtime_error(\"bytes_to_str: iconv error\");\n            }\n        } else {\n            // conversion successful\n            dst.resize(dst_len - dst_left);\n            break;\n        }\n    }\n\n    if (iconv_close(cd) != 0) {\n        throw std::runtime_error(\"bytes_to_str: iconv close error\");\n    }\n\n    return dst;\n}\n#elif defined(KS_STR_ENCODING_NONE)\nstd::string kaitai::kstream::bytes_to_str(std::string src, std::string src_enc) {\n    return src;\n}\n#else\n#error Need to decide how to handle strings: please define one of: KS_STR_ENCODING_ICONV, KS_STR_ENCODING_NONE\n#endif\n"
  },
  {
    "path": "phonelibs/kaitai/kaitaistream.h",
    "content": "#ifndef KAITAI_STREAM_H\n#define KAITAI_STREAM_H\n\n// Kaitai Struct runtime API version: x.y.z = 'xxxyyyzzz' decimal\n#define KAITAI_STRUCT_VERSION 9000L\n\n#include <istream>\n#include <sstream>\n#include <stdint.h>\n#include <sys/types.h>\n\nnamespace kaitai {\n\n/**\n * Kaitai Stream class (kaitai::kstream) is an implementation of\n * <a href=\"https://doc.kaitai.io/stream_api.html\">Kaitai Struct stream API</a>\n * for C++/STL. It's implemented as a wrapper over generic STL std::istream.\n *\n * It provides a wide variety of simple methods to read (parse) binary\n * representations of primitive types, such as integer and floating\n * point numbers, byte arrays and strings, and also provides stream\n * positioning / navigation methods with unified cross-language and\n * cross-toolkit semantics.\n *\n * Typically, end users won't access Kaitai Stream class manually, but would\n * describe a binary structure format using .ksy language and then would use\n * Kaitai Struct compiler to generate source code in desired target language.\n * That code, in turn, would use this class and API to do the actual parsing\n * job.\n */\nclass kstream {\npublic:\n    /**\n     * Constructs new Kaitai Stream object, wrapping a given std::istream.\n     * \\param io istream object to use for this Kaitai Stream\n     */\n    kstream(std::istream* io);\n\n    /**\n     * Constructs new Kaitai Stream object, wrapping a given in-memory data\n     * buffer.\n     * \\param data data buffer to use for this Kaitai Stream\n     */\n    kstream(std::string& data);\n\n    void close();\n\n    /** @name Stream positioning */\n    //@{\n    /**\n     * Check if stream pointer is at the end of stream. Note that the semantics\n     * are different from traditional STL semantics: one does *not* need to do a\n     * read (which will fail) after the actual end of the stream to trigger EOF\n     * flag, which can be accessed after that read. It is sufficient to just be\n     * at the end of the stream for this method to return true.\n     * \\return \"true\" if we are located at the end of the stream.\n     */\n    bool is_eof() const;\n\n    /**\n     * Set stream pointer to designated position.\n     * \\param pos new position (offset in bytes from the beginning of the stream)\n     */\n    void seek(uint64_t pos);\n\n    /**\n     * Get current position of a stream pointer.\n     * \\return pointer position, number of bytes from the beginning of the stream\n     */\n    uint64_t pos();\n\n    /**\n     * Get total size of the stream in bytes.\n     * \\return size of the stream in bytes\n     */\n    uint64_t size();\n    //@}\n\n    /** @name Integer numbers */\n    //@{\n\n    // ------------------------------------------------------------------------\n    // Signed\n    // ------------------------------------------------------------------------\n\n    int8_t read_s1();\n\n    // ........................................................................\n    // Big-endian\n    // ........................................................................\n\n    int16_t read_s2be();\n    int32_t read_s4be();\n    int64_t read_s8be();\n\n    // ........................................................................\n    // Little-endian\n    // ........................................................................\n\n    int16_t read_s2le();\n    int32_t read_s4le();\n    int64_t read_s8le();\n\n    // ------------------------------------------------------------------------\n    // Unsigned\n    // ------------------------------------------------------------------------\n\n    uint8_t read_u1();\n\n    // ........................................................................\n    // Big-endian\n    // ........................................................................\n\n    uint16_t read_u2be();\n    uint32_t read_u4be();\n    uint64_t read_u8be();\n\n    // ........................................................................\n    // Little-endian\n    // ........................................................................\n\n    uint16_t read_u2le();\n    uint32_t read_u4le();\n    uint64_t read_u8le();\n\n    //@}\n\n    /** @name Floating point numbers */\n    //@{\n\n    // ........................................................................\n    // Big-endian\n    // ........................................................................\n\n    float read_f4be();\n    double read_f8be();\n\n    // ........................................................................\n    // Little-endian\n    // ........................................................................\n\n    float read_f4le();\n    double read_f8le();\n\n    //@}\n\n    /** @name Unaligned bit values */\n    //@{\n\n    void align_to_byte();\n    uint64_t read_bits_int_be(int n);\n    uint64_t read_bits_int(int n);\n    uint64_t read_bits_int_le(int n);\n\n    //@}\n\n    /** @name Byte arrays */\n    //@{\n\n    std::string read_bytes(std::streamsize len);\n    std::string read_bytes_full();\n    std::string read_bytes_term(char term, bool include, bool consume, bool eos_error);\n    std::string ensure_fixed_contents(std::string expected);\n\n    static std::string bytes_strip_right(std::string src, char pad_byte);\n    static std::string bytes_terminate(std::string src, char term, bool include);\n    static std::string bytes_to_str(std::string src, std::string src_enc);\n\n    //@}\n\n    /** @name Byte array processing */\n    //@{\n\n    /**\n     * Performs a XOR processing with given data, XORing every byte of input with a single\n     * given value.\n     * @param data data to process\n     * @param key value to XOR with\n     * @return processed data\n     */\n    static std::string process_xor_one(std::string data, uint8_t key);\n\n    /**\n     * Performs a XOR processing with given data, XORing every byte of input with a key\n     * array, repeating key array many times, if necessary (i.e. if data array is longer\n     * than key array).\n     * @param data data to process\n     * @param key array of bytes to XOR with\n     * @return processed data\n     */\n    static std::string process_xor_many(std::string data, std::string key);\n\n    /**\n     * Performs a circular left rotation shift for a given buffer by a given amount of bits,\n     * using groups of 1 bytes each time. Right circular rotation should be performed\n     * using this procedure with corrected amount.\n     * @param data source data to process\n     * @param amount number of bits to shift by\n     * @return copy of source array with requested shift applied\n     */\n    static std::string process_rotate_left(std::string data, int amount);\n\n#ifdef KS_ZLIB\n    /**\n     * Performs an unpacking (\"inflation\") of zlib-compressed data with usual zlib headers.\n     * @param data data to unpack\n     * @return unpacked data\n     * @throws IOException\n     */\n    static std::string process_zlib(std::string data);\n#endif\n\n    //@}\n\n    /**\n     * Performs modulo operation between two integers: dividend `a`\n     * and divisor `b`. Divisor `b` is expected to be positive. The\n     * result is always 0 <= x <= b - 1.\n     */\n    static int mod(int a, int b);\n\n    /**\n     * Converts given integer `val` to a decimal string representation.\n     * Should be used in place of std::to_string() (which is available only\n     * since C++11) in older C++ implementations.\n     */\n    static std::string to_string(int val);\n\n    /**\n     * Reverses given string `val`, so that the first character becomes the\n     * last and the last one becomes the first. This should be used to avoid\n     * the need of local variables at the caller.\n     */\n    static std::string reverse(std::string val);\n\n    /**\n     * Finds the minimal byte in a byte array, treating bytes as\n     * unsigned values.\n     * @param val byte array to scan\n     * @return minimal byte in byte array as integer\n     */\n    static uint8_t byte_array_min(const std::string val);\n\n    /**\n     * Finds the maximal byte in a byte array, treating bytes as\n     * unsigned values.\n     * @param val byte array to scan\n     * @return maximal byte in byte array as integer\n     */\n    static uint8_t byte_array_max(const std::string val);\n\nprivate:\n    std::istream* m_io;\n    std::istringstream m_io_str;\n    int m_bits_left;\n    uint64_t m_bits;\n\n    void init();\n    void exceptions_enable() const;\n\n    static uint64_t get_mask_ones(int n);\n\n    static const int ZLIB_BUF_SIZE = 128 * 1024;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/kaitai/kaitaistruct.h",
    "content": "#ifndef KAITAI_STRUCT_H\n#define KAITAI_STRUCT_H\n\n#include <kaitai/kaitaistream.h>\n\nnamespace kaitai {\n\nclass kstruct {\npublic:\n    kstruct(kstream *_io) { m__io = _io; }\n    virtual ~kstruct() {}\nprotected:\n    kstream *m__io;\npublic:\n    kstream *_io() { return m__io; }\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/libgralloc/include/gralloc_priv.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef GRALLOC_PRIV_H_\n#define GRALLOC_PRIV_H_\n\n#include <stdint.h>\n#include <limits.h>\n#include <sys/cdefs.h>\n#include <hardware/gralloc.h>\n#include <pthread.h>\n#include <errno.h>\n#include <unistd.h>\n\n#include <cutils/native_handle.h>\n\n#include <cutils/log.h>\n\n#define ROUND_UP_PAGESIZE(x) ( (((unsigned long)(x)) + PAGE_SIZE-1)  & \\\n                               (~(PAGE_SIZE-1)) )\n\n/* Gralloc usage bits indicating the type of allocation that should be used */\n/* SYSTEM heap comes from kernel vmalloc (ION_SYSTEM_HEAP_ID)\n * is cached by default and\n * is not secured */\n\n/* GRALLOC_USAGE_PRIVATE_0 is unused */\n\n/* Non linear, Universal Bandwidth Compression */\n#define GRALLOC_USAGE_PRIVATE_ALLOC_UBWC      GRALLOC_USAGE_PRIVATE_1\n\n/* IOMMU heap comes from manually allocated pages, can be cached/uncached,\n * is not secured */\n#define GRALLOC_USAGE_PRIVATE_IOMMU_HEAP      GRALLOC_USAGE_PRIVATE_2\n\n/* MM heap is a carveout heap for video, can be secured */\n#define GRALLOC_USAGE_PRIVATE_MM_HEAP         GRALLOC_USAGE_PRIVATE_3\n\n/* ADSP heap is a carveout heap, is not secured */\n#define GRALLOC_USAGE_PRIVATE_ADSP_HEAP       0x01000000\n\n/* Set this for allocating uncached memory (using O_DSYNC),\n * cannot be used with noncontiguous heaps */\n#define GRALLOC_USAGE_PRIVATE_UNCACHED        0x02000000\n\n/* Buffer content should be displayed on an primary display only */\n#define GRALLOC_USAGE_PRIVATE_INTERNAL_ONLY   0x04000000\n\n/* Buffer content should be displayed on an external display only */\n#define GRALLOC_USAGE_PRIVATE_EXTERNAL_ONLY   0x08000000\n\n/* This flag is set for WFD usecase */\n#define GRALLOC_USAGE_PRIVATE_WFD             0x00200000\n\n/* CAMERA heap is a carveout heap for camera, is not secured */\n#define GRALLOC_USAGE_PRIVATE_CAMERA_HEAP     0x00400000\n\n/* This flag is used for SECURE display usecase */\n#define GRALLOC_USAGE_PRIVATE_SECURE_DISPLAY  0x00800000\n\n/* define Gralloc perform */\n#define GRALLOC_MODULE_PERFORM_CREATE_HANDLE_FROM_BUFFER 1\n// This will be used by the graphics drivers to know if certain features\n// are defined in this display HAL.\n// Ex: Newer GFX libraries + Older Display HAL\n#define GRALLOC_MODULE_PERFORM_GET_STRIDE 2\n#define GRALLOC_MODULE_PERFORM_GET_CUSTOM_STRIDE_FROM_HANDLE 3\n#define GRALLOC_MODULE_PERFORM_GET_CUSTOM_STRIDE_AND_HEIGHT_FROM_HANDLE 4\n#define GRALLOC_MODULE_PERFORM_GET_ATTRIBUTES 5\n#define GRALLOC_MODULE_PERFORM_GET_COLOR_SPACE_FROM_HANDLE 6\n#define GRALLOC_MODULE_PERFORM_GET_YUV_PLANE_INFO 7\n#define GRALLOC_MODULE_PERFORM_GET_MAP_SECURE_BUFFER_INFO 8\n#define GRALLOC_MODULE_PERFORM_GET_UBWC_FLAG 9\n#define GRALLOC_MODULE_PERFORM_GET_RGB_DATA_ADDRESS 10\n#define GRALLOC_MODULE_PERFORM_GET_IGC 11\n#define GRALLOC_MODULE_PERFORM_SET_IGC 12\n#define GRALLOC_MODULE_PERFORM_SET_SINGLE_BUFFER_MODE 13\n\n/* OEM specific HAL formats */\n\n#define HAL_PIXEL_FORMAT_RGBA_5551               6\n#define HAL_PIXEL_FORMAT_RGBA_4444               7\n#define HAL_PIXEL_FORMAT_NV12_ENCODEABLE         0x102\n#define HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS      0x7FA30C04\n#define HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED      0x7FA30C03\n#define HAL_PIXEL_FORMAT_YCbCr_420_SP            0x109\n#define HAL_PIXEL_FORMAT_YCrCb_420_SP_ADRENO     0x7FA30C01\n#define HAL_PIXEL_FORMAT_YCrCb_422_SP            0x10B\n#define HAL_PIXEL_FORMAT_R_8                     0x10D\n#define HAL_PIXEL_FORMAT_RG_88                   0x10E\n#define HAL_PIXEL_FORMAT_YCbCr_444_SP            0x10F\n#define HAL_PIXEL_FORMAT_YCrCb_444_SP            0x110\n#define HAL_PIXEL_FORMAT_YCrCb_422_I             0x111\n#define HAL_PIXEL_FORMAT_BGRX_8888               0x112\n#define HAL_PIXEL_FORMAT_NV21_ZSL                0x113\n#define HAL_PIXEL_FORMAT_YCrCb_420_SP_VENUS      0x114\n#define HAL_PIXEL_FORMAT_BGR_565                 0x115\n#define HAL_PIXEL_FORMAT_INTERLACE               0x180\n\n//v4l2_fourcc('Y', 'U', 'Y', 'L'). 24 bpp YUYV 4:2:2 10 bit per component\n#define HAL_PIXEL_FORMAT_YCbCr_422_I_10BIT       0x4C595559\n\n//v4l2_fourcc('Y', 'B', 'W', 'C'). 10 bit per component. This compressed\n//format reduces the memory access bandwidth\n#define HAL_PIXEL_FORMAT_YCbCr_422_I_10BIT_COMPRESSED  0x43574259\n\n// UBWC aligned Venus format\n#define HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC 0x7FA30C06\n\n//Khronos ASTC formats\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_4x4_KHR             0x93B0\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_5x4_KHR             0x93B1\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_5x5_KHR             0x93B2\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_6x5_KHR             0x93B3\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_6x6_KHR             0x93B4\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x5_KHR             0x93B5\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x6_KHR             0x93B6\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x8_KHR             0x93B7\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x5_KHR            0x93B8\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x6_KHR            0x93B9\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x8_KHR            0x93BA\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x10_KHR           0x93BB\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_12x10_KHR           0x93BC\n#define HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_12x12_KHR           0x93BD\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR     0x93D0\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR     0x93D1\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR     0x93D2\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR     0x93D3\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR     0x93D4\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR     0x93D5\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR     0x93D6\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR     0x93D7\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR    0x93D8\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR    0x93D9\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR    0x93DA\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR   0x93DB\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR   0x93DC\n#define HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR   0x93DD\n\n/* possible values for inverse gamma correction */\n#define HAL_IGC_NOT_SPECIFIED     0\n#define HAL_IGC_s_RGB             1\n\n/* possible formats for 3D content*/\nenum {\n    HAL_NO_3D                      = 0x0,\n    HAL_3D_SIDE_BY_SIDE_L_R        = 0x1,\n    HAL_3D_SIDE_BY_SIDE_R_L        = 0x2,\n    HAL_3D_TOP_BOTTOM              = 0x4,\n    HAL_3D_IN_SIDE_BY_SIDE_L_R     = 0x10000, //unused legacy format\n};\n\nenum {\n    BUFFER_TYPE_UI = 0,\n    BUFFER_TYPE_VIDEO\n};\n\n#ifdef __cplusplus\nstruct private_handle_t : public native_handle {\n#else\n    struct private_handle_t {\n        native_handle_t nativeHandle;\n#endif\n        enum {\n            PRIV_FLAGS_FRAMEBUFFER        = 0x00000001,\n            PRIV_FLAGS_USES_ION           = 0x00000008,\n            PRIV_FLAGS_USES_ASHMEM        = 0x00000010,\n            PRIV_FLAGS_NEEDS_FLUSH        = 0x00000020,\n            PRIV_FLAGS_INTERNAL_ONLY      = 0x00000040,\n            PRIV_FLAGS_NON_CPU_WRITER     = 0x00000080,\n            PRIV_FLAGS_NONCONTIGUOUS_MEM  = 0x00000100,\n            PRIV_FLAGS_CACHED             = 0x00000200,\n            PRIV_FLAGS_SECURE_BUFFER      = 0x00000400,\n            // Display on external only\n            PRIV_FLAGS_EXTERNAL_ONLY      = 0x00002000,\n            // Set by HWC for protected non secure buffers\n            PRIV_FLAGS_PROTECTED_BUFFER   = 0x00004000,\n            PRIV_FLAGS_VIDEO_ENCODER      = 0x00010000,\n            PRIV_FLAGS_CAMERA_WRITE       = 0x00020000,\n            PRIV_FLAGS_CAMERA_READ        = 0x00040000,\n            PRIV_FLAGS_HW_COMPOSER        = 0x00080000,\n            PRIV_FLAGS_HW_TEXTURE         = 0x00100000,\n            PRIV_FLAGS_ITU_R_601          = 0x00200000, //Unused from display\n            PRIV_FLAGS_ITU_R_601_FR       = 0x00400000, //Unused from display\n            PRIV_FLAGS_ITU_R_709          = 0x00800000, //Unused from display\n            PRIV_FLAGS_SECURE_DISPLAY     = 0x01000000,\n            // Buffer is rendered in Tile Format\n            PRIV_FLAGS_TILE_RENDERED      = 0x02000000,\n            // Buffer rendered using CPU/SW renderer\n            PRIV_FLAGS_CPU_RENDERED       = 0x04000000,\n            // Buffer is allocated with UBWC alignment\n            PRIV_FLAGS_UBWC_ALIGNED       = 0x08000000,\n            // Buffer allocated will be consumed by SF/HWC\n            PRIV_FLAGS_DISP_CONSUMER      = 0x10000000\n        };\n\n        // file-descriptors\n        int     fd;\n        int     fd_metadata;          // fd for the meta-data\n        // ints\n        int     magic;\n        int     flags;\n        unsigned int  size;\n        unsigned int  offset;\n        int     bufferType;\n        uint64_t base __attribute__((aligned(8)));\n        unsigned int  offset_metadata;\n        // The gpu address mapped into the mmu.\n        uint64_t gpuaddr __attribute__((aligned(8)));\n        int     format;\n        int     width;              // specifies aligned width\n        int     height;             // specifies aligned height\n        int     real_width;\n        int     real_height;\n        uint64_t base_metadata __attribute__((aligned(8)));\n\n#ifdef __cplusplus\n        static const int sNumFds = 2;\n        static inline int sNumInts() {\n            return ((sizeof(private_handle_t) - sizeof(native_handle_t)) /\n                    sizeof(int)) - sNumFds;\n        }\n        static const int sMagic = 'gmsm';\n\n        private_handle_t(int fd, unsigned int size, int flags, int bufferType,\n                         int format, int aligned_width, int aligned_height,\n                         int width, int height, int eFd = -1,\n                         unsigned int eOffset = 0, uint64_t eBase = 0) :\n            fd(fd), fd_metadata(eFd), magic(sMagic),\n            flags(flags), size(size), offset(0), bufferType(bufferType),\n            base(0), offset_metadata(eOffset), gpuaddr(0),\n            format(format), width(aligned_width), height(aligned_height),\n            real_width(width), real_height(height), base_metadata(eBase)\n        {\n            version = (int) sizeof(native_handle);\n            numInts = sNumInts();\n            numFds = sNumFds;\n        }\n        ~private_handle_t() {\n            magic = 0;\n        }\n\n        static int validate(const native_handle* h) {\n            const private_handle_t* hnd = (const private_handle_t*)h;\n            if (!h || h->version != sizeof(native_handle) ||\n                h->numInts != sNumInts() || h->numFds != sNumFds ||\n                hnd->magic != sMagic)\n            {\n                ALOGD(\"Invalid gralloc handle (at %p): \"\n                      \"ver(%d/%zu) ints(%d/%d) fds(%d/%d)\"\n                      \"magic(%c%c%c%c/%c%c%c%c)\",\n                      h,\n                      h ? h->version : -1, sizeof(native_handle),\n                      h ? h->numInts : -1, sNumInts(),\n                      h ? h->numFds : -1, sNumFds,\n                      hnd ? (((hnd->magic >> 24) & 0xFF)?\n                             ((hnd->magic >> 24) & 0xFF) : '-') : '?',\n                      hnd ? (((hnd->magic >> 16) & 0xFF)?\n                             ((hnd->magic >> 16) & 0xFF) : '-') : '?',\n                      hnd ? (((hnd->magic >> 8) & 0xFF)?\n                             ((hnd->magic >> 8) & 0xFF) : '-') : '?',\n                      hnd ? (((hnd->magic >> 0) & 0xFF)?\n                             ((hnd->magic >> 0) & 0xFF) : '-') : '?',\n                      (sMagic >> 24) & 0xFF,\n                      (sMagic >> 16) & 0xFF,\n                      (sMagic >> 8) & 0xFF,\n                      (sMagic >> 0) & 0xFF);\n                return -EINVAL;\n            }\n            return 0;\n        }\n\n        static private_handle_t* dynamicCast(const native_handle* in) {\n            if (validate(in) == 0) {\n                return (private_handle_t*) in;\n            }\n            return NULL;\n        }\n#endif\n    };\n\n#endif /* GRALLOC_PRIV_H_ */\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/basic_types.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_BASIC_TYPES_H_\n#define INCLUDE_LIBYUV_BASIC_TYPES_H_\n\n#include <stddef.h>  // for NULL, size_t\n\n#if defined(_MSC_VER) && (_MSC_VER < 1600)\n#include <sys/types.h>  // for uintptr_t on x86\n#else\n#include <stdint.h>  // for uintptr_t\n#endif\n\n#ifndef GG_LONGLONG\n#ifndef INT_TYPES_DEFINED\n#define INT_TYPES_DEFINED\n#ifdef COMPILER_MSVC\ntypedef unsigned __int64 uint64;\ntypedef __int64 int64;\n#ifndef INT64_C\n#define INT64_C(x) x ## I64\n#endif\n#ifndef UINT64_C\n#define UINT64_C(x) x ## UI64\n#endif\n#define INT64_F \"I64\"\n#else  // COMPILER_MSVC\n#if defined(__LP64__) && !defined(__OpenBSD__) && !defined(__APPLE__)\ntypedef unsigned long uint64;  // NOLINT\ntypedef long int64;  // NOLINT\n#ifndef INT64_C\n#define INT64_C(x) x ## L\n#endif\n#ifndef UINT64_C\n#define UINT64_C(x) x ## UL\n#endif\n#define INT64_F \"l\"\n#else  // defined(__LP64__) && !defined(__OpenBSD__) && !defined(__APPLE__)\ntypedef unsigned long long uint64;  // NOLINT\ntypedef long long int64;  // NOLINT\n#ifndef INT64_C\n#define INT64_C(x) x ## LL\n#endif\n#ifndef UINT64_C\n#define UINT64_C(x) x ## ULL\n#endif\n#define INT64_F \"ll\"\n#endif  // __LP64__\n#endif  // COMPILER_MSVC\ntypedef unsigned int uint32;\ntypedef int int32;\ntypedef unsigned short uint16;  // NOLINT\ntypedef short int16;  // NOLINT\ntypedef unsigned char uint8;\ntypedef signed char int8;\n#endif  // INT_TYPES_DEFINED\n#endif  // GG_LONGLONG\n\n// Detect compiler is for x86 or x64.\n#if defined(__x86_64__) || defined(_M_X64) || \\\n    defined(__i386__) || defined(_M_IX86)\n#define CPU_X86 1\n#endif\n// Detect compiler is for ARM.\n#if defined(__arm__) || defined(_M_ARM)\n#define CPU_ARM 1\n#endif\n\n#ifndef ALIGNP\n#ifdef __cplusplus\n#define ALIGNP(p, t) \\\n    (reinterpret_cast<uint8*>(((reinterpret_cast<uintptr_t>(p) + \\\n    ((t) - 1)) & ~((t) - 1))))\n#else\n#define ALIGNP(p, t) \\\n    ((uint8*)((((uintptr_t)(p) + ((t) - 1)) & ~((t) - 1))))  /* NOLINT */\n#endif\n#endif\n\n#if !defined(LIBYUV_API)\n#if defined(_WIN32) || defined(__CYGWIN__)\n#if defined(LIBYUV_BUILDING_SHARED_LIBRARY)\n#define LIBYUV_API __declspec(dllexport)\n#elif defined(LIBYUV_USING_SHARED_LIBRARY)\n#define LIBYUV_API __declspec(dllimport)\n#else\n#define LIBYUV_API\n#endif  // LIBYUV_BUILDING_SHARED_LIBRARY\n#elif defined(__GNUC__) && (__GNUC__ >= 4) && !defined(__APPLE__) && \\\n    (defined(LIBYUV_BUILDING_SHARED_LIBRARY) || \\\n    defined(LIBYUV_USING_SHARED_LIBRARY))\n#define LIBYUV_API __attribute__ ((visibility (\"default\")))\n#else\n#define LIBYUV_API\n#endif  // __GNUC__\n#endif  // LIBYUV_API\n\n#define LIBYUV_BOOL int\n#define LIBYUV_FALSE 0\n#define LIBYUV_TRUE 1\n\n// Visual C x86 or GCC little endian.\n#if defined(__x86_64__) || defined(_M_X64) || \\\n  defined(__i386__) || defined(_M_IX86) || \\\n  defined(__arm__) || defined(_M_ARM) || \\\n  (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)\n#define LIBYUV_LITTLE_ENDIAN\n#endif\n\n#endif  // INCLUDE_LIBYUV_BASIC_TYPES_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/compare.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_COMPARE_H_\n#define INCLUDE_LIBYUV_COMPARE_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Compute a hash for specified memory. Seed of 5381 recommended.\nLIBYUV_API\nuint32 HashDjb2(const uint8* src, uint64 count, uint32 seed);\n\n// Scan an opaque argb image and return fourcc based on alpha offset.\n// Returns FOURCC_ARGB, FOURCC_BGRA, or 0 if unknown.\nLIBYUV_API\nuint32 ARGBDetect(const uint8* argb, int stride_argb, int width, int height);\n\n// Sum Square Error - used to compute Mean Square Error or PSNR.\nLIBYUV_API\nuint64 ComputeSumSquareError(const uint8* src_a,\n                             const uint8* src_b, int count);\n\nLIBYUV_API\nuint64 ComputeSumSquareErrorPlane(const uint8* src_a, int stride_a,\n                                  const uint8* src_b, int stride_b,\n                                  int width, int height);\n\nstatic const int kMaxPsnr = 128;\n\nLIBYUV_API\ndouble SumSquareErrorToPsnr(uint64 sse, uint64 count);\n\nLIBYUV_API\ndouble CalcFramePsnr(const uint8* src_a, int stride_a,\n                     const uint8* src_b, int stride_b,\n                     int width, int height);\n\nLIBYUV_API\ndouble I420Psnr(const uint8* src_y_a, int stride_y_a,\n                const uint8* src_u_a, int stride_u_a,\n                const uint8* src_v_a, int stride_v_a,\n                const uint8* src_y_b, int stride_y_b,\n                const uint8* src_u_b, int stride_u_b,\n                const uint8* src_v_b, int stride_v_b,\n                int width, int height);\n\nLIBYUV_API\ndouble CalcFrameSsim(const uint8* src_a, int stride_a,\n                     const uint8* src_b, int stride_b,\n                     int width, int height);\n\nLIBYUV_API\ndouble I420Ssim(const uint8* src_y_a, int stride_y_a,\n                const uint8* src_u_a, int stride_u_a,\n                const uint8* src_v_a, int stride_v_a,\n                const uint8* src_y_b, int stride_y_b,\n                const uint8* src_u_b, int stride_u_b,\n                const uint8* src_v_b, int stride_v_b,\n                int width, int height);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_COMPARE_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/compare_row.h",
    "content": "/*\n *  Copyright 2013 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_COMPARE_ROW_H_\n#define INCLUDE_LIBYUV_COMPARE_ROW_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n#if defined(__pnacl__) || defined(__CLR_VER) || \\\n    (defined(__i386__) && !defined(__SSE2__))\n#define LIBYUV_DISABLE_X86\n#endif\n// MemorySanitizer does not support assembly code yet. http://crbug.com/344505\n#if defined(__has_feature)\n#if __has_feature(memory_sanitizer)\n#define LIBYUV_DISABLE_X86\n#endif\n#endif\n\n// Visual C 2012 required for AVX2.\n#if defined(_M_IX86) && !defined(__clang__) && \\\n    defined(_MSC_VER) && _MSC_VER >= 1700\n#define VISUALC_HAS_AVX2 1\n#endif  // VisualStudio >= 2012\n\n// clang >= 3.4.0 required for AVX2.\n#if defined(__clang__) && (defined(__x86_64__) || defined(__i386__))\n#if (__clang_major__ > 3) || (__clang_major__ == 3 && (__clang_minor__ >= 4))\n#define CLANG_HAS_AVX2 1\n#endif  // clang >= 3.4\n#endif  // __clang__\n\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    defined(_M_IX86) && (defined(VISUALC_HAS_AVX2) || defined(CLANG_HAS_AVX2))\n#define HAS_HASHDJB2_AVX2\n#endif\n\n// The following are available for Visual C and GCC:\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    (defined(__x86_64__) || (defined(__i386__) || defined(_M_IX86)))\n#define HAS_HASHDJB2_SSE41\n#define HAS_SUMSQUAREERROR_SSE2\n#endif\n\n// The following are available for Visual C and clangcl 32 bit:\n#if !defined(LIBYUV_DISABLE_X86) && defined(_M_IX86) && \\\n    (defined(VISUALC_HAS_AVX2) || defined(CLANG_HAS_AVX2))\n#define HAS_HASHDJB2_AVX2\n#define HAS_SUMSQUAREERROR_AVX2\n#endif\n\n// The following are available for Neon:\n#if !defined(LIBYUV_DISABLE_NEON) && \\\n    (defined(__ARM_NEON__) || defined(LIBYUV_NEON) || defined(__aarch64__))\n#define HAS_SUMSQUAREERROR_NEON\n#endif\n\nuint32 SumSquareError_C(const uint8* src_a, const uint8* src_b, int count);\nuint32 SumSquareError_SSE2(const uint8* src_a, const uint8* src_b, int count);\nuint32 SumSquareError_AVX2(const uint8* src_a, const uint8* src_b, int count);\nuint32 SumSquareError_NEON(const uint8* src_a, const uint8* src_b, int count);\n\nuint32 HashDjb2_C(const uint8* src, int count, uint32 seed);\nuint32 HashDjb2_SSE41(const uint8* src, int count, uint32 seed);\nuint32 HashDjb2_AVX2(const uint8* src, int count, uint32 seed);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_COMPARE_ROW_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/convert.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_CONVERT_H_\n#define INCLUDE_LIBYUV_CONVERT_H_\n\n#include \"libyuv/basic_types.h\"\n\n#include \"libyuv/rotate.h\"  // For enum RotationMode.\n\n// TODO(fbarchard): fix WebRTC source to include following libyuv headers:\n#include \"libyuv/convert_argb.h\"  // For WebRTC I420ToARGB. b/620\n#include \"libyuv/convert_from.h\"  // For WebRTC ConvertFromI420. b/620\n#include \"libyuv/planar_functions.h\"  // For WebRTC I420Rect, CopyPlane. b/618\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Convert I444 to I420.\nLIBYUV_API\nint I444ToI420(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert I422 to I420.\nLIBYUV_API\nint I422ToI420(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert I411 to I420.\nLIBYUV_API\nint I411ToI420(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Copy I420 to I420.\n#define I420ToI420 I420Copy\nLIBYUV_API\nint I420Copy(const uint8* src_y, int src_stride_y,\n             const uint8* src_u, int src_stride_u,\n             const uint8* src_v, int src_stride_v,\n             uint8* dst_y, int dst_stride_y,\n             uint8* dst_u, int dst_stride_u,\n             uint8* dst_v, int dst_stride_v,\n             int width, int height);\n\n// Convert I400 (grey) to I420.\nLIBYUV_API\nint I400ToI420(const uint8* src_y, int src_stride_y,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n#define J400ToJ420 I400ToI420\n\n// Convert NV12 to I420.\nLIBYUV_API\nint NV12ToI420(const uint8* src_y, int src_stride_y,\n               const uint8* src_uv, int src_stride_uv,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert NV21 to I420.\nLIBYUV_API\nint NV21ToI420(const uint8* src_y, int src_stride_y,\n               const uint8* src_vu, int src_stride_vu,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert YUY2 to I420.\nLIBYUV_API\nint YUY2ToI420(const uint8* src_yuy2, int src_stride_yuy2,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert UYVY to I420.\nLIBYUV_API\nint UYVYToI420(const uint8* src_uyvy, int src_stride_uyvy,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert M420 to I420.\nLIBYUV_API\nint M420ToI420(const uint8* src_m420, int src_stride_m420,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert Android420 to I420.\nLIBYUV_API\nint Android420ToI420(const uint8* src_y, int src_stride_y,\n                     const uint8* src_u, int src_stride_u,\n                     const uint8* src_v, int src_stride_v,\n                     int pixel_stride_uv,\n                     uint8* dst_y, int dst_stride_y,\n                     uint8* dst_u, int dst_stride_u,\n                     uint8* dst_v, int dst_stride_v,\n                     int width, int height);\n\n// ARGB little endian (bgra in memory) to I420.\nLIBYUV_API\nint ARGBToI420(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// BGRA little endian (argb in memory) to I420.\nLIBYUV_API\nint BGRAToI420(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// ABGR little endian (rgba in memory) to I420.\nLIBYUV_API\nint ABGRToI420(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// RGBA little endian (abgr in memory) to I420.\nLIBYUV_API\nint RGBAToI420(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// RGB little endian (bgr in memory) to I420.\nLIBYUV_API\nint RGB24ToI420(const uint8* src_frame, int src_stride_frame,\n                uint8* dst_y, int dst_stride_y,\n                uint8* dst_u, int dst_stride_u,\n                uint8* dst_v, int dst_stride_v,\n                int width, int height);\n\n// RGB big endian (rgb in memory) to I420.\nLIBYUV_API\nint RAWToI420(const uint8* src_frame, int src_stride_frame,\n              uint8* dst_y, int dst_stride_y,\n              uint8* dst_u, int dst_stride_u,\n              uint8* dst_v, int dst_stride_v,\n              int width, int height);\n\n// RGB16 (RGBP fourcc) little endian to I420.\nLIBYUV_API\nint RGB565ToI420(const uint8* src_frame, int src_stride_frame,\n                 uint8* dst_y, int dst_stride_y,\n                 uint8* dst_u, int dst_stride_u,\n                 uint8* dst_v, int dst_stride_v,\n                 int width, int height);\n\n// RGB15 (RGBO fourcc) little endian to I420.\nLIBYUV_API\nint ARGB1555ToI420(const uint8* src_frame, int src_stride_frame,\n                   uint8* dst_y, int dst_stride_y,\n                   uint8* dst_u, int dst_stride_u,\n                   uint8* dst_v, int dst_stride_v,\n                   int width, int height);\n\n// RGB12 (R444 fourcc) little endian to I420.\nLIBYUV_API\nint ARGB4444ToI420(const uint8* src_frame, int src_stride_frame,\n                   uint8* dst_y, int dst_stride_y,\n                   uint8* dst_u, int dst_stride_u,\n                   uint8* dst_v, int dst_stride_v,\n                   int width, int height);\n\n#ifdef HAVE_JPEG\n// src_width/height provided by capture.\n// dst_width/height for clipping determine final size.\nLIBYUV_API\nint MJPGToI420(const uint8* sample, size_t sample_size,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int src_width, int src_height,\n               int dst_width, int dst_height);\n\n// Query size of MJPG in pixels.\nLIBYUV_API\nint MJPGSize(const uint8* sample, size_t sample_size,\n             int* width, int* height);\n#endif\n\n// Convert camera sample to I420 with cropping, rotation and vertical flip.\n// \"src_size\" is needed to parse MJPG.\n// \"dst_stride_y\" number of bytes in a row of the dst_y plane.\n//   Normally this would be the same as dst_width, with recommended alignment\n//   to 16 bytes for better efficiency.\n//   If rotation of 90 or 270 is used, stride is affected. The caller should\n//   allocate the I420 buffer according to rotation.\n// \"dst_stride_u\" number of bytes in a row of the dst_u plane.\n//   Normally this would be the same as (dst_width + 1) / 2, with\n//   recommended alignment to 16 bytes for better efficiency.\n//   If rotation of 90 or 270 is used, stride is affected.\n// \"crop_x\" and \"crop_y\" are starting position for cropping.\n//   To center, crop_x = (src_width - dst_width) / 2\n//              crop_y = (src_height - dst_height) / 2\n// \"src_width\" / \"src_height\" is size of src_frame in pixels.\n//   \"src_height\" can be negative indicating a vertically flipped image source.\n// \"crop_width\" / \"crop_height\" is the size to crop the src to.\n//    Must be less than or equal to src_width/src_height\n//    Cropping parameters are pre-rotation.\n// \"rotation\" can be 0, 90, 180 or 270.\n// \"format\" is a fourcc. ie 'I420', 'YUY2'\n// Returns 0 for successful; -1 for invalid parameter. Non-zero for failure.\nLIBYUV_API\nint ConvertToI420(const uint8* src_frame, size_t src_size,\n                  uint8* dst_y, int dst_stride_y,\n                  uint8* dst_u, int dst_stride_u,\n                  uint8* dst_v, int dst_stride_v,\n                  int crop_x, int crop_y,\n                  int src_width, int src_height,\n                  int crop_width, int crop_height,\n                  enum RotationMode rotation,\n                  uint32 format);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_CONVERT_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/convert_argb.h",
    "content": "/*\n *  Copyright 2012 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_CONVERT_ARGB_H_\n#define INCLUDE_LIBYUV_CONVERT_ARGB_H_\n\n#include \"libyuv/basic_types.h\"\n\n#include \"libyuv/rotate.h\"  // For enum RotationMode.\n\n// TODO(fbarchard): This set of functions should exactly match convert.h\n// TODO(fbarchard): Add tests. Create random content of right size and convert\n// with C vs Opt and or to I420 and compare.\n// TODO(fbarchard): Some of these functions lack parameter setting.\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Alias.\n#define ARGBToARGB ARGBCopy\n\n// Copy ARGB to ARGB.\nLIBYUV_API\nint ARGBCopy(const uint8* src_argb, int src_stride_argb,\n             uint8* dst_argb, int dst_stride_argb,\n             int width, int height);\n\n// Convert I420 to ARGB.\nLIBYUV_API\nint I420ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Duplicate prototype for function in convert_from.h for remoting.\nLIBYUV_API\nint I420ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert I422 to ARGB.\nLIBYUV_API\nint I422ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert I444 to ARGB.\nLIBYUV_API\nint I444ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert J444 to ARGB.\nLIBYUV_API\nint J444ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert I444 to ABGR.\nLIBYUV_API\nint I444ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// Convert I411 to ARGB.\nLIBYUV_API\nint I411ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert I420 with Alpha to preattenuated ARGB.\nLIBYUV_API\nint I420AlphaToARGB(const uint8* src_y, int src_stride_y,\n                    const uint8* src_u, int src_stride_u,\n                    const uint8* src_v, int src_stride_v,\n                    const uint8* src_a, int src_stride_a,\n                    uint8* dst_argb, int dst_stride_argb,\n                    int width, int height, int attenuate);\n\n// Convert I420 with Alpha to preattenuated ABGR.\nLIBYUV_API\nint I420AlphaToABGR(const uint8* src_y, int src_stride_y,\n                    const uint8* src_u, int src_stride_u,\n                    const uint8* src_v, int src_stride_v,\n                    const uint8* src_a, int src_stride_a,\n                    uint8* dst_abgr, int dst_stride_abgr,\n                    int width, int height, int attenuate);\n\n// Convert I400 (grey) to ARGB.  Reverse of ARGBToI400.\nLIBYUV_API\nint I400ToARGB(const uint8* src_y, int src_stride_y,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert J400 (jpeg grey) to ARGB.\nLIBYUV_API\nint J400ToARGB(const uint8* src_y, int src_stride_y,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Alias.\n#define YToARGB I400ToARGB\n\n// Convert NV12 to ARGB.\nLIBYUV_API\nint NV12ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_uv, int src_stride_uv,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert NV21 to ARGB.\nLIBYUV_API\nint NV21ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_vu, int src_stride_vu,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert M420 to ARGB.\nLIBYUV_API\nint M420ToARGB(const uint8* src_m420, int src_stride_m420,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert YUY2 to ARGB.\nLIBYUV_API\nint YUY2ToARGB(const uint8* src_yuy2, int src_stride_yuy2,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert UYVY to ARGB.\nLIBYUV_API\nint UYVYToARGB(const uint8* src_uyvy, int src_stride_uyvy,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert J420 to ARGB.\nLIBYUV_API\nint J420ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert J422 to ARGB.\nLIBYUV_API\nint J422ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert J420 to ABGR.\nLIBYUV_API\nint J420ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// Convert J422 to ABGR.\nLIBYUV_API\nint J422ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// Convert H420 to ARGB.\nLIBYUV_API\nint H420ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert H422 to ARGB.\nLIBYUV_API\nint H422ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert H420 to ABGR.\nLIBYUV_API\nint H420ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// Convert H422 to ABGR.\nLIBYUV_API\nint H422ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// BGRA little endian (argb in memory) to ARGB.\nLIBYUV_API\nint BGRAToARGB(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// ABGR little endian (rgba in memory) to ARGB.\nLIBYUV_API\nint ABGRToARGB(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// RGBA little endian (abgr in memory) to ARGB.\nLIBYUV_API\nint RGBAToARGB(const uint8* src_frame, int src_stride_frame,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Deprecated function name.\n#define BG24ToARGB RGB24ToARGB\n\n// RGB little endian (bgr in memory) to ARGB.\nLIBYUV_API\nint RGB24ToARGB(const uint8* src_frame, int src_stride_frame,\n                uint8* dst_argb, int dst_stride_argb,\n                int width, int height);\n\n// RGB big endian (rgb in memory) to ARGB.\nLIBYUV_API\nint RAWToARGB(const uint8* src_frame, int src_stride_frame,\n              uint8* dst_argb, int dst_stride_argb,\n              int width, int height);\n\n// RGB16 (RGBP fourcc) little endian to ARGB.\nLIBYUV_API\nint RGB565ToARGB(const uint8* src_frame, int src_stride_frame,\n                 uint8* dst_argb, int dst_stride_argb,\n                 int width, int height);\n\n// RGB15 (RGBO fourcc) little endian to ARGB.\nLIBYUV_API\nint ARGB1555ToARGB(const uint8* src_frame, int src_stride_frame,\n                   uint8* dst_argb, int dst_stride_argb,\n                   int width, int height);\n\n// RGB12 (R444 fourcc) little endian to ARGB.\nLIBYUV_API\nint ARGB4444ToARGB(const uint8* src_frame, int src_stride_frame,\n                   uint8* dst_argb, int dst_stride_argb,\n                   int width, int height);\n\n#ifdef HAVE_JPEG\n// src_width/height provided by capture\n// dst_width/height for clipping determine final size.\nLIBYUV_API\nint MJPGToARGB(const uint8* sample, size_t sample_size,\n               uint8* dst_argb, int dst_stride_argb,\n               int src_width, int src_height,\n               int dst_width, int dst_height);\n#endif\n\n// Convert camera sample to ARGB with cropping, rotation and vertical flip.\n// \"src_size\" is needed to parse MJPG.\n// \"dst_stride_argb\" number of bytes in a row of the dst_argb plane.\n//   Normally this would be the same as dst_width, with recommended alignment\n//   to 16 bytes for better efficiency.\n//   If rotation of 90 or 270 is used, stride is affected. The caller should\n//   allocate the I420 buffer according to rotation.\n// \"dst_stride_u\" number of bytes in a row of the dst_u plane.\n//   Normally this would be the same as (dst_width + 1) / 2, with\n//   recommended alignment to 16 bytes for better efficiency.\n//   If rotation of 90 or 270 is used, stride is affected.\n// \"crop_x\" and \"crop_y\" are starting position for cropping.\n//   To center, crop_x = (src_width - dst_width) / 2\n//              crop_y = (src_height - dst_height) / 2\n// \"src_width\" / \"src_height\" is size of src_frame in pixels.\n//   \"src_height\" can be negative indicating a vertically flipped image source.\n// \"crop_width\" / \"crop_height\" is the size to crop the src to.\n//    Must be less than or equal to src_width/src_height\n//    Cropping parameters are pre-rotation.\n// \"rotation\" can be 0, 90, 180 or 270.\n// \"format\" is a fourcc. ie 'I420', 'YUY2'\n// Returns 0 for successful; -1 for invalid parameter. Non-zero for failure.\nLIBYUV_API\nint ConvertToARGB(const uint8* src_frame, size_t src_size,\n                  uint8* dst_argb, int dst_stride_argb,\n                  int crop_x, int crop_y,\n                  int src_width, int src_height,\n                  int crop_width, int crop_height,\n                  enum RotationMode rotation,\n                  uint32 format);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_CONVERT_ARGB_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/convert_from.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_CONVERT_FROM_H_\n#define INCLUDE_LIBYUV_CONVERT_FROM_H_\n\n#include \"libyuv/basic_types.h\"\n#include \"libyuv/rotate.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// See Also convert.h for conversions from formats to I420.\n\n// I420Copy in convert to I420ToI420.\n\nLIBYUV_API\nint I420ToI422(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\nLIBYUV_API\nint I420ToI444(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\nLIBYUV_API\nint I420ToI411(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Copy to I400. Source can be I420, I422, I444, I400, NV12 or NV21.\nLIBYUV_API\nint I400Copy(const uint8* src_y, int src_stride_y,\n             uint8* dst_y, int dst_stride_y,\n             int width, int height);\n\nLIBYUV_API\nint I420ToNV12(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_uv, int dst_stride_uv,\n               int width, int height);\n\nLIBYUV_API\nint I420ToNV21(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_vu, int dst_stride_vu,\n               int width, int height);\n\nLIBYUV_API\nint I420ToYUY2(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_frame, int dst_stride_frame,\n               int width, int height);\n\nLIBYUV_API\nint I420ToUYVY(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_frame, int dst_stride_frame,\n               int width, int height);\n\nLIBYUV_API\nint I420ToARGB(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\nLIBYUV_API\nint I420ToBGRA(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\nLIBYUV_API\nint I420ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\nLIBYUV_API\nint I420ToRGBA(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_rgba, int dst_stride_rgba,\n               int width, int height);\n\nLIBYUV_API\nint I420ToRGB24(const uint8* src_y, int src_stride_y,\n                const uint8* src_u, int src_stride_u,\n                const uint8* src_v, int src_stride_v,\n                uint8* dst_frame, int dst_stride_frame,\n                int width, int height);\n\nLIBYUV_API\nint I420ToRAW(const uint8* src_y, int src_stride_y,\n              const uint8* src_u, int src_stride_u,\n              const uint8* src_v, int src_stride_v,\n              uint8* dst_frame, int dst_stride_frame,\n              int width, int height);\n\nLIBYUV_API\nint I420ToRGB565(const uint8* src_y, int src_stride_y,\n                 const uint8* src_u, int src_stride_u,\n                 const uint8* src_v, int src_stride_v,\n                 uint8* dst_frame, int dst_stride_frame,\n                 int width, int height);\n\n// Convert I420 To RGB565 with 4x4 dither matrix (16 bytes).\n// Values in dither matrix from 0 to 7 recommended.\n// The order of the dither matrix is first byte is upper left.\n\nLIBYUV_API\nint I420ToRGB565Dither(const uint8* src_y, int src_stride_y,\n                       const uint8* src_u, int src_stride_u,\n                       const uint8* src_v, int src_stride_v,\n                       uint8* dst_frame, int dst_stride_frame,\n                       const uint8* dither4x4, int width, int height);\n\nLIBYUV_API\nint I420ToARGB1555(const uint8* src_y, int src_stride_y,\n                   const uint8* src_u, int src_stride_u,\n                   const uint8* src_v, int src_stride_v,\n                   uint8* dst_frame, int dst_stride_frame,\n                   int width, int height);\n\nLIBYUV_API\nint I420ToARGB4444(const uint8* src_y, int src_stride_y,\n                   const uint8* src_u, int src_stride_u,\n                   const uint8* src_v, int src_stride_v,\n                   uint8* dst_frame, int dst_stride_frame,\n                   int width, int height);\n\n// Convert I420 to specified format.\n// \"dst_sample_stride\" is bytes in a row for the destination. Pass 0 if the\n//    buffer has contiguous rows. Can be negative. A multiple of 16 is optimal.\nLIBYUV_API\nint ConvertFromI420(const uint8* y, int y_stride,\n                    const uint8* u, int u_stride,\n                    const uint8* v, int v_stride,\n                    uint8* dst_sample, int dst_sample_stride,\n                    int width, int height,\n                    uint32 format);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_CONVERT_FROM_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/convert_from_argb.h",
    "content": "/*\n *  Copyright 2012 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_CONVERT_FROM_ARGB_H_\n#define INCLUDE_LIBYUV_CONVERT_FROM_ARGB_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Copy ARGB to ARGB.\n#define ARGBToARGB ARGBCopy\nLIBYUV_API\nint ARGBCopy(const uint8* src_argb, int src_stride_argb,\n             uint8* dst_argb, int dst_stride_argb,\n             int width, int height);\n\n// Convert ARGB To BGRA.\nLIBYUV_API\nint ARGBToBGRA(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_bgra, int dst_stride_bgra,\n               int width, int height);\n\n// Convert ARGB To ABGR.\nLIBYUV_API\nint ARGBToABGR(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// Convert ARGB To RGBA.\nLIBYUV_API\nint ARGBToRGBA(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_rgba, int dst_stride_rgba,\n               int width, int height);\n\n// Convert ARGB To RGB24.\nLIBYUV_API\nint ARGBToRGB24(const uint8* src_argb, int src_stride_argb,\n                uint8* dst_rgb24, int dst_stride_rgb24,\n                int width, int height);\n\n// Convert ARGB To RAW.\nLIBYUV_API\nint ARGBToRAW(const uint8* src_argb, int src_stride_argb,\n              uint8* dst_rgb, int dst_stride_rgb,\n              int width, int height);\n\n// Convert ARGB To RGB565.\nLIBYUV_API\nint ARGBToRGB565(const uint8* src_argb, int src_stride_argb,\n                 uint8* dst_rgb565, int dst_stride_rgb565,\n                 int width, int height);\n\n// Convert ARGB To RGB565 with 4x4 dither matrix (16 bytes).\n// Values in dither matrix from 0 to 7 recommended.\n// The order of the dither matrix is first byte is upper left.\n// TODO(fbarchard): Consider pointer to 2d array for dither4x4.\n// const uint8(*dither)[4][4];\nLIBYUV_API\nint ARGBToRGB565Dither(const uint8* src_argb, int src_stride_argb,\n                       uint8* dst_rgb565, int dst_stride_rgb565,\n                       const uint8* dither4x4, int width, int height);\n\n// Convert ARGB To ARGB1555.\nLIBYUV_API\nint ARGBToARGB1555(const uint8* src_argb, int src_stride_argb,\n                   uint8* dst_argb1555, int dst_stride_argb1555,\n                   int width, int height);\n\n// Convert ARGB To ARGB4444.\nLIBYUV_API\nint ARGBToARGB4444(const uint8* src_argb, int src_stride_argb,\n                   uint8* dst_argb4444, int dst_stride_argb4444,\n                   int width, int height);\n\n// Convert ARGB To I444.\nLIBYUV_API\nint ARGBToI444(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert ARGB To I422.\nLIBYUV_API\nint ARGBToI422(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert ARGB To I420. (also in convert.h)\nLIBYUV_API\nint ARGBToI420(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert ARGB to J420. (JPeg full range I420).\nLIBYUV_API\nint ARGBToJ420(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_yj, int dst_stride_yj,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert ARGB to J422.\nLIBYUV_API\nint ARGBToJ422(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_yj, int dst_stride_yj,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert ARGB To I411.\nLIBYUV_API\nint ARGBToI411(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert ARGB to J400. (JPeg full range).\nLIBYUV_API\nint ARGBToJ400(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_yj, int dst_stride_yj,\n               int width, int height);\n\n// Convert ARGB to I400.\nLIBYUV_API\nint ARGBToI400(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               int width, int height);\n\n// Convert ARGB to G. (Reverse of J400toARGB, which replicates G back to ARGB)\nLIBYUV_API\nint ARGBToG(const uint8* src_argb, int src_stride_argb,\n            uint8* dst_g, int dst_stride_g,\n            int width, int height);\n\n// Convert ARGB To NV12.\nLIBYUV_API\nint ARGBToNV12(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_uv, int dst_stride_uv,\n               int width, int height);\n\n// Convert ARGB To NV21.\nLIBYUV_API\nint ARGBToNV21(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_vu, int dst_stride_vu,\n               int width, int height);\n\n// Convert ARGB To NV21.\nLIBYUV_API\nint ARGBToNV21(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_vu, int dst_stride_vu,\n               int width, int height);\n\n// Convert ARGB To YUY2.\nLIBYUV_API\nint ARGBToYUY2(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_yuy2, int dst_stride_yuy2,\n               int width, int height);\n\n// Convert ARGB To UYVY.\nLIBYUV_API\nint ARGBToUYVY(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_uyvy, int dst_stride_uyvy,\n               int width, int height);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_CONVERT_FROM_ARGB_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/cpu_id.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_CPU_ID_H_\n#define INCLUDE_LIBYUV_CPU_ID_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Internal flag to indicate cpuid requires initialization.\nstatic const int kCpuInitialized = 0x1;\n\n// These flags are only valid on ARM processors.\nstatic const int kCpuHasARM = 0x2;\nstatic const int kCpuHasNEON = 0x4;\n// 0x8 reserved for future ARM flag.\n\n// These flags are only valid on x86 processors.\nstatic const int kCpuHasX86 = 0x10;\nstatic const int kCpuHasSSE2 = 0x20;\nstatic const int kCpuHasSSSE3 = 0x40;\nstatic const int kCpuHasSSE41 = 0x80;\nstatic const int kCpuHasSSE42 = 0x100;\nstatic const int kCpuHasAVX = 0x200;\nstatic const int kCpuHasAVX2 = 0x400;\nstatic const int kCpuHasERMS = 0x800;\nstatic const int kCpuHasFMA3 = 0x1000;\nstatic const int kCpuHasAVX3 = 0x2000;\n// 0x2000, 0x4000, 0x8000 reserved for future X86 flags.\n\n// These flags are only valid on MIPS processors.\nstatic const int kCpuHasMIPS = 0x10000;\nstatic const int kCpuHasDSPR2 = 0x20000;\nstatic const int kCpuHasMSA = 0x40000;\n\n// Internal function used to auto-init.\nLIBYUV_API\nint InitCpuFlags(void);\n\n// Internal function for parsing /proc/cpuinfo.\nLIBYUV_API\nint ArmCpuCaps(const char* cpuinfo_name);\n\n// Detect CPU has SSE2 etc.\n// Test_flag parameter should be one of kCpuHas constants above.\n// returns non-zero if instruction set is detected\nstatic __inline int TestCpuFlag(int test_flag) {\n  LIBYUV_API extern int cpu_info_;\n  return (!cpu_info_ ? InitCpuFlags() : cpu_info_) & test_flag;\n}\n\n// For testing, allow CPU flags to be disabled.\n// ie MaskCpuFlags(~kCpuHasSSSE3) to disable SSSE3.\n// MaskCpuFlags(-1) to enable all cpu specific optimizations.\n// MaskCpuFlags(1) to disable all cpu specific optimizations.\nLIBYUV_API\nvoid MaskCpuFlags(int enable_flags);\n\n// Low level cpuid for X86. Returns zeros on other CPUs.\n// eax is the info type that you want.\n// ecx is typically the cpu number, and should normally be zero.\nLIBYUV_API\nvoid CpuId(uint32 eax, uint32 ecx, uint32* cpu_info);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_CPU_ID_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/macros_msa.h",
    "content": "/*\n *  Copyright 2016 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_MACROS_MSA_H_\n#define INCLUDE_LIBYUV_MACROS_MSA_H_\n\n#if !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa)\n#include <stdint.h>\n#include <msa.h>\n\n#define LD_B(RTYPE, psrc) *((RTYPE*)(psrc))   /* NOLINT */\n#define LD_UB(...) LD_B(v16u8, __VA_ARGS__)\n\n#define ST_B(RTYPE, in, pdst) *((RTYPE*)(pdst)) = (in)  /* NOLINT */\n#define ST_UB(...) ST_B(v16u8, __VA_ARGS__)\n\n/* Description : Load two vectors with 16 'byte' sized elements\n   Arguments   : Inputs  - psrc, stride\n                 Outputs - out0, out1\n                 Return Type - as per RTYPE\n   Details     : Load 16 byte elements in 'out0' from (psrc)\n                 Load 16 byte elements in 'out1' from (psrc + stride)\n*/\n#define LD_B2(RTYPE, psrc, stride, out0, out1) {  \\\n  out0 = LD_B(RTYPE, (psrc));                     \\\n  out1 = LD_B(RTYPE, (psrc) + stride);            \\\n}\n#define LD_UB2(...) LD_B2(v16u8, __VA_ARGS__)\n\n#define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) {  \\\n  LD_B2(RTYPE, (psrc), stride, out0, out1);                   \\\n  LD_B2(RTYPE, (psrc) + 2 * stride , stride, out2, out3);     \\\n}\n#define LD_UB4(...) LD_B4(v16u8, __VA_ARGS__)\n\n/* Description : Store two vectors with stride each having 16 'byte' sized\n                 elements\n   Arguments   : Inputs - in0, in1, pdst, stride\n   Details     : Store 16 byte elements from 'in0' to (pdst)\n                 Store 16 byte elements from 'in1' to (pdst + stride)\n*/\n#define ST_B2(RTYPE, in0, in1, pdst, stride) {  \\\n  ST_B(RTYPE, in0, (pdst));                     \\\n  ST_B(RTYPE, in1, (pdst) + stride);            \\\n}\n#define ST_UB2(...) ST_B2(v16u8, __VA_ARGS__)\n#\n#define ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride) {  \\\n  ST_B2(RTYPE, in0, in1, (pdst), stride);                 \\\n  ST_B2(RTYPE, in2, in3, (pdst) + 2 * stride, stride);    \\\n}\n#define ST_UB4(...) ST_B4(v16u8, __VA_ARGS__)\n#\n/* Description : Shuffle byte vector elements as per mask vector\n   Arguments   : Inputs  - in0, in1, in2, in3, mask0, mask1\n                 Outputs - out0, out1\n                 Return Type - as per RTYPE\n   Details     : Byte elements from 'in0' & 'in1' are copied selectively to\n                 'out0' as per control vector 'mask0'\n*/\n#define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) {   \\\n  out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0);  \\\n  out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2);  \\\n}\n#define VSHF_B2_UB(...) VSHF_B2(v16u8, __VA_ARGS__)\n\n#endif  /* !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa) */\n\n#endif  // INCLUDE_LIBYUV_MACROS_MSA_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/mjpeg_decoder.h",
    "content": "/*\n *  Copyright 2012 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_MJPEG_DECODER_H_\n#define INCLUDE_LIBYUV_MJPEG_DECODER_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\n// NOTE: For a simplified public API use convert.h MJPGToI420().\n\nstruct jpeg_common_struct;\nstruct jpeg_decompress_struct;\nstruct jpeg_source_mgr;\n\nnamespace libyuv {\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nLIBYUV_BOOL ValidateJpeg(const uint8* sample, size_t sample_size);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n#endif\n\nstatic const uint32 kUnknownDataSize = 0xFFFFFFFF;\n\nenum JpegSubsamplingType {\n  kJpegYuv420,\n  kJpegYuv422,\n  kJpegYuv411,\n  kJpegYuv444,\n  kJpegYuv400,\n  kJpegUnknown\n};\n\nstruct Buffer {\n  const uint8* data;\n  int len;\n};\n\nstruct BufferVector {\n  Buffer* buffers;\n  int len;\n  int pos;\n};\n\nstruct SetJmpErrorMgr;\n\n// MJPEG (\"Motion JPEG\") is a pseudo-standard video codec where the frames are\n// simply independent JPEG images with a fixed huffman table (which is omitted).\n// It is rarely used in video transmission, but is common as a camera capture\n// format, especially in Logitech devices. This class implements a decoder for\n// MJPEG frames.\n//\n// See http://tools.ietf.org/html/rfc2435\nclass LIBYUV_API MJpegDecoder {\n public:\n  typedef void (*CallbackFunction)(void* opaque,\n                                   const uint8* const* data,\n                                   const int* strides,\n                                   int rows);\n\n  static const int kColorSpaceUnknown;\n  static const int kColorSpaceGrayscale;\n  static const int kColorSpaceRgb;\n  static const int kColorSpaceYCbCr;\n  static const int kColorSpaceCMYK;\n  static const int kColorSpaceYCCK;\n\n  MJpegDecoder();\n  ~MJpegDecoder();\n\n  // Loads a new frame, reads its headers, and determines the uncompressed\n  // image format.\n  // Returns LIBYUV_TRUE if image looks valid and format is supported.\n  // If return value is LIBYUV_TRUE, then the values for all the following\n  // getters are populated.\n  // src_len is the size of the compressed mjpeg frame in bytes.\n  LIBYUV_BOOL LoadFrame(const uint8* src, size_t src_len);\n\n  // Returns width of the last loaded frame in pixels.\n  int GetWidth();\n\n  // Returns height of the last loaded frame in pixels.\n  int GetHeight();\n\n  // Returns format of the last loaded frame. The return value is one of the\n  // kColorSpace* constants.\n  int GetColorSpace();\n\n  // Number of color components in the color space.\n  int GetNumComponents();\n\n  // Sample factors of the n-th component.\n  int GetHorizSampFactor(int component);\n\n  int GetVertSampFactor(int component);\n\n  int GetHorizSubSampFactor(int component);\n\n  int GetVertSubSampFactor(int component);\n\n  // Public for testability.\n  int GetImageScanlinesPerImcuRow();\n\n  // Public for testability.\n  int GetComponentScanlinesPerImcuRow(int component);\n\n  // Width of a component in bytes.\n  int GetComponentWidth(int component);\n\n  // Height of a component.\n  int GetComponentHeight(int component);\n\n  // Width of a component in bytes with padding for DCTSIZE. Public for testing.\n  int GetComponentStride(int component);\n\n  // Size of a component in bytes.\n  int GetComponentSize(int component);\n\n  // Call this after LoadFrame() if you decide you don't want to decode it\n  // after all.\n  LIBYUV_BOOL UnloadFrame();\n\n  // Decodes the entire image into a one-buffer-per-color-component format.\n  // dst_width must match exactly. dst_height must be <= to image height; if\n  // less, the image is cropped. \"planes\" must have size equal to at least\n  // GetNumComponents() and they must point to non-overlapping buffers of size\n  // at least GetComponentSize(i). The pointers in planes are incremented\n  // to point to after the end of the written data.\n  // TODO(fbarchard): Add dst_x, dst_y to allow specific rect to be decoded.\n  LIBYUV_BOOL DecodeToBuffers(uint8** planes, int dst_width, int dst_height);\n\n  // Decodes the entire image and passes the data via repeated calls to a\n  // callback function. Each call will get the data for a whole number of\n  // image scanlines.\n  // TODO(fbarchard): Add dst_x, dst_y to allow specific rect to be decoded.\n  LIBYUV_BOOL DecodeToCallback(CallbackFunction fn, void* opaque,\n                        int dst_width, int dst_height);\n\n  // The helper function which recognizes the jpeg sub-sampling type.\n  static JpegSubsamplingType JpegSubsamplingTypeHelper(\n     int* subsample_x, int* subsample_y, int number_of_components);\n\n private:\n  void AllocOutputBuffers(int num_outbufs);\n  void DestroyOutputBuffers();\n\n  LIBYUV_BOOL StartDecode();\n  LIBYUV_BOOL FinishDecode();\n\n  void SetScanlinePointers(uint8** data);\n  LIBYUV_BOOL DecodeImcuRow();\n\n  int GetComponentScanlinePadding(int component);\n\n  // A buffer holding the input data for a frame.\n  Buffer buf_;\n  BufferVector buf_vec_;\n\n  jpeg_decompress_struct* decompress_struct_;\n  jpeg_source_mgr* source_mgr_;\n  SetJmpErrorMgr* error_mgr_;\n\n  // LIBYUV_TRUE iff at least one component has scanline padding. (i.e.,\n  // GetComponentScanlinePadding() != 0.)\n  LIBYUV_BOOL has_scanline_padding_;\n\n  // Temporaries used to point to scanline outputs.\n  int num_outbufs_;  // Outermost size of all arrays below.\n  uint8*** scanlines_;\n  int* scanlines_sizes_;\n  // Temporary buffer used for decoding when we can't decode directly to the\n  // output buffers. Large enough for just one iMCU row.\n  uint8** databuf_;\n  int* databuf_strides_;\n};\n\n}  // namespace libyuv\n\n#endif  //  __cplusplus\n#endif  // INCLUDE_LIBYUV_MJPEG_DECODER_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/planar_functions.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_PLANAR_FUNCTIONS_H_\n#define INCLUDE_LIBYUV_PLANAR_FUNCTIONS_H_\n\n#include \"libyuv/basic_types.h\"\n\n// TODO(fbarchard): Remove the following headers includes.\n#include \"libyuv/convert.h\"\n#include \"libyuv/convert_argb.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Copy a plane of data.\nLIBYUV_API\nvoid CopyPlane(const uint8* src_y, int src_stride_y,\n               uint8* dst_y, int dst_stride_y,\n               int width, int height);\n\nLIBYUV_API\nvoid CopyPlane_16(const uint16* src_y, int src_stride_y,\n                  uint16* dst_y, int dst_stride_y,\n                  int width, int height);\n\n// Set a plane of data to a 32 bit value.\nLIBYUV_API\nvoid SetPlane(uint8* dst_y, int dst_stride_y,\n              int width, int height,\n              uint32 value);\n\n// Split interleaved UV plane into separate U and V planes.\nLIBYUV_API\nvoid SplitUVPlane(const uint8* src_uv, int src_stride_uv,\n                  uint8* dst_u, int dst_stride_u,\n                  uint8* dst_v, int dst_stride_v,\n                  int width, int height);\n\n// Merge separate U and V planes into one interleaved UV plane.\nLIBYUV_API\nvoid MergeUVPlane(const uint8* src_u, int src_stride_u,\n                  const uint8* src_v, int src_stride_v,\n                  uint8* dst_uv, int dst_stride_uv,\n                  int width, int height);\n\n// Copy I400.  Supports inverting.\nLIBYUV_API\nint I400ToI400(const uint8* src_y, int src_stride_y,\n               uint8* dst_y, int dst_stride_y,\n               int width, int height);\n\n#define J400ToJ400 I400ToI400\n\n// Copy I422 to I422.\n#define I422ToI422 I422Copy\nLIBYUV_API\nint I422Copy(const uint8* src_y, int src_stride_y,\n             const uint8* src_u, int src_stride_u,\n             const uint8* src_v, int src_stride_v,\n             uint8* dst_y, int dst_stride_y,\n             uint8* dst_u, int dst_stride_u,\n             uint8* dst_v, int dst_stride_v,\n             int width, int height);\n\n// Copy I444 to I444.\n#define I444ToI444 I444Copy\nLIBYUV_API\nint I444Copy(const uint8* src_y, int src_stride_y,\n             const uint8* src_u, int src_stride_u,\n             const uint8* src_v, int src_stride_v,\n             uint8* dst_y, int dst_stride_y,\n             uint8* dst_u, int dst_stride_u,\n             uint8* dst_v, int dst_stride_v,\n             int width, int height);\n\n// Convert YUY2 to I422.\nLIBYUV_API\nint YUY2ToI422(const uint8* src_yuy2, int src_stride_yuy2,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Convert UYVY to I422.\nLIBYUV_API\nint UYVYToI422(const uint8* src_uyvy, int src_stride_uyvy,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\nLIBYUV_API\nint YUY2ToNV12(const uint8* src_yuy2, int src_stride_yuy2,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_uv, int dst_stride_uv,\n               int width, int height);\n\nLIBYUV_API\nint UYVYToNV12(const uint8* src_uyvy, int src_stride_uyvy,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_uv, int dst_stride_uv,\n               int width, int height);\n\n// Convert I420 to I400. (calls CopyPlane ignoring u/v).\nLIBYUV_API\nint I420ToI400(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               int width, int height);\n\n// Alias\n#define J420ToJ400 I420ToI400\n#define I420ToI420Mirror I420Mirror\n\n// I420 mirror.\nLIBYUV_API\nint I420Mirror(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int width, int height);\n\n// Alias\n#define I400ToI400Mirror I400Mirror\n\n// I400 mirror.  A single plane is mirrored horizontally.\n// Pass negative height to achieve 180 degree rotation.\nLIBYUV_API\nint I400Mirror(const uint8* src_y, int src_stride_y,\n               uint8* dst_y, int dst_stride_y,\n               int width, int height);\n\n// Alias\n#define ARGBToARGBMirror ARGBMirror\n\n// ARGB mirror.\nLIBYUV_API\nint ARGBMirror(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Convert NV12 to RGB565.\nLIBYUV_API\nint NV12ToRGB565(const uint8* src_y, int src_stride_y,\n                 const uint8* src_uv, int src_stride_uv,\n                 uint8* dst_rgb565, int dst_stride_rgb565,\n                 int width, int height);\n\n// I422ToARGB is in convert_argb.h\n// Convert I422 to BGRA.\nLIBYUV_API\nint I422ToBGRA(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_bgra, int dst_stride_bgra,\n               int width, int height);\n\n// Convert I422 to ABGR.\nLIBYUV_API\nint I422ToABGR(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_abgr, int dst_stride_abgr,\n               int width, int height);\n\n// Convert I422 to RGBA.\nLIBYUV_API\nint I422ToRGBA(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_rgba, int dst_stride_rgba,\n               int width, int height);\n\n// Alias\n#define RGB24ToRAW RAWToRGB24\n\nLIBYUV_API\nint RAWToRGB24(const uint8* src_raw, int src_stride_raw,\n               uint8* dst_rgb24, int dst_stride_rgb24,\n               int width, int height);\n\n// Draw a rectangle into I420.\nLIBYUV_API\nint I420Rect(uint8* dst_y, int dst_stride_y,\n             uint8* dst_u, int dst_stride_u,\n             uint8* dst_v, int dst_stride_v,\n             int x, int y, int width, int height,\n             int value_y, int value_u, int value_v);\n\n// Draw a rectangle into ARGB.\nLIBYUV_API\nint ARGBRect(uint8* dst_argb, int dst_stride_argb,\n             int x, int y, int width, int height, uint32 value);\n\n// Convert ARGB to gray scale ARGB.\nLIBYUV_API\nint ARGBGrayTo(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_argb, int dst_stride_argb,\n               int width, int height);\n\n// Make a rectangle of ARGB gray scale.\nLIBYUV_API\nint ARGBGray(uint8* dst_argb, int dst_stride_argb,\n             int x, int y, int width, int height);\n\n// Make a rectangle of ARGB Sepia tone.\nLIBYUV_API\nint ARGBSepia(uint8* dst_argb, int dst_stride_argb,\n              int x, int y, int width, int height);\n\n// Apply a matrix rotation to each ARGB pixel.\n// matrix_argb is 4 signed ARGB values. -128 to 127 representing -2 to 2.\n// The first 4 coefficients apply to B, G, R, A and produce B of the output.\n// The next 4 coefficients apply to B, G, R, A and produce G of the output.\n// The next 4 coefficients apply to B, G, R, A and produce R of the output.\n// The last 4 coefficients apply to B, G, R, A and produce A of the output.\nLIBYUV_API\nint ARGBColorMatrix(const uint8* src_argb, int src_stride_argb,\n                    uint8* dst_argb, int dst_stride_argb,\n                    const int8* matrix_argb,\n                    int width, int height);\n\n// Deprecated. Use ARGBColorMatrix instead.\n// Apply a matrix rotation to each ARGB pixel.\n// matrix_argb is 3 signed ARGB values. -128 to 127 representing -1 to 1.\n// The first 4 coefficients apply to B, G, R, A and produce B of the output.\n// The next 4 coefficients apply to B, G, R, A and produce G of the output.\n// The last 4 coefficients apply to B, G, R, A and produce R of the output.\nLIBYUV_API\nint RGBColorMatrix(uint8* dst_argb, int dst_stride_argb,\n                   const int8* matrix_rgb,\n                   int x, int y, int width, int height);\n\n// Apply a color table each ARGB pixel.\n// Table contains 256 ARGB values.\nLIBYUV_API\nint ARGBColorTable(uint8* dst_argb, int dst_stride_argb,\n                   const uint8* table_argb,\n                   int x, int y, int width, int height);\n\n// Apply a color table each ARGB pixel but preserve destination alpha.\n// Table contains 256 ARGB values.\nLIBYUV_API\nint RGBColorTable(uint8* dst_argb, int dst_stride_argb,\n                  const uint8* table_argb,\n                  int x, int y, int width, int height);\n\n// Apply a luma/color table each ARGB pixel but preserve destination alpha.\n// Table contains 32768 values indexed by [Y][C] where 7 it 7 bit luma from\n// RGB (YJ style) and C is an 8 bit color component (R, G or B).\nLIBYUV_API\nint ARGBLumaColorTable(const uint8* src_argb, int src_stride_argb,\n                       uint8* dst_argb, int dst_stride_argb,\n                       const uint8* luma_rgb_table,\n                       int width, int height);\n\n// Apply a 3 term polynomial to ARGB values.\n// poly points to a 4x4 matrix.  The first row is constants.  The 2nd row is\n// coefficients for b, g, r and a.  The 3rd row is coefficients for b squared,\n// g squared, r squared and a squared.  The 4rd row is coefficients for b to\n// the 3, g to the 3, r to the 3 and a to the 3.  The values are summed and\n// result clamped to 0 to 255.\n// A polynomial approximation can be dirived using software such as 'R'.\n\nLIBYUV_API\nint ARGBPolynomial(const uint8* src_argb, int src_stride_argb,\n                   uint8* dst_argb, int dst_stride_argb,\n                   const float* poly,\n                   int width, int height);\n\n// Convert plane of 16 bit shorts to half floats.\n// Source values are multiplied by scale before storing as half float.\nLIBYUV_API\nint HalfFloatPlane(const uint16* src_y, int src_stride_y,\n                   uint16* dst_y, int dst_stride_y,\n                   float scale,\n                   int width, int height);\n\n// Quantize a rectangle of ARGB. Alpha unaffected.\n// scale is a 16 bit fractional fixed point scaler between 0 and 65535.\n// interval_size should be a value between 1 and 255.\n// interval_offset should be a value between 0 and 255.\nLIBYUV_API\nint ARGBQuantize(uint8* dst_argb, int dst_stride_argb,\n                 int scale, int interval_size, int interval_offset,\n                 int x, int y, int width, int height);\n\n// Copy ARGB to ARGB.\nLIBYUV_API\nint ARGBCopy(const uint8* src_argb, int src_stride_argb,\n             uint8* dst_argb, int dst_stride_argb,\n             int width, int height);\n\n// Copy Alpha channel of ARGB to alpha of ARGB.\nLIBYUV_API\nint ARGBCopyAlpha(const uint8* src_argb, int src_stride_argb,\n                  uint8* dst_argb, int dst_stride_argb,\n                  int width, int height);\n\n// Extract the alpha channel from ARGB.\nLIBYUV_API\nint ARGBExtractAlpha(const uint8* src_argb, int src_stride_argb,\n                     uint8* dst_a, int dst_stride_a,\n                     int width, int height);\n\n// Copy Y channel to Alpha of ARGB.\nLIBYUV_API\nint ARGBCopyYToAlpha(const uint8* src_y, int src_stride_y,\n                     uint8* dst_argb, int dst_stride_argb,\n                     int width, int height);\n\ntypedef void (*ARGBBlendRow)(const uint8* src_argb0, const uint8* src_argb1,\n                             uint8* dst_argb, int width);\n\n// Get function to Alpha Blend ARGB pixels and store to destination.\nLIBYUV_API\nARGBBlendRow GetARGBBlend();\n\n// Alpha Blend ARGB images and store to destination.\n// Source is pre-multiplied by alpha using ARGBAttenuate.\n// Alpha of destination is set to 255.\nLIBYUV_API\nint ARGBBlend(const uint8* src_argb0, int src_stride_argb0,\n              const uint8* src_argb1, int src_stride_argb1,\n              uint8* dst_argb, int dst_stride_argb,\n              int width, int height);\n\n// Alpha Blend plane and store to destination.\n// Source is not pre-multiplied by alpha.\nLIBYUV_API\nint BlendPlane(const uint8* src_y0, int src_stride_y0,\n               const uint8* src_y1, int src_stride_y1,\n               const uint8* alpha, int alpha_stride,\n               uint8* dst_y, int dst_stride_y,\n               int width, int height);\n\n// Alpha Blend YUV images and store to destination.\n// Source is not pre-multiplied by alpha.\n// Alpha is full width x height and subsampled to half size to apply to UV.\nLIBYUV_API\nint I420Blend(const uint8* src_y0, int src_stride_y0,\n              const uint8* src_u0, int src_stride_u0,\n              const uint8* src_v0, int src_stride_v0,\n              const uint8* src_y1, int src_stride_y1,\n              const uint8* src_u1, int src_stride_u1,\n              const uint8* src_v1, int src_stride_v1,\n              const uint8* alpha, int alpha_stride,\n              uint8* dst_y, int dst_stride_y,\n              uint8* dst_u, int dst_stride_u,\n              uint8* dst_v, int dst_stride_v,\n              int width, int height);\n\n// Multiply ARGB image by ARGB image. Shifted down by 8. Saturates to 255.\nLIBYUV_API\nint ARGBMultiply(const uint8* src_argb0, int src_stride_argb0,\n                 const uint8* src_argb1, int src_stride_argb1,\n                 uint8* dst_argb, int dst_stride_argb,\n                 int width, int height);\n\n// Add ARGB image with ARGB image. Saturates to 255.\nLIBYUV_API\nint ARGBAdd(const uint8* src_argb0, int src_stride_argb0,\n            const uint8* src_argb1, int src_stride_argb1,\n            uint8* dst_argb, int dst_stride_argb,\n            int width, int height);\n\n// Subtract ARGB image (argb1) from ARGB image (argb0). Saturates to 0.\nLIBYUV_API\nint ARGBSubtract(const uint8* src_argb0, int src_stride_argb0,\n                 const uint8* src_argb1, int src_stride_argb1,\n                 uint8* dst_argb, int dst_stride_argb,\n                 int width, int height);\n\n// Convert I422 to YUY2.\nLIBYUV_API\nint I422ToYUY2(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_frame, int dst_stride_frame,\n               int width, int height);\n\n// Convert I422 to UYVY.\nLIBYUV_API\nint I422ToUYVY(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_frame, int dst_stride_frame,\n               int width, int height);\n\n// Convert unattentuated ARGB to preattenuated ARGB.\nLIBYUV_API\nint ARGBAttenuate(const uint8* src_argb, int src_stride_argb,\n                  uint8* dst_argb, int dst_stride_argb,\n                  int width, int height);\n\n// Convert preattentuated ARGB to unattenuated ARGB.\nLIBYUV_API\nint ARGBUnattenuate(const uint8* src_argb, int src_stride_argb,\n                    uint8* dst_argb, int dst_stride_argb,\n                    int width, int height);\n\n// Internal function - do not call directly.\n// Computes table of cumulative sum for image where the value is the sum\n// of all values above and to the left of the entry. Used by ARGBBlur.\nLIBYUV_API\nint ARGBComputeCumulativeSum(const uint8* src_argb, int src_stride_argb,\n                             int32* dst_cumsum, int dst_stride32_cumsum,\n                             int width, int height);\n\n// Blur ARGB image.\n// dst_cumsum table of width * (height + 1) * 16 bytes aligned to\n//   16 byte boundary.\n// dst_stride32_cumsum is number of ints in a row (width * 4).\n// radius is number of pixels around the center.  e.g. 1 = 3x3. 2=5x5.\n// Blur is optimized for radius of 5 (11x11) or less.\nLIBYUV_API\nint ARGBBlur(const uint8* src_argb, int src_stride_argb,\n             uint8* dst_argb, int dst_stride_argb,\n             int32* dst_cumsum, int dst_stride32_cumsum,\n             int width, int height, int radius);\n\n// Multiply ARGB image by ARGB value.\nLIBYUV_API\nint ARGBShade(const uint8* src_argb, int src_stride_argb,\n              uint8* dst_argb, int dst_stride_argb,\n              int width, int height, uint32 value);\n\n// Interpolate between two images using specified amount of interpolation\n// (0 to 255) and store to destination.\n// 'interpolation' is specified as 8 bit fraction where 0 means 100% src0\n// and 255 means 1% src0 and 99% src1.\nLIBYUV_API\nint InterpolatePlane(const uint8* src0, int src_stride0,\n                     const uint8* src1, int src_stride1,\n                     uint8* dst, int dst_stride,\n                     int width, int height, int interpolation);\n\n// Interpolate between two ARGB images using specified amount of interpolation\n// Internally calls InterpolatePlane with width * 4 (bpp).\nLIBYUV_API\nint ARGBInterpolate(const uint8* src_argb0, int src_stride_argb0,\n                    const uint8* src_argb1, int src_stride_argb1,\n                    uint8* dst_argb, int dst_stride_argb,\n                    int width, int height, int interpolation);\n\n// Interpolate between two YUV images using specified amount of interpolation\n// Internally calls InterpolatePlane on each plane where the U and V planes\n// are half width and half height.\nLIBYUV_API\nint I420Interpolate(const uint8* src0_y, int src0_stride_y,\n                    const uint8* src0_u, int src0_stride_u,\n                    const uint8* src0_v, int src0_stride_v,\n                    const uint8* src1_y, int src1_stride_y,\n                    const uint8* src1_u, int src1_stride_u,\n                    const uint8* src1_v, int src1_stride_v,\n                    uint8* dst_y, int dst_stride_y,\n                    uint8* dst_u, int dst_stride_u,\n                    uint8* dst_v, int dst_stride_v,\n                    int width, int height, int interpolation);\n\n#if defined(__pnacl__) || defined(__CLR_VER) || \\\n    (defined(__i386__) && !defined(__SSE2__))\n#define LIBYUV_DISABLE_X86\n#endif\n// MemorySanitizer does not support assembly code yet. http://crbug.com/344505\n#if defined(__has_feature)\n#if __has_feature(memory_sanitizer)\n#define LIBYUV_DISABLE_X86\n#endif\n#endif\n// The following are available on all x86 platforms:\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    (defined(_M_IX86) || defined(__x86_64__) || defined(__i386__))\n#define HAS_ARGBAFFINEROW_SSE2\n#endif\n\n// Row function for copying pixels from a source with a slope to a row\n// of destination. Useful for scaling, rotation, mirror, texture mapping.\nLIBYUV_API\nvoid ARGBAffineRow_C(const uint8* src_argb, int src_argb_stride,\n                     uint8* dst_argb, const float* uv_dudv, int width);\nLIBYUV_API\nvoid ARGBAffineRow_SSE2(const uint8* src_argb, int src_argb_stride,\n                        uint8* dst_argb, const float* uv_dudv, int width);\n\n// Shuffle ARGB channel order.  e.g. BGRA to ARGB.\n// shuffler is 16 bytes and must be aligned.\nLIBYUV_API\nint ARGBShuffle(const uint8* src_bgra, int src_stride_bgra,\n                uint8* dst_argb, int dst_stride_argb,\n                const uint8* shuffler, int width, int height);\n\n// Sobel ARGB effect with planar output.\nLIBYUV_API\nint ARGBSobelToPlane(const uint8* src_argb, int src_stride_argb,\n                     uint8* dst_y, int dst_stride_y,\n                     int width, int height);\n\n// Sobel ARGB effect.\nLIBYUV_API\nint ARGBSobel(const uint8* src_argb, int src_stride_argb,\n              uint8* dst_argb, int dst_stride_argb,\n              int width, int height);\n\n// Sobel ARGB effect w/ Sobel X, Sobel, Sobel Y in ARGB.\nLIBYUV_API\nint ARGBSobelXY(const uint8* src_argb, int src_stride_argb,\n                uint8* dst_argb, int dst_stride_argb,\n                int width, int height);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_PLANAR_FUNCTIONS_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/rotate.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_ROTATE_H_\n#define INCLUDE_LIBYUV_ROTATE_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Supported rotation.\ntypedef enum RotationMode {\n  kRotate0 = 0,  // No rotation.\n  kRotate90 = 90,  // Rotate 90 degrees clockwise.\n  kRotate180 = 180,  // Rotate 180 degrees.\n  kRotate270 = 270,  // Rotate 270 degrees clockwise.\n\n  // Deprecated.\n  kRotateNone = 0,\n  kRotateClockwise = 90,\n  kRotateCounterClockwise = 270,\n} RotationModeEnum;\n\n// Rotate I420 frame.\nLIBYUV_API\nint I420Rotate(const uint8* src_y, int src_stride_y,\n               const uint8* src_u, int src_stride_u,\n               const uint8* src_v, int src_stride_v,\n               uint8* dst_y, int dst_stride_y,\n               uint8* dst_u, int dst_stride_u,\n               uint8* dst_v, int dst_stride_v,\n               int src_width, int src_height, enum RotationMode mode);\n\n// Rotate NV12 input and store in I420.\nLIBYUV_API\nint NV12ToI420Rotate(const uint8* src_y, int src_stride_y,\n                     const uint8* src_uv, int src_stride_uv,\n                     uint8* dst_y, int dst_stride_y,\n                     uint8* dst_u, int dst_stride_u,\n                     uint8* dst_v, int dst_stride_v,\n                     int src_width, int src_height, enum RotationMode mode);\n\n// Rotate a plane by 0, 90, 180, or 270.\nLIBYUV_API\nint RotatePlane(const uint8* src, int src_stride,\n                uint8* dst, int dst_stride,\n                int src_width, int src_height, enum RotationMode mode);\n\n// Rotate planes by 90, 180, 270. Deprecated.\nLIBYUV_API\nvoid RotatePlane90(const uint8* src, int src_stride,\n                   uint8* dst, int dst_stride,\n                   int width, int height);\n\nLIBYUV_API\nvoid RotatePlane180(const uint8* src, int src_stride,\n                    uint8* dst, int dst_stride,\n                    int width, int height);\n\nLIBYUV_API\nvoid RotatePlane270(const uint8* src, int src_stride,\n                    uint8* dst, int dst_stride,\n                    int width, int height);\n\nLIBYUV_API\nvoid RotateUV90(const uint8* src, int src_stride,\n                uint8* dst_a, int dst_stride_a,\n                uint8* dst_b, int dst_stride_b,\n                int width, int height);\n\n// Rotations for when U and V are interleaved.\n// These functions take one input pointer and\n// split the data into two buffers while\n// rotating them. Deprecated.\nLIBYUV_API\nvoid RotateUV180(const uint8* src, int src_stride,\n                 uint8* dst_a, int dst_stride_a,\n                 uint8* dst_b, int dst_stride_b,\n                 int width, int height);\n\nLIBYUV_API\nvoid RotateUV270(const uint8* src, int src_stride,\n                 uint8* dst_a, int dst_stride_a,\n                 uint8* dst_b, int dst_stride_b,\n                 int width, int height);\n\n// The 90 and 270 functions are based on transposes.\n// Doing a transpose with reversing the read/write\n// order will result in a rotation by +- 90 degrees.\n// Deprecated.\nLIBYUV_API\nvoid TransposePlane(const uint8* src, int src_stride,\n                    uint8* dst, int dst_stride,\n                    int width, int height);\n\nLIBYUV_API\nvoid TransposeUV(const uint8* src, int src_stride,\n                 uint8* dst_a, int dst_stride_a,\n                 uint8* dst_b, int dst_stride_b,\n                 int width, int height);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_ROTATE_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/rotate_argb.h",
    "content": "/*\n *  Copyright 2012 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_ROTATE_ARGB_H_\n#define INCLUDE_LIBYUV_ROTATE_ARGB_H_\n\n#include \"libyuv/basic_types.h\"\n#include \"libyuv/rotate.h\"  // For RotationMode.\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Rotate ARGB frame\nLIBYUV_API\nint ARGBRotate(const uint8* src_argb, int src_stride_argb,\n               uint8* dst_argb, int dst_stride_argb,\n               int src_width, int src_height, enum RotationMode mode);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_ROTATE_ARGB_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/rotate_row.h",
    "content": "/*\n *  Copyright 2013 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_ROTATE_ROW_H_\n#define INCLUDE_LIBYUV_ROTATE_ROW_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n#if defined(__pnacl__) || defined(__CLR_VER) || \\\n    (defined(__i386__) && !defined(__SSE2__))\n#define LIBYUV_DISABLE_X86\n#endif\n// MemorySanitizer does not support assembly code yet. http://crbug.com/344505\n#if defined(__has_feature)\n#if __has_feature(memory_sanitizer)\n#define LIBYUV_DISABLE_X86\n#endif\n#endif\n// The following are available for Visual C and clangcl 32 bit:\n#if !defined(LIBYUV_DISABLE_X86) && defined(_M_IX86)\n#define HAS_TRANSPOSEWX8_SSSE3\n#define HAS_TRANSPOSEUVWX8_SSE2\n#endif\n\n// The following are available for GCC 32 or 64 bit but not NaCL for 64 bit:\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    (defined(__i386__) || (defined(__x86_64__) && !defined(__native_client__)))\n#define HAS_TRANSPOSEWX8_SSSE3\n#endif\n\n// The following are available for 64 bit GCC but not NaCL:\n#if !defined(LIBYUV_DISABLE_X86) && !defined(__native_client__) && \\\n    defined(__x86_64__)\n#define HAS_TRANSPOSEWX8_FAST_SSSE3\n#define HAS_TRANSPOSEUVWX8_SSE2\n#endif\n\n#if !defined(LIBYUV_DISABLE_NEON) && !defined(__native_client__) && \\\n    (defined(__ARM_NEON__) || defined(LIBYUV_NEON) || defined(__aarch64__))\n#define HAS_TRANSPOSEWX8_NEON\n#define HAS_TRANSPOSEUVWX8_NEON\n#endif\n\n#if !defined(LIBYUV_DISABLE_MIPS) && !defined(__native_client__) && \\\n    defined(__mips__) && \\\n    defined(__mips_dsp) && (__mips_dsp_rev >= 2)\n#define HAS_TRANSPOSEWX8_DSPR2\n#define HAS_TRANSPOSEUVWX8_DSPR2\n#endif  // defined(__mips__)\n\nvoid TransposeWxH_C(const uint8* src, int src_stride,\n                    uint8* dst, int dst_stride, int width, int height);\n\nvoid TransposeWx8_C(const uint8* src, int src_stride,\n                    uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_NEON(const uint8* src, int src_stride,\n                       uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_SSSE3(const uint8* src, int src_stride,\n                        uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_Fast_SSSE3(const uint8* src, int src_stride,\n                             uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_DSPR2(const uint8* src, int src_stride,\n                        uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_Fast_DSPR2(const uint8* src, int src_stride,\n                             uint8* dst, int dst_stride, int width);\n\nvoid TransposeWx8_Any_NEON(const uint8* src, int src_stride,\n                           uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_Any_SSSE3(const uint8* src, int src_stride,\n                            uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_Fast_Any_SSSE3(const uint8* src, int src_stride,\n                                 uint8* dst, int dst_stride, int width);\nvoid TransposeWx8_Any_DSPR2(const uint8* src, int src_stride,\n                            uint8* dst, int dst_stride, int width);\n\nvoid TransposeUVWxH_C(const uint8* src, int src_stride,\n                      uint8* dst_a, int dst_stride_a,\n                      uint8* dst_b, int dst_stride_b,\n                      int width, int height);\n\nvoid TransposeUVWx8_C(const uint8* src, int src_stride,\n                      uint8* dst_a, int dst_stride_a,\n                      uint8* dst_b, int dst_stride_b, int width);\nvoid TransposeUVWx8_SSE2(const uint8* src, int src_stride,\n                         uint8* dst_a, int dst_stride_a,\n                         uint8* dst_b, int dst_stride_b, int width);\nvoid TransposeUVWx8_NEON(const uint8* src, int src_stride,\n                         uint8* dst_a, int dst_stride_a,\n                         uint8* dst_b, int dst_stride_b, int width);\nvoid TransposeUVWx8_DSPR2(const uint8* src, int src_stride,\n                          uint8* dst_a, int dst_stride_a,\n                          uint8* dst_b, int dst_stride_b, int width);\n\nvoid TransposeUVWx8_Any_SSE2(const uint8* src, int src_stride,\n                             uint8* dst_a, int dst_stride_a,\n                             uint8* dst_b, int dst_stride_b, int width);\nvoid TransposeUVWx8_Any_NEON(const uint8* src, int src_stride,\n                             uint8* dst_a, int dst_stride_a,\n                             uint8* dst_b, int dst_stride_b, int width);\nvoid TransposeUVWx8_Any_DSPR2(const uint8* src, int src_stride,\n                              uint8* dst_a, int dst_stride_a,\n                              uint8* dst_b, int dst_stride_b, int width);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_ROTATE_ROW_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/row.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_ROW_H_\n#define INCLUDE_LIBYUV_ROW_H_\n\n#include <stdlib.h>  // For malloc.\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n#define IS_ALIGNED(p, a) (!((uintptr_t)(p) & ((a) - 1)))\n\n#define align_buffer_64(var, size)                                             \\\n  uint8* var##_mem = (uint8*)(malloc((size) + 63));               /* NOLINT */ \\\n  uint8* var = (uint8*)(((intptr_t)(var##_mem) + 63) & ~63)       /* NOLINT */\n\n#define free_aligned_buffer_64(var) \\\n  free(var##_mem);  \\\n  var = 0\n\n#if defined(__pnacl__) || defined(__CLR_VER) || \\\n    (defined(__i386__) && !defined(__SSE2__))\n#define LIBYUV_DISABLE_X86\n#endif\n// MemorySanitizer does not support assembly code yet. http://crbug.com/344505\n#if defined(__has_feature)\n#if __has_feature(memory_sanitizer)\n#define LIBYUV_DISABLE_X86\n#endif\n#endif\n// True if compiling for SSSE3 as a requirement.\n#if defined(__SSSE3__) || (defined(_M_IX86_FP) && (_M_IX86_FP >= 3))\n#define LIBYUV_SSSE3_ONLY\n#endif\n\n#if defined(__native_client__)\n#define LIBYUV_DISABLE_NEON\n#endif\n// clang >= 3.5.0 required for Arm64.\n#if defined(__clang__) && defined(__aarch64__) && !defined(LIBYUV_DISABLE_NEON)\n#if (__clang_major__ < 3) || (__clang_major__ == 3 && (__clang_minor__ < 5))\n#define LIBYUV_DISABLE_NEON\n#endif  // clang >= 3.5\n#endif  // __clang__\n\n// GCC >= 4.7.0 required for AVX2.\n#if defined(__GNUC__) && (defined(__x86_64__) || defined(__i386__))\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && (__GNUC_MINOR__ >= 7))\n#define GCC_HAS_AVX2 1\n#endif  // GNUC >= 4.7\n#endif  // __GNUC__\n\n// clang >= 3.4.0 required for AVX2.\n#if defined(__clang__) && (defined(__x86_64__) || defined(__i386__))\n#if (__clang_major__ > 3) || (__clang_major__ == 3 && (__clang_minor__ >= 4))\n#define CLANG_HAS_AVX2 1\n#endif  // clang >= 3.4\n#endif  // __clang__\n\n// Visual C 2012 required for AVX2.\n#if defined(_M_IX86) && !defined(__clang__) && \\\n    defined(_MSC_VER) && _MSC_VER >= 1700\n#define VISUALC_HAS_AVX2 1\n#endif  // VisualStudio >= 2012\n\n// The following are available on all x86 platforms:\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    (defined(_M_IX86) || defined(__x86_64__) || defined(__i386__))\n// Conversions:\n#define HAS_ABGRTOUVROW_SSSE3\n#define HAS_ABGRTOYROW_SSSE3\n#define HAS_ARGB1555TOARGBROW_SSE2\n#define HAS_ARGB4444TOARGBROW_SSE2\n#define HAS_ARGBSETROW_X86\n#define HAS_ARGBSHUFFLEROW_SSE2\n#define HAS_ARGBSHUFFLEROW_SSSE3\n#define HAS_ARGBTOARGB1555ROW_SSE2\n#define HAS_ARGBTOARGB4444ROW_SSE2\n#define HAS_ARGBTORAWROW_SSSE3\n#define HAS_ARGBTORGB24ROW_SSSE3\n#define HAS_ARGBTORGB565DITHERROW_SSE2\n#define HAS_ARGBTORGB565ROW_SSE2\n#define HAS_ARGBTOUV444ROW_SSSE3\n#define HAS_ARGBTOUVJROW_SSSE3\n#define HAS_ARGBTOUVROW_SSSE3\n#define HAS_ARGBTOYJROW_SSSE3\n#define HAS_ARGBTOYROW_SSSE3\n#define HAS_ARGBEXTRACTALPHAROW_SSE2\n#define HAS_BGRATOUVROW_SSSE3\n#define HAS_BGRATOYROW_SSSE3\n#define HAS_COPYROW_ERMS\n#define HAS_COPYROW_SSE2\n#define HAS_H422TOARGBROW_SSSE3\n#define HAS_I400TOARGBROW_SSE2\n#define HAS_I422TOARGB1555ROW_SSSE3\n#define HAS_I422TOARGB4444ROW_SSSE3\n#define HAS_I422TOARGBROW_SSSE3\n#define HAS_I422TORGB24ROW_SSSE3\n#define HAS_I422TORGB565ROW_SSSE3\n#define HAS_I422TORGBAROW_SSSE3\n#define HAS_I422TOUYVYROW_SSE2\n#define HAS_I422TOYUY2ROW_SSE2\n#define HAS_I444TOARGBROW_SSSE3\n#define HAS_J400TOARGBROW_SSE2\n#define HAS_J422TOARGBROW_SSSE3\n#define HAS_MERGEUVROW_SSE2\n#define HAS_MIRRORROW_SSSE3\n#define HAS_MIRRORUVROW_SSSE3\n#define HAS_NV12TOARGBROW_SSSE3\n#define HAS_NV12TORGB565ROW_SSSE3\n#define HAS_NV21TOARGBROW_SSSE3\n#define HAS_RAWTOARGBROW_SSSE3\n#define HAS_RAWTORGB24ROW_SSSE3\n#define HAS_RAWTOYROW_SSSE3\n#define HAS_RGB24TOARGBROW_SSSE3\n#define HAS_RGB24TOYROW_SSSE3\n#define HAS_RGB565TOARGBROW_SSE2\n#define HAS_RGBATOUVROW_SSSE3\n#define HAS_RGBATOYROW_SSSE3\n#define HAS_SETROW_ERMS\n#define HAS_SETROW_X86\n#define HAS_SPLITUVROW_SSE2\n#define HAS_UYVYTOARGBROW_SSSE3\n#define HAS_UYVYTOUV422ROW_SSE2\n#define HAS_UYVYTOUVROW_SSE2\n#define HAS_UYVYTOYROW_SSE2\n#define HAS_YUY2TOARGBROW_SSSE3\n#define HAS_YUY2TOUV422ROW_SSE2\n#define HAS_YUY2TOUVROW_SSE2\n#define HAS_YUY2TOYROW_SSE2\n\n// Effects:\n#define HAS_ARGBADDROW_SSE2\n#define HAS_ARGBAFFINEROW_SSE2\n#define HAS_ARGBATTENUATEROW_SSSE3\n#define HAS_ARGBBLENDROW_SSSE3\n#define HAS_ARGBCOLORMATRIXROW_SSSE3\n#define HAS_ARGBCOLORTABLEROW_X86\n#define HAS_ARGBCOPYALPHAROW_SSE2\n#define HAS_ARGBCOPYYTOALPHAROW_SSE2\n#define HAS_ARGBGRAYROW_SSSE3\n#define HAS_ARGBLUMACOLORTABLEROW_SSSE3\n#define HAS_ARGBMIRRORROW_SSE2\n#define HAS_ARGBMULTIPLYROW_SSE2\n#define HAS_ARGBPOLYNOMIALROW_SSE2\n#define HAS_ARGBQUANTIZEROW_SSE2\n#define HAS_ARGBSEPIAROW_SSSE3\n#define HAS_ARGBSHADEROW_SSE2\n#define HAS_ARGBSUBTRACTROW_SSE2\n#define HAS_ARGBUNATTENUATEROW_SSE2\n#define HAS_BLENDPLANEROW_SSSE3\n#define HAS_COMPUTECUMULATIVESUMROW_SSE2\n#define HAS_CUMULATIVESUMTOAVERAGEROW_SSE2\n#define HAS_INTERPOLATEROW_SSSE3\n#define HAS_RGBCOLORTABLEROW_X86\n#define HAS_SOBELROW_SSE2\n#define HAS_SOBELTOPLANEROW_SSE2\n#define HAS_SOBELXROW_SSE2\n#define HAS_SOBELXYROW_SSE2\n#define HAS_SOBELYROW_SSE2\n\n// The following functions fail on gcc/clang 32 bit with fpic and framepointer.\n// caveat: clangcl uses row_win.cc which works.\n#if defined(NDEBUG) || !(defined(_DEBUG) && defined(__i386__)) || \\\n    !defined(__i386__) || defined(_MSC_VER)\n// TODO(fbarchard): fix build error on x86 debug\n// https://code.google.com/p/libyuv/issues/detail?id=524\n#define HAS_I411TOARGBROW_SSSE3\n// TODO(fbarchard): fix build error on android_full_debug=1\n// https://code.google.com/p/libyuv/issues/detail?id=517\n#define HAS_I422ALPHATOARGBROW_SSSE3\n#endif\n#endif\n\n// The following are available on all x86 platforms, but\n// require VS2012, clang 3.4 or gcc 4.7.\n// The code supports NaCL but requires a new compiler and validator.\n#if !defined(LIBYUV_DISABLE_X86) && (defined(VISUALC_HAS_AVX2) || \\\n    defined(CLANG_HAS_AVX2) || defined(GCC_HAS_AVX2))\n#define HAS_ARGBCOPYALPHAROW_AVX2\n#define HAS_ARGBCOPYYTOALPHAROW_AVX2\n#define HAS_ARGBMIRRORROW_AVX2\n#define HAS_ARGBPOLYNOMIALROW_AVX2\n#define HAS_ARGBSHUFFLEROW_AVX2\n#define HAS_ARGBTORGB565DITHERROW_AVX2\n#define HAS_ARGBTOUVJROW_AVX2\n#define HAS_ARGBTOUVROW_AVX2\n#define HAS_ARGBTOYJROW_AVX2\n#define HAS_ARGBTOYROW_AVX2\n#define HAS_COPYROW_AVX\n#define HAS_H422TOARGBROW_AVX2\n#define HAS_I400TOARGBROW_AVX2\n#if !(defined(_DEBUG) && defined(__i386__))\n// TODO(fbarchard): fix build error on android_full_debug=1\n// https://code.google.com/p/libyuv/issues/detail?id=517\n#define HAS_I422ALPHATOARGBROW_AVX2\n#endif\n#define HAS_I411TOARGBROW_AVX2\n#define HAS_I422TOARGB1555ROW_AVX2\n#define HAS_I422TOARGB4444ROW_AVX2\n#define HAS_I422TOARGBROW_AVX2\n#define HAS_I422TORGB24ROW_AVX2\n#define HAS_I422TORGB565ROW_AVX2\n#define HAS_I422TORGBAROW_AVX2\n#define HAS_I444TOARGBROW_AVX2\n#define HAS_INTERPOLATEROW_AVX2\n#define HAS_J422TOARGBROW_AVX2\n#define HAS_MERGEUVROW_AVX2\n#define HAS_MIRRORROW_AVX2\n#define HAS_NV12TOARGBROW_AVX2\n#define HAS_NV12TORGB565ROW_AVX2\n#define HAS_NV21TOARGBROW_AVX2\n#define HAS_SPLITUVROW_AVX2\n#define HAS_UYVYTOARGBROW_AVX2\n#define HAS_UYVYTOUV422ROW_AVX2\n#define HAS_UYVYTOUVROW_AVX2\n#define HAS_UYVYTOYROW_AVX2\n#define HAS_YUY2TOARGBROW_AVX2\n#define HAS_YUY2TOUV422ROW_AVX2\n#define HAS_YUY2TOUVROW_AVX2\n#define HAS_YUY2TOYROW_AVX2\n#define HAS_HALFFLOATROW_AVX2\n\n// Effects:\n#define HAS_ARGBADDROW_AVX2\n#define HAS_ARGBATTENUATEROW_AVX2\n#define HAS_ARGBMULTIPLYROW_AVX2\n#define HAS_ARGBSUBTRACTROW_AVX2\n#define HAS_ARGBUNATTENUATEROW_AVX2\n#define HAS_BLENDPLANEROW_AVX2\n#endif\n\n// The following are available for AVX2 Visual C and clangcl 32 bit:\n// TODO(fbarchard): Port to gcc.\n#if !defined(LIBYUV_DISABLE_X86) && defined(_M_IX86) && \\\n    (defined(VISUALC_HAS_AVX2) || defined(CLANG_HAS_AVX2))\n#define HAS_ARGB1555TOARGBROW_AVX2\n#define HAS_ARGB4444TOARGBROW_AVX2\n#define HAS_ARGBTOARGB1555ROW_AVX2\n#define HAS_ARGBTOARGB4444ROW_AVX2\n#define HAS_ARGBTORGB565ROW_AVX2\n#define HAS_J400TOARGBROW_AVX2\n#define HAS_RGB565TOARGBROW_AVX2\n#endif\n\n// The following are also available on x64 Visual C.\n#if !defined(LIBYUV_DISABLE_X86) && defined(_MSC_VER) && defined(_M_X64) && \\\n    (!defined(__clang__) || defined(__SSSE3__))\n#define HAS_I422ALPHATOARGBROW_SSSE3\n#define HAS_I422TOARGBROW_SSSE3\n#endif\n\n// The following are available on gcc x86 platforms:\n// TODO(fbarchard): Port to Visual C.\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    (defined(__x86_64__) || (defined(__i386__) && !defined(_MSC_VER)))\n#define HAS_HALFFLOATROW_SSE2\n#endif\n\n// The following are available on Neon platforms:\n#if !defined(LIBYUV_DISABLE_NEON) && \\\n    (defined(__aarch64__) || defined(__ARM_NEON__) || defined(LIBYUV_NEON))\n#define HAS_ABGRTOUVROW_NEON\n#define HAS_ABGRTOYROW_NEON\n#define HAS_ARGB1555TOARGBROW_NEON\n#define HAS_ARGB1555TOUVROW_NEON\n#define HAS_ARGB1555TOYROW_NEON\n#define HAS_ARGB4444TOARGBROW_NEON\n#define HAS_ARGB4444TOUVROW_NEON\n#define HAS_ARGB4444TOYROW_NEON\n#define HAS_ARGBSETROW_NEON\n#define HAS_ARGBTOARGB1555ROW_NEON\n#define HAS_ARGBTOARGB4444ROW_NEON\n#define HAS_ARGBTORAWROW_NEON\n#define HAS_ARGBTORGB24ROW_NEON\n#define HAS_ARGBTORGB565DITHERROW_NEON\n#define HAS_ARGBTORGB565ROW_NEON\n#define HAS_ARGBTOUV411ROW_NEON\n#define HAS_ARGBTOUV444ROW_NEON\n#define HAS_ARGBTOUVJROW_NEON\n#define HAS_ARGBTOUVROW_NEON\n#define HAS_ARGBTOYJROW_NEON\n#define HAS_ARGBTOYROW_NEON\n#define HAS_ARGBEXTRACTALPHAROW_NEON\n#define HAS_BGRATOUVROW_NEON\n#define HAS_BGRATOYROW_NEON\n#define HAS_COPYROW_NEON\n#define HAS_I400TOARGBROW_NEON\n#define HAS_I411TOARGBROW_NEON\n#define HAS_I422ALPHATOARGBROW_NEON\n#define HAS_I422TOARGB1555ROW_NEON\n#define HAS_I422TOARGB4444ROW_NEON\n#define HAS_I422TOARGBROW_NEON\n#define HAS_I422TORGB24ROW_NEON\n#define HAS_I422TORGB565ROW_NEON\n#define HAS_I422TORGBAROW_NEON\n#define HAS_I422TOUYVYROW_NEON\n#define HAS_I422TOYUY2ROW_NEON\n#define HAS_I444TOARGBROW_NEON\n#define HAS_J400TOARGBROW_NEON\n#define HAS_MERGEUVROW_NEON\n#define HAS_MIRRORROW_NEON\n#define HAS_MIRRORUVROW_NEON\n#define HAS_NV12TOARGBROW_NEON\n#define HAS_NV12TORGB565ROW_NEON\n#define HAS_NV21TOARGBROW_NEON\n#define HAS_RAWTOARGBROW_NEON\n#define HAS_RAWTORGB24ROW_NEON\n#define HAS_RAWTOUVROW_NEON\n#define HAS_RAWTOYROW_NEON\n#define HAS_RGB24TOARGBROW_NEON\n#define HAS_RGB24TOUVROW_NEON\n#define HAS_RGB24TOYROW_NEON\n#define HAS_RGB565TOARGBROW_NEON\n#define HAS_RGB565TOUVROW_NEON\n#define HAS_RGB565TOYROW_NEON\n#define HAS_RGBATOUVROW_NEON\n#define HAS_RGBATOYROW_NEON\n#define HAS_SETROW_NEON\n#define HAS_SPLITUVROW_NEON\n#define HAS_UYVYTOARGBROW_NEON\n#define HAS_UYVYTOUV422ROW_NEON\n#define HAS_UYVYTOUVROW_NEON\n#define HAS_UYVYTOYROW_NEON\n#define HAS_YUY2TOARGBROW_NEON\n#define HAS_YUY2TOUV422ROW_NEON\n#define HAS_YUY2TOUVROW_NEON\n#define HAS_YUY2TOYROW_NEON\n\n// Effects:\n#define HAS_ARGBADDROW_NEON\n#define HAS_ARGBATTENUATEROW_NEON\n#define HAS_ARGBBLENDROW_NEON\n#define HAS_ARGBCOLORMATRIXROW_NEON\n#define HAS_ARGBGRAYROW_NEON\n#define HAS_ARGBMIRRORROW_NEON\n#define HAS_ARGBMULTIPLYROW_NEON\n#define HAS_ARGBQUANTIZEROW_NEON\n#define HAS_ARGBSEPIAROW_NEON\n#define HAS_ARGBSHADEROW_NEON\n#define HAS_ARGBSHUFFLEROW_NEON\n#define HAS_ARGBSUBTRACTROW_NEON\n#define HAS_INTERPOLATEROW_NEON\n#define HAS_SOBELROW_NEON\n#define HAS_SOBELTOPLANEROW_NEON\n#define HAS_SOBELXROW_NEON\n#define HAS_SOBELXYROW_NEON\n#define HAS_SOBELYROW_NEON\n#endif\n\n// The following are available on Mips platforms:\n#if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__) && \\\n    (_MIPS_SIM == _MIPS_SIM_ABI32) && (__mips_isa_rev < 6)\n#define HAS_COPYROW_MIPS\n#if defined(__mips_dsp) && (__mips_dsp_rev >= 2)\n#define HAS_I422TOARGBROW_DSPR2\n#define HAS_INTERPOLATEROW_DSPR2\n#define HAS_MIRRORROW_DSPR2\n#define HAS_MIRRORUVROW_DSPR2\n#define HAS_SPLITUVROW_DSPR2\n#endif\n#endif\n\n#if !defined(LIBYUV_DISABLE_MSA) && defined(__mips_msa)\n#define HAS_MIRRORROW_MSA\n#define HAS_ARGBMIRRORROW_MSA\n#endif\n\n#if defined(_MSC_VER) && !defined(__CLR_VER) && !defined(__clang__)\n#if defined(VISUALC_HAS_AVX2)\n#define SIMD_ALIGNED(var) __declspec(align(32)) var\n#else\n#define SIMD_ALIGNED(var) __declspec(align(16)) var\n#endif\ntypedef __declspec(align(16)) int16 vec16[8];\ntypedef __declspec(align(16)) int32 vec32[4];\ntypedef __declspec(align(16)) int8 vec8[16];\ntypedef __declspec(align(16)) uint16 uvec16[8];\ntypedef __declspec(align(16)) uint32 uvec32[4];\ntypedef __declspec(align(16)) uint8 uvec8[16];\ntypedef __declspec(align(32)) int16 lvec16[16];\ntypedef __declspec(align(32)) int32 lvec32[8];\ntypedef __declspec(align(32)) int8 lvec8[32];\ntypedef __declspec(align(32)) uint16 ulvec16[16];\ntypedef __declspec(align(32)) uint32 ulvec32[8];\ntypedef __declspec(align(32)) uint8 ulvec8[32];\n#elif !defined(__pnacl__) && (defined(__GNUC__) || defined(__clang__))\n// Caveat GCC 4.2 to 4.7 have a known issue using vectors with const.\n#if defined(CLANG_HAS_AVX2) || defined(GCC_HAS_AVX2)\n#define SIMD_ALIGNED(var) var __attribute__((aligned(32)))\n#else\n#define SIMD_ALIGNED(var) var __attribute__((aligned(16)))\n#endif\ntypedef int16 __attribute__((vector_size(16))) vec16;\ntypedef int32 __attribute__((vector_size(16))) vec32;\ntypedef int8 __attribute__((vector_size(16))) vec8;\ntypedef uint16 __attribute__((vector_size(16))) uvec16;\ntypedef uint32 __attribute__((vector_size(16))) uvec32;\ntypedef uint8 __attribute__((vector_size(16))) uvec8;\ntypedef int16 __attribute__((vector_size(32))) lvec16;\ntypedef int32 __attribute__((vector_size(32))) lvec32;\ntypedef int8 __attribute__((vector_size(32))) lvec8;\ntypedef uint16 __attribute__((vector_size(32))) ulvec16;\ntypedef uint32 __attribute__((vector_size(32))) ulvec32;\ntypedef uint8 __attribute__((vector_size(32))) ulvec8;\n#else\n#define SIMD_ALIGNED(var) var\ntypedef int16 vec16[8];\ntypedef int32 vec32[4];\ntypedef int8 vec8[16];\ntypedef uint16 uvec16[8];\ntypedef uint32 uvec32[4];\ntypedef uint8 uvec8[16];\ntypedef int16 lvec16[16];\ntypedef int32 lvec32[8];\ntypedef int8 lvec8[32];\ntypedef uint16 ulvec16[16];\ntypedef uint32 ulvec32[8];\ntypedef uint8 ulvec8[32];\n#endif\n\n#if defined(__aarch64__)\n// This struct is for Arm64 color conversion.\nstruct YuvConstants {\n  uvec16 kUVToRB;\n  uvec16 kUVToRB2;\n  uvec16 kUVToG;\n  uvec16 kUVToG2;\n  vec16 kUVBiasBGR;\n  vec32 kYToRgb;\n};\n#elif defined(__arm__)\n// This struct is for ArmV7 color conversion.\nstruct YuvConstants {\n  uvec8 kUVToRB;\n  uvec8 kUVToG;\n  vec16 kUVBiasBGR;\n  vec32 kYToRgb;\n};\n#else\n// This struct is for Intel color conversion.\nstruct YuvConstants {\n  int8 kUVToB[32];\n  int8 kUVToG[32];\n  int8 kUVToR[32];\n  int16 kUVBiasB[16];\n  int16 kUVBiasG[16];\n  int16 kUVBiasR[16];\n  int16 kYToRgb[16];\n};\n\n// Offsets into YuvConstants structure\n#define KUVTOB   0\n#define KUVTOG   32\n#define KUVTOR   64\n#define KUVBIASB 96\n#define KUVBIASG 128\n#define KUVBIASR 160\n#define KYTORGB  192\n#endif\n\n// Conversion matrix for YUV to RGB\nextern const struct YuvConstants SIMD_ALIGNED(kYuvI601Constants);  // BT.601\nextern const struct YuvConstants SIMD_ALIGNED(kYuvJPEGConstants);  // JPeg\nextern const struct YuvConstants SIMD_ALIGNED(kYuvH709Constants);  // BT.709\n\n// Conversion matrix for YVU to BGR\nextern const struct YuvConstants SIMD_ALIGNED(kYvuI601Constants);  // BT.601\nextern const struct YuvConstants SIMD_ALIGNED(kYvuJPEGConstants);  // JPeg\nextern const struct YuvConstants SIMD_ALIGNED(kYvuH709Constants);  // BT.709\n\n#if defined(__APPLE__) || defined(__x86_64__) || defined(__llvm__)\n#define OMITFP\n#else\n#define OMITFP __attribute__((optimize(\"omit-frame-pointer\")))\n#endif\n\n// NaCL macros for GCC x86 and x64.\n#if defined(__native_client__)\n#define LABELALIGN \".p2align 5\\n\"\n#else\n#define LABELALIGN\n#endif\n#if defined(__native_client__) && defined(__x86_64__)\n// r14 is used for MEMOP macros.\n#define NACL_R14 \"r14\",\n#define BUNDLELOCK \".bundle_lock\\n\"\n#define BUNDLEUNLOCK \".bundle_unlock\\n\"\n#define MEMACCESS(base) \"%%nacl:(%%r15,%q\" #base \")\"\n#define MEMACCESS2(offset, base) \"%%nacl:\" #offset \"(%%r15,%q\" #base \")\"\n#define MEMLEA(offset, base) #offset \"(%q\" #base \")\"\n#define MEMLEA3(offset, index, scale) \\\n    #offset \"(,%q\" #index \",\" #scale \")\"\n#define MEMLEA4(offset, base, index, scale) \\\n    #offset \"(%q\" #base \",%q\" #index \",\" #scale \")\"\n#define MEMMOVESTRING(s, d) \"%%nacl:(%q\" #s \"),%%nacl:(%q\" #d \"), %%r15\"\n#define MEMSTORESTRING(reg, d) \"%%\" #reg \",%%nacl:(%q\" #d \"), %%r15\"\n#define MEMOPREG(opcode, offset, base, index, scale, reg) \\\n    BUNDLELOCK \\\n    \"lea \" #offset \"(%q\" #base \",%q\" #index \",\" #scale \"),%%r14d\\n\" \\\n    #opcode \" (%%r15,%%r14),%%\" #reg \"\\n\" \\\n    BUNDLEUNLOCK\n#define MEMOPMEM(opcode, reg, offset, base, index, scale) \\\n    BUNDLELOCK \\\n    \"lea \" #offset \"(%q\" #base \",%q\" #index \",\" #scale \"),%%r14d\\n\" \\\n    #opcode \" %%\" #reg \",(%%r15,%%r14)\\n\" \\\n    BUNDLEUNLOCK\n#define MEMOPARG(opcode, offset, base, index, scale, arg) \\\n    BUNDLELOCK \\\n    \"lea \" #offset \"(%q\" #base \",%q\" #index \",\" #scale \"),%%r14d\\n\" \\\n    #opcode \" (%%r15,%%r14),%\" #arg \"\\n\" \\\n    BUNDLEUNLOCK\n#define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \\\n    BUNDLELOCK \\\n    \"lea \" #offset \"(%q\" #base \",%q\" #index \",\" #scale \"),%%r14d\\n\" \\\n    #opcode \" (%%r15,%%r14),%%\" #reg1 \",%%\" #reg2 \"\\n\" \\\n    BUNDLEUNLOCK\n#define VEXTOPMEM(op, sel, reg, offset, base, index, scale) \\\n    BUNDLELOCK \\\n    \"lea \" #offset \"(%q\" #base \",%q\" #index \",\" #scale \"),%%r14d\\n\" \\\n    #op \" $\" #sel \",%%\" #reg \",(%%r15,%%r14)\\n\" \\\n    BUNDLEUNLOCK\n#else  // defined(__native_client__) && defined(__x86_64__)\n#define NACL_R14\n#define BUNDLEALIGN\n#define MEMACCESS(base) \"(%\" #base \")\"\n#define MEMACCESS2(offset, base) #offset \"(%\" #base \")\"\n#define MEMLEA(offset, base) #offset \"(%\" #base \")\"\n#define MEMLEA3(offset, index, scale) \\\n    #offset \"(,%\" #index \",\" #scale \")\"\n#define MEMLEA4(offset, base, index, scale) \\\n    #offset \"(%\" #base \",%\" #index \",\" #scale \")\"\n#define MEMMOVESTRING(s, d)\n#define MEMSTORESTRING(reg, d)\n#define MEMOPREG(opcode, offset, base, index, scale, reg) \\\n    #opcode \" \" #offset \"(%\" #base \",%\" #index \",\" #scale \"),%%\" #reg \"\\n\"\n#define MEMOPMEM(opcode, reg, offset, base, index, scale) \\\n    #opcode \" %%\" #reg \",\"#offset \"(%\" #base \",%\" #index \",\" #scale \")\\n\"\n#define MEMOPARG(opcode, offset, base, index, scale, arg) \\\n    #opcode \" \" #offset \"(%\" #base \",%\" #index \",\" #scale \"),%\" #arg \"\\n\"\n#define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \\\n    #opcode \" \" #offset \"(%\" #base \",%\" #index \",\" #scale \"),%%\" #reg1 \",%%\" \\\n    #reg2 \"\\n\"\n#define VEXTOPMEM(op, sel, reg, offset, base, index, scale) \\\n    #op \" $\" #sel \",%%\" #reg \",\"#offset \"(%\" #base \",%\" #index \",\" #scale \")\\n\"\n#endif  // defined(__native_client__) && defined(__x86_64__)\n\n#if defined(__arm__) || defined(__aarch64__)\n#undef MEMACCESS\n#if defined(__native_client__)\n#define MEMACCESS(base) \".p2align 3\\nbic %\" #base \", #0xc0000000\\n\"\n#else\n#define MEMACCESS(base)\n#endif\n#endif\n\nvoid I444ToARGBRow_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToARGBRow_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422AlphaToARGBRow_NEON(const uint8* y_buf,\n                             const uint8* u_buf,\n                             const uint8* v_buf,\n                             const uint8* a_buf,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422ToARGBRow_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I411ToARGBRow_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToRGBARow_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_rgba,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToRGB24Row_NEON(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_rgb24,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422ToRGB565Row_NEON(const uint8* src_y,\n                          const uint8* src_u,\n                          const uint8* src_v,\n                          uint8* dst_rgb565,\n                          const struct YuvConstants* yuvconstants,\n                          int width);\nvoid I422ToARGB1555Row_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb1555,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToARGB4444Row_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb4444,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid NV12ToARGBRow_NEON(const uint8* src_y,\n                        const uint8* src_uv,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid NV12ToRGB565Row_NEON(const uint8* src_y,\n                          const uint8* src_uv,\n                          uint8* dst_rgb565,\n                          const struct YuvConstants* yuvconstants,\n                          int width);\nvoid NV21ToARGBRow_NEON(const uint8* src_y,\n                        const uint8* src_vu,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid YUY2ToARGBRow_NEON(const uint8* src_yuy2,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid UYVYToARGBRow_NEON(const uint8* src_uyvy,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\n\nvoid ARGBToYRow_AVX2(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYRow_Any_AVX2(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYRow_SSSE3(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_AVX2(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_Any_AVX2(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_SSSE3(const uint8* src_argb, uint8* dst_y, int width);\nvoid BGRAToYRow_SSSE3(const uint8* src_bgra, uint8* dst_y, int width);\nvoid ABGRToYRow_SSSE3(const uint8* src_abgr, uint8* dst_y, int width);\nvoid RGBAToYRow_SSSE3(const uint8* src_rgba, uint8* dst_y, int width);\nvoid RGB24ToYRow_SSSE3(const uint8* src_rgb24, uint8* dst_y, int width);\nvoid RAWToYRow_SSSE3(const uint8* src_raw, uint8* dst_y, int width);\nvoid ARGBToYRow_NEON(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_NEON(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToUV444Row_NEON(const uint8* src_argb, uint8* dst_u, uint8* dst_v,\n                         int width);\nvoid ARGBToUV411Row_NEON(const uint8* src_argb, uint8* dst_u, uint8* dst_v,\n                         int width);\nvoid ARGBToUVRow_NEON(const uint8* src_argb, int src_stride_argb,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_NEON(const uint8* src_argb, int src_stride_argb,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid BGRAToUVRow_NEON(const uint8* src_bgra, int src_stride_bgra,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid ABGRToUVRow_NEON(const uint8* src_abgr, int src_stride_abgr,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid RGBAToUVRow_NEON(const uint8* src_rgba, int src_stride_rgba,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid RGB24ToUVRow_NEON(const uint8* src_rgb24, int src_stride_rgb24,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid RAWToUVRow_NEON(const uint8* src_raw, int src_stride_raw,\n                     uint8* dst_u, uint8* dst_v, int width);\nvoid RGB565ToUVRow_NEON(const uint8* src_rgb565, int src_stride_rgb565,\n                        uint8* dst_u, uint8* dst_v, int width);\nvoid ARGB1555ToUVRow_NEON(const uint8* src_argb1555, int src_stride_argb1555,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid ARGB4444ToUVRow_NEON(const uint8* src_argb4444, int src_stride_argb4444,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid BGRAToYRow_NEON(const uint8* src_bgra, uint8* dst_y, int width);\nvoid ABGRToYRow_NEON(const uint8* src_abgr, uint8* dst_y, int width);\nvoid RGBAToYRow_NEON(const uint8* src_rgba, uint8* dst_y, int width);\nvoid RGB24ToYRow_NEON(const uint8* src_rgb24, uint8* dst_y, int width);\nvoid RAWToYRow_NEON(const uint8* src_raw, uint8* dst_y, int width);\nvoid RGB565ToYRow_NEON(const uint8* src_rgb565, uint8* dst_y, int width);\nvoid ARGB1555ToYRow_NEON(const uint8* src_argb1555, uint8* dst_y, int width);\nvoid ARGB4444ToYRow_NEON(const uint8* src_argb4444, uint8* dst_y, int width);\nvoid ARGBToYRow_C(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_C(const uint8* src_argb, uint8* dst_y, int width);\nvoid BGRAToYRow_C(const uint8* src_bgra, uint8* dst_y, int width);\nvoid ABGRToYRow_C(const uint8* src_abgr, uint8* dst_y, int width);\nvoid RGBAToYRow_C(const uint8* src_rgba, uint8* dst_y, int width);\nvoid RGB24ToYRow_C(const uint8* src_rgb24, uint8* dst_y, int width);\nvoid RAWToYRow_C(const uint8* src_raw, uint8* dst_y, int width);\nvoid RGB565ToYRow_C(const uint8* src_rgb565, uint8* dst_y, int width);\nvoid ARGB1555ToYRow_C(const uint8* src_argb1555, uint8* dst_y, int width);\nvoid ARGB4444ToYRow_C(const uint8* src_argb4444, uint8* dst_y, int width);\nvoid ARGBToYRow_Any_SSSE3(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_Any_SSSE3(const uint8* src_argb, uint8* dst_y, int width);\nvoid BGRAToYRow_Any_SSSE3(const uint8* src_bgra, uint8* dst_y, int width);\nvoid ABGRToYRow_Any_SSSE3(const uint8* src_abgr, uint8* dst_y, int width);\nvoid RGBAToYRow_Any_SSSE3(const uint8* src_rgba, uint8* dst_y, int width);\nvoid RGB24ToYRow_Any_SSSE3(const uint8* src_rgb24, uint8* dst_y, int width);\nvoid RAWToYRow_Any_SSSE3(const uint8* src_raw, uint8* dst_y, int width);\nvoid ARGBToYRow_Any_NEON(const uint8* src_argb, uint8* dst_y, int width);\nvoid ARGBToYJRow_Any_NEON(const uint8* src_argb, uint8* dst_y, int width);\nvoid BGRAToYRow_Any_NEON(const uint8* src_bgra, uint8* dst_y, int width);\nvoid ABGRToYRow_Any_NEON(const uint8* src_abgr, uint8* dst_y, int width);\nvoid RGBAToYRow_Any_NEON(const uint8* src_rgba, uint8* dst_y, int width);\nvoid RGB24ToYRow_Any_NEON(const uint8* src_rgb24, uint8* dst_y, int width);\nvoid RAWToYRow_Any_NEON(const uint8* src_raw, uint8* dst_y, int width);\nvoid RGB565ToYRow_Any_NEON(const uint8* src_rgb565, uint8* dst_y, int width);\nvoid ARGB1555ToYRow_Any_NEON(const uint8* src_argb1555, uint8* dst_y,\n                             int width);\nvoid ARGB4444ToYRow_Any_NEON(const uint8* src_argb4444, uint8* dst_y,\n                             int width);\n\nvoid ARGBToUVRow_AVX2(const uint8* src_argb, int src_stride_argb,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_AVX2(const uint8* src_argb, int src_stride_argb,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVRow_SSSE3(const uint8* src_argb, int src_stride_argb,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_SSSE3(const uint8* src_argb, int src_stride_argb,\n                        uint8* dst_u, uint8* dst_v, int width);\nvoid BGRAToUVRow_SSSE3(const uint8* src_bgra, int src_stride_bgra,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid ABGRToUVRow_SSSE3(const uint8* src_abgr, int src_stride_abgr,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid RGBAToUVRow_SSSE3(const uint8* src_rgba, int src_stride_rgba,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVRow_Any_AVX2(const uint8* src_argb, int src_stride_argb,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_Any_AVX2(const uint8* src_argb, int src_stride_argb,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVRow_Any_SSSE3(const uint8* src_argb, int src_stride_argb,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_Any_SSSE3(const uint8* src_argb, int src_stride_argb,\n                            uint8* dst_u, uint8* dst_v, int width);\nvoid BGRAToUVRow_Any_SSSE3(const uint8* src_bgra, int src_stride_bgra,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid ABGRToUVRow_Any_SSSE3(const uint8* src_abgr, int src_stride_abgr,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid RGBAToUVRow_Any_SSSE3(const uint8* src_rgba, int src_stride_rgba,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUV444Row_Any_NEON(const uint8* src_argb, uint8* dst_u, uint8* dst_v,\n                             int width);\nvoid ARGBToUV411Row_Any_NEON(const uint8* src_argb, uint8* dst_u, uint8* dst_v,\n                             int width);\nvoid ARGBToUVRow_Any_NEON(const uint8* src_argb, int src_stride_argb,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_Any_NEON(const uint8* src_argb, int src_stride_argb,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid BGRAToUVRow_Any_NEON(const uint8* src_bgra, int src_stride_bgra,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid ABGRToUVRow_Any_NEON(const uint8* src_abgr, int src_stride_abgr,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid RGBAToUVRow_Any_NEON(const uint8* src_rgba, int src_stride_rgba,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid RGB24ToUVRow_Any_NEON(const uint8* src_rgb24, int src_stride_rgb24,\n                           uint8* dst_u, uint8* dst_v, int width);\nvoid RAWToUVRow_Any_NEON(const uint8* src_raw, int src_stride_raw,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid RGB565ToUVRow_Any_NEON(const uint8* src_rgb565, int src_stride_rgb565,\n                            uint8* dst_u, uint8* dst_v, int width);\nvoid ARGB1555ToUVRow_Any_NEON(const uint8* src_argb1555,\n                              int src_stride_argb1555,\n                              uint8* dst_u, uint8* dst_v, int width);\nvoid ARGB4444ToUVRow_Any_NEON(const uint8* src_argb4444,\n                              int src_stride_argb4444,\n                              uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVRow_C(const uint8* src_argb, int src_stride_argb,\n                   uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUVJRow_C(const uint8* src_argb, int src_stride_argb,\n                    uint8* dst_u, uint8* dst_v, int width);\nvoid BGRAToUVRow_C(const uint8* src_bgra, int src_stride_bgra,\n                   uint8* dst_u, uint8* dst_v, int width);\nvoid ABGRToUVRow_C(const uint8* src_abgr, int src_stride_abgr,\n                   uint8* dst_u, uint8* dst_v, int width);\nvoid RGBAToUVRow_C(const uint8* src_rgba, int src_stride_rgba,\n                   uint8* dst_u, uint8* dst_v, int width);\nvoid RGB24ToUVRow_C(const uint8* src_rgb24, int src_stride_rgb24,\n                    uint8* dst_u, uint8* dst_v, int width);\nvoid RAWToUVRow_C(const uint8* src_raw, int src_stride_raw,\n                  uint8* dst_u, uint8* dst_v, int width);\nvoid RGB565ToUVRow_C(const uint8* src_rgb565, int src_stride_rgb565,\n                     uint8* dst_u, uint8* dst_v, int width);\nvoid ARGB1555ToUVRow_C(const uint8* src_argb1555, int src_stride_argb1555,\n                       uint8* dst_u, uint8* dst_v, int width);\nvoid ARGB4444ToUVRow_C(const uint8* src_argb4444, int src_stride_argb4444,\n                       uint8* dst_u, uint8* dst_v, int width);\n\nvoid ARGBToUV444Row_SSSE3(const uint8* src_argb,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUV444Row_Any_SSSE3(const uint8* src_argb,\n                              uint8* dst_u, uint8* dst_v, int width);\n\nvoid ARGBToUV444Row_C(const uint8* src_argb,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid ARGBToUV411Row_C(const uint8* src_argb,\n                      uint8* dst_u, uint8* dst_v, int width);\n\nvoid MirrorRow_AVX2(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_SSSE3(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_NEON(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_DSPR2(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_MSA(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_C(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_Any_AVX2(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_Any_SSSE3(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_Any_SSE2(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_Any_NEON(const uint8* src, uint8* dst, int width);\nvoid MirrorRow_Any_MSA(const uint8* src, uint8* dst, int width);\n\nvoid MirrorUVRow_SSSE3(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                       int width);\nvoid MirrorUVRow_NEON(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                      int width);\nvoid MirrorUVRow_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                       int width);\nvoid MirrorUVRow_C(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int width);\n\nvoid ARGBMirrorRow_AVX2(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_SSE2(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_NEON(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_MSA(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_C(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_Any_AVX2(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_Any_SSE2(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_Any_NEON(const uint8* src, uint8* dst, int width);\nvoid ARGBMirrorRow_Any_MSA(const uint8* src, uint8* dst, int width);\n\nvoid SplitUVRow_C(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int width);\nvoid SplitUVRow_SSE2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                     int width);\nvoid SplitUVRow_AVX2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                     int width);\nvoid SplitUVRow_NEON(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                     int width);\nvoid SplitUVRow_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                      int width);\nvoid SplitUVRow_Any_SSE2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                         int width);\nvoid SplitUVRow_Any_AVX2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                         int width);\nvoid SplitUVRow_Any_NEON(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                         int width);\nvoid SplitUVRow_Any_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,\n                          int width);\n\nvoid MergeUVRow_C(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                  int width);\nvoid MergeUVRow_SSE2(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                     int width);\nvoid MergeUVRow_AVX2(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                     int width);\nvoid MergeUVRow_NEON(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                     int width);\nvoid MergeUVRow_Any_SSE2(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                         int width);\nvoid MergeUVRow_Any_AVX2(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                         int width);\nvoid MergeUVRow_Any_NEON(const uint8* src_u, const uint8* src_v, uint8* dst_uv,\n                         int width);\n\nvoid CopyRow_SSE2(const uint8* src, uint8* dst, int count);\nvoid CopyRow_AVX(const uint8* src, uint8* dst, int count);\nvoid CopyRow_ERMS(const uint8* src, uint8* dst, int count);\nvoid CopyRow_NEON(const uint8* src, uint8* dst, int count);\nvoid CopyRow_MIPS(const uint8* src, uint8* dst, int count);\nvoid CopyRow_C(const uint8* src, uint8* dst, int count);\nvoid CopyRow_Any_SSE2(const uint8* src, uint8* dst, int count);\nvoid CopyRow_Any_AVX(const uint8* src, uint8* dst, int count);\nvoid CopyRow_Any_NEON(const uint8* src, uint8* dst, int count);\n\nvoid CopyRow_16_C(const uint16* src, uint16* dst, int count);\n\nvoid ARGBCopyAlphaRow_C(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBCopyAlphaRow_SSE2(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBCopyAlphaRow_AVX2(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBCopyAlphaRow_Any_SSE2(const uint8* src_argb, uint8* dst_argb,\n                               int width);\nvoid ARGBCopyAlphaRow_Any_AVX2(const uint8* src_argb, uint8* dst_argb,\n                               int width);\n\nvoid ARGBExtractAlphaRow_C(const uint8* src_argb, uint8* dst_a, int width);\nvoid ARGBExtractAlphaRow_SSE2(const uint8* src_argb, uint8* dst_a, int width);\nvoid ARGBExtractAlphaRow_NEON(const uint8* src_argb, uint8* dst_a, int width);\nvoid ARGBExtractAlphaRow_Any_SSE2(const uint8* src_argb, uint8* dst_a,\n                                  int width);\nvoid ARGBExtractAlphaRow_Any_NEON(const uint8* src_argb, uint8* dst_a,\n                                  int width);\n\nvoid ARGBCopyYToAlphaRow_C(const uint8* src_y, uint8* dst_argb, int width);\nvoid ARGBCopyYToAlphaRow_SSE2(const uint8* src_y, uint8* dst_argb, int width);\nvoid ARGBCopyYToAlphaRow_AVX2(const uint8* src_y, uint8* dst_argb, int width);\nvoid ARGBCopyYToAlphaRow_Any_SSE2(const uint8* src_y, uint8* dst_argb,\n                                  int width);\nvoid ARGBCopyYToAlphaRow_Any_AVX2(const uint8* src_y, uint8* dst_argb,\n                                  int width);\n\nvoid SetRow_C(uint8* dst, uint8 v8, int count);\nvoid SetRow_X86(uint8* dst, uint8 v8, int count);\nvoid SetRow_ERMS(uint8* dst, uint8 v8, int count);\nvoid SetRow_NEON(uint8* dst, uint8 v8, int count);\nvoid SetRow_Any_X86(uint8* dst, uint8 v8, int count);\nvoid SetRow_Any_NEON(uint8* dst, uint8 v8, int count);\n\nvoid ARGBSetRow_C(uint8* dst_argb, uint32 v32, int count);\nvoid ARGBSetRow_X86(uint8* dst_argb, uint32 v32, int count);\nvoid ARGBSetRow_NEON(uint8* dst_argb, uint32 v32, int count);\nvoid ARGBSetRow_Any_NEON(uint8* dst_argb, uint32 v32, int count);\n\n// ARGBShufflers for BGRAToARGB etc.\nvoid ARGBShuffleRow_C(const uint8* src_argb, uint8* dst_argb,\n                      const uint8* shuffler, int width);\nvoid ARGBShuffleRow_SSE2(const uint8* src_argb, uint8* dst_argb,\n                         const uint8* shuffler, int width);\nvoid ARGBShuffleRow_SSSE3(const uint8* src_argb, uint8* dst_argb,\n                          const uint8* shuffler, int width);\nvoid ARGBShuffleRow_AVX2(const uint8* src_argb, uint8* dst_argb,\n                         const uint8* shuffler, int width);\nvoid ARGBShuffleRow_NEON(const uint8* src_argb, uint8* dst_argb,\n                         const uint8* shuffler, int width);\nvoid ARGBShuffleRow_Any_SSE2(const uint8* src_argb, uint8* dst_argb,\n                             const uint8* shuffler, int width);\nvoid ARGBShuffleRow_Any_SSSE3(const uint8* src_argb, uint8* dst_argb,\n                              const uint8* shuffler, int width);\nvoid ARGBShuffleRow_Any_AVX2(const uint8* src_argb, uint8* dst_argb,\n                             const uint8* shuffler, int width);\nvoid ARGBShuffleRow_Any_NEON(const uint8* src_argb, uint8* dst_argb,\n                             const uint8* shuffler, int width);\n\nvoid RGB24ToARGBRow_SSSE3(const uint8* src_rgb24, uint8* dst_argb, int width);\nvoid RAWToARGBRow_SSSE3(const uint8* src_raw, uint8* dst_argb, int width);\nvoid RAWToRGB24Row_SSSE3(const uint8* src_raw, uint8* dst_rgb24, int width);\nvoid RGB565ToARGBRow_SSE2(const uint8* src_rgb565, uint8* dst_argb, int width);\nvoid ARGB1555ToARGBRow_SSE2(const uint8* src_argb1555, uint8* dst_argb,\n                            int width);\nvoid ARGB4444ToARGBRow_SSE2(const uint8* src_argb4444, uint8* dst_argb,\n                            int width);\nvoid RGB565ToARGBRow_AVX2(const uint8* src_rgb565, uint8* dst_argb, int width);\nvoid ARGB1555ToARGBRow_AVX2(const uint8* src_argb1555, uint8* dst_argb,\n                            int width);\nvoid ARGB4444ToARGBRow_AVX2(const uint8* src_argb4444, uint8* dst_argb,\n                            int width);\n\nvoid RGB24ToARGBRow_NEON(const uint8* src_rgb24, uint8* dst_argb, int width);\nvoid RAWToARGBRow_NEON(const uint8* src_raw, uint8* dst_argb, int width);\nvoid RAWToRGB24Row_NEON(const uint8* src_raw, uint8* dst_rgb24, int width);\nvoid RGB565ToARGBRow_NEON(const uint8* src_rgb565, uint8* dst_argb, int width);\nvoid ARGB1555ToARGBRow_NEON(const uint8* src_argb1555, uint8* dst_argb,\n                            int width);\nvoid ARGB4444ToARGBRow_NEON(const uint8* src_argb4444, uint8* dst_argb,\n                            int width);\nvoid RGB24ToARGBRow_C(const uint8* src_rgb24, uint8* dst_argb, int width);\nvoid RAWToARGBRow_C(const uint8* src_raw, uint8* dst_argb, int width);\nvoid RAWToRGB24Row_C(const uint8* src_raw, uint8* dst_rgb24, int width);\nvoid RGB565ToARGBRow_C(const uint8* src_rgb, uint8* dst_argb, int width);\nvoid ARGB1555ToARGBRow_C(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGB4444ToARGBRow_C(const uint8* src_argb, uint8* dst_argb, int width);\nvoid RGB24ToARGBRow_Any_SSSE3(const uint8* src_rgb24, uint8* dst_argb,\n                              int width);\nvoid RAWToARGBRow_Any_SSSE3(const uint8* src_raw, uint8* dst_argb, int width);\nvoid RAWToRGB24Row_Any_SSSE3(const uint8* src_raw, uint8* dst_rgb24, int width);\n\nvoid RGB565ToARGBRow_Any_SSE2(const uint8* src_rgb565, uint8* dst_argb,\n                              int width);\nvoid ARGB1555ToARGBRow_Any_SSE2(const uint8* src_argb1555, uint8* dst_argb,\n                                int width);\nvoid ARGB4444ToARGBRow_Any_SSE2(const uint8* src_argb4444, uint8* dst_argb,\n                                int width);\nvoid RGB565ToARGBRow_Any_AVX2(const uint8* src_rgb565, uint8* dst_argb,\n                              int width);\nvoid ARGB1555ToARGBRow_Any_AVX2(const uint8* src_argb1555, uint8* dst_argb,\n                                int width);\nvoid ARGB4444ToARGBRow_Any_AVX2(const uint8* src_argb4444, uint8* dst_argb,\n                                int width);\n\nvoid RGB24ToARGBRow_Any_NEON(const uint8* src_rgb24, uint8* dst_argb,\n                             int width);\nvoid RAWToARGBRow_Any_NEON(const uint8* src_raw, uint8* dst_argb, int width);\nvoid RAWToRGB24Row_Any_NEON(const uint8* src_raw, uint8* dst_rgb24, int width);\nvoid RGB565ToARGBRow_Any_NEON(const uint8* src_rgb565, uint8* dst_argb,\n                              int width);\nvoid ARGB1555ToARGBRow_Any_NEON(const uint8* src_argb1555, uint8* dst_argb,\n                                int width);\nvoid ARGB4444ToARGBRow_Any_NEON(const uint8* src_argb4444, uint8* dst_argb,\n                                int width);\n\nvoid ARGBToRGB24Row_SSSE3(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRAWRow_SSSE3(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB565Row_SSE2(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_SSE2(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB4444Row_SSE2(const uint8* src_argb, uint8* dst_rgb, int width);\n\nvoid ARGBToRGB565DitherRow_C(const uint8* src_argb, uint8* dst_rgb,\n                             const uint32 dither4, int width);\nvoid ARGBToRGB565DitherRow_SSE2(const uint8* src_argb, uint8* dst_rgb,\n                                const uint32 dither4, int width);\nvoid ARGBToRGB565DitherRow_AVX2(const uint8* src_argb, uint8* dst_rgb,\n                                const uint32 dither4, int width);\n\nvoid ARGBToRGB565Row_AVX2(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_AVX2(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB4444Row_AVX2(const uint8* src_argb, uint8* dst_rgb, int width);\n\nvoid ARGBToRGB24Row_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRAWRow_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB565Row_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB4444Row_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB565DitherRow_NEON(const uint8* src_argb, uint8* dst_rgb,\n                                const uint32 dither4, int width);\n\nvoid ARGBToRGBARow_C(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB24Row_C(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRAWRow_C(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB565Row_C(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_C(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB4444Row_C(const uint8* src_argb, uint8* dst_rgb, int width);\n\nvoid J400ToARGBRow_SSE2(const uint8* src_y, uint8* dst_argb, int width);\nvoid J400ToARGBRow_AVX2(const uint8* src_y, uint8* dst_argb, int width);\nvoid J400ToARGBRow_NEON(const uint8* src_y, uint8* dst_argb, int width);\nvoid J400ToARGBRow_C(const uint8* src_y, uint8* dst_argb, int width);\nvoid J400ToARGBRow_Any_SSE2(const uint8* src_y, uint8* dst_argb, int width);\nvoid J400ToARGBRow_Any_AVX2(const uint8* src_y, uint8* dst_argb, int width);\nvoid J400ToARGBRow_Any_NEON(const uint8* src_y, uint8* dst_argb, int width);\n\nvoid I444ToARGBRow_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid I422ToARGBRow_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid I422ToARGBRow_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid I422AlphaToARGBRow_C(const uint8* y_buf,\n                          const uint8* u_buf,\n                          const uint8* v_buf,\n                          const uint8* a_buf,\n                          uint8* dst_argb,\n                          const struct YuvConstants* yuvconstants,\n                          int width);\nvoid I411ToARGBRow_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid NV12ToARGBRow_C(const uint8* src_y,\n                     const uint8* src_uv,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid NV12ToRGB565Row_C(const uint8* src_y,\n                       const uint8* src_uv,\n                       uint8* dst_argb,\n                       const struct YuvConstants* yuvconstants,\n                       int width);\nvoid NV21ToARGBRow_C(const uint8* src_y,\n                     const uint8* src_uv,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid YUY2ToARGBRow_C(const uint8* src_yuy2,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid UYVYToARGBRow_C(const uint8* src_uyvy,\n                     uint8* dst_argb,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid I422ToRGBARow_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_rgba,\n                     const struct YuvConstants* yuvconstants,\n                     int width);\nvoid I422ToRGB24Row_C(const uint8* src_y,\n                      const uint8* src_u,\n                      const uint8* src_v,\n                      uint8* dst_rgb24,\n                      const struct YuvConstants* yuvconstants,\n                      int width);\nvoid I422ToARGB4444Row_C(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb4444,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422ToARGB1555Row_C(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb4444,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422ToRGB565Row_C(const uint8* src_y,\n                       const uint8* src_u,\n                       const uint8* src_v,\n                       uint8* dst_rgb565,\n                       const struct YuvConstants* yuvconstants,\n                       int width);\nvoid I422ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToRGBARow_AVX2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I444ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I444ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I444ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I444ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422AlphaToARGBRow_SSSE3(const uint8* y_buf,\n                              const uint8* u_buf,\n                              const uint8* v_buf,\n                              const uint8* a_buf,\n                              uint8* dst_argb,\n                              const struct YuvConstants* yuvconstants,\n                              int width);\nvoid I422AlphaToARGBRow_AVX2(const uint8* y_buf,\n                             const uint8* u_buf,\n                             const uint8* v_buf,\n                             const uint8* a_buf,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I411ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I411ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid NV12ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_uv,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid NV12ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_uv,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid NV12ToRGB565Row_SSSE3(const uint8* src_y,\n                           const uint8* src_uv,\n                           uint8* dst_argb,\n                           const struct YuvConstants* yuvconstants,\n                           int width);\nvoid NV12ToRGB565Row_AVX2(const uint8* src_y,\n                          const uint8* src_uv,\n                          uint8* dst_argb,\n                          const struct YuvConstants* yuvconstants,\n                          int width);\nvoid NV21ToARGBRow_SSSE3(const uint8* src_y,\n                         const uint8* src_uv,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid NV21ToARGBRow_AVX2(const uint8* src_y,\n                        const uint8* src_uv,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid YUY2ToARGBRow_SSSE3(const uint8* src_yuy2,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid UYVYToARGBRow_SSSE3(const uint8* src_uyvy,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid YUY2ToARGBRow_AVX2(const uint8* src_yuy2,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid UYVYToARGBRow_AVX2(const uint8* src_uyvy,\n                        uint8* dst_argb,\n                        const struct YuvConstants* yuvconstants,\n                        int width);\nvoid I422ToRGBARow_SSSE3(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_rgba,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422ToARGB4444Row_SSSE3(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422ToARGB4444Row_AVX2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToARGB1555Row_SSSE3(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422ToARGB1555Row_AVX2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToRGB565Row_SSSE3(const uint8* src_y,\n                           const uint8* src_u,\n                           const uint8* src_v,\n                           uint8* dst_argb,\n                           const struct YuvConstants* yuvconstants,\n                           int width);\nvoid I422ToRGB565Row_AVX2(const uint8* src_y,\n                          const uint8* src_u,\n                          const uint8* src_v,\n                          uint8* dst_argb,\n                          const struct YuvConstants* yuvconstants,\n                          int width);\nvoid I422ToRGB24Row_SSSE3(const uint8* src_y,\n                          const uint8* src_u,\n                          const uint8* src_v,\n                          uint8* dst_rgb24,\n                          const struct YuvConstants* yuvconstants,\n                          int width);\nvoid I422ToRGB24Row_AVX2(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_rgb24,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422ToARGBRow_Any_AVX2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToRGBARow_Any_AVX2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I444ToARGBRow_Any_SSSE3(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I444ToARGBRow_Any_AVX2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToARGBRow_Any_SSSE3(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422AlphaToARGBRow_Any_SSSE3(const uint8* y_buf,\n                                  const uint8* u_buf,\n                                  const uint8* v_buf,\n                                  const uint8* a_buf,\n                                  uint8* dst_argb,\n                                  const struct YuvConstants* yuvconstants,\n                                  int width);\nvoid I422AlphaToARGBRow_Any_AVX2(const uint8* y_buf,\n                                 const uint8* u_buf,\n                                 const uint8* v_buf,\n                                 const uint8* a_buf,\n                                 uint8* dst_argb,\n                                 const struct YuvConstants* yuvconstants,\n                                 int width);\nvoid I411ToARGBRow_Any_SSSE3(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I411ToARGBRow_Any_AVX2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid NV12ToARGBRow_Any_SSSE3(const uint8* src_y,\n                             const uint8* src_uv,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid NV12ToARGBRow_Any_AVX2(const uint8* src_y,\n                            const uint8* src_uv,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid NV21ToARGBRow_Any_SSSE3(const uint8* src_y,\n                             const uint8* src_vu,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid NV21ToARGBRow_Any_AVX2(const uint8* src_y,\n                            const uint8* src_vu,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid NV12ToRGB565Row_Any_SSSE3(const uint8* src_y,\n                               const uint8* src_uv,\n                               uint8* dst_argb,\n                               const struct YuvConstants* yuvconstants,\n                               int width);\nvoid NV12ToRGB565Row_Any_AVX2(const uint8* src_y,\n                              const uint8* src_uv,\n                              uint8* dst_argb,\n                              const struct YuvConstants* yuvconstants,\n                              int width);\nvoid YUY2ToARGBRow_Any_SSSE3(const uint8* src_yuy2,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid UYVYToARGBRow_Any_SSSE3(const uint8* src_uyvy,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid YUY2ToARGBRow_Any_AVX2(const uint8* src_yuy2,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid UYVYToARGBRow_Any_AVX2(const uint8* src_uyvy,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToRGBARow_Any_SSSE3(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_rgba,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422ToARGB4444Row_Any_SSSE3(const uint8* src_y,\n                                 const uint8* src_u,\n                                 const uint8* src_v,\n                                 uint8* dst_rgba,\n                                 const struct YuvConstants* yuvconstants,\n                                 int width);\nvoid I422ToARGB4444Row_Any_AVX2(const uint8* src_y,\n                                const uint8* src_u,\n                                const uint8* src_v,\n                                uint8* dst_rgba,\n                                const struct YuvConstants* yuvconstants,\n                                int width);\nvoid I422ToARGB1555Row_Any_SSSE3(const uint8* src_y,\n                                 const uint8* src_u,\n                                 const uint8* src_v,\n                                 uint8* dst_rgba,\n                                 const struct YuvConstants* yuvconstants,\n                                 int width);\nvoid I422ToARGB1555Row_Any_AVX2(const uint8* src_y,\n                                const uint8* src_u,\n                                const uint8* src_v,\n                                uint8* dst_rgba,\n                                const struct YuvConstants* yuvconstants,\n                                int width);\nvoid I422ToRGB565Row_Any_SSSE3(const uint8* src_y,\n                               const uint8* src_u,\n                               const uint8* src_v,\n                               uint8* dst_rgba,\n                               const struct YuvConstants* yuvconstants,\n                               int width);\nvoid I422ToRGB565Row_Any_AVX2(const uint8* src_y,\n                              const uint8* src_u,\n                              const uint8* src_v,\n                              uint8* dst_rgba,\n                              const struct YuvConstants* yuvconstants,\n                              int width);\nvoid I422ToRGB24Row_Any_SSSE3(const uint8* src_y,\n                              const uint8* src_u,\n                              const uint8* src_v,\n                              uint8* dst_argb,\n                              const struct YuvConstants* yuvconstants,\n                              int width);\nvoid I422ToRGB24Row_Any_AVX2(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\n\nvoid I400ToARGBRow_C(const uint8* src_y, uint8* dst_argb, int width);\nvoid I400ToARGBRow_SSE2(const uint8* src_y, uint8* dst_argb, int width);\nvoid I400ToARGBRow_AVX2(const uint8* src_y, uint8* dst_argb, int width);\nvoid I400ToARGBRow_NEON(const uint8* src_y, uint8* dst_argb, int width);\nvoid I400ToARGBRow_Any_SSE2(const uint8* src_y, uint8* dst_argb, int width);\nvoid I400ToARGBRow_Any_AVX2(const uint8* src_y, uint8* dst_argb, int width);\nvoid I400ToARGBRow_Any_NEON(const uint8* src_y, uint8* dst_argb, int width);\n\n// ARGB preattenuated alpha blend.\nvoid ARGBBlendRow_SSSE3(const uint8* src_argb, const uint8* src_argb1,\n                        uint8* dst_argb, int width);\nvoid ARGBBlendRow_NEON(const uint8* src_argb, const uint8* src_argb1,\n                       uint8* dst_argb, int width);\nvoid ARGBBlendRow_C(const uint8* src_argb, const uint8* src_argb1,\n                    uint8* dst_argb, int width);\n\n// Unattenuated planar alpha blend.\nvoid BlendPlaneRow_SSSE3(const uint8* src0, const uint8* src1,\n                         const uint8* alpha, uint8* dst, int width);\nvoid BlendPlaneRow_Any_SSSE3(const uint8* src0, const uint8* src1,\n                             const uint8* alpha, uint8* dst, int width);\nvoid BlendPlaneRow_AVX2(const uint8* src0, const uint8* src1,\n                        const uint8* alpha, uint8* dst, int width);\nvoid BlendPlaneRow_Any_AVX2(const uint8* src0, const uint8* src1,\n                            const uint8* alpha, uint8* dst, int width);\nvoid BlendPlaneRow_C(const uint8* src0, const uint8* src1,\n                     const uint8* alpha, uint8* dst, int width);\n\n// ARGB multiply images. Same API as Blend, but these require\n// pointer and width alignment for SSE2.\nvoid ARGBMultiplyRow_C(const uint8* src_argb, const uint8* src_argb1,\n                       uint8* dst_argb, int width);\nvoid ARGBMultiplyRow_SSE2(const uint8* src_argb, const uint8* src_argb1,\n                          uint8* dst_argb, int width);\nvoid ARGBMultiplyRow_Any_SSE2(const uint8* src_argb, const uint8* src_argb1,\n                              uint8* dst_argb, int width);\nvoid ARGBMultiplyRow_AVX2(const uint8* src_argb, const uint8* src_argb1,\n                          uint8* dst_argb, int width);\nvoid ARGBMultiplyRow_Any_AVX2(const uint8* src_argb, const uint8* src_argb1,\n                              uint8* dst_argb, int width);\nvoid ARGBMultiplyRow_NEON(const uint8* src_argb, const uint8* src_argb1,\n                          uint8* dst_argb, int width);\nvoid ARGBMultiplyRow_Any_NEON(const uint8* src_argb, const uint8* src_argb1,\n                              uint8* dst_argb, int width);\n\n// ARGB add images.\nvoid ARGBAddRow_C(const uint8* src_argb, const uint8* src_argb1,\n                  uint8* dst_argb, int width);\nvoid ARGBAddRow_SSE2(const uint8* src_argb, const uint8* src_argb1,\n                     uint8* dst_argb, int width);\nvoid ARGBAddRow_Any_SSE2(const uint8* src_argb, const uint8* src_argb1,\n                         uint8* dst_argb, int width);\nvoid ARGBAddRow_AVX2(const uint8* src_argb, const uint8* src_argb1,\n                     uint8* dst_argb, int width);\nvoid ARGBAddRow_Any_AVX2(const uint8* src_argb, const uint8* src_argb1,\n                         uint8* dst_argb, int width);\nvoid ARGBAddRow_NEON(const uint8* src_argb, const uint8* src_argb1,\n                     uint8* dst_argb, int width);\nvoid ARGBAddRow_Any_NEON(const uint8* src_argb, const uint8* src_argb1,\n                         uint8* dst_argb, int width);\n\n// ARGB subtract images. Same API as Blend, but these require\n// pointer and width alignment for SSE2.\nvoid ARGBSubtractRow_C(const uint8* src_argb, const uint8* src_argb1,\n                       uint8* dst_argb, int width);\nvoid ARGBSubtractRow_SSE2(const uint8* src_argb, const uint8* src_argb1,\n                          uint8* dst_argb, int width);\nvoid ARGBSubtractRow_Any_SSE2(const uint8* src_argb, const uint8* src_argb1,\n                              uint8* dst_argb, int width);\nvoid ARGBSubtractRow_AVX2(const uint8* src_argb, const uint8* src_argb1,\n                          uint8* dst_argb, int width);\nvoid ARGBSubtractRow_Any_AVX2(const uint8* src_argb, const uint8* src_argb1,\n                              uint8* dst_argb, int width);\nvoid ARGBSubtractRow_NEON(const uint8* src_argb, const uint8* src_argb1,\n                          uint8* dst_argb, int width);\nvoid ARGBSubtractRow_Any_NEON(const uint8* src_argb, const uint8* src_argb1,\n                              uint8* dst_argb, int width);\n\nvoid ARGBToRGB24Row_Any_SSSE3(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRAWRow_Any_SSSE3(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB565Row_Any_SSE2(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_Any_SSE2(const uint8* src_argb, uint8* dst_rgb,\n                                int width);\nvoid ARGBToARGB4444Row_Any_SSE2(const uint8* src_argb, uint8* dst_rgb,\n                                int width);\n\nvoid ARGBToRGB565DitherRow_Any_SSE2(const uint8* src_argb, uint8* dst_rgb,\n                                    const uint32 dither4, int width);\nvoid ARGBToRGB565DitherRow_Any_AVX2(const uint8* src_argb, uint8* dst_rgb,\n                                    const uint32 dither4, int width);\n\nvoid ARGBToRGB565Row_Any_AVX2(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_Any_AVX2(const uint8* src_argb, uint8* dst_rgb,\n                                int width);\nvoid ARGBToARGB4444Row_Any_AVX2(const uint8* src_argb, uint8* dst_rgb,\n                                int width);\n\nvoid ARGBToRGB24Row_Any_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRAWRow_Any_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToRGB565Row_Any_NEON(const uint8* src_argb, uint8* dst_rgb, int width);\nvoid ARGBToARGB1555Row_Any_NEON(const uint8* src_argb, uint8* dst_rgb,\n                                int width);\nvoid ARGBToARGB4444Row_Any_NEON(const uint8* src_argb, uint8* dst_rgb,\n                                int width);\nvoid ARGBToRGB565DitherRow_Any_NEON(const uint8* src_argb, uint8* dst_rgb,\n                                    const uint32 dither4, int width);\n\nvoid I444ToARGBRow_Any_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToARGBRow_Any_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422AlphaToARGBRow_Any_NEON(const uint8* src_y,\n                                 const uint8* src_u,\n                                 const uint8* src_v,\n                                 const uint8* src_a,\n                                 uint8* dst_argb,\n                                 const struct YuvConstants* yuvconstants,\n                                 int width);\nvoid I411ToARGBRow_Any_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToRGBARow_Any_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToRGB24Row_Any_NEON(const uint8* src_y,\n                             const uint8* src_u,\n                             const uint8* src_v,\n                             uint8* dst_argb,\n                             const struct YuvConstants* yuvconstants,\n                             int width);\nvoid I422ToARGB4444Row_Any_NEON(const uint8* src_y,\n                                const uint8* src_u,\n                                const uint8* src_v,\n                                uint8* dst_argb,\n                                const struct YuvConstants* yuvconstants,\n                                int width);\nvoid I422ToARGB1555Row_Any_NEON(const uint8* src_y,\n                                const uint8* src_u,\n                                const uint8* src_v,\n                                uint8* dst_argb,\n                                const struct YuvConstants* yuvconstants,\n                                int width);\nvoid I422ToRGB565Row_Any_NEON(const uint8* src_y,\n                              const uint8* src_u,\n                              const uint8* src_v,\n                              uint8* dst_argb,\n                              const struct YuvConstants* yuvconstants,\n                              int width);\nvoid NV12ToARGBRow_Any_NEON(const uint8* src_y,\n                            const uint8* src_uv,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid NV21ToARGBRow_Any_NEON(const uint8* src_y,\n                            const uint8* src_vu,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid NV12ToRGB565Row_Any_NEON(const uint8* src_y,\n                              const uint8* src_uv,\n                              uint8* dst_argb,\n                              const struct YuvConstants* yuvconstants,\n                              int width);\nvoid YUY2ToARGBRow_Any_NEON(const uint8* src_yuy2,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid UYVYToARGBRow_Any_NEON(const uint8* src_uyvy,\n                            uint8* dst_argb,\n                            const struct YuvConstants* yuvconstants,\n                            int width);\nvoid I422ToARGBRow_DSPR2(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\nvoid I422ToARGBRow_DSPR2(const uint8* src_y,\n                         const uint8* src_u,\n                         const uint8* src_v,\n                         uint8* dst_argb,\n                         const struct YuvConstants* yuvconstants,\n                         int width);\n\nvoid YUY2ToYRow_AVX2(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_AVX2(const uint8* src_yuy2, int stride_yuy2,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_AVX2(const uint8* src_yuy2,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToYRow_SSE2(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_SSE2(const uint8* src_yuy2, int stride_yuy2,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_SSE2(const uint8* src_yuy2,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToYRow_NEON(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_NEON(const uint8* src_yuy2, int stride_yuy2,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_NEON(const uint8* src_yuy2,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToYRow_C(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_C(const uint8* src_yuy2, int stride_yuy2,\n                   uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_C(const uint8* src_yuy2,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToYRow_Any_AVX2(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_Any_AVX2(const uint8* src_yuy2, int stride_yuy2,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_Any_AVX2(const uint8* src_yuy2,\n                             uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToYRow_Any_SSE2(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_Any_SSE2(const uint8* src_yuy2, int stride_yuy2,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_Any_SSE2(const uint8* src_yuy2,\n                             uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToYRow_Any_NEON(const uint8* src_yuy2, uint8* dst_y, int width);\nvoid YUY2ToUVRow_Any_NEON(const uint8* src_yuy2, int stride_yuy2,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid YUY2ToUV422Row_Any_NEON(const uint8* src_yuy2,\n                             uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_AVX2(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_AVX2(const uint8* src_uyvy, int stride_uyvy,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_AVX2(const uint8* src_uyvy,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_SSE2(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_SSE2(const uint8* src_uyvy, int stride_uyvy,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_SSE2(const uint8* src_uyvy,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_AVX2(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_AVX2(const uint8* src_uyvy, int stride_uyvy,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_AVX2(const uint8* src_uyvy,\n                         uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_NEON(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_NEON(const uint8* src_uyvy, int stride_uyvy,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_NEON(const uint8* src_uyvy,\n                         uint8* dst_u, uint8* dst_v, int width);\n\nvoid UYVYToYRow_C(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_C(const uint8* src_uyvy, int stride_uyvy,\n                   uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_C(const uint8* src_uyvy,\n                      uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_Any_AVX2(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_Any_AVX2(const uint8* src_uyvy, int stride_uyvy,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_Any_AVX2(const uint8* src_uyvy,\n                             uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_Any_SSE2(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_Any_SSE2(const uint8* src_uyvy, int stride_uyvy,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_Any_SSE2(const uint8* src_uyvy,\n                             uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToYRow_Any_NEON(const uint8* src_uyvy, uint8* dst_y, int width);\nvoid UYVYToUVRow_Any_NEON(const uint8* src_uyvy, int stride_uyvy,\n                          uint8* dst_u, uint8* dst_v, int width);\nvoid UYVYToUV422Row_Any_NEON(const uint8* src_uyvy,\n                             uint8* dst_u, uint8* dst_v, int width);\n\nvoid I422ToYUY2Row_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_yuy2, int width);\nvoid I422ToUYVYRow_C(const uint8* src_y,\n                     const uint8* src_u,\n                     const uint8* src_v,\n                     uint8* dst_uyvy, int width);\nvoid I422ToYUY2Row_SSE2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_yuy2, int width);\nvoid I422ToUYVYRow_SSE2(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_uyvy, int width);\nvoid I422ToYUY2Row_Any_SSE2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_yuy2, int width);\nvoid I422ToUYVYRow_Any_SSE2(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_uyvy, int width);\nvoid I422ToYUY2Row_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_yuy2, int width);\nvoid I422ToUYVYRow_NEON(const uint8* src_y,\n                        const uint8* src_u,\n                        const uint8* src_v,\n                        uint8* dst_uyvy, int width);\nvoid I422ToYUY2Row_Any_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_yuy2, int width);\nvoid I422ToUYVYRow_Any_NEON(const uint8* src_y,\n                            const uint8* src_u,\n                            const uint8* src_v,\n                            uint8* dst_uyvy, int width);\n\n// Effects related row functions.\nvoid ARGBAttenuateRow_C(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBAttenuateRow_SSSE3(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBAttenuateRow_AVX2(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBAttenuateRow_NEON(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBAttenuateRow_Any_SSE2(const uint8* src_argb, uint8* dst_argb,\n                               int width);\nvoid ARGBAttenuateRow_Any_SSSE3(const uint8* src_argb, uint8* dst_argb,\n                                int width);\nvoid ARGBAttenuateRow_Any_AVX2(const uint8* src_argb, uint8* dst_argb,\n                               int width);\nvoid ARGBAttenuateRow_Any_NEON(const uint8* src_argb, uint8* dst_argb,\n                               int width);\n\n// Inverse table for unattenuate, shared by C and SSE2.\nextern const uint32 fixed_invtbl8[256];\nvoid ARGBUnattenuateRow_C(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBUnattenuateRow_SSE2(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBUnattenuateRow_AVX2(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBUnattenuateRow_Any_SSE2(const uint8* src_argb, uint8* dst_argb,\n                                 int width);\nvoid ARGBUnattenuateRow_Any_AVX2(const uint8* src_argb, uint8* dst_argb,\n                                 int width);\n\nvoid ARGBGrayRow_C(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBGrayRow_SSSE3(const uint8* src_argb, uint8* dst_argb, int width);\nvoid ARGBGrayRow_NEON(const uint8* src_argb, uint8* dst_argb, int width);\n\nvoid ARGBSepiaRow_C(uint8* dst_argb, int width);\nvoid ARGBSepiaRow_SSSE3(uint8* dst_argb, int width);\nvoid ARGBSepiaRow_NEON(uint8* dst_argb, int width);\n\nvoid ARGBColorMatrixRow_C(const uint8* src_argb, uint8* dst_argb,\n                          const int8* matrix_argb, int width);\nvoid ARGBColorMatrixRow_SSSE3(const uint8* src_argb, uint8* dst_argb,\n                              const int8* matrix_argb, int width);\nvoid ARGBColorMatrixRow_NEON(const uint8* src_argb, uint8* dst_argb,\n                             const int8* matrix_argb, int width);\n\nvoid ARGBColorTableRow_C(uint8* dst_argb, const uint8* table_argb, int width);\nvoid ARGBColorTableRow_X86(uint8* dst_argb, const uint8* table_argb, int width);\n\nvoid RGBColorTableRow_C(uint8* dst_argb, const uint8* table_argb, int width);\nvoid RGBColorTableRow_X86(uint8* dst_argb, const uint8* table_argb, int width);\n\nvoid ARGBQuantizeRow_C(uint8* dst_argb, int scale, int interval_size,\n                       int interval_offset, int width);\nvoid ARGBQuantizeRow_SSE2(uint8* dst_argb, int scale, int interval_size,\n                          int interval_offset, int width);\nvoid ARGBQuantizeRow_NEON(uint8* dst_argb, int scale, int interval_size,\n                          int interval_offset, int width);\n\nvoid ARGBShadeRow_C(const uint8* src_argb, uint8* dst_argb, int width,\n                    uint32 value);\nvoid ARGBShadeRow_SSE2(const uint8* src_argb, uint8* dst_argb, int width,\n                       uint32 value);\nvoid ARGBShadeRow_NEON(const uint8* src_argb, uint8* dst_argb, int width,\n                       uint32 value);\n\n// Used for blur.\nvoid CumulativeSumToAverageRow_SSE2(const int32* topleft, const int32* botleft,\n                                    int width, int area, uint8* dst, int count);\nvoid ComputeCumulativeSumRow_SSE2(const uint8* row, int32* cumsum,\n                                  const int32* previous_cumsum, int width);\n\nvoid CumulativeSumToAverageRow_C(const int32* topleft, const int32* botleft,\n                                 int width, int area, uint8* dst, int count);\nvoid ComputeCumulativeSumRow_C(const uint8* row, int32* cumsum,\n                               const int32* previous_cumsum, int width);\n\nLIBYUV_API\nvoid ARGBAffineRow_C(const uint8* src_argb, int src_argb_stride,\n                     uint8* dst_argb, const float* uv_dudv, int width);\nLIBYUV_API\nvoid ARGBAffineRow_SSE2(const uint8* src_argb, int src_argb_stride,\n                        uint8* dst_argb, const float* uv_dudv, int width);\n\n// Used for I420Scale, ARGBScale, and ARGBInterpolate.\nvoid InterpolateRow_C(uint8* dst_ptr, const uint8* src_ptr,\n                      ptrdiff_t src_stride_ptr,\n                      int width, int source_y_fraction);\nvoid InterpolateRow_SSSE3(uint8* dst_ptr, const uint8* src_ptr,\n                          ptrdiff_t src_stride_ptr, int width,\n                          int source_y_fraction);\nvoid InterpolateRow_AVX2(uint8* dst_ptr, const uint8* src_ptr,\n                         ptrdiff_t src_stride_ptr, int width,\n                         int source_y_fraction);\nvoid InterpolateRow_NEON(uint8* dst_ptr, const uint8* src_ptr,\n                         ptrdiff_t src_stride_ptr, int width,\n                         int source_y_fraction);\nvoid InterpolateRow_DSPR2(uint8* dst_ptr, const uint8* src_ptr,\n                          ptrdiff_t src_stride_ptr, int width,\n                          int source_y_fraction);\nvoid InterpolateRow_Any_NEON(uint8* dst_ptr, const uint8* src_ptr,\n                             ptrdiff_t src_stride_ptr, int width,\n                             int source_y_fraction);\nvoid InterpolateRow_Any_SSSE3(uint8* dst_ptr, const uint8* src_ptr,\n                              ptrdiff_t src_stride_ptr, int width,\n                              int source_y_fraction);\nvoid InterpolateRow_Any_AVX2(uint8* dst_ptr, const uint8* src_ptr,\n                             ptrdiff_t src_stride_ptr, int width,\n                             int source_y_fraction);\nvoid InterpolateRow_Any_DSPR2(uint8* dst_ptr, const uint8* src_ptr,\n                              ptrdiff_t src_stride_ptr, int width,\n                              int source_y_fraction);\n\nvoid InterpolateRow_16_C(uint16* dst_ptr, const uint16* src_ptr,\n                         ptrdiff_t src_stride_ptr,\n                         int width, int source_y_fraction);\n\n// Sobel images.\nvoid SobelXRow_C(const uint8* src_y0, const uint8* src_y1, const uint8* src_y2,\n                 uint8* dst_sobelx, int width);\nvoid SobelXRow_SSE2(const uint8* src_y0, const uint8* src_y1,\n                    const uint8* src_y2, uint8* dst_sobelx, int width);\nvoid SobelXRow_NEON(const uint8* src_y0, const uint8* src_y1,\n                    const uint8* src_y2, uint8* dst_sobelx, int width);\nvoid SobelYRow_C(const uint8* src_y0, const uint8* src_y1,\n                 uint8* dst_sobely, int width);\nvoid SobelYRow_SSE2(const uint8* src_y0, const uint8* src_y1,\n                    uint8* dst_sobely, int width);\nvoid SobelYRow_NEON(const uint8* src_y0, const uint8* src_y1,\n                    uint8* dst_sobely, int width);\nvoid SobelRow_C(const uint8* src_sobelx, const uint8* src_sobely,\n                uint8* dst_argb, int width);\nvoid SobelRow_SSE2(const uint8* src_sobelx, const uint8* src_sobely,\n                   uint8* dst_argb, int width);\nvoid SobelRow_NEON(const uint8* src_sobelx, const uint8* src_sobely,\n                   uint8* dst_argb, int width);\nvoid SobelToPlaneRow_C(const uint8* src_sobelx, const uint8* src_sobely,\n                       uint8* dst_y, int width);\nvoid SobelToPlaneRow_SSE2(const uint8* src_sobelx, const uint8* src_sobely,\n                          uint8* dst_y, int width);\nvoid SobelToPlaneRow_NEON(const uint8* src_sobelx, const uint8* src_sobely,\n                          uint8* dst_y, int width);\nvoid SobelXYRow_C(const uint8* src_sobelx, const uint8* src_sobely,\n                  uint8* dst_argb, int width);\nvoid SobelXYRow_SSE2(const uint8* src_sobelx, const uint8* src_sobely,\n                     uint8* dst_argb, int width);\nvoid SobelXYRow_NEON(const uint8* src_sobelx, const uint8* src_sobely,\n                     uint8* dst_argb, int width);\nvoid SobelRow_Any_SSE2(const uint8* src_sobelx, const uint8* src_sobely,\n                       uint8* dst_argb, int width);\nvoid SobelRow_Any_NEON(const uint8* src_sobelx, const uint8* src_sobely,\n                       uint8* dst_argb, int width);\nvoid SobelToPlaneRow_Any_SSE2(const uint8* src_sobelx, const uint8* src_sobely,\n                              uint8* dst_y, int width);\nvoid SobelToPlaneRow_Any_NEON(const uint8* src_sobelx, const uint8* src_sobely,\n                              uint8* dst_y, int width);\nvoid SobelXYRow_Any_SSE2(const uint8* src_sobelx, const uint8* src_sobely,\n                         uint8* dst_argb, int width);\nvoid SobelXYRow_Any_NEON(const uint8* src_sobelx, const uint8* src_sobely,\n                         uint8* dst_argb, int width);\n\nvoid ARGBPolynomialRow_C(const uint8* src_argb,\n                         uint8* dst_argb, const float* poly,\n                         int width);\nvoid ARGBPolynomialRow_SSE2(const uint8* src_argb,\n                            uint8* dst_argb, const float* poly,\n                            int width);\nvoid ARGBPolynomialRow_AVX2(const uint8* src_argb,\n                            uint8* dst_argb, const float* poly,\n                            int width);\n\n// Scale and convert to half float.\nvoid HalfFloatRow_C(const uint16* src, uint16* dst, float scale, int width);\nvoid HalfFloatRow_AVX2(const uint16* src, uint16* dst, float scale, int width);\nvoid HalfFloatRow_Any_AVX2(const uint16* src, uint16* dst, float scale,\n                           int width);\nvoid HalfFloatRow_SSE2(const uint16* src, uint16* dst, float scale, int width);\nvoid HalfFloatRow_Any_SSE2(const uint16* src, uint16* dst, float scale,\n                           int width);\n\nvoid ARGBLumaColorTableRow_C(const uint8* src_argb, uint8* dst_argb, int width,\n                             const uint8* luma, uint32 lumacoeff);\nvoid ARGBLumaColorTableRow_SSSE3(const uint8* src_argb, uint8* dst_argb,\n                                 int width,\n                                 const uint8* luma, uint32 lumacoeff);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_ROW_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/scale.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_SCALE_H_\n#define INCLUDE_LIBYUV_SCALE_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n// Supported filtering.\ntypedef enum FilterMode {\n  kFilterNone = 0,  // Point sample; Fastest.\n  kFilterLinear = 1,  // Filter horizontally only.\n  kFilterBilinear = 2,  // Faster than box, but lower quality scaling down.\n  kFilterBox = 3  // Highest quality.\n} FilterModeEnum;\n\n// Scale a YUV plane.\nLIBYUV_API\nvoid ScalePlane(const uint8* src, int src_stride,\n                int src_width, int src_height,\n                uint8* dst, int dst_stride,\n                int dst_width, int dst_height,\n                enum FilterMode filtering);\n\nLIBYUV_API\nvoid ScalePlane_16(const uint16* src, int src_stride,\n                   int src_width, int src_height,\n                   uint16* dst, int dst_stride,\n                   int dst_width, int dst_height,\n                   enum FilterMode filtering);\n\n// Scales a YUV 4:2:0 image from the src width and height to the\n// dst width and height.\n// If filtering is kFilterNone, a simple nearest-neighbor algorithm is\n// used. This produces basic (blocky) quality at the fastest speed.\n// If filtering is kFilterBilinear, interpolation is used to produce a better\n// quality image, at the expense of speed.\n// If filtering is kFilterBox, averaging is used to produce ever better\n// quality image, at further expense of speed.\n// Returns 0 if successful.\n\nLIBYUV_API\nint I420Scale(const uint8* src_y, int src_stride_y,\n              const uint8* src_u, int src_stride_u,\n              const uint8* src_v, int src_stride_v,\n              int src_width, int src_height,\n              uint8* dst_y, int dst_stride_y,\n              uint8* dst_u, int dst_stride_u,\n              uint8* dst_v, int dst_stride_v,\n              int dst_width, int dst_height,\n              enum FilterMode filtering);\n\nLIBYUV_API\nint I420Scale_16(const uint16* src_y, int src_stride_y,\n                 const uint16* src_u, int src_stride_u,\n                 const uint16* src_v, int src_stride_v,\n                 int src_width, int src_height,\n                 uint16* dst_y, int dst_stride_y,\n                 uint16* dst_u, int dst_stride_u,\n                 uint16* dst_v, int dst_stride_v,\n                 int dst_width, int dst_height,\n                 enum FilterMode filtering);\n\n#ifdef __cplusplus\n// Legacy API.  Deprecated.\nLIBYUV_API\nint Scale(const uint8* src_y, const uint8* src_u, const uint8* src_v,\n          int src_stride_y, int src_stride_u, int src_stride_v,\n          int src_width, int src_height,\n          uint8* dst_y, uint8* dst_u, uint8* dst_v,\n          int dst_stride_y, int dst_stride_u, int dst_stride_v,\n          int dst_width, int dst_height,\n          LIBYUV_BOOL interpolate);\n\n// Legacy API.  Deprecated.\nLIBYUV_API\nint ScaleOffset(const uint8* src_i420, int src_width, int src_height,\n                uint8* dst_i420, int dst_width, int dst_height, int dst_yoffset,\n                LIBYUV_BOOL interpolate);\n\n// For testing, allow disabling of specialized scalers.\nLIBYUV_API\nvoid SetUseReferenceImpl(LIBYUV_BOOL use);\n#endif  // __cplusplus\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_SCALE_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/scale_argb.h",
    "content": "/*\n *  Copyright 2012 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_SCALE_ARGB_H_\n#define INCLUDE_LIBYUV_SCALE_ARGB_H_\n\n#include \"libyuv/basic_types.h\"\n#include \"libyuv/scale.h\"  // For FilterMode\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\nLIBYUV_API\nint ARGBScale(const uint8* src_argb, int src_stride_argb,\n              int src_width, int src_height,\n              uint8* dst_argb, int dst_stride_argb,\n              int dst_width, int dst_height,\n              enum FilterMode filtering);\n\n// Clipped scale takes destination rectangle coordinates for clip values.\nLIBYUV_API\nint ARGBScaleClip(const uint8* src_argb, int src_stride_argb,\n                  int src_width, int src_height,\n                  uint8* dst_argb, int dst_stride_argb,\n                  int dst_width, int dst_height,\n                  int clip_x, int clip_y, int clip_width, int clip_height,\n                  enum FilterMode filtering);\n\n// Scale with YUV conversion to ARGB and clipping.\nLIBYUV_API\nint YUVToARGBScaleClip(const uint8* src_y, int src_stride_y,\n                       const uint8* src_u, int src_stride_u,\n                       const uint8* src_v, int src_stride_v,\n                       uint32 src_fourcc,\n                       int src_width, int src_height,\n                       uint8* dst_argb, int dst_stride_argb,\n                       uint32 dst_fourcc,\n                       int dst_width, int dst_height,\n                       int clip_x, int clip_y, int clip_width, int clip_height,\n                       enum FilterMode filtering);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_SCALE_ARGB_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/scale_row.h",
    "content": "/*\n *  Copyright 2013 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_SCALE_ROW_H_\n#define INCLUDE_LIBYUV_SCALE_ROW_H_\n\n#include \"libyuv/basic_types.h\"\n#include \"libyuv/scale.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n#if defined(__pnacl__) || defined(__CLR_VER) || \\\n    (defined(__i386__) && !defined(__SSE2__))\n#define LIBYUV_DISABLE_X86\n#endif\n// MemorySanitizer does not support assembly code yet. http://crbug.com/344505\n#if defined(__has_feature)\n#if __has_feature(memory_sanitizer)\n#define LIBYUV_DISABLE_X86\n#endif\n#endif\n\n// GCC >= 4.7.0 required for AVX2.\n#if defined(__GNUC__) && (defined(__x86_64__) || defined(__i386__))\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && (__GNUC_MINOR__ >= 7))\n#define GCC_HAS_AVX2 1\n#endif  // GNUC >= 4.7\n#endif  // __GNUC__\n\n// clang >= 3.4.0 required for AVX2.\n#if defined(__clang__) && (defined(__x86_64__) || defined(__i386__))\n#if (__clang_major__ > 3) || (__clang_major__ == 3 && (__clang_minor__ >= 4))\n#define CLANG_HAS_AVX2 1\n#endif  // clang >= 3.4\n#endif  // __clang__\n\n// Visual C 2012 required for AVX2.\n#if defined(_M_IX86) && !defined(__clang__) && \\\n    defined(_MSC_VER) && _MSC_VER >= 1700\n#define VISUALC_HAS_AVX2 1\n#endif  // VisualStudio >= 2012\n\n// The following are available on all x86 platforms:\n#if !defined(LIBYUV_DISABLE_X86) && \\\n    (defined(_M_IX86) || defined(__x86_64__) || defined(__i386__))\n#define HAS_FIXEDDIV1_X86\n#define HAS_FIXEDDIV_X86\n#define HAS_SCALEARGBCOLS_SSE2\n#define HAS_SCALEARGBCOLSUP2_SSE2\n#define HAS_SCALEARGBFILTERCOLS_SSSE3\n#define HAS_SCALEARGBROWDOWN2_SSE2\n#define HAS_SCALEARGBROWDOWNEVEN_SSE2\n#define HAS_SCALECOLSUP2_SSE2\n#define HAS_SCALEFILTERCOLS_SSSE3\n#define HAS_SCALEROWDOWN2_SSSE3\n#define HAS_SCALEROWDOWN34_SSSE3\n#define HAS_SCALEROWDOWN38_SSSE3\n#define HAS_SCALEROWDOWN4_SSSE3\n#define HAS_SCALEADDROW_SSE2\n#endif\n\n// The following are available on all x86 platforms, but\n// require VS2012, clang 3.4 or gcc 4.7.\n// The code supports NaCL but requires a new compiler and validator.\n#if !defined(LIBYUV_DISABLE_X86) && (defined(VISUALC_HAS_AVX2) || \\\n    defined(CLANG_HAS_AVX2) || defined(GCC_HAS_AVX2))\n#define HAS_SCALEADDROW_AVX2\n#define HAS_SCALEROWDOWN2_AVX2\n#define HAS_SCALEROWDOWN4_AVX2\n#endif\n\n// The following are available on Neon platforms:\n#if !defined(LIBYUV_DISABLE_NEON) && !defined(__native_client__) && \\\n    (defined(__ARM_NEON__) || defined(LIBYUV_NEON) || defined(__aarch64__))\n#define HAS_SCALEARGBCOLS_NEON\n#define HAS_SCALEARGBROWDOWN2_NEON\n#define HAS_SCALEARGBROWDOWNEVEN_NEON\n#define HAS_SCALEFILTERCOLS_NEON\n#define HAS_SCALEROWDOWN2_NEON\n#define HAS_SCALEROWDOWN34_NEON\n#define HAS_SCALEROWDOWN38_NEON\n#define HAS_SCALEROWDOWN4_NEON\n#define HAS_SCALEARGBFILTERCOLS_NEON\n#endif\n\n// The following are available on Mips platforms:\n#if !defined(LIBYUV_DISABLE_MIPS) && !defined(__native_client__) && \\\n    defined(__mips__) && defined(__mips_dsp) && (__mips_dsp_rev >= 2)\n#define HAS_SCALEROWDOWN2_DSPR2\n#define HAS_SCALEROWDOWN4_DSPR2\n#define HAS_SCALEROWDOWN34_DSPR2\n#define HAS_SCALEROWDOWN38_DSPR2\n#endif\n\n// Scale ARGB vertically with bilinear interpolation.\nvoid ScalePlaneVertical(int src_height,\n                        int dst_width, int dst_height,\n                        int src_stride, int dst_stride,\n                        const uint8* src_argb, uint8* dst_argb,\n                        int x, int y, int dy,\n                        int bpp, enum FilterMode filtering);\n\nvoid ScalePlaneVertical_16(int src_height,\n                           int dst_width, int dst_height,\n                           int src_stride, int dst_stride,\n                           const uint16* src_argb, uint16* dst_argb,\n                           int x, int y, int dy,\n                           int wpp, enum FilterMode filtering);\n\n// Simplify the filtering based on scale factors.\nenum FilterMode ScaleFilterReduce(int src_width, int src_height,\n                                  int dst_width, int dst_height,\n                                  enum FilterMode filtering);\n\n// Divide num by div and return as 16.16 fixed point result.\nint FixedDiv_C(int num, int div);\nint FixedDiv_X86(int num, int div);\n// Divide num - 1 by div - 1 and return as 16.16 fixed point result.\nint FixedDiv1_C(int num, int div);\nint FixedDiv1_X86(int num, int div);\n#ifdef HAS_FIXEDDIV_X86\n#define FixedDiv FixedDiv_X86\n#define FixedDiv1 FixedDiv1_X86\n#else\n#define FixedDiv FixedDiv_C\n#define FixedDiv1 FixedDiv1_C\n#endif\n\n// Compute slope values for stepping.\nvoid ScaleSlope(int src_width, int src_height,\n                int dst_width, int dst_height,\n                enum FilterMode filtering,\n                int* x, int* y, int* dx, int* dy);\n\nvoid ScaleRowDown2_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                     uint8* dst, int dst_width);\nvoid ScaleRowDown2_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                        uint16* dst, int dst_width);\nvoid ScaleRowDown2Linear_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                           uint8* dst, int dst_width);\nvoid ScaleRowDown2Linear_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                              uint16* dst, int dst_width);\nvoid ScaleRowDown2Box_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                        uint8* dst, int dst_width);\nvoid ScaleRowDown2Box_Odd_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst, int dst_width);\nvoid ScaleRowDown2Box_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                           uint16* dst, int dst_width);\nvoid ScaleRowDown4_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                     uint8* dst, int dst_width);\nvoid ScaleRowDown4_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                        uint16* dst, int dst_width);\nvoid ScaleRowDown4Box_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                        uint8* dst, int dst_width);\nvoid ScaleRowDown4Box_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                           uint16* dst, int dst_width);\nvoid ScaleRowDown34_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                      uint8* dst, int dst_width);\nvoid ScaleRowDown34_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                         uint16* dst, int dst_width);\nvoid ScaleRowDown34_0_Box_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* d, int dst_width);\nvoid ScaleRowDown34_0_Box_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                               uint16* d, int dst_width);\nvoid ScaleRowDown34_1_Box_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* d, int dst_width);\nvoid ScaleRowDown34_1_Box_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                               uint16* d, int dst_width);\nvoid ScaleCols_C(uint8* dst_ptr, const uint8* src_ptr,\n                 int dst_width, int x, int dx);\nvoid ScaleCols_16_C(uint16* dst_ptr, const uint16* src_ptr,\n                    int dst_width, int x, int dx);\nvoid ScaleColsUp2_C(uint8* dst_ptr, const uint8* src_ptr,\n                    int dst_width, int, int);\nvoid ScaleColsUp2_16_C(uint16* dst_ptr, const uint16* src_ptr,\n                       int dst_width, int, int);\nvoid ScaleFilterCols_C(uint8* dst_ptr, const uint8* src_ptr,\n                       int dst_width, int x, int dx);\nvoid ScaleFilterCols_16_C(uint16* dst_ptr, const uint16* src_ptr,\n                          int dst_width, int x, int dx);\nvoid ScaleFilterCols64_C(uint8* dst_ptr, const uint8* src_ptr,\n                         int dst_width, int x, int dx);\nvoid ScaleFilterCols64_16_C(uint16* dst_ptr, const uint16* src_ptr,\n                            int dst_width, int x, int dx);\nvoid ScaleRowDown38_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                      uint8* dst, int dst_width);\nvoid ScaleRowDown38_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                         uint16* dst, int dst_width);\nvoid ScaleRowDown38_3_Box_C(const uint8* src_ptr,\n                            ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_3_Box_16_C(const uint16* src_ptr,\n                               ptrdiff_t src_stride,\n                               uint16* dst_ptr, int dst_width);\nvoid ScaleRowDown38_2_Box_C(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_2_Box_16_C(const uint16* src_ptr, ptrdiff_t src_stride,\n                               uint16* dst_ptr, int dst_width);\nvoid ScaleAddRow_C(const uint8* src_ptr, uint16* dst_ptr, int src_width);\nvoid ScaleAddRow_16_C(const uint16* src_ptr, uint32* dst_ptr, int src_width);\nvoid ScaleARGBRowDown2_C(const uint8* src_argb,\n                         ptrdiff_t src_stride,\n                         uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Linear_C(const uint8* src_argb,\n                               ptrdiff_t src_stride,\n                               uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Box_C(const uint8* src_argb, ptrdiff_t src_stride,\n                            uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEven_C(const uint8* src_argb, ptrdiff_t src_stride,\n                            int src_stepx,\n                            uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEvenBox_C(const uint8* src_argb,\n                               ptrdiff_t src_stride,\n                               int src_stepx,\n                               uint8* dst_argb, int dst_width);\nvoid ScaleARGBCols_C(uint8* dst_argb, const uint8* src_argb,\n                     int dst_width, int x, int dx);\nvoid ScaleARGBCols64_C(uint8* dst_argb, const uint8* src_argb,\n                       int dst_width, int x, int dx);\nvoid ScaleARGBColsUp2_C(uint8* dst_argb, const uint8* src_argb,\n                        int dst_width, int, int);\nvoid ScaleARGBFilterCols_C(uint8* dst_argb, const uint8* src_argb,\n                           int dst_width, int x, int dx);\nvoid ScaleARGBFilterCols64_C(uint8* dst_argb, const uint8* src_argb,\n                             int dst_width, int x, int dx);\n\n// Specialized scalers for x86.\nvoid ScaleRowDown2_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                         uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Linear_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Box_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                        uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Linear_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                              uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Box_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                           uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                         uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4Box_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                        uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4Box_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                           uint8* dst_ptr, int dst_width);\n\nvoid ScaleRowDown34_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                          uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_1_Box_SSSE3(const uint8* src_ptr,\n                                ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_0_Box_SSSE3(const uint8* src_ptr,\n                                ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                          uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_3_Box_SSSE3(const uint8* src_ptr,\n                                ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_2_Box_SSSE3(const uint8* src_ptr,\n                                ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                             uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Linear_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                                   uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Box_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Box_Odd_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2_Any_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Linear_Any_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                                  uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Box_Any_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown2Box_Odd_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                             uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4Box_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4_Any_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4Box_Any_AVX2(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\n\nvoid ScaleRowDown34_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                              uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_1_Box_Any_SSSE3(const uint8* src_ptr,\n                                    ptrdiff_t src_stride,\n                                    uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_0_Box_Any_SSSE3(const uint8* src_ptr,\n                                    ptrdiff_t src_stride,\n                                    uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_Any_SSSE3(const uint8* src_ptr, ptrdiff_t src_stride,\n                              uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_3_Box_Any_SSSE3(const uint8* src_ptr,\n                                    ptrdiff_t src_stride,\n                                    uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_2_Box_Any_SSSE3(const uint8* src_ptr,\n                                    ptrdiff_t src_stride,\n                                    uint8* dst_ptr, int dst_width);\n\nvoid ScaleAddRow_SSE2(const uint8* src_ptr, uint16* dst_ptr, int src_width);\nvoid ScaleAddRow_AVX2(const uint8* src_ptr, uint16* dst_ptr, int src_width);\nvoid ScaleAddRow_Any_SSE2(const uint8* src_ptr, uint16* dst_ptr, int src_width);\nvoid ScaleAddRow_Any_AVX2(const uint8* src_ptr, uint16* dst_ptr, int src_width);\n\nvoid ScaleFilterCols_SSSE3(uint8* dst_ptr, const uint8* src_ptr,\n                           int dst_width, int x, int dx);\nvoid ScaleColsUp2_SSE2(uint8* dst_ptr, const uint8* src_ptr,\n                       int dst_width, int x, int dx);\n\n\n// ARGB Column functions\nvoid ScaleARGBCols_SSE2(uint8* dst_argb, const uint8* src_argb,\n                        int dst_width, int x, int dx);\nvoid ScaleARGBFilterCols_SSSE3(uint8* dst_argb, const uint8* src_argb,\n                               int dst_width, int x, int dx);\nvoid ScaleARGBColsUp2_SSE2(uint8* dst_argb, const uint8* src_argb,\n                           int dst_width, int x, int dx);\nvoid ScaleARGBFilterCols_NEON(uint8* dst_argb, const uint8* src_argb,\n                              int dst_width, int x, int dx);\nvoid ScaleARGBCols_NEON(uint8* dst_argb, const uint8* src_argb,\n                        int dst_width, int x, int dx);\nvoid ScaleARGBFilterCols_Any_NEON(uint8* dst_argb, const uint8* src_argb,\n                                  int dst_width, int x, int dx);\nvoid ScaleARGBCols_Any_NEON(uint8* dst_argb, const uint8* src_argb,\n                            int dst_width, int x, int dx);\n\n// ARGB Row functions\nvoid ScaleARGBRowDown2_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                            uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Linear_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                                  uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Box_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                               uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst, int dst_width);\nvoid ScaleARGBRowDown2Linear_NEON(const uint8* src_argb, ptrdiff_t src_stride,\n                                  uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Box_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst, int dst_width);\nvoid ScaleARGBRowDown2_Any_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                                uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Linear_Any_SSE2(const uint8* src_argb,\n                                      ptrdiff_t src_stride,\n                                      uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Box_Any_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                                   uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* dst, int dst_width);\nvoid ScaleARGBRowDown2Linear_Any_NEON(const uint8* src_argb,\n                                      ptrdiff_t src_stride,\n                                      uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDown2Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                                   uint8* dst, int dst_width);\n\nvoid ScaleARGBRowDownEven_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                               int src_stepx, uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEvenBox_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                                  int src_stepx,\n                                  uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEven_NEON(const uint8* src_argb, ptrdiff_t src_stride,\n                               int src_stepx,\n                               uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEvenBox_NEON(const uint8* src_argb, ptrdiff_t src_stride,\n                                  int src_stepx,\n                                  uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEven_Any_SSE2(const uint8* src_argb, ptrdiff_t src_stride,\n                                   int src_stepx,\n                                   uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEvenBox_Any_SSE2(const uint8* src_argb,\n                                      ptrdiff_t src_stride,\n                                      int src_stepx,\n                                      uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEven_Any_NEON(const uint8* src_argb, ptrdiff_t src_stride,\n                                   int src_stepx,\n                                   uint8* dst_argb, int dst_width);\nvoid ScaleARGBRowDownEvenBox_Any_NEON(const uint8* src_argb,\n                                      ptrdiff_t src_stride,\n                                      int src_stepx,\n                                      uint8* dst_argb, int dst_width);\n\n// ScaleRowDown2Box also used by planar functions\n// NEON downscalers with interpolation.\n\n// Note - not static due to reuse in convert for 444 to 420.\nvoid ScaleRowDown2_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                        uint8* dst, int dst_width);\nvoid ScaleRowDown2Linear_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                              uint8* dst, int dst_width);\nvoid ScaleRowDown2Box_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                           uint8* dst, int dst_width);\n\nvoid ScaleRowDown4_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                        uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4Box_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                           uint8* dst_ptr, int dst_width);\n\n// Down scale from 4 to 3 pixels. Use the neon multilane read/write\n//  to load up the every 4th pixel into a 4 different registers.\n// Point samples 32 pixels to 24 pixels.\nvoid ScaleRowDown34_NEON(const uint8* src_ptr,\n                         ptrdiff_t src_stride,\n                         uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_0_Box_NEON(const uint8* src_ptr,\n                               ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_1_Box_NEON(const uint8* src_ptr,\n                               ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\n\n// 32 -> 12\nvoid ScaleRowDown38_NEON(const uint8* src_ptr,\n                         ptrdiff_t src_stride,\n                         uint8* dst_ptr, int dst_width);\n// 32x3 -> 12x1\nvoid ScaleRowDown38_3_Box_NEON(const uint8* src_ptr,\n                               ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\n// 32x2 -> 12x1\nvoid ScaleRowDown38_2_Box_NEON(const uint8* src_ptr,\n                               ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\n\nvoid ScaleRowDown2_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst, int dst_width);\nvoid ScaleRowDown2Linear_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                                  uint8* dst, int dst_width);\nvoid ScaleRowDown2Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst, int dst_width);\nvoid ScaleRowDown2Box_Odd_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst, int dst_width);\nvoid ScaleRowDown4_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown4Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                             uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_0_Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                                   uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown34_1_Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                                   uint8* dst_ptr, int dst_width);\n// 32 -> 12\nvoid ScaleRowDown38_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                             uint8* dst_ptr, int dst_width);\n// 32x3 -> 12x1\nvoid ScaleRowDown38_3_Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\n// 32x2 -> 12x1\nvoid ScaleRowDown38_2_Box_Any_NEON(const uint8* src_ptr, ptrdiff_t src_stride,\n                               uint8* dst_ptr, int dst_width);\n\nvoid ScaleAddRow_NEON(const uint8* src_ptr, uint16* dst_ptr, int src_width);\nvoid ScaleAddRow_Any_NEON(const uint8* src_ptr, uint16* dst_ptr, int src_width);\n\nvoid ScaleFilterCols_NEON(uint8* dst_ptr, const uint8* src_ptr,\n                          int dst_width, int x, int dx);\n\nvoid ScaleFilterCols_Any_NEON(uint8* dst_ptr, const uint8* src_ptr,\n                              int dst_width, int x, int dx);\n\nvoid ScaleRowDown2_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                         uint8* dst, int dst_width);\nvoid ScaleRowDown2Box_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst, int dst_width);\nvoid ScaleRowDown4_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                         uint8* dst, int dst_width);\nvoid ScaleRowDown4Box_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                            uint8* dst, int dst_width);\nvoid ScaleRowDown34_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                          uint8* dst, int dst_width);\nvoid ScaleRowDown34_0_Box_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* d, int dst_width);\nvoid ScaleRowDown34_1_Box_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* d, int dst_width);\nvoid ScaleRowDown38_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                          uint8* dst, int dst_width);\nvoid ScaleRowDown38_2_Box_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\nvoid ScaleRowDown38_3_Box_DSPR2(const uint8* src_ptr, ptrdiff_t src_stride,\n                                uint8* dst_ptr, int dst_width);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_SCALE_ROW_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/version.h",
    "content": "/*\n *  Copyright 2012 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_VERSION_H_\n#define INCLUDE_LIBYUV_VERSION_H_\n\n#define LIBYUV_VERSION 1622\n\n#endif  // INCLUDE_LIBYUV_VERSION_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv/video_common.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n// Common definitions for video, including fourcc and VideoFormat.\n\n#ifndef INCLUDE_LIBYUV_VIDEO_COMMON_H_\n#define INCLUDE_LIBYUV_VIDEO_COMMON_H_\n\n#include \"libyuv/basic_types.h\"\n\n#ifdef __cplusplus\nnamespace libyuv {\nextern \"C\" {\n#endif\n\n//////////////////////////////////////////////////////////////////////////////\n// Definition of FourCC codes\n//////////////////////////////////////////////////////////////////////////////\n\n// Convert four characters to a FourCC code.\n// Needs to be a macro otherwise the OS X compiler complains when the kFormat*\n// constants are used in a switch.\n#ifdef __cplusplus\n#define FOURCC(a, b, c, d) ( \\\n    (static_cast<uint32>(a)) | (static_cast<uint32>(b) << 8) | \\\n    (static_cast<uint32>(c) << 16) | (static_cast<uint32>(d) << 24))\n#else\n#define FOURCC(a, b, c, d) ( \\\n    ((uint32)(a)) | ((uint32)(b) << 8) | /* NOLINT */ \\\n    ((uint32)(c) << 16) | ((uint32)(d) << 24))  /* NOLINT */\n#endif\n\n// Some pages discussing FourCC codes:\n//   http://www.fourcc.org/yuv.php\n//   http://v4l2spec.bytesex.org/spec/book1.htm\n//   http://developer.apple.com/quicktime/icefloe/dispatch020.html\n//   http://msdn.microsoft.com/library/windows/desktop/dd206750.aspx#nv12\n//   http://people.xiph.org/~xiphmont/containers/nut/nut4cc.txt\n\n// FourCC codes grouped according to implementation efficiency.\n// Primary formats should convert in 1 efficient step.\n// Secondary formats are converted in 2 steps.\n// Auxilliary formats call primary converters.\nenum FourCC {\n  // 9 Primary YUV formats: 5 planar, 2 biplanar, 2 packed.\n  FOURCC_I420 = FOURCC('I', '4', '2', '0'),\n  FOURCC_I422 = FOURCC('I', '4', '2', '2'),\n  FOURCC_I444 = FOURCC('I', '4', '4', '4'),\n  FOURCC_I411 = FOURCC('I', '4', '1', '1'),\n  FOURCC_I400 = FOURCC('I', '4', '0', '0'),\n  FOURCC_NV21 = FOURCC('N', 'V', '2', '1'),\n  FOURCC_NV12 = FOURCC('N', 'V', '1', '2'),\n  FOURCC_YUY2 = FOURCC('Y', 'U', 'Y', '2'),\n  FOURCC_UYVY = FOURCC('U', 'Y', 'V', 'Y'),\n\n  // 2 Secondary YUV formats: row biplanar.\n  FOURCC_M420 = FOURCC('M', '4', '2', '0'),\n  FOURCC_Q420 = FOURCC('Q', '4', '2', '0'),  // deprecated.\n\n  // 9 Primary RGB formats: 4 32 bpp, 2 24 bpp, 3 16 bpp.\n  FOURCC_ARGB = FOURCC('A', 'R', 'G', 'B'),\n  FOURCC_BGRA = FOURCC('B', 'G', 'R', 'A'),\n  FOURCC_ABGR = FOURCC('A', 'B', 'G', 'R'),\n  FOURCC_24BG = FOURCC('2', '4', 'B', 'G'),\n  FOURCC_RAW  = FOURCC('r', 'a', 'w', ' '),\n  FOURCC_RGBA = FOURCC('R', 'G', 'B', 'A'),\n  FOURCC_RGBP = FOURCC('R', 'G', 'B', 'P'),  // rgb565 LE.\n  FOURCC_RGBO = FOURCC('R', 'G', 'B', 'O'),  // argb1555 LE.\n  FOURCC_R444 = FOURCC('R', '4', '4', '4'),  // argb4444 LE.\n\n  // 4 Secondary RGB formats: 4 Bayer Patterns. deprecated.\n  FOURCC_RGGB = FOURCC('R', 'G', 'G', 'B'),\n  FOURCC_BGGR = FOURCC('B', 'G', 'G', 'R'),\n  FOURCC_GRBG = FOURCC('G', 'R', 'B', 'G'),\n  FOURCC_GBRG = FOURCC('G', 'B', 'R', 'G'),\n\n  // 1 Primary Compressed YUV format.\n  FOURCC_MJPG = FOURCC('M', 'J', 'P', 'G'),\n\n  // 5 Auxiliary YUV variations: 3 with U and V planes are swapped, 1 Alias.\n  FOURCC_YV12 = FOURCC('Y', 'V', '1', '2'),\n  FOURCC_YV16 = FOURCC('Y', 'V', '1', '6'),\n  FOURCC_YV24 = FOURCC('Y', 'V', '2', '4'),\n  FOURCC_YU12 = FOURCC('Y', 'U', '1', '2'),  // Linux version of I420.\n  FOURCC_J420 = FOURCC('J', '4', '2', '0'),\n  FOURCC_J400 = FOURCC('J', '4', '0', '0'),  // unofficial fourcc\n  FOURCC_H420 = FOURCC('H', '4', '2', '0'),  // unofficial fourcc\n\n  // 14 Auxiliary aliases.  CanonicalFourCC() maps these to canonical fourcc.\n  FOURCC_IYUV = FOURCC('I', 'Y', 'U', 'V'),  // Alias for I420.\n  FOURCC_YU16 = FOURCC('Y', 'U', '1', '6'),  // Alias for I422.\n  FOURCC_YU24 = FOURCC('Y', 'U', '2', '4'),  // Alias for I444.\n  FOURCC_YUYV = FOURCC('Y', 'U', 'Y', 'V'),  // Alias for YUY2.\n  FOURCC_YUVS = FOURCC('y', 'u', 'v', 's'),  // Alias for YUY2 on Mac.\n  FOURCC_HDYC = FOURCC('H', 'D', 'Y', 'C'),  // Alias for UYVY.\n  FOURCC_2VUY = FOURCC('2', 'v', 'u', 'y'),  // Alias for UYVY on Mac.\n  FOURCC_JPEG = FOURCC('J', 'P', 'E', 'G'),  // Alias for MJPG.\n  FOURCC_DMB1 = FOURCC('d', 'm', 'b', '1'),  // Alias for MJPG on Mac.\n  FOURCC_BA81 = FOURCC('B', 'A', '8', '1'),  // Alias for BGGR.\n  FOURCC_RGB3 = FOURCC('R', 'G', 'B', '3'),  // Alias for RAW.\n  FOURCC_BGR3 = FOURCC('B', 'G', 'R', '3'),  // Alias for 24BG.\n  FOURCC_CM32 = FOURCC(0, 0, 0, 32),  // Alias for BGRA kCMPixelFormat_32ARGB\n  FOURCC_CM24 = FOURCC(0, 0, 0, 24),  // Alias for RAW kCMPixelFormat_24RGB\n  FOURCC_L555 = FOURCC('L', '5', '5', '5'),  // Alias for RGBO.\n  FOURCC_L565 = FOURCC('L', '5', '6', '5'),  // Alias for RGBP.\n  FOURCC_5551 = FOURCC('5', '5', '5', '1'),  // Alias for RGBO.\n\n  // 1 Auxiliary compressed YUV format set aside for capturer.\n  FOURCC_H264 = FOURCC('H', '2', '6', '4'),\n\n  // Match any fourcc.\n  FOURCC_ANY = -1,\n};\n\nenum FourCCBpp {\n  // Canonical fourcc codes used in our code.\n  FOURCC_BPP_I420 = 12,\n  FOURCC_BPP_I422 = 16,\n  FOURCC_BPP_I444 = 24,\n  FOURCC_BPP_I411 = 12,\n  FOURCC_BPP_I400 = 8,\n  FOURCC_BPP_NV21 = 12,\n  FOURCC_BPP_NV12 = 12,\n  FOURCC_BPP_YUY2 = 16,\n  FOURCC_BPP_UYVY = 16,\n  FOURCC_BPP_M420 = 12,\n  FOURCC_BPP_Q420 = 12,\n  FOURCC_BPP_ARGB = 32,\n  FOURCC_BPP_BGRA = 32,\n  FOURCC_BPP_ABGR = 32,\n  FOURCC_BPP_RGBA = 32,\n  FOURCC_BPP_24BG = 24,\n  FOURCC_BPP_RAW  = 24,\n  FOURCC_BPP_RGBP = 16,\n  FOURCC_BPP_RGBO = 16,\n  FOURCC_BPP_R444 = 16,\n  FOURCC_BPP_RGGB = 8,\n  FOURCC_BPP_BGGR = 8,\n  FOURCC_BPP_GRBG = 8,\n  FOURCC_BPP_GBRG = 8,\n  FOURCC_BPP_YV12 = 12,\n  FOURCC_BPP_YV16 = 16,\n  FOURCC_BPP_YV24 = 24,\n  FOURCC_BPP_YU12 = 12,\n  FOURCC_BPP_J420 = 12,\n  FOURCC_BPP_J400 = 8,\n  FOURCC_BPP_H420 = 12,\n  FOURCC_BPP_MJPG = 0,  // 0 means unknown.\n  FOURCC_BPP_H264 = 0,\n  FOURCC_BPP_IYUV = 12,\n  FOURCC_BPP_YU16 = 16,\n  FOURCC_BPP_YU24 = 24,\n  FOURCC_BPP_YUYV = 16,\n  FOURCC_BPP_YUVS = 16,\n  FOURCC_BPP_HDYC = 16,\n  FOURCC_BPP_2VUY = 16,\n  FOURCC_BPP_JPEG = 1,\n  FOURCC_BPP_DMB1 = 1,\n  FOURCC_BPP_BA81 = 8,\n  FOURCC_BPP_RGB3 = 24,\n  FOURCC_BPP_BGR3 = 24,\n  FOURCC_BPP_CM32 = 32,\n  FOURCC_BPP_CM24 = 24,\n\n  // Match any fourcc.\n  FOURCC_BPP_ANY  = 0,  // 0 means unknown.\n};\n\n// Converts fourcc aliases into canonical ones.\nLIBYUV_API uint32 CanonicalFourCC(uint32 fourcc);\n\n#ifdef __cplusplus\n}  // extern \"C\"\n}  // namespace libyuv\n#endif\n\n#endif  // INCLUDE_LIBYUV_VIDEO_COMMON_H_\n"
  },
  {
    "path": "phonelibs/libyuv/include/libyuv.h",
    "content": "/*\n *  Copyright 2011 The LibYuv Project Authors. All rights reserved.\n *\n *  Use of this source code is governed by a BSD-style license\n *  that can be found in the LICENSE file in the root of the source\n *  tree. An additional intellectual property rights grant can be found\n *  in the file PATENTS. All contributing project authors may\n *  be found in the AUTHORS file in the root of the source tree.\n */\n\n#ifndef INCLUDE_LIBYUV_H_\n#define INCLUDE_LIBYUV_H_\n\n#include \"libyuv/basic_types.h\"\n#include \"libyuv/compare.h\"\n#include \"libyuv/convert.h\"\n#include \"libyuv/convert_argb.h\"\n#include \"libyuv/convert_from.h\"\n#include \"libyuv/convert_from_argb.h\"\n#include \"libyuv/cpu_id.h\"\n#include \"libyuv/mjpeg_decoder.h\"\n#include \"libyuv/planar_functions.h\"\n#include \"libyuv/rotate.h\"\n#include \"libyuv/rotate_argb.h\"\n#include \"libyuv/row.h\"\n#include \"libyuv/scale.h\"\n#include \"libyuv/scale_argb.h\"\n#include \"libyuv/scale_row.h\"\n#include \"libyuv/version.h\"\n#include \"libyuv/video_common.h\"\n\n#endif  // INCLUDE_LIBYUV_H_\n"
  },
  {
    "path": "phonelibs/linux/include/linux/ion.h",
    "content": "/****************************************************************************\n ****************************************************************************\n ***\n ***   This header was automatically generated from a Linux kernel header\n ***   of the same name, to make information necessary for userspace to\n ***   call into the kernel available to libc.  It contains only constants,\n ***   structures, and macros generated from the original header, and thus,\n ***   contains no copyrightable information.\n ***\n ***   To edit the content of this header, modify the corresponding\n ***   source file (e.g. under external/kernel-headers/original/) then\n ***   run bionic/libc/kernel/tools/update_all.py\n ***\n ***   Any manual change here will be lost the next time this script will\n ***   be run. You've been warned!\n ***\n ****************************************************************************\n ****************************************************************************/\n#ifndef _UAPI_LINUX_ION_H\n#define _UAPI_LINUX_ION_H\n#include <linux/ioctl.h>\n#include <linux/types.h>\ntypedef int ion_user_handle_t;\nenum ion_heap_type {\n  ION_HEAP_TYPE_SYSTEM,\n  ION_HEAP_TYPE_SYSTEM_CONTIG,\n  ION_HEAP_TYPE_CARVEOUT,\n  ION_HEAP_TYPE_CHUNK,\n  ION_HEAP_TYPE_DMA,\n  ION_HEAP_TYPE_CUSTOM,\n};\n#define ION_NUM_HEAP_IDS (sizeof(unsigned int) * 8)\n#define ION_FLAG_CACHED 1\n#define ION_FLAG_CACHED_NEEDS_SYNC 2\nstruct ion_allocation_data {\n  size_t len;\n  size_t align;\n  unsigned int heap_id_mask;\n  unsigned int flags;\n  ion_user_handle_t handle;\n};\nstruct ion_fd_data {\n  ion_user_handle_t handle;\n  int fd;\n};\nstruct ion_handle_data {\n  ion_user_handle_t handle;\n};\nstruct ion_custom_data {\n  unsigned int cmd;\n  unsigned long arg;\n};\n#define MAX_HEAP_NAME 32\nstruct ion_heap_data {\n  char name[MAX_HEAP_NAME];\n  __u32 type;\n  __u32 heap_id;\n  __u32 reserved0;\n  __u32 reserved1;\n  __u32 reserved2;\n};\nstruct ion_heap_query {\n  __u32 cnt;\n  __u32 reserved0;\n  __u64 heaps;\n  __u32 reserved1;\n  __u32 reserved2;\n};\n#define ION_IOC_MAGIC 'I'\n#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, struct ion_allocation_data)\n#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data)\n#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data)\n#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data)\n#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)\n#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)\n#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)\n#define ION_IOC_HEAP_QUERY _IOWR(ION_IOC_MAGIC, 8, struct ion_heap_query)\n#endif\n"
  },
  {
    "path": "phonelibs/linux/include/msm_ion.h",
    "content": "#ifndef _UAPI_MSM_ION_H\n#define _UAPI_MSM_ION_H\n\n#include <linux/ion.h>\n\nenum msm_ion_heap_types {\n\tION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1,\n\tION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START,\n\tION_HEAP_TYPE_SYSTEM_SECURE,\n\tION_HEAP_TYPE_HYP_CMA,\n\t/*\n\t * if you add a heap type here you should also add it to\n\t * heap_types_info[] in msm_ion.c\n\t */\n};\n\n/**\n * These are the only ids that should be used for Ion heap ids.\n * The ids listed are the order in which allocation will be attempted\n * if specified. Don't swap the order of heap ids unless you know what\n * you are doing!\n * Id's are spaced by purpose to allow new Id's to be inserted in-between (for\n * possible fallbacks)\n */\n\nenum ion_heap_ids {\n\tINVALID_HEAP_ID = -1,\n\tION_CP_MM_HEAP_ID = 8,\n\tION_SECURE_HEAP_ID = 9,\n\tION_SECURE_DISPLAY_HEAP_ID = 10,\n\tION_CP_MFC_HEAP_ID = 12,\n\tION_CP_WB_HEAP_ID = 16, /* 8660 only */\n\tION_CAMERA_HEAP_ID = 20, /* 8660 only */\n\tION_SYSTEM_CONTIG_HEAP_ID = 21,\n\tION_ADSP_HEAP_ID = 22,\n\tION_PIL1_HEAP_ID = 23, /* Currently used for other PIL images */\n\tION_SF_HEAP_ID = 24,\n\tION_SYSTEM_HEAP_ID = 25,\n\tION_PIL2_HEAP_ID = 26, /* Currently used for modem firmware images */\n\tION_QSECOM_HEAP_ID = 27,\n\tION_AUDIO_HEAP_ID = 28,\n\n\tION_MM_FIRMWARE_HEAP_ID = 29,\n\n\tION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_FLAG_SECURE flag */\n};\n\n/*\n * The IOMMU heap is deprecated! Here are some aliases for backwards\n * compatibility:\n */\n#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID\n#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM\n\nenum ion_fixed_position {\n\tNOT_FIXED,\n\tFIXED_LOW,\n\tFIXED_MIDDLE,\n\tFIXED_HIGH,\n};\n\nenum cp_mem_usage {\n\tVIDEO_BITSTREAM = 0x1,\n\tVIDEO_PIXEL = 0x2,\n\tVIDEO_NONPIXEL = 0x3,\n\tDISPLAY_SECURE_CP_USAGE = 0x4,\n\tCAMERA_SECURE_CP_USAGE = 0x5,\n\tMAX_USAGE = 0x6,\n\tUNKNOWN = 0x7FFFFFFF,\n};\n\n/**\n * Flags to be used when allocating from the secure heap for\n * content protection\n */\n#define ION_FLAG_CP_TOUCH (1 << 17)\n#define ION_FLAG_CP_BITSTREAM (1 << 18)\n#define ION_FLAG_CP_PIXEL  (1 << 19)\n#define ION_FLAG_CP_NON_PIXEL (1 << 20)\n#define ION_FLAG_CP_CAMERA (1 << 21)\n#define ION_FLAG_CP_HLOS (1 << 22)\n#define ION_FLAG_CP_HLOS_FREE (1 << 23)\n#define ION_FLAG_CP_SEC_DISPLAY (1 << 25)\n#define ION_FLAG_CP_APP (1 << 26)\n\n/**\n * Flag to allow non continguous allocation of memory from secure\n * heap\n */\n#define ION_FLAG_ALLOW_NON_CONTIG (1 << 24)\n\n/**\n * Flag to use when allocating to indicate that a heap is secure.\n */\n#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED)\n\n/**\n * Flag for clients to force contiguous memort allocation\n *\n * Use of this flag is carefully monitored!\n */\n#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30)\n\n/*\n * Used in conjunction with heap which pool memory to force an allocation\n * to come from the page allocator directly instead of from the pool allocation\n */\n#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16)\n\n\n#define ION_FLAG_POOL_PREFETCH (1 << 27)\n\n/**\n* Deprecated! Please use the corresponding ION_FLAG_*\n*/\n#define ION_SECURE ION_FLAG_SECURE\n#define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS\n\n/**\n * Macro should be used with ion_heap_ids defined above.\n */\n#define ION_HEAP(bit) (1 << (bit))\n\n#define ION_ADSP_HEAP_NAME\t\"adsp\"\n#define ION_SYSTEM_HEAP_NAME\t\"system\"\n#define ION_VMALLOC_HEAP_NAME\tION_SYSTEM_HEAP_NAME\n#define ION_KMALLOC_HEAP_NAME\t\"kmalloc\"\n#define ION_AUDIO_HEAP_NAME\t\"audio\"\n#define ION_SF_HEAP_NAME\t\"sf\"\n#define ION_MM_HEAP_NAME\t\"mm\"\n#define ION_CAMERA_HEAP_NAME\t\"camera_preview\"\n#define ION_IOMMU_HEAP_NAME\t\"iommu\"\n#define ION_MFC_HEAP_NAME\t\"mfc\"\n#define ION_WB_HEAP_NAME\t\"wb\"\n#define ION_MM_FIRMWARE_HEAP_NAME\t\"mm_fw\"\n#define ION_PIL1_HEAP_NAME  \"pil_1\"\n#define ION_PIL2_HEAP_NAME  \"pil_2\"\n#define ION_QSECOM_HEAP_NAME\t\"qsecom\"\n#define ION_SECURE_HEAP_NAME\t\"secure_heap\"\n#define ION_SECURE_DISPLAY_HEAP_NAME \"secure_display\"\n\n#define ION_SET_CACHED(__cache)\t\t(__cache | ION_FLAG_CACHED)\n#define ION_SET_UNCACHED(__cache)\t(__cache & ~ION_FLAG_CACHED)\n\n#define ION_IS_CACHED(__flags)\t((__flags) & ION_FLAG_CACHED)\n\n/* struct ion_flush_data - data passed to ion for flushing caches\n *\n * @handle:\thandle with data to flush\n * @fd:\t\tfd to flush\n * @vaddr:\tuserspace virtual address mapped with mmap\n * @offset:\toffset into the handle to flush\n * @length:\tlength of handle to flush\n *\n * Performs cache operations on the handle. If p is the start address\n * of the handle, p + offset through p + offset + length will have\n * the cache operations performed\n */\nstruct ion_flush_data {\n\tion_user_handle_t handle;\n\tint fd;\n\tvoid *vaddr;\n\tunsigned int offset;\n\tunsigned int length;\n};\n\nstruct ion_prefetch_regions {\n\tunsigned int vmid;\n\tsize_t *sizes;\n\tunsigned int nr_sizes;\n};\n\nstruct ion_prefetch_data {\n\tint heap_id;\n\tunsigned long len;\n\t/* Is unsigned long bad? 32bit compiler vs 64 bit compiler*/\n\tstruct ion_prefetch_regions *regions;\n\tunsigned int nr_regions;\n};\n\n#define ION_IOC_MSM_MAGIC 'M'\n\n/**\n * DOC: ION_IOC_CLEAN_CACHES - clean the caches\n *\n * Clean the caches of the handle specified.\n */\n#define ION_IOC_CLEAN_CACHES\t_IOWR(ION_IOC_MSM_MAGIC, 0, \\\n\t\t\t\t\t\tstruct ion_flush_data)\n/**\n * DOC: ION_IOC_INV_CACHES - invalidate the caches\n *\n * Invalidate the caches of the handle specified.\n */\n#define ION_IOC_INV_CACHES\t_IOWR(ION_IOC_MSM_MAGIC, 1, \\\n\t\t\t\t\t\tstruct ion_flush_data)\n/**\n * DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches\n *\n * Clean and invalidate the caches of the handle specified.\n */\n#define ION_IOC_CLEAN_INV_CACHES\t_IOWR(ION_IOC_MSM_MAGIC, 2, \\\n\t\t\t\t\t\tstruct ion_flush_data)\n\n#define ION_IOC_PREFETCH\t\t_IOWR(ION_IOC_MSM_MAGIC, 3, \\\n\t\t\t\t\t\tstruct ion_prefetch_data)\n\n#define ION_IOC_DRAIN\t\t\t_IOWR(ION_IOC_MSM_MAGIC, 4, \\\n\t\t\t\t\t\tstruct ion_prefetch_data)\n\n#endif\n"
  },
  {
    "path": "phonelibs/mapbox-gl-native-qt/include/QMapbox",
    "content": "#include \"qmapbox.hpp\"\n"
  },
  {
    "path": "phonelibs/mapbox-gl-native-qt/include/QMapboxGL",
    "content": "#include \"qmapboxgl.hpp\"\n"
  },
  {
    "path": "phonelibs/mapbox-gl-native-qt/include/qmapbox.hpp",
    "content": "#ifndef QMAPBOX_H\n#define QMAPBOX_H\n\n#include <QColor>\n#include <QPair>\n#include <QString>\n#include <QVariant>\n#include <QVector>\n\n// This header follows the Qt coding style: https://wiki.qt.io/Qt_Coding_Style\n\n#if !defined(QT_MAPBOXGL_STATIC)\n#  if defined(QT_BUILD_MAPBOXGL_LIB)\n#    define Q_MAPBOXGL_EXPORT Q_DECL_EXPORT\n#  else\n#    define Q_MAPBOXGL_EXPORT Q_DECL_IMPORT\n#  endif\n#else\n#  define Q_MAPBOXGL_EXPORT\n#endif\n\nnamespace QMapbox {\n\ntypedef QPair<double, double> Coordinate;\ntypedef QPair<Coordinate, double> CoordinateZoom;\ntypedef QPair<double, double> ProjectedMeters;\n\ntypedef QVector<Coordinate> Coordinates;\ntypedef QVector<Coordinates> CoordinatesCollection;\n\ntypedef QVector<CoordinatesCollection> CoordinatesCollections;\n\nstruct Q_MAPBOXGL_EXPORT Feature {\n    enum Type {\n        PointType = 1,\n        LineStringType,\n        PolygonType\n    };\n\n    /*! Class constructor. */\n    Feature(Type type_ = PointType, const CoordinatesCollections& geometry_ = CoordinatesCollections(),\n            const QVariantMap& properties_ = QVariantMap(), const QVariant& id_ = QVariant())\n        : type(type_), geometry(geometry_), properties(properties_), id(id_) {}\n\n    Type type;\n    CoordinatesCollections geometry;\n    QVariantMap properties;\n    QVariant id;\n};\n\nstruct Q_MAPBOXGL_EXPORT ShapeAnnotationGeometry {\n    enum Type {\n        LineStringType = 1,\n        PolygonType,\n        MultiLineStringType,\n        MultiPolygonType\n    };\n\n    /*! Class constructor. */\n    ShapeAnnotationGeometry(Type type_ = LineStringType, const CoordinatesCollections& geometry_ = CoordinatesCollections())\n        : type(type_), geometry(geometry_) {}\n\n    Type type;\n    CoordinatesCollections geometry;\n};\n\nstruct Q_MAPBOXGL_EXPORT SymbolAnnotation {\n    Coordinate geometry;\n    QString icon;\n};\n\nstruct Q_MAPBOXGL_EXPORT LineAnnotation {\n    /*! Class constructor. */\n    LineAnnotation(const ShapeAnnotationGeometry& geometry_ = ShapeAnnotationGeometry(), float opacity_ = 1.0f,\n            float width_ = 1.0f, const QColor& color_ = Qt::black)\n        : geometry(geometry_), opacity(opacity_), width(width_), color(color_) {}\n\n    ShapeAnnotationGeometry geometry;\n    float opacity;\n    float width;\n    QColor color;\n};\n\nstruct Q_MAPBOXGL_EXPORT FillAnnotation {\n    /*! Class constructor. */\n    FillAnnotation(const ShapeAnnotationGeometry& geometry_ = ShapeAnnotationGeometry(), float opacity_ = 1.0f,\n            const QColor& color_ = Qt::black, const QVariant& outlineColor_ = QVariant())\n        : geometry(geometry_), opacity(opacity_), color(color_), outlineColor(outlineColor_) {}\n\n    ShapeAnnotationGeometry geometry;\n    float opacity;\n    QColor color;\n    QVariant outlineColor;\n};\n\ntypedef QVariant Annotation;\ntypedef quint32 AnnotationID;\ntypedef QVector<AnnotationID> AnnotationIDs;\n\nenum NetworkMode {\n    Online, // Default\n    Offline,\n};\n\nQ_MAPBOXGL_EXPORT QVector<QPair<QString, QString> >& defaultStyles();\n\nQ_MAPBOXGL_EXPORT NetworkMode networkMode();\nQ_MAPBOXGL_EXPORT void setNetworkMode(NetworkMode);\n\n// This struct is a 1:1 copy of mbgl::CustomLayerRenderParameters.\nstruct Q_MAPBOXGL_EXPORT CustomLayerRenderParameters {\n    double width;\n    double height;\n    double latitude;\n    double longitude;\n    double zoom;\n    double bearing;\n    double pitch;\n    double fieldOfView;\n};\n\nclass Q_MAPBOXGL_EXPORT CustomLayerHostInterface {\npublic:\n    virtual ~CustomLayerHostInterface() = default;\n    virtual void initialize() = 0;\n    virtual void render(const CustomLayerRenderParameters&) = 0;\n    virtual void deinitialize() = 0;\n};\n\nQ_MAPBOXGL_EXPORT double metersPerPixelAtLatitude(double latitude, double zoom);\nQ_MAPBOXGL_EXPORT ProjectedMeters projectedMetersForCoordinate(const Coordinate &);\nQ_MAPBOXGL_EXPORT Coordinate coordinateForProjectedMeters(const ProjectedMeters &);\n\n} // namespace QMapbox\n\nQ_DECLARE_METATYPE(QMapbox::Coordinate);\nQ_DECLARE_METATYPE(QMapbox::Coordinates);\nQ_DECLARE_METATYPE(QMapbox::CoordinatesCollection);\nQ_DECLARE_METATYPE(QMapbox::CoordinatesCollections);\nQ_DECLARE_METATYPE(QMapbox::Feature);\n\nQ_DECLARE_METATYPE(QMapbox::SymbolAnnotation);\nQ_DECLARE_METATYPE(QMapbox::ShapeAnnotationGeometry);\nQ_DECLARE_METATYPE(QMapbox::LineAnnotation);\nQ_DECLARE_METATYPE(QMapbox::FillAnnotation);\n\n#endif // QMAPBOX_H\n"
  },
  {
    "path": "phonelibs/mapbox-gl-native-qt/include/qmapboxgl.hpp",
    "content": "#ifndef QMAPBOXGL_H\n#define QMAPBOXGL_H\n\n#include <QImage>\n#include <QMapbox>\n#include <QMargins>\n#include <QObject>\n#include <QPointF>\n#include <QSize>\n#include <QString>\n#include <QStringList>\n\n#include <functional>\n\nclass QMapboxGLPrivate;\n\n// This header follows the Qt coding style: https://wiki.qt.io/Qt_Coding_Style\n\nclass Q_MAPBOXGL_EXPORT QMapboxGLSettings\n{\npublic:\n    QMapboxGLSettings();\n\n    enum GLContextMode {\n        UniqueGLContext = 0,\n        SharedGLContext\n    };\n\n    enum MapMode {\n        Continuous = 0,\n        Static\n    };\n\n    enum ConstrainMode {\n        NoConstrain = 0,\n        ConstrainHeightOnly,\n        ConstrainWidthAndHeight\n    };\n\n    enum ViewportMode {\n        DefaultViewport = 0,\n        FlippedYViewport\n    };\n\n    GLContextMode contextMode() const;\n    void setContextMode(GLContextMode);\n\n    MapMode mapMode() const;\n    void setMapMode(MapMode);\n\n    ConstrainMode constrainMode() const;\n    void setConstrainMode(ConstrainMode);\n\n    ViewportMode viewportMode() const;\n    void setViewportMode(ViewportMode);\n\n    unsigned cacheDatabaseMaximumSize() const;\n    void setCacheDatabaseMaximumSize(unsigned);\n\n    QString cacheDatabasePath() const;\n    void setCacheDatabasePath(const QString &);\n\n    QString assetPath() const;\n    void setAssetPath(const QString &);\n\n    QString accessToken() const;\n    void setAccessToken(const QString &);\n\n    QString apiBaseUrl() const;\n    void setApiBaseUrl(const QString &);\n\n    QString localFontFamily() const;\n    void setLocalFontFamily(const QString &);\n\n    std::function<std::string(const std::string &)> resourceTransform() const;\n    void setResourceTransform(const std::function<std::string(const std::string &)> &);\n\nprivate:\n    GLContextMode m_contextMode;\n    MapMode m_mapMode;\n    ConstrainMode m_constrainMode;\n    ViewportMode m_viewportMode;\n\n    unsigned m_cacheMaximumSize;\n    QString m_cacheDatabasePath;\n    QString m_assetPath;\n    QString m_accessToken;\n    QString m_apiBaseUrl;\n    QString m_localFontFamily;\n    std::function<std::string(const std::string &)> m_resourceTransform;\n};\n\nstruct Q_MAPBOXGL_EXPORT QMapboxGLCameraOptions {\n    QVariant center;  // Coordinate\n    QVariant anchor;  // QPointF\n    QVariant zoom;    // double\n    QVariant bearing; // double\n    QVariant pitch;   // double\n};\n\nclass Q_MAPBOXGL_EXPORT QMapboxGL : public QObject\n{\n    Q_OBJECT\n    Q_PROPERTY(double latitude READ latitude WRITE setLatitude)\n    Q_PROPERTY(double longitude READ longitude WRITE setLongitude)\n    Q_PROPERTY(double zoom READ zoom WRITE setZoom)\n    Q_PROPERTY(double bearing READ bearing WRITE setBearing)\n    Q_PROPERTY(double pitch READ pitch WRITE setPitch)\n    Q_PROPERTY(QString styleJson READ styleJson WRITE setStyleJson)\n    Q_PROPERTY(QString styleUrl READ styleUrl WRITE setStyleUrl)\n    Q_PROPERTY(double scale READ scale WRITE setScale)\n    Q_PROPERTY(QMapbox::Coordinate coordinate READ coordinate WRITE setCoordinate)\n    Q_PROPERTY(QMargins margins READ margins WRITE setMargins)\n\npublic:\n    enum MapChange {\n        MapChangeRegionWillChange = 0,\n        MapChangeRegionWillChangeAnimated,\n        MapChangeRegionIsChanging,\n        MapChangeRegionDidChange,\n        MapChangeRegionDidChangeAnimated,\n        MapChangeWillStartLoadingMap,\n        MapChangeDidFinishLoadingMap,\n        MapChangeDidFailLoadingMap,\n        MapChangeWillStartRenderingFrame,\n        MapChangeDidFinishRenderingFrame,\n        MapChangeDidFinishRenderingFrameFullyRendered,\n        MapChangeWillStartRenderingMap,\n        MapChangeDidFinishRenderingMap,\n        MapChangeDidFinishRenderingMapFullyRendered,\n        MapChangeDidFinishLoadingStyle,\n        MapChangeSourceDidChange\n    };\n\n    enum MapLoadingFailure {\n        StyleParseFailure,\n        StyleLoadFailure,\n        NotFoundFailure,\n        UnknownFailure\n    };\n\n    // Determines the orientation of the map.\n    enum NorthOrientation {\n        NorthUpwards, // Default\n        NorthRightwards,\n        NorthDownwards,\n        NorthLeftwards,\n    };\n\n    QMapboxGL(QObject* parent = 0,\n              const QMapboxGLSettings& = QMapboxGLSettings(),\n              const QSize& size = QSize(),\n              qreal pixelRatio = 1);\n    virtual ~QMapboxGL();\n\n    QString styleJson() const;\n    QString styleUrl() const;\n\n    void setStyleJson(const QString &);\n    void setStyleUrl(const QString &);\n\n    double latitude() const;\n    void setLatitude(double latitude);\n\n    double longitude() const;\n    void setLongitude(double longitude);\n\n    double scale() const;\n    void setScale(double scale, const QPointF &center = QPointF());\n\n    double zoom() const;\n    void setZoom(double zoom);\n\n    double minimumZoom() const;\n    double maximumZoom() const;\n\n    double bearing() const;\n    void setBearing(double degrees);\n    void setBearing(double degrees, const QPointF &center);\n\n    double pitch() const;\n    void setPitch(double pitch);\n    void pitchBy(double pitch);\n\n    NorthOrientation northOrientation() const;\n    void setNorthOrientation(NorthOrientation);\n\n    QMapbox::Coordinate coordinate() const;\n    void setCoordinate(const QMapbox::Coordinate &);\n    void setCoordinateZoom(const QMapbox::Coordinate &, double zoom);\n\n    void jumpTo(const QMapboxGLCameraOptions&);\n\n    void setGestureInProgress(bool inProgress);\n\n    void setTransitionOptions(qint64 duration, qint64 delay = 0);\n\n    void addAnnotationIcon(const QString &name, const QImage &sprite);\n\n    QMapbox::AnnotationID addAnnotation(const QMapbox::Annotation &);\n    void updateAnnotation(QMapbox::AnnotationID, const QMapbox::Annotation &);\n    void removeAnnotation(QMapbox::AnnotationID);\n\n    bool setLayoutProperty(const QString &layer, const QString &property, const QVariant &value);\n    bool setPaintProperty(const QString &layer, const QString &property, const QVariant &value);\n\n    bool isFullyLoaded() const;\n\n    void moveBy(const QPointF &offset);\n    void scaleBy(double scale, const QPointF &center = QPointF());\n    void rotateBy(const QPointF &first, const QPointF &second);\n\n    void resize(const QSize &size);\n\n    double metersPerPixelAtLatitude(double latitude, double zoom) const;\n    QMapbox::ProjectedMeters projectedMetersForCoordinate(const QMapbox::Coordinate &) const;\n    QMapbox::Coordinate coordinateForProjectedMeters(const QMapbox::ProjectedMeters &) const;\n    QPointF pixelForCoordinate(const QMapbox::Coordinate &) const;\n    QMapbox::Coordinate coordinateForPixel(const QPointF &) const;\n\n    QMapbox::CoordinateZoom coordinateZoomForBounds(const QMapbox::Coordinate &sw, QMapbox::Coordinate &ne) const;\n    QMapbox::CoordinateZoom coordinateZoomForBounds(const QMapbox::Coordinate &sw, QMapbox::Coordinate &ne, double bearing, double pitch);\n\n    void setMargins(const QMargins &margins);\n    QMargins margins() const;\n\n    void addSource(const QString &sourceID, const QVariantMap& params);\n    bool sourceExists(const QString &sourceID);\n    void updateSource(const QString &sourceID, const QVariantMap& params);\n    void removeSource(const QString &sourceID);\n\n    void addImage(const QString &name, const QImage &sprite);\n    void removeImage(const QString &name);\n\n    void addCustomLayer(const QString &id,\n        QScopedPointer<QMapbox::CustomLayerHostInterface>& host,\n        const QString& before = QString());\n    void addLayer(const QVariantMap &params, const QString& before = QString());\n    bool layerExists(const QString &id);\n    void removeLayer(const QString &id);\n\n    QVector<QString> layerIds() const;\n\n    void setFilter(const QString &layer, const QVariant &filter);\n    QVariant getFilter(const QString &layer) const;\n    // When rendering on a different thread,\n    // should be called on the render thread.\n    void createRenderer();\n    void destroyRenderer();\n    void setFramebufferObject(quint32 fbo, const QSize &size);\n\npublic slots:\n    void render();\n    void connectionEstablished();\n\n    // Commit changes, load all the resources\n    // and renders the map when completed.\n    void startStaticRender();\n\nsignals:\n    void needsRendering();\n    void mapChanged(QMapboxGL::MapChange);\n    void mapLoadingFailed(QMapboxGL::MapLoadingFailure, const QString &reason);\n    void copyrightsChanged(const QString &copyrightsHtml);\n\n    void staticRenderFinished(const QString &error);\n\nprivate:\n    Q_DISABLE_COPY(QMapboxGL)\n\n    QMapboxGLPrivate *d_ptr;\n};\n\nQ_DECLARE_METATYPE(QMapboxGL::MapChange);\nQ_DECLARE_METATYPE(QMapboxGL::MapLoadingFailure);\n\n#endif // QMAPBOXGL_H\n"
  },
  {
    "path": "phonelibs/nanovg/fontstash.h",
    "content": "//\n// Copyright (c) 2009-2013 Mikko Mononen memon@inside.org\n//\n// This software is provided 'as-is', without any express or implied\n// warranty.  In no event will the authors be held liable for any damages\n// arising from the use of this software.\n// Permission is granted to anyone to use this software for any purpose,\n// including commercial applications, and to alter it and redistribute it\n// freely, subject to the following restrictions:\n// 1. The origin of this software must not be misrepresented; you must not\n//    claim that you wrote the original software. If you use this software\n//    in a product, an acknowledgment in the product documentation would be\n//    appreciated but is not required.\n// 2. Altered source versions must be plainly marked as such, and must not be\n//    misrepresented as being the original software.\n// 3. This notice may not be removed or altered from any source distribution.\n//\n\n#ifndef FONS_H\n#define FONS_H\n\n#define FONS_INVALID -1\n\nenum FONSflags {\n\tFONS_ZERO_TOPLEFT = 1,\n\tFONS_ZERO_BOTTOMLEFT = 2,\n};\n\nenum FONSalign {\n\t// Horizontal align\n\tFONS_ALIGN_LEFT \t= 1<<0,\t// Default\n\tFONS_ALIGN_CENTER \t= 1<<1,\n\tFONS_ALIGN_RIGHT \t= 1<<2,\n\t// Vertical align\n\tFONS_ALIGN_TOP \t\t= 1<<3,\n\tFONS_ALIGN_MIDDLE\t= 1<<4,\n\tFONS_ALIGN_BOTTOM\t= 1<<5,\n\tFONS_ALIGN_BASELINE\t= 1<<6, // Default\n};\n\nenum FONSerrorCode {\n\t// Font atlas is full.\n\tFONS_ATLAS_FULL = 1,\n\t// Scratch memory used to render glyphs is full, requested size reported in 'val', you may need to bump up FONS_SCRATCH_BUF_SIZE.\n\tFONS_SCRATCH_FULL = 2,\n\t// Calls to fonsPushState has created too large stack, if you need deep state stack bump up FONS_MAX_STATES.\n\tFONS_STATES_OVERFLOW = 3,\n\t// Trying to pop too many states fonsPopState().\n\tFONS_STATES_UNDERFLOW = 4,\n};\n\nstruct FONSparams {\n\tint width, height;\n\tunsigned char flags;\n\tvoid* userPtr;\n\tint (*renderCreate)(void* uptr, int width, int height);\n\tint (*renderResize)(void* uptr, int width, int height);\n\tvoid (*renderUpdate)(void* uptr, int* rect, const unsigned char* data);\n\tvoid (*renderDraw)(void* uptr, const float* verts, const float* tcoords, const unsigned int* colors, int nverts);\n\tvoid (*renderDelete)(void* uptr);\n};\ntypedef struct FONSparams FONSparams;\n\nstruct FONSquad\n{\n\tfloat x0,y0,s0,t0;\n\tfloat x1,y1,s1,t1;\n};\ntypedef struct FONSquad FONSquad;\n\nstruct FONStextIter {\n\tfloat x, y, nextx, nexty, scale, spacing;\n\tunsigned int codepoint;\n\tshort isize, iblur;\n\tstruct FONSfont* font;\n\tint prevGlyphIndex;\n\tconst char* str;\n\tconst char* next;\n\tconst char* end;\n\tunsigned int utf8state;\n};\ntypedef struct FONStextIter FONStextIter;\n\ntypedef struct FONScontext FONScontext;\n\n// Constructor and destructor.\nFONScontext* fonsCreateInternal(FONSparams* params);\nvoid fonsDeleteInternal(FONScontext* s);\n\nvoid fonsSetErrorCallback(FONScontext* s, void (*callback)(void* uptr, int error, int val), void* uptr);\n// Returns current atlas size.\nvoid fonsGetAtlasSize(FONScontext* s, int* width, int* height);\n// Expands the atlas size.\nint fonsExpandAtlas(FONScontext* s, int width, int height);\n// Resets the whole stash.\nint fonsResetAtlas(FONScontext* stash, int width, int height);\n\n// Add fonts\nint fonsAddFont(FONScontext* s, const char* name, const char* path);\nint fonsAddFontMem(FONScontext* s, const char* name, unsigned char* data, int ndata, int freeData);\nint fonsGetFontByName(FONScontext* s, const char* name);\n\n// State handling\nvoid fonsPushState(FONScontext* s);\nvoid fonsPopState(FONScontext* s);\nvoid fonsClearState(FONScontext* s);\n\n// State setting\nvoid fonsSetSize(FONScontext* s, float size);\nvoid fonsSetColor(FONScontext* s, unsigned int color);\nvoid fonsSetSpacing(FONScontext* s, float spacing);\nvoid fonsSetBlur(FONScontext* s, float blur);\nvoid fonsSetAlign(FONScontext* s, int align);\nvoid fonsSetFont(FONScontext* s, int font);\n\n// Draw text\nfloat fonsDrawText(FONScontext* s, float x, float y, const char* string, const char* end);\n\n// Measure text\nfloat fonsTextBounds(FONScontext* s, float x, float y, const char* string, const char* end, float* bounds);\nvoid fonsLineBounds(FONScontext* s, float y, float* miny, float* maxy);\nvoid fonsVertMetrics(FONScontext* s, float* ascender, float* descender, float* lineh);\n\n// Text iterator\nint fonsTextIterInit(FONScontext* stash, FONStextIter* iter, float x, float y, const char* str, const char* end);\nint fonsTextIterNext(FONScontext* stash, FONStextIter* iter, struct FONSquad* quad);\n\n// Pull texture changes\nconst unsigned char* fonsGetTextureData(FONScontext* stash, int* width, int* height);\nint fonsValidateTexture(FONScontext* s, int* dirty);\n\n// Draws the stash texture for debugging\nvoid fonsDrawDebug(FONScontext* s, float x, float y);\n\n#endif // FONTSTASH_H\n\n\n#ifdef FONTSTASH_IMPLEMENTATION\n\n#define FONS_NOTUSED(v)  (void)sizeof(v)\n\n#ifdef FONS_USE_FREETYPE\n\n#include <ft2build.h>\n#include FT_FREETYPE_H\n#include FT_ADVANCES_H\n#include <math.h>\n\nstruct FONSttFontImpl {\n\tFT_Face font;\n};\ntypedef struct FONSttFontImpl FONSttFontImpl;\n\nstatic FT_Library ftLibrary;\n\nint fons__tt_init(FONScontext *context)\n{\n\tFT_Error ftError;\n        FONS_NOTUSED(context);\n\tftError = FT_Init_FreeType(&ftLibrary);\n\treturn ftError == 0;\n}\n\nint fons__tt_loadFont(FONScontext *context, FONSttFontImpl *font, unsigned char *data, int dataSize)\n{\n\tFT_Error ftError;\n\tFONS_NOTUSED(context);\n\n\t//font->font.userdata = stash;\n\tftError = FT_New_Memory_Face(ftLibrary, (const FT_Byte*)data, dataSize, 0, &font->font);\n\treturn ftError == 0;\n}\n\nvoid fons__tt_getFontVMetrics(FONSttFontImpl *font, int *ascent, int *descent, int *lineGap)\n{\n\t*ascent = font->font->ascender;\n\t*descent = font->font->descender;\n\t*lineGap = font->font->height - (*ascent - *descent);\n}\n\nfloat fons__tt_getPixelHeightScale(FONSttFontImpl *font, float size)\n{\n\treturn size / (font->font->ascender - font->font->descender);\n}\n\nint fons__tt_getGlyphIndex(FONSttFontImpl *font, int codepoint)\n{\n\treturn FT_Get_Char_Index(font->font, codepoint);\n}\n\nint fons__tt_buildGlyphBitmap(FONSttFontImpl *font, int glyph, float size, float scale,\n\t\t\t\t\t\t\t  int *advance, int *lsb, int *x0, int *y0, int *x1, int *y1)\n{\n\tFT_Error ftError;\n\tFT_GlyphSlot ftGlyph;\n\tFT_Fixed advFixed;\n\tFONS_NOTUSED(scale);\n\n\tftError = FT_Set_Pixel_Sizes(font->font, 0, (FT_UInt)(size * (float)font->font->units_per_EM / (float)(font->font->ascender - font->font->descender)));\n\tif (ftError) return 0;\n\tftError = FT_Load_Glyph(font->font, glyph, FT_LOAD_RENDER);\n\tif (ftError) return 0;\n\tftError = FT_Get_Advance(font->font, glyph, FT_LOAD_NO_SCALE, &advFixed);\n\tif (ftError) return 0;\n\tftGlyph = font->font->glyph;\n\t*advance = (int)advFixed;\n\t*lsb = (int)ftGlyph->metrics.horiBearingX;\n\t*x0 = ftGlyph->bitmap_left;\n\t*x1 = *x0 + ftGlyph->bitmap.width;\n\t*y0 = -ftGlyph->bitmap_top;\n\t*y1 = *y0 + ftGlyph->bitmap.rows;\n\treturn 1;\n}\n\nvoid fons__tt_renderGlyphBitmap(FONSttFontImpl *font, unsigned char *output, int outWidth, int outHeight, int outStride,\n\t\t\t\t\t\t\t\tfloat scaleX, float scaleY, int glyph)\n{\n\tFT_GlyphSlot ftGlyph = font->font->glyph;\n\tint ftGlyphOffset = 0;\n\tint x, y;\n\tFONS_NOTUSED(outWidth);\n\tFONS_NOTUSED(outHeight);\n\tFONS_NOTUSED(scaleX);\n\tFONS_NOTUSED(scaleY);\n\tFONS_NOTUSED(glyph);\t// glyph has already been loaded by fons__tt_buildGlyphBitmap\n\n\tfor ( y = 0; y < ftGlyph->bitmap.rows; y++ ) {\n\t\tfor ( x = 0; x < ftGlyph->bitmap.width; x++ ) {\n\t\t\toutput[(y * outStride) + x] = ftGlyph->bitmap.buffer[ftGlyphOffset++];\n\t\t}\n\t}\n}\n\nint fons__tt_getGlyphKernAdvance(FONSttFontImpl *font, int glyph1, int glyph2)\n{\n\tFT_Vector ftKerning;\n\tFT_Get_Kerning(font->font, glyph1, glyph2, FT_KERNING_DEFAULT, &ftKerning);\n\treturn (int)((ftKerning.x + 32) >> 6);  // Round up and convert to integer\n}\n\n#else\n\n#define STB_TRUETYPE_IMPLEMENTATION\nstatic void* fons__tmpalloc(size_t size, void* up);\nstatic void fons__tmpfree(void* ptr, void* up);\n#define STBTT_malloc(x,u)    fons__tmpalloc(x,u)\n#define STBTT_free(x,u)      fons__tmpfree(x,u)\n#include \"stb_truetype.h\"\n\nstruct FONSttFontImpl {\n\tstbtt_fontinfo font;\n};\ntypedef struct FONSttFontImpl FONSttFontImpl;\n\nint fons__tt_init(FONScontext *context)\n{\n\tFONS_NOTUSED(context);\n\treturn 1;\n}\n\nint fons__tt_loadFont(FONScontext *context, FONSttFontImpl *font, unsigned char *data, int dataSize)\n{\n\tint stbError;\n\tFONS_NOTUSED(dataSize);\n\n\tfont->font.userdata = context;\n\tstbError = stbtt_InitFont(&font->font, data, 0);\n\treturn stbError;\n}\n\nvoid fons__tt_getFontVMetrics(FONSttFontImpl *font, int *ascent, int *descent, int *lineGap)\n{\n\tstbtt_GetFontVMetrics(&font->font, ascent, descent, lineGap);\n}\n\nfloat fons__tt_getPixelHeightScale(FONSttFontImpl *font, float size)\n{\n\treturn stbtt_ScaleForPixelHeight(&font->font, size);\n}\n\nint fons__tt_getGlyphIndex(FONSttFontImpl *font, int codepoint)\n{\n\treturn stbtt_FindGlyphIndex(&font->font, codepoint);\n}\n\nint fons__tt_buildGlyphBitmap(FONSttFontImpl *font, int glyph, float size, float scale,\n\t\t\t\t\t\t\t  int *advance, int *lsb, int *x0, int *y0, int *x1, int *y1)\n{\n\tFONS_NOTUSED(size);\n\tstbtt_GetGlyphHMetrics(&font->font, glyph, advance, lsb);\n\tstbtt_GetGlyphBitmapBox(&font->font, glyph, scale, scale, x0, y0, x1, y1);\n\treturn 1;\n}\n\nvoid fons__tt_renderGlyphBitmap(FONSttFontImpl *font, unsigned char *output, int outWidth, int outHeight, int outStride,\n\t\t\t\t\t\t\t\tfloat scaleX, float scaleY, int glyph)\n{\n\tstbtt_MakeGlyphBitmap(&font->font, output, outWidth, outHeight, outStride, scaleX, scaleY, glyph);\n}\n\nint fons__tt_getGlyphKernAdvance(FONSttFontImpl *font, int glyph1, int glyph2)\n{\n\treturn stbtt_GetGlyphKernAdvance(&font->font, glyph1, glyph2);\n}\n\n#endif\n\n#ifndef FONS_SCRATCH_BUF_SIZE\n#\tdefine FONS_SCRATCH_BUF_SIZE 64000\n#endif\n#ifndef FONS_HASH_LUT_SIZE\n#\tdefine FONS_HASH_LUT_SIZE 256\n#endif\n#ifndef FONS_INIT_FONTS\n#\tdefine FONS_INIT_FONTS 4\n#endif\n#ifndef FONS_INIT_GLYPHS\n#\tdefine FONS_INIT_GLYPHS 256\n#endif\n#ifndef FONS_INIT_ATLAS_NODES\n#\tdefine FONS_INIT_ATLAS_NODES 256\n#endif\n#ifndef FONS_VERTEX_COUNT\n#\tdefine FONS_VERTEX_COUNT 1024\n#endif\n#ifndef FONS_MAX_STATES\n#\tdefine FONS_MAX_STATES 20\n#endif\n#ifndef FONS_MAX_FALLBACKS\n#\tdefine FONS_MAX_FALLBACKS 20\n#endif\n\nstatic unsigned int fons__hashint(unsigned int a)\n{\n\ta += ~(a<<15);\n\ta ^=  (a>>10);\n\ta +=  (a<<3);\n\ta ^=  (a>>6);\n\ta += ~(a<<11);\n\ta ^=  (a>>16);\n\treturn a;\n}\n\nstatic int fons__mini(int a, int b)\n{\n\treturn a < b ? a : b;\n}\n\nstatic int fons__maxi(int a, int b)\n{\n\treturn a > b ? a : b;\n}\n\nstruct FONSglyph\n{\n\tunsigned int codepoint;\n\tint index;\n\tint next;\n\tshort size, blur;\n\tshort x0,y0,x1,y1;\n\tshort xadv,xoff,yoff;\n};\ntypedef struct FONSglyph FONSglyph;\n\nstruct FONSfont\n{\n\tFONSttFontImpl font;\n\tchar name[64];\n\tunsigned char* data;\n\tint dataSize;\n\tunsigned char freeData;\n\tfloat ascender;\n\tfloat descender;\n\tfloat lineh;\n\tFONSglyph* glyphs;\n\tint cglyphs;\n\tint nglyphs;\n\tint lut[FONS_HASH_LUT_SIZE];\n\tint fallbacks[FONS_MAX_FALLBACKS];\n\tint nfallbacks;\n};\ntypedef struct FONSfont FONSfont;\n\nstruct FONSstate\n{\n\tint font;\n\tint align;\n\tfloat size;\n\tunsigned int color;\n\tfloat blur;\n\tfloat spacing;\n};\ntypedef struct FONSstate FONSstate;\n\nstruct FONSatlasNode {\n    short x, y, width;\n};\ntypedef struct FONSatlasNode FONSatlasNode;\n\nstruct FONSatlas\n{\n\tint width, height;\n\tFONSatlasNode* nodes;\n\tint nnodes;\n\tint cnodes;\n};\ntypedef struct FONSatlas FONSatlas;\n\nstruct FONScontext\n{\n\tFONSparams params;\n\tfloat itw,ith;\n\tunsigned char* texData;\n\tint dirtyRect[4];\n\tFONSfont** fonts;\n\tFONSatlas* atlas;\n\tint cfonts;\n\tint nfonts;\n\tfloat verts[FONS_VERTEX_COUNT*2];\n\tfloat tcoords[FONS_VERTEX_COUNT*2];\n\tunsigned int colors[FONS_VERTEX_COUNT];\n\tint nverts;\n\tunsigned char* scratch;\n\tint nscratch;\n\tFONSstate states[FONS_MAX_STATES];\n\tint nstates;\n\tvoid (*handleError)(void* uptr, int error, int val);\n\tvoid* errorUptr;\n};\n\n#ifdef STB_TRUETYPE_IMPLEMENTATION\n\nstatic void* fons__tmpalloc(size_t size, void* up)\n{\n\tunsigned char* ptr;\n\tFONScontext* stash = (FONScontext*)up;\n\n\t// 16-byte align the returned pointer\n\tsize = (size + 0xf) & ~0xf;\n\n\tif (stash->nscratch+(int)size > FONS_SCRATCH_BUF_SIZE) {\n\t\tif (stash->handleError)\n\t\t\tstash->handleError(stash->errorUptr, FONS_SCRATCH_FULL, stash->nscratch+(int)size);\n\t\treturn NULL;\n\t}\n\tptr = stash->scratch + stash->nscratch;\n\tstash->nscratch += (int)size;\n\treturn ptr;\n}\n\nstatic void fons__tmpfree(void* ptr, void* up)\n{\n\t(void)ptr;\n\t(void)up;\n\t// empty\n}\n\n#endif // STB_TRUETYPE_IMPLEMENTATION\n\n// Copyright (c) 2008-2010 Bjoern Hoehrmann <bjoern@hoehrmann.de>\n// See http://bjoern.hoehrmann.de/utf-8/decoder/dfa/ for details.\n\n#define FONS_UTF8_ACCEPT 0\n#define FONS_UTF8_REJECT 12\n\nstatic unsigned int fons__decutf8(unsigned int* state, unsigned int* codep, unsigned int byte)\n{\n\tstatic const unsigned char utf8d[] = {\n\t\t// The first part of the table maps bytes to character classes that\n\t\t// to reduce the size of the transition table and create bitmasks.\n\t\t0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,\n\t\t0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,\n\t\t0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,\n\t\t0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,\n\t\t1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,  9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,\n\t\t7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,\n\t\t8,8,2,2,2,2,2,2,2,2,2,2,2,2,2,2,  2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\n\t\t10,3,3,3,3,3,3,3,3,3,3,3,3,4,3,3, 11,6,6,6,5,8,8,8,8,8,8,8,8,8,8,8,\n\n\t\t// The second part is a transition table that maps a combination\n\t\t// of a state of the automaton and a character class to a state.\n\t\t0,12,24,36,60,96,84,12,12,12,48,72, 12,12,12,12,12,12,12,12,12,12,12,12,\n\t\t12, 0,12,12,12,12,12, 0,12, 0,12,12, 12,24,12,12,12,12,12,24,12,24,12,12,\n\t\t12,12,12,12,12,12,12,24,12,12,12,12, 12,24,12,12,12,12,12,12,12,24,12,12,\n\t\t12,12,12,12,12,12,12,36,12,36,12,12, 12,36,12,12,12,12,12,36,12,36,12,12,\n\t\t12,36,12,12,12,12,12,12,12,12,12,12,\n    };\n\n\tunsigned int type = utf8d[byte];\n\n    *codep = (*state != FONS_UTF8_ACCEPT) ?\n\t\t(byte & 0x3fu) | (*codep << 6) :\n\t\t(0xff >> type) & (byte);\n\n\t*state = utf8d[256 + *state + type];\n\treturn *state;\n}\n\n// Atlas based on Skyline Bin Packer by Jukka Jylänki\n\nstatic void fons__deleteAtlas(FONSatlas* atlas)\n{\n\tif (atlas == NULL) return;\n\tif (atlas->nodes != NULL) free(atlas->nodes);\n\tfree(atlas);\n}\n\nstatic FONSatlas* fons__allocAtlas(int w, int h, int nnodes)\n{\n\tFONSatlas* atlas = NULL;\n\n\t// Allocate memory for the font stash.\n\tatlas = (FONSatlas*)malloc(sizeof(FONSatlas));\n\tif (atlas == NULL) goto error;\n\tmemset(atlas, 0, sizeof(FONSatlas));\n\n\tatlas->width = w;\n\tatlas->height = h;\n\n\t// Allocate space for skyline nodes\n\tatlas->nodes = (FONSatlasNode*)malloc(sizeof(FONSatlasNode) * nnodes);\n\tif (atlas->nodes == NULL) goto error;\n\tmemset(atlas->nodes, 0, sizeof(FONSatlasNode) * nnodes);\n\tatlas->nnodes = 0;\n\tatlas->cnodes = nnodes;\n\n\t// Init root node.\n\tatlas->nodes[0].x = 0;\n\tatlas->nodes[0].y = 0;\n\tatlas->nodes[0].width = (short)w;\n\tatlas->nnodes++;\n\n\treturn atlas;\n\nerror:\n\tif (atlas) fons__deleteAtlas(atlas);\n\treturn NULL;\n}\n\nstatic int fons__atlasInsertNode(FONSatlas* atlas, int idx, int x, int y, int w)\n{\n\tint i;\n\t// Insert node\n\tif (atlas->nnodes+1 > atlas->cnodes) {\n\t\tatlas->cnodes = atlas->cnodes == 0 ? 8 : atlas->cnodes * 2;\n\t\tatlas->nodes = (FONSatlasNode*)realloc(atlas->nodes, sizeof(FONSatlasNode) * atlas->cnodes);\n\t\tif (atlas->nodes == NULL)\n\t\t\treturn 0;\n\t}\n\tfor (i = atlas->nnodes; i > idx; i--)\n\t\tatlas->nodes[i] = atlas->nodes[i-1];\n\tatlas->nodes[idx].x = (short)x;\n\tatlas->nodes[idx].y = (short)y;\n\tatlas->nodes[idx].width = (short)w;\n\tatlas->nnodes++;\n\n\treturn 1;\n}\n\nstatic void fons__atlasRemoveNode(FONSatlas* atlas, int idx)\n{\n\tint i;\n\tif (atlas->nnodes == 0) return;\n\tfor (i = idx; i < atlas->nnodes-1; i++)\n\t\tatlas->nodes[i] = atlas->nodes[i+1];\n\tatlas->nnodes--;\n}\n\nstatic void fons__atlasExpand(FONSatlas* atlas, int w, int h)\n{\n\t// Insert node for empty space\n\tif (w > atlas->width)\n\t\tfons__atlasInsertNode(atlas, atlas->nnodes, atlas->width, 0, w - atlas->width);\n\tatlas->width = w;\n\tatlas->height = h;\n}\n\nstatic void fons__atlasReset(FONSatlas* atlas, int w, int h)\n{\n\tatlas->width = w;\n\tatlas->height = h;\n\tatlas->nnodes = 0;\n\n\t// Init root node.\n\tatlas->nodes[0].x = 0;\n\tatlas->nodes[0].y = 0;\n\tatlas->nodes[0].width = (short)w;\n\tatlas->nnodes++;\n}\n\nstatic int fons__atlasAddSkylineLevel(FONSatlas* atlas, int idx, int x, int y, int w, int h)\n{\n\tint i;\n\n\t// Insert new node\n\tif (fons__atlasInsertNode(atlas, idx, x, y+h, w) == 0)\n\t\treturn 0;\n\n\t// Delete skyline segments that fall under the shadow of the new segment.\n\tfor (i = idx+1; i < atlas->nnodes; i++) {\n\t\tif (atlas->nodes[i].x < atlas->nodes[i-1].x + atlas->nodes[i-1].width) {\n\t\t\tint shrink = atlas->nodes[i-1].x + atlas->nodes[i-1].width - atlas->nodes[i].x;\n\t\t\tatlas->nodes[i].x += (short)shrink;\n\t\t\tatlas->nodes[i].width -= (short)shrink;\n\t\t\tif (atlas->nodes[i].width <= 0) {\n\t\t\t\tfons__atlasRemoveNode(atlas, i);\n\t\t\t\ti--;\n\t\t\t} else {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t// Merge same height skyline segments that are next to each other.\n\tfor (i = 0; i < atlas->nnodes-1; i++) {\n\t\tif (atlas->nodes[i].y == atlas->nodes[i+1].y) {\n\t\t\tatlas->nodes[i].width += atlas->nodes[i+1].width;\n\t\t\tfons__atlasRemoveNode(atlas, i+1);\n\t\t\ti--;\n\t\t}\n\t}\n\n\treturn 1;\n}\n\nstatic int fons__atlasRectFits(FONSatlas* atlas, int i, int w, int h)\n{\n\t// Checks if there is enough space at the location of skyline span 'i',\n\t// and return the max height of all skyline spans under that at that location,\n\t// (think tetris block being dropped at that position). Or -1 if no space found.\n\tint x = atlas->nodes[i].x;\n\tint y = atlas->nodes[i].y;\n\tint spaceLeft;\n\tif (x + w > atlas->width)\n\t\treturn -1;\n\tspaceLeft = w;\n\twhile (spaceLeft > 0) {\n\t\tif (i == atlas->nnodes) return -1;\n\t\ty = fons__maxi(y, atlas->nodes[i].y);\n\t\tif (y + h > atlas->height) return -1;\n\t\tspaceLeft -= atlas->nodes[i].width;\n\t\t++i;\n\t}\n\treturn y;\n}\n\nstatic int fons__atlasAddRect(FONSatlas* atlas, int rw, int rh, int* rx, int* ry)\n{\n\tint besth = atlas->height, bestw = atlas->width, besti = -1;\n\tint bestx = -1, besty = -1, i;\n\n\t// Bottom left fit heuristic.\n\tfor (i = 0; i < atlas->nnodes; i++) {\n\t\tint y = fons__atlasRectFits(atlas, i, rw, rh);\n\t\tif (y != -1) {\n\t\t\tif (y + rh < besth || (y + rh == besth && atlas->nodes[i].width < bestw)) {\n\t\t\t\tbesti = i;\n\t\t\t\tbestw = atlas->nodes[i].width;\n\t\t\t\tbesth = y + rh;\n\t\t\t\tbestx = atlas->nodes[i].x;\n\t\t\t\tbesty = y;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (besti == -1)\n\t\treturn 0;\n\n\t// Perform the actual packing.\n\tif (fons__atlasAddSkylineLevel(atlas, besti, bestx, besty, rw, rh) == 0)\n\t\treturn 0;\n\n\t*rx = bestx;\n\t*ry = besty;\n\n\treturn 1;\n}\n\nstatic void fons__addWhiteRect(FONScontext* stash, int w, int h)\n{\n\tint x, y, gx, gy;\n\tunsigned char* dst;\n\tif (fons__atlasAddRect(stash->atlas, w, h, &gx, &gy) == 0)\n\t\treturn;\n\n\t// Rasterize\n\tdst = &stash->texData[gx + gy * stash->params.width];\n\tfor (y = 0; y < h; y++) {\n\t\tfor (x = 0; x < w; x++)\n\t\t\tdst[x] = 0xff;\n\t\tdst += stash->params.width;\n\t}\n\n\tstash->dirtyRect[0] = fons__mini(stash->dirtyRect[0], gx);\n\tstash->dirtyRect[1] = fons__mini(stash->dirtyRect[1], gy);\n\tstash->dirtyRect[2] = fons__maxi(stash->dirtyRect[2], gx+w);\n\tstash->dirtyRect[3] = fons__maxi(stash->dirtyRect[3], gy+h);\n}\n\nFONScontext* fonsCreateInternal(FONSparams* params)\n{\n\tFONScontext* stash = NULL;\n\n\t// Allocate memory for the font stash.\n\tstash = (FONScontext*)malloc(sizeof(FONScontext));\n\tif (stash == NULL) goto error;\n\tmemset(stash, 0, sizeof(FONScontext));\n\n\tstash->params = *params;\n\n\t// Allocate scratch buffer.\n\tstash->scratch = (unsigned char*)malloc(FONS_SCRATCH_BUF_SIZE);\n\tif (stash->scratch == NULL) goto error;\n\n\t// Initialize implementation library\n\tif (!fons__tt_init(stash)) goto error;\n\n\tif (stash->params.renderCreate != NULL) {\n\t\tif (stash->params.renderCreate(stash->params.userPtr, stash->params.width, stash->params.height) == 0)\n\t\t\tgoto error;\n\t}\n\n\tstash->atlas = fons__allocAtlas(stash->params.width, stash->params.height, FONS_INIT_ATLAS_NODES);\n\tif (stash->atlas == NULL) goto error;\n\n\t// Allocate space for fonts.\n\tstash->fonts = (FONSfont**)malloc(sizeof(FONSfont*) * FONS_INIT_FONTS);\n\tif (stash->fonts == NULL) goto error;\n\tmemset(stash->fonts, 0, sizeof(FONSfont*) * FONS_INIT_FONTS);\n\tstash->cfonts = FONS_INIT_FONTS;\n\tstash->nfonts = 0;\n\n\t// Create texture for the cache.\n\tstash->itw = 1.0f/stash->params.width;\n\tstash->ith = 1.0f/stash->params.height;\n\tstash->texData = (unsigned char*)malloc(stash->params.width * stash->params.height);\n\tif (stash->texData == NULL) goto error;\n\tmemset(stash->texData, 0, stash->params.width * stash->params.height);\n\n\tstash->dirtyRect[0] = stash->params.width;\n\tstash->dirtyRect[1] = stash->params.height;\n\tstash->dirtyRect[2] = 0;\n\tstash->dirtyRect[3] = 0;\n\n\t// Add white rect at 0,0 for debug drawing.\n\tfons__addWhiteRect(stash, 2,2);\n\n\tfonsPushState(stash);\n\tfonsClearState(stash);\n\n\treturn stash;\n\nerror:\n\tfonsDeleteInternal(stash);\n\treturn NULL;\n}\n\nstatic FONSstate* fons__getState(FONScontext* stash)\n{\n\treturn &stash->states[stash->nstates-1];\n}\n\nint fonsAddFallbackFont(FONScontext* stash, int base, int fallback)\n{\n\tFONSfont* baseFont = stash->fonts[base];\n\tif (baseFont->nfallbacks < FONS_MAX_FALLBACKS) {\n\t\tbaseFont->fallbacks[baseFont->nfallbacks++] = fallback;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nvoid fonsSetSize(FONScontext* stash, float size)\n{\n\tfons__getState(stash)->size = size;\n}\n\nvoid fonsSetColor(FONScontext* stash, unsigned int color)\n{\n\tfons__getState(stash)->color = color;\n}\n\nvoid fonsSetSpacing(FONScontext* stash, float spacing)\n{\n\tfons__getState(stash)->spacing = spacing;\n}\n\nvoid fonsSetBlur(FONScontext* stash, float blur)\n{\n\tfons__getState(stash)->blur = blur;\n}\n\nvoid fonsSetAlign(FONScontext* stash, int align)\n{\n\tfons__getState(stash)->align = align;\n}\n\nvoid fonsSetFont(FONScontext* stash, int font)\n{\n\tfons__getState(stash)->font = font;\n}\n\nvoid fonsPushState(FONScontext* stash)\n{\n\tif (stash->nstates >= FONS_MAX_STATES) {\n\t\tif (stash->handleError)\n\t\t\tstash->handleError(stash->errorUptr, FONS_STATES_OVERFLOW, 0);\n\t\treturn;\n\t}\n\tif (stash->nstates > 0)\n\t\tmemcpy(&stash->states[stash->nstates], &stash->states[stash->nstates-1], sizeof(FONSstate));\n\tstash->nstates++;\n}\n\nvoid fonsPopState(FONScontext* stash)\n{\n\tif (stash->nstates <= 1) {\n\t\tif (stash->handleError)\n\t\t\tstash->handleError(stash->errorUptr, FONS_STATES_UNDERFLOW, 0);\n\t\treturn;\n\t}\n\tstash->nstates--;\n}\n\nvoid fonsClearState(FONScontext* stash)\n{\n\tFONSstate* state = fons__getState(stash);\n\tstate->size = 12.0f;\n\tstate->color = 0xffffffff;\n\tstate->font = 0;\n\tstate->blur = 0;\n\tstate->spacing = 0;\n\tstate->align = FONS_ALIGN_LEFT | FONS_ALIGN_BASELINE;\n}\n\nstatic void fons__freeFont(FONSfont* font)\n{\n\tif (font == NULL) return;\n\tif (font->glyphs) free(font->glyphs);\n\tif (font->freeData && font->data) free(font->data);\n\tfree(font);\n}\n\nstatic int fons__allocFont(FONScontext* stash)\n{\n\tFONSfont* font = NULL;\n\tif (stash->nfonts+1 > stash->cfonts) {\n\t\tstash->cfonts = stash->cfonts == 0 ? 8 : stash->cfonts * 2;\n\t\tstash->fonts = (FONSfont**)realloc(stash->fonts, sizeof(FONSfont*) * stash->cfonts);\n\t\tif (stash->fonts == NULL)\n\t\t\treturn -1;\n\t}\n\tfont = (FONSfont*)malloc(sizeof(FONSfont));\n\tif (font == NULL) goto error;\n\tmemset(font, 0, sizeof(FONSfont));\n\n\tfont->glyphs = (FONSglyph*)malloc(sizeof(FONSglyph) * FONS_INIT_GLYPHS);\n\tif (font->glyphs == NULL) goto error;\n\tfont->cglyphs = FONS_INIT_GLYPHS;\n\tfont->nglyphs = 0;\n\n\tstash->fonts[stash->nfonts++] = font;\n\treturn stash->nfonts-1;\n\nerror:\n\tfons__freeFont(font);\n\n\treturn FONS_INVALID;\n}\n\nint fonsAddFont(FONScontext* stash, const char* name, const char* path)\n{\n\tFILE* fp = 0;\n\tint dataSize = 0;\n\tunsigned char* data = NULL;\n\n\t// Read in the font data.\n\tfp = fopen(path, \"rb\");\n\tif (fp == NULL) goto error;\n\tfseek(fp,0,SEEK_END);\n\tdataSize = (int)ftell(fp);\n\tfseek(fp,0,SEEK_SET);\n\tdata = (unsigned char*)malloc(dataSize);\n\tif (data == NULL) goto error;\n\tfread(data, 1, dataSize, fp);\n\tfclose(fp);\n\tfp = 0;\n\n\treturn fonsAddFontMem(stash, name, data, dataSize, 1);\n\nerror:\n\tif (data) free(data);\n\tif (fp) fclose(fp);\n\treturn FONS_INVALID;\n}\n\nint fonsAddFontMem(FONScontext* stash, const char* name, unsigned char* data, int dataSize, int freeData)\n{\n\tint i, ascent, descent, fh, lineGap;\n\tFONSfont* font;\n\n\tint idx = fons__allocFont(stash);\n\tif (idx == FONS_INVALID)\n\t\treturn FONS_INVALID;\n\n\tfont = stash->fonts[idx];\n\n\tstrncpy(font->name, name, sizeof(font->name));\n\tfont->name[sizeof(font->name)-1] = '\\0';\n\n\t// Init hash lookup.\n\tfor (i = 0; i < FONS_HASH_LUT_SIZE; ++i)\n\t\tfont->lut[i] = -1;\n\n\t// Read in the font data.\n\tfont->dataSize = dataSize;\n\tfont->data = data;\n\tfont->freeData = (unsigned char)freeData;\n\n\t// Init font\n\tstash->nscratch = 0;\n\tif (!fons__tt_loadFont(stash, &font->font, data, dataSize)) goto error;\n\n\t// Store normalized line height. The real line height is got\n\t// by multiplying the lineh by font size.\n\tfons__tt_getFontVMetrics( &font->font, &ascent, &descent, &lineGap);\n\tfh = ascent - descent;\n\tfont->ascender = (float)ascent / (float)fh;\n\tfont->descender = (float)descent / (float)fh;\n\tfont->lineh = (float)(fh + lineGap) / (float)fh;\n\n\treturn idx;\n\nerror:\n\tfons__freeFont(font);\n\tstash->nfonts--;\n\treturn FONS_INVALID;\n}\n\nint fonsGetFontByName(FONScontext* s, const char* name)\n{\n\tint i;\n\tfor (i = 0; i < s->nfonts; i++) {\n\t\tif (strcmp(s->fonts[i]->name, name) == 0)\n\t\t\treturn i;\n\t}\n\treturn FONS_INVALID;\n}\n\n\nstatic FONSglyph* fons__allocGlyph(FONSfont* font)\n{\n\tif (font->nglyphs+1 > font->cglyphs) {\n\t\tfont->cglyphs = font->cglyphs == 0 ? 8 : font->cglyphs * 2;\n\t\tfont->glyphs = (FONSglyph*)realloc(font->glyphs, sizeof(FONSglyph) * font->cglyphs);\n\t\tif (font->glyphs == NULL) return NULL;\n\t}\n\tfont->nglyphs++;\n\treturn &font->glyphs[font->nglyphs-1];\n}\n\n\n// Based on Exponential blur, Jani Huhtanen, 2006\n\n#define APREC 16\n#define ZPREC 7\n\nstatic void fons__blurCols(unsigned char* dst, int w, int h, int dstStride, int alpha)\n{\n\tint x, y;\n\tfor (y = 0; y < h; y++) {\n\t\tint z = 0; // force zero border\n\t\tfor (x = 1; x < w; x++) {\n\t\t\tz += (alpha * (((int)(dst[x]) << ZPREC) - z)) >> APREC;\n\t\t\tdst[x] = (unsigned char)(z >> ZPREC);\n\t\t}\n\t\tdst[w-1] = 0; // force zero border\n\t\tz = 0;\n\t\tfor (x = w-2; x >= 0; x--) {\n\t\t\tz += (alpha * (((int)(dst[x]) << ZPREC) - z)) >> APREC;\n\t\t\tdst[x] = (unsigned char)(z >> ZPREC);\n\t\t}\n\t\tdst[0] = 0; // force zero border\n\t\tdst += dstStride;\n\t}\n}\n\nstatic void fons__blurRows(unsigned char* dst, int w, int h, int dstStride, int alpha)\n{\n\tint x, y;\n\tfor (x = 0; x < w; x++) {\n\t\tint z = 0; // force zero border\n\t\tfor (y = dstStride; y < h*dstStride; y += dstStride) {\n\t\t\tz += (alpha * (((int)(dst[y]) << ZPREC) - z)) >> APREC;\n\t\t\tdst[y] = (unsigned char)(z >> ZPREC);\n\t\t}\n\t\tdst[(h-1)*dstStride] = 0; // force zero border\n\t\tz = 0;\n\t\tfor (y = (h-2)*dstStride; y >= 0; y -= dstStride) {\n\t\t\tz += (alpha * (((int)(dst[y]) << ZPREC) - z)) >> APREC;\n\t\t\tdst[y] = (unsigned char)(z >> ZPREC);\n\t\t}\n\t\tdst[0] = 0; // force zero border\n\t\tdst++;\n\t}\n}\n\n\nstatic void fons__blur(FONScontext* stash, unsigned char* dst, int w, int h, int dstStride, int blur)\n{\n\tint alpha;\n\tfloat sigma;\n\t(void)stash;\n\n\tif (blur < 1)\n\t\treturn;\n\t// Calculate the alpha such that 90% of the kernel is within the radius. (Kernel extends to infinity)\n\tsigma = (float)blur * 0.57735f; // 1 / sqrt(3)\n\talpha = (int)((1<<APREC) * (1.0f - expf(-2.3f / (sigma+1.0f))));\n\tfons__blurRows(dst, w, h, dstStride, alpha);\n\tfons__blurCols(dst, w, h, dstStride, alpha);\n\tfons__blurRows(dst, w, h, dstStride, alpha);\n\tfons__blurCols(dst, w, h, dstStride, alpha);\n//\tfons__blurrows(dst, w, h, dstStride, alpha);\n//\tfons__blurcols(dst, w, h, dstStride, alpha);\n}\n\nstatic FONSglyph* fons__getGlyph(FONScontext* stash, FONSfont* font, unsigned int codepoint,\n\t\t\t\t\t\t\t\t short isize, short iblur)\n{\n\tint i, g, advance, lsb, x0, y0, x1, y1, gw, gh, gx, gy, x, y;\n\tfloat scale;\n\tFONSglyph* glyph = NULL;\n\tunsigned int h;\n\tfloat size = isize/10.0f;\n\tint pad, added;\n\tunsigned char* bdst;\n\tunsigned char* dst;\n\n\tif (isize < 2) return NULL;\n\tif (iblur > 20) iblur = 20;\n\tpad = iblur+2;\n\n\t// Reset allocator.\n\tstash->nscratch = 0;\n\n\t// Find code point and size.\n\th = fons__hashint(codepoint) & (FONS_HASH_LUT_SIZE-1);\n\ti = font->lut[h];\n\twhile (i != -1) {\n\t\tif (font->glyphs[i].codepoint == codepoint && font->glyphs[i].size == isize && font->glyphs[i].blur == iblur)\n\t\t\treturn &font->glyphs[i];\n\t\ti = font->glyphs[i].next;\n\t}\n\n\t// Could not find glyph, create it.\n\tscale = fons__tt_getPixelHeightScale(&font->font, size);\n\tg = fons__tt_getGlyphIndex(&font->font, codepoint);\n\t// Try to find the glyph in fallback fonts.\n\tif (g == 0) {\n\t\tfor (i = 0; i < font->nfallbacks; ++i) {\n\t\t\tFONSglyph* fallbackGlyph = fons__getGlyph(stash, stash->fonts[font->fallbacks[i]], codepoint, isize, iblur);\n\t\t\tif (fallbackGlyph != NULL && fallbackGlyph->index != 0) {\n\t\t\t\treturn fallbackGlyph;\n\t\t\t}\n\t\t}\n\t}\n\tfons__tt_buildGlyphBitmap(&font->font, g, size, scale, &advance, &lsb, &x0, &y0, &x1, &y1);\n\tgw = x1-x0 + pad*2;\n\tgh = y1-y0 + pad*2;\n\n\t// Find free spot for the rect in the atlas\n\tadded = fons__atlasAddRect(stash->atlas, gw, gh, &gx, &gy);\n\tif (added == 0 && stash->handleError != NULL) {\n\t\t// Atlas is full, let the user to resize the atlas (or not), and try again.\n\t\tstash->handleError(stash->errorUptr, FONS_ATLAS_FULL, 0);\n\t\tadded = fons__atlasAddRect(stash->atlas, gw, gh, &gx, &gy);\n\t}\n\tif (added == 0) return NULL;\n\n\t// Init glyph.\n\tglyph = fons__allocGlyph(font);\n\tglyph->codepoint = codepoint;\n\tglyph->size = isize;\n\tglyph->blur = iblur;\n\tglyph->index = g;\n\tglyph->x0 = (short)gx;\n\tglyph->y0 = (short)gy;\n\tglyph->x1 = (short)(glyph->x0+gw);\n\tglyph->y1 = (short)(glyph->y0+gh);\n\tglyph->xadv = (short)(scale * advance * 10.0f);\n\tglyph->xoff = (short)(x0 - pad);\n\tglyph->yoff = (short)(y0 - pad);\n\tglyph->next = 0;\n\n\t// Insert char to hash lookup.\n\tglyph->next = font->lut[h];\n\tfont->lut[h] = font->nglyphs-1;\n\n\t// Rasterize\n\tdst = &stash->texData[(glyph->x0+pad) + (glyph->y0+pad) * stash->params.width];\n\tfons__tt_renderGlyphBitmap(&font->font, dst, gw-pad*2,gh-pad*2, stash->params.width, scale,scale, g);\n\n\t// Make sure there is one pixel empty border.\n\tdst = &stash->texData[glyph->x0 + glyph->y0 * stash->params.width];\n\tfor (y = 0; y < gh; y++) {\n\t\tdst[y*stash->params.width] = 0;\n\t\tdst[gw-1 + y*stash->params.width] = 0;\n\t}\n\tfor (x = 0; x < gw; x++) {\n\t\tdst[x] = 0;\n\t\tdst[x + (gh-1)*stash->params.width] = 0;\n\t}\n\n\t// Debug code to color the glyph background\n/*\tunsigned char* fdst = &stash->texData[glyph->x0 + glyph->y0 * stash->params.width];\n\tfor (y = 0; y < gh; y++) {\n\t\tfor (x = 0; x < gw; x++) {\n\t\t\tint a = (int)fdst[x+y*stash->params.width] + 20;\n\t\t\tif (a > 255) a = 255;\n\t\t\tfdst[x+y*stash->params.width] = a;\n\t\t}\n\t}*/\n\n\t// Blur\n\tif (iblur > 0) {\n\t\tstash->nscratch = 0;\n\t\tbdst = &stash->texData[glyph->x0 + glyph->y0 * stash->params.width];\n\t\tfons__blur(stash, bdst, gw,gh, stash->params.width, iblur);\n\t}\n\n\tstash->dirtyRect[0] = fons__mini(stash->dirtyRect[0], glyph->x0);\n\tstash->dirtyRect[1] = fons__mini(stash->dirtyRect[1], glyph->y0);\n\tstash->dirtyRect[2] = fons__maxi(stash->dirtyRect[2], glyph->x1);\n\tstash->dirtyRect[3] = fons__maxi(stash->dirtyRect[3], glyph->y1);\n\n\treturn glyph;\n}\n\nstatic void fons__getQuad(FONScontext* stash, FONSfont* font,\n\t\t\t\t\t\t   int prevGlyphIndex, FONSglyph* glyph,\n\t\t\t\t\t\t   float scale, float spacing, float* x, float* y, FONSquad* q)\n{\n\tfloat rx,ry,xoff,yoff,x0,y0,x1,y1;\n\n\tif (prevGlyphIndex != -1) {\n\t\tfloat adv = fons__tt_getGlyphKernAdvance(&font->font, prevGlyphIndex, glyph->index) * scale;\n\t\t*x += (int)(adv + spacing + 0.5f);\n\t}\n\n\t// Each glyph has 2px border to allow good interpolation,\n\t// one pixel to prevent leaking, and one to allow good interpolation for rendering.\n\t// Inset the texture region by one pixel for correct interpolation.\n\txoff = (short)(glyph->xoff+1);\n\tyoff = (short)(glyph->yoff+1);\n\tx0 = (float)(glyph->x0+1);\n\ty0 = (float)(glyph->y0+1);\n\tx1 = (float)(glyph->x1-1);\n\ty1 = (float)(glyph->y1-1);\n\n\tif (stash->params.flags & FONS_ZERO_TOPLEFT) {\n\t\trx = (float)(int)(*x + xoff);\n\t\try = (float)(int)(*y + yoff);\n\n\t\tq->x0 = rx;\n\t\tq->y0 = ry;\n\t\tq->x1 = rx + x1 - x0;\n\t\tq->y1 = ry + y1 - y0;\n\n\t\tq->s0 = x0 * stash->itw;\n\t\tq->t0 = y0 * stash->ith;\n\t\tq->s1 = x1 * stash->itw;\n\t\tq->t1 = y1 * stash->ith;\n\t} else {\n\t\trx = (float)(int)(*x + xoff);\n\t\try = (float)(int)(*y - yoff);\n\n\t\tq->x0 = rx;\n\t\tq->y0 = ry;\n\t\tq->x1 = rx + x1 - x0;\n\t\tq->y1 = ry - y1 + y0;\n\n\t\tq->s0 = x0 * stash->itw;\n\t\tq->t0 = y0 * stash->ith;\n\t\tq->s1 = x1 * stash->itw;\n\t\tq->t1 = y1 * stash->ith;\n\t}\n\n\t*x += (int)(glyph->xadv / 10.0f + 0.5f);\n}\n\nstatic void fons__flush(FONScontext* stash)\n{\n\t// Flush texture\n\tif (stash->dirtyRect[0] < stash->dirtyRect[2] && stash->dirtyRect[1] < stash->dirtyRect[3]) {\n\t\tif (stash->params.renderUpdate != NULL)\n\t\t\tstash->params.renderUpdate(stash->params.userPtr, stash->dirtyRect, stash->texData);\n\t\t// Reset dirty rect\n\t\tstash->dirtyRect[0] = stash->params.width;\n\t\tstash->dirtyRect[1] = stash->params.height;\n\t\tstash->dirtyRect[2] = 0;\n\t\tstash->dirtyRect[3] = 0;\n\t}\n\n\t// Flush triangles\n\tif (stash->nverts > 0) {\n\t\tif (stash->params.renderDraw != NULL)\n\t\t\tstash->params.renderDraw(stash->params.userPtr, stash->verts, stash->tcoords, stash->colors, stash->nverts);\n\t\tstash->nverts = 0;\n\t}\n}\n\nstatic __inline void fons__vertex(FONScontext* stash, float x, float y, float s, float t, unsigned int c)\n{\n\tstash->verts[stash->nverts*2+0] = x;\n\tstash->verts[stash->nverts*2+1] = y;\n\tstash->tcoords[stash->nverts*2+0] = s;\n\tstash->tcoords[stash->nverts*2+1] = t;\n\tstash->colors[stash->nverts] = c;\n\tstash->nverts++;\n}\n\nstatic float fons__getVertAlign(FONScontext* stash, FONSfont* font, int align, short isize)\n{\n\tif (stash->params.flags & FONS_ZERO_TOPLEFT) {\n\t\tif (align & FONS_ALIGN_TOP) {\n\t\t\treturn font->ascender * (float)isize/10.0f;\n\t\t} else if (align & FONS_ALIGN_MIDDLE) {\n\t\t\treturn (font->ascender + font->descender) / 2.0f * (float)isize/10.0f;\n\t\t} else if (align & FONS_ALIGN_BASELINE) {\n\t\t\treturn 0.0f;\n\t\t} else if (align & FONS_ALIGN_BOTTOM) {\n\t\t\treturn font->descender * (float)isize/10.0f;\n\t\t}\n\t} else {\n\t\tif (align & FONS_ALIGN_TOP) {\n\t\t\treturn -font->ascender * (float)isize/10.0f;\n\t\t} else if (align & FONS_ALIGN_MIDDLE) {\n\t\t\treturn -(font->ascender + font->descender) / 2.0f * (float)isize/10.0f;\n\t\t} else if (align & FONS_ALIGN_BASELINE) {\n\t\t\treturn 0.0f;\n\t\t} else if (align & FONS_ALIGN_BOTTOM) {\n\t\t\treturn -font->descender * (float)isize/10.0f;\n\t\t}\n\t}\n\treturn 0.0;\n}\n\nfloat fonsDrawText(FONScontext* stash,\n\t\t\t\t   float x, float y,\n\t\t\t\t   const char* str, const char* end)\n{\n\tFONSstate* state = fons__getState(stash);\n\tunsigned int codepoint;\n\tunsigned int utf8state = 0;\n\tFONSglyph* glyph = NULL;\n\tFONSquad q;\n\tint prevGlyphIndex = -1;\n\tshort isize = (short)(state->size*10.0f);\n\tshort iblur = (short)state->blur;\n\tfloat scale;\n\tFONSfont* font;\n\tfloat width;\n\n\tif (stash == NULL) return x;\n\tif (state->font < 0 || state->font >= stash->nfonts) return x;\n\tfont = stash->fonts[state->font];\n\tif (font->data == NULL) return x;\n\n\tscale = fons__tt_getPixelHeightScale(&font->font, (float)isize/10.0f);\n\n\tif (end == NULL)\n\t\tend = str + strlen(str);\n\n\t// Align horizontally\n\tif (state->align & FONS_ALIGN_LEFT) {\n\t\t// empty\n\t} else if (state->align & FONS_ALIGN_RIGHT) {\n\t\twidth = fonsTextBounds(stash, x,y, str, end, NULL);\n\t\tx -= width;\n\t} else if (state->align & FONS_ALIGN_CENTER) {\n\t\twidth = fonsTextBounds(stash, x,y, str, end, NULL);\n\t\tx -= width * 0.5f;\n\t}\n\t// Align vertically.\n\ty += fons__getVertAlign(stash, font, state->align, isize);\n\n\tfor (; str != end; ++str) {\n\t\tif (fons__decutf8(&utf8state, &codepoint, *(const unsigned char*)str))\n\t\t\tcontinue;\n\t\tglyph = fons__getGlyph(stash, font, codepoint, isize, iblur);\n\t\tif (glyph != NULL) {\n\t\t\tfons__getQuad(stash, font, prevGlyphIndex, glyph, scale, state->spacing, &x, &y, &q);\n\n\t\t\tif (stash->nverts+6 > FONS_VERTEX_COUNT)\n\t\t\t\tfons__flush(stash);\n\n\t\t\tfons__vertex(stash, q.x0, q.y0, q.s0, q.t0, state->color);\n\t\t\tfons__vertex(stash, q.x1, q.y1, q.s1, q.t1, state->color);\n\t\t\tfons__vertex(stash, q.x1, q.y0, q.s1, q.t0, state->color);\n\n\t\t\tfons__vertex(stash, q.x0, q.y0, q.s0, q.t0, state->color);\n\t\t\tfons__vertex(stash, q.x0, q.y1, q.s0, q.t1, state->color);\n\t\t\tfons__vertex(stash, q.x1, q.y1, q.s1, q.t1, state->color);\n\t\t}\n\t\tprevGlyphIndex = glyph != NULL ? glyph->index : -1;\n\t}\n\tfons__flush(stash);\n\n\treturn x;\n}\n\nint fonsTextIterInit(FONScontext* stash, FONStextIter* iter,\n\t\t\t\t\t float x, float y, const char* str, const char* end)\n{\n\tFONSstate* state = fons__getState(stash);\n\tfloat width;\n\n\tmemset(iter, 0, sizeof(*iter));\n\n\tif (stash == NULL) return 0;\n\tif (state->font < 0 || state->font >= stash->nfonts) return 0;\n\titer->font = stash->fonts[state->font];\n\tif (iter->font->data == NULL) return 0;\n\n\titer->isize = (short)(state->size*10.0f);\n\titer->iblur = (short)state->blur;\n\titer->scale = fons__tt_getPixelHeightScale(&iter->font->font, (float)iter->isize/10.0f);\n\n\t// Align horizontally\n\tif (state->align & FONS_ALIGN_LEFT) {\n\t\t// empty\n\t} else if (state->align & FONS_ALIGN_RIGHT) {\n\t\twidth = fonsTextBounds(stash, x,y, str, end, NULL);\n\t\tx -= width;\n\t} else if (state->align & FONS_ALIGN_CENTER) {\n\t\twidth = fonsTextBounds(stash, x,y, str, end, NULL);\n\t\tx -= width * 0.5f;\n\t}\n\t// Align vertically.\n\ty += fons__getVertAlign(stash, iter->font, state->align, iter->isize);\n\n\tif (end == NULL)\n\t\tend = str + strlen(str);\n\n\titer->x = iter->nextx = x;\n\titer->y = iter->nexty = y;\n\titer->spacing = state->spacing;\n\titer->str = str;\n\titer->next = str;\n\titer->end = end;\n\titer->codepoint = 0;\n\titer->prevGlyphIndex = -1;\n\n\treturn 1;\n}\n\nint fonsTextIterNext(FONScontext* stash, FONStextIter* iter, FONSquad* quad)\n{\n\tFONSglyph* glyph = NULL;\n\tconst char* str = iter->next;\n\titer->str = iter->next;\n\n\tif (str == iter->end)\n\t\treturn 0;\n\n\tfor (; str != iter->end; str++) {\n\t\tif (fons__decutf8(&iter->utf8state, &iter->codepoint, *(const unsigned char*)str))\n\t\t\tcontinue;\n\t\tstr++;\n\t\t// Get glyph and quad\n\t\titer->x = iter->nextx;\n\t\titer->y = iter->nexty;\n\t\tglyph = fons__getGlyph(stash, iter->font, iter->codepoint, iter->isize, iter->iblur);\n\t\tif (glyph != NULL)\n\t\t\tfons__getQuad(stash, iter->font, iter->prevGlyphIndex, glyph, iter->scale, iter->spacing, &iter->nextx, &iter->nexty, quad);\n\t\titer->prevGlyphIndex = glyph != NULL ? glyph->index : -1;\n\t\tbreak;\n\t}\n\titer->next = str;\n\n\treturn 1;\n}\n\nvoid fonsDrawDebug(FONScontext* stash, float x, float y)\n{\n\tint i;\n\tint w = stash->params.width;\n\tint h = stash->params.height;\n\tfloat u = w == 0 ? 0 : (1.0f / w);\n\tfloat v = h == 0 ? 0 : (1.0f / h);\n\n\tif (stash->nverts+6+6 > FONS_VERTEX_COUNT)\n\t\tfons__flush(stash);\n\n\t// Draw background\n\tfons__vertex(stash, x+0, y+0, u, v, 0x0fffffff);\n\tfons__vertex(stash, x+w, y+h, u, v, 0x0fffffff);\n\tfons__vertex(stash, x+w, y+0, u, v, 0x0fffffff);\n\n\tfons__vertex(stash, x+0, y+0, u, v, 0x0fffffff);\n\tfons__vertex(stash, x+0, y+h, u, v, 0x0fffffff);\n\tfons__vertex(stash, x+w, y+h, u, v, 0x0fffffff);\n\n\t// Draw texture\n\tfons__vertex(stash, x+0, y+0, 0, 0, 0xffffffff);\n\tfons__vertex(stash, x+w, y+h, 1, 1, 0xffffffff);\n\tfons__vertex(stash, x+w, y+0, 1, 0, 0xffffffff);\n\n\tfons__vertex(stash, x+0, y+0, 0, 0, 0xffffffff);\n\tfons__vertex(stash, x+0, y+h, 0, 1, 0xffffffff);\n\tfons__vertex(stash, x+w, y+h, 1, 1, 0xffffffff);\n\n\t// Drawbug draw atlas\n\tfor (i = 0; i < stash->atlas->nnodes; i++) {\n\t\tFONSatlasNode* n = &stash->atlas->nodes[i];\n\n\t\tif (stash->nverts+6 > FONS_VERTEX_COUNT)\n\t\t\tfons__flush(stash);\n\n\t\tfons__vertex(stash, x+n->x+0, y+n->y+0, u, v, 0xc00000ff);\n\t\tfons__vertex(stash, x+n->x+n->width, y+n->y+1, u, v, 0xc00000ff);\n\t\tfons__vertex(stash, x+n->x+n->width, y+n->y+0, u, v, 0xc00000ff);\n\n\t\tfons__vertex(stash, x+n->x+0, y+n->y+0, u, v, 0xc00000ff);\n\t\tfons__vertex(stash, x+n->x+0, y+n->y+1, u, v, 0xc00000ff);\n\t\tfons__vertex(stash, x+n->x+n->width, y+n->y+1, u, v, 0xc00000ff);\n\t}\n\n\tfons__flush(stash);\n}\n\nfloat fonsTextBounds(FONScontext* stash,\n\t\t\t\t\t float x, float y,\n\t\t\t\t\t const char* str, const char* end,\n\t\t\t\t\t float* bounds)\n{\n\tFONSstate* state = fons__getState(stash);\n\tunsigned int codepoint;\n\tunsigned int utf8state = 0;\n\tFONSquad q;\n\tFONSglyph* glyph = NULL;\n\tint prevGlyphIndex = -1;\n\tshort isize = (short)(state->size*10.0f);\n\tshort iblur = (short)state->blur;\n\tfloat scale;\n\tFONSfont* font;\n\tfloat startx, advance;\n\tfloat minx, miny, maxx, maxy;\n\n\tif (stash == NULL) return 0;\n\tif (state->font < 0 || state->font >= stash->nfonts) return 0;\n\tfont = stash->fonts[state->font];\n\tif (font->data == NULL) return 0;\n\n\tscale = fons__tt_getPixelHeightScale(&font->font, (float)isize/10.0f);\n\n\t// Align vertically.\n\ty += fons__getVertAlign(stash, font, state->align, isize);\n\n\tminx = maxx = x;\n\tminy = maxy = y;\n\tstartx = x;\n\n\tif (end == NULL)\n\t\tend = str + strlen(str);\n\n\tfor (; str != end; ++str) {\n\t\tif (fons__decutf8(&utf8state, &codepoint, *(const unsigned char*)str))\n\t\t\tcontinue;\n\t\tglyph = fons__getGlyph(stash, font, codepoint, isize, iblur);\n\t\tif (glyph != NULL) {\n\t\t\tfons__getQuad(stash, font, prevGlyphIndex, glyph, scale, state->spacing, &x, &y, &q);\n\t\t\tif (q.x0 < minx) minx = q.x0;\n\t\t\tif (q.x1 > maxx) maxx = q.x1;\n\t\t\tif (stash->params.flags & FONS_ZERO_TOPLEFT) {\n\t\t\t\tif (q.y0 < miny) miny = q.y0;\n\t\t\t\tif (q.y1 > maxy) maxy = q.y1;\n\t\t\t} else {\n\t\t\t\tif (q.y1 < miny) miny = q.y1;\n\t\t\t\tif (q.y0 > maxy) maxy = q.y0;\n\t\t\t}\n\t\t}\n\t\tprevGlyphIndex = glyph != NULL ? glyph->index : -1;\n\t}\n\n\tadvance = x - startx;\n\n\t// Align horizontally\n\tif (state->align & FONS_ALIGN_LEFT) {\n\t\t// empty\n\t} else if (state->align & FONS_ALIGN_RIGHT) {\n\t\tminx -= advance;\n\t\tmaxx -= advance;\n\t} else if (state->align & FONS_ALIGN_CENTER) {\n\t\tminx -= advance * 0.5f;\n\t\tmaxx -= advance * 0.5f;\n\t}\n\n\tif (bounds) {\n\t\tbounds[0] = minx;\n\t\tbounds[1] = miny;\n\t\tbounds[2] = maxx;\n\t\tbounds[3] = maxy;\n\t}\n\n\treturn advance;\n}\n\nvoid fonsVertMetrics(FONScontext* stash,\n\t\t\t\t\t float* ascender, float* descender, float* lineh)\n{\n\tFONSfont* font;\n\tFONSstate* state = fons__getState(stash);\n\tshort isize;\n\n\tif (stash == NULL) return;\n\tif (state->font < 0 || state->font >= stash->nfonts) return;\n\tfont = stash->fonts[state->font];\n\tisize = (short)(state->size*10.0f);\n\tif (font->data == NULL) return;\n\n\tif (ascender)\n\t\t*ascender = font->ascender*isize/10.0f;\n\tif (descender)\n\t\t*descender = font->descender*isize/10.0f;\n\tif (lineh)\n\t\t*lineh = font->lineh*isize/10.0f;\n}\n\nvoid fonsLineBounds(FONScontext* stash, float y, float* miny, float* maxy)\n{\n\tFONSfont* font;\n\tFONSstate* state = fons__getState(stash);\n\tshort isize;\n\n\tif (stash == NULL) return;\n\tif (state->font < 0 || state->font >= stash->nfonts) return;\n\tfont = stash->fonts[state->font];\n\tisize = (short)(state->size*10.0f);\n\tif (font->data == NULL) return;\n\n\ty += fons__getVertAlign(stash, font, state->align, isize);\n\n\tif (stash->params.flags & FONS_ZERO_TOPLEFT) {\n\t\t*miny = y - font->ascender * (float)isize/10.0f;\n\t\t*maxy = *miny + font->lineh*isize/10.0f;\n\t} else {\n\t\t*maxy = y + font->descender * (float)isize/10.0f;\n\t\t*miny = *maxy - font->lineh*isize/10.0f;\n\t}\n}\n\nconst unsigned char* fonsGetTextureData(FONScontext* stash, int* width, int* height)\n{\n\tif (width != NULL)\n\t\t*width = stash->params.width;\n\tif (height != NULL)\n\t\t*height = stash->params.height;\n\treturn stash->texData;\n}\n\nint fonsValidateTexture(FONScontext* stash, int* dirty)\n{\n\tif (stash->dirtyRect[0] < stash->dirtyRect[2] && stash->dirtyRect[1] < stash->dirtyRect[3]) {\n\t\tdirty[0] = stash->dirtyRect[0];\n\t\tdirty[1] = stash->dirtyRect[1];\n\t\tdirty[2] = stash->dirtyRect[2];\n\t\tdirty[3] = stash->dirtyRect[3];\n\t\t// Reset dirty rect\n\t\tstash->dirtyRect[0] = stash->params.width;\n\t\tstash->dirtyRect[1] = stash->params.height;\n\t\tstash->dirtyRect[2] = 0;\n\t\tstash->dirtyRect[3] = 0;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nvoid fonsDeleteInternal(FONScontext* stash)\n{\n\tint i;\n\tif (stash == NULL) return;\n\n\tif (stash->params.renderDelete)\n\t\tstash->params.renderDelete(stash->params.userPtr);\n\n\tfor (i = 0; i < stash->nfonts; ++i)\n\t\tfons__freeFont(stash->fonts[i]);\n\n\tif (stash->atlas) fons__deleteAtlas(stash->atlas);\n\tif (stash->fonts) free(stash->fonts);\n\tif (stash->texData) free(stash->texData);\n\tif (stash->scratch) free(stash->scratch);\n\tfree(stash);\n}\n\nvoid fonsSetErrorCallback(FONScontext* stash, void (*callback)(void* uptr, int error, int val), void* uptr)\n{\n\tif (stash == NULL) return;\n\tstash->handleError = callback;\n\tstash->errorUptr = uptr;\n}\n\nvoid fonsGetAtlasSize(FONScontext* stash, int* width, int* height)\n{\n\tif (stash == NULL) return;\n\t*width = stash->params.width;\n\t*height = stash->params.height;\n}\n\nint fonsExpandAtlas(FONScontext* stash, int width, int height)\n{\n\tint i, maxy = 0;\n\tunsigned char* data = NULL;\n\tif (stash == NULL) return 0;\n\n\twidth = fons__maxi(width, stash->params.width);\n\theight = fons__maxi(height, stash->params.height);\n\n\tif (width == stash->params.width && height == stash->params.height)\n\t\treturn 1;\n\n\t// Flush pending glyphs.\n\tfons__flush(stash);\n\n\t// Create new texture\n\tif (stash->params.renderResize != NULL) {\n\t\tif (stash->params.renderResize(stash->params.userPtr, width, height) == 0)\n\t\t\treturn 0;\n\t}\n\t// Copy old texture data over.\n\tdata = (unsigned char*)malloc(width * height);\n\tif (data == NULL)\n\t\treturn 0;\n\tfor (i = 0; i < stash->params.height; i++) {\n\t\tunsigned char* dst = &data[i*width];\n\t\tunsigned char* src = &stash->texData[i*stash->params.width];\n\t\tmemcpy(dst, src, stash->params.width);\n\t\tif (width > stash->params.width)\n\t\t\tmemset(dst+stash->params.width, 0, width - stash->params.width);\n\t}\n\tif (height > stash->params.height)\n\t\tmemset(&data[stash->params.height * width], 0, (height - stash->params.height) * width);\n\n\tfree(stash->texData);\n\tstash->texData = data;\n\n\t// Increase atlas size\n\tfons__atlasExpand(stash->atlas, width, height);\n\n\t// Add existing data as dirty.\n\tfor (i = 0; i < stash->atlas->nnodes; i++)\n\t\tmaxy = fons__maxi(maxy, stash->atlas->nodes[i].y);\n\tstash->dirtyRect[0] = 0;\n\tstash->dirtyRect[1] = 0;\n\tstash->dirtyRect[2] = stash->params.width;\n\tstash->dirtyRect[3] = maxy;\n\n\tstash->params.width = width;\n\tstash->params.height = height;\n\tstash->itw = 1.0f/stash->params.width;\n\tstash->ith = 1.0f/stash->params.height;\n\n\treturn 1;\n}\n\nint fonsResetAtlas(FONScontext* stash, int width, int height)\n{\n\tint i, j;\n\tif (stash == NULL) return 0;\n\n\t// Flush pending glyphs.\n\tfons__flush(stash);\n\n\t// Create new texture\n\tif (stash->params.renderResize != NULL) {\n\t\tif (stash->params.renderResize(stash->params.userPtr, width, height) == 0)\n\t\t\treturn 0;\n\t}\n\n\t// Reset atlas\n\tfons__atlasReset(stash->atlas, width, height);\n\n\t// Clear texture data.\n\tstash->texData = (unsigned char*)realloc(stash->texData, width * height);\n\tif (stash->texData == NULL) return 0;\n\tmemset(stash->texData, 0, width * height);\n\n\t// Reset dirty rect\n\tstash->dirtyRect[0] = width;\n\tstash->dirtyRect[1] = height;\n\tstash->dirtyRect[2] = 0;\n\tstash->dirtyRect[3] = 0;\n\n\t// Reset cached glyphs\n\tfor (i = 0; i < stash->nfonts; i++) {\n\t\tFONSfont* font = stash->fonts[i];\n\t\tfont->nglyphs = 0;\n\t\tfor (j = 0; j < FONS_HASH_LUT_SIZE; j++)\n\t\t\tfont->lut[j] = -1;\n\t}\n\n\tstash->params.width = width;\n\tstash->params.height = height;\n\tstash->itw = 1.0f/stash->params.width;\n\tstash->ith = 1.0f/stash->params.height;\n\n\t// Add white rect at 0,0 for debug drawing.\n\tfons__addWhiteRect(stash, 2,2);\n\n\treturn 1;\n}\n\n\n#endif\n"
  },
  {
    "path": "phonelibs/nanovg/nanovg.c",
    "content": "//\n// Copyright (c) 2013 Mikko Mononen memon@inside.org\n//\n// This software is provided 'as-is', without any express or implied\n// warranty.  In no event will the authors be held liable for any damages\n// arising from the use of this software.\n// Permission is granted to anyone to use this software for any purpose,\n// including commercial applications, and to alter it and redistribute it\n// freely, subject to the following restrictions:\n// 1. The origin of this software must not be misrepresented; you must not\n//    claim that you wrote the original software. If you use this software\n//    in a product, an acknowledgment in the product documentation would be\n//    appreciated but is not required.\n// 2. Altered source versions must be plainly marked as such, and must not be\n//    misrepresented as being the original software.\n// 3. This notice may not be removed or altered from any source distribution.\n//\n\n#include <stdlib.h>\n#include <stdio.h>\n#include <math.h>\n#include <memory.h>\n\n#include \"nanovg.h\"\n#define FONTSTASH_IMPLEMENTATION\n#include \"fontstash.h\"\n#define STB_IMAGE_IMPLEMENTATION\n#include \"stb_image.h\"\n\n#ifdef _MSC_VER\n#pragma warning(disable: 4100)  // unreferenced formal parameter\n#pragma warning(disable: 4127)  // conditional expression is constant\n#pragma warning(disable: 4204)  // nonstandard extension used : non-constant aggregate initializer\n#pragma warning(disable: 4706)  // assignment within conditional expression\n#endif\n\n#define NVG_INIT_FONTIMAGE_SIZE  512\n#define NVG_MAX_FONTIMAGE_SIZE   2048\n#define NVG_MAX_FONTIMAGES       4\n\n#define NVG_INIT_COMMANDS_SIZE 256\n#define NVG_INIT_POINTS_SIZE 128\n#define NVG_INIT_PATHS_SIZE 16\n#define NVG_INIT_VERTS_SIZE 256\n#define NVG_MAX_STATES 32\n\n#define NVG_KAPPA90 0.5522847493f\t// Length proportional to radius of a cubic bezier handle for 90deg arcs.\n\n#define NVG_COUNTOF(arr) (sizeof(arr) / sizeof(0[arr]))\n\n\nenum NVGcommands {\n\tNVG_MOVETO = 0,\n\tNVG_LINETO = 1,\n\tNVG_BEZIERTO = 2,\n\tNVG_CLOSE = 3,\n\tNVG_WINDING = 4,\n};\n\nenum NVGpointFlags\n{\n\tNVG_PT_CORNER = 0x01,\n\tNVG_PT_LEFT = 0x02,\n\tNVG_PT_BEVEL = 0x04,\n\tNVG_PR_INNERBEVEL = 0x08,\n};\n\nstruct NVGstate {\n\tNVGcompositeOperationState compositeOperation;\n\tNVGpaint fill;\n\tNVGpaint stroke;\n\tfloat strokeWidth;\n\tfloat miterLimit;\n\tint lineJoin;\n\tint lineCap;\n\tfloat alpha;\n\tfloat xform[6];\n\tNVGscissor scissor;\n\tfloat fontSize;\n\tfloat letterSpacing;\n\tfloat lineHeight;\n\tfloat fontBlur;\n\tint textAlign;\n\tint fontId;\n};\ntypedef struct NVGstate NVGstate;\n\nstruct NVGpoint {\n\tfloat x,y;\n\tfloat dx, dy;\n\tfloat len;\n\tfloat dmx, dmy;\n\tunsigned char flags;\n};\ntypedef struct NVGpoint NVGpoint;\n\nstruct NVGpathCache {\n\tNVGpoint* points;\n\tint npoints;\n\tint cpoints;\n\tNVGpath* paths;\n\tint npaths;\n\tint cpaths;\n\tNVGvertex* verts;\n\tint nverts;\n\tint cverts;\n\tfloat bounds[4];\n};\ntypedef struct NVGpathCache NVGpathCache;\n\nstruct NVGcontext {\n\tNVGparams params;\n\tfloat* commands;\n\tint ccommands;\n\tint ncommands;\n\tfloat commandx, commandy;\n\tNVGstate states[NVG_MAX_STATES];\n\tint nstates;\n\tNVGpathCache* cache;\n\tfloat tessTol;\n\tfloat distTol;\n\tfloat fringeWidth;\n\tfloat devicePxRatio;\n\tstruct FONScontext* fs;\n\tint fontImages[NVG_MAX_FONTIMAGES];\n\tint fontImageIdx;\n\tint drawCallCount;\n\tint fillTriCount;\n\tint strokeTriCount;\n\tint textTriCount;\n};\n\nstatic float nvg__sqrtf(float a) { return sqrtf(a); }\nstatic float nvg__modf(float a, float b) { return fmodf(a, b); }\nstatic float nvg__sinf(float a) { return sinf(a); }\nstatic float nvg__cosf(float a) { return cosf(a); }\nstatic float nvg__tanf(float a) { return tanf(a); }\nstatic float nvg__atan2f(float a,float b) { return atan2f(a, b); }\nstatic float nvg__acosf(float a) { return acosf(a); }\n\nstatic int nvg__mini(int a, int b) { return a < b ? a : b; }\nstatic int nvg__maxi(int a, int b) { return a > b ? a : b; }\nstatic int nvg__clampi(int a, int mn, int mx) { return a < mn ? mn : (a > mx ? mx : a); }\nstatic float nvg__minf(float a, float b) { return a < b ? a : b; }\nstatic float nvg__maxf(float a, float b) { return a > b ? a : b; }\nstatic float nvg__absf(float a) { return a >= 0.0f ? a : -a; }\nstatic float nvg__signf(float a) { return a >= 0.0f ? 1.0f : -1.0f; }\nstatic float nvg__clampf(float a, float mn, float mx) { return a < mn ? mn : (a > mx ? mx : a); }\nstatic float nvg__cross(float dx0, float dy0, float dx1, float dy1) { return dx1*dy0 - dx0*dy1; }\n\nstatic float nvg__normalize(float *x, float* y)\n{\n\tfloat d = nvg__sqrtf((*x)*(*x) + (*y)*(*y));\n\tif (d > 1e-6f) {\n\t\tfloat id = 1.0f / d;\n\t\t*x *= id;\n\t\t*y *= id;\n\t}\n\treturn d;\n}\n\n\nstatic void nvg__deletePathCache(NVGpathCache* c)\n{\n\tif (c == NULL) return;\n\tif (c->points != NULL) free(c->points);\n\tif (c->paths != NULL) free(c->paths);\n\tif (c->verts != NULL) free(c->verts);\n\tfree(c);\n}\n\nstatic NVGpathCache* nvg__allocPathCache(void)\n{\n\tNVGpathCache* c = (NVGpathCache*)malloc(sizeof(NVGpathCache));\n\tif (c == NULL) goto error;\n\tmemset(c, 0, sizeof(NVGpathCache));\n\n\tc->points = (NVGpoint*)malloc(sizeof(NVGpoint)*NVG_INIT_POINTS_SIZE);\n\tif (!c->points) goto error;\n\tc->npoints = 0;\n\tc->cpoints = NVG_INIT_POINTS_SIZE;\n\n\tc->paths = (NVGpath*)malloc(sizeof(NVGpath)*NVG_INIT_PATHS_SIZE);\n\tif (!c->paths) goto error;\n\tc->npaths = 0;\n\tc->cpaths = NVG_INIT_PATHS_SIZE;\n\n\tc->verts = (NVGvertex*)malloc(sizeof(NVGvertex)*NVG_INIT_VERTS_SIZE);\n\tif (!c->verts) goto error;\n\tc->nverts = 0;\n\tc->cverts = NVG_INIT_VERTS_SIZE;\n\n\treturn c;\nerror:\n\tnvg__deletePathCache(c);\n\treturn NULL;\n}\n\nstatic void nvg__setDevicePixelRatio(NVGcontext* ctx, float ratio)\n{\n\tctx->tessTol = 0.25f / ratio;\n\tctx->distTol = 0.01f / ratio;\n\tctx->fringeWidth = 1.0f / ratio;\n\tctx->devicePxRatio = ratio;\n}\n\nstatic NVGcompositeOperationState nvg__compositeOperationState(int op)\n{\n\tint sfactor, dfactor;\n\n\tif (op == NVG_SOURCE_OVER)\n\t{\n\t\tsfactor = NVG_ONE;\n\t\tdfactor = NVG_ONE_MINUS_SRC_ALPHA;\n\t}\n\telse if (op == NVG_SOURCE_IN)\n\t{\n\t\tsfactor = NVG_DST_ALPHA;\n\t\tdfactor = NVG_ZERO;\n\t}\n\telse if (op == NVG_SOURCE_OUT)\n\t{\n\t\tsfactor = NVG_ONE_MINUS_DST_ALPHA;\n\t\tdfactor = NVG_ZERO;\n\t}\n\telse if (op == NVG_ATOP)\n\t{\n\t\tsfactor = NVG_DST_ALPHA;\n\t\tdfactor = NVG_ONE_MINUS_SRC_ALPHA;\n\t}\n\telse if (op == NVG_DESTINATION_OVER)\n\t{\n\t\tsfactor = NVG_ONE_MINUS_DST_ALPHA;\n\t\tdfactor = NVG_ONE;\n\t}\n\telse if (op == NVG_DESTINATION_IN)\n\t{\n\t\tsfactor = NVG_ZERO;\n\t\tdfactor = NVG_SRC_ALPHA;\n\t}\n\telse if (op == NVG_DESTINATION_OUT)\n\t{\n\t\tsfactor = NVG_ZERO;\n\t\tdfactor = NVG_ONE_MINUS_SRC_ALPHA;\n\t}\n\telse if (op == NVG_DESTINATION_ATOP)\n\t{\n\t\tsfactor = NVG_ONE_MINUS_DST_ALPHA;\n\t\tdfactor = NVG_SRC_ALPHA;\n\t}\n\telse if (op == NVG_LIGHTER)\n\t{\n\t\tsfactor = NVG_ONE;\n\t\tdfactor = NVG_ONE;\n\t}\n\telse if (op == NVG_COPY)\n\t{\n\t\tsfactor = NVG_ONE;\n\t\tdfactor = NVG_ZERO;\n\t}\n\telse if (op == NVG_XOR)\n\t{\n\t\tsfactor = NVG_ONE_MINUS_DST_ALPHA;\n\t\tdfactor = NVG_ONE_MINUS_SRC_ALPHA;\n\t}\n\n\tNVGcompositeOperationState state;\n\tstate.srcRGB = sfactor;\n\tstate.dstRGB = dfactor;\n\tstate.srcAlpha = sfactor;\n\tstate.dstAlpha = dfactor;\n\treturn state;\n}\n\nstatic NVGstate* nvg__getState(NVGcontext* ctx)\n{\n\treturn &ctx->states[ctx->nstates-1];\n}\n\nNVGcontext* nvgCreateInternal(NVGparams* params)\n{\n\tFONSparams fontParams;\n\tNVGcontext* ctx = (NVGcontext*)malloc(sizeof(NVGcontext));\n\tint i;\n\tif (ctx == NULL) goto error;\n\tmemset(ctx, 0, sizeof(NVGcontext));\n\n\tctx->params = *params;\n\tfor (i = 0; i < NVG_MAX_FONTIMAGES; i++)\n\t\tctx->fontImages[i] = 0;\n\n\tctx->commands = (float*)malloc(sizeof(float)*NVG_INIT_COMMANDS_SIZE);\n\tif (!ctx->commands) goto error;\n\tctx->ncommands = 0;\n\tctx->ccommands = NVG_INIT_COMMANDS_SIZE;\n\n\tctx->cache = nvg__allocPathCache();\n\tif (ctx->cache == NULL) goto error;\n\n\tnvgSave(ctx);\n\tnvgReset(ctx);\n\n\tnvg__setDevicePixelRatio(ctx, 1.0f);\n\n\tif (ctx->params.renderCreate(ctx->params.userPtr) == 0) goto error;\n\n\t// Init font rendering\n\tmemset(&fontParams, 0, sizeof(fontParams));\n\tfontParams.width = NVG_INIT_FONTIMAGE_SIZE;\n\tfontParams.height = NVG_INIT_FONTIMAGE_SIZE;\n\tfontParams.flags = FONS_ZERO_TOPLEFT;\n\tfontParams.renderCreate = NULL;\n\tfontParams.renderUpdate = NULL;\n\tfontParams.renderDraw = NULL;\n\tfontParams.renderDelete = NULL;\n\tfontParams.userPtr = NULL;\n\tctx->fs = fonsCreateInternal(&fontParams);\n\tif (ctx->fs == NULL) goto error;\n\n\t// Create font texture\n\tctx->fontImages[0] = ctx->params.renderCreateTexture(ctx->params.userPtr, NVG_TEXTURE_ALPHA, fontParams.width, fontParams.height, 0, NULL);\n\tif (ctx->fontImages[0] == 0) goto error;\n\tctx->fontImageIdx = 0;\n\n\treturn ctx;\n\nerror:\n\tnvgDeleteInternal(ctx);\n\treturn 0;\n}\n\nNVGparams* nvgInternalParams(NVGcontext* ctx)\n{\n    return &ctx->params;\n}\n\nvoid nvgDeleteInternal(NVGcontext* ctx)\n{\n\tint i;\n\tif (ctx == NULL) return;\n\tif (ctx->commands != NULL) free(ctx->commands);\n\tif (ctx->cache != NULL) nvg__deletePathCache(ctx->cache);\n\n\tif (ctx->fs)\n\t\tfonsDeleteInternal(ctx->fs);\n\n\tfor (i = 0; i < NVG_MAX_FONTIMAGES; i++) {\n\t\tif (ctx->fontImages[i] != 0) {\n\t\t\tnvgDeleteImage(ctx, ctx->fontImages[i]);\n\t\t\tctx->fontImages[i] = 0;\n\t\t}\n\t}\n\n\tif (ctx->params.renderDelete != NULL)\n\t\tctx->params.renderDelete(ctx->params.userPtr);\n\n\tfree(ctx);\n}\n\nvoid nvgBeginFrame(NVGcontext* ctx, int windowWidth, int windowHeight, float devicePixelRatio)\n{\n/*\tprintf(\"Tris: draws:%d  fill:%d  stroke:%d  text:%d  TOT:%d\\n\",\n\t\tctx->drawCallCount, ctx->fillTriCount, ctx->strokeTriCount, ctx->textTriCount,\n\t\tctx->fillTriCount+ctx->strokeTriCount+ctx->textTriCount);*/\n\n\tctx->nstates = 0;\n\tnvgSave(ctx);\n\tnvgReset(ctx);\n\n\tnvg__setDevicePixelRatio(ctx, devicePixelRatio);\n\n\tctx->params.renderViewport(ctx->params.userPtr, windowWidth, windowHeight, devicePixelRatio);\n\n\tctx->drawCallCount = 0;\n\tctx->fillTriCount = 0;\n\tctx->strokeTriCount = 0;\n\tctx->textTriCount = 0;\n}\n\nvoid nvgCancelFrame(NVGcontext* ctx)\n{\n\tctx->params.renderCancel(ctx->params.userPtr);\n}\n\nvoid nvgEndFrame(NVGcontext* ctx)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tctx->params.renderFlush(ctx->params.userPtr, state->compositeOperation);\n\tif (ctx->fontImageIdx != 0) {\n\t\tint fontImage = ctx->fontImages[ctx->fontImageIdx];\n\t\tint i, j, iw, ih;\n\t\t// delete images that smaller than current one\n\t\tif (fontImage == 0)\n\t\t\treturn;\n\t\tnvgImageSize(ctx, fontImage, &iw, &ih);\n\t\tfor (i = j = 0; i < ctx->fontImageIdx; i++) {\n\t\t\tif (ctx->fontImages[i] != 0) {\n\t\t\t\tint nw, nh;\n\t\t\t\tnvgImageSize(ctx, ctx->fontImages[i], &nw, &nh);\n\t\t\t\tif (nw < iw || nh < ih)\n\t\t\t\t\tnvgDeleteImage(ctx, ctx->fontImages[i]);\n\t\t\t\telse\n\t\t\t\t\tctx->fontImages[j++] = ctx->fontImages[i];\n\t\t\t}\n\t\t}\n\t\t// make current font image to first\n\t\tctx->fontImages[j++] = ctx->fontImages[0];\n\t\tctx->fontImages[0] = fontImage;\n\t\tctx->fontImageIdx = 0;\n\t\t// clear all images after j\n\t\tfor (i = j; i < NVG_MAX_FONTIMAGES; i++)\n\t\t\tctx->fontImages[i] = 0;\n\t}\n}\n\nNVGcolor nvgRGB(unsigned char r, unsigned char g, unsigned char b)\n{\n\treturn nvgRGBA(r,g,b,255);\n}\n\nNVGcolor nvgRGBf(float r, float g, float b)\n{\n\treturn nvgRGBAf(r,g,b,1.0f);\n}\n\nNVGcolor nvgRGBA(unsigned char r, unsigned char g, unsigned char b, unsigned char a)\n{\n\tNVGcolor color;\n\t// Use longer initialization to suppress warning.\n\tcolor.r = r / 255.0f;\n\tcolor.g = g / 255.0f;\n\tcolor.b = b / 255.0f;\n\tcolor.a = a / 255.0f;\n\treturn color;\n}\n\nNVGcolor nvgRGBAf(float r, float g, float b, float a)\n{\n\tNVGcolor color;\n\t// Use longer initialization to suppress warning.\n\tcolor.r = r;\n\tcolor.g = g;\n\tcolor.b = b;\n\tcolor.a = a;\n\treturn color;\n}\n\nNVGcolor nvgTransRGBA(NVGcolor c, unsigned char a)\n{\n\tc.a = a / 255.0f;\n\treturn c;\n}\n\nNVGcolor nvgTransRGBAf(NVGcolor c, float a)\n{\n\tc.a = a;\n\treturn c;\n}\n\nNVGcolor nvgLerpRGBA(NVGcolor c0, NVGcolor c1, float u)\n{\n\tint i;\n\tfloat oneminu;\n\tNVGcolor cint = {0};\n\n\tu = nvg__clampf(u, 0.0f, 1.0f);\n\toneminu = 1.0f - u;\n\tfor( i = 0; i <4; i++ )\n\t{\n\t\tcint.rgba[i] = c0.rgba[i] * oneminu + c1.rgba[i] * u;\n\t}\n\n\treturn cint;\n}\n\nNVGcolor nvgHSL(float h, float s, float l)\n{\n\treturn nvgHSLA(h,s,l,255);\n}\n\nstatic float nvg__hue(float h, float m1, float m2)\n{\n\tif (h < 0) h += 1;\n\tif (h > 1) h -= 1;\n\tif (h < 1.0f/6.0f)\n\t\treturn m1 + (m2 - m1) * h * 6.0f;\n\telse if (h < 3.0f/6.0f)\n\t\treturn m2;\n\telse if (h < 4.0f/6.0f)\n\t\treturn m1 + (m2 - m1) * (2.0f/3.0f - h) * 6.0f;\n\treturn m1;\n}\n\nNVGcolor nvgHSLA(float h, float s, float l, unsigned char a)\n{\n\tfloat m1, m2;\n\tNVGcolor col;\n\th = nvg__modf(h, 1.0f);\n\tif (h < 0.0f) h += 1.0f;\n\ts = nvg__clampf(s, 0.0f, 1.0f);\n\tl = nvg__clampf(l, 0.0f, 1.0f);\n\tm2 = l <= 0.5f ? (l * (1 + s)) : (l + s - l * s);\n\tm1 = 2 * l - m2;\n\tcol.r = nvg__clampf(nvg__hue(h + 1.0f/3.0f, m1, m2), 0.0f, 1.0f);\n\tcol.g = nvg__clampf(nvg__hue(h, m1, m2), 0.0f, 1.0f);\n\tcol.b = nvg__clampf(nvg__hue(h - 1.0f/3.0f, m1, m2), 0.0f, 1.0f);\n\tcol.a = a/255.0f;\n\treturn col;\n}\n\nvoid nvgTransformIdentity(float* t)\n{\n\tt[0] = 1.0f; t[1] = 0.0f;\n\tt[2] = 0.0f; t[3] = 1.0f;\n\tt[4] = 0.0f; t[5] = 0.0f;\n}\n\nvoid nvgTransformTranslate(float* t, float tx, float ty)\n{\n\tt[0] = 1.0f; t[1] = 0.0f;\n\tt[2] = 0.0f; t[3] = 1.0f;\n\tt[4] = tx; t[5] = ty;\n}\n\nvoid nvgTransformScale(float* t, float sx, float sy)\n{\n\tt[0] = sx; t[1] = 0.0f;\n\tt[2] = 0.0f; t[3] = sy;\n\tt[4] = 0.0f; t[5] = 0.0f;\n}\n\nvoid nvgTransformRotate(float* t, float a)\n{\n\tfloat cs = nvg__cosf(a), sn = nvg__sinf(a);\n\tt[0] = cs; t[1] = sn;\n\tt[2] = -sn; t[3] = cs;\n\tt[4] = 0.0f; t[5] = 0.0f;\n}\n\nvoid nvgTransformSkewX(float* t, float a)\n{\n\tt[0] = 1.0f; t[1] = 0.0f;\n\tt[2] = nvg__tanf(a); t[3] = 1.0f;\n\tt[4] = 0.0f; t[5] = 0.0f;\n}\n\nvoid nvgTransformSkewY(float* t, float a)\n{\n\tt[0] = 1.0f; t[1] = nvg__tanf(a);\n\tt[2] = 0.0f; t[3] = 1.0f;\n\tt[4] = 0.0f; t[5] = 0.0f;\n}\n\nvoid nvgTransformMultiply(float* t, const float* s)\n{\n\tfloat t0 = t[0] * s[0] + t[1] * s[2];\n\tfloat t2 = t[2] * s[0] + t[3] * s[2];\n\tfloat t4 = t[4] * s[0] + t[5] * s[2] + s[4];\n\tt[1] = t[0] * s[1] + t[1] * s[3];\n\tt[3] = t[2] * s[1] + t[3] * s[3];\n\tt[5] = t[4] * s[1] + t[5] * s[3] + s[5];\n\tt[0] = t0;\n\tt[2] = t2;\n\tt[4] = t4;\n}\n\nvoid nvgTransformPremultiply(float* t, const float* s)\n{\n\tfloat s2[6];\n\tmemcpy(s2, s, sizeof(float)*6);\n\tnvgTransformMultiply(s2, t);\n\tmemcpy(t, s2, sizeof(float)*6);\n}\n\nint nvgTransformInverse(float* inv, const float* t)\n{\n\tdouble invdet, det = (double)t[0] * t[3] - (double)t[2] * t[1];\n\tif (det > -1e-6 && det < 1e-6) {\n\t\tnvgTransformIdentity(inv);\n\t\treturn 0;\n\t}\n\tinvdet = 1.0 / det;\n\tinv[0] = (float)(t[3] * invdet);\n\tinv[2] = (float)(-t[2] * invdet);\n\tinv[4] = (float)(((double)t[2] * t[5] - (double)t[3] * t[4]) * invdet);\n\tinv[1] = (float)(-t[1] * invdet);\n\tinv[3] = (float)(t[0] * invdet);\n\tinv[5] = (float)(((double)t[1] * t[4] - (double)t[0] * t[5]) * invdet);\n\treturn 1;\n}\n\nvoid nvgTransformPoint(float* dx, float* dy, const float* t, float sx, float sy)\n{\n\t*dx = sx*t[0] + sy*t[2] + t[4];\n\t*dy = sx*t[1] + sy*t[3] + t[5];\n}\n\nfloat nvgDegToRad(float deg)\n{\n\treturn deg / 180.0f * NVG_PI;\n}\n\nfloat nvgRadToDeg(float rad)\n{\n\treturn rad / NVG_PI * 180.0f;\n}\n\nstatic void nvg__setPaintColor(NVGpaint* p, NVGcolor color)\n{\n\tmemset(p, 0, sizeof(*p));\n\tnvgTransformIdentity(p->xform);\n\tp->radius = 0.0f;\n\tp->feather = 1.0f;\n\tp->innerColor = color;\n\tp->outerColor = color;\n}\n\n\n// State handling\nvoid nvgSave(NVGcontext* ctx)\n{\n\tif (ctx->nstates >= NVG_MAX_STATES)\n\t\treturn;\n\tif (ctx->nstates > 0)\n\t\tmemcpy(&ctx->states[ctx->nstates], &ctx->states[ctx->nstates-1], sizeof(NVGstate));\n\tctx->nstates++;\n}\n\nvoid nvgRestore(NVGcontext* ctx)\n{\n\tif (ctx->nstates <= 1)\n\t\treturn;\n\tctx->nstates--;\n}\n\nvoid nvgReset(NVGcontext* ctx)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tmemset(state, 0, sizeof(*state));\n\n\tnvg__setPaintColor(&state->fill, nvgRGBA(255,255,255,255));\n\tnvg__setPaintColor(&state->stroke, nvgRGBA(0,0,0,255));\n\tstate->compositeOperation = nvg__compositeOperationState(NVG_SOURCE_OVER);\n\tstate->strokeWidth = 1.0f;\n\tstate->miterLimit = 10.0f;\n\tstate->lineCap = NVG_BUTT;\n\tstate->lineJoin = NVG_MITER;\n\tstate->alpha = 1.0f;\n\tnvgTransformIdentity(state->xform);\n\n\tstate->scissor.extent[0] = -1.0f;\n\tstate->scissor.extent[1] = -1.0f;\n\n\tstate->fontSize = 16.0f;\n\tstate->letterSpacing = 0.0f;\n\tstate->lineHeight = 1.0f;\n\tstate->fontBlur = 0.0f;\n\tstate->textAlign = NVG_ALIGN_LEFT | NVG_ALIGN_BASELINE;\n\tstate->fontId = 0;\n}\n\n// State setting\nvoid nvgStrokeWidth(NVGcontext* ctx, float width)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->strokeWidth = width;\n}\n\nvoid nvgMiterLimit(NVGcontext* ctx, float limit)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->miterLimit = limit;\n}\n\nvoid nvgLineCap(NVGcontext* ctx, int cap)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->lineCap = cap;\n}\n\nvoid nvgLineJoin(NVGcontext* ctx, int join)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->lineJoin = join;\n}\n\nvoid nvgGlobalAlpha(NVGcontext* ctx, float alpha)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->alpha = alpha;\n}\n\nvoid nvgTransform(NVGcontext* ctx, float a, float b, float c, float d, float e, float f)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat t[6] = { a, b, c, d, e, f };\n\tnvgTransformPremultiply(state->xform, t);\n}\n\nvoid nvgResetTransform(NVGcontext* ctx)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tnvgTransformIdentity(state->xform);\n}\n\nvoid nvgTranslate(NVGcontext* ctx, float x, float y)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat t[6];\n\tnvgTransformTranslate(t, x,y);\n\tnvgTransformPremultiply(state->xform, t);\n}\n\nvoid nvgRotate(NVGcontext* ctx, float angle)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat t[6];\n\tnvgTransformRotate(t, angle);\n\tnvgTransformPremultiply(state->xform, t);\n}\n\nvoid nvgSkewX(NVGcontext* ctx, float angle)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat t[6];\n\tnvgTransformSkewX(t, angle);\n\tnvgTransformPremultiply(state->xform, t);\n}\n\nvoid nvgSkewY(NVGcontext* ctx, float angle)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat t[6];\n\tnvgTransformSkewY(t, angle);\n\tnvgTransformPremultiply(state->xform, t);\n}\n\nvoid nvgScale(NVGcontext* ctx, float x, float y)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat t[6];\n\tnvgTransformScale(t, x,y);\n\tnvgTransformPremultiply(state->xform, t);\n}\n\nvoid nvgCurrentTransform(NVGcontext* ctx, float* xform)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tif (xform == NULL) return;\n\tmemcpy(xform, state->xform, sizeof(float)*6);\n}\n\nvoid nvgStrokeColor(NVGcontext* ctx, NVGcolor color)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tnvg__setPaintColor(&state->stroke, color);\n}\n\nvoid nvgStrokePaint(NVGcontext* ctx, NVGpaint paint)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->stroke = paint;\n\tnvgTransformMultiply(state->stroke.xform, state->xform);\n}\n\nvoid nvgFillColor(NVGcontext* ctx, NVGcolor color)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tnvg__setPaintColor(&state->fill, color);\n}\n\nvoid nvgFillPaint(NVGcontext* ctx, NVGpaint paint)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->fill = paint;\n\tnvgTransformMultiply(state->fill.xform, state->xform);\n}\n\nint nvgCreateImage(NVGcontext* ctx, const char* filename, int imageFlags)\n{\n\tint w, h, n, image;\n\tunsigned char* img;\n\tstbi_set_unpremultiply_on_load(1);\n\tstbi_convert_iphone_png_to_rgb(1);\n\timg = stbi_load(filename, &w, &h, &n, 4);\n\tif (img == NULL) {\n//\t\tprintf(\"Failed to load %s - %s\\n\", filename, stbi_failure_reason());\n\t\treturn 0;\n\t}\n\timage = nvgCreateImageRGBA(ctx, w, h, imageFlags, img);\n\tstbi_image_free(img);\n\treturn image;\n}\n\nint nvgCreateImageMem(NVGcontext* ctx, int imageFlags, unsigned char* data, int ndata)\n{\n\tint w, h, n, image;\n\tunsigned char* img = stbi_load_from_memory(data, ndata, &w, &h, &n, 4);\n\tif (img == NULL) {\n//\t\tprintf(\"Failed to load %s - %s\\n\", filename, stbi_failure_reason());\n\t\treturn 0;\n\t}\n\timage = nvgCreateImageRGBA(ctx, w, h, imageFlags, img);\n\tstbi_image_free(img);\n\treturn image;\n}\n\nint nvgCreateImageRGBA(NVGcontext* ctx, int w, int h, int imageFlags, const unsigned char* data)\n{\n\treturn ctx->params.renderCreateTexture(ctx->params.userPtr, NVG_TEXTURE_RGBA, w, h, imageFlags, data);\n}\n\nvoid nvgUpdateImage(NVGcontext* ctx, int image, const unsigned char* data)\n{\n\tint w, h;\n\tctx->params.renderGetTextureSize(ctx->params.userPtr, image, &w, &h);\n\tctx->params.renderUpdateTexture(ctx->params.userPtr, image, 0,0, w,h, data);\n}\n\nvoid nvgImageSize(NVGcontext* ctx, int image, int* w, int* h)\n{\n\tctx->params.renderGetTextureSize(ctx->params.userPtr, image, w, h);\n}\n\nvoid nvgDeleteImage(NVGcontext* ctx, int image)\n{\n\tctx->params.renderDeleteTexture(ctx->params.userPtr, image);\n}\n\nNVGpaint nvgLinearGradient(NVGcontext* ctx,\n\t\t\t\t\t\t\t\t  float sx, float sy, float ex, float ey,\n\t\t\t\t\t\t\t\t  NVGcolor icol, NVGcolor ocol)\n{\n\tNVGpaint p;\n\tfloat dx, dy, d;\n\tconst float large = 1e5;\n\tNVG_NOTUSED(ctx);\n\tmemset(&p, 0, sizeof(p));\n\n\t// Calculate transform aligned to the line\n\tdx = ex - sx;\n\tdy = ey - sy;\n\td = sqrtf(dx*dx + dy*dy);\n\tif (d > 0.0001f) {\n\t\tdx /= d;\n\t\tdy /= d;\n\t} else {\n\t\tdx = 0;\n\t\tdy = 1;\n\t}\n\n\tp.xform[0] = dy; p.xform[1] = -dx;\n\tp.xform[2] = dx; p.xform[3] = dy;\n\tp.xform[4] = sx - dx*large; p.xform[5] = sy - dy*large;\n\n\tp.extent[0] = large;\n\tp.extent[1] = large + d*0.5f;\n\n\tp.radius = 0.0f;\n\n\tp.feather = nvg__maxf(1.0f, d);\n\n\tp.innerColor = icol;\n\tp.outerColor = ocol;\n\n\treturn p;\n}\n\nNVGpaint nvgRadialGradient(NVGcontext* ctx,\n\t\t\t\t\t\t\t\t  float cx, float cy, float inr, float outr,\n\t\t\t\t\t\t\t\t  NVGcolor icol, NVGcolor ocol)\n{\n\tNVGpaint p;\n\tfloat r = (inr+outr)*0.5f;\n\tfloat f = (outr-inr);\n\tNVG_NOTUSED(ctx);\n\tmemset(&p, 0, sizeof(p));\n\n\tnvgTransformIdentity(p.xform);\n\tp.xform[4] = cx;\n\tp.xform[5] = cy;\n\n\tp.extent[0] = r;\n\tp.extent[1] = r;\n\n\tp.radius = r;\n\n\tp.feather = nvg__maxf(1.0f, f);\n\n\tp.innerColor = icol;\n\tp.outerColor = ocol;\n\n\treturn p;\n}\n\nNVGpaint nvgBoxGradient(NVGcontext* ctx,\n\t\t\t\t\t\t\t   float x, float y, float w, float h, float r, float f,\n\t\t\t\t\t\t\t   NVGcolor icol, NVGcolor ocol)\n{\n\tNVGpaint p;\n\tNVG_NOTUSED(ctx);\n\tmemset(&p, 0, sizeof(p));\n\n\tnvgTransformIdentity(p.xform);\n\tp.xform[4] = x+w*0.5f;\n\tp.xform[5] = y+h*0.5f;\n\n\tp.extent[0] = w*0.5f;\n\tp.extent[1] = h*0.5f;\n\n\tp.radius = r;\n\n\tp.feather = nvg__maxf(1.0f, f);\n\n\tp.innerColor = icol;\n\tp.outerColor = ocol;\n\n\treturn p;\n}\n\n\nNVGpaint nvgImagePattern(NVGcontext* ctx,\n\t\t\t\t\t\t\t\tfloat cx, float cy, float w, float h, float angle,\n\t\t\t\t\t\t\t\tint image, float alpha)\n{\n\tNVGpaint p;\n\tNVG_NOTUSED(ctx);\n\tmemset(&p, 0, sizeof(p));\n\n\tnvgTransformRotate(p.xform, angle);\n\tp.xform[4] = cx;\n\tp.xform[5] = cy;\n\n\tp.extent[0] = w;\n\tp.extent[1] = h;\n\n\tp.image = image;\n\n\tp.innerColor = p.outerColor = nvgRGBAf(1,1,1,alpha);\n\n\treturn p;\n}\n\n// Scissoring\nvoid nvgScissor(NVGcontext* ctx, float x, float y, float w, float h)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\n\tw = nvg__maxf(0.0f, w);\n\th = nvg__maxf(0.0f, h);\n\n\tnvgTransformIdentity(state->scissor.xform);\n\tstate->scissor.xform[4] = x+w*0.5f;\n\tstate->scissor.xform[5] = y+h*0.5f;\n\tnvgTransformMultiply(state->scissor.xform, state->xform);\n\n\tstate->scissor.extent[0] = w*0.5f;\n\tstate->scissor.extent[1] = h*0.5f;\n}\n\nstatic void nvg__isectRects(float* dst,\n\t\t\t\t\t\t\tfloat ax, float ay, float aw, float ah,\n\t\t\t\t\t\t\tfloat bx, float by, float bw, float bh)\n{\n\tfloat minx = nvg__maxf(ax, bx);\n\tfloat miny = nvg__maxf(ay, by);\n\tfloat maxx = nvg__minf(ax+aw, bx+bw);\n\tfloat maxy = nvg__minf(ay+ah, by+bh);\n\tdst[0] = minx;\n\tdst[1] = miny;\n\tdst[2] = nvg__maxf(0.0f, maxx - minx);\n\tdst[3] = nvg__maxf(0.0f, maxy - miny);\n}\n\nvoid nvgIntersectScissor(NVGcontext* ctx, float x, float y, float w, float h)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat pxform[6], invxorm[6];\n\tfloat rect[4];\n\tfloat ex, ey, tex, tey;\n\n\t// If no previous scissor has been set, set the scissor as current scissor.\n\tif (state->scissor.extent[0] < 0) {\n\t\tnvgScissor(ctx, x, y, w, h);\n\t\treturn;\n\t}\n\n\t// Transform the current scissor rect into current transform space.\n\t// If there is difference in rotation, this will be approximation.\n\tmemcpy(pxform, state->scissor.xform, sizeof(float)*6);\n\tex = state->scissor.extent[0];\n\tey = state->scissor.extent[1];\n\tnvgTransformInverse(invxorm, state->xform);\n\tnvgTransformMultiply(pxform, invxorm);\n\ttex = ex*nvg__absf(pxform[0]) + ey*nvg__absf(pxform[2]);\n\ttey = ex*nvg__absf(pxform[1]) + ey*nvg__absf(pxform[3]);\n\n\t// Intersect rects.\n\tnvg__isectRects(rect, pxform[4]-tex,pxform[5]-tey,tex*2,tey*2, x,y,w,h);\n\n\tnvgScissor(ctx, rect[0], rect[1], rect[2], rect[3]);\n}\n\nvoid nvgResetScissor(NVGcontext* ctx)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tmemset(state->scissor.xform, 0, sizeof(state->scissor.xform));\n\tstate->scissor.extent[0] = -1.0f;\n\tstate->scissor.extent[1] = -1.0f;\n}\n\n// Global composite operation.\nvoid nvgGlobalCompositeOperation(NVGcontext* ctx, int op)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->compositeOperation = nvg__compositeOperationState(op);\n}\n\nvoid nvgGlobalCompositeBlendFunc(NVGcontext* ctx, int sfactor, int dfactor)\n{\n\tnvgGlobalCompositeBlendFuncSeparate(ctx, sfactor, dfactor, sfactor, dfactor);\n}\n\nvoid nvgGlobalCompositeBlendFuncSeparate(NVGcontext* ctx, int srcRGB, int dstRGB, int srcAlpha, int dstAlpha)\n{\n\tNVGcompositeOperationState op;\n\top.srcRGB = srcRGB;\n\top.dstRGB = dstRGB;\n\top.srcAlpha = srcAlpha;\n\top.dstAlpha = dstAlpha;\n\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->compositeOperation = op;\n}\n\nstatic int nvg__ptEquals(float x1, float y1, float x2, float y2, float tol)\n{\n\tfloat dx = x2 - x1;\n\tfloat dy = y2 - y1;\n\treturn dx*dx + dy*dy < tol*tol;\n}\n\nstatic float nvg__distPtSeg(float x, float y, float px, float py, float qx, float qy)\n{\n\tfloat pqx, pqy, dx, dy, d, t;\n\tpqx = qx-px;\n\tpqy = qy-py;\n\tdx = x-px;\n\tdy = y-py;\n\td = pqx*pqx + pqy*pqy;\n\tt = pqx*dx + pqy*dy;\n\tif (d > 0) t /= d;\n\tif (t < 0) t = 0;\n\telse if (t > 1) t = 1;\n\tdx = px + t*pqx - x;\n\tdy = py + t*pqy - y;\n\treturn dx*dx + dy*dy;\n}\n\nstatic void nvg__appendCommands(NVGcontext* ctx, float* vals, int nvals)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tint i;\n\n\tif (ctx->ncommands+nvals > ctx->ccommands) {\n\t\tfloat* commands;\n\t\tint ccommands = ctx->ncommands+nvals + ctx->ccommands/2;\n\t\tcommands = (float*)realloc(ctx->commands, sizeof(float)*ccommands);\n\t\tif (commands == NULL) return;\n\t\tctx->commands = commands;\n\t\tctx->ccommands = ccommands;\n\t}\n\n\tif ((int)vals[0] != NVG_CLOSE && (int)vals[0] != NVG_WINDING) {\n\t\tctx->commandx = vals[nvals-2];\n\t\tctx->commandy = vals[nvals-1];\n\t}\n\n\t// transform commands\n\ti = 0;\n\twhile (i < nvals) {\n\t\tint cmd = (int)vals[i];\n\t\tswitch (cmd) {\n\t\tcase NVG_MOVETO:\n\t\t\tnvgTransformPoint(&vals[i+1],&vals[i+2], state->xform, vals[i+1],vals[i+2]);\n\t\t\ti += 3;\n\t\t\tbreak;\n\t\tcase NVG_LINETO:\n\t\t\tnvgTransformPoint(&vals[i+1],&vals[i+2], state->xform, vals[i+1],vals[i+2]);\n\t\t\ti += 3;\n\t\t\tbreak;\n\t\tcase NVG_BEZIERTO:\n\t\t\tnvgTransformPoint(&vals[i+1],&vals[i+2], state->xform, vals[i+1],vals[i+2]);\n\t\t\tnvgTransformPoint(&vals[i+3],&vals[i+4], state->xform, vals[i+3],vals[i+4]);\n\t\t\tnvgTransformPoint(&vals[i+5],&vals[i+6], state->xform, vals[i+5],vals[i+6]);\n\t\t\ti += 7;\n\t\t\tbreak;\n\t\tcase NVG_CLOSE:\n\t\t\ti++;\n\t\t\tbreak;\n\t\tcase NVG_WINDING:\n\t\t\ti += 2;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\ti++;\n\t\t}\n\t}\n\n\tmemcpy(&ctx->commands[ctx->ncommands], vals, nvals*sizeof(float));\n\n\tctx->ncommands += nvals;\n}\n\n\nstatic void nvg__clearPathCache(NVGcontext* ctx)\n{\n\tctx->cache->npoints = 0;\n\tctx->cache->npaths = 0;\n}\n\nstatic NVGpath* nvg__lastPath(NVGcontext* ctx)\n{\n\tif (ctx->cache->npaths > 0)\n\t\treturn &ctx->cache->paths[ctx->cache->npaths-1];\n\treturn NULL;\n}\n\nstatic void nvg__addPath(NVGcontext* ctx)\n{\n\tNVGpath* path;\n\tif (ctx->cache->npaths+1 > ctx->cache->cpaths) {\n\t\tNVGpath* paths;\n\t\tint cpaths = ctx->cache->npaths+1 + ctx->cache->cpaths/2;\n\t\tpaths = (NVGpath*)realloc(ctx->cache->paths, sizeof(NVGpath)*cpaths);\n\t\tif (paths == NULL) return;\n\t\tctx->cache->paths = paths;\n\t\tctx->cache->cpaths = cpaths;\n\t}\n\tpath = &ctx->cache->paths[ctx->cache->npaths];\n\tmemset(path, 0, sizeof(*path));\n\tpath->first = ctx->cache->npoints;\n\tpath->winding = NVG_CCW;\n\n\tctx->cache->npaths++;\n}\n\nstatic NVGpoint* nvg__lastPoint(NVGcontext* ctx)\n{\n\tif (ctx->cache->npoints > 0)\n\t\treturn &ctx->cache->points[ctx->cache->npoints-1];\n\treturn NULL;\n}\n\nstatic void nvg__addPoint(NVGcontext* ctx, float x, float y, int flags)\n{\n\tNVGpath* path = nvg__lastPath(ctx);\n\tNVGpoint* pt;\n\tif (path == NULL) return;\n\n\tif (path->count > 0 && ctx->cache->npoints > 0) {\n\t\tpt = nvg__lastPoint(ctx);\n\t\tif (nvg__ptEquals(pt->x,pt->y, x,y, ctx->distTol)) {\n\t\t\tpt->flags |= flags;\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (ctx->cache->npoints+1 > ctx->cache->cpoints) {\n\t\tNVGpoint* points;\n\t\tint cpoints = ctx->cache->npoints+1 + ctx->cache->cpoints/2;\n\t\tpoints = (NVGpoint*)realloc(ctx->cache->points, sizeof(NVGpoint)*cpoints);\n\t\tif (points == NULL) return;\n\t\tctx->cache->points = points;\n\t\tctx->cache->cpoints = cpoints;\n\t}\n\n\tpt = &ctx->cache->points[ctx->cache->npoints];\n\tmemset(pt, 0, sizeof(*pt));\n\tpt->x = x;\n\tpt->y = y;\n\tpt->flags = (unsigned char)flags;\n\n\tctx->cache->npoints++;\n\tpath->count++;\n}\n\nstatic void nvg__closePath(NVGcontext* ctx)\n{\n\tNVGpath* path = nvg__lastPath(ctx);\n\tif (path == NULL) return;\n\tpath->closed = 1;\n}\n\nstatic void nvg__pathWinding(NVGcontext* ctx, int winding)\n{\n\tNVGpath* path = nvg__lastPath(ctx);\n\tif (path == NULL) return;\n\tpath->winding = winding;\n}\n\nstatic float nvg__getAverageScale(float *t)\n{\n\tfloat sx = sqrtf(t[0]*t[0] + t[2]*t[2]);\n\tfloat sy = sqrtf(t[1]*t[1] + t[3]*t[3]);\n\treturn (sx + sy) * 0.5f;\n}\n\nstatic NVGvertex* nvg__allocTempVerts(NVGcontext* ctx, int nverts)\n{\n\tif (nverts > ctx->cache->cverts) {\n\t\tNVGvertex* verts;\n\t\tint cverts = (nverts + 0xff) & ~0xff; // Round up to prevent allocations when things change just slightly.\n\t\tverts = (NVGvertex*)realloc(ctx->cache->verts, sizeof(NVGvertex)*cverts);\n\t\tif (verts == NULL) return NULL;\n\t\tctx->cache->verts = verts;\n\t\tctx->cache->cverts = cverts;\n\t}\n\n\treturn ctx->cache->verts;\n}\n\nstatic float nvg__triarea2(float ax, float ay, float bx, float by, float cx, float cy)\n{\n\tfloat abx = bx - ax;\n\tfloat aby = by - ay;\n\tfloat acx = cx - ax;\n\tfloat acy = cy - ay;\n\treturn acx*aby - abx*acy;\n}\n\nstatic float nvg__polyArea(NVGpoint* pts, int npts)\n{\n\tint i;\n\tfloat area = 0;\n\tfor (i = 2; i < npts; i++) {\n\t\tNVGpoint* a = &pts[0];\n\t\tNVGpoint* b = &pts[i-1];\n\t\tNVGpoint* c = &pts[i];\n\t\tarea += nvg__triarea2(a->x,a->y, b->x,b->y, c->x,c->y);\n\t}\n\treturn area * 0.5f;\n}\n\nstatic void nvg__polyReverse(NVGpoint* pts, int npts)\n{\n\tNVGpoint tmp;\n\tint i = 0, j = npts-1;\n\twhile (i < j) {\n\t\ttmp = pts[i];\n\t\tpts[i] = pts[j];\n\t\tpts[j] = tmp;\n\t\ti++;\n\t\tj--;\n\t}\n}\n\n\nstatic void nvg__vset(NVGvertex* vtx, float x, float y, float u, float v)\n{\n\tvtx->x = x;\n\tvtx->y = y;\n\tvtx->u = u;\n\tvtx->v = v;\n}\n\nstatic void nvg__tesselateBezier(NVGcontext* ctx,\n\t\t\t\t\t\t\t\t float x1, float y1, float x2, float y2,\n\t\t\t\t\t\t\t\t float x3, float y3, float x4, float y4,\n\t\t\t\t\t\t\t\t int level, int type)\n{\n\tfloat x12,y12,x23,y23,x34,y34,x123,y123,x234,y234,x1234,y1234;\n\tfloat dx,dy,d2,d3;\n\n\tif (level > 10) return;\n\n\tx12 = (x1+x2)*0.5f;\n\ty12 = (y1+y2)*0.5f;\n\tx23 = (x2+x3)*0.5f;\n\ty23 = (y2+y3)*0.5f;\n\tx34 = (x3+x4)*0.5f;\n\ty34 = (y3+y4)*0.5f;\n\tx123 = (x12+x23)*0.5f;\n\ty123 = (y12+y23)*0.5f;\n\n\tdx = x4 - x1;\n\tdy = y4 - y1;\n\td2 = nvg__absf(((x2 - x4) * dy - (y2 - y4) * dx));\n\td3 = nvg__absf(((x3 - x4) * dy - (y3 - y4) * dx));\n\n\tif ((d2 + d3)*(d2 + d3) < ctx->tessTol * (dx*dx + dy*dy)) {\n\t\tnvg__addPoint(ctx, x4, y4, type);\n\t\treturn;\n\t}\n\n/*\tif (nvg__absf(x1+x3-x2-x2) + nvg__absf(y1+y3-y2-y2) + nvg__absf(x2+x4-x3-x3) + nvg__absf(y2+y4-y3-y3) < ctx->tessTol) {\n\t\tnvg__addPoint(ctx, x4, y4, type);\n\t\treturn;\n\t}*/\n\n\tx234 = (x23+x34)*0.5f;\n\ty234 = (y23+y34)*0.5f;\n\tx1234 = (x123+x234)*0.5f;\n\ty1234 = (y123+y234)*0.5f;\n\n\tnvg__tesselateBezier(ctx, x1,y1, x12,y12, x123,y123, x1234,y1234, level+1, 0);\n\tnvg__tesselateBezier(ctx, x1234,y1234, x234,y234, x34,y34, x4,y4, level+1, type);\n}\n\nstatic void nvg__flattenPaths(NVGcontext* ctx)\n{\n\tNVGpathCache* cache = ctx->cache;\n//\tNVGstate* state = nvg__getState(ctx);\n\tNVGpoint* last;\n\tNVGpoint* p0;\n\tNVGpoint* p1;\n\tNVGpoint* pts;\n\tNVGpath* path;\n\tint i, j;\n\tfloat* cp1;\n\tfloat* cp2;\n\tfloat* p;\n\tfloat area;\n\n\tif (cache->npaths > 0)\n\t\treturn;\n\n\t// Flatten\n\ti = 0;\n\twhile (i < ctx->ncommands) {\n\t\tint cmd = (int)ctx->commands[i];\n\t\tswitch (cmd) {\n\t\tcase NVG_MOVETO:\n\t\t\tnvg__addPath(ctx);\n\t\t\tp = &ctx->commands[i+1];\n\t\t\tnvg__addPoint(ctx, p[0], p[1], NVG_PT_CORNER);\n\t\t\ti += 3;\n\t\t\tbreak;\n\t\tcase NVG_LINETO:\n\t\t\tp = &ctx->commands[i+1];\n\t\t\tnvg__addPoint(ctx, p[0], p[1], NVG_PT_CORNER);\n\t\t\ti += 3;\n\t\t\tbreak;\n\t\tcase NVG_BEZIERTO:\n\t\t\tlast = nvg__lastPoint(ctx);\n\t\t\tif (last != NULL) {\n\t\t\t\tcp1 = &ctx->commands[i+1];\n\t\t\t\tcp2 = &ctx->commands[i+3];\n\t\t\t\tp = &ctx->commands[i+5];\n\t\t\t\tnvg__tesselateBezier(ctx, last->x,last->y, cp1[0],cp1[1], cp2[0],cp2[1], p[0],p[1], 0, NVG_PT_CORNER);\n\t\t\t}\n\t\t\ti += 7;\n\t\t\tbreak;\n\t\tcase NVG_CLOSE:\n\t\t\tnvg__closePath(ctx);\n\t\t\ti++;\n\t\t\tbreak;\n\t\tcase NVG_WINDING:\n\t\t\tnvg__pathWinding(ctx, (int)ctx->commands[i+1]);\n\t\t\ti += 2;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\ti++;\n\t\t}\n\t}\n\n\tcache->bounds[0] = cache->bounds[1] = 1e6f;\n\tcache->bounds[2] = cache->bounds[3] = -1e6f;\n\n\t// Calculate the direction and length of line segments.\n\tfor (j = 0; j < cache->npaths; j++) {\n\t\tpath = &cache->paths[j];\n\t\tpts = &cache->points[path->first];\n\n\t\t// If the first and last points are the same, remove the last, mark as closed path.\n\t\tp0 = &pts[path->count-1];\n\t\tp1 = &pts[0];\n\t\tif (nvg__ptEquals(p0->x,p0->y, p1->x,p1->y, ctx->distTol)) {\n\t\t\tpath->count--;\n\t\t\tp0 = &pts[path->count-1];\n\t\t\tpath->closed = 1;\n\t\t}\n\n\t\t// Enforce winding.\n\t\tif (path->count > 2) {\n\t\t\tarea = nvg__polyArea(pts, path->count);\n\t\t\tif (path->winding == NVG_CCW && area < 0.0f)\n\t\t\t\tnvg__polyReverse(pts, path->count);\n\t\t\tif (path->winding == NVG_CW && area > 0.0f)\n\t\t\t\tnvg__polyReverse(pts, path->count);\n\t\t}\n\n\t\tfor(i = 0; i < path->count; i++) {\n\t\t\t// Calculate segment direction and length\n\t\t\tp0->dx = p1->x - p0->x;\n\t\t\tp0->dy = p1->y - p0->y;\n\t\t\tp0->len = nvg__normalize(&p0->dx, &p0->dy);\n\t\t\t// Update bounds\n\t\t\tcache->bounds[0] = nvg__minf(cache->bounds[0], p0->x);\n\t\t\tcache->bounds[1] = nvg__minf(cache->bounds[1], p0->y);\n\t\t\tcache->bounds[2] = nvg__maxf(cache->bounds[2], p0->x);\n\t\t\tcache->bounds[3] = nvg__maxf(cache->bounds[3], p0->y);\n\t\t\t// Advance\n\t\t\tp0 = p1++;\n\t\t}\n\t}\n}\n\nstatic int nvg__curveDivs(float r, float arc, float tol)\n{\n\tfloat da = acosf(r / (r + tol)) * 2.0f;\n\treturn nvg__maxi(2, (int)ceilf(arc / da));\n}\n\nstatic void nvg__chooseBevel(int bevel, NVGpoint* p0, NVGpoint* p1, float w,\n\t\t\t\t\t\t\tfloat* x0, float* y0, float* x1, float* y1)\n{\n\tif (bevel) {\n\t\t*x0 = p1->x + p0->dy * w;\n\t\t*y0 = p1->y - p0->dx * w;\n\t\t*x1 = p1->x + p1->dy * w;\n\t\t*y1 = p1->y - p1->dx * w;\n\t} else {\n\t\t*x0 = p1->x + p1->dmx * w;\n\t\t*y0 = p1->y + p1->dmy * w;\n\t\t*x1 = p1->x + p1->dmx * w;\n\t\t*y1 = p1->y + p1->dmy * w;\n\t}\n}\n\nstatic NVGvertex* nvg__roundJoin(NVGvertex* dst, NVGpoint* p0, NVGpoint* p1,\n\t\t\t\t\t\t\t\t\t\tfloat lw, float rw, float lu, float ru, int ncap, float fringe)\n{\n\tint i, n;\n\tfloat dlx0 = p0->dy;\n\tfloat dly0 = -p0->dx;\n\tfloat dlx1 = p1->dy;\n\tfloat dly1 = -p1->dx;\n\tNVG_NOTUSED(fringe);\n\n\tif (p1->flags & NVG_PT_LEFT) {\n\t\tfloat lx0,ly0,lx1,ly1,a0,a1;\n\t\tnvg__chooseBevel(p1->flags & NVG_PR_INNERBEVEL, p0, p1, lw, &lx0,&ly0, &lx1,&ly1);\n\t\ta0 = atan2f(-dly0, -dlx0);\n\t\ta1 = atan2f(-dly1, -dlx1);\n\t\tif (a1 > a0) a1 -= NVG_PI*2;\n\n\t\tnvg__vset(dst, lx0, ly0, lu,1); dst++;\n\t\tnvg__vset(dst, p1->x - dlx0*rw, p1->y - dly0*rw, ru,1); dst++;\n\n\t\tn = nvg__clampi((int)ceilf(((a0 - a1) / NVG_PI) * ncap), 2, ncap);\n\t\tfor (i = 0; i < n; i++) {\n\t\t\tfloat u = i/(float)(n-1);\n\t\t\tfloat a = a0 + u*(a1-a0);\n\t\t\tfloat rx = p1->x + cosf(a) * rw;\n\t\t\tfloat ry = p1->y + sinf(a) * rw;\n\t\t\tnvg__vset(dst, p1->x, p1->y, 0.5f,1); dst++;\n\t\t\tnvg__vset(dst, rx, ry, ru,1); dst++;\n\t\t}\n\n\t\tnvg__vset(dst, lx1, ly1, lu,1); dst++;\n\t\tnvg__vset(dst, p1->x - dlx1*rw, p1->y - dly1*rw, ru,1); dst++;\n\n\t} else {\n\t\tfloat rx0,ry0,rx1,ry1,a0,a1;\n\t\tnvg__chooseBevel(p1->flags & NVG_PR_INNERBEVEL, p0, p1, -rw, &rx0,&ry0, &rx1,&ry1);\n\t\ta0 = atan2f(dly0, dlx0);\n\t\ta1 = atan2f(dly1, dlx1);\n\t\tif (a1 < a0) a1 += NVG_PI*2;\n\n\t\tnvg__vset(dst, p1->x + dlx0*rw, p1->y + dly0*rw, lu,1); dst++;\n\t\tnvg__vset(dst, rx0, ry0, ru,1); dst++;\n\n\t\tn = nvg__clampi((int)ceilf(((a1 - a0) / NVG_PI) * ncap), 2, ncap);\n\t\tfor (i = 0; i < n; i++) {\n\t\t\tfloat u = i/(float)(n-1);\n\t\t\tfloat a = a0 + u*(a1-a0);\n\t\t\tfloat lx = p1->x + cosf(a) * lw;\n\t\t\tfloat ly = p1->y + sinf(a) * lw;\n\t\t\tnvg__vset(dst, lx, ly, lu,1); dst++;\n\t\t\tnvg__vset(dst, p1->x, p1->y, 0.5f,1); dst++;\n\t\t}\n\n\t\tnvg__vset(dst, p1->x + dlx1*rw, p1->y + dly1*rw, lu,1); dst++;\n\t\tnvg__vset(dst, rx1, ry1, ru,1); dst++;\n\n\t}\n\treturn dst;\n}\n\nstatic NVGvertex* nvg__bevelJoin(NVGvertex* dst, NVGpoint* p0, NVGpoint* p1,\n\t\t\t\t\t\t\t\t\t\tfloat lw, float rw, float lu, float ru, float fringe)\n{\n\tfloat rx0,ry0,rx1,ry1;\n\tfloat lx0,ly0,lx1,ly1;\n\tfloat dlx0 = p0->dy;\n\tfloat dly0 = -p0->dx;\n\tfloat dlx1 = p1->dy;\n\tfloat dly1 = -p1->dx;\n\tNVG_NOTUSED(fringe);\n\n\tif (p1->flags & NVG_PT_LEFT) {\n\t\tnvg__chooseBevel(p1->flags & NVG_PR_INNERBEVEL, p0, p1, lw, &lx0,&ly0, &lx1,&ly1);\n\n\t\tnvg__vset(dst, lx0, ly0, lu,1); dst++;\n\t\tnvg__vset(dst, p1->x - dlx0*rw, p1->y - dly0*rw, ru,1); dst++;\n\n\t\tif (p1->flags & NVG_PT_BEVEL) {\n\t\t\tnvg__vset(dst, lx0, ly0, lu,1); dst++;\n\t\t\tnvg__vset(dst, p1->x - dlx0*rw, p1->y - dly0*rw, ru,1); dst++;\n\n\t\t\tnvg__vset(dst, lx1, ly1, lu,1); dst++;\n\t\t\tnvg__vset(dst, p1->x - dlx1*rw, p1->y - dly1*rw, ru,1); dst++;\n\t\t} else {\n\t\t\trx0 = p1->x - p1->dmx * rw;\n\t\t\try0 = p1->y - p1->dmy * rw;\n\n\t\t\tnvg__vset(dst, p1->x, p1->y, 0.5f,1); dst++;\n\t\t\tnvg__vset(dst, p1->x - dlx0*rw, p1->y - dly0*rw, ru,1); dst++;\n\n\t\t\tnvg__vset(dst, rx0, ry0, ru,1); dst++;\n\t\t\tnvg__vset(dst, rx0, ry0, ru,1); dst++;\n\n\t\t\tnvg__vset(dst, p1->x, p1->y, 0.5f,1); dst++;\n\t\t\tnvg__vset(dst, p1->x - dlx1*rw, p1->y - dly1*rw, ru,1); dst++;\n\t\t}\n\n\t\tnvg__vset(dst, lx1, ly1, lu,1); dst++;\n\t\tnvg__vset(dst, p1->x - dlx1*rw, p1->y - dly1*rw, ru,1); dst++;\n\n\t} else {\n\t\tnvg__chooseBevel(p1->flags & NVG_PR_INNERBEVEL, p0, p1, -rw, &rx0,&ry0, &rx1,&ry1);\n\n\t\tnvg__vset(dst, p1->x + dlx0*lw, p1->y + dly0*lw, lu,1); dst++;\n\t\tnvg__vset(dst, rx0, ry0, ru,1); dst++;\n\n\t\tif (p1->flags & NVG_PT_BEVEL) {\n\t\t\tnvg__vset(dst, p1->x + dlx0*lw, p1->y + dly0*lw, lu,1); dst++;\n\t\t\tnvg__vset(dst, rx0, ry0, ru,1); dst++;\n\n\t\t\tnvg__vset(dst, p1->x + dlx1*lw, p1->y + dly1*lw, lu,1); dst++;\n\t\t\tnvg__vset(dst, rx1, ry1, ru,1); dst++;\n\t\t} else {\n\t\t\tlx0 = p1->x + p1->dmx * lw;\n\t\t\tly0 = p1->y + p1->dmy * lw;\n\n\t\t\tnvg__vset(dst, p1->x + dlx0*lw, p1->y + dly0*lw, lu,1); dst++;\n\t\t\tnvg__vset(dst, p1->x, p1->y, 0.5f,1); dst++;\n\n\t\t\tnvg__vset(dst, lx0, ly0, lu,1); dst++;\n\t\t\tnvg__vset(dst, lx0, ly0, lu,1); dst++;\n\n\t\t\tnvg__vset(dst, p1->x + dlx1*lw, p1->y + dly1*lw, lu,1); dst++;\n\t\t\tnvg__vset(dst, p1->x, p1->y, 0.5f,1); dst++;\n\t\t}\n\n\t\tnvg__vset(dst, p1->x + dlx1*lw, p1->y + dly1*lw, lu,1); dst++;\n\t\tnvg__vset(dst, rx1, ry1, ru,1); dst++;\n\t}\n\n\treturn dst;\n}\n\nstatic NVGvertex* nvg__buttCapStart(NVGvertex* dst, NVGpoint* p,\n\t\t\t\t\t\t\t\t\t\t   float dx, float dy, float w, float d, float aa)\n{\n\tfloat px = p->x - dx*d;\n\tfloat py = p->y - dy*d;\n\tfloat dlx = dy;\n\tfloat dly = -dx;\n\tnvg__vset(dst, px + dlx*w - dx*aa, py + dly*w - dy*aa, 0,0); dst++;\n\tnvg__vset(dst, px - dlx*w - dx*aa, py - dly*w - dy*aa, 1,0); dst++;\n\tnvg__vset(dst, px + dlx*w, py + dly*w, 0,1); dst++;\n\tnvg__vset(dst, px - dlx*w, py - dly*w, 1,1); dst++;\n\treturn dst;\n}\n\nstatic NVGvertex* nvg__buttCapEnd(NVGvertex* dst, NVGpoint* p,\n\t\t\t\t\t\t\t\t\t\t   float dx, float dy, float w, float d, float aa)\n{\n\tfloat px = p->x + dx*d;\n\tfloat py = p->y + dy*d;\n\tfloat dlx = dy;\n\tfloat dly = -dx;\n\tnvg__vset(dst, px + dlx*w, py + dly*w, 0,1); dst++;\n\tnvg__vset(dst, px - dlx*w, py - dly*w, 1,1); dst++;\n\tnvg__vset(dst, px + dlx*w + dx*aa, py + dly*w + dy*aa, 0,0); dst++;\n\tnvg__vset(dst, px - dlx*w + dx*aa, py - dly*w + dy*aa, 1,0); dst++;\n\treturn dst;\n}\n\n\nstatic NVGvertex* nvg__roundCapStart(NVGvertex* dst, NVGpoint* p,\n\t\t\t\t\t\t\t\t\t\t\tfloat dx, float dy, float w, int ncap, float aa)\n{\n\tint i;\n\tfloat px = p->x;\n\tfloat py = p->y;\n\tfloat dlx = dy;\n\tfloat dly = -dx;\n\tNVG_NOTUSED(aa);\n\tfor (i = 0; i < ncap; i++) {\n\t\tfloat a = i/(float)(ncap-1)*NVG_PI;\n\t\tfloat ax = cosf(a) * w, ay = sinf(a) * w;\n\t\tnvg__vset(dst, px - dlx*ax - dx*ay, py - dly*ax - dy*ay, 0,1); dst++;\n\t\tnvg__vset(dst, px, py, 0.5f,1); dst++;\n\t}\n\tnvg__vset(dst, px + dlx*w, py + dly*w, 0,1); dst++;\n\tnvg__vset(dst, px - dlx*w, py - dly*w, 1,1); dst++;\n\treturn dst;\n}\n\nstatic NVGvertex* nvg__roundCapEnd(NVGvertex* dst, NVGpoint* p,\n\t\t\t\t\t\t\t\t\t\t  float dx, float dy, float w, int ncap, float aa)\n{\n\tint i;\n\tfloat px = p->x;\n\tfloat py = p->y;\n\tfloat dlx = dy;\n\tfloat dly = -dx;\n\tNVG_NOTUSED(aa);\n\tnvg__vset(dst, px + dlx*w, py + dly*w, 0,1); dst++;\n\tnvg__vset(dst, px - dlx*w, py - dly*w, 1,1); dst++;\n\tfor (i = 0; i < ncap; i++) {\n\t\tfloat a = i/(float)(ncap-1)*NVG_PI;\n\t\tfloat ax = cosf(a) * w, ay = sinf(a) * w;\n\t\tnvg__vset(dst, px, py, 0.5f,1); dst++;\n\t\tnvg__vset(dst, px - dlx*ax + dx*ay, py - dly*ax + dy*ay, 0,1); dst++;\n\t}\n\treturn dst;\n}\n\n\nstatic void nvg__calculateJoins(NVGcontext* ctx, float w, int lineJoin, float miterLimit)\n{\n\tNVGpathCache* cache = ctx->cache;\n\tint i, j;\n\tfloat iw = 0.0f;\n\n\tif (w > 0.0f) iw = 1.0f / w;\n\n\t// Calculate which joins needs extra vertices to append, and gather vertex count.\n\tfor (i = 0; i < cache->npaths; i++) {\n\t\tNVGpath* path = &cache->paths[i];\n\t\tNVGpoint* pts = &cache->points[path->first];\n\t\tNVGpoint* p0 = &pts[path->count-1];\n\t\tNVGpoint* p1 = &pts[0];\n\t\tint nleft = 0;\n\n\t\tpath->nbevel = 0;\n\n\t\tfor (j = 0; j < path->count; j++) {\n\t\t\tfloat dlx0, dly0, dlx1, dly1, dmr2, cross, limit;\n\t\t\tdlx0 = p0->dy;\n\t\t\tdly0 = -p0->dx;\n\t\t\tdlx1 = p1->dy;\n\t\t\tdly1 = -p1->dx;\n\t\t\t// Calculate extrusions\n\t\t\tp1->dmx = (dlx0 + dlx1) * 0.5f;\n\t\t\tp1->dmy = (dly0 + dly1) * 0.5f;\n\t\t\tdmr2 = p1->dmx*p1->dmx + p1->dmy*p1->dmy;\n\t\t\tif (dmr2 > 0.000001f) {\n\t\t\t\tfloat scale = 1.0f / dmr2;\n\t\t\t\tif (scale > 600.0f) {\n\t\t\t\t\tscale = 600.0f;\n\t\t\t\t}\n\t\t\t\tp1->dmx *= scale;\n\t\t\t\tp1->dmy *= scale;\n\t\t\t}\n\n\t\t\t// Clear flags, but keep the corner.\n\t\t\tp1->flags = (p1->flags & NVG_PT_CORNER) ? NVG_PT_CORNER : 0;\n\n\t\t\t// Keep track of left turns.\n\t\t\tcross = p1->dx * p0->dy - p0->dx * p1->dy;\n\t\t\tif (cross > 0.0f) {\n\t\t\t\tnleft++;\n\t\t\t\tp1->flags |= NVG_PT_LEFT;\n\t\t\t}\n\n\t\t\t// Calculate if we should use bevel or miter for inner join.\n\t\t\tlimit = nvg__maxf(1.01f, nvg__minf(p0->len, p1->len) * iw);\n\t\t\tif ((dmr2 * limit*limit) < 1.0f)\n\t\t\t\tp1->flags |= NVG_PR_INNERBEVEL;\n\n\t\t\t// Check to see if the corner needs to be beveled.\n\t\t\tif (p1->flags & NVG_PT_CORNER) {\n\t\t\t\tif ((dmr2 * miterLimit*miterLimit) < 1.0f || lineJoin == NVG_BEVEL || lineJoin == NVG_ROUND) {\n\t\t\t\t\tp1->flags |= NVG_PT_BEVEL;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif ((p1->flags & (NVG_PT_BEVEL | NVG_PR_INNERBEVEL)) != 0)\n\t\t\t\tpath->nbevel++;\n\n\t\t\tp0 = p1++;\n\t\t}\n\n\t\tpath->convex = (nleft == path->count) ? 1 : 0;\n\t}\n}\n\n\nstatic int nvg__expandStroke(NVGcontext* ctx, float w, int lineCap, int lineJoin, float miterLimit)\n{\n\tNVGpathCache* cache = ctx->cache;\n\tNVGvertex* verts;\n\tNVGvertex* dst;\n\tint cverts, i, j;\n\tfloat aa = ctx->fringeWidth;\n\tint ncap = nvg__curveDivs(w, NVG_PI, ctx->tessTol);\t// Calculate divisions per half circle.\n\n\tnvg__calculateJoins(ctx, w, lineJoin, miterLimit);\n\n\t// Calculate max vertex usage.\n\tcverts = 0;\n\tfor (i = 0; i < cache->npaths; i++) {\n\t\tNVGpath* path = &cache->paths[i];\n\t\tint loop = (path->closed == 0) ? 0 : 1;\n\t\tif (lineJoin == NVG_ROUND)\n\t\t\tcverts += (path->count + path->nbevel*(ncap+2) + 1) * 2; // plus one for loop\n\t\telse\n\t\t\tcverts += (path->count + path->nbevel*5 + 1) * 2; // plus one for loop\n\t\tif (loop == 0) {\n\t\t\t// space for caps\n\t\t\tif (lineCap == NVG_ROUND) {\n\t\t\t\tcverts += (ncap*2 + 2)*2;\n\t\t\t} else {\n\t\t\t\tcverts += (3+3)*2;\n\t\t\t}\n\t\t}\n\t}\n\n\tverts = nvg__allocTempVerts(ctx, cverts);\n\tif (verts == NULL) return 0;\n\n\tfor (i = 0; i < cache->npaths; i++) {\n\t\tNVGpath* path = &cache->paths[i];\n\t\tNVGpoint* pts = &cache->points[path->first];\n\t\tNVGpoint* p0;\n\t\tNVGpoint* p1;\n\t\tint s, e, loop;\n\t\tfloat dx, dy;\n\n\t\tpath->fill = 0;\n\t\tpath->nfill = 0;\n\n\t\t// Calculate fringe or stroke\n\t\tloop = (path->closed == 0) ? 0 : 1;\n\t\tdst = verts;\n\t\tpath->stroke = dst;\n\n\t\tif (loop) {\n\t\t\t// Looping\n\t\t\tp0 = &pts[path->count-1];\n\t\t\tp1 = &pts[0];\n\t\t\ts = 0;\n\t\t\te = path->count;\n\t\t} else {\n\t\t\t// Add cap\n\t\t\tp0 = &pts[0];\n\t\t\tp1 = &pts[1];\n\t\t\ts = 1;\n\t\t\te = path->count-1;\n\t\t}\n\n\t\tif (loop == 0) {\n\t\t\t// Add cap\n\t\t\tdx = p1->x - p0->x;\n\t\t\tdy = p1->y - p0->y;\n\t\t\tnvg__normalize(&dx, &dy);\n\t\t\tif (lineCap == NVG_BUTT)\n\t\t\t\tdst = nvg__buttCapStart(dst, p0, dx, dy, w, -aa*0.5f, aa);\n\t\t\telse if (lineCap == NVG_BUTT || lineCap == NVG_SQUARE)\n\t\t\t\tdst = nvg__buttCapStart(dst, p0, dx, dy, w, w-aa, aa);\n\t\t\telse if (lineCap == NVG_ROUND)\n\t\t\t\tdst = nvg__roundCapStart(dst, p0, dx, dy, w, ncap, aa);\n\t\t}\n\n\t\tfor (j = s; j < e; ++j) {\n\t\t\tif ((p1->flags & (NVG_PT_BEVEL | NVG_PR_INNERBEVEL)) != 0) {\n\t\t\t\tif (lineJoin == NVG_ROUND) {\n\t\t\t\t\tdst = nvg__roundJoin(dst, p0, p1, w, w, 0, 1, ncap, aa);\n\t\t\t\t} else {\n\t\t\t\t\tdst = nvg__bevelJoin(dst, p0, p1, w, w, 0, 1, aa);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tnvg__vset(dst, p1->x + (p1->dmx * w), p1->y + (p1->dmy * w), 0,1); dst++;\n\t\t\t\tnvg__vset(dst, p1->x - (p1->dmx * w), p1->y - (p1->dmy * w), 1,1); dst++;\n\t\t\t}\n\t\t\tp0 = p1++;\n\t\t}\n\n\t\tif (loop) {\n\t\t\t// Loop it\n\t\t\tnvg__vset(dst, verts[0].x, verts[0].y, 0,1); dst++;\n\t\t\tnvg__vset(dst, verts[1].x, verts[1].y, 1,1); dst++;\n\t\t} else {\n\t\t\t// Add cap\n\t\t\tdx = p1->x - p0->x;\n\t\t\tdy = p1->y - p0->y;\n\t\t\tnvg__normalize(&dx, &dy);\n\t\t\tif (lineCap == NVG_BUTT)\n\t\t\t\tdst = nvg__buttCapEnd(dst, p1, dx, dy, w, -aa*0.5f, aa);\n\t\t\telse if (lineCap == NVG_BUTT || lineCap == NVG_SQUARE)\n\t\t\t\tdst = nvg__buttCapEnd(dst, p1, dx, dy, w, w-aa, aa);\n\t\t\telse if (lineCap == NVG_ROUND)\n\t\t\t\tdst = nvg__roundCapEnd(dst, p1, dx, dy, w, ncap, aa);\n\t\t}\n\n\t\tpath->nstroke = (int)(dst - verts);\n\n\t\tverts = dst;\n\t}\n\n\treturn 1;\n}\n\nstatic int nvg__expandFill(NVGcontext* ctx, float w, int lineJoin, float miterLimit)\n{\n\tNVGpathCache* cache = ctx->cache;\n\tNVGvertex* verts;\n\tNVGvertex* dst;\n\tint cverts, convex, i, j;\n\tfloat aa = ctx->fringeWidth;\n\tint fringe = w > 0.0f;\n\n\tnvg__calculateJoins(ctx, w, lineJoin, miterLimit);\n\n\t// Calculate max vertex usage.\n\tcverts = 0;\n\tfor (i = 0; i < cache->npaths; i++) {\n\t\tNVGpath* path = &cache->paths[i];\n\t\tcverts += path->count + path->nbevel + 1;\n\t\tif (fringe)\n\t\t\tcverts += (path->count + path->nbevel*5 + 1) * 2; // plus one for loop\n\t}\n\n\tverts = nvg__allocTempVerts(ctx, cverts);\n\tif (verts == NULL) return 0;\n\n\tconvex = cache->npaths == 1 && cache->paths[0].convex;\n\n\tfor (i = 0; i < cache->npaths; i++) {\n\t\tNVGpath* path = &cache->paths[i];\n\t\tNVGpoint* pts = &cache->points[path->first];\n\t\tNVGpoint* p0;\n\t\tNVGpoint* p1;\n\t\tfloat rw, lw, woff;\n\t\tfloat ru, lu;\n\n\t\t// Calculate shape vertices.\n\t\twoff = 0.5f*aa;\n\t\tdst = verts;\n\t\tpath->fill = dst;\n\n\t\tif (fringe) {\n\t\t\t// Looping\n\t\t\tp0 = &pts[path->count-1];\n\t\t\tp1 = &pts[0];\n\t\t\tfor (j = 0; j < path->count; ++j) {\n\t\t\t\tif (p1->flags & NVG_PT_BEVEL) {\n\t\t\t\t\tfloat dlx0 = p0->dy;\n\t\t\t\t\tfloat dly0 = -p0->dx;\n\t\t\t\t\tfloat dlx1 = p1->dy;\n\t\t\t\t\tfloat dly1 = -p1->dx;\n\t\t\t\t\tif (p1->flags & NVG_PT_LEFT) {\n\t\t\t\t\t\tfloat lx = p1->x + p1->dmx * woff;\n\t\t\t\t\t\tfloat ly = p1->y + p1->dmy * woff;\n\t\t\t\t\t\tnvg__vset(dst, lx, ly, 0.5f,1); dst++;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tfloat lx0 = p1->x + dlx0 * woff;\n\t\t\t\t\t\tfloat ly0 = p1->y + dly0 * woff;\n\t\t\t\t\t\tfloat lx1 = p1->x + dlx1 * woff;\n\t\t\t\t\t\tfloat ly1 = p1->y + dly1 * woff;\n\t\t\t\t\t\tnvg__vset(dst, lx0, ly0, 0.5f,1); dst++;\n\t\t\t\t\t\tnvg__vset(dst, lx1, ly1, 0.5f,1); dst++;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tnvg__vset(dst, p1->x + (p1->dmx * woff), p1->y + (p1->dmy * woff), 0.5f,1); dst++;\n\t\t\t\t}\n\t\t\t\tp0 = p1++;\n\t\t\t}\n\t\t} else {\n\t\t\tfor (j = 0; j < path->count; ++j) {\n\t\t\t\tnvg__vset(dst, pts[j].x, pts[j].y, 0.5f,1);\n\t\t\t\tdst++;\n\t\t\t}\n\t\t}\n\n\t\tpath->nfill = (int)(dst - verts);\n\t\tverts = dst;\n\n\t\t// Calculate fringe\n\t\tif (fringe) {\n\t\t\tlw = w + woff;\n\t\t\trw = w - woff;\n\t\t\tlu = 0;\n\t\t\tru = 1;\n\t\t\tdst = verts;\n\t\t\tpath->stroke = dst;\n\n\t\t\t// Create only half a fringe for convex shapes so that\n\t\t\t// the shape can be rendered without stenciling.\n\t\t\tif (convex) {\n\t\t\t\tlw = woff;\t// This should generate the same vertex as fill inset above.\n\t\t\t\tlu = 0.5f;\t// Set outline fade at middle.\n\t\t\t}\n\n\t\t\t// Looping\n\t\t\tp0 = &pts[path->count-1];\n\t\t\tp1 = &pts[0];\n\n\t\t\tfor (j = 0; j < path->count; ++j) {\n\t\t\t\tif ((p1->flags & (NVG_PT_BEVEL | NVG_PR_INNERBEVEL)) != 0) {\n\t\t\t\t\tdst = nvg__bevelJoin(dst, p0, p1, lw, rw, lu, ru, ctx->fringeWidth);\n\t\t\t\t} else {\n\t\t\t\t\tnvg__vset(dst, p1->x + (p1->dmx * lw), p1->y + (p1->dmy * lw), lu,1); dst++;\n\t\t\t\t\tnvg__vset(dst, p1->x - (p1->dmx * rw), p1->y - (p1->dmy * rw), ru,1); dst++;\n\t\t\t\t}\n\t\t\t\tp0 = p1++;\n\t\t\t}\n\n\t\t\t// Loop it\n\t\t\tnvg__vset(dst, verts[0].x, verts[0].y, lu,1); dst++;\n\t\t\tnvg__vset(dst, verts[1].x, verts[1].y, ru,1); dst++;\n\n\t\t\tpath->nstroke = (int)(dst - verts);\n\t\t\tverts = dst;\n\t\t} else {\n\t\t\tpath->stroke = NULL;\n\t\t\tpath->nstroke = 0;\n\t\t}\n\t}\n\n\treturn 1;\n}\n\n\n// Draw\nvoid nvgBeginPath(NVGcontext* ctx)\n{\n\tctx->ncommands = 0;\n\tnvg__clearPathCache(ctx);\n}\n\nvoid nvgMoveTo(NVGcontext* ctx, float x, float y)\n{\n\tfloat vals[] = { NVG_MOVETO, x, y };\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgLineTo(NVGcontext* ctx, float x, float y)\n{\n\tfloat vals[] = { NVG_LINETO, x, y };\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgBezierTo(NVGcontext* ctx, float c1x, float c1y, float c2x, float c2y, float x, float y)\n{\n\tfloat vals[] = { NVG_BEZIERTO, c1x, c1y, c2x, c2y, x, y };\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgQuadTo(NVGcontext* ctx, float cx, float cy, float x, float y)\n{\n    float x0 = ctx->commandx;\n    float y0 = ctx->commandy;\n    float vals[] = { NVG_BEZIERTO,\n        x0 + 2.0f/3.0f*(cx - x0), y0 + 2.0f/3.0f*(cy - y0),\n        x + 2.0f/3.0f*(cx - x), y + 2.0f/3.0f*(cy - y),\n        x, y };\n    nvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgArcTo(NVGcontext* ctx, float x1, float y1, float x2, float y2, float radius)\n{\n\tfloat x0 = ctx->commandx;\n\tfloat y0 = ctx->commandy;\n\tfloat dx0,dy0, dx1,dy1, a, d, cx,cy, a0,a1;\n\tint dir;\n\n\tif (ctx->ncommands == 0) {\n\t\treturn;\n\t}\n\n\t// Handle degenerate cases.\n\tif (nvg__ptEquals(x0,y0, x1,y1, ctx->distTol) ||\n\t\tnvg__ptEquals(x1,y1, x2,y2, ctx->distTol) ||\n\t\tnvg__distPtSeg(x1,y1, x0,y0, x2,y2) < ctx->distTol*ctx->distTol ||\n\t\tradius < ctx->distTol) {\n\t\tnvgLineTo(ctx, x1,y1);\n\t\treturn;\n\t}\n\n\t// Calculate tangential circle to lines (x0,y0)-(x1,y1) and (x1,y1)-(x2,y2).\n\tdx0 = x0-x1;\n\tdy0 = y0-y1;\n\tdx1 = x2-x1;\n\tdy1 = y2-y1;\n\tnvg__normalize(&dx0,&dy0);\n\tnvg__normalize(&dx1,&dy1);\n\ta = nvg__acosf(dx0*dx1 + dy0*dy1);\n\td = radius / nvg__tanf(a/2.0f);\n\n//\tprintf(\"a=%f° d=%f\\n\", a/NVG_PI*180.0f, d);\n\n\tif (d > 10000.0f) {\n\t\tnvgLineTo(ctx, x1,y1);\n\t\treturn;\n\t}\n\n\tif (nvg__cross(dx0,dy0, dx1,dy1) > 0.0f) {\n\t\tcx = x1 + dx0*d + dy0*radius;\n\t\tcy = y1 + dy0*d + -dx0*radius;\n\t\ta0 = nvg__atan2f(dx0, -dy0);\n\t\ta1 = nvg__atan2f(-dx1, dy1);\n\t\tdir = NVG_CW;\n//\t\tprintf(\"CW c=(%f, %f) a0=%f° a1=%f°\\n\", cx, cy, a0/NVG_PI*180.0f, a1/NVG_PI*180.0f);\n\t} else {\n\t\tcx = x1 + dx0*d + -dy0*radius;\n\t\tcy = y1 + dy0*d + dx0*radius;\n\t\ta0 = nvg__atan2f(-dx0, dy0);\n\t\ta1 = nvg__atan2f(dx1, -dy1);\n\t\tdir = NVG_CCW;\n//\t\tprintf(\"CCW c=(%f, %f) a0=%f° a1=%f°\\n\", cx, cy, a0/NVG_PI*180.0f, a1/NVG_PI*180.0f);\n\t}\n\n\tnvgArc(ctx, cx, cy, radius, a0, a1, dir);\n}\n\nvoid nvgClosePath(NVGcontext* ctx)\n{\n\tfloat vals[] = { NVG_CLOSE };\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgPathWinding(NVGcontext* ctx, int dir)\n{\n\tfloat vals[] = { NVG_WINDING, (float)dir };\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgArc(NVGcontext* ctx, float cx, float cy, float r, float a0, float a1, int dir)\n{\n\tfloat a = 0, da = 0, hda = 0, kappa = 0;\n\tfloat dx = 0, dy = 0, x = 0, y = 0, tanx = 0, tany = 0;\n\tfloat px = 0, py = 0, ptanx = 0, ptany = 0;\n\tfloat vals[3 + 5*7 + 100];\n\tint i, ndivs, nvals;\n\tint move = ctx->ncommands > 0 ? NVG_LINETO : NVG_MOVETO;\n\n\t// Clamp angles\n\tda = a1 - a0;\n\tif (dir == NVG_CW) {\n\t\tif (nvg__absf(da) >= NVG_PI*2) {\n\t\t\tda = NVG_PI*2;\n\t\t} else {\n\t\t\twhile (da < 0.0f) da += NVG_PI*2;\n\t\t}\n\t} else {\n\t\tif (nvg__absf(da) >= NVG_PI*2) {\n\t\t\tda = -NVG_PI*2;\n\t\t} else {\n\t\t\twhile (da > 0.0f) da -= NVG_PI*2;\n\t\t}\n\t}\n\n\t// Split arc into max 90 degree segments.\n\tndivs = nvg__maxi(1, nvg__mini((int)(nvg__absf(da) / (NVG_PI*0.5f) + 0.5f), 5));\n\thda = (da / (float)ndivs) / 2.0f;\n\tkappa = nvg__absf(4.0f / 3.0f * (1.0f - nvg__cosf(hda)) / nvg__sinf(hda));\n\n\tif (dir == NVG_CCW)\n\t\tkappa = -kappa;\n\n\tnvals = 0;\n\tfor (i = 0; i <= ndivs; i++) {\n\t\ta = a0 + da * (i/(float)ndivs);\n\t\tdx = nvg__cosf(a);\n\t\tdy = nvg__sinf(a);\n\t\tx = cx + dx*r;\n\t\ty = cy + dy*r;\n\t\ttanx = -dy*r*kappa;\n\t\ttany = dx*r*kappa;\n\n\t\tif (i == 0) {\n\t\t\tvals[nvals++] = (float)move;\n\t\t\tvals[nvals++] = x;\n\t\t\tvals[nvals++] = y;\n\t\t} else {\n\t\t\tvals[nvals++] = NVG_BEZIERTO;\n\t\t\tvals[nvals++] = px+ptanx;\n\t\t\tvals[nvals++] = py+ptany;\n\t\t\tvals[nvals++] = x-tanx;\n\t\t\tvals[nvals++] = y-tany;\n\t\t\tvals[nvals++] = x;\n\t\t\tvals[nvals++] = y;\n\t\t}\n\t\tpx = x;\n\t\tpy = y;\n\t\tptanx = tanx;\n\t\tptany = tany;\n\t}\n\n\tnvg__appendCommands(ctx, vals, nvals);\n}\n\nvoid nvgRect(NVGcontext* ctx, float x, float y, float w, float h)\n{\n\tfloat vals[] = {\n\t\tNVG_MOVETO, x,y,\n\t\tNVG_LINETO, x,y+h,\n\t\tNVG_LINETO, x+w,y+h,\n\t\tNVG_LINETO, x+w,y,\n\t\tNVG_CLOSE\n\t};\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgRoundedRect(NVGcontext* ctx, float x, float y, float w, float h, float r)\n{\n\tnvgRoundedRectVarying(ctx, x, y, w, h, r, r, r, r);\n}\n\nvoid nvgRoundedRectVarying(NVGcontext* ctx, float x, float y, float w, float h, float radTopLeft, float radTopRight, float radBottomRight, float radBottomLeft)\n{\n\tif(radTopLeft < 0.1f && radTopRight < 0.1f && radBottomRight < 0.1f && radBottomLeft < 0.1f) {\n\t\tnvgRect(ctx, x, y, w, h);\n\t\treturn;\n\t} else {\n\t\tfloat halfw = nvg__absf(w)*0.5f;\n\t\tfloat halfh = nvg__absf(h)*0.5f;\n\t\tfloat rxBL = nvg__minf(radBottomLeft, halfw) * nvg__signf(w), ryBL = nvg__minf(radBottomLeft, halfh) * nvg__signf(h);\n\t\tfloat rxBR = nvg__minf(radBottomRight, halfw) * nvg__signf(w), ryBR = nvg__minf(radBottomRight, halfh) * nvg__signf(h);\n\t\tfloat rxTR = nvg__minf(radTopRight, halfw) * nvg__signf(w), ryTR = nvg__minf(radTopRight, halfh) * nvg__signf(h);\n\t\tfloat rxTL = nvg__minf(radTopLeft, halfw) * nvg__signf(w), ryTL = nvg__minf(radTopLeft, halfh) * nvg__signf(h);\n\t\tfloat vals[] = {\n\t\t\tNVG_MOVETO, x, y + ryTL,\n\t\t\tNVG_LINETO, x, y + h - ryBL,\n\t\t\tNVG_BEZIERTO, x, y + h - ryBL*(1 - NVG_KAPPA90), x + rxBL*(1 - NVG_KAPPA90), y + h, x + rxBL, y + h,\n\t\t\tNVG_LINETO, x + w - rxBR, y + h,\n\t\t\tNVG_BEZIERTO, x + w - rxBR*(1 - NVG_KAPPA90), y + h, x + w, y + h - ryBR*(1 - NVG_KAPPA90), x + w, y + h - ryBR,\n\t\t\tNVG_LINETO, x + w, y + ryTR,\n\t\t\tNVG_BEZIERTO, x + w, y + ryTR*(1 - NVG_KAPPA90), x + w - rxTR*(1 - NVG_KAPPA90), y, x + w - rxTR, y,\n\t\t\tNVG_LINETO, x + rxTL, y,\n\t\t\tNVG_BEZIERTO, x + rxTL*(1 - NVG_KAPPA90), y, x, y + ryTL*(1 - NVG_KAPPA90), x, y + ryTL,\n\t\t\tNVG_CLOSE\n\t\t};\n\t\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n\t}\n}\n\nvoid nvgEllipse(NVGcontext* ctx, float cx, float cy, float rx, float ry)\n{\n\tfloat vals[] = {\n\t\tNVG_MOVETO, cx-rx, cy,\n\t\tNVG_BEZIERTO, cx-rx, cy+ry*NVG_KAPPA90, cx-rx*NVG_KAPPA90, cy+ry, cx, cy+ry,\n\t\tNVG_BEZIERTO, cx+rx*NVG_KAPPA90, cy+ry, cx+rx, cy+ry*NVG_KAPPA90, cx+rx, cy,\n\t\tNVG_BEZIERTO, cx+rx, cy-ry*NVG_KAPPA90, cx+rx*NVG_KAPPA90, cy-ry, cx, cy-ry,\n\t\tNVG_BEZIERTO, cx-rx*NVG_KAPPA90, cy-ry, cx-rx, cy-ry*NVG_KAPPA90, cx-rx, cy,\n\t\tNVG_CLOSE\n\t};\n\tnvg__appendCommands(ctx, vals, NVG_COUNTOF(vals));\n}\n\nvoid nvgCircle(NVGcontext* ctx, float cx, float cy, float r)\n{\n\tnvgEllipse(ctx, cx,cy, r,r);\n}\n\nvoid nvgDebugDumpPathCache(NVGcontext* ctx)\n{\n\tconst NVGpath* path;\n\tint i, j;\n\n\tprintf(\"Dumping %d cached paths\\n\", ctx->cache->npaths);\n\tfor (i = 0; i < ctx->cache->npaths; i++) {\n\t\tpath = &ctx->cache->paths[i];\n\t\tprintf(\" - Path %d\\n\", i);\n\t\tif (path->nfill) {\n\t\t\tprintf(\"   - fill: %d\\n\", path->nfill);\n\t\t\tfor (j = 0; j < path->nfill; j++)\n\t\t\t\tprintf(\"%f\\t%f\\n\", path->fill[j].x, path->fill[j].y);\n\t\t}\n\t\tif (path->nstroke) {\n\t\t\tprintf(\"   - stroke: %d\\n\", path->nstroke);\n\t\t\tfor (j = 0; j < path->nstroke; j++)\n\t\t\t\tprintf(\"%f\\t%f\\n\", path->stroke[j].x, path->stroke[j].y);\n\t\t}\n\t}\n}\n\nvoid nvgFill(NVGcontext* ctx)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tconst NVGpath* path;\n\tNVGpaint fillPaint = state->fill;\n\tint i;\n\n\tnvg__flattenPaths(ctx);\n\tif (ctx->params.edgeAntiAlias)\n\t\tnvg__expandFill(ctx, ctx->fringeWidth, NVG_MITER, 2.4f);\n\telse\n\t\tnvg__expandFill(ctx, 0.0f, NVG_MITER, 2.4f);\n\n\t// Apply global alpha\n\tfillPaint.innerColor.a *= state->alpha;\n\tfillPaint.outerColor.a *= state->alpha;\n\n\tctx->params.renderFill(ctx->params.userPtr, &fillPaint, &state->scissor, ctx->fringeWidth,\n\t\t\t\t\t\t   ctx->cache->bounds, ctx->cache->paths, ctx->cache->npaths);\n\n\t// Count triangles\n\tfor (i = 0; i < ctx->cache->npaths; i++) {\n\t\tpath = &ctx->cache->paths[i];\n\t\tctx->fillTriCount += path->nfill-2;\n\t\tctx->fillTriCount += path->nstroke-2;\n\t\tctx->drawCallCount += 2;\n\t}\n}\n\nvoid nvgStroke(NVGcontext* ctx)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat scale = nvg__getAverageScale(state->xform);\n\tfloat strokeWidth = nvg__clampf(state->strokeWidth * scale, 0.0f, 200.0f);\n\tNVGpaint strokePaint = state->stroke;\n\tconst NVGpath* path;\n\tint i;\n\n\tif (strokeWidth < ctx->fringeWidth) {\n\t\t// If the stroke width is less than pixel size, use alpha to emulate coverage.\n\t\t// Since coverage is area, scale by alpha*alpha.\n\t\tfloat alpha = nvg__clampf(strokeWidth / ctx->fringeWidth, 0.0f, 1.0f);\n\t\tstrokePaint.innerColor.a *= alpha*alpha;\n\t\tstrokePaint.outerColor.a *= alpha*alpha;\n\t\tstrokeWidth = ctx->fringeWidth;\n\t}\n\n\t// Apply global alpha\n\tstrokePaint.innerColor.a *= state->alpha;\n\tstrokePaint.outerColor.a *= state->alpha;\n\n\tnvg__flattenPaths(ctx);\n\n\tif (ctx->params.edgeAntiAlias)\n\t\tnvg__expandStroke(ctx, strokeWidth*0.5f + ctx->fringeWidth*0.5f, state->lineCap, state->lineJoin, state->miterLimit);\n\telse\n\t\tnvg__expandStroke(ctx, strokeWidth*0.5f, state->lineCap, state->lineJoin, state->miterLimit);\n\n\tctx->params.renderStroke(ctx->params.userPtr, &strokePaint, &state->scissor, ctx->fringeWidth,\n\t\t\t\t\t\t\t strokeWidth, ctx->cache->paths, ctx->cache->npaths);\n\n\t// Count triangles\n\tfor (i = 0; i < ctx->cache->npaths; i++) {\n\t\tpath = &ctx->cache->paths[i];\n\t\tctx->strokeTriCount += path->nstroke-2;\n\t\tctx->drawCallCount++;\n\t}\n}\n\n// Add fonts\nint nvgCreateFont(NVGcontext* ctx, const char* name, const char* path)\n{\n\treturn fonsAddFont(ctx->fs, name, path);\n}\n\nint nvgCreateFontMem(NVGcontext* ctx, const char* name, unsigned char* data, int ndata, int freeData)\n{\n\treturn fonsAddFontMem(ctx->fs, name, data, ndata, freeData);\n}\n\nint nvgFindFont(NVGcontext* ctx, const char* name)\n{\n\tif (name == NULL) return -1;\n\treturn fonsGetFontByName(ctx->fs, name);\n}\n\n\nint nvgAddFallbackFontId(NVGcontext* ctx, int baseFont, int fallbackFont)\n{\n\tif(baseFont == -1 || fallbackFont == -1) return 0;\n\treturn fonsAddFallbackFont(ctx->fs, baseFont, fallbackFont);\n}\n\nint nvgAddFallbackFont(NVGcontext* ctx, const char* baseFont, const char* fallbackFont)\n{\n\treturn nvgAddFallbackFontId(ctx, nvgFindFont(ctx, baseFont), nvgFindFont(ctx, fallbackFont));\n}\n\n// State setting\nvoid nvgFontSize(NVGcontext* ctx, float size)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->fontSize = size;\n}\n\nvoid nvgFontBlur(NVGcontext* ctx, float blur)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->fontBlur = blur;\n}\n\nvoid nvgTextLetterSpacing(NVGcontext* ctx, float spacing)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->letterSpacing = spacing;\n}\n\nvoid nvgTextLineHeight(NVGcontext* ctx, float lineHeight)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->lineHeight = lineHeight;\n}\n\nvoid nvgTextAlign(NVGcontext* ctx, int align)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->textAlign = align;\n}\n\nvoid nvgFontFaceId(NVGcontext* ctx, int font)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->fontId = font;\n}\n\nvoid nvgFontFace(NVGcontext* ctx, const char* font)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tstate->fontId = fonsGetFontByName(ctx->fs, font);\n}\n\nstatic float nvg__quantize(float a, float d)\n{\n\treturn ((int)(a / d + 0.5f)) * d;\n}\n\nstatic float nvg__getFontScale(NVGstate* state)\n{\n\treturn nvg__minf(nvg__quantize(nvg__getAverageScale(state->xform), 0.01f), 4.0f);\n}\n\nstatic void nvg__flushTextTexture(NVGcontext* ctx)\n{\n\tint dirty[4];\n\n\tif (fonsValidateTexture(ctx->fs, dirty)) {\n\t\tint fontImage = ctx->fontImages[ctx->fontImageIdx];\n\t\t// Update texture\n\t\tif (fontImage != 0) {\n\t\t\tint iw, ih;\n\t\t\tconst unsigned char* data = fonsGetTextureData(ctx->fs, &iw, &ih);\n\t\t\tint x = dirty[0];\n\t\t\tint y = dirty[1];\n\t\t\tint w = dirty[2] - dirty[0];\n\t\t\tint h = dirty[3] - dirty[1];\n\t\t\tctx->params.renderUpdateTexture(ctx->params.userPtr, fontImage, x,y, w,h, data);\n\t\t}\n\t}\n}\n\nstatic int nvg__allocTextAtlas(NVGcontext* ctx)\n{\n\tint iw, ih;\n\tnvg__flushTextTexture(ctx);\n\tif (ctx->fontImageIdx >= NVG_MAX_FONTIMAGES-1)\n\t\treturn 0;\n\t// if next fontImage already have a texture\n\tif (ctx->fontImages[ctx->fontImageIdx+1] != 0)\n\t\tnvgImageSize(ctx, ctx->fontImages[ctx->fontImageIdx+1], &iw, &ih);\n\telse { // calculate the new font image size and create it.\n\t\tnvgImageSize(ctx, ctx->fontImages[ctx->fontImageIdx], &iw, &ih);\n\t\tif (iw > ih)\n\t\t\tih *= 2;\n\t\telse\n\t\t\tiw *= 2;\n\t\tif (iw > NVG_MAX_FONTIMAGE_SIZE || ih > NVG_MAX_FONTIMAGE_SIZE)\n\t\t\tiw = ih = NVG_MAX_FONTIMAGE_SIZE;\n\t\tctx->fontImages[ctx->fontImageIdx+1] = ctx->params.renderCreateTexture(ctx->params.userPtr, NVG_TEXTURE_ALPHA, iw, ih, 0, NULL);\n\t}\n\t++ctx->fontImageIdx;\n\tfonsResetAtlas(ctx->fs, iw, ih);\n\treturn 1;\n}\n\nstatic void nvg__renderText(NVGcontext* ctx, NVGvertex* verts, int nverts)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tNVGpaint paint = state->fill;\n\n\t// Render triangles.\n\tpaint.image = ctx->fontImages[ctx->fontImageIdx];\n\n\t// Apply global alpha\n\tpaint.innerColor.a *= state->alpha;\n\tpaint.outerColor.a *= state->alpha;\n\n\tctx->params.renderTriangles(ctx->params.userPtr, &paint, &state->scissor, verts, nverts);\n\n\tctx->drawCallCount++;\n\tctx->textTriCount += nverts/3;\n}\n\nfloat nvgText(NVGcontext* ctx, float x, float y, const char* string, const char* end)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tFONStextIter iter, prevIter;\n\tFONSquad q;\n\tNVGvertex* verts;\n\tfloat scale = nvg__getFontScale(state) * ctx->devicePxRatio;\n\tfloat invscale = 1.0f / scale;\n\tint cverts = 0;\n\tint nverts = 0;\n\n\tif (end == NULL)\n\t\tend = string + strlen(string);\n\n\tif (state->fontId == FONS_INVALID) return x;\n\n\tfonsSetSize(ctx->fs, state->fontSize*scale);\n\tfonsSetSpacing(ctx->fs, state->letterSpacing*scale);\n\tfonsSetBlur(ctx->fs, state->fontBlur*scale);\n\tfonsSetAlign(ctx->fs, state->textAlign);\n\tfonsSetFont(ctx->fs, state->fontId);\n\n\tcverts = nvg__maxi(2, (int)(end - string)) * 6; // conservative estimate.\n\tverts = nvg__allocTempVerts(ctx, cverts);\n\tif (verts == NULL) return x;\n\n\tfonsTextIterInit(ctx->fs, &iter, x*scale, y*scale, string, end);\n\tprevIter = iter;\n\twhile (fonsTextIterNext(ctx->fs, &iter, &q)) {\n\t\tfloat c[4*2];\n\t\tif (iter.prevGlyphIndex == -1) { // can not retrieve glyph?\n\t\t\tif (!nvg__allocTextAtlas(ctx))\n\t\t\t\tbreak; // no memory :(\n\t\t\tif (nverts != 0) {\n\t\t\t\tnvg__renderText(ctx, verts, nverts);\n\t\t\t\tnverts = 0;\n\t\t\t}\n\t\t\titer = prevIter;\n\t\t\tfonsTextIterNext(ctx->fs, &iter, &q); // try again\n\t\t\tif (iter.prevGlyphIndex == -1) // still can not find glyph?\n\t\t\t\tbreak;\n\t\t}\n\t\tprevIter = iter;\n\t\t// Transform corners.\n\t\tnvgTransformPoint(&c[0],&c[1], state->xform, q.x0*invscale, q.y0*invscale);\n\t\tnvgTransformPoint(&c[2],&c[3], state->xform, q.x1*invscale, q.y0*invscale);\n\t\tnvgTransformPoint(&c[4],&c[5], state->xform, q.x1*invscale, q.y1*invscale);\n\t\tnvgTransformPoint(&c[6],&c[7], state->xform, q.x0*invscale, q.y1*invscale);\n\t\t// Create triangles\n\t\tif (nverts+6 <= cverts) {\n\t\t\tnvg__vset(&verts[nverts], c[0], c[1], q.s0, q.t0); nverts++;\n\t\t\tnvg__vset(&verts[nverts], c[4], c[5], q.s1, q.t1); nverts++;\n\t\t\tnvg__vset(&verts[nverts], c[2], c[3], q.s1, q.t0); nverts++;\n\t\t\tnvg__vset(&verts[nverts], c[0], c[1], q.s0, q.t0); nverts++;\n\t\t\tnvg__vset(&verts[nverts], c[6], c[7], q.s0, q.t1); nverts++;\n\t\t\tnvg__vset(&verts[nverts], c[4], c[5], q.s1, q.t1); nverts++;\n\t\t}\n\t}\n\n\t// TODO: add back-end bit to do this just once per frame.\n\tnvg__flushTextTexture(ctx);\n\n\tnvg__renderText(ctx, verts, nverts);\n\n\treturn iter.x;\n}\n\nvoid nvgTextBox(NVGcontext* ctx, float x, float y, float breakRowWidth, const char* string, const char* end)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tNVGtextRow rows[2];\n\tint nrows = 0, i;\n\tint oldAlign = state->textAlign;\n\tint haling = state->textAlign & (NVG_ALIGN_LEFT | NVG_ALIGN_CENTER | NVG_ALIGN_RIGHT);\n\tint valign = state->textAlign & (NVG_ALIGN_TOP | NVG_ALIGN_MIDDLE | NVG_ALIGN_BOTTOM | NVG_ALIGN_BASELINE);\n\tfloat lineh = 0;\n\n\tif (state->fontId == FONS_INVALID) return;\n\n\tnvgTextMetrics(ctx, NULL, NULL, &lineh);\n\n\tstate->textAlign = NVG_ALIGN_LEFT | valign;\n\n\twhile ((nrows = nvgTextBreakLines(ctx, string, end, breakRowWidth, rows, 2))) {\n\t\tfor (i = 0; i < nrows; i++) {\n\t\t\tNVGtextRow* row = &rows[i];\n\t\t\tif (haling & NVG_ALIGN_LEFT)\n\t\t\t\tnvgText(ctx, x, y, row->start, row->end);\n\t\t\telse if (haling & NVG_ALIGN_CENTER)\n\t\t\t\tnvgText(ctx, x + breakRowWidth*0.5f - row->width*0.5f, y, row->start, row->end);\n\t\t\telse if (haling & NVG_ALIGN_RIGHT)\n\t\t\t\tnvgText(ctx, x + breakRowWidth - row->width, y, row->start, row->end);\n\t\t\ty += lineh * state->lineHeight;\n\t\t}\n\t\tstring = rows[nrows-1].next;\n\t}\n\n\tstate->textAlign = oldAlign;\n}\n\nint nvgTextGlyphPositions(NVGcontext* ctx, float x, float y, const char* string, const char* end, NVGglyphPosition* positions, int maxPositions)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat scale = nvg__getFontScale(state) * ctx->devicePxRatio;\n\tfloat invscale = 1.0f / scale;\n\tFONStextIter iter, prevIter;\n\tFONSquad q;\n\tint npos = 0;\n\n\tif (state->fontId == FONS_INVALID) return 0;\n\n\tif (end == NULL)\n\t\tend = string + strlen(string);\n\n\tif (string == end)\n\t\treturn 0;\n\n\tfonsSetSize(ctx->fs, state->fontSize*scale);\n\tfonsSetSpacing(ctx->fs, state->letterSpacing*scale);\n\tfonsSetBlur(ctx->fs, state->fontBlur*scale);\n\tfonsSetAlign(ctx->fs, state->textAlign);\n\tfonsSetFont(ctx->fs, state->fontId);\n\n\tfonsTextIterInit(ctx->fs, &iter, x*scale, y*scale, string, end);\n\tprevIter = iter;\n\twhile (fonsTextIterNext(ctx->fs, &iter, &q)) {\n\t\tif (iter.prevGlyphIndex < 0 && nvg__allocTextAtlas(ctx)) { // can not retrieve glyph?\n\t\t\titer = prevIter;\n\t\t\tfonsTextIterNext(ctx->fs, &iter, &q); // try again\n\t\t}\n\t\tprevIter = iter;\n\t\tpositions[npos].str = iter.str;\n\t\tpositions[npos].x = iter.x * invscale;\n\t\tpositions[npos].minx = nvg__minf(iter.x, q.x0) * invscale;\n\t\tpositions[npos].maxx = nvg__maxf(iter.nextx, q.x1) * invscale;\n\t\tnpos++;\n\t\tif (npos >= maxPositions)\n\t\t\tbreak;\n\t}\n\n\treturn npos;\n}\n\nenum NVGcodepointType {\n\tNVG_SPACE,\n\tNVG_NEWLINE,\n\tNVG_CHAR,\n};\n\nint nvgTextBreakLines(NVGcontext* ctx, const char* string, const char* end, float breakRowWidth, NVGtextRow* rows, int maxRows)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat scale = nvg__getFontScale(state) * ctx->devicePxRatio;\n\tfloat invscale = 1.0f / scale;\n\tFONStextIter iter, prevIter;\n\tFONSquad q;\n\tint nrows = 0;\n\tfloat rowStartX = 0;\n\tfloat rowWidth = 0;\n\tfloat rowMinX = 0;\n\tfloat rowMaxX = 0;\n\tconst char* rowStart = NULL;\n\tconst char* rowEnd = NULL;\n\tconst char* wordStart = NULL;\n\tfloat wordStartX = 0;\n\tfloat wordMinX = 0;\n\tconst char* breakEnd = NULL;\n\tfloat breakWidth = 0;\n\tfloat breakMaxX = 0;\n\tint type = NVG_SPACE, ptype = NVG_SPACE;\n\tunsigned int pcodepoint = 0;\n\n\tif (maxRows == 0) return 0;\n\tif (state->fontId == FONS_INVALID) return 0;\n\n\tif (end == NULL)\n\t\tend = string + strlen(string);\n\n\tif (string == end) return 0;\n\n\tfonsSetSize(ctx->fs, state->fontSize*scale);\n\tfonsSetSpacing(ctx->fs, state->letterSpacing*scale);\n\tfonsSetBlur(ctx->fs, state->fontBlur*scale);\n\tfonsSetAlign(ctx->fs, state->textAlign);\n\tfonsSetFont(ctx->fs, state->fontId);\n\n\tbreakRowWidth *= scale;\n\n\tfonsTextIterInit(ctx->fs, &iter, 0, 0, string, end);\n\tprevIter = iter;\n\twhile (fonsTextIterNext(ctx->fs, &iter, &q)) {\n\t\tif (iter.prevGlyphIndex < 0 && nvg__allocTextAtlas(ctx)) { // can not retrieve glyph?\n\t\t\titer = prevIter;\n\t\t\tfonsTextIterNext(ctx->fs, &iter, &q); // try again\n\t\t}\n\t\tprevIter = iter;\n\t\tswitch (iter.codepoint) {\n\t\t\tcase 9:\t\t\t// \\t\n\t\t\tcase 11:\t\t// \\v\n\t\t\tcase 12:\t\t// \\f\n\t\t\tcase 32:\t\t// space\n\t\t\tcase 0x00a0:\t// NBSP\n\t\t\t\ttype = NVG_SPACE;\n\t\t\t\tbreak;\n\t\t\tcase 10:\t\t// \\n\n\t\t\t\ttype = pcodepoint == 13 ? NVG_SPACE : NVG_NEWLINE;\n\t\t\t\tbreak;\n\t\t\tcase 13:\t\t// \\r\n\t\t\t\ttype = pcodepoint == 10 ? NVG_SPACE : NVG_NEWLINE;\n\t\t\t\tbreak;\n\t\t\tcase 0x0085:\t// NEL\n\t\t\t\ttype = NVG_NEWLINE;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\ttype = NVG_CHAR;\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (type == NVG_NEWLINE) {\n\t\t\t// Always handle new lines.\n\t\t\trows[nrows].start = rowStart != NULL ? rowStart : iter.str;\n\t\t\trows[nrows].end = rowEnd != NULL ? rowEnd : iter.str;\n\t\t\trows[nrows].width = rowWidth * invscale;\n\t\t\trows[nrows].minx = rowMinX * invscale;\n\t\t\trows[nrows].maxx = rowMaxX * invscale;\n\t\t\trows[nrows].next = iter.next;\n\t\t\tnrows++;\n\t\t\tif (nrows >= maxRows)\n\t\t\t\treturn nrows;\n\t\t\t// Set null break point\n\t\t\tbreakEnd = rowStart;\n\t\t\tbreakWidth = 0.0;\n\t\t\tbreakMaxX = 0.0;\n\t\t\t// Indicate to skip the white space at the beginning of the row.\n\t\t\trowStart = NULL;\n\t\t\trowEnd = NULL;\n\t\t\trowWidth = 0;\n\t\t\trowMinX = rowMaxX = 0;\n\t\t} else {\n\t\t\tif (rowStart == NULL) {\n\t\t\t\t// Skip white space until the beginning of the line\n\t\t\t\tif (type == NVG_CHAR) {\n\t\t\t\t\t// The current char is the row so far\n\t\t\t\t\trowStartX = iter.x;\n\t\t\t\t\trowStart = iter.str;\n\t\t\t\t\trowEnd = iter.next;\n\t\t\t\t\trowWidth = iter.nextx - rowStartX; // q.x1 - rowStartX;\n\t\t\t\t\trowMinX = q.x0 - rowStartX;\n\t\t\t\t\trowMaxX = q.x1 - rowStartX;\n\t\t\t\t\twordStart = iter.str;\n\t\t\t\t\twordStartX = iter.x;\n\t\t\t\t\twordMinX = q.x0 - rowStartX;\n\t\t\t\t\t// Set null break point\n\t\t\t\t\tbreakEnd = rowStart;\n\t\t\t\t\tbreakWidth = 0.0;\n\t\t\t\t\tbreakMaxX = 0.0;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tfloat nextWidth = iter.nextx - rowStartX;\n\n\t\t\t\t// track last non-white space character\n\t\t\t\tif (type == NVG_CHAR) {\n\t\t\t\t\trowEnd = iter.next;\n\t\t\t\t\trowWidth = iter.nextx - rowStartX;\n\t\t\t\t\trowMaxX = q.x1 - rowStartX;\n\t\t\t\t}\n\t\t\t\t// track last end of a word\n\t\t\t\tif (ptype == NVG_CHAR && type == NVG_SPACE) {\n\t\t\t\t\tbreakEnd = iter.str;\n\t\t\t\t\tbreakWidth = rowWidth;\n\t\t\t\t\tbreakMaxX = rowMaxX;\n\t\t\t\t}\n\t\t\t\t// track last beginning of a word\n\t\t\t\tif (ptype == NVG_SPACE && type == NVG_CHAR) {\n\t\t\t\t\twordStart = iter.str;\n\t\t\t\t\twordStartX = iter.x;\n\t\t\t\t\twordMinX = q.x0 - rowStartX;\n\t\t\t\t}\n\n\t\t\t\t// Break to new line when a character is beyond break width.\n\t\t\t\tif (type == NVG_CHAR && nextWidth > breakRowWidth) {\n\t\t\t\t\t// The run length is too long, need to break to new line.\n\t\t\t\t\tif (breakEnd == rowStart) {\n\t\t\t\t\t\t// The current word is longer than the row length, just break it from here.\n\t\t\t\t\t\trows[nrows].start = rowStart;\n\t\t\t\t\t\trows[nrows].end = iter.str;\n\t\t\t\t\t\trows[nrows].width = rowWidth * invscale;\n\t\t\t\t\t\trows[nrows].minx = rowMinX * invscale;\n\t\t\t\t\t\trows[nrows].maxx = rowMaxX * invscale;\n\t\t\t\t\t\trows[nrows].next = iter.str;\n\t\t\t\t\t\tnrows++;\n\t\t\t\t\t\tif (nrows >= maxRows)\n\t\t\t\t\t\t\treturn nrows;\n\t\t\t\t\t\trowStartX = iter.x;\n\t\t\t\t\t\trowStart = iter.str;\n\t\t\t\t\t\trowEnd = iter.next;\n\t\t\t\t\t\trowWidth = iter.nextx - rowStartX;\n\t\t\t\t\t\trowMinX = q.x0 - rowStartX;\n\t\t\t\t\t\trowMaxX = q.x1 - rowStartX;\n\t\t\t\t\t\twordStart = iter.str;\n\t\t\t\t\t\twordStartX = iter.x;\n\t\t\t\t\t\twordMinX = q.x0 - rowStartX;\n\t\t\t\t\t} else {\n\t\t\t\t\t\t// Break the line from the end of the last word, and start new line from the beginning of the new.\n\t\t\t\t\t\trows[nrows].start = rowStart;\n\t\t\t\t\t\trows[nrows].end = breakEnd;\n\t\t\t\t\t\trows[nrows].width = breakWidth * invscale;\n\t\t\t\t\t\trows[nrows].minx = rowMinX * invscale;\n\t\t\t\t\t\trows[nrows].maxx = breakMaxX * invscale;\n\t\t\t\t\t\trows[nrows].next = wordStart;\n\t\t\t\t\t\tnrows++;\n\t\t\t\t\t\tif (nrows >= maxRows)\n\t\t\t\t\t\t\treturn nrows;\n\t\t\t\t\t\trowStartX = wordStartX;\n\t\t\t\t\t\trowStart = wordStart;\n\t\t\t\t\t\trowEnd = iter.next;\n\t\t\t\t\t\trowWidth = iter.nextx - rowStartX;\n\t\t\t\t\t\trowMinX = wordMinX;\n\t\t\t\t\t\trowMaxX = q.x1 - rowStartX;\n\t\t\t\t\t\t// No change to the word start\n\t\t\t\t\t}\n\t\t\t\t\t// Set null break point\n\t\t\t\t\tbreakEnd = rowStart;\n\t\t\t\t\tbreakWidth = 0.0;\n\t\t\t\t\tbreakMaxX = 0.0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tpcodepoint = iter.codepoint;\n\t\tptype = type;\n\t}\n\n\t// Break the line from the end of the last word, and start new line from the beginning of the new.\n\tif (rowStart != NULL) {\n\t\trows[nrows].start = rowStart;\n\t\trows[nrows].end = rowEnd;\n\t\trows[nrows].width = rowWidth * invscale;\n\t\trows[nrows].minx = rowMinX * invscale;\n\t\trows[nrows].maxx = rowMaxX * invscale;\n\t\trows[nrows].next = end;\n\t\tnrows++;\n\t}\n\n\treturn nrows;\n}\n\nfloat nvgTextBounds(NVGcontext* ctx, float x, float y, const char* string, const char* end, float* bounds)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat scale = nvg__getFontScale(state) * ctx->devicePxRatio;\n\tfloat invscale = 1.0f / scale;\n\tfloat width;\n\n\tif (state->fontId == FONS_INVALID) return 0;\n\n\tfonsSetSize(ctx->fs, state->fontSize*scale);\n\tfonsSetSpacing(ctx->fs, state->letterSpacing*scale);\n\tfonsSetBlur(ctx->fs, state->fontBlur*scale);\n\tfonsSetAlign(ctx->fs, state->textAlign);\n\tfonsSetFont(ctx->fs, state->fontId);\n\n\twidth = fonsTextBounds(ctx->fs, x*scale, y*scale, string, end, bounds);\n\tif (bounds != NULL) {\n\t\t// Use line bounds for height.\n\t\tfonsLineBounds(ctx->fs, y*scale, &bounds[1], &bounds[3]);\n\t\tbounds[0] *= invscale;\n\t\tbounds[1] *= invscale;\n\t\tbounds[2] *= invscale;\n\t\tbounds[3] *= invscale;\n\t}\n\treturn width * invscale;\n}\n\nvoid nvgTextBoxBounds(NVGcontext* ctx, float x, float y, float breakRowWidth, const char* string, const char* end, float* bounds)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tNVGtextRow rows[2];\n\tfloat scale = nvg__getFontScale(state) * ctx->devicePxRatio;\n\tfloat invscale = 1.0f / scale;\n\tint nrows = 0, i;\n\tint oldAlign = state->textAlign;\n\tint haling = state->textAlign & (NVG_ALIGN_LEFT | NVG_ALIGN_CENTER | NVG_ALIGN_RIGHT);\n\tint valign = state->textAlign & (NVG_ALIGN_TOP | NVG_ALIGN_MIDDLE | NVG_ALIGN_BOTTOM | NVG_ALIGN_BASELINE);\n\tfloat lineh = 0, rminy = 0, rmaxy = 0;\n\tfloat minx, miny, maxx, maxy;\n\n\tif (state->fontId == FONS_INVALID) {\n\t\tif (bounds != NULL)\n\t\t\tbounds[0] = bounds[1] = bounds[2] = bounds[3] = 0.0f;\n\t\treturn;\n\t}\n\n\tnvgTextMetrics(ctx, NULL, NULL, &lineh);\n\n\tstate->textAlign = NVG_ALIGN_LEFT | valign;\n\n\tminx = maxx = x;\n\tminy = maxy = y;\n\n\tfonsSetSize(ctx->fs, state->fontSize*scale);\n\tfonsSetSpacing(ctx->fs, state->letterSpacing*scale);\n\tfonsSetBlur(ctx->fs, state->fontBlur*scale);\n\tfonsSetAlign(ctx->fs, state->textAlign);\n\tfonsSetFont(ctx->fs, state->fontId);\n\tfonsLineBounds(ctx->fs, 0, &rminy, &rmaxy);\n\trminy *= invscale;\n\trmaxy *= invscale;\n\n\twhile ((nrows = nvgTextBreakLines(ctx, string, end, breakRowWidth, rows, 2))) {\n\t\tfor (i = 0; i < nrows; i++) {\n\t\t\tNVGtextRow* row = &rows[i];\n\t\t\tfloat rminx, rmaxx, dx = 0;\n\t\t\t// Horizontal bounds\n\t\t\tif (haling & NVG_ALIGN_LEFT)\n\t\t\t\tdx = 0;\n\t\t\telse if (haling & NVG_ALIGN_CENTER)\n\t\t\t\tdx = breakRowWidth*0.5f - row->width*0.5f;\n\t\t\telse if (haling & NVG_ALIGN_RIGHT)\n\t\t\t\tdx = breakRowWidth - row->width;\n\t\t\trminx = x + row->minx + dx;\n\t\t\trmaxx = x + row->maxx + dx;\n\t\t\tminx = nvg__minf(minx, rminx);\n\t\t\tmaxx = nvg__maxf(maxx, rmaxx);\n\t\t\t// Vertical bounds.\n\t\t\tminy = nvg__minf(miny, y + rminy);\n\t\t\tmaxy = nvg__maxf(maxy, y + rmaxy);\n\n\t\t\ty += lineh * state->lineHeight;\n\t\t}\n\t\tstring = rows[nrows-1].next;\n\t}\n\n\tstate->textAlign = oldAlign;\n\n\tif (bounds != NULL) {\n\t\tbounds[0] = minx;\n\t\tbounds[1] = miny;\n\t\tbounds[2] = maxx;\n\t\tbounds[3] = maxy;\n\t}\n}\n\nvoid nvgTextMetrics(NVGcontext* ctx, float* ascender, float* descender, float* lineh)\n{\n\tNVGstate* state = nvg__getState(ctx);\n\tfloat scale = nvg__getFontScale(state) * ctx->devicePxRatio;\n\tfloat invscale = 1.0f / scale;\n\n\tif (state->fontId == FONS_INVALID) return;\n\n\tfonsSetSize(ctx->fs, state->fontSize*scale);\n\tfonsSetSpacing(ctx->fs, state->letterSpacing*scale);\n\tfonsSetBlur(ctx->fs, state->fontBlur*scale);\n\tfonsSetAlign(ctx->fs, state->textAlign);\n\tfonsSetFont(ctx->fs, state->fontId);\n\n\tfonsVertMetrics(ctx->fs, ascender, descender, lineh);\n\tif (ascender != NULL)\n\t\t*ascender *= invscale;\n\tif (descender != NULL)\n\t\t*descender *= invscale;\n\tif (lineh != NULL)\n\t\t*lineh *= invscale;\n}\n// vim: ft=c nu noet ts=4\n"
  },
  {
    "path": "phonelibs/nanovg/nanovg.h",
    "content": "//\n// Copyright (c) 2013 Mikko Mononen memon@inside.org\n//\n// This software is provided 'as-is', without any express or implied\n// warranty.  In no event will the authors be held liable for any damages\n// arising from the use of this software.\n// Permission is granted to anyone to use this software for any purpose,\n// including commercial applications, and to alter it and redistribute it\n// freely, subject to the following restrictions:\n// 1. The origin of this software must not be misrepresented; you must not\n//    claim that you wrote the original software. If you use this software\n//    in a product, an acknowledgment in the product documentation would be\n//    appreciated but is not required.\n// 2. Altered source versions must be plainly marked as such, and must not be\n//    misrepresented as being the original software.\n// 3. This notice may not be removed or altered from any source distribution.\n//\n\n#ifndef NANOVG_H\n#define NANOVG_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define NVG_PI 3.14159265358979323846264338327f\n\n#ifdef _MSC_VER\n#pragma warning(push)\n#pragma warning(disable: 4201)  // nonstandard extension used : nameless struct/union\n#endif\n\ntypedef struct NVGcontext NVGcontext;\n\nstruct NVGcolor {\n\tunion {\n\t\tfloat rgba[4];\n\t\tstruct {\n\t\t\tfloat r,g,b,a;\n\t\t};\n\t};\n};\ntypedef struct NVGcolor NVGcolor;\n\nstruct NVGpaint {\n\tfloat xform[6];\n\tfloat extent[2];\n\tfloat radius;\n\tfloat feather;\n\tNVGcolor innerColor;\n\tNVGcolor outerColor;\n\tint image;\n};\ntypedef struct NVGpaint NVGpaint;\n\nenum NVGwinding {\n\tNVG_CCW = 1,\t\t\t// Winding for solid shapes\n\tNVG_CW = 2,\t\t\t\t// Winding for holes\n};\n\nenum NVGsolidity {\n\tNVG_SOLID = 1,\t\t\t// CCW\n\tNVG_HOLE = 2,\t\t\t// CW\n};\n\nenum NVGlineCap {\n\tNVG_BUTT,\n\tNVG_ROUND,\n\tNVG_SQUARE,\n\tNVG_BEVEL,\n\tNVG_MITER,\n};\n\nenum NVGalign {\n\t// Horizontal align\n\tNVG_ALIGN_LEFT \t\t= 1<<0,\t// Default, align text horizontally to left.\n\tNVG_ALIGN_CENTER \t= 1<<1,\t// Align text horizontally to center.\n\tNVG_ALIGN_RIGHT \t= 1<<2,\t// Align text horizontally to right.\n\t// Vertical align\n\tNVG_ALIGN_TOP \t\t= 1<<3,\t// Align text vertically to top.\n\tNVG_ALIGN_MIDDLE\t= 1<<4,\t// Align text vertically to middle.\n\tNVG_ALIGN_BOTTOM\t= 1<<5,\t// Align text vertically to bottom.\n\tNVG_ALIGN_BASELINE\t= 1<<6, // Default, align text vertically to baseline.\n};\n\nenum NVGblendFactor {\n\tNVG_ZERO = 1<<0,\n\tNVG_ONE = 1<<1,\n\tNVG_SRC_COLOR = 1<<2,\n\tNVG_ONE_MINUS_SRC_COLOR = 1<<3,\n\tNVG_DST_COLOR = 1<<4,\n\tNVG_ONE_MINUS_DST_COLOR = 1<<5,\n\tNVG_SRC_ALPHA = 1<<6,\n\tNVG_ONE_MINUS_SRC_ALPHA = 1<<7,\n\tNVG_DST_ALPHA = 1<<8,\n\tNVG_ONE_MINUS_DST_ALPHA = 1<<9,\n\tNVG_SRC_ALPHA_SATURATE = 1<<10,\n};\n\nenum NVGcompositeOperation {\n\tNVG_SOURCE_OVER,\n\tNVG_SOURCE_IN,\n\tNVG_SOURCE_OUT,\n\tNVG_ATOP,\n\tNVG_DESTINATION_OVER,\n\tNVG_DESTINATION_IN,\n\tNVG_DESTINATION_OUT,\n\tNVG_DESTINATION_ATOP,\n\tNVG_LIGHTER,\n\tNVG_COPY,\n\tNVG_XOR,\n};\n\nstruct NVGcompositeOperationState {\n\tint srcRGB;\n\tint dstRGB;\n\tint srcAlpha;\n\tint dstAlpha;\n};\ntypedef struct NVGcompositeOperationState NVGcompositeOperationState;\n\nstruct NVGglyphPosition {\n\tconst char* str;\t// Position of the glyph in the input string.\n\tfloat x;\t\t\t// The x-coordinate of the logical glyph position.\n\tfloat minx, maxx;\t// The bounds of the glyph shape.\n};\ntypedef struct NVGglyphPosition NVGglyphPosition;\n\nstruct NVGtextRow {\n\tconst char* start;\t// Pointer to the input text where the row starts.\n\tconst char* end;\t// Pointer to the input text where the row ends (one past the last character).\n\tconst char* next;\t// Pointer to the beginning of the next row.\n\tfloat width;\t\t// Logical width of the row.\n\tfloat minx, maxx;\t// Actual bounds of the row. Logical with and bounds can differ because of kerning and some parts over extending.\n};\ntypedef struct NVGtextRow NVGtextRow;\n\nenum NVGimageFlags {\n    NVG_IMAGE_GENERATE_MIPMAPS\t= 1<<0,     // Generate mipmaps during creation of the image.\n\tNVG_IMAGE_REPEATX\t\t\t= 1<<1,\t\t// Repeat image in X direction.\n\tNVG_IMAGE_REPEATY\t\t\t= 1<<2,\t\t// Repeat image in Y direction.\n\tNVG_IMAGE_FLIPY\t\t\t\t= 1<<3,\t\t// Flips (inverses) image in Y direction when rendered.\n\tNVG_IMAGE_PREMULTIPLIED\t\t= 1<<4,\t\t// Image data has premultiplied alpha.\n};\n\n// Begin drawing a new frame\n// Calls to nanovg drawing API should be wrapped in nvgBeginFrame() & nvgEndFrame()\n// nvgBeginFrame() defines the size of the window to render to in relation currently\n// set viewport (i.e. glViewport on GL backends). Device pixel ration allows to\n// control the rendering on Hi-DPI devices.\n// For example, GLFW returns two dimension for an opened window: window size and\n// frame buffer size. In that case you would set windowWidth/Height to the window size\n// devicePixelRatio to: frameBufferWidth / windowWidth.\nvoid nvgBeginFrame(NVGcontext* ctx, int windowWidth, int windowHeight, float devicePixelRatio);\n\n// Cancels drawing the current frame.\nvoid nvgCancelFrame(NVGcontext* ctx);\n\n// Ends drawing flushing remaining render state.\nvoid nvgEndFrame(NVGcontext* ctx);\n\n//\n// Composite operation\n//\n// The composite operations in NanoVG are modeled after HTML Canvas API, and\n// the blend func is based on OpenGL (see corresponding manuals for more info).\n// The colors in the blending state have premultiplied alpha.\n\n// Sets the composite operation. The op parameter should be one of NVGcompositeOperation.\nvoid nvgGlobalCompositeOperation(NVGcontext* ctx, int op);\n\n// Sets the composite operation with custom pixel arithmetic. The parameters should be one of NVGblendFactor.\nvoid nvgGlobalCompositeBlendFunc(NVGcontext* ctx, int sfactor, int dfactor);\n\n// Sets the composite operation with custom pixel arithmetic for RGB and alpha components separately. The parameters should be one of NVGblendFactor.\nvoid nvgGlobalCompositeBlendFuncSeparate(NVGcontext* ctx, int srcRGB, int dstRGB, int srcAlpha, int dstAlpha);\n\n//\n// Color utils\n//\n// Colors in NanoVG are stored as unsigned ints in ABGR format.\n\n// Returns a color value from red, green, blue values. Alpha will be set to 255 (1.0f).\nNVGcolor nvgRGB(unsigned char r, unsigned char g, unsigned char b);\n\n// Returns a color value from red, green, blue values. Alpha will be set to 1.0f.\nNVGcolor nvgRGBf(float r, float g, float b);\n\n\n// Returns a color value from red, green, blue and alpha values.\nNVGcolor nvgRGBA(unsigned char r, unsigned char g, unsigned char b, unsigned char a);\n\n// Returns a color value from red, green, blue and alpha values.\nNVGcolor nvgRGBAf(float r, float g, float b, float a);\n\n\n// Linearly interpolates from color c0 to c1, and returns resulting color value.\nNVGcolor nvgLerpRGBA(NVGcolor c0, NVGcolor c1, float u);\n\n// Sets transparency of a color value.\nNVGcolor nvgTransRGBA(NVGcolor c0, unsigned char a);\n\n// Sets transparency of a color value.\nNVGcolor nvgTransRGBAf(NVGcolor c0, float a);\n\n// Returns color value specified by hue, saturation and lightness.\n// HSL values are all in range [0..1], alpha will be set to 255.\nNVGcolor nvgHSL(float h, float s, float l);\n\n// Returns color value specified by hue, saturation and lightness and alpha.\n// HSL values are all in range [0..1], alpha in range [0..255]\nNVGcolor nvgHSLA(float h, float s, float l, unsigned char a);\n\n//\n// State Handling\n//\n// NanoVG contains state which represents how paths will be rendered.\n// The state contains transform, fill and stroke styles, text and font styles,\n// and scissor clipping.\n\n// Pushes and saves the current render state into a state stack.\n// A matching nvgRestore() must be used to restore the state.\nvoid nvgSave(NVGcontext* ctx);\n\n// Pops and restores current render state.\nvoid nvgRestore(NVGcontext* ctx);\n\n// Resets current render state to default values. Does not affect the render state stack.\nvoid nvgReset(NVGcontext* ctx);\n\n//\n// Render styles\n//\n// Fill and stroke render style can be either a solid color or a paint which is a gradient or a pattern.\n// Solid color is simply defined as a color value, different kinds of paints can be created\n// using nvgLinearGradient(), nvgBoxGradient(), nvgRadialGradient() and nvgImagePattern().\n//\n// Current render style can be saved and restored using nvgSave() and nvgRestore().\n\n// Sets current stroke style to a solid color.\nvoid nvgStrokeColor(NVGcontext* ctx, NVGcolor color);\n\n// Sets current stroke style to a paint, which can be a one of the gradients or a pattern.\nvoid nvgStrokePaint(NVGcontext* ctx, NVGpaint paint);\n\n// Sets current fill style to a solid color.\nvoid nvgFillColor(NVGcontext* ctx, NVGcolor color);\n\n// Sets current fill style to a paint, which can be a one of the gradients or a pattern.\nvoid nvgFillPaint(NVGcontext* ctx, NVGpaint paint);\n\n// Sets the miter limit of the stroke style.\n// Miter limit controls when a sharp corner is beveled.\nvoid nvgMiterLimit(NVGcontext* ctx, float limit);\n\n// Sets the stroke width of the stroke style.\nvoid nvgStrokeWidth(NVGcontext* ctx, float size);\n\n// Sets how the end of the line (cap) is drawn,\n// Can be one of: NVG_BUTT (default), NVG_ROUND, NVG_SQUARE.\nvoid nvgLineCap(NVGcontext* ctx, int cap);\n\n// Sets how sharp path corners are drawn.\n// Can be one of NVG_MITER (default), NVG_ROUND, NVG_BEVEL.\nvoid nvgLineJoin(NVGcontext* ctx, int join);\n\n// Sets the transparency applied to all rendered shapes.\n// Already transparent paths will get proportionally more transparent as well.\nvoid nvgGlobalAlpha(NVGcontext* ctx, float alpha);\n\n//\n// Transforms\n//\n// The paths, gradients, patterns and scissor region are transformed by an transformation\n// matrix at the time when they are passed to the API.\n// The current transformation matrix is a affine matrix:\n//   [sx kx tx]\n//   [ky sy ty]\n//   [ 0  0  1]\n// Where: sx,sy define scaling, kx,ky skewing, and tx,ty translation.\n// The last row is assumed to be 0,0,1 and is not stored.\n//\n// Apart from nvgResetTransform(), each transformation function first creates\n// specific transformation matrix and pre-multiplies the current transformation by it.\n//\n// Current coordinate system (transformation) can be saved and restored using nvgSave() and nvgRestore().\n\n// Resets current transform to a identity matrix.\nvoid nvgResetTransform(NVGcontext* ctx);\n\n// Premultiplies current coordinate system by specified matrix.\n// The parameters are interpreted as matrix as follows:\n//   [a c e]\n//   [b d f]\n//   [0 0 1]\nvoid nvgTransform(NVGcontext* ctx, float a, float b, float c, float d, float e, float f);\n\n// Translates current coordinate system.\nvoid nvgTranslate(NVGcontext* ctx, float x, float y);\n\n// Rotates current coordinate system. Angle is specified in radians.\nvoid nvgRotate(NVGcontext* ctx, float angle);\n\n// Skews the current coordinate system along X axis. Angle is specified in radians.\nvoid nvgSkewX(NVGcontext* ctx, float angle);\n\n// Skews the current coordinate system along Y axis. Angle is specified in radians.\nvoid nvgSkewY(NVGcontext* ctx, float angle);\n\n// Scales the current coordinate system.\nvoid nvgScale(NVGcontext* ctx, float x, float y);\n\n// Stores the top part (a-f) of the current transformation matrix in to the specified buffer.\n//   [a c e]\n//   [b d f]\n//   [0 0 1]\n// There should be space for 6 floats in the return buffer for the values a-f.\nvoid nvgCurrentTransform(NVGcontext* ctx, float* xform);\n\n\n// The following functions can be used to make calculations on 2x3 transformation matrices.\n// A 2x3 matrix is represented as float[6].\n\n// Sets the transform to identity matrix.\nvoid nvgTransformIdentity(float* dst);\n\n// Sets the transform to translation matrix matrix.\nvoid nvgTransformTranslate(float* dst, float tx, float ty);\n\n// Sets the transform to scale matrix.\nvoid nvgTransformScale(float* dst, float sx, float sy);\n\n// Sets the transform to rotate matrix. Angle is specified in radians.\nvoid nvgTransformRotate(float* dst, float a);\n\n// Sets the transform to skew-x matrix. Angle is specified in radians.\nvoid nvgTransformSkewX(float* dst, float a);\n\n// Sets the transform to skew-y matrix. Angle is specified in radians.\nvoid nvgTransformSkewY(float* dst, float a);\n\n// Sets the transform to the result of multiplication of two transforms, of A = A*B.\nvoid nvgTransformMultiply(float* dst, const float* src);\n\n// Sets the transform to the result of multiplication of two transforms, of A = B*A.\nvoid nvgTransformPremultiply(float* dst, const float* src);\n\n// Sets the destination to inverse of specified transform.\n// Returns 1 if the inverse could be calculated, else 0.\nint nvgTransformInverse(float* dst, const float* src);\n\n// Transform a point by given transform.\nvoid nvgTransformPoint(float* dstx, float* dsty, const float* xform, float srcx, float srcy);\n\n// Converts degrees to radians and vice versa.\nfloat nvgDegToRad(float deg);\nfloat nvgRadToDeg(float rad);\n\n//\n// Images\n//\n// NanoVG allows you to load jpg, png, psd, tga, pic and gif files to be used for rendering.\n// In addition you can upload your own image. The image loading is provided by stb_image.\n// The parameter imageFlags is combination of flags defined in NVGimageFlags.\n\n// Creates image by loading it from the disk from specified file name.\n// Returns handle to the image.\nint nvgCreateImage(NVGcontext* ctx, const char* filename, int imageFlags);\n\n// Creates image by loading it from the specified chunk of memory.\n// Returns handle to the image.\nint nvgCreateImageMem(NVGcontext* ctx, int imageFlags, unsigned char* data, int ndata);\n\n// Creates image from specified image data.\n// Returns handle to the image.\nint nvgCreateImageRGBA(NVGcontext* ctx, int w, int h, int imageFlags, const unsigned char* data);\n\n// Updates image data specified by image handle.\nvoid nvgUpdateImage(NVGcontext* ctx, int image, const unsigned char* data);\n\n// Returns the dimensions of a created image.\nvoid nvgImageSize(NVGcontext* ctx, int image, int* w, int* h);\n\n// Deletes created image.\nvoid nvgDeleteImage(NVGcontext* ctx, int image);\n\n//\n// Paints\n//\n// NanoVG supports four types of paints: linear gradient, box gradient, radial gradient and image pattern.\n// These can be used as paints for strokes and fills.\n\n// Creates and returns a linear gradient. Parameters (sx,sy)-(ex,ey) specify the start and end coordinates\n// of the linear gradient, icol specifies the start color and ocol the end color.\n// The gradient is transformed by the current transform when it is passed to nvgFillPaint() or nvgStrokePaint().\nNVGpaint nvgLinearGradient(NVGcontext* ctx, float sx, float sy, float ex, float ey,\n\t\t\t\t\t\t   NVGcolor icol, NVGcolor ocol);\n\n// Creates and returns a box gradient. Box gradient is a feathered rounded rectangle, it is useful for rendering\n// drop shadows or highlights for boxes. Parameters (x,y) define the top-left corner of the rectangle,\n// (w,h) define the size of the rectangle, r defines the corner radius, and f feather. Feather defines how blurry\n// the border of the rectangle is. Parameter icol specifies the inner color and ocol the outer color of the gradient.\n// The gradient is transformed by the current transform when it is passed to nvgFillPaint() or nvgStrokePaint().\nNVGpaint nvgBoxGradient(NVGcontext* ctx, float x, float y, float w, float h,\n\t\t\t\t\t\tfloat r, float f, NVGcolor icol, NVGcolor ocol);\n\n// Creates and returns a radial gradient. Parameters (cx,cy) specify the center, inr and outr specify\n// the inner and outer radius of the gradient, icol specifies the start color and ocol the end color.\n// The gradient is transformed by the current transform when it is passed to nvgFillPaint() or nvgStrokePaint().\nNVGpaint nvgRadialGradient(NVGcontext* ctx, float cx, float cy, float inr, float outr,\n\t\t\t\t\t\t   NVGcolor icol, NVGcolor ocol);\n\n// Creates and returns an image patter. Parameters (ox,oy) specify the left-top location of the image pattern,\n// (ex,ey) the size of one image, angle rotation around the top-left corner, image is handle to the image to render.\n// The gradient is transformed by the current transform when it is passed to nvgFillPaint() or nvgStrokePaint().\nNVGpaint nvgImagePattern(NVGcontext* ctx, float ox, float oy, float ex, float ey,\n\t\t\t\t\t\t float angle, int image, float alpha);\n\n//\n// Scissoring\n//\n// Scissoring allows you to clip the rendering into a rectangle. This is useful for various\n// user interface cases like rendering a text edit or a timeline.\n\n// Sets the current scissor rectangle.\n// The scissor rectangle is transformed by the current transform.\nvoid nvgScissor(NVGcontext* ctx, float x, float y, float w, float h);\n\n// Intersects current scissor rectangle with the specified rectangle.\n// The scissor rectangle is transformed by the current transform.\n// Note: in case the rotation of previous scissor rect differs from\n// the current one, the intersection will be done between the specified\n// rectangle and the previous scissor rectangle transformed in the current\n// transform space. The resulting shape is always rectangle.\nvoid nvgIntersectScissor(NVGcontext* ctx, float x, float y, float w, float h);\n\n// Reset and disables scissoring.\nvoid nvgResetScissor(NVGcontext* ctx);\n\n//\n// Paths\n//\n// Drawing a new shape starts with nvgBeginPath(), it clears all the currently defined paths.\n// Then you define one or more paths and sub-paths which describe the shape. The are functions\n// to draw common shapes like rectangles and circles, and lower level step-by-step functions,\n// which allow to define a path curve by curve.\n//\n// NanoVG uses even-odd fill rule to draw the shapes. Solid shapes should have counter clockwise\n// winding and holes should have counter clockwise order. To specify winding of a path you can\n// call nvgPathWinding(). This is useful especially for the common shapes, which are drawn CCW.\n//\n// Finally you can fill the path using current fill style by calling nvgFill(), and stroke it\n// with current stroke style by calling nvgStroke().\n//\n// The curve segments and sub-paths are transformed by the current transform.\n\n// Clears the current path and sub-paths.\nvoid nvgBeginPath(NVGcontext* ctx);\n\n// Starts new sub-path with specified point as first point.\nvoid nvgMoveTo(NVGcontext* ctx, float x, float y);\n\n// Adds line segment from the last point in the path to the specified point.\nvoid nvgLineTo(NVGcontext* ctx, float x, float y);\n\n// Adds cubic bezier segment from last point in the path via two control points to the specified point.\nvoid nvgBezierTo(NVGcontext* ctx, float c1x, float c1y, float c2x, float c2y, float x, float y);\n\n// Adds quadratic bezier segment from last point in the path via a control point to the specified point.\nvoid nvgQuadTo(NVGcontext* ctx, float cx, float cy, float x, float y);\n\n// Adds an arc segment at the corner defined by the last path point, and two specified points.\nvoid nvgArcTo(NVGcontext* ctx, float x1, float y1, float x2, float y2, float radius);\n\n// Closes current sub-path with a line segment.\nvoid nvgClosePath(NVGcontext* ctx);\n\n// Sets the current sub-path winding, see NVGwinding and NVGsolidity.\nvoid nvgPathWinding(NVGcontext* ctx, int dir);\n\n// Creates new circle arc shaped sub-path. The arc center is at cx,cy, the arc radius is r,\n// and the arc is drawn from angle a0 to a1, and swept in direction dir (NVG_CCW, or NVG_CW).\n// Angles are specified in radians.\nvoid nvgArc(NVGcontext* ctx, float cx, float cy, float r, float a0, float a1, int dir);\n\n// Creates new rectangle shaped sub-path.\nvoid nvgRect(NVGcontext* ctx, float x, float y, float w, float h);\n\n// Creates new rounded rectangle shaped sub-path.\nvoid nvgRoundedRect(NVGcontext* ctx, float x, float y, float w, float h, float r);\n\n// Creates new rounded rectangle shaped sub-path with varying radii for each corner.\nvoid nvgRoundedRectVarying(NVGcontext* ctx, float x, float y, float w, float h, float radTopLeft, float radTopRight, float radBottomRight, float radBottomLeft);\n\n// Creates new ellipse shaped sub-path.\nvoid nvgEllipse(NVGcontext* ctx, float cx, float cy, float rx, float ry);\n\n// Creates new circle shaped sub-path.\nvoid nvgCircle(NVGcontext* ctx, float cx, float cy, float r);\n\n// Fills the current path with current fill style.\nvoid nvgFill(NVGcontext* ctx);\n\n// Fills the current path with current stroke style.\nvoid nvgStroke(NVGcontext* ctx);\n\n\n//\n// Text\n//\n// NanoVG allows you to load .ttf files and use the font to render text.\n//\n// The appearance of the text can be defined by setting the current text style\n// and by specifying the fill color. Common text and font settings such as\n// font size, letter spacing and text align are supported. Font blur allows you\n// to create simple text effects such as drop shadows.\n//\n// At render time the font face can be set based on the font handles or name.\n//\n// Font measure functions return values in local space, the calculations are\n// carried in the same resolution as the final rendering. This is done because\n// the text glyph positions are snapped to the nearest pixels sharp rendering.\n//\n// The local space means that values are not rotated or scale as per the current\n// transformation. For example if you set font size to 12, which would mean that\n// line height is 16, then regardless of the current scaling and rotation, the\n// returned line height is always 16. Some measures may vary because of the scaling\n// since aforementioned pixel snapping.\n//\n// While this may sound a little odd, the setup allows you to always render the\n// same way regardless of scaling. I.e. following works regardless of scaling:\n//\n//\t\tconst char* txt = \"Text me up.\";\n//\t\tnvgTextBounds(vg, x,y, txt, NULL, bounds);\n//\t\tnvgBeginPath(vg);\n//\t\tnvgRoundedRect(vg, bounds[0],bounds[1], bounds[2]-bounds[0], bounds[3]-bounds[1]);\n//\t\tnvgFill(vg);\n//\n// Note: currently only solid color fill is supported for text.\n\n// Creates font by loading it from the disk from specified file name.\n// Returns handle to the font.\nint nvgCreateFont(NVGcontext* ctx, const char* name, const char* filename);\n\n// Creates font by loading it from the specified memory chunk.\n// Returns handle to the font.\nint nvgCreateFontMem(NVGcontext* ctx, const char* name, unsigned char* data, int ndata, int freeData);\n\n// Finds a loaded font of specified name, and returns handle to it, or -1 if the font is not found.\nint nvgFindFont(NVGcontext* ctx, const char* name);\n\n// Adds a fallback font by handle.\nint nvgAddFallbackFontId(NVGcontext* ctx, int baseFont, int fallbackFont);\n\n// Adds a fallback font by name.\nint nvgAddFallbackFont(NVGcontext* ctx, const char* baseFont, const char* fallbackFont);\n\n// Sets the font size of current text style.\nvoid nvgFontSize(NVGcontext* ctx, float size);\n\n// Sets the blur of current text style.\nvoid nvgFontBlur(NVGcontext* ctx, float blur);\n\n// Sets the letter spacing of current text style.\nvoid nvgTextLetterSpacing(NVGcontext* ctx, float spacing);\n\n// Sets the proportional line height of current text style. The line height is specified as multiple of font size.\nvoid nvgTextLineHeight(NVGcontext* ctx, float lineHeight);\n\n// Sets the text align of current text style, see NVGalign for options.\nvoid nvgTextAlign(NVGcontext* ctx, int align);\n\n// Sets the font face based on specified id of current text style.\nvoid nvgFontFaceId(NVGcontext* ctx, int font);\n\n// Sets the font face based on specified name of current text style.\nvoid nvgFontFace(NVGcontext* ctx, const char* font);\n\n// Draws text string at specified location. If end is specified only the sub-string up to the end is drawn.\nfloat nvgText(NVGcontext* ctx, float x, float y, const char* string, const char* end);\n\n// Draws multi-line text string at specified location wrapped at the specified width. If end is specified only the sub-string up to the end is drawn.\n// White space is stripped at the beginning of the rows, the text is split at word boundaries or when new-line characters are encountered.\n// Words longer than the max width are slit at nearest character (i.e. no hyphenation).\nvoid nvgTextBox(NVGcontext* ctx, float x, float y, float breakRowWidth, const char* string, const char* end);\n\n// Measures the specified text string. Parameter bounds should be a pointer to float[4],\n// if the bounding box of the text should be returned. The bounds value are [xmin,ymin, xmax,ymax]\n// Returns the horizontal advance of the measured text (i.e. where the next character should drawn).\n// Measured values are returned in local coordinate space.\nfloat nvgTextBounds(NVGcontext* ctx, float x, float y, const char* string, const char* end, float* bounds);\n\n// Measures the specified multi-text string. Parameter bounds should be a pointer to float[4],\n// if the bounding box of the text should be returned. The bounds value are [xmin,ymin, xmax,ymax]\n// Measured values are returned in local coordinate space.\nvoid nvgTextBoxBounds(NVGcontext* ctx, float x, float y, float breakRowWidth, const char* string, const char* end, float* bounds);\n\n// Calculates the glyph x positions of the specified text. If end is specified only the sub-string will be used.\n// Measured values are returned in local coordinate space.\nint nvgTextGlyphPositions(NVGcontext* ctx, float x, float y, const char* string, const char* end, NVGglyphPosition* positions, int maxPositions);\n\n// Returns the vertical metrics based on the current text style.\n// Measured values are returned in local coordinate space.\nvoid nvgTextMetrics(NVGcontext* ctx, float* ascender, float* descender, float* lineh);\n\n// Breaks the specified text into lines. If end is specified only the sub-string will be used.\n// White space is stripped at the beginning of the rows, the text is split at word boundaries or when new-line characters are encountered.\n// Words longer than the max width are slit at nearest character (i.e. no hyphenation).\nint nvgTextBreakLines(NVGcontext* ctx, const char* string, const char* end, float breakRowWidth, NVGtextRow* rows, int maxRows);\n\n//\n// Internal Render API\n//\nenum NVGtexture {\n\tNVG_TEXTURE_ALPHA = 0x01,\n\tNVG_TEXTURE_RGBA = 0x02,\n};\n\nstruct NVGscissor {\n\tfloat xform[6];\n\tfloat extent[2];\n};\ntypedef struct NVGscissor NVGscissor;\n\nstruct NVGvertex {\n\tfloat x,y,u,v;\n};\ntypedef struct NVGvertex NVGvertex;\n\nstruct NVGpath {\n\tint first;\n\tint count;\n\tunsigned char closed;\n\tint nbevel;\n\tNVGvertex* fill;\n\tint nfill;\n\tNVGvertex* stroke;\n\tint nstroke;\n\tint winding;\n\tint convex;\n};\ntypedef struct NVGpath NVGpath;\n\nstruct NVGparams {\n\tvoid* userPtr;\n\tint edgeAntiAlias;\n\tint (*renderCreate)(void* uptr);\n\tint (*renderCreateTexture)(void* uptr, int type, int w, int h, int imageFlags, const unsigned char* data);\n\tint (*renderDeleteTexture)(void* uptr, int image);\n\tint (*renderUpdateTexture)(void* uptr, int image, int x, int y, int w, int h, const unsigned char* data);\n\tint (*renderGetTextureSize)(void* uptr, int image, int* w, int* h);\n\tvoid (*renderViewport)(void* uptr, int width, int height, float devicePixelRatio);\n\tvoid (*renderCancel)(void* uptr);\n\tvoid (*renderFlush)(void* uptr, NVGcompositeOperationState compositeOperation);\n\tvoid (*renderFill)(void* uptr, NVGpaint* paint, NVGscissor* scissor, float fringe, const float* bounds, const NVGpath* paths, int npaths);\n\tvoid (*renderStroke)(void* uptr, NVGpaint* paint, NVGscissor* scissor, float fringe, float strokeWidth, const NVGpath* paths, int npaths);\n\tvoid (*renderTriangles)(void* uptr, NVGpaint* paint, NVGscissor* scissor, const NVGvertex* verts, int nverts);\n\tvoid (*renderDelete)(void* uptr);\n};\ntypedef struct NVGparams NVGparams;\n\n// Constructor and destructor, called by the render back-end.\nNVGcontext* nvgCreateInternal(NVGparams* params);\nvoid nvgDeleteInternal(NVGcontext* ctx);\n\nNVGparams* nvgInternalParams(NVGcontext* ctx);\n\n// Debug function to dump cached path data.\nvoid nvgDebugDumpPathCache(NVGcontext* ctx);\n\n#ifdef _MSC_VER\n#pragma warning(pop)\n#endif\n\n#define NVG_NOTUSED(v) for (;;) { (void)(1 ? (void)0 : ( (void)(v) ) ); break; }\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // NANOVG_H\n"
  },
  {
    "path": "phonelibs/nanovg/nanovg_gl.h",
    "content": "//\n// Copyright (c) 2009-2013 Mikko Mononen memon@inside.org\n//\n// This software is provided 'as-is', without any express or implied\n// warranty.  In no event will the authors be held liable for any damages\n// arising from the use of this software.\n// Permission is granted to anyone to use this software for any purpose,\n// including commercial applications, and to alter it and redistribute it\n// freely, subject to the following restrictions:\n// 1. The origin of this software must not be misrepresented; you must not\n//    claim that you wrote the original software. If you use this software\n//    in a product, an acknowledgment in the product documentation would be\n//    appreciated but is not required.\n// 2. Altered source versions must be plainly marked as such, and must not be\n//    misrepresented as being the original software.\n// 3. This notice may not be removed or altered from any source distribution.\n//\n#ifndef NANOVG_GL_H\n#define NANOVG_GL_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Create flags\n\nenum NVGcreateFlags {\n\t// Flag indicating if geometry based anti-aliasing is used (may not be needed when using MSAA).\n\tNVG_ANTIALIAS \t\t= 1<<0,\n\t// Flag indicating if strokes should be drawn using stencil buffer. The rendering will be a little\n\t// slower, but path overlaps (i.e. self-intersecting or sharp turns) will be drawn just once.\n\tNVG_STENCIL_STROKES\t= 1<<1,\n\t// Flag indicating that additional debug checks are done.\n\tNVG_DEBUG \t\t\t= 1<<2,\n};\n\n#if defined NANOVG_GL2_IMPLEMENTATION\n#  define NANOVG_GL2 1\n#  define NANOVG_GL_IMPLEMENTATION 1\n#elif defined NANOVG_GL3_IMPLEMENTATION\n#  define NANOVG_GL3 1\n#  define NANOVG_GL_IMPLEMENTATION 1\n#  define NANOVG_GL_USE_UNIFORMBUFFER 1\n#elif defined NANOVG_GLES2_IMPLEMENTATION\n#  define NANOVG_GLES2 1\n#  define NANOVG_GL_IMPLEMENTATION 1\n#elif defined NANOVG_GLES3_IMPLEMENTATION\n#  define NANOVG_GLES3 1\n#  define NANOVG_GL_IMPLEMENTATION 1\n#endif\n\n#define NANOVG_GL_USE_STATE_FILTER (1)\n\n// Creates NanoVG contexts for different OpenGL (ES) versions.\n// Flags should be combination of the create flags above.\n\n#if defined NANOVG_GL2\n\nNVGcontext* nvgCreateGL2(int flags);\nvoid nvgDeleteGL2(NVGcontext* ctx);\n\nint nvglCreateImageFromHandleGL2(NVGcontext* ctx, GLuint textureId, int w, int h, int flags);\nGLuint nvglImageHandleGL2(NVGcontext* ctx, int image);\n\n#endif\n\n#if defined NANOVG_GL3\n\nNVGcontext* nvgCreateGL3(int flags);\nvoid nvgDeleteGL3(NVGcontext* ctx);\n\nint nvglCreateImageFromHandleGL3(NVGcontext* ctx, GLuint textureId, int w, int h, int flags);\nGLuint nvglImageHandleGL3(NVGcontext* ctx, int image);\n\n#endif\n\n#if defined NANOVG_GLES2\n\nNVGcontext* nvgCreateGLES2(int flags);\nvoid nvgDeleteGLES2(NVGcontext* ctx);\n\nint nvglCreateImageFromHandleGLES2(NVGcontext* ctx, GLuint textureId, int w, int h, int flags);\nGLuint nvglImageHandleGLES2(NVGcontext* ctx, int image);\n\n#endif\n\n#if defined NANOVG_GLES3\n\nNVGcontext* nvgCreateGLES3(int flags);\nvoid nvgDeleteGLES3(NVGcontext* ctx);\n\nint nvglCreateImageFromHandleGLES3(NVGcontext* ctx, GLuint textureId, int w, int h, int flags);\nGLuint nvglImageHandleGLES3(NVGcontext* ctx, int image);\n\n#endif\n\n// These are additional flags on top of NVGimageFlags.\nenum NVGimageFlagsGL {\n\tNVG_IMAGE_NODELETE\t\t\t= 1<<16,\t// Do not delete GL texture handle.\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* NANOVG_GL_H */\n\n#ifdef NANOVG_GL_IMPLEMENTATION\n\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <math.h>\n#include \"nanovg.h\"\n\nenum GLNVGuniformLoc {\n\tGLNVG_LOC_VIEWSIZE,\n\tGLNVG_LOC_TEX,\n\tGLNVG_LOC_FRAG,\n\tGLNVG_MAX_LOCS\n};\n\nenum GLNVGshaderType {\n\tNSVG_SHADER_FILLGRAD,\n\tNSVG_SHADER_FILLIMG,\n\tNSVG_SHADER_SIMPLE,\n\tNSVG_SHADER_IMG\n};\n\n#if NANOVG_GL_USE_UNIFORMBUFFER\nenum GLNVGuniformBindings {\n\tGLNVG_FRAG_BINDING = 0,\n};\n#endif\n\nstruct GLNVGshader {\n\tGLuint prog;\n\tGLuint frag;\n\tGLuint vert;\n\tGLint loc[GLNVG_MAX_LOCS];\n};\ntypedef struct GLNVGshader GLNVGshader;\n\nstruct GLNVGtexture {\n\tint id;\n\tGLuint tex;\n\tint width, height;\n\tint type;\n\tint flags;\n};\ntypedef struct GLNVGtexture GLNVGtexture;\n\nenum GLNVGcallType {\n\tGLNVG_NONE = 0,\n\tGLNVG_FILL,\n\tGLNVG_CONVEXFILL,\n\tGLNVG_STROKE,\n\tGLNVG_TRIANGLES,\n};\n\nstruct GLNVGcall {\n\tint type;\n\tint image;\n\tint pathOffset;\n\tint pathCount;\n\tint triangleOffset;\n\tint triangleCount;\n\tint uniformOffset;\n};\ntypedef struct GLNVGcall GLNVGcall;\n\nstruct GLNVGpath {\n\tint fillOffset;\n\tint fillCount;\n\tint strokeOffset;\n\tint strokeCount;\n};\ntypedef struct GLNVGpath GLNVGpath;\n\nstruct GLNVGfragUniforms {\n\t#if NANOVG_GL_USE_UNIFORMBUFFER\n\t\tfloat scissorMat[12]; // matrices are actually 3 vec4s\n\t\tfloat paintMat[12];\n\t\tstruct NVGcolor innerCol;\n\t\tstruct NVGcolor outerCol;\n\t\tfloat scissorExt[2];\n\t\tfloat scissorScale[2];\n\t\tfloat extent[2];\n\t\tfloat radius;\n\t\tfloat feather;\n\t\tfloat strokeMult;\n\t\tfloat strokeThr;\n\t\tint texType;\n\t\tint type;\n\t#else\n\t\t// note: after modifying layout or size of uniform array,\n\t\t// don't forget to also update the fragment shader source!\n\t\t#define NANOVG_GL_UNIFORMARRAY_SIZE 11\n\t\tunion {\n\t\t\tstruct {\n\t\t\t\tfloat scissorMat[12]; // matrices are actually 3 vec4s\n\t\t\t\tfloat paintMat[12];\n\t\t\t\tstruct NVGcolor innerCol;\n\t\t\t\tstruct NVGcolor outerCol;\n\t\t\t\tfloat scissorExt[2];\n\t\t\t\tfloat scissorScale[2];\n\t\t\t\tfloat extent[2];\n\t\t\t\tfloat radius;\n\t\t\t\tfloat feather;\n\t\t\t\tfloat strokeMult;\n\t\t\t\tfloat strokeThr;\n\t\t\t\tfloat texType;\n\t\t\t\tfloat type;\n\t\t\t};\n\t\t\tfloat uniformArray[NANOVG_GL_UNIFORMARRAY_SIZE][4];\n\t\t};\n\t#endif\n};\ntypedef struct GLNVGfragUniforms GLNVGfragUniforms;\n\nstruct GLNVGcontext {\n\tGLNVGshader shader;\n\tGLNVGtexture* textures;\n\tfloat view[2];\n\tint ntextures;\n\tint ctextures;\n\tint textureId;\n\tGLuint vertBuf;\n#if defined NANOVG_GL3\n\tGLuint vertArr;\n#endif\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\tGLuint fragBuf;\n#endif\n\tint fragSize;\n\tint flags;\n\n\t// Per frame buffers\n\tGLNVGcall* calls;\n\tint ccalls;\n\tint ncalls;\n\tGLNVGpath* paths;\n\tint cpaths;\n\tint npaths;\n\tstruct NVGvertex* verts;\n\tint cverts;\n\tint nverts;\n\tunsigned char* uniforms;\n\tint cuniforms;\n\tint nuniforms;\n\n\t// cached state\n\t#if NANOVG_GL_USE_STATE_FILTER\n\tGLuint boundTexture;\n\tGLuint stencilMask;\n\tGLenum stencilFunc;\n\tGLint stencilFuncRef;\n\tGLuint stencilFuncMask;\n\t#endif\n};\ntypedef struct GLNVGcontext GLNVGcontext;\n\nstatic int glnvg__maxi(int a, int b) { return a > b ? a : b; }\n\n#ifdef NANOVG_GLES2\nstatic unsigned int glnvg__nearestPow2(unsigned int num)\n{\n\tunsigned n = num > 0 ? num - 1 : 0;\n\tn |= n >> 1;\n\tn |= n >> 2;\n\tn |= n >> 4;\n\tn |= n >> 8;\n\tn |= n >> 16;\n\tn++;\n\treturn n;\n}\n#endif\n\nstatic void glnvg__bindTexture(GLNVGcontext* gl, GLuint tex)\n{\n#if NANOVG_GL_USE_STATE_FILTER\n\tif (gl->boundTexture != tex) {\n\t\tgl->boundTexture = tex;\n\t\tglBindTexture(GL_TEXTURE_2D, tex);\n\t}\n#else\n\tglBindTexture(GL_TEXTURE_2D, tex);\n#endif\n}\n\nstatic void glnvg__stencilMask(GLNVGcontext* gl, GLuint mask)\n{\n#if NANOVG_GL_USE_STATE_FILTER\n\tif (gl->stencilMask != mask) {\n\t\tgl->stencilMask = mask;\n\t\tglStencilMask(mask);\n\t}\n#else\n\tglStencilMask(mask);\n#endif\n}\n\nstatic void glnvg__stencilFunc(GLNVGcontext* gl, GLenum func, GLint ref, GLuint mask)\n{\n#if NANOVG_GL_USE_STATE_FILTER\n\tif ((gl->stencilFunc != func) ||\n\t\t(gl->stencilFuncRef != ref) ||\n\t\t(gl->stencilFuncMask != mask)) {\n\n\t\tgl->stencilFunc = func;\n\t\tgl->stencilFuncRef = ref;\n\t\tgl->stencilFuncMask = mask;\n\t\tglStencilFunc(func, ref, mask);\n\t}\n#else\n\tglStencilFunc(func, ref, mask);\n#endif\n}\n\nstatic GLNVGtexture* glnvg__allocTexture(GLNVGcontext* gl)\n{\n\tGLNVGtexture* tex = NULL;\n\tint i;\n\n\tfor (i = 0; i < gl->ntextures; i++) {\n\t\tif (gl->textures[i].id == 0) {\n\t\t\ttex = &gl->textures[i];\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (tex == NULL) {\n\t\tif (gl->ntextures+1 > gl->ctextures) {\n\t\t\tGLNVGtexture* textures;\n\t\t\tint ctextures = glnvg__maxi(gl->ntextures+1, 4) +  gl->ctextures/2; // 1.5x Overallocate\n\t\t\ttextures = (GLNVGtexture*)realloc(gl->textures, sizeof(GLNVGtexture)*ctextures);\n\t\t\tif (textures == NULL) return NULL;\n\t\t\tgl->textures = textures;\n\t\t\tgl->ctextures = ctextures;\n\t\t}\n\t\ttex = &gl->textures[gl->ntextures++];\n\t}\n\n\tmemset(tex, 0, sizeof(*tex));\n\ttex->id = ++gl->textureId;\n\n\treturn tex;\n}\n\nstatic GLNVGtexture* glnvg__findTexture(GLNVGcontext* gl, int id)\n{\n\tint i;\n\tfor (i = 0; i < gl->ntextures; i++)\n\t\tif (gl->textures[i].id == id)\n\t\t\treturn &gl->textures[i];\n\treturn NULL;\n}\n\nstatic int glnvg__deleteTexture(GLNVGcontext* gl, int id)\n{\n\tint i;\n\tfor (i = 0; i < gl->ntextures; i++) {\n\t\tif (gl->textures[i].id == id) {\n\t\t\tif (gl->textures[i].tex != 0 && (gl->textures[i].flags & NVG_IMAGE_NODELETE) == 0)\n\t\t\t\tglDeleteTextures(1, &gl->textures[i].tex);\n\t\t\tmemset(&gl->textures[i], 0, sizeof(gl->textures[i]));\n\t\t\treturn 1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic void glnvg__dumpShaderError(GLuint shader, const char* name, const char* type)\n{\n\tGLchar str[512+1];\n\tGLsizei len = 0;\n\tglGetShaderInfoLog(shader, 512, &len, str);\n\tif (len > 512) len = 512;\n\tstr[len] = '\\0';\n\tprintf(\"Shader %s/%s error:\\n%s\\n\", name, type, str);\n}\n\nstatic void glnvg__dumpProgramError(GLuint prog, const char* name)\n{\n\tGLchar str[512+1];\n\tGLsizei len = 0;\n\tglGetProgramInfoLog(prog, 512, &len, str);\n\tif (len > 512) len = 512;\n\tstr[len] = '\\0';\n\tprintf(\"Program %s error:\\n%s\\n\", name, str);\n}\n\nstatic void glnvg__checkError(GLNVGcontext* gl, const char* str)\n{\n\tGLenum err;\n\tif ((gl->flags & NVG_DEBUG) == 0) return;\n\terr = glGetError();\n\tif (err != GL_NO_ERROR) {\n\t\tprintf(\"Error %08x after %s\\n\", err, str);\n\t\treturn;\n\t}\n}\n\nstatic int glnvg__createShader(GLNVGshader* shader, const char* name, const char* header, const char* opts, const char* vshader, const char* fshader)\n{\n\tGLint status;\n\tGLuint prog, vert, frag;\n\tconst char* str[3];\n\tstr[0] = header;\n\tstr[1] = opts != NULL ? opts : \"\";\n\n\tmemset(shader, 0, sizeof(*shader));\n\n\tprog = glCreateProgram();\n\tvert = glCreateShader(GL_VERTEX_SHADER);\n\tfrag = glCreateShader(GL_FRAGMENT_SHADER);\n\tstr[2] = vshader;\n\tglShaderSource(vert, 3, str, 0);\n\tstr[2] = fshader;\n\tglShaderSource(frag, 3, str, 0);\n\n\tglCompileShader(vert);\n\tglGetShaderiv(vert, GL_COMPILE_STATUS, &status);\n\tif (status != GL_TRUE) {\n\t\tglnvg__dumpShaderError(vert, name, \"vert\");\n\t\treturn 0;\n\t}\n\n\tglCompileShader(frag);\n\tglGetShaderiv(frag, GL_COMPILE_STATUS, &status);\n\tif (status != GL_TRUE) {\n\t\tglnvg__dumpShaderError(frag, name, \"frag\");\n\t\treturn 0;\n\t}\n\n\tglAttachShader(prog, vert);\n\tglAttachShader(prog, frag);\n\n\tglBindAttribLocation(prog, 0, \"vertex\");\n\tglBindAttribLocation(prog, 1, \"tcoord\");\n\n\tglLinkProgram(prog);\n\tglGetProgramiv(prog, GL_LINK_STATUS, &status);\n\tif (status != GL_TRUE) {\n\t\tglnvg__dumpProgramError(prog, name);\n\t\treturn 0;\n\t}\n\n\tshader->prog = prog;\n\tshader->vert = vert;\n\tshader->frag = frag;\n\n\treturn 1;\n}\n\nstatic void glnvg__deleteShader(GLNVGshader* shader)\n{\n\tif (shader->prog != 0)\n\t\tglDeleteProgram(shader->prog);\n\tif (shader->vert != 0)\n\t\tglDeleteShader(shader->vert);\n\tif (shader->frag != 0)\n\t\tglDeleteShader(shader->frag);\n}\n\nstatic void glnvg__getUniforms(GLNVGshader* shader)\n{\n\tshader->loc[GLNVG_LOC_VIEWSIZE] = glGetUniformLocation(shader->prog, \"viewSize\");\n\tshader->loc[GLNVG_LOC_TEX] = glGetUniformLocation(shader->prog, \"tex\");\n\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\tshader->loc[GLNVG_LOC_FRAG] = glGetUniformBlockIndex(shader->prog, \"frag\");\n#else\n\tshader->loc[GLNVG_LOC_FRAG] = glGetUniformLocation(shader->prog, \"frag\");\n#endif\n}\n\nstatic int glnvg__renderCreate(void* uptr)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tint align = 4;\n\n\t// TODO: mediump float may not be enough for GLES2 in iOS.\n\t// see the following discussion: https://github.com/memononen/nanovg/issues/46\n\tstatic const char* shaderHeader =\n#if defined NANOVG_GL2\n\t\t\"#define NANOVG_GL2 1\\n\"\n#elif defined NANOVG_GL3\n\t\t\"#version 150 core\\n\"\n\t\t\"#define NANOVG_GL3 1\\n\"\n#elif defined NANOVG_GLES2\n\t\t\"#version 100\\n\"\n\t\t\"#define NANOVG_GL2 1\\n\"\n#elif defined NANOVG_GLES3\n\t\t\"#version 300 es\\n\"\n\t\t\"#define NANOVG_GL3 1\\n\"\n#endif\n\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\t\"#define USE_UNIFORMBUFFER 1\\n\"\n#else\n\t\"#define UNIFORMARRAY_SIZE 11\\n\"\n#endif\n\t\"\\n\";\n\n\tstatic const char* fillVertShader =\n\t\t\"#ifdef NANOVG_GL3\\n\"\n\t\t\"\tuniform vec2 viewSize;\\n\"\n\t\t\"\tin vec2 vertex;\\n\"\n\t\t\"\tin vec2 tcoord;\\n\"\n\t\t\"\tout vec2 ftcoord;\\n\"\n\t\t\"\tout vec2 fpos;\\n\"\n\t\t\"#else\\n\"\n\t\t\"\tuniform vec2 viewSize;\\n\"\n\t\t\"\tattribute vec2 vertex;\\n\"\n\t\t\"\tattribute vec2 tcoord;\\n\"\n\t\t\"\tvarying vec2 ftcoord;\\n\"\n\t\t\"\tvarying vec2 fpos;\\n\"\n\t\t\"#endif\\n\"\n\t\t\"void main(void) {\\n\"\n\t\t\"\tftcoord = tcoord;\\n\"\n\t\t\"\tfpos = vertex;\\n\"\n\t\t\"\tgl_Position = vec4(2.0*vertex.x/viewSize.x - 1.0, 1.0 - 2.0*vertex.y/viewSize.y, 0, 1);\\n\"\n\t\t\"}\\n\";\n\n\tstatic const char* fillFragShader =\n\t\t\"#ifdef GL_ES\\n\"\n\t\t\"#if defined(GL_FRAGMENT_PRECISION_HIGH) || defined(NANOVG_GL3)\\n\"\n\t\t\" precision highp float;\\n\"\n\t\t\"#else\\n\"\n\t\t\" precision mediump float;\\n\"\n\t\t\"#endif\\n\"\n\t\t\"#endif\\n\"\n\t\t\"#ifdef NANOVG_GL3\\n\"\n\t\t\"#ifdef USE_UNIFORMBUFFER\\n\"\n\t\t\"\tlayout(std140) uniform frag {\\n\"\n\t\t\"\t\tmat3 scissorMat;\\n\"\n\t\t\"\t\tmat3 paintMat;\\n\"\n\t\t\"\t\tvec4 innerCol;\\n\"\n\t\t\"\t\tvec4 outerCol;\\n\"\n\t\t\"\t\tvec2 scissorExt;\\n\"\n\t\t\"\t\tvec2 scissorScale;\\n\"\n\t\t\"\t\tvec2 extent;\\n\"\n\t\t\"\t\tfloat radius;\\n\"\n\t\t\"\t\tfloat feather;\\n\"\n\t\t\"\t\tfloat strokeMult;\\n\"\n\t\t\"\t\tfloat strokeThr;\\n\"\n\t\t\"\t\tint texType;\\n\"\n\t\t\"\t\tint type;\\n\"\n\t\t\"\t};\\n\"\n\t\t\"#else\\n\" // NANOVG_GL3 && !USE_UNIFORMBUFFER\n\t\t\"\tuniform vec4 frag[UNIFORMARRAY_SIZE];\\n\"\n\t\t\"#endif\\n\"\n\t\t\"\tuniform sampler2D tex;\\n\"\n\t\t\"\tin vec2 ftcoord;\\n\"\n\t\t\"\tin vec2 fpos;\\n\"\n\t\t\"\tout vec4 outColor;\\n\"\n\t\t\"#else\\n\" // !NANOVG_GL3\n\t\t\"\tuniform vec4 frag[UNIFORMARRAY_SIZE];\\n\"\n\t\t\"\tuniform sampler2D tex;\\n\"\n\t\t\"\tvarying vec2 ftcoord;\\n\"\n\t\t\"\tvarying vec2 fpos;\\n\"\n\t\t\"#endif\\n\"\n\t\t\"#ifndef USE_UNIFORMBUFFER\\n\"\n\t\t\"\t#define scissorMat mat3(frag[0].xyz, frag[1].xyz, frag[2].xyz)\\n\"\n\t\t\"\t#define paintMat mat3(frag[3].xyz, frag[4].xyz, frag[5].xyz)\\n\"\n\t\t\"\t#define innerCol frag[6]\\n\"\n\t\t\"\t#define outerCol frag[7]\\n\"\n\t\t\"\t#define scissorExt frag[8].xy\\n\"\n\t\t\"\t#define scissorScale frag[8].zw\\n\"\n\t\t\"\t#define extent frag[9].xy\\n\"\n\t\t\"\t#define radius frag[9].z\\n\"\n\t\t\"\t#define feather frag[9].w\\n\"\n\t\t\"\t#define strokeMult frag[10].x\\n\"\n\t\t\"\t#define strokeThr frag[10].y\\n\"\n\t\t\"\t#define texType int(frag[10].z)\\n\"\n\t\t\"\t#define type int(frag[10].w)\\n\"\n\t\t\"#endif\\n\"\n\t\t\"\\n\"\n\t\t\"float sdroundrect(vec2 pt, vec2 ext, float rad) {\\n\"\n\t\t\"\tvec2 ext2 = ext - vec2(rad,rad);\\n\"\n\t\t\"\tvec2 d = abs(pt) - ext2;\\n\"\n\t\t\"\treturn min(max(d.x,d.y),0.0) + length(max(d,0.0)) - rad;\\n\"\n\t\t\"}\\n\"\n\t\t\"\\n\"\n\t\t\"// Scissoring\\n\"\n\t\t\"float scissorMask(vec2 p) {\\n\"\n\t\t\"\tvec2 sc = (abs((scissorMat * vec3(p,1.0)).xy) - scissorExt);\\n\"\n\t\t\"\tsc = vec2(0.5,0.5) - sc * scissorScale;\\n\"\n\t\t\"\treturn clamp(sc.x,0.0,1.0) * clamp(sc.y,0.0,1.0);\\n\"\n\t\t\"}\\n\"\n\t\t\"#ifdef EDGE_AA\\n\"\n\t\t\"// Stroke - from [0..1] to clipped pyramid, where the slope is 1px.\\n\"\n\t\t\"float strokeMask() {\\n\"\n\t\t\"\treturn min(1.0, (1.0-abs(ftcoord.x*2.0-1.0))*strokeMult) * min(1.0, ftcoord.y);\\n\"\n\t\t\"}\\n\"\n\t\t\"#endif\\n\"\n\t\t\"\\n\"\n\t\t\"void main(void) {\\n\"\n\t\t\"   vec4 result;\\n\"\n\t\t\"\tfloat scissor = scissorMask(fpos);\\n\"\n\t\t\"#ifdef EDGE_AA\\n\"\n\t\t\"\tfloat strokeAlpha = strokeMask();\\n\"\n\t\t\"#else\\n\"\n\t\t\"\tfloat strokeAlpha = 1.0;\\n\"\n\t\t\"#endif\\n\"\n\t\t\"\tif (type == 0) {\t\t\t// Gradient\\n\"\n\t\t\"\t\t// Calculate gradient color using box gradient\\n\"\n\t\t\"\t\tvec2 pt = (paintMat * vec3(fpos,1.0)).xy;\\n\"\n\t\t\"\t\tfloat d = clamp((sdroundrect(pt, extent, radius) + feather*0.5) / feather, 0.0, 1.0);\\n\"\n\t\t\"\t\tvec4 color = mix(innerCol,outerCol,d);\\n\"\n\t\t\"\t\t// Combine alpha\\n\"\n\t\t\"\t\tcolor *= strokeAlpha * scissor;\\n\"\n\t\t\"\t\tresult = color;\\n\"\n\t\t\"\t} else if (type == 1) {\t\t// Image\\n\"\n\t\t\"\t\t// Calculate color fron texture\\n\"\n\t\t\"\t\tvec2 pt = (paintMat * vec3(fpos,1.0)).xy / extent;\\n\"\n\t\t\"#ifdef NANOVG_GL3\\n\"\n\t\t\"\t\tvec4 color = texture(tex, pt);\\n\"\n\t\t\"#else\\n\"\n\t\t\"\t\tvec4 color = texture2D(tex, pt);\\n\"\n\t\t\"#endif\\n\"\n\t\t\"\t\tif (texType == 1) color = vec4(color.xyz*color.w,color.w);\"\n\t\t\"\t\tif (texType == 2) color = vec4(color.x);\"\n\t\t\"\t\t// Apply color tint and alpha.\\n\"\n\t\t\"\t\tcolor *= innerCol;\\n\"\n\t\t\"\t\t// Combine alpha\\n\"\n\t\t\"\t\tcolor *= strokeAlpha * scissor;\\n\"\n\t\t\"\t\tresult = color;\\n\"\n\t\t\"\t} else if (type == 2) {\t\t// Stencil fill\\n\"\n\t\t\"\t\tresult = vec4(1,1,1,1);\\n\"\n\t\t\"\t} else if (type == 3) {\t\t// Textured tris\\n\"\n\t\t\"#ifdef NANOVG_GL3\\n\"\n\t\t\"\t\tvec4 color = texture(tex, ftcoord);\\n\"\n\t\t\"#else\\n\"\n\t\t\"\t\tvec4 color = texture2D(tex, ftcoord);\\n\"\n\t\t\"#endif\\n\"\n\t\t\"\t\tif (texType == 1) color = vec4(color.xyz*color.w,color.w);\"\n\t\t\"\t\tif (texType == 2) color = vec4(color.x);\"\n\t\t\"\t\tcolor *= scissor;\\n\"\n\t\t\"\t\tresult = color * innerCol;\\n\"\n\t\t\"\t}\\n\"\n\t\t\"#ifdef EDGE_AA\\n\"\n\t\t\"\tif (strokeAlpha < strokeThr) discard;\\n\"\n\t\t\"#endif\\n\"\n\t\t\"#ifdef NANOVG_GL3\\n\"\n\t\t\"\toutColor = result;\\n\"\n\t\t\"#else\\n\"\n\t\t\"\tgl_FragColor = result;\\n\"\n\t\t\"#endif\\n\"\n\t\t\"}\\n\";\n\n\tglnvg__checkError(gl, \"init\");\n\n\tif (gl->flags & NVG_ANTIALIAS) {\n\t\tif (glnvg__createShader(&gl->shader, \"shader\", shaderHeader, \"#define EDGE_AA 1\\n\", fillVertShader, fillFragShader) == 0)\n\t\t\treturn 0;\n\t} else {\n\t\tif (glnvg__createShader(&gl->shader, \"shader\", shaderHeader, NULL, fillVertShader, fillFragShader) == 0)\n\t\t\treturn 0;\n\t}\n\n\tglnvg__checkError(gl, \"uniform locations\");\n\tglnvg__getUniforms(&gl->shader);\n\n\t// Create dynamic vertex array\n#if defined NANOVG_GL3\n\tglGenVertexArrays(1, &gl->vertArr);\n#endif\n\tglGenBuffers(1, &gl->vertBuf);\n\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\t// Create UBOs\n\tglUniformBlockBinding(gl->shader.prog, gl->shader.loc[GLNVG_LOC_FRAG], GLNVG_FRAG_BINDING);\n\tglGenBuffers(1, &gl->fragBuf);\n\tglGetIntegerv(GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT, &align);\n#endif\n\tgl->fragSize = sizeof(GLNVGfragUniforms) + align - sizeof(GLNVGfragUniforms) % align;\n\n\tglnvg__checkError(gl, \"create done\");\n\n\tglFinish();\n\n\treturn 1;\n}\n\nstatic int glnvg__renderCreateTexture(void* uptr, int type, int w, int h, int imageFlags, const unsigned char* data)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tGLNVGtexture* tex = glnvg__allocTexture(gl);\n\n\tif (tex == NULL) return 0;\n\n#ifdef NANOVG_GLES2\n\t// Check for non-power of 2.\n\tif (glnvg__nearestPow2(w) != (unsigned int)w || glnvg__nearestPow2(h) != (unsigned int)h) {\n\t\t// No repeat\n\t\tif ((imageFlags & NVG_IMAGE_REPEATX) != 0 || (imageFlags & NVG_IMAGE_REPEATY) != 0) {\n\t\t\tprintf(\"Repeat X/Y is not supported for non power-of-two textures (%d x %d)\\n\", w, h);\n\t\t\timageFlags &= ~(NVG_IMAGE_REPEATX | NVG_IMAGE_REPEATY);\n\t\t}\n\t\t// No mips.\n\t\tif (imageFlags & NVG_IMAGE_GENERATE_MIPMAPS) {\n\t\t\tprintf(\"Mip-maps is not support for non power-of-two textures (%d x %d)\\n\", w, h);\n\t\t\timageFlags &= ~NVG_IMAGE_GENERATE_MIPMAPS;\n\t\t}\n\t}\n#endif\n\n\tglGenTextures(1, &tex->tex);\n\ttex->width = w;\n\ttex->height = h;\n\ttex->type = type;\n\ttex->flags = imageFlags;\n\tglnvg__bindTexture(gl, tex->tex);\n\n\tglPixelStorei(GL_UNPACK_ALIGNMENT,1);\n#ifndef NANOVG_GLES2\n\tglPixelStorei(GL_UNPACK_ROW_LENGTH, tex->width);\n\tglPixelStorei(GL_UNPACK_SKIP_PIXELS, 0);\n\tglPixelStorei(GL_UNPACK_SKIP_ROWS, 0);\n#endif\n\n#if defined (NANOVG_GL2)\n\t// GL 1.4 and later has support for generating mipmaps using a tex parameter.\n\tif (imageFlags & NVG_IMAGE_GENERATE_MIPMAPS) {\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_GENERATE_MIPMAP, GL_TRUE);\n\t}\n#endif\n\n\tif (type == NVG_TEXTURE_RGBA)\n\t\tglTexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, w, h, 0, GL_RGBA, GL_UNSIGNED_BYTE, data);\n\telse\n#if defined(NANOVG_GLES2)\n\t\tglTexImage2D(GL_TEXTURE_2D, 0, GL_LUMINANCE, w, h, 0, GL_LUMINANCE, GL_UNSIGNED_BYTE, data);\n#elif defined(NANOVG_GLES3)\n\t\tglTexImage2D(GL_TEXTURE_2D, 0, GL_R8, w, h, 0, GL_RED, GL_UNSIGNED_BYTE, data);\n#else\n\t\tglTexImage2D(GL_TEXTURE_2D, 0, GL_RED, w, h, 0, GL_RED, GL_UNSIGNED_BYTE, data);\n#endif\n\n\tif (imageFlags & NVG_IMAGE_GENERATE_MIPMAPS) {\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR_MIPMAP_LINEAR);\n\t} else {\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR);\n\t}\n\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR);\n\n\tif (imageFlags & NVG_IMAGE_REPEATX)\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_REPEAT);\n\telse\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE);\n\n\tif (imageFlags & NVG_IMAGE_REPEATY)\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_REPEAT);\n\telse\n\t\tglTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE);\n\n\tglPixelStorei(GL_UNPACK_ALIGNMENT, 4);\n#ifndef NANOVG_GLES2\n\tglPixelStorei(GL_UNPACK_ROW_LENGTH, 0);\n\tglPixelStorei(GL_UNPACK_SKIP_PIXELS, 0);\n\tglPixelStorei(GL_UNPACK_SKIP_ROWS, 0);\n#endif\n\n\t// The new way to build mipmaps on GLES and GL3\n#if !defined(NANOVG_GL2)\n\tif (imageFlags & NVG_IMAGE_GENERATE_MIPMAPS) {\n\t\tglGenerateMipmap(GL_TEXTURE_2D);\n\t}\n#endif\n\n\tglnvg__checkError(gl, \"create tex\");\n\tglnvg__bindTexture(gl, 0);\n\n\treturn tex->id;\n}\n\n\nstatic int glnvg__renderDeleteTexture(void* uptr, int image)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\treturn glnvg__deleteTexture(gl, image);\n}\n\nstatic int glnvg__renderUpdateTexture(void* uptr, int image, int x, int y, int w, int h, const unsigned char* data)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tGLNVGtexture* tex = glnvg__findTexture(gl, image);\n\n\tif (tex == NULL) return 0;\n\tglnvg__bindTexture(gl, tex->tex);\n\n\tglPixelStorei(GL_UNPACK_ALIGNMENT,1);\n\n#ifndef NANOVG_GLES2\n\tglPixelStorei(GL_UNPACK_ROW_LENGTH, tex->width);\n\tglPixelStorei(GL_UNPACK_SKIP_PIXELS, x);\n\tglPixelStorei(GL_UNPACK_SKIP_ROWS, y);\n#else\n\t// No support for all of skip, need to update a whole row at a time.\n\tif (tex->type == NVG_TEXTURE_RGBA)\n\t\tdata += y*tex->width*4;\n\telse\n\t\tdata += y*tex->width;\n\tx = 0;\n\tw = tex->width;\n#endif\n\n\tif (tex->type == NVG_TEXTURE_RGBA)\n\t\tglTexSubImage2D(GL_TEXTURE_2D, 0, x,y, w,h, GL_RGBA, GL_UNSIGNED_BYTE, data);\n\telse\n#ifdef NANOVG_GLES2\n\t\tglTexSubImage2D(GL_TEXTURE_2D, 0, x,y, w,h, GL_LUMINANCE, GL_UNSIGNED_BYTE, data);\n#else\n\t\tglTexSubImage2D(GL_TEXTURE_2D, 0, x,y, w,h, GL_RED, GL_UNSIGNED_BYTE, data);\n#endif\n\n\tglPixelStorei(GL_UNPACK_ALIGNMENT, 4);\n#ifndef NANOVG_GLES2\n\tglPixelStorei(GL_UNPACK_ROW_LENGTH, 0);\n\tglPixelStorei(GL_UNPACK_SKIP_PIXELS, 0);\n\tglPixelStorei(GL_UNPACK_SKIP_ROWS, 0);\n#endif\n\n\tglnvg__bindTexture(gl, 0);\n\n\treturn 1;\n}\n\nstatic int glnvg__renderGetTextureSize(void* uptr, int image, int* w, int* h)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tGLNVGtexture* tex = glnvg__findTexture(gl, image);\n\tif (tex == NULL) return 0;\n\t*w = tex->width;\n\t*h = tex->height;\n\treturn 1;\n}\n\nstatic void glnvg__xformToMat3x4(float* m3, float* t)\n{\n\tm3[0] = t[0];\n\tm3[1] = t[1];\n\tm3[2] = 0.0f;\n\tm3[3] = 0.0f;\n\tm3[4] = t[2];\n\tm3[5] = t[3];\n\tm3[6] = 0.0f;\n\tm3[7] = 0.0f;\n\tm3[8] = t[4];\n\tm3[9] = t[5];\n\tm3[10] = 1.0f;\n\tm3[11] = 0.0f;\n}\n\nstatic NVGcolor glnvg__premulColor(NVGcolor c)\n{\n\tc.r *= c.a;\n\tc.g *= c.a;\n\tc.b *= c.a;\n\treturn c;\n}\n\nstatic int glnvg__convertPaint(GLNVGcontext* gl, GLNVGfragUniforms* frag, NVGpaint* paint,\n\t\t\t\t\t\t\t   NVGscissor* scissor, float width, float fringe, float strokeThr)\n{\n\tGLNVGtexture* tex = NULL;\n\tfloat invxform[6];\n\n\tmemset(frag, 0, sizeof(*frag));\n\n\tfrag->innerCol = glnvg__premulColor(paint->innerColor);\n\tfrag->outerCol = glnvg__premulColor(paint->outerColor);\n\n\tif (scissor->extent[0] < -0.5f || scissor->extent[1] < -0.5f) {\n\t\tmemset(frag->scissorMat, 0, sizeof(frag->scissorMat));\n\t\tfrag->scissorExt[0] = 1.0f;\n\t\tfrag->scissorExt[1] = 1.0f;\n\t\tfrag->scissorScale[0] = 1.0f;\n\t\tfrag->scissorScale[1] = 1.0f;\n\t} else {\n\t\tnvgTransformInverse(invxform, scissor->xform);\n\t\tglnvg__xformToMat3x4(frag->scissorMat, invxform);\n\t\tfrag->scissorExt[0] = scissor->extent[0];\n\t\tfrag->scissorExt[1] = scissor->extent[1];\n\t\tfrag->scissorScale[0] = sqrtf(scissor->xform[0]*scissor->xform[0] + scissor->xform[2]*scissor->xform[2]) / fringe;\n\t\tfrag->scissorScale[1] = sqrtf(scissor->xform[1]*scissor->xform[1] + scissor->xform[3]*scissor->xform[3]) / fringe;\n\t}\n\n\tmemcpy(frag->extent, paint->extent, sizeof(frag->extent));\n\tfrag->strokeMult = (width*0.5f + fringe*0.5f) / fringe;\n\tfrag->strokeThr = strokeThr;\n\n\tif (paint->image != 0) {\n\t\ttex = glnvg__findTexture(gl, paint->image);\n\t\tif (tex == NULL) return 0;\n\t\tif ((tex->flags & NVG_IMAGE_FLIPY) != 0) {\n\t\t\tfloat m1[6], m2[6];\n\t\t\tnvgTransformTranslate(m1, 0.0f, frag->extent[1] * 0.5f);\n\t\t\tnvgTransformMultiply(m1, paint->xform);\n\t\t\tnvgTransformScale(m2, 1.0f, -1.0f);\n\t\t\tnvgTransformMultiply(m2, m1);\n\t\t\tnvgTransformTranslate(m1, 0.0f, -frag->extent[1] * 0.5f);\n\t\t\tnvgTransformMultiply(m1, m2);\n\t\t\tnvgTransformInverse(invxform, m1);\n\t\t} else {\n\t\t\tnvgTransformInverse(invxform, paint->xform);\n\t\t}\n\t\tfrag->type = NSVG_SHADER_FILLIMG;\n\n\t\tif (tex->type == NVG_TEXTURE_RGBA)\n\t\t\tfrag->texType = (tex->flags & NVG_IMAGE_PREMULTIPLIED) ? 0 : 1;\n\t\telse\n\t\t\tfrag->texType = 2;\n//\t\tprintf(\"frag->texType = %d\\n\", frag->texType);\n\t} else {\n\t\tfrag->type = NSVG_SHADER_FILLGRAD;\n\t\tfrag->radius = paint->radius;\n\t\tfrag->feather = paint->feather;\n\t\tnvgTransformInverse(invxform, paint->xform);\n\t}\n\n\tglnvg__xformToMat3x4(frag->paintMat, invxform);\n\n\treturn 1;\n}\n\nstatic GLNVGfragUniforms* nvg__fragUniformPtr(GLNVGcontext* gl, int i);\n\nstatic void glnvg__setUniforms(GLNVGcontext* gl, int uniformOffset, int image)\n{\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\tglBindBufferRange(GL_UNIFORM_BUFFER, GLNVG_FRAG_BINDING, gl->fragBuf, uniformOffset, sizeof(GLNVGfragUniforms));\n#else\n\tGLNVGfragUniforms* frag = nvg__fragUniformPtr(gl, uniformOffset);\n\tglUniform4fv(gl->shader.loc[GLNVG_LOC_FRAG], NANOVG_GL_UNIFORMARRAY_SIZE, &(frag->uniformArray[0][0]));\n#endif\n\n\tif (image != 0) {\n\t\tGLNVGtexture* tex = glnvg__findTexture(gl, image);\n\t\tglnvg__bindTexture(gl, tex != NULL ? tex->tex : 0);\n\t\tglnvg__checkError(gl, \"tex paint tex\");\n\t} else {\n\t\tglnvg__bindTexture(gl, 0);\n\t}\n}\n\nstatic void glnvg__renderViewport(void* uptr, int width, int height, float devicePixelRatio)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tgl->view[0] = (float)width;\n\tgl->view[1] = (float)height;\n}\n\nstatic void glnvg__fill(GLNVGcontext* gl, GLNVGcall* call)\n{\n\tGLNVGpath* paths = &gl->paths[call->pathOffset];\n\tint i, npaths = call->pathCount;\n\n\t// Draw shapes\n\tglEnable(GL_STENCIL_TEST);\n\tglnvg__stencilMask(gl, 0xff);\n\tglnvg__stencilFunc(gl, GL_ALWAYS, 0, 0xff);\n\tglColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE);\n\n\t// set bindpoint for solid loc\n\tglnvg__setUniforms(gl, call->uniformOffset, 0);\n\tglnvg__checkError(gl, \"fill simple\");\n\n\tglStencilOpSeparate(GL_FRONT, GL_KEEP, GL_KEEP, GL_INCR_WRAP);\n\tglStencilOpSeparate(GL_BACK, GL_KEEP, GL_KEEP, GL_DECR_WRAP);\n\tglDisable(GL_CULL_FACE);\n\tfor (i = 0; i < npaths; i++)\n\t\tglDrawArrays(GL_TRIANGLE_FAN, paths[i].fillOffset, paths[i].fillCount);\n\tglEnable(GL_CULL_FACE);\n\n\t// Draw anti-aliased pixels\n\tglColorMask(GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE);\n\n\tglnvg__setUniforms(gl, call->uniformOffset + gl->fragSize, call->image);\n\tglnvg__checkError(gl, \"fill fill\");\n\n\tif (gl->flags & NVG_ANTIALIAS) {\n\t\tglnvg__stencilFunc(gl, GL_EQUAL, 0x00, 0xff);\n\t\tglStencilOp(GL_KEEP, GL_KEEP, GL_KEEP);\n\t\t// Draw fringes\n\t\tfor (i = 0; i < npaths; i++)\n\t\t\tglDrawArrays(GL_TRIANGLE_STRIP, paths[i].strokeOffset, paths[i].strokeCount);\n\t}\n\n\t// Draw fill\n\tglnvg__stencilFunc(gl, GL_NOTEQUAL, 0x0, 0xff);\n\tglStencilOp(GL_ZERO, GL_ZERO, GL_ZERO);\n\tglDrawArrays(GL_TRIANGLES, call->triangleOffset, call->triangleCount);\n\n\tglDisable(GL_STENCIL_TEST);\n}\n\nstatic void glnvg__convexFill(GLNVGcontext* gl, GLNVGcall* call)\n{\n\tGLNVGpath* paths = &gl->paths[call->pathOffset];\n\tint i, npaths = call->pathCount;\n\n\tglnvg__setUniforms(gl, call->uniformOffset, call->image);\n\tglnvg__checkError(gl, \"convex fill\");\n\n\tfor (i = 0; i < npaths; i++)\n\t\tglDrawArrays(GL_TRIANGLE_FAN, paths[i].fillOffset, paths[i].fillCount);\n\tif (gl->flags & NVG_ANTIALIAS) {\n\t\t// Draw fringes\n\t\tfor (i = 0; i < npaths; i++)\n\t\t\tglDrawArrays(GL_TRIANGLE_STRIP, paths[i].strokeOffset, paths[i].strokeCount);\n\t}\n}\n\nstatic void glnvg__stroke(GLNVGcontext* gl, GLNVGcall* call)\n{\n\tGLNVGpath* paths = &gl->paths[call->pathOffset];\n\tint npaths = call->pathCount, i;\n\n\tif (gl->flags & NVG_STENCIL_STROKES) {\n\n\t\tglEnable(GL_STENCIL_TEST);\n\t\tglnvg__stencilMask(gl, 0xff);\n\n\t\t// Fill the stroke base without overlap\n\t\tglnvg__stencilFunc(gl, GL_EQUAL, 0x0, 0xff);\n\t\tglStencilOp(GL_KEEP, GL_KEEP, GL_INCR);\n\t\tglnvg__setUniforms(gl, call->uniformOffset + gl->fragSize, call->image);\n\t\tglnvg__checkError(gl, \"stroke fill 0\");\n\t\tfor (i = 0; i < npaths; i++)\n\t\t\tglDrawArrays(GL_TRIANGLE_STRIP, paths[i].strokeOffset, paths[i].strokeCount);\n\n\t\t// Draw anti-aliased pixels.\n\t\tglnvg__setUniforms(gl, call->uniformOffset, call->image);\n\t\tglnvg__stencilFunc(gl, GL_EQUAL, 0x00, 0xff);\n\t\tglStencilOp(GL_KEEP, GL_KEEP, GL_KEEP);\n\t\tfor (i = 0; i < npaths; i++)\n\t\t\tglDrawArrays(GL_TRIANGLE_STRIP, paths[i].strokeOffset, paths[i].strokeCount);\n\n\t\t// Clear stencil buffer.\n\t\tglColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE);\n\t\tglnvg__stencilFunc(gl, GL_ALWAYS, 0x0, 0xff);\n\t\tglStencilOp(GL_ZERO, GL_ZERO, GL_ZERO);\n\t\tglnvg__checkError(gl, \"stroke fill 1\");\n\t\tfor (i = 0; i < npaths; i++)\n\t\t\tglDrawArrays(GL_TRIANGLE_STRIP, paths[i].strokeOffset, paths[i].strokeCount);\n\t\tglColorMask(GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE);\n\n\t\tglDisable(GL_STENCIL_TEST);\n\n//\t\tglnvg__convertPaint(gl, nvg__fragUniformPtr(gl, call->uniformOffset + gl->fragSize), paint, scissor, strokeWidth, fringe, 1.0f - 0.5f/255.0f);\n\n\t} else {\n\t\tglnvg__setUniforms(gl, call->uniformOffset, call->image);\n\t\tglnvg__checkError(gl, \"stroke fill\");\n\t\t// Draw Strokes\n\t\tfor (i = 0; i < npaths; i++)\n\t\t\tglDrawArrays(GL_TRIANGLE_STRIP, paths[i].strokeOffset, paths[i].strokeCount);\n\t}\n}\n\nstatic void glnvg__triangles(GLNVGcontext* gl, GLNVGcall* call)\n{\n\tglnvg__setUniforms(gl, call->uniformOffset, call->image);\n\tglnvg__checkError(gl, \"triangles fill\");\n\n\tglDrawArrays(GL_TRIANGLES, call->triangleOffset, call->triangleCount);\n}\n\nstatic void glnvg__renderCancel(void* uptr) {\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tgl->nverts = 0;\n\tgl->npaths = 0;\n\tgl->ncalls = 0;\n\tgl->nuniforms = 0;\n}\n\nstatic GLenum glnvg_convertBlendFuncFactor(int factor)\n{\n\tif (factor == NVG_ZERO)\n\t\treturn GL_ZERO;\n\tif (factor == NVG_ONE)\n\t\treturn GL_ONE;\n\tif (factor == NVG_SRC_COLOR)\n\t\treturn GL_SRC_COLOR;\n\tif (factor == NVG_ONE_MINUS_SRC_COLOR)\n\t\treturn GL_ONE_MINUS_SRC_COLOR;\n\tif (factor == NVG_DST_COLOR)\n\t\treturn GL_DST_COLOR;\n\tif (factor == NVG_ONE_MINUS_DST_COLOR)\n\t\treturn GL_ONE_MINUS_DST_COLOR;\n\tif (factor == NVG_SRC_ALPHA)\n\t\treturn GL_SRC_ALPHA;\n\tif (factor == NVG_ONE_MINUS_SRC_ALPHA)\n\t\treturn GL_ONE_MINUS_SRC_ALPHA;\n\tif (factor == NVG_DST_ALPHA)\n\t\treturn GL_DST_ALPHA;\n\tif (factor == NVG_ONE_MINUS_DST_ALPHA)\n\t\treturn GL_ONE_MINUS_DST_ALPHA;\n\tif (factor == NVG_SRC_ALPHA_SATURATE)\n\t\treturn GL_SRC_ALPHA_SATURATE;\n\treturn GL_INVALID_ENUM;\n}\n\nstatic void glnvg__blendCompositeOperation(NVGcompositeOperationState op)\n{\n\tGLenum srcRGB = glnvg_convertBlendFuncFactor(op.srcRGB);\n\tGLenum dstRGB = glnvg_convertBlendFuncFactor(op.dstRGB);\n\tGLenum srcAlpha = glnvg_convertBlendFuncFactor(op.srcAlpha);\n\tGLenum dstAlpha = glnvg_convertBlendFuncFactor(op.dstAlpha);\n\tif (srcRGB == GL_INVALID_ENUM || dstRGB == GL_INVALID_ENUM || srcAlpha == GL_INVALID_ENUM || dstAlpha == GL_INVALID_ENUM)\n\t\tglBlendFunc(GL_ONE, GL_ONE_MINUS_SRC_ALPHA);\n\telse\n\t\tglBlendFuncSeparate(srcRGB, dstRGB, srcAlpha, dstAlpha);\n}\n\nstatic void glnvg__renderFlush(void* uptr, NVGcompositeOperationState compositeOperation)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tint i;\n\n\tif (gl->ncalls > 0) {\n\n\t\t// Setup require GL state.\n\t\tglUseProgram(gl->shader.prog);\n\n\t\tglnvg__blendCompositeOperation(compositeOperation);\n\t\tglEnable(GL_CULL_FACE);\n\t\tglCullFace(GL_BACK);\n\t\tglFrontFace(GL_CCW);\n\t\tglEnable(GL_BLEND);\n\t\tglDisable(GL_DEPTH_TEST);\n\t\tglDisable(GL_SCISSOR_TEST);\n\t\tglColorMask(GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE);\n\t\tglStencilMask(0xffffffff);\n\t\tglStencilOp(GL_KEEP, GL_KEEP, GL_KEEP);\n\t\tglStencilFunc(GL_ALWAYS, 0, 0xffffffff);\n\t\tglActiveTexture(GL_TEXTURE0);\n\t\tglBindTexture(GL_TEXTURE_2D, 0);\n\t\t#if NANOVG_GL_USE_STATE_FILTER\n\t\tgl->boundTexture = 0;\n\t\tgl->stencilMask = 0xffffffff;\n\t\tgl->stencilFunc = GL_ALWAYS;\n\t\tgl->stencilFuncRef = 0;\n\t\tgl->stencilFuncMask = 0xffffffff;\n\t\t#endif\n\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\t\t// Upload ubo for frag shaders\n\t\tglBindBuffer(GL_UNIFORM_BUFFER, gl->fragBuf);\n\t\tglBufferData(GL_UNIFORM_BUFFER, gl->nuniforms * gl->fragSize, gl->uniforms, GL_STREAM_DRAW);\n#endif\n\n\t\t// Upload vertex data\n#if defined NANOVG_GL3\n\t\tglBindVertexArray(gl->vertArr);\n#endif\n\t\tglBindBuffer(GL_ARRAY_BUFFER, gl->vertBuf);\n\t\tglBufferData(GL_ARRAY_BUFFER, gl->nverts * sizeof(NVGvertex), gl->verts, GL_STREAM_DRAW);\n\t\tglEnableVertexAttribArray(0);\n\t\tglEnableVertexAttribArray(1);\n\t\tglVertexAttribPointer(0, 2, GL_FLOAT, GL_FALSE, sizeof(NVGvertex), (const GLvoid*)(size_t)0);\n\t\tglVertexAttribPointer(1, 2, GL_FLOAT, GL_FALSE, sizeof(NVGvertex), (const GLvoid*)(0 + 2*sizeof(float)));\n\n\t\t// Set view and texture just once per frame.\n\t\tglUniform1i(gl->shader.loc[GLNVG_LOC_TEX], 0);\n\t\tglUniform2fv(gl->shader.loc[GLNVG_LOC_VIEWSIZE], 1, gl->view);\n\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\t\tglBindBuffer(GL_UNIFORM_BUFFER, gl->fragBuf);\n#endif\n\n\t\tfor (i = 0; i < gl->ncalls; i++) {\n\t\t\tGLNVGcall* call = &gl->calls[i];\n\t\t\tif (call->type == GLNVG_FILL)\n\t\t\t\tglnvg__fill(gl, call);\n\t\t\telse if (call->type == GLNVG_CONVEXFILL)\n\t\t\t\tglnvg__convexFill(gl, call);\n\t\t\telse if (call->type == GLNVG_STROKE)\n\t\t\t\tglnvg__stroke(gl, call);\n\t\t\telse if (call->type == GLNVG_TRIANGLES)\n\t\t\t\tglnvg__triangles(gl, call);\n\t\t}\n\n\t\tglDisableVertexAttribArray(0);\n\t\tglDisableVertexAttribArray(1);\n#if defined NANOVG_GL3\n\t\tglBindVertexArray(0);\n#endif\n\t\tglDisable(GL_CULL_FACE);\n\t\t\tglBindBuffer(GL_ARRAY_BUFFER, 0);\n\t\tglUseProgram(0);\n\t\tglnvg__bindTexture(gl, 0);\n\t}\n\n\t// Reset calls\n\tgl->nverts = 0;\n\tgl->npaths = 0;\n\tgl->ncalls = 0;\n\tgl->nuniforms = 0;\n}\n\nstatic int glnvg__maxVertCount(const NVGpath* paths, int npaths)\n{\n\tint i, count = 0;\n\tfor (i = 0; i < npaths; i++) {\n\t\tcount += paths[i].nfill;\n\t\tcount += paths[i].nstroke;\n\t}\n\treturn count;\n}\n\nstatic GLNVGcall* glnvg__allocCall(GLNVGcontext* gl)\n{\n\tGLNVGcall* ret = NULL;\n\tif (gl->ncalls+1 > gl->ccalls) {\n\t\tGLNVGcall* calls;\n\t\tint ccalls = glnvg__maxi(gl->ncalls+1, 128) + gl->ccalls/2; // 1.5x Overallocate\n\t\tcalls = (GLNVGcall*)realloc(gl->calls, sizeof(GLNVGcall) * ccalls);\n\t\tif (calls == NULL) return NULL;\n\t\tgl->calls = calls;\n\t\tgl->ccalls = ccalls;\n\t}\n\tret = &gl->calls[gl->ncalls++];\n\tmemset(ret, 0, sizeof(GLNVGcall));\n\treturn ret;\n}\n\nstatic int glnvg__allocPaths(GLNVGcontext* gl, int n)\n{\n\tint ret = 0;\n\tif (gl->npaths+n > gl->cpaths) {\n\t\tGLNVGpath* paths;\n\t\tint cpaths = glnvg__maxi(gl->npaths + n, 128) + gl->cpaths/2; // 1.5x Overallocate\n\t\tpaths = (GLNVGpath*)realloc(gl->paths, sizeof(GLNVGpath) * cpaths);\n\t\tif (paths == NULL) return -1;\n\t\tgl->paths = paths;\n\t\tgl->cpaths = cpaths;\n\t}\n\tret = gl->npaths;\n\tgl->npaths += n;\n\treturn ret;\n}\n\nstatic int glnvg__allocVerts(GLNVGcontext* gl, int n)\n{\n\tint ret = 0;\n\tif (gl->nverts+n > gl->cverts) {\n\t\tNVGvertex* verts;\n\t\tint cverts = glnvg__maxi(gl->nverts + n, 4096) + gl->cverts/2; // 1.5x Overallocate\n\t\tverts = (NVGvertex*)realloc(gl->verts, sizeof(NVGvertex) * cverts);\n\t\tif (verts == NULL) return -1;\n\t\tgl->verts = verts;\n\t\tgl->cverts = cverts;\n\t}\n\tret = gl->nverts;\n\tgl->nverts += n;\n\treturn ret;\n}\n\nstatic int glnvg__allocFragUniforms(GLNVGcontext* gl, int n)\n{\n\tint ret = 0, structSize = gl->fragSize;\n\tif (gl->nuniforms+n > gl->cuniforms) {\n\t\tunsigned char* uniforms;\n\t\tint cuniforms = glnvg__maxi(gl->nuniforms+n, 128) + gl->cuniforms/2; // 1.5x Overallocate\n\t\tuniforms = (unsigned char*)realloc(gl->uniforms, structSize * cuniforms);\n\t\tif (uniforms == NULL) return -1;\n\t\tgl->uniforms = uniforms;\n\t\tgl->cuniforms = cuniforms;\n\t}\n\tret = gl->nuniforms * structSize;\n\tgl->nuniforms += n;\n\treturn ret;\n}\n\nstatic GLNVGfragUniforms* nvg__fragUniformPtr(GLNVGcontext* gl, int i)\n{\n\treturn (GLNVGfragUniforms*)&gl->uniforms[i];\n}\n\nstatic void glnvg__vset(NVGvertex* vtx, float x, float y, float u, float v)\n{\n\tvtx->x = x;\n\tvtx->y = y;\n\tvtx->u = u;\n\tvtx->v = v;\n}\n\nstatic void glnvg__renderFill(void* uptr, NVGpaint* paint, NVGscissor* scissor, float fringe,\n\t\t\t\t\t\t\t  const float* bounds, const NVGpath* paths, int npaths)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tGLNVGcall* call = glnvg__allocCall(gl);\n\tNVGvertex* quad;\n\tGLNVGfragUniforms* frag;\n\tint i, maxverts, offset;\n\n\tif (call == NULL) return;\n\n\tcall->type = GLNVG_FILL;\n\tcall->pathOffset = glnvg__allocPaths(gl, npaths);\n\tif (call->pathOffset == -1) goto error;\n\tcall->pathCount = npaths;\n\tcall->image = paint->image;\n\n\tif (npaths == 1 && paths[0].convex)\n\t\tcall->type = GLNVG_CONVEXFILL;\n\n\t// Allocate vertices for all the paths.\n\tmaxverts = glnvg__maxVertCount(paths, npaths) + 6;\n\toffset = glnvg__allocVerts(gl, maxverts);\n\tif (offset == -1) goto error;\n\n\tfor (i = 0; i < npaths; i++) {\n\t\tGLNVGpath* copy = &gl->paths[call->pathOffset + i];\n\t\tconst NVGpath* path = &paths[i];\n\t\tmemset(copy, 0, sizeof(GLNVGpath));\n\t\tif (path->nfill > 0) {\n\t\t\tcopy->fillOffset = offset;\n\t\t\tcopy->fillCount = path->nfill;\n\t\t\tmemcpy(&gl->verts[offset], path->fill, sizeof(NVGvertex) * path->nfill);\n\t\t\toffset += path->nfill;\n\t\t}\n\t\tif (path->nstroke > 0) {\n\t\t\tcopy->strokeOffset = offset;\n\t\t\tcopy->strokeCount = path->nstroke;\n\t\t\tmemcpy(&gl->verts[offset], path->stroke, sizeof(NVGvertex) * path->nstroke);\n\t\t\toffset += path->nstroke;\n\t\t}\n\t}\n\n\t// Quad\n\tcall->triangleOffset = offset;\n\tcall->triangleCount = 6;\n\tquad = &gl->verts[call->triangleOffset];\n\tglnvg__vset(&quad[0], bounds[0], bounds[3], 0.5f, 1.0f);\n\tglnvg__vset(&quad[1], bounds[2], bounds[3], 0.5f, 1.0f);\n\tglnvg__vset(&quad[2], bounds[2], bounds[1], 0.5f, 1.0f);\n\n\tglnvg__vset(&quad[3], bounds[0], bounds[3], 0.5f, 1.0f);\n\tglnvg__vset(&quad[4], bounds[2], bounds[1], 0.5f, 1.0f);\n\tglnvg__vset(&quad[5], bounds[0], bounds[1], 0.5f, 1.0f);\n\n\t// Setup uniforms for draw calls\n\tif (call->type == GLNVG_FILL) {\n\t\tcall->uniformOffset = glnvg__allocFragUniforms(gl, 2);\n\t\tif (call->uniformOffset == -1) goto error;\n\t\t// Simple shader for stencil\n\t\tfrag = nvg__fragUniformPtr(gl, call->uniformOffset);\n\t\tmemset(frag, 0, sizeof(*frag));\n\t\tfrag->strokeThr = -1.0f;\n\t\tfrag->type = NSVG_SHADER_SIMPLE;\n\t\t// Fill shader\n\t\tglnvg__convertPaint(gl, nvg__fragUniformPtr(gl, call->uniformOffset + gl->fragSize), paint, scissor, fringe, fringe, -1.0f);\n\t} else {\n\t\tcall->uniformOffset = glnvg__allocFragUniforms(gl, 1);\n\t\tif (call->uniformOffset == -1) goto error;\n\t\t// Fill shader\n\t\tglnvg__convertPaint(gl, nvg__fragUniformPtr(gl, call->uniformOffset), paint, scissor, fringe, fringe, -1.0f);\n\t}\n\n\treturn;\n\nerror:\n\t// We get here if call alloc was ok, but something else is not.\n\t// Roll back the last call to prevent drawing it.\n\tif (gl->ncalls > 0) gl->ncalls--;\n}\n\nstatic void glnvg__renderStroke(void* uptr, NVGpaint* paint, NVGscissor* scissor, float fringe,\n\t\t\t\t\t\t\t\tfloat strokeWidth, const NVGpath* paths, int npaths)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tGLNVGcall* call = glnvg__allocCall(gl);\n\tint i, maxverts, offset;\n\n\tif (call == NULL) return;\n\n\tcall->type = GLNVG_STROKE;\n\tcall->pathOffset = glnvg__allocPaths(gl, npaths);\n\tif (call->pathOffset == -1) goto error;\n\tcall->pathCount = npaths;\n\tcall->image = paint->image;\n\n\t// Allocate vertices for all the paths.\n\tmaxverts = glnvg__maxVertCount(paths, npaths);\n\toffset = glnvg__allocVerts(gl, maxverts);\n\tif (offset == -1) goto error;\n\n\tfor (i = 0; i < npaths; i++) {\n\t\tGLNVGpath* copy = &gl->paths[call->pathOffset + i];\n\t\tconst NVGpath* path = &paths[i];\n\t\tmemset(copy, 0, sizeof(GLNVGpath));\n\t\tif (path->nstroke) {\n\t\t\tcopy->strokeOffset = offset;\n\t\t\tcopy->strokeCount = path->nstroke;\n\t\t\tmemcpy(&gl->verts[offset], path->stroke, sizeof(NVGvertex) * path->nstroke);\n\t\t\toffset += path->nstroke;\n\t\t}\n\t}\n\n\tif (gl->flags & NVG_STENCIL_STROKES) {\n\t\t// Fill shader\n\t\tcall->uniformOffset = glnvg__allocFragUniforms(gl, 2);\n\t\tif (call->uniformOffset == -1) goto error;\n\n\t\tglnvg__convertPaint(gl, nvg__fragUniformPtr(gl, call->uniformOffset), paint, scissor, strokeWidth, fringe, -1.0f);\n\t\tglnvg__convertPaint(gl, nvg__fragUniformPtr(gl, call->uniformOffset + gl->fragSize), paint, scissor, strokeWidth, fringe, 1.0f - 0.5f/255.0f);\n\n\t} else {\n\t\t// Fill shader\n\t\tcall->uniformOffset = glnvg__allocFragUniforms(gl, 1);\n\t\tif (call->uniformOffset == -1) goto error;\n\t\tglnvg__convertPaint(gl, nvg__fragUniformPtr(gl, call->uniformOffset), paint, scissor, strokeWidth, fringe, -1.0f);\n\t}\n\n\treturn;\n\nerror:\n\t// We get here if call alloc was ok, but something else is not.\n\t// Roll back the last call to prevent drawing it.\n\tif (gl->ncalls > 0) gl->ncalls--;\n}\n\nstatic void glnvg__renderTriangles(void* uptr, NVGpaint* paint, NVGscissor* scissor,\n\t\t\t\t\t\t\t\t   const NVGvertex* verts, int nverts)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tGLNVGcall* call = glnvg__allocCall(gl);\n\tGLNVGfragUniforms* frag;\n\n\tif (call == NULL) return;\n\n\tcall->type = GLNVG_TRIANGLES;\n\tcall->image = paint->image;\n\n\t// Allocate vertices for all the paths.\n\tcall->triangleOffset = glnvg__allocVerts(gl, nverts);\n\tif (call->triangleOffset == -1) goto error;\n\tcall->triangleCount = nverts;\n\n\tmemcpy(&gl->verts[call->triangleOffset], verts, sizeof(NVGvertex) * nverts);\n\n\t// Fill shader\n\tcall->uniformOffset = glnvg__allocFragUniforms(gl, 1);\n\tif (call->uniformOffset == -1) goto error;\n\tfrag = nvg__fragUniformPtr(gl, call->uniformOffset);\n\tglnvg__convertPaint(gl, frag, paint, scissor, 1.0f, 1.0f, -1.0f);\n\tfrag->type = NSVG_SHADER_IMG;\n\n\treturn;\n\nerror:\n\t// We get here if call alloc was ok, but something else is not.\n\t// Roll back the last call to prevent drawing it.\n\tif (gl->ncalls > 0) gl->ncalls--;\n}\n\nstatic void glnvg__renderDelete(void* uptr)\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)uptr;\n\tint i;\n\tif (gl == NULL) return;\n\n\tglnvg__deleteShader(&gl->shader);\n\n#if NANOVG_GL3\n#if NANOVG_GL_USE_UNIFORMBUFFER\n\tif (gl->fragBuf != 0)\n\t\tglDeleteBuffers(1, &gl->fragBuf);\n#endif\n\tif (gl->vertArr != 0)\n\t\tglDeleteVertexArrays(1, &gl->vertArr);\n#endif\n\tif (gl->vertBuf != 0)\n\t\tglDeleteBuffers(1, &gl->vertBuf);\n\n\tfor (i = 0; i < gl->ntextures; i++) {\n\t\tif (gl->textures[i].tex != 0 && (gl->textures[i].flags & NVG_IMAGE_NODELETE) == 0)\n\t\t\tglDeleteTextures(1, &gl->textures[i].tex);\n\t}\n\tfree(gl->textures);\n\n\tfree(gl->paths);\n\tfree(gl->verts);\n\tfree(gl->uniforms);\n\tfree(gl->calls);\n\n\tfree(gl);\n}\n\n\n#if defined NANOVG_GL2\nNVGcontext* nvgCreateGL2(int flags)\n#elif defined NANOVG_GL3\nNVGcontext* nvgCreateGL3(int flags)\n#elif defined NANOVG_GLES2\nNVGcontext* nvgCreateGLES2(int flags)\n#elif defined NANOVG_GLES3\nNVGcontext* nvgCreateGLES3(int flags)\n#endif\n{\n\tNVGparams params;\n\tNVGcontext* ctx = NULL;\n\tGLNVGcontext* gl = (GLNVGcontext*)malloc(sizeof(GLNVGcontext));\n\tif (gl == NULL) goto error;\n\tmemset(gl, 0, sizeof(GLNVGcontext));\n\n\tmemset(&params, 0, sizeof(params));\n\tparams.renderCreate = glnvg__renderCreate;\n\tparams.renderCreateTexture = glnvg__renderCreateTexture;\n\tparams.renderDeleteTexture = glnvg__renderDeleteTexture;\n\tparams.renderUpdateTexture = glnvg__renderUpdateTexture;\n\tparams.renderGetTextureSize = glnvg__renderGetTextureSize;\n\tparams.renderViewport = glnvg__renderViewport;\n\tparams.renderCancel = glnvg__renderCancel;\n\tparams.renderFlush = glnvg__renderFlush;\n\tparams.renderFill = glnvg__renderFill;\n\tparams.renderStroke = glnvg__renderStroke;\n\tparams.renderTriangles = glnvg__renderTriangles;\n\tparams.renderDelete = glnvg__renderDelete;\n\tparams.userPtr = gl;\n\tparams.edgeAntiAlias = flags & NVG_ANTIALIAS ? 1 : 0;\n\n\tgl->flags = flags;\n\n\tctx = nvgCreateInternal(&params);\n\tif (ctx == NULL) goto error;\n\n\treturn ctx;\n\nerror:\n\t// 'gl' is freed by nvgDeleteInternal.\n\tif (ctx != NULL) nvgDeleteInternal(ctx);\n\treturn NULL;\n}\n\n#if defined NANOVG_GL2\nvoid nvgDeleteGL2(NVGcontext* ctx)\n#elif defined NANOVG_GL3\nvoid nvgDeleteGL3(NVGcontext* ctx)\n#elif defined NANOVG_GLES2\nvoid nvgDeleteGLES2(NVGcontext* ctx)\n#elif defined NANOVG_GLES3\nvoid nvgDeleteGLES3(NVGcontext* ctx)\n#endif\n{\n\tnvgDeleteInternal(ctx);\n}\n\n#if defined NANOVG_GL2\nint nvglCreateImageFromHandleGL2(NVGcontext* ctx, GLuint textureId, int w, int h, int imageFlags)\n#elif defined NANOVG_GL3\nint nvglCreateImageFromHandleGL3(NVGcontext* ctx, GLuint textureId, int w, int h, int imageFlags)\n#elif defined NANOVG_GLES2\nint nvglCreateImageFromHandleGLES2(NVGcontext* ctx, GLuint textureId, int w, int h, int imageFlags)\n#elif defined NANOVG_GLES3\nint nvglCreateImageFromHandleGLES3(NVGcontext* ctx, GLuint textureId, int w, int h, int imageFlags)\n#endif\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)nvgInternalParams(ctx)->userPtr;\n\tGLNVGtexture* tex = glnvg__allocTexture(gl);\n\n\tif (tex == NULL) return 0;\n\n\ttex->type = NVG_TEXTURE_RGBA;\n\ttex->tex = textureId;\n\ttex->flags = imageFlags;\n\ttex->width = w;\n\ttex->height = h;\n\n\treturn tex->id;\n}\n\n#if defined NANOVG_GL2\nGLuint nvglImageHandleGL2(NVGcontext* ctx, int image)\n#elif defined NANOVG_GL3\nGLuint nvglImageHandleGL3(NVGcontext* ctx, int image)\n#elif defined NANOVG_GLES2\nGLuint nvglImageHandleGLES2(NVGcontext* ctx, int image)\n#elif defined NANOVG_GLES3\nGLuint nvglImageHandleGLES3(NVGcontext* ctx, int image)\n#endif\n{\n\tGLNVGcontext* gl = (GLNVGcontext*)nvgInternalParams(ctx)->userPtr;\n\tGLNVGtexture* tex = glnvg__findTexture(gl, image);\n\treturn tex->tex;\n}\n\n#endif /* NANOVG_GL_IMPLEMENTATION */\n"
  },
  {
    "path": "phonelibs/nanovg/nanovg_gl_utils.h",
    "content": "//\n// Copyright (c) 2009-2013 Mikko Mononen memon@inside.org\n//\n// This software is provided 'as-is', without any express or implied\n// warranty.  In no event will the authors be held liable for any damages\n// arising from the use of this software.\n// Permission is granted to anyone to use this software for any purpose,\n// including commercial applications, and to alter it and redistribute it\n// freely, subject to the following restrictions:\n// 1. The origin of this software must not be misrepresented; you must not\n//    claim that you wrote the original software. If you use this software\n//    in a product, an acknowledgment in the product documentation would be\n//    appreciated but is not required.\n// 2. Altered source versions must be plainly marked as such, and must not be\n//    misrepresented as being the original software.\n// 3. This notice may not be removed or altered from any source distribution.\n//\n#ifndef NANOVG_GL_UTILS_H\n#define NANOVG_GL_UTILS_H\n\nstruct NVGLUframebuffer {\n\tNVGcontext* ctx;\n\tGLuint fbo;\n\tGLuint rbo;\n\tGLuint texture;\n\tint image;\n};\ntypedef struct NVGLUframebuffer NVGLUframebuffer;\n\n// Helper function to create GL frame buffer to render to.\nvoid nvgluBindFramebuffer(NVGLUframebuffer* fb);\nNVGLUframebuffer* nvgluCreateFramebuffer(NVGcontext* ctx, int w, int h, int imageFlags);\nvoid nvgluDeleteFramebuffer(NVGLUframebuffer* fb);\n\n#endif // NANOVG_GL_UTILS_H\n\n#ifdef NANOVG_GL_IMPLEMENTATION\n\n#if defined(NANOVG_GL3) || defined(NANOVG_GLES2) || defined(NANOVG_GLES3)\n// FBO is core in OpenGL 3>.\n#\tdefine NANOVG_FBO_VALID 1\n#elif defined(NANOVG_GL2)\n// On OS X including glext defines FBO on GL2 too.\n#\tifdef __APPLE__\n#\t\tinclude <OpenGL/glext.h>\n#\t\tdefine NANOVG_FBO_VALID 1\n#\tendif\n#endif\n\nstatic GLint defaultFBO = -1;\n\nNVGLUframebuffer* nvgluCreateFramebuffer(NVGcontext* ctx, int w, int h, int imageFlags)\n{\n#ifdef NANOVG_FBO_VALID\n\tGLint defaultFBO;\n\tGLint defaultRBO;\n\tNVGLUframebuffer* fb = NULL;\n\n\tglGetIntegerv(GL_FRAMEBUFFER_BINDING, &defaultFBO);\n\tglGetIntegerv(GL_RENDERBUFFER_BINDING, &defaultRBO);\n\n\tfb = (NVGLUframebuffer*)malloc(sizeof(NVGLUframebuffer));\n\tif (fb == NULL) goto error;\n\tmemset(fb, 0, sizeof(NVGLUframebuffer));\n\n\tfb->image = nvgCreateImageRGBA(ctx, w, h, imageFlags | NVG_IMAGE_FLIPY | NVG_IMAGE_PREMULTIPLIED, NULL);\n\n#if defined NANOVG_GL2\n\tfb->texture = nvglImageHandleGL2(ctx, fb->image);\n#elif defined NANOVG_GL3\n\tfb->texture = nvglImageHandleGL3(ctx, fb->image);\n#elif defined NANOVG_GLES2\n\tfb->texture = nvglImageHandleGLES2(ctx, fb->image);\n#elif defined NANOVG_GLES3\n\tfb->texture = nvglImageHandleGLES3(ctx, fb->image);\n#endif\n\n\tfb->ctx = ctx;\n\n\t// frame buffer object\n\tglGenFramebuffers(1, &fb->fbo);\n\tglBindFramebuffer(GL_FRAMEBUFFER, fb->fbo);\n\n\t// render buffer object\n\tglGenRenderbuffers(1, &fb->rbo);\n\tglBindRenderbuffer(GL_RENDERBUFFER, fb->rbo);\n\tglRenderbufferStorage(GL_RENDERBUFFER, GL_STENCIL_INDEX8, w, h);\n\n\t// combine all\n\tglFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, fb->texture, 0);\n\tglFramebufferRenderbuffer(GL_FRAMEBUFFER, GL_STENCIL_ATTACHMENT, GL_RENDERBUFFER, fb->rbo);\n\n\tif (glCheckFramebufferStatus(GL_FRAMEBUFFER) != GL_FRAMEBUFFER_COMPLETE) goto error;\n\n\tglBindFramebuffer(GL_FRAMEBUFFER, defaultFBO);\n\tglBindRenderbuffer(GL_RENDERBUFFER, defaultRBO);\n\treturn fb;\nerror:\n\tglBindFramebuffer(GL_FRAMEBUFFER, defaultFBO);\n\tglBindRenderbuffer(GL_RENDERBUFFER, defaultRBO);\n\tnvgluDeleteFramebuffer(fb);\n\treturn NULL;\n#else\n\tNVG_NOTUSED(ctx);\n\tNVG_NOTUSED(w);\n\tNVG_NOTUSED(h);\n\tNVG_NOTUSED(imageFlags);\n\treturn NULL;\n#endif\n}\n\nvoid nvgluBindFramebuffer(NVGLUframebuffer* fb)\n{\n#ifdef NANOVG_FBO_VALID\n\tif (defaultFBO == -1) glGetIntegerv(GL_FRAMEBUFFER_BINDING, &defaultFBO);\n\tglBindFramebuffer(GL_FRAMEBUFFER, fb != NULL ? fb->fbo : defaultFBO);\n#else\n\tNVG_NOTUSED(fb);\n#endif\n}\n\nvoid nvgluDeleteFramebuffer(NVGLUframebuffer* fb)\n{\n#ifdef NANOVG_FBO_VALID\n\tif (fb == NULL) return;\n\tif (fb->fbo != 0)\n\t\tglDeleteFramebuffers(1, &fb->fbo);\n\tif (fb->rbo != 0)\n\t\tglDeleteRenderbuffers(1, &fb->rbo);\n\tif (fb->image >= 0)\n\t\tnvgDeleteImage(fb->ctx, fb->image);\n\tfb->ctx = NULL;\n\tfb->fbo = 0;\n\tfb->rbo = 0;\n\tfb->texture = 0;\n\tfb->image = -1;\n\tfree(fb);\n#else\n\tNVG_NOTUSED(fb);\n#endif\n}\n\n#endif // NANOVG_GL_IMPLEMENTATION\n"
  },
  {
    "path": "phonelibs/nanovg/stb_image.h",
    "content": "/* stb_image - v2.10 - public domain image loader - http://nothings.org/stb_image.h\n                                     no warranty implied; use at your own risk\n\n   Do this:\n      #define STB_IMAGE_IMPLEMENTATION\n   before you include this file in *one* C or C++ file to create the implementation.\n\n   // i.e. it should look like this:\n   #include ...\n   #include ...\n   #include ...\n   #define STB_IMAGE_IMPLEMENTATION\n   #include \"stb_image.h\"\n\n   You can #define STBI_ASSERT(x) before the #include to avoid using assert.h.\n   And #define STBI_MALLOC, STBI_REALLOC, and STBI_FREE to avoid using malloc,realloc,free\n\n\n   QUICK NOTES:\n      Primarily of interest to game developers and other people who can\n          avoid problematic images and only need the trivial interface\n\n      JPEG baseline & progressive (12 bpc/arithmetic not supported, same as stock IJG lib)\n      PNG 1/2/4/8-bit-per-channel (16 bpc not supported)\n\n      TGA (not sure what subset, if a subset)\n      BMP non-1bpp, non-RLE\n      PSD (composited view only, no extra channels, 8/16 bit-per-channel)\n\n      GIF (*comp always reports as 4-channel)\n      HDR (radiance rgbE format)\n      PIC (Softimage PIC)\n      PNM (PPM and PGM binary only)\n\n      Animated GIF still needs a proper API, but here's one way to do it:\n          http://gist.github.com/urraka/685d9a6340b26b830d49\n\n      - decode from memory or through FILE (define STBI_NO_STDIO to remove code)\n      - decode from arbitrary I/O callbacks\n      - SIMD acceleration on x86/x64 (SSE2) and ARM (NEON)\n\n   Full documentation under \"DOCUMENTATION\" below.\n\n\n   Revision 2.00 release notes:\n\n      - Progressive JPEG is now supported.\n\n      - PPM and PGM binary formats are now supported, thanks to Ken Miller.\n\n      - x86 platforms now make use of SSE2 SIMD instructions for\n        JPEG decoding, and ARM platforms can use NEON SIMD if requested.\n        This work was done by Fabian \"ryg\" Giesen. SSE2 is used by\n        default, but NEON must be enabled explicitly; see docs.\n\n        With other JPEG optimizations included in this version, we see\n        2x speedup on a JPEG on an x86 machine, and a 1.5x speedup\n        on a JPEG on an ARM machine, relative to previous versions of this\n        library. The same results will not obtain for all JPGs and for all\n        x86/ARM machines. (Note that progressive JPEGs are significantly\n        slower to decode than regular JPEGs.) This doesn't mean that this\n        is the fastest JPEG decoder in the land; rather, it brings it\n        closer to parity with standard libraries. If you want the fastest\n        decode, look elsewhere. (See \"Philosophy\" section of docs below.)\n\n        See final bullet items below for more info on SIMD.\n\n      - Added STBI_MALLOC, STBI_REALLOC, and STBI_FREE macros for replacing\n        the memory allocator. Unlike other STBI libraries, these macros don't\n        support a context parameter, so if you need to pass a context in to\n        the allocator, you'll have to store it in a global or a thread-local\n        variable.\n\n      - Split existing STBI_NO_HDR flag into two flags, STBI_NO_HDR and\n        STBI_NO_LINEAR.\n            STBI_NO_HDR:     suppress implementation of .hdr reader format\n            STBI_NO_LINEAR:  suppress high-dynamic-range light-linear float API\n\n      - You can suppress implementation of any of the decoders to reduce\n        your code footprint by #defining one or more of the following\n        symbols before creating the implementation.\n\n            STBI_NO_JPEG\n            STBI_NO_PNG\n            STBI_NO_BMP\n            STBI_NO_PSD\n            STBI_NO_TGA\n            STBI_NO_GIF\n            STBI_NO_HDR\n            STBI_NO_PIC\n            STBI_NO_PNM   (.ppm and .pgm)\n\n      - You can request *only* certain decoders and suppress all other ones\n        (this will be more forward-compatible, as addition of new decoders\n        doesn't require you to disable them explicitly):\n\n            STBI_ONLY_JPEG\n            STBI_ONLY_PNG\n            STBI_ONLY_BMP\n            STBI_ONLY_PSD\n            STBI_ONLY_TGA\n            STBI_ONLY_GIF\n            STBI_ONLY_HDR\n            STBI_ONLY_PIC\n            STBI_ONLY_PNM   (.ppm and .pgm)\n\n         Note that you can define multiples of these, and you will get all\n         of them (\"only x\" and \"only y\" is interpreted to mean \"only x&y\").\n\n       - If you use STBI_NO_PNG (or _ONLY_ without PNG), and you still\n         want the zlib decoder to be available, #define STBI_SUPPORT_ZLIB\n\n      - Compilation of all SIMD code can be suppressed with\n            #define STBI_NO_SIMD\n        It should not be necessary to disable SIMD unless you have issues\n        compiling (e.g. using an x86 compiler which doesn't support SSE\n        intrinsics or that doesn't support the method used to detect\n        SSE2 support at run-time), and even those can be reported as\n        bugs so I can refine the built-in compile-time checking to be\n        smarter.\n\n      - The old STBI_SIMD system which allowed installing a user-defined\n        IDCT etc. has been removed. If you need this, don't upgrade. My\n        assumption is that almost nobody was doing this, and those who\n        were will find the built-in SIMD more satisfactory anyway.\n\n      - RGB values computed for JPEG images are slightly different from\n        previous versions of stb_image. (This is due to using less\n        integer precision in SIMD.) The C code has been adjusted so\n        that the same RGB values will be computed regardless of whether\n        SIMD support is available, so your app should always produce\n        consistent results. But these results are slightly different from\n        previous versions. (Specifically, about 3% of available YCbCr values\n        will compute different RGB results from pre-1.49 versions by +-1;\n        most of the deviating values are one smaller in the G channel.)\n\n      - If you must produce consistent results with previous versions of\n        stb_image, #define STBI_JPEG_OLD and you will get the same results\n        you used to; however, you will not get the SIMD speedups for\n        the YCbCr-to-RGB conversion step (although you should still see\n        significant JPEG speedup from the other changes).\n\n        Please note that STBI_JPEG_OLD is a temporary feature; it will be\n        removed in future versions of the library. It is only intended for\n        near-term back-compatibility use.\n\n\n   Latest revision history:\n      2.10  (2016-01-22) avoid warning introduced in 2.09\n      2.09  (2016-01-16) 16-bit TGA; comments in PNM files; STBI_REALLOC_SIZED\n      2.08  (2015-09-13) fix to 2.07 cleanup, reading RGB PSD as RGBA\n      2.07  (2015-09-13) partial animated GIF support\n                         limited 16-bit PSD support\n                         minor bugs, code cleanup, and compiler warnings\n      2.06  (2015-04-19) fix bug where PSD returns wrong '*comp' value\n      2.05  (2015-04-19) fix bug in progressive JPEG handling, fix warning\n      2.04  (2015-04-15) try to re-enable SIMD on MinGW 64-bit\n      2.03  (2015-04-12) additional corruption checking\n                         stbi_set_flip_vertically_on_load\n                         fix NEON support; fix mingw support\n      2.02  (2015-01-19) fix incorrect assert, fix warning\n      2.01  (2015-01-17) fix various warnings\n      2.00b (2014-12-25) fix STBI_MALLOC in progressive JPEG\n      2.00  (2014-12-25) optimize JPEG, including x86 SSE2 & ARM NEON SIMD\n                         progressive JPEG\n                         PGM/PPM support\n                         STBI_MALLOC,STBI_REALLOC,STBI_FREE\n                         STBI_NO_*, STBI_ONLY_*\n                         GIF bugfix\n      1.48  (2014-12-14) fix incorrectly-named assert()\n      1.47  (2014-12-14) 1/2/4-bit PNG support (both grayscale and paletted)\n                         optimize PNG\n                         fix bug in interlaced PNG with user-specified channel count\n\n   See end of file for full revision history.\n\n\n ============================    Contributors    =========================\n\n Image formats                          Extensions, features\n    Sean Barrett (jpeg, png, bmp)          Jetro Lauha (stbi_info)\n    Nicolas Schulz (hdr, psd)              Martin \"SpartanJ\" Golini (stbi_info)\n    Jonathan Dummer (tga)                  James \"moose2000\" Brown (iPhone PNG)\n    Jean-Marc Lienher (gif)                Ben \"Disch\" Wenger (io callbacks)\n    Tom Seddon (pic)                       Omar Cornut (1/2/4-bit PNG)\n    Thatcher Ulrich (psd)                  Nicolas Guillemot (vertical flip)\n    Ken Miller (pgm, ppm)                  Richard Mitton (16-bit PSD)\n    urraka@github (animated gif)           Junggon Kim (PNM comments)\n                                           Daniel Gibson (16-bit TGA)\n\n Optimizations & bugfixes\n    Fabian \"ryg\" Giesen\n    Arseny Kapoulkine\n\n Bug & warning fixes\n    Marc LeBlanc            David Woo          Guillaume George   Martins Mozeiko\n    Christpher Lloyd        Martin Golini      Jerry Jansson      Joseph Thomson\n    Dave Moore              Roy Eltham         Hayaki Saito       Phil Jordan\n    Won Chun                Luke Graham        Johan Duparc       Nathan Reed\n    the Horde3D community   Thomas Ruf         Ronny Chevalier    Nick Verigakis\n    Janez Zemva             John Bartholomew   Michal Cichon      svdijk@github\n    Jonathan Blow           Ken Hamada         Tero Hanninen      Baldur Karlsson\n    Laurent Gomila          Cort Stratton      Sergio Gonzalez    romigrou@github\n    Aruelien Pocheville     Thibault Reuille   Cass Everitt\n    Ryamond Barbiero        Paul Du Bois       Engin Manap\n    Blazej Dariusz Roszkowski\n    Michaelangel007@github\n\n\nLICENSE\n\nThis software is in the public domain. Where that dedication is not\nrecognized, you are granted a perpetual, irrevocable license to copy,\ndistribute, and modify this file as you see fit.\n\n*/\n\n#ifndef STBI_INCLUDE_STB_IMAGE_H\n#define STBI_INCLUDE_STB_IMAGE_H\n\n// DOCUMENTATION\n//\n// Limitations:\n//    - no 16-bit-per-channel PNG\n//    - no 12-bit-per-channel JPEG\n//    - no JPEGs with arithmetic coding\n//    - no 1-bit BMP\n//    - GIF always returns *comp=4\n//\n// Basic usage (see HDR discussion below for HDR usage):\n//    int x,y,n;\n//    unsigned char *data = stbi_load(filename, &x, &y, &n, 0);\n//    // ... process data if not NULL ...\n//    // ... x = width, y = height, n = # 8-bit components per pixel ...\n//    // ... replace '0' with '1'..'4' to force that many components per pixel\n//    // ... but 'n' will always be the number that it would have been if you said 0\n//    stbi_image_free(data)\n//\n// Standard parameters:\n//    int *x       -- outputs image width in pixels\n//    int *y       -- outputs image height in pixels\n//    int *comp    -- outputs # of image components in image file\n//    int req_comp -- if non-zero, # of image components requested in result\n//\n// The return value from an image loader is an 'unsigned char *' which points\n// to the pixel data, or NULL on an allocation failure or if the image is\n// corrupt or invalid. The pixel data consists of *y scanlines of *x pixels,\n// with each pixel consisting of N interleaved 8-bit components; the first\n// pixel pointed to is top-left-most in the image. There is no padding between\n// image scanlines or between pixels, regardless of format. The number of\n// components N is 'req_comp' if req_comp is non-zero, or *comp otherwise.\n// If req_comp is non-zero, *comp has the number of components that _would_\n// have been output otherwise. E.g. if you set req_comp to 4, you will always\n// get RGBA output, but you can check *comp to see if it's trivially opaque\n// because e.g. there were only 3 channels in the source image.\n//\n// An output image with N components has the following components interleaved\n// in this order in each pixel:\n//\n//     N=#comp     components\n//       1           grey\n//       2           grey, alpha\n//       3           red, green, blue\n//       4           red, green, blue, alpha\n//\n// If image loading fails for any reason, the return value will be NULL,\n// and *x, *y, *comp will be unchanged. The function stbi_failure_reason()\n// can be queried for an extremely brief, end-user unfriendly explanation\n// of why the load failed. Define STBI_NO_FAILURE_STRINGS to avoid\n// compiling these strings at all, and STBI_FAILURE_USERMSG to get slightly\n// more user-friendly ones.\n//\n// Paletted PNG, BMP, GIF, and PIC images are automatically depalettized.\n//\n// ===========================================================================\n//\n// Philosophy\n//\n// stb libraries are designed with the following priorities:\n//\n//    1. easy to use\n//    2. easy to maintain\n//    3. good performance\n//\n// Sometimes I let \"good performance\" creep up in priority over \"easy to maintain\",\n// and for best performance I may provide less-easy-to-use APIs that give higher\n// performance, in addition to the easy to use ones. Nevertheless, it's important\n// to keep in mind that from the standpoint of you, a client of this library,\n// all you care about is #1 and #3, and stb libraries do not emphasize #3 above all.\n//\n// Some secondary priorities arise directly from the first two, some of which\n// make more explicit reasons why performance can't be emphasized.\n//\n//    - Portable (\"ease of use\")\n//    - Small footprint (\"easy to maintain\")\n//    - No dependencies (\"ease of use\")\n//\n// ===========================================================================\n//\n// I/O callbacks\n//\n// I/O callbacks allow you to read from arbitrary sources, like packaged\n// files or some other source. Data read from callbacks are processed\n// through a small internal buffer (currently 128 bytes) to try to reduce\n// overhead.\n//\n// The three functions you must define are \"read\" (reads some bytes of data),\n// \"skip\" (skips some bytes of data), \"eof\" (reports if the stream is at the end).\n//\n// ===========================================================================\n//\n// SIMD support\n//\n// The JPEG decoder will try to automatically use SIMD kernels on x86 when\n// supported by the compiler. For ARM Neon support, you must explicitly\n// request it.\n//\n// (The old do-it-yourself SIMD API is no longer supported in the current\n// code.)\n//\n// On x86, SSE2 will automatically be used when available based on a run-time\n// test; if not, the generic C versions are used as a fall-back. On ARM targets,\n// the typical path is to have separate builds for NEON and non-NEON devices\n// (at least this is true for iOS and Android). Therefore, the NEON support is\n// toggled by a build flag: define STBI_NEON to get NEON loops.\n//\n// The output of the JPEG decoder is slightly different from versions where\n// SIMD support was introduced (that is, for versions before 1.49). The\n// difference is only +-1 in the 8-bit RGB channels, and only on a small\n// fraction of pixels. You can force the pre-1.49 behavior by defining\n// STBI_JPEG_OLD, but this will disable some of the SIMD decoding path\n// and hence cost some performance.\n//\n// If for some reason you do not want to use any of SIMD code, or if\n// you have issues compiling it, you can disable it entirely by\n// defining STBI_NO_SIMD.\n//\n// ===========================================================================\n//\n// HDR image support   (disable by defining STBI_NO_HDR)\n//\n// stb_image now supports loading HDR images in general, and currently\n// the Radiance .HDR file format, although the support is provided\n// generically. You can still load any file through the existing interface;\n// if you attempt to load an HDR file, it will be automatically remapped to\n// LDR, assuming gamma 2.2 and an arbitrary scale factor defaulting to 1;\n// both of these constants can be reconfigured through this interface:\n//\n//     stbi_hdr_to_ldr_gamma(2.2f);\n//     stbi_hdr_to_ldr_scale(1.0f);\n//\n// (note, do not use _inverse_ constants; stbi_image will invert them\n// appropriately).\n//\n// Additionally, there is a new, parallel interface for loading files as\n// (linear) floats to preserve the full dynamic range:\n//\n//    float *data = stbi_loadf(filename, &x, &y, &n, 0);\n//\n// If you load LDR images through this interface, those images will\n// be promoted to floating point values, run through the inverse of\n// constants corresponding to the above:\n//\n//     stbi_ldr_to_hdr_scale(1.0f);\n//     stbi_ldr_to_hdr_gamma(2.2f);\n//\n// Finally, given a filename (or an open file or memory block--see header\n// file for details) containing image data, you can query for the \"most\n// appropriate\" interface to use (that is, whether the image is HDR or\n// not), using:\n//\n//     stbi_is_hdr(char *filename);\n//\n// ===========================================================================\n//\n// iPhone PNG support:\n//\n// By default we convert iphone-formatted PNGs back to RGB, even though\n// they are internally encoded differently. You can disable this conversion\n// by by calling stbi_convert_iphone_png_to_rgb(0), in which case\n// you will always just get the native iphone \"format\" through (which\n// is BGR stored in RGB).\n//\n// Call stbi_set_unpremultiply_on_load(1) as well to force a divide per\n// pixel to remove any premultiplied alpha *only* if the image file explicitly\n// says there's premultiplied data (currently only happens in iPhone images,\n// and only if iPhone convert-to-rgb processing is on).\n//\n\n\n#ifndef STBI_NO_STDIO\n#include <stdio.h>\n#endif // STBI_NO_STDIO\n\n#define STBI_VERSION 1\n\nenum\n{\n   STBI_default = 0, // only used for req_comp\n\n   STBI_grey       = 1,\n   STBI_grey_alpha = 2,\n   STBI_rgb        = 3,\n   STBI_rgb_alpha  = 4\n};\n\ntypedef unsigned char stbi_uc;\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#ifdef STB_IMAGE_STATIC\n#define STBIDEF static\n#else\n#define STBIDEF extern\n#endif\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// PRIMARY API - works on images of any type\n//\n\n//\n// load image by filename, open file, or memory buffer\n//\n\ntypedef struct\n{\n   int      (*read)  (void *user,char *data,int size);   // fill 'data' with 'size' bytes.  return number of bytes actually read\n   void     (*skip)  (void *user,int n);                 // skip the next 'n' bytes, or 'unget' the last -n bytes if negative\n   int      (*eof)   (void *user);                       // returns nonzero if we are at end of file/data\n} stbi_io_callbacks;\n\nSTBIDEF stbi_uc *stbi_load               (char              const *filename,           int *x, int *y, int *comp, int req_comp);\nSTBIDEF stbi_uc *stbi_load_from_memory   (stbi_uc           const *buffer, int len   , int *x, int *y, int *comp, int req_comp);\nSTBIDEF stbi_uc *stbi_load_from_callbacks(stbi_io_callbacks const *clbk  , void *user, int *x, int *y, int *comp, int req_comp);\n\n#ifndef STBI_NO_STDIO\nSTBIDEF stbi_uc *stbi_load_from_file  (FILE *f,                  int *x, int *y, int *comp, int req_comp);\n// for stbi_load_from_file, file pointer is left pointing immediately after image\n#endif\n\n#ifndef STBI_NO_LINEAR\n   STBIDEF float *stbi_loadf                 (char const *filename,           int *x, int *y, int *comp, int req_comp);\n   STBIDEF float *stbi_loadf_from_memory     (stbi_uc const *buffer, int len, int *x, int *y, int *comp, int req_comp);\n   STBIDEF float *stbi_loadf_from_callbacks  (stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp, int req_comp);\n\n   #ifndef STBI_NO_STDIO\n   STBIDEF float *stbi_loadf_from_file  (FILE *f,                int *x, int *y, int *comp, int req_comp);\n   #endif\n#endif\n\n#ifndef STBI_NO_HDR\n   STBIDEF void   stbi_hdr_to_ldr_gamma(float gamma);\n   STBIDEF void   stbi_hdr_to_ldr_scale(float scale);\n#endif // STBI_NO_HDR\n\n#ifndef STBI_NO_LINEAR\n   STBIDEF void   stbi_ldr_to_hdr_gamma(float gamma);\n   STBIDEF void   stbi_ldr_to_hdr_scale(float scale);\n#endif // STBI_NO_LINEAR\n\n// stbi_is_hdr is always defined, but always returns false if STBI_NO_HDR\nSTBIDEF int    stbi_is_hdr_from_callbacks(stbi_io_callbacks const *clbk, void *user);\nSTBIDEF int    stbi_is_hdr_from_memory(stbi_uc const *buffer, int len);\n#ifndef STBI_NO_STDIO\nSTBIDEF int      stbi_is_hdr          (char const *filename);\nSTBIDEF int      stbi_is_hdr_from_file(FILE *f);\n#endif // STBI_NO_STDIO\n\n\n// get a VERY brief reason for failure\n// NOT THREADSAFE\nSTBIDEF const char *stbi_failure_reason  (void);\n\n// free the loaded image -- this is just free()\nSTBIDEF void     stbi_image_free      (void *retval_from_stbi_load);\n\n// get image dimensions & components without fully decoding\nSTBIDEF int      stbi_info_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp);\nSTBIDEF int      stbi_info_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp);\n\n#ifndef STBI_NO_STDIO\nSTBIDEF int      stbi_info            (char const *filename,     int *x, int *y, int *comp);\nSTBIDEF int      stbi_info_from_file  (FILE *f,                  int *x, int *y, int *comp);\n\n#endif\n\n\n\n// for image formats that explicitly notate that they have premultiplied alpha,\n// we just return the colors as stored in the file. set this flag to force\n// unpremultiplication. results are undefined if the unpremultiply overflow.\nSTBIDEF void stbi_set_unpremultiply_on_load(int flag_true_if_should_unpremultiply);\n\n// indicate whether we should process iphone images back to canonical format,\n// or just pass them through \"as-is\"\nSTBIDEF void stbi_convert_iphone_png_to_rgb(int flag_true_if_should_convert);\n\n// flip the image vertically, so the first pixel in the output array is the bottom left\nSTBIDEF void stbi_set_flip_vertically_on_load(int flag_true_if_should_flip);\n\n// ZLIB client - used by PNG, available for other purposes\n\nSTBIDEF char *stbi_zlib_decode_malloc_guesssize(const char *buffer, int len, int initial_size, int *outlen);\nSTBIDEF char *stbi_zlib_decode_malloc_guesssize_headerflag(const char *buffer, int len, int initial_size, int *outlen, int parse_header);\nSTBIDEF char *stbi_zlib_decode_malloc(const char *buffer, int len, int *outlen);\nSTBIDEF int   stbi_zlib_decode_buffer(char *obuffer, int olen, const char *ibuffer, int ilen);\n\nSTBIDEF char *stbi_zlib_decode_noheader_malloc(const char *buffer, int len, int *outlen);\nSTBIDEF int   stbi_zlib_decode_noheader_buffer(char *obuffer, int olen, const char *ibuffer, int ilen);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n//\n//\n////   end header file   /////////////////////////////////////////////////////\n#endif // STBI_INCLUDE_STB_IMAGE_H\n\n#ifdef STB_IMAGE_IMPLEMENTATION\n\n#if defined(STBI_ONLY_JPEG) || defined(STBI_ONLY_PNG) || defined(STBI_ONLY_BMP) \\\n  || defined(STBI_ONLY_TGA) || defined(STBI_ONLY_GIF) || defined(STBI_ONLY_PSD) \\\n  || defined(STBI_ONLY_HDR) || defined(STBI_ONLY_PIC) || defined(STBI_ONLY_PNM) \\\n  || defined(STBI_ONLY_ZLIB)\n   #ifndef STBI_ONLY_JPEG\n   #define STBI_NO_JPEG\n   #endif\n   #ifndef STBI_ONLY_PNG\n   #define STBI_NO_PNG\n   #endif\n   #ifndef STBI_ONLY_BMP\n   #define STBI_NO_BMP\n   #endif\n   #ifndef STBI_ONLY_PSD\n   #define STBI_NO_PSD\n   #endif\n   #ifndef STBI_ONLY_TGA\n   #define STBI_NO_TGA\n   #endif\n   #ifndef STBI_ONLY_GIF\n   #define STBI_NO_GIF\n   #endif\n   #ifndef STBI_ONLY_HDR\n   #define STBI_NO_HDR\n   #endif\n   #ifndef STBI_ONLY_PIC\n   #define STBI_NO_PIC\n   #endif\n   #ifndef STBI_ONLY_PNM\n   #define STBI_NO_PNM\n   #endif\n#endif\n\n#if defined(STBI_NO_PNG) && !defined(STBI_SUPPORT_ZLIB) && !defined(STBI_NO_ZLIB)\n#define STBI_NO_ZLIB\n#endif\n\n\n#include <stdarg.h>\n#include <stddef.h> // ptrdiff_t on osx\n#include <stdlib.h>\n#include <string.h>\n\n#if !defined(STBI_NO_LINEAR) || !defined(STBI_NO_HDR)\n#include <math.h>  // ldexp\n#endif\n\n#ifndef STBI_NO_STDIO\n#include <stdio.h>\n#endif\n\n#ifndef STBI_ASSERT\n#include <assert.h>\n#define STBI_ASSERT(x) assert(x)\n#endif\n\n\n#ifndef _MSC_VER\n   #ifdef __cplusplus\n   #define stbi_inline inline\n   #else\n   #define stbi_inline\n   #endif\n#else\n   #define stbi_inline __forceinline\n#endif\n\n\n#ifdef _MSC_VER\ntypedef unsigned short stbi__uint16;\ntypedef   signed short stbi__int16;\ntypedef unsigned int   stbi__uint32;\ntypedef   signed int   stbi__int32;\n#else\n#include <stdint.h>\ntypedef uint16_t stbi__uint16;\ntypedef int16_t  stbi__int16;\ntypedef uint32_t stbi__uint32;\ntypedef int32_t  stbi__int32;\n#endif\n\n// should produce compiler error if size is wrong\ntypedef unsigned char validate_uint32[sizeof(stbi__uint32)==4 ? 1 : -1];\n\n#ifdef _MSC_VER\n#define STBI_NOTUSED(v)  (void)(v)\n#else\n#define STBI_NOTUSED(v)  (void)sizeof(v)\n#endif\n\n#ifdef _MSC_VER\n#define STBI_HAS_LROTL\n#endif\n\n#ifdef STBI_HAS_LROTL\n   #define stbi_lrot(x,y)  _lrotl(x,y)\n#else\n   #define stbi_lrot(x,y)  (((x) << (y)) | ((x) >> (32 - (y))))\n#endif\n\n#if defined(STBI_MALLOC) && defined(STBI_FREE) && (defined(STBI_REALLOC) || defined(STBI_REALLOC_SIZED))\n// ok\n#elif !defined(STBI_MALLOC) && !defined(STBI_FREE) && !defined(STBI_REALLOC) && !defined(STBI_REALLOC_SIZED)\n// ok\n#else\n#error \"Must define all or none of STBI_MALLOC, STBI_FREE, and STBI_REALLOC (or STBI_REALLOC_SIZED).\"\n#endif\n\n#ifndef STBI_MALLOC\n#define STBI_MALLOC(sz)           malloc(sz)\n#define STBI_REALLOC(p,newsz)     realloc(p,newsz)\n#define STBI_FREE(p)              free(p)\n#endif\n\n#ifndef STBI_REALLOC_SIZED\n#define STBI_REALLOC_SIZED(p,oldsz,newsz) STBI_REALLOC(p,newsz)\n#endif\n\n// x86/x64 detection\n#if defined(__x86_64__) || defined(_M_X64)\n#define STBI__X64_TARGET\n#elif defined(__i386) || defined(_M_IX86)\n#define STBI__X86_TARGET\n#endif\n\n#if defined(__GNUC__) && (defined(STBI__X86_TARGET) || defined(STBI__X64_TARGET)) && !defined(__SSE2__) && !defined(STBI_NO_SIMD)\n// NOTE: not clear do we actually need this for the 64-bit path?\n// gcc doesn't support sse2 intrinsics unless you compile with -msse2,\n// (but compiling with -msse2 allows the compiler to use SSE2 everywhere;\n// this is just broken and gcc are jerks for not fixing it properly\n// http://www.virtualdub.org/blog/pivot/entry.php?id=363 )\n#define STBI_NO_SIMD\n#endif\n\n#if defined(__MINGW32__) && defined(STBI__X86_TARGET) && !defined(STBI_MINGW_ENABLE_SSE2) && !defined(STBI_NO_SIMD)\n// Note that __MINGW32__ doesn't actually mean 32-bit, so we have to avoid STBI__X64_TARGET\n//\n// 32-bit MinGW wants ESP to be 16-byte aligned, but this is not in the\n// Windows ABI and VC++ as well as Windows DLLs don't maintain that invariant.\n// As a result, enabling SSE2 on 32-bit MinGW is dangerous when not\n// simultaneously enabling \"-mstackrealign\".\n//\n// See https://github.com/nothings/stb/issues/81 for more information.\n//\n// So default to no SSE2 on 32-bit MinGW. If you've read this far and added\n// -mstackrealign to your build settings, feel free to #define STBI_MINGW_ENABLE_SSE2.\n#define STBI_NO_SIMD\n#endif\n\n#if !defined(STBI_NO_SIMD) && defined(STBI__X86_TARGET)\n#define STBI_SSE2\n#include <emmintrin.h>\n\n#ifdef _MSC_VER\n\n#if _MSC_VER >= 1400  // not VC6\n#include <intrin.h> // __cpuid\nstatic int stbi__cpuid3(void)\n{\n   int info[4];\n   __cpuid(info,1);\n   return info[3];\n}\n#else\nstatic int stbi__cpuid3(void)\n{\n   int res;\n   __asm {\n      mov  eax,1\n      cpuid\n      mov  res,edx\n   }\n   return res;\n}\n#endif\n\n#define STBI_SIMD_ALIGN(type, name) __declspec(align(16)) type name\n\nstatic int stbi__sse2_available()\n{\n   int info3 = stbi__cpuid3();\n   return ((info3 >> 26) & 1) != 0;\n}\n#else // assume GCC-style if not VC++\n#define STBI_SIMD_ALIGN(type, name) type name __attribute__((aligned(16)))\n\nstatic int stbi__sse2_available()\n{\n#if defined(__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__) >= 408 // GCC 4.8 or later\n   // GCC 4.8+ has a nice way to do this\n   return __builtin_cpu_supports(\"sse2\");\n#else\n   // portable way to do this, preferably without using GCC inline ASM?\n   // just bail for now.\n   return 0;\n#endif\n}\n#endif\n#endif\n\n// ARM NEON\n#if defined(STBI_NO_SIMD) && defined(STBI_NEON)\n#undef STBI_NEON\n#endif\n\n#ifdef STBI_NEON\n#include <arm_neon.h>\n// assume GCC or Clang on ARM targets\n#define STBI_SIMD_ALIGN(type, name) type name __attribute__((aligned(16)))\n#endif\n\n#ifndef STBI_SIMD_ALIGN\n#define STBI_SIMD_ALIGN(type, name) type name\n#endif\n\n///////////////////////////////////////////////\n//\n//  stbi__context struct and start_xxx functions\n\n// stbi__context structure is our basic context used by all images, so it\n// contains all the IO context, plus some basic image information\ntypedef struct\n{\n   stbi__uint32 img_x, img_y;\n   int img_n, img_out_n;\n\n   stbi_io_callbacks io;\n   void *io_user_data;\n\n   int read_from_callbacks;\n   int buflen;\n   stbi_uc buffer_start[128];\n\n   stbi_uc *img_buffer, *img_buffer_end;\n   stbi_uc *img_buffer_original, *img_buffer_original_end;\n} stbi__context;\n\n\nstatic void stbi__refill_buffer(stbi__context *s);\n\n// initialize a memory-decode context\nstatic void stbi__start_mem(stbi__context *s, stbi_uc const *buffer, int len)\n{\n   s->io.read = NULL;\n   s->read_from_callbacks = 0;\n   s->img_buffer = s->img_buffer_original = (stbi_uc *) buffer;\n   s->img_buffer_end = s->img_buffer_original_end = (stbi_uc *) buffer+len;\n}\n\n// initialize a callback-based context\nstatic void stbi__start_callbacks(stbi__context *s, stbi_io_callbacks *c, void *user)\n{\n   s->io = *c;\n   s->io_user_data = user;\n   s->buflen = sizeof(s->buffer_start);\n   s->read_from_callbacks = 1;\n   s->img_buffer_original = s->buffer_start;\n   stbi__refill_buffer(s);\n   s->img_buffer_original_end = s->img_buffer_end;\n}\n\n#ifndef STBI_NO_STDIO\n\nstatic int stbi__stdio_read(void *user, char *data, int size)\n{\n   return (int) fread(data,1,size,(FILE*) user);\n}\n\nstatic void stbi__stdio_skip(void *user, int n)\n{\n   fseek((FILE*) user, n, SEEK_CUR);\n}\n\nstatic int stbi__stdio_eof(void *user)\n{\n   return feof((FILE*) user);\n}\n\nstatic stbi_io_callbacks stbi__stdio_callbacks =\n{\n   stbi__stdio_read,\n   stbi__stdio_skip,\n   stbi__stdio_eof,\n};\n\nstatic void stbi__start_file(stbi__context *s, FILE *f)\n{\n   stbi__start_callbacks(s, &stbi__stdio_callbacks, (void *) f);\n}\n\n//static void stop_file(stbi__context *s) { }\n\n#endif // !STBI_NO_STDIO\n\nstatic void stbi__rewind(stbi__context *s)\n{\n   // conceptually rewind SHOULD rewind to the beginning of the stream,\n   // but we just rewind to the beginning of the initial buffer, because\n   // we only use it after doing 'test', which only ever looks at at most 92 bytes\n   s->img_buffer = s->img_buffer_original;\n   s->img_buffer_end = s->img_buffer_original_end;\n}\n\n#ifndef STBI_NO_JPEG\nstatic int      stbi__jpeg_test(stbi__context *s);\nstatic stbi_uc *stbi__jpeg_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__jpeg_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_PNG\nstatic int      stbi__png_test(stbi__context *s);\nstatic stbi_uc *stbi__png_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__png_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_BMP\nstatic int      stbi__bmp_test(stbi__context *s);\nstatic stbi_uc *stbi__bmp_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__bmp_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_TGA\nstatic int      stbi__tga_test(stbi__context *s);\nstatic stbi_uc *stbi__tga_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__tga_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_PSD\nstatic int      stbi__psd_test(stbi__context *s);\nstatic stbi_uc *stbi__psd_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__psd_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_HDR\nstatic int      stbi__hdr_test(stbi__context *s);\nstatic float   *stbi__hdr_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__hdr_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_PIC\nstatic int      stbi__pic_test(stbi__context *s);\nstatic stbi_uc *stbi__pic_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__pic_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_GIF\nstatic int      stbi__gif_test(stbi__context *s);\nstatic stbi_uc *stbi__gif_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__gif_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n#ifndef STBI_NO_PNM\nstatic int      stbi__pnm_test(stbi__context *s);\nstatic stbi_uc *stbi__pnm_load(stbi__context *s, int *x, int *y, int *comp, int req_comp);\nstatic int      stbi__pnm_info(stbi__context *s, int *x, int *y, int *comp);\n#endif\n\n// this is not threadsafe\nstatic const char *stbi__g_failure_reason;\n\nSTBIDEF const char *stbi_failure_reason(void)\n{\n   return stbi__g_failure_reason;\n}\n\nstatic int stbi__err(const char *str)\n{\n   stbi__g_failure_reason = str;\n   return 0;\n}\n\nstatic void *stbi__malloc(size_t size)\n{\n    return STBI_MALLOC(size);\n}\n\n// stbi__err - error\n// stbi__errpf - error returning pointer to float\n// stbi__errpuc - error returning pointer to unsigned char\n\n#ifdef STBI_NO_FAILURE_STRINGS\n   #define stbi__err(x,y)  0\n#elif defined(STBI_FAILURE_USERMSG)\n   #define stbi__err(x,y)  stbi__err(y)\n#else\n   #define stbi__err(x,y)  stbi__err(x)\n#endif\n\n#define stbi__errpf(x,y)   ((float *)(size_t) (stbi__err(x,y)?NULL:NULL))\n#define stbi__errpuc(x,y)  ((unsigned char *)(size_t) (stbi__err(x,y)?NULL:NULL))\n\nSTBIDEF void stbi_image_free(void *retval_from_stbi_load)\n{\n   STBI_FREE(retval_from_stbi_load);\n}\n\n#ifndef STBI_NO_LINEAR\nstatic float   *stbi__ldr_to_hdr(stbi_uc *data, int x, int y, int comp);\n#endif\n\n#ifndef STBI_NO_HDR\nstatic stbi_uc *stbi__hdr_to_ldr(float   *data, int x, int y, int comp);\n#endif\n\nstatic int stbi__vertically_flip_on_load = 0;\n\nSTBIDEF void stbi_set_flip_vertically_on_load(int flag_true_if_should_flip)\n{\n    stbi__vertically_flip_on_load = flag_true_if_should_flip;\n}\n\nstatic unsigned char *stbi__load_main(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   #ifndef STBI_NO_JPEG\n   if (stbi__jpeg_test(s)) return stbi__jpeg_load(s,x,y,comp,req_comp);\n   #endif\n   #ifndef STBI_NO_PNG\n   if (stbi__png_test(s))  return stbi__png_load(s,x,y,comp,req_comp);\n   #endif\n   #ifndef STBI_NO_BMP\n   if (stbi__bmp_test(s))  return stbi__bmp_load(s,x,y,comp,req_comp);\n   #endif\n   #ifndef STBI_NO_GIF\n   if (stbi__gif_test(s))  return stbi__gif_load(s,x,y,comp,req_comp);\n   #endif\n   #ifndef STBI_NO_PSD\n   if (stbi__psd_test(s))  return stbi__psd_load(s,x,y,comp,req_comp);\n   #endif\n   #ifndef STBI_NO_PIC\n   if (stbi__pic_test(s))  return stbi__pic_load(s,x,y,comp,req_comp);\n   #endif\n   #ifndef STBI_NO_PNM\n   if (stbi__pnm_test(s))  return stbi__pnm_load(s,x,y,comp,req_comp);\n   #endif\n\n   #ifndef STBI_NO_HDR\n   if (stbi__hdr_test(s)) {\n      float *hdr = stbi__hdr_load(s, x,y,comp,req_comp);\n      return stbi__hdr_to_ldr(hdr, *x, *y, req_comp ? req_comp : *comp);\n   }\n   #endif\n\n   #ifndef STBI_NO_TGA\n   // test tga last because it's a crappy test!\n   if (stbi__tga_test(s))\n      return stbi__tga_load(s,x,y,comp,req_comp);\n   #endif\n\n   return stbi__errpuc(\"unknown image type\", \"Image not of any known type, or corrupt\");\n}\n\nstatic unsigned char *stbi__load_flip(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   unsigned char *result = stbi__load_main(s, x, y, comp, req_comp);\n\n   if (stbi__vertically_flip_on_load && result != NULL) {\n      int w = *x, h = *y;\n      int depth = req_comp ? req_comp : *comp;\n      int row,col,z;\n      stbi_uc temp;\n\n      // @OPTIMIZE: use a bigger temp buffer and memcpy multiple pixels at once\n      for (row = 0; row < (h>>1); row++) {\n         for (col = 0; col < w; col++) {\n            for (z = 0; z < depth; z++) {\n               temp = result[(row * w + col) * depth + z];\n               result[(row * w + col) * depth + z] = result[((h - row - 1) * w + col) * depth + z];\n               result[((h - row - 1) * w + col) * depth + z] = temp;\n            }\n         }\n      }\n   }\n\n   return result;\n}\n\n#ifndef STBI_NO_HDR\nstatic void stbi__float_postprocess(float *result, int *x, int *y, int *comp, int req_comp)\n{\n   if (stbi__vertically_flip_on_load && result != NULL) {\n      int w = *x, h = *y;\n      int depth = req_comp ? req_comp : *comp;\n      int row,col,z;\n      float temp;\n\n      // @OPTIMIZE: use a bigger temp buffer and memcpy multiple pixels at once\n      for (row = 0; row < (h>>1); row++) {\n         for (col = 0; col < w; col++) {\n            for (z = 0; z < depth; z++) {\n               temp = result[(row * w + col) * depth + z];\n               result[(row * w + col) * depth + z] = result[((h - row - 1) * w + col) * depth + z];\n               result[((h - row - 1) * w + col) * depth + z] = temp;\n            }\n         }\n      }\n   }\n}\n#endif\n\n#ifndef STBI_NO_STDIO\n\nstatic FILE *stbi__fopen(char const *filename, char const *mode)\n{\n   FILE *f;\n#if defined(_MSC_VER) && _MSC_VER >= 1400\n   if (0 != fopen_s(&f, filename, mode))\n      f=0;\n#else\n   f = fopen(filename, mode);\n#endif\n   return f;\n}\n\n\nSTBIDEF stbi_uc *stbi_load(char const *filename, int *x, int *y, int *comp, int req_comp)\n{\n   FILE *f = stbi__fopen(filename, \"rb\");\n   unsigned char *result;\n   if (!f) return stbi__errpuc(\"can't fopen\", \"Unable to open file\");\n   result = stbi_load_from_file(f,x,y,comp,req_comp);\n   fclose(f);\n   return result;\n}\n\nSTBIDEF stbi_uc *stbi_load_from_file(FILE *f, int *x, int *y, int *comp, int req_comp)\n{\n   unsigned char *result;\n   stbi__context s;\n   stbi__start_file(&s,f);\n   result = stbi__load_flip(&s,x,y,comp,req_comp);\n   if (result) {\n      // need to 'unget' all the characters in the IO buffer\n      fseek(f, - (int) (s.img_buffer_end - s.img_buffer), SEEK_CUR);\n   }\n   return result;\n}\n#endif //!STBI_NO_STDIO\n\nSTBIDEF stbi_uc *stbi_load_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__context s;\n   stbi__start_mem(&s,buffer,len);\n   return stbi__load_flip(&s,x,y,comp,req_comp);\n}\n\nSTBIDEF stbi_uc *stbi_load_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__context s;\n   stbi__start_callbacks(&s, (stbi_io_callbacks *) clbk, user);\n   return stbi__load_flip(&s,x,y,comp,req_comp);\n}\n\n#ifndef STBI_NO_LINEAR\nstatic float *stbi__loadf_main(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   unsigned char *data;\n   #ifndef STBI_NO_HDR\n   if (stbi__hdr_test(s)) {\n      float *hdr_data = stbi__hdr_load(s,x,y,comp,req_comp);\n      if (hdr_data)\n         stbi__float_postprocess(hdr_data,x,y,comp,req_comp);\n      return hdr_data;\n   }\n   #endif\n   data = stbi__load_flip(s, x, y, comp, req_comp);\n   if (data)\n      return stbi__ldr_to_hdr(data, *x, *y, req_comp ? req_comp : *comp);\n   return stbi__errpf(\"unknown image type\", \"Image not of any known type, or corrupt\");\n}\n\nSTBIDEF float *stbi_loadf_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__context s;\n   stbi__start_mem(&s,buffer,len);\n   return stbi__loadf_main(&s,x,y,comp,req_comp);\n}\n\nSTBIDEF float *stbi_loadf_from_callbacks(stbi_io_callbacks const *clbk, void *user, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__context s;\n   stbi__start_callbacks(&s, (stbi_io_callbacks *) clbk, user);\n   return stbi__loadf_main(&s,x,y,comp,req_comp);\n}\n\n#ifndef STBI_NO_STDIO\nSTBIDEF float *stbi_loadf(char const *filename, int *x, int *y, int *comp, int req_comp)\n{\n   float *result;\n   FILE *f = stbi__fopen(filename, \"rb\");\n   if (!f) return stbi__errpf(\"can't fopen\", \"Unable to open file\");\n   result = stbi_loadf_from_file(f,x,y,comp,req_comp);\n   fclose(f);\n   return result;\n}\n\nSTBIDEF float *stbi_loadf_from_file(FILE *f, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__context s;\n   stbi__start_file(&s,f);\n   return stbi__loadf_main(&s,x,y,comp,req_comp);\n}\n#endif // !STBI_NO_STDIO\n\n#endif // !STBI_NO_LINEAR\n\n// these is-hdr-or-not is defined independent of whether STBI_NO_LINEAR is\n// defined, for API simplicity; if STBI_NO_LINEAR is defined, it always\n// reports false!\n\nSTBIDEF int stbi_is_hdr_from_memory(stbi_uc const *buffer, int len)\n{\n   #ifndef STBI_NO_HDR\n   stbi__context s;\n   stbi__start_mem(&s,buffer,len);\n   return stbi__hdr_test(&s);\n   #else\n   STBI_NOTUSED(buffer);\n   STBI_NOTUSED(len);\n   return 0;\n   #endif\n}\n\n#ifndef STBI_NO_STDIO\nSTBIDEF int      stbi_is_hdr          (char const *filename)\n{\n   FILE *f = stbi__fopen(filename, \"rb\");\n   int result=0;\n   if (f) {\n      result = stbi_is_hdr_from_file(f);\n      fclose(f);\n   }\n   return result;\n}\n\nSTBIDEF int      stbi_is_hdr_from_file(FILE *f)\n{\n   #ifndef STBI_NO_HDR\n   stbi__context s;\n   stbi__start_file(&s,f);\n   return stbi__hdr_test(&s);\n   #else\n   STBI_NOTUSED(f);\n   return 0;\n   #endif\n}\n#endif // !STBI_NO_STDIO\n\nSTBIDEF int      stbi_is_hdr_from_callbacks(stbi_io_callbacks const *clbk, void *user)\n{\n   #ifndef STBI_NO_HDR\n   stbi__context s;\n   stbi__start_callbacks(&s, (stbi_io_callbacks *) clbk, user);\n   return stbi__hdr_test(&s);\n   #else\n   STBI_NOTUSED(clbk);\n   STBI_NOTUSED(user);\n   return 0;\n   #endif\n}\n\n#ifndef STBI_NO_LINEAR\nstatic float stbi__l2h_gamma=2.2f, stbi__l2h_scale=1.0f;\n\nSTBIDEF void   stbi_ldr_to_hdr_gamma(float gamma) { stbi__l2h_gamma = gamma; }\nSTBIDEF void   stbi_ldr_to_hdr_scale(float scale) { stbi__l2h_scale = scale; }\n#endif\n\nstatic float stbi__h2l_gamma_i=1.0f/2.2f, stbi__h2l_scale_i=1.0f;\n\nSTBIDEF void   stbi_hdr_to_ldr_gamma(float gamma) { stbi__h2l_gamma_i = 1/gamma; }\nSTBIDEF void   stbi_hdr_to_ldr_scale(float scale) { stbi__h2l_scale_i = 1/scale; }\n\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// Common code used by all image loaders\n//\n\nenum\n{\n   STBI__SCAN_load=0,\n   STBI__SCAN_type,\n   STBI__SCAN_header\n};\n\nstatic void stbi__refill_buffer(stbi__context *s)\n{\n   int n = (s->io.read)(s->io_user_data,(char*)s->buffer_start,s->buflen);\n   if (n == 0) {\n      // at end of file, treat same as if from memory, but need to handle case\n      // where s->img_buffer isn't pointing to safe memory, e.g. 0-byte file\n      s->read_from_callbacks = 0;\n      s->img_buffer = s->buffer_start;\n      s->img_buffer_end = s->buffer_start+1;\n      *s->img_buffer = 0;\n   } else {\n      s->img_buffer = s->buffer_start;\n      s->img_buffer_end = s->buffer_start + n;\n   }\n}\n\nstbi_inline static stbi_uc stbi__get8(stbi__context *s)\n{\n   if (s->img_buffer < s->img_buffer_end)\n      return *s->img_buffer++;\n   if (s->read_from_callbacks) {\n      stbi__refill_buffer(s);\n      return *s->img_buffer++;\n   }\n   return 0;\n}\n\nstbi_inline static int stbi__at_eof(stbi__context *s)\n{\n   if (s->io.read) {\n      if (!(s->io.eof)(s->io_user_data)) return 0;\n      // if feof() is true, check if buffer = end\n      // special case: we've only got the special 0 character at the end\n      if (s->read_from_callbacks == 0) return 1;\n   }\n\n   return s->img_buffer >= s->img_buffer_end;\n}\n\nstatic void stbi__skip(stbi__context *s, int n)\n{\n   if (n < 0) {\n      s->img_buffer = s->img_buffer_end;\n      return;\n   }\n   if (s->io.read) {\n      int blen = (int) (s->img_buffer_end - s->img_buffer);\n      if (blen < n) {\n         s->img_buffer = s->img_buffer_end;\n         (s->io.skip)(s->io_user_data, n - blen);\n         return;\n      }\n   }\n   s->img_buffer += n;\n}\n\nstatic int stbi__getn(stbi__context *s, stbi_uc *buffer, int n)\n{\n   if (s->io.read) {\n      int blen = (int) (s->img_buffer_end - s->img_buffer);\n      if (blen < n) {\n         int res, count;\n\n         memcpy(buffer, s->img_buffer, blen);\n\n         count = (s->io.read)(s->io_user_data, (char*) buffer + blen, n - blen);\n         res = (count == (n-blen));\n         s->img_buffer = s->img_buffer_end;\n         return res;\n      }\n   }\n\n   if (s->img_buffer+n <= s->img_buffer_end) {\n      memcpy(buffer, s->img_buffer, n);\n      s->img_buffer += n;\n      return 1;\n   } else\n      return 0;\n}\n\nstatic int stbi__get16be(stbi__context *s)\n{\n   int z = stbi__get8(s);\n   return (z << 8) + stbi__get8(s);\n}\n\nstatic stbi__uint32 stbi__get32be(stbi__context *s)\n{\n   stbi__uint32 z = stbi__get16be(s);\n   return (z << 16) + stbi__get16be(s);\n}\n\n#if defined(STBI_NO_BMP) && defined(STBI_NO_TGA) && defined(STBI_NO_GIF)\n// nothing\n#else\nstatic int stbi__get16le(stbi__context *s)\n{\n   int z = stbi__get8(s);\n   return z + (stbi__get8(s) << 8);\n}\n#endif\n\n#ifndef STBI_NO_BMP\nstatic stbi__uint32 stbi__get32le(stbi__context *s)\n{\n   stbi__uint32 z = stbi__get16le(s);\n   return z + (stbi__get16le(s) << 16);\n}\n#endif\n\n#define STBI__BYTECAST(x)  ((stbi_uc) ((x) & 255))  // truncate int to byte without warnings\n\n\n//////////////////////////////////////////////////////////////////////////////\n//\n//  generic converter from built-in img_n to req_comp\n//    individual types do this automatically as much as possible (e.g. jpeg\n//    does all cases internally since it needs to colorspace convert anyway,\n//    and it never has alpha, so very few cases ). png can automatically\n//    interleave an alpha=255 channel, but falls back to this for other cases\n//\n//  assume data buffer is malloced, so malloc a new one and free that one\n//  only failure mode is malloc failing\n\nstatic stbi_uc stbi__compute_y(int r, int g, int b)\n{\n   return (stbi_uc) (((r*77) + (g*150) +  (29*b)) >> 8);\n}\n\nstatic unsigned char *stbi__convert_format(unsigned char *data, int img_n, int req_comp, unsigned int x, unsigned int y)\n{\n   int i,j;\n   unsigned char *good;\n\n   if (req_comp == img_n) return data;\n   STBI_ASSERT(req_comp >= 1 && req_comp <= 4);\n\n   good = (unsigned char *) stbi__malloc(req_comp * x * y);\n   if (good == NULL) {\n      STBI_FREE(data);\n      return stbi__errpuc(\"outofmem\", \"Out of memory\");\n   }\n\n   for (j=0; j < (int) y; ++j) {\n      unsigned char *src  = data + j * x * img_n   ;\n      unsigned char *dest = good + j * x * req_comp;\n\n      #define COMBO(a,b)  ((a)*8+(b))\n      #define CASE(a,b)   case COMBO(a,b): for(i=x-1; i >= 0; --i, src += a, dest += b)\n      // convert source image with img_n components to one with req_comp components;\n      // avoid switch per pixel, so use switch per scanline and massive macros\n      switch (COMBO(img_n, req_comp)) {\n         CASE(1,2) dest[0]=src[0], dest[1]=255; break;\n         CASE(1,3) dest[0]=dest[1]=dest[2]=src[0]; break;\n         CASE(1,4) dest[0]=dest[1]=dest[2]=src[0], dest[3]=255; break;\n         CASE(2,1) dest[0]=src[0]; break;\n         CASE(2,3) dest[0]=dest[1]=dest[2]=src[0]; break;\n         CASE(2,4) dest[0]=dest[1]=dest[2]=src[0], dest[3]=src[1]; break;\n         CASE(3,4) dest[0]=src[0],dest[1]=src[1],dest[2]=src[2],dest[3]=255; break;\n         CASE(3,1) dest[0]=stbi__compute_y(src[0],src[1],src[2]); break;\n         CASE(3,2) dest[0]=stbi__compute_y(src[0],src[1],src[2]), dest[1] = 255; break;\n         CASE(4,1) dest[0]=stbi__compute_y(src[0],src[1],src[2]); break;\n         CASE(4,2) dest[0]=stbi__compute_y(src[0],src[1],src[2]), dest[1] = src[3]; break;\n         CASE(4,3) dest[0]=src[0],dest[1]=src[1],dest[2]=src[2]; break;\n         default: STBI_ASSERT(0);\n      }\n      #undef CASE\n   }\n\n   STBI_FREE(data);\n   return good;\n}\n\n#ifndef STBI_NO_LINEAR\nstatic float   *stbi__ldr_to_hdr(stbi_uc *data, int x, int y, int comp)\n{\n   int i,k,n;\n   float *output = (float *) stbi__malloc(x * y * comp * sizeof(float));\n   if (output == NULL) { STBI_FREE(data); return stbi__errpf(\"outofmem\", \"Out of memory\"); }\n   // compute number of non-alpha components\n   if (comp & 1) n = comp; else n = comp-1;\n   for (i=0; i < x*y; ++i) {\n      for (k=0; k < n; ++k) {\n         output[i*comp + k] = (float) (pow(data[i*comp+k]/255.0f, stbi__l2h_gamma) * stbi__l2h_scale);\n      }\n      if (k < comp) output[i*comp + k] = data[i*comp+k]/255.0f;\n   }\n   STBI_FREE(data);\n   return output;\n}\n#endif\n\n#ifndef STBI_NO_HDR\n#define stbi__float2int(x)   ((int) (x))\nstatic stbi_uc *stbi__hdr_to_ldr(float   *data, int x, int y, int comp)\n{\n   int i,k,n;\n   stbi_uc *output = (stbi_uc *) stbi__malloc(x * y * comp);\n   if (output == NULL) { STBI_FREE(data); return stbi__errpuc(\"outofmem\", \"Out of memory\"); }\n   // compute number of non-alpha components\n   if (comp & 1) n = comp; else n = comp-1;\n   for (i=0; i < x*y; ++i) {\n      for (k=0; k < n; ++k) {\n         float z = (float) pow(data[i*comp+k]*stbi__h2l_scale_i, stbi__h2l_gamma_i) * 255 + 0.5f;\n         if (z < 0) z = 0;\n         if (z > 255) z = 255;\n         output[i*comp + k] = (stbi_uc) stbi__float2int(z);\n      }\n      if (k < comp) {\n         float z = data[i*comp+k] * 255 + 0.5f;\n         if (z < 0) z = 0;\n         if (z > 255) z = 255;\n         output[i*comp + k] = (stbi_uc) stbi__float2int(z);\n      }\n   }\n   STBI_FREE(data);\n   return output;\n}\n#endif\n\n//////////////////////////////////////////////////////////////////////////////\n//\n//  \"baseline\" JPEG/JFIF decoder\n//\n//    simple implementation\n//      - doesn't support delayed output of y-dimension\n//      - simple interface (only one output format: 8-bit interleaved RGB)\n//      - doesn't try to recover corrupt jpegs\n//      - doesn't allow partial loading, loading multiple at once\n//      - still fast on x86 (copying globals into locals doesn't help x86)\n//      - allocates lots of intermediate memory (full size of all components)\n//        - non-interleaved case requires this anyway\n//        - allows good upsampling (see next)\n//    high-quality\n//      - upsampled channels are bilinearly interpolated, even across blocks\n//      - quality integer IDCT derived from IJG's 'slow'\n//    performance\n//      - fast huffman; reasonable integer IDCT\n//      - some SIMD kernels for common paths on targets with SSE2/NEON\n//      - uses a lot of intermediate memory, could cache poorly\n\n#ifndef STBI_NO_JPEG\n\n// huffman decoding acceleration\n#define FAST_BITS   9  // larger handles more cases; smaller stomps less cache\n\ntypedef struct\n{\n   stbi_uc  fast[1 << FAST_BITS];\n   // weirdly, repacking this into AoS is a 10% speed loss, instead of a win\n   stbi__uint16 code[256];\n   stbi_uc  values[256];\n   stbi_uc  size[257];\n   unsigned int maxcode[18];\n   int    delta[17];   // old 'firstsymbol' - old 'firstcode'\n} stbi__huffman;\n\ntypedef struct\n{\n   stbi__context *s;\n   stbi__huffman huff_dc[4];\n   stbi__huffman huff_ac[4];\n   stbi_uc dequant[4][64];\n   stbi__int16 fast_ac[4][1 << FAST_BITS];\n\n// sizes for components, interleaved MCUs\n   int img_h_max, img_v_max;\n   int img_mcu_x, img_mcu_y;\n   int img_mcu_w, img_mcu_h;\n\n// definition of jpeg image component\n   struct\n   {\n      int id;\n      int h,v;\n      int tq;\n      int hd,ha;\n      int dc_pred;\n\n      int x,y,w2,h2;\n      stbi_uc *data;\n      void *raw_data, *raw_coeff;\n      stbi_uc *linebuf;\n      short   *coeff;   // progressive only\n      int      coeff_w, coeff_h; // number of 8x8 coefficient blocks\n   } img_comp[4];\n\n   stbi__uint32   code_buffer; // jpeg entropy-coded buffer\n   int            code_bits;   // number of valid bits\n   unsigned char  marker;      // marker seen while filling entropy buffer\n   int            nomore;      // flag if we saw a marker so must stop\n\n   int            progressive;\n   int            spec_start;\n   int            spec_end;\n   int            succ_high;\n   int            succ_low;\n   int            eob_run;\n\n   int scan_n, order[4];\n   int restart_interval, todo;\n\n// kernels\n   void (*idct_block_kernel)(stbi_uc *out, int out_stride, short data[64]);\n   void (*YCbCr_to_RGB_kernel)(stbi_uc *out, const stbi_uc *y, const stbi_uc *pcb, const stbi_uc *pcr, int count, int step);\n   stbi_uc *(*resample_row_hv_2_kernel)(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs);\n} stbi__jpeg;\n\nstatic int stbi__build_huffman(stbi__huffman *h, int *count)\n{\n   int i,j,k=0,code;\n   // build size list for each symbol (from JPEG spec)\n   for (i=0; i < 16; ++i)\n      for (j=0; j < count[i]; ++j)\n         h->size[k++] = (stbi_uc) (i+1);\n   h->size[k] = 0;\n\n   // compute actual symbols (from jpeg spec)\n   code = 0;\n   k = 0;\n   for(j=1; j <= 16; ++j) {\n      // compute delta to add to code to compute symbol id\n      h->delta[j] = k - code;\n      if (h->size[k] == j) {\n         while (h->size[k] == j)\n            h->code[k++] = (stbi__uint16) (code++);\n         if (code-1 >= (1 << j)) return stbi__err(\"bad code lengths\",\"Corrupt JPEG\");\n      }\n      // compute largest code + 1 for this size, preshifted as needed later\n      h->maxcode[j] = code << (16-j);\n      code <<= 1;\n   }\n   h->maxcode[j] = 0xffffffff;\n\n   // build non-spec acceleration table; 255 is flag for not-accelerated\n   memset(h->fast, 255, 1 << FAST_BITS);\n   for (i=0; i < k; ++i) {\n      int s = h->size[i];\n      if (s <= FAST_BITS) {\n         int c = h->code[i] << (FAST_BITS-s);\n         int m = 1 << (FAST_BITS-s);\n         for (j=0; j < m; ++j) {\n            h->fast[c+j] = (stbi_uc) i;\n         }\n      }\n   }\n   return 1;\n}\n\n// build a table that decodes both magnitude and value of small ACs in\n// one go.\nstatic void stbi__build_fast_ac(stbi__int16 *fast_ac, stbi__huffman *h)\n{\n   int i;\n   for (i=0; i < (1 << FAST_BITS); ++i) {\n      stbi_uc fast = h->fast[i];\n      fast_ac[i] = 0;\n      if (fast < 255) {\n         int rs = h->values[fast];\n         int run = (rs >> 4) & 15;\n         int magbits = rs & 15;\n         int len = h->size[fast];\n\n         if (magbits && len + magbits <= FAST_BITS) {\n            // magnitude code followed by receive_extend code\n            int k = ((i << len) & ((1 << FAST_BITS) - 1)) >> (FAST_BITS - magbits);\n            int m = 1 << (magbits - 1);\n            if (k < m) k += (-1 << magbits) + 1;\n            // if the result is small enough, we can fit it in fast_ac table\n            if (k >= -128 && k <= 127)\n               fast_ac[i] = (stbi__int16) ((k << 8) + (run << 4) + (len + magbits));\n         }\n      }\n   }\n}\n\nstatic void stbi__grow_buffer_unsafe(stbi__jpeg *j)\n{\n   do {\n      int b = j->nomore ? 0 : stbi__get8(j->s);\n      if (b == 0xff) {\n         int c = stbi__get8(j->s);\n         if (c != 0) {\n            j->marker = (unsigned char) c;\n            j->nomore = 1;\n            return;\n         }\n      }\n      j->code_buffer |= b << (24 - j->code_bits);\n      j->code_bits += 8;\n   } while (j->code_bits <= 24);\n}\n\n// (1 << n) - 1\nstatic stbi__uint32 stbi__bmask[17]={0,1,3,7,15,31,63,127,255,511,1023,2047,4095,8191,16383,32767,65535};\n\n// decode a jpeg huffman value from the bitstream\nstbi_inline static int stbi__jpeg_huff_decode(stbi__jpeg *j, stbi__huffman *h)\n{\n   unsigned int temp;\n   int c,k;\n\n   if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);\n\n   // look at the top FAST_BITS and determine what symbol ID it is,\n   // if the code is <= FAST_BITS\n   c = (j->code_buffer >> (32 - FAST_BITS)) & ((1 << FAST_BITS)-1);\n   k = h->fast[c];\n   if (k < 255) {\n      int s = h->size[k];\n      if (s > j->code_bits)\n         return -1;\n      j->code_buffer <<= s;\n      j->code_bits -= s;\n      return h->values[k];\n   }\n\n   // naive test is to shift the code_buffer down so k bits are\n   // valid, then test against maxcode. To speed this up, we've\n   // preshifted maxcode left so that it has (16-k) 0s at the\n   // end; in other words, regardless of the number of bits, it\n   // wants to be compared against something shifted to have 16;\n   // that way we don't need to shift inside the loop.\n   temp = j->code_buffer >> 16;\n   for (k=FAST_BITS+1 ; ; ++k)\n      if (temp < h->maxcode[k])\n         break;\n   if (k == 17) {\n      // error! code not found\n      j->code_bits -= 16;\n      return -1;\n   }\n\n   if (k > j->code_bits)\n      return -1;\n\n   // convert the huffman code to the symbol id\n   c = ((j->code_buffer >> (32 - k)) & stbi__bmask[k]) + h->delta[k];\n   STBI_ASSERT((((j->code_buffer) >> (32 - h->size[c])) & stbi__bmask[h->size[c]]) == h->code[c]);\n\n   // convert the id to a symbol\n   j->code_bits -= k;\n   j->code_buffer <<= k;\n   return h->values[c];\n}\n\n// bias[n] = (-1<<n) + 1\nstatic int const stbi__jbias[16] = {0,-1,-3,-7,-15,-31,-63,-127,-255,-511,-1023,-2047,-4095,-8191,-16383,-32767};\n\n// combined JPEG 'receive' and JPEG 'extend', since baseline\n// always extends everything it receives.\nstbi_inline static int stbi__extend_receive(stbi__jpeg *j, int n)\n{\n   unsigned int k;\n   int sgn;\n   if (j->code_bits < n) stbi__grow_buffer_unsafe(j);\n\n   sgn = (stbi__int32)j->code_buffer >> 31; // sign bit is always in MSB\n   k = stbi_lrot(j->code_buffer, n);\n   STBI_ASSERT(n >= 0 && n < (int) (sizeof(stbi__bmask)/sizeof(*stbi__bmask)));\n   j->code_buffer = k & ~stbi__bmask[n];\n   k &= stbi__bmask[n];\n   j->code_bits -= n;\n   return k + (stbi__jbias[n] & ~sgn);\n}\n\n// get some unsigned bits\nstbi_inline static int stbi__jpeg_get_bits(stbi__jpeg *j, int n)\n{\n   unsigned int k;\n   if (j->code_bits < n) stbi__grow_buffer_unsafe(j);\n   k = stbi_lrot(j->code_buffer, n);\n   j->code_buffer = k & ~stbi__bmask[n];\n   k &= stbi__bmask[n];\n   j->code_bits -= n;\n   return k;\n}\n\nstbi_inline static int stbi__jpeg_get_bit(stbi__jpeg *j)\n{\n   unsigned int k;\n   if (j->code_bits < 1) stbi__grow_buffer_unsafe(j);\n   k = j->code_buffer;\n   j->code_buffer <<= 1;\n   --j->code_bits;\n   return k & 0x80000000;\n}\n\n// given a value that's at position X in the zigzag stream,\n// where does it appear in the 8x8 matrix coded as row-major?\nstatic stbi_uc stbi__jpeg_dezigzag[64+15] =\n{\n    0,  1,  8, 16,  9,  2,  3, 10,\n   17, 24, 32, 25, 18, 11,  4,  5,\n   12, 19, 26, 33, 40, 48, 41, 34,\n   27, 20, 13,  6,  7, 14, 21, 28,\n   35, 42, 49, 56, 57, 50, 43, 36,\n   29, 22, 15, 23, 30, 37, 44, 51,\n   58, 59, 52, 45, 38, 31, 39, 46,\n   53, 60, 61, 54, 47, 55, 62, 63,\n   // let corrupt input sample past end\n   63, 63, 63, 63, 63, 63, 63, 63,\n   63, 63, 63, 63, 63, 63, 63\n};\n\n// decode one 64-entry block--\nstatic int stbi__jpeg_decode_block(stbi__jpeg *j, short data[64], stbi__huffman *hdc, stbi__huffman *hac, stbi__int16 *fac, int b, stbi_uc *dequant)\n{\n   int diff,dc,k;\n   int t;\n\n   if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);\n   t = stbi__jpeg_huff_decode(j, hdc);\n   if (t < 0) return stbi__err(\"bad huffman code\",\"Corrupt JPEG\");\n\n   // 0 all the ac values now so we can do it 32-bits at a time\n   memset(data,0,64*sizeof(data[0]));\n\n   diff = t ? stbi__extend_receive(j, t) : 0;\n   dc = j->img_comp[b].dc_pred + diff;\n   j->img_comp[b].dc_pred = dc;\n   data[0] = (short) (dc * dequant[0]);\n\n   // decode AC components, see JPEG spec\n   k = 1;\n   do {\n      unsigned int zig;\n      int c,r,s;\n      if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);\n      c = (j->code_buffer >> (32 - FAST_BITS)) & ((1 << FAST_BITS)-1);\n      r = fac[c];\n      if (r) { // fast-AC path\n         k += (r >> 4) & 15; // run\n         s = r & 15; // combined length\n         j->code_buffer <<= s;\n         j->code_bits -= s;\n         // decode into unzigzag'd location\n         zig = stbi__jpeg_dezigzag[k++];\n         data[zig] = (short) ((r >> 8) * dequant[zig]);\n      } else {\n         int rs = stbi__jpeg_huff_decode(j, hac);\n         if (rs < 0) return stbi__err(\"bad huffman code\",\"Corrupt JPEG\");\n         s = rs & 15;\n         r = rs >> 4;\n         if (s == 0) {\n            if (rs != 0xf0) break; // end block\n            k += 16;\n         } else {\n            k += r;\n            // decode into unzigzag'd location\n            zig = stbi__jpeg_dezigzag[k++];\n            data[zig] = (short) (stbi__extend_receive(j,s) * dequant[zig]);\n         }\n      }\n   } while (k < 64);\n   return 1;\n}\n\nstatic int stbi__jpeg_decode_block_prog_dc(stbi__jpeg *j, short data[64], stbi__huffman *hdc, int b)\n{\n   int diff,dc;\n   int t;\n   if (j->spec_end != 0) return stbi__err(\"can't merge dc and ac\", \"Corrupt JPEG\");\n\n   if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);\n\n   if (j->succ_high == 0) {\n      // first scan for DC coefficient, must be first\n      memset(data,0,64*sizeof(data[0])); // 0 all the ac values now\n      t = stbi__jpeg_huff_decode(j, hdc);\n      diff = t ? stbi__extend_receive(j, t) : 0;\n\n      dc = j->img_comp[b].dc_pred + diff;\n      j->img_comp[b].dc_pred = dc;\n      data[0] = (short) (dc << j->succ_low);\n   } else {\n      // refinement scan for DC coefficient\n      if (stbi__jpeg_get_bit(j))\n         data[0] += (short) (1 << j->succ_low);\n   }\n   return 1;\n}\n\n// @OPTIMIZE: store non-zigzagged during the decode passes,\n// and only de-zigzag when dequantizing\nstatic int stbi__jpeg_decode_block_prog_ac(stbi__jpeg *j, short data[64], stbi__huffman *hac, stbi__int16 *fac)\n{\n   int k;\n   if (j->spec_start == 0) return stbi__err(\"can't merge dc and ac\", \"Corrupt JPEG\");\n\n   if (j->succ_high == 0) {\n      int shift = j->succ_low;\n\n      if (j->eob_run) {\n         --j->eob_run;\n         return 1;\n      }\n\n      k = j->spec_start;\n      do {\n         unsigned int zig;\n         int c,r,s;\n         if (j->code_bits < 16) stbi__grow_buffer_unsafe(j);\n         c = (j->code_buffer >> (32 - FAST_BITS)) & ((1 << FAST_BITS)-1);\n         r = fac[c];\n         if (r) { // fast-AC path\n            k += (r >> 4) & 15; // run\n            s = r & 15; // combined length\n            j->code_buffer <<= s;\n            j->code_bits -= s;\n            zig = stbi__jpeg_dezigzag[k++];\n            data[zig] = (short) ((r >> 8) << shift);\n         } else {\n            int rs = stbi__jpeg_huff_decode(j, hac);\n            if (rs < 0) return stbi__err(\"bad huffman code\",\"Corrupt JPEG\");\n            s = rs & 15;\n            r = rs >> 4;\n            if (s == 0) {\n               if (r < 15) {\n                  j->eob_run = (1 << r);\n                  if (r)\n                     j->eob_run += stbi__jpeg_get_bits(j, r);\n                  --j->eob_run;\n                  break;\n               }\n               k += 16;\n            } else {\n               k += r;\n               zig = stbi__jpeg_dezigzag[k++];\n               data[zig] = (short) (stbi__extend_receive(j,s) << shift);\n            }\n         }\n      } while (k <= j->spec_end);\n   } else {\n      // refinement scan for these AC coefficients\n\n      short bit = (short) (1 << j->succ_low);\n\n      if (j->eob_run) {\n         --j->eob_run;\n         for (k = j->spec_start; k <= j->spec_end; ++k) {\n            short *p = &data[stbi__jpeg_dezigzag[k]];\n            if (*p != 0)\n               if (stbi__jpeg_get_bit(j))\n                  if ((*p & bit)==0) {\n                     if (*p > 0)\n                        *p += bit;\n                     else\n                        *p -= bit;\n                  }\n         }\n      } else {\n         k = j->spec_start;\n         do {\n            int r,s;\n            int rs = stbi__jpeg_huff_decode(j, hac); // @OPTIMIZE see if we can use the fast path here, advance-by-r is so slow, eh\n            if (rs < 0) return stbi__err(\"bad huffman code\",\"Corrupt JPEG\");\n            s = rs & 15;\n            r = rs >> 4;\n            if (s == 0) {\n               if (r < 15) {\n                  j->eob_run = (1 << r) - 1;\n                  if (r)\n                     j->eob_run += stbi__jpeg_get_bits(j, r);\n                  r = 64; // force end of block\n               } else {\n                  // r=15 s=0 should write 16 0s, so we just do\n                  // a run of 15 0s and then write s (which is 0),\n                  // so we don't have to do anything special here\n               }\n            } else {\n               if (s != 1) return stbi__err(\"bad huffman code\", \"Corrupt JPEG\");\n               // sign bit\n               if (stbi__jpeg_get_bit(j))\n                  s = bit;\n               else\n                  s = -bit;\n            }\n\n            // advance by r\n            while (k <= j->spec_end) {\n               short *p = &data[stbi__jpeg_dezigzag[k++]];\n               if (*p != 0) {\n                  if (stbi__jpeg_get_bit(j))\n                     if ((*p & bit)==0) {\n                        if (*p > 0)\n                           *p += bit;\n                        else\n                           *p -= bit;\n                     }\n               } else {\n                  if (r == 0) {\n                     *p = (short) s;\n                     break;\n                  }\n                  --r;\n               }\n            }\n         } while (k <= j->spec_end);\n      }\n   }\n   return 1;\n}\n\n// take a -128..127 value and stbi__clamp it and convert to 0..255\nstbi_inline static stbi_uc stbi__clamp(int x)\n{\n   // trick to use a single test to catch both cases\n   if ((unsigned int) x > 255) {\n      if (x < 0) return 0;\n      if (x > 255) return 255;\n   }\n   return (stbi_uc) x;\n}\n\n#define stbi__f2f(x)  ((int) (((x) * 4096 + 0.5)))\n#define stbi__fsh(x)  ((x) << 12)\n\n// derived from jidctint -- DCT_ISLOW\n#define STBI__IDCT_1D(s0,s1,s2,s3,s4,s5,s6,s7) \\\n   int t0,t1,t2,t3,p1,p2,p3,p4,p5,x0,x1,x2,x3; \\\n   p2 = s2;                                    \\\n   p3 = s6;                                    \\\n   p1 = (p2+p3) * stbi__f2f(0.5411961f);       \\\n   t2 = p1 + p3*stbi__f2f(-1.847759065f);      \\\n   t3 = p1 + p2*stbi__f2f( 0.765366865f);      \\\n   p2 = s0;                                    \\\n   p3 = s4;                                    \\\n   t0 = stbi__fsh(p2+p3);                      \\\n   t1 = stbi__fsh(p2-p3);                      \\\n   x0 = t0+t3;                                 \\\n   x3 = t0-t3;                                 \\\n   x1 = t1+t2;                                 \\\n   x2 = t1-t2;                                 \\\n   t0 = s7;                                    \\\n   t1 = s5;                                    \\\n   t2 = s3;                                    \\\n   t3 = s1;                                    \\\n   p3 = t0+t2;                                 \\\n   p4 = t1+t3;                                 \\\n   p1 = t0+t3;                                 \\\n   p2 = t1+t2;                                 \\\n   p5 = (p3+p4)*stbi__f2f( 1.175875602f);      \\\n   t0 = t0*stbi__f2f( 0.298631336f);           \\\n   t1 = t1*stbi__f2f( 2.053119869f);           \\\n   t2 = t2*stbi__f2f( 3.072711026f);           \\\n   t3 = t3*stbi__f2f( 1.501321110f);           \\\n   p1 = p5 + p1*stbi__f2f(-0.899976223f);      \\\n   p2 = p5 + p2*stbi__f2f(-2.562915447f);      \\\n   p3 = p3*stbi__f2f(-1.961570560f);           \\\n   p4 = p4*stbi__f2f(-0.390180644f);           \\\n   t3 += p1+p4;                                \\\n   t2 += p2+p3;                                \\\n   t1 += p2+p4;                                \\\n   t0 += p1+p3;\n\nstatic void stbi__idct_block(stbi_uc *out, int out_stride, short data[64])\n{\n   int i,val[64],*v=val;\n   stbi_uc *o;\n   short *d = data;\n\n   // columns\n   for (i=0; i < 8; ++i,++d, ++v) {\n      // if all zeroes, shortcut -- this avoids dequantizing 0s and IDCTing\n      if (d[ 8]==0 && d[16]==0 && d[24]==0 && d[32]==0\n           && d[40]==0 && d[48]==0 && d[56]==0) {\n         //    no shortcut                 0     seconds\n         //    (1|2|3|4|5|6|7)==0          0     seconds\n         //    all separate               -0.047 seconds\n         //    1 && 2|3 && 4|5 && 6|7:    -0.047 seconds\n         int dcterm = d[0] << 2;\n         v[0] = v[8] = v[16] = v[24] = v[32] = v[40] = v[48] = v[56] = dcterm;\n      } else {\n         STBI__IDCT_1D(d[ 0],d[ 8],d[16],d[24],d[32],d[40],d[48],d[56])\n         // constants scaled things up by 1<<12; let's bring them back\n         // down, but keep 2 extra bits of precision\n         x0 += 512; x1 += 512; x2 += 512; x3 += 512;\n         v[ 0] = (x0+t3) >> 10;\n         v[56] = (x0-t3) >> 10;\n         v[ 8] = (x1+t2) >> 10;\n         v[48] = (x1-t2) >> 10;\n         v[16] = (x2+t1) >> 10;\n         v[40] = (x2-t1) >> 10;\n         v[24] = (x3+t0) >> 10;\n         v[32] = (x3-t0) >> 10;\n      }\n   }\n\n   for (i=0, v=val, o=out; i < 8; ++i,v+=8,o+=out_stride) {\n      // no fast case since the first 1D IDCT spread components out\n      STBI__IDCT_1D(v[0],v[1],v[2],v[3],v[4],v[5],v[6],v[7])\n      // constants scaled things up by 1<<12, plus we had 1<<2 from first\n      // loop, plus horizontal and vertical each scale by sqrt(8) so together\n      // we've got an extra 1<<3, so 1<<17 total we need to remove.\n      // so we want to round that, which means adding 0.5 * 1<<17,\n      // aka 65536. Also, we'll end up with -128 to 127 that we want\n      // to encode as 0..255 by adding 128, so we'll add that before the shift\n      x0 += 65536 + (128<<17);\n      x1 += 65536 + (128<<17);\n      x2 += 65536 + (128<<17);\n      x3 += 65536 + (128<<17);\n      // tried computing the shifts into temps, or'ing the temps to see\n      // if any were out of range, but that was slower\n      o[0] = stbi__clamp((x0+t3) >> 17);\n      o[7] = stbi__clamp((x0-t3) >> 17);\n      o[1] = stbi__clamp((x1+t2) >> 17);\n      o[6] = stbi__clamp((x1-t2) >> 17);\n      o[2] = stbi__clamp((x2+t1) >> 17);\n      o[5] = stbi__clamp((x2-t1) >> 17);\n      o[3] = stbi__clamp((x3+t0) >> 17);\n      o[4] = stbi__clamp((x3-t0) >> 17);\n   }\n}\n\n#ifdef STBI_SSE2\n// sse2 integer IDCT. not the fastest possible implementation but it\n// produces bit-identical results to the generic C version so it's\n// fully \"transparent\".\nstatic void stbi__idct_simd(stbi_uc *out, int out_stride, short data[64])\n{\n   // This is constructed to match our regular (generic) integer IDCT exactly.\n   __m128i row0, row1, row2, row3, row4, row5, row6, row7;\n   __m128i tmp;\n\n   // dot product constant: even elems=x, odd elems=y\n   #define dct_const(x,y)  _mm_setr_epi16((x),(y),(x),(y),(x),(y),(x),(y))\n\n   // out(0) = c0[even]*x + c0[odd]*y   (c0, x, y 16-bit, out 32-bit)\n   // out(1) = c1[even]*x + c1[odd]*y\n   #define dct_rot(out0,out1, x,y,c0,c1) \\\n      __m128i c0##lo = _mm_unpacklo_epi16((x),(y)); \\\n      __m128i c0##hi = _mm_unpackhi_epi16((x),(y)); \\\n      __m128i out0##_l = _mm_madd_epi16(c0##lo, c0); \\\n      __m128i out0##_h = _mm_madd_epi16(c0##hi, c0); \\\n      __m128i out1##_l = _mm_madd_epi16(c0##lo, c1); \\\n      __m128i out1##_h = _mm_madd_epi16(c0##hi, c1)\n\n   // out = in << 12  (in 16-bit, out 32-bit)\n   #define dct_widen(out, in) \\\n      __m128i out##_l = _mm_srai_epi32(_mm_unpacklo_epi16(_mm_setzero_si128(), (in)), 4); \\\n      __m128i out##_h = _mm_srai_epi32(_mm_unpackhi_epi16(_mm_setzero_si128(), (in)), 4)\n\n   // wide add\n   #define dct_wadd(out, a, b) \\\n      __m128i out##_l = _mm_add_epi32(a##_l, b##_l); \\\n      __m128i out##_h = _mm_add_epi32(a##_h, b##_h)\n\n   // wide sub\n   #define dct_wsub(out, a, b) \\\n      __m128i out##_l = _mm_sub_epi32(a##_l, b##_l); \\\n      __m128i out##_h = _mm_sub_epi32(a##_h, b##_h)\n\n   // butterfly a/b, add bias, then shift by \"s\" and pack\n   #define dct_bfly32o(out0, out1, a,b,bias,s) \\\n      { \\\n         __m128i abiased_l = _mm_add_epi32(a##_l, bias); \\\n         __m128i abiased_h = _mm_add_epi32(a##_h, bias); \\\n         dct_wadd(sum, abiased, b); \\\n         dct_wsub(dif, abiased, b); \\\n         out0 = _mm_packs_epi32(_mm_srai_epi32(sum_l, s), _mm_srai_epi32(sum_h, s)); \\\n         out1 = _mm_packs_epi32(_mm_srai_epi32(dif_l, s), _mm_srai_epi32(dif_h, s)); \\\n      }\n\n   // 8-bit interleave step (for transposes)\n   #define dct_interleave8(a, b) \\\n      tmp = a; \\\n      a = _mm_unpacklo_epi8(a, b); \\\n      b = _mm_unpackhi_epi8(tmp, b)\n\n   // 16-bit interleave step (for transposes)\n   #define dct_interleave16(a, b) \\\n      tmp = a; \\\n      a = _mm_unpacklo_epi16(a, b); \\\n      b = _mm_unpackhi_epi16(tmp, b)\n\n   #define dct_pass(bias,shift) \\\n      { \\\n         /* even part */ \\\n         dct_rot(t2e,t3e, row2,row6, rot0_0,rot0_1); \\\n         __m128i sum04 = _mm_add_epi16(row0, row4); \\\n         __m128i dif04 = _mm_sub_epi16(row0, row4); \\\n         dct_widen(t0e, sum04); \\\n         dct_widen(t1e, dif04); \\\n         dct_wadd(x0, t0e, t3e); \\\n         dct_wsub(x3, t0e, t3e); \\\n         dct_wadd(x1, t1e, t2e); \\\n         dct_wsub(x2, t1e, t2e); \\\n         /* odd part */ \\\n         dct_rot(y0o,y2o, row7,row3, rot2_0,rot2_1); \\\n         dct_rot(y1o,y3o, row5,row1, rot3_0,rot3_1); \\\n         __m128i sum17 = _mm_add_epi16(row1, row7); \\\n         __m128i sum35 = _mm_add_epi16(row3, row5); \\\n         dct_rot(y4o,y5o, sum17,sum35, rot1_0,rot1_1); \\\n         dct_wadd(x4, y0o, y4o); \\\n         dct_wadd(x5, y1o, y5o); \\\n         dct_wadd(x6, y2o, y5o); \\\n         dct_wadd(x7, y3o, y4o); \\\n         dct_bfly32o(row0,row7, x0,x7,bias,shift); \\\n         dct_bfly32o(row1,row6, x1,x6,bias,shift); \\\n         dct_bfly32o(row2,row5, x2,x5,bias,shift); \\\n         dct_bfly32o(row3,row4, x3,x4,bias,shift); \\\n      }\n\n   __m128i rot0_0 = dct_const(stbi__f2f(0.5411961f), stbi__f2f(0.5411961f) + stbi__f2f(-1.847759065f));\n   __m128i rot0_1 = dct_const(stbi__f2f(0.5411961f) + stbi__f2f( 0.765366865f), stbi__f2f(0.5411961f));\n   __m128i rot1_0 = dct_const(stbi__f2f(1.175875602f) + stbi__f2f(-0.899976223f), stbi__f2f(1.175875602f));\n   __m128i rot1_1 = dct_const(stbi__f2f(1.175875602f), stbi__f2f(1.175875602f) + stbi__f2f(-2.562915447f));\n   __m128i rot2_0 = dct_const(stbi__f2f(-1.961570560f) + stbi__f2f( 0.298631336f), stbi__f2f(-1.961570560f));\n   __m128i rot2_1 = dct_const(stbi__f2f(-1.961570560f), stbi__f2f(-1.961570560f) + stbi__f2f( 3.072711026f));\n   __m128i rot3_0 = dct_const(stbi__f2f(-0.390180644f) + stbi__f2f( 2.053119869f), stbi__f2f(-0.390180644f));\n   __m128i rot3_1 = dct_const(stbi__f2f(-0.390180644f), stbi__f2f(-0.390180644f) + stbi__f2f( 1.501321110f));\n\n   // rounding biases in column/row passes, see stbi__idct_block for explanation.\n   __m128i bias_0 = _mm_set1_epi32(512);\n   __m128i bias_1 = _mm_set1_epi32(65536 + (128<<17));\n\n   // load\n   row0 = _mm_load_si128((const __m128i *) (data + 0*8));\n   row1 = _mm_load_si128((const __m128i *) (data + 1*8));\n   row2 = _mm_load_si128((const __m128i *) (data + 2*8));\n   row3 = _mm_load_si128((const __m128i *) (data + 3*8));\n   row4 = _mm_load_si128((const __m128i *) (data + 4*8));\n   row5 = _mm_load_si128((const __m128i *) (data + 5*8));\n   row6 = _mm_load_si128((const __m128i *) (data + 6*8));\n   row7 = _mm_load_si128((const __m128i *) (data + 7*8));\n\n   // column pass\n   dct_pass(bias_0, 10);\n\n   {\n      // 16bit 8x8 transpose pass 1\n      dct_interleave16(row0, row4);\n      dct_interleave16(row1, row5);\n      dct_interleave16(row2, row6);\n      dct_interleave16(row3, row7);\n\n      // transpose pass 2\n      dct_interleave16(row0, row2);\n      dct_interleave16(row1, row3);\n      dct_interleave16(row4, row6);\n      dct_interleave16(row5, row7);\n\n      // transpose pass 3\n      dct_interleave16(row0, row1);\n      dct_interleave16(row2, row3);\n      dct_interleave16(row4, row5);\n      dct_interleave16(row6, row7);\n   }\n\n   // row pass\n   dct_pass(bias_1, 17);\n\n   {\n      // pack\n      __m128i p0 = _mm_packus_epi16(row0, row1); // a0a1a2a3...a7b0b1b2b3...b7\n      __m128i p1 = _mm_packus_epi16(row2, row3);\n      __m128i p2 = _mm_packus_epi16(row4, row5);\n      __m128i p3 = _mm_packus_epi16(row6, row7);\n\n      // 8bit 8x8 transpose pass 1\n      dct_interleave8(p0, p2); // a0e0a1e1...\n      dct_interleave8(p1, p3); // c0g0c1g1...\n\n      // transpose pass 2\n      dct_interleave8(p0, p1); // a0c0e0g0...\n      dct_interleave8(p2, p3); // b0d0f0h0...\n\n      // transpose pass 3\n      dct_interleave8(p0, p2); // a0b0c0d0...\n      dct_interleave8(p1, p3); // a4b4c4d4...\n\n      // store\n      _mm_storel_epi64((__m128i *) out, p0); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p0, 0x4e)); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, p2); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p2, 0x4e)); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, p1); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p1, 0x4e)); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, p3); out += out_stride;\n      _mm_storel_epi64((__m128i *) out, _mm_shuffle_epi32(p3, 0x4e));\n   }\n\n#undef dct_const\n#undef dct_rot\n#undef dct_widen\n#undef dct_wadd\n#undef dct_wsub\n#undef dct_bfly32o\n#undef dct_interleave8\n#undef dct_interleave16\n#undef dct_pass\n}\n\n#endif // STBI_SSE2\n\n#ifdef STBI_NEON\n\n// NEON integer IDCT. should produce bit-identical\n// results to the generic C version.\nstatic void stbi__idct_simd(stbi_uc *out, int out_stride, short data[64])\n{\n   int16x8_t row0, row1, row2, row3, row4, row5, row6, row7;\n\n   int16x4_t rot0_0 = vdup_n_s16(stbi__f2f(0.5411961f));\n   int16x4_t rot0_1 = vdup_n_s16(stbi__f2f(-1.847759065f));\n   int16x4_t rot0_2 = vdup_n_s16(stbi__f2f( 0.765366865f));\n   int16x4_t rot1_0 = vdup_n_s16(stbi__f2f( 1.175875602f));\n   int16x4_t rot1_1 = vdup_n_s16(stbi__f2f(-0.899976223f));\n   int16x4_t rot1_2 = vdup_n_s16(stbi__f2f(-2.562915447f));\n   int16x4_t rot2_0 = vdup_n_s16(stbi__f2f(-1.961570560f));\n   int16x4_t rot2_1 = vdup_n_s16(stbi__f2f(-0.390180644f));\n   int16x4_t rot3_0 = vdup_n_s16(stbi__f2f( 0.298631336f));\n   int16x4_t rot3_1 = vdup_n_s16(stbi__f2f( 2.053119869f));\n   int16x4_t rot3_2 = vdup_n_s16(stbi__f2f( 3.072711026f));\n   int16x4_t rot3_3 = vdup_n_s16(stbi__f2f( 1.501321110f));\n\n#define dct_long_mul(out, inq, coeff) \\\n   int32x4_t out##_l = vmull_s16(vget_low_s16(inq), coeff); \\\n   int32x4_t out##_h = vmull_s16(vget_high_s16(inq), coeff)\n\n#define dct_long_mac(out, acc, inq, coeff) \\\n   int32x4_t out##_l = vmlal_s16(acc##_l, vget_low_s16(inq), coeff); \\\n   int32x4_t out##_h = vmlal_s16(acc##_h, vget_high_s16(inq), coeff)\n\n#define dct_widen(out, inq) \\\n   int32x4_t out##_l = vshll_n_s16(vget_low_s16(inq), 12); \\\n   int32x4_t out##_h = vshll_n_s16(vget_high_s16(inq), 12)\n\n// wide add\n#define dct_wadd(out, a, b) \\\n   int32x4_t out##_l = vaddq_s32(a##_l, b##_l); \\\n   int32x4_t out##_h = vaddq_s32(a##_h, b##_h)\n\n// wide sub\n#define dct_wsub(out, a, b) \\\n   int32x4_t out##_l = vsubq_s32(a##_l, b##_l); \\\n   int32x4_t out##_h = vsubq_s32(a##_h, b##_h)\n\n// butterfly a/b, then shift using \"shiftop\" by \"s\" and pack\n#define dct_bfly32o(out0,out1, a,b,shiftop,s) \\\n   { \\\n      dct_wadd(sum, a, b); \\\n      dct_wsub(dif, a, b); \\\n      out0 = vcombine_s16(shiftop(sum_l, s), shiftop(sum_h, s)); \\\n      out1 = vcombine_s16(shiftop(dif_l, s), shiftop(dif_h, s)); \\\n   }\n\n#define dct_pass(shiftop, shift) \\\n   { \\\n      /* even part */ \\\n      int16x8_t sum26 = vaddq_s16(row2, row6); \\\n      dct_long_mul(p1e, sum26, rot0_0); \\\n      dct_long_mac(t2e, p1e, row6, rot0_1); \\\n      dct_long_mac(t3e, p1e, row2, rot0_2); \\\n      int16x8_t sum04 = vaddq_s16(row0, row4); \\\n      int16x8_t dif04 = vsubq_s16(row0, row4); \\\n      dct_widen(t0e, sum04); \\\n      dct_widen(t1e, dif04); \\\n      dct_wadd(x0, t0e, t3e); \\\n      dct_wsub(x3, t0e, t3e); \\\n      dct_wadd(x1, t1e, t2e); \\\n      dct_wsub(x2, t1e, t2e); \\\n      /* odd part */ \\\n      int16x8_t sum15 = vaddq_s16(row1, row5); \\\n      int16x8_t sum17 = vaddq_s16(row1, row7); \\\n      int16x8_t sum35 = vaddq_s16(row3, row5); \\\n      int16x8_t sum37 = vaddq_s16(row3, row7); \\\n      int16x8_t sumodd = vaddq_s16(sum17, sum35); \\\n      dct_long_mul(p5o, sumodd, rot1_0); \\\n      dct_long_mac(p1o, p5o, sum17, rot1_1); \\\n      dct_long_mac(p2o, p5o, sum35, rot1_2); \\\n      dct_long_mul(p3o, sum37, rot2_0); \\\n      dct_long_mul(p4o, sum15, rot2_1); \\\n      dct_wadd(sump13o, p1o, p3o); \\\n      dct_wadd(sump24o, p2o, p4o); \\\n      dct_wadd(sump23o, p2o, p3o); \\\n      dct_wadd(sump14o, p1o, p4o); \\\n      dct_long_mac(x4, sump13o, row7, rot3_0); \\\n      dct_long_mac(x5, sump24o, row5, rot3_1); \\\n      dct_long_mac(x6, sump23o, row3, rot3_2); \\\n      dct_long_mac(x7, sump14o, row1, rot3_3); \\\n      dct_bfly32o(row0,row7, x0,x7,shiftop,shift); \\\n      dct_bfly32o(row1,row6, x1,x6,shiftop,shift); \\\n      dct_bfly32o(row2,row5, x2,x5,shiftop,shift); \\\n      dct_bfly32o(row3,row4, x3,x4,shiftop,shift); \\\n   }\n\n   // load\n   row0 = vld1q_s16(data + 0*8);\n   row1 = vld1q_s16(data + 1*8);\n   row2 = vld1q_s16(data + 2*8);\n   row3 = vld1q_s16(data + 3*8);\n   row4 = vld1q_s16(data + 4*8);\n   row5 = vld1q_s16(data + 5*8);\n   row6 = vld1q_s16(data + 6*8);\n   row7 = vld1q_s16(data + 7*8);\n\n   // add DC bias\n   row0 = vaddq_s16(row0, vsetq_lane_s16(1024, vdupq_n_s16(0), 0));\n\n   // column pass\n   dct_pass(vrshrn_n_s32, 10);\n\n   // 16bit 8x8 transpose\n   {\n// these three map to a single VTRN.16, VTRN.32, and VSWP, respectively.\n// whether compilers actually get this is another story, sadly.\n#define dct_trn16(x, y) { int16x8x2_t t = vtrnq_s16(x, y); x = t.val[0]; y = t.val[1]; }\n#define dct_trn32(x, y) { int32x4x2_t t = vtrnq_s32(vreinterpretq_s32_s16(x), vreinterpretq_s32_s16(y)); x = vreinterpretq_s16_s32(t.val[0]); y = vreinterpretq_s16_s32(t.val[1]); }\n#define dct_trn64(x, y) { int16x8_t x0 = x; int16x8_t y0 = y; x = vcombine_s16(vget_low_s16(x0), vget_low_s16(y0)); y = vcombine_s16(vget_high_s16(x0), vget_high_s16(y0)); }\n\n      // pass 1\n      dct_trn16(row0, row1); // a0b0a2b2a4b4a6b6\n      dct_trn16(row2, row3);\n      dct_trn16(row4, row5);\n      dct_trn16(row6, row7);\n\n      // pass 2\n      dct_trn32(row0, row2); // a0b0c0d0a4b4c4d4\n      dct_trn32(row1, row3);\n      dct_trn32(row4, row6);\n      dct_trn32(row5, row7);\n\n      // pass 3\n      dct_trn64(row0, row4); // a0b0c0d0e0f0g0h0\n      dct_trn64(row1, row5);\n      dct_trn64(row2, row6);\n      dct_trn64(row3, row7);\n\n#undef dct_trn16\n#undef dct_trn32\n#undef dct_trn64\n   }\n\n   // row pass\n   // vrshrn_n_s32 only supports shifts up to 16, we need\n   // 17. so do a non-rounding shift of 16 first then follow\n   // up with a rounding shift by 1.\n   dct_pass(vshrn_n_s32, 16);\n\n   {\n      // pack and round\n      uint8x8_t p0 = vqrshrun_n_s16(row0, 1);\n      uint8x8_t p1 = vqrshrun_n_s16(row1, 1);\n      uint8x8_t p2 = vqrshrun_n_s16(row2, 1);\n      uint8x8_t p3 = vqrshrun_n_s16(row3, 1);\n      uint8x8_t p4 = vqrshrun_n_s16(row4, 1);\n      uint8x8_t p5 = vqrshrun_n_s16(row5, 1);\n      uint8x8_t p6 = vqrshrun_n_s16(row6, 1);\n      uint8x8_t p7 = vqrshrun_n_s16(row7, 1);\n\n      // again, these can translate into one instruction, but often don't.\n#define dct_trn8_8(x, y) { uint8x8x2_t t = vtrn_u8(x, y); x = t.val[0]; y = t.val[1]; }\n#define dct_trn8_16(x, y) { uint16x4x2_t t = vtrn_u16(vreinterpret_u16_u8(x), vreinterpret_u16_u8(y)); x = vreinterpret_u8_u16(t.val[0]); y = vreinterpret_u8_u16(t.val[1]); }\n#define dct_trn8_32(x, y) { uint32x2x2_t t = vtrn_u32(vreinterpret_u32_u8(x), vreinterpret_u32_u8(y)); x = vreinterpret_u8_u32(t.val[0]); y = vreinterpret_u8_u32(t.val[1]); }\n\n      // sadly can't use interleaved stores here since we only write\n      // 8 bytes to each scan line!\n\n      // 8x8 8-bit transpose pass 1\n      dct_trn8_8(p0, p1);\n      dct_trn8_8(p2, p3);\n      dct_trn8_8(p4, p5);\n      dct_trn8_8(p6, p7);\n\n      // pass 2\n      dct_trn8_16(p0, p2);\n      dct_trn8_16(p1, p3);\n      dct_trn8_16(p4, p6);\n      dct_trn8_16(p5, p7);\n\n      // pass 3\n      dct_trn8_32(p0, p4);\n      dct_trn8_32(p1, p5);\n      dct_trn8_32(p2, p6);\n      dct_trn8_32(p3, p7);\n\n      // store\n      vst1_u8(out, p0); out += out_stride;\n      vst1_u8(out, p1); out += out_stride;\n      vst1_u8(out, p2); out += out_stride;\n      vst1_u8(out, p3); out += out_stride;\n      vst1_u8(out, p4); out += out_stride;\n      vst1_u8(out, p5); out += out_stride;\n      vst1_u8(out, p6); out += out_stride;\n      vst1_u8(out, p7);\n\n#undef dct_trn8_8\n#undef dct_trn8_16\n#undef dct_trn8_32\n   }\n\n#undef dct_long_mul\n#undef dct_long_mac\n#undef dct_widen\n#undef dct_wadd\n#undef dct_wsub\n#undef dct_bfly32o\n#undef dct_pass\n}\n\n#endif // STBI_NEON\n\n#define STBI__MARKER_none  0xff\n// if there's a pending marker from the entropy stream, return that\n// otherwise, fetch from the stream and get a marker. if there's no\n// marker, return 0xff, which is never a valid marker value\nstatic stbi_uc stbi__get_marker(stbi__jpeg *j)\n{\n   stbi_uc x;\n   if (j->marker != STBI__MARKER_none) { x = j->marker; j->marker = STBI__MARKER_none; return x; }\n   x = stbi__get8(j->s);\n   if (x != 0xff) return STBI__MARKER_none;\n   while (x == 0xff)\n      x = stbi__get8(j->s);\n   return x;\n}\n\n// in each scan, we'll have scan_n components, and the order\n// of the components is specified by order[]\n#define STBI__RESTART(x)     ((x) >= 0xd0 && (x) <= 0xd7)\n\n// after a restart interval, stbi__jpeg_reset the entropy decoder and\n// the dc prediction\nstatic void stbi__jpeg_reset(stbi__jpeg *j)\n{\n   j->code_bits = 0;\n   j->code_buffer = 0;\n   j->nomore = 0;\n   j->img_comp[0].dc_pred = j->img_comp[1].dc_pred = j->img_comp[2].dc_pred = 0;\n   j->marker = STBI__MARKER_none;\n   j->todo = j->restart_interval ? j->restart_interval : 0x7fffffff;\n   j->eob_run = 0;\n   // no more than 1<<31 MCUs if no restart_interal? that's plenty safe,\n   // since we don't even allow 1<<30 pixels\n}\n\nstatic int stbi__parse_entropy_coded_data(stbi__jpeg *z)\n{\n   stbi__jpeg_reset(z);\n   if (!z->progressive) {\n      if (z->scan_n == 1) {\n         int i,j;\n         STBI_SIMD_ALIGN(short, data[64]);\n         int n = z->order[0];\n         // non-interleaved data, we just need to process one block at a time,\n         // in trivial scanline order\n         // number of blocks to do just depends on how many actual \"pixels\" this\n         // component has, independent of interleaved MCU blocking and such\n         int w = (z->img_comp[n].x+7) >> 3;\n         int h = (z->img_comp[n].y+7) >> 3;\n         for (j=0; j < h; ++j) {\n            for (i=0; i < w; ++i) {\n               int ha = z->img_comp[n].ha;\n               if (!stbi__jpeg_decode_block(z, data, z->huff_dc+z->img_comp[n].hd, z->huff_ac+ha, z->fast_ac[ha], n, z->dequant[z->img_comp[n].tq])) return 0;\n               z->idct_block_kernel(z->img_comp[n].data+z->img_comp[n].w2*j*8+i*8, z->img_comp[n].w2, data);\n               // every data block is an MCU, so countdown the restart interval\n               if (--z->todo <= 0) {\n                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);\n                  // if it's NOT a restart, then just bail, so we get corrupt data\n                  // rather than no data\n                  if (!STBI__RESTART(z->marker)) return 1;\n                  stbi__jpeg_reset(z);\n               }\n            }\n         }\n         return 1;\n      } else { // interleaved\n         int i,j,k,x,y;\n         STBI_SIMD_ALIGN(short, data[64]);\n         for (j=0; j < z->img_mcu_y; ++j) {\n            for (i=0; i < z->img_mcu_x; ++i) {\n               // scan an interleaved mcu... process scan_n components in order\n               for (k=0; k < z->scan_n; ++k) {\n                  int n = z->order[k];\n                  // scan out an mcu's worth of this component; that's just determined\n                  // by the basic H and V specified for the component\n                  for (y=0; y < z->img_comp[n].v; ++y) {\n                     for (x=0; x < z->img_comp[n].h; ++x) {\n                        int x2 = (i*z->img_comp[n].h + x)*8;\n                        int y2 = (j*z->img_comp[n].v + y)*8;\n                        int ha = z->img_comp[n].ha;\n                        if (!stbi__jpeg_decode_block(z, data, z->huff_dc+z->img_comp[n].hd, z->huff_ac+ha, z->fast_ac[ha], n, z->dequant[z->img_comp[n].tq])) return 0;\n                        z->idct_block_kernel(z->img_comp[n].data+z->img_comp[n].w2*y2+x2, z->img_comp[n].w2, data);\n                     }\n                  }\n               }\n               // after all interleaved components, that's an interleaved MCU,\n               // so now count down the restart interval\n               if (--z->todo <= 0) {\n                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);\n                  if (!STBI__RESTART(z->marker)) return 1;\n                  stbi__jpeg_reset(z);\n               }\n            }\n         }\n         return 1;\n      }\n   } else {\n      if (z->scan_n == 1) {\n         int i,j;\n         int n = z->order[0];\n         // non-interleaved data, we just need to process one block at a time,\n         // in trivial scanline order\n         // number of blocks to do just depends on how many actual \"pixels\" this\n         // component has, independent of interleaved MCU blocking and such\n         int w = (z->img_comp[n].x+7) >> 3;\n         int h = (z->img_comp[n].y+7) >> 3;\n         for (j=0; j < h; ++j) {\n            for (i=0; i < w; ++i) {\n               short *data = z->img_comp[n].coeff + 64 * (i + j * z->img_comp[n].coeff_w);\n               if (z->spec_start == 0) {\n                  if (!stbi__jpeg_decode_block_prog_dc(z, data, &z->huff_dc[z->img_comp[n].hd], n))\n                     return 0;\n               } else {\n                  int ha = z->img_comp[n].ha;\n                  if (!stbi__jpeg_decode_block_prog_ac(z, data, &z->huff_ac[ha], z->fast_ac[ha]))\n                     return 0;\n               }\n               // every data block is an MCU, so countdown the restart interval\n               if (--z->todo <= 0) {\n                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);\n                  if (!STBI__RESTART(z->marker)) return 1;\n                  stbi__jpeg_reset(z);\n               }\n            }\n         }\n         return 1;\n      } else { // interleaved\n         int i,j,k,x,y;\n         for (j=0; j < z->img_mcu_y; ++j) {\n            for (i=0; i < z->img_mcu_x; ++i) {\n               // scan an interleaved mcu... process scan_n components in order\n               for (k=0; k < z->scan_n; ++k) {\n                  int n = z->order[k];\n                  // scan out an mcu's worth of this component; that's just determined\n                  // by the basic H and V specified for the component\n                  for (y=0; y < z->img_comp[n].v; ++y) {\n                     for (x=0; x < z->img_comp[n].h; ++x) {\n                        int x2 = (i*z->img_comp[n].h + x);\n                        int y2 = (j*z->img_comp[n].v + y);\n                        short *data = z->img_comp[n].coeff + 64 * (x2 + y2 * z->img_comp[n].coeff_w);\n                        if (!stbi__jpeg_decode_block_prog_dc(z, data, &z->huff_dc[z->img_comp[n].hd], n))\n                           return 0;\n                     }\n                  }\n               }\n               // after all interleaved components, that's an interleaved MCU,\n               // so now count down the restart interval\n               if (--z->todo <= 0) {\n                  if (z->code_bits < 24) stbi__grow_buffer_unsafe(z);\n                  if (!STBI__RESTART(z->marker)) return 1;\n                  stbi__jpeg_reset(z);\n               }\n            }\n         }\n         return 1;\n      }\n   }\n}\n\nstatic void stbi__jpeg_dequantize(short *data, stbi_uc *dequant)\n{\n   int i;\n   for (i=0; i < 64; ++i)\n      data[i] *= dequant[i];\n}\n\nstatic void stbi__jpeg_finish(stbi__jpeg *z)\n{\n   if (z->progressive) {\n      // dequantize and idct the data\n      int i,j,n;\n      for (n=0; n < z->s->img_n; ++n) {\n         int w = (z->img_comp[n].x+7) >> 3;\n         int h = (z->img_comp[n].y+7) >> 3;\n         for (j=0; j < h; ++j) {\n            for (i=0; i < w; ++i) {\n               short *data = z->img_comp[n].coeff + 64 * (i + j * z->img_comp[n].coeff_w);\n               stbi__jpeg_dequantize(data, z->dequant[z->img_comp[n].tq]);\n               z->idct_block_kernel(z->img_comp[n].data+z->img_comp[n].w2*j*8+i*8, z->img_comp[n].w2, data);\n            }\n         }\n      }\n   }\n}\n\nstatic int stbi__process_marker(stbi__jpeg *z, int m)\n{\n   int L;\n   switch (m) {\n      case STBI__MARKER_none: // no marker found\n         return stbi__err(\"expected marker\",\"Corrupt JPEG\");\n\n      case 0xDD: // DRI - specify restart interval\n         if (stbi__get16be(z->s) != 4) return stbi__err(\"bad DRI len\",\"Corrupt JPEG\");\n         z->restart_interval = stbi__get16be(z->s);\n         return 1;\n\n      case 0xDB: // DQT - define quantization table\n         L = stbi__get16be(z->s)-2;\n         while (L > 0) {\n            int q = stbi__get8(z->s);\n            int p = q >> 4;\n            int t = q & 15,i;\n            if (p != 0) return stbi__err(\"bad DQT type\",\"Corrupt JPEG\");\n            if (t > 3) return stbi__err(\"bad DQT table\",\"Corrupt JPEG\");\n            for (i=0; i < 64; ++i)\n               z->dequant[t][stbi__jpeg_dezigzag[i]] = stbi__get8(z->s);\n            L -= 65;\n         }\n         return L==0;\n\n      case 0xC4: // DHT - define huffman table\n         L = stbi__get16be(z->s)-2;\n         while (L > 0) {\n            stbi_uc *v;\n            int sizes[16],i,n=0;\n            int q = stbi__get8(z->s);\n            int tc = q >> 4;\n            int th = q & 15;\n            if (tc > 1 || th > 3) return stbi__err(\"bad DHT header\",\"Corrupt JPEG\");\n            for (i=0; i < 16; ++i) {\n               sizes[i] = stbi__get8(z->s);\n               n += sizes[i];\n            }\n            L -= 17;\n            if (tc == 0) {\n               if (!stbi__build_huffman(z->huff_dc+th, sizes)) return 0;\n               v = z->huff_dc[th].values;\n            } else {\n               if (!stbi__build_huffman(z->huff_ac+th, sizes)) return 0;\n               v = z->huff_ac[th].values;\n            }\n            for (i=0; i < n; ++i)\n               v[i] = stbi__get8(z->s);\n            if (tc != 0)\n               stbi__build_fast_ac(z->fast_ac[th], z->huff_ac + th);\n            L -= n;\n         }\n         return L==0;\n   }\n   // check for comment block or APP blocks\n   if ((m >= 0xE0 && m <= 0xEF) || m == 0xFE) {\n      stbi__skip(z->s, stbi__get16be(z->s)-2);\n      return 1;\n   }\n   return 0;\n}\n\n// after we see SOS\nstatic int stbi__process_scan_header(stbi__jpeg *z)\n{\n   int i;\n   int Ls = stbi__get16be(z->s);\n   z->scan_n = stbi__get8(z->s);\n   if (z->scan_n < 1 || z->scan_n > 4 || z->scan_n > (int) z->s->img_n) return stbi__err(\"bad SOS component count\",\"Corrupt JPEG\");\n   if (Ls != 6+2*z->scan_n) return stbi__err(\"bad SOS len\",\"Corrupt JPEG\");\n   for (i=0; i < z->scan_n; ++i) {\n      int id = stbi__get8(z->s), which;\n      int q = stbi__get8(z->s);\n      for (which = 0; which < z->s->img_n; ++which)\n         if (z->img_comp[which].id == id)\n            break;\n      if (which == z->s->img_n) return 0; // no match\n      z->img_comp[which].hd = q >> 4;   if (z->img_comp[which].hd > 3) return stbi__err(\"bad DC huff\",\"Corrupt JPEG\");\n      z->img_comp[which].ha = q & 15;   if (z->img_comp[which].ha > 3) return stbi__err(\"bad AC huff\",\"Corrupt JPEG\");\n      z->order[i] = which;\n   }\n\n   {\n      int aa;\n      z->spec_start = stbi__get8(z->s);\n      z->spec_end   = stbi__get8(z->s); // should be 63, but might be 0\n      aa = stbi__get8(z->s);\n      z->succ_high = (aa >> 4);\n      z->succ_low  = (aa & 15);\n      if (z->progressive) {\n         if (z->spec_start > 63 || z->spec_end > 63  || z->spec_start > z->spec_end || z->succ_high > 13 || z->succ_low > 13)\n            return stbi__err(\"bad SOS\", \"Corrupt JPEG\");\n      } else {\n         if (z->spec_start != 0) return stbi__err(\"bad SOS\",\"Corrupt JPEG\");\n         if (z->succ_high != 0 || z->succ_low != 0) return stbi__err(\"bad SOS\",\"Corrupt JPEG\");\n         z->spec_end = 63;\n      }\n   }\n\n   return 1;\n}\n\nstatic int stbi__process_frame_header(stbi__jpeg *z, int scan)\n{\n   stbi__context *s = z->s;\n   int Lf,p,i,q, h_max=1,v_max=1,c;\n   Lf = stbi__get16be(s);         if (Lf < 11) return stbi__err(\"bad SOF len\",\"Corrupt JPEG\"); // JPEG\n   p  = stbi__get8(s);            if (p != 8) return stbi__err(\"only 8-bit\",\"JPEG format not supported: 8-bit only\"); // JPEG baseline\n   s->img_y = stbi__get16be(s);   if (s->img_y == 0) return stbi__err(\"no header height\", \"JPEG format not supported: delayed height\"); // Legal, but we don't handle it--but neither does IJG\n   s->img_x = stbi__get16be(s);   if (s->img_x == 0) return stbi__err(\"0 width\",\"Corrupt JPEG\"); // JPEG requires\n   c = stbi__get8(s);\n   if (c != 3 && c != 1) return stbi__err(\"bad component count\",\"Corrupt JPEG\");    // JFIF requires\n   s->img_n = c;\n   for (i=0; i < c; ++i) {\n      z->img_comp[i].data = NULL;\n      z->img_comp[i].linebuf = NULL;\n   }\n\n   if (Lf != 8+3*s->img_n) return stbi__err(\"bad SOF len\",\"Corrupt JPEG\");\n\n   for (i=0; i < s->img_n; ++i) {\n      z->img_comp[i].id = stbi__get8(s);\n      if (z->img_comp[i].id != i+1)   // JFIF requires\n         if (z->img_comp[i].id != i)  // some version of jpegtran outputs non-JFIF-compliant files!\n            return stbi__err(\"bad component ID\",\"Corrupt JPEG\");\n      q = stbi__get8(s);\n      z->img_comp[i].h = (q >> 4);  if (!z->img_comp[i].h || z->img_comp[i].h > 4) return stbi__err(\"bad H\",\"Corrupt JPEG\");\n      z->img_comp[i].v = q & 15;    if (!z->img_comp[i].v || z->img_comp[i].v > 4) return stbi__err(\"bad V\",\"Corrupt JPEG\");\n      z->img_comp[i].tq = stbi__get8(s);  if (z->img_comp[i].tq > 3) return stbi__err(\"bad TQ\",\"Corrupt JPEG\");\n   }\n\n   if (scan != STBI__SCAN_load) return 1;\n\n   if ((1 << 30) / s->img_x / s->img_n < s->img_y) return stbi__err(\"too large\", \"Image too large to decode\");\n\n   for (i=0; i < s->img_n; ++i) {\n      if (z->img_comp[i].h > h_max) h_max = z->img_comp[i].h;\n      if (z->img_comp[i].v > v_max) v_max = z->img_comp[i].v;\n   }\n\n   // compute interleaved mcu info\n   z->img_h_max = h_max;\n   z->img_v_max = v_max;\n   z->img_mcu_w = h_max * 8;\n   z->img_mcu_h = v_max * 8;\n   z->img_mcu_x = (s->img_x + z->img_mcu_w-1) / z->img_mcu_w;\n   z->img_mcu_y = (s->img_y + z->img_mcu_h-1) / z->img_mcu_h;\n\n   for (i=0; i < s->img_n; ++i) {\n      // number of effective pixels (e.g. for non-interleaved MCU)\n      z->img_comp[i].x = (s->img_x * z->img_comp[i].h + h_max-1) / h_max;\n      z->img_comp[i].y = (s->img_y * z->img_comp[i].v + v_max-1) / v_max;\n      // to simplify generation, we'll allocate enough memory to decode\n      // the bogus oversized data from using interleaved MCUs and their\n      // big blocks (e.g. a 16x16 iMCU on an image of width 33); we won't\n      // discard the extra data until colorspace conversion\n      z->img_comp[i].w2 = z->img_mcu_x * z->img_comp[i].h * 8;\n      z->img_comp[i].h2 = z->img_mcu_y * z->img_comp[i].v * 8;\n      z->img_comp[i].raw_data = stbi__malloc(z->img_comp[i].w2 * z->img_comp[i].h2+15);\n\n      if (z->img_comp[i].raw_data == NULL) {\n         for(--i; i >= 0; --i) {\n            STBI_FREE(z->img_comp[i].raw_data);\n            z->img_comp[i].raw_data = NULL;\n         }\n         return stbi__err(\"outofmem\", \"Out of memory\");\n      }\n      // align blocks for idct using mmx/sse\n      z->img_comp[i].data = (stbi_uc*) (((size_t) z->img_comp[i].raw_data + 15) & ~15);\n      z->img_comp[i].linebuf = NULL;\n      if (z->progressive) {\n         z->img_comp[i].coeff_w = (z->img_comp[i].w2 + 7) >> 3;\n         z->img_comp[i].coeff_h = (z->img_comp[i].h2 + 7) >> 3;\n         z->img_comp[i].raw_coeff = STBI_MALLOC(z->img_comp[i].coeff_w * z->img_comp[i].coeff_h * 64 * sizeof(short) + 15);\n         z->img_comp[i].coeff = (short*) (((size_t) z->img_comp[i].raw_coeff + 15) & ~15);\n      } else {\n         z->img_comp[i].coeff = 0;\n         z->img_comp[i].raw_coeff = 0;\n      }\n   }\n\n   return 1;\n}\n\n// use comparisons since in some cases we handle more than one case (e.g. SOF)\n#define stbi__DNL(x)         ((x) == 0xdc)\n#define stbi__SOI(x)         ((x) == 0xd8)\n#define stbi__EOI(x)         ((x) == 0xd9)\n#define stbi__SOF(x)         ((x) == 0xc0 || (x) == 0xc1 || (x) == 0xc2)\n#define stbi__SOS(x)         ((x) == 0xda)\n\n#define stbi__SOF_progressive(x)   ((x) == 0xc2)\n\nstatic int stbi__decode_jpeg_header(stbi__jpeg *z, int scan)\n{\n   int m;\n   z->marker = STBI__MARKER_none; // initialize cached marker to empty\n   m = stbi__get_marker(z);\n   if (!stbi__SOI(m)) return stbi__err(\"no SOI\",\"Corrupt JPEG\");\n   if (scan == STBI__SCAN_type) return 1;\n   m = stbi__get_marker(z);\n   while (!stbi__SOF(m)) {\n      if (!stbi__process_marker(z,m)) return 0;\n      m = stbi__get_marker(z);\n      while (m == STBI__MARKER_none) {\n         // some files have extra padding after their blocks, so ok, we'll scan\n         if (stbi__at_eof(z->s)) return stbi__err(\"no SOF\", \"Corrupt JPEG\");\n         m = stbi__get_marker(z);\n      }\n   }\n   z->progressive = stbi__SOF_progressive(m);\n   if (!stbi__process_frame_header(z, scan)) return 0;\n   return 1;\n}\n\n// decode image to YCbCr format\nstatic int stbi__decode_jpeg_image(stbi__jpeg *j)\n{\n   int m;\n   for (m = 0; m < 4; m++) {\n      j->img_comp[m].raw_data = NULL;\n      j->img_comp[m].raw_coeff = NULL;\n   }\n   j->restart_interval = 0;\n   if (!stbi__decode_jpeg_header(j, STBI__SCAN_load)) return 0;\n   m = stbi__get_marker(j);\n   while (!stbi__EOI(m)) {\n      if (stbi__SOS(m)) {\n         if (!stbi__process_scan_header(j)) return 0;\n         if (!stbi__parse_entropy_coded_data(j)) return 0;\n         if (j->marker == STBI__MARKER_none ) {\n            // handle 0s at the end of image data from IP Kamera 9060\n            while (!stbi__at_eof(j->s)) {\n               int x = stbi__get8(j->s);\n               if (x == 255) {\n                  j->marker = stbi__get8(j->s);\n                  break;\n               } else if (x != 0) {\n                  return stbi__err(\"junk before marker\", \"Corrupt JPEG\");\n               }\n            }\n            // if we reach eof without hitting a marker, stbi__get_marker() below will fail and we'll eventually return 0\n         }\n      } else {\n         if (!stbi__process_marker(j, m)) return 0;\n      }\n      m = stbi__get_marker(j);\n   }\n   if (j->progressive)\n      stbi__jpeg_finish(j);\n   return 1;\n}\n\n// static jfif-centered resampling (across block boundaries)\n\ntypedef stbi_uc *(*resample_row_func)(stbi_uc *out, stbi_uc *in0, stbi_uc *in1,\n                                    int w, int hs);\n\n#define stbi__div4(x) ((stbi_uc) ((x) >> 2))\n\nstatic stbi_uc *resample_row_1(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)\n{\n   STBI_NOTUSED(out);\n   STBI_NOTUSED(in_far);\n   STBI_NOTUSED(w);\n   STBI_NOTUSED(hs);\n   return in_near;\n}\n\nstatic stbi_uc* stbi__resample_row_v_2(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)\n{\n   // need to generate two samples vertically for every one in input\n   int i;\n   STBI_NOTUSED(hs);\n   for (i=0; i < w; ++i)\n      out[i] = stbi__div4(3*in_near[i] + in_far[i] + 2);\n   return out;\n}\n\nstatic stbi_uc*  stbi__resample_row_h_2(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)\n{\n   // need to generate two samples horizontally for every one in input\n   int i;\n   stbi_uc *input = in_near;\n\n   if (w == 1) {\n      // if only one sample, can't do any interpolation\n      out[0] = out[1] = input[0];\n      return out;\n   }\n\n   out[0] = input[0];\n   out[1] = stbi__div4(input[0]*3 + input[1] + 2);\n   for (i=1; i < w-1; ++i) {\n      int n = 3*input[i]+2;\n      out[i*2+0] = stbi__div4(n+input[i-1]);\n      out[i*2+1] = stbi__div4(n+input[i+1]);\n   }\n   out[i*2+0] = stbi__div4(input[w-2]*3 + input[w-1] + 2);\n   out[i*2+1] = input[w-1];\n\n   STBI_NOTUSED(in_far);\n   STBI_NOTUSED(hs);\n\n   return out;\n}\n\n#define stbi__div16(x) ((stbi_uc) ((x) >> 4))\n\nstatic stbi_uc *stbi__resample_row_hv_2(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)\n{\n   // need to generate 2x2 samples for every one in input\n   int i,t0,t1;\n   if (w == 1) {\n      out[0] = out[1] = stbi__div4(3*in_near[0] + in_far[0] + 2);\n      return out;\n   }\n\n   t1 = 3*in_near[0] + in_far[0];\n   out[0] = stbi__div4(t1+2);\n   for (i=1; i < w; ++i) {\n      t0 = t1;\n      t1 = 3*in_near[i]+in_far[i];\n      out[i*2-1] = stbi__div16(3*t0 + t1 + 8);\n      out[i*2  ] = stbi__div16(3*t1 + t0 + 8);\n   }\n   out[w*2-1] = stbi__div4(t1+2);\n\n   STBI_NOTUSED(hs);\n\n   return out;\n}\n\n#if defined(STBI_SSE2) || defined(STBI_NEON)\nstatic stbi_uc *stbi__resample_row_hv_2_simd(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)\n{\n   // need to generate 2x2 samples for every one in input\n   int i=0,t0,t1;\n\n   if (w == 1) {\n      out[0] = out[1] = stbi__div4(3*in_near[0] + in_far[0] + 2);\n      return out;\n   }\n\n   t1 = 3*in_near[0] + in_far[0];\n   // process groups of 8 pixels for as long as we can.\n   // note we can't handle the last pixel in a row in this loop\n   // because we need to handle the filter boundary conditions.\n   for (; i < ((w-1) & ~7); i += 8) {\n#if defined(STBI_SSE2)\n      // load and perform the vertical filtering pass\n      // this uses 3*x + y = 4*x + (y - x)\n      __m128i zero  = _mm_setzero_si128();\n      __m128i farb  = _mm_loadl_epi64((__m128i *) (in_far + i));\n      __m128i nearb = _mm_loadl_epi64((__m128i *) (in_near + i));\n      __m128i farw  = _mm_unpacklo_epi8(farb, zero);\n      __m128i nearw = _mm_unpacklo_epi8(nearb, zero);\n      __m128i diff  = _mm_sub_epi16(farw, nearw);\n      __m128i nears = _mm_slli_epi16(nearw, 2);\n      __m128i curr  = _mm_add_epi16(nears, diff); // current row\n\n      // horizontal filter works the same based on shifted vers of current\n      // row. \"prev\" is current row shifted right by 1 pixel; we need to\n      // insert the previous pixel value (from t1).\n      // \"next\" is current row shifted left by 1 pixel, with first pixel\n      // of next block of 8 pixels added in.\n      __m128i prv0 = _mm_slli_si128(curr, 2);\n      __m128i nxt0 = _mm_srli_si128(curr, 2);\n      __m128i prev = _mm_insert_epi16(prv0, t1, 0);\n      __m128i next = _mm_insert_epi16(nxt0, 3*in_near[i+8] + in_far[i+8], 7);\n\n      // horizontal filter, polyphase implementation since it's convenient:\n      // even pixels = 3*cur + prev = cur*4 + (prev - cur)\n      // odd  pixels = 3*cur + next = cur*4 + (next - cur)\n      // note the shared term.\n      __m128i bias  = _mm_set1_epi16(8);\n      __m128i curs = _mm_slli_epi16(curr, 2);\n      __m128i prvd = _mm_sub_epi16(prev, curr);\n      __m128i nxtd = _mm_sub_epi16(next, curr);\n      __m128i curb = _mm_add_epi16(curs, bias);\n      __m128i even = _mm_add_epi16(prvd, curb);\n      __m128i odd  = _mm_add_epi16(nxtd, curb);\n\n      // interleave even and odd pixels, then undo scaling.\n      __m128i int0 = _mm_unpacklo_epi16(even, odd);\n      __m128i int1 = _mm_unpackhi_epi16(even, odd);\n      __m128i de0  = _mm_srli_epi16(int0, 4);\n      __m128i de1  = _mm_srli_epi16(int1, 4);\n\n      // pack and write output\n      __m128i outv = _mm_packus_epi16(de0, de1);\n      _mm_storeu_si128((__m128i *) (out + i*2), outv);\n#elif defined(STBI_NEON)\n      // load and perform the vertical filtering pass\n      // this uses 3*x + y = 4*x + (y - x)\n      uint8x8_t farb  = vld1_u8(in_far + i);\n      uint8x8_t nearb = vld1_u8(in_near + i);\n      int16x8_t diff  = vreinterpretq_s16_u16(vsubl_u8(farb, nearb));\n      int16x8_t nears = vreinterpretq_s16_u16(vshll_n_u8(nearb, 2));\n      int16x8_t curr  = vaddq_s16(nears, diff); // current row\n\n      // horizontal filter works the same based on shifted vers of current\n      // row. \"prev\" is current row shifted right by 1 pixel; we need to\n      // insert the previous pixel value (from t1).\n      // \"next\" is current row shifted left by 1 pixel, with first pixel\n      // of next block of 8 pixels added in.\n      int16x8_t prv0 = vextq_s16(curr, curr, 7);\n      int16x8_t nxt0 = vextq_s16(curr, curr, 1);\n      int16x8_t prev = vsetq_lane_s16(t1, prv0, 0);\n      int16x8_t next = vsetq_lane_s16(3*in_near[i+8] + in_far[i+8], nxt0, 7);\n\n      // horizontal filter, polyphase implementation since it's convenient:\n      // even pixels = 3*cur + prev = cur*4 + (prev - cur)\n      // odd  pixels = 3*cur + next = cur*4 + (next - cur)\n      // note the shared term.\n      int16x8_t curs = vshlq_n_s16(curr, 2);\n      int16x8_t prvd = vsubq_s16(prev, curr);\n      int16x8_t nxtd = vsubq_s16(next, curr);\n      int16x8_t even = vaddq_s16(curs, prvd);\n      int16x8_t odd  = vaddq_s16(curs, nxtd);\n\n      // undo scaling and round, then store with even/odd phases interleaved\n      uint8x8x2_t o;\n      o.val[0] = vqrshrun_n_s16(even, 4);\n      o.val[1] = vqrshrun_n_s16(odd,  4);\n      vst2_u8(out + i*2, o);\n#endif\n\n      // \"previous\" value for next iter\n      t1 = 3*in_near[i+7] + in_far[i+7];\n   }\n\n   t0 = t1;\n   t1 = 3*in_near[i] + in_far[i];\n   out[i*2] = stbi__div16(3*t1 + t0 + 8);\n\n   for (++i; i < w; ++i) {\n      t0 = t1;\n      t1 = 3*in_near[i]+in_far[i];\n      out[i*2-1] = stbi__div16(3*t0 + t1 + 8);\n      out[i*2  ] = stbi__div16(3*t1 + t0 + 8);\n   }\n   out[w*2-1] = stbi__div4(t1+2);\n\n   STBI_NOTUSED(hs);\n\n   return out;\n}\n#endif\n\nstatic stbi_uc *stbi__resample_row_generic(stbi_uc *out, stbi_uc *in_near, stbi_uc *in_far, int w, int hs)\n{\n   // resample with nearest-neighbor\n   int i,j;\n   STBI_NOTUSED(in_far);\n   for (i=0; i < w; ++i)\n      for (j=0; j < hs; ++j)\n         out[i*hs+j] = in_near[i];\n   return out;\n}\n\n#ifdef STBI_JPEG_OLD\n// this is the same YCbCr-to-RGB calculation that stb_image has used\n// historically before the algorithm changes in 1.49\n#define float2fixed(x)  ((int) ((x) * 65536 + 0.5))\nstatic void stbi__YCbCr_to_RGB_row(stbi_uc *out, const stbi_uc *y, const stbi_uc *pcb, const stbi_uc *pcr, int count, int step)\n{\n   int i;\n   for (i=0; i < count; ++i) {\n      int y_fixed = (y[i] << 16) + 32768; // rounding\n      int r,g,b;\n      int cr = pcr[i] - 128;\n      int cb = pcb[i] - 128;\n      r = y_fixed + cr*float2fixed(1.40200f);\n      g = y_fixed - cr*float2fixed(0.71414f) - cb*float2fixed(0.34414f);\n      b = y_fixed                            + cb*float2fixed(1.77200f);\n      r >>= 16;\n      g >>= 16;\n      b >>= 16;\n      if ((unsigned) r > 255) { if (r < 0) r = 0; else r = 255; }\n      if ((unsigned) g > 255) { if (g < 0) g = 0; else g = 255; }\n      if ((unsigned) b > 255) { if (b < 0) b = 0; else b = 255; }\n      out[0] = (stbi_uc)r;\n      out[1] = (stbi_uc)g;\n      out[2] = (stbi_uc)b;\n      out[3] = 255;\n      out += step;\n   }\n}\n#else\n// this is a reduced-precision calculation of YCbCr-to-RGB introduced\n// to make sure the code produces the same results in both SIMD and scalar\n#define float2fixed(x)  (((int) ((x) * 4096.0f + 0.5f)) << 8)\nstatic void stbi__YCbCr_to_RGB_row(stbi_uc *out, const stbi_uc *y, const stbi_uc *pcb, const stbi_uc *pcr, int count, int step)\n{\n   int i;\n   for (i=0; i < count; ++i) {\n      int y_fixed = (y[i] << 20) + (1<<19); // rounding\n      int r,g,b;\n      int cr = pcr[i] - 128;\n      int cb = pcb[i] - 128;\n      r = y_fixed +  cr* float2fixed(1.40200f);\n      g = y_fixed + (cr*-float2fixed(0.71414f)) + ((cb*-float2fixed(0.34414f)) & 0xffff0000);\n      b = y_fixed                               +   cb* float2fixed(1.77200f);\n      r >>= 20;\n      g >>= 20;\n      b >>= 20;\n      if ((unsigned) r > 255) { if (r < 0) r = 0; else r = 255; }\n      if ((unsigned) g > 255) { if (g < 0) g = 0; else g = 255; }\n      if ((unsigned) b > 255) { if (b < 0) b = 0; else b = 255; }\n      out[0] = (stbi_uc)r;\n      out[1] = (stbi_uc)g;\n      out[2] = (stbi_uc)b;\n      out[3] = 255;\n      out += step;\n   }\n}\n#endif\n\n#if defined(STBI_SSE2) || defined(STBI_NEON)\nstatic void stbi__YCbCr_to_RGB_simd(stbi_uc *out, stbi_uc const *y, stbi_uc const *pcb, stbi_uc const *pcr, int count, int step)\n{\n   int i = 0;\n\n#ifdef STBI_SSE2\n   // step == 3 is pretty ugly on the final interleave, and i'm not convinced\n   // it's useful in practice (you wouldn't use it for textures, for example).\n   // so just accelerate step == 4 case.\n   if (step == 4) {\n      // this is a fairly straightforward implementation and not super-optimized.\n      __m128i signflip  = _mm_set1_epi8(-0x80);\n      __m128i cr_const0 = _mm_set1_epi16(   (short) ( 1.40200f*4096.0f+0.5f));\n      __m128i cr_const1 = _mm_set1_epi16( - (short) ( 0.71414f*4096.0f+0.5f));\n      __m128i cb_const0 = _mm_set1_epi16( - (short) ( 0.34414f*4096.0f+0.5f));\n      __m128i cb_const1 = _mm_set1_epi16(   (short) ( 1.77200f*4096.0f+0.5f));\n      __m128i y_bias = _mm_set1_epi8((char) (unsigned char) 128);\n      __m128i xw = _mm_set1_epi16(255); // alpha channel\n\n      for (; i+7 < count; i += 8) {\n         // load\n         __m128i y_bytes = _mm_loadl_epi64((__m128i *) (y+i));\n         __m128i cr_bytes = _mm_loadl_epi64((__m128i *) (pcr+i));\n         __m128i cb_bytes = _mm_loadl_epi64((__m128i *) (pcb+i));\n         __m128i cr_biased = _mm_xor_si128(cr_bytes, signflip); // -128\n         __m128i cb_biased = _mm_xor_si128(cb_bytes, signflip); // -128\n\n         // unpack to short (and left-shift cr, cb by 8)\n         __m128i yw  = _mm_unpacklo_epi8(y_bias, y_bytes);\n         __m128i crw = _mm_unpacklo_epi8(_mm_setzero_si128(), cr_biased);\n         __m128i cbw = _mm_unpacklo_epi8(_mm_setzero_si128(), cb_biased);\n\n         // color transform\n         __m128i yws = _mm_srli_epi16(yw, 4);\n         __m128i cr0 = _mm_mulhi_epi16(cr_const0, crw);\n         __m128i cb0 = _mm_mulhi_epi16(cb_const0, cbw);\n         __m128i cb1 = _mm_mulhi_epi16(cbw, cb_const1);\n         __m128i cr1 = _mm_mulhi_epi16(crw, cr_const1);\n         __m128i rws = _mm_add_epi16(cr0, yws);\n         __m128i gwt = _mm_add_epi16(cb0, yws);\n         __m128i bws = _mm_add_epi16(yws, cb1);\n         __m128i gws = _mm_add_epi16(gwt, cr1);\n\n         // descale\n         __m128i rw = _mm_srai_epi16(rws, 4);\n         __m128i bw = _mm_srai_epi16(bws, 4);\n         __m128i gw = _mm_srai_epi16(gws, 4);\n\n         // back to byte, set up for transpose\n         __m128i brb = _mm_packus_epi16(rw, bw);\n         __m128i gxb = _mm_packus_epi16(gw, xw);\n\n         // transpose to interleave channels\n         __m128i t0 = _mm_unpacklo_epi8(brb, gxb);\n         __m128i t1 = _mm_unpackhi_epi8(brb, gxb);\n         __m128i o0 = _mm_unpacklo_epi16(t0, t1);\n         __m128i o1 = _mm_unpackhi_epi16(t0, t1);\n\n         // store\n         _mm_storeu_si128((__m128i *) (out + 0), o0);\n         _mm_storeu_si128((__m128i *) (out + 16), o1);\n         out += 32;\n      }\n   }\n#endif\n\n#ifdef STBI_NEON\n   // in this version, step=3 support would be easy to add. but is there demand?\n   if (step == 4) {\n      // this is a fairly straightforward implementation and not super-optimized.\n      uint8x8_t signflip = vdup_n_u8(0x80);\n      int16x8_t cr_const0 = vdupq_n_s16(   (short) ( 1.40200f*4096.0f+0.5f));\n      int16x8_t cr_const1 = vdupq_n_s16( - (short) ( 0.71414f*4096.0f+0.5f));\n      int16x8_t cb_const0 = vdupq_n_s16( - (short) ( 0.34414f*4096.0f+0.5f));\n      int16x8_t cb_const1 = vdupq_n_s16(   (short) ( 1.77200f*4096.0f+0.5f));\n\n      for (; i+7 < count; i += 8) {\n         // load\n         uint8x8_t y_bytes  = vld1_u8(y + i);\n         uint8x8_t cr_bytes = vld1_u8(pcr + i);\n         uint8x8_t cb_bytes = vld1_u8(pcb + i);\n         int8x8_t cr_biased = vreinterpret_s8_u8(vsub_u8(cr_bytes, signflip));\n         int8x8_t cb_biased = vreinterpret_s8_u8(vsub_u8(cb_bytes, signflip));\n\n         // expand to s16\n         int16x8_t yws = vreinterpretq_s16_u16(vshll_n_u8(y_bytes, 4));\n         int16x8_t crw = vshll_n_s8(cr_biased, 7);\n         int16x8_t cbw = vshll_n_s8(cb_biased, 7);\n\n         // color transform\n         int16x8_t cr0 = vqdmulhq_s16(crw, cr_const0);\n         int16x8_t cb0 = vqdmulhq_s16(cbw, cb_const0);\n         int16x8_t cr1 = vqdmulhq_s16(crw, cr_const1);\n         int16x8_t cb1 = vqdmulhq_s16(cbw, cb_const1);\n         int16x8_t rws = vaddq_s16(yws, cr0);\n         int16x8_t gws = vaddq_s16(vaddq_s16(yws, cb0), cr1);\n         int16x8_t bws = vaddq_s16(yws, cb1);\n\n         // undo scaling, round, convert to byte\n         uint8x8x4_t o;\n         o.val[0] = vqrshrun_n_s16(rws, 4);\n         o.val[1] = vqrshrun_n_s16(gws, 4);\n         o.val[2] = vqrshrun_n_s16(bws, 4);\n         o.val[3] = vdup_n_u8(255);\n\n         // store, interleaving r/g/b/a\n         vst4_u8(out, o);\n         out += 8*4;\n      }\n   }\n#endif\n\n   for (; i < count; ++i) {\n      int y_fixed = (y[i] << 20) + (1<<19); // rounding\n      int r,g,b;\n      int cr = pcr[i] - 128;\n      int cb = pcb[i] - 128;\n      r = y_fixed + cr* float2fixed(1.40200f);\n      g = y_fixed + cr*-float2fixed(0.71414f) + ((cb*-float2fixed(0.34414f)) & 0xffff0000);\n      b = y_fixed                             +   cb* float2fixed(1.77200f);\n      r >>= 20;\n      g >>= 20;\n      b >>= 20;\n      if ((unsigned) r > 255) { if (r < 0) r = 0; else r = 255; }\n      if ((unsigned) g > 255) { if (g < 0) g = 0; else g = 255; }\n      if ((unsigned) b > 255) { if (b < 0) b = 0; else b = 255; }\n      out[0] = (stbi_uc)r;\n      out[1] = (stbi_uc)g;\n      out[2] = (stbi_uc)b;\n      out[3] = 255;\n      out += step;\n   }\n}\n#endif\n\n// set up the kernels\nstatic void stbi__setup_jpeg(stbi__jpeg *j)\n{\n   j->idct_block_kernel = stbi__idct_block;\n   j->YCbCr_to_RGB_kernel = stbi__YCbCr_to_RGB_row;\n   j->resample_row_hv_2_kernel = stbi__resample_row_hv_2;\n\n#ifdef STBI_SSE2\n   if (stbi__sse2_available()) {\n      j->idct_block_kernel = stbi__idct_simd;\n      #ifndef STBI_JPEG_OLD\n      j->YCbCr_to_RGB_kernel = stbi__YCbCr_to_RGB_simd;\n      #endif\n      j->resample_row_hv_2_kernel = stbi__resample_row_hv_2_simd;\n   }\n#endif\n\n#ifdef STBI_NEON\n   j->idct_block_kernel = stbi__idct_simd;\n   #ifndef STBI_JPEG_OLD\n   j->YCbCr_to_RGB_kernel = stbi__YCbCr_to_RGB_simd;\n   #endif\n   j->resample_row_hv_2_kernel = stbi__resample_row_hv_2_simd;\n#endif\n}\n\n// clean up the temporary component buffers\nstatic void stbi__cleanup_jpeg(stbi__jpeg *j)\n{\n   int i;\n   for (i=0; i < j->s->img_n; ++i) {\n      if (j->img_comp[i].raw_data) {\n         STBI_FREE(j->img_comp[i].raw_data);\n         j->img_comp[i].raw_data = NULL;\n         j->img_comp[i].data = NULL;\n      }\n      if (j->img_comp[i].raw_coeff) {\n         STBI_FREE(j->img_comp[i].raw_coeff);\n         j->img_comp[i].raw_coeff = 0;\n         j->img_comp[i].coeff = 0;\n      }\n      if (j->img_comp[i].linebuf) {\n         STBI_FREE(j->img_comp[i].linebuf);\n         j->img_comp[i].linebuf = NULL;\n      }\n   }\n}\n\ntypedef struct\n{\n   resample_row_func resample;\n   stbi_uc *line0,*line1;\n   int hs,vs;   // expansion factor in each axis\n   int w_lores; // horizontal pixels pre-expansion\n   int ystep;   // how far through vertical expansion we are\n   int ypos;    // which pre-expansion row we're on\n} stbi__resample;\n\nstatic stbi_uc *load_jpeg_image(stbi__jpeg *z, int *out_x, int *out_y, int *comp, int req_comp)\n{\n   int n, decode_n;\n   z->s->img_n = 0; // make stbi__cleanup_jpeg safe\n\n   // validate req_comp\n   if (req_comp < 0 || req_comp > 4) return stbi__errpuc(\"bad req_comp\", \"Internal error\");\n\n   // load a jpeg image from whichever source, but leave in YCbCr format\n   if (!stbi__decode_jpeg_image(z)) { stbi__cleanup_jpeg(z); return NULL; }\n\n   // determine actual number of components to generate\n   n = req_comp ? req_comp : z->s->img_n;\n\n   if (z->s->img_n == 3 && n < 3)\n      decode_n = 1;\n   else\n      decode_n = z->s->img_n;\n\n   // resample and color-convert\n   {\n      int k;\n      unsigned int i,j;\n      stbi_uc *output;\n      stbi_uc *coutput[4];\n\n      stbi__resample res_comp[4];\n\n      for (k=0; k < decode_n; ++k) {\n         stbi__resample *r = &res_comp[k];\n\n         // allocate line buffer big enough for upsampling off the edges\n         // with upsample factor of 4\n         z->img_comp[k].linebuf = (stbi_uc *) stbi__malloc(z->s->img_x + 3);\n         if (!z->img_comp[k].linebuf) { stbi__cleanup_jpeg(z); return stbi__errpuc(\"outofmem\", \"Out of memory\"); }\n\n         r->hs      = z->img_h_max / z->img_comp[k].h;\n         r->vs      = z->img_v_max / z->img_comp[k].v;\n         r->ystep   = r->vs >> 1;\n         r->w_lores = (z->s->img_x + r->hs-1) / r->hs;\n         r->ypos    = 0;\n         r->line0   = r->line1 = z->img_comp[k].data;\n\n         if      (r->hs == 1 && r->vs == 1) r->resample = resample_row_1;\n         else if (r->hs == 1 && r->vs == 2) r->resample = stbi__resample_row_v_2;\n         else if (r->hs == 2 && r->vs == 1) r->resample = stbi__resample_row_h_2;\n         else if (r->hs == 2 && r->vs == 2) r->resample = z->resample_row_hv_2_kernel;\n         else                               r->resample = stbi__resample_row_generic;\n      }\n\n      // can't error after this so, this is safe\n      output = (stbi_uc *) stbi__malloc(n * z->s->img_x * z->s->img_y + 1);\n      if (!output) { stbi__cleanup_jpeg(z); return stbi__errpuc(\"outofmem\", \"Out of memory\"); }\n\n      // now go ahead and resample\n      for (j=0; j < z->s->img_y; ++j) {\n         stbi_uc *out = output + n * z->s->img_x * j;\n         for (k=0; k < decode_n; ++k) {\n            stbi__resample *r = &res_comp[k];\n            int y_bot = r->ystep >= (r->vs >> 1);\n            coutput[k] = r->resample(z->img_comp[k].linebuf,\n                                     y_bot ? r->line1 : r->line0,\n                                     y_bot ? r->line0 : r->line1,\n                                     r->w_lores, r->hs);\n            if (++r->ystep >= r->vs) {\n               r->ystep = 0;\n               r->line0 = r->line1;\n               if (++r->ypos < z->img_comp[k].y)\n                  r->line1 += z->img_comp[k].w2;\n            }\n         }\n         if (n >= 3) {\n            stbi_uc *y = coutput[0];\n            if (z->s->img_n == 3) {\n               z->YCbCr_to_RGB_kernel(out, y, coutput[1], coutput[2], z->s->img_x, n);\n            } else\n               for (i=0; i < z->s->img_x; ++i) {\n                  out[0] = out[1] = out[2] = y[i];\n                  out[3] = 255; // not used if n==3\n                  out += n;\n               }\n         } else {\n            stbi_uc *y = coutput[0];\n            if (n == 1)\n               for (i=0; i < z->s->img_x; ++i) out[i] = y[i];\n            else\n               for (i=0; i < z->s->img_x; ++i) *out++ = y[i], *out++ = 255;\n         }\n      }\n      stbi__cleanup_jpeg(z);\n      *out_x = z->s->img_x;\n      *out_y = z->s->img_y;\n      if (comp) *comp  = z->s->img_n; // report original components, not output\n      return output;\n   }\n}\n\nstatic unsigned char *stbi__jpeg_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__jpeg j;\n   j.s = s;\n   stbi__setup_jpeg(&j);\n   return load_jpeg_image(&j, x,y,comp,req_comp);\n}\n\nstatic int stbi__jpeg_test(stbi__context *s)\n{\n   int r;\n   stbi__jpeg j;\n   j.s = s;\n   stbi__setup_jpeg(&j);\n   r = stbi__decode_jpeg_header(&j, STBI__SCAN_type);\n   stbi__rewind(s);\n   return r;\n}\n\nstatic int stbi__jpeg_info_raw(stbi__jpeg *j, int *x, int *y, int *comp)\n{\n   if (!stbi__decode_jpeg_header(j, STBI__SCAN_header)) {\n      stbi__rewind( j->s );\n      return 0;\n   }\n   if (x) *x = j->s->img_x;\n   if (y) *y = j->s->img_y;\n   if (comp) *comp = j->s->img_n;\n   return 1;\n}\n\nstatic int stbi__jpeg_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   stbi__jpeg j;\n   j.s = s;\n   return stbi__jpeg_info_raw(&j, x, y, comp);\n}\n#endif\n\n// public domain zlib decode    v0.2  Sean Barrett 2006-11-18\n//    simple implementation\n//      - all input must be provided in an upfront buffer\n//      - all output is written to a single output buffer (can malloc/realloc)\n//    performance\n//      - fast huffman\n\n#ifndef STBI_NO_ZLIB\n\n// fast-way is faster to check than jpeg huffman, but slow way is slower\n#define STBI__ZFAST_BITS  9 // accelerate all cases in default tables\n#define STBI__ZFAST_MASK  ((1 << STBI__ZFAST_BITS) - 1)\n\n// zlib-style huffman encoding\n// (jpegs packs from left, zlib from right, so can't share code)\ntypedef struct\n{\n   stbi__uint16 fast[1 << STBI__ZFAST_BITS];\n   stbi__uint16 firstcode[16];\n   int maxcode[17];\n   stbi__uint16 firstsymbol[16];\n   stbi_uc  size[288];\n   stbi__uint16 value[288];\n} stbi__zhuffman;\n\nstbi_inline static int stbi__bitreverse16(int n)\n{\n  n = ((n & 0xAAAA) >>  1) | ((n & 0x5555) << 1);\n  n = ((n & 0xCCCC) >>  2) | ((n & 0x3333) << 2);\n  n = ((n & 0xF0F0) >>  4) | ((n & 0x0F0F) << 4);\n  n = ((n & 0xFF00) >>  8) | ((n & 0x00FF) << 8);\n  return n;\n}\n\nstbi_inline static int stbi__bit_reverse(int v, int bits)\n{\n   STBI_ASSERT(bits <= 16);\n   // to bit reverse n bits, reverse 16 and shift\n   // e.g. 11 bits, bit reverse and shift away 5\n   return stbi__bitreverse16(v) >> (16-bits);\n}\n\nstatic int stbi__zbuild_huffman(stbi__zhuffman *z, stbi_uc *sizelist, int num)\n{\n   int i,k=0;\n   int code, next_code[16], sizes[17];\n\n   // DEFLATE spec for generating codes\n   memset(sizes, 0, sizeof(sizes));\n   memset(z->fast, 0, sizeof(z->fast));\n   for (i=0; i < num; ++i)\n      ++sizes[sizelist[i]];\n   sizes[0] = 0;\n   for (i=1; i < 16; ++i)\n      if (sizes[i] > (1 << i))\n         return stbi__err(\"bad sizes\", \"Corrupt PNG\");\n   code = 0;\n   for (i=1; i < 16; ++i) {\n      next_code[i] = code;\n      z->firstcode[i] = (stbi__uint16) code;\n      z->firstsymbol[i] = (stbi__uint16) k;\n      code = (code + sizes[i]);\n      if (sizes[i])\n         if (code-1 >= (1 << i)) return stbi__err(\"bad codelengths\",\"Corrupt PNG\");\n      z->maxcode[i] = code << (16-i); // preshift for inner loop\n      code <<= 1;\n      k += sizes[i];\n   }\n   z->maxcode[16] = 0x10000; // sentinel\n   for (i=0; i < num; ++i) {\n      int s = sizelist[i];\n      if (s) {\n         int c = next_code[s] - z->firstcode[s] + z->firstsymbol[s];\n         stbi__uint16 fastv = (stbi__uint16) ((s << 9) | i);\n         z->size [c] = (stbi_uc     ) s;\n         z->value[c] = (stbi__uint16) i;\n         if (s <= STBI__ZFAST_BITS) {\n            int j = stbi__bit_reverse(next_code[s],s);\n            while (j < (1 << STBI__ZFAST_BITS)) {\n               z->fast[j] = fastv;\n               j += (1 << s);\n            }\n         }\n         ++next_code[s];\n      }\n   }\n   return 1;\n}\n\n// zlib-from-memory implementation for PNG reading\n//    because PNG allows splitting the zlib stream arbitrarily,\n//    and it's annoying structurally to have PNG call ZLIB call PNG,\n//    we require PNG read all the IDATs and combine them into a single\n//    memory buffer\n\ntypedef struct\n{\n   stbi_uc *zbuffer, *zbuffer_end;\n   int num_bits;\n   stbi__uint32 code_buffer;\n\n   char *zout;\n   char *zout_start;\n   char *zout_end;\n   int   z_expandable;\n\n   stbi__zhuffman z_length, z_distance;\n} stbi__zbuf;\n\nstbi_inline static stbi_uc stbi__zget8(stbi__zbuf *z)\n{\n   if (z->zbuffer >= z->zbuffer_end) return 0;\n   return *z->zbuffer++;\n}\n\nstatic void stbi__fill_bits(stbi__zbuf *z)\n{\n   do {\n      STBI_ASSERT(z->code_buffer < (1U << z->num_bits));\n      z->code_buffer |= (unsigned int) stbi__zget8(z) << z->num_bits;\n      z->num_bits += 8;\n   } while (z->num_bits <= 24);\n}\n\nstbi_inline static unsigned int stbi__zreceive(stbi__zbuf *z, int n)\n{\n   unsigned int k;\n   if (z->num_bits < n) stbi__fill_bits(z);\n   k = z->code_buffer & ((1 << n) - 1);\n   z->code_buffer >>= n;\n   z->num_bits -= n;\n   return k;\n}\n\nstatic int stbi__zhuffman_decode_slowpath(stbi__zbuf *a, stbi__zhuffman *z)\n{\n   int b,s,k;\n   // not resolved by fast table, so compute it the slow way\n   // use jpeg approach, which requires MSbits at top\n   k = stbi__bit_reverse(a->code_buffer, 16);\n   for (s=STBI__ZFAST_BITS+1; ; ++s)\n      if (k < z->maxcode[s])\n         break;\n   if (s == 16) return -1; // invalid code!\n   // code size is s, so:\n   b = (k >> (16-s)) - z->firstcode[s] + z->firstsymbol[s];\n   STBI_ASSERT(z->size[b] == s);\n   a->code_buffer >>= s;\n   a->num_bits -= s;\n   return z->value[b];\n}\n\nstbi_inline static int stbi__zhuffman_decode(stbi__zbuf *a, stbi__zhuffman *z)\n{\n   int b,s;\n   if (a->num_bits < 16) stbi__fill_bits(a);\n   b = z->fast[a->code_buffer & STBI__ZFAST_MASK];\n   if (b) {\n      s = b >> 9;\n      a->code_buffer >>= s;\n      a->num_bits -= s;\n      return b & 511;\n   }\n   return stbi__zhuffman_decode_slowpath(a, z);\n}\n\nstatic int stbi__zexpand(stbi__zbuf *z, char *zout, int n)  // need to make room for n bytes\n{\n   char *q;\n   int cur, limit, old_limit;\n   z->zout = zout;\n   if (!z->z_expandable) return stbi__err(\"output buffer limit\",\"Corrupt PNG\");\n   cur   = (int) (z->zout     - z->zout_start);\n   limit = old_limit = (int) (z->zout_end - z->zout_start);\n   while (cur + n > limit)\n      limit *= 2;\n   q = (char *) STBI_REALLOC_SIZED(z->zout_start, old_limit, limit);\n   STBI_NOTUSED(old_limit);\n   if (q == NULL) return stbi__err(\"outofmem\", \"Out of memory\");\n   z->zout_start = q;\n   z->zout       = q + cur;\n   z->zout_end   = q + limit;\n   return 1;\n}\n\nstatic int stbi__zlength_base[31] = {\n   3,4,5,6,7,8,9,10,11,13,\n   15,17,19,23,27,31,35,43,51,59,\n   67,83,99,115,131,163,195,227,258,0,0 };\n\nstatic int stbi__zlength_extra[31]=\n{ 0,0,0,0,0,0,0,0,1,1,1,1,2,2,2,2,3,3,3,3,4,4,4,4,5,5,5,5,0,0,0 };\n\nstatic int stbi__zdist_base[32] = { 1,2,3,4,5,7,9,13,17,25,33,49,65,97,129,193,\n257,385,513,769,1025,1537,2049,3073,4097,6145,8193,12289,16385,24577,0,0};\n\nstatic int stbi__zdist_extra[32] =\n{ 0,0,0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,11,11,12,12,13,13};\n\nstatic int stbi__parse_huffman_block(stbi__zbuf *a)\n{\n   char *zout = a->zout;\n   for(;;) {\n      int z = stbi__zhuffman_decode(a, &a->z_length);\n      if (z < 256) {\n         if (z < 0) return stbi__err(\"bad huffman code\",\"Corrupt PNG\"); // error in huffman codes\n         if (zout >= a->zout_end) {\n            if (!stbi__zexpand(a, zout, 1)) return 0;\n            zout = a->zout;\n         }\n         *zout++ = (char) z;\n      } else {\n         stbi_uc *p;\n         int len,dist;\n         if (z == 256) {\n            a->zout = zout;\n            return 1;\n         }\n         z -= 257;\n         len = stbi__zlength_base[z];\n         if (stbi__zlength_extra[z]) len += stbi__zreceive(a, stbi__zlength_extra[z]);\n         z = stbi__zhuffman_decode(a, &a->z_distance);\n         if (z < 0) return stbi__err(\"bad huffman code\",\"Corrupt PNG\");\n         dist = stbi__zdist_base[z];\n         if (stbi__zdist_extra[z]) dist += stbi__zreceive(a, stbi__zdist_extra[z]);\n         if (zout - a->zout_start < dist) return stbi__err(\"bad dist\",\"Corrupt PNG\");\n         if (zout + len > a->zout_end) {\n            if (!stbi__zexpand(a, zout, len)) return 0;\n            zout = a->zout;\n         }\n         p = (stbi_uc *) (zout - dist);\n         if (dist == 1) { // run of one byte; common in images.\n            stbi_uc v = *p;\n            if (len) { do *zout++ = v; while (--len); }\n         } else {\n            if (len) { do *zout++ = *p++; while (--len); }\n         }\n      }\n   }\n}\n\nstatic int stbi__compute_huffman_codes(stbi__zbuf *a)\n{\n   static stbi_uc length_dezigzag[19] = { 16,17,18,0,8,7,9,6,10,5,11,4,12,3,13,2,14,1,15 };\n   stbi__zhuffman z_codelength;\n   stbi_uc lencodes[286+32+137];//padding for maximum single op\n   stbi_uc codelength_sizes[19];\n   int i,n;\n\n   int hlit  = stbi__zreceive(a,5) + 257;\n   int hdist = stbi__zreceive(a,5) + 1;\n   int hclen = stbi__zreceive(a,4) + 4;\n\n   memset(codelength_sizes, 0, sizeof(codelength_sizes));\n   for (i=0; i < hclen; ++i) {\n      int s = stbi__zreceive(a,3);\n      codelength_sizes[length_dezigzag[i]] = (stbi_uc) s;\n   }\n   if (!stbi__zbuild_huffman(&z_codelength, codelength_sizes, 19)) return 0;\n\n   n = 0;\n   while (n < hlit + hdist) {\n      int c = stbi__zhuffman_decode(a, &z_codelength);\n      if (c < 0 || c >= 19) return stbi__err(\"bad codelengths\", \"Corrupt PNG\");\n      if (c < 16)\n         lencodes[n++] = (stbi_uc) c;\n      else if (c == 16) {\n         c = stbi__zreceive(a,2)+3;\n         memset(lencodes+n, lencodes[n-1], c);\n         n += c;\n      } else if (c == 17) {\n         c = stbi__zreceive(a,3)+3;\n         memset(lencodes+n, 0, c);\n         n += c;\n      } else {\n         STBI_ASSERT(c == 18);\n         c = stbi__zreceive(a,7)+11;\n         memset(lencodes+n, 0, c);\n         n += c;\n      }\n   }\n   if (n != hlit+hdist) return stbi__err(\"bad codelengths\",\"Corrupt PNG\");\n   if (!stbi__zbuild_huffman(&a->z_length, lencodes, hlit)) return 0;\n   if (!stbi__zbuild_huffman(&a->z_distance, lencodes+hlit, hdist)) return 0;\n   return 1;\n}\n\nstatic int stbi__parse_uncomperssed_block(stbi__zbuf *a)\n{\n   stbi_uc header[4];\n   int len,nlen,k;\n   if (a->num_bits & 7)\n      stbi__zreceive(a, a->num_bits & 7); // discard\n   // drain the bit-packed data into header\n   k = 0;\n   while (a->num_bits > 0) {\n      header[k++] = (stbi_uc) (a->code_buffer & 255); // suppress MSVC run-time check\n      a->code_buffer >>= 8;\n      a->num_bits -= 8;\n   }\n   STBI_ASSERT(a->num_bits == 0);\n   // now fill header the normal way\n   while (k < 4)\n      header[k++] = stbi__zget8(a);\n   len  = header[1] * 256 + header[0];\n   nlen = header[3] * 256 + header[2];\n   if (nlen != (len ^ 0xffff)) return stbi__err(\"zlib corrupt\",\"Corrupt PNG\");\n   if (a->zbuffer + len > a->zbuffer_end) return stbi__err(\"read past buffer\",\"Corrupt PNG\");\n   if (a->zout + len > a->zout_end)\n      if (!stbi__zexpand(a, a->zout, len)) return 0;\n   memcpy(a->zout, a->zbuffer, len);\n   a->zbuffer += len;\n   a->zout += len;\n   return 1;\n}\n\nstatic int stbi__parse_zlib_header(stbi__zbuf *a)\n{\n   int cmf   = stbi__zget8(a);\n   int cm    = cmf & 15;\n   /* int cinfo = cmf >> 4; */\n   int flg   = stbi__zget8(a);\n   if ((cmf*256+flg) % 31 != 0) return stbi__err(\"bad zlib header\",\"Corrupt PNG\"); // zlib spec\n   if (flg & 32) return stbi__err(\"no preset dict\",\"Corrupt PNG\"); // preset dictionary not allowed in png\n   if (cm != 8) return stbi__err(\"bad compression\",\"Corrupt PNG\"); // DEFLATE required for png\n   // window = 1 << (8 + cinfo)... but who cares, we fully buffer output\n   return 1;\n}\n\n// @TODO: should statically initialize these for optimal thread safety\nstatic stbi_uc stbi__zdefault_length[288], stbi__zdefault_distance[32];\nstatic void stbi__init_zdefaults(void)\n{\n   int i;   // use <= to match clearly with spec\n   for (i=0; i <= 143; ++i)     stbi__zdefault_length[i]   = 8;\n   for (   ; i <= 255; ++i)     stbi__zdefault_length[i]   = 9;\n   for (   ; i <= 279; ++i)     stbi__zdefault_length[i]   = 7;\n   for (   ; i <= 287; ++i)     stbi__zdefault_length[i]   = 8;\n\n   for (i=0; i <=  31; ++i)     stbi__zdefault_distance[i] = 5;\n}\n\nstatic int stbi__parse_zlib(stbi__zbuf *a, int parse_header)\n{\n   int final, type;\n   if (parse_header)\n      if (!stbi__parse_zlib_header(a)) return 0;\n   a->num_bits = 0;\n   a->code_buffer = 0;\n   do {\n      final = stbi__zreceive(a,1);\n      type = stbi__zreceive(a,2);\n      if (type == 0) {\n         if (!stbi__parse_uncomperssed_block(a)) return 0;\n      } else if (type == 3) {\n         return 0;\n      } else {\n         if (type == 1) {\n            // use fixed code lengths\n            if (!stbi__zdefault_distance[31]) stbi__init_zdefaults();\n            if (!stbi__zbuild_huffman(&a->z_length  , stbi__zdefault_length  , 288)) return 0;\n            if (!stbi__zbuild_huffman(&a->z_distance, stbi__zdefault_distance,  32)) return 0;\n         } else {\n            if (!stbi__compute_huffman_codes(a)) return 0;\n         }\n         if (!stbi__parse_huffman_block(a)) return 0;\n      }\n   } while (!final);\n   return 1;\n}\n\nstatic int stbi__do_zlib(stbi__zbuf *a, char *obuf, int olen, int exp, int parse_header)\n{\n   a->zout_start = obuf;\n   a->zout       = obuf;\n   a->zout_end   = obuf + olen;\n   a->z_expandable = exp;\n\n   return stbi__parse_zlib(a, parse_header);\n}\n\nSTBIDEF char *stbi_zlib_decode_malloc_guesssize(const char *buffer, int len, int initial_size, int *outlen)\n{\n   stbi__zbuf a;\n   char *p = (char *) stbi__malloc(initial_size);\n   if (p == NULL) return NULL;\n   a.zbuffer = (stbi_uc *) buffer;\n   a.zbuffer_end = (stbi_uc *) buffer + len;\n   if (stbi__do_zlib(&a, p, initial_size, 1, 1)) {\n      if (outlen) *outlen = (int) (a.zout - a.zout_start);\n      return a.zout_start;\n   } else {\n      STBI_FREE(a.zout_start);\n      return NULL;\n   }\n}\n\nSTBIDEF char *stbi_zlib_decode_malloc(char const *buffer, int len, int *outlen)\n{\n   return stbi_zlib_decode_malloc_guesssize(buffer, len, 16384, outlen);\n}\n\nSTBIDEF char *stbi_zlib_decode_malloc_guesssize_headerflag(const char *buffer, int len, int initial_size, int *outlen, int parse_header)\n{\n   stbi__zbuf a;\n   char *p = (char *) stbi__malloc(initial_size);\n   if (p == NULL) return NULL;\n   a.zbuffer = (stbi_uc *) buffer;\n   a.zbuffer_end = (stbi_uc *) buffer + len;\n   if (stbi__do_zlib(&a, p, initial_size, 1, parse_header)) {\n      if (outlen) *outlen = (int) (a.zout - a.zout_start);\n      return a.zout_start;\n   } else {\n      STBI_FREE(a.zout_start);\n      return NULL;\n   }\n}\n\nSTBIDEF int stbi_zlib_decode_buffer(char *obuffer, int olen, char const *ibuffer, int ilen)\n{\n   stbi__zbuf a;\n   a.zbuffer = (stbi_uc *) ibuffer;\n   a.zbuffer_end = (stbi_uc *) ibuffer + ilen;\n   if (stbi__do_zlib(&a, obuffer, olen, 0, 1))\n      return (int) (a.zout - a.zout_start);\n   else\n      return -1;\n}\n\nSTBIDEF char *stbi_zlib_decode_noheader_malloc(char const *buffer, int len, int *outlen)\n{\n   stbi__zbuf a;\n   char *p = (char *) stbi__malloc(16384);\n   if (p == NULL) return NULL;\n   a.zbuffer = (stbi_uc *) buffer;\n   a.zbuffer_end = (stbi_uc *) buffer+len;\n   if (stbi__do_zlib(&a, p, 16384, 1, 0)) {\n      if (outlen) *outlen = (int) (a.zout - a.zout_start);\n      return a.zout_start;\n   } else {\n      STBI_FREE(a.zout_start);\n      return NULL;\n   }\n}\n\nSTBIDEF int stbi_zlib_decode_noheader_buffer(char *obuffer, int olen, const char *ibuffer, int ilen)\n{\n   stbi__zbuf a;\n   a.zbuffer = (stbi_uc *) ibuffer;\n   a.zbuffer_end = (stbi_uc *) ibuffer + ilen;\n   if (stbi__do_zlib(&a, obuffer, olen, 0, 0))\n      return (int) (a.zout - a.zout_start);\n   else\n      return -1;\n}\n#endif\n\n// public domain \"baseline\" PNG decoder   v0.10  Sean Barrett 2006-11-18\n//    simple implementation\n//      - only 8-bit samples\n//      - no CRC checking\n//      - allocates lots of intermediate memory\n//        - avoids problem of streaming data between subsystems\n//        - avoids explicit window management\n//    performance\n//      - uses stb_zlib, a PD zlib implementation with fast huffman decoding\n\n#ifndef STBI_NO_PNG\ntypedef struct\n{\n   stbi__uint32 length;\n   stbi__uint32 type;\n} stbi__pngchunk;\n\nstatic stbi__pngchunk stbi__get_chunk_header(stbi__context *s)\n{\n   stbi__pngchunk c;\n   c.length = stbi__get32be(s);\n   c.type   = stbi__get32be(s);\n   return c;\n}\n\nstatic int stbi__check_png_header(stbi__context *s)\n{\n   static stbi_uc png_sig[8] = { 137,80,78,71,13,10,26,10 };\n   int i;\n   for (i=0; i < 8; ++i)\n      if (stbi__get8(s) != png_sig[i]) return stbi__err(\"bad png sig\",\"Not a PNG\");\n   return 1;\n}\n\ntypedef struct\n{\n   stbi__context *s;\n   stbi_uc *idata, *expanded, *out;\n} stbi__png;\n\n\nenum {\n   STBI__F_none=0,\n   STBI__F_sub=1,\n   STBI__F_up=2,\n   STBI__F_avg=3,\n   STBI__F_paeth=4,\n   // synthetic filters used for first scanline to avoid needing a dummy row of 0s\n   STBI__F_avg_first,\n   STBI__F_paeth_first\n};\n\nstatic stbi_uc first_row_filter[5] =\n{\n   STBI__F_none,\n   STBI__F_sub,\n   STBI__F_none,\n   STBI__F_avg_first,\n   STBI__F_paeth_first\n};\n\nstatic int stbi__paeth(int a, int b, int c)\n{\n   int p = a + b - c;\n   int pa = abs(p-a);\n   int pb = abs(p-b);\n   int pc = abs(p-c);\n   if (pa <= pb && pa <= pc) return a;\n   if (pb <= pc) return b;\n   return c;\n}\n\nstatic stbi_uc stbi__depth_scale_table[9] = { 0, 0xff, 0x55, 0, 0x11, 0,0,0, 0x01 };\n\n// create the png data from post-deflated data\nstatic int stbi__create_png_image_raw(stbi__png *a, stbi_uc *raw, stbi__uint32 raw_len, int out_n, stbi__uint32 x, stbi__uint32 y, int depth, int color)\n{\n   stbi__context *s = a->s;\n   stbi__uint32 i,j,stride = x*out_n;\n   stbi__uint32 img_len, img_width_bytes;\n   int k;\n   int img_n = s->img_n; // copy it into a local for later\n\n   STBI_ASSERT(out_n == s->img_n || out_n == s->img_n+1);\n   a->out = (stbi_uc *) stbi__malloc(x * y * out_n); // extra bytes to write off the end into\n   if (!a->out) return stbi__err(\"outofmem\", \"Out of memory\");\n\n   img_width_bytes = (((img_n * x * depth) + 7) >> 3);\n   img_len = (img_width_bytes + 1) * y;\n   if (s->img_x == x && s->img_y == y) {\n      if (raw_len != img_len) return stbi__err(\"not enough pixels\",\"Corrupt PNG\");\n   } else { // interlaced:\n      if (raw_len < img_len) return stbi__err(\"not enough pixels\",\"Corrupt PNG\");\n   }\n\n   for (j=0; j < y; ++j) {\n      stbi_uc *cur = a->out + stride*j;\n      stbi_uc *prior = cur - stride;\n      int filter = *raw++;\n      int filter_bytes = img_n;\n      int width = x;\n      if (filter > 4)\n         return stbi__err(\"invalid filter\",\"Corrupt PNG\");\n\n      if (depth < 8) {\n         STBI_ASSERT(img_width_bytes <= x);\n         cur += x*out_n - img_width_bytes; // store output to the rightmost img_len bytes, so we can decode in place\n         filter_bytes = 1;\n         width = img_width_bytes;\n      }\n\n      // if first row, use special filter that doesn't sample previous row\n      if (j == 0) filter = first_row_filter[filter];\n\n      // handle first byte explicitly\n      for (k=0; k < filter_bytes; ++k) {\n         switch (filter) {\n            case STBI__F_none       : cur[k] = raw[k]; break;\n            case STBI__F_sub        : cur[k] = raw[k]; break;\n            case STBI__F_up         : cur[k] = STBI__BYTECAST(raw[k] + prior[k]); break;\n            case STBI__F_avg        : cur[k] = STBI__BYTECAST(raw[k] + (prior[k]>>1)); break;\n            case STBI__F_paeth      : cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(0,prior[k],0)); break;\n            case STBI__F_avg_first  : cur[k] = raw[k]; break;\n            case STBI__F_paeth_first: cur[k] = raw[k]; break;\n         }\n      }\n\n      if (depth == 8) {\n         if (img_n != out_n)\n            cur[img_n] = 255; // first pixel\n         raw += img_n;\n         cur += out_n;\n         prior += out_n;\n      } else {\n         raw += 1;\n         cur += 1;\n         prior += 1;\n      }\n\n      // this is a little gross, so that we don't switch per-pixel or per-component\n      if (depth < 8 || img_n == out_n) {\n         int nk = (width - 1)*img_n;\n         #define CASE(f) \\\n             case f:     \\\n                for (k=0; k < nk; ++k)\n         switch (filter) {\n            // \"none\" filter turns into a memcpy here; make that explicit.\n            case STBI__F_none:         memcpy(cur, raw, nk); break;\n            CASE(STBI__F_sub)          cur[k] = STBI__BYTECAST(raw[k] + cur[k-filter_bytes]); break;\n            CASE(STBI__F_up)           cur[k] = STBI__BYTECAST(raw[k] + prior[k]); break;\n            CASE(STBI__F_avg)          cur[k] = STBI__BYTECAST(raw[k] + ((prior[k] + cur[k-filter_bytes])>>1)); break;\n            CASE(STBI__F_paeth)        cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k-filter_bytes],prior[k],prior[k-filter_bytes])); break;\n            CASE(STBI__F_avg_first)    cur[k] = STBI__BYTECAST(raw[k] + (cur[k-filter_bytes] >> 1)); break;\n            CASE(STBI__F_paeth_first)  cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k-filter_bytes],0,0)); break;\n         }\n         #undef CASE\n         raw += nk;\n      } else {\n         STBI_ASSERT(img_n+1 == out_n);\n         #define CASE(f) \\\n             case f:     \\\n                for (i=x-1; i >= 1; --i, cur[img_n]=255,raw+=img_n,cur+=out_n,prior+=out_n) \\\n                   for (k=0; k < img_n; ++k)\n         switch (filter) {\n            CASE(STBI__F_none)         cur[k] = raw[k]; break;\n            CASE(STBI__F_sub)          cur[k] = STBI__BYTECAST(raw[k] + cur[k-out_n]); break;\n            CASE(STBI__F_up)           cur[k] = STBI__BYTECAST(raw[k] + prior[k]); break;\n            CASE(STBI__F_avg)          cur[k] = STBI__BYTECAST(raw[k] + ((prior[k] + cur[k-out_n])>>1)); break;\n            CASE(STBI__F_paeth)        cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k-out_n],prior[k],prior[k-out_n])); break;\n            CASE(STBI__F_avg_first)    cur[k] = STBI__BYTECAST(raw[k] + (cur[k-out_n] >> 1)); break;\n            CASE(STBI__F_paeth_first)  cur[k] = STBI__BYTECAST(raw[k] + stbi__paeth(cur[k-out_n],0,0)); break;\n         }\n         #undef CASE\n      }\n   }\n\n   // we make a separate pass to expand bits to pixels; for performance,\n   // this could run two scanlines behind the above code, so it won't\n   // intefere with filtering but will still be in the cache.\n   if (depth < 8) {\n      for (j=0; j < y; ++j) {\n         stbi_uc *cur = a->out + stride*j;\n         stbi_uc *in  = a->out + stride*j + x*out_n - img_width_bytes;\n         // unpack 1/2/4-bit into a 8-bit buffer. allows us to keep the common 8-bit path optimal at minimal cost for 1/2/4-bit\n         // png guarante byte alignment, if width is not multiple of 8/4/2 we'll decode dummy trailing data that will be skipped in the later loop\n         stbi_uc scale = (color == 0) ? stbi__depth_scale_table[depth] : 1; // scale grayscale values to 0..255 range\n\n         // note that the final byte might overshoot and write more data than desired.\n         // we can allocate enough data that this never writes out of memory, but it\n         // could also overwrite the next scanline. can it overwrite non-empty data\n         // on the next scanline? yes, consider 1-pixel-wide scanlines with 1-bit-per-pixel.\n         // so we need to explicitly clamp the final ones\n\n         if (depth == 4) {\n            for (k=x*img_n; k >= 2; k-=2, ++in) {\n               *cur++ = scale * ((*in >> 4)       );\n               *cur++ = scale * ((*in     ) & 0x0f);\n            }\n            if (k > 0) *cur++ = scale * ((*in >> 4)       );\n         } else if (depth == 2) {\n            for (k=x*img_n; k >= 4; k-=4, ++in) {\n               *cur++ = scale * ((*in >> 6)       );\n               *cur++ = scale * ((*in >> 4) & 0x03);\n               *cur++ = scale * ((*in >> 2) & 0x03);\n               *cur++ = scale * ((*in     ) & 0x03);\n            }\n            if (k > 0) *cur++ = scale * ((*in >> 6)       );\n            if (k > 1) *cur++ = scale * ((*in >> 4) & 0x03);\n            if (k > 2) *cur++ = scale * ((*in >> 2) & 0x03);\n         } else if (depth == 1) {\n            for (k=x*img_n; k >= 8; k-=8, ++in) {\n               *cur++ = scale * ((*in >> 7)       );\n               *cur++ = scale * ((*in >> 6) & 0x01);\n               *cur++ = scale * ((*in >> 5) & 0x01);\n               *cur++ = scale * ((*in >> 4) & 0x01);\n               *cur++ = scale * ((*in >> 3) & 0x01);\n               *cur++ = scale * ((*in >> 2) & 0x01);\n               *cur++ = scale * ((*in >> 1) & 0x01);\n               *cur++ = scale * ((*in     ) & 0x01);\n            }\n            if (k > 0) *cur++ = scale * ((*in >> 7)       );\n            if (k > 1) *cur++ = scale * ((*in >> 6) & 0x01);\n            if (k > 2) *cur++ = scale * ((*in >> 5) & 0x01);\n            if (k > 3) *cur++ = scale * ((*in >> 4) & 0x01);\n            if (k > 4) *cur++ = scale * ((*in >> 3) & 0x01);\n            if (k > 5) *cur++ = scale * ((*in >> 2) & 0x01);\n            if (k > 6) *cur++ = scale * ((*in >> 1) & 0x01);\n         }\n         if (img_n != out_n) {\n            int q;\n            // insert alpha = 255\n            cur = a->out + stride*j;\n            if (img_n == 1) {\n               for (q=x-1; q >= 0; --q) {\n                  cur[q*2+1] = 255;\n                  cur[q*2+0] = cur[q];\n               }\n            } else {\n               STBI_ASSERT(img_n == 3);\n               for (q=x-1; q >= 0; --q) {\n                  cur[q*4+3] = 255;\n                  cur[q*4+2] = cur[q*3+2];\n                  cur[q*4+1] = cur[q*3+1];\n                  cur[q*4+0] = cur[q*3+0];\n               }\n            }\n         }\n      }\n   }\n\n   return 1;\n}\n\nstatic int stbi__create_png_image(stbi__png *a, stbi_uc *image_data, stbi__uint32 image_data_len, int out_n, int depth, int color, int interlaced)\n{\n   stbi_uc *final;\n   int p;\n   if (!interlaced)\n      return stbi__create_png_image_raw(a, image_data, image_data_len, out_n, a->s->img_x, a->s->img_y, depth, color);\n\n   // de-interlacing\n   final = (stbi_uc *) stbi__malloc(a->s->img_x * a->s->img_y * out_n);\n   for (p=0; p < 7; ++p) {\n      int xorig[] = { 0,4,0,2,0,1,0 };\n      int yorig[] = { 0,0,4,0,2,0,1 };\n      int xspc[]  = { 8,8,4,4,2,2,1 };\n      int yspc[]  = { 8,8,8,4,4,2,2 };\n      int i,j,x,y;\n      // pass1_x[4] = 0, pass1_x[5] = 1, pass1_x[12] = 1\n      x = (a->s->img_x - xorig[p] + xspc[p]-1) / xspc[p];\n      y = (a->s->img_y - yorig[p] + yspc[p]-1) / yspc[p];\n      if (x && y) {\n         stbi__uint32 img_len = ((((a->s->img_n * x * depth) + 7) >> 3) + 1) * y;\n         if (!stbi__create_png_image_raw(a, image_data, image_data_len, out_n, x, y, depth, color)) {\n            STBI_FREE(final);\n            return 0;\n         }\n         for (j=0; j < y; ++j) {\n            for (i=0; i < x; ++i) {\n               int out_y = j*yspc[p]+yorig[p];\n               int out_x = i*xspc[p]+xorig[p];\n               memcpy(final + out_y*a->s->img_x*out_n + out_x*out_n,\n                      a->out + (j*x+i)*out_n, out_n);\n            }\n         }\n         STBI_FREE(a->out);\n         image_data += img_len;\n         image_data_len -= img_len;\n      }\n   }\n   a->out = final;\n\n   return 1;\n}\n\nstatic int stbi__compute_transparency(stbi__png *z, stbi_uc tc[3], int out_n)\n{\n   stbi__context *s = z->s;\n   stbi__uint32 i, pixel_count = s->img_x * s->img_y;\n   stbi_uc *p = z->out;\n\n   // compute color-based transparency, assuming we've\n   // already got 255 as the alpha value in the output\n   STBI_ASSERT(out_n == 2 || out_n == 4);\n\n   if (out_n == 2) {\n      for (i=0; i < pixel_count; ++i) {\n         p[1] = (p[0] == tc[0] ? 0 : 255);\n         p += 2;\n      }\n   } else {\n      for (i=0; i < pixel_count; ++i) {\n         if (p[0] == tc[0] && p[1] == tc[1] && p[2] == tc[2])\n            p[3] = 0;\n         p += 4;\n      }\n   }\n   return 1;\n}\n\nstatic int stbi__expand_png_palette(stbi__png *a, stbi_uc *palette, int len, int pal_img_n)\n{\n   stbi__uint32 i, pixel_count = a->s->img_x * a->s->img_y;\n   stbi_uc *p, *temp_out, *orig = a->out;\n\n   p = (stbi_uc *) stbi__malloc(pixel_count * pal_img_n);\n   if (p == NULL) return stbi__err(\"outofmem\", \"Out of memory\");\n\n   // between here and free(out) below, exitting would leak\n   temp_out = p;\n\n   if (pal_img_n == 3) {\n      for (i=0; i < pixel_count; ++i) {\n         int n = orig[i]*4;\n         p[0] = palette[n  ];\n         p[1] = palette[n+1];\n         p[2] = palette[n+2];\n         p += 3;\n      }\n   } else {\n      for (i=0; i < pixel_count; ++i) {\n         int n = orig[i]*4;\n         p[0] = palette[n  ];\n         p[1] = palette[n+1];\n         p[2] = palette[n+2];\n         p[3] = palette[n+3];\n         p += 4;\n      }\n   }\n   STBI_FREE(a->out);\n   a->out = temp_out;\n\n   STBI_NOTUSED(len);\n\n   return 1;\n}\n\nstatic int stbi__unpremultiply_on_load = 0;\nstatic int stbi__de_iphone_flag = 0;\n\nSTBIDEF void stbi_set_unpremultiply_on_load(int flag_true_if_should_unpremultiply)\n{\n   stbi__unpremultiply_on_load = flag_true_if_should_unpremultiply;\n}\n\nSTBIDEF void stbi_convert_iphone_png_to_rgb(int flag_true_if_should_convert)\n{\n   stbi__de_iphone_flag = flag_true_if_should_convert;\n}\n\nstatic void stbi__de_iphone(stbi__png *z)\n{\n   stbi__context *s = z->s;\n   stbi__uint32 i, pixel_count = s->img_x * s->img_y;\n   stbi_uc *p = z->out;\n\n   if (s->img_out_n == 3) {  // convert bgr to rgb\n      for (i=0; i < pixel_count; ++i) {\n         stbi_uc t = p[0];\n         p[0] = p[2];\n         p[2] = t;\n         p += 3;\n      }\n   } else {\n      STBI_ASSERT(s->img_out_n == 4);\n      if (stbi__unpremultiply_on_load) {\n         // convert bgr to rgb and unpremultiply\n         for (i=0; i < pixel_count; ++i) {\n            stbi_uc a = p[3];\n            stbi_uc t = p[0];\n            if (a) {\n               p[0] = p[2] * 255 / a;\n               p[1] = p[1] * 255 / a;\n               p[2] =  t   * 255 / a;\n            } else {\n               p[0] = p[2];\n               p[2] = t;\n            }\n            p += 4;\n         }\n      } else {\n         // convert bgr to rgb\n         for (i=0; i < pixel_count; ++i) {\n            stbi_uc t = p[0];\n            p[0] = p[2];\n            p[2] = t;\n            p += 4;\n         }\n      }\n   }\n}\n\n#define STBI__PNG_TYPE(a,b,c,d)  (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))\n\nstatic int stbi__parse_png_file(stbi__png *z, int scan, int req_comp)\n{\n   stbi_uc palette[1024], pal_img_n=0;\n   stbi_uc has_trans=0, tc[3];\n   stbi__uint32 ioff=0, idata_limit=0, i, pal_len=0;\n   int first=1,k,interlace=0, color=0, depth=0, is_iphone=0;\n   stbi__context *s = z->s;\n\n   z->expanded = NULL;\n   z->idata = NULL;\n   z->out = NULL;\n\n   if (!stbi__check_png_header(s)) return 0;\n\n   if (scan == STBI__SCAN_type) return 1;\n\n   for (;;) {\n      stbi__pngchunk c = stbi__get_chunk_header(s);\n      switch (c.type) {\n         case STBI__PNG_TYPE('C','g','B','I'):\n            is_iphone = 1;\n            stbi__skip(s, c.length);\n            break;\n         case STBI__PNG_TYPE('I','H','D','R'): {\n            int comp,filter;\n            if (!first) return stbi__err(\"multiple IHDR\",\"Corrupt PNG\");\n            first = 0;\n            if (c.length != 13) return stbi__err(\"bad IHDR len\",\"Corrupt PNG\");\n            s->img_x = stbi__get32be(s); if (s->img_x > (1 << 24)) return stbi__err(\"too large\",\"Very large image (corrupt?)\");\n            s->img_y = stbi__get32be(s); if (s->img_y > (1 << 24)) return stbi__err(\"too large\",\"Very large image (corrupt?)\");\n            depth = stbi__get8(s);  if (depth != 1 && depth != 2 && depth != 4 && depth != 8)  return stbi__err(\"1/2/4/8-bit only\",\"PNG not supported: 1/2/4/8-bit only\");\n            color = stbi__get8(s);  if (color > 6)         return stbi__err(\"bad ctype\",\"Corrupt PNG\");\n            if (color == 3) pal_img_n = 3; else if (color & 1) return stbi__err(\"bad ctype\",\"Corrupt PNG\");\n            comp  = stbi__get8(s);  if (comp) return stbi__err(\"bad comp method\",\"Corrupt PNG\");\n            filter= stbi__get8(s);  if (filter) return stbi__err(\"bad filter method\",\"Corrupt PNG\");\n            interlace = stbi__get8(s); if (interlace>1) return stbi__err(\"bad interlace method\",\"Corrupt PNG\");\n            if (!s->img_x || !s->img_y) return stbi__err(\"0-pixel image\",\"Corrupt PNG\");\n            if (!pal_img_n) {\n               s->img_n = (color & 2 ? 3 : 1) + (color & 4 ? 1 : 0);\n               if ((1 << 30) / s->img_x / s->img_n < s->img_y) return stbi__err(\"too large\", \"Image too large to decode\");\n               if (scan == STBI__SCAN_header) return 1;\n            } else {\n               // if paletted, then pal_n is our final components, and\n               // img_n is # components to decompress/filter.\n               s->img_n = 1;\n               if ((1 << 30) / s->img_x / 4 < s->img_y) return stbi__err(\"too large\",\"Corrupt PNG\");\n               // if SCAN_header, have to scan to see if we have a tRNS\n            }\n            break;\n         }\n\n         case STBI__PNG_TYPE('P','L','T','E'):  {\n            if (first) return stbi__err(\"first not IHDR\", \"Corrupt PNG\");\n            if (c.length > 256*3) return stbi__err(\"invalid PLTE\",\"Corrupt PNG\");\n            pal_len = c.length / 3;\n            if (pal_len * 3 != c.length) return stbi__err(\"invalid PLTE\",\"Corrupt PNG\");\n            for (i=0; i < pal_len; ++i) {\n               palette[i*4+0] = stbi__get8(s);\n               palette[i*4+1] = stbi__get8(s);\n               palette[i*4+2] = stbi__get8(s);\n               palette[i*4+3] = 255;\n            }\n            break;\n         }\n\n         case STBI__PNG_TYPE('t','R','N','S'): {\n            if (first) return stbi__err(\"first not IHDR\", \"Corrupt PNG\");\n            if (z->idata) return stbi__err(\"tRNS after IDAT\",\"Corrupt PNG\");\n            if (pal_img_n) {\n               if (scan == STBI__SCAN_header) { s->img_n = 4; return 1; }\n               if (pal_len == 0) return stbi__err(\"tRNS before PLTE\",\"Corrupt PNG\");\n               if (c.length > pal_len) return stbi__err(\"bad tRNS len\",\"Corrupt PNG\");\n               pal_img_n = 4;\n               for (i=0; i < c.length; ++i)\n                  palette[i*4+3] = stbi__get8(s);\n            } else {\n               if (!(s->img_n & 1)) return stbi__err(\"tRNS with alpha\",\"Corrupt PNG\");\n               if (c.length != (stbi__uint32) s->img_n*2) return stbi__err(\"bad tRNS len\",\"Corrupt PNG\");\n               has_trans = 1;\n               for (k=0; k < s->img_n; ++k)\n                  tc[k] = (stbi_uc) (stbi__get16be(s) & 255) * stbi__depth_scale_table[depth]; // non 8-bit images will be larger\n            }\n            break;\n         }\n\n         case STBI__PNG_TYPE('I','D','A','T'): {\n            if (first) return stbi__err(\"first not IHDR\", \"Corrupt PNG\");\n            if (pal_img_n && !pal_len) return stbi__err(\"no PLTE\",\"Corrupt PNG\");\n            if (scan == STBI__SCAN_header) { s->img_n = pal_img_n; return 1; }\n            if ((int)(ioff + c.length) < (int)ioff) return 0;\n            if (ioff + c.length > idata_limit) {\n               stbi__uint32 idata_limit_old = idata_limit;\n               stbi_uc *p;\n               if (idata_limit == 0) idata_limit = c.length > 4096 ? c.length : 4096;\n               while (ioff + c.length > idata_limit)\n                  idata_limit *= 2;\n               STBI_NOTUSED(idata_limit_old);\n               p = (stbi_uc *) STBI_REALLOC_SIZED(z->idata, idata_limit_old, idata_limit); if (p == NULL) return stbi__err(\"outofmem\", \"Out of memory\");\n               z->idata = p;\n            }\n            if (!stbi__getn(s, z->idata+ioff,c.length)) return stbi__err(\"outofdata\",\"Corrupt PNG\");\n            ioff += c.length;\n            break;\n         }\n\n         case STBI__PNG_TYPE('I','E','N','D'): {\n            stbi__uint32 raw_len, bpl;\n            if (first) return stbi__err(\"first not IHDR\", \"Corrupt PNG\");\n            if (scan != STBI__SCAN_load) return 1;\n            if (z->idata == NULL) return stbi__err(\"no IDAT\",\"Corrupt PNG\");\n            // initial guess for decoded data size to avoid unnecessary reallocs\n            bpl = (s->img_x * depth + 7) / 8; // bytes per line, per component\n            raw_len = bpl * s->img_y * s->img_n /* pixels */ + s->img_y /* filter mode per row */;\n            z->expanded = (stbi_uc *) stbi_zlib_decode_malloc_guesssize_headerflag((char *) z->idata, ioff, raw_len, (int *) &raw_len, !is_iphone);\n            if (z->expanded == NULL) return 0; // zlib should set error\n            STBI_FREE(z->idata); z->idata = NULL;\n            if ((req_comp == s->img_n+1 && req_comp != 3 && !pal_img_n) || has_trans)\n               s->img_out_n = s->img_n+1;\n            else\n               s->img_out_n = s->img_n;\n            if (!stbi__create_png_image(z, z->expanded, raw_len, s->img_out_n, depth, color, interlace)) return 0;\n            if (has_trans)\n               if (!stbi__compute_transparency(z, tc, s->img_out_n)) return 0;\n            if (is_iphone && stbi__de_iphone_flag && s->img_out_n > 2)\n               stbi__de_iphone(z);\n            if (pal_img_n) {\n               // pal_img_n == 3 or 4\n               s->img_n = pal_img_n; // record the actual colors we had\n               s->img_out_n = pal_img_n;\n               if (req_comp >= 3) s->img_out_n = req_comp;\n               if (!stbi__expand_png_palette(z, palette, pal_len, s->img_out_n))\n                  return 0;\n            }\n            STBI_FREE(z->expanded); z->expanded = NULL;\n            return 1;\n         }\n\n         default:\n            // if critical, fail\n            if (first) return stbi__err(\"first not IHDR\", \"Corrupt PNG\");\n            if ((c.type & (1 << 29)) == 0) {\n               #ifndef STBI_NO_FAILURE_STRINGS\n               // not threadsafe\n               static char invalid_chunk[] = \"XXXX PNG chunk not known\";\n               invalid_chunk[0] = STBI__BYTECAST(c.type >> 24);\n               invalid_chunk[1] = STBI__BYTECAST(c.type >> 16);\n               invalid_chunk[2] = STBI__BYTECAST(c.type >>  8);\n               invalid_chunk[3] = STBI__BYTECAST(c.type >>  0);\n               #endif\n               return stbi__err(invalid_chunk, \"PNG not supported: unknown PNG chunk type\");\n            }\n            stbi__skip(s, c.length);\n            break;\n      }\n      // end of PNG chunk, read and skip CRC\n      stbi__get32be(s);\n   }\n}\n\nstatic unsigned char *stbi__do_png(stbi__png *p, int *x, int *y, int *n, int req_comp)\n{\n   unsigned char *result=NULL;\n   if (req_comp < 0 || req_comp > 4) return stbi__errpuc(\"bad req_comp\", \"Internal error\");\n   if (stbi__parse_png_file(p, STBI__SCAN_load, req_comp)) {\n      result = p->out;\n      p->out = NULL;\n      if (req_comp && req_comp != p->s->img_out_n) {\n         result = stbi__convert_format(result, p->s->img_out_n, req_comp, p->s->img_x, p->s->img_y);\n         p->s->img_out_n = req_comp;\n         if (result == NULL) return result;\n      }\n      *x = p->s->img_x;\n      *y = p->s->img_y;\n      if (n) *n = p->s->img_out_n;\n   }\n   STBI_FREE(p->out);      p->out      = NULL;\n   STBI_FREE(p->expanded); p->expanded = NULL;\n   STBI_FREE(p->idata);    p->idata    = NULL;\n\n   return result;\n}\n\nstatic unsigned char *stbi__png_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   stbi__png p;\n   p.s = s;\n   return stbi__do_png(&p, x,y,comp,req_comp);\n}\n\nstatic int stbi__png_test(stbi__context *s)\n{\n   int r;\n   r = stbi__check_png_header(s);\n   stbi__rewind(s);\n   return r;\n}\n\nstatic int stbi__png_info_raw(stbi__png *p, int *x, int *y, int *comp)\n{\n   if (!stbi__parse_png_file(p, STBI__SCAN_header, 0)) {\n      stbi__rewind( p->s );\n      return 0;\n   }\n   if (x) *x = p->s->img_x;\n   if (y) *y = p->s->img_y;\n   if (comp) *comp = p->s->img_n;\n   return 1;\n}\n\nstatic int stbi__png_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   stbi__png p;\n   p.s = s;\n   return stbi__png_info_raw(&p, x, y, comp);\n}\n#endif\n\n// Microsoft/Windows BMP image\n\n#ifndef STBI_NO_BMP\nstatic int stbi__bmp_test_raw(stbi__context *s)\n{\n   int r;\n   int sz;\n   if (stbi__get8(s) != 'B') return 0;\n   if (stbi__get8(s) != 'M') return 0;\n   stbi__get32le(s); // discard filesize\n   stbi__get16le(s); // discard reserved\n   stbi__get16le(s); // discard reserved\n   stbi__get32le(s); // discard data offset\n   sz = stbi__get32le(s);\n   r = (sz == 12 || sz == 40 || sz == 56 || sz == 108 || sz == 124);\n   return r;\n}\n\nstatic int stbi__bmp_test(stbi__context *s)\n{\n   int r = stbi__bmp_test_raw(s);\n   stbi__rewind(s);\n   return r;\n}\n\n\n// returns 0..31 for the highest set bit\nstatic int stbi__high_bit(unsigned int z)\n{\n   int n=0;\n   if (z == 0) return -1;\n   if (z >= 0x10000) n += 16, z >>= 16;\n   if (z >= 0x00100) n +=  8, z >>=  8;\n   if (z >= 0x00010) n +=  4, z >>=  4;\n   if (z >= 0x00004) n +=  2, z >>=  2;\n   if (z >= 0x00002) n +=  1, z >>=  1;\n   return n;\n}\n\nstatic int stbi__bitcount(unsigned int a)\n{\n   a = (a & 0x55555555) + ((a >>  1) & 0x55555555); // max 2\n   a = (a & 0x33333333) + ((a >>  2) & 0x33333333); // max 4\n   a = (a + (a >> 4)) & 0x0f0f0f0f; // max 8 per 4, now 8 bits\n   a = (a + (a >> 8)); // max 16 per 8 bits\n   a = (a + (a >> 16)); // max 32 per 8 bits\n   return a & 0xff;\n}\n\nstatic int stbi__shiftsigned(int v, int shift, int bits)\n{\n   int result;\n   int z=0;\n\n   if (shift < 0) v <<= -shift;\n   else v >>= shift;\n   result = v;\n\n   z = bits;\n   while (z < 8) {\n      result += v >> z;\n      z += bits;\n   }\n   return result;\n}\n\ntypedef struct\n{\n   int bpp, offset, hsz;\n   unsigned int mr,mg,mb,ma, all_a;\n} stbi__bmp_data;\n\nstatic void *stbi__bmp_parse_header(stbi__context *s, stbi__bmp_data *info)\n{\n   int hsz;\n   if (stbi__get8(s) != 'B' || stbi__get8(s) != 'M') return stbi__errpuc(\"not BMP\", \"Corrupt BMP\");\n   stbi__get32le(s); // discard filesize\n   stbi__get16le(s); // discard reserved\n   stbi__get16le(s); // discard reserved\n   info->offset = stbi__get32le(s);\n   info->hsz = hsz = stbi__get32le(s);\n   \n   if (hsz != 12 && hsz != 40 && hsz != 56 && hsz != 108 && hsz != 124) return stbi__errpuc(\"unknown BMP\", \"BMP type not supported: unknown\");\n   if (hsz == 12) {\n      s->img_x = stbi__get16le(s);\n      s->img_y = stbi__get16le(s);\n   } else {\n      s->img_x = stbi__get32le(s);\n      s->img_y = stbi__get32le(s);\n   }\n   if (stbi__get16le(s) != 1) return stbi__errpuc(\"bad BMP\", \"bad BMP\");\n   info->bpp = stbi__get16le(s);\n   if (info->bpp == 1) return stbi__errpuc(\"monochrome\", \"BMP type not supported: 1-bit\");\n   if (hsz != 12) {\n      int compress = stbi__get32le(s);\n      if (compress == 1 || compress == 2) return stbi__errpuc(\"BMP RLE\", \"BMP type not supported: RLE\");\n      stbi__get32le(s); // discard sizeof\n      stbi__get32le(s); // discard hres\n      stbi__get32le(s); // discard vres\n      stbi__get32le(s); // discard colorsused\n      stbi__get32le(s); // discard max important\n      if (hsz == 40 || hsz == 56) {\n         if (hsz == 56) {\n            stbi__get32le(s);\n            stbi__get32le(s);\n            stbi__get32le(s);\n            stbi__get32le(s);\n         }\n         if (info->bpp == 16 || info->bpp == 32) {\n            info->mr = info->mg = info->mb = 0;\n            if (compress == 0) {\n               if (info->bpp == 32) {\n                  info->mr = 0xffu << 16;\n                  info->mg = 0xffu <<  8;\n                  info->mb = 0xffu <<  0;\n                  info->ma = 0xffu << 24;\n                  info->all_a = 0; // if all_a is 0 at end, then we loaded alpha channel but it was all 0\n               } else {\n                  info->mr = 31u << 10;\n                  info->mg = 31u <<  5;\n                  info->mb = 31u <<  0;\n               }\n            } else if (compress == 3) {\n               info->mr = stbi__get32le(s);\n               info->mg = stbi__get32le(s);\n               info->mb = stbi__get32le(s);\n               // not documented, but generated by photoshop and handled by mspaint\n               if (info->mr == info->mg && info->mg == info->mb) {\n                  // ?!?!?\n                  return stbi__errpuc(\"bad BMP\", \"bad BMP\");\n               }\n            } else\n               return stbi__errpuc(\"bad BMP\", \"bad BMP\");\n         }\n      } else {\n         int i;\n         if (hsz != 108 && hsz != 124)\n            return stbi__errpuc(\"bad BMP\", \"bad BMP\");\n         info->mr = stbi__get32le(s);\n         info->mg = stbi__get32le(s);\n         info->mb = stbi__get32le(s);\n         info->ma = stbi__get32le(s);\n         stbi__get32le(s); // discard color space\n         for (i=0; i < 12; ++i)\n            stbi__get32le(s); // discard color space parameters\n         if (hsz == 124) {\n            stbi__get32le(s); // discard rendering intent\n            stbi__get32le(s); // discard offset of profile data\n            stbi__get32le(s); // discard size of profile data\n            stbi__get32le(s); // discard reserved\n         }\n      }\n   }\n   return (void *) 1;\n}\n\n\nstatic stbi_uc *stbi__bmp_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   stbi_uc *out;\n   unsigned int mr=0,mg=0,mb=0,ma=0, all_a;\n   stbi_uc pal[256][4];\n   int psize=0,i,j,width;\n   int flip_vertically, pad, target;\n   stbi__bmp_data info;\n\n   info.all_a = 255;   \n   if (stbi__bmp_parse_header(s, &info) == NULL)\n      return NULL; // error code already set\n\n   flip_vertically = ((int) s->img_y) > 0;\n   s->img_y = abs((int) s->img_y);\n\n   mr = info.mr;\n   mg = info.mg;\n   mb = info.mb;\n   ma = info.ma;\n   all_a = info.all_a;\n\n   if (info.hsz == 12) {\n      if (info.bpp < 24)\n         psize = (info.offset - 14 - 24) / 3;\n   } else {\n      if (info.bpp < 16)\n         psize = (info.offset - 14 - info.hsz) >> 2;\n   }\n\n   s->img_n = ma ? 4 : 3;\n   if (req_comp && req_comp >= 3) // we can directly decode 3 or 4\n      target = req_comp;\n   else\n      target = s->img_n; // if they want monochrome, we'll post-convert\n\n   out = (stbi_uc *) stbi__malloc(target * s->img_x * s->img_y);\n   if (!out) return stbi__errpuc(\"outofmem\", \"Out of memory\");\n   if (info.bpp < 16) {\n      int z=0;\n      if (psize == 0 || psize > 256) { STBI_FREE(out); return stbi__errpuc(\"invalid\", \"Corrupt BMP\"); }\n      for (i=0; i < psize; ++i) {\n         pal[i][2] = stbi__get8(s);\n         pal[i][1] = stbi__get8(s);\n         pal[i][0] = stbi__get8(s);\n         if (info.hsz != 12) stbi__get8(s);\n         pal[i][3] = 255;\n      }\n      stbi__skip(s, info.offset - 14 - info.hsz - psize * (info.hsz == 12 ? 3 : 4));\n      if (info.bpp == 4) width = (s->img_x + 1) >> 1;\n      else if (info.bpp == 8) width = s->img_x;\n      else { STBI_FREE(out); return stbi__errpuc(\"bad bpp\", \"Corrupt BMP\"); }\n      pad = (-width)&3;\n      for (j=0; j < (int) s->img_y; ++j) {\n         for (i=0; i < (int) s->img_x; i += 2) {\n            int v=stbi__get8(s),v2=0;\n            if (info.bpp == 4) {\n               v2 = v & 15;\n               v >>= 4;\n            }\n            out[z++] = pal[v][0];\n            out[z++] = pal[v][1];\n            out[z++] = pal[v][2];\n            if (target == 4) out[z++] = 255;\n            if (i+1 == (int) s->img_x) break;\n            v = (info.bpp == 8) ? stbi__get8(s) : v2;\n            out[z++] = pal[v][0];\n            out[z++] = pal[v][1];\n            out[z++] = pal[v][2];\n            if (target == 4) out[z++] = 255;\n         }\n         stbi__skip(s, pad);\n      }\n   } else {\n      int rshift=0,gshift=0,bshift=0,ashift=0,rcount=0,gcount=0,bcount=0,acount=0;\n      int z = 0;\n      int easy=0;\n      stbi__skip(s, info.offset - 14 - info.hsz);\n      if (info.bpp == 24) width = 3 * s->img_x;\n      else if (info.bpp == 16) width = 2*s->img_x;\n      else /* bpp = 32 and pad = 0 */ width=0;\n      pad = (-width) & 3;\n      if (info.bpp == 24) {\n         easy = 1;\n      } else if (info.bpp == 32) {\n         if (mb == 0xff && mg == 0xff00 && mr == 0x00ff0000 && ma == 0xff000000)\n            easy = 2;\n      }\n      if (!easy) {\n         if (!mr || !mg || !mb) { STBI_FREE(out); return stbi__errpuc(\"bad masks\", \"Corrupt BMP\"); }\n         // right shift amt to put high bit in position #7\n         rshift = stbi__high_bit(mr)-7; rcount = stbi__bitcount(mr);\n         gshift = stbi__high_bit(mg)-7; gcount = stbi__bitcount(mg);\n         bshift = stbi__high_bit(mb)-7; bcount = stbi__bitcount(mb);\n         ashift = stbi__high_bit(ma)-7; acount = stbi__bitcount(ma);\n      }\n      for (j=0; j < (int) s->img_y; ++j) {\n         if (easy) {\n            for (i=0; i < (int) s->img_x; ++i) {\n               unsigned char a;\n               out[z+2] = stbi__get8(s);\n               out[z+1] = stbi__get8(s);\n               out[z+0] = stbi__get8(s);\n               z += 3;\n               a = (easy == 2 ? stbi__get8(s) : 255);\n               all_a |= a;\n               if (target == 4) out[z++] = a;\n            }\n         } else {\n            int bpp = info.bpp;\n            for (i=0; i < (int) s->img_x; ++i) {\n               stbi__uint32 v = (bpp == 16 ? (stbi__uint32) stbi__get16le(s) : stbi__get32le(s));\n               int a;\n               out[z++] = STBI__BYTECAST(stbi__shiftsigned(v & mr, rshift, rcount));\n               out[z++] = STBI__BYTECAST(stbi__shiftsigned(v & mg, gshift, gcount));\n               out[z++] = STBI__BYTECAST(stbi__shiftsigned(v & mb, bshift, bcount));\n               a = (ma ? stbi__shiftsigned(v & ma, ashift, acount) : 255);\n               all_a |= a;\n               if (target == 4) out[z++] = STBI__BYTECAST(a);\n            }\n         }\n         stbi__skip(s, pad);\n      }\n   }\n   \n   // if alpha channel is all 0s, replace with all 255s\n   if (target == 4 && all_a == 0)\n      for (i=4*s->img_x*s->img_y-1; i >= 0; i -= 4)\n         out[i] = 255;\n\n   if (flip_vertically) {\n      stbi_uc t;\n      for (j=0; j < (int) s->img_y>>1; ++j) {\n         stbi_uc *p1 = out +      j     *s->img_x*target;\n         stbi_uc *p2 = out + (s->img_y-1-j)*s->img_x*target;\n         for (i=0; i < (int) s->img_x*target; ++i) {\n            t = p1[i], p1[i] = p2[i], p2[i] = t;\n         }\n      }\n   }\n\n   if (req_comp && req_comp != target) {\n      out = stbi__convert_format(out, target, req_comp, s->img_x, s->img_y);\n      if (out == NULL) return out; // stbi__convert_format frees input on failure\n   }\n\n   *x = s->img_x;\n   *y = s->img_y;\n   if (comp) *comp = s->img_n;\n   return out;\n}\n#endif\n\n// Targa Truevision - TGA\n// by Jonathan Dummer\n#ifndef STBI_NO_TGA\n// returns STBI_rgb or whatever, 0 on error\nstatic int stbi__tga_get_comp(int bits_per_pixel, int is_grey, int* is_rgb16)\n{\n   // only RGB or RGBA (incl. 16bit) or grey allowed\n   if(is_rgb16) *is_rgb16 = 0;\n   switch(bits_per_pixel) {\n      case 8:  return STBI_grey;\n      case 16: if(is_grey) return STBI_grey_alpha;\n            // else: fall-through\n      case 15: if(is_rgb16) *is_rgb16 = 1;\n            return STBI_rgb;\n      case 24: // fall-through\n      case 32: return bits_per_pixel/8;\n      default: return 0;\n   }\n}\n\nstatic int stbi__tga_info(stbi__context *s, int *x, int *y, int *comp)\n{\n    int tga_w, tga_h, tga_comp, tga_image_type, tga_bits_per_pixel, tga_colormap_bpp;\n    int sz, tga_colormap_type;\n    stbi__get8(s);                   // discard Offset\n    tga_colormap_type = stbi__get8(s); // colormap type\n    if( tga_colormap_type > 1 ) {\n        stbi__rewind(s);\n        return 0;      // only RGB or indexed allowed\n    }\n    tga_image_type = stbi__get8(s); // image type\n    if ( tga_colormap_type == 1 ) { // colormapped (paletted) image\n        if (tga_image_type != 1 && tga_image_type != 9) {\n            stbi__rewind(s);\n            return 0;\n        }\n        stbi__skip(s,4);       // skip index of first colormap entry and number of entries\n        sz = stbi__get8(s);    //   check bits per palette color entry\n        if ( (sz != 8) && (sz != 15) && (sz != 16) && (sz != 24) && (sz != 32) ) {\n            stbi__rewind(s);\n            return 0;\n        }\n        stbi__skip(s,4);       // skip image x and y origin\n        tga_colormap_bpp = sz;\n    } else { // \"normal\" image w/o colormap - only RGB or grey allowed, +/- RLE\n        if ( (tga_image_type != 2) && (tga_image_type != 3) && (tga_image_type != 10) && (tga_image_type != 11) ) {\n            stbi__rewind(s);\n            return 0; // only RGB or grey allowed, +/- RLE\n        }\n        stbi__skip(s,9); // skip colormap specification and image x/y origin\n        tga_colormap_bpp = 0;\n    }\n    tga_w = stbi__get16le(s);\n    if( tga_w < 1 ) {\n        stbi__rewind(s);\n        return 0;   // test width\n    }\n    tga_h = stbi__get16le(s);\n    if( tga_h < 1 ) {\n        stbi__rewind(s);\n        return 0;   // test height\n    }\n    tga_bits_per_pixel = stbi__get8(s); // bits per pixel\n    stbi__get8(s); // ignore alpha bits\n    if (tga_colormap_bpp != 0) {\n        if((tga_bits_per_pixel != 8) && (tga_bits_per_pixel != 16)) {\n            // when using a colormap, tga_bits_per_pixel is the size of the indexes\n            // I don't think anything but 8 or 16bit indexes makes sense\n            stbi__rewind(s);\n            return 0;\n        }\n        tga_comp = stbi__tga_get_comp(tga_colormap_bpp, 0, NULL);\n    } else {\n        tga_comp = stbi__tga_get_comp(tga_bits_per_pixel, (tga_image_type == 3) || (tga_image_type == 11), NULL);\n    }\n    if(!tga_comp) {\n      stbi__rewind(s);\n      return 0;\n    }\n    if (x) *x = tga_w;\n    if (y) *y = tga_h;\n    if (comp) *comp = tga_comp;\n    return 1;                   // seems to have passed everything\n}\n\nstatic int stbi__tga_test(stbi__context *s)\n{\n   int res = 0;\n   int sz, tga_color_type;\n   stbi__get8(s);      //   discard Offset\n   tga_color_type = stbi__get8(s);   //   color type\n   if ( tga_color_type > 1 ) goto errorEnd;   //   only RGB or indexed allowed\n   sz = stbi__get8(s);   //   image type\n   if ( tga_color_type == 1 ) { // colormapped (paletted) image\n      if (sz != 1 && sz != 9) goto errorEnd; // colortype 1 demands image type 1 or 9\n      stbi__skip(s,4);       // skip index of first colormap entry and number of entries\n      sz = stbi__get8(s);    //   check bits per palette color entry\n      if ( (sz != 8) && (sz != 15) && (sz != 16) && (sz != 24) && (sz != 32) ) goto errorEnd;\n      stbi__skip(s,4);       // skip image x and y origin\n   } else { // \"normal\" image w/o colormap\n      if ( (sz != 2) && (sz != 3) && (sz != 10) && (sz != 11) ) goto errorEnd; // only RGB or grey allowed, +/- RLE\n      stbi__skip(s,9); // skip colormap specification and image x/y origin\n   }\n   if ( stbi__get16le(s) < 1 ) goto errorEnd;      //   test width\n   if ( stbi__get16le(s) < 1 ) goto errorEnd;      //   test height\n   sz = stbi__get8(s);   //   bits per pixel\n   if ( (tga_color_type == 1) && (sz != 8) && (sz != 16) ) goto errorEnd; // for colormapped images, bpp is size of an index\n   if ( (sz != 8) && (sz != 15) && (sz != 16) && (sz != 24) && (sz != 32) ) goto errorEnd;\n\n   res = 1; // if we got this far, everything's good and we can return 1 instead of 0\n\nerrorEnd:\n   stbi__rewind(s);\n   return res;\n}\n\n// read 16bit value and convert to 24bit RGB\nvoid stbi__tga_read_rgb16(stbi__context *s, stbi_uc* out)\n{\n   stbi__uint16 px = stbi__get16le(s);\n   stbi__uint16 fiveBitMask = 31;\n   // we have 3 channels with 5bits each\n   int r = (px >> 10) & fiveBitMask;\n   int g = (px >> 5) & fiveBitMask;\n   int b = px & fiveBitMask;\n   // Note that this saves the data in RGB(A) order, so it doesn't need to be swapped later\n   out[0] = (r * 255)/31;\n   out[1] = (g * 255)/31;\n   out[2] = (b * 255)/31;\n\n   // some people claim that the most significant bit might be used for alpha\n   // (possibly if an alpha-bit is set in the \"image descriptor byte\")\n   // but that only made 16bit test images completely translucent..\n   // so let's treat all 15 and 16bit TGAs as RGB with no alpha.\n}\n\nstatic stbi_uc *stbi__tga_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   //   read in the TGA header stuff\n   int tga_offset = stbi__get8(s);\n   int tga_indexed = stbi__get8(s);\n   int tga_image_type = stbi__get8(s);\n   int tga_is_RLE = 0;\n   int tga_palette_start = stbi__get16le(s);\n   int tga_palette_len = stbi__get16le(s);\n   int tga_palette_bits = stbi__get8(s);\n   int tga_x_origin = stbi__get16le(s);\n   int tga_y_origin = stbi__get16le(s);\n   int tga_width = stbi__get16le(s);\n   int tga_height = stbi__get16le(s);\n   int tga_bits_per_pixel = stbi__get8(s);\n   int tga_comp, tga_rgb16=0;\n   int tga_inverted = stbi__get8(s);\n   // int tga_alpha_bits = tga_inverted & 15; // the 4 lowest bits - unused (useless?)\n   //   image data\n   unsigned char *tga_data;\n   unsigned char *tga_palette = NULL;\n   int i, j;\n   unsigned char raw_data[4];\n   int RLE_count = 0;\n   int RLE_repeating = 0;\n   int read_next_pixel = 1;\n\n   //   do a tiny bit of precessing\n   if ( tga_image_type >= 8 )\n   {\n      tga_image_type -= 8;\n      tga_is_RLE = 1;\n   }\n   tga_inverted = 1 - ((tga_inverted >> 5) & 1);\n\n   //   If I'm paletted, then I'll use the number of bits from the palette\n   if ( tga_indexed ) tga_comp = stbi__tga_get_comp(tga_palette_bits, 0, &tga_rgb16);\n   else tga_comp = stbi__tga_get_comp(tga_bits_per_pixel, (tga_image_type == 3), &tga_rgb16);\n\n   if(!tga_comp) // shouldn't really happen, stbi__tga_test() should have ensured basic consistency\n      return stbi__errpuc(\"bad format\", \"Can't find out TGA pixelformat\");\n\n   //   tga info\n   *x = tga_width;\n   *y = tga_height;\n   if (comp) *comp = tga_comp;\n\n   tga_data = (unsigned char*)stbi__malloc( (size_t)tga_width * tga_height * tga_comp );\n   if (!tga_data) return stbi__errpuc(\"outofmem\", \"Out of memory\");\n\n   // skip to the data's starting position (offset usually = 0)\n   stbi__skip(s, tga_offset );\n\n   if ( !tga_indexed && !tga_is_RLE && !tga_rgb16 ) {\n      for (i=0; i < tga_height; ++i) {\n         int row = tga_inverted ? tga_height -i - 1 : i;\n         stbi_uc *tga_row = tga_data + row*tga_width*tga_comp;\n         stbi__getn(s, tga_row, tga_width * tga_comp);\n      }\n   } else  {\n      //   do I need to load a palette?\n      if ( tga_indexed)\n      {\n         //   any data to skip? (offset usually = 0)\n         stbi__skip(s, tga_palette_start );\n         //   load the palette\n         tga_palette = (unsigned char*)stbi__malloc( tga_palette_len * tga_comp );\n         if (!tga_palette) {\n            STBI_FREE(tga_data);\n            return stbi__errpuc(\"outofmem\", \"Out of memory\");\n         }\n         if (tga_rgb16) {\n            stbi_uc *pal_entry = tga_palette;\n            STBI_ASSERT(tga_comp == STBI_rgb);\n            for (i=0; i < tga_palette_len; ++i) {\n               stbi__tga_read_rgb16(s, pal_entry);\n               pal_entry += tga_comp;\n            }\n         } else if (!stbi__getn(s, tga_palette, tga_palette_len * tga_comp)) {\n               STBI_FREE(tga_data);\n               STBI_FREE(tga_palette);\n               return stbi__errpuc(\"bad palette\", \"Corrupt TGA\");\n         }\n      }\n      //   load the data\n      for (i=0; i < tga_width * tga_height; ++i)\n      {\n         //   if I'm in RLE mode, do I need to get a RLE stbi__pngchunk?\n         if ( tga_is_RLE )\n         {\n            if ( RLE_count == 0 )\n            {\n               //   yep, get the next byte as a RLE command\n               int RLE_cmd = stbi__get8(s);\n               RLE_count = 1 + (RLE_cmd & 127);\n               RLE_repeating = RLE_cmd >> 7;\n               read_next_pixel = 1;\n            } else if ( !RLE_repeating )\n            {\n               read_next_pixel = 1;\n            }\n         } else\n         {\n            read_next_pixel = 1;\n         }\n         //   OK, if I need to read a pixel, do it now\n         if ( read_next_pixel )\n         {\n            //   load however much data we did have\n            if ( tga_indexed )\n            {\n               // read in index, then perform the lookup\n               int pal_idx = (tga_bits_per_pixel == 8) ? stbi__get8(s) : stbi__get16le(s);\n               if ( pal_idx >= tga_palette_len ) {\n                  // invalid index\n                  pal_idx = 0;\n               }\n               pal_idx *= tga_comp;\n               for (j = 0; j < tga_comp; ++j) {\n                  raw_data[j] = tga_palette[pal_idx+j];\n               }\n            } else if(tga_rgb16) {\n               STBI_ASSERT(tga_comp == STBI_rgb);\n               stbi__tga_read_rgb16(s, raw_data);\n            } else {\n               //   read in the data raw\n               for (j = 0; j < tga_comp; ++j) {\n                  raw_data[j] = stbi__get8(s);\n               }\n            }\n            //   clear the reading flag for the next pixel\n            read_next_pixel = 0;\n         } // end of reading a pixel\n\n         // copy data\n         for (j = 0; j < tga_comp; ++j)\n           tga_data[i*tga_comp+j] = raw_data[j];\n\n         //   in case we're in RLE mode, keep counting down\n         --RLE_count;\n      }\n      //   do I need to invert the image?\n      if ( tga_inverted )\n      {\n         for (j = 0; j*2 < tga_height; ++j)\n         {\n            int index1 = j * tga_width * tga_comp;\n            int index2 = (tga_height - 1 - j) * tga_width * tga_comp;\n            for (i = tga_width * tga_comp; i > 0; --i)\n            {\n               unsigned char temp = tga_data[index1];\n               tga_data[index1] = tga_data[index2];\n               tga_data[index2] = temp;\n               ++index1;\n               ++index2;\n            }\n         }\n      }\n      //   clear my palette, if I had one\n      if ( tga_palette != NULL )\n      {\n         STBI_FREE( tga_palette );\n      }\n   }\n\n   // swap RGB - if the source data was RGB16, it already is in the right order\n   if (tga_comp >= 3 && !tga_rgb16)\n   {\n      unsigned char* tga_pixel = tga_data;\n      for (i=0; i < tga_width * tga_height; ++i)\n      {\n         unsigned char temp = tga_pixel[0];\n         tga_pixel[0] = tga_pixel[2];\n         tga_pixel[2] = temp;\n         tga_pixel += tga_comp;\n      }\n   }\n\n   // convert to target component count\n   if (req_comp && req_comp != tga_comp)\n      tga_data = stbi__convert_format(tga_data, tga_comp, req_comp, tga_width, tga_height);\n\n   //   the things I do to get rid of an error message, and yet keep\n   //   Microsoft's C compilers happy... [8^(\n   tga_palette_start = tga_palette_len = tga_palette_bits =\n         tga_x_origin = tga_y_origin = 0;\n   //   OK, done\n   return tga_data;\n}\n#endif\n\n// *************************************************************************************************\n// Photoshop PSD loader -- PD by Thatcher Ulrich, integration by Nicolas Schulz, tweaked by STB\n\n#ifndef STBI_NO_PSD\nstatic int stbi__psd_test(stbi__context *s)\n{\n   int r = (stbi__get32be(s) == 0x38425053);\n   stbi__rewind(s);\n   return r;\n}\n\nstatic stbi_uc *stbi__psd_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   int   pixelCount;\n   int channelCount, compression;\n   int channel, i, count, len;\n   int bitdepth;\n   int w,h;\n   stbi_uc *out;\n\n   // Check identifier\n   if (stbi__get32be(s) != 0x38425053)   // \"8BPS\"\n      return stbi__errpuc(\"not PSD\", \"Corrupt PSD image\");\n\n   // Check file type version.\n   if (stbi__get16be(s) != 1)\n      return stbi__errpuc(\"wrong version\", \"Unsupported version of PSD image\");\n\n   // Skip 6 reserved bytes.\n   stbi__skip(s, 6 );\n\n   // Read the number of channels (R, G, B, A, etc).\n   channelCount = stbi__get16be(s);\n   if (channelCount < 0 || channelCount > 16)\n      return stbi__errpuc(\"wrong channel count\", \"Unsupported number of channels in PSD image\");\n\n   // Read the rows and columns of the image.\n   h = stbi__get32be(s);\n   w = stbi__get32be(s);\n\n   // Make sure the depth is 8 bits.\n   bitdepth = stbi__get16be(s);\n   if (bitdepth != 8 && bitdepth != 16)\n      return stbi__errpuc(\"unsupported bit depth\", \"PSD bit depth is not 8 or 16 bit\");\n\n   // Make sure the color mode is RGB.\n   // Valid options are:\n   //   0: Bitmap\n   //   1: Grayscale\n   //   2: Indexed color\n   //   3: RGB color\n   //   4: CMYK color\n   //   7: Multichannel\n   //   8: Duotone\n   //   9: Lab color\n   if (stbi__get16be(s) != 3)\n      return stbi__errpuc(\"wrong color format\", \"PSD is not in RGB color format\");\n\n   // Skip the Mode Data.  (It's the palette for indexed color; other info for other modes.)\n   stbi__skip(s,stbi__get32be(s) );\n\n   // Skip the image resources.  (resolution, pen tool paths, etc)\n   stbi__skip(s, stbi__get32be(s) );\n\n   // Skip the reserved data.\n   stbi__skip(s, stbi__get32be(s) );\n\n   // Find out if the data is compressed.\n   // Known values:\n   //   0: no compression\n   //   1: RLE compressed\n   compression = stbi__get16be(s);\n   if (compression > 1)\n      return stbi__errpuc(\"bad compression\", \"PSD has an unknown compression format\");\n\n   // Create the destination image.\n   out = (stbi_uc *) stbi__malloc(4 * w*h);\n   if (!out) return stbi__errpuc(\"outofmem\", \"Out of memory\");\n   pixelCount = w*h;\n\n   // Initialize the data to zero.\n   //memset( out, 0, pixelCount * 4 );\n\n   // Finally, the image data.\n   if (compression) {\n      // RLE as used by .PSD and .TIFF\n      // Loop until you get the number of unpacked bytes you are expecting:\n      //     Read the next source byte into n.\n      //     If n is between 0 and 127 inclusive, copy the next n+1 bytes literally.\n      //     Else if n is between -127 and -1 inclusive, copy the next byte -n+1 times.\n      //     Else if n is 128, noop.\n      // Endloop\n\n      // The RLE-compressed data is preceeded by a 2-byte data count for each row in the data,\n      // which we're going to just skip.\n      stbi__skip(s, h * channelCount * 2 );\n\n      // Read the RLE data by channel.\n      for (channel = 0; channel < 4; channel++) {\n         stbi_uc *p;\n\n         p = out+channel;\n         if (channel >= channelCount) {\n            // Fill this channel with default data.\n            for (i = 0; i < pixelCount; i++, p += 4)\n               *p = (channel == 3 ? 255 : 0);\n         } else {\n            // Read the RLE data.\n            count = 0;\n            while (count < pixelCount) {\n               len = stbi__get8(s);\n               if (len == 128) {\n                  // No-op.\n               } else if (len < 128) {\n                  // Copy next len+1 bytes literally.\n                  len++;\n                  count += len;\n                  while (len) {\n                     *p = stbi__get8(s);\n                     p += 4;\n                     len--;\n                  }\n               } else if (len > 128) {\n                  stbi_uc   val;\n                  // Next -len+1 bytes in the dest are replicated from next source byte.\n                  // (Interpret len as a negative 8-bit int.)\n                  len ^= 0x0FF;\n                  len += 2;\n                  val = stbi__get8(s);\n                  count += len;\n                  while (len) {\n                     *p = val;\n                     p += 4;\n                     len--;\n                  }\n               }\n            }\n         }\n      }\n\n   } else {\n      // We're at the raw image data.  It's each channel in order (Red, Green, Blue, Alpha, ...)\n      // where each channel consists of an 8-bit value for each pixel in the image.\n\n      // Read the data by channel.\n      for (channel = 0; channel < 4; channel++) {\n         stbi_uc *p;\n\n         p = out + channel;\n         if (channel >= channelCount) {\n            // Fill this channel with default data.\n            stbi_uc val = channel == 3 ? 255 : 0;\n            for (i = 0; i < pixelCount; i++, p += 4)\n               *p = val;\n         } else {\n            // Read the data.\n            if (bitdepth == 16) {\n               for (i = 0; i < pixelCount; i++, p += 4)\n                  *p = (stbi_uc) (stbi__get16be(s) >> 8);\n            } else {\n               for (i = 0; i < pixelCount; i++, p += 4)\n                  *p = stbi__get8(s);\n            }\n         }\n      }\n   }\n\n   if (req_comp && req_comp != 4) {\n      out = stbi__convert_format(out, 4, req_comp, w, h);\n      if (out == NULL) return out; // stbi__convert_format frees input on failure\n   }\n\n   if (comp) *comp = 4;\n   *y = h;\n   *x = w;\n\n   return out;\n}\n#endif\n\n// *************************************************************************************************\n// Softimage PIC loader\n// by Tom Seddon\n//\n// See http://softimage.wiki.softimage.com/index.php/INFO:_PIC_file_format\n// See http://ozviz.wasp.uwa.edu.au/~pbourke/dataformats/softimagepic/\n\n#ifndef STBI_NO_PIC\nstatic int stbi__pic_is4(stbi__context *s,const char *str)\n{\n   int i;\n   for (i=0; i<4; ++i)\n      if (stbi__get8(s) != (stbi_uc)str[i])\n         return 0;\n\n   return 1;\n}\n\nstatic int stbi__pic_test_core(stbi__context *s)\n{\n   int i;\n\n   if (!stbi__pic_is4(s,\"\\x53\\x80\\xF6\\x34\"))\n      return 0;\n\n   for(i=0;i<84;++i)\n      stbi__get8(s);\n\n   if (!stbi__pic_is4(s,\"PICT\"))\n      return 0;\n\n   return 1;\n}\n\ntypedef struct\n{\n   stbi_uc size,type,channel;\n} stbi__pic_packet;\n\nstatic stbi_uc *stbi__readval(stbi__context *s, int channel, stbi_uc *dest)\n{\n   int mask=0x80, i;\n\n   for (i=0; i<4; ++i, mask>>=1) {\n      if (channel & mask) {\n         if (stbi__at_eof(s)) return stbi__errpuc(\"bad file\",\"PIC file too short\");\n         dest[i]=stbi__get8(s);\n      }\n   }\n\n   return dest;\n}\n\nstatic void stbi__copyval(int channel,stbi_uc *dest,const stbi_uc *src)\n{\n   int mask=0x80,i;\n\n   for (i=0;i<4; ++i, mask>>=1)\n      if (channel&mask)\n         dest[i]=src[i];\n}\n\nstatic stbi_uc *stbi__pic_load_core(stbi__context *s,int width,int height,int *comp, stbi_uc *result)\n{\n   int act_comp=0,num_packets=0,y,chained;\n   stbi__pic_packet packets[10];\n\n   // this will (should...) cater for even some bizarre stuff like having data\n    // for the same channel in multiple packets.\n   do {\n      stbi__pic_packet *packet;\n\n      if (num_packets==sizeof(packets)/sizeof(packets[0]))\n         return stbi__errpuc(\"bad format\",\"too many packets\");\n\n      packet = &packets[num_packets++];\n\n      chained = stbi__get8(s);\n      packet->size    = stbi__get8(s);\n      packet->type    = stbi__get8(s);\n      packet->channel = stbi__get8(s);\n\n      act_comp |= packet->channel;\n\n      if (stbi__at_eof(s))          return stbi__errpuc(\"bad file\",\"file too short (reading packets)\");\n      if (packet->size != 8)  return stbi__errpuc(\"bad format\",\"packet isn't 8bpp\");\n   } while (chained);\n\n   *comp = (act_comp & 0x10 ? 4 : 3); // has alpha channel?\n\n   for(y=0; y<height; ++y) {\n      int packet_idx;\n\n      for(packet_idx=0; packet_idx < num_packets; ++packet_idx) {\n         stbi__pic_packet *packet = &packets[packet_idx];\n         stbi_uc *dest = result+y*width*4;\n\n         switch (packet->type) {\n            default:\n               return stbi__errpuc(\"bad format\",\"packet has bad compression type\");\n\n            case 0: {//uncompressed\n               int x;\n\n               for(x=0;x<width;++x, dest+=4)\n                  if (!stbi__readval(s,packet->channel,dest))\n                     return 0;\n               break;\n            }\n\n            case 1://Pure RLE\n               {\n                  int left=width, i;\n\n                  while (left>0) {\n                     stbi_uc count,value[4];\n\n                     count=stbi__get8(s);\n                     if (stbi__at_eof(s))   return stbi__errpuc(\"bad file\",\"file too short (pure read count)\");\n\n                     if (count > left)\n                        count = (stbi_uc) left;\n\n                     if (!stbi__readval(s,packet->channel,value))  return 0;\n\n                     for(i=0; i<count; ++i,dest+=4)\n                        stbi__copyval(packet->channel,dest,value);\n                     left -= count;\n                  }\n               }\n               break;\n\n            case 2: {//Mixed RLE\n               int left=width;\n               while (left>0) {\n                  int count = stbi__get8(s), i;\n                  if (stbi__at_eof(s))  return stbi__errpuc(\"bad file\",\"file too short (mixed read count)\");\n\n                  if (count >= 128) { // Repeated\n                     stbi_uc value[4];\n\n                     if (count==128)\n                        count = stbi__get16be(s);\n                     else\n                        count -= 127;\n                     if (count > left)\n                        return stbi__errpuc(\"bad file\",\"scanline overrun\");\n\n                     if (!stbi__readval(s,packet->channel,value))\n                        return 0;\n\n                     for(i=0;i<count;++i, dest += 4)\n                        stbi__copyval(packet->channel,dest,value);\n                  } else { // Raw\n                     ++count;\n                     if (count>left) return stbi__errpuc(\"bad file\",\"scanline overrun\");\n\n                     for(i=0;i<count;++i, dest+=4)\n                        if (!stbi__readval(s,packet->channel,dest))\n                           return 0;\n                  }\n                  left-=count;\n               }\n               break;\n            }\n         }\n      }\n   }\n\n   return result;\n}\n\nstatic stbi_uc *stbi__pic_load(stbi__context *s,int *px,int *py,int *comp,int req_comp)\n{\n   stbi_uc *result;\n   int i, x,y;\n\n   for (i=0; i<92; ++i)\n      stbi__get8(s);\n\n   x = stbi__get16be(s);\n   y = stbi__get16be(s);\n   if (stbi__at_eof(s))  return stbi__errpuc(\"bad file\",\"file too short (pic header)\");\n   if ((1 << 28) / x < y) return stbi__errpuc(\"too large\", \"Image too large to decode\");\n\n   stbi__get32be(s); //skip `ratio'\n   stbi__get16be(s); //skip `fields'\n   stbi__get16be(s); //skip `pad'\n\n   // intermediate buffer is RGBA\n   result = (stbi_uc *) stbi__malloc(x*y*4);\n   memset(result, 0xff, x*y*4);\n\n   if (!stbi__pic_load_core(s,x,y,comp, result)) {\n      STBI_FREE(result);\n      result=0;\n   }\n   *px = x;\n   *py = y;\n   if (req_comp == 0) req_comp = *comp;\n   result=stbi__convert_format(result,4,req_comp,x,y);\n\n   return result;\n}\n\nstatic int stbi__pic_test(stbi__context *s)\n{\n   int r = stbi__pic_test_core(s);\n   stbi__rewind(s);\n   return r;\n}\n#endif\n\n// *************************************************************************************************\n// GIF loader -- public domain by Jean-Marc Lienher -- simplified/shrunk by stb\n\n#ifndef STBI_NO_GIF\ntypedef struct\n{\n   stbi__int16 prefix;\n   stbi_uc first;\n   stbi_uc suffix;\n} stbi__gif_lzw;\n\ntypedef struct\n{\n   int w,h;\n   stbi_uc *out, *old_out;             // output buffer (always 4 components)\n   int flags, bgindex, ratio, transparent, eflags, delay;\n   stbi_uc  pal[256][4];\n   stbi_uc lpal[256][4];\n   stbi__gif_lzw codes[4096];\n   stbi_uc *color_table;\n   int parse, step;\n   int lflags;\n   int start_x, start_y;\n   int max_x, max_y;\n   int cur_x, cur_y;\n   int line_size;\n} stbi__gif;\n\nstatic int stbi__gif_test_raw(stbi__context *s)\n{\n   int sz;\n   if (stbi__get8(s) != 'G' || stbi__get8(s) != 'I' || stbi__get8(s) != 'F' || stbi__get8(s) != '8') return 0;\n   sz = stbi__get8(s);\n   if (sz != '9' && sz != '7') return 0;\n   if (stbi__get8(s) != 'a') return 0;\n   return 1;\n}\n\nstatic int stbi__gif_test(stbi__context *s)\n{\n   int r = stbi__gif_test_raw(s);\n   stbi__rewind(s);\n   return r;\n}\n\nstatic void stbi__gif_parse_colortable(stbi__context *s, stbi_uc pal[256][4], int num_entries, int transp)\n{\n   int i;\n   for (i=0; i < num_entries; ++i) {\n      pal[i][2] = stbi__get8(s);\n      pal[i][1] = stbi__get8(s);\n      pal[i][0] = stbi__get8(s);\n      pal[i][3] = transp == i ? 0 : 255;\n   }\n}\n\nstatic int stbi__gif_header(stbi__context *s, stbi__gif *g, int *comp, int is_info)\n{\n   stbi_uc version;\n   if (stbi__get8(s) != 'G' || stbi__get8(s) != 'I' || stbi__get8(s) != 'F' || stbi__get8(s) != '8')\n      return stbi__err(\"not GIF\", \"Corrupt GIF\");\n\n   version = stbi__get8(s);\n   if (version != '7' && version != '9')    return stbi__err(\"not GIF\", \"Corrupt GIF\");\n   if (stbi__get8(s) != 'a')                return stbi__err(\"not GIF\", \"Corrupt GIF\");\n\n   stbi__g_failure_reason = \"\";\n   g->w = stbi__get16le(s);\n   g->h = stbi__get16le(s);\n   g->flags = stbi__get8(s);\n   g->bgindex = stbi__get8(s);\n   g->ratio = stbi__get8(s);\n   g->transparent = -1;\n\n   if (comp != 0) *comp = 4;  // can't actually tell whether it's 3 or 4 until we parse the comments\n\n   if (is_info) return 1;\n\n   if (g->flags & 0x80)\n      stbi__gif_parse_colortable(s,g->pal, 2 << (g->flags & 7), -1);\n\n   return 1;\n}\n\nstatic int stbi__gif_info_raw(stbi__context *s, int *x, int *y, int *comp)\n{\n   stbi__gif g;\n   if (!stbi__gif_header(s, &g, comp, 1)) {\n      stbi__rewind( s );\n      return 0;\n   }\n   if (x) *x = g.w;\n   if (y) *y = g.h;\n   return 1;\n}\n\nstatic void stbi__out_gif_code(stbi__gif *g, stbi__uint16 code)\n{\n   stbi_uc *p, *c;\n\n   // recurse to decode the prefixes, since the linked-list is backwards,\n   // and working backwards through an interleaved image would be nasty\n   if (g->codes[code].prefix >= 0)\n      stbi__out_gif_code(g, g->codes[code].prefix);\n\n   if (g->cur_y >= g->max_y) return;\n\n   p = &g->out[g->cur_x + g->cur_y];\n   c = &g->color_table[g->codes[code].suffix * 4];\n\n   if (c[3] >= 128) {\n      p[0] = c[2];\n      p[1] = c[1];\n      p[2] = c[0];\n      p[3] = c[3];\n   }\n   g->cur_x += 4;\n\n   if (g->cur_x >= g->max_x) {\n      g->cur_x = g->start_x;\n      g->cur_y += g->step;\n\n      while (g->cur_y >= g->max_y && g->parse > 0) {\n         g->step = (1 << g->parse) * g->line_size;\n         g->cur_y = g->start_y + (g->step >> 1);\n         --g->parse;\n      }\n   }\n}\n\nstatic stbi_uc *stbi__process_gif_raster(stbi__context *s, stbi__gif *g)\n{\n   stbi_uc lzw_cs;\n   stbi__int32 len, init_code;\n   stbi__uint32 first;\n   stbi__int32 codesize, codemask, avail, oldcode, bits, valid_bits, clear;\n   stbi__gif_lzw *p;\n\n   lzw_cs = stbi__get8(s);\n   if (lzw_cs > 12) return NULL;\n   clear = 1 << lzw_cs;\n   first = 1;\n   codesize = lzw_cs + 1;\n   codemask = (1 << codesize) - 1;\n   bits = 0;\n   valid_bits = 0;\n   for (init_code = 0; init_code < clear; init_code++) {\n      g->codes[init_code].prefix = -1;\n      g->codes[init_code].first = (stbi_uc) init_code;\n      g->codes[init_code].suffix = (stbi_uc) init_code;\n   }\n\n   // support no starting clear code\n   avail = clear+2;\n   oldcode = -1;\n\n   len = 0;\n   for(;;) {\n      if (valid_bits < codesize) {\n         if (len == 0) {\n            len = stbi__get8(s); // start new block\n            if (len == 0)\n               return g->out;\n         }\n         --len;\n         bits |= (stbi__int32) stbi__get8(s) << valid_bits;\n         valid_bits += 8;\n      } else {\n         stbi__int32 code = bits & codemask;\n         bits >>= codesize;\n         valid_bits -= codesize;\n         // @OPTIMIZE: is there some way we can accelerate the non-clear path?\n         if (code == clear) {  // clear code\n            codesize = lzw_cs + 1;\n            codemask = (1 << codesize) - 1;\n            avail = clear + 2;\n            oldcode = -1;\n            first = 0;\n         } else if (code == clear + 1) { // end of stream code\n            stbi__skip(s, len);\n            while ((len = stbi__get8(s)) > 0)\n               stbi__skip(s,len);\n            return g->out;\n         } else if (code <= avail) {\n            if (first) return stbi__errpuc(\"no clear code\", \"Corrupt GIF\");\n\n            if (oldcode >= 0) {\n               p = &g->codes[avail++];\n               if (avail > 4096)        return stbi__errpuc(\"too many codes\", \"Corrupt GIF\");\n               p->prefix = (stbi__int16) oldcode;\n               p->first = g->codes[oldcode].first;\n               p->suffix = (code == avail) ? p->first : g->codes[code].first;\n            } else if (code == avail)\n               return stbi__errpuc(\"illegal code in raster\", \"Corrupt GIF\");\n\n            stbi__out_gif_code(g, (stbi__uint16) code);\n\n            if ((avail & codemask) == 0 && avail <= 0x0FFF) {\n               codesize++;\n               codemask = (1 << codesize) - 1;\n            }\n\n            oldcode = code;\n         } else {\n            return stbi__errpuc(\"illegal code in raster\", \"Corrupt GIF\");\n         }\n      }\n   }\n}\n\nstatic void stbi__fill_gif_background(stbi__gif *g, int x0, int y0, int x1, int y1)\n{\n   int x, y;\n   stbi_uc *c = g->pal[g->bgindex];\n   for (y = y0; y < y1; y += 4 * g->w) {\n      for (x = x0; x < x1; x += 4) {\n         stbi_uc *p  = &g->out[y + x];\n         p[0] = c[2];\n         p[1] = c[1];\n         p[2] = c[0];\n         p[3] = 0;\n      }\n   }\n}\n\n// this function is designed to support animated gifs, although stb_image doesn't support it\nstatic stbi_uc *stbi__gif_load_next(stbi__context *s, stbi__gif *g, int *comp, int req_comp)\n{\n   int i;\n   stbi_uc *prev_out = 0;\n\n   if (g->out == 0 && !stbi__gif_header(s, g, comp,0))\n      return 0; // stbi__g_failure_reason set by stbi__gif_header\n\n   prev_out = g->out;\n   g->out = (stbi_uc *) stbi__malloc(4 * g->w * g->h);\n   if (g->out == 0) return stbi__errpuc(\"outofmem\", \"Out of memory\");\n\n   switch ((g->eflags & 0x1C) >> 2) {\n      case 0: // unspecified (also always used on 1st frame)\n         stbi__fill_gif_background(g, 0, 0, 4 * g->w, 4 * g->w * g->h);\n         break;\n      case 1: // do not dispose\n         if (prev_out) memcpy(g->out, prev_out, 4 * g->w * g->h);\n         g->old_out = prev_out;\n         break;\n      case 2: // dispose to background\n         if (prev_out) memcpy(g->out, prev_out, 4 * g->w * g->h);\n         stbi__fill_gif_background(g, g->start_x, g->start_y, g->max_x, g->max_y);\n         break;\n      case 3: // dispose to previous\n         if (g->old_out) {\n            for (i = g->start_y; i < g->max_y; i += 4 * g->w)\n               memcpy(&g->out[i + g->start_x], &g->old_out[i + g->start_x], g->max_x - g->start_x);\n         }\n         break;\n   }\n\n   for (;;) {\n      switch (stbi__get8(s)) {\n         case 0x2C: /* Image Descriptor */\n         {\n            int prev_trans = -1;\n            stbi__int32 x, y, w, h;\n            stbi_uc *o;\n\n            x = stbi__get16le(s);\n            y = stbi__get16le(s);\n            w = stbi__get16le(s);\n            h = stbi__get16le(s);\n            if (((x + w) > (g->w)) || ((y + h) > (g->h)))\n               return stbi__errpuc(\"bad Image Descriptor\", \"Corrupt GIF\");\n\n            g->line_size = g->w * 4;\n            g->start_x = x * 4;\n            g->start_y = y * g->line_size;\n            g->max_x   = g->start_x + w * 4;\n            g->max_y   = g->start_y + h * g->line_size;\n            g->cur_x   = g->start_x;\n            g->cur_y   = g->start_y;\n\n            g->lflags = stbi__get8(s);\n\n            if (g->lflags & 0x40) {\n               g->step = 8 * g->line_size; // first interlaced spacing\n               g->parse = 3;\n            } else {\n               g->step = g->line_size;\n               g->parse = 0;\n            }\n\n            if (g->lflags & 0x80) {\n               stbi__gif_parse_colortable(s,g->lpal, 2 << (g->lflags & 7), g->eflags & 0x01 ? g->transparent : -1);\n               g->color_table = (stbi_uc *) g->lpal;\n            } else if (g->flags & 0x80) {\n               if (g->transparent >= 0 && (g->eflags & 0x01)) {\n                  prev_trans = g->pal[g->transparent][3];\n                  g->pal[g->transparent][3] = 0;\n               }\n               g->color_table = (stbi_uc *) g->pal;\n            } else\n               return stbi__errpuc(\"missing color table\", \"Corrupt GIF\");\n\n            o = stbi__process_gif_raster(s, g);\n            if (o == NULL) return NULL;\n\n            if (prev_trans != -1)\n               g->pal[g->transparent][3] = (stbi_uc) prev_trans;\n\n            return o;\n         }\n\n         case 0x21: // Comment Extension.\n         {\n            int len;\n            if (stbi__get8(s) == 0xF9) { // Graphic Control Extension.\n               len = stbi__get8(s);\n               if (len == 4) {\n                  g->eflags = stbi__get8(s);\n                  g->delay = stbi__get16le(s);\n                  g->transparent = stbi__get8(s);\n               } else {\n                  stbi__skip(s, len);\n                  break;\n               }\n            }\n            while ((len = stbi__get8(s)) != 0)\n               stbi__skip(s, len);\n            break;\n         }\n\n         case 0x3B: // gif stream termination code\n            return (stbi_uc *) s; // using '1' causes warning on some compilers\n\n         default:\n            return stbi__errpuc(\"unknown code\", \"Corrupt GIF\");\n      }\n   }\n\n   STBI_NOTUSED(req_comp);\n}\n\nstatic stbi_uc *stbi__gif_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   stbi_uc *u = 0;\n   stbi__gif g;\n   memset(&g, 0, sizeof(g));\n\n   u = stbi__gif_load_next(s, &g, comp, req_comp);\n   if (u == (stbi_uc *) s) u = 0;  // end of animated gif marker\n   if (u) {\n      *x = g.w;\n      *y = g.h;\n      if (req_comp && req_comp != 4)\n         u = stbi__convert_format(u, 4, req_comp, g.w, g.h);\n   }\n   else if (g.out)\n      STBI_FREE(g.out);\n\n   return u;\n}\n\nstatic int stbi__gif_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   return stbi__gif_info_raw(s,x,y,comp);\n}\n#endif\n\n// *************************************************************************************************\n// Radiance RGBE HDR loader\n// originally by Nicolas Schulz\n#ifndef STBI_NO_HDR\nstatic int stbi__hdr_test_core(stbi__context *s)\n{\n   const char *signature = \"#?RADIANCE\\n\";\n   int i;\n   for (i=0; signature[i]; ++i)\n      if (stbi__get8(s) != signature[i])\n         return 0;\n   return 1;\n}\n\nstatic int stbi__hdr_test(stbi__context* s)\n{\n   int r = stbi__hdr_test_core(s);\n   stbi__rewind(s);\n   return r;\n}\n\n#define STBI__HDR_BUFLEN  1024\nstatic char *stbi__hdr_gettoken(stbi__context *z, char *buffer)\n{\n   int len=0;\n   char c = '\\0';\n\n   c = (char) stbi__get8(z);\n\n   while (!stbi__at_eof(z) && c != '\\n') {\n      buffer[len++] = c;\n      if (len == STBI__HDR_BUFLEN-1) {\n         // flush to end of line\n         while (!stbi__at_eof(z) && stbi__get8(z) != '\\n')\n            ;\n         break;\n      }\n      c = (char) stbi__get8(z);\n   }\n\n   buffer[len] = 0;\n   return buffer;\n}\n\nstatic void stbi__hdr_convert(float *output, stbi_uc *input, int req_comp)\n{\n   if ( input[3] != 0 ) {\n      float f1;\n      // Exponent\n      f1 = (float) ldexp(1.0f, input[3] - (int)(128 + 8));\n      if (req_comp <= 2)\n         output[0] = (input[0] + input[1] + input[2]) * f1 / 3;\n      else {\n         output[0] = input[0] * f1;\n         output[1] = input[1] * f1;\n         output[2] = input[2] * f1;\n      }\n      if (req_comp == 2) output[1] = 1;\n      if (req_comp == 4) output[3] = 1;\n   } else {\n      switch (req_comp) {\n         case 4: output[3] = 1; /* fallthrough */\n         case 3: output[0] = output[1] = output[2] = 0;\n                 break;\n         case 2: output[1] = 1; /* fallthrough */\n         case 1: output[0] = 0;\n                 break;\n      }\n   }\n}\n\nstatic float *stbi__hdr_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   char buffer[STBI__HDR_BUFLEN];\n   char *token;\n   int valid = 0;\n   int width, height;\n   stbi_uc *scanline;\n   float *hdr_data;\n   int len;\n   unsigned char count, value;\n   int i, j, k, c1,c2, z;\n\n\n   // Check identifier\n   if (strcmp(stbi__hdr_gettoken(s,buffer), \"#?RADIANCE\") != 0)\n      return stbi__errpf(\"not HDR\", \"Corrupt HDR image\");\n\n   // Parse header\n   for(;;) {\n      token = stbi__hdr_gettoken(s,buffer);\n      if (token[0] == 0) break;\n      if (strcmp(token, \"FORMAT=32-bit_rle_rgbe\") == 0) valid = 1;\n   }\n\n   if (!valid)    return stbi__errpf(\"unsupported format\", \"Unsupported HDR format\");\n\n   // Parse width and height\n   // can't use sscanf() if we're not using stdio!\n   token = stbi__hdr_gettoken(s,buffer);\n   if (strncmp(token, \"-Y \", 3))  return stbi__errpf(\"unsupported data layout\", \"Unsupported HDR format\");\n   token += 3;\n   height = (int) strtol(token, &token, 10);\n   while (*token == ' ') ++token;\n   if (strncmp(token, \"+X \", 3))  return stbi__errpf(\"unsupported data layout\", \"Unsupported HDR format\");\n   token += 3;\n   width = (int) strtol(token, NULL, 10);\n\n   *x = width;\n   *y = height;\n\n   if (comp) *comp = 3;\n   if (req_comp == 0) req_comp = 3;\n\n   // Read data\n   hdr_data = (float *) stbi__malloc(height * width * req_comp * sizeof(float));\n\n   // Load image data\n   // image data is stored as some number of sca\n   if ( width < 8 || width >= 32768) {\n      // Read flat data\n      for (j=0; j < height; ++j) {\n         for (i=0; i < width; ++i) {\n            stbi_uc rgbe[4];\n           main_decode_loop:\n            stbi__getn(s, rgbe, 4);\n            stbi__hdr_convert(hdr_data + j * width * req_comp + i * req_comp, rgbe, req_comp);\n         }\n      }\n   } else {\n      // Read RLE-encoded data\n      scanline = NULL;\n\n      for (j = 0; j < height; ++j) {\n         c1 = stbi__get8(s);\n         c2 = stbi__get8(s);\n         len = stbi__get8(s);\n         if (c1 != 2 || c2 != 2 || (len & 0x80)) {\n            // not run-length encoded, so we have to actually use THIS data as a decoded\n            // pixel (note this can't be a valid pixel--one of RGB must be >= 128)\n            stbi_uc rgbe[4];\n            rgbe[0] = (stbi_uc) c1;\n            rgbe[1] = (stbi_uc) c2;\n            rgbe[2] = (stbi_uc) len;\n            rgbe[3] = (stbi_uc) stbi__get8(s);\n            stbi__hdr_convert(hdr_data, rgbe, req_comp);\n            i = 1;\n            j = 0;\n            STBI_FREE(scanline);\n            goto main_decode_loop; // yes, this makes no sense\n         }\n         len <<= 8;\n         len |= stbi__get8(s);\n         if (len != width) { STBI_FREE(hdr_data); STBI_FREE(scanline); return stbi__errpf(\"invalid decoded scanline length\", \"corrupt HDR\"); }\n         if (scanline == NULL) scanline = (stbi_uc *) stbi__malloc(width * 4);\n\n         for (k = 0; k < 4; ++k) {\n            i = 0;\n            while (i < width) {\n               count = stbi__get8(s);\n               if (count > 128) {\n                  // Run\n                  value = stbi__get8(s);\n                  count -= 128;\n                  for (z = 0; z < count; ++z)\n                     scanline[i++ * 4 + k] = value;\n               } else {\n                  // Dump\n                  for (z = 0; z < count; ++z)\n                     scanline[i++ * 4 + k] = stbi__get8(s);\n               }\n            }\n         }\n         for (i=0; i < width; ++i)\n            stbi__hdr_convert(hdr_data+(j*width + i)*req_comp, scanline + i*4, req_comp);\n      }\n      STBI_FREE(scanline);\n   }\n\n   return hdr_data;\n}\n\nstatic int stbi__hdr_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   char buffer[STBI__HDR_BUFLEN];\n   char *token;\n   int valid = 0;\n\n   if (stbi__hdr_test(s) == 0) {\n       stbi__rewind( s );\n       return 0;\n   }\n\n   for(;;) {\n      token = stbi__hdr_gettoken(s,buffer);\n      if (token[0] == 0) break;\n      if (strcmp(token, \"FORMAT=32-bit_rle_rgbe\") == 0) valid = 1;\n   }\n\n   if (!valid) {\n       stbi__rewind( s );\n       return 0;\n   }\n   token = stbi__hdr_gettoken(s,buffer);\n   if (strncmp(token, \"-Y \", 3)) {\n       stbi__rewind( s );\n       return 0;\n   }\n   token += 3;\n   *y = (int) strtol(token, &token, 10);\n   while (*token == ' ') ++token;\n   if (strncmp(token, \"+X \", 3)) {\n       stbi__rewind( s );\n       return 0;\n   }\n   token += 3;\n   *x = (int) strtol(token, NULL, 10);\n   *comp = 3;\n   return 1;\n}\n#endif // STBI_NO_HDR\n\n#ifndef STBI_NO_BMP\nstatic int stbi__bmp_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   void *p;\n   stbi__bmp_data info;\n\n   info.all_a = 255;   \n   p = stbi__bmp_parse_header(s, &info);\n   stbi__rewind( s );\n   if (p == NULL)\n      return 0;\n   *x = s->img_x;\n   *y = s->img_y;\n   *comp = info.ma ? 4 : 3;\n   return 1;\n}\n#endif\n\n#ifndef STBI_NO_PSD\nstatic int stbi__psd_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   int channelCount;\n   if (stbi__get32be(s) != 0x38425053) {\n       stbi__rewind( s );\n       return 0;\n   }\n   if (stbi__get16be(s) != 1) {\n       stbi__rewind( s );\n       return 0;\n   }\n   stbi__skip(s, 6);\n   channelCount = stbi__get16be(s);\n   if (channelCount < 0 || channelCount > 16) {\n       stbi__rewind( s );\n       return 0;\n   }\n   *y = stbi__get32be(s);\n   *x = stbi__get32be(s);\n   if (stbi__get16be(s) != 8) {\n       stbi__rewind( s );\n       return 0;\n   }\n   if (stbi__get16be(s) != 3) {\n       stbi__rewind( s );\n       return 0;\n   }\n   *comp = 4;\n   return 1;\n}\n#endif\n\n#ifndef STBI_NO_PIC\nstatic int stbi__pic_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   int act_comp=0,num_packets=0,chained;\n   stbi__pic_packet packets[10];\n\n   if (!stbi__pic_is4(s,\"\\x53\\x80\\xF6\\x34\")) {\n      stbi__rewind(s);\n      return 0;\n   }\n\n   stbi__skip(s, 88);\n\n   *x = stbi__get16be(s);\n   *y = stbi__get16be(s);\n   if (stbi__at_eof(s)) {\n      stbi__rewind( s);\n      return 0;\n   }\n   if ( (*x) != 0 && (1 << 28) / (*x) < (*y)) {\n      stbi__rewind( s );\n      return 0;\n   }\n\n   stbi__skip(s, 8);\n\n   do {\n      stbi__pic_packet *packet;\n\n      if (num_packets==sizeof(packets)/sizeof(packets[0]))\n         return 0;\n\n      packet = &packets[num_packets++];\n      chained = stbi__get8(s);\n      packet->size    = stbi__get8(s);\n      packet->type    = stbi__get8(s);\n      packet->channel = stbi__get8(s);\n      act_comp |= packet->channel;\n\n      if (stbi__at_eof(s)) {\n          stbi__rewind( s );\n          return 0;\n      }\n      if (packet->size != 8) {\n          stbi__rewind( s );\n          return 0;\n      }\n   } while (chained);\n\n   *comp = (act_comp & 0x10 ? 4 : 3);\n\n   return 1;\n}\n#endif\n\n// *************************************************************************************************\n// Portable Gray Map and Portable Pixel Map loader\n// by Ken Miller\n//\n// PGM: http://netpbm.sourceforge.net/doc/pgm.html\n// PPM: http://netpbm.sourceforge.net/doc/ppm.html\n//\n// Known limitations:\n//    Does not support comments in the header section\n//    Does not support ASCII image data (formats P2 and P3)\n//    Does not support 16-bit-per-channel\n\n#ifndef STBI_NO_PNM\n\nstatic int      stbi__pnm_test(stbi__context *s)\n{\n   char p, t;\n   p = (char) stbi__get8(s);\n   t = (char) stbi__get8(s);\n   if (p != 'P' || (t != '5' && t != '6')) {\n       stbi__rewind( s );\n       return 0;\n   }\n   return 1;\n}\n\nstatic stbi_uc *stbi__pnm_load(stbi__context *s, int *x, int *y, int *comp, int req_comp)\n{\n   stbi_uc *out;\n   if (!stbi__pnm_info(s, (int *)&s->img_x, (int *)&s->img_y, (int *)&s->img_n))\n      return 0;\n   *x = s->img_x;\n   *y = s->img_y;\n   *comp = s->img_n;\n\n   out = (stbi_uc *) stbi__malloc(s->img_n * s->img_x * s->img_y);\n   if (!out) return stbi__errpuc(\"outofmem\", \"Out of memory\");\n   stbi__getn(s, out, s->img_n * s->img_x * s->img_y);\n\n   if (req_comp && req_comp != s->img_n) {\n      out = stbi__convert_format(out, s->img_n, req_comp, s->img_x, s->img_y);\n      if (out == NULL) return out; // stbi__convert_format frees input on failure\n   }\n   return out;\n}\n\nstatic int      stbi__pnm_isspace(char c)\n{\n   return c == ' ' || c == '\\t' || c == '\\n' || c == '\\v' || c == '\\f' || c == '\\r';\n}\n\nstatic void     stbi__pnm_skip_whitespace(stbi__context *s, char *c)\n{\n   for (;;) {\n      while (!stbi__at_eof(s) && stbi__pnm_isspace(*c))\n         *c = (char) stbi__get8(s);\n\n      if (stbi__at_eof(s) || *c != '#')\n         break;\n\n      while (!stbi__at_eof(s) && *c != '\\n' && *c != '\\r' )\n         *c = (char) stbi__get8(s);\n   }\n}\n\nstatic int      stbi__pnm_isdigit(char c)\n{\n   return c >= '0' && c <= '9';\n}\n\nstatic int      stbi__pnm_getinteger(stbi__context *s, char *c)\n{\n   int value = 0;\n\n   while (!stbi__at_eof(s) && stbi__pnm_isdigit(*c)) {\n      value = value*10 + (*c - '0');\n      *c = (char) stbi__get8(s);\n   }\n\n   return value;\n}\n\nstatic int      stbi__pnm_info(stbi__context *s, int *x, int *y, int *comp)\n{\n   int maxv;\n   char c, p, t;\n\n   stbi__rewind( s );\n\n   // Get identifier\n   p = (char) stbi__get8(s);\n   t = (char) stbi__get8(s);\n   if (p != 'P' || (t != '5' && t != '6')) {\n       stbi__rewind( s );\n       return 0;\n   }\n\n   *comp = (t == '6') ? 3 : 1;  // '5' is 1-component .pgm; '6' is 3-component .ppm\n\n   c = (char) stbi__get8(s);\n   stbi__pnm_skip_whitespace(s, &c);\n\n   *x = stbi__pnm_getinteger(s, &c); // read width\n   stbi__pnm_skip_whitespace(s, &c);\n\n   *y = stbi__pnm_getinteger(s, &c); // read height\n   stbi__pnm_skip_whitespace(s, &c);\n\n   maxv = stbi__pnm_getinteger(s, &c);  // read max value\n\n   if (maxv > 255)\n      return stbi__err(\"max value > 255\", \"PPM image not 8-bit\");\n   else\n      return 1;\n}\n#endif\n\nstatic int stbi__info_main(stbi__context *s, int *x, int *y, int *comp)\n{\n   #ifndef STBI_NO_JPEG\n   if (stbi__jpeg_info(s, x, y, comp)) return 1;\n   #endif\n\n   #ifndef STBI_NO_PNG\n   if (stbi__png_info(s, x, y, comp))  return 1;\n   #endif\n\n   #ifndef STBI_NO_GIF\n   if (stbi__gif_info(s, x, y, comp))  return 1;\n   #endif\n\n   #ifndef STBI_NO_BMP\n   if (stbi__bmp_info(s, x, y, comp))  return 1;\n   #endif\n\n   #ifndef STBI_NO_PSD\n   if (stbi__psd_info(s, x, y, comp))  return 1;\n   #endif\n\n   #ifndef STBI_NO_PIC\n   if (stbi__pic_info(s, x, y, comp))  return 1;\n   #endif\n\n   #ifndef STBI_NO_PNM\n   if (stbi__pnm_info(s, x, y, comp))  return 1;\n   #endif\n\n   #ifndef STBI_NO_HDR\n   if (stbi__hdr_info(s, x, y, comp))  return 1;\n   #endif\n\n   // test tga last because it's a crappy test!\n   #ifndef STBI_NO_TGA\n   if (stbi__tga_info(s, x, y, comp))\n       return 1;\n   #endif\n   return stbi__err(\"unknown image type\", \"Image not of any known type, or corrupt\");\n}\n\n#ifndef STBI_NO_STDIO\nSTBIDEF int stbi_info(char const *filename, int *x, int *y, int *comp)\n{\n    FILE *f = stbi__fopen(filename, \"rb\");\n    int result;\n    if (!f) return stbi__err(\"can't fopen\", \"Unable to open file\");\n    result = stbi_info_from_file(f, x, y, comp);\n    fclose(f);\n    return result;\n}\n\nSTBIDEF int stbi_info_from_file(FILE *f, int *x, int *y, int *comp)\n{\n   int r;\n   stbi__context s;\n   long pos = ftell(f);\n   stbi__start_file(&s, f);\n   r = stbi__info_main(&s,x,y,comp);\n   fseek(f,pos,SEEK_SET);\n   return r;\n}\n#endif // !STBI_NO_STDIO\n\nSTBIDEF int stbi_info_from_memory(stbi_uc const *buffer, int len, int *x, int *y, int *comp)\n{\n   stbi__context s;\n   stbi__start_mem(&s,buffer,len);\n   return stbi__info_main(&s,x,y,comp);\n}\n\nSTBIDEF int stbi_info_from_callbacks(stbi_io_callbacks const *c, void *user, int *x, int *y, int *comp)\n{\n   stbi__context s;\n   stbi__start_callbacks(&s, (stbi_io_callbacks *) c, user);\n   return stbi__info_main(&s,x,y,comp);\n}\n\n#endif // STB_IMAGE_IMPLEMENTATION\n\n/*\n   revision history:\n      2.10  (2016-01-22) avoid warning introduced in 2.09 by STBI_REALLOC_SIZED\n      2.09  (2016-01-16) allow comments in PNM files\n                         16-bit-per-pixel TGA (not bit-per-component)\n                         info() for TGA could break due to .hdr handling\n                         info() for BMP to shares code instead of sloppy parse\n                         can use STBI_REALLOC_SIZED if allocator doesn't support realloc\n                         code cleanup\n      2.08  (2015-09-13) fix to 2.07 cleanup, reading RGB PSD as RGBA\n      2.07  (2015-09-13) fix compiler warnings\n                         partial animated GIF support\n                         limited 16-bpc PSD support\n                         #ifdef unused functions\n                         bug with < 92 byte PIC,PNM,HDR,TGA\n      2.06  (2015-04-19) fix bug where PSD returns wrong '*comp' value\n      2.05  (2015-04-19) fix bug in progressive JPEG handling, fix warning\n      2.04  (2015-04-15) try to re-enable SIMD on MinGW 64-bit\n      2.03  (2015-04-12) extra corruption checking (mmozeiko)\n                         stbi_set_flip_vertically_on_load (nguillemot)\n                         fix NEON support; fix mingw support\n      2.02  (2015-01-19) fix incorrect assert, fix warning\n      2.01  (2015-01-17) fix various warnings; suppress SIMD on gcc 32-bit without -msse2\n      2.00b (2014-12-25) fix STBI_MALLOC in progressive JPEG\n      2.00  (2014-12-25) optimize JPG, including x86 SSE2 & NEON SIMD (ryg)\n                         progressive JPEG (stb)\n                         PGM/PPM support (Ken Miller)\n                         STBI_MALLOC,STBI_REALLOC,STBI_FREE\n                         GIF bugfix -- seemingly never worked\n                         STBI_NO_*, STBI_ONLY_*\n      1.48  (2014-12-14) fix incorrectly-named assert()\n      1.47  (2014-12-14) 1/2/4-bit PNG support, both direct and paletted (Omar Cornut & stb)\n                         optimize PNG (ryg)\n                         fix bug in interlaced PNG with user-specified channel count (stb)\n      1.46  (2014-08-26)\n              fix broken tRNS chunk (colorkey-style transparency) in non-paletted PNG\n      1.45  (2014-08-16)\n              fix MSVC-ARM internal compiler error by wrapping malloc\n      1.44  (2014-08-07)\n              various warning fixes from Ronny Chevalier\n      1.43  (2014-07-15)\n              fix MSVC-only compiler problem in code changed in 1.42\n      1.42  (2014-07-09)\n              don't define _CRT_SECURE_NO_WARNINGS (affects user code)\n              fixes to stbi__cleanup_jpeg path\n              added STBI_ASSERT to avoid requiring assert.h\n      1.41  (2014-06-25)\n              fix search&replace from 1.36 that messed up comments/error messages\n      1.40  (2014-06-22)\n              fix gcc struct-initialization warning\n      1.39  (2014-06-15)\n              fix to TGA optimization when req_comp != number of components in TGA;\n              fix to GIF loading because BMP wasn't rewinding (whoops, no GIFs in my test suite)\n              add support for BMP version 5 (more ignored fields)\n      1.38  (2014-06-06)\n              suppress MSVC warnings on integer casts truncating values\n              fix accidental rename of 'skip' field of I/O\n      1.37  (2014-06-04)\n              remove duplicate typedef\n      1.36  (2014-06-03)\n              convert to header file single-file library\n              if de-iphone isn't set, load iphone images color-swapped instead of returning NULL\n      1.35  (2014-05-27)\n              various warnings\n              fix broken STBI_SIMD path\n              fix bug where stbi_load_from_file no longer left file pointer in correct place\n              fix broken non-easy path for 32-bit BMP (possibly never used)\n              TGA optimization by Arseny Kapoulkine\n      1.34  (unknown)\n              use STBI_NOTUSED in stbi__resample_row_generic(), fix one more leak in tga failure case\n      1.33  (2011-07-14)\n              make stbi_is_hdr work in STBI_NO_HDR (as specified), minor compiler-friendly improvements\n      1.32  (2011-07-13)\n              support for \"info\" function for all supported filetypes (SpartanJ)\n      1.31  (2011-06-20)\n              a few more leak fixes, bug in PNG handling (SpartanJ)\n      1.30  (2011-06-11)\n              added ability to load files via callbacks to accomidate custom input streams (Ben Wenger)\n              removed deprecated format-specific test/load functions\n              removed support for installable file formats (stbi_loader) -- would have been broken for IO callbacks anyway\n              error cases in bmp and tga give messages and don't leak (Raymond Barbiero, grisha)\n              fix inefficiency in decoding 32-bit BMP (David Woo)\n      1.29  (2010-08-16)\n              various warning fixes from Aurelien Pocheville\n      1.28  (2010-08-01)\n              fix bug in GIF palette transparency (SpartanJ)\n      1.27  (2010-08-01)\n              cast-to-stbi_uc to fix warnings\n      1.26  (2010-07-24)\n              fix bug in file buffering for PNG reported by SpartanJ\n      1.25  (2010-07-17)\n              refix trans_data warning (Won Chun)\n      1.24  (2010-07-12)\n              perf improvements reading from files on platforms with lock-heavy fgetc()\n              minor perf improvements for jpeg\n              deprecated type-specific functions so we'll get feedback if they're needed\n              attempt to fix trans_data warning (Won Chun)\n      1.23    fixed bug in iPhone support\n      1.22  (2010-07-10)\n              removed image *writing* support\n              stbi_info support from Jetro Lauha\n              GIF support from Jean-Marc Lienher\n              iPhone PNG-extensions from James Brown\n              warning-fixes from Nicolas Schulz and Janez Zemva (i.stbi__err. Janez (U+017D)emva)\n      1.21    fix use of 'stbi_uc' in header (reported by jon blow)\n      1.20    added support for Softimage PIC, by Tom Seddon\n      1.19    bug in interlaced PNG corruption check (found by ryg)\n      1.18  (2008-08-02)\n              fix a threading bug (local mutable static)\n      1.17    support interlaced PNG\n      1.16    major bugfix - stbi__convert_format converted one too many pixels\n      1.15    initialize some fields for thread safety\n      1.14    fix threadsafe conversion bug\n              header-file-only version (#define STBI_HEADER_FILE_ONLY before including)\n      1.13    threadsafe\n      1.12    const qualifiers in the API\n      1.11    Support installable IDCT, colorspace conversion routines\n      1.10    Fixes for 64-bit (don't use \"unsigned long\")\n              optimized upsampling by Fabian \"ryg\" Giesen\n      1.09    Fix format-conversion for PSD code (bad global variables!)\n      1.08    Thatcher Ulrich's PSD code integrated by Nicolas Schulz\n      1.07    attempt to fix C++ warning/errors again\n      1.06    attempt to fix C++ warning/errors again\n      1.05    fix TGA loading to return correct *comp and use good luminance calc\n      1.04    default float alpha is 1, not 255; use 'void *' for stbi_image_free\n      1.03    bugfixes to STBI_NO_STDIO, STBI_NO_HDR\n      1.02    support for (subset of) HDR files, float interface for preferred access to them\n      1.01    fix bug: possible bug in handling right-side up bmps... not sure\n              fix bug: the stbi__bmp_load() and stbi__tga_load() functions didn't work at all\n      1.00    interface to zlib that skips zlib header\n      0.99    correct handling of alpha in palette\n      0.98    TGA loader by lonesock; dynamically add loaders (untested)\n      0.97    jpeg errors on too large a file; also catch another malloc failure\n      0.96    fix detection of invalid v value - particleman@mollyrocket forum\n      0.95    during header scan, seek to markers in case of padding\n      0.94    STBI_NO_STDIO to disable stdio usage; rename all #defines the same\n      0.93    handle jpegtran output; verbose errors\n      0.92    read 4,8,16,24,32-bit BMP files of several formats\n      0.91    output 24-bit Windows 3.0 BMP files\n      0.90    fix a few more warnings; bump version number to approach 1.0\n      0.61    bugfixes due to Marc LeBlanc, Christopher Lloyd\n      0.60    fix compiling as c++\n      0.59    fix warnings: merge Dave Moore's -Wall fixes\n      0.58    fix bug: zlib uncompressed mode len/nlen was wrong endian\n      0.57    fix bug: jpg last huffman symbol before marker was >9 bits but less than 16 available\n      0.56    fix bug: zlib uncompressed mode len vs. nlen\n      0.55    fix bug: restart_interval not initialized to 0\n      0.54    allow NULL for 'int *comp'\n      0.53    fix bug in png 3->4; speedup png decoding\n      0.52    png handles req_comp=3,4 directly; minor cleanup; jpeg comments\n      0.51    obey req_comp requests, 1-component jpegs return as 1-component,\n              on 'test' only check type, not whether we support this variant\n      0.50  (2006-11-19)\n              first released version\n*/\n"
  },
  {
    "path": "phonelibs/nanovg/stb_truetype.h",
    "content": "// stb_truetype.h - v1.24 - public domain\n// authored from 2009-2020 by Sean Barrett / RAD Game Tools\n//\n// =======================================================================\n//\n//    NO SECURITY GUARANTEE -- DO NOT USE THIS ON UNTRUSTED FONT FILES\n//\n// This library does no range checking of the offsets found in the file,\n// meaning an attacker can use it to read arbitrary memory.\n//\n// =======================================================================\n//\n//   This library processes TrueType files:\n//        parse files\n//        extract glyph metrics\n//        extract glyph shapes\n//        render glyphs to one-channel bitmaps with antialiasing (box filter)\n//        render glyphs to one-channel SDF bitmaps (signed-distance field/function)\n//\n//   Todo:\n//        non-MS cmaps\n//        crashproof on bad data\n//        hinting? (no longer patented)\n//        cleartype-style AA?\n//        optimize: use simple memory allocator for intermediates\n//        optimize: build edge-list directly from curves\n//        optimize: rasterize directly from curves?\n//\n// ADDITIONAL CONTRIBUTORS\n//\n//   Mikko Mononen: compound shape support, more cmap formats\n//   Tor Andersson: kerning, subpixel rendering\n//   Dougall Johnson: OpenType / Type 2 font handling\n//   Daniel Ribeiro Maciel: basic GPOS-based kerning\n//\n//   Misc other:\n//       Ryan Gordon\n//       Simon Glass\n//       github:IntellectualKitty\n//       Imanol Celaya\n//       Daniel Ribeiro Maciel\n//\n//   Bug/warning reports/fixes:\n//       \"Zer\" on mollyrocket       Fabian \"ryg\" Giesen   github:NiLuJe\n//       Cass Everitt               Martins Mozeiko       github:aloucks\n//       stoiko (Haemimont Games)   Cap Petschulat        github:oyvindjam\n//       Brian Hook                 Omar Cornut           github:vassvik\n//       Walter van Niftrik         Ryan Griege\n//       David Gow                  Peter LaValle\n//       David Given                Sergey Popov\n//       Ivan-Assen Ivanov          Giumo X. Clanjor\n//       Anthony Pesch              Higor Euripedes\n//       Johan Duparc               Thomas Fields\n//       Hou Qiming                 Derek Vinyard\n//       Rob Loach                  Cort Stratton\n//       Kenney Phillis Jr.         Brian Costabile\n//       Ken Voskuil (kaesve)\n//\n// VERSION HISTORY\n//\n//   1.24 (2020-02-05) fix warning\n//   1.23 (2020-02-02) query SVG data for glyphs; query whole kerning table (but only kern not GPOS)\n//   1.22 (2019-08-11) minimize missing-glyph duplication; fix kerning if both 'GPOS' and 'kern' are defined\n//   1.21 (2019-02-25) fix warning\n//   1.20 (2019-02-07) PackFontRange skips missing codepoints; GetScaleFontVMetrics()\n//   1.19 (2018-02-11) GPOS kerning, STBTT_fmod\n//   1.18 (2018-01-29) add missing function\n//   1.17 (2017-07-23) make more arguments const; doc fix\n//   1.16 (2017-07-12) SDF support\n//   1.15 (2017-03-03) make more arguments const\n//   1.14 (2017-01-16) num-fonts-in-TTC function\n//   1.13 (2017-01-02) support OpenType fonts, certain Apple fonts\n//   1.12 (2016-10-25) suppress warnings about casting away const with -Wcast-qual\n//   1.11 (2016-04-02) fix unused-variable warning\n//   1.10 (2016-04-02) user-defined fabs(); rare memory leak; remove duplicate typedef\n//   1.09 (2016-01-16) warning fix; avoid crash on outofmem; use allocation userdata properly\n//   1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges\n//   1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints;\n//                     variant PackFontRanges to pack and render in separate phases;\n//                     fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?);\n//                     fixed an assert() bug in the new rasterizer\n//                     replace assert() with STBTT_assert() in new rasterizer\n//\n//   Full history can be found at the end of this file.\n//\n// LICENSE\n//\n//   See end of file for license information.\n//\n// USAGE\n//\n//   Include this file in whatever places need to refer to it. In ONE C/C++\n//   file, write:\n//      #define STB_TRUETYPE_IMPLEMENTATION\n//   before the #include of this file. This expands out the actual\n//   implementation into that C/C++ file.\n//\n//   To make the implementation private to the file that generates the implementation,\n//      #define STBTT_STATIC\n//\n//   Simple 3D API (don't ship this, but it's fine for tools and quick start)\n//           stbtt_BakeFontBitmap()               -- bake a font to a bitmap for use as texture\n//           stbtt_GetBakedQuad()                 -- compute quad to draw for a given char\n//\n//   Improved 3D API (more shippable):\n//           #include \"stb_rect_pack.h\"           -- optional, but you really want it\n//           stbtt_PackBegin()\n//           stbtt_PackSetOversampling()          -- for improved quality on small fonts\n//           stbtt_PackFontRanges()               -- pack and renders\n//           stbtt_PackEnd()\n//           stbtt_GetPackedQuad()\n//\n//   \"Load\" a font file from a memory buffer (you have to keep the buffer loaded)\n//           stbtt_InitFont()\n//           stbtt_GetFontOffsetForIndex()        -- indexing for TTC font collections\n//           stbtt_GetNumberOfFonts()             -- number of fonts for TTC font collections\n//\n//   Render a unicode codepoint to a bitmap\n//           stbtt_GetCodepointBitmap()           -- allocates and returns a bitmap\n//           stbtt_MakeCodepointBitmap()          -- renders into bitmap you provide\n//           stbtt_GetCodepointBitmapBox()        -- how big the bitmap must be\n//\n//   Character advance/positioning\n//           stbtt_GetCodepointHMetrics()\n//           stbtt_GetFontVMetrics()\n//           stbtt_GetFontVMetricsOS2()\n//           stbtt_GetCodepointKernAdvance()\n//\n//   Starting with version 1.06, the rasterizer was replaced with a new,\n//   faster and generally-more-precise rasterizer. The new rasterizer more\n//   accurately measures pixel coverage for anti-aliasing, except in the case\n//   where multiple shapes overlap, in which case it overestimates the AA pixel\n//   coverage. Thus, anti-aliasing of intersecting shapes may look wrong. If\n//   this turns out to be a problem, you can re-enable the old rasterizer with\n//        #define STBTT_RASTERIZER_VERSION 1\n//   which will incur about a 15% speed hit.\n//\n// ADDITIONAL DOCUMENTATION\n//\n//   Immediately after this block comment are a series of sample programs.\n//\n//   After the sample programs is the \"header file\" section. This section\n//   includes documentation for each API function.\n//\n//   Some important concepts to understand to use this library:\n//\n//      Codepoint\n//         Characters are defined by unicode codepoints, e.g. 65 is\n//         uppercase A, 231 is lowercase c with a cedilla, 0x7e30 is\n//         the hiragana for \"ma\".\n//\n//      Glyph\n//         A visual character shape (every codepoint is rendered as\n//         some glyph)\n//\n//      Glyph index\n//         A font-specific integer ID representing a glyph\n//\n//      Baseline\n//         Glyph shapes are defined relative to a baseline, which is the\n//         bottom of uppercase characters. Characters extend both above\n//         and below the baseline.\n//\n//      Current Point\n//         As you draw text to the screen, you keep track of a \"current point\"\n//         which is the origin of each character. The current point's vertical\n//         position is the baseline. Even \"baked fonts\" use this model.\n//\n//      Vertical Font Metrics\n//         The vertical qualities of the font, used to vertically position\n//         and space the characters. See docs for stbtt_GetFontVMetrics.\n//\n//      Font Size in Pixels or Points\n//         The preferred interface for specifying font sizes in stb_truetype\n//         is to specify how tall the font's vertical extent should be in pixels.\n//         If that sounds good enough, skip the next paragraph.\n//\n//         Most font APIs instead use \"points\", which are a common typographic\n//         measurement for describing font size, defined as 72 points per inch.\n//         stb_truetype provides a point API for compatibility. However, true\n//         \"per inch\" conventions don't make much sense on computer displays\n//         since different monitors have different number of pixels per\n//         inch. For example, Windows traditionally uses a convention that\n//         there are 96 pixels per inch, thus making 'inch' measurements have\n//         nothing to do with inches, and thus effectively defining a point to\n//         be 1.333 pixels. Additionally, the TrueType font data provides\n//         an explicit scale factor to scale a given font's glyphs to points,\n//         but the author has observed that this scale factor is often wrong\n//         for non-commercial fonts, thus making fonts scaled in points\n//         according to the TrueType spec incoherently sized in practice.\n//\n// DETAILED USAGE:\n//\n//  Scale:\n//    Select how high you want the font to be, in points or pixels.\n//    Call ScaleForPixelHeight or ScaleForMappingEmToPixels to compute\n//    a scale factor SF that will be used by all other functions.\n//\n//  Baseline:\n//    You need to select a y-coordinate that is the baseline of where\n//    your text will appear. Call GetFontBoundingBox to get the baseline-relative\n//    bounding box for all characters. SF*-y0 will be the distance in pixels\n//    that the worst-case character could extend above the baseline, so if\n//    you want the top edge of characters to appear at the top of the\n//    screen where y=0, then you would set the baseline to SF*-y0.\n//\n//  Current point:\n//    Set the current point where the first character will appear. The\n//    first character could extend left of the current point; this is font\n//    dependent. You can either choose a current point that is the leftmost\n//    point and hope, or add some padding, or check the bounding box or\n//    left-side-bearing of the first character to be displayed and set\n//    the current point based on that.\n//\n//  Displaying a character:\n//    Compute the bounding box of the character. It will contain signed values\n//    relative to <current_point, baseline>. I.e. if it returns x0,y0,x1,y1,\n//    then the character should be displayed in the rectangle from\n//    <current_point+SF*x0, baseline+SF*y0> to <current_point+SF*x1,baseline+SF*y1).\n//\n//  Advancing for the next character:\n//    Call GlyphHMetrics, and compute 'current_point += SF * advance'.\n//\n//\n// ADVANCED USAGE\n//\n//   Quality:\n//\n//    - Use the functions with Subpixel at the end to allow your characters\n//      to have subpixel positioning. Since the font is anti-aliased, not\n//      hinted, this is very import for quality. (This is not possible with\n//      baked fonts.)\n//\n//    - Kerning is now supported, and if you're supporting subpixel rendering\n//      then kerning is worth using to give your text a polished look.\n//\n//   Performance:\n//\n//    - Convert Unicode codepoints to glyph indexes and operate on the glyphs;\n//      if you don't do this, stb_truetype is forced to do the conversion on\n//      every call.\n//\n//    - There are a lot of memory allocations. We should modify it to take\n//      a temp buffer and allocate from the temp buffer (without freeing),\n//      should help performance a lot.\n//\n// NOTES\n//\n//   The system uses the raw data found in the .ttf file without changing it\n//   and without building auxiliary data structures. This is a bit inefficient\n//   on little-endian systems (the data is big-endian), but assuming you're\n//   caching the bitmaps or glyph shapes this shouldn't be a big deal.\n//\n//   It appears to be very hard to programmatically determine what font a\n//   given file is in a general way. I provide an API for this, but I don't\n//   recommend it.\n//\n//\n// PERFORMANCE MEASUREMENTS FOR 1.06:\n//\n//                      32-bit     64-bit\n//   Previous release:  8.83 s     7.68 s\n//   Pool allocations:  7.72 s     6.34 s\n//   Inline sort     :  6.54 s     5.65 s\n//   New rasterizer  :  5.63 s     5.00 s\n\n//////////////////////////////////////////////////////////////////////////////\n//////////////////////////////////////////////////////////////////////////////\n////\n////  SAMPLE PROGRAMS\n////\n//\n//  Incomplete text-in-3d-api example, which draws quads properly aligned to be lossless\n//\n#if 0\n#define STB_TRUETYPE_IMPLEMENTATION  // force following include to generate implementation\n#include \"stb_truetype.h\"\n\nunsigned char ttf_buffer[1<<20];\nunsigned char temp_bitmap[512*512];\n\nstbtt_bakedchar cdata[96]; // ASCII 32..126 is 95 glyphs\nGLuint ftex;\n\nvoid my_stbtt_initfont(void)\n{\n   fread(ttf_buffer, 1, 1<<20, fopen(\"c:/windows/fonts/times.ttf\", \"rb\"));\n   stbtt_BakeFontBitmap(ttf_buffer,0, 32.0, temp_bitmap,512,512, 32,96, cdata); // no guarantee this fits!\n   // can free ttf_buffer at this point\n   glGenTextures(1, &ftex);\n   glBindTexture(GL_TEXTURE_2D, ftex);\n   glTexImage2D(GL_TEXTURE_2D, 0, GL_ALPHA, 512,512, 0, GL_ALPHA, GL_UNSIGNED_BYTE, temp_bitmap);\n   // can free temp_bitmap at this point\n   glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR);\n}\n\nvoid my_stbtt_print(float x, float y, char *text)\n{\n   // assume orthographic projection with units = screen pixels, origin at top left\n   glEnable(GL_TEXTURE_2D);\n   glBindTexture(GL_TEXTURE_2D, ftex);\n   glBegin(GL_QUADS);\n   while (*text) {\n      if (*text >= 32 && *text < 128) {\n         stbtt_aligned_quad q;\n         stbtt_GetBakedQuad(cdata, 512,512, *text-32, &x,&y,&q,1);//1=opengl & d3d10+,0=d3d9\n         glTexCoord2f(q.s0,q.t1); glVertex2f(q.x0,q.y0);\n         glTexCoord2f(q.s1,q.t1); glVertex2f(q.x1,q.y0);\n         glTexCoord2f(q.s1,q.t0); glVertex2f(q.x1,q.y1);\n         glTexCoord2f(q.s0,q.t0); glVertex2f(q.x0,q.y1);\n      }\n      ++text;\n   }\n   glEnd();\n}\n#endif\n//\n//\n//////////////////////////////////////////////////////////////////////////////\n//\n// Complete program (this compiles): get a single bitmap, print as ASCII art\n//\n#if 0\n#include <stdio.h>\n#define STB_TRUETYPE_IMPLEMENTATION  // force following include to generate implementation\n#include \"stb_truetype.h\"\n\nchar ttf_buffer[1<<25];\n\nint main(int argc, char **argv)\n{\n   stbtt_fontinfo font;\n   unsigned char *bitmap;\n   int w,h,i,j,c = (argc > 1 ? atoi(argv[1]) : 'a'), s = (argc > 2 ? atoi(argv[2]) : 20);\n\n   fread(ttf_buffer, 1, 1<<25, fopen(argc > 3 ? argv[3] : \"c:/windows/fonts/arialbd.ttf\", \"rb\"));\n\n   stbtt_InitFont(&font, ttf_buffer, stbtt_GetFontOffsetForIndex(ttf_buffer,0));\n   bitmap = stbtt_GetCodepointBitmap(&font, 0,stbtt_ScaleForPixelHeight(&font, s), c, &w, &h, 0,0);\n\n   for (j=0; j < h; ++j) {\n      for (i=0; i < w; ++i)\n         putchar(\" .:ioVM@\"[bitmap[j*w+i]>>5]);\n      putchar('\\n');\n   }\n   return 0;\n}\n#endif\n//\n// Output:\n//\n//     .ii.\n//    @@@@@@.\n//   V@Mio@@o\n//   :i.  V@V\n//     :oM@@M\n//   :@@@MM@M\n//   @@o  o@M\n//  :@@.  M@M\n//   @@@o@@@@\n//   :M@@V:@@.\n//\n//////////////////////////////////////////////////////////////////////////////\n//\n// Complete program: print \"Hello World!\" banner, with bugs\n//\n#if 0\nchar buffer[24<<20];\nunsigned char screen[20][79];\n\nint main(int arg, char **argv)\n{\n   stbtt_fontinfo font;\n   int i,j,ascent,baseline,ch=0;\n   float scale, xpos=2; // leave a little padding in case the character extends left\n   char *text = \"Heljo World!\"; // intentionally misspelled to show 'lj' brokenness\n\n   fread(buffer, 1, 1000000, fopen(\"c:/windows/fonts/arialbd.ttf\", \"rb\"));\n   stbtt_InitFont(&font, buffer, 0);\n\n   scale = stbtt_ScaleForPixelHeight(&font, 15);\n   stbtt_GetFontVMetrics(&font, &ascent,0,0);\n   baseline = (int) (ascent*scale);\n\n   while (text[ch]) {\n      int advance,lsb,x0,y0,x1,y1;\n      float x_shift = xpos - (float) floor(xpos);\n      stbtt_GetCodepointHMetrics(&font, text[ch], &advance, &lsb);\n      stbtt_GetCodepointBitmapBoxSubpixel(&font, text[ch], scale,scale,x_shift,0, &x0,&y0,&x1,&y1);\n      stbtt_MakeCodepointBitmapSubpixel(&font, &screen[baseline + y0][(int) xpos + x0], x1-x0,y1-y0, 79, scale,scale,x_shift,0, text[ch]);\n      // note that this stomps the old data, so where character boxes overlap (e.g. 'lj') it's wrong\n      // because this API is really for baking character bitmaps into textures. if you want to render\n      // a sequence of characters, you really need to render each bitmap to a temp buffer, then\n      // \"alpha blend\" that into the working buffer\n      xpos += (advance * scale);\n      if (text[ch+1])\n         xpos += scale*stbtt_GetCodepointKernAdvance(&font, text[ch],text[ch+1]);\n      ++ch;\n   }\n\n   for (j=0; j < 20; ++j) {\n      for (i=0; i < 78; ++i)\n         putchar(\" .:ioVM@\"[screen[j][i]>>5]);\n      putchar('\\n');\n   }\n\n   return 0;\n}\n#endif\n\n\n//////////////////////////////////////////////////////////////////////////////\n//////////////////////////////////////////////////////////////////////////////\n////\n////   INTEGRATION WITH YOUR CODEBASE\n////\n////   The following sections allow you to supply alternate definitions\n////   of C library functions used by stb_truetype, e.g. if you don't\n////   link with the C runtime library.\n\n#ifdef STB_TRUETYPE_IMPLEMENTATION\n   // #define your own (u)stbtt_int8/16/32 before including to override this\n   #ifndef stbtt_uint8\n   typedef unsigned char   stbtt_uint8;\n   typedef signed   char   stbtt_int8;\n   typedef unsigned short  stbtt_uint16;\n   typedef signed   short  stbtt_int16;\n   typedef unsigned int    stbtt_uint32;\n   typedef signed   int    stbtt_int32;\n   #endif\n\n   typedef char stbtt__check_size32[sizeof(stbtt_int32)==4 ? 1 : -1];\n   typedef char stbtt__check_size16[sizeof(stbtt_int16)==2 ? 1 : -1];\n\n   // e.g. #define your own STBTT_ifloor/STBTT_iceil() to avoid math.h\n   #ifndef STBTT_ifloor\n   #include <math.h>\n   #define STBTT_ifloor(x)   ((int) floor(x))\n   #define STBTT_iceil(x)    ((int) ceil(x))\n   #endif\n\n   #ifndef STBTT_sqrt\n   #include <math.h>\n   #define STBTT_sqrt(x)      sqrt(x)\n   #define STBTT_pow(x,y)     pow(x,y)\n   #endif\n\n   #ifndef STBTT_fmod\n   #include <math.h>\n   #define STBTT_fmod(x,y)    fmod(x,y)\n   #endif\n\n   #ifndef STBTT_cos\n   #include <math.h>\n   #define STBTT_cos(x)       cos(x)\n   #define STBTT_acos(x)      acos(x)\n   #endif\n\n   #ifndef STBTT_fabs\n   #include <math.h>\n   #define STBTT_fabs(x)      fabs(x)\n   #endif\n\n   // #define your own functions \"STBTT_malloc\" / \"STBTT_free\" to avoid malloc.h\n   #ifndef STBTT_malloc\n   #include <stdlib.h>\n   #define STBTT_malloc(x,u)  ((void)(u),malloc(x))\n   #define STBTT_free(x,u)    ((void)(u),free(x))\n   #endif\n\n   #ifndef STBTT_assert\n   #include <assert.h>\n   #define STBTT_assert(x)    assert(x)\n   #endif\n\n   #ifndef STBTT_strlen\n   #include <string.h>\n   #define STBTT_strlen(x)    strlen(x)\n   #endif\n\n   #ifndef STBTT_memcpy\n   #include <string.h>\n   #define STBTT_memcpy       memcpy\n   #define STBTT_memset       memset\n   #endif\n#endif\n\n///////////////////////////////////////////////////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n////\n////   INTERFACE\n////\n////\n\n#ifndef __STB_INCLUDE_STB_TRUETYPE_H__\n#define __STB_INCLUDE_STB_TRUETYPE_H__\n\n#ifdef STBTT_STATIC\n#define STBTT_DEF static\n#else\n#define STBTT_DEF extern\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// private structure\ntypedef struct\n{\n   unsigned char *data;\n   int cursor;\n   int size;\n} stbtt__buf;\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// TEXTURE BAKING API\n//\n// If you use this API, you only have to call two functions ever.\n//\n\ntypedef struct\n{\n   unsigned short x0,y0,x1,y1; // coordinates of bbox in bitmap\n   float xoff,yoff,xadvance;\n} stbtt_bakedchar;\n\nSTBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset,  // font location (use offset=0 for plain .ttf)\n                                float pixel_height,                     // height of font in pixels\n                                unsigned char *pixels, int pw, int ph,  // bitmap to be filled in\n                                int first_char, int num_chars,          // characters to bake\n                                stbtt_bakedchar *chardata);             // you allocate this, it's num_chars long\n// if return is positive, the first unused row of the bitmap\n// if return is negative, returns the negative of the number of characters that fit\n// if return is 0, no characters fit and no rows were used\n// This uses a very crappy packing.\n\ntypedef struct\n{\n   float x0,y0,s0,t0; // top-left\n   float x1,y1,s1,t1; // bottom-right\n} stbtt_aligned_quad;\n\nSTBTT_DEF void stbtt_GetBakedQuad(const stbtt_bakedchar *chardata, int pw, int ph,  // same data as above\n                               int char_index,             // character to display\n                               float *xpos, float *ypos,   // pointers to current position in screen pixel space\n                               stbtt_aligned_quad *q,      // output: quad to draw\n                               int opengl_fillrule);       // true if opengl fill rule; false if DX9 or earlier\n// Call GetBakedQuad with char_index = 'character - first_char', and it\n// creates the quad you need to draw and advances the current position.\n//\n// The coordinate system used assumes y increases downwards.\n//\n// Characters will extend both above and below the current position;\n// see discussion of \"BASELINE\" above.\n//\n// It's inefficient; you might want to c&p it and optimize it.\n\nSTBTT_DEF void stbtt_GetScaledFontVMetrics(const unsigned char *fontdata, int index, float size, float *ascent, float *descent, float *lineGap);\n// Query the font vertical metrics without having to create a font first.\n\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// NEW TEXTURE BAKING API\n//\n// This provides options for packing multiple fonts into one atlas, not\n// perfectly but better than nothing.\n\ntypedef struct\n{\n   unsigned short x0,y0,x1,y1; // coordinates of bbox in bitmap\n   float xoff,yoff,xadvance;\n   float xoff2,yoff2;\n} stbtt_packedchar;\n\ntypedef struct stbtt_pack_context stbtt_pack_context;\ntypedef struct stbtt_fontinfo stbtt_fontinfo;\n#ifndef STB_RECT_PACK_VERSION\ntypedef struct stbrp_rect stbrp_rect;\n#endif\n\nSTBTT_DEF int  stbtt_PackBegin(stbtt_pack_context *spc, unsigned char *pixels, int width, int height, int stride_in_bytes, int padding, void *alloc_context);\n// Initializes a packing context stored in the passed-in stbtt_pack_context.\n// Future calls using this context will pack characters into the bitmap passed\n// in here: a 1-channel bitmap that is width * height. stride_in_bytes is\n// the distance from one row to the next (or 0 to mean they are packed tightly\n// together). \"padding\" is the amount of padding to leave between each\n// character (normally you want '1' for bitmaps you'll use as textures with\n// bilinear filtering).\n//\n// Returns 0 on failure, 1 on success.\n\nSTBTT_DEF void stbtt_PackEnd  (stbtt_pack_context *spc);\n// Cleans up the packing context and frees all memory.\n\n#define STBTT_POINT_SIZE(x)   (-(x))\n\nSTBTT_DEF int  stbtt_PackFontRange(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, float font_size,\n                                int first_unicode_char_in_range, int num_chars_in_range, stbtt_packedchar *chardata_for_range);\n// Creates character bitmaps from the font_index'th font found in fontdata (use\n// font_index=0 if you don't know what that is). It creates num_chars_in_range\n// bitmaps for characters with unicode values starting at first_unicode_char_in_range\n// and increasing. Data for how to render them is stored in chardata_for_range;\n// pass these to stbtt_GetPackedQuad to get back renderable quads.\n//\n// font_size is the full height of the character from ascender to descender,\n// as computed by stbtt_ScaleForPixelHeight. To use a point size as computed\n// by stbtt_ScaleForMappingEmToPixels, wrap the point size in STBTT_POINT_SIZE()\n// and pass that result as 'font_size':\n//       ...,                  20 , ... // font max minus min y is 20 pixels tall\n//       ..., STBTT_POINT_SIZE(20), ... // 'M' is 20 pixels tall\n\ntypedef struct\n{\n   float font_size;\n   int first_unicode_codepoint_in_range;  // if non-zero, then the chars are continuous, and this is the first codepoint\n   int *array_of_unicode_codepoints;       // if non-zero, then this is an array of unicode codepoints\n   int num_chars;\n   stbtt_packedchar *chardata_for_range; // output\n   unsigned char h_oversample, v_oversample; // don't set these, they're used internally\n} stbtt_pack_range;\n\nSTBTT_DEF int  stbtt_PackFontRanges(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges);\n// Creates character bitmaps from multiple ranges of characters stored in\n// ranges. This will usually create a better-packed bitmap than multiple\n// calls to stbtt_PackFontRange. Note that you can call this multiple\n// times within a single PackBegin/PackEnd.\n\nSTBTT_DEF void stbtt_PackSetOversampling(stbtt_pack_context *spc, unsigned int h_oversample, unsigned int v_oversample);\n// Oversampling a font increases the quality by allowing higher-quality subpixel\n// positioning, and is especially valuable at smaller text sizes.\n//\n// This function sets the amount of oversampling for all following calls to\n// stbtt_PackFontRange(s) or stbtt_PackFontRangesGatherRects for a given\n// pack context. The default (no oversampling) is achieved by h_oversample=1\n// and v_oversample=1. The total number of pixels required is\n// h_oversample*v_oversample larger than the default; for example, 2x2\n// oversampling requires 4x the storage of 1x1. For best results, render\n// oversampled textures with bilinear filtering. Look at the readme in\n// stb/tests/oversample for information about oversampled fonts\n//\n// To use with PackFontRangesGather etc., you must set it before calls\n// call to PackFontRangesGatherRects.\n\nSTBTT_DEF void stbtt_PackSetSkipMissingCodepoints(stbtt_pack_context *spc, int skip);\n// If skip != 0, this tells stb_truetype to skip any codepoints for which\n// there is no corresponding glyph. If skip=0, which is the default, then\n// codepoints without a glyph recived the font's \"missing character\" glyph,\n// typically an empty box by convention.\n\nSTBTT_DEF void stbtt_GetPackedQuad(const stbtt_packedchar *chardata, int pw, int ph,  // same data as above\n                               int char_index,             // character to display\n                               float *xpos, float *ypos,   // pointers to current position in screen pixel space\n                               stbtt_aligned_quad *q,      // output: quad to draw\n                               int align_to_integer);\n\nSTBTT_DEF int  stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects);\nSTBTT_DEF void stbtt_PackFontRangesPackRects(stbtt_pack_context *spc, stbrp_rect *rects, int num_rects);\nSTBTT_DEF int  stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects);\n// Calling these functions in sequence is roughly equivalent to calling\n// stbtt_PackFontRanges(). If you more control over the packing of multiple\n// fonts, or if you want to pack custom data into a font texture, take a look\n// at the source to of stbtt_PackFontRanges() and create a custom version\n// using these functions, e.g. call GatherRects multiple times,\n// building up a single array of rects, then call PackRects once,\n// then call RenderIntoRects repeatedly. This may result in a\n// better packing than calling PackFontRanges multiple times\n// (or it may not).\n\n// this is an opaque structure that you shouldn't mess with which holds\n// all the context needed from PackBegin to PackEnd.\nstruct stbtt_pack_context {\n   void *user_allocator_context;\n   void *pack_info;\n   int   width;\n   int   height;\n   int   stride_in_bytes;\n   int   padding;\n   int   skip_missing;\n   unsigned int   h_oversample, v_oversample;\n   unsigned char *pixels;\n   void  *nodes;\n};\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// FONT LOADING\n//\n//\n\nSTBTT_DEF int stbtt_GetNumberOfFonts(const unsigned char *data);\n// This function will determine the number of fonts in a font file.  TrueType\n// collection (.ttc) files may contain multiple fonts, while TrueType font\n// (.ttf) files only contain one font. The number of fonts can be used for\n// indexing with the previous function where the index is between zero and one\n// less than the total fonts. If an error occurs, -1 is returned.\n\nSTBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *data, int index);\n// Each .ttf/.ttc file may have more than one font. Each font has a sequential\n// index number starting from 0. Call this function to get the font offset for\n// a given index; it returns -1 if the index is out of range. A regular .ttf\n// file will only define one font and it always be at offset 0, so it will\n// return '0' for index 0, and -1 for all other indices.\n\n// The following structure is defined publicly so you can declare one on\n// the stack or as a global or etc, but you should treat it as opaque.\nstruct stbtt_fontinfo\n{\n   void           * userdata;\n   unsigned char  * data;              // pointer to .ttf file\n   int              fontstart;         // offset of start of font\n\n   int numGlyphs;                     // number of glyphs, needed for range checking\n\n   int loca,head,glyf,hhea,hmtx,kern,gpos,svg; // table locations as offset from start of .ttf\n   int index_map;                     // a cmap mapping for our chosen character encoding\n   int indexToLocFormat;              // format needed to map from glyph index to glyph\n\n   stbtt__buf cff;                    // cff font data\n   stbtt__buf charstrings;            // the charstring index\n   stbtt__buf gsubrs;                 // global charstring subroutines index\n   stbtt__buf subrs;                  // private charstring subroutines index\n   stbtt__buf fontdicts;              // array of font dicts\n   stbtt__buf fdselect;               // map from glyph to fontdict\n};\n\nSTBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data, int offset);\n// Given an offset into the file that defines a font, this function builds\n// the necessary cached info for the rest of the system. You must allocate\n// the stbtt_fontinfo yourself, and stbtt_InitFont will fill it out. You don't\n// need to do anything special to free it, because the contents are pure\n// value data with no additional data structures. Returns 0 on failure.\n\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// CHARACTER TO GLYPH-INDEX CONVERSIOn\n\nSTBTT_DEF int stbtt_FindGlyphIndex(const stbtt_fontinfo *info, int unicode_codepoint);\n// If you're going to perform multiple operations on the same character\n// and you want a speed-up, call this function with the character you're\n// going to process, then use glyph-based functions instead of the\n// codepoint-based functions.\n// Returns 0 if the character codepoint is not defined in the font.\n\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// CHARACTER PROPERTIES\n//\n\nSTBTT_DEF float stbtt_ScaleForPixelHeight(const stbtt_fontinfo *info, float pixels);\n// computes a scale factor to produce a font whose \"height\" is 'pixels' tall.\n// Height is measured as the distance from the highest ascender to the lowest\n// descender; in other words, it's equivalent to calling stbtt_GetFontVMetrics\n// and computing:\n//       scale = pixels / (ascent - descent)\n// so if you prefer to measure height by the ascent only, use a similar calculation.\n\nSTBTT_DEF float stbtt_ScaleForMappingEmToPixels(const stbtt_fontinfo *info, float pixels);\n// computes a scale factor to produce a font whose EM size is mapped to\n// 'pixels' tall. This is probably what traditional APIs compute, but\n// I'm not positive.\n\nSTBTT_DEF void stbtt_GetFontVMetrics(const stbtt_fontinfo *info, int *ascent, int *descent, int *lineGap);\n// ascent is the coordinate above the baseline the font extends; descent\n// is the coordinate below the baseline the font extends (i.e. it is typically negative)\n// lineGap is the spacing between one row's descent and the next row's ascent...\n// so you should advance the vertical position by \"*ascent - *descent + *lineGap\"\n//   these are expressed in unscaled coordinates, so you must multiply by\n//   the scale factor for a given size\n\nSTBTT_DEF int  stbtt_GetFontVMetricsOS2(const stbtt_fontinfo *info, int *typoAscent, int *typoDescent, int *typoLineGap);\n// analogous to GetFontVMetrics, but returns the \"typographic\" values from the OS/2\n// table (specific to MS/Windows TTF files).\n//\n// Returns 1 on success (table present), 0 on failure.\n\nSTBTT_DEF void stbtt_GetFontBoundingBox(const stbtt_fontinfo *info, int *x0, int *y0, int *x1, int *y1);\n// the bounding box around all possible characters\n\nSTBTT_DEF void stbtt_GetCodepointHMetrics(const stbtt_fontinfo *info, int codepoint, int *advanceWidth, int *leftSideBearing);\n// leftSideBearing is the offset from the current horizontal position to the left edge of the character\n// advanceWidth is the offset from the current horizontal position to the next horizontal position\n//   these are expressed in unscaled coordinates\n\nSTBTT_DEF int  stbtt_GetCodepointKernAdvance(const stbtt_fontinfo *info, int ch1, int ch2);\n// an additional amount to add to the 'advance' value between ch1 and ch2\n\nSTBTT_DEF int stbtt_GetCodepointBox(const stbtt_fontinfo *info, int codepoint, int *x0, int *y0, int *x1, int *y1);\n// Gets the bounding box of the visible part of the glyph, in unscaled coordinates\n\nSTBTT_DEF void stbtt_GetGlyphHMetrics(const stbtt_fontinfo *info, int glyph_index, int *advanceWidth, int *leftSideBearing);\nSTBTT_DEF int  stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2);\nSTBTT_DEF int  stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1);\n// as above, but takes one or more glyph indices for greater efficiency\n\ntypedef struct stbtt_kerningentry\n{\n   int glyph1; // use stbtt_FindGlyphIndex\n   int glyph2;\n   int advance;\n} stbtt_kerningentry;\n\nSTBTT_DEF int  stbtt_GetKerningTableLength(const stbtt_fontinfo *info);\nSTBTT_DEF int  stbtt_GetKerningTable(const stbtt_fontinfo *info, stbtt_kerningentry* table, int table_length);\n// Retrieves a complete list of all of the kerning pairs provided by the font\n// stbtt_GetKerningTable never writes more than table_length entries and returns how many entries it did write.\n// The table will be sorted by (a.glyph1 == b.glyph1)?(a.glyph2 < b.glyph2):(a.glyph1 < b.glyph1)\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// GLYPH SHAPES (you probably don't need these, but they have to go before\n// the bitmaps for C declaration-order reasons)\n//\n\n#ifndef STBTT_vmove // you can predefine these to use different values (but why?)\n   enum {\n      STBTT_vmove=1,\n      STBTT_vline,\n      STBTT_vcurve,\n      STBTT_vcubic\n   };\n#endif\n\n#ifndef stbtt_vertex // you can predefine this to use different values\n                   // (we share this with other code at RAD)\n   #define stbtt_vertex_type short // can't use stbtt_int16 because that's not visible in the header file\n   typedef struct\n   {\n      stbtt_vertex_type x,y,cx,cy,cx1,cy1;\n      unsigned char type,padding;\n   } stbtt_vertex;\n#endif\n\nSTBTT_DEF int stbtt_IsGlyphEmpty(const stbtt_fontinfo *info, int glyph_index);\n// returns non-zero if nothing is drawn for this glyph\n\nSTBTT_DEF int stbtt_GetCodepointShape(const stbtt_fontinfo *info, int unicode_codepoint, stbtt_vertex **vertices);\nSTBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **vertices);\n// returns # of vertices and fills *vertices with the pointer to them\n//   these are expressed in \"unscaled\" coordinates\n//\n// The shape is a series of contours. Each one starts with\n// a STBTT_moveto, then consists of a series of mixed\n// STBTT_lineto and STBTT_curveto segments. A lineto\n// draws a line from previous endpoint to its x,y; a curveto\n// draws a quadratic bezier from previous endpoint to\n// its x,y, using cx,cy as the bezier control point.\n\nSTBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *vertices);\n// frees the data allocated above\n\nSTBTT_DEF int stbtt_GetCodepointSVG(const stbtt_fontinfo *info, int unicode_codepoint, const char **svg);\nSTBTT_DEF int stbtt_GetGlyphSVG(const stbtt_fontinfo *info, int gl, const char **svg);\n// fills svg with the character's SVG data.\n// returns data size or 0 if SVG not found.\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// BITMAP RENDERING\n//\n\nSTBTT_DEF void stbtt_FreeBitmap(unsigned char *bitmap, void *userdata);\n// frees the bitmap allocated below\n\nSTBTT_DEF unsigned char *stbtt_GetCodepointBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int codepoint, int *width, int *height, int *xoff, int *yoff);\n// allocates a large-enough single-channel 8bpp bitmap and renders the\n// specified character/glyph at the specified scale into it, with\n// antialiasing. 0 is no coverage (transparent), 255 is fully covered (opaque).\n// *width & *height are filled out with the width & height of the bitmap,\n// which is stored left-to-right, top-to-bottom.\n//\n// xoff/yoff are the offset it pixel space from the glyph origin to the top-left of the bitmap\n\nSTBTT_DEF unsigned char *stbtt_GetCodepointBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint, int *width, int *height, int *xoff, int *yoff);\n// the same as stbtt_GetCodepoitnBitmap, but you can specify a subpixel\n// shift for the character\n\nSTBTT_DEF void stbtt_MakeCodepointBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int codepoint);\n// the same as stbtt_GetCodepointBitmap, but you pass in storage for the bitmap\n// in the form of 'output', with row spacing of 'out_stride' bytes. the bitmap\n// is clipped to out_w/out_h bytes. Call stbtt_GetCodepointBitmapBox to get the\n// width and height and positioning info for it first.\n\nSTBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint);\n// same as stbtt_MakeCodepointBitmap, but you can specify a subpixel\n// shift for the character\n\nSTBTT_DEF void stbtt_MakeCodepointBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int oversample_x, int oversample_y, float *sub_x, float *sub_y, int codepoint);\n// same as stbtt_MakeCodepointBitmapSubpixel, but prefiltering\n// is performed (see stbtt_PackSetOversampling)\n\nSTBTT_DEF void stbtt_GetCodepointBitmapBox(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1);\n// get the bbox of the bitmap centered around the glyph origin; so the\n// bitmap width is ix1-ix0, height is iy1-iy0, and location to place\n// the bitmap top left is (leftSideBearing*scale,iy0).\n// (Note that the bitmap uses y-increases-down, but the shape uses\n// y-increases-up, so CodepointBitmapBox and CodepointBox are inverted.)\n\nSTBTT_DEF void stbtt_GetCodepointBitmapBoxSubpixel(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1);\n// same as stbtt_GetCodepointBitmapBox, but you can specify a subpixel\n// shift for the character\n\n// the following functions are equivalent to the above functions, but operate\n// on glyph indices instead of Unicode codepoints (for efficiency)\nSTBTT_DEF unsigned char *stbtt_GetGlyphBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int glyph, int *width, int *height, int *xoff, int *yoff);\nSTBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int glyph, int *width, int *height, int *xoff, int *yoff);\nSTBTT_DEF void stbtt_MakeGlyphBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int glyph);\nSTBTT_DEF void stbtt_MakeGlyphBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int glyph);\nSTBTT_DEF void stbtt_MakeGlyphBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int oversample_x, int oversample_y, float *sub_x, float *sub_y, int glyph);\nSTBTT_DEF void stbtt_GetGlyphBitmapBox(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1);\nSTBTT_DEF void stbtt_GetGlyphBitmapBoxSubpixel(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y,float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1);\n\n\n// @TODO: don't expose this structure\ntypedef struct\n{\n   int w,h,stride;\n   unsigned char *pixels;\n} stbtt__bitmap;\n\n// rasterize a shape with quadratic beziers into a bitmap\nSTBTT_DEF void stbtt_Rasterize(stbtt__bitmap *result,        // 1-channel bitmap to draw into\n                               float flatness_in_pixels,     // allowable error of curve in pixels\n                               stbtt_vertex *vertices,       // array of vertices defining shape\n                               int num_verts,                // number of vertices in above array\n                               float scale_x, float scale_y, // scale applied to input vertices\n                               float shift_x, float shift_y, // translation applied to input vertices\n                               int x_off, int y_off,         // another translation applied to input\n                               int invert,                   // if non-zero, vertically flip shape\n                               void *userdata);              // context for to STBTT_MALLOC\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// Signed Distance Function (or Field) rendering\n\nSTBTT_DEF void stbtt_FreeSDF(unsigned char *bitmap, void *userdata);\n// frees the SDF bitmap allocated below\n\nSTBTT_DEF unsigned char * stbtt_GetGlyphSDF(const stbtt_fontinfo *info, float scale, int glyph, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff);\nSTBTT_DEF unsigned char * stbtt_GetCodepointSDF(const stbtt_fontinfo *info, float scale, int codepoint, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff);\n// These functions compute a discretized SDF field for a single character, suitable for storing\n// in a single-channel texture, sampling with bilinear filtering, and testing against\n// larger than some threshold to produce scalable fonts.\n//        info              --  the font\n//        scale             --  controls the size of the resulting SDF bitmap, same as it would be creating a regular bitmap\n//        glyph/codepoint   --  the character to generate the SDF for\n//        padding           --  extra \"pixels\" around the character which are filled with the distance to the character (not 0),\n//                                 which allows effects like bit outlines\n//        onedge_value      --  value 0-255 to test the SDF against to reconstruct the character (i.e. the isocontour of the character)\n//        pixel_dist_scale  --  what value the SDF should increase by when moving one SDF \"pixel\" away from the edge (on the 0..255 scale)\n//                                 if positive, > onedge_value is inside; if negative, < onedge_value is inside\n//        width,height      --  output height & width of the SDF bitmap (including padding)\n//        xoff,yoff         --  output origin of the character\n//        return value      --  a 2D array of bytes 0..255, width*height in size\n//\n// pixel_dist_scale & onedge_value are a scale & bias that allows you to make\n// optimal use of the limited 0..255 for your application, trading off precision\n// and special effects. SDF values outside the range 0..255 are clamped to 0..255.\n//\n// Example:\n//      scale = stbtt_ScaleForPixelHeight(22)\n//      padding = 5\n//      onedge_value = 180\n//      pixel_dist_scale = 180/5.0 = 36.0\n//\n//      This will create an SDF bitmap in which the character is about 22 pixels\n//      high but the whole bitmap is about 22+5+5=32 pixels high. To produce a filled\n//      shape, sample the SDF at each pixel and fill the pixel if the SDF value\n//      is greater than or equal to 180/255. (You'll actually want to antialias,\n//      which is beyond the scope of this example.) Additionally, you can compute\n//      offset outlines (e.g. to stroke the character border inside & outside,\n//      or only outside). For example, to fill outside the character up to 3 SDF\n//      pixels, you would compare against (180-36.0*3)/255 = 72/255. The above\n//      choice of variables maps a range from 5 pixels outside the shape to\n//      2 pixels inside the shape to 0..255; this is intended primarily for apply\n//      outside effects only (the interior range is needed to allow proper\n//      antialiasing of the font at *smaller* sizes)\n//\n// The function computes the SDF analytically at each SDF pixel, not by e.g.\n// building a higher-res bitmap and approximating it. In theory the quality\n// should be as high as possible for an SDF of this size & representation, but\n// unclear if this is true in practice (perhaps building a higher-res bitmap\n// and computing from that can allow drop-out prevention).\n//\n// The algorithm has not been optimized at all, so expect it to be slow\n// if computing lots of characters or very large sizes.\n\n\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// Finding the right font...\n//\n// You should really just solve this offline, keep your own tables\n// of what font is what, and don't try to get it out of the .ttf file.\n// That's because getting it out of the .ttf file is really hard, because\n// the names in the file can appear in many possible encodings, in many\n// possible languages, and e.g. if you need a case-insensitive comparison,\n// the details of that depend on the encoding & language in a complex way\n// (actually underspecified in truetype, but also gigantic).\n//\n// But you can use the provided functions in two possible ways:\n//     stbtt_FindMatchingFont() will use *case-sensitive* comparisons on\n//             unicode-encoded names to try to find the font you want;\n//             you can run this before calling stbtt_InitFont()\n//\n//     stbtt_GetFontNameString() lets you get any of the various strings\n//             from the file yourself and do your own comparisons on them.\n//             You have to have called stbtt_InitFont() first.\n\n\nSTBTT_DEF int stbtt_FindMatchingFont(const unsigned char *fontdata, const char *name, int flags);\n// returns the offset (not index) of the font that matches, or -1 if none\n//   if you use STBTT_MACSTYLE_DONTCARE, use a font name like \"Arial Bold\".\n//   if you use any other flag, use a font name like \"Arial\"; this checks\n//     the 'macStyle' header field; i don't know if fonts set this consistently\n#define STBTT_MACSTYLE_DONTCARE     0\n#define STBTT_MACSTYLE_BOLD         1\n#define STBTT_MACSTYLE_ITALIC       2\n#define STBTT_MACSTYLE_UNDERSCORE   4\n#define STBTT_MACSTYLE_NONE         8   // <= not same as 0, this makes us check the bitfield is 0\n\nSTBTT_DEF int stbtt_CompareUTF8toUTF16_bigendian(const char *s1, int len1, const char *s2, int len2);\n// returns 1/0 whether the first string interpreted as utf8 is identical to\n// the second string interpreted as big-endian utf16... useful for strings from next func\n\nSTBTT_DEF const char *stbtt_GetFontNameString(const stbtt_fontinfo *font, int *length, int platformID, int encodingID, int languageID, int nameID);\n// returns the string (which may be big-endian double byte, e.g. for unicode)\n// and puts the length in bytes in *length.\n//\n// some of the values for the IDs are below; for more see the truetype spec:\n//     http://developer.apple.com/textfonts/TTRefMan/RM06/Chap6name.html\n//     http://www.microsoft.com/typography/otspec/name.htm\n\nenum { // platformID\n   STBTT_PLATFORM_ID_UNICODE   =0,\n   STBTT_PLATFORM_ID_MAC       =1,\n   STBTT_PLATFORM_ID_ISO       =2,\n   STBTT_PLATFORM_ID_MICROSOFT =3\n};\n\nenum { // encodingID for STBTT_PLATFORM_ID_UNICODE\n   STBTT_UNICODE_EID_UNICODE_1_0    =0,\n   STBTT_UNICODE_EID_UNICODE_1_1    =1,\n   STBTT_UNICODE_EID_ISO_10646      =2,\n   STBTT_UNICODE_EID_UNICODE_2_0_BMP=3,\n   STBTT_UNICODE_EID_UNICODE_2_0_FULL=4\n};\n\nenum { // encodingID for STBTT_PLATFORM_ID_MICROSOFT\n   STBTT_MS_EID_SYMBOL        =0,\n   STBTT_MS_EID_UNICODE_BMP   =1,\n   STBTT_MS_EID_SHIFTJIS      =2,\n   STBTT_MS_EID_UNICODE_FULL  =10\n};\n\nenum { // encodingID for STBTT_PLATFORM_ID_MAC; same as Script Manager codes\n   STBTT_MAC_EID_ROMAN        =0,   STBTT_MAC_EID_ARABIC       =4,\n   STBTT_MAC_EID_JAPANESE     =1,   STBTT_MAC_EID_HEBREW       =5,\n   STBTT_MAC_EID_CHINESE_TRAD =2,   STBTT_MAC_EID_GREEK        =6,\n   STBTT_MAC_EID_KOREAN       =3,   STBTT_MAC_EID_RUSSIAN      =7\n};\n\nenum { // languageID for STBTT_PLATFORM_ID_MICROSOFT; same as LCID...\n       // problematic because there are e.g. 16 english LCIDs and 16 arabic LCIDs\n   STBTT_MS_LANG_ENGLISH     =0x0409,   STBTT_MS_LANG_ITALIAN     =0x0410,\n   STBTT_MS_LANG_CHINESE     =0x0804,   STBTT_MS_LANG_JAPANESE    =0x0411,\n   STBTT_MS_LANG_DUTCH       =0x0413,   STBTT_MS_LANG_KOREAN      =0x0412,\n   STBTT_MS_LANG_FRENCH      =0x040c,   STBTT_MS_LANG_RUSSIAN     =0x0419,\n   STBTT_MS_LANG_GERMAN      =0x0407,   STBTT_MS_LANG_SPANISH     =0x0409,\n   STBTT_MS_LANG_HEBREW      =0x040d,   STBTT_MS_LANG_SWEDISH     =0x041D\n};\n\nenum { // languageID for STBTT_PLATFORM_ID_MAC\n   STBTT_MAC_LANG_ENGLISH      =0 ,   STBTT_MAC_LANG_JAPANESE     =11,\n   STBTT_MAC_LANG_ARABIC       =12,   STBTT_MAC_LANG_KOREAN       =23,\n   STBTT_MAC_LANG_DUTCH        =4 ,   STBTT_MAC_LANG_RUSSIAN      =32,\n   STBTT_MAC_LANG_FRENCH       =1 ,   STBTT_MAC_LANG_SPANISH      =6 ,\n   STBTT_MAC_LANG_GERMAN       =2 ,   STBTT_MAC_LANG_SWEDISH      =5 ,\n   STBTT_MAC_LANG_HEBREW       =10,   STBTT_MAC_LANG_CHINESE_SIMPLIFIED =33,\n   STBTT_MAC_LANG_ITALIAN      =3 ,   STBTT_MAC_LANG_CHINESE_TRAD =19\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // __STB_INCLUDE_STB_TRUETYPE_H__\n\n///////////////////////////////////////////////////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n////\n////   IMPLEMENTATION\n////\n////\n\n#ifdef STB_TRUETYPE_IMPLEMENTATION\n\n#ifndef STBTT_MAX_OVERSAMPLE\n#define STBTT_MAX_OVERSAMPLE   8\n#endif\n\n#if STBTT_MAX_OVERSAMPLE > 255\n#error \"STBTT_MAX_OVERSAMPLE cannot be > 255\"\n#endif\n\ntypedef int stbtt__test_oversample_pow2[(STBTT_MAX_OVERSAMPLE & (STBTT_MAX_OVERSAMPLE-1)) == 0 ? 1 : -1];\n\n#ifndef STBTT_RASTERIZER_VERSION\n#define STBTT_RASTERIZER_VERSION 2\n#endif\n\n#ifdef _MSC_VER\n#define STBTT__NOTUSED(v)  (void)(v)\n#else\n#define STBTT__NOTUSED(v)  (void)sizeof(v)\n#endif\n\n//////////////////////////////////////////////////////////////////////////\n//\n// stbtt__buf helpers to parse data from file\n//\n\nstatic stbtt_uint8 stbtt__buf_get8(stbtt__buf *b)\n{\n   if (b->cursor >= b->size)\n      return 0;\n   return b->data[b->cursor++];\n}\n\nstatic stbtt_uint8 stbtt__buf_peek8(stbtt__buf *b)\n{\n   if (b->cursor >= b->size)\n      return 0;\n   return b->data[b->cursor];\n}\n\nstatic void stbtt__buf_seek(stbtt__buf *b, int o)\n{\n   STBTT_assert(!(o > b->size || o < 0));\n   b->cursor = (o > b->size || o < 0) ? b->size : o;\n}\n\nstatic void stbtt__buf_skip(stbtt__buf *b, int o)\n{\n   stbtt__buf_seek(b, b->cursor + o);\n}\n\nstatic stbtt_uint32 stbtt__buf_get(stbtt__buf *b, int n)\n{\n   stbtt_uint32 v = 0;\n   int i;\n   STBTT_assert(n >= 1 && n <= 4);\n   for (i = 0; i < n; i++)\n      v = (v << 8) | stbtt__buf_get8(b);\n   return v;\n}\n\nstatic stbtt__buf stbtt__new_buf(const void *p, size_t size)\n{\n   stbtt__buf r;\n   STBTT_assert(size < 0x40000000);\n   r.data = (stbtt_uint8*) p;\n   r.size = (int) size;\n   r.cursor = 0;\n   return r;\n}\n\n#define stbtt__buf_get16(b)  stbtt__buf_get((b), 2)\n#define stbtt__buf_get32(b)  stbtt__buf_get((b), 4)\n\nstatic stbtt__buf stbtt__buf_range(const stbtt__buf *b, int o, int s)\n{\n   stbtt__buf r = stbtt__new_buf(NULL, 0);\n   if (o < 0 || s < 0 || o > b->size || s > b->size - o) return r;\n   r.data = b->data + o;\n   r.size = s;\n   return r;\n}\n\nstatic stbtt__buf stbtt__cff_get_index(stbtt__buf *b)\n{\n   int count, start, offsize;\n   start = b->cursor;\n   count = stbtt__buf_get16(b);\n   if (count) {\n      offsize = stbtt__buf_get8(b);\n      STBTT_assert(offsize >= 1 && offsize <= 4);\n      stbtt__buf_skip(b, offsize * count);\n      stbtt__buf_skip(b, stbtt__buf_get(b, offsize) - 1);\n   }\n   return stbtt__buf_range(b, start, b->cursor - start);\n}\n\nstatic stbtt_uint32 stbtt__cff_int(stbtt__buf *b)\n{\n   int b0 = stbtt__buf_get8(b);\n   if (b0 >= 32 && b0 <= 246)       return b0 - 139;\n   else if (b0 >= 247 && b0 <= 250) return (b0 - 247)*256 + stbtt__buf_get8(b) + 108;\n   else if (b0 >= 251 && b0 <= 254) return -(b0 - 251)*256 - stbtt__buf_get8(b) - 108;\n   else if (b0 == 28)               return stbtt__buf_get16(b);\n   else if (b0 == 29)               return stbtt__buf_get32(b);\n   STBTT_assert(0);\n   return 0;\n}\n\nstatic void stbtt__cff_skip_operand(stbtt__buf *b) {\n   int v, b0 = stbtt__buf_peek8(b);\n   STBTT_assert(b0 >= 28);\n   if (b0 == 30) {\n      stbtt__buf_skip(b, 1);\n      while (b->cursor < b->size) {\n         v = stbtt__buf_get8(b);\n         if ((v & 0xF) == 0xF || (v >> 4) == 0xF)\n            break;\n      }\n   } else {\n      stbtt__cff_int(b);\n   }\n}\n\nstatic stbtt__buf stbtt__dict_get(stbtt__buf *b, int key)\n{\n   stbtt__buf_seek(b, 0);\n   while (b->cursor < b->size) {\n      int start = b->cursor, end, op;\n      while (stbtt__buf_peek8(b) >= 28)\n         stbtt__cff_skip_operand(b);\n      end = b->cursor;\n      op = stbtt__buf_get8(b);\n      if (op == 12)  op = stbtt__buf_get8(b) | 0x100;\n      if (op == key) return stbtt__buf_range(b, start, end-start);\n   }\n   return stbtt__buf_range(b, 0, 0);\n}\n\nstatic void stbtt__dict_get_ints(stbtt__buf *b, int key, int outcount, stbtt_uint32 *out)\n{\n   int i;\n   stbtt__buf operands = stbtt__dict_get(b, key);\n   for (i = 0; i < outcount && operands.cursor < operands.size; i++)\n      out[i] = stbtt__cff_int(&operands);\n}\n\nstatic int stbtt__cff_index_count(stbtt__buf *b)\n{\n   stbtt__buf_seek(b, 0);\n   return stbtt__buf_get16(b);\n}\n\nstatic stbtt__buf stbtt__cff_index_get(stbtt__buf b, int i)\n{\n   int count, offsize, start, end;\n   stbtt__buf_seek(&b, 0);\n   count = stbtt__buf_get16(&b);\n   offsize = stbtt__buf_get8(&b);\n   STBTT_assert(i >= 0 && i < count);\n   STBTT_assert(offsize >= 1 && offsize <= 4);\n   stbtt__buf_skip(&b, i*offsize);\n   start = stbtt__buf_get(&b, offsize);\n   end = stbtt__buf_get(&b, offsize);\n   return stbtt__buf_range(&b, 2+(count+1)*offsize+start, end - start);\n}\n\n//////////////////////////////////////////////////////////////////////////\n//\n// accessors to parse data from file\n//\n\n// on platforms that don't allow misaligned reads, if we want to allow\n// truetype fonts that aren't padded to alignment, define ALLOW_UNALIGNED_TRUETYPE\n\n#define ttBYTE(p)     (* (stbtt_uint8 *) (p))\n#define ttCHAR(p)     (* (stbtt_int8 *) (p))\n#define ttFixed(p)    ttLONG(p)\n\nstatic stbtt_uint16 ttUSHORT(stbtt_uint8 *p) { return p[0]*256 + p[1]; }\nstatic stbtt_int16 ttSHORT(stbtt_uint8 *p)   { return p[0]*256 + p[1]; }\nstatic stbtt_uint32 ttULONG(stbtt_uint8 *p)  { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; }\nstatic stbtt_int32 ttLONG(stbtt_uint8 *p)    { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; }\n\n#define stbtt_tag4(p,c0,c1,c2,c3) ((p)[0] == (c0) && (p)[1] == (c1) && (p)[2] == (c2) && (p)[3] == (c3))\n#define stbtt_tag(p,str)           stbtt_tag4(p,str[0],str[1],str[2],str[3])\n\nstatic int stbtt__isfont(stbtt_uint8 *font)\n{\n   // check the version number\n   if (stbtt_tag4(font, '1',0,0,0))  return 1; // TrueType 1\n   if (stbtt_tag(font, \"typ1\"))   return 1; // TrueType with type 1 font -- we don't support this!\n   if (stbtt_tag(font, \"OTTO\"))   return 1; // OpenType with CFF\n   if (stbtt_tag4(font, 0,1,0,0)) return 1; // OpenType 1.0\n   if (stbtt_tag(font, \"true\"))   return 1; // Apple specification for TrueType fonts\n   return 0;\n}\n\n// @OPTIMIZE: binary search\nstatic stbtt_uint32 stbtt__find_table(stbtt_uint8 *data, stbtt_uint32 fontstart, const char *tag)\n{\n   stbtt_int32 num_tables = ttUSHORT(data+fontstart+4);\n   stbtt_uint32 tabledir = fontstart + 12;\n   stbtt_int32 i;\n   for (i=0; i < num_tables; ++i) {\n      stbtt_uint32 loc = tabledir + 16*i;\n      if (stbtt_tag(data+loc+0, tag))\n         return ttULONG(data+loc+8);\n   }\n   return 0;\n}\n\nstatic int stbtt_GetFontOffsetForIndex_internal(unsigned char *font_collection, int index)\n{\n   // if it's just a font, there's only one valid index\n   if (stbtt__isfont(font_collection))\n      return index == 0 ? 0 : -1;\n\n   // check if it's a TTC\n   if (stbtt_tag(font_collection, \"ttcf\")) {\n      // version 1?\n      if (ttULONG(font_collection+4) == 0x00010000 || ttULONG(font_collection+4) == 0x00020000) {\n         stbtt_int32 n = ttLONG(font_collection+8);\n         if (index >= n)\n            return -1;\n         return ttULONG(font_collection+12+index*4);\n      }\n   }\n   return -1;\n}\n\nstatic int stbtt_GetNumberOfFonts_internal(unsigned char *font_collection)\n{\n   // if it's just a font, there's only one valid font\n   if (stbtt__isfont(font_collection))\n      return 1;\n\n   // check if it's a TTC\n   if (stbtt_tag(font_collection, \"ttcf\")) {\n      // version 1?\n      if (ttULONG(font_collection+4) == 0x00010000 || ttULONG(font_collection+4) == 0x00020000) {\n         return ttLONG(font_collection+8);\n      }\n   }\n   return 0;\n}\n\nstatic stbtt__buf stbtt__get_subrs(stbtt__buf cff, stbtt__buf fontdict)\n{\n   stbtt_uint32 subrsoff = 0, private_loc[2] = { 0, 0 };\n   stbtt__buf pdict;\n   stbtt__dict_get_ints(&fontdict, 18, 2, private_loc);\n   if (!private_loc[1] || !private_loc[0]) return stbtt__new_buf(NULL, 0);\n   pdict = stbtt__buf_range(&cff, private_loc[1], private_loc[0]);\n   stbtt__dict_get_ints(&pdict, 19, 1, &subrsoff);\n   if (!subrsoff) return stbtt__new_buf(NULL, 0);\n   stbtt__buf_seek(&cff, private_loc[1]+subrsoff);\n   return stbtt__cff_get_index(&cff);\n}\n\n// since most people won't use this, find this table the first time it's needed\nstatic int stbtt__get_svg(stbtt_fontinfo *info)\n{\n   stbtt_uint32 t;\n   if (info->svg < 0) {\n      t = stbtt__find_table(info->data, info->fontstart, \"SVG \");\n      if (t) {\n         stbtt_uint32 offset = ttULONG(info->data + t + 2);\n         info->svg = t + offset;\n      } else {\n         info->svg = 0;\n      }\n   }\n   return info->svg;\n}\n\nstatic int stbtt_InitFont_internal(stbtt_fontinfo *info, unsigned char *data, int fontstart)\n{\n   stbtt_uint32 cmap, t;\n   stbtt_int32 i,numTables;\n\n   info->data = data;\n   info->fontstart = fontstart;\n   info->cff = stbtt__new_buf(NULL, 0);\n\n   cmap = stbtt__find_table(data, fontstart, \"cmap\");       // required\n   info->loca = stbtt__find_table(data, fontstart, \"loca\"); // required\n   info->head = stbtt__find_table(data, fontstart, \"head\"); // required\n   info->glyf = stbtt__find_table(data, fontstart, \"glyf\"); // required\n   info->hhea = stbtt__find_table(data, fontstart, \"hhea\"); // required\n   info->hmtx = stbtt__find_table(data, fontstart, \"hmtx\"); // required\n   info->kern = stbtt__find_table(data, fontstart, \"kern\"); // not required\n   info->gpos = stbtt__find_table(data, fontstart, \"GPOS\"); // not required\n\n   if (!cmap || !info->head || !info->hhea || !info->hmtx)\n      return 0;\n   if (info->glyf) {\n      // required for truetype\n      if (!info->loca) return 0;\n   } else {\n      // initialization for CFF / Type2 fonts (OTF)\n      stbtt__buf b, topdict, topdictidx;\n      stbtt_uint32 cstype = 2, charstrings = 0, fdarrayoff = 0, fdselectoff = 0;\n      stbtt_uint32 cff;\n\n      cff = stbtt__find_table(data, fontstart, \"CFF \");\n      if (!cff) return 0;\n\n      info->fontdicts = stbtt__new_buf(NULL, 0);\n      info->fdselect = stbtt__new_buf(NULL, 0);\n\n      // @TODO this should use size from table (not 512MB)\n      info->cff = stbtt__new_buf(data+cff, 512*1024*1024);\n      b = info->cff;\n\n      // read the header\n      stbtt__buf_skip(&b, 2);\n      stbtt__buf_seek(&b, stbtt__buf_get8(&b)); // hdrsize\n\n      // @TODO the name INDEX could list multiple fonts,\n      // but we just use the first one.\n      stbtt__cff_get_index(&b);  // name INDEX\n      topdictidx = stbtt__cff_get_index(&b);\n      topdict = stbtt__cff_index_get(topdictidx, 0);\n      stbtt__cff_get_index(&b);  // string INDEX\n      info->gsubrs = stbtt__cff_get_index(&b);\n\n      stbtt__dict_get_ints(&topdict, 17, 1, &charstrings);\n      stbtt__dict_get_ints(&topdict, 0x100 | 6, 1, &cstype);\n      stbtt__dict_get_ints(&topdict, 0x100 | 36, 1, &fdarrayoff);\n      stbtt__dict_get_ints(&topdict, 0x100 | 37, 1, &fdselectoff);\n      info->subrs = stbtt__get_subrs(b, topdict);\n\n      // we only support Type 2 charstrings\n      if (cstype != 2) return 0;\n      if (charstrings == 0) return 0;\n\n      if (fdarrayoff) {\n         // looks like a CID font\n         if (!fdselectoff) return 0;\n         stbtt__buf_seek(&b, fdarrayoff);\n         info->fontdicts = stbtt__cff_get_index(&b);\n         info->fdselect = stbtt__buf_range(&b, fdselectoff, b.size-fdselectoff);\n      }\n\n      stbtt__buf_seek(&b, charstrings);\n      info->charstrings = stbtt__cff_get_index(&b);\n   }\n\n   t = stbtt__find_table(data, fontstart, \"maxp\");\n   if (t)\n      info->numGlyphs = ttUSHORT(data+t+4);\n   else\n      info->numGlyphs = 0xffff;\n\n   info->svg = -1;\n\n   // find a cmap encoding table we understand *now* to avoid searching\n   // later. (todo: could make this installable)\n   // the same regardless of glyph.\n   numTables = ttUSHORT(data + cmap + 2);\n   info->index_map = 0;\n   for (i=0; i < numTables; ++i) {\n      stbtt_uint32 encoding_record = cmap + 4 + 8 * i;\n      // find an encoding we understand:\n      switch(ttUSHORT(data+encoding_record)) {\n         case STBTT_PLATFORM_ID_MICROSOFT:\n            switch (ttUSHORT(data+encoding_record+2)) {\n               case STBTT_MS_EID_UNICODE_BMP:\n               case STBTT_MS_EID_UNICODE_FULL:\n                  // MS/Unicode\n                  info->index_map = cmap + ttULONG(data+encoding_record+4);\n                  break;\n            }\n            break;\n        case STBTT_PLATFORM_ID_UNICODE:\n            // Mac/iOS has these\n            // all the encodingIDs are unicode, so we don't bother to check it\n            info->index_map = cmap + ttULONG(data+encoding_record+4);\n            break;\n      }\n   }\n   if (info->index_map == 0)\n      return 0;\n\n   info->indexToLocFormat = ttUSHORT(data+info->head + 50);\n   return 1;\n}\n\nSTBTT_DEF int stbtt_FindGlyphIndex(const stbtt_fontinfo *info, int unicode_codepoint)\n{\n   stbtt_uint8 *data = info->data;\n   stbtt_uint32 index_map = info->index_map;\n\n   stbtt_uint16 format = ttUSHORT(data + index_map + 0);\n   if (format == 0) { // apple byte encoding\n      stbtt_int32 bytes = ttUSHORT(data + index_map + 2);\n      if (unicode_codepoint < bytes-6)\n         return ttBYTE(data + index_map + 6 + unicode_codepoint);\n      return 0;\n   } else if (format == 6) {\n      stbtt_uint32 first = ttUSHORT(data + index_map + 6);\n      stbtt_uint32 count = ttUSHORT(data + index_map + 8);\n      if ((stbtt_uint32) unicode_codepoint >= first && (stbtt_uint32) unicode_codepoint < first+count)\n         return ttUSHORT(data + index_map + 10 + (unicode_codepoint - first)*2);\n      return 0;\n   } else if (format == 2) {\n      STBTT_assert(0); // @TODO: high-byte mapping for japanese/chinese/korean\n      return 0;\n   } else if (format == 4) { // standard mapping for windows fonts: binary search collection of ranges\n      stbtt_uint16 segcount = ttUSHORT(data+index_map+6) >> 1;\n      stbtt_uint16 searchRange = ttUSHORT(data+index_map+8) >> 1;\n      stbtt_uint16 entrySelector = ttUSHORT(data+index_map+10);\n      stbtt_uint16 rangeShift = ttUSHORT(data+index_map+12) >> 1;\n\n      // do a binary search of the segments\n      stbtt_uint32 endCount = index_map + 14;\n      stbtt_uint32 search = endCount;\n\n      if (unicode_codepoint > 0xffff)\n         return 0;\n\n      // they lie from endCount .. endCount + segCount\n      // but searchRange is the nearest power of two, so...\n      if (unicode_codepoint >= ttUSHORT(data + search + rangeShift*2))\n         search += rangeShift*2;\n\n      // now decrement to bias correctly to find smallest\n      search -= 2;\n      while (entrySelector) {\n         stbtt_uint16 end;\n         searchRange >>= 1;\n         end = ttUSHORT(data + search + searchRange*2);\n         if (unicode_codepoint > end)\n            search += searchRange*2;\n         --entrySelector;\n      }\n      search += 2;\n\n      {\n         stbtt_uint16 offset, start;\n         stbtt_uint16 item = (stbtt_uint16) ((search - endCount) >> 1);\n\n         STBTT_assert(unicode_codepoint <= ttUSHORT(data + endCount + 2*item));\n         start = ttUSHORT(data + index_map + 14 + segcount*2 + 2 + 2*item);\n         if (unicode_codepoint < start)\n            return 0;\n\n         offset = ttUSHORT(data + index_map + 14 + segcount*6 + 2 + 2*item);\n         if (offset == 0)\n            return (stbtt_uint16) (unicode_codepoint + ttSHORT(data + index_map + 14 + segcount*4 + 2 + 2*item));\n\n         return ttUSHORT(data + offset + (unicode_codepoint-start)*2 + index_map + 14 + segcount*6 + 2 + 2*item);\n      }\n   } else if (format == 12 || format == 13) {\n      stbtt_uint32 ngroups = ttULONG(data+index_map+12);\n      stbtt_int32 low,high;\n      low = 0; high = (stbtt_int32)ngroups;\n      // Binary search the right group.\n      while (low < high) {\n         stbtt_int32 mid = low + ((high-low) >> 1); // rounds down, so low <= mid < high\n         stbtt_uint32 start_char = ttULONG(data+index_map+16+mid*12);\n         stbtt_uint32 end_char = ttULONG(data+index_map+16+mid*12+4);\n         if ((stbtt_uint32) unicode_codepoint < start_char)\n            high = mid;\n         else if ((stbtt_uint32) unicode_codepoint > end_char)\n            low = mid+1;\n         else {\n            stbtt_uint32 start_glyph = ttULONG(data+index_map+16+mid*12+8);\n            if (format == 12)\n               return start_glyph + unicode_codepoint-start_char;\n            else // format == 13\n               return start_glyph;\n         }\n      }\n      return 0; // not found\n   }\n   // @TODO\n   STBTT_assert(0);\n   return 0;\n}\n\nSTBTT_DEF int stbtt_GetCodepointShape(const stbtt_fontinfo *info, int unicode_codepoint, stbtt_vertex **vertices)\n{\n   return stbtt_GetGlyphShape(info, stbtt_FindGlyphIndex(info, unicode_codepoint), vertices);\n}\n\nstatic void stbtt_setvertex(stbtt_vertex *v, stbtt_uint8 type, stbtt_int32 x, stbtt_int32 y, stbtt_int32 cx, stbtt_int32 cy)\n{\n   v->type = type;\n   v->x = (stbtt_int16) x;\n   v->y = (stbtt_int16) y;\n   v->cx = (stbtt_int16) cx;\n   v->cy = (stbtt_int16) cy;\n}\n\nstatic int stbtt__GetGlyfOffset(const stbtt_fontinfo *info, int glyph_index)\n{\n   int g1,g2;\n\n   STBTT_assert(!info->cff.size);\n\n   if (glyph_index >= info->numGlyphs) return -1; // glyph index out of range\n   if (info->indexToLocFormat >= 2)    return -1; // unknown index->glyph map format\n\n   if (info->indexToLocFormat == 0) {\n      g1 = info->glyf + ttUSHORT(info->data + info->loca + glyph_index * 2) * 2;\n      g2 = info->glyf + ttUSHORT(info->data + info->loca + glyph_index * 2 + 2) * 2;\n   } else {\n      g1 = info->glyf + ttULONG (info->data + info->loca + glyph_index * 4);\n      g2 = info->glyf + ttULONG (info->data + info->loca + glyph_index * 4 + 4);\n   }\n\n   return g1==g2 ? -1 : g1; // if length is 0, return -1\n}\n\nstatic int stbtt__GetGlyphInfoT2(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1);\n\nSTBTT_DEF int stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1)\n{\n   if (info->cff.size) {\n      stbtt__GetGlyphInfoT2(info, glyph_index, x0, y0, x1, y1);\n   } else {\n      int g = stbtt__GetGlyfOffset(info, glyph_index);\n      if (g < 0) return 0;\n\n      if (x0) *x0 = ttSHORT(info->data + g + 2);\n      if (y0) *y0 = ttSHORT(info->data + g + 4);\n      if (x1) *x1 = ttSHORT(info->data + g + 6);\n      if (y1) *y1 = ttSHORT(info->data + g + 8);\n   }\n   return 1;\n}\n\nSTBTT_DEF int stbtt_GetCodepointBox(const stbtt_fontinfo *info, int codepoint, int *x0, int *y0, int *x1, int *y1)\n{\n   return stbtt_GetGlyphBox(info, stbtt_FindGlyphIndex(info,codepoint), x0,y0,x1,y1);\n}\n\nSTBTT_DEF int stbtt_IsGlyphEmpty(const stbtt_fontinfo *info, int glyph_index)\n{\n   stbtt_int16 numberOfContours;\n   int g;\n   if (info->cff.size)\n      return stbtt__GetGlyphInfoT2(info, glyph_index, NULL, NULL, NULL, NULL) == 0;\n   g = stbtt__GetGlyfOffset(info, glyph_index);\n   if (g < 0) return 1;\n   numberOfContours = ttSHORT(info->data + g);\n   return numberOfContours == 0;\n}\n\nstatic int stbtt__close_shape(stbtt_vertex *vertices, int num_vertices, int was_off, int start_off,\n    stbtt_int32 sx, stbtt_int32 sy, stbtt_int32 scx, stbtt_int32 scy, stbtt_int32 cx, stbtt_int32 cy)\n{\n   if (start_off) {\n      if (was_off)\n         stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, (cx+scx)>>1, (cy+scy)>>1, cx,cy);\n      stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, sx,sy,scx,scy);\n   } else {\n      if (was_off)\n         stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve,sx,sy,cx,cy);\n      else\n         stbtt_setvertex(&vertices[num_vertices++], STBTT_vline,sx,sy,0,0);\n   }\n   return num_vertices;\n}\n\nstatic int stbtt__GetGlyphShapeTT(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)\n{\n   stbtt_int16 numberOfContours;\n   stbtt_uint8 *endPtsOfContours;\n   stbtt_uint8 *data = info->data;\n   stbtt_vertex *vertices=0;\n   int num_vertices=0;\n   int g = stbtt__GetGlyfOffset(info, glyph_index);\n\n   *pvertices = NULL;\n\n   if (g < 0) return 0;\n\n   numberOfContours = ttSHORT(data + g);\n\n   if (numberOfContours > 0) {\n      stbtt_uint8 flags=0,flagcount;\n      stbtt_int32 ins, i,j=0,m,n, next_move, was_off=0, off, start_off=0;\n      stbtt_int32 x,y,cx,cy,sx,sy, scx,scy;\n      stbtt_uint8 *points;\n      endPtsOfContours = (data + g + 10);\n      ins = ttUSHORT(data + g + 10 + numberOfContours * 2);\n      points = data + g + 10 + numberOfContours * 2 + 2 + ins;\n\n      n = 1+ttUSHORT(endPtsOfContours + numberOfContours*2-2);\n\n      m = n + 2*numberOfContours;  // a loose bound on how many vertices we might need\n      vertices = (stbtt_vertex *) STBTT_malloc(m * sizeof(vertices[0]), info->userdata);\n      if (vertices == 0)\n         return 0;\n\n      next_move = 0;\n      flagcount=0;\n\n      // in first pass, we load uninterpreted data into the allocated array\n      // above, shifted to the end of the array so we won't overwrite it when\n      // we create our final data starting from the front\n\n      off = m - n; // starting offset for uninterpreted data, regardless of how m ends up being calculated\n\n      // first load flags\n\n      for (i=0; i < n; ++i) {\n         if (flagcount == 0) {\n            flags = *points++;\n            if (flags & 8)\n               flagcount = *points++;\n         } else\n            --flagcount;\n         vertices[off+i].type = flags;\n      }\n\n      // now load x coordinates\n      x=0;\n      for (i=0; i < n; ++i) {\n         flags = vertices[off+i].type;\n         if (flags & 2) {\n            stbtt_int16 dx = *points++;\n            x += (flags & 16) ? dx : -dx; // ???\n         } else {\n            if (!(flags & 16)) {\n               x = x + (stbtt_int16) (points[0]*256 + points[1]);\n               points += 2;\n            }\n         }\n         vertices[off+i].x = (stbtt_int16) x;\n      }\n\n      // now load y coordinates\n      y=0;\n      for (i=0; i < n; ++i) {\n         flags = vertices[off+i].type;\n         if (flags & 4) {\n            stbtt_int16 dy = *points++;\n            y += (flags & 32) ? dy : -dy; // ???\n         } else {\n            if (!(flags & 32)) {\n               y = y + (stbtt_int16) (points[0]*256 + points[1]);\n               points += 2;\n            }\n         }\n         vertices[off+i].y = (stbtt_int16) y;\n      }\n\n      // now convert them to our format\n      num_vertices=0;\n      sx = sy = cx = cy = scx = scy = 0;\n      for (i=0; i < n; ++i) {\n         flags = vertices[off+i].type;\n         x     = (stbtt_int16) vertices[off+i].x;\n         y     = (stbtt_int16) vertices[off+i].y;\n\n         if (next_move == i) {\n            if (i != 0)\n               num_vertices = stbtt__close_shape(vertices, num_vertices, was_off, start_off, sx,sy,scx,scy,cx,cy);\n\n            // now start the new one\n            start_off = !(flags & 1);\n            if (start_off) {\n               // if we start off with an off-curve point, then when we need to find a point on the curve\n               // where we can start, and we need to save some state for when we wraparound.\n               scx = x;\n               scy = y;\n               if (!(vertices[off+i+1].type & 1)) {\n                  // next point is also a curve point, so interpolate an on-point curve\n                  sx = (x + (stbtt_int32) vertices[off+i+1].x) >> 1;\n                  sy = (y + (stbtt_int32) vertices[off+i+1].y) >> 1;\n               } else {\n                  // otherwise just use the next point as our start point\n                  sx = (stbtt_int32) vertices[off+i+1].x;\n                  sy = (stbtt_int32) vertices[off+i+1].y;\n                  ++i; // we're using point i+1 as the starting point, so skip it\n               }\n            } else {\n               sx = x;\n               sy = y;\n            }\n            stbtt_setvertex(&vertices[num_vertices++], STBTT_vmove,sx,sy,0,0);\n            was_off = 0;\n            next_move = 1 + ttUSHORT(endPtsOfContours+j*2);\n            ++j;\n         } else {\n            if (!(flags & 1)) { // if it's a curve\n               if (was_off) // two off-curve control points in a row means interpolate an on-curve midpoint\n                  stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, (cx+x)>>1, (cy+y)>>1, cx, cy);\n               cx = x;\n               cy = y;\n               was_off = 1;\n            } else {\n               if (was_off)\n                  stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, x,y, cx, cy);\n               else\n                  stbtt_setvertex(&vertices[num_vertices++], STBTT_vline, x,y,0,0);\n               was_off = 0;\n            }\n         }\n      }\n      num_vertices = stbtt__close_shape(vertices, num_vertices, was_off, start_off, sx,sy,scx,scy,cx,cy);\n   } else if (numberOfContours < 0) {\n      // Compound shapes.\n      int more = 1;\n      stbtt_uint8 *comp = data + g + 10;\n      num_vertices = 0;\n      vertices = 0;\n      while (more) {\n         stbtt_uint16 flags, gidx;\n         int comp_num_verts = 0, i;\n         stbtt_vertex *comp_verts = 0, *tmp = 0;\n         float mtx[6] = {1,0,0,1,0,0}, m, n;\n\n         flags = ttSHORT(comp); comp+=2;\n         gidx = ttSHORT(comp); comp+=2;\n\n         if (flags & 2) { // XY values\n            if (flags & 1) { // shorts\n               mtx[4] = ttSHORT(comp); comp+=2;\n               mtx[5] = ttSHORT(comp); comp+=2;\n            } else {\n               mtx[4] = ttCHAR(comp); comp+=1;\n               mtx[5] = ttCHAR(comp); comp+=1;\n            }\n         }\n         else {\n            // @TODO handle matching point\n            STBTT_assert(0);\n         }\n         if (flags & (1<<3)) { // WE_HAVE_A_SCALE\n            mtx[0] = mtx[3] = ttSHORT(comp)/16384.0f; comp+=2;\n            mtx[1] = mtx[2] = 0;\n         } else if (flags & (1<<6)) { // WE_HAVE_AN_X_AND_YSCALE\n            mtx[0] = ttSHORT(comp)/16384.0f; comp+=2;\n            mtx[1] = mtx[2] = 0;\n            mtx[3] = ttSHORT(comp)/16384.0f; comp+=2;\n         } else if (flags & (1<<7)) { // WE_HAVE_A_TWO_BY_TWO\n            mtx[0] = ttSHORT(comp)/16384.0f; comp+=2;\n            mtx[1] = ttSHORT(comp)/16384.0f; comp+=2;\n            mtx[2] = ttSHORT(comp)/16384.0f; comp+=2;\n            mtx[3] = ttSHORT(comp)/16384.0f; comp+=2;\n         }\n\n         // Find transformation scales.\n         m = (float) STBTT_sqrt(mtx[0]*mtx[0] + mtx[1]*mtx[1]);\n         n = (float) STBTT_sqrt(mtx[2]*mtx[2] + mtx[3]*mtx[3]);\n\n         // Get indexed glyph.\n         comp_num_verts = stbtt_GetGlyphShape(info, gidx, &comp_verts);\n         if (comp_num_verts > 0) {\n            // Transform vertices.\n            for (i = 0; i < comp_num_verts; ++i) {\n               stbtt_vertex* v = &comp_verts[i];\n               stbtt_vertex_type x,y;\n               x=v->x; y=v->y;\n               v->x = (stbtt_vertex_type)(m * (mtx[0]*x + mtx[2]*y + mtx[4]));\n               v->y = (stbtt_vertex_type)(n * (mtx[1]*x + mtx[3]*y + mtx[5]));\n               x=v->cx; y=v->cy;\n               v->cx = (stbtt_vertex_type)(m * (mtx[0]*x + mtx[2]*y + mtx[4]));\n               v->cy = (stbtt_vertex_type)(n * (mtx[1]*x + mtx[3]*y + mtx[5]));\n            }\n            // Append vertices.\n            tmp = (stbtt_vertex*)STBTT_malloc((num_vertices+comp_num_verts)*sizeof(stbtt_vertex), info->userdata);\n            if (!tmp) {\n               if (vertices) STBTT_free(vertices, info->userdata);\n               if (comp_verts) STBTT_free(comp_verts, info->userdata);\n               return 0;\n            }\n            if (num_vertices > 0) STBTT_memcpy(tmp, vertices, num_vertices*sizeof(stbtt_vertex));\n            STBTT_memcpy(tmp+num_vertices, comp_verts, comp_num_verts*sizeof(stbtt_vertex));\n            if (vertices) STBTT_free(vertices, info->userdata);\n            vertices = tmp;\n            STBTT_free(comp_verts, info->userdata);\n            num_vertices += comp_num_verts;\n         }\n         // More components ?\n         more = flags & (1<<5);\n      }\n   } else {\n      // numberOfCounters == 0, do nothing\n   }\n\n   *pvertices = vertices;\n   return num_vertices;\n}\n\ntypedef struct\n{\n   int bounds;\n   int started;\n   float first_x, first_y;\n   float x, y;\n   stbtt_int32 min_x, max_x, min_y, max_y;\n\n   stbtt_vertex *pvertices;\n   int num_vertices;\n} stbtt__csctx;\n\n#define STBTT__CSCTX_INIT(bounds) {bounds,0, 0,0, 0,0, 0,0,0,0, NULL, 0}\n\nstatic void stbtt__track_vertex(stbtt__csctx *c, stbtt_int32 x, stbtt_int32 y)\n{\n   if (x > c->max_x || !c->started) c->max_x = x;\n   if (y > c->max_y || !c->started) c->max_y = y;\n   if (x < c->min_x || !c->started) c->min_x = x;\n   if (y < c->min_y || !c->started) c->min_y = y;\n   c->started = 1;\n}\n\nstatic void stbtt__csctx_v(stbtt__csctx *c, stbtt_uint8 type, stbtt_int32 x, stbtt_int32 y, stbtt_int32 cx, stbtt_int32 cy, stbtt_int32 cx1, stbtt_int32 cy1)\n{\n   if (c->bounds) {\n      stbtt__track_vertex(c, x, y);\n      if (type == STBTT_vcubic) {\n         stbtt__track_vertex(c, cx, cy);\n         stbtt__track_vertex(c, cx1, cy1);\n      }\n   } else {\n      stbtt_setvertex(&c->pvertices[c->num_vertices], type, x, y, cx, cy);\n      c->pvertices[c->num_vertices].cx1 = (stbtt_int16) cx1;\n      c->pvertices[c->num_vertices].cy1 = (stbtt_int16) cy1;\n   }\n   c->num_vertices++;\n}\n\nstatic void stbtt__csctx_close_shape(stbtt__csctx *ctx)\n{\n   if (ctx->first_x != ctx->x || ctx->first_y != ctx->y)\n      stbtt__csctx_v(ctx, STBTT_vline, (int)ctx->first_x, (int)ctx->first_y, 0, 0, 0, 0);\n}\n\nstatic void stbtt__csctx_rmove_to(stbtt__csctx *ctx, float dx, float dy)\n{\n   stbtt__csctx_close_shape(ctx);\n   ctx->first_x = ctx->x = ctx->x + dx;\n   ctx->first_y = ctx->y = ctx->y + dy;\n   stbtt__csctx_v(ctx, STBTT_vmove, (int)ctx->x, (int)ctx->y, 0, 0, 0, 0);\n}\n\nstatic void stbtt__csctx_rline_to(stbtt__csctx *ctx, float dx, float dy)\n{\n   ctx->x += dx;\n   ctx->y += dy;\n   stbtt__csctx_v(ctx, STBTT_vline, (int)ctx->x, (int)ctx->y, 0, 0, 0, 0);\n}\n\nstatic void stbtt__csctx_rccurve_to(stbtt__csctx *ctx, float dx1, float dy1, float dx2, float dy2, float dx3, float dy3)\n{\n   float cx1 = ctx->x + dx1;\n   float cy1 = ctx->y + dy1;\n   float cx2 = cx1 + dx2;\n   float cy2 = cy1 + dy2;\n   ctx->x = cx2 + dx3;\n   ctx->y = cy2 + dy3;\n   stbtt__csctx_v(ctx, STBTT_vcubic, (int)ctx->x, (int)ctx->y, (int)cx1, (int)cy1, (int)cx2, (int)cy2);\n}\n\nstatic stbtt__buf stbtt__get_subr(stbtt__buf idx, int n)\n{\n   int count = stbtt__cff_index_count(&idx);\n   int bias = 107;\n   if (count >= 33900)\n      bias = 32768;\n   else if (count >= 1240)\n      bias = 1131;\n   n += bias;\n   if (n < 0 || n >= count)\n      return stbtt__new_buf(NULL, 0);\n   return stbtt__cff_index_get(idx, n);\n}\n\nstatic stbtt__buf stbtt__cid_get_glyph_subrs(const stbtt_fontinfo *info, int glyph_index)\n{\n   stbtt__buf fdselect = info->fdselect;\n   int nranges, start, end, v, fmt, fdselector = -1, i;\n\n   stbtt__buf_seek(&fdselect, 0);\n   fmt = stbtt__buf_get8(&fdselect);\n   if (fmt == 0) {\n      // untested\n      stbtt__buf_skip(&fdselect, glyph_index);\n      fdselector = stbtt__buf_get8(&fdselect);\n   } else if (fmt == 3) {\n      nranges = stbtt__buf_get16(&fdselect);\n      start = stbtt__buf_get16(&fdselect);\n      for (i = 0; i < nranges; i++) {\n         v = stbtt__buf_get8(&fdselect);\n         end = stbtt__buf_get16(&fdselect);\n         if (glyph_index >= start && glyph_index < end) {\n            fdselector = v;\n            break;\n         }\n         start = end;\n      }\n   }\n   if (fdselector == -1) stbtt__new_buf(NULL, 0);\n   return stbtt__get_subrs(info->cff, stbtt__cff_index_get(info->fontdicts, fdselector));\n}\n\nstatic int stbtt__run_charstring(const stbtt_fontinfo *info, int glyph_index, stbtt__csctx *c)\n{\n   int in_header = 1, maskbits = 0, subr_stack_height = 0, sp = 0, v, i, b0;\n   int has_subrs = 0, clear_stack;\n   float s[48];\n   stbtt__buf subr_stack[10], subrs = info->subrs, b;\n   float f;\n\n#define STBTT__CSERR(s) (0)\n\n   // this currently ignores the initial width value, which isn't needed if we have hmtx\n   b = stbtt__cff_index_get(info->charstrings, glyph_index);\n   while (b.cursor < b.size) {\n      i = 0;\n      clear_stack = 1;\n      b0 = stbtt__buf_get8(&b);\n      switch (b0) {\n      // @TODO implement hinting\n      case 0x13: // hintmask\n      case 0x14: // cntrmask\n         if (in_header)\n            maskbits += (sp / 2); // implicit \"vstem\"\n         in_header = 0;\n         stbtt__buf_skip(&b, (maskbits + 7) / 8);\n         break;\n\n      case 0x01: // hstem\n      case 0x03: // vstem\n      case 0x12: // hstemhm\n      case 0x17: // vstemhm\n         maskbits += (sp / 2);\n         break;\n\n      case 0x15: // rmoveto\n         in_header = 0;\n         if (sp < 2) return STBTT__CSERR(\"rmoveto stack\");\n         stbtt__csctx_rmove_to(c, s[sp-2], s[sp-1]);\n         break;\n      case 0x04: // vmoveto\n         in_header = 0;\n         if (sp < 1) return STBTT__CSERR(\"vmoveto stack\");\n         stbtt__csctx_rmove_to(c, 0, s[sp-1]);\n         break;\n      case 0x16: // hmoveto\n         in_header = 0;\n         if (sp < 1) return STBTT__CSERR(\"hmoveto stack\");\n         stbtt__csctx_rmove_to(c, s[sp-1], 0);\n         break;\n\n      case 0x05: // rlineto\n         if (sp < 2) return STBTT__CSERR(\"rlineto stack\");\n         for (; i + 1 < sp; i += 2)\n            stbtt__csctx_rline_to(c, s[i], s[i+1]);\n         break;\n\n      // hlineto/vlineto and vhcurveto/hvcurveto alternate horizontal and vertical\n      // starting from a different place.\n\n      case 0x07: // vlineto\n         if (sp < 1) return STBTT__CSERR(\"vlineto stack\");\n         goto vlineto;\n      case 0x06: // hlineto\n         if (sp < 1) return STBTT__CSERR(\"hlineto stack\");\n         for (;;) {\n            if (i >= sp) break;\n            stbtt__csctx_rline_to(c, s[i], 0);\n            i++;\n      vlineto:\n            if (i >= sp) break;\n            stbtt__csctx_rline_to(c, 0, s[i]);\n            i++;\n         }\n         break;\n\n      case 0x1F: // hvcurveto\n         if (sp < 4) return STBTT__CSERR(\"hvcurveto stack\");\n         goto hvcurveto;\n      case 0x1E: // vhcurveto\n         if (sp < 4) return STBTT__CSERR(\"vhcurveto stack\");\n         for (;;) {\n            if (i + 3 >= sp) break;\n            stbtt__csctx_rccurve_to(c, 0, s[i], s[i+1], s[i+2], s[i+3], (sp - i == 5) ? s[i + 4] : 0.0f);\n            i += 4;\n      hvcurveto:\n            if (i + 3 >= sp) break;\n            stbtt__csctx_rccurve_to(c, s[i], 0, s[i+1], s[i+2], (sp - i == 5) ? s[i+4] : 0.0f, s[i+3]);\n            i += 4;\n         }\n         break;\n\n      case 0x08: // rrcurveto\n         if (sp < 6) return STBTT__CSERR(\"rcurveline stack\");\n         for (; i + 5 < sp; i += 6)\n            stbtt__csctx_rccurve_to(c, s[i], s[i+1], s[i+2], s[i+3], s[i+4], s[i+5]);\n         break;\n\n      case 0x18: // rcurveline\n         if (sp < 8) return STBTT__CSERR(\"rcurveline stack\");\n         for (; i + 5 < sp - 2; i += 6)\n            stbtt__csctx_rccurve_to(c, s[i], s[i+1], s[i+2], s[i+3], s[i+4], s[i+5]);\n         if (i + 1 >= sp) return STBTT__CSERR(\"rcurveline stack\");\n         stbtt__csctx_rline_to(c, s[i], s[i+1]);\n         break;\n\n      case 0x19: // rlinecurve\n         if (sp < 8) return STBTT__CSERR(\"rlinecurve stack\");\n         for (; i + 1 < sp - 6; i += 2)\n            stbtt__csctx_rline_to(c, s[i], s[i+1]);\n         if (i + 5 >= sp) return STBTT__CSERR(\"rlinecurve stack\");\n         stbtt__csctx_rccurve_to(c, s[i], s[i+1], s[i+2], s[i+3], s[i+4], s[i+5]);\n         break;\n\n      case 0x1A: // vvcurveto\n      case 0x1B: // hhcurveto\n         if (sp < 4) return STBTT__CSERR(\"(vv|hh)curveto stack\");\n         f = 0.0;\n         if (sp & 1) { f = s[i]; i++; }\n         for (; i + 3 < sp; i += 4) {\n            if (b0 == 0x1B)\n               stbtt__csctx_rccurve_to(c, s[i], f, s[i+1], s[i+2], s[i+3], 0.0);\n            else\n               stbtt__csctx_rccurve_to(c, f, s[i], s[i+1], s[i+2], 0.0, s[i+3]);\n            f = 0.0;\n         }\n         break;\n\n      case 0x0A: // callsubr\n         if (!has_subrs) {\n            if (info->fdselect.size)\n               subrs = stbtt__cid_get_glyph_subrs(info, glyph_index);\n            has_subrs = 1;\n         }\n         // fallthrough\n      case 0x1D: // callgsubr\n         if (sp < 1) return STBTT__CSERR(\"call(g|)subr stack\");\n         v = (int) s[--sp];\n         if (subr_stack_height >= 10) return STBTT__CSERR(\"recursion limit\");\n         subr_stack[subr_stack_height++] = b;\n         b = stbtt__get_subr(b0 == 0x0A ? subrs : info->gsubrs, v);\n         if (b.size == 0) return STBTT__CSERR(\"subr not found\");\n         b.cursor = 0;\n         clear_stack = 0;\n         break;\n\n      case 0x0B: // return\n         if (subr_stack_height <= 0) return STBTT__CSERR(\"return outside subr\");\n         b = subr_stack[--subr_stack_height];\n         clear_stack = 0;\n         break;\n\n      case 0x0E: // endchar\n         stbtt__csctx_close_shape(c);\n         return 1;\n\n      case 0x0C: { // two-byte escape\n         float dx1, dx2, dx3, dx4, dx5, dx6, dy1, dy2, dy3, dy4, dy5, dy6;\n         float dx, dy;\n         int b1 = stbtt__buf_get8(&b);\n         switch (b1) {\n         // @TODO These \"flex\" implementations ignore the flex-depth and resolution,\n         // and always draw beziers.\n         case 0x22: // hflex\n            if (sp < 7) return STBTT__CSERR(\"hflex stack\");\n            dx1 = s[0];\n            dx2 = s[1];\n            dy2 = s[2];\n            dx3 = s[3];\n            dx4 = s[4];\n            dx5 = s[5];\n            dx6 = s[6];\n            stbtt__csctx_rccurve_to(c, dx1, 0, dx2, dy2, dx3, 0);\n            stbtt__csctx_rccurve_to(c, dx4, 0, dx5, -dy2, dx6, 0);\n            break;\n\n         case 0x23: // flex\n            if (sp < 13) return STBTT__CSERR(\"flex stack\");\n            dx1 = s[0];\n            dy1 = s[1];\n            dx2 = s[2];\n            dy2 = s[3];\n            dx3 = s[4];\n            dy3 = s[5];\n            dx4 = s[6];\n            dy4 = s[7];\n            dx5 = s[8];\n            dy5 = s[9];\n            dx6 = s[10];\n            dy6 = s[11];\n            //fd is s[12]\n            stbtt__csctx_rccurve_to(c, dx1, dy1, dx2, dy2, dx3, dy3);\n            stbtt__csctx_rccurve_to(c, dx4, dy4, dx5, dy5, dx6, dy6);\n            break;\n\n         case 0x24: // hflex1\n            if (sp < 9) return STBTT__CSERR(\"hflex1 stack\");\n            dx1 = s[0];\n            dy1 = s[1];\n            dx2 = s[2];\n            dy2 = s[3];\n            dx3 = s[4];\n            dx4 = s[5];\n            dx5 = s[6];\n            dy5 = s[7];\n            dx6 = s[8];\n            stbtt__csctx_rccurve_to(c, dx1, dy1, dx2, dy2, dx3, 0);\n            stbtt__csctx_rccurve_to(c, dx4, 0, dx5, dy5, dx6, -(dy1+dy2+dy5));\n            break;\n\n         case 0x25: // flex1\n            if (sp < 11) return STBTT__CSERR(\"flex1 stack\");\n            dx1 = s[0];\n            dy1 = s[1];\n            dx2 = s[2];\n            dy2 = s[3];\n            dx3 = s[4];\n            dy3 = s[5];\n            dx4 = s[6];\n            dy4 = s[7];\n            dx5 = s[8];\n            dy5 = s[9];\n            dx6 = dy6 = s[10];\n            dx = dx1+dx2+dx3+dx4+dx5;\n            dy = dy1+dy2+dy3+dy4+dy5;\n            if (STBTT_fabs(dx) > STBTT_fabs(dy))\n               dy6 = -dy;\n            else\n               dx6 = -dx;\n            stbtt__csctx_rccurve_to(c, dx1, dy1, dx2, dy2, dx3, dy3);\n            stbtt__csctx_rccurve_to(c, dx4, dy4, dx5, dy5, dx6, dy6);\n            break;\n\n         default:\n            return STBTT__CSERR(\"unimplemented\");\n         }\n      } break;\n\n      default:\n         if (b0 != 255 && b0 != 28 && (b0 < 32 || b0 > 254))\n            return STBTT__CSERR(\"reserved operator\");\n\n         // push immediate\n         if (b0 == 255) {\n            f = (float)(stbtt_int32)stbtt__buf_get32(&b) / 0x10000;\n         } else {\n            stbtt__buf_skip(&b, -1);\n            f = (float)(stbtt_int16)stbtt__cff_int(&b);\n         }\n         if (sp >= 48) return STBTT__CSERR(\"push stack overflow\");\n         s[sp++] = f;\n         clear_stack = 0;\n         break;\n      }\n      if (clear_stack) sp = 0;\n   }\n   return STBTT__CSERR(\"no endchar\");\n\n#undef STBTT__CSERR\n}\n\nstatic int stbtt__GetGlyphShapeT2(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)\n{\n   // runs the charstring twice, once to count and once to output (to avoid realloc)\n   stbtt__csctx count_ctx = STBTT__CSCTX_INIT(1);\n   stbtt__csctx output_ctx = STBTT__CSCTX_INIT(0);\n   if (stbtt__run_charstring(info, glyph_index, &count_ctx)) {\n      *pvertices = (stbtt_vertex*)STBTT_malloc(count_ctx.num_vertices*sizeof(stbtt_vertex), info->userdata);\n      output_ctx.pvertices = *pvertices;\n      if (stbtt__run_charstring(info, glyph_index, &output_ctx)) {\n         STBTT_assert(output_ctx.num_vertices == count_ctx.num_vertices);\n         return output_ctx.num_vertices;\n      }\n   }\n   *pvertices = NULL;\n   return 0;\n}\n\nstatic int stbtt__GetGlyphInfoT2(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1)\n{\n   stbtt__csctx c = STBTT__CSCTX_INIT(1);\n   int r = stbtt__run_charstring(info, glyph_index, &c);\n   if (x0)  *x0 = r ? c.min_x : 0;\n   if (y0)  *y0 = r ? c.min_y : 0;\n   if (x1)  *x1 = r ? c.max_x : 0;\n   if (y1)  *y1 = r ? c.max_y : 0;\n   return r ? c.num_vertices : 0;\n}\n\nSTBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices)\n{\n   if (!info->cff.size)\n      return stbtt__GetGlyphShapeTT(info, glyph_index, pvertices);\n   else\n      return stbtt__GetGlyphShapeT2(info, glyph_index, pvertices);\n}\n\nSTBTT_DEF void stbtt_GetGlyphHMetrics(const stbtt_fontinfo *info, int glyph_index, int *advanceWidth, int *leftSideBearing)\n{\n   stbtt_uint16 numOfLongHorMetrics = ttUSHORT(info->data+info->hhea + 34);\n   if (glyph_index < numOfLongHorMetrics) {\n      if (advanceWidth)     *advanceWidth    = ttSHORT(info->data + info->hmtx + 4*glyph_index);\n      if (leftSideBearing)  *leftSideBearing = ttSHORT(info->data + info->hmtx + 4*glyph_index + 2);\n   } else {\n      if (advanceWidth)     *advanceWidth    = ttSHORT(info->data + info->hmtx + 4*(numOfLongHorMetrics-1));\n      if (leftSideBearing)  *leftSideBearing = ttSHORT(info->data + info->hmtx + 4*numOfLongHorMetrics + 2*(glyph_index - numOfLongHorMetrics));\n   }\n}\n\nSTBTT_DEF int  stbtt_GetKerningTableLength(const stbtt_fontinfo *info)\n{\n   stbtt_uint8 *data = info->data + info->kern;\n\n   // we only look at the first table. it must be 'horizontal' and format 0.\n   if (!info->kern)\n      return 0;\n   if (ttUSHORT(data+2) < 1) // number of tables, need at least 1\n      return 0;\n   if (ttUSHORT(data+8) != 1) // horizontal flag must be set in format\n      return 0;\n\n   return ttUSHORT(data+10);\n}\n\nSTBTT_DEF int stbtt_GetKerningTable(const stbtt_fontinfo *info, stbtt_kerningentry* table, int table_length)\n{\n   stbtt_uint8 *data = info->data + info->kern;\n   int k, length;\n\n   // we only look at the first table. it must be 'horizontal' and format 0.\n   if (!info->kern)\n      return 0;\n   if (ttUSHORT(data+2) < 1) // number of tables, need at least 1\n      return 0;\n   if (ttUSHORT(data+8) != 1) // horizontal flag must be set in format\n      return 0;\n\n   length = ttUSHORT(data+10);\n   if (table_length < length)\n      length = table_length;\n\n   for (k = 0; k < length; k++)\n   {\n      table[k].glyph1 = ttUSHORT(data+18+(k*6));\n      table[k].glyph2 = ttUSHORT(data+20+(k*6));\n      table[k].advance = ttSHORT(data+22+(k*6));\n   }\n\n   return length;\n}\n\nstatic int  stbtt__GetGlyphKernInfoAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2)\n{\n   stbtt_uint8 *data = info->data + info->kern;\n   stbtt_uint32 needle, straw;\n   int l, r, m;\n\n   // we only look at the first table. it must be 'horizontal' and format 0.\n   if (!info->kern)\n      return 0;\n   if (ttUSHORT(data+2) < 1) // number of tables, need at least 1\n      return 0;\n   if (ttUSHORT(data+8) != 1) // horizontal flag must be set in format\n      return 0;\n\n   l = 0;\n   r = ttUSHORT(data+10) - 1;\n   needle = glyph1 << 16 | glyph2;\n   while (l <= r) {\n      m = (l + r) >> 1;\n      straw = ttULONG(data+18+(m*6)); // note: unaligned read\n      if (needle < straw)\n         r = m - 1;\n      else if (needle > straw)\n         l = m + 1;\n      else\n         return ttSHORT(data+22+(m*6));\n   }\n   return 0;\n}\n\nstatic stbtt_int32  stbtt__GetCoverageIndex(stbtt_uint8 *coverageTable, int glyph)\n{\n    stbtt_uint16 coverageFormat = ttUSHORT(coverageTable);\n    switch(coverageFormat) {\n        case 1: {\n            stbtt_uint16 glyphCount = ttUSHORT(coverageTable + 2);\n\n            // Binary search.\n            stbtt_int32 l=0, r=glyphCount-1, m;\n            int straw, needle=glyph;\n            while (l <= r) {\n                stbtt_uint8 *glyphArray = coverageTable + 4;\n                stbtt_uint16 glyphID;\n                m = (l + r) >> 1;\n                glyphID = ttUSHORT(glyphArray + 2 * m);\n                straw = glyphID;\n                if (needle < straw)\n                    r = m - 1;\n                else if (needle > straw)\n                    l = m + 1;\n                else {\n                     return m;\n                }\n            }\n        } break;\n\n        case 2: {\n            stbtt_uint16 rangeCount = ttUSHORT(coverageTable + 2);\n            stbtt_uint8 *rangeArray = coverageTable + 4;\n\n            // Binary search.\n            stbtt_int32 l=0, r=rangeCount-1, m;\n            int strawStart, strawEnd, needle=glyph;\n            while (l <= r) {\n                stbtt_uint8 *rangeRecord;\n                m = (l + r) >> 1;\n                rangeRecord = rangeArray + 6 * m;\n                strawStart = ttUSHORT(rangeRecord);\n                strawEnd = ttUSHORT(rangeRecord + 2);\n                if (needle < strawStart)\n                    r = m - 1;\n                else if (needle > strawEnd)\n                    l = m + 1;\n                else {\n                    stbtt_uint16 startCoverageIndex = ttUSHORT(rangeRecord + 4);\n                    return startCoverageIndex + glyph - strawStart;\n                }\n            }\n        } break;\n\n        default: {\n            // There are no other cases.\n            STBTT_assert(0);\n        } break;\n    }\n\n    return -1;\n}\n\nstatic stbtt_int32  stbtt__GetGlyphClass(stbtt_uint8 *classDefTable, int glyph)\n{\n    stbtt_uint16 classDefFormat = ttUSHORT(classDefTable);\n    switch(classDefFormat)\n    {\n        case 1: {\n            stbtt_uint16 startGlyphID = ttUSHORT(classDefTable + 2);\n            stbtt_uint16 glyphCount = ttUSHORT(classDefTable + 4);\n            stbtt_uint8 *classDef1ValueArray = classDefTable + 6;\n\n            if (glyph >= startGlyphID && glyph < startGlyphID + glyphCount)\n                return (stbtt_int32)ttUSHORT(classDef1ValueArray + 2 * (glyph - startGlyphID));\n\n            classDefTable = classDef1ValueArray + 2 * glyphCount;\n        } break;\n\n        case 2: {\n            stbtt_uint16 classRangeCount = ttUSHORT(classDefTable + 2);\n            stbtt_uint8 *classRangeRecords = classDefTable + 4;\n\n            // Binary search.\n            stbtt_int32 l=0, r=classRangeCount-1, m;\n            int strawStart, strawEnd, needle=glyph;\n            while (l <= r) {\n                stbtt_uint8 *classRangeRecord;\n                m = (l + r) >> 1;\n                classRangeRecord = classRangeRecords + 6 * m;\n                strawStart = ttUSHORT(classRangeRecord);\n                strawEnd = ttUSHORT(classRangeRecord + 2);\n                if (needle < strawStart)\n                    r = m - 1;\n                else if (needle > strawEnd)\n                    l = m + 1;\n                else\n                    return (stbtt_int32)ttUSHORT(classRangeRecord + 4);\n            }\n\n            classDefTable = classRangeRecords + 6 * classRangeCount;\n        } break;\n\n        default: {\n            // There are no other cases.\n            STBTT_assert(0);\n        } break;\n    }\n\n    return -1;\n}\n\n// Define to STBTT_assert(x) if you want to break on unimplemented formats.\n#define STBTT_GPOS_TODO_assert(x)\n\nstatic stbtt_int32  stbtt__GetGlyphGPOSInfoAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2)\n{\n    stbtt_uint16 lookupListOffset;\n    stbtt_uint8 *lookupList;\n    stbtt_uint16 lookupCount;\n    stbtt_uint8 *data;\n    stbtt_int32 i;\n\n    if (!info->gpos) return 0;\n\n    data = info->data + info->gpos;\n\n    if (ttUSHORT(data+0) != 1) return 0; // Major version 1\n    if (ttUSHORT(data+2) != 0) return 0; // Minor version 0\n\n    lookupListOffset = ttUSHORT(data+8);\n    lookupList = data + lookupListOffset;\n    lookupCount = ttUSHORT(lookupList);\n\n    for (i=0; i<lookupCount; ++i) {\n        stbtt_uint16 lookupOffset = ttUSHORT(lookupList + 2 + 2 * i);\n        stbtt_uint8 *lookupTable = lookupList + lookupOffset;\n\n        stbtt_uint16 lookupType = ttUSHORT(lookupTable);\n        stbtt_uint16 subTableCount = ttUSHORT(lookupTable + 4);\n        stbtt_uint8 *subTableOffsets = lookupTable + 6;\n        switch(lookupType) {\n            case 2: { // Pair Adjustment Positioning Subtable\n                stbtt_int32 sti;\n                for (sti=0; sti<subTableCount; sti++) {\n                    stbtt_uint16 subtableOffset = ttUSHORT(subTableOffsets + 2 * sti);\n                    stbtt_uint8 *table = lookupTable + subtableOffset;\n                    stbtt_uint16 posFormat = ttUSHORT(table);\n                    stbtt_uint16 coverageOffset = ttUSHORT(table + 2);\n                    stbtt_int32 coverageIndex = stbtt__GetCoverageIndex(table + coverageOffset, glyph1);\n                    if (coverageIndex == -1) continue;\n\n                    switch (posFormat) {\n                        case 1: {\n                            stbtt_int32 l, r, m;\n                            int straw, needle;\n                            stbtt_uint16 valueFormat1 = ttUSHORT(table + 4);\n                            stbtt_uint16 valueFormat2 = ttUSHORT(table + 6);\n                            stbtt_int32 valueRecordPairSizeInBytes = 2;\n                            stbtt_uint16 pairSetCount = ttUSHORT(table + 8);\n                            stbtt_uint16 pairPosOffset = ttUSHORT(table + 10 + 2 * coverageIndex);\n                            stbtt_uint8 *pairValueTable = table + pairPosOffset;\n                            stbtt_uint16 pairValueCount = ttUSHORT(pairValueTable);\n                            stbtt_uint8 *pairValueArray = pairValueTable + 2;\n                            // TODO: Support more formats.\n                            STBTT_GPOS_TODO_assert(valueFormat1 == 4);\n                            if (valueFormat1 != 4) return 0;\n                            STBTT_GPOS_TODO_assert(valueFormat2 == 0);\n                            if (valueFormat2 != 0) return 0;\n\n                            STBTT_assert(coverageIndex < pairSetCount);\n                            STBTT__NOTUSED(pairSetCount);\n\n                            needle=glyph2;\n                            r=pairValueCount-1;\n                            l=0;\n\n                            // Binary search.\n                            while (l <= r) {\n                                stbtt_uint16 secondGlyph;\n                                stbtt_uint8 *pairValue;\n                                m = (l + r) >> 1;\n                                pairValue = pairValueArray + (2 + valueRecordPairSizeInBytes) * m;\n                                secondGlyph = ttUSHORT(pairValue);\n                                straw = secondGlyph;\n                                if (needle < straw)\n                                    r = m - 1;\n                                else if (needle > straw)\n                                    l = m + 1;\n                                else {\n                                    stbtt_int16 xAdvance = ttSHORT(pairValue + 2);\n                                    return xAdvance;\n                                }\n                            }\n                        } break;\n\n                        case 2: {\n                            stbtt_uint16 valueFormat1 = ttUSHORT(table + 4);\n                            stbtt_uint16 valueFormat2 = ttUSHORT(table + 6);\n\n                            stbtt_uint16 classDef1Offset = ttUSHORT(table + 8);\n                            stbtt_uint16 classDef2Offset = ttUSHORT(table + 10);\n                            int glyph1class = stbtt__GetGlyphClass(table + classDef1Offset, glyph1);\n                            int glyph2class = stbtt__GetGlyphClass(table + classDef2Offset, glyph2);\n\n                            stbtt_uint16 class1Count = ttUSHORT(table + 12);\n                            stbtt_uint16 class2Count = ttUSHORT(table + 14);\n                            STBTT_assert(glyph1class < class1Count);\n                            STBTT_assert(glyph2class < class2Count);\n\n                            // TODO: Support more formats.\n                            STBTT_GPOS_TODO_assert(valueFormat1 == 4);\n                            if (valueFormat1 != 4) return 0;\n                            STBTT_GPOS_TODO_assert(valueFormat2 == 0);\n                            if (valueFormat2 != 0) return 0;\n\n                            if (glyph1class >= 0 && glyph1class < class1Count && glyph2class >= 0 && glyph2class < class2Count) {\n                                stbtt_uint8 *class1Records = table + 16;\n                                stbtt_uint8 *class2Records = class1Records + 2 * (glyph1class * class2Count);\n                                stbtt_int16 xAdvance = ttSHORT(class2Records + 2 * glyph2class);\n                                return xAdvance;\n                            }\n                        } break;\n\n                        default: {\n                            // There are no other cases.\n                            STBTT_assert(0);\n                            break;\n                        };\n                    }\n                }\n                break;\n            };\n\n            default:\n                // TODO: Implement other stuff.\n                break;\n        }\n    }\n\n    return 0;\n}\n\nSTBTT_DEF int  stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int g1, int g2)\n{\n   int xAdvance = 0;\n\n   if (info->gpos)\n      xAdvance += stbtt__GetGlyphGPOSInfoAdvance(info, g1, g2);\n   else if (info->kern)\n      xAdvance += stbtt__GetGlyphKernInfoAdvance(info, g1, g2);\n\n   return xAdvance;\n}\n\nSTBTT_DEF int  stbtt_GetCodepointKernAdvance(const stbtt_fontinfo *info, int ch1, int ch2)\n{\n   if (!info->kern && !info->gpos) // if no kerning table, don't waste time looking up both codepoint->glyphs\n      return 0;\n   return stbtt_GetGlyphKernAdvance(info, stbtt_FindGlyphIndex(info,ch1), stbtt_FindGlyphIndex(info,ch2));\n}\n\nSTBTT_DEF void stbtt_GetCodepointHMetrics(const stbtt_fontinfo *info, int codepoint, int *advanceWidth, int *leftSideBearing)\n{\n   stbtt_GetGlyphHMetrics(info, stbtt_FindGlyphIndex(info,codepoint), advanceWidth, leftSideBearing);\n}\n\nSTBTT_DEF void stbtt_GetFontVMetrics(const stbtt_fontinfo *info, int *ascent, int *descent, int *lineGap)\n{\n   if (ascent ) *ascent  = ttSHORT(info->data+info->hhea + 4);\n   if (descent) *descent = ttSHORT(info->data+info->hhea + 6);\n   if (lineGap) *lineGap = ttSHORT(info->data+info->hhea + 8);\n}\n\nSTBTT_DEF int  stbtt_GetFontVMetricsOS2(const stbtt_fontinfo *info, int *typoAscent, int *typoDescent, int *typoLineGap)\n{\n   int tab = stbtt__find_table(info->data, info->fontstart, \"OS/2\");\n   if (!tab)\n      return 0;\n   if (typoAscent ) *typoAscent  = ttSHORT(info->data+tab + 68);\n   if (typoDescent) *typoDescent = ttSHORT(info->data+tab + 70);\n   if (typoLineGap) *typoLineGap = ttSHORT(info->data+tab + 72);\n   return 1;\n}\n\nSTBTT_DEF void stbtt_GetFontBoundingBox(const stbtt_fontinfo *info, int *x0, int *y0, int *x1, int *y1)\n{\n   *x0 = ttSHORT(info->data + info->head + 36);\n   *y0 = ttSHORT(info->data + info->head + 38);\n   *x1 = ttSHORT(info->data + info->head + 40);\n   *y1 = ttSHORT(info->data + info->head + 42);\n}\n\nSTBTT_DEF float stbtt_ScaleForPixelHeight(const stbtt_fontinfo *info, float height)\n{\n   int fheight = ttSHORT(info->data + info->hhea + 4) - ttSHORT(info->data + info->hhea + 6);\n   return (float) height / fheight;\n}\n\nSTBTT_DEF float stbtt_ScaleForMappingEmToPixels(const stbtt_fontinfo *info, float pixels)\n{\n   int unitsPerEm = ttUSHORT(info->data + info->head + 18);\n   return pixels / unitsPerEm;\n}\n\nSTBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *v)\n{\n   STBTT_free(v, info->userdata);\n}\n\nSTBTT_DEF stbtt_uint8 *stbtt_FindSVGDoc(const stbtt_fontinfo *info, int gl)\n{\n   int i;\n   stbtt_uint8 *data = info->data;\n   stbtt_uint8 *svg_doc_list = data + stbtt__get_svg((stbtt_fontinfo *) info);\n\n   int numEntries = ttUSHORT(svg_doc_list);\n   stbtt_uint8 *svg_docs = svg_doc_list + 2;\n\n   for(i=0; i<numEntries; i++) {\n      stbtt_uint8 *svg_doc = svg_docs + (12 * i);\n      if ((gl >= ttUSHORT(svg_doc)) && (gl <= ttUSHORT(svg_doc + 2)))\n         return svg_doc;\n   }\n   return 0;\n}\n\nSTBTT_DEF int stbtt_GetGlyphSVG(const stbtt_fontinfo *info, int gl, const char **svg)\n{\n   stbtt_uint8 *data = info->data;\n   stbtt_uint8 *svg_doc;\n\n   if (info->svg == 0)\n      return 0;\n\n   svg_doc = stbtt_FindSVGDoc(info, gl);\n   if (svg_doc != NULL) {\n      *svg = (char *) data + info->svg + ttULONG(svg_doc + 4);\n      return ttULONG(svg_doc + 8);\n   } else {\n      return 0;\n   }\n}\n\nSTBTT_DEF int stbtt_GetCodepointSVG(const stbtt_fontinfo *info, int unicode_codepoint, const char **svg)\n{\n   return stbtt_GetGlyphSVG(info, stbtt_FindGlyphIndex(info, unicode_codepoint), svg);\n}\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// antialiasing software rasterizer\n//\n\nSTBTT_DEF void stbtt_GetGlyphBitmapBoxSubpixel(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y,float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1)\n{\n   int x0=0,y0=0,x1,y1; // =0 suppresses compiler warning\n   if (!stbtt_GetGlyphBox(font, glyph, &x0,&y0,&x1,&y1)) {\n      // e.g. space character\n      if (ix0) *ix0 = 0;\n      if (iy0) *iy0 = 0;\n      if (ix1) *ix1 = 0;\n      if (iy1) *iy1 = 0;\n   } else {\n      // move to integral bboxes (treating pixels as little squares, what pixels get touched)?\n      if (ix0) *ix0 = STBTT_ifloor( x0 * scale_x + shift_x);\n      if (iy0) *iy0 = STBTT_ifloor(-y1 * scale_y + shift_y);\n      if (ix1) *ix1 = STBTT_iceil ( x1 * scale_x + shift_x);\n      if (iy1) *iy1 = STBTT_iceil (-y0 * scale_y + shift_y);\n   }\n}\n\nSTBTT_DEF void stbtt_GetGlyphBitmapBox(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1)\n{\n   stbtt_GetGlyphBitmapBoxSubpixel(font, glyph, scale_x, scale_y,0.0f,0.0f, ix0, iy0, ix1, iy1);\n}\n\nSTBTT_DEF void stbtt_GetCodepointBitmapBoxSubpixel(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1)\n{\n   stbtt_GetGlyphBitmapBoxSubpixel(font, stbtt_FindGlyphIndex(font,codepoint), scale_x, scale_y,shift_x,shift_y, ix0,iy0,ix1,iy1);\n}\n\nSTBTT_DEF void stbtt_GetCodepointBitmapBox(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1)\n{\n   stbtt_GetCodepointBitmapBoxSubpixel(font, codepoint, scale_x, scale_y,0.0f,0.0f, ix0,iy0,ix1,iy1);\n}\n\n//////////////////////////////////////////////////////////////////////////////\n//\n//  Rasterizer\n\ntypedef struct stbtt__hheap_chunk\n{\n   struct stbtt__hheap_chunk *next;\n} stbtt__hheap_chunk;\n\ntypedef struct stbtt__hheap\n{\n   struct stbtt__hheap_chunk *head;\n   void   *first_free;\n   int    num_remaining_in_head_chunk;\n} stbtt__hheap;\n\nstatic void *stbtt__hheap_alloc(stbtt__hheap *hh, size_t size, void *userdata)\n{\n   if (hh->first_free) {\n      void *p = hh->first_free;\n      hh->first_free = * (void **) p;\n      return p;\n   } else {\n      if (hh->num_remaining_in_head_chunk == 0) {\n         int count = (size < 32 ? 2000 : size < 128 ? 800 : 100);\n         stbtt__hheap_chunk *c = (stbtt__hheap_chunk *) STBTT_malloc(sizeof(stbtt__hheap_chunk) + size * count, userdata);\n         if (c == NULL)\n            return NULL;\n         c->next = hh->head;\n         hh->head = c;\n         hh->num_remaining_in_head_chunk = count;\n      }\n      --hh->num_remaining_in_head_chunk;\n      return (char *) (hh->head) + sizeof(stbtt__hheap_chunk) + size * hh->num_remaining_in_head_chunk;\n   }\n}\n\nstatic void stbtt__hheap_free(stbtt__hheap *hh, void *p)\n{\n   *(void **) p = hh->first_free;\n   hh->first_free = p;\n}\n\nstatic void stbtt__hheap_cleanup(stbtt__hheap *hh, void *userdata)\n{\n   stbtt__hheap_chunk *c = hh->head;\n   while (c) {\n      stbtt__hheap_chunk *n = c->next;\n      STBTT_free(c, userdata);\n      c = n;\n   }\n}\n\ntypedef struct stbtt__edge {\n   float x0,y0, x1,y1;\n   int invert;\n} stbtt__edge;\n\n\ntypedef struct stbtt__active_edge\n{\n   struct stbtt__active_edge *next;\n   #if STBTT_RASTERIZER_VERSION==1\n   int x,dx;\n   float ey;\n   int direction;\n   #elif STBTT_RASTERIZER_VERSION==2\n   float fx,fdx,fdy;\n   float direction;\n   float sy;\n   float ey;\n   #else\n   #error \"Unrecognized value of STBTT_RASTERIZER_VERSION\"\n   #endif\n} stbtt__active_edge;\n\n#if STBTT_RASTERIZER_VERSION == 1\n#define STBTT_FIXSHIFT   10\n#define STBTT_FIX        (1 << STBTT_FIXSHIFT)\n#define STBTT_FIXMASK    (STBTT_FIX-1)\n\nstatic stbtt__active_edge *stbtt__new_active(stbtt__hheap *hh, stbtt__edge *e, int off_x, float start_point, void *userdata)\n{\n   stbtt__active_edge *z = (stbtt__active_edge *) stbtt__hheap_alloc(hh, sizeof(*z), userdata);\n   float dxdy = (e->x1 - e->x0) / (e->y1 - e->y0);\n   STBTT_assert(z != NULL);\n   if (!z) return z;\n\n   // round dx down to avoid overshooting\n   if (dxdy < 0)\n      z->dx = -STBTT_ifloor(STBTT_FIX * -dxdy);\n   else\n      z->dx = STBTT_ifloor(STBTT_FIX * dxdy);\n\n   z->x = STBTT_ifloor(STBTT_FIX * e->x0 + z->dx * (start_point - e->y0)); // use z->dx so when we offset later it's by the same amount\n   z->x -= off_x * STBTT_FIX;\n\n   z->ey = e->y1;\n   z->next = 0;\n   z->direction = e->invert ? 1 : -1;\n   return z;\n}\n#elif STBTT_RASTERIZER_VERSION == 2\nstatic stbtt__active_edge *stbtt__new_active(stbtt__hheap *hh, stbtt__edge *e, int off_x, float start_point, void *userdata)\n{\n   stbtt__active_edge *z = (stbtt__active_edge *) stbtt__hheap_alloc(hh, sizeof(*z), userdata);\n   float dxdy = (e->x1 - e->x0) / (e->y1 - e->y0);\n   STBTT_assert(z != NULL);\n   //STBTT_assert(e->y0 <= start_point);\n   if (!z) return z;\n   z->fdx = dxdy;\n   z->fdy = dxdy != 0.0f ? (1.0f/dxdy) : 0.0f;\n   z->fx = e->x0 + dxdy * (start_point - e->y0);\n   z->fx -= off_x;\n   z->direction = e->invert ? 1.0f : -1.0f;\n   z->sy = e->y0;\n   z->ey = e->y1;\n   z->next = 0;\n   return z;\n}\n#else\n#error \"Unrecognized value of STBTT_RASTERIZER_VERSION\"\n#endif\n\n#if STBTT_RASTERIZER_VERSION == 1\n// note: this routine clips fills that extend off the edges... ideally this\n// wouldn't happen, but it could happen if the truetype glyph bounding boxes\n// are wrong, or if the user supplies a too-small bitmap\nstatic void stbtt__fill_active_edges(unsigned char *scanline, int len, stbtt__active_edge *e, int max_weight)\n{\n   // non-zero winding fill\n   int x0=0, w=0;\n\n   while (e) {\n      if (w == 0) {\n         // if we're currently at zero, we need to record the edge start point\n         x0 = e->x; w += e->direction;\n      } else {\n         int x1 = e->x; w += e->direction;\n         // if we went to zero, we need to draw\n         if (w == 0) {\n            int i = x0 >> STBTT_FIXSHIFT;\n            int j = x1 >> STBTT_FIXSHIFT;\n\n            if (i < len && j >= 0) {\n               if (i == j) {\n                  // x0,x1 are the same pixel, so compute combined coverage\n                  scanline[i] = scanline[i] + (stbtt_uint8) ((x1 - x0) * max_weight >> STBTT_FIXSHIFT);\n               } else {\n                  if (i >= 0) // add antialiasing for x0\n                     scanline[i] = scanline[i] + (stbtt_uint8) (((STBTT_FIX - (x0 & STBTT_FIXMASK)) * max_weight) >> STBTT_FIXSHIFT);\n                  else\n                     i = -1; // clip\n\n                  if (j < len) // add antialiasing for x1\n                     scanline[j] = scanline[j] + (stbtt_uint8) (((x1 & STBTT_FIXMASK) * max_weight) >> STBTT_FIXSHIFT);\n                  else\n                     j = len; // clip\n\n                  for (++i; i < j; ++i) // fill pixels between x0 and x1\n                     scanline[i] = scanline[i] + (stbtt_uint8) max_weight;\n               }\n            }\n         }\n      }\n\n      e = e->next;\n   }\n}\n\nstatic void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e, int n, int vsubsample, int off_x, int off_y, void *userdata)\n{\n   stbtt__hheap hh = { 0, 0, 0 };\n   stbtt__active_edge *active = NULL;\n   int y,j=0;\n   int max_weight = (255 / vsubsample);  // weight per vertical scanline\n   int s; // vertical subsample index\n   unsigned char scanline_data[512], *scanline;\n\n   if (result->w > 512)\n      scanline = (unsigned char *) STBTT_malloc(result->w, userdata);\n   else\n      scanline = scanline_data;\n\n   y = off_y * vsubsample;\n   e[n].y0 = (off_y + result->h) * (float) vsubsample + 1;\n\n   while (j < result->h) {\n      STBTT_memset(scanline, 0, result->w);\n      for (s=0; s < vsubsample; ++s) {\n         // find center of pixel for this scanline\n         float scan_y = y + 0.5f;\n         stbtt__active_edge **step = &active;\n\n         // update all active edges;\n         // remove all active edges that terminate before the center of this scanline\n         while (*step) {\n            stbtt__active_edge * z = *step;\n            if (z->ey <= scan_y) {\n               *step = z->next; // delete from list\n               STBTT_assert(z->direction);\n               z->direction = 0;\n               stbtt__hheap_free(&hh, z);\n            } else {\n               z->x += z->dx; // advance to position for current scanline\n               step = &((*step)->next); // advance through list\n            }\n         }\n\n         // resort the list if needed\n         for(;;) {\n            int changed=0;\n            step = &active;\n            while (*step && (*step)->next) {\n               if ((*step)->x > (*step)->next->x) {\n                  stbtt__active_edge *t = *step;\n                  stbtt__active_edge *q = t->next;\n\n                  t->next = q->next;\n                  q->next = t;\n                  *step = q;\n                  changed = 1;\n               }\n               step = &(*step)->next;\n            }\n            if (!changed) break;\n         }\n\n         // insert all edges that start before the center of this scanline -- omit ones that also end on this scanline\n         while (e->y0 <= scan_y) {\n            if (e->y1 > scan_y) {\n               stbtt__active_edge *z = stbtt__new_active(&hh, e, off_x, scan_y, userdata);\n               if (z != NULL) {\n                  // find insertion point\n                  if (active == NULL)\n                     active = z;\n                  else if (z->x < active->x) {\n                     // insert at front\n                     z->next = active;\n                     active = z;\n                  } else {\n                     // find thing to insert AFTER\n                     stbtt__active_edge *p = active;\n                     while (p->next && p->next->x < z->x)\n                        p = p->next;\n                     // at this point, p->next->x is NOT < z->x\n                     z->next = p->next;\n                     p->next = z;\n                  }\n               }\n            }\n            ++e;\n         }\n\n         // now process all active edges in XOR fashion\n         if (active)\n            stbtt__fill_active_edges(scanline, result->w, active, max_weight);\n\n         ++y;\n      }\n      STBTT_memcpy(result->pixels + j * result->stride, scanline, result->w);\n      ++j;\n   }\n\n   stbtt__hheap_cleanup(&hh, userdata);\n\n   if (scanline != scanline_data)\n      STBTT_free(scanline, userdata);\n}\n\n#elif STBTT_RASTERIZER_VERSION == 2\n\n// the edge passed in here does not cross the vertical line at x or the vertical line at x+1\n// (i.e. it has already been clipped to those)\nstatic void stbtt__handle_clipped_edge(float *scanline, int x, stbtt__active_edge *e, float x0, float y0, float x1, float y1)\n{\n   if (y0 == y1) return;\n   STBTT_assert(y0 < y1);\n   STBTT_assert(e->sy <= e->ey);\n   if (y0 > e->ey) return;\n   if (y1 < e->sy) return;\n   if (y0 < e->sy) {\n      x0 += (x1-x0) * (e->sy - y0) / (y1-y0);\n      y0 = e->sy;\n   }\n   if (y1 > e->ey) {\n      x1 += (x1-x0) * (e->ey - y1) / (y1-y0);\n      y1 = e->ey;\n   }\n\n   if (x0 == x)\n      STBTT_assert(x1 <= x+1);\n   else if (x0 == x+1)\n      STBTT_assert(x1 >= x);\n   else if (x0 <= x)\n      STBTT_assert(x1 <= x);\n   else if (x0 >= x+1)\n      STBTT_assert(x1 >= x+1);\n   else\n      STBTT_assert(x1 >= x && x1 <= x+1);\n\n   if (x0 <= x && x1 <= x)\n      scanline[x] += e->direction * (y1-y0);\n   else if (x0 >= x+1 && x1 >= x+1)\n      ;\n   else {\n      STBTT_assert(x0 >= x && x0 <= x+1 && x1 >= x && x1 <= x+1);\n      scanline[x] += e->direction * (y1-y0) * (1-((x0-x)+(x1-x))/2); // coverage = 1 - average x position\n   }\n}\n\nstatic void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill, int len, stbtt__active_edge *e, float y_top)\n{\n   float y_bottom = y_top+1;\n\n   while (e) {\n      // brute force every pixel\n\n      // compute intersection points with top & bottom\n      STBTT_assert(e->ey >= y_top);\n\n      if (e->fdx == 0) {\n         float x0 = e->fx;\n         if (x0 < len) {\n            if (x0 >= 0) {\n               stbtt__handle_clipped_edge(scanline,(int) x0,e, x0,y_top, x0,y_bottom);\n               stbtt__handle_clipped_edge(scanline_fill-1,(int) x0+1,e, x0,y_top, x0,y_bottom);\n            } else {\n               stbtt__handle_clipped_edge(scanline_fill-1,0,e, x0,y_top, x0,y_bottom);\n            }\n         }\n      } else {\n         float x0 = e->fx;\n         float dx = e->fdx;\n         float xb = x0 + dx;\n         float x_top, x_bottom;\n         float sy0,sy1;\n         float dy = e->fdy;\n         STBTT_assert(e->sy <= y_bottom && e->ey >= y_top);\n\n         // compute endpoints of line segment clipped to this scanline (if the\n         // line segment starts on this scanline. x0 is the intersection of the\n         // line with y_top, but that may be off the line segment.\n         if (e->sy > y_top) {\n            x_top = x0 + dx * (e->sy - y_top);\n            sy0 = e->sy;\n         } else {\n            x_top = x0;\n            sy0 = y_top;\n         }\n         if (e->ey < y_bottom) {\n            x_bottom = x0 + dx * (e->ey - y_top);\n            sy1 = e->ey;\n         } else {\n            x_bottom = xb;\n            sy1 = y_bottom;\n         }\n\n         if (x_top >= 0 && x_bottom >= 0 && x_top < len && x_bottom < len) {\n            // from here on, we don't have to range check x values\n\n            if ((int) x_top == (int) x_bottom) {\n               float height;\n               // simple case, only spans one pixel\n               int x = (int) x_top;\n               height = sy1 - sy0;\n               STBTT_assert(x >= 0 && x < len);\n               scanline[x] += e->direction * (1-((x_top - x) + (x_bottom-x))/2)  * height;\n               scanline_fill[x] += e->direction * height; // everything right of this pixel is filled\n            } else {\n               int x,x1,x2;\n               float y_crossing, step, sign, area;\n               // covers 2+ pixels\n               if (x_top > x_bottom) {\n                  // flip scanline vertically; signed area is the same\n                  float t;\n                  sy0 = y_bottom - (sy0 - y_top);\n                  sy1 = y_bottom - (sy1 - y_top);\n                  t = sy0, sy0 = sy1, sy1 = t;\n                  t = x_bottom, x_bottom = x_top, x_top = t;\n                  dx = -dx;\n                  dy = -dy;\n                  t = x0, x0 = xb, xb = t;\n               }\n\n               x1 = (int) x_top;\n               x2 = (int) x_bottom;\n               // compute intersection with y axis at x1+1\n               y_crossing = (x1+1 - x0) * dy + y_top;\n\n               sign = e->direction;\n               // area of the rectangle covered from y0..y_crossing\n               area = sign * (y_crossing-sy0);\n               // area of the triangle (x_top,y0), (x+1,y0), (x+1,y_crossing)\n               scanline[x1] += area * (1-((x_top - x1)+(x1+1-x1))/2);\n\n               step = sign * dy;\n               for (x = x1+1; x < x2; ++x) {\n                  scanline[x] += area + step/2;\n                  area += step;\n               }\n               y_crossing += dy * (x2 - (x1+1));\n\n               STBTT_assert(STBTT_fabs(area) <= 1.01f);\n\n               scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing);\n\n               scanline_fill[x2] += sign * (sy1-sy0);\n            }\n         } else {\n            // if edge goes outside of box we're drawing, we require\n            // clipping logic. since this does not match the intended use\n            // of this library, we use a different, very slow brute\n            // force implementation\n            int x;\n            for (x=0; x < len; ++x) {\n               // cases:\n               //\n               // there can be up to two intersections with the pixel. any intersection\n               // with left or right edges can be handled by splitting into two (or three)\n               // regions. intersections with top & bottom do not necessitate case-wise logic.\n               //\n               // the old way of doing this found the intersections with the left & right edges,\n               // then used some simple logic to produce up to three segments in sorted order\n               // from top-to-bottom. however, this had a problem: if an x edge was epsilon\n               // across the x border, then the corresponding y position might not be distinct\n               // from the other y segment, and it might ignored as an empty segment. to avoid\n               // that, we need to explicitly produce segments based on x positions.\n\n               // rename variables to clearly-defined pairs\n               float y0 = y_top;\n               float x1 = (float) (x);\n               float x2 = (float) (x+1);\n               float x3 = xb;\n               float y3 = y_bottom;\n\n               // x = e->x + e->dx * (y-y_top)\n               // (y-y_top) = (x - e->x) / e->dx\n               // y = (x - e->x) / e->dx + y_top\n               float y1 = (x - x0) / dx + y_top;\n               float y2 = (x+1 - x0) / dx + y_top;\n\n               if (x0 < x1 && x3 > x2) {         // three segments descending down-right\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1);\n                  stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x2,y2);\n                  stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x3,y3);\n               } else if (x3 < x1 && x0 > x2) {  // three segments descending down-left\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x2,y2);\n                  stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x1,y1);\n                  stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x3,y3);\n               } else if (x0 < x1 && x3 > x1) {  // two segments across x, down-right\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1);\n                  stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x3,y3);\n               } else if (x3 < x1 && x0 > x1) {  // two segments across x, down-left\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1);\n                  stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x3,y3);\n               } else if (x0 < x2 && x3 > x2) {  // two segments across x+1, down-right\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x2,y2);\n                  stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x3,y3);\n               } else if (x3 < x2 && x0 > x2) {  // two segments across x+1, down-left\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x2,y2);\n                  stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x3,y3);\n               } else {  // one segment\n                  stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x3,y3);\n               }\n            }\n         }\n      }\n      e = e->next;\n   }\n}\n\n// directly AA rasterize edges w/o supersampling\nstatic void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e, int n, int vsubsample, int off_x, int off_y, void *userdata)\n{\n   stbtt__hheap hh = { 0, 0, 0 };\n   stbtt__active_edge *active = NULL;\n   int y,j=0, i;\n   float scanline_data[129], *scanline, *scanline2;\n\n   STBTT__NOTUSED(vsubsample);\n\n   if (result->w > 64)\n      scanline = (float *) STBTT_malloc((result->w*2+1) * sizeof(float), userdata);\n   else\n      scanline = scanline_data;\n\n   scanline2 = scanline + result->w;\n\n   y = off_y;\n   e[n].y0 = (float) (off_y + result->h) + 1;\n\n   while (j < result->h) {\n      // find center of pixel for this scanline\n      float scan_y_top    = y + 0.0f;\n      float scan_y_bottom = y + 1.0f;\n      stbtt__active_edge **step = &active;\n\n      STBTT_memset(scanline , 0, result->w*sizeof(scanline[0]));\n      STBTT_memset(scanline2, 0, (result->w+1)*sizeof(scanline[0]));\n\n      // update all active edges;\n      // remove all active edges that terminate before the top of this scanline\n      while (*step) {\n         stbtt__active_edge * z = *step;\n         if (z->ey <= scan_y_top) {\n            *step = z->next; // delete from list\n            STBTT_assert(z->direction);\n            z->direction = 0;\n            stbtt__hheap_free(&hh, z);\n         } else {\n            step = &((*step)->next); // advance through list\n         }\n      }\n\n      // insert all edges that start before the bottom of this scanline\n      while (e->y0 <= scan_y_bottom) {\n         if (e->y0 != e->y1) {\n            stbtt__active_edge *z = stbtt__new_active(&hh, e, off_x, scan_y_top, userdata);\n            if (z != NULL) {\n               if (j == 0 && off_y != 0) {\n                  if (z->ey < scan_y_top) {\n                     // this can happen due to subpixel positioning and some kind of fp rounding error i think\n                     z->ey = scan_y_top;\n                  }\n               }\n               STBTT_assert(z->ey >= scan_y_top); // if we get really unlucky a tiny bit of an edge can be out of bounds\n               // insert at front\n               z->next = active;\n               active = z;\n            }\n         }\n         ++e;\n      }\n\n      // now process all active edges\n      if (active)\n         stbtt__fill_active_edges_new(scanline, scanline2+1, result->w, active, scan_y_top);\n\n      {\n         float sum = 0;\n         for (i=0; i < result->w; ++i) {\n            float k;\n            int m;\n            sum += scanline2[i];\n            k = scanline[i] + sum;\n            k = (float) STBTT_fabs(k)*255 + 0.5f;\n            m = (int) k;\n            if (m > 255) m = 255;\n            result->pixels[j*result->stride + i] = (unsigned char) m;\n         }\n      }\n      // advance all the edges\n      step = &active;\n      while (*step) {\n         stbtt__active_edge *z = *step;\n         z->fx += z->fdx; // advance to position for current scanline\n         step = &((*step)->next); // advance through list\n      }\n\n      ++y;\n      ++j;\n   }\n\n   stbtt__hheap_cleanup(&hh, userdata);\n\n   if (scanline != scanline_data)\n      STBTT_free(scanline, userdata);\n}\n#else\n#error \"Unrecognized value of STBTT_RASTERIZER_VERSION\"\n#endif\n\n#define STBTT__COMPARE(a,b)  ((a)->y0 < (b)->y0)\n\nstatic void stbtt__sort_edges_ins_sort(stbtt__edge *p, int n)\n{\n   int i,j;\n   for (i=1; i < n; ++i) {\n      stbtt__edge t = p[i], *a = &t;\n      j = i;\n      while (j > 0) {\n         stbtt__edge *b = &p[j-1];\n         int c = STBTT__COMPARE(a,b);\n         if (!c) break;\n         p[j] = p[j-1];\n         --j;\n      }\n      if (i != j)\n         p[j] = t;\n   }\n}\n\nstatic void stbtt__sort_edges_quicksort(stbtt__edge *p, int n)\n{\n   /* threshold for transitioning to insertion sort */\n   while (n > 12) {\n      stbtt__edge t;\n      int c01,c12,c,m,i,j;\n\n      /* compute median of three */\n      m = n >> 1;\n      c01 = STBTT__COMPARE(&p[0],&p[m]);\n      c12 = STBTT__COMPARE(&p[m],&p[n-1]);\n      /* if 0 >= mid >= end, or 0 < mid < end, then use mid */\n      if (c01 != c12) {\n         /* otherwise, we'll need to swap something else to middle */\n         int z;\n         c = STBTT__COMPARE(&p[0],&p[n-1]);\n         /* 0>mid && mid<n:  0>n => n; 0<n => 0 */\n         /* 0<mid && mid>n:  0>n => 0; 0<n => n */\n         z = (c == c12) ? 0 : n-1;\n         t = p[z];\n         p[z] = p[m];\n         p[m] = t;\n      }\n      /* now p[m] is the median-of-three */\n      /* swap it to the beginning so it won't move around */\n      t = p[0];\n      p[0] = p[m];\n      p[m] = t;\n\n      /* partition loop */\n      i=1;\n      j=n-1;\n      for(;;) {\n         /* handling of equality is crucial here */\n         /* for sentinels & efficiency with duplicates */\n         for (;;++i) {\n            if (!STBTT__COMPARE(&p[i], &p[0])) break;\n         }\n         for (;;--j) {\n            if (!STBTT__COMPARE(&p[0], &p[j])) break;\n         }\n         /* make sure we haven't crossed */\n         if (i >= j) break;\n         t = p[i];\n         p[i] = p[j];\n         p[j] = t;\n\n         ++i;\n         --j;\n      }\n      /* recurse on smaller side, iterate on larger */\n      if (j < (n-i)) {\n         stbtt__sort_edges_quicksort(p,j);\n         p = p+i;\n         n = n-i;\n      } else {\n         stbtt__sort_edges_quicksort(p+i, n-i);\n         n = j;\n      }\n   }\n}\n\nstatic void stbtt__sort_edges(stbtt__edge *p, int n)\n{\n   stbtt__sort_edges_quicksort(p, n);\n   stbtt__sort_edges_ins_sort(p, n);\n}\n\ntypedef struct\n{\n   float x,y;\n} stbtt__point;\n\nstatic void stbtt__rasterize(stbtt__bitmap *result, stbtt__point *pts, int *wcount, int windings, float scale_x, float scale_y, float shift_x, float shift_y, int off_x, int off_y, int invert, void *userdata)\n{\n   float y_scale_inv = invert ? -scale_y : scale_y;\n   stbtt__edge *e;\n   int n,i,j,k,m;\n#if STBTT_RASTERIZER_VERSION == 1\n   int vsubsample = result->h < 8 ? 15 : 5;\n#elif STBTT_RASTERIZER_VERSION == 2\n   int vsubsample = 1;\n#else\n   #error \"Unrecognized value of STBTT_RASTERIZER_VERSION\"\n#endif\n   // vsubsample should divide 255 evenly; otherwise we won't reach full opacity\n\n   // now we have to blow out the windings into explicit edge lists\n   n = 0;\n   for (i=0; i < windings; ++i)\n      n += wcount[i];\n\n   e = (stbtt__edge *) STBTT_malloc(sizeof(*e) * (n+1), userdata); // add an extra one as a sentinel\n   if (e == 0) return;\n   n = 0;\n\n   m=0;\n   for (i=0; i < windings; ++i) {\n      stbtt__point *p = pts + m;\n      m += wcount[i];\n      j = wcount[i]-1;\n      for (k=0; k < wcount[i]; j=k++) {\n         int a=k,b=j;\n         // skip the edge if horizontal\n         if (p[j].y == p[k].y)\n            continue;\n         // add edge from j to k to the list\n         e[n].invert = 0;\n         if (invert ? p[j].y > p[k].y : p[j].y < p[k].y) {\n            e[n].invert = 1;\n            a=j,b=k;\n         }\n         e[n].x0 = p[a].x * scale_x + shift_x;\n         e[n].y0 = (p[a].y * y_scale_inv + shift_y) * vsubsample;\n         e[n].x1 = p[b].x * scale_x + shift_x;\n         e[n].y1 = (p[b].y * y_scale_inv + shift_y) * vsubsample;\n         ++n;\n      }\n   }\n\n   // now sort the edges by their highest point (should snap to integer, and then by x)\n   //STBTT_sort(e, n, sizeof(e[0]), stbtt__edge_compare);\n   stbtt__sort_edges(e, n);\n\n   // now, traverse the scanlines and find the intersections on each scanline, use xor winding rule\n   stbtt__rasterize_sorted_edges(result, e, n, vsubsample, off_x, off_y, userdata);\n\n   STBTT_free(e, userdata);\n}\n\nstatic void stbtt__add_point(stbtt__point *points, int n, float x, float y)\n{\n   if (!points) return; // during first pass, it's unallocated\n   points[n].x = x;\n   points[n].y = y;\n}\n\n// tessellate until threshold p is happy... @TODO warped to compensate for non-linear stretching\nstatic int stbtt__tesselate_curve(stbtt__point *points, int *num_points, float x0, float y0, float x1, float y1, float x2, float y2, float objspace_flatness_squared, int n)\n{\n   // midpoint\n   float mx = (x0 + 2*x1 + x2)/4;\n   float my = (y0 + 2*y1 + y2)/4;\n   // versus directly drawn line\n   float dx = (x0+x2)/2 - mx;\n   float dy = (y0+y2)/2 - my;\n   if (n > 16) // 65536 segments on one curve better be enough!\n      return 1;\n   if (dx*dx+dy*dy > objspace_flatness_squared) { // half-pixel error allowed... need to be smaller if AA\n      stbtt__tesselate_curve(points, num_points, x0,y0, (x0+x1)/2.0f,(y0+y1)/2.0f, mx,my, objspace_flatness_squared,n+1);\n      stbtt__tesselate_curve(points, num_points, mx,my, (x1+x2)/2.0f,(y1+y2)/2.0f, x2,y2, objspace_flatness_squared,n+1);\n   } else {\n      stbtt__add_point(points, *num_points,x2,y2);\n      *num_points = *num_points+1;\n   }\n   return 1;\n}\n\nstatic void stbtt__tesselate_cubic(stbtt__point *points, int *num_points, float x0, float y0, float x1, float y1, float x2, float y2, float x3, float y3, float objspace_flatness_squared, int n)\n{\n   // @TODO this \"flatness\" calculation is just made-up nonsense that seems to work well enough\n   float dx0 = x1-x0;\n   float dy0 = y1-y0;\n   float dx1 = x2-x1;\n   float dy1 = y2-y1;\n   float dx2 = x3-x2;\n   float dy2 = y3-y2;\n   float dx = x3-x0;\n   float dy = y3-y0;\n   float longlen = (float) (STBTT_sqrt(dx0*dx0+dy0*dy0)+STBTT_sqrt(dx1*dx1+dy1*dy1)+STBTT_sqrt(dx2*dx2+dy2*dy2));\n   float shortlen = (float) STBTT_sqrt(dx*dx+dy*dy);\n   float flatness_squared = longlen*longlen-shortlen*shortlen;\n\n   if (n > 16) // 65536 segments on one curve better be enough!\n      return;\n\n   if (flatness_squared > objspace_flatness_squared) {\n      float x01 = (x0+x1)/2;\n      float y01 = (y0+y1)/2;\n      float x12 = (x1+x2)/2;\n      float y12 = (y1+y2)/2;\n      float x23 = (x2+x3)/2;\n      float y23 = (y2+y3)/2;\n\n      float xa = (x01+x12)/2;\n      float ya = (y01+y12)/2;\n      float xb = (x12+x23)/2;\n      float yb = (y12+y23)/2;\n\n      float mx = (xa+xb)/2;\n      float my = (ya+yb)/2;\n\n      stbtt__tesselate_cubic(points, num_points, x0,y0, x01,y01, xa,ya, mx,my, objspace_flatness_squared,n+1);\n      stbtt__tesselate_cubic(points, num_points, mx,my, xb,yb, x23,y23, x3,y3, objspace_flatness_squared,n+1);\n   } else {\n      stbtt__add_point(points, *num_points,x3,y3);\n      *num_points = *num_points+1;\n   }\n}\n\n// returns number of contours\nstatic stbtt__point *stbtt_FlattenCurves(stbtt_vertex *vertices, int num_verts, float objspace_flatness, int **contour_lengths, int *num_contours, void *userdata)\n{\n   stbtt__point *points=0;\n   int num_points=0;\n\n   float objspace_flatness_squared = objspace_flatness * objspace_flatness;\n   int i,n=0,start=0, pass;\n\n   // count how many \"moves\" there are to get the contour count\n   for (i=0; i < num_verts; ++i)\n      if (vertices[i].type == STBTT_vmove)\n         ++n;\n\n   *num_contours = n;\n   if (n == 0) return 0;\n\n   *contour_lengths = (int *) STBTT_malloc(sizeof(**contour_lengths) * n, userdata);\n\n   if (*contour_lengths == 0) {\n      *num_contours = 0;\n      return 0;\n   }\n\n   // make two passes through the points so we don't need to realloc\n   for (pass=0; pass < 2; ++pass) {\n      float x=0,y=0;\n      if (pass == 1) {\n         points = (stbtt__point *) STBTT_malloc(num_points * sizeof(points[0]), userdata);\n         if (points == NULL) goto error;\n      }\n      num_points = 0;\n      n= -1;\n      for (i=0; i < num_verts; ++i) {\n         switch (vertices[i].type) {\n            case STBTT_vmove:\n               // start the next contour\n               if (n >= 0)\n                  (*contour_lengths)[n] = num_points - start;\n               ++n;\n               start = num_points;\n\n               x = vertices[i].x, y = vertices[i].y;\n               stbtt__add_point(points, num_points++, x,y);\n               break;\n            case STBTT_vline:\n               x = vertices[i].x, y = vertices[i].y;\n               stbtt__add_point(points, num_points++, x, y);\n               break;\n            case STBTT_vcurve:\n               stbtt__tesselate_curve(points, &num_points, x,y,\n                                        vertices[i].cx, vertices[i].cy,\n                                        vertices[i].x,  vertices[i].y,\n                                        objspace_flatness_squared, 0);\n               x = vertices[i].x, y = vertices[i].y;\n               break;\n            case STBTT_vcubic:\n               stbtt__tesselate_cubic(points, &num_points, x,y,\n                                        vertices[i].cx, vertices[i].cy,\n                                        vertices[i].cx1, vertices[i].cy1,\n                                        vertices[i].x,  vertices[i].y,\n                                        objspace_flatness_squared, 0);\n               x = vertices[i].x, y = vertices[i].y;\n               break;\n         }\n      }\n      (*contour_lengths)[n] = num_points - start;\n   }\n\n   return points;\nerror:\n   STBTT_free(points, userdata);\n   STBTT_free(*contour_lengths, userdata);\n   *contour_lengths = 0;\n   *num_contours = 0;\n   return NULL;\n}\n\nSTBTT_DEF void stbtt_Rasterize(stbtt__bitmap *result, float flatness_in_pixels, stbtt_vertex *vertices, int num_verts, float scale_x, float scale_y, float shift_x, float shift_y, int x_off, int y_off, int invert, void *userdata)\n{\n   float scale            = scale_x > scale_y ? scale_y : scale_x;\n   int winding_count      = 0;\n   int *winding_lengths   = NULL;\n   stbtt__point *windings = stbtt_FlattenCurves(vertices, num_verts, flatness_in_pixels / scale, &winding_lengths, &winding_count, userdata);\n   if (windings) {\n      stbtt__rasterize(result, windings, winding_lengths, winding_count, scale_x, scale_y, shift_x, shift_y, x_off, y_off, invert, userdata);\n      STBTT_free(winding_lengths, userdata);\n      STBTT_free(windings, userdata);\n   }\n}\n\nSTBTT_DEF void stbtt_FreeBitmap(unsigned char *bitmap, void *userdata)\n{\n   STBTT_free(bitmap, userdata);\n}\n\nSTBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int glyph, int *width, int *height, int *xoff, int *yoff)\n{\n   int ix0,iy0,ix1,iy1;\n   stbtt__bitmap gbm;\n   stbtt_vertex *vertices;\n   int num_verts = stbtt_GetGlyphShape(info, glyph, &vertices);\n\n   if (scale_x == 0) scale_x = scale_y;\n   if (scale_y == 0) {\n      if (scale_x == 0) {\n         STBTT_free(vertices, info->userdata);\n         return NULL;\n      }\n      scale_y = scale_x;\n   }\n\n   stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale_x, scale_y, shift_x, shift_y, &ix0,&iy0,&ix1,&iy1);\n\n   // now we get the size\n   gbm.w = (ix1 - ix0);\n   gbm.h = (iy1 - iy0);\n   gbm.pixels = NULL; // in case we error\n\n   if (width ) *width  = gbm.w;\n   if (height) *height = gbm.h;\n   if (xoff  ) *xoff   = ix0;\n   if (yoff  ) *yoff   = iy0;\n\n   if (gbm.w && gbm.h) {\n      gbm.pixels = (unsigned char *) STBTT_malloc(gbm.w * gbm.h, info->userdata);\n      if (gbm.pixels) {\n         gbm.stride = gbm.w;\n\n         stbtt_Rasterize(&gbm, 0.35f, vertices, num_verts, scale_x, scale_y, shift_x, shift_y, ix0, iy0, 1, info->userdata);\n      }\n   }\n   STBTT_free(vertices, info->userdata);\n   return gbm.pixels;\n}\n\nSTBTT_DEF unsigned char *stbtt_GetGlyphBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int glyph, int *width, int *height, int *xoff, int *yoff)\n{\n   return stbtt_GetGlyphBitmapSubpixel(info, scale_x, scale_y, 0.0f, 0.0f, glyph, width, height, xoff, yoff);\n}\n\nSTBTT_DEF void stbtt_MakeGlyphBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int glyph)\n{\n   int ix0,iy0;\n   stbtt_vertex *vertices;\n   int num_verts = stbtt_GetGlyphShape(info, glyph, &vertices);\n   stbtt__bitmap gbm;\n\n   stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale_x, scale_y, shift_x, shift_y, &ix0,&iy0,0,0);\n   gbm.pixels = output;\n   gbm.w = out_w;\n   gbm.h = out_h;\n   gbm.stride = out_stride;\n\n   if (gbm.w && gbm.h)\n      stbtt_Rasterize(&gbm, 0.35f, vertices, num_verts, scale_x, scale_y, shift_x, shift_y, ix0,iy0, 1, info->userdata);\n\n   STBTT_free(vertices, info->userdata);\n}\n\nSTBTT_DEF void stbtt_MakeGlyphBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int glyph)\n{\n   stbtt_MakeGlyphBitmapSubpixel(info, output, out_w, out_h, out_stride, scale_x, scale_y, 0.0f,0.0f, glyph);\n}\n\nSTBTT_DEF unsigned char *stbtt_GetCodepointBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint, int *width, int *height, int *xoff, int *yoff)\n{\n   return stbtt_GetGlyphBitmapSubpixel(info, scale_x, scale_y,shift_x,shift_y, stbtt_FindGlyphIndex(info,codepoint), width,height,xoff,yoff);\n}\n\nSTBTT_DEF void stbtt_MakeCodepointBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int oversample_x, int oversample_y, float *sub_x, float *sub_y, int codepoint)\n{\n   stbtt_MakeGlyphBitmapSubpixelPrefilter(info, output, out_w, out_h, out_stride, scale_x, scale_y, shift_x, shift_y, oversample_x, oversample_y, sub_x, sub_y, stbtt_FindGlyphIndex(info,codepoint));\n}\n\nSTBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint)\n{\n   stbtt_MakeGlyphBitmapSubpixel(info, output, out_w, out_h, out_stride, scale_x, scale_y, shift_x, shift_y, stbtt_FindGlyphIndex(info,codepoint));\n}\n\nSTBTT_DEF unsigned char *stbtt_GetCodepointBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int codepoint, int *width, int *height, int *xoff, int *yoff)\n{\n   return stbtt_GetCodepointBitmapSubpixel(info, scale_x, scale_y, 0.0f,0.0f, codepoint, width,height,xoff,yoff);\n}\n\nSTBTT_DEF void stbtt_MakeCodepointBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int codepoint)\n{\n   stbtt_MakeCodepointBitmapSubpixel(info, output, out_w, out_h, out_stride, scale_x, scale_y, 0.0f,0.0f, codepoint);\n}\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// bitmap baking\n//\n// This is SUPER-CRAPPY packing to keep source code small\n\nstatic int stbtt_BakeFontBitmap_internal(unsigned char *data, int offset,  // font location (use offset=0 for plain .ttf)\n                                float pixel_height,                     // height of font in pixels\n                                unsigned char *pixels, int pw, int ph,  // bitmap to be filled in\n                                int first_char, int num_chars,          // characters to bake\n                                stbtt_bakedchar *chardata)\n{\n   float scale;\n   int x,y,bottom_y, i;\n   stbtt_fontinfo f;\n   f.userdata = NULL;\n   if (!stbtt_InitFont(&f, data, offset))\n      return -1;\n   STBTT_memset(pixels, 0, pw*ph); // background of 0 around pixels\n   x=y=1;\n   bottom_y = 1;\n\n   scale = stbtt_ScaleForPixelHeight(&f, pixel_height);\n\n   for (i=0; i < num_chars; ++i) {\n      int advance, lsb, x0,y0,x1,y1,gw,gh;\n      int g = stbtt_FindGlyphIndex(&f, first_char + i);\n      stbtt_GetGlyphHMetrics(&f, g, &advance, &lsb);\n      stbtt_GetGlyphBitmapBox(&f, g, scale,scale, &x0,&y0,&x1,&y1);\n      gw = x1-x0;\n      gh = y1-y0;\n      if (x + gw + 1 >= pw)\n         y = bottom_y, x = 1; // advance to next row\n      if (y + gh + 1 >= ph) // check if it fits vertically AFTER potentially moving to next row\n         return -i;\n      STBTT_assert(x+gw < pw);\n      STBTT_assert(y+gh < ph);\n      stbtt_MakeGlyphBitmap(&f, pixels+x+y*pw, gw,gh,pw, scale,scale, g);\n      chardata[i].x0 = (stbtt_int16) x;\n      chardata[i].y0 = (stbtt_int16) y;\n      chardata[i].x1 = (stbtt_int16) (x + gw);\n      chardata[i].y1 = (stbtt_int16) (y + gh);\n      chardata[i].xadvance = scale * advance;\n      chardata[i].xoff     = (float) x0;\n      chardata[i].yoff     = (float) y0;\n      x = x + gw + 1;\n      if (y+gh+1 > bottom_y)\n         bottom_y = y+gh+1;\n   }\n   return bottom_y;\n}\n\nSTBTT_DEF void stbtt_GetBakedQuad(const stbtt_bakedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int opengl_fillrule)\n{\n   float d3d_bias = opengl_fillrule ? 0 : -0.5f;\n   float ipw = 1.0f / pw, iph = 1.0f / ph;\n   const stbtt_bakedchar *b = chardata + char_index;\n   int round_x = STBTT_ifloor((*xpos + b->xoff) + 0.5f);\n   int round_y = STBTT_ifloor((*ypos + b->yoff) + 0.5f);\n\n   q->x0 = round_x + d3d_bias;\n   q->y0 = round_y + d3d_bias;\n   q->x1 = round_x + b->x1 - b->x0 + d3d_bias;\n   q->y1 = round_y + b->y1 - b->y0 + d3d_bias;\n\n   q->s0 = b->x0 * ipw;\n   q->t0 = b->y0 * iph;\n   q->s1 = b->x1 * ipw;\n   q->t1 = b->y1 * iph;\n\n   *xpos += b->xadvance;\n}\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// rectangle packing replacement routines if you don't have stb_rect_pack.h\n//\n\n#ifndef STB_RECT_PACK_VERSION\n\ntypedef int stbrp_coord;\n\n////////////////////////////////////////////////////////////////////////////////////\n//                                                                                //\n//                                                                                //\n// COMPILER WARNING ?!?!?                                                         //\n//                                                                                //\n//                                                                                //\n// if you get a compile warning due to these symbols being defined more than      //\n// once, move #include \"stb_rect_pack.h\" before #include \"stb_truetype.h\"         //\n//                                                                                //\n////////////////////////////////////////////////////////////////////////////////////\n\ntypedef struct\n{\n   int width,height;\n   int x,y,bottom_y;\n} stbrp_context;\n\ntypedef struct\n{\n   unsigned char x;\n} stbrp_node;\n\nstruct stbrp_rect\n{\n   stbrp_coord x,y;\n   int id,w,h,was_packed;\n};\n\nstatic void stbrp_init_target(stbrp_context *con, int pw, int ph, stbrp_node *nodes, int num_nodes)\n{\n   con->width  = pw;\n   con->height = ph;\n   con->x = 0;\n   con->y = 0;\n   con->bottom_y = 0;\n   STBTT__NOTUSED(nodes);\n   STBTT__NOTUSED(num_nodes);\n}\n\nstatic void stbrp_pack_rects(stbrp_context *con, stbrp_rect *rects, int num_rects)\n{\n   int i;\n   for (i=0; i < num_rects; ++i) {\n      if (con->x + rects[i].w > con->width) {\n         con->x = 0;\n         con->y = con->bottom_y;\n      }\n      if (con->y + rects[i].h > con->height)\n         break;\n      rects[i].x = con->x;\n      rects[i].y = con->y;\n      rects[i].was_packed = 1;\n      con->x += rects[i].w;\n      if (con->y + rects[i].h > con->bottom_y)\n         con->bottom_y = con->y + rects[i].h;\n   }\n   for (   ; i < num_rects; ++i)\n      rects[i].was_packed = 0;\n}\n#endif\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// bitmap baking\n//\n// This is SUPER-AWESOME (tm Ryan Gordon) packing using stb_rect_pack.h. If\n// stb_rect_pack.h isn't available, it uses the BakeFontBitmap strategy.\n\nSTBTT_DEF int stbtt_PackBegin(stbtt_pack_context *spc, unsigned char *pixels, int pw, int ph, int stride_in_bytes, int padding, void *alloc_context)\n{\n   stbrp_context *context = (stbrp_context *) STBTT_malloc(sizeof(*context)            ,alloc_context);\n   int            num_nodes = pw - padding;\n   stbrp_node    *nodes   = (stbrp_node    *) STBTT_malloc(sizeof(*nodes  ) * num_nodes,alloc_context);\n\n   if (context == NULL || nodes == NULL) {\n      if (context != NULL) STBTT_free(context, alloc_context);\n      if (nodes   != NULL) STBTT_free(nodes  , alloc_context);\n      return 0;\n   }\n\n   spc->user_allocator_context = alloc_context;\n   spc->width = pw;\n   spc->height = ph;\n   spc->pixels = pixels;\n   spc->pack_info = context;\n   spc->nodes = nodes;\n   spc->padding = padding;\n   spc->stride_in_bytes = stride_in_bytes != 0 ? stride_in_bytes : pw;\n   spc->h_oversample = 1;\n   spc->v_oversample = 1;\n   spc->skip_missing = 0;\n\n   stbrp_init_target(context, pw-padding, ph-padding, nodes, num_nodes);\n\n   if (pixels)\n      STBTT_memset(pixels, 0, pw*ph); // background of 0 around pixels\n\n   return 1;\n}\n\nSTBTT_DEF void stbtt_PackEnd  (stbtt_pack_context *spc)\n{\n   STBTT_free(spc->nodes    , spc->user_allocator_context);\n   STBTT_free(spc->pack_info, spc->user_allocator_context);\n}\n\nSTBTT_DEF void stbtt_PackSetOversampling(stbtt_pack_context *spc, unsigned int h_oversample, unsigned int v_oversample)\n{\n   STBTT_assert(h_oversample <= STBTT_MAX_OVERSAMPLE);\n   STBTT_assert(v_oversample <= STBTT_MAX_OVERSAMPLE);\n   if (h_oversample <= STBTT_MAX_OVERSAMPLE)\n      spc->h_oversample = h_oversample;\n   if (v_oversample <= STBTT_MAX_OVERSAMPLE)\n      spc->v_oversample = v_oversample;\n}\n\nSTBTT_DEF void stbtt_PackSetSkipMissingCodepoints(stbtt_pack_context *spc, int skip)\n{\n   spc->skip_missing = skip;\n}\n\n#define STBTT__OVER_MASK  (STBTT_MAX_OVERSAMPLE-1)\n\nstatic void stbtt__h_prefilter(unsigned char *pixels, int w, int h, int stride_in_bytes, unsigned int kernel_width)\n{\n   unsigned char buffer[STBTT_MAX_OVERSAMPLE];\n   int safe_w = w - kernel_width;\n   int j;\n   STBTT_memset(buffer, 0, STBTT_MAX_OVERSAMPLE); // suppress bogus warning from VS2013 -analyze\n   for (j=0; j < h; ++j) {\n      int i;\n      unsigned int total;\n      STBTT_memset(buffer, 0, kernel_width);\n\n      total = 0;\n\n      // make kernel_width a constant in common cases so compiler can optimize out the divide\n      switch (kernel_width) {\n         case 2:\n            for (i=0; i <= safe_w; ++i) {\n               total += pixels[i] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i];\n               pixels[i] = (unsigned char) (total / 2);\n            }\n            break;\n         case 3:\n            for (i=0; i <= safe_w; ++i) {\n               total += pixels[i] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i];\n               pixels[i] = (unsigned char) (total / 3);\n            }\n            break;\n         case 4:\n            for (i=0; i <= safe_w; ++i) {\n               total += pixels[i] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i];\n               pixels[i] = (unsigned char) (total / 4);\n            }\n            break;\n         case 5:\n            for (i=0; i <= safe_w; ++i) {\n               total += pixels[i] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i];\n               pixels[i] = (unsigned char) (total / 5);\n            }\n            break;\n         default:\n            for (i=0; i <= safe_w; ++i) {\n               total += pixels[i] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i];\n               pixels[i] = (unsigned char) (total / kernel_width);\n            }\n            break;\n      }\n\n      for (; i < w; ++i) {\n         STBTT_assert(pixels[i] == 0);\n         total -= buffer[i & STBTT__OVER_MASK];\n         pixels[i] = (unsigned char) (total / kernel_width);\n      }\n\n      pixels += stride_in_bytes;\n   }\n}\n\nstatic void stbtt__v_prefilter(unsigned char *pixels, int w, int h, int stride_in_bytes, unsigned int kernel_width)\n{\n   unsigned char buffer[STBTT_MAX_OVERSAMPLE];\n   int safe_h = h - kernel_width;\n   int j;\n   STBTT_memset(buffer, 0, STBTT_MAX_OVERSAMPLE); // suppress bogus warning from VS2013 -analyze\n   for (j=0; j < w; ++j) {\n      int i;\n      unsigned int total;\n      STBTT_memset(buffer, 0, kernel_width);\n\n      total = 0;\n\n      // make kernel_width a constant in common cases so compiler can optimize out the divide\n      switch (kernel_width) {\n         case 2:\n            for (i=0; i <= safe_h; ++i) {\n               total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes];\n               pixels[i*stride_in_bytes] = (unsigned char) (total / 2);\n            }\n            break;\n         case 3:\n            for (i=0; i <= safe_h; ++i) {\n               total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes];\n               pixels[i*stride_in_bytes] = (unsigned char) (total / 3);\n            }\n            break;\n         case 4:\n            for (i=0; i <= safe_h; ++i) {\n               total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes];\n               pixels[i*stride_in_bytes] = (unsigned char) (total / 4);\n            }\n            break;\n         case 5:\n            for (i=0; i <= safe_h; ++i) {\n               total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes];\n               pixels[i*stride_in_bytes] = (unsigned char) (total / 5);\n            }\n            break;\n         default:\n            for (i=0; i <= safe_h; ++i) {\n               total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK];\n               buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes];\n               pixels[i*stride_in_bytes] = (unsigned char) (total / kernel_width);\n            }\n            break;\n      }\n\n      for (; i < h; ++i) {\n         STBTT_assert(pixels[i*stride_in_bytes] == 0);\n         total -= buffer[i & STBTT__OVER_MASK];\n         pixels[i*stride_in_bytes] = (unsigned char) (total / kernel_width);\n      }\n\n      pixels += 1;\n   }\n}\n\nstatic float stbtt__oversample_shift(int oversample)\n{\n   if (!oversample)\n      return 0.0f;\n\n   // The prefilter is a box filter of width \"oversample\",\n   // which shifts phase by (oversample - 1)/2 pixels in\n   // oversampled space. We want to shift in the opposite\n   // direction to counter this.\n   return (float)-(oversample - 1) / (2.0f * (float)oversample);\n}\n\n// rects array must be big enough to accommodate all characters in the given ranges\nSTBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects)\n{\n   int i,j,k;\n   int missing_glyph_added = 0;\n\n   k=0;\n   for (i=0; i < num_ranges; ++i) {\n      float fh = ranges[i].font_size;\n      float scale = fh > 0 ? stbtt_ScaleForPixelHeight(info, fh) : stbtt_ScaleForMappingEmToPixels(info, -fh);\n      ranges[i].h_oversample = (unsigned char) spc->h_oversample;\n      ranges[i].v_oversample = (unsigned char) spc->v_oversample;\n      for (j=0; j < ranges[i].num_chars; ++j) {\n         int x0,y0,x1,y1;\n         int codepoint = ranges[i].array_of_unicode_codepoints == NULL ? ranges[i].first_unicode_codepoint_in_range + j : ranges[i].array_of_unicode_codepoints[j];\n         int glyph = stbtt_FindGlyphIndex(info, codepoint);\n         if (glyph == 0 && (spc->skip_missing || missing_glyph_added)) {\n            rects[k].w = rects[k].h = 0;\n         } else {\n            stbtt_GetGlyphBitmapBoxSubpixel(info,glyph,\n                                            scale * spc->h_oversample,\n                                            scale * spc->v_oversample,\n                                            0,0,\n                                            &x0,&y0,&x1,&y1);\n            rects[k].w = (stbrp_coord) (x1-x0 + spc->padding + spc->h_oversample-1);\n            rects[k].h = (stbrp_coord) (y1-y0 + spc->padding + spc->v_oversample-1);\n            if (glyph == 0)\n               missing_glyph_added = 1;\n         }\n         ++k;\n      }\n   }\n\n   return k;\n}\n\nSTBTT_DEF void stbtt_MakeGlyphBitmapSubpixelPrefilter(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int prefilter_x, int prefilter_y, float *sub_x, float *sub_y, int glyph)\n{\n   stbtt_MakeGlyphBitmapSubpixel(info,\n                                 output,\n                                 out_w - (prefilter_x - 1),\n                                 out_h - (prefilter_y - 1),\n                                 out_stride,\n                                 scale_x,\n                                 scale_y,\n                                 shift_x,\n                                 shift_y,\n                                 glyph);\n\n   if (prefilter_x > 1)\n      stbtt__h_prefilter(output, out_w, out_h, out_stride, prefilter_x);\n\n   if (prefilter_y > 1)\n      stbtt__v_prefilter(output, out_w, out_h, out_stride, prefilter_y);\n\n   *sub_x = stbtt__oversample_shift(prefilter_x);\n   *sub_y = stbtt__oversample_shift(prefilter_y);\n}\n\n// rects array must be big enough to accommodate all characters in the given ranges\nSTBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, const stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects)\n{\n   int i,j,k, missing_glyph = -1, return_value = 1;\n\n   // save current values\n   int old_h_over = spc->h_oversample;\n   int old_v_over = spc->v_oversample;\n\n   k = 0;\n   for (i=0; i < num_ranges; ++i) {\n      float fh = ranges[i].font_size;\n      float scale = fh > 0 ? stbtt_ScaleForPixelHeight(info, fh) : stbtt_ScaleForMappingEmToPixels(info, -fh);\n      float recip_h,recip_v,sub_x,sub_y;\n      spc->h_oversample = ranges[i].h_oversample;\n      spc->v_oversample = ranges[i].v_oversample;\n      recip_h = 1.0f / spc->h_oversample;\n      recip_v = 1.0f / spc->v_oversample;\n      sub_x = stbtt__oversample_shift(spc->h_oversample);\n      sub_y = stbtt__oversample_shift(spc->v_oversample);\n      for (j=0; j < ranges[i].num_chars; ++j) {\n         stbrp_rect *r = &rects[k];\n         if (r->was_packed && r->w != 0 && r->h != 0) {\n            stbtt_packedchar *bc = &ranges[i].chardata_for_range[j];\n            int advance, lsb, x0,y0,x1,y1;\n            int codepoint = ranges[i].array_of_unicode_codepoints == NULL ? ranges[i].first_unicode_codepoint_in_range + j : ranges[i].array_of_unicode_codepoints[j];\n            int glyph = stbtt_FindGlyphIndex(info, codepoint);\n            stbrp_coord pad = (stbrp_coord) spc->padding;\n\n            // pad on left and top\n            r->x += pad;\n            r->y += pad;\n            r->w -= pad;\n            r->h -= pad;\n            stbtt_GetGlyphHMetrics(info, glyph, &advance, &lsb);\n            stbtt_GetGlyphBitmapBox(info, glyph,\n                                    scale * spc->h_oversample,\n                                    scale * spc->v_oversample,\n                                    &x0,&y0,&x1,&y1);\n            stbtt_MakeGlyphBitmapSubpixel(info,\n                                          spc->pixels + r->x + r->y*spc->stride_in_bytes,\n                                          r->w - spc->h_oversample+1,\n                                          r->h - spc->v_oversample+1,\n                                          spc->stride_in_bytes,\n                                          scale * spc->h_oversample,\n                                          scale * spc->v_oversample,\n                                          0,0,\n                                          glyph);\n\n            if (spc->h_oversample > 1)\n               stbtt__h_prefilter(spc->pixels + r->x + r->y*spc->stride_in_bytes,\n                                  r->w, r->h, spc->stride_in_bytes,\n                                  spc->h_oversample);\n\n            if (spc->v_oversample > 1)\n               stbtt__v_prefilter(spc->pixels + r->x + r->y*spc->stride_in_bytes,\n                                  r->w, r->h, spc->stride_in_bytes,\n                                  spc->v_oversample);\n\n            bc->x0       = (stbtt_int16)  r->x;\n            bc->y0       = (stbtt_int16)  r->y;\n            bc->x1       = (stbtt_int16) (r->x + r->w);\n            bc->y1       = (stbtt_int16) (r->y + r->h);\n            bc->xadvance =                scale * advance;\n            bc->xoff     =       (float)  x0 * recip_h + sub_x;\n            bc->yoff     =       (float)  y0 * recip_v + sub_y;\n            bc->xoff2    =                (x0 + r->w) * recip_h + sub_x;\n            bc->yoff2    =                (y0 + r->h) * recip_v + sub_y;\n\n            if (glyph == 0)\n               missing_glyph = j;\n         } else if (spc->skip_missing) {\n            return_value = 0;\n         } else if (r->was_packed && r->w == 0 && r->h == 0 && missing_glyph >= 0) {\n            ranges[i].chardata_for_range[j] = ranges[i].chardata_for_range[missing_glyph];\n         } else {\n            return_value = 0; // if any fail, report failure\n         }\n\n         ++k;\n      }\n   }\n\n   // restore original values\n   spc->h_oversample = old_h_over;\n   spc->v_oversample = old_v_over;\n\n   return return_value;\n}\n\nSTBTT_DEF void stbtt_PackFontRangesPackRects(stbtt_pack_context *spc, stbrp_rect *rects, int num_rects)\n{\n   stbrp_pack_rects((stbrp_context *) spc->pack_info, rects, num_rects);\n}\n\nSTBTT_DEF int stbtt_PackFontRanges(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges)\n{\n   stbtt_fontinfo info;\n   int i,j,n, return_value = 1;\n   //stbrp_context *context = (stbrp_context *) spc->pack_info;\n   stbrp_rect    *rects;\n\n   // flag all characters as NOT packed\n   for (i=0; i < num_ranges; ++i)\n      for (j=0; j < ranges[i].num_chars; ++j)\n         ranges[i].chardata_for_range[j].x0 =\n         ranges[i].chardata_for_range[j].y0 =\n         ranges[i].chardata_for_range[j].x1 =\n         ranges[i].chardata_for_range[j].y1 = 0;\n\n   n = 0;\n   for (i=0; i < num_ranges; ++i)\n      n += ranges[i].num_chars;\n\n   rects = (stbrp_rect *) STBTT_malloc(sizeof(*rects) * n, spc->user_allocator_context);\n   if (rects == NULL)\n      return 0;\n\n   info.userdata = spc->user_allocator_context;\n   stbtt_InitFont(&info, fontdata, stbtt_GetFontOffsetForIndex(fontdata,font_index));\n\n   n = stbtt_PackFontRangesGatherRects(spc, &info, ranges, num_ranges, rects);\n\n   stbtt_PackFontRangesPackRects(spc, rects, n);\n\n   return_value = stbtt_PackFontRangesRenderIntoRects(spc, &info, ranges, num_ranges, rects);\n\n   STBTT_free(rects, spc->user_allocator_context);\n   return return_value;\n}\n\nSTBTT_DEF int stbtt_PackFontRange(stbtt_pack_context *spc, const unsigned char *fontdata, int font_index, float font_size,\n            int first_unicode_codepoint_in_range, int num_chars_in_range, stbtt_packedchar *chardata_for_range)\n{\n   stbtt_pack_range range;\n   range.first_unicode_codepoint_in_range = first_unicode_codepoint_in_range;\n   range.array_of_unicode_codepoints = NULL;\n   range.num_chars                   = num_chars_in_range;\n   range.chardata_for_range          = chardata_for_range;\n   range.font_size                   = font_size;\n   return stbtt_PackFontRanges(spc, fontdata, font_index, &range, 1);\n}\n\nSTBTT_DEF void stbtt_GetScaledFontVMetrics(const unsigned char *fontdata, int index, float size, float *ascent, float *descent, float *lineGap)\n{\n   int i_ascent, i_descent, i_lineGap;\n   float scale;\n   stbtt_fontinfo info;\n   stbtt_InitFont(&info, fontdata, stbtt_GetFontOffsetForIndex(fontdata, index));\n   scale = size > 0 ? stbtt_ScaleForPixelHeight(&info, size) : stbtt_ScaleForMappingEmToPixels(&info, -size);\n   stbtt_GetFontVMetrics(&info, &i_ascent, &i_descent, &i_lineGap);\n   *ascent  = (float) i_ascent  * scale;\n   *descent = (float) i_descent * scale;\n   *lineGap = (float) i_lineGap * scale;\n}\n\nSTBTT_DEF void stbtt_GetPackedQuad(const stbtt_packedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int align_to_integer)\n{\n   float ipw = 1.0f / pw, iph = 1.0f / ph;\n   const stbtt_packedchar *b = chardata + char_index;\n\n   if (align_to_integer) {\n      float x = (float) STBTT_ifloor((*xpos + b->xoff) + 0.5f);\n      float y = (float) STBTT_ifloor((*ypos + b->yoff) + 0.5f);\n      q->x0 = x;\n      q->y0 = y;\n      q->x1 = x + b->xoff2 - b->xoff;\n      q->y1 = y + b->yoff2 - b->yoff;\n   } else {\n      q->x0 = *xpos + b->xoff;\n      q->y0 = *ypos + b->yoff;\n      q->x1 = *xpos + b->xoff2;\n      q->y1 = *ypos + b->yoff2;\n   }\n\n   q->s0 = b->x0 * ipw;\n   q->t0 = b->y0 * iph;\n   q->s1 = b->x1 * ipw;\n   q->t1 = b->y1 * iph;\n\n   *xpos += b->xadvance;\n}\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// sdf computation\n//\n\n#define STBTT_min(a,b)  ((a) < (b) ? (a) : (b))\n#define STBTT_max(a,b)  ((a) < (b) ? (b) : (a))\n\nstatic int stbtt__ray_intersect_bezier(float orig[2], float ray[2], float q0[2], float q1[2], float q2[2], float hits[2][2])\n{\n   float q0perp = q0[1]*ray[0] - q0[0]*ray[1];\n   float q1perp = q1[1]*ray[0] - q1[0]*ray[1];\n   float q2perp = q2[1]*ray[0] - q2[0]*ray[1];\n   float roperp = orig[1]*ray[0] - orig[0]*ray[1];\n\n   float a = q0perp - 2*q1perp + q2perp;\n   float b = q1perp - q0perp;\n   float c = q0perp - roperp;\n\n   float s0 = 0., s1 = 0.;\n   int num_s = 0;\n\n   if (a != 0.0) {\n      float discr = b*b - a*c;\n      if (discr > 0.0) {\n         float rcpna = -1 / a;\n         float d = (float) STBTT_sqrt(discr);\n         s0 = (b+d) * rcpna;\n         s1 = (b-d) * rcpna;\n         if (s0 >= 0.0 && s0 <= 1.0)\n            num_s = 1;\n         if (d > 0.0 && s1 >= 0.0 && s1 <= 1.0) {\n            if (num_s == 0) s0 = s1;\n            ++num_s;\n         }\n      }\n   } else {\n      // 2*b*s + c = 0\n      // s = -c / (2*b)\n      s0 = c / (-2 * b);\n      if (s0 >= 0.0 && s0 <= 1.0)\n         num_s = 1;\n   }\n\n   if (num_s == 0)\n      return 0;\n   else {\n      float rcp_len2 = 1 / (ray[0]*ray[0] + ray[1]*ray[1]);\n      float rayn_x = ray[0] * rcp_len2, rayn_y = ray[1] * rcp_len2;\n\n      float q0d =   q0[0]*rayn_x +   q0[1]*rayn_y;\n      float q1d =   q1[0]*rayn_x +   q1[1]*rayn_y;\n      float q2d =   q2[0]*rayn_x +   q2[1]*rayn_y;\n      float rod = orig[0]*rayn_x + orig[1]*rayn_y;\n\n      float q10d = q1d - q0d;\n      float q20d = q2d - q0d;\n      float q0rd = q0d - rod;\n\n      hits[0][0] = q0rd + s0*(2.0f - 2.0f*s0)*q10d + s0*s0*q20d;\n      hits[0][1] = a*s0+b;\n\n      if (num_s > 1) {\n         hits[1][0] = q0rd + s1*(2.0f - 2.0f*s1)*q10d + s1*s1*q20d;\n         hits[1][1] = a*s1+b;\n         return 2;\n      } else {\n         return 1;\n      }\n   }\n}\n\nstatic int equal(float *a, float *b)\n{\n   return (a[0] == b[0] && a[1] == b[1]);\n}\n\nstatic int stbtt__compute_crossings_x(float x, float y, int nverts, stbtt_vertex *verts)\n{\n   int i;\n   float orig[2], ray[2] = { 1, 0 };\n   float y_frac;\n   int winding = 0;\n\n   orig[0] = x;\n   orig[1] = y;\n\n   // make sure y never passes through a vertex of the shape\n   y_frac = (float) STBTT_fmod(y, 1.0f);\n   if (y_frac < 0.01f)\n      y += 0.01f;\n   else if (y_frac > 0.99f)\n      y -= 0.01f;\n   orig[1] = y;\n\n   // test a ray from (-infinity,y) to (x,y)\n   for (i=0; i < nverts; ++i) {\n      if (verts[i].type == STBTT_vline) {\n         int x0 = (int) verts[i-1].x, y0 = (int) verts[i-1].y;\n         int x1 = (int) verts[i  ].x, y1 = (int) verts[i  ].y;\n         if (y > STBTT_min(y0,y1) && y < STBTT_max(y0,y1) && x > STBTT_min(x0,x1)) {\n            float x_inter = (y - y0) / (y1 - y0) * (x1-x0) + x0;\n            if (x_inter < x)\n               winding += (y0 < y1) ? 1 : -1;\n         }\n      }\n      if (verts[i].type == STBTT_vcurve) {\n         int x0 = (int) verts[i-1].x , y0 = (int) verts[i-1].y ;\n         int x1 = (int) verts[i  ].cx, y1 = (int) verts[i  ].cy;\n         int x2 = (int) verts[i  ].x , y2 = (int) verts[i  ].y ;\n         int ax = STBTT_min(x0,STBTT_min(x1,x2)), ay = STBTT_min(y0,STBTT_min(y1,y2));\n         int by = STBTT_max(y0,STBTT_max(y1,y2));\n         if (y > ay && y < by && x > ax) {\n            float q0[2],q1[2],q2[2];\n            float hits[2][2];\n            q0[0] = (float)x0;\n            q0[1] = (float)y0;\n            q1[0] = (float)x1;\n            q1[1] = (float)y1;\n            q2[0] = (float)x2;\n            q2[1] = (float)y2;\n            if (equal(q0,q1) || equal(q1,q2)) {\n               x0 = (int)verts[i-1].x;\n               y0 = (int)verts[i-1].y;\n               x1 = (int)verts[i  ].x;\n               y1 = (int)verts[i  ].y;\n               if (y > STBTT_min(y0,y1) && y < STBTT_max(y0,y1) && x > STBTT_min(x0,x1)) {\n                  float x_inter = (y - y0) / (y1 - y0) * (x1-x0) + x0;\n                  if (x_inter < x)\n                     winding += (y0 < y1) ? 1 : -1;\n               }\n            } else {\n               int num_hits = stbtt__ray_intersect_bezier(orig, ray, q0, q1, q2, hits);\n               if (num_hits >= 1)\n                  if (hits[0][0] < 0)\n                     winding += (hits[0][1] < 0 ? -1 : 1);\n               if (num_hits >= 2)\n                  if (hits[1][0] < 0)\n                     winding += (hits[1][1] < 0 ? -1 : 1);\n            }\n         }\n      }\n   }\n   return winding;\n}\n\nstatic float stbtt__cuberoot( float x )\n{\n   if (x<0)\n      return -(float) STBTT_pow(-x,1.0f/3.0f);\n   else\n      return  (float) STBTT_pow( x,1.0f/3.0f);\n}\n\n// x^3 + c*x^2 + b*x + a = 0\nstatic int stbtt__solve_cubic(float a, float b, float c, float* r)\n{\n\tfloat s = -a / 3;\n\tfloat p = b - a*a / 3;\n\tfloat q = a * (2*a*a - 9*b) / 27 + c;\n   float p3 = p*p*p;\n\tfloat d = q*q + 4*p3 / 27;\n\tif (d >= 0) {\n\t\tfloat z = (float) STBTT_sqrt(d);\n\t\tfloat u = (-q + z) / 2;\n\t\tfloat v = (-q - z) / 2;\n\t\tu = stbtt__cuberoot(u);\n\t\tv = stbtt__cuberoot(v);\n\t\tr[0] = s + u + v;\n\t\treturn 1;\n\t} else {\n\t   float u = (float) STBTT_sqrt(-p/3);\n\t   float v = (float) STBTT_acos(-STBTT_sqrt(-27/p3) * q / 2) / 3; // p3 must be negative, since d is negative\n\t   float m = (float) STBTT_cos(v);\n      float n = (float) STBTT_cos(v-3.141592/2)*1.732050808f;\n\t   r[0] = s + u * 2 * m;\n\t   r[1] = s - u * (m + n);\n\t   r[2] = s - u * (m - n);\n\n      //STBTT_assert( STBTT_fabs(((r[0]+a)*r[0]+b)*r[0]+c) < 0.05f);  // these asserts may not be safe at all scales, though they're in bezier t parameter units so maybe?\n      //STBTT_assert( STBTT_fabs(((r[1]+a)*r[1]+b)*r[1]+c) < 0.05f);\n      //STBTT_assert( STBTT_fabs(((r[2]+a)*r[2]+b)*r[2]+c) < 0.05f);\n   \treturn 3;\n   }\n}\n\nSTBTT_DEF unsigned char * stbtt_GetGlyphSDF(const stbtt_fontinfo *info, float scale, int glyph, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff)\n{\n   float scale_x = scale, scale_y = scale;\n   int ix0,iy0,ix1,iy1;\n   int w,h;\n   unsigned char *data;\n\n   if (scale == 0) return NULL;\n\n   stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale, scale, 0.0f,0.0f, &ix0,&iy0,&ix1,&iy1);\n\n   // if empty, return NULL\n   if (ix0 == ix1 || iy0 == iy1)\n      return NULL;\n\n   ix0 -= padding;\n   iy0 -= padding;\n   ix1 += padding;\n   iy1 += padding;\n\n   w = (ix1 - ix0);\n   h = (iy1 - iy0);\n\n   if (width ) *width  = w;\n   if (height) *height = h;\n   if (xoff  ) *xoff   = ix0;\n   if (yoff  ) *yoff   = iy0;\n\n   // invert for y-downwards bitmaps\n   scale_y = -scale_y;\n\n   {\n      int x,y,i,j;\n      float *precompute;\n      stbtt_vertex *verts;\n      int num_verts = stbtt_GetGlyphShape(info, glyph, &verts);\n      data = (unsigned char *) STBTT_malloc(w * h, info->userdata);\n      precompute = (float *) STBTT_malloc(num_verts * sizeof(float), info->userdata);\n\n      for (i=0,j=num_verts-1; i < num_verts; j=i++) {\n         if (verts[i].type == STBTT_vline) {\n            float x0 = verts[i].x*scale_x, y0 = verts[i].y*scale_y;\n            float x1 = verts[j].x*scale_x, y1 = verts[j].y*scale_y;\n            float dist = (float) STBTT_sqrt((x1-x0)*(x1-x0) + (y1-y0)*(y1-y0));\n            precompute[i] = (dist == 0) ? 0.0f : 1.0f / dist;\n         } else if (verts[i].type == STBTT_vcurve) {\n            float x2 = verts[j].x *scale_x, y2 = verts[j].y *scale_y;\n            float x1 = verts[i].cx*scale_x, y1 = verts[i].cy*scale_y;\n            float x0 = verts[i].x *scale_x, y0 = verts[i].y *scale_y;\n            float bx = x0 - 2*x1 + x2, by = y0 - 2*y1 + y2;\n            float len2 = bx*bx + by*by;\n            if (len2 != 0.0f)\n               precompute[i] = 1.0f / (bx*bx + by*by);\n            else\n               precompute[i] = 0.0f;\n         } else\n            precompute[i] = 0.0f;\n      }\n\n      for (y=iy0; y < iy1; ++y) {\n         for (x=ix0; x < ix1; ++x) {\n            float val;\n            float min_dist = 999999.0f;\n            float sx = (float) x + 0.5f;\n            float sy = (float) y + 0.5f;\n            float x_gspace = (sx / scale_x);\n            float y_gspace = (sy / scale_y);\n\n            int winding = stbtt__compute_crossings_x(x_gspace, y_gspace, num_verts, verts); // @OPTIMIZE: this could just be a rasterization, but needs to be line vs. non-tesselated curves so a new path\n\n            for (i=0; i < num_verts; ++i) {\n               float x0 = verts[i].x*scale_x, y0 = verts[i].y*scale_y;\n\n               // check against every point here rather than inside line/curve primitives -- @TODO: wrong if multiple 'moves' in a row produce a garbage point, and given culling, probably more efficient to do within line/curve\n               float dist2 = (x0-sx)*(x0-sx) + (y0-sy)*(y0-sy);\n               if (dist2 < min_dist*min_dist)\n                  min_dist = (float) STBTT_sqrt(dist2);\n\n               if (verts[i].type == STBTT_vline) {\n                  float x1 = verts[i-1].x*scale_x, y1 = verts[i-1].y*scale_y;\n\n                  // coarse culling against bbox\n                  //if (sx > STBTT_min(x0,x1)-min_dist && sx < STBTT_max(x0,x1)+min_dist &&\n                  //    sy > STBTT_min(y0,y1)-min_dist && sy < STBTT_max(y0,y1)+min_dist)\n                  float dist = (float) STBTT_fabs((x1-x0)*(y0-sy) - (y1-y0)*(x0-sx)) * precompute[i];\n                  STBTT_assert(i != 0);\n                  if (dist < min_dist) {\n                     // check position along line\n                     // x' = x0 + t*(x1-x0), y' = y0 + t*(y1-y0)\n                     // minimize (x'-sx)*(x'-sx)+(y'-sy)*(y'-sy)\n                     float dx = x1-x0, dy = y1-y0;\n                     float px = x0-sx, py = y0-sy;\n                     // minimize (px+t*dx)^2 + (py+t*dy)^2 = px*px + 2*px*dx*t + t^2*dx*dx + py*py + 2*py*dy*t + t^2*dy*dy\n                     // derivative: 2*px*dx + 2*py*dy + (2*dx*dx+2*dy*dy)*t, set to 0 and solve\n                     float t = -(px*dx + py*dy) / (dx*dx + dy*dy);\n                     if (t >= 0.0f && t <= 1.0f)\n                        min_dist = dist;\n                  }\n               } else if (verts[i].type == STBTT_vcurve) {\n                  float x2 = verts[i-1].x *scale_x, y2 = verts[i-1].y *scale_y;\n                  float x1 = verts[i  ].cx*scale_x, y1 = verts[i  ].cy*scale_y;\n                  float box_x0 = STBTT_min(STBTT_min(x0,x1),x2);\n                  float box_y0 = STBTT_min(STBTT_min(y0,y1),y2);\n                  float box_x1 = STBTT_max(STBTT_max(x0,x1),x2);\n                  float box_y1 = STBTT_max(STBTT_max(y0,y1),y2);\n                  // coarse culling against bbox to avoid computing cubic unnecessarily\n                  if (sx > box_x0-min_dist && sx < box_x1+min_dist && sy > box_y0-min_dist && sy < box_y1+min_dist) {\n                     int num=0;\n                     float ax = x1-x0, ay = y1-y0;\n                     float bx = x0 - 2*x1 + x2, by = y0 - 2*y1 + y2;\n                     float mx = x0 - sx, my = y0 - sy;\n                     float res[3],px,py,t,it;\n                     float a_inv = precompute[i];\n                     if (a_inv == 0.0) { // if a_inv is 0, it's 2nd degree so use quadratic formula\n                        float a = 3*(ax*bx + ay*by);\n                        float b = 2*(ax*ax + ay*ay) + (mx*bx+my*by);\n                        float c = mx*ax+my*ay;\n                        if (a == 0.0) { // if a is 0, it's linear\n                           if (b != 0.0) {\n                              res[num++] = -c/b;\n                           }\n                        } else {\n                           float discriminant = b*b - 4*a*c;\n                           if (discriminant < 0)\n                              num = 0;\n                           else {\n                              float root = (float) STBTT_sqrt(discriminant);\n                              res[0] = (-b - root)/(2*a);\n                              res[1] = (-b + root)/(2*a);\n                              num = 2; // don't bother distinguishing 1-solution case, as code below will still work\n                           }\n                        }\n                     } else {\n                        float b = 3*(ax*bx + ay*by) * a_inv; // could precompute this as it doesn't depend on sample point\n                        float c = (2*(ax*ax + ay*ay) + (mx*bx+my*by)) * a_inv;\n                        float d = (mx*ax+my*ay) * a_inv;\n                        num = stbtt__solve_cubic(b, c, d, res);\n                     }\n                     if (num >= 1 && res[0] >= 0.0f && res[0] <= 1.0f) {\n                        t = res[0], it = 1.0f - t;\n                        px = it*it*x0 + 2*t*it*x1 + t*t*x2;\n                        py = it*it*y0 + 2*t*it*y1 + t*t*y2;\n                        dist2 = (px-sx)*(px-sx) + (py-sy)*(py-sy);\n                        if (dist2 < min_dist * min_dist)\n                           min_dist = (float) STBTT_sqrt(dist2);\n                     }\n                     if (num >= 2 && res[1] >= 0.0f && res[1] <= 1.0f) {\n                        t = res[1], it = 1.0f - t;\n                        px = it*it*x0 + 2*t*it*x1 + t*t*x2;\n                        py = it*it*y0 + 2*t*it*y1 + t*t*y2;\n                        dist2 = (px-sx)*(px-sx) + (py-sy)*(py-sy);\n                        if (dist2 < min_dist * min_dist)\n                           min_dist = (float) STBTT_sqrt(dist2);\n                     }\n                     if (num >= 3 && res[2] >= 0.0f && res[2] <= 1.0f) {\n                        t = res[2], it = 1.0f - t;\n                        px = it*it*x0 + 2*t*it*x1 + t*t*x2;\n                        py = it*it*y0 + 2*t*it*y1 + t*t*y2;\n                        dist2 = (px-sx)*(px-sx) + (py-sy)*(py-sy);\n                        if (dist2 < min_dist * min_dist)\n                           min_dist = (float) STBTT_sqrt(dist2);\n                     }\n                  }\n               }\n            }\n            if (winding == 0)\n               min_dist = -min_dist;  // if outside the shape, value is negative\n            val = onedge_value + pixel_dist_scale * min_dist;\n            if (val < 0)\n               val = 0;\n            else if (val > 255)\n               val = 255;\n            data[(y-iy0)*w+(x-ix0)] = (unsigned char) val;\n         }\n      }\n      STBTT_free(precompute, info->userdata);\n      STBTT_free(verts, info->userdata);\n   }\n   return data;\n}\n\nSTBTT_DEF unsigned char * stbtt_GetCodepointSDF(const stbtt_fontinfo *info, float scale, int codepoint, int padding, unsigned char onedge_value, float pixel_dist_scale, int *width, int *height, int *xoff, int *yoff)\n{\n   return stbtt_GetGlyphSDF(info, scale, stbtt_FindGlyphIndex(info, codepoint), padding, onedge_value, pixel_dist_scale, width, height, xoff, yoff);\n}\n\nSTBTT_DEF void stbtt_FreeSDF(unsigned char *bitmap, void *userdata)\n{\n   STBTT_free(bitmap, userdata);\n}\n\n//////////////////////////////////////////////////////////////////////////////\n//\n// font name matching -- recommended not to use this\n//\n\n// check if a utf8 string contains a prefix which is the utf16 string; if so return length of matching utf8 string\nstatic stbtt_int32 stbtt__CompareUTF8toUTF16_bigendian_prefix(stbtt_uint8 *s1, stbtt_int32 len1, stbtt_uint8 *s2, stbtt_int32 len2)\n{\n   stbtt_int32 i=0;\n\n   // convert utf16 to utf8 and compare the results while converting\n   while (len2) {\n      stbtt_uint16 ch = s2[0]*256 + s2[1];\n      if (ch < 0x80) {\n         if (i >= len1) return -1;\n         if (s1[i++] != ch) return -1;\n      } else if (ch < 0x800) {\n         if (i+1 >= len1) return -1;\n         if (s1[i++] != 0xc0 + (ch >> 6)) return -1;\n         if (s1[i++] != 0x80 + (ch & 0x3f)) return -1;\n      } else if (ch >= 0xd800 && ch < 0xdc00) {\n         stbtt_uint32 c;\n         stbtt_uint16 ch2 = s2[2]*256 + s2[3];\n         if (i+3 >= len1) return -1;\n         c = ((ch - 0xd800) << 10) + (ch2 - 0xdc00) + 0x10000;\n         if (s1[i++] != 0xf0 + (c >> 18)) return -1;\n         if (s1[i++] != 0x80 + ((c >> 12) & 0x3f)) return -1;\n         if (s1[i++] != 0x80 + ((c >>  6) & 0x3f)) return -1;\n         if (s1[i++] != 0x80 + ((c      ) & 0x3f)) return -1;\n         s2 += 2; // plus another 2 below\n         len2 -= 2;\n      } else if (ch >= 0xdc00 && ch < 0xe000) {\n         return -1;\n      } else {\n         if (i+2 >= len1) return -1;\n         if (s1[i++] != 0xe0 + (ch >> 12)) return -1;\n         if (s1[i++] != 0x80 + ((ch >> 6) & 0x3f)) return -1;\n         if (s1[i++] != 0x80 + ((ch     ) & 0x3f)) return -1;\n      }\n      s2 += 2;\n      len2 -= 2;\n   }\n   return i;\n}\n\nstatic int stbtt_CompareUTF8toUTF16_bigendian_internal(char *s1, int len1, char *s2, int len2)\n{\n   return len1 == stbtt__CompareUTF8toUTF16_bigendian_prefix((stbtt_uint8*) s1, len1, (stbtt_uint8*) s2, len2);\n}\n\n// returns results in whatever encoding you request... but note that 2-byte encodings\n// will be BIG-ENDIAN... use stbtt_CompareUTF8toUTF16_bigendian() to compare\nSTBTT_DEF const char *stbtt_GetFontNameString(const stbtt_fontinfo *font, int *length, int platformID, int encodingID, int languageID, int nameID)\n{\n   stbtt_int32 i,count,stringOffset;\n   stbtt_uint8 *fc = font->data;\n   stbtt_uint32 offset = font->fontstart;\n   stbtt_uint32 nm = stbtt__find_table(fc, offset, \"name\");\n   if (!nm) return NULL;\n\n   count = ttUSHORT(fc+nm+2);\n   stringOffset = nm + ttUSHORT(fc+nm+4);\n   for (i=0; i < count; ++i) {\n      stbtt_uint32 loc = nm + 6 + 12 * i;\n      if (platformID == ttUSHORT(fc+loc+0) && encodingID == ttUSHORT(fc+loc+2)\n          && languageID == ttUSHORT(fc+loc+4) && nameID == ttUSHORT(fc+loc+6)) {\n         *length = ttUSHORT(fc+loc+8);\n         return (const char *) (fc+stringOffset+ttUSHORT(fc+loc+10));\n      }\n   }\n   return NULL;\n}\n\nstatic int stbtt__matchpair(stbtt_uint8 *fc, stbtt_uint32 nm, stbtt_uint8 *name, stbtt_int32 nlen, stbtt_int32 target_id, stbtt_int32 next_id)\n{\n   stbtt_int32 i;\n   stbtt_int32 count = ttUSHORT(fc+nm+2);\n   stbtt_int32 stringOffset = nm + ttUSHORT(fc+nm+4);\n\n   for (i=0; i < count; ++i) {\n      stbtt_uint32 loc = nm + 6 + 12 * i;\n      stbtt_int32 id = ttUSHORT(fc+loc+6);\n      if (id == target_id) {\n         // find the encoding\n         stbtt_int32 platform = ttUSHORT(fc+loc+0), encoding = ttUSHORT(fc+loc+2), language = ttUSHORT(fc+loc+4);\n\n         // is this a Unicode encoding?\n         if (platform == 0 || (platform == 3 && encoding == 1) || (platform == 3 && encoding == 10)) {\n            stbtt_int32 slen = ttUSHORT(fc+loc+8);\n            stbtt_int32 off = ttUSHORT(fc+loc+10);\n\n            // check if there's a prefix match\n            stbtt_int32 matchlen = stbtt__CompareUTF8toUTF16_bigendian_prefix(name, nlen, fc+stringOffset+off,slen);\n            if (matchlen >= 0) {\n               // check for target_id+1 immediately following, with same encoding & language\n               if (i+1 < count && ttUSHORT(fc+loc+12+6) == next_id && ttUSHORT(fc+loc+12) == platform && ttUSHORT(fc+loc+12+2) == encoding && ttUSHORT(fc+loc+12+4) == language) {\n                  slen = ttUSHORT(fc+loc+12+8);\n                  off = ttUSHORT(fc+loc+12+10);\n                  if (slen == 0) {\n                     if (matchlen == nlen)\n                        return 1;\n                  } else if (matchlen < nlen && name[matchlen] == ' ') {\n                     ++matchlen;\n                     if (stbtt_CompareUTF8toUTF16_bigendian_internal((char*) (name+matchlen), nlen-matchlen, (char*)(fc+stringOffset+off),slen))\n                        return 1;\n                  }\n               } else {\n                  // if nothing immediately following\n                  if (matchlen == nlen)\n                     return 1;\n               }\n            }\n         }\n\n         // @TODO handle other encodings\n      }\n   }\n   return 0;\n}\n\nstatic int stbtt__matches(stbtt_uint8 *fc, stbtt_uint32 offset, stbtt_uint8 *name, stbtt_int32 flags)\n{\n   stbtt_int32 nlen = (stbtt_int32) STBTT_strlen((char *) name);\n   stbtt_uint32 nm,hd;\n   if (!stbtt__isfont(fc+offset)) return 0;\n\n   // check italics/bold/underline flags in macStyle...\n   if (flags) {\n      hd = stbtt__find_table(fc, offset, \"head\");\n      if ((ttUSHORT(fc+hd+44) & 7) != (flags & 7)) return 0;\n   }\n\n   nm = stbtt__find_table(fc, offset, \"name\");\n   if (!nm) return 0;\n\n   if (flags) {\n      // if we checked the macStyle flags, then just check the family and ignore the subfamily\n      if (stbtt__matchpair(fc, nm, name, nlen, 16, -1))  return 1;\n      if (stbtt__matchpair(fc, nm, name, nlen,  1, -1))  return 1;\n      if (stbtt__matchpair(fc, nm, name, nlen,  3, -1))  return 1;\n   } else {\n      if (stbtt__matchpair(fc, nm, name, nlen, 16, 17))  return 1;\n      if (stbtt__matchpair(fc, nm, name, nlen,  1,  2))  return 1;\n      if (stbtt__matchpair(fc, nm, name, nlen,  3, -1))  return 1;\n   }\n\n   return 0;\n}\n\nstatic int stbtt_FindMatchingFont_internal(unsigned char *font_collection, char *name_utf8, stbtt_int32 flags)\n{\n   stbtt_int32 i;\n   for (i=0;;++i) {\n      stbtt_int32 off = stbtt_GetFontOffsetForIndex(font_collection, i);\n      if (off < 0) return off;\n      if (stbtt__matches((stbtt_uint8 *) font_collection, off, (stbtt_uint8*) name_utf8, flags))\n         return off;\n   }\n}\n\n#if defined(__GNUC__) || defined(__clang__)\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wcast-qual\"\n#endif\n\nSTBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset,\n                                float pixel_height, unsigned char *pixels, int pw, int ph,\n                                int first_char, int num_chars, stbtt_bakedchar *chardata)\n{\n   return stbtt_BakeFontBitmap_internal((unsigned char *) data, offset, pixel_height, pixels, pw, ph, first_char, num_chars, chardata);\n}\n\nSTBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *data, int index)\n{\n   return stbtt_GetFontOffsetForIndex_internal((unsigned char *) data, index);\n}\n\nSTBTT_DEF int stbtt_GetNumberOfFonts(const unsigned char *data)\n{\n   return stbtt_GetNumberOfFonts_internal((unsigned char *) data);\n}\n\nSTBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data, int offset)\n{\n   return stbtt_InitFont_internal(info, (unsigned char *) data, offset);\n}\n\nSTBTT_DEF int stbtt_FindMatchingFont(const unsigned char *fontdata, const char *name, int flags)\n{\n   return stbtt_FindMatchingFont_internal((unsigned char *) fontdata, (char *) name, flags);\n}\n\nSTBTT_DEF int stbtt_CompareUTF8toUTF16_bigendian(const char *s1, int len1, const char *s2, int len2)\n{\n   return stbtt_CompareUTF8toUTF16_bigendian_internal((char *) s1, len1, (char *) s2, len2);\n}\n\n#if defined(__GNUC__) || defined(__clang__)\n#pragma GCC diagnostic pop\n#endif\n\n#endif // STB_TRUETYPE_IMPLEMENTATION\n\n\n// FULL VERSION HISTORY\n//\n//   1.19 (2018-02-11) OpenType GPOS kerning (horizontal only), STBTT_fmod\n//   1.18 (2018-01-29) add missing function\n//   1.17 (2017-07-23) make more arguments const; doc fix\n//   1.16 (2017-07-12) SDF support\n//   1.15 (2017-03-03) make more arguments const\n//   1.14 (2017-01-16) num-fonts-in-TTC function\n//   1.13 (2017-01-02) support OpenType fonts, certain Apple fonts\n//   1.12 (2016-10-25) suppress warnings about casting away const with -Wcast-qual\n//   1.11 (2016-04-02) fix unused-variable warning\n//   1.10 (2016-04-02) allow user-defined fabs() replacement\n//                     fix memory leak if fontsize=0.0\n//                     fix warning from duplicate typedef\n//   1.09 (2016-01-16) warning fix; avoid crash on outofmem; use alloc userdata for PackFontRanges\n//   1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges\n//   1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints;\n//                     allow PackFontRanges to pack and render in separate phases;\n//                     fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?);\n//                     fixed an assert() bug in the new rasterizer\n//                     replace assert() with STBTT_assert() in new rasterizer\n//   1.06 (2015-07-14) performance improvements (~35% faster on x86 and x64 on test machine)\n//                     also more precise AA rasterizer, except if shapes overlap\n//                     remove need for STBTT_sort\n//   1.05 (2015-04-15) fix misplaced definitions for STBTT_STATIC\n//   1.04 (2015-04-15) typo in example\n//   1.03 (2015-04-12) STBTT_STATIC, fix memory leak in new packing, various fixes\n//   1.02 (2014-12-10) fix various warnings & compile issues w/ stb_rect_pack, C++\n//   1.01 (2014-12-08) fix subpixel position when oversampling to exactly match\n//                        non-oversampled; STBTT_POINT_SIZE for packed case only\n//   1.00 (2014-12-06) add new PackBegin etc. API, w/ support for oversampling\n//   0.99 (2014-09-18) fix multiple bugs with subpixel rendering (ryg)\n//   0.9  (2014-08-07) support certain mac/iOS fonts without an MS platformID\n//   0.8b (2014-07-07) fix a warning\n//   0.8  (2014-05-25) fix a few more warnings\n//   0.7  (2013-09-25) bugfix: subpixel glyph bug fixed in 0.5 had come back\n//   0.6c (2012-07-24) improve documentation\n//   0.6b (2012-07-20) fix a few more warnings\n//   0.6  (2012-07-17) fix warnings; added stbtt_ScaleForMappingEmToPixels,\n//                        stbtt_GetFontBoundingBox, stbtt_IsGlyphEmpty\n//   0.5  (2011-12-09) bugfixes:\n//                        subpixel glyph renderer computed wrong bounding box\n//                        first vertex of shape can be off-curve (FreeSans)\n//   0.4b (2011-12-03) fixed an error in the font baking example\n//   0.4  (2011-12-01) kerning, subpixel rendering (tor)\n//                    bugfixes for:\n//                        codepoint-to-glyph conversion using table fmt=12\n//                        codepoint-to-glyph conversion using table fmt=4\n//                        stbtt_GetBakedQuad with non-square texture (Zer)\n//                    updated Hello World! sample to use kerning and subpixel\n//                    fixed some warnings\n//   0.3  (2009-06-24) cmap fmt=12, compound shapes (MM)\n//                    userdata, malloc-from-userdata, non-zero fill (stb)\n//   0.2  (2009-03-11) Fix unsigned/signed char warnings\n//   0.1  (2009-03-09) First public release\n//\n\n/*\n------------------------------------------------------------------------------\nThis software is available under 2 licenses -- choose whichever you prefer.\n------------------------------------------------------------------------------\nALTERNATIVE A - MIT License\nCopyright (c) 2017 Sean Barrett\nPermission is hereby granted, free of charge, to any person obtaining a copy of\nthis software and associated documentation files (the \"Software\"), to deal in\nthe Software without restriction, including without limitation the rights to\nuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies\nof the Software, and to permit persons to whom the Software is furnished to do\nso, subject to the following conditions:\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n------------------------------------------------------------------------------\nALTERNATIVE B - Public Domain (www.unlicense.org)\nThis is free and unencumbered software released into the public domain.\nAnyone is free to copy, modify, publish, use, compile, sell, or distribute this\nsoftware, either in source code form or as a compiled binary, for any purpose,\ncommercial or non-commercial, and by any means.\nIn jurisdictions that recognize copyright laws, the author or authors of this\nsoftware dedicate any and all copyright interest in the software to the public\ndomain. We make this dedication for the benefit of the public at large and to\nthe detriment of our heirs and successors. We intend this dedication to be an\novert act of relinquishment in perpetuity of all present and future rights to\nthis software under copyright law.\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\nACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\nWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n------------------------------------------------------------------------------\n*/\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl.h",
    "content": "/*******************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n ******************************************************************************/\n\n#ifndef __OPENCL_CL_H\n#define __OPENCL_CL_H\n\n#ifdef __APPLE__\n#include <OpenCL/cl_platform.h>\n#else\n#include <CL/cl_platform.h>\n#endif\t\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/******************************************************************************/\n\ntypedef struct _cl_platform_id *    cl_platform_id;\ntypedef struct _cl_device_id *      cl_device_id;\ntypedef struct _cl_context *        cl_context;\ntypedef struct _cl_command_queue *  cl_command_queue;\ntypedef struct _cl_mem *            cl_mem;\ntypedef struct _cl_program *        cl_program;\ntypedef struct _cl_kernel *         cl_kernel;\ntypedef struct _cl_event *          cl_event;\ntypedef struct _cl_sampler *        cl_sampler;\n\ntypedef cl_uint             cl_bool;                     /* WARNING!  Unlike cl_ types in cl_platform.h, cl_bool is not guaranteed to be the same size as the bool in kernels. */ \ntypedef cl_ulong            cl_bitfield;\ntypedef cl_bitfield         cl_device_type;\ntypedef cl_uint             cl_platform_info;\ntypedef cl_uint             cl_device_info;\ntypedef cl_bitfield         cl_device_fp_config;\ntypedef cl_uint             cl_device_mem_cache_type;\ntypedef cl_uint             cl_device_local_mem_type;\ntypedef cl_bitfield         cl_device_exec_capabilities;\ntypedef cl_bitfield         cl_device_svm_capabilities;\ntypedef cl_bitfield         cl_command_queue_properties;\ntypedef intptr_t            cl_device_partition_property;\ntypedef cl_bitfield         cl_device_affinity_domain;\n\ntypedef intptr_t            cl_context_properties;\ntypedef cl_uint             cl_context_info;\ntypedef cl_bitfield         cl_queue_properties;\ntypedef cl_uint             cl_command_queue_info;\ntypedef cl_uint             cl_channel_order;\ntypedef cl_uint             cl_channel_type;\ntypedef cl_bitfield         cl_mem_flags;\ntypedef cl_bitfield         cl_svm_mem_flags;\ntypedef cl_uint             cl_mem_object_type;\ntypedef cl_uint             cl_mem_info;\ntypedef cl_bitfield         cl_mem_migration_flags;\ntypedef cl_uint             cl_image_info;\ntypedef cl_uint             cl_buffer_create_type;\ntypedef cl_uint             cl_addressing_mode;\ntypedef cl_uint             cl_filter_mode;\ntypedef cl_uint             cl_sampler_info;\ntypedef cl_bitfield         cl_map_flags;\ntypedef intptr_t            cl_pipe_properties;\ntypedef cl_uint             cl_pipe_info;\ntypedef cl_uint             cl_program_info;\ntypedef cl_uint             cl_program_build_info;\ntypedef cl_uint             cl_program_binary_type;\ntypedef cl_int              cl_build_status;\ntypedef cl_uint             cl_kernel_info;\ntypedef cl_uint             cl_kernel_arg_info;\ntypedef cl_uint             cl_kernel_arg_address_qualifier;\ntypedef cl_uint             cl_kernel_arg_access_qualifier;\ntypedef cl_bitfield         cl_kernel_arg_type_qualifier;\ntypedef cl_uint             cl_kernel_work_group_info;\ntypedef cl_uint             cl_kernel_sub_group_info;\ntypedef cl_uint             cl_event_info;\ntypedef cl_uint             cl_command_type;\ntypedef cl_uint             cl_profiling_info;\ntypedef cl_bitfield         cl_sampler_properties;\ntypedef cl_uint             cl_kernel_exec_info;\n\ntypedef struct _cl_image_format {\n    cl_channel_order        image_channel_order;\n    cl_channel_type         image_channel_data_type;\n} cl_image_format;\n\ntypedef struct _cl_image_desc {\n    cl_mem_object_type      image_type;\n    size_t                  image_width;\n    size_t                  image_height;\n    size_t                  image_depth;\n    size_t                  image_array_size;\n    size_t                  image_row_pitch;\n    size_t                  image_slice_pitch;\n    cl_uint                 num_mip_levels;\n    cl_uint                 num_samples;\n#ifdef __GNUC__\n    __extension__   /* Prevents warnings about anonymous union in -pedantic builds */\n#endif\n    union {\n      cl_mem                  buffer;\n      cl_mem                  mem_object;\n    };\n} cl_image_desc;\n\ntypedef struct _cl_buffer_region {\n    size_t                  origin;\n    size_t                  size;\n} cl_buffer_region;\n\n\n/******************************************************************************/\n\n/* Error Codes */\n#define CL_SUCCESS                                  0\n#define CL_DEVICE_NOT_FOUND                         -1\n#define CL_DEVICE_NOT_AVAILABLE                     -2\n#define CL_COMPILER_NOT_AVAILABLE                   -3\n#define CL_MEM_OBJECT_ALLOCATION_FAILURE            -4\n#define CL_OUT_OF_RESOURCES                         -5\n#define CL_OUT_OF_HOST_MEMORY                       -6\n#define CL_PROFILING_INFO_NOT_AVAILABLE             -7\n#define CL_MEM_COPY_OVERLAP                         -8\n#define CL_IMAGE_FORMAT_MISMATCH                    -9\n#define CL_IMAGE_FORMAT_NOT_SUPPORTED               -10\n#define CL_BUILD_PROGRAM_FAILURE                    -11\n#define CL_MAP_FAILURE                              -12\n#define CL_MISALIGNED_SUB_BUFFER_OFFSET             -13\n#define CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST -14\n#define CL_COMPILE_PROGRAM_FAILURE                  -15\n#define CL_LINKER_NOT_AVAILABLE                     -16\n#define CL_LINK_PROGRAM_FAILURE                     -17\n#define CL_DEVICE_PARTITION_FAILED                  -18\n#define CL_KERNEL_ARG_INFO_NOT_AVAILABLE            -19\n\n#define CL_INVALID_VALUE                            -30\n#define CL_INVALID_DEVICE_TYPE                      -31\n#define CL_INVALID_PLATFORM                         -32\n#define CL_INVALID_DEVICE                           -33\n#define CL_INVALID_CONTEXT                          -34\n#define CL_INVALID_QUEUE_PROPERTIES                 -35\n#define CL_INVALID_COMMAND_QUEUE                    -36\n#define CL_INVALID_HOST_PTR                         -37\n#define CL_INVALID_MEM_OBJECT                       -38\n#define CL_INVALID_IMAGE_FORMAT_DESCRIPTOR          -39\n#define CL_INVALID_IMAGE_SIZE                       -40\n#define CL_INVALID_SAMPLER                          -41\n#define CL_INVALID_BINARY                           -42\n#define CL_INVALID_BUILD_OPTIONS                    -43\n#define CL_INVALID_PROGRAM                          -44\n#define CL_INVALID_PROGRAM_EXECUTABLE               -45\n#define CL_INVALID_KERNEL_NAME                      -46\n#define CL_INVALID_KERNEL_DEFINITION                -47\n#define CL_INVALID_KERNEL                           -48\n#define CL_INVALID_ARG_INDEX                        -49\n#define CL_INVALID_ARG_VALUE                        -50\n#define CL_INVALID_ARG_SIZE                         -51\n#define CL_INVALID_KERNEL_ARGS                      -52\n#define CL_INVALID_WORK_DIMENSION                   -53\n#define CL_INVALID_WORK_GROUP_SIZE                  -54\n#define CL_INVALID_WORK_ITEM_SIZE                   -55\n#define CL_INVALID_GLOBAL_OFFSET                    -56\n#define CL_INVALID_EVENT_WAIT_LIST                  -57\n#define CL_INVALID_EVENT                            -58\n#define CL_INVALID_OPERATION                        -59\n#define CL_INVALID_GL_OBJECT                        -60\n#define CL_INVALID_BUFFER_SIZE                      -61\n#define CL_INVALID_MIP_LEVEL                        -62\n#define CL_INVALID_GLOBAL_WORK_SIZE                 -63\n#define CL_INVALID_PROPERTY                         -64\n#define CL_INVALID_IMAGE_DESCRIPTOR                 -65\n#define CL_INVALID_COMPILER_OPTIONS                 -66\n#define CL_INVALID_LINKER_OPTIONS                   -67\n#define CL_INVALID_DEVICE_PARTITION_COUNT           -68\n#define CL_INVALID_PIPE_SIZE                        -69\n#define CL_INVALID_DEVICE_QUEUE                     -70\n\n/* OpenCL Version */\n#define CL_VERSION_1_0                              1\n#define CL_VERSION_1_1                              1\n#define CL_VERSION_1_2                              1\n#define CL_VERSION_2_0                              1\n#define CL_VERSION_2_1                              1\n\n/* cl_bool */\n#define CL_FALSE                                    0\n#define CL_TRUE                                     1\n#define CL_BLOCKING                                 CL_TRUE\n#define CL_NON_BLOCKING                             CL_FALSE\n\n/* cl_platform_info */\n#define CL_PLATFORM_PROFILE                         0x0900\n#define CL_PLATFORM_VERSION                         0x0901\n#define CL_PLATFORM_NAME                            0x0902\n#define CL_PLATFORM_VENDOR                          0x0903\n#define CL_PLATFORM_EXTENSIONS                      0x0904\n#define CL_PLATFORM_HOST_TIMER_RESOLUTION           0x0905\n\n/* cl_device_type - bitfield */\n#define CL_DEVICE_TYPE_DEFAULT                      (1 << 0)\n#define CL_DEVICE_TYPE_CPU                          (1 << 1)\n#define CL_DEVICE_TYPE_GPU                          (1 << 2)\n#define CL_DEVICE_TYPE_ACCELERATOR                  (1 << 3)\n#define CL_DEVICE_TYPE_CUSTOM                       (1 << 4)\n#define CL_DEVICE_TYPE_ALL                          0xFFFFFFFF\n\n/* cl_device_info */\n#define CL_DEVICE_TYPE                                   0x1000\n#define CL_DEVICE_VENDOR_ID                              0x1001\n#define CL_DEVICE_MAX_COMPUTE_UNITS                      0x1002\n#define CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS               0x1003\n#define CL_DEVICE_MAX_WORK_GROUP_SIZE                    0x1004\n#define CL_DEVICE_MAX_WORK_ITEM_SIZES                    0x1005\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR            0x1006\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT           0x1007\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT             0x1008\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG            0x1009\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT           0x100A\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE          0x100B\n#define CL_DEVICE_MAX_CLOCK_FREQUENCY                    0x100C\n#define CL_DEVICE_ADDRESS_BITS                           0x100D\n#define CL_DEVICE_MAX_READ_IMAGE_ARGS                    0x100E\n#define CL_DEVICE_MAX_WRITE_IMAGE_ARGS                   0x100F\n#define CL_DEVICE_MAX_MEM_ALLOC_SIZE                     0x1010\n#define CL_DEVICE_IMAGE2D_MAX_WIDTH                      0x1011\n#define CL_DEVICE_IMAGE2D_MAX_HEIGHT                     0x1012\n#define CL_DEVICE_IMAGE3D_MAX_WIDTH                      0x1013\n#define CL_DEVICE_IMAGE3D_MAX_HEIGHT                     0x1014\n#define CL_DEVICE_IMAGE3D_MAX_DEPTH                      0x1015\n#define CL_DEVICE_IMAGE_SUPPORT                          0x1016\n#define CL_DEVICE_MAX_PARAMETER_SIZE                     0x1017\n#define CL_DEVICE_MAX_SAMPLERS                           0x1018\n#define CL_DEVICE_MEM_BASE_ADDR_ALIGN                    0x1019\n#define CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE               0x101A\n#define CL_DEVICE_SINGLE_FP_CONFIG                       0x101B\n#define CL_DEVICE_GLOBAL_MEM_CACHE_TYPE                  0x101C\n#define CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE              0x101D\n#define CL_DEVICE_GLOBAL_MEM_CACHE_SIZE                  0x101E\n#define CL_DEVICE_GLOBAL_MEM_SIZE                        0x101F\n#define CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE               0x1020\n#define CL_DEVICE_MAX_CONSTANT_ARGS                      0x1021\n#define CL_DEVICE_LOCAL_MEM_TYPE                         0x1022\n#define CL_DEVICE_LOCAL_MEM_SIZE                         0x1023\n#define CL_DEVICE_ERROR_CORRECTION_SUPPORT               0x1024\n#define CL_DEVICE_PROFILING_TIMER_RESOLUTION             0x1025\n#define CL_DEVICE_ENDIAN_LITTLE                          0x1026\n#define CL_DEVICE_AVAILABLE                              0x1027\n#define CL_DEVICE_COMPILER_AVAILABLE                     0x1028\n#define CL_DEVICE_EXECUTION_CAPABILITIES                 0x1029\n#define CL_DEVICE_QUEUE_PROPERTIES                       0x102A    /* deprecated */\n#define CL_DEVICE_QUEUE_ON_HOST_PROPERTIES               0x102A\n#define CL_DEVICE_NAME                                   0x102B\n#define CL_DEVICE_VENDOR                                 0x102C\n#define CL_DRIVER_VERSION                                0x102D\n#define CL_DEVICE_PROFILE                                0x102E\n#define CL_DEVICE_VERSION                                0x102F\n#define CL_DEVICE_EXTENSIONS                             0x1030\n#define CL_DEVICE_PLATFORM                               0x1031\n#define CL_DEVICE_DOUBLE_FP_CONFIG                       0x1032\n/* 0x1033 reserved for CL_DEVICE_HALF_FP_CONFIG */\n#define CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF            0x1034\n#define CL_DEVICE_HOST_UNIFIED_MEMORY                    0x1035   /* deprecated */\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR               0x1036\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT              0x1037\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_INT                0x1038\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG               0x1039\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT              0x103A\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE             0x103B\n#define CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF               0x103C\n#define CL_DEVICE_OPENCL_C_VERSION                       0x103D\n#define CL_DEVICE_LINKER_AVAILABLE                       0x103E\n#define CL_DEVICE_BUILT_IN_KERNELS                       0x103F\n#define CL_DEVICE_IMAGE_MAX_BUFFER_SIZE                  0x1040\n#define CL_DEVICE_IMAGE_MAX_ARRAY_SIZE                   0x1041\n#define CL_DEVICE_PARENT_DEVICE                          0x1042\n#define CL_DEVICE_PARTITION_MAX_SUB_DEVICES              0x1043\n#define CL_DEVICE_PARTITION_PROPERTIES                   0x1044\n#define CL_DEVICE_PARTITION_AFFINITY_DOMAIN              0x1045\n#define CL_DEVICE_PARTITION_TYPE                         0x1046\n#define CL_DEVICE_REFERENCE_COUNT                        0x1047\n#define CL_DEVICE_PREFERRED_INTEROP_USER_SYNC            0x1048\n#define CL_DEVICE_PRINTF_BUFFER_SIZE                     0x1049\n#define CL_DEVICE_IMAGE_PITCH_ALIGNMENT                  0x104A\n#define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT           0x104B\n#define CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS              0x104C\n#define CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE               0x104D\n#define CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES             0x104E\n#define CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE         0x104F\n#define CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE               0x1050\n#define CL_DEVICE_MAX_ON_DEVICE_QUEUES                   0x1051\n#define CL_DEVICE_MAX_ON_DEVICE_EVENTS                   0x1052\n#define CL_DEVICE_SVM_CAPABILITIES                       0x1053\n#define CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE   0x1054\n#define CL_DEVICE_MAX_PIPE_ARGS                          0x1055\n#define CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS           0x1056\n#define CL_DEVICE_PIPE_MAX_PACKET_SIZE                   0x1057\n#define CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT    0x1058\n#define CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT      0x1059\n#define CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT       0x105A\n#define CL_DEVICE_IL_VERSION                             0x105B\n#define CL_DEVICE_MAX_NUM_SUB_GROUPS                     0x105C\n#define CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS 0x105D\n\n/* cl_device_fp_config - bitfield */\n#define CL_FP_DENORM                                (1 << 0)\n#define CL_FP_INF_NAN                               (1 << 1)\n#define CL_FP_ROUND_TO_NEAREST                      (1 << 2)\n#define CL_FP_ROUND_TO_ZERO                         (1 << 3)\n#define CL_FP_ROUND_TO_INF                          (1 << 4)\n#define CL_FP_FMA                                   (1 << 5)\n#define CL_FP_SOFT_FLOAT                            (1 << 6)\n#define CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT         (1 << 7)\n\n/* cl_device_mem_cache_type */\n#define CL_NONE                                     0x0\n#define CL_READ_ONLY_CACHE                          0x1\n#define CL_READ_WRITE_CACHE                         0x2\n\n/* cl_device_local_mem_type */\n#define CL_LOCAL                                    0x1\n#define CL_GLOBAL                                   0x2\n\n/* cl_device_exec_capabilities - bitfield */\n#define CL_EXEC_KERNEL                              (1 << 0)\n#define CL_EXEC_NATIVE_KERNEL                       (1 << 1)\n\n/* cl_command_queue_properties - bitfield */\n#define CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE      (1 << 0)\n#define CL_QUEUE_PROFILING_ENABLE                   (1 << 1)\n#define CL_QUEUE_ON_DEVICE                          (1 << 2)\n#define CL_QUEUE_ON_DEVICE_DEFAULT                  (1 << 3)\n\n/* cl_context_info  */\n#define CL_CONTEXT_REFERENCE_COUNT                  0x1080\n#define CL_CONTEXT_DEVICES                          0x1081\n#define CL_CONTEXT_PROPERTIES                       0x1082\n#define CL_CONTEXT_NUM_DEVICES                      0x1083\n\n/* cl_context_properties */\n#define CL_CONTEXT_PLATFORM                         0x1084\n#define CL_CONTEXT_INTEROP_USER_SYNC                0x1085\n    \n/* cl_device_partition_property */\n#define CL_DEVICE_PARTITION_EQUALLY                 0x1086\n#define CL_DEVICE_PARTITION_BY_COUNTS               0x1087\n#define CL_DEVICE_PARTITION_BY_COUNTS_LIST_END      0x0\n#define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN      0x1088\n    \n/* cl_device_affinity_domain */\n#define CL_DEVICE_AFFINITY_DOMAIN_NUMA               (1 << 0)\n#define CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE           (1 << 1)\n#define CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE           (1 << 2)\n#define CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE           (1 << 3)\n#define CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE           (1 << 4)\n#define CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE (1 << 5)\n    \n/* cl_device_svm_capabilities */\n#define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER           (1 << 0)\n#define CL_DEVICE_SVM_FINE_GRAIN_BUFFER             (1 << 1)\n#define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM             (1 << 2)\n#define CL_DEVICE_SVM_ATOMICS                       (1 << 3)\n\n/* cl_command_queue_info */\n#define CL_QUEUE_CONTEXT                            0x1090\n#define CL_QUEUE_DEVICE                             0x1091\n#define CL_QUEUE_REFERENCE_COUNT                    0x1092\n#define CL_QUEUE_PROPERTIES                         0x1093\n#define CL_QUEUE_SIZE                               0x1094\n#define CL_QUEUE_DEVICE_DEFAULT                     0x1095\n\n/* cl_mem_flags and cl_svm_mem_flags - bitfield */\n#define CL_MEM_READ_WRITE                           (1 << 0)\n#define CL_MEM_WRITE_ONLY                           (1 << 1)\n#define CL_MEM_READ_ONLY                            (1 << 2)\n#define CL_MEM_USE_HOST_PTR                         (1 << 3)\n#define CL_MEM_ALLOC_HOST_PTR                       (1 << 4)\n#define CL_MEM_COPY_HOST_PTR                        (1 << 5)\n/* reserved                                         (1 << 6)    */\n#define CL_MEM_HOST_WRITE_ONLY                      (1 << 7)\n#define CL_MEM_HOST_READ_ONLY                       (1 << 8)\n#define CL_MEM_HOST_NO_ACCESS                       (1 << 9)\n#define CL_MEM_SVM_FINE_GRAIN_BUFFER                (1 << 10)   /* used by cl_svm_mem_flags only */\n#define CL_MEM_SVM_ATOMICS                          (1 << 11)   /* used by cl_svm_mem_flags only */\n#define CL_MEM_KERNEL_READ_AND_WRITE                (1 << 12)\n\n/* cl_mem_migration_flags - bitfield */\n#define CL_MIGRATE_MEM_OBJECT_HOST                  (1 << 0)\n#define CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED     (1 << 1)\n\n/* cl_channel_order */\n#define CL_R                                        0x10B0\n#define CL_A                                        0x10B1\n#define CL_RG                                       0x10B2\n#define CL_RA                                       0x10B3\n#define CL_RGB                                      0x10B4\n#define CL_RGBA                                     0x10B5\n#define CL_BGRA                                     0x10B6\n#define CL_ARGB                                     0x10B7\n#define CL_INTENSITY                                0x10B8\n#define CL_LUMINANCE                                0x10B9\n#define CL_Rx                                       0x10BA\n#define CL_RGx                                      0x10BB\n#define CL_RGBx                                     0x10BC\n#define CL_DEPTH                                    0x10BD\n#define CL_DEPTH_STENCIL                            0x10BE\n#define CL_sRGB                                     0x10BF\n#define CL_sRGBx                                    0x10C0\n#define CL_sRGBA                                    0x10C1\n#define CL_sBGRA                                    0x10C2\n#define CL_ABGR                                     0x10C3\n\n/* cl_channel_type */\n#define CL_SNORM_INT8                               0x10D0\n#define CL_SNORM_INT16                              0x10D1\n#define CL_UNORM_INT8                               0x10D2\n#define CL_UNORM_INT16                              0x10D3\n#define CL_UNORM_SHORT_565                          0x10D4\n#define CL_UNORM_SHORT_555                          0x10D5\n#define CL_UNORM_INT_101010                         0x10D6\n#define CL_SIGNED_INT8                              0x10D7\n#define CL_SIGNED_INT16                             0x10D8\n#define CL_SIGNED_INT32                             0x10D9\n#define CL_UNSIGNED_INT8                            0x10DA\n#define CL_UNSIGNED_INT16                           0x10DB\n#define CL_UNSIGNED_INT32                           0x10DC\n#define CL_HALF_FLOAT                               0x10DD\n#define CL_FLOAT                                    0x10DE\n#define CL_UNORM_INT24                              0x10DF\n#define CL_UNORM_INT_101010_2                       0x10E0\n\n/* cl_mem_object_type */\n#define CL_MEM_OBJECT_BUFFER                        0x10F0\n#define CL_MEM_OBJECT_IMAGE2D                       0x10F1\n#define CL_MEM_OBJECT_IMAGE3D                       0x10F2\n#define CL_MEM_OBJECT_IMAGE2D_ARRAY                 0x10F3\n#define CL_MEM_OBJECT_IMAGE1D                       0x10F4\n#define CL_MEM_OBJECT_IMAGE1D_ARRAY                 0x10F5\n#define CL_MEM_OBJECT_IMAGE1D_BUFFER                0x10F6\n#define CL_MEM_OBJECT_PIPE                          0x10F7\n\n/* cl_mem_info */\n#define CL_MEM_TYPE                                 0x1100\n#define CL_MEM_FLAGS                                0x1101\n#define CL_MEM_SIZE                                 0x1102\n#define CL_MEM_HOST_PTR                             0x1103\n#define CL_MEM_MAP_COUNT                            0x1104\n#define CL_MEM_REFERENCE_COUNT                      0x1105\n#define CL_MEM_CONTEXT                              0x1106\n#define CL_MEM_ASSOCIATED_MEMOBJECT                 0x1107\n#define CL_MEM_OFFSET                               0x1108\n#define CL_MEM_USES_SVM_POINTER                     0x1109\n\n/* cl_image_info */\n#define CL_IMAGE_FORMAT                             0x1110\n#define CL_IMAGE_ELEMENT_SIZE                       0x1111\n#define CL_IMAGE_ROW_PITCH                          0x1112\n#define CL_IMAGE_SLICE_PITCH                        0x1113\n#define CL_IMAGE_WIDTH                              0x1114\n#define CL_IMAGE_HEIGHT                             0x1115\n#define CL_IMAGE_DEPTH                              0x1116\n#define CL_IMAGE_ARRAY_SIZE                         0x1117\n#define CL_IMAGE_BUFFER                             0x1118\n#define CL_IMAGE_NUM_MIP_LEVELS                     0x1119\n#define CL_IMAGE_NUM_SAMPLES                        0x111A\n    \n/* cl_pipe_info */\n#define CL_PIPE_PACKET_SIZE                         0x1120\n#define CL_PIPE_MAX_PACKETS                         0x1121\n\n/* cl_addressing_mode */\n#define CL_ADDRESS_NONE                             0x1130\n#define CL_ADDRESS_CLAMP_TO_EDGE                    0x1131\n#define CL_ADDRESS_CLAMP                            0x1132\n#define CL_ADDRESS_REPEAT                           0x1133\n#define CL_ADDRESS_MIRRORED_REPEAT                  0x1134\n\n/* cl_filter_mode */\n#define CL_FILTER_NEAREST                           0x1140\n#define CL_FILTER_LINEAR                            0x1141\n\n/* cl_sampler_info */\n#define CL_SAMPLER_REFERENCE_COUNT                  0x1150\n#define CL_SAMPLER_CONTEXT                          0x1151\n#define CL_SAMPLER_NORMALIZED_COORDS                0x1152\n#define CL_SAMPLER_ADDRESSING_MODE                  0x1153\n#define CL_SAMPLER_FILTER_MODE                      0x1154\n#define CL_SAMPLER_MIP_FILTER_MODE                  0x1155\n#define CL_SAMPLER_LOD_MIN                          0x1156\n#define CL_SAMPLER_LOD_MAX                          0x1157\n\n/* cl_map_flags - bitfield */\n#define CL_MAP_READ                                 (1 << 0)\n#define CL_MAP_WRITE                                (1 << 1)\n#define CL_MAP_WRITE_INVALIDATE_REGION              (1 << 2)\n\n/* cl_program_info */\n#define CL_PROGRAM_REFERENCE_COUNT                  0x1160\n#define CL_PROGRAM_CONTEXT                          0x1161\n#define CL_PROGRAM_NUM_DEVICES                      0x1162\n#define CL_PROGRAM_DEVICES                          0x1163\n#define CL_PROGRAM_SOURCE                           0x1164\n#define CL_PROGRAM_BINARY_SIZES                     0x1165\n#define CL_PROGRAM_BINARIES                         0x1166\n#define CL_PROGRAM_NUM_KERNELS                      0x1167\n#define CL_PROGRAM_KERNEL_NAMES                     0x1168\n#define CL_PROGRAM_IL                               0x1169\n\n/* cl_program_build_info */\n#define CL_PROGRAM_BUILD_STATUS                     0x1181\n#define CL_PROGRAM_BUILD_OPTIONS                    0x1182\n#define CL_PROGRAM_BUILD_LOG                        0x1183\n#define CL_PROGRAM_BINARY_TYPE                      0x1184\n#define CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE 0x1185\n    \n/* cl_program_binary_type */\n#define CL_PROGRAM_BINARY_TYPE_NONE                 0x0\n#define CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT      0x1\n#define CL_PROGRAM_BINARY_TYPE_LIBRARY              0x2\n#define CL_PROGRAM_BINARY_TYPE_EXECUTABLE           0x4\n\n/* cl_build_status */\n#define CL_BUILD_SUCCESS                            0\n#define CL_BUILD_NONE                               -1\n#define CL_BUILD_ERROR                              -2\n#define CL_BUILD_IN_PROGRESS                        -3\n\n/* cl_kernel_info */\n#define CL_KERNEL_FUNCTION_NAME                     0x1190\n#define CL_KERNEL_NUM_ARGS                          0x1191\n#define CL_KERNEL_REFERENCE_COUNT                   0x1192\n#define CL_KERNEL_CONTEXT                           0x1193\n#define CL_KERNEL_PROGRAM                           0x1194\n#define CL_KERNEL_ATTRIBUTES                        0x1195\n#define CL_KERNEL_MAX_NUM_SUB_GROUPS                0x11B9\n#define CL_KERNEL_COMPILE_NUM_SUB_GROUPS            0x11BA\n\n/* cl_kernel_arg_info */\n#define CL_KERNEL_ARG_ADDRESS_QUALIFIER             0x1196\n#define CL_KERNEL_ARG_ACCESS_QUALIFIER              0x1197\n#define CL_KERNEL_ARG_TYPE_NAME                     0x1198\n#define CL_KERNEL_ARG_TYPE_QUALIFIER                0x1199\n#define CL_KERNEL_ARG_NAME                          0x119A\n\n/* cl_kernel_arg_address_qualifier */\n#define CL_KERNEL_ARG_ADDRESS_GLOBAL                0x119B\n#define CL_KERNEL_ARG_ADDRESS_LOCAL                 0x119C\n#define CL_KERNEL_ARG_ADDRESS_CONSTANT              0x119D\n#define CL_KERNEL_ARG_ADDRESS_PRIVATE               0x119E\n\n/* cl_kernel_arg_access_qualifier */\n#define CL_KERNEL_ARG_ACCESS_READ_ONLY              0x11A0\n#define CL_KERNEL_ARG_ACCESS_WRITE_ONLY             0x11A1\n#define CL_KERNEL_ARG_ACCESS_READ_WRITE             0x11A2\n#define CL_KERNEL_ARG_ACCESS_NONE                   0x11A3\n    \n/* cl_kernel_arg_type_qualifer */\n#define CL_KERNEL_ARG_TYPE_NONE                     0\n#define CL_KERNEL_ARG_TYPE_CONST                    (1 << 0)\n#define CL_KERNEL_ARG_TYPE_RESTRICT                 (1 << 1)\n#define CL_KERNEL_ARG_TYPE_VOLATILE                 (1 << 2)\n#define CL_KERNEL_ARG_TYPE_PIPE                     (1 << 3)\n\n/* cl_kernel_work_group_info */\n#define CL_KERNEL_WORK_GROUP_SIZE                   0x11B0\n#define CL_KERNEL_COMPILE_WORK_GROUP_SIZE           0x11B1\n#define CL_KERNEL_LOCAL_MEM_SIZE                    0x11B2\n#define CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE 0x11B3\n#define CL_KERNEL_PRIVATE_MEM_SIZE                  0x11B4\n#define CL_KERNEL_GLOBAL_WORK_SIZE                  0x11B5\n\n/* cl_kernel_sub_group_info */\n#define CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE    0x2033\n#define CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE       0x2034\n#define CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT    0x11B8\n    \n/* cl_kernel_exec_info */\n#define CL_KERNEL_EXEC_INFO_SVM_PTRS                0x11B6\n#define CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM   0x11B7\n\n/* cl_event_info  */\n#define CL_EVENT_COMMAND_QUEUE                      0x11D0\n#define CL_EVENT_COMMAND_TYPE                       0x11D1\n#define CL_EVENT_REFERENCE_COUNT                    0x11D2\n#define CL_EVENT_COMMAND_EXECUTION_STATUS           0x11D3\n#define CL_EVENT_CONTEXT                            0x11D4\n\n/* cl_command_type */\n#define CL_COMMAND_NDRANGE_KERNEL                   0x11F0\n#define CL_COMMAND_TASK                             0x11F1\n#define CL_COMMAND_NATIVE_KERNEL                    0x11F2\n#define CL_COMMAND_READ_BUFFER                      0x11F3\n#define CL_COMMAND_WRITE_BUFFER                     0x11F4\n#define CL_COMMAND_COPY_BUFFER                      0x11F5\n#define CL_COMMAND_READ_IMAGE                       0x11F6\n#define CL_COMMAND_WRITE_IMAGE                      0x11F7\n#define CL_COMMAND_COPY_IMAGE                       0x11F8\n#define CL_COMMAND_COPY_IMAGE_TO_BUFFER             0x11F9\n#define CL_COMMAND_COPY_BUFFER_TO_IMAGE             0x11FA\n#define CL_COMMAND_MAP_BUFFER                       0x11FB\n#define CL_COMMAND_MAP_IMAGE                        0x11FC\n#define CL_COMMAND_UNMAP_MEM_OBJECT                 0x11FD\n#define CL_COMMAND_MARKER                           0x11FE\n#define CL_COMMAND_ACQUIRE_GL_OBJECTS               0x11FF\n#define CL_COMMAND_RELEASE_GL_OBJECTS               0x1200\n#define CL_COMMAND_READ_BUFFER_RECT                 0x1201\n#define CL_COMMAND_WRITE_BUFFER_RECT                0x1202\n#define CL_COMMAND_COPY_BUFFER_RECT                 0x1203\n#define CL_COMMAND_USER                             0x1204\n#define CL_COMMAND_BARRIER                          0x1205\n#define CL_COMMAND_MIGRATE_MEM_OBJECTS              0x1206\n#define CL_COMMAND_FILL_BUFFER                      0x1207\n#define CL_COMMAND_FILL_IMAGE                       0x1208\n#define CL_COMMAND_SVM_FREE                         0x1209\n#define CL_COMMAND_SVM_MEMCPY                       0x120A\n#define CL_COMMAND_SVM_MEMFILL                      0x120B\n#define CL_COMMAND_SVM_MAP                          0x120C\n#define CL_COMMAND_SVM_UNMAP                        0x120D\n\n/* command execution status */\n#define CL_COMPLETE                                 0x0\n#define CL_RUNNING                                  0x1\n#define CL_SUBMITTED                                0x2\n#define CL_QUEUED                                   0x3\n\n/* cl_buffer_create_type  */\n#define CL_BUFFER_CREATE_TYPE_REGION                0x1220\n\n/* cl_profiling_info  */\n#define CL_PROFILING_COMMAND_QUEUED                 0x1280\n#define CL_PROFILING_COMMAND_SUBMIT                 0x1281\n#define CL_PROFILING_COMMAND_START                  0x1282\n#define CL_PROFILING_COMMAND_END                    0x1283\n#define CL_PROFILING_COMMAND_COMPLETE               0x1284\n\n/********************************************************************************************************/\n\n/* Platform API */\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetPlatformIDs(cl_uint          /* num_entries */,\n                 cl_platform_id * /* platforms */,\n                 cl_uint *        /* num_platforms */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL \nclGetPlatformInfo(cl_platform_id   /* platform */, \n                  cl_platform_info /* param_name */,\n                  size_t           /* param_value_size */, \n                  void *           /* param_value */,\n                  size_t *         /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\n/* Device APIs */\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetDeviceIDs(cl_platform_id   /* platform */,\n               cl_device_type   /* device_type */, \n               cl_uint          /* num_entries */, \n               cl_device_id *   /* devices */, \n               cl_uint *        /* num_devices */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetDeviceInfo(cl_device_id    /* device */,\n                cl_device_info  /* param_name */, \n                size_t          /* param_value_size */, \n                void *          /* param_value */,\n                size_t *        /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclCreateSubDevices(cl_device_id                         /* in_device */,\n                   const cl_device_partition_property * /* properties */,\n                   cl_uint                              /* num_devices */,\n                   cl_device_id *                       /* out_devices */,\n                   cl_uint *                            /* num_devices_ret */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainDevice(cl_device_id /* device */) CL_API_SUFFIX__VERSION_1_2;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseDevice(cl_device_id /* device */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetDefaultDeviceCommandQueue(cl_context           /* context */,\n                               cl_device_id         /* device */,\n                               cl_command_queue     /* command_queue */) CL_API_SUFFIX__VERSION_2_1;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetDeviceAndHostTimer(cl_device_id    /* device */,\n                        cl_ulong*       /* device_timestamp */,\n                        cl_ulong*       /* host_timestamp */) CL_API_SUFFIX__VERSION_2_1;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetHostTimer(cl_device_id /* device */,\n               cl_ulong *   /* host_timestamp */)  CL_API_SUFFIX__VERSION_2_1;\n\n    \n/* Context APIs  */\nextern CL_API_ENTRY cl_context CL_API_CALL\nclCreateContext(const cl_context_properties * /* properties */,\n                cl_uint                 /* num_devices */,\n                const cl_device_id *    /* devices */,\n                void (CL_CALLBACK * /* pfn_notify */)(const char *, const void *, size_t, void *),\n                void *                  /* user_data */,\n                cl_int *                /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_context CL_API_CALL\nclCreateContextFromType(const cl_context_properties * /* properties */,\n                        cl_device_type          /* device_type */,\n                        void (CL_CALLBACK *     /* pfn_notify*/ )(const char *, const void *, size_t, void *),\n                        void *                  /* user_data */,\n                        cl_int *                /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainContext(cl_context /* context */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseContext(cl_context /* context */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetContextInfo(cl_context         /* context */, \n                 cl_context_info    /* param_name */, \n                 size_t             /* param_value_size */, \n                 void *             /* param_value */, \n                 size_t *           /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\n/* Command Queue APIs */\nextern CL_API_ENTRY cl_command_queue CL_API_CALL\nclCreateCommandQueueWithProperties(cl_context               /* context */,\n                                   cl_device_id             /* device */,\n                                   const cl_queue_properties *    /* properties */,\n                                   cl_int *                 /* errcode_ret */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainCommandQueue(cl_command_queue /* command_queue */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseCommandQueue(cl_command_queue /* command_queue */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetCommandQueueInfo(cl_command_queue      /* command_queue */,\n                      cl_command_queue_info /* param_name */,\n                      size_t                /* param_value_size */,\n                      void *                /* param_value */,\n                      size_t *              /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\n/* Memory Object APIs */\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateBuffer(cl_context   /* context */,\n               cl_mem_flags /* flags */,\n               size_t       /* size */,\n               void *       /* host_ptr */,\n               cl_int *     /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateSubBuffer(cl_mem                   /* buffer */,\n                  cl_mem_flags             /* flags */,\n                  cl_buffer_create_type    /* buffer_create_type */,\n                  const void *             /* buffer_create_info */,\n                  cl_int *                 /* errcode_ret */) CL_API_SUFFIX__VERSION_1_1;\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateImage(cl_context              /* context */,\n              cl_mem_flags            /* flags */,\n              const cl_image_format * /* image_format */,\n              const cl_image_desc *   /* image_desc */, \n              void *                  /* host_ptr */,\n              cl_int *                /* errcode_ret */) CL_API_SUFFIX__VERSION_1_2;\n                        \nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreatePipe(cl_context                 /* context */,\n             cl_mem_flags               /* flags */,\n             cl_uint                    /* pipe_packet_size */,\n             cl_uint                    /* pipe_max_packets */,\n             const cl_pipe_properties * /* properties */,\n             cl_int *                   /* errcode_ret */) CL_API_SUFFIX__VERSION_2_0;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainMemObject(cl_mem /* memobj */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseMemObject(cl_mem /* memobj */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetSupportedImageFormats(cl_context           /* context */,\n                           cl_mem_flags         /* flags */,\n                           cl_mem_object_type   /* image_type */,\n                           cl_uint              /* num_entries */,\n                           cl_image_format *    /* image_formats */,\n                           cl_uint *            /* num_image_formats */) CL_API_SUFFIX__VERSION_1_0;\n                                    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetMemObjectInfo(cl_mem           /* memobj */,\n                   cl_mem_info      /* param_name */, \n                   size_t           /* param_value_size */,\n                   void *           /* param_value */,\n                   size_t *         /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetImageInfo(cl_mem           /* image */,\n               cl_image_info    /* param_name */, \n               size_t           /* param_value_size */,\n               void *           /* param_value */,\n               size_t *         /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetPipeInfo(cl_mem           /* pipe */,\n              cl_pipe_info     /* param_name */,\n              size_t           /* param_value_size */,\n              void *           /* param_value */,\n              size_t *         /* param_value_size_ret */) CL_API_SUFFIX__VERSION_2_0;\n    \n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetMemObjectDestructorCallback(cl_mem /* memobj */,\n                                 void (CL_CALLBACK * /*pfn_notify*/)( cl_mem /* memobj */, void* /*user_data*/),\n                                 void * /*user_data */ )             CL_API_SUFFIX__VERSION_1_1;\n\n/* SVM Allocation APIs */\nextern CL_API_ENTRY void * CL_API_CALL\nclSVMAlloc(cl_context       /* context */,\n           cl_svm_mem_flags /* flags */,\n           size_t           /* size */,\n           cl_uint          /* alignment */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY void CL_API_CALL\nclSVMFree(cl_context        /* context */,\n          void *            /* svm_pointer */) CL_API_SUFFIX__VERSION_2_0;\n    \n/* Sampler APIs */\nextern CL_API_ENTRY cl_sampler CL_API_CALL\nclCreateSamplerWithProperties(cl_context                     /* context */,\n                              const cl_sampler_properties *  /* normalized_coords */,\n                              cl_int *                       /* errcode_ret */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainSampler(cl_sampler /* sampler */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseSampler(cl_sampler /* sampler */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetSamplerInfo(cl_sampler         /* sampler */,\n                 cl_sampler_info    /* param_name */,\n                 size_t             /* param_value_size */,\n                 void *             /* param_value */,\n                 size_t *           /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n                            \n/* Program Object APIs  */\nextern CL_API_ENTRY cl_program CL_API_CALL\nclCreateProgramWithSource(cl_context        /* context */,\n                          cl_uint           /* count */,\n                          const char **     /* strings */,\n                          const size_t *    /* lengths */,\n                          cl_int *          /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_program CL_API_CALL\nclCreateProgramWithBinary(cl_context                     /* context */,\n                          cl_uint                        /* num_devices */,\n                          const cl_device_id *           /* device_list */,\n                          const size_t *                 /* lengths */,\n                          const unsigned char **         /* binaries */,\n                          cl_int *                       /* binary_status */,\n                          cl_int *                       /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_program CL_API_CALL\nclCreateProgramWithBuiltInKernels(cl_context            /* context */,\n                                  cl_uint               /* num_devices */,\n                                  const cl_device_id *  /* device_list */,\n                                  const char *          /* kernel_names */,\n                                  cl_int *              /* errcode_ret */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_program CL_API_CALL\nclCreateProgramWithIL(cl_context    /* context */,\n                     const void*    /* il */,\n                     size_t         /* length */,\n                     cl_int*        /* errcode_ret */) CL_API_SUFFIX__VERSION_2_1;\n\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainProgram(cl_program /* program */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseProgram(cl_program /* program */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclBuildProgram(cl_program           /* program */,\n               cl_uint              /* num_devices */,\n               const cl_device_id * /* device_list */,\n               const char *         /* options */, \n               void (CL_CALLBACK *  /* pfn_notify */)(cl_program /* program */, void * /* user_data */),\n               void *               /* user_data */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclCompileProgram(cl_program           /* program */,\n                 cl_uint              /* num_devices */,\n                 const cl_device_id * /* device_list */,\n                 const char *         /* options */, \n                 cl_uint              /* num_input_headers */,\n                 const cl_program *   /* input_headers */,\n                 const char **        /* header_include_names */,\n                 void (CL_CALLBACK *  /* pfn_notify */)(cl_program /* program */, void * /* user_data */),\n                 void *               /* user_data */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_program CL_API_CALL\nclLinkProgram(cl_context           /* context */,\n              cl_uint              /* num_devices */,\n              const cl_device_id * /* device_list */,\n              const char *         /* options */, \n              cl_uint              /* num_input_programs */,\n              const cl_program *   /* input_programs */,\n              void (CL_CALLBACK *  /* pfn_notify */)(cl_program /* program */, void * /* user_data */),\n              void *               /* user_data */,\n              cl_int *             /* errcode_ret */ ) CL_API_SUFFIX__VERSION_1_2;\n\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclUnloadPlatformCompiler(cl_platform_id /* platform */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetProgramInfo(cl_program         /* program */,\n                 cl_program_info    /* param_name */,\n                 size_t             /* param_value_size */,\n                 void *             /* param_value */,\n                 size_t *           /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetProgramBuildInfo(cl_program            /* program */,\n                      cl_device_id          /* device */,\n                      cl_program_build_info /* param_name */,\n                      size_t                /* param_value_size */,\n                      void *                /* param_value */,\n                      size_t *              /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n                            \n/* Kernel Object APIs */\nextern CL_API_ENTRY cl_kernel CL_API_CALL\nclCreateKernel(cl_program      /* program */,\n               const char *    /* kernel_name */,\n               cl_int *        /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclCreateKernelsInProgram(cl_program     /* program */,\n                         cl_uint        /* num_kernels */,\n                         cl_kernel *    /* kernels */,\n                         cl_uint *      /* num_kernels_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_kernel CL_API_CALL\nclCloneKernel(cl_kernel     /* source_kernel */,\n              cl_int*       /* errcode_ret */) CL_API_SUFFIX__VERSION_2_1;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainKernel(cl_kernel    /* kernel */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseKernel(cl_kernel   /* kernel */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetKernelArg(cl_kernel    /* kernel */,\n               cl_uint      /* arg_index */,\n               size_t       /* arg_size */,\n               const void * /* arg_value */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetKernelArgSVMPointer(cl_kernel    /* kernel */,\n                         cl_uint      /* arg_index */,\n                         const void * /* arg_value */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetKernelExecInfo(cl_kernel            /* kernel */,\n                    cl_kernel_exec_info  /* param_name */,\n                    size_t               /* param_value_size */,\n                    const void *         /* param_value */) CL_API_SUFFIX__VERSION_2_0;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetKernelInfo(cl_kernel       /* kernel */,\n                cl_kernel_info  /* param_name */,\n                size_t          /* param_value_size */,\n                void *          /* param_value */,\n                size_t *        /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetKernelArgInfo(cl_kernel       /* kernel */,\n                   cl_uint         /* arg_indx */,\n                   cl_kernel_arg_info  /* param_name */,\n                   size_t          /* param_value_size */,\n                   void *          /* param_value */,\n                   size_t *        /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetKernelWorkGroupInfo(cl_kernel                  /* kernel */,\n                         cl_device_id               /* device */,\n                         cl_kernel_work_group_info  /* param_name */,\n                         size_t                     /* param_value_size */,\n                         void *                     /* param_value */,\n                         size_t *                   /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetKernelSubGroupInfo(cl_kernel                   /* kernel */,\n                        cl_device_id                /* device */,\n                        cl_kernel_sub_group_info    /* param_name */,\n                        size_t                      /* input_value_size */,\n                        const void*                 /*input_value */,\n                        size_t                      /* param_value_size */,\n                        void*                       /* param_value */,\n                        size_t*                     /* param_value_size_ret */ ) CL_API_SUFFIX__VERSION_2_1;\n\n\n/* Event Object APIs */\nextern CL_API_ENTRY cl_int CL_API_CALL\nclWaitForEvents(cl_uint             /* num_events */,\n                const cl_event *    /* event_list */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetEventInfo(cl_event         /* event */,\n               cl_event_info    /* param_name */,\n               size_t           /* param_value_size */,\n               void *           /* param_value */,\n               size_t *         /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n                            \nextern CL_API_ENTRY cl_event CL_API_CALL\nclCreateUserEvent(cl_context    /* context */,\n                  cl_int *      /* errcode_ret */) CL_API_SUFFIX__VERSION_1_1;               \n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclRetainEvent(cl_event /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclReleaseEvent(cl_event /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetUserEventStatus(cl_event   /* event */,\n                     cl_int     /* execution_status */) CL_API_SUFFIX__VERSION_1_1;\n                     \nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetEventCallback( cl_event    /* event */,\n                    cl_int      /* command_exec_callback_type */,\n                    void (CL_CALLBACK * /* pfn_notify */)(cl_event, cl_int, void *),\n                    void *      /* user_data */) CL_API_SUFFIX__VERSION_1_1;\n\n/* Profiling APIs */\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetEventProfilingInfo(cl_event            /* event */,\n                        cl_profiling_info   /* param_name */,\n                        size_t              /* param_value_size */,\n                        void *              /* param_value */,\n                        size_t *            /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n                                \n/* Flush and Finish APIs */\nextern CL_API_ENTRY cl_int CL_API_CALL\nclFlush(cl_command_queue /* command_queue */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclFinish(cl_command_queue /* command_queue */) CL_API_SUFFIX__VERSION_1_0;\n\n/* Enqueued Commands APIs */\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueReadBuffer(cl_command_queue    /* command_queue */,\n                    cl_mem              /* buffer */,\n                    cl_bool             /* blocking_read */,\n                    size_t              /* offset */,\n                    size_t              /* size */, \n                    void *              /* ptr */,\n                    cl_uint             /* num_events_in_wait_list */,\n                    const cl_event *    /* event_wait_list */,\n                    cl_event *          /* event */) CL_API_SUFFIX__VERSION_1_0;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueReadBufferRect(cl_command_queue    /* command_queue */,\n                        cl_mem              /* buffer */,\n                        cl_bool             /* blocking_read */,\n                        const size_t *      /* buffer_offset */,\n                        const size_t *      /* host_offset */, \n                        const size_t *      /* region */,\n                        size_t              /* buffer_row_pitch */,\n                        size_t              /* buffer_slice_pitch */,\n                        size_t              /* host_row_pitch */,\n                        size_t              /* host_slice_pitch */,                        \n                        void *              /* ptr */,\n                        cl_uint             /* num_events_in_wait_list */,\n                        const cl_event *    /* event_wait_list */,\n                        cl_event *          /* event */) CL_API_SUFFIX__VERSION_1_1;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueWriteBuffer(cl_command_queue   /* command_queue */, \n                     cl_mem             /* buffer */, \n                     cl_bool            /* blocking_write */, \n                     size_t             /* offset */, \n                     size_t             /* size */, \n                     const void *       /* ptr */, \n                     cl_uint            /* num_events_in_wait_list */, \n                     const cl_event *   /* event_wait_list */, \n                     cl_event *         /* event */) CL_API_SUFFIX__VERSION_1_0;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueWriteBufferRect(cl_command_queue    /* command_queue */,\n                         cl_mem              /* buffer */,\n                         cl_bool             /* blocking_write */,\n                         const size_t *      /* buffer_offset */,\n                         const size_t *      /* host_offset */, \n                         const size_t *      /* region */,\n                         size_t              /* buffer_row_pitch */,\n                         size_t              /* buffer_slice_pitch */,\n                         size_t              /* host_row_pitch */,\n                         size_t              /* host_slice_pitch */,                        \n                         const void *        /* ptr */,\n                         cl_uint             /* num_events_in_wait_list */,\n                         const cl_event *    /* event_wait_list */,\n                         cl_event *          /* event */) CL_API_SUFFIX__VERSION_1_1;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueFillBuffer(cl_command_queue   /* command_queue */,\n                    cl_mem             /* buffer */, \n                    const void *       /* pattern */, \n                    size_t             /* pattern_size */, \n                    size_t             /* offset */, \n                    size_t             /* size */, \n                    cl_uint            /* num_events_in_wait_list */, \n                    const cl_event *   /* event_wait_list */, \n                    cl_event *         /* event */) CL_API_SUFFIX__VERSION_1_2;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueCopyBuffer(cl_command_queue    /* command_queue */, \n                    cl_mem              /* src_buffer */,\n                    cl_mem              /* dst_buffer */, \n                    size_t              /* src_offset */,\n                    size_t              /* dst_offset */,\n                    size_t              /* size */, \n                    cl_uint             /* num_events_in_wait_list */,\n                    const cl_event *    /* event_wait_list */,\n                    cl_event *          /* event */) CL_API_SUFFIX__VERSION_1_0;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueCopyBufferRect(cl_command_queue    /* command_queue */, \n                        cl_mem              /* src_buffer */,\n                        cl_mem              /* dst_buffer */, \n                        const size_t *      /* src_origin */,\n                        const size_t *      /* dst_origin */,\n                        const size_t *      /* region */, \n                        size_t              /* src_row_pitch */,\n                        size_t              /* src_slice_pitch */,\n                        size_t              /* dst_row_pitch */,\n                        size_t              /* dst_slice_pitch */,\n                        cl_uint             /* num_events_in_wait_list */,\n                        const cl_event *    /* event_wait_list */,\n                        cl_event *          /* event */) CL_API_SUFFIX__VERSION_1_1;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueReadImage(cl_command_queue     /* command_queue */,\n                   cl_mem               /* image */,\n                   cl_bool              /* blocking_read */, \n                   const size_t *       /* origin[3] */,\n                   const size_t *       /* region[3] */,\n                   size_t               /* row_pitch */,\n                   size_t               /* slice_pitch */, \n                   void *               /* ptr */,\n                   cl_uint              /* num_events_in_wait_list */,\n                   const cl_event *     /* event_wait_list */,\n                   cl_event *           /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueWriteImage(cl_command_queue    /* command_queue */,\n                    cl_mem              /* image */,\n                    cl_bool             /* blocking_write */, \n                    const size_t *      /* origin[3] */,\n                    const size_t *      /* region[3] */,\n                    size_t              /* input_row_pitch */,\n                    size_t              /* input_slice_pitch */, \n                    const void *        /* ptr */,\n                    cl_uint             /* num_events_in_wait_list */,\n                    const cl_event *    /* event_wait_list */,\n                    cl_event *          /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueFillImage(cl_command_queue   /* command_queue */,\n                   cl_mem             /* image */, \n                   const void *       /* fill_color */, \n                   const size_t *     /* origin[3] */, \n                   const size_t *     /* region[3] */, \n                   cl_uint            /* num_events_in_wait_list */, \n                   const cl_event *   /* event_wait_list */, \n                   cl_event *         /* event */) CL_API_SUFFIX__VERSION_1_2;\n                            \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueCopyImage(cl_command_queue     /* command_queue */,\n                   cl_mem               /* src_image */,\n                   cl_mem               /* dst_image */, \n                   const size_t *       /* src_origin[3] */,\n                   const size_t *       /* dst_origin[3] */,\n                   const size_t *       /* region[3] */, \n                   cl_uint              /* num_events_in_wait_list */,\n                   const cl_event *     /* event_wait_list */,\n                   cl_event *           /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueCopyImageToBuffer(cl_command_queue /* command_queue */,\n                           cl_mem           /* src_image */,\n                           cl_mem           /* dst_buffer */, \n                           const size_t *   /* src_origin[3] */,\n                           const size_t *   /* region[3] */, \n                           size_t           /* dst_offset */,\n                           cl_uint          /* num_events_in_wait_list */,\n                           const cl_event * /* event_wait_list */,\n                           cl_event *       /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueCopyBufferToImage(cl_command_queue /* command_queue */,\n                           cl_mem           /* src_buffer */,\n                           cl_mem           /* dst_image */, \n                           size_t           /* src_offset */,\n                           const size_t *   /* dst_origin[3] */,\n                           const size_t *   /* region[3] */, \n                           cl_uint          /* num_events_in_wait_list */,\n                           const cl_event * /* event_wait_list */,\n                           cl_event *       /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY void * CL_API_CALL\nclEnqueueMapBuffer(cl_command_queue /* command_queue */,\n                   cl_mem           /* buffer */,\n                   cl_bool          /* blocking_map */, \n                   cl_map_flags     /* map_flags */,\n                   size_t           /* offset */,\n                   size_t           /* size */,\n                   cl_uint          /* num_events_in_wait_list */,\n                   const cl_event * /* event_wait_list */,\n                   cl_event *       /* event */,\n                   cl_int *         /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY void * CL_API_CALL\nclEnqueueMapImage(cl_command_queue  /* command_queue */,\n                  cl_mem            /* image */, \n                  cl_bool           /* blocking_map */, \n                  cl_map_flags      /* map_flags */, \n                  const size_t *    /* origin[3] */,\n                  const size_t *    /* region[3] */,\n                  size_t *          /* image_row_pitch */,\n                  size_t *          /* image_slice_pitch */,\n                  cl_uint           /* num_events_in_wait_list */,\n                  const cl_event *  /* event_wait_list */,\n                  cl_event *        /* event */,\n                  cl_int *          /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueUnmapMemObject(cl_command_queue /* command_queue */,\n                        cl_mem           /* memobj */,\n                        void *           /* mapped_ptr */,\n                        cl_uint          /* num_events_in_wait_list */,\n                        const cl_event *  /* event_wait_list */,\n                        cl_event *        /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueMigrateMemObjects(cl_command_queue       /* command_queue */,\n                           cl_uint                /* num_mem_objects */,\n                           const cl_mem *         /* mem_objects */,\n                           cl_mem_migration_flags /* flags */,\n                           cl_uint                /* num_events_in_wait_list */,\n                           const cl_event *       /* event_wait_list */,\n                           cl_event *             /* event */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueNDRangeKernel(cl_command_queue /* command_queue */,\n                       cl_kernel        /* kernel */,\n                       cl_uint          /* work_dim */,\n                       const size_t *   /* global_work_offset */,\n                       const size_t *   /* global_work_size */,\n                       const size_t *   /* local_work_size */,\n                       cl_uint          /* num_events_in_wait_list */,\n                       const cl_event * /* event_wait_list */,\n                       cl_event *       /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueNativeKernel(cl_command_queue  /* command_queue */,\n\t\t\t\t\t  void (CL_CALLBACK * /*user_func*/)(void *), \n                      void *            /* args */,\n                      size_t            /* cb_args */, \n                      cl_uint           /* num_mem_objects */,\n                      const cl_mem *    /* mem_list */,\n                      const void **     /* args_mem_loc */,\n                      cl_uint           /* num_events_in_wait_list */,\n                      const cl_event *  /* event_wait_list */,\n                      cl_event *        /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueMarkerWithWaitList(cl_command_queue  /* command_queue */,\n                            cl_uint           /* num_events_in_wait_list */,\n                            const cl_event *  /* event_wait_list */,\n                            cl_event *        /* event */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueBarrierWithWaitList(cl_command_queue  /* command_queue */,\n                             cl_uint           /* num_events_in_wait_list */,\n                             const cl_event *  /* event_wait_list */,\n                             cl_event *        /* event */) CL_API_SUFFIX__VERSION_1_2;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueSVMFree(cl_command_queue  /* command_queue */,\n                 cl_uint           /* num_svm_pointers */,\n                 void *[]          /* svm_pointers[] */,\n                 void (CL_CALLBACK * /*pfn_free_func*/)(cl_command_queue /* queue */,\n                                                        cl_uint          /* num_svm_pointers */,\n                                                        void *[]         /* svm_pointers[] */,\n                                                        void *           /* user_data */),\n                 void *            /* user_data */,\n                 cl_uint           /* num_events_in_wait_list */,\n                 const cl_event *  /* event_wait_list */,\n                 cl_event *        /* event */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueSVMMemcpy(cl_command_queue  /* command_queue */,\n                   cl_bool           /* blocking_copy */,\n                   void *            /* dst_ptr */,\n                   const void *      /* src_ptr */,\n                   size_t            /* size */,\n                   cl_uint           /* num_events_in_wait_list */,\n                   const cl_event *  /* event_wait_list */,\n                   cl_event *        /* event */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueSVMMemFill(cl_command_queue  /* command_queue */,\n                    void *            /* svm_ptr */,\n                    const void *      /* pattern */,\n                    size_t            /* pattern_size */,\n                    size_t            /* size */,\n                    cl_uint           /* num_events_in_wait_list */,\n                    const cl_event *  /* event_wait_list */,\n                    cl_event *        /* event */) CL_API_SUFFIX__VERSION_2_0;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueSVMMap(cl_command_queue  /* command_queue */,\n                cl_bool           /* blocking_map */,\n                cl_map_flags      /* flags */,\n                void *            /* svm_ptr */,\n                size_t            /* size */,\n                cl_uint           /* num_events_in_wait_list */,\n                const cl_event *  /* event_wait_list */,\n                cl_event *        /* event */) CL_API_SUFFIX__VERSION_2_0;\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueSVMUnmap(cl_command_queue  /* command_queue */,\n                  void *            /* svm_ptr */,\n                  cl_uint           /* num_events_in_wait_list */,\n                  const cl_event *  /* event_wait_list */,\n                  cl_event *        /* event */) CL_API_SUFFIX__VERSION_2_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueSVMMigrateMem(cl_command_queue         /* command_queue */,\n                       cl_uint                  /* num_svm_pointers */,\n                       const void **            /* svm_pointers */,\n                       const size_t *           /* sizes */,\n                       cl_mem_migration_flags   /* flags */,\n                       cl_uint                  /* num_events_in_wait_list */,\n                       const cl_event *         /* event_wait_list */,\n                       cl_event *               /* event */) CL_API_SUFFIX__VERSION_2_1;\n\n\n/* Extension function access\n *\n * Returns the extension function address for the given function name,\n * or NULL if a valid function can not be found.  The client must\n * check to make sure the address is not NULL, before using or \n * calling the returned function address.\n */\nextern CL_API_ENTRY void * CL_API_CALL \nclGetExtensionFunctionAddressForPlatform(cl_platform_id /* platform */,\n                                         const char *   /* func_name */) CL_API_SUFFIX__VERSION_1_2;\n    \n\n/* Deprecated OpenCL 1.1 APIs */\nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL\nclCreateImage2D(cl_context              /* context */,\n                cl_mem_flags            /* flags */,\n                const cl_image_format * /* image_format */,\n                size_t                  /* image_width */,\n                size_t                  /* image_height */,\n                size_t                  /* image_row_pitch */, \n                void *                  /* host_ptr */,\n                cl_int *                /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL\nclCreateImage3D(cl_context              /* context */,\n                cl_mem_flags            /* flags */,\n                const cl_image_format * /* image_format */,\n                size_t                  /* image_width */, \n                size_t                  /* image_height */,\n                size_t                  /* image_depth */, \n                size_t                  /* image_row_pitch */, \n                size_t                  /* image_slice_pitch */, \n                void *                  /* host_ptr */,\n                cl_int *                /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL\nclEnqueueMarker(cl_command_queue    /* command_queue */,\n                cl_event *          /* event */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL\nclEnqueueWaitForEvents(cl_command_queue /* command_queue */,\n                        cl_uint          /* num_events */,\n                        const cl_event * /* event_list */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL\nclEnqueueBarrier(cl_command_queue /* command_queue */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n\nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_int CL_API_CALL\nclUnloadCompiler(void) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED void * CL_API_CALL\nclGetExtensionFunctionAddress(const char * /* func_name */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \n/* Deprecated OpenCL 2.0 APIs */\nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_command_queue CL_API_CALL\nclCreateCommandQueue(cl_context                     /* context */,\n                     cl_device_id                   /* device */,\n                     cl_command_queue_properties    /* properties */,\n                     cl_int *                       /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED;\n    \n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_sampler CL_API_CALL\nclCreateSampler(cl_context          /* context */,\n                cl_bool             /* normalized_coords */,\n                cl_addressing_mode  /* addressing_mode */,\n                cl_filter_mode      /* filter_mode */,\n                cl_int *            /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_2_DEPRECATED cl_int CL_API_CALL\nclEnqueueTask(cl_command_queue  /* command_queue */,\n              cl_kernel         /* kernel */,\n              cl_uint           /* num_events_in_wait_list */,\n              const cl_event *  /* event_wait_list */,\n              cl_event *        /* event */) CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED;\n    \n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __OPENCL_CL_H */\n\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_d3d10.h",
    "content": "/**********************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n **********************************************************************************/\n\n/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */\n\n#ifndef __OPENCL_CL_D3D10_H\n#define __OPENCL_CL_D3D10_H\n\n#include <d3d10.h>\n#include <CL/cl.h>\n#include <CL/cl_platform.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/******************************************************************************\n * cl_khr_d3d10_sharing                                                       */\n#define cl_khr_d3d10_sharing 1\n\ntypedef cl_uint cl_d3d10_device_source_khr;\ntypedef cl_uint cl_d3d10_device_set_khr;\n\n/******************************************************************************/\n\n/* Error Codes */\n#define CL_INVALID_D3D10_DEVICE_KHR                  -1002\n#define CL_INVALID_D3D10_RESOURCE_KHR                -1003\n#define CL_D3D10_RESOURCE_ALREADY_ACQUIRED_KHR       -1004\n#define CL_D3D10_RESOURCE_NOT_ACQUIRED_KHR           -1005\n\n/* cl_d3d10_device_source_nv */\n#define CL_D3D10_DEVICE_KHR                          0x4010\n#define CL_D3D10_DXGI_ADAPTER_KHR                    0x4011\n\n/* cl_d3d10_device_set_nv */\n#define CL_PREFERRED_DEVICES_FOR_D3D10_KHR           0x4012\n#define CL_ALL_DEVICES_FOR_D3D10_KHR                 0x4013\n\n/* cl_context_info */\n#define CL_CONTEXT_D3D10_DEVICE_KHR                  0x4014\n#define CL_CONTEXT_D3D10_PREFER_SHARED_RESOURCES_KHR 0x402C\n\n/* cl_mem_info */\n#define CL_MEM_D3D10_RESOURCE_KHR                    0x4015\n\n/* cl_image_info */\n#define CL_IMAGE_D3D10_SUBRESOURCE_KHR               0x4016\n\n/* cl_command_type */\n#define CL_COMMAND_ACQUIRE_D3D10_OBJECTS_KHR         0x4017\n#define CL_COMMAND_RELEASE_D3D10_OBJECTS_KHR         0x4018\n\n/******************************************************************************/\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromD3D10KHR_fn)(\n    cl_platform_id             platform,\n    cl_d3d10_device_source_khr d3d_device_source,\n    void *                     d3d_object,\n    cl_d3d10_device_set_khr    d3d_device_set,\n    cl_uint                    num_entries,\n    cl_device_id *             devices,\n    cl_uint *                  num_devices) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10BufferKHR_fn)(\n    cl_context     context,\n    cl_mem_flags   flags,\n    ID3D10Buffer * resource,\n    cl_int *       errcode_ret) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10Texture2DKHR_fn)(\n    cl_context        context,\n    cl_mem_flags      flags,\n    ID3D10Texture2D * resource,\n    UINT              subresource,\n    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10Texture3DKHR_fn)(\n    cl_context        context,\n    cl_mem_flags      flags,\n    ID3D10Texture3D * resource,\n    UINT              subresource,\n    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireD3D10ObjectsKHR_fn)(\n    cl_command_queue command_queue,\n    cl_uint          num_objects,\n    const cl_mem *   mem_objects,\n    cl_uint          num_events_in_wait_list,\n    const cl_event * event_wait_list,\n    cl_event *       event) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseD3D10ObjectsKHR_fn)(\n    cl_command_queue command_queue,\n    cl_uint          num_objects,\n    const cl_mem *   mem_objects,\n    cl_uint          num_events_in_wait_list,\n    const cl_event * event_wait_list,\n    cl_event *       event) CL_API_SUFFIX__VERSION_1_0;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __OPENCL_CL_D3D10_H */\n\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_d3d11.h",
    "content": "/**********************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n **********************************************************************************/\n\n/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */\n\n#ifndef __OPENCL_CL_D3D11_H\n#define __OPENCL_CL_D3D11_H\n\n#include <d3d11.h>\n#include <CL/cl.h>\n#include <CL/cl_platform.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/******************************************************************************\n * cl_khr_d3d11_sharing                                                       */\n#define cl_khr_d3d11_sharing 1\n\ntypedef cl_uint cl_d3d11_device_source_khr;\ntypedef cl_uint cl_d3d11_device_set_khr;\n\n/******************************************************************************/\n\n/* Error Codes */\n#define CL_INVALID_D3D11_DEVICE_KHR                  -1006\n#define CL_INVALID_D3D11_RESOURCE_KHR                -1007\n#define CL_D3D11_RESOURCE_ALREADY_ACQUIRED_KHR       -1008\n#define CL_D3D11_RESOURCE_NOT_ACQUIRED_KHR           -1009\n\n/* cl_d3d11_device_source */\n#define CL_D3D11_DEVICE_KHR                          0x4019\n#define CL_D3D11_DXGI_ADAPTER_KHR                    0x401A\n\n/* cl_d3d11_device_set */\n#define CL_PREFERRED_DEVICES_FOR_D3D11_KHR           0x401B\n#define CL_ALL_DEVICES_FOR_D3D11_KHR                 0x401C\n\n/* cl_context_info */\n#define CL_CONTEXT_D3D11_DEVICE_KHR                  0x401D\n#define CL_CONTEXT_D3D11_PREFER_SHARED_RESOURCES_KHR 0x402D\n\n/* cl_mem_info */\n#define CL_MEM_D3D11_RESOURCE_KHR                    0x401E\n\n/* cl_image_info */\n#define CL_IMAGE_D3D11_SUBRESOURCE_KHR               0x401F\n\n/* cl_command_type */\n#define CL_COMMAND_ACQUIRE_D3D11_OBJECTS_KHR         0x4020\n#define CL_COMMAND_RELEASE_D3D11_OBJECTS_KHR         0x4021\n\n/******************************************************************************/\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromD3D11KHR_fn)(\n    cl_platform_id             platform,\n    cl_d3d11_device_source_khr d3d_device_source,\n    void *                     d3d_object,\n    cl_d3d11_device_set_khr    d3d_device_set,\n    cl_uint                    num_entries,\n    cl_device_id *             devices,\n    cl_uint *                  num_devices) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11BufferKHR_fn)(\n    cl_context     context,\n    cl_mem_flags   flags,\n    ID3D11Buffer * resource,\n    cl_int *       errcode_ret) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11Texture2DKHR_fn)(\n    cl_context        context,\n    cl_mem_flags      flags,\n    ID3D11Texture2D * resource,\n    UINT              subresource,\n    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11Texture3DKHR_fn)(\n    cl_context        context,\n    cl_mem_flags      flags,\n    ID3D11Texture3D * resource,\n    UINT              subresource,\n    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireD3D11ObjectsKHR_fn)(\n    cl_command_queue command_queue,\n    cl_uint          num_objects,\n    const cl_mem *   mem_objects,\n    cl_uint          num_events_in_wait_list,\n    const cl_event * event_wait_list,\n    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseD3D11ObjectsKHR_fn)(\n    cl_command_queue command_queue,\n    cl_uint          num_objects,\n    const cl_mem *   mem_objects,\n    cl_uint          num_events_in_wait_list,\n    const cl_event * event_wait_list,\n    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __OPENCL_CL_D3D11_H */\n\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_dx9_media_sharing.h",
    "content": "/**********************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n **********************************************************************************/\n\n/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */\n\n#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_H\n#define __OPENCL_CL_DX9_MEDIA_SHARING_H\n\n#include <CL/cl.h>\n#include <CL/cl_platform.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/******************************************************************************/\n/* cl_khr_dx9_media_sharing                                                   */\n#define cl_khr_dx9_media_sharing 1\n\ntypedef cl_uint             cl_dx9_media_adapter_type_khr;\ntypedef cl_uint             cl_dx9_media_adapter_set_khr;\n    \n#if defined(_WIN32)\n#include <d3d9.h>\ntypedef struct _cl_dx9_surface_info_khr\n{\n    IDirect3DSurface9 *resource;\n    HANDLE shared_handle;\n} cl_dx9_surface_info_khr;\n#endif\n\n\n/******************************************************************************/\n\n/* Error Codes */\n#define CL_INVALID_DX9_MEDIA_ADAPTER_KHR                -1010\n#define CL_INVALID_DX9_MEDIA_SURFACE_KHR                -1011\n#define CL_DX9_MEDIA_SURFACE_ALREADY_ACQUIRED_KHR       -1012\n#define CL_DX9_MEDIA_SURFACE_NOT_ACQUIRED_KHR           -1013\n\n/* cl_media_adapter_type_khr */\n#define CL_ADAPTER_D3D9_KHR                              0x2020\n#define CL_ADAPTER_D3D9EX_KHR                            0x2021\n#define CL_ADAPTER_DXVA_KHR                              0x2022\n\n/* cl_media_adapter_set_khr */\n#define CL_PREFERRED_DEVICES_FOR_DX9_MEDIA_ADAPTER_KHR   0x2023\n#define CL_ALL_DEVICES_FOR_DX9_MEDIA_ADAPTER_KHR         0x2024\n\n/* cl_context_info */\n#define CL_CONTEXT_ADAPTER_D3D9_KHR                      0x2025\n#define CL_CONTEXT_ADAPTER_D3D9EX_KHR                    0x2026\n#define CL_CONTEXT_ADAPTER_DXVA_KHR                      0x2027\n\n/* cl_mem_info */\n#define CL_MEM_DX9_MEDIA_ADAPTER_TYPE_KHR                0x2028\n#define CL_MEM_DX9_MEDIA_SURFACE_INFO_KHR                0x2029\n\n/* cl_image_info */\n#define CL_IMAGE_DX9_MEDIA_PLANE_KHR                     0x202A\n\n/* cl_command_type */\n#define CL_COMMAND_ACQUIRE_DX9_MEDIA_SURFACES_KHR        0x202B\n#define CL_COMMAND_RELEASE_DX9_MEDIA_SURFACES_KHR        0x202C\n\n/******************************************************************************/\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromDX9MediaAdapterKHR_fn)(\n    cl_platform_id                   platform,\n    cl_uint                          num_media_adapters,\n    cl_dx9_media_adapter_type_khr *  media_adapter_type,\n    void *                           media_adapters,\n    cl_dx9_media_adapter_set_khr     media_adapter_set,\n    cl_uint                          num_entries,\n    cl_device_id *                   devices,\n    cl_uint *                        num_devices) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromDX9MediaSurfaceKHR_fn)(\n    cl_context                    context,\n    cl_mem_flags                  flags,\n    cl_dx9_media_adapter_type_khr adapter_type,\n    void *                        surface_info,\n    cl_uint                       plane,                                                                          \n    cl_int *                      errcode_ret) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireDX9MediaSurfacesKHR_fn)(\n    cl_command_queue command_queue,\n    cl_uint          num_objects,\n    const cl_mem *   mem_objects,\n    cl_uint          num_events_in_wait_list,\n    const cl_event * event_wait_list,\n    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseDX9MediaSurfacesKHR_fn)(\n    cl_command_queue command_queue,\n    cl_uint          num_objects,\n    const cl_mem *   mem_objects,\n    cl_uint          num_events_in_wait_list,\n    const cl_event * event_wait_list,\n    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __OPENCL_CL_DX9_MEDIA_SHARING_H */\n\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_egl.h",
    "content": "/*******************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n ******************************************************************************/\n\n#ifndef __OPENCL_CL_EGL_H\n#define __OPENCL_CL_EGL_H\n\n#ifdef __APPLE__\n\n#else\n#include <CL/cl.h>\n#endif  \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* Command type for events created with clEnqueueAcquireEGLObjectsKHR */\n#define CL_COMMAND_EGL_FENCE_SYNC_OBJECT_KHR  0x202F\n#define CL_COMMAND_ACQUIRE_EGL_OBJECTS_KHR    0x202D\n#define CL_COMMAND_RELEASE_EGL_OBJECTS_KHR    0x202E\n\n/* Error type for clCreateFromEGLImageKHR */\n#define CL_INVALID_EGL_OBJECT_KHR             -1093\n#define CL_EGL_RESOURCE_NOT_ACQUIRED_KHR      -1092\n\n/* CLeglImageKHR is an opaque handle to an EGLImage */\ntypedef void* CLeglImageKHR;\n\n/* CLeglDisplayKHR is an opaque handle to an EGLDisplay */\ntypedef void* CLeglDisplayKHR;\n\n/* CLeglSyncKHR is an opaque handle to an EGLSync object */\ntypedef void* CLeglSyncKHR;\n\n/* properties passed to clCreateFromEGLImageKHR */\ntypedef intptr_t cl_egl_image_properties_khr;\n\n\n#define cl_khr_egl_image 1\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateFromEGLImageKHR(cl_context                  /* context */,\n                        CLeglDisplayKHR             /* egldisplay */,\n                        CLeglImageKHR               /* eglimage */,\n                        cl_mem_flags                /* flags */,\n                        const cl_egl_image_properties_khr * /* properties */,\n                        cl_int *                    /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromEGLImageKHR_fn)(\n\tcl_context                  context,\n\tCLeglDisplayKHR             egldisplay,\n\tCLeglImageKHR               eglimage,\n\tcl_mem_flags                flags,\n\tconst cl_egl_image_properties_khr * properties,\n\tcl_int *                    errcode_ret);\n\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueAcquireEGLObjectsKHR(cl_command_queue /* command_queue */,\n                              cl_uint          /* num_objects */,\n                              const cl_mem *   /* mem_objects */,\n                              cl_uint          /* num_events_in_wait_list */,\n                              const cl_event * /* event_wait_list */,\n                              cl_event *       /* event */) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireEGLObjectsKHR_fn)(\n\tcl_command_queue command_queue,\n\tcl_uint          num_objects,\n\tconst cl_mem *   mem_objects,\n\tcl_uint          num_events_in_wait_list,\n\tconst cl_event * event_wait_list,\n\tcl_event *       event);\n\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueReleaseEGLObjectsKHR(cl_command_queue /* command_queue */,\n                              cl_uint          /* num_objects */,\n                              const cl_mem *   /* mem_objects */,\n                              cl_uint          /* num_events_in_wait_list */,\n                              const cl_event * /* event_wait_list */,\n                              cl_event *       /* event */) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseEGLObjectsKHR_fn)(\n\tcl_command_queue command_queue,\n\tcl_uint          num_objects,\n\tconst cl_mem *   mem_objects,\n\tcl_uint          num_events_in_wait_list,\n\tconst cl_event * event_wait_list,\n\tcl_event *       event);\n\n\n#define cl_khr_egl_event 1\n\nextern CL_API_ENTRY cl_event CL_API_CALL\nclCreateEventFromEGLSyncKHR(cl_context      /* context */,\n                            CLeglSyncKHR    /* sync */,\n                            CLeglDisplayKHR /* display */,\n                            cl_int *        /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\ntypedef CL_API_ENTRY cl_event (CL_API_CALL *clCreateEventFromEGLSyncKHR_fn)(\n\tcl_context      context,\n\tCLeglSyncKHR    sync,\n\tCLeglDisplayKHR display,\n\tcl_int *        errcode_ret);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __OPENCL_CL_EGL_H */\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_ext.h",
    "content": "/*******************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n ******************************************************************************/\n\n/* $Revision: 11928 $ on $Date: 2010-07-13 09:04:56 -0700 (Tue, 13 Jul 2010) $ */\n\n/* cl_ext.h contains OpenCL extensions which don't have external */\n/* (OpenGL, D3D) dependencies.                                   */\n\n#ifndef __CL_EXT_H\n#define __CL_EXT_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#ifdef __APPLE__\n        #include <OpenCL/cl.h>\n    #include <AvailabilityMacros.h>\n#else\n        #include <CL/cl.h>\n#endif\n\n/* cl_khr_fp16 extension - no extension #define since it has no functions  */\n#define CL_DEVICE_HALF_FP_CONFIG                    0x1033\n\n/* Memory object destruction\n *\n * Apple extension for use to manage externally allocated buffers used with cl_mem objects with CL_MEM_USE_HOST_PTR\n *\n * Registers a user callback function that will be called when the memory object is deleted and its resources \n * freed. Each call to clSetMemObjectCallbackFn registers the specified user callback function on a callback \n * stack associated with memobj. The registered user callback functions are called in the reverse order in \n * which they were registered. The user callback functions are called and then the memory object is deleted \n * and its resources freed. This provides a mechanism for the application (and libraries) using memobj to be \n * notified when the memory referenced by host_ptr, specified when the memory object is created and used as \n * the storage bits for the memory object, can be reused or freed.\n *\n * The application may not call CL api's with the cl_mem object passed to the pfn_notify.\n *\n * Please check for the \"cl_APPLE_SetMemObjectDestructor\" extension using clGetDeviceInfo(CL_DEVICE_EXTENSIONS)\n * before using.\n */\n#define cl_APPLE_SetMemObjectDestructor 1\ncl_int  CL_API_ENTRY clSetMemObjectDestructorAPPLE(  cl_mem /* memobj */, \n                                        void (* /*pfn_notify*/)( cl_mem /* memobj */, void* /*user_data*/), \n                                        void * /*user_data */ )             CL_EXT_SUFFIX__VERSION_1_0;  \n\n\n/* Context Logging Functions\n *\n * The next three convenience functions are intended to be used as the pfn_notify parameter to clCreateContext().\n * Please check for the \"cl_APPLE_ContextLoggingFunctions\" extension using clGetDeviceInfo(CL_DEVICE_EXTENSIONS)\n * before using.\n *\n * clLogMessagesToSystemLog fowards on all log messages to the Apple System Logger \n */\n#define cl_APPLE_ContextLoggingFunctions 1\nextern void CL_API_ENTRY clLogMessagesToSystemLogAPPLE(  const char * /* errstr */, \n                                            const void * /* private_info */, \n                                            size_t       /* cb */, \n                                            void *       /* user_data */ )  CL_EXT_SUFFIX__VERSION_1_0;\n\n/* clLogMessagesToStdout sends all log messages to the file descriptor stdout */\nextern void CL_API_ENTRY clLogMessagesToStdoutAPPLE(   const char * /* errstr */, \n                                          const void * /* private_info */, \n                                          size_t       /* cb */, \n                                          void *       /* user_data */ )    CL_EXT_SUFFIX__VERSION_1_0;\n\n/* clLogMessagesToStderr sends all log messages to the file descriptor stderr */\nextern void CL_API_ENTRY clLogMessagesToStderrAPPLE(   const char * /* errstr */, \n                                          const void * /* private_info */, \n                                          size_t       /* cb */, \n                                          void *       /* user_data */ )    CL_EXT_SUFFIX__VERSION_1_0;\n\n\n/************************ \n* cl_khr_icd extension *                                                  \n************************/\n#define cl_khr_icd 1\n\n/* cl_platform_info                                                        */\n#define CL_PLATFORM_ICD_SUFFIX_KHR                  0x0920\n\n/* Additional Error Codes                                                  */\n#define CL_PLATFORM_NOT_FOUND_KHR                   -1001\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclIcdGetPlatformIDsKHR(cl_uint          /* num_entries */,\n                       cl_platform_id * /* platforms */,\n                       cl_uint *        /* num_platforms */);\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clIcdGetPlatformIDsKHR_fn)(\n    cl_uint          /* num_entries */,\n    cl_platform_id * /* platforms */,\n    cl_uint *        /* num_platforms */);\n\n\n/* Extension: cl_khr_image2D_buffer\n *\n * This extension allows a 2D image to be created from a cl_mem buffer without a copy.\n * The type associated with a 2D image created from a buffer in an OpenCL program is image2d_t.\n * Both the sampler and sampler-less read_image built-in functions are supported for 2D images\n * and 2D images created from a buffer.  Similarly, the write_image built-ins are also supported\n * for 2D images created from a buffer.\n *\n * When the 2D image from buffer is created, the client must specify the width,\n * height, image format (i.e. channel order and channel data type) and optionally the row pitch\n *\n * The pitch specified must be a multiple of CL_DEVICE_IMAGE_PITCH_ALIGNMENT pixels.\n * The base address of the buffer must be aligned to CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT pixels.\n */\n    \n/*************************************\n * cl_khr_initalize_memory extension *\n *************************************/\n    \n#define CL_CONTEXT_MEMORY_INITIALIZE_KHR            0x2030\n    \n    \n/**************************************\n * cl_khr_terminate_context extension *\n **************************************/\n    \n#define CL_DEVICE_TERMINATE_CAPABILITY_KHR          0x2031\n#define CL_CONTEXT_TERMINATE_KHR                    0x2032\n\n#define cl_khr_terminate_context 1\nextern CL_API_ENTRY cl_int CL_API_CALL clTerminateContextKHR(cl_context /* context */) CL_EXT_SUFFIX__VERSION_1_2;\n\ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clTerminateContextKHR_fn)(cl_context /* context */) CL_EXT_SUFFIX__VERSION_1_2;\n    \n    \n/*\n * Extension: cl_khr_spir\n *\n * This extension adds support to create an OpenCL program object from a \n * Standard Portable Intermediate Representation (SPIR) instance\n */\n\n#define CL_DEVICE_SPIR_VERSIONS                     0x40E0\n#define CL_PROGRAM_BINARY_TYPE_INTERMEDIATE         0x40E1\n\n\n/******************************************\n* cl_nv_device_attribute_query extension *\n******************************************/\n/* cl_nv_device_attribute_query extension - no extension #define since it has no functions */\n#define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV       0x4000\n#define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV       0x4001\n#define CL_DEVICE_REGISTERS_PER_BLOCK_NV            0x4002\n#define CL_DEVICE_WARP_SIZE_NV                      0x4003\n#define CL_DEVICE_GPU_OVERLAP_NV                    0x4004\n#define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV            0x4005\n#define CL_DEVICE_INTEGRATED_MEMORY_NV              0x4006\n\n/*********************************\n* cl_amd_device_attribute_query *\n*********************************/\n#define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD        0x4036\n\n/*********************************\n* cl_arm_printf extension\n*********************************/\n#define CL_PRINTF_CALLBACK_ARM                      0x40B0\n#define CL_PRINTF_BUFFERSIZE_ARM                    0x40B1\n\n#ifdef CL_VERSION_1_1\n   /***********************************\n    * cl_ext_device_fission extension *\n    ***********************************/\n    #define cl_ext_device_fission   1\n    \n    extern CL_API_ENTRY cl_int CL_API_CALL\n    clReleaseDeviceEXT( cl_device_id /*device*/ ) CL_EXT_SUFFIX__VERSION_1_1; \n    \n    typedef CL_API_ENTRY cl_int \n    (CL_API_CALL *clReleaseDeviceEXT_fn)( cl_device_id /*device*/ ) CL_EXT_SUFFIX__VERSION_1_1;\n\n    extern CL_API_ENTRY cl_int CL_API_CALL\n    clRetainDeviceEXT( cl_device_id /*device*/ ) CL_EXT_SUFFIX__VERSION_1_1; \n    \n    typedef CL_API_ENTRY cl_int \n    (CL_API_CALL *clRetainDeviceEXT_fn)( cl_device_id /*device*/ ) CL_EXT_SUFFIX__VERSION_1_1;\n\n    typedef cl_ulong  cl_device_partition_property_ext;\n    extern CL_API_ENTRY cl_int CL_API_CALL\n    clCreateSubDevicesEXT(  cl_device_id /*in_device*/,\n                            const cl_device_partition_property_ext * /* properties */,\n                            cl_uint /*num_entries*/,\n                            cl_device_id * /*out_devices*/,\n                            cl_uint * /*num_devices*/ ) CL_EXT_SUFFIX__VERSION_1_1;\n\n    typedef CL_API_ENTRY cl_int \n    ( CL_API_CALL * clCreateSubDevicesEXT_fn)(  cl_device_id /*in_device*/,\n                                                const cl_device_partition_property_ext * /* properties */,\n                                                cl_uint /*num_entries*/,\n                                                cl_device_id * /*out_devices*/,\n                                                cl_uint * /*num_devices*/ ) CL_EXT_SUFFIX__VERSION_1_1;\n\n    /* cl_device_partition_property_ext */\n    #define CL_DEVICE_PARTITION_EQUALLY_EXT             0x4050\n    #define CL_DEVICE_PARTITION_BY_COUNTS_EXT           0x4051\n    #define CL_DEVICE_PARTITION_BY_NAMES_EXT            0x4052\n    #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT  0x4053\n    \n    /* clDeviceGetInfo selectors */\n    #define CL_DEVICE_PARENT_DEVICE_EXT                 0x4054\n    #define CL_DEVICE_PARTITION_TYPES_EXT               0x4055\n    #define CL_DEVICE_AFFINITY_DOMAINS_EXT              0x4056\n    #define CL_DEVICE_REFERENCE_COUNT_EXT               0x4057\n    #define CL_DEVICE_PARTITION_STYLE_EXT               0x4058\n    \n    /* error codes */\n    #define CL_DEVICE_PARTITION_FAILED_EXT              -1057\n    #define CL_INVALID_PARTITION_COUNT_EXT              -1058\n    #define CL_INVALID_PARTITION_NAME_EXT               -1059\n    \n    /* CL_AFFINITY_DOMAINs */\n    #define CL_AFFINITY_DOMAIN_L1_CACHE_EXT             0x1\n    #define CL_AFFINITY_DOMAIN_L2_CACHE_EXT             0x2\n    #define CL_AFFINITY_DOMAIN_L3_CACHE_EXT             0x3\n    #define CL_AFFINITY_DOMAIN_L4_CACHE_EXT             0x4\n    #define CL_AFFINITY_DOMAIN_NUMA_EXT                 0x10\n    #define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT     0x100\n    \n    /* cl_device_partition_property_ext list terminators */\n    #define CL_PROPERTIES_LIST_END_EXT                  ((cl_device_partition_property_ext) 0)\n    #define CL_PARTITION_BY_COUNTS_LIST_END_EXT         ((cl_device_partition_property_ext) 0)\n    #define CL_PARTITION_BY_NAMES_LIST_END_EXT          ((cl_device_partition_property_ext) 0 - 1)\n\n/*********************************\n* cl_qcom_ext_host_ptr extension\n*********************************/\n\n#define CL_MEM_EXT_HOST_PTR_QCOM                  (1 << 29)\n\n#define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM   0x40A0      \n#define CL_DEVICE_PAGE_SIZE_QCOM                  0x40A1\n#define CL_IMAGE_ROW_ALIGNMENT_QCOM               0x40A2\n#define CL_IMAGE_SLICE_ALIGNMENT_QCOM             0x40A3\n#define CL_MEM_HOST_UNCACHED_QCOM                 0x40A4\n#define CL_MEM_HOST_WRITEBACK_QCOM                0x40A5\n#define CL_MEM_HOST_WRITETHROUGH_QCOM             0x40A6\n#define CL_MEM_HOST_WRITE_COMBINING_QCOM          0x40A7\n\ntypedef cl_uint                                   cl_image_pitch_info_qcom;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetDeviceImageInfoQCOM(cl_device_id             device,\n                         size_t                   image_width,\n                         size_t                   image_height,\n                         const cl_image_format   *image_format,\n                         cl_image_pitch_info_qcom param_name,\n                         size_t                   param_value_size,\n                         void                    *param_value,\n                         size_t                  *param_value_size_ret);\n\ntypedef struct _cl_mem_ext_host_ptr\n{\n    /* Type of external memory allocation. */\n    /* Legal values will be defined in layered extensions. */\n    cl_uint  allocation_type;\n            \n    /* Host cache policy for this external memory allocation. */\n    cl_uint  host_cache_policy;\n\n} cl_mem_ext_host_ptr;\n\n/*********************************\n* cl_qcom_ion_host_ptr extension\n*********************************/\n\n#define CL_MEM_ION_HOST_PTR_QCOM                  0x40A8\n\ntypedef struct _cl_mem_ion_host_ptr\n{\n    /* Type of external memory allocation. */\n    /* Must be CL_MEM_ION_HOST_PTR_QCOM for ION allocations. */\n    cl_mem_ext_host_ptr  ext_host_ptr;\n\n    /* ION file descriptor */\n    int                  ion_filedesc;\n            \n    /* Host pointer to the ION allocated memory */\n    void*                ion_hostptr;\n\n} cl_mem_ion_host_ptr;\n\n#endif /* CL_VERSION_1_1 */\n\n\n#ifdef CL_VERSION_2_0\n/*********************************\n* cl_khr_sub_groups extension\n*********************************/\n#define cl_khr_sub_groups 1\n\ntypedef cl_uint  cl_kernel_sub_group_info_khr;\n\n/* cl_khr_sub_group_info */\n#define CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE_KHR\t0x2033\n#define CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE_KHR\t\t0x2034\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetKernelSubGroupInfoKHR(cl_kernel /* in_kernel */,\n\t\t\t\t\t\t   cl_device_id /*in_device*/,\n\t\t\t\t\t\t   cl_kernel_sub_group_info_khr /* param_name */,\n\t\t\t\t\t\t   size_t /*input_value_size*/,\n\t\t\t\t\t\t   const void * /*input_value*/,\n\t\t\t\t\t\t   size_t /*param_value_size*/,\n\t\t\t\t\t\t   void* /*param_value*/,\n\t\t\t\t\t\t   size_t* /*param_value_size_ret*/ ) CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED;\n\t\t\t\t\t\t   \ntypedef CL_API_ENTRY cl_int\n     ( CL_API_CALL * clGetKernelSubGroupInfoKHR_fn)(cl_kernel /* in_kernel */,\n\t\t\t\t\t\t      cl_device_id /*in_device*/,\n\t\t\t\t\t\t      cl_kernel_sub_group_info_khr /* param_name */,\n\t\t\t\t\t\t      size_t /*input_value_size*/,\n\t\t\t\t\t\t      const void * /*input_value*/,\n\t\t\t\t\t\t      size_t /*param_value_size*/,\n\t\t\t\t\t\t      void* /*param_value*/,\n\t\t\t\t\t\t      size_t* /*param_value_size_ret*/ ) CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED;\n#endif /* CL_VERSION_2_0 */\n\n#ifdef CL_VERSION_2_1\n/*********************************\n* cl_khr_priority_hints extension\n*********************************/\n#define cl_khr_priority_hints 1\n\ntypedef cl_uint  cl_queue_priority_khr;\n\n/* cl_command_queue_properties */\n#define CL_QUEUE_PRIORITY_KHR 0x1096\n\n/* cl_queue_priority_khr */\n#define CL_QUEUE_PRIORITY_HIGH_KHR (1<<0)\n#define CL_QUEUE_PRIORITY_MED_KHR (1<<1)\n#define CL_QUEUE_PRIORITY_LOW_KHR (1<<2)\n\n#endif /* CL_VERSION_2_1 */\n\n#ifdef CL_VERSION_2_1\n/*********************************\n* cl_khr_throttle_hints extension\n*********************************/\n#define cl_khr_throttle_hints 1\n\ntypedef cl_uint  cl_queue_throttle_khr;\n\n/* cl_command_queue_properties */\n#define CL_QUEUE_THROTTLE_KHR 0x1097\n\n/* cl_queue_throttle_khr */\n#define CL_QUEUE_THROTTLE_HIGH_KHR (1<<0)\n#define CL_QUEUE_THROTTLE_MED_KHR (1<<1)\n#define CL_QUEUE_THROTTLE_LOW_KHR (1<<2)\n\n#endif /* CL_VERSION_2_1 */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* __CL_EXT_H */\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_ext_qcom.h",
    "content": "/* Copyright (c) 2009-2017 Qualcomm Technologies, Inc.  All Rights Reserved.\n * Qualcomm Technologies Proprietary and Confidential.\n */\n\n#ifndef __OPENCL_CL_EXT_QCOM_H\n#define __OPENCL_CL_EXT_QCOM_H\n\n// Needed by cl_khr_egl_event extension \n#include <EGL/egl.h>\n#include <EGL/eglext.h>\n#include <CL/cl_ext.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/************************************\n * cl_qcom_create_buffer_from_image *\n ************************************/\n\n#define CL_BUFFER_FROM_IMAGE_ROW_PITCH_QCOM         0x40C0\n#define CL_BUFFER_FROM_IMAGE_SLICE_PITCH_QCOM       0x40C1\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateBufferFromImageQCOM(cl_mem       image,\n                            cl_mem_flags flags,\n                            cl_int      *errcode_ret);\n\n\n/************************************\n * cl_qcom_limited_printf extension *\n ************************************/\n\n/* Builtin printf function buffer size in bytes. */\n#define CL_DEVICE_PRINTF_BUFFER_SIZE_QCOM           0x1049\n\n\n/*************************************\n * cl_qcom_extended_images extension *\n *************************************/\n\n#define CL_CONTEXT_ENABLE_EXTENDED_IMAGES_QCOM      0x40AA\n#define CL_DEVICE_EXTENDED_IMAGE2D_MAX_WIDTH_QCOM   0x40AB\n#define CL_DEVICE_EXTENDED_IMAGE2D_MAX_HEIGHT_QCOM  0x40AC\n#define CL_DEVICE_EXTENDED_IMAGE3D_MAX_WIDTH_QCOM   0x40AD\n#define CL_DEVICE_EXTENDED_IMAGE3D_MAX_HEIGHT_QCOM  0x40AE\n#define CL_DEVICE_EXTENDED_IMAGE3D_MAX_DEPTH_QCOM   0x40AF\n\n/*************************************\n * cl_qcom_perf_hint extension *\n *************************************/\n\ntypedef cl_uint                                     cl_perf_hint;\n\n#define CL_CONTEXT_PERF_HINT_QCOM                   0x40C2\n\n/*cl_perf_hint*/\n#define CL_PERF_HINT_HIGH_QCOM                      0x40C3\n#define CL_PERF_HINT_NORMAL_QCOM                    0x40C4\n#define CL_PERF_HINT_LOW_QCOM                       0x40C5\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclSetPerfHintQCOM(cl_context    context,\n                  cl_perf_hint  perf_hint);\n\n// This extension is published at Khronos, so its definitions are made in cl_ext.h.\n// This duplication is for backward compatibility.\n\n#ifndef CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM\n\n/*********************************\n* cl_qcom_android_native_buffer_host_ptr extension\n*********************************/\n\n#define CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM                  0x40C6\n\n\ntypedef struct _cl_mem_android_native_buffer_host_ptr\n{\n    // Type of external memory allocation.\n    // Must be CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM for Android native buffers.\n    cl_mem_ext_host_ptr  ext_host_ptr;\n\n    // Virtual pointer to the android native buffer\n    void*                anb_ptr;\n\n} cl_mem_android_native_buffer_host_ptr;\n\n#endif   //#ifndef CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM\n\n/***********************************\n* cl_img_egl_image extension *\n************************************/\ntypedef void* CLeglImageIMG;\ntypedef void* CLeglDisplayIMG;\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateFromEGLImageIMG(cl_context      context,\n                        cl_mem_flags     flags,\n                        CLeglImageIMG    image,\n                        CLeglDisplayIMG  display,\n                        cl_int           *errcode_ret);\n\n\n/*********************************\n* cl_qcom_other_image extension\n*********************************/\n\n// Extended flag for creating/querying QCOM non-standard images\n#define CL_MEM_OTHER_IMAGE_QCOM                             (1<<25)\n\n// cl_channel_type\n#define CL_QCOM_UNORM_MIPI10                                0x4159\n#define CL_QCOM_UNORM_MIPI12                                0x415A\n#define CL_QCOM_UNSIGNED_MIPI10                             0x415B\n#define CL_QCOM_UNSIGNED_MIPI12                             0x415C\n#define CL_QCOM_UNORM_INT10                                 0x415D\n#define CL_QCOM_UNORM_INT12                                 0x415E\n#define CL_QCOM_UNSIGNED_INT16                              0x415F\n\n// cl_channel_order\n// Dedicate 0x4130-0x415F range for QCOM extended image formats\n// 0x4130 - 0x4132 range is assigned to pixel-oriented compressed format\n#define CL_QCOM_BAYER                                       0x414E\n\n#define CL_QCOM_NV12                                        0x4133\n#define CL_QCOM_NV12_Y                                      0x4134\n#define CL_QCOM_NV12_UV                                     0x4135\n\n#define CL_QCOM_TILED_NV12                                  0x4136\n#define CL_QCOM_TILED_NV12_Y                                0x4137\n#define CL_QCOM_TILED_NV12_UV                               0x4138\n\n#define CL_QCOM_P010                                        0x413C\n#define CL_QCOM_P010_Y                                      0x413D\n#define CL_QCOM_P010_UV                                     0x413E\n\n#define CL_QCOM_TILED_P010                                  0x413F\n#define CL_QCOM_TILED_P010_Y                                0x4140\n#define CL_QCOM_TILED_P010_UV                               0x4141\n\n\n#define CL_QCOM_TP10                                        0x4145\n#define CL_QCOM_TP10_Y                                      0x4146\n#define CL_QCOM_TP10_UV                                     0x4147\n\n#define CL_QCOM_TILED_TP10                                  0x4148\n#define CL_QCOM_TILED_TP10_Y                                0x4149\n#define CL_QCOM_TILED_TP10_UV                               0x414A\n\n/*********************************\n* cl_qcom_compressed_image extension\n*********************************/\n\n// Extended flag for creating/querying QCOM non-planar compressed images\n#define CL_MEM_COMPRESSED_IMAGE_QCOM                        (1<<27)\n\n// Extended image format\n// cl_channel_order\n#define CL_QCOM_COMPRESSED_RGBA                             0x4130\n#define CL_QCOM_COMPRESSED_RGBx                             0x4131\n\n#define CL_QCOM_COMPRESSED_NV12_Y                           0x413A\n#define CL_QCOM_COMPRESSED_NV12_UV                          0x413B\n\n#define CL_QCOM_COMPRESSED_P010                             0x4142\n#define CL_QCOM_COMPRESSED_P010_Y                           0x4143\n#define CL_QCOM_COMPRESSED_P010_UV                          0x4144\n\n#define CL_QCOM_COMPRESSED_TP10                             0x414B\n#define CL_QCOM_COMPRESSED_TP10_Y                           0x414C\n#define CL_QCOM_COMPRESSED_TP10_UV                          0x414D\n\n#define CL_QCOM_COMPRESSED_NV12_4R                          0x414F\n#define CL_QCOM_COMPRESSED_NV12_4R_Y                        0x4150\n#define CL_QCOM_COMPRESSED_NV12_4R_UV                       0x4151\n/*********************************\n* cl_qcom_compressed_yuv_image_read extension\n*********************************/\n\n// Extended flag for creating/querying QCOM compressed images\n#define CL_MEM_COMPRESSED_YUV_IMAGE_QCOM                    (1<<28)\n\n// Extended image format\n#define CL_QCOM_COMPRESSED_NV12                             0x10C4\n\n// Extended flag for setting ION buffer allocation type\n#define CL_MEM_ION_HOST_PTR_COMPRESSED_YUV_QCOM                 0x40CD\n#define CL_MEM_ION_HOST_PTR_PROTECTED_COMPRESSED_YUV_QCOM       0x40CE\n\n/*********************************\n* cl_qcom_accelerated_image_ops\n*********************************/\n#define CL_MEM_OBJECT_WEIGHT_IMAGE_QCOM                         0x4110\n#define CL_DEVICE_HOF_MAX_NUM_PHASES_QCOM                       0x4111\n#define CL_DEVICE_HOF_MAX_FILTER_SIZE_X_QCOM                    0x4112\n#define CL_DEVICE_HOF_MAX_FILTER_SIZE_Y_QCOM                    0x4113\n#define CL_DEVICE_BLOCK_MATCHING_MAX_REGION_SIZE_X_QCOM         0x4114\n#define CL_DEVICE_BLOCK_MATCHING_MAX_REGION_SIZE_Y_QCOM         0x4115\n\n//Extended flag for specifying weight image type\n#define CL_WEIGHT_IMAGE_SEPARABLE_QCOM                          (1<<0)\n\n// Box Filter\ntypedef struct _cl_box_filter_size_qcom\n{\n    // Width of box filter on X direction.\n    float box_filter_width;\n\n    // Height of box filter on Y direction.\n    float box_filter_height;\n} cl_box_filter_size_qcom;\n\n// HOF Weight Image Desc\ntypedef struct _cl_weight_desc_qcom\n{\n    /** Coordinate of the \"center\" point of the weight image,\n        based on the weight image's top-left corner as the origin. */\n    size_t        center_coord_x;\n    size_t        center_coord_y;\n    cl_bitfield   flags;\n} cl_weight_desc_qcom;\n\ntypedef struct _cl_weight_image_desc_qcom\n{\n    cl_image_desc           image_desc;\n    cl_weight_desc_qcom     weight_desc;\n} cl_weight_image_desc_qcom;\n\n/*************************************\n * cl_qcom_protected_context extension *\n *************************************/\n\n#define CL_CONTEXT_PROTECTED_QCOM                    0x40C7\n#define CL_MEM_ION_HOST_PTR_PROTECTED_QCOM           0x40C8\n\n/*************************************\n * cl_qcom_priority_hint extension *\n *************************************/\n#define CL_PRIORITY_HINT_NONE_QCOM                   0\ntypedef cl_uint                                     cl_priority_hint;\n\n#define CL_CONTEXT_PRIORITY_HINT_QCOM               0x40C9\n\n/*cl_priority_hint*/\n#define CL_PRIORITY_HINT_HIGH_QCOM                  0x40CA\n#define CL_PRIORITY_HINT_NORMAL_QCOM                0x40CB\n#define CL_PRIORITY_HINT_LOW_QCOM                   0x40CC\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __OPENCL_CL_EXT_QCOM_H */\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_gl.h",
    "content": "/**********************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n **********************************************************************************/\n\n#ifndef __OPENCL_CL_GL_H\n#define __OPENCL_CL_GL_H\n\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\t\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef cl_uint     cl_gl_object_type;\ntypedef cl_uint     cl_gl_texture_info;\ntypedef cl_uint     cl_gl_platform_info;\ntypedef struct __GLsync *cl_GLsync;\n\n/* cl_gl_object_type = 0x2000 - 0x200F enum values are currently taken           */\n#define CL_GL_OBJECT_BUFFER                     0x2000\n#define CL_GL_OBJECT_TEXTURE2D                  0x2001\n#define CL_GL_OBJECT_TEXTURE3D                  0x2002\n#define CL_GL_OBJECT_RENDERBUFFER               0x2003\n#define CL_GL_OBJECT_TEXTURE2D_ARRAY            0x200E\n#define CL_GL_OBJECT_TEXTURE1D                  0x200F\n#define CL_GL_OBJECT_TEXTURE1D_ARRAY            0x2010\n#define CL_GL_OBJECT_TEXTURE_BUFFER             0x2011\n\n/* cl_gl_texture_info           */\n#define CL_GL_TEXTURE_TARGET                    0x2004\n#define CL_GL_MIPMAP_LEVEL                      0x2005\n#define CL_GL_NUM_SAMPLES                       0x2012\n\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateFromGLBuffer(cl_context     /* context */,\n                     cl_mem_flags   /* flags */,\n                     cl_GLuint      /* bufobj */,\n                     int *          /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateFromGLTexture(cl_context      /* context */,\n                      cl_mem_flags    /* flags */,\n                      cl_GLenum       /* target */,\n                      cl_GLint        /* miplevel */,\n                      cl_GLuint       /* texture */,\n                      cl_int *        /* errcode_ret */) CL_API_SUFFIX__VERSION_1_2;\n    \nextern CL_API_ENTRY cl_mem CL_API_CALL\nclCreateFromGLRenderbuffer(cl_context   /* context */,\n                           cl_mem_flags /* flags */,\n                           cl_GLuint    /* renderbuffer */,\n                           cl_int *     /* errcode_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetGLObjectInfo(cl_mem                /* memobj */,\n                  cl_gl_object_type *   /* gl_object_type */,\n                  cl_GLuint *           /* gl_object_name */) CL_API_SUFFIX__VERSION_1_0;\n                  \nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetGLTextureInfo(cl_mem               /* memobj */,\n                   cl_gl_texture_info   /* param_name */,\n                   size_t               /* param_value_size */,\n                   void *               /* param_value */,\n                   size_t *             /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueAcquireGLObjects(cl_command_queue      /* command_queue */,\n                          cl_uint               /* num_objects */,\n                          const cl_mem *        /* mem_objects */,\n                          cl_uint               /* num_events_in_wait_list */,\n                          const cl_event *      /* event_wait_list */,\n                          cl_event *            /* event */) CL_API_SUFFIX__VERSION_1_0;\n\nextern CL_API_ENTRY cl_int CL_API_CALL\nclEnqueueReleaseGLObjects(cl_command_queue      /* command_queue */,\n                          cl_uint               /* num_objects */,\n                          const cl_mem *        /* mem_objects */,\n                          cl_uint               /* num_events_in_wait_list */,\n                          const cl_event *      /* event_wait_list */,\n                          cl_event *            /* event */) CL_API_SUFFIX__VERSION_1_0;\n\n\n/* Deprecated OpenCL 1.1 APIs */\nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL\nclCreateFromGLTexture2D(cl_context      /* context */,\n                        cl_mem_flags    /* flags */,\n                        cl_GLenum       /* target */,\n                        cl_GLint        /* miplevel */,\n                        cl_GLuint       /* texture */,\n                        cl_int *        /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \nextern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL\nclCreateFromGLTexture3D(cl_context      /* context */,\n                        cl_mem_flags    /* flags */,\n                        cl_GLenum       /* target */,\n                        cl_GLint        /* miplevel */,\n                        cl_GLuint       /* texture */,\n                        cl_int *        /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;\n    \n/* cl_khr_gl_sharing extension  */\n    \n#define cl_khr_gl_sharing 1\n    \ntypedef cl_uint     cl_gl_context_info;\n    \n/* Additional Error Codes  */\n#define CL_INVALID_GL_SHAREGROUP_REFERENCE_KHR  -1000\n    \n/* cl_gl_context_info  */\n#define CL_CURRENT_DEVICE_FOR_GL_CONTEXT_KHR    0x2006\n#define CL_DEVICES_FOR_GL_CONTEXT_KHR           0x2007\n    \n/* Additional cl_context_properties  */\n#define CL_GL_CONTEXT_KHR                       0x2008\n#define CL_EGL_DISPLAY_KHR                      0x2009\n#define CL_GLX_DISPLAY_KHR                      0x200A\n#define CL_WGL_HDC_KHR                          0x200B\n#define CL_CGL_SHAREGROUP_KHR                   0x200C\n    \nextern CL_API_ENTRY cl_int CL_API_CALL\nclGetGLContextInfoKHR(const cl_context_properties * /* properties */,\n                      cl_gl_context_info            /* param_name */,\n                      size_t                        /* param_value_size */,\n                      void *                        /* param_value */,\n                      size_t *                      /* param_value_size_ret */) CL_API_SUFFIX__VERSION_1_0;\n    \ntypedef CL_API_ENTRY cl_int (CL_API_CALL *clGetGLContextInfoKHR_fn)(\n    const cl_context_properties * properties,\n    cl_gl_context_info            param_name,\n    size_t                        param_value_size,\n    void *                        param_value,\n    size_t *                      param_value_size_ret);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __OPENCL_CL_GL_H */\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_gl_ext.h",
    "content": "/**********************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n **********************************************************************************/\n\n/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */\n\n/* cl_gl_ext.h contains vendor (non-KHR) OpenCL extensions which have           */\n/* OpenGL dependencies.                                                         */\n\n#ifndef __OPENCL_CL_GL_EXT_H\n#define __OPENCL_CL_GL_EXT_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#ifdef __APPLE__\n    #include <OpenCL/cl_gl.h>\n#else\n    #include <CL/cl_gl.h>\n#endif\n\n/*\n * For each extension, follow this template\n *  cl_VEN_extname extension  */\n/* #define cl_VEN_extname 1\n * ... define new types, if any\n * ... define new tokens, if any\n * ... define new APIs, if any\n *\n *  If you need GLtypes here, mirror them with a cl_GLtype, rather than including a GL header\n *  This allows us to avoid having to decide whether to include GL headers or GLES here.\n */\n\n/* \n *  cl_khr_gl_event  extension\n *  See section 9.9 in the OpenCL 1.1 spec for more information\n */\n#define CL_COMMAND_GL_FENCE_SYNC_OBJECT_KHR     0x200D\n\nextern CL_API_ENTRY cl_event CL_API_CALL\nclCreateEventFromGLsyncKHR(cl_context           /* context */,\n                           cl_GLsync            /* cl_GLsync */,\n                           cl_int *             /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_1;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\t/* __OPENCL_CL_GL_EXT_H  */\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/cl_platform.h",
    "content": "/**********************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n **********************************************************************************/\n\n/* $Revision: 11803 $ on $Date: 2010-06-25 10:02:12 -0700 (Fri, 25 Jun 2010) $ */\n\n#ifndef __CL_PLATFORM_H\n#define __CL_PLATFORM_H\n\n#ifdef __APPLE__\n    /* Contains #defines for AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER below */\n    #include <AvailabilityMacros.h>\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#if defined(_WIN32)\n    #define CL_API_ENTRY\n    #define CL_API_CALL     __stdcall\n    #define CL_CALLBACK     __stdcall\n#else\n    #define CL_API_ENTRY\n    #define CL_API_CALL\n    #define CL_CALLBACK\n#endif\n\n/*\n * Deprecation flags refer to the last version of the header in which the\n * feature was not deprecated.\n *\n * E.g. VERSION_1_1_DEPRECATED means the feature is present in 1.1 without\n * deprecation but is deprecated in versions later than 1.1.\n */\n\n#ifdef __APPLE__\n    #define CL_EXTENSION_WEAK_LINK       __attribute__((weak_import))\n    #define CL_API_SUFFIX__VERSION_1_0                  AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER\n    #define CL_EXT_SUFFIX__VERSION_1_0                  CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER\n    #define CL_API_SUFFIX__VERSION_1_1                  AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n    #define GCL_API_SUFFIX__VERSION_1_1                 AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n    #define CL_EXT_SUFFIX__VERSION_1_1                  CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n    #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED       CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER_BUT_DEPRECATED_IN_MAC_OS_X_VERSION_10_7\n    \n    #ifdef AVAILABLE_MAC_OS_X_VERSION_10_8_AND_LATER\n        #define CL_API_SUFFIX__VERSION_1_2              AVAILABLE_MAC_OS_X_VERSION_10_8_AND_LATER\n        #define GCL_API_SUFFIX__VERSION_1_2             AVAILABLE_MAC_OS_X_VERSION_10_8_AND_LATER\n        #define CL_EXT_SUFFIX__VERSION_1_2              CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_8_AND_LATER\n        #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED\n        #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED   CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER_BUT_DEPRECATED_IN_MAC_OS_X_VERSION_10_8\n    #else\n        #warning  This path should never happen outside of internal operating system development.  AvailabilityMacros do not function correctly here!\n        #define CL_API_SUFFIX__VERSION_1_2              AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n        #define GCL_API_SUFFIX__VERSION_1_2             AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n        #define CL_EXT_SUFFIX__VERSION_1_2              CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n        #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED   CL_EXTENSION_WEAK_LINK AVAILABLE_MAC_OS_X_VERSION_10_7_AND_LATER\n    #endif\n#else\n    #define CL_EXTENSION_WEAK_LINK  \n    #define CL_API_SUFFIX__VERSION_1_0\n    #define CL_EXT_SUFFIX__VERSION_1_0\n    #define CL_API_SUFFIX__VERSION_1_1\n    #define CL_EXT_SUFFIX__VERSION_1_1\n    #define CL_API_SUFFIX__VERSION_1_2\n    #define CL_EXT_SUFFIX__VERSION_1_2\n    #define CL_API_SUFFIX__VERSION_2_0\n    #define CL_EXT_SUFFIX__VERSION_2_0\n    #define CL_API_SUFFIX__VERSION_2_1\n    #define CL_EXT_SUFFIX__VERSION_2_1\n    \n    #ifdef __GNUC__\n        #ifdef CL_USE_DEPRECATED_OPENCL_1_0_APIS\n            #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED    \n        #else\n            #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED __attribute__((deprecated))\n            #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED    \n        #endif\n    \n        #ifdef CL_USE_DEPRECATED_OPENCL_1_1_APIS\n            #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED    \n            #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED    \n        #else\n            #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED __attribute__((deprecated))\n            #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED    \n        #endif\n\n        #ifdef CL_USE_DEPRECATED_OPENCL_1_2_APIS\n            #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED\n        #else\n            #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED __attribute__((deprecated))\n            #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED\n         #endif\n\n        #ifdef CL_USE_DEPRECATED_OPENCL_2_0_APIS\n            #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED\n        #else\n            #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED __attribute__((deprecated))\n            #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED\n        #endif\n    #elif _WIN32\n        #ifdef CL_USE_DEPRECATED_OPENCL_1_0_APIS\n            #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED    \n        #else\n            #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED \n            #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED __declspec(deprecated)     \n        #endif\n    \n        #ifdef CL_USE_DEPRECATED_OPENCL_1_1_APIS\n            #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED    \n        #else\n            #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED \n            #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED __declspec(deprecated)     \n        #endif\n    \n        #ifdef CL_USE_DEPRECATED_OPENCL_1_2_APIS\n            #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED\n        #else\n            #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED __declspec(deprecated)\n        #endif\n\n        #ifdef CL_USE_DEPRECATED_OPENCL_2_0_APIS\n            #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED\n            #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED\n        #else\n            #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED \n            #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED __declspec(deprecated)\n        #endif\n    #else\n        #define CL_EXT_SUFFIX__VERSION_1_0_DEPRECATED\n        #define CL_EXT_PREFIX__VERSION_1_0_DEPRECATED\n    \n        #define CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED\n        #define CL_EXT_PREFIX__VERSION_1_1_DEPRECATED\n    \n        #define CL_EXT_SUFFIX__VERSION_1_2_DEPRECATED\n        #define CL_EXT_PREFIX__VERSION_1_2_DEPRECATED\n\n        #define CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED\n        #define CL_EXT_PREFIX__VERSION_2_0_DEPRECATED\n    #endif\n#endif\n\n#if (defined (_WIN32) && defined(_MSC_VER))\n\n/* scalar types  */\ntypedef signed   __int8         cl_char;\ntypedef unsigned __int8         cl_uchar;\ntypedef signed   __int16        cl_short;\ntypedef unsigned __int16        cl_ushort;\ntypedef signed   __int32        cl_int;\ntypedef unsigned __int32        cl_uint;\ntypedef signed   __int64        cl_long;\ntypedef unsigned __int64        cl_ulong;\n\ntypedef unsigned __int16        cl_half;\ntypedef float                   cl_float;\ntypedef double                  cl_double;\n\n/* Macro names and corresponding values defined by OpenCL */\n#define CL_CHAR_BIT         8\n#define CL_SCHAR_MAX        127\n#define CL_SCHAR_MIN        (-127-1)\n#define CL_CHAR_MAX         CL_SCHAR_MAX\n#define CL_CHAR_MIN         CL_SCHAR_MIN\n#define CL_UCHAR_MAX        255\n#define CL_SHRT_MAX         32767\n#define CL_SHRT_MIN         (-32767-1)\n#define CL_USHRT_MAX        65535\n#define CL_INT_MAX          2147483647\n#define CL_INT_MIN          (-2147483647-1)\n#define CL_UINT_MAX         0xffffffffU\n#define CL_LONG_MAX         ((cl_long) 0x7FFFFFFFFFFFFFFFLL)\n#define CL_LONG_MIN         ((cl_long) -0x7FFFFFFFFFFFFFFFLL - 1LL)\n#define CL_ULONG_MAX        ((cl_ulong) 0xFFFFFFFFFFFFFFFFULL)\n\n#define CL_FLT_DIG          6\n#define CL_FLT_MANT_DIG     24\n#define CL_FLT_MAX_10_EXP   +38\n#define CL_FLT_MAX_EXP      +128\n#define CL_FLT_MIN_10_EXP   -37\n#define CL_FLT_MIN_EXP      -125\n#define CL_FLT_RADIX        2\n#define CL_FLT_MAX          340282346638528859811704183484516925440.0f\n#define CL_FLT_MIN          1.175494350822287507969e-38f\n#define CL_FLT_EPSILON      0x1.0p-23f\n\n#define CL_DBL_DIG          15\n#define CL_DBL_MANT_DIG     53\n#define CL_DBL_MAX_10_EXP   +308\n#define CL_DBL_MAX_EXP      +1024\n#define CL_DBL_MIN_10_EXP   -307\n#define CL_DBL_MIN_EXP      -1021\n#define CL_DBL_RADIX        2\n#define CL_DBL_MAX          179769313486231570814527423731704356798070567525844996598917476803157260780028538760589558632766878171540458953514382464234321326889464182768467546703537516986049910576551282076245490090389328944075868508455133942304583236903222948165808559332123348274797826204144723168738177180919299881250404026184124858368.0\n#define CL_DBL_MIN          2.225073858507201383090e-308\n#define CL_DBL_EPSILON      2.220446049250313080847e-16\n\n#define  CL_M_E             2.718281828459045090796\n#define  CL_M_LOG2E         1.442695040888963387005\n#define  CL_M_LOG10E        0.434294481903251816668\n#define  CL_M_LN2           0.693147180559945286227\n#define  CL_M_LN10          2.302585092994045901094\n#define  CL_M_PI            3.141592653589793115998\n#define  CL_M_PI_2          1.570796326794896557999\n#define  CL_M_PI_4          0.785398163397448278999\n#define  CL_M_1_PI          0.318309886183790691216\n#define  CL_M_2_PI          0.636619772367581382433\n#define  CL_M_2_SQRTPI      1.128379167095512558561\n#define  CL_M_SQRT2         1.414213562373095145475\n#define  CL_M_SQRT1_2       0.707106781186547572737\n\n#define  CL_M_E_F           2.71828174591064f\n#define  CL_M_LOG2E_F       1.44269502162933f\n#define  CL_M_LOG10E_F      0.43429449200630f\n#define  CL_M_LN2_F         0.69314718246460f\n#define  CL_M_LN10_F        2.30258512496948f\n#define  CL_M_PI_F          3.14159274101257f\n#define  CL_M_PI_2_F        1.57079637050629f\n#define  CL_M_PI_4_F        0.78539818525314f\n#define  CL_M_1_PI_F        0.31830987334251f\n#define  CL_M_2_PI_F        0.63661974668503f\n#define  CL_M_2_SQRTPI_F    1.12837922573090f\n#define  CL_M_SQRT2_F       1.41421353816986f\n#define  CL_M_SQRT1_2_F     0.70710676908493f\n\n#define CL_NAN              (CL_INFINITY - CL_INFINITY)\n#define CL_HUGE_VALF        ((cl_float) 1e50)\n#define CL_HUGE_VAL         ((cl_double) 1e500)\n#define CL_MAXFLOAT         CL_FLT_MAX\n#define CL_INFINITY         CL_HUGE_VALF\n\n#else\n\n#include <stdint.h>\n\n/* scalar types  */\ntypedef int8_t          cl_char;\ntypedef uint8_t         cl_uchar;\ntypedef int16_t         cl_short    __attribute__((aligned(2)));\ntypedef uint16_t        cl_ushort   __attribute__((aligned(2)));\ntypedef int32_t         cl_int      __attribute__((aligned(4)));\ntypedef uint32_t        cl_uint     __attribute__((aligned(4)));\ntypedef int64_t         cl_long     __attribute__((aligned(8)));\ntypedef uint64_t        cl_ulong    __attribute__((aligned(8)));\n\ntypedef uint16_t        cl_half     __attribute__((aligned(2)));\ntypedef float           cl_float    __attribute__((aligned(4)));\ntypedef double          cl_double   __attribute__((aligned(8)));\n\n/* Macro names and corresponding values defined by OpenCL */\n#define CL_CHAR_BIT         8\n#define CL_SCHAR_MAX        127\n#define CL_SCHAR_MIN        (-127-1)\n#define CL_CHAR_MAX         CL_SCHAR_MAX\n#define CL_CHAR_MIN         CL_SCHAR_MIN\n#define CL_UCHAR_MAX        255\n#define CL_SHRT_MAX         32767\n#define CL_SHRT_MIN         (-32767-1)\n#define CL_USHRT_MAX        65535\n#define CL_INT_MAX          2147483647\n#define CL_INT_MIN          (-2147483647-1)\n#define CL_UINT_MAX         0xffffffffU\n#define CL_LONG_MAX         ((cl_long) 0x7FFFFFFFFFFFFFFFLL)\n#define CL_LONG_MIN         ((cl_long) -0x7FFFFFFFFFFFFFFFLL - 1LL)\n#define CL_ULONG_MAX        ((cl_ulong) 0xFFFFFFFFFFFFFFFFULL)\n\n#define CL_FLT_DIG          6\n#define CL_FLT_MANT_DIG     24\n#define CL_FLT_MAX_10_EXP   +38\n#define CL_FLT_MAX_EXP      +128\n#define CL_FLT_MIN_10_EXP   -37\n#define CL_FLT_MIN_EXP      -125\n#define CL_FLT_RADIX        2\n#define CL_FLT_MAX          0x1.fffffep127f\n#define CL_FLT_MIN          0x1.0p-126f\n#define CL_FLT_EPSILON      0x1.0p-23f\n\n#define CL_DBL_DIG          15\n#define CL_DBL_MANT_DIG     53\n#define CL_DBL_MAX_10_EXP   +308\n#define CL_DBL_MAX_EXP      +1024\n#define CL_DBL_MIN_10_EXP   -307\n#define CL_DBL_MIN_EXP      -1021\n#define CL_DBL_RADIX        2\n#define CL_DBL_MAX          0x1.fffffffffffffp1023\n#define CL_DBL_MIN          0x1.0p-1022\n#define CL_DBL_EPSILON      0x1.0p-52\n\n#define  CL_M_E             2.718281828459045090796\n#define  CL_M_LOG2E         1.442695040888963387005\n#define  CL_M_LOG10E        0.434294481903251816668\n#define  CL_M_LN2           0.693147180559945286227\n#define  CL_M_LN10          2.302585092994045901094\n#define  CL_M_PI            3.141592653589793115998\n#define  CL_M_PI_2          1.570796326794896557999\n#define  CL_M_PI_4          0.785398163397448278999\n#define  CL_M_1_PI          0.318309886183790691216\n#define  CL_M_2_PI          0.636619772367581382433\n#define  CL_M_2_SQRTPI      1.128379167095512558561\n#define  CL_M_SQRT2         1.414213562373095145475\n#define  CL_M_SQRT1_2       0.707106781186547572737\n\n#define  CL_M_E_F           2.71828174591064f\n#define  CL_M_LOG2E_F       1.44269502162933f\n#define  CL_M_LOG10E_F      0.43429449200630f\n#define  CL_M_LN2_F         0.69314718246460f\n#define  CL_M_LN10_F        2.30258512496948f\n#define  CL_M_PI_F          3.14159274101257f\n#define  CL_M_PI_2_F        1.57079637050629f\n#define  CL_M_PI_4_F        0.78539818525314f\n#define  CL_M_1_PI_F        0.31830987334251f\n#define  CL_M_2_PI_F        0.63661974668503f\n#define  CL_M_2_SQRTPI_F    1.12837922573090f\n#define  CL_M_SQRT2_F       1.41421353816986f\n#define  CL_M_SQRT1_2_F     0.70710676908493f\n\n#if defined( __GNUC__ )\n   #define CL_HUGE_VALF     __builtin_huge_valf()\n   #define CL_HUGE_VAL      __builtin_huge_val()\n   #define CL_NAN           __builtin_nanf( \"\" )\n#else\n   #define CL_HUGE_VALF     ((cl_float) 1e50)\n   #define CL_HUGE_VAL      ((cl_double) 1e500)\n   float nanf( const char * );\n   #define CL_NAN           nanf( \"\" )  \n#endif\n#define CL_MAXFLOAT         CL_FLT_MAX\n#define CL_INFINITY         CL_HUGE_VALF\n\n#endif\n\n#include <stddef.h>\n\n/* Mirror types to GL types. Mirror types allow us to avoid deciding which 87s to load based on whether we are using GL or GLES here. */\ntypedef unsigned int cl_GLuint;\ntypedef int          cl_GLint;\ntypedef unsigned int cl_GLenum;\n\n/*\n * Vector types \n *\n *  Note:   OpenCL requires that all types be naturally aligned. \n *          This means that vector types must be naturally aligned.\n *          For example, a vector of four floats must be aligned to\n *          a 16 byte boundary (calculated as 4 * the natural 4-byte \n *          alignment of the float).  The alignment qualifiers here\n *          will only function properly if your compiler supports them\n *          and if you don't actively work to defeat them.  For example,\n *          in order for a cl_float4 to be 16 byte aligned in a struct,\n *          the start of the struct must itself be 16-byte aligned. \n *\n *          Maintaining proper alignment is the user's responsibility.\n */\n\n/* Define basic vector types */\n#if defined( __VEC__ )\n   #include <altivec.h>   /* may be omitted depending on compiler. AltiVec spec provides no way to detect whether the header is required. */\n   typedef vector unsigned char     __cl_uchar16;\n   typedef vector signed char       __cl_char16;\n   typedef vector unsigned short    __cl_ushort8;\n   typedef vector signed short      __cl_short8;\n   typedef vector unsigned int      __cl_uint4;\n   typedef vector signed int        __cl_int4;\n   typedef vector float             __cl_float4;\n   #define  __CL_UCHAR16__  1\n   #define  __CL_CHAR16__   1\n   #define  __CL_USHORT8__  1\n   #define  __CL_SHORT8__   1\n   #define  __CL_UINT4__    1\n   #define  __CL_INT4__     1\n   #define  __CL_FLOAT4__   1\n#endif\n\n#if defined( __SSE__ )\n    #if defined( __MINGW64__ )\n        #include <intrin.h>\n    #else\n        #include <xmmintrin.h>\n    #endif\n    #if defined( __GNUC__ )\n        typedef float __cl_float4   __attribute__((vector_size(16)));\n    #else\n        typedef __m128 __cl_float4;\n    #endif\n    #define __CL_FLOAT4__   1\n#endif\n\n#if defined( __SSE2__ )\n    #if defined( __MINGW64__ )\n        #include <intrin.h>\n    #else\n        #include <emmintrin.h>\n    #endif\n    #if defined( __GNUC__ )\n        typedef cl_uchar    __cl_uchar16    __attribute__((vector_size(16)));\n        typedef cl_char     __cl_char16     __attribute__((vector_size(16)));\n        typedef cl_ushort   __cl_ushort8    __attribute__((vector_size(16)));\n        typedef cl_short    __cl_short8     __attribute__((vector_size(16)));\n        typedef cl_uint     __cl_uint4      __attribute__((vector_size(16)));\n        typedef cl_int      __cl_int4       __attribute__((vector_size(16)));\n        typedef cl_ulong    __cl_ulong2     __attribute__((vector_size(16)));\n        typedef cl_long     __cl_long2      __attribute__((vector_size(16)));\n        typedef cl_double   __cl_double2    __attribute__((vector_size(16)));\n    #else\n        typedef __m128i __cl_uchar16;\n        typedef __m128i __cl_char16;\n        typedef __m128i __cl_ushort8;\n        typedef __m128i __cl_short8;\n        typedef __m128i __cl_uint4;\n        typedef __m128i __cl_int4;\n        typedef __m128i __cl_ulong2;\n        typedef __m128i __cl_long2;\n        typedef __m128d __cl_double2;\n    #endif\n    #define __CL_UCHAR16__  1\n    #define __CL_CHAR16__   1\n    #define __CL_USHORT8__  1\n    #define __CL_SHORT8__   1\n    #define __CL_INT4__     1\n    #define __CL_UINT4__    1\n    #define __CL_ULONG2__   1\n    #define __CL_LONG2__    1\n    #define __CL_DOUBLE2__  1\n#endif\n\n#if defined( __MMX__ )\n    #include <mmintrin.h>\n    #if defined( __GNUC__ )\n        typedef cl_uchar    __cl_uchar8     __attribute__((vector_size(8)));\n        typedef cl_char     __cl_char8      __attribute__((vector_size(8)));\n        typedef cl_ushort   __cl_ushort4    __attribute__((vector_size(8)));\n        typedef cl_short    __cl_short4     __attribute__((vector_size(8)));\n        typedef cl_uint     __cl_uint2      __attribute__((vector_size(8)));\n        typedef cl_int      __cl_int2       __attribute__((vector_size(8)));\n        typedef cl_ulong    __cl_ulong1     __attribute__((vector_size(8)));\n        typedef cl_long     __cl_long1      __attribute__((vector_size(8)));\n        typedef cl_float    __cl_float2     __attribute__((vector_size(8)));\n    #else\n        typedef __m64       __cl_uchar8;\n        typedef __m64       __cl_char8;\n        typedef __m64       __cl_ushort4;\n        typedef __m64       __cl_short4;\n        typedef __m64       __cl_uint2;\n        typedef __m64       __cl_int2;\n        typedef __m64       __cl_ulong1;\n        typedef __m64       __cl_long1;\n        typedef __m64       __cl_float2;\n    #endif\n    #define __CL_UCHAR8__   1\n    #define __CL_CHAR8__    1\n    #define __CL_USHORT4__  1\n    #define __CL_SHORT4__   1\n    #define __CL_INT2__     1\n    #define __CL_UINT2__    1\n    #define __CL_ULONG1__   1\n    #define __CL_LONG1__    1\n    #define __CL_FLOAT2__   1\n#endif\n\n#if defined( __AVX__ )\n    #if defined( __MINGW64__ )\n        #include <intrin.h>\n    #else\n        #include <immintrin.h> \n    #endif\n    #if defined( __GNUC__ )\n        typedef cl_float    __cl_float8     __attribute__((vector_size(32)));\n        typedef cl_double   __cl_double4    __attribute__((vector_size(32)));\n    #else\n        typedef __m256      __cl_float8;\n        typedef __m256d     __cl_double4;\n    #endif\n    #define __CL_FLOAT8__   1\n    #define __CL_DOUBLE4__  1\n#endif\n\n/* Define capabilities for anonymous struct members. */\n#if defined( __GNUC__) && ! defined( __STRICT_ANSI__ )\n#define  __CL_HAS_ANON_STRUCT__ 1\n#define  __CL_ANON_STRUCT__ __extension__\n#elif defined( _WIN32) && (_MSC_VER >= 1500)\n   /* Microsoft Developer Studio 2008 supports anonymous structs, but\n    * complains by default. */\n#define  __CL_HAS_ANON_STRUCT__ 1\n#define  __CL_ANON_STRUCT__\n   /* Disable warning C4201: nonstandard extension used : nameless\n    * struct/union */\n#pragma warning( push )\n#pragma warning( disable : 4201 )\n#else\n#define  __CL_HAS_ANON_STRUCT__ 0\n#define  __CL_ANON_STRUCT__\n#endif\n\n/* Define alignment keys */\n#if defined( __GNUC__ )\n    #define CL_ALIGNED(_x)          __attribute__ ((aligned(_x)))\n#elif defined( _WIN32) && (_MSC_VER)\n    /* Alignment keys neutered on windows because MSVC can't swallow function arguments with alignment requirements     */\n    /* http://msdn.microsoft.com/en-us/library/373ak2y1%28VS.71%29.aspx                                                 */\n    /* #include <crtdefs.h>                                                                                             */\n    /* #define CL_ALIGNED(_x)          _CRT_ALIGN(_x)                                                                   */\n    #define CL_ALIGNED(_x)\n#else\n   #warning  Need to implement some method to align data here\n   #define  CL_ALIGNED(_x)\n#endif\n\n/* Indicate whether .xyzw, .s0123 and .hi.lo are supported */\n#if __CL_HAS_ANON_STRUCT__\n    /* .xyzw and .s0123...{f|F} are supported */\n    #define CL_HAS_NAMED_VECTOR_FIELDS 1\n    /* .hi and .lo are supported */\n    #define CL_HAS_HI_LO_VECTOR_FIELDS 1\n#endif\n\n/* Define cl_vector types */\n\n/* ---- cl_charn ---- */\ntypedef union\n{\n    cl_char  CL_ALIGNED(2) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_char  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_char  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_char  lo, hi; };\n#endif\n#if defined( __CL_CHAR2__) \n    __cl_char2     v2;\n#endif\n}cl_char2;\n\ntypedef union\n{\n    cl_char  CL_ALIGNED(4) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_char  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_char  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_char2 lo, hi; };\n#endif\n#if defined( __CL_CHAR2__) \n    __cl_char2     v2[2];\n#endif\n#if defined( __CL_CHAR4__) \n    __cl_char4     v4;\n#endif\n}cl_char4;\n\n/* cl_char3 is identical in size, alignment and behavior to cl_char4. See section 6.1.5. */\ntypedef  cl_char4  cl_char3;\n\ntypedef union\n{\n    cl_char   CL_ALIGNED(8) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_char  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_char  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_char4 lo, hi; };\n#endif\n#if defined( __CL_CHAR2__) \n    __cl_char2     v2[4];\n#endif\n#if defined( __CL_CHAR4__) \n    __cl_char4     v4[2];\n#endif\n#if defined( __CL_CHAR8__ )\n    __cl_char8     v8;\n#endif\n}cl_char8;\n\ntypedef union\n{\n    cl_char  CL_ALIGNED(16) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_char  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_char  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_char8 lo, hi; };\n#endif\n#if defined( __CL_CHAR2__) \n    __cl_char2     v2[8];\n#endif\n#if defined( __CL_CHAR4__) \n    __cl_char4     v4[4];\n#endif\n#if defined( __CL_CHAR8__ )\n    __cl_char8     v8[2];\n#endif\n#if defined( __CL_CHAR16__ )\n    __cl_char16    v16;\n#endif\n}cl_char16;\n\n\n/* ---- cl_ucharn ---- */\ntypedef union\n{\n    cl_uchar  CL_ALIGNED(2) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uchar  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar  lo, hi; };\n#endif\n#if defined( __cl_uchar2__) \n    __cl_uchar2     v2;\n#endif\n}cl_uchar2;\n\ntypedef union\n{\n    cl_uchar  CL_ALIGNED(4) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uchar  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar2 lo, hi; };\n#endif\n#if defined( __CL_UCHAR2__) \n    __cl_uchar2     v2[2];\n#endif\n#if defined( __CL_UCHAR4__) \n    __cl_uchar4     v4;\n#endif\n}cl_uchar4;\n\n/* cl_uchar3 is identical in size, alignment and behavior to cl_uchar4. See section 6.1.5. */\ntypedef  cl_uchar4  cl_uchar3;\n\ntypedef union\n{\n    cl_uchar   CL_ALIGNED(8) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uchar  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar4 lo, hi; };\n#endif\n#if defined( __CL_UCHAR2__) \n    __cl_uchar2     v2[4];\n#endif\n#if defined( __CL_UCHAR4__) \n    __cl_uchar4     v4[2];\n#endif\n#if defined( __CL_UCHAR8__ )\n    __cl_uchar8     v8;\n#endif\n}cl_uchar8;\n\ntypedef union\n{\n    cl_uchar  CL_ALIGNED(16) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uchar  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_uchar8 lo, hi; };\n#endif\n#if defined( __CL_UCHAR2__) \n    __cl_uchar2     v2[8];\n#endif\n#if defined( __CL_UCHAR4__) \n    __cl_uchar4     v4[4];\n#endif\n#if defined( __CL_UCHAR8__ )\n    __cl_uchar8     v8[2];\n#endif\n#if defined( __CL_UCHAR16__ )\n    __cl_uchar16    v16;\n#endif\n}cl_uchar16;\n\n\n/* ---- cl_shortn ---- */\ntypedef union\n{\n    cl_short  CL_ALIGNED(4) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_short  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_short  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_short  lo, hi; };\n#endif\n#if defined( __CL_SHORT2__) \n    __cl_short2     v2;\n#endif\n}cl_short2;\n\ntypedef union\n{\n    cl_short  CL_ALIGNED(8) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_short  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_short  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_short2 lo, hi; };\n#endif\n#if defined( __CL_SHORT2__) \n    __cl_short2     v2[2];\n#endif\n#if defined( __CL_SHORT4__) \n    __cl_short4     v4;\n#endif\n}cl_short4;\n\n/* cl_short3 is identical in size, alignment and behavior to cl_short4. See section 6.1.5. */\ntypedef  cl_short4  cl_short3;\n\ntypedef union\n{\n    cl_short   CL_ALIGNED(16) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_short  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_short  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_short4 lo, hi; };\n#endif\n#if defined( __CL_SHORT2__) \n    __cl_short2     v2[4];\n#endif\n#if defined( __CL_SHORT4__) \n    __cl_short4     v4[2];\n#endif\n#if defined( __CL_SHORT8__ )\n    __cl_short8     v8;\n#endif\n}cl_short8;\n\ntypedef union\n{\n    cl_short  CL_ALIGNED(32) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_short  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_short  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_short8 lo, hi; };\n#endif\n#if defined( __CL_SHORT2__) \n    __cl_short2     v2[8];\n#endif\n#if defined( __CL_SHORT4__) \n    __cl_short4     v4[4];\n#endif\n#if defined( __CL_SHORT8__ )\n    __cl_short8     v8[2];\n#endif\n#if defined( __CL_SHORT16__ )\n    __cl_short16    v16;\n#endif\n}cl_short16;\n\n\n/* ---- cl_ushortn ---- */\ntypedef union\n{\n    cl_ushort  CL_ALIGNED(4) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ushort  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort  lo, hi; };\n#endif\n#if defined( __CL_USHORT2__) \n    __cl_ushort2     v2;\n#endif\n}cl_ushort2;\n\ntypedef union\n{\n    cl_ushort  CL_ALIGNED(8) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ushort  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort2 lo, hi; };\n#endif\n#if defined( __CL_USHORT2__) \n    __cl_ushort2     v2[2];\n#endif\n#if defined( __CL_USHORT4__) \n    __cl_ushort4     v4;\n#endif\n}cl_ushort4;\n\n/* cl_ushort3 is identical in size, alignment and behavior to cl_ushort4. See section 6.1.5. */\ntypedef  cl_ushort4  cl_ushort3;\n\ntypedef union\n{\n    cl_ushort   CL_ALIGNED(16) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ushort  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort4 lo, hi; };\n#endif\n#if defined( __CL_USHORT2__) \n    __cl_ushort2     v2[4];\n#endif\n#if defined( __CL_USHORT4__) \n    __cl_ushort4     v4[2];\n#endif\n#if defined( __CL_USHORT8__ )\n    __cl_ushort8     v8;\n#endif\n}cl_ushort8;\n\ntypedef union\n{\n    cl_ushort  CL_ALIGNED(32) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ushort  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_ushort8 lo, hi; };\n#endif\n#if defined( __CL_USHORT2__) \n    __cl_ushort2     v2[8];\n#endif\n#if defined( __CL_USHORT4__) \n    __cl_ushort4     v4[4];\n#endif\n#if defined( __CL_USHORT8__ )\n    __cl_ushort8     v8[2];\n#endif\n#if defined( __CL_USHORT16__ )\n    __cl_ushort16    v16;\n#endif\n}cl_ushort16;\n\n/* ---- cl_intn ---- */\ntypedef union\n{\n    cl_int  CL_ALIGNED(8) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_int  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_int  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_int  lo, hi; };\n#endif\n#if defined( __CL_INT2__) \n    __cl_int2     v2;\n#endif\n}cl_int2;\n\ntypedef union\n{\n    cl_int  CL_ALIGNED(16) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_int  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_int  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_int2 lo, hi; };\n#endif\n#if defined( __CL_INT2__) \n    __cl_int2     v2[2];\n#endif\n#if defined( __CL_INT4__) \n    __cl_int4     v4;\n#endif\n}cl_int4;\n\n/* cl_int3 is identical in size, alignment and behavior to cl_int4. See section 6.1.5. */\ntypedef  cl_int4  cl_int3;\n\ntypedef union\n{\n    cl_int   CL_ALIGNED(32) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_int  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_int  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_int4 lo, hi; };\n#endif\n#if defined( __CL_INT2__) \n    __cl_int2     v2[4];\n#endif\n#if defined( __CL_INT4__) \n    __cl_int4     v4[2];\n#endif\n#if defined( __CL_INT8__ )\n    __cl_int8     v8;\n#endif\n}cl_int8;\n\ntypedef union\n{\n    cl_int  CL_ALIGNED(64) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_int  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_int  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_int8 lo, hi; };\n#endif\n#if defined( __CL_INT2__) \n    __cl_int2     v2[8];\n#endif\n#if defined( __CL_INT4__) \n    __cl_int4     v4[4];\n#endif\n#if defined( __CL_INT8__ )\n    __cl_int8     v8[2];\n#endif\n#if defined( __CL_INT16__ )\n    __cl_int16    v16;\n#endif\n}cl_int16;\n\n\n/* ---- cl_uintn ---- */\ntypedef union\n{\n    cl_uint  CL_ALIGNED(8) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uint  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_uint  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_uint  lo, hi; };\n#endif\n#if defined( __CL_UINT2__) \n    __cl_uint2     v2;\n#endif\n}cl_uint2;\n\ntypedef union\n{\n    cl_uint  CL_ALIGNED(16) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uint  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_uint  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_uint2 lo, hi; };\n#endif\n#if defined( __CL_UINT2__) \n    __cl_uint2     v2[2];\n#endif\n#if defined( __CL_UINT4__) \n    __cl_uint4     v4;\n#endif\n}cl_uint4;\n\n/* cl_uint3 is identical in size, alignment and behavior to cl_uint4. See section 6.1.5. */\ntypedef  cl_uint4  cl_uint3;\n\ntypedef union\n{\n    cl_uint   CL_ALIGNED(32) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uint  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_uint  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_uint4 lo, hi; };\n#endif\n#if defined( __CL_UINT2__) \n    __cl_uint2     v2[4];\n#endif\n#if defined( __CL_UINT4__) \n    __cl_uint4     v4[2];\n#endif\n#if defined( __CL_UINT8__ )\n    __cl_uint8     v8;\n#endif\n}cl_uint8;\n\ntypedef union\n{\n    cl_uint  CL_ALIGNED(64) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_uint  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_uint  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_uint8 lo, hi; };\n#endif\n#if defined( __CL_UINT2__) \n    __cl_uint2     v2[8];\n#endif\n#if defined( __CL_UINT4__) \n    __cl_uint4     v4[4];\n#endif\n#if defined( __CL_UINT8__ )\n    __cl_uint8     v8[2];\n#endif\n#if defined( __CL_UINT16__ )\n    __cl_uint16    v16;\n#endif\n}cl_uint16;\n\n/* ---- cl_longn ---- */\ntypedef union\n{\n    cl_long  CL_ALIGNED(16) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_long  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_long  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_long  lo, hi; };\n#endif\n#if defined( __CL_LONG2__) \n    __cl_long2     v2;\n#endif\n}cl_long2;\n\ntypedef union\n{\n    cl_long  CL_ALIGNED(32) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_long  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_long  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_long2 lo, hi; };\n#endif\n#if defined( __CL_LONG2__) \n    __cl_long2     v2[2];\n#endif\n#if defined( __CL_LONG4__) \n    __cl_long4     v4;\n#endif\n}cl_long4;\n\n/* cl_long3 is identical in size, alignment and behavior to cl_long4. See section 6.1.5. */\ntypedef  cl_long4  cl_long3;\n\ntypedef union\n{\n    cl_long   CL_ALIGNED(64) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_long  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_long  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_long4 lo, hi; };\n#endif\n#if defined( __CL_LONG2__) \n    __cl_long2     v2[4];\n#endif\n#if defined( __CL_LONG4__) \n    __cl_long4     v4[2];\n#endif\n#if defined( __CL_LONG8__ )\n    __cl_long8     v8;\n#endif\n}cl_long8;\n\ntypedef union\n{\n    cl_long  CL_ALIGNED(128) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_long  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_long  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_long8 lo, hi; };\n#endif\n#if defined( __CL_LONG2__) \n    __cl_long2     v2[8];\n#endif\n#if defined( __CL_LONG4__) \n    __cl_long4     v4[4];\n#endif\n#if defined( __CL_LONG8__ )\n    __cl_long8     v8[2];\n#endif\n#if defined( __CL_LONG16__ )\n    __cl_long16    v16;\n#endif\n}cl_long16;\n\n\n/* ---- cl_ulongn ---- */\ntypedef union\n{\n    cl_ulong  CL_ALIGNED(16) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ulong  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong  lo, hi; };\n#endif\n#if defined( __CL_ULONG2__) \n    __cl_ulong2     v2;\n#endif\n}cl_ulong2;\n\ntypedef union\n{\n    cl_ulong  CL_ALIGNED(32) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ulong  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong2 lo, hi; };\n#endif\n#if defined( __CL_ULONG2__) \n    __cl_ulong2     v2[2];\n#endif\n#if defined( __CL_ULONG4__) \n    __cl_ulong4     v4;\n#endif\n}cl_ulong4;\n\n/* cl_ulong3 is identical in size, alignment and behavior to cl_ulong4. See section 6.1.5. */\ntypedef  cl_ulong4  cl_ulong3;\n\ntypedef union\n{\n    cl_ulong   CL_ALIGNED(64) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ulong  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong4 lo, hi; };\n#endif\n#if defined( __CL_ULONG2__) \n    __cl_ulong2     v2[4];\n#endif\n#if defined( __CL_ULONG4__) \n    __cl_ulong4     v4[2];\n#endif\n#if defined( __CL_ULONG8__ )\n    __cl_ulong8     v8;\n#endif\n}cl_ulong8;\n\ntypedef union\n{\n    cl_ulong  CL_ALIGNED(128) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_ulong  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_ulong8 lo, hi; };\n#endif\n#if defined( __CL_ULONG2__) \n    __cl_ulong2     v2[8];\n#endif\n#if defined( __CL_ULONG4__) \n    __cl_ulong4     v4[4];\n#endif\n#if defined( __CL_ULONG8__ )\n    __cl_ulong8     v8[2];\n#endif\n#if defined( __CL_ULONG16__ )\n    __cl_ulong16    v16;\n#endif\n}cl_ulong16;\n\n\n/* --- cl_floatn ---- */\n\ntypedef union\n{\n    cl_float  CL_ALIGNED(8) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_float  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_float  s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_float  lo, hi; };\n#endif\n#if defined( __CL_FLOAT2__) \n    __cl_float2     v2;\n#endif\n}cl_float2;\n\ntypedef union\n{\n    cl_float  CL_ALIGNED(16) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_float   x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_float   s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_float2  lo, hi; };\n#endif\n#if defined( __CL_FLOAT2__) \n    __cl_float2     v2[2];\n#endif\n#if defined( __CL_FLOAT4__) \n    __cl_float4     v4;\n#endif\n}cl_float4;\n\n/* cl_float3 is identical in size, alignment and behavior to cl_float4. See section 6.1.5. */\ntypedef  cl_float4  cl_float3;\n\ntypedef union\n{\n    cl_float   CL_ALIGNED(32) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_float   x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_float   s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_float4  lo, hi; };\n#endif\n#if defined( __CL_FLOAT2__) \n    __cl_float2     v2[4];\n#endif\n#if defined( __CL_FLOAT4__) \n    __cl_float4     v4[2];\n#endif\n#if defined( __CL_FLOAT8__ )\n    __cl_float8     v8;\n#endif\n}cl_float8;\n\ntypedef union\n{\n    cl_float  CL_ALIGNED(64) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_float  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_float  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_float8 lo, hi; };\n#endif\n#if defined( __CL_FLOAT2__) \n    __cl_float2     v2[8];\n#endif\n#if defined( __CL_FLOAT4__) \n    __cl_float4     v4[4];\n#endif\n#if defined( __CL_FLOAT8__ )\n    __cl_float8     v8[2];\n#endif\n#if defined( __CL_FLOAT16__ )\n    __cl_float16    v16;\n#endif\n}cl_float16;\n\n/* --- cl_doublen ---- */\n\ntypedef union\n{\n    cl_double  CL_ALIGNED(16) s[2];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_double  x, y; };\n   __CL_ANON_STRUCT__ struct{ cl_double s0, s1; };\n   __CL_ANON_STRUCT__ struct{ cl_double lo, hi; };\n#endif\n#if defined( __CL_DOUBLE2__) \n    __cl_double2     v2;\n#endif\n}cl_double2;\n\ntypedef union\n{\n    cl_double  CL_ALIGNED(32) s[4];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_double  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_double  s0, s1, s2, s3; };\n   __CL_ANON_STRUCT__ struct{ cl_double2 lo, hi; };\n#endif\n#if defined( __CL_DOUBLE2__) \n    __cl_double2     v2[2];\n#endif\n#if defined( __CL_DOUBLE4__) \n    __cl_double4     v4;\n#endif\n}cl_double4;\n\n/* cl_double3 is identical in size, alignment and behavior to cl_double4. See section 6.1.5. */\ntypedef  cl_double4  cl_double3;\n\ntypedef union\n{\n    cl_double   CL_ALIGNED(64) s[8];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_double  x, y, z, w; };\n   __CL_ANON_STRUCT__ struct{ cl_double  s0, s1, s2, s3, s4, s5, s6, s7; };\n   __CL_ANON_STRUCT__ struct{ cl_double4 lo, hi; };\n#endif\n#if defined( __CL_DOUBLE2__) \n    __cl_double2     v2[4];\n#endif\n#if defined( __CL_DOUBLE4__) \n    __cl_double4     v4[2];\n#endif\n#if defined( __CL_DOUBLE8__ )\n    __cl_double8     v8;\n#endif\n}cl_double8;\n\ntypedef union\n{\n    cl_double  CL_ALIGNED(128) s[16];\n#if __CL_HAS_ANON_STRUCT__\n   __CL_ANON_STRUCT__ struct{ cl_double  x, y, z, w, __spacer4, __spacer5, __spacer6, __spacer7, __spacer8, __spacer9, sa, sb, sc, sd, se, sf; };\n   __CL_ANON_STRUCT__ struct{ cl_double  s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, sA, sB, sC, sD, sE, sF; };\n   __CL_ANON_STRUCT__ struct{ cl_double8 lo, hi; };\n#endif\n#if defined( __CL_DOUBLE2__) \n    __cl_double2     v2[8];\n#endif\n#if defined( __CL_DOUBLE4__) \n    __cl_double4     v4[4];\n#endif\n#if defined( __CL_DOUBLE8__ )\n    __cl_double8     v8[2];\n#endif\n#if defined( __CL_DOUBLE16__ )\n    __cl_double16    v16;\n#endif\n}cl_double16;\n\n/* Macro to facilitate debugging \n * Usage:\n *   Place CL_PROGRAM_STRING_DEBUG_INFO on the line before the first line of your source. \n *   The first line ends with:   CL_PROGRAM_STRING_DEBUG_INFO \\\"\n *   Each line thereafter of OpenCL C source must end with: \\n\\\n *   The last line ends in \";\n *\n *   Example:\n *\n *   const char *my_program = CL_PROGRAM_STRING_DEBUG_INFO \"\\\n *   kernel void foo( int a, float * b )             \\n\\\n *   {                                               \\n\\\n *      // my comment                                \\n\\\n *      *b[ get_global_id(0)] = a;                   \\n\\\n *   }                                               \\n\\\n *   \";\n *\n * This should correctly set up the line, (column) and file information for your source \n * string so you can do source level debugging.\n */\n#define  __CL_STRINGIFY( _x )               # _x\n#define  _CL_STRINGIFY( _x )                __CL_STRINGIFY( _x )\n#define  CL_PROGRAM_STRING_DEBUG_INFO       \"#line \"  _CL_STRINGIFY(__LINE__) \" \\\"\" __FILE__ \"\\\" \\n\\n\" \n  \n#ifdef __cplusplus\n}\n#endif\n\n#undef __CL_HAS_ANON_STRUCT__\n#undef __CL_ANON_STRUCT__\n#if defined( _WIN32) && (_MSC_VER >= 1500)\n#pragma warning( pop )\n#endif\n\n#endif  /* __CL_PLATFORM_H  */\n"
  },
  {
    "path": "phonelibs/opencl/include/CL/opencl.h",
    "content": "/*******************************************************************************\n * Copyright (c) 2008-2015 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and/or associated documentation files (the\n * \"Materials\"), to deal in the Materials without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Materials, and to\n * permit persons to whom the Materials are furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Materials.\n *\n * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS\n * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS\n * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT\n *    https://www.khronos.org/registry/\n *\n * THE MATERIALS ARE PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.\n ******************************************************************************/\n\n/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */\n\n#ifndef __OPENCL_H\n#define __OPENCL_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#ifdef __APPLE__\n\n#include <OpenCL/cl.h>\n#include <OpenCL/cl_gl.h>\n#include <OpenCL/cl_gl_ext.h>\n#include <OpenCL/cl_ext.h>\n\n#else\n\n#include <CL/cl.h>\n#include <CL/cl_gl.h>\n#include <CL/cl_gl_ext.h>\n#include <CL/cl_ext.h>\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __OPENCL_H   */\n\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Audio.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** @file OMX_Audio.h - OpenMax IL version 1.1.2\n *  The structures needed by Audio components to exchange\n *  parameters and configuration data with the componenmilts.\n */\n\n#ifndef OMX_Audio_h\n#define OMX_Audio_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n/* Each OMX header must include all required header files to allow the\n *  header to compile without errors.  The includes below are required\n *  for this header file to compile successfully \n */\n\n#include <OMX_Core.h>\n\n/** @defgroup midi MIDI\n * @ingroup audio\n */\n \n/** @defgroup effects Audio effects\n * @ingroup audio\n */\n\n/** @defgroup audio OpenMAX IL Audio Domain\n * Structures for OpenMAX IL Audio domain\n * @{\n */\n\n/** Enumeration used to define the possible audio codings.  \n *  If \"OMX_AUDIO_CodingUnused\" is selected, the coding selection must \n *  be done in a vendor specific way.  Since this is for an audio \n *  processing element this enum is relevant.  However, for another \n *  type of component other enums would be in this area.\n */\ntypedef enum OMX_AUDIO_CODINGTYPE {\n    OMX_AUDIO_CodingUnused = 0,  /**< Placeholder value when coding is N/A  */\n    OMX_AUDIO_CodingAutoDetect,  /**< auto detection of audio format */\n    OMX_AUDIO_CodingPCM,         /**< Any variant of PCM coding */\n    OMX_AUDIO_CodingADPCM,       /**< Any variant of ADPCM encoded data */\n    OMX_AUDIO_CodingAMR,         /**< Any variant of AMR encoded data */\n    OMX_AUDIO_CodingGSMFR,       /**< Any variant of GSM fullrate (i.e. GSM610) */\n    OMX_AUDIO_CodingGSMEFR,      /**< Any variant of GSM Enhanced Fullrate encoded data*/\n    OMX_AUDIO_CodingGSMHR,       /**< Any variant of GSM Halfrate encoded data */\n    OMX_AUDIO_CodingPDCFR,       /**< Any variant of PDC Fullrate encoded data */\n    OMX_AUDIO_CodingPDCEFR,      /**< Any variant of PDC Enhanced Fullrate encoded data */\n    OMX_AUDIO_CodingPDCHR,       /**< Any variant of PDC Halfrate encoded data */\n    OMX_AUDIO_CodingTDMAFR,      /**< Any variant of TDMA Fullrate encoded data (TIA/EIA-136-420) */\n    OMX_AUDIO_CodingTDMAEFR,     /**< Any variant of TDMA Enhanced Fullrate encoded data (TIA/EIA-136-410) */\n    OMX_AUDIO_CodingQCELP8,      /**< Any variant of QCELP 8kbps encoded data */\n    OMX_AUDIO_CodingQCELP13,     /**< Any variant of QCELP 13kbps encoded data */\n    OMX_AUDIO_CodingEVRC,        /**< Any variant of EVRC encoded data */\n    OMX_AUDIO_CodingSMV,         /**< Any variant of SMV encoded data */\n    OMX_AUDIO_CodingG711,        /**< Any variant of G.711 encoded data */\n    OMX_AUDIO_CodingG723,        /**< Any variant of G.723 dot 1 encoded data */\n    OMX_AUDIO_CodingG726,        /**< Any variant of G.726 encoded data */\n    OMX_AUDIO_CodingG729,        /**< Any variant of G.729 encoded data */\n    OMX_AUDIO_CodingAAC,         /**< Any variant of AAC encoded data */\n    OMX_AUDIO_CodingMP3,         /**< Any variant of MP3 encoded data */\n    OMX_AUDIO_CodingSBC,         /**< Any variant of SBC encoded data */\n    OMX_AUDIO_CodingVORBIS,      /**< Any variant of VORBIS encoded data */\n    OMX_AUDIO_CodingWMA,         /**< Any variant of WMA encoded data */\n    OMX_AUDIO_CodingRA,          /**< Any variant of RA encoded data */\n    OMX_AUDIO_CodingMIDI,        /**< Any variant of MIDI encoded data */\n    OMX_AUDIO_CodingAC3,         /**< Any variant of AC3 encoded data */\n    OMX_AUDIO_CodingKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_CodingVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_CodingMax = 0x7FFFFFFF\n} OMX_AUDIO_CODINGTYPE;\n\n\n/** The PortDefinition structure is used to define all of the parameters \n *  necessary for the compliant component to setup an input or an output audio \n *  path.  If additional information is needed to define the parameters of the\n *  port (such as frequency), additional structures must be sent such as the\n *  OMX_AUDIO_PARAM_PCMMODETYPE structure to supply the extra parameters for the port.\n */\ntypedef struct OMX_AUDIO_PORTDEFINITIONTYPE {\n    OMX_STRING cMIMEType;            /**< MIME type of data for the port */\n    OMX_NATIVE_DEVICETYPE pNativeRender; /** < platform specific reference\n                                               for an output device, \n                                               otherwise this field is 0 */\n    OMX_BOOL bFlagErrorConcealment;  /**< Turns on error concealment if it is \n                                          supported by the OMX component */\n    OMX_AUDIO_CODINGTYPE eEncoding;  /**< Type of data expected for this \n                                          port (e.g. PCM, AMR, MP3, etc) */\n} OMX_AUDIO_PORTDEFINITIONTYPE;\n\n\n/**  Port format parameter.  This structure is used to enumerate\n  *  the various data input/output format supported by the port.\n  */\ntypedef struct OMX_AUDIO_PARAM_PORTFORMATTYPE {\n    OMX_U32 nSize;                  /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;       /**< OMX specification version information */\n    OMX_U32 nPortIndex;             /**< Indicates which port to set */\n    OMX_U32 nIndex;                 /**< Indicates the enumeration index for the format from 0x0 to N-1 */\n    OMX_AUDIO_CODINGTYPE eEncoding; /**< Type of data expected for this port (e.g. PCM, AMR, MP3, etc) */\n} OMX_AUDIO_PARAM_PORTFORMATTYPE;\n\n\n/** PCM mode type  */ \ntypedef enum OMX_AUDIO_PCMMODETYPE { \n    OMX_AUDIO_PCMModeLinear = 0,  /**< Linear PCM encoded data */ \n    OMX_AUDIO_PCMModeALaw,        /**< A law PCM encoded data (G.711) */ \n    OMX_AUDIO_PCMModeMULaw,       /**< Mu law PCM encoded data (G.711)  */ \n    OMX_AUDIO_PCMModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_PCMModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_PCMModeMax = 0x7FFFFFFF \n} OMX_AUDIO_PCMMODETYPE; \n\n\ntypedef enum OMX_AUDIO_CHANNELTYPE {\n    OMX_AUDIO_ChannelNone = 0x0,    /**< Unused or empty */\n    OMX_AUDIO_ChannelLF   = 0x1,    /**< Left front */\n    OMX_AUDIO_ChannelRF   = 0x2,    /**< Right front */\n    OMX_AUDIO_ChannelCF   = 0x3,    /**< Center front */\n    OMX_AUDIO_ChannelLS   = 0x4,    /**< Left surround */\n    OMX_AUDIO_ChannelRS   = 0x5,    /**< Right surround */\n    OMX_AUDIO_ChannelLFE  = 0x6,    /**< Low frequency effects */\n    OMX_AUDIO_ChannelCS   = 0x7,    /**< Back surround */\n    OMX_AUDIO_ChannelLR   = 0x8,    /**< Left rear. */\n    OMX_AUDIO_ChannelRR   = 0x9,    /**< Right rear. */\n    OMX_AUDIO_ChannelKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_ChannelVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_ChannelMax  = 0x7FFFFFFF \n} OMX_AUDIO_CHANNELTYPE;\n\n#define OMX_AUDIO_MAXCHANNELS 16  /**< maximum number distinct audio channels that a buffer may contain */\n#define OMX_MIN_PCMPAYLOAD_MSEC 5 /**< Minimum audio buffer payload size for uncompressed (PCM) audio */\n\n/** PCM format description */ \ntypedef struct OMX_AUDIO_PARAM_PCMMODETYPE { \n    OMX_U32 nSize;                    /**< Size of this structure, in Bytes */ \n    OMX_VERSIONTYPE nVersion;         /**< OMX specification version information */ \n    OMX_U32 nPortIndex;               /**< port that this structure applies to */ \n    OMX_U32 nChannels;                /**< Number of channels (e.g. 2 for stereo) */ \n    OMX_NUMERICALDATATYPE eNumData;   /**< indicates PCM data as signed or unsigned */ \n    OMX_ENDIANTYPE eEndian;           /**< indicates PCM data as little or big endian */ \n    OMX_BOOL bInterleaved;            /**< True for normal interleaved data; false for \n                                           non-interleaved data (e.g. block data) */ \n    OMX_U32 nBitPerSample;            /**< Bit per sample */ \n    OMX_U32 nSamplingRate;            /**< Sampling rate of the source data.  Use 0 for \n                                           variable or unknown sampling rate. */ \n    OMX_AUDIO_PCMMODETYPE ePCMMode;   /**< PCM mode enumeration */ \n    OMX_AUDIO_CHANNELTYPE eChannelMapping[OMX_AUDIO_MAXCHANNELS]; /**< Slot i contains channel defined by eChannelMap[i] */\n\n} OMX_AUDIO_PARAM_PCMMODETYPE; \n\n\n/** Audio channel mode.  This is used by both AAC and MP3, although the names are more appropriate\n * for the MP3.  For example, JointStereo for MP3 is CouplingChannels for AAC. \n */\ntypedef enum OMX_AUDIO_CHANNELMODETYPE {\n    OMX_AUDIO_ChannelModeStereo = 0,  /**< 2 channels, the bitrate allocation between those \n                                          two channels changes accordingly to each channel information */\n    OMX_AUDIO_ChannelModeJointStereo, /**< mode that takes advantage of what is common between \n                                           2 channels for higher compression gain */\n    OMX_AUDIO_ChannelModeDual,        /**< 2 mono-channels, each channel is encoded with half \n                                           the bitrate of the overall bitrate */\n    OMX_AUDIO_ChannelModeMono,        /**< Mono channel mode */\n    OMX_AUDIO_ChannelModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_ChannelModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_ChannelModeMax = 0x7FFFFFFF\n} OMX_AUDIO_CHANNELMODETYPE;\n\n\ntypedef enum OMX_AUDIO_MP3STREAMFORMATTYPE {\n    OMX_AUDIO_MP3StreamFormatMP1Layer3 = 0, /**< MP3 Audio MPEG 1 Layer 3 Stream format */\n    OMX_AUDIO_MP3StreamFormatMP2Layer3,     /**< MP3 Audio MPEG 2 Layer 3 Stream format */\n    OMX_AUDIO_MP3StreamFormatMP2_5Layer3,   /**< MP3 Audio MPEG2.5 Layer 3 Stream format */\n    OMX_AUDIO_MP3StreamFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_MP3StreamFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_MP3StreamFormatMax = 0x7FFFFFFF\n} OMX_AUDIO_MP3STREAMFORMATTYPE;\n\n/** MP3 params */\ntypedef struct OMX_AUDIO_PARAM_MP3TYPE {\n    OMX_U32 nSize;                 /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;      /**< OMX specification version information */\n    OMX_U32 nPortIndex;            /**< port that this structure applies to */\n    OMX_U32 nChannels;             /**< Number of channels */\n    OMX_U32 nBitRate;              /**< Bit rate of the input data.  Use 0 for variable\n                                        rate or unknown bit rates */\n    OMX_U32 nSampleRate;           /**< Sampling rate of the source data.  Use 0 for\n                                        variable or unknown sampling rate. */\n    OMX_U32 nAudioBandWidth;       /**< Audio band width (in Hz) to which an encoder should\n                                        limit the audio signal. Use 0 to let encoder decide */\n    OMX_AUDIO_CHANNELMODETYPE eChannelMode;   /**< Channel mode enumeration */\n    OMX_AUDIO_MP3STREAMFORMATTYPE eFormat;  /**< MP3 stream format */\n} OMX_AUDIO_PARAM_MP3TYPE;\n\n\ntypedef enum OMX_AUDIO_AACSTREAMFORMATTYPE {\n    OMX_AUDIO_AACStreamFormatMP2ADTS = 0, /**< AAC Audio Data Transport Stream 2 format */\n    OMX_AUDIO_AACStreamFormatMP4ADTS,     /**< AAC Audio Data Transport Stream 4 format */\n    OMX_AUDIO_AACStreamFormatMP4LOAS,     /**< AAC Low Overhead Audio Stream format */\n    OMX_AUDIO_AACStreamFormatMP4LATM,     /**< AAC Low overhead Audio Transport Multiplex */\n    OMX_AUDIO_AACStreamFormatADIF,        /**< AAC Audio Data Interchange Format */\n    OMX_AUDIO_AACStreamFormatMP4FF,       /**< AAC inside MPEG-4/ISO File Format */\n    OMX_AUDIO_AACStreamFormatRAW,         /**< AAC Raw Format */\n    OMX_AUDIO_AACStreamFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_AACStreamFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_AACStreamFormatMax = 0x7FFFFFFF\n} OMX_AUDIO_AACSTREAMFORMATTYPE;\n\n\n/** AAC mode type.  Note that the term profile is used with the MPEG-2\n * standard and the term object type and profile is used with MPEG-4 */\ntypedef enum OMX_AUDIO_AACPROFILETYPE{\n  OMX_AUDIO_AACObjectNull = 0,      /**< Null, not used */\n  OMX_AUDIO_AACObjectMain = 1,      /**< AAC Main object */\n  OMX_AUDIO_AACObjectLC,            /**< AAC Low Complexity object (AAC profile) */\n  OMX_AUDIO_AACObjectSSR,           /**< AAC Scalable Sample Rate object */\n  OMX_AUDIO_AACObjectLTP,           /**< AAC Long Term Prediction object */\n  OMX_AUDIO_AACObjectHE,            /**< AAC High Efficiency (object type SBR, HE-AAC profile) */\n  OMX_AUDIO_AACObjectScalable,      /**< AAC Scalable object */\n  OMX_AUDIO_AACObjectERLC = 17,     /**< ER AAC Low Complexity object (Error Resilient AAC-LC) */\n  OMX_AUDIO_AACObjectLD = 23,       /**< AAC Low Delay object (Error Resilient) */\n  OMX_AUDIO_AACObjectHE_PS = 29,    /**< AAC High Efficiency with Parametric Stereo coding (HE-AAC v2, object type PS) */\n  OMX_AUDIO_AACObjectKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n  OMX_AUDIO_AACObjectVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n  OMX_AUDIO_AACObjectMax = 0x7FFFFFFF\n} OMX_AUDIO_AACPROFILETYPE;\n\n\n/** AAC tool usage (for nAACtools in OMX_AUDIO_PARAM_AACPROFILETYPE).\n * Required for encoder configuration and optional as decoder info output.\n * For MP3, OMX_AUDIO_CHANNELMODETYPE is sufficient. */\n#define OMX_AUDIO_AACToolNone 0x00000000 /**< no AAC tools allowed (encoder config) or active (decoder info output) */\n#define OMX_AUDIO_AACToolMS   0x00000001 /**< MS: Mid/side joint coding tool allowed or active */\n#define OMX_AUDIO_AACToolIS   0x00000002 /**< IS: Intensity stereo tool allowed or active */\n#define OMX_AUDIO_AACToolTNS  0x00000004 /**< TNS: Temporal Noise Shaping tool allowed or active */\n#define OMX_AUDIO_AACToolPNS  0x00000008 /**< PNS: MPEG-4 Perceptual Noise substitution tool allowed or active */\n#define OMX_AUDIO_AACToolLTP  0x00000010 /**< LTP: MPEG-4 Long Term Prediction tool allowed or active */\n#define OMX_AUDIO_AACToolAll  0x7FFFFFFF /**< all AAC tools allowed or active (*/\n\n/** MPEG-4 AAC error resilience (ER) tool usage (for nAACERtools in OMX_AUDIO_PARAM_AACPROFILETYPE).\n * Required for ER encoder configuration and optional as decoder info output */\n#define OMX_AUDIO_AACERNone  0x00000000  /**< no AAC ER tools allowed/used */\n#define OMX_AUDIO_AACERVCB11 0x00000001  /**< VCB11: Virtual Code Books for AAC section data */\n#define OMX_AUDIO_AACERRVLC  0x00000002  /**< RVLC: Reversible Variable Length Coding */\n#define OMX_AUDIO_AACERHCR   0x00000004  /**< HCR: Huffman Codeword Reordering */\n#define OMX_AUDIO_AACERAll   0x7FFFFFFF  /**< all AAC ER tools allowed/used */\n\n\n/** AAC params */\ntypedef struct OMX_AUDIO_PARAM_AACPROFILETYPE {\n    OMX_U32 nSize;                 /**< Size of this structure, in Bytes */\n    OMX_VERSIONTYPE nVersion;      /**< OMX specification version information */\n    OMX_U32 nPortIndex;            /**< Port that this structure applies to */\n    OMX_U32 nChannels;             /**< Number of channels */\n    OMX_U32 nSampleRate;           /**< Sampling rate of the source data.  Use 0 for\n                                        variable or unknown sampling rate. */\n    OMX_U32 nBitRate;              /**< Bit rate of the input data.  Use 0 for variable\n                                        rate or unknown bit rates */\n    OMX_U32 nAudioBandWidth;       /**< Audio band width (in Hz) to which an encoder should\n                                        limit the audio signal. Use 0 to let encoder decide */\n    OMX_U32 nFrameLength;          /**< Frame length (in audio samples per channel) of the codec.\n                                        Can be 1024 or 960 (AAC-LC), 2048 (HE-AAC), 480 or 512 (AAC-LD).\n                                        Use 0 to let encoder decide */\n    OMX_U32 nAACtools;             /**< AAC tool usage */\n    OMX_U32 nAACERtools;           /**< MPEG-4 AAC error resilience tool usage */\n    OMX_AUDIO_AACPROFILETYPE eAACProfile;   /**< AAC profile enumeration */\n    OMX_AUDIO_AACSTREAMFORMATTYPE eAACStreamFormat; /**< AAC stream format enumeration */\n    OMX_AUDIO_CHANNELMODETYPE eChannelMode;   /**< Channel mode enumeration */\n} OMX_AUDIO_PARAM_AACPROFILETYPE;\n\n\n/** VORBIS params */\ntypedef struct OMX_AUDIO_PARAM_VORBISTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_U32 nChannels;        /**< Number of channels */\n    OMX_U32 nBitRate;         /**< Bit rate of the encoded data data.  Use 0 for variable\n                                   rate or unknown bit rates. Encoding is set to the\n                                   bitrate closest to specified  value (in bps) */\n    OMX_U32 nMinBitRate;      /**< Sets minimum bitrate (in bps). */\n    OMX_U32 nMaxBitRate;      /**< Sets maximum bitrate (in bps). */\n\n    OMX_U32 nSampleRate;      /**< Sampling rate of the source data.  Use 0 for\n                                   variable or unknown sampling rate. */\n    OMX_U32 nAudioBandWidth;  /**< Audio band width (in Hz) to which an encoder should\n                                   limit the audio signal. Use 0 to let encoder decide */\n    OMX_S32 nQuality;\t\t  /**< Sets encoding quality to n, between -1 (low) and 10 (high).\n                                   In the default mode of operation, teh quality level is 3.\n                                   Normal quality range is 0 - 10. */\n    OMX_BOOL bManaged;\t\t  /**< Set  bitrate  management  mode. This turns off the\n                                   normal VBR encoding, but allows hard or soft bitrate\n                                   constraints to be enforced by the encoder. This mode can\n                                   be slower, and may also be lower quality. It is\n                                   primarily useful for streaming. */\n    OMX_BOOL bDownmix;\t\t  /**< Downmix input from stereo to mono (has no effect on \n                                   non-stereo streams). Useful for lower-bitrate encoding. */     \n} OMX_AUDIO_PARAM_VORBISTYPE;\n\n\n/** WMA Version */\ntypedef enum OMX_AUDIO_WMAFORMATTYPE {\n  OMX_AUDIO_WMAFormatUnused = 0, /**< format unused or unknown */\n  OMX_AUDIO_WMAFormat7,          /**< Windows Media Audio format 7 */\n  OMX_AUDIO_WMAFormat8,          /**< Windows Media Audio format 8 */\n  OMX_AUDIO_WMAFormat9,          /**< Windows Media Audio format 9 */\n  OMX_AUDIO_WMAFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n  OMX_AUDIO_WMAFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n  OMX_AUDIO_WMAFormatMax = 0x7FFFFFFF\n} OMX_AUDIO_WMAFORMATTYPE;\n\n\n/** WMA Profile */\ntypedef enum OMX_AUDIO_WMAPROFILETYPE {\n  OMX_AUDIO_WMAProfileUnused = 0,  /**< profile unused or unknown */\n  OMX_AUDIO_WMAProfileL1,          /**< Windows Media audio version 9 profile L1 */\n  OMX_AUDIO_WMAProfileL2,          /**< Windows Media audio version 9 profile L2 */\n  OMX_AUDIO_WMAProfileL3,          /**< Windows Media audio version 9 profile L3 */\n  OMX_AUDIO_WMAProfileKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n  OMX_AUDIO_WMAProfileVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n  OMX_AUDIO_WMAProfileMax = 0x7FFFFFFF\n} OMX_AUDIO_WMAPROFILETYPE;\n\n\n/** WMA params */\ntypedef struct OMX_AUDIO_PARAM_WMATYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_U16 nChannels;        /**< Number of channels */\n    OMX_U32 nBitRate;         /**< Bit rate of the input data.  Use 0 for variable\n                                   rate or unknown bit rates */\n    OMX_AUDIO_WMAFORMATTYPE eFormat; /**< Version of WMA stream / data */\n\tOMX_AUDIO_WMAPROFILETYPE eProfile;  /**< Profile of WMA stream / data */\n    OMX_U32 nSamplingRate;    /**< Sampling rate of the source data */\n    OMX_U16 nBlockAlign;      /**< is the block alignment, or block size, in bytes of the audio codec */\n    OMX_U16 nEncodeOptions;   /**< WMA Type-specific data */\n    OMX_U32 nSuperBlockAlign; /**< WMA Type-specific data */\n} OMX_AUDIO_PARAM_WMATYPE;\n\n/** \n * RealAudio format\n */\ntypedef enum OMX_AUDIO_RAFORMATTYPE {\n    OMX_AUDIO_RAFormatUnused = 0, /**< Format unused or unknown */\n    OMX_AUDIO_RA8,                /**< RealAudio 8 codec */\n    OMX_AUDIO_RA9,                /**< RealAudio 9 codec */\n    OMX_AUDIO_RA10_AAC,           /**< MPEG-4 AAC codec for bitrates of more than 128kbps */\n    OMX_AUDIO_RA10_CODEC,         /**< RealAudio codec for bitrates less than 128 kbps */\n    OMX_AUDIO_RA10_LOSSLESS,      /**< RealAudio Lossless */\n    OMX_AUDIO_RA10_MULTICHANNEL,  /**< RealAudio Multichannel */\n    OMX_AUDIO_RA10_VOICE,         /**< RealAudio Voice for bitrates below 15 kbps */\n    OMX_AUDIO_RAFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_RAFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_RAFormatMax = 0x7FFFFFFF\n} OMX_AUDIO_RAFORMATTYPE;\n\n/** RA (Real Audio) params */ \ntypedef struct OMX_AUDIO_PARAM_RATYPE { \n    OMX_U32 nSize;              /**< Size of this structure, in Bytes */ \n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */ \n    OMX_U32 nPortIndex;         /**< Port that this structure applies to */ \n    OMX_U32 nChannels;          /**< Number of channels */ \n    OMX_U32 nSamplingRate;      /**< is the sampling rate of the source data */ \n    OMX_U32 nBitsPerFrame;      /**< is the value for bits per frame  */ \n    OMX_U32 nSamplePerFrame;    /**< is the value for samples per frame */ \n    OMX_U32 nCouplingQuantBits; /**< is the number of coupling quantization bits in the stream */ \n    OMX_U32 nCouplingStartRegion;   /**< is the coupling start region in the stream  */ \n    OMX_U32 nNumRegions;        /**< is the number of regions value */ \n    OMX_AUDIO_RAFORMATTYPE eFormat; /**< is the RealAudio audio format */\n} OMX_AUDIO_PARAM_RATYPE; \n\n\n/** SBC Allocation Method Type */\ntypedef enum OMX_AUDIO_SBCALLOCMETHODTYPE {\n  OMX_AUDIO_SBCAllocMethodLoudness, /**< Loudness allocation method */\n  OMX_AUDIO_SBCAllocMethodSNR,      /**< SNR allocation method */\n  OMX_AUDIO_SBCAllocMethodKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n  OMX_AUDIO_SBCAllocMethodVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n  OMX_AUDIO_SBCAllocMethodMax = 0x7FFFFFFF\n} OMX_AUDIO_SBCALLOCMETHODTYPE;\n\n\n/** SBC params */\ntypedef struct OMX_AUDIO_PARAM_SBCTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_U32 nChannels;         /**< Number of channels */\n    OMX_U32 nBitRate;          /**< Bit rate of the input data.  Use 0 for variable\n                                    rate or unknown bit rates */\n    OMX_U32 nSampleRate;       /**< Sampling rate of the source data.  Use 0 for\n                                    variable or unknown sampling rate. */\n    OMX_U32 nBlocks;           /**< Number of blocks */\n    OMX_U32 nSubbands;         /**< Number of subbands */\n    OMX_U32 nBitPool;          /**< Bitpool value */\n    OMX_BOOL bEnableBitrate;   /**< Use bitrate value instead of bitpool */\n    OMX_AUDIO_CHANNELMODETYPE eChannelMode; /**< Channel mode enumeration */\n    OMX_AUDIO_SBCALLOCMETHODTYPE eSBCAllocType;   /**< SBC Allocation method type */\n} OMX_AUDIO_PARAM_SBCTYPE;\n\n\n/** ADPCM stream format parameters */ \ntypedef struct OMX_AUDIO_PARAM_ADPCMTYPE { \n    OMX_U32 nSize;              /**< size of the structure in bytes */ \n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */ \n    OMX_U32 nPortIndex;         /**< port that this structure applies to */ \n    OMX_U32 nChannels;          /**< Number of channels in the data stream (not \n                                     necessarily the same as the number of channels \n                                     to be rendered. */ \n    OMX_U32 nBitsPerSample;     /**< Number of bits in each sample */ \n    OMX_U32 nSampleRate;        /**< Sampling rate of the source data.  Use 0 for \n                                    variable or unknown sampling rate. */ \n} OMX_AUDIO_PARAM_ADPCMTYPE; \n\n\n/** G723 rate */\ntypedef enum OMX_AUDIO_G723RATE {\n    OMX_AUDIO_G723ModeUnused = 0,  /**< AMRNB Mode unused / unknown */\n    OMX_AUDIO_G723ModeLow,         /**< 5300 bps */\n    OMX_AUDIO_G723ModeHigh,        /**< 6300 bps */\n    OMX_AUDIO_G723ModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_G723ModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_G723ModeMax = 0x7FFFFFFF\n} OMX_AUDIO_G723RATE;\n\n\n/** G723 - Sample rate must be 8 KHz */\ntypedef struct OMX_AUDIO_PARAM_G723TYPE { \n    OMX_U32 nSize;                /**< size of the structure in bytes */ \n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */ \n    OMX_U32 nPortIndex;           /**< port that this structure applies to */ \n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not \n                                       necessarily the same as the number of channels \n                                       to be rendered. */ \n    OMX_BOOL bDTX;                /**< Enable Discontinuous Transmisssion */ \n    OMX_AUDIO_G723RATE eBitRate;  /**< todo: Should this be moved to a config? */\n    OMX_BOOL bHiPassFilter;       /**< Enable High Pass Filter */ \n    OMX_BOOL bPostFilter;         /**< Enable Post Filter */ \n} OMX_AUDIO_PARAM_G723TYPE; \n\n\n/** ITU G726 (ADPCM) rate */\ntypedef enum OMX_AUDIO_G726MODE {\n    OMX_AUDIO_G726ModeUnused = 0,  /**< G726 Mode unused / unknown */\n    OMX_AUDIO_G726Mode16,          /**< 16 kbps */\n    OMX_AUDIO_G726Mode24,          /**< 24 kbps */\n    OMX_AUDIO_G726Mode32,          /**< 32 kbps, most common rate, also G721 */\n    OMX_AUDIO_G726Mode40,          /**< 40 kbps */\n    OMX_AUDIO_G726ModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_G726ModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_G726ModeMax = 0x7FFFFFFF\n} OMX_AUDIO_G726MODE;\n\n\n/** G.726 stream format parameters - must be at 8KHz */ \ntypedef struct OMX_AUDIO_PARAM_G726TYPE { \n    OMX_U32 nSize;              /**< size of the structure in bytes */ \n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */ \n    OMX_U32 nPortIndex;         /**< port that this structure applies to */ \n    OMX_U32 nChannels;          /**< Number of channels in the data stream (not \n                                     necessarily the same as the number of channels \n                                     to be rendered. */ \n     OMX_AUDIO_G726MODE eG726Mode;\n} OMX_AUDIO_PARAM_G726TYPE; \n\n\n/** G729 coder type */\ntypedef enum OMX_AUDIO_G729TYPE {\n    OMX_AUDIO_G729 = 0,           /**< ITU G.729  encoded data */\n    OMX_AUDIO_G729A,              /**< ITU G.729 annex A  encoded data */\n    OMX_AUDIO_G729B,              /**< ITU G.729 with annex B encoded data */\n    OMX_AUDIO_G729AB,             /**< ITU G.729 annexes A and B encoded data */\n    OMX_AUDIO_G729KhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_G729VendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_G729Max = 0x7FFFFFFF\n} OMX_AUDIO_G729TYPE;\n\n\n/** G729 stream format parameters - fixed 6KHz sample rate */\ntypedef struct OMX_AUDIO_PARAM_G729TYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_U32 nChannels;        /**< Number of channels in the data stream (not\n                                   necessarily the same as the number of channels\n                                   to be rendered. */\n    OMX_BOOL bDTX;            /**< Enable Discontinuous Transmisssion */\n    OMX_AUDIO_G729TYPE eBitType;\n} OMX_AUDIO_PARAM_G729TYPE;\n\n\n/** AMR Frame format */ \ntypedef enum OMX_AUDIO_AMRFRAMEFORMATTYPE { \n    OMX_AUDIO_AMRFrameFormatConformance = 0,  /**< Frame Format is AMR Conformance \n                                                   (Standard) Format */ \n    OMX_AUDIO_AMRFrameFormatIF1,              /**< Frame Format is AMR Interface \n                                                   Format 1 */ \n    OMX_AUDIO_AMRFrameFormatIF2,              /**< Frame Format is AMR Interface \n                                                   Format 2*/ \n    OMX_AUDIO_AMRFrameFormatFSF,              /**< Frame Format is AMR File Storage \n                                                   Format */ \n    OMX_AUDIO_AMRFrameFormatRTPPayload,       /**< Frame Format is AMR Real-Time \n                                                   Transport Protocol Payload Format */ \n    OMX_AUDIO_AMRFrameFormatITU,              /**< Frame Format is ITU Format (added at Motorola request) */ \n    OMX_AUDIO_AMRFrameFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_AMRFrameFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_AMRFrameFormatMax = 0x7FFFFFFF \n} OMX_AUDIO_AMRFRAMEFORMATTYPE; \n\n\n/** AMR band mode */\ntypedef enum OMX_AUDIO_AMRBANDMODETYPE {\n    OMX_AUDIO_AMRBandModeUnused = 0,          /**< AMRNB Mode unused / unknown */\n    OMX_AUDIO_AMRBandModeNB0,                 /**< AMRNB Mode 0 =  4750 bps */\n    OMX_AUDIO_AMRBandModeNB1,                 /**< AMRNB Mode 1 =  5150 bps */\n    OMX_AUDIO_AMRBandModeNB2,                 /**< AMRNB Mode 2 =  5900 bps */ \n    OMX_AUDIO_AMRBandModeNB3,                 /**< AMRNB Mode 3 =  6700 bps */\n    OMX_AUDIO_AMRBandModeNB4,                 /**< AMRNB Mode 4 =  7400 bps */\n    OMX_AUDIO_AMRBandModeNB5,                 /**< AMRNB Mode 5 =  7950 bps */\n    OMX_AUDIO_AMRBandModeNB6,                 /**< AMRNB Mode 6 = 10200 bps */\n    OMX_AUDIO_AMRBandModeNB7,                 /**< AMRNB Mode 7 = 12200 bps */\n    OMX_AUDIO_AMRBandModeWB0,                 /**< AMRWB Mode 0 =  6600 bps */\n    OMX_AUDIO_AMRBandModeWB1,                 /**< AMRWB Mode 1 =  8850 bps */\n    OMX_AUDIO_AMRBandModeWB2,                 /**< AMRWB Mode 2 = 12650 bps */ \n    OMX_AUDIO_AMRBandModeWB3,                 /**< AMRWB Mode 3 = 14250 bps */ \n    OMX_AUDIO_AMRBandModeWB4,                 /**< AMRWB Mode 4 = 15850 bps */\n    OMX_AUDIO_AMRBandModeWB5,                 /**< AMRWB Mode 5 = 18250 bps */\n    OMX_AUDIO_AMRBandModeWB6,                 /**< AMRWB Mode 6 = 19850 bps */\n    OMX_AUDIO_AMRBandModeWB7,                 /**< AMRWB Mode 7 = 23050 bps */\n    OMX_AUDIO_AMRBandModeWB8,                 /**< AMRWB Mode 8 = 23850 bps */      \n    OMX_AUDIO_AMRBandModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_AMRBandModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_AMRBandModeMax = 0x7FFFFFFF\n} OMX_AUDIO_AMRBANDMODETYPE;\n     \n\n/** AMR Discontinuous Transmission mode */ \ntypedef enum OMX_AUDIO_AMRDTXMODETYPE { \n    OMX_AUDIO_AMRDTXModeOff = 0,        /**< AMR Discontinuous Transmission Mode is disabled */ \n    OMX_AUDIO_AMRDTXModeOnVAD1,         /**< AMR Discontinuous Transmission Mode using \n                                             Voice Activity Detector 1 (VAD1) is enabled */ \n    OMX_AUDIO_AMRDTXModeOnVAD2,         /**< AMR Discontinuous Transmission Mode using \n                                             Voice Activity Detector 2 (VAD2) is enabled */       \n    OMX_AUDIO_AMRDTXModeOnAuto,         /**< The codec will automatically select between \n                                             Off, VAD1 or VAD2 modes */ \n\n    OMX_AUDIO_AMRDTXasEFR,             /**< DTX as EFR instead of AMR standard (3GPP 26.101, frame type =8,9,10) */\n\n    OMX_AUDIO_AMRDTXModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_AMRDTXModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_AMRDTXModeMax = 0x7FFFFFFF \n} OMX_AUDIO_AMRDTXMODETYPE; \n \n\n/** AMR params */\ntypedef struct OMX_AUDIO_PARAM_AMRTYPE {\n    OMX_U32 nSize;                          /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;               /**< OMX specification version information */\n    OMX_U32 nPortIndex;                     /**< port that this structure applies to */\n    OMX_U32 nChannels;                      /**< Number of channels */\n    OMX_U32 nBitRate;                       /**< Bit rate read only field */\n    OMX_AUDIO_AMRBANDMODETYPE eAMRBandMode; /**< AMR Band Mode enumeration */ \n    OMX_AUDIO_AMRDTXMODETYPE  eAMRDTXMode;  /**< AMR DTX Mode enumeration */\n    OMX_AUDIO_AMRFRAMEFORMATTYPE eAMRFrameFormat; /**< AMR frame format enumeration */\n} OMX_AUDIO_PARAM_AMRTYPE;\n\n\n/** GSM_FR (ETSI 06.10, 3GPP 46.010) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_GSMFRTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_BOOL bDTX;            /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;   /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_GSMFRTYPE;\n\n\n/** GSM-HR (ETSI 06.20, 3GPP 46.020) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_GSMHRTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_BOOL bDTX;            /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;   /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_GSMHRTYPE;\n\n\n/** GSM-EFR (ETSI 06.60, 3GPP 46.060) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_GSMEFRTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_BOOL bDTX;            /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;   /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_GSMEFRTYPE;\n\n\n/** TDMA FR (TIA/EIA-136-420, VSELP 7.95kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_TDMAFRTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_BOOL bDTX;                /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;       /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_TDMAFRTYPE;\n\n\n/** TDMA EFR (TIA/EIA-136-410, ACELP 7.4kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_TDMAEFRTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_BOOL bDTX;                /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;       /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_TDMAEFRTYPE;\n\n\n/** PDC FR ( RCR-27, VSELP 6.7kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_PDCFRTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_BOOL bDTX;                /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;       /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_PDCFRTYPE;\n\n\n/** PDC EFR ( RCR-27, ACELP 6.7kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_PDCEFRTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_BOOL bDTX;                /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;       /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_PDCEFRTYPE;\n\n/** PDC HR ( RCR-27, PSI-CELP 3.45kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_PDCHRTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_BOOL bDTX;                /**< Enable Discontinuous Transmisssion */\n    OMX_BOOL bHiPassFilter;       /**< Enable High Pass Filter */\n} OMX_AUDIO_PARAM_PDCHRTYPE;\n\n\n/** CDMA Rate types */\ntypedef enum OMX_AUDIO_CDMARATETYPE {\n    OMX_AUDIO_CDMARateBlank = 0,          /**< CDMA encoded frame is blank */\n    OMX_AUDIO_CDMARateFull,               /**< CDMA encoded frame in full rate */\n    OMX_AUDIO_CDMARateHalf,               /**< CDMA encoded frame in half rate */\n    OMX_AUDIO_CDMARateQuarter,            /**< CDMA encoded frame in quarter rate */\n    OMX_AUDIO_CDMARateEighth,             /**< CDMA encoded frame in eighth rate (DTX)*/\n    OMX_AUDIO_CDMARateErasure,            /**< CDMA erasure frame */\n    OMX_AUDIO_CDMARateKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_CDMARateVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_CDMARateMax = 0x7FFFFFFF\n} OMX_AUDIO_CDMARATETYPE;\n\n\n/** QCELP8 (TIA/EIA-96, up to 8kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_QCELP8TYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_U32 nBitRate;             /**< Bit rate of the input data.  Use 0 for variable\n                                       rate or unknown bit rates */\n    OMX_AUDIO_CDMARATETYPE eCDMARate; /**< Frame rate */\n    OMX_U32 nMinBitRate;          /**< minmal rate for the encoder = 1,2,3,4, default = 1 */\n    OMX_U32 nMaxBitRate;          /**< maximal rate for the encoder = 1,2,3,4, default = 4 */\n} OMX_AUDIO_PARAM_QCELP8TYPE;\n\n\n/** QCELP13 ( CDMA, EIA/TIA-733, 13.3kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_QCELP13TYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_AUDIO_CDMARATETYPE eCDMARate; /**< Frame rate */\n    OMX_U32 nMinBitRate;          /**< minmal rate for the encoder = 1,2,3,4, default = 1 */\n    OMX_U32 nMaxBitRate;          /**< maximal rate for the encoder = 1,2,3,4, default = 4 */\n} OMX_AUDIO_PARAM_QCELP13TYPE;\n\n\n/** EVRC ( CDMA, EIA/TIA-127, RCELP up to 8.55kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_EVRCTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_AUDIO_CDMARATETYPE eCDMARate; /**< actual Frame rate */\n    OMX_BOOL bRATE_REDUCon;       /**< RATE_REDUCtion is requested for this frame */\n    OMX_U32 nMinBitRate;          /**< minmal rate for the encoder = 1,2,3,4, default = 1 */\n    OMX_U32 nMaxBitRate;          /**< maximal rate for the encoder = 1,2,3,4, default = 4 */\n    OMX_BOOL bHiPassFilter;       /**< Enable encoder's High Pass Filter */\n    OMX_BOOL bNoiseSuppressor;    /**< Enable encoder's noise suppressor pre-processing */\n    OMX_BOOL bPostFilter;         /**< Enable decoder's post Filter */\n} OMX_AUDIO_PARAM_EVRCTYPE;\n\n\n/** SMV ( up to 8.55kbps coder) stream format parameters */\ntypedef struct OMX_AUDIO_PARAM_SMVTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_U32 nChannels;            /**< Number of channels in the data stream (not\n                                       necessarily the same as the number of channels\n                                       to be rendered. */\n    OMX_AUDIO_CDMARATETYPE eCDMARate; /**< Frame rate */\n    OMX_BOOL bRATE_REDUCon;           /**< RATE_REDUCtion is requested for this frame */\n    OMX_U32 nMinBitRate;          /**< minmal rate for the encoder = 1,2,3,4, default = 1 ??*/\n    OMX_U32 nMaxBitRate;          /**< maximal rate for the encoder = 1,2,3,4, default = 4 ??*/\n    OMX_BOOL bHiPassFilter;       /**< Enable encoder's High Pass Filter ??*/\n    OMX_BOOL bNoiseSuppressor;    /**< Enable encoder's noise suppressor pre-processing */\n    OMX_BOOL bPostFilter;         /**< Enable decoder's post Filter ??*/\n} OMX_AUDIO_PARAM_SMVTYPE;\n\n\n/** MIDI Format \n * @ingroup midi\n */\ntypedef enum OMX_AUDIO_MIDIFORMATTYPE\n{\n    OMX_AUDIO_MIDIFormatUnknown = 0, /**< MIDI Format unknown or don't care */\n    OMX_AUDIO_MIDIFormatSMF0,        /**< Standard MIDI File Type 0 */\n    OMX_AUDIO_MIDIFormatSMF1,        /**< Standard MIDI File Type 1 */\n    OMX_AUDIO_MIDIFormatSMF2,        /**< Standard MIDI File Type 2 */\n    OMX_AUDIO_MIDIFormatSPMIDI,      /**< SP-MIDI */\n    OMX_AUDIO_MIDIFormatXMF0,        /**< eXtensible Music Format type 0 */\n    OMX_AUDIO_MIDIFormatXMF1,        /**< eXtensible Music Format type 1 */\n    OMX_AUDIO_MIDIFormatMobileXMF,   /**< Mobile XMF (eXtensible Music Format type 2) */\n    OMX_AUDIO_MIDIFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_MIDIFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_MIDIFormatMax = 0x7FFFFFFF\n} OMX_AUDIO_MIDIFORMATTYPE;\n\n\n/** MIDI params \n * @ingroup midi\n */\ntypedef struct OMX_AUDIO_PARAM_MIDITYPE {\n    OMX_U32 nSize;                 /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;      /**< OMX specification version information */\n    OMX_U32 nPortIndex;            /**< port that this structure applies to */\n    OMX_U32 nFileSize;             /**< size of the MIDI file in bytes, where the entire \n                                        MIDI file passed in, otherwise if 0x0, the MIDI data \n                                        is merged and streamed (instead of passed as an \n                                        entire MIDI file) */\n    OMX_BU32 sMaxPolyphony;        /**< Specifies the maximum simultaneous polyphonic \n                                        voices. A value of zero indicates that the default \n                                        polyphony of the device is used  */                                    \n    OMX_BOOL bLoadDefaultSound;    /**< Whether to load default sound \n                                        bank at initialization */\n    OMX_AUDIO_MIDIFORMATTYPE eMidiFormat; /**< Version of the MIDI file */                                                                           \n} OMX_AUDIO_PARAM_MIDITYPE;\n\n\n/** Type of the MIDI sound bank \n * @ingroup midi\n */\ntypedef enum OMX_AUDIO_MIDISOUNDBANKTYPE {\n    OMX_AUDIO_MIDISoundBankUnused = 0,           /**< unused/unknown soundbank type */\n    OMX_AUDIO_MIDISoundBankDLS1,                 /**< DLS version 1 */\n    OMX_AUDIO_MIDISoundBankDLS2,                 /**< DLS version 2 */\n    OMX_AUDIO_MIDISoundBankMobileDLSBase,        /**< Mobile DLS, using the base functionality */\n    OMX_AUDIO_MIDISoundBankMobileDLSPlusOptions, /**< Mobile DLS, using the specification-defined optional feature set */\n    OMX_AUDIO_MIDISoundBankKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_MIDISoundBankVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_MIDISoundBankMax = 0x7FFFFFFF\n} OMX_AUDIO_MIDISOUNDBANKTYPE;\n\n\n/** Bank Layout describes how bank MSB & LSB are used in the DLS instrument definitions sound bank \n * @ingroup midi\n */\ntypedef enum OMX_AUDIO_MIDISOUNDBANKLAYOUTTYPE {\n   OMX_AUDIO_MIDISoundBankLayoutUnused = 0,   /**< unused/unknown soundbank type */\n   OMX_AUDIO_MIDISoundBankLayoutGM,           /**< GS layout (based on bank MSB 0x00) */\n   OMX_AUDIO_MIDISoundBankLayoutGM2,          /**< General MIDI 2 layout (using MSB 0x78/0x79, LSB 0x00) */\n   OMX_AUDIO_MIDISoundBankLayoutUser,         /**< Does not conform to any bank numbering standards */\n   OMX_AUDIO_MIDISoundBankLayoutKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n   OMX_AUDIO_MIDISoundBankLayoutVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n   OMX_AUDIO_MIDISoundBankLayoutMax = 0x7FFFFFFF\n} OMX_AUDIO_MIDISOUNDBANKLAYOUTTYPE;\n\n\n/** MIDI params to load/unload user soundbank \n * @ingroup midi\n */\ntypedef struct OMX_AUDIO_PARAM_MIDILOADUSERSOUNDTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< port that this structure applies to */\n    OMX_U32 nDLSIndex;        /**< DLS file index to be loaded */\n    OMX_U32 nDLSSize;         /**< Size in bytes */\n    OMX_PTR pDLSData;         /**< Pointer to DLS file data */\n    OMX_AUDIO_MIDISOUNDBANKTYPE eMidiSoundBank;   /**< Midi sound bank type enumeration */\n    OMX_AUDIO_MIDISOUNDBANKLAYOUTTYPE eMidiSoundBankLayout; /**< Midi sound bank layout enumeration */\n} OMX_AUDIO_PARAM_MIDILOADUSERSOUNDTYPE;\n\n\n/** Structure for Live MIDI events and MIP messages. \n * (MIP = Maximum Instantaneous Polyphony; part of the SP-MIDI standard.) \n * @ingroup midi\n */\ntypedef struct OMX_AUDIO_CONFIG_MIDIIMMEDIATEEVENTTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex;       /**< Port that this structure applies to */\n    OMX_U32 nMidiEventSize;   /**< Size of immediate MIDI events or MIP message in bytes  */\n    OMX_U8 nMidiEvents[1];    /**< MIDI event array to be rendered immediately, or an\n                                   array for the MIP message buffer, where the size is \n                                   indicated by nMidiEventSize */\n} OMX_AUDIO_CONFIG_MIDIIMMEDIATEEVENTTYPE;\n\n\n/** MIDI sound bank/ program pair in a given channel \n * @ingroup midi\n */\ntypedef struct OMX_AUDIO_CONFIG_MIDISOUNDBANKPROGRAMTYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< Port that this structure applies to */\n    OMX_U32 nChannel;           /**< Valid channel values range from 1 to 16 */\n    OMX_U16 nIDProgram;         /**< Valid program ID range is 1 to 128 */\n    OMX_U16 nIDSoundBank;       /**< Sound bank ID */\n    OMX_U32 nUserSoundBankIndex;/**< User soundbank index, easier to access soundbanks \n                                     by index if multiple banks are present */\n} OMX_AUDIO_CONFIG_MIDISOUNDBANKPROGRAMTYPE;\n\n\n/** MIDI control \n * @ingroup midi\n */\ntypedef struct OMX_AUDIO_CONFIG_MIDICONTROLTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_BS32 sPitchTransposition; /**< Pitch transposition in semitones, stored as Q22.10 \n                                       format based on JAVA MMAPI (JSR-135) requirement */\n    OMX_BU32 sPlayBackRate;       /**< Relative playback rate, stored as Q14.17 fixed-point\n                                       number based on JSR-135 requirement */\n    OMX_BU32 sTempo ;             /**< Tempo in beats per minute (BPM), stored as Q22.10 \n                                       fixed-point number based on JSR-135 requirement */\n    OMX_U32 nMaxPolyphony;        /**< Specifies the maximum simultaneous polyphonic \n                                       voices. A value of zero indicates that the default \n                                       polyphony of the device is used  */\n    OMX_U32 nNumRepeat;           /**< Number of times to repeat playback */\n    OMX_U32 nStopTime;            /**< Time in milliseconds to indicate when playback \n                                       will stop automatically.  Set to zero if not used */\n    OMX_U16 nChannelMuteMask;     /**< 16 bit mask for channel mute status */\n    OMX_U16 nChannelSoloMask;     /**< 16 bit mask for channel solo status */\n    OMX_U32 nTrack0031MuteMask;   /**< 32 bit mask for track mute status. Note: This is for tracks 0-31 */\n    OMX_U32 nTrack3263MuteMask;   /**< 32 bit mask for track mute status. Note: This is for tracks 32-63 */\n    OMX_U32 nTrack0031SoloMask;   /**< 32 bit mask for track solo status. Note: This is for tracks 0-31 */\n    OMX_U32 nTrack3263SoloMask;   /**< 32 bit mask for track solo status. Note: This is for tracks 32-63 */\n\n} OMX_AUDIO_CONFIG_MIDICONTROLTYPE;\n\n\n/** MIDI Playback States \n * @ingroup midi\n */\ntypedef enum OMX_AUDIO_MIDIPLAYBACKSTATETYPE {\n  OMX_AUDIO_MIDIPlayBackStateUnknown = 0,      /**< Unknown state or state does not map to \n  \t\t\t\t\t\t\t\t\t\t\t\t\tother defined states */\n  OMX_AUDIO_MIDIPlayBackStateClosedEngaged,    /**< No MIDI resource is currently open. \n                                                    The MIDI engine is currently processing \n                                                    MIDI events. */\n  OMX_AUDIO_MIDIPlayBackStateParsing,          /**< A MIDI resource is open and is being \n                                                    primed. The MIDI engine is currently \n                                                    processing MIDI events. */\n  OMX_AUDIO_MIDIPlayBackStateOpenEngaged,      /**< A MIDI resource is open and primed but \n                                                    not playing. The MIDI engine is currently\n                                                    processing MIDI events. The transition to\n                                                    this state is only possible from the \n                                                    OMX_AUDIO_MIDIPlayBackStatePlaying state,\n                                                    when the 'playback head' reaches the end\n                                                    of media data or the playback stops due\n                                                    to stop time set.*/\n  OMX_AUDIO_MIDIPlayBackStatePlaying,          /**< A MIDI resource is open and currently\n                                                    playing. The MIDI engine is currently\n                                                    processing MIDI events.*/\n  OMX_AUDIO_MIDIPlayBackStatePlayingPartially, /**< Best-effort playback due to SP-MIDI/DLS\n                                                    resource constraints */\n  OMX_AUDIO_MIDIPlayBackStatePlayingSilently,  /**< Due to system resource constraints and\n                                                    SP-MIDI content constraints, there is\n                                                    no audible MIDI content during playback\n                                                    currently. The situation may change if\n                                                    resources are freed later.*/\n  OMX_AUDIO_MIDIPlayBackStateKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n  OMX_AUDIO_MIDIPlayBackStateVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n  OMX_AUDIO_MIDIPlayBackStateMax = 0x7FFFFFFF\n} OMX_AUDIO_MIDIPLAYBACKSTATETYPE;\n\n\n/** MIDI status \n * @ingroup midi\n */\ntypedef struct OMX_AUDIO_CONFIG_MIDISTATUSTYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< port that this structure applies to */\n    OMX_U16 nNumTracks;         /**< Number of MIDI tracks in the file, read only field. \n                                     NOTE: May not return a meaningful value until the entire \n                                     file is parsed and buffered.  */\n    OMX_U32 nDuration;          /**< The length of the currently open MIDI resource \n                                     in milliseconds. NOTE: May not return a meaningful value \n                                     until the entire file is parsed and buffered.  */  \n    OMX_U32 nPosition;          /**< Current Position of the MIDI resource being played \n                                     in milliseconds */\n    OMX_BOOL bVibra;            /**< Does Vibra track exist? NOTE: May not return a meaningful \n                                     value until the entire file is parsed and buffered. */\n    OMX_U32 nNumMetaEvents;     /**< Total number of MIDI Meta Events in the currently \n                                     open MIDI resource. NOTE: May not return a meaningful value \n                                     until the entire file is parsed and buffered.  */\n    OMX_U32 nNumActiveVoices;   /**< Number of active voices in the currently playing \n                                     MIDI resource. NOTE: May not return a meaningful value until \n                                     the entire file is parsed and buffered. */\n    OMX_AUDIO_MIDIPLAYBACKSTATETYPE eMIDIPlayBackState;  /**< MIDI playback state enumeration, read only field */\n} OMX_AUDIO_CONFIG_MIDISTATUSTYPE;\n\n\n/** MIDI Meta Event structure one per Meta Event.\n *  MIDI Meta Events are like audio metadata, except that they are interspersed \n *  with the MIDI content throughout the file and are not localized in the header. \n *  As such, it is necessary to retrieve information about these Meta Events from \n *  the engine, as it encounters these Meta Events within the MIDI content. \n *  For example, SMF files can have up to 14 types of MIDI Meta Events (copyright, \n *  author, default tempo, etc.) scattered throughout the file. \n *  @ingroup midi\n */\ntypedef struct OMX_AUDIO_CONFIG_MIDIMETAEVENTTYPE{ \n    OMX_U32 nSize;            /**< size of the structure in bytes */ \n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */ \n    OMX_U32 nPortIndex;       /**< port that this structure applies to */ \n    OMX_U32 nIndex;           /**< Index of Meta Event */ \n    OMX_U8 nMetaEventType;    /**< Meta Event Type, 7bits (i.e. 0 - 127) */ \n    OMX_U32 nMetaEventSize;   /**< size of the Meta Event in bytes */ \n    OMX_U32 nTrack;           /**< track number for the meta event */\n    OMX_U32 nPosition;        /**< Position of the meta-event in milliseconds */\n} OMX_AUDIO_CONFIG_MIDIMETAEVENTTYPE; \n\n\n/** MIDI Meta Event Data structure - one per Meta Event. \n * @ingroup midi\n */ \ntypedef struct OMX_AUDIO_CONFIG_MIDIMETAEVENTDATATYPE{ \n    OMX_U32 nSize;            /**< size of the structure in bytes */ \n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */ \n    OMX_U32 nPortIndex;       /**< port that this structure applies to */ \n    OMX_U32 nIndex;           /**< Index of Meta Event */ \n    OMX_U32 nMetaEventSize;   /**< size of the Meta Event in bytes */ \n    OMX_U8 nData[1];          /**< array of one or more bytes of meta data \n                                   as indicated by the nMetaEventSize field */ \n} OMX_AUDIO_CONFIG__MIDIMETAEVENTDATATYPE; \n\n\n/** Audio Volume adjustment for a port */\ntypedef struct OMX_AUDIO_CONFIG_VOLUMETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< Port index indicating which port to \n                                     set.  Select the input port to set \n                                     just that port's volume.  Select the \n                                     output port to adjust the master \n                                     volume. */\n    OMX_BOOL bLinear;           /**< Is the volume to be set in linear (0.100) \n                                     or logarithmic scale (mB) */\n    OMX_BS32 sVolume;           /**< Volume linear setting in the 0..100 range, OR\n                                     Volume logarithmic setting for this port.  The values\n                                     for volume are in mB (millibels = 1/100 dB) relative\n                                     to a gain of 1 (e.g. the output is the same as the \n                                     input level).  Values are in mB from nMax \n                                     (maximum volume) to nMin mB (typically negative).\n                                     Since the volume is \"voltage\"\n                                     and not a \"power\", it takes a setting of\n                                     -600 mB to decrease the volume by 1/2.  If\n                                     a component cannot accurately set the \n                                     volume to the requested value, it must\n                                     set the volume to the closest value BELOW\n                                     the requested value.  When getting the\n                                     volume setting, the current actual volume\n                                     must be returned. */\n} OMX_AUDIO_CONFIG_VOLUMETYPE;\n\n\n/** Audio Volume adjustment for a channel */\ntypedef struct OMX_AUDIO_CONFIG_CHANNELVOLUMETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< Port index indicating which port to \n                                     set.  Select the input port to set \n                                     just that port's volume.  Select the \n                                     output port to adjust the master \n                                     volume. */\n    OMX_U32 nChannel;           /**< channel to select from 0 to N-1, \n                                     using OMX_ALL to apply volume settings\n                                     to all channels */\n    OMX_BOOL bLinear;           /**< Is the volume to be set in linear (0.100) or \n                                     logarithmic scale (mB) */\n    OMX_BS32 sVolume;           /**< Volume linear setting in the 0..100 range, OR\n                                     Volume logarithmic setting for this port.  \n                                     The values for volume are in mB \n                                     (millibels = 1/100 dB) relative to a gain\n                                     of 1 (e.g. the output is the same as the \n                                     input level).  Values are in mB from nMax \n                                     (maximum volume) to nMin mB (typically negative).  \n                                     Since the volume is \"voltage\"\n                                     and not a \"power\", it takes a setting of\n                                     -600 mB to decrease the volume by 1/2.  If\n                                     a component cannot accurately set the \n                                     volume to the requested value, it must\n                                     set the volume to the closest value BELOW\n                                     the requested value.  When getting the\n                                     volume setting, the current actual volume\n                                     must be returned. */\n    OMX_BOOL bIsMIDI;           /**< TRUE if nChannel refers to a MIDI channel,\n                                     FALSE otherwise */\n} OMX_AUDIO_CONFIG_CHANNELVOLUMETYPE;\n\n\n/** Audio balance setting */\ntypedef struct OMX_AUDIO_CONFIG_BALANCETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< Port index indicating which port to \n                                     set.  Select the input port to set \n                                     just that port's balance.  Select the \n                                     output port to adjust the master \n                                     balance. */\n    OMX_S32 nBalance;           /**< balance setting for this port \n                                     (-100 to 100, where -100 indicates\n                                     all left, and no right */\n} OMX_AUDIO_CONFIG_BALANCETYPE;\n\n\n/** Audio Port mute */\ntypedef struct OMX_AUDIO_CONFIG_MUTETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< Port index indicating which port to \n                                     set.  Select the input port to set \n                                     just that port's mute.  Select the \n                                     output port to adjust the master \n                                     mute. */\n    OMX_BOOL bMute;             /**< Mute setting for this port */\n} OMX_AUDIO_CONFIG_MUTETYPE;\n\n\n/** Audio Channel mute */\ntypedef struct OMX_AUDIO_CONFIG_CHANNELMUTETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< port that this structure applies to */\n    OMX_U32 nChannel;           /**< channel to select from 0 to N-1, \n                                     using OMX_ALL to apply mute settings\n                                     to all channels */\n    OMX_BOOL bMute;             /**< Mute setting for this channel */\n    OMX_BOOL bIsMIDI;           /**< TRUE if nChannel refers to a MIDI channel,\n                                     FALSE otherwise */ \n} OMX_AUDIO_CONFIG_CHANNELMUTETYPE;\n\n\n\n/** Enable / Disable for loudness control, which boosts bass and to a \n *  smaller extent high end frequencies to compensate for hearing\n *  ability at the extreme ends of the audio spectrum\n */ \ntypedef struct OMX_AUDIO_CONFIG_LOUDNESSTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bLoudness;        /**< Enable/disable for loudness */\n} OMX_AUDIO_CONFIG_LOUDNESSTYPE;\n\n\n/** Enable / Disable for bass, which controls low frequencies\n */ \ntypedef struct OMX_AUDIO_CONFIG_BASSTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bEnable;          /**< Enable/disable for bass control */\n    OMX_S32 nBass;             /**< bass setting for the port, as a \n                                    continuous value from -100 to 100  \n                                    (0 means no change in bass level)*/\n} OMX_AUDIO_CONFIG_BASSTYPE;\n\n\n/** Enable / Disable for treble, which controls high frequencies tones\n */ \ntypedef struct OMX_AUDIO_CONFIG_TREBLETYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bEnable;          /**< Enable/disable for treble control */\n    OMX_S32  nTreble;          /**< treble setting for the port, as a\n                                    continuous value from -100 to 100  \n                                    (0 means no change in treble level) */\n} OMX_AUDIO_CONFIG_TREBLETYPE;\n\n\n/** An equalizer is typically used for two reasons: to compensate for an \n *  sub-optimal frequency response of a system to make it sound more natural \n *  or to create intentionally some unnatural coloring to the sound to create\n *  an effect.\n *  @ingroup effects\n */\ntypedef struct OMX_AUDIO_CONFIG_EQUALIZERTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bEnable;          /**< Enable/disable for equalizer */\n    OMX_BU32 sBandIndex;       /**< Band number to be set.  Upper Limit is \n                                    N-1, where N is the number of bands, lower limit is 0 */\n    OMX_BU32 sCenterFreq;      /**< Center frequecies in Hz.  This is a\n                                    read only element and is used to determine \n                                    the lower, center and upper frequency of \n                                    this band.  */\n    OMX_BS32 sBandLevel;       /**< band level in millibels */\n} OMX_AUDIO_CONFIG_EQUALIZERTYPE;\n\n\n/** Stereo widening mode type \n * @ingroup effects\n */ \ntypedef enum OMX_AUDIO_STEREOWIDENINGTYPE {\n    OMX_AUDIO_StereoWideningHeadphones,    /**< Stereo widening for loudspeakers */\n    OMX_AUDIO_StereoWideningLoudspeakers,  /**< Stereo widening for closely spaced loudspeakers */\n    OMX_AUDIO_StereoWideningKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_AUDIO_StereoWideningVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_AUDIO_StereoWideningMax = 0x7FFFFFFF\n} OMX_AUDIO_STEREOWIDENINGTYPE;\n\n\n/** Control for stereo widening, which is a special 2-channel\n *  case of the audio virtualizer effect. For example, for 5.1-channel \n *  output, it translates to virtual surround sound. \n * @ingroup effects\n */ \ntypedef struct OMX_AUDIO_CONFIG_STEREOWIDENINGTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bEnable;          /**< Enable/disable for stereo widening control */\n    OMX_AUDIO_STEREOWIDENINGTYPE eWideningType; /**< Stereo widening algorithm type */\n    OMX_U32  nStereoWidening;  /**< stereo widening setting for the port,\n                                    as a continuous value from 0 to 100  */\n} OMX_AUDIO_CONFIG_STEREOWIDENINGTYPE;\n\n\n/** The chorus effect (or ``choralizer'') is any signal processor which makes\n *  one sound source (such as a voice) sound like many such sources singing \n *  (or playing) in unison. Since performance in unison is never exact, chorus \n *  effects simulate this by making independently modified copies of the input \n *  signal. Modifications may include (1) delay, (2) frequency shift, and \n *  (3) amplitude modulation.\n * @ingroup effects\n */\ntypedef struct OMX_AUDIO_CONFIG_CHORUSTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bEnable;          /**< Enable/disable for chorus */\n    OMX_BU32 sDelay;           /**< average delay in milliseconds */\n    OMX_BU32 sModulationRate;  /**< rate of modulation in millihertz */\n    OMX_U32 nModulationDepth;  /**< depth of modulation as a percentage of \n                                    delay (i.e. 0 to 100) */\n    OMX_BU32 nFeedback;        /**< Feedback from chorus output to input in percentage */\n} OMX_AUDIO_CONFIG_CHORUSTYPE;\n\n\n/** Reverberation is part of the reflected sound that follows the early \n *  reflections. In a typical room, this consists of a dense succession of \n *  echoes whose energy decays exponentially. The reverberation effect structure \n *  as defined here includes both (early) reflections as well as (late) reverberations. \n * @ingroup effects\n */\ntypedef struct OMX_AUDIO_CONFIG_REVERBERATIONTYPE {\n    OMX_U32 nSize;                /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;     /**< OMX specification version information */\n    OMX_U32 nPortIndex;           /**< port that this structure applies to */\n    OMX_BOOL bEnable;             /**< Enable/disable for reverberation control */\n    OMX_BS32 sRoomLevel;          /**< Intensity level for the whole room effect \n                                       (i.e. both early reflections and late \n                                       reverberation) in millibels */\n    OMX_BS32 sRoomHighFreqLevel;  /**< Attenuation at high frequencies\n                                       relative to the intensity at low\n                                       frequencies in millibels */\n    OMX_BS32 sReflectionsLevel;   /**< Intensity level of early reflections\n                                       (relative to room value), in millibels */\n    OMX_BU32 sReflectionsDelay;   /**< Delay time of the first reflection relative \n                                       to the direct path, in milliseconds */\n    OMX_BS32 sReverbLevel;        /**< Intensity level of late reverberation\n                                       relative to room level, in millibels */\n    OMX_BU32 sReverbDelay;        /**< Time delay from the first early reflection \n                                       to the beginning of the late reverberation \n                                       section, in milliseconds */\n    OMX_BU32 sDecayTime;          /**< Late reverberation decay time at low\n                                       frequencies, in milliseconds */\n    OMX_BU32 nDecayHighFreqRatio; /**< Ratio of high frequency decay time relative \n                                       to low frequency decay time in percent  */\n    OMX_U32 nDensity;             /**< Modal density in the late reverberation decay,\n                                       in percent (i.e. 0 - 100) */\n    OMX_U32 nDiffusion;           /**< Echo density in the late reverberation decay,\n                                       in percent (i.e. 0 - 100) */\n    OMX_BU32 sReferenceHighFreq;  /**< Reference high frequency in Hertz. This is \n                                       the frequency used as the reference for all \n                                       the high-frequency settings above */\n\n} OMX_AUDIO_CONFIG_REVERBERATIONTYPE;\n\n\n/** Possible settings for the Echo Cancelation structure to use \n * @ingroup effects\n */\ntypedef enum OMX_AUDIO_ECHOCANTYPE {\n   OMX_AUDIO_EchoCanOff = 0,    /**< Echo Cancellation is disabled */\n   OMX_AUDIO_EchoCanNormal,     /**< Echo Cancellation normal operation - \n                                     echo from plastics and face */\n   OMX_AUDIO_EchoCanHFree,      /**< Echo Cancellation optimized for \n                                     Hands Free operation */\n   OMX_AUDIO_EchoCanCarKit,    /**< Echo Cancellation optimized for \n                                     Car Kit (longer echo) */\n   OMX_AUDIO_EchoCanKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n   OMX_AUDIO_EchoCanVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n   OMX_AUDIO_EchoCanMax = 0x7FFFFFFF\n} OMX_AUDIO_ECHOCANTYPE;\n\n\n/** Enable / Disable for echo cancelation, which removes undesired echo's\n *  from the audio\n * @ingroup effects\n */ \ntypedef struct OMX_AUDIO_CONFIG_ECHOCANCELATIONTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_AUDIO_ECHOCANTYPE eEchoCancelation; /**< Echo cancelation settings */\n} OMX_AUDIO_CONFIG_ECHOCANCELATIONTYPE;\n\n\n/** Enable / Disable for noise reduction, which undesired noise from\n * the audio\n * @ingroup effects\n */ \ntypedef struct OMX_AUDIO_CONFIG_NOISEREDUCTIONTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_U32 nPortIndex;        /**< port that this structure applies to */\n    OMX_BOOL bNoiseReduction;  /**< Enable/disable for noise reduction */\n} OMX_AUDIO_CONFIG_NOISEREDUCTIONTYPE;\n\n/** @} */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Component.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** OMX_Component.h - OpenMax IL version 1.1.2\n *  The OMX_Component header file contains the definitions used to define\n *  the public interface of a component.  This header file is intended to\n *  be used by both the application and the component.\n */\n\n#ifndef OMX_Component_h\n#define OMX_Component_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n\n/* Each OMX header must include all required header files to allow the\n *  header to compile without errors.  The includes below are required\n *  for this header file to compile successfully \n */\n\n#include <OMX_Audio.h>\n#include <OMX_Video.h>\n#include <OMX_Image.h>\n#include <OMX_Other.h>\n\n/** @ingroup comp */\ntypedef enum OMX_PORTDOMAINTYPE { \n    OMX_PortDomainAudio, \n    OMX_PortDomainVideo, \n    OMX_PortDomainImage, \n    OMX_PortDomainOther,\n    OMX_PortDomainKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_PortDomainVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_PortDomainMax = 0x7ffffff\n} OMX_PORTDOMAINTYPE;\n\n/** @ingroup comp */\ntypedef struct OMX_PARAM_PORTDEFINITIONTYPE {\n    OMX_U32 nSize;                 /**< Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;      /**< OMX specification version information */\n    OMX_U32 nPortIndex;            /**< Port number the structure applies to */\n    OMX_DIRTYPE eDir;              /**< Direction (input or output) of this port */\n    OMX_U32 nBufferCountActual;    /**< The actual number of buffers allocated on this port */\n    OMX_U32 nBufferCountMin;       /**< The minimum number of buffers this port requires */\n    OMX_U32 nBufferSize;           /**< Size, in bytes, for buffers to be used for this channel */\n    OMX_BOOL bEnabled;             /**< Ports default to enabled and are enabled/disabled by\n                                        OMX_CommandPortEnable/OMX_CommandPortDisable.\n                                        When disabled a port is unpopulated. A disabled port\n                                        is not populated with buffers on a transition to IDLE. */\n    OMX_BOOL bPopulated;           /**< Port is populated with all of its buffers as indicated by\n                                        nBufferCountActual. A disabled port is always unpopulated. \n                                        An enabled port is populated on a transition to OMX_StateIdle\n                                        and unpopulated on a transition to loaded. */\n    OMX_PORTDOMAINTYPE eDomain;    /**< Domain of the port. Determines the contents of metadata below. */\n    union {\n        OMX_AUDIO_PORTDEFINITIONTYPE audio;\n        OMX_VIDEO_PORTDEFINITIONTYPE video;\n        OMX_IMAGE_PORTDEFINITIONTYPE image;\n        OMX_OTHER_PORTDEFINITIONTYPE other;\n    } format;\n    OMX_BOOL bBuffersContiguous;\n    OMX_U32 nBufferAlignment;\n} OMX_PARAM_PORTDEFINITIONTYPE;\n\n/** @ingroup comp */\ntypedef struct OMX_PARAM_U32TYPE { \n    OMX_U32 nSize;                    /**< Size of this structure, in Bytes */ \n    OMX_VERSIONTYPE nVersion;         /**< OMX specification version information */ \n    OMX_U32 nPortIndex;               /**< port that this structure applies to */ \n    OMX_U32 nU32;                     /**< U32 value */\n} OMX_PARAM_U32TYPE;\n\n/** @ingroup rpm */\ntypedef enum OMX_SUSPENSIONPOLICYTYPE {\n    OMX_SuspensionDisabled, /**< No suspension; v1.0 behavior */\n    OMX_SuspensionEnabled,  /**< Suspension allowed */   \n    OMX_SuspensionPolicyKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_SuspensionPolicyStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_SuspensionPolicyMax = 0x7fffffff\n} OMX_SUSPENSIONPOLICYTYPE;\n\n/** @ingroup rpm */\ntypedef struct OMX_PARAM_SUSPENSIONPOLICYTYPE {\n    OMX_U32 nSize;                  \n    OMX_VERSIONTYPE nVersion;        \n    OMX_SUSPENSIONPOLICYTYPE ePolicy;\n} OMX_PARAM_SUSPENSIONPOLICYTYPE;\n\n/** @ingroup rpm */\ntypedef enum OMX_SUSPENSIONTYPE {\n    OMX_NotSuspended, /**< component is not suspended */\n    OMX_Suspended,    /**< component is suspended */\n    OMX_SuspensionKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_SuspensionVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_SuspendMax = 0x7FFFFFFF\n} OMX_SUSPENSIONTYPE;\n\n/** @ingroup rpm */\ntypedef struct OMX_PARAM_SUSPENSIONTYPE {\n    OMX_U32 nSize;                  \n    OMX_VERSIONTYPE nVersion;       \n    OMX_SUSPENSIONTYPE eType;             \n} OMX_PARAM_SUSPENSIONTYPE ;\n\ntypedef struct OMX_CONFIG_BOOLEANTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_BOOL bEnabled;    \n} OMX_CONFIG_BOOLEANTYPE;\n\n/* Parameter specifying the content uri to use. */\n/** @ingroup cp */\ntypedef struct OMX_PARAM_CONTENTURITYPE\n{\n    OMX_U32 nSize;                      /**< size of the structure in bytes, including\n                                             actual URI name */\n    OMX_VERSIONTYPE nVersion;           /**< OMX specification version information */\n    OMX_U8 contentURI[1];               /**< The URI name */\n} OMX_PARAM_CONTENTURITYPE;\n\n/* Parameter specifying the pipe to use. */\n/** @ingroup cp */\ntypedef struct OMX_PARAM_CONTENTPIPETYPE\n{\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_HANDLETYPE hPipe;       /**< The pipe handle*/\n} OMX_PARAM_CONTENTPIPETYPE;\n\n/** @ingroup rpm */\ntypedef struct OMX_RESOURCECONCEALMENTTYPE {\n    OMX_U32 nSize;             /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n    OMX_BOOL bResourceConcealmentForbidden; /**< disallow the use of resource concealment \n                                            methods (like degrading algorithm quality to \n                                            lower resource consumption or functional bypass) \n                                            on a component as a resolution to resource conflicts. */\n} OMX_RESOURCECONCEALMENTTYPE;\n\n\n/** @ingroup metadata */\ntypedef enum OMX_METADATACHARSETTYPE {\n    OMX_MetadataCharsetUnknown = 0,\n    OMX_MetadataCharsetASCII,\n    OMX_MetadataCharsetBinary,\n    OMX_MetadataCharsetCodePage1252,\n    OMX_MetadataCharsetUTF8,\n    OMX_MetadataCharsetJavaConformantUTF8,\n    OMX_MetadataCharsetUTF7,\n    OMX_MetadataCharsetImapUTF7,\n    OMX_MetadataCharsetUTF16LE, \n    OMX_MetadataCharsetUTF16BE,\n    OMX_MetadataCharsetGB12345,\n    OMX_MetadataCharsetHZGB2312,\n    OMX_MetadataCharsetGB2312,\n    OMX_MetadataCharsetGB18030,\n    OMX_MetadataCharsetGBK,\n    OMX_MetadataCharsetBig5,\n    OMX_MetadataCharsetISO88591,\n    OMX_MetadataCharsetISO88592,\n    OMX_MetadataCharsetISO88593,\n    OMX_MetadataCharsetISO88594,\n    OMX_MetadataCharsetISO88595,\n    OMX_MetadataCharsetISO88596,\n    OMX_MetadataCharsetISO88597,\n    OMX_MetadataCharsetISO88598,\n    OMX_MetadataCharsetISO88599,\n    OMX_MetadataCharsetISO885910,\n    OMX_MetadataCharsetISO885913,\n    OMX_MetadataCharsetISO885914,\n    OMX_MetadataCharsetISO885915,\n    OMX_MetadataCharsetShiftJIS,\n    OMX_MetadataCharsetISO2022JP,\n    OMX_MetadataCharsetISO2022JP1,\n    OMX_MetadataCharsetISOEUCJP,\n    OMX_MetadataCharsetSMS7Bit,\n    OMX_MetadataCharsetKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_MetadataCharsetVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_MetadataCharsetTypeMax= 0x7FFFFFFF\n} OMX_METADATACHARSETTYPE;\n\n/** @ingroup metadata */\ntypedef enum OMX_METADATASCOPETYPE\n{\n    OMX_MetadataScopeAllLevels,\n    OMX_MetadataScopeTopLevel,\n    OMX_MetadataScopePortLevel,\n    OMX_MetadataScopeNodeLevel,\n    OMX_MetadataScopeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_MetadataScopeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_MetadataScopeTypeMax = 0x7fffffff\n} OMX_METADATASCOPETYPE;\n\n/** @ingroup metadata */\ntypedef enum OMX_METADATASEARCHMODETYPE\n{\n    OMX_MetadataSearchValueSizeByIndex,\n    OMX_MetadataSearchItemByIndex,\n    OMX_MetadataSearchNextItemByKey,\n    OMX_MetadataSearchKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_MetadataSearchVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_MetadataSearchTypeMax = 0x7fffffff\n} OMX_METADATASEARCHMODETYPE;\n/** @ingroup metadata */\ntypedef struct OMX_CONFIG_METADATAITEMCOUNTTYPE\n{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_METADATASCOPETYPE eScopeMode;\n    OMX_U32 nScopeSpecifier;\n    OMX_U32 nMetadataItemCount;\n} OMX_CONFIG_METADATAITEMCOUNTTYPE;\n\n/** @ingroup metadata */\ntypedef struct OMX_CONFIG_METADATAITEMTYPE\n{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_METADATASCOPETYPE eScopeMode;\n    OMX_U32 nScopeSpecifier;\n    OMX_U32 nMetadataItemIndex;  \n    OMX_METADATASEARCHMODETYPE eSearchMode;\n    OMX_METADATACHARSETTYPE eKeyCharset;\n    OMX_U8 nKeySizeUsed;\n    OMX_U8 nKey[128];\n    OMX_METADATACHARSETTYPE eValueCharset;\n    OMX_STRING sLanguageCountry;\n    OMX_U32 nValueMaxSize;\n    OMX_U32 nValueSizeUsed;\n    OMX_U8 nValue[1];\n} OMX_CONFIG_METADATAITEMTYPE;\n\n/* @ingroup metadata */\ntypedef struct OMX_CONFIG_CONTAINERNODECOUNTTYPE\n{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_BOOL bAllKeys;\n    OMX_U32 nParentNodeID;\n    OMX_U32 nNumNodes;\n} OMX_CONFIG_CONTAINERNODECOUNTTYPE;\n\n/** @ingroup metadata */\ntypedef struct OMX_CONFIG_CONTAINERNODEIDTYPE\n{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_BOOL bAllKeys;\n    OMX_U32 nParentNodeID;\n    OMX_U32 nNodeIndex; \n    OMX_U32 nNodeID; \n    OMX_STRING cNodeName;\n    OMX_BOOL bIsLeafType;\n} OMX_CONFIG_CONTAINERNODEIDTYPE;\n\n/** @ingroup metadata */\ntypedef struct OMX_PARAM_METADATAFILTERTYPE \n{ \n    OMX_U32 nSize; \n    OMX_VERSIONTYPE nVersion; \n    OMX_BOOL bAllKeys;\t/* if true then this structure refers to all keys and \n                         * the three key fields below are ignored */\n    OMX_METADATACHARSETTYPE eKeyCharset;\n    OMX_U32 nKeySizeUsed; \n    OMX_U8   nKey [128]; \n    OMX_U32 nLanguageCountrySizeUsed;\n    OMX_U8 nLanguageCountry[128];\n    OMX_BOOL bEnabled;\t/* if true then key is part of filter (e.g. \n                         * retained for query later). If false then\n                         * key is not part of filter */\n} OMX_PARAM_METADATAFILTERTYPE; \n\n/** The OMX_HANDLETYPE structure defines the component handle.  The component \n *  handle is used to access all of the component's public methods and also\n *  contains pointers to the component's private data area.  The component\n *  handle is initialized by the OMX core (with help from the component)\n *  during the process of loading the component.  After the component is\n *  successfully loaded, the application can safely access any of the\n *  component's public functions (although some may return an error because\n *  the state is inappropriate for the access).\n * \n *  @ingroup comp\n */\ntypedef struct OMX_COMPONENTTYPE\n{\n    /** The size of this structure, in bytes.  It is the responsibility\n        of the allocator of this structure to fill in this value.  Since\n        this structure is allocated by the GetHandle function, this\n        function will fill in this value. */\n    OMX_U32 nSize;\n\n    /** nVersion is the version of the OMX specification that the structure \n        is built against.  It is the responsibility of the creator of this \n        structure to initialize this value and every user of this structure \n        should verify that it knows how to use the exact version of \n        this structure found herein. */\n    OMX_VERSIONTYPE nVersion;\n\n    /** pComponentPrivate is a pointer to the component private data area.  \n        This member is allocated and initialized by the component when the \n        component is first loaded.  The application should not access this \n        data area. */\n    OMX_PTR pComponentPrivate;\n\n    /** pApplicationPrivate is a pointer that is a parameter to the \n        OMX_GetHandle method, and contains an application private value \n        provided by the IL client.  This application private data is \n        returned to the IL Client by OMX in all callbacks */\n    OMX_PTR pApplicationPrivate;\n\n    /** refer to OMX_GetComponentVersion in OMX_core.h or the OMX IL \n        specification for details on the GetComponentVersion method.\n     */\n    OMX_ERRORTYPE (*GetComponentVersion)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_OUT OMX_STRING pComponentName,\n            OMX_OUT OMX_VERSIONTYPE* pComponentVersion,\n            OMX_OUT OMX_VERSIONTYPE* pSpecVersion,\n            OMX_OUT OMX_UUIDTYPE* pComponentUUID);\n\n    /** refer to OMX_SendCommand in OMX_core.h or the OMX IL \n        specification for details on the SendCommand method.\n     */\n    OMX_ERRORTYPE (*SendCommand)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_COMMANDTYPE Cmd,\n            OMX_IN  OMX_U32 nParam1,\n            OMX_IN  OMX_PTR pCmdData);\n\n    /** refer to OMX_GetParameter in OMX_core.h or the OMX IL \n        specification for details on the GetParameter method.\n     */\n    OMX_ERRORTYPE (*GetParameter)(\n            OMX_IN  OMX_HANDLETYPE hComponent, \n            OMX_IN  OMX_INDEXTYPE nParamIndex,  \n            OMX_INOUT OMX_PTR pComponentParameterStructure);\n\n\n    /** refer to OMX_SetParameter in OMX_core.h or the OMX IL \n        specification for details on the SetParameter method.\n     */\n    OMX_ERRORTYPE (*SetParameter)(\n            OMX_IN  OMX_HANDLETYPE hComponent, \n            OMX_IN  OMX_INDEXTYPE nIndex,\n            OMX_IN  OMX_PTR pComponentParameterStructure);\n\n\n    /** refer to OMX_GetConfig in OMX_core.h or the OMX IL \n        specification for details on the GetConfig method.\n     */\n    OMX_ERRORTYPE (*GetConfig)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_INDEXTYPE nIndex, \n            OMX_INOUT OMX_PTR pComponentConfigStructure);\n\n\n    /** refer to OMX_SetConfig in OMX_core.h or the OMX IL \n        specification for details on the SetConfig method.\n     */\n    OMX_ERRORTYPE (*SetConfig)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_INDEXTYPE nIndex, \n            OMX_IN  OMX_PTR pComponentConfigStructure);\n\n\n    /** refer to OMX_GetExtensionIndex in OMX_core.h or the OMX IL \n        specification for details on the GetExtensionIndex method.\n     */\n    OMX_ERRORTYPE (*GetExtensionIndex)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_STRING cParameterName,\n            OMX_OUT OMX_INDEXTYPE* pIndexType);\n\n\n    /** refer to OMX_GetState in OMX_core.h or the OMX IL \n        specification for details on the GetState method.\n     */\n    OMX_ERRORTYPE (*GetState)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_OUT OMX_STATETYPE* pState);\n\n    \n    /** The ComponentTunnelRequest method will interact with another OMX\n        component to determine if tunneling is possible and to setup the\n        tunneling.  The return codes for this method can be used to \n        determine if tunneling is not possible, or if tunneling is not\n        supported.  \n        \n        Base profile components (i.e. non-interop) do not support this\n        method and should return OMX_ErrorNotImplemented \n\n        The interop profile component MUST support tunneling to another \n        interop profile component with a compatible port parameters.  \n        A component may also support proprietary communication.\n        \n        If proprietary communication is supported the negotiation of \n        proprietary communication is done outside of OMX in a vendor \n        specific way. It is only required that the proper result be \n        returned and the details of how the setup is done is left \n        to the component implementation.  \n    \n        When this method is invoked when nPort in an output port, the\n        component will:\n        1.  Populate the pTunnelSetup structure with the output port's \n            requirements and constraints for the tunnel.\n\n        When this method is invoked when nPort in an input port, the\n        component will:\n        1.  Query the necessary parameters from the output port to \n            determine if the ports are compatible for tunneling\n        2.  If the ports are compatible, the component should store\n            the tunnel step provided by the output port\n        3.  Determine which port (either input or output) is the buffer\n            supplier, and call OMX_SetParameter on the output port to\n            indicate this selection.\n        \n        The component will return from this call within 5 msec.\n    \n        @param [in] hComp\n            Handle of the component to be accessed.  This is the component\n            handle returned by the call to the OMX_GetHandle method.\n        @param [in] nPort\n            nPort is used to select the port on the component to be used\n            for tunneling.\n        @param [in] hTunneledComp\n            Handle of the component to tunnel with.  This is the component \n            handle returned by the call to the OMX_GetHandle method.  When\n            this parameter is 0x0 the component should setup the port for\n            communication with the application / IL Client.\n        @param [in] nPortOutput\n            nPortOutput is used indicate the port the component should\n            tunnel with.\n        @param [in] pTunnelSetup\n            Pointer to the tunnel setup structure.  When nPort is an output port\n            the component should populate the fields of this structure.  When\n            When nPort is an input port the component should review the setup\n            provided by the component with the output port.\n        @return OMX_ERRORTYPE\n            If the command successfully executes, the return code will be\n            OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n        @ingroup tun\n    */\n\n    OMX_ERRORTYPE (*ComponentTunnelRequest)(\n        OMX_IN  OMX_HANDLETYPE hComp,\n        OMX_IN  OMX_U32 nPort,\n        OMX_IN  OMX_HANDLETYPE hTunneledComp,\n        OMX_IN  OMX_U32 nTunneledPort,\n        OMX_INOUT  OMX_TUNNELSETUPTYPE* pTunnelSetup); \n\n    /** refer to OMX_UseBuffer in OMX_core.h or the OMX IL \n        specification for details on the UseBuffer method.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*UseBuffer)(\n            OMX_IN OMX_HANDLETYPE hComponent,\n            OMX_INOUT OMX_BUFFERHEADERTYPE** ppBufferHdr,\n            OMX_IN OMX_U32 nPortIndex,\n            OMX_IN OMX_PTR pAppPrivate,\n            OMX_IN OMX_U32 nSizeBytes,\n            OMX_IN OMX_U8* pBuffer);\n\n    /** refer to OMX_AllocateBuffer in OMX_core.h or the OMX IL \n        specification for details on the AllocateBuffer method.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*AllocateBuffer)(\n            OMX_IN OMX_HANDLETYPE hComponent,\n            OMX_INOUT OMX_BUFFERHEADERTYPE** ppBuffer,\n            OMX_IN OMX_U32 nPortIndex,\n            OMX_IN OMX_PTR pAppPrivate,\n            OMX_IN OMX_U32 nSizeBytes);\n\n    /** refer to OMX_FreeBuffer in OMX_core.h or the OMX IL \n        specification for details on the FreeBuffer method.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*FreeBuffer)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_U32 nPortIndex,\n            OMX_IN  OMX_BUFFERHEADERTYPE* pBuffer);\n\n    /** refer to OMX_EmptyThisBuffer in OMX_core.h or the OMX IL \n        specification for details on the EmptyThisBuffer method.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*EmptyThisBuffer)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_BUFFERHEADERTYPE* pBuffer);\n\n    /** refer to OMX_FillThisBuffer in OMX_core.h or the OMX IL \n        specification for details on the FillThisBuffer method.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*FillThisBuffer)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_BUFFERHEADERTYPE* pBuffer);\n\n    /** The SetCallbacks method is used by the core to specify the callback\n        structure from the application to the component.  This is a blocking\n        call.  The component will return from this call within 5 msec.\n        @param [in] hComponent\n            Handle of the component to be accessed.  This is the component\n            handle returned by the call to the GetHandle function.\n        @param [in] pCallbacks\n            pointer to an OMX_CALLBACKTYPE structure used to provide the \n            callback information to the component\n        @param [in] pAppData\n            pointer to an application defined value.  It is anticipated that \n            the application will pass a pointer to a data structure or a \"this\n            pointer\" in this area to allow the callback (in the application)\n            to determine the context of the call\n        @return OMX_ERRORTYPE\n            If the command successfully executes, the return code will be\n            OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n     */\n    OMX_ERRORTYPE (*SetCallbacks)(\n            OMX_IN  OMX_HANDLETYPE hComponent,\n            OMX_IN  OMX_CALLBACKTYPE* pCallbacks, \n            OMX_IN  OMX_PTR pAppData);\n\n    /** ComponentDeInit method is used to deinitialize the component\n        providing a means to free any resources allocated at component\n        initialization.  NOTE:  After this call the component handle is\n        not valid for further use.\n        @param [in] hComponent\n            Handle of the component to be accessed.  This is the component\n            handle returned by the call to the GetHandle function.\n        @return OMX_ERRORTYPE\n            If the command successfully executes, the return code will be\n            OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n     */\n    OMX_ERRORTYPE (*ComponentDeInit)(\n            OMX_IN  OMX_HANDLETYPE hComponent);\n\n    /** @ingroup buf */\n    OMX_ERRORTYPE (*UseEGLImage)(\n            OMX_IN OMX_HANDLETYPE hComponent,\n            OMX_INOUT OMX_BUFFERHEADERTYPE** ppBufferHdr,\n            OMX_IN OMX_U32 nPortIndex,\n            OMX_IN OMX_PTR pAppPrivate,\n            OMX_IN void* eglImage);\n\n    OMX_ERRORTYPE (*ComponentRoleEnum)(\n        OMX_IN OMX_HANDLETYPE hComponent,\n\t\tOMX_OUT OMX_U8 *cRole,\n\t\tOMX_IN OMX_U32 nIndex);\n\n} OMX_COMPONENTTYPE;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_ContentPipe.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** OMX_ContentPipe.h - OpenMax IL version 1.1.2\n *  The OMX_ContentPipe header file contains the definitions used to define\n *  the public interface for content piples.  This header file is intended to\n *  be used by the component.\n */\n\n#ifndef OMX_CONTENTPIPE_H\n#define OMX_CONTENTPIPE_H\n\n#ifndef KD_EACCES\n/* OpenKODE error codes. CPResult values may be zero (indicating success\n   or one of the following values) */\n#define KD_EACCES (1)\n#define KD_EADDRINUSE (2)\n#define KD_EAGAIN (5)\n#define KD_EBADF (7)\n#define KD_EBUSY (8)\n#define KD_ECONNREFUSED (9)\n#define KD_ECONNRESET (10)\n#define KD_EDEADLK (11)\n#define KD_EDESTADDRREQ (12)\n#define KD_ERANGE (35)\n#define KD_EEXIST (13)\n#define KD_EFBIG (14)\n#define KD_EHOSTUNREACH (15)\n#define KD_EINVAL (17)\n#define KD_EIO (18)\n#define KD_EISCONN (20)\n#define KD_EISDIR (21)\n#define KD_EMFILE (22)\n#define KD_ENAMETOOLONG (23)\n#define KD_ENOENT (24)\n#define KD_ENOMEM (25)\n#define KD_ENOSPC (26)\n#define KD_ENOSYS (27)\n#define KD_ENOTCONN (28)\n#define KD_EPERM (33)\n#define KD_ETIMEDOUT (36)\n#define KD_EILSEQ (19)\n#endif\n\n/** Map types from OMX standard types only here so interface is as generic as possible. */\ntypedef OMX_U32    CPresult;\ntypedef char *     CPstring;  \ntypedef void *     CPhandle;\ntypedef OMX_U32    CPuint;\ntypedef OMX_S32    CPint;  \ntypedef char       CPbyte;  \ntypedef OMX_BOOL   CPbool;\n\n/** enumeration of origin types used in the CP_PIPETYPE's Seek function \n * @ingroup cp\n */\ntypedef enum CP_ORIGINTYPE {\n    CP_OriginBegin,      \n    CP_OriginCur,      \n    CP_OriginEnd,      \n    CP_OriginKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    CP_OriginVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    CP_OriginMax = 0X7FFFFFFF\n} CP_ORIGINTYPE;\n\n/** enumeration of contact access types used in the CP_PIPETYPE's Open function \n * @ingroup cp\n */\ntypedef enum CP_ACCESSTYPE {\n    CP_AccessRead,      \n    CP_AccessWrite,  \n    CP_AccessReadWrite ,  \n    CP_AccessKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    CP_AccessVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    CP_AccessMax = 0X7FFFFFFF\n} CP_ACCESSTYPE;\n\n/** enumeration of results returned by the CP_PIPETYPE's CheckAvailableBytes function \n * @ingroup cp\n */\ntypedef enum CP_CHECKBYTESRESULTTYPE\n{\n    CP_CheckBytesOk,                    /**< There are at least the request number \n                                              of bytes available */\n    CP_CheckBytesNotReady,              /**< The pipe is still retrieving bytes \n                                              and presently lacks sufficient bytes. \n                                              Client will be called when they are \n                                              sufficient bytes are available. */\n    CP_CheckBytesInsufficientBytes  ,     /**< The pipe has retrieved all bytes \n                                              but those available are less than those \n                                              requested */\n    CP_CheckBytesAtEndOfStream,         /**< The pipe has reached the end of stream\n                                              and no more bytes are available. */\n    CP_CheckBytesOutOfBuffers,          /**< All read/write buffers are currently in use. */\n    CP_CheckBytesKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    CP_CheckBytesVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    CP_CheckBytesMax = 0X7FFFFFFF\n} CP_CHECKBYTESRESULTTYPE;\n\n/** enumeration of content pipe events sent to the client callback. \n * @ingroup cp\n */\ntypedef enum CP_EVENTTYPE{\n    CP_BytesAvailable,      \t    /** bytes requested in a CheckAvailableBytes call are now available*/\n    CP_Overflow,  \t\t           /** enumeration of content pipe events sent to the client callback*/\n    CP_PipeDisconnected  ,  \t\t    /** enumeration of content pipe events sent to the client callback*/\n    CP_EventKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    CP_EventVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    CP_EventMax = 0X7FFFFFFF\n} CP_EVENTTYPE;\n\n/** content pipe definition \n * @ingroup cp\n */\ntypedef struct CP_PIPETYPE\n{\n    /** Open a content stream for reading or writing. */ \n    CPresult (*Open)( CPhandle* hContent, CPstring szURI, CP_ACCESSTYPE eAccess );\n\n    /** Close a content stream. */ \n    CPresult (*Close)( CPhandle hContent );\n\n    /** Create a content source and open it for writing. */ \n    CPresult (*Create)( CPhandle *hContent, CPstring szURI );\n\n    /** Check the that specified number of bytes are available for reading or writing (depending on access type).*/\n    CPresult (*CheckAvailableBytes)( CPhandle hContent, CPuint nBytesRequested, CP_CHECKBYTESRESULTTYPE *eResult );\n\n    /** Seek to certain position in the content relative to the specified origin. */\n    CPresult (*SetPosition)( CPhandle  hContent, CPint nOffset, CP_ORIGINTYPE eOrigin);\n\n    /** Retrieve the current position relative to the start of the content. */\n    CPresult (*GetPosition)( CPhandle hContent, CPuint *pPosition);\n\n    /** Retrieve data of the specified size from the content stream (advance content pointer by size of data).\n       Note: pipe client provides pointer. This function is appropriate for small high frequency reads. */\n    CPresult (*Read)( CPhandle hContent, CPbyte *pData, CPuint nSize); \n\n    /** Retrieve a buffer allocated by the pipe that contains the requested number of bytes. \n       Buffer contains the next block of bytes, as specified by nSize, of the content. nSize also\n       returns the size of the block actually read. Content pointer advances the by the returned size. \n       Note: pipe provides pointer. This function is appropriate for large reads. The client must call \n       ReleaseReadBuffer when done with buffer. \n\n       In some cases the requested block may not reside in contiguous memory within the\n       pipe implementation. For instance if the pipe leverages a circular buffer then the requested \n       block may straddle the boundary of the circular buffer. By default a pipe implementation \n       performs a copy in this case to provide the block to the pipe client in one contiguous buffer.\n       If, however, the client sets bForbidCopy, then the pipe returns only those bytes preceding the memory \n       boundary. Here the client may retrieve the data in segments over successive calls. */\n    CPresult (*ReadBuffer)( CPhandle hContent, CPbyte **ppBuffer, CPuint *nSize, CPbool bForbidCopy);\n\n    /** Release a buffer obtained by ReadBuffer back to the pipe. */\n    CPresult (*ReleaseReadBuffer)(CPhandle hContent, CPbyte *pBuffer);\n\n    /** Write data of the specified size to the content (advance content pointer by size of data).\n       Note: pipe client provides pointer. This function is appropriate for small high frequency writes. */\n    CPresult (*Write)( CPhandle hContent, CPbyte *data, CPuint nSize); \n\n    /** Retrieve a buffer allocated by the pipe used to write data to the content. \n       Client will fill buffer with output data. Note: pipe provides pointer. This function is appropriate\n       for large writes. The client must call WriteBuffer when done it has filled the buffer with data.*/\n    CPresult (*GetWriteBuffer)( CPhandle hContent, CPbyte **ppBuffer, CPuint nSize);\n\n    /** Deliver a buffer obtained via GetWriteBuffer to the pipe. Pipe will write the \n       the contents of the buffer to content and advance content pointer by the size of the buffer */\n    CPresult (*WriteBuffer)( CPhandle hContent, CPbyte *pBuffer, CPuint nFilledSize);\n\n    /** Register a per-handle client callback with the content pipe. */\n    CPresult (*RegisterCallback)( CPhandle hContent, CPresult (*ClientCallback)(CP_EVENTTYPE eEvent, CPuint iParam));\n\n} CP_PIPETYPE;\n\n#endif\n\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Core.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** OMX_Core.h - OpenMax IL version 1.1.2\n *  The OMX_Core header file contains the definitions used by both the\n *  application and the component to access common items.\n */\n\n#ifndef OMX_Core_h\n#define OMX_Core_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n/* Each OMX header shall include all required header files to allow the\n *  header to compile without errors.  The includes below are required\n *  for this header file to compile successfully \n */\n\n#include <OMX_Index.h>\n\n\n/** The OMX_COMMANDTYPE enumeration is used to specify the action in the\n *  OMX_SendCommand macro.  \n *  @ingroup core\n */\ntypedef enum OMX_COMMANDTYPE\n{\n    OMX_CommandStateSet,    /**< Change the component state */\n    OMX_CommandFlush,       /**< Flush the data queue(s) of a component */\n    OMX_CommandPortDisable, /**< Disable a port on a component. */\n    OMX_CommandPortEnable,  /**< Enable a port on a component. */\n    OMX_CommandMarkBuffer,  /**< Mark a component/buffer for observation */\n    OMX_CommandKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_CommandVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_CommandMax = 0X7FFFFFFF\n} OMX_COMMANDTYPE;\n\n\n\n/** The OMX_STATETYPE enumeration is used to indicate or change the component\n *  state.  This enumeration reflects the current state of the component when\n *  used with the OMX_GetState macro or becomes the parameter in a state change\n *  command when used with the OMX_SendCommand macro.\n *\n *  The component will be in the Loaded state after the component is initially\n *  loaded into memory.  In the Loaded state, the component is not allowed to\n *  allocate or hold resources other than to build it's internal parameter\n *  and configuration tables.  The application will send one or more\n *  SetParameters/GetParameters and SetConfig/GetConfig commands to the\n *  component and the component will record each of these parameter and\n *  configuration changes for use later.  When the application sends the\n *  Idle command, the component will acquire the resources needed for the\n *  specified configuration and will transition to the idle state if the\n *  allocation is successful.  If the component cannot successfully\n *  transition to the idle state for any reason, the state of the component\n *  shall be fully rolled back to the Loaded state (e.g. all allocated \n *  resources shall be released).  When the component receives the command\n *  to go to the Executing state, it shall begin processing buffers by\n *  sending all input buffers it holds to the application.  While\n *  the component is in the Idle state, the application may also send the\n *  Pause command.  If the component receives the pause command while in the\n *  Idle state, the component shall send all input buffers it holds to the \n *  application, but shall not begin processing buffers.  This will allow the\n *  application to prefill buffers.\n * \n *  @ingroup comp\n */\n\ntypedef enum OMX_STATETYPE\n{\n    OMX_StateInvalid,      /**< component has detected that it's internal data \n                                structures are corrupted to the point that\n                                it cannot determine it's state properly */\n    OMX_StateLoaded,      /**< component has been loaded but has not completed\n                                initialization.  The OMX_SetParameter macro\n                                and the OMX_GetParameter macro are the only \n                                valid macros allowed to be sent to the \n                                component in this state. */\n    OMX_StateIdle,        /**< component initialization has been completed\n                                successfully and the component is ready to\n                                to start. */\n    OMX_StateExecuting,   /**< component has accepted the start command and\n                                is processing data (if data is available) */\n    OMX_StatePause,       /**< component has received pause command */\n    OMX_StateWaitForResources, /**< component is waiting for resources, either after \n                                preemption or before it gets the resources requested.\n                                See specification for complete details. */\n    OMX_StateKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_StateVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_StateMax = 0X7FFFFFFF\n} OMX_STATETYPE;\n\n/** The OMX_ERRORTYPE enumeration defines the standard OMX Errors.  These \n *  errors should cover most of the common failure cases.  However, \n *  vendors are free to add additional error messages of their own as \n *  long as they follow these rules:\n *  1.  Vendor error messages shall be in the range of 0x90000000 to\n *      0x9000FFFF.\n *  2.  Vendor error messages shall be defined in a header file provided\n *      with the component.  No error messages are allowed that are\n *      not defined.\n */\ntypedef enum OMX_ERRORTYPE\n{\n  OMX_ErrorNone = 0,\n\n  /** There were insufficient resources to perform the requested operation */\n  OMX_ErrorInsufficientResources = (OMX_S32) 0x80001000,\n\n  /** There was an error, but the cause of the error could not be determined */\n  OMX_ErrorUndefined = (OMX_S32) 0x80001001,\n\n  /** The component name string was not valid */\n  OMX_ErrorInvalidComponentName = (OMX_S32) 0x80001002,\n\n  /** No component with the specified name string was found */\n  OMX_ErrorComponentNotFound = (OMX_S32) 0x80001003,\n\n  /** The component specified did not have a \"OMX_ComponentInit\" or\n      \"OMX_ComponentDeInit entry point */\n  OMX_ErrorInvalidComponent = (OMX_S32) 0x80001004,\n\n  /** One or more parameters were not valid */\n  OMX_ErrorBadParameter = (OMX_S32) 0x80001005,\n\n  /** The requested function is not implemented */\n  OMX_ErrorNotImplemented = (OMX_S32) 0x80001006,\n\n  /** The buffer was emptied before the next buffer was ready */\n  OMX_ErrorUnderflow = (OMX_S32) 0x80001007,\n\n  /** The buffer was not available when it was needed */\n  OMX_ErrorOverflow = (OMX_S32) 0x80001008,\n\n  /** The hardware failed to respond as expected */\n  OMX_ErrorHardware = (OMX_S32) 0x80001009,\n\n  /** The component is in the state OMX_StateInvalid */\n  OMX_ErrorInvalidState = (OMX_S32) 0x8000100A,\n\n  /** Stream is found to be corrupt */\n  OMX_ErrorStreamCorrupt = (OMX_S32) 0x8000100B,\n\n  /** Ports being connected are not compatible */\n  OMX_ErrorPortsNotCompatible = (OMX_S32) 0x8000100C,\n\n  /** Resources allocated to an idle component have been\n      lost resulting in the component returning to the loaded state */\n  OMX_ErrorResourcesLost = (OMX_S32) 0x8000100D,\n\n  /** No more indicies can be enumerated */\n  OMX_ErrorNoMore = (OMX_S32) 0x8000100E,\n\n  /** The component detected a version mismatch */\n  OMX_ErrorVersionMismatch = (OMX_S32) 0x8000100F,\n\n  /** The component is not ready to return data at this time */\n  OMX_ErrorNotReady = (OMX_S32) 0x80001010,\n\n  /** There was a timeout that occurred */\n  OMX_ErrorTimeout = (OMX_S32) 0x80001011,\n\n  /** This error occurs when trying to transition into the state you are already in */\n  OMX_ErrorSameState = (OMX_S32) 0x80001012,\n\n  /** Resources allocated to an executing or paused component have been \n      preempted, causing the component to return to the idle state */\n  OMX_ErrorResourcesPreempted = (OMX_S32) 0x80001013, \n\n  /** A non-supplier port sends this error to the IL client (via the EventHandler callback) \n      during the allocation of buffers (on a transition from the LOADED to the IDLE state or\n      on a port restart) when it deems that it has waited an unusually long time for the supplier \n      to send it an allocated buffer via a UseBuffer call. */\n  OMX_ErrorPortUnresponsiveDuringAllocation = (OMX_S32) 0x80001014,\n\n  /** A non-supplier port sends this error to the IL client (via the EventHandler callback) \n      during the deallocation of buffers (on a transition from the IDLE to LOADED state or \n      on a port stop) when it deems that it has waited an unusually long time for the supplier \n      to request the deallocation of a buffer header via a FreeBuffer call. */\n  OMX_ErrorPortUnresponsiveDuringDeallocation = (OMX_S32) 0x80001015,\n\n  /** A supplier port sends this error to the IL client (via the EventHandler callback) \n      during the stopping of a port (either on a transition from the IDLE to LOADED \n      state or a port stop) when it deems that it has waited an unusually long time for \n      the non-supplier to return a buffer via an EmptyThisBuffer or FillThisBuffer call. */\n  OMX_ErrorPortUnresponsiveDuringStop = (OMX_S32) 0x80001016,\n\n  /** Attempting a state transtion that is not allowed */\n  OMX_ErrorIncorrectStateTransition = (OMX_S32) 0x80001017,\n\n  /* Attempting a command that is not allowed during the present state. */\n  OMX_ErrorIncorrectStateOperation = (OMX_S32) 0x80001018, \n\n  /** The values encapsulated in the parameter or config structure are not supported. */\n  OMX_ErrorUnsupportedSetting = (OMX_S32) 0x80001019,\n\n  /** The parameter or config indicated by the given index is not supported. */\n  OMX_ErrorUnsupportedIndex = (OMX_S32) 0x8000101A,\n\n  /** The port index supplied is incorrect. */\n  OMX_ErrorBadPortIndex = (OMX_S32) 0x8000101B,\n\n  /** The port has lost one or more of its buffers and it thus unpopulated. */\n  OMX_ErrorPortUnpopulated = (OMX_S32) 0x8000101C,\n\n  /** Component suspended due to temporary loss of resources */\n  OMX_ErrorComponentSuspended = (OMX_S32) 0x8000101D,\n\n  /** Component suspended due to an inability to acquire dynamic resources */\n  OMX_ErrorDynamicResourcesUnavailable = (OMX_S32) 0x8000101E,\n\n  /** When the macroblock error reporting is enabled the component returns new error \n  for every frame that has errors */\n  OMX_ErrorMbErrorsInFrame = (OMX_S32) 0x8000101F,\n\n  /** A component reports this error when it cannot parse or determine the format of an input stream. */\n  OMX_ErrorFormatNotDetected = (OMX_S32) 0x80001020, \n\n  /** The content open operation failed. */\n  OMX_ErrorContentPipeOpenFailed = (OMX_S32) 0x80001021,\n\n  /** The content creation operation failed. */\n  OMX_ErrorContentPipeCreationFailed = (OMX_S32) 0x80001022,\n\n  /** Separate table information is being used */\n  OMX_ErrorSeperateTablesUsed = (OMX_S32) 0x80001023,\n\n  /** Tunneling is unsupported by the component*/\n  OMX_ErrorTunnelingUnsupported = (OMX_S32) 0x80001024,\n\n  OMX_ErrorKhronosExtensions = (OMX_S32)0x8F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n  OMX_ErrorVendorStartUnused = (OMX_S32)0x90000000, /**< Reserved region for introducing Vendor Extensions */\n  OMX_ErrorMax = 0x7FFFFFFF\n} OMX_ERRORTYPE;\n\n/** @ingroup core */\ntypedef OMX_ERRORTYPE (* OMX_COMPONENTINITTYPE)(OMX_IN  OMX_HANDLETYPE hComponent);\n\n/** @ingroup core */\ntypedef struct OMX_COMPONENTREGISTERTYPE\n{\n  const char          * pName;       /* Component name, 128 byte limit (including '\\0') applies */\n  OMX_COMPONENTINITTYPE pInitialize; /* Component instance initialization function */\n} OMX_COMPONENTREGISTERTYPE;\n\n/** @ingroup core */\nextern OMX_COMPONENTREGISTERTYPE OMX_ComponentRegistered[];\n\n/** @ingroup rpm */\ntypedef struct OMX_PRIORITYMGMTTYPE {\n OMX_U32 nSize;             /**< size of the structure in bytes */\n OMX_VERSIONTYPE nVersion;  /**< OMX specification version information */\n OMX_U32 nGroupPriority;            /**< Priority of the component group */\n OMX_U32 nGroupID;                  /**< ID of the component group */\n} OMX_PRIORITYMGMTTYPE;\n\n/* Component name and Role names are limited to 128 characters including the terminating '\\0'. */\n#define OMX_MAX_STRINGNAME_SIZE 128\n\n/** @ingroup comp */\ntypedef struct OMX_PARAM_COMPONENTROLETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U8 cRole[OMX_MAX_STRINGNAME_SIZE];  /**< name of standard component which defines component role */\n} OMX_PARAM_COMPONENTROLETYPE;\n\n/** End of Stream Buffer Flag: \n  *\n  * A component sets EOS when it has no more data to emit on a particular \n  * output port. Thus an output port shall set EOS on the last buffer it \n  * emits. A component's determination of when an output port should \n  * cease sending data is implemenation specific.\n  * @ingroup buf\n  */\n\n#define OMX_BUFFERFLAG_EOS 0x00000001 \n\n/** Start Time Buffer Flag: \n *\n * The source of a stream (e.g. a demux component) sets the STARTTIME\n * flag on the buffer that contains the starting timestamp for the\n * stream. The starting timestamp corresponds to the first data that\n * should be displayed at startup or after a seek.\n * The first timestamp of the stream is not necessarily the start time.\n * For instance, in the case of a seek to a particular video frame, \n * the target frame may be an interframe. Thus the first buffer of \n * the stream will be the intra-frame preceding the target frame and\n * the starttime will occur with the target frame (with any other\n * required frames required to reconstruct the target intervening).\n *\n * The STARTTIME flag is directly associated with the buffer's \n * timestamp ' thus its association to buffer data and its \n * propagation is identical to the timestamp's.\n *\n * When a Sync Component client receives a buffer with the \n * STARTTIME flag it shall perform a SetConfig on its sync port \n * using OMX_ConfigTimeClientStartTime and passing the buffer's\n * timestamp.\n * \n * @ingroup buf\n */\n\n#define OMX_BUFFERFLAG_STARTTIME 0x00000002\n\n \n\n/** Decode Only Buffer Flag: \n *\n * The source of a stream (e.g. a demux component) sets the DECODEONLY\n * flag on any buffer that should shall be decoded but should not be\n * displayed. This flag is used, for instance, when a source seeks to \n * a target interframe that requires the decode of frames preceding the \n * target to facilitate the target's reconstruction. In this case the \n * source would emit the frames preceding the target downstream \n * but mark them as decode only.\n *\n * The DECODEONLY is associated with buffer data and propagated in a \n * manner identical to the buffer timestamp.\n *\n * A component that renders data should ignore all buffers with \n * the DECODEONLY flag set.\n * \n * @ingroup buf\n */\n\n#define OMX_BUFFERFLAG_DECODEONLY 0x00000004\n\n\n/* Data Corrupt Flag: This flag is set when the IL client believes the data in the associated buffer is corrupt \n * @ingroup buf\n */\n\n#define OMX_BUFFERFLAG_DATACORRUPT 0x00000008\n\n/* End of Frame: The buffer contains exactly one end of frame and no data\n *  occurs after the end of frame. This flag is an optional hint. The absence\n *  of this flag does not imply the absence of an end of frame within the buffer. \n * @ingroup buf\n*/\n#define OMX_BUFFERFLAG_ENDOFFRAME 0x00000010\n\n/* Sync Frame Flag: This flag is set when the buffer content contains a coded sync frame ' \n *  a frame that has no dependency on any other frame information \n *  @ingroup buf\n */\n#define OMX_BUFFERFLAG_SYNCFRAME 0x00000020\n\n/* Extra data present flag: there is extra data appended to the data stream\n * residing in the buffer \n * @ingroup buf  \n */\n#define OMX_BUFFERFLAG_EXTRADATA 0x00000040\n\n/** Codec Config Buffer Flag: \n* OMX_BUFFERFLAG_CODECCONFIG is an optional flag that is set by an\n* output port when all bytes in the buffer form part or all of a set of\n* codec specific configuration data.  Examples include SPS/PPS nal units\n* for OMX_VIDEO_CodingAVC or AudioSpecificConfig data for\n* OMX_AUDIO_CodingAAC.  Any component that for a given stream sets \n* OMX_BUFFERFLAG_CODECCONFIG shall not mix codec configuration bytes\n* with frame data in the same buffer, and shall send all buffers\n* containing codec configuration bytes before any buffers containing\n* frame data that those configurations bytes describe.\n* If the stream format for a particular codec has a frame specific\n* header at the start of each frame, for example OMX_AUDIO_CodingMP3 or\n* OMX_AUDIO_CodingAAC in ADTS mode, then these shall be presented as\n* normal without setting OMX_BUFFERFLAG_CODECCONFIG.\n * @ingroup buf\n */\n#define OMX_BUFFERFLAG_CODECCONFIG 0x00000080\n\n/*\n* OMX_BUFFERFLAG_READONLY: This flag is set when a component emitting the\n* buffer on an output port or the IL client wishes to identify the buffer\n* payload contents to be read-only. An IL client or an input port\n* shall not alter the contents of the buffer. This flag shall only be\n* cleared by the originator of the buffer when the buffer is returned.\n* For tunneled ports, the usage of this flag shall be allowed only if the\n* components negotiated a read-only tunnel\n*/\n#define OMX_BUFFERFLAG_READONLY 0x00000200\n\n/** @ingroup buf */\ntypedef struct OMX_BUFFERHEADERTYPE\n{\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U8* pBuffer;            /**< Pointer to actual block of memory \n                                     that is acting as the buffer */\n    OMX_U32 nAllocLen;          /**< size of the buffer allocated, in bytes */\n    OMX_U32 nFilledLen;         /**< number of bytes currently in the \n                                     buffer */\n    OMX_U32 nOffset;            /**< start offset of valid data in bytes from\n                                     the start of the buffer */\n    OMX_PTR pAppPrivate;        /**< pointer to any data the application\n                                     wants to associate with this buffer */\n    OMX_PTR pPlatformPrivate;   /**< pointer to any data the platform\n                                     wants to associate with this buffer */ \n    OMX_PTR pInputPortPrivate;  /**< pointer to any data the input port\n                                     wants to associate with this buffer */\n    OMX_PTR pOutputPortPrivate; /**< pointer to any data the output port\n                                     wants to associate with this buffer */\n    OMX_HANDLETYPE hMarkTargetComponent; /**< The component that will generate a \n                                              mark event upon processing this buffer. */\n    OMX_PTR pMarkData;          /**< Application specific data associated with \n                                     the mark sent on a mark event to disambiguate \n                                     this mark from others. */\n    OMX_U32 nTickCount;         /**< Optional entry that the component and\n                                     application can update with a tick count\n                                     when they access the component.  This\n                                     value should be in microseconds.  Since\n                                     this is a value relative to an arbitrary\n                                     starting point, this value cannot be used \n                                     to determine absolute time.  This is an\n                                     optional entry and not all components\n                                     will update it.*/\n OMX_TICKS nTimeStamp;          /**< Timestamp corresponding to the sample \n                                     starting at the first logical sample \n                                     boundary in the buffer. Timestamps of \n                                     successive samples within the buffer may\n                                     be inferred by adding the duration of the \n                                     of the preceding buffer to the timestamp\n                                     of the preceding buffer.*/\n  OMX_U32     nFlags;           /**< buffer specific flags */\n  OMX_U32 nOutputPortIndex;     /**< The index of the output port (if any) using \n                                     this buffer */\n  OMX_U32 nInputPortIndex;      /**< The index of the input port (if any) using\n                                     this buffer */\n} OMX_BUFFERHEADERTYPE;\n\n/** The OMX_EXTRADATATYPE enumeration is used to define the \n * possible extra data payload types.\n * NB: this enum is binary backwards compatible with the previous\n * OMX_EXTRADATA_QUANT define.  This should be replaced with\n * OMX_ExtraDataQuantization.\n */\ntypedef enum OMX_EXTRADATATYPE\n{\n   OMX_ExtraDataNone = 0,                       /**< Indicates that no more extra data sections follow */        \n   OMX_ExtraDataQuantization,                   /**< The data payload contains quantization data */\n   OMX_ExtraDataKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n   OMX_ExtraDataVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n   OMX_ExtraDataMax = 0x7FFFFFFF\n} OMX_EXTRADATATYPE;\n\n\ntypedef struct OMX_OTHER_EXTRADATATYPE  {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;               \n    OMX_U32 nPortIndex;\n    OMX_EXTRADATATYPE eType;       /* Extra Data type */\n    OMX_U32 nDataSize;   /* Size of the supporting data to follow */\n    OMX_U8  data[1];     /* Supporting data hint  */\n} OMX_OTHER_EXTRADATATYPE;\n\n/** @ingroup comp */\ntypedef struct OMX_PORT_PARAM_TYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPorts;             /**< The number of ports for this component */\n    OMX_U32 nStartPortNumber;   /** first port number for this type of port */\n} OMX_PORT_PARAM_TYPE; \n\n/** @ingroup comp */\ntypedef enum OMX_EVENTTYPE\n{\n    OMX_EventCmdComplete,         /**< component has sucessfully completed a command */\n    OMX_EventError,               /**< component has detected an error condition */\n    OMX_EventMark,                /**< component has detected a buffer mark */\n    OMX_EventPortSettingsChanged, /**< component is reported a port settings change */\n    OMX_EventBufferFlag,          /**< component has detected an EOS */ \n    OMX_EventResourcesAcquired,   /**< component has been granted resources and is\n                                       automatically starting the state change from\n                                       OMX_StateWaitForResources to OMX_StateIdle. */\n   OMX_EventComponentResumed,     /**< Component resumed due to reacquisition of resources */\n   OMX_EventDynamicResourcesAvailable, /**< Component has acquired previously unavailable dynamic resources */\n   OMX_EventPortFormatDetected,      /**< Component has detected a supported format. */\n   OMX_EventKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n   OMX_EventVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n   OMX_EventMax = 0x7FFFFFFF\n} OMX_EVENTTYPE;\n\ntypedef struct OMX_CALLBACKTYPE\n{\n    /** The EventHandler method is used to notify the application when an\n        event of interest occurs.  Events are defined in the OMX_EVENTTYPE\n        enumeration.  Please see that enumeration for details of what will\n        be returned for each type of event. Callbacks should not return\n        an error to the component, so if an error occurs, the application \n        shall handle it internally.  This is a blocking call.\n\n        The application should return from this call within 5 msec to avoid\n        blocking the component for an excessively long period of time.\n\n        @param hComponent\n            handle of the component to access.  This is the component\n            handle returned by the call to the GetHandle function.\n        @param pAppData\n            pointer to an application defined value that was provided in the \n            pAppData parameter to the OMX_GetHandle method for the component.\n            This application defined value is provided so that the application \n            can have a component specific context when receiving the callback.\n        @param eEvent\n            Event that the component wants to notify the application about.\n        @param nData1\n            nData will be the OMX_ERRORTYPE for an error event and will be \n            an OMX_COMMANDTYPE for a command complete event and OMX_INDEXTYPE for a OMX_PortSettingsChanged event.\n         @param nData2\n            nData2 will hold further information related to the event. Can be OMX_STATETYPE for\n            a OMX_CommandStateSet command or port index for a OMX_PortSettingsChanged event.\n            Default value is 0 if not used. )\n        @param pEventData\n            Pointer to additional event-specific data (see spec for meaning).\n      */\n\n   OMX_ERRORTYPE (*EventHandler)(\n        OMX_IN OMX_HANDLETYPE hComponent,\n        OMX_IN OMX_PTR pAppData,\n        OMX_IN OMX_EVENTTYPE eEvent,\n        OMX_IN OMX_U32 nData1,\n        OMX_IN OMX_U32 nData2,\n        OMX_IN OMX_PTR pEventData);\n\n    /** The EmptyBufferDone method is used to return emptied buffers from an\n        input port back to the application for reuse.  This is a blocking call \n        so the application should not attempt to refill the buffers during this\n        call, but should queue them and refill them in another thread.  There\n        is no error return, so the application shall handle any errors generated\n        internally.  \n        \n        The application should return from this call within 5 msec.\n        \n        @param hComponent\n            handle of the component to access.  This is the component\n            handle returned by the call to the GetHandle function.\n        @param pAppData\n            pointer to an application defined value that was provided in the \n            pAppData parameter to the OMX_GetHandle method for the component.\n            This application defined value is provided so that the application \n            can have a component specific context when receiving the callback.\n        @param pBuffer\n            pointer to an OMX_BUFFERHEADERTYPE structure allocated with UseBuffer\n            or AllocateBuffer indicating the buffer that was emptied.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*EmptyBufferDone)(\n        OMX_IN OMX_HANDLETYPE hComponent,\n        OMX_IN OMX_PTR pAppData,\n        OMX_IN OMX_BUFFERHEADERTYPE* pBuffer);\n\n    /** The FillBufferDone method is used to return filled buffers from an\n        output port back to the application for emptying and then reuse.  \n        This is a blocking call so the application should not attempt to \n        empty the buffers during this call, but should queue the buffers \n        and empty them in another thread.  There is no error return, so \n        the application shall handle any errors generated internally.  The \n        application shall also update the buffer header to indicate the\n        number of bytes placed into the buffer.  \n\n        The application should return from this call within 5 msec.\n        \n        @param hComponent\n            handle of the component to access.  This is the component\n            handle returned by the call to the GetHandle function.\n        @param pAppData\n            pointer to an application defined value that was provided in the \n            pAppData parameter to the OMX_GetHandle method for the component.\n            This application defined value is provided so that the application \n            can have a component specific context when receiving the callback.\n        @param pBuffer\n            pointer to an OMX_BUFFERHEADERTYPE structure allocated with UseBuffer\n            or AllocateBuffer indicating the buffer that was filled.\n        @ingroup buf\n     */\n    OMX_ERRORTYPE (*FillBufferDone)(\n        OMX_OUT OMX_HANDLETYPE hComponent,\n        OMX_OUT OMX_PTR pAppData,\n        OMX_OUT OMX_BUFFERHEADERTYPE* pBuffer);\n\n} OMX_CALLBACKTYPE;\n\n/** The OMX_BUFFERSUPPLIERTYPE enumeration is used to dictate port supplier\n    preference when tunneling between two ports.\n    @ingroup tun buf\n*/\ntypedef enum OMX_BUFFERSUPPLIERTYPE\n{\n    OMX_BufferSupplyUnspecified = 0x0, /**< port supplying the buffers is unspecified,\n                                              or don't care */\n    OMX_BufferSupplyInput,             /**< input port supplies the buffers */\n    OMX_BufferSupplyOutput,            /**< output port supplies the buffers */\n    OMX_BufferSupplyKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_BufferSupplyVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_BufferSupplyMax = 0x7FFFFFFF\n} OMX_BUFFERSUPPLIERTYPE;\n\n\n/** buffer supplier parameter \n * @ingroup tun\n */\ntypedef struct OMX_PARAM_BUFFERSUPPLIERTYPE {\n    OMX_U32 nSize; /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex; /**< port that this structure applies to */\n    OMX_BUFFERSUPPLIERTYPE eBufferSupplier; /**< buffer supplier */\n} OMX_PARAM_BUFFERSUPPLIERTYPE;\n\n\n/**< indicates that buffers received by an input port of a tunnel \n     may not modify the data in the buffers \n     @ingroup tun\n */\n#define OMX_PORTTUNNELFLAG_READONLY 0x00000001 \n\n\n/** The OMX_TUNNELSETUPTYPE structure is used to pass data from an output\n    port to an input port as part the two ComponentTunnelRequest calls\n    resulting from a OMX_SetupTunnel call from the IL Client. \n    @ingroup tun\n */   \ntypedef struct OMX_TUNNELSETUPTYPE\n{\n    OMX_U32 nTunnelFlags;             /**< bit flags for tunneling */\n    OMX_BUFFERSUPPLIERTYPE eSupplier; /**< supplier preference */\n} OMX_TUNNELSETUPTYPE; \n\n/* OMX Component headers is included to enable the core to use\n   macros for functions into the component for OMX release 1.0.  \n   Developers should not access any structures or data from within\n   the component header directly */\n/* TO BE REMOVED - #include <OMX_Component.h> */\n\n/** GetComponentVersion will return information about the component.  \n    This is a blocking call.  This macro will go directly from the\n    application to the component (via a core macro).  The\n    component will return from this call within 5 msec.\n    @param [in] hComponent\n        handle of component to execute the command\n    @param [out] pComponentName\n        pointer to an empty string of length 128 bytes.  The component \n        will write its name into this string.  The name will be \n        terminated by a single zero byte.  The name of a component will \n        be 127 bytes or less to leave room for the trailing zero byte.  \n        An example of a valid component name is \"OMX.ABC.ChannelMixer\\0\".\n    @param [out] pComponentVersion\n        pointer to an OMX Version structure that the component will fill \n        in.  The component will fill in a value that indicates the \n        component version.  NOTE: the component version is NOT the same \n        as the OMX Specification version (found in all structures).  The \n        component version is defined by the vendor of the component and \n        its value is entirely up to the component vendor.\n    @param [out] pSpecVersion\n        pointer to an OMX Version structure that the component will fill \n        in.  The SpecVersion is the version of the specification that the \n        component was built against.  Please note that this value may or \n        may not match the structure's version.  For example, if the \n        component was built against the 2.0 specification, but the \n        application (which creates the structure is built against the \n        1.0 specification the versions would be different.\n    @param [out] pComponentUUID\n        pointer to the UUID of the component which will be filled in by \n        the component.  The UUID is a unique identifier that is set at \n        RUN time for the component and is unique to each instantion of \n        the component.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_GetComponentVersion(                            \\\n        hComponent,                                         \\\n        pComponentName,                                     \\\n        pComponentVersion,                                  \\\n        pSpecVersion,                                       \\\n        pComponentUUID)                                     \\\n    ((OMX_COMPONENTTYPE*)hComponent)->GetComponentVersion(  \\\n        hComponent,                                         \\\n        pComponentName,                                     \\\n        pComponentVersion,                                  \\\n        pSpecVersion,                                       \\\n        pComponentUUID)                 /* Macro End */\n\n\n/** Send a command to the component.  This call is a non-blocking call.\n    The component should check the parameters and then queue the command\n    to the component thread to be executed.  The component thread shall \n    send the EventHandler() callback at the conclusion of the command. \n    This macro will go directly from the application to the component (via\n    a core macro).  The component will return from this call within 5 msec.\n    \n    When the command is \"OMX_CommandStateSet\" the component will queue a\n    state transition to the new state idenfied in nParam.\n    \n    When the command is \"OMX_CommandFlush\", to flush a port's buffer queues,\n    the command will force the component to return all buffers NOT CURRENTLY \n    BEING PROCESSED to the application, in the order in which the buffers \n    were received.\n    \n    When the command is \"OMX_CommandPortDisable\" or \n    \"OMX_CommandPortEnable\", the component's port (given by the value of\n    nParam) will be stopped or restarted. \n    \n    When the command \"OMX_CommandMarkBuffer\" is used to mark a buffer, the\n    pCmdData will point to a OMX_MARKTYPE structure containing the component\n    handle of the component to examine the buffer chain for the mark.  nParam1\n    contains the index of the port on which the buffer mark is applied.\n\n    Specification text for more details. \n    \n    @param [in] hComponent\n        handle of component to execute the command\n    @param [in] Cmd\n        Command for the component to execute\n    @param [in] nParam\n        Parameter for the command to be executed.  When Cmd has the value \n        OMX_CommandStateSet, value is a member of OMX_STATETYPE.  When Cmd has \n        the value OMX_CommandFlush, value of nParam indicates which port(s) \n        to flush. -1 is used to flush all ports a single port index will \n        only flush that port.  When Cmd has the value \"OMX_CommandPortDisable\"\n        or \"OMX_CommandPortEnable\", the component's port is given by \n        the value of nParam.  When Cmd has the value \"OMX_CommandMarkBuffer\"\n        the components pot is given by the value of nParam.\n    @param [in] pCmdData\n        Parameter pointing to the OMX_MARKTYPE structure when Cmd has the value\n        \"OMX_CommandMarkBuffer\".     \n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_SendCommand(                                    \\\n         hComponent,                                        \\\n         Cmd,                                               \\\n         nParam,                                            \\\n         pCmdData)                                          \\\n     ((OMX_COMPONENTTYPE*)hComponent)->SendCommand(         \\\n         hComponent,                                        \\\n         Cmd,                                               \\\n         nParam,                                            \\\n         pCmdData)                          /* Macro End */\n\n\n/** The OMX_GetParameter macro will get one of the current parameter \n    settings from the component.  This macro cannot only be invoked when \n    the component is in the OMX_StateInvalid state.  The nParamIndex\n    parameter is used to indicate which structure is being requested from\n    the component.  The application shall allocate the correct structure \n    and shall fill in the structure size and version information before \n    invoking this macro.  When the parameter applies to a port, the\n    caller shall fill in the appropriate nPortIndex value indicating the\n    port on which the parameter applies. If the component has not had \n    any settings changed, then the component should return a set of \n    valid DEFAULT  parameters for the component.  This is a blocking \n    call.  \n    \n    The component should return from this call within 20 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] nParamIndex\n        Index of the structure to be filled.  This value is from the\n        OMX_INDEXTYPE enumeration.\n    @param [in,out] pComponentParameterStructure\n        Pointer to application allocated structure to be filled by the \n        component.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_GetParameter(                                   \\\n        hComponent,                                         \\\n        nParamIndex,                                        \\\n        pComponentParameterStructure)                        \\\n    ((OMX_COMPONENTTYPE*)hComponent)->GetParameter(         \\\n        hComponent,                                         \\\n        nParamIndex,                                        \\\n        pComponentParameterStructure)    /* Macro End */\n\n\n/** The OMX_SetParameter macro will send an initialization parameter\n    structure to a component.  Each structure shall be sent one at a time,\n    in a separate invocation of the macro.  This macro can only be\n    invoked when the component is in the OMX_StateLoaded state, or the\n    port is disabled (when the parameter applies to a port). The \n    nParamIndex parameter is used to indicate which structure is being\n    passed to the component.  The application shall allocate the \n    correct structure and shall fill in the structure size and version \n    information (as well as the actual data) before invoking this macro.\n    The application is free to dispose of this structure after the call\n    as the component is required to copy any data it shall retain.  This \n    is a blocking call.  \n    \n    The component should return from this call within 20 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] nIndex\n        Index of the structure to be sent.  This value is from the\n        OMX_INDEXTYPE enumeration.\n    @param [in] pComponentParameterStructure\n        pointer to application allocated structure to be used for\n        initialization by the component.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_SetParameter(                                   \\\n        hComponent,                                         \\\n        nParamIndex,                                        \\\n        pComponentParameterStructure)                        \\\n    ((OMX_COMPONENTTYPE*)hComponent)->SetParameter(         \\\n        hComponent,                                         \\\n        nParamIndex,                                        \\\n        pComponentParameterStructure)    /* Macro End */\n\n\n/** The OMX_GetConfig macro will get one of the configuration structures \n    from a component.  This macro can be invoked anytime after the \n    component has been loaded.  The nParamIndex call parameter is used to \n    indicate which structure is being requested from the component.  The \n    application shall allocate the correct structure and shall fill in the \n    structure size and version information before invoking this macro.  \n    If the component has not had this configuration parameter sent before, \n    then the component should return a set of valid DEFAULT values for the \n    component.  This is a blocking call.  \n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] nIndex\n        Index of the structure to be filled.  This value is from the\n        OMX_INDEXTYPE enumeration.\n    @param [in,out] pComponentConfigStructure\n        pointer to application allocated structure to be filled by the \n        component.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n*/        \n#define OMX_GetConfig(                                      \\\n        hComponent,                                         \\\n        nConfigIndex,                                       \\\n        pComponentConfigStructure)                           \\\n    ((OMX_COMPONENTTYPE*)hComponent)->GetConfig(            \\\n        hComponent,                                         \\\n        nConfigIndex,                                       \\\n        pComponentConfigStructure)       /* Macro End */\n\n\n/** The OMX_SetConfig macro will send one of the configuration \n    structures to a component.  Each structure shall be sent one at a time,\n    each in a separate invocation of the macro.  This macro can be invoked \n    anytime after the component has been loaded.  The application shall \n    allocate the correct structure and shall fill in the structure size \n    and version information (as well as the actual data) before invoking \n    this macro.  The application is free to dispose of this structure after \n    the call as the component is required to copy any data it shall retain.  \n    This is a blocking call.  \n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] nConfigIndex\n        Index of the structure to be sent.  This value is from the\n        OMX_INDEXTYPE enumeration above.\n    @param [in] pComponentConfigStructure\n        pointer to application allocated structure to be used for\n        initialization by the component.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_SetConfig(                                      \\\n        hComponent,                                         \\\n        nConfigIndex,                                       \\\n        pComponentConfigStructure)                           \\\n    ((OMX_COMPONENTTYPE*)hComponent)->SetConfig(            \\\n        hComponent,                                         \\\n        nConfigIndex,                                       \\\n        pComponentConfigStructure)       /* Macro End */\n\n\n/** The OMX_GetExtensionIndex macro will invoke a component to translate \n    a vendor specific configuration or parameter string into an OMX \n    structure index.  There is no requirement for the vendor to support \n    this command for the indexes already found in the OMX_INDEXTYPE \n    enumeration (this is done to save space in small components).  The \n    component shall support all vendor supplied extension indexes not found\n    in the master OMX_INDEXTYPE enumeration.  This is a blocking call.  \n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the GetHandle function.\n    @param [in] cParameterName\n        OMX_STRING that shall be less than 128 characters long including\n        the trailing null byte.  This is the string that will get \n        translated by the component into a configuration index.\n    @param [out] pIndexType\n        a pointer to a OMX_INDEXTYPE to receive the index value.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_GetExtensionIndex(                              \\\n        hComponent,                                         \\\n        cParameterName,                                     \\\n        pIndexType)                                         \\\n    ((OMX_COMPONENTTYPE*)hComponent)->GetExtensionIndex(    \\\n        hComponent,                                         \\\n        cParameterName,                                     \\\n        pIndexType)                     /* Macro End */\n\n\n/** The OMX_GetState macro will invoke the component to get the current \n    state of the component and place the state value into the location\n    pointed to by pState.  \n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [out] pState\n        pointer to the location to receive the state.  The value returned\n        is one of the OMX_STATETYPE members \n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp\n */\n#define OMX_GetState(                                       \\\n        hComponent,                                         \\\n        pState)                                             \\\n    ((OMX_COMPONENTTYPE*)hComponent)->GetState(             \\\n        hComponent,                                         \\\n        pState)                         /* Macro End */\n\n\n/** The OMX_UseBuffer macro will request that the component use\n    a buffer (and allocate its own buffer header) already allocated \n    by another component, or by the IL Client. This is a blocking \n    call.\n    \n    The component should return from this call within 20 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [out] ppBuffer\n        pointer to an OMX_BUFFERHEADERTYPE structure used to receive the \n        pointer to the buffer header\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp buf\n */\n\n#define OMX_UseBuffer(                                      \\\n           hComponent,                                      \\\n           ppBufferHdr,                                     \\\n           nPortIndex,                                      \\\n           pAppPrivate,                                     \\\n           nSizeBytes,                                      \\\n           pBuffer)                                         \\\n    ((OMX_COMPONENTTYPE*)hComponent)->UseBuffer(            \\\n           hComponent,                                      \\\n           ppBufferHdr,                                     \\\n           nPortIndex,                                      \\\n           pAppPrivate,                                     \\\n           nSizeBytes,                                      \\\n           pBuffer)\n\n\n/** The OMX_AllocateBuffer macro will request that the component allocate \n    a new buffer and buffer header.  The component will allocate the \n    buffer and the buffer header and return a pointer to the buffer \n    header.  This is a blocking call.\n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [out] ppBuffer\n        pointer to an OMX_BUFFERHEADERTYPE structure used to receive \n        the pointer to the buffer header\n    @param [in] nPortIndex\n        nPortIndex is used to select the port on the component the buffer will\n        be used with.  The port can be found by using the nPortIndex\n        value as an index into the Port Definition array of the component.\n    @param [in] pAppPrivate\n        pAppPrivate is used to initialize the pAppPrivate member of the \n        buffer header structure.\n    @param [in] nSizeBytes\n        size of the buffer to allocate.  Used when bAllocateNew is true.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp buf\n */    \n#define OMX_AllocateBuffer(                                 \\\n        hComponent,                                         \\\n        ppBuffer,                                           \\\n        nPortIndex,                                         \\\n        pAppPrivate,                                        \\\n        nSizeBytes)                                         \\\n    ((OMX_COMPONENTTYPE*)hComponent)->AllocateBuffer(       \\\n        hComponent,                                         \\\n        ppBuffer,                                           \\\n        nPortIndex,                                         \\\n        pAppPrivate,                                        \\\n        nSizeBytes)                     /* Macro End */\n\n\n/** The OMX_FreeBuffer macro will release a buffer header from the component\n    which was allocated using either OMX_AllocateBuffer or OMX_UseBuffer. If  \n    the component allocated the buffer (see the OMX_UseBuffer macro) then \n    the component shall free the buffer and buffer header. This is a \n    blocking call. \n    \n    The component should return from this call within 20 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] nPortIndex\n        nPortIndex is used to select the port on the component the buffer will\n        be used with.\n    @param [in] pBuffer\n        pointer to an OMX_BUFFERHEADERTYPE structure allocated with UseBuffer\n        or AllocateBuffer.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp buf\n */\n#define OMX_FreeBuffer(                                     \\\n        hComponent,                                         \\\n        nPortIndex,                                         \\\n        pBuffer)                                            \\\n    ((OMX_COMPONENTTYPE*)hComponent)->FreeBuffer(           \\\n        hComponent,                                         \\\n        nPortIndex,                                         \\\n        pBuffer)                        /* Macro End */\n\n\n/** The OMX_EmptyThisBuffer macro will send a buffer full of data to an \n    input port of a component.  The buffer will be emptied by the component\n    and returned to the application via the EmptyBufferDone call back.\n    This is a non-blocking call in that the component will record the buffer\n    and return immediately and then empty the buffer, later, at the proper \n    time.  As expected, this macro may be invoked only while the component \n    is in the OMX_StateExecuting.  If nPortIndex does not specify an input\n    port, the component shall return an error.  \n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] pBuffer\n        pointer to an OMX_BUFFERHEADERTYPE structure allocated with UseBuffer\n        or AllocateBuffer.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp buf\n */\n#define OMX_EmptyThisBuffer(                                \\\n        hComponent,                                         \\\n        pBuffer)                                            \\\n    ((OMX_COMPONENTTYPE*)hComponent)->EmptyThisBuffer(      \\\n        hComponent,                                         \\\n        pBuffer)                        /* Macro End */\n\n\n/** The OMX_FillThisBuffer macro will send an empty buffer to an \n    output port of a component.  The buffer will be filled by the component\n    and returned to the application via the FillBufferDone call back.\n    This is a non-blocking call in that the component will record the buffer\n    and return immediately and then fill the buffer, later, at the proper \n    time.  As expected, this macro may be invoked only while the component \n    is in the OMX_ExecutingState.  If nPortIndex does not specify an output\n    port, the component shall return an error.  \n    \n    The component should return from this call within 5 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [in] pBuffer\n        pointer to an OMX_BUFFERHEADERTYPE structure allocated with UseBuffer\n        or AllocateBuffer.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp buf\n */\n#define OMX_FillThisBuffer(                                 \\\n        hComponent,                                         \\\n        pBuffer)                                            \\\n    ((OMX_COMPONENTTYPE*)hComponent)->FillThisBuffer(       \\\n        hComponent,                                         \\\n        pBuffer)                        /* Macro End */\n\n\n\n/** The OMX_UseEGLImage macro will request that the component use\n    a EGLImage provided by EGL (and allocate its own buffer header)\n    This is a blocking call.\n    \n    The component should return from this call within 20 msec.\n    \n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the OMX_GetHandle function.\n    @param [out] ppBuffer\n        pointer to an OMX_BUFFERHEADERTYPE structure used to receive the \n        pointer to the buffer header.  Note that the memory location used\n        for this buffer is NOT visible to the IL Client.\n    @param [in] nPortIndex\n        nPortIndex is used to select the port on the component the buffer will\n        be used with.  The port can be found by using the nPortIndex\n        value as an index into the Port Definition array of the component.\n    @param [in] pAppPrivate\n        pAppPrivate is used to initialize the pAppPrivate member of the \n        buffer header structure.\n    @param [in] eglImage\n        eglImage contains the handle of the EGLImage to use as a buffer on the\n        specified port.  The component is expected to validate properties of \n        the EGLImage against the configuration of the port to ensure the component\n        can use the EGLImage as a buffer.          \n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup comp buf\n */\n#define OMX_UseEGLImage(                                    \\\n           hComponent,                                      \\\n           ppBufferHdr,                                     \\\n           nPortIndex,                                      \\\n           pAppPrivate,                                     \\\n           eglImage)                                        \\\n    ((OMX_COMPONENTTYPE*)hComponent)->UseEGLImage(          \\\n           hComponent,                                      \\\n           ppBufferHdr,                                     \\\n           nPortIndex,                                      \\\n           pAppPrivate,                                     \\\n           eglImage)\n\n/** The OMX_Init method is used to initialize the OMX core.  It shall be the\n    first call made into OMX and it should only be executed one time without\n    an interviening OMX_Deinit call.  \n    \n    The core should return from this call within 20 msec.\n\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_APIENTRY OMX_Init(void);\n\n\n/** The OMX_Deinit method is used to deinitialize the OMX core.  It shall be \n    the last call made into OMX. In the event that the core determines that \n    thare are components loaded when this call is made, the core may return \n    with an error rather than try to unload the components.\n        \n    The core should return from this call within 20 msec.\n    \n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_APIENTRY OMX_Deinit(void);\n\n\n/** The OMX_ComponentNameEnum method will enumerate through all the names of\n    recognised valid components in the system. This function is provided\n    as a means to detect all the components in the system run-time. There is\n    no strict ordering to the enumeration order of component names, although\n    each name will only be enumerated once.  If the OMX core supports run-time\n    installation of new components, it is only requried to detect newly\n    installed components when the first call to enumerate component names\n    is made (i.e. when nIndex is 0x0).\n    \n    The core should return from this call in 20 msec.\n    \n    @param [out] cComponentName\n        pointer to a null terminated string with the component name.  The\n        names of the components are strings less than 127 bytes in length\n        plus the trailing null for a maximum size of 128 bytes.  An example \n        of a valid component name is \"OMX.TI.AUDIO.DSP.MIXER\\0\".  Names are \n        assigned by the vendor, but shall start with \"OMX.\" and then have \n        the Vendor designation next.\n    @param [in] nNameLength\n        number of characters in the cComponentName string.  With all \n        component name strings restricted to less than 128 characters \n        (including the trailing null) it is recomended that the caller\n        provide a input string for the cComponentName of 128 characters.\n    @param [in] nIndex\n        number containing the enumeration index for the component. \n        Multiple calls to OMX_ComponentNameEnum with increasing values\n        of nIndex will enumerate through the component names in the\n        system until OMX_ErrorNoMore is returned.  The value of nIndex\n        is 0 to (N-1), where N is the number of valid installed components\n        in the system.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  When the value of nIndex exceeds the number of \n        components in the system minus 1, OMX_ErrorNoMore will be\n        returned. Otherwise the appropriate OMX error will be returned.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_APIENTRY OMX_ComponentNameEnum(\n    OMX_OUT OMX_STRING cComponentName,\n    OMX_IN  OMX_U32 nNameLength,\n    OMX_IN  OMX_U32 nIndex);\n\n\n/** The OMX_GetHandle method will locate the component specified by the\n    component name given, load that component into memory and then invoke\n    the component's methods to create an instance of the component.  \n    \n    The core should return from this call within 20 msec.\n    \n    @param [out] pHandle\n        pointer to an OMX_HANDLETYPE pointer to be filled in by this method.\n    @param [in] cComponentName\n        pointer to a null terminated string with the component name.  The\n        names of the components are strings less than 127 bytes in length\n        plus the trailing null for a maximum size of 128 bytes.  An example \n        of a valid component name is \"OMX.TI.AUDIO.DSP.MIXER\\0\".  Names are \n        assigned by the vendor, but shall start with \"OMX.\" and then have \n        the Vendor designation next.\n    @param [in] pAppData\n        pointer to an application defined value that will be returned\n        during callbacks so that the application can identify the source\n        of the callback.\n    @param [in] pCallBacks\n        pointer to a OMX_CALLBACKTYPE structure that will be passed to the\n        component to initialize it with.  \n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_APIENTRY OMX_GetHandle(\n    OMX_OUT OMX_HANDLETYPE* pHandle, \n    OMX_IN  OMX_STRING cComponentName,\n    OMX_IN  OMX_PTR pAppData,\n    OMX_IN  OMX_CALLBACKTYPE* pCallBacks);\n\n\n/** The OMX_FreeHandle method will free a handle allocated by the OMX_GetHandle \n    method.  If the component reference count goes to zero, the component will\n    be unloaded from memory.  \n    \n    The core should return from this call within 20 msec when the component is \n    in the OMX_StateLoaded state.\n\n    @param [in] hComponent\n        Handle of the component to be accessed.  This is the component\n        handle returned by the call to the GetHandle function.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_APIENTRY OMX_FreeHandle(\n    OMX_IN  OMX_HANDLETYPE hComponent);\n\n\n\n/** The OMX_SetupTunnel method will handle the necessary calls to the components\n    to setup the specified tunnel the two components.  NOTE: This is\n    an actual method (not a #define macro).  This method will make calls into\n    the component ComponentTunnelRequest method to do the actual tunnel \n    connection.  \n\n    The ComponentTunnelRequest method on both components will be called. \n    This method shall not be called unless the component is in the \n    OMX_StateLoaded state except when the ports used for the tunnel are\n    disabled. In this case, the component may be in the OMX_StateExecuting,\n    OMX_StatePause, or OMX_StateIdle states. \n\n    The core should return from this call within 20 msec.\n    \n    @param [in] hOutput\n        Handle of the component to be accessed.  Also this is the handle\n        of the component whose port, specified in the nPortOutput parameter\n        will be used the source for the tunnel. This is the component handle\n        returned by the call to the OMX_GetHandle function.  There is a \n        requirement that hOutput be the source for the data when\n        tunelling (i.e. nPortOutput is an output port).  If 0x0, the component\n        specified in hInput will have it's port specified in nPortInput\n        setup for communication with the application / IL client.\n    @param [in] nPortOutput\n        nPortOutput is used to select the source port on component to be\n        used in the tunnel. \n    @param [in] hInput\n        This is the component to setup the tunnel with. This is the handle\n        of the component whose port, specified in the nPortInput parameter\n        will be used the destination for the tunnel. This is the component handle\n        returned by the call to the OMX_GetHandle function.  There is a \n        requirement that hInput be the destination for the data when\n        tunelling (i.e. nPortInut is an input port).   If 0x0, the component\n        specified in hOutput will have it's port specified in nPortPOutput\n        setup for communication with the application / IL client.\n    @param [in] nPortInput\n        nPortInput is used to select the destination port on component to be\n        used in the tunnel.\n    @return OMX_ERRORTYPE\n        If the command successfully executes, the return code will be\n        OMX_ErrorNone.  Otherwise the appropriate OMX error will be returned.\n        When OMX_ErrorNotImplemented is returned, one or both components is \n        a non-interop component and does not support tunneling.\n        \n        On failure, the ports of both components are setup for communication\n        with the application / IL Client.\n    @ingroup core tun\n */\nOMX_API OMX_ERRORTYPE OMX_APIENTRY OMX_SetupTunnel(\n    OMX_IN  OMX_HANDLETYPE hOutput,\n    OMX_IN  OMX_U32 nPortOutput,\n    OMX_IN  OMX_HANDLETYPE hInput,\n    OMX_IN  OMX_U32 nPortInput);\n    \n/** @ingroup cp */\nOMX_API OMX_ERRORTYPE   OMX_GetContentPipe(\n    OMX_OUT OMX_HANDLETYPE *hPipe,\n    OMX_IN OMX_STRING szURI);\n\n/** The OMX_GetComponentsOfRole method will return the number of components that support the given\n    role and (if the compNames field is non-NULL) the names of those components. The call will fail if \n    an insufficiently sized array of names is supplied. To ensure the array is sufficiently sized the\n    client should:\n        * first call this function with the compNames field NULL to determine the number of component names\n        * second call this function with the compNames field pointing to an array of names allocated \n          according to the number returned by the first call.\n\n    The core should return from this call within 5 msec.\n    \n    @param [in] role\n        This is generic standard component name consisting only of component class \n        name and the type within that class (e.g. 'audio_decoder.aac').\n    @param [inout] pNumComps\n        This is used both as input and output. \n \n        If compNames is NULL, the input is ignored and the output specifies how many components support\n        the given role.\n     \n        If compNames is not NULL, on input it bounds the size of the input structure and \n        on output, it specifies the number of components string names listed within the compNames parameter.\n    @param [inout] compNames\n        If NULL this field is ignored. If non-NULL this points to an array of 128-byte strings which accepts \n        a list of the names of all physical components that implement the specified standard component name. \n        Each name is NULL terminated. numComps indicates the number of names.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_GetComponentsOfRole ( \n\tOMX_IN      OMX_STRING role,\n    OMX_INOUT   OMX_U32 *pNumComps,\n    OMX_INOUT   OMX_U8  **compNames);\n\n/** The OMX_GetRolesOfComponent method will return the number of roles supported by the given\n    component and (if the roles field is non-NULL) the names of those roles. The call will fail if \n    an insufficiently sized array of names is supplied. To ensure the array is sufficiently sized the\n    client should:\n        * first call this function with the roles field NULL to determine the number of role names\n        * second call this function with the roles field pointing to an array of names allocated \n          according to the number returned by the first call.\n\n    The core should return from this call within 5 msec.\n\n    @param [in] compName\n        This is the name of the component being queried about.\n    @param [inout] pNumRoles\n        This is used both as input and output. \n \n        If roles is NULL, the input is ignored and the output specifies how many roles the component supports.\n     \n        If compNames is not NULL, on input it bounds the size of the input structure and \n        on output, it specifies the number of roles string names listed within the roles parameter.\n    @param [out] roles\n        If NULL this field is ignored. If non-NULL this points to an array of 128-byte strings \n        which accepts a list of the names of all standard components roles implemented on the \n        specified component name. numComps indicates the number of names.\n    @ingroup core\n */\nOMX_API OMX_ERRORTYPE OMX_GetRolesOfComponent ( \n\tOMX_IN      OMX_STRING compName, \n    OMX_INOUT   OMX_U32 *pNumRoles,\n    OMX_OUT     OMX_U8 **roles);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_CoreExt.h",
    "content": "/*\n * Copyright (c) 2009 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions:\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n\n/** OMX_CoreExt.h - OpenMax IL version 1.1.2\n * The OMX_CoreExt header file contains extensions to the definitions used\n * by both the application and the component to access common items.\n */\n\n#ifndef OMX_CoreExt_h\n#define OMX_CoreExt_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/* Each OMX header shall include all required header files to allow the\n * header to compile without errors.  The includes below are required\n * for this header file to compile successfully\n */\n#include <OMX_Core.h>\n\n\n/** Event type extensions. */\ntypedef enum OMX_EVENTEXTTYPE\n{\n    OMX_EventIndexSettingChanged = OMX_EventKhronosExtensions, /**< component signals the IL client of a change\n                                                                    in a param, config, or extension */\n    OMX_EventExtMax = 0x7FFFFFFF\n} OMX_EVENTEXTTYPE;\n\n\n/** Enable or disable a callback event. */\ntypedef struct OMX_CONFIG_CALLBACKREQUESTTYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< port that this structure applies to */\n    OMX_INDEXTYPE nIndex;       /**< the index the callback is requested for */\n    OMX_BOOL bEnable;           /**< enable (OMX_TRUE) or disable (OMX_FALSE) the callback */\n} OMX_CONFIG_CALLBACKREQUESTTYPE;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* OMX_CoreExt_h */\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_IVCommon.h",
    "content": "/**\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** \n * @file OMX_IVCommon.h - OpenMax IL version 1.1.2\n *  The structures needed by Video and Image components to exchange\n *  parameters and configuration data with the components.\n */\n#ifndef OMX_IVCommon_h\n#define OMX_IVCommon_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * Each OMX header must include all required header files to allow the header\n * to compile without errors.  The includes below are required for this header\n * file to compile successfully \n */\n\n#include <OMX_Core.h>\n\n/** @defgroup iv OpenMAX IL Imaging and Video Domain\n * Common structures for OpenMAX IL Imaging and Video domains\n * @{\n */\n\n\n/** \n * Enumeration defining possible uncompressed image/video formats. \n *\n * ENUMS:\n *  Unused                 : Placeholder value when format is N/A\n *  Monochrome             : black and white\n *  8bitRGB332             : Red 7:5, Green 4:2, Blue 1:0\n *  12bitRGB444            : Red 11:8, Green 7:4, Blue 3:0\n *  16bitARGB4444          : Alpha 15:12, Red 11:8, Green 7:4, Blue 3:0\n *  16bitARGB1555          : Alpha 15, Red 14:10, Green 9:5, Blue 4:0\n *  16bitRGB565            : Red 15:11, Green 10:5, Blue 4:0\n *  16bitBGR565            : Blue 15:11, Green 10:5, Red 4:0\n *  18bitRGB666            : Red 17:12, Green 11:6, Blue 5:0\n *  18bitARGB1665          : Alpha 17, Red 16:11, Green 10:5, Blue 4:0\n *  19bitARGB1666          : Alpha 18, Red 17:12, Green 11:6, Blue 5:0\n *  24bitRGB888            : Red 24:16, Green 15:8, Blue 7:0\n *  24bitBGR888            : Blue 24:16, Green 15:8, Red 7:0\n *  24bitARGB1887          : Alpha 23, Red 22:15, Green 14:7, Blue 6:0\n *  25bitARGB1888          : Alpha 24, Red 23:16, Green 15:8, Blue 7:0\n *  32bitBGRA8888          : Blue 31:24, Green 23:16, Red 15:8, Alpha 7:0\n *  32bitARGB8888          : Alpha 31:24, Red 23:16, Green 15:8, Blue 7:0\n *  YUV411Planar           : U,Y are subsampled by a factor of 4 horizontally\n *  YUV411PackedPlanar     : packed per payload in planar slices\n *  YUV420Planar           : Three arrays Y,U,V.\n *  YUV420PackedPlanar     : packed per payload in planar slices\n *  YUV420SemiPlanar       : Two arrays, one is all Y, the other is U and V\n *  YUV422Planar           : Three arrays Y,U,V.\n *  YUV422PackedPlanar     : packed per payload in planar slices\n *  YUV422SemiPlanar       : Two arrays, one is all Y, the other is U and V\n *  YCbYCr                 : Organized as 16bit YUYV (i.e. YCbYCr)\n *  YCrYCb                 : Organized as 16bit YVYU (i.e. YCrYCb)\n *  CbYCrY                 : Organized as 16bit UYVY (i.e. CbYCrY)\n *  CrYCbY                 : Organized as 16bit VYUY (i.e. CrYCbY)\n *  YUV444Interleaved      : Each pixel contains equal parts YUV\n *  RawBayer8bit           : SMIA camera output format\n *  RawBayer10bit          : SMIA camera output format\n *  RawBayer8bitcompressed : SMIA camera output format\n */\ntypedef enum OMX_COLOR_FORMATTYPE {\n    OMX_COLOR_FormatUnused,\n    OMX_COLOR_FormatMonochrome,\n    OMX_COLOR_Format8bitRGB332,\n    OMX_COLOR_Format12bitRGB444,\n    OMX_COLOR_Format16bitARGB4444,\n    OMX_COLOR_Format16bitARGB1555,\n    OMX_COLOR_Format16bitRGB565,\n    OMX_COLOR_Format16bitBGR565,\n    OMX_COLOR_Format18bitRGB666,\n    OMX_COLOR_Format18bitARGB1665,\n    OMX_COLOR_Format19bitARGB1666, \n    OMX_COLOR_Format24bitRGB888,\n    OMX_COLOR_Format24bitBGR888,\n    OMX_COLOR_Format24bitARGB1887,\n    OMX_COLOR_Format25bitARGB1888,\n    OMX_COLOR_Format32bitBGRA8888,\n    OMX_COLOR_Format32bitARGB8888,\n    OMX_COLOR_FormatYUV411Planar,\n    OMX_COLOR_FormatYUV411PackedPlanar,\n    OMX_COLOR_FormatYUV420Planar,\n    OMX_COLOR_FormatYUV420PackedPlanar,\n    OMX_COLOR_FormatYUV420SemiPlanar,\n    OMX_COLOR_FormatYUV422Planar,\n    OMX_COLOR_FormatYUV422PackedPlanar,\n    OMX_COLOR_FormatYUV422SemiPlanar,\n    OMX_COLOR_FormatYCbYCr,\n    OMX_COLOR_FormatYCrYCb,\n    OMX_COLOR_FormatCbYCrY,\n    OMX_COLOR_FormatCrYCbY,\n    OMX_COLOR_FormatYUV444Interleaved,\n    OMX_COLOR_FormatRawBayer8bit,\n    OMX_COLOR_FormatRawBayer10bit,\n    OMX_COLOR_FormatRawBayer8bitcompressed,\n    OMX_COLOR_FormatL2, \n    OMX_COLOR_FormatL4, \n    OMX_COLOR_FormatL8, \n    OMX_COLOR_FormatL16, \n    OMX_COLOR_FormatL24, \n    OMX_COLOR_FormatL32,\n    OMX_COLOR_FormatYUV420PackedSemiPlanar,\n    OMX_COLOR_FormatYUV422PackedSemiPlanar,\n    OMX_COLOR_Format18BitBGR666,\n    OMX_COLOR_Format24BitARGB6666,\n    OMX_COLOR_Format24BitABGR6666,\n    OMX_COLOR_FormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_COLOR_FormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    /**<Reserved android opaque colorformat. Tells the encoder that\n     * the actual colorformat will be  relayed by the\n     * Gralloc Buffers.\n     * FIXME: In the process of reserving some enum values for\n     * Android-specific OMX IL colorformats. Change this enum to\n     * an acceptable range once that is done.\n     * */\n    OMX_COLOR_FormatAndroidOpaque = 0x7F000789,\n    OMX_TI_COLOR_FormatYUV420PackedSemiPlanar = 0x7F000100,\n    OMX_QCOM_COLOR_FormatYVU420SemiPlanar = 0x7FA30C00,\n    OMX_QCOM_COLOR_FormatYUV420PackedSemiPlanar64x32Tile2m8ka = 0x7FA30C03,\n    OMX_SEC_COLOR_FormatNV12Tiled = 0x7FC00002,\n    OMX_QCOM_COLOR_FormatYUV420PackedSemiPlanar32m = 0x7FA30C04,\n    OMX_COLOR_FormatMax = 0x7FFFFFFF\n} OMX_COLOR_FORMATTYPE;\n\n\n/** \n * Defines the matrix for conversion from RGB to YUV or vice versa.\n * iColorMatrix should be initialized with the fixed point values \n * used in converting between formats.\n */\ntypedef struct OMX_CONFIG_COLORCONVERSIONTYPE {\n    OMX_U32 nSize;              /**< Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version info */ \n    OMX_U32 nPortIndex;         /**< Port that this struct applies to */\n    OMX_S32 xColorMatrix[3][3]; /**< Stored in signed Q16 format */\n    OMX_S32 xColorOffset[4];    /**< Stored in signed Q16 format */\n}OMX_CONFIG_COLORCONVERSIONTYPE;\n\n\n/** \n * Structure defining percent to scale each frame dimension.  For example:  \n * To make the width 50% larger, use fWidth = 1.5 and to make the width\n * 1/2 the original size, use fWidth = 0.5\n */\ntypedef struct OMX_CONFIG_SCALEFACTORTYPE {\n    OMX_U32 nSize;            /**< Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version info */ \n    OMX_U32 nPortIndex;       /**< Port that this struct applies to */\n    OMX_S32 xWidth;           /**< Fixed point value stored as Q16 */\n    OMX_S32 xHeight;          /**< Fixed point value stored as Q16 */\n}OMX_CONFIG_SCALEFACTORTYPE;\n\n\n/** \n * Enumeration of possible image filter types \n */\ntypedef enum OMX_IMAGEFILTERTYPE {\n    OMX_ImageFilterNone,\n    OMX_ImageFilterNoise,\n    OMX_ImageFilterEmboss,\n    OMX_ImageFilterNegative,\n    OMX_ImageFilterSketch,\n    OMX_ImageFilterOilPaint,\n    OMX_ImageFilterHatch,\n    OMX_ImageFilterGpen,\n    OMX_ImageFilterAntialias, \n    OMX_ImageFilterDeRing,       \n    OMX_ImageFilterSolarize,\n    OMX_ImageFilterKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_ImageFilterVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_ImageFilterMax = 0x7FFFFFFF\n} OMX_IMAGEFILTERTYPE;\n\n\n/** \n * Image filter configuration \n *\n * STRUCT MEMBERS:\n *  nSize        : Size of the structure in bytes       \n *  nVersion     : OMX specification version information\n *  nPortIndex   : Port that this structure applies to \n *  eImageFilter : Image filter type enumeration      \n */\ntypedef struct OMX_CONFIG_IMAGEFILTERTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_IMAGEFILTERTYPE eImageFilter;\n} OMX_CONFIG_IMAGEFILTERTYPE;\n\n\n/** \n * Customized U and V for color enhancement \n *\n * STRUCT MEMBERS:\n *  nSize             : Size of the structure in bytes\n *  nVersion          : OMX specification version information \n *  nPortIndex        : Port that this structure applies to\n *  bColorEnhancement : Enable/disable color enhancement\n *  nCustomizedU      : Practical values: 16-240, range: 0-255, value set for \n *                      U component\n *  nCustomizedV      : Practical values: 16-240, range: 0-255, value set for \n *                      V component\n */\ntypedef struct OMX_CONFIG_COLORENHANCEMENTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion; \n    OMX_U32 nPortIndex;\n    OMX_BOOL bColorEnhancement;\n    OMX_U8 nCustomizedU;\n    OMX_U8 nCustomizedV;\n} OMX_CONFIG_COLORENHANCEMENTTYPE;\n\n\n/** \n * Define color key and color key mask \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information \n *  nPortIndex : Port that this structure applies to\n *  nARGBColor : 32bit Alpha, Red, Green, Blue Color\n *  nARGBMask  : 32bit Mask for Alpha, Red, Green, Blue channels\n */\ntypedef struct OMX_CONFIG_COLORKEYTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nARGBColor;\n    OMX_U32 nARGBMask;\n} OMX_CONFIG_COLORKEYTYPE;\n\n\n/** \n * List of color blend types for pre/post processing \n *\n * ENUMS:\n *  None          : No color blending present\n *  AlphaConstant : Function is (alpha_constant * src) + \n *                  (1 - alpha_constant) * dst)\n *  AlphaPerPixel : Function is (alpha * src) + (1 - alpha) * dst)\n *  Alternate     : Function is alternating pixels from src and dst\n *  And           : Function is (src & dst)\n *  Or            : Function is (src | dst)\n *  Invert        : Function is ~src\n */\ntypedef enum OMX_COLORBLENDTYPE {\n    OMX_ColorBlendNone,\n    OMX_ColorBlendAlphaConstant,\n    OMX_ColorBlendAlphaPerPixel,\n    OMX_ColorBlendAlternate,\n    OMX_ColorBlendAnd,\n    OMX_ColorBlendOr,\n    OMX_ColorBlendInvert,\n    OMX_ColorBlendKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_ColorBlendVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_ColorBlendMax = 0x7FFFFFFF\n} OMX_COLORBLENDTYPE;\n\n\n/** \n * Color blend configuration \n *\n * STRUCT MEMBERS:\n *  nSize             : Size of the structure in bytes                        \n *  nVersion          : OMX specification version information                \n *  nPortIndex        : Port that this structure applies to                   \n *  nRGBAlphaConstant : Constant global alpha values when global alpha is used\n *  eColorBlend       : Color blend type enumeration                         \n */\ntypedef struct OMX_CONFIG_COLORBLENDTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nRGBAlphaConstant;\n    OMX_COLORBLENDTYPE  eColorBlend;\n} OMX_CONFIG_COLORBLENDTYPE;\n\n\n/** \n * Hold frame dimension\n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes      \n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to     \n *  nWidth     : Frame width in pixels                 \n *  nHeight    : Frame height in pixels                \n */\ntypedef struct OMX_FRAMESIZETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nWidth;\n    OMX_U32 nHeight;\n} OMX_FRAMESIZETYPE;\n\n\n/**\n * Rotation configuration \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes             \n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nRotation  : +/- integer rotation value               \n */\ntypedef struct OMX_CONFIG_ROTATIONTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nRotation; \n} OMX_CONFIG_ROTATIONTYPE;\n\n\n/** \n * Possible mirroring directions for pre/post processing \n *\n * ENUMS:\n *  None       : No mirroring                         \n *  Vertical   : Vertical mirroring, flip on X axis   \n *  Horizontal : Horizontal mirroring, flip on Y axis  \n *  Both       : Both vertical and horizontal mirroring\n */\ntypedef enum OMX_MIRRORTYPE {\n    OMX_MirrorNone = 0,\n    OMX_MirrorVertical,\n    OMX_MirrorHorizontal,\n    OMX_MirrorBoth, \n    OMX_MirrorKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_MirrorVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_MirrorMax = 0x7FFFFFFF   \n} OMX_MIRRORTYPE;\n\n\n/** \n * Mirroring configuration \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes      \n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to  \n *  eMirror    : Mirror type enumeration              \n */\ntypedef struct OMX_CONFIG_MIRRORTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion; \n    OMX_U32 nPortIndex;\n    OMX_MIRRORTYPE  eMirror;\n} OMX_CONFIG_MIRRORTYPE;\n\n\n/** \n * Position information only \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes               \n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nX         : X coordinate for the point                     \n *  nY         : Y coordinate for the point \n */                      \ntypedef struct OMX_CONFIG_POINTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nX;\n    OMX_S32 nY;\n} OMX_CONFIG_POINTTYPE;\n\n\n/** \n * Frame size plus position \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes                    \n *  nVersion   : OMX specification version information      \n *  nPortIndex : Port that this structure applies to    \n *  nLeft      : X Coordinate of the top left corner of the rectangle\n *  nTop       : Y Coordinate of the top left corner of the rectangle\n *  nWidth     : Width of the rectangle                              \n *  nHeight    : Height of the rectangle                             \n */\ntypedef struct OMX_CONFIG_RECTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;  \n    OMX_U32 nPortIndex; \n    OMX_S32 nLeft; \n    OMX_S32 nTop;\n    OMX_U32 nWidth;\n    OMX_U32 nHeight;\n} OMX_CONFIG_RECTTYPE;\n\n\n/** \n * Deblocking state; it is required to be set up before starting the codec \n *\n * STRUCT MEMBERS:\n *  nSize       : Size of the structure in bytes      \n *  nVersion    : OMX specification version information \n *  nPortIndex  : Port that this structure applies to\n *  bDeblocking : Enable/disable deblocking mode    \n */\ntypedef struct OMX_PARAM_DEBLOCKINGTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bDeblocking;\n} OMX_PARAM_DEBLOCKINGTYPE;\n\n\n/** \n * Stabilization state \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes          \n *  nVersion   : OMX specification version information    \n *  nPortIndex : Port that this structure applies to   \n *  bStab      : Enable/disable frame stabilization state\n */\ntypedef struct OMX_CONFIG_FRAMESTABTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bStab;\n} OMX_CONFIG_FRAMESTABTYPE;\n\n\n/** \n * White Balance control type \n *\n * STRUCT MEMBERS:\n *  SunLight : Referenced in JSR-234\n *  Flash    : Optimal for device's integrated flash\n */\ntypedef enum OMX_WHITEBALCONTROLTYPE {\n    OMX_WhiteBalControlOff = 0,\n    OMX_WhiteBalControlAuto,\n    OMX_WhiteBalControlSunLight,\n    OMX_WhiteBalControlCloudy,\n    OMX_WhiteBalControlShade,\n    OMX_WhiteBalControlTungsten,\n    OMX_WhiteBalControlFluorescent,\n    OMX_WhiteBalControlIncandescent,\n    OMX_WhiteBalControlFlash,\n    OMX_WhiteBalControlHorizon,\n    OMX_WhiteBalControlKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_WhiteBalControlVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_WhiteBalControlMax = 0x7FFFFFFF\n} OMX_WHITEBALCONTROLTYPE;\n\n\n/** \n * White Balance control configuration \n *\n * STRUCT MEMBERS:\n *  nSize            : Size of the structure in bytes       \n *  nVersion         : OMX specification version information\n *  nPortIndex       : Port that this structure applies to                 \n *  eWhiteBalControl : White balance enumeration            \n */\ntypedef struct OMX_CONFIG_WHITEBALCONTROLTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_WHITEBALCONTROLTYPE eWhiteBalControl;\n} OMX_CONFIG_WHITEBALCONTROLTYPE;\n\n\n/** \n * Exposure control type \n */\ntypedef enum OMX_EXPOSURECONTROLTYPE {\n    OMX_ExposureControlOff = 0,\n    OMX_ExposureControlAuto,\n    OMX_ExposureControlNight,\n    OMX_ExposureControlBackLight,\n    OMX_ExposureControlSpotLight,\n    OMX_ExposureControlSports,\n    OMX_ExposureControlSnow,\n    OMX_ExposureControlBeach,\n    OMX_ExposureControlLargeAperture,\n    OMX_ExposureControlSmallApperture,\n    OMX_ExposureControlKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_ExposureControlVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_ExposureControlMax = 0x7FFFFFFF\n} OMX_EXPOSURECONTROLTYPE;\n\n\n/** \n * White Balance control configuration \n *\n * STRUCT MEMBERS:\n *  nSize            : Size of the structure in bytes      \n *  nVersion         : OMX specification version information\n *  nPortIndex       : Port that this structure applies to                \n *  eExposureControl : Exposure control enumeration         \n */\ntypedef struct OMX_CONFIG_EXPOSURECONTROLTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_EXPOSURECONTROLTYPE eExposureControl;\n} OMX_CONFIG_EXPOSURECONTROLTYPE;\n\n\n/** \n * Defines sensor supported mode. \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes           \n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to \n *  nFrameRate : Single shot mode is indicated by a 0     \n *  bOneShot   : Enable for single shot, disable for streaming\n *  sFrameSize : Framesize                                          \n */\ntypedef struct OMX_PARAM_SENSORMODETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nFrameRate;\n    OMX_BOOL bOneShot;\n    OMX_FRAMESIZETYPE sFrameSize;\n} OMX_PARAM_SENSORMODETYPE;\n\n\n/** \n * Defines contrast level \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes                              \n *  nVersion   : OMX specification version information                \n *  nPortIndex : Port that this structure applies to                 \n *  nContrast  : Values allowed for contrast -100 to 100, zero means no change\n */\ntypedef struct OMX_CONFIG_CONTRASTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nContrast;\n} OMX_CONFIG_CONTRASTTYPE;\n\n\n/** \n * Defines brightness level \n *\n * STRUCT MEMBERS:\n *  nSize       : Size of the structure in bytes          \n *  nVersion    : OMX specification version information \n *  nPortIndex  : Port that this structure applies to \n *  nBrightness : 0-100%        \n */\ntypedef struct OMX_CONFIG_BRIGHTNESSTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nBrightness;\n} OMX_CONFIG_BRIGHTNESSTYPE;\n\n\n/** \n * Defines backlight level configuration for a video sink, e.g. LCD panel \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information \n *  nPortIndex : Port that this structure applies to\n *  nBacklight : Values allowed for backlight 0-100%\n *  nTimeout   : Number of milliseconds before backlight automatically turns \n *               off.  A value of 0x0 disables backight timeout \n */\ntypedef struct OMX_CONFIG_BACKLIGHTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nBacklight;\n    OMX_U32 nTimeout;\n} OMX_CONFIG_BACKLIGHTTYPE;\n\n\n/** \n * Defines setting for Gamma \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information \n *  nPortIndex : Port that this structure applies to\n *  nGamma     : Values allowed for gamma -100 to 100, zero means no change\n */\ntypedef struct OMX_CONFIG_GAMMATYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nGamma;\n} OMX_CONFIG_GAMMATYPE;\n\n\n/** \n * Define for setting saturation \n * \n * STRUCT MEMBERS:\n *  nSize       : Size of the structure in bytes\n *  nVersion    : OMX specification version information\n *  nPortIndex  : Port that this structure applies to\n *  nSaturation : Values allowed for saturation -100 to 100, zero means \n *                no change\n */\ntypedef struct OMX_CONFIG_SATURATIONTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nSaturation;\n} OMX_CONFIG_SATURATIONTYPE;\n\n\n/** \n * Define for setting Lightness \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nLightness : Values allowed for lightness -100 to 100, zero means no \n *               change\n */\ntypedef struct OMX_CONFIG_LIGHTNESSTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nLightness;\n} OMX_CONFIG_LIGHTNESSTYPE;\n\n\n/** \n * Plane blend configuration \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes \n *  nVersion   : OMX specification version information\n *  nPortIndex : Index of input port associated with the plane.\n *  nDepth     : Depth of the plane in relation to the screen. Higher \n *               numbered depths are \"behind\" lower number depths.  \n *               This number defaults to the Port Index number.\n *  nAlpha     : Transparency blending component for the entire plane.  \n *               See blending modes for more detail.\n */\ntypedef struct OMX_CONFIG_PLANEBLENDTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nDepth;\n    OMX_U32 nAlpha;\n} OMX_CONFIG_PLANEBLENDTYPE;\n\n\n/** \n * Define interlace type\n *\n * STRUCT MEMBERS:\n *  nSize                 : Size of the structure in bytes \n *  nVersion              : OMX specification version information \n *  nPortIndex            : Port that this structure applies to\n *  bEnable               : Enable control variable for this functionality \n *                          (see below)\n *  nInterleavePortIndex  : Index of input or output port associated with  \n *                          the interleaved plane. \n *  pPlanarPortIndexes[4] : Index of input or output planar ports.\n */\ntypedef struct OMX_PARAM_INTERLEAVETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnable;\n    OMX_U32 nInterleavePortIndex;\n} OMX_PARAM_INTERLEAVETYPE;\n\n\n/** \n * Defines the picture effect used for an input picture \n */\ntypedef enum OMX_TRANSITIONEFFECTTYPE {\n    OMX_EffectNone,\n    OMX_EffectFadeFromBlack,\n    OMX_EffectFadeToBlack,\n    OMX_EffectUnspecifiedThroughConstantColor,\n    OMX_EffectDissolve,\n    OMX_EffectWipe,\n    OMX_EffectUnspecifiedMixOfTwoScenes,\n    OMX_EffectKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_EffectVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_EffectMax = 0x7FFFFFFF\n} OMX_TRANSITIONEFFECTTYPE;\n\n\n/** \n * Structure used to configure current transition effect \n *\n * STRUCT MEMBERS:\n * nSize      : Size of the structure in bytes\n * nVersion   : OMX specification version information \n * nPortIndex : Port that this structure applies to\n * eEffect    : Effect to enable\n */\ntypedef struct OMX_CONFIG_TRANSITIONEFFECTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_TRANSITIONEFFECTTYPE eEffect;\n} OMX_CONFIG_TRANSITIONEFFECTTYPE;\n\n\n/** \n * Defines possible data unit types for encoded video data. The data unit \n * types are used both for encoded video input for playback as well as\n * encoded video output from recording. \n */\ntypedef enum OMX_DATAUNITTYPE {\n    OMX_DataUnitCodedPicture,\n    OMX_DataUnitVideoSegment,\n    OMX_DataUnitSeveralSegments,\n    OMX_DataUnitArbitraryStreamSection,\n    OMX_DataUnitKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_DataUnitVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_DataUnitMax = 0x7FFFFFFF\n} OMX_DATAUNITTYPE;\n\n\n/** \n * Defines possible encapsulation types for coded video data unit. The \n * encapsulation information is used both for encoded video input for \n * playback as well as encoded video output from recording. \n */\ntypedef enum OMX_DATAUNITENCAPSULATIONTYPE {\n    OMX_DataEncapsulationElementaryStream,\n    OMX_DataEncapsulationGenericPayload,\n    OMX_DataEncapsulationRtpPayload,\n    OMX_DataEncapsulationKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_DataEncapsulationVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_DataEncapsulationMax = 0x7FFFFFFF\n} OMX_DATAUNITENCAPSULATIONTYPE;\n\n\n/** \n * Structure used to configure the type of being decoded/encoded \n */\ntypedef struct OMX_PARAM_DATAUNITTYPE {\n    OMX_U32 nSize;            /**< Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */ \n    OMX_U32 nPortIndex;       /**< Port that this structure applies to */\n    OMX_DATAUNITTYPE eUnitType;\n    OMX_DATAUNITENCAPSULATIONTYPE eEncapsulationType;\n} OMX_PARAM_DATAUNITTYPE;\n\n\n/**\n * Defines dither types \n */\ntypedef enum OMX_DITHERTYPE {\n    OMX_DitherNone,\n    OMX_DitherOrdered,\n    OMX_DitherErrorDiffusion,\n    OMX_DitherOther,\n    OMX_DitherKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_DitherVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_DitherMax = 0x7FFFFFFF\n} OMX_DITHERTYPE;\n\n\n/** \n * Structure used to configure current type of dithering \n */\ntypedef struct OMX_CONFIG_DITHERTYPE {\n    OMX_U32 nSize;            /**< Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */ \n    OMX_U32 nPortIndex;       /**< Port that this structure applies to */\n    OMX_DITHERTYPE eDither;   /**< Type of dithering to use */\n} OMX_CONFIG_DITHERTYPE;\n\ntypedef struct OMX_CONFIG_CAPTUREMODETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;     /**< Port that this structure applies to */\n    OMX_BOOL bContinuous;   /**< If true then ignore frame rate and emit capture \n                             *   data as fast as possible (otherwise obey port's frame rate). */\n    OMX_BOOL bFrameLimited; /**< If true then terminate capture after the port emits the \n                             *   specified number of frames (otherwise the port does not \n                             *   terminate the capture until instructed to do so by the client). \n                             *   Even if set, the client may manually terminate the capture prior \n                             *   to reaching the limit. */\n    OMX_U32 nFrameLimit;      /**< Limit on number of frames emitted during a capture (only\n                               *   valid if bFrameLimited is set). */\n} OMX_CONFIG_CAPTUREMODETYPE;\n\ntypedef enum OMX_METERINGTYPE {\n \n    OMX_MeteringModeAverage,     /**< Center-weighted average metering. */\n    OMX_MeteringModeSpot,  \t      /**< Spot (partial) metering. */\n    OMX_MeteringModeMatrix,      /**< Matrix or evaluative metering. */\n \n    OMX_MeteringKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_MeteringVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_EVModeMax = 0x7fffffff\n} OMX_METERINGTYPE;\n \ntypedef struct OMX_CONFIG_EXPOSUREVALUETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_METERINGTYPE eMetering;\n    OMX_S32 xEVCompensation;      /**< Fixed point value stored as Q16 */\n    OMX_U32 nApertureFNumber;     /**< e.g. nApertureFNumber = 2 implies \"f/2\" - Q16 format */\n    OMX_BOOL bAutoAperture;\t\t/**< Whether aperture number is defined automatically */\n    OMX_U32 nShutterSpeedMsec;    /**< Shutterspeed in milliseconds */ \n    OMX_BOOL bAutoShutterSpeed;\t/**< Whether shutter speed is defined automatically */ \n    OMX_U32 nSensitivity;         /**< e.g. nSensitivity = 100 implies \"ISO 100\" */\n    OMX_BOOL bAutoSensitivity;\t/**< Whether sensitivity is defined automatically */\n} OMX_CONFIG_EXPOSUREVALUETYPE;\n\n/** \n * Focus region configuration \n *\n * STRUCT MEMBERS:\n *  nSize           : Size of the structure in bytes\n *  nVersion        : OMX specification version information\n *  nPortIndex      : Port that this structure applies to\n *  bCenter         : Use center region as focus region of interest\n *  bLeft           : Use left region as focus region of interest\n *  bRight          : Use right region as focus region of interest\n *  bTop            : Use top region as focus region of interest\n *  bBottom         : Use bottom region as focus region of interest\n *  bTopLeft        : Use top left region as focus region of interest\n *  bTopRight       : Use top right region as focus region of interest\n *  bBottomLeft     : Use bottom left region as focus region of interest\n *  bBottomRight    : Use bottom right region as focus region of interest\n */\ntypedef struct OMX_CONFIG_FOCUSREGIONTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bCenter;\n    OMX_BOOL bLeft;\n    OMX_BOOL bRight;\n    OMX_BOOL bTop;\n    OMX_BOOL bBottom;\n    OMX_BOOL bTopLeft;\n    OMX_BOOL bTopRight;\n    OMX_BOOL bBottomLeft;\n    OMX_BOOL bBottomRight;\n} OMX_CONFIG_FOCUSREGIONTYPE;\n\n/** \n * Focus Status type \n */\ntypedef enum OMX_FOCUSSTATUSTYPE {\n    OMX_FocusStatusOff = 0,\n    OMX_FocusStatusRequest,\n    OMX_FocusStatusReached,\n    OMX_FocusStatusUnableToReach,\n    OMX_FocusStatusLost,\n    OMX_FocusStatusKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_FocusStatusVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_FocusStatusMax = 0x7FFFFFFF\n} OMX_FOCUSSTATUSTYPE;\n\n/** \n * Focus status configuration \n *\n * STRUCT MEMBERS:\n *  nSize               : Size of the structure in bytes\n *  nVersion            : OMX specification version information\n *  nPortIndex          : Port that this structure applies to\n *  eFocusStatus        : Specifies the focus status\n *  bCenterStatus       : Use center region as focus region of interest\n *  bLeftStatus         : Use left region as focus region of interest\n *  bRightStatus        : Use right region as focus region of interest\n *  bTopStatus          : Use top region as focus region of interest\n *  bBottomStatus       : Use bottom region as focus region of interest\n *  bTopLeftStatus      : Use top left region as focus region of interest\n *  bTopRightStatus     : Use top right region as focus region of interest\n *  bBottomLeftStatus   : Use bottom left region as focus region of interest\n *  bBottomRightStatus  : Use bottom right region as focus region of interest\n */\ntypedef struct OMX_PARAM_FOCUSSTATUSTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_FOCUSSTATUSTYPE eFocusStatus;\n    OMX_BOOL bCenterStatus;\n    OMX_BOOL bLeftStatus;\n    OMX_BOOL bRightStatus;\n    OMX_BOOL bTopStatus;\n    OMX_BOOL bBottomStatus;\n    OMX_BOOL bTopLeftStatus;\n    OMX_BOOL bTopRightStatus;\n    OMX_BOOL bBottomLeftStatus;\n    OMX_BOOL bBottomRightStatus;\n} OMX_PARAM_FOCUSSTATUSTYPE;\n\n/** @} */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Image.h",
    "content": "/**\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n */\n\n/** \n * @file OMX_Image.h - OpenMax IL version 1.1.2\n * The structures needed by Image components to exchange parameters and \n * configuration data with the components.\n */\n#ifndef OMX_Image_h\n#define OMX_Image_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n/**\n * Each OMX header must include all required header files to allow the \n * header to compile without errors.  The includes below are required  \n * for this header file to compile successfully \n */\n\n#include <OMX_IVCommon.h>\n\n/** @defgroup imaging OpenMAX IL Imaging Domain\n * @ingroup iv\n * Structures for OpenMAX IL Imaging domain\n * @{\n */\n\n/** \n * Enumeration used to define the possible image compression coding. \n */\ntypedef enum OMX_IMAGE_CODINGTYPE {\n    OMX_IMAGE_CodingUnused,      /**< Value when format is N/A */\n    OMX_IMAGE_CodingAutoDetect,  /**< Auto detection of image format */\n    OMX_IMAGE_CodingJPEG,        /**< JPEG/JFIF image format */\n    OMX_IMAGE_CodingJPEG2K,      /**< JPEG 2000 image format */\n    OMX_IMAGE_CodingEXIF,        /**< EXIF image format */\n    OMX_IMAGE_CodingTIFF,        /**< TIFF image format */\n    OMX_IMAGE_CodingGIF,         /**< Graphics image format */\n    OMX_IMAGE_CodingPNG,         /**< PNG image format */\n    OMX_IMAGE_CodingLZW,         /**< LZW image format */\n    OMX_IMAGE_CodingBMP,         /**< Windows Bitmap format */\n    OMX_IMAGE_CodingKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_IMAGE_CodingVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_IMAGE_CodingMax = 0x7FFFFFFF\n} OMX_IMAGE_CODINGTYPE;\n\n\n/**\n * Data structure used to define an image path. The number of image paths \n * for input and output will vary by type of the image component.  \n * \n *  Input (aka Source) : Zero Inputs, one Output,\n *  Splitter           : One Input, 2 or more Outputs,\n *  Processing Element : One Input, one output,\n *  Mixer              : 2 or more inputs, one output,\n *  Output (aka Sink)  : One Input, zero outputs.\n * \n * The PortDefinition structure is used to define all of the parameters \n * necessary for the compliant component to setup an input or an output  \n * image path.  If additional vendor specific data is required, it should  \n * be transmitted to the component using the CustomCommand function.   \n * Compliant components will prepopulate this structure with optimal  \n * values during the OMX_GetParameter() command.\n *\n * STRUCT MEMBERS:\n *  cMIMEType             : MIME type of data for the port\n *  pNativeRender         : Platform specific reference for a display if a \n *                          sync, otherwise this field is 0\n *  nFrameWidth           : Width of frame to be used on port if \n *                          uncompressed format is used.  Use 0 for \n *                          unknown, don't care or variable\n *  nFrameHeight          : Height of frame to be used on port if \n *                          uncompressed format is used. Use 0 for \n *                          unknown, don't care or variable\n *  nStride               : Number of bytes per span of an image (i.e. \n *                          indicates the number of bytes to get from\n *                          span N to span N+1, where negative stride \n *                          indicates the image is bottom up\n *  nSliceHeight          : Height used when encoding in slices\n *  bFlagErrorConcealment : Turns on error concealment if it is supported by \n *                          the OMX component\n *  eCompressionFormat    : Compression format used in this instance of  \n *                          the component. When OMX_IMAGE_CodingUnused is \n *                          specified, eColorFormat is valid\n *  eColorFormat          : Decompressed format used by this component\n *  pNativeWindow         : Platform specific reference for a window object if a \n *                          display sink , otherwise this field is 0x0. \n */\ntypedef struct OMX_IMAGE_PORTDEFINITIONTYPE {\n    OMX_STRING cMIMEType;\n    OMX_NATIVE_DEVICETYPE pNativeRender;\n    OMX_U32 nFrameWidth; \n    OMX_U32 nFrameHeight;\n    OMX_S32 nStride;     \n    OMX_U32 nSliceHeight;\n    OMX_BOOL bFlagErrorConcealment;\n    OMX_IMAGE_CODINGTYPE eCompressionFormat;\n    OMX_COLOR_FORMATTYPE eColorFormat;\n    OMX_NATIVE_WINDOWTYPE pNativeWindow;\n} OMX_IMAGE_PORTDEFINITIONTYPE;\n\n\n/**  \n * Port format parameter.  This structure is used to enumerate the various \n * data input/output format supported by the port.\n * \n * STRUCT MEMBERS:\n *  nSize              : Size of the structure in bytes\n *  nVersion           : OMX specification version information\n *  nPortIndex         : Indicates which port to set\n *  nIndex             : Indicates the enumeration index for the format from \n *                       0x0 to N-1\n *  eCompressionFormat : Compression format used in this instance of the \n *                       component. When OMX_IMAGE_CodingUnused is specified, \n *                       eColorFormat is valid\n *  eColorFormat       : Decompressed format used by this component\n */\ntypedef struct OMX_IMAGE_PARAM_PORTFORMATTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nIndex;\n    OMX_IMAGE_CODINGTYPE eCompressionFormat;\n    OMX_COLOR_FORMATTYPE eColorFormat;\n} OMX_IMAGE_PARAM_PORTFORMATTYPE;\n\n\n/** \n * Flash control type \n *\n * ENUMS\n *  Torch : Flash forced constantly on\n */\ntypedef enum OMX_IMAGE_FLASHCONTROLTYPE {\n    OMX_IMAGE_FlashControlOn = 0,\n    OMX_IMAGE_FlashControlOff,\n    OMX_IMAGE_FlashControlAuto,\n    OMX_IMAGE_FlashControlRedEyeReduction,\n    OMX_IMAGE_FlashControlFillin,\n    OMX_IMAGE_FlashControlTorch,\n    OMX_IMAGE_FlashControlKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_IMAGE_FlashControlVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_IMAGE_FlashControlMax = 0x7FFFFFFF\n} OMX_IMAGE_FLASHCONTROLTYPE;\n\n\n/** \n * Flash control configuration \n *\n * STRUCT MEMBERS:\n *  nSize         : Size of the structure in bytes\n *  nVersion      : OMX specification version information\n *  nPortIndex    : Port that this structure applies to\n *  eFlashControl : Flash control type\n */\ntypedef struct OMX_IMAGE_PARAM_FLASHCONTROLTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_IMAGE_FLASHCONTROLTYPE eFlashControl;\n} OMX_IMAGE_PARAM_FLASHCONTROLTYPE;\n\n\n/** \n * Focus control type \n */\ntypedef enum OMX_IMAGE_FOCUSCONTROLTYPE {\n    OMX_IMAGE_FocusControlOn = 0,\n    OMX_IMAGE_FocusControlOff,\n    OMX_IMAGE_FocusControlAuto,\n    OMX_IMAGE_FocusControlAutoLock,\n    OMX_IMAGE_FocusControlKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_IMAGE_FocusControlVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_IMAGE_FocusControlMax = 0x7FFFFFFF\n} OMX_IMAGE_FOCUSCONTROLTYPE;\n\n \n/** \n * Focus control configuration \n *\n * STRUCT MEMBERS:\n *  nSize           : Size of the structure in bytes\n *  nVersion        : OMX specification version information\n *  nPortIndex      : Port that this structure applies to\n *  eFocusControl   : Focus control\n *  nFocusSteps     : Focus can take on values from 0 mm to infinity. \n *                    Interest is only in number of steps over this range.\n *  nFocusStepIndex : Current focus step index\n */\ntypedef struct OMX_IMAGE_CONFIG_FOCUSCONTROLTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_IMAGE_FOCUSCONTROLTYPE eFocusControl;\n    OMX_U32 nFocusSteps;\n    OMX_U32 nFocusStepIndex;\n} OMX_IMAGE_CONFIG_FOCUSCONTROLTYPE;\n\n\n/** \n * Q Factor for JPEG compression, which controls the tradeoff between image\n * quality and size.  Q Factor provides a more simple means of controlling\n * JPEG compression quality, without directly programming Quantization\n * tables for chroma and luma \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes         \n *  nVersion   : OMX specification version information \n *  nPortIndex : Port that this structure applies to \n *  nQFactor   : JPEG Q factor value in the range of 1-100. A factor of 1 \n *               produces the smallest, worst quality images, and a factor \n *               of 100 produces the largest, best quality images.  A \n *               typical default is 75 for small good quality images               \n */\ntypedef struct OMX_IMAGE_PARAM_QFACTORTYPE {\n    OMX_U32 nSize;            \n    OMX_VERSIONTYPE nVersion; \n    OMX_U32 nPortIndex;       \n    OMX_U32 nQFactor;                                        \n} OMX_IMAGE_PARAM_QFACTORTYPE;\n\n/** \n * Quantization table type \n */\n\ntypedef enum OMX_IMAGE_QUANTIZATIONTABLETYPE {\n    OMX_IMAGE_QuantizationTableLuma = 0,\n    OMX_IMAGE_QuantizationTableChroma,\n    OMX_IMAGE_QuantizationTableChromaCb,\n    OMX_IMAGE_QuantizationTableChromaCr,\n    OMX_IMAGE_QuantizationTableKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_IMAGE_QuantizationTableVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_IMAGE_QuantizationTableMax = 0x7FFFFFFF\n} OMX_IMAGE_QUANTIZATIONTABLETYPE;\n\n/** \n * JPEG quantization tables are used to determine DCT compression for\n * YUV data, as an alternative to specifying Q factor, providing exact \n * control of compression \n *\n * STRUCT MEMBERS:\n *  nSize                   : Size of the structure in bytes\n *  nVersion                : OMX specification version information \n *  nPortIndex              : Port that this structure applies to\n *  eQuantizationTable      : Quantization table type\n *  nQuantizationMatrix[64] : JPEG quantization table of coefficients stored \n *                            in increasing columns then by rows of data (i.e. \n *                            row 1, ... row 8). Quantization values are in \n *                            the range 0-255 and stored in linear order\n *                            (i.e. the component will zig-zag the \n *                            quantization table data if required internally) \n */\ntypedef struct OMX_IMAGE_PARAM_QUANTIZATIONTABLETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_IMAGE_QUANTIZATIONTABLETYPE eQuantizationTable;\n    OMX_U8 nQuantizationMatrix[64];\n} OMX_IMAGE_PARAM_QUANTIZATIONTABLETYPE;\n\n\n/** \n * Huffman table type, the same Huffman table is applied for chroma and \n * luma component \n */\ntypedef enum OMX_IMAGE_HUFFMANTABLETYPE {\n    OMX_IMAGE_HuffmanTableAC = 0,\n    OMX_IMAGE_HuffmanTableDC,\n    OMX_IMAGE_HuffmanTableACLuma,\n    OMX_IMAGE_HuffmanTableACChroma,\n    OMX_IMAGE_HuffmanTableDCLuma,\n    OMX_IMAGE_HuffmanTableDCChroma,\n    OMX_IMAGE_HuffmanTableKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_IMAGE_HuffmanTableVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_IMAGE_HuffmanTableMax = 0x7FFFFFFF\n} OMX_IMAGE_HUFFMANTABLETYPE;\n\n/** \n * JPEG Huffman table \n *\n * STRUCT MEMBERS:\n *  nSize                            : Size of the structure in bytes\n *  nVersion                         : OMX specification version information\n *  nPortIndex                       : Port that this structure applies to\n *  eHuffmanTable                    : Huffman table type\n *  nNumberOfHuffmanCodeOfLength[16] : 0-16, number of Huffman codes of each \n *                                     possible length\n *  nHuffmanTable[256]               : 0-255, the size used for AC and DC \n *                                     HuffmanTable are 16 and 162 \n */\ntypedef struct OMX_IMAGE_PARAM_HUFFMANTTABLETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_IMAGE_HUFFMANTABLETYPE eHuffmanTable;\n    OMX_U8 nNumberOfHuffmanCodeOfLength[16];\n    OMX_U8 nHuffmanTable[256];\n}OMX_IMAGE_PARAM_HUFFMANTTABLETYPE;\n\n/** @} */\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Index.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** @file OMX_Index.h - OpenMax IL version 1.1.2\n *  The OMX_Index header file contains the definitions for both applications\n *  and components .\n */\n\n\n#ifndef OMX_Index_h\n#define OMX_Index_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n/* Each OMX header must include all required header files to allow the\n *  header to compile without errors.  The includes below are required\n *  for this header file to compile successfully \n */\n#include <OMX_Types.h>\n\n\n/** The OMX_INDEXTYPE enumeration is used to select a structure when either\n *  getting or setting parameters and/or configuration data.  Each entry in \n *  this enumeration maps to an OMX specified structure.  When the \n *  OMX_GetParameter, OMX_SetParameter, OMX_GetConfig or OMX_SetConfig methods\n *  are used, the second parameter will always be an entry from this enumeration\n *  and the third entry will be the structure shown in the comments for the entry.\n *  For example, if the application is initializing a cropping function, the \n *  OMX_SetConfig command would have OMX_IndexConfigCommonInputCrop as the second parameter \n *  and would send a pointer to an initialized OMX_RECTTYPE structure as the \n *  third parameter.\n *  \n *  The enumeration entries named with the OMX_Config prefix are sent using\n *  the OMX_SetConfig command and the enumeration entries named with the\n *  OMX_PARAM_ prefix are sent using the OMX_SetParameter command.\n */\ntypedef enum OMX_INDEXTYPE {\n\n    OMX_IndexComponentStartUnused = 0x01000000,\n    OMX_IndexParamPriorityMgmt,             /**< reference: OMX_PRIORITYMGMTTYPE */\n    OMX_IndexParamAudioInit,                /**< reference: OMX_PORT_PARAM_TYPE */\n    OMX_IndexParamImageInit,                /**< reference: OMX_PORT_PARAM_TYPE */\n    OMX_IndexParamVideoInit,                /**< reference: OMX_PORT_PARAM_TYPE */\n    OMX_IndexParamOtherInit,                /**< reference: OMX_PORT_PARAM_TYPE */\n    OMX_IndexParamNumAvailableStreams,      /**< reference: OMX_PARAM_U32TYPE */\n    OMX_IndexParamActiveStream,             /**< reference: OMX_PARAM_U32TYPE */\n    OMX_IndexParamSuspensionPolicy,         /**< reference: OMX_PARAM_SUSPENSIONPOLICYTYPE */\n    OMX_IndexParamComponentSuspended,       /**< reference: OMX_PARAM_SUSPENSIONTYPE */\n    OMX_IndexConfigCapturing,               /**< reference: OMX_CONFIG_BOOLEANTYPE */ \n    OMX_IndexConfigCaptureMode,             /**< reference: OMX_CONFIG_CAPTUREMODETYPE */ \n    OMX_IndexAutoPauseAfterCapture,         /**< reference: OMX_CONFIG_BOOLEANTYPE */ \n    OMX_IndexParamContentURI,               /**< reference: OMX_PARAM_CONTENTURITYPE */\n    OMX_IndexParamCustomContentPipe,        /**< reference: OMX_PARAM_CONTENTPIPETYPE */ \n    OMX_IndexParamDisableResourceConcealment, /**< reference: OMX_RESOURCECONCEALMENTTYPE */\n    OMX_IndexConfigMetadataItemCount,       /**< reference: OMX_CONFIG_METADATAITEMCOUNTTYPE */\n    OMX_IndexConfigContainerNodeCount,      /**< reference: OMX_CONFIG_CONTAINERNODECOUNTTYPE */\n    OMX_IndexConfigMetadataItem,            /**< reference: OMX_CONFIG_METADATAITEMTYPE */\n    OMX_IndexConfigCounterNodeID,           /**< reference: OMX_CONFIG_CONTAINERNODEIDTYPE */\n    OMX_IndexParamMetadataFilterType,       /**< reference: OMX_PARAM_METADATAFILTERTYPE */\n    OMX_IndexParamMetadataKeyFilter,        /**< reference: OMX_PARAM_METADATAFILTERTYPE */\n    OMX_IndexConfigPriorityMgmt,            /**< reference: OMX_PRIORITYMGMTTYPE */\n    OMX_IndexParamStandardComponentRole,    /**< reference: OMX_PARAM_COMPONENTROLETYPE */\n\n    OMX_IndexPortStartUnused = 0x02000000,\n    OMX_IndexParamPortDefinition,           /**< reference: OMX_PARAM_PORTDEFINITIONTYPE */\n    OMX_IndexParamCompBufferSupplier,       /**< reference: OMX_PARAM_BUFFERSUPPLIERTYPE */ \n    OMX_IndexReservedStartUnused = 0x03000000,\n\n    /* Audio parameters and configurations */\n    OMX_IndexAudioStartUnused = 0x04000000,\n    OMX_IndexParamAudioPortFormat,          /**< reference: OMX_AUDIO_PARAM_PORTFORMATTYPE */\n    OMX_IndexParamAudioPcm,                 /**< reference: OMX_AUDIO_PARAM_PCMMODETYPE */\n    OMX_IndexParamAudioAac,                 /**< reference: OMX_AUDIO_PARAM_AACPROFILETYPE */\n    OMX_IndexParamAudioRa,                  /**< reference: OMX_AUDIO_PARAM_RATYPE */\n    OMX_IndexParamAudioMp3,                 /**< reference: OMX_AUDIO_PARAM_MP3TYPE */\n    OMX_IndexParamAudioAdpcm,               /**< reference: OMX_AUDIO_PARAM_ADPCMTYPE */\n    OMX_IndexParamAudioG723,                /**< reference: OMX_AUDIO_PARAM_G723TYPE */\n    OMX_IndexParamAudioG729,                /**< reference: OMX_AUDIO_PARAM_G729TYPE */\n    OMX_IndexParamAudioAmr,                 /**< reference: OMX_AUDIO_PARAM_AMRTYPE */\n    OMX_IndexParamAudioWma,                 /**< reference: OMX_AUDIO_PARAM_WMATYPE */\n    OMX_IndexParamAudioSbc,                 /**< reference: OMX_AUDIO_PARAM_SBCTYPE */\n    OMX_IndexParamAudioMidi,                /**< reference: OMX_AUDIO_PARAM_MIDITYPE */\n    OMX_IndexParamAudioGsm_FR,              /**< reference: OMX_AUDIO_PARAM_GSMFRTYPE */\n    OMX_IndexParamAudioMidiLoadUserSound,   /**< reference: OMX_AUDIO_PARAM_MIDILOADUSERSOUNDTYPE */\n    OMX_IndexParamAudioG726,                /**< reference: OMX_AUDIO_PARAM_G726TYPE */\n    OMX_IndexParamAudioGsm_EFR,             /**< reference: OMX_AUDIO_PARAM_GSMEFRTYPE */\n    OMX_IndexParamAudioGsm_HR,              /**< reference: OMX_AUDIO_PARAM_GSMHRTYPE */\n    OMX_IndexParamAudioPdc_FR,              /**< reference: OMX_AUDIO_PARAM_PDCFRTYPE */\n    OMX_IndexParamAudioPdc_EFR,             /**< reference: OMX_AUDIO_PARAM_PDCEFRTYPE */\n    OMX_IndexParamAudioPdc_HR,              /**< reference: OMX_AUDIO_PARAM_PDCHRTYPE */\n    OMX_IndexParamAudioTdma_FR,             /**< reference: OMX_AUDIO_PARAM_TDMAFRTYPE */\n    OMX_IndexParamAudioTdma_EFR,            /**< reference: OMX_AUDIO_PARAM_TDMAEFRTYPE */\n    OMX_IndexParamAudioQcelp8,              /**< reference: OMX_AUDIO_PARAM_QCELP8TYPE */\n    OMX_IndexParamAudioQcelp13,             /**< reference: OMX_AUDIO_PARAM_QCELP13TYPE */\n    OMX_IndexParamAudioEvrc,                /**< reference: OMX_AUDIO_PARAM_EVRCTYPE */\n    OMX_IndexParamAudioSmv,                 /**< reference: OMX_AUDIO_PARAM_SMVTYPE */\n    OMX_IndexParamAudioVorbis,              /**< reference: OMX_AUDIO_PARAM_VORBISTYPE */\n\n    OMX_IndexConfigAudioMidiImmediateEvent, /**< reference: OMX_AUDIO_CONFIG_MIDIIMMEDIATEEVENTTYPE */\n    OMX_IndexConfigAudioMidiControl,        /**< reference: OMX_AUDIO_CONFIG_MIDICONTROLTYPE */\n    OMX_IndexConfigAudioMidiSoundBankProgram, /**< reference: OMX_AUDIO_CONFIG_MIDISOUNDBANKPROGRAMTYPE */\n    OMX_IndexConfigAudioMidiStatus,         /**< reference: OMX_AUDIO_CONFIG_MIDISTATUSTYPE */\n    OMX_IndexConfigAudioMidiMetaEvent,      /**< reference: OMX_AUDIO_CONFIG_MIDIMETAEVENTTYPE */\n    OMX_IndexConfigAudioMidiMetaEventData,  /**< reference: OMX_AUDIO_CONFIG_MIDIMETAEVENTDATATYPE */\n    OMX_IndexConfigAudioVolume,             /**< reference: OMX_AUDIO_CONFIG_VOLUMETYPE */\n    OMX_IndexConfigAudioBalance,            /**< reference: OMX_AUDIO_CONFIG_BALANCETYPE */\n    OMX_IndexConfigAudioChannelMute,        /**< reference: OMX_AUDIO_CONFIG_CHANNELMUTETYPE */\n    OMX_IndexConfigAudioMute,               /**< reference: OMX_AUDIO_CONFIG_MUTETYPE */\n    OMX_IndexConfigAudioLoudness,           /**< reference: OMX_AUDIO_CONFIG_LOUDNESSTYPE */\n    OMX_IndexConfigAudioEchoCancelation,    /**< reference: OMX_AUDIO_CONFIG_ECHOCANCELATIONTYPE */\n    OMX_IndexConfigAudioNoiseReduction,     /**< reference: OMX_AUDIO_CONFIG_NOISEREDUCTIONTYPE */\n    OMX_IndexConfigAudioBass,               /**< reference: OMX_AUDIO_CONFIG_BASSTYPE */\n    OMX_IndexConfigAudioTreble,             /**< reference: OMX_AUDIO_CONFIG_TREBLETYPE */\n    OMX_IndexConfigAudioStereoWidening,     /**< reference: OMX_AUDIO_CONFIG_STEREOWIDENINGTYPE */\n    OMX_IndexConfigAudioChorus,             /**< reference: OMX_AUDIO_CONFIG_CHORUSTYPE */\n    OMX_IndexConfigAudioEqualizer,          /**< reference: OMX_AUDIO_CONFIG_EQUALIZERTYPE */\n    OMX_IndexConfigAudioReverberation,      /**< reference: OMX_AUDIO_CONFIG_REVERBERATIONTYPE */\n    OMX_IndexConfigAudioChannelVolume,      /**< reference: OMX_AUDIO_CONFIG_CHANNELVOLUMETYPE */\n\n    /* Image specific parameters and configurations */\n    OMX_IndexImageStartUnused = 0x05000000,\n    OMX_IndexParamImagePortFormat,          /**< reference: OMX_IMAGE_PARAM_PORTFORMATTYPE */\n    OMX_IndexParamFlashControl,             /**< reference: OMX_IMAGE_PARAM_FLASHCONTROLTYPE */\n    OMX_IndexConfigFocusControl,            /**< reference: OMX_IMAGE_CONFIG_FOCUSCONTROLTYPE */\n    OMX_IndexParamQFactor,                  /**< reference: OMX_IMAGE_PARAM_QFACTORTYPE */\n    OMX_IndexParamQuantizationTable,        /**< reference: OMX_IMAGE_PARAM_QUANTIZATIONTABLETYPE */\n    OMX_IndexParamHuffmanTable,             /**< reference: OMX_IMAGE_PARAM_HUFFMANTTABLETYPE */\n    OMX_IndexConfigFlashControl,            /**< reference: OMX_IMAGE_PARAM_FLASHCONTROLTYPE */\n\n    /* Video specific parameters and configurations */\n    OMX_IndexVideoStartUnused = 0x06000000,\n    OMX_IndexParamVideoPortFormat,          /**< reference: OMX_VIDEO_PARAM_PORTFORMATTYPE */\n    OMX_IndexParamVideoQuantization,        /**< reference: OMX_VIDEO_PARAM_QUANTIZATIONTYPE */\n    OMX_IndexParamVideoFastUpdate,          /**< reference: OMX_VIDEO_PARAM_VIDEOFASTUPDATETYPE */\n    OMX_IndexParamVideoBitrate,             /**< reference: OMX_VIDEO_PARAM_BITRATETYPE */\n    OMX_IndexParamVideoMotionVector,        /**< reference: OMX_VIDEO_PARAM_MOTIONVECTORTYPE */\n    OMX_IndexParamVideoIntraRefresh,        /**< reference: OMX_VIDEO_PARAM_INTRAREFRESHTYPE */\n    OMX_IndexParamVideoErrorCorrection,     /**< reference: OMX_VIDEO_PARAM_ERRORCORRECTIONTYPE */\n    OMX_IndexParamVideoVBSMC,               /**< reference: OMX_VIDEO_PARAM_VBSMCTYPE */\n    OMX_IndexParamVideoMpeg2,               /**< reference: OMX_VIDEO_PARAM_MPEG2TYPE */\n    OMX_IndexParamVideoMpeg4,               /**< reference: OMX_VIDEO_PARAM_MPEG4TYPE */\n    OMX_IndexParamVideoWmv,                 /**< reference: OMX_VIDEO_PARAM_WMVTYPE */\n    OMX_IndexParamVideoRv,                  /**< reference: OMX_VIDEO_PARAM_RVTYPE */\n    OMX_IndexParamVideoAvc,                 /**< reference: OMX_VIDEO_PARAM_AVCTYPE */\n    OMX_IndexParamVideoH263,                /**< reference: OMX_VIDEO_PARAM_H263TYPE */\n    OMX_IndexParamVideoProfileLevelQuerySupported, /**< reference: OMX_VIDEO_PARAM_PROFILELEVELTYPE */\n    OMX_IndexParamVideoProfileLevelCurrent, /**< reference: OMX_VIDEO_PARAM_PROFILELEVELTYPE */\n    OMX_IndexConfigVideoBitrate,            /**< reference: OMX_VIDEO_CONFIG_BITRATETYPE */\n    OMX_IndexConfigVideoFramerate,          /**< reference: OMX_CONFIG_FRAMERATETYPE */\n    OMX_IndexConfigVideoIntraVOPRefresh,    /**< reference: OMX_CONFIG_INTRAREFRESHVOPTYPE */\n    OMX_IndexConfigVideoIntraMBRefresh,     /**< reference: OMX_CONFIG_MACROBLOCKERRORMAPTYPE */\n    OMX_IndexConfigVideoMBErrorReporting,   /**< reference: OMX_CONFIG_MBERRORREPORTINGTYPE */\n    OMX_IndexParamVideoMacroblocksPerFrame, /**< reference: OMX_PARAM_MACROBLOCKSTYPE */\n    OMX_IndexConfigVideoMacroBlockErrorMap, /**< reference: OMX_CONFIG_MACROBLOCKERRORMAPTYPE */\n    OMX_IndexParamVideoSliceFMO,            /**< reference: OMX_VIDEO_PARAM_AVCSLICEFMO */\n    OMX_IndexConfigVideoAVCIntraPeriod,     /**< reference: OMX_VIDEO_CONFIG_AVCINTRAPERIOD */\n    OMX_IndexConfigVideoNalSize,            /**< reference: OMX_VIDEO_CONFIG_NALSIZE */\n    OMX_IndexConfigCommonDeinterlace,       /**< reference: OMX_VIDEO_CONFIG_DEINTERLACE */\n\n    /* Image & Video common Configurations */\n    OMX_IndexCommonStartUnused = 0x07000000,\n    OMX_IndexParamCommonDeblocking,         /**< reference: OMX_PARAM_DEBLOCKINGTYPE */\n    OMX_IndexParamCommonSensorMode,         /**< reference: OMX_PARAM_SENSORMODETYPE */\n    OMX_IndexParamCommonInterleave,         /**< reference: OMX_PARAM_INTERLEAVETYPE */\n    OMX_IndexConfigCommonColorFormatConversion, /**< reference: OMX_CONFIG_COLORCONVERSIONTYPE */\n    OMX_IndexConfigCommonScale,             /**< reference: OMX_CONFIG_SCALEFACTORTYPE */\n    OMX_IndexConfigCommonImageFilter,       /**< reference: OMX_CONFIG_IMAGEFILTERTYPE */\n    OMX_IndexConfigCommonColorEnhancement,  /**< reference: OMX_CONFIG_COLORENHANCEMENTTYPE */\n    OMX_IndexConfigCommonColorKey,          /**< reference: OMX_CONFIG_COLORKEYTYPE */\n    OMX_IndexConfigCommonColorBlend,        /**< reference: OMX_CONFIG_COLORBLENDTYPE */\n    OMX_IndexConfigCommonFrameStabilisation,/**< reference: OMX_CONFIG_FRAMESTABTYPE */\n    OMX_IndexConfigCommonRotate,            /**< reference: OMX_CONFIG_ROTATIONTYPE */\n    OMX_IndexConfigCommonMirror,            /**< reference: OMX_CONFIG_MIRRORTYPE */\n    OMX_IndexConfigCommonOutputPosition,    /**< reference: OMX_CONFIG_POINTTYPE */\n    OMX_IndexConfigCommonInputCrop,         /**< reference: OMX_CONFIG_RECTTYPE */\n    OMX_IndexConfigCommonOutputCrop,        /**< reference: OMX_CONFIG_RECTTYPE */\n    OMX_IndexConfigCommonDigitalZoom,       /**< reference: OMX_CONFIG_SCALEFACTORTYPE */\n    OMX_IndexConfigCommonOpticalZoom,       /**< reference: OMX_CONFIG_SCALEFACTORTYPE*/\n    OMX_IndexConfigCommonWhiteBalance,      /**< reference: OMX_CONFIG_WHITEBALCONTROLTYPE */\n    OMX_IndexConfigCommonExposure,          /**< reference: OMX_CONFIG_EXPOSURECONTROLTYPE */\n    OMX_IndexConfigCommonContrast,          /**< reference: OMX_CONFIG_CONTRASTTYPE */\n    OMX_IndexConfigCommonBrightness,        /**< reference: OMX_CONFIG_BRIGHTNESSTYPE */\n    OMX_IndexConfigCommonBacklight,         /**< reference: OMX_CONFIG_BACKLIGHTTYPE */\n    OMX_IndexConfigCommonGamma,             /**< reference: OMX_CONFIG_GAMMATYPE */\n    OMX_IndexConfigCommonSaturation,        /**< reference: OMX_CONFIG_SATURATIONTYPE */\n    OMX_IndexConfigCommonLightness,         /**< reference: OMX_CONFIG_LIGHTNESSTYPE */\n    OMX_IndexConfigCommonExclusionRect,     /**< reference: OMX_CONFIG_RECTTYPE */\n    OMX_IndexConfigCommonDithering,         /**< reference: OMX_CONFIG_DITHERTYPE */\n    OMX_IndexConfigCommonPlaneBlend,        /**< reference: OMX_CONFIG_PLANEBLENDTYPE */\n    OMX_IndexConfigCommonExposureValue,     /**< reference: OMX_CONFIG_EXPOSUREVALUETYPE */\n    OMX_IndexConfigCommonOutputSize,        /**< reference: OMX_FRAMESIZETYPE */\n    OMX_IndexParamCommonExtraQuantData,     /**< reference: OMX_OTHER_EXTRADATATYPE */\n    OMX_IndexConfigCommonFocusRegion,       /**< reference: OMX_CONFIG_FOCUSREGIONTYPE */\n    OMX_IndexConfigCommonFocusStatus,       /**< reference: OMX_PARAM_FOCUSSTATUSTYPE */\n    OMX_IndexConfigCommonTransitionEffect,  /**< reference: OMX_CONFIG_TRANSITIONEFFECTTYPE */\n\n    /* Reserved Configuration range */\n    OMX_IndexOtherStartUnused = 0x08000000,\n    OMX_IndexParamOtherPortFormat,          /**< reference: OMX_OTHER_PARAM_PORTFORMATTYPE */\n    OMX_IndexConfigOtherPower,              /**< reference: OMX_OTHER_CONFIG_POWERTYPE */\n    OMX_IndexConfigOtherStats,              /**< reference: OMX_OTHER_CONFIG_STATSTYPE */\n\n\n    /* Reserved Time range */\n    OMX_IndexTimeStartUnused = 0x09000000,\n    OMX_IndexConfigTimeScale,               /**< reference: OMX_TIME_CONFIG_SCALETYPE */\n    OMX_IndexConfigTimeClockState,          /**< reference: OMX_TIME_CONFIG_CLOCKSTATETYPE */\n    OMX_IndexConfigTimeActiveRefClock,      /**< reference: OMX_TIME_CONFIG_ACTIVEREFCLOCKTYPE */\n    OMX_IndexConfigTimeCurrentMediaTime,    /**< reference: OMX_TIME_CONFIG_TIMESTAMPTYPE (read only) */\n    OMX_IndexConfigTimeCurrentWallTime,     /**< reference: OMX_TIME_CONFIG_TIMESTAMPTYPE (read only) */\n    OMX_IndexConfigTimeCurrentAudioReference, /**< reference: OMX_TIME_CONFIG_TIMESTAMPTYPE (write only) */\n    OMX_IndexConfigTimeCurrentVideoReference, /**< reference: OMX_TIME_CONFIG_TIMESTAMPTYPE (write only) */\n    OMX_IndexConfigTimeMediaTimeRequest,    /**< reference: OMX_TIME_CONFIG_MEDIATIMEREQUESTTYPE (write only) */\n    OMX_IndexConfigTimeClientStartTime,     /**<reference:  OMX_TIME_CONFIG_TIMESTAMPTYPE (write only) */\n    OMX_IndexConfigTimePosition,            /**< reference: OMX_TIME_CONFIG_TIMESTAMPTYPE */\n    OMX_IndexConfigTimeSeekMode,            /**< reference: OMX_TIME_CONFIG_SEEKMODETYPE */\n\n\n    OMX_IndexKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    /* Vendor specific area */\n    OMX_IndexVendorStartUnused = 0x7F000000,\n    /* Vendor specific structures should be in the range of 0x7F000000 \n       to 0x7FFFFFFE.  This range is not broken out by vendor, so\n       private indexes are not guaranteed unique and therefore should\n       only be sent to the appropriate component. */\n\n    OMX_IndexMax = 0x7FFFFFFF\n\n} OMX_INDEXTYPE;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_IndexExt.h",
    "content": "/*\n * Copyright (c) 2010 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions:\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n\n/** @file OMX_IndexExt.h - OpenMax IL version 1.1.2\n * The OMX_IndexExt header file contains extensions to the definitions\n * for both applications and components .\n */\n\n#ifndef OMX_IndexExt_h\n#define OMX_IndexExt_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/* Each OMX header shall include all required header files to allow the\n * header to compile without errors.  The includes below are required\n * for this header file to compile successfully\n */\n#include <OMX_Index.h>\n\n\n/** Khronos standard extension indices.\n\nThis enum lists the current Khronos extension indices to OpenMAX IL.\n*/\ntypedef enum OMX_INDEXEXTTYPE {\n\n    /* Component parameters and configurations */\n    OMX_IndexExtComponentStartUnused = OMX_IndexKhronosExtensions + 0x00100000,\n    OMX_IndexConfigCallbackRequest,  /**< reference: OMX_CONFIG_CALLBACKREQUESTTYPE */\n    OMX_IndexConfigCommitMode,                      /**< reference: OMX_CONFIG_COMMITMODETYPE */\n    OMX_IndexConfigCommit,                          /**< reference: OMX_CONFIG_COMMITTYPE */\n\n    /* Port parameters and configurations */\n    OMX_IndexExtPortStartUnused = OMX_IndexKhronosExtensions + 0x00200000,\n\n    /* Audio parameters and configurations */\n    OMX_IndexExtAudioStartUnused = OMX_IndexKhronosExtensions + 0x00400000,\n\n    /* Image parameters and configurations */\n    OMX_IndexExtImageStartUnused = OMX_IndexKhronosExtensions + 0x00500000,\n\n    /* Video parameters and configurations */\n    OMX_IndexExtVideoStartUnused = OMX_IndexKhronosExtensions + 0x00600000,\n    OMX_IndexParamNalStreamFormatSupported,         /**< reference: OMX_NALSTREAMFORMATTYPE */\n    OMX_IndexParamNalStreamFormat,                  /**< reference: OMX_NALSTREAMFORMATTYPE */\n    OMX_IndexParamNalStreamFormatSelect,            /**< reference: OMX_NALSTREAMFORMATTYPE */\n    OMX_IndexParamVideoVp8,                         /**< reference: OMX_VIDEO_PARAM_VP8TYPE */\n    OMX_IndexConfigVideoVp8ReferenceFrame,          /**< reference: OMX_VIDEO_VP8REFERENCEFRAMETYPE */\n    OMX_IndexConfigVideoVp8ReferenceFrameType,      /**< reference: OMX_VIDEO_VP8REFERENCEFRAMEINFOTYPE */\n    OMX_IndexParamVideoReserved,                    /**< Reserved for future index */\n    OMX_IndexParamVideoHevc,                        /**< reference: OMX_VIDEO_PARAM_HEVCTYPE */\n\n    /* Image & Video common configurations */\n    OMX_IndexExtCommonStartUnused = OMX_IndexKhronosExtensions + 0x00700000,\n\n    /* Other configurations */\n    OMX_IndexExtOtherStartUnused = OMX_IndexKhronosExtensions + 0x00800000,\n    OMX_IndexConfigAutoFramerateConversion,         /**< reference: OMX_CONFIG_BOOLEANTYPE */\n    OMX_IndexConfigPriority,                        /**< reference: OMX_PARAM_U32TYPE */\n    OMX_IndexConfigOperatingRate,                   /**< reference: OMX_PARAM_U32TYPE in Q16 format for video and in Hz for audio */\n\n    /* Time configurations */\n    OMX_IndexExtTimeStartUnused = OMX_IndexKhronosExtensions + 0x00900000,\n\n    OMX_IndexExtMax = 0x7FFFFFFF\n} OMX_INDEXEXTTYPE;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* OMX_IndexExt_h */\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Other.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** @file OMX_Other.h - OpenMax IL version 1.1.2\n *  The structures needed by Other components to exchange\n *  parameters and configuration data with the components.\n */\n\n#ifndef OMX_Other_h\n#define OMX_Other_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n/* Each OMX header must include all required header files to allow the\n *  header to compile without errors.  The includes below are required\n *  for this header file to compile successfully \n */\n\n#include <OMX_Core.h>\n\n\n/** \n * Enumeration of possible data types which match to multiple domains or no\n * domain at all.  For types which are vendor specific, a value above\n * OMX_OTHER_VENDORTSTART should be used.\n */\ntypedef enum OMX_OTHER_FORMATTYPE {\n    OMX_OTHER_FormatTime = 0, /**< Transmission of various timestamps, elapsed time, \n                                   time deltas, etc */\n    OMX_OTHER_FormatPower,    /**< Perhaps used for enabling/disabling power \n                                   management, setting clocks? */\n    OMX_OTHER_FormatStats,    /**< Could be things such as frame rate, frames \n                                   dropped, etc */\n    OMX_OTHER_FormatBinary,   /**< Arbitrary binary data */\n    OMX_OTHER_FormatVendorReserved = 1000, /**< Starting value for vendor specific \n                                                formats */\n\n    OMX_OTHER_FormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_OTHER_FormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_OTHER_FormatMax = 0x7FFFFFFF\n} OMX_OTHER_FORMATTYPE;\n\n/** \n * Enumeration of seek modes.\n */\ntypedef enum OMX_TIME_SEEKMODETYPE {\n    OMX_TIME_SeekModeFast = 0, /**< Prefer seeking to an approximation\n                                * of the requested seek position over   \n                                * the actual seek position if it\n                                * results in a faster seek. */\n    OMX_TIME_SeekModeAccurate, /**< Prefer seeking to the actual seek \n                                * position over an approximation\n                                * of the requested seek position even\n                                * if it results in a slower seek. */\n    OMX_TIME_SeekModeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_TIME_SeekModeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_TIME_SeekModeMax = 0x7FFFFFFF\n} OMX_TIME_SEEKMODETYPE;\n\n/* Structure representing the seekmode of the component */\ntypedef struct OMX_TIME_CONFIG_SEEKMODETYPE {\n    OMX_U32 nSize;                  /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;       /**< OMX specification version information */\n    OMX_TIME_SEEKMODETYPE eType;    /**< The seek mode */\n} OMX_TIME_CONFIG_SEEKMODETYPE;\n\n/** Structure representing a time stamp used with the following configs \n * on the Clock Component (CC):\n * \n * OMX_IndexConfigTimeCurrentWallTime: query of the CCs current wall  \n *     time\n * OMX_IndexConfigTimeCurrentMediaTime: query of the CCs current media\n *     time\n * OMX_IndexConfigTimeCurrentAudioReference and  \n * OMX_IndexConfigTimeCurrentVideoReference: audio/video reference \n *     clock sending SC its reference time\n * OMX_IndexConfigTimeClientStartTime: a Clock Component client sends \n *     this structure to the Clock Component via a SetConfig on its \n *     client port when it receives a buffer with\n *     OMX_BUFFERFLAG_STARTTIME set. It must use the timestamp\n *     specified by that buffer for nStartTimestamp. \n *\n * Its also used with the following config on components in general:\n *\n * OMX_IndexConfigTimePosition: IL client querying component position \n * (GetConfig) or commanding a component to seek to the given location\n * (SetConfig)\n */\t\ntypedef struct OMX_TIME_CONFIG_TIMESTAMPTYPE {\n    OMX_U32 nSize;               /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;    /**< OMX specification version\n                                  *   information */\n    OMX_U32 nPortIndex;     /**< port that this structure applies to */\n    OMX_TICKS nTimestamp;  \t     /**< timestamp .*/ \n} OMX_TIME_CONFIG_TIMESTAMPTYPE;  \n\n/** Enumeration of possible reference clocks to the media time. */\ntypedef enum OMX_TIME_UPDATETYPE {\n      OMX_TIME_UpdateRequestFulfillment,    /**< Update is the fulfillment of a media time request. */\n      OMX_TIME_UpdateScaleChanged,\t        /**< Update was generated because the scale chagned. */\n      OMX_TIME_UpdateClockStateChanged,     /**< Update was generated because the clock state changed. */\n      OMX_TIME_UpdateKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n      OMX_TIME_UpdateVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n      OMX_TIME_UpdateMax = 0x7FFFFFFF\n} OMX_TIME_UPDATETYPE;\n\n/** Enumeration of possible reference clocks to the media time. */\ntypedef enum OMX_TIME_REFCLOCKTYPE {\n      OMX_TIME_RefClockNone,    /**< Use no references. */\n      OMX_TIME_RefClockAudio,\t/**< Use references sent through OMX_IndexConfigTimeCurrentAudioReference */\n      OMX_TIME_RefClockVideo,   /**< Use references sent through OMX_IndexConfigTimeCurrentVideoReference */\n      OMX_TIME_RefClockKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n      OMX_TIME_RefClockVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n      OMX_TIME_RefClockMax = 0x7FFFFFFF\n} OMX_TIME_REFCLOCKTYPE;\n\n/** Enumeration of clock states. */\ntypedef enum OMX_TIME_CLOCKSTATE {\n      OMX_TIME_ClockStateRunning,             /**< Clock running. */\n      OMX_TIME_ClockStateWaitingForStartTime, /**< Clock waiting until the \n                                               *   prescribed clients emit their\n                                               *   start time. */\n      OMX_TIME_ClockStateStopped,             /**< Clock stopped. */\n      OMX_TIME_ClockStateKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n      OMX_TIME_ClockStateVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n      OMX_TIME_ClockStateMax = 0x7FFFFFFF\n} OMX_TIME_CLOCKSTATE;\n\n/** Structure representing a media time request to the clock component.\n *\n *  A client component sends this structure to the Clock Component via a SetConfig\n *  on its client port to specify a media timestamp the Clock Component\n *  should emit.  The Clock Component should fulfill the request by sending a\n *  OMX_TIME_MEDIATIMETYPE when its media clock matches the requested \n *  timestamp.\n *\n *  The client may require a media time request be fulfilled slightly\n *  earlier than the media time specified. In this case the client specifies \n *  an offset which is equal to the difference between wall time corresponding \n *  to the requested media time and the wall time when it will be \n *  fulfilled. \n *\n *  A client component may uses these requests and the OMX_TIME_MEDIATIMETYPE to\n *  time events according to timestamps. If a client must perform an operation O at\n *  a time T (e.g. deliver a video frame at its corresponding timestamp), it makes a \n *  media time request at T (perhaps specifying an offset to ensure the request fulfillment\n *  is a little early). When the clock component passes the resulting OMX_TIME_MEDIATIMETYPE\n *  structure back to the client component, the client may perform operation O (perhaps having\n *  to wait a slight amount more time itself as specified by the return values).\n */\n\ntypedef struct OMX_TIME_CONFIG_MEDIATIMEREQUESTTYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< port that this structure applies to */\n    OMX_PTR pClientPrivate;     /**< Client private data to disabiguate this media time \n                                 *   from others (e.g. the number of the frame to deliver). \n                                 *   Duplicated in the media time structure that fulfills \n                                 *   this request. A value of zero is reserved for time scale \n                                 *   updates. */\n    OMX_TICKS nMediaTimestamp;  /**< Media timestamp requested.*/ \n    OMX_TICKS nOffset;          /**< Amount of wall clock time by which this\n                                 *   request should be fulfilled early */\n} OMX_TIME_CONFIG_MEDIATIMEREQUESTTYPE;\n\n/**< Structure sent from the clock component client either when fulfilling \n *   a media time request or when the time scale has changed. \n *\n *   In the former case the Clock Component fills this structure and times its emission \n *   to a client component (via the client port) according to the corresponding media \n *   time request sent by the client. The Clock Component should time the emission to occur\n *   when the requested timestamp matches the Clock Component's media time but also the \n *   prescribed offset early. \n *\n *   Upon scale changes the clock component clears the nClientPrivate data, sends the current\n *   media time and sets the nScale to the new scale via the client port. It emits a \n *   OMX_TIME_MEDIATIMETYPE to all clients independent of any requests. This allows clients to \n *   alter processing to accomodate scaling. For instance a video component might skip inter-frames \n *   in the case of extreme fastforward. Likewise an audio component might add or remove samples \n *   from an audio frame to scale audio data. \n *\n *   It is expected that some clock components may not be able to fulfill requests\n *   at exactly the prescribed time. This is acceptable so long as the request is \n *   fulfilled at least as early as described and not later. This structure provides \n *   fields the client may use to wait for the remaining time.\n *\n *   The client may use either the nOffset or nWallTimeAtMedia fields to determine the \n *   wall time until the nMediaTimestamp actually occurs. In the latter case the\n *   client can get a more accurate value for offset by getting the current wall\n *   from the cloc component and subtracting it from nWallTimeAtMedia. \n */\n\ntypedef struct OMX_TIME_MEDIATIMETYPE {\n    OMX_U32 nSize;                  /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;       /**< OMX specification version information */\n    OMX_U32 nClientPrivate;         /**< Client private data to disabiguate this media time \n                                     *   from others. Copied from the media time request. \n                                     *   A value of zero is reserved for time scale updates. */\n    OMX_TIME_UPDATETYPE eUpdateType; /**< Reason for the update */\n    OMX_TICKS nMediaTimestamp;      /**< Media time requested. If no media time was \n                                     *   requested then this is the current media time. */ \n    OMX_TICKS nOffset;              /**< Amount of wall clock time by which this\n                                     *   request was actually fulfilled early */\n\n    OMX_TICKS nWallTimeAtMediaTime; /**< Wall time corresponding to nMediaTimeStamp.\n                                     *   A client may compare this value to current\n                                     *   media time obtained from the Clock Component to determine\n                                     *   the wall time until the media timestamp is really\n                                     *   current. */\n    OMX_S32 xScale;                 /**< Current media time scale in Q16 format. */\n    OMX_TIME_CLOCKSTATE eState;     /* Seeking Change. Added 7/12.*/\n                                    /**< State of the media time. */\n} OMX_TIME_MEDIATIMETYPE;  \n\n/** Structure representing the current media time scale factor. Applicable only to clock \n *  component, other components see scale changes via OMX_TIME_MEDIATIMETYPE buffers sent via\n *  the clock component client ports. Upon recieving this config the clock component changes \n *  the rate by which the media time increases or decreases effectively implementing trick modes. \n */ \ntypedef struct OMX_TIME_CONFIG_SCALETYPE {\n    OMX_U32 nSize;                  /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;       /**< OMX specification version information */\n    OMX_S32 xScale;                 /**< This is a value in Q16 format which is used for\n                                     * scaling the media time */\n} OMX_TIME_CONFIG_SCALETYPE;\n \n/** Bits used to identify a clock port. Used in OMX_TIME_CONFIG_CLOCKSTATETYPEs nWaitMask field */\n#define OMX_CLOCKPORT0 0x00000001\n#define OMX_CLOCKPORT1 0x00000002\n#define OMX_CLOCKPORT2 0x00000004\n#define OMX_CLOCKPORT3 0x00000008\n#define OMX_CLOCKPORT4 0x00000010\n#define OMX_CLOCKPORT5 0x00000020\n#define OMX_CLOCKPORT6 0x00000040\n#define OMX_CLOCKPORT7 0x00000080\n\n/** Structure representing the current mode of the media clock. \n *  IL Client uses this config to change or query the mode of the \n *  media clock of the clock component. Applicable only to clock\n *  component. \n *  \n *  On a SetConfig if eState is OMX_TIME_ClockStateRunning media time\n *  starts immediately at the prescribed start time. If\n *  OMX_TIME_ClockStateWaitingForStartTime the Clock Component ignores\n *  the given nStartTime and waits for all clients specified in the \n *  nWaitMask to send starttimes (via \n *  OMX_IndexConfigTimeClientStartTime). The Clock Component then starts \n *  the media clock using the earliest start time supplied. */    \ntypedef struct OMX_TIME_CONFIG_CLOCKSTATETYPE {\n    OMX_U32 nSize;              /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version \n                                 *   information */\n    OMX_TIME_CLOCKSTATE eState; /**< State of the media time. */\n    OMX_TICKS nStartTime;       /**< Start time of the media time. */\n    OMX_TICKS nOffset;          /**< Time to offset the media time by \n                                 * (e.g. preroll). Media time will be\n                                 * reported to be nOffset ticks earlier.     \n                                 */\n    OMX_U32 nWaitMask;          /**< Mask of OMX_CLOCKPORT values. */\n} OMX_TIME_CONFIG_CLOCKSTATETYPE;\n\n/** Structure representing the reference clock currently being used to\n *  compute media time. IL client uses this config to change or query the \n *  clock component's active reference clock */\ntypedef struct OMX_TIME_CONFIG_ACTIVEREFCLOCKTYPE {\n    OMX_U32 nSize;                  /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;       /**< OMX specification version information */\n    OMX_TIME_REFCLOCKTYPE eClock;   /**< Reference clock used to compute media time */                        \n} OMX_TIME_CONFIG_ACTIVEREFCLOCKTYPE;\n\n/** Descriptor for setting specifics of power type.\n *  Note: this structure is listed for backwards compatibility. */\ntypedef struct OMX_OTHER_CONFIG_POWERTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_BOOL bEnablePM;       /**< Flag to enable Power Management */\n} OMX_OTHER_CONFIG_POWERTYPE;\n\n\n/** Descriptor for setting specifics of stats type.\n *  Note: this structure is listed for backwards compatibility. */\ntypedef struct OMX_OTHER_CONFIG_STATSTYPE {\n    OMX_U32 nSize;            /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    /* what goes here */\n} OMX_OTHER_CONFIG_STATSTYPE;\n\n\n/**\n * The PortDefinition structure is used to define all of the parameters \n * necessary for the compliant component to setup an input or an output other \n * path.\n */\ntypedef struct OMX_OTHER_PORTDEFINITIONTYPE {\n    OMX_OTHER_FORMATTYPE eFormat;  /**< Type of data expected for this channel */\n} OMX_OTHER_PORTDEFINITIONTYPE;\n\n/**  Port format parameter.  This structure is used to enumerate\n  *  the various data input/output format supported by the port.\n  */\ntypedef struct OMX_OTHER_PARAM_PORTFORMATTYPE {\n    OMX_U32 nSize; /**< size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /**< OMX specification version information */\n    OMX_U32 nPortIndex; /**< Indicates which port to set */\n    OMX_U32 nIndex; /**< Indicates the enumeration index for the format from 0x0 to N-1 */\n    OMX_OTHER_FORMATTYPE eFormat; /**< Type of data expected for this channel */\n} OMX_OTHER_PARAM_PORTFORMATTYPE; \n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_QCOMExtns.h",
    "content": "/*--------------------------------------------------------------------------\nCopyright (c) 2009-2015, The Linux Foundation. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n    * Redistributions of source code must retain the above copyright\n      notice, this list of conditions and the following disclaimer.\n    * Redistributions in binary form must reproduce the above copyright\n      notice, this list of conditions and the following disclaimer in the\n      documentation and/or other materials provided with the distribution.\n    * Neither the name of The Linux Foundation nor\n      the names of its contributors may be used to endorse or promote\n      products derived from this software without specific prior written\n      permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\nNON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR\nCONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\nEXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\nPROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\nOR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\nWHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\nOTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\nADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n--------------------------------------------------------------------------*/\n#ifndef __OMX_QCOM_EXTENSIONS_H__\n#define __OMX_QCOM_EXTENSIONS_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/*============================================================================\n*//** @file OMX_QCOMExtns.h\n  This header contains constants and type definitions that specify the\n  extensions added to the OpenMAX Vendor specific APIs.\n\n*//*========================================================================*/\n\n\n///////////////////////////////////////////////////////////////////////////////\n//                             Include Files\n///////////////////////////////////////////////////////////////////////////////\n#include \"OMX_Core.h\"\n#include \"OMX_Video.h\"\n\n#define OMX_VIDEO_MAX_HP_LAYERS 6\n/**\n * This extension is used to register mapping of a virtual\n * address to a physical address. This extension is a parameter\n * which can be set using the OMX_SetParameter macro. The data\n * pointer corresponding to this extension is\n * OMX_QCOM_MemMapEntry. This parameter is a 'write only'\n * parameter (Current value cannot be queried using\n * OMX_GetParameter macro).\n */\n#define OMX_QCOM_EXTN_REGISTER_MMAP     \"OMX.QCOM.index.param.register_mmap\"\n\n/**\n * This structure describes the data pointer corresponding to\n * the OMX_QCOM_MMAP_REGISTER_EXTN extension. This parameter\n * must be set only 'after' populating a port with a buffer\n * using OMX_UseBuffer, wherein the data pointer of the buffer\n * corresponds to the virtual address as specified in this\n * structure.\n */\nstruct OMX_QCOM_PARAM_MEMMAPENTRYTYPE\n{\n    OMX_U32 nSize;              /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /**< OMX specification version information */\n    OMX_U32 nPortIndex;         /**< Port number the structure applies to */\n\n    /**\n     * The virtual address of memory block\n     */\n    OMX_U64 nVirtualAddress;\n\n    /**\n     * The physical address corresponding to the virtual address. The physical\n     * address is contiguous for the entire valid range of the virtual\n     * address.\n     */\n    OMX_U64 nPhysicalAddress;\n};\n\n#define QOMX_VIDEO_IntraRefreshRandom (OMX_VIDEO_IntraRefreshVendorStartUnused + 0)\n\n/* This error event is used for H.264 long-term reference (LTR) encoding.\n * When IL client specifies an LTR frame with its identifier via\n * OMX_QCOM_INDEX_CONFIG_VIDEO_LTRUSE to the encoder, if the specified\n * LTR frame can not be located by the encoder in its LTR list, the encoder\n * issues this error event to IL client to notify the failure of LTRUse config.\n */\n#define QOMX_ErrorLTRUseFailed        (OMX_ErrorVendorStartUnused + 1)\n\n#define QOMX_VIDEO_BUFFERFLAG_BFRAME 0x00100000\n\n#define QOMX_VIDEO_BUFFERFLAG_EOSEQ  0x00200000\n\n#define QOMX_VIDEO_BUFFERFLAG_MBAFF  0x00400000\n\n#define QOMX_VIDEO_BUFFERFLAG_CANCEL 0x00800000\n\n#define OMX_QCOM_PORTDEFN_EXTN   \"OMX.QCOM.index.param.portdefn\"\n/* Allowed APIs on the above Index: OMX_GetParameter() and OMX_SetParameter() */\n\ntypedef enum OMX_QCOMMemoryRegion\n{\n    OMX_QCOM_MemRegionInvalid,\n    OMX_QCOM_MemRegionEBI1,\n    OMX_QCOM_MemRegionSMI,\n    OMX_QCOM_MemRegionMax = 0X7FFFFFFF\n} OMX_QCOMMemoryRegion;\n\ntypedef enum OMX_QCOMCacheAttr\n{\n    OMX_QCOM_CacheAttrNone,\n    OMX_QCOM_CacheAttrWriteBack,\n    OMX_QCOM_CacheAttrWriteThrough,\n    OMX_QCOM_CacheAttrMAX = 0X7FFFFFFF\n} OMX_QCOMCacheAttr;\n\ntypedef struct OMX_QCOMRectangle\n{\n   OMX_S32 x;\n   OMX_S32 y;\n   OMX_S32 dx;\n   OMX_S32 dy;\n} OMX_QCOMRectangle;\n\n/** OMX_QCOMFramePackingFormat\n  * Input or output buffer format\n  */\ntypedef enum OMX_QCOMFramePackingFormat\n{\n  /* 0 - unspecified\n   */\n  OMX_QCOM_FramePacking_Unspecified,\n\n  /*  1 - Partial frames may be present OMX IL 1.1.1 Figure 2-10:\n   *  Case 1??Each Buffer Filled In Whole or In Part\n   */\n  OMX_QCOM_FramePacking_Arbitrary,\n\n  /*  2 - Multiple complete frames per buffer (integer number)\n   *  OMX IL 1.1.1 Figure 2-11: Case 2Each Buffer Filled with\n   *  Only Complete Frames of Data\n   */\n  OMX_QCOM_FramePacking_CompleteFrames,\n\n  /*  3 - Only one complete frame per buffer, no partial frame\n   *  OMX IL 1.1.1 Figure 2-12: Case 3Each Buffer Filled with\n   *  Only One Frame of Compressed Data. Usually at least one\n   *  complete unit of data will be delivered in a buffer for\n   *  uncompressed data formats.\n   */\n  OMX_QCOM_FramePacking_OnlyOneCompleteFrame,\n\n  /*  4 - Only one complete subframe per buffer, no partial subframe\n   *  Example: In H264, one complete NAL per buffer, where one frame\n   *  can contatin multiple NAL\n   */\n  OMX_QCOM_FramePacking_OnlyOneCompleteSubFrame,\n\n  OMX_QCOM_FramePacking_MAX = 0X7FFFFFFF\n} OMX_QCOMFramePackingFormat;\n\ntypedef struct OMX_QCOM_PARAM_PORTDEFINITIONTYPE {\n OMX_U32 nSize;           /** Size of the structure in bytes */\n OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n OMX_U32 nPortIndex;    /** Portindex which is extended by this structure */\n\n /** Platform specific memory region EBI1, SMI, etc.,*/\n OMX_QCOMMemoryRegion nMemRegion;\n\n OMX_QCOMCacheAttr nCacheAttr; /** Cache attributes */\n\n /** Input or output buffer format */\n OMX_U32 nFramePackingFormat;\n\n} OMX_QCOM_PARAM_PORTDEFINITIONTYPE;\n\ntypedef struct OMX_QCOM_VIDEO_PARAM_QPRANGETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 minQP;\n    OMX_U32 maxQP;\n} OMX_QCOM_VIDEO_PARAM_QPRANGETYPE;\n\n#define OMX_QCOM_PLATFORMPVT_EXTN   \"OMX.QCOM.index.param.platformprivate\"\n/** Allowed APIs on the above Index: OMX_SetParameter() */\n\ntypedef enum OMX_QCOM_PLATFORM_PRIVATE_ENTRY_TYPE\n{\n    /** Enum for PMEM information */\n    OMX_QCOM_PLATFORM_PRIVATE_PMEM = 0x1\n} OMX_QCOM_PLATFORM_PRIVATE_ENTRY_TYPE;\n\n/** IL client will set the following structure. A failure\n *  code will be returned if component does not support the\n *  value provided for 'type'.\n */\nstruct OMX_QCOM_PLATFORMPRIVATE_EXTN\n{\n    OMX_U32 nSize;        /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion; /** OMX spec version information */\n    OMX_U32 nPortIndex;  /** Port number on which usebuffer extn is applied */\n\n    /** Type of extensions should match an entry from\n     OMX_QCOM_PLATFORM_PRIVATE_ENTRY_TYPE\n    */\n    OMX_QCOM_PLATFORM_PRIVATE_ENTRY_TYPE type;\n};\n\ntypedef struct OMX_QCOM_PLATFORM_PRIVATE_PMEM_INFO\n{\n    /** pmem file descriptor */\n    unsigned long pmem_fd;\n    /** Offset from pmem device base address */\n    OMX_U32 offset;\n    OMX_U32 size;\n    OMX_U32 mapped_size;\n    OMX_PTR buffer;\n}OMX_QCOM_PLATFORM_PRIVATE_PMEM_INFO;\n\ntypedef struct OMX_QCOM_PLATFORM_PRIVATE_ENTRY\n{\n    /** Entry type */\n    OMX_QCOM_PLATFORM_PRIVATE_ENTRY_TYPE type;\n\n    /** Pointer to platform specific entry */\n    OMX_PTR entry;\n}OMX_QCOM_PLATFORM_PRIVATE_ENTRY;\n\ntypedef struct OMX_QCOM_PLATFORM_PRIVATE_LIST\n{\n    /** Number of entries */\n    OMX_U32 nEntries;\n\n    /** Pointer to array of platform specific entries *\n     * Contiguous block of OMX_QCOM_PLATFORM_PRIVATE_ENTRY element\n    */\n    OMX_QCOM_PLATFORM_PRIVATE_ENTRY* entryList;\n}OMX_QCOM_PLATFORM_PRIVATE_LIST;\n\n#define OMX_QCOM_FRAME_PACKING_FORMAT   \"OMX.QCOM.index.param.framepackfmt\"\n/* Allowed API call: OMX_GetParameter() */\n/* IL client can use this index to rerieve the list of frame formats *\n * supported by the component */\n\ntypedef struct OMX_QCOM_FRAME_PACKINGFORMAT_TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nIndex;\n    OMX_QCOMFramePackingFormat eframePackingFormat;\n} OMX_QCOM_FRAME_PACKINGFORMAT_TYPE;\n\n\n/**\n * Following is the enum for color formats supported on Qualcomm\n * MSMs YVU420SemiPlanar color format is not defined in OpenMAX\n * 1.1.1 and prior versions of OpenMAX specification.\n */\n\nenum OMX_QCOM_COLOR_FORMATTYPE\n{\n\n/** YVU420SemiPlanar: YVU planar format, organized with a first\n *  plane containing Y pixels, and a second plane containing\n *  interleaved V and U pixels. V and U pixels are sub-sampled\n *  by a factor of two both horizontally and vertically.\n */\n    QOMX_COLOR_FormatYVU420SemiPlanar = 0x7FA30C00,\n    QOMX_COLOR_FormatYVU420PackedSemiPlanar32m4ka,\n    QOMX_COLOR_FormatYUV420PackedSemiPlanar16m2ka,\n    QOMX_COLOR_FormatYUV420PackedSemiPlanar64x32Tile2m8ka,\n    QOMX_COLOR_FORMATYUV420PackedSemiPlanar32m,\n    QOMX_COLOR_FORMATYUV420PackedSemiPlanar32mMultiView,\n    QOMX_COLOR_FORMATYUV420PackedSemiPlanar32mCompressed,\n    QOMX_COLOR_Format32bitRGBA8888,\n    QOMX_COLOR_Format32bitRGBA8888Compressed,\n    QOMX_COLOR_FormatAndroidOpaque = (OMX_COLOR_FORMATTYPE) OMX_COLOR_FormatVendorStartUnused  + 0x789,\n};\n\nenum OMX_QCOM_VIDEO_CODINGTYPE\n{\n/** Codecs support by qualcomm which are not listed in OMX 1.1.x\n *  spec\n *   */\n    OMX_QCOM_VIDEO_CodingVC1  = 0x7FA30C00 ,\n    OMX_QCOM_VIDEO_CodingWMV9 = 0x7FA30C01,\n    QOMX_VIDEO_CodingDivx = 0x7FA30C02,     /**< Value when coding is Divx */\n    QOMX_VIDEO_CodingSpark = 0x7FA30C03,     /**< Value when coding is Sorenson Spark */\n    QOMX_VIDEO_CodingVp = 0x7FA30C04,\n    QOMX_VIDEO_CodingVp8 = OMX_VIDEO_CodingVP8,   /**< keeping old enum for backwards compatibility*/\n    QOMX_VIDEO_CodingHevc = OMX_VIDEO_CodingHEVC, /**< keeping old enum for backwards compatibility*/\n    QOMX_VIDEO_CodingMVC = 0x7FA30C07,\n    QOMX_VIDEO_CodingVp9 = OMX_VIDEO_CodingVP9,   /**< keeping old enum for backwards compatibility*/\n};\n\nenum OMX_QCOM_EXTN_INDEXTYPE\n{\n    /** Qcom proprietary extension index list */\n\n    /* \"OMX.QCOM.index.param.register_mmap\" */\n    OMX_QcomIndexRegmmap = 0x7F000000,\n\n    /* \"OMX.QCOM.index.param.platformprivate\" */\n    OMX_QcomIndexPlatformPvt = 0x7F000001,\n\n    /* \"OMX.QCOM.index.param.portdefn\" */\n    OMX_QcomIndexPortDefn = 0x7F000002,\n\n    /* \"OMX.QCOM.index.param.framepackingformat\" */\n    OMX_QcomIndexPortFramePackFmt = 0x7F000003,\n\n    /*\"OMX.QCOM.index.param.Interlaced */\n    OMX_QcomIndexParamInterlaced = 0x7F000004,\n\n    /*\"OMX.QCOM.index.config.interlaceformat */\n    OMX_QcomIndexConfigInterlaced = 0x7F000005,\n\n    /*\"OMX.QCOM.index.param.syntaxhdr\" */\n    QOMX_IndexParamVideoSyntaxHdr = 0x7F000006,\n\n    /*\"OMX.QCOM.index.config.intraperiod\" */\n    QOMX_IndexConfigVideoIntraperiod = 0x7F000007,\n\n    /*\"OMX.QCOM.index.config.randomIntrarefresh\" */\n    QOMX_IndexConfigVideoIntraRefresh = 0x7F000008,\n\n    /*\"OMX.QCOM.index.config.video.TemporalSpatialTradeOff\" */\n    QOMX_IndexConfigVideoTemporalSpatialTradeOff = 0x7F000009,\n\n    /*\"OMX.QCOM.index.param.video.EncoderMode\" */\n    QOMX_IndexParamVideoEncoderMode = 0x7F00000A,\n\n    /*\"OMX.QCOM.index.param.Divxtype */\n    OMX_QcomIndexParamVideoDivx = 0x7F00000B,\n\n    /*\"OMX.QCOM.index.param.Sparktype */\n    OMX_QcomIndexParamVideoSpark = 0x7F00000C,\n\n    /*\"OMX.QCOM.index.param.Vptype */\n    OMX_QcomIndexParamVideoVp = 0x7F00000D,\n\n    OMX_QcomIndexQueryNumberOfVideoDecInstance = 0x7F00000E,\n\n    OMX_QcomIndexParamVideoSyncFrameDecodingMode = 0x7F00000F,\n\n    OMX_QcomIndexParamVideoDecoderPictureOrder = 0x7F000010,\n\n    /* \"OMX.QCOM.index.config.video.FramePackingInfo\" */\n    OMX_QcomIndexConfigVideoFramePackingArrangement = 0x7F000011,\n\n    OMX_QcomIndexParamConcealMBMapExtraData = 0x7F000012,\n\n    OMX_QcomIndexParamFrameInfoExtraData = 0x7F000013,\n\n    OMX_QcomIndexParamInterlaceExtraData = 0x7F000014,\n\n    OMX_QcomIndexParamH264TimeInfo = 0x7F000015,\n\n    OMX_QcomIndexParamIndexExtraDataType = 0x7F000016,\n\n    OMX_GoogleAndroidIndexEnableAndroidNativeBuffers = 0x7F000017,\n\n    OMX_GoogleAndroidIndexUseAndroidNativeBuffer = 0x7F000018,\n\n    OMX_GoogleAndroidIndexGetAndroidNativeBufferUsage = 0x7F000019,\n\n    /*\"OMX.QCOM.index.config.video.QPRange\" */\n    OMX_QcomIndexConfigVideoQPRange = 0x7F00001A,\n\n    /*\"OMX.QCOM.index.param.EnableTimeStampReoder\"*/\n    OMX_QcomIndexParamEnableTimeStampReorder = 0x7F00001B,\n\n    /*\"OMX.google.android.index.storeMetaDataInBuffers\"*/\n    OMX_QcomIndexParamVideoMetaBufferMode = 0x7F00001C,\n\n    /*\"OMX.google.android.index.useAndroidNativeBuffer2\"*/\n    OMX_GoogleAndroidIndexUseAndroidNativeBuffer2 = 0x7F00001D,\n\n    /*\"OMX.QCOM.index.param.VideoMaxAllowedBitrateCheck\"*/\n    OMX_QcomIndexParamVideoMaxAllowedBitrateCheck = 0x7F00001E,\n\n    OMX_QcomIndexEnableSliceDeliveryMode = 0x7F00001F,\n\n    /* \"OMX.QCOM.index.param.video.ExtnUserExtraData\" */\n    OMX_QcomIndexEnableExtnUserData = 0x7F000020,\n\n    /*\"OMX.QCOM.index.param.video.EnableSmoothStreaming\"*/\n    OMX_QcomIndexParamEnableSmoothStreaming = 0x7F000021,\n\n    /*\"OMX.QCOM.index.param.video.QPRange\" */\n    OMX_QcomIndexParamVideoQPRange = 0x7F000022,\n\n    OMX_QcomIndexEnableH263PlusPType = 0x7F000023,\n\n    /*\"OMX.QCOM.index.param.video.LTRCountRangeSupported\"*/\n    QOMX_IndexParamVideoLTRCountRangeSupported = 0x7F000024,\n\n    /*\"OMX.QCOM.index.param.video.LTRMode\"*/\n    QOMX_IndexParamVideoLTRMode = 0x7F000025,\n\n    /*\"OMX.QCOM.index.param.video.LTRCount\"*/\n    QOMX_IndexParamVideoLTRCount = 0x7F000026,\n\n    /*\"OMX.QCOM.index.config.video.LTRPeriod\"*/\n    QOMX_IndexConfigVideoLTRPeriod = 0x7F000027,\n\n    /*\"OMX.QCOM.index.config.video.LTRUse\"*/\n    QOMX_IndexConfigVideoLTRUse = 0x7F000028,\n\n    /*\"OMX.QCOM.index.config.video.LTRMark\"*/\n    QOMX_IndexConfigVideoLTRMark = 0x7F000029,\n\n    /* OMX.google.android.index.prependSPSPPSToIDRFrames */\n    OMX_QcomIndexParamSequenceHeaderWithIDR = 0x7F00002A,\n\n    OMX_QcomIndexParamH264AUDelimiter = 0x7F00002B,\n\n    OMX_QcomIndexParamVideoDownScalar = 0x7F00002C,\n\n    /* \"OMX.QCOM.index.param.video.FramePackingExtradata\" */\n    OMX_QcomIndexParamVideoFramePackingExtradata = 0x7F00002D,\n\n    /* \"OMX.QCOM.index.config.activeregiondetection\" */\n    OMX_QcomIndexConfigActiveRegionDetection = 0x7F00002E,\n\n    /* \"OMX.QCOM.index.config.activeregiondetectionstatus\" */\n    OMX_QcomIndexConfigActiveRegionDetectionStatus = 0x7F00002F,\n\n    /* \"OMX.QCOM.index.config.scalingmode\" */\n    OMX_QcomIndexConfigScalingMode = 0x7F000030,\n\n    /* \"OMX.QCOM.index.config.noisereduction\" */\n    OMX_QcomIndexConfigNoiseReduction = 0x7F000031,\n\n    /* \"OMX.QCOM.index.config.imageenhancement\" */\n    OMX_QcomIndexConfigImageEnhancement = 0x7F000032,\n\n    /* google smooth-streaming support */\n    OMX_QcomIndexParamVideoAdaptivePlaybackMode = 0x7F000033,\n\n    /* H.264 MVC codec index */\n    QOMX_IndexParamVideoMvc = 0x7F000034,\n\n    /* \"OMX.QCOM.index.param.video.QPExtradata\" */\n    OMX_QcomIndexParamVideoQPExtraData = 0x7F000035,\n\n    /* \"OMX.QCOM.index.param.video.InputBitsInfoExtradata\" */\n    OMX_QcomIndexParamVideoInputBitsInfoExtraData = 0x7F000036,\n\n    /* VP8 Hierarchical P support */\n    OMX_QcomIndexHierarchicalStructure = 0x7F000037,\n\n    OMX_QcomIndexParamPerfLevel = 0x7F000038,\n\n    OMX_QcomIndexParamH264VUITimingInfo = 0x7F000039,\n\n    OMX_QcomIndexParamPeakBitrate = 0x7F00003A,\n\n    /* Enable InitialQP index */\n    QOMX_IndexParamVideoInitialQp = 0x7F00003B,\n\n    OMX_QcomIndexParamSetMVSearchrange = 0x7F00003C,\n\n    OMX_QcomIndexConfigPerfLevel = 0x7F00003D,\n\n    /*\"OMX.QCOM.index.param.video.LTRCount\"*/\n    OMX_QcomIndexParamVideoLTRCount = QOMX_IndexParamVideoLTRCount,\n\n    /*\"OMX.QCOM.index.config.video.LTRUse\"*/\n    OMX_QcomIndexConfigVideoLTRUse = QOMX_IndexConfigVideoLTRUse,\n\n    /*\"OMX.QCOM.index.config.video.LTRMark\"*/\n    OMX_QcomIndexConfigVideoLTRMark = QOMX_IndexConfigVideoLTRMark,\n\n    /*\"OMX.QCOM.index.param.video.CustomBufferSize\"*/\n    OMX_QcomIndexParamVideoCustomBufferSize = 0x7F00003E,\n\n    /* Max Hierarchical P layers */\n    OMX_QcomIndexMaxHierarchicallayers = 0x7F000041,\n\n    /* Set Encoder Performance Index */\n    OMX_QcomIndexConfigVideoVencPerfMode = 0x7F000042,\n\n    /* Set Hybrid Hier-p layers */\n    OMX_QcomIndexParamVideoHybridHierpMode = 0x7F000043,\n\n    OMX_QcomIndexFlexibleYUVDescription = 0x7F000044,\n\n    /* Vpp Hqv Control Type */\n    OMX_QcomIndexParamVppHqvControl = 0x7F000045,\n\n    /* Enable VPP */\n    OMX_QcomIndexParamEnableVpp = 0x7F000046,\n\n    /* MBI statistics mode */\n    OMX_QcomIndexParamMBIStatisticsMode = 0x7F000047,\n\n    /* Set PictureTypeDecode */\n    OMX_QcomIndexConfigPictureTypeDecode = 0x7F000048,\n\n    OMX_QcomIndexConfigH264EntropyCodingCabac = 0x7F000049,\n\n    /* \"OMX.QCOM.index.param.video.InputBatch\" */\n    OMX_QcomIndexParamBatchSize = 0x7F00004A,\n\n    OMX_QcomIndexConfigNumHierPLayers = 0x7F00004B,\n\n    OMX_QcomIndexConfigRectType = 0x7F00004C,\n\n    OMX_QcomIndexConfigBaseLayerId = 0x7F00004E,\n\n    OMX_QcomIndexParamDriverVersion = 0x7F00004F,\n\n    OMX_QcomIndexConfigQp = 0x7F000050,\n\n    OMX_QcomIndexParamVencAspectRatio = 0x7F000051,\n\n    OMX_QTIIndexParamVQZipSEIExtraData = 0x7F000052,\n\n    /* Enable VQZIP SEI NAL type */\n    OMX_QTIIndexParamVQZIPSEIType = 0x7F000053,\n\n    OMX_QTIIndexParamPassInputBufferFd = 0x7F000054,\n\n    /* Set Prefer-adaptive playback*/\n    /* \"OMX.QTI.index.param.video.PreferAdaptivePlayback\" */\n    OMX_QTIIndexParamVideoPreferAdaptivePlayback = 0x7F000055,\n\n    /* Set time params */\n    OMX_QTIIndexConfigSetTimeData = 0x7F000056,\n    /* Force Compressed format for DPB when resolution <=1080p\n     * and OPB is cpu_access */\n    /* OMX.QTI.index.param.video.ForceCompressedForDPB */\n    OMX_QTIIndexParamForceCompressedForDPB = 0x7F000057,\n\n    /* Enable ROI info */\n    OMX_QTIIndexParamVideoEnableRoiInfo = 0x7F000058,\n\n    /* Configure ROI info */\n    OMX_QTIIndexConfigVideoRoiInfo = 0x7F000059,\n\n    /* Set Low Latency Mode */\n    OMX_QTIIndexParamLowLatencyMode = 0x7F00005A,\n\n    /* Force OPB to UnCompressed mode */\n    OMX_QTIIndexParamForceUnCompressedForOPB = 0x7F00005B,\n\n};\n\n/**\n* This is custom extension to configure Low Latency Mode.\n*\n* STRUCT MEMBERS\n*\n* nSize         : Size of Structure in bytes\n* nVersion      : OpenMAX IL specification version information\n* bLowLatencyMode   : Enable/Disable Low Latency mode\n*/\n\ntypedef struct QOMX_EXTNINDEX_VIDEO_VENC_LOW_LATENCY_MODE\n{\n   OMX_U32 nSize;\n   OMX_VERSIONTYPE nVersion;\n   OMX_BOOL bLowLatencyMode;\n} QOMX_EXTNINDEX_VIDEO_VENC_LOW_LATENCY_MODE;\n\n/**\n* This is custom extension to configure Encoder Aspect Ratio.\n*\n* STRUCT MEMBERS\n*\n* nSize         : Size of Structure in bytes\n* nVersion      : OpenMAX IL specification version information\n* nSARWidth     : Horizontal aspect size\n* nSARHeight    : Vertical aspect size\n*/\n\ntypedef struct QOMX_EXTNINDEX_VIDEO_VENC_SAR\n{\n   OMX_U32 nSize;\n   OMX_U32 nVersion;\n   OMX_U32 nSARWidth;\n   OMX_U32 nSARHeight;\n} QOMX_EXTNINDEX_VIDEO_VENC_SAR;\n\n/**\n* This is custom extension to configure Hier-p layers.\n* This mode configures Hier-p layers dynamically.\n*\n* STRUCT MEMBERS\n*\n* nSize         : Size of Structure in bytes\n* nVersion      : OpenMAX IL specification version information\n* nNumHierLayers: Set the number of Hier-p layers for the session\n*                  - This should be less than the MAX Hier-P\n*                    layers set for the session.\n*/\n\ntypedef struct QOMX_EXTNINDEX_VIDEO_HIER_P_LAYERS {\n   OMX_U32 nSize;\n   OMX_VERSIONTYPE nVersion;\n   OMX_U32 nNumHierLayers;\n} QOMX_EXTNINDEX_VIDEO_HIER_P_LAYERS;\n\n\n/**\n* This is custom extension to configure Hybrid Hier-p settings.\n* This mode is different from enabling Hier-p mode. This\n* property enables Hier-p encoding with LTR referencing in each\n* sub-GOP.\n*\n* STRUCT MEMBERS\n*\n* nSize         : Size of Structure in bytes\n* nVersion      : OpenMAX IL specification version information\n* nKeyFrameInterval : Indicates the I frame interval\n* nHpLayers     : Set the number of Hier-p layers for the session\n*                  - This should be <= 6. (1 Base layer +\n*                    5 Enhancement layers)\n* nTemporalLayerBitrateRatio[OMX_VIDEO_MAX_HP_LAYERS] : Bitrate to\n*                    be set for each enhancement layer\n* nMinQuantizer  : minimum session QP\n* nMaxQuantizer  : Maximun session QP\n*/\n\ntypedef struct QOMX_EXTNINDEX_VIDEO_HYBRID_HP_MODE {\n   OMX_U32 nSize;\n   OMX_VERSIONTYPE nVersion;\n   OMX_U32 nKeyFrameInterval;\n   OMX_U32 nTemporalLayerBitrateRatio[OMX_VIDEO_MAX_HP_LAYERS];\n   OMX_U32 nMinQuantizer;\n   OMX_U32 nMaxQuantizer;\n   OMX_U32 nHpLayers;\n} QOMX_EXTNINDEX_VIDEO_HYBRID_HP_MODE;\n\n/**\n * Encoder Performance Mode.  This structure is used to set\n * performance mode or power save mode when encoding. The search\n * range is modified to save power or improve quality.\n *\n * STRUCT MEMBERS:\n * OMX_U32 nPerfMode  : Performance mode:\n *                                      1: MAX_QUALITY\n *                                      2: POWER_SAVE\n */\n\ntypedef struct QOMX_EXTNINDEX_VIDEO_PERFMODE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPerfMode;\n} QOMX_EXTNINDEX_VIDEO_PERFMODE;\n\n/**\n * Initial QP parameter.  This structure is used to enable\n * vendor specific extension to let client enable setting\n * initial QP values to I P B Frames\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  OMX_U32 nQpI       : First Iframe QP\n *  OMX_U32 nQpP       : First Pframe QP\n *  OMX_U32 nQpB       : First Bframe QP\n *  OMX_U32 bEnableInitQp : Bit field indicating which frame type(s) shall\n *                             use the specified initial QP.\n *                          Bit 0: Enable initial QP for I/IDR\n *                                 and use value specified in nInitQpI\n *                          Bit 1: Enable initial QP for P\n *                                 and use value specified in nInitQpP\n *                          Bit 2: Enable initial QP for B\n *                                 and use value specified in nInitQpB\n */\n\ntypedef struct QOMX_EXTNINDEX_VIDEO_INITIALQP {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nQpI;\n    OMX_U32 nQpP;\n    OMX_U32 nQpB;\n    OMX_U32 bEnableInitQp;\n} QOMX_EXTNINDEX_VIDEO_INITIALQP;\n\n/**\n * Extension index parameter.  This structure is used to enable\n * vendor specific extension on input/output port and\n * to pass the required flags and data, if any.\n * The format of flags and data being passed is known to\n * the client and component apriori.\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure plus pData size\n *  nVersion           : OMX specification version information\n *  nPortIndex         : Indicates which port to set\n *  bEnable            : Extension index enable (1) or disable (0)\n *  nFlags             : Extension index flags, if any\n *  nDataSize          : Size of the extension index data to follow\n *  pData              : Extension index data, if present.\n */\ntypedef struct QOMX_EXTNINDEX_PARAMTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnable;\n    OMX_U32 nFlags;\n    OMX_U32 nDataSize;\n    OMX_PTR pData;\n} QOMX_EXTNINDEX_PARAMTYPE;\n\n/**\n * Range index parameter.  This structure is used to enable\n * vendor specific extension on input/output port and\n * to pass the required minimum and maximum values\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  nMin               : Minimum value\n *  nMax               : Maximum value\n *  nSteSize           : Step size\n */\ntypedef struct QOMX_EXTNINDEX_RANGETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_S32 nMin;\n    OMX_S32 nMax;\n    OMX_S32 nStepSize;\n} QOMX_EXTNINDEX_RANGETYPE;\n\n/**\n *   Specifies LTR mode types.\n */\ntypedef enum QOMX_VIDEO_LTRMODETYPE\n{\n    QOMX_VIDEO_LTRMode_Disable    = 0x0, /**< LTR encoding is disabled */\n    QOMX_VIDEO_LTRMode_Manual     = 0x1, /**< In this mode, IL client configures\n                                           **  the encoder the LTR count and manually\n                                           **  controls the marking and use of LTR\n                                           **  frames during video encoding.\n                                           */\n    QOMX_VIDEO_LTRMode_Auto       = 0x2, /**< In this mode, IL client configures\n                                           **  the encoder the LTR count and LTR\n                                           **  period. The encoder marks LTR frames\n                                           **  automatically based on the LTR period\n                                           **  during video encoding. IL client controls\n                                           **  the use of LTR frames.\n                                           */\n    QOMX_VIDEO_LTRMode_MAX    = 0x7FFFFFFF /** Maximum LTR Mode type */\n} QOMX_VIDEO_LTRMODETYPE;\n\n/**\n * LTR mode index parameter.  This structure is used\n * to enable vendor specific extension on output port\n * to pass the LTR mode information.\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  eLTRMode           : Specifies the LTR mode used in encoder\n */\ntypedef struct QOMX_VIDEO_PARAM_LTRMODE_TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    QOMX_VIDEO_LTRMODETYPE eLTRMode;\n} QOMX_VIDEO_PARAM_LTRMODE_TYPE;\n\n/**\n * LTR count index parameter.  This structure is used\n * to enable vendor specific extension on output port\n * to pass the LTR count information.\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  nCount             : Specifies the number of LTR frames stored in the\n *                       encoder component\n */\ntypedef struct QOMX_VIDEO_PARAM_LTRCOUNT_TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nCount;\n} QOMX_VIDEO_PARAM_LTRCOUNT_TYPE;\n\n\n/**\n * This should be used with OMX_QcomIndexParamVideoLTRCount extension.\n */\ntypedef QOMX_VIDEO_PARAM_LTRCOUNT_TYPE OMX_QCOM_VIDEO_PARAM_LTRCOUNT_TYPE;\n\n/**\n * LTR period index parameter.  This structure is used\n * to enable vendor specific extension on output port\n * to pass the LTR period information.\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  nFrames            : Specifies the number of frames between two consecutive\n *                       LTR frames.\n */\ntypedef struct QOMX_VIDEO_CONFIG_LTRPERIOD_TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nFrames;\n} QOMX_VIDEO_CONFIG_LTRPERIOD_TYPE;\n\n/**\n * Marks the next encoded frame as an LTR frame.\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  nID                : Specifies the identifier of the LTR frame to be marked\n *                       as reference frame for encoding subsequent frames.\n */\ntypedef struct QOMX_VIDEO_CONFIG_LTRMARK_TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nID;\n} QOMX_VIDEO_CONFIG_LTRMARK_TYPE;\n\n/**\n * This should be used with OMX_QcomIndexConfigVideoLTRMark extension.\n */\ntypedef QOMX_VIDEO_CONFIG_LTRMARK_TYPE OMX_QCOM_VIDEO_CONFIG_LTRMARK_TYPE;\n\n/**\n * Specifies an LTR frame to encode subsequent frames.\n * STRUCT MEMBERS:\n *  nSize              : Size of Structure in bytes\n *  nVersion           : OpenMAX IL specification version information\n *  nPortIndex         : Index of the port to which this structure applies\n *  nID                : Specifies the identifier of the LTR frame to be used\n                         as reference frame for encoding subsequent frames.\n *  nFrames            : Specifies the number of subsequent frames to be\n                         encoded using the LTR frame with its identifier\n                         nID as reference frame. Short-term reference frames\n                         will be used thereafter. The value of 0xFFFFFFFF\n                         indicates that all subsequent frames will be\n                         encodedusing this LTR frame as reference frame.\n */\ntypedef struct QOMX_VIDEO_CONFIG_LTRUSE_TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nID;\n    OMX_U32 nFrames;\n} QOMX_VIDEO_CONFIG_LTRUSE_TYPE;\n\n/**\n * This should be used with OMX_QcomIndexConfigVideoLTRUse extension.\n */\ntypedef QOMX_VIDEO_CONFIG_LTRUSE_TYPE OMX_QCOM_VIDEO_CONFIG_LTRUSE_TYPE;\n\n/**\n * Enumeration used to define the video encoder modes\n *\n * ENUMS:\n *  EncoderModeDefault : Default video recording mode.\n *                       All encoder settings made through\n *                       OMX_SetParameter/OMX_SetConfig are applied. No\n *                       parameter is overridden.\n *  EncoderModeMMS : Video recording mode for MMS (Multimedia Messaging\n *                   Service). This mode is similar to EncoderModeDefault\n *                   except that here the Rate control mode is overridden\n *                   internally and set as a variant of variable bitrate with\n *                   variable frame rate. After this mode is set if the IL\n *                   client tries to set OMX_VIDEO_CONTROLRATETYPE via\n *                   OMX_IndexParamVideoBitrate that would be rejected. For\n *                   this, client should set mode back to EncoderModeDefault\n *                   first and then change OMX_VIDEO_CONTROLRATETYPE.\n */\ntypedef enum QOMX_VIDEO_ENCODERMODETYPE\n{\n    QOMX_VIDEO_EncoderModeDefault        = 0x00,\n    QOMX_VIDEO_EncoderModeMMS            = 0x01,\n    QOMX_VIDEO_EncoderModeMax            = 0x7FFFFFFF\n} QOMX_VIDEO_ENCODERMODETYPE;\n\n/**\n * This structure is used to set the video encoder mode.\n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version info\n *  nPortIndex : Port that this structure applies to\n *  nMode : defines the video encoder mode\n */\ntypedef struct QOMX_VIDEO_PARAM_ENCODERMODETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    QOMX_VIDEO_ENCODERMODETYPE nMode;\n} QOMX_VIDEO_PARAM_ENCODERMODETYPE;\n\n/**\n * This structure describes the parameters corresponding to the\n * QOMX_VIDEO_SYNTAXHDRTYPE extension. This parameter can be queried\n * during the loaded state.\n */\n\ntypedef struct QOMX_VIDEO_SYNTAXHDRTYPE\n{\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_U32 nPortIndex;      /** Portindex which is extended by this structure */\n   OMX_U32 nBytes;          /** The number of bytes filled in to the buffer */\n   OMX_U8 data[1];          /** Buffer to store the header information */\n} QOMX_VIDEO_SYNTAXHDRTYPE;\n\n/**\n * This structure describes the parameters corresponding to the\n * QOMX_VIDEO_TEMPORALSPATIALTYPE extension. This parameter can be set\n * dynamically during any state except the state invalid.  This is primarily\n * used for setting MaxQP from the application.  This is set on the out port.\n */\n\ntypedef struct QOMX_VIDEO_TEMPORALSPATIALTYPE\n{\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_U32 nPortIndex;      /** Portindex which is extended by this structure */\n   OMX_U32 nTSFactor;       /** Temoral spatial tradeoff factor value in 0-100 */\n} QOMX_VIDEO_TEMPORALSPATIALTYPE;\n\n/**\n * This structure describes the parameters corresponding to the\n * OMX_QCOM_VIDEO_CONFIG_INTRAPERIODTYPE extension. This parameter can be set\n * dynamically during any state except the state invalid.  This is set on the out port.\n */\n\ntypedef struct QOMX_VIDEO_INTRAPERIODTYPE\n{\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_U32 nPortIndex;      /** Portindex which is extended by this structure */\n   OMX_U32 nIDRPeriod;      /** This specifies coding a frame as IDR after every nPFrames\n                                of intra frames. If this parameter is set to 0, only the\n                                first frame of the encode session is an IDR frame. This\n                                field is ignored for non-AVC codecs and is used only for\n                                codecs that support IDR Period */\n   OMX_U32 nPFrames;         /** The number of \"P\" frames between two \"I\" frames */\n   OMX_U32 nBFrames;         /** The number of \"B\" frames between two \"I\" frames */\n} QOMX_VIDEO_INTRAPERIODTYPE;\n\n/**\n * This structure describes the parameters corresponding to the\n * OMX_QCOM_VIDEO_CONFIG_ULBUFFEROCCUPANCYTYPE extension. This parameter can be set\n * dynamically during any state except the state invalid. This is used for the buffer negotiation\n * with other clients.  This is set on the out port.\n */\ntypedef struct OMX_QCOM_VIDEO_CONFIG_ULBUFFEROCCUPANCYTYPE\n{\n   OMX_U32 nSize;            /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion; /** OMX specification version information */\n   OMX_U32 nPortIndex;       /** Portindex which is extended by this structure */\n   OMX_U32 nBufferOccupancy; /** The number of bytes to be set for the buffer occupancy */\n} OMX_QCOM_VIDEO_CONFIG_ULBUFFEROCCUPANCYTYPE;\n\n/**\n * This structure describes the parameters corresponding to the\n * OMX_QCOM_VIDEO_CONFIG_RANDOMINTRAREFRESHTYPE extension. This parameter can be set\n * dynamically during any state except the state invalid. This is primarily used for the dynamic/random\n * intrarefresh.  This is set on the out port.\n */\ntypedef struct OMX_QCOM_VIDEO_CONFIG_RANDOMINTRAREFRESHTYPE\n{\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_U32 nPortIndex;      /** Portindex which is extended by this structure */\n   OMX_U32 nRirMBs;         /** The number of MBs to be set for intrarefresh */\n} OMX_QCOM_VIDEO_CONFIG_RANDOMINTRAREFRESHTYPE;\n\n\n/**\n * This structure describes the parameters corresponding to the\n * OMX_QCOM_VIDEO_CONFIG_QPRANGE extension. This parameter can be set\n * dynamically during any state except the state invalid. This is primarily\n * used for the min/max QP to be set from the application.  This\n * is set on the out port.\n */\ntypedef struct OMX_QCOM_VIDEO_CONFIG_QPRANGE\n{\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_U32 nPortIndex;      /** Portindex which is extended by this structure */\n   OMX_U32 nMinQP;          /** The number for minimum quantization parameter */\n   OMX_U32 nMaxQP;          /** The number for maximum quantization parameter */\n} OMX_QCOM_VIDEO_CONFIG_QPRANGE;\n\n/**\n * This structure describes the parameters for the\n * OMX_QcomIndexParamH264AUDelimiter extension.  It enables/disables\n * the AU delimiters in the H264 stream, which is used by WFD.\n */\ntypedef struct OMX_QCOM_VIDEO_CONFIG_H264_AUD\n{\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_BOOL bEnable;        /** Enable/disable the setting */\n} OMX_QCOM_VIDEO_CONFIG_H264_AUD;\n\ntypedef enum QOMX_VIDEO_PERF_LEVEL\n{\n    OMX_QCOM_PerfLevelNominal,\n    OMX_QCOM_PerfLevelTurbo\n} QOMX_VIDEO_PERF_LEVEL;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QcomIndexParamPerfLevel extension. It will set\n * the performance mode specified as QOMX_VIDEO_PERF_LEVEL.\n */\ntypedef struct OMX_QCOM_VIDEO_PARAM_PERF_LEVEL {\n    OMX_U32 nSize;                      /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;           /** OMX specification version information */\n    QOMX_VIDEO_PERF_LEVEL ePerfLevel;   /** Performance level */\n} OMX_QCOM_VIDEO_PARAM_PERF_LEVEL;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QcomIndexConfigPerfLevel extension. It will set\n * the performance mode specified as QOMX_VIDEO_PERF_LEVEL.\n */\ntypedef struct OMX_QCOM_VIDEO_CONFIG_PERF_LEVEL {\n    OMX_U32 nSize;                      /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;           /** OMX specification version information */\n    QOMX_VIDEO_PERF_LEVEL ePerfLevel;   /** Performance level */\n} OMX_QCOM_VIDEO_CONFIG_PERF_LEVEL;\n\ntypedef enum QOMX_VIDEO_PICTURE_TYPE_DECODE\n{\n    OMX_QCOM_PictypeDecode_IPB,\n    OMX_QCOM_PictypeDecode_I\n} QOMX_VIDEO_PICTURE_TYPE_DECODE;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QcomIndexConfigPictureTypeDecode extension. It\n * will set the picture type decode specified by eDecodeType.\n */\ntypedef struct OMX_QCOM_VIDEO_CONFIG_PICTURE_TYPE_DECODE {\n    OMX_U32 nSize;                      /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;           /** OMX specification version information */\n    QOMX_VIDEO_PICTURE_TYPE_DECODE eDecodeType;   /** Decode type */\n} OMX_QCOM_VIDEO_CONFIG_PICTURE_TYPE_DECODE;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QcomIndexParamH264VUITimingInfo extension. It\n * will enable/disable the VUI timing info.\n */\ntypedef struct OMX_QCOM_VIDEO_PARAM_VUI_TIMING_INFO {\n    OMX_U32 nSize;              /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /** OMX specification version information */\n    OMX_BOOL bEnable;           /** Enable/disable the setting */\n} OMX_QCOM_VIDEO_PARAM_VUI_TIMING_INFO;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QcomIndexParamVQZIPSEIType extension. It\n * will enable/disable the VQZIP SEI info.\n */\ntypedef struct OMX_QTI_VIDEO_PARAM_VQZIP_SEI_TYPE {\n    OMX_U32 nSize;              /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /** OMX specification version information */\n    OMX_BOOL bEnable;           /** Enable/disable the setting */\n} OMX_QTI_VIDEO_PARAM_VQZIP_SEI_TYPE;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QcomIndexParamPeakBitrate extension. It will\n * set the peak bitrate specified by nPeakBitrate.\n */\ntypedef struct OMX_QCOM_VIDEO_PARAM_PEAK_BITRATE {\n    OMX_U32 nSize;              /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /** OMX specification version information */\n    OMX_U32 nPeakBitrate;       /** Peak bitrate value */\n} OMX_QCOM_VIDEO_PARAM_PEAK_BITRATE;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QTIIndexParamForceCompressedForDPB extension. Enabling\n * this extension will force the split mode DPB(compressed)/OPB(Linear)\n * for all resolutions.On some chipsets preferred mode would be combined\n * Linear for both DPB/OPB to save memory. For example on 8996 preferred mode\n * would be combined linear for resolutions <= 1080p .\n * Enabling this might save power but with the cost\n * of increased memory i.e almost double the number on output YUV buffers.\n */\ntypedef struct OMX_QTI_VIDEO_PARAM_FORCE_COMPRESSED_FOR_DPB_TYPE {\n    OMX_U32 nSize;              /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /** OMX specification version information */\n    OMX_BOOL bEnable;           /** Enable/disable the setting */\n} OMX_QTI_VIDEO_PARAM_FORCE_COMPRESSED_FOR_DPB_TYPE;\n\n/**\n * This structure describes the parameters corresponding\n * to OMX_QTIIndexParamForceUnCompressedForOPB extension. Enabling this\n * extension will force the OPB to be linear for the current video session.\n * If this property is not set, then the OPB will be set to linear or compressed\n * based on resolution selected and/or if cpu access is requested on the\n * OPB buffer.\n */\ntypedef struct OMX_QTI_VIDEO_PARAM_FORCE_UNCOMPRESSED_FOR_OPB_TYPE {\n    OMX_U32 nSize;              /** Sizeo f the structure in bytes */\n    OMX_VERSIONTYPE nVersion;   /** OMX specification version information */\n    OMX_BOOL bEnable;           /** Enable/disable the setting */\n} OMX_QTI_VIDEO_PARAM_FORCE_UNCOMPRESSED_FOR_OPB_TYPE;\n\ntypedef struct OMX_VENDOR_EXTRADATATYPE  {\n    OMX_U32 nPortIndex;\n    OMX_U32 nDataSize;\n    OMX_U8  *pData;     // cdata (codec_data/extradata)\n} OMX_VENDOR_EXTRADATATYPE;\n\n/**\n * This structure describes the parameters corresponding to the\n * OMX_VENDOR_VIDEOFRAMERATE extension. This parameter can be set\n * dynamically during any state except the state invalid. This is\n * used for frame rate to be set from the application. This\n * is set on the in port.\n */\ntypedef struct OMX_VENDOR_VIDEOFRAMERATE  {\n   OMX_U32 nSize;           /** Size of the structure in bytes */\n   OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n   OMX_U32 nPortIndex;      /** Portindex which is extended by this structure */\n   OMX_U32 nFps;            /** Frame rate value */\n   OMX_BOOL bEnabled;       /** Flag to enable or disable client's frame rate value */\n} OMX_VENDOR_VIDEOFRAMERATE;\n\ntypedef enum OMX_INDEXVENDORTYPE {\n    OMX_IndexVendorFileReadInputFilename = 0xFF000001,\n    OMX_IndexVendorParser3gpInputFilename = 0xFF000002,\n    OMX_IndexVendorVideoExtraData = 0xFF000003,\n    OMX_IndexVendorAudioExtraData = 0xFF000004,\n    OMX_IndexVendorVideoFrameRate = 0xFF000005,\n} OMX_INDEXVENDORTYPE;\n\ntypedef enum OMX_QCOM_VC1RESOLUTIONTYPE\n{\n   OMX_QCOM_VC1_PICTURE_RES_1x1,\n   OMX_QCOM_VC1_PICTURE_RES_2x1,\n   OMX_QCOM_VC1_PICTURE_RES_1x2,\n   OMX_QCOM_VC1_PICTURE_RES_2x2\n} OMX_QCOM_VC1RESOLUTIONTYPE;\n\ntypedef enum OMX_QCOM_INTERLACETYPE\n{\n    OMX_QCOM_InterlaceFrameProgressive,\n    OMX_QCOM_InterlaceInterleaveFrameTopFieldFirst,\n    OMX_QCOM_InterlaceInterleaveFrameBottomFieldFirst,\n    OMX_QCOM_InterlaceFrameTopFieldFirst,\n    OMX_QCOM_InterlaceFrameBottomFieldFirst,\n    OMX_QCOM_InterlaceFieldTop,\n    OMX_QCOM_InterlaceFieldBottom\n}OMX_QCOM_INTERLACETYPE;\n\ntypedef struct OMX_QCOM_PARAM_VIDEO_INTERLACETYPE\n{\n    OMX_U32 nSize;           /** Size of the structure in bytes */\n    OMX_VERSIONTYPE nVersion;/** OMX specification version information */\n    OMX_U32 nPortIndex;    /** Portindex which is extended by this structure */\n    OMX_BOOL bInterlace;  /** Interlace content **/\n}OMX_QCOM_PARAM_VIDEO_INTERLACETYPE;\n\ntypedef struct OMX_QCOM_CONFIG_INTERLACETYPE\n{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nIndex;\n    OMX_QCOM_INTERLACETYPE eInterlaceType;\n}OMX_QCOM_CONFIG_INTERLACETYPE;\n\n#define MAX_PAN_SCAN_WINDOWS 4\n\ntypedef struct OMX_QCOM_PANSCAN\n{\n   OMX_U32 numWindows;\n   OMX_QCOMRectangle window[MAX_PAN_SCAN_WINDOWS];\n} OMX_QCOM_PANSCAN;\n\ntypedef struct OMX_QCOM_ASPECT_RATIO\n{\n   OMX_U32 aspectRatioX;\n   OMX_U32 aspectRatioY;\n} OMX_QCOM_ASPECT_RATIO;\n\ntypedef struct OMX_QCOM_DISPLAY_ASPECT_RATIO\n{\n   OMX_U32 displayVerticalSize;\n   OMX_U32 displayHorizontalSize;\n} OMX_QCOM_DISPLAY_ASPECT_RATIO;\n\ntypedef struct OMX_QCOM_FRAME_PACK_ARRANGEMENT\n{\n  OMX_U32 nSize;\n  OMX_VERSIONTYPE nVersion;\n  OMX_U32 nPortIndex;\n  OMX_U32 id;\n  OMX_U32 cancel_flag;\n  OMX_U32 type;\n  OMX_U32 quincunx_sampling_flag;\n  OMX_U32 content_interpretation_type;\n  OMX_U32 spatial_flipping_flag;\n  OMX_U32 frame0_flipped_flag;\n  OMX_U32 field_views_flag;\n  OMX_U32 current_frame_is_frame0_flag;\n  OMX_U32 frame0_self_contained_flag;\n  OMX_U32 frame1_self_contained_flag;\n  OMX_U32 frame0_grid_position_x;\n  OMX_U32 frame0_grid_position_y;\n  OMX_U32 frame1_grid_position_x;\n  OMX_U32 frame1_grid_position_y;\n  OMX_U32 reserved_byte;\n  OMX_U32 repetition_period;\n  OMX_U32 extension_flag;\n} OMX_QCOM_FRAME_PACK_ARRANGEMENT;\n\ntypedef struct OMX_QCOM_EXTRADATA_QP\n{\n   OMX_U32        nQP;\n} OMX_QCOM_EXTRADATA_QP;\n\ntypedef struct OMX_QCOM_EXTRADATA_BITS_INFO\n{\n   OMX_U32 header_bits;\n   OMX_U32 frame_bits;\n} OMX_QCOM_EXTRADATA_BITS_INFO;\n\ntypedef struct OMX_QCOM_EXTRADATA_USERDATA {\n   OMX_U32 type;\n   OMX_U32 data[1];\n} OMX_QCOM_EXTRADATA_USERDATA;\n\ntypedef struct OMX_QCOM_EXTRADATA_FRAMEINFO\n{\n   // common frame meta data. interlace related info removed\n   OMX_VIDEO_PICTURETYPE  ePicType;\n   OMX_QCOM_INTERLACETYPE interlaceType;\n   OMX_QCOM_PANSCAN       panScan;\n   OMX_QCOM_ASPECT_RATIO  aspectRatio;\n   OMX_QCOM_DISPLAY_ASPECT_RATIO displayAspectRatio;\n   OMX_U32                nConcealedMacroblocks;\n   OMX_U32                nFrameRate;\n   OMX_TICKS              nTimeStamp;\n} OMX_QCOM_EXTRADATA_FRAMEINFO;\n\ntypedef struct OMX_QCOM_EXTRADATA_FRAMEDIMENSION\n{\n   /** Frame Dimensions added to each YUV buffer */\n   OMX_U32   nDecWidth;  /** Width  rounded to multiple of 16 */\n   OMX_U32   nDecHeight; /** Height rounded to multiple of 16 */\n   OMX_U32   nActualWidth; /** Actual Frame Width */\n   OMX_U32   nActualHeight; /** Actual Frame Height */\n\n} OMX_QCOM_EXTRADATA_FRAMEDIMENSION;\n\ntypedef struct OMX_QCOM_H264EXTRADATA\n{\n   OMX_U64 seiTimeStamp;\n} OMX_QCOM_H264EXTRADATA;\n\ntypedef struct OMX_QCOM_VC1EXTRADATA\n{\n   OMX_U32                     nVC1RangeY;\n   OMX_U32                     nVC1RangeUV;\n   OMX_QCOM_VC1RESOLUTIONTYPE eVC1PicResolution;\n} OMX_QCOM_VC1EXTRADATA;\n\ntypedef union OMX_QCOM_EXTRADATA_CODEC_DATA\n{\n   OMX_QCOM_H264EXTRADATA h264ExtraData;\n   OMX_QCOM_VC1EXTRADATA vc1ExtraData;\n} OMX_QCOM_EXTRADATA_CODEC_DATA;\n\ntypedef struct OMX_QCOM_EXTRADATA_MBINFO\n{\n   OMX_U32 nFormat;\n   OMX_U32 nDataSize;\n   OMX_U8  data[0];\n} OMX_QCOM_EXTRADATA_MBINFO;\n\ntypedef struct OMX_QCOM_EXTRADATA_VQZIPSEI {\n    OMX_U32 nSize;\n    OMX_U8 data[0];\n} OMX_QCOM_EXTRADATA_VQZIPSEI;\n\ntypedef struct OMX_QTI_VIDEO_PARAM_ENABLE_ROIINFO {\n    OMX_U32         nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32         nPortIndex;\n    OMX_BOOL        bEnableRoiInfo;\n} OMX_QTI_VIDEO_PARAM_ENABLE_ROIINFO;\n\ntypedef struct OMX_QTI_VIDEO_CONFIG_ROIINFO {\n    OMX_U32         nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32         nPortIndex;\n    OMX_S32         nUpperQpOffset;\n    OMX_S32         nLowerQpOffset;\n    OMX_BOOL        bUseRoiInfo;\n    OMX_S32         nRoiMBInfoSize;\n    OMX_PTR         pRoiMBInfo;\n} OMX_QTI_VIDEO_CONFIG_ROIINFO;\n\ntypedef enum OMX_QCOM_EXTRADATATYPE\n{\n    OMX_ExtraDataFrameInfo =               0x7F000001,\n    OMX_ExtraDataH264 =                    0x7F000002,\n    OMX_ExtraDataVC1 =                     0x7F000003,\n    OMX_ExtraDataFrameDimension =          0x7F000004,\n    OMX_ExtraDataVideoEncoderSliceInfo =   0x7F000005,\n    OMX_ExtraDataConcealMB =               0x7F000006,\n    OMX_ExtraDataInterlaceFormat =         0x7F000007,\n    OMX_ExtraDataPortDef =                 0x7F000008,\n    OMX_ExtraDataMP2ExtnData =             0x7F000009,\n    OMX_ExtraDataMP2UserData =             0x7F00000a,\n    OMX_ExtraDataVideoLTRInfo =            0x7F00000b,\n    OMX_ExtraDataFramePackingArrangement = 0x7F00000c,\n    OMX_ExtraDataQP =                      0x7F00000d,\n    OMX_ExtraDataInputBitsInfo =           0x7F00000e,\n    OMX_ExtraDataVideoEncoderMBInfo =      0x7F00000f,\n    OMX_ExtraDataVQZipSEI  =               0x7F000010,\n} OMX_QCOM_EXTRADATATYPE;\n\ntypedef struct  OMX_STREAMINTERLACEFORMATTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bInterlaceFormat;\n    OMX_U32 nInterlaceFormats;\n} OMX_STREAMINTERLACEFORMAT;\n\ntypedef enum OMX_INTERLACETYPE\n{\n   OMX_InterlaceFrameProgressive,\n   OMX_InterlaceInterleaveFrameTopFieldFirst,\n   OMX_InterlaceInterleaveFrameBottomFieldFirst,\n   OMX_InterlaceFrameTopFieldFirst,\n   OMX_InterlaceFrameBottomFieldFirst\n} OMX_INTERLACES;\n\n\n#define OMX_EXTRADATA_HEADER_SIZE 20\n\n/**\n * AVC profile types, each profile indicates support for various\n * performance bounds and different annexes.\n */\ntypedef enum QOMX_VIDEO_AVCPROFILETYPE {\n    QOMX_VIDEO_AVCProfileBaseline      = OMX_VIDEO_AVCProfileBaseline,\n    QOMX_VIDEO_AVCProfileMain          = OMX_VIDEO_AVCProfileMain,\n    QOMX_VIDEO_AVCProfileExtended      = OMX_VIDEO_AVCProfileExtended,\n    QOMX_VIDEO_AVCProfileHigh          = OMX_VIDEO_AVCProfileHigh,\n    QOMX_VIDEO_AVCProfileHigh10        = OMX_VIDEO_AVCProfileHigh10,\n    QOMX_VIDEO_AVCProfileHigh422       = OMX_VIDEO_AVCProfileHigh422,\n    QOMX_VIDEO_AVCProfileHigh444       = OMX_VIDEO_AVCProfileHigh444,\n    /* QCom specific profile indexes */\n    QOMX_VIDEO_AVCProfileConstrained           = OMX_VIDEO_AVCProfileVendorStartUnused,\n    QOMX_VIDEO_AVCProfileConstrainedBaseline,\n    QOMX_VIDEO_AVCProfileConstrainedHigh,\n} QOMX_VIDEO_AVCPROFILETYPE;\n\n\n/**\n * H.264 MVC Profiles\n  */\ntypedef enum QOMX_VIDEO_MVCPROFILETYPE {\n    QOMX_VIDEO_MVCProfileStereoHigh = 0x1,\n    QOMX_VIDEO_MVCProfileMultiViewHigh = 0x2,\n    QOMX_VIDEO_MVCProfileKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_MVCProfileVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_MVCProfileMax = 0x7FFFFFFF\n} QOMX_VIDEO_MVCPROFILETYPE;\n\n/**\n * H.264 MVC Levels\n  */\ntypedef enum QOMX_VIDEO_MVCLEVELTYPE {\n    QOMX_VIDEO_MVCLevel1   = 0x01,     /**< Level 1 */\n    QOMX_VIDEO_MVCLevel1b  = 0x02,     /**< Level 1b */\n    QOMX_VIDEO_MVCLevel11  = 0x04,     /**< Level 1.1 */\n    QOMX_VIDEO_MVCLevel12  = 0x08,     /**< Level 1.2 */\n    QOMX_VIDEO_MVCLevel13  = 0x10,     /**< Level 1.3 */\n    QOMX_VIDEO_MVCLevel2   = 0x20,     /**< Level 2 */\n    QOMX_VIDEO_MVCLevel21  = 0x40,     /**< Level 2.1 */\n    QOMX_VIDEO_MVCLevel22  = 0x80,     /**< Level 2.2 */\n    QOMX_VIDEO_MVCLevel3   = 0x100,    /**< Level 3 */\n    QOMX_VIDEO_MVCLevel31  = 0x200,    /**< Level 3.1 */\n    QOMX_VIDEO_MVCLevel32  = 0x400,    /**< Level 3.2 */\n    QOMX_VIDEO_MVCLevel4   = 0x800,    /**< Level 4 */\n    QOMX_VIDEO_MVCLevel41  = 0x1000,   /**< Level 4.1 */\n    QOMX_VIDEO_MVCLevel42  = 0x2000,   /**< Level 4.2 */\n    QOMX_VIDEO_MVCLevel5   = 0x4000,   /**< Level 5 */\n    QOMX_VIDEO_MVCLevel51  = 0x8000,   /**< Level 5.1 */\n    QOMX_VIDEO_MVCLevelKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_MVCLevelVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_MVCLevelMax = 0x7FFFFFFF\n} QOMX_VIDEO_MVCLEVELTYPE;\n\n/**\n * DivX Versions\n */\ntypedef enum  QOMX_VIDEO_DIVXFORMATTYPE {\n    QOMX_VIDEO_DIVXFormatUnused = 0x01, /**< Format unused or unknown */\n    QOMX_VIDEO_DIVXFormat311    = 0x02, /**< DivX 3.11 */\n    QOMX_VIDEO_DIVXFormat4      = 0x04, /**< DivX 4 */\n    QOMX_VIDEO_DIVXFormat5      = 0x08, /**< DivX 5 */\n    QOMX_VIDEO_DIVXFormat6      = 0x10, /**< DivX 6 */\n    QOMX_VIDEO_DIVXFormatKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_DIVXFormatVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_DIVXFormatMax = 0x7FFFFFFF\n} QOMX_VIDEO_DIVXFORMATTYPE;\n\n/**\n * DivX profile types, each profile indicates support for\n * various performance bounds.\n */\ntypedef enum QOMX_VIDEO_DIVXPROFILETYPE {\n    QOMX_VIDEO_DivXProfileqMobile = 0x01, /**< qMobile Profile */\n    QOMX_VIDEO_DivXProfileMobile  = 0x02, /**< Mobile Profile */\n    QOMX_VIDEO_DivXProfileMT      = 0x04, /**< Mobile Theatre Profile */\n    QOMX_VIDEO_DivXProfileHT      = 0x08, /**< Home Theatre Profile */\n    QOMX_VIDEO_DivXProfileHD      = 0x10, /**< High Definition Profile */\n    QOMX_VIDEO_DIVXProfileKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_DIVXProfileVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_DIVXProfileMax = 0x7FFFFFFF\n} QOMX_VIDEO_DIVXPROFILETYPE;\n\n/**\n * DivX Video Params\n *\n *  STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  eFormat    : Version of DivX stream / data\n *  eProfile   : Profile of DivX stream / data\n */\ntypedef struct QOMX_VIDEO_PARAM_DIVXTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    QOMX_VIDEO_DIVXFORMATTYPE eFormat;\n    QOMX_VIDEO_DIVXPROFILETYPE eProfile;\n} QOMX_VIDEO_PARAM_DIVXTYPE;\n\n\n\n/**\n *  VP Versions\n */\ntypedef enum QOMX_VIDEO_VPFORMATTYPE {\n    QOMX_VIDEO_VPFormatUnused = 0x01, /**< Format unused or unknown */\n    QOMX_VIDEO_VPFormat6      = 0x02, /**< VP6 Video Format */\n    QOMX_VIDEO_VPFormat7      = 0x04, /**< VP7 Video Format */\n    QOMX_VIDEO_VPFormat8      = 0x08, /**< VP8 Video Format */\n    QOMX_VIDEO_VPFormat9      = 0x10, /**< VP9 Video Format */\n    QOMX_VIDEO_VPFormatKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_VPFormatVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_VPFormatMax = 0x7FFFFFFF\n} QOMX_VIDEO_VPFORMATTYPE;\n\n/**\n * VP profile types, each profile indicates support for various\n * encoding tools.\n */\ntypedef enum QOMX_VIDEO_VPPROFILETYPE {\n    QOMX_VIDEO_VPProfileSimple   = 0x01, /**< Simple Profile, applies to VP6 only */\n    QOMX_VIDEO_VPProfileAdvanced = 0x02, /**< Advanced Profile, applies to VP6 only */\n    QOMX_VIDEO_VPProfileVersion0 = 0x04, /**< Version 0, applies to VP7 and VP8 */\n    QOMX_VIDEO_VPProfileVersion1 = 0x08, /**< Version 1, applies to VP7 and VP8 */\n    QOMX_VIDEO_VPProfileVersion2 = 0x10, /**< Version 2, applies to VP8 only */\n    QOMX_VIDEO_VPProfileVersion3 = 0x20, /**< Version 3, applies to VP8 only */\n    QOMX_VIDEO_VPProfileKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_VPProfileVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_VPProfileMax = 0x7FFFFFFF\n} QOMX_VIDEO_VPPROFILETYPE;\n\n/**\n * VP Video Params\n *\n *  STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  eFormat    : Format of VP stream / data\n *  eProfile   : Profile or Version of VP stream / data\n */\ntypedef struct QOMX_VIDEO_PARAM_VPTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    QOMX_VIDEO_VPFORMATTYPE eFormat;\n    QOMX_VIDEO_VPPROFILETYPE eProfile;\n} QOMX_VIDEO_PARAM_VPTYPE;\n\n/**\n * Spark Versions\n */\ntypedef enum QOMX_VIDEO_SPARKFORMATTYPE {\n    QOMX_VIDEO_SparkFormatUnused = 0x01, /**< Format unused or unknown */\n    QOMX_VIDEO_SparkFormat0      = 0x02, /**< Video Format Version 0 */\n    QOMX_VIDEO_SparkFormat1      = 0x04, /**< Video Format Version 1 */\n    QOMX_VIDEO_SparkFormatKhronosExtensions = 0x6F000000,\n    QOMX_VIDEO_SparkFormatVendorStartUnused = 0x7F000000,\n    QOMX_VIDEO_SparkFormatMax = 0x7FFFFFFF\n} QOMX_VIDEO_SPARKFORMATTYPE;\n\n/**\n * Spark Video Params\n *\n *  STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  eFormat    : Version of Spark stream / data\n */\ntypedef struct QOMX_VIDEO_PARAM_SPARKTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    QOMX_VIDEO_SPARKFORMATTYPE eFormat;\n} QOMX_VIDEO_PARAM_SPARKTYPE;\n\n\ntypedef struct QOMX_VIDEO_QUERY_DECODER_INSTANCES {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nNumOfInstances;\n} QOMX_VIDEO_QUERY_DECODER_INSTANCES;\n\ntypedef struct QOMX_ENABLETYPE {\n    OMX_BOOL bEnable;\n} QOMX_ENABLETYPE;\n\ntypedef enum QOMX_VIDEO_EVENTS {\n    OMX_EventIndexsettingChanged = OMX_EventVendorStartUnused\n} QOMX_VIDEO_EVENTS;\n\ntypedef enum QOMX_VIDEO_PICTURE_ORDER {\n    QOMX_VIDEO_DISPLAY_ORDER = 0x1,\n    QOMX_VIDEO_DECODE_ORDER = 0x2\n} QOMX_VIDEO_PICTURE_ORDER;\n\ntypedef struct QOMX_VIDEO_DECODER_PICTURE_ORDER {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    QOMX_VIDEO_PICTURE_ORDER eOutputPictureOrder;\n} QOMX_VIDEO_DECODER_PICTURE_ORDER;\n\ntypedef struct QOMX_INDEXEXTRADATATYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnabled;\n    OMX_INDEXTYPE nIndex;\n} QOMX_INDEXEXTRADATATYPE;\n\ntypedef struct QOMX_INDEXTIMESTAMPREORDER {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnable;\n} QOMX_INDEXTIMESTAMPREORDER;\n\ntypedef struct QOMX_INDEXDOWNSCALAR {\n        OMX_U32 nSize;\n        OMX_VERSIONTYPE nVersion;\n        OMX_U32 nPortIndex;\n        OMX_BOOL bEnable;\n} QOMX_INDEXDOWNSCALAR;\n\ntypedef struct QOMX_VIDEO_CUSTOM_BUFFERSIZE {\n        OMX_U32 nSize;\n        OMX_VERSIONTYPE nVersion;\n        OMX_U32 nPortIndex;\n        OMX_U32 nBufferSize;\n} QOMX_VIDEO_CUSTOM_BUFFERSIZE;\n\n#define OMX_QCOM_INDEX_PARAM_VIDEO_SYNCFRAMEDECODINGMODE \"OMX.QCOM.index.param.video.SyncFrameDecodingMode\"\n#define OMX_QCOM_INDEX_PARAM_INDEXEXTRADATA \"OMX.QCOM.index.param.IndexExtraData\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_SLICEDELIVERYMODE \"OMX.QCOM.index.param.SliceDeliveryMode\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_FRAMEPACKING_EXTRADATA \"OMX.QCOM.index.param.video.FramePackingExtradata\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_QP_EXTRADATA \"OMX.QCOM.index.param.video.QPExtradata\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_INPUTBITSINFO_EXTRADATA \"OMX.QCOM.index.param.video.InputBitsInfoExtradata\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_EXTNUSER_EXTRADATA \"OMX.QCOM.index.param.video.ExtnUserExtraData\"\n#define OMX_QCOM_INDEX_CONFIG_VIDEO_FRAMEPACKING_INFO \"OMX.QCOM.index.config.video.FramePackingInfo\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_MPEG2SEQDISP_EXTRADATA \"OMX.QCOM.index.param.video.Mpeg2SeqDispExtraData\"\n\n#define OMX_QCOM_INDEX_PARAM_VIDEO_HIERSTRUCTURE \"OMX.QCOM.index.param.video.HierStructure\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_LTRCOUNT \"OMX.QCOM.index.param.video.LTRCount\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_LTRPERIOD \"OMX.QCOM.index.param.video.LTRPeriod\"\n#define OMX_QCOM_INDEX_CONFIG_VIDEO_LTRUSE \"OMX.QCOM.index.config.video.LTRUse\"\n#define OMX_QCOM_INDEX_CONFIG_VIDEO_LTRMARK \"OMX.QCOM.index.config.video.LTRMark\"\n#define OMX_QCOM_INDEX_CONFIG_VIDEO_HIER_P_LAYERS \"OMX.QCOM.index.config.video.hierplayers\"\n#define OMX_QCOM_INDEX_CONFIG_RECTANGLE_TYPE \"OMX.QCOM.index.config.video.rectangle\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_BASE_LAYER_ID \"OMX.QCOM.index.param.video.baselayerid\"\n#define OMX_QCOM_INDEX_CONFIG_VIDEO_QP \"OMX.QCOM.index.config.video.qp\"\n#define OMX_QCOM_INDEX_PARAM_VIDEO_SAR \"OMX.QCOM.index.param.video.sar\"\n#define OMX_QTI_INDEX_PARAM_VIDEO_LOW_LATENCY \"OMX.QTI.index.param.video.LowLatency\"\n\n#define OMX_QCOM_INDEX_PARAM_VIDEO_PASSINPUTBUFFERFD \"OMX.QCOM.index.param.video.PassInputBufferFd\"\n#define OMX_QTI_INDEX_PARAM_VIDEO_PREFER_ADAPTIVE_PLAYBACK \"OMX.QTI.index.param.video.PreferAdaptivePlayback\"\n#define OMX_QTI_INDEX_CONFIG_VIDEO_SETTIMEDATA \"OMX.QTI.index.config.video.settimedata\"\n#define OMX_QTI_INDEX_PARAM_VIDEO_FORCE_COMPRESSED_FOR_DPB \"OMX.QTI.index.param.video.ForceCompressedForDPB\"\n#define OMX_QTI_INDEX_PARAM_VIDEO_ENABLE_ROIINFO \"OMX.QTI.index.param.enableRoiInfo\"\n#define OMX_QTI_INDEX_CONFIG_VIDEO_ROIINFO \"OMX.QTI.index.config.RoiInfo\"\n\ntypedef enum {\n    QOMX_VIDEO_FRAME_PACKING_CHECKERBOARD = 0,\n    QOMX_VIDEO_FRAME_PACKING_COLUMN_INTERLEAVE = 1,\n    QOMX_VIDEO_FRAME_PACKING_ROW_INTERLEAVE = 2,\n    QOMX_VIDEO_FRAME_PACKING_SIDE_BY_SIDE = 3,\n    QOMX_VIDEO_FRAME_PACKING_TOP_BOTTOM = 4,\n    QOMX_VIDEO_FRAME_PACKING_TEMPORAL = 5,\n} QOMX_VIDEO_FRAME_PACKING_ARRANGEMENT;\n\ntypedef enum {\n    QOMX_VIDEO_CONTENT_UNSPECIFIED = 0,\n    QOMX_VIDEO_CONTENT_LR_VIEW = 1,\n    QOMX_VIDEO_CONTENT_RL_VIEW = 2,\n} QOMX_VIDEO_CONTENT_INTERPRETATION;\n\n/**\n * Specifies the extended picture types. These values should be\n * OR'd along with the types defined in OMX_VIDEO_PICTURETYPE to\n * signal all pictures types which are allowed.\n *\n * ENUMS:\n *  H.264 Specific Picture Types:   IDR\n */\ntypedef enum QOMX_VIDEO_PICTURETYPE {\n    QOMX_VIDEO_PictureTypeIDR = OMX_VIDEO_PictureTypeVendorStartUnused + 0x1000\n} QOMX_VIDEO_PICTURETYPE;\n\n#define OMX_QCOM_INDEX_CONFIG_ACTIVE_REGION_DETECTION           \"OMX.QCOM.index.config.activeregiondetection\"\n#define OMX_QCOM_INDEX_CONFIG_ACTIVE_REGION_DETECTION_STATUS    \"OMX.QCOM.index.config.activeregiondetectionstatus\"\n#define OMX_QCOM_INDEX_CONFIG_SCALING_MODE                      \"OMX.QCOM.index.config.scalingmode\"\n#define OMX_QCOM_INDEX_CONFIG_NOISEREDUCTION                    \"OMX.QCOM.index.config.noisereduction\"\n#define OMX_QCOM_INDEX_CONFIG_IMAGEENHANCEMENT                  \"OMX.QCOM.index.config.imageenhancement\"\n#define OMX_QCOM_INDEX_PARAM_HELDBUFFERCOUNT                    \"OMX.QCOM.index.param.HeldBufferCount\" /**< reference: QOMX_HELDBUFFERCOUNTTYPE */\n\n\ntypedef struct QOMX_RECTTYPE {\n    OMX_S32 nLeft;\n    OMX_S32 nTop;\n    OMX_U32 nWidth;\n    OMX_U32 nHeight;\n} QOMX_RECTTYPE;\n\ntypedef struct QOMX_ACTIVEREGIONDETECTIONTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnable;\n    QOMX_RECTTYPE sROI;\n    OMX_U32 nNumExclusionRegions;\n    QOMX_RECTTYPE sExclusionRegions[1];\n} QOMX_ACTIVEREGIONDETECTIONTYPE;\n\ntypedef struct QOMX_ACTIVEREGIONDETECTION_STATUSTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bDetected;\n    QOMX_RECTTYPE sDetectedRegion;\n} QOMX_ACTIVEREGIONDETECTION_STATUSTYPE;\n\ntypedef enum QOMX_SCALE_MODETYPE {\n    QOMX_SCALE_MODE_Normal,\n    QOMX_SCALE_MODE_Anamorphic,\n    QOMX_SCALE_MODE_Max = 0x7FFFFFFF\n} QOMX_SCALE_MODETYPE;\n\ntypedef struct QOMX_SCALINGMODETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    QOMX_SCALE_MODETYPE  eScaleMode;\n} QOMX_SCALINGMODETYPE;\n\ntypedef struct QOMX_NOISEREDUCTIONTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnable;\n    OMX_BOOL bAutoMode;\n    OMX_S32 nNoiseReduction;\n} QOMX_NOISEREDUCTIONTYPE;\n\ntypedef struct QOMX_IMAGEENHANCEMENTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnable;\n    OMX_BOOL bAutoMode;\n    OMX_S32 nImageEnhancement;\n} QOMX_IMAGEENHANCEMENTTYPE;\n\n/*\n * these are part of OMX1.2 but JB MR2 branch doesn't have them defined\n * OMX_IndexParamInterlaceFormat\n * OMX_INTERLACEFORMATTYPE\n */\n#ifndef OMX_IndexParamInterlaceFormat\n#define OMX_IndexParamInterlaceFormat (0x7FF00000)\ntypedef struct OMX_INTERLACEFORMATTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nFormat;\n    OMX_TICKS nTimeStamp;\n} OMX_INTERLACEFORMATTYPE;\n#endif\n\n/**\n * This structure is used to indicate the maximum number of buffers\n * that a port will hold during data flow.\n *\n * STRUCT MEMBERS:\n *  nSize              : Size of the structure in bytes\n *  nVersion           : OMX specification version info\n *  nPortIndex         : Port that this structure applies to\n *  nHeldBufferCount   : Read-only, maximum number of buffers that will be held\n */\ntypedef struct QOMX_HELDBUFFERCOUNTTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nHeldBufferCount;\n} QOMX_HELDBUFFERCOUNTTYPE;\n\ntypedef enum QOMX_VIDEO_HIERARCHICALCODINGTYPE {\n    QOMX_HIERARCHICALCODING_P = 0x01,\n    QOMX_HIERARCHICALCODING_B = 0x02,\n} QOMX_VIDEO_HIERARCHICALCODINGTYPE;\n\ntypedef struct QOMX_VIDEO_HIERARCHICALLAYERS {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nNumLayers;\n    QOMX_VIDEO_HIERARCHICALCODINGTYPE eHierarchicalCodingType;\n} QOMX_VIDEO_HIERARCHICALLAYERS;\n\ntypedef struct QOMX_VIDEO_H264ENTROPYCODINGTYPE {\n   OMX_U32 nSize;\n   OMX_VERSIONTYPE nVersion;\n   OMX_BOOL bCabac;\n   OMX_U32 nCabacInitIdc;\n} QOMX_VIDEO_H264ENTROPYCODINGTYPE;\n\n\n/* VIDEO POSTPROCESSING CTRLS AND ENUMS */\n#define QOMX_VPP_HQV_CUSTOMPAYLOAD_SZ 256\n#define VPP_HQV_CONTROL_GLOBAL_START (VPP_HQV_CONTROL_CUST + 1)\n\ntypedef enum QOMX_VPP_HQV_MODE {\n    VPP_HQV_MODE_OFF,\n    VPP_HQV_MODE_AUTO,\n    VPP_HQV_MODE_MANUAL,\n    VPP_HQV_MODE_MAX\n} QOMX_VPP_HQV_MODE;\n\ntypedef enum QOMX_VPP_HQVCONTROLTYPE {\n    VPP_HQV_CONTROL_CADE = 0x1,\n    VPP_HQV_CONTROL_CNR = 0x04,\n    VPP_HQV_CONTROL_AIE = 0x05,\n    VPP_HQV_CONTROL_FRC = 0x06,\n    VPP_HQV_CONTROL_CUST = 0x07,\n    VPP_HQV_CONTROL_GLOBAL_DEMO = VPP_HQV_CONTROL_GLOBAL_START,\n    VPP_HQV_CONTROL_MAX,\n} QOMX_VPP_HQVCONTROLTYPE;\n\ntypedef enum QOMX_VPP_HQV_HUE_MODE {\n    VPP_HQV_HUE_MODE_OFF,\n    VPP_HQV_HUE_MODE_ON,\n    VPP_HQV_HUE_MODE_MAX,\n} QOMX_VPP_HQV_HUE_MODE;\n\ntypedef enum QOMX_VPP_HQV_FRC_MODE {\n   VPP_HQV_FRC_MODE_OFF,\n   VPP_HQV_FRC_MODE_LOW,\n   VPP_HQV_FRC_MODE_MED,\n   VPP_HQV_FRC_MODE_HIGH,\n   VPP_HQV_FRC_MODE_MAX,\n} QOMX_VPP_HQV_FRC_MODE;\n\n\ntypedef struct QOMX_VPP_HQVCTRL_CADE {\n    QOMX_VPP_HQV_MODE mode;\n    OMX_U32 level;\n    OMX_S32 contrast;\n    OMX_S32 saturation;\n} QOMX_VPP_HQVCTRL_CADE;\n\ntypedef struct QOMX_VPP_HQVCTRL_CNR {\n    QOMX_VPP_HQV_MODE mode;\n    OMX_U32 level;\n} QOMX_VPP_HQVCTRL_CNR;\n\ntypedef struct QOMX_VPP_HQVCTRL_AIE {\n    QOMX_VPP_HQV_MODE mode;\n    QOMX_VPP_HQV_HUE_MODE hue_mode;\n    OMX_U32 cade_level;\n    OMX_U32 ltm_level;\n} QOMX_VPP_HQVCTRL_AIE;\n\ntypedef struct QOMX_VPP_HQVCTRL_CUSTOM {\n    OMX_U32 id;\n    OMX_U32 len;\n    OMX_U8 data[QOMX_VPP_HQV_CUSTOMPAYLOAD_SZ];\n} QOMX_VPP_HQVCTRL_CUSTOM;\n\ntypedef struct QOMX_VPP_HQVCTRL_GLOBAL_DEMO {\n    OMX_U32 process_percent;\n} QOMX_VPP_HQVCTRL_GLOBAL_DEMO;\n\ntypedef struct QOMX_VPP_HQVCTRL_FRC {\n    QOMX_VPP_HQV_FRC_MODE mode;\n} QOMX_VPP_HQVCTRL_FRC;\n\ntypedef struct QOMX_VPP_HQVCONTROL {\n    QOMX_VPP_HQV_MODE mode;\n    QOMX_VPP_HQVCONTROLTYPE ctrl_type;\n    union {\n        QOMX_VPP_HQVCTRL_CADE cade;\n        QOMX_VPP_HQVCTRL_CNR cnr;\n        QOMX_VPP_HQVCTRL_AIE aie;\n        QOMX_VPP_HQVCTRL_CUSTOM custom;\n        QOMX_VPP_HQVCTRL_GLOBAL_DEMO global_demo;\n        QOMX_VPP_HQVCTRL_FRC frc;\n    };\n} QOMX_VPP_HQVCONTROL;\n\n/* STRUCTURE TO TURN VPP ON */\ntypedef struct QOMX_VPP_ENABLE {\n    OMX_BOOL enable_vpp;\n} QOMX_VPP_ENABLE;\n\ntypedef enum OMX_QOMX_VIDEO_MBISTATISTICSTYPE {\n    QOMX_MBI_STATISTICS_MODE_DEFAULT = 0,\n    QOMX_MBI_STATISTICS_MODE_1 = 0x01,\n    QOMX_MBI_STATISTICS_MODE_2 = 0x02,\n} OMX_QOMX_VIDEO_MBISTATISTICSTYPE;\n\ntypedef struct OMX_QOMX_VIDEO_MBI_STATISTICS {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_QOMX_VIDEO_MBISTATISTICSTYPE eMBIStatisticsType;\n} OMX_QOMX_VIDEO_MBI_STATISTICS;\n\ntypedef struct QOMX_VIDEO_BATCHSIZETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nBatchSize;\n} QOMX_VIDEO_BATCHSIZETYPE;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __OMX_QCOM_EXTENSIONS_H__ */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Skype_VideoExtensions.h",
    "content": "/*@@@+++@@@@******************************************************************\n\n Microsoft Skype Engineering\n Copyright (C) 2014 Microsoft Corporation.\n\nMIT License\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n\n*@@@---@@@@******************************************************************/\n\n\n#ifndef __OMX_SKYPE_VIDEOEXTENSIONS_H__\n#define __OMX_SKYPE_VIDEOEXTENSIONS_H__\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n#include <OMX_Core.h>\n\n#pragma pack(push, 1)\n\n\ntypedef enum OMX_SKYPE_VIDEO_SliceControlMode\n{\n    OMX_SKYPE_VIDEO_SliceControlModeNone        = 0,\n    OMX_SKYPE_VIDEO_SliceControlModeMB          = 1,\n    OMX_SKYPE_VIDEO_SliceControlModeByte        = 2,\n    OMX_SKYPE_VIDEO_SliceControlModMBRow        = 3,\n} OMX_SKYPE_VIDEO_SliceControlMode;\n\n\ntypedef enum OMX_SKYPE_VIDEO_HierarType\n{\n    OMX_SKYPE_VIDEO_HierarType_P                = 0x01,\n    OMX_SKYPE_VIDEO_HierarType_B                = 0x02,\n} OMX_SKYPE_VIDEO_HIERAR_HierarType;\n\ntypedef enum OMX_VIDEO_EXTENSION_AVCPROFILETYPE\n{\n    OMX_VIDEO_EXT_AVCProfileConstrainedBaseline = 0x01,\n    OMX_VIDEO_EXT_AVCProfileConstrainedHigh     = 0x02,\n} OMX_VIDEO_EXTENSION_AVCPROFILETYPE;\n\ntypedef struct OMX_SKYPE_VIDEO_ENCODERPARAMS {\n    OMX_BOOL bLowLatency;\n    OMX_BOOL bUseExtendedProfile;\n    OMX_BOOL bSequenceHeaderWithIDR;\n    OMX_VIDEO_EXTENSION_AVCPROFILETYPE eProfile;\n    OMX_U32 nLTRFrames;\n    OMX_SKYPE_VIDEO_HierarType eHierarType;\n    OMX_U32 nMaxTemporalLayerCount;\n    OMX_SKYPE_VIDEO_SliceControlMode eSliceControlMode;\n    OMX_U32 nSarIndex;\n    OMX_U32 nSarWidth;\n    OMX_U32 nSarHeight;\n} OMX_SKYPE_VIDEO_ENCODERPARAMS;\n\ntypedef struct OMX_SKYPE_VIDEO_PARAM_ENCODERSETTING {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_SKYPE_VIDEO_ENCODERPARAMS stEncParam;\n} OMX_SKYPE_VIDEO_PARAM_ENCODESETTING;\n\ntypedef struct OMX_SKYPE_VIDEO_ENCODERCAP {\n    OMX_BOOL bLowLatency;\n    OMX_U32 nMaxFrameWidth;\n    OMX_U32 nMaxFrameHeight;\n    OMX_U32 nMaxInstances;\n    OMX_U32 nMaxTemporaLayerCount;\n    OMX_U32 nMaxRefFrames;\n    OMX_U32 nMaxLTRFrames;\n    OMX_VIDEO_AVCLEVELTYPE nMaxLevel;\n    OMX_U32 nSliceControlModesBM;\n    OMX_U32 nMaxMacroblockProcessingRate;\n    OMX_U32 xMinScaleFactor;\n} OMX_SKYPE_VIDEO_ENCODERCAP;\n\ntypedef struct OMX_SKYPE_VIDEO_PARAM_ENCODERCAP {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_SKYPE_VIDEO_ENCODERCAP stEncCap;\n} OMX_SKYPE_VIDEO_PARAM_ENCODERCAP;\n\ntypedef struct OMX_SKYPE_VIDEO_DECODERCAP {\n    OMX_BOOL bLowLatency;\n    OMX_U32 nMaxFrameWidth;\n    OMX_U32 nMaxFrameHeight;\n    OMX_U32 nMaxInstances;\n    OMX_VIDEO_AVCLEVELTYPE nMaxLevel;\n    OMX_U32 nMaxMacroblockProcessingRate;\n} OMX_SKYPE_VIDEO_DECODERCAP;\n\ntypedef struct OMX_SKYPE_VIDEO_PARAM_DECODERCAP {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_SKYPE_VIDEO_DECODERCAP stDecoderCap;\n} OMX_SKYPE_VIDEO_PARAM_DECODERCAP;\n\ntypedef struct OMX_SKYPE_VIDEO_CONFIG_QP {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nQP;\n} OMX_SKYPE_VIDEO_CONFIG_QP;\n\ntypedef struct OMX_SKYPE_VIDEO_CONFIG_BASELAYERPID{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nPID;\n} OMX_SKYPE_VIDEO_CONFIG_BASELAYERPID;\n\ntypedef struct OMX_SKYPE_VIDEO_PARAM_DRIVERVER {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U64 nDriverVersion;\n} OMX_SKYPE_VIDEO_PARAM_DRIVERVER;\n\ntypedef enum OMX_SKYPE_VIDEO_DownScaleFactor\n{\n    OMX_SKYPE_VIDEO_DownScaleFactor_1_1         = 0,\n    OMX_SKYPE_VIDEO_DownScaleFactor_Equal_AR    = 1,\n    OMX_SKYPE_VIDEO_DownScaleFactor_Any         = 2,\n} OMX_SKYPE_VIDEO_DownScaleFactor;\n\n#pragma pack(pop)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Types.h",
    "content": "/*\n * Copyright (c) 2008 The Khronos Group Inc.\n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions:\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n\n/** OMX_Types.h - OpenMax IL version 1.1.2\n *  The OMX_Types header file contains the primitive type definitions used by\n *  the core, the application and the component.  This file may need to be\n *  modified to be used on systems that do not have \"char\" set to 8 bits, \n *  \"short\" set to 16 bits and \"long\" set to 32 bits.\n */\n\n#ifndef OMX_Types_h\n#define OMX_Types_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/** The OMX_API and OMX_APIENTRY are platform specific definitions used\n *  to declare OMX function prototypes.  They are modified to meet the\n *  requirements for a particular platform */\n#ifdef __SYMBIAN32__\n#   ifdef __OMX_EXPORTS\n#       define OMX_API __declspec(dllexport)\n#   else\n#       ifdef _WIN32\n#           define OMX_API __declspec(dllexport)\n#       else\n#           define OMX_API __declspec(dllimport)\n#       endif\n#   endif\n#else\n#   ifdef _WIN32\n#      ifdef __OMX_EXPORTS\n#          define OMX_API __declspec(dllexport)\n#      else\n#          define OMX_API __declspec(dllimport)\n#      endif\n#   else\n#      ifdef __OMX_EXPORTS\n#          define OMX_API\n#      else\n#          define OMX_API extern\n#      endif\n#   endif\n#endif\n\n#ifndef OMX_APIENTRY\n#define OMX_APIENTRY\n#endif\n\n/** OMX_IN is used to identify inputs to an OMX function.  This designation\n    will also be used in the case of a pointer that points to a parameter\n    that is used as an output. */\n#ifndef OMX_IN\n#define OMX_IN\n#endif\n\n/** OMX_OUT is used to identify outputs from an OMX function.  This\n    designation will also be used in the case of a pointer that points\n    to a parameter that is used as an input. */\n#ifndef OMX_OUT\n#define OMX_OUT\n#endif\n\n\n/** OMX_INOUT is used to identify parameters that may be either inputs or\n    outputs from an OMX function at the same time.  This designation will\n    also be used in the case of a pointer that  points to a parameter that\n    is used both as an input and an output. */\n#ifndef OMX_INOUT\n#define OMX_INOUT\n#endif\n\n/** OMX_ALL is used to as a wildcard to select all entities of the same type\n *  when specifying the index, or referring to a object by an index.  (i.e.\n *  use OMX_ALL to indicate all N channels). When used as a port index\n *  for a config or parameter this OMX_ALL denotes that the config or\n *  parameter applies to the entire component not just one port. */\n#define OMX_ALL 0xFFFFFFFF\n\n/** In the following we define groups that help building doxygen documentation */\n\n/** @defgroup core OpenMAX IL core\n * Functions and structure related to the OMX IL core\n */\n \n /** @defgroup comp OpenMAX IL component\n * Functions and structure related to the OMX IL component\n */\n \n/** @defgroup rpm Resource and Policy Management\n * Structures for resource and policy management of components\n */\n\n/** @defgroup buf Buffer Management\n * Buffer handling functions and structures\n */\n  \n/** @defgroup tun Tunneling\n * @ingroup core comp\n * Structures and functions to manage tunnels among component ports\n */\n \n/** @defgroup cp Content Pipes\n *  @ingroup core\n */\n \n /** @defgroup metadata Metadata handling\n  * \n  */ \n\n/** OMX_U8 is an 8 bit unsigned quantity that is byte aligned */\ntypedef unsigned char OMX_U8;\n\n/** OMX_S8 is an 8 bit signed quantity that is byte aligned */\ntypedef signed char OMX_S8;\n\n/** OMX_U16 is a 16 bit unsigned quantity that is 16 bit word aligned */\ntypedef unsigned short OMX_U16;\n\n/** OMX_S16 is a 16 bit signed quantity that is 16 bit word aligned */\ntypedef signed short OMX_S16;\n\n/** OMX_U32 is a 32 bit unsigned quantity that is 32 bit word aligned */\ntypedef unsigned int OMX_U32;\n\n/** OMX_S32 is a 32 bit signed quantity that is 32 bit word aligned */\ntypedef signed int OMX_S32;\n\n\n/* Users with compilers that cannot accept the \"long long\" designation should\n   define the OMX_SKIP64BIT macro.  It should be noted that this may cause\n   some components to fail to compile if the component was written to require\n   64 bit integral types.  However, these components would NOT compile anyway\n   since the compiler does not support the way the component was written.\n*/\n#ifndef OMX_SKIP64BIT\n#ifdef __SYMBIAN32__\n/** OMX_U64 is a 64 bit unsigned quantity that is 64 bit word aligned */\ntypedef unsigned long long OMX_U64;\n\n/** OMX_S64 is a 64 bit signed quantity that is 64 bit word aligned */\ntypedef signed long long OMX_S64;\n\n#elif defined(WIN32)\n\n/** OMX_U64 is a 64 bit unsigned quantity that is 64 bit word aligned */\ntypedef unsigned __int64  OMX_U64;\n\n/** OMX_S64 is a 64 bit signed quantity that is 64 bit word aligned */\ntypedef signed   __int64  OMX_S64;\n\n#else /* WIN32 */\n\n/** OMX_U64 is a 64 bit unsigned quantity that is 64 bit word aligned */\ntypedef unsigned long long OMX_U64;\n\n/** OMX_S64 is a 64 bit signed quantity that is 64 bit word aligned */\ntypedef signed long long OMX_S64;\n\n#endif /* WIN32 */\n#endif\n\n\n/** The OMX_BOOL type is intended to be used to represent a true or a false\n    value when passing parameters to and from the OMX core and components.  The\n    OMX_BOOL is a 32 bit quantity and is aligned on a 32 bit word boundary.\n */\ntypedef enum OMX_BOOL {\n    OMX_FALSE = 0,\n    OMX_TRUE = !OMX_FALSE,\n    OMX_BOOL_MAX = 0x7FFFFFFF\n} OMX_BOOL;\n \n#ifdef OMX_ANDROID_COMPILE_AS_32BIT_ON_64BIT_PLATFORMS\n\ntypedef OMX_U32 OMX_PTR;\ntypedef OMX_PTR OMX_STRING;\ntypedef OMX_PTR OMX_BYTE;\n\n#else\n\n/** The OMX_PTR type is intended to be used to pass pointers between the OMX\n    applications and the OMX Core and components.  This is a 32 bit pointer and\n    is aligned on a 32 bit boundary.\n */\ntypedef void* OMX_PTR;\n\n/** The OMX_STRING type is intended to be used to pass \"C\" type strings between\n    the application and the core and component.  The OMX_STRING type is a 32\n    bit pointer to a zero terminated string.  The  pointer is word aligned and\n    the string is byte aligned.\n */\ntypedef char* OMX_STRING;\n\n/** The OMX_BYTE type is intended to be used to pass arrays of bytes such as\n    buffers between the application and the component and core.  The OMX_BYTE\n    type is a 32 bit pointer to a zero terminated string.  The  pointer is word\n    aligned and the string is byte aligned.\n */\ntypedef unsigned char* OMX_BYTE;\n\n/** OMX_UUIDTYPE is a very long unique identifier to uniquely identify\n    at runtime.  This identifier should be generated by a component in a way\n    that guarantees that every instance of the identifier running on the system\n    is unique. */\n\n\n#endif\n\ntypedef unsigned char OMX_UUIDTYPE[128];\n\n/** The OMX_DIRTYPE enumeration is used to indicate if a port is an input or\n    an output port.  This enumeration is common across all component types.\n */\ntypedef enum OMX_DIRTYPE\n{\n    OMX_DirInput,              /**< Port is an input port */\n    OMX_DirOutput,             /**< Port is an output port */\n    OMX_DirMax = 0x7FFFFFFF\n} OMX_DIRTYPE;\n\n/** The OMX_ENDIANTYPE enumeration is used to indicate the bit ordering\n    for numerical data (i.e. big endian, or little endian).\n */\ntypedef enum OMX_ENDIANTYPE\n{\n    OMX_EndianBig, /**< big endian */\n    OMX_EndianLittle, /**< little endian */\n    OMX_EndianMax = 0x7FFFFFFF\n} OMX_ENDIANTYPE;\n\n\n/** The OMX_NUMERICALDATATYPE enumeration is used to indicate if data\n    is signed or unsigned\n */\ntypedef enum OMX_NUMERICALDATATYPE\n{\n    OMX_NumericalDataSigned, /**< signed data */\n    OMX_NumericalDataUnsigned, /**< unsigned data */\n    OMX_NumercialDataMax = 0x7FFFFFFF\n} OMX_NUMERICALDATATYPE;\n\n\n/** Unsigned bounded value type */\ntypedef struct OMX_BU32 {\n    OMX_U32 nValue; /**< actual value */\n    OMX_U32 nMin;   /**< minimum for value (i.e. nValue >= nMin) */\n    OMX_U32 nMax;   /**< maximum for value (i.e. nValue <= nMax) */\n} OMX_BU32;\n\n\n/** Signed bounded value type */\ntypedef struct OMX_BS32 {\n    OMX_S32 nValue; /**< actual value */\n    OMX_S32 nMin;   /**< minimum for value (i.e. nValue >= nMin) */\n    OMX_S32 nMax;   /**< maximum for value (i.e. nValue <= nMax) */\n} OMX_BS32;\n\n\n/** Structure representing some time or duration in microseconds. This structure\n  *  must be interpreted as a signed 64 bit value. The quantity is signed to accommodate\n  *  negative deltas and preroll scenarios. The quantity is represented in microseconds\n  *  to accomodate high resolution timestamps (e.g. DVD presentation timestamps based\n  *  on a 90kHz clock) and to allow more accurate and synchronized delivery (e.g.\n  *  individual audio samples delivered at 192 kHz). The quantity is 64 bit to \n  *  accommodate a large dynamic range (signed 32 bit values would allow only for plus\n  *  or minus 35 minutes).\n  *\n  *  Implementations with limited precision may convert the signed 64 bit value to\n  *  a signed 32 bit value internally but risk loss of precision.\n  */\n#ifndef OMX_SKIP64BIT\ntypedef OMX_S64 OMX_TICKS;\n#else\ntypedef struct OMX_TICKS\n{\n    OMX_U32 nLowPart;    /** low bits of the signed 64 bit tick value */\n    OMX_U32 nHighPart;   /** high bits of the signed 64 bit tick value */\n} OMX_TICKS;\n#endif\n#define OMX_TICKS_PER_SECOND 1000000\n\n/** Define the public interface for the OMX Handle.  The core will not use\n    this value internally, but the application should only use this value.\n */\ntypedef void* OMX_HANDLETYPE;\n\ntypedef struct OMX_MARKTYPE\n{\n    OMX_HANDLETYPE hMarkTargetComponent;   /**< The component that will\n                                                generate a mark event upon\n                                                processing the mark. */\n    OMX_PTR pMarkData;   /**< Application specific data associated with \n                              the mark sent on a mark event to disambiguate\n                              this mark from others. */\n} OMX_MARKTYPE;\n\n\n/** OMX_NATIVE_DEVICETYPE is used to map a OMX video port to the\n *  platform & operating specific object used to reference the display \n *  or can be used by a audio port for native audio rendering */\ntypedef void* OMX_NATIVE_DEVICETYPE;\n\n/** OMX_NATIVE_WINDOWTYPE is used to map a OMX video port to the\n *  platform & operating specific object used to reference the window */\ntypedef void* OMX_NATIVE_WINDOWTYPE;\n\n/** The OMX_VERSIONTYPE union is used to specify the version for\n    a structure or component.  For a component, the version is entirely\n    specified by the component vendor.  Components doing the same function\n    from different vendors may or may not have the same version.  For\n    structures, the version shall be set by the entity that allocates the\n    structure.  For structures specified in the OMX 1.1 specification, the\n    value of the version shall be set to 1.1.0.0 in all cases.  Access to the\n    OMX_VERSIONTYPE can be by a single 32 bit access (e.g. by nVersion) or\n    by accessing one of the structure elements to, for example, check only\n    the Major revision.\n */\ntypedef union OMX_VERSIONTYPE\n{\n    struct\n    {\n        OMX_U8 nVersionMajor;   /**< Major version accessor element */\n        OMX_U8 nVersionMinor;   /**< Minor version accessor element */\n        OMX_U8 nRevision;       /**< Revision version accessor element */\n        OMX_U8 nStep;           /**< Step version accessor element */\n    } s;\n    OMX_U32 nVersion;           /**< 32 bit value to make accessing the\n                                    version easily done in a single word\n                                    size copy/compare operation */\n} OMX_VERSIONTYPE;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_Video.h",
    "content": "/**\n * Copyright (c) 2008 The Khronos Group Inc. \n * \n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions: \n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software. \n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \n *\n */\n\n/** \n *  @file OMX_Video.h - OpenMax IL version 1.1.2\n *  The structures is needed by Video components to exchange parameters \n *  and configuration data with OMX components.\n */\n#ifndef OMX_Video_h\n#define OMX_Video_h\n\n/** @defgroup video OpenMAX IL Video Domain\n * @ingroup iv\n * Structures for OpenMAX IL Video domain\n * @{\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n\n/**\n * Each OMX header must include all required header files to allow the\n * header to compile without errors.  The includes below are required\n * for this header file to compile successfully \n */\n\n#include <OMX_IVCommon.h>\n\n\n/**\n * Enumeration used to define the possible video compression codings.  \n * NOTE:  This essentially refers to file extensions. If the coding is \n *        being used to specify the ENCODE type, then additional work \n *        must be done to configure the exact flavor of the compression \n *        to be used.  For decode cases where the user application can \n *        not differentiate between MPEG-4 and H.264 bit streams, it is \n *        up to the codec to handle this.\n */\ntypedef enum OMX_VIDEO_CODINGTYPE {\n    OMX_VIDEO_CodingUnused,     /**< Value when coding is N/A */\n    OMX_VIDEO_CodingAutoDetect, /**< Autodetection of coding type */\n    OMX_VIDEO_CodingMPEG2,      /**< AKA: H.262 */\n    OMX_VIDEO_CodingH263,       /**< H.263 */\n    OMX_VIDEO_CodingMPEG4,      /**< MPEG-4 */\n    OMX_VIDEO_CodingWMV,        /**< all versions of Windows Media Video */\n    OMX_VIDEO_CodingRV,         /**< all versions of Real Video */\n    OMX_VIDEO_CodingAVC,        /**< H.264/AVC */\n    OMX_VIDEO_CodingMJPEG,      /**< Motion JPEG */\n    OMX_VIDEO_CodingVP8,        /**< Google VP8, formerly known as On2 VP8 */\n    OMX_VIDEO_CodingVP9,        /**< Google VP9 */\n    OMX_VIDEO_CodingHEVC,       /**< HEVC */\n    OMX_VIDEO_CodingKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_CodingVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_CodingMax = 0x7FFFFFFF\n} OMX_VIDEO_CODINGTYPE;\n\n\n/**\n * Data structure used to define a video path.  The number of Video paths for \n * input and output will vary by type of the Video component.  \n * \n *    Input (aka Source) : zero Inputs, one Output,\n *    Splitter           : one Input, 2 or more Outputs,\n *    Processing Element : one Input, one output,\n *    Mixer              : 2 or more inputs, one output,\n *    Output (aka Sink)  : one Input, zero outputs.\n * \n * The PortDefinition structure is used to define all of the parameters \n * necessary for the compliant component to setup an input or an output video \n * path.  If additional vendor specific data is required, it should be \n * transmitted to the component using the CustomCommand function.  Compliant \n * components will prepopulate this structure with optimal values during the \n * GetDefaultInitParams command.\n *\n * STRUCT MEMBERS:\n *  cMIMEType             : MIME type of data for the port\n *  pNativeRender         : Platform specific reference for a display if a \n *                          sync, otherwise this field is 0\n *  nFrameWidth           : Width of frame to be used on channel if \n *                          uncompressed format is used.  Use 0 for unknown,\n *                          don't care or variable\n *  nFrameHeight          : Height of frame to be used on channel if \n *                          uncompressed format is used. Use 0 for unknown,\n *                          don't care or variable\n *  nStride               : Number of bytes per span of an image \n *                          (i.e. indicates the number of bytes to get\n *                          from span N to span N+1, where negative stride\n *                          indicates the image is bottom up\n *  nSliceHeight          : Height used when encoding in slices\n *  nBitrate              : Bit rate of frame to be used on channel if \n *                          compressed format is used. Use 0 for unknown, \n *                          don't care or variable\n *  xFramerate            : Frame rate to be used on channel if uncompressed \n *                          format is used. Use 0 for unknown, don't care or \n *                          variable.  Units are Q16 frames per second.\n *  bFlagErrorConcealment : Turns on error concealment if it is supported by \n *                          the OMX component\n *  eCompressionFormat    : Compression format used in this instance of the \n *                          component. When OMX_VIDEO_CodingUnused is \n *                          specified, eColorFormat is used\n *  eColorFormat : Decompressed format used by this component\n *  pNativeWindow : Platform specific reference for a window object if a \n *                          display sink , otherwise this field is 0x0. \n */\ntypedef struct OMX_VIDEO_PORTDEFINITIONTYPE {\n    OMX_STRING cMIMEType;\n    OMX_NATIVE_DEVICETYPE pNativeRender;\n    OMX_U32 nFrameWidth;\n    OMX_U32 nFrameHeight;\n    OMX_S32 nStride;\n    OMX_U32 nSliceHeight;\n    OMX_U32 nBitrate;\n    OMX_U32 xFramerate;\n    OMX_BOOL bFlagErrorConcealment;\n    OMX_VIDEO_CODINGTYPE eCompressionFormat;\n    OMX_COLOR_FORMATTYPE eColorFormat;\n    OMX_NATIVE_WINDOWTYPE pNativeWindow;\n} OMX_VIDEO_PORTDEFINITIONTYPE;\n\n/**  \n * Port format parameter.  This structure is used to enumerate the various \n * data input/output format supported by the port.\n * \n * STRUCT MEMBERS:\n *  nSize              : Size of the structure in bytes\n *  nVersion           : OMX specification version information\n *  nPortIndex         : Indicates which port to set\n *  nIndex             : Indicates the enumeration index for the format from \n *                       0x0 to N-1\n *  eCompressionFormat : Compression format used in this instance of the \n *                       component. When OMX_VIDEO_CodingUnused is specified, \n *                       eColorFormat is used \n *  eColorFormat       : Decompressed format used by this component\n *  xFrameRate         : Indicates the video frame rate in Q16 format\n */\ntypedef struct OMX_VIDEO_PARAM_PORTFORMATTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nIndex;\n    OMX_VIDEO_CODINGTYPE eCompressionFormat; \n    OMX_COLOR_FORMATTYPE eColorFormat;\n    OMX_U32 xFramerate;\n} OMX_VIDEO_PARAM_PORTFORMATTYPE;\n\n\n/**\n * This is a structure for configuring video compression quantization \n * parameter values.  Codecs may support different QP values for different\n * frame types.\n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version info\n *  nPortIndex : Port that this structure applies to\n *  nQpI       : QP value to use for index frames\n *  nQpP       : QP value to use for P frames\n *  nQpB       : QP values to use for bidirectional frames \n */\ntypedef struct OMX_VIDEO_PARAM_QUANTIZATIONTYPE {\n    OMX_U32 nSize;            \n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nQpI;\n    OMX_U32 nQpP;\n    OMX_U32 nQpB;\n} OMX_VIDEO_PARAM_QUANTIZATIONTYPE;\n\n\n/** \n * Structure for configuration of video fast update parameters. \n *  \n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version info \n *  nPortIndex : Port that this structure applies to\n *  bEnableVFU : Enable/Disable video fast update\n *  nFirstGOB  : Specifies the number of the first macroblock row\n *  nFirstMB   : specifies the first MB relative to the specified first GOB\n *  nNumMBs    : Specifies the number of MBs to be refreshed from nFirstGOB \n *               and nFirstMB\n */\ntypedef struct OMX_VIDEO_PARAM_VIDEOFASTUPDATETYPE {\n    OMX_U32 nSize;            \n    OMX_VERSIONTYPE nVersion; \n    OMX_U32 nPortIndex;       \n    OMX_BOOL bEnableVFU;      \n    OMX_U32 nFirstGOB;                            \n    OMX_U32 nFirstMB;                            \n    OMX_U32 nNumMBs;                                  \n} OMX_VIDEO_PARAM_VIDEOFASTUPDATETYPE;\n\n\n/** \n * Enumeration of possible bitrate control types \n */\ntypedef enum OMX_VIDEO_CONTROLRATETYPE {\n    OMX_Video_ControlRateDisable,\n    OMX_Video_ControlRateVariable,\n    OMX_Video_ControlRateConstant,\n    OMX_Video_ControlRateVariableSkipFrames,\n    OMX_Video_ControlRateConstantSkipFrames,\n    OMX_Video_ControlRateKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_Video_ControlRateVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_Video_ControlRateMax = 0x7FFFFFFF\n} OMX_VIDEO_CONTROLRATETYPE;\n\n\n/** \n * Structure for configuring bitrate mode of a codec. \n *\n * STRUCT MEMBERS:\n *  nSize          : Size of the struct in bytes\n *  nVersion       : OMX spec version info\n *  nPortIndex     : Port that this struct applies to\n *  eControlRate   : Control rate type enum\n *  nTargetBitrate : Target bitrate to encode with\n */\ntypedef struct OMX_VIDEO_PARAM_BITRATETYPE {\n    OMX_U32 nSize;                          \n    OMX_VERSIONTYPE nVersion;               \n    OMX_U32 nPortIndex;                     \n    OMX_VIDEO_CONTROLRATETYPE eControlRate; \n    OMX_U32 nTargetBitrate;                 \n} OMX_VIDEO_PARAM_BITRATETYPE;\n\n\n/** \n * Enumeration of possible motion vector (MV) types \n */\ntypedef enum OMX_VIDEO_MOTIONVECTORTYPE {\n    OMX_Video_MotionVectorPixel,\n    OMX_Video_MotionVectorHalfPel,\n    OMX_Video_MotionVectorQuarterPel,\n    OMX_Video_MotionVectorEighthPel,\n    OMX_Video_MotionVectorKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_Video_MotionVectorVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_Video_MotionVectorMax = 0x7FFFFFFF\n} OMX_VIDEO_MOTIONVECTORTYPE;\n\n\n/**\n * Structure for configuring the number of motion vectors used as well\n * as their accuracy.\n * \n * STRUCT MEMBERS:\n *  nSize            : Size of the struct in bytes\n *  nVersion         : OMX spec version info\n *  nPortIndex       : port that this structure applies to\n *  eAccuracy        : Enumerated MV accuracy\n *  bUnrestrictedMVs : Allow unrestricted MVs\n *  bFourMV          : Allow use of 4 MVs\n *  sXSearchRange    : Search range in horizontal direction for MVs\n *  sYSearchRange    : Search range in vertical direction for MVs\n */\ntypedef struct OMX_VIDEO_PARAM_MOTIONVECTORTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_VIDEO_MOTIONVECTORTYPE eAccuracy;\n    OMX_BOOL bUnrestrictedMVs;\n    OMX_BOOL bFourMV;\n    OMX_S32 sXSearchRange;\n    OMX_S32 sYSearchRange;\n} OMX_VIDEO_PARAM_MOTIONVECTORTYPE;\n\n\n/** \n * Enumeration of possible methods to use for Intra Refresh \n */\ntypedef enum OMX_VIDEO_INTRAREFRESHTYPE {\n    OMX_VIDEO_IntraRefreshCyclic,\n    OMX_VIDEO_IntraRefreshAdaptive,\n    OMX_VIDEO_IntraRefreshBoth,\n    OMX_VIDEO_IntraRefreshKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_IntraRefreshVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_IntraRefreshRandom,\n    OMX_VIDEO_IntraRefreshMax = 0x7FFFFFFF\n} OMX_VIDEO_INTRAREFRESHTYPE;\n\n\n/**\n * Structure for configuring intra refresh mode \n * \n * STRUCT MEMBERS:\n *  nSize        : Size of the structure in bytes\n *  nVersion     : OMX specification version information\n *  nPortIndex   : Port that this structure applies to\n *  eRefreshMode : Cyclic, Adaptive, or Both\n *  nAirMBs      : Number of intra macroblocks to refresh in a frame when \n *                 AIR is enabled\n *  nAirRef      : Number of times a motion marked macroblock has to be  \n *                 intra coded\n *  nCirMBs      : Number of consecutive macroblocks to be coded as \"intra\"  \n *                 when CIR is enabled\n */\ntypedef struct OMX_VIDEO_PARAM_INTRAREFRESHTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_VIDEO_INTRAREFRESHTYPE eRefreshMode;\n    OMX_U32 nAirMBs;\n    OMX_U32 nAirRef;\n    OMX_U32 nCirMBs;\n} OMX_VIDEO_PARAM_INTRAREFRESHTYPE;\n\n\n/**\n * Structure for enabling various error correction methods for video \n * compression.\n *\n * STRUCT MEMBERS:\n *  nSize                   : Size of the structure in bytes\n *  nVersion                : OMX specification version information \n *  nPortIndex              : Port that this structure applies to \n *  bEnableHEC              : Enable/disable header extension codes (HEC)\n *  bEnableResync           : Enable/disable resynchronization markers\n *  nResynchMarkerSpacing   : Resynch markers interval (in bits) to be \n *                            applied in the stream \n *  bEnableDataPartitioning : Enable/disable data partitioning \n *  bEnableRVLC             : Enable/disable reversible variable length \n *                            coding\n */\ntypedef struct OMX_VIDEO_PARAM_ERRORCORRECTIONTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnableHEC;\n    OMX_BOOL bEnableResync;\n    OMX_U32  nResynchMarkerSpacing;\n    OMX_BOOL bEnableDataPartitioning;\n    OMX_BOOL bEnableRVLC;\n} OMX_VIDEO_PARAM_ERRORCORRECTIONTYPE;\n\n\n/** \n * Configuration of variable block-size motion compensation (VBSMC) \n * \n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information \n *  nPortIndex : Port that this structure applies to\n *  b16x16     : Enable inter block search 16x16\n *  b16x8      : Enable inter block search 16x8\n *  b8x16      : Enable inter block search 8x16\n *  b8x8       : Enable inter block search 8x8\n *  b8x4       : Enable inter block search 8x4\n *  b4x8       : Enable inter block search 4x8\n *  b4x4       : Enable inter block search 4x4\n */\ntypedef struct OMX_VIDEO_PARAM_VBSMCTYPE {\n    OMX_U32 nSize; \n    OMX_VERSIONTYPE nVersion; \n    OMX_U32 nPortIndex;       \n    OMX_BOOL b16x16; \n    OMX_BOOL b16x8; \n    OMX_BOOL b8x16;\n    OMX_BOOL b8x8;\n    OMX_BOOL b8x4;\n    OMX_BOOL b4x8;\n    OMX_BOOL b4x4;\n} OMX_VIDEO_PARAM_VBSMCTYPE;\n\n\n/** \n * H.263 profile types, each profile indicates support for various \n * performance bounds and different annexes.\n *\n * ENUMS:\n *  Baseline           : Baseline Profile: H.263 (V1), no optional modes                                                    \n *  H320 Coding        : H.320 Coding Efficiency Backward Compatibility \n *                       Profile: H.263+ (V2), includes annexes I, J, L.4\n *                       and T\n *  BackwardCompatible : Backward Compatibility Profile: H.263 (V1), \n *                       includes annex F                                    \n *  ISWV2              : Interactive Streaming Wireless Profile: H.263+ \n *                       (V2), includes annexes I, J, K and T                 \n *  ISWV3              : Interactive Streaming Wireless Profile: H.263++  \n *                       (V3), includes profile 3 and annexes V and W.6.3.8   \n *  HighCompression    : Conversational High Compression Profile: H.263++  \n *                       (V3), includes profiles 1 & 2 and annexes D and U   \n *  Internet           : Conversational Internet Profile: H.263++ (V3),  \n *                       includes profile 5 and annex K                       \n *  Interlace          : Conversational Interlace Profile: H.263++ (V3),  \n *                       includes profile 5 and annex W.6.3.11               \n *  HighLatency        : High Latency Profile: H.263++ (V3), includes  \n *                       profile 6 and annexes O.1 and P.5                       \n */\ntypedef enum OMX_VIDEO_H263PROFILETYPE {\n    OMX_VIDEO_H263ProfileBaseline            = 0x01,        \n    OMX_VIDEO_H263ProfileH320Coding          = 0x02,          \n    OMX_VIDEO_H263ProfileBackwardCompatible  = 0x04,  \n    OMX_VIDEO_H263ProfileISWV2               = 0x08,               \n    OMX_VIDEO_H263ProfileISWV3               = 0x10,               \n    OMX_VIDEO_H263ProfileHighCompression     = 0x20,     \n    OMX_VIDEO_H263ProfileInternet            = 0x40,            \n    OMX_VIDEO_H263ProfileInterlace           = 0x80,           \n    OMX_VIDEO_H263ProfileHighLatency         = 0x100,         \n    OMX_VIDEO_H263ProfileKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_H263ProfileVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_H263ProfileMax                 = 0x7FFFFFFF  \n} OMX_VIDEO_H263PROFILETYPE;\n\n\n/** \n * H.263 level types, each level indicates support for various frame sizes, \n * bit rates, decoder frame rates.\n */\ntypedef enum OMX_VIDEO_H263LEVELTYPE {\n    OMX_VIDEO_H263Level10  = 0x01,  \n    OMX_VIDEO_H263Level20  = 0x02,      \n    OMX_VIDEO_H263Level30  = 0x04,      \n    OMX_VIDEO_H263Level40  = 0x08,      \n    OMX_VIDEO_H263Level45  = 0x10,      \n    OMX_VIDEO_H263Level50  = 0x20,      \n    OMX_VIDEO_H263Level60  = 0x40,      \n    OMX_VIDEO_H263Level70  = 0x80, \n    OMX_VIDEO_H263LevelKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_H263LevelVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_H263LevelMax = 0x7FFFFFFF  \n} OMX_VIDEO_H263LEVELTYPE;\n\n\n/** \n * Specifies the picture type. These values should be OR'd to signal all \n * pictures types which are allowed.\n *\n * ENUMS:\n *  Generic Picture Types:          I, P and B\n *  H.263 Specific Picture Types:   SI and SP\n *  H.264 Specific Picture Types:   EI and EP\n *  MPEG-4 Specific Picture Types:  S\n */\ntypedef enum OMX_VIDEO_PICTURETYPE {\n    OMX_VIDEO_PictureTypeI   = 0x01,\n    OMX_VIDEO_PictureTypeP   = 0x02,\n    OMX_VIDEO_PictureTypeB   = 0x04,\n    OMX_VIDEO_PictureTypeSI  = 0x08,\n    OMX_VIDEO_PictureTypeSP  = 0x10,\n    OMX_VIDEO_PictureTypeEI  = 0x11,\n    OMX_VIDEO_PictureTypeEP  = 0x12,\n    OMX_VIDEO_PictureTypeS   = 0x14,\n    OMX_VIDEO_PictureTypeKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_PictureTypeVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_PictureTypeMax = 0x7FFFFFFF\n} OMX_VIDEO_PICTURETYPE;\n\n\n/** \n * H.263 Params \n *\n * STRUCT MEMBERS:\n *  nSize                    : Size of the structure in bytes\n *  nVersion                 : OMX specification version information \n *  nPortIndex               : Port that this structure applies to\n *  nPFrames                 : Number of P frames between each I frame\n *  nBFrames                 : Number of B frames between each I frame\n *  eProfile                 : H.263 profile(s) to use\n *  eLevel                   : H.263 level(s) to use\n *  bPLUSPTYPEAllowed        : Indicating that it is allowed to use PLUSPTYPE \n *                             (specified in the 1998 version of H.263) to \n *                             indicate custom picture sizes or clock \n *                             frequencies \n *  nAllowedPictureTypes     : Specifies the picture types allowed in the \n *                             bitstream\n *  bForceRoundingTypeToZero : value of the RTYPE bit (bit 6 of MPPTYPE) is \n *                             not constrained. It is recommended to change \n *                             the value of the RTYPE bit for each reference \n *                             picture in error-free communication\n *  nPictureHeaderRepetition : Specifies the frequency of picture header \n *                             repetition\n *  nGOBHeaderInterval       : Specifies the interval of non-empty GOB  \n *                             headers in units of GOBs\n */\ntypedef struct OMX_VIDEO_PARAM_H263TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nPFrames;\n    OMX_U32 nBFrames;\n    OMX_VIDEO_H263PROFILETYPE eProfile;\n\tOMX_VIDEO_H263LEVELTYPE eLevel;\n    OMX_BOOL bPLUSPTYPEAllowed;\n    OMX_U32 nAllowedPictureTypes;\n    OMX_BOOL bForceRoundingTypeToZero;\n    OMX_U32 nPictureHeaderRepetition;\n    OMX_U32 nGOBHeaderInterval;\n} OMX_VIDEO_PARAM_H263TYPE;\n\n\n/** \n * MPEG-2 profile types, each profile indicates support for various \n * performance bounds and different annexes.\n */\ntypedef enum OMX_VIDEO_MPEG2PROFILETYPE {\n    OMX_VIDEO_MPEG2ProfileSimple = 0,  /**< Simple Profile */\n    OMX_VIDEO_MPEG2ProfileMain,        /**< Main Profile */\n    OMX_VIDEO_MPEG2Profile422,         /**< 4:2:2 Profile */\n    OMX_VIDEO_MPEG2ProfileSNR,         /**< SNR Profile */\n    OMX_VIDEO_MPEG2ProfileSpatial,     /**< Spatial Profile */\n    OMX_VIDEO_MPEG2ProfileHigh,        /**< High Profile */\n    OMX_VIDEO_MPEG2ProfileKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_MPEG2ProfileVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_MPEG2ProfileMax = 0x7FFFFFFF  \n} OMX_VIDEO_MPEG2PROFILETYPE;\n\n\n/** \n * MPEG-2 level types, each level indicates support for various frame \n * sizes, bit rates, decoder frame rates.  No need \n */\ntypedef enum OMX_VIDEO_MPEG2LEVELTYPE {\n    OMX_VIDEO_MPEG2LevelLL = 0,  /**< Low Level */ \n    OMX_VIDEO_MPEG2LevelML,      /**< Main Level */ \n    OMX_VIDEO_MPEG2LevelH14,     /**< High 1440 */ \n    OMX_VIDEO_MPEG2LevelHL,      /**< High Level */   \n    OMX_VIDEO_MPEG2LevelKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_MPEG2LevelVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_MPEG2LevelMax = 0x7FFFFFFF  \n} OMX_VIDEO_MPEG2LEVELTYPE;\n\n\n/** \n * MPEG-2 params \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nPFrames   : Number of P frames between each I frame\n *  nBFrames   : Number of B frames between each I frame\n *  eProfile   : MPEG-2 profile(s) to use\n *  eLevel     : MPEG-2 levels(s) to use\n */\ntypedef struct OMX_VIDEO_PARAM_MPEG2TYPE {\n    OMX_U32 nSize;           \n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;      \n    OMX_U32 nPFrames;        \n    OMX_U32 nBFrames;        \n    OMX_VIDEO_MPEG2PROFILETYPE eProfile;\n\tOMX_VIDEO_MPEG2LEVELTYPE eLevel;   \n} OMX_VIDEO_PARAM_MPEG2TYPE;\n\n\n/** \n * MPEG-4 profile types, each profile indicates support for various \n * performance bounds and different annexes.\n * \n * ENUMS:\n *  - Simple Profile, Levels 1-3\n *  - Simple Scalable Profile, Levels 1-2\n *  - Core Profile, Levels 1-2\n *  - Main Profile, Levels 2-4\n *  - N-bit Profile, Level 2\n *  - Scalable Texture Profile, Level 1\n *  - Simple Face Animation Profile, Levels 1-2\n *  - Simple Face and Body Animation (FBA) Profile, Levels 1-2\n *  - Basic Animated Texture Profile, Levels 1-2\n *  - Hybrid Profile, Levels 1-2\n *  - Advanced Real Time Simple Profiles, Levels 1-4\n *  - Core Scalable Profile, Levels 1-3\n *  - Advanced Coding Efficiency Profile, Levels 1-4\n *  - Advanced Core Profile, Levels 1-2\n *  - Advanced Scalable Texture, Levels 2-3\n */\ntypedef enum OMX_VIDEO_MPEG4PROFILETYPE {\n    OMX_VIDEO_MPEG4ProfileSimple           = 0x01,        \n    OMX_VIDEO_MPEG4ProfileSimpleScalable   = 0x02,    \n    OMX_VIDEO_MPEG4ProfileCore             = 0x04,              \n    OMX_VIDEO_MPEG4ProfileMain             = 0x08,             \n    OMX_VIDEO_MPEG4ProfileNbit             = 0x10,              \n    OMX_VIDEO_MPEG4ProfileScalableTexture  = 0x20,   \n    OMX_VIDEO_MPEG4ProfileSimpleFace       = 0x40,        \n    OMX_VIDEO_MPEG4ProfileSimpleFBA        = 0x80,         \n    OMX_VIDEO_MPEG4ProfileBasicAnimated    = 0x100,     \n    OMX_VIDEO_MPEG4ProfileHybrid           = 0x200,            \n    OMX_VIDEO_MPEG4ProfileAdvancedRealTime = 0x400,  \n    OMX_VIDEO_MPEG4ProfileCoreScalable     = 0x800,      \n    OMX_VIDEO_MPEG4ProfileAdvancedCoding   = 0x1000,    \n    OMX_VIDEO_MPEG4ProfileAdvancedCore     = 0x2000,      \n    OMX_VIDEO_MPEG4ProfileAdvancedScalable = 0x4000,\n    OMX_VIDEO_MPEG4ProfileAdvancedSimple   = 0x8000,\n    OMX_VIDEO_MPEG4ProfileKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_MPEG4ProfileVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_MPEG4ProfileMax              = 0x7FFFFFFF  \n} OMX_VIDEO_MPEG4PROFILETYPE;\n\n\n/** \n * MPEG-4 level types, each level indicates support for various frame \n * sizes, bit rates, decoder frame rates.  No need \n */\ntypedef enum OMX_VIDEO_MPEG4LEVELTYPE {\n    OMX_VIDEO_MPEG4Level0  = 0x01,   /**< Level 0 */   \n    OMX_VIDEO_MPEG4Level0b = 0x02,   /**< Level 0b */   \n    OMX_VIDEO_MPEG4Level1  = 0x04,   /**< Level 1 */ \n    OMX_VIDEO_MPEG4Level2  = 0x08,   /**< Level 2 */ \n    OMX_VIDEO_MPEG4Level3  = 0x10,   /**< Level 3 */ \n    OMX_VIDEO_MPEG4Level4  = 0x20,   /**< Level 4 */  \n    OMX_VIDEO_MPEG4Level4a = 0x40,   /**< Level 4a */  \n    OMX_VIDEO_MPEG4Level5  = 0x80,   /**< Level 5 */  \n    OMX_VIDEO_MPEG4LevelKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_MPEG4LevelVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_MPEG4LevelMax = 0x7FFFFFFF  \n} OMX_VIDEO_MPEG4LEVELTYPE;\n\n\n/** \n * MPEG-4 configuration.  This structure handles configuration options\n * which are specific to MPEG4 algorithms\n *\n * STRUCT MEMBERS:\n *  nSize                : Size of the structure in bytes\n *  nVersion             : OMX specification version information\n *  nPortIndex           : Port that this structure applies to\n *  nSliceHeaderSpacing  : Number of macroblocks between slice header (H263+ \n *                         Annex K). Put zero if not used\n *  bSVH                 : Enable Short Video Header mode\n *  bGov                 : Flag to enable GOV\n *  nPFrames             : Number of P frames between each I frame (also called \n *                         GOV period)\n *  nBFrames             : Number of B frames between each I frame\n *  nIDCVLCThreshold     : Value of intra DC VLC threshold\n *  bACPred              : Flag to use ac prediction\n *  nMaxPacketSize       : Maximum size of packet in bytes.\n *  nTimeIncRes          : Used to pass VOP time increment resolution for MPEG4. \n *                         Interpreted as described in MPEG4 standard.\n *  eProfile             : MPEG-4 profile(s) to use.\n *  eLevel               : MPEG-4 level(s) to use.\n *  nAllowedPictureTypes : Specifies the picture types allowed in the bitstream\n *  nHeaderExtension     : Specifies the number of consecutive video packet\n *                         headers within a VOP\n *  bReversibleVLC       : Specifies whether reversible variable length coding \n *                         is in use\n */\ntypedef struct OMX_VIDEO_PARAM_MPEG4TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nSliceHeaderSpacing;\n    OMX_BOOL bSVH;\n    OMX_BOOL bGov;\n    OMX_U32 nPFrames;\n    OMX_U32 nBFrames;\n    OMX_U32 nIDCVLCThreshold;\n    OMX_BOOL bACPred;\n    OMX_U32 nMaxPacketSize;\n    OMX_U32 nTimeIncRes;\n    OMX_VIDEO_MPEG4PROFILETYPE eProfile;\n    OMX_VIDEO_MPEG4LEVELTYPE eLevel;\n    OMX_U32 nAllowedPictureTypes;\n    OMX_U32 nHeaderExtension;\n    OMX_BOOL bReversibleVLC;\n} OMX_VIDEO_PARAM_MPEG4TYPE;\n\n\n/** \n * WMV Versions \n */\ntypedef enum OMX_VIDEO_WMVFORMATTYPE {\n    OMX_VIDEO_WMVFormatUnused = 0x01,   /**< Format unused or unknown */\n    OMX_VIDEO_WMVFormat7      = 0x02,   /**< Windows Media Video format 7 */\n    OMX_VIDEO_WMVFormat8      = 0x04,   /**< Windows Media Video format 8 */\n    OMX_VIDEO_WMVFormat9      = 0x08,   /**< Windows Media Video format 9 */\n    OMX_VIDEO_WMFFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_WMFFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_WMVFormatMax    = 0x7FFFFFFF\n} OMX_VIDEO_WMVFORMATTYPE;\n\n\n/** \n * WMV Params \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  eFormat    : Version of WMV stream / data\n */\ntypedef struct OMX_VIDEO_PARAM_WMVTYPE {\n    OMX_U32 nSize; \n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_VIDEO_WMVFORMATTYPE eFormat;\n} OMX_VIDEO_PARAM_WMVTYPE;\n\n\n/** \n * Real Video Version \n */\ntypedef enum OMX_VIDEO_RVFORMATTYPE {\n    OMX_VIDEO_RVFormatUnused = 0, /**< Format unused or unknown */\n    OMX_VIDEO_RVFormat8,          /**< Real Video format 8 */\n    OMX_VIDEO_RVFormat9,          /**< Real Video format 9 */\n    OMX_VIDEO_RVFormatG2,         /**< Real Video Format G2 */\n    OMX_VIDEO_RVFormatKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_RVFormatVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_RVFormatMax = 0x7FFFFFFF\n} OMX_VIDEO_RVFORMATTYPE;\n\n\n/** \n * Real Video Params \n *\n * STUCT MEMBERS:\n *  nSize              : Size of the structure in bytes\n *  nVersion           : OMX specification version information \n *  nPortIndex         : Port that this structure applies to\n *  eFormat            : Version of RV stream / data\n *  nBitsPerPixel      : Bits per pixel coded in the frame\n *  nPaddedWidth       : Padded width in pixel of a video frame\n *  nPaddedHeight      : Padded Height in pixels of a video frame\n *  nFrameRate         : Rate of video in frames per second\n *  nBitstreamFlags    : Flags which internal information about the bitstream\n *  nBitstreamVersion  : Bitstream version\n *  nMaxEncodeFrameSize: Max encoded frame size\n *  bEnablePostFilter  : Turn on/off post filter\n *  bEnableTemporalInterpolation : Turn on/off temporal interpolation\n *  bEnableLatencyMode : When enabled, the decoder does not display a decoded \n *                       frame until it has detected that no enhancement layer \n *  \t\t\t\t\t frames or dependent B frames will be coming. This \n *  \t\t\t\t\t detection usually occurs when a subsequent non-B \n *  \t\t\t\t\t frame is encountered \n */\ntypedef struct OMX_VIDEO_PARAM_RVTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_VIDEO_RVFORMATTYPE eFormat;\n    OMX_U16 nBitsPerPixel;\n    OMX_U16 nPaddedWidth;\n    OMX_U16 nPaddedHeight;\n    OMX_U32 nFrameRate;\n    OMX_U32 nBitstreamFlags;\n    OMX_U32 nBitstreamVersion;\n    OMX_U32 nMaxEncodeFrameSize;\n    OMX_BOOL bEnablePostFilter;\n    OMX_BOOL bEnableTemporalInterpolation;\n    OMX_BOOL bEnableLatencyMode;\n} OMX_VIDEO_PARAM_RVTYPE;\n\n\n/** \n * AVC profile types, each profile indicates support for various \n * performance bounds and different annexes.\n */\ntypedef enum OMX_VIDEO_AVCPROFILETYPE {\n    OMX_VIDEO_AVCProfileBaseline = 0x01,   /**< Baseline profile */\n    OMX_VIDEO_AVCProfileMain     = 0x02,   /**< Main profile */\n    OMX_VIDEO_AVCProfileExtended = 0x04,   /**< Extended profile */\n    OMX_VIDEO_AVCProfileHigh     = 0x08,   /**< High profile */\n    OMX_VIDEO_AVCProfileHigh10   = 0x10,   /**< High 10 profile */\n    OMX_VIDEO_AVCProfileHigh422  = 0x20,   /**< High 4:2:2 profile */\n    OMX_VIDEO_AVCProfileHigh444  = 0x40,   /**< High 4:4:4 profile */\n    OMX_VIDEO_AVCProfileKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_AVCProfileVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_AVCProfileMax      = 0x7FFFFFFF  \n} OMX_VIDEO_AVCPROFILETYPE;\n\n\n/** \n * AVC level types, each level indicates support for various frame sizes, \n * bit rates, decoder frame rates.  No need \n */\ntypedef enum OMX_VIDEO_AVCLEVELTYPE {\n    OMX_VIDEO_AVCLevel1   = 0x01,     /**< Level 1 */\n    OMX_VIDEO_AVCLevel1b  = 0x02,     /**< Level 1b */\n    OMX_VIDEO_AVCLevel11  = 0x04,     /**< Level 1.1 */\n    OMX_VIDEO_AVCLevel12  = 0x08,     /**< Level 1.2 */\n    OMX_VIDEO_AVCLevel13  = 0x10,     /**< Level 1.3 */\n    OMX_VIDEO_AVCLevel2   = 0x20,     /**< Level 2 */\n    OMX_VIDEO_AVCLevel21  = 0x40,     /**< Level 2.1 */\n    OMX_VIDEO_AVCLevel22  = 0x80,     /**< Level 2.2 */\n    OMX_VIDEO_AVCLevel3   = 0x100,    /**< Level 3 */\n    OMX_VIDEO_AVCLevel31  = 0x200,    /**< Level 3.1 */\n    OMX_VIDEO_AVCLevel32  = 0x400,    /**< Level 3.2 */\n    OMX_VIDEO_AVCLevel4   = 0x800,    /**< Level 4 */\n    OMX_VIDEO_AVCLevel41  = 0x1000,   /**< Level 4.1 */\n    OMX_VIDEO_AVCLevel42  = 0x2000,   /**< Level 4.2 */\n    OMX_VIDEO_AVCLevel5   = 0x4000,   /**< Level 5 */\n    OMX_VIDEO_AVCLevel51  = 0x8000,   /**< Level 5.1 */\n    OMX_VIDEO_AVCLevel52  = 0x10000,   /**< Level 5.2 */\n    OMX_VIDEO_AVCLevelKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_AVCLevelVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_AVCLevelMax = 0x7FFFFFFF  \n} OMX_VIDEO_AVCLEVELTYPE;\n\n\n/** \n * AVC loop filter modes \n *\n * OMX_VIDEO_AVCLoopFilterEnable               : Enable\n * OMX_VIDEO_AVCLoopFilterDisable              : Disable\n * OMX_VIDEO_AVCLoopFilterDisableSliceBoundary : Disabled on slice boundaries\n */\ntypedef enum OMX_VIDEO_AVCLOOPFILTERTYPE {\n    OMX_VIDEO_AVCLoopFilterEnable = 0,\n    OMX_VIDEO_AVCLoopFilterDisable,\n    OMX_VIDEO_AVCLoopFilterDisableSliceBoundary,\n    OMX_VIDEO_AVCLoopFilterKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_AVCLoopFilterVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_AVCLoopFilterMax = 0x7FFFFFFF\n} OMX_VIDEO_AVCLOOPFILTERTYPE;\n\n\n/** \n * AVC params \n *\n * STRUCT MEMBERS:\n *  nSize                     : Size of the structure in bytes\n *  nVersion                  : OMX specification version information\n *  nPortIndex                : Port that this structure applies to\n *  nSliceHeaderSpacing       : Number of macroblocks between slice header, put  \n *                              zero if not used\n *  nPFrames                  : Number of P frames between each I frame\n *  nBFrames                  : Number of B frames between each I frame\n *  bUseHadamard              : Enable/disable Hadamard transform\n *  nRefFrames                : Max number of reference frames to use for inter\n *                              motion search (1-16)\n *  nRefIdxTrailing           : Pic param set ref frame index (index into ref\n *                              frame buffer of trailing frames list), B frame\n *                              support\n *  nRefIdxForward            : Pic param set ref frame index (index into ref\n *                              frame buffer of forward frames list), B frame\n *                              support\n *  bEnableUEP                : Enable/disable unequal error protection. This \n *                              is only valid of data partitioning is enabled.\n *  bEnableFMO                : Enable/disable flexible macroblock ordering\n *  bEnableASO                : Enable/disable arbitrary slice ordering\n *  bEnableRS                 : Enable/disable sending of redundant slices\n *  eProfile                  : AVC profile(s) to use\n *  eLevel                    : AVC level(s) to use\n *  nAllowedPictureTypes      : Specifies the picture types allowed in the \n *                              bitstream\n *  bFrameMBsOnly             : specifies that every coded picture of the \n *                              coded video sequence is a coded frame \n *                              containing only frame macroblocks\n *  bMBAFF                    : Enable/disable switching between frame and \n *                              field macroblocks within a picture\n *  bEntropyCodingCABAC       : Entropy decoding method to be applied for the \n *                              syntax elements for which two descriptors appear \n *                              in the syntax tables\n *  bWeightedPPrediction      : Enable/disable weighted prediction shall not \n *                              be applied to P and SP slices\n *  nWeightedBipredicitonMode : Default weighted prediction is applied to B \n *                              slices \n *  bconstIpred               : Enable/disable intra prediction\n *  bDirect8x8Inference       : Specifies the method used in the derivation \n *                              process for luma motion vectors for B_Skip, \n *                              B_Direct_16x16 and B_Direct_8x8 as specified \n *                              in subclause 8.4.1.2 of the AVC spec \n *  bDirectSpatialTemporal    : Flag indicating spatial or temporal direct\n *                              mode used in B slice coding (related to \n *                              bDirect8x8Inference) . Spatial direct mode is \n *                              more common and should be the default.\n *  nCabacInitIdx             : Index used to init CABAC contexts\n *  eLoopFilterMode           : Enable/disable loop filter\n */\ntypedef struct OMX_VIDEO_PARAM_AVCTYPE {\n    OMX_U32 nSize;                 \n    OMX_VERSIONTYPE nVersion;      \n    OMX_U32 nPortIndex;            \n    OMX_U32 nSliceHeaderSpacing;  \n    OMX_U32 nPFrames;     \n    OMX_U32 nBFrames;     \n    OMX_BOOL bUseHadamard;\n    OMX_U32 nRefFrames;  \n\tOMX_U32 nRefIdx10ActiveMinus1;\n\tOMX_U32 nRefIdx11ActiveMinus1;\n    OMX_BOOL bEnableUEP;  \n    OMX_BOOL bEnableFMO;  \n    OMX_BOOL bEnableASO;  \n    OMX_BOOL bEnableRS;   \n    OMX_VIDEO_AVCPROFILETYPE eProfile;\n\tOMX_VIDEO_AVCLEVELTYPE eLevel; \n    OMX_U32 nAllowedPictureTypes;  \n\tOMX_BOOL bFrameMBsOnly;        \t\t\t\t\t\t\t\t\t\n    OMX_BOOL bMBAFF;               \n    OMX_BOOL bEntropyCodingCABAC;  \n    OMX_BOOL bWeightedPPrediction; \n    OMX_U32 nWeightedBipredicitonMode; \n    OMX_BOOL bconstIpred ;\n    OMX_BOOL bDirect8x8Inference;  \n\tOMX_BOOL bDirectSpatialTemporal;\n\tOMX_U32 nCabacInitIdc;\n\tOMX_VIDEO_AVCLOOPFILTERTYPE eLoopFilterMode;\n} OMX_VIDEO_PARAM_AVCTYPE;\n\ntypedef struct OMX_VIDEO_PARAM_PROFILELEVELTYPE {\n   OMX_U32 nSize;                 \n   OMX_VERSIONTYPE nVersion;      \n   OMX_U32 nPortIndex;            \n   OMX_U32 eProfile;      /**< type is OMX_VIDEO_AVCPROFILETYPE, OMX_VIDEO_H263PROFILETYPE, \n                                 or OMX_VIDEO_MPEG4PROFILETYPE depending on context */\n   OMX_U32 eLevel;        /**< type is OMX_VIDEO_AVCLEVELTYPE, OMX_VIDEO_H263LEVELTYPE, \n                                 or OMX_VIDEO_MPEG4PROFILETYPE depending on context */\n   OMX_U32 nProfileIndex; /**< Used to query for individual profile support information,\n                               This parameter is valid only for \n                               OMX_IndexParamVideoProfileLevelQuerySupported index,\n                               For all other indices this parameter is to be ignored. */\n} OMX_VIDEO_PARAM_PROFILELEVELTYPE;\n\n/** \n * Structure for dynamically configuring bitrate mode of a codec. \n *\n * STRUCT MEMBERS:\n *  nSize          : Size of the struct in bytes\n *  nVersion       : OMX spec version info\n *  nPortIndex     : Port that this struct applies to\n *  nEncodeBitrate : Target average bitrate to be generated in bps\n */\ntypedef struct OMX_VIDEO_CONFIG_BITRATETYPE {\n    OMX_U32 nSize;                          \n    OMX_VERSIONTYPE nVersion;               \n    OMX_U32 nPortIndex;                     \n    OMX_U32 nEncodeBitrate;                 \n} OMX_VIDEO_CONFIG_BITRATETYPE;\n\n/** \n * Defines Encoder Frame Rate setting\n *\n * STRUCT MEMBERS:\n *  nSize            : Size of the structure in bytes\n *  nVersion         : OMX specification version information \n *  nPortIndex       : Port that this structure applies to\n *  xEncodeFramerate : Encoding framerate represented in Q16 format\n */\ntypedef struct OMX_CONFIG_FRAMERATETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 xEncodeFramerate; /* Q16 format */\n} OMX_CONFIG_FRAMERATETYPE;\n\ntypedef struct OMX_CONFIG_INTRAREFRESHVOPTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL IntraRefreshVOP;\n} OMX_CONFIG_INTRAREFRESHVOPTYPE;\n\ntypedef struct OMX_CONFIG_MACROBLOCKERRORMAPTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nErrMapSize;           /* Size of the Error Map in bytes */\n    OMX_U8  ErrMap[1];             /* Error map hint */\n} OMX_CONFIG_MACROBLOCKERRORMAPTYPE;\n\ntypedef struct OMX_CONFIG_MBERRORREPORTINGTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bEnabled;\n} OMX_CONFIG_MBERRORREPORTINGTYPE;\n\ntypedef struct OMX_PARAM_MACROBLOCKSTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nMacroblocks;\n} OMX_PARAM_MACROBLOCKSTYPE;\n\n/** \n * AVC Slice Mode modes \n *\n * OMX_VIDEO_SLICEMODE_AVCDefault   : Normal frame encoding, one slice per frame\n * OMX_VIDEO_SLICEMODE_AVCMBSlice   : NAL mode, number of MBs per frame\n * OMX_VIDEO_SLICEMODE_AVCByteSlice : NAL mode, number of bytes per frame\n */\ntypedef enum OMX_VIDEO_AVCSLICEMODETYPE {\n    OMX_VIDEO_SLICEMODE_AVCDefault = 0,\n    OMX_VIDEO_SLICEMODE_AVCMBSlice,\n    OMX_VIDEO_SLICEMODE_AVCByteSlice,\n    OMX_VIDEO_SLICEMODE_AVCKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ \n    OMX_VIDEO_SLICEMODE_AVCVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */\n    OMX_VIDEO_SLICEMODE_AVCLevelMax = 0x7FFFFFFF\n} OMX_VIDEO_AVCSLICEMODETYPE;\n\n/** \n * AVC FMO Slice Mode Params \n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nNumSliceGroups : Specifies the number of slice groups\n *  nSliceGroupMapType : Specifies the type of slice groups\n *  eSliceMode : Specifies the type of slice\n */\ntypedef struct OMX_VIDEO_PARAM_AVCSLICEFMO {\n    OMX_U32 nSize; \n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U8 nNumSliceGroups;\n    OMX_U8 nSliceGroupMapType;\n    OMX_VIDEO_AVCSLICEMODETYPE eSliceMode;\n} OMX_VIDEO_PARAM_AVCSLICEFMO;\n\n/** \n * AVC IDR Period Configs\n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nIDRPeriod : Specifies periodicity of IDR frames\n *  nPFrames : Specifies internal of coding Intra frames\n */\ntypedef struct OMX_VIDEO_CONFIG_AVCINTRAPERIOD {\n    OMX_U32 nSize; \n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nIDRPeriod;\n    OMX_U32 nPFrames;\n} OMX_VIDEO_CONFIG_AVCINTRAPERIOD;\n\n/** \n * AVC NAL Size Configs\n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nNaluBytes : Specifies the NAL unit size\n */\ntypedef struct OMX_VIDEO_CONFIG_NALSIZE {\n    OMX_U32 nSize; \n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nNaluBytes;\n} OMX_VIDEO_CONFIG_NALSIZE;\n\n\n/**\n * Deinterlace Config\n *\n * STRUCT MEMBERS:\n *  nSize      : Size of the structure in bytes\n *  nVersion   : OMX specification version information\n *  nPortIndex : Port that this structure applies to\n *  nEnable : Specifies to enable deinterlace\n */\ntypedef struct OMX_VIDEO_CONFIG_DEINTERLACE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_U32 nEnable;\n} OMX_VIDEO_CONFIG_DEINTERLACE;\n\n/** @} */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n/* File EOF */\n\n"
  },
  {
    "path": "phonelibs/openmax/include/OMX_VideoExt.h",
    "content": "/*\n * Copyright (c) 2010 The Khronos Group Inc.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject\n * to the following conditions:\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n\n/** OMX_VideoExt.h - OpenMax IL version 1.1.2\n * The OMX_VideoExt header file contains extensions to the\n * definitions used by both the application and the component to\n * access video items.\n */\n\n#ifndef OMX_VideoExt_h\n#define OMX_VideoExt_h\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/* Each OMX header shall include all required header files to allow the\n * header to compile without errors.  The includes below are required\n * for this header file to compile successfully\n */\n#include <OMX_Core.h>\n\n/** NALU Formats */\ntypedef enum OMX_NALUFORMATSTYPE {\n    OMX_NaluFormatStartCodes = 1,\n    OMX_NaluFormatOneNaluPerBuffer = 2,\n    OMX_NaluFormatOneByteInterleaveLength = 4,\n    OMX_NaluFormatTwoByteInterleaveLength = 8,\n    OMX_NaluFormatFourByteInterleaveLength = 16,\n    OMX_NaluFormatCodingMax = 0x7FFFFFFF\n} OMX_NALUFORMATSTYPE;\n\n/** NAL Stream Format */\ntypedef struct OMX_NALSTREAMFORMATTYPE{\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_NALUFORMATSTYPE eNaluFormat;\n} OMX_NALSTREAMFORMATTYPE;\n\n/** VP8 profiles */\ntypedef enum OMX_VIDEO_VP8PROFILETYPE {\n    OMX_VIDEO_VP8ProfileMain = 0x01,\n    OMX_VIDEO_VP8ProfileUnknown = 0x6EFFFFFF,\n    OMX_VIDEO_VP8ProfileMax = 0x7FFFFFFF\n} OMX_VIDEO_VP8PROFILETYPE;\n\n/** VP8 levels */\ntypedef enum OMX_VIDEO_VP8LEVELTYPE {\n    OMX_VIDEO_VP8Level_Version0 = 0x01,\n    OMX_VIDEO_VP8Level_Version1 = 0x02,\n    OMX_VIDEO_VP8Level_Version2 = 0x04,\n    OMX_VIDEO_VP8Level_Version3 = 0x08,\n    OMX_VIDEO_VP8LevelUnknown = 0x6EFFFFFF,\n    OMX_VIDEO_VP8LevelMax = 0x7FFFFFFF\n} OMX_VIDEO_VP8LEVELTYPE;\n\n/** VP8 Param */\ntypedef struct OMX_VIDEO_PARAM_VP8TYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_VIDEO_VP8PROFILETYPE eProfile;\n    OMX_VIDEO_VP8LEVELTYPE eLevel;\n    OMX_U32 nDCTPartitions;\n    OMX_BOOL bErrorResilientMode;\n} OMX_VIDEO_PARAM_VP8TYPE;\n\n/** Structure for configuring VP8 reference frames */\ntypedef struct OMX_VIDEO_VP8REFERENCEFRAMETYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bPreviousFrameRefresh;\n    OMX_BOOL bGoldenFrameRefresh;\n    OMX_BOOL bAlternateFrameRefresh;\n    OMX_BOOL bUsePreviousFrame;\n    OMX_BOOL bUseGoldenFrame;\n    OMX_BOOL bUseAlternateFrame;\n} OMX_VIDEO_VP8REFERENCEFRAMETYPE;\n\n/** Structure for querying VP8 reference frame type */\ntypedef struct OMX_VIDEO_VP8REFERENCEFRAMEINFOTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_BOOL bIsIntraFrame;\n    OMX_BOOL bIsGoldenOrAlternateFrame;\n} OMX_VIDEO_VP8REFERENCEFRAMEINFOTYPE;\n\n/** HEVC Profiles */\ntypedef enum OMX_VIDEO_HEVCPROFILETYPE {\n    OMX_VIDEO_HEVCProfileMain    = 0x01,\n    OMX_VIDEO_HEVCProfileMain10  = 0x02,\n    OMX_VIDEO_HEVCProfileUnknown = 0x6EFFFFFF,\n    OMX_VIDEO_HEVCProfileMax      = 0x7FFFFFFF\n} OMX_VIDEO_HEVCPROFILETYPE;\n\n/** HEVC levels */\ntypedef enum OMX_VIDEO_HEVCLEVELTYPE {\n    OMX_VIDEO_HEVCLevel_Version0  = 0x0,\n    OMX_VIDEO_HEVCMainTierLevel1  = 0x1,\n    OMX_VIDEO_HEVCHighTierLevel1  = 0x2,\n    OMX_VIDEO_HEVCMainTierLevel2  = 0x4,\n    OMX_VIDEO_HEVCHighTierLevel2  = 0x8,\n    OMX_VIDEO_HEVCMainTierLevel21 = 0x10,\n    OMX_VIDEO_HEVCHighTierLevel21 = 0x20,\n    OMX_VIDEO_HEVCMainTierLevel3  = 0x40,\n    OMX_VIDEO_HEVCHighTierLevel3  = 0x80,\n    OMX_VIDEO_HEVCMainTierLevel31 = 0x100,\n    OMX_VIDEO_HEVCHighTierLevel31 = 0x200,\n    OMX_VIDEO_HEVCMainTierLevel4  = 0x400,\n    OMX_VIDEO_HEVCHighTierLevel4  = 0x800,\n    OMX_VIDEO_HEVCMainTierLevel41 = 0x1000,\n    OMX_VIDEO_HEVCHighTierLevel41 = 0x2000,\n    OMX_VIDEO_HEVCMainTierLevel5  = 0x4000,\n    OMX_VIDEO_HEVCHighTierLevel5  = 0x8000,\n    OMX_VIDEO_HEVCMainTierLevel51 = 0x10000,\n    OMX_VIDEO_HEVCHighTierLevel51 = 0x20000,\n    OMX_VIDEO_HEVCMainTierLevel52 = 0x40000,\n    OMX_VIDEO_HEVCHighTierLevel52 = 0x80000,\n    OMX_VIDEO_HEVCMainTierLevel6  = 0x100000,\n    OMX_VIDEO_HEVCHighTierLevel6  = 0x200000,\n    OMX_VIDEO_HEVCMainTierLevel61 = 0x400000,\n    OMX_VIDEO_HEVCHighTierLevel61 = 0x800000,\n    OMX_VIDEO_HEVCMainTierLevel62 = 0x1000000,\n    OMX_VIDEO_HEVCLevelUnknown = 0x6EFFFFFF,\n    OMX_VIDEO_HEVCLevelMax = 0x7FFFFFFF\n} OMX_VIDEO_HEVCLEVELTYPE;\n\n/** HEVC Param */\ntypedef struct OMX_VIDEO_PARAM_HEVCTYPE {\n    OMX_U32 nSize;\n    OMX_VERSIONTYPE nVersion;\n    OMX_U32 nPortIndex;\n    OMX_VIDEO_HEVCPROFILETYPE eProfile;\n    OMX_VIDEO_HEVCLEVELTYPE eLevel;\n} OMX_VIDEO_PARAM_HEVCTYPE;\n\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* OMX_VideoExt_h */\n/* File EOF */\n"
  },
  {
    "path": "phonelibs/qpoases/EXAMPLES/example1.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file EXAMPLES/example1.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tVery simple example for testing qpOASES (using QProblem class).\n */\n\n\n#include <QProblem.hpp>\n\n\n/** Example for qpOASES main function using the QProblem class. */\nint main( )\n{\n\t/* Setup data of first QP. */\n\treal_t H[2*2] = { 1.0, 0.0, 0.0, 0.5 };\n\treal_t A[1*2] = { 1.0, 1.0 };\n\treal_t g[2] = { 1.5, 1.0 };\n\treal_t lb[2] = { 0.5, -2.0 };\n\treal_t ub[2] = { 5.0, 2.0 };\n\treal_t lbA[1] = { -1.0 };\n\treal_t ubA[1] = { 2.0 };\n\n\t/* Setup data of second QP. */\n\treal_t g_new[2] = { 1.0, 1.5 };\n\treal_t lb_new[2] = { 0.0, -1.0 };\n\treal_t ub_new[2] = { 5.0, -0.5 };\n\treal_t lbA_new[1] = { -2.0 };\n\treal_t ubA_new[1] = { 1.0 };\n\n\n\t/* Setting up QProblem object. */\n\tQProblem example( 2,1 );\n\n\t/* Solve first QP. */\n\tint nWSR = 10;\n\texample.init( H,g,A,lb,ub,lbA,ubA, nWSR,0 );\n\n\t/* Solve second QP. */\n\tnWSR = 10;\n\texample.hotstart( g_new,lb_new,ub_new,lbA_new,ubA_new, nWSR,0 );\n\n\treturn 0;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/EXAMPLES/example1b.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file EXAMPLES/example1b.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3\n *\t\\date 2007-2008\n *\n *\tVery simple example for testing qpOASES using the QProblemB class.\n */\n\n\n#include <QProblemB.hpp>\n\n\n/** Example for qpOASES main function using the QProblemB class. */\nint main( )\n{\n\t/* Setup data of first QP. */\n\treal_t H[2*2] = { 1.0, 0.0, 0.0, 0.5 };\n\treal_t g[2] = { 1.5, 1.0 };\n\treal_t lb[2] = { 0.5, -2.0 };\n\treal_t ub[2] = { 5.0, 2.0 };\n\n\t/* Setup data of second QP. */\n\treal_t g_new[2] = { 1.0, 1.5 };\n\treal_t lb_new[2] = { 0.0, -1.0 };\n\treal_t ub_new[2] = { 5.0, -0.5 };\n\n\n\t/* Setting up QProblemB object. */\n\tQProblemB example( 2 );\n\n\t/* Solve first QP. */\n\tint nWSR = 10;\n\texample.init( H,g,lb,ub, nWSR,0 );\n\n\t/* Solve second QP. */\n\tnWSR = 10;\n\texample.hotstart( g_new,lb_new,ub_new, nWSR,0 );\n\n\treturn 0;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/Bounds.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/Bounds.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the Bounds class designed to manage working sets of\n *\tbounds within a QProblem.\n */\n\n\n#ifndef QPOASES_BOUNDS_HPP\n#define QPOASES_BOUNDS_HPP\n\n\n#include <SubjectTo.hpp>\n\n\n\n/** This class manages working sets of bounds by storing\n *\tindex sets and other status information.\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass Bounds : public SubjectTo\n{\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tBounds( );\n\n\t\t/** Copy constructor (deep copy). */\n\t\tBounds(\tconst Bounds& rhs\t/**< Rhs object. */\n\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~Bounds( );\n\n\t\t/** Assignment operator (deep copy). */\n\t\tBounds& operator=(\tconst Bounds& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Pseudo-constructor takes the number of bounds.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue init(\tint n\t/**< Number of bounds. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Initially adds number of a new (i.e. not yet in the list) bound to\n\t\t *  given index set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_SETUP_BOUND_FAILED \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS */\n\t\treturnValue setupBound(\tint _number,\t\t\t\t\t/**< Number of new bound. */\n\t\t\t\t\t\t\t\tSubjectToStatus _status\t\t\t/**< Status of new bound. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Initially adds all numbers of new (i.e. not yet in the list) bounds to\n\t\t *  to the index set of free bounds; the order depends on the SujectToType\n\t\t *  of each index.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_SETUP_BOUND_FAILED */\n\t\treturnValue setupAllFree( );\n\n\n\t\t/** Moves index of a bound from index list of fixed to that of free bounds.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_MOVING_BOUND_FAILED \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\treturnValue moveFixedToFree(\tint _number\t\t\t\t/**< Number of bound to be freed. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Moves index of a bound from index list of free to that of fixed bounds.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_MOVING_BOUND_FAILED \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\treturnValue moveFreeToFixed(\tint _number,\t\t\t/**< Number of bound to be fixed. */\n\t\t\t\t\t\t\t\t\t\tSubjectToStatus _status\t/**< Status of bound to be fixed. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Swaps the indices of two free bounds within the index set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_SWAPINDEX_FAILED */\n\t\treturnValue swapFree(\tint number1,\t\t\t\t\t/**< Number of first constraint or bound. */\n\t\t\t\t\t\t\t\tint number2\t\t\t\t\t\t/**< Number of second constraint or bound. */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns number of variables.\n\t\t *\t\\return Number of variables. */\n\t\tinline int getNV( ) const;\n\n\t\t/** Returns number of implicitly fixed variables.\n\t\t *\t\\return Number of implicitly fixed variables. */\n\t\tinline int getNFV( ) const;\n\n\t\t/** Returns number of bounded (but possibly free) variables.\n\t\t *\t\\return Number of bounded (but possibly free) variables. */\n\t\tinline int getNBV( ) const;\n\n\t\t/** Returns number of unbounded variables.\n\t\t *\t\\return Number of unbounded variables. */\n\t\tinline int getNUV( ) const;\n\n\n\t\t/** Sets number of implicitly fixed variables.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setNFV(\tint n\t/**< Number of implicitly fixed variables. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Sets number of bounded (but possibly free) variables.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setNBV(\tint n\t/**< Number of bounded (but possibly free) variables. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Sets number of unbounded variables.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setNUV(\tint n\t/**< Number of unbounded variables */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns number of free variables.\n\t\t *\t\\return Number of free variables. */\n\t\tinline int getNFR( );\n\n\t\t/** Returns number of fixed variables.\n\t\t *\t\\return Number of fixed variables. */\n\t\tinline int getNFX( );\n\n\n\t\t/** Returns a pointer to free variables index list.\n\t\t *\t\\return Pointer to free variables index list. */\n\t\tinline Indexlist* getFree( );\n\n\t\t/** Returns a pointer to fixed variables index list.\n\t\t *\t\\return Pointer to fixed variables index list. */\n\t\tinline Indexlist* getFixed( );\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\tint nV;\t\t\t\t\t/**< Number of variables (nV = nFV + nBV + nUV). */\n\t\tint nFV;\t\t\t\t/**< Number of implicitly fixed variables. */\n\t\tint\tnBV;\t\t\t\t/**< Number of bounded (but possibly free) variables. */\n\t\tint nUV;\t\t\t\t/**< Number of unbounded variables. */\n\n\t\tIndexlist free;\t\t\t/**< Index list of free variables. */\n\t\tIndexlist fixed;\t\t/**< Index list of fixed variables. */\n};\n\n#include <Bounds.ipp>\n\n#endif\t/* QPOASES_BOUNDS_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/Constants.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/Constants.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2008\n *\n *\tDefinition of all global constants.\n */\n\n\n#ifndef QPOASES_CONSTANTS_HPP\n#define QPOASES_CONSTANTS_HPP\n\n#ifndef QPOASES_CUSTOM_INTERFACE\n#include \"acado_qpoases_interface.hpp\"\n#else\n  #define XSTR(x) #x\n  #define STR(x) XSTR(x)\n  #include STR(QPOASES_CUSTOM_INTERFACE)\n#endif\n\n/** Maximum number of variables within a QP formulation.\n\tNote: this value has to be positive! */\nconst int NVMAX = QPOASES_NVMAX;\n\n/** Maximum number of constraints within a QP formulation.\n\tNote: this value has to be positive! */\nconst int NCMAX = QPOASES_NCMAX;\n\n/** Redefinition of NCMAX used for memory allocation, to avoid zero sized arrays\n    and compiler errors. */\nconst int NCMAX_ALLOC = (NCMAX == 0) ? 1 : NCMAX;\n\n/**< Maximum number of working set recalculations.\n\tNote: this value has to be positive! */\nconst int NWSRMAX = QPOASES_NWSRMAX;\n\n/** Desired KKT tolerance of QP solution; a warning RET_INACCURATE_SOLUTION is\n *  issued if this tolerance is not met.\n *\tNote: this value has to be positive! */\nconst real_t DESIREDACCURACY = (real_t) 1.0e-3;\n\n/** Critical KKT tolerance of QP solution; an error is issued if this\n *  tolerance is not met.\n *\tNote: this value has to be positive! */\nconst real_t CRITICALACCURACY = (real_t) 1.0e-2;\n\n\n\n/** Numerical value of machine precision (min eps, s.t. 1+eps > 1).\n\tNote: this value has to be positive! */\nconst real_t EPS = (real_t) QPOASES_EPS;\n\n/** Numerical value of zero (for situations in which it would be\n *\tunreasonable to compare with 0.0).\n *\tNote: this value has to be positive! */\nconst real_t ZERO = (real_t) 1.0e-50;\n\n/** Numerical value of infinity (e.g. for non-existing bounds).\n *\tNote: this value has to be positive! */\nconst real_t INFTY = (real_t) 1.0e12;\n\n\n/** Lower/upper (constraints') bound tolerance (an inequality constraint\n *\twhose lower and upper bound differ by less than BOUNDTOL is regarded\n *\tto be an equality constraint).\n *\tNote: this value has to be positive! */\nconst real_t BOUNDTOL = (real_t) 1.0e-10;\n\n/** Offset for relaxing (constraints') bounds at beginning of an initial homotopy.\n *\tNote: this value has to be positive! */\nconst real_t BOUNDRELAXATION = (real_t) 1.0e3;\n\n\n/** Factor that determines physical lengths of index lists.\n *\tNote: this value has to be greater than 1! */\nconst int INDEXLISTFACTOR = 5;\n\n\n#endif\t/* QPOASES_CONSTANTS_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/Constraints.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/Constraints.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the Constraints class designed to manage working sets of\n *\tconstraints within a QProblem.\n */\n\n\n#ifndef QPOASES_CONSTRAINTS_HPP\n#define QPOASES_CONSTRAINTS_HPP\n\n\n#include <SubjectTo.hpp>\n\n\n\n/** This class manages working sets of constraints by storing\n *\tindex sets and other status information.\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass Constraints : public SubjectTo\n{\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tConstraints( );\n\n\t\t/** Copy constructor (deep copy). */\n\t\tConstraints(\tconst Constraints& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~Constraints( );\n\n\t\t/** Assignment operator (deep copy). */\n\t\tConstraints& operator=(\tconst Constraints& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Pseudo-constructor takes the number of constraints.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue init(\tint n\t/**< Number of constraints. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Initially adds number of a new (i.e. not yet in the list) constraint to\n\t\t *  a given index set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_SETUP_CONSTRAINT_FAILED \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS */\n\t\treturnValue setupConstraint(\tint _number,\t\t\t\t/**< Number of new constraint. */\n\t\t\t\t\t\t\t\t\t\tSubjectToStatus _status\t\t/**< Status of new constraint. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Initially adds all enabled numbers of new (i.e. not yet in the list) constraints to\n\t\t *  to the index set of inactive constraints; the order depends on the SujectToType\n\t\t *  of each index. Only disabled constraints are added to index set of disabled constraints!\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_SETUP_CONSTRAINT_FAILED */\n\t\treturnValue setupAllInactive( );\n\n\n\t\t/** Moves index of a constraint from index list of active to that of inactive constraints.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_MOVING_CONSTRAINT_FAILED */\n\t\treturnValue moveActiveToInactive(\tint _number\t\t\t\t/**< Number of constraint to become inactive. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Moves index of a constraint from index list of inactive to that of active constraints.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_MOVING_CONSTRAINT_FAILED */\n\t\treturnValue moveInactiveToActive(\tint _number,\t\t\t/**< Number of constraint to become active. */\n\t\t\t\t\t\t\t\t\t\t\tSubjectToStatus _status\t/**< Status of constraint to become active. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns the number of constraints.\n\t\t *\t\\return Number of constraints. */\n\t\tinline int getNC( ) const;\n\n\t\t/** Returns the number of implicit equality constraints.\n\t\t *\t\\return Number of implicit equality constraints. */\n\t\tinline int getNEC( ) const;\n\n\t\t/** Returns the number of \"real\" inequality constraints.\n\t\t *\t\\return Number of \"real\" inequality constraints. */\n\t\tinline int getNIC( ) const;\n\n\t\t/** Returns the number of unbounded constraints (i.e. without any bounds).\n\t\t *\t\\return Number of unbounded constraints (i.e. without any bounds). */\n\t\tinline int getNUC( ) const;\n\n\n\t\t/** Sets number of implicit equality constraints.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setNEC(\tint n\t/**< Number of implicit equality constraints. */\n\t\t\t\t\t\t\t);\n\n\t\t/** Sets number of \"real\" inequality constraints.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setNIC(\tint n\t/**< Number of \"real\" inequality constraints. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Sets number of unbounded constraints (i.e. without any bounds).\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setNUC(\tint n\t/**< Number of unbounded constraints (i.e. without any bounds). */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns the number of active constraints.\n\t\t *\t\\return Number of constraints. */\n\t\tinline int getNAC( );\n\n\t\t/** Returns the number of inactive constraints.\n\t\t *\t\\return Number of constraints. */\n\t\tinline int getNIAC( );\n\n\n\t\t/** Returns a pointer to active constraints index list.\n\t\t *\t\\return Pointer to active constraints index list. */\n\t\tinline Indexlist* getActive( );\n\n\t\t/** Returns a pointer to inactive constraints index list.\n\t\t *\t\\return Pointer to inactive constraints index list. */\n\t\tinline Indexlist* getInactive( );\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\tint nC;\t\t\t\t\t/**< Number of constraints (nC = nEC + nIC + nUC). */\n\t\tint nEC;\t\t\t\t/**< Number of implicit equality constraints. */\n\t\tint\tnIC;\t\t\t\t/**< Number of \"real\" inequality constraints. */\n\t\tint nUC;\t\t\t\t/**< Number of unbounded constraints (i.e. without any bounds). */\n\n\t\tIndexlist active;\t\t/**< Index list of active constraints. */\n\t\tIndexlist inactive;\t\t/**< Index list of inactive constraints. */\n};\n\n\n#include <Constraints.ipp>\n\n#endif\t/* QPOASES_CONSTRAINTS_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/CyclingManager.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/CyclingManager.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the CyclingManager class designed to detect\n *\tand handle possible cycling during QP iterations.\n */\n\n\n#ifndef QPOASES_CYCLINGMANAGER_HPP\n#define QPOASES_CYCLINGMANAGER_HPP\n\n\n#include <Utils.hpp>\n\n\n\n/** This class is intended to detect and handle possible cycling during QP iterations.\n *\tAs cycling seems to occur quite rarely, this class is NOT FULLY IMPLEMENTED YET!\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass CyclingManager\n{\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tCyclingManager( );\n\n\t\t/** Copy constructor (deep copy). */\n\t\tCyclingManager(\tconst CyclingManager& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~CyclingManager( );\n\n\t\t/** Copy asingment operator (deep copy). */\n\t\tCyclingManager& operator=(\tconst CyclingManager& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Pseudo-constructor which takes the number of bounds/constraints.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue init(\tint _nV,\t/**< Number of bounds to be managed. */\n\t\t\t\t\t\t\tint _nC\t\t/**< Number of constraints to be managed. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Stores index of a bound/constraint that might cause cycling.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\treturnValue setCyclingStatus(\tint number,\t\t\t\t/**< Number of bound/constraint. */\n\t\t\t\t\t\t\t\t\t\tBooleanType isBound,\t/**< Flag that indicates if given number corresponds to a\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *   bound (BT_TRUE) or a constraint (BT_FALSE). */\n\t\t\t\t\t\t\t\t\t\tCyclingStatus _status\t/**< Cycling status of bound/constraint. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Returns if bound/constraint might cause cycling.\n\t\t *\t\\return BT_TRUE: bound/constraint might cause cycling \\n\n\t\t \t\t\tBT_FALSE: otherwise */\n\t\tCyclingStatus getCyclingStatus(\tint number,\t\t\t/**< Number of bound/constraint. */\n\t\t\t\t\t\t\t\t\t\tBooleanType isBound\t/**< Flag that indicates if given number corresponds to\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *   a bound (BT_TRUE) or a constraint (BT_FALSE). */\n\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Clears all previous cycling information.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue clearCyclingData( );\n\n\n\t\t/** Returns if cycling was detected.\n\t\t *\t\\return BT_TRUE iff cycling was detected. */\n\t\tinline BooleanType isCyclingDetected( ) const;\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\tint\tnV;\t\t\t\t\t\t\t\t\t/**< Number of managed bounds. */\n\t\tint\tnC;\t\t\t\t\t\t\t\t\t/**< Number of managed constraints. */\n\n\t\tCyclingStatus status[NVMAX+NCMAX];\t\t/**< Array to store cycling status of all bounds/constraints. */\n\n\t\tBooleanType cyclingDetected;\t\t\t/**< Flag if cycling was detected. */\n};\n\n\n#include <CyclingManager.ipp>\n\n#endif\t/* QPOASES_CYCLINGMANAGER_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/EXTRAS/SolutionAnalysis.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/EXTRAS/SolutionAnalysis.hpp\n *\t\\author Milan Vukov, Boris Houska, Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2012\n *\n *\tSolution analysis class, based on a class in the standard version of the qpOASES\n */\n\n\n//\n\n#ifndef QPOASES_SOLUTIONANALYSIS_HPP\n#define QPOASES_SOLUTIONANALYSIS_HPP\n\n#include <QProblem.hpp>\n\n/** Enables the computation of variance as is in the standard version of qpOASES */\n#define QPOASES_USE_OLD_VERSION 0\n\n#if QPOASES_USE_OLD_VERSION\n#define KKT_DIM (2 * NVMAX + NCMAX)\n#endif\n\nclass SolutionAnalysis\n{\npublic:\n\t\n\t/** Default constructor. */\n\tSolutionAnalysis( );\n\t\n\t/** Copy constructor (deep copy). */\n\tSolutionAnalysis( \tconst SolutionAnalysis& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t);\n\t\n\t/** Destructor. */\n\t~SolutionAnalysis( );\n\t\n\t/** Copy asingment operator (deep copy). */\n\tSolutionAnalysis& operator=(\tconst SolutionAnalysis& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t\t);\n\t\n\t/** A routine for computation of inverse of the Hessian matrix. */\n\treturnValue getHessianInverse(\n\t\t\t\t\t\t\t\t\tQProblem* qp,\t\t\t/** QP */\n\t\t\t\t\t\t\t\t\treal_t* hessianInverse\t/** Inverse of the Hessian matrix*/\n\t\t\t\t\t\t\t\t\t);\n\t\n\t/** A routine for computation of inverse of the Hessian matrix. */\n\treturnValue getHessianInverse(\tQProblemB* qp,\t\t\t/** QP */\n\t\t\t\t\t\t\t\t\treal_t* hessianInverse\t/** Inverse of the Hessian matrix*/\n\t\t\t\t\t\t\t\t\t);\n\n#if QPOASES_USE_OLD_VERSION\n\treturnValue getVarianceCovariance(\n\t\t\t\t\t\t\t\t\t\tQProblem* qp,\n\t\t\t\t\t\t\t\t\t\treal_t* g_b_bA_VAR,\n\t\t\t\t\t\t\t\t\t\treal_t* Primal_Dual_VAR\n\t\t\t\t\t\t\t\t\t\t);\n#endif\n\t\nprivate:\n\t\n\treal_t delta_g_cov[ NVMAX ];\t\t/** A covariance-vector of g */\n\treal_t delta_lb_cov[ NVMAX ];\t\t/** A covariance-vector of lb */\n\treal_t delta_ub_cov[ NVMAX ];\t\t/** A covariance-vector of ub */\n\treal_t delta_lbA_cov[ NCMAX_ALLOC ];\t\t/** A covariance-vector of lbA */\n\treal_t delta_ubA_cov[ NCMAX_ALLOC ];\t\t/** A covariance-vector of ubA */\n\t\n#if QPOASES_USE_OLD_VERSION\n\treal_t K[KKT_DIM * KKT_DIM];\t\t/** A matrix to store an intermediate result */\n#endif\n\t\n\tint FR_idx[ NVMAX ];\t\t\t\t/** Index array for free variables */\n\tint FX_idx[ NVMAX ];\t\t\t\t/** Index array for fixed variables */\n\tint AC_idx[ NCMAX_ALLOC ];\t\t\t\t/** Index array for active constraints */\n\t\n\treal_t delta_xFR[ NVMAX ];\t\t\t/** QP reaction, primal, w.r.t. free */\n\treal_t delta_xFX[ NVMAX ];\t\t\t/** QP reaction, primal, w.r.t. fixed */\n\treal_t delta_yAC[ NVMAX ];\t\t\t/** QP reaction, dual, w.r.t. active */\n\treal_t delta_yFX[ NVMAX ];\t\t\t/** QP reaction, dual, w.r.t. fixed*/\n};\n\n#endif // QPOASES_SOLUTIONANALYSIS_HPP\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/Indexlist.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/Indexlist.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the Indexlist class designed to manage index lists of\n *\tconstraints and bounds within a SubjectTo object.\n */\n\n\n#ifndef QPOASES_INDEXLIST_HPP\n#define QPOASES_INDEXLIST_HPP\n\n\n#include <Utils.hpp>\n\n\n/** This class manages index lists.\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass Indexlist\n{\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tIndexlist( );\n\n\t\t/** Copy constructor (deep copy). */\n\t\tIndexlist(\tconst Indexlist& rhs\t/**< Rhs object. */\n\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~Indexlist( );\n\n\t\t/** Assingment operator (deep copy). */\n\t\tIndexlist& operator=(\tconst Indexlist& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Pseudo-constructor.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue init( );\n\n\n\t\t/** Creates an array of all numbers within the index set in correct order.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_INDEXLIST_CORRUPTED */\n\t\treturnValue\tgetNumberArray(\tint* const numberarray\t/**< Output: Array of numbers (NULL on error). */\n\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Determines the index within the index list at with a given number is stored.\n\t\t *\t\\return >= 0: Index of given number. \\n\n\t\t \t\t\t-1: Number not found. */\n\t\tint\tgetIndex(\tint givennumber\t/**< Number whose index shall be determined. */\n\t\t\t\t\t\t) const;\n\n\t\t/** Determines the physical index within the index list at with a given number is stored.\n\t\t *\t\\return >= 0: Index of given number. \\n\n\t\t \t\t\t-1: Number not found. */\n\t\tint\tgetPhysicalIndex(\tint givennumber\t/**< Number whose physical index shall be determined. */\n\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns the number stored at a given physical index.\n\t\t *\t\\return >= 0: Number stored at given physical index. \\n\n\t\t \t\t\t-RET_INDEXLIST_OUTOFBOUNDS */\n\t\tint\tgetNumber(\tint physicalindex\t/**< Physical index of the number to be returned. */\n\t\t\t\t\t\t) const;\n\n\n\t\t/** Returns the current length of the index list.\n\t\t *\t\\return Current length of the index list. */\n\t\tinline int getLength( );\n\n\t\t/** Returns last number within the index list.\n\t\t *\t\\return Last number within the index list. */\n\t\tinline int getLastNumber( ) const;\n\n\n\t\t/** Adds number to index list.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_INDEXLIST_MUST_BE_REORDERD \\n\n\t\t \t\t\tRET_INDEXLIST_EXCEEDS_MAX_LENGTH */\n\t\treturnValue addNumber(\tint addnumber\t/**< Number to be added. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Removes number from index list.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue removeNumber(\tint removenumber\t/**< Number to be removed. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Swaps two numbers within index list.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue swapNumbers(\tint number1,/**< First number for swapping. */\n\t\t\t\t\t\t\t\t\tint number2\t/**< Second number for swapping. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Determines if a given number is contained in the index set.\n\t\t *\t\\return BT_TRUE iff number is contain in the index set */\n\t\tinline BooleanType isMember(\tint _number\t/**< Number to be tested for membership. */\n\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\tint number[INDEXLISTFACTOR*(NVMAX+NCMAX)];\t\t/**< Array to store numbers of constraints or bounds. */\n\t\tint next[INDEXLISTFACTOR*(NVMAX+NCMAX)];\t\t/**< Array to store physical index of successor. */\n\t\tint previous[INDEXLISTFACTOR*(NVMAX+NCMAX)];\t/**< Array to store physical index of predecossor. */\n\t\tint\tlength;\t\t\t\t\t\t\t\t\t\t/**< Length of index list. */\n\t\tint\tfirst;\t\t\t\t\t\t\t\t\t\t/**< Physical index of first element. */\n\t\tint\tlast;\t\t\t\t\t\t\t\t\t\t/**< Physical index of last element. */\n\t\tint\tlastusedindex;\t\t\t\t\t\t\t\t/**< Physical index of last entry in index list. */\n\t\tint\tphysicallength;\t\t\t\t\t\t\t\t/**< Physical length of index list. */\n};\n\n\n#include <Indexlist.ipp>\n\n#endif\t/* QPOASES_INDEXLIST_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/MessageHandling.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/MessageHandling.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the MessageHandling class including global return values.\n */\n\n\n#ifndef QPOASES_MESSAGEHANDLING_HPP\n#define QPOASES_MESSAGEHANDLING_HPP\n\n// #define PC_DEBUG\n\n#ifdef PC_DEBUG\n  #include <stdio.h>\n\n  /** Defines an alias for  FILE  from stdio.h. */\n  #define myFILE FILE\n  /** Defines an alias for  stderr  from stdio.h. */\n  #define myStderr stderr\n  /** Defines an alias for  stdout  from stdio.h. */\n  #define myStdout stdout\n#else\n  /** Defines an alias for  FILE  from stdio.h. */\n  #define myFILE int\n  /** Defines an alias for  stderr  from stdio.h. */\n  #define myStderr 0\n  /** Defines an alias for  stdout  from stdio.h. */\n  #define myStdout 0\n#endif\n\n\n#include <Types.hpp>\n#include <Constants.hpp>\n\n\n/** Defines symbols for global return values. \\n\n *  Important: All return values are assumed to be nonnegative! */\nenum returnValue\n{\nTERMINAL_LIST_ELEMENT = -1,\t\t\t\t\t\t/**< Terminal list element, internal usage only! */\n/* miscellaneous */\nSUCCESSFUL_RETURN = 0,\t\t\t\t\t\t\t/**< Successful return. */\nRET_DIV_BY_ZERO,\t\t   \t\t\t\t\t\t/**< Division by zero. */\nRET_INDEX_OUT_OF_BOUNDS,\t\t\t\t\t\t/**< Index out of bounds. */\nRET_INVALID_ARGUMENTS,\t\t\t\t\t\t\t/**< At least one of the arguments is invalid. */\nRET_ERROR_UNDEFINED,\t\t\t\t\t\t\t/**< Error number undefined. */\nRET_WARNING_UNDEFINED,\t\t\t\t\t\t\t/**< Warning number undefined. */\nRET_INFO_UNDEFINED,\t\t\t\t\t\t\t\t/**< Info number undefined. */\nRET_EWI_UNDEFINED,\t\t\t\t\t\t\t\t/**< Error/warning/info number undefined. */\nRET_AVAILABLE_WITH_LINUX_ONLY,\t\t\t\t\t/**< This function is available under Linux only. */\nRET_UNKNOWN_BUG,\t\t\t\t\t\t\t\t/**< The error occured is not yet known. */\nRET_PRINTLEVEL_CHANGED,\t\t\t\t\t\t\t/**< 10 Print level changed. */\nRET_NOT_YET_IMPLEMENTED,\t\t\t\t\t\t/**< Requested function is not yet implemented in this version of qpOASES. */\n/* Indexlist */\nRET_INDEXLIST_MUST_BE_REORDERD,\t\t\t\t\t/**< Index list has to be reordered. */\nRET_INDEXLIST_EXCEEDS_MAX_LENGTH,\t\t\t\t/**< Index list exceeds its maximal physical length. */\nRET_INDEXLIST_CORRUPTED,\t\t\t\t\t\t/**< Index list corrupted. */\nRET_INDEXLIST_OUTOFBOUNDS,\t\t\t\t\t\t/**< Physical index is out of bounds. */\nRET_INDEXLIST_ADD_FAILED,\t\t\t\t\t\t/**< Adding indices from another index set failed. */\nRET_INDEXLIST_INTERSECT_FAILED,\t\t\t\t\t/**< Intersection with another index set failed. */\n/* SubjectTo / Bounds / Constraints */\nRET_INDEX_ALREADY_OF_DESIRED_STATUS,\t\t\t/**< Index is already of desired status. */\nRET_ADDINDEX_FAILED,\t\t\t\t\t\t\t/**< Cannot swap between different indexsets. */\nRET_SWAPINDEX_FAILED,\t\t\t\t\t\t\t/**< 20 Adding index to index set failed. */\nRET_NOTHING_TO_DO,\t\t\t\t\t\t\t\t/**< Nothing to do. */\nRET_SETUP_BOUND_FAILED,\t\t\t\t\t\t\t/**< Setting up bound index failed. */\nRET_SETUP_CONSTRAINT_FAILED,\t\t\t\t\t/**< Setting up constraint index failed. */\nRET_MOVING_BOUND_FAILED,\t\t\t\t\t\t/**< Moving bound between index sets failed. */\nRET_MOVING_CONSTRAINT_FAILED,\t\t\t\t\t/**< Moving constraint between index sets failed. */\n/* QProblem */\nRET_QP_ALREADY_INITIALISED,\t\t\t\t\t\t/**< QProblem has already been initialised. */\nRET_NO_INIT_WITH_STANDARD_SOLVER,\t\t\t\t/**< Initialisation via extern QP solver is not yet implemented. */\nRET_RESET_FAILED,\t\t\t\t\t\t\t\t/**< Reset failed. */\nRET_INIT_FAILED,\t\t\t\t\t\t\t\t/**< Initialisation failed. */\nRET_INIT_FAILED_TQ,\t\t\t\t\t\t\t\t/**< 30 Initialisation failed due to TQ factorisation. */\nRET_INIT_FAILED_CHOLESKY,\t\t\t\t\t\t/**< Initialisation failed due to Cholesky decomposition. */\nRET_INIT_FAILED_HOTSTART,\t\t\t\t\t\t/**< Initialisation failed! QP could not be solved! */\nRET_INIT_FAILED_INFEASIBILITY,\t\t\t\t\t/**< Initial QP could not be solved due to infeasibility! */\nRET_INIT_FAILED_UNBOUNDEDNESS,\t\t\t\t\t/**< Initial QP could not be solved due to unboundedness! */\nRET_INIT_SUCCESSFUL,\t\t\t\t\t\t\t/**< Initialisation done. */\nRET_OBTAINING_WORKINGSET_FAILED,\t\t\t\t/**< Failed to obtain working set for auxiliary QP. */\nRET_SETUP_WORKINGSET_FAILED,\t\t\t\t\t/**< Failed to setup working set for auxiliary QP. */\nRET_SETUP_AUXILIARYQP_FAILED,\t\t\t\t\t/**< Failed to setup auxiliary QP for initialised homotopy. */\nRET_NO_EXTERN_SOLVER,\t\t\t\t\t\t\t/**< No extern QP solver available. */\nRET_QP_UNBOUNDED,\t\t\t\t\t\t\t\t/**< 40 QP is unbounded. */\nRET_QP_INFEASIBLE,\t\t\t\t\t\t\t\t/**< QP is infeasible. */\nRET_QP_NOT_SOLVED,\t\t\t\t\t\t\t\t/**< Problems occured while solving QP with standard solver. */\nRET_QP_SOLVED,\t\t\t\t\t\t\t\t\t/**< QP successfully solved. */\nRET_UNABLE_TO_SOLVE_QP,\t\t\t\t\t\t\t/**< Problems occured while solving QP. */\nRET_INITIALISATION_STARTED,\t\t\t\t\t\t/**< Starting problem initialisation. */\nRET_HOTSTART_FAILED,\t\t\t\t\t\t\t/**< Unable to perform homotopy due to internal error. */\nRET_HOTSTART_FAILED_TO_INIT,\t\t\t\t\t/**< Unable to initialise problem. */\nRET_HOTSTART_FAILED_AS_QP_NOT_INITIALISED,\t\t/**< Unable to perform homotopy as previous QP is not solved. */\nRET_ITERATION_STARTED,\t\t\t\t\t\t\t/**< Iteration... */\nRET_SHIFT_DETERMINATION_FAILED,\t\t\t\t\t/**< 50 Determination of shift of the QP data failed. */\nRET_STEPDIRECTION_DETERMINATION_FAILED,\t\t\t/**< Determination of step direction failed. */\nRET_STEPLENGTH_DETERMINATION_FAILED,\t\t\t/**< Determination of step direction failed. */\nRET_OPTIMAL_SOLUTION_FOUND,\t\t\t\t\t\t/**< Optimal solution of neighbouring QP found. */\nRET_HOMOTOPY_STEP_FAILED,\t\t\t\t\t\t/**< Unable to perform homotopy step. */\nRET_HOTSTART_STOPPED_INFEASIBILITY,\t\t\t\t/**< Premature homotopy termination because QP is infeasible. */\nRET_HOTSTART_STOPPED_UNBOUNDEDNESS,\t\t\t\t/**< Premature homotopy termination because QP is unbounded. */\nRET_WORKINGSET_UPDATE_FAILED,\t\t\t\t\t/**< Unable to update working sets according to initial guesses. */\nRET_MAX_NWSR_REACHED,\t\t\t\t\t\t\t/**< Maximum number of working set recalculations performed. */\nRET_CONSTRAINTS_NOT_SPECIFIED,\t\t\t\t\t/**< Problem does comprise constraints! You also have to specify new constraints' bounds. */\nRET_INVALID_FACTORISATION_FLAG,\t\t\t\t\t/**< 60 Invalid factorisation flag. */\nRET_UNABLE_TO_SAVE_QPDATA,\t\t\t\t\t\t/**< Unable to save QP data. */\nRET_STEPDIRECTION_FAILED_TQ,\t\t\t\t\t/**< Abnormal termination due to TQ factorisation. */\nRET_STEPDIRECTION_FAILED_CHOLESKY,\t\t\t\t/**< Abnormal termination due to Cholesky factorisation. */\nRET_CYCLING_DETECTED,\t\t\t\t\t\t\t/**< Cycling detected. */\nRET_CYCLING_NOT_RESOLVED,\t\t\t\t\t\t/**< Cycling cannot be resolved, QP probably infeasible. */\nRET_CYCLING_RESOLVED,\t\t\t\t\t\t\t/**< Cycling probably resolved. */\nRET_STEPSIZE,\t\t\t\t\t\t\t\t\t/**< For displaying performed stepsize. */\nRET_STEPSIZE_NONPOSITIVE,\t\t\t\t\t\t/**< For displaying non-positive stepsize. */\nRET_SETUPSUBJECTTOTYPE_FAILED,\t\t\t\t\t/**< Setup of SubjectToTypes failed. */\nRET_ADDCONSTRAINT_FAILED,\t\t\t\t\t\t/**< 70 Addition of constraint to working set failed. */\nRET_ADDCONSTRAINT_FAILED_INFEASIBILITY,\t\t\t/**< Addition of constraint to working set failed (due to QP infeasibility). */\nRET_ADDBOUND_FAILED,\t\t\t\t\t\t\t/**< Addition of bound to working set failed. */\nRET_ADDBOUND_FAILED_INFEASIBILITY,\t\t\t\t/**< Addition of bound to working set failed (due to QP infeasibility). */\nRET_REMOVECONSTRAINT_FAILED,\t\t\t\t\t/**< Removal of constraint from working set failed. */\nRET_REMOVEBOUND_FAILED,\t\t\t\t\t\t\t/**< Removal of bound from working set failed. */\nRET_REMOVE_FROM_ACTIVESET,\t\t\t\t\t\t/**< Removing from active set... */\nRET_ADD_TO_ACTIVESET,\t\t\t\t\t\t\t/**< Adding to active set... */\nRET_REMOVE_FROM_ACTIVESET_FAILED,\t\t\t\t/**< Removing from active set failed. */\nRET_ADD_TO_ACTIVESET_FAILED,\t\t\t\t\t/**< Adding to active set failed. */\nRET_CONSTRAINT_ALREADY_ACTIVE,\t\t\t\t\t/**< 80 Constraint is already active. */\nRET_ALL_CONSTRAINTS_ACTIVE,\t\t\t\t\t\t/**< All constraints are active, no further constraint can be added. */\nRET_LINEARLY_DEPENDENT,\t\t\t\t\t\t\t/**< New bound/constraint is linearly dependent. */\nRET_LINEARLY_INDEPENDENT,\t\t\t\t\t\t/**< New bound/constraint is linearly independent. */\nRET_LI_RESOLVED,\t\t\t\t\t\t\t\t/**< Linear independence of active contraint matrix successfully resolved. */\nRET_ENSURELI_FAILED,\t\t\t\t\t\t\t/**< Failed to ensure linear indepence of active contraint matrix. */\nRET_ENSURELI_FAILED_TQ,\t\t\t\t\t\t\t/**< Abnormal termination due to TQ factorisation. */\nRET_ENSURELI_FAILED_NOINDEX,\t\t\t\t\t/**< No index found, QP probably infeasible. */\nRET_ENSURELI_FAILED_CYCLING,\t\t\t\t\t/**< Cycling detected, QP probably infeasible. */\nRET_BOUND_ALREADY_ACTIVE,\t\t\t\t\t\t/**< Bound is already active. */\nRET_ALL_BOUNDS_ACTIVE,\t\t\t\t\t\t\t/**< 90 All bounds are active, no further bound can be added. */\nRET_CONSTRAINT_NOT_ACTIVE,\t\t\t\t\t\t/**< Constraint is not active. */\nRET_BOUND_NOT_ACTIVE,\t\t\t\t\t\t\t/**< Bound is not active. */\nRET_HESSIAN_NOT_SPD,\t\t\t\t\t\t\t/**< Projected Hessian matrix not positive definite. */\nRET_MATRIX_SHIFT_FAILED,\t\t\t\t\t\t/**< Unable to update matrices or to transform vectors. */\nRET_MATRIX_FACTORISATION_FAILED,\t\t\t\t/**< Unable to calculate new matrix factorisations. */\nRET_PRINT_ITERATION_FAILED,\t\t\t\t\t\t/**< Unable to print information on current iteration. */\nRET_NO_GLOBAL_MESSAGE_OUTPUTFILE,\t\t\t\t/**< No global message output file initialised. */\n/* Utils */\nRET_UNABLE_TO_OPEN_FILE,\t\t\t\t\t\t/**< Unable to open file. */\nRET_UNABLE_TO_WRITE_FILE,\t\t\t\t\t\t/**< Unable to write into file. */\nRET_UNABLE_TO_READ_FILE,\t\t\t\t\t\t/**< 100 Unable to read from file. */\nRET_FILEDATA_INCONSISTENT,\t\t\t\t\t\t/**< File contains inconsistent data. */\n/* SolutionAnalysis */\nRET_NO_SOLUTION, \t\t\t\t\t\t\t\t/**< QP solution does not satisfy KKT optimality conditions. */\nRET_INACCURATE_SOLUTION\t\t\t\t\t\t\t/**< KKT optimality conditions not satisfied to sufficient accuracy. */\n};\n\n\n\n/** This class handles all kinds of messages (errors, warnings, infos) initiated\n *  by qpOASES modules and stores the correspoding global preferences.\n *\n *\t\\author Hans Joachim Ferreau (special thanks to Leonard Wirsching)\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass MessageHandling\n{\n\t/*\n\t *\tINTERNAL DATA STRUCTURES\n\t */\n\tpublic:\n\t\t/** Data structure for entries in global message list. */\n\t\ttypedef struct {\n\t\t\treturnValue key;\t\t\t\t\t\t\t/**< Global return value. */\n\t\t\tconst char* data;\t\t\t\t\t\t\t/**< Corresponding message. */\n\t\t\tVisibilityStatus globalVisibilityStatus; \t/**< Determines if message can be printed.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t* \t If this value is set to VS_HIDDEN, no message is printed! */\n\t\t} ReturnValueList;\n\n\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tMessageHandling( );\n\n\t\t/** Constructor which takes the desired output file. */\n\t\tMessageHandling(  myFILE* _outputFile\t\t\t\t\t/**< Output file. */\n\t\t\t\t\t\t  );\n\n\t\t/** Constructor which takes the desired visibility states. */\n\t\tMessageHandling(\tVisibilityStatus _errorVisibility,\t/**< Visibility status for error messages. */\n\t\t\t\t\t\t\tVisibilityStatus _warningVisibility,/**< Visibility status for warning messages. */\n\t\t\t\t\t\t\tVisibilityStatus _infoVisibility\t/**< Visibility status for info messages. */\n\t\t\t\t\t\t\t);\n\n\t\t/** Constructor which takes the desired output file and desired visibility states. */\n\t\tMessageHandling(\tmyFILE* _outputFile,\t\t\t\t/**< Output file. */\n\t\t\t\t\t\t\tVisibilityStatus _errorVisibility,\t/**< Visibility status for error messages. */\n\t\t\t\t\t\t\tVisibilityStatus _warningVisibility,/**< Visibility status for warning messages. */\n\t\t\t\t\t\t\tVisibilityStatus _infoVisibility\t/**< Visibility status for info messages. */\n\t\t\t\t\t\t\t);\n\n\t\t/** Copy constructor (deep copy). */\n\t\tMessageHandling(\tconst MessageHandling& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~MessageHandling( );\n\n\t\t/** Assignment operator (deep copy). */\n\t\tMessageHandling& operator=(\tconst MessageHandling& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Prints an error message(a simplified macro THROWERROR is also provided). \\n\n\t\t *  Errors are definied as abnormal events which cause an immediate termination of the current (sub) function.\n\t\t *  Errors of a sub function should be commented by the calling function by means of a warning message\n\t\t *  (if this error does not cause an error of the calling function, either)!\n\t\t *  \\return Error number returned by sub function call\n\t\t */\n\t\treturnValue throwError(\n\t\t\treturnValue Enumber,\t\t\t\t\t/**< Error number returned by sub function call. */\n\t\t\tconst char* additionaltext,\t\t\t\t/**< Additional error text (0, if none). */\n\t\t\tconst char* functionname,\t\t\t\t/**< Name of function which caused the error. */\n\t\t\tconst char* filename,\t\t\t\t\t/**< Name of file which caused the error. */\n\t\t\tconst unsigned long linenumber,\t\t\t/**< Number of line which caused the error.incompatible binary file */\n\t\t\tVisibilityStatus localVisibilityStatus\t/**< Determines (locally) if error message can be printed to myStderr.\n\t\t\t   \t\t\t\t\t\t\t\t\t *   If GLOBAL visibility status of the message is set to VS_HIDDEN,\n\t   \t\t\t \t\t\t\t\t\t\t\t *   no message is printed, anyway! */\n\t\t);\n\n\t\t/** Prints a warning message (a simplified macro THROWWARNING is also provided).\n\t\t *  Warnings are definied as abnormal events which does NOT cause an immediate termination of the current (sub) function.\n\t\t *  \\return Warning number returned by sub function call\n\t\t */\n\t\treturnValue throwWarning(\n\t\t\treturnValue Wnumber,\t \t\t\t\t/**< Warning number returned by sub function call. */\n\t\t\tconst char* additionaltext,\t\t\t\t/**< Additional warning text (0, if none). */\n\t\t\tconst char* functionname,\t\t\t\t/**< Name of function which caused the warning. */\n\t\t\tconst char* filename,   \t\t\t\t/**< Name of file which caused the warning. */\n\t\t\tconst unsigned long linenumber,\t \t\t/**< Number of line which caused the warning. */\n\t\t\tVisibilityStatus localVisibilityStatus\t/**< Determines (locally) if warning message can be printed to myStderr.\n\t\t   \t\t  \t\t\t\t\t\t\t\t\t *   If GLOBAL visibility status of the message is set to VS_HIDDEN,\n\t\t\t\t\t \t\t\t\t\t\t\t\t *   no message is printed, anyway! */\n\t\t\t);\n\n\t   /** Prints a info message (a simplified macro THROWINFO is also provided).\n\t\t *  \\return Info number returned by sub function call\n\t\t */\n\t\treturnValue throwInfo(\n\t\t\treturnValue Inumber,\t \t\t\t\t/**< Info number returned by sub function call. */\n\t\t\tconst char* additionaltext,\t \t\t\t/**< Additional warning text (0, if none). */\n\t\t\tconst char* functionname,\t\t\t\t/**< Name of function which submitted the info. */\n\t\t\tconst char* filename,   \t\t\t\t/**< Name of file which submitted the info. */\n\t\t\tconst unsigned long linenumber,\t\t\t/**< Number of line which submitted the info. */\n\t\t\tVisibilityStatus localVisibilityStatus\t/**< Determines (locally) if info message can be printed to myStderr.\n\t\t\t\t  \t\t\t\t\t\t\t\t\t *   If GLOBAL visibility status of the message is set to VS_HIDDEN,\n\t\t\t\t   \t\t\t\t\t\t\t\t\t *   no message is printed, anyway! */\n\t\t\t);\n\n\n\t\t/** Resets all preferences to default values.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue reset( );\n\n\n\t\t/** Prints a complete list of all messages to output file.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue listAllMessages( );\n\n\n\t\t/** Returns visibility status for error messages.\n\t\t *\t\\return Visibility status for error messages. */\n\t\tinline VisibilityStatus getErrorVisibilityStatus( ) const;\n\n\t\t/** Returns visibility status for warning messages.\n\t\t *\t\\return Visibility status for warning messages. */\n\t\tinline VisibilityStatus getWarningVisibilityStatus( ) const;\n\n\t\t/** Returns visibility status for info messages.\n\t\t *\t\\return Visibility status for info messages. */\n\t\tinline VisibilityStatus getInfoVisibilityStatus( ) const;\n\n\t\t/** Returns pointer to output file.\n\t\t *\t\\return Pointer to output file. */\n\t\tinline myFILE* getOutputFile( ) const;\n\n\t\t/** Returns error count value.\n\t\t *\t\\return Error count value. */\n\t\tinline int getErrorCount( ) const;\n\n\n\t\t/** Changes visibility status for error messages. */\n\t\tinline void setErrorVisibilityStatus(\tVisibilityStatus _errorVisibility\t/**< New visibility status for error messages. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes visibility status for warning messages. */\n\t\tinline void setWarningVisibilityStatus(\tVisibilityStatus _warningVisibility\t/**< New visibility status for warning messages. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes visibility status for info messages. */\n\t\tinline void setInfoVisibilityStatus(\tVisibilityStatus _infoVisibility\t/**< New visibility status for info messages. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes output file for messages. */\n\t\tinline void setOutputFile(\tmyFILE* _outputFile\t/**< New output file for messages. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes error count.\n\t\t * \\return SUCCESSFUL_RETURN \\n\n\t\t *\t\t   RET_INVALID_ARGUMENT */\n\t\tinline returnValue setErrorCount(\tint _errorCount\t/**< New error count value. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Return the error code string. */\n\t\tstatic const char* getErrorString(int error);\n\n\t/*\n\t *\tPROTECTED MEMBER FUNCTIONS\n\t */\n\tprotected:\n\t\t/** Prints a info message to myStderr (auxiliary function).\n\t\t *  \\return Error/warning/info number returned by sub function call\n\t\t */\n\t\treturnValue throwMessage(\n\t\t\treturnValue RETnumber,\t \t\t\t\t/**< Error/warning/info number returned by sub function call. */\n\t\t\tconst char* additionaltext,\t\t\t\t/**< Additional warning text (0, if none). */\n\t\t\tconst char* functionname,\t\t\t\t/**< Name of function which caused the error/warning/info. */\n\t\t\tconst char* filename,   \t\t\t\t/**< Name of file which caused the error/warning/info. */\n\t\t\tconst unsigned long linenumber,\t\t\t/**< Number of line which caused the error/warning/info. */\n\t\t\tVisibilityStatus localVisibilityStatus,\t/**< Determines (locally) if info message can be printed to myStderr.\n\t\t\t\t\t  \t\t\t\t\t\t\t\t *   If GLOBAL visibility status of the message is set to VS_HIDDEN,\n\t\t\t\t   \t\t\t\t\t\t\t\t\t *   no message is printed, anyway! */\n\t\t\tconst char* RETstring\t\t\t\t\t/**< Leading string of error/warning/info message. */\n\t\t\t);\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\tVisibilityStatus errorVisibility;\t\t/**< Error messages visible? */\n\t\tVisibilityStatus warningVisibility;\t\t/**< Warning messages visible? */\n\t\tVisibilityStatus infoVisibility;\t\t/**< Info messages visible? */\n\n\t\tmyFILE* outputFile;\t\t\t\t\t\t/**< Output file for messages. */\n\n\t\tint errorCount; \t\t\t\t\t\t/**< Counts number of errors (for nicer output only). */\n};\n\n\n#ifndef __FUNCTION__\n  /** Ensures that __FUNCTION__ macro is defined. */\n  #define __FUNCTION__ 0\n#endif\n\n#ifndef __FILE__\n  /** Ensures that __FILE__ macro is defined. */\n  #define __FILE__ 0\n#endif\n\n#ifndef __LINE__\n  /** Ensures that __LINE__ macro is defined. */\n  #define __LINE__ 0\n#endif\n\n\n/** Short version of throwError with default values, only returnValue is needed */\n#define THROWERROR(retval) ( getGlobalMessageHandler( )->throwError((retval),0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE) )\n\n/** Short version of throwWarning with default values, only returnValue is needed */\n#define THROWWARNING(retval) ( getGlobalMessageHandler( )->throwWarning((retval),0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE) )\n\n/** Short version of throwInfo with default values, only returnValue is needed */\n#define THROWINFO(retval) ( getGlobalMessageHandler( )->throwInfo((retval),0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE) )\n\n\n/** Returns a pointer to global message handler.\n *  \\return Pointer to global message handler.\n */\nMessageHandling* getGlobalMessageHandler( );\n\n\n#include <MessageHandling.ipp>\n\n#endif /* QPOASES_MESSAGEHANDLING_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/QProblem.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/QProblem.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the QProblem class which is able to use the newly\n *\tdeveloped online active set strategy for parametric quadratic programming.\n */\n\n\n\n#ifndef QPOASES_QPROBLEM_HPP\n#define QPOASES_QPROBLEM_HPP\n\n\n#include <QProblemB.hpp>\n#include <Constraints.hpp>\n#include <CyclingManager.hpp>\n\n\n/** A class for setting up and solving quadratic programs. The main feature is\n *\tthe possibily to use the newly developed online active set strategy for\n * \tparametric quadratic programming.\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass QProblem : public QProblemB\n{\n\t/* allow SolutionAnalysis class to access private members */\n\tfriend class SolutionAnalysis;\n\t\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tQProblem( );\n\n\t\t/** Constructor which takes the QP dimensions only. */\n\t\tQProblem(\tint _nV,\t  \t\t\t\t/**< Number of variables. */\n\t\t\t\t\tint _nC  \t\t\t\t\t/**< Number of constraints. */\n\t\t\t\t\t);\n\n\t\t/** Copy constructor (deep copy). */\n\t\tQProblem(\tconst QProblem& rhs\t/**< Rhs object. */\n\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~QProblem( );\n\n\t\t/** Assignment operator (deep copy). */\n\t\tQProblem& operator=(\tconst QProblem& rhs\t\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Clears all data structures of QProblemB except for QP data.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_RESET_FAILED */\n\t\treturnValue reset( );\n\n\n\t\t/** Initialises a QProblem with given QP data and solves it\n\t\t *\tusing an initial homotopy with empty working set (at most nWSR iterations).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INIT_FAILED \\n\n\t\t\t\t\tRET_INIT_FAILED_CHOLESKY \\n\n\t\t\t\t\tRET_INIT_FAILED_TQ \\n\n\t\t\t\t\tRET_INIT_FAILED_HOTSTART \\n\n\t\t\t\t\tRET_INIT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_INIT_FAILED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS \\n\n\t\t\t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t \t\t\tRET_NO_SOLUTION */\n\t\treturnValue init(\tconst real_t* const _H, \t\t/**< Hessian matrix. */\n\t\t\t\t\t\t\tconst real_t* const _g, \t\t/**< Gradient vector. */\n\t\t\t\t\t\t\tconst real_t* const _A,  \t\t/**< Constraint matrix. */\n\t\t\t\t\t\t\tconst real_t* const _lb,\t\t/**< Lower bound vector (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _ub,\t\t/**< Upper bound vector (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _lbA,\t\t/**< Lower constraints' bound vector. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _ubA,\t\t/**< Upper constraints' bound vector. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tint& nWSR,\t\t\t\t\t\t/**< Input: Maximum number of working set recalculations when using initial homotopy.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOutput: Number of performed working set recalculations. */\n\t\t\t\t\t\t\tconst real_t* const yOpt = 0,\t/**< Initial guess for dual solution vector. */\n\t\t\t\t\t\t\treal_t* const cputime = 0\t\t/**< Output: CPU time required to initialise QP. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Initialises a QProblem with given QP data and solves it\n\t\t *\tusing an initial homotopy with empty working set (at most nWSR iterations).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INIT_FAILED \\n\n\t\t\t\t\tRET_INIT_FAILED_CHOLESKY \\n\n\t\t\t\t\tRET_INIT_FAILED_TQ \\n\n\t\t\t\t\tRET_INIT_FAILED_HOTSTART \\n\n\t\t\t\t\tRET_INIT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_INIT_FAILED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS \\n\n\t\t\t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t \t\t\tRET_NO_SOLUTION */\n\t\treturnValue init(\tconst real_t* const _H, \t\t/**< Hessian matrix. */\n\t\t\t\t\t\t\tconst real_t* const _R, \t\t/**< Cholesky factorization of the Hessian matrix. */\n\t\t\t\t\t\t\tconst real_t* const _g, \t\t/**< Gradient vector. */\n\t\t\t\t\t\t\tconst real_t* const _A,  \t\t/**< Constraint matrix. */\n\t\t\t\t\t\t\tconst real_t* const _lb,\t\t/**< Lower bound vector (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _ub,\t\t/**< Upper bound vector (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _lbA,\t\t/**< Lower constraints' bound vector. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _ubA,\t\t/**< Upper constraints' bound vector. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tint& nWSR,\t\t\t\t\t\t/**< Input: Maximum number of working set recalculations when using initial homotopy.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOutput: Number of performed working set recalculations. */\n\t\t\t\t\t\t\tconst real_t* const yOpt = 0,\t/**< Initial guess for dual solution vector. */\n\t\t\t\t\t\t\treal_t* const cputime = 0\t\t/**< Output: CPU time required to initialise QP. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Solves QProblem using online active set strategy.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_MAX_NWSR_REACHED \\n\n\t\t \t\t\tRET_HOTSTART_FAILED_AS_QP_NOT_INITIALISED \\n\n\t\t\t\t\tRET_HOTSTART_FAILED \\n\n\t\t\t\t\tRET_SHIFT_DETERMINATION_FAILED \\n\n\t\t\t\t\tRET_STEPDIRECTION_DETERMINATION_FAILED \\n\n\t\t\t\t\tRET_STEPLENGTH_DETERMINATION_FAILED \\n\n\t\t\t\t\tRET_HOMOTOPY_STEP_FAILED \\n\n\t\t\t\t\tRET_HOTSTART_STOPPED_INFEASIBILITY \\n\n\t\t\t\t\tRET_HOTSTART_STOPPED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t \t\t\tRET_NO_SOLUTION */\n\t\treturnValue hotstart(\tconst real_t* const g_new,\t\t/**< Gradient of neighbouring QP to be solved. */\n\t\t\t\t\t\t\t\tconst real_t* const lb_new,\t\t/**< Lower bounds of neighbouring QP to be solved. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t \t If no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\tconst real_t* const ub_new,\t\t/**< Upper bounds of neighbouring QP to be solved. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t \t If no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\tconst real_t* const lbA_new,\t/**< Lower constraints' bounds of neighbouring QP to be solved. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t \t If no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\tconst real_t* const ubA_new,\t/**< Upper constraints' bounds of neighbouring QP to be solved. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t \t If no upper constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\tint& nWSR,\t\t\t\t\t\t/**< Input: Maximum number of working set recalculations; \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t Output: Number of performed working set recalculations. */\n\t\t\t\t\t\t\t\treal_t* const cputime\t\t\t/**< Output: CPU time required to solve QP (or to perform nWSR iterations). */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns constraint matrix of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getA(\treal_t* const _A\t/**< Array of appropriate dimension for copying constraint matrix.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns a single row of constraint matrix of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue getA(\tint number,\t\t\t/**< Number of entry to be returned. */\n\t\t\t\t\t\t\t\t\treal_t* const row\t/**< Array of appropriate dimension for copying (number)th constraint. */\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns lower constraints' bound vector of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getLBA(\treal_t* const _lbA\t/**< Array of appropriate dimension for copying lower constraints' bound vector.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns single entry of lower constraints' bound vector of the QP.\n\t\t  *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue getLBA(\tint number,\t\t/**< Number of entry to be returned. */\n\t\t\t\t\t\t\t\t\treal_t& value\t/**< Output: lbA[number].*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns upper constraints' bound vector of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getUBA(\treal_t* const _ubA\t/**< Array of appropriate dimension for copying upper constraints' bound vector.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns single entry of upper constraints' bound vector of the QP.\n\t\t  *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue getUBA(\tint number,\t\t/**< Number of entry to be returned. */\n\t\t\t\t\t\t\t\t\treal_t& value\t/**< Output: ubA[number].*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Returns current constraints object of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getConstraints(\tConstraints* const _constraints\t/** Output: Constraints object. */\n\t\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Returns the number of constraints.\n\t\t *\t\\return Number of constraints. */\n\t\tinline int getNC( ) const;\n\n\t\t/** Returns the number of (implicitly defined) equality constraints.\n\t\t *\t\\return Number of (implicitly defined) equality constraints. */\n\t\tinline int getNEC( ) const;\n\n\t\t/** Returns the number of active constraints.\n\t\t *\t\\return Number of active constraints. */\n\t\tinline int getNAC( );\n\n\t\t/** Returns the number of inactive constraints.\n\t\t *\t\\return Number of inactive constraints. */\n\t\tinline int getNIAC( );\n\n\t\t/** Returns the dimension of null space.\n\t\t *\t\\return Dimension of null space. */\n\t\tint getNZ( );\n\n\n\t\t/** Returns the dual solution vector (deep copy).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_QP_NOT_SOLVED */\n\t\treturnValue getDualSolution(\treal_t* const yOpt\t/**< Output: Dual solution vector (if QP has been solved). */\n\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t/*\n\t *\tPROTECTED MEMBER FUNCTIONS\n\t */\n\tprotected:\n\t\t/** Determines type of constraints and bounds (i.e. implicitly fixed, unbounded etc.).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_SETUPSUBJECTTOTYPE_FAILED */\n\t\treturnValue setupSubjectToType( );\n\n\t\t/** Computes the Cholesky decomposition R of the projected Hessian (i.e. R^T*R = Z^T*H*Z).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t *\t\t\tRET_INDEXLIST_CORRUPTED */\n\t\treturnValue setupCholeskyDecompositionProjected( );\n\n\t\t/** Initialises TQ factorisation of A (i.e. A*Q = [0 T]) if NO constraint is active.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_INDEXLIST_CORRUPTED */\n\t\treturnValue setupTQfactorisation( );\n\n\n\t\t/** Solves a QProblem whose QP data is assumed to be stored in the member variables.\n\t\t *  A guess for its primal/dual optimal solution vectors and the corresponding\n\t\t *  working sets of bounds and constraints can be provided.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INIT_FAILED \\n\n\t\t\t\t\tRET_INIT_FAILED_CHOLESKY \\n\n\t\t\t\t\tRET_INIT_FAILED_TQ \\n\n\t\t\t\t\tRET_INIT_FAILED_HOTSTART \\n\n\t\t\t\t\tRET_INIT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_INIT_FAILED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED */\n\t\treturnValue solveInitialQP(\tconst real_t* const xOpt,\t\t\t\t\t\t/**< Optimal primal solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const yOpt,\t\t\t\t\t\t/**< Optimal dual solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds,\t\t\t\t/**< Guessed working set of bounds for solution (xOpt,yOpt).\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst Constraints* const guessedConstraints,\t/**< Optimal working set of constraints for solution (xOpt,yOpt).\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tint& nWSR, \t\t\t\t\t\t\t\t\t\t/**< Input: Maximum number of working set recalculations; \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t\t\t *\t Output: Number of performed working set recalculations. */\n\t\t\t\t\t\t\t\t\treal_t* const cputime\t\t\t\t\t\t\t/**< Output: CPU time required to solve QP (or to perform nWSR iterations). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Obtains the desired working set for the auxiliary initial QP in\n\t\t *  accordance with the user specifications\n\t\t *  (assumes that member AX has already been initialised!)\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_OBTAINING_WORKINGSET_FAILED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS */\n\t\treturnValue obtainAuxiliaryWorkingSet(\tconst real_t* const xOpt,\t\t\t\t\t\t/**< Optimal primal solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t If a NULL pointer is passed, all entries are assumed to be zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const yOpt,\t\t\t\t\t\t/**< Optimal dual solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t If a NULL pointer is passed, all entries are assumed to be zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds,\t\t\t\t/**< Guessed working set of bounds for solution (xOpt,yOpt). */\n\t\t\t\t\t\t\t\t\t\t\t\tconst Constraints* const guessedConstraints,\t/**< Guessed working set for solution (xOpt,yOpt). */\n\t\t\t\t\t\t\t\t\t\t\t\tBounds* auxiliaryBounds,\t\t\t\t\t\t/**< Input: Allocated bound object. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t Ouput: Working set of constraints for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\t\tConstraints* auxiliaryConstraints\t\t\t\t/**< Input: Allocated bound object. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t Ouput: Working set for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Setups bound and constraints data structures according to auxiliaryBounds/Constraints.\n\t\t *  (If the working set shall be setup afresh, make sure that\n\t\t *  bounds and constraints data structure have been resetted\n\t\t *  and the TQ factorisation has been initialised!)\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_SETUP_WORKINGSET_FAILED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS \\n\n\t\t\t\t\tRET_UNKNOWN BUG */\n\t\treturnValue setupAuxiliaryWorkingSet(\tconst Bounds* const auxiliaryBounds,\t\t\t/**< Working set of bounds for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst Constraints* const auxiliaryConstraints,\t/**< Working set of constraints for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType setupAfresh\t\t\t\t\t\t\t/**< Flag indicating if given working set shall be\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *    setup afresh or by updating the current one. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Setups the optimal primal/dual solution of the auxiliary initial QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue setupAuxiliaryQPsolution(\tconst real_t* const xOpt,\t\t\t/**< Optimal primal solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t*\t If a NULL pointer is passed, all entries are set to zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const yOpt\t\t\t/**< Optimal dual solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t If a NULL pointer is passed, all entries are set to zero. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Setups gradient of the auxiliary initial QP for given\n\t\t *  optimal primal/dual solution and given initial working set\n\t\t *  (assumes that members X, Y and BOUNDS, CONSTRAINTS have already been initialised!).\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue setupAuxiliaryQPgradient( );\n\n\t\t/** Setups (constraints') bounds of the auxiliary initial QP for given\n\t\t *  optimal primal/dual solution and given initial working set\n\t\t *  (assumes that members X, Y and BOUNDS, CONSTRAINTS have already been initialised!).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_UNKNOWN BUG */\n\t\treturnValue setupAuxiliaryQPbounds(\tconst Bounds* const auxiliaryBounds,\t\t\t/**< Working set of bounds for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\tconst Constraints* const auxiliaryConstraints,\t/**< Working set of constraints for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\tBooleanType useRelaxation\t\t\t\t\t\t/**< Flag indicating if inactive (constraints') bounds shall be relaxed. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Adds a constraint to active set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_ADDCONSTRAINT_FAILED \\n\n\t\t\t\t\tRET_ADDCONSTRAINT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_ENSURELI_FAILED */\n\t\treturnValue addConstraint(\tint number,\t\t\t\t\t/**< Number of constraint to be added to active set. */\n\t\t\t\t\t\t\t\t\tSubjectToStatus C_status,\t/**< Status of new active constraint. */\n\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\t/**< Flag indicating if Cholesky decomposition shall be updated. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Checks if new active constraint to be added is linearly dependent from\n\t\t *\tfrom row of the active constraints matrix.\n\t\t *\t\\return\t RET_LINEARLY_DEPENDENT \\n\n\t\t \t\t\t RET_LINEARLY_INDEPENDENT \\n\n\t\t\t\t\t RET_INDEXLIST_CORRUPTED */\n\t\treturnValue addConstraint_checkLI(\tint number\t\t\t/**< Number of constraint to be added to active set. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Ensures linear independence of constraint matrix when a new constraint is added.\n\t\t * \tTo this end a bound or constraint is removed simultaneously if necessary.\n\t\t *\t\\return\t SUCCESSFUL_RETURN \\n\n\t\t \t\t\t RET_LI_RESOLVED \\n\n\t\t\t\t\t RET_ENSURELI_FAILED \\n\n\t\t\t\t\t RET_ENSURELI_FAILED_TQ \\n\n\t\t\t\t\t RET_ENSURELI_FAILED_NOINDEX \\n\n\t\t\t\t\t RET_REMOVE_FROM_ACTIVESET */\n\t\treturnValue addConstraint_ensureLI(\tint number,\t\t\t\t\t/**< Number of constraint to be added to active set. */\n\t\t\t\t\t\t\t\t\t\t\tSubjectToStatus C_status\t/**< Status of new active bound. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Adds a bound to active set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_ADDBOUND_FAILED \\n\n\t\t\t\t\tRET_ADDBOUND_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_ENSURELI_FAILED */\n\t\treturnValue addBound(\tint number,\t\t\t\t\t/**< Number of bound to be added to active set. */\n\t\t\t\t\t\t\t\tSubjectToStatus B_status,\t/**< Status of new active bound. */\n\t\t\t\t\t\t\t\tBooleanType updateCholesky\t/**< Flag indicating if Cholesky decomposition shall be updated. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Checks if new active bound to be added is linearly dependent from\n\t\t *\tfrom row of the active constraints matrix.\n\t\t *\t\\return\t RET_LINEARLY_DEPENDENT \\n\n\t\t \t\t\t RET_LINEARLY_INDEPENDENT */\n\t\treturnValue addBound_checkLI(\tint number\t\t\t/**< Number of bound to be added to active set. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Ensures linear independence of constraint matrix when a new bound is added.\n\t\t *\tTo this end a bound or constraint is removed simultaneously if necessary.\n\t\t *\t\\return\t SUCCESSFUL_RETURN \\n\n\t\t \t\t\t RET_LI_RESOLVED \\n\n\t\t\t\t\t RET_ENSURELI_FAILED \\n\n\t\t\t\t\t RET_ENSURELI_FAILED_TQ \\n\n\t\t\t\t\t RET_ENSURELI_FAILED_NOINDEX \\n\n\t\t\t\t\t RET_REMOVE_FROM_ACTIVESET */\n\t\treturnValue addBound_ensureLI(\tint number,\t\t\t\t\t/**< Number of bound to be added to active set. */\n\t\t\t\t\t\t\t\t\t\tSubjectToStatus B_status\t/**< Status of new active bound. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Removes a constraint from active set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_CONSTRAINT_NOT_ACTIVE \\n\n\t\t\t\t\tRET_REMOVECONSTRAINT_FAILED \\n\n\t\t\t\t\tRET_HESSIAN_NOT_SPD */\n\t\treturnValue removeConstraint(\tint number,\t\t\t\t\t/**< Number of constraint to be removed from active set. */\n\t\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\t/**< Flag indicating if Cholesky decomposition shall be updated. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Removes a bounds from active set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_BOUND_NOT_ACTIVE \\n\n\t\t\t\t\tRET_HESSIAN_NOT_SPD \\n\n\t\t\t\t\tRET_REMOVEBOUND_FAILED */\n\t\treturnValue removeBound(\tint number,\t\t\t\t\t/**< Number of bound to be removed from active set. */\n\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\t/**< Flag indicating if Cholesky decomposition shall be updated. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Solves the system Ra = b or R^Ta = b where R is an upper triangular matrix.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_DIV_BY_ZERO */\n\t\treturnValue backsolveR(\tconst real_t* const b,\t/**< Right hand side vector. */\n\t\t\t\t\t\t\t\tBooleanType transposed,\t/**< Indicates if the transposed system shall be solved. */\n\t\t\t\t\t\t\t\treal_t* const a \t\t/**< Output: Solution vector */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Solves the system Ra = b or R^Ta = b where R is an upper triangular matrix. \\n\n\t\t *  Special variant for the case that this function is called from within \"removeBound()\".\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_DIV_BY_ZERO */\n\t\treturnValue backsolveR(\tconst real_t* const b,\t\t/**< Right hand side vector. */\n\t\t\t\t\t\t\t\tBooleanType transposed,\t\t/**< Indicates if the transposed system shall be solved. */\n\t\t\t\t\t\t\t\tBooleanType removingBound,\t/**< Indicates if function is called from \"removeBound()\". */\n\t\t\t\t\t\t\t\treal_t* const a \t\t\t/**< Output: Solution vector */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Solves the system Ta = b or T^Ta = b where T is a reverse upper triangular matrix.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_DIV_BY_ZERO */\n\t\treturnValue backsolveT(\tconst real_t* const b,\t/**< Right hand side vector. */\n\t\t\t\t\t\t\t\tBooleanType transposed,\t/**< Indicates if the transposed system shall be solved. */\n\t\t\t\t\t\t\t\treal_t* const a \t\t/**< Output: Solution vector */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Determines step direction of the shift of the QP data.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue hotstart_determineDataShift(const int* const FX_idx, \t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst int* const AC_idx, \t/**< Index array of active constraints. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const g_new,\t/**< New gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const lbA_new,/**< New lower constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const ubA_new,/**< New upper constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const lb_new,\t/**< New lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const ub_new,\t/**< New upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_g,\t \t/**< Output: Step direction of gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_lbA,\t/**< Output: Step direction of lower constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_ubA,\t/**< Output: Step direction of upper constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_lb,\t \t/**< Output: Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_ub,\t \t/**< Output: Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType& Delta_bC_isZero,/**< Output: Indicates if active constraints' bounds are to be shifted. */\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType& Delta_bB_isZero/**< Output: Indicates if active bounds are to be shifted. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Determines step direction of the homotopy path.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_STEPDIRECTION_FAILED_TQ \\n\n\t\t\t\t\tRET_STEPDIRECTION_FAILED_CHOLESKY */\n\t\treturnValue hotstart_determineStepDirection(const int* const FR_idx, \t\t/**< Index array of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const FX_idx, \t\t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const AC_idx, \t\t/**< Index array of active constraints. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g,\t/**< Step direction of gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lbA,\t/**< Step direction of lower constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ubA,\t/**< Step direction of upper constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb,\t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType Delta_bC_isZero, \t/**< Indicates if active constraints' bounds are to be shifted. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType Delta_bB_isZero,\t/**< Indicates if active bounds are to be shifted. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_xFX, \t\t/**< Output: Primal homotopy step direction of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_xFR,\t \t/**< Output: Primal homotopy step direction of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_yAC, \t\t/**< Output: Dual homotopy step direction of active constraints' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_yFX \t\t/**< Output: Dual homotopy step direction of fixed variables' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Determines the maximum possible step length along the homotopy path.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue hotstart_determineStepLength(\tconst int* const FR_idx, \t\t\t/**< Index array of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const FX_idx, \t\t\t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const AC_idx, \t\t\t/**< Index array of active constraints. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const IAC_idx, \t\t\t/**< Index array of inactive constraints. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lbA,\t\t/**< Step direction of lower constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ubA,\t\t/**< Step direction of upper constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb,\t \t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t \t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFX, \t\t/**< Primal homotopy step direction of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFR,\t\t/**< Primal homotopy step direction of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yAC,\t\t/**< Dual homotopy step direction of active constraints' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yFX,\t\t/**< Dual homotopy step direction of fixed variables' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_Ax,\t\t\t\t/**< Output: Step in vector Ax. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tint& BC_idx, \t\t\t\t\t\t/**< Output: Index of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tSubjectToStatus& BC_status,\t\t\t/**< Output: Status of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType& BC_isBound \t\t\t/**< Output: Indicates if blocking constraint is a bound. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Performs a step along the homotopy path (and updates active set).\n\t\t *\t\\return  SUCCESSFUL_RETURN \\n\n\t\t \t\t\t RET_OPTIMAL_SOLUTION_FOUND \\n\n\t\t \t\t\t RET_REMOVE_FROM_ACTIVESET_FAILED \\n\n\t\t\t\t\t RET_ADD_TO_ACTIVESET_FAILED \\n\n\t\t\t\t\t RET_QP_INFEASIBLE */\n\t\treturnValue hotstart_performStep(\tconst int* const FR_idx, \t\t\t/**< Index array of free variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst int* const FX_idx, \t\t\t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst int* const AC_idx, \t\t\t/**< Index array of active constraints. */\n\t\t\t\t\t\t\t\t\t\t\tconst int* const IAC_idx, \t\t\t/**< Index array of inactive constraints. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g,\t \t/**< Step direction of gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lbA,\t \t/**< Step direction of lower constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ubA,\t \t/**< Step direction of upper constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb,\t \t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t \t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFX, \t\t/**< Primal homotopy step direction of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFR,\t \t/**< Primal homotopy step direction of free variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yAC,\t \t/**< Dual homotopy step direction of active constraints' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yFX, \t\t/**< Dual homotopy step direction of fixed variables' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_Ax, \t\t/**< Step in vector Ax. */\n\t\t\t\t\t\t\t\t\t\t\tint BC_idx, \t\t\t\t\t\t/**< Index of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\tSubjectToStatus BC_status,\t\t\t/**< Status of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\tBooleanType BC_isBound \t\t\t\t/**< Indicates if blocking constraint is a bound. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Checks if lower/upper (constraints') bounds remain consistent\n\t\t *  (i.e. if lb <= ub and lbA <= ubA ) during the current step.\n\t\t *\t\\return BT_TRUE iff (constraints\") bounds remain consistent\n\t\t */\n\t\tBooleanType areBoundsConsistent(\tconst real_t* const delta_lb,\t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lbA,\t/**< Step direction of lower constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ubA\t/**< Step direction of upper constraints' bounds. */\n\t\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Setups internal QP data.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS */\n\t\treturnValue setupQPdata(\tconst real_t* const _H, \t/**< Hessian matrix. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _R, \t/**< Cholesky factorization of the Hessian matrix. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _g, \t/**< Gradient vector. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _A,  \t/**< Constraint matrix. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _lb,\t/**< Lower bound vector (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t If no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _ub,\t/**< Upper bound vector (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t If no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _lbA,\t/**< Lower constraints' bound vector. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t If no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _ubA\t/**< Upper constraints' bound vector. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t If no lower constraints' bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t#ifdef PC_DEBUG  /* Define print functions only for debugging! */\n\n\t\t/** Prints concise information on the current iteration.\n\t\t *\t\\return  SUCCESSFUL_RETURN \\n */\n\t\treturnValue printIteration(\tint iteration,\t\t\t\t/**< Number of current iteration. */\n\t\t\t\t\t\t\t\t\tint BC_idx, \t\t\t\t/**< Index of blocking constraint. */\n\t\t\t\t\t\t\t\t\tSubjectToStatus BC_status,\t/**< Status of blocking constraint. */\n\t\t\t\t\t\t\t\t\tBooleanType BC_isBound \t\t/**< Indicates if blocking constraint is a bound. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Prints concise information on the current iteration.\n\t\t *  NOTE: ONLY DEFINED FOR SUPPRESSING A COMPILER WARNING!!\n\t\t *\t\\return  SUCCESSFUL_RETURN \\n */\n\t\treturnValue printIteration(\tint iteration,\t\t\t\t/**< Number of current iteration. */\n\t\t\t\t\t\t\t\t\tint BC_idx, \t\t\t\t/**< Index of blocking bound. */\n\t\t\t\t\t\t\t\t\tSubjectToStatus BC_status\t/**< Status of blocking bound. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t#endif  /* PC_DEBUG */\n\n\n\t\t/** Determines the maximum violation of the KKT optimality conditions\n\t\t *  of the current iterate within the QProblem object.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t * \t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t * \t\t\tRET_NO_SOLUTION */\n\t\treturnValue checkKKTconditions( );\n\n\n\t\t/** Sets constraint matrix of the QP. \\n\n\t\t\t(Remark: Also internal vector Ax is recomputed!)\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setA(\tconst real_t* const A_new\t/**< New constraint matrix (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes single row of constraint matrix of the QP. \\n\n\t\t\t(Remark: Also correponding component of internal vector Ax is recomputed!)\n\t\t *\t\\return SUCCESSFUL_RETURN  \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setA(\tint number,\t\t\t\t\t/**< Number of row to be changed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const value\t/**< New (number)th constraint (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Sets constraints' lower bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setLBA(\tconst real_t* const lbA_new\t/**< New constraints' lower bound vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes single entry of lower constraints' bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN  \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setLBA(\tint number,\t\t/**< Number of entry to be changed. */\n\t\t\t\t\t\t\t\t\treal_t value\t/**< New value for entry of lower constraints' bound vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Sets constraints' upper bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setUBA(\tconst real_t* const ubA_new\t/**< New constraints' upper bound vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes single entry of upper constraints' bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN  \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setUBA(\tint number,\t\t/**< Number of entry to be changed. */\n\t\t\t\t\t\t\t\t\treal_t value\t/**< New value for entry of upper constraints' bound vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\treal_t A[NCMAX_ALLOC*NVMAX];\t\t/**< Constraint matrix. */\n\t\treal_t lbA[NCMAX_ALLOC];\t\t\t/**< Lower constraints' bound vector. */\n\t\treal_t ubA[NCMAX_ALLOC];\t\t\t/**< Upper constraints' bound vector. */\n\n\t\tConstraints constraints;\t\t\t/**< Data structure for problem's constraints. */\n\n\t\treal_t T[NVMAX*NVMAX];\t\t\t\t/**< Reverse triangular matrix, A = [0 T]*Q'. */\n\t\treal_t Q[NVMAX*NVMAX];\t\t\t\t/**< Orthonormal quadratic matrix, A = [0 T]*Q'. */\n\t\tint sizeT;\t\t\t\t\t\t\t/**< Matrix T is stored in a (sizeT x sizeT) array. */\n\n\t\treal_t Ax[NCMAX_ALLOC];\t\t\t\t/**< Stores the current product A*x (for increased efficiency only). */\n\n\t\tCyclingManager cyclingManager;\t\t/**< Data structure for storing (possible) cycling information (NOT YET IMPLEMENTED!). */\n};\n\n\n#include <QProblem.ipp>\n\n#endif\t/* QPOASES_QPROBLEM_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/QProblemB.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/QProblemB.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the QProblemB class which is able to use the newly\n *\tdeveloped online active set strategy for parametric quadratic programming\n *\tfor problems with (simple) bounds only.\n */\n\n\n\n#ifndef QPOASES_QPROBLEMB_HPP\n#define QPOASES_QPROBLEMB_HPP\n\n\n#include <Bounds.hpp>\n\n\n\nclass SolutionAnalysis;\n\n/** Class for setting up and solving quadratic programs with (simple) bounds only.\n *\tThe main feature is the possibily to use the newly developed online active set strategy\n *\tfor parametric quadratic programming.\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass QProblemB\n{\n\t/* allow SolutionAnalysis class to access private members */\n\tfriend class SolutionAnalysis;\n\t\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tQProblemB( );\n\n\t\t/** Constructor which takes the QP dimension only. */\n\t\tQProblemB(\tint _nV\t\t\t\t\t\t/**< Number of variables. */\n\t\t\t\t\t);\n\n\t\t/** Copy constructor (deep copy). */\n\t\tQProblemB(\tconst QProblemB& rhs\t/**< Rhs object. */\n\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~QProblemB( );\n\n\t\t/** Assignment operator (deep copy). */\n\t\tQProblemB& operator=(\tconst QProblemB& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Clears all data structures of QProblemB except for QP data.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_RESET_FAILED */\n\t\treturnValue reset( );\n\n\n\t\t/** Initialises a QProblemB with given QP data and solves it\n\t\t *\tusing an initial homotopy with empty working set (at most nWSR iterations).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INIT_FAILED \\n\n\t\t\t\t\tRET_INIT_FAILED_CHOLESKY \\n\n\t\t\t\t\tRET_INIT_FAILED_HOTSTART \\n\n\t\t\t\t\tRET_INIT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_INIT_FAILED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS \\n\n\t\t\t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t \t\t\tRET_NO_SOLUTION */\n\t\treturnValue init(\tconst real_t* const _H, \t\t/**< Hessian matrix. */\n\t\t\t\t\t\t\tconst real_t* const _g,\t\t\t/**< Gradient vector. */\n\t\t\t\t\t\t\tconst real_t* const _lb,\t\t/**< Lower bounds (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _ub,\t\t/**< Upper bounds (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tint& nWSR, \t\t\t\t\t\t/**< Input: Maximum number of working set recalculations when using initial homotopy. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOutput: Number of performed working set recalculations. */\n\t\t\t\t\t\t\tconst real_t* const yOpt = 0,\t/**< Initial guess for dual solution vector. */\n\t\t\t\t \t\t\treal_t* const cputime = 0\t\t/**< Output: CPU time required to initialise QP. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Initialises a QProblemB with given QP data and solves it\n\t\t *\tusing an initial homotopy with empty working set (at most nWSR iterations).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INIT_FAILED \\n\n\t\t\t\t\tRET_INIT_FAILED_CHOLESKY \\n\n\t\t\t\t\tRET_INIT_FAILED_HOTSTART \\n\n\t\t\t\t\tRET_INIT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_INIT_FAILED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS \\n\n\t\t\t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t \t\t\tRET_NO_SOLUTION */\n\t\treturnValue init(\tconst real_t* const _H, \t\t/**< Hessian matrix. */\n\t\t\t\t\t\t\tconst real_t* const _R, \t\t/**< Cholesky factorization of the Hessian matrix. */\n\t\t\t\t\t\t\tconst real_t* const _g,\t\t\t/**< Gradient vector. */\n\t\t\t\t\t\t\tconst real_t* const _lb,\t\t/**< Lower bounds (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tconst real_t* const _ub,\t\t/**< Upper bounds (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIf no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\tint& nWSR, \t\t\t\t\t\t/**< Input: Maximum number of working set recalculations when using initial homotopy. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOutput: Number of performed working set recalculations. */\n\t\t\t\t\t\t\tconst real_t* const yOpt = 0,\t/**< Initial guess for dual solution vector. */\n\t\t\t\t \t\t\treal_t* const cputime = 0\t\t/**< Output: CPU time required to initialise QP. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Solves an initialised QProblemB using online active set strategy.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED \\n\n\t\t\t\t\tRET_HOTSTART_FAILED_AS_QP_NOT_INITIALISED \\n\n\t\t\t\t\tRET_HOTSTART_FAILED \\n\n\t\t\t\t\tRET_SHIFT_DETERMINATION_FAILED \\n\n\t\t\t\t\tRET_STEPDIRECTION_DETERMINATION_FAILED \\n\n\t\t\t\t\tRET_STEPLENGTH_DETERMINATION_FAILED \\n\n\t\t\t\t\tRET_HOMOTOPY_STEP_FAILED \\n\n\t\t\t\t\tRET_HOTSTART_STOPPED_INFEASIBILITY \\n\n\t\t\t\t\tRET_HOTSTART_STOPPED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t \t\t\tRET_NO_SOLUTION */\n\t\treturnValue hotstart(\tconst real_t* const g_new,\t/**< Gradient of neighbouring QP to be solved. */\n\t\t\t\t\t\t\t\tconst real_t* const lb_new,\t/**< Lower bounds of neighbouring QP to be solved. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t If no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\tconst real_t* const ub_new,\t/**< Upper bounds of neighbouring QP to be solved. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t\t If no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\tint& nWSR,\t\t\t\t\t/**< Input: Maximum number of working set recalculations; \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t Output: Number of performed working set recalculations. */\n\t\t\t\t\t\t\t\treal_t* const cputime\t\t/**< Output: CPU time required to solve QP (or to perform nWSR iterations). */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns Hessian matrix of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getH(\treal_t* const _H\t/**< Array of appropriate dimension for copying Hessian matrix.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns gradient vector of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getG(\treal_t* const _g\t/**< Array of appropriate dimension for copying gradient vector.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns lower bound vector of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getLB(\treal_t* const _lb\t/**< Array of appropriate dimension for copying lower bound vector.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns single entry of lower bound vector of the QP.\n\t\t  *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue getLB(\tint number,\t\t/**< Number of entry to be returned. */\n\t\t\t\t\t\t\t\t\treal_t& value\t/**< Output: lb[number].*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns upper bound vector of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getUB(\treal_t* const _ub\t/**< Array of appropriate dimension for copying upper bound vector.*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns single entry of upper bound vector of the QP.\n\t\t  *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue getUB(\tint number,\t\t/**< Number of entry to be returned. */\n\t\t\t\t\t\t\t\t\treal_t& value\t/**< Output: ub[number].*/\n\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Returns current bounds object of the QP (deep copy).\n\t\t  *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue getBounds(\tBounds* const _bounds\t/** Output: Bounds object. */\n\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Returns the number of variables.\n\t\t *\t\\return Number of variables. */\n\t\tinline int getNV( ) const;\n\n\t\t/** Returns the number of free variables.\n\t\t *\t\\return Number of free variables. */\n\t\tinline int getNFR( );\n\n\t\t/** Returns the number of fixed variables.\n\t\t *\t\\return Number of fixed variables. */\n\t\tinline int getNFX( );\n\n\t\t/** Returns the number of implicitly fixed variables.\n\t\t *\t\\return Number of implicitly fixed variables. */\n\t\tinline int getNFV( ) const;\n\n\t\t/** Returns the dimension of null space.\n\t\t *\t\\return Dimension of null space. */\n\t\tint getNZ( );\n\n\n\t\t/** Returns the optimal objective function value.\n\t\t *\t\\return finite value: Optimal objective function value (QP was solved) \\n\n\t\t \t\t\t+infinity:\t  QP was not yet solved */\n\t\treal_t getObjVal( ) const;\n\n\t\t/** Returns the objective function value at an arbitrary point x.\n\t\t *\t\\return Objective function value at point x */\n\t\treal_t getObjVal(\tconst real_t* const _x\t/**< Point at which the objective function shall be evaluated. */\n\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns the primal solution vector.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_QP_NOT_SOLVED */\n\t\treturnValue getPrimalSolution(\treal_t* const xOpt\t\t\t/**< Output: Primal solution vector (if QP has been solved). */\n\t\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Returns the dual solution vector.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_QP_NOT_SOLVED */\n\t\treturnValue getDualSolution(\treal_t* const yOpt\t/**< Output: Dual solution vector (if QP has been solved). */\n\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Returns status of the solution process.\n\t\t *\t\\return Status of solution process. */\n\t\tinline QProblemStatus getStatus( ) const;\n\n\n\t\t/** Returns if the QProblem object is initialised.\n\t\t *\t\\return BT_TRUE:  QProblemB initialised \\n\n\t\t \t\t\tBT_FALSE: QProblemB not initialised */\n\t\tinline BooleanType isInitialised( ) const;\n\n\t\t/** Returns if the QP has been solved.\n\t\t *\t\\return BT_TRUE:  QProblemB solved \\n\n\t\t \t\t\tBT_FALSE: QProblemB not solved */\n\t\tinline BooleanType isSolved( ) const;\n\n\t\t/** Returns if the QP is infeasible.\n\t\t *\t\\return BT_TRUE:  QP infeasible \\n\n\t\t \t\t\tBT_FALSE: QP feasible (or not known to be infeasible!) */\n\t\tinline BooleanType isInfeasible( ) const;\n\n\t\t/** Returns if the QP is unbounded.\n\t\t *\t\\return BT_TRUE:  QP unbounded \\n\n\t\t \t\t\tBT_FALSE: QP unbounded (or not known to be unbounded!) */\n\t\tinline BooleanType isUnbounded( ) const;\n\n\n\t\t/** Returns the print level.\n\t\t *\t\\return Print level. */\n\t\tinline PrintLevel getPrintLevel( ) const;\n\n\t\t/** Changes the print level.\n \t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue setPrintLevel(\tPrintLevel _printlevel\t/**< New print level. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns Hessian type flag (type is not determined due to this call!).\n\t\t *\t\\return Hessian type. */\n\t\tinline HessianType getHessianType( ) const;\n\n\t\t/** Changes the print level.\n \t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setHessianType(\tHessianType _hessianType /**< New Hessian type. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t/*\n\t *\tPROTECTED MEMBER FUNCTIONS\n\t */\n\tprotected:\n\t\t/** Checks if Hessian happens to be the identity matrix,\n\t\t *  and sets corresponding status flag (otherwise the flag remains unaltered!).\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue checkForIdentityHessian( );\n\n\t\t/** Determines type of constraints and bounds (i.e. implicitly fixed, unbounded etc.).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_SETUPSUBJECTTOTYPE_FAILED */\n\t\treturnValue setupSubjectToType( );\n\n\t\t/** Computes the Cholesky decomposition R of the (simply projected) Hessian (i.e. R^T*R = Z^T*H*Z).\n\t\t *  It only works in the case where Z is a simple projection matrix!\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t *\t\t\tRET_INDEXLIST_CORRUPTED */\n\t\treturnValue setupCholeskyDecomposition( );\n\n\n\t\t/** Solves a QProblemB whose QP data is assumed to be stored in the member variables.\n\t\t *  A guess for its primal/dual optimal solution vectors and the corresponding\n\t\t *  optimal working set can be provided.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INIT_FAILED \\n\n\t\t\t\t\tRET_INIT_FAILED_CHOLESKY \\n\n\t\t\t\t\tRET_INIT_FAILED_HOTSTART \\n\n\t\t\t\t\tRET_INIT_FAILED_INFEASIBILITY \\n\n\t\t\t\t\tRET_INIT_FAILED_UNBOUNDEDNESS \\n\n\t\t\t\t\tRET_MAX_NWSR_REACHED */\n\t\treturnValue solveInitialQP(\tconst real_t* const xOpt,\t\t\t/**< Optimal primal solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const yOpt,\t\t\t/**< Optimal dual solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds,\t/**< Guessed working set for solution (xOpt,yOpt).\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t A NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tint& nWSR, \t\t\t\t\t\t\t/**< Input: Maximum number of working set recalculations; \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t\t *\t Output: Number of performed working set recalculations. */\n\t\t\t\t\t\t\t\t\treal_t* const cputime\t\t\t\t/**< Output: CPU time required to solve QP (or to perform nWSR iterations). */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Obtains the desired working set for the auxiliary initial QP in\n\t\t *  accordance with the user specifications\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_OBTAINING_WORKINGSET_FAILED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS */\n\t\treturnValue obtainAuxiliaryWorkingSet(\tconst real_t* const xOpt,\t\t\t/**< Optimal primal solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t If a NULL pointer is passed, all entries are assumed to be zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const yOpt,\t\t\t/**< Optimal dual solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t If a NULL pointer is passed, all entries are assumed to be zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds,\t/**< Guessed working set for solution (xOpt,yOpt). */\n\t\t\t\t\t\t\t\t\t\t\t\tBounds* auxiliaryBounds\t\t\t\t/**< Input: Allocated bound object. \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t Ouput: Working set for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Setups bound data structure according to auxiliaryBounds.\n\t\t *  (If the working set shall be setup afresh, make sure that\n\t\t *  bounds data structure has been resetted!)\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_SETUP_WORKINGSET_FAILED \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS \\n\n\t\t\t\t\tRET_UNKNOWN BUG */\n\t\treturnValue setupAuxiliaryWorkingSet(\tconst Bounds* const auxiliaryBounds,\t/**< Working set for auxiliary QP. */\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType setupAfresh\t\t\t\t\t/**< Flag indicating if given working set shall be\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *    setup afresh or by updating the current one. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Setups the optimal primal/dual solution of the auxiliary initial QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue setupAuxiliaryQPsolution(\tconst real_t* const xOpt,\t\t\t/**< Optimal primal solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \t*\t If a NULL pointer is passed, all entries are set to zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const yOpt\t\t\t/**< Optimal dual solution vector.\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t *\t If a NULL pointer is passed, all entries are set to zero. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Setups gradient of the auxiliary initial QP for given\n\t\t *  optimal primal/dual solution and given initial working set\n\t\t *  (assumes that members X, Y and BOUNDS have already been initialised!).\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue setupAuxiliaryQPgradient( );\n\n\t\t/** Setups bounds of the auxiliary initial QP for given\n\t\t *  optimal primal/dual solution and given initial working set\n\t\t *  (assumes that members X, Y and BOUNDS have already been initialised!).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_UNKNOWN BUG */\n\t\treturnValue setupAuxiliaryQPbounds( BooleanType useRelaxation\t/**< Flag indicating if inactive bounds shall be relaxed. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Adds a bound to active set (specialised version for the case where no constraints exist).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_ADDBOUND_FAILED */\n\t\treturnValue addBound(\tint number,\t\t\t\t\t/**< Number of bound to be added to active set. */\n\t\t\t\t\t\t\t\tSubjectToStatus B_status,\t/**< Status of new active bound. */\n\t\t\t\t\t\t\t\tBooleanType updateCholesky\t/**< Flag indicating if Cholesky decomposition shall be updated. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Removes a bounds from active set (specialised version for the case where no constraints exist).\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_HESSIAN_NOT_SPD \\n\n\t\t\t\t\tRET_REMOVEBOUND_FAILED */\n\t\treturnValue removeBound(\tint number,\t\t\t\t\t/**< Number of bound to be removed from active set. */\n\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\t/**< Flag indicating if Cholesky decomposition shall be updated. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Solves the system Ra = b or R^Ta = b where R is an upper triangular matrix.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_DIV_BY_ZERO */\n\t\treturnValue backsolveR(\tconst real_t* const b,\t/**< Right hand side vector. */\n\t\t\t\t\t\t\t\tBooleanType transposed,\t/**< Indicates if the transposed system shall be solved. */\n\t\t\t\t\t\t\t\treal_t* const a \t\t/**< Output: Solution vector */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Solves the system Ra = b or R^Ta = b where R is an upper triangular matrix. \\n\n\t\t *  Special variant for the case that this function is called from within \"removeBound()\".\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_DIV_BY_ZERO */\n\t\treturnValue backsolveR(\tconst real_t* const b,\t\t/**< Right hand side vector. */\n\t\t\t\t\t\t\t\tBooleanType transposed,\t\t/**< Indicates if the transposed system shall be solved. */\n\t\t\t\t\t\t\t\tBooleanType removingBound,\t/**< Indicates if function is called from \"removeBound()\". */\n\t\t\t\t\t\t\t\treal_t* const a \t\t\t/**< Output: Solution vector */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Determines step direction of the shift of the QP data.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue hotstart_determineDataShift(const int* const FX_idx, \t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const g_new,\t/**< New gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const lb_new,\t/**< New lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const ub_new,\t/**< New upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_g,\t \t/**< Output: Step direction of gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_lb,\t \t/**< Output: Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_ub,\t \t/**< Output: Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType& Delta_bB_isZero/**< Output: Indicates if active bounds are to be shifted. */\n\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Checks if lower/upper bounds remain consistent\n\t\t *  (i.e. if lb <= ub) during the current step.\n\t\t *\t\\return BT_TRUE iff bounds remain consistent\n\t\t */\n\t\tBooleanType areBoundsConsistent(\tconst real_t* const delta_lb,\t\t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub\t\t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Setups internal QP data.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t\t\t\tRET_INVALID_ARGUMENTS */\n\t\treturnValue setupQPdata(\tconst real_t* const _H, \t/**< Hessian matrix. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _R, \t/**< Cholesky factorization of the Hessian matrix. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _g,\t\t/**< Gradient vector. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _lb,\t/**< Lower bounds (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t If no lower bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\tconst real_t* const _ub\t\t/**< Upper bounds (on variables). \\n\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t If no upper bounds exist, a NULL pointer can be passed. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Sets Hessian matrix of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setH(\tconst real_t* const H_new\t/**< New Hessian matrix (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes gradient vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setG(\tconst real_t* const g_new\t/**< New gradient vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes lower bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setLB(\tconst real_t* const lb_new\t/**< New lower bound vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes single entry of lower bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN  \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setLB(\tint number,\t\t/**< Number of entry to be changed. */\n\t\t\t\t\t\t\t\t\treal_t value\t/**< New value for entry of lower bound vector. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes upper bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline returnValue setUB(\tconst real_t* const ub_new\t/**< New upper bound vector (with correct dimension!). */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Changes single entry of upper bound vector of the QP.\n\t\t *\t\\return SUCCESSFUL_RETURN  \\n\n\t\t\t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setUB(\tint number,\t\t/**< Number of entry to be changed. */\n\t\t\t\t\t\t\t\t\treal_t value\t/**< New value for entry of upper bound vector. */\n\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Computes parameters for the Givens matrix G for which [x,y]*G = [z,0]\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline void computeGivens(\treal_t xold,\t/**< Matrix entry to be normalised. */\n\t\t\t\t\t\t\t\t\treal_t yold,\t/**< Matrix entry to be annihilated. */\n\t\t\t\t\t\t\t\t\treal_t& xnew,\t/**< Output: Normalised matrix entry. */\n\t\t\t\t\t\t\t\t\treal_t& ynew,\t/**< Output: Annihilated matrix entry. */\n\t\t\t\t\t\t\t\t\treal_t& c,\t\t/**< Output: Cosine entry of Givens matrix. */\n\t\t\t\t\t\t\t\t\treal_t& s \t\t/**< Output: Sine entry of Givens matrix. */\n\t\t\t\t\t\t\t\t\t) const;\n\n\t\t/** Applies Givens matrix determined by c and s (cf. computeGivens).\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\tinline void applyGivens(\treal_t c,\t\t/**< Cosine entry of Givens matrix. */\n\t\t\t\t\t\t\t\t\treal_t s,\t\t/**< Sine entry of Givens matrix. */\n\t\t\t\t\t\t\t\t\treal_t xold,\t/**< Matrix entry to be transformed corresponding to\n\t\t\t\t\t\t\t\t\t\t\t\t\t *\t the normalised entry of the original matrix. */\n\t\t\t\t\t\t\t\t\treal_t yold, \t/**< Matrix entry to be transformed corresponding to\n\t\t\t\t\t\t\t\t\t\t\t\t\t *\t the annihilated entry of the original matrix. */\n\t\t\t\t\t\t\t\t\treal_t& xnew,\t/**< Output: Transformed matrix entry corresponding to\n\t\t\t\t\t\t\t\t\t\t\t\t\t *\t the normalised entry of the original matrix. */\n\t\t\t\t\t\t\t\t\treal_t& ynew\t/**< Output: Transformed matrix entry corresponding to\n\t\t\t\t\t\t\t\t\t\t\t\t\t *\t the annihilated entry of the original matrix. */\n\t\t\t\t\t\t\t\t\t) const;\n\n\n\t/*\n\t *\tPRIVATE MEMBER FUNCTIONS\n\t */\n\tprivate:\n\t\t/** Determines step direction of the homotopy path.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_STEPDIRECTION_FAILED_CHOLESKY */\n\t\treturnValue hotstart_determineStepDirection(const int* const FR_idx, \t\t/**< Index array of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const FX_idx, \t\t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g,\t/**< Step direction of gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb,\t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType Delta_bB_isZero,\t/**< Indicates if active bounds are to be shifted. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_xFX, \t\t/**< Output: Primal homotopy step direction of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_xFR,\t \t/**< Output: Primal homotopy step direction of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_yFX \t\t/**< Output: Dual homotopy step direction of fixed variables' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Determines the maximum possible step length along the homotopy path.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue hotstart_determineStepLength(\tconst int* const FR_idx, \t\t/**< Index array of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst int* const FX_idx, \t\t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb,\t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFR,\t/**< Primal homotopy step direction of free variables. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yFX,\t/**< Dual homotopy step direction of fixed variables' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tint& BC_idx, \t\t\t\t\t/**< Output: Index of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\t\t\tSubjectToStatus& BC_status\t\t/**< Output: Status of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Performs a step along the homotopy path (and updates active set).\n\t\t *\t\\return  SUCCESSFUL_RETURN \\n\n\t\t \t\t\t RET_OPTIMAL_SOLUTION_FOUND \\n\n\t\t \t\t\t RET_REMOVE_FROM_ACTIVESET_FAILED \\n\n\t\t\t\t\t RET_ADD_TO_ACTIVESET_FAILED \\n\n\t\t\t\t\t RET_QP_INFEASIBLE */\n\t\treturnValue hotstart_performStep(\tconst int* const FR_idx, \t\t\t/**< Index array of free variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst int* const FX_idx, \t\t\t/**< Index array of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g,\t \t/**< Step direction of gradient vector. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb,\t \t/**< Step direction of lower bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_ub,\t \t/**< Step direction of upper bounds. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFX, \t\t/**< Primal homotopy step direction of fixed variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFR,\t \t/**< Primal homotopy step direction of free variables. */\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yFX, \t\t/**< Dual homotopy step direction of fixed variables' multiplier. */\n\t\t\t\t\t\t\t\t\t\t\tint BC_idx, \t\t\t\t\t\t/**< Index of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\tSubjectToStatus BC_status \t\t\t/**< Status of blocking constraint. */\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t#ifdef PC_DEBUG  /* Define print functions only for debugging! */\n\n\t\t/** Prints concise information on the current iteration.\n\t\t *\t\\return  SUCCESSFUL_RETURN \\n */\n\t\treturnValue printIteration(\tint iteration,\t\t\t\t/**< Number of current iteration. */\n\t\t\t\t\t\t\t\t\tint BC_idx, \t\t\t\t/**< Index of blocking bound. */\n\t\t\t\t\t\t\t\t\tSubjectToStatus BC_status\t/**< Status of blocking bound. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t#endif  /* PC_DEBUG */\n\n\n\t\t/** Determines the maximum violation of the KKT optimality conditions\n\t\t *  of the current iterate within the QProblemB object.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t * \t\t\tRET_INACCURATE_SOLUTION \\n\n\t\t * \t\t\tRET_NO_SOLUTION */\n\t\treturnValue checkKKTconditions( );\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\treal_t H[NVMAX*NVMAX];\t\t/**< Hessian matrix. */\n\t\tBooleanType hasHessian;\t\t/**< Flag indicating whether H contains Hessian or corresponding Cholesky factor R; \\sa init. */\n\n\t\treal_t g[NVMAX];\t\t\t/**< Gradient. */\n\t\treal_t lb[NVMAX];\t\t\t/**< Lower bound vector (on variables). */\n\t\treal_t ub[NVMAX];\t\t\t/**< Upper bound vector (on variables). */\n\n\t\tBounds bounds;\t\t\t\t/**< Data structure for problem's bounds. */\n\n\t\treal_t R[NVMAX*NVMAX];\t\t/**< Cholesky decomposition of H (i.e. H = R^T*R). */\n\t\tBooleanType hasCholesky;\t/**< Flag indicating whether Cholesky decomposition has already been setup. */\n\n\t\treal_t x[NVMAX];\t\t\t/**< Primal solution vector. */\n\t\treal_t y[NVMAX+NCMAX];\t\t/**< Dual solution vector. */\n\n\t\treal_t tau;\t\t\t\t\t/**< Last homotopy step length. */\n\n\t\tQProblemStatus status;\t\t/**< Current status of the solution process. */\n\n\t\tBooleanType infeasible;\t\t/**< QP infeasible? */\n\t\tBooleanType unbounded;\t\t/**< QP unbounded? */\n\n\t\tHessianType hessianType;\t/**< Type of Hessian matrix. */\n\n\t\tPrintLevel printlevel;\t\t/**< Print level. */\n\n\t\tint count;\t\t\t\t\t/**< Counts the number of hotstart function calls (internal usage only!). */\n};\n\n\n#include <QProblemB.ipp>\n\n#endif\t/* QPOASES_QPROBLEMB_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/SubjectTo.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/SubjectTo.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of the SubjectTo class designed to manage working sets of\n *\tconstraints and bounds within a QProblem.\n */\n\n\n#ifndef QPOASES_SUBJECTTO_HPP\n#define QPOASES_SUBJECTTO_HPP\n\n\n#include <Indexlist.hpp>\n\n\n\n/** This class manages working sets of constraints and bounds by storing\n *\tindex sets and other status information.\n *\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n */\nclass SubjectTo\n{\n\t/*\n\t *\tPUBLIC MEMBER FUNCTIONS\n\t */\n\tpublic:\n\t\t/** Default constructor. */\n\t\tSubjectTo( );\n\n\t\t/** Copy constructor (deep copy). */\n\t\tSubjectTo(\tconst SubjectTo& rhs\t/**< Rhs object. */\n\t\t\t\t\t);\n\n\t\t/** Destructor. */\n\t\t~SubjectTo( );\n\n\t\t/** Assignment operator (deep copy). */\n\t\tSubjectTo& operator=(\tconst SubjectTo& rhs\t/**< Rhs object. */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Pseudo-constructor takes the number of constraints or bounds.\n\t\t *\t\\return SUCCESSFUL_RETURN */\n\t\treturnValue init(\tint n \t/**< Number of constraints or bounds. */\n\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns type of (constraints') bound.\n\t\t *\t\\return Type of (constraints') bound \\n\n\t\t \t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline SubjectToType getType(\tint i\t\t/**< Number of (constraints') bound. */\n\t\t\t\t\t\t\t\t\t\t) const ;\n\n\t\t/** Returns status of (constraints') bound.\n\t\t *\t\\return Status of (constraints') bound \\n\n\t\t \t\t\tST_UNDEFINED */\n\t\tinline SubjectToStatus getStatus(\tint i\t\t/**< Number of (constraints') bound. */\n\t\t\t\t\t\t\t\t\t\t\t) const;\n\n\n\t\t/** Sets type of (constraints') bound.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setType(\tint i,\t\t\t\t/**< Number of (constraints') bound. */\n\t\t\t\t\t\t\t\t\tSubjectToType value\t/**< Type of (constraints') bound. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Sets status of (constraints') bound.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_INDEX_OUT_OF_BOUNDS */\n\t\tinline returnValue setStatus(\tint i,\t\t\t\t\t/**< Number of (constraints') bound. */\n\t\t\t\t\t\t\t\t\t\tSubjectToStatus value\t/**< Status of (constraints') bound. */\n\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Sets status of lower (constraints') bounds. */\n\t\tinline void setNoLower(\tBooleanType _status\t\t/**< Status of lower (constraints') bounds. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Sets status of upper (constraints') bounds. */\n\t\tinline void setNoUpper(\tBooleanType _status\t\t/**< Status of upper (constraints') bounds. */\n\t\t\t\t\t\t\t\t);\n\n\n\t\t/** Returns status of lower (constraints') bounds.\n\t\t *\t\\return BT_TRUE if there is no lower (constraints') bound on any variable. */\n\t\tinline BooleanType isNoLower( ) const;\n\n\t\t/** Returns status of upper bounds.\n\t\t *\t\\return BT_TRUE if there is no upper (constraints') bound on any variable. */\n\t\tinline BooleanType isNoUpper( ) const;\n\n\n\t/*\n\t *\tPROTECTED MEMBER FUNCTIONS\n\t */\n\tprotected:\n\t\t/** Adds the index of a new constraint or bound to index set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_ADDINDEX_FAILED */\n\t\treturnValue addIndex(\tIndexlist* const indexlist,\t/**< Index list to which the new index shall be added. */\n\t\t\t\t\t\t\t\tint newnumber,\t\t\t\t/**< Number of new constraint or bound. */\n\t\t\t\t\t\t\t\tSubjectToStatus newstatus\t/**< Status of new constraint or bound. */\n\t\t\t\t\t\t\t\t);\n\n\t\t/** Removes the index of a constraint or bound from index set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_UNKNOWN_BUG */\n\t\treturnValue removeIndex(\tIndexlist* const indexlist,\t/**< Index list from which the new index shall be removed. */\n\t\t\t\t\t\t\t\t\tint removenumber\t\t\t/**< Number of constraint or bound to be removed. */\n\t\t\t\t\t\t\t\t\t);\n\n\t\t/** Swaps the indices of two constraints or bounds within the index set.\n\t\t *\t\\return SUCCESSFUL_RETURN \\n\n\t\t \t\t\tRET_SWAPINDEX_FAILED */\n\t\treturnValue swapIndex(\tIndexlist* const indexlist,\t/**< Index list in which the indices shold be swapped. */\n\t\t\t\t\t\t\t\tint number1,\t\t\t\t/**< Number of first constraint or bound. */\n\t\t\t\t\t\t\t\tint number2\t\t\t\t\t/**< Number of second constraint or bound. */\n\t\t\t\t\t\t\t\t);\n\n\n\t/*\n\t *\tPROTECTED MEMBER VARIABLES\n\t */\n\tprotected:\n\t\tSubjectToType type[NVMAX+NCMAX]; \t\t/**< Type of constraints/bounds. */\n\t\tSubjectToStatus status[NVMAX+NCMAX];\t/**< Status of constraints/bounds. */\n\n\t\tBooleanType noLower;\t\t\t\t \t/**< This flag indicates if there is no lower bound on any variable. */\n\t\tBooleanType noUpper;\t \t\t\t\t/**< This flag indicates if there is no upper bound on any variable. */\n\n\n\t/*\n\t *\tPRIVATE MEMBER VARIABLES\n\t */\n\tprivate:\n\t\tint size;\n};\n\n\n\n#include <SubjectTo.ipp>\n\n#endif\t/* QPOASES_SUBJECTTO_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/Types.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/Types.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2008\n *\n *\tDeclaration of all non-built-in types (except for classes).\n */\n\n\n#ifndef QPOASES_TYPES_HPP\n#define QPOASES_TYPES_HPP\n\n\n\n/** Define real_t for facilitating switching between double and float. */\n// typedef double real_t;\n\n\n/** Summarises all possible logical values. */\nenum BooleanType\n{\n\tBT_FALSE,\t\t\t\t\t/**< Logical value for \"false\". */\n\tBT_TRUE\t\t\t\t\t\t/**< Logical value for \"true\". */\n};\n\n\n/** Summarises all possible print levels. Print levels are used to describe\n *\tthe desired amount of output during runtime of qpOASES. */\nenum PrintLevel\n{\n\tPL_NONE,\t\t\t\t\t/**< No output. */\n\tPL_LOW,\t\t\t\t\t\t/**< Print error messages only. */\n\tPL_MEDIUM,\t\t\t\t\t/**< Print error and warning messages as well as concise info messages. */\n\tPL_HIGH\t\t\t\t\t\t/**< Print all messages with full details. */\n};\n\n\n/** Defines visibility status of a message. */\nenum VisibilityStatus\n{\n\tVS_VISIBLE,\t\t\t\t\t/**< Message visible. */\n\tVS_HIDDEN\t\t\t\t\t/**< Message not visible. */\n};\n\n\n/** Summarises all possible states of the (S)QProblem(B) object during the\nsolution process of a QP sequence. */\nenum QProblemStatus\n{\n\tQPS_NOTINITIALISED,\t\t\t/**< QProblem object is freshly instantiated or reset. */\n\tQPS_PREPARINGAUXILIARYQP,\t/**< An auxiliary problem is currently setup, either at the very beginning\n\t\t\t\t\t\t\t\t *   via an initial homotopy or after changing the QP matrices. */\n\tQPS_AUXILIARYQPSOLVED,\t\t/**< An auxilary problem was solved, either at the very beginning\n\t\t\t\t\t\t\t\t *   via an initial homotopy or after changing the QP matrices. */\n\tQPS_PERFORMINGHOMOTOPY,\t\t/**< A homotopy according to the main idea of the online active\n\t\t\t\t\t\t\t\t *   set strategy is performed. */\n\tQPS_HOMOTOPYQPSOLVED,\t\t/**< An intermediate QP along the homotopy path was solved. */\n\tQPS_SOLVED\t\t\t\t\t/**< The solution of the actual QP was found. */\n};\n\n\n/** Summarises all possible types of bounds and constraints. */\nenum SubjectToType\n{\n\tST_UNBOUNDED,\t\t\t\t/**< Bound/constraint is unbounded. */\n\tST_BOUNDED,\t\t\t\t\t/**< Bound/constraint is bounded but not fixed. */\n\tST_EQUALITY,\t\t\t\t/**< Bound/constraint is fixed (implicit equality bound/constraint). */\n\tST_UNKNOWN\t\t\t\t\t/**< Type of bound/constraint unknown. */\n};\n\n\n/** Summarises all possible states of bounds and constraints. */\nenum SubjectToStatus\n{\n\tST_INACTIVE,\t\t\t\t/**< Bound/constraint is inactive. */\n\tST_LOWER,\t\t\t\t\t/**< Bound/constraint is at its lower bound. */\n\tST_UPPER,\t\t\t\t\t/**< Bound/constraint is at its upper bound. */\n\tST_UNDEFINED\t\t\t\t/**< Status of bound/constraint undefined. */\n};\n\n\n/** Summarises all possible cycling states of bounds and constraints. */\nenum CyclingStatus\n{\n\tCYC_NOT_INVOLVED,\t\t\t/**< Bound/constraint is not involved in current cycling. */\n\tCYC_PREV_ADDED,\t\t\t\t/**< Bound/constraint has previously been added during the current cycling. */\n\tCYC_PREV_REMOVED\t\t\t/**< Bound/constraint has previously been removed during the current cycling. */\n};\n\n\n/** Summarises all possible types of the QP's Hessian matrix. */\nenum HessianType\n{\n\tHST_SEMIDEF,\t\t\t\t/**< Hessian is positive semi-definite. */\n\tHST_POSDEF_NULLSPACE,\t\t/**< Hessian is positive definite on null space of active bounds/constraints. */\n\tHST_POSDEF,\t\t\t\t\t/**< Hessian is (strictly) positive definite. */\n\tHST_IDENTITY\t\t\t\t/**< Hessian is identity matrix. */\n};\n\n\n\n#endif\t/* QPOASES_TYPES_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/INCLUDE/Utils.hpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file INCLUDE/Utils.hpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of global utility functions for working with qpOASES.\n */\n\n\n#ifndef QPOASES_UTILS_HPP\n#define QPOASES_UTILS_HPP\n\n\n#include <MessageHandling.hpp>\n\n\n#ifdef PC_DEBUG  /* Define print functions only for debugging! */\n\n/** Prints a vector.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst real_t* const v,\t/**< Vector to be printed. */\n\t\t\t\t\tint n\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\t);\n\n/** Prints a permuted vector.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst real_t* const v,\t\t/**< Vector to be printed. */\n\t\t\t\t\tint n,\t\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\tconst int* const V_idx\t\t/**< Pemutation vector. */\n\t\t\t\t\t);\n\n/** Prints a named vector.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst real_t* const v,\t/**< Vector to be printed. */\n\t\t\t\t\tint n,\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\tconst char* name\t\t/** Name of vector. */\n\t\t\t\t\t);\n\n/** Prints a matrix.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst real_t* const M,\t/**< Matrix to be printed. */\n\t\t\t\t\tint nrow,\t\t\t\t/**< Row number of matrix. */\n\t\t\t\t\tint ncol\t\t\t\t/**< Column number of matrix. */\n\t\t\t\t\t);\n\n/** Prints a permuted matrix.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst real_t* const M,\t\t/**< Matrix to be printed. */\n\t\t\t\t\tint nrow,\t\t\t\t\t/**< Row number of matrix. */\n\t\t\t\t\tint ncol\t,\t\t\t\t/**< Column number of matrix. */\n\t\t\t\t\tconst int* const ROW_idx,\t/**< Row pemutation vector. */\n\t\t\t\t\tconst int* const COL_idx\t/**< Column pemutation vector. */\n\t\t\t\t\t);\n\n/** Prints a named matrix.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst real_t* const M,\t/**< Matrix to be printed. */\n\t\t\t\t\tint nrow,\t\t\t\t/**< Row number of matrix. */\n\t\t\t\t\tint ncol,\t\t\t\t/**< Column number of matrix. */\n\t\t\t\t\tconst char* name\t\t/** Name of matrix. */\n\t\t\t\t\t);\n\n/** Prints an index array.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst int* const index,\t/**< Index array to be printed. */\n\t\t\t\t\tint n\t\t\t\t\t/**< Length of index array. */\n\t\t\t\t\t);\n\n/** Prints a named index array.\n * \\return SUCCESSFUL_RETURN */\nreturnValue print(\tconst int* const index,\t/**< Index array to be printed. */\n\t\t\t\t\tint n,\t\t\t\t\t/**< Length of index array. */\n\t\t\t\t\tconst char* name\t\t/**< Name of index array. */\n\t\t\t\t\t);\n\n\n/** Prints a string to desired output target (useful also for MATLAB output!).\n * \\return SUCCESSFUL_RETURN */\nreturnValue myPrintf(\tconst char* s\t/**< String to be written. */\n\t\t\t\t\t\t);\n\n\n/** Prints qpOASES copyright notice.\n * \\return SUCCESSFUL_RETURN */\nreturnValue printCopyrightNotice( );\n\n\n/** Reads a real_t matrix from file.\n * \\return SUCCESSFUL_RETURN \\n\n \t\t   RET_UNABLE_TO_OPEN_FILE \\n\n\t\t   RET_UNABLE_TO_READ_FILE */\nreturnValue readFromFile(\treal_t* data,\t\t\t\t/**< Matrix to be read from file. */\n\t\t\t\t\t\t\tint nrow,\t\t\t\t\t/**< Row number of matrix. */\n\t\t\t\t\t\t\tint ncol,\t\t\t\t\t/**< Column number of matrix. */\n\t\t\t\t\t\t\tconst char* datafilename\t/**< Data file name. */\n\t\t\t\t\t\t\t);\n\n/** Reads a real_t vector from file.\n * \\return SUCCESSFUL_RETURN \\n\n \t\t   RET_UNABLE_TO_OPEN_FILE \\n\n\t\t   RET_UNABLE_TO_READ_FILE */\nreturnValue readFromFile(\treal_t* data,\t\t\t\t/**< Vector to be read from file. */\n\t\t\t\t\t\t\tint n,\t\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\t\t\tconst char* datafilename\t/**< Data file name. */\n\t\t\t\t\t\t\t);\n\n/** Reads an integer (column) vector from file.\n * \\return SUCCESSFUL_RETURN \\n\n \t\t   RET_UNABLE_TO_OPEN_FILE \\n\n\t\t   RET_UNABLE_TO_READ_FILE */\nreturnValue readFromFile(\tint* data,\t\t\t\t\t/**< Vector to be read from file. */\n\t\t\t\t\t\t\tint n,\t\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\t\t\tconst char* datafilename\t/**< Data file name. */\n\t\t\t\t\t\t\t);\n\n\n/** Writes a real_t matrix into a file.\n * \\return SUCCESSFUL_RETURN \\n\n \t\t   RET_UNABLE_TO_OPEN_FILE  */\nreturnValue writeIntoFile(\tconst real_t* const data,\t/**< Matrix to be written into file. */\n\t\t\t\t\t\t\tint nrow,\t\t\t\t\t/**< Row number of matrix. */\n\t\t\t\t\t\t\tint ncol,\t\t\t\t\t/**< Column number of matrix. */\n\t\t\t\t\t\t\tconst char* datafilename,\t/**< Data file name. */\n\t\t\t\t\t\t\tBooleanType append\t\t\t/**< Indicates if data shall be appended if the file already exists (otherwise it is overwritten). */\n\t\t\t\t\t\t\t);\n\n/** Writes a real_t vector into a file.\n * \\return SUCCESSFUL_RETURN \\n\n \t\t   RET_UNABLE_TO_OPEN_FILE  */\nreturnValue writeIntoFile(\tconst real_t* const data,\t/**< Vector to be written into file. */\n\t\t\t\t\t\t\tint n,\t\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\t\t\tconst char* datafilename,\t/**< Data file name. */\n\t\t\t\t\t\t\tBooleanType append\t\t\t/**< Indicates if data shall be appended if the file already exists (otherwise it is overwritten). */\n\t\t\t\t\t\t\t);\n\n/** Writes an integer (column) vector into a file.\n * \\return SUCCESSFUL_RETURN \\n\n \t\t   RET_UNABLE_TO_OPEN_FILE */\nreturnValue writeIntoFile(\tconst int* const integer,\t/**< Integer vector to be written into file. */\n\t\t\t\t\t\t\tint n,\t\t\t\t\t\t/**< Length of vector. */\n\t\t\t\t\t\t\tconst char* datafilename,\t/**< Data file name. */\n\t\t\t\t\t\t\tBooleanType append\t\t\t/**< Indicates if integer shall be appended if the file already exists (otherwise it is overwritten). */\n\t\t\t\t\t\t\t);\n\n#endif  /* PC_DEBUG */\n\n\n/** Returns the current system time.\n * \\return current system time */\nreal_t getCPUtime( );\n\n\n/** Returns the Euclidean norm of a vector.\n * \\return 0: successful */\nreal_t getNorm(\tconst real_t* const v,\t/**< Vector. */\n\t\t\t\tint n\t\t\t\t\t/**< Vector's dimension. */\n\t\t\t\t);\n\n/** Returns the absolute value of a real_t.\n * \\return Absolute value of a real_t */\ninline real_t getAbs(\treal_t x\t\t/**< Input argument. */\n\t\t\t\t\t\t);\n\n\n\n#include <Utils.ipp>\n\n#endif\t/* QPOASES_UTILS_HPP */\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/LICENSE.txt",
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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN\nWRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY\nAND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU\nFOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR\nCONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE\nLIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING\nRENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A\nFAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF\nSUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH\nDAMAGES.\n\n\t\t     END OF TERMS AND CONDITIONS\n\f\n           How to Apply These Terms to Your New Libraries\n\n  If you develop a new library, and you want it to be of the greatest\npossible use to the public, we recommend making it free software that\neveryone can redistribute and change.  You can do so by permitting\nredistribution under these terms (or, alternatively, under the terms of the\nordinary General Public License).\n\n  To apply these terms, attach the following notices to the library.  It is\nsafest to attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least the\n\"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the library's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This library is free software; you can redistribute it and/or\n    modify it under the terms of the GNU Lesser General Public\n    License as published by the Free Software Foundation; either\n    version 2.1 of the License, or (at your option) any later version.\n\n    This library is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n    Lesser General Public License for more details.\n\n    You should have received a copy of the GNU Lesser General Public\n    License along with this library; if not, write to the Free Software\n    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n\nAlso add information on how to contact you by electronic and paper mail.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the library, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the\n  library `Frob' (a library for tweaking knobs) written by James Random Hacker.\n\n  <signature of Ty Coon>, 1 April 1990\n  Ty Coon, President of Vice\n\nThat's all there is to it!\n\n\n"
  },
  {
    "path": "phonelibs/qpoases/README.txt",
    "content": "##\n##\tqpOASES -- An Implementation of the Online Active Set Strategy.\n##\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n##\n##\tqpOASES is free software; you can redistribute it and/or\n##\tmodify it under the terms of the GNU Lesser General Public\n##\tLicense as published by the Free Software Foundation; either\n##\tversion 2.1 of the License, or (at your option) any later version.\n##\n##\tqpOASES is distributed in the hope that it will be useful,\n##\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n##\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n##\tLesser General Public License for more details.\n##\n##\tYou should have received a copy of the GNU Lesser General Public\n##\tLicense along with qpOASES; if not, write to the Free Software\n##\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n##\n\n\n\nINTRODUCTION\n=============\n\nqpOASES is an open-source C++ implementation of the recently proposed \nonline active set strategy (see [1], [2]), which was inspired by important \nobservations from the field of parametric quadratic programming. It has \nseveral theoretical features that make it particularly suited for model \npredictive control (MPC) applications.\n\nThe software package qpOASES implements these ideas and has already been \nsuccessfully used for closed-loop control of a real-world Diesel engine [3].\n\n\nReferences:\n\n[1] H.J. Ferreau. An Online Active Set Strategy for Fast Solution of \nParametric Quadratic Programs with Applications to Predictive Engine Control. \nDiplom thesis, University of Heidelberg, 2006.\n\n[2] H.J. Ferreau, H.G. Bock, M. Diehl. An online active set strategy to \novercome the limitations of explicit MPC. International Journal of Robust \nand Nonlinear Control, 18 (8), pp. 816-830, 2008.\n\n[3] H.J. Ferreau, P. Ortner, P. Langthaler, L. del Re, M. Diehl. Predictive \nControl of a Real-World Diesel Engine using an Extended Online Active Set \nStrategy. Annual Reviews in Control, 31 (2), pp. 293-301, 2007.\n\n\n\nGETTING STARTED\n================\n\n1. For installation, usage and additional information on this software package \n   see the qpOASES User's Manual located at ./DOC/manual.pdf!\n\n\n2. The file ./LICENSE.txt contains a copy of the GNU Lesser General Public \n   License. Please read it carefully before using qpOASES!\n\n\n3. The whole software package can be downloaded from \n\n        http://homes.esat.kuleuven.be/~optec/software/qpOASES/ \n\n   On this webpage you will also find a list of frequently asked questions.\n\n\n\nCONTACT THE AUTHORS\n====================\n\nIf you have got questions, remarks or comments on qpOASES \nplease contact the main author:\n\n        Hans Joachim Ferreau\n        Katholieke Universiteit Leuven\n        Department of Electrical Engineering (ESAT)\n        Kasteelpark Arenberg 10, bus 2446\n        B-3001 Leuven-Heverlee, Belgium\n\n        Phone: +32 16 32 03 63\n        E-mail: joachim.ferreau@esat.kuleuven.be\n                qpOASES@esat.kuleuven.be\n\nAlso bug reports and source code extensions are most welcome!\n\n\n\n##\n##\tend of file\n##\n"
  },
  {
    "path": "phonelibs/qpoases/SConscript",
    "content": "Import('env', 'interface_dir')\n\nqp_files = [\n    Glob(\"SRC/*.cpp\"),\n    Glob(\"SRC/EXTRAS/*.cpp\"),\n]\n\ncpp_path = [\n    \".\",\n    \"INCLUDE\",\n    \"INCLUDE/EXTRAS\",\n    \"SRC/\",\n    interface_dir,\n]\n\nenv.Library('qpoases', qp_files,  CPPPATH=cpp_path)\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Bounds.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Bounds.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the Bounds class designed to manage working sets of\n *\tbounds within a QProblem.\n */\n\n\n#include <Bounds.hpp>\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tB o u n d s\n */\nBounds::Bounds( ) :\tSubjectTo( ),\n\t\t\t\t\tnV( 0 ),\n\t\t\t\t\tnFV( 0 ),\n\t\t\t\t\tnBV( 0 ),\n\t\t\t\t\tnUV( 0 )\n{\n}\n\n\n/*\n *\tB o u n d s\n */\nBounds::Bounds( const Bounds& rhs ) :\tSubjectTo( rhs ),\n\t\t\t\t\t\t\t\t\t\tnV( rhs.nV ),\n\t\t\t\t\t\t\t\t\t\tnFV( rhs.nFV ),\n\t\t\t\t\t\t\t\t\t\tnBV( rhs.nBV ),\n\t\t\t\t\t\t\t\t\t\tnUV( rhs.nUV )\n{\n\tfree  = rhs.free;\n\tfixed = rhs.fixed;\n}\n\n\n/*\n *\t~ B o u n d s\n */\nBounds::~Bounds( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nBounds& Bounds::operator=( const Bounds& rhs )\n{\n\tif ( this != &rhs )\n\t{\n\t\tSubjectTo::operator=( rhs );\n\n\t\tnV  = rhs.nV;\n\t\tnFV = rhs.nFV;\n\t\tnBV = rhs.nBV;\n\t\tnUV = rhs.nUV;\n\n\t\tfree  = rhs.free;\n\t\tfixed = rhs.fixed;\n\t}\n\n\treturn *this;\n}\n\n\n/*\n *\ti n i t\n */\nreturnValue Bounds::init( int n )\n{\n\tnV = n;\n\tnFV = 0;\n\tnBV = 0;\n\tnUV = 0;\n\n\tfree.init( );\n\tfixed.init( );\n\n\treturn SubjectTo::init( n );\n}\n\n\n/*\n *\ts e t u p B o u n d\n */\nreturnValue Bounds::setupBound(\tint _number, SubjectToStatus _status\n\t\t\t\t\t\t\t\t)\n{\n\t/* consistency check */\n\tif ( ( _number < 0 ) || ( _number >= getNV( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t\n\t/* Add bound index to respective index list. */\n\tswitch ( _status )\n\t{\n\t\tcase ST_INACTIVE:\n\t\t\tif ( this->addIndex( this->getFree( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_BOUND_FAILED );\n\t\t\tbreak;\n\n\t\tcase ST_LOWER:\n\t\t\tif ( this->addIndex( this->getFixed( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_BOUND_FAILED );\n\t\t\tbreak;\n\n\t\tcase ST_UPPER:\n\t\t\tif ( this->addIndex( this->getFixed( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_BOUND_FAILED );\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A l l F r e e\n */\nreturnValue Bounds::setupAllFree( )\n{\n\tint i;\n\n\t/* 1) Place unbounded variables at the beginning of the index list of free variables. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( getType( i ) == ST_UNBOUNDED )\n\t\t{\n\t\t\tif ( setupBound( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_BOUND_FAILED );\n\t\t}\n\t}\n\n\t/* 2) Add remaining (i.e. bounded but possibly free) variables to the index list of free variables. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( getType( i ) == ST_BOUNDED )\n\t\t{\n\t\t\tif ( setupBound( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_BOUND_FAILED );\n\t\t}\n\t}\n\n\t/* 3) Place implicitly fixed variables at the end of the index list of free variables. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( getType( i ) == ST_EQUALITY )\n\t\t{\n\t\t\tif ( setupBound( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_BOUND_FAILED );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tm o v e F i x e d T o F r e e\n */\nreturnValue Bounds::moveFixedToFree( int _number )\n{\n\t/* consistency check */\n\tif ( ( _number < 0 ) || ( _number >= getNV( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\n\t/* Move index from indexlist of fixed variables to that of free ones. */\n\tif ( this->removeIndex( this->getFixed( ),_number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\tif ( this->addIndex( this->getFree( ),_number,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tm o v e F r e e T o F i x e d\n */\nreturnValue Bounds::moveFreeToFixed(\tint _number, SubjectToStatus _status\n\t\t\t\t\t\t\t\t\t\t)\n{\n\t/* consistency check */\n\tif ( ( _number < 0 ) || ( _number >= getNV( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\n\t/* Move index from indexlist of free variables to that of fixed ones. */\n\tif ( this->removeIndex( this->getFree( ),_number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\tif ( this->addIndex( this->getFixed( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts w a p F r e e\n */\nreturnValue Bounds::swapFree(\tint number1, int number2\n\t\t\t\t\t\t\t\t)\n{\n\t/* consistency check */\n\tif ( ( number1 < 0 ) || ( number1 >= getNV( ) ) || ( number2 < 0 ) || ( number2 >= getNV( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\n\t/* Swap index within indexlist of free variables. */\n\treturn this->swapIndex( this->getFree( ),number1,number2 );\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Bounds.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Bounds.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of inlined member functions of the Bounds class designed \n *\tto manage working sets of bounds within a QProblem.\n */\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n/*\n *\tg e t N V\n */\ninline int Bounds::getNV( ) const\n{\n \treturn nV;\n}\n\n\n/*\n *\tg e t N F X\n */\ninline int Bounds::getNFV( ) const\n{\n \treturn nFV;\n}\n\n\n/*\n *\tg e t N B V\n */\ninline int Bounds::getNBV( ) const\n{\n \treturn nBV;\n}\n \n\n/*\n *\tg e t N U V\n */\ninline int Bounds::getNUV( ) const\n{\n\treturn nUV;\n}\n\n\n\n/*\n *\ts e t N F X\n */\ninline returnValue Bounds::setNFV( int n )\n{\n \tnFV = n;\n\treturn SUCCESSFUL_RETURN;\t\n}\n \n \n/*\n *\ts e t N B V\n */\ninline returnValue Bounds::setNBV( int n )\n{\n \tnBV = n;\n\treturn SUCCESSFUL_RETURN;\n}\n \n\n/*\n *\ts e t N U V\n */\ninline returnValue Bounds::setNUV( int n )\n{\n\tnUV = n;\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t N F R\n */\ninline int Bounds::getNFR( )\n{\n \treturn free.getLength( );\n}\n\n\n/*\n *\tg e t N F X\n */\ninline int Bounds::getNFX( )\n{\n \treturn fixed.getLength( );\n}\n\n\n/*\n *\tg e t F r e e\n */\ninline Indexlist* Bounds::getFree( )\n{\n\treturn &free;\n}\n\n\n/*\n *\tg e t F i x e d\n */\ninline Indexlist* Bounds::getFixed( )\n{\n\treturn &fixed;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Constraints.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Constraints.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the Constraints class designed to manage working sets of\n *\tconstraints within a QProblem.\n */\n\n\n#include <Constraints.hpp>\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tC o n s t r a i n t s\n */\nConstraints::Constraints( ) :\tSubjectTo( ),\n\t\t\t\t\t\t\t\tnC( 0 ),\n\t\t\t\t\t\t\t\tnEC( 0 ),\n\t\t\t\t\t\t\t\tnIC( 0 ),\n\t\t\t\t\t\t\t\tnUC( 0 )\n{\n}\n\n\n/*\n *\tC o n s t r a i n t s\n */\nConstraints::Constraints( const Constraints& rhs ) :\tSubjectTo( rhs ),\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tnC( rhs.nC ),\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tnEC( rhs.nEC ),\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tnIC( rhs.nIC ),\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tnUC( rhs.nUC )\n{\n\tactive =   rhs.active;\n\tinactive = rhs.inactive;\n}\n\n\n/*\n *\t~ C o n s t r a i n t s\n */\nConstraints::~Constraints( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nConstraints& Constraints::operator=( const Constraints& rhs )\n{\n\tif ( this != &rhs )\n\t{\n\t\tSubjectTo::operator=( rhs );\n\n\t\tnC  = rhs.nC;\n\t\tnEC = rhs.nEC;\n\t\tnIC = rhs.nIC;\n\t\tnUC = rhs.nUC;\n\n\t\tactive =   rhs.active;\n\t\tinactive = rhs.inactive;\n\t}\n\n\treturn *this;\n}\n\n\n/*\n *\ti n i t\n */\nreturnValue Constraints::init( int n )\n{\n\tnC = n;\n\tnEC = 0;\n\tnIC = 0;\n\tnUC = 0;\n\n\tactive.init( );\n\tinactive.init( );\n\n\treturn SubjectTo::init( n );\n}\n\n\n/*\n *\ts e t u p C o n s t r a i n t\n */\nreturnValue Constraints::setupConstraint(\tint _number, SubjectToStatus _status\n\t\t\t\t\t\t\t\t\t\t\t)\n{\n\t/* consistency check */\n\tif ( ( _number < 0 ) || ( _number >= getNC( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t\n\t/* Add constraint index to respective index list. */\n\tswitch ( _status )\n\t{\n\t\tcase ST_INACTIVE:\n\t\t\tif ( this->addIndex( this->getInactive( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t\tbreak;\n\n\t\tcase ST_LOWER:\n\t\t\tif ( this->addIndex( this->getActive( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t\tbreak;\n\n\t\tcase ST_UPPER:\n\t\t\tif ( this->addIndex( this->getActive( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A l l I n a c t i v e\n */\nreturnValue Constraints::setupAllInactive( )\n{\n\tint i;\n\n\n\t/* 1) Place unbounded constraints at the beginning of the index list of inactive constraints. */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( getType( i ) == ST_UNBOUNDED )\n\t\t{\n\t\t\tif ( setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t}\n\t}\n\n\t/* 2) Add remaining (i.e. \"real\" inequality) constraints to the index list of inactive constraints. */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( getType( i ) == ST_BOUNDED )\n\t\t{\n\t\t\tif ( setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t}\n\t}\n\n\t/* 3) Place implicit equality constraints at the end of the index list of inactive constraints. */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( getType( i ) == ST_EQUALITY )\n\t\t{\n\t\t\tif ( setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t}\n\t}\n\n\t/* 4) Moreover, add all constraints of unknown type. */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( getType( i ) == ST_UNKNOWN )\n\t\t{\n\t\t\tif ( setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_CONSTRAINT_FAILED );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tm o v e A c t i v e T o I n a c t i v e\n */\nreturnValue Constraints::moveActiveToInactive( int _number )\n{\n\t/* consistency check */\n\tif ( ( _number < 0 ) || ( _number >= getNC( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\n\t/* Move index from indexlist of active constraints to that of inactive ones. */\n\tif ( this->removeIndex( this->getActive( ),_number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\tif ( this->addIndex( this->getInactive( ),_number,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tm o v e I n a c t i v e T o A c t i v e\n */\nreturnValue Constraints::moveInactiveToActive(\tint _number, SubjectToStatus _status\n\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\t/* consistency check */\n\tif ( ( _number < 0 ) || ( _number >= getNC( ) ) )\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\n\t/* Move index from indexlist of inactive constraints to that of active ones. */\n\tif ( this->removeIndex( this->getInactive( ),_number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\tif ( this->addIndex( this->getActive( ),_number,_status ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_MOVING_BOUND_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Constraints.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Constraints.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tDeclaration of inlined member functions of the Constraints class designed \n *\tto manage working sets of constraints within a QProblem.\n */\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n/*\n *\tg e t N C\n */\ninline int Constraints::getNC( ) const\n{\n \treturn nC;\n}\n \n\n/*\n *\tg e t N E C\n */\ninline int Constraints::getNEC( ) const\n{\n \treturn nEC;\n}\n \n\n/*\n *\tg e t N I C\n */\ninline int Constraints::getNIC( ) const\n{\n \treturn nIC;\n}\n \n\n/*\n *\tg e t N U C\n */\ninline int Constraints::getNUC( ) const\n{\n \treturn nUC;\n}\n\n\n/*\n *\ts e t N E C\n */\ninline returnValue Constraints::setNEC( int n )\n{\n \tnEC = n;\n\treturn SUCCESSFUL_RETURN;\n}\n \n\n/*\n *\ts e t N I C\n */\ninline returnValue Constraints::setNIC( int n )\n{\n \tnIC = n;\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t N U C\n */\ninline returnValue Constraints::setNUC( int n )\n{\n \tnUC = n;\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t N A C\n */\ninline int Constraints::getNAC( )\n{\n \treturn active.getLength( );\n}\n\n\n/*\n *\tg e t N I A C\n */\ninline int Constraints::getNIAC( )\n{\n \treturn inactive.getLength( );\n}\n\n\n/*\n *\tg e t A c t i v e\n */\ninline Indexlist* Constraints::getActive( )\n{\n\treturn &active;\n}\n\n\n/*\n *\tg e t I n a c t i v e\n */\ninline Indexlist* Constraints::getInactive( )\n{\n\treturn &inactive;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/CyclingManager.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/CyclingManager.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the CyclingManager class designed to detect\n *\tand handle possible cycling during QP iterations.\n *\n */\n\n\n#include <CyclingManager.hpp>\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tC y c l i n g M a n a g e r\n */\nCyclingManager::CyclingManager( ) :\tnV( 0 ),\n\t\t\t\t\t\t\t\t\tnC( 0 )\n{\n\tcyclingDetected = BT_FALSE;\n}\n\n\n/*\n *\tC y c l i n g M a n a g e r\n */\nCyclingManager::CyclingManager( const CyclingManager& rhs ) :\tnV( rhs.nV ),\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tnC( rhs.nC ),\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tcyclingDetected( rhs.cyclingDetected )\n{\n\tint i;\n\n\tfor( i=0; i<nV+nC; ++i )\n\t\tstatus[i] = rhs.status[i];\n}\n\n\n/*\n *\t~ C y c l i n g M a n a g e r\n */\nCyclingManager::~CyclingManager( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nCyclingManager& CyclingManager::operator=( const CyclingManager& rhs )\n{\n\tint i;\n\n\tif ( this != &rhs )\n\t{\n\t\tnV = rhs.nV;\n\t\tnC = rhs.nC;\n\n\t\tfor( i=0; i<nV+nC; ++i )\n\t\t\tstatus[i] = rhs.status[i];\n\n\t\tcyclingDetected = rhs.cyclingDetected;\n\t}\n\n\treturn *this;\n}\n\n\n\n/*\n *\ti n i t\n */\nreturnValue CyclingManager::init( int _nV, int _nC )\n{\n\tnV = _nV;\n\tnC = _nC;\n\n\tcyclingDetected = BT_FALSE;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\ts e t C y c l i n g S t a t u s\n */\nreturnValue CyclingManager::setCyclingStatus(\tint number,\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType isBound, CyclingStatus _status\n\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tif ( isBound == BT_TRUE )\n\t{\n\t\t/* Set cycling status of a bound. */\n\t\tif ( ( number >= 0 ) && ( number < nV ) )\n\t\t{\n\t\t\tstatus[number] = _status;\n\t\t\treturn SUCCESSFUL_RETURN;\n\t\t}\n\t\telse\n\t\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t}\n\telse\n\t{\n\t\t/* Set cycling status of a constraint. */\n\t\tif ( ( number >= 0 ) && ( number < nC ) )\n\t\t{\n\t\t\tstatus[nV+number] = _status;\n\t\t\treturn SUCCESSFUL_RETURN;\n\t\t}\n\t\telse\n\t\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t}\n}\n\n\n/*\n *\tg e t C y c l i n g S t a t u s\n */\nCyclingStatus CyclingManager::getCyclingStatus( int number, BooleanType isBound ) const\n{\n\tif ( isBound == BT_TRUE )\n\t{\n\t\t/* Return cycling status of a bound. */\n\t\tif ( ( number >= 0 ) && ( number < nV ) )\n\t\t\treturn status[number];\n\t}\n\telse\n\t{\n\t\t/* Return cycling status of a constraint. */\n\t\tif ( ( number >= 0 ) && ( number < nC ) )\n\t\t\treturn status[nV+number];\n\t}\n\n\treturn CYC_NOT_INVOLVED;\n}\n\n\n/*\n *\tc l e a r C y c l i n g D a t a\n */\nreturnValue CyclingManager::clearCyclingData( )\n{\n\tint i;\n\n\t/* Reset all status values ... */\n\tfor( i=0; i<nV+nC; ++i )\n\t\tstatus[i] = CYC_NOT_INVOLVED;\n\n\t/* ... and the main cycling flag. */\n\tcyclingDetected = BT_FALSE;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/CyclingManager.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/CyclingManager.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of inlined member functions of the CyclingManager class \n *\tdesigned to detect and handle possible cycling during QP iterations.\n *\t\n */\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n/*\n *\ti s C y c l i n g D e t e c t e d\n */\ninline BooleanType CyclingManager::isCyclingDetected( ) const\n{\n\treturn cyclingDetected;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/EXTRAS/SolutionAnalysis.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/EXTRAS/SolutionAnalysis.cpp\n *\t\\author Milan Vukov, Boris Houska, Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2012\n *\n *\tSolution analysis class, based on a class in the standard version of the qpOASES\n */\n\n#include <EXTRAS/SolutionAnalysis.hpp>\n\n/*\n *\tS o l u t i o n A n a l y s i s\n */\nSolutionAnalysis::SolutionAnalysis( )\n{\n\t\n}\n\n/*\n *\tS o l u t i o n A n a l y s i s\n */\nSolutionAnalysis::SolutionAnalysis( const SolutionAnalysis& rhs )\n{\n\t\n}\n\n/*\n *\t~ S o l u t i o n A n a l y s i s\n */\nSolutionAnalysis::~SolutionAnalysis( )\n{\n\t\n}\n\n/*\n *\to p e r a t o r =\n */\nSolutionAnalysis& SolutionAnalysis::operator=( const SolutionAnalysis& rhs )\n{\n\tif ( this != &rhs )\n\t{\n\t\t\n\t}\n\t\n\treturn *this;\n}\n\n/*\n * g e t H e s s i a n I n v e r s e\n */\nreturnValue SolutionAnalysis::getHessianInverse( QProblem* qp, real_t* hessianInverse )\n{\n\treturnValue returnvalue; /* the return value */\n\tBooleanType Delta_bC_isZero = BT_FALSE; /* (just use FALSE here) */\n\tBooleanType Delta_bB_isZero = BT_FALSE; /* (just use FALSE here) */\n\t\n\tregister int run1, run2, run3;\n\t\n\tregister int nFR, nFX;\n\t\n\t/* Ask for the number of free and fixed variables, assumes that active set\n\t * is constant for the covariance evaluation */\n\tnFR = qp->getNFR( );\n\tnFX = qp->getNFX( );\n\t\n\t/* Ask for the corresponding index arrays: */\n\tif ( qp->bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\tif ( qp->bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\tif ( qp->constraints.getActive( )->getNumberArray( AC_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\t/* Initialization: */\n\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\tdelta_g_cov[ run1 ] = 0.0;\n\t\n\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\tdelta_lb_cov[ run1 ] = 0.0;\n\t\n\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\tdelta_ub_cov[ run1 ] = 0.0;\n\t\n\tfor( run1 = 0; run1 < NCMAX; run1++ )\n\t\tdelta_lbA_cov[ run1 ] = 0.0;\n\t\n\tfor( run1 = 0; run1 < NCMAX; run1++ )\n\t\tdelta_ubA_cov[ run1 ] = 0.0;\n\t\n\t/* The following loop solves the following:\n\t *\n\t * KKT * x =\n\t *   [delta_g_cov', delta_lbA_cov', delta_ubA_cov', delta_lb_cov', delta_ub_cov]'\n\t *\n\t * for the first NVMAX (negative) elementary vectors in order to get\n\t * transposed inverse of the Hessian. Assuming that the Hessian is\n\t * symmetric, the function will return transposed inverse, instead of the\n\t * true inverse.\n\t *\n\t * Note, that we use negative elementary vectors due because internal\n\t * implementation of the function hotstart_determineStepDirection requires\n\t * so.\n\t *\n\t * */\n\t\n\tfor( run3 = 0; run3 < NVMAX; run3++ )\n\t{\n\t\t/* Line wise loading of the corresponding (negative) elementary vector: */\n\t\tdelta_g_cov[ run3 ] = -1.0;\n\t\t\n\t\t/* Evaluation of the step: */\n\t\treturnvalue = qp->hotstart_determineStepDirection(\n\t\t\tFR_idx, FX_idx, AC_idx,\n\t\t\tdelta_g_cov, delta_lbA_cov, delta_ubA_cov, delta_lb_cov, delta_ub_cov,\n\t\t\tDelta_bC_isZero, Delta_bB_isZero,\n\t\t\tdelta_xFX, delta_xFR, delta_yAC, delta_yFX\n\t\t\t);\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\treturn returnvalue;\n\t\t}\n\t\t\n\t\t/* Line wise storage of the QP reaction: */\n\t\tfor( run1 = 0; run1 < nFR; run1++ )\n\t\t{\n\t\t\trun2 = FR_idx[ run1 ];\n\t\t\t\n\t\t\thessianInverse[run3 * NVMAX + run2] = delta_xFR[ run1 ];\n\t\t} \n\t\t\n\t\tfor( run1 = 0; run1 < nFX; run1++ )\n\t\t{ \n\t\t\trun2 = FX_idx[ run1 ];\n\t\t\t\n\t\t\thessianInverse[run3 * NVMAX + run2] = delta_xFX[ run1 ];\n\t\t}\n\t\t\n\t\t/* Prepare for the next iteration */\n\t\tdelta_g_cov[ run3 ] = 0.0;\n\t}\n\t\n\t// TODO: Perform the transpose of the inverse of the Hessian matrix\n\t\n\treturn SUCCESSFUL_RETURN; \n}\n\n/*\n * g e t H e s s i a n I n v e r s e\n */\nreturnValue SolutionAnalysis::getHessianInverse( QProblemB* qp, real_t* hessianInverse )\n{\n\treturnValue returnvalue; /* the return value */\n\tBooleanType Delta_bB_isZero = BT_FALSE; /* (just use FALSE here) */\n\t\n\tregister int run1, run2, run3;\n\t\n\tregister int nFR, nFX;\n\t\n\t/* Ask for the number of free and fixed variables, assumes that active set\n\t * is constant for the covariance evaluation */\n\tnFR = qp->getNFR( );\n\tnFX = qp->getNFX( );\n\t\n\t/* Ask for the corresponding index arrays: */\n\tif ( qp->bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\tif ( qp->bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\t/* Initialization: */\n\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\tdelta_g_cov[ run1 ] = 0.0;\n\t\n\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\tdelta_lb_cov[ run1 ] = 0.0;\n\t\n\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\tdelta_ub_cov[ run1 ] = 0.0;\n\t\n\t/* The following loop solves the following:\n\t *\n\t * KKT * x =\n\t *   [delta_g_cov', delta_lb_cov', delta_ub_cov']'\n\t *\n\t * for the first NVMAX (negative) elementary vectors in order to get\n\t * transposed inverse of the Hessian. Assuming that the Hessian is\n\t * symmetric, the function will return transposed inverse, instead of the\n\t * true inverse.\n\t *\n\t * Note, that we use negative elementary vectors due because internal\n\t * implementation of the function hotstart_determineStepDirection requires\n\t * so.\n\t *\n\t * */\n\t\n\tfor( run3 = 0; run3 < NVMAX; run3++ )\n\t{\n\t\t/* Line wise loading of the corresponding (negative) elementary vector: */\n\t\tdelta_g_cov[ run3 ] = -1.0;\n\t\t\n\t\t/* Evaluation of the step: */\n\t\treturnvalue = qp->hotstart_determineStepDirection(\n\t\t\tFR_idx, FX_idx,\n\t\t\tdelta_g_cov, delta_lb_cov, delta_ub_cov,\n\t\t\tDelta_bB_isZero,\n\t\t\tdelta_xFX, delta_xFR, delta_yFX\n\t\t\t);\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\treturn returnvalue;\n\t\t}\n\t\t\t\t\n\t\t/* Line wise storage of the QP reaction: */\n\t\tfor( run1 = 0; run1 < nFR; run1++ )\n\t\t{\n\t\t\trun2 = FR_idx[ run1 ];\n\t\t\t\n\t\t\thessianInverse[run3 * NVMAX + run2] = delta_xFR[ run1 ];\n\t\t} \n\t\t\n\t\tfor( run1 = 0; run1 < nFX; run1++ )\n\t\t{ \n\t\t\trun2 = FX_idx[ run1 ];\n\t\t\t\n\t\t\thessianInverse[run3 * NVMAX + run2] = delta_xFX[ run1 ];\n\t\t}\n\t\t\n\t\t/* Prepare for the next iteration */\n\t\tdelta_g_cov[ run3 ] = 0.0;\n\t}\n\t\n\t// TODO: Perform the transpose of the inverse of the Hessian matrix\n\t\n\treturn SUCCESSFUL_RETURN; \n}\n\n/*\n * g e t V a r i a n c e C o v a r i a n c e\n */\n\n#if QPOASES_USE_OLD_VERSION\n\nreturnValue SolutionAnalysis::getVarianceCovariance( QProblem* qp, real_t* g_b_bA_VAR, real_t* Primal_Dual_VAR )\n{\n\tint run1, run2, run3; /* simple run variables (for loops). */\n\t\n\treturnValue returnvalue; /* the return value */\n\tBooleanType Delta_bC_isZero = BT_FALSE; /* (just use FALSE here) */\n\tBooleanType Delta_bB_isZero = BT_FALSE; /* (just use FALSE here) */\n\t\n\t/* ASK FOR THE NUMBER OF FREE AND FIXED VARIABLES:\n\t * (ASSUMES THAT ACTIVE SET IS CONSTANT FOR THE\n\t *  VARIANCE-COVARIANCE EVALUATION)\n\t * ----------------------------------------------- */\n\tint nFR, nFX, nAC;\n\t\n\tnFR = qp->getNFR( );\n\tnFX = qp->getNFX( );\n\tnAC = qp->getNAC( );\n\t\n\tif ( qp->bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\tif ( qp->bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\tif ( qp->constraints.getActive( )->getNumberArray( AC_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\t\n\t/* SOME INITIALIZATIONS:\n\t * --------------------- */\n\tfor( run1 = 0; run1 < KKT_DIM * KKT_DIM; run1++ )\n\t{\n\t\tK [run1] = 0.0;\n\t\tPrimal_Dual_VAR[run1] = 0.0;\n\t}\n\t\n\t/* ================================================================= */\n\t\n\t/* FIRST MATRIX MULTIPLICATION (OBTAINS THE INTERMEDIATE RESULT\n\t *  K := [ (\"ACTIVE\" KKT-MATRIX OF THE QP)^(-1) * g_b_bA_VAR ]^T )\n\t * THE EVALUATION OF THE INVERSE OF THE KKT-MATRIX OF THE QP\n\t * WITH RESPECT TO THE CURRENT ACTIVE SET\n\t * USES THE EXISTING CHOLESKY AND TQ-DECOMPOSITIONS. FOR DETAILS\n\t * cf. THE (protected) FUNCTION determineStepDirection. */\n\t\n\tfor( run3 = 0; run3 < KKT_DIM; run3++ )\n\t{\n\t\t\n\t\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\t{\n\t\t\tdelta_g_cov [run1] = g_b_bA_VAR[run3*KKT_DIM+run1];\n\t\t\tdelta_lb_cov [run1] = g_b_bA_VAR[run3*KKT_DIM+NVMAX+run1]; /*  LINE-WISE LOADING OF THE INPUT */\n\t\t\tdelta_ub_cov [run1] = g_b_bA_VAR[run3*KKT_DIM+NVMAX+run1]; /*  VARIANCE-COVARIANCE            */\n\t\t}\n\t\tfor( run1 = 0; run1 < NCMAX; run1++ )\n\t\t{\n\t\t\tdelta_lbA_cov [run1] = g_b_bA_VAR[run3*KKT_DIM+2*NVMAX+run1];\n\t\t\tdelta_ubA_cov [run1] = g_b_bA_VAR[run3*KKT_DIM+2*NVMAX+run1];\n\t\t}\n\t\t\n\t\t/* EVALUATION OF THE STEP:\n\t\t * ------------------------------------------------------------------------------ */\n\t\t\n\t\treturnvalue = qp->hotstart_determineStepDirection(\n\t\t\tFR_idx, FX_idx, AC_idx,\n\t\t\tdelta_g_cov, delta_lbA_cov, delta_ubA_cov, delta_lb_cov, delta_ub_cov,\n\t\t\tDelta_bC_isZero, Delta_bB_isZero, delta_xFX,delta_xFR,\n\t\t\tdelta_yAC,delta_yFX );\n\t\t\n\t\t/* ------------------------------------------------------------------------------ */\n\t\t\n\t\t/* STOP THE ALGORITHM IN THE CASE OF NO SUCCESFUL RETURN:\n\t\t * ------------------------------------------------------ */\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\treturn returnvalue;\n\t\t}\n\t\t\n\t\t/*  LINE WISE                  */\n\t\t/*  STORAGE OF THE QP-REACTION */\n\t\t/*  (uses the index list)      */\n\t\t\n\t\tfor( run1=0; run1<nFR; run1++ )\n\t\t{\n\t\t\trun2 = FR_idx[run1];\n\t\t\tK[run3*KKT_DIM+run2] = delta_xFR[run1];\n\t\t} \n\t\tfor( run1=0; run1<nFX; run1++ )\n\t\t{ \n\t\t\trun2 = FX_idx[run1]; \n\t\t\tK[run3*KKT_DIM+run2] = delta_xFX[run1];\n\t\t\tK[run3*KKT_DIM+NVMAX+run2] = delta_yFX[run1];\n\t\t}\n\t\tfor( run1=0; run1<nAC; run1++ )\n\t\t{\n\t\t\trun2 = AC_idx[run1];\n\t\t\tK[run3*KKT_DIM+2*NVMAX+run2] = delta_yAC[run1];\n\t\t}\n\t}\n\t\n\t/* ================================================================= */\n\t\n\t/* SECOND MATRIX MULTIPLICATION (OBTAINS THE FINAL RESULT\n\t * Primal_Dual_VAR := (\"ACTIVE\" KKT-MATRIX OF THE QP)^(-1) * K )\n\t * THE APPLICATION OF THE KKT-INVERSE IS AGAIN REALIZED\n\t * BY USING THE PROTECTED FUNCTION\n\t * determineStepDirection */\n\t\n\tfor( run3 = 0; run3 < KKT_DIM; run3++ )\n\t{\n\t\t\n\t\tfor( run1 = 0; run1 < NVMAX; run1++ )\n\t\t{\n\t\t\tdelta_g_cov [run1] = K[run3+ run1*KKT_DIM];\n\t\t\tdelta_lb_cov [run1] = K[run3+(NVMAX+run1)*KKT_DIM]; /*  ROW WISE LOADING OF THE */\n\t\t\tdelta_ub_cov [run1] = K[run3+(NVMAX+run1)*KKT_DIM]; /*  INTERMEDIATE RESULT K   */\n\t\t}\n\t\tfor( run1 = 0; run1 < NCMAX; run1++ )\n\t\t{\n\t\t\tdelta_lbA_cov [run1] = K[run3+(2*NVMAX+run1)*KKT_DIM];\n\t\t\tdelta_ubA_cov [run1] = K[run3+(2*NVMAX+run1)*KKT_DIM];\n\t\t}\n\t\t\n\t\t/* EVALUATION OF THE STEP:\n\t\t * ------------------------------------------------------------------------------ */\n\t\t\n\t\treturnvalue = qp->hotstart_determineStepDirection(\n\t\t\tFR_idx, FX_idx, AC_idx,\n\t\t\tdelta_g_cov, delta_lbA_cov, delta_ubA_cov, delta_lb_cov, delta_ub_cov,\n\t\t\tDelta_bC_isZero, Delta_bB_isZero, delta_xFX,delta_xFR,\n\t\t\tdelta_yAC,delta_yFX );\n\t\t\n\t\t/* ------------------------------------------------------------------------------ */\n\t\t\n\t\t/* STOP THE ALGORITHM IN THE CASE OF NO SUCCESFUL RETURN:\n\t\t * ------------------------------------------------------ */\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\treturn returnvalue;\n\t\t}\n\t\t\n\t\t/*  ROW-WISE STORAGE */\n\t\t/*  OF THE RESULT.   */\n\t\t\n\t\tfor( run1=0; run1<nFR; run1++ )\n\t\t{\n\t\t\trun2 = FR_idx[run1];\n\t\t\tPrimal_Dual_VAR[run3+run2*KKT_DIM] = delta_xFR[run1];\n\t\t}\n\t\tfor( run1=0; run1<nFX; run1++ )\n\t\t{ \n\t\t\trun2 = FX_idx[run1]; \n\t\t\tPrimal_Dual_VAR[run3+run2*KKT_DIM ] = delta_xFX[run1];\n\t\t\tPrimal_Dual_VAR[run3+(NVMAX+run2)*KKT_DIM] = delta_yFX[run1];\n\t\t}\n\t\tfor( run1=0; run1<nAC; run1++ )\n\t\t{\n\t\t\trun2 = AC_idx[run1];\n\t\t\tPrimal_Dual_VAR[run3+(2*NVMAX+run2)*KKT_DIM] = delta_yAC[run1];\n\t\t}\n\t}\n\t\n\treturn SUCCESSFUL_RETURN;\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Indexlist.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Indexlist.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the Indexlist class designed to manage index lists of\n *\tconstraints and bounds within a QProblem_SubjectTo.\n */\n\n\n#include <Indexlist.hpp>\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tI n d e x l i s t\n */\nIndexlist::Indexlist( ) :\tlength( 0 ),\n\t\t\t\t\t\t\tfirst( -1 ),\n\t\t\t\t\t\t\tlast( -1 ),\n\t\t\t\t\t\t\tlastusedindex( -1 ),\n\t\t\t\t\t\t\tphysicallength( INDEXLISTFACTOR*(NVMAX+NCMAX) )\n{\n\tint i;\n\n\tfor( i=0; i<physicallength; ++i )\n\t{\n\t\tnumber[i] = -1;\n\t\tnext[i] = -1;\n\t\tprevious[i] = -1;\n\t}\n}\n\n\n/*\n *\tI n d e x l i s t\n */\nIndexlist::Indexlist( const Indexlist& rhs ) :\tlength( rhs.length ),\n\t\t\t\t\t\t\t\t\t\t\t\tfirst( rhs.first ),\n\t\t\t\t\t\t\t\t\t\t\t\tlast( rhs.last ),\n\t\t\t\t\t\t\t\t\t\t\t\tlastusedindex( rhs.lastusedindex ),\n\t\t\t\t\t\t\t\t\t\t\t\tphysicallength( rhs.physicallength )\n{\n\tint i;\n\n\tfor( i=0; i<physicallength; ++i )\n\t{\n\t\tnumber[i] = rhs.number[i];\n\t\tnext[i] = rhs.next[i];\n\t\tprevious[i] = rhs.previous[i];\n\t}\n}\n\n\n/*\n *\t~ I n d e x l i s t\n */\nIndexlist::~Indexlist( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nIndexlist& Indexlist::operator=( const Indexlist& rhs )\n{\n\tint i;\n\n\tif ( this != &rhs )\n\t{\n\t\tlength = rhs.length;\n\t\tfirst = rhs.first;\n\t\tlast = rhs.last;\n\t\tlastusedindex = rhs.lastusedindex;\n\t\tphysicallength = rhs.physicallength;\n\n\t\tfor( i=0; i<physicallength; ++i )\n\t\t{\n\t\t\tnumber[i] = rhs.number[i];\n\t\t\tnext[i] = rhs.next[i];\n\t\t\tprevious[i] = rhs.previous[i];\n\t\t}\n\t}\n\n\treturn *this;\n}\n\n\n/*\n *\ti n i t\n */\nreturnValue Indexlist::init( )\n{\n\tint i;\n\n\tlength = 0;\n\tfirst = -1;\n\tlast = -1;\n\tlastusedindex = -1;\n\tphysicallength = INDEXLISTFACTOR*(NVMAX+NCMAX);\n\n\tfor( i=0; i<physicallength; ++i )\n\t{\n\t\tnumber[i] = -1;\n\t\tnext[i] = -1;\n\t\tprevious[i] = -1;\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t N u m b e r A r r a y\n */\nreturnValue Indexlist::getNumberArray( int* const numberarray ) const\n{\n\tint i;\n\tint n = first;\n\n\t/* Run trough indexlist and store numbers in numberarray. */\n\tfor( i=0; i<length; ++i )\n\t{\n\t\tif ( ( n >= 0 ) && ( number[n] >= 0 ) )\n\t\t\tnumberarray[i] = number[n];\n\t\telse\n\t\t\treturn THROWERROR( RET_INDEXLIST_CORRUPTED );\n\n\t\tn = next[n];\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t I n d e x\n */\nint Indexlist::getIndex( int givennumber ) const\n{\n\tint i;\n\tint n = first;\n\tint index = -1;\t/* return -1 by default */\n\n\t/* Run trough indexlist until number is found, if so return it index. */\n\tfor ( i=0; i<length; ++i )\n\t{\n\t\tif ( number[n] == givennumber )\n\t\t{\n\t\t\tindex = i;\n\t\t\tbreak;\n\t\t}\n\n\t\tn = next[n];\n\t}\n\n\treturn index;\n}\n\n\n/*\n *\tg e t P h y s i c a l I n d e x\n */\nint Indexlist::getPhysicalIndex( int givennumber ) const\n{\n\tint i;\n\tint n = first;\n\tint index = -1;\t/* return -1 by default */\n\n\t/* Run trough indexlist until number is found, if so return it physicalindex. */\n\tfor ( i=0; i<length; ++i )\n\t{\n\t\tif ( number[n] == givennumber )\n\t\t{\n\t\t\tindex = n;\n\t\t\tbreak;\n\t\t}\n\n\t\tn = next[n];\n\t}\n\n\treturn index;\n}\n\n\n/*\n *\ta d d N u m b e r\n */\nreturnValue Indexlist::addNumber( int addnumber )\n{\n\tint i;\n\n\tif ( lastusedindex+1 < physicallength )\n\t{\n\t\t/* If there is enough storage, add number to indexlist. */\n\t\t++lastusedindex;\n\t\tnumber[lastusedindex] = addnumber;\n\t\tnext[lastusedindex] = 0;\n\n\t\tif ( length == 0 )\n\t\t{\n\t\t\tfirst = lastusedindex;\n\t\t\tprevious[lastusedindex] = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tnext[last] = lastusedindex;\n\t\t\tprevious[lastusedindex] = last;\n\t\t}\n\n\t\tlast = lastusedindex;\n\t\t++length;\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\t/* Rearrangement of index list necessary! */\n\t\tif ( length == physicallength )\n\t\t\treturn THROWERROR( RET_INDEXLIST_EXCEEDS_MAX_LENGTH );\n\t\telse\n\t\t{\n\t\t\tint numberArray[NVMAX+NCMAX];\n\t\t\tgetNumberArray( numberArray );\n\n\t\t\t/* copy existing elements */\n\t\t\tfor ( i=0; i<length; ++i )\n\t\t\t{\n\t\t\t\tnumber[i] = numberArray[i];\n\t\t\t\tnext[i] = i+1;\n\t\t\t\tprevious[i] = i-1;\n\t\t\t}\n\n\t\t\t/* add new number at end of list */\n\t\t\tnumber[length] = addnumber;\n\t\t\tnext[length] = -1;\n\t\t\tprevious[length] = length-1;\n\n\t\t\t/* and set remaining entries to empty */\n\t\t\tfor ( i=length+1; i<physicallength; ++i )\n\t\t\t{\n\t\t\t\tnumber[i] = -1;\n\t\t\t\tnext[i] = -1;\n\t\t\t\tprevious[i] = -1;\n\t\t\t}\n\n\t\t\tfirst = 0;\n\t\t\tlast = length;\n\t\t\tlastusedindex = length;\n\t\t\t++length;\n\n\t\t\treturn THROWWARNING( RET_INDEXLIST_MUST_BE_REORDERD );\n\t\t}\n\t}\n}\n\n\n/*\n *\tr e m o v e N u m b e r\n */\nreturnValue Indexlist::removeNumber( int removenumber )\n{\n\tint i = getPhysicalIndex( removenumber );\n\n\t/* nothing to be done if number is not contained in index set */\n\tif ( i < 0 )\n\t\treturn SUCCESSFUL_RETURN;\n\n\tint p = previous[i];\n\tint n = next[i];\n\n\tif ( i == last )\n\t\tlast = p;\n\telse\n\t\tprevious[n] = p;\n\n\tif ( i == first )\n\t\tfirst = n;\n\telse\n\t\tnext[p] = n;\n\n\tnumber[i] = -1;\n\tnext[i] = -1;\n\tprevious[i] = -1;\n\t--length;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts w a p N u m b e r s\n */\nreturnValue Indexlist::swapNumbers( int number1, int number2 )\n{\n\tint index1 = getPhysicalIndex( number1 );\n\tint index2 = getPhysicalIndex( number2 );\n\n\t/* consistency check */\n\tif ( ( index1 < 0 ) || ( index2 < 0 ) )\n\t\treturn THROWERROR( RET_INDEXLIST_CORRUPTED );\n\n\tint tmp = number[index1];\n\tnumber[index1] = number[index2];\n\tnumber[index2] = tmp;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Indexlist.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Indexlist.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of inlined member functions of the Indexlist class designed \n *\tto manage index lists of constraints and bounds within a QProblem_SubjectTo.\n */\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n/*\n *\tg e t N u m b e r\n */\ninline int Indexlist::getNumber( int physicalindex ) const\n{\n\t/* consistency check */\n\tif ( ( physicalindex < 0 ) || ( physicalindex > length ) )\n\t\treturn -RET_INDEXLIST_OUTOFBOUNDS;\n\n\treturn number[physicalindex];\n}\n\n\n/*\n *\tg e t L e n g t h\n */\ninline int Indexlist::getLength( )\n{\n\treturn length;\n}\n\n\n/*\n *\tg e t L a s t N u m b e r\n */\ninline int Indexlist::getLastNumber( ) const\n{\n\treturn number[last];\n}\n\n\n/*\n *\tg e t L a s t N u m b e r\n */\ninline BooleanType Indexlist::isMember( int _number ) const\n{\n\tif ( getIndex( _number ) >= 0 )\n\t\treturn BT_TRUE;\n\telse\n\t\treturn BT_FALSE;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/MessageHandling.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/MessageHandling.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the MessageHandling class including global return values.\n *\n */\n\n\n\n#include <MessageHandling.hpp>\n#include <Utils.hpp>\n\n\n\n\n/** Defines pairs of global return values and messages. */\nMessageHandling::ReturnValueList returnValueList[] =\n{\n/* miscellaneous */\n{ SUCCESSFUL_RETURN, \"Successful return\", VS_VISIBLE },\n{ RET_DIV_BY_ZERO, \"Division by zero\", VS_VISIBLE },\n{ RET_INDEX_OUT_OF_BOUNDS, \"Index out of bounds\", VS_VISIBLE },\n{ RET_INVALID_ARGUMENTS, \"At least one of the arguments is invalid\", VS_VISIBLE },\n{ RET_ERROR_UNDEFINED, \"Error number undefined\", VS_VISIBLE },\n{ RET_WARNING_UNDEFINED, \"Warning number undefined\", VS_VISIBLE },\n{ RET_INFO_UNDEFINED, \"Info number undefined\", VS_VISIBLE },\n{ RET_EWI_UNDEFINED, \"Error/warning/info number undefined\", VS_VISIBLE },\n{ RET_AVAILABLE_WITH_LINUX_ONLY, \"This function is available under Linux only\", VS_HIDDEN },\n{ RET_UNKNOWN_BUG, \"The error occured is not yet known\", VS_VISIBLE },\n{ RET_PRINTLEVEL_CHANGED, \"Print level changed\", VS_VISIBLE },\n{ RET_NOT_YET_IMPLEMENTED, \"Requested function is not yet implemented.\", VS_VISIBLE },\n/* Indexlist */\n{ RET_INDEXLIST_MUST_BE_REORDERD, \"Index list has to be reordered\", VS_VISIBLE },\n{ RET_INDEXLIST_EXCEEDS_MAX_LENGTH, \"Index list exceeds its maximal physical length\", VS_VISIBLE },\n{ RET_INDEXLIST_CORRUPTED, \"Index list corrupted\", VS_VISIBLE },\n{ RET_INDEXLIST_OUTOFBOUNDS, \"Physical index is out of bounds\", VS_VISIBLE },\n{ RET_INDEXLIST_ADD_FAILED, \"Adding indices from another index set failed\", VS_VISIBLE },\n{ RET_INDEXLIST_INTERSECT_FAILED, \"Intersection with another index set failed\", VS_VISIBLE },\n/* SubjectTo / Bounds / Constraints */\n{ RET_INDEX_ALREADY_OF_DESIRED_STATUS, \"Index is already of desired status\", VS_VISIBLE },\n{ RET_SWAPINDEX_FAILED, \"Cannot swap between different indexsets\", VS_VISIBLE },\n{ RET_ADDINDEX_FAILED, \"Adding index to index set failed\", VS_VISIBLE },\n{ RET_NOTHING_TO_DO, \"Nothing to do\", VS_VISIBLE },\n{ RET_SETUP_BOUND_FAILED, \"Setting up bound index failed\", VS_VISIBLE },\n{ RET_SETUP_CONSTRAINT_FAILED, \"Setting up constraint index failed\", VS_VISIBLE },\n{ RET_MOVING_BOUND_FAILED, \"Moving bound between index sets failed\", VS_VISIBLE },\n{ RET_MOVING_CONSTRAINT_FAILED, \"Moving constraint between index sets failed\", VS_VISIBLE },\n/* QProblem */\n{ RET_QP_ALREADY_INITIALISED, \"QProblem has already been initialised\", VS_VISIBLE },\n{ RET_NO_INIT_WITH_STANDARD_SOLVER, \"Initialisation via extern QP solver is not yet implemented\", VS_VISIBLE },\n{ RET_RESET_FAILED, \"Reset failed\", VS_VISIBLE },\n{ RET_INIT_FAILED, \"Initialisation failed\", VS_VISIBLE },\n{ RET_INIT_FAILED_TQ, \"Initialisation failed due to TQ factorisation\", VS_VISIBLE },\n{ RET_INIT_FAILED_CHOLESKY, \"Initialisation failed due to Cholesky decomposition\", VS_VISIBLE },\n{ RET_INIT_FAILED_HOTSTART, \"Initialisation failed! QP could not be solved!\", VS_VISIBLE },\n{ RET_INIT_FAILED_INFEASIBILITY, \"Initial QP could not be solved due to infeasibility!\", VS_VISIBLE },\n{ RET_INIT_FAILED_UNBOUNDEDNESS, \"Initial QP could not be solved due to unboundedness!\", VS_VISIBLE },\n{ RET_INIT_SUCCESSFUL, \"Initialisation done\", VS_VISIBLE },\n{ RET_OBTAINING_WORKINGSET_FAILED, \"Failed to obtain working set for auxiliary QP\", VS_VISIBLE },\n{ RET_SETUP_WORKINGSET_FAILED, \"Failed to setup working set for auxiliary QP\", VS_VISIBLE },\n{ RET_SETUP_AUXILIARYQP_FAILED, \"Failed to setup auxiliary QP for initialised homotopy\", VS_VISIBLE },\n{ RET_NO_EXTERN_SOLVER, \"No extern QP solver available\", VS_VISIBLE },\n{ RET_QP_UNBOUNDED, \"QP is unbounded\", VS_VISIBLE },\n{ RET_QP_INFEASIBLE, \"QP is infeasible\", VS_VISIBLE },\n{ RET_QP_NOT_SOLVED, \"Problems occured while solving QP with standard solver\", VS_VISIBLE },\n{ RET_QP_SOLVED, \"QP successfully solved\", VS_VISIBLE },\n{ RET_UNABLE_TO_SOLVE_QP, \"Problems occured while solving QP\", VS_VISIBLE },\n{ RET_INITIALISATION_STARTED, \"Starting problem initialisation...\", VS_VISIBLE },\n{ RET_HOTSTART_FAILED, \"Unable to perform homotopy due to internal error\", VS_VISIBLE },\n{ RET_HOTSTART_FAILED_TO_INIT, \"Unable to initialise problem\", VS_VISIBLE },\n{ RET_HOTSTART_FAILED_AS_QP_NOT_INITIALISED, \"Unable to perform homotopy as previous QP is not solved\", VS_VISIBLE },\n{ RET_ITERATION_STARTED, \"Iteration\", VS_VISIBLE },\n{ RET_SHIFT_DETERMINATION_FAILED, \"Determination of shift of the QP data failed\", VS_VISIBLE },\n{ RET_STEPDIRECTION_DETERMINATION_FAILED, \"Determination of step direction failed\", VS_VISIBLE },\n{ RET_STEPLENGTH_DETERMINATION_FAILED, \"Determination of step direction failed\", VS_VISIBLE },\n{ RET_OPTIMAL_SOLUTION_FOUND, \"Optimal solution of neighbouring QP found\", VS_VISIBLE },\n{ RET_HOMOTOPY_STEP_FAILED, \"Unable to perform homotopy step\", VS_VISIBLE },\n{ RET_HOTSTART_STOPPED_INFEASIBILITY, \"Premature homotopy termination because QP is infeasible\", VS_VISIBLE },\n{ RET_HOTSTART_STOPPED_UNBOUNDEDNESS, \"Premature homotopy termination because QP is unbounded\", VS_VISIBLE },\n{ RET_WORKINGSET_UPDATE_FAILED, \"Unable to update working sets according to initial guesses\", VS_VISIBLE },\n{ RET_MAX_NWSR_REACHED, \"Maximum number of working set recalculations performed\", VS_VISIBLE },\n{ RET_CONSTRAINTS_NOT_SPECIFIED, \"Problem does comprise constraints! You have to specify new constraints' bounds\", VS_VISIBLE },\n{ RET_INVALID_FACTORISATION_FLAG, \"Invalid factorisation flag\", VS_VISIBLE },\n{ RET_UNABLE_TO_SAVE_QPDATA, \"Unable to save QP data\", VS_VISIBLE },\n{ RET_STEPDIRECTION_FAILED_TQ, \"Abnormal termination due to TQ factorisation\", VS_VISIBLE },\n{ RET_STEPDIRECTION_FAILED_CHOLESKY, \"Abnormal termination due to Cholesky factorisation\", VS_VISIBLE },\n{ RET_CYCLING_DETECTED, \"Cycling detected\", VS_VISIBLE },\n{ RET_CYCLING_NOT_RESOLVED, \"Cycling cannot be resolved, QP is probably infeasible\", VS_VISIBLE },\n{ RET_CYCLING_RESOLVED, \"Cycling probably resolved\", VS_VISIBLE },\n{ RET_STEPSIZE, \"\", VS_VISIBLE },\n{ RET_STEPSIZE_NONPOSITIVE, \"\", VS_VISIBLE },\n{ RET_SETUPSUBJECTTOTYPE_FAILED, \"Setup of SubjectToTypes failed\", VS_VISIBLE },\n{ RET_ADDCONSTRAINT_FAILED, \"Addition of constraint to working set failed\", VS_VISIBLE },\n{ RET_ADDCONSTRAINT_FAILED_INFEASIBILITY, \"Addition of constraint to working set failed\", VS_VISIBLE },\n{ RET_ADDBOUND_FAILED, \"Addition of bound to working set failed\", VS_VISIBLE },\n{ RET_ADDBOUND_FAILED_INFEASIBILITY, \"Addition of bound to working set failed\", VS_VISIBLE },\n{ RET_REMOVECONSTRAINT_FAILED, \"Removal of constraint from working set failed\", VS_VISIBLE },\n{ RET_REMOVEBOUND_FAILED, \"Removal of bound from working set failed\", VS_VISIBLE },\n{ RET_REMOVE_FROM_ACTIVESET, \"Removing from active set:\", VS_VISIBLE },\n{ RET_ADD_TO_ACTIVESET, \"Adding to active set:\", VS_VISIBLE },\n{ RET_REMOVE_FROM_ACTIVESET_FAILED, \"Removing from active set failed\", VS_VISIBLE },\n{ RET_ADD_TO_ACTIVESET_FAILED, \"Adding to active set failed\", VS_VISIBLE },\n{ RET_CONSTRAINT_ALREADY_ACTIVE, \"Constraint is already active\", VS_VISIBLE },\n{ RET_ALL_CONSTRAINTS_ACTIVE, \"All constraints are active, no further constraint can be added\", VS_VISIBLE },\n{ RET_LINEARLY_DEPENDENT, \"New bound/constraint is linearly dependent\", VS_VISIBLE },\n{ RET_LINEARLY_INDEPENDENT, \"New bound/constraint is linearly independent\", VS_VISIBLE },\n{ RET_LI_RESOLVED, \"Linear independence of active contraint matrix successfully resolved\", VS_VISIBLE },\n{ RET_ENSURELI_FAILED, \"Failed to ensure linear indepence of active contraint matrix\", VS_VISIBLE },\n{ RET_ENSURELI_FAILED_TQ, \"Abnormal termination due to TQ factorisation\", VS_VISIBLE },\n{ RET_ENSURELI_FAILED_NOINDEX, \"No index found, QP is probably infeasible\", VS_VISIBLE },\n{ RET_ENSURELI_FAILED_CYCLING, \"Cycling detected, QP is probably infeasible\", VS_VISIBLE },\n{ RET_BOUND_ALREADY_ACTIVE, \"Bound is already active\", VS_VISIBLE },\n{ RET_ALL_BOUNDS_ACTIVE, \"All bounds are active, no further bound can be added\", VS_VISIBLE },\n{ RET_CONSTRAINT_NOT_ACTIVE, \"Constraint is not active\", VS_VISIBLE },\n{ RET_BOUND_NOT_ACTIVE, \"Bound is not active\", VS_VISIBLE },\n{ RET_HESSIAN_NOT_SPD, \"Projected Hessian matrix not positive definite\", VS_VISIBLE },\n{ RET_MATRIX_SHIFT_FAILED, \"Unable to update matrices or to transform vectors\", VS_VISIBLE },\n{ RET_MATRIX_FACTORISATION_FAILED, \"Unable to calculate new matrix factorisations\", VS_VISIBLE },\n{ RET_PRINT_ITERATION_FAILED, \"Unable to print information on current iteration\", VS_VISIBLE },\n{ RET_NO_GLOBAL_MESSAGE_OUTPUTFILE, \"No global message output file initialised\", VS_VISIBLE },\n/* Utils */\n{ RET_UNABLE_TO_OPEN_FILE, \"Unable to open file\", VS_VISIBLE },\n{ RET_UNABLE_TO_WRITE_FILE, \"Unable to write into file\", VS_VISIBLE },\n{ RET_UNABLE_TO_READ_FILE, \"Unable to read from file\", VS_VISIBLE },\n{ RET_FILEDATA_INCONSISTENT, \"File contains inconsistent data\", VS_VISIBLE },\n/* SolutionAnalysis */\n{ RET_NO_SOLUTION, \"QP solution does not satisfy KKT optimality conditions\", VS_VISIBLE },\n{ RET_INACCURATE_SOLUTION, \"KKT optimality conditions not satisfied to sufficient accuracy\", VS_VISIBLE },\n{ TERMINAL_LIST_ELEMENT, \"\", VS_HIDDEN } /* IMPORTANT: Terminal list element! */\n};\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tM e s s a g e H a n d l i n g\n */\nMessageHandling::MessageHandling( ) :\terrorVisibility( VS_VISIBLE ),\n\t\t\t\t\t\t\t\t\t\twarningVisibility( VS_VISIBLE ),\n\t\t\t\t\t\t\t\t\t\tinfoVisibility( VS_VISIBLE ),\n\t\t\t\t\t\t\t\t\t\toutputFile( myStdout ),\n\t\t\t\t\t\t\t\t\t\terrorCount( 0 )\n{\n}\n\n/*\n *\tM e s s a g e H a n d l i n g\n */\nMessageHandling::MessageHandling( myFILE* _outputFile ) :\n\t\t\t\t\t\t\t\t\t\terrorVisibility( VS_VISIBLE ),\n\t\t\t\t\t\t\t\t\t\twarningVisibility( VS_VISIBLE ),\n\t\t\t\t\t\t\t\t\t\tinfoVisibility( VS_VISIBLE ),\n\t\t\t\t\t\t\t\t\t\toutputFile( _outputFile ),\n\t\t\t\t\t\t\t\t\t\terrorCount( 0 )\n{\n}\n\n/*\n *\tM e s s a g e H a n d l i n g\n */\nMessageHandling::MessageHandling(\tVisibilityStatus _errorVisibility,\n\t\t\t\t\t\t\t\t\tVisibilityStatus _warningVisibility,\n\t\t \t\t\t\t\t\t\tVisibilityStatus _infoVisibility\n\t\t\t\t\t\t\t\t\t) :\n\t\t\t\t\t\t\t\t\t\terrorVisibility( _errorVisibility ),\n\t\t\t\t\t\t\t\t\t\twarningVisibility( _warningVisibility ),\n\t\t\t\t\t\t\t\t\t\tinfoVisibility( _infoVisibility ),\n\t\t\t\t\t\t\t\t\t\toutputFile( myStderr ),\n\t\t\t\t\t\t\t\t\t\terrorCount( 0 )\n{\n}\n\n/*\n *\tM e s s a g e H a n d l i n g\n */\nMessageHandling::MessageHandling( \tmyFILE* _outputFile,\n\t\t\t\t\t\t\t\t\tVisibilityStatus _errorVisibility,\n\t\t\t\t\t\t\t\t\tVisibilityStatus _warningVisibility,\n\t\t \t\t\t\t\t\t\tVisibilityStatus _infoVisibility\n\t\t\t\t\t\t\t\t\t) :\n\t\t\t\t\t\t\t\t\t\terrorVisibility( _errorVisibility ),\n\t\t\t\t\t\t\t\t\t\twarningVisibility( _warningVisibility ),\n\t\t\t\t\t\t\t\t\t\tinfoVisibility( _infoVisibility ),\n\t\t\t\t\t\t\t\t\t\toutputFile( _outputFile ),\n\t\t\t\t\t\t\t\t\t\terrorCount( 0 )\n{\n}\n\n\n\n/*\n *\tM e s s a g e H a n d l i n g\n */\nMessageHandling::MessageHandling( const MessageHandling& rhs ) :\n\t\t\t\t\t\t\t\t\t\terrorVisibility( rhs.errorVisibility ),\n\t\t\t\t\t\t\t\t\t\twarningVisibility( rhs.warningVisibility ),\n\t\t\t\t\t\t\t\t\t\tinfoVisibility( rhs.infoVisibility ),\n\t\t\t\t\t\t\t\t\t\toutputFile( rhs.outputFile ),\n\t\t\t\t\t\t\t\t\t\terrorCount( rhs.errorCount )\n{\n}\n\n\n/*\n *\t~ M e s s a g e H a n d l i n g\n */\nMessageHandling::~MessageHandling( )\n{\n\t#ifdef PC_DEBUG\n\tif ( outputFile != 0 )\n\t\tfclose( outputFile );\n\t#endif\n}\n\n\n/*\n *\to p e r a t o r =\n */\nMessageHandling& MessageHandling::operator=( const MessageHandling& rhs )\n{\n\tif ( this != &rhs )\n\t{\n\t\terrorVisibility = rhs.errorVisibility;\n\t\twarningVisibility = rhs.warningVisibility;\n\t\tinfoVisibility = rhs.infoVisibility;\n\t\toutputFile = rhs.outputFile;\n\t\terrorCount = rhs.errorCount;\n\t}\n\n\treturn *this;\n}\n\n\n/*\n *\tt h r o w E r r o r\n */\nreturnValue MessageHandling::throwError(\n\treturnValue Enumber,\n\tconst char* additionaltext,\n\tconst char* functionname,\n\tconst char* filename,\n\tconst unsigned long linenumber,\n\tVisibilityStatus localVisibilityStatus\n\t)\n{\n\t/* consistency check */\n\tif ( Enumber <= SUCCESSFUL_RETURN )\n\t\treturn throwError( RET_ERROR_UNDEFINED,0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\n\t/* Call to common throwMessage function if error shall be displayed. */\n\tif ( errorVisibility == VS_VISIBLE )\n\t\treturn throwMessage( Enumber,additionaltext,functionname,filename,linenumber,localVisibilityStatus,\"ERROR\" );\n\telse\n\t\treturn Enumber;\n}\n\n\n/*\n *\tt h r o w W a r n i n g\n */\nreturnValue MessageHandling::throwWarning(\n\treturnValue Wnumber,\n\tconst char* additionaltext,\n\tconst char* functionname,\n\tconst char* filename,\n\tconst unsigned long linenumber,\n\tVisibilityStatus localVisibilityStatus\n  \t)\n{\n\t/* consistency check */\n  \tif ( Wnumber <= SUCCESSFUL_RETURN )\n\t\treturn throwError( RET_WARNING_UNDEFINED,0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\n\t/* Call to common throwMessage function if warning shall be displayed. */\n\tif ( warningVisibility == VS_VISIBLE )\n\t\treturn throwMessage( Wnumber,additionaltext,functionname,filename,linenumber,localVisibilityStatus,\"WARNING\" );\n  \telse\n  \t\treturn Wnumber;\n}\n\n\n/*\n *\tt h r o w I n f o\n */\nreturnValue MessageHandling::throwInfo(\n  \treturnValue Inumber,\n\tconst char* additionaltext,\n  \tconst char* functionname,\n\tconst char* filename,\n\tconst unsigned long linenumber,\n\tVisibilityStatus localVisibilityStatus\n \t)\n{\n\t/* consistency check */\n\tif ( Inumber < SUCCESSFUL_RETURN )\n\t\treturn throwError( RET_INFO_UNDEFINED,0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\n\t/* Call to common throwMessage function if info shall be displayed. */\n\tif ( infoVisibility == VS_VISIBLE )\n\t\treturn throwMessage( Inumber,additionaltext,functionname,filename,linenumber,localVisibilityStatus,\"INFO\" );\n\telse\n\t\treturn Inumber;\n}\n\n\n/*\n *\tr e s e t\n */\nreturnValue MessageHandling::reset( )\n{\n\tsetErrorVisibilityStatus(   VS_VISIBLE );\n\tsetWarningVisibilityStatus( VS_VISIBLE );\n\tsetInfoVisibilityStatus(    VS_VISIBLE );\n\n\tsetOutputFile( myStderr );\n\tsetErrorCount( 0 );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tl i s t A l l M e s s a g e s\n */\nreturnValue MessageHandling::listAllMessages( )\n{\n\t#ifdef PC_DEBUG\n\tint keypos = 0;\n\tchar myPrintfString[160];\n\n\t/* Run through whole returnValueList and print each item. */\n\twhile ( returnValueList[keypos].key != TERMINAL_LIST_ELEMENT )\n\t{\n\t\tsprintf( myPrintfString,\" %d - %s \\n\",keypos,returnValueList[keypos].data );\n\t\tmyPrintf( myPrintfString );\n\n\t\t++keypos;\n\t}\n\t#endif\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*****************************************************************************\n *  P R O T E C T E D                                                        *\n *****************************************************************************/\n\n\n#ifdef PC_DEBUG  /* Re-define throwMessage function for embedded code! */\n\n/*\n *\tt h r o w M e s s a g e\n */\nreturnValue MessageHandling::throwMessage(\n\treturnValue RETnumber,\n\tconst char* additionaltext,\n\tconst char* functionname,\n\tconst char* filename,\n\tconst unsigned long linenumber,\n\tVisibilityStatus localVisibilityStatus,\n\tconst char* RETstring\n \t)\n{\n\tint i;\n\n\tint keypos = 0;\n\tchar myPrintfString[160];\n\n\t/* 1) Determine number of whitespace for output. */\n\tchar whitespaces[41];\n\tint numberOfWhitespaces = (errorCount-1)*2;\n\n\tif ( numberOfWhitespaces < 0 )\n\t\tnumberOfWhitespaces = 0;\n\n\tif ( numberOfWhitespaces > 40 )\n\t\tnumberOfWhitespaces = 40;\n\n\tfor( i=0; i<numberOfWhitespaces; ++i )\n\t\twhitespaces[i] = ' ';\n\twhitespaces[numberOfWhitespaces] = '\\0';\n\n\t/* 2) Find error/warning/info in list. */\n\twhile ( returnValueList[keypos].key != TERMINAL_LIST_ELEMENT )\n\t{\n\t\tif ( returnValueList[keypos].key == RETnumber )\n\t\t\tbreak;\n\t\telse\n\t\t\t++keypos;\n\t}\n\n\tif ( returnValueList[keypos].key == TERMINAL_LIST_ELEMENT )\n\t{\n\t\tthrowError( RET_EWI_UNDEFINED,0,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\treturn RETnumber;\n\t}\n\n\t/* 3) Print error/warning/info. */\n\tif ( ( returnValueList[keypos].globalVisibilityStatus == VS_VISIBLE ) && ( localVisibilityStatus == VS_VISIBLE ) )\n\t{\n\t\tif ( errorCount > 0 )\n\t\t{\n\t\t\tsprintf( myPrintfString,\"%s->\", whitespaces );\n\t\t\tmyPrintf( myPrintfString );\n\t\t}\n\n\t\tif ( additionaltext == 0 )\n\t\t{\n\t\t\tsprintf(\tmyPrintfString,\"%s (%s, %s:%d): \\t%s\\n\",\n\t\t\t\t\t\tRETstring,functionname,filename,(int)linenumber,returnValueList[keypos].data\n\t\t\t\t\t\t);\n\t\t\tmyPrintf( myPrintfString );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tsprintf(\tmyPrintfString,\"%s (%s, %s:%d): \\t%s %s\\n\",\n\t\t\t\t\t\tRETstring,functionname,filename,(int)linenumber,returnValueList[keypos].data,additionaltext\n\t\t\t\t\t\t);\n\t\t\tmyPrintf( myPrintfString );\n\t\t}\n\n\t\t/* take care of proper indention for subsequent error messages */\n\t\tif ( RETstring[0] == 'E' )\n\t\t{\n\t\t\t++errorCount;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( errorCount > 0 )\n\t\t\t\tmyPrintf( \"\\n\" );\n\t\t\terrorCount = 0;\n\t\t}\n\t}\n\n\treturn RETnumber;\n}\n\n#else  /* = PC_DEBUG not defined */\n\n/*\n *\tt h r o w M e s s a g e\n */\nreturnValue MessageHandling::throwMessage(\n\treturnValue RETnumber,\n\tconst char* additionaltext,\n\tconst char* functionname,\n\tconst char* filename,\n\tconst unsigned long linenumber,\n\tVisibilityStatus localVisibilityStatus,\n\tconst char* RETstring\n \t)\n{\n\t/* DUMMY CODE FOR PRETENDING USE OF ARGUMENTS\n\t * FOR SUPPRESSING COMPILER WARNINGS! */\n\tint i = 0;\n\tif ( additionaltext == 0 ) i++;\n\tif ( functionname == 0 ) i++;\n\tif ( filename == 0 ) i++;\n\tif ( linenumber == 0 ) i++;\n\tif ( localVisibilityStatus == VS_VISIBLE ) i++;\n\tif ( RETstring == 0 ) i++;\n\t/* END OF DUMMY CODE */\n\n\treturn RETnumber;\n}\n\n#endif  /* PC_DEBUG */\n\n\n\n/*****************************************************************************\n *  G L O B A L  M E S S A G E  H A N D L E R                                *\n *****************************************************************************/\n\n\n/** Global message handler for all qpOASES modules.*/\nMessageHandling globalMessageHandler( myStderr,VS_VISIBLE,VS_VISIBLE,VS_VISIBLE );\n\n\n/*\n *\tg e t G l o b a l M e s s a g e H a n d l e r\n */\nMessageHandling* getGlobalMessageHandler( )\n{\n\treturn &globalMessageHandler;\n}\n\nconst char* MessageHandling::getErrorString(int error)\n{\n\treturn returnValueList[ error ].data;\n}\n\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/MessageHandling.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/MessageHandling.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of inlined member functions of the MessageHandling class. \n */\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n \n/*\n *\tg e t E r r o r V i s i b i l i t y S t a t u s\n */\ninline VisibilityStatus MessageHandling::getErrorVisibilityStatus( ) const\n{\n \treturn errorVisibility;\n}\n\n\n/*\n *\tg e t W a r n i n g V i s i b i l i t y S t a t u s\n */\ninline VisibilityStatus MessageHandling::getWarningVisibilityStatus( ) const\n{\n \treturn warningVisibility;\n}\n\n\n/*\n *\tg e t I n f o V i s i b i l i t y S t a t u s\n */\ninline VisibilityStatus MessageHandling::getInfoVisibilityStatus( ) const\n{\n \treturn infoVisibility;\n}\n\n\n/*\n *\tg e t O u t p u t F i l e\n */\ninline myFILE* MessageHandling::getOutputFile( ) const\n{\n \treturn outputFile;\n}\n\n\n/*\n *\tg e t E r r o r C o u n t\n */\ninline int MessageHandling::getErrorCount( ) const\n{\n \treturn errorCount;\n}\n\n\n/*\n *\ts e t E r r o r V i s i b i l i t y S t a t u s\n */\ninline void MessageHandling::setErrorVisibilityStatus( VisibilityStatus _errorVisibility ) \n{\n \terrorVisibility = _errorVisibility;\n}\n\n\n/*\n *\ts e t W a r n i n g V i s i b i l i t y S t a t u s\n */\ninline void MessageHandling::setWarningVisibilityStatus( VisibilityStatus _warningVisibility ) \n{\n \twarningVisibility = _warningVisibility;\n}\n\n\n/*\n *\ts e t I n f o V i s i b i l i t y S t a t u s\n */\ninline void MessageHandling::setInfoVisibilityStatus( VisibilityStatus _infoVisibility ) \n{\n \tinfoVisibility = _infoVisibility;\n}\n\n\n/*\n *\ts e t O u t p u t F i l e\n */\ninline void MessageHandling::setOutputFile( myFILE* _outputFile ) \n{\n \toutputFile = _outputFile;\n}\n\n\n/*\n *\ts e t E r r o r C o u n t\n */\ninline returnValue MessageHandling::setErrorCount( int _errorCount )\n{\n\tif ( _errorCount >= 0 ) \t\n\t{\n\t\terrorCount = _errorCount;\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn RET_INVALID_ARGUMENTS;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/QProblem.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/QProblem.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the QProblem class which is able to use the newly\n *\tdeveloped online active set strategy for parametric quadratic programming.\n */\n\n\n#include <QProblem.hpp>\n\n#include <stdio.h>\n\nvoid printmatrix2(char *name, double *A, int m, int n) {\n  int i, j;\n\n  printf(\"%s = [...\\n\", name);\n  for (i = 0; i < m; i++) {\n    for (j = 0; j < n; j++)\n        printf(\"  % 9.4f\", A[i*n+j]);\n    printf(\",\\n\");\n  }\n  printf(\"];\\n\");\n}\n\n//#define __PERFORM_KKT_TEST__\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tQ P r o b l e m\n */\nQProblem::QProblem( ) : QProblemB( )\n{\n\tconstraints.init( 0 );\n\n\tsizeT = 0;\n\n\tcyclingManager.init( 0,0 );\n}\n\n\n/*\n *\tQ P r o b l e m\n */\nQProblem::QProblem( int _nV, int _nC ) : QProblemB( _nV )\n{\n\t/* consistency checks */\n\tif ( _nV <= 0 )\n\t\t_nV = 1;\n\n\tif ( _nC < 0 )\n\t{\n\t\t_nC = 0;\n\t\tTHROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\tconstraints.init( _nC );\n\n\n\tsizeT = _nC;\n\tif ( _nC > _nV )\n\t\tsizeT = _nV;\n\n\tcyclingManager.init( _nV,_nC );\n}\n\n\n/*\n *\tQ P r o b l e m\n */\nQProblem::QProblem( const QProblem& rhs ) :\tQProblemB( rhs )\n{\n\tint i, j;\n\n\tint _nV = rhs.bounds.getNV( );\n\tint _nC = rhs.constraints.getNC( );\n\n\tfor( i=0; i<_nC; ++i )\n\t\tfor( j=0; j<_nV; ++j )\n\t\t\tA[i*NVMAX + j] = rhs.A[i*NVMAX + j];\n\n\tfor( i=0; i<_nC; ++i )\n\t\tlbA[i] = rhs.lbA[i];\n\n\tfor( i=0; i<_nC; ++i )\n\t\t\tubA[i] = rhs.ubA[i];\n\n\tconstraints = rhs.constraints;\n\n\tfor( i=0; i<(_nV+_nC); ++i )\n\t\ty[i] = rhs.y[i];\n\n\n\tsizeT = rhs.sizeT;\n\n\tfor( i=0; i<sizeT; ++i )\n\t\tfor( j=0; j<sizeT; ++j )\n\t\t\tT[i*NVMAX + j] = rhs.T[i*NVMAX + j];\n\n\tfor( i=0; i<_nV; ++i )\n\t\tfor( j=0; j<_nV; ++j )\n\t\t\tQ[i*NVMAX + j] = rhs.Q[i*NVMAX + j];\n\n\tfor( i=0; i<_nC; ++i )\n\t\tAx[i] = rhs.Ax[i];\n\n\tcyclingManager = rhs.cyclingManager;\n}\n\n\n/*\n *\t~ Q P r o b l e m\n */\nQProblem::~QProblem( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nQProblem& QProblem::operator=( const QProblem& rhs )\n{\n\tint i, j;\n\n\tif ( this != &rhs )\n\t{\n\t\tQProblemB::operator=( rhs );\n\n\n\t\tint _nV = rhs.bounds.getNV( );\n\t\tint _nC = rhs.constraints.getNC( );\n\n\t\tfor( i=0; i<_nC; ++i )\n\t\t\tfor( j=0; j<_nV; ++j )\n\t\t\t\tA[i*NVMAX + j] = rhs.A[i*NVMAX + j];\n\n\t\tfor( i=0; i<_nC; ++i )\n\t\t\tlbA[i] = rhs.lbA[i];\n\n\t\tfor( i=0; i<_nC; ++i )\n\t\t\tubA[i] = rhs.ubA[i];\n\n\t\tconstraints = rhs.constraints;\n\n\t\tfor( i=0; i<(_nV+_nC); ++i )\n\t\t\ty[i] = rhs.y[i];\n\n\n\t\tsizeT = rhs.sizeT;\n\n\t\tfor( i=0; i<sizeT; ++i )\n\t\t\tfor( j=0; j<sizeT; ++j )\n\t\t\t\tT[i*NVMAX + j] = rhs.T[i*NVMAX + j];\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tfor( j=0; j<_nV; ++j )\n\t\t\t\tQ[i*NVMAX + j] = rhs.Q[i*NVMAX + j];\n\n\t\tfor( i=0; i<_nC; ++i )\n\t\t\tAx[i] = rhs.Ax[i];\n\n\t\tcyclingManager = rhs.cyclingManager;\n\t}\n\n\treturn *this;\n}\n\n\n/*\n *\tr e s e t\n */\nreturnValue QProblem::reset( )\n{\n\tint i, j;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* 1) Reset bounds, Cholesky decomposition and status flags. */\n\tif ( QProblemB::reset( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_RESET_FAILED );\n\n\t/* 2) Reset constraints. */\n\tconstraints.init( nC );\n\n\t/* 3) Reset TQ factorisation. */\n\tfor( i=0; i<sizeT; ++i )\n\t\tfor( j=0; j<sizeT; ++j )\n\t\t\tT[i*NVMAX + j] = 0.0;\n\n\tfor( i=0; i<nV; ++i )\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tQ[i*NVMAX + j] = 0.0;\n\n\t/* 4) Reset cycling manager. */\n\tif ( cyclingManager.clearCyclingData( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_RESET_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ti n i t\n */\nreturnValue QProblem::init(\tconst real_t* const _H, const real_t* const _g, const real_t* const _A,\n\t\t\t\t\t\t\tconst real_t* const _lb, const real_t* const _ub,\n\t\t\t\t\t\t\tconst real_t* const _lbA, const real_t* const _ubA,\n\t\t\t\t\t\t\tint& nWSR, const real_t* const yOpt, real_t* const cputime\n\t\t\t\t\t\t\t)\n{\n\t/* 1) Setup QP data. */\n\tif (setupQPdata(_H, 0, _g, _A, _lb, _ub, _lbA, _ubA) != SUCCESSFUL_RETURN)\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* 2) Call to main initialisation routine (without any additional information). */\n\treturn solveInitialQP( 0,yOpt,0,0, nWSR,cputime );\n}\n\nreturnValue QProblem::init(\tconst real_t* const _H, const real_t* const _R, const real_t* const _g, const real_t* const _A,\n\t\t\t\t\t\t\tconst real_t* const _lb, const real_t* const _ub,\n\t\t\t\t\t\t\tconst real_t* const _lbA, const real_t* const _ubA,\n\t\t\t\t\t\t\tint& nWSR, const real_t* const yOpt, real_t* const cputime\n\t\t\t\t\t\t\t)\n{\n\t/* 1) Setup QP data. */\n\tif (setupQPdata(_H, _R, _g, _A, _lb, _ub, _lbA, _ubA) != SUCCESSFUL_RETURN)\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* 2) Call to main initialisation routine (without any additional information). */\n\treturn solveInitialQP( 0,yOpt,0,0, nWSR,cputime );\n}\n\n\n/*\n *\th o t s t a r t\n */\nreturnValue QProblem::hotstart(\tconst real_t* const g_new, const real_t* const lb_new, const real_t* const ub_new,\n\t\t\t\t\t\t\t\tconst real_t* const lbA_new, const real_t* const ubA_new,\n\t\t\t\t\t\t\t\tint& nWSR, real_t* const cputime\n\t\t\t\t\t\t\t\t)\n{\n\tint l;\n\n\t/* consistency check */\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )       ||\n\t\t ( getStatus( ) == QPS_PREPARINGAUXILIARYQP ) ||\n\t\t ( getStatus( ) == QPS_PERFORMINGHOMOTOPY )   )\n\t{\n\t\treturn THROWERROR( RET_HOTSTART_FAILED_AS_QP_NOT_INITIALISED );\n\t}\n\n\t/* start runtime measurement */\n\treal_t starttime = 0.0;\n\tif ( cputime != 0 )\n\t\tstarttime = getCPUtime( );\n\n\n\t/* I) PREPARATIONS */\n\t/* 1) Reset cycling and status flags and increase QP counter. */\n\tcyclingManager.clearCyclingData( );\n\n\tinfeasible = BT_FALSE;\n\tunbounded = BT_FALSE;\n\n\t++count;\n\n\t/* 2) Allocate delta vectors of gradient and (constraints') bounds. */\n\treturnValue returnvalue;\n\tBooleanType Delta_bC_isZero, Delta_bB_isZero;\n\n\tint FR_idx[NVMAX];\n\tint FX_idx[NVMAX];\n\tint AC_idx[NCMAX_ALLOC];\n\tint IAC_idx[NCMAX_ALLOC];\n\n\treal_t delta_g[NVMAX];\n\treal_t delta_lb[NVMAX];\n\treal_t delta_ub[NVMAX];\n\treal_t delta_lbA[NCMAX_ALLOC];\n\treal_t delta_ubA[NCMAX_ALLOC];\n\n\treal_t delta_xFR[NVMAX];\n\treal_t delta_xFX[NVMAX];\n\treal_t delta_yAC[NCMAX_ALLOC];\n\treal_t delta_yFX[NVMAX];\n\treal_t delta_Ax[NCMAX_ALLOC];\n\n\tint BC_idx;\n\tSubjectToStatus BC_status;\n\tBooleanType BC_isBound;\n\n\t#ifdef PC_DEBUG\n\tchar messageString[80];\n\t#endif\n\n\n\t/* II) MAIN HOMOTOPY LOOP */\n\tfor( l=0; l<nWSR; ++l )\n\t{\n\t\tstatus = QPS_PERFORMINGHOMOTOPY;\n\n\t\tif ( printlevel == PL_HIGH )\n\t\t{\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"%d ...\",l );\n\t\t  \tgetGlobalMessageHandler( )->throwInfo( RET_ITERATION_STARTED,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t\t#endif\n\t\t}\n\n\t\t/* 1) Setup index arrays. */\n\t\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\n\t\tif ( bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\n\t\tif ( constraints.getActive( )->getNumberArray( AC_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\n\t\tif ( constraints.getInactive( )->getNumberArray( IAC_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\n\t\t/* 2) Detemination of shift direction of the gradient and the (constraints') bounds. */\n\t\treturnvalue = hotstart_determineDataShift(  FX_idx, AC_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tg_new,lbA_new,ubA_new,lb_new,ub_new,\n\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_g,delta_lbA,delta_ubA,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tDelta_bC_isZero, Delta_bB_isZero );\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\t\t\tTHROWERROR( RET_SHIFT_DETERMINATION_FAILED );\n\t\t\treturn returnvalue;\n\t\t}\n\n\t\t/* 3) Determination of step direction of X and Y. */\n\t\treturnvalue = hotstart_determineStepDirection(\tFR_idx,FX_idx,AC_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_g,delta_lbA,delta_ubA,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tDelta_bC_isZero, Delta_bB_isZero,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_xFX,delta_xFR,delta_yAC,delta_yFX\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\t\t\tTHROWERROR( RET_STEPDIRECTION_DETERMINATION_FAILED );\n\t\t\treturn returnvalue;\n\t\t}\n\n\t\t/* 4) Determination of step length TAU. */\n\t\treturnvalue = hotstart_determineStepLength(\tFR_idx,FX_idx,AC_idx,IAC_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_lbA,delta_ubA,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_xFX,delta_xFR,delta_yAC,delta_yFX,delta_Ax,\n\t\t\t\t\t\t\t\t\t\t\t\t\tBC_idx,BC_status,BC_isBound\n\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\t\t\tTHROWERROR( RET_STEPLENGTH_DETERMINATION_FAILED );\n\t\t\treturn returnvalue;\n\t\t}\n\n\t\t/* 5) Realisation of the homotopy step. */\n\t\treturnvalue = hotstart_performStep(\tFR_idx,FX_idx,AC_idx,IAC_idx,\n\t\t\t\t\t\t\t\t\t\t\tdelta_g,delta_lbA,delta_ubA,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\tdelta_xFX,delta_xFR,delta_yAC,delta_yFX,delta_Ax,\n\t\t\t\t\t\t\t\t\t\t\tBC_idx,BC_status,BC_isBound\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\n\t\t\t/* stop runtime measurement */\n\t\t\tif ( cputime != 0 )\n\t\t\t\t\t*cputime = getCPUtime( ) - starttime;\n\n\t\t\t/* optimal solution found? */\n\t\t\tif ( returnvalue == RET_OPTIMAL_SOLUTION_FOUND )\n\t\t\t{\n\t\t\t\tstatus = QPS_SOLVED;\n\n\t\t\t\tif ( printlevel == PL_HIGH )\n\t\t\t\t\tTHROWINFO( RET_OPTIMAL_SOLUTION_FOUND );\n\n\t\t\t\t#ifdef PC_DEBUG\n\t \t\t\tif ( printIteration( l,BC_idx,BC_status,BC_isBound ) != SUCCESSFUL_RETURN )\n\t\t\t\t\tTHROWERROR( RET_PRINT_ITERATION_FAILED ); /* do not pass this as return value! */\n\t\t\t\t#endif\n\n\t\t\t\t/* check KKT optimality conditions */\n\t\t\t\treturn checkKKTconditions( );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* checks for infeasibility... */\n\t\t\t\tif ( isInfeasible( ) == BT_TRUE )\n\t\t\t\t{\n\t\t\t\t\tstatus = QPS_HOMOTOPYQPSOLVED;\n\t\t\t\t\treturn THROWERROR( RET_HOTSTART_STOPPED_INFEASIBILITY );\n\t\t\t\t}\n\n\t\t\t\t/* ...unboundedness... */\n\t\t\t\tif ( unbounded == BT_TRUE ) /* not necessary since objective function convex! */\n\t\t\t\t\treturn THROWERROR( RET_HOTSTART_STOPPED_UNBOUNDEDNESS );\n\n\t\t\t\t/* ... and throw unspecific error otherwise */\n\t\t\t\tTHROWERROR( RET_HOMOTOPY_STEP_FAILED );\n\t\t\t\treturn returnvalue;\n\t\t\t}\n\t\t}\n\n\t\t/* 6) Output information of successful QP iteration. */\n\t\tstatus = QPS_HOMOTOPYQPSOLVED;\n\n\t\t#ifdef PC_DEBUG\n\t\tif ( printIteration( l,BC_idx,BC_status,BC_isBound ) != SUCCESSFUL_RETURN )\n\t\t\tTHROWERROR( RET_PRINT_ITERATION_FAILED ); /* do not pass this as return value! */\n\t\t#endif\n\t}\n\n\n\t/* stop runtime measurement */\n\tif ( cputime != 0 )\n\t\t*cputime = getCPUtime( ) - starttime;\n\n\n\t/* if programm gets to here, output information that QP could not be solved\n\t * within the given maximum numbers of working set changes */\n\tif ( printlevel == PL_HIGH )\n\t{\n\t\t#ifdef PC_DEBUG\n\t\tsprintf( messageString,\"(nWSR = %d)\",nWSR );\n\t\treturn getGlobalMessageHandler( )->throwWarning( RET_MAX_NWSR_REACHED,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t#endif\n\t}\n\n\t/* Finally check KKT optimality conditions. */\n\treturnValue returnvalueKKTcheck = checkKKTconditions( );\n\n\tif ( returnvalueKKTcheck != SUCCESSFUL_RETURN )\n\t\treturn returnvalueKKTcheck;\n\telse\n\t\treturn RET_MAX_NWSR_REACHED;\n}\n\n\n/*\n *\tg e t N Z\n */\nint QProblem::getNZ( )\n{\n\t/* nZ = nFR - nAC */\n\treturn bounds.getFree( )->getLength( ) - constraints.getActive( )->getLength( );\n}\n\n\n/*\n *\tg e t D u a l S o l u t i o n\n */\nreturnValue QProblem::getDualSolution( real_t* const yOpt ) const\n{\n\tint i;\n\n\t/* return optimal dual solution vector\n\t * only if current QP has been solved */\n\tif ( ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED ) )\n\t{\n\t\tfor( i=0; i<getNV( )+getNC( ); ++i )\n\t\t\tyOpt[i] = y[i];\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn RET_QP_NOT_SOLVED;\n\t}\n}\n\n\n\n/*****************************************************************************\n *  P R O T E C T E D                                                        *\n *****************************************************************************/\n\n/*\n *\ts e t u p S u b j e c t T o T y p e\n */\nreturnValue QProblem::setupSubjectToType( )\n{\n\tint i;\n\tint nC = getNC( );\n\n\n\t/* I) SETUP SUBJECTTOTYPE FOR BOUNDS */\n\tif ( QProblemB::setupSubjectToType( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_SETUPSUBJECTTOTYPE_FAILED );\n\n\n\t/* II) SETUP SUBJECTTOTYPE FOR CONSTRAINTS */\n\t/* 1) Check if lower constraints' bounds are present. */\n\tconstraints.setNoLower( BT_TRUE );\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( lbA[i] > -INFTY )\n\t\t{\n\t\t\tconstraints.setNoLower( BT_FALSE );\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* 2) Check if upper constraints' bounds are present. */\n\tconstraints.setNoUpper( BT_TRUE );\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( ubA[i] < INFTY )\n\t\t{\n\t\t\tconstraints.setNoUpper( BT_FALSE );\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* 3) Determine implicit equality constraints and unbounded constraints. */\n\tint nEC = 0;\n\tint nUC = 0;\n\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( ( lbA[i] < -INFTY + BOUNDTOL ) && ( ubA[i] > INFTY - BOUNDTOL ) )\n\t\t{\n\t\t\tconstraints.setType( i,ST_UNBOUNDED );\n\t\t\t++nUC;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( lbA[i] > ubA[i] - BOUNDTOL )\n\t\t\t{\n\t\t\t\tconstraints.setType( i,ST_EQUALITY );\n\t\t\t\t++nEC;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tconstraints.setType( i,ST_BOUNDED );\n\t\t\t}\n\t\t}\n\t}\n\n\t/* 4) Set dimensions of constraints structure. */\n\tconstraints.setNEC( nEC );\n\tconstraints.setNUC( nUC );\n\tconstraints.setNIC( nC - nEC - nUC );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tc h o l e s k y D e c o m p o s i t i o n P r o j e c t e d\n */\nreturnValue QProblem::setupCholeskyDecompositionProjected( )\n{\n\tint i, j, k, ii, kk;\n\tint nV  = getNV( );\n\tint nFR = getNFR( );\n\tint nZ  = getNZ( );\n\n\t/* 1) Initialises R with all zeros. */\n\tfor( i=0; i<nV; ++i )\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tR[i*NVMAX + j] = 0.0;\n\n\t/* 2) Calculate Cholesky decomposition of projected Hessian Z'*H*Z. */\n\tif ( hessianType == HST_IDENTITY )\n\t{\n\t\t/* if Hessian is identity, so is its Cholesky factor. */\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tR[i*NVMAX + i] = 1.0;\n\t}\n\telse\n\t{\n\t\tif ( nZ > 0 )\n\t\t{\n\t\t\tint FR_idx[NVMAX];\n\t\t\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_INDEXLIST_CORRUPTED );\n\n#if 0\n\t\t\treal_t HZ[NVMAX*NVMAX];\n\t\t\treal_t ZHZ[NVMAX*NVMAX];\n\n\t\t\t/* calculate H*Z */\n\t\t\tfor ( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\n\t\t\t\tfor ( j=0; j<nZ; ++j )\n\t\t\t\t{\n\t\t\t\t\treal_t sum = 0.0;\n\t\t\t\t\tfor ( k=0; k<nFR; ++k )\n\t\t\t\t\t{\n\t\t\t\t\t\tkk = FR_idx[k];\n\t\t\t\t\t\tsum += H[ii*NVMAX + kk] * Q[kk*NVMAX + j];\n\t\t\t\t\t}\n\t\t\t\t\tHZ[i * NVMAX + j] = sum;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* calculate Z'*H*Z */\n\t\t\tfor ( i=0; i<nZ; ++i )\n\t\t\t\tfor ( j=0; j<nZ; ++j )\n\t\t\t\t{\n\t\t\t\t\treal_t sum = 0.0;\n\t\t\t\t\tfor ( k=0; k<nFR; ++k )\n\t\t\t\t\t{\n\t\t\t\t\t\tkk = FR_idx[k];\n\t\t\t\t\t\tsum += Q[kk*NVMAX + i] * HZ[k*NVMAX + j];\n\t\t\t\t\t}\n\t\t\t\t\tZHZ[i * NVMAX + j] = sum;\n\t\t\t\t}\n\n\t\t\t/* R'*R = Z'*H*Z */\n\t\t\treal_t sum, inv;\n\n\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t{\n\t\t\t\t/* j == i */\n\t\t\t\tsum = ZHZ[i*NVMAX + i];\n\n\t\t\t\tfor( k=(i-1); k>=0; --k )\n\t\t\t\t\tsum -= R[k*NVMAX + i] * R[k*NVMAX + i];\n\n\t\t\t\tif ( sum > 0.0 )\n\t\t\t\t{\n\t\t\t\t\tR[i*NVMAX + i] = sqrt( sum );\n\t\t\t\t\tinv = 1.0 / R[i * NVMAX + i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\thessianType = HST_SEMIDEF;\n\t\t\t\t\treturn THROWERROR( RET_HESSIAN_NOT_SPD );\n\t\t\t\t}\n\n\t\t\t\tfor( j=(i+1); j<nZ; ++j )\n\t\t\t\t{\n\t\t\t\t\tsum = ZHZ[j*NVMAX + i];\n\n\t\t\t\t\tfor( k=(i-1); k>=0; --k )\n\t\t\t\t\t\tsum -= R[k*NVMAX + i] * R[k*NVMAX + j];\n\n\t\t\t\t\tR[i*NVMAX + j] = sum * inv;\n\t\t\t\t}\n\t\t\t}\n#else\n\t\t\treal_t HZ[NVMAX];\n\t\t\treal_t ZHZ[NVMAX];\n\n\t\t\treal_t sum, inv;\n\t\t\tfor (j = 0; j < nZ; ++j)\n\t\t\t{\n\t\t\t\t/* Cache one column of Z. */\n\t\t\t\tfor (i = 0; i < NVMAX; ++i)\n\t\t\t\t\tZHZ[i] = Q[i * NVMAX + j];\n\n\t\t\t\t/* Create one column of the product H * Z. */\n\t\t\t\tfor (i = 0; i < nFR; ++i)\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\n\t\t\t\t\tsum = 0.0;\n\t\t\t\t\tfor (k = 0; k < nFR; ++k)\n\t\t\t\t\t{\n\t\t\t\t\t\tkk = FR_idx[k];\n\t\t\t\t\t\tsum += H[ii * NVMAX + kk] * ZHZ[kk];\n\t\t\t\t\t}\n\t\t\t\t\tHZ[ii] = sum;\n\t\t\t\t}\n\n\t\t\t\t/* Create one column of the product Z^T * H * Z. */\n\t\t\t\tfor (i = j; i < nZ; ++i)\n\t\t\t\t\tZHZ[ i ] = 0.0;\n\n\t\t\t\tfor (k = 0; k < nFR; ++k)\n\t\t\t\t{\n\t\t\t\t\tkk = FR_idx[k];\n\t\t\t\t\treal_t q = HZ[kk];\n\t\t\t\t\tfor (i = j; i < nZ; ++i)\n\t\t\t\t\t{\n\t\t\t\t\t\tZHZ[i] += Q[kk * NVMAX + i] * q;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\t/* Use the computed column to update the factorization. */\n\t\t\t\t/* j == i */\n\t\t\t\tsum = ZHZ[j];\n\n\t\t\t\tfor (k = (j - 1); k >= 0; --k)\n\t\t\t\t\tsum -= R[k * NVMAX + j] * R[k * NVMAX + j];\n\n\t\t\t\tif (sum > 0.0)\n\t\t\t\t{\n\t\t\t\t\tR[j * NVMAX + j] = sqrt(sum);\n\t\t\t\t\tinv = 1.0 / R[j * NVMAX + j];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\thessianType = HST_SEMIDEF;\n\t\t\t\t\treturn THROWERROR( RET_HESSIAN_NOT_SPD );\n\t\t\t\t}\n\n\t\t\t\tfor (i = (j + 1); i < nZ; ++i)\n\t\t\t\t{\n\t\t\t\t\tsum = ZHZ[i];\n\n\t\t\t\t\tfor (k = (j - 1); k >= 0; --k)\n\t\t\t\t\t\tsum -= R[k * NVMAX + j] * R[k * NVMAX + i];\n\n\t\t\t\t\tR[j * NVMAX + i] = sum * inv;\n\t\t\t\t}\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p T Q f a c t o r i s a t i o n\n */\nreturnValue QProblem::setupTQfactorisation( )\n{\n\tint i, j, ii;\n\tint nV  = getNV( );\n\tint nFR = getNFR( );\n\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INDEXLIST_CORRUPTED );\n\n\t/* 1) Set Q to unity matrix. */\n\tfor( i=0; i<nV; ++i )\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tQ[i*NVMAX + j] = 0.0;\n\n\tfor( i=0; i<nFR; ++i )\n\t{\n\t\tii = FR_idx[i];\n\t\tQ[ii*NVMAX + i] = 1.0;\n\t}\n\n \t/* 2) Set T to zero matrix. */\n\tfor( i=0; i<sizeT; ++i )\n\t\tfor( j=0; j<sizeT; ++j )\n\t\t\tT[i*NVMAX + j] = 0.0;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts o l v e I n i t i a l Q P\n */\nreturnValue QProblem::solveInitialQP(\tconst real_t* const xOpt, const real_t* const yOpt,\n\t\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds, const Constraints* const guessedConstraints,\n\t\t\t\t\t\t\t\t\t\tint& nWSR, real_t* const cputime\n\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i;\n\n\t/* some definitions */\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* start runtime measurement */\n\treal_t starttime = 0.0;\n\tif ( cputime != 0 )\n\t\tstarttime = getCPUtime( );\n\n\n\tstatus = QPS_NOTINITIALISED;\n\n\t/* I) ANALYSE QP DATA: */\n\t/* 1) Check if Hessian happens to be the identity matrix. */\n\tif ( checkForIdentityHessian( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 2) Setup type of bounds and constraints (i.e. unbounded, implicitly fixed etc.). */\n\tif ( setupSubjectToType( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 3) Initialise cycling manager. */\n\tcyclingManager.clearCyclingData( );\n\n\tstatus = QPS_PREPARINGAUXILIARYQP;\n\n\n\t/* II) SETUP AUXILIARY QP WITH GIVEN OPTIMAL SOLUTION: */\n\t/* 1) Setup bounds and constraints data structure. */\n\tif ( bounds.setupAllFree( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tif ( constraints.setupAllInactive( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 2) Setup optimal primal/dual solution for auxiliary QP. */\n\tif ( setupAuxiliaryQPsolution( xOpt,yOpt ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 3) Obtain linear independent working set for auxiliary QP. */\n\n\tstatic Bounds auxiliaryBounds;\n\n\tauxiliaryBounds.init( nV );\n\n\tstatic Constraints auxiliaryConstraints;\n\n\tauxiliaryConstraints.init( nC );\n\n\tif ( obtainAuxiliaryWorkingSet(\txOpt,yOpt,guessedBounds,guessedConstraints,\n\t\t\t\t\t\t\t\t\t&auxiliaryBounds,&auxiliaryConstraints ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 4) Setup working set of auxiliary QP and setup matrix factorisations. */\n\tif ( setupTQfactorisation( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED_TQ );\n\n\tif ( setupAuxiliaryWorkingSet( &auxiliaryBounds,&auxiliaryConstraints,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tif ( ( getNAC( ) + getNFX( ) ) == 0 )\n\t{\n\t\t/* Factorise full Hessian if no bounds/constraints are active. */\n\t\tif (hasCholesky == BT_FALSE)\n\t\t\tif ( setupCholeskyDecomposition( ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_INIT_FAILED_CHOLESKY );\n\t\t/* ... else we use user provided Cholesky factorization. At the moment\n\t\t * we can do that only for cold-started solver. */\n\t}\n\telse\n\t{\n\t\t/* Factorise projected Hessian if there active bounds/constraints. */\n\t\tif ( setupCholeskyDecompositionProjected( ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_INIT_FAILED_CHOLESKY );\n\t\t/* TODO: use user-supplied Hessian decomposition. R_Z = R * Z. */\n\t}\n\n\t/* 5) Store original QP formulation... */\n\treal_t g_original[NVMAX];\n\treal_t lb_original[NVMAX];\n\treal_t ub_original[NVMAX];\n\treal_t lbA_original[NCMAX_ALLOC];\n\treal_t ubA_original[NCMAX_ALLOC];\n\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tg_original[i] = g[i];\n\t\tlb_original[i] = lb[i];\n\t\tub_original[i] = ub[i];\n\t}\n\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tlbA_original[i] = lbA[i];\n\t\tubA_original[i] = ubA[i];\n\t}\n\n\t/* ... and setup QP data of an auxiliary QP having an optimal solution\n\t * as specified by the user (or xOpt = yOpt = 0, by default). */\n\tif ( setupAuxiliaryQPgradient( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tif ( setupAuxiliaryQPbounds( &auxiliaryBounds,&auxiliaryConstraints,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tstatus = QPS_AUXILIARYQPSOLVED;\n\n\n\t/* III) SOLVE ACTUAL INITIAL QP: */\n\t/* Use hotstart method to find the solution of the original initial QP,... */\n\treturnValue returnvalue = hotstart( g_original,lb_original,ub_original,lbA_original,ubA_original, nWSR,0 );\n\n\n\t/* ... check for infeasibility and unboundedness... */\n\tif ( isInfeasible( ) == BT_TRUE )\n\t\treturn THROWERROR( RET_INIT_FAILED_INFEASIBILITY );\n\n\tif ( isUnbounded( ) == BT_TRUE )\n\t\treturn THROWERROR( RET_INIT_FAILED_UNBOUNDEDNESS );\n\n\t/* ... and internal errors. */\n\tif ( ( returnvalue != SUCCESSFUL_RETURN ) && ( returnvalue != RET_MAX_NWSR_REACHED )  &&\n\t     ( returnvalue != RET_INACCURATE_SOLUTION ) && ( returnvalue != RET_NO_SOLUTION ) )\n\t\treturn THROWERROR( RET_INIT_FAILED_HOTSTART );\n\n\n\t/* stop runtime measurement */\n\tif ( cputime != 0 )\n\t\t*cputime = getCPUtime( ) - starttime;\n\n\tif ( printlevel == PL_HIGH )\n\t\tTHROWINFO( RET_INIT_SUCCESSFUL );\n\n\treturn returnvalue;\n}\n\n\n/*\n *\to b t a i n A u x i l i a r y W o r k i n g S e t\n */\nreturnValue QProblem::obtainAuxiliaryWorkingSet(\tconst real_t* const xOpt, const real_t* const yOpt,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds, const Constraints* const guessedConstraints,\n\t\t\t\t\t\t\t\t\t\t\t\t\tBounds* auxiliaryBounds, Constraints* auxiliaryConstraints\n\t\t\t\t\t\t\t\t\t\t\t\t\t) const\n{\n\tint i = 0;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* 1) Ensure that desiredBounds is allocated (and different from guessedBounds). */\n\tif ( ( auxiliaryBounds == 0 ) || ( auxiliaryBounds == guessedBounds ) )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\tif ( ( auxiliaryConstraints == 0 ) || ( auxiliaryConstraints == guessedConstraints ) )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\n\tSubjectToStatus guessedStatus;\n\n\t/* 2) Setup working set of bounds for auxiliary initial QP. */\n\tif ( QProblemB::obtainAuxiliaryWorkingSet( xOpt,yOpt,guessedBounds, auxiliaryBounds ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\n\t/* 3) Setup working set of constraints for auxiliary initial QP. */\n\tif ( guessedConstraints != 0 )\n\t{\n\t\t/* If an initial working set is specific, use it!\n\t\t * Moreover, add all equality constraints if specified. */\n\t\tfor( i=0; i<nC; ++i )\n\t\t{\n\t\t\tguessedStatus = guessedConstraints->getStatus( i );\n\n\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t{\n\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,guessedStatus ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t}\n\t\t}\n\t}\n\telse\t/* No initial working set specified. */\n\t{\n\t\t/* Obtain initial working set by \"clipping\". */\n\t\tif ( ( xOpt != 0 ) && ( yOpt == 0 ) )\n\t\t{\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t{\n\t\t\t\tif ( Ax[i] <= lbA[i] + BOUNDTOL )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif ( Ax[i] >= ubA[i] - BOUNDTOL )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_UPPER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\t/* Moreover, add all equality constraints if specified. */\n\t\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Obtain initial working set in accordance to sign of dual solution vector. */\n\t\tif ( ( xOpt == 0 ) && ( yOpt != 0 ) )\n\t\t{\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t{\n\t\t\t\tif ( yOpt[nV+i] > ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif ( yOpt[nV+i] < -ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_UPPER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\t/* Moreover, add all equality constraints if specified. */\n\t\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* If xOpt and yOpt are null pointer and no initial working is specified,\n\t\t * start with empty working set (or implicitly fixed bounds and equality constraints only)\n\t\t * for auxiliary QP. */\n\t\tif ( ( xOpt == 0 ) && ( yOpt == 0 ) )\n\t\t{\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t{\n\t\t\t\t/* Only add all equality constraints if specified. */\n\t\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryConstraints->setupConstraint( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\ts e t u p A u x i l i a r y W o r k i n g S e t\n */\nreturnValue QProblem::setupAuxiliaryWorkingSet(\tconst Bounds* const auxiliaryBounds,\n\t\t\t\t\t\t\t\t\t\t\t\tconst Constraints* const auxiliaryConstraints,\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType setupAfresh\n\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\t/* consistency checks */\n\tif ( auxiliaryBounds != 0 )\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tif ( ( bounds.getStatus( i ) == ST_UNDEFINED ) || ( auxiliaryBounds->getStatus( i ) == ST_UNDEFINED ) )\n\t\t\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\tif ( auxiliaryConstraints != 0 )\n\t{\n\t\tfor( i=0; i<nC; ++i )\n\t\t\tif ( ( constraints.getStatus( i ) == ST_UNDEFINED ) || ( auxiliaryConstraints->getStatus( i ) == ST_UNDEFINED ) )\n\t\t\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\n\t/* I) SETUP CHOLESKY FLAG:\n\t *    Cholesky decomposition shall only be updated if working set\n\t *    shall be updated (i.e. NOT setup afresh!) */\n\tBooleanType updateCholesky;\n\tif ( setupAfresh == BT_TRUE )\n\t\tupdateCholesky = BT_FALSE;\n\telse\n\t\tupdateCholesky = BT_TRUE;\n\n\n\t/* II) REMOVE FORMERLY ACTIVE (CONSTRAINTS') BOUNDS (IF NECESSARY): */\n\tif ( setupAfresh == BT_FALSE )\n\t{\n\t\t/* 1) Remove all active constraints that shall be inactive AND\n\t\t*    all active constraints that are active at the wrong bound. */\n\t\tfor( i=0; i<nC; ++i )\n\t\t{\n\t\t\tif ( ( constraints.getStatus( i ) == ST_LOWER ) && ( auxiliaryConstraints->getStatus( i ) != ST_LOWER ) )\n\t\t\t\tif ( removeConstraint( i,updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\n\t\t\tif ( ( constraints.getStatus( i ) == ST_UPPER ) && ( auxiliaryConstraints->getStatus( i ) != ST_UPPER ) )\n\t\t\t\tif ( removeConstraint( i,updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\t\t}\n\n\t\t/* 2) Remove all active bounds that shall be inactive AND\n\t\t*    all active bounds that are active at the wrong bound. */\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\n\t\t\tif ( ( bounds.getStatus( i ) == ST_LOWER ) && ( auxiliaryBounds->getStatus( i ) != ST_LOWER ) )\n\t\t\t\tif ( removeBound( i,updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\n\t\t\tif ( ( bounds.getStatus( i ) == ST_UPPER ) && ( auxiliaryBounds->getStatus( i ) != ST_UPPER ) )\n\t\t\t\tif ( removeBound( i,updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\t\t}\n\t}\n\n\n\t/* III) ADD NEWLY ACTIVE (CONSTRAINTS') BOUNDS: */\n\t/* 1) Add all inactive bounds that shall be active AND\n\t *    all formerly active bounds that have been active at the wrong bound. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( ( bounds.getStatus( i ) == ST_INACTIVE ) && ( auxiliaryBounds->getStatus( i ) != ST_INACTIVE ) )\n\t\t{\n\t\t\t/* Add bound only if it is linearly independent from the current working set. */\n\t\t\tif ( addBound_checkLI( i ) == RET_LINEARLY_INDEPENDENT )\n\t\t\t{\n\t\t\t\tif ( addBound( i,auxiliaryBounds->getStatus( i ),updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\t\t\t}\n\t\t}\n\t}\n\n\t/* 2) Add all inactive constraints that shall be active AND\n\t *    all formerly active constraints that have been active at the wrong bound. */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( ( auxiliaryConstraints->getStatus( i ) == ST_LOWER ) || ( auxiliaryConstraints->getStatus( i ) == ST_UPPER ) )\n\t\t{\n\t\t\t/* formerly inactive */\n\t\t\tif ( constraints.getStatus( i ) == ST_INACTIVE )\n\t\t\t{\n\t\t\t\t/* Add constraint only if it is linearly independent from the current working set. */\n\t\t\t\tif ( addConstraint_checkLI( i ) == RET_LINEARLY_INDEPENDENT )\n\t\t\t\t{\n\t\t\t\t\tif ( addConstraint( i,auxiliaryConstraints->getStatus( i ),updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y Q P s o l u t i o n\n */\nreturnValue QProblem::setupAuxiliaryQPsolution(\tconst real_t* const xOpt, const real_t* const yOpt\n\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* Setup primal/dual solution vector for auxiliary initial QP:\n\t * if a null pointer is passed, a zero vector is assigned;\n\t *  old solution vector is kept if pointer to internal solution vevtor is passed. */\n\tif ( xOpt != 0 )\n\t{\n\t\tif ( xOpt != x )\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t\tx[i] = xOpt[i];\n\n\t\tfor ( j=0; j<nC; ++j )\n\t\t{\n\t\t\tAx[j] = 0.0;\n\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t\tAx[j] += A[j*NVMAX + i] * x[i];\n\t\t}\n\t}\n\telse\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tx[i] = 0.0;\n\n\t\tfor ( j=0; j<nC; ++j )\n\t\t\tAx[j] = 0.0;\n\t}\n\n\tif ( yOpt != 0 )\n\t{\n\t\tif ( yOpt != y )\n\t\t\tfor( i=0; i<nV+nC; ++i )\n\t\t\t\ty[i] = yOpt[i];\n\t}\n\telse\n\t{\n\t\tfor( i=0; i<nV+nC; ++i )\n\t\t\ty[i] = 0.0;\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y Q P g r a d i e n t\n */\nreturnValue QProblem::setupAuxiliaryQPgradient( )\n{\n\tint i, j;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* Setup gradient vector: g = -H*x + [Id A]'*[yB yC]. */\n\tfor ( i=0; i<nV; ++i )\n\t{\n\t\t/* Id'*yB */\n\t\tg[i] = y[i];\n\n\t\t/* A'*yC */\n\t\tfor ( j=0; j<nC; ++j )\n\t\t\tg[i] += A[j*NVMAX + i] * y[nV+j];\n\n\t\t/* -H*x */\n\t\tfor ( j=0; j<nV; ++j )\n\t\t\tg[i] -= H[i*NVMAX + j] * x[j];\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y Q P b o u n d s\n */\nreturnValue QProblem::setupAuxiliaryQPbounds(\tconst Bounds* const auxiliaryBounds,\n\t\t\t\t\t\t\t\t\t\t\t\tconst Constraints* const auxiliaryConstraints,\n\t\t\t\t\t\t\t\t\t\t\t\tBooleanType useRelaxation\n\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* 1) Setup bound vectors. */\n\tfor ( i=0; i<nV; ++i )\n\t{\n\t\tswitch ( bounds.getStatus( i ) )\n\t\t{\n\t\t\tcase ST_INACTIVE:\n\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t{\n\t\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t\t{\n\t\t\t\t\t\tlb[i] = x[i];\n\t\t\t\t\t\tub[i] = x[i];\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If a bound is inactive although it was supposed to be\n\t\t\t\t\t\t* active by the auxiliaryBounds, it could not be added\n\t\t\t\t\t\t* due to linear dependence. Thus set it \"strongly inactive\". */\n\t\t\t\t\t\tif ( auxiliaryBounds->getStatus( i ) == ST_LOWER )\n\t\t\t\t\t\t\tlb[i] = x[i];\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tlb[i] = x[i] - BOUNDRELAXATION;\n\n\t\t\t\t\t\tif ( auxiliaryBounds->getStatus( i ) == ST_UPPER )\n\t\t\t\t\t\t\tub[i] = x[i];\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tub[i] = x[i] + BOUNDRELAXATION;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase ST_LOWER:\n\t\t\t\tlb[i] = x[i];\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tub[i] = x[i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t\t\tub[i] = x[i] + BOUNDRELAXATION;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase ST_UPPER:\n\t\t\t\tub[i] = x[i];\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tlb[i] = x[i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t\t\tlb[i] = x[i] - BOUNDRELAXATION;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t\t}\n\t}\n\n\t/* 2) Setup constraints vectors. */\n\tfor ( i=0; i<nC; ++i )\n\t{\n\t\tswitch ( constraints.getStatus( i ) )\n\t\t{\n\t\t\tcase ST_INACTIVE:\n\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t{\n\t\t\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t\t\t{\n\t\t\t\t\t\tlbA[i] = Ax[i];\n\t\t\t\t\t\tubA[i] = Ax[i];\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If a constraint is inactive although it was supposed to be\n\t\t\t\t\t\t* active by the auxiliaryConstraints, it could not be added\n\t\t\t\t\t\t* due to linear dependence. Thus set it \"strongly inactive\". */\n\t\t\t\t\t\tif ( auxiliaryConstraints->getStatus( i ) == ST_LOWER )\n\t\t\t\t\t\t\tlbA[i] = Ax[i];\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tlbA[i] = Ax[i] - BOUNDRELAXATION;\n\n\t\t\t\t\t\tif ( auxiliaryConstraints->getStatus( i ) == ST_UPPER )\n\t\t\t\t\t\t\tubA[i] = Ax[i];\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tubA[i] = Ax[i] + BOUNDRELAXATION;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase ST_LOWER:\n\t\t\t\tlbA[i] = Ax[i];\n\t\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tubA[i] = Ax[i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t\t\tubA[i] = Ax[i] + BOUNDRELAXATION;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase ST_UPPER:\n\t\t\t\tubA[i] = Ax[i];\n\t\t\t\tif ( constraints.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tlbA[i] = Ax[i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t\t\tlbA[i] = Ax[i] - BOUNDRELAXATION;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ta d d C o n s t r a i n t\n */\nreturnValue QProblem::addConstraint(\tint number, SubjectToStatus C_status,\n\t\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\n\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii;\n\n\t/* consistency checks */\n\tif ( constraints.getStatus( number ) != ST_INACTIVE )\n\t\treturn THROWERROR( RET_CONSTRAINT_ALREADY_ACTIVE );\n\n\tif ( ( constraints.getNC( ) - getNAC( ) ) == constraints.getNUC( ) )\n\t\treturn THROWERROR( RET_ALL_CONSTRAINTS_ACTIVE );\n\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )    ||\n\t\t ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED )            )\n\t{\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\n\n\t/* I) ENSURE LINEAR INDEPENDENCE OF THE WORKING SET,\n\t *    i.e. remove a constraint or bound if linear dependence occurs. */\n\t/* check for LI only if Cholesky decomposition shall be updated! */\n\tif ( updateCholesky == BT_TRUE )\n\t{\n\t\treturnValue ensureLIreturnvalue = addConstraint_ensureLI( number,C_status );\n\n\t\tswitch ( ensureLIreturnvalue )\n\t\t{\n\t\t\tcase SUCCESSFUL_RETURN:\n\t\t\t\tbreak;\n\n\t\t\tcase RET_LI_RESOLVED:\n\t\t\t\tbreak;\n\n\t\t\tcase RET_ENSURELI_FAILED_NOINDEX:\n\t\t\t\treturn THROWERROR( RET_ADDCONSTRAINT_FAILED_INFEASIBILITY );\n\n\t\t\tcase RET_ENSURELI_FAILED_CYCLING:\n\t\t\t\treturn THROWERROR( RET_ADDCONSTRAINT_FAILED_INFEASIBILITY );\n\n\t\t\tdefault:\n\t\t\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\t\t}\n\t}\n\n\t/* some definitions */\n\tint nFR = getNFR( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\tint tcol = sizeT - nAC;\n\n\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ADDCONSTRAINT_FAILED );\n\n\treal_t aFR[NVMAX];\n\treal_t wZ[NVMAX];\n\tfor( i=0; i<nZ; ++i )\n\t\twZ[i] = 0.0;\n\n\n\t/* II) ADD NEW ACTIVE CONSTRAINT TO MATRIX T: */\n\t/* 1) Add row [wZ wY] = aFR'*[Z Y] to the end of T: assign aFR. */\n\tfor( i=0; i<nFR; ++i )\n\t{\n\t\tii = FR_idx[i];\n\t\taFR[i] = A[number*NVMAX + ii];\n\t}\n\n\t/* calculate wZ */\n\tfor( i=0; i<nFR; ++i )\n\t{\n\t\tii = FR_idx[i];\n\t\tfor( j=0; j<nZ; ++j )\n\t\t\twZ[j] += aFR[i] * Q[ii*NVMAX + j];\n\t}\n\n\t/* 2) Calculate wY and store it directly into T. */\n\tif ( nAC > 0 )\n\t{\n\t\tfor( j=0; j<nAC; ++j )\n\t\t\tT[nAC*NVMAX + tcol+j] = 0.0;\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\t\t\tfor( j=0; j<nAC; ++j )\n\t\t\t\tT[nAC*NVMAX + tcol+j] += aFR[i] * Q[ii*NVMAX + nZ+j];\n\t\t}\n\t}\n\n\n\treal_t c, s;\n\n\tif ( nZ > 0 )\n\t{\n\t\t/* II) RESTORE TRIANGULAR FORM OF T: */\n\t\t/*     Use column-wise Givens rotations to restore reverse triangular form\n\t\t*      of T, simultanenous change of Q (i.e. Z) and R. */\n\t\tfor( j=0; j<nZ-1; ++j )\n\t\t{\n\t\t\tcomputeGivens( wZ[j+1],wZ[j], wZ[j+1],wZ[j],c,s );\n\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\t\t\t\tapplyGivens( c,s,Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j], Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j] );\n\t\t\t}\n\n\t\t\tif ( ( updateCholesky == BT_TRUE ) && ( hessianType != HST_IDENTITY ) )\n\t\t\t{\n\t\t\t\tfor( i=0; i<=j+1; ++i )\n\t\t\t\t\tapplyGivens( c,s,R[i*NVMAX + 1+j],R[i*NVMAX + j], R[i*NVMAX + 1+j],R[i*NVMAX + j] );\n\t\t\t}\n\t\t}\n\n\t\tT[nAC*NVMAX + tcol-1] = wZ[nZ-1];\n\n\n\t\tif ( ( updateCholesky == BT_TRUE ) && ( hessianType != HST_IDENTITY ) )\n\t\t{\n\t\t\t/* III) RESTORE TRIANGULAR FORM OF R:\n\t\t\t *      Use row-wise Givens rotations to restore upper triangular form of R. */\n\t\t\tfor( i=0; i<nZ-1; ++i )\n\t\t\t{\n\t\t\t\tcomputeGivens( R[i*NVMAX + i],R[(1+i)*NVMAX + i], R[i*NVMAX + i],R[(1+i)*NVMAX + i],c,s );\n\n\t\t\t\tfor( j=(1+i); j<(nZ-1); ++j ) /* last column of R is thrown away */\n\t\t\t\t\tapplyGivens( c,s,R[i*NVMAX + j],R[(1+i)*NVMAX + j], R[i*NVMAX + j],R[(1+i)*NVMAX + j] );\n\t\t\t}\n\t\t\t/* last column of R is thrown away */\n\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\tR[i*NVMAX + nZ-1] = 0.0;\n\t\t}\n\t}\n\n\n\t/* IV) UPDATE INDICES */\n\tif ( constraints.moveInactiveToActive( number,C_status ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ADDCONSTRAINT_FAILED );\n\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\ta d d C o n s t r a i n t _ c h e c k L I\n */\nreturnValue QProblem::addConstraint_checkLI( int number )\n{\n\tint i, j, jj;\n\tint nFR = getNFR( );\n\tint nZ  = getNZ( );\n\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INDEXLIST_CORRUPTED );\n\n\t/* Check if constraint <number> is linearly independent from the\n\t   the active ones (<=> is element of null space of Afr). */\n\treal_t sum;\n\n\tfor( i=0; i<nZ; ++i )\n\t{\n\t\tsum = 0.0;\n\t\tfor( j=0; j<nFR; ++j )\n\t\t{\n\t\t\tjj = FR_idx[j];\n\t\t\tsum += Q[jj*NVMAX + i] * A[number*NVMAX + jj];\n\t\t}\n\n\t\tif ( getAbs( sum ) > 10.0*EPS )\n\t\t\treturn RET_LINEARLY_INDEPENDENT;\n\t}\n\n\treturn RET_LINEARLY_DEPENDENT;\n}\n\n\n/*\n *\ta d d C o n s t r a i n t _ e n s u r e L I\n */\nreturnValue QProblem::addConstraint_ensureLI( int number, SubjectToStatus C_status )\n{\n\tint i, j, ii, jj;\n\tint nV  = getNV( );\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\n\t/* I) Check if new constraint is linearly independent from the active ones. */\n\treturnValue returnvalueCheckLI = addConstraint_checkLI( number );\n\n\tif ( returnvalueCheckLI == RET_INDEXLIST_CORRUPTED )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\tif ( returnvalueCheckLI == RET_LINEARLY_INDEPENDENT )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n \t/* II) NEW CONSTRAINT IS LINEARLY DEPENDENT: */\n\t/* 1) Determine coefficients of linear combination,\n\t *    cf. M.J. Best. Applied Mathematics and Parallel Computing, chapter:\n\t *    An Algorithm for the Solution of the Parametric Quadratic Programming\n\t *    Problem, pages 57-76. Physica-Verlag, Heidelberg, 1996. */\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\tint FX_idx[NVMAX];\n\tif ( bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\treal_t xiC[NCMAX_ALLOC];\n\treal_t xiC_TMP[NCMAX_ALLOC];\n\treal_t xiB[NVMAX];\n\n\t/* 2) Calculate xiC */\n\tif ( nAC > 0 )\n\t{\n\t\tif ( C_status == ST_LOWER )\n\t\t{\n\t\t\tfor( i=0; i<nAC; ++i )\n\t\t\t{\n\t\t\t\txiC_TMP[i] = 0.0;\n\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\txiC_TMP[i] += Q[jj*NVMAX + nZ+i] * A[number*NVMAX + jj];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tfor( i=0; i<nAC; ++i )\n\t\t\t{\n\t\t\t\txiC_TMP[i] = 0.0;\n\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\txiC_TMP[i] -= Q[jj*NVMAX + nZ+i] * A[number*NVMAX + jj];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif ( backsolveT( xiC_TMP, BT_TRUE, xiC ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_ENSURELI_FAILED_TQ );\n\t}\n\n\t/* 3) Calculate xiB. */\n\tint AC_idx[NCMAX_ALLOC];\n\tif ( constraints.getActive( )->getNumberArray( AC_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\tif ( C_status == ST_LOWER )\n\t{\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\t\t\txiB[i] = A[number*NVMAX + ii];\n\n\t\t\tfor( j=0; j<nAC; ++j )\n\t\t\t{\n\t\t\t\tjj = AC_idx[j];\n\t\t\t\txiB[i] -= A[jj*NVMAX + ii] * xiC[j];\n\t\t\t}\n\t\t}\n\t}\n\telse\n\t{\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\t\t\txiB[i] = -A[number*NVMAX + ii];\n\n\t\t\tfor( j=0; j<nAC; ++j )\n\t\t\t{\n\t\t\t\tjj = AC_idx[j];\n\t\t\t\txiB[i] -= A[jj*NVMAX + ii] * xiC[j];\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* III) DETERMINE CONSTRAINT/BOUND TO BE REMOVED. */\n\treal_t y_min = INFTY * INFTY;\n\tint y_min_number = -1;\n\tBooleanType y_min_isBound = BT_FALSE;\n\n\t/* 1) Constraints. */\n\tfor( i=0; i<nAC; ++i )\n\t{\n\t\tii = AC_idx[i];\n\n\t\tif ( constraints.getStatus( ii ) == ST_LOWER )\n\t\t{\n\t\t\tif ( ( xiC[i] > ZERO ) && ( y[nV+ii] >= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[nV+ii]/xiC[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[nV+ii]/xiC[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( ( xiC[i] < -ZERO ) && ( y[nV+ii] <= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[nV+ii]/xiC[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[nV+ii]/xiC[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* 2) Bounds. */\n\tfor( i=0; i<nFX; ++i )\n\t{\n\t\tii = FX_idx[i];\n\n\t\tif ( bounds.getStatus( ii ) == ST_LOWER )\n\t\t{\n\t\t\tif ( ( xiB[i] > ZERO ) && ( y[ii] >= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[ii]/xiB[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[ii]/xiB[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t\ty_min_isBound = BT_TRUE;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( ( xiB[i] < -ZERO ) && ( y[ii] <= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[ii]/xiB[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[ii]/xiB[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t\ty_min_isBound = BT_TRUE;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* setup output preferences */\n\t#ifdef PC_DEBUG\n\tchar messageString[80];\n\tVisibilityStatus visibilityStatus;\n\n\tif ( printlevel == PL_HIGH )\n\t\tvisibilityStatus = VS_VISIBLE;\n\telse\n\t\tvisibilityStatus = VS_HIDDEN;\n\t#endif\n\n\n\t/* IV) REMOVE CONSTRAINT/BOUND FOR RESOLVING LINEAR DEPENDENCE: */\n\tif ( y_min_number >= 0 )\n\t{\n\t\t/* 1) Check for cycling due to infeasibility. */\n\t\tif ( ( cyclingManager.getCyclingStatus( number,BT_FALSE ) == CYC_PREV_REMOVED ) &&\n\t\t\t ( cyclingManager.getCyclingStatus( y_min_number,y_min_isBound ) == CYC_PREV_ADDED ) )\n\t\t{\n\t\t\tinfeasible = BT_TRUE;\n\n\t\t\treturn THROWERROR( RET_ENSURELI_FAILED_CYCLING );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* set cycling data */\n\t\t\tcyclingManager.clearCyclingData( );\n\t\t\tcyclingManager.setCyclingStatus( number,BT_FALSE, CYC_PREV_ADDED );\n\t\t\tcyclingManager.setCyclingStatus( y_min_number,y_min_isBound, CYC_PREV_REMOVED );\n\t\t}\n\n\t\t/* 2) Update Lagrange multiplier... */\n\t\tfor( i=0; i<nAC; ++i )\n\t\t{\n\t\t\tii = AC_idx[i];\n\t\t\ty[nV+ii] -= y_min * xiC[i];\n\t\t}\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\t\t\ty[ii] -= y_min * xiB[i];\n\t\t}\n\n\t\t/* ... also for newly active constraint... */\n\t\tif ( C_status == ST_LOWER )\n\t\t\ty[nV+number] = y_min;\n\t\telse\n\t\t\ty[nV+number] = -y_min;\n\n\t\t/* ... and for constraint to be removed. */\n\t\tif ( y_min_isBound == BT_TRUE )\n\t\t{\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"bound no. %d.\",y_min_number );\n\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t#endif\n\n\t\t\tif ( removeBound( y_min_number,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\ty[y_min_number] = 0.0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"constraint no. %d.\",y_min_number );\n\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t#endif\n\n\t\t\tif ( removeConstraint( y_min_number,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\ty[nV+y_min_number] = 0.0;\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* no constraint/bound can be removed => QP is infeasible! */\n\t\tinfeasible = BT_TRUE;\n\n\t\treturn THROWERROR( RET_ENSURELI_FAILED_NOINDEX );\n\t}\n\n\treturn getGlobalMessageHandler( )->throwInfo( RET_LI_RESOLVED,0,__FUNCTION__,__FILE__,__LINE__,VS_HIDDEN );\n}\n\n\n\n/*\n *\ta d d B o u n d\n */\nreturnValue QProblem::addBound(\tint number, SubjectToStatus B_status,\n\t\t\t\t\t\t\t\tBooleanType updateCholesky\n\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii;\n\n\t/* consistency checks */\n\tif ( bounds.getStatus( number ) != ST_INACTIVE )\n\t\treturn THROWERROR( RET_BOUND_ALREADY_ACTIVE );\n\n\tif ( getNFR( ) == bounds.getNUV( ) )\n\t\treturn THROWERROR( RET_ALL_BOUNDS_ACTIVE );\n\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )    ||\n\t\t ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n \t\t ( getStatus( ) == QPS_SOLVED )            )\n\t{\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\n\n\t/* I) ENSURE LINEAR INDEPENDENCE OF THE WORKING SET,\n\t *    i.e. remove a constraint or bound if linear dependence occurs. */\n\t/* check for LI only if Cholesky decomposition shall be updated! */\n\tif ( updateCholesky == BT_TRUE )\n\t{\n\t\treturnValue ensureLIreturnvalue = addBound_ensureLI( number,B_status );\n\n\t\tswitch ( ensureLIreturnvalue )\n\t\t{\n\t\t\tcase SUCCESSFUL_RETURN:\n\t\t\t\tbreak;\n\n\t\t\tcase RET_LI_RESOLVED:\n\t\t\t\tbreak;\n\n\t\t\tcase RET_ENSURELI_FAILED_NOINDEX:\n\t\t\t\treturn THROWERROR( RET_ADDBOUND_FAILED_INFEASIBILITY );\n\n\t\t\tcase RET_ENSURELI_FAILED_CYCLING:\n\t\t\t\treturn THROWERROR( RET_ADDBOUND_FAILED_INFEASIBILITY );\n\n\t\t\tdefault:\n\t\t\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\t\t}\n\t}\n\n\n\t/* some definitions */\n\tint nFR = getNFR( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\tint tcol = sizeT - nAC;\n\n\n\t/* I) SWAP INDEXLIST OF FREE VARIABLES:\n\t *    move the variable to be fixed to the end of the list of free variables. */\n\tint lastfreenumber = bounds.getFree( )->getLastNumber( );\n\tif ( lastfreenumber != number )\n\t\tif ( bounds.swapFree( number,lastfreenumber ) != SUCCESSFUL_RETURN )\n\t\t\tTHROWERROR( RET_ADDBOUND_FAILED );\n\n\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ADDBOUND_FAILED );\n\n\treal_t w[NVMAX];\n\n\n\t/* II) ADD NEW ACTIVE BOUND TO TOP OF MATRIX T: */\n\t/* 1) add row [wZ wY] = [Z Y](number) at the top of T: assign w */\n\tfor( i=0; i<nFR; ++i )\n\t\tw[i] = Q[FR_idx[nFR-1]*NVMAX + i];\n\n\n\t/* 2) Use column-wise Givens rotations to restore reverse triangular form\n\t *    of the first row of T, simultanenous change of Q (i.e. Z) and R. */\n\treal_t c, s;\n\n\tfor( j=0; j<nZ-1; ++j )\n\t{\n\t\tcomputeGivens( w[j+1],w[j], w[j+1],w[j],c,s );\n\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\t\t\tapplyGivens( c,s,Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j], Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j] );\n\t\t}\n\n\t\tif ( ( updateCholesky == BT_TRUE ) && ( hessianType != HST_IDENTITY ) )\n\t\t{\n\t\t\tfor( i=0; i<=j+1; ++i )\n\t\t\t\tapplyGivens( c,s,R[i*NVMAX + 1+j],R[i*NVMAX + j], R[i*NVMAX + 1+j],R[i*NVMAX + j] );\n\t\t}\n\t}\n\n\n\tif ( nAC > 0 )\t  /* ( nAC == 0 ) <=> ( nZ == nFR ) <=> Y and T are empty => nothing to do */\n\t{\n\t\t/* store new column a in a temporary vector instead of shifting T one column to the left */\n\t\treal_t tmp[NCMAX_ALLOC];\n\t\tfor( i=0; i<nAC; ++i )\n\t\t\ttmp[i] = 0.0;\n\n\t\t{\n\t\t\tj = nZ-1;\n\n\t\t\tcomputeGivens( w[j+1],w[j], w[j+1],w[j],c,s );\n\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\t\t\t\tapplyGivens( c,s,Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j], Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j] );\n\t\t\t}\n\n\t\t\tapplyGivens( c,s,T[(nAC-1)*NVMAX + tcol],tmp[nAC-1], tmp[nAC-1],T[(nAC-1)*NVMAX + tcol] );\n\t\t}\n\n\t\tfor( j=nZ; j<nFR-1; ++j )\n\t\t{\n\t\t\tcomputeGivens( w[j+1],w[j], w[j+1],w[j],c,s );\n\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\t\t\t\tapplyGivens( c,s,Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j], Q[ii*NVMAX + 1+j],Q[ii*NVMAX + j] );\n\t\t\t}\n\n\t\t\tfor( i=(nFR-2-j); i<nAC; ++i )\n\t\t\t\tapplyGivens( c,s,T[i*NVMAX + 1+tcol-nZ+j],tmp[i], tmp[i],T[i*NVMAX + 1+tcol-nZ+j] );\n\t\t}\n\n\t}\n\n\n\tif ( ( updateCholesky == BT_TRUE ) && ( hessianType != HST_IDENTITY ) )\n\t{\n\t\t/* III) RESTORE TRIANGULAR FORM OF R:\n\t\t *      use row-wise Givens rotations to restore upper triangular form of R */\n\t\tfor( i=0; i<nZ-1; ++i )\n\t\t{\n\t\t\tcomputeGivens( R[i*NVMAX + i],R[(1+i)*NVMAX + i], R[i*NVMAX + i],R[(1+i)*NVMAX + i],c,s );\n\n\t\t\tfor( j=(1+i); j<nZ-1; ++j ) /* last column of R is thrown away */\n\t\t\t\tapplyGivens( c,s,R[i*NVMAX + j],R[(1+i)*NVMAX + j], R[i*NVMAX + j],R[(1+i)*NVMAX + j] );\n\t\t}\n\t\t/* last column of R is thrown away */\n\t\tfor( i=0; i<nZ; ++i )\n\t\t\tR[i*NVMAX + nZ-1] = 0.0;\n\t}\n\n\n\t/* IV) UPDATE INDICES */\n\tif ( bounds.moveFreeToFixed( number,B_status ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ADDBOUND_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ta d d B o u n d _ c h e c k L I\n */\nreturnValue QProblem::addBound_checkLI( int number )\n{\n\tint i;\n\n\t/* some definitions */\n\tint nZ  = getNZ( );\n\n\t/* Check if constraint <number> is linearly independent from the\n\t   the active ones (<=> is element of null space of Afr). */\n\tfor( i=0; i<nZ; ++i )\n\t{\n\t\tif ( getAbs( Q[number*NVMAX + i] ) > EPS )\n\t\t\treturn RET_LINEARLY_INDEPENDENT;\n\t}\n\n\treturn RET_LINEARLY_DEPENDENT;\n}\n\n\n/*\n *\ta d d B o u n d _ e n s u r e L I\n */\nreturnValue QProblem::addBound_ensureLI( int number, SubjectToStatus B_status )\n{\n\tint i, j, ii, jj;\n\tint nV  = getNV( );\n\tint nFX = getNFX( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\n\t/* I) Check if new constraint is linearly independent from the active ones. */\n\treturnValue returnvalueCheckLI = addBound_checkLI( number );\n\n\tif ( returnvalueCheckLI == RET_LINEARLY_INDEPENDENT )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n \t/* II) NEW BOUND IS LINEARLY DEPENDENT: */\n\t/* 1) Determine coefficients of linear combination,\n\t *    cf. M.J. Best. Applied Mathematics and Parallel Computing, chapter:\n\t *    An Algorithm for the Solution of the Parametric Quadratic Programming\n\t *    Problem, pages 57-76. Physica-Verlag, Heidelberg, 1996. */\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\tint FX_idx[NVMAX];\n\tif ( bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\tint AC_idx[NCMAX_ALLOC];\n\tif ( constraints.getActive( )->getNumberArray( AC_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ENSURELI_FAILED );\n\n\treal_t xiC[NCMAX_ALLOC];\n\treal_t xiC_TMP[NCMAX_ALLOC];\n\treal_t xiB[NVMAX];\n\n\t/* 2) Calculate xiC. */\n\tif ( nAC > 0 )\n\t{\n\t\tif ( B_status == ST_LOWER )\n\t\t{\n\t\t\tfor( i=0; i<nAC; ++i )\n\t\t\t\txiC_TMP[i] = Q[number*NVMAX + nZ+i];\n\t\t}\n\t\telse\n\t\t{\n\t\t\tfor( i=0; i<nAC; ++i )\n\t\t\t\txiC_TMP[i] = -Q[number*NVMAX + nZ+i];\n\t\t}\n\n\t\tif ( backsolveT( xiC_TMP, BT_TRUE, xiC ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_ENSURELI_FAILED_TQ );\n\t}\n\n\t/* 3) Calculate xiB. */\n\tfor( i=0; i<nFX; ++i )\n\t{\n\t\tii = FX_idx[i];\n\n\t\txiB[i] = 0.0;\n\t\tfor( j=0; j<nAC; ++j )\n\t\t{\n\t\t\tjj = AC_idx[j];\n\t\t\txiB[i] -= A[jj*NVMAX + ii] * xiC[j];\n\t\t}\n\t}\n\n\n\t/* III) DETERMINE CONSTRAINT/BOUND TO BE REMOVED. */\n\treal_t y_min = INFTY * INFTY;\n\tint y_min_number = -1;\n\tBooleanType y_min_isBound = BT_FALSE;\n\n\t/* 1) Constraints. */\n\tfor( i=0; i<nAC; ++i )\n\t{\n\t\tii = AC_idx[i];\n\n\t\tif ( constraints.getStatus( ii ) == ST_LOWER )\n\t\t{\n\t\t\tif ( ( xiC[i] > ZERO ) && ( y[nV+ii] >= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[nV+ii]/xiC[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[nV+ii]/xiC[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( ( xiC[i] < -ZERO ) && ( y[nV+ii] <= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[nV+ii]/xiC[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[nV+ii]/xiC[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* 2) Bounds. */\n\tfor( i=0; i<nFX; ++i )\n\t{\n\t\tii = FX_idx[i];\n\n\t\tif ( bounds.getStatus( ii ) == ST_LOWER )\n\t\t{\n\t\t\tif ( ( xiB[i] > ZERO ) && ( y[ii] >= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[ii]/xiB[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[ii]/xiB[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t\ty_min_isBound = BT_TRUE;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( ( xiB[i] < -ZERO ) && ( y[ii] <= 0.0 ) )\n\t\t\t{\n\t\t\t\tif ( y[ii]/xiB[i] < y_min )\n\t\t\t\t{\n\t\t\t\t\ty_min = y[ii]/xiB[i];\n\t\t\t\t\ty_min_number = ii;\n\t\t\t\t\ty_min_isBound = BT_TRUE;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* setup output preferences */\n\t#ifdef PC_DEBUG\n\tchar messageString[80];\n\tVisibilityStatus visibilityStatus;\n\n\tif ( printlevel == PL_HIGH )\n\t\tvisibilityStatus = VS_VISIBLE;\n\telse\n\t\tvisibilityStatus = VS_HIDDEN;\n\t#endif\n\n\n\t/* IV) REMOVE CONSTRAINT/BOUND FOR RESOLVING LINEAR DEPENDENCE: */\n\tif ( y_min_number >= 0 )\n\t{\n\t\t/* 1) Check for cycling due to infeasibility. */\n\t\tif ( ( cyclingManager.getCyclingStatus( number,BT_TRUE ) == CYC_PREV_REMOVED ) &&\n\t\t\t ( cyclingManager.getCyclingStatus( y_min_number,y_min_isBound ) == CYC_PREV_ADDED ) )\n\t\t{\n\t\t\tinfeasible = BT_TRUE;\n\n\t\t\treturn THROWERROR( RET_ENSURELI_FAILED_CYCLING );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* set cycling data */\n\t\t\tcyclingManager.clearCyclingData( );\n\t\t\tcyclingManager.setCyclingStatus( number,BT_TRUE, CYC_PREV_ADDED );\n\t\t\tcyclingManager.setCyclingStatus( y_min_number,y_min_isBound, CYC_PREV_REMOVED );\n\t\t}\n\n\n\t\t/* 2) Update Lagrange multiplier... */\n\t\tfor( i=0; i<nAC; ++i )\n\t\t{\n\t\t\tii = AC_idx[i];\n\t\t\ty[nV+ii] -= y_min * xiC[i];\n\t\t}\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\t\t\ty[ii] -= y_min * xiB[i];\n\t\t}\n\n\t\t/* ... also for newly active bound ... */\n\t\tif ( B_status == ST_LOWER )\n\t\t\ty[number] = y_min;\n\t\telse\n\t\t\ty[number] = -y_min;\n\n\t\t/* ... and for bound to be removed. */\n\t\tif ( y_min_isBound == BT_TRUE )\n\t\t{\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"bound no. %d.\",y_min_number );\n\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t#endif\n\n\t\t\tif ( removeBound( y_min_number,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\ty[y_min_number] = 0.0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"constraint no. %d.\",y_min_number );\n\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t#endif\n\n\t\t\tif ( removeConstraint( y_min_number,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\ty[nV+y_min_number] = 0.0;\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* no constraint/bound can be removed => QP is infeasible! */\n\t\tinfeasible = BT_TRUE;\n\n\t\treturn THROWERROR( RET_ENSURELI_FAILED_NOINDEX );\n\t}\n\n\treturn getGlobalMessageHandler( )->throwInfo( RET_LI_RESOLVED,0,__FUNCTION__,__FILE__,__LINE__,VS_HIDDEN );\n}\n\n\n\n/*\n *\tr e m o v e C o n s t r a i n t\n */\nreturnValue QProblem::removeConstraint(\tint number,\n\t\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\n\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii, jj;\n\n\t/* consistency check */\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )    ||\n\t\t ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n \t\t ( getStatus( ) == QPS_SOLVED )            )\n\t{\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\n\t/* some definitions */\n\tint nFR = getNFR( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\tint tcol = sizeT - nAC;\n\tint number_idx = constraints.getActive( )->getIndex( number );\n\n\n\t/* consistency checks */\n\tif ( constraints.getStatus( number ) == ST_INACTIVE )\n\t\treturn THROWERROR( RET_CONSTRAINT_NOT_ACTIVE );\n\n\tif ( ( number_idx < 0 ) || ( number_idx >= nAC ) )\n\t\treturn THROWERROR( RET_CONSTRAINT_NOT_ACTIVE );\n\n\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVECONSTRAINT_FAILED );\n\n\n\t/* I) REMOVE <number>th ROW FROM T,\n\t *    i.e. shift rows number+1 through nAC  upwards (instead of the actual\n\t *    constraint number its corresponding index within matrix A is used). */\n\tif ( number_idx < nAC-1 )\n\t{\n\t\tfor( i=(number_idx+1); i<nAC; ++i )\n\t\t\tfor( j=(nAC-i-1); j<nAC; ++j )\n\t\t\t\tT[(i-1)*NVMAX + tcol+j] = T[i*NVMAX + tcol+j];\n\t\t/* gimmick: write zeros into the last row of T */\n\t\tfor( j=0; j<nAC; ++j )\n\t\t\tT[(nAC-1)*NVMAX + tcol+j] = 0.0;\n\n\n\t\t/* II) RESTORE TRIANGULAR FORM OF T,\n\t\t *     use column-wise Givens rotations to restore reverse triangular form\n\t\t *     of T simultanenous change of Q (i.e. Y). */\n\t\treal_t c, s;\n\n\t\tfor( j=(nAC-2-number_idx); j>=0; --j )\n\t\t{\n\t\t\tcomputeGivens( T[(nAC-2-j)*NVMAX + tcol+1+j],T[(nAC-2-j)*NVMAX + tcol+j], T[(nAC-2-j)*NVMAX + tcol+1+j],T[(nAC-2-j)*NVMAX + tcol+j],c,s );\n\n\t\t\tfor( i=(nAC-j-1); i<(nAC-1); ++i )\n\t\t\t\tapplyGivens( c,s,T[i*NVMAX + tcol+1+j],T[i*NVMAX + tcol+j], T[i*NVMAX + tcol+1+j],T[i*NVMAX + tcol+j] );\n\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\t\t\t\tapplyGivens( c,s,Q[ii*NVMAX + nZ+1+j],Q[ii*NVMAX + nZ+j], Q[ii*NVMAX + nZ+1+j],Q[ii*NVMAX + nZ+j] );\n\t\t\t}\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* gimmick: write zeros into the last row of T */\n\t\tfor( j=0; j<nAC; ++j )\n\t\t\tT[(nAC-1)*NVMAX + tcol+j] = 0.0;\n\t}\n\n\n\tif ( ( updateCholesky == BT_TRUE ) && ( hessianType != HST_IDENTITY ) )\n\t{\n\t\t/* III) UPDATE CHOLESKY DECOMPOSITION,\n\t\t *      calculate new additional column (i.e. [r sqrt(rho2)]')\n\t\t *      of the Cholesky factor R. */\n\t\treal_t Hz[NVMAX];\n\t\tfor ( i=0; i<nFR; ++i )\n\t\t\tHz[i] = 0.0;\n\t\treal_t rho2 = 0.0;\n\n\t\t/* 1) Calculate Hz = H*z, where z is the new rightmost column of Z\n\t\t *    (i.e. the old leftmost column of Y).  */\n\t\tfor( j=0; j<nFR; ++j )\n\t\t{\n\t\t\tjj = FR_idx[j];\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\tHz[i] += H[jj*NVMAX + FR_idx[i]] * Q[jj*NVMAX + nZ];\n\t\t}\n\n\t\tif ( nZ > 0 )\n\t\t{\n\t\t\treal_t ZHz[NVMAX];\n\t\t\tfor ( i=0; i<nZ; ++i )\n\t\t\t\tZHz[i] = 0.0;\n\t\t\treal_t r[NVMAX];\n\n\t\t\t/* 2) Calculate ZHz = Z'*Hz (old Z). */\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\n\t\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\t\tZHz[i] += Q[jj*NVMAX + i] * Hz[j];\n\t\t\t}\n\n\t\t\t/* 3) Calculate r = R^-T * ZHz. */\n\t\t\tif ( backsolveR( ZHz,BT_TRUE,r ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_REMOVECONSTRAINT_FAILED );\n\n\t\t\t/* 4) Calculate rho2 = rho^2 = z'*Hz - r'*r\n\t\t\t *    and store r into R. */\n\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t{\n\t\t\t\trho2 -= r[i]*r[i];\n\t\t\t\tR[i*NVMAX + nZ] = r[i];\n\t\t\t}\n\t\t}\n\n\t\tfor( j=0; j<nFR; ++j )\n\t\t\trho2 += Q[FR_idx[j]*NVMAX + nZ] * Hz[j];\n\n\t\t/* 5) Store rho into R. */\n\t\tif ( rho2 > 0.0 )\n\t\t\tR[nZ*NVMAX + nZ] = sqrt( rho2 );\n\t\telse\n\t\t{\n\t\t\thessianType = HST_SEMIDEF;\n\t\t\treturn THROWERROR( RET_HESSIAN_NOT_SPD );\n\t\t}\n\t}\n\n\t/* IV) UPDATE INDICES */\n\tif ( constraints.moveActiveToInactive( number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVECONSTRAINT_FAILED );\n\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tr e m o v e B o u n d\n */\nreturnValue QProblem::removeBound(\tint number,\n\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii, jj;\n\n\t/* consistency checks */\n\tif ( bounds.getStatus( number ) == ST_INACTIVE )\n\t\treturn THROWERROR( RET_BOUND_NOT_ACTIVE );\n\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )    ||\n\t\t ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n \t\t ( getStatus( ) == QPS_SOLVED )            )\n\t{\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\n\t/* some definitions */\n\tint nFR = getNFR( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\tint tcol = sizeT - nAC;\n\n\n\t/* I) UPDATE INDICES */\n\tif ( bounds.moveFixedToFree( number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\t/* I) APPEND <nFR+1>th UNITY VECOTR TO Q. */\n\tint nnFRp1 = FR_idx[nFR];\n\tfor( i=0; i<nFR; ++i )\n\t{\n\t\tii = FR_idx[i];\n\t\tQ[ii*NVMAX + nFR] = 0.0;\n\t\tQ[nnFRp1*NVMAX + i] = 0.0;\n\t}\n\tQ[nnFRp1*NVMAX + nFR] = 1.0;\n\n\tif ( nAC > 0 )\n\t{\n\t\t/* store new column a in a temporary vector instead of shifting T one column to the left and appending a */\n\t\tint AC_idx[NCMAX_ALLOC];\n\t\tif ( constraints.getActive( )->getNumberArray( AC_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\t\treal_t tmp[NCMAX_ALLOC];\n\t\tfor( i=0; i<nAC; ++i )\n\t\t{\n\t\t\tii = AC_idx[i];\n\t\t\ttmp[i] =  A[ii*NVMAX + number];\n\t\t}\n\n\n\t\t/* II) RESTORE TRIANGULAR FORM OF T,\n\t\t *     use column-wise Givens rotations to restore reverse triangular form\n\t\t *     of T = [T A(:,number)], simultanenous change of Q (i.e. Y and Z). */\n\t\treal_t c, s;\n\n\t\tfor( j=(nAC-1); j>=0; --j )\n\t\t{\n\t\t\tcomputeGivens( tmp[nAC-1-j],T[(nAC-1-j)*NVMAX + tcol+j],T[(nAC-1-j)*NVMAX + tcol+j],tmp[nAC-1-j],c,s );\n\n\t\t\tfor( i=(nAC-j); i<nAC; ++i )\n\t\t\t\tapplyGivens( c,s,tmp[i],T[i*NVMAX + tcol+j],T[i*NVMAX + tcol+j],tmp[i] );\n\n\t\t\tfor( i=0; i<=nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\t\t\t\t/* nZ+1+nAC = nFR+1  /  nZ+(1) = nZ+1 */\n\t\t\t\tapplyGivens( c,s,Q[ii*NVMAX + nZ+1+j],Q[ii*NVMAX + nZ+j],Q[ii*NVMAX + nZ+1+j],Q[ii*NVMAX + nZ+j] );\n\t\t\t}\n\t\t}\n\t}\n\n\n\tif ( ( updateCholesky == BT_TRUE ) && ( hessianType != HST_IDENTITY ) )\n\t{\n\t\t/* III) UPDATE CHOLESKY DECOMPOSITION,\n\t\t *      calculate new additional column (i.e. [r sqrt(rho2)]')\n\t\t *      of the Cholesky factor R: */\n\t\treal_t z2 = Q[nnFRp1*NVMAX + nZ];\n\t\treal_t rho2 = H[nnFRp1*NVMAX + nnFRp1]*z2*z2; /* rho2 = h2*z2*z2 */\n\n\t\tif ( nFR > 0 )\n\t\t{\n\t\t\treal_t Hz[NVMAX];\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\tHz[i] = 0.0;\n\t\t\t/* 1) Calculate R'*r = Zfr'*Hfr*z1 + z2*Zfr'*h1 =: Zfr'*Hz + z2*Zfr'*h1 =: rhs and\n\t\t\t *    rho2 = z1'*Hfr*z1 + 2*z2*h1'*z1 + h2*z2^2 - r'*r =: z1'*Hz + 2*z2*h1'*z1 + h2*z2^2 - r'r */\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\t/*\t\t\t   H * z1 */\n\t\t\t\t\tHz[i] += H[jj*NVMAX + ii] * Q[jj*NVMAX + nZ];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif ( nZ > 0 )\n\t\t\t{\n\t\t\t\treal_t r[NVMAX];\n\t\t\t\treal_t rhs[NVMAX];\n\t\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\t\trhs[i] = 0.0;\n\n\t\t\t\t/* 2) Calculate rhs. */\n\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\t\t\t\t\t\t\t/* Zfr' * ( Hz + z2*h1 ) */\n\t\t\t\t\t\trhs[i] += Q[jj*NVMAX + i] * ( Hz[j] + z2 * H[nnFRp1*NVMAX + jj] );\n\t\t\t\t}\n\n\t\t\t\t/* 3) Calculate r = R^-T * rhs. */\n\t\t\t\tif ( backsolveR( rhs,BT_TRUE,BT_TRUE,r ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\t\t\t\t/* 4) Calculate rho2 = rho^2 = z'*Hz - r'*r\n\t\t\t\t *    and store r into R. */\n\t\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\t{\n\t\t\t\t\trho2 -= r[i]*r[i];\n\t\t\t\t\tR[i*NVMAX + nZ] = r[i];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\t\t/* z1' * ( Hz + 2*z2*h1 ) */\n\t\t\t\trho2 += Q[jj*NVMAX + nZ] * ( Hz[j] + 2.0*z2*H[nnFRp1*NVMAX + jj] );\n\t\t\t}\n\t\t}\n\n\n\t\t/* 5) Store rho into R. */\n\t\tif ( rho2 > 0.0 )\n\t\t\tR[nZ*NVMAX + nZ] = sqrt( rho2 );\n\t\telse\n\t\t{\n\t\t\thessianType = HST_SEMIDEF;\n\t\t\treturn THROWERROR( RET_HESSIAN_NOT_SPD );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tb a c k s o l v e R  (CODE DUPLICATE OF QProblemB CLASS!!!)\n */\nreturnValue QProblem::backsolveR(\tconst real_t* const b, BooleanType transposed,\n\t\t\t\t\t\t\t\t\treal_t* const a\n\t\t\t\t\t\t\t\t\t)\n{\n\t/* Call standard backsolve procedure (i.e. removingBound == BT_FALSE). */\n\treturn backsolveR( b,transposed,BT_FALSE,a );\n}\n\n\n/*\n *\tb a c k s o l v e R  (CODE DUPLICATE OF QProblemB CLASS!!!)\n */\nreturnValue QProblem::backsolveR(\tconst real_t* const b, BooleanType transposed,\n\t\t\t\t\t\t\t\t\tBooleanType removingBound,\n\t\t\t\t\t\t\t\t\treal_t* const a\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tint nR = getNZ( );\n\n\treal_t sum;\n\n\t/* if backsolve is called while removing a bound, reduce nZ by one. */\n\tif ( removingBound == BT_TRUE )\n\t\t--nR;\n\n\t/* nothing to do */\n\tif ( nR <= 0 )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n\t/* Solve Ra = b, where R might be transposed. */\n\tif ( transposed == BT_FALSE )\n\t{\n\t\t/* solve Ra = b */\n\t\tfor( i=(nR-1); i>=0; --i )\n\t\t{\n\t\t\tsum = b[i];\n\t\t\tfor( j=(i+1); j<nR; ++j )\n\t\t\t\tsum -= R[i*NVMAX + j] * a[j];\n\n\t\t\tif ( getAbs( R[i*NVMAX + i] ) > ZERO )\n\t\t\t\ta[i] = sum / R[i*NVMAX + i];\n\t\t\telse\n\t\t\t\treturn THROWERROR( RET_DIV_BY_ZERO );\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* solve R^T*a = b */\n\t\tfor( i=0; i<nR; ++i )\n\t\t{\n\t\t\tsum = b[i];\n\n\t\t\tfor( j=0; j<i; ++j )\n\t\t\t\tsum -= R[j*NVMAX + i] * a[j];\n\n\t\t\tif ( getAbs( R[i*NVMAX + i] ) > ZERO )\n\t\t\t\ta[i] = sum / R[i*NVMAX + i];\n\t\t\telse\n\t\t\t\treturn THROWERROR( RET_DIV_BY_ZERO );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\tb a c k s o l v e T\n */\nreturnValue QProblem::backsolveT( const real_t* const b, BooleanType transposed, real_t* const a )\n{\n\tint i, j;\n\tint nT = getNAC( );\n\tint tcol = sizeT - nT;\n\n\treal_t sum;\n\n\t/* nothing to do */\n\tif ( nT <= 0 )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n\t/* Solve Ta = b, where T might be transposed. */\n\tif ( transposed == BT_FALSE )\n\t{\n\t\t/* solve Ta = b */\n\t\tfor( i=0; i<nT; ++i )\n\t\t{\n\t\t\tsum = b[i];\n\t\t\tfor( j=0; j<i; ++j )\n\t\t\t\tsum -= T[i*NVMAX + sizeT-1-j] * a[nT-1-j];\n\n\t\t\tif ( getAbs( T[i*NVMAX + sizeT-1-i] ) > ZERO )\n\t\t\t\ta[nT-1-i] = sum / T[i*NVMAX + sizeT-1-i];\n\t\t\telse\n\t\t\t\treturn THROWERROR( RET_DIV_BY_ZERO );\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* solve T^T*a = b */\n\t\tfor( i=0; i<nT; ++i )\n\t\t{\n\t\t\tsum = b[i];\n\t\t\tfor( j=0; j<i; ++j )\n\t\t\t\tsum -= T[(nT-1-j)*NVMAX + tcol+i] * a[nT-1-j];\n\n\t\t\tif ( getAbs( T[(nT-1-i)*NVMAX + tcol+i] ) > ZERO )\n\t\t\t\ta[nT-1-i] = sum / T[(nT-1-i)*NVMAX + tcol+i];\n\t\t\telse\n\t\t\t\treturn THROWERROR( RET_DIV_BY_ZERO );\n\t\t}\n\t}\n\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ d e t e r m i n e D a t a S h i f t\n */\nreturnValue QProblem::hotstart_determineDataShift(  const int* const FX_idx, const int* const AC_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const g_new, const real_t* const lbA_new, const real_t* const ubA_new,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const lb_new, const real_t* const ub_new,\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_g, real_t* const delta_lbA, real_t* const delta_ubA,\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_lb, real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType& Delta_bC_isZero, BooleanType& Delta_bB_isZero\n\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, ii;\n\tint nC  = getNC( );\n\tint nAC = getNAC( );\n\n\n\t/* I) DETERMINE DATA SHIFT FOR BOUNDS */\n\tQProblemB::hotstart_determineDataShift( FX_idx,g_new,lb_new,ub_new, delta_g,delta_lb,delta_ub, Delta_bB_isZero );\n\n\n\t/* II) DETERMINE DATA SHIFT FOR CONSTRAINTS */\n\t/* 1) Calculate shift directions. */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\t/* if lower constraints' bounds do not exist, shift them to -infinity */\n\t\tif ( lbA_new != 0 )\n\t\t\tdelta_lbA[i] = lbA_new[i] - lbA[i];\n\t\telse\n\t\t\tdelta_lbA[i] = -INFTY - lbA[i];\n\t}\n\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\t/* if upper constraints' bounds do not exist, shift them to infinity */\n\t\tif ( ubA_new != 0 )\n\t\t\tdelta_ubA[i] = ubA_new[i] - ubA[i];\n\t\telse\n\t\t\tdelta_ubA[i] = INFTY - ubA[i];\n\t}\n\n\t/* 2) Determine if active constraints' bounds are to be shifted. */\n\tDelta_bC_isZero = BT_TRUE;\n\n\tfor ( i=0; i<nAC; ++i )\n\t{\n\t\tii = AC_idx[i];\n\n\t\tif ( ( getAbs( delta_lbA[ii] ) > EPS ) || ( getAbs( delta_ubA[ii] ) > EPS ) )\n\t\t{\n\t\t\tDelta_bC_isZero = BT_FALSE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ d e t e r m i n e S t e p D i r e c t i o n\n */\nreturnValue QProblem::hotstart_determineStepDirection(\tconst int* const FR_idx, const int* const FX_idx, const int* const AC_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g, const real_t* const delta_lbA, const real_t* const delta_ubA,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType Delta_bC_isZero, BooleanType Delta_bB_isZero,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_xFX, real_t* const delta_xFR,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_yAC, real_t* const delta_yFX\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii, jj;\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\tint nAC = getNAC( );\n\tint nZ  = getNZ( );\n\n\t/* initialise auxiliary vectors */\n\treal_t HMX_delta_xFX[NVMAX];\n\treal_t YFR_delta_xFRy[NVMAX];\n\treal_t ZFR_delta_xFRz[NVMAX];\n\treal_t HFR_YFR_delta_xFRy[NVMAX];\n\tfor( i=0; i<nFR; ++i )\n\t{\n\t\tdelta_xFR[i] = 0.0;\n\t\tHMX_delta_xFX[i] = 0.0;\n\t\tYFR_delta_xFRy[i] = 0.0;\n\t\tZFR_delta_xFRz[i] = 0.0;\n\t\tHFR_YFR_delta_xFRy[i] = 0.0;\n\t}\n\n\treal_t delta_xFRy[NCMAX_ALLOC];\n\treal_t delta_xFRz[NVMAX];\n\tfor( i=0; i<nZ; ++i )\n\t\tdelta_xFRz[i] = 0.0;\n\n\n\t/* I) DETERMINE delta_xFX */\n\tif ( nFX > 0 )\n\t{\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\n\t\t\tif ( bounds.getStatus( ii ) == ST_LOWER )\n\t\t\t\tdelta_xFX[i] = delta_lb[ii];\n\t\t\telse\n\t\t\t\tdelta_xFX[i] = delta_ub[ii];\n\t\t}\n\t}\n\n\t/* II) DETERMINE delta_xFR */\n\tif ( nFR > 0 )\n\t{\n\t\t/* 1) Determine delta_xFRy. */\n\t\tif ( nAC > 0 )\n\t\t{\n\t\t\tif ( ( Delta_bC_isZero == BT_TRUE ) && ( Delta_bB_isZero == BT_TRUE ) )\n\t\t\t{\n\t\t\t\tfor( i=0; i<nAC; ++i )\n\t\t\t\t\tdelta_xFRy[i] = 0.0;\n\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t\tdelta_xFR[i] = 0.0;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* auxillary variable */\n\t\t\t\treal_t delta_xFRy_TMP[NCMAX_ALLOC];\n\n\t\t\t\tfor( i=0; i<nAC; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = AC_idx[i];\n\n\t\t\t\t\tif ( constraints.getStatus( ii ) == ST_LOWER )\n\t\t\t\t\t\tdelta_xFRy_TMP[i] = delta_lbA[ii];\n\t\t\t\t\telse\n\t\t\t\t\t\tdelta_xFRy_TMP[i] = delta_ubA[ii];\n\n\t\t\t\t\tif ( Delta_bB_isZero == BT_FALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tfor( j=0; j<nFX; ++j )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tjj = FX_idx[j];\n\t\t\t\t\t\t\tdelta_xFRy_TMP[i] -= A[ii*NVMAX + jj] * delta_xFX[j];\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif ( backsolveT( delta_xFRy_TMP, BT_FALSE, delta_xFRy ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_STEPDIRECTION_FAILED_TQ );\n\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tfor( j=0; j<nAC; ++j )\n\t\t\t\t\t\tYFR_delta_xFRy[i] += Q[ii*NVMAX + nZ+j] * delta_xFRy[j];\n\n\t\t\t\t\t/* delta_xFR = YFR*delta_xFRy (+ ZFR*delta_xFRz) */\n\t\t\t\t\tdelta_xFR[i] = YFR_delta_xFRy[i];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* 2) Determine delta_xFRz. */\n\t\tif ( hessianType == HST_IDENTITY )\n\t\t{\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\t\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\t\tdelta_xFRz[i] -= Q[jj*NVMAX + i] * delta_g[jj];\n\t\t\t}\n\n\t\t\tif ( nZ > 0 )\n\t\t\t{\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tfor( j=0; j<nZ; ++j )\n\t\t\t\t\t\tZFR_delta_xFRz[i] += Q[ii*NVMAX + j] * delta_xFRz[j];\n\n\t\t\t\t\tdelta_xFR[i] += ZFR_delta_xFRz[i];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( Delta_bB_isZero == BT_FALSE )\n\t\t\t{\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tfor( j=0; j<nFX; ++j )\n\t\t\t\t\t{\n\t\t\t\t\t\tjj = FX_idx[j];\n\t\t\t\t\t\tHMX_delta_xFX[i] += H[ii*NVMAX + jj] * delta_xFX[j];\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif ( nAC > 0 )\n\t\t\t{\n\t\t\t\tif ( ( Delta_bC_isZero == BT_FALSE ) || ( Delta_bB_isZero == BT_FALSE ) )\n\t\t\t\t{\n\t\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t\t{\n\t\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\t\tHFR_YFR_delta_xFRy[i] += H[ii*NVMAX + jj] * YFR_delta_xFRy[j];\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\n\t\t\tif ( nZ > 0 )\n\t\t\t{\n\t\t\t\t/* auxiliary variable */\n\t\t\t\treal_t delta_xFRz_TMP[NVMAX];\n\t\t\t\treal_t delta_xFRz_RHS[NVMAX];\n\n\n\t\t\t\tif ( ( nAC > 0 ) && ( nFX > 0 ) && ( Delta_bB_isZero == BT_FALSE ) )\n\t\t\t\t{\n\t\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t\t{\n\t\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\tdelta_xFRz_RHS[j] = delta_g[jj] + HFR_YFR_delta_xFRy[j] + HMX_delta_xFX[j];\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( ( nAC == 0 ) && ( Delta_bB_isZero == BT_TRUE ) )\n\t\t\t\t\t{\n\t\t\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\t\tdelta_xFRz_RHS[j] = delta_g[jj];\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tif ( nAC > 0 ) /* => Delta_bB_isZero == BT_TRUE, as BT_FALSE would imply nFX>0 */\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\t\t\tdelta_xFRz_RHS[j] = delta_g[jj] + HFR_YFR_delta_xFRy[j];\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse /* Delta_bB_isZero == BT_FALSE, as nAC==0 */\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\t\t\tdelta_xFRz_RHS[j] = delta_g[jj] + HMX_delta_xFX[j];\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\tfor( i=0; i<nZ; ++i )\n\t\t\t\t\t\tdelta_xFRz[i] -= Q[jj*NVMAX + i] * delta_xFRz_RHS[j];\n\t\t\t\t}\n\n\n\t\t\t\tif ( backsolveR( delta_xFRz,BT_TRUE,delta_xFRz_TMP ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_STEPDIRECTION_FAILED_CHOLESKY );\n\n\t\t\t\tif ( backsolveR( delta_xFRz_TMP,BT_FALSE,delta_xFRz ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_STEPDIRECTION_FAILED_CHOLESKY );\n\n\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tfor( j=0; j<nZ; ++j )\n\t\t\t\t\t\tZFR_delta_xFRz[i] += Q[ii*NVMAX + j] * delta_xFRz[j];\n\n\t\t\t\t\tdelta_xFR[i] += ZFR_delta_xFRz[i];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* III) DETERMINE delta_yAC */\n\tif ( nAC > 0 ) /* => ( nFR = nZ + nAC > 0 ) */\n\t{\n\t\t/* auxiliary variables */\n\t\treal_t delta_yAC_TMP[NCMAX_ALLOC];\n\t\tfor( i=0; i<nAC; ++i )\n\t\t\tdelta_yAC_TMP[i] = 0.0;\n\t\treal_t delta_yAC_RHS[NVMAX];\n\t\tfor( i=0; i<nFR; ++i )\n\t\t\tdelta_yAC_RHS[i] = 0.0;\n\n\t\tif ( hessianType == HST_IDENTITY )\n\t\t{\n\t\t\t/* delta_yAC = (T')^-1 * ( Yfr*delta_gFR + delta_xFRy ) */\n\t\t\tfor( j=0; j<nAC; ++j )\n\t\t\t{\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tdelta_yAC_TMP[j] += Q[ii*NVMAX + nZ+j] * delta_g[ii];\n\t\t\t\t}\n\n\t\t\t\tdelta_yAC_TMP[j] += delta_xFRy[j];\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( ( Delta_bC_isZero == BT_TRUE ) && ( Delta_bB_isZero == BT_TRUE ) )\n\t\t\t{\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tdelta_yAC_RHS[i] = delta_g[ii];\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tdelta_yAC_RHS[i] = HFR_YFR_delta_xFRy[i] + delta_g[ii];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif ( nZ > 0 )\n\t\t\t{\n\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t{\n\t\t\t\t\tii = FR_idx[i];\n\t\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t\t{\n\t\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\t\tdelta_yAC_RHS[i] += H[ii*NVMAX + jj] * ZFR_delta_xFRz[j];\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif ( nFX > 0 )\n\t\t\t{\n\t\t\t\tif ( Delta_bB_isZero == BT_FALSE )\n\t\t\t\t{\n\t\t\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t\t\t\tdelta_yAC_RHS[i] += HMX_delta_xFX[i];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tfor( i=0; i<nAC; ++i)\n\t\t\t{\n\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\tdelta_yAC_TMP[i] += Q[jj*NVMAX + nZ+i] * delta_yAC_RHS[j];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif ( backsolveT( delta_yAC_TMP,BT_TRUE,delta_yAC ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_STEPDIRECTION_FAILED_TQ );\n\t}\n\n\n\t/* IV) DETERMINE delta_yFX */\n\tif ( nFX > 0 )\n\t{\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\n\t\t\tdelta_yFX[i] = delta_g[ii];\n\n\t\t\tfor( j=0; j<nAC; ++j )\n\t\t\t{\n\t\t\t\tjj = AC_idx[j];\n\t\t\t\tdelta_yFX[i] -= A[jj*NVMAX + ii] * delta_yAC[j];\n\t\t\t}\n\n\t\t\tif ( hessianType == HST_IDENTITY )\n\t\t\t{\n\t\t\t\tdelta_yFX[i] += delta_xFX[i];\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\tdelta_yFX[i] += H[ii*NVMAX + jj] * delta_xFR[j];\n\t\t\t\t}\n\n\t\t\t\tif ( Delta_bB_isZero == BT_FALSE )\n\t\t\t\t{\n\t\t\t\t\tfor( j=0; j<nFX; ++j )\n\t\t\t\t\t{\n\t\t\t\t\t\tjj = FX_idx[j];\n\t\t\t\t\t\tdelta_yFX[i] += H[ii*NVMAX + jj] * delta_xFX[j];\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ d e t e r m i n e S t e p L e n g t h\n */\nreturnValue QProblem::hotstart_determineStepLength(\tconst int* const FR_idx, const int* const FX_idx, const int* const AC_idx, const int* const IAC_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lbA, const real_t* const delta_ubA,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFX, const real_t* const delta_xFR,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yAC, const real_t* const delta_yFX,\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_Ax, int& BC_idx, SubjectToStatus& BC_status, BooleanType& BC_isBound\n\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii, jj;\n\tint nV  = getNV( );\n\tint nC  = getNC( );\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\tint nAC = getNAC( );\n\tint nIAC = getNIAC( );\n\n\t/* initialise maximum steplength array */\n\treal_t maxStepLength[2*(NVMAX+NCMAX_ALLOC)];\n\tfor ( i=0; i<2*(nV+nC); ++i )\n\t\tmaxStepLength[i] = 1.0;\n\n\n\t/* I) DETERMINE MAXIMUM DUAL STEPLENGTH: */\n\t/* 1) Ensure that active dual constraints' bounds remain valid\n\t *    (ignoring inequality constraints).  */\n\tfor( i=0; i<nAC; ++i )\n\t{\n\t\tii = AC_idx[i];\n\n\t\tif ( constraints.getType( ii ) != ST_EQUALITY )\n\t\t{\n\t\t\tif ( constraints.getStatus( ii ) == ST_LOWER )\n\t\t\t{\n\t\t\t\t/* active lower constraints' bounds */\n\t\t\t\tif ( delta_yAC[i] < -ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( y[nV+ii] > 0.0 )\n\t\t\t\t\t\tmaxStepLength[nV+ii] = y[nV+ii] / ( -delta_yAC[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[nV+ii] = 0.0;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* active upper constraints' bounds */\n\t\t\t\tif ( delta_yAC[i] > ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( y[nV+ii] < 0.0 )\n\t\t\t\t\t\tmaxStepLength[nV+ii] = y[nV+ii] / ( -delta_yAC[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[nV+ii] = 0.0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* 2) Ensure that active dual bounds remain valid\n\t *    (ignoring implicitly fixed variables). */\n\tfor( i=0; i<nFX; ++i )\n\t{\n\t\tii = FX_idx[i];\n\n\t\tif ( bounds.getType( ii ) != ST_EQUALITY )\n\t\t{\n\t\t\tif ( bounds.getStatus( ii ) == ST_LOWER )\n\t\t\t{\n\t\t\t\t/* active lower bounds */\n\t\t\t\tif ( delta_yFX[i] < -ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( y[ii] > 0.0 )\n\t\t\t\t\t\tmaxStepLength[ii] = y[ii] / ( -delta_yFX[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[ii] = 0.0;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* active upper bounds */\n\t\t\t\tif ( delta_yFX[i] > ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( y[ii] < 0.0 )\n\t\t\t\t\t\tmaxStepLength[ii] = y[ii] / ( -delta_yFX[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[ii] = 0.0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* II) DETERMINE MAXIMUM PRIMAL STEPLENGTH */\n\t/* 1) Ensure that inactive constraints' bounds remain valid\n\t *    (ignoring unbounded constraints). */\n\treal_t delta_x[NVMAX];\n\tfor( j=0; j<nFR; ++j )\n\t{\n\t\tjj = FR_idx[j];\n\t\tdelta_x[jj] = delta_xFR[j];\n\t}\n\tfor( j=0; j<nFX; ++j )\n\t{\n\t\tjj = FX_idx[j];\n\t\tdelta_x[jj] = delta_xFX[j];\n\t}\n\n\tfor( i=0; i<nIAC; ++i )\n\t{\n\t\tii = IAC_idx[i];\n\n\t\tif ( constraints.getType( ii ) != ST_UNBOUNDED )\n\t\t{\n\t\t\tdelta_Ax[ii] = 0.0;\n\t\t\tfor( j=0; j<nV; ++j )\n\t\t\t\tdelta_Ax[ii] += A[ii*NVMAX + j] * delta_x[j]; // POSSIBLE SPEEDUP!\n\n\t\t\t/* inactive lower constraints' bounds */\n\t\t\tif ( constraints.isNoLower( ) == BT_FALSE )\n\t\t\t{\n\t\t\t\tif ( delta_lbA[ii] > delta_Ax[ii] )\n\t\t\t\t{\n\t\t\t\t\tif ( Ax[ii] > lbA[ii] )\n\t\t\t\t\t\tmaxStepLength[nV+ii] = ( Ax[ii] - lbA[ii] ) / ( delta_lbA[ii] - delta_Ax[ii] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[nV+ii] = 0.0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* inactive upper constraints' bounds */\n\t\t\tif ( constraints.isNoUpper( ) == BT_FALSE )\n\t\t\t{\n\t\t\t\tif ( delta_ubA[ii] < delta_Ax[ii] )\n\t\t\t\t{\n\t\t\t\t\tif ( Ax[ii] < ubA[ii] )\n\t\t\t\t\t\tmaxStepLength[nV+nC+nV+ii] = ( Ax[ii] - ubA[ii] ) / ( delta_ubA[ii] - delta_Ax[ii] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[nV+nC+nV+ii] = 0.0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* 2) Ensure that inactive bounds remain valid\n\t *    (ignoring unbounded variables). */\n\t/* inactive lower bounds */\n\tif ( bounds.isNoLower( ) == BT_FALSE )\n\t{\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\t\t\tif ( bounds.getType( ii ) != ST_UNBOUNDED )\n\t\t\t\tif ( delta_lb[ii] > delta_xFR[i] )\n\t\t\t\t{\n\t\t\t\t\tif ( x[ii] > lb[ii] )\n\t\t\t\t\t\tmaxStepLength[ii] = ( x[ii] - lb[ii] ) / ( delta_lb[ii] - delta_xFR[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[ii] = 0.0;\n\t\t\t\t}\n\t\t}\n\t}\n\n\t/* inactive upper bounds */\n\tif ( bounds.isNoUpper( ) == BT_FALSE )\n\t{\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\t\t\tif ( bounds.getType( ii ) != ST_UNBOUNDED )\n\t\t\t\tif ( delta_ub[ii] < delta_xFR[i] )\n\t\t\t\t{\n\t\t\t\t\tif ( x[ii] < ub[ii] )\n\t\t\t\t\t\tmaxStepLength[nV+nC+ii] = ( x[ii] - ub[ii] ) / ( delta_ub[ii] - delta_xFR[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\tmaxStepLength[nV+nC+ii] = 0.0;\n\t\t\t\t}\n\t\t}\n\t}\n\n\n\t/* III) DETERMINE MAXIMUM HOMOTOPY STEPLENGTH */\n\treal_t tau_new = 1.0;\n\n\tBC_idx = 0;\n\tBC_status = ST_UNDEFINED;\n\tBC_isBound = BT_FALSE;\n\n\tfor ( i=0; i<nV; ++i )\n\t{\n\t\t/* 1) Consider lower/dual blocking bounds. */\n\t\tif ( maxStepLength[i] < tau_new )\n\t\t{\n\t\t\ttau_new = maxStepLength[i];\n\t\t\tBC_idx = i;\n\t\t\tBC_isBound = BT_TRUE;\n\t\t\tif ( bounds.getStatus( i ) == ST_INACTIVE ) /* inactive? */\n\t\t\t\tBC_status = ST_LOWER;\n\t\t\telse\n\t\t\t\tBC_status = ST_INACTIVE;\n\t\t}\n\n\t\t/* 2) Consider upper blocking bounds. */\n\t\tif ( maxStepLength[nV+nC+i] < tau_new )\n\t\t{\n\t\t\ttau_new = maxStepLength[nV+nC+i];\n\t\t\tBC_idx = i;\n\t\t\tBC_isBound = BT_TRUE;\n\t\t\tBC_status = ST_UPPER;\n\t\t}\n\t}\n\n\tfor ( i=nV; i<nV+nC; ++i )\n\t{\n\t\t/* 3) Consider lower/dual blocking constraints. */\n\t\tif ( maxStepLength[i] < tau_new )\n\t\t{\n\t\t\ttau_new = maxStepLength[i];\n\t\t\tBC_idx = i-nV;\n\t\t\tBC_isBound = BT_FALSE;\n\t\t\tif ( constraints.getStatus( i-nV ) == ST_INACTIVE ) /* inactive? */\n\t\t\t\tBC_status = ST_LOWER;\n\t\t\telse\n\t\t\t\tBC_status = ST_INACTIVE;\n\t\t}\n\n\t\t/* 4) Consider upper blocking constraints. */\n\t\tif ( maxStepLength[nV+nC+i] < tau_new )\n\t\t{\n\t\t\ttau_new = maxStepLength[nV+nC+i];\n\t\t\tBC_idx = i-nV;\n\t\t\tBC_isBound = BT_FALSE;\n\t\t\tBC_status = ST_UPPER;\n\t\t}\n\t}\n\n\n\t/* IV) CLEAR CYCLING DATA\n\t *     if a positive step can be taken */\n\tif ( tau_new > EPS )\n\t\tcyclingManager.clearCyclingData( );\n\n\n\t/* V) SET MAXIMUM HOMOTOPY STEPLENGTH */\n\ttau = tau_new;\n\n\t#ifdef PC_DEBUG\n\tif ( printlevel == PL_HIGH )\n\t{\n\n\t \tchar messageString[80];\n\n\t\tif ( BC_status == ST_UNDEFINED )\n\t\t\tsprintf( messageString,\"Stepsize is %.6e!\",tau );\n\t\telse\n\t\t\tsprintf( messageString,\"Stepsize is %.6e! (BC_idx = %d, BC_isBound = %d, BC_status = %d)\",tau,BC_idx,BC_isBound,BC_status );\n\n\t\tgetGlobalMessageHandler( )->throwInfo( RET_STEPSIZE_NONPOSITIVE,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t}\n\t#endif\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ p e r f o r m S t e p\n */\nreturnValue QProblem::hotstart_performStep(\tconst int* const FR_idx, const int* const FX_idx, const int* const AC_idx, const int* const IAC_idx,\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g, const real_t* const delta_lbA, const real_t* const delta_ubA,\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFX, const real_t* const delta_xFR,\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yAC, const real_t* const delta_yFX,\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_Ax, int BC_idx, SubjectToStatus BC_status, BooleanType BC_isBound\n\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii;\n\tint nV  = getNV( );\n\tint nC  = getNC( );\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\tint nAC = getNAC( );\n\tint nIAC = getNIAC( );\n\n\n\t/* I) CHECK (CONSTRAINTS') BOUNDS' CONSISTENCY */\n\tif ( areBoundsConsistent( delta_lb,delta_ub,delta_lbA,delta_ubA ) == BT_FALSE )\n\t{\n\t\tinfeasible = BT_TRUE;\n\t\ttau = 0.0;\n\n\t\treturn THROWERROR( RET_QP_INFEASIBLE );\n\t}\n\n\n\t/* II) GO TO ACTIVE SET CHANGE */\n\tif ( tau > ZERO )\n\t{\n\t\t/* 1) Perform step in primal und dual space... */\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\t\t\tx[ii] += tau*delta_xFR[i];\n\t\t}\n\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\t\t\tx[ii] += tau*delta_xFX[i];\n\t\t\ty[ii] += tau*delta_yFX[i];\n\t\t}\n\n\t\tfor( i=0; i<nAC; ++i )\n\t\t{\n\t\t\tii = AC_idx[i];\n\t\t\ty[nV+ii] += tau*delta_yAC[i];\n\t\t}\n\n\t\t/* ... also for Ax. */\n\t\tfor( i=0; i<nIAC; ++i )\n\t\t{\n\t\t\tii = IAC_idx[i];\n\t\t\tif ( constraints.getType( ii ) != ST_UNBOUNDED )\n\t\t\t\tAx[ii] += tau*delta_Ax[ii];\n\t\t}\n\t\tfor( i=0; i<nAC; ++i )\n\t\t{\n\t\t\tii = AC_idx[i];\n\n\t\t\tAx[ii] = 0.0;\n\t\t\tfor( j=0; j<nV; ++j )\n\t\t\t\tAx[ii] += A[ii*NVMAX + j] * x[j];\n\t\t}\n\n\t\t/* 2) Shift QP data. */\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\n\t\t\tg[i]  += tau*delta_g[i];\n\t\t\tlb[i] += tau*delta_lb[i];\n\t\t\tub[i] += tau*delta_ub[i];\n\t\t}\n\n\t\tfor( i=0; i<nC; ++i )\n\t\t{\n\t\t\tlbA[i] += tau*delta_lbA[i];\n\t\t\tubA[i] += tau*delta_ubA[i];\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* print a stepsize warning if stepsize is zero */\n\t\t#ifdef PC_DEBUG\n\t\tchar messageString[80];\n\t\tsprintf( messageString,\"Stepsize is %.6e\",tau );\n\t\tgetGlobalMessageHandler( )->throwWarning( RET_STEPSIZE,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t#endif\n\t}\n\n\n\t/* setup output preferences */\n\t#ifdef PC_DEBUG\n\tchar messageString[80];\n\tVisibilityStatus visibilityStatus;\n\n\tif ( printlevel == PL_HIGH )\n\t\tvisibilityStatus = VS_VISIBLE;\n\telse\n\t\tvisibilityStatus = VS_HIDDEN;\n\t#endif\n\n\t\n\t/* III) UPDATE ACTIVE SET */\n\tswitch ( BC_status )\n\t{\n\t\t/* Optimal solution found as no working set change detected. */\n\t\tcase ST_UNDEFINED:\n\t\t\treturn RET_OPTIMAL_SOLUTION_FOUND;\n\n\n\t\t/* Remove one variable from active set. */\n\t\tcase ST_INACTIVE:\n\t\t\tif ( BC_isBound == BT_TRUE )\n\t\t\t{\n\t\t\t\t#ifdef PC_DEBUG\n\t\t\t\tsprintf( messageString,\"bound no. %d.\", BC_idx );\n\t\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t\t#endif\n\n\t\t\t\tif ( removeBound( BC_idx,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\t\ty[BC_idx] = 0.0;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t#ifdef PC_DEBUG\n\t\t\t\tsprintf( messageString,\"constraint no. %d.\", BC_idx );\n\t\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t\t#endif\n\n\t\t\t\tif ( removeConstraint( BC_idx,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\t\ty[nV+BC_idx] = 0.0;\n\t\t\t}\n\t\t\tbreak;\n\n\n\t\t/* Add one variable to active set. */\n\t\tdefault:\n\t\t\tif ( BC_isBound == BT_TRUE )\n\t\t\t{\n\t\t\t\t#ifdef PC_DEBUG\n\t\t\t\tif ( BC_status == ST_LOWER )\n\t\t\t\t\tsprintf( messageString,\"lower bound no. %d.\", BC_idx );\n\t\t\t\telse\n\t\t\t\t\tsprintf( messageString,\"upper bound no. %d.\", BC_idx );\n\t\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_ADD_TO_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t\t#endif\n\n\t\t\t\tif ( addBound( BC_idx,BC_status,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_ADD_TO_ACTIVESET_FAILED );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t#ifdef PC_DEBUG\n\t\t\t\tif ( BC_status == ST_LOWER )\n\t\t\t\t\tsprintf( messageString,\"lower constraint's bound no. %d.\", BC_idx );\n\t\t\t\telse\n\t\t\t\t\tsprintf( messageString,\"upper constraint's bound no. %d.\", BC_idx );\n\t\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_ADD_TO_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t\t#endif\n\n\t\t\t\tif ( addConstraint( BC_idx,BC_status,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_ADD_TO_ACTIVESET_FAILED );\n\t\t\t}\n\t\t\tbreak;\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ta r e B o u n d s C o n s i s t e n t\n */\nBooleanType QProblem::areBoundsConsistent(\tconst real_t* const delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lbA, const real_t* const delta_ubA\n\t\t\t\t\t\t\t\t\t\t\t) const\n{\n\tint i;\n\n\t/* 1) Check bounds' consistency. */\n\tif ( QProblemB::areBoundsConsistent( delta_lb,delta_ub ) == BT_FALSE )\n\t\treturn BT_FALSE;\n\n\t/* 2) Check constraints' consistency, i.e.\n\t *    check if delta_lb[i] is greater than delta_ub[i]\n\t *    for a component i whose bounds are already (numerically) equal. */\n\tfor( i=0; i<getNC( ); ++i )\n\t\tif ( ( lbA[i] > ubA[i] - BOUNDTOL ) && ( delta_lbA[i] > delta_ubA[i] + EPS ) )\n\t\t\treturn BT_FALSE;\n\n\treturn BT_TRUE;\n}\n\n\n/*\n *\ts e t u p Q P d a t a\n */\nreturnValue QProblem::setupQPdata(\tconst real_t* const _H, const real_t* const _R, const real_t* const _g, const real_t* const _A,\n\t\t\t\t\t\t\t\t\tconst real_t* const _lb, const real_t* const _ub,\n\t\t\t\t\t\t\t\t\tconst real_t* const _lbA, const real_t* const _ubA\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\n\t/* 1) Load Hessian matrix as well as lower and upper bounds vectors. */\n\tif (QProblemB::setupQPdata(_H, _R, _g, _lb, _ub) != SUCCESSFUL_RETURN)\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* 2) Load constraint matrix. */\n\tif ( ( nC > 0 ) && ( _A == 0 ) )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\tif ( nC > 0 )\n\t{\n\t\tfor( i=0; i<nC; ++i )\n\t\t\tfor( j=0; j<nV; ++j )\n\t\t\t\tA[i*NVMAX + j] = _A[i*nV + j];\n\n\t\t/* 3) Setup lower constraints' bounds vector. */\n\t\tif ( _lbA != 0 )\n\t\t{\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t\tlbA[i] = _lbA[i];\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* if no lower constraints' bounds are specified, set them to -infinity */\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t\tlbA[i] = -INFTY;\n\t\t}\n\n\t\t/* 4) Setup upper constraints' bounds vector. */\n\t\tif ( _ubA != 0 )\n\t\t{\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t\tubA[i] = _ubA[i];\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* if no upper constraints' bounds are specified, set them to infinity */\n\t\t\tfor( i=0; i<nC; ++i )\n\t\t\t\tubA[i] = INFTY;\n\t\t}\n\t}\n\n// \tprintmatrix2( \"A\",A,10,20 );\n\t\n// \tprintmatrix2( \"lbA\",lbA,1,nC );\n// \tprintmatrix2( \"ubA\",ubA,1,nC );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n#ifdef PC_DEBUG  /* Define print functions only for debugging! */\n\n/*\n *\tp r i n t I t e r a t i o n\n */\nreturnValue QProblem::printIteration( \tint iteration,\n\t\t\t\t\t\t\t\t\t\tint BC_idx,\tSubjectToStatus BC_status, BooleanType BC_isBound\n\t\t  \t\t\t\t\t\t\t\t)\n{\n\tchar myPrintfString[160];\n\n\t/* consistency check */\n\tif ( iteration < 0 )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* nothing to do */\n\tif ( printlevel != PL_MEDIUM )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n\t/* 1) Print header at first iteration. */\n \tif ( iteration == 0 )\n\t{\n\t\tsprintf( myPrintfString,\"\\n##############  qpOASES  --  QP NO.%4.1d  ###############\\n\", count );\n\t\tmyPrintf( myPrintfString );\n\n\t\tsprintf( myPrintfString,\"  Iter  |  StepLength   |     Info      |  nFX  |  nAC  \\n\" );\n\t\tmyPrintf( myPrintfString );\n\t}\n\n\t/* 2) Print iteration line. */\n\tif ( BC_status == ST_UNDEFINED )\n\t{\n\t\tsprintf( myPrintfString,\"  %4.1d  |  %1.5e  |   QP SOLVED   | %4.1d  | %4.1d  \\n\", iteration,tau,getNFX( ),getNAC( ) );\n\t\tmyPrintf( myPrintfString );\n\t}\n\telse\n\t{\n\t\tchar info[8];\n\n\t\tif ( BC_status == ST_INACTIVE )\n\t\t\tsprintf( info,\"REM \" );\n\t\telse\n\t\t\tsprintf( info,\"ADD \" );\n\n\t\tif ( BC_isBound == BT_TRUE )\n\t\t\tsprintf( &(info[4]),\"BND\" );\n\t\telse\n\t\t\tsprintf( &(info[4]),\"CON\" );\n\n\t\tsprintf( myPrintfString,\"  %4.1d  |  %1.5e  |  %s%4.1d  | %4.1d  | %4.1d  \\n\", iteration,tau,info,BC_idx,getNFX( ),getNAC( ) );\n\t\tmyPrintf( myPrintfString );\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t I t e r a t i o n\n */\nreturnValue QProblem::printIteration( \tint iteration,\n\t\t\t\t\t\t\t\t\t\tint BC_idx,\tSubjectToStatus BC_status\n\t\t  \t\t\t\t\t\t\t\t)\n{\n\treturn printIteration( iteration,BC_idx,BC_status,BT_TRUE );\n}\n\n#endif  /* PC_DEBUG */\n\n\n\n/*\n *\tc h e c k K K T c o n d i t i o n s\n */\nreturnValue QProblem::checkKKTconditions( )\n{\n\t#ifdef __PERFORM_KKT_TEST__\n\n\tint i, j, jj;\n\tint nV  = getNV( );\n\tint nC  = getNC( );\n\tint nAC = getNAC( );\n\n\treal_t tmp;\n\treal_t maxKKTviolation = 0.0;\n\n\tint AC_idx[NCMAX_ALLOC];\n\tconstraints.getActive( )->getNumberArray( AC_idx );\n\n\t/* 1) check for Hx + g - [yFX yAC]*[Id A]' = 0. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\ttmp = g[i];\n\n\t\tfor( j=0; j<nV; ++j )\n\t\t\ttmp += H[i*NVMAX + j] * x[j];\n\n\t\ttmp -= y[i];\n\n\t\t/* Only sum over active constraints as y is zero for all inactive ones. */\n\t\tfor( j=0; j<nAC; ++j )\n\t\t{\n\t\t\tjj = AC_idx[j];\n\t\t\ttmp -= A[jj*NVMAX + i] * y[nV+jj];\n\t\t}\n\n\t\tif ( getAbs( tmp ) > maxKKTviolation )\n\t\t\tmaxKKTviolation = getAbs( tmp );\n\t}\n\n\t/* 2) Check for [lb lbA] <= [Id A]*x <= [ub ubA]. */\n\t/* lbA <= Ax <= ubA */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tif ( lbA[i] - Ax[i] > maxKKTviolation )\n\t\t\tmaxKKTviolation = lbA[i] - Ax[i];\n\n\t\tif ( Ax[i] - ubA[i] > maxKKTviolation )\n\t\t\tmaxKKTviolation = Ax[i] - ubA[i];\n\t}\n\n\t/* lb <= x <= ub */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( lb[i] - x[i] > maxKKTviolation )\n\t\t\tmaxKKTviolation = lb[i] - x[i];\n\n\t\tif ( x[i] - ub[i] > maxKKTviolation )\n\t\t\tmaxKKTviolation = x[i] - ub[i];\n\t}\n\n\t/* 3) Check for correct sign of y and for complementary slackness. */\n\t/* bounds */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tswitch ( bounds.getStatus( i ) )\n\t\t{\n\t\t\tcase ST_LOWER:\n\t\t\t\tif ( -y[i] > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = -y[i];\n\t\t\t\tif ( getAbs( x[i] - lb[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( x[i] - lb[i] );\n\t\t\t\tbreak;\n\n\t\t\tcase ST_UPPER:\n\t\t\t\tif ( y[i] > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = y[i];\n\t\t\t\tif ( getAbs( ub[i] - x[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( ub[i] - x[i] );\n\t\t\t\tbreak;\n\n\t\t\tdefault: /* inactive */\n\t\t\tif ( getAbs( y[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( y[i] );\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* constraints */\n\tfor( i=0; i<nC; ++i )\n\t{\n\t\tswitch ( constraints.getStatus( i ) )\n\t\t{\n\t\t\tcase ST_LOWER:\n\t\t\t\tif ( -y[nV+i] > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = -y[nV+i];\n\t\t\t\tif ( getAbs( Ax[i] - lbA[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( Ax[i] - lbA[i] );\n\t\t\t\tbreak;\n\n\t\t\tcase ST_UPPER:\n\t\t\t\tif ( y[nV+i] > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = y[nV+i];\n\t\t\t\tif ( getAbs( ubA[i] - Ax[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( ubA[i] - Ax[i] );\n\t\t\t\tbreak;\n\n\t\t\tdefault: /* inactive */\n\t\t\tif ( getAbs( y[nV+i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( y[nV+i] );\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif ( maxKKTviolation > CRITICALACCURACY )\n\t\treturn RET_NO_SOLUTION;\n\n\tif ( maxKKTviolation > DESIREDACCURACY )\n\t\treturn RET_INACCURATE_SOLUTION;\n\n\t#endif /* __PERFORM_KKT_TEST__ */\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/QProblem.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/QProblem.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of inlined member functions of the QProblem class which \n *\tis able to use the newly developed online active set strategy for \n *\tparametric quadratic programming.\n */\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n/*\n *\tg e t A\n */\ninline returnValue QProblem::getA( real_t* const _A ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNV( )*getNC( ); ++i )\n\t\t_A[i] = A[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t A\n */\ninline returnValue QProblem::getA( int number, real_t* const row ) const\n{\n\tint nV = getNV( );\n\t\t\n\tif ( ( number >= 0 ) && ( number < getNC( ) ) )\n\t{\n\t\tfor ( int i=0; i<nV; ++i )\n\t\t\trow[i] = A[number*NVMAX + i];\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\tg e t L B A\n */\ninline returnValue QProblem::getLBA( real_t* const _lbA ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNC( ); ++i )\n\t\t_lbA[i] = lbA[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t L B A\n */\ninline returnValue QProblem::getLBA( int number, real_t& value ) const\n{\n\tif ( ( number >= 0 ) && ( number < getNC( ) ) )\n\t{\n\t\tvalue = lbA[number];\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\tg e t U B A\n */\ninline returnValue QProblem::getUBA( real_t* const _ubA ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNC( ); ++i )\n\t\t_ubA[i] = ubA[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t U B A\n */\ninline returnValue QProblem::getUBA( int number, real_t& value ) const\n{\n\tif ( ( number >= 0 ) && ( number < getNC( ) ) )\n\t{\n\t\tvalue = ubA[number];\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\tg e t C o n s t r a i n t s\n */\ninline returnValue QProblem::getConstraints( Constraints* const _constraints ) const\n{\n\t*_constraints = constraints;\n\t\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\tg e t N C\n */\ninline int QProblem::getNC( ) const\n{\n\treturn constraints.getNC( );\n}\n\n\n/*\n *\tg e t N E C\n */\ninline int QProblem::getNEC( ) const\n{\n\treturn constraints.getNEC( );\n}\n\n\n/*\n *\tg e t N A C\n */\ninline int QProblem::getNAC( )\n{\n\treturn constraints.getNAC( );\n}\n\n\n/*\n *\tg e t N I A C\n */\ninline int QProblem::getNIAC( )\n{\n\treturn constraints.getNIAC( );\n}\n\n\n\n/*****************************************************************************\n *  P R O T E C T E D                                                        *\n *****************************************************************************/\n \n\n/*\n *\ts e t A\n */\ninline returnValue QProblem::setA( const real_t* const A_new )\n{\n\tint i, j;\n\tint nV = getNV( );\n\tint nC = getNC( );\n\n\t/* Set constraint matrix AND update member AX. */\n\tfor( j=0; j<nC; ++j )\n\t{\n\t\tAx[j] = 0.0;\n\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\t\n\t\t\tA[j*NVMAX + i] = A_new[j*nV + i];\n\t\t\tAx[j] += A[j*NVMAX + i] * x[i];\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t A\n */\ninline returnValue QProblem::setA( int number, const real_t* const row )\n{\n\tint i;\n\tint nV = getNV( );\n\n\t/* Set constraint matrix AND update member AX. */\n\tif ( ( number >= 0 ) && ( number < getNC( ) ) )\n\t{\n\t\tAx[number] = 0.0;\n\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\n\t\t\tA[number*NVMAX + i] = row[i];\n\t\t\tAx[number] += A[number*NVMAX + i] * x[i];\n\t\t}\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\ts e t L B A\n */\ninline returnValue QProblem::setLBA( const real_t* const lbA_new )\n{\n\tint i;\n\tint nC = getNC();\n\n\tfor( i=0; i<nC; ++i )\n\t\tlbA[i] = lbA_new[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t L B A\n */\ninline returnValue QProblem::setLBA( int number, real_t value )\n{\n\tif ( ( number >= 0 ) && ( number < getNC( ) ) )\n\t{\n\t\tlbA[number] = value;\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\ts e t U B A\n */\ninline returnValue QProblem::setUBA( const real_t* const ubA_new )\n{\n\tint i;\n\tint nC = getNC();\n\n\tfor( i=0; i<nC; ++i )\n\t\tubA[i] = ubA_new[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t U B A\n */\ninline returnValue QProblem::setUBA( int number, real_t value )\n{\n\tif ( ( number >= 0 ) && ( number < getNC( ) ) )\n\t{\n\t\tubA[number] = value;\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/QProblemB.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/QProblemB.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the QProblemB class which is able to use the newly\n *\tdeveloped online active set strategy for parametric quadratic programming.\n */\n\n\n#include <QProblemB.hpp>\n\n#include <stdio.h>\n\nvoid printmatrix(char *name, double *A, int m, int n) {\n  int i, j;\n\n  printf(\"%s = [...\\n\", name);\n  for (i = 0; i < m; i++) {\n    for (j = 0; j < n; j++)\n        printf(\"  % 9.4f\", A[i*n+j]);\n    printf(\",\\n\");\n  }\n  printf(\"];\\n\");\n}\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tQ P r o b l e m B\n */\nQProblemB::QProblemB( )\n{\n\t/* reset global message handler */\n\tgetGlobalMessageHandler( )->reset( );\n\n\thasHessian = BT_FALSE;\n\n\tbounds.init( 0 );\n\n\thasCholesky = BT_FALSE;\n\n\ttau = 0.0;\n\n\thessianType = HST_POSDEF_NULLSPACE; /* Hessian is assumed to be positive definite by default */\n\tinfeasible = BT_FALSE;\n\tunbounded = BT_FALSE;\n\n\tstatus = QPS_NOTINITIALISED;\n\n\t#ifdef PC_DEBUG\n\tprintlevel = PL_MEDIUM;\n\tsetPrintLevel( PL_MEDIUM );\n\t#else\n\tprintlevel = QPOASES_PRINTLEVEL;\n\t#endif\n\n\tcount = 0;\n}\n\n\n/*\n *\tQ P r o b l e m B\n */\nQProblemB::QProblemB( int _nV )\n{\n\t/* consistency check */\n\tif ( _nV <= 0 )\n\t{\n\t\t_nV = 1;\n\t\tTHROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\thasHessian = BT_FALSE;\n\n\t/* reset global message handler */\n\tgetGlobalMessageHandler( )->reset( );\n\n\tbounds.init( _nV );\n\n\thasCholesky = BT_FALSE;\n\n\ttau = 0.0;\n\n\thessianType = HST_POSDEF_NULLSPACE; /* Hessian is assumed to be positive definite by default */\n\tinfeasible = BT_FALSE;\n\tunbounded = BT_FALSE;\n\n\tstatus = QPS_NOTINITIALISED;\n\n\t#ifdef PC_DEBUG\n\tprintlevel = PL_MEDIUM;\n\tsetPrintLevel( PL_MEDIUM );\n\t#else\n\tprintlevel = QPOASES_PRINTLEVEL;\n\t#endif\n\n\tcount = 0;\n}\n\n\n/*\n *\tQ P r o b l e m B\n */\nQProblemB::QProblemB( const QProblemB& rhs )\n{\n\tint i, j;\n\n\tint _nV = rhs.bounds.getNV( );\n\n\tfor( i=0; i<_nV; ++i )\n\t\tfor( j=0; j<_nV; ++j )\n\t\t\tH[i*NVMAX + j] = rhs.H[i*NVMAX + j];\n\n\thasHessian = rhs.hasHessian;\n\n\tfor( i=0; i<_nV; ++i )\n\t\tg[i] = rhs.g[i];\n\n\tfor( i=0; i<_nV; ++i )\n\t\tlb[i] = rhs.lb[i];\n\n\tfor( i=0; i<_nV; ++i )\n\t\tub[i] = rhs.ub[i];\n\n\n\tbounds = rhs.bounds;\n\n\tfor( i=0; i<_nV; ++i )\n\t\tfor( j=0; j<_nV; ++j )\n\t\t\tR[i*NVMAX + j] = rhs.R[i*NVMAX + j];\n\thasCholesky = rhs.hasCholesky;\n\n\tfor( i=0; i<_nV; ++i )\n\t\tx[i] = rhs.x[i];\n\n\tfor( i=0; i<_nV; ++i )\n\t\ty[i] = rhs.y[i];\n\n\ttau = rhs.tau;\n\n\thessianType = rhs.hessianType;\n\tinfeasible = rhs.infeasible;\n\tunbounded = rhs.unbounded;\n\n\tstatus = rhs.status;\n\n\tprintlevel = rhs.printlevel;\n\n\tcount = rhs.count;\n}\n\n\n/*\n *\t~ Q P r o b l e m B\n */\nQProblemB::~QProblemB( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nQProblemB& QProblemB::operator=( const QProblemB& rhs )\n{\n\tint i, j;\n\n\tif ( this != &rhs )\n\t{\n\t\tint _nV = rhs.bounds.getNV( );\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tfor( j=0; j<_nV; ++j )\n\t\t\t\tH[i*NVMAX + j] = rhs.H[i*NVMAX + j];\n\n\t\thasHessian = rhs.hasHessian;\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tg[i] = rhs.g[i];\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tlb[i] = rhs.lb[i];\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tub[i] = rhs.ub[i];\n\n\t\tbounds = rhs.bounds;\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tfor( j=0; j<_nV; ++j )\n\t\t\t\tR[i*NVMAX + j] = rhs.R[i*NVMAX + j];\n\t\thasCholesky = rhs.hasCholesky;\n\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\tx[i] = rhs.x[i];\n\n\t\tfor( i=0; i<_nV; ++i )\n\t\t\ty[i] = rhs.y[i];\n\n\t\ttau = rhs.tau;\n\n\t\thessianType = rhs.hessianType;\n\t\tinfeasible = rhs.infeasible;\n\t\tunbounded = rhs.unbounded;\n\n\t\tstatus = rhs.status;\n\n\t\tprintlevel = rhs.printlevel;\n\t\tsetPrintLevel( rhs.printlevel );\n\n\t\tcount = rhs.count;\n\t}\n\n\treturn *this;\n}\n\n\n/*\n *\tr e s e t\n */\nreturnValue QProblemB::reset( )\n{\n\tint i, j;\n\tint nV = getNV( );\n\n\t/** 0) Reset has Hessian flag. */\n\thasHessian = BT_FALSE;\n\n\t/* 1) Reset bounds. */\n\tbounds.init( nV );\n\n\t/* 2) Reset Cholesky decomposition. */\n\tfor( i=0; i<nV; ++i )\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tR[i*NVMAX + j] = 0.0;\n\thasCholesky = BT_FALSE;\n\n\t/* 3) Reset steplength and status flags. */\n\ttau = 0.0;\n\n\thessianType = HST_POSDEF_NULLSPACE; /* Hessian is assumed to be positive definite by default */\n\tinfeasible = BT_FALSE;\n\tunbounded = BT_FALSE;\n\n\tstatus = QPS_NOTINITIALISED;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ti n i t\n */\nreturnValue QProblemB::init(\tconst real_t* const _H, const real_t* const _g,\n\t\t\t\t\t\t\t\tconst real_t* const _lb, const real_t* const _ub,\n\t\t\t\t\t\t\t\tint& nWSR, const real_t* const yOpt, real_t* const cputime\n\t\t\t\t\t\t\t\t)\n{\n\t/* 1) Setup QP data. */\n\tif (setupQPdata(_H, 0, _g, _lb, _ub) != SUCCESSFUL_RETURN)\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* 2) Call to main initialisation routine (without any additional information). */\n\treturn solveInitialQP(0, yOpt, 0, nWSR, cputime);\n}\n\nreturnValue QProblemB::init(\tconst real_t* const _H, const real_t* const _R, const real_t* const _g,\n\t\t\t\t\t\t\t\tconst real_t* const _lb, const real_t* const _ub,\n\t\t\t\t\t\t\t\tint& nWSR, const real_t* const yOpt, real_t* const cputime\n\t\t\t\t\t\t\t\t)\n{\n\t/* 1) Setup QP data. */\n\tif (setupQPdata(_H, _R, _g, _lb, _ub) != SUCCESSFUL_RETURN)\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* 2) Call to main initialisation routine (without any additional information). */\n\treturn solveInitialQP(0, yOpt, 0, nWSR, cputime);\n}\n\n\n/*\n *\th o t s t a r t\n */\nreturnValue QProblemB::hotstart(\tconst real_t* const g_new, const real_t* const lb_new, const real_t* const ub_new,\n\t\t\t\t\t\t\t\t\tint& nWSR, real_t* const cputime\n\t\t\t\t\t\t\t\t\t)\n{\n\tint l;\n\n\t/* consistency check */\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )       ||\n\t\t ( getStatus( ) == QPS_PREPARINGAUXILIARYQP ) ||\n\t\t ( getStatus( ) == QPS_PERFORMINGHOMOTOPY )   )\n\t{\n\t\treturn THROWERROR( RET_HOTSTART_FAILED_AS_QP_NOT_INITIALISED );\n\t}\n\n\t/* start runtime measurement */\n\treal_t starttime = 0.0;\n\tif ( cputime != 0 )\n\t\tstarttime = getCPUtime( );\n\n\n\t/* I) PREPARATIONS */\n\t/* 1) Reset status flags and increase QP counter. */\n\tinfeasible = BT_FALSE;\n\tunbounded = BT_FALSE;\n\n\t++count;\n\n\t/* 2) Allocate delta vectors of gradient and bounds. */\n\treturnValue returnvalue;\n\tBooleanType Delta_bB_isZero;\n\n\tint FR_idx[NVMAX];\n\tint FX_idx[NVMAX];\n\n\treal_t delta_g[NVMAX];\n\treal_t delta_lb[NVMAX];\n\treal_t delta_ub[NVMAX];\n\n\treal_t delta_xFR[NVMAX];\n\treal_t delta_xFX[NVMAX];\n\treal_t delta_yFX[NVMAX];\n\n\tint BC_idx;\n\tSubjectToStatus BC_status;\n\n\t#ifdef PC_DEBUG\n\tchar messageString[80];\n\t#endif\n\n\t/* II) MAIN HOMOTOPY LOOP */\n\tfor( l=0; l<nWSR; ++l )\n\t{\n\t\tstatus = QPS_PERFORMINGHOMOTOPY;\n\n\t\tif ( printlevel == PL_HIGH )\n\t\t{\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"%d ...\",l );\n\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_ITERATION_STARTED,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t\t#endif\n\t\t}\n\n\t\t/* 1) Setup index arrays. */\n\t\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\n\t\tif ( bounds.getFixed( )->getNumberArray( FX_idx ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_HOTSTART_FAILED );\n\n\t\t/* 2) Initialize shift direction of the gradient and the bounds. */\n\t\treturnvalue = hotstart_determineDataShift(  FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tg_new,lb_new,ub_new,\n\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_g,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tDelta_bB_isZero\n\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\t\t\tTHROWERROR( RET_SHIFT_DETERMINATION_FAILED );\n\t\t\treturn returnvalue;\n\t\t}\n\n\t\t/* 3) Determination of step direction of X and Y. */\n\t\treturnvalue = hotstart_determineStepDirection(\tFR_idx,FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_g,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tDelta_bB_isZero,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_xFX,delta_xFR,delta_yFX\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t);\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\t\t\tTHROWERROR( RET_STEPDIRECTION_DETERMINATION_FAILED );\n\t\t\treturn returnvalue;\n\t\t}\n\n\n\t\t/* 4) Determination of step length TAU. */\n\t\treturnvalue = hotstart_determineStepLength(\tFR_idx,FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tdelta_xFR,delta_yFX,\n\t\t\t\t\t\t\t\t\t\t\t\t\tBC_idx,BC_status );\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\t\t\tTHROWERROR( RET_STEPLENGTH_DETERMINATION_FAILED );\n\t\t\treturn returnvalue;\n\t\t}\n\n\t\t/* 5) Realization of the homotopy step. */\n\t\treturnvalue = hotstart_performStep(\tFR_idx,FX_idx,\n\t\t\t\t\t\t\t\t\t\t\tdelta_g,delta_lb,delta_ub,\n\t\t\t\t\t\t\t\t\t\t\tdelta_xFX,delta_xFR,delta_yFX,\n\t\t\t\t\t\t\t\t\t\t\tBC_idx,BC_status\n\t\t\t\t\t\t\t\t\t\t\t);\n\n\n\t\tif ( returnvalue != SUCCESSFUL_RETURN )\n\t\t{\n\t\t\tnWSR = l;\n\n\t\t\t/* stop runtime measurement */\n\t\t\tif ( cputime != 0 )\n\t\t\t\t*cputime = getCPUtime( ) - starttime;\n\n\t\t\t/* optimal solution found? */\n\t\t\tif ( returnvalue == RET_OPTIMAL_SOLUTION_FOUND )\n\t\t\t{\n\t\t\t\tstatus = QPS_SOLVED;\n\n\t\t\t\tif ( printlevel == PL_HIGH )\n\t\t\t\t\tTHROWINFO( RET_OPTIMAL_SOLUTION_FOUND );\n\n\t\t\t\t#ifdef PC_DEBUG\n\t \t\t\tif ( printIteration( l,BC_idx,BC_status ) != SUCCESSFUL_RETURN )\n\t\t\t\t\tTHROWERROR( RET_PRINT_ITERATION_FAILED ); /* do not pass this as return value! */\n\t\t\t\t#endif\n\n\t\t\t\t/* check KKT optimality conditions */\n\t\t\t\treturn checkKKTconditions( );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* checks for infeasibility... */\n\t\t\t\tif ( infeasible == BT_TRUE )\n\t\t\t\t{\n\t\t\t\t\tstatus = QPS_HOMOTOPYQPSOLVED;\n\t\t\t\t\treturn THROWERROR( RET_HOTSTART_STOPPED_INFEASIBILITY );\n\t\t\t\t}\n\n\t\t\t\t/* ...unboundedness... */\n\t\t\t\tif ( unbounded == BT_TRUE ) /* not necessary since objective function convex! */\n\t\t\t\t\treturn THROWERROR( RET_HOTSTART_STOPPED_UNBOUNDEDNESS );\n\n\t\t\t\t/* ... and throw unspecific error otherwise */\n\t\t\t\tTHROWERROR( RET_HOMOTOPY_STEP_FAILED );\n\t\t\t\treturn returnvalue;\n\t\t\t}\n\t\t}\n\n\t\t/* 6) Output information of successful QP iteration. */\n\t\tstatus = QPS_HOMOTOPYQPSOLVED;\n\n\t\t#ifdef PC_DEBUG\n\t\tif ( printIteration( l,BC_idx,BC_status ) != SUCCESSFUL_RETURN )\n\t\t\tTHROWERROR( RET_PRINT_ITERATION_FAILED ); /* do not pass this as return value! */\n\t\t#endif\n\t}\n\n\n\t/* stop runtime measurement */\n\tif ( cputime != 0 )\n\t\t*cputime = getCPUtime( ) - starttime;\n\n\n\t/* if programm gets to here, output information that QP could not be solved\n\t * within the given maximum numbers of working set changes */\n\tif ( printlevel == PL_HIGH )\n\t{\n\t\t#ifdef PC_DEBUG\n\t\tsprintf( messageString,\"(nWSR = %d)\",nWSR );\n\t\treturn getGlobalMessageHandler( )->throwWarning( RET_MAX_NWSR_REACHED,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t#endif\n\t}\n\n\t/* Finally check KKT optimality conditions. */\n\treturnValue returnvalueKKTcheck = checkKKTconditions( );\n\n\tif ( returnvalueKKTcheck != SUCCESSFUL_RETURN )\n\t\treturn returnvalueKKTcheck;\n\telse\n\t\treturn RET_MAX_NWSR_REACHED;\n}\n\n\n/*\n *\tg e t N Z\n */\nint QProblemB::getNZ( )\n{\n\t/* if no constraints are present: nZ=nFR */\n\treturn bounds.getFree( )->getLength( );\n}\n\n\n/*\n *\tg e t O b j V a l\n */\nreal_t QProblemB::getObjVal( ) const\n{\n\treal_t objVal;\n\n\t/* calculated optimal objective function value\n\t * only if current QP has been solved */\n\tif ( ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED ) )\n\t{\n\t\tobjVal = getObjVal( x );\n\t}\n\telse\n\t{\n\t\tobjVal = INFTY;\n\t}\n\n\treturn objVal;\n}\n\n\n/*\n *\tg e t O b j V a l\n */\nreal_t QProblemB::getObjVal( const real_t* const _x ) const\n{\n\tint i, j;\n\tint nV = getNV( );\n\n\treal_t obj_tmp = 0.0;\n\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tobj_tmp += _x[i]*g[i];\n\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tobj_tmp += 0.5*_x[i]*H[i*NVMAX + j]*_x[j];\n\t}\n\n\treturn obj_tmp;\n}\n\n\n/*\n *\tg e t P r i m a l S o l u t i o n\n */\nreturnValue QProblemB::getPrimalSolution( real_t* const xOpt ) const\n{\n\tint i;\n\n\t/* return optimal primal solution vector\n\t * only if current QP has been solved */\n\tif ( ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED ) )\n\t{\n\t\tfor( i=0; i<getNV( ); ++i )\n\t\t\txOpt[i] = x[i];\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn RET_QP_NOT_SOLVED;\n\t}\n}\n\n\n/*\n *\tg e t D u a l S o l u t i o n\n */\nreturnValue QProblemB::getDualSolution( real_t* const yOpt ) const\n{\n\tint i;\n\n\t/* return optimal dual solution vector\n\t * only if current QP has been solved */\n\tif ( ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED ) )\n\t{\n\t\tfor( i=0; i<getNV( ); ++i )\n\t\t\tyOpt[i] = y[i];\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn RET_QP_NOT_SOLVED;\n\t}\n}\n\n\n/*\n *\ts e t P r i n t L e v e l\n */\nreturnValue QProblemB::setPrintLevel( PrintLevel _printlevel )\n{\n\t#ifndef __MATLAB__\n\tif ( ( printlevel >= PL_MEDIUM ) && ( printlevel != _printlevel ) )\n\t\tTHROWINFO( RET_PRINTLEVEL_CHANGED );\n\t#endif\n\n\tprintlevel = _printlevel;\n\n\t/* update message handler preferences */\n \tswitch ( printlevel )\n \t{\n \t\tcase PL_NONE:\n \t\t\tgetGlobalMessageHandler( )->setErrorVisibilityStatus( VS_HIDDEN );\n\t\t\tgetGlobalMessageHandler( )->setWarningVisibilityStatus( VS_HIDDEN );\n\t\t\tgetGlobalMessageHandler( )->setInfoVisibilityStatus( VS_HIDDEN );\n\t\t\tbreak;\n\n\t\tcase PL_LOW:\n \t\t\tgetGlobalMessageHandler( )->setErrorVisibilityStatus( VS_VISIBLE );\n\t\t\tgetGlobalMessageHandler( )->setWarningVisibilityStatus( VS_HIDDEN );\n\t\t\tgetGlobalMessageHandler( )->setInfoVisibilityStatus( VS_HIDDEN );\n\t\t\tbreak;\n\n \t\tdefault: /* PL_MEDIUM, PL_HIGH */\n \t\t\tgetGlobalMessageHandler( )->setErrorVisibilityStatus( VS_VISIBLE );\n\t\t\tgetGlobalMessageHandler( )->setWarningVisibilityStatus( VS_VISIBLE );\n\t\t\tgetGlobalMessageHandler( )->setInfoVisibilityStatus( VS_VISIBLE );\n\t\t\tbreak;\n \t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*****************************************************************************\n *  P R O T E C T E D                                                        *\n *****************************************************************************/\n\n/*\n *\tc h e c k F o r I d e n t i t y H e s s i a n\n */\nreturnValue QProblemB::checkForIdentityHessian( )\n{\n\tint i, j;\n\tint nV = getNV( );\n\n\t/* nothing to do as status flag remains unaltered\n\t * if Hessian differs from identity matrix */\n\tif ( hessianType == HST_IDENTITY )\n\t\treturn SUCCESSFUL_RETURN;\n\n\t/* 1) If Hessian differs from identity matrix,\n\t *    return without changing the internal HessianType. */\n\tfor ( i=0; i<nV; ++i )\n\t\tif ( getAbs( H[i*NVMAX + i] - 1.0 ) > EPS )\n\t\t\treturn SUCCESSFUL_RETURN;\n\n\tfor ( i=0; i<nV; ++i )\n\t{\n\t\tfor ( j=0; j<i; ++j )\n\t\t\tif ( ( getAbs( H[i*NVMAX + j] ) > EPS ) || ( getAbs( H[j*NVMAX + i] ) > EPS ) )\n\t\t\t\treturn SUCCESSFUL_RETURN;\n\t}\n\n\t/* 2) If this point is reached, Hessian equals the idetity matrix. */\n\thessianType = HST_IDENTITY;\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p S u b j e c t T o T y p e\n */\nreturnValue QProblemB::setupSubjectToType( )\n{\n\tint i;\n\tint nV = getNV( );\n\n\n\t/* 1) Check if lower bounds are present. */\n\tbounds.setNoLower( BT_TRUE );\n\tfor( i=0; i<nV; ++i )\n\t\tif ( lb[i] > -INFTY )\n\t\t{\n\t\t\tbounds.setNoLower( BT_FALSE );\n\t\t\tbreak;\n\t\t}\n\n\t/* 2) Check if upper bounds are present. */\n\tbounds.setNoUpper( BT_TRUE );\n\tfor( i=0; i<nV; ++i )\n\t\tif ( ub[i] < INFTY )\n\t\t{\n\t\t\tbounds.setNoUpper( BT_FALSE );\n\t\t\tbreak;\n\t\t}\n\n\t/* 3) Determine implicitly fixed and unbounded variables. */\n\tint nFV = 0;\n\tint nUV = 0;\n\n\tfor( i=0; i<nV; ++i )\n\t\tif ( ( lb[i] < -INFTY + BOUNDTOL ) && ( ub[i] > INFTY - BOUNDTOL ) )\n\t\t{\n\t\t\tbounds.setType( i,ST_UNBOUNDED );\n\t\t\t++nUV;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif ( lb[i] > ub[i] - BOUNDTOL )\n\t\t\t{\n\t\t\t\tbounds.setType( i,ST_EQUALITY );\n\t\t\t\t++nFV;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tbounds.setType( i,ST_BOUNDED );\n\t\t\t}\n\t\t}\n\n\t/* 4) Set dimensions of bounds structure. */\n\tbounds.setNFV( nFV );\n\tbounds.setNUV( nUV );\n\tbounds.setNBV( nV - nFV - nUV );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tc h o l e s k y D e c o m p o s i t i o n\n */\nreturnValue QProblemB::setupCholeskyDecomposition( )\n{\n\tint i, j, k, ii, jj;\n\tint nV  = getNV( );\n\tint nFR = getNFR( );\n\n\t/* If Hessian flag is false, it means that H & R already contain Cholesky\n\t * factorization -- provided from outside. */\n\tif (hasHessian == BT_FALSE)\n\t\treturn SUCCESSFUL_RETURN;\n\n\t/* 1) Initialises R with all zeros. */\n\tfor( i=0; i<nV; ++i )\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tR[i*NVMAX + j] = 0.0;\n\n\t/* 2) Calculate Cholesky decomposition of H (projected to free variables). */\n\tif ( hessianType == HST_IDENTITY )\n\t{\n\t\t/* if Hessian is identity, so is its Cholesky factor. */\n\t\tfor( i=0; i<nFR; ++i )\n\t\t\tR[i*NVMAX + i] = 1.0;\n\t}\n\telse\n\t{\n\t\tif ( nFR > 0 )\n\t\t{\n\t\t\tint FR_idx[NVMAX];\n\t\t\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_INDEXLIST_CORRUPTED );\n\n\t\t\t/* R'*R = H */\n\t\t\treal_t sum;\n\t\t\treal_t inv;\n\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\t/* j == i */\n\t\t\t\tii = FR_idx[i];\n\t\t\t\tsum = H[ii*NVMAX + ii];\n\n\t\t\t\tfor( k=(i-1); k>=0; --k )\n\t\t\t\t\tsum -= R[k*NVMAX + i] * R[k*NVMAX + i];\n\n\t\t\t\tif ( sum > 0.0 )\n\t\t\t\t{\n\t\t\t\t\tR[i*NVMAX + i] = sqrt( sum );\n\t\t\t\t\tinv = 1.0 / R[i*NVMAX + i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\thessianType = HST_SEMIDEF;\n\t\t\t\t\treturn THROWERROR( RET_HESSIAN_NOT_SPD );\n\t\t\t\t}\n\n\t\t\t\t/* j > i */\n\t\t\t\tfor( j=(i+1); j<nFR; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FR_idx[j];\n\t\t\t\t\tsum = H[jj*NVMAX + ii];\n\n\t\t\t\t\tfor( k=(i-1); k>=0; --k )\n\t\t\t\t\t\tsum -= R[k*NVMAX + i] * R[k*NVMAX + j];\n\n\t\t\t\t\tR[i*NVMAX + j] = sum * inv;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts o l v e I n i t i a l Q P\n */\nreturnValue QProblemB::solveInitialQP(\tconst real_t* const xOpt, const real_t* const yOpt,\n\t\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds,\n\t\t\t\t\t\t\t\t\t\tint& nWSR, real_t* const cputime\n\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, nFR;\n\tint nV = getNV( );\n\n\n\t/* start runtime measurement */\n\treal_t starttime = 0.0;\n\tif ( cputime != 0 )\n\t\tstarttime = getCPUtime( );\n\n\n\tstatus = QPS_NOTINITIALISED;\n\n\t/* I) ANALYSE QP DATA: */\n\t/* 1) Check if Hessian happens to be the identity matrix. */\n\tif ( checkForIdentityHessian( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 2) Setup type of bounds (i.e. unbounded, implicitly fixed etc.). */\n\tif ( setupSubjectToType( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tstatus = QPS_PREPARINGAUXILIARYQP;\n\n\n\t/* II) SETUP AUXILIARY QP WITH GIVEN OPTIMAL SOLUTION: */\n\t/* 1) Setup bounds data structure. */\n\tif ( bounds.setupAllFree( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 2) Setup optimal primal/dual solution for auxiliary QP. */\n\tif ( setupAuxiliaryQPsolution( xOpt,yOpt ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 3) Obtain linear independent working set for auxiliary QP. */\n\n\tstatic Bounds auxiliaryBounds;\n\n\tauxiliaryBounds.init( nV );\n\n\tif ( obtainAuxiliaryWorkingSet( xOpt,yOpt,guessedBounds, &auxiliaryBounds ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\t/* 4) Setup working set of auxiliary QP and setup cholesky decomposition. */\n\tif ( setupAuxiliaryWorkingSet( &auxiliaryBounds,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tnFR = getNFR();\n\t/* At the moment we can only provide a Cholesky of the Hessian if\n\t * the solver is cold-started. */\n\tif (hasCholesky == BT_FALSE || nFR != nV)\n\t\tif (setupCholeskyDecomposition() != SUCCESSFUL_RETURN)\n\t\t\treturn THROWERROR( RET_INIT_FAILED_CHOLESKY );\n\n\t/* 5) Store original QP formulation... */\n\treal_t g_original[NVMAX];\n\treal_t lb_original[NVMAX];\n\treal_t ub_original[NVMAX];\n\n\tfor( i=0; i<nV; ++i )\n\t\tg_original[i] = g[i];\n\tfor( i=0; i<nV; ++i )\n\t\tlb_original[i] = lb[i];\n\tfor( i=0; i<nV; ++i )\n\t\tub_original[i] = ub[i];\n\n\t/* ... and setup QP data of an auxiliary QP having an optimal solution\n\t * as specified by the user (or xOpt = yOpt = 0, by default). */\n\tif ( setupAuxiliaryQPgradient( ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tif ( setupAuxiliaryQPbounds( BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_INIT_FAILED );\n\n\tstatus = QPS_AUXILIARYQPSOLVED;\n\n\n\t/* III) SOLVE ACTUAL INITIAL QP: */\n\t/* Use hotstart method to find the solution of the original initial QP,... */\n\treturnValue returnvalue = hotstart( g_original,lb_original,ub_original, nWSR,0 );\n\n\n\t/* ... check for infeasibility and unboundedness... */\n\tif ( isInfeasible( ) == BT_TRUE )\n\t\treturn THROWERROR( RET_INIT_FAILED_INFEASIBILITY );\n\n\tif ( isUnbounded( ) == BT_TRUE )\n\t\treturn THROWERROR( RET_INIT_FAILED_UNBOUNDEDNESS );\n\n\t/* ... and internal errors. */\n\tif ( ( returnvalue != SUCCESSFUL_RETURN ) && ( returnvalue != RET_MAX_NWSR_REACHED )  &&\n\t     ( returnvalue != RET_INACCURATE_SOLUTION ) && ( returnvalue != RET_NO_SOLUTION ) )\n\t\treturn THROWERROR( RET_INIT_FAILED_HOTSTART );\n\n\n\t/* stop runtime measurement */\n\tif ( cputime != 0 )\n\t\t*cputime = getCPUtime( ) - starttime;\n\n\tif ( printlevel == PL_HIGH )\n\t\tTHROWINFO( RET_INIT_SUCCESSFUL );\n\n\treturn returnvalue;\n}\n\n\n/*\n *\to b t a i n A u x i l i a r y W o r k i n g S e t\n */\nreturnValue QProblemB::obtainAuxiliaryWorkingSet(\tconst real_t* const xOpt, const real_t* const yOpt,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst Bounds* const guessedBounds, Bounds* auxiliaryBounds\n\t\t\t\t\t\t\t\t\t\t\t\t\t) const\n{\n\tint i = 0;\n\tint nV = getNV( );\n\n\n\t/* 1) Ensure that desiredBounds is allocated (and different from guessedBounds). */\n\tif ( ( auxiliaryBounds == 0 ) || ( auxiliaryBounds == guessedBounds ) )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\n\t/* 2) Setup working set for auxiliary initial QP. */\n\tif ( guessedBounds != 0 )\n\t{\n\t\t/* If an initial working set is specific, use it!\n\t\t * Moreover, add all implictly fixed variables if specified. */\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\n\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t{\n\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif ( auxiliaryBounds->setupBound( i,guessedBounds->getStatus( i ) ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t}\n\t\t}\n\t}\n\telse\t/* No initial working set specified. */\n\t{\n\t\tif ( ( xOpt != 0 ) && ( yOpt == 0 ) )\n\t\t{\n\t\t\t/* Obtain initial working set by \"clipping\". */\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t{\n\t\t\t\tif ( xOpt[i] <= lb[i] + BOUNDTOL )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif ( xOpt[i] >= ub[i] - BOUNDTOL )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_UPPER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\t/* Moreover, add all implictly fixed variables if specified. */\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif ( ( xOpt == 0 ) && ( yOpt != 0 ) )\n\t\t{\n\t\t\t/* Obtain initial working set in accordance to sign of dual solution vector. */\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t{\n\t\t\t\tif ( yOpt[i] > ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif ( yOpt[i] < -ZERO )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_UPPER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\t/* Moreover, add all implictly fixed variables if specified. */\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* If xOpt and yOpt are null pointer and no initial working is specified,\n\t\t * start with empty working set (or implicitly fixed bounds only)\n\t\t * for auxiliary QP. */\n\t\tif ( ( xOpt == 0 ) && ( yOpt == 0 ) )\n\t\t{\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t{\n\t\t\t\t/* Only add all implictly fixed variables if specified. */\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_LOWER ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( auxiliaryBounds->setupBound( i,ST_INACTIVE ) != SUCCESSFUL_RETURN )\n\t\t\t\t\t\treturn THROWERROR( RET_OBTAINING_WORKINGSET_FAILED );\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y W o r k i n g S e t\n */\nreturnValue QProblemB::setupAuxiliaryWorkingSet( \tconst Bounds* const auxiliaryBounds,\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType setupAfresh\n\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i;\n\tint nV = getNV( );\n\n\t/* consistency checks */\n\tif ( auxiliaryBounds != 0 )\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tif ( ( bounds.getStatus( i ) == ST_UNDEFINED ) || ( auxiliaryBounds->getStatus( i ) == ST_UNDEFINED ) )\n\t\t\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\t}\n\n\n\t/* I) SETUP CHOLESKY FLAG:\n\t *    Cholesky decomposition shall only be updated if working set\n\t *    shall be updated (i.e. NOT setup afresh!) */\n\tBooleanType updateCholesky;\n\tif ( setupAfresh == BT_TRUE )\n\t\tupdateCholesky = BT_FALSE;\n\telse\n\t\tupdateCholesky = BT_TRUE;\n\n\n\t/* II) REMOVE FORMERLY ACTIVE BOUNDS (IF NECESSARY): */\n\tif ( setupAfresh == BT_FALSE )\n\t{\n\t\t/* Remove all active bounds that shall be inactive AND\n\t\t*  all active bounds that are active at the wrong bound. */\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\n\t\t\tif ( ( bounds.getStatus( i ) == ST_LOWER ) && ( auxiliaryBounds->getStatus( i ) != ST_LOWER ) )\n\t\t\t\tif ( removeBound( i,updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\n\t\t\tif ( ( bounds.getStatus( i ) == ST_UPPER ) && ( auxiliaryBounds->getStatus( i ) != ST_UPPER ) )\n\t\t\t\tif ( removeBound( i,updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\t\t}\n\t}\n\n\n\t/* III) ADD NEWLY ACTIVE BOUNDS: */\n\t/*      Add all inactive bounds that shall be active AND\n\t *      all formerly active bounds that have been active at the wrong bound. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( ( bounds.getStatus( i ) == ST_INACTIVE ) && ( auxiliaryBounds->getStatus( i ) != ST_INACTIVE ) )\n\t\t{\n\t\t\tif ( addBound( i,auxiliaryBounds->getStatus( i ),updateCholesky ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_SETUP_WORKINGSET_FAILED );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y Q P s o l u t i o n\n */\nreturnValue QProblemB::setupAuxiliaryQPsolution(\tconst real_t* const xOpt, const real_t* const yOpt\n\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i;\n\tint nV = getNV( );\n\n\n\t/* Setup primal/dual solution vectors for auxiliary initial QP:\n\t * if a null pointer is passed, a zero vector is assigned;\n\t * old solution vector is kept if pointer to internal solution vector is passed. */\n\tif ( xOpt != 0 )\n\t{\n\t\tif ( xOpt != x )\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t\tx[i] = xOpt[i];\n\t}\n\telse\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tx[i] = 0.0;\n\t}\n\n\tif ( yOpt != 0 )\n\t{\n\t\tif ( yOpt != y )\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t\ty[i] = yOpt[i];\n\t}\n\telse\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\ty[i] = 0.0;\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y Q P g r a d i e n t\n */\nreturnValue QProblemB::setupAuxiliaryQPgradient( )\n{\n\tint i, j;\n\tint nV = getNV( );\n\n\n\t/* Setup gradient vector: g = -H*x + y'*Id. */\n\tfor ( i=0; i<nV; ++i )\n\t{\n\t\t/* y'*Id */\n\t\tg[i] = y[i];\n\n\t\t/* -H*x */\n\t\tfor ( j=0; j<nV; ++j )\n\t\t\tg[i] -= H[i*NVMAX + j] * x[j];\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t u p A u x i l i a r y Q P b o u n d s\n */\nreturnValue QProblemB::setupAuxiliaryQPbounds( BooleanType useRelaxation )\n{\n\tint i;\n\tint nV = getNV( );\n\n\n\t/* Setup bound vectors. */\n\tfor ( i=0; i<nV; ++i )\n\t{\n\t\tswitch ( bounds.getStatus( i ) )\n\t\t{\n\t\t\tcase ST_INACTIVE:\n\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t{\n\t\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t\t{\n\t\t\t\t\t\tlb[i] = x[i];\n\t\t\t\t\t\tub[i] = x[i];\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tlb[i] = x[i] - BOUNDRELAXATION;\n\t\t\t\t\t\tub[i] = x[i] + BOUNDRELAXATION;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase ST_LOWER:\n\t\t\t\tlb[i] = x[i];\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tub[i] = x[i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t\t\tub[i] = x[i] + BOUNDRELAXATION;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tcase ST_UPPER:\n\t\t\t\tub[i] = x[i];\n\t\t\t\tif ( bounds.getType( i ) == ST_EQUALITY )\n\t\t\t\t{\n\t\t\t\t\tlb[i] = x[i];\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tif ( useRelaxation == BT_TRUE )\n\t\t\t\t\t\tlb[i] = x[i] - BOUNDRELAXATION;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ta d d B o u n d\n */\nreturnValue QProblemB::addBound(\tint number, SubjectToStatus B_status,\n\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tint nFR = getNFR( );\n\n\n\t/* consistency check */\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )    ||\n\t\t ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED )            )\n\t{\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\n\t/* Perform cholesky updates only if QProblemB has been initialised! */\n\tif ( ( getStatus( ) == QPS_PREPARINGAUXILIARYQP ) || ( updateCholesky == BT_FALSE ) )\n\t{\n\t\t/* UPDATE INDICES */\n\t\tif ( bounds.moveFreeToFixed( number,B_status ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_ADDBOUND_FAILED );\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\n\n\t/* I) PERFORM CHOLESKY UPDATE: */\n\t/* 1) Index of variable to be added within the list of free variables. */\n\tint number_idx = bounds.getFree( )->getIndex( number );\n\n\treal_t c, s;\n\n\t/* 2) Use row-wise Givens rotations to restore upper triangular form of R. */\n\tfor( i=number_idx+1; i<nFR; ++i )\n\t{\n\t\tcomputeGivens( R[(i-1)*NVMAX + i],R[i*NVMAX + i], R[(i-1)*NVMAX + i],R[i*NVMAX + i],c,s );\n\n\t\tfor( j=(1+i); j<nFR; ++j ) /* last column of R is thrown away */\n\t\t\tapplyGivens( c,s,R[(i-1)*NVMAX + j],R[i*NVMAX + j], R[(i-1)*NVMAX + j],R[i*NVMAX + j] );\n\t}\n\n\t/* 3) Delete <number_idx>th column and ... */\n\tfor( i=0; i<nFR-1; ++i )\n\t\tfor( j=number_idx+1; j<nFR; ++j )\n\t\t\tR[i*NVMAX + j-1] = R[i*NVMAX + j];\n\t/* ... last column of R. */\n\tfor( i=0; i<nFR; ++i )\n\t\tR[i*NVMAX + nFR-1] = 0.0;\n\n\n\t/* II) UPDATE INDICES */\n\tif ( bounds.moveFreeToFixed( number,B_status ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_ADDBOUND_FAILED );\n\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\nreturnValue QProblemB::removeBound(\tint number,\n\t\t\t\t\t\t\t\t\tBooleanType updateCholesky\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, ii;\n\tint nFR = getNFR( );\n\n\n\t/* consistency check */\n\tif ( ( getStatus( ) == QPS_NOTINITIALISED )    ||\n\t\t ( getStatus( ) == QPS_AUXILIARYQPSOLVED ) ||\n\t\t ( getStatus( ) == QPS_HOMOTOPYQPSOLVED )  ||\n\t\t ( getStatus( ) == QPS_SOLVED )            )\n\t{\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\t}\n\n\n\t/* I) UPDATE INDICES */\n\tif ( bounds.moveFixedToFree( number ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\t/* Perform cholesky updates only if QProblemB has been initialised! */\n\tif ( ( getStatus( ) == QPS_PREPARINGAUXILIARYQP ) || ( updateCholesky == BT_FALSE ) )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n\t/* II) PERFORM CHOLESKY UPDATE */\n\tint FR_idx[NVMAX];\n\tif ( bounds.getFree( )->getNumberArray( FR_idx ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\t/* 1) Calculate new column of cholesky decomposition. */\n\treal_t rhs[NVMAX];\n\treal_t r[NVMAX];\n\treal_t r0 = H[number*NVMAX + number];\n\n\tfor( i=0; i<nFR; ++i )\n\t{\n\t\tii = FR_idx[i];\n\t\trhs[i] = H[number*NVMAX + ii];\n\t}\n\n\tif ( backsolveR( rhs,BT_TRUE,BT_TRUE,r ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_REMOVEBOUND_FAILED );\n\n\tfor( i=0; i<nFR; ++i )\n\t\tr0 -= r[i]*r[i];\n\n\t/* 2) Store new column into R. */\n\tfor( i=0; i<nFR; ++i )\n\t\tR[i*NVMAX + nFR] = r[i];\n\n\tif ( r0 > 0.0 )\n\t\tR[nFR*NVMAX + nFR] = sqrt( r0 );\n\telse\n\t{\n\t\thessianType = HST_SEMIDEF;\n\t\treturn THROWERROR( RET_HESSIAN_NOT_SPD );\n\t}\n\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tb a c k s o l v e R  (CODE DUPLICATED IN QProblem CLASS!!!)\n */\nreturnValue QProblemB::backsolveR(\tconst real_t* const b, BooleanType transposed,\n\t\t\t\t\t\t\t\t\treal_t* const a\n\t\t\t\t\t\t\t\t\t)\n{\n\t/* Call standard backsolve procedure (i.e. removingBound == BT_FALSE). */\n\treturn backsolveR( b,transposed,BT_FALSE,a );\n}\n\n\n/*\n *\tb a c k s o l v e R  (CODE DUPLICATED IN QProblem CLASS!!!)\n */\nreturnValue QProblemB::backsolveR(\tconst real_t* const b, BooleanType transposed,\n\t\t\t\t\t\t\t\t\tBooleanType removingBound,\n\t\t\t\t\t\t\t\t\treal_t* const a\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tint nR = getNZ( );\n\n\treal_t sum;\n\n\t/* if backsolve is called while removing a bound, reduce nZ by one. */\n\tif ( removingBound == BT_TRUE )\n\t\t--nR;\n\n\t/* nothing to do */\n\tif ( nR <= 0 )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n\t/* Solve Ra = b, where R might be transposed. */\n\tif ( transposed == BT_FALSE )\n\t{\n\t\t/* solve Ra = b */\n\t\tfor( i=(nR-1); i>=0; --i )\n\t\t{\n\t\t\tsum = b[i];\n\t\t\tfor( j=(i+1); j<nR; ++j )\n\t\t\t\tsum -= R[i*NVMAX + j] * a[j];\n\n\t\t\tif ( getAbs( R[i*NVMAX + i] ) > ZERO )\n\t\t\t\ta[i] = sum / R[i*NVMAX + i];\n\t\t\telse\n\t\t\t\treturn THROWERROR( RET_DIV_BY_ZERO );\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* solve R^T*a = b */\n\t\tfor( i=0; i<nR; ++i )\n\t\t{\n\t\t\tsum = b[i];\n\n\t\t\tfor( j=0; j<i; ++j )\n\t\t\t\tsum -= R[j*NVMAX + i] * a[j];\n\n\t\t\tif ( getAbs( R[i*NVMAX + i] ) > ZERO )\n\t\t\t\ta[i] = sum / R[i*NVMAX + i];\n\t\t\telse\n\t\t\t\treturn THROWERROR( RET_DIV_BY_ZERO );\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ d e t e r m i n e D a t a S h i f t\n */\nreturnValue QProblemB::hotstart_determineDataShift(\tconst int* const FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const g_new, const real_t* const lb_new, const real_t* const ub_new,\n\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_g, real_t* const delta_lb, real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType& Delta_bB_isZero\n\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, ii;\n\tint nV  = getNV( );\n\tint nFX = getNFX( );\n\n\n\t/* 1) Calculate shift directions. */\n\tfor( i=0; i<nV; ++i )\n\t\tdelta_g[i]  = g_new[i]  - g[i];\n\n\tif ( lb_new != 0 )\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tdelta_lb[i] = lb_new[i] - lb[i];\n\t}\n\telse\n\t{\n\t\t/* if no lower bounds exist, assume the new lower bounds to be -infinity */\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tdelta_lb[i] = -INFTY - lb[i];\n\t}\n\n\tif ( ub_new != 0 )\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tdelta_ub[i] = ub_new[i] - ub[i];\n\t}\n\telse\n\t{\n\t\t/* if no upper bounds exist, assume the new upper bounds to be infinity */\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tdelta_ub[i] = INFTY - ub[i];\n\t}\n\n\t/* 2) Determine if active bounds are to be shifted. */\n\tDelta_bB_isZero = BT_TRUE;\n\n\tfor ( i=0; i<nFX; ++i )\n\t{\n\t\tii = FX_idx[i];\n\n\t\tif ( ( getAbs( delta_lb[ii] ) > EPS ) || ( getAbs( delta_ub[ii] ) > EPS ) )\n\t\t{\n\t\t\tDelta_bB_isZero = BT_FALSE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ta r e B o u n d s C o n s i s t e n t\n */\nBooleanType QProblemB::areBoundsConsistent(\tconst real_t* const delta_lb, const real_t* const delta_ub\n\t\t\t\t\t\t\t\t\t\t\t) const\n{\n\tint i;\n\n\t/* Check if delta_lb[i] is greater than delta_ub[i]\n\t * for a component i whose bounds are already (numerically) equal. */\n\tfor( i=0; i<getNV( ); ++i )\n\t\tif ( ( lb[i] > ub[i] - BOUNDTOL ) && ( delta_lb[i] > delta_ub[i] + EPS ) )\n\t\t\treturn BT_FALSE;\n\n\treturn BT_TRUE;\n}\n\n\n/*\n *\ts e t u p Q P d a t a\n */\nreturnValue QProblemB::setupQPdata(\tconst real_t* const _H, const real_t* const _R, const real_t* const _g,\n\t\t\t\t\t\t\t\t\tconst real_t* const _lb, const real_t* const _ub\n\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tint nV = getNV( );\n\n\t/* 1) Setup Hessian matrix and it's Cholesky factorization. */\n\tif (_H != 0)\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tfor( j=0; j<nV; ++j )\n\t\t\t\tH[i*NVMAX + j] = _H[i*nV + j];\n\t\thasHessian = BT_TRUE;\n\t}\n\telse\n\t\thasHessian = BT_FALSE;\n\n\tif (_R != 0)\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tfor( j=0; j<nV; ++j )\n\t\t\t\tR[i*NVMAX + j] = _R[i*nV + j];\n\t\thasCholesky = BT_TRUE;\n\n\t\t/* If Hessian is not provided, store it's factorization in H, and that guy\n\t\t * is going to be used for H * x products (R^T * R * x in this case). */\n\t\tif (hasHessian == BT_FALSE)\n\t\t\tfor( i=0; i<nV; ++i )\n\t\t\t\tfor( j=0; j<nV; ++j )\n\t\t\t\t\tH[i*NVMAX + j] = _R[i*nV + j];\n\t}\n\telse\n\t\thasCholesky = BT_FALSE;\n\n\tif (hasHessian == BT_FALSE && hasCholesky == BT_FALSE)\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* 2) Setup gradient vector. */\n\tif ( _g == 0 )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\tfor( i=0; i<nV; ++i )\n\t\tg[i] = _g[i];\n\n\t/* 3) Setup lower bounds vector. */\n\tif ( _lb != 0 )\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tlb[i] = _lb[i];\n\t}\n\telse\n\t{\n\t\t/* if no lower bounds are specified, set them to -infinity */\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tlb[i] = -INFTY;\n\t}\n\n\t/* 4) Setup upper bounds vector. */\n\tif ( _ub != 0 )\n\t{\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tub[i] = _ub[i];\n\t}\n\telse\n\t{\n\t\t/* if no upper bounds are specified, set them to infinity */\n\t\tfor( i=0; i<nV; ++i )\n\t\t\tub[i] = INFTY;\n\t}\n\n\t//printmatrix( \"H\",H,nV,nV );\n\t//printmatrix( \"R\",R,nV,nV );\n\t//printmatrix( \"g\",g,1,nV );\n\t//printmatrix( \"lb\",lb,1,nV );\n\t//printmatrix( \"ub\",ub,1,nV );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*****************************************************************************\n *  P R I V A T E                                                            *\n *****************************************************************************/\n\n/*\n *\th o t s t a r t _ d e t e r m i n e S t e p D i r e c t i o n\n */\nreturnValue QProblemB::hotstart_determineStepDirection(\tconst int* const FR_idx, const int* const FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g, const real_t* const delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tBooleanType Delta_bB_isZero,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_xFX, real_t* const delta_xFR,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\treal_t* const delta_yFX\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, j, ii, jj;\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\n\n\t/* initialise auxiliary vectors */\n\treal_t HMX_delta_xFX[NVMAX];\n\tfor( i=0; i<nFR; ++i )\n\t\tHMX_delta_xFX[i] = 0.0;\n\n\n\t/* I) DETERMINE delta_xFX */\n\tif ( nFX > 0 )\n\t{\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\n\t\t\tif ( bounds.getStatus( ii ) == ST_LOWER )\n\t\t\t\tdelta_xFX[i] = delta_lb[ii];\n\t\t\telse\n\t\t\t\tdelta_xFX[i] = delta_ub[ii];\n\t\t}\n\t}\n\n\n\t/* II) DETERMINE delta_xFR */\n\tif ( nFR > 0 )\n\t{\n\t\t/* auxiliary variables */\n\t\treal_t delta_xFRz_TMP[NVMAX];\n\t\treal_t delta_xFRz_RHS[NVMAX];\n\n\t\t/* Determine delta_xFRz. */\n\t\tif ( Delta_bB_isZero == BT_FALSE )\n\t\t{\n\t\t\tfor( i=0; i<nFR; ++i )\n\t\t\t{\n\t\t\t\tii = FR_idx[i];\n\t\t\t\tfor( j=0; j<nFX; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FX_idx[j];\n\t\t\t\t\tHMX_delta_xFX[i] += H[ii*NVMAX + jj] * delta_xFX[j];\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif ( Delta_bB_isZero == BT_TRUE )\n\t\t{\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\t\t\t\tdelta_xFRz_RHS[j] = delta_g[jj];\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\t\t\t\tdelta_xFRz_RHS[j] = delta_g[jj] + HMX_delta_xFX[j]; /* *ZFR */\n\t\t\t}\n\t\t}\n\n\t\tfor( i=0; i<nFR; ++i )\n\t\t\tdelta_xFR[i] = -delta_xFRz_RHS[i];\n\n\t\tif ( backsolveR( delta_xFR,BT_TRUE,delta_xFRz_TMP ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_STEPDIRECTION_FAILED_CHOLESKY );\n\n\t\tif ( backsolveR( delta_xFRz_TMP,BT_FALSE,delta_xFR ) != SUCCESSFUL_RETURN )\n\t\t\treturn THROWERROR( RET_STEPDIRECTION_FAILED_CHOLESKY );\n\t}\n\n\n\t/* III) DETERMINE delta_yFX */\n\tif ( nFX > 0 )\n\t{\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\n\t\t\tdelta_yFX[i] = 0.0;\n\t\t\tfor( j=0; j<nFR; ++j )\n\t\t\t{\n\t\t\t\tjj = FR_idx[j];\n\t\t\t\tdelta_yFX[i] += H[ii*NVMAX + jj] * delta_xFR[j];\n\t\t\t}\n\n\t\t\tif ( Delta_bB_isZero == BT_FALSE )\n\t\t\t{\n\t\t\t\tfor( j=0; j<nFX; ++j )\n\t\t\t\t{\n\t\t\t\t\tjj = FX_idx[j];\n\t\t\t\t\tdelta_yFX[i] += H[ii*NVMAX + jj] * delta_xFX[j];\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tdelta_yFX[i] += delta_g[ii];\n\t\t}\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ d e t e r m i n e S t e p L e n g t h\n */\nreturnValue QProblemB::hotstart_determineStepLength(\tconst int* const FR_idx, const int* const FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFR,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yFX,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tint& BC_idx, SubjectToStatus& BC_status\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, ii;\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\n\treal_t tau_tmp;\n\treal_t tau_new = 1.0;\n\n\tBC_idx = 0;\n\tBC_status = ST_UNDEFINED;\n\n\n\t/* I) DETERMINE MAXIMUM DUAL STEPLENGTH, i.e. ensure that\n\t *    active dual bounds remain valid (ignoring implicitly fixed variables): */\n\tfor( i=0; i<nFX; ++i )\n\t{\n\t\tii = FX_idx[i];\n\n\t\tif ( bounds.getType( ii ) != ST_EQUALITY )\n\t\t{\n\t\t\tif ( bounds.getStatus( ii ) == ST_LOWER )\n\t\t\t{\n\t\t\t\t/* 1) Active lower bounds. */\n\t\t\t\tif ( ( delta_yFX[i] < -ZERO ) && ( y[ii] >= 0.0 ) )\n\t\t\t\t{\n\t\t\t\t\ttau_tmp = y[ii] / ( -delta_yFX[i] );\n\t\t\t\t\tif ( tau_tmp < tau_new )\n\t\t\t\t\t{\n\t\t\t\t\t\tif ( tau_tmp >= 0.0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\ttau_new = tau_tmp;\n\t\t\t\t\t\t\tBC_idx = ii;\n\t\t\t\t\t\t\tBC_status = ST_INACTIVE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* 2) Active upper bounds. */\n\t\t\t\tif ( ( delta_yFX[i] > ZERO ) && ( y[ii] <= 0.0 ) )\n\t\t\t\t{\n\t\t\t\t\ttau_tmp = y[ii] / ( -delta_yFX[i] );\n\t\t\t\t\tif ( tau_tmp < tau_new )\n\t\t\t\t\t{\n\t\t\t\t\t\tif ( tau_tmp >= 0.0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\ttau_new = tau_tmp;\n\t\t\t\t\t\t\tBC_idx = ii;\n\t\t\t\t\t\t\tBC_status = ST_INACTIVE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* II) DETERMINE MAXIMUM PRIMAL STEPLENGTH, i.e. ensure that\n\t *     inactive bounds remain valid (ignoring unbounded variables). */\n\t/* 1) Inactive lower bounds. */\n\tif ( bounds.isNoLower( ) == BT_FALSE )\n\t{\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\n\t\t\tif ( bounds.getType( ii ) != ST_UNBOUNDED )\n\t\t\t{\n\t\t\t\tif ( delta_lb[ii] > delta_xFR[i] )\n\t\t\t\t{\n\t\t\t\t\tif ( x[ii] > lb[ii] )\n\t\t\t\t\t\ttau_tmp = ( x[ii] - lb[ii] ) / ( delta_lb[ii] - delta_xFR[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\ttau_tmp = 0.0;\n\n\t\t\t\t\tif ( tau_tmp < tau_new )\n\t\t\t\t\t{\n\t\t\t\t\t\tif ( tau_tmp >= 0.0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\ttau_new = tau_tmp;\n\t\t\t\t\t\t\tBC_idx = ii;\n\t\t\t\t\t\t\tBC_status = ST_LOWER;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* 2) Inactive upper bounds. */\n\tif ( bounds.isNoUpper( ) == BT_FALSE )\n\t{\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\n\t\t\tif ( bounds.getType( ii ) != ST_UNBOUNDED )\n\t\t\t{\n\t\t\t\tif ( delta_ub[ii] < delta_xFR[i] )\n\t\t\t\t{\n\t\t\t\t\tif ( x[ii] < ub[ii] )\n\t\t\t\t\t\ttau_tmp = ( x[ii] - ub[ii] ) / ( delta_ub[ii] - delta_xFR[i] );\n\t\t\t\t\telse\n\t\t\t\t\t\ttau_tmp = 0.0;\n\n\t\t\t\t\tif ( tau_tmp < tau_new )\n\t\t\t\t\t{\n\t\t\t\t\t\tif ( tau_tmp >= 0.0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\ttau_new = tau_tmp;\n\t\t\t\t\t\t\tBC_idx = ii;\n\t\t\t\t\t\t\tBC_status = ST_UPPER;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* III) SET MAXIMUM HOMOTOPY STEPLENGTH */\n\ttau = tau_new;\n\n\tif ( printlevel ==  PL_HIGH )\n\t{\n\t\t#ifdef PC_DEBUG\n\t\tchar messageString[80];\n\n\t\tif ( BC_status == ST_UNDEFINED )\n\t\t\tsprintf( messageString,\"Stepsize is %.6e!\",tau );\n\t\telse\n\t\t\tsprintf( messageString,\"Stepsize is %.6e! (BC_idx = %d, BC_status = %d)\",tau,BC_idx,BC_status );\n\n\t\tgetGlobalMessageHandler( )->throwInfo( RET_STEPSIZE_NONPOSITIVE,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t#endif\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\th o t s t a r t _ p e r f o r m S t e p\n */\nreturnValue QProblemB::hotstart_performStep(\tconst int* const FR_idx, const int* const FX_idx,\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_g, const real_t* const  delta_lb, const real_t* const delta_ub,\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_xFX, const real_t* const delta_xFR,\n\t\t\t\t\t\t\t\t\t\t\t\tconst real_t* const delta_yFX,\n\t\t\t\t\t\t\t\t\t\t\t\tint BC_idx, SubjectToStatus BC_status\n\t\t\t\t\t\t\t\t\t\t\t\t)\n{\n\tint i, ii;\n\tint nV  = getNV( );\n\tint nFR = getNFR( );\n\tint nFX = getNFX( );\n\n\n\t/* I) CHECK BOUNDS' CONSISTENCY */\n\tif ( areBoundsConsistent( delta_lb,delta_ub ) == BT_FALSE )\n\t{\n\t\tinfeasible = BT_TRUE;\n\t\ttau = 0.0;\n\n\t\treturn THROWERROR( RET_QP_INFEASIBLE );\n\t}\n\n\n\t/* II) GO TO ACTIVE SET CHANGE */\n\tif ( tau > ZERO )\n\t{\n\t\t/* 1) Perform step in primal und dual space. */\n\t\tfor( i=0; i<nFR; ++i )\n\t\t{\n\t\t\tii = FR_idx[i];\n\t\t\tx[ii] += tau*delta_xFR[i];\n\t\t}\n\n\t\tfor( i=0; i<nFX; ++i )\n\t\t{\n\t\t\tii = FX_idx[i];\n\t\t\tx[ii] += tau*delta_xFX[i];\n\t\t\ty[ii] += tau*delta_yFX[i];\n\t\t}\n\n\t\t/* 2) Shift QP data. */\n\t\tfor( i=0; i<nV; ++i )\n\t\t{\n\t\t\tg[i]  += tau*delta_g[i];\n\t\t\tlb[i] += tau*delta_lb[i];\n\t\t\tub[i] += tau*delta_ub[i];\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* print a stepsize warning if stepsize is zero */\n\t\t#ifdef PC_DEBUG\n\t\tchar messageString[80];\n\t\tsprintf( messageString,\"Stepsize is %.6e\",tau );\n\t\tgetGlobalMessageHandler( )->throwWarning( RET_STEPSIZE,messageString,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t#endif\n\t}\n\n\n\t/* setup output preferences */\n\t#ifdef PC_DEBUG\n\tchar messageString[80];\n  \tVisibilityStatus visibilityStatus;\n\n  \tif ( printlevel == PL_HIGH )\n\t\tvisibilityStatus = VS_VISIBLE;\n\telse\n\t\tvisibilityStatus = VS_HIDDEN;\n\t#endif\n\n\n\t/* III) UPDATE ACTIVE SET */\n\tswitch ( BC_status )\n\t{\n\t\t/* Optimal solution found as no working set change detected. */\n\t\tcase ST_UNDEFINED:\n\t\t\treturn RET_OPTIMAL_SOLUTION_FOUND;\n\n\n\t\t/* Remove one variable from active set. */\n\t\tcase ST_INACTIVE:\n\t\t\t#ifdef PC_DEBUG\n\t\t\tsprintf( messageString,\"bound no. %d.\", BC_idx );\n\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_REMOVE_FROM_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t#endif\n\n\t\t\tif ( removeBound( BC_idx,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_REMOVE_FROM_ACTIVESET_FAILED );\n\n\t\t\ty[BC_idx] = 0.0;\n\t\t\tbreak;\n\n\n\t\t/* Add one variable to active set. */\n\t\tdefault:\n\t\t\t#ifdef PC_DEBUG\n\t\t\tif ( BC_status == ST_LOWER )\n\t\t\t\tsprintf( messageString,\"lower bound no. %d.\", BC_idx );\n\t\t\telse\n\t\t\t\tsprintf( messageString,\"upper bound no. %d.\", BC_idx );\n\t\t\t\tgetGlobalMessageHandler( )->throwInfo( RET_ADD_TO_ACTIVESET,messageString,__FUNCTION__,__FILE__,__LINE__,visibilityStatus );\n\t\t\t#endif\n\n\t\t\tif ( addBound( BC_idx,BC_status,BT_TRUE ) != SUCCESSFUL_RETURN )\n\t\t\t\treturn THROWERROR( RET_ADD_TO_ACTIVESET_FAILED );\n\t\t\tbreak;\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n#ifdef PC_DEBUG  /* Define print functions only for debugging! */\n\n/*\n *\tp r i n t I t e r a t i o n\n */\nreturnValue QProblemB::printIteration( \tint iteration,\n\t\t\t\t\t\t\t\t\t\tint BC_idx,\tSubjectToStatus BC_status\n\t\t  \t\t\t\t\t\t\t\t)\n{\n\tchar myPrintfString[160];\n\n\t/* consistency check */\n\tif ( iteration < 0 )\n\t\treturn THROWERROR( RET_INVALID_ARGUMENTS );\n\n\t/* nothing to do */\n\tif ( printlevel != PL_MEDIUM )\n\t\treturn SUCCESSFUL_RETURN;\n\n\n\t/* 1) Print header at first iteration. */\n \tif ( iteration == 0 )\n\t{\n\t\tsprintf( myPrintfString,\"\\n##############  qpOASES  --  QP NO.%4.1d  ###############\\n\", count );\n\t\tmyPrintf( myPrintfString );\n\n\t\tsprintf( myPrintfString,\"   Iter   |   StepLength    |       Info      |   nFX   \\n\" );\n\t\tmyPrintf( myPrintfString );\n\t}\n\n\t/* 2) Print iteration line. */\n\tif ( BC_status == ST_UNDEFINED )\n\t{\n\t\tsprintf( myPrintfString,\"   %4.1d   |   %1.5e   |    QP SOLVED    |  %4.1d   \\n\", iteration,tau,getNFX( ) );\n\t\tmyPrintf( myPrintfString );\n\t}\n\telse\n\t{\n\t\tchar info[8];\n\n\t\tif ( BC_status == ST_INACTIVE )\n\t\t\tsprintf( info,\"REM BND\" );\n\t\telse\n\t\t\tsprintf( info,\"ADD BND\" );\n\n\t\tsprintf( myPrintfString,\"   %4.1d   |   %1.5e   |   %s%4.1d   |  %4.1d   \\n\", iteration,tau,info,BC_idx,getNFX( ) );\n\t\tmyPrintf( myPrintfString );\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n#endif  /* PC_DEBUG */\n\n\n\n/*\n *\tc h e c k K K T c o n d i t i o n s\n */\nreturnValue QProblemB::checkKKTconditions( )\n{\n\t#ifdef __PERFORM_KKT_TEST__\n\n\tint i, j;\n\tint nV = getNV( );\n\n\treal_t tmp;\n\treal_t maxKKTviolation = 0.0;\n\n\n\t/* 1) Check for Hx + g - y*A' = 0  (here: A = Id). */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\ttmp = g[i];\n\n\t\tfor( j=0; j<nV; ++j )\n\t\t\ttmp += H[i*nV + j] * x[j];\n\n\t\ttmp -= y[i];\n\n\t\tif ( getAbs( tmp ) > maxKKTviolation )\n\t\t\tmaxKKTviolation = getAbs( tmp );\n\t}\n\n\t/* 2) Check for lb <= x <= ub. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tif ( lb[i] - x[i] > maxKKTviolation )\n\t\t\tmaxKKTviolation = lb[i] - x[i];\n\n\t\tif ( x[i] - ub[i] > maxKKTviolation )\n\t\t\tmaxKKTviolation = x[i] - ub[i];\n\t}\n\n\t/* 3) Check for correct sign of y and for complementary slackness. */\n\tfor( i=0; i<nV; ++i )\n\t{\n\t\tswitch ( bounds.getStatus( i ) )\n\t\t{\n\t\t\tcase ST_LOWER:\n\t\t\t\tif ( -y[i] > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = -y[i];\n\t\t\t\tif ( getAbs( ( x[i] - lb[i] ) * y[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( ( x[i] - lb[i] ) * y[i] );\n\t\t\t\tbreak;\n\n\t\t\tcase ST_UPPER:\n\t\t\t\tif ( y[i] > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = y[i];\n\t\t\t\tif ( getAbs( ( ub[i] - x[i] ) * y[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( ( ub[i] - x[i] ) * y[i] );\n\t\t\t\tbreak;\n\n\t\t\tdefault: /* inactive */\n\t\t\tif ( getAbs( y[i] ) > maxKKTviolation )\n\t\t\t\t\tmaxKKTviolation = getAbs( y[i] );\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif ( maxKKTviolation > CRITICALACCURACY )\n\t\treturn RET_NO_SOLUTION;\n\n\tif ( maxKKTviolation > DESIREDACCURACY )\n\t\treturn RET_INACCURATE_SOLUTION;\n\n\t#endif /* __PERFORM_KKT_TEST__ */\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/QProblemB.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/QProblemB.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of inlined member functions of the QProblemB class which \n *\tis able to use the newly developed online active set strategy for \n *\tparametric quadratic programming.\n */\n\n\n\n#include <math.h>\n\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n/*\n *\tg e t H\n */\ninline returnValue QProblemB::getH( real_t* const _H ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNV( )*getNV( ); ++i )\n\t\t_H[i] = H[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t G\n */\ninline returnValue QProblemB::getG( real_t* const _g ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNV( ); ++i )\n\t\t_g[i] = g[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t L B\n */\ninline returnValue QProblemB::getLB( real_t* const _lb ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNV( ); ++i )\n\t\t_lb[i] = lb[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t L B\n */\ninline returnValue QProblemB::getLB( int number, real_t& value ) const\n{\n\tif ( ( number >= 0 ) && ( number < getNV( ) ) )\n\t{\n\t\tvalue = lb[number];\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t}\n}\n\n\n/*\n *\tg e t U B\n */\ninline returnValue QProblemB::getUB( real_t* const _ub ) const\n{\n\tint i;\n\n\tfor ( i=0; i<getNV( ); ++i )\n\t\t_ub[i] = ub[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t U B\n */\ninline returnValue QProblemB::getUB( int number, real_t& value ) const\n{\n\tif ( ( number >= 0 ) && ( number < getNV( ) ) )\n\t{\n\t\tvalue = ub[number];\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t}\n}\n\n\n/*\n *\tg e t B o u n d s\n */\ninline returnValue QProblemB::getBounds( Bounds* const _bounds ) const\n{\n\t*_bounds = bounds;\n\t\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tg e t N V\n */\ninline int QProblemB::getNV( ) const\n{\n\treturn bounds.getNV( );\n}\n\n\n/*\n *\tg e t N F R\n */\ninline int QProblemB::getNFR( )\n{\n\treturn bounds.getNFR( );\n}\n\n\n/*\n *\tg e t N F X\n */\ninline int QProblemB::getNFX( )\n{\n\treturn bounds.getNFX( );\n}\n\n\n/*\n *\tg e t N F V\n */\ninline int QProblemB::getNFV( ) const\n{\n\treturn bounds.getNFV( );\n}\n\n\n/*\n *\tg e t S t a t u s\n */\ninline QProblemStatus QProblemB::getStatus( ) const\n{\n\treturn status;\n}\n\n\n/*\n *\ti s I n i t i a l i s e d\n */\ninline BooleanType QProblemB::isInitialised( ) const\n{\n\tif ( status == QPS_NOTINITIALISED )\n\t\treturn BT_FALSE;\n\telse\n\t\treturn BT_TRUE;\n}\n\n\n/*\n *\ti s S o l v e d\n */\ninline BooleanType QProblemB::isSolved( ) const\n{\n\tif ( status == QPS_SOLVED )\n\t\treturn BT_TRUE;\n\telse\n\t\treturn BT_FALSE;\n}\n\n\n/*\n *\ti s I n f e a s i b l e\n */\ninline BooleanType QProblemB::isInfeasible( ) const\n{\n\treturn infeasible;\n}\n\n\n/*\n *\ti s U n b o u n d e d\n */\ninline BooleanType QProblemB::isUnbounded( ) const\n{\n\treturn unbounded;\n}\n\n\n/*\n *\tg e t P r i n t L e v e l\n */\ninline PrintLevel QProblemB::getPrintLevel( ) const\n{\n\treturn printlevel;\n}\n\n\n/*\n *\tg e t H e s s i a n T y p e\n */\ninline HessianType QProblemB::getHessianType( ) const\n{\n\treturn hessianType;\n}\n\n\n/*\n *\ts e t H e s s i a n T y p e\n */\ninline returnValue QProblemB::setHessianType( HessianType _hessianType )\n{\n\thessianType = _hessianType;\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*****************************************************************************\n *  P R O T E C T E D                                                        *\n *****************************************************************************/\n\n/*\n *\ts e t H\n */\ninline returnValue QProblemB::setH( const real_t* const H_new )\n{\n\tint i, j;\n\n\tint nV = getNV();\n\n\tfor( i=0; i<nV; ++i )\n\t\tfor( j=0; j<nV; ++j )\n\t\t\tH[i*NVMAX + j] = H_new[i*nV + j];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t G\n */\ninline returnValue QProblemB::setG( const real_t* const g_new )\n{\n\tint i;\n\n\tint nV = getNV();\n\n\tfor( i=0; i<nV; ++i )\n\t\tg[i] = g_new[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t L B\n */\ninline returnValue QProblemB::setLB( const real_t* const lb_new )\n{\n\tint i;\n\n\tint nV = getNV();\n\n\tfor( i=0; i<nV; ++i )\n\t\tlb[i] = lb_new[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t L B\n */\ninline returnValue QProblemB::setLB( int number, real_t value )\n{\n\tif ( ( number >= 0 ) && ( number < getNV( ) ) )\n\t{\n\t\tlb[number] = value;\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t}\n}\n\n\n/*\n *\ts e t U B\n */\ninline returnValue QProblemB::setUB( const real_t* const ub_new )\n{\n\tint i;\n\n\tint nV = getNV();\n\n\tfor( i=0; i<nV; ++i )\n\t\tub[i] = ub_new[i];\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts e t U B\n */\ninline returnValue QProblemB::setUB( int number, real_t value )\n{\n\tif ( ( number >= 0 ) && ( number < getNV( ) ) )\n\t{\n\t\tub[number] = value;\n\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t{\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n\t}\n}\n\n\n/*\n *\tc o m p u t e G i v e n s\n */\ninline void QProblemB::computeGivens(\treal_t xold, real_t yold, real_t& xnew, real_t& ynew,\n\t\t\t\t\t\t\t\t\t\treal_t& c, real_t& s \n\t\t\t\t\t\t\t\t\t\t) const\n{\n    if ( getAbs( yold ) <= ZERO )\n\t{\n        c = 1.0;\n        s = 0.0;\n\t\t\n\t\txnew = xold;\n\t\tynew = yold;\n\t}\n    else\n\t{\n\t\treal_t t, mu;\n\n        mu = getAbs( xold );\n\t\tif ( getAbs( yold ) > mu )\n\t\t\tmu = getAbs( yold );\n\t\t\n        t = mu * sqrt( (xold/mu)*(xold/mu) + (yold/mu)*(yold/mu) );\n\t\t\n\t\tif ( xold < 0.0 )\n            t = -t;\n\t\t\n        c = xold/t;\n        s = yold/t;\n        xnew = t;\n        ynew = 0.0;\n\t}\n\t\n\treturn;\n}\n\n\t\t\n/*\n *\ta p p l y G i v e n s\n */\ninline void QProblemB::applyGivens(\treal_t c, real_t s, real_t xold, real_t yold,\n\t\t\t\t\t\t\t\t\treal_t& xnew, real_t& ynew \n\t\t\t\t\t\t\t\t\t) const\n{\n\t/* Usual Givens plane rotation requiring four multiplications. */\n\txnew =  c*xold + s*yold;\n\tynew = -s*xold + c*yold;\n// \tdouble nu = s/(1.0+c);\n// \n// \txnew = xold*c + yold*s;\n// \tynew = (xnew+xold)*nu - yold;\n\t\n\treturn;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/SubjectTo.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/SubjectTo.cpp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the SubjectTo class designed to manage working sets of\n *\tconstraints and bounds within a QProblem.\n */\n\n\n#include <SubjectTo.hpp>\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n\n\n/*\n *\tS u b j e c t T o\n */\nSubjectTo::SubjectTo( ) :\tnoLower( BT_TRUE ),\n\t\t\t\t\t\t\tnoUpper( BT_TRUE ),\n\t\t\t\t\t\t\tsize( 0 )\n{\n\tint i;\n\n\tfor( i=0; i<size; ++i )\n\t{\n\t\ttype[i] = ST_UNKNOWN;\n\t\tstatus[i] = ST_UNDEFINED;\n\t}\n}\n\n\n/*\n *\tS u b j e c t T o\n */\nSubjectTo::SubjectTo( const SubjectTo& rhs ) :\tnoLower( rhs.noLower ),\n\t\t\t\t\t\t\t\t\t\t\t\tnoUpper( rhs.noUpper ),\n\t\t\t\t\t\t\t\t\t\t\t\tsize( rhs.size )\n{\n\tint i;\n\n\tfor( i=0; i<size; ++i )\n\t{\n\t\ttype[i] = rhs.type[i];\n\t\tstatus[i] = rhs.status[i];\n\t}\n}\n\n\n/*\n *\t~ S u b j e c t T o\n */\nSubjectTo::~SubjectTo( )\n{\n}\n\n\n/*\n *\to p e r a t o r =\n */\nSubjectTo& SubjectTo::operator=( const SubjectTo& rhs )\n{\n\tint i;\n\n\tif ( this != &rhs )\n\t{\n\t\tsize = rhs.size;\n\n\t\tfor( i=0; i<size; ++i )\n\t\t{\n\t\t\ttype[i] = rhs.type[i];\n\t\t\tstatus[i] = rhs.status[i];\n\t\t}\n\n\t\tnoLower = rhs.noLower;\n\t\tnoUpper = rhs.noUpper;\n\t}\n\n\treturn *this;\n}\n\n\n\n/*\n *\ti n i t\n */\nreturnValue SubjectTo::init( int n )\n{\n\tint i;\n\n\tsize = n;\n\n\tnoLower = BT_TRUE;\n\tnoUpper = BT_TRUE;\n\n\tfor( i=0; i<size; ++i )\n\t{\n\t\ttype[i] = ST_UNKNOWN;\n\t\tstatus[i] = ST_UNDEFINED;\n\t}\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n\n/*****************************************************************************\n *  P R O T E C T E D                                                        *\n *****************************************************************************/\n\n/*\n *\ta d d I n d e x\n */\nreturnValue SubjectTo::addIndex(\tIndexlist* const indexlist,\n\t\t\t\t\t\t\t\t\tint newnumber, SubjectToStatus newstatus\n\t\t\t\t\t\t\t\t\t)\n{\n\t/* consistency check */\n\tif ( status[newnumber] == newstatus )\n\t\treturn THROWERROR( RET_INDEX_ALREADY_OF_DESIRED_STATUS );\n\n\tstatus[newnumber] = newstatus;\n\n\tif ( indexlist->addNumber( newnumber ) == RET_INDEXLIST_EXCEEDS_MAX_LENGTH )\n\t\treturn THROWERROR( RET_ADDINDEX_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tr e m o v e I n d e x\n */\nreturnValue SubjectTo::removeIndex(\tIndexlist* const indexlist, \n\t\t\t\t\t\t\t\t\tint removenumber\n\t\t\t\t\t\t\t\t\t)\n{\n\tstatus[removenumber] = ST_UNDEFINED;\n\n\tif ( indexlist->removeNumber( removenumber ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_UNKNOWN_BUG );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\ts w a p I n d e x\n */\nreturnValue SubjectTo::swapIndex(\tIndexlist* const indexlist,\n\t\t\t\t\t\t\t\t\tint number1, int number2\n\t\t\t\t\t\t\t\t\t)\n{\n\t/* consistency checks */\n\tif ( status[number1] != status[number2] )\n\t\treturn THROWERROR( RET_SWAPINDEX_FAILED );\n\n\tif ( number1 == number2 )\n\t{\n\t\tTHROWWARNING( RET_NOTHING_TO_DO );\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\n\tif ( indexlist->swapNumbers( number1,number2 ) != SUCCESSFUL_RETURN )\n\t\treturn THROWERROR( RET_SWAPINDEX_FAILED );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/SubjectTo.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/SubjectTo.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of the inlined member functions of the SubjectTo class \n *\tdesigned to manage working sets of constraints and bounds within a QProblem.\n */\n\n\n/*****************************************************************************\n *  P U B L I C                                                              *\n *****************************************************************************/\n \n\n/*\n *\tg e t T y p e\n */\ninline SubjectToType SubjectTo::getType( int i ) const\n{\n\tif ( ( i >= 0 ) && ( i < size ) )\n\t\treturn type[i];\n\telse\n\t\treturn ST_UNKNOWN;\n}\n\n\n/*\n *\tg e t S t a t u s\n */\ninline SubjectToStatus SubjectTo::getStatus( int i ) const\n{\n\tif ( ( i >= 0 ) && ( i < size ) )\n\t\treturn status[i];\n\telse\n\t\treturn ST_UNDEFINED;\n}\n\n\n/*\n *\ts e t T y p e\n */\ninline returnValue SubjectTo::setType( int i, SubjectToType value )\n{\n\tif ( ( i >= 0 ) && ( i < size ) )\n\t{\n\t\ttype[i] = value;\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\ts e t S t a t u s\n */\ninline returnValue SubjectTo::setStatus( int i, SubjectToStatus value )\n{\n\tif ( ( i >= 0 ) && ( i < size ) )\n\t{\n\t\tstatus[i] = value;\n\t\treturn SUCCESSFUL_RETURN;\n\t}\n\telse\n\t\treturn THROWERROR( RET_INDEX_OUT_OF_BOUNDS );\n}\n\n\n/*\n *\ts e t N o L o w e r\n */\ninline void SubjectTo::setNoLower( BooleanType _status )\n{\n\tnoLower = _status;\n}\n \n\n/*\n *\ts e t N o U p p e r\n */\ninline void SubjectTo::setNoUpper( BooleanType _status )\n{\n\tnoUpper = _status;\n}\n\n\n/*\n *\ti s N o L o w e r\n */\ninline BooleanType SubjectTo::isNoLower( ) const\n{\n\treturn noLower;\n}\n\n \n/*\n *\ti s N o L o w e r\n */\ninline BooleanType SubjectTo::isNoUpper( ) const\n{\n\treturn noUpper;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Utils.cpp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n/**\n *\t\\file SRC/Utils.cpp\n *\t\\author Hans Joachim Ferreau, Eckhard Arnold\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of some inlined utilities for working with the different QProblem\n *  classes.\n */\n\n\n#include <math.h>\n\n#if defined(__WIN32__) || defined(WIN32)\n  #include <windows.h>\n#elif defined(LINUX)\n  #include <sys/stat.h>\n  #include <sys/time.h>\n#endif\n\n#ifdef __MATLAB__\n  #include <mex.h>\n#endif\n\n\n#include <Utils.hpp>\n\n\n\n#ifdef PC_DEBUG  /* Define print functions only for debugging! */\n/*\n *\tp r i n t\n */\nreturnValue print( const real_t* const v, int n )\n{\n\tint i;\n\tchar myPrintfString[160];\n\n\t/* Print a vector. */\n\tmyPrintf( \"[\\t\" );\n\tfor( i=0; i<n; ++i )\n\t{\n\t\tsprintf( myPrintfString,\" %.16e\\t\", v[i] );\n\t\tmyPrintf( myPrintfString );\n\t}\n\tmyPrintf( \"]\\n\" );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print(\tconst real_t* const v, int n,\n\t\t\t\t\tconst int* const V_idx\n\t\t\t\t\t)\n{\n\tint i;\n\tchar myPrintfString[160];\n\n\t/* Print a permuted vector. */\n\tmyPrintf( \"[\\t\" );\n\tfor( i=0; i<n; ++i )\n\t{\n\t\tsprintf( myPrintfString,\" %.16e\\t\", v[ V_idx[i] ] );\n\t\tmyPrintf( myPrintfString );\n\t}\n\tmyPrintf( \"]\\n\" );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print(\tconst real_t* const v, int n,\n\t\t\t\t\tconst char* name\n\t\t\t\t\t)\n{\n\tchar myPrintfString[160];\n\n\t/* Print vector name ... */\n\tsprintf( myPrintfString,\"%s = \", name );\n\tmyPrintf( myPrintfString );\n\n\t/* ... and the vector itself. */\n\treturn print( v, n );\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print( const real_t* const M, int nrow, int ncol )\n{\n\tint i;\n\n\t/* Print a matrix as a collection of row vectors. */\n\tfor( i=0; i<nrow; ++i )\n\t\tprint( &(M[i*ncol]), ncol );\n\tmyPrintf( \"\\n\" );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print(\tconst real_t* const M, int nrow, int ncol,\n\t\t\t\t\tconst int* const ROW_idx, const int* const COL_idx\n\t\t\t\t\t)\n{\n\tint i;\n\n\t/* Print a permuted matrix as a collection of permuted row vectors. */\n\tfor( i=0; i<nrow; ++i )\n\t\tprint( &( M[ ROW_idx[i]*ncol ] ), ncol, COL_idx );\n\tmyPrintf( \"\\n\" );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print(\tconst real_t* const M, int nrow, int ncol,\n\t\t\t\t\tconst char* name\n\t\t\t\t\t)\n{\n\tchar myPrintfString[160];\n\n\t/* Print matrix name ... */\n\tsprintf( myPrintfString,\"%s = \", name );\n\tmyPrintf( myPrintfString );\n\n\t/* ... and the matrix itself. */\n\treturn print( M, nrow, ncol );\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print( const int* const index, int n )\n{\n\tint i;\n\tchar myPrintfString[160];\n\n\t/* Print a indexlist. */\n\tmyPrintf( \"[\\t\" );\n\tfor( i=0; i<n; ++i )\n\t{\n\t\tsprintf( myPrintfString,\" %d\\t\", index[i] );\n\t\tmyPrintf( myPrintfString );\n\t}\n\tmyPrintf( \"]\\n\" );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t\n */\nreturnValue print(\tconst int* const index, int n,\n\t\t\t\t\tconst char* name\n\t\t\t\t\t)\n{\n\tchar myPrintfString[160];\n\n\t/* Print indexlist name ... */\n\tsprintf( myPrintfString,\"%s = \", name );\n\tmyPrintf( myPrintfString );\n\n\t/* ... and the indexlist itself. */\n\treturn print( index, n );\n}\n\n\n/*\n *\tm y P r i n t f\n */\nreturnValue myPrintf( const char* s )\n{\n\t#ifdef __MATLAB__\n\tmexPrintf( s );\n\t#else\n\tmyFILE* outputfile = getGlobalMessageHandler( )->getOutputFile( );\n\tif ( outputfile == 0 )\n\t\treturn THROWERROR( RET_NO_GLOBAL_MESSAGE_OUTPUTFILE );\n\n\tfprintf( outputfile, \"%s\", s );\n\t#endif\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tp r i n t C o p y r i g h t N o t i c e\n */\nreturnValue printCopyrightNotice( )\n{\n\treturn myPrintf( \"\\nqpOASES -- An Implementation of the Online Active Set Strategy.\\nCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\\n\\nqpOASES is distributed under the terms of the \\nGNU Lesser General Public License 2.1 in the hope that it will be \\nuseful, but WITHOUT ANY WARRANTY; without even the implied warranty \\nof MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \\nSee the GNU Lesser General Public License for more details.\\n\\n\" );\n}\n\n\n/*\n *\tr e a d F r o m F i l e\n */\nreturnValue readFromFile(\treal_t* data, int nrow, int ncol,\n\t\t\t\t\t\t\tconst char* datafilename\n\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tfloat float_data;\n\tmyFILE* datafile;\n\n\t/* 1) Open file. */\n\tif ( ( datafile = fopen( datafilename, \"r\" ) ) == 0 )\n\t{\n\t\tchar errstr[80];\n\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_OPEN_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t}\n\n\t/* 2) Read data from file. */\n\tfor( i=0; i<nrow; ++i )\n\t{\n\t\tfor( j=0; j<ncol; ++j )\n\t\t{\n\t\t\tif ( fscanf( datafile, \"%f \", &float_data ) == 0 )\n\t\t\t{\n\t\t\t\tfclose( datafile );\n\t\t\t\tchar errstr[80];\n\t\t\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\t\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_READ_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t\t}\n\t\t\tdata[i*ncol + j] = ( (real_t) float_data );\n\t\t}\n\t}\n\n\t/* 3) Close file. */\n\tfclose( datafile );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tr e a d F r o m F i l e\n */\nreturnValue readFromFile(\treal_t* data, int n,\n\t\t\t\t\t\t\tconst char* datafilename\n\t\t\t\t\t\t\t)\n{\n\treturn readFromFile( data, n, 1, datafilename );\n}\n\n\n\n/*\n *\tr e a d F r o m F i l e\n */\nreturnValue readFromFile(\tint* data, int n,\n\t\t\t\t\t\t\tconst char* datafilename\n\t\t\t\t\t\t\t)\n{\n\tint i;\n\tmyFILE* datafile;\n\n\t/* 1) Open file. */\n\tif ( ( datafile = fopen( datafilename, \"r\" ) ) == 0 )\n\t{\n\t\tchar errstr[80];\n\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_OPEN_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t}\n\n\t/* 2) Read data from file. */\n\tfor( i=0; i<n; ++i )\n\t{\n\t\tif ( fscanf( datafile, \"%d\\n\", &(data[i]) ) == 0 )\n\t\t{\n\t\t\tfclose( datafile );\n\t\t\tchar errstr[80];\n\t\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_READ_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t}\n\t}\n\n\t/* 3) Close file. */\n\tfclose( datafile );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tw r i t e I n t o F i l e\n */\nreturnValue writeIntoFile(\tconst real_t* const data, int nrow, int ncol,\n\t\t\t\t\t\t\tconst char* datafilename, BooleanType append\n\t\t\t\t\t\t\t)\n{\n\tint i, j;\n\tmyFILE* datafile;\n\n\t/* 1) Open file. */\n\tif ( append == BT_TRUE )\n\t{\n\t\t/* append data */\n\t\tif ( ( datafile = fopen( datafilename, \"a\" ) ) == 0 )\n\t\t{\n\t\t\tchar errstr[80];\n\t\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_OPEN_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* do not append data */\n\t\tif ( ( datafile = fopen( datafilename, \"w\" ) ) == 0 )\n\t\t{\n\t\t\tchar errstr[80];\n\t\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_OPEN_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t}\n\t}\n\n\t/* 2) Write data into file. */\n\tfor( i=0; i<nrow; ++i )\n\t{\n\t\tfor( j=0; j<ncol; ++j )\n\t\t \tfprintf( datafile, \"%.16e \", data[i*ncol+j] );\n\n\t\tfprintf( datafile, \"\\n\" );\n\t}\n\n\t/* 3) Close file. */\n\tfclose( datafile );\n\n\treturn SUCCESSFUL_RETURN;\n}\n\n\n/*\n *\tw r i t e I n t o F i l e\n */\nreturnValue writeIntoFile(\tconst real_t* const data, int n,\n\t\t\t\t\t\t\tconst char* datafilename, BooleanType append\n\t\t\t\t\t\t\t)\n{\n\treturn writeIntoFile( data,1,n,datafilename,append );\n}\n\n\n/*\n *\tw r i t e I n t o F i l e\n */\nreturnValue writeIntoFile(\tconst int* const data, int n,\n\t\t\t\t\t\t\tconst char* datafilename, BooleanType append\n\t\t\t\t\t\t\t)\n{\n\tint i;\n\n\tmyFILE* datafile;\n\n\t/* 1) Open file. */\n\tif ( append == BT_TRUE )\n\t{\n\t\t/* append data */\n\t\tif ( ( datafile = fopen( datafilename, \"a\" ) ) == 0 )\n\t\t{\n\t\t\tchar errstr[80];\n\t\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_OPEN_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* do not append data */\n\t\tif ( ( datafile = fopen( datafilename, \"w\" ) ) == 0 )\n\t\t{\n\t\t\tchar errstr[80];\n\t\t\tsprintf( errstr,\"(%s)\",datafilename );\n\t\t\treturn getGlobalMessageHandler( )->throwError( RET_UNABLE_TO_OPEN_FILE,errstr,__FUNCTION__,__FILE__,__LINE__,VS_VISIBLE );\n\t\t}\n\t}\n\n\t/* 2) Write data into file. */\n\tfor( i=0; i<n; ++i )\n\t\tfprintf( datafile, \"%d\\n\", data[i] );\n\n\t/* 3) Close file. */\n\tfclose( datafile );\n\n\treturn SUCCESSFUL_RETURN;\n}\n#endif  /* PC_DEBUG */\n\n\n/*\n *\tg e t C P U t i m e\n */\nreal_t getCPUtime( )\n{\n\treal_t current_time = -1.0;\n\n\t#if defined(__WIN32__) || defined(WIN32)\n\tLARGE_INTEGER counter, frequency;\n\tQueryPerformanceFrequency(&frequency);\n\tQueryPerformanceCounter(&counter);\n\tcurrent_time = ((real_t) counter.QuadPart) / ((real_t) frequency.QuadPart);\n\t#elif defined(LINUX)\n\tstruct timeval theclock;\n\tgettimeofday( &theclock,0 );\n\tcurrent_time = 1.0*theclock.tv_sec + 1.0e-6*theclock.tv_usec;\n\t#endif\n\n\treturn current_time;\n}\n\n\n/*\n *\tg e t N o r m\n */\nreal_t getNorm( const real_t* const v, int n )\n{\n\tint i;\n\n\treal_t norm = 0.0;\n\n\tfor( i=0; i<n; ++i )\n\t\tnorm += v[i]*v[i];\n\n\treturn sqrt( norm );\n}\n\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/SRC/Utils.ipp",
    "content": "/*\n *\tThis file is part of qpOASES.\n *\n *\tqpOASES -- An Implementation of the Online Active Set Strategy.\n *\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n *\n *\tqpOASES is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tqpOASES is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with qpOASES; if not, write to the Free Software\n *\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n *\n */\n\n\n\n/**\n *\t\\file SRC/Utils.ipp\n *\t\\author Hans Joachim Ferreau\n *\t\\version 1.3embedded\n *\t\\date 2007-2008\n *\n *\tImplementation of some inlined utilities for working with the different QProblem \n *  classes.\n */\n\n\n\n/*\n *\tg e t A b s\n */\ninline real_t getAbs( real_t x )\n{\n\tif ( x < 0.0 )\n\t\treturn -x;\n\telse\n\t\treturn x;\n}\n\n\n/*\n *\tend of file\n */\n"
  },
  {
    "path": "phonelibs/qpoases/VERSIONS.txt",
    "content": "##\n##\tqpOASES -- An Implementation of the Online Active Set Strategy.\n##\tCopyright (C) 2007-2008 by Hans Joachim Ferreau et al. All rights reserved.\n##\n##\tqpOASES is free software; you can redistribute it and/or\n##\tmodify it under the terms of the GNU Lesser General Public\n##\tLicense as published by the Free Software Foundation; either\n##\tversion 2.1 of the License, or (at your option) any later version.\n##\n##\tqpOASES is distributed in the hope that it will be useful,\n##\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n##\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n##\tLesser General Public License for more details.\n##\n##\tYou should have received a copy of the GNU Lesser General Public\n##\tLicense along with qpOASES; if not, write to the Free Software\n##\tFoundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n##\n\n\n\nVERSION HISTORY\n===============\n\n1.3embedded (last updated on 30th April 2009):\n-----------------------------------------------------------------------\n\n+ Re-programming of internal memory management to avoid dynamic memory allocations \n+ Most #ifdef directives removed\n+ Almost all type definitions gathered within INCLUDE/Types.hpp\n+ Irrelevant functionality removed (like the SQProblem class, functionality \n  for loading data from files or the SCILAB interface)\n+ Replacement of all doubles by real_t\n+ Introduction of define \"PC_DEBUG\" for switching off all print functions\n+ stdio.h was made optional, string.h is no longer needed\n+ relative paths removed from #include directives\n+ made auxiliary objects locally static within solveInitialQP()\n+ Matlab interface fixed for single precision\n+ New return value -2 from Legacy wrapper added to Matlab/Simulink interfaces\n+ KKT optimality check moved into QProblem(B) class, SolutionAnalysis class removed\n\n\n1.3 (released on 2nd June 2008, last updated on 19th June 2008):\n-----------------------------------------------------------------------\n\n+ Implementation of \"initialised homotopy\" concept\n+ Addition of the SolutionAnalysis class\n+ Utility functions for solving test problems in OQP format added\n+ Flexibility of Matlab(R) interface enhanced\n+ Major source code cleanup\n  (Attention: a few class names and calling interfaces have changed!)\n\n\n\n1.2 (released on 9th October 2007):\n-----------------------------------------------------------------------\n\n+ Special treatment of diagonal Hessians\n+ Improved infeasibility detection\n+ Further improved Matlab(R) interface\n+ Extended Simulink(R) interface\n+ scilab interface added\n+ Code cleanup and several bugfixes\n\n\n\n1.1 (released on 8th July 2007):\n--------------------------------\n\n+ Implementation of the QProblemB class\n+ Basic implementation of the SQProblem class\n+ Improved Matlab(R) interface\n+ Enabling/Disabling of constraints introduced\n+ Several bugfixes\n\n\n\n1.0 (released on 17th April 2007):\n----------------------------------\n\nInitial release.\n\n\n\n##\n##\tend of file\n##\n"
  },
  {
    "path": "phonelibs/qrcode/QrCode.cc",
    "content": "/* \n * QR Code generator library (C++)\n * \n * Copyright (c) Project Nayuki. (MIT License)\n * https://www.nayuki.io/page/qr-code-generator-library\n * \n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n * - The above copyright notice and this permission notice shall be included in\n *   all copies or substantial portions of the Software.\n * - The Software is provided \"as is\", without warranty of any kind, express or\n *   implied, including but not limited to the warranties of merchantability,\n *   fitness for a particular purpose and noninfringement. In no event shall the\n *   authors or copyright holders be liable for any claim, damages or other\n *   liability, whether in an action of contract, tort or otherwise, arising from,\n *   out of or in connection with the Software or the use or other dealings in the\n *   Software.\n */\n\n#include <algorithm>\n#include <climits>\n#include <cstddef>\n#include <cstdlib>\n#include <cstring>\n#include <sstream>\n#include <stdexcept>\n#include <utility>\n#include \"QrCode.hpp\"\n\nusing std::int8_t;\nusing std::uint8_t;\nusing std::size_t;\nusing std::vector;\n\n\nnamespace qrcodegen {\n\nQrSegment::Mode::Mode(int mode, int cc0, int cc1, int cc2) :\n\t\tmodeBits(mode) {\n\tnumBitsCharCount[0] = cc0;\n\tnumBitsCharCount[1] = cc1;\n\tnumBitsCharCount[2] = cc2;\n}\n\n\nint QrSegment::Mode::getModeBits() const {\n\treturn modeBits;\n}\n\n\nint QrSegment::Mode::numCharCountBits(int ver) const {\n\treturn numBitsCharCount[(ver + 7) / 17];\n}\n\n\nconst QrSegment::Mode QrSegment::Mode::NUMERIC     (0x1, 10, 12, 14);\nconst QrSegment::Mode QrSegment::Mode::ALPHANUMERIC(0x2,  9, 11, 13);\nconst QrSegment::Mode QrSegment::Mode::BYTE        (0x4,  8, 16, 16);\nconst QrSegment::Mode QrSegment::Mode::KANJI       (0x8,  8, 10, 12);\nconst QrSegment::Mode QrSegment::Mode::ECI         (0x7,  0,  0,  0);\n\n\nQrSegment QrSegment::makeBytes(const vector<uint8_t> &data) {\n\tif (data.size() > static_cast<unsigned int>(INT_MAX))\n\t\tthrow std::length_error(\"Data too long\");\n\tBitBuffer bb;\n\tfor (uint8_t b : data)\n\t\tbb.appendBits(b, 8);\n\treturn QrSegment(Mode::BYTE, static_cast<int>(data.size()), std::move(bb));\n}\n\n\nQrSegment QrSegment::makeNumeric(const char *digits) {\n\tBitBuffer bb;\n\tint accumData = 0;\n\tint accumCount = 0;\n\tint charCount = 0;\n\tfor (; *digits != '\\0'; digits++, charCount++) {\n\t\tchar c = *digits;\n\t\tif (c < '0' || c > '9')\n\t\t\tthrow std::domain_error(\"String contains non-numeric characters\");\n\t\taccumData = accumData * 10 + (c - '0');\n\t\taccumCount++;\n\t\tif (accumCount == 3) {\n\t\t\tbb.appendBits(static_cast<uint32_t>(accumData), 10);\n\t\t\taccumData = 0;\n\t\t\taccumCount = 0;\n\t\t}\n\t}\n\tif (accumCount > 0)  // 1 or 2 digits remaining\n\t\tbb.appendBits(static_cast<uint32_t>(accumData), accumCount * 3 + 1);\n\treturn QrSegment(Mode::NUMERIC, charCount, std::move(bb));\n}\n\n\nQrSegment QrSegment::makeAlphanumeric(const char *text) {\n\tBitBuffer bb;\n\tint accumData = 0;\n\tint accumCount = 0;\n\tint charCount = 0;\n\tfor (; *text != '\\0'; text++, charCount++) {\n\t\tconst char *temp = std::strchr(ALPHANUMERIC_CHARSET, *text);\n\t\tif (temp == nullptr)\n\t\t\tthrow std::domain_error(\"String contains unencodable characters in alphanumeric mode\");\n\t\taccumData = accumData * 45 + static_cast<int>(temp - ALPHANUMERIC_CHARSET);\n\t\taccumCount++;\n\t\tif (accumCount == 2) {\n\t\t\tbb.appendBits(static_cast<uint32_t>(accumData), 11);\n\t\t\taccumData = 0;\n\t\t\taccumCount = 0;\n\t\t}\n\t}\n\tif (accumCount > 0)  // 1 character remaining\n\t\tbb.appendBits(static_cast<uint32_t>(accumData), 6);\n\treturn QrSegment(Mode::ALPHANUMERIC, charCount, std::move(bb));\n}\n\n\nvector<QrSegment> QrSegment::makeSegments(const char *text) {\n\t// Select the most efficient segment encoding automatically\n\tvector<QrSegment> result;\n\tif (*text == '\\0');  // Leave result empty\n\telse if (isNumeric(text))\n\t\tresult.push_back(makeNumeric(text));\n\telse if (isAlphanumeric(text))\n\t\tresult.push_back(makeAlphanumeric(text));\n\telse {\n\t\tvector<uint8_t> bytes;\n\t\tfor (; *text != '\\0'; text++)\n\t\t\tbytes.push_back(static_cast<uint8_t>(*text));\n\t\tresult.push_back(makeBytes(bytes));\n\t}\n\treturn result;\n}\n\n\nQrSegment QrSegment::makeEci(long assignVal) {\n\tBitBuffer bb;\n\tif (assignVal < 0)\n\t\tthrow std::domain_error(\"ECI assignment value out of range\");\n\telse if (assignVal < (1 << 7))\n\t\tbb.appendBits(static_cast<uint32_t>(assignVal), 8);\n\telse if (assignVal < (1 << 14)) {\n\t\tbb.appendBits(2, 2);\n\t\tbb.appendBits(static_cast<uint32_t>(assignVal), 14);\n\t} else if (assignVal < 1000000L) {\n\t\tbb.appendBits(6, 3);\n\t\tbb.appendBits(static_cast<uint32_t>(assignVal), 21);\n\t} else\n\t\tthrow std::domain_error(\"ECI assignment value out of range\");\n\treturn QrSegment(Mode::ECI, 0, std::move(bb));\n}\n\n\nQrSegment::QrSegment(Mode md, int numCh, const std::vector<bool> &dt) :\n\t\tmode(md),\n\t\tnumChars(numCh),\n\t\tdata(dt) {\n\tif (numCh < 0)\n\t\tthrow std::domain_error(\"Invalid value\");\n}\n\n\nQrSegment::QrSegment(Mode md, int numCh, std::vector<bool> &&dt) :\n\t\tmode(md),\n\t\tnumChars(numCh),\n\t\tdata(std::move(dt)) {\n\tif (numCh < 0)\n\t\tthrow std::domain_error(\"Invalid value\");\n}\n\n\nint QrSegment::getTotalBits(const vector<QrSegment> &segs, int version) {\n\tint result = 0;\n\tfor (const QrSegment &seg : segs) {\n\t\tint ccbits = seg.mode.numCharCountBits(version);\n\t\tif (seg.numChars >= (1L << ccbits))\n\t\t\treturn -1;  // The segment's length doesn't fit the field's bit width\n\t\tif (4 + ccbits > INT_MAX - result)\n\t\t\treturn -1;  // The sum will overflow an int type\n\t\tresult += 4 + ccbits;\n\t\tif (seg.data.size() > static_cast<unsigned int>(INT_MAX - result))\n\t\t\treturn -1;  // The sum will overflow an int type\n\t\tresult += static_cast<int>(seg.data.size());\n\t}\n\treturn result;\n}\n\n\nbool QrSegment::isAlphanumeric(const char *text) {\n\tfor (; *text != '\\0'; text++) {\n\t\tif (std::strchr(ALPHANUMERIC_CHARSET, *text) == nullptr)\n\t\t\treturn false;\n\t}\n\treturn true;\n}\n\n\nbool QrSegment::isNumeric(const char *text) {\n\tfor (; *text != '\\0'; text++) {\n\t\tchar c = *text;\n\t\tif (c < '0' || c > '9')\n\t\t\treturn false;\n\t}\n\treturn true;\n}\n\n\nQrSegment::Mode QrSegment::getMode() const {\n\treturn mode;\n}\n\n\nint QrSegment::getNumChars() const {\n\treturn numChars;\n}\n\n\nconst std::vector<bool> &QrSegment::getData() const {\n\treturn data;\n}\n\n\nconst char *QrSegment::ALPHANUMERIC_CHARSET = \"0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ $%*+-./:\";\n\n\n\nint QrCode::getFormatBits(Ecc ecl) {\n\tswitch (ecl) {\n\t\tcase Ecc::LOW     :  return 1;\n\t\tcase Ecc::MEDIUM  :  return 0;\n\t\tcase Ecc::QUARTILE:  return 3;\n\t\tcase Ecc::HIGH    :  return 2;\n\t\tdefault:  throw std::logic_error(\"Assertion error\");\n\t}\n}\n\n\nQrCode QrCode::encodeText(const char *text, Ecc ecl) {\n\tvector<QrSegment> segs = QrSegment::makeSegments(text);\n\treturn encodeSegments(segs, ecl);\n}\n\n\nQrCode QrCode::encodeBinary(const vector<uint8_t> &data, Ecc ecl) {\n\tvector<QrSegment> segs{QrSegment::makeBytes(data)};\n\treturn encodeSegments(segs, ecl);\n}\n\n\nQrCode QrCode::encodeSegments(const vector<QrSegment> &segs, Ecc ecl,\n\t\tint minVersion, int maxVersion, int mask, bool boostEcl) {\n\tif (!(MIN_VERSION <= minVersion && minVersion <= maxVersion && maxVersion <= MAX_VERSION) || mask < -1 || mask > 7)\n\t\tthrow std::invalid_argument(\"Invalid value\");\n\t\n\t// Find the minimal version number to use\n\tint version, dataUsedBits;\n\tfor (version = minVersion; ; version++) {\n\t\tint dataCapacityBits = getNumDataCodewords(version, ecl) * 8;  // Number of data bits available\n\t\tdataUsedBits = QrSegment::getTotalBits(segs, version);\n\t\tif (dataUsedBits != -1 && dataUsedBits <= dataCapacityBits)\n\t\t\tbreak;  // This version number is found to be suitable\n\t\tif (version >= maxVersion) {  // All versions in the range could not fit the given data\n\t\t\tstd::ostringstream sb;\n\t\t\tif (dataUsedBits == -1)\n\t\t\t\tsb << \"Segment too long\";\n\t\t\telse {\n\t\t\t\tsb << \"Data length = \" << dataUsedBits << \" bits, \";\n\t\t\t\tsb << \"Max capacity = \" << dataCapacityBits << \" bits\";\n\t\t\t}\n\t\t\tthrow data_too_long(sb.str());\n\t\t}\n\t}\n\tif (dataUsedBits == -1)\n\t\tthrow std::logic_error(\"Assertion error\");\n\t\n\t// Increase the error correction level while the data still fits in the current version number\n\tfor (Ecc newEcl : vector<Ecc>{Ecc::MEDIUM, Ecc::QUARTILE, Ecc::HIGH}) {  // From low to high\n\t\tif (boostEcl && dataUsedBits <= getNumDataCodewords(version, newEcl) * 8)\n\t\t\tecl = newEcl;\n\t}\n\t\n\t// Concatenate all segments to create the data bit string\n\tBitBuffer bb;\n\tfor (const QrSegment &seg : segs) {\n\t\tbb.appendBits(static_cast<uint32_t>(seg.getMode().getModeBits()), 4);\n\t\tbb.appendBits(static_cast<uint32_t>(seg.getNumChars()), seg.getMode().numCharCountBits(version));\n\t\tbb.insert(bb.end(), seg.getData().begin(), seg.getData().end());\n\t}\n\tif (bb.size() != static_cast<unsigned int>(dataUsedBits))\n\t\tthrow std::logic_error(\"Assertion error\");\n\t\n\t// Add terminator and pad up to a byte if applicable\n\tsize_t dataCapacityBits = static_cast<size_t>(getNumDataCodewords(version, ecl)) * 8;\n\tif (bb.size() > dataCapacityBits)\n\t\tthrow std::logic_error(\"Assertion error\");\n\tbb.appendBits(0, std::min(4, static_cast<int>(dataCapacityBits - bb.size())));\n\tbb.appendBits(0, (8 - static_cast<int>(bb.size() % 8)) % 8);\n\tif (bb.size() % 8 != 0)\n\t\tthrow std::logic_error(\"Assertion error\");\n\t\n\t// Pad with alternating bytes until data capacity is reached\n\tfor (uint8_t padByte = 0xEC; bb.size() < dataCapacityBits; padByte ^= 0xEC ^ 0x11)\n\t\tbb.appendBits(padByte, 8);\n\t\n\t// Pack bits into bytes in big endian\n\tvector<uint8_t> dataCodewords(bb.size() / 8);\n\tfor (size_t i = 0; i < bb.size(); i++)\n\t\tdataCodewords[i >> 3] |= (bb.at(i) ? 1 : 0) << (7 - (i & 7));\n\t\n\t// Create the QR Code object\n\treturn QrCode(version, ecl, dataCodewords, mask);\n}\n\n\nQrCode::QrCode(int ver, Ecc ecl, const vector<uint8_t> &dataCodewords, int msk) :\n\t\t// Initialize fields and check arguments\n\t\tversion(ver),\n\t\terrorCorrectionLevel(ecl) {\n\tif (ver < MIN_VERSION || ver > MAX_VERSION)\n\t\tthrow std::domain_error(\"Version value out of range\");\n\tif (msk < -1 || msk > 7)\n\t\tthrow std::domain_error(\"Mask value out of range\");\n\tsize = ver * 4 + 17;\n\tsize_t sz = static_cast<size_t>(size);\n\tmodules    = vector<vector<bool> >(sz, vector<bool>(sz));  // Initially all white\n\tisFunction = vector<vector<bool> >(sz, vector<bool>(sz));\n\t\n\t// Compute ECC, draw modules\n\tdrawFunctionPatterns();\n\tconst vector<uint8_t> allCodewords = addEccAndInterleave(dataCodewords);\n\tdrawCodewords(allCodewords);\n\t\n\t// Do masking\n\tif (msk == -1) {  // Automatically choose best mask\n\t\tlong minPenalty = LONG_MAX;\n\t\tfor (int i = 0; i < 8; i++) {\n\t\t\tapplyMask(i);\n\t\t\tdrawFormatBits(i);\n\t\t\tlong penalty = getPenaltyScore();\n\t\t\tif (penalty < minPenalty) {\n\t\t\t\tmsk = i;\n\t\t\t\tminPenalty = penalty;\n\t\t\t}\n\t\t\tapplyMask(i);  // Undoes the mask due to XOR\n\t\t}\n\t}\n\tif (msk < 0 || msk > 7)\n\t\tthrow std::logic_error(\"Assertion error\");\n\tthis->mask = msk;\n\tapplyMask(msk);  // Apply the final choice of mask\n\tdrawFormatBits(msk);  // Overwrite old format bits\n\t\n\tisFunction.clear();\n\tisFunction.shrink_to_fit();\n}\n\n\nint QrCode::getVersion() const {\n\treturn version;\n}\n\n\nint QrCode::getSize() const {\n\treturn size;\n}\n\n\nQrCode::Ecc QrCode::getErrorCorrectionLevel() const {\n\treturn errorCorrectionLevel;\n}\n\n\nint QrCode::getMask() const {\n\treturn mask;\n}\n\n\nbool QrCode::getModule(int x, int y) const {\n\treturn 0 <= x && x < size && 0 <= y && y < size && module(x, y);\n}\n\n\nstd::string QrCode::toSvgString(int border) const {\n\tif (border < 0)\n\t\tthrow std::domain_error(\"Border must be non-negative\");\n\tif (border > INT_MAX / 2 || border * 2 > INT_MAX - size)\n\t\tthrow std::overflow_error(\"Border too large\");\n\t\n\tstd::ostringstream sb;\n\tsb << \"<?xml version=\\\"1.0\\\" encoding=\\\"UTF-8\\\"?>\\n\";\n\tsb << \"<!DOCTYPE svg PUBLIC \\\"-//W3C//DTD SVG 1.1//EN\\\" \\\"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd\\\">\\n\";\n\tsb << \"<svg xmlns=\\\"http://www.w3.org/2000/svg\\\" version=\\\"1.1\\\" viewBox=\\\"0 0 \";\n\tsb << (size + border * 2) << \" \" << (size + border * 2) << \"\\\" stroke=\\\"none\\\">\\n\";\n\tsb << \"\\t<rect width=\\\"100%\\\" height=\\\"100%\\\" fill=\\\"#FFFFFF\\\"/>\\n\";\n\tsb << \"\\t<path d=\\\"\";\n\tfor (int y = 0; y < size; y++) {\n\t\tfor (int x = 0; x < size; x++) {\n\t\t\tif (getModule(x, y)) {\n\t\t\t\tif (x != 0 || y != 0)\n\t\t\t\t\tsb << \" \";\n\t\t\t\tsb << \"M\" << (x + border) << \",\" << (y + border) << \"h1v1h-1z\";\n\t\t\t}\n\t\t}\n\t}\n\tsb << \"\\\" fill=\\\"#000000\\\"/>\\n\";\n\tsb << \"</svg>\\n\";\n\treturn sb.str();\n}\n\n\nvoid QrCode::drawFunctionPatterns() {\n\t// Draw horizontal and vertical timing patterns\n\tfor (int i = 0; i < size; i++) {\n\t\tsetFunctionModule(6, i, i % 2 == 0);\n\t\tsetFunctionModule(i, 6, i % 2 == 0);\n\t}\n\t\n\t// Draw 3 finder patterns (all corners except bottom right; overwrites some timing modules)\n\tdrawFinderPattern(3, 3);\n\tdrawFinderPattern(size - 4, 3);\n\tdrawFinderPattern(3, size - 4);\n\t\n\t// Draw numerous alignment patterns\n\tconst vector<int> alignPatPos = getAlignmentPatternPositions();\n\tsize_t numAlign = alignPatPos.size();\n\tfor (size_t i = 0; i < numAlign; i++) {\n\t\tfor (size_t j = 0; j < numAlign; j++) {\n\t\t\t// Don't draw on the three finder corners\n\t\t\tif (!((i == 0 && j == 0) || (i == 0 && j == numAlign - 1) || (i == numAlign - 1 && j == 0)))\n\t\t\t\tdrawAlignmentPattern(alignPatPos.at(i), alignPatPos.at(j));\n\t\t}\n\t}\n\t\n\t// Draw configuration data\n\tdrawFormatBits(0);  // Dummy mask value; overwritten later in the constructor\n\tdrawVersion();\n}\n\n\nvoid QrCode::drawFormatBits(int msk) {\n\t// Calculate error correction code and pack bits\n\tint data = getFormatBits(errorCorrectionLevel) << 3 | msk;  // errCorrLvl is uint2, msk is uint3\n\tint rem = data;\n\tfor (int i = 0; i < 10; i++)\n\t\trem = (rem << 1) ^ ((rem >> 9) * 0x537);\n\tint bits = (data << 10 | rem) ^ 0x5412;  // uint15\n\tif (bits >> 15 != 0)\n\t\tthrow std::logic_error(\"Assertion error\");\n\t\n\t// Draw first copy\n\tfor (int i = 0; i <= 5; i++)\n\t\tsetFunctionModule(8, i, getBit(bits, i));\n\tsetFunctionModule(8, 7, getBit(bits, 6));\n\tsetFunctionModule(8, 8, getBit(bits, 7));\n\tsetFunctionModule(7, 8, getBit(bits, 8));\n\tfor (int i = 9; i < 15; i++)\n\t\tsetFunctionModule(14 - i, 8, getBit(bits, i));\n\t\n\t// Draw second copy\n\tfor (int i = 0; i < 8; i++)\n\t\tsetFunctionModule(size - 1 - i, 8, getBit(bits, i));\n\tfor (int i = 8; i < 15; i++)\n\t\tsetFunctionModule(8, size - 15 + i, getBit(bits, i));\n\tsetFunctionModule(8, size - 8, true);  // Always black\n}\n\n\nvoid QrCode::drawVersion() {\n\tif (version < 7)\n\t\treturn;\n\t\n\t// Calculate error correction code and pack bits\n\tint rem = version;  // version is uint6, in the range [7, 40]\n\tfor (int i = 0; i < 12; i++)\n\t\trem = (rem << 1) ^ ((rem >> 11) * 0x1F25);\n\tlong bits = static_cast<long>(version) << 12 | rem;  // uint18\n\tif (bits >> 18 != 0)\n\t\tthrow std::logic_error(\"Assertion error\");\n\t\n\t// Draw two copies\n\tfor (int i = 0; i < 18; i++) {\n\t\tbool bit = getBit(bits, i);\n\t\tint a = size - 11 + i % 3;\n\t\tint b = i / 3;\n\t\tsetFunctionModule(a, b, bit);\n\t\tsetFunctionModule(b, a, bit);\n\t}\n}\n\n\nvoid QrCode::drawFinderPattern(int x, int y) {\n\tfor (int dy = -4; dy <= 4; dy++) {\n\t\tfor (int dx = -4; dx <= 4; dx++) {\n\t\t\tint dist = std::max(std::abs(dx), std::abs(dy));  // Chebyshev/infinity norm\n\t\t\tint xx = x + dx, yy = y + dy;\n\t\t\tif (0 <= xx && xx < size && 0 <= yy && yy < size)\n\t\t\t\tsetFunctionModule(xx, yy, dist != 2 && dist != 4);\n\t\t}\n\t}\n}\n\n\nvoid QrCode::drawAlignmentPattern(int x, int y) {\n\tfor (int dy = -2; dy <= 2; dy++) {\n\t\tfor (int dx = -2; dx <= 2; dx++)\n\t\t\tsetFunctionModule(x + dx, y + dy, std::max(std::abs(dx), std::abs(dy)) != 1);\n\t}\n}\n\n\nvoid QrCode::setFunctionModule(int x, int y, bool isBlack) {\n\tsize_t ux = static_cast<size_t>(x);\n\tsize_t uy = static_cast<size_t>(y);\n\tmodules   .at(uy).at(ux) = isBlack;\n\tisFunction.at(uy).at(ux) = true;\n}\n\n\nbool QrCode::module(int x, int y) const {\n\treturn modules.at(static_cast<size_t>(y)).at(static_cast<size_t>(x));\n}\n\n\nvector<uint8_t> QrCode::addEccAndInterleave(const vector<uint8_t> &data) const {\n\tif (data.size() != static_cast<unsigned int>(getNumDataCodewords(version, errorCorrectionLevel)))\n\t\tthrow std::invalid_argument(\"Invalid argument\");\n\t\n\t// Calculate parameter numbers\n\tint numBlocks = NUM_ERROR_CORRECTION_BLOCKS[static_cast<int>(errorCorrectionLevel)][version];\n\tint blockEccLen = ECC_CODEWORDS_PER_BLOCK  [static_cast<int>(errorCorrectionLevel)][version];\n\tint rawCodewords = getNumRawDataModules(version) / 8;\n\tint numShortBlocks = numBlocks - rawCodewords % numBlocks;\n\tint shortBlockLen = rawCodewords / numBlocks;\n\t\n\t// Split data into blocks and append ECC to each block\n\tvector<vector<uint8_t> > blocks;\n\tconst vector<uint8_t> rsDiv = reedSolomonComputeDivisor(blockEccLen);\n\tfor (int i = 0, k = 0; i < numBlocks; i++) {\n\t\tvector<uint8_t> dat(data.cbegin() + k, data.cbegin() + (k + shortBlockLen - blockEccLen + (i < numShortBlocks ? 0 : 1)));\n\t\tk += static_cast<int>(dat.size());\n\t\tconst vector<uint8_t> ecc = reedSolomonComputeRemainder(dat, rsDiv);\n\t\tif (i < numShortBlocks)\n\t\t\tdat.push_back(0);\n\t\tdat.insert(dat.end(), ecc.cbegin(), ecc.cend());\n\t\tblocks.push_back(std::move(dat));\n\t}\n\t\n\t// Interleave (not concatenate) the bytes from every block into a single sequence\n\tvector<uint8_t> result;\n\tfor (size_t i = 0; i < blocks.at(0).size(); i++) {\n\t\tfor (size_t j = 0; j < blocks.size(); j++) {\n\t\t\t// Skip the padding byte in short blocks\n\t\t\tif (i != static_cast<unsigned int>(shortBlockLen - blockEccLen) || j >= static_cast<unsigned int>(numShortBlocks))\n\t\t\t\tresult.push_back(blocks.at(j).at(i));\n\t\t}\n\t}\n\tif (result.size() != static_cast<unsigned int>(rawCodewords))\n\t\tthrow std::logic_error(\"Assertion error\");\n\treturn result;\n}\n\n\nvoid QrCode::drawCodewords(const vector<uint8_t> &data) {\n\tif (data.size() != static_cast<unsigned int>(getNumRawDataModules(version) / 8))\n\t\tthrow std::invalid_argument(\"Invalid argument\");\n\t\n\tsize_t i = 0;  // Bit index into the data\n\t// Do the funny zigzag scan\n\tfor (int right = size - 1; right >= 1; right -= 2) {  // Index of right column in each column pair\n\t\tif (right == 6)\n\t\t\tright = 5;\n\t\tfor (int vert = 0; vert < size; vert++) {  // Vertical counter\n\t\t\tfor (int j = 0; j < 2; j++) {\n\t\t\t\tsize_t x = static_cast<size_t>(right - j);  // Actual x coordinate\n\t\t\t\tbool upward = ((right + 1) & 2) == 0;\n\t\t\t\tsize_t y = static_cast<size_t>(upward ? size - 1 - vert : vert);  // Actual y coordinate\n\t\t\t\tif (!isFunction.at(y).at(x) && i < data.size() * 8) {\n\t\t\t\t\tmodules.at(y).at(x) = getBit(data.at(i >> 3), 7 - static_cast<int>(i & 7));\n\t\t\t\t\ti++;\n\t\t\t\t}\n\t\t\t\t// If this QR Code has any remainder bits (0 to 7), they were assigned as\n\t\t\t\t// 0/false/white by the constructor and are left unchanged by this method\n\t\t\t}\n\t\t}\n\t}\n\tif (i != data.size() * 8)\n\t\tthrow std::logic_error(\"Assertion error\");\n}\n\n\nvoid QrCode::applyMask(int msk) {\n\tif (msk < 0 || msk > 7)\n\t\tthrow std::domain_error(\"Mask value out of range\");\n\tsize_t sz = static_cast<size_t>(size);\n\tfor (size_t y = 0; y < sz; y++) {\n\t\tfor (size_t x = 0; x < sz; x++) {\n\t\t\tbool invert;\n\t\t\tswitch (msk) {\n\t\t\t\tcase 0:  invert = (x + y) % 2 == 0;                    break;\n\t\t\t\tcase 1:  invert = y % 2 == 0;                          break;\n\t\t\t\tcase 2:  invert = x % 3 == 0;                          break;\n\t\t\t\tcase 3:  invert = (x + y) % 3 == 0;                    break;\n\t\t\t\tcase 4:  invert = (x / 3 + y / 2) % 2 == 0;            break;\n\t\t\t\tcase 5:  invert = x * y % 2 + x * y % 3 == 0;          break;\n\t\t\t\tcase 6:  invert = (x * y % 2 + x * y % 3) % 2 == 0;    break;\n\t\t\t\tcase 7:  invert = ((x + y) % 2 + x * y % 3) % 2 == 0;  break;\n\t\t\t\tdefault:  throw std::logic_error(\"Assertion error\");\n\t\t\t}\n\t\t\tmodules.at(y).at(x) = modules.at(y).at(x) ^ (invert & !isFunction.at(y).at(x));\n\t\t}\n\t}\n}\n\n\nlong QrCode::getPenaltyScore() const {\n\tlong result = 0;\n\t\n\t// Adjacent modules in row having same color, and finder-like patterns\n\tfor (int y = 0; y < size; y++) {\n\t\tbool runColor = false;\n\t\tint runX = 0;\n\t\tstd::array<int,7> runHistory = {};\n\t\tfor (int x = 0; x < size; x++) {\n\t\t\tif (module(x, y) == runColor) {\n\t\t\t\trunX++;\n\t\t\t\tif (runX == 5)\n\t\t\t\t\tresult += PENALTY_N1;\n\t\t\t\telse if (runX > 5)\n\t\t\t\t\tresult++;\n\t\t\t} else {\n\t\t\t\tfinderPenaltyAddHistory(runX, runHistory);\n\t\t\t\tif (!runColor)\n\t\t\t\t\tresult += finderPenaltyCountPatterns(runHistory) * PENALTY_N3;\n\t\t\t\trunColor = module(x, y);\n\t\t\t\trunX = 1;\n\t\t\t}\n\t\t}\n\t\tresult += finderPenaltyTerminateAndCount(runColor, runX, runHistory) * PENALTY_N3;\n\t}\n\t// Adjacent modules in column having same color, and finder-like patterns\n\tfor (int x = 0; x < size; x++) {\n\t\tbool runColor = false;\n\t\tint runY = 0;\n\t\tstd::array<int,7> runHistory = {};\n\t\tfor (int y = 0; y < size; y++) {\n\t\t\tif (module(x, y) == runColor) {\n\t\t\t\trunY++;\n\t\t\t\tif (runY == 5)\n\t\t\t\t\tresult += PENALTY_N1;\n\t\t\t\telse if (runY > 5)\n\t\t\t\t\tresult++;\n\t\t\t} else {\n\t\t\t\tfinderPenaltyAddHistory(runY, runHistory);\n\t\t\t\tif (!runColor)\n\t\t\t\t\tresult += finderPenaltyCountPatterns(runHistory) * PENALTY_N3;\n\t\t\t\trunColor = module(x, y);\n\t\t\t\trunY = 1;\n\t\t\t}\n\t\t}\n\t\tresult += finderPenaltyTerminateAndCount(runColor, runY, runHistory) * PENALTY_N3;\n\t}\n\t\n\t// 2*2 blocks of modules having same color\n\tfor (int y = 0; y < size - 1; y++) {\n\t\tfor (int x = 0; x < size - 1; x++) {\n\t\t\tbool  color = module(x, y);\n\t\t\tif (  color == module(x + 1, y) &&\n\t\t\t      color == module(x, y + 1) &&\n\t\t\t      color == module(x + 1, y + 1))\n\t\t\t\tresult += PENALTY_N2;\n\t\t}\n\t}\n\t\n\t// Balance of black and white modules\n\tint black = 0;\n\tfor (const vector<bool> &row : modules) {\n\t\tfor (bool color : row) {\n\t\t\tif (color)\n\t\t\t\tblack++;\n\t\t}\n\t}\n\tint total = size * size;  // Note that size is odd, so black/total != 1/2\n\t// Compute the smallest integer k >= 0 such that (45-5k)% <= black/total <= (55+5k)%\n\tint k = static_cast<int>((std::abs(black * 20L - total * 10L) + total - 1) / total) - 1;\n\tresult += k * PENALTY_N4;\n\treturn result;\n}\n\n\nvector<int> QrCode::getAlignmentPatternPositions() const {\n\tif (version == 1)\n\t\treturn vector<int>();\n\telse {\n\t\tint numAlign = version / 7 + 2;\n\t\tint step = (version == 32) ? 26 :\n\t\t\t(version*4 + numAlign*2 + 1) / (numAlign*2 - 2) * 2;\n\t\tvector<int> result;\n\t\tfor (int i = 0, pos = size - 7; i < numAlign - 1; i++, pos -= step)\n\t\t\tresult.insert(result.begin(), pos);\n\t\tresult.insert(result.begin(), 6);\n\t\treturn result;\n\t}\n}\n\n\nint QrCode::getNumRawDataModules(int ver) {\n\tif (ver < MIN_VERSION || ver > MAX_VERSION)\n\t\tthrow std::domain_error(\"Version number out of range\");\n\tint result = (16 * ver + 128) * ver + 64;\n\tif (ver >= 2) {\n\t\tint numAlign = ver / 7 + 2;\n\t\tresult -= (25 * numAlign - 10) * numAlign - 55;\n\t\tif (ver >= 7)\n\t\t\tresult -= 36;\n\t}\n\tif (!(208 <= result && result <= 29648))\n\t\tthrow std::logic_error(\"Assertion error\");\n\treturn result;\n}\n\n\nint QrCode::getNumDataCodewords(int ver, Ecc ecl) {\n\treturn getNumRawDataModules(ver) / 8\n\t\t- ECC_CODEWORDS_PER_BLOCK    [static_cast<int>(ecl)][ver]\n\t\t* NUM_ERROR_CORRECTION_BLOCKS[static_cast<int>(ecl)][ver];\n}\n\n\nvector<uint8_t> QrCode::reedSolomonComputeDivisor(int degree) {\n\tif (degree < 1 || degree > 255)\n\t\tthrow std::domain_error(\"Degree out of range\");\n\t// Polynomial coefficients are stored from highest to lowest power, excluding the leading term which is always 1.\n\t// For example the polynomial x^3 + 255x^2 + 8x + 93 is stored as the uint8 array {255, 8, 93}.\n\tvector<uint8_t> result(static_cast<size_t>(degree));\n\tresult.at(result.size() - 1) = 1;  // Start off with the monomial x^0\n\t\n\t// Compute the product polynomial (x - r^0) * (x - r^1) * (x - r^2) * ... * (x - r^{degree-1}),\n\t// and drop the highest monomial term which is always 1x^degree.\n\t// Note that r = 0x02, which is a generator element of this field GF(2^8/0x11D).\n\tuint8_t root = 1;\n\tfor (int i = 0; i < degree; i++) {\n\t\t// Multiply the current product by (x - r^i)\n\t\tfor (size_t j = 0; j < result.size(); j++) {\n\t\t\tresult.at(j) = reedSolomonMultiply(result.at(j), root);\n\t\t\tif (j + 1 < result.size())\n\t\t\t\tresult.at(j) ^= result.at(j + 1);\n\t\t}\n\t\troot = reedSolomonMultiply(root, 0x02);\n\t}\n\treturn result;\n}\n\n\nvector<uint8_t> QrCode::reedSolomonComputeRemainder(const vector<uint8_t> &data, const vector<uint8_t> &divisor) {\n\tvector<uint8_t> result(divisor.size());\n\tfor (uint8_t b : data) {  // Polynomial division\n\t\tuint8_t factor = b ^ result.at(0);\n\t\tresult.erase(result.begin());\n\t\tresult.push_back(0);\n\t\tfor (size_t i = 0; i < result.size(); i++)\n\t\t\tresult.at(i) ^= reedSolomonMultiply(divisor.at(i), factor);\n\t}\n\treturn result;\n}\n\n\nuint8_t QrCode::reedSolomonMultiply(uint8_t x, uint8_t y) {\n\t// Russian peasant multiplication\n\tint z = 0;\n\tfor (int i = 7; i >= 0; i--) {\n\t\tz = (z << 1) ^ ((z >> 7) * 0x11D);\n\t\tz ^= ((y >> i) & 1) * x;\n\t}\n\tif (z >> 8 != 0)\n\t\tthrow std::logic_error(\"Assertion error\");\n\treturn static_cast<uint8_t>(z);\n}\n\n\nint QrCode::finderPenaltyCountPatterns(const std::array<int,7> &runHistory) const {\n\tint n = runHistory.at(1);\n\tif (n > size * 3)\n\t\tthrow std::logic_error(\"Assertion error\");\n\tbool core = n > 0 && runHistory.at(2) == n && runHistory.at(3) == n * 3 && runHistory.at(4) == n && runHistory.at(5) == n;\n\treturn (core && runHistory.at(0) >= n * 4 && runHistory.at(6) >= n ? 1 : 0)\n\t     + (core && runHistory.at(6) >= n * 4 && runHistory.at(0) >= n ? 1 : 0);\n}\n\n\nint QrCode::finderPenaltyTerminateAndCount(bool currentRunColor, int currentRunLength, std::array<int,7> &runHistory) const {\n\tif (currentRunColor) {  // Terminate black run\n\t\tfinderPenaltyAddHistory(currentRunLength, runHistory);\n\t\tcurrentRunLength = 0;\n\t}\n\tcurrentRunLength += size;  // Add white border to final run\n\tfinderPenaltyAddHistory(currentRunLength, runHistory);\n\treturn finderPenaltyCountPatterns(runHistory);\n}\n\n\nvoid QrCode::finderPenaltyAddHistory(int currentRunLength, std::array<int,7> &runHistory) const {\n\tif (runHistory.at(0) == 0)\n\t\tcurrentRunLength += size;  // Add white border to initial run\n\tstd::copy_backward(runHistory.cbegin(), runHistory.cend() - 1, runHistory.end());\n\trunHistory.at(0) = currentRunLength;\n}\n\n\nbool QrCode::getBit(long x, int i) {\n\treturn ((x >> i) & 1) != 0;\n}\n\n\n/*---- Tables of constants ----*/\n\nconst int QrCode::PENALTY_N1 =  3;\nconst int QrCode::PENALTY_N2 =  3;\nconst int QrCode::PENALTY_N3 = 40;\nconst int QrCode::PENALTY_N4 = 10;\n\n\nconst int8_t QrCode::ECC_CODEWORDS_PER_BLOCK[4][41] = {\n\t// Version: (note that index 0 is for padding, and is set to an illegal value)\n\t//0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40    Error correction level\n\t{-1,  7, 10, 15, 20, 26, 18, 20, 24, 30, 18, 20, 24, 26, 30, 22, 24, 28, 30, 28, 28, 28, 28, 30, 30, 26, 28, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30},  // Low\n\t{-1, 10, 16, 26, 18, 24, 16, 18, 22, 22, 26, 30, 22, 22, 24, 24, 28, 28, 26, 26, 26, 26, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28},  // Medium\n\t{-1, 13, 22, 18, 26, 18, 24, 18, 22, 20, 24, 28, 26, 24, 20, 30, 24, 28, 28, 26, 30, 28, 30, 30, 30, 30, 28, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30},  // Quartile\n\t{-1, 17, 28, 22, 16, 22, 28, 26, 26, 24, 28, 24, 28, 22, 24, 24, 30, 28, 28, 26, 28, 30, 24, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30},  // High\n};\n\nconst int8_t QrCode::NUM_ERROR_CORRECTION_BLOCKS[4][41] = {\n\t// Version: (note that index 0 is for padding, and is set to an illegal value)\n\t//0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40    Error correction level\n\t{-1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 4,  4,  4,  4,  4,  6,  6,  6,  6,  7,  8,  8,  9,  9, 10, 12, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 24, 25},  // Low\n\t{-1, 1, 1, 1, 2, 2, 4, 4, 4, 5, 5,  5,  8,  9,  9, 10, 10, 11, 13, 14, 16, 17, 17, 18, 20, 21, 23, 25, 26, 28, 29, 31, 33, 35, 37, 38, 40, 43, 45, 47, 49},  // Medium\n\t{-1, 1, 1, 2, 2, 4, 4, 6, 6, 8, 8,  8, 10, 12, 16, 12, 17, 16, 18, 21, 20, 23, 23, 25, 27, 29, 34, 34, 35, 38, 40, 43, 45, 48, 51, 53, 56, 59, 62, 65, 68},  // Quartile\n\t{-1, 1, 1, 2, 4, 4, 4, 5, 6, 8, 8, 11, 11, 16, 16, 18, 16, 19, 21, 25, 25, 25, 34, 30, 32, 35, 37, 40, 42, 45, 48, 51, 54, 57, 60, 63, 66, 70, 74, 77, 81},  // High\n};\n\n\ndata_too_long::data_too_long(const std::string &msg) :\n\tstd::length_error(msg) {}\n\n\n\nBitBuffer::BitBuffer()\n\t: std::vector<bool>() {}\n\n\nvoid BitBuffer::appendBits(std::uint32_t val, int len) {\n\tif (len < 0 || len > 31 || val >> len != 0)\n\t\tthrow std::domain_error(\"Value out of range\");\n\tfor (int i = len - 1; i >= 0; i--)  // Append bit by bit\n\t\tthis->push_back(((val >> i) & 1) != 0);\n}\n\n}\n"
  },
  {
    "path": "phonelibs/qrcode/QrCode.hpp",
    "content": "/* \n * QR Code generator library (C++)\n * \n * Copyright (c) Project Nayuki. (MIT License)\n * https://www.nayuki.io/page/qr-code-generator-library\n * \n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n * - The above copyright notice and this permission notice shall be included in\n *   all copies or substantial portions of the Software.\n * - The Software is provided \"as is\", without warranty of any kind, express or\n *   implied, including but not limited to the warranties of merchantability,\n *   fitness for a particular purpose and noninfringement. In no event shall the\n *   authors or copyright holders be liable for any claim, damages or other\n *   liability, whether in an action of contract, tort or otherwise, arising from,\n *   out of or in connection with the Software or the use or other dealings in the\n *   Software.\n */\n\n#pragma once\n\n#include <array>\n#include <cstdint>\n#include <stdexcept>\n#include <string>\n#include <vector>\n\n\nnamespace qrcodegen {\n\n/* \n * A segment of character/binary/control data in a QR Code symbol.\n * Instances of this class are immutable.\n * The mid-level way to create a segment is to take the payload data\n * and call a static factory function such as QrSegment::makeNumeric().\n * The low-level way to create a segment is to custom-make the bit buffer\n * and call the QrSegment() constructor with appropriate values.\n * This segment class imposes no length restrictions, but QR Codes have restrictions.\n * Even in the most favorable conditions, a QR Code can only hold 7089 characters of data.\n * Any segment longer than this is meaningless for the purpose of generating QR Codes.\n */\nclass QrSegment final {\n\t\n\t/*---- Public helper enumeration ----*/\n\t\n\t/* \n\t * Describes how a segment's data bits are interpreted. Immutable.\n\t */\n\tpublic: class Mode final {\n\t\t\n\t\t/*-- Constants --*/\n\t\t\n\t\tpublic: static const Mode NUMERIC;\n\t\tpublic: static const Mode ALPHANUMERIC;\n\t\tpublic: static const Mode BYTE;\n\t\tpublic: static const Mode KANJI;\n\t\tpublic: static const Mode ECI;\n\t\t\n\t\t\n\t\t/*-- Fields --*/\n\t\t\n\t\t// The mode indicator bits, which is a uint4 value (range 0 to 15).\n\t\tprivate: int modeBits;\n\t\t\n\t\t// Number of character count bits for three different version ranges.\n\t\tprivate: int numBitsCharCount[3];\n\t\t\n\t\t\n\t\t/*-- Constructor --*/\n\t\t\n\t\tprivate: Mode(int mode, int cc0, int cc1, int cc2);\n\t\t\n\t\t\n\t\t/*-- Methods --*/\n\t\t\n\t\t/* \n\t\t * (Package-private) Returns the mode indicator bits, which is an unsigned 4-bit value (range 0 to 15).\n\t\t */\n\t\tpublic: int getModeBits() const;\n\t\t\n\t\t/* \n\t\t * (Package-private) Returns the bit width of the character count field for a segment in\n\t\t * this mode in a QR Code at the given version number. The result is in the range [0, 16].\n\t\t */\n\t\tpublic: int numCharCountBits(int ver) const;\n\t\t\n\t};\n\t\n\t\n\t\n\t/*---- Static factory functions (mid level) ----*/\n\t\n\t/* \n\t * Returns a segment representing the given binary data encoded in\n\t * byte mode. All input byte vectors are acceptable. Any text string\n\t * can be converted to UTF-8 bytes and encoded as a byte mode segment.\n\t */\n\tpublic: static QrSegment makeBytes(const std::vector<std::uint8_t> &data);\n\t\n\t\n\t/* \n\t * Returns a segment representing the given string of decimal digits encoded in numeric mode.\n\t */\n\tpublic: static QrSegment makeNumeric(const char *digits);\n\t\n\t\n\t/* \n\t * Returns a segment representing the given text string encoded in alphanumeric mode.\n\t * The characters allowed are: 0 to 9, A to Z (uppercase only), space,\n\t * dollar, percent, asterisk, plus, hyphen, period, slash, colon.\n\t */\n\tpublic: static QrSegment makeAlphanumeric(const char *text);\n\t\n\t\n\t/* \n\t * Returns a list of zero or more segments to represent the given text string. The result\n\t * may use various segment modes and switch modes to optimize the length of the bit stream.\n\t */\n\tpublic: static std::vector<QrSegment> makeSegments(const char *text);\n\t\n\t\n\t/* \n\t * Returns a segment representing an Extended Channel Interpretation\n\t * (ECI) designator with the given assignment value.\n\t */\n\tpublic: static QrSegment makeEci(long assignVal);\n\t\n\t\n\t/*---- Public static helper functions ----*/\n\t\n\t/* \n\t * Tests whether the given string can be encoded as a segment in alphanumeric mode.\n\t * A string is encodable iff each character is in the following set: 0 to 9, A to Z\n\t * (uppercase only), space, dollar, percent, asterisk, plus, hyphen, period, slash, colon.\n\t */\n\tpublic: static bool isAlphanumeric(const char *text);\n\t\n\t\n\t/* \n\t * Tests whether the given string can be encoded as a segment in numeric mode.\n\t * A string is encodable iff each character is in the range 0 to 9.\n\t */\n\tpublic: static bool isNumeric(const char *text);\n\t\n\t\n\t\n\t/*---- Instance fields ----*/\n\t\n\t/* The mode indicator of this segment. Accessed through getMode(). */\n\tprivate: Mode mode;\n\t\n\t/* The length of this segment's unencoded data. Measured in characters for\n\t * numeric/alphanumeric/kanji mode, bytes for byte mode, and 0 for ECI mode.\n\t * Always zero or positive. Not the same as the data's bit length.\n\t * Accessed through getNumChars(). */\n\tprivate: int numChars;\n\t\n\t/* The data bits of this segment. Accessed through getData(). */\n\tprivate: std::vector<bool> data;\n\t\n\t\n\t/*---- Constructors (low level) ----*/\n\t\n\t/* \n\t * Creates a new QR Code segment with the given attributes and data.\n\t * The character count (numCh) must agree with the mode and the bit buffer length,\n\t * but the constraint isn't checked. The given bit buffer is copied and stored.\n\t */\n\tpublic: QrSegment(Mode md, int numCh, const std::vector<bool> &dt);\n\t\n\t\n\t/* \n\t * Creates a new QR Code segment with the given parameters and data.\n\t * The character count (numCh) must agree with the mode and the bit buffer length,\n\t * but the constraint isn't checked. The given bit buffer is moved and stored.\n\t */\n\tpublic: QrSegment(Mode md, int numCh, std::vector<bool> &&dt);\n\t\n\t\n\t/*---- Methods ----*/\n\t\n\t/* \n\t * Returns the mode field of this segment.\n\t */\n\tpublic: Mode getMode() const;\n\t\n\t\n\t/* \n\t * Returns the character count field of this segment.\n\t */\n\tpublic: int getNumChars() const;\n\t\n\t\n\t/* \n\t * Returns the data bits of this segment.\n\t */\n\tpublic: const std::vector<bool> &getData() const;\n\t\n\t\n\t// (Package-private) Calculates the number of bits needed to encode the given segments at\n\t// the given version. Returns a non-negative number if successful. Otherwise returns -1 if a\n\t// segment has too many characters to fit its length field, or the total bits exceeds INT_MAX.\n\tpublic: static int getTotalBits(const std::vector<QrSegment> &segs, int version);\n\t\n\t\n\t/*---- Private constant ----*/\n\t\n\t/* The set of all legal characters in alphanumeric mode, where\n\t * each character value maps to the index in the string. */\n\tprivate: static const char *ALPHANUMERIC_CHARSET;\n\t\n};\n\n\n\n/* \n * A QR Code symbol, which is a type of two-dimension barcode.\n * Invented by Denso Wave and described in the ISO/IEC 18004 standard.\n * Instances of this class represent an immutable square grid of black and white cells.\n * The class provides static factory functions to create a QR Code from text or binary data.\n * The class covers the QR Code Model 2 specification, supporting all versions (sizes)\n * from 1 to 40, all 4 error correction levels, and 4 character encoding modes.\n * \n * Ways to create a QR Code object:\n * - High level: Take the payload data and call QrCode::encodeText() or QrCode::encodeBinary().\n * - Mid level: Custom-make the list of segments and call QrCode::encodeSegments().\n * - Low level: Custom-make the array of data codeword bytes (including\n *   segment headers and final padding, excluding error correction codewords),\n *   supply the appropriate version number, and call the QrCode() constructor.\n * (Note that all ways require supplying the desired error correction level.)\n */\nclass QrCode final {\n\t\n\t/*---- Public helper enumeration ----*/\n\t\n\t/* \n\t * The error correction level in a QR Code symbol.\n\t */\n\tpublic: enum class Ecc {\n\t\tLOW = 0 ,  // The QR Code can tolerate about  7% erroneous codewords\n\t\tMEDIUM  ,  // The QR Code can tolerate about 15% erroneous codewords\n\t\tQUARTILE,  // The QR Code can tolerate about 25% erroneous codewords\n\t\tHIGH    ,  // The QR Code can tolerate about 30% erroneous codewords\n\t};\n\t\n\t\n\t// Returns a value in the range 0 to 3 (unsigned 2-bit integer).\n\tprivate: static int getFormatBits(Ecc ecl);\n\t\n\t\n\t\n\t/*---- Static factory functions (high level) ----*/\n\t\n\t/* \n\t * Returns a QR Code representing the given Unicode text string at the given error correction level.\n\t * As a conservative upper bound, this function is guaranteed to succeed for strings that have 2953 or fewer\n\t * UTF-8 code units (not Unicode code points) if the low error correction level is used. The smallest possible\n\t * QR Code version is automatically chosen for the output. The ECC level of the result may be higher than\n\t * the ecl argument if it can be done without increasing the version.\n\t */\n\tpublic: static QrCode encodeText(const char *text, Ecc ecl);\n\t\n\t\n\t/* \n\t * Returns a QR Code representing the given binary data at the given error correction level.\n\t * This function always encodes using the binary segment mode, not any text mode. The maximum number of\n\t * bytes allowed is 2953. The smallest possible QR Code version is automatically chosen for the output.\n\t * The ECC level of the result may be higher than the ecl argument if it can be done without increasing the version.\n\t */\n\tpublic: static QrCode encodeBinary(const std::vector<std::uint8_t> &data, Ecc ecl);\n\t\n\t\n\t/*---- Static factory functions (mid level) ----*/\n\t\n\t/* \n\t * Returns a QR Code representing the given segments with the given encoding parameters.\n\t * The smallest possible QR Code version within the given range is automatically\n\t * chosen for the output. Iff boostEcl is true, then the ECC level of the result\n\t * may be higher than the ecl argument if it can be done without increasing the\n\t * version. The mask number is either between 0 to 7 (inclusive) to force that\n\t * mask, or -1 to automatically choose an appropriate mask (which may be slow).\n\t * This function allows the user to create a custom sequence of segments that switches\n\t * between modes (such as alphanumeric and byte) to encode text in less space.\n\t * This is a mid-level API; the high-level API is encodeText() and encodeBinary().\n\t */\n\tpublic: static QrCode encodeSegments(const std::vector<QrSegment> &segs, Ecc ecl,\n\t\tint minVersion=1, int maxVersion=40, int mask=-1, bool boostEcl=true);  // All optional parameters\n\t\n\t\n\t\n\t/*---- Instance fields ----*/\n\t\n\t// Immutable scalar parameters:\n\t\n\t/* The version number of this QR Code, which is between 1 and 40 (inclusive).\n\t * This determines the size of this barcode. */\n\tprivate: int version;\n\t\n\t/* The width and height of this QR Code, measured in modules, between\n\t * 21 and 177 (inclusive). This is equal to version * 4 + 17. */\n\tprivate: int size;\n\t\n\t/* The error correction level used in this QR Code. */\n\tprivate: Ecc errorCorrectionLevel;\n\t\n\t/* The index of the mask pattern used in this QR Code, which is between 0 and 7 (inclusive).\n\t * Even if a QR Code is created with automatic masking requested (mask = -1),\n\t * the resulting object still has a mask value between 0 and 7. */\n\tprivate: int mask;\n\t\n\t// Private grids of modules/pixels, with dimensions of size*size:\n\t\n\t// The modules of this QR Code (false = white, true = black).\n\t// Immutable after constructor finishes. Accessed through getModule().\n\tprivate: std::vector<std::vector<bool> > modules;\n\t\n\t// Indicates function modules that are not subjected to masking. Discarded when constructor finishes.\n\tprivate: std::vector<std::vector<bool> > isFunction;\n\t\n\t\n\t\n\t/*---- Constructor (low level) ----*/\n\t\n\t/* \n\t * Creates a new QR Code with the given version number,\n\t * error correction level, data codeword bytes, and mask number.\n\t * This is a low-level API that most users should not use directly.\n\t * A mid-level API is the encodeSegments() function.\n\t */\n\tpublic: QrCode(int ver, Ecc ecl, const std::vector<std::uint8_t> &dataCodewords, int msk);\n\t\n\t\n\t\n\t/*---- Public instance methods ----*/\n\t\n\t/* \n\t * Returns this QR Code's version, in the range [1, 40].\n\t */\n\tpublic: int getVersion() const;\n\t\n\t\n\t/* \n\t * Returns this QR Code's size, in the range [21, 177].\n\t */\n\tpublic: int getSize() const;\n\t\n\t\n\t/* \n\t * Returns this QR Code's error correction level.\n\t */\n\tpublic: Ecc getErrorCorrectionLevel() const;\n\t\n\t\n\t/* \n\t * Returns this QR Code's mask, in the range [0, 7].\n\t */\n\tpublic: int getMask() const;\n\t\n\t\n\t/* \n\t * Returns the color of the module (pixel) at the given coordinates, which is false\n\t * for white or true for black. The top left corner has the coordinates (x=0, y=0).\n\t * If the given coordinates are out of bounds, then false (white) is returned.\n\t */\n\tpublic: bool getModule(int x, int y) const;\n\t\n\t\n\t/* \n\t * Returns a string of SVG code for an image depicting this QR Code, with the given number\n\t * of border modules. The string always uses Unix newlines (\\n), regardless of the platform.\n\t */\n\tpublic: std::string toSvgString(int border) const;\n\t\n\t\n\t\n\t/*---- Private helper methods for constructor: Drawing function modules ----*/\n\t\n\t// Reads this object's version field, and draws and marks all function modules.\n\tprivate: void drawFunctionPatterns();\n\t\n\t\n\t// Draws two copies of the format bits (with its own error correction code)\n\t// based on the given mask and this object's error correction level field.\n\tprivate: void drawFormatBits(int msk);\n\t\n\t\n\t// Draws two copies of the version bits (with its own error correction code),\n\t// based on this object's version field, iff 7 <= version <= 40.\n\tprivate: void drawVersion();\n\t\n\t\n\t// Draws a 9*9 finder pattern including the border separator,\n\t// with the center module at (x, y). Modules can be out of bounds.\n\tprivate: void drawFinderPattern(int x, int y);\n\t\n\t\n\t// Draws a 5*5 alignment pattern, with the center module\n\t// at (x, y). All modules must be in bounds.\n\tprivate: void drawAlignmentPattern(int x, int y);\n\t\n\t\n\t// Sets the color of a module and marks it as a function module.\n\t// Only used by the constructor. Coordinates must be in bounds.\n\tprivate: void setFunctionModule(int x, int y, bool isBlack);\n\t\n\t\n\t// Returns the color of the module at the given coordinates, which must be in range.\n\tprivate: bool module(int x, int y) const;\n\t\n\t\n\t/*---- Private helper methods for constructor: Codewords and masking ----*/\n\t\n\t// Returns a new byte string representing the given data with the appropriate error correction\n\t// codewords appended to it, based on this object's version and error correction level.\n\tprivate: std::vector<std::uint8_t> addEccAndInterleave(const std::vector<std::uint8_t> &data) const;\n\t\n\t\n\t// Draws the given sequence of 8-bit codewords (data and error correction) onto the entire\n\t// data area of this QR Code. Function modules need to be marked off before this is called.\n\tprivate: void drawCodewords(const std::vector<std::uint8_t> &data);\n\t\n\t\n\t// XORs the codeword modules in this QR Code with the given mask pattern.\n\t// The function modules must be marked and the codeword bits must be drawn\n\t// before masking. Due to the arithmetic of XOR, calling applyMask() with\n\t// the same mask value a second time will undo the mask. A final well-formed\n\t// QR Code needs exactly one (not zero, two, etc.) mask applied.\n\tprivate: void applyMask(int msk);\n\t\n\t\n\t// Calculates and returns the penalty score based on state of this QR Code's current modules.\n\t// This is used by the automatic mask choice algorithm to find the mask pattern that yields the lowest score.\n\tprivate: long getPenaltyScore() const;\n\t\n\t\n\t\n\t/*---- Private helper functions ----*/\n\t\n\t// Returns an ascending list of positions of alignment patterns for this version number.\n\t// Each position is in the range [0,177), and are used on both the x and y axes.\n\t// This could be implemented as lookup table of 40 variable-length lists of unsigned bytes.\n\tprivate: std::vector<int> getAlignmentPatternPositions() const;\n\t\n\t\n\t// Returns the number of data bits that can be stored in a QR Code of the given version number, after\n\t// all function modules are excluded. This includes remainder bits, so it might not be a multiple of 8.\n\t// The result is in the range [208, 29648]. This could be implemented as a 40-entry lookup table.\n\tprivate: static int getNumRawDataModules(int ver);\n\t\n\t\n\t// Returns the number of 8-bit data (i.e. not error correction) codewords contained in any\n\t// QR Code of the given version number and error correction level, with remainder bits discarded.\n\t// This stateless pure function could be implemented as a (40*4)-cell lookup table.\n\tprivate: static int getNumDataCodewords(int ver, Ecc ecl);\n\t\n\t\n\t// Returns a Reed-Solomon ECC generator polynomial for the given degree. This could be\n\t// implemented as a lookup table over all possible parameter values, instead of as an algorithm.\n\tprivate: static std::vector<std::uint8_t> reedSolomonComputeDivisor(int degree);\n\t\n\t\n\t// Returns the Reed-Solomon error correction codeword for the given data and divisor polynomials.\n\tprivate: static std::vector<std::uint8_t> reedSolomonComputeRemainder(const std::vector<std::uint8_t> &data, const std::vector<std::uint8_t> &divisor);\n\t\n\t\n\t// Returns the product of the two given field elements modulo GF(2^8/0x11D).\n\t// All inputs are valid. This could be implemented as a 256*256 lookup table.\n\tprivate: static std::uint8_t reedSolomonMultiply(std::uint8_t x, std::uint8_t y);\n\t\n\t\n\t// Can only be called immediately after a white run is added, and\n\t// returns either 0, 1, or 2. A helper function for getPenaltyScore().\n\tprivate: int finderPenaltyCountPatterns(const std::array<int,7> &runHistory) const;\n\t\n\t\n\t// Must be called at the end of a line (row or column) of modules. A helper function for getPenaltyScore().\n\tprivate: int finderPenaltyTerminateAndCount(bool currentRunColor, int currentRunLength, std::array<int,7> &runHistory) const;\n\t\n\t\n\t// Pushes the given value to the front and drops the last value. A helper function for getPenaltyScore().\n\tprivate: void finderPenaltyAddHistory(int currentRunLength, std::array<int,7> &runHistory) const;\n\t\n\t\n\t// Returns true iff the i'th bit of x is set to 1.\n\tprivate: static bool getBit(long x, int i);\n\t\n\t\n\t/*---- Constants and tables ----*/\n\t\n\t// The minimum version number supported in the QR Code Model 2 standard.\n\tpublic: static constexpr int MIN_VERSION =  1;\n\t\n\t// The maximum version number supported in the QR Code Model 2 standard.\n\tpublic: static constexpr int MAX_VERSION = 40;\n\t\n\t\n\t// For use in getPenaltyScore(), when evaluating which mask is best.\n\tprivate: static const int PENALTY_N1;\n\tprivate: static const int PENALTY_N2;\n\tprivate: static const int PENALTY_N3;\n\tprivate: static const int PENALTY_N4;\n\t\n\t\n\tprivate: static const std::int8_t ECC_CODEWORDS_PER_BLOCK[4][41];\n\tprivate: static const std::int8_t NUM_ERROR_CORRECTION_BLOCKS[4][41];\n\t\n};\n\n\n\n/*---- Public exception class ----*/\n\n/* \n * Thrown when the supplied data does not fit any QR Code version. Ways to handle this exception include:\n * - Decrease the error correction level if it was greater than Ecc::LOW.\n * - If the encodeSegments() function was called with a maxVersion argument, then increase\n *   it if it was less than QrCode::MAX_VERSION. (This advice does not apply to the other\n *   factory functions because they search all versions up to QrCode::MAX_VERSION.)\n * - Split the text data into better or optimal segments in order to reduce the number of bits required.\n * - Change the text or binary data to be shorter.\n * - Change the text to fit the character set of a particular segment mode (e.g. alphanumeric).\n * - Propagate the error upward to the caller/user.\n */\nclass data_too_long : public std::length_error {\n\t\n\tpublic: explicit data_too_long(const std::string &msg);\n\t\n};\n\n\n\n/* \n * An appendable sequence of bits (0s and 1s). Mainly used by QrSegment.\n */\nclass BitBuffer final : public std::vector<bool> {\n\t\n\t/*---- Constructor ----*/\n\t\n\t// Creates an empty bit buffer (length 0).\n\tpublic: BitBuffer();\n\t\n\t\n\t\n\t/*---- Method ----*/\n\t\n\t// Appends the given number of low-order bits of the given value\n\t// to this buffer. Requires 0 <= len <= 31 and val < 2^len.\n\tpublic: void appendBits(std::uint32_t val, int len);\n\t\n};\n\n}\n"
  },
  {
    "path": "phonelibs/snpe/include/DiagLog/IDiagLog.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015, 2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#ifndef __IDIAGLOG_HPP_\n#define __IDIAGLOG_HPP_\n\n#include <string>\n\n#include \"DiagLog/Options.hpp\"\n#include \"DlSystem/String.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl\n{\nnamespace DiagLog\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/// @brief .\n///\n/// Interface for controlling logging for zdl components.\n\nclass ZDL_EXPORT IDiagLog\n{\npublic:\n\n   /// @brief .\n   ///\n   /// Sets the options after initialization occurs.\n   ///\n   /// @param[in] loggingOptions The options to set up diagnostic logging.\n   ///\n   /// @return False if the options could not be set. Ensure logging is not started.\n   virtual bool setOptions(const Options& loggingOptions) = 0;\n\n   /// @brief .\n   ///\n   /// Gets the curent options for the diag logger.\n   ///\n   /// @return Diag log options object.\n   virtual Options getOptions() = 0;\n\n   /// @brief .\n   ///\n   /// Allows for setting the log mask once diag logging has started\n   ///\n   /// @return True if the level was set successfully, false if a failure occurred.\n   virtual bool setDiagLogMask(const std::string& mask) = 0;\n\n   /// @brief .\n   ///\n   /// Allows for setting the log mask once diag logging has started\n   ///\n   /// @return True if the level was set successfully, false if a failure occurred.\n   virtual bool setDiagLogMask(const zdl::DlSystem::String& mask) = 0;\n\n   /// @brief .\n   ///\n   /// Enables logging for zdl components.\n   ///\n   /// Logging should be started prior to the instantiation of zdl components\n   /// to ensure all events are captured.\n   ///\n   /// @return False if diagnostic logging could not be started.\n   virtual bool start(void) = 0;\n\n   /// @brief Disables logging for zdl components.\n   virtual bool stop(void) = 0;\n\n   virtual ~IDiagLog() {};\n};\n\n} // DiagLog namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DiagLog/Options.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015, 2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#ifndef __DIAGLOG_OPTIONS_HPP_\n#define __DIAGLOG_OPTIONS_HPP_\n\n#include <string>\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl\n{\nnamespace DiagLog\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/// @brief .\n///\n/// Options for setting up diagnostic logging for zdl components.\nclass ZDL_EXPORT Options\n{\npublic:\n   Options() :\n      DiagLogMask(\"\"),\n      LogFileDirectory(\"diaglogs\"),\n      LogFileName(\"DiagLog\"),\n      LogFileRotateCount(20),\n      LogFileReplace(true)\n   {\n      // Solves the empty string problem with multiple std libs\n      DiagLogMask.reserve(1);\n   }\n\n   /// @brief .\n   ///\n   /// Enables diag logging only on the specified area mask (DNN_RUNTIME=ON | OFF)\n   std::string DiagLogMask;\n\n   /// @brief .\n   ///\n   /// The path to the directory where log files will be written.\n   /// The path may be relative or absolute. Relative paths are interpreted\n   /// from the current working directory.\n   /// Default value is \"diaglogs\"\n   std::string LogFileDirectory;\n\n   /// @brief .\n   ///\n   //// The name used for log files. If this value is empty then BaseName will be\n   /// used as the default file name.\n   /// Default value is \"DiagLog\"\n   std::string LogFileName;\n\n   /// @brief .\n   ///\n   /// The maximum number of log files to create. If set to 0 no log rotation\n   /// will be used and the log file name specified will be used each time, overwriting\n   /// any existing log file that may exist.\n   /// Default value is 20\n   uint32_t LogFileRotateCount;\n\n   /// @brief\n   ///\n   /// If the log file already exists, control whether it will be replaced\n   /// (existing contents truncated), or appended.\n   /// Default value is true\n   bool LogFileReplace;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n} // DiagLog namespace\n} // zdl namespace\n\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlContainer/IDlContainer.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef ZEROTH_IDNC_CONTAINER_HPP\n#define ZEROTH_IDNC_CONTAINER_HPP\n\n#include <memory>\n#include <stdint.h>\n#include <string>\n#include <vector>\n#include <set>\n\n#include \"DlSystem/ZdlExportDefine.hpp\"\n#include \"DlSystem/String.hpp\"\n\nnamespace zdl {\nnamespace DlContainer {\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\nclass IDlContainer;\nclass dlc_error;\n\n/**\n * The structure of a record in a DL container.\n */\nstruct ZDL_EXPORT DlcRecord\n{\n   /// Name of the record.\n   std::string name;\n   /// Byte blob holding the data for the record.\n   std::vector<uint8_t> data;\n\n   DlcRecord();\n   DlcRecord( DlcRecord&& other )\n      : name(std::move(other.name))\n      , data(std::move(other.data))\n   {}\n   DlcRecord(const std::string& new_name)\n      : name(new_name)\n      , data()\n   {\n      if(name.empty())\n      {\n         name.reserve(1);\n      }\n   }\n   DlcRecord(const DlcRecord&) = delete;\n};\n\n// The maximum length of any record name.\nextern const uint32_t RECORD_NAME_MAX_SIZE;\n// The maximum size of the record payload (bytes).\nextern const uint32_t RECORD_DATA_MAX_SIZE;\n// The maximum number of records in an archive at one time.\nextern const uint32_t ARCHIVE_MAX_RECORDS;\n\n/**\n * Represents a container for a neural network model which can\n * be used to load the model into the SNPE runtime.\n */\nclass ZDL_EXPORT IDlContainer\n{\npublic:\n   /**\n    * Initializes a container from a container archive file.\n    *\n    * @param[in] filename Container archive file path.\n    *\n    * @return A pointer to the initialized container\n    */\n   static std::unique_ptr<IDlContainer>\n   open(const std::string &filename) noexcept;\n\n   /**\n    * Initializes a container from a container archive file.\n    *\n    * @param[in] filename Container archive file path.\n    *\n    * @return A pointer to the initialized container\n    */\n   static std::unique_ptr<IDlContainer>\n   open(const zdl::DlSystem::String &filename) noexcept;\n\n   /**\n    * Initializes a container from a byte buffer.\n    *\n    * @param[in] buffer Byte buffer holding the contents of an archive\n    *                   file.\n    *\n    * @return A pointer to the initialized container\n    */\n   static std::unique_ptr<IDlContainer>\n   open(const std::vector<uint8_t> &buffer) noexcept;\n\n   /**\n    * Initializes a container from a byte buffer.\n    *\n    * @param[in] buffer Byte buffer holding the contents of an archive\n    *                   file.\n    *\n    * @param[in] size Size of the byte buffer.\n    *\n    * @return A pointer to the initialized container\n    */\n   static std::unique_ptr<IDlContainer>\n   open(const uint8_t* buffer, const size_t size) noexcept;\n\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n   /**\n    * Get the record catalog for a container.\n    *\n    * @param[out] catalog Buffer that will hold the record names on\n    *                    return.\n    */\n   virtual void getCatalog(std::set<std::string> &catalog) const = 0;\n\n    /**\n     * Get the record catalog for a container.\n     *\n     * @param[out] catalog Buffer that will hold the record names on\n     *                    return.\n     */\n   virtual void getCatalog(std::set<zdl::DlSystem::String> &catalog) const = 0;\n\n   /**\n    * Get a record from a container by name.\n    *\n    * @param[in] name Name of the record to fetch.\n    * @param[out] record The passed in record will be populated with the\n    *                   record data on return. Note that the caller\n    *                   will own the data in the record and is\n    *                   responsible for freeing it if needed.\n    */\n   virtual void getRecord(const std::string &name, DlcRecord &record) const = 0;\n\n   /**\n    * Get a record from a container by name.\n    *\n    * @param[in] name Name of the record to fetch.\n    * @param[out] record The passed in record will be populated with the\n    *                   record data on return. Note that the caller\n    *                   will own the data in the record and is\n    *                   responsible for freeing it if needed.\n    */\n   virtual void getRecord(const zdl::DlSystem::String &name, DlcRecord &record) const = 0;\n\n   /**\n    * Save the container to an archive on disk. This function will save the\n    * container if the filename is different from the file that it was opened\n    * from, or if at least one record was modified since the container was\n    * opened.\n    *\n    * It will truncate any existing file at the target path.\n    *\n    * @param filename Container archive file path.\n    *\n    * @return indication of success/failure\n    */\n   virtual bool save(const std::string &filename) = 0;\n\n   /**\n    * Save the container to an archive on disk. This function will save the\n    * container if the filename is different from the file that it was opened\n    * from, or if at least one record was modified since the container was\n    * opened.\n    *\n    * It will truncate any existing file at the target path.\n    *\n    * @param filename Container archive file path.\n    *\n    * @return indication of success/failure\n    */\n   virtual bool save (const zdl::DlSystem::String &filename) = 0;\n\n   virtual ~IDlContainer() {}\n};\n\n} // ns DlContainer\n} // ns zdl\n\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/DlEnums.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2014-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _DL_ENUMS_HPP_\n#define _DL_ENUMS_HPP_\n\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\n\nnamespace zdl {\nnamespace DlSystem\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * Enumeration of supported target runtimes.\n */\nenum class Runtime_t\n{\n   /// Run the processing on Snapdragon CPU.\n   /// Data: float 32bit\n   /// Math: float 32bit\n   CPU_FLOAT32  = 0,\n\n   /// Run the processing on the Adreno GPU.\n   /// Data: float 16bit\n   /// Math: float 32bit\n   GPU_FLOAT32_16_HYBRID = 1,\n\n   /// Run the processing on the Hexagon DSP.\n   /// Data: 8bit fixed point Tensorflow style format\n   /// Math: 8bit fixed point Tensorflow style format\n   DSP_FIXED8_TF = 2,\n\n   /// Run the processing on the Adreno GPU.\n   /// Data: float 16bit\n   /// Math: float 16bit\n   GPU_FLOAT16 = 3,\n\n   /// Run the processing on Snapdragon AIX+HVX.\n   /// Data: 8bit fixed point Tensorflow style format\n   /// Math: 8bit fixed point Tensorflow style format\n   AIP_FIXED8_TF = 5,\n   AIP_FIXED_TF = AIP_FIXED8_TF,\n\n   /// Default legacy enum to retain backward compatibility.\n   /// CPU = CPU_FLOAT32\n   CPU = CPU_FLOAT32,\n\n   /// Default legacy enum to retain backward compatibility.\n   /// GPU = GPU_FLOAT32_16_HYBRID\n   GPU = GPU_FLOAT32_16_HYBRID,\n\n   /// Default legacy enum to retain backward compatibility.\n   /// DSP = DSP_FIXED8_TF\n   DSP = DSP_FIXED8_TF,\n\n   /// Special value indicating the property is unset.\n   UNSET = -1\n};\n\n/**\n * Enumeration of runtime available check options.\n */\nenum class RuntimeCheckOption_t\n{\n   /// Perform standard runtime available check\n   DEFAULT = 0,\n   /// Perform standard runtime available check\n   NORMAL_CHECK = 0,\n   /// Perform basic runtime available check, may be runtime specific\n   BASIC_CHECK = 1,\n};\n\n/**\n * Enumeration of various performance profiles that can be requested.\n */\nenum class PerformanceProfile_t\n{\n    /// Run in a standard mode.\n    /// This mode will be deprecated in the future and replaced with BALANCED.\n    DEFAULT = 0,\n    /// Run in a balanced mode.\n    BALANCED = 0,\n\n    /// Run in high performance mode\n    HIGH_PERFORMANCE = 1,\n\n    /// Run in a power sensitive mode, at the expense of performance.\n    POWER_SAVER = 2,\n\n    /// Use system settings.  SNPE makes no calls to any performance related APIs.\n    SYSTEM_SETTINGS = 3,\n\n    /// Run in sustained high performance mode\n    SUSTAINED_HIGH_PERFORMANCE = 4,\n\n    /// Run in burst mode\n    BURST = 5,\n\n    /// Run in lower clock than POWER_SAVER, at the expense of performance.\n    LOW_POWER_SAVER = 6,\n\n    /// Run in higher clock and provides better performance than POWER_SAVER.\n    HIGH_POWER_SAVER = 7,\n\n    /// Run in lower balanced mode\n    LOW_BALANCED = 8,\n};\n\n/**\n * Enumeration of various profilngLevels that can be requested.\n */\nenum class ProfilingLevel_t\n{\n    /// No profiling.\n    /// Collects no runtime stats in the DiagLog\n    OFF = 0,\n\n    /// Basic profiling\n    /// Collects some runtime stats in the DiagLog\n    BASIC = 1,\n\n    /// Detailed profiling\n    /// Collects more runtime stats in the DiagLog, including per-layer statistics\n    /// Performance may be impacted\n    DETAILED = 2,\n\n    /// Moderate profiling\n    /// Collects more runtime stats in the DiagLog, no per-layer statistics\n    MODERATE = 3\n};\n\n/**\n * Enumeration of various execution priority hints.\n */\nenum class ExecutionPriorityHint_t\n{\n    /// Normal priority\n    NORMAL = 0,\n\n    /// Higher than normal priority\n    HIGH = 1,\n\n    /// Lower priority\n    LOW = 2\n\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++*/\n\n/**\n * Enumeration that lists the supported image encoding formats.\n */\nenum class ImageEncoding_t\n{\n   /// For unknown image type. Also used as a default value for ImageEncoding_t.\n   UNKNOWN = 0,\n\n   /// The RGB format consists of 3 bytes per pixel: one byte for\n   /// Red, one for Green, and one for Blue. The byte ordering is\n   /// endian independent and is always in RGB byte order.\n   RGB = 1,\n\n   /// The ARGB32 format consists of 4 bytes per pixel: one byte for\n   /// Red, one for Green, one for Blue, and one for the alpha channel.\n   /// The alpha channel is ignored. The byte ordering depends on the\n   /// underlying CPU. For little endian CPUs, the byte order is BGRA.\n   /// For big endian CPUs, the byte order is ARGB.\n   ARGB32 = 2,\n\n   /// The RGBA format consists of 4 bytes per pixel: one byte for\n   /// Red, one for Green, one for Blue, and one for the alpha channel.\n   /// The alpha channel is ignored. The byte ordering is endian independent\n   /// and is always in RGBA byte order.\n   RGBA = 3,\n\n   /// The GRAYSCALE format is for 8-bit grayscale.\n   GRAYSCALE = 4,\n\n   /// NV21 is the Android version of YUV. The Chrominance is down\n   /// sampled and has a subsampling ratio of 4:2:0. Note that this\n   /// image format has 3 channels, but the U and V channels\n   /// are subsampled. For every four Y pixels there is one U and one V pixel. @newpage\n   NV21 = 5,\n\n   /// The BGR format consists of 3 bytes per pixel: one byte for\n   /// Red, one for Green and one for Blue. The byte ordering is\n   /// endian independent and is always BGR byte order.\n   BGR = 6\n};\n\n}} // namespaces end\n\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/DlError.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2016-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _DL_ERROR_HPP_\n#define _DL_ERROR_HPP_\n\n#include <stdint.h>\n#include <limits> // numeric_limits\n\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl {\nnamespace DlSystem {\n\n// clang and arm gcc different in how ZDL_EXPORT is used with enum class\n#if !defined (__clang__)\nenum class ErrorCode : uint32_t ZDL_EXPORT {\n#else\nenum class ZDL_EXPORT ErrorCode : uint32_t {\n#endif // ARM64V8A\n   NONE = 0,\n\n   // System config errors\n   SNPE_CONFIG_MISSING_PARAM                             = 100,\n   SNPE_CONFIG_INVALID_PARAM                             = 101,\n   SNPE_CONFIG_MISSING_FILE                              = 102,\n   SNPE_CONFIG_NNCONFIG_NOT_SET                          = 103,\n   SNPE_CONFIG_NNCONFIG_INVALID                          = 104,\n   SNPE_CONFIG_WRONG_INPUT_NAME                          = 105,\n   SNPE_CONFIG_INCORRECT_INPUT_DIMENSIONS                = 106,\n   SNPE_CONFIG_DIMENSIONS_MODIFICATION_NOT_SUPPORTED     = 107,\n   SNPE_CONFIG_BOTH_OUTPUT_LAYER_TENSOR_NAMES_SET        = 108,\n\n   SNPE_CONFIG_NNCONFIG_ONLY_TENSOR_SUPPORTED            = 120,\n   SNPE_CONFIG_NNCONFIG_ONLY_USER_BUFFER_SUPPORTED       = 121,\n\n   // DlSystem errors\n   SNPE_DLSYSTEM_MISSING_BUFFER                          = 200,\n   SNPE_DLSYSTEM_TENSOR_CAST_FAILED                      = 201,\n   SNPE_DLSYSTEM_FIXED_POINT_PARAM_INVALID               = 202,\n   SNPE_DLSYSTEM_SIZE_MISMATCH                           = 203,\n   SNPE_DLSYSTEM_NAME_NOT_FOUND                          = 204,\n   SNPE_DLSYSTEM_VALUE_MISMATCH                          = 205,\n   SNPE_DLSYSTEM_INSERT_FAILED                           = 206,\n   SNPE_DLSYSTEM_TENSOR_FILE_READ_FAILED                 = 207,\n   SNPE_DLSYSTEM_DIAGLOG_FAILURE                         = 208,\n   SNPE_DLSYSTEM_LAYER_NOT_SET                           = 209,\n   SNPE_DLSYSTEM_WRONG_NUMBER_INPUT_BUFFERS              = 210,\n   SNPE_DLSYSTEM_RUNTIME_TENSOR_SHAPE_MISMATCH           = 211,\n   SNPE_DLSYSTEM_TENSOR_MISSING                          = 212,\n   SNPE_DLSYSTEM_TENSOR_ITERATION_UNSUPPORTED            = 213,\n   SNPE_DLSYSTEM_BUFFER_MANAGER_MISSING                  = 214,\n   SNPE_DLSYSTEM_RUNTIME_BUFFER_SOURCE_UNSUPPORTED       = 215,\n   SNPE_DLSYSTEM_BUFFER_CAST_FAILED                      = 216,\n   SNPE_DLSYSTEM_WRONG_TRANSITION_TYPE                   = 217,\n   SNPE_DLSYSTEM_LAYER_ALREADY_REGISTERED                = 218,\n\n   SNPE_DLSYSTEM_BUFFERENCODING_UNKNOWN                  = 240,\n   SNPE_DLSYSTEM_BUFFER_INVALID_PARAM                    = 241,\n\n   // DlContainer errors\n   SNPE_DLCONTAINER_MODEL_PARSING_FAILED                 = 300,\n   SNPE_DLCONTAINER_UNKNOWN_LAYER_CODE                   = 301,\n   SNPE_DLCONTAINER_MISSING_LAYER_PARAM                  = 302,\n   SNPE_DLCONTAINER_LAYER_PARAM_NOT_SUPPORTED            = 303,\n   SNPE_DLCONTAINER_LAYER_PARAM_INVALID                  = 304,\n   SNPE_DLCONTAINER_TENSOR_DATA_MISSING                  = 305,\n   SNPE_DLCONTAINER_MODEL_LOAD_FAILED                    = 306,\n   SNPE_DLCONTAINER_MISSING_RECORDS                      = 307,\n   SNPE_DLCONTAINER_INVALID_RECORD                       = 308,\n   SNPE_DLCONTAINER_WRITE_FAILURE                        = 309,\n   SNPE_DLCONTAINER_READ_FAILURE                         = 310,\n   SNPE_DLCONTAINER_BAD_CONTAINER                        = 311,\n   SNPE_DLCONTAINER_BAD_DNN_FORMAT_VERSION               = 312,\n   SNPE_DLCONTAINER_UNKNOWN_AXIS_ANNOTATION              = 313,\n   SNPE_DLCONTAINER_UNKNOWN_SHUFFLE_TYPE                 = 314,\n   SNPE_DLCONTAINER_TEMP_FILE_FAILURE                    = 315,\n\n   // Network errors\n   SNPE_NETWORK_EMPTY_NETWORK                            = 400,\n   SNPE_NETWORK_CREATION_FAILED                          = 401,\n   SNPE_NETWORK_PARTITION_FAILED                         = 402,\n   SNPE_NETWORK_NO_OUTPUT_DEFINED                        = 403,\n   SNPE_NETWORK_MISMATCH_BETWEEN_NAMES_AND_DIMS          = 404,\n   SNPE_NETWORK_MISSING_INPUT_NAMES                      = 405,\n   SNPE_NETWORK_MISSING_OUTPUT_NAMES                     = 406,\n\n   // Host runtime errors\n   SNPE_HOST_RUNTIME_TARGET_UNAVAILABLE                  = 500,\n\n   // CPU runtime errors\n   SNPE_CPU_LAYER_NOT_SUPPORTED                          = 600,\n   SNPE_CPU_LAYER_PARAM_NOT_SUPPORTED                    = 601,\n   SNPE_CPU_LAYER_PARAM_INVALID                          = 602,\n   SNPE_CPU_LAYER_PARAM_COMBINATION_INVALID              = 603,\n   SNPE_CPU_BUFFER_NOT_FOUND                             = 604,\n   SNPE_CPU_NETWORK_NOT_SUPPORTED                        = 605,\n   SNPE_CPU_UDO_OPERATION_FAILED                         = 606,\n\n   // CPU fixed-point runtime errors\n   SNPE_CPU_FXP_LAYER_NOT_SUPPORTED                      = 700,\n   SNPE_CPU_FXP_LAYER_PARAM_NOT_SUPPORTED                = 701,\n   SNPE_CPU_FXP_LAYER_PARAM_INVALID                      = 702,\n\n   // GPU runtime errors\n   SNPE_GPU_LAYER_NOT_SUPPORTED                          = 800,\n   SNPE_GPU_LAYER_PARAM_NOT_SUPPORTED                    = 801,\n   SNPE_GPU_LAYER_PARAM_INVALID                          = 802,\n   SNPE_GPU_LAYER_PARAM_COMBINATION_INVALID              = 803,\n   SNPE_GPU_KERNEL_COMPILATION_FAILED                    = 804,\n   SNPE_GPU_CONTEXT_NOT_SET                              = 805,\n   SNPE_GPU_KERNEL_NOT_SET                               = 806,\n   SNPE_GPU_KERNEL_PARAM_INVALID                         = 807,\n   SNPE_GPU_OPENCL_CHECK_FAILED                          = 808,\n   SNPE_GPU_OPENCL_FUNCTION_ERROR                        = 809,\n   SNPE_GPU_BUFFER_NOT_FOUND                             = 810,\n   SNPE_GPU_TENSOR_DIM_INVALID                           = 811,\n   SNPE_GPU_MEMORY_FLAGS_INVALID                         = 812,\n   SNPE_GPU_UNEXPECTED_NUMBER_OF_IO                      = 813,\n   SNPE_GPU_LAYER_PROXY_ERROR                            = 814,\n   SNPE_GPU_BUFFER_IN_USE                                = 815,\n   SNPE_GPU_BUFFER_MODIFICATION_ERROR                    = 816,\n   SNPE_GPU_DATA_ARRANGEMENT_INVALID                     = 817,\n   SNPE_GPU_UDO_OPERATION_FAILED                         = 818,\n   // DSP runtime errors\n   SNPE_DSP_LAYER_NOT_SUPPORTED                          = 900,\n   SNPE_DSP_LAYER_PARAM_NOT_SUPPORTED                    = 901,\n   SNPE_DSP_LAYER_PARAM_INVALID                          = 902,\n   SNPE_DSP_LAYER_PARAM_COMBINATION_INVALID              = 903,\n   SNPE_DSP_STUB_NOT_PRESENT                             = 904,\n   SNPE_DSP_LAYER_NAME_TRUNCATED                         = 905,\n   SNPE_DSP_LAYER_INPUT_BUFFER_NAME_TRUNCATED            = 906,\n   SNPE_DSP_LAYER_OUTPUT_BUFFER_NAME_TRUNCATED           = 907,\n   SNPE_DSP_RUNTIME_COMMUNICATION_ERROR                  = 908,\n   SNPE_DSP_RUNTIME_INVALID_PARAM_ERROR                  = 909,\n   SNPE_DSP_RUNTIME_SYSTEM_ERROR                         = 910,\n   SNPE_DSP_RUNTIME_CRASHED_ERROR                        = 911,\n\n   // Model validataion errors\n   SNPE_MODEL_VALIDATION_LAYER_NOT_SUPPORTED             = 1000,\n   SNPE_MODEL_VALIDATION_LAYER_PARAM_NOT_SUPPORTED       = 1001,\n   SNPE_MODEL_VALIDATION_LAYER_PARAM_INVALID             = 1002,\n   SNPE_MODEL_VALIDATION_LAYER_PARAM_MISSING             = 1003,\n   SNPE_MODEL_VALIDATION_LAYER_PARAM_COMBINATION_INVALID = 1004,\n   SNPE_MODEL_VALIDATION_LAYER_ORDERING_INVALID          = 1005,\n   SNPE_MODEL_VALIDATION_INVALID_CONSTRAINT              = 1006,\n   SNPE_MODEL_VALIDATION_MISSING_BUFFER                  = 1007,\n   SNPE_MODEL_VALIDATION_BUFFER_REUSE_NOT_SUPPORTED      = 1008,\n   SNPE_MODEL_VALIDATION_LAYER_COULD_NOT_BE_ASSIGNED     = 1009,\n   SNPE_MODEL_VALIDATION_UDO_LAYER_FAILED                = 1010,\n\n   // UDL errors\n   SNPE_UDL_LAYER_EMPTY_UDL_NETWORK                      = 1100,\n   SNPE_UDL_LAYER_PARAM_INVALID                          = 1101,\n   SNPE_UDL_LAYER_INSTANCE_MISSING                       = 1102,\n   SNPE_UDL_LAYER_SETUP_FAILED                           = 1103,\n   SNPE_UDL_EXECUTE_FAILED                               = 1104,\n   SNPE_UDL_BUNDLE_INVALID                               = 1105,\n   SNPE_UDO_REGISTRATION_FAILED                          = 1106,\n   SNPE_UDO_GET_PACKAGE_FAILED                           = 1107,\n   SNPE_UDO_GET_IMPLEMENTATION_FAILED                    = 1108,\n\n   // Dependent library errors\n   SNPE_STD_LIBRARY_ERROR                                = 1200,\n\n   // Unknown exception (catch (...)), Has no component attached to this\n   SNPE_UNKNOWN_EXCEPTION                                = 1210,\n\n   // Storage Errors\n   SNPE_STORAGE_INVALID_KERNEL_REPO                      = 1300,\n\n   // AIP runtime errors\n   SNPE_AIP_LAYER_NOT_SUPPORTED                          = 1400,\n   SNPE_AIP_LAYER_PARAM_NOT_SUPPORTED                    = 1401,\n   SNPE_AIP_LAYER_PARAM_INVALID                          = 1402,\n   SNPE_AIP_LAYER_PARAM_COMBINATION_INVALID              = 1403,\n   SNPE_AIP_STUB_NOT_PRESENT                             = 1404,\n   SNPE_AIP_LAYER_NAME_TRUNCATED                         = 1405,\n   SNPE_AIP_LAYER_INPUT_BUFFER_NAME_TRUNCATED            = 1406,\n   SNPE_AIP_LAYER_OUTPUT_BUFFER_NAME_TRUNCATED           = 1407,\n   SNPE_AIP_RUNTIME_COMMUNICATION_ERROR                  = 1408,\n   SNPE_AIP_RUNTIME_INVALID_PARAM_ERROR                  = 1409,\n   SNPE_AIP_RUNTIME_SYSTEM_ERROR                         = 1410,\n   SNPE_AIP_RUNTIME_TENSOR_MISSING                       = 1411,\n   SNPE_AIP_RUNTIME_TENSOR_SHAPE_MISMATCH                = 1412,\n   SNPE_AIP_RUNTIME_BAD_AIX_RECORD                       = 1413,\n\n   // DlCaching errors\n   SNPE_DLCACHING_INVALID_METADATA                       = 1500,\n   SNPE_DLCACHING_INVALID_INITBLOB                       = 1501,\n\n   // Infrastructure Errors\n   SNPE_INFRA_CLUSTERMGR_INSTANCE_INVALID                = 1600,\n   SNPE_INFRA_CLUSTERMGR_EXECUTE_SYNC_FAILED             = 1601\n\n};\n\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * Returns the error code of the last error encountered.\n *\n * @return The error code.\n *\n * @note The returned error code is significant only when the return\n *       value of the call indicated an error.\n */\nZDL_EXPORT ErrorCode getLastErrorCode();\n\n/**\n * Returns the error string of the last error encountered.\n *\n * @return The error string.\n *\n * @note The returned error string is significant only when the return\n *       value of the call indicated an error.\n */\nZDL_EXPORT const char* getLastErrorString();\n\n/**\n * Returns the info string of the last error encountered.\n */\nZDL_EXPORT const char* getLastInfoString();\n\n/**\n * Returns the uint32_t representation of the error code enum.\n *\n * @param[in] code The error code to be converted.\n *\n * @return uint32_t representation of the error code.\n */\nZDL_EXPORT uint32_t enumToUInt32(zdl::DlSystem::ErrorCode code);\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n} // DlSystem\n} // zdl\n\n#endif // _DL_ERROR_HPP_\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/DlOptional.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2016, 2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _DL_SYSTEM_OPTIONAL_HPP_\n#define _DL_SYSTEM_OPTIONAL_HPP_\n\n#include <cstdio>\n#include <utility>\n#include <stdexcept>\n\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl {\nnamespace DlSystem {\n\ntemplate <typename T>\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * Class to manage a value that may or may not exist. The boolean value\n * of the Optional class is true if the object contains a value and false\n * if it does not contain a value.\n *\n * The class must be evaluated and confirmed as true (containing a value)\n * before being dereferenced.\n */\nclass ZDL_EXPORT Optional final {\npublic:\n   enum class LIFECYCLE {\n      NONE = 0,\n      REFERENCE_OWNED = 1,\n      POINTER_OWNED = 2,\n      POINTER_NOT_OWNED = 3\n   };\n\n   struct ReferenceCount {\n      size_t count = 0;\n\n      void increment() { count++; }\n\n      size_t decrement() {\n         if (count > 0) {\n            count--;\n         }\n         return count;\n      }\n   };\n\n   using U = typename std::remove_pointer<T>::type;\n\n   /**\n    * The default constructor is set to not have any value, and is\n    * therefore evaluated as false.\n    */\n   // Do not explicit it so we can return {}\n   Optional() {\n      m_Type = LIFECYCLE::NONE;\n   }\n\n   /**\n    * Construct an Optional class using an object.\n    * @param[in] Reference to an object v\n    * @param[out] Optional instance of object v\n    */\n   template <typename Q = T>\n   Optional (const T& v, typename std::enable_if<!std::is_pointer<Q>::value>::type* = 0)\n           : m_Type(LIFECYCLE::REFERENCE_OWNED) {\n      try {\n         m_StoragePtr = new T(v);\n      } catch (...) {\n         m_StoragePtr = nullptr;\n         m_Type = LIFECYCLE::NONE;\n      }\n   }\n\n   template <typename Q = T>\n   Optional(U* v, LIFECYCLE type, typename std::enable_if<std::is_pointer<Q>::value>::type* = 0)\n           : m_Type(type) {\n      switch (m_Type) {\n         case LIFECYCLE::POINTER_OWNED:\n            m_StoragePtr = v;\n            m_Count = new ReferenceCount();\n            m_Count->increment();\n            break;\n         case LIFECYCLE::POINTER_NOT_OWNED:\n            m_StoragePtr = v;\n            break;\n         case LIFECYCLE::REFERENCE_OWNED:\n            throw std::bad_exception();\n         case LIFECYCLE::NONE:\n            break;\n      }\n   }\n\n   Optional(const Optional &other) : m_Type(other.m_Type), m_Count(other.m_Count) {\n      if (isReference()) {\n         m_StoragePtr = new U(*other.m_StoragePtr);\n      } else if (isPointer()) {\n         m_StoragePtr = other.m_StoragePtr;\n         if (isOwned()) {\n            m_Count->increment();\n         }\n      }\n   }\n\n   Optional& operator=(const Optional& other) noexcept {\n      Optional tmp(other);\n      swap(std::move(tmp));\n      return *this;\n   }\n\n   Optional(Optional&& other) noexcept {\n      swap(std::move(other));\n   }\n\n   Optional& operator=(Optional&& other) noexcept {\n      swap(std::move(other));\n      return *this;\n   }\n\n   ~Optional() {\n      if (isOwned()) {\n         if (isReference() || (isPointer() && m_Count->decrement() == 0)) {\n            delete m_StoragePtr;\n            delete m_Count;\n         }\n      }\n   }\n\n   /**\n    * Boolean value of Optional class is only true when there exists a value.\n    */\n   operator bool() const noexcept { return isValid(); }\n\n   bool operator!() const noexcept { return !isValid(); }\n\n   /**\n    * Get reference of Optional object\n    * @warning User must validate Optional has value before.\n    */\n   const T& operator*() { return this->GetReference(); }\n\n   /**\n    * Get reference of Optional object\n    * @warning User must validate Optional has value before.\n    */\n   const T& operator*() const { return this->GetReference(); }\n\n   operator T&() { return this->GetReference(); }\n\n   T operator->() {\n      T self = this->GetReference();\n      return self;\n   }\nprivate:\n   void swap(Optional&& other) {\n      m_Type = other.m_Type;\n      m_StoragePtr = other.m_StoragePtr;\n      m_Count = other.m_Count;\n\n      other.m_Type = LIFECYCLE::NONE;\n      other.m_StoragePtr = nullptr;\n      other.m_Count = nullptr;\n   }\n\n   template <typename Q = T>\n   typename std::enable_if<std::is_same<U, Q>::value, const Q&>::type GetReference() const noexcept {\n      if (!isReference()) std::terminate();\n      return *static_cast<const Q*>(m_StoragePtr);\n   }\n\n   template <typename Q = T>\n   typename std::enable_if<std::is_same<U*, Q>::value, const Q&>::type GetReference() const noexcept {\n      if (!isPointer()) std::terminate();\n      return static_cast<const Q&>(m_StoragePtr);\n   }\n\n   template <typename Q = T>\n   typename std::enable_if<std::is_same<U, Q>::value, Q&>::type GetReference() noexcept {\n      if (!isReference()) std::terminate();\n      return *m_StoragePtr;\n   }\n\n   template <typename Q = T>\n   typename std::enable_if<std::is_same<U*, Q>::value, Q&>::type GetReference() noexcept {\n      if (!isPointer()) std::terminate();\n      return m_StoragePtr;\n   }\n\n   bool isPointer() const {\n      return m_Type == LIFECYCLE::POINTER_OWNED || m_Type == LIFECYCLE::POINTER_NOT_OWNED;\n   }\n\n   bool isOwned() const {\n      return m_Type == LIFECYCLE::REFERENCE_OWNED || m_Type == LIFECYCLE::POINTER_OWNED;\n   }\n\n   bool isReference() const {\n      return m_Type == LIFECYCLE::REFERENCE_OWNED;\n   }\n\n   bool isValid() const {\n      return m_Type != LIFECYCLE::NONE;\n   }\n\n   U* m_StoragePtr = nullptr;\n   LIFECYCLE m_Type;\n   ReferenceCount *m_Count = nullptr;\n};\n\n} // ns DlSystem\n} // ns zdl\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // _DL_SYSTEM_OPTIONAL_HPP_\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/DlVersion.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2014-2015 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n\n#ifndef _DL_VERSION_HPP_\n#define _DL_VERSION_HPP_\n\n#include \"ZdlExportDefine.hpp\"\n#include <stdint.h>\n#include <string>\n#include \"DlSystem/String.hpp\"\n\n\nnamespace zdl {\nnamespace DlSystem\n{\n   class Version_t;\n}}\n\n\nnamespace zdl { namespace DlSystem\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * A class that contains the different portions of a version number.\n */\nclass ZDL_EXPORT Version_t\n{\npublic:\n   /// Holds the major version number. Changes in this value indicate\n   /// major changes that break backward compatibility.\n   int32_t         Major;\n\n   /// Holds the minor version number. Changes in this value indicate\n   /// minor changes made to library that are backwards compatible\n   /// (such as additions to the interface).\n   int32_t         Minor;\n\n   /// Holds the teeny version number. Changes in this value indicate\n   /// changes such as bug fixes and patches made to the library that\n   /// do not affect the interface.\n   int32_t         Teeny;\n\n   /// This string holds information about the build version.\n   ///\n   std::string     Build;\n\n   static zdl::DlSystem::Version_t fromString(const std::string &stringValue);\n\n   static zdl::DlSystem::Version_t fromString(const zdl::DlSystem::String &stringValue);\n\n   /**\n    * @brief Returns a string in the form Major.Minor.Teeny.Build\n    *\n    * @return A formatted string holding the version information.\n    */\n   const std::string toString() const;\n\n   /**\n    * @brief Returns a string in the form Major.Minor.Teeny.Build\n    *\n    * @return A formatted string holding the version information.\n    */\n   const zdl::DlSystem::String asString() const;\n};\n\n}}\n\n/** @} */ /* end_addtogroup c_plus_plus_apis */\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/IBufferAttributes.hpp",
    "content": "//==============================================================================\n//\n// Copyright (c) 2017-2019 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _IBUFFER_ATTRIBUTES_HPP\n#define _IBUFFER_ATTRIBUTES_HPP\n#include \"IUserBuffer.hpp\"\n#include \"TensorShape.hpp\"\n#include \"ZdlExportDefine.hpp\"\n\nnamespace zdl {\n    namespace DlSystem {\n        class UserBufferEncoding;\n    }\n}\n\nnamespace zdl {\nnamespace DlSystem {\n\n/**\n * @brief IBufferAttributes returns a buffer's dimension and alignment\n *        requirements, along with info on its encoding type\n */\nclass ZDL_EXPORT IBufferAttributes {\npublic:\n\n    /**\n      * @brief Gets the buffer's element size, in bytes\n      *\n      * This can be used to compute the memory size required\n      * to back this buffer.\n      *\n      * @return Element size, in bytes\n     */\n    virtual size_t getElementSize() const noexcept = 0;\n\n    /**\n      * @brief Gets the element's encoding type\n      *\n      * @return encoding type\n     */\n    virtual zdl::DlSystem::UserBufferEncoding::ElementType_t getEncodingType() const noexcept = 0;\n\n    /**\n      * @brief Gets the number of elements in each dimension\n      *\n      * @return Dimension size, in terms of number of elements\n     */\n    virtual const TensorShape getDims() const noexcept = 0;\n\n    /**\n      * @brief Gets the alignment requirement of each dimension\n      *\n      * Alignment per each dimension is expressed as an multiple, for\n      * example, if one particular dimension can accept multiples of 8,\n      * the alignment will be 8.\n      *\n      * @return Alignment in each dimension, in terms of multiple of\n      *         number of elements\n     */\n    virtual const TensorShape getAlignments() const noexcept = 0;\n\n    /**\n      * @brief Gets the buffer encoding returned from the network responsible\n      * for generating this buffer. Depending on the encoding type, this will\n      * be an instance of an encoding type specific derived class.\n      *\n      * @return Derived user buffer encoding object.\n     */\n    virtual zdl::DlSystem::UserBufferEncoding* getEncoding() const noexcept = 0;\n\n    virtual ~IBufferAttributes() {}\n};\n\n\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/ITensor.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _ITENSOR_HPP_\n#define _ITENSOR_HPP_\n\n#include \"ITensorItr.hpp\"\n#include \"ITensorItrImpl.hpp\"\n#include \"TensorShape.hpp\"\n#include \"ZdlExportDefine.hpp\"\n#include <memory>\n#include <ostream>\n#include <cmath>\n\nnamespace zdl {\nnamespace DlSystem\n{\n   class ITensor;\n}}\n\nnamespace zdl { namespace DlSystem\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * Represents a tensor which holds n-dimensional data. It is important to\n * understand how the tensor data is represented in memory \n * relative to the tensor dimensions. Tensors store data in \n * memory in row-major order (i.e. the last tensor dimension is \n * the fastest varying one). For example, if you have a two \n * dimensional tensor with 3 rows and 2 columns (i.e. the tensor \n * dimensions are 3,2 as returned in tensor dimension vectors)\n * with the following data in terms rows and columns: \n *  \n * | 1 2 | <br/>\n * | 3 4 | <br/>\n * | 5 6 | <br/>\n *  \n * This data would be stored in memory as 1,2,3,4,5,6. \n */\nclass ZDL_EXPORT ITensor \n{\npublic:\n\n   typedef zdl::DlSystem::ITensorItr<false> iterator;\n   typedef zdl::DlSystem::ITensorItr<true> const_iterator;\n\n   virtual ~ITensor() {}\n\n   /**\n    * Returns a tensor iterator pointing to the beginning \n    * of the data in the tensor.\n    * \n    * @return A tensor iterator that points to the first data\n    *         element in the tensor.\n    */\n   virtual iterator begin() = 0;\n\n   /**\n    * Returns the const version of a tensor iterator \n    * pointing to the beginning of the data in the tensor.\n    * \n    * @return A tensor const iterator that points to the first data\n    *         element in the tensor.\n    */\n   virtual const_iterator cbegin() const = 0;\n\n   /**\n    * Returns a tensor iterator pointing to the end of the\n    * data in the tensor. This tensor should not be\n    * dereferenced.\n    * \n    * @return A tensor iterator that points to the end of the data \n    *         (one past the last element) in the tensor.\n    */\n   virtual iterator end() = 0;\n\n   /**\n    * Returns the const version of a tensor iterator \n    * pointing to the end of the data in the tensor. This\n    * tensor should not be dereferenced.\n    * \n    * @return A tensor const iterator that points to the end of the\n    *         data (one past the last element) in the tensor.\n    */\n   virtual const_iterator cend() const = 0;\n\n   /**\n    * @brief Gets the shape of this tensor.\n    *  \n    * The last element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest \n    * varying dimension, etc. \n    * \n    * @return A shape class holding the tensor dimensions.\n    */\n   virtual TensorShape getShape() const = 0;\n\n   /**\n    * Returns the element size of the data in the tensor \n    * (discounting strides). This is how big a buffer would\n    * need to be to hold the tensor data contiguously in\n    * memory.\n    *  \n    * @return The size of the tensor (in elements).\n    */\n   virtual size_t getSize() const = 0;\n\n   /**\n    * @brief Serializes the tensor to an output stream.\n    * \n    * @param[in] output The output stream to which to write the tensor \n    *  \n    * @throw std::runtime_error If the stream is ever in a bad \n    *        state before the tensor is fully serialized.\n    */\n   virtual void serialize(std::ostream &output) const = 0;\n\n   friend iterator;\n   friend const_iterator;\n\n   virtual bool isQuantized() {return false;}\n   virtual float GetDelta() {return NAN;};\n   virtual float GetOffset() {return NAN;};\n\nprotected:\n\n   /**\n    * Returns the tensor iterator implementation.\n    * \n    * @return A pointer to the tensor iterator implementation.\n    */\n   virtual std::unique_ptr<::DlSystem::ITensorItrImpl> getItrImpl() const = 0;\n};\n\n}}\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/ITensorFactory.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015-2016 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _ITENSOR_FACTORY_HPP\n#define _ITENSOR_FACTORY_HPP\n\n#include \"ITensor.hpp\"\n#include \"TensorShape.hpp\"\n#include \"ZdlExportDefine.hpp\"\n#include <istream>\n\nnamespace zdl {\n    namespace DlSystem\n    {\n        class ITensor;\n        class TensorShape;\n    }\n}\n\nnamespace zdl { namespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * Factory interface class to create ITensor objects.\n */\nclass ZDL_EXPORT ITensorFactory\n{\npublic:\n   virtual ~ITensorFactory() = default;\n\n   /**\n    * Creates a new ITensor with uninitialized data. \n    *  \n    * The strides for the tensor will match the tensor dimensions \n    * (i.e., the tensor data is contiguous in memory).\n    *  \n    * @param[in] shape The dimensions for the tensor in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    * \n    * @return A pointer to the created tensor or nullptr if creating failed.\n    */\n   virtual std::unique_ptr<ITensor>\n      createTensor(const TensorShape &shape) noexcept = 0;\n\n   /**\n    * Creates a new ITensor by loading it from a file.\n    *  \n    * @param[in] input The input stream from which to read the tensor \n    *                  data.\n    *  \n    * @return A pointer to the created tensor or nullptr if creating failed.\n    *\n    */\n   virtual std::unique_ptr<ITensor> createTensor(std::istream &input) noexcept = 0;\n\n   /**\n    * Create a new ITensor with specific data.\n    * (i.e. the tensor data is contiguous in memory). This tensor is\n    * primarily used to create a tensor where tensor size can't be\n    * computed directly from dimension. One such example is\n    * NV21-formatted image, or any YUV formatted image\n    *\n    * @param[in] shape The dimensions for the tensor in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    *\n    * @param[in] data The actual data with which the Tensor object is filled.\n    *\n    * @param[in] dataSize The size of data\n    *\n    * @return A pointer to the created tensor\n    */\n   virtual std::unique_ptr<ITensor>\n      createTensor(const TensorShape &shape, const unsigned char *data, size_t dataSize) noexcept = 0;\n};\n\n}}\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/ITensorItr.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _ITENSOR_ITR_HPP_\n#define _ITENSOR_ITR_HPP_\n\n#include \"ZdlExportDefine.hpp\"\n#include \"ITensorItrImpl.hpp\"\n\n#include <memory>\n#include <iterator>\n#include <iostream>\n\nnamespace zdl {\nnamespace DlSystem\n{\n   template<bool IS_CONST> class ITensorItr;\n   class ITensor;\n   void ZDL_EXPORT fill(ITensorItr<false> first, ITensorItr<false> end, float val);\n   template<class InItr, class OutItr> OutItr ZDL_EXPORT copy(InItr first, InItr last, OutItr result)\n   {\n      return std::copy(first, last, result);\n   }\n}}\nnamespace DlSystem\n{\n   class ITensorItrImpl;\n}\n\nnamespace zdl { namespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * A bidirectional iterator (with limited random access \n * capabilities) for the zdl::DlSystem::ITensor class.\n *  \n * This is a standard bidrectional iterator and is compatible\n * with standard algorithm functions that operate on bidirectional \n * access iterators (e.g., std::copy, std::fill, etc.). It uses a\n * template parameter to create const and non-const iterators \n * from the same code. Iterators are easiest to declare via the \n * typedefs iterator and const_iterator in the ITensor class \n * (e.g., zdl::DlSystem::ITensor::iterator). \n *  \n * Note that if the tensor the iterator is traversing was \n * created with nondefault (i.e., nontrivial) strides, the \n * iterator will obey the strides when traversing the tensor \n * data. \n *  \n * Also note that nontrivial strides dramatically affect the\n * performance of the iterator (on the order of 20x slower). \n */ \ntemplate<bool IS_CONST=true>\nclass ZDL_EXPORT ITensorItr : public std::iterator<std::bidirectional_iterator_tag, float>\n{\npublic:\n\n   typedef typename std::conditional<IS_CONST, const float&, float&>::type VALUE_REF;\n\n   ITensorItr() = delete;\n   virtual ~ITensorItr() {}\n\n   ITensorItr(std::unique_ptr<::DlSystem::ITensorItrImpl> impl, \n              bool isTrivial = false, \n              float* data = nullptr)\n      : m_Impl(impl->clone())\n      , m_IsTrivial(isTrivial)\n      , m_Data(data)\n      , m_DataStart(data) {}\n\n   ITensorItr(const ITensorItr<IS_CONST>& itr)\n      : m_Impl(itr.m_Impl->clone()),\n        m_IsTrivial(itr.m_IsTrivial),\n        m_Data(itr.m_Data),\n        m_DataStart(itr.m_DataStart) {}\n\n   zdl::DlSystem::ITensorItr<IS_CONST>& operator=(const ITensorItr<IS_CONST>& other)\n   {\n      if (this == &other) return *this;\n      m_Impl = std::move(other.m_Impl->clone());\n      m_IsTrivial = other.m_IsTrivial;\n      m_Data = other.m_Data;\n      m_DataStart = other.m_DataStart;\n      return *this;\n   }\n\n   inline zdl::DlSystem::ITensorItr<IS_CONST>& operator++()\n   {\n      if (m_IsTrivial) m_Data++; else m_Impl->increment();\n      return *this;\n   }\n   inline zdl::DlSystem::ITensorItr<IS_CONST> operator++(int)\n   {\n      ITensorItr tmp(*this);\n      operator++();\n      return tmp;\n   }\n   inline zdl::DlSystem::ITensorItr<IS_CONST>& operator--()\n   {\n      if (m_IsTrivial) m_Data--; else m_Impl->decrement();\n      return *this;\n   }\n   inline zdl::DlSystem::ITensorItr<IS_CONST> operator--(int)\n   {\n      ITensorItr tmp(*this);\n      operator--();\n      return tmp;\n   }\n   inline zdl::DlSystem::ITensorItr<IS_CONST>& operator+=(int rhs)\n   {\n      if (m_IsTrivial) m_Data += rhs; else m_Impl->increment(rhs);\n      return *this;\n   }\n   inline friend zdl::DlSystem::ITensorItr<IS_CONST> operator+(zdl::DlSystem::ITensorItr<IS_CONST> lhs, int rhs)\n      { lhs += rhs; return lhs; }\n   inline zdl::DlSystem::ITensorItr<IS_CONST>& operator-=(int rhs)\n   {\n      if (m_IsTrivial) m_Data -= rhs; else m_Impl->decrement(rhs);\n      return *this;\n   }\n   inline friend zdl::DlSystem::ITensorItr<IS_CONST> operator-(zdl::DlSystem::ITensorItr<IS_CONST> lhs, int rhs)\n      { lhs -= rhs; return lhs; }\n\n   inline size_t operator-(const zdl::DlSystem::ITensorItr<IS_CONST>& rhs)\n   {\n      if (m_IsTrivial) return (m_Data - m_DataStart) - (rhs.m_Data - rhs.m_DataStart);\n      return m_Impl->getPosition() - rhs.m_Impl->getPosition();\n   }\n\n   inline friend bool operator<(const ITensorItr<IS_CONST>& lhs, const ITensorItr<IS_CONST>& rhs)\n   {\n      if (lhs.m_IsTrivial) return lhs.m_Data < rhs.m_Data;\n      return lhs.m_Impl->dataPointer() < rhs.m_Impl->dataPointer();\n   }\n   inline friend bool operator>(const ITensorItr<IS_CONST>& lhs, const ITensorItr<IS_CONST>& rhs)\n      { return rhs < lhs; }\n   inline friend bool operator<=(const ITensorItr<IS_CONST>& lhs, const ITensorItr<IS_CONST>& rhs)\n      { return !(lhs > rhs); }\n   inline friend bool operator>=(const ITensorItr<IS_CONST>& lhs, const ITensorItr<IS_CONST>& rhs)\n      { return !(lhs < rhs); }\n\n   inline bool operator==(const ITensorItr<IS_CONST>& rhs) const\n   {\n      if (m_IsTrivial) return m_Data == rhs.m_Data;\n      return m_Impl->dataPointer() == rhs.m_Impl->dataPointer();\n   }\n   inline bool operator!=(const ITensorItr<IS_CONST>& rhs) const\n      { return !operator==(rhs); }\n\n   inline VALUE_REF operator[](size_t idx)\n   {\n      if (m_IsTrivial) return *(m_DataStart + idx);\n      return m_Impl->getReferenceAt(idx);\n   }\n   inline VALUE_REF operator*()\n      { if (m_IsTrivial) return *m_Data; else return m_Impl->getReference(); }\n   inline VALUE_REF operator->()\n      { return *(*this); }\n   inline float* dataPointer() const\n      { if (m_IsTrivial) return m_Data; else return m_Impl->dataPointer(); }\n\n\nprotected:\n   std::unique_ptr<::DlSystem::ITensorItrImpl> m_Impl;\n   bool m_IsTrivial = false;\n   float* m_Data = nullptr;\n   float* m_DataStart = nullptr;\n};\n\n}}\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/ITensorItrImpl.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _ITENSOR_ITR_IMPL_HPP_\n#define _ITENSOR_ITR_IMPL_HPP_\n\n#include \"ZdlExportDefine.hpp\"\n\n#include <memory>\n#include <iterator>\n\nnamespace DlSystem\n{\n   class ITensorItrImpl;\n}\n\nclass ZDL_EXPORT DlSystem::ITensorItrImpl\n{\npublic:\n   ITensorItrImpl() {}\n   virtual ~ITensorItrImpl() {}\n\n   virtual float getValue() const = 0;\n   virtual float& getReference() = 0;\n   virtual float& getReferenceAt(size_t idx) = 0;\n   virtual float* dataPointer() const = 0;\n   virtual void increment(int incVal = 1) = 0;\n   virtual void decrement(int decVal = 1) = 0;\n   virtual size_t getPosition() = 0;\n   virtual std::unique_ptr<DlSystem::ITensorItrImpl> clone() = 0;\n\nprivate:\n   ITensorItrImpl& operator=(const ITensorItrImpl& other) = delete;\n   ITensorItrImpl(const ITensorItrImpl& other) = delete;\n};\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/IUDL.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2016-2017 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _DL_SYSTEM_IUDL_HPP_\n#define _DL_SYSTEM_IUDL_HPP_\n\n#include \"ZdlExportDefine.hpp\"\n\nnamespace zdl {\nnamespace DlSystem {\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * Base class user concrete UDL implementation.\n *\n * All functions are marked as:\n *\n * - virtual\n * - noexcept\n *\n * User should make sure no exceptions are propagated outside of\n * their module. Errors can be communicated via return values.\n */\nclass ZDL_EXPORT IUDL {\npublic:\n   /**\n    * @brief .\n    *\n    * Destructor\n    */\n   virtual ~IUDL() = default;\n\n   /**\n    * @brief Sets up the user's environment.\n    * This is called by the SNPE framework to allow the user the\n    * opportunity to setup anything which is needed for running\n    * user defined layers.\n    *\n    * @param cookie User provided opaque data returned by the SNPE\n    *               runtime\n    *\n    * @param insz How many elements in input size array\n    * @param indim Pointer to a buffer that holds input dimension\n    *               array\n    * @param indimsz Input dimension size  array of the buffer\n    *                 'indim'. Corresponds to indim\n    *\n    * @param outsz How many elements in output size array\n    * @param outdim Pointer to a buffer that holds output\n    *              dimension array\n    * @param outdimsz Output dimension size of the buffer 'oudim'.\n    *                  Corresponds to indim\n    *\n    * @return true on success, false otherwise\n    */\n   virtual bool setup(void *cookie,\n                      size_t insz, const size_t **indim, const size_t *indimsz,\n                      size_t outsz, const size_t **outdim, const size_t *outdimsz)  = 0;\n\n   /**\n    * @brief Close the instance. Invoked by the SNPE\n    * framework to allow the user the opportunity to release any resources\n    * allocated during setup.\n    *\n    * @param cookie - User provided opaque data returned by the SNPE runtime\n    */\n   virtual void close(void *cookie) noexcept = 0;\n\n   /**\n    * @brief Execute the user defined layer\n    *\n    * @param cookie User provided opaque data returned by the SNPE \n    *               runtime\n    *\n    * @param input Const pointer to a float buffer that contains\n    *               the input\n    *\n    * @param output Float pointer to a buffer that would hold\n    *                 the user defined layer's output. This buffer\n    *                 is allocated and owned by SNPE runtime.\n    */\n   virtual bool execute(void *cookie, const float **input, float **output)  = 0;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n} // ns DlSystem\n\n} // ns zdl\n\n#endif // _DL_SYSTEM_IUDL_HPP_\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/IUserBuffer.hpp",
    "content": "//==============================================================================\n//\n// Copyright (c) 2017-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _IUSER_BUFFER_HPP\n#define _IUSER_BUFFER_HPP\n\n#include \"TensorShape.hpp\"\n#include \"ZdlExportDefine.hpp\"\n#include <math.h>\n\nnamespace zdl {\nnamespace DlSystem {\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n\n/**\n  * @brief .\n  *\n  * A base class buffer encoding type\n  */\nclass ZDL_EXPORT UserBufferEncoding {\npublic:\n\n    /**\n      * @brief .\n      *\n      * An enum class of all supported element types in a IUserBuffer\n      */\n    enum class ElementType_t\n    {\n        /// Unknown element type.\n        UNKNOWN         = 0,\n\n        /// Each element is presented by float.\n        FLOAT           = 1,\n\n        /// Each element is presented by an unsigned int.\n        UNSIGNED8BIT    = 2,\n\n        /// Each element is presented by an 8-bit quantized value.\n        TF8             = 10,\n\n        /// Each element is presented by an 16-bit quantized value.\n        TF16            = 11\n    };\n\n    /**\n      * @brief Retrieves the size of the element, in bytes.\n      *\n      * @return Size of the element, in bytes.\n     */\n    virtual size_t getElementSize() const noexcept = 0;\n\n    /**\n      * @brief Retrieves the element type\n      *\n      * @return Element type\n     */\n    ElementType_t getElementType() const noexcept {return m_ElementType;};\n\n    virtual ~UserBufferEncoding() {}\n\nprotected:\n    UserBufferEncoding(ElementType_t  elementType) : m_ElementType(elementType) {};\nprivate:\n    const ElementType_t  m_ElementType;\n};\n\n/**\n  * @brief .\n  *\n  * A base class buffer source type\n  *\n  * @note User buffer from CPU support all kinds of runtimes;\n  *       User buffer from GLBUFFER support only GPU runtime.\n  */\nclass ZDL_EXPORT UserBufferSource {\npublic:\n   enum class SourceType_t\n   {\n      /// Unknown buffer source type.\n      UNKNOWN = 0,\n\n      /// The network inputs are from CPU buffer.\n      CPU = 1,\n\n      /// The network inputs are from OpenGL buffer.\n      GLBUFFER = 2\n   };\n\n   /**\n     * @brief Retrieves the source type\n     *\n     * @return Source type\n    */\n   SourceType_t getSourceType() const noexcept {return m_SourceType;};\n\nprotected:\n   UserBufferSource(SourceType_t sourceType): m_SourceType(sourceType) {};\nprivate:\n   const SourceType_t m_SourceType;\n};\n\n/**\n  * @brief .\n  *\n  * An source type where input data is delivered from OpenGL buffer\n  */\nclass ZDL_EXPORT UserBufferSourceGLBuffer : public UserBufferSource{\npublic:\n   UserBufferSourceGLBuffer() : UserBufferSource(SourceType_t::GLBUFFER) {};\n};\n\n/**\n  * @brief .\n  *\n  * An encoding type where each element is represented by an unsigned int\n  */\nclass ZDL_EXPORT UserBufferEncodingUnsigned8Bit : public UserBufferEncoding {\npublic:\n    UserBufferEncodingUnsigned8Bit() : UserBufferEncoding(ElementType_t::UNSIGNED8BIT) {};\n    size_t getElementSize() const noexcept override;\n\nprotected:\n    UserBufferEncodingUnsigned8Bit(ElementType_t  elementType) : UserBufferEncoding(elementType) {};\n\n};\n\n/**\n  * @brief .\n  *\n  * An encoding type where each element is represented by a float\n  */\nclass ZDL_EXPORT UserBufferEncodingFloat : public UserBufferEncoding {\npublic:\n    UserBufferEncodingFloat() : UserBufferEncoding(ElementType_t::FLOAT) {};\n    size_t getElementSize() const noexcept override;\n\n};\n\n/**\n  * @brief .\n  *\n  * An encoding type where each element is represented by tf8, which is an\n  * 8-bit quantizd value, which has an exact representation of 0.0\n  */\n\nclass ZDL_EXPORT UserBufferEncodingTf8 : public UserBufferEncodingUnsigned8Bit {\npublic:\n    UserBufferEncodingTf8() = delete;\n    UserBufferEncodingTf8(unsigned char stepFor0, float stepSize) :\n            UserBufferEncodingUnsigned8Bit(ElementType_t::TF8),\n            m_StepExactly0(stepFor0),\n            m_QuantizedStepSize(stepSize) {};\n\n    UserBufferEncodingTf8(const zdl::DlSystem::UserBufferEncoding &ubEncoding) : UserBufferEncodingUnsigned8Bit(ubEncoding.getElementType()){\n            const zdl::DlSystem::UserBufferEncodingTf8* ubEncodingTf8\n                            = dynamic_cast <const zdl::DlSystem::UserBufferEncodingTf8*> (&ubEncoding);\n            if (ubEncodingTf8) {\n                m_StepExactly0 = ubEncodingTf8->getStepExactly0();\n                m_QuantizedStepSize = ubEncodingTf8->getQuantizedStepSize();\n            }\n    }\n\n/**\n      * @brief Sets the step value that represents 0\n      *\n      * @param[in] stepExactly0 The step value that represents 0\n      *\n     */\n\n    void setStepExactly0(const unsigned char stepExactly0) {\n        m_StepExactly0 = stepExactly0;\n    }\n\n\n/**\n      * @brief Sets the float value that each step represents\n      *\n      * @param[in] quantizedStepSize The float value of each step size\n      *\n     */\n\n    void setQuantizedStepSize(const float quantizedStepSize) {\n        m_QuantizedStepSize = quantizedStepSize;\n    }\n\n\n/**\n      * @brief Retrieves the step that represents 0.0\n      *\n      * @return Step value\n     */\n\n    unsigned char getStepExactly0() const {\n        return m_StepExactly0;\n    }\n\n\n/**\n     * Calculates the minimum floating point value that\n     * can be represented with this encoding.\n     *\n     * @return Minimum representable floating point value\n     */\n\n    float getMin() const {\n        return m_QuantizedStepSize * (0 - m_StepExactly0);\n    }\n\n\n/**\n     * Calculates the maximum floating point value that\n     * can be represented with this encoding.\n     *\n     * @return Maximum representable floating point value\n     */\n\n    float getMax() const {\n        return m_QuantizedStepSize * (255 - m_StepExactly0);\n    }\n\n\n/**\n      * @brief Retrieves the step size\n      *\n      * @return Step size\n     */\n\n    float getQuantizedStepSize() const {\n        return m_QuantizedStepSize;\n    }\n\nprivate:\n    unsigned char m_StepExactly0;\n\n    float m_QuantizedStepSize;\n};\n\n\n\nclass ZDL_EXPORT UserBufferEncodingTfN : public UserBufferEncoding {\npublic:\n   UserBufferEncodingTfN() = delete;\n   UserBufferEncodingTfN(uint64_t stepFor0, float stepSize, uint8_t bWidth=8):\n                                           UserBufferEncoding(getTypeFromWidth(bWidth)),\n                                           bitWidth(bWidth),\n                                           m_StepExactly0(stepFor0),\n                                           m_QuantizedStepSize(stepSize){};\n\n   UserBufferEncodingTfN(const zdl::DlSystem::UserBufferEncoding &ubEncoding) : UserBufferEncoding(ubEncoding.getElementType()){\n            const zdl::DlSystem::UserBufferEncodingTfN* ubEncodingTfN\n                            = dynamic_cast <const zdl::DlSystem::UserBufferEncodingTfN*> (&ubEncoding);\n            if (ubEncodingTfN) {\n                m_StepExactly0 = ubEncodingTfN->getStepExactly0();\n                m_QuantizedStepSize = ubEncodingTfN->getQuantizedStepSize();\n                bitWidth = ubEncodingTfN->bitWidth;\n            }\n   }\n\n   size_t getElementSize() const noexcept override;\n   /**\n      * @brief Sets the step value that represents 0\n      *\n      * @param[in] stepExactly0 The step value that represents 0\n      *\n     */\n   void setStepExactly0(uint64_t stepExactly0) {\n      m_StepExactly0 = stepExactly0;\n   }\n\n   /**\n     * @brief Sets the float value that each step represents\n     *\n     * @param[in] quantizedStepSize The float value of each step size\n     *\n    */\n   void setQuantizedStepSize(const float quantizedStepSize) {\n      m_QuantizedStepSize = quantizedStepSize;\n   }\n\n   /**\n     * @brief Retrieves the step that represents 0.0\n     *\n     * @return Step value\n    */\n   uint64_t getStepExactly0() const {\n      return m_StepExactly0;\n   }\n\n   /**\n    * Calculates the minimum floating point value that\n    * can be represented with this encoding.\n    *\n    * @return Minimum representable floating point value\n    */\n   float getMin() const {\n      return static_cast<float>(m_QuantizedStepSize * (0 - (double)m_StepExactly0));\n   }\n\n   /**\n    * Calculates the maximum floating point value that\n    * can be represented with this encoding.\n    *\n    * @return Maximum representable floating point value\n    */\n   float getMax() const{\n       return static_cast<float>(m_QuantizedStepSize * (pow(2,bitWidth)-1 - (double)m_StepExactly0));\n   };\n\n   /**\n     * @brief Retrieves the step size\n     *\n     * @return Step size\n    */\n   float getQuantizedStepSize() const {\n      return m_QuantizedStepSize;\n   }\n\n   ElementType_t getTypeFromWidth(uint8_t width);\n\n   uint8_t bitWidth;\nprivate:\n   uint64_t m_StepExactly0;\n   float m_QuantizedStepSize;\n};\n\n\n/**\n * @brief UserBuffer contains a pointer and info on how to walk it and interpret its content.\n */\nclass ZDL_EXPORT IUserBuffer {\npublic:\n    virtual ~IUserBuffer() = default;\n    \n    /**\n      * @brief Retrieves the total number of bytes between elements in each dimension if\n      * the buffer were to be interpreted as a multi-dimensional array.\n      *\n      * @return Number of bytes between elements in each dimension.\n      * e.g. A tightly packed tensor of floats with dimensions [4, 3, 2] would\n      * return strides of [24, 8, 4].\n     */\n    virtual const TensorShape& getStrides() const = 0;\n\n    /**\n      * @brief Retrieves the size of the buffer, in bytes.\n      *\n      * @return Size of the underlying buffer, in bytes.\n     */\n    virtual size_t getSize() const = 0;\n\n    /**\n      * @brief Retrieves the size of the inference data in the buffer, in bytes.\n      *\n      * The inference results from a dynamic-sized model may not be exactly the same size\n      * as the UserBuffer provided to SNPE. This function can be used to get the amount\n      * of output inference data, which may be less or greater than the size of the UserBuffer.\n      *\n      * If the inference results fit in the UserBuffer, getOutputSize() would be less than\n      * or equal to getSize(). But if the inference results were more than the capacity of\n      * the provided UserBuffer, the results would be truncated to fit the UserBuffer. But,\n      * getOutputSize() would be greater than getSize(), which indicates a bigger buffer\n      * needs to be provided to SNPE to hold all of the inference results.\n      *\n      * @return Size required for the buffer to hold all inference results, which can be less\n      * or more than the size of the buffer, in bytes.\n    */\n    virtual size_t getOutputSize() const = 0;\n\n    /**\n      * @brief Changes the underlying memory that backs the UserBuffer.\n      *\n      * This can be used to avoid creating multiple UserBuffer objects\n      * when the only thing that differs is the memory location.\n      *\n      * @param[in] buffer Pointer to the memory location\n      *\n      * @return Whether the set succeeds.\n     */\n    virtual bool setBufferAddress(void *buffer) noexcept = 0;\n\n    /**\n      * @brief Gets a const reference to the data encoding object of\n      *        the underlying buffer\n      *\n      * This is necessary when the UserBuffer is filled by SNPE with\n      * data types such as TF8, where the caller needs to know the quantization\n      * parameters in order to interpret the data properly\n      *\n      * @return A read-only encoding object\n     */\n    virtual const UserBufferEncoding& getEncoding() const noexcept = 0;\n\n    /**\n      * @brief Gets a reference to the data encoding object of\n      *        the underlying buffer\n      *\n      * This is necessary when the UserBuffer is re-used, and the encoding\n      * parameters can change.  For example, each input can be quantized with\n      * different step sizes.\n      *\n      * @return Data encoding meta-data\n     */\n    virtual UserBufferEncoding& getEncoding() noexcept = 0;\n\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}\n}\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/IUserBufferFactory.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2017 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _IUSERBUFFER_FACTORY_HPP\n#define _IUSERBUFFER_FACTORY_HPP\n\n#include \"IUserBuffer.hpp\"\n#include \"TensorShape.hpp\"\n#include \"ZdlExportDefine.hpp\"\n#include \"DlEnums.hpp\"\nnamespace zdl {\n    namespace DlSystem {\n        class IUserBuffer;\n\n        class TensorShape;\n    }\n}\n\nnamespace zdl {\nnamespace DlSystem {\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n* Factory interface class to create IUserBuffer objects.\n*/\nclass ZDL_EXPORT IUserBufferFactory {\npublic:\n    virtual ~IUserBufferFactory() = default;\n\n    /**\n     * @brief Creates a UserBuffer\n     *\n     * @param[in] buffer Pointer to the buffer that the caller supplies\n     *\n     * @param[in] bufSize Buffer size, in bytes\n     *\n     * @param[in] strides Total number of bytes between elements in each dimension.\n     *          E.g. A tightly packed tensor of floats with dimensions [4, 3, 2] would have strides of [24, 8, 4].\n     *\n     * @param[in] userBufferEncoding Reference to an UserBufferEncoding object\n     *\n     * @note Caller has to ensure that memory pointed to by buffer stays accessible\n     *       for the lifetime of the object created\n     */\n    virtual std::unique_ptr<IUserBuffer>\n    createUserBuffer(void *buffer, size_t bufSize, const zdl::DlSystem::TensorShape &strides, zdl::DlSystem::UserBufferEncoding* userBufferEncoding) noexcept = 0;\n\n    /**\n     * @brief Creates a UserBuffer\n     *\n     * @param[in] buffer Pointer to the buffer that the caller supplies\n     *\n     * @param[in] bufSize Buffer size, in bytes\n     *\n     * @param[in] strides Total number of bytes between elements in each dimension.\n     *          E.g. A tightly packed tensor of floats with dimensions [4, 3, 2] would have strides of [24, 8, 4].\n     *\n     * @param[in] userBufferEncoding Reference to an UserBufferEncoding object\n     *\n     * @param[in] userBufferSource Reference to an UserBufferSource object\n     *\n     * @note Caller has to ensure that memory pointed to by buffer stays accessible\n     *       for the lifetime of the object created\n     */\n    virtual std::unique_ptr<IUserBuffer>\n    createUserBuffer(void *buffer, size_t bufSize, const zdl::DlSystem::TensorShape &strides, zdl::DlSystem::UserBufferEncoding* userBufferEncoding, zdl::DlSystem::UserBufferSource* userBufferSource) noexcept = 0;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}\n}\n\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/PlatformConfig.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2017-2018 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef _DL_SYSTEM_PLATFORM_CONFIG_HPP_\n#define _DL_SYSTEM_PLATFORM_CONFIG_HPP_\n\n#include \"DlSystem/ZdlExportDefine.hpp\"\n#include <string>\n\nnamespace zdl{\nnamespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n\n/**\n  * @brief .\n  *\n  * A structure OpenGL configuration\n  *\n  * @note When certain OpenGL context and display are provided to UserGLConfig for using\n  *       GPU buffer as input directly, the user MUST ensure the particular OpenGL\n  *       context and display remain vaild throughout the execution of neural network models.\n  */\nstruct ZDL_EXPORT UserGLConfig\n{\n   /// Holds user EGL context.\n   ///\n   void* userGLContext = nullptr;\n\n   /// Holds user EGL display.\n   void* userGLDisplay = nullptr;\n};\n\n/**\n  * @brief .\n  *\n  * A structure Gpu configuration\n  */\nstruct ZDL_EXPORT UserGpuConfig{\n   /// Holds user OpenGL configuration.\n   ///\n   UserGLConfig userGLConfig;\n};\n\n/**\n  * @brief .\n  *\n  * A class user platform configuration\n  */\nclass ZDL_EXPORT PlatformConfig\n{\npublic:\n\n   /**\n     * @brief .\n     *\n     * An enum class of all supported platform types\n     */\n   enum class PlatformType_t\n   {\n      /// Unknown platform type.\n      UNKNOWN = 0,\n\n      /// Snapdragon CPU.\n      CPU = 1,\n\n      /// Adreno GPU.\n      GPU = 2,\n\n      /// Hexagon DSP.\n      DSP = 3\n   };\n\n   /**\n     * @brief .\n     *\n     * A union class user platform configuration information\n     */\n   union PlatformConfigInfo\n   {\n      /// Holds user GPU Configuration.\n      ///\n      UserGpuConfig userGpuConfig;\n\n      PlatformConfigInfo(){};\n   };\n\n   PlatformConfig() : m_PlatformType(PlatformType_t::UNKNOWN),\n                      m_PlatformOptions(\"\") {};\n\n   /**\n     * @brief Retrieves the platform type\n     *\n     * @return Platform type\n     */\n   PlatformType_t getPlatformType() const {return m_PlatformType;};\n\n   /**\n     * @brief Indicates whther the plaform configuration is valid.\n     *\n     * @return True if the platform configuration is valid; false otherwise.\n     */\n   bool isValid() const {return (PlatformType_t::UNKNOWN != m_PlatformType);};\n\n   /**\n     * @brief Retrieves the Gpu configuration\n     *\n     * @param[out] userGpuConfig The passed in userGpuConfig populated with the Gpu configuration on return.\n     *\n     * @return True if Gpu configuration was retrieved; false otherwise.\n     */\n   bool getUserGpuConfig(UserGpuConfig& userGpuConfig) const\n   {\n      if(m_PlatformType == PlatformType_t::GPU)\n      {\n         userGpuConfig = m_PlatformConfigInfo.userGpuConfig;\n         return true;\n      }\n      else\n      {\n         return false;\n      }\n   }\n\n   /**\n     * @brief Sets the Gpu configuration\n     *\n     * @param[in] userGpuConfig Gpu Configuration\n     *\n     * @return True if Gpu configuration was successfully set; false otherwise.\n     */\n   bool setUserGpuConfig(UserGpuConfig& userGpuConfig)\n   {\n      if((userGpuConfig.userGLConfig.userGLContext != nullptr) && (userGpuConfig.userGLConfig.userGLDisplay != nullptr))\n      {\n         switch (m_PlatformType)\n         {\n         case PlatformType_t::GPU:\n            m_PlatformConfigInfo.userGpuConfig = userGpuConfig;\n            return true;\n         case PlatformType_t::UNKNOWN:\n            m_PlatformType = PlatformType_t::GPU;\n            m_PlatformConfigInfo.userGpuConfig = userGpuConfig;\n            return true;\n         default:\n            return false;\n         }\n      }\n      else\n         return false;\n   }\n\n   /**\n     * @brief Sets the platform options\n     *\n     * @param[in] options Options as a string in the form of \"keyword:options\"\n     *\n     * @return True if options are pass validation; otherwise false.  If false, the options are not updated.\n     */\n   bool setPlatformOptions(std::string options) {\n      std::string oldOptions = m_PlatformOptions;\n      m_PlatformOptions = options;\n      if (isOptionsValid()) {\n         return true;\n      } else {\n         m_PlatformOptions = oldOptions;\n         return false;\n      }\n   }\n\n   /**\n     * @brief Indicates whther the plaform configuration is valid.\n     *\n     * @return True if the platform configuration is valid; false otherwise.\n     */\n   bool isOptionsValid() const;\n\n   /**\n     * @brief Gets the platform options\n     *\n     * @return Options as a string\n     */\n   std::string getPlatformOptions() const { return m_PlatformOptions; }\n\nprivate:\n   PlatformType_t m_PlatformType;\n   PlatformConfigInfo m_PlatformConfigInfo;\n   std::string m_PlatformOptions;\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}} //namespace end\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/RuntimeList.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2019 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#include \"ZdlExportDefine.hpp\"\n#include \"DlSystem/DlEnums.hpp\"\n#include \"DlSystem/StringList.hpp\"\n#include <cstddef>\n#include <memory>\n\n#ifndef DL_SYSTEM_RUNTIME_LIST_HPP\n#define DL_SYSTEM_RUNTIME_LIST_HPP\n\nnamespace DlSystem\n{\n   // Forward declaration of Runtime List implementation.\n   class RuntimeListImpl;\n}\n\nnamespace zdl\n{\nnamespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n  * @brief .\n  *\n  * A class representing list of runtimes\n  */\nclass ZDL_EXPORT RuntimeList final\n{\npublic:\n\n    /**\n    * @brief .\n    *\n    * Creates a new runtime list\n    *\n    */\n   RuntimeList();\n\n   /**\n   * @brief .\n   *\n   * copy constructor.\n   * @param[in] other object to copy.\n   */\n   RuntimeList(const RuntimeList& other);\n\n   /**\n   * @brief .\n   *\n   * constructor with single Runtime_t object\n   * @param[in] Runtime_t object\n   */\n   RuntimeList(const zdl::DlSystem::Runtime_t& runtime);\n\n   /**\n    * @brief .\n    *\n    * assignment operator.\n    */\n   RuntimeList& operator=(const RuntimeList& other);\n\n   /**\n    * @brief .\n    *\n    * subscript operator.\n    */\n   Runtime_t& operator[](size_t index);\n\n   /**\n    * @brief Adds runtime to the end of the runtime list\n    *        order of precedence is former followed by latter entry\n    *\n    * @param[in] runtime to add\n    *\n    * Ruturns false If the runtime already exists\n    */\n   bool add(const zdl::DlSystem::Runtime_t& runtime);\n\n   /**\n    * @brief Removes the runtime from the list\n    *\n    * @param[in] runtime to be removed\n    *\n    * @note If the runtime is not found, nothing is done.\n    */\n   void remove(const zdl::DlSystem::Runtime_t runtime) noexcept;\n\n   /**\n    * @brief Returns the number of runtimes in the list\n    */\n   size_t size() const noexcept;\n\n   /**\n    * @brief Returns true if the list is empty\n    */\n   bool empty() const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Removes all runtime from the list\n    */\n   void clear() noexcept;\n\n   /**\n    * @brief .\n    *\n    * Returns a StringList of names from the runtime list in\n    * order of precedence\n    */\n   zdl::DlSystem::StringList getRuntimeListNames() const;\n\n   /**\n    * @brief .\n    *\n    * @param[in] runtime string\n    * Returns a Runtime enum corresponding to the in param string\n    *\n    */\n   static zdl::DlSystem::Runtime_t stringToRuntime(const char* runtimeStr);\n\n   /**\n    * @brief .\n    *\n    * @param[in] runtime\n    * Returns a string corresponding to the in param runtime enum\n    *\n    */\n   static const char* runtimeToString(const zdl::DlSystem::Runtime_t runtime);\n\n   ~RuntimeList();\n\nprivate:\n   void deepCopy(const RuntimeList &other);\n   std::unique_ptr<::DlSystem::RuntimeListImpl> m_RuntimeListImpl;\n};\n\n} // DlSystem namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // DL_SYSTEM_RUNTIME_LIST_HPP\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/String.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2017, 2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#ifndef PLATFORM_STANDARD_STRING_HPP\n#define PLATFORM_STANDARD_STRING_HPP\n\n#include <cstdio>\n#include <string>\n#include <ostream>\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl\n{\nnamespace DlSystem\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * Class for wrapping char * as a really stripped down std::string replacement.\n */\nclass ZDL_EXPORT String final\n{\npublic:\n   String() = delete;\n\n   /**\n    * Construct a string from std::string reference.\n    * @param str Reference to a std::string\n    */\n   explicit String(const std::string& str);\n\n   /**\n    * Construct a string from char* reference.\n    * @param a char*\n    */\n   explicit String(const char* str);\n\n   /**\n    * move constructor.\n    */\n   String(String&& other) noexcept;\n\n   /**\n    * copy constructor.\n    */\n   String(const String& other) = delete;\n\n   /**\n    * assignment operator.\n    */\n   String& operator=(const String&) = delete;\n\n   /**\n    * move assignment operator.\n    */\n   String& operator=(String&&) = delete;\n\n   /**\n    * class comparators\n    */\n   bool operator<(const String& rhs) const noexcept;\n   bool operator>(const String& rhs) const noexcept;\n   bool operator<=(const String& rhs) const noexcept;\n   bool operator>=(const String& rhs) const noexcept;\n   bool operator==(const String& rhs) const noexcept;\n   bool operator!=(const String& rhs) const noexcept;\n\n   /**\n    * class comparators against std::string\n    */\n   bool operator<(const std::string& rhs) const noexcept;\n   bool operator>(const std::string& rhs) const noexcept;\n   bool operator<=(const std::string& rhs) const noexcept;\n   bool operator>=(const std::string& rhs) const noexcept;\n   bool operator==(const std::string& rhs) const noexcept;\n   bool operator!=(const std::string& rhs) const noexcept;\n\n   const char* c_str() const noexcept;\n\n   ~String();\nprivate:\n\n   char* m_string;\n};\n\n/**\n * overloaded << operator\n */\nZDL_EXPORT std::ostream& operator<<(std::ostream& os, const String& str) noexcept;\n\n} // DlSystem namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // PLATFORM_STANDARD_STRING_HPP\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/StringList.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2016 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#include <cstdio>\n#include \"ZdlExportDefine.hpp\"\n\n#ifndef DL_SYSTEM_STRINGLIST_HPP\n#define DL_SYSTEM_STRINGLIST_HPP\n\nnamespace zdl\n{\nnamespace DlSystem\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * Class for holding an order list of null-terminated ASCII strings.\n */\nclass ZDL_EXPORT StringList final\n{\npublic:\n   StringList() {}\n\n   /**\n    * Construct a string list with some pre-allocated memory.\n    * @warning Contents of the list will be uninitialized\n    * @param[in] length Number of elements for which to pre-allocate space.\n    */\n   explicit StringList(size_t length);\n\n   /**\n    * Append a string to the list.\n    * @param[in] str Null-terminated ASCII string to append to the list.\n    */\n   void append(const char* str);\n\n   /**\n    * Returns the string at the indicated position,\n    *  or an empty string if the positions is greater than the size\n    *  of the list.\n    * @param[in] idx Position in the list of the desired string\n    */\n   const char* at(size_t idx) const noexcept;\n\n   /**\n    * Pointer to the first string in the list.\n    *  Can be used to iterate through the list.\n    */\n   const char** begin() const noexcept;\n\n   /**\n    * Pointer to one after the last string in the list.\n    *  Can be used to iterate through the list.\n    */\n   const char** end() const noexcept;\n\n   /**\n    * Return the number of valid string pointers held by this list.\n    */\n   size_t size() const noexcept;\n\n\n   /**\n    * assignment operator. \n    */\n   StringList& operator=(const StringList&) noexcept;\n\n   /**\n    * copy constructor.\n    * @param[in] other object to copy.\n    */\n   StringList(const StringList& other);\n\n   /**\n    * move constructor.\n    * @param[in] other object to move.    \n    */\n   StringList(StringList&& other) noexcept;\n\n   ~StringList();\nprivate:\n   void copy(const StringList& other);\n\n   void resize(size_t length);\n\n   void clear();\n\n   static const char* s_Empty;\n   const char** m_Strings = nullptr;\n   const char** m_End = nullptr;\n   size_t       m_Size = 0;\n};\n\n} // DlSystem namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // DL_SYSTEM_STRINGLIST_HPP\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/TensorMap.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2016 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#include <memory>\n#include \"ZdlExportDefine.hpp\"\n#include \"ITensor.hpp\"\n#include \"StringList.hpp\"\n\n#ifndef DL_SYSTEM_TENSOR_MAP_HPP\n#define DL_SYSTEM_TENSOR_MAP_HPP\n\nnamespace DlSystem\n{\n   // Forward declaration of tensor map implementation.\n   class TensorMapImpl;\n}\n\nnamespace zdl\n{\nnamespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n  * @brief .\n  *\n  * A class representing the map of tensor.\n  */\nclass ZDL_EXPORT TensorMap final\n{\npublic:\n\n  /**\n   * @brief .\n   *\n   * Creates a new empty tensor map\n   */\n   TensorMap();\n\n  /**\n   * copy constructor.\n   * @param[in] other object to copy. \n   */\n   TensorMap(const TensorMap& other);\n\n  /**\n    * assignment operator. \n    */\n   TensorMap& operator=(const TensorMap& other);\n\n   /**\n    * @brief Adds a name and the corresponding tensor pointer\n    *        to the map\n    *\n    * @param[in] name The name of the tensor\n    * @param[out] tensor The pointer to the tensor\n    *\n    * @note If a tensor with the same name already exists, the\n    *       tensor is replaced with the existing tensor.\n    */\n   void add(const char *name, zdl::DlSystem::ITensor *tensor);\n\n   /**\n    * @brief Removes a mapping of tensor and its name by its name\n    *\n    * @param[in] name The name of tensor to be removed\n    *\n    * @note If no tensor with the specified name is found, nothing\n    *       is done.\n    */\n   void remove(const char *name) noexcept;\n\n   /**\n    * @brief Returns the number of tensors in the map\n    */\n   size_t size() const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Removes all tensors from the map\n    */\n   void clear() noexcept;\n\n   /**\n    * @brief Returns the tensor given its name.\n    *  \n    * @param[in] name The name of the tensor to get. \n    *  \n    * @return nullptr if no tensor with the specified name is \n    *         found; otherwise, a valid pointer to the tensor.\n    */\n   zdl::DlSystem::ITensor* getTensor(const char *name) const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Returns the names of all tensors\n    */\n   zdl::DlSystem::StringList getTensorNames() const;\n\n   ~TensorMap();\nprivate:\n   void swap(const TensorMap &other);\n   std::unique_ptr<::DlSystem::TensorMapImpl> m_TensorMapImpl;\n};\n\n} // DlSystem namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // DL_SYSTEM_TENSOR_MAP_HPP\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/TensorShape.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2016 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#include <initializer_list>\n#include <cstdio>\n#include <memory>\n#include <vector>\n#include \"ZdlExportDefine.hpp\"\n\n#ifndef DL_SYSTEM_TENSOR_SHAPE_HPP\n#define DL_SYSTEM_TENSOR_SHAPE_HPP\n\nnamespace DlSystem\n{\n   // Forward declaration of tensor shape implementation.\n   class TensorShapeImpl;\n}\n\nnamespace zdl\n{\nnamespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * Convenient typedef to represent dimension\n */\nusing Dimension = size_t;\n\n/**\n  * @brief .\n  *\n  * A class representing the shape of tensor. It is used at the\n  * time of creation of tensor.\n  */\nclass ZDL_EXPORT TensorShape final\n{\npublic:\n\n    /**\n    * @brief .\n    *\n    * Creates a new shape with a list of dims specified in\n    * initializer list fashion.\n    *\n    * @param[in] dims The dimensions are specified in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    *\n    */\n   TensorShape(std::initializer_list<Dimension> dims);\n\n   /**\n    * @brief .\n    *\n    * Creates a new shape with a list of dims specified in array\n    *\n    * @param[in] dims The dimensions are specified in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    *\n    * @param[in] size Size of the array.\n    *\n    */\n   TensorShape(const Dimension *dims, size_t size);\n\n    /**\n    * @brief .\n    *\n    * Creates a new shape with a vector of dims specified in\n    * vector fashion.\n    *\n    * @param[in] dims The dimensions are specified in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    * \n    */   \n   TensorShape(std::vector<Dimension> dims);\n\n   /**\n   * @brief .\n   *   \n   * copy constructor.\n   * @param[in] other object to copy. \n   */   \n   TensorShape(const TensorShape& other);\n\n   /**\n    * @brief .\n    *  \n    * assignment operator. \n    */   \n   TensorShape& operator=(const TensorShape& other);\n\n    /**\n    * @brief .\n    *\n    * Creates a new shape with no dims. It can be extended later\n    * by invoking concatenate.\n    */\n   TensorShape();\n\n  /**\n    * @brief .\n    *\n    * Concatenates additional dimensions specified in \n    * initializer list fashion to the existing dimensions. \n    *\n    * @param[in] dims The dimensions are specified in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    *\n   */\n   void concatenate(std::initializer_list<Dimension> dims);\n\n   /**\n    * @brief .\n    *\n    * Concatenates additional dimensions specified in \n    * the array to the existing dimensions. \n    *\n    * @param[in] dims The dimensions are specified in which the last\n    * element of the vector represents the fastest varying\n    * dimension and the zeroth element represents the slowest\n    * varying, etc.\n    * \n    * @param[in] size Size of the array.\n    *\n   */\n   void concatenate(const Dimension *dims, size_t size);\n\n  /**\n    * @brief .\n    *\n    * Concatenates an additional dimension to the existing\n    * dimensions.\n    *\n    * @param[in] dim The dimensions are specified in which the last element\n    * of the vector represents the fastest varying dimension and the\n    * zeroth element represents the slowest varying, etc.\n    *\n   */\n   void concatenate(const Dimension &dim);\n\n  /**\n    * @brief .\n    *\n    * Retrieves a single dimension, based on its index.\n    *\n    * @return The value of dimension\n    *\n    * @throws std::out_of_range if the index is >= the number of\n    * dimensions (or rank).\n    */\n   Dimension& operator[](size_t index);\n   Dimension& operator[](size_t index) const;\n\n  /**\n    * @brief .\n    *\n    * Retrieves the rank i.e. number of dimensions.\n    *\n    * @return The rank\n    */\n   size_t rank() const;\n\n  /**\n    * @brief .\n    *\n    * Retrieves a pointer to the first dimension of shape\n    *\n    * @return nullptr if no dimension exists; otherwise, points to\n    * the first dimension. \n    *\n    */\n   const Dimension* getDimensions() const;\n\n   ~TensorShape();\n\nprivate:\n   void swap(const TensorShape &other);\n   std::unique_ptr<::DlSystem::TensorShapeImpl> m_TensorShapeImpl;\n};\n\n} // DlSystem namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // DL_SYSTEM_TENSOR_SHAPE_HPP\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/TensorShapeMap.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2017-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#include <initializer_list>\n#include <cstdio>\n#include <memory>\n#include \"ZdlExportDefine.hpp\"\n#include \"DlSystem/TensorShape.hpp\"\n#include \"DlSystem/StringList.hpp\"\n\n#ifndef DL_SYSTEM_TENSOR_SHAPE_MAP_HPP\n#define DL_SYSTEM_TENSOR_SHAPE_MAP_HPP\n\nnamespace DlSystem\n{\n   // Forward declaration of tensor shape map implementation.\n   class TensorShapeMapImpl;\n}\n\nnamespace zdl\n{\nnamespace DlSystem\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n  * @brief .\n  *\n  * A class representing the map of names and tensorshapes.\n  */\nclass ZDL_EXPORT TensorShapeMap final\n{\npublic:\n\n    /**\n    * @brief .\n    *\n    * Creates a new tensor shape map\n    *\n    */\n   TensorShapeMap();\n\n   /**\n   * @brief .\n   *\n   * copy constructor.\n   * @param[in] other object to copy.\n   */\n   TensorShapeMap(const TensorShapeMap& other);\n\n   /**\n    * @brief .\n    *\n    * assignment operator.\n    */\n   TensorShapeMap& operator=(const TensorShapeMap& other);\n\n   /**\n    * @brief Adds a name and the corresponding tensor pointer\n    *        to the map\n    *\n    * @param[in] name The name of the tensor\n    * @param[out] tensor The pointer to the tensor\n    *\n    * @note If a tensor with the same name already exists, no new\n    *       tensor is added.\n    */\n   void add(const char *name, const zdl::DlSystem::TensorShape& tensorShape);\n\n   /**\n    * @brief Removes a mapping of tensor and its name by its name\n    *\n    * @param[in] name The name of tensor to be removed\n    *\n    * @note If no tensor with the specified name is found, nothing\n    *       is done.\n    */\n   void remove(const char *name) noexcept;\n\n   /**\n    * @brief Returns the number of tensors in the map\n    */\n   size_t size() const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Removes all tensors from the map\n    */\n   void clear() noexcept;\n\n   /**\n    * @brief Returns the tensor given its name.\n    *\n    * @param[in] name The name of the tensor to get.\n    *\n    * @return nullptr if no tensor with the specified name is\n    *         found; otherwise, a valid pointer to the tensor.\n    */\n   zdl::DlSystem::TensorShape getTensorShape(const char *name) const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Returns the names of all tensor shapes\n    */\n   zdl::DlSystem::StringList getTensorShapeNames() const;\n\n   ~TensorShapeMap();\nprivate:\n   void swap(const TensorShapeMap &other);\n   std::unique_ptr<::DlSystem::TensorShapeMapImpl> m_TensorShapeMapImpl;\n};\n\n} // DlSystem namespace\n} // zdl namespace\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // DL_SYSTEM_TENSOR_SHAPE_MAP_HPP\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/UDLContext.hpp",
    "content": "//==============================================================================\n//\n// Copyright (c) 2016 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef UDL_CONTEXT_HPP\n#define UDL_CONTEXT_HPP\n\n#include <cstring> // memset\n#include <tuple>\n\n#include \"ZdlExportDefine.hpp\"\n\nnamespace zdl { namespace DlSystem {\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * UDLContext holds the user defined layer context which \n * consists of a layer name, layer ID, blob and blob size. \n *  \n * An instance of UDLContext is passed as an argument to the\n * UDLFactoryFunc provided by the user every time the SNPE \n * runtime encounters an unknown layer descriptor. The instance \n * of a UDLContext is created by the SNPE runtime and is \n * consumed by the user's factory function. The user should \n * obtain a copy of this class and should not assume any \n * prolonged object lifetime beyond the UDLFactoryFunction.\n */\nclass ZDL_EXPORT UDLContext final {\npublic:\n   /**\n    * @brief Constructor\n    *\n    * @param[in] name name of the layer\n    *\n    * @param[in] type layer type\n    *\n    * @param[in] id identifier for the layer\n    *\n    * @param[in] id Blob/bytes as packed by the user code as part of\n    *           the Python converter script\n    */\n   UDLContext(const std::string& name,\n              const std::string& type,\n              int32_t id,\n              const std::string& blob) :\n      m_Name(name), m_Type(type), m_Size(blob.size()), m_Id(id) {\n      // FIXME not dealing with alloc error\n      m_Buffer = new uint8_t[m_Size];\n      std::memcpy(m_Buffer, blob.data(), m_Size);\n   }\n\n   /**\n    * @brief .\n    *\n    * Empty constructor is useful for\n    * creating an empty UDLContext and then run copy constructor\n    * from a fully initialized one.\n    */\n   explicit UDLContext() {}\n\n   /**\n    * @brief .\n    *\n    * destructor Deallocates any internal allocated memory\n    */\n   ~UDLContext() { release(); }\n\n   /**\n    * @brief .\n    *\n    * Deallocate any internally allocated memory\n    */\n   void release() {\n      if (m_Buffer && m_Size)\n         std::memset(m_Buffer, 0, m_Size);\n      delete []m_Buffer;\n      m_Buffer = nullptr;\n      m_Size = 0;\n   }\n\n   /**\n    * @brief .\n    *\n    * Copy Constructor - makes a copy from ctx\n    *\n    * @param[in] ctx Source UDLContext to copy from\n    */\n   UDLContext(const UDLContext& ctx) : m_Name(ctx.m_Name),\n      m_Type(ctx.m_Type),\n      m_Id(ctx.m_Id) {\n      std::tuple<uint8_t*, size_t> cpy = ctx.getCopy();\n      // current compiler does not support get<type>\n      m_Buffer = std::get<0>(cpy);\n      m_Size = std::get<1>(cpy);\n   }\n\n   /**\n    * @brief \n    *\n    * Assignment operator - makes a copy from ctx\n    *\n    * @param[in] ctx Source UDLContext to copy from\n    *\n    * @return this\n    */\n   UDLContext& operator=(const UDLContext& ctx) {\n      UDLContext c (ctx);\n      this->swap(c); // non throwing swap\n      return *this;\n   }\n\n   /**\n    * @brief .\n    *\n    * Move Constructor - Move internals from ctx into this\n    *\n    * @param[in] ctx Source UDLContext to move from\n    */\n   UDLContext(UDLContext&& ctx) :\n      m_Name(std::move(ctx.m_Name)),\n      m_Type(std::move(ctx.m_Type)),\n      m_Buffer(ctx.m_Buffer),\n      m_Size(ctx.m_Size),\n      m_Id(ctx.m_Id) {\n      ctx.clear();\n   }\n\n   /**\n    * @brief .\n    *\n    * Assignment move - Move assignment operator from ctx\n    *\n    * @param[in] ctx Source UDLContext to move from\n    *\n    * @return this\n    */\n   UDLContext& operator=(UDLContext&& ctx) {\n      m_Name = std::move(ctx.m_Name);\n      m_Type = std::move(ctx.m_Type);\n      m_Buffer = ctx.m_Buffer;\n      m_Size = ctx.m_Size;\n      m_Id = ctx.m_Id;\n      ctx.clear();\n      return *this;\n   }\n\n   /**\n    * @brief .\n    *\n    * Obtain the name of the layer\n    *\n    * @return const reference to the name of the layer\n    */\n   const std::string& getName() const noexcept { return m_Name; }\n\n   /**\n    * @brief .\n    *\n    * Obtain the type of the layer\n    *\n    * @return const reference to the type of the layer\n    */\n   const std::string& getType() const noexcept { return m_Type; }\n\n   /**\n    * @brief .\n    *\n    * Obtain the Id of the layer\n    *\n    * @return The id of the layer\n    */\n   int32_t getId() const noexcept  { return m_Id; }\n\n   /**\n    * @brief .\n    *\n    * Obtain the size of the blob\n    *\n    * @return Size of the internal blob\n    */\n   size_t getSize() const noexcept { return m_Size; }\n\n   /**\n    * @brief .\n    *\n    * Get a const pointer to the internal blob\n    *\n    * @return Const pointer to the internal blob\n    */\n   const uint8_t* getBlob() const noexcept { return m_Buffer; }\n\n   /**\n    * @brief .\n    *\n    * Get a copy of the blob/size into a tuple\n    *\n    * @return A tuple with a pointer to a copy of the blob and a\n    *         size\n    */\n   std::tuple<uint8_t*, size_t> getCopy() const {\n      uint8_t* buf = new uint8_t[m_Size];\n      // FIXME missing memcpy\n      std::memcpy(buf, m_Buffer, m_Size);\n      return std::make_tuple(buf, m_Size);\n   }\n\n   /**\n    * @brief .\n    *\n    * Set zeros in the internals members\n    */\n   void clear() {\n      m_Name.clear();\n      m_Type.clear();\n      m_Buffer = 0;\n      m_Size = 0;\n      m_Id = -1;\n   }\nprivate:\n   void swap(UDLContext& c) noexcept {\n      std::swap(m_Name, c.m_Name);\n      std::swap(m_Type, c.m_Type);\n      std::swap(m_Id,   c.m_Id);\n      std::swap(m_Buffer, c.m_Buffer);\n      std::swap(m_Size, c.m_Size);\n   }\n   std::string m_Name; // name of the layer instance\n   std::string m_Type; // The actual layer type\n   uint8_t*    m_Buffer = nullptr;\n   size_t      m_Size = 0;\n   int32_t     m_Id = -1;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}}\n\n#endif /* UDL_CONTEXT_HPP */\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/UDLFunc.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2015 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _UDL_FUNC_HPP_\n#define _UDL_FUNC_HPP_\n\n#include <functional>\n\n#include \"ZdlExportDefine.hpp\"\n#include <DlSystem/IUDL.hpp>\n\nnamespace zdl {\n    namespace DlSystem {\n        class UDLContext;\n    }\n}\n\nnamespace zdl { namespace DlSystem {\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n/**\n * @brief .\n *\n * Definition of UDLFactoyFunc, using/typedef and default FactoryFunction\n * UDLBundle - a simple way to bundle func and cookie into one type\n */\n\n\n/**\n * @brief .\n * \n * Convenient typedef for user defined layer creation factory\n *\n * @param[out] void* Cookie - a user opaque data that was passed during SNPE's runtime's\n *        CreateInstance. SNPE's runtime is passing this back to the user.\n *\n * @param[out] DlSystem::UDLContext* - The specific Layer Description context what is passe\n *        SNPE runtime.\n *\n * @return IUDL* - a Concrete instance of IUDL derivative\n */\nusing UDLFactoryFunc = std::function<zdl::DlSystem::IUDL* (void*, const zdl::DlSystem::UDLContext*)>;\n\n/**\n * @brief .\n *\n * default UDL factory implementation\n *\n * @param[out] DlSystem::UDLContext* - The specific Layer Description context what is passe\n *        SNPE runtime.\n *\n * @param[out] void* Cookie - a user opaque data that was passed during SNPE's runtime's\n *        CreateInstance. SNPE's runtime is passing this back to the user.\n * \n * @return IUDL* - nullptr to indicate SNPE's runtime that there is no specific\n *         implementation for UDL. When SNPE's runtime sees nullptr as a return\n *         value from the factory, it will halt execution if model has an unknown layer\n *\n */\ninline ZDL_EXPORT zdl::DlSystem::IUDL* DefaultUDLFunc(void*, const zdl::DlSystem::UDLContext*) { return nullptr; }\n\n/**\n * @brief .\n * \n * Simple struct to bundle 2 elements.\n * A user defined cookie that would be returned for each\n * IUDL call. The user can place anything there and the\n * SNPE runtime will provide it back\n */\nstruct ZDL_EXPORT UDLBundle {\n   void          *cookie = nullptr;\n   UDLFactoryFunc func   = DefaultUDLFunc;\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n}}\n\n\n#endif // _UDL_FUNC_HPP_\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/UserBufferMap.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2017 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n#include <memory>\n#include \"ZdlExportDefine.hpp\"\n#include \"StringList.hpp\"\n\n#ifndef DL_SYSTEM_USER_BUFFER_MAP_HPP\n#define DL_SYSTEM_USER_BUFFER_MAP_HPP\n\nnamespace DlSystem\n{\n    // Forward declaration of UserBuffer map implementation.\n    class UserBufferMapImpl;\n}\n\nnamespace zdl\n{\nnamespace DlSystem\n{\nclass IUserBuffer;\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n  * @brief .\n  *\n  * A class representing the map of UserBuffer.\n  */\nclass ZDL_EXPORT UserBufferMap final\n{\npublic:\n\n    /**\n     * @brief .\n     *\n     * Creates a new empty UserBuffer map\n     */\n    UserBufferMap();\n\n    /**\n     * copy constructor.\n     * @param[in] other object to copy.\n     */\n    UserBufferMap(const UserBufferMap& other);\n\n    /**\n      * assignment operator.\n      */\n    UserBufferMap& operator=(const UserBufferMap& other);\n\n    /**\n     * @brief Adds a name and the corresponding UserBuffer pointer\n     *        to the map\n     *\n     * @param[in] name The name of the UserBuffer\n     * @param[in] userBuffer The pointer to the UserBuffer\n     *\n     * @note If a UserBuffer with the same name already exists, the new\n     *       UserBuffer pointer would be updated.\n     */\n    void add(const char *name, zdl::DlSystem::IUserBuffer *buffer);\n\n    /**\n     * @brief Removes a mapping of one UserBuffer and its name by its name\n     *\n     * @param[in] name The name of UserBuffer to be removed\n     *\n     * @note If no UserBuffer with the specified name is found, nothing\n     *       is done.\n     */\n    void remove(const char *name) noexcept;\n\n    /**\n     * @brief Returns the number of UserBuffers in the map\n     */\n    size_t size() const noexcept;\n\n    /**\n     * @brief .\n     *\n     * Removes all UserBuffers from the map\n     */\n    void clear() noexcept;\n\n    /**\n     * @brief Returns the UserBuffer given its name.\n     *\n     * @param[in] name The name of the UserBuffer to get.\n     *\n     * @return nullptr if no UserBuffer with the specified name is\n     *         found; otherwise, a valid pointer to the UserBuffer.\n     */\n    zdl::DlSystem::IUserBuffer* getUserBuffer(const char *name) const noexcept;\n\n    /**\n     * @brief .\n     *\n     * Returns the names of all UserBuffers\n     *\n     * @return A list of UserBuffer names.\n     */\n    zdl::DlSystem::StringList getUserBufferNames() const;\n\n    ~UserBufferMap();\nprivate:\n    void swap(const UserBufferMap &other);\n    std::unique_ptr<::DlSystem::UserBufferMapImpl> m_UserBufferMapImpl;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n} // DlSystem namespace\n} // zdl namespace\n\n\n#endif // DL_SYSTEM_TENSOR_MAP_HPP\n\n"
  },
  {
    "path": "phonelibs/snpe/include/DlSystem/ZdlExportDefine.hpp",
    "content": "//=============================================================================\n//\n//  Copyright (c) 2015, 2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//=============================================================================\n\n#pragma once\n\n#ifndef ZDL_EXPORT\n#define ZDL_EXPORT\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/PlatformValidator/PlatformValidator.hpp",
    "content": "// =============================================================================\n//\n// Copyright (c) 2018-2019 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n// =============================================================================\n\n#ifndef SNPE_PLATFORMVALIDATOR_HPP\n#define SNPE_PLATFORMVALIDATOR_HPP\n\n#include \"DlSystem/DlEnums.hpp\"\n#include \"DlSystem/DlMacros.hpp\"\nSNPE_DISABLE_WARNINGS(\"-Wdelete-non-virtual-dtor\",\"-Wdelete-non-virtual-dtor\")\n#include <string>\n#include <memory>\nSNPE_ENABLE_WARNINGS\n\nnamespace zdl\n{\n   namespace SNPE\n   {\n      class PlatformValidator;\n\n      class IPlatformValidatorRuntime;\n   }\n}\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n* The class for checking SNPE compatibility/capability of a device.\n*\n*/\n\nclass zdl::SNPE::PlatformValidator\n{\npublic:\n   /**\n    * @brief Default Constructor of the PlatformValidator Class\n    *\n    * @return A new instance of a PlatformValidator object\n    *         that can be used to check the SNPE compatibility\n    *         of a device\n    */\n   PlatformValidator();\n\n   ~PlatformValidator();\n\n   /**\n    * @brief Sets the runtime processor for compatibility check\n    *\n    * @return Void\n    */\n   void setRuntime(zdl::DlSystem::Runtime_t runtime);\n\n   /**\n    * @brief Checks if the Runtime prerequisites for SNPE are available.\n    *\n    * @return True if the Runtime prerequisites are available, else false.\n    */\n   bool isRuntimeAvailable();\n\n   /**\n    * @brief Returns the core version for the Runtime selected.\n    *\n    * @return String which contains the actual core version value\n    */\n   std::string getCoreVersion();\n\n   /**\n    * @brief Returns the library version for the Runtime selected.\n    *\n    * @return String which contains the actual lib version value\n    */\n   std::string getLibVersion();\n\n   /**\n    * @brief Runs a small program on the runtime and Checks if SNPE is supported for Runtime.\n    *\n    * @return If True, the device is ready for SNPE execution, else not.\n    */\n\n   bool runtimeCheck();\n\nprivate:\n    zdl::DlSystem::Runtime_t m_runtimeType;\n    std::unique_ptr<IPlatformValidatorRuntime> m_platformValidatorRuntime;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif //SNPE_PLATFORMVALIDATOR_HPP\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/ApplicationBufferMap.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2019 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef PSNPE_APPLICATIONBUFFERMAP_HPP\n#define PSNPE_APPLICATIONBUFFERMAP_HPP\n#include <vector>\n#include <string>\n#include <unordered_map>\n\n#include \"DlSystem/UserBufferMap.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl\n{\nnamespace PSNPE\n{\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * A class representing the UserBufferMap of Input and Output asynchronous mode.\n */\n\nclass ZDL_EXPORT ApplicationBufferMap final\n{\n\n public:\n   /**\n    * @brief Adds a name and the corresponding buffer\n    *        to the map\n    *\n    * @param[in] name The name of the UserBuffer\n    * @param[in] buffer The vector of the uint8_t data\n    *\n    * @note If a UserBuffer with the same name already exists, the new\n    *       UserBuffer pointer would be updated.\n    */\n   void add(const char* name, std::vector<uint8_t>& buff) noexcept;\n   void add(const char* name, std::vector<float>& buff) noexcept;\n   /**\n    * @brief Removes a mapping of one UserBuffer and its name by its name\n    *\n    * @param[in] name The name of UserBuffer to be removed\n    *\n    * @note If no UserBuffer with the specified name is found, nothing\n    *       is done.\n    */\n   void remove(const char* name) noexcept;\n\n   /**\n    * @brief Returns the number of UserBuffers in the map\n    */\n   size_t size() const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Removes all UserBuffers from the map\n    */\n   void clear() noexcept;\n\n   /**\n    * @brief Returns the UserBuffer given its name.\n    *\n    * @param[in] name The name of the UserBuffer to get.\n    *\n    * @return nullptr if no UserBuffer with the specified name is\n    *         found; otherwise, a valid pointer to the UserBuffer.\n    */\n   const std::vector<uint8_t>& getUserBuffer(const char* name) const;\n   const std::vector<uint8_t>& operator[](const char* name) const;\n   /**\n    * @brief .\n    *\n    * Returns the names of all UserAsyncBufferMap\n    *\n    * @return A list of UserBuffer names.\n    */\n   zdl::DlSystem::StringList getUserBufferNames() const;\n   const std::unordered_map<std::string, std::vector<uint8_t>>& getUserBuffer() const;\n   explicit ApplicationBufferMap();\n   ~ApplicationBufferMap();\n   explicit ApplicationBufferMap(\n     const std::unordered_map<std::string, std::vector<uint8_t>> buffer);\n\n private:\n   std::unordered_map<std::string, std::vector<uint8_t>> m_UserMap;\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n} // namespace PSNPE\n} // namespace zdl\n\n#endif // PSNPE_APPLICATIONBUFFERMAP_HPP\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/PSNPE.hpp",
    "content": "// =============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n// =============================================================================\n\n#ifndef PSNPE_HPP\n#define PSNPE_HPP\n\n#include <cstdlib>\n#include <functional>\n#include \"SNPE/SNPE.hpp\"\n#include \"DlSystem/UserBufferMap.hpp\"\n#include \"DlContainer/IDlContainer.hpp\"\n#include \"DlSystem/DlEnums.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\n#include \"UserBufferList.hpp\"\n#include \"RuntimeConfigList.hpp\"\n#include \"ApplicationBufferMap.hpp\"\n\nnamespace zdl\n{\nnamespace PSNPE\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n *@ brief build snpe instance in serial or parallel\n *\n */\nenum ZDL_EXPORT BuildMode {\n   SERIAL = 0,\n   PARALLEL = 1\n};\n/**\n * @brief  Input and output transmission mode\n */\nenum ZDL_EXPORT InputOutputTransmissionMode\n{\n   sync = 0,\n   outputAsync = 1,\n   inputOutputAsync = 2\n};\n\n/**\n * @brief  A structure representing parameters of callback function of Async Output mode\n */\nstruct ZDL_EXPORT OutputAsyncCallbackParam\n{\n   size_t dataIndex;\n   bool executeStatus;\n   OutputAsyncCallbackParam(size_t _index,bool _status)\n     : dataIndex(_index),executeStatus(_status){};\n};\n/**\n * @brief  A structure representing parameters of callback function of Async Input/Output mode\n */\nstruct ZDL_EXPORT InputOutputAsyncCallbackParam\n{\n   size_t dataIndex;\n   const ApplicationBufferMap& outputMap;\n   bool executeStatus;\n   InputOutputAsyncCallbackParam(size_t _index, const ApplicationBufferMap& output_map,bool _status)\n     : dataIndex(_index)\n     , outputMap(output_map)\n     ,executeStatus(_status){\n\n     };\n};\n/**\n * @brief  This callback is called when the output data is ready, only use for Output Async mode\n */\nusing OutputAsyncCallbackFunc = std::function<void(OutputAsyncCallbackParam)>;\n/**\n * @brief  This callback is called when the output data is ready, only use for Output-Input Async mode\n */\nusing InputOutputAsyncCallbackFunc = std::function<void(InputOutputAsyncCallbackParam)>;\n/**\n * @brief   This callback is called when the input data is ready,only use for Output-Input Async mode \n */\nusing InputOutputAsyncInputCallback = std::function<std::shared_ptr<ApplicationBufferMap>(const std::vector<std::string> &,\n    const zdl::DlSystem::StringList &)>;\n/**\n * @brief .\n *\n * A structure PSNPE configuration\n *\n */\nstruct ZDL_EXPORT BuildConfig final\n{\n   BuildMode buildMode = BuildMode::SERIAL; ///< Specify build in serial mode or parallel mode\n   zdl::DlContainer::IDlContainer* container;///< The opened container ptr\n   zdl::DlSystem::StringList outputBufferNames;///< Specify the output layer name\n   RuntimeConfigList runtimeConfigList;///< The runtime config list for PSNPE, @see RuntimeConfig\n   size_t inputThreadNumbers = 1;///< Specify the number of threads used in the execution phase to process input data, only used in inputOutputAsync mode\n   size_t outputThreadNumbers = 1;///< Specify the number of threads used in the execution phase to process output data, only used in inputOutputAsync and outputAsync mode\n   OutputAsyncCallbackFunc outputCallback;///< The callback to deal with output data ,only used in outputAsync mode\n   InputOutputAsyncCallbackFunc inputOutputCallback;///< The callback to deal with output data ,only used in inputOutputAsync mode\n   InputOutputAsyncInputCallback inputOutputInputCallback;///< The callback to deal with input data ,only used in inputOutputAsync mode\n   InputOutputTransmissionMode inputOutputTransmissionMode = InputOutputTransmissionMode::sync;///< Specify execution mode\n   zdl::DlSystem::ProfilingLevel_t profilingLevel = zdl::DlSystem::ProfilingLevel_t::OFF;///< Specify profiling level for Diaglog\n   uint64_t encode[2] = {0, 0};\n   bool enableInitCache = false;\n};\n/**\n * @brief .\n *\n * The class for executing SNPE instances in parallel.\n */\nclass ZDL_EXPORT PSNPE final\n{\n public:\n   ~PSNPE();\n\n   explicit PSNPE() noexcept :m_TransmissionMode(InputOutputTransmissionMode::sync){};\n\n   /**\n    * @brief Build snpe instances.\n    *\n    */\n   bool build(BuildConfig& buildConfig) noexcept;\n\n   /**\n    * @brief Execute snpe instances in Async Output mode and Sync mode\n    *\n    * @param[in] inputBufferList A list of user buffers that contains the input data\n    *\n    * @param[in,out] outputBufferList A list of user buffers that will hold the output data\n    *\n    */\n   bool execute(UserBufferList& inputBufferList, UserBufferList& outputBufferList) noexcept;\n\n   /**\n    * @brief  Execute snpe instances in Async Input/Output mode\n    *\n    * @param[in]inputMap A map of input buffers that contains input data. The names of buffers\n    *                     need to be matched with names retrived through getInputTensorNames()\n    *\n    * @param dataIndex Index of the input data\n    *\n    * @param isTF8buff Whether prefer to using 8 bit quantized element for inference\n    *\n    * @return True if executed successfully; flase, otherwise.\n    */\n   bool executeInputOutputAsync(const std::vector<std::string>& inputMap, size_t dataIndex, bool isTF8buff) noexcept;\n   bool executeInputOutputAsync(const std::vector<std::string>& inputMap, size_t dataIndex, bool isTF8buff,bool isTF8Outputbuff) noexcept;\n   /**\n    * @brief Returns the input layer names of the network.\n    *\n    * @return StringList which contains the input layer names\n    */\n   const zdl::DlSystem::StringList getInputTensorNames() const noexcept;\n\n   /**\n    * @brief Returns the output layer names of the network.\n    *\n    * @return StringList which contains the output layer names\n    */\n   const zdl::DlSystem::StringList getOutputTensorNames() const noexcept;\n\n   /**\n    * @brief Returns the input tensor dimensions of the network.\n    *\n    * @return TensorShape which contains the dimensions.\n    */\n   const zdl::DlSystem::TensorShape getInputDimensions() const noexcept;\n\n   /**\n    * @brief Returns attributes of buffers.\n    *\n    * @see zdl::SNPE\n    *\n    * @return BufferAttributes of input/output tensor named.\n    */\n   const zdl::DlSystem::TensorShape getBufferAttributesDims(const char *name) const noexcept;\n\n   zdl::DlSystem::Optional<zdl::DlSystem::IBufferAttributes*> getInputOutputBufferAttributes(const char *name) const noexcept;\n\n private:\n   PSNPE(const PSNPE&) = delete;\n   PSNPE& operator=(const PSNPE&) = delete;\n   zdl::PSNPE::InputOutputTransmissionMode m_TransmissionMode;\n\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n} // namespace PSNPE\n} // namespace zdl\n#endif // PSNPE_HPP\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/RuntimeConfigList.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n#ifndef PSNPE_RUNTIMECONFIGLIST_HPP\n#define PSNPE_RUNTIMECONFIGLIST_HPP\n\n#include <iostream>\n#include \"DlContainer/IDlContainer.hpp\"\n#include \"DlSystem/DlEnums.hpp\"\n#include \"DlSystem/RuntimeList.hpp\"\n#include \"DlSystem/TensorShapeMap.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\nnamespace zdl {\nnamespace PSNPE {\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * The structure for configuring a BulkSNPE runtime\n *\n */\nstruct ZDL_EXPORT RuntimeConfig final {\n    zdl::DlSystem::Runtime_t runtime;\n    zdl::DlSystem::RuntimeList runtimeList;\n    zdl::DlSystem::PerformanceProfile_t perfProfile;\n    zdl::DlSystem::TensorShapeMap inputDimensionsMap;\n    bool enableCPUFallback;\n    RuntimeConfig()\n        : runtime{zdl::DlSystem::Runtime_t::CPU_FLOAT32},\n          perfProfile{zdl::DlSystem::PerformanceProfile_t::HIGH_PERFORMANCE},\n          enableCPUFallback{false} {}\n    RuntimeConfig(const RuntimeConfig& other) {\n        runtime = other.runtime;\n        runtimeList = other.runtimeList;\n        perfProfile = other.perfProfile;\n        enableCPUFallback = other.enableCPUFallback;\n        inputDimensionsMap = other.inputDimensionsMap;\n    }\n\n    RuntimeConfig& operator=(const RuntimeConfig& other) {\n        this->runtimeList = other.runtimeList;\n        this->runtime = other.runtime;\n        this->perfProfile = other.perfProfile;\n        this->enableCPUFallback = other.enableCPUFallback;\n        this->inputDimensionsMap = other.inputDimensionsMap;\n        return *this;\n    }\n\n    ~RuntimeConfig() {}\n};\n\n/**\n * @brief .\n *\n * The class for creating a RuntimeConfig container.\n *\n */\nclass ZDL_EXPORT RuntimeConfigList final {\n   public:\n    RuntimeConfigList();\n    RuntimeConfigList(const size_t size);\n    void push_back(const RuntimeConfig& runtimeConfig);\n    RuntimeConfig& operator[](const size_t index);\n    RuntimeConfigList& operator=(const RuntimeConfigList& other);\n    size_t size() const noexcept;\n    size_t capacity() const noexcept;\n    void clear() noexcept;\n    ~RuntimeConfigList() = default;\n\n   private:\n    void swap(const RuntimeConfigList& other);\n    std::vector<RuntimeConfig> m_runtimeConfigs;\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}  // namespace PSNPE\n}  // namespace zdl\n#endif  // PSNPE_RUNTIMECONFIGLIST_HPP\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/SNPE.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2015-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _SNPE_SNPE_HPP_\n#define _SNPE_SNPE_HPP_\n\n#include \"DlSystem/DlOptional.hpp\"\n#include \"DlSystem/DlVersion.hpp\"\n#include \"DlSystem/IBufferAttributes.hpp\"\n#include \"DlSystem/ITensor.hpp\"\n#include \"DlSystem/TensorShape.hpp\"\n#include \"DlSystem/TensorMap.hpp\"\n#include \"DlSystem/String.hpp\"\n#include \"DlSystem/StringList.hpp\"\n#include \"DlSystem/IUserBuffer.hpp\"\n#include \"DlSystem/UserBufferMap.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl {\n   namespace SNPE\n   {\n      class SnpeRuntime;\n   }\n}\nnamespace zdl {\n   namespace DiagLog\n   {\n      class IDiagLog;\n   }\n}\n\nnamespace zdl { namespace SNPE {\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief .\n *\n * The SNPE interface class definition\n */\nclass ZDL_EXPORT SNPE final\n{\npublic:\n\n   // keep this undocumented to be hidden in doxygen using HIDE_UNDOC_MEMBERS\n   explicit SNPE(std::unique_ptr<zdl::SNPE::SnpeRuntime>&& runtime) noexcept;\n   ~SNPE();\n\n   /**\n    * @brief Gets the names of input tensors to the network\n    *\n    * To support multiple input scenarios, where multiple tensors are\n    * passed through execute() in a TensorMap, each tensor needs to\n    * be uniquely named. The names of tensors can be retrieved\n    * through this function.\n    *\n    * In the case of a single input, one name will be returned.\n    *\n    * @note Note that because the returned value is an Optional list,\n    * the list must be verified as boolean true value before being\n    * dereferenced.\n    *\n    * @return An Optional List of input tensor names.\n    *\n    * @see zdl::DlSystem::Optional\n    */\n   zdl::DlSystem::Optional<zdl::DlSystem::StringList>\n      getInputTensorNames() const noexcept;\n\n    /**\n     * @brief Gets the names of output tensors to the network\n     *\n     * @return List of output tensor names.\n     */\n   zdl::DlSystem::Optional<zdl::DlSystem::StringList>\n      getOutputTensorNames() const noexcept;\n\n   /**\n    * @brief Gets the name of output tensor from the input layer name\n    *\n    * @return Output tensor name.\n    */\n   zdl::DlSystem::StringList\n      getOutputTensorNamesByLayerName(const char *name) const noexcept;\n\n   /**\n    * @brief Processes the input data and returns the output\n    *\n    * @param[in] A map of tensors that contains the input data for\n    *            each input. The names of tensors needs to be\n    *            matched with names retrieved through\n    *            getInputTensorNames()\n    *\n    * @param[in,out] An empty map of tensors that will contain the output\n    *                data of potentially multiple layers (the key\n    *                in the map is the layer name) upon return\n    *\n    * @note output tensormap has to be empty.  To forward propagate\n    *       and get results in user-supplied tensors, use\n    *       executeWithSuppliedOutputTensors.\n    */\n   bool execute(const zdl::DlSystem::TensorMap &input,\n                zdl::DlSystem::TensorMap &output) noexcept;\n\n   /**\n    * @brief Processes the input data and returns the output\n    *\n    * @param[in] A single tensor contains the input data.\n    *\n    * @param[in,out] An empty map of tensors that will contain the output\n    *                data of potentially multiple layers (the key\n    *                in the map is the layer name) upon return\n    *\n    * @note output tensormap has to be empty.\n    */\n   bool execute(const zdl::DlSystem::ITensor *input,\n                zdl::DlSystem::TensorMap &output) noexcept;\n\n   /**\n    * @brief Processes the input data and returns the output, using\n    *        user-supplied buffers\n    *\n    * @param[in] A map of UserBuffers that contains the input data for\n    *            each input. The names of UserBuffers needs to be\n    *            matched with names retrieved through\n    *            getInputTensorNames()\n    *\n    * @param[in,out] A map of UserBuffers that will hold the output\n    *                data of potentially multiple layers (the key\n    *                in the map is the UserBuffer name)\n    *\n    * @note input and output UserBuffer maps must be fully pre-populated. with\n    *       dimensions matching what the network expects.\n    *       For example, if there are 5 output UserBuffers they all have to be\n    *       present in map.\n    *\n    *       Caller must guarantee that for the duration of execute(), the buffer\n    *       stored in UserBuffer would remain valid.  For more detail on buffer\n    *       ownership and lifetime requirements, please refer to zdl::DlSystem::UserBuffer\n    *       documentation.\n    */\n   bool execute(const zdl::DlSystem::UserBufferMap &input,\n                const zdl::DlSystem::UserBufferMap &output) noexcept;\n\n    /**\n    * @brief Returns the version string embedded at model conversion\n    * time.\n    *\n    * @return Model version string, which is a free-form string\n    *         supplied at the time of the conversion\n    *\n    */\n   zdl::DlSystem::String getModelVersion() const noexcept;\n\n   /**\n    * @brief Returns the dimensions of the input data to the model in the\n    * form of TensorShape. The dimensions in TensorShape corresponds to\n    * what the tensor dimensions would need to be for an input tensor to\n    * the model.\n    *\n    * @param[in] layer input name.\n    *\n    * @note Note that this function only makes sense for networks \n    *       that have a fixed input size. For networks in which the\n    *       input size varies with each call of Execute(), this\n    *       function should not be used.\n    *\n    * @note Because the returned type is an Optional instance, it must\n    *       be verified as a boolean true value before being dereferenced.\n    * \n    * @return An Optional instance of TensorShape that maintains dimensions,\n    *         matching the tensor dimensions for input to the model,\n    *         where the last entry is the fastest varying dimension, etc.\n    *  \n    * @see zdl::DlSystem::ITensor\n    * @see zdl::DlSystem::TensorShape\n    * @see zdl::DlSystem::Optional\n    */\n   zdl::DlSystem::Optional<zdl::DlSystem::TensorShape>\n      getInputDimensions() const noexcept;\n   zdl::DlSystem::Optional<zdl::DlSystem::TensorShape>\n      getInputDimensions(const char *name) const noexcept;\n\n   /**\n    * @brief Gets the output layer(s) for the network. \n    *  \n    * Note that the output layers returned by this function may be \n    * different than those specified when the network was created \n    * via the zdl::SNPE::SNPEBuilder. For example, if the\n    * network was created in debug mode with no explicit output \n    * layers specified, this will contain all layers.\n    *\n    * @note Note that because the returned value is an Optional StringList,\n    * the list must be verified as a boolean true value before being\n    * dereferenced.\n    *\n    * @return A List of output layer names.\n    *\n    * @see zdl::DlSystem::Optional\n    */\n   zdl::DlSystem::Optional<zdl::DlSystem::StringList>\n      getOutputLayerNames() const noexcept;\n\n   /**\n     * @brief Returns attributes of buffers used to feed input tensors and receive result from output tensors.\n     *\n     * @param[in] Tensor name.\n     *\n     * @return BufferAttributes of input/output tensor named\n     */\n   zdl::DlSystem::Optional<zdl::DlSystem::IBufferAttributes*> getInputOutputBufferAttributes(const char *name) const noexcept;\n\n   zdl::DlSystem::Optional<zdl::DlSystem::IBufferAttributes*> getInputOutputBufferAttributesTf8(const char *name) const noexcept;\n\n   /**\n    * @brief .\n    *\n    * Get the diagnostic logging interface\n    *\n    * @note Note that because the returned type is an Optional instance,\n    * it must be verified as a boolean true value before being\n    * dereferenced.\n    *\n    * @see zdl::DlSystem::Optional\n    */\n   zdl::DlSystem::Optional<zdl::DiagLog::IDiagLog*>\n      getDiagLogInterface() noexcept;\n\nprivate:\n   SNPE(const SNPE&) = delete;\n   SNPE& operator=(const SNPE&) = delete;\n\n   std::unique_ptr<SnpeRuntime> m_Runtime;\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n}}\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/SNPEBuilder.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2017-2019 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _SNPE_BUILDER_HPP_\n#define _SNPE_BUILDER_HPP_\n\n#include \"SNPE/SNPE.hpp\"\n#include \"DlSystem/DlEnums.hpp\"\n#include \"DlSystem/UDLFunc.hpp\"\n#include \"DlSystem/DlOptional.hpp\"\n#include \"DlSystem/TensorShapeMap.hpp\"\n#include \"DlSystem/PlatformConfig.hpp\"\n#include \"DlSystem/RuntimeList.hpp\"\n\nnamespace zdl {\n   namespace DlContainer\n   {\n      class IDlContainer;\n   }\n}\n\nstruct SNPEBuilderImpl;\n\n\nnamespace zdl { namespace SNPE {\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * The builder class for creating SNPE objects.\n * Not meant to be extended.\n */\nclass ZDL_EXPORT SNPEBuilder final\n{\nprivate:\n   std::unique_ptr<::SNPEBuilderImpl> m_Impl;\npublic:\n\n   /**\n    * @brief Constructor of NeuralNetwork Builder with a supplied model.\n    *\n    * @param[in] container A container holding the model.\n    *\n    * @return A new instance of a SNPEBuilder object\n    *         that can be used to configure and build\n    *         an instance of SNPE.\n    *\n    */\n   explicit SNPEBuilder(\n      zdl::DlContainer::IDlContainer* container);\n   ~SNPEBuilder();\n\n   /**\n    * NOTE: DEPRECATED, MAY BE REMOVED IN THE FUTURE. Please use\n    *       setRuntimeProcessorOrder()\n    *\n    * @brief Sets the runtime processor.\n    *\n    * @param[in] targetRuntimeProcessor The target runtime.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setRuntimeProcessor(\n      zdl::DlSystem::Runtime_t targetRuntimeProcessor);\n\n   /**\n    * @brief Requests a performance profile.\n    *\n    * @param[in] targetRuntimeProfile The target performance profile.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setPerformanceProfile(\n      zdl::DlSystem::PerformanceProfile_t performanceProfile);\n\n   /**\n    * @brief Sets the profiling level. Default profiling level for\n    *        SNPEBuilder is off. Off and basic only applies to DSP runtime.\n    *\n    * @param[in] profilingLevel The target profiling level.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setProfilingLevel(\n      zdl::DlSystem::ProfilingLevel_t profilingLevel);\n\n    /**\n     * @brief Sets a preference for execution priority.\n     *\n     * This allows the caller to give coarse hint to SNPE runtime\n     * about the priority of the network.  SNPE runtime is free to use\n     * this information to co-ordinate between different workloads\n     * that may or may not extend beyond SNPE.\n     *\n     * @param[in] ExecutionPriorityHint_t The target performance profile.\n     *\n     * @return The current instance of SNPEBuilder.\n     */\n   SNPEBuilder& setExecutionPriorityHint(\n            zdl::DlSystem::ExecutionPriorityHint_t priority);\n\n    /**\n    * @brief Sets the layers that will generate output.\n    *\n    * @param[in] outputLayerNames List of layer names to\n    *                             output. An empty list will\n    *                             result in only the final\n    *                             layer of the model being\n    *                             the output layer.  The list\n    *                             will be copied.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setOutputLayers(\n      const zdl::DlSystem::StringList& outputLayerNames);\n\n   /**\n   * @brief Sets the output tensor names.\n   *\n   * @param[in] outputTensorNames List of tensor names to\n   *                             output. An empty list will\n   *                             result in producing output for the final\n   *                             output tensor of the model.\n   *                             The list will be copied.\n   *\n   * @return The current instance of SNPEBuilder.\n   */\n   SNPEBuilder& setOutputTensors(\n      const zdl::DlSystem::StringList& outputTensorNames);\n\n   /**\n    * @brief Passes in a User-defined layer.\n    *\n    * @param udlBundle Bundle of udl factory function and a cookie\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setUdlBundle(\n      zdl::DlSystem::UDLBundle udlBundle);\n\n   /**\n    * @brief Sets whether this neural network will perform inference with\n    *        input from user-supplied buffers, and write output to user-supplied\n    *        buffers.  Default behaviour is to use tensors created by\n    *        ITensorFactory.\n    *\n    * @param[in] bufferMode Whether to use user-supplied buffer or not.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setUseUserSuppliedBuffers(\n      bool bufferMode);\n\n    /**\n    * @brief Sets the debug mode of the runtime.\n    *\n    * @param[in] debugMode This enables debug mode for the runtime. It\n    *                      does two things. For an empty\n    *                      outputLayerNames list, all layers will be\n    *                      output. It might also disable some internal\n    *                      runtime optimizations (e.g., some networks\n    *                      might be optimized by combining layers,\n    *                      etc.).\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setDebugMode(\n      bool debugMode);\n\n   /**\n    * NOTE: DEPRECATED, MAY BE REMOVED IN THE FUTURE. Please use\n    *       setRuntimeProcessorOrder()\n    *\n    * @brief Sets the mode of CPU fallback functionality.\n    *\n    * @param[in] mode   This flag enables/disables the functionality\n    *                   of CPU fallback. When the CPU fallback\n    *                   functionality is enabled, layers in model that\n    *                   violates runtime constraints will run on CPU\n    *                   while the rest of non-violating layers will\n    *                   run on the chosen runtime processor. In\n    *                   disabled mode, models with layers violating\n    *                   runtime constraints will NOT run on the chosen\n    *                   runtime processor and will result in runtime\n    *                   exception. By default, the functionality is\n    *                   enabled.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setCPUFallbackMode(\n      bool mode);\n\n\n   /**\n    * @brief Sets network's input dimensions to enable resizing of\n    *        the spatial dimensions of each layer for fully convolutional networks,\n    *        and the batch dimension for all networks.\n    *\n    * @param[in] tensorShapeMap The map of input names and their new dimensions.\n    *                           The new dimensions overwrite the input dimensions\n    *                           embedded in the model and then resize each layer\n    *                           of the model. If the model contains\n    *                           layers whose dimensions cannot be resized e.g FullyConnected,\n    *                           exception will be thrown when SNPE instance is actually built.\n    *                           In general the batch dimension is always resizable.\n    *                           After resizing of layers' dimensions in model based\n    *                           on new input dimensions, the new model is revalidated\n    *                           against all runtime constraints, whose failures may\n    *                           result in cpu fallback situation.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setInputDimensions(const zdl::DlSystem::TensorShapeMap& inputDimensionsMap);\n\n   /**\n    * @brief Sets the mode of init caching functionality.\n    *\n    * @param[in] mode   This flag enables/disables the functionality of init caching.\n    *                   When init caching functionality is enabled, a set of init caches\n    *                   will be created during network building/initialization process\n    *                   and will be added to DLC container. If such DLC container is saved\n    *                   by the user, in subsequent network building/initialization processes\n    *                   these init caches will be loaded from the DLC so as to reduce initialization time.\n    *                   In disable mode, no init caches will be added to DLC container.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setInitCacheMode(\n      bool cacheMode);\n\n   /**\n    * @brief Returns an instance of SNPE based on the current parameters.\n    *\n    * @return A new instance of a SNPE object that can be used\n    *         to execute models or null if any errors occur.\n    */\n   std::unique_ptr<SNPE> build() noexcept;\n\n   /**\n    * @brief Sets the platform configuration.\n    *\n    * @param[in] platformConfig The platform configuration.\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setPlatformConfig(const zdl::DlSystem::PlatformConfig& platformConfig);\n\n   /**\n    * @brief Sets network's runtime order of precedence. Example:\n    *        CPU_FLOAT32, GPU_FLOAT16, AIP_FIXED8_TF\n    *        Note:- setRuntimeProcessor() or setCPUFallbackMode() will be silently ignored when\n    *        setRuntimeProcessorOrder() is invoked\n    *\n    * @param[in] runtimeList The list of runtime in order of precedence\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setRuntimeProcessorOrder(const zdl::DlSystem::RuntimeList& runtimeList);\n\n    /**\n    * @brief Sets the unconsumed tensors as output\n    *\n    * @param[in] setOutput This enables unconsumed tensors (i.e)\n    *                      outputs which are not inputs to any\n    *                      layer (basically dead ends) to be marked\n    *                      for output\n    *\n    * @return The current instance of SNPEBuilder.\n    */\n   SNPEBuilder& setUnconsumedTensorsAsOutputs(\n      bool setOutput);\n\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n}}\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/SNPEFactory.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2015-2020 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef _SNPE_FACTORY_HPP_\n#define _SNPE_FACTORY_HPP_\n\n#include \"SNPE/SNPE.hpp\"\n#include \"DlSystem/DlEnums.hpp\"\n#include \"DlSystem/UDLFunc.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\n#include \"DlSystem/DlOptional.hpp\"\n\nnamespace zdl {\n   namespace DlSystem\n   {\n      class ITensorFactory;\n      class IUserBufferFactory;\n   }\n   namespace DlContainer\n   {\n      class IDlContainer;\n   }\n}\n\n\n\nnamespace zdl { namespace SNPE {\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * The factory class for creating SNPE objects.\n *\n */\nclass ZDL_EXPORT SNPEFactory\n{\npublic:\n\n   /**\n    * Indicates whether the supplied runtime is available on the\n    * current platform.\n    *\n    * @param[in] runtime The target runtime to check.\n    *\n    * @param[in] option Extent to perform runtime available check.\n    *\n    * @return True if the supplied runtime is available; false,\n    *         otherwise.\n    */\n   static bool isRuntimeAvailable(zdl::DlSystem::Runtime_t runtime);\n\n   /**\n    * Indicates whether the supplied runtime is available on the\n    * current platform.\n    *\n    * @param[in] runtime The target runtime to check.\n    *\n    * @param[in] option Extent to perform runtime available check.\n    *\n    * @return True if the supplied runtime is available; false,\n    *         otherwise.\n    */\n   static bool isRuntimeAvailable(zdl::DlSystem::Runtime_t runtime,\n                                  zdl::DlSystem::RuntimeCheckOption_t option);\n\n   /**\n    * Gets a reference to the tensor factory.\n    *\n    * @return A reference to the tensor factory.\n    */\n   static zdl::DlSystem::ITensorFactory& getTensorFactory();\n\n   /**\n    * Gets a reference to the UserBuffer factory.\n    *\n    * @return A reference to the UserBuffer factory.\n    */\n   static zdl::DlSystem::IUserBufferFactory& getUserBufferFactory();\n\n   /**\n    * Gets the version of the SNPE library.\n    *\n    * @return Version of the SNPE library.\n    *\n    */\n   static zdl::DlSystem::Version_t getLibraryVersion();\n\n   /**\n    * Set the SNPE storage location for all SNPE instances in this\n    * process. Note that this may only be called once, and if so\n    * must be called before creating any SNPE instances.\n    *\n    * @param[in] storagePath Absolute path to a directory which SNPE may\n    *  use for caching and other storage purposes.\n    *\n    * @return True if the supplied path was succesfully set as\n    *  the SNPE storage location, false otherwise.\n    */\n   static bool setSNPEStorageLocation(const char* storagePath);\n\n   /**\n    * @brief Register a user-defined op package with SNPE.\n    *\n    * @param[in] regLibraryPath Path to the registration library\n    *                      that allows clients to register a set of operations that are\n    *                      part of the package, and share op info with SNPE\n    *\n    * @return True if successful, False otherwise.\n    */\n   static bool addOpPackage( const std::string& regLibraryPath );\n\n   /**\n    * Indicates whether the OpenGL and OpenCL interoperability is supported\n    * on GPU platform.\n    *\n    * @return True if the OpenGL and OpenCl interop is supported; false,\n    *         otherwise.\n    */\n   static bool isGLCLInteropSupported();\n};\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n}}\n\n\n#endif\n"
  },
  {
    "path": "phonelibs/snpe/include/SNPE/UserBufferList.hpp",
    "content": "//==============================================================================\n//\n//  Copyright (c) 2019 Qualcomm Technologies, Inc.\n//  All Rights Reserved.\n//  Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n#ifndef PSNPE_USERBUFFERLIST_HPP\n#define PSNPE_USERBUFFERLIST_HPP\n\n#include <vector>\n#include \"DlSystem/UserBufferMap.hpp\"\n#include \"DlSystem/ZdlExportDefine.hpp\"\n\nnamespace zdl {\nnamespace PSNPE\n{\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n/**\n* @brief .\n*\n* The class for creating a UserBufferMap container.\n*\n*/\nclass ZDL_EXPORT UserBufferList final\n{\npublic:\n   UserBufferList();\n   UserBufferList(const size_t size);\n   void push_back(const zdl::DlSystem::UserBufferMap &userBufferMap);\n   zdl::DlSystem::UserBufferMap& operator[](const size_t index);\n   UserBufferList& operator =(const UserBufferList &other);\n   size_t size() const noexcept;\n   size_t capacity() const noexcept;\n   void clear() noexcept;\n   ~UserBufferList() = default;\n\nprivate:\n   void swap(const UserBufferList &other);\n   std::vector<zdl::DlSystem::UserBufferMap> m_userBufferMaps;\n\n};\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n} // namespace PSNPE\n} // namespace zdl\n#endif //PSNPE_USERBUFFERLIST_HPP\n"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoBase.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef SNPE_UDO_BASE_H\n#define SNPE_UDO_BASE_H\n\n#include <stdint.h>\n\n// Provide values to use for API version.\n#define API_VERSION_MAJOR 1\n#define API_VERSION_MINOR 5\n#define API_VERSION_TEENY 0\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n// Defines a bitmask of enum values.\ntypedef uint32_t SnpeUdo_Bitmask_t;\n\n// A string of characters, rather than an array of bytes.\n// Assumed to be UTF-8.\ntypedef char* SnpeUdo_String_t;\n\n// The maximum allowable length of a SnpeUdo_String_t in bytes,\n// including null terminator. SNPE will truncate strings longer\n// than this.\n#define SNPE_UDO_MAX_STRING_SIZE 1024\n\n/**\n  * An enum which holds the various error types.\n  * The error types are divided to classes :\n  * 0 - 99    : generic errors\n  * 100 - 200 : errors related to configuration\n  *\n  */\ntypedef enum\n{\n   /// No Error\n   SNPE_UDO_NO_ERROR                    = 0,\n   /// Unsupported value for core type\n   SNPE_UDO_WRONG_CORE                  = 1,\n   /// Invalid attribute/argument passed into UDO API\n   SNPE_UDO_INVALID_ARGUMENT            = 2,\n   /// Unsupported feature error\n   SNPE_UDO_UNSUPPORTED_FEATURE         = 3,\n   /// Error relating to memory allocation\n   SNPE_UDO_MEM_ALLOC_ERROR             = 4,\n   /* Configuration Specific errors */\n   /// No op with given attributes available in library\n   SNPE_UDO_WRONG_OPERATION             = 100,\n   /// Unsupported value for core type in UDO configuration\n   SNPE_UDO_WRONG_CORE_TYPE             = 101,\n   /// Wrong number of params in UDO definition\n   SNPE_UDO_WRONG_NUM_OF_PARAMS         = 102,\n   /// Wrong number of dimensions for tensor(s) in UDO definition\n   SNPE_UDO_WRONG_NUM_OF_DIMENSIONS     = 103,\n   /// Wrong number of input tensors in UDO definition\n   SNPE_UDO_WRONG_NUM_OF_INPUTS         = 104,\n   /// Wrong number of output tensors in UDO definition\n   SNPE_UDO_WRONG_NUM_OF_OUTPUTS        = 105,\n   SNPE_UDO_PROGRAM_CACHE_NOT_FOUND     = 106,\n   SNPE_UDO_UNKNOWN_ERROR               = 0xFFFFFFFF\n} SnpeUdo_ErrorType_t;\n\n/**\n  * An enum which holds the various data types.\n  * Designed to be used as single values or combined into a bitfield parameter\n  * (0x1, 0x2, 0x4, etc)\n  * \\n FIXED_XX types are targeted for data in tensors.\n  * \\n UINT / INT types are targeted for scalar params\n  */\ntypedef enum\n{\n   /// data type: 16-bit floating point\n   SNPE_UDO_DATATYPE_FLOAT_16       = 0x01,\n   /// data type: 32-bit floating point\n   SNPE_UDO_DATATYPE_FLOAT_32       = 0x02,\n   /// data type: 4-bit fixed point\n   SNPE_UDO_DATATYPE_FIXED_4        = 0x04,\n   /// data type: 8-bit fixed point\n   SNPE_UDO_DATATYPE_FIXED_8        = 0x08,\n   /// data type: 16-bit fixed point\n   SNPE_UDO_DATATYPE_FIXED_16       = 0x10,\n   /// data type: 32-bit fixed point\n   SNPE_UDO_DATATYPE_FIXED_32       = 0x20,\n   /// data type: 8-bit unsigned integer\n   SNPE_UDO_DATATYPE_UINT_8         = 0x100,\n   /// data type: 16-bit unsigned integer\n   SNPE_UDO_DATATYPE_UINT_16        = 0x200,\n   /// data type: 32-bit unsigned integer\n   SNPE_UDO_DATATYPE_UINT_32        = 0x400,\n   /// data type: 8-bit signed integer\n   SNPE_UDO_DATATYPE_INT_8          = 0x1000,\n   /// data type: 16-bit signed integer\n   SNPE_UDO_DATATYPE_INT_16         = 0x2000,\n   /// data type: 32-bit signed integer\n   SNPE_UDO_DATATYPE_INT_32         = 0x4000,\n   SNPE_UDO_DATATYPE_LAST           = 0xFFFFFFFF\n} SnpeUdo_DataType_t;\n\n/**\n  * An enum which holds the various layouts.\n  * Designed to be used as single values or combined into a bitfield parameter\n  * (0x1, 0x2, 0x4, etc)\n  */\ntypedef enum\n{\n   /// data layout (4D): NHWC (batch-height-width-channel)\n   SNPE_UDO_LAYOUT_NHWC             = 0x01,\n   /// data layout (4D): NCHW (batch-channel-height-width)\n   SNPE_UDO_LAYOUT_NCHW             = 0x02,\n   /// data layout (5D): NDHWC (batch-dimension-height-width-channel)\n   SNPE_UDO_LAYOUT_NDHWC            = 0x04,\n   SNPE_UDO_LAYOUT_GPU_OPTIMAL1     = 0x08,\n   SNPE_UDO_LAYOUT_GPU_OPTIMAL2     = 0x10,\n   SNPE_UDO_LAYOUT_DSP_OPTIMAL1     = 0x11,\n   SNPE_UDO_LAYOUT_DSP_OPTIMAL2     = 0x12,\n   // Indicates no data will be allocated for this tensor.\n   // Used to specify optional inputs/outputs positionally.\n   SNPE_UDO_LAYOUT_NULL             = 0x13,\n   SNPE_UDO_LAYOUT_LAST             = 0xFFFFFFFF\n} SnpeUdo_TensorLayout_t;\n\n/**\n  * An enum which holds the UDO library Core type .\n  * Designed to be used as single values or combined into a bitfield parameter\n  * (0x1, 0x2, 0x4, etc)\n  */\ntypedef enum\n{\n   /// Library target IP Core is undefined\n   SNPE_UDO_CORETYPE_UNDEFINED   = 0x00,\n   /// Library target IP Core is CPU\n   SNPE_UDO_CORETYPE_CPU         = 0x01,\n   /// Library target IP Core is GPU\n   SNPE_UDO_CORETYPE_GPU         = 0x02,\n   /// Library target IP Core is DSP\n   SNPE_UDO_CORETYPE_DSP         = 0x04,\n   SNPE_UDO_CORETYPE_LAST         = 0xFFFFFFFF\n} SnpeUdo_CoreType_t;\n\n/**\n  * An enum to specify the parameter type : Scalar or Tensor\n  */\ntypedef enum\n{\n   /// UDO static param type: scalar\n   SNPE_UDO_PARAMTYPE_SCALAR,\n   /// UDO static param type: string\n   SNPE_UDO_PARAMTYPE_STRING,\n   /// UDO static param type: tensor\n   SNPE_UDO_PARAMTYPE_TENSOR,\n   SNPE_UDO_PARAMTYPE_LAST   = 0xFFFFFFFF\n} SnpeUdo_ParamType_t;\n\n/**\n  * An enum to specify quantization type\n  */\ntypedef enum\n{\n   /// Tensor Quantization type: NONE. Signifies unquantized tensor data\n   SNPE_UDO_QUANTIZATION_NONE,\n   /// Tensor Quantization type: Tensorflow-style\n   SNPE_UDO_QUANTIZATION_TF,\n   SNPE_UDO_QUANTIZATION_QMN,\n   SNPE_UDO_QUANTIZATION_LAST   = 0xFFFFFFFF\n} SnpeUdo_QuantizationType_t;\n\n/**\n * @brief A struct which is used to provide a version number using 3 values : major, minor, teeny\n *\n */\ntypedef struct\n{\n   /// version field: major - for backward-incompatible changes\n   uint32_t major;\n   /// version field: minor - for backward-compatible feature updates\n   uint32_t minor;\n   /// version field: teeny - for minor bug-fixes and clean-up\n   uint32_t teeny;\n} SnpeUdo_Version_t;\n\n/**\n * @brief A struct returned from version query, contains the Library version and API version\n *\n */\ntypedef struct\n{\n   /// Version of UDO library. Controlled by users\n   SnpeUdo_Version_t libVersion;\n   /// Version of SNPE UDO API used in compiling library. Determined by SNPE\n   SnpeUdo_Version_t apiVersion;\n} SnpeUdo_LibVersion_t;\n\n/**\n * @brief A union to hold the value of a generic type. Allows defining a parameter struct\n * in a generic way, with a \"value\" location that holds the data regardless of the type.\n *\n */\ntypedef union\n{\n   /// value type: float\n   float    floatValue;\n   /// value type: unsigned 32-bit integer\n   uint32_t uint32Value;\n   /// value type: signed 32-bit integer\n   int32_t  int32Value;\n   /// value type: unsigned 16-bit integer\n   uint16_t uint16Value;\n   /// value type: signed 16-bit integer\n   int16_t  int16Value;\n   /// value type: unsigned 8-bit integer\n   uint8_t  uint8Value;\n   /// value type: signed 8-bit integer\n   int8_t   int8Value;\n} SnpeUdo_Value_t;\n\n/**\n * @brief A struct which defines a scalar parameter : name, data type, and union of values\n *\n */\ntypedef struct\n{\n   /// The parameter data type : float, int, etc.\n   SnpeUdo_DataType_t  dataType;\n   /// a union of specified type which holds the data\n   SnpeUdo_Value_t dataValue;\n} SnpeUdo_ScalarParam_t;\n\n/**\n * @brief A struct which defines the quantization parameters in case of Tensorflow style quantization\n *\n */\ntypedef struct\n{\n   /// minimum value of the quantization range of data\n   float minValue;\n   /// maximum value of the quantization range of data\n   float maxValue;\n} SnpeUdo_TFQuantize_t;\n\n/**\n * @brief A struct which defines the quantization type, and union of supported quantization structs\n *\n */\ntypedef struct\n{\n   /// quantization type (only TF-style currently supported)\n   SnpeUdo_QuantizationType_t quantizeType;\n   union\n   {\n     /// TF-style min-max quantization ranges\n     SnpeUdo_TFQuantize_t TFParams;\n   };\n} SnpeUdo_QuantizeParams_t;\n\n/**\n * @brief A struct which defines the datatype associated with a specified core-type\n * This should be used to denote the datatypes for a single tensor info, depending\n * on the intended execution core.\n *\n */\ntypedef struct\n{\n    /// The IP Core\n    SnpeUdo_CoreType_t     coreType;\n    /// The associated datatype for this coreType\n    SnpeUdo_DataType_t       dataType;\n} SnpeUdo_PerCoreDatatype_t;\n\n/**\n * @brief A struct which defines a tensor parameter : name, data type, layout, quantization, more.\n *        Also holds a pointer to the tensor data.\n *\n */\ntypedef struct\n{\n   /// The maximum allowable dimensions of the tensor. The memory held in\n   /// _tensorData_ is guaranteed to be large enough for this.\n   uint32_t*                maxDimensions;\n   /// The current dimensions of the tensor. An operation may modify the current\n   /// dimensions of its output, to indicate cases where the output has been\n   /// \"resized\".\n   /// Note that for static parameters, the current and max dimensions must\n   /// match.\n   uint32_t*                currDimensions;\n   /// Quantization params applicable to the tensor. Currently only supports\n   /// Tensorflow quantization style.\n   SnpeUdo_QuantizeParams_t quantizeParams;\n   /// Number of dimensions to the tensor: 3D, 4D, etc.\n   uint32_t                 tensorRank;\n   /// The parameter data type: float, int, etc.\n   SnpeUdo_DataType_t       dataType;\n   /// The tensor layout type: NCHW, NHWC, etc.\n   SnpeUdo_TensorLayout_t   layout;\n   /// Opaque pointer to tensor data. User may be required to re-interpret the pointer\n   /// based on core-specific definitions.\n   void*                    tensorData;\n} SnpeUdo_TensorParam_t;\n\n/**\n * @brief A struct which defines tensor information for activation tensors only\n *\n * It describes an activation tensor object using its name, the intended layout and the datatype\n * it will take depending on the intended runtime core. The repeated field indicates that\n * that the tensor info describes several input/output activation tensors, which all share the\n * aforementioned properties.\n */\ntypedef struct\n{\n    /// The tensor name\n    SnpeUdo_String_t    tensorName;\n    /// The tensor layout type: NCHW, NHWC, etc.\n    SnpeUdo_TensorLayout_t   layout;\n    /// The per core datatype: {SNPE_UDO_DATATYPE, SNPE_UDO_CORE_TYPE}\n    SnpeUdo_PerCoreDatatype_t* perCoreDatatype;\n    /// A boolean field indicating that this tensorinfo will be repeated e.x for ops such as Concat or Split\n    bool repeated;\n\n} SnpeUdo_TensorInfo_t;\n\n\n/**\n * @brief struct which defines a UDO parameter - a union of scalar, tensor and string parameters\n *\n */\ntypedef struct\n{\n   /// Type is scalar or tensor\n  SnpeUdo_ParamType_t paramType;\n  /// The param name, for example : \"offset\", \"activation_type\"\n  SnpeUdo_String_t    paramName;\n  union\n  {\n    /// scalar param value\n    SnpeUdo_ScalarParam_t scalarParam;\n    /// tensor param value\n    SnpeUdo_TensorParam_t tensorParam;\n    /// string param value\n    SnpeUdo_String_t      stringParam;\n  };\n} SnpeUdo_Param_t;\n\n/**\n * @brief A struct which defines Operation information which is specific for IP core (CPU, GPU, DSP ...)\n *\n */\ntypedef struct\n{\n   /// The IP Core\n   SnpeUdo_CoreType_t     udoCoreType;\n   /// Bitmask, defines supported internal calculation types (like FLOAT_32, etc)\n   /// Based on SnpeUdo_DataType\n   SnpeUdo_Bitmask_t      operationCalculationTypes;\n} SnpeUdo_OpCoreInfo_t;\n\n/**\n * @brief A struct which defines the common and core-specific Operation information\n *\n */\ntypedef struct\n{\n   /// Operation type\n   SnpeUdo_String_t      operationType;\n   /// A bitmask describing which IP Cores (CPU, GPU, DSP ...) support this operation\n   /// Translated based on SnpeUdo_CoreType\n   SnpeUdo_Bitmask_t     supportedByCores;\n   /// Number of static parameters defined by the op\n   uint32_t              numOfStaticParams;\n   /// Array of static parameters. Can be scalar or tensor params\n   SnpeUdo_Param_t*      staticParams;\n   /// Number of input tensors this op receives\n   uint32_t              numOfInputs;\n   /// Array of input tensor names to this operation\n   SnpeUdo_String_t*      inputNames;\n   /// Number of output tensors this op receives\n   uint32_t              numOfOutputs;\n   /// Array of output tensor names to this operation\n   SnpeUdo_String_t*      outputNames;\n   /// Number of cores that the op can execute on\n   uint32_t              numOfCoreInfo;\n   /// Array of per-core information entries\n   SnpeUdo_OpCoreInfo_t* opPerCoreInfo;\n    /// Array of input tensor infos for this operation\n   SnpeUdo_TensorInfo_t*     inputInfos;\n   /// Array of output tensor infos for this operation\n   SnpeUdo_TensorInfo_t*     outputInfos;\n} SnpeUdo_OperationInfo_t;\n\n/**\n * @brief A struct which provides the implementation library info : type, name\n *\n */\ntypedef struct\n{\n   /// Defines the IP Core that this implementation library is targeting\n   SnpeUdo_CoreType_t     udoCoreType;\n   /// library name. will be looked at in the standard library path\n   SnpeUdo_String_t       libraryName;\n} SnpeUdo_LibraryInfo_t;\n\n/**\n * @brief A struct returned by the registration library and contains information on the UDO package :\n * name, operations, libraries, etc.\n *\n */\ntypedef struct\n{\n   /// A string containing the package name\n   SnpeUdo_String_t         packageName;\n   /// A bitmask describing supported IP cores (CPU, GPU, DSP ...)\n   /// Translated based on SnpeUdo_CoreType\n   SnpeUdo_Bitmask_t        supportedCoreTypes;\n   /// The number of implementation libraries in the package\n   uint32_t                numOfImplementationLib;\n   /// Array of implementation libraries names/types\n   SnpeUdo_LibraryInfo_t*   implementationLib;\n   /// A string containing all operation types separated by space\n   SnpeUdo_String_t         operationsString;\n   /// Number of supported operations\n   uint32_t                numOfOperations;\n   /// Array of Operation info structs. Each entry describes one\n   /// Operation (name, params, inputs, outputs)\n   SnpeUdo_OperationInfo_t* operationsInfo;\n} SnpeUdo_RegInfo_t;\n\n/**\n* @brief A struct returned by the implementation library and contains information on the\n* specific library: name, IP Core, operations, etc.\n*\n*/\ntypedef struct\n{\n   /// Defines the IP Core that this implementation library is targeting\n   SnpeUdo_CoreType_t     udoCoreType;\n   /// A string containing the package name\n   SnpeUdo_String_t       packageName;\n   /// A string containing all operation types separated by space\n   SnpeUdo_String_t       operationsString;\n   /// Number of supported operations\n   uint32_t              numOfOperations;\n} SnpeUdo_ImpInfo_t;\n\n/**\n * @brief This struct defines an operation. It is used for validation\n * or creation of an operation.\n * In case of using it for creation, the static params which are tensors\n * contain pointers to the real data (weights, for example), and input/output\n * tensors also include pointers to the buffers used.\n */\ntypedef struct\n{\n   /// The IP Core that the operation is defined for - CPU, GPU, DSP...\n   SnpeUdo_CoreType_t      udoCoreType;\n   /// Operation type\n   SnpeUdo_String_t        operationType;\n   /// The number of static parameters provided in the staticParams array.\n   /// this number has to match the number provided by the UDO Registration library information\n   uint32_t               numOfStaticParams;\n   /// Array of static parameters\n   SnpeUdo_Param_t*        staticParams;\n   /// The number of input parameters provided in inputs array.\n   /// this number has to match the number provided by the UDO Registration library information\n   uint32_t               numOfInputs;\n   /// Array of input tensors, providing layout, data type, sizes, etc\n   /// When used to create an operation, also contains the initial location of the data\n   SnpeUdo_TensorParam_t*  inputs;\n   /// The number of output parameters provided in inputs array.\n   /// this number has to match the number provided by the UDO Registration library information\n   uint32_t               numOfOutputs;\n   /// Array of output tensors, providing layout, data type, sizes, etc\n   /// When used to create an operation, also contains the initial location of the data\n   SnpeUdo_TensorParam_t*  outputs;\n} SnpeUdo_OpDefinition_t;\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif //SNPE_UDO_BASE_H\n"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoImpl.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef SNPE_UDO_IMPL_H\n#define SNPE_UDO_IMPL_H\n\n#include <stdbool.h>\n\n#include \"SnpeUdo/UdoShared.h\"\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\ntypedef struct _SnpeUdo_OpFactory_t* SnpeUdo_OpFactory_t;\ntypedef struct _SnpeUdo_Operation_t* SnpeUdo_Operation_t;\n\n/**\n * @brief Initialize the shared library's data structures. Calling any other\n *        library function before this one will result in error.\n *\n * @param[in] globalInfrastructure Global core-specific infrastructure to be\n *            used by operations created in this library. The definition and\n *            semantics of this object will be defined in the corresponding\n *            implementation header for the core type.\n * @return Error code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_initImplLibrary(void* globalInfrastructure);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_InitImplLibraryFunction_t)(void*);\n\n/**\n * @brief A function to query the API version of the UDO implementation library.\n *        The function populates a SnpeUdo_LibVersion_t struct, which contains a SnpeUdo_Version_t\n *        struct for API version and library version.\n *\n * @param[in, out] version A pointer to struct which contains major, minor, teeny information for\n *                 library and api versions.\n *\n * @return Error code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_getImplVersion(SnpeUdo_LibVersion_t** version);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_getImplVersion_t)(SnpeUdo_LibVersion_t** version);\n\n/**\n * @brief Release the shared library's data structures, and invalidate any\n *        handles returned by the library. The behavior of any outstanding\n *        asynchronous calls made to this library when this function is called\n *        are undefined. All library functions (except SnpeUdo_initImplLibrary) will\n *        return an error after this function has been successfully called.\n *\n *        It should be possible to call SnpeUdo_initImplLibrary after calling this\n *        function, and re-initialize the library.\n *\n * @return Error code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_terminateImplLibrary(void);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_TerminateImplLibraryFunction_t)(void);\n\n\n/**\n * @brief A function to query info on the UDO implementation library.\n *        The function populates a structure which contains information about\n *        operations that are part of this library\n *\n * @param[in, out] implementationInfo A pointer to struct which contains information\n *                 on the operations\n *\n * @return error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_getImpInfo(SnpeUdo_ImpInfo_t** implementationInfo);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_GetImpInfoFunction_t)(SnpeUdo_ImpInfo_t** implementationInfo);\n\n/**\n * @brief A function to create an operation factory.\n *        The function receives the operation type, and an array of static parameters,\n *        and returns operation factory handler\n *\n * @param[in] udoCoreType The Core type to create the operation on. An error will\n *            be returned if this does not match the core type of the library.\n *\n * @param[in] perFactoryInfrastructure CreateOpFactory infrastructure appropriate to this\n *            core type. The definition and semantics of this object will be defined\n *            in the corresponding implementation header for the core type.\n *\n * @param[in] operationType A string containing Operation type. for example \"MY_CONV\"\n *\n * @param[in] numOfStaticParams The number of static parameters.\n *\n * @param[in] staticParams Array of static parameters\n *\n * @param[in,out] opFactory Handler to Operation Factory, to be used when creating operations\n *\n * @return Error Code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_createOpFactory(SnpeUdo_CoreType_t    udoCoreType,\n                        void*                perFactoryInfrastructure,\n                        SnpeUdo_String_t      operationType,\n                        uint32_t             numOfStaticParams,\n                        SnpeUdo_Param_t*      staticParams,\n                        SnpeUdo_OpFactory_t*  opFactory);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_CreateOpFactoryFunction_t)(SnpeUdo_CoreType_t,\n                                     void*,\n                                     SnpeUdo_String_t,\n                                     uint32_t,\n                                     SnpeUdo_Param_t*,\n                                     SnpeUdo_OpFactory_t*);\n\n\n/**\n * @brief A function to release the resources allocated for an operation factory\n *        created by this library.\n *\n * @param[in] factory The operation factory to release. Upon success this handle will be invalidated.\n *\n * @return Error Code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_releaseOpFactory(SnpeUdo_OpFactory_t opFactory);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_ReleaseOpFactoryFunction_t)(SnpeUdo_OpFactory_t);\n\n/**\n * @brief A function to create an operation from the factory.\n *        The function receives array of inputs and array of outputs, and creates an operation\n *        instance, returning the operation instance handler.\n *\n * @param[in] opFactory OpFactory instance containing the parameters for this operation.\n *\n * @param[in] perOpInfrastructure Per-Op infrastructure for this operation. The definition\n *            and semantics of this object will be defined in the implementation header\n *            appropriate to this core type.\n *\n * @param[in] numOfInputs The number of input tensors this operation will receive.\n *\n * @param[in] inputs Array of input tensors, providing both the sizes and initial\n *            location of the data.\n *\n * @param[in] numOfOutputs Number of output tensors this operation will produce.\n *\n * @param[in] outputs Array of output tensors, providing both the sizes and\n *            initial location of the data.\n *\n * @param[in,out] operation Handle for newly created operation instance.\n *\n * @return Error Code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_createOperation(SnpeUdo_OpFactory_t    opFactory,\n                        void*                 perOpInfrastructure,\n                        uint32_t              numOfInputs,\n                        SnpeUdo_TensorParam_t* inputs,\n                        uint32_t              numOfOutputs,\n                        SnpeUdo_TensorParam_t* outputs,\n                        SnpeUdo_Operation_t*   operation);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_CreateOperationFunction_t)(SnpeUdo_OpFactory_t,\n                                     void*,\n                                     uint32_t,\n                                     SnpeUdo_TensorParam_t*,\n                                     uint32_t,\n                                     SnpeUdo_TensorParam_t*,\n                                     SnpeUdo_Operation_t*);\n\n/**\n * @brief A pointer to notification function.\n *\n *        The notification function supports the non-blocking (e.g. asynchronous) execution use-case.\n *        In case an \"executeUdoOp\" function is called with \"blocking\" set to zero, and a\n *        notify function, this function will be called by the implementation library at the\n *        end of execution. The implementation library will pass the notify function the ID\n *        that was provided to it when \"executeUdoOp\" was called.\n *\n * @param[in] ID 32-bit value, that was provided to executeUdoOp by the calling entity.\n *            Can be used to track the notifications, in case of multiple execute calls issued.\n *\n * @return Error code\n *\n */\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_ExternalNotify_t)(const uint32_t ID);\n\n/**\n * @brief Operation execution function.\n *\n *        Calling this function will run the operation on set of inputs, generating a set of outputs.\n *        The call can be blocking (synchronous) or non-blocking (asynchronous). To support the\n *        non-blocking mode, the calling entity can pass an ID and a notification function.\n *        At the end of the execution this notification function would be called, passing it the ID.\n *        <b> NOTE: Asynchronous execution mode not supported in this release. </b>\n *\n * @param[in] operation handle to the operation on which execute is invoked\n * @param[in] blocking flag to indicate execution mode.\n *            If set, execution is blocking,\n *            e.g SnpeUdo_executeOp call does not return until execution is done.\n *            If not set, SnpeUdo_executeOp returns immediately, and the\n *            library will call the notification function (if set) when execution is done.\n *\n * @param[in] ID 32-bit number that can be used by the calling entity to track execution\n *            in case of non-blocking execution.\n *            For example, it can be a sequence number, increased by one on each call.\n *\n * @param[in] notifyFunc Pointer to notification function. if the pointer is set, and execution is\n *            non-blocking, the library will call this function at end of execution,\n *            passing the number provided as ID\n *\n * @return Error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_executeOp(SnpeUdo_Operation_t operation,\n                  bool         blocking,\n                  const uint32_t ID,\n                  SnpeUdo_ExternalNotify_t notifyFunc);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_ExecuteOpFunction_t)(SnpeUdo_Operation_t,\n                               bool,\n                               const uint32_t,\n                               SnpeUdo_ExternalNotify_t);\n\n/**\n * @brief A function to setting the inputs & outputs. part of SnpeUdo_Operation struct,\n *        returned from creation of a new operation instance.\n *        <b> Not supported in this release. </b>\n *\n *        This function allows the calling entity to change some of the inputs and outputs\n *        between calls to execute.\n *        Note that the change is limited to changing the <b> pointer </b> to the tensor data only.\n *        Any other change may be rejected by the implementation library, causing\n *        immediate invalidation of the operation instance\n *\n * @param[in] operation Operation on which IO tensors are set\n *\n * @param[in] inputs array of tensor parameters. The calling entity may provide a subset of the\n *            operation inputs, providing only those that it wants to change.\n *\n * @param[in] outputs array of tensor parameters. The calling entity may provide a subset of the\n *            operation outputs, providing only those that it wants to change.\n *\n * @return Error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_setOpIO(SnpeUdo_Operation_t operation,\n                SnpeUdo_TensorParam_t* inputs,\n                SnpeUdo_TensorParam_t* outputs);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_SetOpIOFunction_t)(SnpeUdo_Operation_t,\n                             SnpeUdo_TensorParam_t*,\n                             SnpeUdo_TensorParam_t*);\n\n/**\n * @brief A function to return execution times.\n *\n *        This function can be called to query the operation execution times on the IP core\n *        on which the operation is run. The time is provided in micro-seconds\n *\n * @param[in] operation Handle to operation whose execution time is being profiled\n *\n * @param[in,out] executionTime pointer to a uint32 value.This function writes the operation\n *                execution time in usec into this value.\n *\n * @return Error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_profileOp(SnpeUdo_Operation_t operation, uint32_t *executionTime);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_ProfileOpFunction_t)(SnpeUdo_Operation_t, uint32_t*);\n\n/**\n * @brief A function to release the operation instance\n *        \\n When it is called, the implementation library needs to release all resources\n *        allocated for this operation instance.\n *        \\n Note that all function pointers which are part of SnpeUdo_Operation become\n *        <b> invalid </b> once releaseUdoOp call returns.\n *\n * @param[in] operation Handle to operation to be released\n * @return Error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_releaseOp(SnpeUdo_Operation_t operation);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_ReleaseOpFunction_t)(SnpeUdo_Operation_t);\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n#endif //SNPE_UDO_IMPL_H\n"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoImplCpu.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n// Header to be used by a CPU UDO Implementation library\n\n#ifndef SNPE_UDO_IMPL_CPU_H\n#define SNPE_UDO_IMPL_CPU_H\n\n#include <stdio.h>\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief This struct provides the infrastructure needed by a developer of\n * CPU UDO Implementation library.\n *\n * The framework/runtime which loads the CPU UDO implementation library provides\n * this infrastructure data to the loaded library at the time of op factory creation.\n * as an opaque pointer. It contains hooks for the UDO library to invoke supported\n * functionality at the time of execution\n *\n * @param getData function pointer to retrieve raw tensor data from opaque pointer\n *  passed into the UDO when creating an instance.\n * @param getDataSize function pointer to retrieve tensor data size from opaque pointer\n */\n\ntypedef struct\n{\n   /// function pointer to retrieve raw tensor data from opaque pointer\n   /// passed into the UDO when creating an instance.\n   float* (*getData)(void*);\n   /// function pointer to retrieve tensor data size from opaque pointer\n   size_t (*getDataSize) (void*);\n} SnpeUdo_CpuInfrastructure_t;\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // SNPE_UDO_IMPL_CPU_H"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoImplDsp.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n//==============================================================================\n/*\n * THIS HEADER FILE IS COPIED FROM HEXAGON-NN PROJECT\n *\n */\n//==============================================================================\n\n\n// Header to be used by a DSP Hexnn UDO Implementation library\n\n#ifndef SNPE_UDO_IMPL_DSP_H\n#define SNPE_UDO_IMPL_DSP_H\n#include <stdio.h>\n#include \"SnpeUdo/UdoImpl.h\"\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief A function to validate that a set of params is supported by an operation\n *        This function is HexNN specific, use case is when registration library is not in use.\n *        Optional function.\n *\n * @param[in] operationType Operation type\n * @param[in] numOfStaticParams Number of static params defined by the op\n * @param[in] staticParams Array of static params to the op\n * @return Error code, indicating if the operation can be created on this set of configuration or not.\n *\n */\n\nSnpeUdo_ErrorType_t\nSnpeUdo_validateOperation (SnpeUdo_String_t operationType,\n                           uint32_t numOfStaticParams,\n                           const SnpeUdo_Param_t* staticParams);\n\ntypedef SnpeUdo_ErrorType_t (*SnpeUdo_ValidateOperationFunction_t) (SnpeUdo_String_t,\n                                                                    uint32_t,\n                                                                    const SnpeUdo_Param_t*);\n\n\n// enum used for indicating input/outout tensor data layouts on DSP, plain vs d32\ntypedef enum {\n        SNPE_UDO_DSP_TENSOR_LAYOUT_PLAIN,\n        SNPE_UDO_DSP_TENSOR_LAYOUT_D32\n} SnpeUdo_HexNNTensorLayout_t;\n\n/**\n * @brief A function to query numbers of inputs and outputs,\n *        quantization type of each input and each output as arrays,\n *        and data layout (plain vs d32) of each input and each output as arrays\n *        of an operation.\n * inputsQuantTypes and inputsLayouts should point to arrays of size numOfInputs\n * outputsQuantTypes and outputsLayouts should point to arrays of size numOfOutputs\n *\n * Note: inputsLayouts and inputsLayouts can point to NULL, in this case, it is\n * assumed all inputs and/or outputs have plain data layouts, i.e. no D32\n *\n * @param[in] operationType Operation type\n * @param[in] numOfStaticParams Number of static params defined by the op\n * @param[in] staticParams Array of static params to the op\n * @param[in,out] numOfInputs Number of input tensors to the op\n * @param[in,out] inputsQuantTypes Array of Quantization info for each input tensor\n * @param[in,out] inputsLayouts Array of layout type for each input tensor\n * @param[in,out] numOfOutputs Number of output tensors to the op\n * @param[in,out] outputsQuantTypes Array of Quantization info for each output tensor\n * @param[in,out] outputsLayouts Array of layout type for each output tensor\n * @return error code, indicating status of query\n */\n\nSnpeUdo_ErrorType_t\nSnpeUdo_queryOperation (SnpeUdo_String_t operationType,\n                        uint32_t numOfStaticParams,\n                        const SnpeUdo_Param_t* staticParams,\n                        uint32_t* numOfInputs,\n                        SnpeUdo_QuantizationType_t** inputsQuantTypes,\n                        SnpeUdo_HexNNTensorLayout_t** inputsLayouts,\n                        uint32_t* numOfOutputs,\n                        SnpeUdo_QuantizationType_t** outputsQuantTypes,\n                        SnpeUdo_HexNNTensorLayout_t** outputsLayouts);\n\ntypedef SnpeUdo_ErrorType_t (*SnpeUdo_QueryOperationFunction_t) (SnpeUdo_String_t,\n                                                                 uint32_t,\n                                                                 const SnpeUdo_Param_t*,\n                                                                 uint32_t*,\n                                                                 SnpeUdo_QuantizationType_t**,\n                                                                 SnpeUdo_HexNNTensorLayout_t**,\n                                                                 uint32_t*,\n                                                                 SnpeUdo_QuantizationType_t**,\n                                                                 SnpeUdo_HexNNTensorLayout_t**);\n\n\n\n// Global infrastructure functions supported by Hexagon-NN v2\ntypedef void (*workerThread_t) (void* perOpInfrastructure, void* userData);\ntypedef int (*udoSetOutputTensorSize_t) (void* perOpInfrastructure, uint32_t outIdx, uint32_t size);\ntypedef int (*udoGetInputD32Paddings_t) (void* perOpInfrastructure, uint32_t inIdx,\n                                         uint32_t* heightPadBefore, uint32_t* heightPadAfter,\n                                         uint32_t* widthPadBefore, uint32_t* widthPadAfter,\n                                         uint32_t* depthPadBefore, uint32_t* depthPadAfter);\ntypedef int (*udoSetOutputD32ShapeSizePaddings_t) (void* perOpInfrastructure, uint32_t outIdx,\n                                                   uint32_t batch,\n                                                   uint32_t height, uint32_t heightPadBefore, uint32_t heightPadAfter,\n                                                   uint32_t width, uint32_t widthPadBefore, uint32_t widthPadAfter,\n                                                   uint32_t depth, uint32_t depthPadBefore, uint32_t depthPadAfter,\n                                                   SnpeUdo_DataType_t dataType);\ntypedef void* (*udoMemalign_t) (size_t n, size_t size);\ntypedef void* (*udoMalloc_t) (size_t size);\ntypedef void* (*udoCalloc_t) (size_t n, size_t size);\ntypedef void (*udoFree_t) (void* ptr);\ntypedef uint32_t (*udoGetVtcmSize_t) (void* perOpInfrastructure);\ntypedef void* (*udoGetVtcmPtr_t) (void* perOpInfrastructure);\ntypedef uint32_t (*udoVtcmIsReal_t) (void* perOpInfrastructure);\ntypedef void (*udoRunWorkerThreads_t) (void* perOpInfrastructure, uint32_t nThreads, workerThread_t w, void* userData);\n\ntypedef struct hexNNv2GlobalInfra {\n    udoSetOutputTensorSize_t udoSetOutputTensorSize;\n    udoGetInputD32Paddings_t udoGetInputD32Paddings;\n    udoSetOutputD32ShapeSizePaddings_t udoSetOutputD32ShapeSizePaddings;\n    udoMemalign_t udoMemalign;\n    udoMalloc_t udoMalloc;\n    udoCalloc_t udoCalloc;\n    udoFree_t udoFree;\n    udoGetVtcmSize_t udoGetVtcmSize;\n    udoGetVtcmPtr_t udoGetVtcmPtr;\n    udoVtcmIsReal_t udoVtcmIsReal;\n    udoRunWorkerThreads_t udoRunWorkerThreads;\n} SnpeUdo_HexNNv2GlobalInfra_t;\n\n// hexnn types\ntypedef enum hexnnInfraType {\n   UDO_INFRA_HEXNN_V2,\n   UDO_INFRA_HEXNN_V3   // reserved, do not use\n} SnpeUdo_HexNNInfraType_t;\n\n\n/**\n * @brief Infrastructures needed by a developer of DSP Hexnn UDO Implementation library.\n *\n * The framework/runtime which loads the Hexnn UDO implementation library provides\n * this infrastructure to the loaded library by calling \"SnpeUdo_initImplLibrary\"\n * function, and passing it (cast to void*). The Hexnn UDO library is expected\n * to cast it back to this structure.\n *\n */\ntypedef struct dspGlobalInfrastructure {\n    SnpeUdo_Version_t   dspInfraVersion;     // api version\n    SnpeUdo_HexNNInfraType_t infraType;\n    SnpeUdo_HexNNv2GlobalInfra_t hexNNv2Infra;\n} SnpeUdo_DspGlobalInfrastructure_t;\n\n\n/**\n * hexnn v2 per op factory infrastructure\n *\n * The framework/runtime passes per op factory infrastructure as a void pointer\n * to HexNN UDO implementation library by calling function \"SnpeUdo_createOpFactory\".\n * UDO implementation library is expected to cast it back to this following struct.\n *\n */\ntypedef struct hexnnv2OpFactoryInfra {\n   unsigned long graphId;\n} SnpeUdo_HexNNv2OpFactoryInfra_t;\n\n\n/**\n * hexnn v2 per operation infrastructure\n *\n * The framework/runtime passes per operation infrastructure as a void pointer\n * to HexNN UDO implementation library by calling function \"SnpeUdo_createOperation\".\n * UDO implementation library is expected to cast it to the following type and save it.\n *\n * This is needed to be passed back into some functions from global infrastructure.\n *\n */\ntypedef void* SnpeUdo_HexNNv2OpInfra_t;\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // SNPE_UDO_IMPL_DSP_H\n"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoImplGpu.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n// Header to be used by a GPU UDO Implementation library\n\n#ifndef SNPE_UDO_IMPL_GPU_H\n#define SNPE_UDO_IMPL_GPU_H\n\n#include \"CL/cl.h\"\n#include \"SnpeUdo/UdoBase.h\"\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * This header defines version 0.0.0 of the GPU UDO Infrastructure.\n * It defines the interpretation of the global and per-OpFactory infrastructure pointers\n * as well as the interpretation of tensorData pointers.\n *\n * The per-Operation infrastructure pointer is defined to be null, and should not be used.\n *\n * The SnpeUdoTensorParam_t struct below provides the interpretation for\n * the tensorData opaque pointer for SnpeUdoTensorParams representing inputs or outputs.\n *\n * The tensorData opaque pointer populated in SnpeUdoScalarParam_t structs should be interpreted\n * as a host-readable data pointer.\n *\n */\n\n/**\n * @brief Function to retrieve opencl program from Program Cache repository.\n * @param programCache is opaque pointer to Program Cache repository provided by\n * SNPE GPU UDO runtime.\n * @param programName is name associated with opencl program for UDO.\n * @param program is pointer to opencl program which will be populated with\n * valid opencl program if found in Program Cache repository.\n * @return SnpeUdo_ErrorType_t is error type returned. SNPE_UDO_NO_ERROR is returned\n * on success.\n */\ntypedef SnpeUdo_ErrorType_t (*SnpeUdo_getProgram_t)\n   (void* programCache, const char* programName, cl_program* program);\n\n/**\n * @brief Function to store valid opencl program in Program Cache repository.\n * @param programCache is opaque pointer to Program Cache repository provided by\n * SNPE GPU UDO runtime.\n * @param programName is name associated with opencl program for UDO.\n * @param program is valid opencl program after program is built.\n * @return SnpeUdo_ErrorType_t is error type returned. SNPE_UDO_NO_ERROR is returned\n * on success.\n * */\ntypedef SnpeUdo_ErrorType_t (*SnpeUdo_storeProgram_t)\n   (void* programCache, const char * programName, cl_program program);\n\n/**\n * @brief Global Infrastructure Definition for GPU UDO Implementations.\n */\ntypedef struct {\n   // Infrastructure definition version. This header is 0.0.0\n   SnpeUdo_Version_t   gpuInfraVersion;\n   SnpeUdo_getProgram_t SnpeUdo_getProgram;\n   SnpeUdo_storeProgram_t SnpeUdo_storeProgram;\n} SnpeUdo_GpuInfrastructure_t;\n\n/**\n * @brief Per OpFactory Infrastructure Definition for GPU UDO Implementations.\n * @note  This version of the infrastructure definition guarantees that the same\n *        Per OpFactory infrastructure pointer will be provided to all OpFactories\n *        in the same network.\n */\ntypedef struct\n{\n   cl_context context;\n   cl_command_queue commandQueue;\n   void* programCache;\n} SnpeUdo_GpuOpFactoryInfrastructure_t;\n\n/**\n * @brief Opaque tensorData definition for operation inputs and outputs.\n *\n * The following is a list of all SnpeUdoTensorLayout_t values supported by the\n * GPU UDO implementation, and how the parameters of the struct should be\n * interpreted in each case:\n *\n * SNPE_UDO_LAYOUT_NHWC:\n *   mem shall be single-element array, pointing to a cl buffer memory object.\n *   the dimensions of this object match the dimensions specified in the encompassing\n *   SnpeUdoTensorParam_t's currDimensions.\n *\n *   memCount shall be 1.\n *\n *   paddedRank and paddedDimensions are undefined and shall be ignored by the UDO\n *   implementation.\n *\n */\ntypedef struct\n{\n   cl_mem*   mem;\n   uint32_t  memCount;\n   uint32_t  paddedRank;\n   uint32_t* paddedDimensions;\n\n} SnpeUdo_GpuTensorData_t;\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // SNPE_UDO_IMPL_GPU_H\n"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoReg.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef SNPE_UDO_REG_H\n#define SNPE_UDO_REG_H\n\n#include \"SnpeUdo/UdoShared.h\"\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief Initialize the shared library's data structures. Calling any other\n *        library function before this one will result in an error being returned.\n *\n * @return Error code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_initRegLibrary(void);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_InitRegLibraryFunction_t)(void);\n\n/**\n * @brief A function to query the API version of the UDO registration library.\n *        The function populates a SnpeUdo_LibVersion_t struct, which contains a SnpeUdo_Version_t\n *        struct for API version and library version.\n *\n * @param[in, out] version A pointer to struct which contains major, minor, teeny information for\n *                 library and api versions.\n *\n * @return Error code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_getRegLibraryVersion(SnpeUdo_LibVersion_t** version);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_getRegLibraryVersion_t)(SnpeUdo_LibVersion_t** version);\n\n/**\n * @brief Release the shared library's data structures, and invalidate any\n *        handles returned by the library. The behavior of any outstanding\n *        asynchronous calls made to this library when this function is called\n *        are undefined. All library functions (except SnpeUdo_InitRegLibrary) will\n *        return an error after this function has been successfully called.\n *\n *        It should be possible to call SnpeUdo_InitRegLibrary after calling this\n *        function, and re-initialize the library.\n *\n * @return Error code\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_terminateRegLibrary(void);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_TerminateRegLibraryFunction_t)(void);\n\n\n/**\n * @brief A function to query the info on the UDO set.\n *        The function populates a structure which contains information about\n *        the package and operations contained in it.\n *\n * @param[in, out] registrationInfo A struct which contains information on the set of UDOs\n *\n * @return Error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_getRegInfo(SnpeUdo_RegInfo_t** registrationInfo);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_GetRegInfoFunction_t)(SnpeUdo_RegInfo_t** registrationInfo);\n\n/**\n * @brief A function to validate that a set of params is supported by an operation\n *        The function receives an operation definition struct, and returns if this configuration is\n *        supported (e.g. if an operation can be created using this configuration)\n *\n * @param[in] opDefinition A struct of SnpeUdo_OpDefinition type, containing the information needed to\n *            validate that an operation can be created with this configuration.\n *\n * @return Error code, indicating is the operation can be created on this set or not.\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_validateOperation(SnpeUdo_OpDefinition_t* opDefinition);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_ValidateOperationFunction_t)(SnpeUdo_OpDefinition_t* opDefinition);\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n#endif //SNPE_UDO_REG_H\n"
  },
  {
    "path": "phonelibs/snpe/include/SnpeUdo/UdoShared.h",
    "content": "//==============================================================================\n//\n// Copyright (c) 2019-2020 Qualcomm Technologies, Inc.\n// All Rights Reserved.\n// Confidential and Proprietary - Qualcomm Technologies, Inc.\n//\n//==============================================================================\n\n#ifndef SNPE_UDO_SHARED_H\n#define SNPE_UDO_SHARED_H\n\n#include \"SnpeUdo/UdoBase.h\"\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n/** @addtogroup c_plus_plus_apis C++\n@{ */\n\n/**\n * @brief A function to return the various versions as they relate to the UDO\n *        The function returns a struct containing the the following:\n *        libVersion: the version of the implementation library compiled for the UDO. Set by user\n *        apiVersion: the version of the UDO API used in compiling the implementation library.\n *        Set by SNPE\n *\n * @param[in, out] version A pointer to Version struct of type SnpeUdo_LibVersion_t\n *\n * @return Error code\n *\n */\nSnpeUdo_ErrorType_t\nSnpeUdo_getVersion (SnpeUdo_LibVersion_t** version);\n\ntypedef SnpeUdo_ErrorType_t\n(*SnpeUdo_GetVersionFunction_t) (SnpeUdo_LibVersion_t** version);\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n/** @} */ /* end_addtogroup c_plus_plus_apis C++ */\n\n#endif // SNPE_UDO_SHARED_H\n"
  },
  {
    "path": "phonelibs/zlib/build.txt",
    "content": "# with neos tree\ncd ~/android/system\nmka libz\n\ncp ~/android/system/out/target/product/oneplus3/obj/STATIC_LIBRARIES/libz_intermediates/libz.a lib/\n"
  },
  {
    "path": "pyextra/.gitignore",
    "content": "*.pyc\n"
  },
  {
    "path": "rednose/SConscript",
    "content": "Import('env', 'envCython', 'arch', 'rednose_config')\n\ngenerated_folder = rednose_config['generated_folder']\n\ntemplates = Glob('#rednose/templates/*')\n\nsympy_helpers = \"#rednose/helpers/sympy_helpers.py\"\nekf_sym = \"#rednose/helpers/ekf_sym.py\"\nekf_sym_pyx = \"#rednose/helpers/ekf_sym_pyx.pyx\"\nekf_sym_cc = env.Object(\"#rednose/helpers/ekf_sym.cc\")\ncommon_ekf = \"#rednose/helpers/common_ekf.cc\"\n\nfound = {}\nfor target, (command, combined_lib, extra_generated) in rednose_config['to_build'].items():\n  if File(command).exists():\n    found[target] = (command, combined_lib, extra_generated)\n\nlib_target = [common_ekf]\nfor target, (command, combined_lib, extra_generated) in found.items():\n  target_files = File([f'{generated_folder}/{target}.cpp', f'{generated_folder}/{target}.h'])\n  extra_generated = [File(f'{generated_folder}/{x}') for x in extra_generated]\n  command_file = File(command)\n\n  env.Command(target_files + extra_generated,\n              [templates, command_file, sympy_helpers, ekf_sym],\n              command_file.get_abspath() + \" \" + target + \" \" + Dir(generated_folder).get_abspath())\n\n  if combined_lib:\n    lib_target.append(target_files[0])\n  else:\n    env.SharedLibrary(f'{generated_folder}/' + target, [target_files[0], common_ekf])\n\nlibkf = env.SharedLibrary(f'{generated_folder}/libkf', lib_target)\n\nlenv = envCython.Clone()\nlenv[\"LINKFLAGS\"] += [libkf[0].get_labspath()]\nekf_sym_so = lenv.Program('#rednose/helpers/ekf_sym_pyx.so', [ekf_sym_pyx, ekf_sym_cc, common_ekf])\nlenv.Depends(ekf_sym_so, libkf)\n\nExport('libkf')\n"
  },
  {
    "path": "rednose/helpers/__init__.py",
    "content": "import os\nimport platform\nfrom cffi import FFI\n\nTEMPLATE_DIR = os.path.abspath(os.path.join(os.path.dirname(__file__), '..', 'templates'))\n\n\ndef write_code(folder, name, code, header):\n  if not os.path.exists(folder):\n    os.mkdir(folder)\n\n  open(os.path.join(folder, f\"{name}.cpp\"), 'w').write(code)\n  open(os.path.join(folder, f\"{name}.h\"), 'w').write(header)\n\n\ndef load_code(folder, name, lib_name=None):\n  if lib_name is None:\n    lib_name = name\n  shared_ext = \"dylib\" if platform.system() == \"Darwin\" else \"so\"\n  shared_fn = os.path.join(folder, f\"lib{lib_name}.{shared_ext}\")\n  header_fn = os.path.join(folder, f\"{name}.h\")\n\n  with open(header_fn) as f:\n    header = f.read()\n\n  # is the only thing that can be parsed by cffi\n  header = \"\\n\".join([line for line in header.split(\"\\n\") if line.startswith(\"void \")])\n\n  ffi = FFI()\n  ffi.cdef(header)\n  return (ffi, ffi.dlopen(shared_fn))\n\n\nclass KalmanError(Exception):\n  pass\n"
  },
  {
    "path": "rednose/helpers/chi2_lookup.py",
    "content": "import os\n\nimport numpy as np\n\n\ndef gen_chi2_ppf_lookup(max_dim=200):\n  from scipy.stats import chi2\n  table = np.zeros((max_dim, 98))\n  for dim in range(1, max_dim):\n    table[dim] = chi2.ppf(np.arange(.01, .99, .01), dim)\n\n  np.save('chi2_lookup_table', table)\n\n\ndef chi2_ppf(p, dim):\n  table = np.load(os.path.dirname(os.path.realpath(__file__)) + '/chi2_lookup_table.npy')\n  result = np.interp(p, np.arange(.01, .99, .01), table[dim])\n  return result\n\n\nif __name__ == \"__main__\":\n  gen_chi2_ppf_lookup()\n"
  },
  {
    "path": "rednose/helpers/common_ekf.cc",
    "content": "#include \"common_ekf.h\"\n\nstd::vector<const EKF*>& get_ekfs() {\n  static std::vector<const EKF*> vec;\n  return vec;\n}\n\nvoid ekf_register(const EKF* ekf) {\n  get_ekfs().push_back(ekf);\n}\n\nconst EKF* ekf_lookup(const std::string& ekf_name) {\n  for (const auto& ekfi : get_ekfs()) {\n    if (ekf_name == ekfi->name) {\n      return ekfi;\n    }\n  }\n  return NULL;\n}\n"
  },
  {
    "path": "rednose/helpers/common_ekf.h",
    "content": "#pragma once\n\n#include <iostream>\n#include <cassert>\n#include <string>\n#include <vector>\n#include <deque>\n#include <unordered_map>\n#include <map>\n#include <cmath>\n\n#include <eigen3/Eigen/Dense>\n\ntypedef void (*extra_routine_t)(double *, double *);\n\nstruct EKF {\n  std::string name;\n  std::vector<int> kinds;\n  std::vector<int> feature_kinds;\n\n  void (*f_fun)(double *, double, double *);\n  void (*F_fun)(double *, double, double *);\n  void (*err_fun)(double *, double *, double *);\n  void (*inv_err_fun)(double *, double *, double *);\n  void (*H_mod_fun)(double *, double *);\n  void (*predict)(double *, double *, double *, double);\n  std::unordered_map<int, void (*)(double *, double *, double *)> hs = {};\n  std::unordered_map<int, void (*)(double *, double *, double *)> Hs = {};\n  std::unordered_map<int, void (*)(double *, double *, double *, double *, double *)> updates = {};\n  std::unordered_map<int, void (*)(double *, double *, double *)> Hes = {};\n  std::unordered_map<std::string, void (*)(double)> sets = {};\n  std::unordered_map<std::string, extra_routine_t> extra_routines = {};\n};\n\nstd::vector<const EKF*>& get_ekfs();\nconst EKF* ekf_lookup(const std::string& ekf_name);\n\nvoid ekf_register(const EKF* ekf);\n\n#define ekf_init(ekf) \\\nstatic void __attribute__((constructor)) do_ekf_init_ ## ekf(void) { \\\n  ekf_register(&ekf); \\\n}\n"
  },
  {
    "path": "rednose/helpers/ekf_sym.cc",
    "content": "#include \"ekf_sym.h\"\n\nusing namespace EKFS;\nusing namespace Eigen;\n\nEKFSym::EKFSym(std::string name, Map<MatrixXdr> Q, Map<VectorXd> x_initial, Map<MatrixXdr> P_initial, int dim_main,\n    int dim_main_err, int N, int dim_augment, int dim_augment_err, std::vector<int> maha_test_kinds,\n    std::vector<int> quaternion_idxs, std::vector<std::string> global_vars, double max_rewind_age)\n{\n  // TODO: add logger\n\n  this->ekf = ekf_lookup(name);\n  assert(this->ekf);\n\n  this->msckf = N > 0;\n  this->N = N;\n  this->dim_augment = dim_augment;\n  this->dim_augment_err = dim_augment_err;\n  this->dim_main = dim_main;\n  this->dim_main_err = dim_main_err;\n\n  this->dim_x = x_initial.rows();\n  this->dim_err = P_initial.rows();\n\n  assert(dim_main + dim_augment * N == dim_x);\n  assert(dim_main_err + dim_augment_err * N == this->dim_err);\n  assert(Q.rows() == P_initial.rows() && Q.cols() == P_initial.cols());\n\n  // kinds that should get mahalanobis distance\n  // tested for outlier rejection\n  this->maha_test_kinds = maha_test_kinds;\n\n  // quaternions need normalization\n  this->quaternion_idxs = quaternion_idxs;\n\n  this->global_vars = global_vars;\n\n  // Process noise\n  this->Q = Q;\n\n  this->max_rewind_age = max_rewind_age;\n  this->init_state(x_initial, P_initial, NAN);\n}\n\nvoid EKFSym::init_state(Map<VectorXd> state, Map<MatrixXdr> covs, double filter_time) {\n  this->x = state;\n  this->P = covs;\n  this->filter_time = filter_time;\n  this->augment_times = VectorXd::Zero(this->N);\n  this->reset_rewind();\n}\n\nVectorXd EKFSym::state() {\n  return this->x;\n}\n\nMatrixXdr EKFSym::covs() {\n  return this->P;\n}\n\nvoid EKFSym::set_filter_time(double t) {\n  this->filter_time = t;\n}\n\ndouble EKFSym::get_filter_time() {\n  return this->filter_time;\n}\n\nvoid EKFSym::normalize_quaternions() {\n  for(std::size_t i = 0; i < this->quaternion_idxs.size(); ++i) {\n    this->normalize_slice(this->quaternion_idxs[i], this->quaternion_idxs[i] + 4);\n  }\n}\n\nvoid EKFSym::normalize_slice(int slice_start, int slice_end_ex) {\n  this->x.block(slice_start, 0, slice_end_ex - slice_start, this->x.cols()).normalize();\n}\n\nvoid EKFSym::set_global(std::string global_var, double val) {\n  this->ekf->sets.at(global_var)(val);\n}\n\nstd::optional<Estimate> EKFSym::predict_and_update_batch(double t, int kind, std::vector<Map<VectorXd>> z_map,\n    std::vector<Map<MatrixXdr>> R_map, std::vector<std::vector<double>> extra_args, bool augment)\n{\n  // TODO handle rewinding at this level\n\n  std::deque<Observation> rewound;\n  if (!std::isnan(this->filter_time) && t < this->filter_time) {\n    if (this->rewind_t.empty() || t < this->rewind_t.front() || t < this->rewind_t.back() - this->max_rewind_age) {\n      std::cout << \"observation too old at \" << t << \" with filter at \" << this->filter_time << \", ignoring\" << std::endl;\n      return std::nullopt;\n    }\n    rewound = this->rewind(t);\n  }\n\n  Observation obs;\n  obs.t = t;\n  obs.kind = kind;\n  obs.extra_args = extra_args;\n  for (Map<VectorXd> zi : z_map) {\n    obs.z.push_back(zi);\n  }\n  for (Map<MatrixXdr> Ri : R_map) {\n    obs.R.push_back(Ri);\n  }\n\n  std::optional<Estimate> res = std::make_optional(this->predict_and_update_batch(obs, augment));\n\n  // optional fast forward\n  while (!rewound.empty()) {\n    this->predict_and_update_batch(rewound.front(), false);\n    rewound.pop_front();\n  }\n\n  return res;\n}\n\nvoid EKFSym::reset_rewind() {\n  this->rewind_obscache.clear();\n  this->rewind_t.clear();\n  this->rewind_states.clear();\n}\n\nstd::deque<Observation> EKFSym::rewind(double t) {\n  std::deque<Observation> rewound;\n\n  // rewind observations until t is after previous observation\n  while (this->rewind_t.back() > t) {\n    rewound.push_front(this->rewind_obscache.back());\n    this->rewind_t.pop_back();\n    this->rewind_states.pop_back();\n    this->rewind_obscache.pop_back();\n  }\n\n  // set the state to the time right before that\n  this->filter_time = this->rewind_t.back();\n  this->x = this->rewind_states.back().first;\n  this->P = this->rewind_states.back().second;\n\n  return rewound;\n}\n\nvoid EKFSym::checkpoint(Observation& obs) {\n  // push to rewinder\n  this->rewind_t.push_back(this->filter_time);\n  this->rewind_states.push_back(std::make_pair(this->x, this->P));\n  this->rewind_obscache.push_back(obs);\n\n  // only keep a certain number around\n  if (this->rewind_t.size() > REWIND_TO_KEEP) {\n    this->rewind_t.pop_front();\n    this->rewind_states.pop_front();\n    this->rewind_obscache.pop_front();\n  }\n}\n\nEstimate EKFSym::predict_and_update_batch(Observation& obs, bool augment) {\n  assert(obs.z.size() == obs.R.size());\n  assert(obs.z.size() == obs.extra_args.size());\n\n  this->predict(obs.t);\n\n  Estimate res;\n  res.t = obs.t;\n  res.kind = obs.kind;\n  res.z = obs.z;\n  res.extra_args = obs.extra_args;\n  res.xk1 = this->x;\n  res.Pk1 = this->P;\n\n  // update batch\n  std::vector<VectorXd> y;\n  for (int i = 0; i < obs.z.size(); i++) {\n    assert(obs.z[i].rows() == obs.R[i].rows());\n    assert(obs.z[i].rows() == obs.R[i].cols());\n\n    // update state\n    y.push_back(this->update(obs.kind, obs.z[i], obs.R[i], obs.extra_args[i]));\n  }\n\n  res.xk = this->x;\n  res.Pk = this->P;\n  res.y = y;\n\n  assert(!augment); // TODO\n  // if (augment) {\n  //   this->augment();\n  // }\n\n  this->checkpoint(obs);\n\n  return res;\n}\n\nvoid EKFSym::predict(double t) {\n  // initialize time\n  if (std::isnan(this->filter_time)) {\n    this->filter_time = t;\n  }\n\n  // predict\n  double dt = t - this->filter_time;\n  assert(dt >= 0.0);\n\n  this->ekf->predict(this->x.data(), this->P.data(), this->Q.data(), dt);\n  this->normalize_quaternions();\n  this->filter_time = t;\n}\n\nVectorXd EKFSym::update(int kind, VectorXd z, MatrixXdr R, std::vector<double> extra_args) {\n  this->ekf->updates.at(kind)(this->x.data(), this->P.data(), z.data(), R.data(), extra_args.data());\n  this->normalize_quaternions();\n\n  if (this->msckf && std::find(this->feature_track_kinds.begin(), this->feature_track_kinds.end(), kind) != this->feature_track_kinds.end()) {\n    return z.head(z.rows() - extra_args.size());\n  }\n  return z;\n}\n\nextra_routine_t EKFSym::get_extra_routine(const std::string& routine) {\n  return this->ekf->extra_routines.at(routine);\n}\n"
  },
  {
    "path": "rednose/helpers/ekf_sym.h",
    "content": "#pragma once\n\n#include <iostream>\n#include <cassert>\n#include <string>\n#include <vector>\n#include <deque>\n#include <unordered_map>\n#include <map>\n#include <cmath>\n#include <optional>\n\n#include <eigen3/Eigen/Dense>\n\n#include \"common_ekf.h\"\n\n#define REWIND_TO_KEEP 512\n\nnamespace EKFS {\n\ntypedef Eigen::Matrix<double, Eigen::Dynamic, Eigen::Dynamic, Eigen::RowMajor> MatrixXdr;\n\ntypedef struct Observation {\n  double t;\n  int kind;\n  std::vector<Eigen::VectorXd> z;\n  std::vector<MatrixXdr> R;\n  std::vector<std::vector<double>> extra_args;\n} Observation;\n\ntypedef struct Estimate {\n  Eigen::VectorXd xk1;\n  Eigen::VectorXd xk;\n  MatrixXdr Pk1;\n  MatrixXdr Pk;\n  double t;\n  int kind;\n  std::vector<Eigen::VectorXd> y;\n  std::vector<Eigen::VectorXd> z;\n  std::vector<std::vector<double>> extra_args;\n} Estimate;\n\nclass EKFSym {\npublic:\n  EKFSym(std::string name, Eigen::Map<MatrixXdr> Q, Eigen::Map<Eigen::VectorXd> x_initial,\n      Eigen::Map<MatrixXdr> P_initial, int dim_main, int dim_main_err, int N = 0, int dim_augment = 0,\n      int dim_augment_err = 0, std::vector<int> maha_test_kinds = std::vector<int>(),\n      std::vector<int> quaternion_idxs = std::vector<int>(),\n      std::vector<std::string> global_vars = std::vector<std::string>(), double max_rewind_age = 1.0);\n  void init_state(Eigen::Map<Eigen::VectorXd> state, Eigen::Map<MatrixXdr> covs, double filter_time);\n\n  Eigen::VectorXd state();\n  MatrixXdr covs();\n  void set_filter_time(double t);\n  double get_filter_time();\n  void normalize_quaternions();\n  void normalize_slice(int slice_start, int slice_end_ex);\n  void set_global(std::string global_var, double val);\n  void reset_rewind();\n\n  void predict(double t);\n  std::optional<Estimate> predict_and_update_batch(double t, int kind, std::vector<Eigen::Map<Eigen::VectorXd>> z,\n      std::vector<Eigen::Map<MatrixXdr>> R, std::vector<std::vector<double>> extra_args = {{}}, bool augment = false);\n\n  extra_routine_t get_extra_routine(const std::string& routine);\n\nprivate:\n  std::deque<Observation> rewind(double t);\n  void checkpoint(Observation& obs);\n\n  Estimate predict_and_update_batch(Observation& obs, bool augment);\n  Eigen::VectorXd update(int kind, Eigen::VectorXd z, MatrixXdr R, std::vector<double> extra_args);\n\n  // stuct with linked sympy generated functions\n  const EKF *ekf = NULL;\n\n  Eigen::VectorXd x;  // state\n  MatrixXdr P;  // covs\n\n  bool msckf;\n  int N;\n  int dim_augment;\n  int dim_augment_err;\n  int dim_main;\n  int dim_main_err;\n\n  // state\n  int dim_x;\n  int dim_err;\n\n  double filter_time;\n\n  std::vector<int> maha_test_kinds;\n  std::vector<int> quaternion_idxs;\n\n  std::vector<std::string> global_vars;\n\n  // process noise\n  MatrixXdr Q;\n\n  // rewind stuff\n  double max_rewind_age;\n  std::deque<double> rewind_t;\n  std::deque<std::pair<Eigen::VectorXd, MatrixXdr>> rewind_states;\n  std::deque<Observation> rewind_obscache;\n\n  Eigen::VectorXd augment_times;\n\n  std::vector<int> feature_track_kinds;\n};\n\n}\n"
  },
  {
    "path": "rednose/helpers/ekf_sym.py",
    "content": "import os\nimport logging\nfrom bisect import bisect_right\n\nimport numpy as np\nimport sympy as sp\nfrom numpy import dot\n\nfrom rednose.helpers.sympy_helpers import sympy_into_c\nfrom rednose.helpers import TEMPLATE_DIR, load_code\nfrom rednose.helpers.chi2_lookup import chi2_ppf\n\n\ndef solve(a, b):\n  if a.shape[0] == 1 and a.shape[1] == 1:\n    return b / a[0][0]\n  else:\n    return np.linalg.solve(a, b)\n\n\ndef null(H, eps=1e-12):\n  _, s, vh = np.linalg.svd(H)\n  padding = max(0, np.shape(H)[1] - np.shape(s)[0])\n  null_mask = np.concatenate(((s <= eps), np.ones((padding,), dtype=bool)), axis=0)\n  null_space = np.compress(null_mask, vh, axis=0)\n  return np.transpose(null_space)\n\n\ndef gen_code(folder, name, f_sym, dt_sym, x_sym, obs_eqs, dim_x, dim_err, eskf_params=None, msckf_params=None,  # pylint: disable=dangerous-default-value\n             maha_test_kinds=[], quaternion_idxs=[], global_vars=None, extra_routines=[]):\n  # optional state transition matrix, H modifier\n  # and err_function if an error-state kalman filter (ESKF)\n  # is desired. Best described in \"Quaternion kinematics\n  # for the error-state Kalman filter\" by Joan Sola\n\n  if eskf_params:\n    err_eqs = eskf_params[0]\n    inv_err_eqs = eskf_params[1]\n    H_mod_sym = eskf_params[2]\n    f_err_sym = eskf_params[3]\n    x_err_sym = eskf_params[4]\n  else:\n    nom_x = sp.MatrixSymbol('nom_x', dim_x, 1)\n    true_x = sp.MatrixSymbol('true_x', dim_x, 1)\n    delta_x = sp.MatrixSymbol('delta_x', dim_x, 1)\n    err_function_sym = sp.Matrix(nom_x + delta_x)\n    inv_err_function_sym = sp.Matrix(true_x - nom_x)\n    err_eqs = [err_function_sym, nom_x, delta_x]\n    inv_err_eqs = [inv_err_function_sym, nom_x, true_x]\n\n    H_mod_sym = sp.Matrix(np.eye(dim_x))\n    f_err_sym = f_sym\n    x_err_sym = x_sym\n\n  # This configures the multi-state augmentation\n  # needed for EKF-SLAM with MSCKF (Mourikis et al 2007)\n  if msckf_params:\n    msckf = True\n    dim_main = msckf_params[0]      # size of the main state\n    dim_augment = msckf_params[1]   # size of one augment state chunk\n    dim_main_err = msckf_params[2]\n    dim_augment_err = msckf_params[3]\n    N = msckf_params[4]\n    feature_track_kinds = msckf_params[5]\n    assert dim_main + dim_augment * N == dim_x\n    assert dim_main_err + dim_augment_err * N == dim_err\n  else:\n    msckf = False\n    dim_main = dim_x\n    dim_augment = 0\n    dim_main_err = dim_err\n    dim_augment_err = 0\n    N = 0\n\n  # linearize with jacobians\n  F_sym = f_err_sym.jacobian(x_err_sym)\n\n  if eskf_params:\n    for sym in x_err_sym:\n      F_sym = F_sym.subs(sym, 0)\n\n  assert dt_sym in F_sym.free_symbols\n\n  for i in range(len(obs_eqs)):\n    obs_eqs[i].append(obs_eqs[i][0].jacobian(x_sym))\n    if msckf and obs_eqs[i][1] in feature_track_kinds:\n      obs_eqs[i].append(obs_eqs[i][0].jacobian(obs_eqs[i][2]))\n    else:\n      obs_eqs[i].append(None)\n\n  # collect sympy functions\n  sympy_functions = []\n\n  # extra routines\n  sympy_functions += extra_routines\n\n  # error functions\n  sympy_functions.append(('err_fun', err_eqs[0], [err_eqs[1], err_eqs[2]]))\n  sympy_functions.append(('inv_err_fun', inv_err_eqs[0], [inv_err_eqs[1], inv_err_eqs[2]]))\n\n  # H modifier for ESKF updates\n  sympy_functions.append(('H_mod_fun', H_mod_sym, [x_sym]))\n\n  # state propagation function\n  sympy_functions.append(('f_fun', f_sym, [x_sym, dt_sym]))\n  sympy_functions.append(('F_fun', F_sym, [x_sym, dt_sym]))\n\n  # observation functions\n  for h_sym, kind, ea_sym, H_sym, He_sym in obs_eqs:\n    sympy_functions.append(('h_%d' % kind, h_sym, [x_sym, ea_sym]))\n    sympy_functions.append(('H_%d' % kind, H_sym, [x_sym, ea_sym]))\n    if msckf and kind in feature_track_kinds:\n      sympy_functions.append(('He_%d' % kind, He_sym, [x_sym, ea_sym]))\n\n  # Generate and wrap all th c code\n  sympy_header, code = sympy_into_c(sympy_functions, global_vars)\n\n  header = \"#pragma once\\n\"\n  header += \"#include \\\"rednose/helpers/common_ekf.h\\\"\\n\"\n  header += \"extern \\\"C\\\" {\\n\"\n\n  pre_code = f\"#include \\\"{name}.h\\\"\\n\"\n  pre_code += \"\\nnamespace {\\n\"\n  pre_code += \"#define DIM %d\\n\" % dim_x\n  pre_code += \"#define EDIM %d\\n\" % dim_err\n  pre_code += \"#define MEDIM %d\\n\" % dim_main_err\n  pre_code += \"typedef void (*Hfun)(double *, double *, double *);\\n\"\n\n  if global_vars is not None:\n    for var in global_vars:\n      pre_code += f\"\\ndouble {var.name};\\n\"\n      pre_code += f\"\\nvoid set_{var.name}(double x){{ {var.name} = x;}}\\n\"\n\n  post_code = \"\\n}\\n\" # namespace\n  post_code += \"extern \\\"C\\\" {\\n\\n\"\n\n  for h_sym, kind, ea_sym, H_sym, He_sym in obs_eqs:\n    if msckf and kind in feature_track_kinds:\n      He_str = 'He_%d' % kind\n      # ea_dim = ea_sym.shape[0]\n    else:\n      He_str = 'NULL'\n      # ea_dim = 1 # not really dim of ea but makes c function work\n    maha_thresh = chi2_ppf(0.95, int(h_sym.shape[0]))  # mahalanobis distance for outlier detection\n    maha_test = kind in maha_test_kinds\n\n    pre_code += f\"const static double MAHA_THRESH_{kind} = {maha_thresh};\\n\"\n\n    header += f\"void {name}_update_{kind}(double *in_x, double *in_P, double *in_z, double *in_R, double *in_ea);\\n\"\n    post_code += f\"void {name}_update_{kind}(double *in_x, double *in_P, double *in_z, double *in_R, double *in_ea) {{\\n\"\n    post_code += f\"  update<{h_sym.shape[0]}, 3, {int(maha_test)}>(in_x, in_P, h_{kind}, H_{kind}, {He_str}, in_z, in_R, in_ea, MAHA_THRESH_{kind});\\n\"\n    post_code += \"}\\n\"\n\n  # For ffi loading of specific functions\n  for line in sympy_header.split(\"\\n\"):\n    if line.startswith(\"void \"):  # sympy functions\n      func_call = line[5: line.index(')') + 1]\n      header += f\"void {name}_{func_call};\\n\"\n      post_code += f\"void {name}_{func_call} {{\\n\"\n      post_code += f\"  {func_call.replace('double *', '').replace('double', '')};\\n\"\n      post_code += \"}\\n\"\n  header += f\"void {name}_predict(double *in_x, double *in_P, double *in_Q, double dt);\\n\"\n  post_code += f\"void {name}_predict(double *in_x, double *in_P, double *in_Q, double dt) {{\\n\"\n  post_code += \"  predict(in_x, in_P, in_Q, dt);\\n\"\n  post_code += \"}\\n\"\n  if global_vars is not None:\n    for var in global_vars:\n      header += f\"void {name}_set_{var.name}(double x);\\n\"\n      post_code += f\"void {name}_set_{var.name}(double x) {{\\n\"\n      post_code += f\"  set_{var.name}(x);\\n\"\n      post_code += \"}\\n\"\n\n  post_code += \"}\\n\\n\" # extern c\n\n  funcs = ['f_fun', 'F_fun', 'err_fun', 'inv_err_fun', 'H_mod_fun', 'predict']\n  func_lists = {\n    'h': [kind for _, kind, _, _, _ in obs_eqs],\n    'H': [kind for _, kind, _, _, _ in obs_eqs],\n    'update': [kind for _, kind, _, _, _ in obs_eqs],\n    'He': [kind for _, kind, _, _, _ in obs_eqs if msckf and kind in feature_track_kinds],\n    'set': [var.name for var in global_vars] if global_vars is not None else [],\n  }\n  func_extra = [x[0] for x in extra_routines]\n\n  # For dynamic loading of specific functions\n  post_code += f\"const EKF {name} = {{\\n\"\n  post_code += f\"  .name = \\\"{name}\\\",\\n\"\n  post_code += f\"  .kinds = {{ {', '.join([str(kind) for _, kind, _, _, _ in obs_eqs])} }},\\n\"\n  post_code += f\"  .feature_kinds = {{ {', '.join([str(kind) for _, kind, _, _, _ in obs_eqs if msckf and kind in feature_track_kinds])} }},\\n\"\n  for func in funcs:\n    post_code += f\"  .{func} = {name}_{func},\\n\"\n  for group, kinds in func_lists.items():\n    post_code += f\"  .{group}s = {{\\n\"\n    for kind in kinds:\n      str_kind = f\"\\\"{kind}\\\"\" if type(kind) == str else kind\n      post_code += f\"    {{ {str_kind}, {name}_{group}_{kind} }},\\n\"\n    post_code += \"  },\\n\"\n  post_code += \"  .extra_routines = {\\n\"\n  for f in func_extra:\n    post_code += f\"    {{ \\\"{f}\\\", {name}_{f} }},\\n\"\n  post_code += \"  },\\n\"\n  post_code += \"};\\n\\n\"\n  post_code += f\"ekf_init({name});\\n\"\n\n  # merge code blocks\n  header += \"}\"\n  code = \"\\n\".join([pre_code, code, open(os.path.join(TEMPLATE_DIR, \"ekf_c.c\")).read(), post_code])\n\n  # write to file\n  if not os.path.exists(folder):\n    os.mkdir(folder)\n\n  open(os.path.join(folder, f\"{name}.h\"), 'w').write(header)  # header is used for ffi import\n  open(os.path.join(folder, f\"{name}.cpp\"), 'w').write(code)\n\n\nclass EKF_sym():\n  def __init__(self, folder, name, Q, x_initial, P_initial, dim_main, dim_main_err,  # pylint: disable=dangerous-default-value\n               N=0, dim_augment=0, dim_augment_err=0, maha_test_kinds=[], quaternion_idxs=[], global_vars=None, max_rewind_age=1.0, logger=logging):\n    \"\"\"Generates process function and all observation functions for the kalman filter.\"\"\"\n    self.msckf = N > 0\n    self.N = N\n    self.dim_augment = dim_augment\n    self.dim_augment_err = dim_augment_err\n    self.dim_main = dim_main\n    self.dim_main_err = dim_main_err\n\n    self.logger = logger\n\n    # state\n    x_initial = x_initial.reshape((-1, 1))\n    self.dim_x = x_initial.shape[0]\n    self.dim_err = P_initial.shape[0]\n    assert dim_main + dim_augment * N == self.dim_x\n    assert dim_main_err + dim_augment_err * N == self.dim_err\n    assert Q.shape == P_initial.shape\n\n    # kinds that should get mahalanobis distance\n    # tested for outlier rejection\n    self.maha_test_kinds = maha_test_kinds\n\n    # quaternions need normalization\n    self.quaternion_idxs = quaternion_idxs\n\n    # process noise\n    self.Q = Q\n\n    # rewind stuff\n    self.max_rewind_age = max_rewind_age\n    self.rewind_t = []\n    self.rewind_states = []\n    self.rewind_obscache = []\n    self.init_state(x_initial, P_initial, None)\n\n    ffi, lib = load_code(folder, name, \"kf\")\n    kinds, self.feature_track_kinds = [], []\n    for func in dir(lib):\n      if func[:len(name) + 3] == f'{name}_h_':\n        kinds.append(int(func[len(name) + 3:]))\n      if func[:len(name) + 4] == f'{name}_He_':\n        self.feature_track_kinds.append(int(func[len(name) + 4:]))\n\n    # wrap all the sympy functions\n    def wrap_1lists(func_name):\n      func = eval(f\"lib.{name}_{func_name}\", {\"lib\": lib})  # pylint: disable=eval-used\n\n      def ret(lst1, out):\n        func(ffi.cast(\"double *\", lst1.ctypes.data),\n             ffi.cast(\"double *\", out.ctypes.data))\n      return ret\n\n    def wrap_2lists(func_name):\n      func = eval(f\"lib.{name}_{func_name}\", {\"lib\": lib})  # pylint: disable=eval-used\n\n      def ret(lst1, lst2, out):\n        func(ffi.cast(\"double *\", lst1.ctypes.data),\n             ffi.cast(\"double *\", lst2.ctypes.data),\n             ffi.cast(\"double *\", out.ctypes.data))\n      return ret\n\n    def wrap_1list_1float(func_name):\n      func = eval(f\"lib.{name}_{func_name}\", {\"lib\": lib})  # pylint: disable=eval-used\n\n      def ret(lst1, fl, out):\n        func(ffi.cast(\"double *\", lst1.ctypes.data),\n             ffi.cast(\"double\", fl),\n             ffi.cast(\"double *\", out.ctypes.data))\n      return ret\n\n    self.f = wrap_1list_1float(\"f_fun\")\n    self.F = wrap_1list_1float(\"F_fun\")\n\n    self.err_function = wrap_2lists(\"err_fun\")\n    self.inv_err_function = wrap_2lists(\"inv_err_fun\")\n    self.H_mod = wrap_1lists(\"H_mod_fun\")\n\n    self.hs, self.Hs, self.Hes = {}, {}, {}\n    for kind in kinds:\n      self.hs[kind] = wrap_2lists(f\"h_{kind}\")\n      self.Hs[kind] = wrap_2lists(f\"H_{kind}\")\n      if self.msckf and kind in self.feature_track_kinds:\n        self.Hes[kind] = wrap_2lists(f\"He_{kind}\")\n\n    self.set_globals = {}\n    if global_vars is not None:\n      for global_var in global_vars:\n        self.set_globals[global_var] = getattr(lib, f\"{name}_set_{global_var}\")\n\n    # wrap the C++ predict function\n    def _predict_blas(x, P, dt):\n      func = eval(f\"lib.{name}_predict\", {\"lib\": lib})  # pylint: disable=eval-used\n      func(ffi.cast(\"double *\", x.ctypes.data),\n           ffi.cast(\"double *\", P.ctypes.data),\n           ffi.cast(\"double *\", self.Q.ctypes.data),\n           ffi.cast(\"double\", dt))\n      return x, P\n\n    # wrap the C++ update function\n    def fun_wrapper(f, kind):\n      f = eval(f\"lib.{name}_{f}\", {\"lib\": lib})  # pylint: disable=eval-used\n\n      def _update_inner_blas(x, P, z, R, extra_args):\n        f(ffi.cast(\"double *\", x.ctypes.data),\n          ffi.cast(\"double *\", P.ctypes.data),\n          ffi.cast(\"double *\", z.ctypes.data),\n          ffi.cast(\"double *\", R.ctypes.data),\n          ffi.cast(\"double *\", extra_args.ctypes.data))\n        if self.msckf and kind in self.feature_track_kinds:\n          y = z[:-len(extra_args)]\n        else:\n          y = z\n        return x, P, y\n      return _update_inner_blas\n\n    self._updates = {}\n    for kind in kinds:\n      self._updates[kind] = fun_wrapper(\"update_%d\" % kind, kind)\n\n    def _update_blas(x, P, kind, z, R, extra_args=[]):  # pylint: disable=dangerous-default-value\n        return self._updates[kind](x, P, z, R, extra_args)\n\n    # assign the functions\n    self._predict = _predict_blas\n    # self._predict = self._predict_python\n    self._update = _update_blas\n    # self._update = self._update_python\n\n  def init_state(self, state, covs, filter_time):\n    self.x = np.array(state.reshape((-1, 1))).astype(np.float64)\n    self.P = np.array(covs).astype(np.float64)\n    self.filter_time = filter_time\n    self.augment_times = [0] * self.N\n    self.rewind_obscache = []\n    self.rewind_t = []\n    self.rewind_states = []\n\n  def reset_rewind(self):\n    self.rewind_obscache = []\n    self.rewind_t = []\n    self.rewind_states = []\n\n  def augment(self):\n    # TODO this is not a generalized way of doing this and implies that the augmented states\n    # are simply the first (dim_augment_state) elements of the main state.\n    assert self.msckf\n    d1 = self.dim_main\n    d2 = self.dim_main_err\n    d3 = self.dim_augment\n    d4 = self.dim_augment_err\n\n    # push through augmented states\n    self.x[d1:-d3] = self.x[d1 + d3:]\n    self.x[-d3:] = self.x[:d3]\n    assert self.x.shape == (self.dim_x, 1)\n\n    # push through augmented covs\n    assert self.P.shape == (self.dim_err, self.dim_err)\n    P_reduced = self.P\n    P_reduced = np.delete(P_reduced, np.s_[d2:d2 + d4], axis=1)\n    P_reduced = np.delete(P_reduced, np.s_[d2:d2 + d4], axis=0)\n    assert P_reduced.shape == (self.dim_err - d4, self.dim_err - d4)\n    to_mult = np.zeros((self.dim_err, self.dim_err - d4))\n    to_mult[:-d4, :] = np.eye(self.dim_err - d4)\n    to_mult[-d4:, :d4] = np.eye(d4)\n    self.P = to_mult.dot(P_reduced.dot(to_mult.T))\n    self.augment_times = self.augment_times[1:]\n    self.augment_times.append(self.filter_time)\n    assert self.P.shape == (self.dim_err, self.dim_err)\n\n  def state(self):\n    return np.array(self.x).flatten()\n\n  def covs(self):\n    return self.P\n\n  def set_filter_time(self, t):\n    self.filter_time = t\n\n  def get_filter_time(self):\n    return self.filter_time\n\n  def normalize_quaternions(self):\n    for idx in self.quaternion_idxs:\n      self.normalize_slice(idx, idx+4)\n\n  def normalize_slice(self, slice_start, slice_end_ex):\n    self.x[slice_start:slice_end_ex] /= np.linalg.norm(self.x[slice_start:slice_end_ex])\n\n  def get_augment_times(self):\n    return self.augment_times\n\n  def set_global(self, global_var, val):\n    self.set_globals[global_var](val)\n\n  def rewind(self, t):\n    # find where we are rewinding to\n    idx = bisect_right(self.rewind_t, t)\n    assert self.rewind_t[idx - 1] <= t\n    assert self.rewind_t[idx] > t    # must be true, or rewind wouldn't be called\n\n    # set the state to the time right before that\n    self.filter_time = self.rewind_t[idx - 1]\n    self.x[:] = self.rewind_states[idx - 1][0]\n    self.P[:] = self.rewind_states[idx - 1][1]\n\n    # return the observations we rewound over for fast forwarding\n    ret = self.rewind_obscache[idx:]\n\n    # throw away the old future\n    # TODO: is this making a copy?\n    self.rewind_t = self.rewind_t[:idx]\n    self.rewind_states = self.rewind_states[:idx]\n    self.rewind_obscache = self.rewind_obscache[:idx]\n\n    return ret\n\n  def checkpoint(self, obs):\n    # push to rewinder\n    self.rewind_t.append(self.filter_time)\n    self.rewind_states.append((np.copy(self.x), np.copy(self.P)))\n    self.rewind_obscache.append(obs)\n\n    # only keep a certain number around\n    REWIND_TO_KEEP = 512\n    self.rewind_t = self.rewind_t[-REWIND_TO_KEEP:]\n    self.rewind_states = self.rewind_states[-REWIND_TO_KEEP:]\n    self.rewind_obscache = self.rewind_obscache[-REWIND_TO_KEEP:]\n\n  def predict(self, t):\n    # initialize time\n    if self.filter_time is None:\n      self.filter_time = t\n\n    # predict\n    dt = t - self.filter_time\n    assert dt >= 0\n    self.x, self.P = self._predict(self.x, self.P, dt)\n    self.normalize_quaternions()\n    self.filter_time = t\n\n  def predict_and_update_batch(self, t, kind, z, R, extra_args=[[]], augment=False):  # pylint: disable=dangerous-default-value\n    # TODO handle rewinding at this level\"\n\n    # rewind\n    if self.filter_time is not None and t < self.filter_time:\n      if len(self.rewind_t) == 0 or t < self.rewind_t[0] or t < self.rewind_t[-1] - self.max_rewind_age:\n        self.logger.error(\"observation too old at %.3f with filter at %.3f, ignoring\" % (t, self.filter_time))\n        return None\n      rewound = self.rewind(t)\n    else:\n      rewound = []\n\n    ret = self._predict_and_update_batch(t, kind, z, R, extra_args, augment)\n\n    # optional fast forward\n    for r in rewound:\n      self._predict_and_update_batch(*r)\n\n    return ret\n\n  def _predict_and_update_batch(self, t, kind, z, R, extra_args, augment=False):\n    \"\"\"The main kalman filter function\n    Predicts the state and then updates a batch of observations\n    dim_x: dimensionality of the state space\n    dim_z: dimensionality of the observation and depends on kind\n    n: number of observations\n    Args:\n      t                 (float): Time of observation\n      kind                (int): Type of observation\n      z         (vec [n,dim_z]): Measurements\n      R  (mat [n,dim_z, dim_z]): Measurement Noise\n      extra_args    (list, [n]): Values used in H computations\n    \"\"\"\n    assert z.shape[0] == R.shape[0]\n    assert z.shape[1] == R.shape[1]\n    assert z.shape[1] == R.shape[2]\n\n    # initialize time\n    if self.filter_time is None:\n      self.filter_time = t\n\n    # predict\n    dt = t - self.filter_time\n    assert dt >= 0\n    self.x, self.P = self._predict(self.x, self.P, dt)\n    self.filter_time = t\n    xk_km1, Pk_km1 = np.copy(self.x).flatten(), np.copy(self.P)\n\n    # update batch\n    y = []\n    for i in range(len(z)):\n      # these are from the user, so we canonicalize them\n      z_i = np.array(z[i], dtype=np.float64, order='F')\n      R_i = np.array(R[i], dtype=np.float64, order='F')\n      extra_args_i = np.array(extra_args[i], dtype=np.float64, order='F')\n      # update\n      self.x, self.P, y_i = self._update(self.x, self.P, kind, z_i, R_i, extra_args=extra_args_i)\n      self.normalize_quaternions()\n      y.append(y_i)\n    xk_k, Pk_k = np.copy(self.x).flatten(), np.copy(self.P)\n\n    if augment:\n      self.augment()\n\n    # checkpoint\n    self.checkpoint((t, kind, z, R, extra_args))\n\n    return xk_km1, xk_k, Pk_km1, Pk_k, t, kind, y, z, extra_args\n\n  def _predict_python(self, x, P, dt):\n    x_new = np.zeros(x.shape, dtype=np.float64)\n    self.f(x, dt, x_new)\n\n    F = np.zeros(P.shape, dtype=np.float64)\n    self.F(x, dt, F)\n\n    if not self.msckf:\n      P = dot(dot(F, P), F.T)\n    else:\n      # Update the predicted state covariance:\n      #  Pk+1|k   =  |F*Pii*FT + Q*dt   F*Pij |\n      #              |PijT*FT           Pjj   |\n      # Where F is the jacobian of the main state\n      # predict function, Pii is the main state's\n      # covariance and Q its process noise. Pij\n      # is the covariance between the augmented\n      # states and the main state.\n      #\n      d2 = self.dim_main_err    # known at compile time\n      F_curr = F[:d2, :d2]\n      P[:d2, :d2] = (F_curr.dot(P[:d2, :d2])).dot(F_curr.T)\n      P[:d2, d2:] = F_curr.dot(P[:d2, d2:])\n      P[d2:, :d2] = P[d2:, :d2].dot(F_curr.T)\n\n    P += dt * self.Q\n    return x_new, P\n\n  def _update_python(self, x, P, kind, z, R, extra_args=[]):  # pylint: disable=dangerous-default-value\n    # init vars\n    z = z.reshape((-1, 1))\n    h = np.zeros(z.shape, dtype=np.float64)\n    H = np.zeros((z.shape[0], self.dim_x), dtype=np.float64)\n\n    # C functions\n    self.hs[kind](x, extra_args, h)\n    self.Hs[kind](x, extra_args, H)\n\n    # y is the \"loss\"\n    y = z - h\n\n    # *** same above this line ***\n\n    if self.msckf and kind in self.Hes:\n      # Do some algebraic magic to decorrelate\n      He = np.zeros((z.shape[0], len(extra_args)), dtype=np.float64)\n      self.Hes[kind](x, extra_args, He)\n\n      # TODO: Don't call a function here, do projection locally\n      A = null(He.T)\n\n      y = A.T.dot(y)\n      H = A.T.dot(H)\n      R = A.T.dot(R.dot(A))\n\n      # TODO If nullspace isn't the dimension we want\n      if A.shape[1] + He.shape[1] != A.shape[0]:\n        self.logger.warning('Warning: null space projection failed, measurement ignored')\n        return x, P, np.zeros(A.shape[0] - He.shape[1])\n\n    # if using eskf\n    H_mod = np.zeros((x.shape[0], P.shape[0]), dtype=np.float64)\n    self.H_mod(x, H_mod)\n    H = H.dot(H_mod)\n\n    # Do mahalobis distance test\n    # currently just runs on msckf observations\n    # could run on anything if needed\n    if self.msckf and kind in self.maha_test_kinds:\n      a = np.linalg.inv(H.dot(P).dot(H.T) + R)\n      maha_dist = y.T.dot(a.dot(y))\n      if maha_dist > chi2_ppf(0.95, y.shape[0]):\n        R = 10e16 * R\n\n    # *** same below this line ***\n\n    # Outlier resilient weighting as described in:\n    # \"A Kalman Filter for Robust Outlier Detection - Jo-Anne Ting, ...\"\n    weight = 1  # (1.5)/(1 + np.sum(y**2)/np.sum(R))\n\n    S = dot(dot(H, P), H.T) + R / weight\n    K = solve(S, dot(H, P.T)).T\n    I_KH = np.eye(P.shape[0]) - dot(K, H)\n\n    # update actual state\n    delta_x = dot(K, y)\n    P = dot(dot(I_KH, P), I_KH.T) + dot(dot(K, R), K.T)\n\n    # inject observed error into state\n    x_new = np.zeros(x.shape, dtype=np.float64)\n    self.err_function(x, delta_x, x_new)\n    return x_new, P, y.flatten()\n\n  def maha_test(self, x, P, kind, z, R, extra_args=[], maha_thresh=0.95):  # pylint: disable=dangerous-default-value\n    # init vars\n    z = z.reshape((-1, 1))\n    h = np.zeros(z.shape, dtype=np.float64)\n    H = np.zeros((z.shape[0], self.dim_x), dtype=np.float64)\n\n    # C functions\n    self.hs[kind](x, extra_args, h)\n    self.Hs[kind](x, extra_args, H)\n\n    # y is the \"loss\"\n    y = z - h\n\n    # if using eskf\n    H_mod = np.zeros((x.shape[0], P.shape[0]), dtype=np.float64)\n    self.H_mod(x, H_mod)\n    H = H.dot(H_mod)\n\n    a = np.linalg.inv(H.dot(P).dot(H.T) + R)\n    maha_dist = y.T.dot(a.dot(y))\n    if maha_dist > chi2_ppf(maha_thresh, y.shape[0]):\n      return False\n    else:\n      return True\n\n  def rts_smooth(self, estimates, norm_quats=False):\n    '''\n    Returns rts smoothed results of\n    kalman filter estimates\n    If the kalman state is augmented with\n    old states only the main state is smoothed\n    '''\n    xk_n = estimates[-1][0]\n    Pk_n = estimates[-1][2]\n    Fk_1 = np.zeros(Pk_n.shape, dtype=np.float64)\n\n    states_smoothed = [xk_n]\n    covs_smoothed = [Pk_n]\n    for k in range(len(estimates) - 2, -1, -1):\n      xk1_n = xk_n\n      if norm_quats:\n        xk1_n[3:7] /= np.linalg.norm(xk1_n[3:7])\n      Pk1_n = Pk_n\n\n      xk1_k, _, Pk1_k, _, t2, _, _, _, _ = estimates[k + 1]\n      _, xk_k, _, Pk_k, t1, _, _, _, _ = estimates[k]\n      dt = t2 - t1\n      self.F(xk_k, dt, Fk_1)\n\n      d1 = self.dim_main\n      d2 = self.dim_main_err\n      Ck = np.linalg.solve(Pk1_k[:d2, :d2], Fk_1[:d2, :d2].dot(Pk_k[:d2, :d2].T)).T\n      xk_n = xk_k\n      delta_x = np.zeros((Pk_n.shape[0], 1), dtype=np.float64)\n      self.inv_err_function(xk1_k, xk1_n, delta_x)\n      delta_x[:d2] = Ck.dot(delta_x[:d2])\n      x_new = np.zeros((xk_n.shape[0], 1), dtype=np.float64)\n      self.err_function(xk_k, delta_x, x_new)\n      xk_n[:d1] = x_new[:d1, 0]\n      Pk_n = Pk_k\n      Pk_n[:d2, :d2] = Pk_k[:d2, :d2] + Ck.dot(Pk1_n[:d2, :d2] - Pk1_k[:d2, :d2]).dot(Ck.T)\n      states_smoothed.append(xk_n)\n      covs_smoothed.append(Pk_n)\n\n    return np.flipud(np.vstack(states_smoothed)), np.stack(covs_smoothed, 0)[::-1]\n"
  },
  {
    "path": "rednose/helpers/ekf_sym_pyx.pyx",
    "content": "# cython: language_level=3\n# cython: profile=True\n# distutils: language = c++\n\ncimport cython\n\nfrom libcpp.string cimport string\nfrom libcpp.vector cimport vector\nfrom libcpp cimport bool\ncimport numpy as np\n\nimport numpy as np\n\ncdef extern from \"<optional>\" namespace \"std\" nogil:\n  cdef cppclass optional[T]:\n    ctypedef T value_type\n    bool has_value()\n    T& value()\n\ncdef extern from \"rednose/helpers/ekf_sym.h\" namespace \"EKFS\":\n  cdef cppclass MapVectorXd \"Eigen::Map<Eigen::VectorXd>\":\n    MapVectorXd(double*, int)\n\n  cdef cppclass MapMatrixXdr \"Eigen::Map<Eigen::Matrix<double, Eigen::Dynamic, Eigen::Dynamic, Eigen::RowMajor> >\":\n    MapMatrixXdr(double*, int, int)\n\n  cdef cppclass VectorXd \"Eigen::VectorXd\":\n    VectorXd()\n    double* data()\n    int rows()\n\n  cdef cppclass MatrixXdr \"Eigen::Matrix<double, Eigen::Dynamic, Eigen::Dynamic, Eigen::RowMajor>\":\n    MatrixXdr()\n    double* data()\n    int rows()\n    int cols()\n\n  ctypedef struct Estimate:\n    VectorXd xk1\n    VectorXd xk\n    MatrixXdr Pk1\n    MatrixXdr Pk\n    double t\n    int kind\n    vector[VectorXd] y\n    vector[VectorXd] z\n    vector[vector[double]] extra_args\n\n  cdef cppclass EKFSym:\n    EKFSym(string name, MapMatrixXdr Q, MapVectorXd x_initial, MapMatrixXdr P_initial, int dim_main,\n        int dim_main_err, int N, int dim_augment, int dim_augment_err, vector[int] maha_test_kinds,\n        vector[int] quaternion_idxs, vector[string] global_vars, double max_rewind_age)\n    void init_state(MapVectorXd state, MapMatrixXdr covs, double filter_time)\n\n    VectorXd state()\n    MatrixXdr covs()\n    void set_filter_time(double t)\n    double get_filter_time()\n    void set_global(string name, double val)\n    void reset_rewind()\n\n    void predict(double t)\n    optional[Estimate] predict_and_update_batch(double t, int kind, vector[MapVectorXd] z, vector[MapMatrixXdr] z,\n        vector[vector[double]] extra_args, bool augment)\n\n# Functions like `numpy_to_matrix` are not possible, cython requires default\n# constructor for return variable types which aren't available with Eigen::Map\n\n@cython.wraparound(False)\n@cython.boundscheck(False)\ncdef np.ndarray[np.float64_t, ndim=2, mode=\"c\"] matrix_to_numpy(MatrixXdr arr):\n  cdef double[:,:] mem_view = <double[:arr.rows(),:arr.cols()]>arr.data()\n  return np.copy(np.asarray(mem_view, dtype=np.double, order=\"C\"))\n\n@cython.wraparound(False)\n@cython.boundscheck(False)\ncdef np.ndarray[np.float64_t, ndim=1, mode=\"c\"] vector_to_numpy(VectorXd arr):\n  cdef double[:] mem_view = <double[:arr.rows()]>arr.data()\n  return np.copy(np.asarray(mem_view, dtype=np.double, order=\"C\"))\n\ncdef class EKF_sym:\n  cdef EKFSym* ekf\n  def __cinit__(self, str gen_dir, str name, np.ndarray[np.float64_t, ndim=2] Q,\n      np.ndarray[np.float64_t, ndim=1] x_initial, np.ndarray[np.float64_t, ndim=2] P_initial, int dim_main,\n      int dim_main_err, int N=0, int dim_augment=0, int dim_augment_err=0, list maha_test_kinds=[],\n      list quaternion_idxs=[], list global_vars=[], double max_rewind_age=1.0, logger=None):\n    # TODO logger\n\n    cdef np.ndarray[np.float64_t, ndim=2, mode='c'] Q_b = np.ascontiguousarray(Q, dtype=np.double)\n    cdef np.ndarray[np.float64_t, ndim=1, mode='c'] x_initial_b = np.ascontiguousarray(x_initial, dtype=np.double)\n    cdef np.ndarray[np.float64_t, ndim=2, mode='c'] P_initial_b = np.ascontiguousarray(P_initial, dtype=np.double)\n    self.ekf = new EKFSym(\n      name.encode('utf8'),\n      MapMatrixXdr(<double*> Q_b.data, Q.shape[0], Q.shape[1]),\n      MapVectorXd(<double*> x_initial_b.data, x_initial.shape[0]),\n      MapMatrixXdr(<double*> P_initial_b.data, P_initial.shape[0], P_initial.shape[1]),\n      dim_main,\n      dim_main_err,\n      N,\n      dim_augment,\n      dim_augment_err,\n      maha_test_kinds,\n      quaternion_idxs,\n      [x.encode('utf8') for x in global_vars],\n      max_rewind_age\n    )\n\n  def init_state(self, np.ndarray[np.float64_t, ndim=1] state, np.ndarray[np.float64_t, ndim=2] covs, filter_time):\n    cdef np.ndarray[np.float64_t, ndim=1, mode='c'] state_b = np.ascontiguousarray(state, dtype=np.double)\n    cdef np.ndarray[np.float64_t, ndim=2, mode='c'] covs_b = np.ascontiguousarray(covs, dtype=np.double)\n    self.ekf.init_state(\n      MapVectorXd(<double*> state_b.data, state.shape[0]),\n      MapMatrixXdr(<double*> covs_b.data, covs.shape[0], covs.shape[1]),\n      np.nan if filter_time is None else filter_time\n    )\n\n  def state(self):\n    cdef np.ndarray res = vector_to_numpy(self.ekf.state())\n    return res\n\n  def covs(self):\n    return matrix_to_numpy(self.ekf.covs())\n\n  def set_filter_time(self, double t):\n    self.ekf.set_filter_time(t)\n\n  def get_filter_time(self):\n    return self.ekf.get_filter_time()\n\n  def set_global(self, str global_var, double val):\n    self.ekf.set_global(global_var.encode('utf8'), val)\n\n  def reset_rewind(self):\n    self.ekf.reset_rewind()\n\n  def predict(self, double t):\n    self.ekf.predict(t)\n\n  def predict_and_update_batch(self, double t, int kind, z, R, extra_args=[[]], bool augment=False):\n    cdef vector[MapVectorXd] z_map\n    cdef np.ndarray[np.float64_t, ndim=1, mode='c'] zi_b\n    for zi in z:\n      zi_b = np.ascontiguousarray(zi, dtype=np.double)\n      z_map.push_back(MapVectorXd(<double*> zi_b.data, zi.shape[0]))\n\n    cdef vector[MapMatrixXdr] R_map\n    cdef np.ndarray[np.float64_t, ndim=2, mode='c'] Ri_b\n    for Ri in R:\n      Ri_b = np.ascontiguousarray(Ri, dtype=np.double)\n      R_map.push_back(MapMatrixXdr(<double*> Ri_b.data, Ri.shape[0], Ri.shape[1]))\n\n    cdef vector[vector[double]] extra_args_map\n    cdef vector[double] args_map\n    for args in extra_args:\n      args_map.clear()\n      for a in args:\n        args_map.push_back(a)\n      extra_args_map.push_back(args_map)\n\n    cdef optional[Estimate] res = self.ekf.predict_and_update_batch(t, kind, z_map, R_map, extra_args_map, augment)\n    if not res.has_value():\n      return None\n\n    cdef VectorXd tmpvec\n    return (\n      vector_to_numpy(res.value().xk1),\n      vector_to_numpy(res.value().xk),\n      matrix_to_numpy(res.value().Pk1),\n      matrix_to_numpy(res.value().Pk),\n      res.value().t,\n      res.value().kind,\n      [vector_to_numpy(tmpvec) for tmpvec in res.value().y],\n      z,  # TODO: take return values?\n      extra_args,\n    )\n\n  def augment(self):\n    raise NotImplementedError()  # TODO\n\n  def get_augment_times(self):\n    raise NotImplementedError()  # TODO\n\n  def rts_smooth(self, estimates, norm_quats=False):\n    raise NotImplementedError()  # TODO\n\n  def maha_test(self, x, P, kind, z, R, extra_args=[], maha_thresh=0.95):\n    raise NotImplementedError()  # TODO\n\n  def __dealloc__(self):\n    del self.ekf\n"
  },
  {
    "path": "rednose/helpers/feature_handler.py",
    "content": "#!/usr/bin/env python3\n\nimport os\nimport sys\n\nimport numpy as np\n\nfrom rednose.helpers import TEMPLATE_DIR, load_code, write_code\nfrom rednose.helpers.sympy_helpers import quat_matrix_l, rot_matrix\n\n\ndef sane(track):\n  img_pos = track[1:, 2:4]\n  diffs_x = abs(img_pos[1:, 0] - img_pos[:-1, 0])\n  diffs_y = abs(img_pos[1:, 1] - img_pos[:-1, 1])\n  for i in range(1, len(diffs_x)):\n    if ((diffs_x[i] > 0.05 or diffs_x[i - 1] > 0.05) and\n        (diffs_x[i] > 2 * diffs_x[i - 1] or\n         diffs_x[i] < .5 * diffs_x[i - 1])) or \\\n       ((diffs_y[i] > 0.05 or diffs_y[i - 1] > 0.05) and\n        (diffs_y[i] > 2 * diffs_y[i - 1] or\n         diffs_y[i] < .5 * diffs_y[i - 1])):\n      return False\n  return True\n\n\nclass FeatureHandler():\n  name = 'feature_handler'\n\n  @staticmethod\n  def generate_code(generated_dir, K=5):\n    # Wrap c code for slow matching\n    c_header = \"\\nvoid merge_features(double *tracks, double *features, long long *empty_idxs);\"\n\n    c_code = \"#include <math.h>\\n\"\n    c_code += \"#include <string.h>\\n\"\n    c_code += \"#define K %d\\n\" % K\n    c_code += \"extern \\\"C\\\" {\\n\"\n    c_code += \"\\n\" + open(os.path.join(TEMPLATE_DIR, \"feature_handler.c\")).read()\n    c_code += \"\\n}\\n\"\n\n    filename = f\"{FeatureHandler.name}_{K}\"\n    write_code(generated_dir, filename, c_code, c_header)\n\n  def __init__(self, generated_dir, K=5):\n    self.MAX_TRACKS = 6000\n    self.K = K\n\n    # Array of tracks, each track has K 5D features preceded\n    # by 5 params that inidicate [f_idx, last_idx, updated, complete, valid]\n    # f_idx: idx of current last feature in track\n    # idx of of last feature in frame\n    # bool for whether this track has been update\n    # bool for whether this track is complete\n    # bool for whether this track is valid\n    self.tracks = np.zeros((self.MAX_TRACKS, K + 1, 5))\n    self.tracks[:] = np.nan\n\n    name = f\"{FeatureHandler.name}_{K}\"\n    ffi, lib = load_code(generated_dir, name)\n\n    def merge_features_c(tracks, features, empty_idxs):\n      lib.merge_features(ffi.cast(\"double *\", tracks.ctypes.data),\n                         ffi.cast(\"double *\", features.ctypes.data),\n                         ffi.cast(\"long long *\", empty_idxs.ctypes.data))\n\n    # self.merge_features = self.merge_features_python\n    self.merge_features = merge_features_c\n\n  def reset(self):\n    self.tracks[:] = np.nan\n\n  def merge_features_python(self, tracks, features, empty_idxs):\n    empty_idx = 0\n    for f in features:\n      match_idx = int(f[4])\n      if tracks[match_idx, 0, 1] == match_idx and tracks[match_idx, 0, 2] == 0:\n        tracks[match_idx, 0, 0] += 1\n        tracks[match_idx, 0, 1] = f[1]\n        tracks[match_idx, 0, 2] = 1\n        tracks[match_idx, int(tracks[match_idx, 0, 0])] = f\n        if tracks[match_idx, 0, 0] == self.K:\n          tracks[match_idx, 0, 3] = 1\n          if sane(tracks[match_idx]):\n            tracks[match_idx, 0, 4] = 1\n      else:\n        if empty_idx == len(empty_idxs):\n          print('need more empty space')\n          continue\n        tracks[empty_idxs[empty_idx], 0, 0] = 1\n        tracks[empty_idxs[empty_idx], 0, 1] = f[1]\n        tracks[empty_idxs[empty_idx], 0, 2] = 1\n        tracks[empty_idxs[empty_idx], 1] = f\n        empty_idx += 1\n\n  def update_tracks(self, features):\n    last_idxs = np.copy(self.tracks[:, 0, 1])\n    real = np.isfinite(last_idxs)\n    self.tracks[last_idxs[real].astype(int)] = self.tracks[real]\n\n    mask = np.ones(self.MAX_TRACKS, np.bool)\n    mask[last_idxs[real].astype(int)] = 0\n    empty_idxs = np.arange(self.MAX_TRACKS)[mask]\n\n    self.tracks[empty_idxs] = np.nan\n    self.tracks[:, 0, 2] = 0\n    self.merge_features(self.tracks, features, empty_idxs)\n\n  def handle_features(self, features):\n    self.update_tracks(features)\n    valid_idxs = self.tracks[:, 0, 4] == 1\n    complete_idxs = self.tracks[:, 0, 3] == 1\n    stale_idxs = self.tracks[:, 0, 2] == 0\n    valid_tracks = self.tracks[valid_idxs]\n    self.tracks[complete_idxs] = np.nan\n    self.tracks[stale_idxs] = np.nan\n    return valid_tracks[:, 1:, :4].reshape((len(valid_tracks), self.K * 4))\n\n\ndef generate_orient_error_jac(K):\n  import sympy as sp\n  from rednose.helpers.sympy_helpers import quat_rotate\n\n  x_sym = sp.MatrixSymbol('abr', 3, 1)\n  dtheta = sp.MatrixSymbol('dtheta', 3, 1)\n  delta_quat = sp.Matrix(np.ones(4))\n  delta_quat[1:, :] = sp.Matrix(0.5 * dtheta[0:3, :])\n  poses_sym = sp.MatrixSymbol('poses', 7 * K, 1)\n  img_pos_sym = sp.MatrixSymbol('img_positions', 2 * K, 1)\n  alpha, beta, rho = x_sym\n  to_c = sp.Matrix(rot_matrix(-np.pi / 2, -np.pi / 2, 0))\n  pos_0 = sp.Matrix(np.array(poses_sym[K * 7 - 7:K * 7 - 4])[:, 0])\n  q = quat_matrix_l(poses_sym[K * 7 - 4:K * 7]) * delta_quat\n  quat_rot = quat_rotate(*q)\n  rot_g_to_0 = to_c * quat_rot.T\n  rows = []\n  for i in range(K):\n    pos_i = sp.Matrix(np.array(poses_sym[i * 7:i * 7 + 3])[:, 0])\n    q = quat_matrix_l(poses_sym[7 * i + 3:7 * i + 7]) * delta_quat\n    quat_rot = quat_rotate(*q)\n    rot_g_to_i = to_c * quat_rot.T\n    rot_0_to_i = rot_g_to_i * (rot_g_to_0.T)\n    trans_0_to_i = rot_g_to_i * (pos_0 - pos_i)\n    funct_vec = rot_0_to_i * sp.Matrix([alpha, beta, 1]) + rho * trans_0_to_i\n    h1, h2, h3 = funct_vec\n    rows.append(h1 / h3 - img_pos_sym[i * 2 + 0])\n    rows.append(h2 / h3 - img_pos_sym[i * 2 + 1])\n  img_pos_residual_sym = sp.Matrix(rows)\n\n  # sympy into c\n  sympy_functions = []\n  sympy_functions.append(('orient_error_jac', img_pos_residual_sym.jacobian(dtheta), [x_sym, poses_sym, img_pos_sym, dtheta]))\n\n  return sympy_functions\n\n\nif __name__ == \"__main__\":\n  K = int(sys.argv[1].split(\"_\")[-1])\n  generated_dir = sys.argv[2]\n  FeatureHandler.generate_code(generated_dir, K=K)\n"
  },
  {
    "path": "rednose/helpers/kalmanfilter.py",
    "content": "from typing import Any, Dict\n\nimport numpy as np\n\n\nclass KalmanFilter:\n  name = \"<name>\"\n  initial_x = np.zeros((0, 0))\n  initial_P_diag = np.zeros((0, 0))\n  Q = np.zeros((0, 0))\n  obs_noise: Dict[int, Any] = {}\n\n  filter = None  # Should be initialized when initializating a KalmanFilter implementation\n\n  @property\n  def x(self):\n    return self.filter.state()\n\n  @property\n  def t(self):\n    return self.filter.get_filter_time()\n\n  @property\n  def P(self):\n    return self.filter.covs()\n\n  def init_state(self, state, covs_diag=None, covs=None, filter_time=None):\n    if covs_diag is not None:\n      P = np.diag(covs_diag)\n    elif covs is not None:\n      P = covs\n    else:\n      P = self.filter.covs()\n    self.filter.init_state(state, P, filter_time)\n\n  def get_R(self, kind, n):\n    obs_noise = self.obs_noise[kind]\n    dim = obs_noise.shape[0]\n    R = np.zeros((n, dim, dim))\n    for i in range(n):\n      R[i, :, :] = obs_noise\n    return R\n\n  def predict_and_observe(self, t, kind, data, R=None):\n    if len(data) > 0:\n      data = np.atleast_2d(data)\n\n    if R is None:\n      R = self.get_R(kind, len(data))\n\n    self.filter.predict_and_update_batch(t, kind, data, R)\n"
  },
  {
    "path": "rednose/helpers/lst_sq_computer.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport sys\n\nimport numpy as np\nimport sympy as sp\n\nfrom rednose.helpers import TEMPLATE_DIR, load_code, write_code\nfrom rednose.helpers.sympy_helpers import quat_rotate, sympy_into_c, rot_matrix, rotations_from_quats\n\n\ndef generate_residual(K):\n  x_sym = sp.MatrixSymbol('abr', 3, 1)\n  poses_sym = sp.MatrixSymbol('poses', 7 * K, 1)\n  img_pos_sym = sp.MatrixSymbol('img_positions', 2 * K, 1)\n  alpha, beta, rho = x_sym\n  to_c = sp.Matrix(rot_matrix(-np.pi / 2, -np.pi / 2, 0))\n  pos_0 = sp.Matrix(np.array(poses_sym[K * 7 - 7:K * 7 - 4])[:, 0])\n  q = poses_sym[K * 7 - 4:K * 7]\n  quat_rot = quat_rotate(*q)\n  rot_g_to_0 = to_c * quat_rot.T\n  rows = []\n\n  for i in range(K):\n    pos_i = sp.Matrix(np.array(poses_sym[i * 7:i * 7 + 3])[:, 0])\n    q = poses_sym[7 * i + 3:7 * i + 7]\n    quat_rot = quat_rotate(*q)\n    rot_g_to_i = to_c * quat_rot.T\n    rot_0_to_i = rot_g_to_i * rot_g_to_0.T\n    trans_0_to_i = rot_g_to_i * (pos_0 - pos_i)\n    funct_vec = rot_0_to_i * sp.Matrix([alpha, beta, 1]) + rho * trans_0_to_i\n    h1, h2, h3 = funct_vec\n    rows.append(h1 / h3 - img_pos_sym[i * 2 + 0])\n    rows.append(h2 / h3 - img_pos_sym[i * 2 + 1])\n  img_pos_residual_sym = sp.Matrix(rows)\n\n  # sympy into c\n  sympy_functions = []\n  sympy_functions.append(('res_fun', img_pos_residual_sym, [x_sym, poses_sym, img_pos_sym]))\n  sympy_functions.append(('jac_fun', img_pos_residual_sym.jacobian(x_sym), [x_sym, poses_sym, img_pos_sym]))\n\n  return sympy_functions\n\n\nclass LstSqComputer():\n  name = 'pos_computer'\n\n  @staticmethod\n  def generate_code(generated_dir, K=4):\n    sympy_functions = generate_residual(K)\n    header, sympy_code = sympy_into_c(sympy_functions)\n\n    code = \"\\n#include \\\"rednose/helpers/common_ekf.h\\\"\\n\"\n    code += \"\\n#define KDIM %d\\n\" % K\n    code += \"extern \\\"C\\\" {\\n\"\n    code += sympy_code\n    code += \"\\n\" + open(os.path.join(TEMPLATE_DIR, \"compute_pos.c\")).read() + \"\\n\"\n    code += \"}\\n\"\n\n    header += \"\\nvoid compute_pos(double *to_c, double *in_poses, double *in_img_positions, double *param, double *pos);\\n\"\n\n    filename = f\"{LstSqComputer.name}_{K}\"\n    write_code(generated_dir, filename, code, header)\n\n  def __init__(self, generated_dir, K=4, MIN_DEPTH=2, MAX_DEPTH=500):\n    self.to_c = rot_matrix(-np.pi / 2, -np.pi / 2, 0)\n    self.MAX_DEPTH = MAX_DEPTH\n    self.MIN_DEPTH = MIN_DEPTH\n\n    name = f\"{LstSqComputer.name}_{K}\"\n    ffi, lib = load_code(generated_dir, name)\n\n    # wrap c functions\n    def residual_jac(x, poses, img_positions):\n      out = np.zeros(((K * 2, 3)), dtype=np.float64)\n      lib.jac_fun(ffi.cast(\"double *\", x.ctypes.data),\n                  ffi.cast(\"double *\", poses.ctypes.data),\n                  ffi.cast(\"double *\", img_positions.ctypes.data),\n                  ffi.cast(\"double *\", out.ctypes.data))\n      return out\n    self.residual_jac = residual_jac\n\n    def residual(x, poses, img_positions):\n      out = np.zeros((K * 2), dtype=np.float64)\n      lib.res_fun(ffi.cast(\"double *\", x.ctypes.data),\n                  ffi.cast(\"double *\", poses.ctypes.data),\n                  ffi.cast(\"double *\", img_positions.ctypes.data),\n                  ffi.cast(\"double *\", out.ctypes.data))\n      return out\n    self.residual = residual\n\n    def compute_pos_c(poses, img_positions):\n      pos = np.zeros(3, dtype=np.float64)\n      param = np.zeros(3, dtype=np.float64)\n      # Can't be a view for the ctype\n      img_positions = np.copy(img_positions)\n      lib.compute_pos(ffi.cast(\"double *\", self.to_c.ctypes.data),\n                      ffi.cast(\"double *\", poses.ctypes.data),\n                      ffi.cast(\"double *\", img_positions.ctypes.data),\n                      ffi.cast(\"double *\", param.ctypes.data),\n                      ffi.cast(\"double *\", pos.ctypes.data))\n      return pos, param\n    self.compute_pos_c = compute_pos_c\n\n  def compute_pos(self, poses, img_positions, debug=False):\n    pos, param = self.compute_pos_c(poses, img_positions)\n    # pos, param = self.compute_pos_python(poses, img_positions)\n\n    depth = 1 / param[2]\n    if debug:\n      # orient_err_jac = self.orient_error_jac(param, poses, img_positions, np.zeros(3)).reshape((-1,2,3))\n      jac = self.residual_jac(param, poses, img_positions).reshape((-1, 2, 3))\n      res = self.residual(param, poses, img_positions).reshape((-1, 2))\n      return pos, param, res, jac  # , orient_err_jac\n    elif (self.MIN_DEPTH < depth < self.MAX_DEPTH):\n      return pos\n    else:\n      return None\n\n  def gauss_newton(self, fun, jac, x, args):\n    poses, img_positions = args\n    delta = 1\n    counter = 0\n    while abs(np.linalg.norm(delta)) > 1e-4 and counter < 30:\n      delta = np.linalg.pinv(jac(x, poses, img_positions)).dot(fun(x, poses, img_positions))\n      x = x - delta\n      counter += 1\n    return [x]\n\n  def compute_pos_python(self, poses, img_positions, check_quality=False):\n    import scipy.optimize as opt\n\n    # This procedure is also described\n    # in the MSCKF paper (Mourikis et al. 2007)\n    x = np.array([img_positions[-1][0],\n                  img_positions[-1][1], 0.1])\n    res = opt.leastsq(self.residual, x, Dfun=self.residual_jac, args=(poses, img_positions))  # scipy opt\n    # res = self.gauss_newton(self.residual, self.residual_jac, x, (poses, img_positions)) # diy gauss_newton\n\n    alpha, beta, rho = res[0]\n    rot_0_to_g = (rotations_from_quats(poses[-1, 3:])).dot(self.to_c.T)\n    return (rot_0_to_g.dot(np.array([alpha, beta, 1]))) / rho + poses[-1, :3]\n\n\n# EXPERIMENTAL CODE\ndef unroll_shutter(img_positions, poses, v, rot_rates, ecef_pos):\n  # only speed correction for now\n  t_roll = 0.016  # 16ms rolling shutter?\n  vroll, vpitch, vyaw = rot_rates\n  A = 0.5 * np.array([[-1, -vroll, -vpitch, -vyaw],\n                      [vroll, 0, vyaw, -vpitch],\n                      [vpitch, -vyaw, 0, vroll],\n                      [vyaw, vpitch, -vroll, 0]])\n  q_dot = A.dot(poses[-1][3:7])\n  v = np.append(v, q_dot)\n  v = np.array([v[0], v[1], v[2], 0, 0, 0, 0])\n  current_pose = poses[-1] + v * 0.05\n  poses = np.vstack((current_pose, poses))\n  dt = -img_positions[:, 1] * t_roll / 0.48\n  errs = project(poses, ecef_pos) - project(poses + np.atleast_2d(dt).T.dot(np.atleast_2d(v)), ecef_pos)\n  return img_positions - errs\n\n\ndef project(poses, ecef_pos):\n  img_positions = np.zeros((len(poses), 2))\n  for i, p in enumerate(poses):\n    cam_frame = rotations_from_quats(p[3:]).T.dot(ecef_pos - p[:3])\n    img_positions[i] = np.array([cam_frame[1] / cam_frame[0], cam_frame[2] / cam_frame[0]])\n  return img_positions\n\n\nif __name__ == \"__main__\":\n  K = int(sys.argv[1].split(\"_\")[-1])\n  generated_dir = sys.argv[2]\n  LstSqComputer.generate_code(generated_dir, K=K)\n"
  },
  {
    "path": "rednose/helpers/sympy_helpers.py",
    "content": "#!/usr/bin/env python3\nimport sympy as sp\nimport numpy as np\n\n# TODO: remove code duplication between openpilot.common.orientation\ndef quat2rot(quats):\n  quats = np.array(quats)\n  input_shape = quats.shape\n  quats = np.atleast_2d(quats)\n  Rs = np.zeros((quats.shape[0], 3, 3))\n  q0 = quats[:, 0]\n  q1 = quats[:, 1]\n  q2 = quats[:, 2]\n  q3 = quats[:, 3]\n  Rs[:, 0, 0] = q0 * q0 + q1 * q1 - q2 * q2 - q3 * q3\n  Rs[:, 0, 1] = 2 * (q1 * q2 - q0 * q3)\n  Rs[:, 0, 2] = 2 * (q0 * q2 + q1 * q3)\n  Rs[:, 1, 0] = 2 * (q1 * q2 + q0 * q3)\n  Rs[:, 1, 1] = q0 * q0 - q1 * q1 + q2 * q2 - q3 * q3\n  Rs[:, 1, 2] = 2 * (q2 * q3 - q0 * q1)\n  Rs[:, 2, 0] = 2 * (q1 * q3 - q0 * q2)\n  Rs[:, 2, 1] = 2 * (q0 * q1 + q2 * q3)\n  Rs[:, 2, 2] = q0 * q0 - q1 * q1 - q2 * q2 + q3 * q3\n\n  if len(input_shape) < 2:\n    return Rs[0]\n  else:\n    return Rs\n\n\ndef euler2quat(eulers):\n  eulers = np.array(eulers)\n  if len(eulers.shape) > 1:\n    output_shape = (-1,4)\n  else:\n    output_shape = (4,)\n  eulers = np.atleast_2d(eulers)\n  gamma, theta, psi = eulers[:,0],  eulers[:,1],  eulers[:,2]\n\n  q0 = np.cos(gamma / 2) * np.cos(theta / 2) * np.cos(psi / 2) + \\\n       np.sin(gamma / 2) * np.sin(theta / 2) * np.sin(psi / 2)\n  q1 = np.sin(gamma / 2) * np.cos(theta / 2) * np.cos(psi / 2) - \\\n       np.cos(gamma / 2) * np.sin(theta / 2) * np.sin(psi / 2)\n  q2 = np.cos(gamma / 2) * np.sin(theta / 2) * np.cos(psi / 2) + \\\n       np.sin(gamma / 2) * np.cos(theta / 2) * np.sin(psi / 2)\n  q3 = np.cos(gamma / 2) * np.cos(theta / 2) * np.sin(psi / 2) - \\\n       np.sin(gamma / 2) * np.sin(theta / 2) * np.cos(psi / 2)\n\n  quats = np.array([q0, q1, q2, q3]).T\n  for i in range(len(quats)):\n    if quats[i,0] < 0:  # pylint: disable=unsubscriptable-object\n      quats[i] = -quats[i]  # pylint: disable=unsupported-assignment-operation,unsubscriptable-object\n  return quats.reshape(output_shape)\n\n\ndef euler2rot(eulers):\n  return quat2rot(euler2quat(eulers))\n\nrotations_from_quats = quat2rot\n\n\ndef cross(x):\n  ret = sp.Matrix(np.zeros((3, 3)))\n  ret[0, 1], ret[0, 2] = -x[2], x[1]\n  ret[1, 0], ret[1, 2] = x[2], -x[0]\n  ret[2, 0], ret[2, 1] = -x[1], x[0]\n  return ret\n\n\ndef rot_matrix(roll, pitch, yaw):\n  cr, sr = np.cos(roll), np.sin(roll)\n  cp, sp = np.cos(pitch), np.sin(pitch)\n  cy, sy = np.cos(yaw), np.sin(yaw)\n  rr = np.array([[1,0,0],[0, cr,-sr],[0, sr, cr]])\n  rp = np.array([[cp,0,sp],[0, 1,0],[-sp, 0, cp]])\n  ry = np.array([[cy,-sy,0],[sy, cy,0],[0, 0, 1]])\n  return ry.dot(rp.dot(rr))\n\n\ndef euler_rotate(roll, pitch, yaw):\n  # make symbolic rotation matrix from eulers\n  matrix_roll = sp.Matrix([[1, 0, 0],\n                           [0, sp.cos(roll), -sp.sin(roll)],\n                           [0, sp.sin(roll), sp.cos(roll)]])\n  matrix_pitch = sp.Matrix([[sp.cos(pitch), 0, sp.sin(pitch)],\n                            [0, 1, 0],\n                            [-sp.sin(pitch), 0, sp.cos(pitch)]])\n  matrix_yaw = sp.Matrix([[sp.cos(yaw), -sp.sin(yaw), 0],\n                          [sp.sin(yaw), sp.cos(yaw), 0],\n                          [0, 0, 1]])\n  return matrix_yaw * matrix_pitch * matrix_roll\n\n\ndef quat_rotate(q0, q1, q2, q3):\n  # make symbolic rotation matrix from quat\n  return sp.Matrix([[q0**2 + q1**2 - q2**2 - q3**2, 2 * (q1 * q2 + q0 * q3), 2 * (q1 * q3 - q0 * q2)],\n                    [2 * (q1 * q2 - q0 * q3), q0**2 - q1**2 + q2**2 - q3**2, 2 * (q2 * q3 + q0 * q1)],\n                    [2 * (q1 * q3 + q0 * q2), 2 * (q2 * q3 - q0 * q1), q0**2 - q1**2 - q2**2 + q3**2]]).T\n\n\ndef quat_matrix_l(p):\n  return sp.Matrix([[p[0], -p[1], -p[2], -p[3]],\n                    [p[1],  p[0], -p[3],  p[2]],\n                    [p[2],  p[3],  p[0], -p[1]],\n                    [p[3], -p[2],  p[1],  p[0]]])\n\n\ndef quat_matrix_r(p):\n  return sp.Matrix([[p[0], -p[1], -p[2], -p[3]],\n                    [p[1],  p[0],  p[3], -p[2]],\n                    [p[2], -p[3],  p[0],  p[1]],\n                    [p[3],  p[2], -p[1],  p[0]]])\n\n\ndef sympy_into_c(sympy_functions, global_vars=None):\n  from sympy.utilities import codegen\n  routines = []\n  for name, expr, args in sympy_functions:\n    r = codegen.make_routine(name, expr, language=\"C99\", global_vars=global_vars)\n\n    # argument ordering input to sympy is broken with function with output arguments\n    nargs = []\n\n    # reorder the input arguments\n    for aa in args:\n      if aa is None:\n        nargs.append(codegen.InputArgument(sp.Symbol('unused'), dimensions=[1, 1]))\n        continue\n      found = False\n      for a in r.arguments:\n        if str(aa.name) == str(a.name):\n          nargs.append(a)\n          found = True\n          break\n      if not found:\n        # [1,1] is a hack for Matrices\n        nargs.append(codegen.InputArgument(aa, dimensions=[1, 1]))\n\n    # add the output arguments\n    for a in r.arguments:\n      if type(a) == codegen.OutputArgument:\n        nargs.append(a)\n\n    # assert len(r.arguments) == len(args)+1\n    r.arguments = nargs\n\n    # add routine to list\n    routines.append(r)\n\n  [(_, c_code), (_, c_header)] = codegen.get_code_generator('C', 'ekf', 'C99').write(routines, \"ekf\")\n  c_header = '\\n'.join(x for x in c_header.split(\"\\n\") if len(x) > 0 and x[0] != '#')\n\n  c_code = '\\n'.join(x for x in c_code.split(\"\\n\") if len(x) > 0 and x[0] != '#')\n\n  return c_header, c_code\n"
  },
  {
    "path": "rednose/templates/compute_pos.c",
    "content": "#include <eigen3/Eigen/QR>\n#include <eigen3/Eigen/Dense>\n#include <iostream>\n\ntypedef Eigen::Matrix<double, KDIM*2, 3, Eigen::RowMajor> R3M;\ntypedef Eigen::Matrix<double, KDIM*2, 1> R1M;\ntypedef Eigen::Matrix<double, 3, 1> O1M;\ntypedef Eigen::Matrix<double, 3, 3, Eigen::RowMajor> M3D;\n\nvoid gauss_newton(double *in_x, double *in_poses, double *in_img_positions) {\n\n  double res[KDIM*2] = {0};\n  double jac[KDIM*6] = {0};\n\n  O1M x(in_x);\n  O1M delta;\n  int counter = 0;\n  while ((delta.squaredNorm() > 0.0001 and counter < 30) or counter == 0){\n    res_fun(in_x, in_poses, in_img_positions, res);\n    jac_fun(in_x, in_poses, in_img_positions, jac);\n    R1M E(res); R3M J(jac);\n    delta = (J.transpose()*J).inverse() * J.transpose() * E;\n    x = x - delta;\n    memcpy(in_x, x.data(), 3 * sizeof(double));\n    counter = counter + 1;\n  }\n}\n\n\nvoid compute_pos(double *to_c, double *poses, double *img_positions, double *param, double *pos) {\n    param[0] = img_positions[KDIM*2-2];\n    param[1] = img_positions[KDIM*2-1];\n    param[2] = 0.1;\n    gauss_newton(param, poses, img_positions);\n\n    Eigen::Quaterniond q;\n    q.w() = poses[KDIM*7-4];\n    q.x() = poses[KDIM*7-3];\n    q.y() = poses[KDIM*7-2];\n    q.z() = poses[KDIM*7-1];\n    M3D RC(to_c);\n    Eigen::Matrix3d R = q.normalized().toRotationMatrix();\n    Eigen::Matrix3d rot = R * RC.transpose();\n\n    pos[0] = param[0]/param[2];\n    pos[1] = param[1]/param[2];\n    pos[2] = 1.0/param[2];\n    O1M ecef_offset(poses + KDIM*7-7);\n    O1M ecef_output(pos);\n    ecef_output = rot*ecef_output + ecef_offset;\n    memcpy(pos, ecef_output.data(), 3 * sizeof(double));\n}\n"
  },
  {
    "path": "rednose/templates/ekf_c.c",
    "content": "#include <eigen3/Eigen/Dense>\n#include <iostream>\n\ntypedef Eigen::Matrix<double, DIM, DIM, Eigen::RowMajor> DDM;\ntypedef Eigen::Matrix<double, EDIM, EDIM, Eigen::RowMajor> EEM;\ntypedef Eigen::Matrix<double, DIM, EDIM, Eigen::RowMajor> DEM;\n\nvoid predict(double *in_x, double *in_P, double *in_Q, double dt) {\n  typedef Eigen::Matrix<double, MEDIM, MEDIM, Eigen::RowMajor> RRM;\n\n  double nx[DIM] = {0};\n  double in_F[EDIM*EDIM] = {0};\n\n  // functions from sympy\n  f_fun(in_x, dt, nx);\n  F_fun(in_x, dt, in_F);\n\n\n  EEM F(in_F);\n  EEM P(in_P);\n  EEM Q(in_Q);\n\n  RRM F_main = F.topLeftCorner(MEDIM, MEDIM);\n  P.topLeftCorner(MEDIM, MEDIM) = (F_main * P.topLeftCorner(MEDIM, MEDIM)) * F_main.transpose();\n  P.topRightCorner(MEDIM, EDIM - MEDIM) = F_main * P.topRightCorner(MEDIM, EDIM - MEDIM);\n  P.bottomLeftCorner(EDIM - MEDIM, MEDIM) = P.bottomLeftCorner(EDIM - MEDIM, MEDIM) * F_main.transpose();\n\n  P = P + dt*Q;\n\n  // copy out state\n  memcpy(in_x, nx, DIM * sizeof(double));\n  memcpy(in_P, P.data(), EDIM * EDIM * sizeof(double));\n}\n\n// note: extra_args dim only correct when null space projecting\n// otherwise 1\ntemplate <int ZDIM, int EADIM, bool MAHA_TEST>\nvoid update(double *in_x, double *in_P, Hfun h_fun, Hfun H_fun, Hfun Hea_fun, double *in_z, double *in_R, double *in_ea, double MAHA_THRESHOLD) {\n  typedef Eigen::Matrix<double, ZDIM, ZDIM, Eigen::RowMajor> ZZM;\n  typedef Eigen::Matrix<double, ZDIM, DIM, Eigen::RowMajor> ZDM;\n  typedef Eigen::Matrix<double, Eigen::Dynamic, EDIM, Eigen::RowMajor> XEM;\n  //typedef Eigen::Matrix<double, EDIM, ZDIM, Eigen::RowMajor> EZM;\n  typedef Eigen::Matrix<double, Eigen::Dynamic, 1> X1M;\n  typedef Eigen::Matrix<double, Eigen::Dynamic, Eigen::Dynamic, Eigen::RowMajor> XXM;\n\n  double in_hx[ZDIM] = {0};\n  double in_H[ZDIM * DIM] = {0};\n  double in_H_mod[EDIM * DIM] = {0};\n  double delta_x[EDIM] = {0};\n  double x_new[DIM] = {0};\n\n\n  // state x, P\n  Eigen::Matrix<double, ZDIM, 1> z(in_z);\n  EEM P(in_P);\n  ZZM pre_R(in_R);\n\n  // functions from sympy\n  h_fun(in_x, in_ea, in_hx);\n  H_fun(in_x, in_ea, in_H);\n  ZDM pre_H(in_H);\n\n  // get y (y = z - hx)\n  Eigen::Matrix<double, ZDIM, 1> pre_y(in_hx); pre_y = z - pre_y;\n  X1M y; XXM H; XXM R;\n  if (Hea_fun){\n    typedef Eigen::Matrix<double, ZDIM, EADIM, Eigen::RowMajor> ZAM;\n    double in_Hea[ZDIM * EADIM] = {0};\n    Hea_fun(in_x, in_ea, in_Hea);\n    ZAM Hea(in_Hea);\n    XXM A = Hea.transpose().fullPivLu().kernel();\n\n\n    y = A.transpose() * pre_y;\n    H = A.transpose() * pre_H;\n    R = A.transpose() * pre_R * A;\n  } else {\n    y = pre_y;\n    H = pre_H;\n    R = pre_R;\n  }\n  // get modified H\n  H_mod_fun(in_x, in_H_mod);\n  DEM H_mod(in_H_mod);\n  XEM H_err = H * H_mod;\n\n  // Do mahalobis distance test\n  if (MAHA_TEST){\n    XXM a = (H_err * P * H_err.transpose() + R).inverse();\n    double maha_dist = y.transpose() * a * y;\n    if (maha_dist > MAHA_THRESHOLD){\n      R = 1.0e16 * R;\n    }\n  }\n\n  // Outlier resilient weighting\n  double weight = 1;//(1.5)/(1 + y.squaredNorm()/R.sum());\n\n  // kalman gains and I_KH\n  XXM S = ((H_err * P) * H_err.transpose()) + R/weight;\n  XEM KT = S.fullPivLu().solve(H_err * P.transpose());\n  //EZM K = KT.transpose(); TODO: WHY DOES THIS NOT COMPILE?\n  //EZM K = S.fullPivLu().solve(H_err * P.transpose()).transpose();\n  //std::cout << \"Here is the matrix rot:\\n\" << K << std::endl;\n  EEM I_KH = Eigen::Matrix<double, EDIM, EDIM>::Identity() - (KT.transpose() * H_err);\n\n  // update state by injecting dx\n  Eigen::Matrix<double, EDIM, 1> dx(delta_x);\n  dx  = (KT.transpose() * y);\n  memcpy(delta_x, dx.data(), EDIM * sizeof(double));\n  err_fun(in_x, delta_x, x_new);\n  Eigen::Matrix<double, DIM, 1> x(x_new);\n\n  // update cov\n  P = ((I_KH * P) * I_KH.transpose()) + ((KT.transpose() * R) * KT);\n\n  // copy out state\n  memcpy(in_x, x.data(), DIM * sizeof(double));\n  memcpy(in_P, P.data(), EDIM * EDIM * sizeof(double));\n  memcpy(in_z, y.data(), y.rows() * sizeof(double));\n}\n\n\n"
  },
  {
    "path": "rednose/templates/feature_handler.c",
    "content": "bool sane(double track [K + 1][5]) {\n  double diffs_x [K-1];\n  double diffs_y [K-1];\n  int i;\n  for (i = 0; i < K-1; i++) {\n    diffs_x[i] = fabs(track[i+2][2] - track[i+1][2]);\n    diffs_y[i] = fabs(track[i+2][3] - track[i+1][3]);\n  }\n  for (i = 1; i < K-1; i++) {\n    if (((diffs_x[i] > 0.05 or diffs_x[i-1] > 0.05) and\n         (diffs_x[i] > 2*diffs_x[i-1] or\n          diffs_x[i] < .5*diffs_x[i-1])) or\n        ((diffs_y[i] > 0.05 or diffs_y[i-1] > 0.05) and\n\t (diffs_y[i] > 2*diffs_y[i-1] or\n          diffs_y[i] < .5*diffs_y[i-1]))){\n      return false;\n    }\n  }\n  return true;\n}\n\nvoid merge_features(double *tracks, double *features, long long *empty_idxs) {\n  double feature_arr [3000][5];\n  memcpy(feature_arr, features, 3000 * 5 * sizeof(double));\n  double track_arr [6000][K + 1][5];\n  memcpy(track_arr, tracks, (K+1) * 6000 * 5 * sizeof(double));\n  int match;\n  int empty_idx = 0;\n  int idx;\n  for (int i = 0; i < 3000; i++) {\n    match = feature_arr[i][4];\n    if (track_arr[match][0][1] == match and track_arr[match][0][2] == 0){\n      track_arr[match][0][0] = track_arr[match][0][0] + 1;\n      track_arr[match][0][1] = feature_arr[i][1];\n      track_arr[match][0][2] = 1;\n      idx = track_arr[match][0][0];\n      memcpy(track_arr[match][idx], feature_arr[i], 5 * sizeof(double));\n      if (idx == K){\n        // label complete\n        track_arr[match][0][3] = 1;\n\tif (sane(track_arr[match])){\n          // label valid\n          track_arr[match][0][4] = 1;\n\t}\n      }\n    } else {\n      // gen new track with this feature\n      track_arr[empty_idxs[empty_idx]][0][0] = 1;\n      track_arr[empty_idxs[empty_idx]][0][1] = feature_arr[i][1];\n      track_arr[empty_idxs[empty_idx]][0][2] = 1;\n      memcpy(track_arr[empty_idxs[empty_idx]][1], feature_arr[i], 5 * sizeof(double));\n      empty_idx = empty_idx + 1;\n    }\n  }\n  memcpy(tracks, track_arr, (K+1) * 6000 * 5 * sizeof(double));\n}\n"
  },
  {
    "path": "release/build_devel.sh",
    "content": "#!/usr/bin/bash -e\n\nDIR=\"$(cd \"$(dirname \"${BASH_SOURCE[0]}\")\" >/dev/null && pwd)\"\n\nTARGET_DIR=/data/openpilot\nSOURCE_DIR=\"$(git rev-parse --show-toplevel)\"\n\n# set git identity\nsource $DIR/identity.sh\n\necho \"[-] Setting up repo T=$SECONDS\"\nif [ ! -d \"$TARGET_DIR\" ]; then\n  mkdir -p $TARGET_DIR\n  cd $TARGET_DIR\n  git init\n  git remote add origin git@github.com:commaai/openpilot.git\nfi\n\necho \"[-] bringing master-ci and devel in sync T=$SECONDS\"\ncd $TARGET_DIR\ngit prune || true\ngit remote prune origin || true\ngit fetch origin master-ci\ngit fetch origin devel\n\ngit checkout -f --track origin/master-ci\ngit reset --hard master-ci\ngit checkout master-ci\ngit reset --hard origin/devel\ngit clean -xdf\n\n# remove everything except .git\necho \"[-] erasing old openpilot T=$SECONDS\"\nfind . -maxdepth 1 -not -path './.git' -not -name '.' -not -name '..' -exec rm -rf '{}' \\;\n\n# reset source tree\ncd $SOURCE_DIR\ngit clean -xdf\n\n# do the files copy\necho \"[-] copying files T=$SECONDS\"\ncd $SOURCE_DIR\ncp -pR --parents $(cat release/files_common) $TARGET_DIR/\ncp -pR --parents $(cat release/files_tici) $TARGET_DIR/\nif [ ! -z \"$EXTRA_FILES\" ]; then\n  cp -pR --parents $EXTRA_FILES $TARGET_DIR/\nfi\n\n# append source commit hash and build date to version\nGIT_HASH=$(git --git-dir=$SOURCE_DIR/.git rev-parse --short HEAD)\nDATETIME=$(date '+%Y-%m-%dT%H:%M:%S')\nVERSION=$(cat selfdrive/common/version.h | awk -F\\\" '{print $2}')\necho \"#define COMMA_VERSION \\\"$VERSION-$GIT_HASH-$DATETIME\\\"\" > selfdrive/common/version.h\n\n# in the directory\ncd $TARGET_DIR\nrm -f panda/board/obj/panda.bin.signed\n\necho \"[-] committing version $VERSION T=$SECONDS\"\ngit add -f .\ngit status\ngit commit -a -m \"openpilot v$VERSION release\"\n\nif [ ! -z \"$PUSH\" ]; then\n  echo \"[-] Pushing to $PUSH T=$SECONDS\"\n  git remote set-url origin git@github.com:commaai/openpilot.git\n  git push -f origin master-ci:$PUSH\nfi\n\necho \"[-] done T=$SECONDS\"\n"
  },
  {
    "path": "release/build_release2.sh",
    "content": "#!/usr/bin/env bash\nset -e\n\nexport GIT_COMMITTER_NAME=\"Vehicle Researcher\"\nexport GIT_COMMITTER_EMAIL=\"user@comma.ai\"\nexport GIT_AUTHOR_NAME=\"Vehicle Researcher\"\nexport GIT_AUTHOR_EMAIL=\"user@comma.ai\"\n\nexport GIT_SSH_COMMAND=\"ssh -i /data/gitkey\"\n\n# set CLEAN to build outside of CI\nif [ ! -z \"$CLEAN\" ]; then\n  # Create folders\n  rm -rf /data/openpilot\n  mkdir -p /data/openpilot\n  cd /data/openpilot\n\n  # Create git repo\n  git init\n  git remote add origin git@github.com:commaai/openpilot.git\n  git fetch origin devel-staging\nelse\n  cd /data/openpilot\n  git clean -xdf\n  git branch -D release2-staging || true\nfi\n\ngit fetch origin release2-staging\ngit fetch origin dashcam-staging\n\n# Create release2 with no history\nif [ ! -z \"$CLEAN\" ]; then\n  git checkout --orphan release2-staging origin/devel-staging\nelse\n  git checkout --orphan release2-staging\nfi\n\nVERSION=$(cat selfdrive/common/version.h | awk -F[\\\"-]  '{print $2}')\necho \"#define COMMA_VERSION \\\"$VERSION-release\\\"\" > selfdrive/common/version.h\n\ngit commit -m \"openpilot v$VERSION\"\n\n# Build signed panda firmware\npushd panda/\nCERT=/tmp/pandaextra/certs/release RELEASE=1 scons -u .\nmv board/obj/panda.bin.signed /tmp/panda.bin.signed\npopd\n\n# Build stuff\nln -sfn /data/openpilot /data/pythonpath\nexport PYTHONPATH=\"/data/openpilot:/data/openpilot/pyextra\"\nscons -j3\n\n# Run tests\npython selfdrive/manager/test/test_manager.py\nselfdrive/car/tests/test_car_interfaces.py\n\n# Ensure no submodules in release\nif test \"$(git submodule--helper list | wc -l)\" -gt \"0\"; then\n  echo \"submodules found:\"\n  git submodule--helper list\n  exit 1\nfi\ngit submodule status\n\n# Cleanup\nfind . -name '*.a' -delete\nfind . -name '*.o' -delete\nfind . -name '*.os' -delete\nfind . -name '*.pyc' -delete\nfind . -name '__pycache__' -delete\nrm -rf panda/board panda/certs panda/crypto\nrm -rf .sconsign.dblite Jenkinsfile release/\nrm models/supercombo.dlc\n\n# Move back signed panda fw\nmkdir -p panda/board/obj\nmv /tmp/panda.bin.signed panda/board/obj/panda.bin.signed\n\n# Restore phonelibs\ngit checkout phonelibs/\n\n# Mark as prebuilt release\ntouch prebuilt\n\n# Add built files to git\ngit add -f .\ngit commit --amend -m \"openpilot v$VERSION\"\n\n# Print committed files that are normally gitignored\n#git status --ignored\n\nif [ ! -z \"$PUSH\" ]; then\n  git remote set-url origin git@github.com:commaai/openpilot.git\n\n  # Push to release2-staging\n  git push -f origin release2-staging\n\n  # Create dashcam release\n  git rm selfdrive/car/*/carcontroller.py\n\n  git commit -m \"create dashcam release from release2\"\n  git push -f origin release2-staging:dashcam-staging\nfi\n"
  },
  {
    "path": "release/build_release3.sh",
    "content": "#!/usr/bin/bash -e\n\n# git diff --name-status origin/release3-staging | grep \"^A\" | less\n\nDIR=\"$(cd \"$(dirname \"${BASH_SOURCE[0]}\")\" >/dev/null && pwd)\"\n\ncd $DIR\n\nBUILD_DIR=/data/openpilot\nSOURCE_DIR=\"$(git rev-parse --show-toplevel)\"\n\nBRANCH=release3-staging\n\n# set git identity\nsource $DIR/identity.sh\n\necho \"[-] Setting up repo T=$SECONDS\"\nrm -rf $BUILD_DIR\nmkdir -p $BUILD_DIR\ncd $BUILD_DIR\ngit init\ngit remote add origin git@github.com:commaai/openpilot.git\ngit checkout -f -B $BRANCH\n\n# do the files copy\necho \"[-] copying files T=$SECONDS\"\ncd $SOURCE_DIR\ncp -pR --parents $(cat release/files_common) $BUILD_DIR/\ncp -pR --parents $(cat release/files_tici) $BUILD_DIR/\n\n# in the directory\ncd $BUILD_DIR\n\nrm -f panda/board/obj/panda.bin.signed\n\nVERSION=$(cat selfdrive/common/version.h | awk -F[\\\"-]  '{print $2}')\necho \"#define COMMA_VERSION \\\"$VERSION-release\\\"\" > selfdrive/common/version.h\n\necho \"[-] committing version $VERSION T=$SECONDS\"\ngit add -f .\ngit commit -a -m \"openpilot v$VERSION release\"\n\n# Build panda firmware\npushd panda/\nCERT=/data/pandaextra/certs/release RELEASE=1 scons -u .\nmv board/obj/panda.bin.signed /tmp/panda.bin.signed\npopd\n\n# Build\nexport PYTHONPATH=\"$BUILD_DIR\"\nscons -j$(nproc)\n\n# Run tests\n#python selfdrive/manager/test/test_manager.py\nselfdrive/car/tests/test_car_interfaces.py\n\n# Cleanup\nfind . -name '*.a' -delete\nfind . -name '*.o' -delete\nfind . -name '*.os' -delete\nfind . -name '*.pyc' -delete\nfind . -name '__pycache__' -delete\nrm -rf panda/board panda/certs panda/crypto\nrm -rf .sconsign.dblite Jenkinsfile release/\nrm models/supercombo.dlc\n\n# Move back signed panda fw\nmkdir -p panda/board/obj\nmv /tmp/panda.bin.signed panda/board/obj/panda.bin.signed\n\n# Restore phonelibs\ngit checkout phonelibs/\n\n# Mark as prebuilt release\ntouch prebuilt\n\n# Add built files to git\ngit add -f .\ngit commit --amend -m \"openpilot v$VERSION\"\n\nif [ ! -z \"$PUSH\" ]; then\n  echo \"[-] pushing T=$SECONDS\"\n  git remote set-url origin git@github.com:commaai/openpilot.git\n  git push -f origin $BRANCH\n\n  # Create dashcam\n  git rm selfdrive/car/*/carcontroller.py\n  git commit -m \"create dashcam release from release\"\n  git push -f origin $BRANCH:dashcam3-staging\nfi\n\necho \"[-] done T=$SECONDS\"\n"
  },
  {
    "path": "release/check-submodules.sh",
    "content": "#!/bin/bash\n\nwhile read hash submodule ref; do\n  git -C $submodule fetch --depth 100 origin master\n  git -C $submodule branch -r --contains $hash | grep \"origin/master\"\n  if [ \"$?\" -eq 0 ]; then\n    echo \"$submodule ok\"\n  else\n    echo \"$submodule: $hash is not on master\"\n    exit 1\n  fi\ndone <<< $(git submodule status --recursive)\n"
  },
  {
    "path": "release/files_common",
    "content": ".gitignore\nLICENSE\nlaunch_env.sh\nlaunch_chffrplus.sh\nlaunch_openpilot.sh\n\nJenkinsfile\nSConstruct\n\nCONTRIBUTING.md\nREADME.md\nRELEASES.md\nSAFETY.md\nsite_scons/site_tools/cython.py\n\ncommon/.gitignore\ncommon/__init__.py\ncommon/gpio.py\ncommon/realtime.py\ncommon/clock.pyx\ncommon/timeout.py\ncommon/ffi_wrapper.py\ncommon/file_helpers.py\ncommon/logging_extra.py\ncommon/numpy_fast.py\ncommon/params.py\ncommon/params_pxd.pxd\ncommon/params_pyx.pyx\ncommon/xattr.py\ncommon/profiler.py\ncommon/basedir.py\ncommon/dict_helpers.py\ncommon/filter_simple.py\ncommon/stat_live.py\ncommon/spinner.py\ncommon/text_window.py\ncommon/cython_hacks.py\ncommon/SConscript\n\ncommon/kalman/.gitignore\ncommon/kalman/*\n\ncommon/transformations/__init__.py\ncommon/transformations/camera.py\ncommon/transformations/model.py\n\ncommon/transformations/SConscript\ncommon/transformations/coordinates.py\ncommon/transformations/coordinates.cc\ncommon/transformations/coordinates.hpp\ncommon/transformations/orientation.py\ncommon/transformations/orientation.cc\ncommon/transformations/orientation.hpp\ncommon/transformations/transformations.pxd\ncommon/transformations/transformations.pyx\n\ncommon/api/__init__.py\n\nmodels/supercombo.dlc\nmodels/dmonitoring_model_q.dlc\n\nrelease/*\n\nselfdrive/version.py\n\nselfdrive/__init__.py\nselfdrive/config.py\nselfdrive/crash.py\nselfdrive/swaglog.py\nselfdrive/logmessaged.py\nselfdrive/tombstoned.py\nselfdrive/pandad.py\nselfdrive/updated.py\nselfdrive/rtshield.py\n\nselfdrive/athena/__init__.py\nselfdrive/athena/athenad.py\nselfdrive/athena/manage_athenad.py\nselfdrive/athena/registration.py\n\nselfdrive/boardd/.gitignore\nselfdrive/boardd/SConscript\nselfdrive/boardd/__init__.py\nselfdrive/boardd/boardd.cc\nselfdrive/boardd/boardd.py\nselfdrive/boardd/boardd_api_impl.pyx\nselfdrive/boardd/can_list_to_can_capnp.cc\nselfdrive/boardd/panda.cc\nselfdrive/boardd/panda.h\nselfdrive/boardd/pigeon.cc\nselfdrive/boardd/pigeon.h\nselfdrive/boardd/set_time.py\n\nselfdrive/car/__init__.py\nselfdrive/car/car_helpers.py\nselfdrive/car/fingerprints.py\nselfdrive/car/interfaces.py\nselfdrive/car/vin.py\nselfdrive/car/fw_versions.py\nselfdrive/car/isotp_parallel_query.py\nselfdrive/car/tests/__init__.py\nselfdrive/car/tests/test_car_interfaces.py\nselfdrive/car/chrysler/__init__.py\nselfdrive/car/chrysler/carstate.py\nselfdrive/car/chrysler/interface.py\nselfdrive/car/chrysler/radar_interface.py\nselfdrive/car/chrysler/values.py\nselfdrive/car/chrysler/carcontroller.py\nselfdrive/car/chrysler/chryslercan.py\nselfdrive/car/honda/__init__.py\nselfdrive/car/honda/carstate.py\nselfdrive/car/honda/interface.py\nselfdrive/car/honda/radar_interface.py\nselfdrive/car/honda/values.py\nselfdrive/car/honda/carcontroller.py\nselfdrive/car/honda/hondacan.py\nselfdrive/car/hyundai/__init__.py\nselfdrive/car/hyundai/carstate.py\nselfdrive/car/hyundai/interface.py\nselfdrive/car/hyundai/radar_interface.py\nselfdrive/car/hyundai/values.py\nselfdrive/car/hyundai/carcontroller.py\nselfdrive/car/hyundai/hyundaican.py\nselfdrive/car/toyota/__init__.py\nselfdrive/car/toyota/carstate.py\nselfdrive/car/toyota/interface.py\nselfdrive/car/toyota/radar_interface.py\nselfdrive/car/toyota/values.py\nselfdrive/car/toyota/carcontroller.py\nselfdrive/car/toyota/toyotacan.py\nselfdrive/car/nissan/__init__.py\nselfdrive/car/nissan/carcontroller.py\nselfdrive/car/nissan/carstate.py\nselfdrive/car/nissan/interface.py\nselfdrive/car/nissan/nissancan.py\nselfdrive/car/nissan/radar_interface.py\nselfdrive/car/nissan/values.py\nselfdrive/car/volkswagen/__init__.py\nselfdrive/car/volkswagen/carstate.py\nselfdrive/car/volkswagen/interface.py\nselfdrive/car/volkswagen/radar_interface.py\nselfdrive/car/volkswagen/values.py\nselfdrive/car/volkswagen/carcontroller.py\nselfdrive/car/volkswagen/volkswagencan.py\nselfdrive/car/gm/__init__.py\nselfdrive/car/gm/carstate.py\nselfdrive/car/gm/interface.py\nselfdrive/car/gm/radar_interface.py\nselfdrive/car/gm/values.py\nselfdrive/car/gm/carcontroller.py\nselfdrive/car/gm/gmcan.py\nselfdrive/car/ford/__init__.py\nselfdrive/car/ford/carstate.py\nselfdrive/car/ford/interface.py\nselfdrive/car/ford/radar_interface.py\nselfdrive/car/ford/values.py\nselfdrive/car/ford/carcontroller.py\nselfdrive/car/ford/fordcan.py\nselfdrive/car/subaru/__init__.py\nselfdrive/car/subaru/carstate.py\nselfdrive/car/subaru/interface.py\nselfdrive/car/subaru/radar_interface.py\nselfdrive/car/subaru/values.py\nselfdrive/car/subaru/carcontroller.py\nselfdrive/car/subaru/subarucan.py\nselfdrive/car/mazda/__init__.py\nselfdrive/car/mazda/carstate.py\nselfdrive/car/mazda/interface.py\nselfdrive/car/mazda/radar_interface.py\nselfdrive/car/mazda/values.py\nselfdrive/car/mazda/carcontroller.py\nselfdrive/car/mazda/mazdacan.py\nselfdrive/car/tesla/__init__.py\nselfdrive/car/tesla/teslacan.py\nselfdrive/car/tesla/carcontroller.py\nselfdrive/car/tesla/radar_interface.py\nselfdrive/car/tesla/values.py\nselfdrive/car/tesla/carstate.py\nselfdrive/car/tesla/interface.py\nselfdrive/car/mock/*.py\n\nselfdrive/clocksd/.gitignore\nselfdrive/clocksd/SConscript\nselfdrive/clocksd/clocksd.cc\n\nselfdrive/debug/*.py\n\nselfdrive/common/SConscript\nselfdrive/common/version.h\n\nselfdrive/common/framebuffer.h\nselfdrive/common/framebuffer.cc\nselfdrive/common/glutil.cc\nselfdrive/common/glutil.h\nselfdrive/common/touch.[c,h]\nselfdrive/common/swaglog.h\nselfdrive/common/swaglog.cc\nselfdrive/common/util.cc\nselfdrive/common/util.h\nselfdrive/common/queue.h\nselfdrive/common/clutil.cc\nselfdrive/common/clutil.h\nselfdrive/common/params.h\nselfdrive/common/params.cc\nselfdrive/common/watchdog.cc\nselfdrive/common/watchdog.h\n\nselfdrive/common/modeldata.h\nselfdrive/common/mat.h\nselfdrive/common/timing.h\n\nselfdrive/common/visionimg.cc\nselfdrive/common/visionimg.h\n\nselfdrive/common/gpio.cc\nselfdrive/common/gpio.h\nselfdrive/common/i2c.cc\nselfdrive/common/i2c.h\n\n\nselfdrive/controls/__init__.py\nselfdrive/controls/controlsd.py\nselfdrive/controls/plannerd.py\nselfdrive/controls/radard.py\nselfdrive/controls/lib/__init__.py\nselfdrive/controls/lib/alertmanager.py\nselfdrive/controls/lib/alerts_offroad.json\nselfdrive/controls/lib/events.py\nselfdrive/controls/lib/drive_helpers.py\nselfdrive/controls/lib/latcontrol_pid.py\nselfdrive/controls/lib/latcontrol_indi.py\nselfdrive/controls/lib/latcontrol_lqr.py\nselfdrive/controls/lib/latcontrol_angle.py\nselfdrive/controls/lib/longcontrol.py\nselfdrive/controls/lib/lateral_planner.py\nselfdrive/controls/lib/lane_planner.py\nselfdrive/controls/lib/pid.py\nselfdrive/controls/lib/longitudinal_planner.py\nselfdrive/controls/lib/radar_helpers.py\nselfdrive/controls/lib/vehicle_model.py\nselfdrive/controls/lib/fcw.py\nselfdrive/controls/lib/long_mpc.py\nselfdrive/controls/lib/lead_mpc.py\n\nselfdrive/controls/lib/cluster/*\n\nselfdrive/controls/lib/lateral_mpc/lib_mpc_export/*\nselfdrive/controls/lib/lateral_mpc/.gitignore\nselfdrive/controls/lib/lateral_mpc/SConscript\nselfdrive/controls/lib/lateral_mpc/__init__.py\nselfdrive/controls/lib/lateral_mpc/generator.cpp\nselfdrive/controls/lib/lateral_mpc/libmpc_py.py\nselfdrive/controls/lib/lateral_mpc/lateral_mpc.c\n\nselfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/*\nselfdrive/controls/lib/lead_mpc_lib/.gitignore\nselfdrive/controls/lib/lead_mpc_lib/SConscript\nselfdrive/controls/lib/lead_mpc_lib/__init__.py\nselfdrive/controls/lib/lead_mpc_lib/generator.cpp\nselfdrive/controls/lib/lead_mpc_lib/libmpc_py.py\nselfdrive/controls/lib/lead_mpc_lib/longitudinal_mpc.c\n\nselfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/*\nselfdrive/controls/lib/longitudinal_mpc_lib/.gitignore\nselfdrive/controls/lib/longitudinal_mpc_lib/SConscript\nselfdrive/controls/lib/longitudinal_mpc_lib/__init__.py\nselfdrive/controls/lib/longitudinal_mpc_lib/generator.cpp\nselfdrive/controls/lib/longitudinal_mpc_lib/libmpc_py.py\nselfdrive/controls/lib/longitudinal_mpc_lib/longitudinal_mpc.c\n\nselfdrive/hardware/__init__.py\nselfdrive/hardware/base.h\nselfdrive/hardware/base.py\nselfdrive/hardware/hw.h\nselfdrive/hardware/eon/__init__.py\nselfdrive/hardware/eon/hardware.h\nselfdrive/hardware/eon/hardware.py\nselfdrive/hardware/eon/androidd.py\nselfdrive/hardware/tici/__init__.py\nselfdrive/hardware/tici/hardware.py\nselfdrive/hardware/tici/amplifier.py\nselfdrive/hardware/tici/iwlist.py\nselfdrive/hardware/pc/__init__.py\nselfdrive/hardware/pc/hardware.py\n\nselfdrive/locationd/__init__.py\nselfdrive/locationd/.gitignore\nselfdrive/locationd/SConscript\nselfdrive/locationd/ubloxd.cc\nselfdrive/locationd/ublox_msg.cc\nselfdrive/locationd/ublox_msg.h\nselfdrive/locationd/generated/ubx.cpp\nselfdrive/locationd/generated/ubx.h\nselfdrive/locationd/generated/gps.cpp\nselfdrive/locationd/generated/gps.h\n\nselfdrive/locationd/locationd.h\nselfdrive/locationd/locationd.cc\nselfdrive/locationd/paramsd.py\nselfdrive/locationd/models/.gitignore\nselfdrive/locationd/models/live_kf.py\nselfdrive/locationd/models/car_kf.py\nselfdrive/locationd/models/constants.py\nselfdrive/locationd/models/live_kf.h\nselfdrive/locationd/models/live_kf.cc\n\nselfdrive/locationd/calibrationd.py\n\nselfdrive/logcatd/SConscript\nselfdrive/logcatd/logcatd_android.cc\nselfdrive/logcatd/logcatd_systemd.cc\n\nselfdrive/proclogd/SConscript\nselfdrive/proclogd/main.cc\nselfdrive/proclogd/proclog.cc\nselfdrive/proclogd/proclog.h\n\nselfdrive/loggerd/SConscript\nselfdrive/loggerd/encoder.h\nselfdrive/loggerd/omx_encoder.cc\nselfdrive/loggerd/omx_encoder.h\nselfdrive/loggerd/logger.cc\nselfdrive/loggerd/logger.h\nselfdrive/loggerd/loggerd.cc\nselfdrive/loggerd/bootlog.cc\nselfdrive/loggerd/raw_logger.cc\nselfdrive/loggerd/raw_logger.h\nselfdrive/loggerd/include/msm_media_info.h\n\nselfdrive/loggerd/__init__.py\nselfdrive/loggerd/config.py\nselfdrive/loggerd/uploader.py\nselfdrive/loggerd/deleter.py\nselfdrive/loggerd/xattr_cache.py\n\nselfdrive/sensord/SConscript\nselfdrive/sensord/libdiag.h\nselfdrive/sensord/sensors_qcom.cc\nselfdrive/sensord/sensors_qcom2.cc\nselfdrive/sensord/sensors/*.cc\nselfdrive/sensord/sensors/*.h\nselfdrive/sensord/sensord\n\nselfdrive/thermald/thermald.py\nselfdrive/thermald/power_monitoring.py\n\nselfdrive/test/__init__.py\nselfdrive/test/helpers.py\nselfdrive/test/setup_device_ci.sh\nselfdrive/test/test_fingerprints.py\nselfdrive/test/test_onroad.py\n\nselfdrive/ui/.gitignore\nselfdrive/ui/SConscript\nselfdrive/ui/*.cc\nselfdrive/ui/*.h\nselfdrive/ui/ui\nselfdrive/ui/text\nselfdrive/ui/spinner\nselfdrive/ui/soundd\n\nselfdrive/ui/qt/*.cc\nselfdrive/ui/qt/*.h\nselfdrive/ui/qt/offroad/*.cc\nselfdrive/ui/qt/offroad/*.h\nselfdrive/ui/qt/offroad/*.qml\nselfdrive/ui/qt/widgets/*.cc\nselfdrive/ui/qt/widgets/*.h\nselfdrive/ui/qt/spinner_aarch64\nselfdrive/ui/qt/text_aarch64\n\nselfdrive/camerad/SConscript\nselfdrive/camerad/main.cc\n\nselfdrive/camerad/snapshot/*\nselfdrive/camerad/include/*\nselfdrive/camerad/cameras/camera_common.h\nselfdrive/camerad/cameras/camera_common.cc\nselfdrive/camerad/cameras/camera_frame_stream.cc\nselfdrive/camerad/cameras/camera_frame_stream.h\nselfdrive/camerad/cameras/camera_qcom.cc\nselfdrive/camerad/cameras/camera_qcom.h\nselfdrive/camerad/cameras/debayer.cl\nselfdrive/camerad/cameras/sensor_i2c.h\nselfdrive/camerad/cameras/sensor2_i2c.h\n\nselfdrive/camerad/transforms/rgb_to_yuv.cc\nselfdrive/camerad/transforms/rgb_to_yuv.h\nselfdrive/camerad/transforms/rgb_to_yuv.cl\nselfdrive/camerad/transforms/rgb_to_yuv_test.cc\n\nselfdrive/camerad/imgproc/conv.cl\nselfdrive/camerad/imgproc/pool.cl\nselfdrive/camerad/imgproc/utils.cc\nselfdrive/camerad/imgproc/utils.h\n\nselfdrive/manager/__init__.py\nselfdrive/manager/build.py\nselfdrive/manager/helpers.py\nselfdrive/manager/manager.py\nselfdrive/manager/process_config.py\nselfdrive/manager/process.py\nselfdrive/manager/test/__init__.py\nselfdrive/manager/test/test_manager.py\n\nselfdrive/modeld/SConscript\nselfdrive/modeld/modeld.cc\nselfdrive/modeld/dmonitoringmodeld.cc\nselfdrive/modeld/constants.py\nselfdrive/modeld/modeld\nselfdrive/modeld/dmonitoringmodeld\n\nselfdrive/modeld/models/commonmodel.cc\nselfdrive/modeld/models/commonmodel.h\nselfdrive/modeld/models/driving.cc\nselfdrive/modeld/models/driving.h\nselfdrive/modeld/models/dmonitoring.cc\nselfdrive/modeld/models/dmonitoring.h\n\nselfdrive/modeld/transforms/loadyuv.cc\nselfdrive/modeld/transforms/loadyuv.h\nselfdrive/modeld/transforms/loadyuv.cl\nselfdrive/modeld/transforms/transform.cc\nselfdrive/modeld/transforms/transform.h\nselfdrive/modeld/transforms/transform.cl\n\nselfdrive/modeld/thneed/thneed.*\nselfdrive/modeld/thneed/serialize.cc\nselfdrive/modeld/thneed/compile.cc\nselfdrive/modeld/thneed/include/*\n\nselfdrive/modeld/runners/snpemodel.cc\nselfdrive/modeld/runners/snpemodel.h\nselfdrive/modeld/runners/thneedmodel.cc\nselfdrive/modeld/runners/thneedmodel.h\nselfdrive/modeld/runners/runmodel.h\nselfdrive/modeld/runners/run.h\n\nselfdrive/monitoring/dmonitoringd.py\nselfdrive/monitoring/driver_monitor.py\n\nselfdrive/assets/.gitignore\nselfdrive/assets/assets.qrc\nselfdrive/assets/*.png\nselfdrive/assets/*.svg\nselfdrive/assets/fonts/*.ttf\nselfdrive/assets/images/*\nselfdrive/assets/offroad/*\nselfdrive/assets/sounds/*\nselfdrive/assets/training/*\n\nphonelibs/SConscript\n\nphonelibs/nanovg/*.c\nphonelibs/nanovg/*.h\n\nphonelibs/libgralloc/**\nphonelibs/linux/**\nphonelibs/opencl/**\nphonelibs/zlib/*\nphonelibs/bzip2/*\nphonelibs/openmax/**\n\nphonelibs/json11/json11.cpp\nphonelibs/json11/json11.hpp\n\nphonelibs/qpoases/**\n\nphonelibs/qrcode/*.cc\nphonelibs/qrcode/*.hpp\n\nphonelibs/kaitai/*.h\nphonelibs/kaitai/*.cpp\n\nphonelibs/libyuv/include/**\nphonelibs/libyuv/lib/**\nphonelibs/libyuv/larch64/**\n\nphonelibs/snpe/include/**\nphonelibs/snpe/aarch64**\nphonelibs/snpe/larch64**\nphonelibs/snpe/dsp**\n\nphonelibs/android_frameworks_native/**\nphonelibs/android_hardware_libhardware/**\nphonelibs/android_system_core/**\n\ninstaller/updater/updater\ninstaller/updater/updater.cc\ninstaller/updater/update.json\ninstaller/updater/Makefile\n\nscripts/update_now.sh\nscripts/stop_updater.sh\n\npyextra/.gitignore\n\nrednose/**\n\ncereal/.gitignore\ncereal/__init__.py\ncereal/car.capnp\ncereal/legacy.capnp\ncereal/log.capnp\ncereal/services.py\ncereal/SConscript\ncereal/include/**\ncereal/logger/logger.h\ncereal/messaging/.gitignore\ncereal/messaging/__init__.py\ncereal/messaging/bridge.cc\ncereal/messaging/impl_msgq.cc\ncereal/messaging/impl_msgq.h\ncereal/messaging/impl_zmq.cc\ncereal/messaging/impl_zmq.h\ncereal/messaging/messaging.cc\ncereal/messaging/messaging.h\ncereal/messaging/messaging.pxd\ncereal/messaging/messaging_pyx.pyx\ncereal/messaging/msgq.cc\ncereal/messaging/msgq.h\ncereal/messaging/socketmaster.cc\ncereal/visionipc/.gitignore\ncereal/visionipc/__init__.py\ncereal/visionipc/*.cc\ncereal/visionipc/*.h\ncereal/visionipc/*.pyx\ncereal/visionipc/*.pxd\n\npanda/.gitignore\npanda/__init__.py\npanda/board/**\npanda/certs/**\npanda/crypto/**\npanda/examples/query_fw_versions.py\npanda/python/**\n\nopendbc/.gitignore\nopendbc/__init__.py\nopendbc/can/__init__.py\nopendbc/can/SConscript\nopendbc/can/can_define.py\nopendbc/can/common.cc\nopendbc/can/common.h\nopendbc/can/common.pxd\nopendbc/can/common_dbc.h\nopendbc/can/dbc.cc\nopendbc/can/dbc.py\nopendbc/can/dbc_template.cc\nopendbc/can/packer.cc\nopendbc/can/packer.py\nopendbc/can/packer_pyx.pyx\nopendbc/can/parser.cc\nopendbc/can/parser.py\nopendbc/can/parser_pyx.pyx\nopendbc/can/process_dbc.py\nopendbc/can/dbc_out/.gitkeep\nopendbc/can/dbc_out/.gitignore\n\nopendbc/chrysler_pacifica_2017_hybrid.dbc\nopendbc/chrysler_pacifica_2017_hybrid_private_fusion.dbc\n\nopendbc/gm_global_a_powertrain.dbc\nopendbc/gm_global_a_object.dbc\nopendbc/gm_global_a_chassis.dbc\n\nopendbc/ford_fusion_2018_pt.dbc\nopendbc/ford_fusion_2018_adas.dbc\n\nopendbc/honda_accord_2018_can_generated.dbc\nopendbc/acura_ilx_2016_can_generated.dbc\nopendbc/acura_rdx_2018_can_generated.dbc\nopendbc/acura_rdx_2020_can_generated.dbc\nopendbc/honda_civic_touring_2016_can_generated.dbc\nopendbc/honda_civic_hatchback_ex_2017_can_generated.dbc\nopendbc/honda_civic_sedan_16_diesel_2019_can_generated.dbc\nopendbc/honda_crv_touring_2016_can_generated.dbc\nopendbc/honda_crv_ex_2017_can_generated.dbc\nopendbc/honda_crv_ex_2017_body_generated.dbc\nopendbc/honda_crv_executive_2016_can_generated.dbc\nopendbc/honda_crv_hybrid_2019_can_generated.dbc\nopendbc/honda_fit_ex_2018_can_generated.dbc\nopendbc/honda_odyssey_exl_2018_generated.dbc\nopendbc/honda_odyssey_extreme_edition_2018_china_can_generated.dbc\nopendbc/honda_pilot_touring_2017_can_generated.dbc\nopendbc/honda_ridgeline_black_edition_2017_can_generated.dbc\nopendbc/honda_insight_ex_2019_can_generated.dbc\nopendbc/acura_ilx_2016_nidec.dbc\n\nopendbc/hyundai_kia_generic.dbc\n\nopendbc/mazda_2017.dbc\n\nopendbc/nissan_x_trail_2017.dbc\nopendbc/nissan_leaf_2018.dbc\n\nopendbc/subaru_global_2017_generated.dbc\nopendbc/subaru_outback_2015_generated.dbc\nopendbc/subaru_outback_2019_generated.dbc\nopendbc/subaru_forester_2017_generated.dbc\n\nopendbc/toyota_rav4_hybrid_2017_pt_generated.dbc\nopendbc/toyota_rav4_2017_pt_generated.dbc\nopendbc/toyota_prius_2017_pt_generated.dbc\nopendbc/toyota_corolla_2017_pt_generated.dbc\nopendbc/lexus_rx_350_2016_pt_generated.dbc\nopendbc/lexus_rx_hybrid_2017_pt_generated.dbc\nopendbc/toyota_nodsu_pt_generated.dbc\nopendbc/toyota_nodsu_hybrid_pt_generated.dbc\nopendbc/toyota_camry_hybrid_2018_pt_generated.dbc\nopendbc/toyota_highlander_2017_pt_generated.dbc\nopendbc/toyota_highlander_hybrid_2018_pt_generated.dbc\nopendbc/toyota_avalon_2017_pt_generated.dbc\nopendbc/toyota_sienna_xle_2018_pt_generated.dbc\nopendbc/lexus_is_2018_pt_generated.dbc\nopendbc/lexus_ct200h_2018_pt_generated.dbc\nopendbc/lexus_nx300h_2018_pt_generated.dbc\nopendbc/lexus_nx300_2018_pt_generated.dbc\nopendbc/toyota_adas.dbc\nopendbc/toyota_tss2_adas.dbc\n\nopendbc/vw_mqb_2010.dbc\n\nopendbc/tesla_can.dbc\nopendbc/tesla_radar.dbc\n"
  },
  {
    "path": "release/files_pc",
    "content": "phonelibs/mapbox-gl-native-qt/x86_64/**\n\nphonelibs/qt-plugins/x86_64/**\n"
  },
  {
    "path": "release/files_tici",
    "content": "phonelibs/mapbox-gl-native-qt/include/*\n\nselfdrive/timezoned.py\n\nselfdrive/assets/navigation/*\nselfdrive/assets/training_wide/*\nselfdrive/assets/sounds_tici/*\n\nselfdrive/camerad/cameras/camera_qcom2.cc\nselfdrive/camerad/cameras/camera_qcom2.h\nselfdrive/camerad/cameras/real_debayer.cl\n\nselfdrive/hardware/tici/__init__.py\nselfdrive/hardware/tici/hardware.h\nselfdrive/hardware/tici/hardware.py\nselfdrive/hardware/tici/pins.py\nselfdrive/hardware/tici/agnos.py\nselfdrive/hardware/tici/agnos.json\nselfdrive/hardware/tici/amplifier.py\nselfdrive/hardware/tici/updater\n\nselfdrive/ui/qt/spinner_larch64\nselfdrive/ui/qt/text_larch64\nselfdrive/ui/qt/maps/*.cc\nselfdrive/ui/qt/maps/*.h\n"
  },
  {
    "path": "release/identity.sh",
    "content": "export GIT_COMMITTER_NAME=\"Vehicle Researcher\"\nexport GIT_COMMITTER_EMAIL=\"user@comma.ai\"\nexport GIT_AUTHOR_NAME=\"Vehicle Researcher\"\nexport GIT_AUTHOR_EMAIL=\"user@comma.ai\"\nexport GIT_SSH_COMMAND=\"ssh -i /data/gitkey\"\n"
  },
  {
    "path": "scripts/complete_setup.sh",
    "content": "#!/usr/bin/bash\n\ntouch /data/data/com.termux/files/continue.sh\necho \"#!/usr/bin/bash\" >> /data/data/com.termux/files/continue.sh\necho \"cd /data/openpilot\" >> /data/data/com.termux/files/continue.sh\necho \"exec ./launch_openpilot.sh\" >> /data/data/com.termux/files/continue.sh\n\nchmod u+x /data/data/com.termux/files/continue.sh\nreboot"
  },
  {
    "path": "scripts/installers/font_installer.py",
    "content": "#!/usr/bin/env python3\nimport os\n\nif __name__ == \"__main__\":\n  install_font = False\n\n  if os.path.isfile(\"/EON\"):\n    if not os.path.isfile(\"/system/fonts/NotoSansCJKtc-Regular.otf\"):\n      os.system(\"mount -o remount,rw /system\")\n      os.system(\"rm -fr /system/fonts/NotoSansTC*.otf\")\n      os.system(\"rm -fr /system/fonts/NotoSansSC*.otf\")\n      os.system(\"rm -fr /system/fonts/NotoSansKR*.otf\")\n      os.system(\"rm -fr /system/fonts/NotoSansJP*.otf\")\n      os.system(\"cp -rf /data/openpilot/selfdrive/assets/fonts/NotoSansCJKtc-* /system/fonts/\")\n      os.system(\"cp -rf /data/openpilot/selfdrive/assets/fonts/fonts.xml /system/etc/fonts.xml\")\n      os.system(\"chmod 644 /system/etc/fonts.xml\")\n      os.system(\"chmod 644 /system/fonts/NotoSansCJKtc-*\")\n      os.system(\"mount -o remount,r /system\")\n\n  elif os.path.isfile(\"/TICI\"):\n    pass\n  else:\n    pass\n"
  },
  {
    "path": "scripts/installers/language_installer.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport subprocess\n\nif __name__ == \"__main__\":\n\n  if os.path.isfile(\"/EON\"):\n    language = subprocess.check_output([\"getprop\", \"persist.sys.locale\"], encoding='utf8').strip()\n    if language != \"\":\n      os.system(\"echo -n %s > /data/params/d/dp_locale\" % language)\n  elif os.path.isfile(\"/TICI\"):\n    pass\n  else:\n    pass\n"
  },
  {
    "path": "scripts/installers/sshkey_installer.py",
    "content": "#!/usr/bin/env python3\nimport os\n\nif __name__ == \"__main__\":\n  install_key = False\n  if os.path.isfile(\"/EON\"):\n    os.system(\"setprop persist.neos.ssh 1\")\n    os.system(\"echo -n 1 > /data/params/d/SshEnabled\")\n    if not os.path.isfile(\"/data/params/d/GithubSshKeys\"):\n      install_key = True\n    else:\n      with open('/data/params/d/GithubSshKeys') as f:\n        if f.read().strip() == \"\":\n          install_key = True\n\n    if install_key:\n      os.system(\"echo -n openpilot > /data/params/d/GithubUsername\")\n      os.system(\"cp /data/openpilot/scripts/ssh_key/setup_keys /data/params/d/GithubSshKeys\")\n\n  elif os.path.isfile(\"/TICI\"):\n    pass\n  else:\n    pass"
  },
  {
    "path": "scripts/oneplus_update_neos.sh",
    "content": "#!/usr/bin/bash\n\nif [ -z \"$BASEDIR\" ]; then\n  BASEDIR=\"/data/openpilot\"\nfi\n\nsource \"$BASEDIR/launch_env.sh\"\ncp -f \"$BASEDIR/installer/updater/update.zip\" \"/data/media/0/update.zip\" || exit\npm disable ai.comma.plus.offroad\nkillall _ui\n\"$BASEDIR/installer/updater/updater\" \"file://$BASEDIR/installer/updater/oneplus.json\"\n"
  },
  {
    "path": "scripts/rebuild.sh",
    "content": "#!/usr/bin/bash\n\nexport LD_LIBRARY_PATH=/data/data/com.termux/files/usr/lib\nexport HOME=/data/data/com.termux/files/home\nexport PATH=/usr/local/bin:/data/data/com.termux/files/usr/bin:/data/data/com.termux/files/usr/sbin:/data/data/com.termux/files/usr/bin/applets:/bin:/sbin:/vendor/bin:/system/sbin:/system/bin:/system/xbin:/data/data/com.termux/files/usr/bin/git\nprintf %s \"1\" > /data/params/d/DragonUpdating\ncd /data/openpilot || exit\n#git reset --hard @{u}\ngit clean -xdf\nrm -fr /tmp/scons_cache/\nfind . -type f -name '*.py[co]' -delete -o -type d -name __pycache__ -delete\nscons --clean\nreboot"
  },
  {
    "path": "scripts/reset_dp.sh",
    "content": "#!/usr/bin/bash\n\nexport LD_LIBRARY_PATH=/data/data/com.termux/files/usr/lib\nexport HOME=/data/data/com.termux/files/home\nexport PATH=/usr/local/bin:/data/data/com.termux/files/usr/bin:/data/data/com.termux/files/usr/sbin:/data/data/com.termux/files/usr/bin/applets:/bin:/sbin:/vendor/bin:/system/sbin:/system/bin:/system/xbin:/data/data/com.termux/files/usr/bin/git\nexport PYTHONPATH=/data/openpilot\nrm -fr /data/params/d/dp_*\nrm -fr /data/params/d/Dragon*\nreboot"
  },
  {
    "path": "scripts/reset_update.sh",
    "content": "#!/usr/bin/bash\n\nexport LD_LIBRARY_PATH=/data/data/com.termux/files/usr/lib\nexport HOME=/data/data/com.termux/files/home\nexport PATH=/usr/local/bin:/data/data/com.termux/files/usr/bin:/data/data/com.termux/files/usr/sbin:/data/data/com.termux/files/usr/bin/applets:/bin:/sbin:/vendor/bin:/system/sbin:/system/bin:/system/xbin:/data/data/com.termux/files/usr/bin/git\nexport PYTHONPATH=/data/openpilot\nrm /data/openpilot/panda/board/obj/panda.bin\ncd /data/openpilot && git fetch --all && git reset --hard @{u} && git clean -xdf && scons --clean && reboot\n"
  },
  {
    "path": "scripts/reset_usb.py",
    "content": "#!/usr/bin/env python\nimport os\nimport sys\nfrom subprocess import Popen, PIPE\nimport fcntl\n\ndef create_usb_list():\n    device_list = list()\n    try:\n        lsusb_out = Popen('lsusb -v', shell=True, bufsize=64, stdin=PIPE, stdout=PIPE, close_fds=True).stdout.read().strip().decode('utf-8')\n        usb_devices = lsusb_out.split('%s%s' % (os.linesep, os.linesep))\n        for device_categories in usb_devices:\n            if not device_categories:\n                continue\n            categories = device_categories.split(os.linesep)\n            device_stuff = categories[0].strip().split()\n            bus = device_stuff[1]\n            device = device_stuff[3][:-1]\n            device_dict = {'bus': bus, 'device': device}\n            device_info = ' '.join(device_stuff[6:])\n            device_dict['description'] = device_info\n            for category in categories:\n                if not category:\n                    continue\n                categoryinfo = category.strip().split()\n                if categoryinfo[0] == 'iManufacturer':\n                    manufacturer_info = ' '.join(categoryinfo[2:])\n                    device_dict['manufacturer'] = manufacturer_info\n                if categoryinfo[0] == 'iProduct':\n                    device_info = ' '.join(categoryinfo[2:])\n                    device_dict['device'] = device_info\n            path = '/dev/bus/usb/%s/%s' % (bus, device)\n            device_dict['path'] = path\n\n            device_list.append(device_dict)\n    except Exception as ex:\n        print('Failed to list usb devices! Error: %s' % ex)\n        sys.exit(-1)\n    return device_list\n\n\ndef kill_usb(dev_path):\n    USBDEVFS_RESET = 21780\n    try:\n        f = open(dev_path, 'w', os.O_WRONLY)\n        fcntl.ioctl(f, USBDEVFS_RESET, 0)\n        print('Successfully reset %s' % dev_path)\n        sys.exit(0)\n    except Exception as ex:\n        print('Failed to reset device! Error: %s' % ex)\n        sys.exit(-1)\n\nif __name__ == \"__main__\":\n    usb_list = create_usb_list()\n    for device in usb_list:\n        if device['manufacturer'] == 'comma.ai':\n            kill_usb(device['path'])\n    sys.exit(0)"
  },
  {
    "path": "scripts/ssh_key/id_rsa",
    "content": "-----BEGIN RSA PRIVATE KEY-----\nMIIEvAIBADANBgkqhkiG9w0BAQEFAASCBKYwggSiAgEAAoIBAQC+iXXq30Tq+J5N\nKat3KWHCzcmwZ55nGh6WggAqECa5CasBlM9VeROpVu3beA+5h0MibRgbD4DMtVXB\nt6gEvZ8nd04E7eLA9LTZyFDZ7SkSOVj4oXOQsT0GnJmKrASW5KslTWqVzTfo2XCt\nZ+004ikLxmyFeBO8NOcErW1pa8gFdQDToH9FrA7kgysic/XVESTOoe7XlzRoe/eZ\nacEQ+jtnmFd21A4aEADkk00Ahjr0uKaJiLUAPatxs2icIXWpgYtfqqtaKF23wSt6\n1OTu6cAwXbOWr3m+IUSRUO0IRzEIQS3z1jfd1svgzSgSSwZ1Lhj4AoKxIEAIc8qJ\nrO4uymCJAgMBAAECggEBAISFevxHGdoL3Z5xkw6oO5SQKO2GxEeVhRzNgmu/HA+q\nx8OryqD6O1CWY4037kft6iWxlwiLOdwna2P25ueVM3LxqdQH2KS4DmlCx+kq6FwC\ngv063fQPMhC9LpWimvaQSPEC7VUPjQlo4tPY6sTTYBUOh0A1ihRm/x7juKuQCWix\nCq8C/DVnB1X4mGj+W3nJc5TwVJtgJbbiBrq6PWrhvB/3qmkxHRL7dU2SBb2iNRF1\nLLY30dJx/cD73UDKNHrlrsjk3UJc29Mp4/MladKvUkRqNwlYxSuAtJV0nZ3+iFkL\ns3adSTHdJpClQer45R51rFDlVsDz2ZBpb/hRNRoGDuECgYEA6A1EixLq7QYOh3cb\nXhyh3W4kpVvA/FPfKH1OMy3ONOD/Y9Oa+M/wthW1wSoRL2n+uuIW5OAhTIvIEivj\n6bAZsTT3twrvOrvYu9rx9aln4p8BhyvdjeW4kS7T8FP5ol6LoOt2sTP3T1LOuJPO\nuQvOjlKPKIMh3c3RFNWTnGzMPa0CgYEA0jNiPLxP3A2nrX0keKDI+VHuvOY88gdh\n0W5BuLMLovOIDk9aQFIbBbMuW1OTjHKv9NK+Lrw+YbCFqOGf1dU/UN5gSyE8lX/Q\nFsUGUqUZx574nJZnOIcy3ONOnQLcvHAQToLFAGUd7PWgP3CtHkt9hEv2koUwL4vo\nikTP1u9Gkc0CgYEA2apoWxPZrY963XLKBxNQecYxNbLFaWq67t3rFnKm9E8BAICi\n4zUaE5J1tMVi7Vi9iks9Ml9SnNyZRQJKfQ+kaebHXbkyAaPmfv+26rqHKboA0uxA\nnDOZVwXX45zBkp6g1sdHxJx8JLoGEnkC9eyvSi0C//tRLx86OhLErXwYcNkCf1it\nVMRKrWYoXJTUNo6tRhvodM88UnnIo3u3CALjhgU4uC1RTMHV4ZCGBwiAOb8GozSl\ns5YD1E1iKwEULloHnK6BIh6P5v8q7J6uf/xdqoKMjlWBHgq6/roxKvkSPA1DOZ3l\njTadcgKFnRUmc+JT9p/ZbCxkA/ALFg8++G+0ghECgYA8vG3M/utweLvq4RI7l7U7\nb+i2BajfK2OmzNi/xugfeLjY6k2tfQGRuv6ppTjehtji2uvgDWkgjJUgPfZpir3I\nRsVMUiFgloWGHETOy0Qvc5AwtqTJFLTD1Wza2uBilSVIEsg6Y83Gickh+ejOmEsY\n6co17RFaAZHwGfCFFjO76Q==\n-----END RSA PRIVATE KEY-----\n"
  },
  {
    "path": "scripts/ssh_key/setup_keys",
    "content": "from=\"10.0.0.0/8,172.16.0.0/12,192.168.0.0/16\" ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQC+iXXq30Tq+J5NKat3KWHCzcmwZ55nGh6WggAqECa5CasBlM9VeROpVu3beA+5h0MibRgbD4DMtVXBt6gEvZ8nd04E7eLA9LTZyFDZ7SkSOVj4oXOQsT0GnJmKrASW5KslTWqVzTfo2XCtZ+004ikLxmyFeBO8NOcErW1pa8gFdQDToH9FrA7kgysic/XVESTOoe7XlzRoe/eZacEQ+jtnmFd21A4aEADkk00Ahjr0uKaJiLUAPatxs2icIXWpgYtfqqtaKF23wSt61OTu6cAwXbOWr3m+IUSRUO0IRzEIQS3z1jfd1svgzSgSSwZ1Lhj4AoKxIEAIc8qJrO4uymCJ public\n"
  },
  {
    "path": "scripts/stop_updater.sh",
    "content": "#!/usr/bin/env sh\n\n# Stop updater\npkill -2 -f selfdrive.updated\n\n# Remove pending update\nrm -f /data/safe_staging/finalized/.overlay_consistent\n"
  },
  {
    "path": "scripts/update_now.sh",
    "content": "#!/usr/bin/env sh\n\n# Send SIGHUP to updater\npkill -1 -f selfdrive.updated\n"
  },
  {
    "path": "scripts/update_panda_firmware.sh",
    "content": "#!/usr/bin/bash\n\nexport LD_LIBRARY_PATH=/data/data/com.termux/files/usr/lib\nexport HOME=/data/data/com.termux/files/home\nexport PATH=/usr/local/bin:/data/data/com.termux/files/usr/bin:/data/data/com.termux/files/usr/sbin:/data/data/com.termux/files/usr/bin/applets:/bin:/sbin:/vendor/bin:/system/sbin:/system/bin:/system/xbin:/data/data/com.termux/files/usr/bin/python\nexport PYTHONPATH=/data/openpilot\nrm /data/openpilot/panda/board/obj/panda.bin\ncd /data/openpilot/panda || exit ; pkill -f boardd ; python -c \"from panda import Panda; Panda().flash()\" && reboot"
  },
  {
    "path": "scripts/vw.sh",
    "content": "#!/usr/bin/bash\n\nif [ $1 -eq 1 ]; then\n  printf %s \"1\" > /data/params/d/dp_vw_panda\nfi\nif [ $1 -eq 0 ]; then\n  printf %s \"0\" > /data/params/d/dp_vw_panda\nfi\nrm /data/openpilot/panda/board/obj/panda.bin"
  },
  {
    "path": "selfdrive/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/assets/.gitignore",
    "content": "*.cc\n"
  },
  {
    "path": "selfdrive/assets/assets.qrc",
    "content": "<!DOCTYPE RCC><RCC version=\"1.0\">\n<qresource>\n  <file>img_continue_triangle.svg</file>\n  <file>img_circled_check.svg</file>\n  <file>img_circled_slash.svg</file>\n  <file>img_eye_open.svg</file>\n  <file>img_eye_closed.svg</file>\n  <file>offroad/icon_lock_closed.svg</file>\n  <file>offroad/icon_checkmark.svg</file>\n  <file>offroad/icon_wifi_strength_low.svg</file>\n  <file>offroad/icon_wifi_strength_medium.svg</file>\n  <file>offroad/icon_wifi_strength_high.svg</file>\n  <file>offroad/icon_wifi_strength_full.svg</file>\n</qresource>\n</RCC>\n"
  },
  {
    "path": "selfdrive/assets/fonts/fonts.xml",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<!--\n    NOTE: this is the newer (L) version of the system font configuration,\n    supporting richer weight selection. Some apps will expect the older\n    version, so please keep system_fonts.xml and fallback_fonts.xml in sync\n    with any changes, even though framework will only read this file.\n\n    All fonts withohut names are added to the default list. Fonts are chosen\n    based on a match: full BCP-47 language tag including script, then just\n    language, and finally order (the first font containing the glyph).\n\n    Order of appearance is also the tiebreaker for weight matching. This is\n    the reason why the 900 weights of Roboto precede the 700 weights - we\n    prefer the former when an 800 weight is requested. Since bold spans\n    effectively add 300 to the weight, this ensures that 900 is the bold\n    paired with the 500 weight, ensuring adequate contrast.\n-->\n<familyset version=\"22\">\n    <!-- first font is default -->\n    <family name=\"sans-serif\">\n        <font weight=\"100\" style=\"normal\">Roboto-Thin.ttf</font>\n        <font weight=\"100\" style=\"italic\">Roboto-ThinItalic.ttf</font>\n        <font weight=\"300\" style=\"normal\">Roboto-Light.ttf</font>\n        <font weight=\"300\" style=\"italic\">Roboto-LightItalic.ttf</font>\n        <font weight=\"400\" style=\"normal\">Roboto-Regular.ttf</font>\n        <font weight=\"400\" style=\"italic\">Roboto-Italic.ttf</font>\n        <font weight=\"500\" style=\"normal\">Roboto-Medium.ttf</font>\n        <font weight=\"500\" style=\"italic\">Roboto-MediumItalic.ttf</font>\n        <font weight=\"900\" style=\"normal\">Roboto-Black.ttf</font>\n        <font weight=\"900\" style=\"italic\">Roboto-BlackItalic.ttf</font>\n        <font weight=\"700\" style=\"normal\">Roboto-Bold.ttf</font>\n        <font weight=\"700\" style=\"italic\">Roboto-BoldItalic.ttf</font>\n    </family>\n\n    <!-- Note that aliases must come after the fonts they reference. -->\n    <alias name=\"sans-serif-thin\" to=\"sans-serif\" weight=\"100\" />\n    <alias name=\"sans-serif-light\" to=\"sans-serif\" weight=\"300\" />\n    <alias name=\"sans-serif-medium\" to=\"sans-serif\" weight=\"500\" />\n    <alias name=\"sans-serif-black\" to=\"sans-serif\" weight=\"900\" />\n    <alias name=\"arial\" to=\"sans-serif\" />\n    <alias name=\"helvetica\" to=\"sans-serif\" />\n    <alias name=\"tahoma\" to=\"sans-serif\" />\n    <alias name=\"verdana\" to=\"sans-serif\" />\n\n    <family name=\"sans-serif-condensed\">\n        <font weight=\"300\" style=\"normal\">RobotoCondensed-Light.ttf</font>\n        <font weight=\"300\" style=\"italic\">RobotoCondensed-LightItalic.ttf</font>\n        <font weight=\"400\" style=\"normal\">RobotoCondensed-Regular.ttf</font>\n        <font weight=\"400\" style=\"italic\">RobotoCondensed-Italic.ttf</font>\n        <font weight=\"700\" style=\"normal\">RobotoCondensed-Bold.ttf</font>\n        <font weight=\"700\" style=\"italic\">RobotoCondensed-BoldItalic.ttf</font>\n    </family>\n    <alias name=\"sans-serif-condensed-light\" to=\"sans-serif-condensed\" weight=\"300\" />\n\n    <family name=\"serif\">\n        <font weight=\"400\" style=\"normal\">NotoSerif-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSerif-Bold.ttf</font>\n        <font weight=\"400\" style=\"italic\">NotoSerif-Italic.ttf</font>\n        <font weight=\"700\" style=\"italic\">NotoSerif-BoldItalic.ttf</font>\n    </family>\n    <alias name=\"times\" to=\"serif\" />\n    <alias name=\"times new roman\" to=\"serif\" />\n    <alias name=\"palatino\" to=\"serif\" />\n    <alias name=\"georgia\" to=\"serif\" />\n    <alias name=\"baskerville\" to=\"serif\" />\n    <alias name=\"goudy\" to=\"serif\" />\n    <alias name=\"fantasy\" to=\"serif\" />\n    <alias name=\"ITC Stone Serif\" to=\"serif\" />\n\n    <family name=\"monospace\">\n        <font weight=\"400\" style=\"normal\">DroidSansMono.ttf</font>\n    </family>\n    <alias name=\"sans-serif-monospace\" to=\"monospace\" />\n    <alias name=\"monaco\" to=\"monospace\" />\n\n    <family name=\"serif-monospace\">\n        <font weight=\"400\" style=\"normal\">CutiveMono.ttf</font>\n    </family>\n    <alias name=\"courier\" to=\"serif-monospace\" />\n    <alias name=\"courier new\" to=\"serif-monospace\" />\n\n    <family name=\"casual\">\n        <font weight=\"400\" style=\"normal\">ComingSoon.ttf</font>\n    </family>\n\n    <family name=\"cursive\">\n        <font weight=\"400\" style=\"normal\">DancingScript-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">DancingScript-Bold.ttf</font>\n    </family>\n\n    <family name=\"sans-serif-smallcaps\">\n        <font weight=\"400\" style=\"normal\">CarroisGothicSC-Regular.ttf</font>\n    </family>\n\n    <!-- fallback fonts -->\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoNaskhArabic-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoNaskhArabic-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoNaskhArabicUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoNaskhArabicUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansEthiopic-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansEthiopic-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansHebrew-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansHebrew-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansThai-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansThai-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansThaiUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansThaiUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansArmenian-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansArmenian-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansGeorgian-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGeorgian-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansDevanagari-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansDevanagari-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansDevanagariUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansDevanagariUI-Bold.ttf</font>\n    </family>\n    <!-- Gujarati should come after Devanagari -->\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansGujarati-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGujarati-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansGujaratiUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGujaratiUI-Bold.ttf</font>\n    </family>\n    <!-- Gurmukhi should come after Devanagari -->\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansGurmukhi-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGurmukhi-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansGurmukhiUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGurmukhiUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansTamil-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTamil-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansTamilUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTamilUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansMalayalam-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMalayalam-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansMalayalamUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMalayalamUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansBengali-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansBengali-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansBengaliUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansBengaliUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansTelugu-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTelugu-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansTeluguUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTeluguUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansKannada-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKannada-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansKannadaUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKannadaUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansOriya-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansOriya-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansOriyaUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansOriyaUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSinhala-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansSinhala-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansKhmer-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKhmer-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansKhmerUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKhmerUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansLao-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansLao-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansLaoUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansLaoUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansMyanmar-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMyanmar-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansMyanmarUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMyanmarUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansThaana-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansThaana-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCham-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansCham-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBalinese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBamum-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBatak-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBuginese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBuhid-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCanadianAboriginal-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCherokee-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCoptic-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansGlagolitic-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansHanunoo-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansJavanese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansKayahLi-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansLepcha-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansLimbu-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansLisu-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansMandaic-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansMeeteiMayek-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansNewTaiLue-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansNKo-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansOlChiki-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansRejang-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSaurashtra-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSundanese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSylotiNagri-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSyriacEstrangela-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTagbanwa-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTaiTham-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTaiViet-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTibetan-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTifinagh-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansVai-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansYi-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSymbols-Regular-Subsetted.ttf</font>\n    </family>\n    <family lang=\"ja\">\n        <font weight=\"400\" style=\"normal\">NotoSansJP-Regular.otf</font>\n    </family>\n    <family lang=\"ko\">\n        <font weight=\"400\" style=\"normal\">NotoSansKR-Regular.otf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NanumGothic.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoColorEmoji.ttf</font>\n    </family>\n    <family lang=\"zh-Hans\">\n        <font weight=\"400\" style=\"normal\">NotoSansCJKtc-Regular.otf</font>\n        <font weight=\"500\" style=\"normal\">NotoSansCJKtc-Medium.otf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansCJKtc-Bold.otf</font>\n    </family>\n    <family lang=\"zh-Hant\">\n        <font weight=\"400\" style=\"normal\">NotoSansCJKtc-Regular.otf</font>\n        <font weight=\"500\" style=\"normal\">NotoSansCJKtc-Medium.otf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansCJKtc-Bold.otf</font>\n    </family>\n    <family lang=\"ja\">\n        <font weight=\"400\" style=\"normal\">MTLmr3m.ttf</font>\n    </family>\n    <!--\n        Tai Le and Mongolian are intentionally kept last, to make sure they don't override\n        the East Asian punctuation for Chinese.\n    -->\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTaiLe-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansMongolian-Regular.ttf</font>\n    </family>\n</familyset>\n"
  },
  {
    "path": "selfdrive/assets/locales/events.pot",
    "content": "# SOME DESCRIPTIVE TITLE.\n# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER\n# This file is distributed under the same license as the PACKAGE package.\n# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.\n#\n#, fuzzy\nmsgid \"\"\nmsgstr \"\"\n\"Project-Id-Version: PACKAGE VERSION\\n\"\n\"Report-Msgid-Bugs-To: \\n\"\n\"POT-Creation-Date: 2020-10-15 13:37+1000\\n\"\n\"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\\n\"\n\"Last-Translator: FULL NAME <EMAIL@ADDRESS>\\n\"\n\"Language-Team: LANGUAGE <LL@li.org>\\n\"\n\"Language: \\n\"\n\"MIME-Version: 1.0\\n\"\n\"Content-Type: text/plain; charset=CHARSET\\n\"\n\"Content-Transfer-Encoding: 8bit\\n\"\n\n#: selfdrive/controls/lib/events.py:153\nmsgid \"openpilot Unavailable\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:160 selfdrive/controls/lib/events.py:167\nmsgid \"TAKE CONTROL IMMEDIATELY\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:187 selfdrive/controls/lib/events.py:328\n#: selfdrive/controls/lib/events.py:354 selfdrive/controls/lib/events.py:418\n#: selfdrive/controls/lib/events.py:470 selfdrive/controls/lib/events.py:522\n#: selfdrive/controls/lib/events.py:532\nmsgid \"TAKE CONTROL\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:188\n#, python-format\nmsgid \"Steer Unavailable Below %(speed)d %(unit)s\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:196\n#, python-format\nmsgid \"Calibration in Progress: %d%%\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:197\n#, python-format\nmsgid \"Drive Above %(speed)d %(unit)s\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:204\nmsgid \"Poor GPS reception\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"If sky is visible, contact support\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"Check GPS antenna placement\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:210\nmsgid \"Cruise Mode Disabled\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:212\nmsgid \"Main Switch Off\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:222\nmsgid \"DEBUG ALERT\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:230\nmsgid \"Be ready to take over at any time\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:231 selfdrive/controls/lib/events.py:239\n#: selfdrive/controls/lib/events.py:247 selfdrive/controls/lib/events.py:255\nmsgid \"Always keep hands on wheel and eyes on road\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:238\nmsgid \"WARNING: This branch is not tested\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:246\nmsgid \"Dashcam mode\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:254\nmsgid \"Dashcam mode for unsupported car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:262\nmsgid \"Unsupported Giraffe Configuration\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:263\nmsgid \"Visit comma.ai/tg\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:270\nmsgid \"White Panda Is No Longer Supported\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:271\nmsgid \"Upgrade to comma two or black panda\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:274\nmsgid \"White panda is no longer supported\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:279\nmsgid \"Stock LKAS is turned on\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:280\nmsgid \"Turn off stock LKAS to engage\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:288\nmsgid \"Community Feature Detected\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:289\nmsgid \"Enable Community Features in Developer Settings\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:296\nmsgid \"Dashcam Mode\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:297\nmsgid \"Car Unrecognized\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:304 selfdrive/controls/lib/events.py:312\n#: selfdrive/controls/lib/events.py:320\nmsgid \"BRAKE!\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:305\nmsgid \"Stock AEB: Risk of Collision\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:313\nmsgid \"Stock FCW: Risk of Collision\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:321\nmsgid \"Risk of Collision\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:329\nmsgid \"Lane Departure Detected\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:338\nmsgid \"openpilot will not brake while gas pressed\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:346\nmsgid \"Vehicle Parameter Identification Failed\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:355 selfdrive/controls/lib/events.py:523\n#: selfdrive/controls/lib/events.py:526\nmsgid \"Steering Temporarily Unavailable\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:362\nmsgid \"KEEP EYES ON ROAD: Driver Distracted\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:370\nmsgid \"KEEP EYES ON ROAD\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:371\nmsgid \"Driver Appears Distracted\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:378 selfdrive/controls/lib/events.py:402\nmsgid \"DISENGAGE IMMEDIATELY\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:379\nmsgid \"Driver Was Distracted\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:386\nmsgid \"TOUCH STEERING WHEEL: No Face Detected\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:394\nmsgid \"TOUCH STEERING WHEEL\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:395\nmsgid \"Driver Is Unresponsive\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:403\nmsgid \"Driver Was Unresponsive\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:410\nmsgid \"CHECK DRIVER FACE VISIBILITY\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:411\nmsgid \"Driver Monitor Model Output Uncertain\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:419\nmsgid \"Resume Driving Manually\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:426\nmsgid \"STOPPED\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:427\nmsgid \"Press Resume to Move\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:438\nmsgid \"Steer Left to Start Lane Change\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:439 selfdrive/controls/lib/events.py:447\n#: selfdrive/controls/lib/events.py:455 selfdrive/controls/lib/events.py:463\n#: selfdrive/controls/lib/events.py:802 selfdrive/controls/lib/events.py:810\nmsgid \"Monitor Other Vehicles\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:446\nmsgid \"Steer Right to Start Lane Change\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:454\nmsgid \"Car Detected in Blindspot\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:462\nmsgid \"Changing Lane\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:471\nmsgid \"Turn Exceeds Steering Limit\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:496\nmsgid \"Brake Hold Active\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:501\nmsgid \"Park Brake Engaged\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:506\nmsgid \"Pedal Pressed During Attempt\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:517\nmsgid \"Enable Adaptive Cruise\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:533\nmsgid \"Attempting Refocus: Camera Focus Invalid\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:539\nmsgid \"Out of Storage Space\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:544\nmsgid \"Speed Too Low\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:549 selfdrive/controls/lib/events.py:553\nmsgid \"NEOS Update Required\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:550\nmsgid \"Please Wait for Update\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:558 selfdrive/controls/lib/events.py:562\nmsgid \"No Data from Device Sensors\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:559 selfdrive/controls/lib/events.py:572\n#: selfdrive/controls/lib/events.py:669\nmsgid \"Reboot your Device\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:571 selfdrive/controls/lib/events.py:575\nmsgid \"Speaker not found\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:579\nmsgid \"Distraction Level Too High\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:583\nmsgid \"System Overheated\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:584\nmsgid \"System overheated\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:588 selfdrive/controls/lib/events.py:589\nmsgid \"Gear not D\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:594\nmsgid \"Calibration Invalid\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:595\nmsgid \"Reposition Device and Recalibrate\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:598 selfdrive/controls/lib/events.py:599\nmsgid \"Calibration Invalid: Reposition Device & Recalibrate\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:603 selfdrive/controls/lib/events.py:605\nmsgid \"Calibration in Progress\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:609\nmsgid \"Door Open\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:610\nmsgid \"Door open\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:614\nmsgid \"Seatbelt Unlatched\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:615\nmsgid \"Seatbelt unlatched\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:619 selfdrive/controls/lib/events.py:620\nmsgid \"ESP Off\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:624 selfdrive/controls/lib/events.py:625\nmsgid \"Low Battery\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:629 selfdrive/controls/lib/events.py:630\nmsgid \"Communication Issue between Processes\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:635 selfdrive/controls/lib/events.py:636\nmsgid \"Radar Communication Issue\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:641 selfdrive/controls/lib/events.py:642\n#: selfdrive/controls/lib/events.py:646 selfdrive/controls/lib/events.py:647\nmsgid \"Radar Error: Restart the Car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:651 selfdrive/controls/lib/events.py:652\nmsgid \"Driving model lagging\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:656 selfdrive/controls/lib/events.py:657\nmsgid \"Vision Model Output Uncertain\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:661 selfdrive/controls/lib/events.py:662\nmsgid \"Device Fell Off Mount\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:666 selfdrive/controls/lib/events.py:672\nmsgid \"Low Memory: Reboot Your Device\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:668\nmsgid \"RAM Critically Low\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:677 selfdrive/controls/lib/events.py:678\nmsgid \"Controls Failed\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:682\nmsgid \"Controls Mismatch\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:686 selfdrive/controls/lib/events.py:688\n#: selfdrive/controls/lib/events.py:692\nmsgid \"CAN Error: Check Connections\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:696 selfdrive/controls/lib/events.py:702\nmsgid \"LKAS Fault: Restart the Car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:698\nmsgid \"LKAS Fault: Restart the car to engage\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:706 selfdrive/controls/lib/events.py:712\n#: selfdrive/controls/lib/events.py:795\nmsgid \"Cruise Fault: Restart the Car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:708 selfdrive/controls/lib/events.py:791\nmsgid \"Cruise Fault: Restart the car to engage\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:716\nmsgid \"Gas Fault: Restart the Car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:717\nmsgid \"Gas Error: Restart the Car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:722\nmsgid \"\"\n\"Reverse\\n\"\n\"Gear\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:726\nmsgid \"Reverse Gear\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:731\nmsgid \"Cruise Is Off\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:735 selfdrive/controls/lib/events.py:736\nmsgid \"Planner Solution Error\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:740 selfdrive/controls/lib/events.py:742\n#: selfdrive/controls/lib/events.py:746\nmsgid \"Harness Malfunction\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:743\nmsgid \"Please Check Hardware\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:751 selfdrive/controls/lib/events.py:760\nmsgid \"openpilot Canceled\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:752\nmsgid \"No close lead car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:755\nmsgid \"No Close Lead Car\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:761\nmsgid \"Speed too low\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:768 selfdrive/controls/lib/events.py:773\nmsgid \"Speed Too High\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:769\nmsgid \"Slow down to resume operation\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:774\nmsgid \"Slow down to engage\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:781\nmsgid \"Please connect to Internet\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:782\nmsgid \"An Update Check Is Required to Engage\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:785\nmsgid \"Please Connect to Internet\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:801\nmsgid \"Left ALC will start in 3s\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:809\nmsgid \"Right ALC will start in 3s\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:817\nmsgid \"STEERING REQUIRED: Lane Keeping OFF\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:825\nmsgid \"STEERING REQUIRED: Blinkers ON\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:833 selfdrive/controls/lib/events.py:838\nmsgid \"Lead Car Is Moving\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:847\nmsgid \"WARNING\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:848\nmsgid \"Grab wheel to start bypass\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:855\nmsgid \"BYPASSING\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:856\nmsgid \"HOLD WHEEL\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:863\nmsgid \"Bypassed!\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:864\nmsgid \"Release wheel when ready\"\nmsgstr \"\"\n"
  },
  {
    "path": "selfdrive/assets/locales/ja-JP/LC_MESSAGES/events.po",
    "content": "# SOME DESCRIPTIVE TITLE.\n# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER\n# This file is distributed under the same license as the PACKAGE package.\n# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.\n#\nmsgid \"\"\nmsgstr \"\"\n\"Project-Id-Version: PACKAGE VERSION\\n\"\n\"Report-Msgid-Bugs-To: \\n\"\n\"POT-Creation-Date: 2020-10-15 13:37+1000\\n\"\n\"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\\n\"\n\"Last-Translator: nikkurie <@nikkurie>\\n\"\n\"Language-Team: LANGUAGE <LL@li.org>\\n\"\n\"Language: ja-JP\\n\"\n\"MIME-Version: 1.0\\n\"\n\"Content-Type: text/plain; charset=UTF-8\\n\"\n\"Content-Transfer-Encoding: 8bit\\n\"\n\n#: selfdrive/controls/lib/events.py:153\nmsgid \"openpilot Unavailable\"\nmsgstr \"オープンパイロットは利用できません\"\n\n#: selfdrive/controls/lib/events.py:160 selfdrive/controls/lib/events.py:167\nmsgid \"TAKE CONTROL IMMEDIATELY\"\nmsgstr \"すぐにハンドルを持って\"\n\n#: selfdrive/controls/lib/events.py:187 selfdrive/controls/lib/events.py:328\n#: selfdrive/controls/lib/events.py:354 selfdrive/controls/lib/events.py:418\n#: selfdrive/controls/lib/events.py:470 selfdrive/controls/lib/events.py:522\n#: selfdrive/controls/lib/events.py:532\nmsgid \"TAKE CONTROL\"\nmsgstr \"ハンドルを持って\"\n\n#: selfdrive/controls/lib/events.py:188\n#, fuzzy, python-format\nmsgid \"Steer Unavailable Below %(speed)d %(unit)s\"\nmsgstr \"横の制御が無効になり速度が以下になります\"\n\n#: selfdrive/controls/lib/events.py:196\n#, fuzzy, python-format\nmsgid \"Calibration in Progress: %d%%\"\nmsgstr \"キャリブレーション中:\"\n\n#: selfdrive/controls/lib/events.py:197\n#, python-format\nmsgid \"Drive Above %(speed)d %(unit)s\"\nmsgstr \"%(speed)d %(unit)s 制限速度以上の運転をしてください\"\n\n#: selfdrive/controls/lib/events.py:204\nmsgid \"Poor GPS reception\"\nmsgstr \"GPS受信不良\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"If sky is visible, contact support\"\nmsgstr \"地下・トンネルでない場合は、カスタマーサービスに連絡ください\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"Check GPS antenna placement\"\nmsgstr \"GPSアンテナの位置を確認してください。\"\n\n#: selfdrive/controls/lib/events.py:210\nmsgid \"Cruise Mode Disabled\"\nmsgstr \"クルーズモードをオフ\"\n\n#: selfdrive/controls/lib/events.py:212\nmsgid \"Main Switch Off\"\nmsgstr \"メインスイッチをオフ\"\n\n#: selfdrive/controls/lib/events.py:222\nmsgid \"DEBUG ALERT\"\nmsgstr \"テストメッセージを削除\"\n\n#: selfdrive/controls/lib/events.py:230\nmsgid \"Be ready to take over at any time\"\nmsgstr \"いつでも引き継げるよう準備しておいてください。\"\n\n#: selfdrive/controls/lib/events.py:231 selfdrive/controls/lib/events.py:239\n#: selfdrive/controls/lib/events.py:247 selfdrive/controls/lib/events.py:255\nmsgid \"Always keep hands on wheel and eyes on road\"\nmsgstr \"常にハンドルに触れ、道路から目を離さない\"\n\n#: selfdrive/controls/lib/events.py:238\nmsgid \"WARNING: This branch is not tested\"\nmsgstr \"警告: このブランチはテストされていません\"\n\n#: selfdrive/controls/lib/events.py:246\nmsgid \"Dashcam mode\"\nmsgstr \"ダッシュカムモード\"\n\n#: selfdrive/controls/lib/events.py:254\nmsgid \"Dashcam mode for unsupported car\"\nmsgstr \"未対応車のためダッシュカムモードのみ\"\n\n#: selfdrive/controls/lib/events.py:262\nmsgid \"Unsupported Giraffe Configuration\"\nmsgstr \"サポートされていないGiraffeの設定\"\n\n#: selfdrive/controls/lib/events.py:263\nmsgid \"Visit comma.ai/tg\"\nmsgstr \"comma.ai/tg を参照\"\n\n#: selfdrive/controls/lib/events.py:270\nmsgid \"White Panda Is No Longer Supported\"\nmsgstr \"ホワイトパンダはサポート終了しました\"\n\n#: selfdrive/controls/lib/events.py:271\nmsgid \"Upgrade to comma two or black panda\"\nmsgstr \"コンマ2やブラックパンダにアップグレード\"\n\n#: selfdrive/controls/lib/events.py:274\nmsgid \"White panda is no longer supported\"\nmsgstr \"ホワイトパンダはサポート終了しました\"\n\n#: selfdrive/controls/lib/events.py:279\nmsgid \"Stock LKAS is turned on\"\nmsgstr \"純正LKASがオン\"\n\n#: selfdrive/controls/lib/events.py:280\nmsgid \"Turn off stock LKAS to engage\"\nmsgstr \"純正LKASをオフにしてエンゲージ\"\n\n#: selfdrive/controls/lib/events.py:288\nmsgid \"Community Feature Detected\"\nmsgstr \"コミュニティ開発の機能を検出\"\n\n#: selfdrive/controls/lib/events.py:289\nmsgid \"Enable Community Features in Developer Settings\"\nmsgstr \"開発者設定でコミュニティ機能を有効にする\"\n\n#: selfdrive/controls/lib/events.py:296\nmsgid \"Dashcam Mode\"\nmsgstr \"ダッシュカムモード\"\n\n#: selfdrive/controls/lib/events.py:297\nmsgid \"Car Unrecognized\"\nmsgstr \"認識できない車\"\n\n#: selfdrive/controls/lib/events.py:304 selfdrive/controls/lib/events.py:312\n#: selfdrive/controls/lib/events.py:320\nmsgid \"BRAKE!\"\nmsgstr \"ブレーキ！\"\n\n#: selfdrive/controls/lib/events.py:305\nmsgid \"Stock AEB: Risk of Collision\"\nmsgstr \"衝突の危険\"\n\n#: selfdrive/controls/lib/events.py:313\nmsgid \"Stock FCW: Risk of Collision\"\nmsgstr \"衝突の危険\"\n\n#: selfdrive/controls/lib/events.py:321\nmsgid \"Risk of Collision\"\nmsgstr \"衝突の危険\"\n\n#: selfdrive/controls/lib/events.py:329\nmsgid \"Lane Departure Detected\"\nmsgstr \"車線逸脱を検知\"\n\n#: selfdrive/controls/lib/events.py:338\nmsgid \"openpilot will not brake while gas pressed\"\nmsgstr \"アクセル中、オープンパイロットはブレーキをかけません\"\n\n#: selfdrive/controls/lib/events.py:346\nmsgid \"Vehicle Parameter Identification Failed\"\nmsgstr \"車両パラメータの識別に失敗しました。\"\n\n#: selfdrive/controls/lib/events.py:355 selfdrive/controls/lib/events.py:523\n#: selfdrive/controls/lib/events.py:526\nmsgid \"Steering Temporarily Unavailable\"\nmsgstr \"ステアリングは一時的に利用不可\"\n\n#: selfdrive/controls/lib/events.py:362\nmsgid \"KEEP EYES ON ROAD: Driver Distracted\"\nmsgstr \"道路から目を離さないで:注意散漫です\"\n\n#: selfdrive/controls/lib/events.py:370\nmsgid \"KEEP EYES ON ROAD\"\nmsgstr \"道路から目を離さないで\"\n\n#: selfdrive/controls/lib/events.py:371\nmsgid \"Driver Appears Distracted\"\nmsgstr \"ドライバーは注意散漫に見えます\"\n\n#: selfdrive/controls/lib/events.py:378 selfdrive/controls/lib/events.py:402\nmsgid \"DISENGAGE IMMEDIATELY\"\nmsgstr \"すぐに解除してください\"\n\n#: selfdrive/controls/lib/events.py:379\nmsgid \"Driver Was Distracted\"\nmsgstr \"ドライバーは注意力散漫\"\n\n#: selfdrive/controls/lib/events.py:386\nmsgid \"TOUCH STEERING WHEEL: No Face Detected\"\nmsgstr \"ハンドルに触れて:顔が検出できない\"\n\n#: selfdrive/controls/lib/events.py:394\nmsgid \"TOUCH STEERING WHEEL\"\nmsgstr \"ハンドルに触れて\"\n\n#: selfdrive/controls/lib/events.py:395\nmsgid \"Driver Is Unresponsive\"\nmsgstr \"ドライバーが無反応\"\n\n#: selfdrive/controls/lib/events.py:403\nmsgid \"Driver Was Unresponsive\"\nmsgstr \"ドライバーが無反応でした\"\n\n#: selfdrive/controls/lib/events.py:410\nmsgid \"CHECK DRIVER FACE VISIBILITY\"\nmsgstr \"ドライバーの顔の視認性を確認\"\n\n#: selfdrive/controls/lib/events.py:411\nmsgid \"Driver Monitor Model Output Uncertain\"\nmsgstr \"ドライバー監視モデルが不完全\"\n\n#: selfdrive/controls/lib/events.py:419\nmsgid \"Resume Driving Manually\"\nmsgstr \"手動で運転を再開\"\n\n#: selfdrive/controls/lib/events.py:426\nmsgid \"STOPPED\"\nmsgstr \"停止\"\n\n#: selfdrive/controls/lib/events.py:427\nmsgid \"Press Resume to Move\"\nmsgstr \"Resumeを押して移動します。\"\n\n#: selfdrive/controls/lib/events.py:438\nmsgid \"Steer Left to Start Lane Change\"\nmsgstr \"左ハンドルで車線変更を開始\"\n\n#: selfdrive/controls/lib/events.py:439 selfdrive/controls/lib/events.py:447\n#: selfdrive/controls/lib/events.py:455 selfdrive/controls/lib/events.py:463\n#: selfdrive/controls/lib/events.py:802 selfdrive/controls/lib/events.py:810\nmsgid \"Monitor Other Vehicles\"\nmsgstr \"他の車両を監視\"\n\n#: selfdrive/controls/lib/events.py:446\nmsgid \"Steer Right to Start Lane Change\"\nmsgstr \"右ハンドルで車線変更を開始\"\n\n#: selfdrive/controls/lib/events.py:454\nmsgid \"Car Detected in Blindspot\"\nmsgstr \"ブラインドスポットで車両を発見\"\n\n#: selfdrive/controls/lib/events.py:462\nmsgid \"Changing Lane\"\nmsgstr \"レーンチェンジ中\"\n\n#: selfdrive/controls/lib/events.py:471\nmsgid \"Turn Exceeds Steering Limit\"\nmsgstr \"ステアリングリミットを超えています\"\n\n#: selfdrive/controls/lib/events.py:496\nmsgid \"Brake Hold Active\"\nmsgstr \"サイドブレーキが作動\"\n\n#: selfdrive/controls/lib/events.py:501\nmsgid \"Park Brake Engaged\"\nmsgstr \"サイドブレーキ作動中\"\n\n#: selfdrive/controls/lib/events.py:506\nmsgid \"Pedal Pressed During Attempt\"\nmsgstr \"ペダル/ブレーキを検出\"\n\n#: selfdrive/controls/lib/events.py:517\nmsgid \"Enable Adaptive Cruise\"\nmsgstr \"ACCを有効化\"\n\n#: selfdrive/controls/lib/events.py:533\nmsgid \"Attempting Refocus: Camera Focus Invalid\"\nmsgstr \"再フォーカス中です\"\n\n#: selfdrive/controls/lib/events.py:539\nmsgid \"Out of Storage Space\"\nmsgstr \"空き容量不足\"\n\n#: selfdrive/controls/lib/events.py:544\nmsgid \"Speed Too Low\"\nmsgstr \"速度が遅すぎます\"\n\n#: selfdrive/controls/lib/events.py:549 selfdrive/controls/lib/events.py:553\nmsgid \"NEOS Update Required\"\nmsgstr \"NEOSの更新が必要\"\n\n#: selfdrive/controls/lib/events.py:550\nmsgid \"Please Wait for Update\"\nmsgstr \"更新をお待ちください\"\n\n#: selfdrive/controls/lib/events.py:558 selfdrive/controls/lib/events.py:562\nmsgid \"No Data from Device Sensors\"\nmsgstr \"デバイスセンサからのデータがありません\"\n\n#: selfdrive/controls/lib/events.py:559 selfdrive/controls/lib/events.py:572\n#: selfdrive/controls/lib/events.py:669\nmsgid \"Reboot your Device\"\nmsgstr \"デバイスを再起動\"\n\n#: selfdrive/controls/lib/events.py:571 selfdrive/controls/lib/events.py:575\nmsgid \"Speaker not found\"\nmsgstr \"スピーカーが見つかりません\"\n\n#: selfdrive/controls/lib/events.py:579\nmsgid \"Distraction Level Too High\"\nmsgstr \"注意力散漫すぎます\"\n\n#: selfdrive/controls/lib/events.py:583\nmsgid \"System Overheated\"\nmsgstr \"オーバーヒート\"\n\n#: selfdrive/controls/lib/events.py:584\nmsgid \"System overheated\"\nmsgstr \"オーバーヒート\"\n\n#: selfdrive/controls/lib/events.py:588 selfdrive/controls/lib/events.py:589\nmsgid \"Gear not D\"\nmsgstr \"Dではない\"\n\n#: selfdrive/controls/lib/events.py:594\n#, fuzzy\nmsgid \"Calibration Invalid\"\nmsgstr \"キャリブレーション\"\n\n#: selfdrive/controls/lib/events.py:595\n#, fuzzy\nmsgid \"Reposition Device and Recalibrate\"\nmsgstr \"キャリブレーションが無効です。再実行してください。\"\n\n#: selfdrive/controls/lib/events.py:598 selfdrive/controls/lib/events.py:599\nmsgid \"Calibration Invalid: Reposition Device & Recalibrate\"\nmsgstr \"キャリブレーションが無効です。再実行してください。\"\n\n#: selfdrive/controls/lib/events.py:603 selfdrive/controls/lib/events.py:605\nmsgid \"Calibration in Progress\"\nmsgstr \"キャリブレーション\"\n\n#: selfdrive/controls/lib/events.py:609\nmsgid \"Door Open\"\nmsgstr \"ドアが開いています\"\n\n#: selfdrive/controls/lib/events.py:610\nmsgid \"Door open\"\nmsgstr \"ドアが開いています\"\n\n#: selfdrive/controls/lib/events.py:614\nmsgid \"Seatbelt Unlatched\"\nmsgstr \"シートベルト未着用\"\n\n#: selfdrive/controls/lib/events.py:615\nmsgid \"Seatbelt unlatched\"\nmsgstr \"シートベルト未着用\"\n\n#: selfdrive/controls/lib/events.py:619 selfdrive/controls/lib/events.py:620\nmsgid \"ESP Off\"\nmsgstr \"ESPオフ\"\n\n#: selfdrive/controls/lib/events.py:624 selfdrive/controls/lib/events.py:625\nmsgid \"Low Battery\"\nmsgstr \"低バッテリー\"\n\n#: selfdrive/controls/lib/events.py:629 selfdrive/controls/lib/events.py:630\nmsgid \"Communication Issue between Processes\"\nmsgstr \"プロセス間の通信の問題\"\n\n#: selfdrive/controls/lib/events.py:635 selfdrive/controls/lib/events.py:636\nmsgid \"Radar Communication Issue\"\nmsgstr \"レーダー通信問題\"\n\n#: selfdrive/controls/lib/events.py:641 selfdrive/controls/lib/events.py:642\n#: selfdrive/controls/lib/events.py:646 selfdrive/controls/lib/events.py:647\nmsgid \"Radar Error: Restart the Car\"\nmsgstr \"レーダーエラー:車を再起動\"\n\n#: selfdrive/controls/lib/events.py:651 selfdrive/controls/lib/events.py:652\nmsgid \"Driving model lagging\"\nmsgstr \"制御モデルに遅延がある\"\n\n#: selfdrive/controls/lib/events.py:656 selfdrive/controls/lib/events.py:657\nmsgid \"Vision Model Output Uncertain\"\nmsgstr \"映像が不明瞭です\"\n\n#: selfdrive/controls/lib/events.py:661 selfdrive/controls/lib/events.py:662\nmsgid \"Device Fell Off Mount\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:666 selfdrive/controls/lib/events.py:672\nmsgid \"Low Memory: Reboot Your Device\"\nmsgstr \"ローメモリ:デバイスを再起動\"\n\n#: selfdrive/controls/lib/events.py:668\nmsgid \"RAM Critically Low\"\nmsgstr \"RAMが致命的に低い\"\n\n#: selfdrive/controls/lib/events.py:677 selfdrive/controls/lib/events.py:678\nmsgid \"Controls Failed\"\nmsgstr \"制御失敗\"\n\n#: selfdrive/controls/lib/events.py:682\nmsgid \"Controls Mismatch\"\nmsgstr \"制御不一致\"\n\n#: selfdrive/controls/lib/events.py:686 selfdrive/controls/lib/events.py:688\n#: selfdrive/controls/lib/events.py:692\nmsgid \"CAN Error: Check Connections\"\nmsgstr \"CANエラー:接続を確認\"\n\n#: selfdrive/controls/lib/events.py:696 selfdrive/controls/lib/events.py:702\nmsgid \"LKAS Fault: Restart the Car\"\nmsgstr \"LKASの故障:車を再起動\"\n\n#: selfdrive/controls/lib/events.py:698\nmsgid \"LKAS Fault: Restart the car to engage\"\nmsgstr \"LKASの故障:車を再起動後発進\"\n\n#: selfdrive/controls/lib/events.py:706 selfdrive/controls/lib/events.py:712\n#: selfdrive/controls/lib/events.py:795\nmsgid \"Cruise Fault: Restart the Car\"\nmsgstr \"クルーズ失敗:車を再起動\"\n\n#: selfdrive/controls/lib/events.py:708 selfdrive/controls/lib/events.py:791\nmsgid \"Cruise Fault: Restart the car to engage\"\nmsgstr \"クルーズ失敗:車を再起動後発進\"\n\n#: selfdrive/controls/lib/events.py:716\nmsgid \"Gas Fault: Restart the Car\"\nmsgstr \"アクセル故障:車を再起動\"\n\n#: selfdrive/controls/lib/events.py:717\nmsgid \"Gas Error: Restart the Car\"\nmsgstr \"アクセルエラー:車を再起動\"\n\n#: selfdrive/controls/lib/events.py:722\n#, fuzzy\nmsgid \"\"\n\"Reverse\\n\"\n\"Gear\"\nmsgstr \"Rに切り替え\"\n\n#: selfdrive/controls/lib/events.py:726\nmsgid \"Reverse Gear\"\nmsgstr \"Rに切り替え\"\n\n#: selfdrive/controls/lib/events.py:731\nmsgid \"Cruise Is Off\"\nmsgstr \"クルーズコントロールオフ\"\n\n#: selfdrive/controls/lib/events.py:735 selfdrive/controls/lib/events.py:736\nmsgid \"Planner Solution Error\"\nmsgstr \"Planner Solution エラー\"\n\n#: selfdrive/controls/lib/events.py:740 selfdrive/controls/lib/events.py:742\n#: selfdrive/controls/lib/events.py:746\nmsgid \"Harness Malfunction\"\nmsgstr \"ハーネスが故障\"\n\n#: selfdrive/controls/lib/events.py:743\nmsgid \"Please Check Hardware\"\nmsgstr \"ハードウェアを確認して\"\n\n#: selfdrive/controls/lib/events.py:751 selfdrive/controls/lib/events.py:760\nmsgid \"openpilot Canceled\"\nmsgstr \"オープンパイロットはキャンセルされました\"\n\n#: selfdrive/controls/lib/events.py:752\nmsgid \"No close lead car\"\nmsgstr \"リードカー不在\"\n\n#: selfdrive/controls/lib/events.py:755\nmsgid \"No Close Lead Car\"\nmsgstr \"リードカー不在\"\n\n#: selfdrive/controls/lib/events.py:761\nmsgid \"Speed too low\"\nmsgstr \"速度が遅すぎる\"\n\n#: selfdrive/controls/lib/events.py:768 selfdrive/controls/lib/events.py:773\nmsgid \"Speed Too High\"\nmsgstr \"速度が速すぎる\"\n\n#: selfdrive/controls/lib/events.py:769\nmsgid \"Slow down to resume operation\"\nmsgstr \"速度を下げてオープンパイロットを再開\"\n\n#: selfdrive/controls/lib/events.py:774\nmsgid \"Slow down to engage\"\nmsgstr \"速度を落として発進\"\n\n#: selfdrive/controls/lib/events.py:781\nmsgid \"Please connect to Internet\"\nmsgstr \"インターネット接続を確認\"\n\n#: selfdrive/controls/lib/events.py:782\nmsgid \"An Update Check Is Required to Engage\"\nmsgstr \"発進するには更新が必要です\"\n\n#: selfdrive/controls/lib/events.py:785\nmsgid \"Please Connect to Internet\"\nmsgstr \"インターネット接続を確認\"\n\n#: selfdrive/controls/lib/events.py:801\nmsgid \"Left ALC will start in 3s\"\nmsgstr \"左車線に移動します\"\n\n#: selfdrive/controls/lib/events.py:809\nmsgid \"Right ALC will start in 3s\"\nmsgstr \"右車線に移動します\"\n\n#: selfdrive/controls/lib/events.py:817\nmsgid \"STEERING REQUIRED: Lane Keeping OFF\"\nmsgstr \"操作が必要:レーンキープオフ\"\n\n#: selfdrive/controls/lib/events.py:825\nmsgid \"STEERING REQUIRED: Blinkers ON\"\nmsgstr \"操作が必要:ウインカーオン\"\n\n#: selfdrive/controls/lib/events.py:833 selfdrive/controls/lib/events.py:838\nmsgid \"Lead Car Is Moving\"\nmsgstr \"リードカーが移動しました\"\n\n#: selfdrive/controls/lib/events.py:847\nmsgid \"WARNING\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:848\nmsgid \"Grab wheel to start bypass\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:855\nmsgid \"BYPASSING\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:856\nmsgid \"HOLD WHEEL\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:863\nmsgid \"Bypassed!\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:864\nmsgid \"Release wheel when ready\"\nmsgstr \"\"\n\n#~ msgid \"Drive Above\"\n#~ msgstr \"制限速度以上の運転をしてください\"\n"
  },
  {
    "path": "selfdrive/assets/locales/ko-KR/LC_MESSAGES/events.po",
    "content": "# SOME DESCRIPTIVE TITLE.\n# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER\n# This file is distributed under the same license as the PACKAGE package.\n# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.\n#\n#, fuzzy\nmsgid \"\"\nmsgstr \"\"\n\"Project-Id-Version: PACKAGE VERSION\\n\"\n\"Report-Msgid-Bugs-To: \\n\"\n\"POT-Creation-Date: 2020-10-15 13:37+1000\\n\"\n\"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\\n\"\n\"Last-Translator: FULL NAME <EMAIL@ADDRESS>\\n\"\n\"Language-Team: LANGUAGE <LL@li.org>\\n\"\n\"Language: ko-KR\\n\"\n\"MIME-Version: 1.0\\n\"\n\"Content-Type: text/plain; charset=UTF-8\\n\"\n\"Content-Transfer-Encoding: 8bit\\n\"\n\n#: selfdrive/controls/lib/events.py:153\nmsgid \"openpilot Unavailable\"\nmsgstr \"오픈파일럿 사용불가\"\n\n#: selfdrive/controls/lib/events.py:160 selfdrive/controls/lib/events.py:167\nmsgid \"TAKE CONTROL IMMEDIATELY\"\nmsgstr \"핸들을 잡아주세요\"\n\n#: selfdrive/controls/lib/events.py:187 selfdrive/controls/lib/events.py:328\n#: selfdrive/controls/lib/events.py:354 selfdrive/controls/lib/events.py:418\n#: selfdrive/controls/lib/events.py:470 selfdrive/controls/lib/events.py:522\n#: selfdrive/controls/lib/events.py:532\nmsgid \"TAKE CONTROL\"\nmsgstr \"핸들을 잡아주세요\"\n\n#: selfdrive/controls/lib/events.py:188\n#, fuzzy, python-format\nmsgid \"Steer Unavailable Below %(speed)d %(unit)s\"\nmsgstr \"%d %s 이하에서는 조향제어가 불가합니다\"\n\n#: selfdrive/controls/lib/events.py:196\n#, fuzzy, python-format\nmsgid \"Calibration in Progress: %d%%\"\nmsgstr \"캘리브레이션 진행중: %d%%\"\n\n#: selfdrive/controls/lib/events.py:197\n#, fuzzy, python-format\nmsgid \"Drive Above %(speed)d %(unit)s\"\nmsgstr \"%(speed)d %(unit)s 이상의 속도로 주행하세요\"\n\n#: selfdrive/controls/lib/events.py:204\nmsgid \"Poor GPS reception\"\nmsgstr \"GPS 신호 약함\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"If sky is visible, contact support\"\nmsgstr \"환경에 문제가 없을경우 서비스팀에 연락하세요\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"Check GPS antenna placement\"\nmsgstr \"GPS안테나 위치를 점검하세요\"\n\n#: selfdrive/controls/lib/events.py:210\nmsgid \"Cruise Mode Disabled\"\nmsgstr \"크루즈 모드 꺼짐\"\n\n#: selfdrive/controls/lib/events.py:212\nmsgid \"Main Switch Off\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:222\nmsgid \"DEBUG ALERT\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:230\nmsgid \"Be ready to take over at any time\"\nmsgstr \"오픈파일럿 사용준비가 되었습니다\"\n\n#: selfdrive/controls/lib/events.py:231 selfdrive/controls/lib/events.py:239\n#: selfdrive/controls/lib/events.py:247 selfdrive/controls/lib/events.py:255\nmsgid \"Always keep hands on wheel and eyes on road\"\nmsgstr \"안전운전을 위해 항상 핸들을 잡고 도로교통 상황을 주시하세요\"\n\n#: selfdrive/controls/lib/events.py:238\nmsgid \"WARNING: This branch is not tested\"\nmsgstr \"경고: 이 Branch는 테스트되지 않았습니다\"\n\n#: selfdrive/controls/lib/events.py:246\nmsgid \"Dashcam mode\"\nmsgstr \"대시캠 모드\"\n\n#: selfdrive/controls/lib/events.py:254\nmsgid \"Dashcam mode for unsupported car\"\nmsgstr \"안전운전을 위해 항상 핸들을 잡고 도로교통 상황을 주시하세요\"\n\n#: selfdrive/controls/lib/events.py:262\nmsgid \"Unsupported Giraffe Configuration\"\nmsgstr \"지원되지 않는 지라프 설정\"\n\n#: selfdrive/controls/lib/events.py:263\nmsgid \"Visit comma.ai/tg\"\nmsgstr \"comma.ai/tg 방문하세요\"\n\n#: selfdrive/controls/lib/events.py:270\nmsgid \"White Panda Is No Longer Supported\"\nmsgstr \"화이트판다는 더 이상 지원되지 않습니다\"\n\n#: selfdrive/controls/lib/events.py:271\nmsgid \"Upgrade to comma two or black panda\"\nmsgstr \"콤마2나 블랙판다로 업그레이드 하세요\"\n\n#: selfdrive/controls/lib/events.py:274\nmsgid \"White panda is no longer supported\"\nmsgstr \"화이트판다는 더 이상 지원되지 않습니다\"\n\n#: selfdrive/controls/lib/events.py:279\nmsgid \"Stock LKAS is turned on\"\nmsgstr \"차량의 LKAS 기능이 켜져 있습니다\"\n\n#: selfdrive/controls/lib/events.py:280\nmsgid \"Turn off stock LKAS to engage\"\nmsgstr \"오픈파일럿 사용을 위해 LKAS를 끄세요\"\n\n#: selfdrive/controls/lib/events.py:288\nmsgid \"Community Feature Detected\"\nmsgstr \"커뮤니티 기능 감지됨\"\n\n#: selfdrive/controls/lib/events.py:289\nmsgid \"Enable Community Features in Developer Settings\"\nmsgstr \"개발자 설정에서 커뮤니티 기능을 활성화하세요\"\n\n#: selfdrive/controls/lib/events.py:296\nmsgid \"Dashcam Mode\"\nmsgstr \"대시캠 모드\"\n\n#: selfdrive/controls/lib/events.py:297\nmsgid \"Car Unrecognized\"\nmsgstr \"미인식 차량\"\n\n#: selfdrive/controls/lib/events.py:304 selfdrive/controls/lib/events.py:312\n#: selfdrive/controls/lib/events.py:320\nmsgid \"BRAKE!\"\nmsgstr \"브레이크!\"\n\n#: selfdrive/controls/lib/events.py:305\nmsgid \"Stock AEB: Risk of Collision\"\nmsgstr \"순정 AEB: 충돌 위험\"\n\n#: selfdrive/controls/lib/events.py:313\nmsgid \"Stock FCW: Risk of Collision\"\nmsgstr \"순정 FCW: 충돌 위험\"\n\n#: selfdrive/controls/lib/events.py:321\nmsgid \"Risk of Collision\"\nmsgstr \"충돌 위험\"\n\n#: selfdrive/controls/lib/events.py:329\nmsgid \"Lane Departure Detected\"\nmsgstr \"차선이탈이 감지되었습니다\"\n\n#: selfdrive/controls/lib/events.py:338\nmsgid \"openpilot will not brake while gas pressed\"\nmsgstr \"가속중에는 오픈파일럿 브레이크 작동불가\"\n\n#: selfdrive/controls/lib/events.py:346\nmsgid \"Vehicle Parameter Identification Failed\"\nmsgstr \"차량 매개 변수 식별 실패\"\n\n#: selfdrive/controls/lib/events.py:355 selfdrive/controls/lib/events.py:523\n#: selfdrive/controls/lib/events.py:526\nmsgid \"Steering Temporarily Unavailable\"\nmsgstr \"조향제어가 일시적으로 비활성화 되었습니다\"\n\n#: selfdrive/controls/lib/events.py:362\nmsgid \"KEEP EYES ON ROAD: Driver Distracted\"\nmsgstr \"도로상황에 주의를 기울이세요\"\n\n#: selfdrive/controls/lib/events.py:370\nmsgid \"KEEP EYES ON ROAD\"\nmsgstr \"도로상황에 주의하세요\"\n\n#: selfdrive/controls/lib/events.py:371\nmsgid \"Driver Appears Distracted\"\nmsgstr \"전방주시 필요\"\n\n#: selfdrive/controls/lib/events.py:378 selfdrive/controls/lib/events.py:402\nmsgid \"DISENGAGE IMMEDIATELY\"\nmsgstr \"경고: 조향제어가 즉시 해제됩니다\"\n\n#: selfdrive/controls/lib/events.py:379\nmsgid \"Driver Was Distracted\"\nmsgstr \"운전자 전방주시 불안\"\n\n#: selfdrive/controls/lib/events.py:386\nmsgid \"TOUCH STEERING WHEEL: No Face Detected\"\nmsgstr \"핸들을 터치하세요: 모니터링 없음\"\n\n#: selfdrive/controls/lib/events.py:394\nmsgid \"TOUCH STEERING WHEEL\"\nmsgstr \"핸들을 터치하세요\"\n\n#: selfdrive/controls/lib/events.py:395\nmsgid \"Driver Is Unresponsive\"\nmsgstr \"운전자 모니터링 없음\"\n\n#: selfdrive/controls/lib/events.py:403\nmsgid \"Driver Was Unresponsive\"\nmsgstr \"운전자 모니터링 없음\"\n\n#: selfdrive/controls/lib/events.py:410\nmsgid \"CHECK DRIVER FACE VISIBILITY\"\nmsgstr \"운전자 얼굴 확인 중\"\n\n#: selfdrive/controls/lib/events.py:411\nmsgid \"Driver Monitor Model Output Uncertain\"\nmsgstr \"운전자 얼굴 인식이 어렵습니다\"\n\n#: selfdrive/controls/lib/events.py:419\nmsgid \"Resume Driving Manually\"\nmsgstr \"수동으로 재출발 하세요\"\n\n#: selfdrive/controls/lib/events.py:426\nmsgid \"STOPPED\"\nmsgstr \"잠시멈춤\"\n\n#: selfdrive/controls/lib/events.py:427\nmsgid \"Press Resume to Move\"\nmsgstr \"재출발을 위해 RES버튼을 누르세요\"\n\n#: selfdrive/controls/lib/events.py:438\nmsgid \"Steer Left to Start Lane Change\"\nmsgstr \"차선 변경을 위해 핸들을 좌측으로 살짝 돌리세요\"\n\n#: selfdrive/controls/lib/events.py:439 selfdrive/controls/lib/events.py:447\n#: selfdrive/controls/lib/events.py:455 selfdrive/controls/lib/events.py:463\n#: selfdrive/controls/lib/events.py:802 selfdrive/controls/lib/events.py:810\nmsgid \"Monitor Other Vehicles\"\nmsgstr \"다른 차량에 주의하세요\"\n\n#: selfdrive/controls/lib/events.py:446\nmsgid \"Steer Right to Start Lane Change\"\nmsgstr \"차선 변경을 위해 핸들을 우측으로 살짝 돌리세요\"\n\n#: selfdrive/controls/lib/events.py:454\nmsgid \"Car Detected in Blindspot\"\nmsgstr \"측면 차량 접근 중\"\n\n#: selfdrive/controls/lib/events.py:462\nmsgid \"Changing Lane\"\nmsgstr \"차선 변경 중\"\n\n#: selfdrive/controls/lib/events.py:471\nmsgid \"Turn Exceeds Steering Limit\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:496\nmsgid \"Brake Hold Active\"\nmsgstr \"브레이크 홀드 중\"\n\n#: selfdrive/controls/lib/events.py:501\nmsgid \"Park Brake Engaged\"\nmsgstr \"파킹브레이크 체결 됨\"\n\n#: selfdrive/controls/lib/events.py:506\nmsgid \"Pedal Pressed During Attempt\"\nmsgstr \"시작 중 페달 밟음\"\n\n#: selfdrive/controls/lib/events.py:517\nmsgid \"Enable Adaptive Cruise\"\nmsgstr \"어댑티브 크루즈를 활성화하세요\"\n\n#: selfdrive/controls/lib/events.py:533\nmsgid \"Attempting Refocus: Camera Focus Invalid\"\nmsgstr \"카메라 포커스 조정중: 카메라 포커스 부정확\"\n\n#: selfdrive/controls/lib/events.py:539\nmsgid \"Out of Storage Space\"\nmsgstr \"저장공간 부족\"\n\n#: selfdrive/controls/lib/events.py:544\nmsgid \"Speed Too Low\"\nmsgstr \"차량의 속도 낮음\"\n\n#: selfdrive/controls/lib/events.py:549 selfdrive/controls/lib/events.py:553\nmsgid \"NEOS Update Required\"\nmsgstr \"NEOS 업데이트 필요\"\n\n#: selfdrive/controls/lib/events.py:550\nmsgid \"Please Wait for Update\"\nmsgstr \"업데이트를 위해 기다리세요\"\n\n#: selfdrive/controls/lib/events.py:558 selfdrive/controls/lib/events.py:562\nmsgid \"No Data from Device Sensors\"\nmsgstr \"EON센서로부터 데이터를 받지 못했습니다\"\n\n#: selfdrive/controls/lib/events.py:559 selfdrive/controls/lib/events.py:572\n#: selfdrive/controls/lib/events.py:669\nmsgid \"Reboot your Device\"\nmsgstr \"장치를 재시작 하세요\"\n\n#: selfdrive/controls/lib/events.py:571 selfdrive/controls/lib/events.py:575\nmsgid \"Speaker not found\"\nmsgstr \"스피커를 찾을 수 없습니다\"\n\n#: selfdrive/controls/lib/events.py:579\nmsgid \"Distraction Level Too High\"\nmsgstr \"운전자 전방주시 매우 불안\"\n\n#: selfdrive/controls/lib/events.py:583\nmsgid \"System Overheated\"\nmsgstr \"시스템이 과열되었습니다\"\n\n#: selfdrive/controls/lib/events.py:584\nmsgid \"System overheated\"\nmsgstr \"시스템이 과열되었습니다\"\n\n#: selfdrive/controls/lib/events.py:588 selfdrive/controls/lib/events.py:589\nmsgid \"Gear not D\"\nmsgstr \"기어가 드라이브모드가 아닙니다\"\n\n#: selfdrive/controls/lib/events.py:594\n#, fuzzy\nmsgid \"Calibration Invalid\"\nmsgstr \"캘리브레이션 진행 중\"\n\n#: selfdrive/controls/lib/events.py:595\n#, fuzzy\nmsgid \"Reposition Device and Recalibrate\"\nmsgstr \"캘리브레이션 유효하지 않음: 장치 위치 조정 및 재 캘리브레이션\"\n\n#: selfdrive/controls/lib/events.py:598 selfdrive/controls/lib/events.py:599\nmsgid \"Calibration Invalid: Reposition Device & Recalibrate\"\nmsgstr \"캘리브레이션 유효하지 않음: 장치 위치 조정 및 재 캘리브레이션\"\n\n#: selfdrive/controls/lib/events.py:603 selfdrive/controls/lib/events.py:605\nmsgid \"Calibration in Progress\"\nmsgstr \"캘리브레이션 진행 중\"\n\n#: selfdrive/controls/lib/events.py:609\nmsgid \"Door Open\"\nmsgstr \"도어가 열려있습니다\"\n\n#: selfdrive/controls/lib/events.py:610\nmsgid \"Door open\"\nmsgstr \"도어가 열려있습니다\"\n\n#: selfdrive/controls/lib/events.py:614\nmsgid \"Seatbelt Unlatched\"\nmsgstr \"안전벨트를 체결하세요\"\n\n#: selfdrive/controls/lib/events.py:615\nmsgid \"Seatbelt unlatched\"\nmsgstr \"안전벨트를 체결하세요\"\n\n#: selfdrive/controls/lib/events.py:619 selfdrive/controls/lib/events.py:620\nmsgid \"ESP Off\"\nmsgstr \"ESP 꺼짐\"\n\n#: selfdrive/controls/lib/events.py:624 selfdrive/controls/lib/events.py:625\nmsgid \"Low Battery\"\nmsgstr \"배터리 부족\"\n\n#: selfdrive/controls/lib/events.py:629 selfdrive/controls/lib/events.py:630\nmsgid \"Communication Issue between Processes\"\nmsgstr \"프로세스 간 통신 오류가 있습니다\"\n\n#: selfdrive/controls/lib/events.py:635 selfdrive/controls/lib/events.py:636\nmsgid \"Radar Communication Issue\"\nmsgstr \"레이더 오류: 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:641 selfdrive/controls/lib/events.py:642\n#: selfdrive/controls/lib/events.py:646 selfdrive/controls/lib/events.py:647\nmsgid \"Radar Error: Restart the Car\"\nmsgstr \"레이더 오류: 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:651 selfdrive/controls/lib/events.py:652\nmsgid \"Driving model lagging\"\nmsgstr \"주행 모델 지연\"\n\n#: selfdrive/controls/lib/events.py:656 selfdrive/controls/lib/events.py:657\nmsgid \"Vision Model Output Uncertain\"\nmsgstr \"전방 영상 인식 불안\"\n\n#: selfdrive/controls/lib/events.py:661 selfdrive/controls/lib/events.py:662\nmsgid \"Device Fell Off Mount\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:666 selfdrive/controls/lib/events.py:672\nmsgid \"Low Memory: Reboot Your Device\"\nmsgstr \"메모리 부족: 장치를 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:668\nmsgid \"RAM Critically Low\"\nmsgstr \"메모리 부족 심각\"\n\n#: selfdrive/controls/lib/events.py:677 selfdrive/controls/lib/events.py:678\nmsgid \"Controls Failed\"\nmsgstr \"차량제어 불가\"\n\n#: selfdrive/controls/lib/events.py:682\nmsgid \"Controls Mismatch\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:686 selfdrive/controls/lib/events.py:688\n#: selfdrive/controls/lib/events.py:692\nmsgid \"CAN Error: Check Connections\"\nmsgstr \"CAN 오류: CAN 신호를 확인하세요\"\n\n#: selfdrive/controls/lib/events.py:696 selfdrive/controls/lib/events.py:702\nmsgid \"LKAS Fault: Restart the Car\"\nmsgstr \"LKAS 오류: 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:698\nmsgid \"LKAS Fault: Restart the car to engage\"\nmsgstr \"LKAS 오류: 시작을 위해 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:706 selfdrive/controls/lib/events.py:712\n#: selfdrive/controls/lib/events.py:795\nmsgid \"Cruise Fault: Restart the Car\"\nmsgstr \"크루즈 오류: 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:708 selfdrive/controls/lib/events.py:791\nmsgid \"Cruise Fault: Restart the car to engage\"\nmsgstr \"크루즈 오류: 시작을 위해 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:716\nmsgid \"Gas Fault: Restart the Car\"\nmsgstr \"가속페달 오류: 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:717\nmsgid \"Gas Error: Restart the Car\"\nmsgstr \"가속페달 오류: 차량을 재시작하세요\"\n\n#: selfdrive/controls/lib/events.py:722\n#, fuzzy\nmsgid \"\"\n\"Reverse\\n\"\n\"Gear\"\nmsgstr \"후진 기어\"\n\n#: selfdrive/controls/lib/events.py:726\nmsgid \"Reverse Gear\"\nmsgstr \"후진 기어\"\n\n#: selfdrive/controls/lib/events.py:731\nmsgid \"Cruise Is Off\"\nmsgstr \"크루즈 꺼짐\"\n\n#: selfdrive/controls/lib/events.py:735 selfdrive/controls/lib/events.py:736\nmsgid \"Planner Solution Error\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:740 selfdrive/controls/lib/events.py:742\n#: selfdrive/controls/lib/events.py:746\nmsgid \"Harness Malfunction\"\nmsgstr \"하네스 오작동\"\n\n#: selfdrive/controls/lib/events.py:743\nmsgid \"Please Check Hardware\"\nmsgstr \"장치를 점검하세요\"\n\n#: selfdrive/controls/lib/events.py:751 selfdrive/controls/lib/events.py:760\nmsgid \"openpilot Canceled\"\nmsgstr \"오픈파일럿 시작불가\"\n\n#: selfdrive/controls/lib/events.py:752\nmsgid \"No close lead car\"\nmsgstr \"선행차량이 없습니다\"\n\n#: selfdrive/controls/lib/events.py:755\nmsgid \"No Close Lead Car\"\nmsgstr \"선행차량이 없습니다\"\n\n#: selfdrive/controls/lib/events.py:761\nmsgid \"Speed too low\"\nmsgstr \"선행차량이 없습니다\"\n\n#: selfdrive/controls/lib/events.py:768 selfdrive/controls/lib/events.py:773\nmsgid \"Speed Too High\"\nmsgstr \"속도가 너무 높습니다\"\n\n#: selfdrive/controls/lib/events.py:769\nmsgid \"Slow down to resume operation\"\nmsgstr \"재 작동을 위해 차량의 속도를 낮추세요\"\n\n#: selfdrive/controls/lib/events.py:774\nmsgid \"Slow down to engage\"\nmsgstr \"시작을 위해 차량의 속도를 낮추세요\"\n\n#: selfdrive/controls/lib/events.py:781\nmsgid \"Please connect to Internet\"\nmsgstr \"인터넷에 연결하세요\"\n\n#: selfdrive/controls/lib/events.py:782\nmsgid \"An Update Check Is Required to Engage\"\nmsgstr \"시작을 위해 업데이트를 확인해야 합니다\"\n\n#: selfdrive/controls/lib/events.py:785\nmsgid \"Please Connect to Internet\"\nmsgstr \"인터넷에 연결하세요\"\n\n#: selfdrive/controls/lib/events.py:801\nmsgid \"Left ALC will start in 3s\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:809\nmsgid \"Right ALC will start in 3s\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:817\nmsgid \"STEERING REQUIRED: Lane Keeping OFF\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:825\nmsgid \"STEERING REQUIRED: Blinkers ON\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:833 selfdrive/controls/lib/events.py:838\nmsgid \"Lead Car Is Moving\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:847\nmsgid \"WARNING\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:848\nmsgid \"Grab wheel to start bypass\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:855\nmsgid \"BYPASSING\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:856\nmsgid \"HOLD WHEEL\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:863\nmsgid \"Bypassed!\"\nmsgstr \"\"\n\n#: selfdrive/controls/lib/events.py:864\nmsgid \"Release wheel when ready\"\nmsgstr \"\"\n"
  },
  {
    "path": "selfdrive/assets/locales/zh-CN/LC_MESSAGES/events.po",
    "content": "# SOME DESCRIPTIVE TITLE.\n# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER\n# This file is distributed under the same license as the PACKAGE package.\n# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.\n#\nmsgid \"\"\nmsgstr \"\"\n\"Project-Id-Version: PACKAGE VERSION\\n\"\n\"Report-Msgid-Bugs-To: \\n\"\n\"POT-Creation-Date: 2020-10-15 13:37+1000\\n\"\n\"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\\n\"\n\"Last-Translator: Rick Lan <ricklan@gmail.com>\\n\"\n\"Language-Team: LANGUAGE <LL@li.org>\\n\"\n\"Language: zh-CN\\n\"\n\"MIME-Version: 1.0\\n\"\n\"Content-Type: text/plain; charset=UTF-8\\n\"\n\"Content-Transfer-Encoding: 8bit\\n\"\n\n#: selfdrive/controls/lib/events.py:153\nmsgid \"openpilot Unavailable\"\nmsgstr \"无法使用 openpilot\"\n\n#: selfdrive/controls/lib/events.py:160 selfdrive/controls/lib/events.py:167\nmsgid \"TAKE CONTROL IMMEDIATELY\"\nmsgstr \"即刻接管控制\"\n\n#: selfdrive/controls/lib/events.py:187 selfdrive/controls/lib/events.py:328\n#: selfdrive/controls/lib/events.py:354 selfdrive/controls/lib/events.py:418\n#: selfdrive/controls/lib/events.py:470 selfdrive/controls/lib/events.py:522\n#: selfdrive/controls/lib/events.py:532\nmsgid \"TAKE CONTROL\"\nmsgstr \"接管控制\"\n\n#: selfdrive/controls/lib/events.py:188\n#, fuzzy, python-format\nmsgid \"Steer Unavailable Below %(speed)d %(unit)s\"\nmsgstr \"横向控制暂时失效，车速低于 %d %s\"\n\n#: selfdrive/controls/lib/events.py:196\n#, fuzzy, python-format\nmsgid \"Calibration in Progress: %d%%\"\nmsgstr \"正在校准中：%d%%\"\n\n#: selfdrive/controls/lib/events.py:197\n#, fuzzy, python-format\nmsgid \"Drive Above %(speed)d %(unit)s\"\nmsgstr \"车速请高于 %(speed)d %(unit)s\"\n\n#: selfdrive/controls/lib/events.py:204\nmsgid \"Poor GPS reception\"\nmsgstr \"GPS 讯号不良\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"If sky is visible, contact support\"\nmsgstr \"如果您不在地下室/隧道，请联系客服\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"Check GPS antenna placement\"\nmsgstr \"请检查 GPS 天线位置\"\n\n#: selfdrive/controls/lib/events.py:210\nmsgid \"Cruise Mode Disabled\"\nmsgstr \"巡航模式关闭\"\n\n#: selfdrive/controls/lib/events.py:212\nmsgid \"Main Switch Off\"\nmsgstr \"主开关已关闭\"\n\n#: selfdrive/controls/lib/events.py:222\nmsgid \"DEBUG ALERT\"\nmsgstr \"除错用警示讯息\"\n\n#: selfdrive/controls/lib/events.py:230\nmsgid \"Be ready to take over at any time\"\nmsgstr \"请准备好随时接管\"\n\n#: selfdrive/controls/lib/events.py:231 selfdrive/controls/lib/events.py:239\n#: selfdrive/controls/lib/events.py:247 selfdrive/controls/lib/events.py:255\nmsgid \"Always keep hands on wheel and eyes on road\"\nmsgstr \"将手放在方向盘上并持续监视路况\"\n\n#: selfdrive/controls/lib/events.py:238\nmsgid \"WARNING: This branch is not tested\"\nmsgstr \"注意：这个分支未经过测试\"\n\n#: selfdrive/controls/lib/events.py:246\nmsgid \"Dashcam mode\"\nmsgstr \"行车记录模式\"\n\n#: selfdrive/controls/lib/events.py:254\nmsgid \"Dashcam mode for unsupported car\"\nmsgstr \"行车记录模式 (尚未支援车种)\"\n\n#: selfdrive/controls/lib/events.py:262\nmsgid \"Unsupported Giraffe Configuration\"\nmsgstr \"未支援的 Giraffe 设置\"\n\n#: selfdrive/controls/lib/events.py:263\nmsgid \"Visit comma.ai/tg\"\nmsgstr \"请查阅 comma.ai/tg\"\n\n#: selfdrive/controls/lib/events.py:270\nmsgid \"White Panda Is No Longer Supported\"\nmsgstr \"不再支持 White Panda\"\n\n#: selfdrive/controls/lib/events.py:271\nmsgid \"Upgrade to comma two or black panda\"\nmsgstr \"请升级至 comma two 或是使用 black panda\"\n\n#: selfdrive/controls/lib/events.py:274\nmsgid \"White panda is no longer supported\"\nmsgstr \"不再支持 White panda\"\n\n#: selfdrive/controls/lib/events.py:279\nmsgid \"Stock LKAS is turned on\"\nmsgstr \"原厂 LKAS 已开启\"\n\n#: selfdrive/controls/lib/events.py:280\nmsgid \"Turn off stock LKAS to engage\"\nmsgstr \"需关闭原厂 LKAS 才能启用\"\n\n#: selfdrive/controls/lib/events.py:288\nmsgid \"Community Feature Detected\"\nmsgstr \"检测到社群开发功能\"\n\n#: selfdrive/controls/lib/events.py:289\nmsgid \"Enable Community Features in Developer Settings\"\nmsgstr \"请至开发人员设定裡启用社群开发功能\"\n\n#: selfdrive/controls/lib/events.py:296\nmsgid \"Dashcam Mode\"\nmsgstr \"行车记录模式\"\n\n#: selfdrive/controls/lib/events.py:297\nmsgid \"Car Unrecognized\"\nmsgstr \"无法辨识车款\"\n\n#: selfdrive/controls/lib/events.py:304 selfdrive/controls/lib/events.py:312\n#: selfdrive/controls/lib/events.py:320\nmsgid \"BRAKE!\"\nmsgstr \"刹车！\"\n\n#: selfdrive/controls/lib/events.py:305\nmsgid \"Stock AEB: Risk of Collision\"\nmsgstr \"有碰撞的风险\"\n\n#: selfdrive/controls/lib/events.py:313\nmsgid \"Stock FCW: Risk of Collision\"\nmsgstr \"有碰撞的风险\"\n\n#: selfdrive/controls/lib/events.py:321\nmsgid \"Risk of Collision\"\nmsgstr \"有碰撞的风险\"\n\n#: selfdrive/controls/lib/events.py:329\nmsgid \"Lane Departure Detected\"\nmsgstr \"偏离车道\"\n\n#: selfdrive/controls/lib/events.py:338\nmsgid \"openpilot will not brake while gas pressed\"\nmsgstr \"在您踩着油门的时候 openpilot 将不会刹车\"\n\n#: selfdrive/controls/lib/events.py:346\nmsgid \"Vehicle Parameter Identification Failed\"\nmsgstr \"车子参数识别失败\"\n\n#: selfdrive/controls/lib/events.py:355 selfdrive/controls/lib/events.py:523\n#: selfdrive/controls/lib/events.py:526\nmsgid \"Steering Temporarily Unavailable\"\nmsgstr \"横向控制暂时失效\"\n\n#: selfdrive/controls/lib/events.py:362\nmsgid \"KEEP EYES ON ROAD: Driver Distracted\"\nmsgstr \"注意路况：驾驶分心\"\n\n#: selfdrive/controls/lib/events.py:370\nmsgid \"KEEP EYES ON ROAD\"\nmsgstr \"注意路况\"\n\n#: selfdrive/controls/lib/events.py:371\nmsgid \"Driver Appears Distracted\"\nmsgstr \"驾驶分心\"\n\n#: selfdrive/controls/lib/events.py:378 selfdrive/controls/lib/events.py:402\nmsgid \"DISENGAGE IMMEDIATELY\"\nmsgstr \"立即解除\"\n\n#: selfdrive/controls/lib/events.py:379\nmsgid \"Driver Was Distracted\"\nmsgstr \"驾驶分心\"\n\n#: selfdrive/controls/lib/events.py:386\nmsgid \"TOUCH STEERING WHEEL: No Face Detected\"\nmsgstr \"请触碰方向盘：未侦测到驾驶面容\"\n\n#: selfdrive/controls/lib/events.py:394\nmsgid \"TOUCH STEERING WHEEL\"\nmsgstr \"请触碰方向盘\"\n\n#: selfdrive/controls/lib/events.py:395\nmsgid \"Driver Is Unresponsive\"\nmsgstr \"驾驶没有反应\"\n\n#: selfdrive/controls/lib/events.py:403\nmsgid \"Driver Was Unresponsive\"\nmsgstr \"驾驶没有反应\"\n\n#: selfdrive/controls/lib/events.py:410\nmsgid \"CHECK DRIVER FACE VISIBILITY\"\nmsgstr \"请检查驾驶面部的可见度\"\n\n#: selfdrive/controls/lib/events.py:411\nmsgid \"Driver Monitor Model Output Uncertain\"\nmsgstr \"驾驶监控模型判断不明确\"\n\n#: selfdrive/controls/lib/events.py:419\nmsgid \"Resume Driving Manually\"\nmsgstr \"请自行恢復驾驶\"\n\n#: selfdrive/controls/lib/events.py:426\nmsgid \"STOPPED\"\nmsgstr \"已停止\"\n\n#: selfdrive/controls/lib/events.py:427\nmsgid \"Press Resume to Move\"\nmsgstr \"请按 RES 继续\"\n\n#: selfdrive/controls/lib/events.py:438\nmsgid \"Steer Left to Start Lane Change\"\nmsgstr \"请往左打方向盘切换至左车道\"\n\n#: selfdrive/controls/lib/events.py:439 selfdrive/controls/lib/events.py:447\n#: selfdrive/controls/lib/events.py:455 selfdrive/controls/lib/events.py:463\n#: selfdrive/controls/lib/events.py:802 selfdrive/controls/lib/events.py:810\nmsgid \"Monitor Other Vehicles\"\nmsgstr \"请注意其它车辆\"\n\n#: selfdrive/controls/lib/events.py:446\nmsgid \"Steer Right to Start Lane Change\"\nmsgstr \"请往右打方向盘切换至右车道\"\n\n#: selfdrive/controls/lib/events.py:454\nmsgid \"Car Detected in Blindspot\"\nmsgstr \"盲点侦测到车辆\"\n\n#: selfdrive/controls/lib/events.py:462\nmsgid \"Changing Lane\"\nmsgstr \"切换车道中\"\n\n#: selfdrive/controls/lib/events.py:471\nmsgid \"Turn Exceeds Steering Limit\"\nmsgstr \"弯道超过横向操控限制\"\n\n#: selfdrive/controls/lib/events.py:496\nmsgid \"Brake Hold Active\"\nmsgstr \"驻车煞车已启用\"\n\n#: selfdrive/controls/lib/events.py:501\nmsgid \"Park Brake Engaged\"\nmsgstr \"电子驻车已启动\"\n\n#: selfdrive/controls/lib/events.py:506\nmsgid \"Pedal Pressed During Attempt\"\nmsgstr \"启用时侦测到驾驶踩踏油门/刹车\"\n\n#: selfdrive/controls/lib/events.py:517\nmsgid \"Enable Adaptive Cruise\"\nmsgstr \"启用自适应巡航\"\n\n#: selfdrive/controls/lib/events.py:533\nmsgid \"Attempting Refocus: Camera Focus Invalid\"\nmsgstr \"尝试对焦：相机已失焦\"\n\n#: selfdrive/controls/lib/events.py:539\nmsgid \"Out of Storage Space\"\nmsgstr \"存储空间不足\"\n\n#: selfdrive/controls/lib/events.py:544\nmsgid \"Speed Too Low\"\nmsgstr \"车速过慢\"\n\n#: selfdrive/controls/lib/events.py:549 selfdrive/controls/lib/events.py:553\nmsgid \"NEOS Update Required\"\nmsgstr \"NEOS 需要更新\"\n\n#: selfdrive/controls/lib/events.py:550\nmsgid \"Please Wait for Update\"\nmsgstr \"更新中请稍候\"\n\n#: selfdrive/controls/lib/events.py:558 selfdrive/controls/lib/events.py:562\nmsgid \"No Data from Device Sensors\"\nmsgstr \"未收到装置传感器数据\"\n\n#: selfdrive/controls/lib/events.py:559 selfdrive/controls/lib/events.py:572\n#: selfdrive/controls/lib/events.py:669\nmsgid \"Reboot your Device\"\nmsgstr \"请重启装置\"\n\n#: selfdrive/controls/lib/events.py:571 selfdrive/controls/lib/events.py:575\nmsgid \"Speaker not found\"\nmsgstr \"找不到音效装置\"\n\n#: selfdrive/controls/lib/events.py:579\nmsgid \"Distraction Level Too High\"\nmsgstr \"驾驶分心太多次\"\n\n#: selfdrive/controls/lib/events.py:583\nmsgid \"System Overheated\"\nmsgstr \"系统过热\"\n\n#: selfdrive/controls/lib/events.py:584\nmsgid \"System overheated\"\nmsgstr \"系统过热\"\n\n#: selfdrive/controls/lib/events.py:588 selfdrive/controls/lib/events.py:589\nmsgid \"Gear not D\"\nmsgstr \"不在 D 档位\"\n\n#: selfdrive/controls/lib/events.py:594\n#, fuzzy\nmsgid \"Calibration Invalid\"\nmsgstr \"正在校准中\"\n\n#: selfdrive/controls/lib/events.py:595\n#, fuzzy\nmsgid \"Reposition Device and Recalibrate\"\nmsgstr \"校准无效：请将装置放于新的位置并重新校准\"\n\n#: selfdrive/controls/lib/events.py:598 selfdrive/controls/lib/events.py:599\nmsgid \"Calibration Invalid: Reposition Device & Recalibrate\"\nmsgstr \"校准无效：请将装置放于新的位置并重新校准\"\n\n#: selfdrive/controls/lib/events.py:603 selfdrive/controls/lib/events.py:605\nmsgid \"Calibration in Progress\"\nmsgstr \"正在校准中\"\n\n#: selfdrive/controls/lib/events.py:609\nmsgid \"Door Open\"\nmsgstr \"车门开启\"\n\n#: selfdrive/controls/lib/events.py:610\nmsgid \"Door open\"\nmsgstr \"车门未关\"\n\n#: selfdrive/controls/lib/events.py:614\nmsgid \"Seatbelt Unlatched\"\nmsgstr \"安全带未繫\"\n\n#: selfdrive/controls/lib/events.py:615\nmsgid \"Seatbelt unlatched\"\nmsgstr \"安全带未繫\"\n\n#: selfdrive/controls/lib/events.py:619 selfdrive/controls/lib/events.py:620\nmsgid \"ESP Off\"\nmsgstr \"ESP 关闭\"\n\n#: selfdrive/controls/lib/events.py:624 selfdrive/controls/lib/events.py:625\nmsgid \"Low Battery\"\nmsgstr \"电量过低\"\n\n#: selfdrive/controls/lib/events.py:629 selfdrive/controls/lib/events.py:630\nmsgid \"Communication Issue between Processes\"\nmsgstr \"行程间出现通讯问题\"\n\n#: selfdrive/controls/lib/events.py:635 selfdrive/controls/lib/events.py:636\nmsgid \"Radar Communication Issue\"\nmsgstr \"雷达通讯出现问题\"\n\n#: selfdrive/controls/lib/events.py:641 selfdrive/controls/lib/events.py:642\n#: selfdrive/controls/lib/events.py:646 selfdrive/controls/lib/events.py:647\nmsgid \"Radar Error: Restart the Car\"\nmsgstr \"雷达讯号错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:651 selfdrive/controls/lib/events.py:652\nmsgid \"Driving model lagging\"\nmsgstr \"操控模型有延迟\"\n\n#: selfdrive/controls/lib/events.py:656 selfdrive/controls/lib/events.py:657\nmsgid \"Vision Model Output Uncertain\"\nmsgstr \"视觉模型判断不明确\"\n\n#: selfdrive/controls/lib/events.py:661 selfdrive/controls/lib/events.py:662\nmsgid \"Device Fell Off Mount\"\nmsgstr \"装置掉落侦测\"\n\n#: selfdrive/controls/lib/events.py:666 selfdrive/controls/lib/events.py:672\nmsgid \"Low Memory: Reboot Your Device\"\nmsgstr \"记忆体不足：请重启您的装置\"\n\n#: selfdrive/controls/lib/events.py:668\nmsgid \"RAM Critically Low\"\nmsgstr \"记忆体严重不足\"\n\n#: selfdrive/controls/lib/events.py:677 selfdrive/controls/lib/events.py:678\nmsgid \"Controls Failed\"\nmsgstr \"控制发生错误\"\n\n#: selfdrive/controls/lib/events.py:682\nmsgid \"Controls Mismatch\"\nmsgstr \"控制不匹配\"\n\n#: selfdrive/controls/lib/events.py:686 selfdrive/controls/lib/events.py:688\n#: selfdrive/controls/lib/events.py:692\nmsgid \"CAN Error: Check Connections\"\nmsgstr \"CAN 讯号错误：请检查线路\"\n\n#: selfdrive/controls/lib/events.py:696 selfdrive/controls/lib/events.py:702\nmsgid \"LKAS Fault: Restart the Car\"\nmsgstr \"LKAS 错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:698\nmsgid \"LKAS Fault: Restart the car to engage\"\nmsgstr \"LKAS 错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:706 selfdrive/controls/lib/events.py:712\n#: selfdrive/controls/lib/events.py:795\nmsgid \"Cruise Fault: Restart the Car\"\nmsgstr \"巡航系统错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:708 selfdrive/controls/lib/events.py:791\nmsgid \"Cruise Fault: Restart the car to engage\"\nmsgstr \"巡航系统错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:716\nmsgid \"Gas Fault: Restart the Car\"\nmsgstr \"油门错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:717\nmsgid \"Gas Error: Restart the Car\"\nmsgstr \"油门错误：请重新发动车辆\"\n\n#: selfdrive/controls/lib/events.py:722\n#, fuzzy\nmsgid \"\"\n\"Reverse\\n\"\n\"Gear\"\nmsgstr \"切换至倒车档\"\n\n#: selfdrive/controls/lib/events.py:726\nmsgid \"Reverse Gear\"\nmsgstr \"切换至倒车档\"\n\n#: selfdrive/controls/lib/events.py:731\nmsgid \"Cruise Is Off\"\nmsgstr \"巡航系统关闭\"\n\n#: selfdrive/controls/lib/events.py:735 selfdrive/controls/lib/events.py:736\nmsgid \"Planner Solution Error\"\nmsgstr \"Planner Solution 错误\"\n\n#: selfdrive/controls/lib/events.py:740 selfdrive/controls/lib/events.py:742\n#: selfdrive/controls/lib/events.py:746\nmsgid \"Harness Malfunction\"\nmsgstr \"Harness 故障\"\n\n#: selfdrive/controls/lib/events.py:743\nmsgid \"Please Check Hardware\"\nmsgstr \"请检查硬体\"\n\n#: selfdrive/controls/lib/events.py:751 selfdrive/controls/lib/events.py:760\nmsgid \"openpilot Canceled\"\nmsgstr \"openpilot 已取消\"\n\n#: selfdrive/controls/lib/events.py:752\nmsgid \"No close lead car\"\nmsgstr \"前方没有车辆\"\n\n#: selfdrive/controls/lib/events.py:755\nmsgid \"No Close Lead Car\"\nmsgstr \"前方没有车辆\"\n\n#: selfdrive/controls/lib/events.py:761\nmsgid \"Speed too low\"\nmsgstr \"车速过慢\"\n\n#: selfdrive/controls/lib/events.py:768 selfdrive/controls/lib/events.py:773\nmsgid \"Speed Too High\"\nmsgstr \"车速过快\"\n\n#: selfdrive/controls/lib/events.py:769\nmsgid \"Slow down to resume operation\"\nmsgstr \"请减速后再启用\"\n\n#: selfdrive/controls/lib/events.py:774\nmsgid \"Slow down to engage\"\nmsgstr \"请减速后再启用\"\n\n#: selfdrive/controls/lib/events.py:781\nmsgid \"Please connect to Internet\"\nmsgstr \"请连接网路\"\n\n#: selfdrive/controls/lib/events.py:782\nmsgid \"An Update Check Is Required to Engage\"\nmsgstr \"需检查更新后才能启用\"\n\n#: selfdrive/controls/lib/events.py:785\nmsgid \"Please Connect to Internet\"\nmsgstr \"请连接网路\"\n\n#: selfdrive/controls/lib/events.py:801\nmsgid \"Left ALC will start in 3s\"\nmsgstr \"准备自动切至左车道\"\n\n#: selfdrive/controls/lib/events.py:809\nmsgid \"Right ALC will start in 3s\"\nmsgstr \"准备自动切至右车道\"\n\n#: selfdrive/controls/lib/events.py:817\nmsgid \"STEERING REQUIRED: Lane Keeping OFF\"\nmsgstr \"请接管方向盘：车道维持关闭\"\n\n#: selfdrive/controls/lib/events.py:825\nmsgid \"STEERING REQUIRED: Blinkers ON\"\nmsgstr \"请接管方向盘：方向灯开启\"\n\n#: selfdrive/controls/lib/events.py:833 selfdrive/controls/lib/events.py:838\nmsgid \"Lead Car Is Moving\"\nmsgstr \"前方车辆车移动中\"\n\n#: selfdrive/controls/lib/events.py:847\nmsgid \"WARNING\"\nmsgstr \"警告\"\n\n#: selfdrive/controls/lib/events.py:848\nmsgid \"Grab wheel to start bypass\"\nmsgstr \"请握好方向盘以绕过时间限制\"\n\n#: selfdrive/controls/lib/events.py:855\nmsgid \"BYPASSING\"\nmsgstr \"绕过时间限制中\"\n\n#: selfdrive/controls/lib/events.py:856\nmsgid \"HOLD WHEEL\"\nmsgstr \"握好方向盘\"\n\n#: selfdrive/controls/lib/events.py:863\nmsgid \"Bypassed!\"\nmsgstr \"时间限制已绕过\"\n\n#: selfdrive/controls/lib/events.py:864\nmsgid \"Release wheel when ready\"\nmsgstr \"准备好后请松开放向盘\"\n"
  },
  {
    "path": "selfdrive/assets/locales/zh-TW/LC_MESSAGES/events.po",
    "content": "# SOME DESCRIPTIVE TITLE.\n# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER\n# This file is distributed under the same license as the PACKAGE package.\n# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.\n#\nmsgid \"\"\nmsgstr \"\"\n\"Project-Id-Version: PACKAGE VERSION\\n\"\n\"Report-Msgid-Bugs-To: \\n\"\n\"POT-Creation-Date: 2020-10-15 13:37+1000\\n\"\n\"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\\n\"\n\"Last-Translator: Rick Lan <ricklan@gmail.com>\\n\"\n\"Language-Team: LANGUAGE <LL@li.org>\\n\"\n\"Language: zh-TW\\n\"\n\"MIME-Version: 1.0\\n\"\n\"Content-Type: text/plain; charset=UTF-8\\n\"\n\"Content-Transfer-Encoding: 8bit\\n\"\n\n#: selfdrive/controls/lib/events.py:153\nmsgid \"openpilot Unavailable\"\nmsgstr \"無法使用 openpilot\"\n\n#: selfdrive/controls/lib/events.py:160 selfdrive/controls/lib/events.py:167\nmsgid \"TAKE CONTROL IMMEDIATELY\"\nmsgstr \"即刻接管控制\"\n\n#: selfdrive/controls/lib/events.py:187 selfdrive/controls/lib/events.py:328\n#: selfdrive/controls/lib/events.py:354 selfdrive/controls/lib/events.py:418\n#: selfdrive/controls/lib/events.py:470 selfdrive/controls/lib/events.py:522\n#: selfdrive/controls/lib/events.py:532\nmsgid \"TAKE CONTROL\"\nmsgstr \"接管控制\"\n\n#: selfdrive/controls/lib/events.py:188\n#, fuzzy, python-format\nmsgid \"Steer Unavailable Below %(speed)d %(unit)s\"\nmsgstr \"橫向控制暫時失效，車速低於 %d %s\"\n\n#: selfdrive/controls/lib/events.py:196\n#, fuzzy, python-format\nmsgid \"Calibration in Progress: %d%%\"\nmsgstr \"正在校準中：%d%%\"\n\n#: selfdrive/controls/lib/events.py:197\n#, fuzzy, python-format\nmsgid \"Drive Above %(speed)d %(unit)s\"\nmsgstr \"車速請高於 %(speed)d %(unit)s\"\n\n#: selfdrive/controls/lib/events.py:204\nmsgid \"Poor GPS reception\"\nmsgstr \"GPS 訊號不良\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"If sky is visible, contact support\"\nmsgstr \"如果您不在地下室/隧道，請聯系客服\"\n\n#: selfdrive/controls/lib/events.py:205\nmsgid \"Check GPS antenna placement\"\nmsgstr \"請檢查 GPS 天線位置\"\n\n#: selfdrive/controls/lib/events.py:210\nmsgid \"Cruise Mode Disabled\"\nmsgstr \"巡航模式關閉\"\n\n#: selfdrive/controls/lib/events.py:212\nmsgid \"Main Switch Off\"\nmsgstr \"主開關已關閉\"\n\n#: selfdrive/controls/lib/events.py:222\nmsgid \"DEBUG ALERT\"\nmsgstr \"除錯用警示訊息\"\n\n#: selfdrive/controls/lib/events.py:230\nmsgid \"Be ready to take over at any time\"\nmsgstr \"請準備好隨時接管\"\n\n#: selfdrive/controls/lib/events.py:231 selfdrive/controls/lib/events.py:239\n#: selfdrive/controls/lib/events.py:247 selfdrive/controls/lib/events.py:255\nmsgid \"Always keep hands on wheel and eyes on road\"\nmsgstr \"將手放在方向盤上並持續監視路況\"\n\n#: selfdrive/controls/lib/events.py:238\nmsgid \"WARNING: This branch is not tested\"\nmsgstr \"注意：這個分支未經過測試\"\n\n#: selfdrive/controls/lib/events.py:246\nmsgid \"Dashcam mode\"\nmsgstr \"行車記錄模式\"\n\n#: selfdrive/controls/lib/events.py:254\nmsgid \"Dashcam mode for unsupported car\"\nmsgstr \"行車記錄模式 (尚未支援車種)\"\n\n#: selfdrive/controls/lib/events.py:262\nmsgid \"Unsupported Giraffe Configuration\"\nmsgstr \"未支援的 Giraffe 設置\"\n\n#: selfdrive/controls/lib/events.py:263\nmsgid \"Visit comma.ai/tg\"\nmsgstr \"請查閱 comma.ai/tg\"\n\n#: selfdrive/controls/lib/events.py:270\nmsgid \"White Panda Is No Longer Supported\"\nmsgstr \"不再支援 White Panda\"\n\n#: selfdrive/controls/lib/events.py:271\nmsgid \"Upgrade to comma two or black panda\"\nmsgstr \"請升級至 comma two 或是使用 black panda\"\n\n#: selfdrive/controls/lib/events.py:274\nmsgid \"White panda is no longer supported\"\nmsgstr \"不再支援 White panda\"\n\n#: selfdrive/controls/lib/events.py:279\nmsgid \"Stock LKAS is turned on\"\nmsgstr \"原廠 LKAS 已開啟\"\n\n#: selfdrive/controls/lib/events.py:280\nmsgid \"Turn off stock LKAS to engage\"\nmsgstr \"需關閉原廠 LKAS 才能啟用\"\n\n#: selfdrive/controls/lib/events.py:288\nmsgid \"Community Feature Detected\"\nmsgstr \"檢測到社群開發功能\"\n\n#: selfdrive/controls/lib/events.py:289\nmsgid \"Enable Community Features in Developer Settings\"\nmsgstr \"請至開發人員設定裡啟用社群開發功能\"\n\n#: selfdrive/controls/lib/events.py:296\nmsgid \"Dashcam Mode\"\nmsgstr \"行車記錄模式\"\n\n#: selfdrive/controls/lib/events.py:297\nmsgid \"Car Unrecognized\"\nmsgstr \"無法辨識車款\"\n\n#: selfdrive/controls/lib/events.py:304 selfdrive/controls/lib/events.py:312\n#: selfdrive/controls/lib/events.py:320\nmsgid \"BRAKE!\"\nmsgstr \"剎車！\"\n\n#: selfdrive/controls/lib/events.py:305\nmsgid \"Stock AEB: Risk of Collision\"\nmsgstr \"有碰撞的風險\"\n\n#: selfdrive/controls/lib/events.py:313\nmsgid \"Stock FCW: Risk of Collision\"\nmsgstr \"有碰撞的風險\"\n\n#: selfdrive/controls/lib/events.py:321\nmsgid \"Risk of Collision\"\nmsgstr \"有碰撞的風險\"\n\n#: selfdrive/controls/lib/events.py:329\nmsgid \"Lane Departure Detected\"\nmsgstr \"偏離車道\"\n\n#: selfdrive/controls/lib/events.py:338\nmsgid \"openpilot will not brake while gas pressed\"\nmsgstr \"在您踩著油門的時候 openpilot 將不會剎車\"\n\n#: selfdrive/controls/lib/events.py:346\nmsgid \"Vehicle Parameter Identification Failed\"\nmsgstr \"車子參數識別失敗\"\n\n#: selfdrive/controls/lib/events.py:355 selfdrive/controls/lib/events.py:523\n#: selfdrive/controls/lib/events.py:526\nmsgid \"Steering Temporarily Unavailable\"\nmsgstr \"橫向控制暫時失效\"\n\n#: selfdrive/controls/lib/events.py:362\nmsgid \"KEEP EYES ON ROAD: Driver Distracted\"\nmsgstr \"注意路況：駕駛分心\"\n\n#: selfdrive/controls/lib/events.py:370\nmsgid \"KEEP EYES ON ROAD\"\nmsgstr \"注意路況\"\n\n#: selfdrive/controls/lib/events.py:371\nmsgid \"Driver Appears Distracted\"\nmsgstr \"駕駛分心\"\n\n#: selfdrive/controls/lib/events.py:378 selfdrive/controls/lib/events.py:402\nmsgid \"DISENGAGE IMMEDIATELY\"\nmsgstr \"立即解除\"\n\n#: selfdrive/controls/lib/events.py:379\nmsgid \"Driver Was Distracted\"\nmsgstr \"駕駛分心\"\n\n#: selfdrive/controls/lib/events.py:386\nmsgid \"TOUCH STEERING WHEEL: No Face Detected\"\nmsgstr \"請觸碰方向盤：未偵測到駕駛面容\"\n\n#: selfdrive/controls/lib/events.py:394\nmsgid \"TOUCH STEERING WHEEL\"\nmsgstr \"請觸碰方向盤\"\n\n#: selfdrive/controls/lib/events.py:395\nmsgid \"Driver Is Unresponsive\"\nmsgstr \"駕駛沒有反應\"\n\n#: selfdrive/controls/lib/events.py:403\nmsgid \"Driver Was Unresponsive\"\nmsgstr \"駕駛沒有反應\"\n\n#: selfdrive/controls/lib/events.py:410\nmsgid \"CHECK DRIVER FACE VISIBILITY\"\nmsgstr \"請檢查駕駛面部的可見度\"\n\n#: selfdrive/controls/lib/events.py:411\nmsgid \"Driver Monitor Model Output Uncertain\"\nmsgstr \"駕駛監控模型判斷不明確\"\n\n#: selfdrive/controls/lib/events.py:419\nmsgid \"Resume Driving Manually\"\nmsgstr \"請自行恢復駕駛\"\n\n#: selfdrive/controls/lib/events.py:426\nmsgid \"STOPPED\"\nmsgstr \"已停止\"\n\n#: selfdrive/controls/lib/events.py:427\nmsgid \"Press Resume to Move\"\nmsgstr \"請按 RES 繼續\"\n\n#: selfdrive/controls/lib/events.py:438\nmsgid \"Steer Left to Start Lane Change\"\nmsgstr \"請往左打方向盤切換至左車道\"\n\n#: selfdrive/controls/lib/events.py:439 selfdrive/controls/lib/events.py:447\n#: selfdrive/controls/lib/events.py:455 selfdrive/controls/lib/events.py:463\n#: selfdrive/controls/lib/events.py:802 selfdrive/controls/lib/events.py:810\nmsgid \"Monitor Other Vehicles\"\nmsgstr \"請注意其它車輛\"\n\n#: selfdrive/controls/lib/events.py:446\nmsgid \"Steer Right to Start Lane Change\"\nmsgstr \"請往右打方向盤切換至右車道\"\n\n#: selfdrive/controls/lib/events.py:454\nmsgid \"Car Detected in Blindspot\"\nmsgstr \"盲點偵測到車輛\"\n\n#: selfdrive/controls/lib/events.py:462\nmsgid \"Changing Lane\"\nmsgstr \"切換車道中\"\n\n#: selfdrive/controls/lib/events.py:471\nmsgid \"Turn Exceeds Steering Limit\"\nmsgstr \"彎道超過橫向操控限制\"\n\n#: selfdrive/controls/lib/events.py:496\nmsgid \"Brake Hold Active\"\nmsgstr \"駐車煞車已啟用\"\n\n#: selfdrive/controls/lib/events.py:501\nmsgid \"Park Brake Engaged\"\nmsgstr \"電子駐車已啟動\"\n\n#: selfdrive/controls/lib/events.py:506\nmsgid \"Pedal Pressed During Attempt\"\nmsgstr \"啟用時偵測到駕駛踩踏油門/剎車\"\n\n#: selfdrive/controls/lib/events.py:517\nmsgid \"Enable Adaptive Cruise\"\nmsgstr \"啟用主動定速巡航\"\n\n#: selfdrive/controls/lib/events.py:533\nmsgid \"Attempting Refocus: Camera Focus Invalid\"\nmsgstr \"嘗試對焦：相機已失焦\"\n\n#: selfdrive/controls/lib/events.py:539\nmsgid \"Out of Storage Space\"\nmsgstr \"儲存空間不足\"\n\n#: selfdrive/controls/lib/events.py:544\nmsgid \"Speed Too Low\"\nmsgstr \"車速過慢\"\n\n#: selfdrive/controls/lib/events.py:549 selfdrive/controls/lib/events.py:553\nmsgid \"NEOS Update Required\"\nmsgstr \"NEOS 需要更新\"\n\n#: selfdrive/controls/lib/events.py:550\nmsgid \"Please Wait for Update\"\nmsgstr \"更新中請稍候\"\n\n#: selfdrive/controls/lib/events.py:558 selfdrive/controls/lib/events.py:562\nmsgid \"No Data from Device Sensors\"\nmsgstr \"未收到裝置傳感器數據\"\n\n#: selfdrive/controls/lib/events.py:559 selfdrive/controls/lib/events.py:572\n#: selfdrive/controls/lib/events.py:669\nmsgid \"Reboot your Device\"\nmsgstr \"請重啟裝置\"\n\n#: selfdrive/controls/lib/events.py:571 selfdrive/controls/lib/events.py:575\nmsgid \"Speaker not found\"\nmsgstr \"找不到音效裝置\"\n\n#: selfdrive/controls/lib/events.py:579\nmsgid \"Distraction Level Too High\"\nmsgstr \"駕駛分心太多次\"\n\n#: selfdrive/controls/lib/events.py:583\nmsgid \"System Overheated\"\nmsgstr \"系統過熱\"\n\n#: selfdrive/controls/lib/events.py:584\nmsgid \"System overheated\"\nmsgstr \"系統過熱\"\n\n#: selfdrive/controls/lib/events.py:588 selfdrive/controls/lib/events.py:589\nmsgid \"Gear not D\"\nmsgstr \"不在 D 檔位\"\n\n#: selfdrive/controls/lib/events.py:594\n#, fuzzy\nmsgid \"Calibration Invalid\"\nmsgstr \"正在校準中\"\n\n#: selfdrive/controls/lib/events.py:595\n#, fuzzy\nmsgid \"Reposition Device and Recalibrate\"\nmsgstr \"校準無效：請將裝置放於新的位置並重新校準\"\n\n#: selfdrive/controls/lib/events.py:598 selfdrive/controls/lib/events.py:599\nmsgid \"Calibration Invalid: Reposition Device & Recalibrate\"\nmsgstr \"校準無效：請將裝置放於新的位置並重新校準\"\n\n#: selfdrive/controls/lib/events.py:603 selfdrive/controls/lib/events.py:605\nmsgid \"Calibration in Progress\"\nmsgstr \"正在校準中\"\n\n#: selfdrive/controls/lib/events.py:609\nmsgid \"Door Open\"\nmsgstr \"車門開啟\"\n\n#: selfdrive/controls/lib/events.py:610\nmsgid \"Door open\"\nmsgstr \"車門未關\"\n\n#: selfdrive/controls/lib/events.py:614\nmsgid \"Seatbelt Unlatched\"\nmsgstr \"安全帶未繫\"\n\n#: selfdrive/controls/lib/events.py:615\nmsgid \"Seatbelt unlatched\"\nmsgstr \"安全帶未繫\"\n\n#: selfdrive/controls/lib/events.py:619 selfdrive/controls/lib/events.py:620\nmsgid \"ESP Off\"\nmsgstr \"ESP 關閉\"\n\n#: selfdrive/controls/lib/events.py:624 selfdrive/controls/lib/events.py:625\nmsgid \"Low Battery\"\nmsgstr \"電量過低\"\n\n#: selfdrive/controls/lib/events.py:629 selfdrive/controls/lib/events.py:630\nmsgid \"Communication Issue between Processes\"\nmsgstr \"行程間出現通訊問題\"\n\n#: selfdrive/controls/lib/events.py:635 selfdrive/controls/lib/events.py:636\nmsgid \"Radar Communication Issue\"\nmsgstr \"雷達通訊出現問題\"\n\n#: selfdrive/controls/lib/events.py:641 selfdrive/controls/lib/events.py:642\n#: selfdrive/controls/lib/events.py:646 selfdrive/controls/lib/events.py:647\nmsgid \"Radar Error: Restart the Car\"\nmsgstr \"雷達訊號錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:651 selfdrive/controls/lib/events.py:652\nmsgid \"Driving model lagging\"\nmsgstr \"操控模型有延遲\"\n\n#: selfdrive/controls/lib/events.py:656 selfdrive/controls/lib/events.py:657\nmsgid \"Vision Model Output Uncertain\"\nmsgstr \"視覺模型判斷不明確\"\n\n#: selfdrive/controls/lib/events.py:661 selfdrive/controls/lib/events.py:662\nmsgid \"Device Fell Off Mount\"\nmsgstr \"裝置掉落偵測\"\n\n#: selfdrive/controls/lib/events.py:666 selfdrive/controls/lib/events.py:672\nmsgid \"Low Memory: Reboot Your Device\"\nmsgstr \"記憶體不足：請重啟您的裝置\"\n\n#: selfdrive/controls/lib/events.py:668\nmsgid \"RAM Critically Low\"\nmsgstr \"記憶體嚴重不足\"\n\n#: selfdrive/controls/lib/events.py:677 selfdrive/controls/lib/events.py:678\nmsgid \"Controls Failed\"\nmsgstr \"控制發生錯誤\"\n\n#: selfdrive/controls/lib/events.py:682\nmsgid \"Controls Mismatch\"\nmsgstr \"控制不匹配\"\n\n#: selfdrive/controls/lib/events.py:686 selfdrive/controls/lib/events.py:688\n#: selfdrive/controls/lib/events.py:692\nmsgid \"CAN Error: Check Connections\"\nmsgstr \"CAN 訊號錯誤：請檢查線路\"\n\n#: selfdrive/controls/lib/events.py:696 selfdrive/controls/lib/events.py:702\nmsgid \"LKAS Fault: Restart the Car\"\nmsgstr \"LKAS 錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:698\nmsgid \"LKAS Fault: Restart the car to engage\"\nmsgstr \"LKAS 錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:706 selfdrive/controls/lib/events.py:712\n#: selfdrive/controls/lib/events.py:795\nmsgid \"Cruise Fault: Restart the Car\"\nmsgstr \"巡航系統錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:708 selfdrive/controls/lib/events.py:791\nmsgid \"Cruise Fault: Restart the car to engage\"\nmsgstr \"巡航系統錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:716\nmsgid \"Gas Fault: Restart the Car\"\nmsgstr \"油門錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:717\nmsgid \"Gas Error: Restart the Car\"\nmsgstr \"油門錯誤：請重新發動車輛\"\n\n#: selfdrive/controls/lib/events.py:722\n#, fuzzy\nmsgid \"\"\n\"Reverse\\n\"\n\"Gear\"\nmsgstr \"切換至倒車檔\"\n\n#: selfdrive/controls/lib/events.py:726\nmsgid \"Reverse Gear\"\nmsgstr \"切換至倒車檔\"\n\n#: selfdrive/controls/lib/events.py:731\nmsgid \"Cruise Is Off\"\nmsgstr \"巡航系統關閉\"\n\n#: selfdrive/controls/lib/events.py:735 selfdrive/controls/lib/events.py:736\nmsgid \"Planner Solution Error\"\nmsgstr \"Planner Solution 錯誤\"\n\n#: selfdrive/controls/lib/events.py:740 selfdrive/controls/lib/events.py:742\n#: selfdrive/controls/lib/events.py:746\nmsgid \"Harness Malfunction\"\nmsgstr \"Harness 故障\"\n\n#: selfdrive/controls/lib/events.py:743\nmsgid \"Please Check Hardware\"\nmsgstr \"請檢查硬體\"\n\n#: selfdrive/controls/lib/events.py:751 selfdrive/controls/lib/events.py:760\nmsgid \"openpilot Canceled\"\nmsgstr \"openpilot 已取消\"\n\n#: selfdrive/controls/lib/events.py:752\nmsgid \"No close lead car\"\nmsgstr \"前方沒有車輛\"\n\n#: selfdrive/controls/lib/events.py:755\nmsgid \"No Close Lead Car\"\nmsgstr \"前方沒有車輛\"\n\n#: selfdrive/controls/lib/events.py:761\nmsgid \"Speed too low\"\nmsgstr \"車速過慢\"\n\n#: selfdrive/controls/lib/events.py:768 selfdrive/controls/lib/events.py:773\nmsgid \"Speed Too High\"\nmsgstr \"車速過快\"\n\n#: selfdrive/controls/lib/events.py:769\nmsgid \"Slow down to resume operation\"\nmsgstr \"請減速後再啟用\"\n\n#: selfdrive/controls/lib/events.py:774\nmsgid \"Slow down to engage\"\nmsgstr \"請減速後再啟用\"\n\n#: selfdrive/controls/lib/events.py:781\nmsgid \"Please connect to Internet\"\nmsgstr \"請連接網路\"\n\n#: selfdrive/controls/lib/events.py:782\nmsgid \"An Update Check Is Required to Engage\"\nmsgstr \"需檢查更新後才能啟用\"\n\n#: selfdrive/controls/lib/events.py:785\nmsgid \"Please Connect to Internet\"\nmsgstr \"請連接網路\"\n\n#: selfdrive/controls/lib/events.py:801\nmsgid \"Left ALC will start in 3s\"\nmsgstr \"準備自動切至左車道\"\n\n#: selfdrive/controls/lib/events.py:809\nmsgid \"Right ALC will start in 3s\"\nmsgstr \"準備自動切至右車道\"\n\n#: selfdrive/controls/lib/events.py:817\nmsgid \"STEERING REQUIRED: Lane Keeping OFF\"\nmsgstr \"請接管方向盤：車道維持關閉\"\n\n#: selfdrive/controls/lib/events.py:825\nmsgid \"STEERING REQUIRED: Blinkers ON\"\nmsgstr \"請接管方向盤：方向燈開啟\"\n\n#: selfdrive/controls/lib/events.py:833 selfdrive/controls/lib/events.py:838\nmsgid \"Lead Car Is Moving\"\nmsgstr \"前方車輛車移動中\"\n\n#: selfdrive/controls/lib/events.py:847\nmsgid \"WARNING\"\nmsgstr \"警告\"\n\n#: selfdrive/controls/lib/events.py:848\nmsgid \"Grab wheel to start bypass\"\nmsgstr \"請握好方向盤以繞過時間限制\"\n\n#: selfdrive/controls/lib/events.py:855\nmsgid \"BYPASSING\"\nmsgstr \"繞過時間限制中\"\n\n#: selfdrive/controls/lib/events.py:856\nmsgid \"HOLD WHEEL\"\nmsgstr \"握好方向盤\"\n\n#: selfdrive/controls/lib/events.py:863\nmsgid \"Bypassed!\"\nmsgstr \"時間限制已繞過\"\n\n#: selfdrive/controls/lib/events.py:864\nmsgid \"Release wheel when ready\"\nmsgstr \"準備好後請鬆開放向盤\"\n"
  },
  {
    "path": "selfdrive/assets/offroad/fcc.html",
    "content": "<!DOCTYPE html>\n<body>\n  <h2>Supplier's Declaration of Conformity: 47 CFR § 2.1077 Compliance Information</h2>\n\n  <h3>Unique Identifier</h3>\n  <p>comma three</p>\n\n  <h3>Authorized Components</h3>\n\n  <h5>Thundersoft TurboX D845 SOM</h5>\n  <p>FCC ID: 2AOHHTURBOXSOMD845</p>\n\n  <h5>Quectel/EG25-G</h5>\n  <p>FCC ID: XMR201903EG25GM</p>\n  <p>\n  This device complies with Part 15 of the FCC Rules.\n  Operation is subject to the following two conditions:\n\n  <p>(1) this device may not cause harmful interference, and\n  <p>(2) this device must accept any interference received, including interference that may cause undesired operation.</p>\n\n  The following test reports are subject to this declaration:\n  Test report number: HR20191001605\n  Issue date: 2019-2-21\n\n  The following manufacturer/importer/entity (located in the USA) is responsible for this declaration:\n  Company name: Quectel Wireless Solutions Co., Ltd.\n  Name/Title (legal representative): Yin JiXiong\n  Address: 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China\n  Phone: +8602150086326 Extension: 800\n  Fax: +862153253668\n  E-mail: johnny.xiang@quectel.com\n  </p>\n\n  <h3>Responsible Party - U.S. Contact Information</h3>\n  <p>comma.ai</p>\n  <p>501 W Broadway St</p>\n  <p>STE A #403</p>\n  <p>San Diego, California</p>\n  <p>92101</p>\n  <p>United States</p>\n  <p>support@comma.ai</p>\n\n  <h3>FCC Compliance Statement</h3>\n  <p> This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.</p>\n  <p>This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.</p>\n  <p>If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:</p>\n  <p>Reorient or relocate the receiving antenna.</p>\n  <p>Increase the separation between the equipment and receiver.</p>\n  <p>Connect the equipment to an outlet on a circuit different from that to which the receiver is connected.</p>\n  <p>Consult the dealer or an experienced radio/TV technician for help.</p>\n  <p>Changes or modifications to this product not expressly approved by the party responsible for compliance could void the electromagnetic compatibility (EMC) and wireless compliance and negate your authority to operate the product.</p>\n  <p>This product has demonstrated EMC compliance under conditions that included the use of compliant peripheral devices and shielded cables between system components. It is important that you use compliant peripheral devices and shielded cables between system components to reduce the possibility of causing interference to radios, televisions, and other electronic devices.</p>\n  <p>The radiated output power of this device meets the limits of FCC/IC radio frequency exposure limits. This device should be operated with a minimum separation distance of 20 cm (8 inches) between the equipment and a person's body.</p>\n</body>\n</html>\n"
  },
  {
    "path": "selfdrive/assets/offroad/tc.html",
    "content": "<!DOCTYPE html>\n\n<head>\n  <meta charset=\"utf-8\" />\n  <title>openpilot Terms of Service</title>\n  <style type=\"text/css\">\n    p {\n      margin: 45px 0;\n    }\n  </style>\n</head>\n\n<body>\n  <p>The Terms and Conditions below are effective for all users</p>\n  <p>Last Updated on October 18, 2019</p>\n  <p>Please read these Terms of Use (“Terms”) carefully before using openpilot which is open-sourced software developed by Comma.ai, Inc., a corporation organized under the laws of Delaware (“comma,” “us,” “we,” or “our”).</p>\n  <p><strong>Before using and by accessing openpilot, you indicate that you have read, understood, and agree to these Terms.</strong> These Terms apply to all users and others who access or use openpilot. If others use openpilot through your user account or vehicle, you are responsible to ensure that they only use openpilot when it is safe to do so, and in compliance with these Terms and with applicable law. If you disagree with any part of the Terms, you should not access or use openpilot.</p>\n  <h3 id=\"communications\">Communications</h3>\n  <p>You agree that comma may contact you by email or telephone in connection with openpilot or for other business purposes. You may opt out of receiving email messages at any time by contacting us at support@comma.ai.</p>\n  <p>We collect, use, and share information from and about you and your vehicle in connection with openpilot. You consent to comma accessing the systems associated with openpilot, without additional notice or consent, for the purposes of providing openpilot, data collection, software updates, safety and cybersecurity, suspension or removal of your account, and as disclosed in the Privacy Policy (available at https://connect.comma.ai/privacy).</p>\n  <h3 id=\"safety\">Safety</h3>\n  <p>openpilot performs the functions of Adaptive Cruise Control (ACC) and Lane Keeping Assist System (LKAS) designed for use in compatible motor vehicles. While using openpilot, it is your responsibility to obey all laws, traffic rules, and traffic regulations governing your vehicle and its operation. Access to and use of openpilot is at your own risk and responsibility, and openpilot should be accessed and/or used only when you can do so safely.</p>\n  <p>openpilot does not make your vehicle “autonomous” or capable of operation without the active monitoring of a licensed driver. It is designed to assist a licensed driver. A licensed driver must pay attention to the road, remain aware of navigation at all times, and be prepared to take immediate action. Failure to do so can cause damage, injury, or death.</p>\n  <h3 id=\"supported-locations-and-models\">Supported Locations and Models</h3>\n  <p>openpilot is compatible only with particular makes and models of vehicles. For a complete list of currently supported vehicles, visit https://comma.ai. openpilot will not function properly when installed in an incompatible vehicle. openpilot is compatible only within the geographical boundaries of the United States of America.</p>\n  <h3 id=\"indemnification\">Indemnification</h3>\n  <p><strong>To the maximum extent allowable by law, you agree to defend, indemnify and hold harmless comma, and its employees, partners, suppliers, contractors, investors, agents, officers, directors, and affiliates, from and against any and all claims, damages, causes of action, penalties, interest, demands, obligations, losses, liabilities, costs or debt, additional taxes, and expenses (including but not limited to attorneys’ fees), resulting from or arising out of (i) your use and access of, or inability to use or access, openpilot, (ii) your breach of these Terms, (iii) the inaccuracy of any information, representation or warranty made by you, (iv) activities of anyone other than you in connection with openpilot conducted through your comma device or account, (v) any other of your activities under or in connection with these Terms or openpilot.</strong></p>\n  <h3 id=\"limitation-of-liability\">Limitation of Liability</h3>\n  <p>In no event shall comma, nor its directors, employees, partners, agents, suppliers, or affiliates, be liable for any indirect, incidental, special, consequential or punitive damages, including without limitation, loss of profits, data, use, goodwill, or other intangible losses, resulting from (i) your access to or use of or inability to access or use of the Software; or (ii) any conduct or content of any third party on the Software whether based on warranty, contract, tort (including negligence) or any other legal theory, whether or not we have been informed of the possibility of such damage, and even if a remedy set forth herein is found to have failed of its essential purpose.</p>\n  <h3 id=\"no-warranty-or-obligations-to-maintain-or-service\">No Warranty or Obligations to Maintain or Service</h3>\n  <p>comma provides openpilot without representations, conditions, or warranties of any kind. openpilot is provided on an “AS IS” and “AS AVAILABLE” basis, including with all faults and errors as may occur. To the extent permitted by law and unless prohibited by law, comma on behalf of itself and all persons and parties acting by, through, or for comma, explicitly disclaims all warranties or conditions, express, implied, or collateral, including any implied warranties of merchantability, satisfactory quality, and fitness for a particular purpose in respect of openpilot.</p>\n  <p>To the extent permitted by law, comma does not warrant the operation, performance, or availability of openpilot under all conditions. comma is not responsible for any failures caused by server errors, misdirected or redirected transmissions, failed internet connections, interruptions or failures in the transmission of data, any computer virus, or any acts or omissions of third parties that damage the network or impair wireless service.</p>\n  <p>We undertake reasonable measures to preserve and secure information collected through our openpilot. However, no data collection, transmission or storage system is 100% secure, and there is always a risk that your information may be intercepted without our consent. <em>In using openpilot, you acknowledge that comma is not responsible for intercepted information, and you hereby release us from any and all claims arising out of or related to the use of intercepted information in any unauthorized manner.</em></p>\n  <p>By providing openpilot, comma does not transfer or license its intellectual property or grant rights in its brand names, nor does comma make representations with respect to third-party intellectual property rights.</p>\n  <p>We are not obligated to provide any maintenance or support for openpilot, technical or otherwise. If we voluntarily provide any maintenance or support for openpilot, we may stop any such maintenance, support, or services at any time in our sole discretion.</p>\n  <h3 id=\"modification-of-software\">Modification of Software</h3>\n  <p>In no event shall comma, nor its directors, employees, partners, agents, suppliers, or affiliates, be liable if you choose to modify the software.</p>\n  <h3 id=\"changes\">Changes</h3>\n  <p>We reserve the right, at our sole discretion, to modify or replace these Terms at any time. If a revision is material we will provide at least 15 days’ notice prior to any new terms taking effect. What constitutes a material change will be determined at our sole discretion.</p>\n  <p>By continuing to access or use our Software after any revisions become effective, you agree to be bound by the revised terms. If you do not agree to the new terms, you are no longer authorized to use the Software.</p>\n  <h3 id=\"contact-us\">Contact Us</h3>\n  <p>If you have any questions about these Terms, please contact us at support@comma.ai.</p>\n</body>\n</html>\n"
  },
  {
    "path": "selfdrive/athena/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/athena/athenad.py",
    "content": "#!/usr/bin/env python3\nimport base64\nimport hashlib\nimport io\nimport json\nimport os\nimport sys\nimport queue\nimport random\nimport select\nimport socket\nimport threading\nimport time\nfrom collections import namedtuple\nfrom functools import partial\nfrom typing import Any\n\nimport requests\nfrom jsonrpc import JSONRPCResponseManager, dispatcher\nfrom websocket import ABNF, WebSocketTimeoutException, WebSocketException, create_connection\nfrom common.params import Params\nAPI_HOST = os.getenv('API_HOST', 'https://api.commadotai.com') if not Params().get_bool(\"dp_api_custom\") else Params().get(\"dp_api_custom_url\", encoding='utf-8')\n\nimport cereal.messaging as messaging\nfrom cereal.services import service_list\nfrom common.api import Api\nfrom common.file_helpers import CallbackReader\nfrom common.basedir import PERSIST\nfrom common.params import Params\nfrom common.realtime import sec_since_boot\nfrom selfdrive.hardware import HARDWARE, PC, TICI\nfrom selfdrive.loggerd.config import ROOT\nfrom selfdrive.loggerd.xattr_cache import getxattr, setxattr\nfrom selfdrive.swaglog import cloudlog, SWAGLOG_DIR\nfrom selfdrive.version import version, get_version, get_git_remote, get_git_branch, get_git_commit\n\nATHENA_HOST = os.getenv('ATHENA_HOST', 'wss://athena.comma.ai')\nHANDLER_THREADS = int(os.getenv('HANDLER_THREADS', \"4\"))\nLOCAL_PORT_WHITELIST = set([8022])\n\nLOG_ATTR_NAME = 'user.upload'\nLOG_ATTR_VALUE_MAX_UNIX_TIME = int.to_bytes(2147483647, 4, sys.byteorder)\nRECONNECT_TIMEOUT_S = 70\n\nRETRY_DELAY = 10  # seconds\nMAX_RETRY_COUNT = 30  # Try for at most 5 minutes if upload fails immediately\nWS_FRAME_SIZE = 4096\n\ndispatcher[\"echo\"] = lambda s: s\nrecv_queue: Any = queue.Queue()\nsend_queue: Any = queue.Queue()\nupload_queue: Any = queue.Queue()\nlog_send_queue: Any = queue.Queue()\nlog_recv_queue: Any = queue.Queue()\ncancelled_uploads: Any = set()\nUploadItem = namedtuple('UploadItem', ['path', 'url', 'headers', 'created_at', 'id', 'retry_count', 'current', 'progress'], defaults=(0, False, 0))\n\ncur_upload_items = {}\n\n\ndef handle_long_poll(ws):\n  end_event = threading.Event()\n\n  threads = [\n              threading.Thread(target=ws_recv, args=(ws, end_event), name='ws_recv'),\n              threading.Thread(target=ws_send, args=(ws, end_event), name='ws_send'),\n              threading.Thread(target=upload_handler, args=(end_event,), name='upload_handler'),\n              threading.Thread(target=log_handler, args=(end_event,), name='log_handler'),\n            ] + [\n              threading.Thread(target=jsonrpc_handler, args=(end_event,), name=f'worker_{x}')\n              for x in range(HANDLER_THREADS)\n            ]\n\n  for thread in threads:\n    thread.start()\n  try:\n    while not end_event.is_set():\n      time.sleep(0.1)\n  except (KeyboardInterrupt, SystemExit):\n    end_event.set()\n    raise\n  finally:\n    for thread in threads:\n      cloudlog.debug(f\"athena.joining {thread.name}\")\n      thread.join()\n\n\ndef jsonrpc_handler(end_event):\n  dispatcher[\"startLocalProxy\"] = partial(startLocalProxy, end_event)\n  while not end_event.is_set():\n    try:\n      data = recv_queue.get(timeout=1)\n      if \"method\" in data:\n        cloudlog.debug(f\"athena.jsonrpc_handler.call_method {data}\")\n        response = JSONRPCResponseManager.handle(data, dispatcher)\n        send_queue.put_nowait(response.json)\n      elif \"id\" in data and (\"result\" in data or \"error\" in data):\n        log_recv_queue.put_nowait(data)\n      else:\n        raise Exception(\"not a valid request or response\")\n    except queue.Empty:\n      pass\n    except Exception as e:\n      cloudlog.exception(\"athena jsonrpc handler failed\")\n      send_queue.put_nowait(json.dumps({\"error\": str(e)}))\n\n\ndef upload_handler(end_event):\n  tid = threading.get_ident()\n\n  while not end_event.is_set():\n    cur_upload_items[tid] = None\n\n    try:\n      cur_upload_items[tid] = upload_queue.get(timeout=1)._replace(current=True)\n      if cur_upload_items[tid].id in cancelled_uploads:\n        cancelled_uploads.remove(cur_upload_items[tid].id)\n        continue\n\n      try:\n        def cb(sz, cur):\n          cur_upload_items[tid] = cur_upload_items[tid]._replace(progress=cur / sz if sz else 1)\n\n        _do_upload(cur_upload_items[tid], cb)\n      except (requests.exceptions.Timeout, requests.exceptions.ConnectionError, requests.exceptions.SSLError) as e:\n        cloudlog.warning(f\"athena.upload_handler.retry {e} {cur_upload_items[tid]}\")\n\n        if cur_upload_items[tid].retry_count < MAX_RETRY_COUNT:\n          item = cur_upload_items[tid]\n          item = item._replace(\n            retry_count=item.retry_count + 1,\n            progress=0,\n            current=False\n          )\n          upload_queue.put_nowait(item)\n          cur_upload_items[tid] = None\n\n          for _ in range(RETRY_DELAY):\n            time.sleep(1)\n            if end_event.is_set():\n              break\n\n    except queue.Empty:\n      pass\n    except Exception:\n      cloudlog.exception(\"athena.upload_handler.exception\")\n\n\ndef _do_upload(upload_item, callback=None):\n  with open(upload_item.path, \"rb\") as f:\n    size = os.fstat(f.fileno()).st_size\n\n    if callback:\n      f = CallbackReader(f, callback, size)\n\n    return requests.put(upload_item.url,\n                        data=f,\n                        headers={**upload_item.headers, 'Content-Length': str(size)},\n                        timeout=30)\n\n\n# security: user should be able to request any message from their car\n@dispatcher.add_method\ndef getMessage(service=None, timeout=1000):\n  if service is None or service not in service_list:\n    raise Exception(\"invalid service\")\n\n  socket = messaging.sub_sock(service, timeout=timeout)\n  ret = messaging.recv_one(socket)\n\n  if ret is None:\n    raise TimeoutError\n\n  return ret.to_dict()\n\n\n@dispatcher.add_method\ndef getVersion():\n  return {\n    \"version\": get_version(),\n    \"remote\": get_git_remote(),\n    \"branch\": get_git_branch(),\n    \"commit\": get_git_commit(),\n  }\n\n\n@dispatcher.add_method\ndef setNavDestination(latitude=0, longitude=0):\n  destination = {\n    \"latitude\": latitude,\n    \"longitude\": longitude,\n  }\n  Params().put(\"NavDestination\", json.dumps(destination))\n\n  return {\"success\": 1}\n\n\ndef scan_dir(path, prefix):\n  files = list()\n  # only walk directories that match the prefix\n  # (glob and friends traverse entire dir tree)\n  with os.scandir(path) as i:\n    for e in i:\n      rel_path = os.path.relpath(e.path, ROOT)\n      if e.is_dir(follow_symlinks=False):\n        # add trailing slash\n        rel_path = os.path.join(rel_path, '')\n        # if prefix is a partial dir name, current dir will start with prefix\n        # if prefix is a partial file name, prefix with start with dir name\n        if rel_path.startswith(prefix) or prefix.startswith(rel_path):\n          files.extend(scan_dir(e.path, prefix))\n      else:\n        if rel_path.startswith(prefix):\n          files.append(rel_path)\n  return files\n\n@dispatcher.add_method\ndef listDataDirectory(prefix=''):\n  return scan_dir(ROOT, prefix)\n\n\n@dispatcher.add_method\ndef reboot():\n  sock = messaging.sub_sock(\"deviceState\", timeout=1000)\n  ret = messaging.recv_one(sock)\n  if ret is None or ret.deviceState.started:\n    raise Exception(\"Reboot unavailable\")\n\n  def do_reboot():\n    time.sleep(2)\n    HARDWARE.reboot()\n\n  threading.Thread(target=do_reboot).start()\n\n  return {\"success\": 1}\n\n\n@dispatcher.add_method\ndef uploadFileToUrl(fn, url, headers):\n  if len(fn) == 0 or fn[0] == '/' or '..' in fn:\n    return 500\n  path = os.path.join(ROOT, fn)\n  if not os.path.exists(path):\n    return 404\n\n  item = UploadItem(path=path, url=url, headers=headers, created_at=int(time.time() * 1000), id=None)\n  upload_id = hashlib.sha1(str(item).encode()).hexdigest()\n  item = item._replace(id=upload_id)\n\n  upload_queue.put_nowait(item)\n\n  return {\"enqueued\": 1, \"item\": item._asdict()}\n\n\n@dispatcher.add_method\ndef listUploadQueue():\n  items = list(upload_queue.queue) + list(cur_upload_items.values())\n  return [i._asdict() for i in items if i is not None]\n\n\n@dispatcher.add_method\ndef cancelUpload(upload_id):\n  upload_ids = set(item.id for item in list(upload_queue.queue))\n  if upload_id not in upload_ids:\n    return 404\n\n  cancelled_uploads.add(upload_id)\n  return {\"success\": 1}\n\n\n@dispatcher.add_method\ndef primeActivated(activated):\n  dongle_id = Params().get(\"DongleId\", encoding='utf-8')\n  api = Api(dongle_id)\n  manage_tokens(api)\n  return {\"success\": 1}\n\n\ndef startLocalProxy(global_end_event, remote_ws_uri, local_port):\n  try:\n    if local_port not in LOCAL_PORT_WHITELIST:\n      raise Exception(\"Requested local port not whitelisted\")\n\n    cloudlog.debug(\"athena.startLocalProxy.starting\")\n\n    params = Params()\n    dongle_id = params.get(\"DongleId\").decode('utf8')\n    identity_token = Api(dongle_id).get_token()\n    ws = create_connection(remote_ws_uri,\n                           cookie=\"jwt=\" + identity_token,\n                           enable_multithread=True)\n\n    ssock, csock = socket.socketpair()\n    local_sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)\n    local_sock.connect(('127.0.0.1', local_port))\n    local_sock.setblocking(0)\n\n    proxy_end_event = threading.Event()\n    threads = [\n      threading.Thread(target=ws_proxy_recv, args=(ws, local_sock, ssock, proxy_end_event, global_end_event)),\n      threading.Thread(target=ws_proxy_send, args=(ws, local_sock, csock, proxy_end_event))\n    ]\n    for thread in threads:\n      thread.start()\n\n    cloudlog.debug(\"athena.startLocalProxy.started\")\n    return {\"success\": 1}\n  except Exception as e:\n    cloudlog.exception(\"athenad.startLocalProxy.exception\")\n    raise e\n\n\n@dispatcher.add_method\ndef getPublicKey():\n  if not os.path.isfile(PERSIST + '/comma/id_rsa.pub'):\n    return None\n\n  with open(PERSIST + '/comma/id_rsa.pub', 'r') as f:\n    return f.read()\n\n\n@dispatcher.add_method\ndef getSshAuthorizedKeys():\n  return Params().get(\"GithubSshKeys\", encoding='utf8') or ''\n\n\n@dispatcher.add_method\ndef getSimInfo():\n  return HARDWARE.get_sim_info()\n\n\n@dispatcher.add_method\ndef getNetworkType():\n  return HARDWARE.get_network_type()\n\n\n@dispatcher.add_method\ndef getNetworks():\n  return HARDWARE.get_networks()\n\n\n@dispatcher.add_method\ndef takeSnapshot():\n  from selfdrive.camerad.snapshot.snapshot import snapshot, jpeg_write\n  ret = snapshot()\n  if ret is not None:\n    def b64jpeg(x):\n      if x is not None:\n        f = io.BytesIO()\n        jpeg_write(f, x)\n        return base64.b64encode(f.getvalue()).decode(\"utf-8\")\n      else:\n        return None\n    return {'jpegBack': b64jpeg(ret[0]),\n            'jpegFront': b64jpeg(ret[1])}\n  else:\n    raise Exception(\"not available while camerad is started\")\n\n\ndef get_logs_to_send_sorted():\n  # TODO: scan once then use inotify to detect file creation/deletion\n  curr_time = int(time.time())\n  logs = []\n  for log_entry in os.listdir(SWAGLOG_DIR):\n    log_path = os.path.join(SWAGLOG_DIR, log_entry)\n    try:\n      time_sent = int.from_bytes(getxattr(log_path, LOG_ATTR_NAME), sys.byteorder)\n    except (ValueError, TypeError):\n      time_sent = 0\n    # assume send failed and we lost the response if sent more than one hour ago\n    if not time_sent or curr_time - time_sent > 3600:\n      logs.append(log_entry)\n  # excluding most recent (active) log file\n  return sorted(logs)[:-1]\n\n\ndef log_handler(end_event):\n  if PC:\n    return\n\n  log_files = []\n  last_scan = 0\n  while not end_event.is_set():\n    try:\n      curr_scan = sec_since_boot()\n      if curr_scan - last_scan > 10:\n        log_files = get_logs_to_send_sorted()\n        last_scan = curr_scan\n\n      # send one log\n      curr_log = None\n      if len(log_files) > 0:\n        log_entry = log_files.pop() # newest log file\n        cloudlog.debug(f\"athena.log_handler.forward_request {log_entry}\")\n        try:\n          curr_time = int(time.time())\n          log_path = os.path.join(SWAGLOG_DIR, log_entry)\n          setxattr(log_path, LOG_ATTR_NAME, int.to_bytes(curr_time, 4, sys.byteorder))\n          with open(log_path, \"r\") as f:\n            jsonrpc = {\n              \"method\": \"forwardLogs\",\n              \"params\": {\n                \"logs\": f.read()\n              },\n              \"jsonrpc\": \"2.0\",\n              \"id\": log_entry\n            }\n            log_send_queue.put_nowait(json.dumps(jsonrpc))\n            curr_log = log_entry\n        except OSError:\n          pass  # file could be deleted by log rotation\n\n      # wait for response up to ~100 seconds\n      # always read queue at least once to process any old responses that arrive\n      for _ in range(100):\n        if end_event.is_set():\n          break\n        try:\n          log_resp = json.loads(log_recv_queue.get(timeout=1))\n          log_entry = log_resp.get(\"id\")\n          log_success = \"result\" in log_resp and log_resp[\"result\"].get(\"success\")\n          cloudlog.debug(f\"athena.log_handler.forward_response {log_entry} {log_success}\")\n          if log_entry and log_success:\n            log_path = os.path.join(SWAGLOG_DIR, log_entry)\n            try:\n              setxattr(log_path, LOG_ATTR_NAME, LOG_ATTR_VALUE_MAX_UNIX_TIME)\n            except OSError:\n              pass  # file could be deleted by log rotation\n          if curr_log == log_entry:\n            break\n        except queue.Empty:\n          if curr_log is None:\n            break\n\n    except Exception:\n      cloudlog.exception(\"athena.log_handler.exception\")\n\n\ndef ws_proxy_recv(ws, local_sock, ssock, end_event, global_end_event):\n  while not (end_event.is_set() or global_end_event.is_set()):\n    try:\n      data = ws.recv()\n      local_sock.sendall(data)\n    except WebSocketTimeoutException:\n      pass\n    except Exception:\n      cloudlog.exception(\"athenad.ws_proxy_recv.exception\")\n      break\n\n  cloudlog.debug(\"athena.ws_proxy_recv closing sockets\")\n  ssock.close()\n  local_sock.close()\n  cloudlog.debug(\"athena.ws_proxy_recv done closing sockets\")\n\n  end_event.set()\n\n\ndef ws_proxy_send(ws, local_sock, signal_sock, end_event):\n  while not end_event.is_set():\n    try:\n      r, _, _ = select.select((local_sock, signal_sock), (), ())\n      if r:\n        if r[0].fileno() == signal_sock.fileno():\n          # got end signal from ws_proxy_recv\n          end_event.set()\n          break\n        data = local_sock.recv(4096)\n        if not data:\n          # local_sock is dead\n          end_event.set()\n          break\n\n        ws.send(data, ABNF.OPCODE_BINARY)\n    except Exception:\n      cloudlog.exception(\"athenad.ws_proxy_send.exception\")\n      end_event.set()\n\n  cloudlog.debug(\"athena.ws_proxy_send closing sockets\")\n  signal_sock.close()\n  cloudlog.debug(\"athena.ws_proxy_send done closing sockets\")\n\n\ndef ws_recv(ws, end_event):\n  last_ping = int(sec_since_boot() * 1e9)\n  while not end_event.is_set():\n    try:\n      opcode, data = ws.recv_data(control_frame=True)\n      if opcode in (ABNF.OPCODE_TEXT, ABNF.OPCODE_BINARY):\n        if opcode == ABNF.OPCODE_TEXT:\n          data = data.decode(\"utf-8\")\n        recv_queue.put_nowait(data)\n      elif opcode == ABNF.OPCODE_PING:\n        last_ping = int(sec_since_boot() * 1e9)\n        Params().put(\"LastAthenaPingTime\", str(last_ping))\n    except WebSocketTimeoutException:\n      ns_since_last_ping = int(sec_since_boot() * 1e9) - last_ping\n      if ns_since_last_ping > RECONNECT_TIMEOUT_S * 1e9:\n        cloudlog.exception(\"athenad.ws_recv.timeout\")\n        end_event.set()\n    except Exception:\n      cloudlog.exception(\"athenad.ws_recv.exception\")\n      end_event.set()\n\n\ndef ws_send(ws, end_event):\n  while not end_event.is_set():\n    try:\n      try:\n        data = send_queue.get_nowait()\n      except queue.Empty:\n        data = log_send_queue.get(timeout=1)\n      for i in range(0, len(data), WS_FRAME_SIZE):\n        frame = data[i:i+WS_FRAME_SIZE]\n        last = i + WS_FRAME_SIZE >= len(data)\n        opcode = ABNF.OPCODE_TEXT if i == 0 else ABNF.OPCODE_CONT\n        ws.send_frame(ABNF.create_frame(frame, opcode, last))\n    except queue.Empty:\n      pass\n    except Exception:\n      cloudlog.exception(\"athenad.ws_send.exception\")\n      end_event.set()\n\n\ndef backoff(retries):\n  return random.randrange(0, min(128, int(2 ** retries)))\n\n\ndef manage_tokens(api):\n  if not TICI:\n    return\n\n  try:\n    params = Params()\n    mapbox = api.get(f\"/v1/tokens/mapbox/{api.dongle_id}/\", timeout=5.0, access_token=api.get_token())\n    if mapbox.status_code == 200:\n      params.put(\"MapboxToken\", mapbox.json()[\"token\"])\n    else:\n      params.delete(\"MapboxToken\")\n  except Exception:\n    cloudlog.exception(\"Failed to update tokens\")\n\n\ndef main():\n  params = Params()\n  dongle_id = params.get(\"DongleId\", encoding='utf-8')\n\n  ws_uri = ATHENA_HOST + \"/ws/v2/\" + dongle_id\n  api = Api(dongle_id)\n\n  conn_retries = 0\n  while 1:\n    try:\n      cloudlog.event(\"athenad.main.connecting_ws\", ws_uri=ws_uri)\n      ws = create_connection(ws_uri,\n                             cookie=\"jwt=\" + api.get_token(),\n                             enable_multithread=True,\n                             timeout=30.0)\n      cloudlog.event(\"athenad.main.connected_ws\", ws_uri=ws_uri)\n      params.delete(\"PrimeRedirected\")\n\n      manage_tokens(api)\n\n      conn_retries = 0\n      cur_upload_items.clear()\n\n      handle_long_poll(ws)\n    except (KeyboardInterrupt, SystemExit):\n      break\n    except (ConnectionError, TimeoutError, WebSocketException):\n      conn_retries += 1\n      params.delete(\"PrimeRedirected\")\n      params.delete(\"LastAthenaPingTime\")\n    except socket.timeout:\n      try:\n        r = requests.get(API_HOST + \"/v1/me\", allow_redirects=False,\n                         headers={\"User-Agent\": f\"openpilot-{version}\"}, timeout=15.0)\n        if r.status_code == 302 and r.headers['Location'].startswith(\"http://u.web2go.com\"):\n          params.put_bool(\"PrimeRedirected\", True)\n      except Exception:\n        cloudlog.exception(\"athenad.socket_timeout.exception\")\n      params.delete(\"LastAthenaPingTime\")\n    except Exception:\n      cloudlog.exception(\"athenad.main.exception\")\n\n      conn_retries += 1\n      params.delete(\"PrimeRedirected\")\n      params.delete(\"LastAthenaPingTime\")\n\n    time.sleep(backoff(conn_retries))\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/athena/manage_athenad.py",
    "content": "#!/usr/bin/env python3\n\nimport time\nfrom multiprocessing import Process\n\nfrom common.params import Params\nfrom selfdrive.manager.process import launcher\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.version import version, dirty\n\nATHENA_MGR_PID_PARAM = \"AthenadPid\"\n\n\ndef main():\n  params = Params()\n  dongle_id = params.get(\"DongleId\").decode('utf-8')\n  cloudlog.bind_global(dongle_id=dongle_id, version=version, dirty=dirty)\n\n  try:\n    while 1:\n      cloudlog.info(\"starting athena daemon\")\n      proc = Process(name='athenad', target=launcher, args=('selfdrive.athena.athenad',))\n      proc.start()\n      proc.join()\n      cloudlog.event(\"athenad exited\", exitcode=proc.exitcode)\n      time.sleep(5)\n  except Exception:\n    cloudlog.exception(\"manage_athenad.exception\")\n  finally:\n    params.delete(ATHENA_MGR_PID_PARAM)\n\n\nif __name__ == '__main__':\n  main()\n"
  },
  {
    "path": "selfdrive/athena/registration.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport time\nimport json\nimport jwt\n\nfrom datetime import datetime, timedelta\nfrom common.api import api_get\nfrom common.params import Params\nfrom common.spinner import Spinner\nfrom common.file_helpers import mkdirs_exists_ok\nfrom common.basedir import PERSIST\nfrom selfdrive.controls.lib.alertmanager import set_offroad_alert\nfrom selfdrive.hardware import HARDWARE\nfrom selfdrive.swaglog import cloudlog\n\n\nUNREGISTERED_DONGLE_ID = \"UnregisteredDevice\"\n\n\ndef register(show_spinner=False) -> str:\n  params = Params()\n  params.put(\"SubscriberInfo\", HARDWARE.get_subscriber_info())\n\n  IMEI = params.get(\"IMEI\", encoding='utf8')\n  HardwareSerial = params.get(\"HardwareSerial\", encoding='utf8')\n  dongle_id = params.get(\"DongleId\", encoding='utf8')\n  needs_registration = None in (IMEI, HardwareSerial, dongle_id)\n\n  # create a key for auth\n  # your private key is kept on your device persist partition and never sent to our servers\n  # do not erase your persist partition\n  if not os.path.isfile(PERSIST+\"/comma/id_rsa.pub\"):\n    needs_registration = True\n    cloudlog.warning(\"generating your personal RSA key\")\n    mkdirs_exists_ok(PERSIST+\"/comma\")\n    assert os.system(\"openssl genrsa -out \"+PERSIST+\"/comma/id_rsa.tmp 2048\") == 0\n    assert os.system(\"openssl rsa -in \"+PERSIST+\"/comma/id_rsa.tmp -pubout -out \"+PERSIST+\"/comma/id_rsa.tmp.pub\") == 0\n    os.rename(PERSIST+\"/comma/id_rsa.tmp\", PERSIST+\"/comma/id_rsa\")\n    os.rename(PERSIST+\"/comma/id_rsa.tmp.pub\", PERSIST+\"/comma/id_rsa.pub\")\n\n  if needs_registration:\n    if show_spinner:\n      spinner = Spinner()\n      spinner.update(\"registering device\")\n\n    # Create registration token, in the future, this key will make JWTs directly\n    with open(PERSIST+\"/comma/id_rsa.pub\") as f1, open(PERSIST+\"/comma/id_rsa\") as f2:\n      public_key = f1.read()\n      private_key = f2.read()\n\n    # Block until we get the imei\n    serial = HARDWARE.get_serial()\n    start_time = time.monotonic()\n    imei1, imei2 = None, None\n    while imei1 is None and imei2 is None:\n      try:\n        imei1, imei2 = HARDWARE.get_imei(0), HARDWARE.get_imei(1)\n      except Exception:\n        cloudlog.exception(\"Error getting imei, trying again...\")\n        time.sleep(1)\n\n      if time.monotonic() - start_time > 60 and show_spinner:\n        spinner.update(f\"registering device - serial: {serial}, IMEI: ({imei1}, {imei2})\")\n\n    params.put(\"IMEI\", imei1)\n    params.put(\"HardwareSerial\", serial)\n\n    backoff = 0\n    start_time = time.monotonic()\n    while True:\n      try:\n        register_token = jwt.encode({'register': True, 'exp': datetime.utcnow() + timedelta(hours=1)}, private_key, algorithm='RS256')\n        cloudlog.info(\"getting pilotauth\")\n        resp = api_get(\"v2/pilotauth/\", method='POST', timeout=15,\n                       imei=imei1, imei2=imei2, serial=serial, public_key=public_key, register_token=register_token)\n\n        if resp.status_code in (402, 403):\n          cloudlog.info(f\"Unable to register device, got {resp.status_code}\")\n          dongle_id = UNREGISTERED_DONGLE_ID\n        else:\n          dongleauth = json.loads(resp.text)\n          dongle_id = dongleauth[\"dongle_id\"]\n        break\n      except Exception:\n        cloudlog.exception(\"failed to authenticate\")\n        backoff = min(backoff + 1, 15)\n        time.sleep(backoff)\n\n      if time.monotonic() - start_time > 60 and show_spinner:\n        spinner.update(f\"registering device - serial: {serial}, IMEI: ({imei1}, {imei2})\")\n\n    if show_spinner:\n      spinner.close()\n\n  if dongle_id:\n    params.put(\"DongleId\", dongle_id)\n    set_offroad_alert(\"Offroad_UnofficialHardware\", dongle_id == UNREGISTERED_DONGLE_ID)\n  return dongle_id\n\n\nif __name__ == \"__main__\":\n  print(register())\n"
  },
  {
    "path": "selfdrive/camerad/SConscript",
    "content": "Import('env', 'arch', 'cereal', 'messaging', 'common', 'gpucommon', 'visionipc', 'USE_WEBCAM', 'USE_MIPI')\n\nlibs = ['m', 'pthread', common, 'jpeg', 'OpenCL', cereal, messaging, 'zmq', 'capnp', 'kj', visionipc, gpucommon]\n\nif arch == \"aarch64\":\n  libs += ['gsl', 'CB', 'adreno_utils', 'EGL', 'GLESv3', 'cutils', 'ui']\n  cameras = ['cameras/camera_qcom.cc']\nelif arch == \"larch64\":\n  libs += ['atomic']\n  cameras = ['cameras/camera_qcom2.cc']\nelse:\n  if USE_MIPI or USE_WEBCAM:\n    flag = \"MIPI\" if USE_MIPI else \"WEBCAM\"\n\n    libs += ['opencv_core', 'opencv_highgui', 'opencv_imgproc', 'opencv_videoio']\n    if USE_MIPI:\n      libs += ['opencv_cudawarping']\n    cameras = ['cameras/camera_%s.cc' % flag.lower()]\n    env = env.Clone()\n    env.Append(CXXFLAGS = \"-D%s\" % flag)\n    env.Append(CFLAGS = \"-D%s\" % flag)\n    env.Append(CPPPATH = ['/usr/include/opencv4', '/usr/local/include/opencv4'])\n  else:\n    cameras = ['cameras/camera_frame_stream.cc']\n\n  if arch == \"Darwin\":\n    del libs[libs.index('OpenCL')]\n    del libs[libs.index(gpucommon)][gpucommon.index('GL')]\n    env = env.Clone()\n    env['FRAMEWORKS'] = ['OpenCL', 'OpenGL']\n\nenv.Program('camerad', [\n    'main.cc',\n    'cameras/camera_common.cc',\n    'transforms/rgb_to_yuv.cc',\n    'imgproc/utils.cc',\n    cameras,\n  ], LIBS=libs)\n\nif GetOption(\"test\"):\n  env.Program('test/ae_gray_test', [\n      'test/ae_gray_test.cc',\n      'cameras/camera_common.cc',\n      'transforms/rgb_to_yuv.cc',\n    ], LIBS=libs)\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_common.cc",
    "content": "#include \"selfdrive/camerad/cameras/camera_common.h\"\n\n#include <unistd.h>\n\n#include <cassert>\n#include <cstdio>\n#include <chrono>\n#include <thread>\n\n#include \"libyuv.h\"\n#include <jpeglib.h>\n\n#include \"selfdrive/camerad/imgproc/utils.h\"\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/modeldata.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n\n#ifdef QCOM\n#include \"selfdrive/camerad/cameras/camera_qcom.h\"\n#elif QCOM2\n#include \"selfdrive/camerad/cameras/camera_qcom2.h\"\n#elif WEBCAM\n#include \"selfdrive/camerad/cameras/camera_webcam.h\"\n#elif MIPI\n#include \"selfdrive/camerad/cameras/camera_mipi.h\"\n#else\n#include \"selfdrive/camerad/cameras/camera_frame_stream.h\"\n#endif\n\nconst int YUV_COUNT = 100;\n\nstatic cl_program build_debayer_program(cl_device_id device_id, cl_context context, const CameraInfo *ci, const CameraBuf *b, const CameraState *s) {\n  char args[4096];\n  snprintf(args, sizeof(args),\n           \"-cl-fast-relaxed-math -cl-denorms-are-zero \"\n           \"-DFRAME_WIDTH=%d -DFRAME_HEIGHT=%d -DFRAME_STRIDE=%d \"\n           \"-DRGB_WIDTH=%d -DRGB_HEIGHT=%d -DRGB_STRIDE=%d \"\n           \"-DBAYER_FLIP=%d -DHDR=%d -DCAM_NUM=%d\",\n           ci->frame_width, ci->frame_height, ci->frame_stride,\n           b->rgb_width, b->rgb_height, b->rgb_stride,\n           ci->bayer_flip, ci->hdr, s->camera_num);\n  const char *cl_file = Hardware::TICI() ? \"cameras/real_debayer.cl\" : \"cameras/debayer.cl\";\n  return cl_program_from_file(context, device_id, cl_file, args);\n}\n\nvoid CameraBuf::init(cl_device_id device_id, cl_context context, CameraState *s, VisionIpcServer * v, int frame_cnt, VisionStreamType rgb_type, VisionStreamType yuv_type, release_cb release_callback) {\n  vipc_server = v;\n  this->rgb_type = rgb_type;\n  this->yuv_type = yuv_type;\n  this->release_callback = release_callback;\n\n  const CameraInfo *ci = &s->ci;\n  camera_state = s;\n  frame_buf_count = frame_cnt;\n\n  // RAW frame\n  const int frame_size = ci->frame_height * ci->frame_stride;\n  camera_bufs = std::make_unique<VisionBuf[]>(frame_buf_count);\n  camera_bufs_metadata = std::make_unique<FrameMetadata[]>(frame_buf_count);\n\n  for (int i = 0; i < frame_buf_count; i++) {\n    camera_bufs[i].allocate(frame_size);\n    camera_bufs[i].init_cl(device_id, context);\n  }\n\n  rgb_width = ci->frame_width;\n  rgb_height = ci->frame_height;\n\n  if (!Hardware::TICI() && ci->bayer) {\n    // debayering does a 2x downscale\n    rgb_width = ci->frame_width / 2;\n    rgb_height = ci->frame_height / 2;\n  }\n\n  yuv_transform = get_model_yuv_transform(ci->bayer);\n\n  vipc_server->create_buffers(rgb_type, UI_BUF_COUNT, true, rgb_width, rgb_height);\n  rgb_stride = vipc_server->get_buffer(rgb_type)->stride;\n\n  vipc_server->create_buffers(yuv_type, YUV_COUNT, false, rgb_width, rgb_height);\n\n  if (ci->bayer) {\n    cl_program prg_debayer = build_debayer_program(device_id, context, ci, this, s);\n    krnl_debayer = CL_CHECK_ERR(clCreateKernel(prg_debayer, \"debayer10\", &err));\n    CL_CHECK(clReleaseProgram(prg_debayer));\n  }\n\n  rgb2yuv = std::make_unique<Rgb2Yuv>(context, device_id, rgb_width, rgb_height, rgb_stride);\n\n#ifdef __APPLE__\n  q = CL_CHECK_ERR(clCreateCommandQueue(context, device_id, 0, &err));\n#else\n  const cl_queue_properties props[] = {0};  //CL_QUEUE_PRIORITY_KHR, CL_QUEUE_PRIORITY_HIGH_KHR, 0};\n  q = CL_CHECK_ERR(clCreateCommandQueueWithProperties(context, device_id, props, &err));\n#endif\n}\n\nCameraBuf::~CameraBuf() {\n  for (int i = 0; i < frame_buf_count; i++) {\n    camera_bufs[i].free();\n  }\n\n  if (krnl_debayer) CL_CHECK(clReleaseKernel(krnl_debayer));\n  if (q) CL_CHECK(clReleaseCommandQueue(q));\n}\n\nbool CameraBuf::acquire() {\n  if (!safe_queue.try_pop(cur_buf_idx, 1)) return false;\n\n  if (camera_bufs_metadata[cur_buf_idx].frame_id == -1) {\n    LOGE(\"no frame data? wtf\");\n    release();\n    return false;\n  }\n\n  cur_frame_data = camera_bufs_metadata[cur_buf_idx];\n  cur_rgb_buf = vipc_server->get_buffer(rgb_type);\n\n  cl_event debayer_event;\n  cl_mem camrabuf_cl = camera_bufs[cur_buf_idx].buf_cl;\n  if (camera_state->ci.bayer) {\n    CL_CHECK(clSetKernelArg(krnl_debayer, 0, sizeof(cl_mem), &camrabuf_cl));\n    CL_CHECK(clSetKernelArg(krnl_debayer, 1, sizeof(cl_mem), &cur_rgb_buf->buf_cl));\n#ifdef QCOM2\n    constexpr int localMemSize = (DEBAYER_LOCAL_WORKSIZE + 2 * (3 / 2)) * (DEBAYER_LOCAL_WORKSIZE + 2 * (3 / 2)) * sizeof(short int);\n    const size_t globalWorkSize[] = {size_t(camera_state->ci.frame_width), size_t(camera_state->ci.frame_height)};\n    const size_t localWorkSize[] = {DEBAYER_LOCAL_WORKSIZE, DEBAYER_LOCAL_WORKSIZE};\n    CL_CHECK(clSetKernelArg(krnl_debayer, 2, localMemSize, 0));\n    CL_CHECK(clEnqueueNDRangeKernel(q, krnl_debayer, 2, NULL, globalWorkSize, localWorkSize,\n                                    0, 0, &debayer_event));\n#else\n    float digital_gain = camera_state->digital_gain;\n    if ((int)digital_gain == 0) {\n      digital_gain = 1.0;\n    }\n    CL_CHECK(clSetKernelArg(krnl_debayer, 2, sizeof(float), &digital_gain));\n    const size_t debayer_work_size = rgb_height;  // doesn't divide evenly, is this okay?\n    CL_CHECK(clEnqueueNDRangeKernel(q, krnl_debayer, 1, NULL,\n                                    &debayer_work_size, NULL, 0, 0, &debayer_event));\n#endif\n  } else {\n    assert(rgb_stride == camera_state->ci.frame_stride);\n    CL_CHECK(clEnqueueCopyBuffer(q, camrabuf_cl, cur_rgb_buf->buf_cl, 0, 0,\n                               cur_rgb_buf->len, 0, 0, &debayer_event));\n  }\n\n  clWaitForEvents(1, &debayer_event);\n  CL_CHECK(clReleaseEvent(debayer_event));\n\n  cur_yuv_buf = vipc_server->get_buffer(yuv_type);\n  rgb2yuv->queue(q, cur_rgb_buf->buf_cl, cur_yuv_buf->buf_cl);\n\n  VisionIpcBufExtra extra = {\n                        cur_frame_data.frame_id,\n                        cur_frame_data.timestamp_sof,\n                        cur_frame_data.timestamp_eof,\n  };\n  vipc_server->send(cur_rgb_buf, &extra);\n  vipc_server->send(cur_yuv_buf, &extra);\n\n  return true;\n}\n\nvoid CameraBuf::release() {\n  if (release_callback) {\n    release_callback((void*)camera_state, cur_buf_idx);\n  }\n}\n\nvoid CameraBuf::queue(size_t buf_idx) {\n  safe_queue.push(buf_idx);\n}\n\n// common functions\n\nvoid fill_frame_data(cereal::FrameData::Builder &framed, const FrameMetadata &frame_data) {\n  framed.setFrameId(frame_data.frame_id);\n  framed.setTimestampEof(frame_data.timestamp_eof);\n  framed.setTimestampSof(frame_data.timestamp_sof);\n  framed.setFrameLength(frame_data.frame_length);\n  framed.setIntegLines(frame_data.integ_lines);\n  framed.setGain(frame_data.gain);\n  framed.setHighConversionGain(frame_data.high_conversion_gain);\n  framed.setMeasuredGreyFraction(frame_data.measured_grey_fraction);\n  framed.setTargetGreyFraction(frame_data.target_grey_fraction);\n  framed.setLensPos(frame_data.lens_pos);\n  framed.setLensSag(frame_data.lens_sag);\n  framed.setLensErr(frame_data.lens_err);\n  framed.setLensTruePos(frame_data.lens_true_pos);\n}\n\nkj::Array<uint8_t> get_frame_image(const CameraBuf *b) {\n  static const int x_min = util::getenv(\"XMIN\", 0);\n  static const int y_min = util::getenv(\"YMIN\", 0);\n  static const int env_xmax = util::getenv(\"XMAX\", -1);\n  static const int env_ymax = util::getenv(\"YMAX\", -1);\n  static const int scale = util::getenv(\"SCALE\", 1);\n\n  assert(b->cur_rgb_buf);\n\n  const int x_max = env_xmax != -1 ? env_xmax : b->rgb_width - 1;\n  const int y_max = env_ymax != -1 ? env_ymax : b->rgb_height - 1;\n  const int new_width = (x_max - x_min + 1) / scale;\n  const int new_height = (y_max - y_min + 1) / scale;\n  const uint8_t *dat = (const uint8_t *)b->cur_rgb_buf->addr;\n\n  kj::Array<uint8_t> frame_image = kj::heapArray<uint8_t>(new_width*new_height*3);\n  uint8_t *resized_dat = frame_image.begin();\n  int goff = x_min*3 + y_min*b->rgb_stride;\n  for (int r=0;r<new_height;r++) {\n    for (int c=0;c<new_width;c++) {\n      memcpy(&resized_dat[(r*new_width+c)*3], &dat[goff+r*b->rgb_stride*scale+c*3*scale], 3*sizeof(uint8_t));\n    }\n  }\n  return kj::mv(frame_image);\n}\n\nstatic void publish_thumbnail(PubMaster *pm, const CameraBuf *b) {\n  uint8_t* thumbnail_buffer = NULL;\n  unsigned long thumbnail_len = 0;\n\n  unsigned char *row = (unsigned char *)malloc(b->rgb_width/4*3);\n\n  struct jpeg_compress_struct cinfo;\n  struct jpeg_error_mgr jerr;\n\n  cinfo.err = jpeg_std_error(&jerr);\n  jpeg_create_compress(&cinfo);\n  jpeg_mem_dest(&cinfo, &thumbnail_buffer, &thumbnail_len);\n\n  cinfo.image_width = b->rgb_width / 4;\n  cinfo.image_height = b->rgb_height / 4;\n  cinfo.input_components = 3;\n  cinfo.in_color_space = JCS_RGB;\n\n  jpeg_set_defaults(&cinfo);\n#ifndef __APPLE__\n  jpeg_set_quality(&cinfo, 50, true);\n  jpeg_start_compress(&cinfo, true);\n#else\n  jpeg_set_quality(&cinfo, 50, static_cast<boolean>(true) );\n  jpeg_start_compress(&cinfo, static_cast<boolean>(true) );\n#endif\n\n  JSAMPROW row_pointer[1];\n  const uint8_t *bgr_ptr = (const uint8_t *)b->cur_rgb_buf->addr;\n  for (int ii = 0; ii < b->rgb_height/4; ii+=1) {\n    for (int j = 0; j < b->rgb_width*3; j+=12) {\n      for (int k = 0; k < 3; k++) {\n        uint16_t dat = 0;\n        int i = ii * 4;\n        dat += bgr_ptr[b->rgb_stride*i + j + k];\n        dat += bgr_ptr[b->rgb_stride*i + j+3 + k];\n        dat += bgr_ptr[b->rgb_stride*(i+1) + j + k];\n        dat += bgr_ptr[b->rgb_stride*(i+1) + j+3 + k];\n        dat += bgr_ptr[b->rgb_stride*(i+2) + j + k];\n        dat += bgr_ptr[b->rgb_stride*(i+2) + j+3 + k];\n        dat += bgr_ptr[b->rgb_stride*(i+3) + j + k];\n        dat += bgr_ptr[b->rgb_stride*(i+3) + j+3 + k];\n        row[(j/4) + (2-k)] = dat/8;\n      }\n    }\n    row_pointer[0] = row;\n    jpeg_write_scanlines(&cinfo, row_pointer, 1);\n  }\n  jpeg_finish_compress(&cinfo);\n  jpeg_destroy_compress(&cinfo);\n  free(row);\n\n  MessageBuilder msg;\n  auto thumbnaild = msg.initEvent().initThumbnail();\n  thumbnaild.setFrameId(b->cur_frame_data.frame_id);\n  thumbnaild.setTimestampEof(b->cur_frame_data.timestamp_eof);\n  thumbnaild.setThumbnail(kj::arrayPtr((const uint8_t*)thumbnail_buffer, thumbnail_len));\n\n  pm->send(\"thumbnail\", msg);\n  free(thumbnail_buffer);\n}\n\nfloat set_exposure_target(const CameraBuf *b, int x_start, int x_end, int x_skip, int y_start, int y_end, int y_skip) {\n  int lum_med;\n  uint32_t lum_binning[256] = {0};\n  const uint8_t *pix_ptr = b->cur_yuv_buf->y;\n\n  unsigned int lum_total = 0;\n  for (int y = y_start; y < y_end; y += y_skip) {\n    for (int x = x_start; x < x_end; x += x_skip) {\n      uint8_t lum = pix_ptr[(y * b->rgb_width) + x];\n      lum_binning[lum]++;\n      lum_total += 1;\n    }\n  }\n\n\n  // Find mean lumimance value\n  unsigned int lum_cur = 0;\n  for (lum_med = 255; lum_med >= 0; lum_med--) {\n    lum_cur += lum_binning[lum_med];\n\n    if (lum_cur >= lum_total / 2) {\n      break;\n    }\n  }\n\n  return lum_med / 256.0;\n}\n\nextern ExitHandler do_exit;\n\nvoid *processing_thread(MultiCameraState *cameras, CameraState *cs, process_thread_cb callback) {\n  const char *thread_name = nullptr;\n  if (cs == &cameras->road_cam) {\n    thread_name = \"RoadCamera\";\n  } else if (cs == &cameras->driver_cam) {\n    thread_name = \"DriverCamera\";\n  } else {\n    thread_name = \"WideRoadCamera\";\n  }\n  set_thread_name(thread_name);\n\n  uint32_t cnt = 0;\n  while (!do_exit) {\n    if (!cs->buf.acquire()) continue;\n\n    callback(cameras, cs, cnt);\n\n    if (cs == &(cameras->road_cam) && cameras->pm && cnt % 100 == 3) {\n      // this takes 10ms???\n      publish_thumbnail(cameras->pm, &(cs->buf));\n    }\n    cs->buf.release();\n    ++cnt;\n  }\n  return NULL;\n}\n\nstd::thread start_process_thread(MultiCameraState *cameras, CameraState *cs, process_thread_cb callback) {\n  return std::thread(processing_thread, cameras, cs, callback);\n}\n\nstatic void driver_cam_auto_exposure(CameraState *c, SubMaster &sm) {\n  static const bool is_rhd = Params().getBool(\"IsRHD\");\n  struct ExpRect {int x1, x2, x_skip, y1, y2, y_skip;};\n  const CameraBuf *b = &c->buf;\n\n  int x_offset = 0, y_offset = 0;\n  int frame_width = b->rgb_width, frame_height = b->rgb_height;\n\n\n  ExpRect def_rect;\n  if (Hardware::TICI()) {\n    x_offset = 630, y_offset = 156;\n    frame_width = 668, frame_height = frame_width / 1.33;\n    def_rect = {96, 1832, 2, 242, 1148, 4};\n  } else {\n    def_rect = {is_rhd ? 0 : b->rgb_width * 3 / 5, is_rhd ? b->rgb_width * 2 / 5 : b->rgb_width, 2,\n                b->rgb_height / 3, b->rgb_height, 1};\n  }\n\n  static ExpRect rect = def_rect;\n  // use driver face crop for AE\n  if (Hardware::EON() && sm.updated(\"driverState\")) {\n    if (auto state = sm[\"driverState\"].getDriverState(); state.getFaceProb() > 0.4) {\n      auto face_position = state.getFacePosition();\n      int x = is_rhd ? 0 : frame_width - (0.5 * frame_height);\n      x += (face_position[0] * (is_rhd ? -1.0 : 1.0) + 0.5) * (0.5 * frame_height) + x_offset;\n      int y = (face_position[1] + 0.5) * frame_height + y_offset;\n      rect = {std::max(0, x - 72), std::min(b->rgb_width - 1, x + 72), 2,\n              std::max(0, y - 72), std::min(b->rgb_height - 1, y + 72), 1};\n    }\n  }\n\n  camera_autoexposure(c, set_exposure_target(b, rect.x1, rect.x2, rect.x_skip, rect.y1, rect.y2, rect.y_skip));\n}\n\nvoid common_process_driver_camera(SubMaster *sm, PubMaster *pm, CameraState *c, int cnt) {\n  int j = Hardware::TICI() ? 1 : 3;\n  if (cnt % j == 0) {\n    sm->update(0);\n    driver_cam_auto_exposure(c, *sm);\n  }\n  MessageBuilder msg;\n  auto framed = msg.initEvent().initDriverCameraState();\n  framed.setFrameType(cereal::FrameData::FrameType::FRONT);\n  fill_frame_data(framed, c->buf.cur_frame_data);\n  if (env_send_driver) {\n    framed.setImage(get_frame_image(&c->buf));\n  }\n  pm->send(\"driverCameraState\", msg);\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_common.h",
    "content": "#pragma once\n\n#include <cstdint>\n#include <cstdlib>\n#include <memory>\n#include <thread>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"cereal/visionipc/visionbuf.h\"\n#include \"cereal/visionipc/visionipc.h\"\n#include \"cereal/visionipc/visionipc_server.h\"\n#include \"selfdrive/camerad/transforms/rgb_to_yuv.h\"\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/queue.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/visionimg.h\"\n\n#define CAMERA_ID_IMX298 0\n#define CAMERA_ID_IMX179 1\n#define CAMERA_ID_S5K3P8SP 2\n#define CAMERA_ID_OV8865 3\n#define CAMERA_ID_IMX298_FLIPPED 4\n#define CAMERA_ID_OV10640 5\n#define CAMERA_ID_LGC920 6\n#define CAMERA_ID_LGC615 7\n#define CAMERA_ID_AR0231 8\n#define CAMERA_ID_IMX477 9\n#define CAMERA_ID_MAX 10\n\n#define UI_BUF_COUNT 4\n\nenum CameraType {\n  RoadCam = 0,\n  DriverCam,\n  WideRoadCam\n};\n\nconst bool env_send_driver = getenv(\"SEND_DRIVER\") != NULL;\nconst bool env_send_road = getenv(\"SEND_ROAD\") != NULL;\nconst bool env_send_wide_road = getenv(\"SEND_WIDE_ROAD\") != NULL;\n\ntypedef void (*release_cb)(void *cookie, int buf_idx);\n\ntypedef struct CameraInfo {\n  int frame_width, frame_height;\n  int frame_stride;\n  bool bayer;\n  int bayer_flip;\n  bool hdr;\n} CameraInfo;\n\ntypedef struct LogCameraInfo {\n  CameraType type;\n  const char* filename;\n  const char* frame_packet_name;\n  const char* encode_idx_name;\n  VisionStreamType stream_type;\n  int frame_width, frame_height;\n  int fps;\n  int bitrate;\n  bool is_h265;\n  bool downscale;\n  bool has_qcamera;\n  bool trigger_rotate;\n  bool enable;\n} LogCameraInfo;\n\ntypedef struct FrameMetadata {\n  uint32_t frame_id;\n  unsigned int frame_length;\n\n  // Timestamps\n  uint64_t timestamp_sof; // only set on tici\n  uint64_t timestamp_eof;\n\n  // Exposure\n  unsigned int integ_lines;\n  bool high_conversion_gain;\n  float gain;\n  float measured_grey_fraction;\n  float target_grey_fraction;\n\n  // Focus\n  unsigned int lens_pos;\n  float lens_sag;\n  float lens_err;\n  float lens_true_pos;\n} FrameMetadata;\n\ntypedef struct CameraExpInfo {\n  int op_id;\n  float grey_frac;\n} CameraExpInfo;\n\nstruct MultiCameraState;\nstruct CameraState;\n\nclass CameraBuf {\nprivate:\n  VisionIpcServer *vipc_server;\n  CameraState *camera_state;\n  cl_kernel krnl_debayer;\n\n  std::unique_ptr<Rgb2Yuv> rgb2yuv;\n\n  VisionStreamType rgb_type, yuv_type;\n\n  int cur_buf_idx;\n\n  SafeQueue<int> safe_queue;\n\n  int frame_buf_count;\n  release_cb release_callback;\n\npublic:\n  cl_command_queue q;\n  FrameMetadata cur_frame_data;\n  VisionBuf *cur_rgb_buf;\n  VisionBuf *cur_yuv_buf;\n  std::unique_ptr<VisionBuf[]> camera_bufs;\n  std::unique_ptr<FrameMetadata[]> camera_bufs_metadata;\n  int rgb_width, rgb_height, rgb_stride;\n\n  mat3 yuv_transform;\n\n  CameraBuf() = default;\n  ~CameraBuf();\n  void init(cl_device_id device_id, cl_context context, CameraState *s, VisionIpcServer * v, int frame_cnt, VisionStreamType rgb_type, VisionStreamType yuv_type, release_cb release_callback=nullptr);\n  bool acquire();\n  void release();\n  void queue(size_t buf_idx);\n};\n\ntypedef void (*process_thread_cb)(MultiCameraState *s, CameraState *c, int cnt);\n\nvoid fill_frame_data(cereal::FrameData::Builder &framed, const FrameMetadata &frame_data);\nkj::Array<uint8_t> get_frame_image(const CameraBuf *b);\nfloat set_exposure_target(const CameraBuf *b, int x_start, int x_end, int x_skip, int y_start, int y_end, int y_skip);\nstd::thread start_process_thread(MultiCameraState *cameras, CameraState *cs, process_thread_cb callback);\nvoid common_process_driver_camera(SubMaster *sm, PubMaster *pm, CameraState *c, int cnt);\n\nvoid cameras_init(VisionIpcServer *v, MultiCameraState *s, cl_device_id device_id, cl_context ctx);\nvoid cameras_open(MultiCameraState *s);\nvoid cameras_run(MultiCameraState *s);\nvoid cameras_close(MultiCameraState *s);\nvoid camera_autoexposure(CameraState *s, float grey_frac);\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_frame_stream.cc",
    "content": "#include \"selfdrive/camerad/cameras/camera_frame_stream.h\"\n\n#include <unistd.h>\n#include <cassert>\n\n#include <capnp/dynamic.h>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/util.h\"\n\n#define FRAME_WIDTH 1164\n#define FRAME_HEIGHT 874\n\nextern ExitHandler do_exit;\n\nnamespace {\n\n// TODO: make this more generic\nCameraInfo cameras_supported[CAMERA_ID_MAX] = {\n  [CAMERA_ID_IMX298] = {\n    .frame_width = FRAME_WIDTH,\n    .frame_height = FRAME_HEIGHT,\n    .frame_stride = FRAME_WIDTH*3,\n    .bayer = false,\n    .bayer_flip = false,\n  },\n  [CAMERA_ID_OV8865] = {\n    .frame_width = 1632,\n    .frame_height = 1224,\n    .frame_stride = 2040, // seems right\n    .bayer = false,\n    .bayer_flip = 3,\n    .hdr = false\n  },\n};\n\nvoid camera_init(VisionIpcServer * v, CameraState *s, int camera_id, unsigned int fps, cl_device_id device_id, cl_context ctx, VisionStreamType rgb_type, VisionStreamType yuv_type) {\n  assert(camera_id < std::size(cameras_supported));\n  s->ci = cameras_supported[camera_id];\n  assert(s->ci.frame_width != 0);\n\n  s->camera_num = camera_id;\n  s->fps = fps;\n  s->buf.init(device_id, ctx, s, v, FRAME_BUF_COUNT, rgb_type, yuv_type);\n}\n\nvoid run_frame_stream(CameraState &camera, const char* frame_pkt) {\n  SubMaster sm({frame_pkt});\n\n  size_t buf_idx = 0;\n  while (!do_exit) {\n    sm.update(1000);\n    if(sm.updated(frame_pkt)) {\n      auto msg = static_cast<capnp::DynamicStruct::Reader>(sm[frame_pkt]);\n      auto frame = msg.get(frame_pkt).as<capnp::DynamicStruct>();\n      camera.buf.camera_bufs_metadata[buf_idx] = {\n        .frame_id = frame.get(\"frameId\").as<uint32_t>(),\n        .timestamp_eof = frame.get(\"timestampEof\").as<uint64_t>(),\n        .timestamp_sof = frame.get(\"timestampSof\").as<uint64_t>(),\n      };\n\n      cl_command_queue q = camera.buf.camera_bufs[buf_idx].copy_q;\n      cl_mem yuv_cl = camera.buf.camera_bufs[buf_idx].buf_cl;\n\n      auto image = frame.get(\"image\").as<capnp::Data>();\n      clEnqueueWriteBuffer(q, yuv_cl, CL_TRUE, 0, image.size(), image.begin(), 0, NULL, NULL);\n      camera.buf.queue(buf_idx);\n      buf_idx = (buf_idx + 1) % FRAME_BUF_COUNT;\n    }\n  }\n}\n\n}  // namespace\n\nvoid cameras_init(VisionIpcServer *v, MultiCameraState *s, cl_device_id device_id, cl_context ctx) {\n  camera_init(v, &s->road_cam, CAMERA_ID_IMX298, 20, device_id, ctx,\n              VISION_STREAM_RGB_BACK, VISION_STREAM_YUV_BACK);\n  camera_init(v, &s->driver_cam, CAMERA_ID_OV8865, 10, device_id, ctx,\n              VISION_STREAM_RGB_FRONT, VISION_STREAM_YUV_FRONT);\n}\n\nvoid cameras_open(MultiCameraState *s) {}\nvoid cameras_close(MultiCameraState *s) {}\nvoid camera_autoexposure(CameraState *s, float grey_frac) {}\nvoid process_road_camera(MultiCameraState *s, CameraState *c, int cnt) {}\n\nvoid cameras_run(MultiCameraState *s) {\n  std::thread t = start_process_thread(s, &s->road_cam, process_road_camera);\n  set_thread_name(\"frame_streaming\");\n  run_frame_stream(s->road_cam, \"roadCameraState\");\n  t.join();\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_frame_stream.h",
    "content": "#pragma once\n\n#define CL_USE_DEPRECATED_OPENCL_1_2_APIS\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\n\n#include \"camera_common.h\"\n\n#define FRAME_BUF_COUNT 16\n\ntypedef struct CameraState {\n  int camera_num;\n  CameraInfo ci;\n\n  int fps;\n  float digital_gain;\n\n  CameraBuf buf;\n} CameraState;\n\ntypedef struct MultiCameraState {\n  CameraState road_cam;\n  CameraState driver_cam;\n\n  SubMaster *sm;\n  PubMaster *pm;\n} MultiCameraState;\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_mipi.cc",
    "content": "#include \"selfdrive/camerad/cameras/camera_mipi.h\"\n\n#include <assert.h>\n#include <string.h>\n#include <unistd.h>\n\n#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wundefined-inline\"\n#include <opencv2/core.hpp>\n#include <opencv2/opencv.hpp>\n#include <opencv2/highgui.hpp>\n#pragma clang diagnostic pop\n\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n\n#define FRAME_WIDTH  1164\n#define FRAME_HEIGHT 874\n\nextern ExitHandler do_exit;\n\nnamespace {\n\nCameraInfo cameras_supported[CAMERA_ID_MAX] = {\n  // road facing\n  [CAMERA_ID_IMX477] = {\n      .frame_width = FRAME_WIDTH,\n      .frame_height = FRAME_HEIGHT,\n      .frame_stride = FRAME_WIDTH*3,\n      .bayer = false,\n      .bayer_flip = false,\n  },\n};\nstd::string gstreamer_pipeline(int sensor_mode, int sensor_id, int flip_method, int display_width, int display_height) {\n    // sensor mode 1 = 1920 x 1080\n    return \"nvarguscamerasrc sensor_mode=\" + std::to_string(sensor_mode) +\n           \" sensor_id=\" + std::to_string(sensor_id) +\n           \" ! video/x-raw(memory:NVMM)\" +\n           \", format=(string)NV12\" +\n           \", framerate=(fraction)20/1\" +\n           \", width=(int)\" + std::to_string(display_width) +\n           \", height=(int)\" + std::to_string(display_height) +\n           \" ! nvvidconv flip-method=\" + std::to_string(flip_method) +\n           \" ! video/x-raw, format=BGRx\" +\n           \" ! videoconvert ! video/x-raw, format=(string)BGR\" +\n           \" ! appsink\";\n}\nvoid camera_open(CameraState *s, bool rear) {\n  // empty\n}\n\nvoid camera_close(CameraState *s) {\n  // empty\n}\n\nvoid camera_init(VisionIpcServer * v, CameraState *s, int camera_id, unsigned int fps, cl_device_id device_id, cl_context ctx, VisionStreamType rgb_type, VisionStreamType yuv_type) {\n  assert(camera_id < std::size(cameras_supported));\n  s->ci = cameras_supported[camera_id];\n  assert(s->ci.frame_width != 0);\n\n  s->camera_num = camera_id;\n  s->fps = fps;\n  s->buf.init(device_id, ctx, s, v, FRAME_BUF_COUNT, rgb_type, yuv_type);\n}\n\nvoid run_camera(CameraState *s, cv::VideoCapture &video_cap, float *ts) {\n  assert(video_cap.isOpened());\n\n  cv::Size size(s->ci.frame_width, s->ci.frame_height);\n  const cv::Mat transform = cv::Mat(3, 3, CV_32F, ts);\n  uint32_t frame_id = 0;\n  size_t buf_idx = 0;\n\n  while (!do_exit) {\n    cv::Mat frame_mat, transformed_mat;\n    video_cap >> frame_mat;\n    cv::warpPerspective(frame_mat, transformed_mat, transform, size, cv::INTER_LINEAR, cv::BORDER_CONSTANT, 0);\n\n    s->buf.camera_bufs_metadata[buf_idx] = {.frame_id = frame_id};\n\n    auto &buf = s->buf.camera_bufs[buf_idx];\n    int transformed_size = transformed_mat.total() * transformed_mat.elemSize();\n    CL_CHECK(clEnqueueWriteBuffer(buf.copy_q, buf.buf_cl, CL_TRUE, 0, transformed_size, transformed_mat.data, 0, NULL, NULL));\n\n    s->buf.queue(buf_idx);\n\n    ++frame_id;\n    buf_idx = (buf_idx + 1) % FRAME_BUF_COUNT;\n  }\n}\n\nstatic void road_camera_thread(CameraState *s) {\n  set_thread_name(\"mipi_road_camera_thread\");\n\n  std::string pipeline = gstreamer_pipeline(\n    1, // sensor mode\n    0, // sensor id\n    2, // flip method\n    864, // width\n    486); // height\n\n  cv::VideoCapture cap_road(pipeline, cv::CAP_GSTREAMER); // road\n  float ts[9] = {1.50330396, 0.0, -59.40969163,\n                  0.0, 1.50330396, 76.20704846,\n                  0.0, 0.0, 1.0};\n  run_camera(s, cap_road, ts);\n}\n\n}  // namespace\n\nvoid cameras_init(VisionIpcServer *v, MultiCameraState *s, cl_device_id device_id, cl_context ctx) {\n  camera_init(v, &s->road_cam, CAMERA_ID_IMX477, 20, device_id, ctx,\n              VISION_STREAM_RGB_BACK, VISION_STREAM_YUV_BACK);\n  s->pm = new PubMaster({\"roadCameraState\", \"thumbnail\"});\n}\n\nvoid camera_autoexposure(CameraState *s, float grey_frac) {}\n\nvoid cameras_open(MultiCameraState *s) {\n  camera_open(&s->road_cam, true);\n}\n\nvoid cameras_close(MultiCameraState *s) {\n  camera_close(&s->road_cam);\n  delete s->pm;\n}\n\nvoid process_road_camera(MultiCameraState *s, CameraState *c, int cnt) {\n  const CameraBuf *b = &c->buf;\n  MessageBuilder msg;\n  auto framed = msg.initEvent().initRoadCameraState();\n  fill_frame_data(framed, b->cur_frame_data);\n  framed.setImage(kj::arrayPtr((const uint8_t *)b->cur_yuv_buf->addr, b->cur_yuv_buf->len));\n  framed.setTransform(b->yuv_transform.v);\n  s->pm->send(\"roadCameraState\", msg);\n}\n\nvoid cameras_run(MultiCameraState *s) {\n  std::vector<std::thread> threads;\n  threads.push_back(start_process_thread(s, &s->road_cam, process_road_camera));\n\n  std::thread t_rear = std::thread(road_camera_thread, &s->road_cam);\n  set_thread_name(\"mipi_thread\");\n\n  t_rear.join();\n\n  for (auto &t : threads) t.join();\n\n  cameras_close(s);\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_mipi.h",
    "content": "#pragma once\n\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\n\n#include \"selfdrive/camerad/cameras/camera_common.h\"\n\n#define FRAME_BUF_COUNT 16\n\ntypedef struct CameraState {\n  CameraInfo ci;\n  int camera_num;\n  int fps;\n  float digital_gain;\n  CameraBuf buf;\n} CameraState;\n\n\ntypedef struct MultiCameraState {\n  CameraState road_cam;\n  CameraState driver_cam;\n\n  SubMaster *sm;\n  PubMaster *pm;\n} MultiCameraState;\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_qcom.cc",
    "content": "#include \"selfdrive/camerad/cameras/camera_qcom.h\"\n\n#include <fcntl.h>\n#include <poll.h>\n#include <sys/ioctl.h>\n#include <unistd.h>\n\n#include <algorithm>\n#include <atomic>\n#include <cassert>\n#include <cmath>\n#include <cstdio>\n\n#include <cutils/properties.h>\n#include <linux/media.h>\n\n#include \"selfdrive/camerad/cameras/sensor_i2c.h\"\n#include \"selfdrive/camerad/include/msm_cam_sensor.h\"\n#include \"selfdrive/camerad/include/msmb_camera.h\"\n#include \"selfdrive/camerad/include/msmb_isp.h\"\n#include \"selfdrive/camerad/include/msmb_ispif.h\"\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n\n// leeco actuator (DW9800W H-Bridge Driver IC)\n// from sniff\n//const uint16_t INFINITY_DAC = 364;\n\nextern ExitHandler do_exit;\n\nstatic int cam_ioctl(int fd, unsigned long int request, void *arg, const char *log_msg = nullptr) {\n  int err = HANDLE_EINTR(ioctl(fd, request, arg));\n  if (err != 0 && log_msg) {\n    LOG(util::string_format(\"%s: %d\", log_msg, err).c_str());\n  }\n  return err;\n}\n// global var for AE/AF ops\nstd::atomic<CameraExpInfo> road_cam_exp{{0}};\nstd::atomic<CameraExpInfo> driver_cam_exp{{0}};\n\nCameraInfo cameras_supported[CAMERA_ID_MAX] = {\n  [CAMERA_ID_IMX298] = {\n    .frame_width = 2328,\n    .frame_height = 1748,\n    .frame_stride = 2912,\n    .bayer = true,\n    .bayer_flip = 0,\n    .hdr = true\n  },\n  [CAMERA_ID_IMX179] = {\n    .frame_width = 3280,\n    .frame_height = 2464,\n    .frame_stride = 4104,\n    .bayer = true,\n    .bayer_flip = 0,\n    .hdr = false\n  },\n  [CAMERA_ID_S5K3P8SP] = {\n    .frame_width = 2304,\n    .frame_height = 1728,\n    .frame_stride = 2880,\n    .bayer = true,\n    .bayer_flip = 1,\n    .hdr = false\n  },\n  [CAMERA_ID_OV8865] = {\n    .frame_width = 1632,\n    .frame_height = 1224,\n    .frame_stride = 2040, // seems right\n    .bayer = true,\n    .bayer_flip = 3,\n    .hdr = false\n  },\n  // this exists to get the kernel to build for the LeEco in release\n  [CAMERA_ID_IMX298_FLIPPED] = {\n    .frame_width = 2328,\n    .frame_height = 1748,\n    .frame_stride = 2912,\n    .bayer = true,\n    .bayer_flip = 3,\n    .hdr = true\n  },\n  [CAMERA_ID_OV10640] = {\n    .frame_width = 1280,\n    .frame_height = 1080,\n    .frame_stride = 2040,\n    .bayer = true,\n    .bayer_flip = 0,\n    .hdr = true\n  },\n};\n\nstatic void camera_release_buffer(void* cookie, int buf_idx) {\n  CameraState *s = (CameraState *)cookie;\n  // printf(\"camera_release_buffer %d\\n\", buf_idx);\n  s->ss[0].qbuf_info[buf_idx].dirty_buf = 1;\n  HANDLE_EINTR(ioctl(s->isp_fd, VIDIOC_MSM_ISP_ENQUEUE_BUF, &s->ss[0].qbuf_info[buf_idx]));\n}\n\nint sensor_write_regs(CameraState *s, struct msm_camera_i2c_reg_array* arr, size_t size, msm_camera_i2c_data_type data_type) {\n  struct msm_camera_i2c_reg_setting out_settings = {\n    .reg_setting = arr,\n    .size = (uint16_t)size,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .data_type = data_type,\n    .delay = 0,\n  };\n  sensorb_cfg_data cfg_data = {.cfgtype = CFG_WRITE_I2C_ARRAY, .cfg.setting = &out_settings};\n  return HANDLE_EINTR(ioctl(s->sensor_fd, VIDIOC_MSM_SENSOR_CFG, &cfg_data));\n}\n\nstatic int imx298_apply_exposure(CameraState *s, int gain, int integ_lines, uint32_t frame_length) {\n  int analog_gain = std::min(gain, 448);\n  s->digital_gain = gain > 448 ? (512.0/(512-(gain))) / 8.0 : 1.0;\n  //printf(\"%5d/%5d %5d %f\\n\", s->cur_integ_lines, s->frame_length, analog_gain, s->digital_gain);\n\n  struct msm_camera_i2c_reg_array reg_array[] = {\n    // REG_HOLD\n    {0x104,0x1,0},\n    {0x3002,0x0,0}, // long autoexposure off\n\n    // FRM_LENGTH\n    {0x340, (uint16_t)(frame_length >> 8), 0}, {0x341, (uint16_t)(frame_length & 0xff), 0},\n    // INTEG_TIME aka coarse_int_time_addr aka shutter speed\n    {0x202, (uint16_t)(integ_lines >> 8), 0}, {0x203, (uint16_t)(integ_lines & 0xff),0},\n    // global_gain_addr\n    // if you assume 1x gain is 32, 448 is 14x gain, aka 2^14=16384\n    {0x204, (uint16_t)(analog_gain >> 8), 0}, {0x205, (uint16_t)(analog_gain & 0xff),0},\n\n    // digital gain for colors: gain_greenR, gain_red, gain_blue, gain_greenB\n    /*{0x20e, digital_gain_gr >> 8, 0}, {0x20f,digital_gain_gr & 0xFF,0},\n    {0x210, digital_gain_r >> 8, 0}, {0x211,digital_gain_r & 0xFF,0},\n    {0x212, digital_gain_b >> 8, 0}, {0x213,digital_gain_b & 0xFF,0},\n    {0x214, digital_gain_gb >> 8, 0}, {0x215,digital_gain_gb & 0xFF,0},*/\n\n    // REG_HOLD\n    {0x104,0x0,0},\n  };\n  return sensor_write_regs(s, reg_array, std::size(reg_array), MSM_CAMERA_I2C_BYTE_DATA);\n}\n\nstatic int ov8865_apply_exposure(CameraState *s, int gain, int integ_lines, uint32_t frame_length) {\n  //printf(\"driver camera: %d %d %d\\n\", gain, integ_lines, frame_length);\n  int coarse_gain_bitmap, fine_gain_bitmap;\n\n  // get bitmaps from iso\n  static const int gains[] = {0, 100, 200, 400, 800};\n  int i;\n  for (i = 1; i < std::size(gains); i++) {\n    if (gain >= gains[i - 1] && gain < gains[i])\n      break;\n  }\n  int coarse_gain = i - 1;\n  float fine_gain = (gain - gains[coarse_gain])/(float)(gains[coarse_gain+1]-gains[coarse_gain]);\n  coarse_gain_bitmap = (1 << coarse_gain) - 1;\n  fine_gain_bitmap = ((int)(16*fine_gain) << 3) + 128; // 7th is always 1, 0-2nd are always 0\n\n  integ_lines *= 16; // The exposure value in reg is in 16ths of a line\n\n  struct msm_camera_i2c_reg_array reg_array[] = {\n    //{0x104,0x1,0},\n\n    // FRM_LENGTH\n    {0x380e, (uint16_t)(frame_length >> 8), 0}, {0x380f, (uint16_t)(frame_length & 0xff), 0},\n    // AEC EXPO\n    {0x3500, (uint16_t)(integ_lines >> 16), 0}, {0x3501, (uint16_t)(integ_lines >> 8), 0}, {0x3502, (uint16_t)(integ_lines & 0xff),0},\n    // AEC MANUAL\n    {0x3503, 0x4, 0},\n    // AEC GAIN\n    {0x3508, (uint16_t)(coarse_gain_bitmap), 0}, {0x3509, (uint16_t)(fine_gain_bitmap), 0},\n\n    //{0x104,0x0,0},\n  };\n  return sensor_write_regs(s, reg_array, std::size(reg_array), MSM_CAMERA_I2C_BYTE_DATA);\n}\n\nstatic int imx179_s5k3p8sp_apply_exposure(CameraState *s, int gain, int integ_lines, uint32_t frame_length) {\n  //printf(\"driver camera: %d %d %d\\n\", gain, integ_lines, frame_length);\n  struct msm_camera_i2c_reg_array reg_array[] = {\n    {0x104,0x1,0},\n\n    // FRM_LENGTH\n    {0x340, (uint16_t)(frame_length >> 8), 0}, {0x341, (uint16_t)(frame_length & 0xff), 0},\n    // coarse_int_time\n    {0x202, (uint16_t)(integ_lines >> 8), 0}, {0x203, (uint16_t)(integ_lines & 0xff),0},\n    // global_gain\n    {0x204, (uint16_t)(gain >> 8), 0}, {0x205, (uint16_t)(gain & 0xff),0},\n\n    // REG_HOLD\n    {0x104,0x0,0},\n  };\n  return sensor_write_regs(s, reg_array, std::size(reg_array), MSM_CAMERA_I2C_BYTE_DATA);\n}\n\nstatic void camera_init(VisionIpcServer *v, CameraState *s, int camera_id, int camera_num,\n                        uint32_t pixel_clock, uint32_t line_length_pclk,\n                        uint32_t max_gain, uint32_t fps, cl_device_id device_id, cl_context ctx,\n                        VisionStreamType rgb_type, VisionStreamType yuv_type) {\n  s->camera_num = camera_num;\n  s->camera_id = camera_id;\n\n  assert(camera_id < std::size(cameras_supported));\n  s->ci = cameras_supported[camera_id];\n  assert(s->ci.frame_width != 0);\n\n  s->pixel_clock = pixel_clock;\n  s->max_gain = max_gain;\n  s->fps = fps;\n  s->frame_length = s->pixel_clock / line_length_pclk / s->fps;\n  s->self_recover = 0;\n\n  if (camera_id == CAMERA_ID_IMX298) {\n    s->apply_exposure = imx298_apply_exposure;\n  } else if (camera_id == CAMERA_ID_S5K3P8SP || camera_id == CAMERA_ID_IMX179) {\n    s->apply_exposure = imx179_s5k3p8sp_apply_exposure;\n  } else {\n    s->apply_exposure = ov8865_apply_exposure;\n  }\n  s->buf.init(device_id, ctx, s, v, FRAME_BUF_COUNT, rgb_type, yuv_type, camera_release_buffer);\n}\n\nvoid cameras_init(VisionIpcServer *v, MultiCameraState *s, cl_device_id device_id, cl_context ctx) {\n  char project_name[1024] = {0};\n  property_get(\"ro.boot.project_name\", project_name, \"\");\n\n  char product_name[1024] = {0};\n  property_get(\"ro.product.name\", product_name, \"\");\n\n  if (strlen(project_name) == 0) {\n    LOGD(\"LePro 3 op system detected\");\n    s->device = DEVICE_LP3;\n\n    // sensor is flipped in LP3\n    // IMAGE_ORIENT = 3\n    init_array_imx298[0].reg_data = 3;\n    cameras_supported[CAMERA_ID_IMX298].bayer_flip = 3;\n  } else if (strcmp(product_name, \"OnePlus3\") == 0 && strcmp(project_name, \"15811\") != 0) {\n    // no more OP3 support\n    s->device = DEVICE_OP3;\n    assert(false);\n  } else if (strcmp(product_name, \"OnePlus3\") == 0 && strcmp(project_name, \"15811\") == 0) {\n    // only OP3T support\n    s->device = DEVICE_OP3T;\n  } else {\n    assert(false);\n  }\n\n  // 0   = ISO 100\n  // 256 = ISO 200\n  // 384 = ISO 400\n  // 448 = ISO 800\n  // 480 = ISO 1600\n  // 496 = ISO 3200\n  // 504 = ISO 6400, 8x digital gain\n  // 508 = ISO 12800, 16x digital gain\n  // 510 = ISO 25600, 32x digital gain\n\n  camera_init(v, &s->road_cam, CAMERA_ID_IMX298, 0,\n              /*pixel_clock=*/600000000, /*line_length_pclk=*/5536,\n              /*max_gain=*/510,  //0 (ISO 100)- 448 (ISO 800, max analog gain) - 511 (super noisy)\n#ifdef HIGH_FPS\n              /*fps*/ 60,\n#else\n              /*fps*/ 20,\n#endif\n              device_id, ctx,\n              VISION_STREAM_RGB_BACK, VISION_STREAM_YUV_BACK);\n  s->road_cam.apply_exposure = imx298_apply_exposure;\n\n  if (s->device == DEVICE_OP3T) {\n    camera_init(v, &s->driver_cam, CAMERA_ID_S5K3P8SP, 1,\n                /*pixel_clock=*/560000000, /*line_length_pclk=*/5120,\n                /*max_gain=*/510, 10, device_id, ctx,\n                VISION_STREAM_RGB_FRONT, VISION_STREAM_YUV_FRONT);\n    s->driver_cam.apply_exposure = imx179_s5k3p8sp_apply_exposure;\n  } else if (s->device == DEVICE_LP3) {\n    camera_init(v, &s->driver_cam, CAMERA_ID_OV8865, 1,\n                /*pixel_clock=*/72000000, /*line_length_pclk=*/1602,\n                /*max_gain=*/510, 10, device_id, ctx,\n                VISION_STREAM_RGB_FRONT, VISION_STREAM_YUV_FRONT);\n    s->driver_cam.apply_exposure = ov8865_apply_exposure;\n  } else {\n    camera_init(v, &s->driver_cam, CAMERA_ID_IMX179, 1,\n                /*pixel_clock=*/251200000, /*line_length_pclk=*/3440,\n                /*max_gain=*/224, 20, device_id, ctx,\n                VISION_STREAM_RGB_FRONT, VISION_STREAM_YUV_FRONT);\n    s->driver_cam.apply_exposure = imx179_s5k3p8sp_apply_exposure;\n  }\n\n  s->road_cam.device = s->device;\n  s->driver_cam.device = s->device;\n\n  s->sm = new SubMaster({\"driverState\"});\n  s->pm = new PubMaster({\"roadCameraState\", \"driverCameraState\", \"thumbnail\"});\n\n  for (int i = 0; i < FRAME_BUF_COUNT; i++) {\n    // TODO: make lengths correct\n    s->focus_bufs[i].allocate(0xb80);\n    s->stats_bufs[i].allocate(0xb80);\n  }\n  std::fill_n(s->lapres, std::size(s->lapres), 16160);\n  s->lap_conv = new LapConv(device_id, ctx, s->road_cam.buf.rgb_width, s->road_cam.buf.rgb_height, 3);\n}\n\nstatic void set_exposure(CameraState *s, float exposure_frac, float gain_frac) {\n  int err = 0;\n  uint32_t gain = s->cur_gain;\n  uint32_t integ_lines = s->cur_integ_lines;\n\n  if (exposure_frac >= 0) {\n    exposure_frac = std::clamp(exposure_frac, 2.0f / s->frame_length, 1.0f);\n    integ_lines = s->frame_length * exposure_frac;\n\n    // See page 79 of the datasheet, this is the max allowed (-1 for phase adjust)\n    integ_lines = std::min(integ_lines, s->frame_length - 11);\n  }\n\n  if (gain_frac >= 0) {\n    // ISO200 is minimum gain\n    gain_frac = std::clamp(gain_frac, 1.0f/64, 1.0f);\n\n    // linearize gain response\n    // TODO: will be wrong for driver camera\n    // 0.125 -> 448\n    // 0.25  -> 480\n    // 0.5   -> 496\n    // 1.0   -> 504\n    // 512 - 512/(128*gain_frac)\n    gain = (s->max_gain/510) * (512 - 512/(256*gain_frac));\n  }\n\n  if (gain != s->cur_gain || integ_lines != s->cur_integ_lines) {\n    if (s->apply_exposure == ov8865_apply_exposure) {\n      gain = 800 * gain_frac; // ISO\n      err = s->apply_exposure(s, gain, integ_lines, s->frame_length);\n    } else if (s->apply_exposure) {\n      err = s->apply_exposure(s, gain, integ_lines, s->frame_length);\n    }\n    if (err == 0) {\n      std::lock_guard lk(s->frame_info_lock);\n      s->cur_gain = gain;\n      s->cur_integ_lines = integ_lines;\n    } else {\n      LOGE(\"camera %d apply_exposure err: %d\", s->camera_num, err);\n    }\n  }\n\n  if (err == 0) {\n    s->cur_exposure_frac = exposure_frac;\n    std::lock_guard lk(s->frame_info_lock);\n    s->cur_gain_frac = gain_frac;\n  }\n\n  //LOGD(\"set exposure: %f %f - %d\", exposure_frac, gain_frac, err);\n}\n\nstatic void do_autoexposure(CameraState *s, float grey_frac) {\n  const float target_grey = 0.3;\n\n  s->frame_info_lock.lock();\n  s->measured_grey_fraction = grey_frac;\n  s->target_grey_fraction = target_grey;\n  s->frame_info_lock.unlock();\n\n  if (s->apply_exposure == ov8865_apply_exposure) {\n    // gain limits downstream\n    const float gain_frac_min = 0.015625;\n    const float gain_frac_max = 1.0;\n    // exposure time limits\n    const uint32_t exposure_time_min = 16;\n    const uint32_t exposure_time_max = s->frame_length - 11; // copied from set_exposure()\n\n    float cur_gain_frac = s->cur_gain_frac;\n    float exposure_factor = pow(1.05, (target_grey - grey_frac) / 0.05);\n    if (cur_gain_frac > 0.125 && exposure_factor < 1) {\n      cur_gain_frac *= exposure_factor;\n    } else if (s->cur_integ_lines * exposure_factor <= exposure_time_max && s->cur_integ_lines * exposure_factor >= exposure_time_min) { // adjust exposure time first\n      s->cur_exposure_frac *= exposure_factor;\n    } else if (cur_gain_frac * exposure_factor <= gain_frac_max && cur_gain_frac * exposure_factor >= gain_frac_min) {\n      cur_gain_frac *= exposure_factor;\n    }\n    s->frame_info_lock.lock();\n    s->cur_gain_frac = cur_gain_frac;\n    s->frame_info_lock.unlock();\n\n    set_exposure(s, s->cur_exposure_frac, cur_gain_frac);\n  } else { // keep the old for others\n    float new_exposure = s->cur_exposure_frac;\n    new_exposure *= pow(1.05, (target_grey - grey_frac) / 0.05 );\n    //LOGD(\"diff %f: %f to %f\", target_grey - grey_frac, s->cur_exposure_frac, new_exposure);\n\n    float new_gain = s->cur_gain_frac;\n    if (new_exposure < 0.10) {\n      new_gain *= 0.95;\n    } else if (new_exposure > 0.40) {\n      new_gain *= 1.05;\n    }\n\n    set_exposure(s, new_exposure, new_gain);\n  }\n}\n\nstatic uint8_t* get_eeprom(int eeprom_fd, size_t *out_len) {\n  msm_eeprom_cfg_data cfg = {.cfgtype = CFG_EEPROM_GET_CAL_DATA};\n  int err = cam_ioctl(eeprom_fd, VIDIOC_MSM_EEPROM_CFG, &cfg, \"get_eeprom begin\");\n  assert(err >= 0);\n\n  uint32_t num_bytes = cfg.cfg.get_data.num_bytes;\n  assert(num_bytes > 100);\n\n  uint8_t* buffer = (uint8_t*)malloc(num_bytes);\n  assert(buffer);\n  memset(buffer, 0, num_bytes);\n\n  cfg.cfgtype = CFG_EEPROM_READ_CAL_DATA;\n  cfg.cfg.read_data.num_bytes = num_bytes;\n  cfg.cfg.read_data.dbuffer = buffer;\n  err = cam_ioctl(eeprom_fd, VIDIOC_MSM_EEPROM_CFG, &cfg, \"get_eeprom end\");\n  assert(err >= 0);\n\n  *out_len = num_bytes;\n  return buffer;\n}\n\nstatic void imx298_ois_calibration(int ois_fd, uint8_t* eeprom) {\n  const int ois_registers[][2] = {\n    // == SET_FADJ_PARAM() == (factory adjustment)\n\n    // Set Hall Current DAC\n    {0x8230, *(uint16_t*)(eeprom+0x102)}, //_P_30_ADC_CH0 (CURDAT)\n\n    // Set Hall     PreAmp Offset\n    {0x8231, *(uint16_t*)(eeprom+0x104)}, //_P_31_ADC_CH1 (HALOFS_X)\n    {0x8232, *(uint16_t*)(eeprom+0x106)}, //_P_32_ADC_CH2 (HALOFS_Y)\n\n    // Set Hall-X/Y PostAmp Offset\n    {0x841e, *(uint16_t*)(eeprom+0x108)}, //_M_X_H_ofs\n    {0x849e, *(uint16_t*)(eeprom+0x10a)}, //_M_Y_H_ofs\n\n    // Set Residual Offset\n    {0x8239, *(uint16_t*)(eeprom+0x10c)}, //_P_39_Ch3_VAL_1 (PSTXOF)\n    {0x823b, *(uint16_t*)(eeprom+0x10e)}, //_P_3B_Ch3_VAL_3 (PSTYOF)\n\n    // DIGITAL GYRO OFFSET\n    {0x8406, *(uint16_t*)(eeprom+0x110)}, //_M_Kgx00\n    {0x8486, *(uint16_t*)(eeprom+0x112)}, //_M_Kgy00\n    {0x846a, *(uint16_t*)(eeprom+0x120)}, //_M_TMP_X_\n    {0x846b, *(uint16_t*)(eeprom+0x122)}, //_M_TMP_Y_\n\n    // HALLSENSE\n    // Set Hall Gain\n    {0x8446, *(uint16_t*)(eeprom+0x114)}, //_M_KgxHG\n    {0x84c6, *(uint16_t*)(eeprom+0x116)}, //_M_KgyHG\n    // Set Cross Talk Canceller\n    {0x8470, *(uint16_t*)(eeprom+0x124)}, //_M_KgxH0\n    {0x8472, *(uint16_t*)(eeprom+0x126)}, //_M_KgyH0\n\n    // LOOPGAIN\n    {0x840f, *(uint16_t*)(eeprom+0x118)}, //_M_KgxG\n    {0x848f, *(uint16_t*)(eeprom+0x11a)}, //_M_KgyG\n\n    // Position Servo ON ( OIS OFF )\n    {0x847f, 0x0c0c}, //_M_EQCTL\n  };\n\n  struct msm_camera_i2c_seq_reg_array ois_reg_settings[std::size(ois_registers)] = {{0}};\n  for (int i=0; i<std::size(ois_registers); i++) {\n    ois_reg_settings[i].reg_addr = ois_registers[i][0];\n    ois_reg_settings[i].reg_data[0] = ois_registers[i][1] & 0xff;\n    ois_reg_settings[i].reg_data[1] = (ois_registers[i][1] >> 8) & 0xff;\n    ois_reg_settings[i].reg_data_size = 2;\n  }\n  struct msm_camera_i2c_seq_reg_setting ois_reg_setting = {\n    .reg_setting = &ois_reg_settings[0],\n    .size = std::size(ois_reg_settings),\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .delay = 0,\n  };\n  msm_ois_cfg_data cfg = {.cfgtype = CFG_OIS_I2C_WRITE_SEQ_TABLE, .cfg.settings = &ois_reg_setting};\n  cam_ioctl(ois_fd, VIDIOC_MSM_OIS_CFG, &cfg, \"ois reg calibration\");\n}\n\nstatic void sensors_init(MultiCameraState *s) {\n  int err;\n\n  unique_fd sensorinit_fd;\n  if (s->device == DEVICE_LP3) {\n    sensorinit_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev11\", O_RDWR | O_NONBLOCK));\n  } else {\n    sensorinit_fd = (open(\"/dev/v4l-subdev12\", O_RDWR | O_NONBLOCK));\n  }\n  assert(sensorinit_fd >= 0);\n\n  // init road camera sensor\n\n  struct msm_camera_sensor_slave_info slave_info = {0};\n  if (s->device == DEVICE_LP3) {\n    slave_info = (struct msm_camera_sensor_slave_info){\n      .sensor_name = \"imx298\",\n      .eeprom_name = \"sony_imx298\",\n      .actuator_name = \"dw9800w\",\n      .ois_name = \"\",\n      .flash_name = \"pmic\",\n      .camera_id = CAMERA_0,\n      .slave_addr = 32,\n      .i2c_freq_mode = I2C_FAST_MODE,\n      .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n      .sensor_id_info = {.sensor_id_reg_addr = 22, .sensor_id = 664, .module_id = 9, .vcm_id = 6},\n      .power_setting_array = {\n        .power_setting_a = {\n          {.seq_type = SENSOR_GPIO, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 2},\n          {.seq_type = SENSOR_GPIO, .seq_val = 5, .config_val = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 3, .delay = 1},\n          {.seq_type = SENSOR_CLK, .config_val = 24000000, .delay = 1},\n          {.seq_type = SENSOR_GPIO, .config_val = 2, .delay = 10},\n        },\n        .size = 7,\n        .power_down_setting_a = {\n          {.seq_type = SENSOR_CLK, .delay = 1},\n          {.seq_type = SENSOR_GPIO, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_GPIO, .seq_val = 5},\n          {.seq_type = SENSOR_VREG, .seq_val = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 3, .delay = 1},\n        },\n        .size_down = 6,\n      },\n      .is_init_params_valid = 0,\n      .sensor_init_params = {.modes_supported = 1, .position = BACK_CAMERA_B, .sensor_mount_angle = 90},\n      .output_format = MSM_SENSOR_BAYER,\n    };\n  } else {\n    slave_info = (struct msm_camera_sensor_slave_info){\n      .sensor_name = \"imx298\",\n      .eeprom_name = \"sony_imx298\",\n      .actuator_name = \"rohm_bu63165gwl\",\n      .ois_name = \"rohm_bu63165gwl\",\n      .camera_id = CAMERA_0,\n      .slave_addr = 52,\n      .i2c_freq_mode = I2C_CUSTOM_MODE,\n      .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n      .sensor_id_info = {.sensor_id_reg_addr = 22, .sensor_id = 664},\n      .power_setting_array = {\n        .power_setting_a = {\n          {.seq_type = SENSOR_GPIO, .delay = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 2, .delay = 2},\n          {.seq_type = SENSOR_VREG, .delay = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 1, .delay = 2},\n          {.seq_type = SENSOR_GPIO, .seq_val = 6, .config_val = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 3, .delay = 5},\n          {.seq_type = SENSOR_VREG, .seq_val = 4, .delay = 5},\n          {.seq_type = SENSOR_CLK, .config_val = 24000000, .delay = 2},\n          {.seq_type = SENSOR_GPIO, .config_val = 2, .delay = 2},\n        },\n        .size = 9,\n        .power_down_setting_a = {\n          {.seq_type = SENSOR_GPIO, .delay = 10},\n          {.seq_type = SENSOR_CLK, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 4},\n          {.seq_type = SENSOR_VREG, .seq_val = 3, .delay = 1},\n          {.seq_type = SENSOR_GPIO, .seq_val = 6},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_VREG},\n          {.seq_type = SENSOR_VREG, .seq_val = 2},\n        },\n        .size_down = 8,\n      },\n      .is_init_params_valid = 0,\n      .sensor_init_params = {.modes_supported = 1, .position = BACK_CAMERA_B, .sensor_mount_angle = 360},\n      .output_format = MSM_SENSOR_BAYER,\n    };\n  }\n  slave_info.power_setting_array.power_setting =\n    (struct msm_sensor_power_setting *)&slave_info.power_setting_array.power_setting_a[0];\n  slave_info.power_setting_array.power_down_setting =\n    (struct msm_sensor_power_setting *)&slave_info.power_setting_array.power_down_setting_a[0];\n  sensor_init_cfg_data sensor_init_cfg = {.cfgtype = CFG_SINIT_PROBE, .cfg.setting = &slave_info};\n  err = cam_ioctl(sensorinit_fd, VIDIOC_MSM_SENSOR_INIT_CFG, &sensor_init_cfg, \"sensor init cfg (road)\");\n  assert(err >= 0);\n\n  struct msm_camera_sensor_slave_info slave_info2 = {0};\n  if (s->device == DEVICE_LP3) {\n    slave_info2 = (struct msm_camera_sensor_slave_info){\n      .sensor_name = \"ov8865_sunny\",\n      .eeprom_name = \"ov8865_plus\",\n      .actuator_name = \"\",\n      .ois_name = \"\",\n      .flash_name = \"\",\n      .camera_id = CAMERA_2,\n      .slave_addr = 108,\n      .i2c_freq_mode = I2C_FAST_MODE,\n      .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n      .sensor_id_info = {.sensor_id_reg_addr = 12299, .sensor_id = 34917, .module_id = 2},\n      .power_setting_array = {\n        .power_setting_a = {\n          {.seq_type = SENSOR_GPIO, .delay = 5},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 2},\n          {.seq_type = SENSOR_VREG},\n          {.seq_type = SENSOR_CLK, .config_val = 24000000, .delay = 1},\n          {.seq_type = SENSOR_GPIO, .config_val = 2, .delay = 1},\n        },\n        .size = 6,\n        .power_down_setting_a = {\n          {.seq_type = SENSOR_GPIO, .delay = 5},\n          {.seq_type = SENSOR_CLK, .delay = 1},\n          {.seq_type = SENSOR_VREG},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 2, .delay = 1},\n        },\n        .size_down = 5,\n      },\n      .is_init_params_valid = 0,\n      .sensor_init_params = {.modes_supported = 1, .position = FRONT_CAMERA_B, .sensor_mount_angle = 270},\n      .output_format = MSM_SENSOR_BAYER,\n    };\n  } else if (s->driver_cam.camera_id == CAMERA_ID_S5K3P8SP) {\n    // init driver camera\n    slave_info2 = (struct msm_camera_sensor_slave_info){\n      .sensor_name = \"s5k3p8sp\",\n      .eeprom_name = \"s5k3p8sp_m24c64s\",\n      .actuator_name = \"\",\n      .ois_name = \"\",\n      .camera_id = CAMERA_1,\n      .slave_addr = 32,\n      .i2c_freq_mode = I2C_FAST_MODE,\n      .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n      .sensor_id_info = {.sensor_id = 12552},\n      .power_setting_array = {\n        .power_setting_a = {\n          {.seq_type = SENSOR_GPIO, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 2, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 1, .delay = 1},\n          {.seq_type = SENSOR_VREG, .delay = 1},\n          {.seq_type = SENSOR_CLK, .config_val = 24000000, .delay = 1},\n          {.seq_type = SENSOR_GPIO, .config_val = 2, .delay = 1},\n        },\n        .size = 6,\n        .power_down_setting_a = {\n          {.seq_type = SENSOR_CLK, .delay = 1},\n          {.seq_type = SENSOR_GPIO, .delay = 1},\n          {.seq_type = SENSOR_VREG, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 1, .delay = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 2, .delay = 1},\n        },\n        .size_down = 5,\n      },\n      .is_init_params_valid = 0,\n      .sensor_init_params = {.modes_supported = 1, .position = FRONT_CAMERA_B, .sensor_mount_angle = 270},\n      .output_format = MSM_SENSOR_BAYER,\n    };\n  } else {\n    // init driver camera\n    slave_info2 = (struct msm_camera_sensor_slave_info){\n      .sensor_name = \"imx179\",\n      .eeprom_name = \"sony_imx179\",\n      .actuator_name = \"\",\n      .ois_name = \"\",\n      .camera_id = CAMERA_1,\n      .slave_addr = 32,\n      .i2c_freq_mode = I2C_FAST_MODE,\n      .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n      .sensor_id_info = {.sensor_id_reg_addr = 2, .sensor_id = 377, .sensor_id_mask = 4095},\n      .power_setting_array = {\n        .power_setting_a = {\n          {.seq_type = SENSOR_VREG, .seq_val = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_VREG},\n          {.seq_type = SENSOR_GPIO, .config_val = 2},\n          {.seq_type = SENSOR_CLK, .config_val = 24000000},\n        },\n        .size = 5,\n        .power_down_setting_a = {\n          {.seq_type = SENSOR_CLK},\n          {.seq_type = SENSOR_GPIO, .delay = 1},\n          {.seq_type = SENSOR_VREG, .delay = 2},\n          {.seq_type = SENSOR_VREG, .seq_val = 1},\n          {.seq_type = SENSOR_VREG, .seq_val = 2},\n        },\n        .size_down = 5,\n      },\n      .is_init_params_valid = 0,\n      .sensor_init_params = {.modes_supported = 1, .position = FRONT_CAMERA_B, .sensor_mount_angle = 270},\n      .output_format = MSM_SENSOR_BAYER,\n    };\n  }\n  slave_info2.power_setting_array.power_setting =\n    (struct msm_sensor_power_setting *)&slave_info2.power_setting_array.power_setting_a[0];\n  slave_info2.power_setting_array.power_down_setting =\n    (struct msm_sensor_power_setting *)&slave_info2.power_setting_array.power_down_setting_a[0];\n  sensor_init_cfg.cfgtype = CFG_SINIT_PROBE;\n  sensor_init_cfg.cfg.setting = &slave_info2;\n  err = cam_ioctl(sensorinit_fd, VIDIOC_MSM_SENSOR_INIT_CFG, &sensor_init_cfg, \"sensor init cfg (driver)\");\n  assert(err >= 0);\n}\n\nstatic void camera_open(CameraState *s, bool is_road_cam) {\n  int err;\n\n  struct csid_cfg_data csid_cfg_data = {};\n  struct v4l2_event_subscription sub = {};\n\n  struct msm_actuator_cfg_data actuator_cfg_data = {};\n  struct msm_ois_cfg_data ois_cfg_data = {};\n\n  // open devices\n  const char *sensor_dev;\n  if (is_road_cam) {\n    s->csid_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev3\", O_RDWR | O_NONBLOCK));\n    assert(s->csid_fd >= 0);\n    s->csiphy_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev0\", O_RDWR | O_NONBLOCK));\n    assert(s->csiphy_fd >= 0);\n    if (s->device == DEVICE_LP3) {\n      sensor_dev = \"/dev/v4l-subdev17\";\n    } else {\n      sensor_dev = \"/dev/v4l-subdev18\";\n    }\n    if (s->device == DEVICE_LP3) {\n      s->isp_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev13\", O_RDWR | O_NONBLOCK));\n    } else {\n      s->isp_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev14\", O_RDWR | O_NONBLOCK));\n    }\n    assert(s->isp_fd >= 0);\n    s->eeprom_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev8\", O_RDWR | O_NONBLOCK));\n    assert(s->eeprom_fd >= 0);\n\n    s->actuator_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev7\", O_RDWR | O_NONBLOCK));\n    assert(s->actuator_fd >= 0);\n\n    if (s->device != DEVICE_LP3) {\n      s->ois_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev10\", O_RDWR | O_NONBLOCK));\n      assert(s->ois_fd >= 0);\n    }\n  } else {\n    s->csid_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev5\", O_RDWR | O_NONBLOCK));\n    assert(s->csid_fd >= 0);\n    s->csiphy_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev2\", O_RDWR | O_NONBLOCK));\n    assert(s->csiphy_fd >= 0);\n    if (s->device == DEVICE_LP3) {\n      sensor_dev = \"/dev/v4l-subdev18\";\n    } else {\n      sensor_dev = \"/dev/v4l-subdev19\";\n    }\n    if (s->device == DEVICE_LP3) {\n      s->isp_fd = open(\"/dev/v4l-subdev14\", O_RDWR | O_NONBLOCK);\n    } else {\n      s->isp_fd = open(\"/dev/v4l-subdev15\", O_RDWR | O_NONBLOCK);\n    }\n    assert(s->isp_fd >= 0);\n    s->eeprom_fd = open(\"/dev/v4l-subdev9\", O_RDWR | O_NONBLOCK);\n    assert(s->eeprom_fd >= 0);\n  }\n\n  // wait for sensor device\n  // on first startup, these devices aren't present yet\n  for (int i = 0; i < 10; i++) {\n    s->sensor_fd = HANDLE_EINTR(open(sensor_dev, O_RDWR | O_NONBLOCK));\n    if (s->sensor_fd >= 0) break;\n    LOGW(\"waiting for sensors...\");\n    util::sleep_for(1000); // sleep one second\n  }\n  assert(s->sensor_fd >= 0);\n\n  // *** SHUTDOWN ALL ***\n\n  // CSIPHY: release csiphy\n  struct msm_camera_csi_lane_params csi_lane_params = {0};\n  csi_lane_params.csi_lane_mask = 0x1f;\n  csiphy_cfg_data csiphy_cfg_data = { .cfg.csi_lane_params = &csi_lane_params, .cfgtype = CSIPHY_RELEASE};\n  err = cam_ioctl(s->csiphy_fd, VIDIOC_MSM_CSIPHY_IO_CFG, &csiphy_cfg_data, \"release csiphy\");\n\n  // CSID: release csid\n  csid_cfg_data.cfgtype = CSID_RELEASE;\n  cam_ioctl(s->csid_fd, VIDIOC_MSM_CSID_IO_CFG, &csid_cfg_data, \"release csid\");\n\n  // SENSOR: send power down\n  struct sensorb_cfg_data sensorb_cfg_data = {.cfgtype = CFG_POWER_DOWN};\n  cam_ioctl(s->sensor_fd, VIDIOC_MSM_SENSOR_CFG, &sensorb_cfg_data, \"sensor power down\");\n\n  // actuator powerdown\n  actuator_cfg_data.cfgtype = CFG_ACTUATOR_POWERDOWN;\n  cam_ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data, \"actuator powerdown\");\n\n  if (is_road_cam && s->device != DEVICE_LP3) {\n    // ois powerdown\n    ois_cfg_data.cfgtype = CFG_OIS_POWERDOWN;\n    err = cam_ioctl(s->ois_fd, VIDIOC_MSM_OIS_CFG, &ois_cfg_data, \"ois powerdown\");\n  }\n\n  // reset isp\n  // struct msm_vfe_axi_halt_cmd halt_cmd = {\n  //   .stop_camif = 1,\n  //   .overflow_detected = 1,\n  //   .blocking_halt = 1,\n  // };\n  // err = ioctl(s->isp_fd, VIDIOC_MSM_ISP_AXI_HALT, &halt_cmd);\n  // printf(\"axi halt: %d\\n\", err);\n\n  // struct msm_vfe_axi_reset_cmd reset_cmd = {\n  //   .blocking = 1,\n  //   .frame_id = 1,\n  // };\n  // err = ioctl(s->isp_fd, VIDIOC_MSM_ISP_AXI_RESET, &reset_cmd);\n  // printf(\"axi reset: %d\\n\", err);\n\n  // struct msm_vfe_axi_restart_cmd restart_cmd = {\n  //   .enable_camif = 1,\n  // };\n  // err = ioctl(s->isp_fd, VIDIOC_MSM_ISP_AXI_RESTART, &restart_cmd);\n  // printf(\"axi restart: %d\\n\", err);\n\n  // **** GO GO GO ****\n  LOG(\"******************** GO GO GO ************************\");\n\n  s->eeprom = get_eeprom(s->eeprom_fd, &s->eeprom_size);\n\n  // CSID: init csid\n  csid_cfg_data.cfgtype = CSID_INIT;\n  cam_ioctl(s->csid_fd, VIDIOC_MSM_CSID_IO_CFG, &csid_cfg_data, \"init csid\");\n\n  // CSIPHY: init csiphy\n  csiphy_cfg_data = {.cfgtype = CSIPHY_INIT};\n  cam_ioctl(s->csiphy_fd, VIDIOC_MSM_CSIPHY_IO_CFG, &csiphy_cfg_data, \"init csiphy\");\n\n  // SENSOR: stop stream\n  struct msm_camera_i2c_reg_setting stop_settings = {\n    .reg_setting = stop_reg_array,\n    .size = std::size(stop_reg_array),\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .data_type = MSM_CAMERA_I2C_BYTE_DATA,\n    .delay = 0\n  };\n  sensorb_cfg_data.cfgtype = CFG_SET_STOP_STREAM_SETTING;\n  sensorb_cfg_data.cfg.setting = &stop_settings;\n  cam_ioctl(s->sensor_fd, VIDIOC_MSM_SENSOR_CFG, &sensorb_cfg_data, \"stop stream\");\n\n  // SENSOR: send power up\n  sensorb_cfg_data = {.cfgtype = CFG_POWER_UP};\n  cam_ioctl(s->sensor_fd, VIDIOC_MSM_SENSOR_CFG, &sensorb_cfg_data, \"sensor power up\");\n\n  // **** configure the sensor ****\n\n  // SENSOR: send i2c configuration\n  if (s->camera_id == CAMERA_ID_IMX298) {\n    err = sensor_write_regs(s, init_array_imx298, std::size(init_array_imx298), MSM_CAMERA_I2C_BYTE_DATA);\n  } else if  (s->camera_id == CAMERA_ID_S5K3P8SP) {\n    err = sensor_write_regs(s, init_array_s5k3p8sp, std::size(init_array_s5k3p8sp), MSM_CAMERA_I2C_WORD_DATA);\n  } else if (s->camera_id == CAMERA_ID_IMX179) {\n    err = sensor_write_regs(s, init_array_imx179, std::size(init_array_imx179), MSM_CAMERA_I2C_BYTE_DATA);\n  } else if (s->camera_id == CAMERA_ID_OV8865) {\n    err = sensor_write_regs(s, init_array_ov8865, std::size(init_array_ov8865), MSM_CAMERA_I2C_BYTE_DATA);\n  } else {\n    assert(false);\n  }\n  LOG(\"sensor init i2c: %d\", err);\n\n  if (is_road_cam) {\n    // init the actuator\n    actuator_cfg_data.cfgtype = CFG_ACTUATOR_POWERUP;\n    cam_ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data, \"actuator powerup\");\n\n    actuator_cfg_data.cfgtype = CFG_ACTUATOR_INIT;\n    cam_ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data, \"actuator init\");\n\n    // no OIS in LP3\n    if (s->device != DEVICE_LP3) {\n      // see sony_imx298_eeprom_format_afdata in libmmcamera_sony_imx298_eeprom.so\n      const float far_margin = -0.28;\n      uint16_t macro_dac = *(uint16_t*)(s->eeprom + 0x24);\n      s->infinity_dac = *(uint16_t*)(s->eeprom + 0x26);\n      LOG(\"macro_dac: %d infinity_dac: %d\", macro_dac, s->infinity_dac);\n\n      int dac_range = macro_dac - s->infinity_dac;\n      s->infinity_dac += far_margin * dac_range;\n\n      LOG(\" -> macro_dac: %d infinity_dac: %d\", macro_dac, s->infinity_dac);\n\n      struct msm_actuator_reg_params_t actuator_reg_params[] = {\n        {.reg_write_type = MSM_ACTUATOR_WRITE_DAC, .reg_addr = 240, .data_type = 10, .addr_type = 4},\n        {.reg_write_type = MSM_ACTUATOR_WRITE_DAC, .reg_addr = 241, .data_type = 10, .addr_type = 4},\n        {.reg_write_type = MSM_ACTUATOR_WRITE_DAC, .reg_addr = 242, .data_type = 10, .addr_type = 4},\n        {.reg_write_type = MSM_ACTUATOR_WRITE_DAC, .reg_addr = 243, .data_type = 10, .addr_type = 4},\n      };\n\n      //...\n      struct reg_settings_t actuator_init_settings[1] = {0};\n\n      struct region_params_t region_params[] = {\n        {.step_bound = {512, 0,}, .code_per_step = 118, .qvalue = 128}\n      };\n\n      actuator_cfg_data.cfgtype = CFG_SET_ACTUATOR_INFO;\n      actuator_cfg_data.cfg.set_info = (struct msm_actuator_set_info_t){\n        .actuator_params = {\n          .act_type = ACTUATOR_VCM,\n          .reg_tbl_size = 4,\n          .data_size = 10,\n          .init_setting_size = 0,\n          .i2c_freq_mode = I2C_CUSTOM_MODE,\n          .i2c_addr = 28,\n          .i2c_addr_type = MSM_ACTUATOR_BYTE_ADDR,\n          .i2c_data_type = MSM_ACTUATOR_BYTE_DATA,\n          .reg_tbl_params = &actuator_reg_params[0],\n          .init_settings = &actuator_init_settings[0],\n          .park_lens = {\n            .damping_step = 1023,\n            .damping_delay = 15000,\n            .hw_params = 58404,\n            .max_step = 20,\n          }\n        },\n        .af_tuning_params =   {\n          .initial_code = (int16_t)s->infinity_dac,\n          .pwd_step = 0,\n          .region_size = 1,\n          .total_steps = 512,\n          .region_params = &region_params[0],\n        },\n      };\n      err = cam_ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data, \"actuator set info\");\n\n      // power up ois\n      ois_cfg_data.cfgtype = CFG_OIS_POWERUP;\n      err = cam_ioctl(s->ois_fd, VIDIOC_MSM_OIS_CFG, &ois_cfg_data, \"ois powerup\");\n\n      ois_cfg_data.cfgtype = CFG_OIS_INIT;\n      err = cam_ioctl(s->ois_fd, VIDIOC_MSM_OIS_CFG, &ois_cfg_data, \"ois init\");\n\n      ois_cfg_data.cfgtype = CFG_OIS_CONTROL;\n      ois_cfg_data.cfg.set_info.ois_params = (struct msm_ois_params_t){\n        // .data_size = 26312,\n        .setting_size = 120,\n        .i2c_addr = 28,\n        .i2c_freq_mode = I2C_CUSTOM_MODE,\n        // .i2c_addr_type = wtf\n        // .i2c_data_type = wtf\n        .settings = &ois_init_settings[0],\n      };\n      cam_ioctl(s->ois_fd, VIDIOC_MSM_OIS_CFG, &ois_cfg_data, \"ois init settings\");\n    } else {\n      // leeco actuator (DW9800W H-Bridge Driver IC)\n      // from sniff\n      s->infinity_dac = 364;\n\n      struct msm_actuator_reg_params_t actuator_reg_params[] = {\n        {\n          .reg_write_type = MSM_ACTUATOR_WRITE_DAC,\n          // MSB here at address 3\n          .reg_addr = 3,\n          .data_type = 9,\n          .addr_type = 4,\n        },\n      };\n\n      struct reg_settings_t actuator_init_settings[] = {\n        { .reg_addr=2, .addr_type=MSM_ACTUATOR_BYTE_ADDR, .reg_data=1, .data_type = MSM_ACTUATOR_BYTE_DATA, .i2c_operation = MSM_ACT_WRITE, .delay = 0 },   // PD = power down\n        { .reg_addr=2, .addr_type=MSM_ACTUATOR_BYTE_ADDR, .reg_data=0, .data_type = MSM_ACTUATOR_BYTE_DATA, .i2c_operation = MSM_ACT_WRITE, .delay = 2 },   // 0 = power up\n        { .reg_addr=2, .addr_type=MSM_ACTUATOR_BYTE_ADDR, .reg_data=2, .data_type = MSM_ACTUATOR_BYTE_DATA, .i2c_operation = MSM_ACT_WRITE, .delay = 2 },   // RING = SAC mode\n        { .reg_addr=6, .addr_type=MSM_ACTUATOR_BYTE_ADDR, .reg_data=64, .data_type = MSM_ACTUATOR_BYTE_DATA, .i2c_operation = MSM_ACT_WRITE, .delay = 0 },  // 0x40 = SAC3 mode\n        { .reg_addr=7, .addr_type=MSM_ACTUATOR_BYTE_ADDR, .reg_data=113, .data_type = MSM_ACTUATOR_BYTE_DATA, .i2c_operation = MSM_ACT_WRITE, .delay = 0 },\n        // 0x71 = DIV1 | DIV0 | SACT0 -- Tvib x 1/4 (quarter)\n        // SAC Tvib = 6.3 ms + 0.1 ms = 6.4 ms / 4 = 1.6 ms\n        // LSC 1-step = 252 + 1*4 = 256 ms / 4 = 64 ms\n      };\n\n      struct region_params_t region_params[] = {\n        {.step_bound = {238, 0,}, .code_per_step = 235, .qvalue = 128}\n      };\n\n      actuator_cfg_data.cfgtype = CFG_SET_ACTUATOR_INFO;\n      actuator_cfg_data.cfg.set_info = (struct msm_actuator_set_info_t){\n        .actuator_params = {\n          .act_type = ACTUATOR_BIVCM,\n          .reg_tbl_size = 1,\n          .data_size = 10,\n          .init_setting_size = 5,\n          .i2c_freq_mode = I2C_STANDARD_MODE,\n          .i2c_addr = 24,\n          .i2c_addr_type = MSM_ACTUATOR_BYTE_ADDR,\n          .i2c_data_type = MSM_ACTUATOR_WORD_DATA,\n          .reg_tbl_params = &actuator_reg_params[0],\n          .init_settings = &actuator_init_settings[0],\n          .park_lens = {.damping_step = 1023, .damping_delay = 14000, .hw_params = 11, .max_step = 20},\n        },\n        .af_tuning_params = {\n          .initial_code = (int16_t)s->infinity_dac,\n          .pwd_step = 0,\n          .region_size = 1,\n          .total_steps = 238,\n          .region_params = &region_params[0],\n        },\n      };\n\n      cam_ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data, \"actuator set info\");\n    }\n  }\n\n  if (s->camera_id == CAMERA_ID_IMX298) {\n    err = sensor_write_regs(s, mode_setting_array_imx298, std::size(mode_setting_array_imx298), MSM_CAMERA_I2C_BYTE_DATA);\n    LOG(\"sensor setup: %d\", err);\n  }\n\n  // CSIPHY: configure csiphy\n  struct msm_camera_csiphy_params csiphy_params = {};\n  if (s->camera_id == CAMERA_ID_IMX298) {\n    csiphy_params = {.lane_cnt = 4, .settle_cnt = 14, .lane_mask = 0x1f, .csid_core = 0};\n  } else if (s->camera_id == CAMERA_ID_S5K3P8SP) {\n    csiphy_params = {.lane_cnt = 4, .settle_cnt = 24, .lane_mask = 0x1f, .csid_core = 0};\n  } else if (s->camera_id == CAMERA_ID_IMX179) {\n    csiphy_params = {.lane_cnt = 4, .settle_cnt = 11, .lane_mask = 0x1f, .csid_core = 2};\n  } else if (s->camera_id == CAMERA_ID_OV8865) {\n    // guess!\n    csiphy_params = {.lane_cnt = 4, .settle_cnt = 24, .lane_mask = 0x1f, .csid_core = 2};\n  }\n  csiphy_cfg_data.cfgtype = CSIPHY_CFG;\n  csiphy_cfg_data.cfg.csiphy_params = &csiphy_params;\n  cam_ioctl(s->csiphy_fd, VIDIOC_MSM_CSIPHY_IO_CFG, &csiphy_cfg_data, \"csiphy configure\");\n\n  // CSID: configure csid\n#define CSI_STATS 0x35\n#define CSI_PD 0x36\n  struct msm_camera_csid_params csid_params = {\n    .lane_cnt = 4,\n    .lane_assign = 0x4320,\n    .phy_sel = (uint8_t)(is_road_cam ? 0 : 2),\n    .lut_params.num_cid = (uint8_t)(is_road_cam ? 3 : 1),\n    .lut_params.vc_cfg_a = {\n      {.cid = 0, .dt = CSI_RAW10, .decode_format = CSI_DECODE_10BIT},\n      {.cid = 1, .dt = CSI_PD, .decode_format = CSI_DECODE_10BIT},\n      {.cid = 2, .dt = CSI_STATS, .decode_format = CSI_DECODE_10BIT},\n    },\n  };\n\n  csid_params.lut_params.vc_cfg[0] = &csid_params.lut_params.vc_cfg_a[0];\n  csid_params.lut_params.vc_cfg[1] = &csid_params.lut_params.vc_cfg_a[1];\n  csid_params.lut_params.vc_cfg[2] = &csid_params.lut_params.vc_cfg_a[2];\n\n  csid_cfg_data.cfgtype = CSID_CFG;\n  csid_cfg_data.cfg.csid_params = &csid_params;\n  cam_ioctl(s->csid_fd, VIDIOC_MSM_CSID_IO_CFG, &csid_cfg_data, \"csid configure\");\n\n  // ISP: SMMU_ATTACH\n  msm_vfe_smmu_attach_cmd smmu_attach_cmd = {.security_mode = 0, .iommu_attach_mode = IOMMU_ATTACH};\n  cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_SMMU_ATTACH, &smmu_attach_cmd, \"isp smmu attach\");\n\n  // ******************* STREAM RAW *****************************\n\n  // configure QMET input\n  struct msm_vfe_input_cfg input_cfg = {};\n  for (int i = 0; i < (is_road_cam ? 3 : 1); i++) {\n    StreamState *ss = &s->ss[i];\n\n    memset(&input_cfg, 0, sizeof(struct msm_vfe_input_cfg));\n    input_cfg.input_src = (msm_vfe_input_src)(VFE_RAW_0+i);\n    input_cfg.input_pix_clk = s->pixel_clock;\n    input_cfg.d.rdi_cfg.cid = i;\n    input_cfg.d.rdi_cfg.frame_based = 1;\n    err = ioctl(s->isp_fd, VIDIOC_MSM_ISP_INPUT_CFG, &input_cfg);\n    LOG(\"configure input(%d): %d\", i, err);\n\n    // ISP: REQUEST_STREAM\n    ss->stream_req.axi_stream_handle = 0;\n    if (is_road_cam) {\n      ss->stream_req.session_id = 2;\n      ss->stream_req.stream_id = /*ISP_META_CHANNEL_BIT | */ISP_NATIVE_BUF_BIT | (1+i);\n    } else {\n      ss->stream_req.session_id = 3;\n      ss->stream_req.stream_id = ISP_NATIVE_BUF_BIT | 1;\n    }\n\n    if (i == 0) {\n      ss->stream_req.output_format = v4l2_fourcc('R', 'G', '1', '0');\n    } else {\n      ss->stream_req.output_format = v4l2_fourcc('Q', 'M', 'E', 'T');\n    }\n    ss->stream_req.stream_src = (msm_vfe_axi_stream_src)(RDI_INTF_0+i);\n\n#ifdef HIGH_FPS\n    if (is_road_cam) {\n      ss->stream_req.frame_skip_pattern = EVERY_3FRAME;\n    }\n#endif\n\n    ss->stream_req.frame_base = 1;\n    ss->stream_req.buf_divert = 1; //i == 0;\n\n    // setup stream plane. doesn't even matter?\n    /*s->stream_req.plane_cfg[0].output_plane_format = Y_PLANE;\n    s->stream_req.plane_cfg[0].output_width = s->ci.frame_width;\n    s->stream_req.plane_cfg[0].output_height = s->ci.frame_height;\n    s->stream_req.plane_cfg[0].output_stride = s->ci.frame_width;\n    s->stream_req.plane_cfg[0].output_scan_lines = s->ci.frame_height;\n    s->stream_req.plane_cfg[0].rdi_cid = 0;*/\n\n    err = ioctl(s->isp_fd, VIDIOC_MSM_ISP_REQUEST_STREAM, &ss->stream_req);\n    LOG(\"isp request stream: %d -> 0x%x\", err, ss->stream_req.axi_stream_handle);\n\n    // ISP: REQUEST_BUF\n    ss->buf_request.session_id = ss->stream_req.session_id;\n    ss->buf_request.stream_id = ss->stream_req.stream_id;\n    ss->buf_request.num_buf = FRAME_BUF_COUNT;\n    ss->buf_request.buf_type = ISP_PRIVATE_BUF;\n    ss->buf_request.handle = 0;\n    cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_REQUEST_BUF, &ss->buf_request, \"isp request buf\");\n    LOG(\"got buf handle: 0x%x\", ss->buf_request.handle);\n\n    // ENQUEUE all buffers\n    for (int j = 0; j < ss->buf_request.num_buf; j++) {\n      ss->qbuf_info[j].handle = ss->buf_request.handle;\n      ss->qbuf_info[j].buf_idx = j;\n      ss->qbuf_info[j].buffer.num_planes = 1;\n      ss->qbuf_info[j].buffer.planes[0].addr = ss->bufs[j].fd;\n      ss->qbuf_info[j].buffer.planes[0].length = ss->bufs[j].len;\n      err = ioctl(s->isp_fd, VIDIOC_MSM_ISP_ENQUEUE_BUF, &ss->qbuf_info[j]);\n    }\n\n    // ISP: UPDATE_STREAM\n    struct msm_vfe_axi_stream_update_cmd update_cmd = {};\n    update_cmd.num_streams = 1;\n    update_cmd.update_info[0].user_stream_id = ss->stream_req.stream_id;\n    update_cmd.update_info[0].stream_handle = ss->stream_req.axi_stream_handle;\n    update_cmd.update_type = UPDATE_STREAM_ADD_BUFQ;\n    cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_UPDATE_STREAM, &update_cmd, \"isp update stream\");\n  }\n\n  LOG(\"******** START STREAMS ********\");\n\n  sub.id = 0;\n  sub.type = 0x1ff;\n  cam_ioctl(s->isp_fd, VIDIOC_SUBSCRIBE_EVENT, &sub, \"isp subscribe\");\n\n  // ISP: START_STREAM\n  s->stream_cfg.cmd = START_STREAM;\n  s->stream_cfg.num_streams = is_road_cam ? 3 : 1;\n  for (int i = 0; i < s->stream_cfg.num_streams; i++) {\n    s->stream_cfg.stream_handle[i] = s->ss[i].stream_req.axi_stream_handle;\n  }\n  cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_CFG_STREAM, &s->stream_cfg, \"isp start stream\");\n}\n\nstatic struct damping_params_t actuator_ringing_params = {\n  .damping_step = 1023,\n  .damping_delay = 15000,\n  .hw_params = 0x0000e422,\n};\n\nstatic void road_camera_start(CameraState *s) {\n  struct msm_actuator_cfg_data actuator_cfg_data = {0};\n\n  set_exposure(s, 1.0, 1.0);\n  int inf_step;\n\n  int err = sensor_write_regs(s, start_reg_array, std::size(start_reg_array), MSM_CAMERA_I2C_BYTE_DATA);\n  LOG(\"sensor start regs: %d\", err);\n\n  if (s->device != DEVICE_LP3) {\n    imx298_ois_calibration(s->ois_fd, s->eeprom);\n    inf_step = 332 - s->infinity_dac;\n\n    // initial guess\n    s->lens_true_pos = 300;\n  } else {\n    // default is OP3, this is for LeEco\n    actuator_ringing_params.damping_step = 1023;\n    actuator_ringing_params.damping_delay = 20000;\n    actuator_ringing_params.hw_params = 13;\n\n    // focus on infinity assuming phone is perpendicular\n    inf_step = 512 - s->infinity_dac;\n\n    // initial guess\n    s->lens_true_pos = 400;\n  }\n\n  // reset lens position\n  memset(&actuator_cfg_data, 0, sizeof(actuator_cfg_data));\n  actuator_cfg_data.cfgtype = CFG_SET_POSITION;\n  actuator_cfg_data.cfg.setpos = (struct msm_actuator_set_position_t){\n    .number_of_steps = 1,\n    .hw_params = (uint32_t)((s->device != DEVICE_LP3) ? 0x0000e424 : 7),\n    .pos = {s->infinity_dac, 0},\n    .delay = {0,}\n  };\n  cam_ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data, \"actuator set pos\");\n\n  // TODO: confirm this isn't needed\n  /*memset(&actuator_cfg_data, 0, sizeof(actuator_cfg_data));\n  actuator_cfg_data.cfgtype = CFG_MOVE_FOCUS;\n  actuator_cfg_data.cfg.move = (struct msm_actuator_move_params_t){\n    .dir = 0,\n    .sign_dir = 1,\n    .dest_step_pos = inf_step,\n    .num_steps = inf_step,\n    .curr_lens_pos = 0,\n    .ringing_params = &actuator_ringing_params,\n  };\n  err = ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data); // should be ~332 at startup ?\n  LOG(\"init actuator move focus: %d\", err);*/\n  //actuator_cfg_data.cfg.move.curr_lens_pos;\n\n  s->cur_lens_pos = 0;\n  s->cur_step_pos = inf_step;\n\n  actuator_move(s, s->cur_lens_pos);\n  LOG(\"init lens pos: %d\", s->cur_lens_pos);\n}\n\nvoid actuator_move(CameraState *s, uint16_t target) {\n  int step = target - s->cur_lens_pos;\n  // LP3 moves only on even positions. TODO: use proper sensor params\n  if (s->device == DEVICE_LP3) {\n    step /= 2;\n  }\n\n  int dest_step_pos = s->cur_step_pos + step;\n  dest_step_pos = std::clamp(dest_step_pos, 0, 255);\n\n  struct msm_actuator_cfg_data actuator_cfg_data = {0};\n  actuator_cfg_data.cfgtype = CFG_MOVE_FOCUS;\n  actuator_cfg_data.cfg.move = (struct msm_actuator_move_params_t){\n    .dir = (int8_t)((step > 0) ? MOVE_NEAR : MOVE_FAR),\n    .sign_dir = (int8_t)((step > 0) ? MSM_ACTUATOR_MOVE_SIGNED_NEAR : MSM_ACTUATOR_MOVE_SIGNED_FAR),\n    .dest_step_pos = (int16_t)dest_step_pos,\n    .num_steps = abs(step),\n    .curr_lens_pos = s->cur_lens_pos,\n    .ringing_params = &actuator_ringing_params,\n  };\n  HANDLE_EINTR(ioctl(s->actuator_fd, VIDIOC_MSM_ACTUATOR_CFG, &actuator_cfg_data));\n\n  s->cur_step_pos = dest_step_pos;\n  s->cur_lens_pos = actuator_cfg_data.cfg.move.curr_lens_pos;\n  //LOGD(\"step %d   target: %d  lens pos: %d\", dest_step_pos, target, s->cur_lens_pos);\n}\n\nstatic void parse_autofocus(CameraState *s, uint8_t *d) {\n  int good_count = 0;\n  int16_t max_focus = -32767;\n  int avg_focus = 0;\n\n  /*printf(\"FOCUS: \");\n  for (int i = 0; i < 0x10; i++) {\n    printf(\"%2.2X \", d[i]);\n  }*/\n\n  for (int i = 0; i < NUM_FOCUS; i++) {\n    int doff = i*5+5;\n    s->confidence[i] = d[doff];\n    // this should just be a 10-bit signed int instead of 11\n    // TODO: write it in a nicer way\n    int16_t focus_t = (d[doff+1] << 3) | (d[doff+2] >> 5);\n    if (focus_t >= 1024) focus_t = -(2048-focus_t);\n    s->focus[i] = focus_t;\n    //printf(\"%x->%d \", d[doff], focus_t);\n    if (s->confidence[i] > 0x20) {\n      good_count++;\n      max_focus = std::max(max_focus, s->focus[i]);\n      avg_focus += s->focus[i];\n    }\n  }\n  // self recover override\n  if (s->self_recover > 1) {\n    s->focus_err = 200 * ((s->self_recover % 2 == 0) ? 1:-1); // far for even numbers, close for odd\n    s->self_recover -= 2;\n    return;\n  }\n\n  if (good_count < 4) {\n    s->focus_err = nan(\"\");\n    return;\n  }\n\n  avg_focus /= good_count;\n\n  // outlier rejection\n  if (abs(avg_focus - max_focus) > 200) {\n    s->focus_err = nan(\"\");\n    return;\n  }\n\n  s->focus_err = max_focus*1.0;\n}\n\nstatic std::optional<float> get_accel_z(SubMaster *sm) {\n  sm->update(0);\n  if(sm->updated(\"sensorEvents\")) {\n    for (auto event : (*sm)[\"sensorEvents\"].getSensorEvents()) {\n      if (event.which() == cereal::SensorEventData::ACCELERATION) {\n        if (auto v = event.getAcceleration().getV(); v.size() >= 3)\n          return -v[2];\n        break;\n      }\n    }\n  }\n  return std::nullopt;\n}\n\nstatic void do_autofocus(CameraState *s, SubMaster *sm) {\n  const int dac_down = s->device == DEVICE_LP3 ? LP3_AF_DAC_DOWN : OP3T_AF_DAC_DOWN;\n  const int dac_up = s->device == DEVICE_LP3 ? LP3_AF_DAC_UP : OP3T_AF_DAC_UP;\n\n  float lens_true_pos = s->lens_true_pos.load();\n  if (!isnan(s->focus_err)) {\n    // learn lens_true_pos\n    const float focus_kp = 0.005;\n    lens_true_pos -= s->focus_err*focus_kp;\n  }\n\n  if (auto accel_z = get_accel_z(sm)) {\n    s->last_sag_acc_z = *accel_z;\n  }\n  const float sag = (s->last_sag_acc_z / 9.8) * 128;\n  // stay off the walls\n  lens_true_pos = std::clamp(lens_true_pos, float(dac_down), float(dac_up));\n  int target = std::clamp(lens_true_pos - sag, float(dac_down), float(dac_up));\n  s->lens_true_pos.store(lens_true_pos);\n\n  /*char debug[4096];\n  char *pdebug = debug;\n  pdebug += sprintf(pdebug, \"focus \");\n  for (int i = 0; i < NUM_FOCUS; i++) pdebug += sprintf(pdebug, \"%2x(%4d) \", s->confidence[i], s->focus[i]);\n  pdebug += sprintf(pdebug, \"  err: %7.2f  offset: %6.2f sag: %6.2f lens_true_pos: %6.2f  cur_lens_pos: %4d->%4d\", err * focus_kp, offset, sag, s->lens_true_pos, s->cur_lens_pos, target);\n  LOGD(debug);*/\n\n  actuator_move(s, target);\n}\n\nvoid camera_autoexposure(CameraState *s, float grey_frac) {\n  if (s->camera_num == 0) {\n    CameraExpInfo tmp = road_cam_exp.load();\n    tmp.op_id++;\n    tmp.grey_frac = grey_frac;\n    road_cam_exp.store(tmp);\n  } else {\n    CameraExpInfo tmp = driver_cam_exp.load();\n    tmp.op_id++;\n    tmp.grey_frac = grey_frac;\n    driver_cam_exp.store(tmp);\n  }\n}\n\nstatic void driver_camera_start(CameraState *s) {\n  set_exposure(s, 1.0, 1.0);\n  int err = sensor_write_regs(s, start_reg_array, std::size(start_reg_array), MSM_CAMERA_I2C_BYTE_DATA);\n  LOG(\"sensor start regs: %d\", err);\n}\n\nvoid cameras_open(MultiCameraState *s) {\n  struct msm_ispif_param_data ispif_params = {\n    .num = 4,\n    .entries = {\n      // road camera\n      {.vfe_intf = VFE0, .intftype = RDI0, .num_cids = 1, .cids[0] = CID0, .csid = CSID0},\n      // driver camera\n      {.vfe_intf = VFE1, .intftype = RDI0, .num_cids = 1, .cids[0] = CID0, .csid = CSID2},\n      // road camera (focus)\n      {.vfe_intf = VFE0, .intftype = RDI1, .num_cids = 1, .cids[0] = CID1, .csid = CSID0},\n      // road camera (stats, for AE)\n      {.vfe_intf = VFE0, .intftype = RDI2, .num_cids = 1, .cids[0] = CID2, .csid = CSID0},\n    },\n  };\n  s->msmcfg_fd = HANDLE_EINTR(open(\"/dev/media0\", O_RDWR | O_NONBLOCK));\n  assert(s->msmcfg_fd >= 0);\n\n  sensors_init(s);\n\n  s->v4l_fd = HANDLE_EINTR(open(\"/dev/video0\", O_RDWR | O_NONBLOCK));\n  assert(s->v4l_fd >= 0);\n\n  if (s->device == DEVICE_LP3) {\n    s->ispif_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev15\", O_RDWR | O_NONBLOCK));\n  } else {\n    s->ispif_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev16\", O_RDWR | O_NONBLOCK));\n  }\n  assert(s->ispif_fd >= 0);\n\n  // ISPIF: stop\n  // memset(&ispif_cfg_data, 0, sizeof(ispif_cfg_data));\n  // ispif_cfg_data.cfg_type = ISPIF_STOP_FRAME_BOUNDARY;\n  // ispif_cfg_data.params = ispif_params;\n  // err = ioctl(s->ispif_fd, VIDIOC_MSM_ISPIF_CFG, &ispif_cfg_data);\n  // LOG(\"ispif stop: %d\", err);\n\n  LOG(\"*** open driver camera ***\");\n  s->driver_cam.ss[0].bufs = s->driver_cam.buf.camera_bufs.get();\n  camera_open(&s->driver_cam, false);\n\n  LOG(\"*** open road camera ***\");\n  s->road_cam.ss[0].bufs = s->road_cam.buf.camera_bufs.get();\n  s->road_cam.ss[1].bufs = s->focus_bufs;\n  s->road_cam.ss[2].bufs = s->stats_bufs;\n  camera_open(&s->road_cam, true);\n\n  if (getenv(\"CAMERA_TEST\")) {\n    cameras_close(s);\n    exit(0);\n  }\n\n  // ISPIF: set vfe info\n  struct ispif_cfg_data ispif_cfg_data = {.cfg_type = ISPIF_SET_VFE_INFO, .vfe_info.num_vfe = 2};\n  int err = HANDLE_EINTR(ioctl(s->ispif_fd, VIDIOC_MSM_ISPIF_CFG, &ispif_cfg_data));\n  LOG(\"ispif set vfe info: %d\", err);\n\n  // ISPIF: setup\n  ispif_cfg_data = {.cfg_type = ISPIF_INIT, .csid_version = 0x30050000 /* CSID_VERSION_V35*/};\n  cam_ioctl(s->ispif_fd, VIDIOC_MSM_ISPIF_CFG, &ispif_cfg_data, \"ispif setup\");\n\n  ispif_cfg_data = {.cfg_type = ISPIF_CFG, .params = ispif_params};\n  cam_ioctl(s->ispif_fd, VIDIOC_MSM_ISPIF_CFG, &ispif_cfg_data, \"ispif cfg\");\n\n  ispif_cfg_data.cfg_type = ISPIF_START_FRAME_BOUNDARY;\n  cam_ioctl(s->ispif_fd, VIDIOC_MSM_ISPIF_CFG, &ispif_cfg_data, \"ispif start_frame_boundary\");\n\n  driver_camera_start(&s->driver_cam);\n  road_camera_start(&s->road_cam);\n}\n\n\nstatic void camera_close(CameraState *s) {\n  // ISP: STOP_STREAM\n  s->stream_cfg.cmd = STOP_STREAM;\n  cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_CFG_STREAM, &s->stream_cfg, \"isp stop stream\");\n\n  for (int i = 0; i < 3; i++) {\n    StreamState *ss = &s->ss[i];\n    if (ss->stream_req.axi_stream_handle != 0) {\n      cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_RELEASE_BUF, &ss->buf_request, \"isp release buf\");\n\n      struct msm_vfe_axi_stream_release_cmd stream_release = {\n        .stream_handle = ss->stream_req.axi_stream_handle,\n      };\n      cam_ioctl(s->isp_fd, VIDIOC_MSM_ISP_RELEASE_STREAM, &stream_release, \"isp release stream\");\n    }\n  }\n  free(s->eeprom);\n}\n\nconst char* get_isp_event_name(uint32_t type) {\n  switch (type) {\n  case ISP_EVENT_REG_UPDATE: return \"ISP_EVENT_REG_UPDATE\";\n  case ISP_EVENT_EPOCH_0: return \"ISP_EVENT_EPOCH_0\";\n  case ISP_EVENT_EPOCH_1: return \"ISP_EVENT_EPOCH_1\";\n  case ISP_EVENT_START_ACK: return \"ISP_EVENT_START_ACK\";\n  case ISP_EVENT_STOP_ACK: return \"ISP_EVENT_STOP_ACK\";\n  case ISP_EVENT_IRQ_VIOLATION: return \"ISP_EVENT_IRQ_VIOLATION\";\n  case ISP_EVENT_STATS_OVERFLOW: return \"ISP_EVENT_STATS_OVERFLOW\";\n  case ISP_EVENT_ERROR: return \"ISP_EVENT_ERROR\";\n  case ISP_EVENT_SOF: return \"ISP_EVENT_SOF\";\n  case ISP_EVENT_EOF: return \"ISP_EVENT_EOF\";\n  case ISP_EVENT_BUF_DONE: return \"ISP_EVENT_BUF_DONE\";\n  case ISP_EVENT_BUF_DIVERT: return \"ISP_EVENT_BUF_DIVERT\";\n  case ISP_EVENT_STATS_NOTIFY: return \"ISP_EVENT_STATS_NOTIFY\";\n  case ISP_EVENT_COMP_STATS_NOTIFY: return \"ISP_EVENT_COMP_STATS_NOTIFY\";\n  case ISP_EVENT_FE_READ_DONE: return \"ISP_EVENT_FE_READ_DONE\";\n  case ISP_EVENT_IOMMU_P_FAULT: return \"ISP_EVENT_IOMMU_P_FAULT\";\n  case ISP_EVENT_HW_FATAL_ERROR: return \"ISP_EVENT_HW_FATAL_ERROR\";\n  case ISP_EVENT_PING_PONG_MISMATCH: return \"ISP_EVENT_PING_PONG_MISMATCH\";\n  case ISP_EVENT_REG_UPDATE_MISSING: return \"ISP_EVENT_REG_UPDATE_MISSING\";\n  case ISP_EVENT_BUF_FATAL_ERROR: return \"ISP_EVENT_BUF_FATAL_ERROR\";\n  case ISP_EVENT_STREAM_UPDATE_DONE: return \"ISP_EVENT_STREAM_UPDATE_DONE\";\n  default: return \"unknown\";\n  }\n}\n\nstatic FrameMetadata get_frame_metadata(CameraState *s, uint32_t frame_id) {\n  std::lock_guard lk(s->frame_info_lock);\n  for (auto &i : s->frame_metadata) {\n    if (i.frame_id == frame_id) {\n      return i;\n    }\n  }\n  // should never happen\n  return (FrameMetadata){\n    .frame_id = (uint32_t)-1,\n  };\n}\n\nstatic void ops_thread(MultiCameraState *s) {\n  int last_road_cam_op_id = 0;\n  int last_driver_cam_op_id = 0;\n\n  CameraExpInfo road_cam_op;\n  CameraExpInfo driver_cam_op;\n\n  set_thread_name(\"camera_settings\");\n  SubMaster sm({\"sensorEvents\"});\n  while(!do_exit) {\n    road_cam_op = road_cam_exp.load();\n    if (road_cam_op.op_id != last_road_cam_op_id) {\n      do_autoexposure(&s->road_cam, road_cam_op.grey_frac);\n      do_autofocus(&s->road_cam, &sm);\n      last_road_cam_op_id = road_cam_op.op_id;\n    }\n\n    driver_cam_op = driver_cam_exp.load();\n    if (driver_cam_op.op_id != last_driver_cam_op_id) {\n      do_autoexposure(&s->driver_cam, driver_cam_op.grey_frac);\n      last_driver_cam_op_id = driver_cam_op.op_id;\n    }\n\n    util::sleep_for(50);\n  }\n}\n\nstatic void setup_self_recover(CameraState *c, const uint16_t *lapres, size_t lapres_size) {\n  const int dac_down = c->device == DEVICE_LP3 ? LP3_AF_DAC_DOWN : OP3T_AF_DAC_DOWN;\n  const int dac_up = c->device == DEVICE_LP3 ? LP3_AF_DAC_UP : OP3T_AF_DAC_UP;\n  const int dac_m = c->device == DEVICE_LP3 ? LP3_AF_DAC_M : OP3T_AF_DAC_M;\n  const int dac_3sig = c->device == DEVICE_LP3 ? LP3_AF_DAC_3SIG : OP3T_AF_DAC_3SIG;\n\n  const float lens_true_pos = c->lens_true_pos.load();\n  int self_recover = c->self_recover.load();\n  if (self_recover < 2 && (lens_true_pos < (dac_down + 1) || lens_true_pos > (dac_up - 1)) && is_blur(lapres, lapres_size)) {\n    // truly stuck, needs help\n    if (--self_recover < -FOCUS_RECOVER_PATIENCE) {\n      LOGD(\"road camera bad state detected. attempting recovery from %.1f, recover state is %d\", lens_true_pos, self_recover);\n      // parity determined by which end is stuck at\n      self_recover = FOCUS_RECOVER_STEPS + (lens_true_pos < dac_m ? 1 : 0);\n    }\n  } else if (self_recover < 2 && (lens_true_pos < (dac_m - dac_3sig) || lens_true_pos > (dac_m + dac_3sig))) {\n    // in suboptimal position with high prob, but may still recover by itself\n    if (--self_recover < -(FOCUS_RECOVER_PATIENCE * 3)) {\n      self_recover = FOCUS_RECOVER_STEPS / 2 + (lens_true_pos < dac_m ? 1 : 0);\n    }\n  } else if (self_recover < 0) {\n    self_recover += 1;  // reset if fine\n  }\n  c->self_recover.store(self_recover);\n}\n\nvoid process_driver_camera(MultiCameraState *s, CameraState *c, int cnt) {\n  common_process_driver_camera(s->sm, s->pm, c, cnt);\n}\n\n// called by processing_thread\nvoid process_road_camera(MultiCameraState *s, CameraState *c, int cnt) {\n  const CameraBuf *b = &c->buf;\n  const int roi_id = cnt % std::size(s->lapres);  // rolling roi\n  s->lapres[roi_id] = s->lap_conv->Update(b->q, (uint8_t *)b->cur_rgb_buf->addr, roi_id);\n  setup_self_recover(c, &s->lapres[0], std::size(s->lapres));\n\n  MessageBuilder msg;\n  auto framed = msg.initEvent().initRoadCameraState();\n  fill_frame_data(framed, b->cur_frame_data);\n  if (env_send_road) {\n    framed.setImage(get_frame_image(b));\n  }\n  framed.setFocusVal(s->road_cam.focus);\n  framed.setFocusConf(s->road_cam.confidence);\n  framed.setRecoverState(s->road_cam.self_recover);\n  framed.setSharpnessScore(s->lapres);\n  framed.setTransform(b->yuv_transform.v);\n  s->pm->send(\"roadCameraState\", msg);\n\n  if (cnt % 3 == 0) {\n    const int x = 290, y = 322, width = 560, height = 314;\n    const int skip = 1;\n    camera_autoexposure(c, set_exposure_target(b, x, x + width, skip, y, y + height, skip));\n  }\n}\n\nvoid cameras_run(MultiCameraState *s) {\n  std::vector<std::thread> threads;\n  threads.push_back(std::thread(ops_thread, s));\n  threads.push_back(start_process_thread(s, &s->road_cam, process_road_camera));\n  threads.push_back(start_process_thread(s, &s->driver_cam, process_driver_camera));\n\n  CameraState* cameras[2] = {&s->road_cam, &s->driver_cam};\n\n  while (!do_exit) {\n    struct pollfd fds[2] = {{.fd = cameras[0]->isp_fd, .events = POLLPRI},\n                            {.fd = cameras[1]->isp_fd, .events = POLLPRI}};\n    int ret = poll(fds, std::size(fds), 1000);\n    if (ret < 0) {\n      if (errno == EINTR || errno == EAGAIN) continue;\n      LOGE(\"poll failed (%d - %d)\", ret, errno);\n      break;\n    }\n\n    // process cameras\n    for (int i=0; i<2; i++) {\n      if (!fds[i].revents) continue;\n\n      CameraState *c = cameras[i];\n\n      struct v4l2_event ev = {};\n      ret = HANDLE_EINTR(ioctl(c->isp_fd, VIDIOC_DQEVENT, &ev));\n      const msm_isp_event_data *isp_event_data = (const msm_isp_event_data *)ev.u.data;\n\n      if (ev.type == ISP_EVENT_BUF_DIVERT) {\n        const int buf_idx = isp_event_data->u.buf_done.buf_idx;\n        const int buffer = (isp_event_data->u.buf_done.stream_id & 0xFFFF) - 1;\n        if (buffer == 0) {\n          c->buf.camera_bufs_metadata[buf_idx] = get_frame_metadata(c, isp_event_data->frame_id);\n          c->buf.queue(buf_idx);\n        } else {\n          auto &ss = c->ss[buffer];\n          if (buffer == 1) {\n            parse_autofocus(c, (uint8_t *)(ss.bufs[buf_idx].addr));\n          }\n          ss.qbuf_info[buf_idx].dirty_buf = 1;\n          HANDLE_EINTR(ioctl(c->isp_fd, VIDIOC_MSM_ISP_ENQUEUE_BUF, &ss.qbuf_info[buf_idx]));\n        }\n\n      } else if (ev.type == ISP_EVENT_EOF) {\n        const uint64_t timestamp = (isp_event_data->mono_timestamp.tv_sec * 1000000000ULL + isp_event_data->mono_timestamp.tv_usec * 1000);\n        std::lock_guard lk(c->frame_info_lock);\n        c->frame_metadata[c->frame_metadata_idx] = (FrameMetadata){\n            .frame_id = isp_event_data->frame_id,\n            .timestamp_eof = timestamp,\n            .frame_length = (uint32_t)c->frame_length,\n            .integ_lines = (uint32_t)c->cur_integ_lines,\n            .lens_pos = c->cur_lens_pos,\n            .lens_sag = c->last_sag_acc_z,\n            .lens_err = c->focus_err,\n            .lens_true_pos = c->lens_true_pos,\n            .gain = c->cur_gain_frac,\n            .measured_grey_fraction = c->measured_grey_fraction,\n            .target_grey_fraction = c->target_grey_fraction,\n            .high_conversion_gain = false,\n        };\n        c->frame_metadata_idx = (c->frame_metadata_idx + 1) % METADATA_BUF_COUNT;\n\n      } else if (ev.type == ISP_EVENT_ERROR) {\n        LOGE(\"ISP_EVENT_ERROR! err type: 0x%08x\", isp_event_data->u.error_info.err_type);\n      }\n    }\n  }\n\n  LOG(\" ************** STOPPING **************\");\n\n  for (auto &t : threads) t.join();\n\n  cameras_close(s);\n}\n\nvoid cameras_close(MultiCameraState *s) {\n  camera_close(&s->road_cam);\n  camera_close(&s->driver_cam);\n  for (int i = 0; i < FRAME_BUF_COUNT; i++) {\n    s->focus_bufs[i].free();\n    s->stats_bufs[i].free();\n  }\n\n  delete s->lap_conv;\n  delete s->sm;\n  delete s->pm;\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_qcom.h",
    "content": "#pragma once\n\n#include <atomic>\n#include <cstdint>\n#include <memory>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"cereal/visionipc/visionbuf.h\"\n#include \"selfdrive/camerad/cameras/camera_common.h\"\n#include \"selfdrive/camerad/imgproc/utils.h\"\n#include \"selfdrive/camerad/include/msm_cam_sensor.h\"\n#include \"selfdrive/camerad/include/msmb_camera.h\"\n#include \"selfdrive/camerad/include/msmb_isp.h\"\n#include \"selfdrive/camerad/include/msmb_ispif.h\"\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/util.h\"\n\n#define FRAME_BUF_COUNT 4\n#define METADATA_BUF_COUNT 4\n\n#define DEVICE_OP3 0\n#define DEVICE_OP3T 1\n#define DEVICE_LP3 2\n\n#define NUM_FOCUS 8\n\n#define LP3_AF_DAC_DOWN 366\n#define LP3_AF_DAC_UP 634\n#define LP3_AF_DAC_M 440\n#define LP3_AF_DAC_3SIG 52\n#define OP3T_AF_DAC_DOWN 224\n#define OP3T_AF_DAC_UP 456\n#define OP3T_AF_DAC_M 300\n#define OP3T_AF_DAC_3SIG 96\n\n#define FOCUS_RECOVER_PATIENCE 50 // 2.5 seconds of complete blur\n#define FOCUS_RECOVER_STEPS 240 // 6 seconds\n\ntypedef struct CameraState CameraState;\n\ntypedef int (*camera_apply_exposure_func)(CameraState *s, int gain, int integ_lines, uint32_t frame_length);\n\ntypedef struct StreamState {\n  struct msm_isp_buf_request buf_request;\n  struct msm_vfe_axi_stream_request_cmd stream_req;\n  struct msm_isp_qbuf_info qbuf_info[FRAME_BUF_COUNT];\n  VisionBuf *bufs;\n} StreamState;\n\ntypedef struct CameraState {\n  int camera_num;\n  int camera_id;\n  int device;\n\n  int fps;\n  CameraInfo ci;\n\n  unique_fd csid_fd;\n  unique_fd csiphy_fd;\n  unique_fd sensor_fd;\n  unique_fd isp_fd;\n\n  struct msm_vfe_axi_stream_cfg_cmd stream_cfg;\n\n  StreamState ss[3];\n  CameraBuf buf;\n\n  std::mutex frame_info_lock;\n  FrameMetadata frame_metadata[METADATA_BUF_COUNT];\n  int frame_metadata_idx;\n\n  // exposure\n  uint32_t pixel_clock, line_length_pclk;\n  uint32_t frame_length;\n  unsigned int max_gain;\n  float cur_exposure_frac, cur_gain_frac;\n  int cur_gain, cur_integ_lines;\n\n  float measured_grey_fraction;\n  float target_grey_fraction;\n\n  std::atomic<float> digital_gain;\n  camera_apply_exposure_func apply_exposure;\n\n  // rear camera only,used for focusing\n  unique_fd actuator_fd, ois_fd, eeprom_fd;\n  std::atomic<float> focus_err;\n  std::atomic<float> last_sag_acc_z;\n  std::atomic<float> lens_true_pos;\n  std::atomic<int> self_recover; // af recovery counter, neg is patience, pos is active\n  uint16_t cur_step_pos;\n  uint16_t cur_lens_pos;\n  int16_t focus[NUM_FOCUS];\n  uint8_t confidence[NUM_FOCUS];\n  uint16_t infinity_dac;\n  size_t eeprom_size;\n  uint8_t *eeprom;\n} CameraState;\n\n\ntypedef struct MultiCameraState {\n  int device;\n\n  unique_fd ispif_fd;\n  unique_fd msmcfg_fd;\n  unique_fd v4l_fd;\n  uint16_t lapres[(ROI_X_MAX-ROI_X_MIN+1)*(ROI_Y_MAX-ROI_Y_MIN+1)];\n\n  VisionBuf focus_bufs[FRAME_BUF_COUNT];\n  VisionBuf stats_bufs[FRAME_BUF_COUNT];\n\n  CameraState road_cam;\n  CameraState driver_cam;\n\n  SubMaster *sm;\n  PubMaster *pm;\n  LapConv *lap_conv;\n} MultiCameraState;\n\nvoid actuator_move(CameraState *s, uint16_t target);\nint sensor_write_regs(CameraState *s, struct msm_camera_i2c_reg_array* arr, size_t size, int data_type);\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_qcom2.cc",
    "content": "#include \"selfdrive/camerad/cameras/camera_qcom2.h\"\n\n#include <fcntl.h>\n#include <poll.h>\n#include <sys/ioctl.h>\n#include <sys/mman.h>\n#include <unistd.h>\n\n#include <atomic>\n#include <cassert>\n#include <cerrno>\n#include <cmath>\n#include <cstdio>\n#include <cstring>\n\n#include \"media/cam_defs.h\"\n#include \"media/cam_isp.h\"\n#include \"media/cam_isp_ife.h\"\n#include \"media/cam_sensor.h\"\n#include \"media/cam_sensor_cmn_header.h\"\n#include \"media/cam_sync.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/camerad/cameras/sensor2_i2c.h\"\n\nextern ExitHandler do_exit;\n\nconst size_t FRAME_WIDTH = 1928;\nconst size_t FRAME_HEIGHT = 1208;\nconst size_t FRAME_STRIDE = 2416;  // for 10 bit output\n\nconst int MIPI_SETTLE_CNT = 33;  // Calculated by camera_freqs.py\n\nCameraInfo cameras_supported[CAMERA_ID_MAX] = {\n  [CAMERA_ID_AR0231] = {\n    .frame_width = FRAME_WIDTH,\n    .frame_height = FRAME_HEIGHT,\n    .frame_stride = FRAME_STRIDE,\n    .bayer = true,\n    .bayer_flip = 1,\n    .hdr = false\n  },\n};\n\nconst float DC_GAIN = 2.5;\nconst float sensor_analog_gains[] = {\n  1.0/8.0, 2.0/8.0, 2.0/7.0, 3.0/7.0, // 0, 1, 2, 3\n  3.0/6.0, 4.0/6.0, 4.0/5.0, 5.0/5.0, // 4, 5, 6, 7\n  5.0/4.0, 6.0/4.0, 6.0/3.0, 7.0/3.0, // 8, 9, 10, 11\n  7.0/2.0, 8.0/2.0, 8.0/1.0};         // 12, 13, 14, 15 = bypass\n\nconst int ANALOG_GAIN_MIN_IDX = 0x1; // 0.25x\nconst int ANALOG_GAIN_REC_IDX = 0x6; // 0.8x\nconst int ANALOG_GAIN_MAX_IDX = 0xD; // 4.0x\n\nconst int EXPOSURE_TIME_MIN = 2; // with HDR, fastest ss\nconst int EXPOSURE_TIME_MAX = 1904; // with HDR, slowest ss\n\n// ************** low level camera helpers ****************\nint cam_control(int fd, int op_code, void *handle, int size) {\n  struct cam_control camcontrol = {0};\n  camcontrol.op_code = op_code;\n  camcontrol.handle = (uint64_t)handle;\n  if (size == 0) { \n    camcontrol.size = 8;\n    camcontrol.handle_type = CAM_HANDLE_MEM_HANDLE;\n  } else {\n    camcontrol.size = size;\n    camcontrol.handle_type = CAM_HANDLE_USER_POINTER;\n  }\n\n  int ret = HANDLE_EINTR(ioctl(fd, VIDIOC_CAM_CONTROL, &camcontrol));\n  if (ret == -1) {\n    printf(\"OP CODE ERR - %d \\n\", op_code);\n    perror(\"wat\");\n  }\n  return ret;\n}\n\nstd::optional<int32_t> device_acquire(int fd, int32_t session_handle, void *data) {\n  struct cam_acquire_dev_cmd cmd = {\n      .session_handle = session_handle,\n      .handle_type = CAM_HANDLE_USER_POINTER,\n      .num_resources = (uint32_t)(data ? 1 : 0),\n      .resource_hdl = (uint64_t)data,\n  };\n  int err = cam_control(fd, CAM_ACQUIRE_DEV, &cmd, sizeof(cmd));\n  return err == 0 ? std::make_optional(cmd.dev_handle) : std::nullopt;\n};\n\nint device_config(int fd, int32_t session_handle, int32_t dev_handle, uint64_t packet_handle) {\n  struct cam_config_dev_cmd cmd = {\n      .session_handle = session_handle,\n      .dev_handle = dev_handle,\n      .packet_handle = packet_handle,\n  };\n  return cam_control(fd, CAM_CONFIG_DEV, &cmd, sizeof(cmd));\n}\n\nint device_control(int fd, int op_code, int session_handle, int dev_handle) {\n  // start stop and release are all the same\n  struct cam_start_stop_dev_cmd cmd { .session_handle = session_handle, .dev_handle = dev_handle };\n  return cam_control(fd, op_code, &cmd, sizeof(cmd));\n}\n\nvoid *alloc_w_mmu_hdl(int video0_fd, int len, uint32_t *handle, int align = 8, int flags = CAM_MEM_FLAG_KMD_ACCESS | CAM_MEM_FLAG_UMD_ACCESS | CAM_MEM_FLAG_CMD_BUF_TYPE,\n                      int mmu_hdl = 0, int mmu_hdl2 = 0) {\n  struct cam_mem_mgr_alloc_cmd mem_mgr_alloc_cmd = {0};\n  mem_mgr_alloc_cmd.len = len;\n  mem_mgr_alloc_cmd.align = align;\n  mem_mgr_alloc_cmd.flags = flags;\n  mem_mgr_alloc_cmd.num_hdl = 0;\n  if (mmu_hdl != 0) {\n    mem_mgr_alloc_cmd.mmu_hdls[0] = mmu_hdl;\n    mem_mgr_alloc_cmd.num_hdl++;\n  }\n  if (mmu_hdl2 != 0) {\n    mem_mgr_alloc_cmd.mmu_hdls[1] = mmu_hdl2;\n    mem_mgr_alloc_cmd.num_hdl++;\n  }\n\n  cam_control(video0_fd, CAM_REQ_MGR_ALLOC_BUF, &mem_mgr_alloc_cmd, sizeof(mem_mgr_alloc_cmd));\n  *handle = mem_mgr_alloc_cmd.out.buf_handle;\n\n  void *ptr = NULL;\n  if (mem_mgr_alloc_cmd.out.fd > 0) {\n    ptr = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, mem_mgr_alloc_cmd.out.fd, 0);\n    assert(ptr != MAP_FAILED);\n  }\n\n  // LOGD(\"allocated: %x %d %llx mapped %p\", mem_mgr_alloc_cmd.out.buf_handle, mem_mgr_alloc_cmd.out.fd, mem_mgr_alloc_cmd.out.vaddr, ptr);\n\n  return ptr;\n}\n\nvoid release(int video0_fd, uint32_t handle) {\n  int ret;\n  struct cam_mem_mgr_release_cmd mem_mgr_release_cmd = {0};\n  mem_mgr_release_cmd.buf_handle = handle;\n\n  ret = cam_control(video0_fd, CAM_REQ_MGR_RELEASE_BUF, &mem_mgr_release_cmd, sizeof(mem_mgr_release_cmd));\n  assert(ret == 0);\n}\n\nvoid release_fd(int video0_fd, uint32_t handle) {\n  // handle to fd\n  close(handle>>16);\n  release(video0_fd, handle);\n}\n\nvoid clear_req_queue(int fd, int32_t session_hdl, int32_t link_hdl) {\n  struct cam_req_mgr_flush_info req_mgr_flush_request = {0};\n  req_mgr_flush_request.session_hdl = session_hdl;\n  req_mgr_flush_request.link_hdl = link_hdl;\n  req_mgr_flush_request.flush_type = CAM_REQ_MGR_FLUSH_TYPE_ALL;\n  int ret;\n  ret = cam_control(fd, CAM_REQ_MGR_FLUSH_REQ, &req_mgr_flush_request, sizeof(req_mgr_flush_request));\n  // LOGD(\"flushed all req: %d\", ret);\n}\n\n// ************** high level camera helpers ****************\n\nvoid sensors_poke(struct CameraState *s, int request_id) {\n  uint32_t cam_packet_handle = 0;\n  int size = sizeof(struct cam_packet);\n  struct cam_packet *pkt = (struct cam_packet *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, size, &cam_packet_handle);\n  pkt->num_cmd_buf = 0;\n  pkt->kmd_cmd_buf_index = -1;\n  pkt->header.size = size;\n  pkt->header.op_code = 0x7f;\n  pkt->header.request_id = request_id;\n\n  int ret = device_config(s->sensor_fd, s->session_handle, s->sensor_dev_handle, cam_packet_handle);\n  assert(ret == 0);\n\n  munmap(pkt, size);\n  release_fd(s->multi_cam_state->video0_fd, cam_packet_handle);\n}\n\nvoid sensors_i2c(struct CameraState *s, struct i2c_random_wr_payload* dat, int len, int op_code) {\n  // LOGD(\"sensors_i2c: %d\", len);\n  uint32_t cam_packet_handle = 0;\n  int size = sizeof(struct cam_packet)+sizeof(struct cam_cmd_buf_desc)*1;\n  struct cam_packet *pkt = (struct cam_packet *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, size, &cam_packet_handle);\n  pkt->num_cmd_buf = 1;\n  pkt->kmd_cmd_buf_index = -1;\n  pkt->header.size = size;\n  pkt->header.op_code = op_code;\n  struct cam_cmd_buf_desc *buf_desc = (struct cam_cmd_buf_desc *)&pkt->payload;\n\n  buf_desc[0].size = buf_desc[0].length = sizeof(struct i2c_rdwr_header) + len*sizeof(struct i2c_random_wr_payload);\n  buf_desc[0].type = CAM_CMD_BUF_I2C;\n\n  struct cam_cmd_i2c_random_wr *i2c_random_wr = (struct cam_cmd_i2c_random_wr *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, buf_desc[0].size, (uint32_t*)&buf_desc[0].mem_handle);\n  i2c_random_wr->header.count = len;\n  i2c_random_wr->header.op_code = 1;\n  i2c_random_wr->header.cmd_type = CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR;\n  i2c_random_wr->header.data_type = CAMERA_SENSOR_I2C_TYPE_WORD;\n  i2c_random_wr->header.addr_type = CAMERA_SENSOR_I2C_TYPE_WORD;\n  memcpy(i2c_random_wr->random_wr_payload, dat, len*sizeof(struct i2c_random_wr_payload));\n\n  int ret = device_config(s->sensor_fd, s->session_handle, s->sensor_dev_handle, cam_packet_handle);\n  assert(ret == 0);\n\n  munmap(i2c_random_wr, buf_desc[0].size);\n  release_fd(s->multi_cam_state->video0_fd, buf_desc[0].mem_handle);\n  munmap(pkt, size);\n  release_fd(s->multi_cam_state->video0_fd, cam_packet_handle);\n}\nstatic cam_cmd_power *power_set_wait(cam_cmd_power *power, int16_t delay_ms) {\n  cam_cmd_unconditional_wait *unconditional_wait = (cam_cmd_unconditional_wait *)((char *)power + (sizeof(struct cam_cmd_power) + (power->count - 1) * sizeof(struct cam_power_settings)));\n  unconditional_wait->cmd_type = CAMERA_SENSOR_CMD_TYPE_WAIT;\n  unconditional_wait->delay = delay_ms;\n  unconditional_wait->op_code = CAMERA_SENSOR_WAIT_OP_SW_UCND;\n  return (struct cam_cmd_power *)(unconditional_wait + 1);\n};\n\nvoid sensors_init(int video0_fd, int sensor_fd, int camera_num) {\n  uint32_t cam_packet_handle = 0;\n  int size = sizeof(struct cam_packet)+sizeof(struct cam_cmd_buf_desc)*2;\n  struct cam_packet *pkt = (struct cam_packet *)alloc_w_mmu_hdl(video0_fd, size, &cam_packet_handle);\n  pkt->num_cmd_buf = 2;\n  pkt->kmd_cmd_buf_index = -1;\n  pkt->header.op_code = 0x1000003;\n  pkt->header.size = size;\n  struct cam_cmd_buf_desc *buf_desc = (struct cam_cmd_buf_desc *)&pkt->payload;\n\n  buf_desc[0].size = buf_desc[0].length = sizeof(struct cam_cmd_i2c_info) + sizeof(struct cam_cmd_probe);\n  buf_desc[0].type = CAM_CMD_BUF_LEGACY;\n  struct cam_cmd_i2c_info *i2c_info = (struct cam_cmd_i2c_info *)alloc_w_mmu_hdl(video0_fd, buf_desc[0].size, (uint32_t*)&buf_desc[0].mem_handle);\n  struct cam_cmd_probe *probe = (struct cam_cmd_probe *)((uint8_t *)i2c_info) + sizeof(struct cam_cmd_i2c_info);\n\n  switch (camera_num) {\n    case 0:\n      // port 0\n      i2c_info->slave_addr = 0x20;\n      probe->camera_id = 0;\n      break;\n    case 1:\n      // port 1\n      i2c_info->slave_addr = 0x30;\n      probe->camera_id = 1;\n      break;\n    case 2:\n      // port 2\n      i2c_info->slave_addr = 0x20;\n      probe->camera_id = 2;\n      break;\n  }\n\n  // 0(I2C_STANDARD_MODE) = 100khz, 1(I2C_FAST_MODE) = 400khz\n  //i2c_info->i2c_freq_mode = I2C_STANDARD_MODE;\n  i2c_info->i2c_freq_mode = I2C_FAST_MODE;\n  i2c_info->cmd_type = CAMERA_SENSOR_CMD_TYPE_I2C_INFO;\n\n  probe->data_type = CAMERA_SENSOR_I2C_TYPE_WORD;\n  probe->addr_type = CAMERA_SENSOR_I2C_TYPE_WORD;\n  probe->op_code = 3;   // don't care?\n  probe->cmd_type = CAMERA_SENSOR_CMD_TYPE_PROBE;\n  probe->reg_addr = 0x3000; //0x300a; //0x300b;\n  probe->expected_data = 0x354; //0x7750; //0x885a;\n  probe->data_mask = 0;\n\n  //buf_desc[1].size = buf_desc[1].length = 148;\n  buf_desc[1].size = buf_desc[1].length = 196;\n  buf_desc[1].type = CAM_CMD_BUF_I2C;\n  struct cam_cmd_power *power_settings = (struct cam_cmd_power *)alloc_w_mmu_hdl(video0_fd, buf_desc[1].size, (uint32_t*)&buf_desc[1].mem_handle);\n  memset(power_settings, 0, buf_desc[1].size);\n  // 7750\n  /*power->count = 2;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_UP;\n  power->power_settings[0].power_seq_type = 2;\n  power->power_settings[1].power_seq_type = 8;\n  power = (void*)power + (sizeof(struct cam_cmd_power) + (power->count-1)*sizeof(struct cam_power_settings));*/\n\n  // 885a\n  struct cam_cmd_power *power = power_settings;\n  power->count = 4;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_UP;\n  power->power_settings[0].power_seq_type = 3; // clock??\n  power->power_settings[1].power_seq_type = 1; // analog\n  power->power_settings[2].power_seq_type = 2; // digital\n  power->power_settings[3].power_seq_type = 8; // reset low\n  power = power_set_wait(power, 5);\n\n  // set clock\n  power->count = 1;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_UP;\n  power->power_settings[0].power_seq_type = 0;\n  power->power_settings[0].config_val_low = 19200000; //Hz\n  power = power_set_wait(power, 10);\n\n  // 8,1 is this reset?\n  power->count = 1;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_UP;\n  power->power_settings[0].power_seq_type = 8;\n  power->power_settings[0].config_val_low = 1;\n  power = power_set_wait(power, 100);\n\n  // probe happens here\n\n  // disable clock\n  power->count = 1;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_DOWN;\n  power->power_settings[0].power_seq_type = 0;\n  power->power_settings[0].config_val_low = 0;\n  power = power_set_wait(power, 1);\n\n  // reset high\n  power->count = 1;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_DOWN;\n  power->power_settings[0].power_seq_type = 8;\n  power->power_settings[0].config_val_low = 1;\n  power = power_set_wait(power, 1);\n\n  // reset low\n  power->count = 1;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_DOWN;\n  power->power_settings[0].power_seq_type = 8;\n  power->power_settings[0].config_val_low = 0;\n  power = power_set_wait(power, 1);\n\n  // 7750\n  /*power->count = 1;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_DOWN;\n  power->power_settings[0].power_seq_type = 2;\n  power = (void*)power + (sizeof(struct cam_cmd_power) + (power->count-1)*sizeof(struct cam_power_settings));*/\n\n  // 885a\n  power->count = 3;\n  power->cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_DOWN;\n  power->power_settings[0].power_seq_type = 2;\n  power->power_settings[1].power_seq_type = 1;\n  power->power_settings[2].power_seq_type = 3;\n\n  LOGD(\"probing the sensor\");\n  int ret = cam_control(sensor_fd, CAM_SENSOR_PROBE_CMD, (void *)(uintptr_t)cam_packet_handle, 0);\n  assert(ret == 0);\n\n  munmap(i2c_info, buf_desc[0].size);\n  release_fd(video0_fd, buf_desc[0].mem_handle);\n  munmap(power_settings, buf_desc[1].size);\n  release_fd(video0_fd, buf_desc[1].mem_handle);\n  munmap(pkt, size);\n  release_fd(video0_fd, cam_packet_handle);\n}\n\nvoid config_isp(struct CameraState *s, int io_mem_handle, int fence, int request_id, int buf0_mem_handle, int buf0_offset) {\n  uint32_t cam_packet_handle = 0;\n  int size = sizeof(struct cam_packet)+sizeof(struct cam_cmd_buf_desc)*2;\n  if (io_mem_handle != 0) {\n    size += sizeof(struct cam_buf_io_cfg);\n  }\n  struct cam_packet *pkt = (struct cam_packet *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, size, &cam_packet_handle);\n  pkt->num_cmd_buf = 2;\n  pkt->kmd_cmd_buf_index = 0;\n\n  if (io_mem_handle != 0) {\n    pkt->io_configs_offset = sizeof(struct cam_cmd_buf_desc)*2;\n    pkt->num_io_configs = 1;\n  }\n\n  if (io_mem_handle != 0) {\n    pkt->header.op_code = 0xf000001;\n    pkt->header.request_id = request_id;\n  } else {\n    pkt->header.op_code = 0xf000000;\n  }\n  pkt->header.size = size;\n  struct cam_cmd_buf_desc *buf_desc = (struct cam_cmd_buf_desc *)&pkt->payload;\n  struct cam_buf_io_cfg *io_cfg = (struct cam_buf_io_cfg *)((char*)&pkt->payload + pkt->io_configs_offset);\n\n  // TODO: support MMU\n  buf_desc[0].size = 65624;\n  buf_desc[0].length = 0;\n  buf_desc[0].type = CAM_CMD_BUF_DIRECT;\n  buf_desc[0].meta_data = 3;\n  buf_desc[0].mem_handle = buf0_mem_handle;\n  buf_desc[0].offset = buf0_offset;\n\n  buf_desc[1].size = 324;\n\tif (io_mem_handle != 0) {\n    buf_desc[1].length = 228; // 0 works here too\n    buf_desc[1].offset = 0x60;\n\t} else {\n    buf_desc[1].length = 324;\n  }\n  buf_desc[1].type = CAM_CMD_BUF_GENERIC;\n  buf_desc[1].meta_data = CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON;\n  uint32_t *buf2 = (uint32_t *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, buf_desc[1].size, (uint32_t*)&buf_desc[1].mem_handle, 0x20);\n\n  // cam_isp_packet_generic_blob_handler\n  uint32_t tmp[] = {\n    // size is 0x20, type is 0(CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG)\n    0x2000,\n    0x1, 0x0, CAM_ISP_IFE_OUT_RES_RDI_0, 0x1, 0x0, 0x1, 0x0, 0x0, // 1 port, CAM_ISP_IFE_OUT_RES_RDI_0\n    // size is 0x38, type is 1(CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG), clocks\n    0x3801,\n    0x1, 0x4, // Dual mode, 4 RDI wires\n    0x18148d00, 0x0, 0x18148d00, 0x0, 0x18148d00, 0x0, // rdi clock\n    0x0, 0x0, 0x0, 0x0, 0x0, 0x0,  // junk?\n    // offset 0x60\n    // size is 0xe0, type is 2(CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG), bandwidth\n    0xe002,\n    0x1, 0x4, // 4 RDI\n    0x0, 0x0, 0x1ad27480, 0x0, 0x1ad27480, 0x0, // left_pix_vote\n    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, // right_pix_vote\n    0x0, 0x0, 0x6ee11c0, 0x2, 0x6ee11c0, 0x2,  // rdi_vote\n    0x0, 0x0, 0x0, 0x0,\n    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\n    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\n    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\n    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};\n  memcpy(buf2, tmp, sizeof(tmp));\n\n  if (io_mem_handle != 0) {\n    io_cfg[0].mem_handle[0] = io_mem_handle;\n\t\tio_cfg[0].planes[0] = (struct cam_plane_cfg){\n\t\t .width = FRAME_WIDTH,\n\t\t .height = FRAME_HEIGHT,\n\t\t .plane_stride = FRAME_STRIDE,\n\t\t .slice_height = FRAME_HEIGHT,\n\t\t .meta_stride = 0x0,\n\t\t .meta_size = 0x0,\n\t\t .meta_offset = 0x0,\n\t\t .packer_config = 0x0,\n\t\t .mode_config = 0x0,\n\t\t .tile_config = 0x0,\n\t\t .h_init = 0x0,\n\t\t .v_init = 0x0,\n\t\t};\n    io_cfg[0].format = CAM_FORMAT_MIPI_RAW_10;\n    io_cfg[0].color_pattern = 0x5;\n    io_cfg[0].bpp = 0xc;\n    io_cfg[0].resource_type = CAM_ISP_IFE_OUT_RES_RDI_0;\n    io_cfg[0].fence = fence;\n    io_cfg[0].direction = CAM_BUF_OUTPUT;\n    io_cfg[0].subsample_pattern = 0x1;\n    io_cfg[0].framedrop_pattern = 0x1;\n  }\n\n  int ret = device_config(s->multi_cam_state->isp_fd, s->session_handle, s->isp_dev_handle, cam_packet_handle);\n  assert(ret == 0);\n  if (ret != 0) {\n    printf(\"ISP CONFIG FAILED\\n\");\n  }\n\n  munmap(buf2, buf_desc[1].size);\n  release_fd(s->multi_cam_state->video0_fd, buf_desc[1].mem_handle);\n  // release_fd(s->multi_cam_state->video0_fd, buf_desc[0].mem_handle);\n  munmap(pkt, size);\n  release_fd(s->multi_cam_state->video0_fd, cam_packet_handle);\n}\n\nvoid enqueue_buffer(struct CameraState *s, int i, bool dp) {\n  int ret;\n  int request_id = s->request_ids[i];\n\n  if (s->buf_handle[i]) {\n    release(s->multi_cam_state->video0_fd, s->buf_handle[i]);\n    // wait\n    struct cam_sync_wait sync_wait = {0};\n    sync_wait.sync_obj = s->sync_objs[i];\n    sync_wait.timeout_ms = 50; // max dt tolerance, typical should be 23\n    ret = cam_control(s->multi_cam_state->video1_fd, CAM_SYNC_WAIT, &sync_wait, sizeof(sync_wait));\n    // LOGD(\"fence wait: %d %d\", ret, sync_wait.sync_obj);\n\n    s->buf.camera_bufs_metadata[i].timestamp_eof = (uint64_t)nanos_since_boot(); // set true eof\n    if (dp) s->buf.queue(i);\n\n    // destroy old output fence\n    struct cam_sync_info sync_destroy = {0};\n    strcpy(sync_destroy.name, \"NodeOutputPortFence\");\n    sync_destroy.sync_obj = s->sync_objs[i];\n    ret = cam_control(s->multi_cam_state->video1_fd, CAM_SYNC_DESTROY, &sync_destroy, sizeof(sync_destroy));\n    // LOGD(\"fence destroy: %d %d\", ret, sync_destroy.sync_obj);\n  }\n\n  // do stuff\n  struct cam_req_mgr_sched_request req_mgr_sched_request = {0};\n  req_mgr_sched_request.session_hdl = s->session_handle;\n  req_mgr_sched_request.link_hdl = s->link_handle;\n  req_mgr_sched_request.req_id = request_id;\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_SCHED_REQ, &req_mgr_sched_request, sizeof(req_mgr_sched_request));\n  // LOGD(\"sched req: %d %d\", ret, request_id);\n\n  // create output fence\n  struct cam_sync_info sync_create = {0};\n  strcpy(sync_create.name, \"NodeOutputPortFence\");\n  ret = cam_control(s->multi_cam_state->video1_fd, CAM_SYNC_CREATE, &sync_create, sizeof(sync_create));\n  // LOGD(\"fence req: %d %d\", ret, sync_create.sync_obj);\n  s->sync_objs[i] = sync_create.sync_obj;\n\n  // configure ISP to put the image in place\n  struct cam_mem_mgr_map_cmd mem_mgr_map_cmd = {0};\n  mem_mgr_map_cmd.mmu_hdls[0] = s->multi_cam_state->device_iommu;\n  mem_mgr_map_cmd.num_hdl = 1;\n  mem_mgr_map_cmd.flags = CAM_MEM_FLAG_HW_READ_WRITE;\n  mem_mgr_map_cmd.fd = s->buf.camera_bufs[i].fd;\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_MAP_BUF, &mem_mgr_map_cmd, sizeof(mem_mgr_map_cmd));\n  // LOGD(\"map buf req: (fd: %d) 0x%x %d\", s->bufs[i].fd, mem_mgr_map_cmd.out.buf_handle, ret);\n  s->buf_handle[i] = mem_mgr_map_cmd.out.buf_handle;\n\n  // poke sensor\n  sensors_poke(s, request_id);\n  // LOGD(\"Poked sensor\");\n\n  // push the buffer\n  config_isp(s, s->buf_handle[i], s->sync_objs[i], request_id, s->buf0_handle, 65632*(i+1));\n}\n\nvoid enqueue_req_multi(struct CameraState *s, int start, int n, bool dp) {\n   for (int i=start;i<start+n;++i) {\n     s->request_ids[(i - 1) % FRAME_BUF_COUNT] = i;\n     enqueue_buffer(s, (i - 1) % FRAME_BUF_COUNT, dp);\n   }\n}\n\n// ******************* camera *******************\n\nstatic void camera_init(MultiCameraState *multi_cam_state, VisionIpcServer * v, CameraState *s, int camera_id, int camera_num, unsigned int fps, cl_device_id device_id, cl_context ctx, VisionStreamType rgb_type, VisionStreamType yuv_type) {\n  LOGD(\"camera init %d\", camera_num);\n  s->multi_cam_state = multi_cam_state;\n  assert(camera_id < std::size(cameras_supported));\n  s->ci = cameras_supported[camera_id];\n  assert(s->ci.frame_width != 0);\n\n  s->camera_num = camera_num;\n\n  s->request_id_last = 0;\n  s->skipped = true;\n\n  s->min_ev = EXPOSURE_TIME_MIN * sensor_analog_gains[ANALOG_GAIN_MIN_IDX];\n  s->max_ev = EXPOSURE_TIME_MAX * sensor_analog_gains[ANALOG_GAIN_MAX_IDX] * DC_GAIN;\n  s->target_grey_fraction = 0.3;\n\n  s->dc_gain_enabled = false;\n  s->gain_idx = ANALOG_GAIN_REC_IDX;\n  s->exposure_time = 5;\n  s->cur_ev[0] = s->cur_ev[1] = s->cur_ev[2] = (s->dc_gain_enabled ? DC_GAIN : 1) * sensor_analog_gains[s->gain_idx] * s->exposure_time;\n\n  s->buf.init(device_id, ctx, s, v, FRAME_BUF_COUNT, rgb_type, yuv_type);\n}\n\nint open_v4l_by_name_and_index(const char name[], int index, int flags = O_RDWR | O_NONBLOCK) {\n  for (int v4l_index = 0; /**/; ++v4l_index) {\n    std::string v4l_name = util::read_file(util::string_format(\"/sys/class/video4linux/v4l-subdev%d/name\", v4l_index));\n    if (v4l_name.empty()) return -1;\n    if (v4l_name.find(name) == 0) {\n      if (index == 0) {\n        return open(util::string_format(\"/dev/v4l-subdev%d\", v4l_index).c_str(), flags);\n      }\n      index--;\n    }\n  }\n}\n\nstatic void camera_open(CameraState *s) {\n  int ret;\n  s->sensor_fd = open_v4l_by_name_and_index(\"cam-sensor-driver\", s->camera_num);\n  assert(s->sensor_fd >= 0);\n  LOGD(\"opened sensor\");\n\n  s->csiphy_fd = open_v4l_by_name_and_index(\"cam-csiphy-driver\", s->camera_num);\n  assert(s->csiphy_fd >= 0);\n  LOGD(\"opened csiphy\");\n\n  // probe the sensor\n  LOGD(\"-- Probing sensor %d\", s->camera_num);\n  sensors_init(s->multi_cam_state->video0_fd, s->sensor_fd, s->camera_num);\n\n  // create session\n  struct cam_req_mgr_session_info session_info = {}; \n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_CREATE_SESSION, &session_info, sizeof(session_info));\n  LOGD(\"get session: %d 0x%X\", ret, session_info.session_hdl);\n  s->session_handle = session_info.session_hdl;\n\n  // access the sensor\n  LOGD(\"-- Accessing sensor\");\n  auto sensor_dev_handle = device_acquire(s->sensor_fd, s->session_handle, nullptr);\n  assert(sensor_dev_handle);\n  s->sensor_dev_handle = *sensor_dev_handle;\n  LOGD(\"acquire sensor dev\");\n\n  static struct cam_isp_resource isp_resource = {0};\n  isp_resource.resource_id = CAM_ISP_RES_ID_PORT;\n  isp_resource.length = sizeof(struct cam_isp_in_port_info) + sizeof(struct cam_isp_out_port_info)*(1-1);\n  isp_resource.handle_type = CAM_HANDLE_USER_POINTER;\n\n  struct cam_isp_in_port_info *in_port_info = (struct cam_isp_in_port_info *)malloc(isp_resource.length);\n  isp_resource.res_hdl = (uint64_t)in_port_info;\n\n  switch (s->camera_num) {\n    case 0:\n      in_port_info->res_type = CAM_ISP_IFE_IN_RES_PHY_0;\n      break;\n    case 1:\n      in_port_info->res_type = CAM_ISP_IFE_IN_RES_PHY_1;\n      break;\n    case 2:\n      in_port_info->res_type = CAM_ISP_IFE_IN_RES_PHY_2;\n      break;\n  }\n\n  in_port_info->lane_type = CAM_ISP_LANE_TYPE_DPHY;\n  in_port_info->lane_num = 4;\n  in_port_info->lane_cfg = 0x3210;\n\n  in_port_info->vc = 0x0;\n  //in_port_info->dt = 0x2C; //CSI_RAW12\n  //in_port_info->format = CAM_FORMAT_MIPI_RAW_12;\n\n  in_port_info->dt = 0x2B; //CSI_RAW10\n  in_port_info->format = CAM_FORMAT_MIPI_RAW_10;\n\n  in_port_info->test_pattern = 0x2; // 0x3?\n  in_port_info->usage_type = 0x0;\n\n  in_port_info->left_start = 0x0;\n  in_port_info->left_stop = FRAME_WIDTH - 1;\n  in_port_info->left_width = FRAME_WIDTH;\n\n  in_port_info->right_start = 0x0;\n  in_port_info->right_stop = FRAME_WIDTH - 1;\n  in_port_info->right_width = FRAME_WIDTH;\n\n  in_port_info->line_start = 0x0;\n  in_port_info->line_stop = FRAME_HEIGHT - 1;\n  in_port_info->height = FRAME_HEIGHT;\n\n  in_port_info->pixel_clk = 0x0;\n  in_port_info->batch_size = 0x0;\n  in_port_info->dsp_mode = 0x0;\n  in_port_info->hbi_cnt = 0x0;\n  in_port_info->custom_csid = 0x0;\n\n  in_port_info->num_out_res = 0x1;\n  in_port_info->data[0] = (struct cam_isp_out_port_info){\n    .res_type = CAM_ISP_IFE_OUT_RES_RDI_0,\n    //.format = CAM_FORMAT_MIPI_RAW_12,\n    .format = CAM_FORMAT_MIPI_RAW_10,\n    .width = FRAME_WIDTH,\n    .height = FRAME_HEIGHT,\n    .comp_grp_id = 0x0, .split_point = 0x0, .secure_mode = 0x0,\n  };\n\n  auto isp_dev_handle = device_acquire(s->multi_cam_state->isp_fd, s->session_handle, &isp_resource);\n  assert(isp_dev_handle);\n  s->isp_dev_handle = *isp_dev_handle; \n  LOGD(\"acquire isp dev\");\n  free(in_port_info);\n\n  struct cam_csiphy_acquire_dev_info csiphy_acquire_dev_info = {.combo_mode = 0};\n  auto csiphy_dev_handle = device_acquire(s->csiphy_fd, s->session_handle, &csiphy_acquire_dev_info);\n  assert(csiphy_dev_handle);\n  s->csiphy_dev_handle = *csiphy_dev_handle;\n  LOGD(\"acquire csiphy dev\");\n\n  // acquires done\n\n  // config ISP\n  alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, 984480, (uint32_t*)&s->buf0_handle, 0x20, CAM_MEM_FLAG_HW_READ_WRITE | CAM_MEM_FLAG_KMD_ACCESS | CAM_MEM_FLAG_UMD_ACCESS | CAM_MEM_FLAG_CMD_BUF_TYPE, s->multi_cam_state->device_iommu, s->multi_cam_state->cdm_iommu);\n  config_isp(s, 0, 0, 1, s->buf0_handle, 0);\n\n  LOG(\"-- Configuring sensor\");\n  sensors_i2c(s, init_array_ar0231, sizeof(init_array_ar0231)/sizeof(struct i2c_random_wr_payload),\n    CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG);\n  //sensors_i2c(s, start_reg_array, sizeof(start_reg_array)/sizeof(struct i2c_random_wr_payload),\n    //CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON);\n  //sensors_i2c(s, stop_reg_array, sizeof(stop_reg_array)/sizeof(struct i2c_random_wr_payload),\n    //CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF);\n\n  // config csiphy\n  LOG(\"-- Config CSI PHY\");\n  {\n    uint32_t cam_packet_handle = 0;\n    int size = sizeof(struct cam_packet)+sizeof(struct cam_cmd_buf_desc)*1;\n    struct cam_packet *pkt = (struct cam_packet *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, size, &cam_packet_handle);\n    pkt->num_cmd_buf = 1;\n    pkt->kmd_cmd_buf_index = -1;\n    pkt->header.size = size;\n    struct cam_cmd_buf_desc *buf_desc = (struct cam_cmd_buf_desc *)&pkt->payload;\n\n    buf_desc[0].size = buf_desc[0].length = sizeof(struct cam_csiphy_info);\n    buf_desc[0].type = CAM_CMD_BUF_GENERIC;\n\n    struct cam_csiphy_info *csiphy_info = (struct cam_csiphy_info *)alloc_w_mmu_hdl(s->multi_cam_state->video0_fd, buf_desc[0].size, (uint32_t*)&buf_desc[0].mem_handle);\n    csiphy_info->lane_mask = 0x1f;\n    csiphy_info->lane_assign = 0x3210;// skip clk. How is this 16 bit for 5 channels??\n    csiphy_info->csiphy_3phase = 0x0; // no 3 phase, only 2 conductors per lane\n    csiphy_info->combo_mode = 0x0;\n    csiphy_info->lane_cnt = 0x4;\n    csiphy_info->secure_mode = 0x0;\n    csiphy_info->settle_time = MIPI_SETTLE_CNT * 200000000ULL;\n    csiphy_info->data_rate = 48000000;  // Calculated by camera_freqs.py\n\n    int ret = device_config(s->csiphy_fd, s->session_handle, s->csiphy_dev_handle, cam_packet_handle);\n    assert(ret == 0);\n\n    munmap(csiphy_info, buf_desc[0].size);\n    release_fd(s->multi_cam_state->video0_fd, buf_desc[0].mem_handle);\n    munmap(pkt, size);\n    release_fd(s->multi_cam_state->video0_fd, cam_packet_handle);\n  }\n\n  // link devices\n  LOG(\"-- Link devices\");\n  static struct cam_req_mgr_link_info req_mgr_link_info = {0};\n  req_mgr_link_info.session_hdl = s->session_handle;\n  req_mgr_link_info.num_devices = 2;\n  req_mgr_link_info.dev_hdls[0] = s->isp_dev_handle;\n  req_mgr_link_info.dev_hdls[1] = s->sensor_dev_handle;\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_LINK, &req_mgr_link_info, sizeof(req_mgr_link_info));\n  LOGD(\"link: %d\", ret);\n  s->link_handle = req_mgr_link_info.link_hdl;\n\n  static struct cam_req_mgr_link_control req_mgr_link_control = {0};\n  req_mgr_link_control.ops = CAM_REQ_MGR_LINK_ACTIVATE;\n  req_mgr_link_control.session_hdl = s->session_handle;\n  req_mgr_link_control.num_links = 1;\n  req_mgr_link_control.link_hdls[0] = s->link_handle;\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_LINK_CONTROL, &req_mgr_link_control, sizeof(req_mgr_link_control));\n  LOGD(\"link control: %d\", ret);\n\n  ret = device_control(s->csiphy_fd, CAM_START_DEV, s->session_handle, s->csiphy_dev_handle);\n  LOGD(\"start csiphy: %d\", ret);\n  ret = device_control(s->multi_cam_state->isp_fd, CAM_START_DEV, s->session_handle, s->isp_dev_handle);\n  LOGD(\"start isp: %d\", ret);\n  ret = device_control(s->sensor_fd, CAM_START_DEV, s->session_handle, s->sensor_dev_handle);\n  LOGD(\"start sensor: %d\", ret);\n\n  enqueue_req_multi(s, 1, FRAME_BUF_COUNT, 0);\n}\n\nvoid cameras_init(VisionIpcServer *v, MultiCameraState *s, cl_device_id device_id, cl_context ctx) {\n  camera_init(s, v, &s->road_cam, CAMERA_ID_AR0231, 1, 20, device_id, ctx,\n              VISION_STREAM_RGB_BACK, VISION_STREAM_YUV_BACK); // swap left/right\n  printf(\"road camera initted \\n\");\n  camera_init(s, v, &s->wide_road_cam, CAMERA_ID_AR0231, 0, 20, device_id, ctx,\n              VISION_STREAM_RGB_WIDE, VISION_STREAM_YUV_WIDE);\n  printf(\"wide road camera initted \\n\");\n  camera_init(s, v, &s->driver_cam, CAMERA_ID_AR0231, 2, 20, device_id, ctx,\n              VISION_STREAM_RGB_FRONT, VISION_STREAM_YUV_FRONT);\n  printf(\"driver camera initted \\n\");\n\n  s->sm = new SubMaster({\"driverState\"});\n  s->pm = new PubMaster({\"roadCameraState\", \"driverCameraState\", \"wideRoadCameraState\", \"thumbnail\"});\n}\n\nvoid cameras_open(MultiCameraState *s) {\n  int ret;\n\n  LOG(\"-- Opening devices\");\n  // video0 is req_mgr, the target of many ioctls\n  s->video0_fd = HANDLE_EINTR(open(\"/dev/v4l/by-path/platform-soc:qcom_cam-req-mgr-video-index0\", O_RDWR | O_NONBLOCK));\n  assert(s->video0_fd >= 0);\n  LOGD(\"opened video0\");\n\n  // video1 is cam_sync, the target of some ioctls\n  s->video1_fd = HANDLE_EINTR(open(\"/dev/v4l/by-path/platform-cam_sync-video-index0\", O_RDWR | O_NONBLOCK));\n  assert(s->video1_fd >= 0);\n  LOGD(\"opened video1\");\n\n  // looks like there's only one of these\n  s->isp_fd = HANDLE_EINTR(open(\"/dev/v4l-subdev1\", O_RDWR | O_NONBLOCK));\n  assert(s->isp_fd >= 0);\n  LOGD(\"opened isp\");\n\n  // query icp for MMU handles\n  LOG(\"-- Query ICP for MMU handles\");\n  static struct cam_isp_query_cap_cmd isp_query_cap_cmd = {0};\n  static struct cam_query_cap_cmd query_cap_cmd = {0};\n  query_cap_cmd.handle_type = 1;\n  query_cap_cmd.caps_handle = (uint64_t)&isp_query_cap_cmd;\n  query_cap_cmd.size = sizeof(isp_query_cap_cmd);\n  ret = cam_control(s->isp_fd, CAM_QUERY_CAP, &query_cap_cmd, sizeof(query_cap_cmd));\n  assert(ret == 0);\n  LOGD(\"using MMU handle: %x\", isp_query_cap_cmd.device_iommu.non_secure);\n  LOGD(\"using MMU handle: %x\", isp_query_cap_cmd.cdm_iommu.non_secure);\n  s->device_iommu = isp_query_cap_cmd.device_iommu.non_secure;\n  s->cdm_iommu = isp_query_cap_cmd.cdm_iommu.non_secure;\n\n  // subscribe\n  LOG(\"-- Subscribing\");\n  static struct v4l2_event_subscription sub = {0};\n  sub.type = V4L_EVENT_CAM_REQ_MGR_EVENT;\n  sub.id = 2; // should use boot time for sof\n  ret = HANDLE_EINTR(ioctl(s->video0_fd, VIDIOC_SUBSCRIBE_EVENT, &sub));\n  printf(\"req mgr subscribe: %d\\n\", ret);\n\n  camera_open(&s->road_cam);\n  printf(\"road camera opened \\n\");\n  camera_open(&s->wide_road_cam);\n  printf(\"wide road camera opened \\n\");\n  camera_open(&s->driver_cam);\n  printf(\"driver camera opened \\n\");\n}\n\nstatic void camera_close(CameraState *s) {\n  int ret;\n\n  // stop devices\n  LOG(\"-- Stop devices\");\n  // ret = device_control(s->sensor_fd, CAM_STOP_DEV, s->session_handle, s->sensor_dev_handle);\n  // LOGD(\"stop sensor: %d\", ret);\n  ret = device_control(s->multi_cam_state->isp_fd, CAM_STOP_DEV, s->session_handle, s->isp_dev_handle);\n  LOGD(\"stop isp: %d\", ret);\n  ret = device_control(s->csiphy_fd, CAM_STOP_DEV, s->session_handle, s->csiphy_dev_handle);\n  LOGD(\"stop csiphy: %d\", ret);\n  // link control stop\n  LOG(\"-- Stop link control\");\n  static struct cam_req_mgr_link_control req_mgr_link_control = {0};\n  req_mgr_link_control.ops = CAM_REQ_MGR_LINK_DEACTIVATE;\n  req_mgr_link_control.session_hdl = s->session_handle;\n  req_mgr_link_control.num_links = 1;\n  req_mgr_link_control.link_hdls[0] = s->link_handle;\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_LINK_CONTROL, &req_mgr_link_control, sizeof(req_mgr_link_control));\n  LOGD(\"link control stop: %d\", ret);\n\n  // unlink\n  LOG(\"-- Unlink\");\n  static struct cam_req_mgr_unlink_info req_mgr_unlink_info = {0};\n  req_mgr_unlink_info.session_hdl = s->session_handle;\n  req_mgr_unlink_info.link_hdl = s->link_handle;\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_UNLINK, &req_mgr_unlink_info, sizeof(req_mgr_unlink_info));\n  LOGD(\"unlink: %d\", ret);\n\n  // release devices\n  LOGD(\"-- Release devices\");\n  ret = device_control(s->sensor_fd, CAM_RELEASE_DEV, s->session_handle, s->sensor_dev_handle);\n  LOGD(\"release sensor: %d\", ret);\n  ret = device_control(s->multi_cam_state->isp_fd, CAM_RELEASE_DEV, s->session_handle, s->isp_dev_handle);\n  LOGD(\"release isp: %d\", ret);\n  ret = device_control(s->csiphy_fd, CAM_RELEASE_DEV, s->session_handle, s->csiphy_dev_handle);\n  LOGD(\"release csiphy: %d\", ret);\n\n  // destroyed session\n  struct cam_req_mgr_session_info session_info = {.session_hdl = s->session_handle};\n  ret = cam_control(s->multi_cam_state->video0_fd, CAM_REQ_MGR_DESTROY_SESSION, &session_info, sizeof(session_info));\n  LOGD(\"destroyed session: %d\", ret);\n}\n\nvoid cameras_close(MultiCameraState *s) {\n  camera_close(&s->road_cam);\n  camera_close(&s->wide_road_cam);\n  camera_close(&s->driver_cam);\n\n  delete s->sm;\n  delete s->pm;\n}\n\n// ******************* just a helper *******************\n\nvoid handle_camera_event(CameraState *s, void *evdat) {\n  struct cam_req_mgr_message *event_data = (struct cam_req_mgr_message *)evdat;\n\n  uint64_t timestamp = event_data->u.frame_msg.timestamp;\n  int main_id = event_data->u.frame_msg.frame_id;\n  int real_id = event_data->u.frame_msg.request_id;\n\n  if (real_id != 0) { // next ready\n    if (real_id == 1) {s->idx_offset = main_id;}\n    int buf_idx = (real_id - 1) % FRAME_BUF_COUNT;\n\n    // check for skipped frames\n    if (main_id > s->frame_id_last + 1 && !s->skipped) {\n      // realign\n      clear_req_queue(s->multi_cam_state->video0_fd, event_data->session_hdl, event_data->u.frame_msg.link_hdl);\n      enqueue_req_multi(s, real_id + 1, FRAME_BUF_COUNT - 1, 0);\n      s->skipped = true;\n    } else if (main_id == s->frame_id_last + 1) {\n      s->skipped = false;\n    }\n\n    // check for dropped requests\n    if (real_id > s->request_id_last + 1) {\n      enqueue_req_multi(s, s->request_id_last + 1 + FRAME_BUF_COUNT, real_id - (s->request_id_last + 1), 0);\n    }\n\n    // metas\n    s->frame_id_last = main_id;\n    s->request_id_last = real_id;\n\n    auto &meta_data = s->buf.camera_bufs_metadata[buf_idx];\n    meta_data.frame_id = main_id - s->idx_offset;\n    meta_data.timestamp_sof = timestamp;\n    s->exp_lock.lock();\n    meta_data.gain = s->dc_gain_enabled ? s->analog_gain_frac * DC_GAIN : s->analog_gain_frac;\n    meta_data.high_conversion_gain = s->dc_gain_enabled;\n    meta_data.integ_lines = s->exposure_time;\n    meta_data.measured_grey_fraction = s->measured_grey_fraction;\n    meta_data.target_grey_fraction = s->target_grey_fraction;\n    s->exp_lock.unlock();\n\n    // dispatch\n    enqueue_req_multi(s, real_id + FRAME_BUF_COUNT, 1, 1);\n  } else { // not ready\n    // reset after half second of no response\n    if (main_id > s->frame_id_last + 10) {\n      clear_req_queue(s->multi_cam_state->video0_fd, event_data->session_hdl, event_data->u.frame_msg.link_hdl);\n      enqueue_req_multi(s, s->request_id_last + 1, FRAME_BUF_COUNT, 0);\n      s->frame_id_last = main_id;\n      s->skipped = true;\n    }\n  }\n}\n\nstatic void set_camera_exposure(CameraState *s, float grey_frac) {\n  const float dt = 0.05;\n\n  const float ts_grey = 10.0;\n  const float ts_ev = 0.05;\n\n  const float k_grey = (dt / ts_grey) / (1.0 + dt / ts_grey);\n  const float k_ev = (dt / ts_ev) / (1.0 + dt / ts_ev);\n\n  // It takes 3 frames for the commanded exposure settings to take effect. The first frame is already started by the time\n  // we reach this function, the other 2 are due to the register buffering in the sensor.\n  // Therefore we use the target EV from 3 frames ago, the grey fraction that was just measured was the result of that control action.\n  // TODO: Lower latency to 2 frames, by using the histogram outputed by the sensor we can do AE before the debayering is complete\n\n  const float cur_ev = s->cur_ev[s->buf.cur_frame_data.frame_id % 3];\n\n  // Scale target grey between 0.1 and 0.4 depending on lighting conditions\n  float new_target_grey = std::clamp(0.4 - 0.3 * log2(1.0 + cur_ev) / log2(6000.0), 0.1, 0.4);\n  float target_grey = (1.0 - k_grey) * s->target_grey_fraction + k_grey * new_target_grey;\n\n  float desired_ev = std::clamp(cur_ev * target_grey / grey_frac, s->min_ev, s->max_ev);\n  float k = (1.0 - k_ev) / 3.0;\n  desired_ev = (k * s->cur_ev[0]) + (k * s->cur_ev[1]) + (k * s->cur_ev[2]) + (k_ev * desired_ev);\n\n  float best_ev_score = 1e6;\n  int new_g = 0;\n  int new_t = 0;\n\n  // Hysteresis around high conversion gain\n  // We usually want this on since it results in lower noise, but turn off in very bright day scenes\n  bool enable_dc_gain = s->dc_gain_enabled;\n  if (!enable_dc_gain && target_grey < 0.2) {\n    enable_dc_gain = true;\n  } else if (enable_dc_gain && target_grey > 0.3) {\n    enable_dc_gain = false;\n  }\n\n  // Simple brute force optimizer to choose sensor parameters\n  // to reach desired EV\n  for (int g = std::max((int)ANALOG_GAIN_MIN_IDX, s->gain_idx - 1); g <= std::min((int)ANALOG_GAIN_MAX_IDX, s->gain_idx + 1); g++) {\n    float gain = sensor_analog_gains[g] * (enable_dc_gain ? DC_GAIN : 1);\n\n    // Compute optimal time for given gain\n    int t = std::clamp(int(std::round(desired_ev / gain)), EXPOSURE_TIME_MIN, EXPOSURE_TIME_MAX);\n\n    // Only go below recomended gain when absolutely necessary to not overexpose\n    if (g < ANALOG_GAIN_REC_IDX && t > 20 && g < s->gain_idx) {\n      continue;\n    }\n\n    // Compute error to desired ev\n    float score = std::abs(desired_ev - (t * gain)) * 10;\n\n    // Going below recomended gain needs lower penalty to not overexpose\n    float m = g > ANALOG_GAIN_REC_IDX ? 5.0 : 0.1;\n    score += std::abs(g - (int)ANALOG_GAIN_REC_IDX) * m;\n\n    // LOGE(\"cam: %d - gain: %d, t: %d (%.2f), score %.2f, score + gain %.2f, %.3f, %.3f\", s->camera_num, g, t, desired_ev / gain, score, score + std::abs(g - s->gain_idx) * (score + 1.0) / 10.0, desired_ev, s->min_ev);\n\n    // Small penalty on changing gain\n    score += std::abs(g - s->gain_idx) * (score + 1.0) / 10.0;\n\n    if (score < best_ev_score) {\n      new_t = t;\n      new_g = g;\n      best_ev_score = score;\n    }\n  }\n\n  s->exp_lock.lock();\n\n  s->measured_grey_fraction = grey_frac;\n  s->target_grey_fraction = target_grey;\n\n  s->analog_gain_frac = sensor_analog_gains[new_g];\n  s->gain_idx = new_g;\n  s->exposure_time = new_t;\n  s->dc_gain_enabled = enable_dc_gain;\n\n  float gain = s->analog_gain_frac * (s->dc_gain_enabled ? DC_GAIN : 1.0);\n  s->cur_ev[s->buf.cur_frame_data.frame_id % 3] = s->exposure_time * gain;\n\n  s->exp_lock.unlock();\n\n  // Processing a frame takes right about 50ms, so we need to wait a few ms\n  // so we don't send i2c commands around the frame start.\n  int ms = (nanos_since_boot() - s->buf.cur_frame_data.timestamp_sof) / 1000000;\n  if (ms < 60) {\n    util::sleep_for(60 - ms);\n  }\n  // LOGE(\"ae - camera %d, cur_t %.5f, sof %.5f, dt %.5f\", s->camera_num, 1e-9 * nanos_since_boot(), 1e-9 * s->buf.cur_frame_data.timestamp_sof, 1e-9 * (nanos_since_boot() - s->buf.cur_frame_data.timestamp_sof));\n\n  uint16_t analog_gain_reg = 0xFF00 | (new_g << 4) | new_g;\n  struct i2c_random_wr_payload exp_reg_array[] = {\n                                                  {0x3366, analog_gain_reg},\n                                                  {0x3362, (uint16_t)(s->dc_gain_enabled ? 0x1 : 0x0)},\n                                                  {0x3012, (uint16_t)s->exposure_time},\n                                                };\n  sensors_i2c(s, exp_reg_array, sizeof(exp_reg_array)/sizeof(struct i2c_random_wr_payload),\n              CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG);\n\n}\n\nvoid camera_autoexposure(CameraState *s, float grey_frac) {\n  set_camera_exposure(s, grey_frac);\n}\n\n\nvoid process_driver_camera(MultiCameraState *s, CameraState *c, int cnt) {\n  common_process_driver_camera(s->sm, s->pm, c, cnt);\n}\n\n// called by processing_thread\nvoid process_road_camera(MultiCameraState *s, CameraState *c, int cnt) {\n  const CameraBuf *b = &c->buf;\n\n  MessageBuilder msg;\n  auto framed = c == &s->road_cam ? msg.initEvent().initRoadCameraState() : msg.initEvent().initWideRoadCameraState();\n  fill_frame_data(framed, b->cur_frame_data);\n  if ((c == &s->road_cam && env_send_road) || (c == &s->wide_road_cam && env_send_wide_road)) {\n    framed.setImage(get_frame_image(b));\n  }\n  if (c == &s->road_cam) {\n    framed.setTransform(b->yuv_transform.v);\n  }\n  s->pm->send(c == &s->road_cam ? \"roadCameraState\" : \"wideRoadCameraState\", msg);\n\n  const auto [x, y, w, h] = (c == &s->wide_road_cam) ? std::tuple(96, 250, 1734, 524) : std::tuple(96, 160, 1734, 986);\n  const int skip = 2;\n  camera_autoexposure(c, set_exposure_target(b, x, x + w, skip, y, y + h, skip));\n}\n\nvoid cameras_run(MultiCameraState *s) {\n  LOG(\"-- Starting threads\");\n  std::vector<std::thread> threads;\n  threads.push_back(start_process_thread(s, &s->road_cam, process_road_camera));\n  threads.push_back(start_process_thread(s, &s->driver_cam, process_driver_camera));\n  threads.push_back(start_process_thread(s, &s->wide_road_cam, process_road_camera));\n\n  // start devices\n  LOG(\"-- Starting devices\");\n  int start_reg_len = sizeof(start_reg_array) / sizeof(struct i2c_random_wr_payload);\n  sensors_i2c(&s->road_cam, start_reg_array, start_reg_len, CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG);\n  sensors_i2c(&s->wide_road_cam, start_reg_array, start_reg_len, CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG);\n  sensors_i2c(&s->driver_cam, start_reg_array, start_reg_len, CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG);\n\n  // poll events\n  LOG(\"-- Dequeueing Video events\");\n  while (!do_exit) {\n    struct pollfd fds[1] = {{0}};\n\n    fds[0].fd = s->video0_fd;\n    fds[0].events = POLLPRI;\n\n    int ret = poll(fds, std::size(fds), 1000);\n    if (ret < 0) {\n      if (errno == EINTR || errno == EAGAIN) continue;\n      LOGE(\"poll failed (%d - %d)\", ret, errno);\n      break;\n    }\n\n    if (!fds[0].revents) continue;\n\n    struct v4l2_event ev = {0};\n    ret = HANDLE_EINTR(ioctl(fds[0].fd, VIDIOC_DQEVENT, &ev));\n    if (ret == 0) {\n      if (ev.type == V4L_EVENT_CAM_REQ_MGR_EVENT) {\n        struct cam_req_mgr_message *event_data = (struct cam_req_mgr_message *)ev.u.data;\n        // LOGD(\"v4l2 event: sess_hdl %d, link_hdl %d, frame_id %d, req_id %lld, timestamp 0x%llx, sof_status %d\\n\", event_data->session_hdl, event_data->u.frame_msg.link_hdl, event_data->u.frame_msg.frame_id, event_data->u.frame_msg.request_id, event_data->u.frame_msg.timestamp, event_data->u.frame_msg.sof_status);\n        // printf(\"sess_hdl %d, link_hdl %d, frame_id %lu, req_id %lu, timestamp 0x%lx, sof_status %d\\n\", event_data->session_hdl, event_data->u.frame_msg.link_hdl, event_data->u.frame_msg.frame_id, event_data->u.frame_msg.request_id, event_data->u.frame_msg.timestamp, event_data->u.frame_msg.sof_status);\n\n        if (event_data->session_hdl == s->road_cam.session_handle) {\n          handle_camera_event(&s->road_cam, event_data);\n        } else if (event_data->session_hdl == s->wide_road_cam.session_handle) {\n          handle_camera_event(&s->wide_road_cam, event_data);\n        } else if (event_data->session_hdl == s->driver_cam.session_handle) {\n          handle_camera_event(&s->driver_cam, event_data);\n        } else {\n          printf(\"Unknown vidioc event source\\n\");\n          assert(false);\n        }\n      }\n    } else {\n      LOGE(\"VIDIOC_DQEVENT failed, errno=%d\", errno);\n    }\n  }\n\n  LOG(\" ************** STOPPING **************\");\n\n  for (auto &t : threads) t.join();\n\n  cameras_close(s);\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/camera_qcom2.h",
    "content": "#pragma once\n\n#include <cstdint>\n\n#include <media/cam_req_mgr.h>\n\n#include \"selfdrive/camerad/cameras/camera_common.h\"\n#include \"selfdrive/common/util.h\"\n\n#define FRAME_BUF_COUNT 4\n#define DEBAYER_LOCAL_WORKSIZE 16\ntypedef struct CameraState {\n  MultiCameraState *multi_cam_state;\n  CameraInfo ci;\n\n  std::mutex exp_lock;\n\n  int exposure_time;\n  bool dc_gain_enabled;\n  float analog_gain_frac;\n\n  float cur_ev[3];\n  float min_ev, max_ev;\n\n  float measured_grey_fraction;\n  float target_grey_fraction;\n  int gain_idx;\n\n  unique_fd sensor_fd;\n  unique_fd csiphy_fd;\n\n  int camera_num;\n\n  int32_t session_handle;\n  int32_t sensor_dev_handle;\n  int32_t isp_dev_handle;\n  int32_t csiphy_dev_handle;\n\n  int32_t link_handle;\n\n  int buf0_handle;\n  int buf_handle[FRAME_BUF_COUNT];\n  int sync_objs[FRAME_BUF_COUNT];\n  int request_ids[FRAME_BUF_COUNT];\n  int request_id_last;\n  int frame_id_last;\n  int idx_offset;\n  bool skipped;\n\n  CameraBuf buf;\n} CameraState;\n\ntypedef struct MultiCameraState {\n  unique_fd video0_fd;\n  unique_fd video1_fd;\n  unique_fd isp_fd;\n  int device_iommu;\n  int cdm_iommu;\n\n\n  CameraState road_cam;\n  CameraState wide_road_cam;\n  CameraState driver_cam;\n\n  SubMaster *sm;\n  PubMaster *pm;\n} MultiCameraState;\n"
  },
  {
    "path": "selfdrive/camerad/cameras/debayer.cl",
    "content": "const __constant float3 color_correction[3] = {\n  // Matrix from WBraw -> sRGBD65 (normalized)\n  (float3)( 1.62393627, -0.2092988,  0.00119886),\n  (float3)(-0.45734315,  1.5534676, -0.59296798),\n  (float3)(-0.16659312, -0.3441688,  1.59176912),\n};\n\nfloat3 color_correct(float3 x) {\n  float3 ret = (0,0,0);\n\n  // white balance of daylight\n  x /= (float3)(0.4609375, 1.0, 0.546875);\n  x = max(0.0, min(1.0, x));\n\n  // fix up the colors\n  ret += x.x * color_correction[0];\n  ret += x.y * color_correction[1];\n  ret += x.z * color_correction[2];\n  return ret;\n}\n\nfloat3 srgb_gamma(float3 p) {\n  // go all out and add an sRGB gamma curve\n  const float3 ph = (1.0f + 0.055f)*pow(p, 1/2.4f) - 0.055f;\n\tconst float3 pl = p*12.92f;\n\treturn select(ph, pl, islessequal(p, 0.0031308f));\n}\n\n__constant int dpcm_lookup[512] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16, -17, -18, -19, -20, -21, -22, -23, -24, -25, -26, -27, -28, -29, -30, -31, 935, 951, 967, 983, 999, 1015, 1031, 1047, 1063, 1079, 1095, 1111, 1127, 1143, 1159, 1175, 1191, 1207, 1223, 1239, 1255, 1271, 1287, 1303, 1319, 1335, 1351, 1367, 1383, 1399, 1415, 1431, -935, -951, -967, -983, -999, -1015, -1031, -1047, -1063, -1079, -1095, -1111, -1127, -1143, -1159, -1175, -1191, -1207, -1223, -1239, -1255, -1271, -1287, -1303, -1319, -1335, -1351, -1367, -1383, -1399, -1415, -1431, 419, 427, 435, 443, 451, 459, 467, 475, 483, 491, 499, 507, 515, 523, 531, 539, 547, 555, 563, 571, 579, 587, 595, 603, 611, 619, 627, 635, 643, 651, 659, 667, 675, 683, 691, 699, 707, 715, 723, 731, 739, 747, 755, 763, 771, 779, 787, 795, 803, 811, 819, 827, 835, 843, 851, 859, 867, 875, 883, 891, 899, 907, 915, 923, -419, -427, -435, -443, -451, -459, -467, -475, -483, -491, -499, -507, -515, -523, -531, -539, -547, -555, -563, -571, -579, -587, -595, -603, -611, -619, -627, -635, -643, -651, -659, -667, -675, -683, -691, -699, -707, -715, -723, -731, -739, -747, -755, -763, -771, -779, -787, -795, -803, -811, -819, -827, -835, -843, -851, -859, -867, -875, -883, -891, -899, -907, -915, -923, 161, 165, 169, 173, 177, 181, 185, 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253, 257, 261, 265, 269, 273, 277, 281, 285, 289, 293, 297, 301, 305, 309, 313, 317, 321, 325, 329, 333, 337, 341, 345, 349, 353, 357, 361, 365, 369, 373, 377, 381, 385, 389, 393, 397, 401, 405, 409, 413, -161, -165, -169, -173, -177, -181, -185, -189, -193, -197, -201, -205, -209, -213, -217, -221, -225, -229, -233, -237, -241, -245, -249, -253, -257, -261, -265, -269, -273, -277, -281, -285, -289, -293, -297, -301, -305, -309, -313, -317, -321, -325, -329, -333, -337, -341, -345, -349, -353, -357, -361, -365, -369, -373, -377, -381, -385, -389, -393, -397, -401, -405, -409, -413, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, -32, -34, -36, -38, -40, -42, -44, -46, -48, -50, -52, -54, -56, -58, -60, -62, -64, -66, -68, -70, -72, -74, -76, -78, -80, -82, -84, -86, -88, -90, -92, -94, -96, -98, -100, -102, -104, -106, -108, -110, -112, -114, -116, -118, -120, -122, -124, -126, -128, -130, -132, -134, -136, -138, -140, -142, -144, -146, -148, -150, -152, -154, -156, -158};\n\ninline uint4 decompress(uint4 p, uint4 pl) {\n  uint4 r1 = (pl + (uint4)(dpcm_lookup[p.s0], dpcm_lookup[p.s1], dpcm_lookup[p.s2], dpcm_lookup[p.s3]));\n  uint4 r2 = ((p-0x200)<<5) | 0xF;\n  r2 += select((uint4)(0,0,0,0), (uint4)(1,1,1,1), r2 <= pl);\n  return select(r2, r1, p < 0x200);\n}\n\n__kernel void debayer10(__global uchar const * const in,\n                        __global uchar * out, float digital_gain)\n{\n  const int oy = get_global_id(0);\n  if (oy >= RGB_HEIGHT) return;\n  const int iy = oy * 2;\n\n  uint4 pint_last;\n  for (int ox = 0; ox < RGB_WIDTH; ox += 2) {\n    const int ix = (ox/2) * 5;\n\n    // TODO: why doesn't this work for the frontview\n    /*const uchar8 v1 = vload8(0, &in[iy * FRAME_STRIDE + ix]);\n    const uchar ex1 = v1.s4;\n    const uchar8 v2 = vload8(0, &in[(iy+1) * FRAME_STRIDE + ix]);\n    const uchar ex2 = v2.s4;*/\n\n    const uchar4 v1 = vload4(0, &in[iy * FRAME_STRIDE + ix]);\n    const uchar ex1 = in[iy * FRAME_STRIDE + ix + 4];\n    const uchar4 v2 = vload4(0, &in[(iy+1) * FRAME_STRIDE + ix]);\n    const uchar ex2 = in[(iy+1) * FRAME_STRIDE + ix + 4];\n\n    uint4 pinta[2];\n    pinta[0] = (uint4)(\n      (((uint)v1.s0 << 2) + ( (ex1 >> 0) & 3)),\n      (((uint)v1.s1 << 2) + ( (ex1 >> 2) & 3)),\n      (((uint)v2.s0 << 2) + ( (ex2 >> 0) & 3)),\n      (((uint)v2.s1 << 2) + ( (ex2 >> 2) & 3)));\n    pinta[1] = (uint4)(\n      (((uint)v1.s2 << 2) + ( (ex1 >> 4) & 3)),\n      (((uint)v1.s3 << 2) + ( (ex1 >> 6) & 3)),\n      (((uint)v2.s2 << 2) + ( (ex2 >> 4) & 3)),\n      (((uint)v2.s3 << 2) + ( (ex2 >> 6) & 3)));\n\n    #pragma unroll\n    for (uint px = 0; px < 2; px++) {\n      uint4 pint = pinta[px];\n\n#if HDR\n      // decompress HDR\n      pint = (ox == 0 && px == 0) ? ((pint<<4) | 8) : decompress(pint, pint_last);\n      pint_last = pint;\n#endif\n\n      float4 p = convert_float4(pint);\n\n      // 64 is the black level of the sensor, remove\n      // (changed to 56 for HDR)\n      const float black_level = 56.0f;\n      // TODO: switch to max here?\n      p = (p - black_level);\n\n      // correct vignetting (no pow function?)\n      // see https://www.eecis.udel.edu/~jye/lab_research/09/JiUp.pdf the A (4th order)\n      const float r = ((oy - RGB_HEIGHT/2)*(oy - RGB_HEIGHT/2) + (ox - RGB_WIDTH/2)*(ox - RGB_WIDTH/2));\n      const float fake_f = 700.0f;    // should be 910, but this fits...\n      const float lil_a = (1.0f + r/(fake_f*fake_f));\n      p = p * lil_a * lil_a;\n\n      // rescale to 1.0\n#if HDR\n      p /= (16384.0f-black_level);\n#else\n      p /= (1024.0f-black_level);\n#endif\n\n      // digital gain\n      p *= digital_gain;\n\n      // use both green channels\n#if BAYER_FLIP == 3\n      float3 c1 = (float3)(p.s3, (p.s1+p.s2)/2.0f, p.s0);\n#elif BAYER_FLIP == 2\n      float3 c1 = (float3)(p.s2, (p.s0+p.s3)/2.0f, p.s1);\n#elif BAYER_FLIP == 1\n      float3 c1 = (float3)(p.s1, (p.s0+p.s3)/2.0f, p.s2);\n#elif BAYER_FLIP == 0\n      float3 c1 = (float3)(p.s0, (p.s1+p.s2)/2.0f, p.s3);\n#endif\n\n      // color correction\n      c1 = color_correct(c1);\n\n#if HDR\n      // srgb gamma isn't right for YUV, so it's disabled for now\n      c1 = srgb_gamma(c1);\n#endif\n\n      // output BGR\n      const int ooff = oy * RGB_STRIDE/3 + ox;\n      vstore3(convert_uchar3_sat(c1.zyx * 255.0f), ooff+px, out);\n    }\n  }\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/real_debayer.cl",
    "content": "#pragma OPENCL EXTENSION cl_khr_fp16 : enable\n\nconst half black_level = 42.0;\n\nconst __constant half3 color_correction[3] = {\n  // post wb CCM\n  (half3)(1.82717181, -0.31231438, 0.07307673),\n  (half3)(-0.5743977, 1.36858544, -0.53183455),\n  (half3)(-0.25277411, -0.05627105, 1.45875782),\n};\n\n// tone mapping params\nconst half cpk = 0.75;\nconst half cpb = 0.125;\nconst half cpxk = 0.0025;\nconst half cpxb = 0.01;\n\nhalf mf(half x, half cp) {\n  half rk = 9 - 100*cp;\n  if (x > cp) {\n    return (rk * (x-cp) * (1-(cpk*cp+cpb)) * (1+1/(rk*(1-cp))) / (1+rk*(x-cp))) + cpk*cp + cpb;\n  } else if (x < cp) {\n    return (rk * (x-cp) * (cpk*cp+cpb) * (1+1/(rk*cp)) / (1-rk*(x-cp))) + cpk*cp + cpb;\n  } else {\n    return x;\n  }\n}\n\nhalf3 color_correct(half3 rgb) {\n  half3 ret = (0,0,0);\n  half cpx = 0.01;\n  ret += (half)rgb.x * color_correction[0];\n  ret += (half)rgb.y * color_correction[1];\n  ret += (half)rgb.z * color_correction[2];\n  ret.x = mf(ret.x, cpx);\n  ret.y = mf(ret.y, cpx);\n  ret.z = mf(ret.z, cpx);\n  ret = clamp(0.0h, 255.0h, ret*255.0h);\n  return ret;\n}\n\nhalf val_from_10(const uchar * source, int gx, int gy) {\n  // parse 10bit\n  int start = gy * FRAME_STRIDE + (5 * (gx / 4));\n  int offset = gx % 4;\n  uint major = (uint)source[start + offset] << 2;\n  uint minor = (source[start + 4] >> (2 * offset)) & 3;\n  half pv = (half)(major + minor);\n\n  // normalize\n  pv = max(0.0h, pv - black_level);\n  pv *= 0.00101833h; // /= (1024.0f - black_level);\n\n  // correct vignetting\n  if (CAM_NUM == 1) { // fcamera\n    gx = (gx - RGB_WIDTH/2);\n    gy = (gy - RGB_HEIGHT/2);\n    float r = gx*gx + gy*gy;\n    half s;\n    if (r < 62500) {\n      s = (half)(1.0f + 0.0000008f*r);\n    } else if (r < 490000) {\n      s = (half)(0.9625f + 0.0000014f*r);\n    } else if (r < 1102500) {\n      s = (half)(1.26434f + 0.0000000000016f*r*r);\n    } else {\n      s = (half)(0.53503625f + 0.0000000000022f*r*r);\n    }\n    pv = s * pv;\n  }\n\n  pv = clamp(0.0h, 1.0h, pv);\n  return pv;\n}\n\nhalf fabs_diff(half x, half y) {\n  return fabs(x-y);\n}\n\nhalf phi(half x) {\n  // detection funtion\n  return 2 - x;\n  // if (x > 1) {\n  //   return 1 / x;\n  // } else {\n  //   return 2 - x;\n  // }\n}\n\n__kernel void debayer10(const __global uchar * in,\n                        __global uchar * out,\n                        __local half * cached\n                       )\n{\n  const int x_global = get_global_id(0);\n  const int y_global = get_global_id(1);\n\n  const int localRowLen = 2 + get_local_size(0); // 2 padding\n  const int x_local = get_local_id(0); // 0-15\n  const int y_local = get_local_id(1); // 0-15\n  const int localOffset = (y_local + 1) * localRowLen + x_local + 1; // max 18x18-1\n\n  int out_idx = 3 * x_global + 3 * y_global * RGB_WIDTH;\n\n  half pv = val_from_10(in, x_global, y_global);\n  cached[localOffset] = pv;\n\n  // don't care\n  if (x_global < 1 || x_global >= RGB_WIDTH - 1 || y_global < 1 || y_global >= RGB_HEIGHT - 1) {\n    return;\n  }\n\n  // cache padding\n  int localColOffset = -1;\n  int globalColOffset = -1;\n\n  // cache padding\n  if (x_local < 1) {\n    localColOffset = x_local;\n    globalColOffset = -1;\n    cached[(y_local + 1) * localRowLen + x_local] = val_from_10(in, x_global-1, y_global);\n  } else if (x_local >= get_local_size(0) - 1) {\n    localColOffset = x_local + 2;\n    globalColOffset = 1;\n    cached[localOffset + 1] = val_from_10(in, x_global+1, y_global);\n  }\n\n  if (y_local < 1) {\n    cached[y_local * localRowLen + x_local + 1] = val_from_10(in, x_global, y_global-1);\n    if (localColOffset != -1) {\n      cached[y_local * localRowLen + localColOffset] = val_from_10(in, x_global+globalColOffset, y_global-1);\n    }\n  } else if (y_local >= get_local_size(1) - 1) {\n    cached[(y_local + 2) * localRowLen + x_local + 1] = val_from_10(in, x_global, y_global+1);\n    if (localColOffset != -1) {\n      cached[(y_local + 2) * localRowLen + localColOffset] = val_from_10(in, x_global+globalColOffset, y_global+1);\n    }\n  }\n\n  // sync\n  barrier(CLK_LOCAL_MEM_FENCE);\n\n  half d1 = cached[localOffset - localRowLen - 1];\n  half d2 = cached[localOffset - localRowLen + 1];\n  half d3 = cached[localOffset + localRowLen - 1];\n  half d4 = cached[localOffset + localRowLen + 1];\n  half n1 = cached[localOffset - localRowLen];\n  half n2 = cached[localOffset + 1];\n  half n3 = cached[localOffset + localRowLen];\n  half n4 = cached[localOffset - 1];\n\n  half3 rgb;\n\n  // a simplified version of https://opensignalprocessingjournal.com/contents/volumes/V6/TOSIGPJ-6-1/TOSIGPJ-6-1.pdf\n  if (x_global % 2 == 0) {\n    if (y_global % 2 == 0) {\n      rgb.y = pv; // G1(R)\n      half k1 = phi(fabs_diff(d1, pv) + fabs_diff(d2, pv));\n      half k2 = phi(fabs_diff(d2, pv) + fabs_diff(d4, pv));\n      half k3 = phi(fabs_diff(d3, pv) + fabs_diff(d4, pv));\n      half k4 = phi(fabs_diff(d1, pv) + fabs_diff(d3, pv));\n      // R_G1\n      rgb.x = (k2*n2+k4*n4)/(k2+k4);\n      // B_G1\n      rgb.z = (k1*n1+k3*n3)/(k1+k3);\n    } else {\n      rgb.z = pv; // B\n      half k1 = phi(fabs_diff(d1, d3) + fabs_diff(d2, d4));\n      half k2 = phi(fabs_diff(n1, n4) + fabs_diff(n2, n3));\n      half k3 = phi(fabs_diff(d1, d2) + fabs_diff(d3, d4));\n      half k4 = phi(fabs_diff(n1, n2) + fabs_diff(n3, n4));\n      // G_B\n      rgb.y = (k1*(n1+n3)*0.5+k3*(n2+n4)*0.5)/(k1+k3);\n      // R_B\n      rgb.x = (k2*(d2+d3)*0.5+k4*(d1+d4)*0.5)/(k2+k4);\n    }\n  } else {\n    if (y_global % 2 == 0) {\n      rgb.x = pv; // R\n      half k1 = phi(fabs_diff(d1, d3) + fabs_diff(d2, d4));\n      half k2 = phi(fabs_diff(n1, n4) + fabs_diff(n2, n3));\n      half k3 = phi(fabs_diff(d1, d2) + fabs_diff(d3, d4));\n      half k4 = phi(fabs_diff(n1, n2) + fabs_diff(n3, n4));\n      // G_R\n      rgb.y = (k1*(n1+n3)*0.5+k3*(n2+n4)*0.5)/(k1+k3);\n      // B_R\n      rgb.z = (k2*(d2+d3)*0.5+k4*(d1+d4)*0.5)/(k2+k4);\n    } else {\n      rgb.y = pv; // G2(B)\n      half k1 = phi(fabs_diff(d1, pv) + fabs_diff(d2, pv));\n      half k2 = phi(fabs_diff(d2, pv) + fabs_diff(d4, pv));\n      half k3 = phi(fabs_diff(d3, pv) + fabs_diff(d4, pv));\n      half k4 = phi(fabs_diff(d1, pv) + fabs_diff(d3, pv));\n      // R_G2\n      rgb.x = (k1*n1+k3*n3)/(k1+k3);\n      // B_G2\n      rgb.z = (k2*n2+k4*n4)/(k2+k4);\n    }\n  }\n\n  rgb = clamp(0.0h, 1.0h, rgb);\n  rgb = color_correct(rgb);\n\n  out[out_idx + 0] = (uchar)(rgb.z);\n  out[out_idx + 1] = (uchar)(rgb.y);\n  out[out_idx + 2] = (uchar)(rgb.x);\n}\n"
  },
  {
    "path": "selfdrive/camerad/cameras/sensor2_i2c.h",
    "content": "struct i2c_random_wr_payload start_reg_array[] = {{0x301A, 0x91C}};\nstruct i2c_random_wr_payload stop_reg_array[] = {{0x301A, 0x918}};\n\nstruct i2c_random_wr_payload init_array_ar0231[] = {\n  {0x301A, 0x0018}, // RESET_REGISTER\n\n  // CLOCK Settings\n  {0x302A, 0x0006}, // VT_PIX_CLK_DIV\n  {0x302C, 0x0001}, // VT_SYS_CLK_DIV\n  {0x302E, 0x0002}, // PRE_PLL_CLK_DIV\n  {0x3030, 0x0032}, // PLL_MULTIPLIER\n  {0x3036, 0x000A}, // OP_WORD_CLK_DIV\n  {0x3038, 0x0001}, // OP_SYS_CLK_DIV\n\n  // FORMAT\n  {0x3040, 0xC000}, // READ_MODE\n  {0x3004, 0x0000}, // X_ADDR_START_ (A)\n  {0x308A, 0x0000}, // X_ADDR_START_ (B)\n  {0x3008, 0x0787}, // X_ADDR_END_ (A)\n  {0x308E, 0x0787}, // X_ADDR_END_ (B)\n  {0x3002, 0x0000}, // Y_ADDR_START_ (A)\n  {0x308C, 0x0000}, // Y_ADDR_START_ (B)\n  {0x3006, 0x04B7}, // Y_ADDR_END_ (A)\n  {0x3090, 0x04B7}, // Y_ADDR_END_ (B)\n  {0x3032, 0x0000}, // SCALING_MODE\n  {0x30A2, 0x0001}, // X_ODD_INC_ (A)\n  {0x30AE, 0x0001}, // X_ODD_INC_ (B)\n  {0x30A6, 0x0001}, // Y_ODD_INC_ (A)\n  {0x30A8, 0x0001}, // Y_ODD_INC_ (B)\n  {0x3402, 0x0F10}, // X_OUTPUT_CONTROL\n  {0x3404, 0x0970}, // Y_OUTPUT_CONTROL\n  {0x3064, 0x1802}, // SMIA_TEST\n  {0x30BA, 0x11F2}, // DIGITAL_CTRL\n\n  // SLAV* MODE\n  {0x30CE, 0x0120},\n  {0x340A, 0xE6}, // E6 // 0000 1110 0110\n  {0x340C, 0x802}, // 2 // 0000 0000 0010\n\n  // Readout timing\n  {0x300C, 0x07B9}, // LINE_LENGTH_PCK (A)\n  {0x303E, 0x07B9}, // LINE_LENGTH_PCK (B)\n  {0x300A, 0x07E7}, // FRAME_LENGTH_LINES (A)\n  {0x30AA, 0x07E7}, // FRAME_LENGTH_LINES (B)\n  {0x3042, 0x0000}, // EXTRA_DELAY\n\n  // Readout Settings\n  {0x31AE, 0x0204}, // SERIAL_FORMAT, 4-lane MIPI\n  {0x31AC, 0x0C0A}, // DATA_FORMAT_BITS, 12 -> 10\n  {0x3342, 0x122B}, // MIPI_F1_PDT_EDT\n  {0x3346, 0x122B}, // MIPI_F2_PDT_EDT\n  {0x334A, 0x122B}, // MIPI_F3_PDT_EDT\n  {0x334E, 0x122B}, // MIPI_F4_PDT_EDT\n  {0x3344, 0x0011}, // MIPI_F1_VDT_VC\n  {0x3348, 0x0111}, // MIPI_F2_VDT_VC\n  {0x334C, 0x0211}, // MIPI_F3_VDT_VC\n  {0x3350, 0x0311}, // MIPI_F4_VDT_VC\n  {0x31B0, 0x0053}, // FRAME_PREAMBLE\n  {0x31B2, 0x003B}, // LINE_PREAMBLE\n  {0x301A, 0x001C}, // RESET_REGISTER\n\n  // Noise Corrections\n  {0x3092, 0x0C24}, // ROW_NOISE_CONTROL\n  {0x337A, 0x0C80}, // DBLC_SCALE0\n  {0x3370, 0x03B1}, // DBLC\n  {0x3044, 0x0400}, // DARK_CONTROL\n\n  // Enable dead pixel correction using\n  // the 1D line correction scheme\n  {0x31E0, 0x0003},\n\n  // HDR Settings\n  {0x3082, 0x0004}, // OPERATION_MODE_CTRL (A)\n  {0x3084, 0x0004}, // OPERATION_MODE_CTRL (B)\n\n  {0x3238, 0x0004}, // EXPOSURE_RATIO (A)\n  {0x323A, 0x0004}, // EXPOSURE_RATIO (B)\n\n  {0x3014, 0x098E}, // FINE_INTEGRATION_TIME_ (A)\n  {0x3018, 0x098E}, // FINE_INTEGRATION_TIME_ (B)\n\n  {0x321E, 0x098E}, // FINE_INTEGRATION_TIME2 (A)\n  {0x3220, 0x098E}, // FINE_INTEGRATION_TIME2 (B)\n\n  {0x31D0, 0x0000}, // COMPANDING, no good in 10 bit?\n  {0x33DA, 0x0000}, // COMPANDING\n  {0x318E, 0x0200}, // PRE_HDR_GAIN_EN\n\n  // DLO Settings\n  {0x3100, 0x4000}, // DLO_CONTROL0\n  {0x3280, 0x0CCC}, // T1 G1\n  {0x3282, 0x0CCC}, // T1 R\n  {0x3284, 0x0CCC}, // T1 B\n  {0x3286, 0x0CCC}, // T1 G2\n  {0x3288, 0x0FA0}, // T2 G1\n  {0x328A, 0x0FA0}, // T2 R\n  {0x328C, 0x0FA0}, // T2 B\n  {0x328E, 0x0FA0}, // T2 G2\n\n   // Initial Gains\n  {0x3022, 0x0001}, // GROUPED_PARAMETER_HOLD_\n  {0x3366, 0xFF77}, // ANALOG_GAIN (1x) (A)\n  {0x3368, 0xFF77}, // ANALOG_GAIN (1x) (B)\n\n  {0x3060, 0x3333}, // ANALOG_COLOR_GAIN\n\n  {0x3362, 0x0000}, // DC GAIN (A & B)\n\n  {0x305A, 0x00F8}, // red gain (A)\n  {0x3058, 0x0122}, // blue gain (A)\n  {0x3056, 0x009A}, // g1 gain (A)\n  {0x305C, 0x009A}, // g2 gain (A)\n\n  {0x30C0, 0x00F8}, // red gain (B)\n  {0x30BE, 0x0122}, // blue gain (B)\n  {0x30BC, 0x009A}, // g1 gain (B)\n  {0x30C2, 0x009A}, // g2 gain (B)\n\n  {0x3022, 0x0000}, // GROUPED_PARAMETER_HOLD_\n\n  // Initial Integration Time\n  {0x3012, 0x0005}, // (A)\n  {0x3016, 0x0005}, // (B)\n};\n"
  },
  {
    "path": "selfdrive/camerad/cameras/sensor_i2c.h",
    "content": "static struct msm_camera_i2c_reg_array init_array_imx298[] = {\n  {0x101,0x0,0},  // IMAGE_ORIENT\n  {0x601,0x0,0},  // test pattern\n  //{0xb02,0,0},    // green correction?\n  // external clock setting\n  {0x136,0x18,0}, {0x137,0x0,0}, // EXCK_FREQ = Extclk_frequency_mhz\n  // global setting?\n  {0x30f4,0x1,0},\n  {0x30f5,0x7a,0},\n  {0x30f6,0x0,0},\n  {0x30f7,0xec,0},\n  {0x30fc,0x1,0},\n  {0x3101,0x1,0},\n  {0x5b2f,0x8,0},\n  {0x5d32,0x5,0},\n  {0x5d7c,0x0,0},\n  {0x5d7d,0x0,0},\n  {0x5db9,0x1,0},\n  {0x5e43,0x0,0},\n  {0x6300,0x0,0},\n  {0x6301,0xea,0},\n  {0x6302,0x0,0},\n  {0x6303,0xb4,0},\n  {0x6564,0x0,0},\n  {0x6565,0xb6,0},\n  {0x6566,0x0,0},\n  {0x6567,0xe6,0},\n  {0x6714,0x1,0},\n  {0x6758,0xb,0},\n  {0x6910,0x4,0},\n  {0x6916,0x1,0},\n  {0x6918,0x4,0},\n  {0x691e,0x1,0},\n  {0x6931,0x1,0},\n  {0x6937,0x2,0},\n  {0x693b,0x2,0},\n  {0x6d00,0x4a,0},\n  {0x6d01,0x41,0},\n  {0x6d02,0x23,0},\n  {0x6d05,0x4c,0},\n  {0x6d06,0x10,0},\n  {0x6d08,0x30,0},\n  {0x6d09,0x38,0},\n  {0x6d0a,0x2c,0},\n  {0x6d0b,0x2d,0},\n  {0x6d0c,0x34,0},\n  {0x6d0d,0x42,0},\n  {0x6d19,0x1c,0},\n  {0x6d1a,0x71,0},\n  {0x6d1b,0xc6,0},\n  {0x6d1c,0x94,0},\n  {0x6d24,0xe4,0},\n  {0x6d30,0xa,0},\n  {0x6d31,0x1,0},\n  {0x6d33,0xb,0},\n  {0x6d34,0x5,0},\n  {0x6d35,0x0,0},\n  {0x83c2,0x3,0},\n  {0x83c3,0x8,0},\n  {0x83c4,0x48,0},\n  {0x83c7,0x8,0},\n  {0x83cb,0x0,0},\n  {0xb101,0xff,0},\n  {0xb103,0xff,0},\n  {0xb105,0xff,0},\n  {0xb107,0xff,0},\n  {0xb109,0xff,0},\n  {0xb10b,0xff,0},\n  {0xb10d,0xff,0},\n  {0xb10f,0xff,0},\n  {0xb111,0xff,0},\n  {0xb163,0x3c,0},\n  {0xc2a0,0x8,0},\n  {0xc2a3,0x3,0},\n  {0xc2a5,0x8,0},\n  {0xc2a6,0x48,0},\n  {0xc2a9,0x0,0},\n  {0xf800,0x5e,0},\n  {0xf801,0x5e,0},\n  {0xf802,0xcd,0},\n  {0xf803,0x20,0},\n  {0xf804,0x55,0},\n  {0xf805,0xd4,0},\n  {0xf806,0x1f,0},\n  {0xf808,0xf8,0},\n  {0xf809,0x3a,0},\n  {0xf80a,0xf1,0},\n  {0xf80b,0x7e,0},\n  {0xf80c,0x55,0},\n  {0xf80d,0x38,0},\n  {0xf80e,0xe3,0},\n  {0xf810,0x74,0},\n  {0xf811,0x41,0},\n  {0xf812,0xbf,0},\n  {0xf844,0x40,0},\n  {0xf845,0xba,0},\n  {0xf846,0x70,0},\n  {0xf847,0x47,0},\n  {0xf848,0xc0,0},\n  {0xf849,0xba,0},\n  {0xf84a,0x70,0},\n  {0xf84b,0x47,0},\n  {0xf84c,0x82,0},\n  {0xf84d,0xf6,0},\n  {0xf84e,0x32,0},\n  {0xf84f,0xfd,0},\n  {0xf851,0xf0,0},\n  {0xf852,0x2,0},\n  {0xf853,0xf8,0},\n  {0xf854,0x81,0},\n  {0xf855,0xf6,0},\n  {0xf856,0xc0,0},\n  {0xf857,0xff,0},\n  {0xf858,0x10,0},\n  {0xf859,0xb5,0},\n  {0xf85a,0xd,0},\n  {0xf85b,0x48,0},\n  {0xf85c,0x40,0},\n  {0xf85d,0x7a,0},\n  {0xf85e,0x1,0},\n  {0xf85f,0x28,0},\n  {0xf860,0x15,0},\n  {0xf861,0xd1,0},\n  {0xf862,0xc,0},\n  {0xf863,0x49,0},\n  {0xf864,0xc,0},\n  {0xf865,0x46,0},\n  {0xf866,0x40,0},\n  {0xf867,0x3c,0},\n  {0xf868,0x48,0},\n  {0xf869,0x8a,0},\n  {0xf86a,0x62,0},\n  {0xf86b,0x8a,0},\n  {0xf86c,0x80,0},\n  {0xf86d,0x1a,0},\n  {0xf86e,0x8a,0},\n  {0xf86f,0x89,0},\n  {0xf871,0xb2,0},\n  {0xf872,0x10,0},\n  {0xf873,0x18,0},\n  {0xf874,0xa,0},\n  {0xf875,0x46,0},\n  {0xf876,0x20,0},\n  {0xf877,0x32,0},\n  {0xf878,0x12,0},\n  {0xf879,0x88,0},\n  {0xf87a,0x90,0},\n  {0xf87b,0x42,0},\n  {0xf87d,0xda,0},\n  {0xf87e,0x10,0},\n  {0xf87f,0x46,0},\n  {0xf880,0x80,0},\n  {0xf881,0xb2,0},\n  {0xf882,0x88,0},\n  {0xf883,0x81,0},\n  {0xf884,0x84,0},\n  {0xf885,0xf6,0},\n  {0xf886,0xd2,0},\n  {0xf887,0xf9,0},\n  {0xf888,0xe0,0},\n  {0xf889,0x67,0},\n  {0xf88a,0x85,0},\n  {0xf88b,0xf6,0},\n  {0xf88c,0xa1,0},\n  {0xf88d,0xfc,0},\n  {0xf88e,0x10,0},\n  {0xf88f,0xbd,0},\n  {0xf891,0x18,0},\n  {0xf892,0x21,0},\n  {0xf893,0x24,0},\n  {0xf895,0x18,0},\n  {0xf896,0x19,0},\n  {0xf897,0xb4,0},\n  {0x4e29,0x1,0},\n  // PDAF stuff\n  {0x3166,0x1,0}, //AREA_EN_0\n  {0x3167,0x1,0},\n  {0x3168,0x1,0},\n  {0x3169,0x1,0},\n  {0x316a,0x1,0},\n  {0x316b,0x1,0},\n  {0x316c,0x1,0},\n  {0x316d,0x1,0},\n  {0x3158,0x2,0},\n  {0x3159,0x2,0},\n  {0x315a,0x2,0},\n  {0x315b,0x3,0},\n  {0x3013,0x7,0}, //RMSC_NR_MODE\n  {0x3035,0x1,0},\n  {0x3051,0x0,0},\n  {0x3056,0x2,0},\n  {0x3057,0x1,0},\n  {0x3060,0x0,0},\n  {0x8435,0x0,0},\n  {0x8455,0x0,0},\n  {0x847c,0x0,0},\n  {0x84fb,0x1,0},\n  {0x9619,0xa0,0},\n  {0x961b,0xa0,0},\n  {0x961d,0xa0,0},\n  {0x961f,0x20,0},\n  {0x9621,0x20,0},\n  {0x9623,0x20,0},\n  {0x9625,0xa0,0},\n  {0x9627,0xa0,0},\n  {0x9629,0xa0,0},\n  {0x962b,0x20,0},\n  {0x962d,0x20,0},\n  {0x962f,0x20,0},\n  {0x9901,0x35,0},\n  {0x9903,0x23,0},\n  {0x9905,0x23,0},\n  {0x9906,0x0,0},\n  {0x9907,0x31,0},\n  {0x9908,0x0,0},\n  {0x9909,0x1b,0},\n  {0x990a,0x0,0},\n  {0x990b,0x15,0},\n  {0x990d,0x3f,0},\n  {0x990f,0x3f,0},\n  {0x9911,0x3f,0},\n  {0x9913,0x64,0},\n  {0x9915,0x64,0},\n  {0x9917,0x64,0},\n  {0x9919,0x50,0},\n  {0x991b,0x60,0},\n  {0x991d,0x65,0},\n  {0x991f,0x1,0},\n  {0x9921,0x1,0},\n  {0x9923,0x1,0},\n  {0x9925,0x23,0},\n  {0x9927,0x23,0},\n  {0x9929,0x23,0},\n  {0x992b,0x2f,0},\n  {0x992d,0x1a,0},\n  {0x992f,0x14,0},\n  {0x9931,0x3f,0},\n  {0x9933,0x3f,0},\n  {0x9935,0x3f,0},\n  {0x9937,0x6b,0},\n  {0x9939,0x7c,0},\n  {0x993b,0x81,0},\n  {0x9943,0xf,0},\n  {0x9945,0xf,0},\n  {0x9947,0xf,0},\n  {0x9949,0xf,0},\n  {0x994b,0xf,0},\n  {0x994d,0xf,0},\n  {0x994f,0x42,0},\n  {0x9951,0xf,0},\n  {0x9953,0xb,0},\n  {0x9955,0x5a,0},\n  {0x9957,0x13,0},\n  {0x9959,0xc,0},\n  {0x995a,0x0,0},\n  {0x995b,0x0,0},\n  {0x995c,0x0,0},\n  {0x996b,0x0,0},\n  {0x996d,0x10,0},\n  {0x996f,0x10,0},\n  {0x9971,0xc8,0},\n  {0x9973,0x32,0},\n  {0x9975,0x4,0},\n  {0x9976,0xa,0},\n  {0x9977,0xa,0},\n  {0x9978,0xa,0},\n  {0x99a4,0x2f,0},\n  {0x99a5,0x2f,0},\n  {0x99a6,0x2f,0},\n  {0x99a7,0xa,0},\n  {0x99a8,0xa,0},\n  {0x99a9,0xa,0},\n  {0x99aa,0x2f,0},\n  {0x99ab,0x2f,0},\n  {0x99ac,0x2f,0},\n  {0x99ad,0x0,0},\n  {0x99ae,0x0,0},\n  {0x99af,0x0,0},\n  {0x99b0,0x40,0},\n  {0x99b1,0x40,0},\n  {0x99b2,0x40,0},\n  {0x99b3,0x30,0},\n  {0x99b4,0x30,0},\n  {0x99b5,0x30,0},\n  {0x99bb,0xa,0},\n  {0x99bd,0xa,0},\n  {0x99bf,0xa,0},\n  {0x99c0,0x9,0},\n  {0x99c1,0x9,0},\n  {0x99c2,0x9,0},\n  {0x99c6,0x3c,0},\n  {0x99c7,0x3c,0},\n  {0x99c8,0x3c,0},\n  {0x99c9,0xff,0},\n  {0x99ca,0xff,0},\n  {0x99cb,0xff,0},\n  {0x9b01,0x35,0},\n  {0x9b03,0x14,0},\n  {0x9b05,0x14,0},\n  {0x9b07,0x31,0},\n  {0x9b09,0x1b,0},\n  {0x9b0b,0x15,0},\n  {0x9b0d,0x1e,0},\n  {0x9b0f,0x1e,0},\n  {0x9b11,0x1e,0},\n  {0x9b13,0x64,0},\n  {0x9b15,0x64,0},\n  {0x9b17,0x64,0},\n  {0x9b19,0x50,0},\n  {0x9b1b,0x60,0},\n  {0x9b1d,0x65,0},\n  {0x9b1f,0x1,0},\n  {0x9b21,0x1,0},\n  {0x9b23,0x1,0},\n  {0x9b25,0x14,0},\n  {0x9b27,0x14,0},\n  {0x9b29,0x14,0},\n  {0x9b2b,0x2f,0},\n  {0x9b2d,0x1a,0},\n  {0x9b2f,0x14,0},\n  {0x9b31,0x1e,0},\n  {0x9b33,0x1e,0},\n  {0x9b35,0x1e,0},\n  {0x9b37,0x6b,0},\n  {0x9b39,0x7c,0},\n  {0x9b3b,0x81,0},\n  {0x9b43,0xf,0},\n  {0x9b45,0xf,0},\n  {0x9b47,0xf,0},\n  {0x9b49,0xf,0},\n  {0x9b4b,0xf,0},\n  {0x9b4d,0xf,0},\n  {0x9b4f,0x2d,0},\n  {0x9b51,0xb,0},\n  {0x9b53,0x8,0},\n  {0x9b55,0x40,0},\n  {0x9b57,0xd,0},\n  {0x9b59,0x8,0},\n  {0x9b5a,0x0,0},\n  {0x9b5b,0x0,0},\n  {0x9b5c,0x0,0},\n  {0x9b6b,0x0,0},\n  {0x9b6d,0x10,0},\n  {0x9b6f,0x10,0},\n  {0x9b71,0xc8,0},\n  {0x9b73,0x32,0},\n  {0x9b75,0x4,0},\n  {0x9bb0,0x40,0},\n  {0x9bb1,0x40,0},\n  {0x9bb2,0x40,0},\n  {0x9bb3,0x30,0},\n  {0x9bb4,0x30,0},\n  {0x9bb5,0x30,0},\n  {0x9bbb,0xa,0},\n  {0x9bbd,0xa,0},\n  {0x9bbf,0xa,0},\n  {0x9bc0,0x9,0},\n  {0x9bc1,0x9,0},\n  {0x9bc2,0x9,0},\n  {0x9bc6,0x18,0},\n  {0x9bc7,0x18,0},\n  {0x9bc8,0x18,0},\n  {0x9bc9,0xff,0},\n  {0x9bca,0xff,0},\n  {0x9bcb,0xff,0},\n  {0xb2b2,0x1,0},\n};\n\nstatic struct msm_camera_i2c_reg_array mode_setting_array_imx298[] = {\n// i2c settings for mode 3\n// {\n//   .x_output = 2328,\n//   .y_output = 1748,\n//   .line_length_pclk = 5536,\n//   .frame_length_lines = 1802,\n//   .vt_pixel_clk = 299300000,\n//   .op_pixel_clk = 299300000,\n//   .binning_factor = 2,\n//   .min_fps = 15.000000,\n//   .max_fps = 30.020000,\n//   .mode = 1,\n//   .offset_x = 0,\n//   .offset_y = 0,\n//   .scale_factor = 1.000000,\n//   .is_pdaf_supported = 1,\n// }\n\n// mode settings\n\n// hdr settings\n{0x0114, 0x03, 0}, // CSI_LANE_MODE = 4-lane\n/*{0x0220, 0x00, 0}, // HDR_MODE = disable\n{0x0221, 0x11, 0}, // HDR_RESO_REDU_H/V = Full Pixel\n{0x0222, 0x10, 0}, // EXPO_RATIO = 16*/\n{0x0220, 0x01, 0}, // HDR_MODE = enable with combined gain and 16x ratio\n{0x0221, 0x22, 0}, // HDR_RESO_REDU_H/V = 2 binning\n{0x0222, 0x10, 0}, // EXPO_RATIO = 16\n\n{0x0340, 0x07, 0}, {0x0341, 0x0a, 0}, // FRM_LENGTH  = frame_length_lines = 1802\n{0x0342, 0x15, 0}, {0x0343, 0xa0, 0}, // LINE_LENGTH = line_length_pclk   = 5536\n{0x0344, 0x00, 0}, {0x0345, 0x00, 0}, // x_addr_start\n{0x0346, 0x00, 0}, {0x0347, 0x00, 0}, // y_addr_start\n{0x0348, 0x12, 0}, {0x0349, 0x2f, 0}, // x_addr_end\n{0x034a, 0x0d, 0}, {0x034b, 0xa7, 0}, // y_addr_end\n{0x0381, 0x01, 0}, // x_even_inc\n{0x0383, 0x01, 0}, // x_odd_inc\n{0x0385, 0x01, 0}, // y_even_inc\n{0x0387, 0x01, 0}, // y_odd_inc\n{0x0900, 0x01, 0}, // BINNING_MODE = enable\n{0x0901, 0x22, 0}, // BINING_TYPE_H/V = 2binning\n{0x0902, 0x00, 0}, // binning_weighting = average\n\n{0x0b06, 1, 0},     // SING_DEF_CORR_EN\n{0x0b0a, 1, 0},     // combined defect correct\n\n{0x3010, 0x66, 0}, // HDR_OUTPUT_CTRL = ATR + HDR compose + DPC1D + DCP2D\n{0x3011, 0x01, 0}, // HDR_OUTPUT_CTRL2 = PD enable\n{0x30c0, 0x11, 0}, // RED_GAIN_CB?\n{0x300d, 0x00, 0}, // FORCE_FDSUM = disable\n{0x30fd, 0x00, 0},\n{0x8493, 0x00, 0},\n{0x8863, 0x00, 0},\n{0x90d7, 0x19, 0},\n\n// set black level\n{0x3090, 1, 0},\n{0x3092, 0, 0},\n{0x3093, 0x38, 0},\n\n// output size settings\n{0x0112, 0x0a, 0}, {0x0113, 0x0a, 0}, // CS_DT_FMT_H = 0x0a0a (RAW10 output)\n{0x034c, 0x09, 0}, {0x034d, 0x18, 0}, // X_OUT_SIZE = 2328 (1164*2)\n{0x034e, 0x06, 0}, {0x034f, 0xd4, 0}, // Y_OUT_SIZE = 1748 (874*2)\n{0x0401, 0x00, 0}, // SCALING_MODE\n{0x0404, 0x00, 0}, {0x0405, 0x10, 0}, // SCALE_M\n{0x0408, 0x00, 0}, {0x0409, 0x00, 0}, // DCROP_XOFS\n{0x040a, 0x00, 0}, {0x040b, 0x00, 0}, // DCROP_YOFS\n{0x040c, 0x09, 0}, {0x040d, 0x18, 0}, // DCROP_WIDTH\n{0x040e, 0x06, 0}, {0x040f, 0xd4, 0}, // DCROP_HIGT\n\n// clock settings\n// 299300000\n/*\n{0x0301, 0x05, 0}, // VT_PIX_CLK_DIV\n{0x0303, 0x02, 0}, // VT_SYS_CLK_DIV\n{0x0305, 0x04, 0}, // PRE_PLL_CLK_DIV\n{0x0306, 0x00, 0}, {0x0307, 0x7d, 0}, // PLL_MULTIPLIER . mode 1: 0xf6\n{0x0309, 0x0a, 0}, // OP_PIX_CLK_DIV\n{0x030b, 0x01, 0}, // OP_SYS_CLK_DIV\n{0x030d, 0x0f, 0}, // PREPLLCK_OP_DIV\n{0x030e, 0x03, 0}, {0x030f, 0x41, 0}, // PLL_OP_MPY\n{0x0310, 0x00, 0}, // PLL_MULT_DRIV\n*/\n// 600000000\n{0x0301, 0x05, 0},\n{0x0303, 0x02, 0},\n{0x0305, 0x04, 0},\n{0x0306, 0x00, 0},\n{0x0307, 0xfa, 0},\n{0x0309, 0x0a, 0},\n{0x030b, 0x01, 0},\n{0x030d, 0x0f, 0},\n{0x030e, 0x03, 0}, {0x030f, 0x41, 0},\n{0x0310, 0x00, 0},\n\n// data rate settings\n/*{0x0820, 0x0b, 0}, // requested_link_bit_rate_mbps = 3000\n{0x0821, 0xb8, 0},\n{0x0822, 0x00, 0},\n{0x0823, 0x00, 0},*/\n{0x0820, 0x17, 0}, // requested_link_bit_rate_mbps = 6000\n{0x0821, 0x70, 0},\n{0x0822, 0x00, 0},\n{0x0823, 0x00, 0},\n\n//integration time settings\n{0x0202, 0x07, 0}, {0x0203, 0x00, 0}, // INTEG_TIME = 1792\n{0x0224, 0x01, 0}, {0x0225, 0xf4, 0}, // ST_COARSE_INTEG_TIME = 506\n\n// gain settings\n{0x0204, 0x00, 0}, {0x0205, 0x00, 0}, // ANA_GAIN_GLOBAL = 512 / (512 - X)\n{0x0216, 0x00, 0}, {0x0217, 0x00, 0}, // ST_ANA_GAIN_GLOBAL[8]\n{0x020e, 0x01, 0}, {0x020f, 0x00, 0}, // DIG_GAIN_GR\n{0x0210, 0x01, 0}, {0x0211, 0x00, 0}, // DIG_GAIN_R\n{0x0212, 0x01, 0}, {0x0213, 0x00, 0}, // DIG_GAIN_B\n{0x0214, 0x01, 0}, {0x0215, 0x00, 0}, // DIG_GAIN_GB\n\n// HDR white balance settings (ABS_GAIN)\n{0xb8e, 0x01, 0}, {0xb8f, 0x00, 0}, // GR\n{0xb90, 0x02, 0}, {0xb91, 0x2b, 0}, // R\n{0xb92, 0x01, 0}, {0xb93, 0xd4, 0}, // B\n{0xb94, 0x01, 0}, {0xb95, 0x00, 0}, // GB\n\n// phase detection settings\n{0x3058, 0x00, 0}, // NML_NR_EN\n{0x3103, 0x01, 0}, // NML_PD_CAL_ENABLE = enable\n{0x3108, 0x00, 0}, {0x3109, 0x2c, 0}, //PD_AREA_X_OFFSET\n{0x310a, 0x00, 0}, {0x310b, 0x24, 0}, //PD_AREA_Y_OFFSET\n{0x310c, 0x01, 0}, {0x310d, 0xa4, 0}, //PD_AREA_WIDTH\n{0x310e, 0x01, 0}, {0x310f, 0xa4, 0}, //PD_AREA_HEIGHT\n// whole size is 0x918 x 0x6d4\n{0x3110, 0x03, 0}, // PD_AREA_0 = 0x375-0x4d1, 0x258-0x3b6\n{0x3111, 0x75, 0},\n{0x3112, 0x02, 0},\n{0x3113, 0x58, 0},\n{0x3114, 0x04, 0},\n{0x3115, 0xd1, 0},\n{0x3116, 0x03, 0},\n{0x3117, 0xb6, 0},\n{0x3118, 0x04, 0}, // PD_AREA_1 = 0x446-0x5a2, 0x258-0x3b6\n{0x3119, 0x46, 0},\n{0x311a, 0x02, 0},\n{0x311b, 0x58, 0},\n{0x311c, 0x05, 0},\n{0x311d, 0xa2, 0},\n{0x311e, 0x03, 0},\n{0x311f, 0xb6, 0},\n{0x3120, 0x03, 0}, // PD_AREA_2 = 0x375-0x4d1, 0x32a-0x488\n{0x3121, 0x75, 0},\n{0x3122, 0x03, 0},\n{0x3123, 0x2a, 0},\n{0x3124, 0x04, 0},\n{0x3125, 0xd1, 0},\n{0x3126, 0x04, 0},\n{0x3127, 0x88, 0},\n{0x3128, 0x04, 0}, // PD_AREA_3 = 0x446-0x5a2, 0x32a-0x488\n{0x3129, 0x46, 0},\n{0x312a, 0x03, 0},\n{0x312b, 0x2a, 0},\n{0x312c, 0x05, 0},\n{0x312d, 0xa2, 0},\n{0x312e, 0x04, 0},\n{0x312f, 0x88, 0},\n{0x3130, 0x03, 0}, // PD_AREA_4 = 0x375-0x5a2, 0x258-0x488\n{0x3131, 0x75, 0},\n{0x3132, 0x02, 0},\n{0x3133, 0x58, 0},\n{0x3134, 0x05, 0},\n{0x3135, 0xa2, 0},\n{0x3136, 0x04, 0},\n{0x3137, 0x88, 0},\n{0x3138, 0x02, 0}, // PD_AREA_5 = 0x2ba-0x65d, 0x210-0x4d0\n{0x3139, 0xba, 0},\n{0x313a, 0x02, 0},\n{0x313b, 0x10, 0},\n{0x313c, 0x06, 0},\n{0x313d, 0x5d, 0},\n{0x313e, 0x04, 0},\n{0x313f, 0xd0, 0},\n{0x3140, 0x00, 0}, // PD_AREA_6 = 0xa1-0x876, 0x6b-0x676\n{0x3141, 0xa1, 0},\n{0x3142, 0x00, 0},\n{0x3143, 0x6b, 0},\n{0x3144, 0x08, 0},\n{0x3145, 0x76, 0},\n{0x3146, 0x06, 0},\n{0x3147, 0x76, 0},\n{0x3148, 0x00, 0}, // PD_AREA_7 = 0xa1-0x876, 0x5e-0x34c\n{0x3149, 0xa1, 0},\n{0x314a, 0x00, 0},\n{0x314b, 0x5e, 0},\n{0x314c, 0x08, 0},\n{0x314d, 0x76, 0},\n{0x314e, 0x03, 0},\n{0x314f, 0x4c, 0},\n{0x3165, 0x02, 0}, // AREA_EN_0 = free area\n};\n\n// static struct msm_camera_i2c_reg_array reg_array3[] = {\n//   // REG_HOLD ON\n//   {0x104,0x1,0},\n//   // from regression\n//   {0x3002,0x0,0},\n//   // FRM_LENGTH, 1802 vs 3554\n//   // {0x340,0x7,0}, {0x341,0xa,0},  // camera start  {0x340,0xd,0}, {0x341,0xe2,0},\n//   // INTEG_TIME aka coarse_int_time_addr aka shutter speed\n//   {0x202,0x03,0}, {0x203,0xda,0},\n//   // global_gain_addr\n//   {0x204,0x0,0}, {0x205,0x0,0},\n\n//   //??\n//   {0x20e,0x1,0}, {0x20f,0x0,0},\n//   {0x210,0x1,0}, {0x211,0x0,0},\n//   {0x212,0x1,0}, {0x213,0x0,0},\n//   {0x214,0x1,0}, {0x215,0x0,0},\n\n//   // REG_HOLD: mode setting\n//   {0x104,0x0,0},\n// };\n\n// start, remove standby mode\nstatic struct msm_camera_i2c_reg_array start_reg_array[] = {{0x100,0x1,0}};\n\n// stop, enable standby mode\nstatic struct msm_camera_i2c_reg_array stop_reg_array[] = {{0x100,0x0,0}};\n\n///////////////////\n\n\nstatic struct msm_camera_i2c_reg_array init_array_imx179[] = {\n  { 0x100, 0x0, 0}, // MODE_SELECT\n  { 0x101, 0x0, 0}, // IMAGE_ORIENT\n  { 0x202, 0x9, 0}, { 0x203, 0xd2, 0}, // COARSE_INTEGRATION_TIME\n  { 0x301, 0x5, 0}, // vt_pix_clk_div\n  { 0x303, 0x1, 0}, // vt_sys_clk_div\n  { 0x305, 0x6, 0}, // pre_pll_clk_div\n  { 0x309, 0x5, 0}, // op_pix_clk_div\n  { 0x30b, 0x1, 0}, // op_sys_clk_div\n  { 0x30c, 0x0, 0}, { 0x30d, 0x9d, 0},\n\n  { 0x340, 0x9, 0}, { 0x341, 0xd6, 0}, // frame_length_lines\n  { 0x342, 0xd, 0}, { 0x343, 0x70, 0}, // line_length_pclk\n  { 0x344, 0x0, 0}, { 0x345, 0x0, 0}, // x_addr_start\n  { 0x346, 0x0, 0}, { 0x347, 0x0, 0}, // y_addr_start\n  { 0x348, 0xc, 0}, { 0x349, 0xcf, 0}, // last_pixel / x_addr_end\n  { 0x34a, 0x9, 0}, { 0x34b, 0x9f, 0}, // last_line / y_addr_end\n  { 0x34c, 0xc, 0}, { 0x34d, 0xd0, 0}, // pixels_per_line / x_output_size\n  { 0x34e, 0x9, 0}, { 0x34f, 0xa0, 0}, // lines_per_frame / y_output_size\n  { 0x383, 0x1, 0}, // x_odd_inc\n  { 0x387, 0x1, 0}, // y_odd_inc\n  { 0x390, 0x0, 0}, // binning_mode\n  { 0x401, 0x0, 0}, // SCALING_MODE\n  { 0x405, 0x10, 0}, // SCALE_M\n\n  {0x3020, 0x10, 0},\n  {0x3041, 0x15, 0}, // READ_MODE?\n  {0x3042, 0x87, 0},\n  {0x3089, 0x4f, 0},\n  {0x3309, 0x9a, 0},\n  {0x3344, 0x57, 0},\n  {0x3345, 0x1f, 0},\n  {0x3362, 0xa, 0},\n  {0x3363, 0xa, 0},\n  {0x3364, 0x0, 0},\n  {0x3368, 0x18, 0},\n  {0x3369, 0x0, 0},\n  {0x3370, 0x6f, 0},\n  {0x3371, 0x27, 0},\n  {0x3372, 0x4f, 0},\n  {0x3373, 0x2f, 0},\n  {0x3374, 0x27, 0},\n  {0x3375, 0x2f, 0},\n  {0x3376, 0x97, 0},\n  {0x3377, 0x37, 0},\n  {0x33c8, 0x0, 0},\n  {0x33d4, 0xc, 0},\n  {0x33d5, 0xd0, 0},\n  {0x33d6, 0x9, 0},\n  {0x33d7, 0xa0, 0},\n  // znr\n  {0x4100, 0xe, 0},\n  {0x4108, 0x1, 0},\n  {0x4109, 0x7c, 0},\n};\n\n\n\n/////////////// ois stuff ///////////////\n\n/*\n#define _OP_FIRM_DWNLD  0x80\n#define _OP_Periphe_RW  0x82\n#define _OP_Memory__RW  0x84\n#define _OP_AD_TRNSFER  0x86\n#define _OP_COEF_DWNLD  0x88\n#define _OP_PrgMem__RD  0x8A\n#define _OP_SpecialCMD  0x8C\n*/\n\nstatic struct reg_settings_ois_t ois_init_settings[] = {\n  {\n    .reg_addr = 0x8262,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0xbf03,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8263,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x9f05,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8264,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x6040,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8260,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x1130,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8265,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x8000,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8261,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0280,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8261,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0380,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8261,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0988,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x34\\x84\\x00\\x03\\xff\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x03\\x00\\x10\\x7e\\x84\\x50\\x00\\x08\\x40\\x7e\\xa0\\x00\\x03\\x00\\x10\\x7e\\x84\\x60\\x00\\x08\\x40\\x7e\\xa0\\x00\\x03\\x00\\x90\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x10\\x08\\x80\\x00\\xa0\\x10\\x00\\x08\\x7f\\xff\\x11\\x8f\\x02\\x07\\x80\\x00\\x11\\x40\\xff\\xa0\\x90\\x01\\x84\\x20\\x8f\\x08\\x40\\xfe\\x90\\x40\\xf5\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x08\\x80\\x01\\xa0\\x00\\x01\\x11\\x8f\\x02\\x07\\xff\\xff\\x11\\x08\\x00\\x20\\x50\\x12\\x07\\x00\\x10\\x08\\x80\\x00\\xa0\\x10\\xff\\x84\\x20\\x0a\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x7f\\xff\\x21\\x08\\xfe\\x84\\x00\\x04\\x07\\x20\\x0c\\x08\\x7f\\xff\\x21\\x08\\xfe\\x84\\x00\\x03\\x00\\x90\\x17\\x84\\x20\\x1f\\x08\\x80\\x17\\xa0\\x10\\x10\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x7f\\xff\\x21\\x10\\x00\\x08\\x01\\x00\\x11\\x40\\x51\\xa0\\x90\\x17\\x84\\x20\\x0f\\x08\\x80\\x47\\xa0\\x8d\\x0c\\x07\\x00\\x00\\x11\\x30\\x03\\x07\\x80\\x41\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8090,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x50\\x00\\x08\\x40\\xfc\\x90\\x88\\x2f\\x84\\x00\\x00\\x11\\x30\\x02\\x07\\x40\\xff\\x90\\x50\\x00\\x08\\x40\\xfd\\x90\\x40\\x7f\\xa0\\x10\\xff\\x84\\x20\\x2c\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x7f\\xff\\x11\\x20\\x0d\\x08\\x80\\x0f\\x90\\x80\\x26\\xa0\\x90\\x2e\\x84\\x00\\x10\\x08\\x90\\x26\\x84\\x00\\x10\\x08\\x80\\x1f\\xa0\\x20\\x2e\\x08\\x40\\xed\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8090,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x20\\x0f\\x08\\x80\\x0e\\x90\\x00\\x00\\x21\\x30\\x02\\x07\\x40\\xeb\\xa0\\x50\\x00\\x08\\x40\\xfe\\x90\\x40\\x7f\\xa0\\x04\\xeb\\x84\\x10\\x00\\x20\\x20\\x0f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x80\\x00\\x21\\x60\\x04\\x07\\x40\\xff\\xa0\\x10\\x00\\x08\\x40\\xea\\x90\\x10\\x00\\x20\\x20\\x0f\\x08\\x80\\x00\\x11\\x00\\x0b\\x07\\x08\\x00\\x20\\x60\\x0d\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x00\\x08\\x40\\xea\\x90\\x8f\\x06\\x07\\x04\\xff\\x84\\x20\\x09\\x60\\x10\\xfc\\x84\\x08\\xfd\\x84\\x04\\xfe\\x84\\x00\\x03\\x00\\x00\\x10\\x08\\x80\\x37\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x90\\x69\\x84\\x00\\x10\\x08\\x80\\x69\\xa0\\x20\\x1a\\x08\\x40\\x64\\xa0\\x10\\x10\\x08\\x80\\x4f\\xa0\\x20\\x1d\\x08\\x40\\x5f\\xa0\\x20\\x1e\\x08\\x40\\x5d\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x00\\x08\\x80\\x68\\x90\\x40\\xfe\\xa0\\x20\\x0e\\x07\\x50\\x00\\x08\\x40\\x7f\\xa0\\x04\\xfe\\x84\\x00\\x04\\x00\\x10\\xf0\\x44\\x50\\x00\\x08\\x00\\x7f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x20\\xf0\\x60\\x04\\x5c\\x84\\x04\\x61\\x84\\x04\\x57\\x84\\x00\\x00\\x21\\x04\\x74\\x84\\x00\\x40\\x21\\x00\\x0b\\x07\\x04\\x74\\x84\\x00\\x00\\x21\\x10\\x57\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x30\\x20\\x08\\x00\\x04\\x11\\x50\\x00\\x08\\x03\\xff\\x11\\x20\\xfa\\x60\\x10\\xf0\\x44\\x50\\x20\\x08\\x00\\x7f\\x11\\x60\\x20\\x08\\x40\\x00\\x08\\x00\\x08\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x30\\x1a\\x07\\x50\\x00\\x08\\x07\\x00\\x11\\x9f\\x1d\\x07\\x8b\\x1e\\x07\\x9c\\x15\\x07\\x20\\xf8\\x60\\x10\\x28\\x44\\x60\\x00\\x08\\x01\\x00\\x11\\x20\\x28\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8060,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x87\\x1b\\x07\\x40\\xf7\\xa0\\x81\\x27\\x07\\x20\\x48\\x60\\x10\\x0a\\x44\\x10\\xf4\\x84\\x3b\\xd4\\x00\\xe0\\x14\\x43\\x08\\x00\\x20\\x00\\x06\\x07\\x89\\x02\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\xae\\x90\\x81\\x04\\x07\\x40\\x2e\\x90\\x40\\x7f\\xa0\\x10\\x2e\\x44\\x20\\x2f\\x08\\x9f\\x02\\x07\\x00\\x00\\x11\\x10\\x00\\x20\\x00\\x00\\x08\\x40\\x67\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x11\\x84\\x02\\x07\\x20\\xf0\\x60\\x9f\\x03\\x07\\x40\\x7e\\xa0\\x40\\x65\\x90\\x10\\x62\\x84\\x10\\x10\\x08\\x40\\x61\\xa0\\x20\\x1d\\x08\\x40\\x5f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x20\\x1e\\x08\\x40\\x5d\\xa0\\x10\\x00\\x08\\x40\\x5e\\x90\\x20\\x30\\x60\\x10\\xcf\\x84\\x20\\x1c\\x08\\x7f\\xff\\x21\\x3b\\xf7\\x00\\xc8\\x14\\x43\\x10\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8020,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x08\\x40\\xb5\\x90\\x40\\xad\\xa0\\x00\\x0a\\x07\\x10\\x4f\\x84\\x20\\x1c\\x08\\x7f\\xff\\x21\\x3c\\x01\\x00\\x48\\x14\\x43\\x10\\x00\\x20\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x35\\x90\\x40\\x2d\\xa0\\x00\\x14\\x07\\x80\\x0c\\x07\\x82\\x03\\x07\\x04\\x50\\x84\\x10\\x00\\x20\\x20\\x02\\x07\\x00\\x08\\x21\\x40\\x00\\x08\\x00\\x01\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x50\\xa0\\x00\\x04\\x00\\x20\\x7f\\x00\\x80\\x14\\x43\\x01\\x00\\x01\\x04\\x00\\x11\\x02\\x00\\x21\\x10\\x9f\\x84\\x10\\x20\\x08\\x40\\x97\\x90\\x10\\xbf\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x20\\x1d\\x08\\x40\\xc6\\xa0\\x20\\x8e\\x08\\x40\\x72\\x90\\x40\\x16\\xa0\\x10\\x96\\x84\\x10\\x00\\x08\\x40\\x9e\\x90\\x20\\x36\\x60\\x20\\x91\\x00\\x00\\x14\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8043,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x01\\x01\\x00\\x04\\x11\\x00\\x02\\x21\\x10\\x1f\\x84\\x10\\x20\\x08\\x40\\x17\\x90\\x10\\x3f\\x84\\x20\\x1d\\x08\\x40\\x46\\xa0\\x20\\x8e\\x08\\x40\\x70\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8090,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x96\\xa0\\x10\\x16\\x84\\x10\\x00\\x08\\x40\\x1e\\x90\\x20\\x34\\x60\\x10\\x65\\x84\\x50\\x10\\x08\\x00\\x00\\x21\\x84\\x03\\x07\\x20\\xf0\\x60\\x9f\\x03\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x7e\\xa0\\x00\\x10\\x08\\x40\\x65\\xa0\\x20\\x0d\\x08\\x40\\x64\\x90\\x40\\x62\\xa0\\x00\\x04\\x00\\x04\\x1c\\x44\\x04\\x1b\\x44\\xc3\\xff\\x21\\x87\\x04\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x7f\\xa0\\x10\\x42\\x84\\x20\\x1e\\x08\\x7f\\xff\\x21\\x10\\x20\\x08\\x40\\x1c\\x90\\x10\\x07\\x84\\x10\\x00\\x08\\x40\\x06\\x90\\x40\\x55\\xa0\\x10\\xc2\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x20\\x1e\\x08\\x7f\\xff\\x21\\x10\\x20\\x08\\x40\\x9c\\x90\\x10\\x87\\x84\\x10\\x00\\x08\\x40\\x86\\x90\\x40\\x56\\xa0\\x10\\x56\\x84\\x20\\x0f\\x08\\x40\\x7b\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8090,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x22\\x00\\x60\\x40\\x00\\x08\\x40\\x79\\xa0\\x00\\x08\\x11\\x10\\x55\\x84\\x20\\x0f\\x08\\x40\\x7a\\x90\\x22\\x00\\x60\\x50\\x00\\x08\\x40\\x79\\xa0\\x00\\xff\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x04\\x6f\\x84\\x00\\x05\\x21\\x21\\x39\\x00\\x04\\x00\\x11\\x10\\xc1\\x84\\x20\\x0f\\x08\\x70\\x07\\x07\\x10\\x10\\x08\\x40\\xc0\\xa0\\x20\\x0f\\x08\\x7f\\xff\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x8f\\x02\\x07\\x80\\x00\\x11\\x08\\x00\\x20\\x08\\xc1\\x84\\x40\\xbd\\x90\\x9e\\x02\\x07\\x40\\x7f\\xa0\\x40\\xec\\x90\\x04\\x6e\\x84\\x00\\x05\\x21\\x21\\x4c\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x04\\x11\\x10\\x41\\x84\\x20\\x0f\\x08\\x70\\x07\\x07\\x10\\x10\\x08\\x40\\x40\\xa0\\x20\\x0f\\x08\\x7f\\xff\\x11\\x8f\\x02\\x07\\x80\\x00\\x11\\x08\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8020,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x08\\x41\\x84\\x40\\x3d\\x90\\x9e\\x02\\x07\\x40\\x7f\\xa0\\x40\\x6d\\x90\\x10\\x2d\\x44\\x20\\xe7\\x00\\x08\\x00\\x11\\x20\\x32\\x60\\x80\\x14\\x43\\x10\\x2c\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8044,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x20\\xec\\x00\\x00\\x08\\x11\\x20\\x31\\x60\\x00\\x14\\x43\\x04\\x34\\x44\\x40\\x5b\\xa0\\x00\\x04\\x00\\x21\\x6a\\x00\\x80\\x00\\x11\\x21\\x70\\x00\\x3f\\xff\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x08\\xe8\\x84\\x20\\x32\\x50\\x08\\x68\\x84\\x20\\x31\\x50\\x08\\x5e\\x84\\x20\\x30\\x50\\x0f\\xc4\\x07\\x10\\x34\\x44\\x10\\x5b\\x84\\x6f\\xf3\\x07\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x02\\x00\\x21\\x40\\xfc\\x90\\x3d\\xd4\\x00\\x04\\xfc\\x84\\x00\\x00\\x21\\x04\\xfd\\x84\\x00\\x08\\x21\\x00\\x04\\x00\\x21\\x81\\x00\\xc0\\x00\\x11\\x04\\x5b\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x02\\x00\\x21\\x70\\x06\\x07\\x10\\xfe\\x84\\x30\\x20\\x08\\x00\\x03\\x11\\x10\\x00\\x08\\x40\\x59\\x90\\x04\\xff\\x84\\x40\\x58\\xa0\\x10\\x59\\x84\\x20\\x0f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x59\\xa0\\x20\\x00\\x11\\x70\\x1e\\x07\\x10\\x00\\x08\\x00\\x0b\\x11\\x0f\\xe4\\x07\\x10\\x59\\x84\\x00\\x00\\x08\\x20\\x30\\x50\\x40\\x59\\xa0\\x70\\x06\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x00\\x08\\x00\\x0a\\x11\\x0f\\xec\\x07\\x08\\x34\\x44\\x02\\x10\\x11\\x10\\x58\\x84\\x20\\x0f\\x08\\x40\\x58\\xa0\\x20\\x00\\x11\\x30\\x08\\x07\\x0f\\xf4\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x58\\x84\\x00\\x00\\x08\\x20\\x30\\x50\\x40\\x58\\xa0\\x70\\x06\\x07\\x10\\x00\\x08\\x00\\x05\\x11\\x00\\x04\\x00\\x10\\x5a\\x84\\x00\\x00\\x08\\x00\\x01\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x5a\\xa0\\x08\\x34\\x44\\x02\\x00\\x11\\x30\\x08\\x07\\x60\\x00\\x08\\x00\\x00\\x11\\x40\\x5a\\xa0\\x8f\\x4f\\x07\\x40\\x7e\\xa0\\x00\\x04\\x00\\x3c\\xdd\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x00\\x20\\xa8\\x14\\x43\\x04\\xa7\\x84\\x20\\x8e\\x08\\x40\\xc4\\x90\\x40\\xaf\\xa0\\x20\\x0f\\x08\\x40\\xc5\\x90\\x40\\xa7\\xa0\\x3c\\xe7\\x00\\x10\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8020,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x28\\x14\\x43\\x04\\x27\\x84\\x20\\x8e\\x08\\x40\\x44\\x90\\x40\\x2f\\xa0\\x20\\x0f\\x08\\x40\\x45\\x90\\x40\\x27\\xa0\\x00\\x04\\x00\\x10\\xf0\\x44\\x50\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\xff\\xf7\\x11\\x93\\x04\\x07\\x20\\xf0\\x60\\x04\\x61\\x84\\x04\\x5c\\x84\\x40\\x57\\xa0\\x00\\x04\\x00\\x10\\x61\\x84\\x00\\x20\\x08\\x20\\x1f\\x08\\x40\\xff\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x00\\x08\\x40\\x5c\\x90\\x40\\x57\\xa0\\x04\\x74\\x84\\x10\\x00\\x20\\x00\\x00\\x08\\x40\\x74\\xa0\\x00\\x01\\x11\\x20\\x05\\x07\\x00\\x40\\x21\\x70\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x7f\\xff\\x21\\x08\\xff\\x84\\x42\\x00\\x90\\x85\\x02\\x07\\x20\\xf0\\x60\\x7f\\xff\\x11\\x60\\x20\\x08\\x00\\xd0\\x11\\x40\\x00\\x08\\x00\\x02\\x11\\x86\\x1b\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x74\\xa0\\x08\\x6f\\x84\\x00\\x00\\x11\\x04\\xf1\\x84\\x00\\x40\\x21\\x21\\xf7\\x00\\x02\\x00\\x11\\x60\\x07\\x07\\x10\\x20\\x08\\x40\\xc3\\x90\\x20\\x2f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x80\\x00\\x11\\x70\\x02\\x07\\x7f\\xff\\x11\\x10\\x00\\x08\\x40\\x8d\\x90\\x40\\x85\\xa0\\x08\\x6e\\x84\\x00\\x00\\x11\\x04\\xf0\\x84\\x00\\x40\\x21\\x22\\x07\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x02\\x11\\x60\\x07\\x07\\x10\\x20\\x08\\x40\\x43\\x90\\x20\\x2f\\x08\\x80\\x00\\x11\\x70\\x02\\x07\\x7f\\xff\\x11\\x10\\x00\\x08\\x40\\x0d\\x90\\x40\\x05\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\xec\\x84\\x00\\x10\\x08\\x10\\xe7\\x84\\x40\\xe7\\xa0\\x20\\x0f\\x08\\x40\\xef\\xa0\\x10\\x6d\\x84\\x00\\x10\\x08\\x10\\x6c\\x84\\x40\\x6c\\xa0\\x20\\x0f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x7d\\xa0\\x7f\\xff\\x11\\x00\\x04\\x00\\x10\\xef\\x84\\x00\\x10\\x08\\x10\\xee\\x84\\x40\\xee\\xa0\\x20\\x0f\\x08\\x40\\xbd\\xa0\\x10\\x7d\\x84\\x00\\x10\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x7c\\x84\\x40\\x7c\\xa0\\x20\\x0f\\x08\\x40\\x3d\\xa0\\x40\\x00\\x11\\x3e\\x9b\\x00\\xfb\\xff\\x21\\x6f\\x14\\x43\\x3e\\x9e\\x00\\xff\\xfb\\x21\\x6e\\x14\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8043,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x3d\\x57\\x00\\x40\\xaf\\xa0\\xa0\\x14\\x43\\x3d\\x5a\\x00\\x40\\x2f\\xa0\\x20\\x14\\x43\\x00\\x04\\x00\\x3d\\x5e\\x00\\x40\\xa5\\xa0\\xb0\\x14\\x43\\x3d\\x61\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x25\\xa0\\x30\\x14\\x43\\x00\\x00\\x00\\x22\\x28\\x00\\x00\\x02\\x07\\x22\\x26\\x00\\x8a\\x03\\x07\\x89\\x04\\x07\\x40\\x7e\\xa0\\x40\\xbd\\x90\\x98\\x14\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8043,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x9c\\x84\\x20\\x8f\\x08\\x40\\x9a\\x90\\x40\\x99\\xa0\\x20\\x2e\\x08\\x40\\xbd\\x90\\x00\\x10\\x08\\x40\\x9b\\xa0\\x20\\x0e\\x08\\x7f\\xff\\x21\\x40\\xf5\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8090,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x22\\x3c\\x00\\x00\\x02\\x07\\x22\\x3a\\x00\\x82\\x03\\x07\\x81\\x04\\x07\\x40\\x7e\\xa0\\x40\\x3d\\x90\\x18\\x14\\x43\\x10\\x1c\\x84\\x20\\x8f\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8008,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x1a\\x90\\x40\\x19\\xa0\\x20\\x2e\\x08\\x40\\x3d\\x90\\x00\\x10\\x08\\x40\\x1b\\xa0\\x20\\x0e\\x08\\x7f\\xff\\x21\\x40\\xf5\\x90\\x3d\\x8c\\x00\\xb8\\x14\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8043,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\xc2\\xa0\\x3d\\x8f\\x00\\x38\\x14\\x43\\x40\\x42\\xa0\\x00\\x04\\x00\\x10\\x51\\x84\\x20\\x0f\\x08\\x7f\\xc0\\x11\\x40\\x51\\xa0\\x08\\xbb\\x84\\x08\\x3b\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\xcb\\x90\\x11\\x9e\\x02\\x07\\xc7\\x00\\x11\\x40\\x7f\\xa0\\x08\\xba\\x84\\x08\\x3a\\x84\\x74\\x70\\x11\\x9e\\x02\\x07\\x59\\x00\\x11\\x40\\x7f\\xa0\\x3e\\xed\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\xfd\\xff\\x21\\xf1\\x14\\x43\\x3e\\xf0\\x00\\xff\\xfd\\x21\\xf0\\x14\\x43\\x00\\x04\\x00\\x04\\xb9\\x84\\x40\\xb6\\xa0\\x04\\x39\\x84\\x40\\x36\\xa0\\x00\\x04\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x3e\\xc3\\x00\\x40\\x87\\xa0\\x80\\x14\\x43\\x3e\\xc6\\x00\\x40\\x07\\xa0\\x00\\x14\\x43\\x00\\x04\\x00\\x00\\x00\\x00\\x04\\xf5\\x84\\x00\\x00\\x21\\x70\\x03\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\xf5\\x84\\x10\\x00\\x08\\x40\\xf3\\x90\\x40\\xf5\\xa0\\x3e\\xd2\\x00\\x40\\x85\\xa0\\x88\\x14\\x43\\x3e\\xd5\\x00\\x40\\x05\\xa0\\x08\\x14\\x43\\x00\\x04\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8000,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x01\\x07\\x00\\x02\\x07\\x00\\x03\\x07\\x00\\x04\\x07\\x00\\x06\\x07\\x00\\x16\\x07\\x00\\x1e\\x07\\x00\\x24\\x07\\x00\\x3c\\x07\\x00\\x72\\x07\\x00\\x8d\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\xe0\\x07\\x00\\xf6\\x07\\x01\\x9f\\x07\\x01\\xd1\\x07\\x00\\x10\\x07\\x1f\\xff\\x07\\x20\\x03\\x60\\x0f\\x5f\\x07\\x08\\xfa\\x84\\x04\\x11\\x44\\xff\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x2f\\x63\\x07\\x70\\x10\\x08\\x00\\xf0\\x21\\x50\\x00\\x08\\x00\\xf0\\x21\\x40\\xf9\\x90\\x00\\x08\\x07\\x3e\\x79\\x00\\x0f\\x6b\\x07\\x90\\x01\\x07\\x40\\xf9\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x80a0,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x3f\\x6e\\x07\\x70\\x00\\x08\\x00\\x7f\\x11\\x40\\xf8\\xa0\\x9d\\x07\\x07\\x20\\x12\\x60\\x08\\xfa\\x84\\x04\\x11\\x44\\x3e\\x54\\x00\\x00\\x16\\x07\\x48\\x80\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x08\\x09\\x44\\x40\\x75\\x90\\x7f\\xef\\x07\\x10\\x00\\x20\\x00\\x10\\x08\\xff\\xff\\x21\\x06\\x00\\x84\\x40\\xfb\\xa0\\x60\\x00\\x08\\x00\\x00\\x21\\x40\\xff\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8090,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\xfb\\x84\\x60\\x20\\x08\\x40\\xfb\\x90\\x30\\x00\\x08\\x00\\x08\\x11\\x3d\\xea\\x00\\x04\\xfb\\x84\\x3d\\xec\\x00\\x04\\xff\\x84\\x40\\xf8\\xa0\\x04\\x11\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8044,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x8f\\xff\\x07\\x20\\x19\\x60\\x3e\\xd2\\x00\\x00\\x31\\x07\\x00\\x01\\x00\\x00\\x33\\x07\\x00\\x02\\x00\\x27\\x18\\x43\\x75\\x00\\x43\\x8f\\xff\\x07\\x20\\x19\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8060,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x04\\xf5\\x84\\x40\\xf2\\xa0\\x04\\x51\\x84\\x7f\\xff\\x21\\x04\\xf5\\x84\\x00\\x00\\x21\\x04\\xf3\\x84\\x00\\x10\\x21\\x04\\xf2\\x84\\x0c\\x00\\x21\\x04\\x72\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8044,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x77\\x21\\x3f\\xfa\\x07\\x70\\x20\\x08\\x00\\x00\\x11\\x10\\x2d\\x44\\x10\\x2c\\x44\\x00\\x20\\x08\\x10\\x00\\x11\\x00\\x00\\x08\\x00\\x00\\x11\\x80\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8021,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x04\\x73\\x44\\x07\\x07\\x21\\x04\\x72\\x44\\x00\\x07\\x21\\x04\\x73\\x44\\x07\\x77\\x21\\x04\\x73\\x44\\x00\\x70\\x21\\x04\\x2e\\x44\\x04\\x2d\\x44\\x04\\x2c\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8044,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x80\\x00\\x21\\x04\\x1c\\x44\\x04\\x1b\\x44\\x0d\\x00\\x21\\x04\\x1c\\x44\\x04\\x1b\\x44\\x0c\\x80\\x21\\x04\\x1c\\x44\\x04\\x1b\\x44\\x1f\\x08\\x21\\x0f\\x18\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8043,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x08\\x28\\x44\\x01\\x11\\x11\\x08\\x5d\\x84\\x10\\x00\\x10\\x10\\x00\\x08\\x40\\x00\\x21\\x30\\x04\\x07\\x40\\xff\\x90\\x50\\x20\\x08\\xc0\\x00\\x11\\x10\\xff\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x20\\x08\\x00\\x40\\x11\\x40\\x00\\x08\\x00\\x01\\x11\\x20\\x51\\x60\\x10\\x00\\x44\\x60\\x00\\x08\\x40\\x54\\x90\\x20\\x00\\x60\\x00\\x79\\x07\\x81\\x48\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x80\\x03\\x07\\x40\\xf8\\xa0\\x48\\xc0\\x11\\x00\\x77\\x07\\x00\\x78\\x07\\x00\\x79\\x07\\x00\\x04\\x07\\x00\\x7b\\x07\\x00\\x7c\\x07\\x00\\x7d\\x07\\x00\\x55\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8007,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x7f\\x07\\x00\\x80\\x07\\x00\\x81\\x07\\x00\\x74\\x07\\x00\\x83\\x07\\x00\\x82\\x07\\x00\\x85\\x07\\x00\\x86\\x07\\x0f\\xef\\x07\\x1f\\xff\\x07\\xff\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8011,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x10\\x00\\x20\\x30\\x10\\x08\\x00\\x01\\x21\\x50\\x00\\x08\\x00\\x0f\\x21\\x40\\xf9\\x90\\x30\\x90\\x07\\x70\\x10\\x08\\x00\\x80\\x21\\x50\\x00\\x08\\x00\\xf0\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8021,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x08\\xf9\\x84\\x04\\xf8\\x84\\x2f\\xff\\x07\\x3e\\x59\\x00\\x04\\xf1\\x84\\x04\\xf0\\x84\\x04\\x5a\\x84\\x00\\x00\\x21\\x04\\xf6\\x84\\x00\\x02\\x21\\x04\\xfa\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8084,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x40\\x00\\x21\\x04\\xf7\\x84\\x01\\x04\\x21\\x04\\x1c\\x44\\x04\\x1b\\x44\\x0b\\x23\\x21\\x0f\\x18\\x43\\x04\\x70\\x44\\x06\\x66\\x21\\x04\\x3b\\x44\\x04\\x39\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8044,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x80\\x21\\x04\\x3c\\x44\\x2a\\x0a\\x21\\x04\\x2f\\x44\\x00\\x44\\x21\\x04\\x29\\x44\\x00\\x00\\x21\\x03\\x19\\x42\\x4e\\x19\\x43\\x0c\\x59\\x43\\x27\\x18\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8043,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x15\\x00\\x43\\x04\\x22\\x44\\x03\\x07\\x21\\x04\\x21\\x44\\x11\\x11\\x21\\x04\\x20\\x44\\x33\\x33\\x21\\x00\\x00\\x42\\xc0\\x3d\\x42\\x80\\x3d\\x43\\x04\\x35\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8044,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x21\\x04\\x05\\x43\\x42\\xcd\\x00\",\n    .reg_data_seq_size = 9,\n  },{\n    .reg_addr = 0x88ef,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x20\\x00\\x18\\x00\\x00\\x00\\x00\\xab\\x0a\\x00\\x40\\x00\\x40\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x80\\x00\\x00\\x27\\x83\\x64\\x7e\\xca\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x88b2,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x7f\\x59\\x7f\\xbe\\x7f\\xfe\\x7f\\xfe\\x7f\\xee\\x73\\x54\\x4c\\x70\\x5a\\x00\\x6b\\x0e\\x6b\\x1c\\x5b\\xcb\\x32\\x8c\\x0b\\xd2\\x13\\x07\\x28\\x01\\x49\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\xff\\x7f\\x0b\\x97\\x14\\xae\\xf7\\x53\\x26\\x63\\x07\\x46\\x00\\x20\\x00\\x89\\x00\\x40\\x80\\x41\\x00\\x7f\\xff\\x7f\\xd3\\x09\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x88ff,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x7f\\x00\\x00\\x00\\x00\\x90\\xcb\\x70\\x74\\xfe\\x7f\\x52\\x09\\x00\\x00\\xfe\\x7f\\x00\\x00\\x00\\x00\\x00\\xf2\\x00\\x40\\xf0\\x7f\\x00\\x0c\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x4a\\x00\\x4a\\x00\\x24\\xff\\x7f\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xff\\x7f\\x00\\x00\\x00\\x50\\x00\\x30\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\xa0\\x00\\x00\\x03\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x20\\xff\\x7f\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\xff\\x7f\\x00\\x78\\x00\\x08\\x00\\x00\\x10\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xff\\x7f\\x00\\x40\\x00\\x40\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x80\\xff\\x7f\\x1c\\x1b\\xc5\\x07\\xc0\\x20\\x12\\xf0\\x00\\x10\\x10\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x02\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xcc\\x59\\x00\\x00\\x00\\x40\\x00\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0a\\x00\\x00\\x00\\x00\\x00\\x00\\x08\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xff\\x7f\\x0b\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8897,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x14\\xae\\xf7\\x53\\x26\\x63\\x07\\x46\\x00\\x20\\x00\\x89\\x00\\x40\\x80\\x41\\x00\\x7f\\xff\\x7f\\xd3\\x09\\x00\\x00\\xff\\x7f\\x00\\x00\\x00\\x00\\x90\\xcb\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8870,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x74\\xfe\\x7f\\x52\\x09\\x00\\x00\\xfe\\x7f\\x00\\x00\\x00\\x00\\x00\\xf2\\x00\\x40\\xf0\\x7f\\x00\\x0c\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x4a\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x884a,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x24\\xff\\x7f\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xff\\x7f\\x00\\x00\\x00\\x50\\x00\\x30\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xa0\\x00\\x00\\x03\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8800,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x20\\xff\\x7f\\x00\\x00\\x00\\x00\\x00\\x00\\xff\\x7f\\x00\",\n    .reg_data_seq_size = 32,\n  },{\n    .reg_addr = 0x8878,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0000,\n    .data_type = MSM_CAMERA_I2C_SEQ_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\\x00\\x08\\x00\\x00\\x10\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xff\\x7f\\x00\\x40\\x00\\x40\",\n    .reg_data_seq_size = 18,\n  },{\n    .reg_addr = 0x8205,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0c00,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8205,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0d00,\n    .data_type = MSM_CAMERA_I2C_WORD_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  },{\n    .reg_addr = 0x8c01,\n    .addr_type = MSM_CAMERA_I2C_WORD_ADDR,\n    .reg_data = 0x0001,\n    .data_type = MSM_CAMERA_I2C_BYTE_DATA,\n    .i2c_operation = MSM_OIS_WRITE,\n    .delay = 0,\n    .reg_data_seq = \"\",\n    .reg_data_seq_size = 0,\n  }\n};\n\n/*\n// still mode settings:\n  {0x847f, 0x0c0c,}, //_M_EQCTL\n\n  {0x8436, 0xfd7f,}, //_M_Kgxdr\n  {0x8440, 0xf07f,}, //_M_X_LMT\n  {0x8443, 0xb41e,}, //_M_X_TGT\n  {0x841b, 0x4001,}, //_M_Kgx10\n\n  {0x84b6, 0xfd7f,}, //_M_Kgydr\n  {0x84c0, 0xf07f,}, //_M_Y_LMT\n  {0x84c3, 0xb41e,}, //_M_Y_TGT\n  {0x849b, 0x4001,}, //_M_Kgy10\n\n  {0x8438, 0x2d0f,}, //_M_Kgx11\n  {0x84b8, 0x2d0f,}, //_M_Kgy11\n  {0x8447, 0x002b,}, //_M_KgxTG\n  {0x84c7, 0x002b,}, //_M_KgyTG\n\n  {0x847f, 0x0d0d,}, //_M_EQCTL\n*/\n\nstatic struct msm_camera_i2c_reg_array init_array_s5k3p8sp[] = {\n  {0x6028,0x2000,0}, {0x6214,0x7971,0}, {0x6218,0x7150,0}, {0x30e,0x3d,0},\n  {0x6028,0x2000,0}, {0x602a,0x2f38,0}, {0x6f12,0x88,0}, {0x6f12,0xd70,0},\n  {0x344,0x18,0},\n  {0x348,0x1217,0},  // last_pixel = 0x90C*2\n  {0x346,0x18,0},\n  {0x34a,0xd97,0},   // last_line = 0x6CC*2\n  {0x34c,0x900,0},   // width?\n  {0x34e,0x6c0,0},   // height?\n  {0x342,0x1400,0},  // line_length_pclk\n  {0x340,0xe3b,0},   // frame_length_lines\n  {0x202,0x200,0},   // integ_time\n  {0x200,0x618,0},\n  {0x900,0x122,0}, {0x380,0x1,0}, {0x382,0x3,0}, {0x384,0x3,0}, {0x386,0x1,0}, {0x400,0x0,0}, {0x404,0x10,0},\n  {0x3604,0x2,0}, {0x3606,0x103,0}, {0xf496,0x48,0}, {0xf470,0x20,0}, {0xf43a,0x15,0}, {0xf484,0x6,0}, {0xf440,0xaf,0}, {0xf442,0x44c6,0},\n  {0xf408,0xfff7,0}, {0x3664,0x19,0}, {0xf494,0x1010,0}, {0x367a,0x100,0}, {0x362a,0x104,0}, {0x362e,0x404,0}, {0x32b2,0x8,0}, {0x3286,0x3,0}, {0x328a,0x5,0},\n  {0xf47c,0x1f,0}, {0xf62e,0xc5,0}, {0xf630,0xcd,0}, {0xf632,0xdd,0}, {0xf634,0xe5,0}, {0xf636,0xf5,0}, {0xf638,0xfd,0}, {0xf63a,0x10d,0}, {0xf63c,0x115,0}, {0xf63e,0x125,0}, {0xf640,0x12d,0},\n  {0x6028,0x2000,0}, {0x602a,0x1704,0}, {0x6f12,0x8011,0}, {0x3070,0x0,0}, {0xb0e,0x0,0}, {0x317a,0x7,0}, {0x31c0,0xc8,0}, {0x1006,0x4,0}, {0x31a4,0x102,0},\n};\n\nstatic struct msm_camera_i2c_reg_array init_array_ov8865[] = {\n// round 1\n//{0x103,0x1,0}, // software reset\n{0x100,0x0,0}, // standby on\n{0x3638,0xff,0},\n{0x302,0x1e,0}, {0x303,0x0,0}, {0x304,0x3,0}, {0x30d,0x1e,0}, {0x30e,0x0,0}, {0x30f,0x9,0}, {0x312,0x1,0}, {0x31e,0xc,0}, // PLL control\n{0x3015,0x1,0}, {0x3018,0x72,0}, {0x3020,0x93,0}, {0x3022,0x1,0},\n{0x3031,0xa,0}, // 10-bit mode\n{0x3106,0x1,0}, {0x3305,0xf1,0}, {0x3308,0x0,0}, {0x3309,0x28,0}, {0x330a,0x0,0}, {0x330b,0x20,0}, {0x330c,0x0,0}, {0x330d,0x0,0}, {0x330e,0x0,0}, {0x330f,0x40,0}, {0x3307,0x4,0}, {0x3604,0x4,0}, {0x3602,0x30,0}, {0x3605,0x0,0}, {0x3607,0x20,0}, {0x3608,0x11,0}, {0x3609,0x68,0}, {0x360a,0x40,0}, {0x360c,0xdd,0}, {0x360e,0xc,0}, {0x3610,0x7,0}, {0x3612,0x86,0}, {0x3613,0x58,0}, {0x3614,0x28,0}, {0x3617,0x40,0}, {0x3618,0x5a,0}, {0x3619,0x9b,0}, {0x361c,0x0,0}, {0x361d,0x60,0}, {0x3631,0x60,0}, {0x3633,0x10,0}, {0x3634,0x10,0}, {0x3635,0x10,0}, {0x3636,0x10,0}, {0x3641,0x55,0}, {0x3646,0x86,0}, {0x3647,0x27,0}, {0x364a,0x1b,0}, {0x3500,0x0,0}, {0x3501,0x4c,0}, {0x3502,0x0,0}, {0x3503,0x0,0}, {0x3508,0x2,0},\n{0x3509,0x0,0}, // AEC GAIN\n{0x3700,0x24,0}, {0x3701,0xc,0}, {0x3702,0x28,0}, {0x3703,0x19,0}, {0x3704,0x14,0}, {0x3705,0x0,0}, {0x3706,0x38,0}, {0x3707,0x4,0}, {0x3708,0x24,0}, {0x3709,0x40,0}, {0x370a,0x0,0}, {0x370b,0xb8,0}, {0x370c,0x4,0}, {0x3718,0x12,0}, {0x3719,0x31,0}, {0x3712,0x42,0}, {0x3714,0x12,0}, {0x371e,0x19,0}, {0x371f,0x40,0}, {0x3720,0x5,0}, {0x3721,0x5,0}, {0x3724,0x2,0}, {0x3725,0x2,0}, {0x3726,0x6,0}, {0x3728,0x5,0}, {0x3729,0x2,0}, {0x372a,0x3,0}, {0x372b,0x53,0}, {0x372c,0xa3,0}, {0x372d,0x53,0}, {0x372e,0x6,0}, {0x372f,0x10,0}, {0x3730,0x1,0}, {0x3731,0x6,0}, {0x3732,0x14,0}, {0x3733,0x10,0}, {0x3734,0x40,0}, {0x3736,0x20,0}, {0x373a,0x2,0}, {0x373b,0xc,0}, {0x373c,0xa,0}, {0x373e,0x3,0}, {0x3755,0x40,0}, {0x3758,0x0,0}, {0x3759,0x4c,0}, {0x375a,0x6,0}, {0x375b,0x13,0}, {0x375c,0x40,0}, {0x375d,0x2,0}, {0x375e,0x0,0}, {0x375f,0x14,0}, {0x3767,0x1c,0}, {0x3768,0x4,0}, {0x3769,0x20,0}, {0x376c,0xc0,0}, {0x376d,0xc0,0}, {0x376a,0x8,0}, {0x3761,0x0,0}, {0x3762,0x0,0}, {0x3763,0x0,0}, {0x3766,0xff,0}, {0x376b,0x42,0}, {0x3772,0x23,0}, {0x3773,0x2,0}, {0x3774,0x16,0}, {0x3775,0x12,0}, {0x3776,0x8,0}, {0x37a0,0x44,0}, {0x37a1,0x3d,0}, {0x37a2,0x3d,0}, {0x37a3,0x1,0}, {0x37a4,0x0,0}, {0x37a5,0x8,0}, {0x37a6,0x0,0}, {0x37a7,0x44,0}, {0x37a8,0x58,0}, {0x37a9,0x58,0}, {0x3760,0x0,0}, {0x376f,0x1,0}, {0x37aa,0x44,0}, {0x37ab,0x2e,0}, {0x37ac,0x2e,0}, {0x37ad,0x33,0}, {0x37ae,0xd,0}, {0x37af,0xd,0}, {0x37b0,0x0,0}, {0x37b1,0x0,0}, {0x37b2,0x0,0}, {0x37b3,0x42,0}, {0x37b4,0x42,0}, {0x37b5,0x33,0}, {0x37b6,0x0,0}, {0x37b7,0x0,0}, {0x37b8,0x0,0}, {0x37b9,0xff,0}, {0x3800,0x0,0}, {0x3801,0xc,0}, {0x3802,0x0,0}, {0x3803,0xc,0},\n{0x3804,0xc,0}, {0x3805,0xd3,0},  // 3283\n{0x3806,0x9,0}, {0x3807,0xa3,0},  // 2467\n{0x3808,0x6,0}, {0x3809,0x60,0},  // 0x660 = 1632 (width)\n{0x380a,0x4,0}, {0x380b,0xc8,0},  // 0x4c8 = 1224 (height)\n{0x380c,0x6,0}, {0x380d,0x42,0},  // line_length_pck\n{0x380e,0x5,0}, {0x380f,0xda,0},  // frame_length_lines\n{0x3810,0x0,0}, {0x3811,0x4,0}, {0x3813,0x4,0},\n{0x3814,0x3,0}, {0x3815,0x1,0},   // H-binning\n{0x3820,0x6,0}, // format1\n{0x3821,0x40,0}, // format2\n{0x382a,0x3,0}, {0x382b,0x1,0},   // V-binning\n{0x382d,0x7f,0}, {0x3830,0x8,0}, {0x3836,0x2,0}, {0x3837,0x18,0},\n{0x3841,0xff,0},\n{0x3846,0x88,0}, {0x3d85,0x6,0}, {0x3d8c,0x75,0}, {0x3d8d,0xef,0}, {0x3f08,0xb,0}, {0x4000,0xf1,0}, {0x4001,0x14,0}, {0x4005,0x10,0}, {0x4006,0x1,0}, {0x4007,0x1,0}, {0x400b,0xc,0}, {0x400d,0x10,0}, {0x401b,0x0,0}, {0x401d,0x0,0}, {0x4020,0x0,0}, {0x4021,0x0,0}, {0x4022,0x4,0}, {0x4023,0x1f,0}, {0x4024,0x6,0}, {0x4025,0x20,0}, {0x4026,0x6,0}, {0x4027,0x4f,0}, {0x4028,0x0,0}, {0x4029,0x2,0}, {0x402a,0x4,0}, {0x402b,0x4,0}, {0x402c,0x2,0}, {0x402d,0x2,0}, {0x402e,0x8,0}, {0x402f,0x2,0}, {0x401f,0x0,0}, {0x4034,0x3f,0}, {0x4300,0xff,0}, {0x4301,0x0,0}, {0x4302,0xf,0}, {0x4500,0x40,0}, {0x4503,0x10,0}, {0x4601,0x74,0}, {0x481f,0x32,0}, {0x4837,0x15,0}, {0x4850,0x10,0}, {0x4851,0x32,0}, {0x4b00,0x2a,0}, {0x4b0d,0x0,0}, {0x4d00,0x4,0}, {0x4d01,0x18,0}, {0x4d02,0xc3,0}, {0x4d03,0xff,0}, {0x4d04,0xff,0}, {0x4d05,0xff,0}, {0x5000,0x96,0}, {0x5001,0x1,0}, {0x5002,0x8,0}, {0x5901,0x0,0},\n{0x5e00,0x0,0},\n//{0x5e00,0x80,0},\n{0x5e01,0x41,0}, {0x5b00,0x2,0}, {0x5b01,0xd0,0}, {0x5b02,0x3,0}, {0x5b03,0xff,0}, {0x5b05,0x6c,0}, {0x5780,0xfc,0}, {0x5781,0xdf,0}, {0x5782,0x3f,0}, {0x5783,0x8,0}, {0x5784,0xc,0}, {0x5786,0x20,0}, {0x5787,0x40,0}, {0x5788,0x8,0}, {0x5789,0x8,0}, {0x578a,0x2,0}, {0x578b,0x1,0}, {0x578c,0x1,0}, {0x578d,0xc,0}, {0x578e,0x2,0}, {0x578f,0x1,0}, {0x5790,0x1,0}, {0x5800,0x1d,0}, {0x5801,0xe,0}, {0x5802,0xc,0}, {0x5803,0xc,0}, {0x5804,0xf,0}, {0x5805,0x22,0}, {0x5806,0xa,0}, {0x5807,0x6,0}, {0x5808,0x5,0}, {0x5809,0x5,0}, {0x580a,0x7,0}, {0x580b,0xa,0}, {0x580c,0x6,0}, {0x580d,0x2,0}, {0x580e,0x0,0}, {0x580f,0x0,0}, {0x5810,0x3,0}, {0x5811,0x7,0}, {0x5812,0x6,0}, {0x5813,0x2,0}, {0x5814,0x0,0}, {0x5815,0x0,0}, {0x5816,0x3,0}, {0x5817,0x7,0}, {0x5818,0x9,0}, {0x5819,0x6,0}, {0x581a,0x4,0}, {0x581b,0x4,0}, {0x581c,0x6,0}, {0x581d,0xa,0}, {0x581e,0x19,0}, {0x581f,0xd,0}, {0x5820,0xb,0}, {0x5821,0xb,0}, {0x5822,0xe,0}, {0x5823,0x22,0}, {0x5824,0x23,0}, {0x5825,0x28,0}, {0x5826,0x29,0}, {0x5827,0x27,0}, {0x5828,0x13,0}, {0x5829,0x26,0}, {0x582a,0x33,0}, {0x582b,0x32,0}, {0x582c,0x33,0}, {0x582d,0x16,0}, {0x582e,0x14,0}, {0x582f,0x30,0}, {0x5830,0x31,0}, {0x5831,0x30,0}, {0x5832,0x15,0}, {0x5833,0x26,0}, {0x5834,0x23,0}, {0x5835,0x21,0}, {0x5836,0x23,0}, {0x5837,0x5,0}, {0x5838,0x36,0}, {0x5839,0x27,0}, {0x583a,0x28,0}, {0x583b,0x26,0}, {0x583c,0x24,0}, {0x583d,0xdf,0},\n//{0x100,0x1,0},\n// round 2 (color calibration)\n{0x7010,0x0,0}, {0x7011,0x0,0}, {0x7012,0x0,0}, {0x7013,0x0,0}, {0x7014,0x0,0}, {0x7015,0x0,0}, {0x7016,0x0,0}, {0x7017,0x0,0}, {0x7018,0x0,0}, {0x7019,0x0,0}, {0x701a,0x0,0}, {0x701b,0x0,0}, {0x701c,0x0,0}, {0x701d,0x0,0}, {0x701e,0x0,0}, {0x701f,0x0,0}, {0x7020,0x0,0}, {0x7021,0x0,0}, {0x7022,0x0,0}, {0x7023,0x0,0}, {0x7024,0x0,0}, {0x7025,0x0,0}, {0x7026,0x0,0}, {0x7027,0x0,0}, {0x7028,0x0,0}, {0x7029,0x0,0}, {0x702a,0x0,0}, {0x702b,0x0,0}, {0x702c,0x0,0}, {0x702d,0x0,0}, {0x702e,0x0,0}, {0x702f,0x0,0}, {0x7030,0x0,0}, {0x7031,0x0,0}, {0x7032,0x0,0}, {0x7033,0x0,0}, {0x7034,0x0,0}, {0x7035,0x0,0}, {0x7036,0x0,0}, {0x7037,0x0,0}, {0x7038,0x0,0}, {0x7039,0x0,0}, {0x703a,0x0,0}, {0x703b,0x0,0}, {0x703c,0x0,0}, {0x703d,0x0,0}, {0x703e,0x0,0}, {0x703f,0x0,0}, {0x7040,0x0,0}, {0x7041,0x0,0}, {0x7042,0x0,0}, {0x7043,0x0,0}, {0x7044,0x0,0}, {0x7045,0x0,0}, {0x7046,0x0,0}, {0x7047,0x0,0}, {0x7048,0x0,0}, {0x7049,0x0,0}, {0x704a,0x0,0}, {0x704b,0x0,0}, {0x704c,0x0,0}, {0x704d,0x0,0}, {0x704e,0x0,0}, {0x704f,0x0,0}, {0x7050,0x0,0}, {0x7051,0x0,0}, {0x7052,0x0,0}, {0x7053,0x0,0}, {0x7054,0x0,0}, {0x7055,0x0,0}, {0x7056,0x0,0}, {0x7057,0x0,0}, {0x7058,0x0,0}, {0x7059,0x0,0}, {0x705a,0x0,0}, {0x705b,0x0,0}, {0x705c,0x0,0}, {0x705d,0x0,0}, {0x705e,0x0,0}, {0x705f,0x0,0}, {0x7060,0x0,0}, {0x7061,0x0,0}, {0x7062,0x0,0}, {0x7063,0x0,0}, {0x7064,0x0,0}, {0x7065,0x0,0}, {0x7066,0x0,0}, {0x7067,0x0,0}, {0x7068,0x0,0}, {0x7069,0x0,0}, {0x706a,0x0,0}, {0x706b,0x0,0}, {0x706c,0x0,0}, {0x706d,0x0,0}, {0x706e,0x0,0}, {0x706f,0x0,0}, {0x7070,0x0,0}, {0x7071,0x0,0}, {0x7072,0x0,0}, {0x7073,0x0,0}, {0x7074,0x0,0}, {0x7075,0x0,0}, {0x7076,0x0,0}, {0x7077,0x0,0}, {0x7078,0x0,0}, {0x7079,0x0,0}, {0x707a,0x0,0}, {0x707b,0x0,0}, {0x707c,0x0,0}, {0x707d,0x0,0}, {0x707e,0x0,0}, {0x707f,0x0,0}, {0x7080,0x0,0}, {0x7081,0x0,0}, {0x7082,0x0,0}, {0x7083,0x0,0}, {0x7084,0x0,0}, {0x7085,0x0,0}, {0x7086,0x0,0}, {0x7087,0x0,0}, {0x7088,0x0,0}, {0x7089,0x0,0}, {0x708a,0x0,0}, {0x708b,0x0,0}, {0x708c,0x0,0}, {0x708d,0x0,0}, {0x708e,0x0,0}, {0x708f,0x0,0}, {0x7090,0x0,0}, {0x7091,0x0,0}, {0x7092,0x0,0}, {0x7093,0x0,0}, {0x7094,0x0,0}, {0x7095,0x0,0}, {0x7096,0x0,0}, {0x7097,0x0,0}, {0x7098,0x0,0}, {0x7099,0x0,0}, {0x709a,0x0,0}, {0x709b,0x0,0}, {0x709c,0x0,0}, {0x709d,0x0,0}, {0x709e,0x0,0}, {0x709f,0x0,0}, {0x70a0,0x0,0}, {0x70a1,0x0,0}, {0x70a2,0x0,0}, {0x70a3,0x0,0}, {0x70a4,0x0,0}, {0x70a5,0x0,0}, {0x70a6,0x0,0}, {0x70a7,0x0,0}, {0x70a8,0x0,0}, {0x70a9,0x0,0}, {0x70aa,0x0,0}, {0x70ab,0x0,0}, {0x70ac,0x0,0}, {0x70ad,0x0,0}, {0x70ae,0x0,0}, {0x70af,0x0,0}, {0x70b0,0x0,0}, {0x70b1,0x0,0}, {0x70b2,0x0,0}, {0x70b3,0x0,0}, {0x70b4,0x0,0}, {0x70b5,0x0,0}, {0x70b6,0x0,0}, {0x70b7,0x0,0}, {0x70b8,0x0,0}, {0x70b9,0x0,0}, {0x70ba,0x0,0}, {0x70bb,0x0,0}, {0x70bc,0x0,0}, {0x70bd,0x0,0}, {0x70be,0x0,0}, {0x70bf,0x0,0}, {0x70c0,0x0,0}, {0x70c1,0x0,0}, {0x70c2,0x0,0}, {0x70c3,0x0,0}, {0x70c4,0x0,0}, {0x70c5,0x0,0}, {0x70c6,0x0,0}, {0x70c7,0x0,0}, {0x70c8,0x0,0}, {0x70c9,0x0,0}, {0x70ca,0x0,0}, {0x70cb,0x0,0}, {0x70cc,0x0,0}, {0x70cd,0x0,0}, {0x70ce,0x0,0}, {0x70cf,0x0,0}, {0x70d0,0x0,0}, {0x70d1,0x0,0}, {0x70d2,0x0,0}, {0x70d3,0x0,0}, {0x70d4,0x0,0}, {0x70d5,0x0,0}, {0x70d6,0x0,0}, {0x70d7,0x0,0}, {0x70d8,0x0,0}, {0x70d9,0x0,0}, {0x70da,0x0,0}, {0x70db,0x0,0}, {0x70dc,0x0,0}, {0x70dd,0x0,0}, {0x70de,0x0,0}, {0x70df,0x0,0}, {0x70e0,0x0,0}, {0x70e1,0x0,0}, {0x70e2,0x0,0}, {0x70e3,0x0,0}, {0x70e4,0x0,0}, {0x70e5,0x0,0}, {0x70e6,0x0,0}, {0x70e7,0x0,0}, {0x70e8,0x0,0}, {0x70e9,0x0,0}, {0x70ea,0x0,0}, {0x70eb,0x0,0}, {0x70ec,0x0,0}, {0x70ed,0x0,0}, {0x70ee,0x0,0}, {0x70ef,0x0,0}, {0x70f0,0x0,0}, {0x70f1,0x0,0}, {0x70f2,0x0,0}, {0x70f3,0x0,0}, {0x70f4,0x0,0}, {0x70f5,0x0,0}, {0x70f6,0x0,0}, {0x70f7,0x0,0}, {0x70f8,0x0,0}, {0x70f9,0x0,0}, {0x70fa,0x0,0}, {0x70fb,0x0,0}, {0x70fc,0x0,0}, {0x70fd,0x0,0}, {0x70fe,0x0,0}, {0x70ff,0x0,0}, {0x7100,0x0,0}, {0x7101,0x0,0}, {0x7102,0x0,0}, {0x7103,0x0,0}, {0x7104,0x0,0}, {0x7105,0x0,0}, {0x7106,0x0,0}, {0x7107,0x0,0}, {0x7108,0x0,0}, {0x7109,0x0,0}, {0x710a,0x0,0}, {0x710b,0x0,0}, {0x710c,0x0,0}, {0x710d,0x0,0}, {0x710e,0x0,0}, {0x710f,0x0,0}, {0x7110,0x0,0}, {0x7111,0x0,0}, {0x7112,0x0,0}, {0x7113,0x0,0}, {0x7114,0x0,0}, {0x7115,0x0,0}, {0x7116,0x0,0}, {0x7117,0x0,0}, {0x7118,0x0,0}, {0x7119,0x0,0}, {0x711a,0x0,0}, {0x711b,0x0,0}, {0x711c,0x0,0}, {0x711d,0x0,0}, {0x711e,0x0,0}, {0x711f,0x0,0}, {0x7120,0x0,0}, {0x7121,0x0,0}, {0x7122,0x0,0}, {0x7123,0x0,0}, {0x7124,0x0,0}, {0x7125,0x0,0}, {0x7126,0x0,0}, {0x7127,0x0,0}, {0x7128,0x0,0}, {0x7129,0x0,0}, {0x712a,0x0,0}, {0x712b,0x0,0}, {0x712c,0x0,0}, {0x712d,0x0,0}, {0x712e,0x0,0}, {0x712f,0x0,0}, {0x7130,0x0,0}, {0x7131,0x0,0}, {0x7132,0x0,0}, {0x501a,0x10,0}, {0x501b,0xd,0}, {0x501c,0x10,0}, {0x501d,0x13,0}, {0x5000,0x96,0}, {0x5800,0x14,0}, {0x5801,0xd,0}, {0x5802,0xa,0}, {0x5803,0xa,0}, {0x5804,0xd,0}, {0x5805,0x13,0}, {0x5806,0xa,0}, {0x5807,0x5,0}, {0x5808,0x3,0}, {0x5809,0x3,0}, {0x580a,0x5,0}, {0x580b,0x9,0}, {0x580c,0x6,0}, {0x580d,0x2,0}, {0x580e,0x0,0}, {0x580f,0x0,0}, {0x5810,0x2,0}, {0x5811,0x5,0}, {0x5812,0x6,0}, {0x5813,0x2,0}, {0x5814,0x0,0}, {0x5815,0x0,0}, {0x5816,0x2,0}, {0x5817,0x5,0}, {0x5818,0xb,0}, {0x5819,0x6,0}, {0x581a,0x3,0}, {0x581b,0x3,0}, {0x581c,0x5,0}, {0x581d,0xa,0}, {0x581e,0x16,0}, {0x581f,0xf,0}, {0x5820,0xb,0}, {0x5821,0xb,0}, {0x5822,0xf,0}, {0x5823,0x15,0}, {0x5824,0x32,0}, {0x5825,0x23,0}, {0x5826,0x23,0}, {0x5827,0x23,0}, {0x5828,0x22,0}, {0x5829,0x21,0}, {0x582a,0x21,0}, {0x582b,0x22,0}, {0x582c,0x21,0},{0x582d,0x11,0}, {0x582e,0x22,0}, {0x582f,0x31,0}, {0x5830,0x41,0}, {0x5831,0x31,0}, {0x5832,0x1,0}, {0x5833,0x21,0}, {0x5834,0x21,0}, {0x5835,0x21,0}, {0x5836,0x11,0}, {0x5837,0x11,0}, {0x5838,0x22,0}, {0x5839,0x22,0}, {0x583a,0x12,0}, {0x583b,0x22,0}, {0x583c,0x22,0}, {0x583d,0xdf,0},\n};\n\n"
  },
  {
    "path": "selfdrive/camerad/imgproc/conv.cl",
    "content": "// const __constant float3 rgb_weights = (0.299, 0.587, 0.114); // opencv rgb2gray weights\n// const __constant float3 bgr_weights = (0.114, 0.587, 0.299); // bgr2gray weights\n\n// convert input rgb image to single channel then conv\n__kernel void rgb2gray_conv2d(\n  const __global uchar * input,\n  __global short * output,\n  __constant short * filter,\n  __local uchar3 * cached\n)\n{\n  const int rowOffset = get_global_id(1) * IMAGE_W;\n  const int my = get_global_id(0) + rowOffset;\n\n  const int localRowLen = TWICE_HALF_FILTER_SIZE + get_local_size(0);\n  const int localRowOffset = ( get_local_id(1) + HALF_FILTER_SIZE ) * localRowLen;\n  const int myLocal = localRowOffset + get_local_id(0) + HALF_FILTER_SIZE;\n\n  // cache local pixels\n  cached[ myLocal ].x = input[ my * 3 ]; // r\n  cached[ myLocal ].y = input[ my * 3 + 1]; // g\n  cached[ myLocal ].z = input[ my * 3 + 2]; // b\n\n  // pad\n  if (\n    get_global_id(0) < HALF_FILTER_SIZE       ||\n    get_global_id(0) > IMAGE_W - HALF_FILTER_SIZE - 1   ||\n    get_global_id(1) < HALF_FILTER_SIZE     ||\n    get_global_id(1) > IMAGE_H - HALF_FILTER_SIZE - 1\n  )\n  {\n    barrier(CLK_LOCAL_MEM_FENCE);\n    return;\n  }\n  else\n  {\n    int localColOffset = -1;\n    int globalColOffset = -1;\n\n    // cache extra\n    if ( get_local_id(0) < HALF_FILTER_SIZE )\n    {\n      localColOffset = get_local_id(0);\n      globalColOffset = -HALF_FILTER_SIZE;\n\n      cached[ localRowOffset + get_local_id(0) ].x = input[ my * 3 - HALF_FILTER_SIZE * 3 ];\n      cached[ localRowOffset + get_local_id(0) ].y = input[ my * 3 - HALF_FILTER_SIZE * 3 + 1];\n      cached[ localRowOffset + get_local_id(0) ].z = input[ my * 3 - HALF_FILTER_SIZE * 3 + 2];\n    }\n    else if ( get_local_id(0) >= get_local_size(0) - HALF_FILTER_SIZE )\n    {\n      localColOffset = get_local_id(0) + TWICE_HALF_FILTER_SIZE;\n      globalColOffset = HALF_FILTER_SIZE;\n\n      cached[ myLocal + HALF_FILTER_SIZE ].x = input[ my * 3 + HALF_FILTER_SIZE * 3 ];\n      cached[ myLocal + HALF_FILTER_SIZE ].y = input[ my * 3 + HALF_FILTER_SIZE * 3 + 1];\n      cached[ myLocal + HALF_FILTER_SIZE ].z = input[ my * 3 + HALF_FILTER_SIZE * 3 + 2];\n    }\n\n\n    if ( get_local_id(1) < HALF_FILTER_SIZE )\n    {\n      cached[ get_local_id(1) * localRowLen + get_local_id(0) + HALF_FILTER_SIZE ].x = input[ my * 3 - HALF_FILTER_SIZE_IMAGE_W * 3 ];\n      cached[ get_local_id(1) * localRowLen + get_local_id(0) + HALF_FILTER_SIZE ].y = input[ my * 3 - HALF_FILTER_SIZE_IMAGE_W * 3 + 1];\n      cached[ get_local_id(1) * localRowLen + get_local_id(0) + HALF_FILTER_SIZE ].z = input[ my * 3 - HALF_FILTER_SIZE_IMAGE_W * 3 + 2];\n      if (localColOffset > 0)\n      {\n        cached[ get_local_id(1) * localRowLen + localColOffset ].x = input[ my * 3 - HALF_FILTER_SIZE_IMAGE_W * 3 + globalColOffset * 3];\n        cached[ get_local_id(1) * localRowLen + localColOffset ].y = input[ my * 3 - HALF_FILTER_SIZE_IMAGE_W * 3 + globalColOffset * 3 + 1];\n        cached[ get_local_id(1) * localRowLen + localColOffset ].z = input[ my * 3 - HALF_FILTER_SIZE_IMAGE_W * 3 + globalColOffset * 3 + 2];\n      }\n    }\n    else if ( get_local_id(1) >= get_local_size(1) -HALF_FILTER_SIZE )\n    {\n      int offset = ( get_local_id(1) + TWICE_HALF_FILTER_SIZE ) * localRowLen;\n      cached[ offset + get_local_id(0) + HALF_FILTER_SIZE ].x = input[ my * 3 + HALF_FILTER_SIZE_IMAGE_W * 3 ];\n      cached[ offset + get_local_id(0) + HALF_FILTER_SIZE ].y = input[ my * 3 + HALF_FILTER_SIZE_IMAGE_W * 3 + 1];\n      cached[ offset + get_local_id(0) + HALF_FILTER_SIZE ].z = input[ my * 3 + HALF_FILTER_SIZE_IMAGE_W * 3 + 2];\n      if (localColOffset > 0)\n      {\n        cached[ offset + localColOffset ].x = input[ my * 3 + HALF_FILTER_SIZE_IMAGE_W * 3 + globalColOffset * 3];\n        cached[ offset + localColOffset ].y = input[ my * 3 + HALF_FILTER_SIZE_IMAGE_W * 3 + globalColOffset * 3 + 1];\n        cached[ offset + localColOffset ].z = input[ my * 3 + HALF_FILTER_SIZE_IMAGE_W * 3 + globalColOffset * 3 + 2];\n      }\n    }\n\n    // sync\n    barrier(CLK_LOCAL_MEM_FENCE);\n\n    // perform convolution\n    int fIndex = 0;\n    short sum = 0;\n\n    for (int r = -HALF_FILTER_SIZE; r <= HALF_FILTER_SIZE; r++)\n    {\n      int curRow = r * localRowLen;\n      for (int c = -HALF_FILTER_SIZE; c <= HALF_FILTER_SIZE; c++, fIndex++)\n      {\n        if (!FLIP_RB){\n          // sum += dot(rgb_weights, cached[ myLocal + curRow + c ]) * filter[ fIndex ];\n          sum += (cached[ myLocal + curRow + c ].x / 3 + cached[ myLocal + curRow + c ].y / 2 + cached[ myLocal + curRow + c ].z / 9) * filter[ fIndex ];\n        } else {\n          // sum += dot(bgr_weights, cached[ myLocal + curRow + c ]) * filter[ fIndex ];\n          sum += (cached[ myLocal + curRow + c ].x / 9 + cached[ myLocal + curRow + c ].y / 2 + cached[ myLocal + curRow + c ].z / 3) * filter[ fIndex ];\n        }\n      }\n    }\n    output[my] = sum;\n  }\n}"
  },
  {
    "path": "selfdrive/camerad/imgproc/pool.cl",
    "content": "// calculate variance in each subregion\n__kernel void var_pool(\n  const __global char * input,\n  __global ushort * output // should not be larger than 128*128 so uint16\n)\n{\n  const int xidx = get_global_id(0) + ROI_X_MIN;\n  const int yidx = get_global_id(1) + ROI_Y_MIN;\n\n  const int size = X_PITCH * Y_PITCH;\n\n  float fsum = 0;\n  char mean, max;\n\n  for (int i = 0; i < size; i++) {\n    int x_offset = i % X_PITCH;\n    int y_offset = i / X_PITCH;\n    fsum += input[xidx*X_PITCH + yidx*Y_PITCH*FULL_STRIDE_X + x_offset + y_offset*FULL_STRIDE_X];\n    max = input[xidx*X_PITCH + yidx*Y_PITCH*FULL_STRIDE_X + x_offset + y_offset*FULL_STRIDE_X]>max ? input[xidx*X_PITCH + yidx*Y_PITCH*FULL_STRIDE_X + x_offset + y_offset*FULL_STRIDE_X]:max;\n  }\n\n  mean = convert_char_rte(fsum / size);\n\n  float fvar = 0;\n  for (int i = 0; i < size; i++) {\n    int x_offset = i % X_PITCH;\n    int y_offset = i / X_PITCH;\n    fvar += (input[xidx*X_PITCH + yidx*Y_PITCH*FULL_STRIDE_X + x_offset + y_offset*FULL_STRIDE_X] - mean) * (input[xidx*X_PITCH + yidx*Y_PITCH*FULL_STRIDE_X + x_offset + y_offset*FULL_STRIDE_X] - mean);\n  }\n\n  fvar = fvar / size;\n\n  output[(xidx-ROI_X_MIN)+(yidx-ROI_Y_MIN)*(ROI_X_MAX-ROI_X_MIN+1)] = convert_ushort_rte(5 * fvar + convert_float_rte(max));\n}"
  },
  {
    "path": "selfdrive/camerad/imgproc/utils.cc",
    "content": "#include \"selfdrive/camerad/imgproc/utils.h\"\n\n#include <algorithm>\n#include <cassert>\n#include <cstdio>\n#include <cmath>\n#include <cstring>\n\nconst int16_t lapl_conv_krnl[9] = {0, 1, 0,\n                                   1, -4, 1,\n                                   0, 1, 0};\n\n// calculate score based on laplacians in one area\nuint16_t get_lapmap_one(const int16_t *lap, int x_pitch, int y_pitch) {\n  const int size = x_pitch * y_pitch;\n  // avg and max of roi\n  int16_t max = 0;\n  int sum = 0;\n  for (int i = 0; i < size; ++i) {\n    const int16_t v = lap[i];\n    sum += v;\n    if (v > max) max = v;\n  }\n\n  const int16_t mean = sum / size;\n\n  // var of roi\n  int var = 0;\n  for (int i = 0; i < size; ++i) {\n    var += std::pow(lap[i] - mean, 2);\n  }\n\n  const float fvar = (float)var / size;\n  return std::min(5 * fvar + max, (float)65535);\n}\n\nbool is_blur(const uint16_t *lapmap, const size_t size) {\n  float bad_sum = 0;\n  for (int i = 0; i < size; i++) {\n    if (lapmap[i] < LM_THRESH) {\n      bad_sum += 1 / (float)size;\n    }\n  }\n  return (bad_sum > LM_PREC_THRESH);\n}\n\nstatic cl_program build_conv_program(cl_device_id device_id, cl_context context, int image_w, int image_h, int filter_size) {\n  char args[4096];\n  snprintf(args, sizeof(args),\n          \"-cl-fast-relaxed-math -cl-denorms-are-zero \"\n          \"-DIMAGE_W=%d -DIMAGE_H=%d -DFLIP_RB=%d \"\n          \"-DFILTER_SIZE=%d -DHALF_FILTER_SIZE=%d -DTWICE_HALF_FILTER_SIZE=%d -DHALF_FILTER_SIZE_IMAGE_W=%d\",\n          image_w, image_h, 1,\n          filter_size, filter_size/2, (filter_size/2)*2, (filter_size/2)*image_w);\n  return cl_program_from_file(context, device_id, \"imgproc/conv.cl\", args);\n}\n\nLapConv::LapConv(cl_device_id device_id, cl_context ctx, int rgb_width, int rgb_height, int filter_size)\n    : width(rgb_width / NUM_SEGMENTS_X), height(rgb_height / NUM_SEGMENTS_Y), \n      roi_buf(width * height * 3), result_buf(width * height) {\n\n  prg = build_conv_program(device_id, ctx, width, height, filter_size);\n  krnl = CL_CHECK_ERR(clCreateKernel(prg, \"rgb2gray_conv2d\", &err));\n  // TODO: Removed CL_MEM_SVM_FINE_GRAIN_BUFFER, confirm it doesn't matter\n  roi_cl = CL_CHECK_ERR(clCreateBuffer(ctx, CL_MEM_READ_WRITE, roi_buf.size() * sizeof(roi_buf[0]), NULL, &err));\n  result_cl = CL_CHECK_ERR(clCreateBuffer(ctx, CL_MEM_READ_WRITE, result_buf.size() * sizeof(result_buf[0]), NULL, &err));\n  filter_cl = CL_CHECK_ERR(clCreateBuffer(ctx, CL_MEM_READ_ONLY | CL_MEM_COPY_HOST_PTR,\n                                          9 * sizeof(int16_t), (void *)&lapl_conv_krnl, &err));\n}\n\nLapConv::~LapConv() {\n  CL_CHECK(clReleaseMemObject(roi_cl));\n  CL_CHECK(clReleaseMemObject(result_cl));\n  CL_CHECK(clReleaseMemObject(filter_cl));\n  CL_CHECK(clReleaseKernel(krnl));\n  CL_CHECK(clReleaseProgram(prg));\n}\n\nuint16_t LapConv::Update(cl_command_queue q, const uint8_t *rgb_buf, const int roi_id) {\n  // sharpness scores\n  const int x_offset = ROI_X_MIN + roi_id % (ROI_X_MAX - ROI_X_MIN + 1);\n  const int y_offset = ROI_Y_MIN + roi_id / (ROI_X_MAX - ROI_X_MIN + 1);\n\n  const uint8_t *rgb_offset = rgb_buf + y_offset * height * FULL_STRIDE_X * 3 + x_offset * width * 3;\n  for (int i = 0; i < height; ++i) {\n    memcpy(&roi_buf[i * width * 3], &rgb_offset[i * FULL_STRIDE_X * 3], width * 3);\n  }\n\n  constexpr int local_mem_size = (CONV_LOCAL_WORKSIZE + 2 * (3 / 2)) * (CONV_LOCAL_WORKSIZE + 2 * (3 / 2)) * (3 * sizeof(uint8_t));\n  const size_t global_work_size[] = {(size_t)width, (size_t)height};\n  const size_t local_work_size[] = {CONV_LOCAL_WORKSIZE, CONV_LOCAL_WORKSIZE};\n\n  CL_CHECK(clEnqueueWriteBuffer(q, roi_cl, CL_TRUE, 0, roi_buf.size() * sizeof(roi_buf[0]), roi_buf.data(), 0, 0, 0));\n  CL_CHECK(clSetKernelArg(krnl, 0, sizeof(cl_mem), (void *)&roi_cl));\n  CL_CHECK(clSetKernelArg(krnl, 1, sizeof(cl_mem), (void *)&result_cl));\n  CL_CHECK(clSetKernelArg(krnl, 2, sizeof(cl_mem), (void *)&filter_cl));\n  CL_CHECK(clSetKernelArg(krnl, 3, local_mem_size, 0));\n  cl_event conv_event;\n  CL_CHECK(clEnqueueNDRangeKernel(q, krnl, 2, NULL, global_work_size, local_work_size, 0, 0, &conv_event));\n  CL_CHECK(clWaitForEvents(1, &conv_event));\n  CL_CHECK(clReleaseEvent(conv_event));\n  CL_CHECK(clEnqueueReadBuffer(q, result_cl, CL_TRUE, 0,\n                               result_buf.size() * sizeof(result_buf[0]), result_buf.data(), 0, 0, 0));\n\n  return get_lapmap_one(result_buf.data(), width, height);\n}\n"
  },
  {
    "path": "selfdrive/camerad/imgproc/utils.h",
    "content": "#pragma once\n\n#include <cstddef>\n#include <cstdint>\n#include <vector>\n\n#include \"selfdrive/common/clutil.h\"\n\n#define NUM_SEGMENTS_X 8\n#define NUM_SEGMENTS_Y 6\n\n#define ROI_X_MIN 1\n#define ROI_X_MAX 6\n#define ROI_Y_MIN 2\n#define ROI_Y_MAX 3\n\n#define LM_THRESH 120\n#define LM_PREC_THRESH 0.9 // 90 perc is blur\n\n// only apply to QCOM\n#define FULL_STRIDE_X 1280\n#define FULL_STRIDE_Y 896\n\n#define CONV_LOCAL_WORKSIZE 16\n\nclass LapConv {\npublic:\n  LapConv(cl_device_id device_id, cl_context ctx, int rgb_width, int rgb_height, int filter_size);\n  ~LapConv();\n  uint16_t Update(cl_command_queue q, const uint8_t *rgb_buf, const int roi_id);\n\nprivate:\n  cl_mem roi_cl, result_cl, filter_cl;\n  cl_program prg;\n  cl_kernel krnl;\n  const int width, height;\n  std::vector<uint8_t> roi_buf;\n  std::vector<int16_t> result_buf;\n};\n\nbool is_blur(const uint16_t *lapmap, const size_t size);\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_cpas.h",
    "content": "#ifndef __UAPI_CAM_CPAS_H__\n#define __UAPI_CAM_CPAS_H__\n\n#include \"cam_defs.h\"\n\n#define CAM_FAMILY_CAMERA_SS     1\n#define CAM_FAMILY_CPAS_SS       2\n\n/**\n * struct cam_cpas_query_cap - CPAS query device capability payload\n *\n * @camera_family     : Camera family type\n * @reserved          : Reserved field for alignment\n * @camera_version    : Camera platform version\n * @cpas_version      : Camera CPAS version within camera platform\n *\n */\nstruct cam_cpas_query_cap {\n\tuint32_t                 camera_family;\n\tuint32_t                 reserved;\n\tstruct cam_hw_version    camera_version;\n\tstruct cam_hw_version    cpas_version;\n};\n\n#endif /* __UAPI_CAM_CPAS_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_defs.h",
    "content": "#ifndef __UAPI_CAM_DEFS_H__\n#define __UAPI_CAM_DEFS_H__\n\n#include <linux/videodev2.h>\n#include <linux/types.h>\n#include <linux/ioctl.h>\n\n\n/* camera op codes */\n#define CAM_COMMON_OPCODE_BASE                  0x100\n#define CAM_QUERY_CAP                           (CAM_COMMON_OPCODE_BASE + 0x1)\n#define CAM_ACQUIRE_DEV                         (CAM_COMMON_OPCODE_BASE + 0x2)\n#define CAM_START_DEV                           (CAM_COMMON_OPCODE_BASE + 0x3)\n#define CAM_STOP_DEV                            (CAM_COMMON_OPCODE_BASE + 0x4)\n#define CAM_CONFIG_DEV                          (CAM_COMMON_OPCODE_BASE + 0x5)\n#define CAM_RELEASE_DEV                         (CAM_COMMON_OPCODE_BASE + 0x6)\n#define CAM_SD_SHUTDOWN                         (CAM_COMMON_OPCODE_BASE + 0x7)\n#define CAM_FLUSH_REQ                           (CAM_COMMON_OPCODE_BASE + 0x8)\n#define CAM_COMMON_OPCODE_MAX                   (CAM_COMMON_OPCODE_BASE + 0x9)\n\n#define CAM_EXT_OPCODE_BASE                     0x200\n#define CAM_CONFIG_DEV_EXTERNAL                 (CAM_EXT_OPCODE_BASE + 0x1)\n\n/* camera handle type */\n#define CAM_HANDLE_USER_POINTER                 1\n#define CAM_HANDLE_MEM_HANDLE                   2\n\n/* Generic Blob CmdBuffer header properties */\n#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK    0xFFFFFF00\n#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT   8\n#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK    0xFF\n#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT   0\n\n/* Command Buffer Types */\n#define CAM_CMD_BUF_DMI                     0x1\n#define CAM_CMD_BUF_DMI16                   0x2\n#define CAM_CMD_BUF_DMI32                   0x3\n#define CAM_CMD_BUF_DMI64                   0x4\n#define CAM_CMD_BUF_DIRECT                  0x5\n#define CAM_CMD_BUF_INDIRECT                0x6\n#define CAM_CMD_BUF_I2C                     0x7\n#define CAM_CMD_BUF_FW                      0x8\n#define CAM_CMD_BUF_GENERIC                 0x9\n#define CAM_CMD_BUF_LEGACY                  0xA\n\n/**\n * enum flush_type_t - Identifies the various flush types\n *\n * @CAM_FLUSH_TYPE_REQ:    Flush specific request\n * @CAM_FLUSH_TYPE_ALL:    Flush all requests belonging to a context\n * @CAM_FLUSH_TYPE_MAX:    Max enum to validate flush type\n *\n */\nenum flush_type_t {\n\tCAM_FLUSH_TYPE_REQ,\n\tCAM_FLUSH_TYPE_ALL,\n\tCAM_FLUSH_TYPE_MAX\n};\n\n/**\n * struct cam_control - Structure used by ioctl control for camera\n *\n * @op_code:            This is the op code for camera control\n * @size:               Control command size\n * @handle_type:        User pointer or shared memory handle\n * @reserved:           Reserved field for 64 bit alignment\n * @handle:             Control command payload\n */\nstruct cam_control {\n\tuint32_t        op_code;\n\tuint32_t        size;\n\tuint32_t        handle_type;\n\tuint32_t        reserved;\n\tuint64_t        handle;\n};\n\n/* camera IOCTL */\n#define VIDIOC_CAM_CONTROL \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control)\n\n/**\n * struct cam_hw_version - Structure for HW version of camera devices\n *\n * @major    : Hardware version major\n * @minor    : Hardware version minor\n * @incr     : Hardware version increment\n * @reserved : Reserved for 64 bit aligngment\n */\nstruct cam_hw_version {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t incr;\n\tuint32_t reserved;\n};\n\n/**\n * struct cam_iommu_handle - Structure for IOMMU handles of camera hw devices\n *\n * @non_secure: Device Non Secure IOMMU handle\n * @secure:     Device Secure IOMMU handle\n *\n */\nstruct cam_iommu_handle {\n\tint32_t non_secure;\n\tint32_t secure;\n};\n\n/* camera secure mode */\n#define CAM_SECURE_MODE_NON_SECURE             0\n#define CAM_SECURE_MODE_SECURE                 1\n\n/* Camera Format Type */\n#define CAM_FORMAT_BASE                         0\n#define CAM_FORMAT_MIPI_RAW_6                   1\n#define CAM_FORMAT_MIPI_RAW_8                   2\n#define CAM_FORMAT_MIPI_RAW_10                  3\n#define CAM_FORMAT_MIPI_RAW_12                  4\n#define CAM_FORMAT_MIPI_RAW_14                  5\n#define CAM_FORMAT_MIPI_RAW_16                  6\n#define CAM_FORMAT_MIPI_RAW_20                  7\n#define CAM_FORMAT_QTI_RAW_8                    8\n#define CAM_FORMAT_QTI_RAW_10                   9\n#define CAM_FORMAT_QTI_RAW_12                   10\n#define CAM_FORMAT_QTI_RAW_14                   11\n#define CAM_FORMAT_PLAIN8                       12\n#define CAM_FORMAT_PLAIN16_8                    13\n#define CAM_FORMAT_PLAIN16_10                   14\n#define CAM_FORMAT_PLAIN16_12                   15\n#define CAM_FORMAT_PLAIN16_14                   16\n#define CAM_FORMAT_PLAIN16_16                   17\n#define CAM_FORMAT_PLAIN32_20                   18\n#define CAM_FORMAT_PLAIN64                      19\n#define CAM_FORMAT_PLAIN128                     20\n#define CAM_FORMAT_ARGB                         21\n#define CAM_FORMAT_ARGB_10                      22\n#define CAM_FORMAT_ARGB_12                      23\n#define CAM_FORMAT_ARGB_14                      24\n#define CAM_FORMAT_DPCM_10_6_10                 25\n#define CAM_FORMAT_DPCM_10_8_10                 26\n#define CAM_FORMAT_DPCM_12_6_12                 27\n#define CAM_FORMAT_DPCM_12_8_12                 28\n#define CAM_FORMAT_DPCM_14_8_14                 29\n#define CAM_FORMAT_DPCM_14_10_14                30\n#define CAM_FORMAT_NV21                         31\n#define CAM_FORMAT_NV12                         32\n#define CAM_FORMAT_TP10                         33\n#define CAM_FORMAT_YUV422                       34\n#define CAM_FORMAT_PD8                          35\n#define CAM_FORMAT_PD10                         36\n#define CAM_FORMAT_UBWC_NV12                    37\n#define CAM_FORMAT_UBWC_NV12_4R                 38\n#define CAM_FORMAT_UBWC_TP10                    39\n#define CAM_FORMAT_UBWC_P010                    40\n#define CAM_FORMAT_PLAIN8_SWAP                  41\n#define CAM_FORMAT_PLAIN8_10                    42\n#define CAM_FORMAT_PLAIN8_10_SWAP               43\n#define CAM_FORMAT_YV12                         44\n#define CAM_FORMAT_Y_ONLY                       45\n#define CAM_FORMAT_MAX                          46\n\n/* camera rotaion */\n#define CAM_ROTATE_CW_0_DEGREE                  0\n#define CAM_ROTATE_CW_90_DEGREE                 1\n#define CAM_RORATE_CW_180_DEGREE                2\n#define CAM_ROTATE_CW_270_DEGREE                3\n\n/* camera Color Space */\n#define CAM_COLOR_SPACE_BASE                    0\n#define CAM_COLOR_SPACE_BT601_FULL              1\n#define CAM_COLOR_SPACE_BT601625                2\n#define CAM_COLOR_SPACE_BT601525                3\n#define CAM_COLOR_SPACE_BT709                   4\n#define CAM_COLOR_SPACE_DEPTH                   5\n#define CAM_COLOR_SPACE_MAX                     6\n\n/* camera buffer direction */\n#define CAM_BUF_INPUT                           1\n#define CAM_BUF_OUTPUT                          2\n#define CAM_BUF_IN_OUT                          3\n\n/* camera packet device Type */\n#define CAM_PACKET_DEV_BASE                     0\n#define CAM_PACKET_DEV_IMG_SENSOR               1\n#define CAM_PACKET_DEV_ACTUATOR                 2\n#define CAM_PACKET_DEV_COMPANION                3\n#define CAM_PACKET_DEV_EEPOM                    4\n#define CAM_PACKET_DEV_CSIPHY                   5\n#define CAM_PACKET_DEV_OIS                      6\n#define CAM_PACKET_DEV_FLASH                    7\n#define CAM_PACKET_DEV_FD                       8\n#define CAM_PACKET_DEV_JPEG_ENC                 9\n#define CAM_PACKET_DEV_JPEG_DEC                 10\n#define CAM_PACKET_DEV_VFE                      11\n#define CAM_PACKET_DEV_CPP                      12\n#define CAM_PACKET_DEV_CSID                     13\n#define CAM_PACKET_DEV_ISPIF                    14\n#define CAM_PACKET_DEV_IFE                      15\n#define CAM_PACKET_DEV_ICP                      16\n#define CAM_PACKET_DEV_LRME                     17\n#define CAM_PACKET_DEV_MAX                      18\n\n\n/* constants */\n#define CAM_PACKET_MAX_PLANES                   3\n\n/**\n * struct cam_plane_cfg - Plane configuration info\n *\n * @width:                      Plane width in pixels\n * @height:                     Plane height in lines\n * @plane_stride:               Plane stride in pixel\n * @slice_height:               Slice height in line (not used by ISP)\n * @meta_stride:                UBWC metadata stride\n * @meta_size:                  UBWC metadata plane size\n * @meta_offset:                UBWC metadata offset\n * @packer_config:              UBWC packer config\n * @mode_config:                UBWC mode config\n * @tile_config:                UBWC tile config\n * @h_init:                     UBWC horizontal initial coordinate in pixels\n * @v_init:                     UBWC vertical initial coordinate in lines\n *\n */\nstruct cam_plane_cfg {\n\tuint32_t                width;\n\tuint32_t                height;\n\tuint32_t                plane_stride;\n\tuint32_t                slice_height;\n\tuint32_t                meta_stride;\n\tuint32_t                meta_size;\n\tuint32_t                meta_offset;\n\tuint32_t                packer_config;\n\tuint32_t                mode_config;\n\tuint32_t                tile_config;\n\tuint32_t                h_init;\n\tuint32_t                v_init;\n};\n\n/**\n * struct cam_cmd_buf_desc - Command buffer descriptor\n *\n * @mem_handle:                 Command buffer handle\n * @offset:                     Command start offset\n * @size:                       Size of the command buffer in bytes\n * @length:                     Used memory in command buffer in bytes\n * @type:                       Type of the command buffer\n * @meta_data:                  Data type for private command buffer\n *                              Between UMD and KMD\n *\n */\nstruct cam_cmd_buf_desc {\n\tint32_t                 mem_handle;\n\tuint32_t                offset;\n\tuint32_t                size;\n\tuint32_t                length;\n\tuint32_t                type;\n\tuint32_t                meta_data;\n};\n\n/**\n * struct cam_buf_io_cfg - Buffer io configuration for buffers\n *\n * @mem_handle:                 Mem_handle array for the buffers.\n * @offsets:                    Offsets for each planes in the buffer\n * @planes:                     Per plane information\n * @width:                      Main plane width in pixel\n * @height:                     Main plane height in lines\n * @format:                     Format of the buffer\n * @color_space:                Color space for the buffer\n * @color_pattern:              Color pattern in the buffer\n * @bpp:                        Bit per pixel\n * @rotation:                   Rotation information for the buffer\n * @resource_type:              Resource type associated with the buffer\n * @fence:                      Fence handle\n * @early_fence:                Fence handle for early signal\n * @aux_cmd_buf:                An auxiliary command buffer that may be\n *                              used for programming the IO\n * @direction:                  Direction of the config\n * @batch_size:                 Batch size in HFR mode\n * @subsample_pattern:          Subsample pattern. Used in HFR mode. It\n *                              should be consistent with batchSize and\n *                              CAMIF programming.\n * @subsample_period:           Subsample period. Used in HFR mode. It\n *                              should be consistent with batchSize and\n *                              CAMIF programming.\n * @framedrop_pattern:          Framedrop pattern\n * @framedrop_period:           Framedrop period\n * @flag:                       Flags for extra information\n * @direction:                  Buffer direction: input or output\n * @padding:                    Padding for the structure\n *\n */\nstruct cam_buf_io_cfg {\n\tint32_t                         mem_handle[CAM_PACKET_MAX_PLANES];\n\tuint32_t                        offsets[CAM_PACKET_MAX_PLANES];\n\tstruct cam_plane_cfg            planes[CAM_PACKET_MAX_PLANES];\n\tuint32_t                        format;\n\tuint32_t                        color_space;\n\tuint32_t                        color_pattern;\n\tuint32_t                        bpp;\n\tuint32_t                        rotation;\n\tuint32_t                        resource_type;\n\tint32_t                         fence;\n\tint32_t                         early_fence;\n\tstruct cam_cmd_buf_desc         aux_cmd_buf;\n\tuint32_t                        direction;\n\tuint32_t                        batch_size;\n\tuint32_t                        subsample_pattern;\n\tuint32_t                        subsample_period;\n\tuint32_t                        framedrop_pattern;\n\tuint32_t                        framedrop_period;\n\tuint32_t                        flag;\n\tuint32_t                        padding;\n};\n\n/**\n * struct cam_packet_header - Camera packet header\n *\n * @op_code:                    Camera packet opcode\n * @size:                       Size of the camera packet in bytes\n * @request_id:                 Request id for this camera packet\n * @flags:                      Flags for the camera packet\n * @padding:                    Padding\n *\n */\nstruct cam_packet_header {\n\tuint32_t                op_code;\n\tuint32_t                size;\n\tuint64_t                request_id;\n\tuint32_t                flags;\n\tuint32_t                padding;\n};\n\n/**\n * struct cam_patch_desc - Patch structure\n *\n * @dst_buf_hdl:                Memory handle for the dest buffer\n * @dst_offset:                 Offset byte in the dest buffer\n * @src_buf_hdl:                Memory handle for the source buffer\n * @src_offset:                 Offset byte in the source buffer\n *\n */\nstruct cam_patch_desc {\n\tint32_t                 dst_buf_hdl;\n\tuint32_t                dst_offset;\n\tint32_t                 src_buf_hdl;\n\tuint32_t                src_offset;\n};\n\n/**\n * struct cam_packet - Camera packet structure\n *\n * @header:                     Camera packet header\n * @cmd_buf_offset:             Command buffer start offset\n * @num_cmd_buf:                Number of the command buffer in the packet\n * @io_config_offset:           Buffer io configuration start offset\n * @num_io_configs:             Number of the buffer io configurations\n * @patch_offset:               Patch offset for the patch structure\n * @num_patches:                Number of the patch structure\n * @kmd_cmd_buf_index:          Command buffer index which contains extra\n *                              space for the KMD buffer\n * @kmd_cmd_buf_offset:         Offset from the beginning of the command\n *                              buffer for KMD usage.\n * @payload:                    Camera packet payload\n *\n */\nstruct cam_packet {\n\tstruct cam_packet_header        header;\n\tuint32_t                        cmd_buf_offset;\n\tuint32_t                        num_cmd_buf;\n\tuint32_t                        io_configs_offset;\n\tuint32_t                        num_io_configs;\n\tuint32_t                        patch_offset;\n\tuint32_t                        num_patches;\n\tuint32_t                        kmd_cmd_buf_index;\n\tuint32_t                        kmd_cmd_buf_offset;\n\tuint64_t                        payload[1];\n\n};\n\n/**\n * struct cam_release_dev_cmd - Control payload for release devices\n *\n * @session_handle:             Session handle for the release\n * @dev_handle:                 Device handle for the release\n */\nstruct cam_release_dev_cmd {\n\tint32_t                 session_handle;\n\tint32_t                 dev_handle;\n};\n\n/**\n * struct cam_start_stop_dev_cmd - Control payload for start/stop device\n *\n * @session_handle:             Session handle for the start/stop command\n * @dev_handle:                 Device handle for the start/stop command\n *\n */\nstruct cam_start_stop_dev_cmd {\n\tint32_t                 session_handle;\n\tint32_t                 dev_handle;\n};\n\n/**\n * struct cam_config_dev_cmd - Command payload for configure device\n *\n * @session_handle:             Session handle for the command\n * @dev_handle:                 Device handle for the command\n * @offset:                     Offset byte in the packet handle.\n * @packet_handle:              Packet memory handle for the actual packet:\n *                              struct cam_packet.\n *\n */\nstruct cam_config_dev_cmd {\n\tint32_t                 session_handle;\n\tint32_t                 dev_handle;\n\tuint64_t                offset;\n\tuint64_t                packet_handle;\n};\n\n/**\n * struct cam_query_cap_cmd - Payload for query device capability\n *\n * @size:               Handle size\n * @handle_type:        User pointer or shared memory handle\n * @caps_handle:        Device specific query command payload\n *\n */\nstruct cam_query_cap_cmd {\n\tuint32_t        size;\n\tuint32_t        handle_type;\n\tuint64_t        caps_handle;\n};\n\n/**\n * struct cam_acquire_dev_cmd - Control payload for acquire devices\n *\n * @session_handle:     Session handle for the acquire command\n * @dev_handle:         Device handle to be returned\n * @handle_type:        Resource handle type:\n *                      1 = user pointer, 2 = mem handle\n * @num_resources:      Number of the resources to be acquired\n * @resources_hdl:      Resource handle that refers to the actual\n *                      resource array. Each item in this\n *                      array is device specific resource structure\n *\n */\nstruct cam_acquire_dev_cmd {\n\tint32_t         session_handle;\n\tint32_t         dev_handle;\n\tuint32_t        handle_type;\n\tuint32_t        num_resources;\n\tuint64_t        resource_hdl;\n};\n\n/**\n * struct cam_flush_dev_cmd - Control payload for flush devices\n *\n * @version:           Version\n * @session_handle:    Session handle for the acquire command\n * @dev_handle:        Device handle to be returned\n * @flush_type:        Flush type:\n *                     0 = flush specific request\n *                     1 = flush all\n * @reserved:          Reserved for 64 bit aligngment\n * @req_id:            Request id that needs to cancel\n *\n */\nstruct cam_flush_dev_cmd {\n\tuint64_t       version;\n\tint32_t        session_handle;\n\tint32_t        dev_handle;\n\tuint32_t       flush_type;\n\tuint32_t       reserved;\n\tint64_t        req_id;\n};\n\n#endif /* __UAPI_CAM_DEFS_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_fd.h",
    "content": "#ifndef __UAPI_CAM_FD_H__\n#define __UAPI_CAM_FD_H__\n\n#include \"cam_defs.h\"\n\n#define CAM_FD_MAX_FACES                       35\n#define CAM_FD_RAW_RESULT_ENTRIES              512\n\n/* FD Op Codes */\n#define CAM_PACKET_OPCODES_FD_FRAME_UPDATE     0x0\n\n/* FD Command Buffer identifiers */\n#define CAM_FD_CMD_BUFFER_ID_GENERIC           0x0\n#define CAM_FD_CMD_BUFFER_ID_CDM               0x1\n#define CAM_FD_CMD_BUFFER_ID_MAX               0x2\n\n/* FD Blob types */\n#define CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST  0x0\n#define CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED  0x1\n\n/* FD Resource IDs */\n#define CAM_FD_INPUT_PORT_ID_IMAGE             0x0\n#define CAM_FD_INPUT_PORT_ID_MAX               0x1\n\n#define CAM_FD_OUTPUT_PORT_ID_RESULTS          0x0\n#define CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS      0x1\n#define CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER      0x2\n#define CAM_FD_OUTPUT_PORT_ID_MAX              0x3\n\n/**\n * struct cam_fd_soc_clock_bw_request - SOC clock, bandwidth request info\n *\n * @clock_rate : Clock rate required while processing frame\n * @bandwidth  : Bandwidth required while processing frame\n * @reserved   : Reserved for future use\n */\nstruct cam_fd_soc_clock_bw_request {\n\tuint64_t    clock_rate;\n\tuint64_t    bandwidth;\n\tuint64_t    reserved[4];\n};\n\n/**\n * struct cam_fd_face - Face properties\n *\n * @prop1 : Property 1 of face\n * @prop2 : Property 2 of face\n * @prop3 : Property 3 of face\n * @prop4 : Property 4 of face\n *\n * Do not change this layout, this is inline with how HW writes\n * these values directly when the buffer is programmed to HW\n */\nstruct cam_fd_face {\n\tuint32_t    prop1;\n\tuint32_t    prop2;\n\tuint32_t    prop3;\n\tuint32_t    prop4;\n};\n\n/**\n * struct cam_fd_results - FD results layout\n *\n * @faces      : Array of faces with face properties\n * @face_count : Number of faces detected\n * @reserved   : Reserved for alignment\n *\n * Do not change this layout, this is inline with how HW writes\n * these values directly when the buffer is programmed to HW\n */\nstruct cam_fd_results {\n\tstruct cam_fd_face    faces[CAM_FD_MAX_FACES];\n\tuint32_t              face_count;\n\tuint32_t              reserved[3];\n};\n\n/**\n * struct cam_fd_hw_caps - Face properties\n *\n * @core_version          : FD core version\n * @wrapper_version       : FD wrapper version\n * @raw_results_available : Whether raw results are available on this HW\n * @supported_modes       : Modes supported by this HW.\n * @reserved              : Reserved for future use\n */\nstruct cam_fd_hw_caps {\n\tstruct cam_hw_version    core_version;\n\tstruct cam_hw_version    wrapper_version;\n\tuint32_t                 raw_results_available;\n\tuint32_t                 supported_modes;\n\tuint64_t                 reserved;\n};\n\n/**\n * struct cam_fd_query_cap_cmd - FD Query capabilities information\n *\n * @device_iommu : FD IOMMU handles\n * @cdm_iommu    : CDM iommu handles\n * @hw_caps      : FD HW capabilities\n * @reserved     : Reserved for alignment\n */\nstruct cam_fd_query_cap_cmd {\n\tstruct cam_iommu_handle    device_iommu;\n\tstruct cam_iommu_handle    cdm_iommu;\n\tstruct cam_fd_hw_caps      hw_caps;\n\tuint64_t                   reserved;\n};\n\n/**\n * struct cam_fd_acquire_dev_info - FD acquire device information\n *\n * @clk_bw_request  : SOC clock, bandwidth request\n * @priority        : Priority for this acquire\n * @mode            : Mode in which to run FD HW.\n * @get_raw_results : Whether this acquire needs face raw results\n *                    while frame processing\n * @reserved        : Reserved field for 64 bit alignment\n */\nstruct cam_fd_acquire_dev_info {\n\tstruct cam_fd_soc_clock_bw_request clk_bw_request;\n\tuint32_t                           priority;\n\tuint32_t                           mode;\n\tuint32_t                           get_raw_results;\n\tuint32_t                           reserved[13];\n};\n\n#endif /* __UAPI_CAM_FD_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_icp.h",
    "content": "#ifndef __UAPI_CAM_ICP_H__\n#define __UAPI_CAM_ICP_H__\n\n#include \"cam_defs.h\"\n\n/* icp, ipe, bps, cdm(ipe/bps) are used in querycap */\n#define CAM_ICP_DEV_TYPE_A5      1\n#define CAM_ICP_DEV_TYPE_IPE     2\n#define CAM_ICP_DEV_TYPE_BPS     3\n#define CAM_ICP_DEV_TYPE_IPE_CDM 4\n#define CAM_ICP_DEV_TYPE_BPS_CDM 5\n#define CAM_ICP_DEV_TYPE_MAX     5\n\n/* definitions needed for icp aquire device */\n#define CAM_ICP_RES_TYPE_BPS        1\n#define CAM_ICP_RES_TYPE_IPE_RT     2\n#define CAM_ICP_RES_TYPE_IPE        3\n#define CAM_ICP_RES_TYPE_MAX        4\n\n/* packet opcode types */\n#define CAM_ICP_OPCODE_IPE_UPDATE 0\n#define CAM_ICP_OPCODE_BPS_UPDATE 1\n\n/* IPE input port resource type */\n#define CAM_ICP_IPE_INPUT_IMAGE_FULL            0x0\n#define CAM_ICP_IPE_INPUT_IMAGE_DS4             0x1\n#define CAM_ICP_IPE_INPUT_IMAGE_DS16            0x2\n#define CAM_ICP_IPE_INPUT_IMAGE_DS64            0x3\n#define CAM_ICP_IPE_INPUT_IMAGE_FULL_REF        0x4\n#define CAM_ICP_IPE_INPUT_IMAGE_DS4_REF         0x5\n#define CAM_ICP_IPE_INPUT_IMAGE_DS16_REF        0x6\n#define CAM_ICP_IPE_INPUT_IMAGE_DS64_REF        0x7\n\n/* IPE output port resource type */\n#define CAM_ICP_IPE_OUTPUT_IMAGE_DISPLAY        0x8\n#define CAM_ICP_IPE_OUTPUT_IMAGE_VIDEO          0x9\n#define CAM_ICP_IPE_OUTPUT_IMAGE_FULL_REF       0xA\n#define CAM_ICP_IPE_OUTPUT_IMAGE_DS4_REF        0xB\n#define CAM_ICP_IPE_OUTPUT_IMAGE_DS16_REF       0xC\n#define CAM_ICP_IPE_OUTPUT_IMAGE_DS64_REF       0xD\n\n#define CAM_ICP_IPE_IMAGE_MAX                   0xE\n\n/* BPS input port resource type */\n#define CAM_ICP_BPS_INPUT_IMAGE                 0x0\n\n/* BPS output port resource type */\n#define CAM_ICP_BPS_OUTPUT_IMAGE_FULL           0x1\n#define CAM_ICP_BPS_OUTPUT_IMAGE_DS4            0x2\n#define CAM_ICP_BPS_OUTPUT_IMAGE_DS16           0x3\n#define CAM_ICP_BPS_OUTPUT_IMAGE_DS64           0x4\n#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BG       0x5\n#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BHIST    0x6\n#define CAM_ICP_BPS_OUTPUT_IMAGE_REG1           0x7\n#define CAM_ICP_BPS_OUTPUT_IMAGE_REG2           0x8\n\n#define CAM_ICP_BPS_IO_IMAGES_MAX               0x9\n\n/* Command meta types */\n#define CAM_ICP_CMD_META_GENERIC_BLOB           0x1\n\n/* Generic blob types */\n#define CAM_ICP_CMD_GENERIC_BLOB_CLK            0x1\n#define CAM_ICP_CMD_GENERIC_BLOB_CFG_IO         0x2\n\n/**\n * struct cam_icp_clk_bw_request\n *\n * @budget_ns: Time required to process frame\n * @frame_cycles: Frame cycles needed to process the frame\n * @rt_flag: Flag to indicate real time stream\n * @uncompressed_bw: Bandwidth required to process frame\n * @compressed_bw: Compressed bandwidth to process frame\n */\nstruct cam_icp_clk_bw_request {\n\tuint64_t budget_ns;\n\tuint32_t frame_cycles;\n\tuint32_t rt_flag;\n\tuint64_t uncompressed_bw;\n\tuint64_t compressed_bw;\n};\n\n/**\n * struct cam_icp_dev_ver - Device information for particular hw type\n *\n * This is used to get device version info of\n * ICP, IPE, BPS and CDM related IPE and BPS from firmware\n * and use this info in CAM_QUERY_CAP IOCTL\n *\n * @dev_type: hardware type for the cap info(icp, ipe, bps, cdm(ipe/bps))\n * @reserved: reserved field\n * @hw_ver: major, minor and incr values of a device version\n */\nstruct cam_icp_dev_ver {\n\tuint32_t dev_type;\n\tuint32_t reserved;\n\tstruct cam_hw_version hw_ver;\n};\n\n/**\n * struct cam_icp_ver - ICP version info\n *\n * This strcuture is used for fw and api version\n * this is used to get firmware version and api version from firmware\n * and use this info in CAM_QUERY_CAP IOCTL\n *\n * @major: FW version major\n * @minor: FW version minor\n * @revision: FW version increment\n */\nstruct cam_icp_ver {\n\tuint32_t major;\n\tuint32_t minor;\n\tuint32_t revision;\n\tuint32_t reserved;\n};\n\n/**\n * struct cam_icp_query_cap_cmd - ICP query device capability payload\n *\n * @dev_iommu_handle: icp iommu handles for secure/non secure modes\n * @cdm_iommu_handle: iommu handles for secure/non secure modes\n * @fw_version: firmware version info\n * @api_version: api version info\n * @num_ipe: number of ipes\n * @num_bps: number of bps\n * @dev_ver: returned device capability array\n */\nstruct cam_icp_query_cap_cmd {\n\tstruct cam_iommu_handle dev_iommu_handle;\n\tstruct cam_iommu_handle cdm_iommu_handle;\n\tstruct cam_icp_ver fw_version;\n\tstruct cam_icp_ver api_version;\n\tuint32_t num_ipe;\n\tuint32_t num_bps;\n\tstruct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX];\n};\n\n/**\n * struct cam_icp_res_info - ICP output resource info\n *\n * @format: format of the resource\n * @width:  width in pixels\n * @height: height in lines\n * @fps:  fps\n */\nstruct cam_icp_res_info {\n\tuint32_t format;\n\tuint32_t width;\n\tuint32_t height;\n\tuint32_t fps;\n};\n\n/**\n * struct cam_icp_acquire_dev_info - An ICP device info\n *\n * @scratch_mem_size: Output param - size of scratch memory\n * @dev_type: device type (IPE_RT/IPE_NON_RT/BPS)\n * @io_config_cmd_size: size of IO config command\n * @io_config_cmd_handle: IO config command for each acquire\n * @secure_mode: camera mode (secure/non secure)\n * @chain_info: chaining info of FW device handles\n * @in_res: resource info used for clock and bandwidth calculation\n * @num_out_res: number of output resources\n * @out_res: output resource\n */\nstruct cam_icp_acquire_dev_info {\n\tuint32_t scratch_mem_size;\n\tuint32_t dev_type;\n\tuint32_t io_config_cmd_size;\n\tint32_t  io_config_cmd_handle;\n\tuint32_t secure_mode;\n\tint32_t chain_info;\n\tstruct cam_icp_res_info in_res;\n\tuint32_t num_out_res;\n\tstruct cam_icp_res_info out_res[1];\n} __attribute__((__packed__));\n\n#endif /* __UAPI_CAM_ICP_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_isp.h",
    "content": "#ifndef __UAPI_CAM_ISP_H__\n#define __UAPI_CAM_ISP_H__\n\n#include \"cam_defs.h\"\n#include \"cam_isp_vfe.h\"\n#include \"cam_isp_ife.h\"\n\n\n/* ISP driver name */\n#define CAM_ISP_DEV_NAME                        \"cam-isp\"\n\n/* HW type */\n#define CAM_ISP_HW_BASE                         0\n#define CAM_ISP_HW_CSID                         1\n#define CAM_ISP_HW_VFE                          2\n#define CAM_ISP_HW_IFE                          3\n#define CAM_ISP_HW_ISPIF                        4\n#define CAM_ISP_HW_MAX                          5\n\n/* Color Pattern */\n#define CAM_ISP_PATTERN_BAYER_RGRGRG            0\n#define CAM_ISP_PATTERN_BAYER_GRGRGR            1\n#define CAM_ISP_PATTERN_BAYER_BGBGBG            2\n#define CAM_ISP_PATTERN_BAYER_GBGBGB            3\n#define CAM_ISP_PATTERN_YUV_YCBYCR              4\n#define CAM_ISP_PATTERN_YUV_YCRYCB              5\n#define CAM_ISP_PATTERN_YUV_CBYCRY              6\n#define CAM_ISP_PATTERN_YUV_CRYCBY              7\n#define CAM_ISP_PATTERN_MAX                     8\n\n/* Usage Type */\n#define CAM_ISP_RES_USAGE_SINGLE                0\n#define CAM_ISP_RES_USAGE_DUAL                  1\n#define CAM_ISP_RES_USAGE_MAX                   2\n\n/* Resource ID */\n#define CAM_ISP_RES_ID_PORT                     0\n#define CAM_ISP_RES_ID_CLK                      1\n#define CAM_ISP_RES_ID_MAX                      2\n\n/* Resource Type - Type of resource for the resource id\n * defined in cam_isp_vfe.h, cam_isp_ife.h\n */\n\n/* Lane Type in input resource for Port */\n#define CAM_ISP_LANE_TYPE_DPHY                  0\n#define CAM_ISP_LANE_TYPE_CPHY                  1\n#define CAM_ISP_LANE_TYPE_MAX                   2\n\n/* ISP Resurce Composite Group ID */\n#define CAM_ISP_RES_COMP_GROUP_NONE             0\n#define CAM_ISP_RES_COMP_GROUP_ID_0             1\n#define CAM_ISP_RES_COMP_GROUP_ID_1             2\n#define CAM_ISP_RES_COMP_GROUP_ID_2             3\n#define CAM_ISP_RES_COMP_GROUP_ID_3             4\n#define CAM_ISP_RES_COMP_GROUP_ID_4             5\n#define CAM_ISP_RES_COMP_GROUP_ID_5             6\n#define CAM_ISP_RES_COMP_GROUP_ID_MAX           6\n\n/* ISP packet opcode for ISP */\n#define CAM_ISP_PACKET_OP_BASE                  0\n#define CAM_ISP_PACKET_INIT_DEV                 1\n#define CAM_ISP_PACKET_UPDATE_DEV               2\n#define CAM_ISP_PACKET_OP_MAX                   3\n\n/* ISP packet meta_data type for command buffer */\n#define CAM_ISP_PACKET_META_BASE                0\n#define CAM_ISP_PACKET_META_LEFT                1\n#define CAM_ISP_PACKET_META_RIGHT               2\n#define CAM_ISP_PACKET_META_COMMON              3\n#define CAM_ISP_PACKET_META_DMI_LEFT            4\n#define CAM_ISP_PACKET_META_DMI_RIGHT           5\n#define CAM_ISP_PACKET_META_DMI_COMMON          6\n#define CAM_ISP_PACKET_META_CLOCK               7\n#define CAM_ISP_PACKET_META_CSID                8\n#define CAM_ISP_PACKET_META_DUAL_CONFIG         9\n#define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT   10\n#define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT  11\n#define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12\n\n/* DSP mode */\n#define CAM_ISP_DSP_MODE_NONE                   0\n#define CAM_ISP_DSP_MODE_ONE_WAY                1\n#define CAM_ISP_DSP_MODE_ROUND                  2\n\n/* ISP Generic Cmd Buffer Blob types */\n#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG      0\n#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG    1\n#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG       2\n\n/* Query devices */\n/**\n * struct cam_isp_dev_cap_info - A cap info for particular hw type\n *\n * @hw_type:            Hardware type for the cap info\n * @reserved:           reserved field for alignment\n * @hw_version:         Hardware version\n *\n */\nstruct cam_isp_dev_cap_info {\n\tuint32_t              hw_type;\n\tuint32_t              reserved;\n\tstruct cam_hw_version hw_version;\n};\n\n/**\n * struct cam_isp_query_cap_cmd - ISP query device capability payload\n *\n * @device_iommu:               returned iommu handles for device\n * @cdm_iommu:                  returned iommu handles for cdm\n * @num_dev:                    returned number of device capabilities\n * @reserved:                   reserved field for alignment\n * @dev_caps:                   returned device capability array\n *\n */\nstruct cam_isp_query_cap_cmd {\n\tstruct cam_iommu_handle       device_iommu;\n\tstruct cam_iommu_handle       cdm_iommu;\n\tint32_t                       num_dev;\n\tuint32_t                      reserved;\n\tstruct cam_isp_dev_cap_info   dev_caps[CAM_ISP_HW_MAX];\n};\n\n/* Acquire Device */\n/**\n * struct cam_isp_out_port_info - An output port resource info\n *\n * @res_type:                   output resource type defined in file\n *                              cam_isp_vfe.h or cam_isp_ife.h\n * @format:                     output format of the resource\n * @wdith:                      output width in pixels\n * @height:                     output height in lines\n * @comp_grp_id:                composite group id for the resource.\n * @split_point:                split point in pixels for the dual VFE.\n * @secure_mode:                flag to tell if output should be run in secure\n *                              mode or not. See cam_defs.h for definition\n * @reserved:                   reserved field for alignment\n *\n */\nstruct cam_isp_out_port_info {\n\tuint32_t                res_type;\n\tuint32_t                format;\n\tuint32_t                width;\n\tuint32_t                height;\n\tuint32_t                comp_grp_id;\n\tuint32_t                split_point;\n\tuint32_t                secure_mode;\n\tuint32_t                reserved;\n};\n\n/**\n * struct cam_isp_in_port_info - An input port resource info\n *\n * @res_type:                   input resource type define in file\n *                              cam_isp_vfe.h or cam_isp_ife.h\n * @lane_type:                  lane type: c-phy or d-phy.\n * @lane_num:                   active lane number\n * @lane_cfg:                   lane configurations: 4 bits per lane\n * @vc:                         input virtual channel number\n * @dt:                         input data type number\n * @format:                     input format\n * @test_pattern:               test pattern for the testgen\n * @usage_type:                 whether dual vfe is required\n * @left_start:                 left input start offset in pixels\n * @left_stop:                  left input stop offset in pixels\n * @left_width:                 left input width in pixels\n * @right_start:                right input start offset in pixels.\n *                              Only for Dual VFE\n * @right_stop:                 right input stop offset in pixels.\n *                              Only for Dual VFE\n * @right_width:                right input width in pixels.\n *                              Only for dual VFE\n * @line_start:                 top of the line number\n * @line_stop:                  bottome of the line number\n * @height:                     input height in lines\n * @pixel_clk;                  sensor output clock\n * @batch_size:                 batch size for HFR mode\n * @dsp_mode:                   DSP stream mode (Defines as CAM_ISP_DSP_MODE_*)\n * @hbi_cnt:                    HBI count for the camif input\n * @reserved:                   Reserved field for alignment\n * @num_out_res:                number of the output resource associated\n * @data:                       payload that contains the output resources\n *\n */\nstruct cam_isp_in_port_info {\n\tuint32_t                        res_type;\n\tuint32_t                        lane_type;\n\tuint32_t                        lane_num;\n\tuint32_t                        lane_cfg;\n\tuint32_t                        vc;\n\tuint32_t                        dt;\n\tuint32_t                        format;\n\tuint32_t                        test_pattern;\n\tuint32_t                        usage_type;\n\tuint32_t                        left_start;\n\tuint32_t                        left_stop;\n\tuint32_t                        left_width;\n\tuint32_t                        right_start;\n\tuint32_t                        right_stop;\n\tuint32_t                        right_width;\n\tuint32_t                        line_start;\n\tuint32_t                        line_stop;\n\tuint32_t                        height;\n\tuint32_t                        pixel_clk;\n\tuint32_t                        batch_size;\n\tuint32_t                        dsp_mode;\n\tuint32_t                        hbi_cnt;\n        uint32_t                        custom_csid;\n\tuint32_t                        reserved;\n\tuint32_t                        num_out_res;\n\tstruct cam_isp_out_port_info    data[1];\n};\n\n/**\n * struct cam_isp_resource - A resource bundle\n *\n * @resoruce_id:                resource id for the resource bundle\n * @length:                     length of the while resource blob\n * @handle_type:                type of the resource handle\n * @reserved:                   reserved field for alignment\n * @res_hdl:                    resource handle that points to the\n *                                     resource array;\n *\n */\nstruct cam_isp_resource {\n\tuint32_t                       resource_id;\n\tuint32_t                       length;\n\tuint32_t                       handle_type;\n\tuint32_t                       reserved;\n\tuint64_t                       res_hdl;\n};\n\n/**\n * struct cam_isp_port_hfr_config - HFR configuration for this port\n *\n * @resource_type:              Resource type\n * @subsample_pattern:          Subsample pattern. Used in HFR mode. It\n *                              should be consistent with batchSize and\n *                              CAMIF programming.\n * @subsample_period:           Subsample period. Used in HFR mode. It\n *                              should be consistent with batchSize and\n *                              CAMIF programming.\n * @framedrop_pattern:          Framedrop pattern\n * @framedrop_period:           Framedrop period\n * @reserved:                   Reserved for alignment\n */\nstruct cam_isp_port_hfr_config {\n\tuint32_t                       resource_type;\n\tuint32_t                       subsample_pattern;\n\tuint32_t                       subsample_period;\n\tuint32_t                       framedrop_pattern;\n\tuint32_t                       framedrop_period;\n\tuint32_t                       reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_isp_resource_hfr_config - Resource HFR configuration\n *\n * @num_ports:                  Number of ports\n * @reserved:                   Reserved for alignment\n * @port_hfr_config:            HFR configuration for each IO port\n */\nstruct cam_isp_resource_hfr_config {\n\tuint32_t                       num_ports;\n\tuint32_t                       reserved;\n\tstruct cam_isp_port_hfr_config port_hfr_config[1];\n} __attribute__((packed));\n\n/**\n * struct cam_isp_dual_split_params - dual isp spilt parameters\n *\n * @split_point:                Split point information x, where (0 < x < width)\n *                              left ISP's input ends at x + righ padding and\n *                              Right ISP's input starts at x - left padding\n * @right_padding:              Padding added past the split point for left\n *                              ISP's input\n * @left_padding:               Padding added before split point for right\n *                              ISP's input\n * @reserved:                   Reserved filed for alignment\n *\n */\nstruct cam_isp_dual_split_params {\n\tuint32_t                       split_point;\n\tuint32_t                       right_padding;\n\tuint32_t                       left_padding;\n\tuint32_t                       reserved;\n};\n\n/**\n * struct cam_isp_dual_stripe_config - stripe config per bus client\n *\n * @offset:                     Start horizontal offset relative to\n *                              output buffer\n *                              In UBWC mode, this value indicates the H_INIT\n *                              value in pixel\n * @width:                      Width of the stripe in bytes\n * @tileconfig                  Ubwc meta tile config. Contain the partial\n *                              tile info\n * @port_id:                    port id of ISP output\n *\n */\nstruct cam_isp_dual_stripe_config {\n\tuint32_t                       offset;\n\tuint32_t                       width;\n\tuint32_t                       tileconfig;\n\tuint32_t                       port_id;\n};\n\n/**\n * struct cam_isp_dual_config - dual isp configuration\n *\n * @num_ports                   Number of isp output ports\n * @reserved                    Reserved field for alignment\n * @split_params:               Inpput split parameters\n * @stripes:                    Stripe information\n *\n */\nstruct cam_isp_dual_config {\n\tuint32_t                           num_ports;\n\tuint32_t                           reserved;\n\tstruct cam_isp_dual_split_params   split_params;\n\tstruct cam_isp_dual_stripe_config  stripes[1];\n} __attribute__((packed));\n\n/**\n * struct cam_isp_clock_config - Clock configuration\n *\n * @usage_type:                 Usage type (Single/Dual)\n * @num_rdi:                    Number of RDI votes\n * @left_pix_hz:                Pixel Clock for Left ISP\n * @right_pix_hz:               Pixel Clock for Right ISP, valid only if Dual\n * @rdi_hz:                     RDI Clock. ISP clock will be max of RDI and\n *                              PIX clocks. For a particular context which ISP\n *                              HW the RDI is allocated to is not known to UMD.\n *                              Hence pass the clock and let KMD decide.\n */\nstruct cam_isp_clock_config {\n\tuint32_t                       usage_type;\n\tuint32_t                       num_rdi;\n\tuint64_t                       left_pix_hz;\n\tuint64_t                       right_pix_hz;\n\tuint64_t                       rdi_hz[1];\n} __attribute__((packed));\n\n/**\n * struct cam_isp_bw_vote - Bandwidth vote information\n *\n * @resource_id:                Resource ID\n * @reserved:                   Reserved field for alignment\n * @cam_bw_bps:                 Bandwidth vote for CAMNOC\n * @ext_bw_bps:                 Bandwidth vote for path-to-DDR after CAMNOC\n */\n\nstruct cam_isp_bw_vote {\n\tuint32_t                       resource_id;\n\tuint32_t                       reserved;\n\tuint64_t                       cam_bw_bps;\n\tuint64_t                       ext_bw_bps;\n} __attribute__((packed));\n\n/**\n * struct cam_isp_bw_config - Bandwidth configuration\n *\n * @usage_type:                 Usage type (Single/Dual)\n * @num_rdi:                    Number of RDI votes\n * @left_pix_vote:              Bandwidth vote for left ISP\n * @right_pix_vote:             Bandwidth vote for right ISP\n * @rdi_vote:                   RDI bandwidth requirements\n */\n\nstruct cam_isp_bw_config {\n\tuint32_t                       usage_type;\n\tuint32_t                       num_rdi;\n\tstruct cam_isp_bw_vote         left_pix_vote;\n\tstruct cam_isp_bw_vote         right_pix_vote;\n\tstruct cam_isp_bw_vote         rdi_vote[1];\n} __attribute__((packed));\n\n#endif /* __UAPI_CAM_ISP_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_isp_ife.h",
    "content": "#ifndef __UAPI_CAM_ISP_IFE_H__\n#define __UAPI_CAM_ISP_IFE_H__\n\n/* IFE output port resource type (global unique)*/\n#define CAM_ISP_IFE_OUT_RES_BASE               0x3000\n\n#define CAM_ISP_IFE_OUT_RES_FULL               (CAM_ISP_IFE_OUT_RES_BASE + 0)\n#define CAM_ISP_IFE_OUT_RES_DS4                (CAM_ISP_IFE_OUT_RES_BASE + 1)\n#define CAM_ISP_IFE_OUT_RES_DS16               (CAM_ISP_IFE_OUT_RES_BASE + 2)\n#define CAM_ISP_IFE_OUT_RES_RAW_DUMP           (CAM_ISP_IFE_OUT_RES_BASE + 3)\n#define CAM_ISP_IFE_OUT_RES_FD                 (CAM_ISP_IFE_OUT_RES_BASE + 4)\n#define CAM_ISP_IFE_OUT_RES_PDAF               (CAM_ISP_IFE_OUT_RES_BASE + 5)\n#define CAM_ISP_IFE_OUT_RES_RDI_0              (CAM_ISP_IFE_OUT_RES_BASE + 6)\n#define CAM_ISP_IFE_OUT_RES_RDI_1              (CAM_ISP_IFE_OUT_RES_BASE + 7)\n#define CAM_ISP_IFE_OUT_RES_RDI_2              (CAM_ISP_IFE_OUT_RES_BASE + 8)\n#define CAM_ISP_IFE_OUT_RES_RDI_3              (CAM_ISP_IFE_OUT_RES_BASE + 9)\n#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BE       (CAM_ISP_IFE_OUT_RES_BASE + 10)\n#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST    (CAM_ISP_IFE_OUT_RES_BASE + 11)\n#define CAM_ISP_IFE_OUT_RES_STATS_TL_BG        (CAM_ISP_IFE_OUT_RES_BASE + 12)\n#define CAM_ISP_IFE_OUT_RES_STATS_BF           (CAM_ISP_IFE_OUT_RES_BASE + 13)\n#define CAM_ISP_IFE_OUT_RES_STATS_AWB_BG       (CAM_ISP_IFE_OUT_RES_BASE + 14)\n#define CAM_ISP_IFE_OUT_RES_STATS_BHIST        (CAM_ISP_IFE_OUT_RES_BASE + 15)\n#define CAM_ISP_IFE_OUT_RES_STATS_RS           (CAM_ISP_IFE_OUT_RES_BASE + 16)\n#define CAM_ISP_IFE_OUT_RES_STATS_CS           (CAM_ISP_IFE_OUT_RES_BASE + 17)\n#define CAM_ISP_IFE_OUT_RES_STATS_IHIST        (CAM_ISP_IFE_OUT_RES_BASE + 18)\n#define CAM_ISP_IFE_OUT_RES_MAX                (CAM_ISP_IFE_OUT_RES_BASE + 19)\n\n\n/* IFE input port resource type (global unique) */\n#define CAM_ISP_IFE_IN_RES_BASE                 0x4000\n\n#define CAM_ISP_IFE_IN_RES_TPG                 (CAM_ISP_IFE_IN_RES_BASE + 0)\n#define CAM_ISP_IFE_IN_RES_PHY_0               (CAM_ISP_IFE_IN_RES_BASE + 1)\n#define CAM_ISP_IFE_IN_RES_PHY_1               (CAM_ISP_IFE_IN_RES_BASE + 2)\n#define CAM_ISP_IFE_IN_RES_PHY_2               (CAM_ISP_IFE_IN_RES_BASE + 3)\n#define CAM_ISP_IFE_IN_RES_PHY_3               (CAM_ISP_IFE_IN_RES_BASE + 4)\n#define CAM_ISP_IFE_IN_RES_MAX                 (CAM_ISP_IFE_IN_RES_BASE + 5)\n\n#endif /* __UAPI_CAM_ISP_IFE_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_isp_vfe.h",
    "content": "#ifndef __UAPI_CAM_ISP_VFE_H__\n#define __UAPI_CAM_ISP_VFE_H__\n\n/* VFE output port resource type  (global unique)  */\n#define CAM_ISP_VFE_OUT_RES_BASE               0x1000\n\n#define CAM_ISP_VFE_OUT_RES_ENC                (CAM_ISP_VFE_OUT_RES_BASE + 0)\n#define CAM_ISP_VFE_OUT_RES_VIEW               (CAM_ISP_VFE_OUT_RES_BASE + 1)\n#define CAM_ISP_VFE_OUT_RES_VID                (CAM_ISP_VFE_OUT_RES_BASE + 2)\n#define CAM_ISP_VFE_OUT_RES_RDI_0              (CAM_ISP_VFE_OUT_RES_BASE + 3)\n#define CAM_ISP_VFE_OUT_RES_RDI_1              (CAM_ISP_VFE_OUT_RES_BASE + 4)\n#define CAM_ISP_VFE_OUT_RES_RDI_2              (CAM_ISP_VFE_OUT_RES_BASE + 5)\n#define CAM_ISP_VFE_OUT_RES_RDI_3              (CAM_ISP_VFE_OUT_RES_BASE + 6)\n#define CAM_ISP_VFE_OUT_RES_STATS_AEC          (CAM_ISP_VFE_OUT_RES_BASE + 7)\n#define CAM_ISP_VFE_OUT_RES_STATS_AF           (CAM_ISP_VFE_OUT_RES_BASE + 8)\n#define CAM_ISP_VFE_OUT_RES_STATS_AWB          (CAM_ISP_VFE_OUT_RES_BASE + 9)\n#define CAM_ISP_VFE_OUT_RES_STATS_RS           (CAM_ISP_VFE_OUT_RES_BASE + 10)\n#define CAM_ISP_VFE_OUT_RES_STATS_CS           (CAM_ISP_VFE_OUT_RES_BASE + 11)\n#define CAM_ISP_VFE_OUT_RES_STATS_IHIST        (CAM_ISP_VFE_OUT_RES_BASE + 12)\n#define CAM_ISP_VFE_OUT_RES_STATS_SKIN         (CAM_ISP_VFE_OUT_RES_BASE + 13)\n#define CAM_ISP_VFE_OUT_RES_STATS_BG           (CAM_ISP_VFE_OUT_RES_BASE + 14)\n#define CAM_ISP_VFE_OUT_RES_STATS_BF           (CAM_ISP_VFE_OUT_RES_BASE + 15)\n#define CAM_ISP_VFE_OUT_RES_STATS_BE           (CAM_ISP_VFE_OUT_RES_BASE + 16)\n#define CAM_ISP_VFE_OUT_RES_STATS_BHIST        (CAM_ISP_VFE_OUT_RES_BASE + 17)\n#define CAM_ISP_VFE_OUT_RES_STATS_BF_SCALE     (CAM_ISP_VFE_OUT_RES_BASE + 18)\n#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BE       (CAM_ISP_VFE_OUT_RES_BASE + 19)\n#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BHIST    (CAM_ISP_VFE_OUT_RES_BASE + 20)\n#define CAM_ISP_VFE_OUT_RES_STATS_AEC_BG       (CAM_ISP_VFE_OUT_RES_BASE + 21)\n#define CAM_ISP_VFE_OUT_RES_CAMIF_RAW          (CAM_ISP_VFE_OUT_RES_BASE + 22)\n#define CAM_ISP_VFE_OUT_RES_IDEAL_RAW          (CAM_ISP_VFE_OUT_RES_BASE + 23)\n#define CAM_ISP_VFE_OUT_RES_MAX                (CAM_ISP_VFE_OUT_RES_BASE + 24)\n\n/* VFE input port_ resource type (global unique) */\n#define CAM_ISP_VFE_IN_RES_BASE                0x2000\n\n#define CAM_ISP_VFE_IN_RES_TPG                 (CAM_ISP_VFE_IN_RES_BASE + 0)\n#define CAM_ISP_VFE_IN_RES_PHY_0               (CAM_ISP_VFE_IN_RES_BASE + 1)\n#define CAM_ISP_VFE_IN_RES_PHY_1               (CAM_ISP_VFE_IN_RES_BASE + 2)\n#define CAM_ISP_VFE_IN_RES_PHY_2               (CAM_ISP_VFE_IN_RES_BASE + 3)\n#define CAM_ISP_VFE_IN_RES_PHY_3               (CAM_ISP_VFE_IN_RES_BASE + 4)\n#define CAM_ISP_VFE_IN_RES_FE                  (CAM_ISP_VFE_IN_RES_BASE + 5)\n#define CAM_ISP_VFE_IN_RES_MAX                 (CAM_ISP_VFE_IN_RES_BASE + 6)\n\n#endif /* __UAPI_CAM_ISP_VFE_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_jpeg.h",
    "content": "#ifndef __UAPI_CAM_JPEG_H__\n#define __UAPI_CAM_JPEG_H__\n\n#include \"cam_defs.h\"\n\n/* enc, dma, cdm(enc/dma) are used in querycap */\n#define CAM_JPEG_DEV_TYPE_ENC      0\n#define CAM_JPEG_DEV_TYPE_DMA      1\n#define CAM_JPEG_DEV_TYPE_MAX      2\n\n#define CAM_JPEG_NUM_DEV_PER_RES_MAX      1\n\n/* definitions needed for jpeg aquire device */\n#define CAM_JPEG_RES_TYPE_ENC        0\n#define CAM_JPEG_RES_TYPE_DMA        1\n#define CAM_JPEG_RES_TYPE_MAX        2\n\n/* packet opcode types */\n#define CAM_JPEG_OPCODE_ENC_UPDATE 0\n#define CAM_JPEG_OPCODE_DMA_UPDATE 1\n\n/* ENC input port resource type */\n#define CAM_JPEG_ENC_INPUT_IMAGE                 0x0\n\n/* ENC output port resource type */\n#define CAM_JPEG_ENC_OUTPUT_IMAGE                0x1\n\n#define CAM_JPEG_ENC_IO_IMAGES_MAX               0x2\n\n/* DMA input port resource type */\n#define CAM_JPEG_DMA_INPUT_IMAGE                 0x0\n\n/* DMA output port resource type */\n#define CAM_JPEG_DMA_OUTPUT_IMAGE                0x1\n\n#define CAM_JPEG_DMA_IO_IMAGES_MAX               0x2\n\n#define CAM_JPEG_IMAGE_MAX                       0x2\n\n/**\n * struct cam_jpeg_dev_ver - Device information for particular hw type\n *\n * This is used to get device version info of JPEG ENC, JPEG DMA\n * from hardware and use this info in CAM_QUERY_CAP IOCTL\n *\n * @size : Size of struct passed\n * @dev_type: Hardware type for the cap info(jpeg enc, jpeg dma)\n * @hw_ver: Major, minor and incr values of a device version\n */\nstruct cam_jpeg_dev_ver {\n\tuint32_t size;\n\tuint32_t dev_type;\n\tstruct cam_hw_version hw_ver;\n};\n\n/**\n * struct cam_jpeg_query_cap_cmd - JPEG query device capability payload\n *\n * @dev_iommu_handle: Jpeg iommu handles for secure/non secure\n *      modes\n * @cdm_iommu_handle: Iommu handles for secure/non secure modes\n * @num_enc: Number of encoder\n * @num_dma: Number of dma\n * @dev_ver: Returned device capability array\n */\nstruct cam_jpeg_query_cap_cmd {\n\tstruct cam_iommu_handle dev_iommu_handle;\n\tstruct cam_iommu_handle cdm_iommu_handle;\n\tuint32_t num_enc;\n\tuint32_t num_dma;\n\tstruct cam_jpeg_dev_ver dev_ver[CAM_JPEG_DEV_TYPE_MAX];\n};\n\n/**\n * struct cam_jpeg_res_info - JPEG output resource info\n *\n * @format: Format of the resource\n * @width:  Width in pixels\n * @height: Height in lines\n * @fps:  Fps\n */\nstruct cam_jpeg_res_info {\n\tuint32_t format;\n\tuint32_t width;\n\tuint32_t height;\n\tuint32_t fps;\n};\n\n/**\n * struct cam_jpeg_acquire_dev_info - An JPEG device info\n *\n * @dev_type: Device type (ENC/DMA)\n * @reserved: Reserved Bytes\n * @in_res: In resource info\n * @in_res: Iut resource info\n */\nstruct cam_jpeg_acquire_dev_info {\n\tuint32_t dev_type;\n\tuint32_t reserved;\n\tstruct cam_jpeg_res_info in_res;\n\tstruct cam_jpeg_res_info out_res;\n};\n\n/**\n * struct cam_jpeg_config_inout_param_info - JPEG Config time\n *     input output params\n *\n * @clk_index: Input Param- clock selection index.(-1 default)\n * @output_size: Output Param - jpeg encode/dma output size in\n *     bytes\n */\nstruct cam_jpeg_config_inout_param_info {\n\tint32_t clk_index;\n\tint32_t output_size;\n};\n\n#endif /* __UAPI_CAM_JPEG_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_lrme.h",
    "content": "#ifndef __UAPI_CAM_LRME_H__\n#define __UAPI_CAM_LRME_H__\n\n#include \"cam_defs.h\"\n\n/* LRME Resource Types */\n\nenum CAM_LRME_IO_TYPE {\n\tCAM_LRME_IO_TYPE_TAR,\n\tCAM_LRME_IO_TYPE_REF,\n\tCAM_LRME_IO_TYPE_RES,\n\tCAM_LRME_IO_TYPE_DS2,\n};\n\n#define CAM_LRME_INPUT_PORT_TYPE_TAR (1 << 0)\n#define CAM_LRME_INPUT_PORT_TYPE_REF (1 << 1)\n\n#define CAM_LRME_OUTPUT_PORT_TYPE_DS2 (1 << 0)\n#define CAM_LRME_OUTPUT_PORT_TYPE_RES (1 << 1)\n\n#define CAM_LRME_DEV_MAX 1\n\n\nstruct cam_lrme_hw_version {\n\tuint32_t gen;\n\tuint32_t rev;\n\tuint32_t step;\n};\n\nstruct cam_lrme_dev_cap {\n\tstruct cam_lrme_hw_version clc_hw_version;\n\tstruct cam_lrme_hw_version bus_rd_hw_version;\n\tstruct cam_lrme_hw_version bus_wr_hw_version;\n\tstruct cam_lrme_hw_version top_hw_version;\n\tstruct cam_lrme_hw_version top_titan_version;\n};\n\n/**\n * struct cam_lrme_query_cap_cmd - LRME query device capability payload\n *\n * @dev_iommu_handle: LRME iommu handles for secure/non secure\n *      modes\n * @cdm_iommu_handle: Iommu handles for secure/non secure modes\n * @num_devices: number of hardware devices\n * @dev_caps: Returned device capability array\n */\nstruct cam_lrme_query_cap_cmd {\n\tstruct cam_iommu_handle device_iommu;\n\tstruct cam_iommu_handle cdm_iommu;\n\tuint32_t num_devices;\n\tstruct cam_lrme_dev_cap dev_caps[CAM_LRME_DEV_MAX];\n};\n\nstruct cam_lrme_soc_info {\n\tuint64_t clock_rate;\n\tuint64_t bandwidth;\n\tuint64_t reserved[4];\n};\n\nstruct cam_lrme_acquire_args {\n\tstruct cam_lrme_soc_info lrme_soc_info;\n};\n\n#endif /* __UAPI_CAM_LRME_H__ */\n\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_req_mgr.h",
    "content": "#ifndef __UAPI_LINUX_CAM_REQ_MGR_H\n#define __UAPI_LINUX_CAM_REQ_MGR_H\n\n#include <linux/videodev2.h>\n#include <linux/types.h>\n#include <linux/ioctl.h>\n#include <linux/media.h>\n#include <media/cam_defs.h>\n\n#define CAM_REQ_MGR_VNODE_NAME \"cam-req-mgr-devnode\"\n\n#define CAM_DEVICE_TYPE_BASE      (MEDIA_ENT_F_OLD_BASE)\n#define CAM_VNODE_DEVICE_TYPE     (CAM_DEVICE_TYPE_BASE)\n#define CAM_SENSOR_DEVICE_TYPE    (CAM_DEVICE_TYPE_BASE + 1)\n#define CAM_IFE_DEVICE_TYPE       (CAM_DEVICE_TYPE_BASE + 2)\n#define CAM_ICP_DEVICE_TYPE       (CAM_DEVICE_TYPE_BASE + 3)\n#define CAM_LRME_DEVICE_TYPE      (CAM_DEVICE_TYPE_BASE + 4)\n#define CAM_JPEG_DEVICE_TYPE      (CAM_DEVICE_TYPE_BASE + 5)\n#define CAM_FD_DEVICE_TYPE        (CAM_DEVICE_TYPE_BASE + 6)\n#define CAM_CPAS_DEVICE_TYPE      (CAM_DEVICE_TYPE_BASE + 7)\n#define CAM_CSIPHY_DEVICE_TYPE    (CAM_DEVICE_TYPE_BASE + 8)\n#define CAM_ACTUATOR_DEVICE_TYPE  (CAM_DEVICE_TYPE_BASE + 9)\n#define CAM_CCI_DEVICE_TYPE       (CAM_DEVICE_TYPE_BASE + 10)\n#define CAM_FLASH_DEVICE_TYPE     (CAM_DEVICE_TYPE_BASE + 11)\n#define CAM_EEPROM_DEVICE_TYPE    (CAM_DEVICE_TYPE_BASE + 12)\n#define CAM_OIS_DEVICE_TYPE       (CAM_DEVICE_TYPE_BASE + 13)\n\n/* cam_req_mgr hdl info */\n#define CAM_REQ_MGR_HDL_IDX_POS           8\n#define CAM_REQ_MGR_HDL_IDX_MASK          ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1)\n#define CAM_REQ_MGR_GET_HDL_IDX(hdl)      (hdl & CAM_REQ_MGR_HDL_IDX_MASK)\n\n/**\n * Max handles supported by cam_req_mgr\n * It includes both session and device handles\n */\n#define CAM_REQ_MGR_MAX_HANDLES           64\n#define MAX_LINKS_PER_SESSION             2\n\n/* V4L event type which user space will subscribe to */\n#define V4L_EVENT_CAM_REQ_MGR_EVENT       (V4L2_EVENT_PRIVATE_START + 0)\n\n/* Specific event ids to get notified in user space */\n#define V4L_EVENT_CAM_REQ_MGR_SOF            0\n#define V4L_EVENT_CAM_REQ_MGR_ERROR          1\n#define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS    2\n\n/* SOF Event status */\n#define CAM_REQ_MGR_SOF_EVENT_SUCCESS           0\n#define CAM_REQ_MGR_SOF_EVENT_ERROR             1\n\n/* Link control operations */\n#define CAM_REQ_MGR_LINK_ACTIVATE               0\n#define CAM_REQ_MGR_LINK_DEACTIVATE             1\n\n/**\n * Request Manager : flush_type\n * @CAM_REQ_MGR_FLUSH_TYPE_ALL: Req mgr will remove all the pending\n * requests from input/processing queue.\n * @CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ: Req mgr will remove only particular\n * request id from input/processing queue.\n * @CAM_REQ_MGR_FLUSH_TYPE_MAX: Max number of the flush type\n * @opcode: CAM_REQ_MGR_FLUSH_REQ\n */\n#define CAM_REQ_MGR_FLUSH_TYPE_ALL          0\n#define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ   1\n#define CAM_REQ_MGR_FLUSH_TYPE_MAX          2\n\n/**\n * Request Manager : Sync Mode type\n * @CAM_REQ_MGR_SYNC_MODE_NO_SYNC: Req mgr will apply non-sync mode for this\n * request.\n * @CAM_REQ_MGR_SYNC_MODE_SYNC: Req mgr will apply sync mode for this request.\n */\n#define CAM_REQ_MGR_SYNC_MODE_NO_SYNC   0\n#define CAM_REQ_MGR_SYNC_MODE_SYNC      1\n\n/**\n * struct cam_req_mgr_event_data\n * @session_hdl: session handle\n * @link_hdl: link handle\n * @frame_id: frame id\n * @reserved: reserved for 64 bit aligngment\n * @req_id: request id\n * @tv_sec: timestamp in seconds\n * @tv_usec: timestamp in micro seconds\n */\nstruct cam_req_mgr_event_data {\n\tint32_t   session_hdl;\n\tint32_t   link_hdl;\n\tint32_t   frame_id;\n\tint32_t   reserved;\n\tint64_t   req_id;\n\tuint64_t  tv_sec;\n\tuint64_t  tv_usec;\n};\n\n/**\n * struct cam_req_mgr_session_info\n * @session_hdl: In/Output param - session_handle\n * @opcode1: CAM_REQ_MGR_CREATE_SESSION\n * @opcode2: CAM_REQ_MGR_DESTROY_SESSION\n */\nstruct cam_req_mgr_session_info {\n\tint32_t session_hdl;\n\tint32_t reserved;\n};\n\n/**\n * struct cam_req_mgr_link_info\n * @session_hdl: Input param - Identifier for CSL session\n * @num_devices: Input Param - Num of devices to be linked\n * @dev_hdls: Input param - List of device handles to be linked\n * @link_hdl: Output Param -Identifier for link\n * @opcode: CAM_REQ_MGR_LINK\n */\nstruct cam_req_mgr_link_info {\n\tint32_t session_hdl;\n\tuint32_t num_devices;\n\tint32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES];\n\tint32_t link_hdl;\n};\n\n/**\n * struct cam_req_mgr_unlink_info\n * @session_hdl: input param - session handle\n * @link_hdl: input param - link handle\n * @opcode: CAM_REQ_MGR_UNLINK\n */\nstruct cam_req_mgr_unlink_info {\n\tint32_t session_hdl;\n\tint32_t link_hdl;\n};\n\n/**\n * struct cam_req_mgr_flush_info\n * @brief: User can tell drivers to flush a particular request id or\n * flush all requests from its pending processing queue. Flush is a\n * blocking call and driver shall ensure all requests are flushed\n * before returning.\n * @session_hdl: Input param - Identifier for CSL session\n * @link_hdl: Input Param -Identifier for link\n * @flush_type: User can cancel a particular req id or can flush\n * all requests in queue\n * @reserved: reserved for 64 bit aligngment\n * @req_id: field is valid only if flush type is cancel request\n * for flush all this field value is not considered.\n * @opcode: CAM_REQ_MGR_FLUSH_REQ\n */\nstruct cam_req_mgr_flush_info {\n\tint32_t session_hdl;\n\tint32_t link_hdl;\n\tuint32_t flush_type;\n\tuint32_t reserved;\n\tint64_t req_id;\n};\n\n/** struct cam_req_mgr_sched_info\n * @session_hdl: Input param - Identifier for CSL session\n * @link_hdl: Input Param -Identifier for link\n * inluding itself.\n * @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this\n * flag is set.\n * @sync_mode: Type of Sync mode for this request\n * @req_id: Input Param - Request Id from which all requests will be flushed\n */\nstruct cam_req_mgr_sched_request {\n\tint32_t session_hdl;\n\tint32_t link_hdl;\n\tint32_t bubble_enable;\n\tint32_t sync_mode;\n\tint64_t req_id;\n};\n\n/**\n * struct cam_req_mgr_sync_mode\n * @session_hdl:         Input param - Identifier for CSL session\n * @sync_mode:           Input Param - Type of sync mode\n * @num_links:           Input Param - Num of links in sync mode (Valid only\n *                             when sync_mode is one of SYNC enabled modes)\n * @link_hdls:           Input Param - Array of link handles to be in sync mode\n *                             (Valid only when sync_mode is one of SYNC\n *                             enabled modes)\n * @master_link_hdl:     Input Param - To dictate which link's SOF drives system\n *                             (Valid only when sync_mode is one of SYNC\n *                             enabled modes)\n *\n * @opcode: CAM_REQ_MGR_SYNC_MODE\n */\nstruct cam_req_mgr_sync_mode {\n\tint32_t session_hdl;\n\tint32_t sync_mode;\n\tint32_t num_links;\n\tint32_t link_hdls[MAX_LINKS_PER_SESSION];\n\tint32_t master_link_hdl;\n\tint32_t reserved;\n};\n\n/**\n * struct cam_req_mgr_link_control\n * @ops:                 Link operations: activate/deactive\n * @session_hdl:         Input param - Identifier for CSL session\n * @num_links:           Input Param - Num of links\n * @reserved:            reserved field\n * @link_hdls:           Input Param - Links to be activated/deactivated\n *\n * @opcode: CAM_REQ_MGR_LINK_CONTROL\n */\nstruct cam_req_mgr_link_control {\n\tint32_t ops;\n\tint32_t session_hdl;\n\tint32_t num_links;\n\tint32_t reserved;\n\tint32_t link_hdls[MAX_LINKS_PER_SESSION];\n};\n\n/**\n * cam_req_mgr specific opcode ids\n */\n#define CAM_REQ_MGR_CREATE_DEV_NODES            (CAM_COMMON_OPCODE_MAX + 1)\n#define CAM_REQ_MGR_CREATE_SESSION              (CAM_COMMON_OPCODE_MAX + 2)\n#define CAM_REQ_MGR_DESTROY_SESSION             (CAM_COMMON_OPCODE_MAX + 3)\n#define CAM_REQ_MGR_LINK                        (CAM_COMMON_OPCODE_MAX + 4)\n#define CAM_REQ_MGR_UNLINK                      (CAM_COMMON_OPCODE_MAX + 5)\n#define CAM_REQ_MGR_SCHED_REQ                   (CAM_COMMON_OPCODE_MAX + 6)\n#define CAM_REQ_MGR_FLUSH_REQ                   (CAM_COMMON_OPCODE_MAX + 7)\n#define CAM_REQ_MGR_SYNC_MODE                   (CAM_COMMON_OPCODE_MAX + 8)\n#define CAM_REQ_MGR_ALLOC_BUF                   (CAM_COMMON_OPCODE_MAX + 9)\n#define CAM_REQ_MGR_MAP_BUF                     (CAM_COMMON_OPCODE_MAX + 10)\n#define CAM_REQ_MGR_RELEASE_BUF                 (CAM_COMMON_OPCODE_MAX + 11)\n#define CAM_REQ_MGR_CACHE_OPS                   (CAM_COMMON_OPCODE_MAX + 12)\n#define CAM_REQ_MGR_LINK_CONTROL                (CAM_COMMON_OPCODE_MAX + 13)\n/* end of cam_req_mgr opcodes */\n\n#define CAM_MEM_FLAG_HW_READ_WRITE              (1<<0)\n#define CAM_MEM_FLAG_HW_READ_ONLY               (1<<1)\n#define CAM_MEM_FLAG_HW_WRITE_ONLY              (1<<2)\n#define CAM_MEM_FLAG_KMD_ACCESS                 (1<<3)\n#define CAM_MEM_FLAG_UMD_ACCESS                 (1<<4)\n#define CAM_MEM_FLAG_PROTECTED_MODE             (1<<5)\n#define CAM_MEM_FLAG_CMD_BUF_TYPE               (1<<6)\n#define CAM_MEM_FLAG_PIXEL_BUF_TYPE             (1<<7)\n#define CAM_MEM_FLAG_STATS_BUF_TYPE             (1<<8)\n#define CAM_MEM_FLAG_PACKET_BUF_TYPE            (1<<9)\n#define CAM_MEM_FLAG_CACHE                      (1<<10)\n#define CAM_MEM_FLAG_HW_SHARED_ACCESS           (1<<11)\n\n#define CAM_MEM_MMU_MAX_HANDLE                  16\n\n/* Maximum allowed buffers in existence */\n#define CAM_MEM_BUFQ_MAX                        1024\n\n#define CAM_MEM_MGR_SECURE_BIT_POS              15\n#define CAM_MEM_MGR_HDL_IDX_SIZE                15\n#define CAM_MEM_MGR_HDL_FD_SIZE                 16\n#define CAM_MEM_MGR_HDL_IDX_END_POS             16\n#define CAM_MEM_MGR_HDL_FD_END_POS              32\n\n#define CAM_MEM_MGR_HDL_IDX_MASK      ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1)\n\n#define GET_MEM_HANDLE(idx, fd) \\\n\t((idx & CAM_MEM_MGR_HDL_IDX_MASK) | \\\n\t(fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE))) \\\n\n#define GET_FD_FROM_HANDLE(hdl) \\\n\t(hdl >> (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE)) \\\n\n#define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK)\n\n#define CAM_MEM_MGR_SET_SECURE_HDL(hdl, flag) \\\n\t((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : \\\n\t((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS)))\n\n#define CAM_MEM_MGR_IS_SECURE_HDL(hdl) \\\n\t(((hdl) & \\\n\t(1<<CAM_MEM_MGR_SECURE_BIT_POS)) >> CAM_MEM_MGR_SECURE_BIT_POS)\n\n/**\n * memory allocation type\n */\n#define CAM_MEM_DMA_NONE                        0\n#define CAM_MEM_DMA_BIDIRECTIONAL               1\n#define CAM_MEM_DMA_TO_DEVICE                   2\n#define CAM_MEM_DMA_FROM_DEVICE                 3\n\n\n/**\n * memory cache operation\n */\n#define CAM_MEM_CLEAN_CACHE                     1\n#define CAM_MEM_INV_CACHE                       2\n#define CAM_MEM_CLEAN_INV_CACHE                 3\n\n\n/**\n * struct cam_mem_alloc_out_params\n * @buf_handle: buffer handle\n * @fd: output buffer file descriptor\n * @vaddr: virtual address pointer\n */\nstruct cam_mem_alloc_out_params {\n\tuint32_t buf_handle;\n\tint32_t fd;\n\tuint64_t vaddr;\n};\n\n/**\n * struct cam_mem_map_out_params\n * @buf_handle: buffer handle\n * @reserved: reserved for future\n * @vaddr: virtual address pointer\n */\nstruct cam_mem_map_out_params {\n\tuint32_t buf_handle;\n\tuint32_t reserved;\n\tuint64_t vaddr;\n};\n\n/**\n * struct cam_mem_mgr_alloc_cmd\n * @len: size of buffer to allocate\n * @align: alignment of the buffer\n * @mmu_hdls: array of mmu handles\n * @num_hdl: number of handles\n * @flags: flags of the buffer\n * @out: out params\n */\n/* CAM_REQ_MGR_ALLOC_BUF */\nstruct cam_mem_mgr_alloc_cmd {\n\tuint64_t len;\n\tuint64_t align;\n\tint32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE];\n\tuint32_t num_hdl;\n\tuint32_t flags;\n\tstruct cam_mem_alloc_out_params out;\n};\n\n/**\n * struct cam_mem_mgr_map_cmd\n * @mmu_hdls: array of mmu handles\n * @num_hdl: number of handles\n * @flags: flags of the buffer\n * @fd: output buffer file descriptor\n * @reserved: reserved field\n * @out: out params\n */\n\n/* CAM_REQ_MGR_MAP_BUF */\nstruct cam_mem_mgr_map_cmd {\n\tint32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE];\n\tuint32_t num_hdl;\n\tuint32_t flags;\n\tint32_t fd;\n\tuint32_t reserved;\n\tstruct cam_mem_map_out_params out;\n};\n\n/**\n * struct cam_mem_mgr_map_cmd\n * @buf_handle: buffer handle\n * @reserved: reserved field\n */\n/* CAM_REQ_MGR_RELEASE_BUF */\nstruct cam_mem_mgr_release_cmd {\n\tint32_t buf_handle;\n\tuint32_t reserved;\n};\n\n/**\n * struct cam_mem_mgr_map_cmd\n * @buf_handle: buffer handle\n * @ops: cache operations\n */\n/* CAM_REQ_MGR_CACHE_OPS */\nstruct cam_mem_cache_ops_cmd {\n\tint32_t buf_handle;\n\tuint32_t mem_cache_ops;\n};\n\n/**\n * Request Manager : error message type\n * @CAM_REQ_MGR_ERROR_TYPE_DEVICE: Device error message, fatal to session\n * @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal\n * @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal\n */\n#define CAM_REQ_MGR_ERROR_TYPE_DEVICE           0\n#define CAM_REQ_MGR_ERROR_TYPE_REQUEST          1\n#define CAM_REQ_MGR_ERROR_TYPE_BUFFER           2\n\n/**\n * struct cam_req_mgr_error_msg\n * @error_type: type of error\n * @request_id: request id of frame\n * @device_hdl: device handle\n * @linke_hdl: link_hdl\n * @resource_size: size of the resource\n */\nstruct cam_req_mgr_error_msg {\n\tuint32_t error_type;\n\tuint32_t request_id;\n\tint32_t device_hdl;\n\tint32_t link_hdl;\n\tuint64_t resource_size;\n};\n\n/**\n * struct cam_req_mgr_frame_msg\n * @request_id: request id of the frame\n * @frame_id: frame id of the frame\n * @timestamp: timestamp of the frame\n * @link_hdl: link handle associated with this message\n * @sof_status: sof status success or fail\n */\nstruct cam_req_mgr_frame_msg {\n\tuint64_t request_id;\n\tuint64_t frame_id;\n\tuint64_t timestamp;\n\tint32_t  link_hdl;\n\tuint32_t sof_status;\n};\n\n/**\n * struct cam_req_mgr_message\n * @session_hdl: session to which the frame belongs to\n * @reserved: reserved field\n * @u: union which can either be error or frame message\n */\nstruct cam_req_mgr_message {\n\tint32_t session_hdl;\n\tint32_t reserved;\n\tunion {\n\t\tstruct cam_req_mgr_error_msg err_msg;\n\t\tstruct cam_req_mgr_frame_msg frame_msg;\n\t} u;\n};\n#endif /* __UAPI_LINUX_CAM_REQ_MGR_H */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_sensor.h",
    "content": "#ifndef __UAPI_CAM_SENSOR_H__\n#define __UAPI_CAM_SENSOR_H__\n\n#include <linux/types.h>\n#include <linux/ioctl.h>\n#include <media/cam_defs.h>\n\n#define CAM_SENSOR_PROBE_CMD   (CAM_COMMON_OPCODE_MAX + 1)\n#define CAM_FLASH_MAX_LED_TRIGGERS 3\n#define MAX_OIS_NAME_SIZE 32\n#define CAM_CSIPHY_SECURE_MODE_ENABLED 1\n/**\n * struct cam_sensor_query_cap - capabilities info for sensor\n *\n * @slot_info        :  Indicates about the slotId or cell Index\n * @secure_camera    :  Camera is in secure/Non-secure mode\n * @pos_pitch        :  Sensor position pitch\n * @pos_roll         :  Sensor position roll\n * @pos_yaw          :  Sensor position yaw\n * @actuator_slot_id :  Actuator slot id which connected to sensor\n * @eeprom_slot_id   :  EEPROM slot id which connected to sensor\n * @ois_slot_id      :  OIS slot id which connected to sensor\n * @flash_slot_id    :  Flash slot id which connected to sensor\n * @csiphy_slot_id   :  CSIphy slot id which connected to sensor\n *\n */\nstruct  cam_sensor_query_cap {\n\tuint32_t        slot_info;\n\tuint32_t        secure_camera;\n\tuint32_t        pos_pitch;\n\tuint32_t        pos_roll;\n\tuint32_t        pos_yaw;\n\tuint32_t        actuator_slot_id;\n\tuint32_t        eeprom_slot_id;\n\tuint32_t        ois_slot_id;\n\tuint32_t        flash_slot_id;\n\tuint32_t        csiphy_slot_id;\n} __attribute__((packed));\n\n/**\n * struct cam_csiphy_query_cap - capabilities info for csiphy\n *\n * @slot_info        :  Indicates about the slotId or cell Index\n * @version          :  CSIphy version\n * @clk lane         :  Of the 5 lanes, informs lane configured\n *                      as clock lane\n * @reserved\n */\nstruct cam_csiphy_query_cap {\n\tuint32_t            slot_info;\n\tuint32_t            version;\n\tuint32_t            clk_lane;\n\tuint32_t            reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_actuator_query_cap - capabilities info for actuator\n *\n * @slot_info        :  Indicates about the slotId or cell Index\n * @reserved\n */\nstruct cam_actuator_query_cap {\n\tuint32_t            slot_info;\n\tuint32_t            reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_eeprom_query_cap_t - capabilities info for eeprom\n *\n * @slot_info                  :  Indicates about the slotId or cell Index\n * @eeprom_kernel_probe        :  Indicates about the kernel or userspace probe\n */\nstruct cam_eeprom_query_cap_t {\n\tuint32_t            slot_info;\n\tuint16_t            eeprom_kernel_probe;\n\tuint16_t            reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_ois_query_cap_t - capabilities info for ois\n *\n * @slot_info                  :  Indicates about the slotId or cell Index\n */\nstruct cam_ois_query_cap_t {\n\tuint32_t            slot_info;\n\tuint16_t            reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_i2c_info - Contains slave I2C related info\n *\n * @slave_addr      :    Slave address\n * @i2c_freq_mode   :    4 bits are used for I2c freq mode\n * @cmd_type        :    Explains type of command\n */\nstruct cam_cmd_i2c_info {\n\tuint16_t    slave_addr;\n\tuint8_t     i2c_freq_mode;\n\tuint8_t     cmd_type;\n} __attribute__((packed));\n\n/**\n * struct cam_ois_opcode - Contains OIS opcode\n *\n * @prog            :    OIS FW prog register address\n * @coeff           :    OIS FW coeff register address\n * @pheripheral     :    OIS pheripheral\n * @memory          :    OIS memory\n */\nstruct cam_ois_opcode {\n\tuint32_t prog;\n\tuint32_t coeff;\n\tuint32_t pheripheral;\n\tuint32_t memory;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_ois_info - Contains OIS slave info\n *\n * @slave_addr            :    OIS i2c slave address\n * @i2c_freq_mode         :    i2c frequency mode\n * @cmd_type              :    Explains type of command\n * @ois_fw_flag           :    indicates if fw is present or not\n * @is_ois_calib          :    indicates the calibration data is available\n * @ois_name              :    OIS name\n * @opcode                :    opcode\n */\nstruct cam_cmd_ois_info {\n\tuint16_t              slave_addr;\n\tuint8_t               i2c_freq_mode;\n\tuint8_t               cmd_type;\n\tuint8_t               ois_fw_flag;\n\tuint8_t               is_ois_calib;\n\tchar                  ois_name[MAX_OIS_NAME_SIZE];\n\tstruct cam_ois_opcode opcode;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_probe - Contains sensor slave info\n *\n * @data_type       :   Slave register data type\n * @addr_type       :   Slave register address type\n * @op_code         :   Don't Care\n * @cmd_type        :   Explains type of command\n * @reg_addr        :   Slave register address\n * @expected_data   :   Data expected at slave register address\n * @data_mask       :   Data mask if only few bits are valid\n * @camera_id       :   Indicates the slot to which camera\n *                      needs to be probed\n * @reserved\n */\nstruct cam_cmd_probe {\n\tuint8_t     data_type;\n\tuint8_t     addr_type;\n\tuint8_t     op_code;\n\tuint8_t     cmd_type;\n\tuint32_t    reg_addr;\n\tuint32_t    expected_data;\n\tuint32_t    data_mask;\n\tuint16_t    camera_id;\n\tuint16_t    reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_power_settings - Contains sensor power setting info\n *\n * @power_seq_type  :   Type of power sequence\n * @reserved\n * @config_val_low  :   Lower 32 bit value configuration value\n * @config_val_high :   Higher 32 bit value configuration value\n *\n */\nstruct cam_power_settings {\n\tuint16_t    power_seq_type;\n\tuint16_t    reserved;\n\tuint32_t    config_val_low;\n\tuint32_t    config_val_high;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_power - Explains about the power settings\n *\n * @count           :    Number of power settings follows\n * @reserved\n * @cmd_type        :    Explains type of command\n * @power_settings  :    Contains power setting info\n */\nstruct cam_cmd_power {\n\tuint16_t                    count;\n\tuint8_t                     reserved;\n\tuint8_t                     cmd_type;\n\tstruct cam_power_settings   power_settings[1];\n} __attribute__((packed));\n\n/**\n * struct i2c_rdwr_header - header of READ/WRITE I2C command\n *\n * @ count           :   Number of registers / data / reg-data pairs\n * @ op_code         :   Operation code\n * @ cmd_type        :   Command buffer type\n * @ data_type       :   I2C data type\n * @ addr_type       :   I2C address type\n * @ reserved\n */\nstruct i2c_rdwr_header {\n\tuint16_t    count;\n\tuint8_t     op_code;\n\tuint8_t     cmd_type;\n\tuint8_t     data_type;\n\tuint8_t     addr_type;\n\tuint16_t    reserved;\n} __attribute__((packed));\n\n/**\n * struct i2c_random_wr_payload - payload for I2C random write\n *\n * @ reg_addr        :   Register address\n * @ reg_data        :   Register data\n *\n */\nstruct i2c_random_wr_payload {\n\tuint32_t     reg_addr;\n\tuint32_t     reg_data;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_i2c_random_wr - I2C random write command\n * @ header            :   header of READ/WRITE I2C command\n * @ random_wr_payload :   payload for I2C random write\n */\nstruct cam_cmd_i2c_random_wr {\n\tstruct i2c_rdwr_header       header;\n\tstruct i2c_random_wr_payload random_wr_payload[1];\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_read - I2C read command\n * @ reg_data        :   Register data\n * @ reserved\n */\nstruct cam_cmd_read {\n\tuint32_t                reg_data;\n\tuint32_t                reserved;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_i2c_continuous_wr - I2C continuous write command\n * @ header          :   header of READ/WRITE I2C command\n * @ reg_addr        :   Register address\n * @ data_read       :   I2C read command\n */\nstruct cam_cmd_i2c_continuous_wr {\n\tstruct i2c_rdwr_header  header;\n\tuint32_t                reg_addr;\n\tstruct cam_cmd_read     data_read[1];\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_i2c_random_rd - I2C random read command\n * @ header          :   header of READ/WRITE I2C command\n * @ data_read       :   I2C read command\n */\nstruct cam_cmd_i2c_random_rd {\n\tstruct i2c_rdwr_header  header;\n\tstruct cam_cmd_read     data_read[1];\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_i2c_continuous_rd - I2C continuous continuous read command\n * @ header          :   header of READ/WRITE I2C command\n * @ reg_addr        :   Register address\n *\n */\nstruct cam_cmd_i2c_continuous_rd {\n\tstruct i2c_rdwr_header  header;\n\tuint32_t                reg_addr;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_conditional_wait - Conditional wait command\n * @data_type       :   Data type\n * @addr_type       :   Address type\n * @op_code         :   Opcode\n * @cmd_type        :   Explains type of command\n * @timeout         :   Timeout for retries\n * @reserved\n * @reg_addr        :   Register Address\n * @reg_data        :   Register data\n * @data_mask       :   Data mask if only few bits are valid\n * @camera_id       :   Indicates the slot to which camera\n *                      needs to be probed\n *\n */\nstruct cam_cmd_conditional_wait {\n\tuint8_t     data_type;\n\tuint8_t     addr_type;\n\tuint8_t     op_code;\n\tuint8_t     cmd_type;\n\tuint16_t    timeout;\n\tuint16_t    reserved;\n\tuint32_t    reg_addr;\n\tuint32_t    reg_data;\n\tuint32_t    data_mask;\n} __attribute__((packed));\n\n/**\n * struct cam_cmd_unconditional_wait - Un-conditional wait command\n * @delay           :   Delay\n * @op_code         :   Opcode\n * @cmd_type        :   Explains type of command\n */\nstruct cam_cmd_unconditional_wait {\n\tint16_t     delay;\n\tuint8_t     op_code;\n\tuint8_t     cmd_type;\n} __attribute__((packed));\n\n/**\n * cam_csiphy_info: Provides cmdbuffer structre\n * @lane_mask     : Lane mask details\n * @lane_assign   : Lane sensor will be using\n * @csiphy_3phase : Total number of lanes\n * @combo_mode    : Info regarding combo_mode is enable / disable\n * @lane_cnt      : Total number of lanes\n * @secure_mode   : Secure mode flag to enable / disable\n * @3phase        : Details whether 3Phase / 2Phase operation\n * @settle_time   : Settling time in ms\n * @data_rate     : Data rate\n *\n */\nstruct cam_csiphy_info {\n\tuint16_t    lane_mask;\n\tuint16_t    lane_assign;\n\tuint8_t     csiphy_3phase;\n\tuint8_t     combo_mode;\n\tuint8_t     lane_cnt;\n\tuint8_t     secure_mode;\n\tuint64_t    settle_time;\n\tuint64_t    data_rate;\n} __attribute__((packed));\n\n/**\n * cam_csiphy_acquire_dev_info : Information needed for\n *                        csiphy at the time of acquire\n * @combo_mode     :    Indicates the device mode of operation\n * @reserved\n *\n */\nstruct cam_csiphy_acquire_dev_info {\n\tuint32_t    combo_mode;\n\tuint32_t    reserved;\n} __attribute__((packed));\n\n/**\n * cam_sensor_acquire_dev : Updates sensor acuire cmd\n * @device_handle  :    Updates device handle\n * @session_handle :    Session handle for acquiring device\n * @handle_type    :    Resource handle type\n * @reserved\n * @info_handle    :    Handle to additional info\n *                      needed for sensor sub modules\n *\n */\nstruct cam_sensor_acquire_dev {\n\tuint32_t    session_handle;\n\tuint32_t    device_handle;\n\tuint32_t    handle_type;\n\tuint32_t    reserved;\n\tuint64_t    info_handle;\n} __attribute__((packed));\n\n/**\n * cam_sensor_streamon_dev : StreamOn command for the sensor\n * @session_handle :    Session handle for acquiring device\n * @device_handle  :    Updates device handle\n * @handle_type    :    Resource handle type\n * @reserved\n * @info_handle    :    Information Needed at the time of streamOn\n *\n */\nstruct cam_sensor_streamon_dev {\n\tuint32_t    session_handle;\n\tuint32_t    device_handle;\n\tuint32_t    handle_type;\n\tuint32_t    reserved;\n\tuint64_t    info_handle;\n} __attribute__((packed));\n\n/**\n * struct cam_flash_init : Init command for the flash\n * @flash_type  :    flash hw type\n * @reserved\n * @cmd_type    :    command buffer type\n */\nstruct cam_flash_init {\n\tuint8_t     flash_type;\n\tuint16_t    reserved;\n\tuint8_t     cmd_type;\n} __attribute__((packed));\n\n/**\n * struct cam_flash_set_rer : RedEyeReduction command buffer\n *\n * @count             :   Number of flash leds\n * @opcode            :   Command buffer opcode\n *\t\t\tCAM_FLASH_FIRE_RER\n * @cmd_type          :   command buffer operation type\n * @num_iteration     :   Number of led turn on/off sequence\n * @reserved\n * @led_on_delay_ms   :   flash led turn on time in ms\n * @led_off_delay_ms  :   flash led turn off time in ms\n * @led_current_ma    :   flash led current in ma\n *\n */\nstruct cam_flash_set_rer {\n\tuint16_t    count;\n\tuint8_t     opcode;\n\tuint8_t     cmd_type;\n\tuint16_t    num_iteration;\n\tuint16_t    reserved;\n\tuint32_t    led_on_delay_ms;\n\tuint32_t    led_off_delay_ms;\n\tuint32_t    led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS];\n} __attribute__((packed));\n\n/**\n * struct cam_flash_set_on_off : led turn on/off command buffer\n *\n * @count              :   Number of Flash leds\n * @opcode             :   command buffer opcodes\n *\t\t\tCAM_FLASH_FIRE_LOW\n *\t\t\tCAM_FLASH_FIRE_HIGH\n *\t\t\tCAM_FLASH_OFF\n * @cmd_type           :   command buffer operation type\n * @led_current_ma     :   flash led current in ma\n *\n */\nstruct cam_flash_set_on_off {\n\tuint16_t    count;\n\tuint8_t     opcode;\n\tuint8_t     cmd_type;\n\tuint32_t    led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS];\n} __attribute__((packed));\n\n/**\n * struct cam_flash_query_curr : query current command buffer\n *\n * @reserved\n * @opcode            :   command buffer opcode\n * @cmd_type          :   command buffer operation type\n * @query_current_ma  :   battery current in ma\n *\n */\nstruct cam_flash_query_curr {\n\tuint16_t    reserved;\n\tuint8_t     opcode;\n\tuint8_t     cmd_type;\n\tuint32_t    query_current_ma;\n} __attribute__ ((packed));\n\n/**\n * struct cam_flash_query_cap  :  capabilities info for flash\n *\n * @slot_info           :  Indicates about the slotId or cell Index\n * @max_current_flash   :  max supported current for flash\n * @max_duration_flash  :  max flash turn on duration\n * @max_current_torch   :  max supported current for torch\n *\n */\nstruct cam_flash_query_cap_info {\n\tuint32_t    slot_info;\n\tuint32_t    max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS];\n\tuint32_t    max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS];\n\tuint32_t    max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS];\n} __attribute__ ((packed));\n\n#endif\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_sensor_cmn_header.h",
    "content": "/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 and\n * only version 2 as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef _CAM_SENSOR_CMN_HEADER_\n#define _CAM_SENSOR_CMN_HEADER_\n\n#include <stdbool.h>\n#include <media/cam_sensor.h>\n#include <media/cam_req_mgr.h>\n\n#define MAX_REGULATOR 5\n#define MAX_POWER_CONFIG 12\n\n#define MAX_PER_FRAME_ARRAY 32\n#define BATCH_SIZE_MAX      16\n\n#define CAM_SENSOR_NAME    \"cam-sensor\"\n#define CAM_ACTUATOR_NAME  \"cam-actuator\"\n#define CAM_CSIPHY_NAME    \"cam-csiphy\"\n#define CAM_FLASH_NAME     \"cam-flash\"\n#define CAM_EEPROM_NAME    \"cam-eeprom\"\n#define CAM_OIS_NAME       \"cam-ois\"\n\n#define MAX_SYSTEM_PIPELINE_DELAY 2\n\n#define CAM_PKT_NOP_OPCODE 127\n\nenum camera_sensor_cmd_type {\n\tCAMERA_SENSOR_CMD_TYPE_INVALID,\n\tCAMERA_SENSOR_CMD_TYPE_PROBE,\n\tCAMERA_SENSOR_CMD_TYPE_PWR_UP,\n\tCAMERA_SENSOR_CMD_TYPE_PWR_DOWN,\n\tCAMERA_SENSOR_CMD_TYPE_I2C_INFO,\n\tCAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR,\n\tCAMERA_SENSOR_CMD_TYPE_I2C_RNDM_RD,\n\tCAMERA_SENSOR_CMD_TYPE_I2C_CONT_WR,\n\tCAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD,\n\tCAMERA_SENSOR_CMD_TYPE_WAIT,\n\tCAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO,\n\tCAMERA_SENSOR_FLASH_CMD_TYPE_FIRE,\n\tCAMERA_SENSOR_FLASH_CMD_TYPE_RER,\n\tCAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR,\n\tCAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET,\n\tCAMERA_SENSOR_CMD_TYPE_RD_DATA,\n\tCAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE,\n\tCAMERA_SENSOR_CMD_TYPE_MAX,\n};\n\nenum camera_sensor_i2c_op_code {\n\tCAMERA_SENSOR_I2C_OP_INVALID,\n\tCAMERA_SENSOR_I2C_OP_RNDM_WR,\n\tCAMERA_SENSOR_I2C_OP_RNDM_WR_VERF,\n\tCAMERA_SENSOR_I2C_OP_CONT_WR_BRST,\n\tCAMERA_SENSOR_I2C_OP_CONT_WR_BRST_VERF,\n\tCAMERA_SENSOR_I2C_OP_CONT_WR_SEQN,\n\tCAMERA_SENSOR_I2C_OP_CONT_WR_SEQN_VERF,\n\tCAMERA_SENSOR_I2C_OP_MAX,\n};\n\nenum camera_sensor_wait_op_code {\n\tCAMERA_SENSOR_WAIT_OP_INVALID,\n\tCAMERA_SENSOR_WAIT_OP_COND,\n\tCAMERA_SENSOR_WAIT_OP_HW_UCND,\n\tCAMERA_SENSOR_WAIT_OP_SW_UCND,\n\tCAMERA_SENSOR_WAIT_OP_MAX,\n};\n\nenum camera_flash_opcode {\n\tCAMERA_SENSOR_FLASH_OP_INVALID,\n\tCAMERA_SENSOR_FLASH_OP_OFF,\n\tCAMERA_SENSOR_FLASH_OP_FIRELOW,\n\tCAMERA_SENSOR_FLASH_OP_FIREHIGH,\n\tCAMERA_SENSOR_FLASH_OP_MAX,\n};\n\nenum camera_sensor_i2c_type {\n\tCAMERA_SENSOR_I2C_TYPE_INVALID,\n\tCAMERA_SENSOR_I2C_TYPE_BYTE,\n\tCAMERA_SENSOR_I2C_TYPE_WORD,\n\tCAMERA_SENSOR_I2C_TYPE_3B,\n\tCAMERA_SENSOR_I2C_TYPE_DWORD,\n\tCAMERA_SENSOR_I2C_TYPE_MAX,\n};\n\nenum i2c_freq_mode {\n\tI2C_STANDARD_MODE,\n\tI2C_FAST_MODE,\n\tI2C_CUSTOM_MODE,\n\tI2C_FAST_PLUS_MODE,\n\tI2C_MAX_MODES,\n};\n\nenum position_roll {\n\tROLL_0       = 0,\n\tROLL_90      = 90,\n\tROLL_180     = 180,\n\tROLL_270     = 270,\n\tROLL_INVALID = 360,\n};\n\nenum position_yaw {\n\tFRONT_CAMERA_YAW = 0,\n\tREAR_CAMERA_YAW  = 180,\n\tINVALID_YAW      = 360,\n};\n\nenum position_pitch {\n\tLEVEL_PITCH    = 0,\n\tINVALID_PITCH  = 360,\n};\n\nenum sensor_sub_module {\n\tSUB_MODULE_SENSOR,\n\tSUB_MODULE_ACTUATOR,\n\tSUB_MODULE_EEPROM,\n\tSUB_MODULE_LED_FLASH,\n\tSUB_MODULE_CSID,\n\tSUB_MODULE_CSIPHY,\n\tSUB_MODULE_OIS,\n\tSUB_MODULE_EXT,\n\tSUB_MODULE_MAX,\n};\n\nenum msm_camera_power_seq_type {\n\tSENSOR_MCLK,\n\tSENSOR_VANA,\n\tSENSOR_VDIG,\n\tSENSOR_VIO,\n\tSENSOR_VAF,\n\tSENSOR_VAF_PWDM,\n\tSENSOR_CUSTOM_REG1,\n\tSENSOR_CUSTOM_REG2,\n\tSENSOR_RESET,\n\tSENSOR_STANDBY,\n\tSENSOR_CUSTOM_GPIO1,\n\tSENSOR_CUSTOM_GPIO2,\n\tSENSOR_SEQ_TYPE_MAX,\n};\n\nenum cam_sensor_packet_opcodes {\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON,\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE,\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG,\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE,\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG,\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF,\n\tCAM_SENSOR_PACKET_OPCODE_SENSOR_NOP = 127\n};\n\nenum cam_actuator_packet_opcodes {\n\tCAM_ACTUATOR_PACKET_OPCODE_INIT,\n\tCAM_ACTUATOR_PACKET_AUTO_MOVE_LENS,\n\tCAM_ACTUATOR_PACKET_MANUAL_MOVE_LENS\n};\n\nenum cam_eeprom_packet_opcodes {\n\tCAM_EEPROM_PACKET_OPCODE_INIT\n};\n\nenum cam_ois_packet_opcodes {\n\tCAM_OIS_PACKET_OPCODE_INIT,\n\tCAM_OIS_PACKET_OPCODE_OIS_CONTROL\n};\n\nenum msm_bus_perf_setting {\n\tS_INIT,\n\tS_PREVIEW,\n\tS_VIDEO,\n\tS_CAPTURE,\n\tS_ZSL,\n\tS_STEREO_VIDEO,\n\tS_STEREO_CAPTURE,\n\tS_DEFAULT,\n\tS_LIVESHOT,\n\tS_DUAL,\n\tS_EXIT\n};\n\nenum msm_camera_device_type_t {\n\tMSM_CAMERA_I2C_DEVICE,\n\tMSM_CAMERA_PLATFORM_DEVICE,\n\tMSM_CAMERA_SPI_DEVICE,\n};\n\nenum cam_flash_device_type {\n\tCAMERA_FLASH_DEVICE_TYPE_PMIC = 0,\n\tCAMERA_FLASH_DEVICE_TYPE_I2C,\n\tCAMERA_FLASH_DEVICE_TYPE_GPIO,\n};\n\nenum cci_i2c_master_t {\n\tMASTER_0,\n\tMASTER_1,\n\tMASTER_MAX,\n};\n\nenum camera_vreg_type {\n\tVREG_TYPE_DEFAULT,\n\tVREG_TYPE_CUSTOM,\n};\n\nenum cam_sensor_i2c_cmd_type {\n\tCAM_SENSOR_I2C_WRITE_RANDOM,\n\tCAM_SENSOR_I2C_WRITE_BURST,\n\tCAM_SENSOR_I2C_WRITE_SEQ,\n\tCAM_SENSOR_I2C_READ,\n\tCAM_SENSOR_I2C_POLL\n};\n\nstruct common_header {\n\tuint16_t    first_word;\n\tuint8_t     third_byte;\n\tuint8_t     cmd_type;\n};\n\nstruct camera_vreg_t {\n\tconst char *reg_name;\n\tint min_voltage;\n\tint max_voltage;\n\tint op_mode;\n\tuint32_t delay;\n\tconst char *custom_vreg_name;\n\tenum camera_vreg_type type;\n};\n\nstruct msm_camera_gpio_num_info {\n\tuint16_t gpio_num[SENSOR_SEQ_TYPE_MAX];\n\tuint8_t valid[SENSOR_SEQ_TYPE_MAX];\n};\n\nstruct msm_cam_clk_info {\n\tconst char *clk_name;\n\tlong clk_rate;\n\tuint32_t delay;\n};\n\nstruct msm_pinctrl_info {\n\tstruct pinctrl *pinctrl;\n\tstruct pinctrl_state *gpio_state_active;\n\tstruct pinctrl_state *gpio_state_suspend;\n\tbool use_pinctrl;\n};\n\nstruct cam_sensor_i2c_reg_array {\n\tuint32_t reg_addr;\n\tuint32_t reg_data;\n\tuint32_t delay;\n\tuint32_t data_mask;\n};\n\nstruct cam_sensor_i2c_reg_setting {\n\tstruct cam_sensor_i2c_reg_array *reg_setting;\n\tunsigned short size;\n\tenum camera_sensor_i2c_type addr_type;\n\tenum camera_sensor_i2c_type data_type;\n\tunsigned short delay;\n};\n\n/*struct i2c_settings_list {\n\tstruct cam_sensor_i2c_reg_setting i2c_settings;\n\tenum cam_sensor_i2c_cmd_type op_code;\n\tstruct list_head list;\n};\n\nstruct i2c_settings_array {\n\tstruct list_head list_head;\n\tint32_t is_settings_valid;\n\tint64_t request_id;\n};\n\nstruct i2c_data_settings {\n\tstruct i2c_settings_array init_settings;\n\tstruct i2c_settings_array config_settings;\n\tstruct i2c_settings_array streamon_settings;\n\tstruct i2c_settings_array streamoff_settings;\n\tstruct i2c_settings_array *per_frame;\n};*/\n\nstruct cam_sensor_power_ctrl_t {\n\tstruct device *dev;\n\tstruct cam_sensor_power_setting *power_setting;\n\tuint16_t power_setting_size;\n\tstruct cam_sensor_power_setting *power_down_setting;\n\tuint16_t power_down_setting_size;\n\tstruct msm_camera_gpio_num_info *gpio_num_info;\n\tstruct msm_pinctrl_info pinctrl_info;\n\tuint8_t cam_pinctrl_status;\n};\n\nstruct cam_camera_slave_info {\n\tuint16_t sensor_slave_addr;\n\tuint16_t sensor_id_reg_addr;\n\tuint16_t sensor_id;\n\tuint16_t sensor_id_mask;\n};\n\nstruct msm_sensor_init_params {\n\tint modes_supported;\n\tunsigned int sensor_mount_angle;\n};\n\nenum msm_sensor_camera_id_t {\n\tCAMERA_0,\n\tCAMERA_1,\n\tCAMERA_2,\n\tCAMERA_3,\n\tCAMERA_4,\n\tCAMERA_5,\n\tCAMERA_6,\n\tMAX_CAMERAS,\n};\n\nstruct msm_sensor_id_info_t {\n\tunsigned short sensor_id_reg_addr;\n\tunsigned short sensor_id;\n\tunsigned short sensor_id_mask;\n};\n\nenum msm_sensor_output_format_t {\n\tMSM_SENSOR_BAYER,\n\tMSM_SENSOR_YCBCR,\n\tMSM_SENSOR_META,\n};\n\nstruct cam_sensor_power_setting {\n\tenum msm_camera_power_seq_type seq_type;\n\tunsigned short seq_val;\n\tlong config_val;\n\tunsigned short delay;\n\tvoid *data[10];\n};\n\nstruct cam_sensor_board_info {\n\tstruct cam_camera_slave_info slave_info;\n\tint32_t sensor_mount_angle;\n\tint32_t secure_mode;\n\tint modes_supported;\n\tint32_t pos_roll;\n\tint32_t pos_yaw;\n\tint32_t pos_pitch;\n\tint32_t  subdev_id[SUB_MODULE_MAX];\n\tint32_t  subdev_intf[SUB_MODULE_MAX];\n\tconst char *misc_regulator;\n\tstruct cam_sensor_power_ctrl_t power_info;\n};\n\nenum msm_camera_vreg_name_t {\n\tCAM_VDIG,\n\tCAM_VIO,\n\tCAM_VANA,\n\tCAM_VAF,\n\tCAM_V_CUSTOM1,\n\tCAM_V_CUSTOM2,\n\tCAM_VREG_MAX,\n};\n\nstruct msm_camera_gpio_conf {\n\tvoid *cam_gpiomux_conf_tbl;\n\tuint8_t cam_gpiomux_conf_tbl_size;\n\tstruct gpio *cam_gpio_common_tbl;\n\tuint8_t cam_gpio_common_tbl_size;\n\tstruct gpio *cam_gpio_req_tbl;\n\tuint8_t cam_gpio_req_tbl_size;\n\tuint32_t gpio_no_mux;\n\tuint32_t *camera_off_table;\n\tuint8_t camera_off_table_size;\n\tuint32_t *camera_on_table;\n\tuint8_t camera_on_table_size;\n\tstruct msm_camera_gpio_num_info *gpio_num_info;\n};\n\n/*for tof camera  Begin*/\nenum EEPROM_DATA_OP_T{\n\tEEPROM_DEFAULT_DATA = 0,\n\tEEPROM_INIT_DATA,\n\tEEPROM_CONFIG_DATA,\n\tEEPROM_STREAMON_DATA,\n\tEEPROM_STREAMOFF_DATA,\n\tEEPROM_OTHER_DATA,\n};\n/*for tof camera  End*/\n#endif /* _CAM_SENSOR_CMN_HEADER_ */\n"
  },
  {
    "path": "selfdrive/camerad/include/media/cam_sync.h",
    "content": "#ifndef __UAPI_CAM_SYNC_H__\n#define __UAPI_CAM_SYNC_H__\n\n#include <linux/videodev2.h>\n#include <linux/types.h>\n#include <linux/ioctl.h>\n#include <linux/media.h>\n\n#define CAM_SYNC_DEVICE_NAME                     \"cam_sync_device\"\n\n/* V4L event which user space will subscribe to */\n#define CAM_SYNC_V4L_EVENT                       (V4L2_EVENT_PRIVATE_START + 0)\n\n/* Specific event ids to get notified in user space */\n#define CAM_SYNC_V4L_EVENT_ID_CB_TRIG            0\n\n/* Size of opaque payload sent to kernel for safekeeping until signal time */\n#define CAM_SYNC_USER_PAYLOAD_SIZE               2\n\n/* Device type for sync device needed for device discovery */\n#define CAM_SYNC_DEVICE_TYPE                     (MEDIA_ENT_F_OLD_BASE)\n\n#define CAM_SYNC_GET_PAYLOAD_PTR(ev, type)       \\\n\t(type *)((char *)ev.u.data + sizeof(struct cam_sync_ev_header))\n\n#define CAM_SYNC_GET_HEADER_PTR(ev)              \\\n\t((struct cam_sync_ev_header *)ev.u.data)\n\n#define CAM_SYNC_STATE_INVALID                   0\n#define CAM_SYNC_STATE_ACTIVE                    1\n#define CAM_SYNC_STATE_SIGNALED_SUCCESS          2\n#define CAM_SYNC_STATE_SIGNALED_ERROR            3\n\n/**\n * struct cam_sync_ev_header - Event header for sync event notification\n *\n * @sync_obj: Sync object\n * @status:   Status of the object\n */\nstruct cam_sync_ev_header {\n\tint32_t sync_obj;\n\tint32_t status;\n};\n\n/**\n * struct cam_sync_info - Sync object creation information\n *\n * @name:       Optional string representation of the sync object\n * @sync_obj:   Sync object returned after creation in kernel\n */\nstruct cam_sync_info {\n\tchar name[64];\n\tint32_t sync_obj;\n};\n\n/**\n * struct cam_sync_signal - Sync object signaling struct\n *\n * @sync_obj:   Sync object to be signaled\n * @sync_state: State of the sync object to which it should be signaled\n */\nstruct cam_sync_signal {\n\tint32_t sync_obj;\n\tuint32_t sync_state;\n};\n\n/**\n * struct cam_sync_merge - Merge information for sync objects\n *\n * @sync_objs:  Pointer to sync objects\n * @num_objs:   Number of objects in the array\n * @merged:     Merged sync object\n */\nstruct cam_sync_merge {\n\t__u64 sync_objs;\n\tuint32_t num_objs;\n\tint32_t merged;\n};\n\n/**\n * struct cam_sync_userpayload_info - Payload info from user space\n *\n * @sync_obj:   Sync object for which payload has to be registered for\n * @reserved:   Reserved\n * @payload:    Pointer to user payload\n */\nstruct cam_sync_userpayload_info {\n\tint32_t sync_obj;\n\tuint32_t reserved;\n\t__u64 payload[CAM_SYNC_USER_PAYLOAD_SIZE];\n};\n\n/**\n * struct cam_sync_wait - Sync object wait information\n *\n * @sync_obj:   Sync object to wait on\n * @reserved:   Reserved\n * @timeout_ms: Timeout in milliseconds\n */\nstruct cam_sync_wait {\n\tint32_t sync_obj;\n\tuint32_t reserved;\n\tuint64_t timeout_ms;\n};\n\n/**\n * struct cam_private_ioctl_arg - Sync driver ioctl argument\n *\n * @id:         IOCTL command id\n * @size:       Size of command payload\n * @result:     Result of command execution\n * @reserved:   Reserved\n * @ioctl_ptr:  Pointer to user data\n */\nstruct cam_private_ioctl_arg {\n\t__u32 id;\n\t__u32 size;\n\t__u32 result;\n\t__u32 reserved;\n\t__u64 ioctl_ptr;\n};\n\n#define CAM_PRIVATE_IOCTL_CMD \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_private_ioctl_arg)\n\n#define CAM_SYNC_CREATE                          0\n#define CAM_SYNC_DESTROY                         1\n#define CAM_SYNC_SIGNAL                          2\n#define CAM_SYNC_MERGE                           3\n#define CAM_SYNC_REGISTER_PAYLOAD                4\n#define CAM_SYNC_DEREGISTER_PAYLOAD              5\n#define CAM_SYNC_WAIT                            6\n\n#endif /* __UAPI_CAM_SYNC_H__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/msm_cam_sensor.h",
    "content": "#ifndef __LINUX_MSM_CAM_SENSOR_H\n#define __LINUX_MSM_CAM_SENSOR_H\n\n#ifdef MSM_CAMERA_BIONIC\n#include <sys/types.h>\n#endif\n\n//#include <linux/v4l2-mediabus.h>\n#include \"msm_camsensor_sdk.h\"\n\n#include <linux/types.h>\n#include <linux/i2c.h>\n#ifdef CONFIG_COMPAT\n#include <linux/compat.h>\n#endif\n\n#define I2C_SEQ_REG_SETTING_MAX   5\n\n#define MSM_SENSOR_MCLK_8HZ   8000000\n#define MSM_SENSOR_MCLK_16HZ  16000000\n#define MSM_SENSOR_MCLK_24HZ  24000000\n\n#define MAX_SENSOR_NAME 32\n#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024\n\n#define MAX_OIS_MOD_NAME_SIZE 32\n#define MAX_OIS_NAME_SIZE 32\n#define MAX_OIS_REG_SETTINGS 800\n\n#define MOVE_NEAR 0\n#define MOVE_FAR  1\n\n#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1\n#define MSM_ACTUATOR_MOVE_SIGNED_NEAR  1\n\n#define MAX_ACTUATOR_REGION  5\n\n#define MAX_EEPROM_NAME 32\n\n#define MAX_AF_ITERATIONS 3\n#define MAX_NUMBER_OF_STEPS 47\n#define MAX_REGULATOR 5\n\n#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */\n#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')\n\t/* 14  BGBG.. GRGR.. */\n#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')\n\t/* 14  GBGB.. RGRG.. */\n#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')\n\t/* 14  GRGR.. BGBG.. */\n#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')\n\t/* 14  RGRG.. GBGB.. */\n\nenum flash_type {\n\tLED_FLASH = 1,\n\tSTROBE_FLASH,\n\tGPIO_FLASH\n};\n\nenum msm_sensor_resolution_t {\n\tMSM_SENSOR_RES_FULL,\n\tMSM_SENSOR_RES_QTR,\n\tMSM_SENSOR_RES_2,\n\tMSM_SENSOR_RES_3,\n\tMSM_SENSOR_RES_4,\n\tMSM_SENSOR_RES_5,\n\tMSM_SENSOR_RES_6,\n\tMSM_SENSOR_RES_7,\n\tMSM_SENSOR_INVALID_RES,\n};\n\nenum msm_camera_stream_type_t {\n\tMSM_CAMERA_STREAM_PREVIEW,\n\tMSM_CAMERA_STREAM_SNAPSHOT,\n\tMSM_CAMERA_STREAM_VIDEO,\n\tMSM_CAMERA_STREAM_INVALID,\n};\n\nenum sensor_sub_module_t {\n\tSUB_MODULE_SENSOR,\n\tSUB_MODULE_CHROMATIX,\n\tSUB_MODULE_ACTUATOR,\n\tSUB_MODULE_EEPROM,\n\tSUB_MODULE_LED_FLASH,\n\tSUB_MODULE_STROBE_FLASH,\n\tSUB_MODULE_CSID,\n\tSUB_MODULE_CSID_3D,\n\tSUB_MODULE_CSIPHY,\n\tSUB_MODULE_CSIPHY_3D,\n\tSUB_MODULE_OIS,\n\tSUB_MODULE_EXT,\n\tSUB_MODULE_MAX,\n};\n\nenum {\n\tMSM_CAMERA_EFFECT_MODE_OFF,\n\tMSM_CAMERA_EFFECT_MODE_MONO,\n\tMSM_CAMERA_EFFECT_MODE_NEGATIVE,\n\tMSM_CAMERA_EFFECT_MODE_SOLARIZE,\n\tMSM_CAMERA_EFFECT_MODE_SEPIA,\n\tMSM_CAMERA_EFFECT_MODE_POSTERIZE,\n\tMSM_CAMERA_EFFECT_MODE_WHITEBOARD,\n\tMSM_CAMERA_EFFECT_MODE_BLACKBOARD,\n\tMSM_CAMERA_EFFECT_MODE_AQUA,\n\tMSM_CAMERA_EFFECT_MODE_EMBOSS,\n\tMSM_CAMERA_EFFECT_MODE_SKETCH,\n\tMSM_CAMERA_EFFECT_MODE_NEON,\n\tMSM_CAMERA_EFFECT_MODE_MAX\n};\n\nenum {\n\tMSM_CAMERA_WB_MODE_AUTO,\n\tMSM_CAMERA_WB_MODE_CUSTOM,\n\tMSM_CAMERA_WB_MODE_INCANDESCENT,\n\tMSM_CAMERA_WB_MODE_FLUORESCENT,\n\tMSM_CAMERA_WB_MODE_WARM_FLUORESCENT,\n\tMSM_CAMERA_WB_MODE_DAYLIGHT,\n\tMSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT,\n\tMSM_CAMERA_WB_MODE_TWILIGHT,\n\tMSM_CAMERA_WB_MODE_SHADE,\n\tMSM_CAMERA_WB_MODE_OFF,\n\tMSM_CAMERA_WB_MODE_MAX\n};\n\nenum {\n\tMSM_CAMERA_SCENE_MODE_OFF,\n\tMSM_CAMERA_SCENE_MODE_AUTO,\n\tMSM_CAMERA_SCENE_MODE_LANDSCAPE,\n\tMSM_CAMERA_SCENE_MODE_SNOW,\n\tMSM_CAMERA_SCENE_MODE_BEACH,\n\tMSM_CAMERA_SCENE_MODE_SUNSET,\n\tMSM_CAMERA_SCENE_MODE_NIGHT,\n\tMSM_CAMERA_SCENE_MODE_PORTRAIT,\n\tMSM_CAMERA_SCENE_MODE_BACKLIGHT,\n\tMSM_CAMERA_SCENE_MODE_SPORTS,\n\tMSM_CAMERA_SCENE_MODE_ANTISHAKE,\n\tMSM_CAMERA_SCENE_MODE_FLOWERS,\n\tMSM_CAMERA_SCENE_MODE_CANDLELIGHT,\n\tMSM_CAMERA_SCENE_MODE_FIREWORKS,\n\tMSM_CAMERA_SCENE_MODE_PARTY,\n\tMSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT,\n\tMSM_CAMERA_SCENE_MODE_THEATRE,\n\tMSM_CAMERA_SCENE_MODE_ACTION,\n\tMSM_CAMERA_SCENE_MODE_AR,\n\tMSM_CAMERA_SCENE_MODE_FACE_PRIORITY,\n\tMSM_CAMERA_SCENE_MODE_BARCODE,\n\tMSM_CAMERA_SCENE_MODE_HDR,\n\tMSM_CAMERA_SCENE_MODE_MAX\n};\n\nenum csid_cfg_type_t {\n\tCSID_INIT,\n\tCSID_CFG,\n\tCSID_TESTMODE_CFG,\n\tCSID_RELEASE,\n};\n\nenum csiphy_cfg_type_t {\n\tCSIPHY_INIT,\n\tCSIPHY_CFG,\n\tCSIPHY_RELEASE,\n};\n\nenum camera_vreg_type {\n\tVREG_TYPE_DEFAULT,\n\tVREG_TYPE_CUSTOM,\n};\n\nenum sensor_af_t {\n\tSENSOR_AF_FOCUSSED,\n\tSENSOR_AF_NOT_FOCUSSED,\n};\n\nenum cci_i2c_master_t {\n\tMASTER_0,\n\tMASTER_1,\n\tMASTER_MAX,\n};\n\nstruct msm_camera_i2c_array_write_config {\n\tstruct msm_camera_i2c_reg_setting conf_array;\n\tuint16_t slave_addr;\n};\n\nstruct msm_camera_i2c_read_config {\n\tuint16_t slave_addr;\n\tuint16_t reg_addr;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tenum msm_camera_i2c_data_type data_type;\n\tuint16_t data;\n};\n\nstruct msm_camera_csi2_params {\n\tstruct msm_camera_csid_params csid_params;\n\tstruct msm_camera_csiphy_params csiphy_params;\n\tuint8_t csi_clk_scale_enable;\n};\n\nstruct msm_camera_csi_lane_params {\n\tuint16_t csi_lane_assign;\n\tuint16_t csi_lane_mask;\n};\n\nstruct csi_lane_params_t {\n\tuint16_t csi_lane_assign;\n\tuint8_t csi_lane_mask;\n\tuint8_t csi_if;\n\tint8_t csid_core[2];\n\tuint8_t csi_phy_sel;\n};\n\nstruct msm_sensor_info_t {\n\tchar     sensor_name[MAX_SENSOR_NAME];\n\tuint32_t session_id;\n\tint32_t  subdev_id[SUB_MODULE_MAX];\n\tint32_t  subdev_intf[SUB_MODULE_MAX];\n\tuint8_t  is_mount_angle_valid;\n\tuint32_t sensor_mount_angle;\n\tint modes_supported;\n\tenum camb_position_t position;\n};\n\nstruct camera_vreg_t {\n\tconst char *reg_name;\n\tint min_voltage;\n\tint max_voltage;\n\tint op_mode;\n\tuint32_t delay;\n\tconst char *custom_vreg_name;\n\tenum camera_vreg_type type;\n};\n\nstruct sensorb_cfg_data {\n\tint cfgtype;\n\tunion {\n\t\tstruct msm_sensor_info_t      sensor_info;\n\t\tstruct msm_sensor_init_params sensor_init_params;\n\t\tvoid                         *setting;\n\t\tstruct msm_sensor_i2c_sync_params sensor_i2c_sync_params;\n\t} cfg;\n};\n\nstruct csid_cfg_data {\n\tenum csid_cfg_type_t cfgtype;\n\tunion {\n\t\tuint32_t csid_version;\n\t\tstruct msm_camera_csid_params *csid_params;\n\t\tstruct msm_camera_csid_testmode_parms *csid_testmode_params;\n\t} cfg;\n};\n\nstruct csiphy_cfg_data {\n\tenum csiphy_cfg_type_t cfgtype;\n\tunion {\n\t\tstruct msm_camera_csiphy_params *csiphy_params;\n\t\tstruct msm_camera_csi_lane_params *csi_lane_params;\n\t} cfg;\n};\n\nenum eeprom_cfg_type_t {\n\tCFG_EEPROM_GET_INFO,\n\tCFG_EEPROM_GET_CAL_DATA,\n\tCFG_EEPROM_READ_CAL_DATA,\n\tCFG_EEPROM_WRITE_DATA,\n\tCFG_EEPROM_GET_MM_INFO,\n\tCFG_EEPROM_INIT,\n};\n\nstruct eeprom_get_t {\n\tuint32_t num_bytes;\n};\n\nstruct eeprom_read_t {\n\tuint8_t *dbuffer;\n\tuint32_t num_bytes;\n};\n\nstruct eeprom_write_t {\n\tuint8_t *dbuffer;\n\tuint32_t num_bytes;\n};\n\nstruct eeprom_get_cmm_t {\n\tuint32_t cmm_support;\n\tuint32_t cmm_compression;\n\tuint32_t cmm_size;\n};\n\nstruct msm_eeprom_info_t {\n\tstruct msm_sensor_power_setting_array *power_setting_array;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tstruct msm_eeprom_memory_map_array *mem_map_array;\n};\n\nstruct msm_eeprom_cfg_data {\n\tenum eeprom_cfg_type_t cfgtype;\n\tuint8_t is_supported;\n\tunion {\n\t\tchar eeprom_name[MAX_SENSOR_NAME];\n\t\tstruct eeprom_get_t get_data;\n\t\tstruct eeprom_read_t read_data;\n\t\tstruct eeprom_write_t write_data;\n\t\tstruct eeprom_get_cmm_t get_cmm_data;\n\t\tstruct msm_eeprom_info_t eeprom_info;\n\t} cfg;\n};\n\n#ifdef CONFIG_COMPAT\nstruct msm_sensor_power_setting32 {\n\tenum msm_sensor_power_seq_type_t seq_type;\n\tuint16_t seq_val;\n\tcompat_uint_t config_val;\n\tuint16_t delay;\n\tcompat_uptr_t data[10];\n};\n\nstruct msm_sensor_power_setting_array32 {\n\tstruct msm_sensor_power_setting32 power_setting_a[MAX_POWER_CONFIG];\n\tcompat_uptr_t power_setting;\n\tuint16_t size;\n\tstruct msm_sensor_power_setting32\n\t\tpower_down_setting_a[MAX_POWER_CONFIG];\n\tcompat_uptr_t power_down_setting;\n\tuint16_t size_down;\n};\n\nstruct msm_camera_sensor_slave_info32 {\n\tchar sensor_name[32];\n\tchar eeprom_name[32];\n\tchar actuator_name[32];\n\tchar ois_name[32];\n\tchar flash_name[32];\n\tenum msm_sensor_camera_id_t camera_id;\n\tuint16_t slave_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tstruct msm_sensor_id_info_t sensor_id_info;\n\tstruct msm_sensor_power_setting_array32 power_setting_array;\n\tuint8_t  is_init_params_valid;\n\tstruct msm_sensor_init_params sensor_init_params;\n\tenum msm_sensor_output_format_t output_format;\n};\n\nstruct msm_camera_csid_lut_params32 {\n\tuint8_t num_cid;\n\tstruct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];\n\tcompat_uptr_t vc_cfg[MAX_CID];\n};\n\nstruct msm_camera_csid_params32 {\n\tuint8_t lane_cnt;\n\tuint16_t lane_assign;\n\tuint8_t phy_sel;\n\tuint32_t csi_clk;\n\tstruct msm_camera_csid_lut_params32 lut_params;\n\tuint8_t csi_3p_sel;\n};\n\nstruct msm_camera_csi2_params32 {\n\tstruct msm_camera_csid_params32 csid_params;\n\tstruct msm_camera_csiphy_params csiphy_params;\n\tuint8_t csi_clk_scale_enable;\n};\n\nstruct csid_cfg_data32 {\n\tenum csid_cfg_type_t cfgtype;\n\tunion {\n\t\tuint32_t csid_version;\n\t\tcompat_uptr_t csid_params;\n\t\tcompat_uptr_t csid_testmode_params;\n\t} cfg;\n};\n\nstruct eeprom_read_t32 {\n\tcompat_uptr_t dbuffer;\n\tuint32_t num_bytes;\n};\n\nstruct eeprom_write_t32 {\n\tcompat_uptr_t dbuffer;\n\tuint32_t num_bytes;\n};\n\nstruct msm_eeprom_info_t32 {\n\tcompat_uptr_t power_setting_array;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tcompat_uptr_t mem_map_array;\n};\n\nstruct msm_eeprom_cfg_data32 {\n\tenum eeprom_cfg_type_t cfgtype;\n\tuint8_t is_supported;\n\tunion {\n\t\tchar eeprom_name[MAX_SENSOR_NAME];\n\t\tstruct eeprom_get_t get_data;\n\t\tstruct eeprom_read_t32 read_data;\n\t\tstruct eeprom_write_t32 write_data;\n\t\tstruct msm_eeprom_info_t32 eeprom_info;\n\t} cfg;\n};\n\nstruct msm_camera_i2c_seq_reg_setting32 {\n\tcompat_uptr_t reg_setting;\n\tuint16_t size;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tuint16_t delay;\n};\n#endif\n\nenum msm_sensor_cfg_type_t {\n\tCFG_SET_SLAVE_INFO,\n\tCFG_SLAVE_READ_I2C,\n\tCFG_WRITE_I2C_ARRAY,\n\tCFG_SLAVE_WRITE_I2C_ARRAY,\n\tCFG_WRITE_I2C_SEQ_ARRAY,\n\tCFG_POWER_UP,\n\tCFG_POWER_DOWN,\n\tCFG_SET_STOP_STREAM_SETTING,\n\tCFG_GET_SENSOR_INFO,\n\tCFG_GET_SENSOR_INIT_PARAMS,\n\tCFG_SET_INIT_SETTING,\n\tCFG_SET_RESOLUTION,\n\tCFG_SET_STOP_STREAM,\n\tCFG_SET_START_STREAM,\n\tCFG_SET_SATURATION,\n\tCFG_SET_CONTRAST,\n\tCFG_SET_SHARPNESS,\n\tCFG_SET_ISO,\n\tCFG_SET_EXPOSURE_COMPENSATION,\n\tCFG_SET_ANTIBANDING,\n\tCFG_SET_BESTSHOT_MODE,\n\tCFG_SET_EFFECT,\n\tCFG_SET_WHITE_BALANCE,\n\tCFG_SET_AUTOFOCUS,\n\tCFG_CANCEL_AUTOFOCUS,\n\tCFG_SET_STREAM_TYPE,\n\tCFG_SET_I2C_SYNC_PARAM,\n\tCFG_WRITE_I2C_ARRAY_ASYNC,\n\tCFG_WRITE_I2C_ARRAY_SYNC,\n\tCFG_WRITE_I2C_ARRAY_SYNC_BLOCK,\n};\n\nenum msm_actuator_cfg_type_t {\n\tCFG_GET_ACTUATOR_INFO,\n\tCFG_SET_ACTUATOR_INFO,\n\tCFG_SET_DEFAULT_FOCUS,\n\tCFG_MOVE_FOCUS,\n\tCFG_SET_POSITION,\n\tCFG_ACTUATOR_POWERDOWN,\n\tCFG_ACTUATOR_POWERUP,\n\tCFG_ACTUATOR_INIT,\n};\n\nenum msm_ois_cfg_type_t {\n\tCFG_OIS_INIT,\n\tCFG_OIS_POWERDOWN,\n\tCFG_OIS_POWERUP,\n\tCFG_OIS_CONTROL,\n\tCFG_OIS_I2C_WRITE_SEQ_TABLE,\n};\n\nenum msm_ois_i2c_operation {\n\tMSM_OIS_WRITE = 0,\n\tMSM_OIS_POLL,\n};\n\nstruct reg_settings_ois_t {\n\tuint16_t reg_addr;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tuint32_t reg_data;\n\tenum msm_camera_i2c_data_type data_type;\n\tenum msm_ois_i2c_operation i2c_operation;\n\tuint32_t delay;\n#define OIS_REG_DATA_SEQ_MAX 128\n    unsigned char reg_data_seq[OIS_REG_DATA_SEQ_MAX];\n    uint32_t reg_data_seq_size;\n};\n\nstruct msm_ois_params_t {\n\tuint16_t data_size;\n\tuint16_t setting_size;\n\tuint32_t i2c_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tenum msm_camera_i2c_reg_addr_type i2c_addr_type;\n\tenum msm_camera_i2c_data_type i2c_data_type;\n\tstruct reg_settings_ois_t *settings;\n};\n\nstruct msm_ois_set_info_t {\n\tstruct msm_ois_params_t ois_params;\n};\n\nstruct msm_actuator_move_params_t {\n\tint8_t dir;\n\tint8_t sign_dir;\n\tint16_t dest_step_pos;\n\tint32_t num_steps;\n\tuint16_t curr_lens_pos;\n\tstruct damping_params_t *ringing_params;\n};\n\nstruct msm_actuator_tuning_params_t {\n\tint16_t initial_code;\n\tuint16_t pwd_step;\n\tuint16_t region_size;\n\tuint32_t total_steps;\n\tstruct region_params_t *region_params;\n};\n\nstruct park_lens_data_t {\n\tuint32_t damping_step;\n\tuint32_t damping_delay;\n\tuint32_t hw_params;\n\tuint32_t max_step;\n};\n\nstruct msm_actuator_params_t {\n\tenum actuator_type act_type;\n\tuint8_t reg_tbl_size;\n\tuint16_t data_size;\n\tuint16_t init_setting_size;\n\tuint32_t i2c_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tenum msm_actuator_addr_type i2c_addr_type;\n\tenum msm_actuator_data_type i2c_data_type;\n\tstruct msm_actuator_reg_params_t *reg_tbl_params;\n\tstruct reg_settings_t *init_settings;\n\tstruct park_lens_data_t park_lens;\n};\n\nstruct msm_actuator_set_info_t {\n\tstruct msm_actuator_params_t actuator_params;\n\tstruct msm_actuator_tuning_params_t af_tuning_params;\n};\n\nstruct msm_actuator_get_info_t {\n\tuint32_t focal_length_num;\n\tuint32_t focal_length_den;\n\tuint32_t f_number_num;\n\tuint32_t f_number_den;\n\tuint32_t f_pix_num;\n\tuint32_t f_pix_den;\n\tuint32_t total_f_dist_num;\n\tuint32_t total_f_dist_den;\n\tuint32_t hor_view_angle_num;\n\tuint32_t hor_view_angle_den;\n\tuint32_t ver_view_angle_num;\n\tuint32_t ver_view_angle_den;\n};\n\nenum af_camera_name {\n\tACTUATOR_MAIN_CAM_0,\n\tACTUATOR_MAIN_CAM_1,\n\tACTUATOR_MAIN_CAM_2,\n\tACTUATOR_MAIN_CAM_3,\n\tACTUATOR_MAIN_CAM_4,\n\tACTUATOR_MAIN_CAM_5,\n\tACTUATOR_WEB_CAM_0,\n\tACTUATOR_WEB_CAM_1,\n\tACTUATOR_WEB_CAM_2,\n};\n\nstruct msm_ois_cfg_data {\n\tint cfgtype;\n\tunion {\n\t\tstruct msm_ois_set_info_t set_info;\n\t\tstruct msm_camera_i2c_seq_reg_setting *settings;\n\t} cfg;\n};\n\nstruct msm_actuator_set_position_t {\n\tuint16_t number_of_steps;\n\tuint32_t hw_params;\n\tuint16_t pos[MAX_NUMBER_OF_STEPS];\n\tuint16_t delay[MAX_NUMBER_OF_STEPS];\n};\n\nstruct msm_actuator_cfg_data {\n\tint cfgtype;\n\tuint8_t is_af_supported;\n\tunion {\n\t\tstruct msm_actuator_move_params_t move;\n\t\tstruct msm_actuator_set_info_t set_info;\n\t\tstruct msm_actuator_get_info_t get_info;\n\t\tstruct msm_actuator_set_position_t setpos;\n\t\tenum af_camera_name cam_name;\n\t} cfg;\n};\n\nenum msm_camera_led_config_t {\n\tMSM_CAMERA_LED_OFF,\n\tMSM_CAMERA_LED_LOW,\n\tMSM_CAMERA_LED_HIGH,\n\tMSM_CAMERA_LED_INIT,\n\tMSM_CAMERA_LED_RELEASE,\n};\n\nstruct msm_camera_led_cfg_t {\n\tenum msm_camera_led_config_t cfgtype;\n\tint32_t torch_current[MAX_LED_TRIGGERS];\n\tint32_t flash_current[MAX_LED_TRIGGERS];\n\tint32_t flash_duration[MAX_LED_TRIGGERS];\n};\n\nstruct msm_flash_init_info_t {\n\tenum msm_flash_driver_type flash_driver_type;\n\tuint32_t slave_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tstruct msm_sensor_power_setting_array *power_setting_array;\n\tstruct msm_camera_i2c_reg_setting_array *settings;\n};\n\nstruct msm_flash_cfg_data_t {\n\tenum msm_flash_cfg_type_t cfg_type;\n\tint32_t flash_current[MAX_LED_TRIGGERS];\n\tint32_t flash_duration[MAX_LED_TRIGGERS];\n\tunion {\n\t\tstruct msm_flash_init_info_t *flash_init_info;\n\t\tstruct msm_camera_i2c_reg_setting_array *settings;\n\t} cfg;\n};\n\n/* sensor init structures and enums */\nenum msm_sensor_init_cfg_type_t {\n\tCFG_SINIT_PROBE,\n\tCFG_SINIT_PROBE_DONE,\n\tCFG_SINIT_PROBE_WAIT_DONE,\n};\n\nstruct sensor_init_cfg_data {\n\tenum msm_sensor_init_cfg_type_t cfgtype;\n\tstruct msm_sensor_info_t        probed_info;\n\tchar                            entity_name[MAX_SENSOR_NAME];\n\tunion {\n\t\tvoid *setting;\n\t} cfg;\n};\n\n#define VIDIOC_MSM_SENSOR_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data)\n\n#define VIDIOC_MSM_SENSOR_RELEASE \\\n\t_IO('V', BASE_VIDIOC_PRIVATE + 2)\n\n#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t)\n\n#define VIDIOC_MSM_CSIPHY_IO_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data)\n\n#define VIDIOC_MSM_CSID_IO_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data)\n\n#define VIDIOC_MSM_ACTUATOR_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data)\n\n#define VIDIOC_MSM_FLASH_LED_DATA_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t)\n\n#define VIDIOC_MSM_EEPROM_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data)\n\n#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t)\n\n#define VIDIOC_MSM_SENSOR_INIT_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data)\n\n#define VIDIOC_MSM_OIS_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data)\n\n#define VIDIOC_MSM_FLASH_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t)\n\n#ifdef CONFIG_COMPAT\nstruct msm_camera_i2c_reg_setting32 {\n\tcompat_uptr_t reg_setting;\n\tuint16_t size;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tenum msm_camera_i2c_data_type data_type;\n\tuint16_t delay;\n};\n\nstruct msm_camera_i2c_array_write_config32 {\n\tstruct msm_camera_i2c_reg_setting32 conf_array;\n\tuint16_t slave_addr;\n};\n\nstruct msm_actuator_tuning_params_t32 {\n\tint16_t initial_code;\n\tuint16_t pwd_step;\n\tuint16_t region_size;\n\tuint32_t total_steps;\n\tcompat_uptr_t region_params;\n};\n\nstruct msm_actuator_params_t32 {\n\tenum actuator_type act_type;\n\tuint8_t reg_tbl_size;\n\tuint16_t data_size;\n\tuint16_t init_setting_size;\n\tuint32_t i2c_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tenum msm_actuator_addr_type i2c_addr_type;\n\tenum msm_actuator_data_type i2c_data_type;\n\tcompat_uptr_t reg_tbl_params;\n\tcompat_uptr_t init_settings;\n\tstruct park_lens_data_t park_lens;\n};\n\nstruct msm_actuator_set_info_t32 {\n\tstruct msm_actuator_params_t32 actuator_params;\n\tstruct msm_actuator_tuning_params_t32 af_tuning_params;\n};\n\nstruct sensor_init_cfg_data32 {\n\tenum msm_sensor_init_cfg_type_t cfgtype;\n\tstruct msm_sensor_info_t        probed_info;\n\tchar                            entity_name[MAX_SENSOR_NAME];\n\tunion {\n\t\tcompat_uptr_t setting;\n\t} cfg;\n};\n\nstruct msm_actuator_move_params_t32 {\n\tint8_t dir;\n\tint8_t sign_dir;\n\tint16_t dest_step_pos;\n\tint32_t num_steps;\n\tuint16_t curr_lens_pos;\n\tcompat_uptr_t ringing_params;\n};\n\nstruct msm_actuator_cfg_data32 {\n\tint cfgtype;\n\tuint8_t is_af_supported;\n\tunion {\n\t\tstruct msm_actuator_move_params_t32 move;\n\t\tstruct msm_actuator_set_info_t32 set_info;\n\t\tstruct msm_actuator_get_info_t get_info;\n\t\tstruct msm_actuator_set_position_t setpos;\n\t\tenum af_camera_name cam_name;\n\t} cfg;\n};\n\nstruct csiphy_cfg_data32 {\n\tenum csiphy_cfg_type_t cfgtype;\n\tunion {\n\t\tcompat_uptr_t csiphy_params;\n\t\tcompat_uptr_t csi_lane_params;\n\t} cfg;\n};\n\nstruct sensorb_cfg_data32 {\n\tint cfgtype;\n\tunion {\n\t\tstruct msm_sensor_info_t      sensor_info;\n\t\tstruct msm_sensor_init_params sensor_init_params;\n\t\tcompat_uptr_t                 setting;\n\t\tstruct msm_sensor_i2c_sync_params sensor_i2c_sync_params;\n\t} cfg;\n};\n\nstruct msm_ois_params_t32 {\n\tuint16_t data_size;\n\tuint16_t setting_size;\n\tuint32_t i2c_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tenum msm_camera_i2c_reg_addr_type i2c_addr_type;\n\tenum msm_camera_i2c_data_type i2c_data_type;\n\tcompat_uptr_t settings;\n};\n\nstruct msm_ois_set_info_t32 {\n\tstruct msm_ois_params_t32 ois_params;\n};\n\nstruct msm_ois_cfg_data32 {\n\tint cfgtype;\n\tunion {\n\t\tstruct msm_ois_set_info_t32 set_info;\n\t\tcompat_uptr_t settings;\n\t} cfg;\n};\n\nstruct msm_flash_init_info_t32 {\n\tenum msm_flash_driver_type flash_driver_type;\n\tuint32_t slave_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tcompat_uptr_t power_setting_array;\n\tcompat_uptr_t settings;\n};\n\nstruct msm_flash_cfg_data_t32 {\n\tenum msm_flash_cfg_type_t cfg_type;\n\tint32_t flash_current[MAX_LED_TRIGGERS];\n\tint32_t flash_duration[MAX_LED_TRIGGERS];\n\tunion {\n\t\tcompat_uptr_t flash_init_info;\n\t\tcompat_uptr_t settings;\n\t} cfg;\n};\n\n#define VIDIOC_MSM_ACTUATOR_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data32)\n\n#define VIDIOC_MSM_SENSOR_INIT_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data32)\n\n#define VIDIOC_MSM_CSIPHY_IO_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data32)\n\n#define VIDIOC_MSM_SENSOR_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data32)\n\n#define VIDIOC_MSM_EEPROM_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data32)\n\n#define VIDIOC_MSM_OIS_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data32)\n\n#define VIDIOC_MSM_CSID_IO_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data32)\n\n#define VIDIOC_MSM_FLASH_CFG32 \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t32)\n#endif\n\n#endif /* __LINUX_MSM_CAM_SENSOR_H */\n"
  },
  {
    "path": "selfdrive/camerad/include/msm_camsensor_sdk.h",
    "content": "#ifndef __LINUX_MSM_CAMSENSOR_SDK_H\n#define __LINUX_MSM_CAMSENSOR_SDK_H\n\n#define KVERSION 0x1\n\n#define MAX_POWER_CONFIG      12\n#define GPIO_OUT_LOW          (0 << 1)\n#define GPIO_OUT_HIGH         (1 << 1)\n#define CSI_EMBED_DATA        0x12\n#define CSI_RESERVED_DATA_0   0x13\n#define CSI_YUV422_8          0x1E\n#define CSI_RAW8              0x2A\n#define CSI_RAW10             0x2B\n#define CSI_RAW12             0x2C\n#define CSI_DECODE_6BIT         0\n#define CSI_DECODE_8BIT         1\n#define CSI_DECODE_10BIT        2\n#define CSI_DECODE_12BIT        3\n#define CSI_DECODE_DPCM_10_8_10 5\n#define MAX_CID                 16\n#define I2C_SEQ_REG_DATA_MAX    1024\n#define I2C_REG_DATA_MAX       (8*1024)\n\n#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */\n#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')\n\t/* 14  BGBG.. GRGR.. */\n#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')\n\t/* 14  GBGB.. RGRG.. */\n#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')\n\t/* 14  GRGR.. BGBG.. */\n#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')\n\t/* 14  RGRG.. GBGB.. */\n\n#define MAX_ACTUATOR_REG_TBL_SIZE 8\n#define MAX_ACTUATOR_REGION       5\n#define NUM_ACTUATOR_DIR          2\n#define MAX_ACTUATOR_SCENARIO     8\n#define MAX_ACT_MOD_NAME_SIZE     32\n#define MAX_ACT_NAME_SIZE         32\n#define MAX_ACTUATOR_INIT_SET     120\n#define MAX_I2C_REG_SET           12\n\n#define MAX_LED_TRIGGERS          3\n\n#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE  80\n#define MSM_EEPROM_MAX_MEM_MAP_CNT      8\n\nenum msm_sensor_camera_id_t {\n\tCAMERA_0,\n\tCAMERA_1,\n\tCAMERA_2,\n\tCAMERA_3,\n\tMAX_CAMERAS,\n};\n\nenum i2c_freq_mode_t {\n\tI2C_STANDARD_MODE,\n\tI2C_FAST_MODE,\n\tI2C_CUSTOM_MODE,\n\tI2C_FAST_PLUS_MODE,\n\tI2C_MAX_MODES,\n};\n\nenum camb_position_t {\n\tBACK_CAMERA_B,\n\tFRONT_CAMERA_B,\n\tAUX_CAMERA_B = 0x100,\n\tINVALID_CAMERA_B,\n};\n\nenum msm_sensor_power_seq_type_t {\n\tSENSOR_CLK,\n\tSENSOR_GPIO,\n\tSENSOR_VREG,\n\tSENSOR_I2C_MUX,\n\tSENSOR_I2C,\n};\n\nenum msm_camera_i2c_reg_addr_type {\n\tMSM_CAMERA_I2C_BYTE_ADDR = 1,\n\tMSM_CAMERA_I2C_WORD_ADDR,\n\tMSM_CAMERA_I2C_3B_ADDR,\n\tMSM_CAMERA_I2C_ADDR_TYPE_MAX,\n};\n\nenum msm_camera_i2c_data_type {\n\tMSM_CAMERA_I2C_BYTE_DATA = 1,\n\tMSM_CAMERA_I2C_WORD_DATA,\n\tMSM_CAMERA_I2C_DWORD_DATA,\n\tMSM_CAMERA_I2C_SET_BYTE_MASK,\n\tMSM_CAMERA_I2C_UNSET_BYTE_MASK,\n\tMSM_CAMERA_I2C_SET_WORD_MASK,\n\tMSM_CAMERA_I2C_UNSET_WORD_MASK,\n\tMSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,\n\tMSM_CAMERA_I2C_SEQ_DATA,\n\tMSM_CAMERA_I2C_DATA_TYPE_MAX,\n};\n\nenum msm_sensor_power_seq_gpio_t {\n\tSENSOR_GPIO_RESET,\n\tSENSOR_GPIO_STANDBY,\n\tSENSOR_GPIO_AF_PWDM,\n\tSENSOR_GPIO_VIO,\n\tSENSOR_GPIO_VANA,\n\tSENSOR_GPIO_VDIG,\n\tSENSOR_GPIO_VAF,\n\tSENSOR_GPIO_FL_EN,\n\tSENSOR_GPIO_FL_NOW,\n\tSENSOR_GPIO_FL_RESET,\n\tSENSOR_GPIO_CUSTOM1,\n\tSENSOR_GPIO_CUSTOM2,\n\tSENSOR_GPIO_MAX,\n};\n\nenum msm_camera_vreg_name_t {\n\tCAM_VDIG,\n\tCAM_VIO,\n\tCAM_VANA,\n\tCAM_VAF,\n\tCAM_V_CUSTOM1,\n\tCAM_V_CUSTOM2,\n\tCAM_VREG_MAX,\n};\n\nenum msm_sensor_clk_type_t {\n\tSENSOR_CAM_MCLK,\n\tSENSOR_CAM_CLK,\n\tSENSOR_CAM_CLK_MAX,\n};\n\nenum camerab_mode_t {\n\tCAMERA_MODE_2D_B = (1<<0),\n\tCAMERA_MODE_3D_B = (1<<1),\n\tCAMERA_MODE_INVALID = (1<<2),\n};\n\nenum msm_actuator_data_type {\n\tMSM_ACTUATOR_BYTE_DATA = 1,\n\tMSM_ACTUATOR_WORD_DATA,\n};\n\nenum msm_actuator_addr_type {\n\tMSM_ACTUATOR_BYTE_ADDR = 1,\n\tMSM_ACTUATOR_WORD_ADDR,\n};\n\nenum msm_actuator_write_type {\n\tMSM_ACTUATOR_WRITE_HW_DAMP,\n\tMSM_ACTUATOR_WRITE_DAC,\n\tMSM_ACTUATOR_WRITE,\n\tMSM_ACTUATOR_WRITE_DIR_REG,\n\tMSM_ACTUATOR_POLL,\n\tMSM_ACTUATOR_READ_WRITE,\n};\n\nenum msm_actuator_i2c_operation {\n\tMSM_ACT_WRITE = 0,\n\tMSM_ACT_POLL,\n};\n\nenum actuator_type {\n\tACTUATOR_VCM,\n\tACTUATOR_PIEZO,\n\tACTUATOR_HVCM,\n\tACTUATOR_BIVCM,\n};\n\nenum msm_flash_driver_type {\n\tFLASH_DRIVER_PMIC,\n\tFLASH_DRIVER_I2C,\n\tFLASH_DRIVER_GPIO,\n\tFLASH_DRIVER_DEFAULT\n};\n\nenum msm_flash_cfg_type_t {\n\tCFG_FLASH_INIT,\n\tCFG_FLASH_RELEASE,\n\tCFG_FLASH_OFF,\n\tCFG_FLASH_LOW,\n\tCFG_FLASH_HIGH,\n};\n\nenum msm_sensor_output_format_t {\n\tMSM_SENSOR_BAYER,\n\tMSM_SENSOR_YCBCR,\n\tMSM_SENSOR_META,\n};\n\nstruct msm_sensor_power_setting {\n\tenum msm_sensor_power_seq_type_t seq_type;\n\tunsigned short seq_val;\n\tlong config_val;\n\tunsigned short delay;\n\tvoid *data[10];\n};\n\nstruct msm_sensor_power_setting_array {\n\tstruct msm_sensor_power_setting  power_setting_a[MAX_POWER_CONFIG];\n\tstruct msm_sensor_power_setting *power_setting;\n\tunsigned short size;\n\tstruct msm_sensor_power_setting  power_down_setting_a[MAX_POWER_CONFIG];\n\tstruct msm_sensor_power_setting *power_down_setting;\n\tunsigned short size_down;\n};\n\nenum msm_camera_i2c_operation {\n\tMSM_CAM_WRITE = 0,\n\tMSM_CAM_POLL,\n\tMSM_CAM_READ,\n};\n\nstruct msm_sensor_i2c_sync_params {\n\tunsigned int cid;\n\tint csid;\n\tunsigned short line;\n\tunsigned short delay;\n};\n\nstruct msm_camera_reg_settings_t {\n\tuint16_t reg_addr;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tuint16_t reg_data;\n\tenum msm_camera_i2c_data_type data_type;\n\tenum msm_camera_i2c_operation i2c_operation;\n\tuint16_t delay;\n};\n\nstruct msm_eeprom_mem_map_t {\n\tint slave_addr;\n\tstruct msm_camera_reg_settings_t\n\t\tmem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE];\n\tint memory_map_size;\n};\n\nstruct msm_eeprom_memory_map_array {\n\tstruct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT];\n\tuint32_t msm_size_of_max_mappings;\n};\n\nstruct msm_sensor_init_params {\n\t/* mask of modes supported: 2D, 3D */\n\tint                 modes_supported;\n\t/* sensor position: front, back */\n\tenum camb_position_t position;\n\t/* sensor mount angle */\n\tunsigned int            sensor_mount_angle;\n};\n\nstruct msm_sensor_id_info_t {\n\tunsigned short sensor_id_reg_addr;\n\tunsigned short sensor_id;\n\tunsigned short sensor_id_mask;\n  // added in LeEco\n  unsigned char module_id;\n  unsigned char vcm_id;\n};\n\nstruct msm_camera_sensor_slave_info {\n\tchar sensor_name[32];\n\tchar eeprom_name[32];\n\tchar actuator_name[32];\n\tchar ois_name[32];\n\tchar flash_name[32];\n\tenum msm_sensor_camera_id_t camera_id;\n\tunsigned short slave_addr;\n\tenum i2c_freq_mode_t i2c_freq_mode;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tstruct msm_sensor_id_info_t sensor_id_info;\n\tstruct msm_sensor_power_setting_array power_setting_array;\n\tunsigned char  is_init_params_valid;\n\tstruct msm_sensor_init_params sensor_init_params;\n\tenum msm_sensor_output_format_t output_format;\n};\n\nstruct msm_camera_i2c_reg_array {\n\tunsigned short reg_addr;\n\tunsigned short reg_data;\n\tunsigned int delay;\n};\n\nstruct msm_camera_i2c_reg_setting {\n\tstruct msm_camera_i2c_reg_array *reg_setting;\n\tunsigned short size;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tenum msm_camera_i2c_data_type data_type;\n\tunsigned short delay;\n};\n\nstruct msm_camera_csid_vc_cfg {\n\tunsigned char cid;\n\tunsigned char dt;\n\tunsigned char decode_format;\n};\n\nstruct msm_camera_csid_lut_params {\n\tunsigned char num_cid;\n\tstruct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];\n\tstruct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID];\n};\n\nstruct msm_camera_csid_params {\n\tunsigned char lane_cnt;\n\tunsigned short lane_assign;\n\tunsigned char phy_sel;\n\tunsigned int csi_clk;\n\tstruct msm_camera_csid_lut_params lut_params;\n\tunsigned char csi_3p_sel;\n};\n\nstruct msm_camera_csid_testmode_parms {\n\tunsigned int num_bytes_per_line;\n\tunsigned int num_lines;\n\tunsigned int h_blanking_count;\n\tunsigned int v_blanking_count;\n\tunsigned int payload_mode;\n};\n\nstruct msm_camera_csiphy_params {\n\tunsigned char lane_cnt;\n\tunsigned char settle_cnt;\n\tunsigned short lane_mask;\n\tunsigned char combo_mode;\n\tunsigned char csid_core;\n\tunsigned int csiphy_clk;\n\tunsigned char csi_3phase;\n};\n\nstruct msm_camera_i2c_seq_reg_array {\n\tunsigned short reg_addr;\n\tunsigned char reg_data[I2C_SEQ_REG_DATA_MAX];\n\tunsigned short reg_data_size;\n};\n\nstruct msm_camera_i2c_seq_reg_setting {\n\tstruct msm_camera_i2c_seq_reg_array *reg_setting;\n\tunsigned short size;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tunsigned short delay;\n};\n\nstruct msm_actuator_reg_params_t {\n\tenum msm_actuator_write_type reg_write_type;\n\tunsigned int hw_mask;\n\tunsigned short reg_addr;\n\tunsigned short hw_shift;\n\tunsigned short data_shift;\n\tunsigned short data_type;\n\tunsigned short addr_type;\n\tunsigned short reg_data;\n\tunsigned short delay;\n};\n\n\nstruct damping_params_t {\n\tunsigned int damping_step;\n\tunsigned int damping_delay;\n\tunsigned int hw_params;\n};\n\nstruct region_params_t {\n\t/* [0] = ForwardDirection Macro boundary\n\t   [1] = ReverseDirection Inf boundary\n\t*/\n\tunsigned short step_bound[2];\n\tunsigned short code_per_step;\n\t/* qvalue for converting float type numbers to integer format */\n\tunsigned int qvalue;\n};\n\nstruct reg_settings_t {\n\tunsigned short reg_addr;\n\tenum msm_actuator_addr_type addr_type;\n\tunsigned short reg_data;\n\tenum msm_actuator_data_type data_type;\n\tenum msm_actuator_i2c_operation i2c_operation;\n\tunsigned int delay;\n};\n\nstruct msm_camera_i2c_reg_setting_array {\n\tstruct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET];\n\tunsigned short size;\n\tenum msm_camera_i2c_reg_addr_type addr_type;\n\tenum msm_camera_i2c_data_type data_type;\n\tunsigned short delay;\n};\n#endif /* __LINUX_MSM_CAM_SENSOR_H */\n"
  },
  {
    "path": "selfdrive/camerad/include/msmb_camera.h",
    "content": "#ifndef __LINUX_MSMB_CAMERA_H\n#define __LINUX_MSMB_CAMERA_H\n\n#include <linux/videodev2.h>\n#include <linux/types.h>\n#include <linux/ioctl.h>\n\n#define MSM_CAM_LOGSYNC_FILE_NAME \"logsync\"\n#define MSM_CAM_LOGSYNC_FILE_BASEDIR \"camera\"\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data)\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data)\n\n#define MSM_CAM_V4L2_IOCTL_CMD_ACK \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data)\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data)\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data)\n\n#ifdef CONFIG_COMPAT\n#define MSM_CAM_V4L2_IOCTL_NOTIFY32 \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 30, struct v4l2_event32)\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY_META32 \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 31, struct v4l2_event32)\n\n#define MSM_CAM_V4L2_IOCTL_CMD_ACK32 \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 32, struct v4l2_event32)\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR32 \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 33, struct v4l2_event32)\n\n#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG32 \\\n\t_IOW('V', BASE_VIDIOC_PRIVATE + 34, struct v4l2_event32)\n\n#endif\n\n#define QCAMERA_DEVICE_GROUP_ID\t1\n#define QCAMERA_VNODE_GROUP_ID\t2\n#define MSM_CAMERA_NAME\t\t\t\t\t\"msm_camera\"\n#define MSM_CONFIGURATION_NAME\t\"msm_config\"\n\n#define MSM_CAMERA_SUBDEV_CSIPHY       0\n#define MSM_CAMERA_SUBDEV_CSID         1\n#define MSM_CAMERA_SUBDEV_ISPIF        2\n#define MSM_CAMERA_SUBDEV_VFE          3\n#define MSM_CAMERA_SUBDEV_AXI          4\n#define MSM_CAMERA_SUBDEV_VPE          5\n#define MSM_CAMERA_SUBDEV_SENSOR       6\n#define MSM_CAMERA_SUBDEV_ACTUATOR     7\n#define MSM_CAMERA_SUBDEV_EEPROM       8\n#define MSM_CAMERA_SUBDEV_CPP          9\n#define MSM_CAMERA_SUBDEV_CCI          10\n#define MSM_CAMERA_SUBDEV_LED_FLASH    11\n#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12\n#define MSM_CAMERA_SUBDEV_BUF_MNGR     13\n#define MSM_CAMERA_SUBDEV_SENSOR_INIT  14\n#define MSM_CAMERA_SUBDEV_OIS          15\n#define MSM_CAMERA_SUBDEV_FLASH        16\n#define MSM_CAMERA_SUBDEV_EXT          17\n\n#define MSM_MAX_CAMERA_SENSORS  5\n\n/* The below macro is defined to put an upper limit on maximum\n * number of buffer requested per stream. In case of extremely\n * large value for number of buffer due to data structure corruption\n * we return error to avoid integer overflow. Group processing\n * can have max of 9 groups of 8 bufs each. This value may be\n * configured in future*/\n#define MSM_CAMERA_MAX_STREAM_BUF 72\n\n/* Max batch size of processing */\n#define MSM_CAMERA_MAX_USER_BUFF_CNT 16\n\n/* featur base */\n#define MSM_CAMERA_FEATURE_BASE     0x00010000\n#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1)\n\n#define MSM_CAMERA_STATUS_BASE      0x00020000\n#define MSM_CAMERA_STATUS_FAIL      (MSM_CAMERA_STATUS_BASE + 1)\n#define MSM_CAMERA_STATUS_SUCCESS   (MSM_CAMERA_STATUS_BASE + 2)\n\n/* event type */\n#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000)\n\n/* event id */\n#define MSM_CAMERA_EVENT_MIN    0\n#define MSM_CAMERA_NEW_SESSION  (MSM_CAMERA_EVENT_MIN + 1)\n#define MSM_CAMERA_DEL_SESSION  (MSM_CAMERA_EVENT_MIN + 2)\n#define MSM_CAMERA_SET_PARM     (MSM_CAMERA_EVENT_MIN + 3)\n#define MSM_CAMERA_GET_PARM     (MSM_CAMERA_EVENT_MIN + 4)\n#define MSM_CAMERA_MAPPING_CFG  (MSM_CAMERA_EVENT_MIN + 5)\n#define MSM_CAMERA_MAPPING_SES  (MSM_CAMERA_EVENT_MIN + 6)\n#define MSM_CAMERA_MSM_NOTIFY   (MSM_CAMERA_EVENT_MIN + 7)\n#define MSM_CAMERA_EVENT_MAX    (MSM_CAMERA_EVENT_MIN + 8)\n\n/* data.command */\n#define MSM_CAMERA_PRIV_S_CROP\t\t (V4L2_CID_PRIVATE_BASE + 1)\n#define MSM_CAMERA_PRIV_G_CROP\t\t (V4L2_CID_PRIVATE_BASE + 2)\n#define MSM_CAMERA_PRIV_G_FMT\t\t\t (V4L2_CID_PRIVATE_BASE + 3)\n#define MSM_CAMERA_PRIV_S_FMT\t\t\t (V4L2_CID_PRIVATE_BASE + 4)\n#define MSM_CAMERA_PRIV_TRY_FMT\t\t (V4L2_CID_PRIVATE_BASE + 5)\n#define MSM_CAMERA_PRIV_METADATA\t (V4L2_CID_PRIVATE_BASE + 6)\n#define MSM_CAMERA_PRIV_QUERY_CAP  (V4L2_CID_PRIVATE_BASE + 7)\n#define MSM_CAMERA_PRIV_STREAM_ON  (V4L2_CID_PRIVATE_BASE + 8)\n#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9)\n#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10)\n#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11)\n#define MSM_CAMERA_PRIV_SHUTDOWN   (V4L2_CID_PRIVATE_BASE + 12)\n#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \\\n\t(V4L2_CID_PRIVATE_BASE + 13)\n#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14)\n#define MSM_CAMERA_PRIV_CMD_MAX  20\n\n/* data.status - success */\n#define MSM_CAMERA_CMD_SUCESS      0x00000001\n#define MSM_CAMERA_BUF_MAP_SUCESS  0x00000002\n\n/* data.status - error */\n#define MSM_CAMERA_ERR_EVT_BASE 0x00010000\n#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1)\n#define MSM_CAMERA_ERR_MAPPING  (MSM_CAMERA_ERR_EVT_BASE + 2)\n#define MSM_CAMERA_ERR_DEVICE_BUSY  (MSM_CAMERA_ERR_EVT_BASE + 3)\n\n/* The msm_v4l2_event_data structure should match the\n * v4l2_event.u.data field.\n * should not exceed 16 elements */\nstruct msm_v4l2_event_data {\n\t/*word 0*/\n\tunsigned int command;\n\t/*word 1*/\n\tunsigned int status;\n\t/*word 2*/\n\tunsigned int session_id;\n\t/*word 3*/\n\tunsigned int stream_id;\n\t/*word 4*/\n\tunsigned int map_op;\n\t/*word 5*/\n\tunsigned int map_buf_idx;\n\t/*word 6*/\n\tunsigned int notify;\n\t/*word 7*/\n\tunsigned int arg_value;\n\t/*word 8*/\n\tunsigned int ret_value;\n\t/*word 9*/\n\tunsigned int v4l2_event_type;\n\t/*word 10*/\n\tunsigned int v4l2_event_id;\n\t/*word 11*/\n\tunsigned int handle;\n\t/*word 12*/\n\tunsigned int nop6;\n\t/*word 13*/\n\tunsigned int nop7;\n\t/*word 14*/\n\tunsigned int nop8;\n\t/*word 15*/\n\tunsigned int nop9;\n};\n\n/* map to v4l2_format.fmt.raw_data */\nstruct msm_v4l2_format_data {\n\tenum v4l2_buf_type type;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int pixelformat; /* FOURCC */\n\tunsigned char num_planes;\n\tunsigned int plane_sizes[VIDEO_MAX_PLANES];\n};\n\n/*  MSM Four-character-code (FOURCC) */\n#define msm_v4l2_fourcc(a, b, c, d)\\\n\t((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\\\n\t((__u32)(d) << 24))\n\n/* Composite stats */\n#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M')\n/* AEC stats */\n#define MSM_V4L2_PIX_FMT_STATS_AE   v4l2_fourcc('S', 'T', 'A', 'E')\n/* AF stats */\n#define MSM_V4L2_PIX_FMT_STATS_AF   v4l2_fourcc('S', 'T', 'A', 'F')\n/* AWB stats */\n#define MSM_V4L2_PIX_FMT_STATS_AWB  v4l2_fourcc('S', 'T', 'W', 'B')\n/* IHIST stats */\n#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T')\n/* Column count stats */\n#define MSM_V4L2_PIX_FMT_STATS_CS   v4l2_fourcc('S', 'T', 'C', 'S')\n/* Row count stats */\n#define MSM_V4L2_PIX_FMT_STATS_RS   v4l2_fourcc('S', 'T', 'R', 'S')\n/* Bayer Grid stats */\n#define MSM_V4L2_PIX_FMT_STATS_BG   v4l2_fourcc('S', 'T', 'B', 'G')\n/* Bayer focus stats */\n#define MSM_V4L2_PIX_FMT_STATS_BF   v4l2_fourcc('S', 'T', 'B', 'F')\n/* Bayer hist stats */\n#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T')\n\nenum smmu_attach_mode {\n\tNON_SECURE_MODE = 0x01,\n\tSECURE_MODE = 0x02,\n\tMAX_PROTECTION_MODE = 0x03,\n};\n\nstruct msm_camera_smmu_attach_type {\n\tenum smmu_attach_mode attach;\n};\n\nstruct msm_camera_user_buf_cont_t {\n\tunsigned int buf_cnt;\n\tunsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT];\n};\n\n#endif /* __LINUX_MSMB_CAMERA_H */\n"
  },
  {
    "path": "selfdrive/camerad/include/msmb_isp.h",
    "content": "#ifndef __MSMB_ISP__\n#define __MSMB_ISP__\n\n#include <linux/videodev2.h>\n\n#define MAX_PLANES_PER_STREAM 3\n#define MAX_NUM_STREAM 7\n\n#define ISP_VERSION_47        47\n#define ISP_VERSION_46        46\n#define ISP_VERSION_44        44\n#define ISP_VERSION_40        40\n#define ISP_VERSION_32        32\n#define ISP_NATIVE_BUF_BIT    (0x10000 << 0)\n#define ISP0_BIT              (0x10000 << 1)\n#define ISP1_BIT              (0x10000 << 2)\n#define ISP_META_CHANNEL_BIT  (0x10000 << 3)\n#define ISP_SCRATCH_BUF_BIT   (0x10000 << 4)\n#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)\n#define ISP_STATS_STREAM_BIT  0x80000000\n\nstruct msm_vfe_cfg_cmd_list;\n\nenum ISP_START_PIXEL_PATTERN {\n\tISP_BAYER_RGRGRG,\n\tISP_BAYER_GRGRGR,\n\tISP_BAYER_BGBGBG,\n\tISP_BAYER_GBGBGB,\n\tISP_YUV_YCbYCr,\n\tISP_YUV_YCrYCb,\n\tISP_YUV_CbYCrY,\n\tISP_YUV_CrYCbY,\n\tISP_PIX_PATTERN_MAX\n};\n\nenum msm_vfe_plane_fmt {\n\tY_PLANE,\n\tCB_PLANE,\n\tCR_PLANE,\n\tCRCB_PLANE,\n\tCBCR_PLANE,\n\tVFE_PLANE_FMT_MAX\n};\n\nenum msm_vfe_input_src {\n\tVFE_PIX_0,\n\tVFE_RAW_0,\n\tVFE_RAW_1,\n\tVFE_RAW_2,\n\tVFE_SRC_MAX,\n};\n\nenum msm_vfe_axi_stream_src {\n\tPIX_ENCODER,\n\tPIX_VIEWFINDER,\n\tPIX_VIDEO,\n\tCAMIF_RAW,\n\tIDEAL_RAW,\n\tRDI_INTF_0,\n\tRDI_INTF_1,\n\tRDI_INTF_2,\n\tVFE_AXI_SRC_MAX\n};\n\nenum msm_vfe_frame_skip_pattern {\n\tNO_SKIP,\n\tEVERY_2FRAME,\n\tEVERY_3FRAME,\n\tEVERY_4FRAME,\n\tEVERY_5FRAME,\n\tEVERY_6FRAME,\n\tEVERY_7FRAME,\n\tEVERY_8FRAME,\n\tEVERY_16FRAME,\n\tEVERY_32FRAME,\n\tSKIP_ALL,\n\tSKIP_RANGE,\n\tMAX_SKIP,\n};\n\n/*\n * Define an unused period. When this period is set it means that the stream is\n * stopped(i.e the pattern is 0). We don't track the current pattern, just the\n * period defines what the pattern is, if period is this then pattern is 0 else\n * pattern is 1\n */\n#define MSM_VFE_STREAM_STOP_PERIOD 15\n\nenum msm_isp_stats_type {\n\tMSM_ISP_STATS_AEC,   /* legacy based AEC */\n\tMSM_ISP_STATS_AF,    /* legacy based AF */\n\tMSM_ISP_STATS_AWB,   /* legacy based AWB */\n\tMSM_ISP_STATS_RS,    /* legacy based RS */\n\tMSM_ISP_STATS_CS,    /* legacy based CS */\n\tMSM_ISP_STATS_IHIST, /* legacy based HIST */\n\tMSM_ISP_STATS_SKIN,  /* legacy based SKIN */\n\tMSM_ISP_STATS_BG,    /* Bayer Grids */\n\tMSM_ISP_STATS_BF,    /* Bayer Focus */\n\tMSM_ISP_STATS_BE,    /* Bayer Exposure*/\n\tMSM_ISP_STATS_BHIST, /* Bayer Hist */\n\tMSM_ISP_STATS_BF_SCALE,  /* Bayer Focus scale */\n\tMSM_ISP_STATS_HDR_BE,    /* HDR Bayer Exposure */\n\tMSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */\n\tMSM_ISP_STATS_AEC_BG,   /* AEC BG */\n\tMSM_ISP_STATS_MAX    /* MAX */\n};\n\n/*\n * @stats_type_mask: Stats type mask (enum msm_isp_stats_type).\n * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)\n * @skip_mode: skip pattern, if skip mode is range only then min/max is used\n * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)\n * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)\n*/\nstruct msm_isp_sw_framskip {\n\tuint32_t stats_type_mask;\n\tuint32_t stream_src_mask;\n\tenum msm_vfe_frame_skip_pattern skip_mode;\n\tuint32_t min_frame_id;\n\tuint32_t max_frame_id;\n};\n\nenum msm_vfe_testgen_color_pattern {\n\tCOLOR_BAR_8_COLOR,\n\tUNICOLOR_WHITE,\n\tUNICOLOR_YELLOW,\n\tUNICOLOR_CYAN,\n\tUNICOLOR_GREEN,\n\tUNICOLOR_MAGENTA,\n\tUNICOLOR_RED,\n\tUNICOLOR_BLUE,\n\tUNICOLOR_BLACK,\n\tMAX_COLOR,\n};\n\nenum msm_vfe_camif_input {\n\tCAMIF_DISABLED,\n\tCAMIF_PAD_REG_INPUT,\n\tCAMIF_MIDDI_INPUT,\n\tCAMIF_MIPI_INPUT,\n};\n\nstruct msm_vfe_fetch_engine_cfg {\n\tuint32_t input_format;\n\tuint32_t buf_width;\n\tuint32_t buf_height;\n\tuint32_t fetch_width;\n\tuint32_t fetch_height;\n\tuint32_t x_offset;\n\tuint32_t y_offset;\n\tuint32_t buf_stride;\n};\n\nenum msm_vfe_camif_output_format {\n\tCAMIF_QCOM_RAW,\n\tCAMIF_MIPI_RAW,\n\tCAMIF_PLAIN_8,\n\tCAMIF_PLAIN_16,\n\tCAMIF_MAX_FORMAT,\n};\n\n/*\n * Camif output general configuration\n */\nstruct msm_vfe_camif_subsample_cfg {\n\tuint32_t irq_subsample_period;\n\tuint32_t irq_subsample_pattern;\n\tuint32_t sof_counter_step;\n\tuint32_t pixel_skip;\n\tuint32_t line_skip;\n\tuint32_t first_line;\n\tuint32_t last_line;\n\tuint32_t first_pixel;\n\tuint32_t last_pixel;\n\tenum msm_vfe_camif_output_format output_format;\n};\n\n/*\n * Camif frame and window configuration\n */\nstruct msm_vfe_camif_cfg {\n\tuint32_t lines_per_frame;\n\tuint32_t pixels_per_line;\n\tuint32_t first_pixel;\n\tuint32_t last_pixel;\n\tuint32_t first_line;\n\tuint32_t last_line;\n\tuint32_t epoch_line0;\n\tuint32_t epoch_line1;\n\tuint32_t is_split;\n\tenum msm_vfe_camif_input camif_input;\n\tstruct msm_vfe_camif_subsample_cfg subsample_cfg;\n};\n\nstruct msm_vfe_testgen_cfg {\n\tuint32_t lines_per_frame;\n\tuint32_t pixels_per_line;\n\tuint32_t v_blank;\n\tuint32_t h_blank;\n\tenum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;\n\tuint32_t rotate_period;\n\tenum msm_vfe_testgen_color_pattern color_bar_pattern;\n\tuint32_t burst_num_frame;\n};\n\nenum msm_vfe_inputmux {\n\tCAMIF,\n\tTESTGEN,\n\tEXTERNAL_READ,\n};\n\nenum msm_vfe_stats_composite_group {\n\tSTATS_COMPOSITE_GRP_NONE,\n\tSTATS_COMPOSITE_GRP_1,\n\tSTATS_COMPOSITE_GRP_2,\n\tSTATS_COMPOSITE_GRP_MAX,\n};\n\nenum msm_vfe_hvx_streaming_cmd {\n\tHVX_DISABLE,\n\tHVX_ONE_WAY,\n\tHVX_ROUND_TRIP\n};\n\nstruct msm_vfe_pix_cfg {\n\tstruct msm_vfe_camif_cfg camif_cfg;\n\tstruct msm_vfe_testgen_cfg testgen_cfg;\n\tstruct msm_vfe_fetch_engine_cfg fetch_engine_cfg;\n\tenum msm_vfe_inputmux input_mux;\n\tenum ISP_START_PIXEL_PATTERN pixel_pattern;\n\tuint32_t input_format;\n\tenum msm_vfe_hvx_streaming_cmd hvx_cmd;\n\tuint32_t is_split;\n};\n\nstruct msm_vfe_rdi_cfg {\n\tuint8_t cid;\n\tuint8_t frame_based;\n};\n\nstruct msm_vfe_input_cfg {\n\tunion {\n\t\tstruct msm_vfe_pix_cfg pix_cfg;\n\t\tstruct msm_vfe_rdi_cfg rdi_cfg;\n\t} d;\n\tenum msm_vfe_input_src input_src;\n\tuint32_t input_pix_clk;\n};\n\nstruct msm_vfe_fetch_eng_start {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint32_t buf_idx;\n\tuint8_t  offline_mode;\n\tuint32_t fd;\n\tuint32_t buf_addr;\n\tuint32_t frame_id;\n};\n\nstruct msm_vfe_axi_plane_cfg {\n\tuint32_t output_width; /*Include padding*/\n\tuint32_t output_height;\n\tuint32_t output_stride;\n\tuint32_t output_scan_lines;\n\tuint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/\n\tuint32_t plane_addr_offset;\n\tuint8_t csid_src; /*RDI 0-2*/\n\tuint8_t rdi_cid;/*CID 1-16*/\n};\n\nenum msm_stream_memory_input_t {\n\tMEMORY_INPUT_DISABLED,\n\tMEMORY_INPUT_ENABLED\n};\n\nstruct msm_vfe_axi_stream_request_cmd {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint32_t vt_enable;\n\tuint32_t output_format;/*Planar/RAW/Misc*/\n\tenum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/\n\tstruct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];\n\n\tuint32_t burst_count;\n\tuint32_t hfr_mode;\n\tuint8_t frame_base;\n\n\tuint32_t init_frame_drop; /*MAX 31 Frames*/\n\tenum msm_vfe_frame_skip_pattern frame_skip_pattern;\n\tuint8_t buf_divert; /* if TRUE no vb2 buf done. */\n\t/*Return values*/\n\tuint32_t axi_stream_handle;\n\tuint32_t controllable_output;\n\tuint32_t burst_len;\n\t/* Flag indicating memory input stream */\n\tenum msm_stream_memory_input_t memory_input;\n};\n\nstruct msm_vfe_axi_stream_release_cmd {\n\tuint32_t stream_handle;\n};\n\nenum msm_vfe_axi_stream_cmd {\n\tSTOP_STREAM,\n\tSTART_STREAM,\n\tSTOP_IMMEDIATELY,\n};\n\nstruct msm_vfe_axi_stream_cfg_cmd {\n\tuint8_t num_streams;\n\tuint32_t stream_handle[VFE_AXI_SRC_MAX];\n\tenum msm_vfe_axi_stream_cmd cmd;\n\tuint8_t sync_frame_id_src;\n};\n\nenum msm_vfe_axi_stream_update_type {\n\tENABLE_STREAM_BUF_DIVERT,\n\tDISABLE_STREAM_BUF_DIVERT,\n\tUPDATE_STREAM_FRAMEDROP_PATTERN,\n\tUPDATE_STREAM_STATS_FRAMEDROP_PATTERN,\n\tUPDATE_STREAM_AXI_CONFIG,\n\tUPDATE_STREAM_REQUEST_FRAMES,\n\tUPDATE_STREAM_ADD_BUFQ,\n\tUPDATE_STREAM_REMOVE_BUFQ,\n\tUPDATE_STREAM_SW_FRAME_DROP,\n};\n\nenum msm_vfe_iommu_type {\n\tIOMMU_ATTACH,\n\tIOMMU_DETACH,\n};\n\nenum msm_vfe_buff_queue_id {\n\tVFE_BUF_QUEUE_DEFAULT,\n\tVFE_BUF_QUEUE_SHARED,\n\tVFE_BUF_QUEUE_MAX,\n};\n\nstruct msm_vfe_axi_stream_cfg_update_info {\n\tuint32_t stream_handle;\n\tuint32_t output_format;\n\tuint32_t user_stream_id;\n\tuint32_t frame_id;\n\tenum msm_vfe_frame_skip_pattern skip_pattern;\n\tstruct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];\n\tstruct msm_isp_sw_framskip sw_skip_info;\n};\n\nstruct msm_vfe_axi_halt_cmd {\n\tuint32_t stop_camif;\n\tuint32_t overflow_detected;\n\tuint32_t blocking_halt;\n};\n\nstruct msm_vfe_axi_reset_cmd {\n\tuint32_t blocking;\n\tuint32_t frame_id;\n};\n\nstruct msm_vfe_axi_restart_cmd {\n\tuint32_t enable_camif;\n};\n\nstruct msm_vfe_axi_stream_update_cmd {\n\tuint32_t num_streams;\n\tenum msm_vfe_axi_stream_update_type update_type;\n\tstruct msm_vfe_axi_stream_cfg_update_info\n\t\t\t\t\tupdate_info[MSM_ISP_STATS_MAX];\n};\n\nstruct msm_vfe_smmu_attach_cmd {\n\tuint32_t security_mode;\n\tuint32_t iommu_attach_mode;\n};\n\nstruct msm_vfe_stats_stream_request_cmd {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tenum msm_isp_stats_type stats_type;\n\tuint32_t composite_flag;\n\tuint32_t framedrop_pattern;\n\tuint32_t init_frame_drop; /*MAX 31 Frames*/\n\tuint32_t irq_subsample_pattern;\n\tuint32_t buffer_offset;\n\tuint32_t stream_handle;\n};\n\nstruct msm_vfe_stats_stream_release_cmd {\n\tuint32_t stream_handle;\n};\nstruct msm_vfe_stats_stream_cfg_cmd {\n\tuint8_t num_streams;\n\tuint32_t stream_handle[MSM_ISP_STATS_MAX];\n\tuint8_t enable;\n\tuint32_t stats_burst_len;\n};\n\nenum msm_vfe_reg_cfg_type {\n\tVFE_WRITE,\n\tVFE_WRITE_MB,\n\tVFE_READ,\n\tVFE_CFG_MASK,\n\tVFE_WRITE_DMI_16BIT,\n\tVFE_WRITE_DMI_32BIT,\n\tVFE_WRITE_DMI_64BIT,\n\tVFE_READ_DMI_16BIT,\n\tVFE_READ_DMI_32BIT,\n\tVFE_READ_DMI_64BIT,\n\tGET_MAX_CLK_RATE,\n\tGET_CLK_RATES,\n\tGET_ISP_ID,\n\tVFE_HW_UPDATE_LOCK,\n\tVFE_HW_UPDATE_UNLOCK,\n\tSET_WM_UB_SIZE,\n\tSET_UB_POLICY,\n};\n\nstruct msm_vfe_cfg_cmd2 {\n\tuint16_t num_cfg;\n\tuint16_t cmd_len;\n\tvoid __user *cfg_data;\n\tvoid __user *cfg_cmd;\n};\n\nstruct msm_vfe_cfg_cmd_list {\n\tstruct msm_vfe_cfg_cmd2      cfg_cmd;\n\tstruct msm_vfe_cfg_cmd_list *next;\n\tuint32_t                     next_size;\n};\n\nstruct msm_vfe_reg_rw_info {\n\tuint32_t reg_offset;\n\tuint32_t cmd_data_offset;\n\tuint32_t len;\n};\n\nstruct msm_vfe_reg_mask_info {\n\tuint32_t reg_offset;\n\tuint32_t mask;\n\tuint32_t val;\n};\n\nstruct msm_vfe_reg_dmi_info {\n\tuint32_t hi_tbl_offset; /*Optional*/\n\tuint32_t lo_tbl_offset; /*Required*/\n\tuint32_t len;\n};\n\nstruct msm_vfe_reg_cfg_cmd {\n\tunion {\n\t\tstruct msm_vfe_reg_rw_info rw_info;\n\t\tstruct msm_vfe_reg_mask_info mask_info;\n\t\tstruct msm_vfe_reg_dmi_info dmi_info;\n\t} u;\n\n\tenum msm_vfe_reg_cfg_type cmd_type;\n};\n\nenum vfe_sd_type {\n\tVFE_SD_0 = 0,\n\tVFE_SD_1,\n\tVFE_SD_COMMON,\n\tVFE_SD_MAX,\n};\n\n/* When you change the value below, check for the sof event_data size.\n * V4l2 limits payload to 64 bytes */\n#define MS_NUM_SLAVE_MAX 1\n\n/* Usecases when 2 HW need to be related or synced */\nenum msm_vfe_dual_hw_type {\n\tDUAL_NONE = 0,\n\tDUAL_HW_VFE_SPLIT = 1,\n\tDUAL_HW_MASTER_SLAVE = 2,\n};\n\n/* Type for 2 INTF when used in Master-Slave mode */\nenum msm_vfe_dual_hw_ms_type {\n\tMS_TYPE_NONE,\n\tMS_TYPE_MASTER,\n\tMS_TYPE_SLAVE,\n};\n\nstruct msm_isp_set_dual_hw_ms_cmd {\n\tuint8_t num_src;\n\t/* Each session can be only one type but multiple intf if YUV cam */\n\tenum msm_vfe_dual_hw_ms_type dual_hw_ms_type;\n\t/* Primary intf is mostly associated with preview.\n\t * This primary intf SOF frame_id and timestamp is tracked\n\t * and used to calculate delta */\n\tenum msm_vfe_input_src primary_intf;\n\t/* input_src array indicates other input INTF that may be Master/Slave.\n\t * For these additional intf, frame_id and timestamp are not saved.\n\t * However, if these are slaves then they will still get their\n\t * frame_id from Master */\n\tenum msm_vfe_input_src input_src[VFE_SRC_MAX];\n\tuint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */\n};\n\nenum msm_isp_buf_type {\n\tISP_PRIVATE_BUF,\n\tISP_SHARE_BUF,\n\tMAX_ISP_BUF_TYPE,\n};\n\nstruct msm_isp_unmap_buf_req {\n\tuint32_t fd;\n};\n\nstruct msm_isp_buf_request {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint8_t num_buf;\n\tuint32_t handle;\n\tenum msm_isp_buf_type buf_type;\n};\n\nstruct msm_isp_qbuf_plane {\n\tuint32_t addr;\n\tuint32_t offset;\n\tuint32_t length;\n};\n\nstruct msm_isp_qbuf_buffer {\n\tstruct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];\n\tuint32_t num_planes;\n};\n\nstruct msm_isp_qbuf_info {\n\tuint32_t handle;\n\tint32_t buf_idx;\n\t/*Only used for prepare buffer*/\n\tstruct msm_isp_qbuf_buffer buffer;\n\t/*Only used for diverted buffer*/\n\tuint32_t dirty_buf;\n};\n\nstruct msm_isp_clk_rates {\n\tuint32_t svs_rate;\n\tuint32_t nominal_rate;\n\tuint32_t high_rate;\n};\n\nstruct msm_vfe_axi_src_state {\n\tenum msm_vfe_input_src input_src;\n\tuint32_t src_active;\n\tuint32_t src_frame_id;\n};\n\nenum msm_isp_event_mask_index {\n\tISP_EVENT_MASK_INDEX_STATS_NOTIFY\t\t= 0,\n\tISP_EVENT_MASK_INDEX_ERROR\t\t\t= 1,\n\tISP_EVENT_MASK_INDEX_IOMMU_P_FAULT\t\t= 2,\n\tISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE\t\t= 3,\n\tISP_EVENT_MASK_INDEX_REG_UPDATE\t\t\t= 4,\n\tISP_EVENT_MASK_INDEX_SOF\t\t\t= 5,\n\tISP_EVENT_MASK_INDEX_BUF_DIVERT\t\t\t= 6,\n\tISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY\t\t= 7,\n\tISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE\t\t= 8,\n\tISP_EVENT_MASK_INDEX_BUF_DONE\t\t\t= 9,\n\tISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING\t\t= 10,\n\tISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH\t\t= 11,\n\tISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR\t\t= 12,\n};\n\n\n#define ISP_EVENT_SUBS_MASK_NONE\t\t\t0\n\n#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)\n\n#define ISP_EVENT_SUBS_MASK_ERROR \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_ERROR)\n\n#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)\n\n#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)\n\n#define ISP_EVENT_SUBS_MASK_REG_UPDATE \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)\n\n#define ISP_EVENT_SUBS_MASK_SOF \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_SOF)\n\n#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)\n\n#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)\n\n#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)\n\n#define ISP_EVENT_SUBS_MASK_BUF_DONE \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_BUF_DONE)\n\n#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)\n\n#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)\n\n#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \\\n\t\t\t(1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)\n\nenum msm_isp_event_idx {\n\tISP_REG_UPDATE        = 0,\n\tISP_EPOCH_0           = 1,\n\tISP_EPOCH_1           = 2,\n\tISP_START_ACK         = 3,\n\tISP_STOP_ACK          = 4,\n\tISP_IRQ_VIOLATION     = 5,\n\tISP_STATS_OVERFLOW    = 6,\n\tISP_BUF_DONE          = 7,\n\tISP_FE_RD_DONE        = 8,\n\tISP_IOMMU_P_FAULT     = 9,\n\tISP_ERROR             = 10,\n\tISP_HW_FATAL_ERROR      = 11,\n\tISP_PING_PONG_MISMATCH = 12,\n\tISP_REG_UPDATE_MISSING = 13,\n\tISP_BUF_FATAL_ERROR = 14,\n\tISP_EVENT_MAX         = 15\n};\n\n#define ISP_EVENT_OFFSET          8\n#define ISP_EVENT_BASE            (V4L2_EVENT_PRIVATE_START)\n#define ISP_BUF_EVENT_BASE        (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))\n#define ISP_STATS_EVENT_BASE      (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))\n#define ISP_CAMIF_EVENT_BASE      (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))\n#define ISP_STREAM_EVENT_BASE     (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))\n#define ISP_EVENT_REG_UPDATE      (ISP_EVENT_BASE + ISP_REG_UPDATE)\n#define ISP_EVENT_EPOCH_0         (ISP_EVENT_BASE + ISP_EPOCH_0)\n#define ISP_EVENT_EPOCH_1         (ISP_EVENT_BASE + ISP_EPOCH_1)\n#define ISP_EVENT_START_ACK       (ISP_EVENT_BASE + ISP_START_ACK)\n#define ISP_EVENT_STOP_ACK        (ISP_EVENT_BASE + ISP_STOP_ACK)\n#define ISP_EVENT_IRQ_VIOLATION   (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)\n#define ISP_EVENT_STATS_OVERFLOW  (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)\n#define ISP_EVENT_ERROR           (ISP_EVENT_BASE + ISP_ERROR)\n#define ISP_EVENT_SOF             (ISP_CAMIF_EVENT_BASE)\n#define ISP_EVENT_EOF             (ISP_CAMIF_EVENT_BASE + 1)\n#define ISP_EVENT_BUF_DONE        (ISP_EVENT_BASE + ISP_BUF_DONE)\n#define ISP_EVENT_BUF_DIVERT      (ISP_BUF_EVENT_BASE)\n#define ISP_EVENT_STATS_NOTIFY    (ISP_STATS_EVENT_BASE)\n#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)\n#define ISP_EVENT_FE_READ_DONE    (ISP_EVENT_BASE + ISP_FE_RD_DONE)\n#define ISP_EVENT_IOMMU_P_FAULT   (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)\n#define ISP_EVENT_HW_FATAL_ERROR  (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)\n#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)\n#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)\n#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)\n#define ISP_EVENT_STREAM_UPDATE_DONE   (ISP_STREAM_EVENT_BASE)\n\n/* The msm_v4l2_event_data structure should match the\n * v4l2_event.u.data field.\n * should not exceed 64 bytes */\n\nstruct msm_isp_buf_event {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint32_t handle;\n\tuint32_t output_format;\n\tint8_t buf_idx;\n};\nstruct msm_isp_fetch_eng_event {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint32_t handle;\n\tuint32_t fd;\n\tint8_t buf_idx;\n\tint8_t offline_mode;\n};\nstruct msm_isp_stats_event {\n\tuint32_t stats_mask;                        /* 4 bytes */\n\tuint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];  /* 11 bytes */\n};\n\nstruct msm_isp_stream_ack {\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint32_t handle;\n};\n\nenum msm_vfe_error_type {\n\tISP_ERROR_NONE,\n\tISP_ERROR_CAMIF,\n\tISP_ERROR_BUS_OVERFLOW,\n\tISP_ERROR_RETURN_EMPTY_BUFFER,\n\tISP_ERROR_FRAME_ID_MISMATCH,\n\tISP_ERROR_MAX,\n};\n\nstruct msm_isp_error_info {\n\tenum msm_vfe_error_type err_type;\n\tuint32_t session_id;\n\tuint32_t stream_id;\n\tuint32_t stream_id_mask;\n};\n\n/* This structure reports delta between master and slave */\nstruct msm_isp_ms_delta_info {\n\tuint8_t num_delta_info;\n\tuint32_t delta[MS_NUM_SLAVE_MAX];\n};\n\n/* This is sent in EPOCH irq */\nstruct msm_isp_output_info {\n\tuint8_t regs_not_updated;\n\t/* mask with bufq_handle for regs not updated or return empty */\n\tuint16_t output_err_mask;\n\t/* mask with stream_idx for get_buf failed */\n\tuint8_t stream_framedrop_mask;\n\t/* mask with stats stream_idx for get_buf failed */\n\tuint16_t stats_framedrop_mask;\n\t/* delta between master and slave */\n};\n\n/* This structure is piggybacked with SOF event */\nstruct msm_isp_sof_info {\n\tuint8_t regs_not_updated;\n\t/* mask with AXI_SRC for regs not updated */\n\tuint16_t reg_update_fail_mask;\n\t/* mask with bufq_handle for get_buf failed */\n\tuint32_t stream_get_buf_fail_mask;\n\t/* mask with stats stream_idx for get_buf failed */\n\tuint16_t stats_get_buf_fail_mask;\n\t/* delta between master and slave */\n\tstruct msm_isp_ms_delta_info ms_delta_info;\n};\n\nstruct msm_isp_event_data {\n\t/*Wall clock except for buffer divert events\n\t *which use monotonic clock\n\t */\n\tstruct timeval timestamp;\n\t/* Monotonic timestamp since bootup */\n\tstruct timeval mono_timestamp;\n\tuint32_t frame_id;\n\tunion {\n\t\t/* Sent for Stats_Done event */\n\t\tstruct msm_isp_stats_event stats;\n\t\t/* Sent for Buf_Divert event */\n\t\tstruct msm_isp_buf_event buf_done;\n\t\t/* Sent for offline fetch done event */\n\t\tstruct msm_isp_fetch_eng_event fetch_done;\n\t\t/* Sent for Error_Event */\n\t\tstruct msm_isp_error_info error_info;\n\t\t/*\n\t\t * This struct needs to be removed once\n\t\t * userspace switches to sof_info\n\t\t */\n\t\tstruct msm_isp_output_info output_info;\n\t\t/* Sent for SOF event */\n\t\tstruct msm_isp_sof_info sof_info;\n\t} u; /* union can have max 52 bytes */\n};\n\n#ifdef CONFIG_COMPAT\nstruct msm_isp_event_data32 {\n\tstruct compat_timeval timestamp;\n\tstruct compat_timeval mono_timestamp;\n\tuint32_t frame_id;\n\tunion {\n\t\tstruct msm_isp_stats_event stats;\n\t\tstruct msm_isp_buf_event buf_done;\n\t\tstruct msm_isp_fetch_eng_event fetch_done;\n\t\tstruct msm_isp_error_info error_info;\n\t\tstruct msm_isp_output_info output_info;\n\t\tstruct msm_isp_sof_info sof_info;\n\t} u;\n};\n#endif\n\n#define V4L2_PIX_FMT_QBGGR8  v4l2_fourcc('Q', 'B', 'G', '8')\n#define V4L2_PIX_FMT_QGBRG8  v4l2_fourcc('Q', 'G', 'B', '8')\n#define V4L2_PIX_FMT_QGRBG8  v4l2_fourcc('Q', 'G', 'R', '8')\n#define V4L2_PIX_FMT_QRGGB8  v4l2_fourcc('Q', 'R', 'G', '8')\n#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')\n#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')\n#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')\n#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')\n#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')\n#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')\n#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')\n#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')\n#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')\n#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')\n#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')\n#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')\n#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')\n#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')\n#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')\n#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')\n#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')\n#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')\n#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')\n#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/\n#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/\n#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/\n#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/\n\n#define VIDIOC_MSM_VFE_REG_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)\n\n#define VIDIOC_MSM_ISP_REQUEST_BUF \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)\n\n#define VIDIOC_MSM_ISP_ENQUEUE_BUF \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)\n\n#define VIDIOC_MSM_ISP_RELEASE_BUF \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)\n\n#define VIDIOC_MSM_ISP_REQUEST_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)\n\n#define VIDIOC_MSM_ISP_CFG_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)\n\n#define VIDIOC_MSM_ISP_RELEASE_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)\n\n#define VIDIOC_MSM_ISP_INPUT_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)\n\n#define VIDIOC_MSM_ISP_SET_SRC_STATE \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)\n\n#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+9, \\\n\tstruct msm_vfe_stats_stream_request_cmd)\n\n#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)\n\n#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+11, \\\n\tstruct msm_vfe_stats_stream_release_cmd)\n\n#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src)\n\n#define VIDIOC_MSM_ISP_UPDATE_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)\n\n#define VIDIOC_MSM_VFE_REG_LIST_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list)\n\n#define VIDIOC_MSM_ISP_SMMU_ATTACH \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd)\n\n#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd)\n\n#define VIDIOC_MSM_ISP_AXI_HALT \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd)\n\n#define VIDIOC_MSM_ISP_AXI_RESET \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd)\n\n#define VIDIOC_MSM_ISP_AXI_RESTART \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd)\n\n#define VIDIOC_MSM_ISP_FETCH_ENG_START \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start)\n\n#define VIDIOC_MSM_ISP_DEQUEUE_BUF \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+21, struct msm_isp_qbuf_info)\n\n#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+22, struct msm_isp_set_dual_hw_ms_cmd)\n\n#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+23, struct msm_vfe_fetch_eng_start)\n\n#define VIDIOC_MSM_ISP_UNMAP_BUF \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE+24, struct msm_isp_unmap_buf_req)\n\n#endif /* __MSMB_ISP__ */\n"
  },
  {
    "path": "selfdrive/camerad/include/msmb_ispif.h",
    "content": "#ifndef MSM_CAM_ISPIF_H\n#define MSM_CAM_ISPIF_H\n\n#define CSID_VERSION_V20                      0x02000011\n#define CSID_VERSION_V22                      0x02001000\n#define CSID_VERSION_V30                      0x30000000\n#define CSID_VERSION_V3                      0x30000000\n\nenum msm_ispif_vfe_intf {\n\tVFE0,\n\tVFE1,\n\tVFE_MAX\n};\n#define VFE0_MASK    (1 << VFE0)\n#define VFE1_MASK    (1 << VFE1)\n\nenum msm_ispif_intftype {\n\tPIX0,\n\tRDI0,\n\tPIX1,\n\tRDI1,\n\tRDI2,\n\tINTF_MAX\n};\n#define MAX_PARAM_ENTRIES (INTF_MAX * 2)\n#define MAX_CID_CH\t8\n\n#define PIX0_MASK (1 << PIX0)\n#define PIX1_MASK (1 << PIX1)\n#define RDI0_MASK (1 << RDI0)\n#define RDI1_MASK (1 << RDI1)\n#define RDI2_MASK (1 << RDI2)\n\n\nenum msm_ispif_vc {\n\tVC0,\n\tVC1,\n\tVC2,\n\tVC3,\n\tVC_MAX\n};\n\nenum msm_ispif_cid {\n\tCID0,\n\tCID1,\n\tCID2,\n\tCID3,\n\tCID4,\n\tCID5,\n\tCID6,\n\tCID7,\n\tCID8,\n\tCID9,\n\tCID10,\n\tCID11,\n\tCID12,\n\tCID13,\n\tCID14,\n\tCID15,\n\tCID_MAX\n};\n\nenum msm_ispif_csid {\n\tCSID0,\n\tCSID1,\n\tCSID2,\n\tCSID3,\n\tCSID_MAX\n};\n\nstruct msm_ispif_params_entry {\n\tenum msm_ispif_vfe_intf vfe_intf;\n\tenum msm_ispif_intftype intftype;\n\tint num_cids;\n\tenum msm_ispif_cid cids[3];\n\tenum msm_ispif_csid csid;\n\tint crop_enable;\n\tuint16_t crop_start_pixel;\n\tuint16_t crop_end_pixel;\n};\n\nstruct msm_ispif_param_data {\n\tuint32_t num;\n\tstruct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];\n};\n\nstruct msm_isp_info {\n\tuint32_t max_resolution;\n\tuint32_t id;\n\tuint32_t ver;\n};\n\nstruct msm_ispif_vfe_info {\n\tint num_vfe;\n\tstruct msm_isp_info info[VFE_MAX];\n};\n\nenum ispif_cfg_type_t {\n\tISPIF_CLK_ENABLE,\n\tISPIF_CLK_DISABLE,\n\tISPIF_INIT,\n\tISPIF_CFG,\n\tISPIF_START_FRAME_BOUNDARY,\n\tISPIF_RESTART_FRAME_BOUNDARY,\n\tISPIF_STOP_FRAME_BOUNDARY,\n\tISPIF_STOP_IMMEDIATELY,\n\tISPIF_RELEASE,\n\tISPIF_ENABLE_REG_DUMP,\n\tISPIF_SET_VFE_INFO,\n};\n\nstruct ispif_cfg_data {\n\tenum ispif_cfg_type_t cfg_type;\n\tunion {\n\t\tint reg_dump;                        /* ISPIF_ENABLE_REG_DUMP */\n\t\tuint32_t csid_version;               /* ISPIF_INIT */\n\t\tstruct msm_ispif_vfe_info vfe_info;  /* ISPIF_SET_VFE_INFO */\n\t\tstruct msm_ispif_param_data params;  /* CFG, START, STOP */\n\t};\n};\n\n#define VIDIOC_MSM_ISPIF_CFG \\\n\t_IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)\n\n#endif /* MSM_CAM_ISPIF_H */\n"
  },
  {
    "path": "selfdrive/camerad/main.cc",
    "content": "#include <poll.h>\n#include <sys/socket.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cstdio>\n#include <thread>\n\n#include \"libyuv.h\"\n\n#include \"cereal/visionipc/visionipc_server.h\"\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n\n#ifdef QCOM\n#include \"selfdrive/camerad/cameras/camera_qcom.h\"\n#elif QCOM2\n#include \"selfdrive/camerad/cameras/camera_qcom2.h\"\n#elif WEBCAM\n#include \"selfdrive/camerad/cameras/camera_webcam.h\"\n#elif MIPI\n#include \"selfdrive/camerad/cameras/camera_mipi.h\"\n#else\n#include \"selfdrive/camerad/cameras/camera_frame_stream.h\"\n#endif\n\nExitHandler do_exit;\n\nvoid party(cl_device_id device_id, cl_context context) {\n  MultiCameraState cameras = {};\n  VisionIpcServer vipc_server(\"camerad\", device_id, context);\n\n  cameras_init(&vipc_server, &cameras, device_id, context);\n  cameras_open(&cameras);\n\n  vipc_server.start_listener();\n\n  cameras_run(&cameras);\n}\n\n#ifdef QCOM\n#include \"CL/cl_ext_qcom.h\"\n#endif\n\nint main(int argc, char *argv[]) {\n  set_realtime_priority(53);\n  if (Hardware::EON()) {\n    set_core_affinity(2);\n  } else if (Hardware::TICI()) {\n    set_core_affinity(6);\n  } else if (Hardware::JETSON()) {\n    set_core_affinity(0);\n  }\n\n  #ifdef XNX\n  cl_device_id device_id = cl_get_device_id(CL_DEVICE_TYPE_GPU);\n  #else\n  cl_device_id device_id = cl_get_device_id(CL_DEVICE_TYPE_DEFAULT);\n  #endif\n\n   // TODO: do this for QCOM2 too\n#if defined(QCOM)\n  const cl_context_properties props[] = {CL_CONTEXT_PRIORITY_HINT_QCOM, CL_PRIORITY_HINT_HIGH_QCOM, 0};\n  cl_context context = CL_CHECK_ERR(clCreateContext(props, 1, &device_id, NULL, NULL, &err));\n#else\n  cl_context context = CL_CHECK_ERR(clCreateContext(NULL, 1, &device_id, NULL, NULL, &err));\n#endif\n\n  party(device_id, context);\n\n  CL_CHECK(clReleaseContext(context));\n}\n"
  },
  {
    "path": "selfdrive/camerad/snapshot/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/camerad/snapshot/snapshot.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport subprocess\nimport time\n\nimport numpy as np\nfrom PIL import Image\nfrom typing import List\n\nimport cereal.messaging as messaging\nfrom common.params import Params\nfrom common.realtime import DT_MDL\nfrom common.transformations.camera import eon_f_frame_size, eon_d_frame_size, leon_d_frame_size, tici_f_frame_size\nfrom selfdrive.hardware import TICI\nfrom selfdrive.controls.lib.alertmanager import set_offroad_alert\nfrom selfdrive.manager.process_config import managed_processes\n\nLM_THRESH = 120  # defined in selfdrive/camerad/imgproc/utils.h\n\n\ndef jpeg_write(fn, dat):\n  img = Image.fromarray(dat)\n  img.save(fn, \"JPEG\")\n\n\ndef extract_image(dat, frame_sizes):\n  img = np.frombuffer(dat, dtype=np.uint8)\n  w, h = frame_sizes[len(img) // 3]\n  b = img[::3].reshape(h, w)\n  g = img[1::3].reshape(h, w)\n  r = img[2::3].reshape(h, w)\n  return np.dstack([r, g, b])\n\n\ndef rois_in_focus(lapres: List[float]) -> float:\n  sz = len(lapres)\n  return sum([1. / sz for sharpness in\n              lapres if sharpness >= LM_THRESH])\n\n\ndef get_snapshots(frame=\"roadCameraState\", front_frame=\"driverCameraState\", focus_perc_threshold=0.):\n  frame_sizes = [eon_f_frame_size, eon_d_frame_size, leon_d_frame_size, tici_f_frame_size]\n  frame_sizes = {w * h: (w, h) for (w, h) in frame_sizes}\n\n  sockets = []\n  if frame is not None:\n    sockets.append(frame)\n  if front_frame is not None:\n    sockets.append(front_frame)\n\n  # wait 4 sec from camerad startup for focus and exposure\n  sm = messaging.SubMaster(sockets)\n  while sm[sockets[0]].frameId < int(4. / DT_MDL):\n    sm.update()\n\n  start_t = time.monotonic()\n  while time.monotonic() - start_t < 10:\n    sm.update()\n    if min(sm.rcv_frame.values()) > 1 and rois_in_focus(sm[frame].sharpnessScore) >= focus_perc_threshold:\n      break\n\n  rear = extract_image(sm[frame].image, frame_sizes) if frame is not None else None\n  front = extract_image(sm[front_frame].image, frame_sizes) if front_frame is not None else None\n  return rear, front\n\n\ndef snapshot():\n  params = Params()\n  front_camera_allowed = params.get_bool(\"RecordFront\")\n\n  if (not params.get_bool(\"IsOffroad\")) or params.get_bool(\"IsTakingSnapshot\"):\n    print(\"Already taking snapshot\")\n    return None, None\n\n  params.put_bool(\"IsTakingSnapshot\", True)\n  set_offroad_alert(\"Offroad_IsTakingSnapshot\", True)\n  time.sleep(2.0)  # Give thermald time to read the param, or if just started give camerad time to start\n\n  # Check if camerad is already started\n  try:\n    subprocess.check_call([\"pgrep\", \"camerad\"])\n    print(\"Camerad already running\")\n    params.put_bool(\"IsTakingSnapshot\", False)\n    params.delete(\"Offroad_IsTakingSnapshot\")\n    return None, None\n  except subprocess.CalledProcessError:\n    pass\n\n  os.environ[\"SEND_ROAD\"] = \"1\"\n  os.environ[\"SEND_WIDE_ROAD\"] = \"1\"\n\n  if front_camera_allowed:\n    os.environ[\"SEND_DRIVER\"] = \"1\"\n\n  managed_processes['camerad'].start()\n  frame = \"wideRoadCameraState\" if TICI else \"roadCameraState\"\n  front_frame = \"driverCameraState\" if front_camera_allowed else None\n  focus_perc_threshold = 0. if TICI else 10 / 12.\n\n  rear, front = get_snapshots(frame, front_frame, focus_perc_threshold)\n  managed_processes['camerad'].stop()\n\n  params.put_bool(\"IsTakingSnapshot\", False)\n  set_offroad_alert(\"Offroad_IsTakingSnapshot\", False)\n\n  if not front_camera_allowed:\n    front = None\n\n  return rear, front\n\n\nif __name__ == \"__main__\":\n  pic, fpic = snapshot()\n  if pic is not None:\n    print(pic.shape)\n    jpeg_write(\"/tmp/back.jpg\", pic)\n    if fpic is not None:\n      jpeg_write(\"/tmp/front.jpg\", fpic)\n  else:\n    print(\"Error taking snapshot\")\n"
  },
  {
    "path": "selfdrive/camerad/transforms/rgb_to_yuv.cc",
    "content": "#include \"selfdrive/camerad/transforms/rgb_to_yuv.h\"\n\n#include <cassert>\n#include <cstdio>\n\nRgb2Yuv::Rgb2Yuv(cl_context ctx, cl_device_id device_id, int width, int height, int rgb_stride) {\n  assert(width % 2 == 0 && height % 2 == 0);\n  char args[1024];\n  snprintf(args, sizeof(args),\n           \"-cl-fast-relaxed-math -cl-denorms-are-zero \"\n#ifdef CL_DEBUG\n           \"-DCL_DEBUG \"\n#endif\n           \"-DWIDTH=%d -DHEIGHT=%d -DUV_WIDTH=%d -DUV_HEIGHT=%d -DRGB_STRIDE=%d -DRGB_SIZE=%d\",\n           width, height, width / 2, height / 2, rgb_stride, width * height);\n\n  cl_program prg = cl_program_from_file(ctx, device_id, \"transforms/rgb_to_yuv.cl\", args);\n  krnl = CL_CHECK_ERR(clCreateKernel(prg, \"rgb_to_yuv\", &err));\n  CL_CHECK(clReleaseProgram(prg));\n\n  work_size[0] = (width + (width % 4 == 0 ? 0 : (4 - width % 4))) / 4;\n  work_size[1] = (height + (height % 4 == 0 ? 0 : (4 - height % 4))) / 4;\n}\n\nRgb2Yuv::~Rgb2Yuv() {\n  CL_CHECK(clReleaseKernel(krnl));\n}\n\nvoid Rgb2Yuv::queue(cl_command_queue q, cl_mem rgb_cl, cl_mem yuv_cl) {\n  CL_CHECK(clSetKernelArg(krnl, 0, sizeof(cl_mem), &rgb_cl));\n  CL_CHECK(clSetKernelArg(krnl, 1, sizeof(cl_mem), &yuv_cl));\n  cl_event event;\n  CL_CHECK(clEnqueueNDRangeKernel(q, krnl, 2, NULL, &work_size[0], NULL, 0, 0, &event));\n  CL_CHECK(clWaitForEvents(1, &event));\n  CL_CHECK(clReleaseEvent(event));\n}\n"
  },
  {
    "path": "selfdrive/camerad/transforms/rgb_to_yuv.cl",
    "content": "#define RGB_TO_Y(r, g, b) ((((mul24(b, 13) + mul24(g, 65) + mul24(r, 33)) + 64) >> 7) + 16)\n#define RGB_TO_U(r, g, b) ((mul24(b, 56) - mul24(g, 37) - mul24(r, 19) + 0x8080) >> 8)\n#define RGB_TO_V(r, g, b) ((mul24(r, 56) - mul24(g, 47) - mul24(b, 9) + 0x8080) >> 8)\n#define AVERAGE(x, y, z, w) ((convert_ushort(x) + convert_ushort(y) + convert_ushort(z) + convert_ushort(w) + 1) >> 1)\n\ninline void convert_2_ys(__global uchar * out_yuv, int yi, const uchar8 rgbs1) {\n  uchar2 yy = (uchar2)(\n    RGB_TO_Y(rgbs1.s2, rgbs1.s1, rgbs1.s0),\n    RGB_TO_Y(rgbs1.s5, rgbs1.s4, rgbs1.s3)\n  );\n#ifdef CL_DEBUG\n  if(yi >= RGB_SIZE)\n    printf(\"Y vector2 overflow, %d > %d\\n\", yi, RGB_SIZE);\n#endif\n  vstore2(yy, 0, out_yuv + yi);\n}\n\ninline void convert_4_ys(__global uchar * out_yuv, int yi, const uchar8 rgbs1, const uchar8 rgbs3) {\n  const uchar4 yy = (uchar4)(\n    RGB_TO_Y(rgbs1.s2, rgbs1.s1, rgbs1.s0),\n    RGB_TO_Y(rgbs1.s5, rgbs1.s4, rgbs1.s3),\n    RGB_TO_Y(rgbs3.s0, rgbs1.s7, rgbs1.s6),\n    RGB_TO_Y(rgbs3.s3, rgbs3.s2, rgbs3.s1)\n  );\n#ifdef CL_DEBUG\n  if(yi > RGB_SIZE - 4)\n    printf(\"Y vector4 overflow, %d > %d\\n\", yi, RGB_SIZE - 4);\n#endif\n  vstore4(yy, 0, out_yuv + yi);\n}\n\ninline void convert_uv(__global uchar * out_yuv, int ui, int vi,\n                    const uchar8 rgbs1, const uchar8 rgbs2) {\n  // U & V: average of 2x2 pixels square\n  const short ab = AVERAGE(rgbs1.s0, rgbs1.s3, rgbs2.s0, rgbs2.s3);\n  const short ag = AVERAGE(rgbs1.s1, rgbs1.s4, rgbs2.s1, rgbs2.s4);\n  const short ar = AVERAGE(rgbs1.s2, rgbs1.s5, rgbs2.s2, rgbs2.s5);\n#ifdef CL_DEBUG\n  if(ui >= RGB_SIZE  + RGB_SIZE / 4)\n    printf(\"U overflow, %d >= %d\\n\", ui, RGB_SIZE  + RGB_SIZE / 4);\n  if(vi >= RGB_SIZE  + RGB_SIZE / 2)\n    printf(\"V overflow, %d >= %d\\n\", vi, RGB_SIZE  + RGB_SIZE / 2);\n#endif\n  out_yuv[ui] = RGB_TO_U(ar, ag, ab);\n  out_yuv[vi] = RGB_TO_V(ar, ag, ab);\n}\n\ninline void convert_2_uvs(__global uchar * out_yuv, int ui, int vi,\n                    const uchar8 rgbs1, const uchar8 rgbs2, const uchar8 rgbs3, const uchar8 rgbs4) {\n  // U & V: average of 2x2 pixels square\n  const short ab1 = AVERAGE(rgbs1.s0, rgbs1.s3, rgbs2.s0, rgbs2.s3);\n  const short ag1 = AVERAGE(rgbs1.s1, rgbs1.s4, rgbs2.s1, rgbs2.s4);\n  const short ar1 = AVERAGE(rgbs1.s2, rgbs1.s5, rgbs2.s2, rgbs2.s5);\n  const short ab2 = AVERAGE(rgbs1.s6, rgbs3.s1, rgbs2.s6, rgbs4.s1);\n  const short ag2 = AVERAGE(rgbs1.s7, rgbs3.s2, rgbs2.s7, rgbs4.s2);\n  const short ar2 = AVERAGE(rgbs3.s0, rgbs3.s3, rgbs4.s0, rgbs4.s3);\n  uchar2 u2 = (uchar2)(\n    RGB_TO_U(ar1, ag1, ab1),\n    RGB_TO_U(ar2, ag2, ab2)\n  );\n  uchar2 v2 = (uchar2)(\n    RGB_TO_V(ar1, ag1, ab1),\n    RGB_TO_V(ar2, ag2, ab2)\n  );\n#ifdef CL_DEBUG1\n  if(ui > RGB_SIZE  + RGB_SIZE / 4 - 2)\n    printf(\"U 2 overflow, %d >= %d\\n\", ui, RGB_SIZE  + RGB_SIZE / 4 - 2);\n  if(vi > RGB_SIZE  + RGB_SIZE / 2 - 2)\n    printf(\"V 2 overflow, %d >= %d\\n\", vi, RGB_SIZE  + RGB_SIZE / 2 - 2);\n#endif\n  vstore2(u2, 0, out_yuv + ui);\n  vstore2(v2, 0, out_yuv + vi);\n}\n\n__kernel void rgb_to_yuv(__global uchar const * const rgb,\n                    __global uchar * out_yuv)\n{\n  const int dx = get_global_id(0);\n  const int dy = get_global_id(1);\n  const int col = mul24(dx, 4); // Current column in rgb image\n  const int row = mul24(dy, 4); // Current row in rgb image\n  const int bgri_start = mad24(row, RGB_STRIDE, mul24(col, 3)); // Start offset of rgb data being converted\n  const int yi_start = mad24(row,  WIDTH, col); // Start offset in the target yuv buffer\n  int ui = mad24(row / 2, UV_WIDTH, RGB_SIZE + col / 2);\n  int vi = mad24(row / 2 , UV_WIDTH, RGB_SIZE + UV_WIDTH * UV_HEIGHT + col / 2);\n  int num_col = min(WIDTH - col, 4);\n  int num_row = min(HEIGHT - row, 4);\n  if(num_row == 4) {\n    const uchar8 rgbs0_0 = vload8(0, rgb + bgri_start);\n    const uchar8 rgbs0_1 = vload8(0, rgb + bgri_start + 8);\n    const uchar8 rgbs1_0 = vload8(0, rgb + bgri_start + RGB_STRIDE);\n    const uchar8 rgbs1_1 = vload8(0, rgb + bgri_start + RGB_STRIDE + 8);\n    const uchar8 rgbs2_0 = vload8(0, rgb + bgri_start + RGB_STRIDE * 2);\n    const uchar8 rgbs2_1 = vload8(0, rgb + bgri_start + RGB_STRIDE * 2 + 8);\n    const uchar8 rgbs3_0 = vload8(0, rgb + bgri_start + RGB_STRIDE * 3);\n    const uchar8 rgbs3_1 = vload8(0, rgb + bgri_start + RGB_STRIDE * 3 + 8);\n    if(num_col == 4) {\n      convert_4_ys(out_yuv, yi_start, rgbs0_0, rgbs0_1);\n      convert_4_ys(out_yuv, yi_start + WIDTH, rgbs1_0, rgbs1_1);\n      convert_4_ys(out_yuv, yi_start + WIDTH * 2, rgbs2_0, rgbs2_1);\n      convert_4_ys(out_yuv, yi_start + WIDTH * 3, rgbs3_0, rgbs3_1);\n      convert_2_uvs(out_yuv, ui, vi, rgbs0_0, rgbs1_0, rgbs0_1, rgbs1_1);\n      convert_2_uvs(out_yuv, ui + UV_WIDTH, vi + UV_WIDTH, rgbs2_0, rgbs3_0, rgbs2_1, rgbs3_1);\n    } else if(num_col == 2) {\n      convert_2_ys(out_yuv, yi_start, rgbs0_0);\n      convert_2_ys(out_yuv, yi_start + WIDTH, rgbs1_0);\n      convert_2_ys(out_yuv, yi_start + WIDTH * 2, rgbs2_0);\n      convert_2_ys(out_yuv, yi_start + WIDTH * 3, rgbs3_0);\n      convert_uv(out_yuv, ui, vi, rgbs0_0, rgbs1_0);\n      convert_uv(out_yuv, ui + UV_WIDTH, vi + UV_WIDTH, rgbs2_0, rgbs3_0);\n    }\n  } else {\n    const uchar8 rgbs0_0 = vload8(0, rgb + bgri_start);\n    const uchar8 rgbs0_1 = vload8(0, rgb + bgri_start + 8);\n    const uchar8 rgbs1_0 = vload8(0, rgb + bgri_start + RGB_STRIDE);\n    const uchar8 rgbs1_1 = vload8(0, rgb + bgri_start + RGB_STRIDE + 8);\n    if(num_col == 4) {\n      convert_4_ys(out_yuv, yi_start, rgbs0_0, rgbs0_1);\n      convert_4_ys(out_yuv, yi_start + WIDTH, rgbs1_0, rgbs1_1);\n      convert_2_uvs(out_yuv, ui, vi, rgbs0_0, rgbs1_0, rgbs0_1, rgbs1_1);\n    } else if(num_col == 2) {\n      convert_2_ys(out_yuv, yi_start, rgbs0_0);\n      convert_2_ys(out_yuv, yi_start + WIDTH, rgbs1_0);\n      convert_uv(out_yuv, ui, vi, rgbs0_0, rgbs1_0);\n    }\n  }\n}\n"
  },
  {
    "path": "selfdrive/camerad/transforms/rgb_to_yuv.h",
    "content": "#pragma once\n\n#include \"selfdrive/common/clutil.h\"\n\nclass Rgb2Yuv {\npublic:\n  Rgb2Yuv(cl_context ctx, cl_device_id device_id, int width, int height, int rgb_stride);\n  ~Rgb2Yuv();\n  void queue(cl_command_queue q, cl_mem rgb_cl, cl_mem yuv_cl);\nprivate:\n  size_t work_size[2];\n  cl_kernel krnl;\n};\n\n"
  },
  {
    "path": "selfdrive/camerad/transforms/rgb_to_yuv_test.cc",
    "content": "#include <fcntl.h>\n#include <getopt.h>\n#include <memory.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cmath>\n#include <csignal>\n#include <cstdint>\n#include <cstdlib>\n#include <fstream>\n#include <iomanip>\n#include <iostream>\n#include <string>\n#include <thread>\n#include <vector>\n\n#ifdef ANDROID\n\n#define MAXE 0\n#include <unistd.h>\n\n#else\n// The libyuv implementation on ARM is slightly different than on x86\n// Our implementation matches the ARM version, so accept errors of 1\n#define MAXE 1\n\n#endif\n\n#include <CL/cl.h>\n\n#include \"libyuv.h\"\n#include \"selfdrive/camerad/transforms/rgb_to_yuv.h\"\n#include \"selfdrive/common/clutil.h\"\n\nstatic inline double millis_since_boot() {\n  struct timespec t;\n  clock_gettime(CLOCK_BOOTTIME, &t);\n  return t.tv_sec * 1000.0 + t.tv_nsec * 1e-6;\n}\n\nvoid cl_init(cl_device_id &device_id, cl_context &context) {\n  device_id = cl_get_device_id(CL_DEVICE_TYPE_DEFAULT);\n  context = CL_CHECK_ERR(clCreateContext(NULL, 1, &device_id, NULL, NULL, &err));\n}\n\n\nbool compare_results(uint8_t *a, uint8_t *b, int len, int stride, int width, int height, uint8_t *rgb) {\n  int min_diff = 0., max_diff = 0., max_e = 0.;\n  int e1 = 0, e0 = 0;\n  int e0y = 0, e0u = 0, e0v = 0, e1y = 0, e1u = 0, e1v = 0;\n  int max_e_i = 0;\n  for (int i = 0;i < len;i++) {\n    int e = ((int)a[i]) - ((int)b[i]);\n    if(e < min_diff) {\n      min_diff = e;\n    }\n    if(e > max_diff) {\n      max_diff = e;\n    }\n    int e_abs = std::abs(e);\n    if(e_abs > max_e) {\n      max_e = e_abs;\n      max_e_i = i;\n    }\n    if(e_abs < 1) {\n      e0++;\n      if(i < stride * height)\n        e0y++;\n      else if(i < stride * height + stride * height / 4)\n        e0u++;\n      else\n        e0v++;\n    } else {\n      e1++;\n      if(i < stride * height)\n        e1y++;\n      else if(i < stride * height + stride * height / 4)\n        e1u++;\n      else\n        e1v++;\n    }\n  }\n  //printf(\"max diff : %d, min diff : %d, e < 1: %d, e >= 1: %d\\n\", max_diff, min_diff, e0, e1);\n  //printf(\"Y: e < 1: %d, e >= 1: %d, U: e < 1: %d, e >= 1: %d, V: e < 1: %d, e >= 1: %d\\n\", e0y, e1y, e0u, e1u, e0v, e1v);\n  if(max_e <= MAXE) {\n    return true;\n  }\n  int row = max_e_i / stride;\n  if(row < height) {\n    printf(\"max error is Y: %d = (libyuv: %u - cl: %u), row: %d, col: %d\\n\", max_e, a[max_e_i], b[max_e_i], row, max_e_i % stride);\n  } else if(row >= height && row < (height + height / 4)) {\n    printf(\"max error is U: %d = %u - %u, row: %d, col: %d\\n\", max_e, a[max_e_i], b[max_e_i], (row - height) / 2, max_e_i % stride / 2);\n  } else {\n    printf(\"max error is V: %d = %u - %u, row: %d, col: %d\\n\", max_e, a[max_e_i], b[max_e_i], (row - height - height / 4) / 2, max_e_i % stride / 2);\n  }\n  return false;\n}\n\nint main(int argc, char** argv) {\n  srand(1337);\n\n  cl_device_id device_id;\n  cl_context context;\n  cl_init(device_id, context)\t;\n\n  int err;\n  const cl_queue_properties props[] = {0}; //CL_QUEUE_PRIORITY_KHR, CL_QUEUE_PRIORITY_HIGH_KHR, 0};\n  cl_command_queue q = clCreateCommandQueueWithProperties(context, device_id, props, &err);\n  if(err != 0) {\n    std::cout << \"clCreateCommandQueueWithProperties error: \" << err << std::endl;\n  }\n\n  int width = 1164;\n  int height = 874;\n\n  int opt = 0;\n  while ((opt = getopt(argc, argv, \"f\")) != -1)\n    {\n      switch (opt)\n        {\n        case 'f':\n          std::cout << \"Using front camera dimensions\" << std::endl;\n          int width = 1152;\n          int height = 846;\n        }\n  }\n\n  std::cout << \"Width: \" << width << \" Height: \" << height << std::endl;\n  uint8_t *rgb_frame = new uint8_t[width * height * 3];\n\n\n  RGBToYUVState rgb_to_yuv_state;\n  rgb_to_yuv_init(&rgb_to_yuv_state, context, device_id, width, height, width * 3);\n\n  int frame_yuv_buf_size = width * height * 3 / 2;\n  cl_mem yuv_cl = CL_CHECK_ERR(clCreateBuffer(context, CL_MEM_READ_WRITE, frame_yuv_buf_size, (void*)NULL, &err));\n  uint8_t *frame_yuv_buf = new uint8_t[frame_yuv_buf_size];\n  uint8_t *frame_yuv_ptr_y = frame_yuv_buf;\n  uint8_t *frame_yuv_ptr_u = frame_yuv_buf + (width * height);\n  uint8_t *frame_yuv_ptr_v = frame_yuv_ptr_u + ((width/2) * (height/2));\n\n  cl_mem rgb_cl = CL_CHECK_ERR(clCreateBuffer(context, CL_MEM_READ_WRITE, width * height * 3, (void*)NULL, &err));\n  int mismatched = 0;\n  int counter = 0;\n  srand (time(NULL));\n\n  for (int i = 0; i < 100; i++) {\n    for (int i = 0; i < width * height * 3; i++) {\n      rgb_frame[i] = (uint8_t)rand();\n    }\n\n    double t1 = millis_since_boot();\n    libyuv::RGB24ToI420((uint8_t*)rgb_frame, width * 3,\n                        frame_yuv_ptr_y, width,\n                        frame_yuv_ptr_u, width/2,\n                        frame_yuv_ptr_v, width/2,\n                        width, height);\n    double t2 = millis_since_boot();\n    //printf(\"Libyuv: rgb to yuv: %.2fms\\n\", t2-t1);\n\n    clEnqueueWriteBuffer(q, rgb_cl, CL_TRUE, 0, width * height * 3, (void *)rgb_frame, 0, NULL, NULL);\n    t1 = millis_since_boot();\n    rgb_to_yuv_queue(&rgb_to_yuv_state, q, rgb_cl, yuv_cl);\n    t2 = millis_since_boot();\n\n    //printf(\"OpenCL: rgb to yuv: %.2fms\\n\", t2-t1);\n    uint8_t *yyy = (uint8_t *)clEnqueueMapBuffer(q, yuv_cl, CL_TRUE,\n                                                 CL_MAP_READ, 0, frame_yuv_buf_size,\n                                                 0, NULL, NULL, &err);\n    if(!compare_results(frame_yuv_ptr_y, yyy, frame_yuv_buf_size, width, width, height, (uint8_t*)rgb_frame))\n      mismatched++;\n    clEnqueueUnmapMemObject(q, yuv_cl, yyy, 0, NULL, NULL);\n\n    // std::this_thread::sleep_for(std::chrono::milliseconds(20));\n    if(counter++ % 100 == 0)\n      printf(\"Matched: %d, Mismatched: %d\\n\", counter - mismatched, mismatched);\n\n  }\n  printf(\"Matched: %d, Mismatched: %d\\n\", counter - mismatched, mismatched);\n\n  delete[] frame_yuv_buf;\n  rgb_to_yuv_destroy(&rgb_to_yuv_state);\n  clReleaseContext(context);\n  delete[] rgb_frame;\n\n  if (mismatched == 0)\n    return 0;\n  else\n    return -1;\n}\n"
  },
  {
    "path": "selfdrive/car/__init__.py",
    "content": "# functions common among cars\nfrom common.numpy_fast import clip\n\n# kg of standard extra cargo to count for drive, gas, etc...\nSTD_CARGO_KG = 136.\n\n\ndef gen_empty_fingerprint():\n  return {i: {} for i in range(0, 4)}\n\n\n# FIXME: hardcoding honda civic 2016 touring params so they can be used to\n# scale unknown params for other cars\nclass CivicParams:\n  MASS = 1326. + STD_CARGO_KG\n  WHEELBASE = 2.70\n  CENTER_TO_FRONT = WHEELBASE * 0.4\n  CENTER_TO_REAR = WHEELBASE - CENTER_TO_FRONT\n  ROTATIONAL_INERTIA = 2500\n  TIRE_STIFFNESS_FRONT = 192150\n  TIRE_STIFFNESS_REAR = 202500\n\n\n# TODO: get actual value, for now starting with reasonable value for\n# civic and scaling by mass and wheelbase\ndef scale_rot_inertia(mass, wheelbase):\n  return CivicParams.ROTATIONAL_INERTIA * mass * wheelbase ** 2 / (CivicParams.MASS * CivicParams.WHEELBASE ** 2)\n\n\n# TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n# mass and CG position, so all cars will have approximately similar dyn behaviors\ndef scale_tire_stiffness(mass, wheelbase, center_to_front, tire_stiffness_factor=1.0):\n  center_to_rear = wheelbase - center_to_front\n  tire_stiffness_front = (CivicParams.TIRE_STIFFNESS_FRONT * tire_stiffness_factor) * mass / CivicParams.MASS * \\\n                         (center_to_rear / wheelbase) / (CivicParams.CENTER_TO_REAR / CivicParams.WHEELBASE)\n\n  tire_stiffness_rear = (CivicParams.TIRE_STIFFNESS_REAR * tire_stiffness_factor) * mass / CivicParams.MASS * \\\n                        (center_to_front / wheelbase) / (CivicParams.CENTER_TO_FRONT / CivicParams.WHEELBASE)\n\n  return tire_stiffness_front, tire_stiffness_rear\n\n\ndef dbc_dict(pt_dbc, radar_dbc, chassis_dbc=None, body_dbc=None):\n  return {'pt': pt_dbc, 'radar': radar_dbc, 'chassis': chassis_dbc, 'body': body_dbc}\n\n\ndef apply_std_steer_torque_limits(apply_torque, apply_torque_last, driver_torque, LIMITS):\n\n  # limits due to driver torque\n  driver_max_torque = LIMITS.STEER_MAX + (LIMITS.STEER_DRIVER_ALLOWANCE + driver_torque * LIMITS.STEER_DRIVER_FACTOR) * LIMITS.STEER_DRIVER_MULTIPLIER\n  driver_min_torque = -LIMITS.STEER_MAX + (-LIMITS.STEER_DRIVER_ALLOWANCE + driver_torque * LIMITS.STEER_DRIVER_FACTOR) * LIMITS.STEER_DRIVER_MULTIPLIER\n  max_steer_allowed = max(min(LIMITS.STEER_MAX, driver_max_torque), 0)\n  min_steer_allowed = min(max(-LIMITS.STEER_MAX, driver_min_torque), 0)\n  apply_torque = clip(apply_torque, min_steer_allowed, max_steer_allowed)\n\n  # slow rate if steer torque increases in magnitude\n  if apply_torque_last > 0:\n    apply_torque = clip(apply_torque, max(apply_torque_last - LIMITS.STEER_DELTA_DOWN, -LIMITS.STEER_DELTA_UP),\n                        apply_torque_last + LIMITS.STEER_DELTA_UP)\n  else:\n    apply_torque = clip(apply_torque, apply_torque_last - LIMITS.STEER_DELTA_UP,\n                        min(apply_torque_last + LIMITS.STEER_DELTA_DOWN, LIMITS.STEER_DELTA_UP))\n\n  return int(round(float(apply_torque)))\n\n\ndef apply_toyota_steer_torque_limits(apply_torque, apply_torque_last, motor_torque, LIMITS):\n  # limits due to comparison of commanded torque VS motor reported torque\n  max_lim = min(max(motor_torque + LIMITS.STEER_ERROR_MAX, LIMITS.STEER_ERROR_MAX), LIMITS.STEER_MAX)\n  min_lim = max(min(motor_torque - LIMITS.STEER_ERROR_MAX, -LIMITS.STEER_ERROR_MAX), -LIMITS.STEER_MAX)\n\n  apply_torque = clip(apply_torque, min_lim, max_lim)\n\n  # slow rate if steer torque increases in magnitude\n  if apply_torque_last > 0:\n    apply_torque = clip(apply_torque,\n                        max(apply_torque_last - LIMITS.STEER_DELTA_DOWN, -LIMITS.STEER_DELTA_UP),\n                        apply_torque_last + LIMITS.STEER_DELTA_UP)\n  else:\n    apply_torque = clip(apply_torque,\n                        apply_torque_last - LIMITS.STEER_DELTA_UP,\n                        min(apply_torque_last + LIMITS.STEER_DELTA_DOWN, LIMITS.STEER_DELTA_UP))\n\n  return int(round(float(apply_torque)))\n\n\ndef crc8_pedal(data):\n  crc = 0xFF    # standard init value\n  poly = 0xD5   # standard crc8: x8+x7+x6+x4+x2+1\n  size = len(data)\n  for i in range(size - 1, -1, -1):\n    crc ^= data[i]\n    for _ in range(8):\n      if ((crc & 0x80) != 0):\n        crc = ((crc << 1) ^ poly) & 0xFF\n      else:\n        crc <<= 1\n  return crc\n\n\ndef create_gas_command(packer, gas_amount, idx):\n  # Common gas pedal msg generator\n  enable = gas_amount > 0.001\n\n  values = {\n    \"ENABLE\": enable,\n    \"COUNTER_PEDAL\": idx & 0xF,\n  }\n\n  if enable:\n    values[\"GAS_COMMAND\"] = gas_amount * 255.\n    values[\"GAS_COMMAND2\"] = gas_amount * 255.\n\n  dat = packer.make_can_msg(\"GAS_COMMAND\", 0, values)[2]\n\n  checksum = crc8_pedal(dat[:-1])\n  values[\"CHECKSUM_PEDAL\"] = checksum\n\n  return packer.make_can_msg(\"GAS_COMMAND\", 0, values)\n\n\ndef make_can_msg(addr, dat, bus):\n  return [addr, 0, dat, bus]\n"
  },
  {
    "path": "selfdrive/car/car_helpers.py",
    "content": "import os\nimport json\nimport threading\nimport requests\nfrom common.params import Params, put_nonblocking\nfrom common.basedir import BASEDIR\nfrom selfdrive.version import comma_remote, tested_branch\nfrom selfdrive.car.fingerprints import eliminate_incompatible_cars, all_legacy_fingerprint_cars\nfrom selfdrive.car.vin import get_vin, VIN_UNKNOWN\nfrom selfdrive.car.fw_versions import get_fw_versions, match_fw_to_car\nfrom selfdrive.swaglog import cloudlog\nimport cereal.messaging as messaging\nfrom selfdrive.car import gen_empty_fingerprint\nimport selfdrive.crash as crash\n\nfrom cereal import car\nEventName = car.CarEvent.EventName\n\n\ndef get_startup_event(car_recognized, controller_available, fuzzy_fingerprint, fw_seen):\n  if True:\n    event = EventName.startup\n  else:\n    event = EventName.startupMaster\n\n  if not car_recognized:\n    if fw_seen:\n      event = EventName.startupNoCar\n    else:\n      event = EventName.startupNoFw\n  elif car_recognized and not controller_available:\n    event = EventName.startupNoControl\n  elif car_recognized and fuzzy_fingerprint:\n    event = EventName.startupFuzzyFingerprint\n  return event\n\n\ndef get_one_can(logcan):\n  while True:\n    can = messaging.recv_one_retry(logcan)\n    if len(can.can) > 0:\n      return can\n\n\ndef load_interfaces(brand_names):\n  ret = {}\n  for brand_name in brand_names:\n    path = ('selfdrive.car.%s' % brand_name)\n    CarInterface = __import__(path + '.interface', fromlist=['CarInterface']).CarInterface\n\n    if os.path.exists(BASEDIR + '/' + path.replace('.', '/') + '/carstate.py'):\n      CarState = __import__(path + '.carstate', fromlist=['CarState']).CarState\n    else:\n      CarState = None\n\n    if os.path.exists(BASEDIR + '/' + path.replace('.', '/') + '/carcontroller.py'):\n      CarController = __import__(path + '.carcontroller', fromlist=['CarController']).CarController\n    else:\n      CarController = None\n\n    for model_name in brand_names[brand_name]:\n      ret[model_name] = (CarInterface, CarController, CarState)\n  return ret\n\n\ndef _get_interface_names():\n  # read all the folders in selfdrive/car and return a dict where:\n  # - keys are all the car names that which we have an interface for\n  # - values are lists of spefic car models for a given car\n  brand_names = {}\n  for car_folder in [x[0] for x in os.walk(BASEDIR + '/selfdrive/car')]:\n    try:\n      brand_name = car_folder.split('/')[-1]\n      model_names = __import__('selfdrive.car.%s.values' % brand_name, fromlist=['CAR']).CAR\n      model_names = [getattr(model_names, c) for c in model_names.__dict__.keys() if not c.startswith(\"__\")]\n      brand_names[brand_name] = model_names\n    except (ImportError, IOError):\n      pass\n\n  return brand_names\n\n\n# imports from directory selfdrive/car/<name>/\ninterface_names = _get_interface_names()\ninterfaces = load_interfaces(interface_names)\n\n\ndef only_toyota_left(candidate_cars):\n  return all((\"TOYOTA\" in c or \"LEXUS\" in c) for c in candidate_cars) and len(candidate_cars) > 0\n\n\n# **** for use live only ****\ndef fingerprint(logcan, sendcan):\n  dp_car_assigned = Params().get('dp_car_assigned', encoding='utf8')\n  fixed_fingerprint = os.environ.get('FINGERPRINT', \"\" if dp_car_assigned is None else dp_car_assigned)\n  skip_fw_query = os.environ.get('SKIP_FW_QUERY', False)\n\n  if not fixed_fingerprint and not skip_fw_query:\n    # Vin query only reliably works thorugh OBDII\n    bus = 1\n\n    cached_params = Params().get(\"CarParamsCache\")\n    if cached_params is not None:\n      cached_params = car.CarParams.from_bytes(cached_params)\n      if cached_params.carName == \"mock\":\n        cached_params = None\n\n    if cached_params is not None and len(cached_params.carFw) > 0 and cached_params.carVin is not VIN_UNKNOWN:\n      cloudlog.warning(\"Using cached CarParams\")\n      vin = cached_params.carVin\n      car_fw = list(cached_params.carFw)\n    else:\n      cloudlog.warning(\"Getting VIN & FW versions\")\n      _, vin = get_vin(logcan, sendcan, bus)\n      car_fw = get_fw_versions(logcan, sendcan, bus)\n\n    exact_fw_match, fw_candidates = match_fw_to_car(car_fw)\n  else:\n    vin = VIN_UNKNOWN\n    exact_fw_match, fw_candidates, car_fw = True, set(), []\n\n  cloudlog.warning(\"VIN %s\", vin)\n  Params().put(\"CarVin\", vin)\n\n  finger = gen_empty_fingerprint()\n  candidate_cars = {i: all_legacy_fingerprint_cars() for i in [0, 1]}  # attempt fingerprint on both bus 0 and 1\n  frame = 0\n  frame_fingerprint = 10  # 0.1s\n  car_fingerprint = None\n  done = False\n\n  while not done:\n    a = get_one_can(logcan)\n\n    for can in a.can:\n      # need to independently try to fingerprint both bus 0 and 1 to work\n      # for the combo black_panda and honda_bosch. Ignore extended messages\n      # and VIN query response.\n      # Include bus 2 for toyotas to disambiguate cars using camera messages\n      # (ideally should be done for all cars but we can't for Honda Bosch)\n      if can.src in range(0, 4):\n        finger[can.src][can.address] = len(can.dat)\n      for b in candidate_cars:\n        if (can.src == b or (only_toyota_left(candidate_cars[b]) and can.src == 2)) and \\\n           can.address < 0x800 and can.address not in [0x7df, 0x7e0, 0x7e8]:\n          candidate_cars[b] = eliminate_incompatible_cars(can, candidate_cars[b])\n\n    # if we only have one car choice and the time since we got our first\n    # message has elapsed, exit\n    for b in candidate_cars:\n      # Toyota needs higher time to fingerprint, since DSU does not broadcast immediately\n      if only_toyota_left(candidate_cars[b]):\n        frame_fingerprint = 100  # 1s\n      if len(candidate_cars[b]) == 1 and frame > frame_fingerprint:\n          # fingerprint done\n          car_fingerprint = candidate_cars[b][0]\n\n    # bail if no cars left or we've been waiting for more than 2s\n    failed = (all(len(cc) == 0 for cc in candidate_cars.values()) and frame > frame_fingerprint) or frame > 200\n    succeeded = car_fingerprint is not None\n    done = failed or succeeded\n\n    frame += 1\n\n  exact_match = True\n  source = car.CarParams.FingerprintSource.can\n\n  # If FW query returns exactly 1 candidate, use it\n  if len(fw_candidates) == 1:\n    car_fingerprint = list(fw_candidates)[0]\n    source = car.CarParams.FingerprintSource.fw\n    exact_match = exact_fw_match\n\n  if fixed_fingerprint:\n    car_fingerprint = fixed_fingerprint\n    source = car.CarParams.FingerprintSource.fixed\n\n  cloudlog.event(\"fingerprinted\", car_fingerprint=car_fingerprint,\n                 source=source, fuzzy=not exact_match, fw_count=len(car_fw))\n  return car_fingerprint, finger, vin, car_fw, source, exact_match\n\ndef is_connected_to_internet(timeout=5):\n    try:\n        requests.get(\"https://sentry.io\", timeout=timeout)\n        return True\n    except Exception:\n        return False\n\ndef crash_log(candidate):\n  while True:\n    if is_connected_to_internet():\n      crash.capture_warning(\"fingerprinted %s\" % candidate)\n      break\n\ndef crash_log2(fingerprints, fw):\n  while True:\n    if is_connected_to_internet():\n      crash.capture_warning(\"car doesn't match any fingerprints: %s\" % fingerprints)\n      crash.capture_warning(\"car doesn't match any fw: %s\" % fw)\n      break\n\ndef get_car(logcan, sendcan):\n  candidate, fingerprints, vin, car_fw, source, exact_match = fingerprint(logcan, sendcan)\n\n  if candidate is None:\n    cloudlog.warning(\"car doesn't match any fingerprints: %r\", fingerprints)\n    candidate = \"mock\"\n    y = threading.Thread(target=crash_log2, args=(fingerprints,car_fw,))\n    y.start()\n\n  x = threading.Thread(target=crash_log, args=(candidate,))\n  x.start()\n\n  try:\n    CarInterface, CarController, CarState = interfaces[candidate]\n    car_params = CarInterface.get_params(candidate, fingerprints, car_fw)\n    candidate_changed = Params().get('dp_last_candidate', encoding='utf8') != candidate\n    put_nonblocking(\"dp_sr_stock\", str(car_params.steerRatio))\n    # update steering_ratio init val\n    dp_sr_custom = Params().get(\"dp_sr_custom\", encoding='utf8')\n    if dp_sr_custom == '' or candidate_changed or (dp_sr_custom != '' and float(dp_sr_custom) <= 9.99):\n      put_nonblocking(\"dp_sr_custom\", str(car_params.steerRatio))\n    # update last candidate\n    put_nonblocking('dp_last_candidate', candidate)\n    car_params.carVin = vin\n    car_params.carFw = car_fw\n    car_params.fingerprintSource = source\n    car_params.fuzzyFingerprint = not exact_match\n\n    return CarInterface(car_params, CarController, CarState), car_params\n  except KeyError:\n    put_nonblocking(\"dp_last_candidate\", '')\n    put_nonblocking(\"dp_car_assigned\", '')\n    put_nonblocking(\"dp_sr_custom\", '9.99')\n    put_nonblocking(\"dp_sr_stock\", '9.99')\n    return None, None\n"
  },
  {
    "path": "selfdrive/car/chrysler/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/chrysler/carcontroller.py",
    "content": "from selfdrive.car import apply_toyota_steer_torque_limits\nfrom selfdrive.car.chrysler.chryslercan import create_lkas_hud, create_lkas_command, \\\n                                               create_wheel_buttons\nfrom selfdrive.car.chrysler.values import CAR, CarControllerParams\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.apply_steer_last = 0\n    self.ccframe = 0\n    self.prev_frame = -1\n    self.hud_count = 0\n    self.car_fingerprint = CP.carFingerprint\n    self.gone_fast_yet = False\n    self.steer_rate_limited = False\n\n    self.packer = CANPacker(dbc_name)\n\n  def update(self, enabled, CS, actuators, pcm_cancel_cmd, hud_alert, dragonconf):\n    # this seems needed to avoid steering faults and to force the sync with the EPS counter\n    frame = CS.lkas_counter\n    if self.prev_frame == frame:\n      return []\n\n    # *** compute control surfaces ***\n    # steer torque\n    new_steer = int(round(actuators.steer * CarControllerParams.STEER_MAX))\n    apply_steer = apply_toyota_steer_torque_limits(new_steer, self.apply_steer_last,\n                                                   CS.out.steeringTorqueEps, CarControllerParams)\n    self.steer_rate_limited = new_steer != apply_steer\n\n    moving_fast = CS.out.vEgo > CS.CP.minSteerSpeed  # for status message\n    if CS.out.vEgo > (CS.CP.minSteerSpeed - 0.5):  # for command high bit\n      self.gone_fast_yet = True\n    elif self.car_fingerprint in (CAR.PACIFICA_2019_HYBRID, CAR.PACIFICA_2020, CAR.JEEP_CHEROKEE_2019):\n      if CS.out.vEgo < (CS.CP.minSteerSpeed - 3.0):\n        self.gone_fast_yet = False  # < 14.5m/s stock turns off this bit, but fine down to 13.5\n    lkas_active = moving_fast and enabled\n\n    if not lkas_active:\n      apply_steer = 0\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_steer = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_steer, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    self.apply_steer_last = apply_steer\n\n    can_sends = []\n\n    #*** control msgs ***\n\n    if pcm_cancel_cmd:\n      # TODO: would be better to start from frame_2b3\n      new_msg = create_wheel_buttons(self.packer, self.ccframe, cancel=True)\n      can_sends.append(new_msg)\n\n    # LKAS_HEARTBIT is forwarded by Panda so no need to send it here.\n    # frame is 100Hz (0.01s period)\n    if (self.ccframe % 25 == 0):  # 0.25s period\n      if (CS.lkas_car_model != -1):\n        new_msg = create_lkas_hud(\n            self.packer, CS.out.gearShifter, lkas_active, hud_alert,\n            self.hud_count, CS.lkas_car_model)\n        can_sends.append(new_msg)\n        self.hud_count += 1\n\n    new_msg = create_lkas_command(self.packer, int(apply_steer), self.gone_fast_yet, frame)\n    can_sends.append(new_msg)\n\n    self.ccframe += 1\n    self.prev_frame = frame\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/chrysler/carstate.py",
    "content": "from cereal import car\nfrom opendbc.can.parser import CANParser\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import CarStateBase\nfrom selfdrive.car.chrysler.values import DBC, STEER_THRESHOLD\n\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n    self.shifter_values = can_define.dv[\"GEAR\"][\"PRNDL\"]\n\n  def update(self, cp, cp_cam):\n\n    ret = car.CarState.new_message()\n\n    self.frame = int(cp.vl[\"EPS_STATUS\"][\"COUNTER\"])\n\n    ret.doorOpen = any([cp.vl[\"DOORS\"][\"DOOR_OPEN_FL\"],\n                        cp.vl[\"DOORS\"][\"DOOR_OPEN_FR\"],\n                        cp.vl[\"DOORS\"][\"DOOR_OPEN_RL\"],\n                        cp.vl[\"DOORS\"][\"DOOR_OPEN_RR\"]])\n    ret.seatbeltUnlatched = cp.vl[\"SEATBELT_STATUS\"][\"SEATBELT_DRIVER_UNLATCHED\"] == 1\n\n    ret.brakePressed = cp.vl[\"BRAKE_2\"][\"BRAKE_PRESSED_2\"] == 5  # human-only\n    ret.brake = 0\n    ret.gas = cp.vl[\"ACCEL_GAS_134\"][\"ACCEL_134\"]\n    ret.gasPressed = ret.gas > 1e-5\n\n    ret.espDisabled = (cp.vl[\"TRACTION_BUTTON\"][\"TRACTION_OFF\"] == 1)\n\n    ret.wheelSpeeds.fl = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_FL\"]\n    ret.wheelSpeeds.rr = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_RR\"]\n    ret.wheelSpeeds.rl = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_RL\"]\n    ret.wheelSpeeds.fr = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_FR\"]\n    ret.vEgoRaw = (cp.vl[\"SPEED_1\"][\"SPEED_LEFT\"] + cp.vl[\"SPEED_1\"][\"SPEED_RIGHT\"]) / 2.\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n    ret.standstill = not ret.vEgoRaw > 0.001\n\n    ret.leftBlinker = cp.vl[\"STEERING_LEVERS\"][\"TURN_SIGNALS\"] == 1\n    ret.rightBlinker = cp.vl[\"STEERING_LEVERS\"][\"TURN_SIGNALS\"] == 2\n    ret.steeringAngleDeg = cp.vl[\"STEERING\"][\"STEER_ANGLE\"]\n    ret.steeringRateDeg = cp.vl[\"STEERING\"][\"STEERING_RATE\"]\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(cp.vl[\"GEAR\"][\"PRNDL\"], None))\n\n    ret.cruiseState.enabled = cp.vl[\"ACC_2\"][\"ACC_STATUS_2\"] == 7  # ACC is green.\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    ret.cruiseState.available = ret.cruiseState.enabled  # FIXME: for now same as enabled\n    ret.cruiseState.speed = cp.vl[\"DASHBOARD\"][\"ACC_SPEED_CONFIG_KPH\"] * CV.KPH_TO_MS\n    # CRUISE_STATE is a three bit msg, 0 is off, 1 and 2 are Non-ACC mode, 3 and 4 are ACC mode, find if there are other states too\n    ret.cruiseState.nonAdaptive = cp.vl[\"DASHBOARD\"][\"CRUISE_STATE\"] in [1, 2]\n\n    ret.steeringTorque = cp.vl[\"EPS_STATUS\"][\"TORQUE_DRIVER\"]\n    ret.steeringTorqueEps = cp.vl[\"EPS_STATUS\"][\"TORQUE_MOTOR\"]\n    ret.steeringPressed = abs(ret.steeringTorque) > STEER_THRESHOLD\n    steer_state = cp.vl[\"EPS_STATUS\"][\"LKAS_STATE\"]\n    ret.steerError = steer_state == 4 or (steer_state == 0 and ret.vEgo > self.CP.minSteerSpeed)\n\n    ret.genericToggle = bool(cp.vl[\"STEERING_LEVERS\"][\"HIGH_BEAM_FLASH\"])\n\n    if self.CP.enableBsm:\n      ret.leftBlindspot = cp.vl[\"BLIND_SPOT_WARNINGS\"][\"BLIND_SPOT_LEFT\"] == 1\n      ret.rightBlindspot = cp.vl[\"BLIND_SPOT_WARNINGS\"][\"BLIND_SPOT_RIGHT\"] == 1\n\n    self.lkas_counter = cp_cam.vl[\"LKAS_COMMAND\"][\"COUNTER\"]\n    self.lkas_car_model = cp_cam.vl[\"LKAS_HUD\"][\"CAR_MODEL\"]\n    self.lkas_status_ok = cp_cam.vl[\"LKAS_HEARTBIT\"][\"LKAS_STATUS_OK\"]\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    signals = [\n      # sig_name, sig_address, default\n      (\"PRNDL\", \"GEAR\", 0),\n      (\"DOOR_OPEN_FL\", \"DOORS\", 0),\n      (\"DOOR_OPEN_FR\", \"DOORS\", 0),\n      (\"DOOR_OPEN_RL\", \"DOORS\", 0),\n      (\"DOOR_OPEN_RR\", \"DOORS\", 0),\n      (\"BRAKE_PRESSED_2\", \"BRAKE_2\", 0),\n      (\"ACCEL_134\", \"ACCEL_GAS_134\", 0),\n      (\"SPEED_LEFT\", \"SPEED_1\", 0),\n      (\"SPEED_RIGHT\", \"SPEED_1\", 0),\n      (\"WHEEL_SPEED_FL\", \"WHEEL_SPEEDS\", 0),\n      (\"WHEEL_SPEED_RR\", \"WHEEL_SPEEDS\", 0),\n      (\"WHEEL_SPEED_RL\", \"WHEEL_SPEEDS\", 0),\n      (\"WHEEL_SPEED_FR\", \"WHEEL_SPEEDS\", 0),\n      (\"STEER_ANGLE\", \"STEERING\", 0),\n      (\"STEERING_RATE\", \"STEERING\", 0),\n      (\"TURN_SIGNALS\", \"STEERING_LEVERS\", 0),\n      (\"ACC_STATUS_2\", \"ACC_2\", 0),\n      (\"HIGH_BEAM_FLASH\", \"STEERING_LEVERS\", 0),\n      (\"ACC_SPEED_CONFIG_KPH\", \"DASHBOARD\", 0),\n      (\"CRUISE_STATE\", \"DASHBOARD\", 0),\n      (\"TORQUE_DRIVER\", \"EPS_STATUS\", 0),\n      (\"TORQUE_MOTOR\", \"EPS_STATUS\", 0),\n      (\"LKAS_STATE\", \"EPS_STATUS\", 1),\n      (\"COUNTER\", \"EPS_STATUS\", -1),\n      (\"TRACTION_OFF\", \"TRACTION_BUTTON\", 0),\n      (\"SEATBELT_DRIVER_UNLATCHED\", \"SEATBELT_STATUS\", 0),\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"BRAKE_2\", 50),\n      (\"EPS_STATUS\", 100),\n      (\"SPEED_1\", 100),\n      (\"WHEEL_SPEEDS\", 50),\n      (\"STEERING\", 100),\n      (\"ACC_2\", 50),\n      (\"GEAR\", 50),\n      (\"ACCEL_GAS_134\", 50),\n      (\"DASHBOARD\", 15),\n      (\"STEERING_LEVERS\", 10),\n      (\"SEATBELT_STATUS\", 2),\n      (\"DOORS\", 1),\n      (\"TRACTION_BUTTON\", 1),\n    ]\n\n    if CP.enableBsm:\n      signals += [\n        (\"BLIND_SPOT_RIGHT\", \"BLIND_SPOT_WARNINGS\", 0),\n        (\"BLIND_SPOT_LEFT\", \"BLIND_SPOT_WARNINGS\", 0),\n      ]\n      checks += [(\"BLIND_SPOT_WARNINGS\", 2)]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    signals = [\n      # sig_name, sig_address, default\n      (\"COUNTER\", \"LKAS_COMMAND\", -1),\n      (\"CAR_MODEL\", \"LKAS_HUD\", -1),\n      (\"LKAS_STATUS_OK\", \"LKAS_HEARTBIT\", -1)\n    ]\n    checks = [\n      (\"LKAS_COMMAND\", 100),\n      (\"LKAS_HEARTBIT\", 10),\n      (\"LKAS_HUD\", 4),\n    ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n"
  },
  {
    "path": "selfdrive/car/chrysler/chryslercan.py",
    "content": "from cereal import car\nfrom selfdrive.car import make_can_msg\n\n\nGearShifter = car.CarState.GearShifter\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\ndef create_lkas_hud(packer, gear, lkas_active, hud_alert, hud_count, lkas_car_model):\n  # LKAS_HUD 0x2a6 (678) Controls what lane-keeping icon is displayed.\n\n  if hud_alert in [VisualAlert.steerRequired, VisualAlert.ldw]:\n    msg = b'\\x00\\x00\\x00\\x03\\x00\\x00\\x00\\x00'\n    return make_can_msg(0x2a6, msg, 0)\n\n  color = 1  # default values are for park or neutral in 2017 are 0 0, but trying 1 1 for 2019\n  lines = 1\n  alerts = 0\n\n  if hud_count < (1 * 4):  # first 3 seconds, 4Hz\n    alerts = 1\n  # CAR.PACIFICA_2018_HYBRID and CAR.PACIFICA_2019_HYBRID\n  # had color = 1 and lines = 1 but trying 2017 hybrid style for now.\n  if gear in (GearShifter.drive, GearShifter.reverse, GearShifter.low):\n    if lkas_active:\n      color = 2  # control active, display green.\n      lines = 6\n    else:\n      color = 1  # control off, display white.\n      lines = 1\n\n  values = {\n    \"LKAS_ICON_COLOR\": color,  # byte 0, last 2 bits\n    \"CAR_MODEL\": lkas_car_model,  # byte 1\n    \"LKAS_LANE_LINES\": lines,  # byte 2, last 4 bits\n    \"LKAS_ALERTS\": alerts,  # byte 3, last 4 bits\n    }\n\n  return packer.make_can_msg(\"LKAS_HUD\", 0, values)  # 0x2a6\n\n\ndef create_lkas_command(packer, apply_steer, moving_fast, frame):\n  # LKAS_COMMAND 0x292 (658) Lane-keeping signal to turn the wheel.\n  values = {\n    \"LKAS_STEERING_TORQUE\": apply_steer,\n    \"LKAS_HIGH_TORQUE\": int(moving_fast),\n    \"COUNTER\": frame % 0x10,\n  }\n  return packer.make_can_msg(\"LKAS_COMMAND\", 0, values)\n\n\ndef create_wheel_buttons(packer, frame, cancel=False):\n  # WHEEL_BUTTONS (571) Message sent to cancel ACC.\n  values = {\n    \"ACC_CANCEL\": cancel,\n    \"COUNTER\": frame % 10\n  }\n  return packer.make_can_msg(\"WHEEL_BUTTONS\", 0, values)\n"
  },
  {
    "path": "selfdrive/car/chrysler/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.car.chrysler.values import CAR\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\nclass CarInterface(CarInterfaceBase):\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"chrysler\"\n    ret.safetyModel = car.CarParams.SafetyModel.chrysler\n    ret.lateralTuning.init('pid')\n\n    # Chrysler port is a community feature, since we don't own one to test\n    ret.communityFeature = True\n\n    # Speed conversion:              20, 45 mph\n    ret.wheelbase = 3.089  # in meters for Pacifica Hybrid 2017\n    ret.steerRatio = 16.2  # Pacifica Hybrid 2017\n    ret.mass = 2242. + STD_CARGO_KG  # kg curb weight Pacifica Hybrid 2017\n    ret.lateralTuning.pid.kpBP, ret.lateralTuning.pid.kiBP = [[9., 20.], [9., 20.]]\n    ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.15, 0.30], [0.03, 0.05]]\n    ret.lateralTuning.pid.kf = 0.00006   # full torque for 10 deg at 80mph means 0.00007818594\n    ret.steerActuatorDelay = 0.1\n    ret.steerRateCost = 0.7\n    ret.steerLimitTimer = 0.4\n\n    if candidate in (CAR.JEEP_CHEROKEE, CAR.JEEP_CHEROKEE_2019):\n      ret.wheelbase = 2.91  # in meters\n      ret.steerRatio = 12.7\n      ret.steerActuatorDelay = 0.2  # in seconds\n\n    ret.centerToFront = ret.wheelbase * 0.44\n\n    ret.minSteerSpeed = 3.8  # m/s\n    if candidate in (CAR.PACIFICA_2019_HYBRID, CAR.PACIFICA_2020, CAR.JEEP_CHEROKEE_2019):\n      # TODO allow 2019 cars to steer down to 13 m/s if already engaged.\n      ret.minSteerSpeed = 17.5  # m/s 17 on the way up, 13 on the way down once engaged.\n\n    # starting with reasonable value for civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront)\n\n    ret.enableBsm = 720 in fingerprint[0]\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    # ******************* do can recv *******************\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n\n    # speeds\n    ret.steeringRateLimited = self.CC.steer_rate_limited if self.CC is not None else False\n\n    # events\n    events = self.create_common_events(ret, extra_gears=[car.CarState.GearShifter.low],\n                                       gas_resume_speed=2.)\n\n    if ret.vEgo < self.CP.minSteerSpeed:\n      events.add(car.CarEvent.EventName.belowSteerSpeed)\n\n    ret.events = events.to_msg()\n\n    # copy back carState packet to CS\n    self.CS.out = ret.as_reader()\n\n    return self.CS.out\n\n  # pass in a car.CarControl\n  # to be called @ 100hz\n  def apply(self, c):\n\n    if (self.CS.frame == -1):\n      return []  # if we haven't seen a frame 220, then do not update.\n\n    can_sends = self.CC.update(c.enabled, self.CS, c.actuators, c.cruiseControl.cancel, c.hudControl.visualAlert, self.dragonconf)\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/chrysler/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom opendbc.can.parser import CANParser\nfrom cereal import car\nfrom selfdrive.car.interfaces import RadarInterfaceBase\nfrom selfdrive.car.chrysler.values import DBC\n\nRADAR_MSGS_C = list(range(0x2c2, 0x2d4+2, 2))  # c_ messages 706,...,724\nRADAR_MSGS_D = list(range(0x2a2, 0x2b4+2, 2))  # d_ messages\nLAST_MSG = max(RADAR_MSGS_C + RADAR_MSGS_D)\nNUMBER_MSGS = len(RADAR_MSGS_C) + len(RADAR_MSGS_D)\n\ndef _create_radar_can_parser(car_fingerprint):\n  msg_n = len(RADAR_MSGS_C)\n  # list of [(signal name, message name or number, initial values), (...)]\n  # [('RADAR_STATE', 1024, 0),\n  #  ('LONG_DIST', 1072, 255),\n  #  ('LONG_DIST', 1073, 255),\n  #  ('LONG_DIST', 1074, 255),\n  #  ('LONG_DIST', 1075, 255),\n\n  # The factor and offset are applied by the dbc parsing library, so the\n  # default values should be after the factor/offset are applied.\n  signals = list(zip(['LONG_DIST'] * msg_n +\n                ['LAT_DIST'] * msg_n +\n                ['REL_SPEED'] * msg_n,\n                RADAR_MSGS_C * 2 +  # LONG_DIST, LAT_DIST\n                RADAR_MSGS_D,    # REL_SPEED\n                [0] * msg_n +  # LONG_DIST\n                [-1000] * msg_n +    # LAT_DIST\n                [-146.278] * msg_n))  # REL_SPEED set to 0, factor/offset to this\n  # TODO what are the checks actually used for?\n  # honda only checks the last message,\n  # toyota checks all the messages. Which do we want?\n  checks = list(zip(RADAR_MSGS_C +\n               RADAR_MSGS_D,\n               [20]*msg_n +  # 20Hz (0.05s)\n               [20]*msg_n))  # 20Hz (0.05s)\n\n  return CANParser(DBC[car_fingerprint]['radar'], signals, checks, 1)\n\ndef _address_to_track(address):\n  if address in RADAR_MSGS_C:\n    return (address - RADAR_MSGS_C[0]) // 2\n  if address in RADAR_MSGS_D:\n    return (address - RADAR_MSGS_D[0]) // 2\n  raise ValueError(\"radar received unexpected address %d\" % address)\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.rcp = _create_radar_can_parser(CP.carFingerprint)\n    self.updated_messages = set()\n    self.trigger_msg = LAST_MSG\n\n  def update(self, can_strings):\n    vls = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(vls)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    ret = car.RadarData.new_message()\n    errors = []\n    if not self.rcp.can_valid:\n      errors.append(\"canError\")\n    ret.errors = errors\n\n    for ii in self.updated_messages:  # ii should be the message ID as a number\n      cpt = self.rcp.vl[ii]\n      trackId = _address_to_track(ii)\n\n      if trackId not in self.pts:\n        self.pts[trackId] = car.RadarData.RadarPoint.new_message()\n        self.pts[trackId].trackId = trackId\n        self.pts[trackId].aRel = float('nan')\n        self.pts[trackId].yvRel = float('nan')\n        self.pts[trackId].measured = True\n\n      if 'LONG_DIST' in cpt:  # c_* message\n        self.pts[trackId].dRel = cpt['LONG_DIST']  # from front of car\n        # our lat_dist is positive to the right in car's frame.\n        # TODO what does yRel want?\n        self.pts[trackId].yRel = cpt['LAT_DIST']  # in car frame's y axis, left is positive\n      else:  # d_* message\n        self.pts[trackId].vRel = cpt['REL_SPEED']\n\n    # We want a list, not a dictionary. Filter out LONG_DIST==0 because that means it's not valid.\n    ret.points = [x for x in self.pts.values() if x.dRel != 0]\n\n    self.updated_messages.clear()\n    return ret\n"
  },
  {
    "path": "selfdrive/car/chrysler/values.py",
    "content": "# flake8: noqa\n\nfrom selfdrive.car import dbc_dict\nfrom cereal import car\nEcu = car.CarParams.Ecu\n\nclass CarControllerParams:\n  STEER_MAX = 261         # 262 faults\n  STEER_DELTA_UP = 3      # 3 is stock. 100 is fine. 200 is too much it seems\n  STEER_DELTA_DOWN = 3    # no faults on the way down it seems\n  STEER_ERROR_MAX = 80\n\n\nclass CAR:\n  PACIFICA_2017_HYBRID = \"CHRYSLER PACIFICA HYBRID 2017\"\n  PACIFICA_2018_HYBRID = \"CHRYSLER PACIFICA HYBRID 2018\"\n  PACIFICA_2019_HYBRID = \"CHRYSLER PACIFICA HYBRID 2019\"\n  PACIFICA_2018 = \"CHRYSLER PACIFICA 2018\"  # includes 2017 Pacifica\n  PACIFICA_2020 = \"CHRYSLER PACIFICA 2020\"\n  JEEP_CHEROKEE = \"JEEP GRAND CHEROKEE V6 2018\"  # includes 2017 Trailhawk\n  JEEP_CHEROKEE_2019 = \"JEEP GRAND CHEROKEE 2019\" # includes 2020 Trailhawk\n\n# Unique CAN messages:\n# Only the hybrids have 270: 8\n# Only the gas have 55: 8, 416: 7\n# For 564, All 2017 have length 4, whereas 2018-19 have length 8.\n# For 924, Pacifica 2017 has length 3, whereas all 2018-19 have length 8.\n# For 560, All 2019 have length 8, whereas all 2017-18 have length 4.\n\n# Jeep Grand Cherokee unique messages:\n# 2017 Trailhawk: 618: 8\n# For 924, Trailhawk 2017 has length 3, whereas 2018 V6 has length 8.\n\nFINGERPRINTS = {\n  CAR.PACIFICA_2017_HYBRID: [{\n    168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 515: 7, 516: 7, 517: 7, 518: 7, 520: 8, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 4, 564: 4, 571: 3, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 701: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 746: 5, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 788:3, 792: 8, 799: 8, 800: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 908: 8, 924: 3, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 956: 8, 958: 8, 959: 8, 969: 4, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1216: 8, 1218: 8, 1220: 8, 1225: 8, 1235: 8, 1242: 8, 1246: 8, 1250: 8, 1284: 8, 1537: 8, 1538: 8, 1562: 8, 1568: 8, 1856: 8, 1858: 8, 1860: 8, 1865: 8, 1875: 8, 1882: 8, 1886: 8, 1890: 8, 1892: 8, 2016: 8, 2024: 8\n  }],\n  CAR.PACIFICA_2018: [{\n    55: 8, 257: 5, 258: 8, 264: 8, 268: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 416: 7, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 516: 7, 517: 7, 520: 8, 524: 8, 526: 6, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 4, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 656: 4, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 746: 5, 752: 2, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 882: 8, 897: 8, 924: 8, 926: 3, 937: 8, 947: 8, 948: 8, 969: 4, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1098: 8, 1100: 8, 1537: 8, 1538: 8, 1562: 8\n  },\n  {\n    55: 8, 257: 5, 258: 8, 264: 8, 268: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 416: 7, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 516: 7, 517: 7, 520: 8, 524: 8, 526: 6, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 4, 564: 4, 571: 3, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 656: 4, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 746: 5, 752: 2, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 882: 8, 897: 8, 924: 3, 926: 3, 937: 8, 947: 8, 948: 8, 969: 4, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1098: 8, 1100: 8, 1537: 8, 1538: 8, 1562: 8\n  }],\n  CAR.PACIFICA_2020: [{\n    55: 8, 179: 8, 181: 8, 257: 5, 258: 8, 264: 8, 268: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 352: 8, 362: 8, 368: 8, 376: 3, 384: 8, 388: 4, 416: 7, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 516: 7, 517: 7, 520: 8, 524: 8, 526: 6, 528: 8, 532: 8, 536: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 650: 8, 656: 4, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 676: 8, 678: 8, 680: 8, 683: 8, 703: 8, 705: 8, 706: 8, 709: 8, 710: 8, 711: 8, 719: 8, 720: 6, 729: 5, 736: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 776: 8, 779: 8, 782: 8, 784: 8, 792: 8, 793: 8, 794: 8, 795: 8, 799: 8, 800: 8, 801: 8, 802: 8, 803: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 847: 1, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 882: 8, 886: 8, 897: 8, 906: 8, 924: 8, 926: 3, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1098: 8, 1100: 8, 1216: 8, 1218: 8, 1220: 8, 1223: 7, 1225: 8, 1227: 8, 1235: 8, 1242: 8, 1246: 8, 1250: 8, 1251: 8, 1252: 8, 1284: 8, 1543: 8, 1568: 8, 1570: 8, 1856: 8, 1858: 8, 1860: 8, 1863: 8, 1865: 8, 1867: 8, 1875: 8, 1882: 8, 1886: 8, 1890: 8, 1891: 8, 1892: 8, 1898: 8, 2015: 8, 2016: 8, 2017:8, 2024: 8, 2025: 8\n  }],\n  CAR.PACIFICA_2018_HYBRID: [{\n    68: 8, 168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 520: 8, 528: 8, 532: 8, 544: 8, 557: 8, 559: 8, 560: 4, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 680: 8, 701: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 736: 8, 737: 8, 746: 5, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 969: 4, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8\n  },\n    # based on 9ae7821dc4e92455|2019-07-01--16-42-55\n  {\n    168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 515: 7, 516: 7, 517: 7, 518: 7, 520: 8, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 4, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 701: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 746: 5, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 969: 4, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1216: 8, 1218: 8, 1220: 8, 1225: 8, 1235: 8, 1242: 8, 1246: 8, 1250: 8, 1251: 8, 1252: 8, 1258: 8, 1259: 8, 1260: 8, 1262: 8, 1284: 8, 1537: 8, 1538: 8, 1562: 8, 1568: 8, 1856: 8, 1858: 8, 1860: 8, 1865: 8, 1875: 8, 1882: 8, 1886: 8, 1890: 8, 1891: 8, 1892: 8, 1898: 8, 1899: 8, 1900: 8, 1902: 8, 2016: 8, 2018: 8, 2019: 8, 2020: 8, 2023: 8, 2024: 8, 2026: 8, 2027: 8, 2028: 8, 2031: 8\n  }],\n  CAR.PACIFICA_2019_HYBRID: [{\n    168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 515: 7, 516: 7, 517: 7, 518: 7, 520: 8, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 680: 8, 701: 8, 703: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 736: 8, 737: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 906: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1538: 8\n  },\n    # Based on 0607d2516fc2148f|2019-02-13--23-03-16\n  {\n    168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 520: 8, 528: 8, 532: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 701: 8, 703: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 906: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1537: 8\n  },\n    # Based on 3c7ce223e3571b54|2019-05-11--20-16-14\n  {\n    168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 520: 8, 528: 8, 532: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 701: 8, 703: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 906: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1562: 8, 1570: 8\n  },\n    # Based on \"8190c7275a24557b|2020-02-24--09-57-23\"\n  {\n    168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 515: 7, 516: 7, 517: 7, 518: 7, 520: 8, 524: 8, 526: 6, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 640: 1, 650: 8, 653: 8, 654: 8, 655: 8, 656: 4, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 683: 8, 701: 8, 703: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 711: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 738: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 793: 8, 794: 8, 795: 8, 796: 8, 797: 8, 798: 8, 799: 8, 800: 8, 801: 8, 802: 8, 803: 8, 804: 8, 805: 8, 807: 8, 808: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 847: 1, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 886: 8, 897: 8, 906: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1216: 8, 1218: 8, 1220: 8, 1225: 8, 1235: 8, 1242: 8, 1246: 8, 1250: 8, 1251: 8, 1252: 8, 1258: 8, 1259: 8, 1260: 8, 1262: 8, 1284: 8, 1568: 8, 1570: 8, 1856: 8, 1858: 8, 1860: 8, 1863: 8, 1865: 8, 1875: 8, 1882: 8, 1886: 8, 1890: 8, 1891: 8, 1892: 8, 1898: 8, 1899: 8, 1900: 8, 1902: 8, 2015: 8, 2016: 8, 2017: 8, 2018: 8, 2019: 8, 2020: 8, 2023: 8, 2024: 8, 2026: 8, 2027: 8, 2028: 8, 2031: 8\n  }],\n  CAR.JEEP_CHEROKEE: [{\n    55: 8, 168: 8, 181: 8, 256: 4, 257: 5, 258: 8, 264: 8, 268: 8, 272: 6, 273: 6, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 292: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 352: 8, 362: 8, 368: 8, 376: 3, 384: 8, 388: 4, 416: 7, 448: 6, 456: 4, 464: 8, 500: 8, 501: 8, 512: 8, 514: 8, 520: 8, 532: 8, 544: 8, 557: 8, 559: 8, 560: 4, 564: 4, 571: 3, 579: 8, 584: 8, 608: 8, 618: 8, 624: 8, 625: 8, 632: 8, 639: 8, 656: 4, 658: 6, 660: 8, 671: 8, 672: 8, 676: 8, 678: 8, 680: 8, 683: 8, 684: 8, 703: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 738: 8, 746: 5, 752: 2, 754: 8, 760: 8, 761: 8, 764: 8, 766: 8, 773: 8, 776: 8, 779: 8, 782: 8, 783: 8, 784: 8, 785: 8, 788: 3, 792: 8, 799: 8, 800: 8, 804: 8, 806: 2, 808: 8, 810: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 831: 6, 832: 8, 838: 2, 840: 8, 844: 5, 847: 1, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 874: 2, 882: 8, 897: 8, 906: 8, 924: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 956: 8, 968: 8, 969: 4, 970: 8, 973: 8, 974: 5, 975: 8, 976: 8, 977: 4, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1062: 8, 1098: 8, 1100: 8, 1543: 8, 1562: 8, 2015: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n  }],\n  CAR.JEEP_CHEROKEE_2019: [{\n    # Jeep Grand Cherokee 2019, including most 2020 models\n    55: 8, 168: 8, 179: 8, 181: 8, 256: 4, 257: 5, 258: 8, 264: 8, 268: 8, 272: 6, 273: 6, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 292: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 341: 8, 344: 8, 352: 8, 362: 8, 368: 8, 376: 3, 384: 8, 388: 4, 416: 7, 448: 6, 456: 4, 464: 8, 500: 8, 501: 8, 512: 8, 514: 8, 520: 8, 530: 8, 532: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 618: 8, 624: 8, 625: 8, 632: 8, 639: 8, 640: 1, 656: 4, 658: 6, 660: 8, 671: 8, 672: 8, 676: 8, 678: 8, 680: 8, 683: 8, 684: 8, 703: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 738: 8, 746: 5, 752: 2, 754: 8, 760: 8, 761: 8, 764: 8, 766: 8, 773: 8, 776: 8, 779: 8, 782: 8, 783: 8, 784: 8, 785: 8, 792: 8, 799: 8, 800: 8, 804: 8, 806: 2, 808: 8, 810: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 831: 6, 832: 8, 838: 2, 840: 8, 844: 5, 847: 1, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 882: 8, 897: 8, 906: 8, 924: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 960: 4, 968: 8, 969: 4, 970: 8, 973: 8, 974: 5, 976: 8, 977: 4, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1062: 8, 1098: 8, 1100: 8, 1216: 8, 1218: 8, 1220: 8, 1223: 8, 1225: 8, 1227: 8, 1235: 8, 1242: 8, 1250: 8, 1251: 8, 1252: 8, 1254: 8, 1264: 8, 1284: 8, 1536: 8, 1537: 8, 1543: 8, 1545: 8, 1562: 8, 1568: 8, 1570: 8, 1572: 8, 1593: 8, 1856: 8, 1858: 8, 1860: 8, 1863: 8, 1865: 8, 1867: 8, 1875: 8, 1882: 8, 1890: 8, 1891: 8, 1892: 8, 1894: 8, 1896: 8, 1904: 8, 2015: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n  }],\n}\n\n\nDBC = {\n  CAR.PACIFICA_2017_HYBRID: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n  CAR.PACIFICA_2018: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n  CAR.PACIFICA_2020: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n  CAR.PACIFICA_2018_HYBRID: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n  CAR.PACIFICA_2019_HYBRID: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n  CAR.JEEP_CHEROKEE: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n  CAR.JEEP_CHEROKEE_2019: dbc_dict('chrysler_pacifica_2017_hybrid', 'chrysler_pacifica_2017_hybrid_private_fusion'),\n}\n\nSTEER_THRESHOLD = 120\n"
  },
  {
    "path": "selfdrive/car/fingerprints.py",
    "content": "import os\nfrom common.basedir import BASEDIR\n\n\ndef get_attr_from_cars(attr, result=dict, combine_brands=True):\n  # read all the folders in selfdrive/car and return a dict where:\n  # - keys are all the car models\n  # - values are attr values from all car folders\n  result = result()\n\n  for car_folder in [x[0] for x in os.walk(BASEDIR + '/selfdrive/car')]:\n    try:\n      car_name = car_folder.split('/')[-1]\n      values = __import__('selfdrive.car.%s.values' % car_name, fromlist=[attr])\n      if hasattr(values, attr):\n        attr_values = getattr(values, attr)\n      else:\n        continue\n\n      if isinstance(attr_values, dict):\n        for f, v in attr_values.items():\n          if combine_brands:\n            result[f] = v\n          else:\n            if car_name not in result:\n              result[car_name] = {}\n            result[car_name][f] = v\n      elif isinstance(attr_values, list):\n        result += attr_values\n\n    except (ImportError, IOError):\n      pass\n\n  return result\n\n\nFW_VERSIONS = get_attr_from_cars('FW_VERSIONS')\n_FINGERPRINTS = get_attr_from_cars('FINGERPRINTS')\n\n_DEBUG_ADDRESS = {1880: 8}   # reserved for debug purposes\n\ndef is_valid_for_fingerprint(msg, car_fingerprint):\n  adr = msg.address\n  # ignore addresses that are more than 11 bits\n  return (adr in car_fingerprint and car_fingerprint[adr] == len(msg.dat)) or adr >= 0x800\n\n\ndef eliminate_incompatible_cars(msg, candidate_cars):\n  \"\"\"Removes cars that could not have sent msg.\n\n     Inputs:\n      msg: A cereal/log CanData message from the car.\n      candidate_cars: A list of cars to consider.\n\n     Returns:\n      A list containing the subset of candidate_cars that could have sent msg.\n  \"\"\"\n  compatible_cars = []\n\n  for car_name in candidate_cars:\n    car_fingerprints = _FINGERPRINTS[car_name]\n\n    for fingerprint in car_fingerprints:\n      fingerprint.update(_DEBUG_ADDRESS)  # add alien debug address\n\n      if is_valid_for_fingerprint(msg, fingerprint):\n        compatible_cars.append(car_name)\n        break\n\n  return compatible_cars\n\n\ndef all_known_cars():\n  \"\"\"Returns a list of all known car strings.\"\"\"\n  return list({*FW_VERSIONS.keys(), *_FINGERPRINTS.keys()})\n\n\ndef all_legacy_fingerprint_cars():\n  \"\"\"Returns a list of all known car strings, FPv1 only.\"\"\"\n  return list(_FINGERPRINTS.keys())\n"
  },
  {
    "path": "selfdrive/car/ford/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/ford/carcontroller.py",
    "content": "import math\nfrom cereal import car\nfrom selfdrive.car import make_can_msg\nfrom selfdrive.car.ford.fordcan import create_steer_command, create_lkas_ui, spam_cancel_button\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\nMAX_STEER_DELTA = 1\nTOGGLE_DEBUG = False\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.packer = CANPacker(dbc_name)\n    self.enabled_last = False\n    self.main_on_last = False\n    self.vehicle_model = VM\n    self.generic_toggle_last = 0\n    self.steer_alert_last = False\n    self.lkas_action = 0\n\n  def update(self, enabled, CS, frame, actuators, visual_alert, pcm_cancel, dragonconf):\n\n    can_sends = []\n    steer_alert = visual_alert in [VisualAlert.steerRequired, VisualAlert.ldw]\n\n    apply_steer = actuators.steer\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_steer = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_steer, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    if pcm_cancel:\n      #print \"CANCELING!!!!\"\n      can_sends.append(spam_cancel_button(self.packer))\n\n    if (frame % 3) == 0:\n\n      curvature = self.vehicle_model.calc_curvature(actuators.steeringAngleDeg*math.pi/180., CS.out.vEgo)\n\n      # The use of the toggle below is handy for trying out the various LKAS modes\n      if TOGGLE_DEBUG:\n        self.lkas_action += int(CS.out.genericToggle and not self.generic_toggle_last)\n        self.lkas_action &= 0xf\n      else:\n        self.lkas_action = 5   # 4 and 5 seem the best. 8 and 9 seem to aggressive and laggy\n\n      can_sends.append(create_steer_command(self.packer, apply_steer, enabled,\n                                            CS.lkas_state, CS.out.steeringAngleDeg, curvature, self.lkas_action))\n      self.generic_toggle_last = CS.out.genericToggle\n\n    if (frame % 100) == 0:\n\n      can_sends.append(make_can_msg(973, b'\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00', 0))\n      #can_sends.append(make_can_msg(984, b'\\x00\\x00\\x00\\x00\\x80\\x45\\x60\\x30', 0))\n\n    if (frame % 100) == 0 or (self.enabled_last != enabled) or (self.main_on_last != CS.out.cruiseState.available) or \\\n       (self.steer_alert_last != steer_alert):\n      can_sends.append(create_lkas_ui(self.packer, CS.out.cruiseState.available, enabled, steer_alert))\n\n    if (frame % 200) == 0:\n      can_sends.append(make_can_msg(1875, b'\\x80\\xb0\\x55\\x55\\x78\\x90\\x00\\x00', 1))\n\n    if (frame % 10) == 0:\n\n      can_sends.append(make_can_msg(1648, b'\\x00\\x00\\x00\\x40\\x00\\x00\\x50\\x00', 1))\n      can_sends.append(make_can_msg(1649, b'\\x10\\x10\\xf1\\x70\\x04\\x00\\x00\\x00', 1))\n\n      can_sends.append(make_can_msg(1664, b'\\x00\\x00\\x03\\xe8\\x00\\x01\\xa9\\xb2', 1))\n      can_sends.append(make_can_msg(1674, b'\\x08\\x00\\x00\\xff\\x0c\\xfb\\x6a\\x08', 1))\n      can_sends.append(make_can_msg(1675, b'\\x00\\x00\\x3b\\x60\\x37\\x00\\x00\\x00', 1))\n      can_sends.append(make_can_msg(1690, b'\\x70\\x00\\x00\\x55\\x86\\x1c\\xe0\\x00', 1))\n\n      can_sends.append(make_can_msg(1910, b'\\x06\\x4b\\x06\\x4b\\x42\\xd3\\x11\\x30', 1))\n      can_sends.append(make_can_msg(1911, b'\\x48\\x53\\x37\\x54\\x48\\x53\\x37\\x54', 1))\n      can_sends.append(make_can_msg(1912, b'\\x31\\x34\\x47\\x30\\x38\\x31\\x43\\x42', 1))\n      can_sends.append(make_can_msg(1913, b'\\x31\\x34\\x47\\x30\\x38\\x32\\x43\\x42', 1))\n      can_sends.append(make_can_msg(1969, b'\\xf4\\x40\\x00\\x00\\x00\\x00\\x00\\x00', 1))\n      can_sends.append(make_can_msg(1971, b'\\x0b\\xc0\\x00\\x00\\x00\\x00\\x00\\x00', 1))\n\n    static_msgs = range(1653, 1658)\n    for addr in static_msgs:\n      cnt = (frame % 10) + 1\n      can_sends.append(make_can_msg(addr, (cnt << 4).to_bytes(1, 'little') + b'\\x00\\x00\\x00\\x00\\x00\\x00\\x00', 1))\n\n    self.enabled_last = enabled\n    self.main_on_last = CS.out.cruiseState.available\n    self.steer_alert_last = steer_alert\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/ford/carstate.py",
    "content": "from cereal import car\nfrom opendbc.can.parser import CANParser\nfrom common.numpy_fast import mean\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import CarStateBase\nfrom selfdrive.car.ford.values import DBC\n\nWHEEL_RADIUS = 0.33\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n\n  def update(self, cp):\n    ret = car.CarState.new_message()\n    ret.wheelSpeeds.rr = cp.vl[\"WheelSpeed_CG1\"][\"WhlRr_W_Meas\"] * WHEEL_RADIUS\n    ret.wheelSpeeds.rl = cp.vl[\"WheelSpeed_CG1\"][\"WhlRl_W_Meas\"] * WHEEL_RADIUS\n    ret.wheelSpeeds.fr = cp.vl[\"WheelSpeed_CG1\"][\"WhlFr_W_Meas\"] * WHEEL_RADIUS\n    ret.wheelSpeeds.fl = cp.vl[\"WheelSpeed_CG1\"][\"WhlFl_W_Meas\"] * WHEEL_RADIUS\n    ret.vEgoRaw = mean([ret.wheelSpeeds.rr, ret.wheelSpeeds.rl, ret.wheelSpeeds.fr, ret.wheelSpeeds.fl])\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n    ret.standstill = not ret.vEgoRaw > 0.001\n    ret.steeringAngleDeg = cp.vl[\"Steering_Wheel_Data_CG1\"][\"SteWhlRelInit_An_Sns\"]\n    ret.steeringPressed = not cp.vl[\"Lane_Keep_Assist_Status\"][\"LaHandsOff_B_Actl\"]\n    ret.steerError = cp.vl[\"Lane_Keep_Assist_Status\"][\"LaActDeny_B_Actl\"] == 1\n    ret.cruiseState.speed = cp.vl[\"Cruise_Status\"][\"Set_Speed\"] * CV.MPH_TO_MS\n    ret.cruiseState.enabled = not (cp.vl[\"Cruise_Status\"][\"Cruise_State\"] in [0, 3])\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    ret.cruiseState.available = cp.vl[\"Cruise_Status\"][\"Cruise_State\"] != 0\n    ret.gas = cp.vl[\"EngineData_14\"][\"ApedPosScal_Pc_Actl\"] / 100.\n    ret.gasPressed = ret.gas > 1e-6\n    ret.brakePressed = bool(cp.vl[\"Cruise_Status\"][\"Brake_Drv_Appl\"])\n    ret.genericToggle = bool(cp.vl[\"Steering_Buttons\"][\"Dist_Incr\"])\n    # TODO: we also need raw driver torque, needed for Assisted Lane Change\n    self.lkas_state = cp.vl[\"Lane_Keep_Assist_Status\"][\"LaActAvail_D_Actl\"]\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    signals = [\n      # sig_name, sig_address, default\n      (\"WhlRr_W_Meas\", \"WheelSpeed_CG1\", 0.),\n      (\"WhlRl_W_Meas\", \"WheelSpeed_CG1\", 0.),\n      (\"WhlFr_W_Meas\", \"WheelSpeed_CG1\", 0.),\n      (\"WhlFl_W_Meas\", \"WheelSpeed_CG1\", 0.),\n      (\"SteWhlRelInit_An_Sns\", \"Steering_Wheel_Data_CG1\", 0.),\n      (\"Cruise_State\", \"Cruise_Status\", 0.),\n      (\"Set_Speed\", \"Cruise_Status\", 0.),\n      (\"LaActAvail_D_Actl\", \"Lane_Keep_Assist_Status\", 0),\n      (\"LaHandsOff_B_Actl\", \"Lane_Keep_Assist_Status\", 0),\n      (\"LaActDeny_B_Actl\", \"Lane_Keep_Assist_Status\", 0),\n      (\"ApedPosScal_Pc_Actl\", \"EngineData_14\", 0.),\n      (\"Dist_Incr\", \"Steering_Buttons\", 0.),\n      (\"Brake_Drv_Appl\", \"Cruise_Status\", 0.),\n    ]\n    checks = []\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0, enforce_checks=False)\n"
  },
  {
    "path": "selfdrive/car/ford/fordcan.py",
    "content": "from common.numpy_fast import clip\nfrom selfdrive.car.ford.values import MAX_ANGLE\n\n\ndef create_steer_command(packer, angle_cmd, enabled, lkas_state, angle_steers, curvature, lkas_action):\n  \"\"\"Creates a CAN message for the Ford Steer Command.\"\"\"\n\n  #if enabled and lkas available:\n  if enabled and lkas_state in [2, 3]:  # and (frame % 500) >= 3:\n    action = lkas_action\n  else:\n    action = 0xf\n    angle_cmd = angle_steers/MAX_ANGLE\n\n  angle_cmd = clip(angle_cmd * MAX_ANGLE, - MAX_ANGLE, MAX_ANGLE)\n\n  values = {\n    \"Lkas_Action\": action,\n    \"Lkas_Alert\": 0xf,             # no alerts\n    \"Lane_Curvature\": clip(curvature, -0.01, 0.01),   # is it just for debug?\n    #\"Lane_Curvature\": 0,   # is it just for debug?\n    \"Steer_Angle_Req\": angle_cmd\n  }\n  return packer.make_can_msg(\"Lane_Keep_Assist_Control\", 0, values)\n\n\ndef create_lkas_ui(packer, main_on, enabled, steer_alert):\n  \"\"\"Creates a CAN message for the Ford Steer Ui.\"\"\"\n\n  if not main_on:\n    lines = 0xf\n  elif enabled:\n    lines = 0x3\n  else:\n    lines = 0x6\n\n  values = {\n    \"Set_Me_X80\": 0x80,\n    \"Set_Me_X45\": 0x45,\n    \"Set_Me_X30\": 0x30,\n    \"Lines_Hud\": lines,\n    \"Hands_Warning_W_Chime\": steer_alert,\n  }\n  return packer.make_can_msg(\"Lane_Keep_Assist_Ui\", 0, values)\n\ndef spam_cancel_button(packer):\n  values = {\n    \"Cancel\": 1\n  }\n  return packer.make_can_msg(\"Steering_Buttons\", 0, values)\n"
  },
  {
    "path": "selfdrive/car/ford/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.ford.values import MAX_ANGLE\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\n\nclass CarInterface(CarInterfaceBase):\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"ford\"\n    ret.lateralTuning.init('pid')\n    ret.safetyModel = car.CarParams.SafetyModel.ford\n    ret.dashcamOnly = True\n\n    ret.wheelbase = 2.85\n    ret.steerRatio = 14.8\n    ret.mass = 3045. * CV.LB_TO_KG + STD_CARGO_KG\n    ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n    ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.01], [0.005]]     # TODO: tune this\n    ret.lateralTuning.pid.kf = 1. / MAX_ANGLE   # MAX Steer angle to normalize FF\n    ret.steerActuatorDelay = 0.1  # Default delay, not measured yet\n    ret.steerLimitTimer = 0.8\n    ret.steerRateCost = 1.0\n    ret.centerToFront = ret.wheelbase * 0.44\n    tire_stiffness_factor = 0.5328\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n\n    ret.steerControlType = car.CarParams.SteerControlType.angle\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    # ******************* do can recv *******************\n    self.cp.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid\n\n    # events\n    events = self.create_common_events(ret)\n\n    if self.CS.lkas_state not in [2, 3] and ret.vEgo > 13. * CV.MPH_TO_MS and ret.cruiseState.enabled:\n      events.add(car.CarEvent.EventName.steerTempUnavailable)\n\n    ret.events = events.to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  # pass in a car.CarControl\n  # to be called @ 100hz\n  def apply(self, c):\n\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, c.actuators,\n                               c.hudControl.visualAlert, c.cruiseControl.cancel, self.dragonconf)\n\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/ford/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.ford.values import DBC\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nRADAR_MSGS = list(range(0x500, 0x540))\n\ndef _create_radar_can_parser(car_fingerprint):\n  msg_n = len(RADAR_MSGS)\n  signals = list(zip(['X_Rel'] * msg_n + ['Angle'] * msg_n + ['V_Rel'] * msg_n,\n                     RADAR_MSGS * 3,\n                     [0] * msg_n + [0] * msg_n + [0] * msg_n))\n  checks = list(zip(RADAR_MSGS, [20]*msg_n))\n\n  return CANParser(DBC[car_fingerprint]['radar'], signals, checks, 1)\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.validCnt = {key: 0 for key in RADAR_MSGS}\n    self.track_id = 0\n\n    self.rcp = _create_radar_can_parser(CP.carFingerprint)\n    self.trigger_msg = 0x53f\n    self.updated_messages = set()\n\n  def update(self, can_strings):\n    vls = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(vls)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    ret = car.RadarData.new_message()\n    errors = []\n    if not self.rcp.can_valid:\n      errors.append(\"canError\")\n    ret.errors = errors\n\n    for ii in sorted(self.updated_messages):\n      cpt = self.rcp.vl[ii]\n\n      if cpt['X_Rel'] > 0.00001:\n        self.validCnt[ii] = 0    # reset counter\n\n      if cpt['X_Rel'] > 0.00001:\n        self.validCnt[ii] += 1\n      else:\n        self.validCnt[ii] = max(self.validCnt[ii] - 1, 0)\n      #print ii, self.validCnt[ii], cpt['VALID'], cpt['X_Rel'], cpt['Angle']\n\n      # radar point only valid if there have been enough valid measurements\n      if self.validCnt[ii] > 0:\n        if ii not in self.pts:\n          self.pts[ii] = car.RadarData.RadarPoint.new_message()\n          self.pts[ii].trackId = self.track_id\n          self.track_id += 1\n        self.pts[ii].dRel = cpt['X_Rel']  # from front of car\n        self.pts[ii].yRel = cpt['X_Rel'] * cpt['Angle'] * CV.DEG_TO_RAD  # in car frame's y axis, left is positive\n        self.pts[ii].vRel = cpt['V_Rel']\n        self.pts[ii].aRel = float('nan')\n        self.pts[ii].yvRel = float('nan')\n        self.pts[ii].measured = True\n      else:\n        if ii in self.pts:\n          del self.pts[ii]\n\n    ret.points = list(self.pts.values())\n    self.updated_messages.clear()\n    return ret\n"
  },
  {
    "path": "selfdrive/car/ford/values.py",
    "content": "# flake8: noqa\n\nfrom selfdrive.car import dbc_dict\nfrom cereal import car\nEcu = car.CarParams.Ecu\n\nMAX_ANGLE = 87.  # make sure we never command the extremes (0xfff) which cause latching fault\n\nclass CAR:\n  FUSION = \"FORD FUSION 2018\"\n\nFINGERPRINTS = {\n  CAR.FUSION: [{\n    71: 8, 74: 8, 75: 8, 76: 8, 90: 8, 92: 8, 93: 8, 118: 8, 119: 8, 120: 8, 125: 8, 129: 8, 130: 8, 131: 8, 132: 8, 133: 8, 145: 8, 146: 8, 357: 8, 359: 8, 360: 8, 361: 8, 376: 8, 390: 8, 391: 8, 392: 8, 394: 8, 512: 8, 514: 8, 516: 8, 531: 8, 532: 8, 534: 8, 535: 8, 560: 8, 578: 8, 604: 8, 613: 8, 673: 8, 827: 8, 848: 8, 934: 8, 935: 8, 936: 8, 947: 8, 963: 8, 970: 8, 972: 8, 973: 8, 984: 8, 992: 8, 994: 8, 997: 8, 998: 8, 1003: 8, 1034: 8, 1045: 8, 1046: 8, 1053: 8, 1054: 8, 1058: 8, 1059: 8, 1068: 8, 1072: 8, 1073: 8, 1082: 8, 1107: 8, 1108: 8, 1109: 8, 1110: 8, 1200: 8, 1427: 8, 1430: 8, 1438: 8, 1459: 8\n  }],\n}\n\nDBC = {\n  CAR.FUSION: dbc_dict('ford_fusion_2018_pt', 'ford_fusion_2018_adas'),\n}\n"
  },
  {
    "path": "selfdrive/car/fw_versions.py",
    "content": "#!/usr/bin/env python3\nimport struct\nimport traceback\nfrom typing import Any\nfrom collections import defaultdict\n\nfrom tqdm import tqdm\n\nimport panda.python.uds as uds\nfrom cereal import car\nfrom selfdrive.car.fingerprints import FW_VERSIONS, get_attr_from_cars\nfrom selfdrive.car.isotp_parallel_query import IsoTpParallelQuery\nfrom selfdrive.car.toyota.values import CAR as TOYOTA\nfrom selfdrive.swaglog import cloudlog\n\n\nEcu = car.CarParams.Ecu\n\n\ndef p16(val):\n  return struct.pack(\"!H\", val)\n\n\nTESTER_PRESENT_REQUEST = bytes([uds.SERVICE_TYPE.TESTER_PRESENT, 0x0])\nTESTER_PRESENT_RESPONSE = bytes([uds.SERVICE_TYPE.TESTER_PRESENT + 0x40, 0x0])\n\nSHORT_TESTER_PRESENT_REQUEST = bytes([uds.SERVICE_TYPE.TESTER_PRESENT])\nSHORT_TESTER_PRESENT_RESPONSE = bytes([uds.SERVICE_TYPE.TESTER_PRESENT + 0x40])\n\nDEFAULT_DIAGNOSTIC_REQUEST = bytes([uds.SERVICE_TYPE.DIAGNOSTIC_SESSION_CONTROL,\n                                    uds.SESSION_TYPE.DEFAULT])\nDEFAULT_DIAGNOSTIC_RESPONSE = bytes([uds.SERVICE_TYPE.DIAGNOSTIC_SESSION_CONTROL + 0x40,\n                                    uds.SESSION_TYPE.DEFAULT, 0x0, 0x32, 0x1, 0xf4])\n\nEXTENDED_DIAGNOSTIC_REQUEST = bytes([uds.SERVICE_TYPE.DIAGNOSTIC_SESSION_CONTROL,\n                                     uds.SESSION_TYPE.EXTENDED_DIAGNOSTIC])\nEXTENDED_DIAGNOSTIC_RESPONSE = bytes([uds.SERVICE_TYPE.DIAGNOSTIC_SESSION_CONTROL + 0x40,\n                                      uds.SESSION_TYPE.EXTENDED_DIAGNOSTIC, 0x0, 0x32, 0x1, 0xf4])\n\nUDS_VERSION_REQUEST = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER]) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.APPLICATION_SOFTWARE_IDENTIFICATION)\nUDS_VERSION_RESPONSE = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER + 0x40]) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.APPLICATION_SOFTWARE_IDENTIFICATION)\n\n\nHYUNDAI_VERSION_REQUEST_SHORT = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER]) + \\\n  p16(0xf1a0)  # 4 Byte version number\nHYUNDAI_VERSION_REQUEST_LONG = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER]) + \\\n  p16(0xf100)  # Long description\nHYUNDAI_VERSION_REQUEST_MULTI = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER]) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.VEHICLE_MANUFACTURER_SPARE_PART_NUMBER) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.APPLICATION_SOFTWARE_IDENTIFICATION) + \\\n  p16(0xf100) + \\\n  p16(0xf1a0)\nHYUNDAI_VERSION_RESPONSE = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER + 0x40])\n\n\nTOYOTA_VERSION_REQUEST = b'\\x1a\\x88\\x01'\nTOYOTA_VERSION_RESPONSE = b'\\x5a\\x88\\x01'\n\nVOLKSWAGEN_VERSION_REQUEST_MULTI = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER]) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.VEHICLE_MANUFACTURER_SPARE_PART_NUMBER) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.VEHICLE_MANUFACTURER_ECU_SOFTWARE_VERSION_NUMBER) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.APPLICATION_DATA_IDENTIFICATION)\nVOLKSWAGEN_VERSION_RESPONSE = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER + 0x40])\n\nOBD_VERSION_REQUEST = b'\\x09\\x04'\nOBD_VERSION_RESPONSE = b'\\x49\\x04'\n\nDEFAULT_RX_OFFSET = 0x8\nVOLKSWAGEN_RX_OFFSET = 0x6a\n\nMAZDA_VERSION_REQUEST = bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER]) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.VEHICLE_MANUFACTURER_ECU_SOFTWARE_NUMBER)\nMAZDA_VERSION_RESPONSE =  bytes([uds.SERVICE_TYPE.READ_DATA_BY_IDENTIFIER + 0x40]) + \\\n  p16(uds.DATA_IDENTIFIER_TYPE.VEHICLE_MANUFACTURER_ECU_SOFTWARE_NUMBER)\n\n# brand, request, response, response offset\nREQUESTS = [\n  # Hyundai\n  (\n    \"hyundai\",\n    [HYUNDAI_VERSION_REQUEST_SHORT],\n    [HYUNDAI_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  (\n    \"hyundai\",\n    [HYUNDAI_VERSION_REQUEST_LONG],\n    [HYUNDAI_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  (\n    \"hyundai\",\n    [HYUNDAI_VERSION_REQUEST_MULTI],\n    [HYUNDAI_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  # Honda\n  (\n    \"honda\",\n    [UDS_VERSION_REQUEST],\n    [UDS_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  # Toyota\n  (\n    \"toyota\",\n    [SHORT_TESTER_PRESENT_REQUEST, TOYOTA_VERSION_REQUEST],\n    [SHORT_TESTER_PRESENT_RESPONSE, TOYOTA_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  (\n    \"toyota\",\n    [SHORT_TESTER_PRESENT_REQUEST, OBD_VERSION_REQUEST],\n    [SHORT_TESTER_PRESENT_RESPONSE, OBD_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  (\n    \"toyota\",\n    [TESTER_PRESENT_REQUEST, DEFAULT_DIAGNOSTIC_REQUEST, EXTENDED_DIAGNOSTIC_REQUEST, UDS_VERSION_REQUEST],\n    [TESTER_PRESENT_RESPONSE, DEFAULT_DIAGNOSTIC_RESPONSE, EXTENDED_DIAGNOSTIC_RESPONSE, UDS_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  # Volkswagen\n  (\n    \"volkswagen\",\n    [VOLKSWAGEN_VERSION_REQUEST_MULTI],\n    [VOLKSWAGEN_VERSION_RESPONSE],\n    VOLKSWAGEN_RX_OFFSET,\n  ),\n  (\n    \"volkswagen\",\n    [VOLKSWAGEN_VERSION_REQUEST_MULTI],\n    [VOLKSWAGEN_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  ),\n  # Mazda\n  (\n    \"mazda\",\n    [MAZDA_VERSION_REQUEST],\n    [MAZDA_VERSION_RESPONSE],\n    DEFAULT_RX_OFFSET,\n  )\n]\n\n\ndef chunks(l, n=128):\n  for i in range(0, len(l), n):\n    yield l[i:i + n]\n\n\ndef build_fw_dict(fw_versions):\n  fw_versions_dict = {}\n  for fw in fw_versions:\n    addr = fw.address\n    sub_addr = fw.subAddress if fw.subAddress != 0 else None\n    fw_versions_dict[(addr, sub_addr)] = fw.fwVersion\n  return fw_versions_dict\n\n\ndef match_fw_to_car_fuzzy(fw_versions_dict, log=True, exclude=None):\n  \"\"\"Do a fuzzy FW match. This function will return a match, and the number of firmware version\n  that were matched uniquely to that specific car. If multiple ECUs uniquely match to different cars\n  the match is rejected.\"\"\"\n\n  # These ECUs are known to be shared between models (EPS only between hybrid/ICE version)\n  # Getting this exactly right isn't crucial, but excluding camera and radar makes it almost\n  # impossible to get 3 matching versions, even if two models with shared parts are released at the same\n  # time and only one is in our database.\n  exclude_types = [Ecu.fwdCamera, Ecu.fwdRadar, Ecu.eps]\n\n  # Build lookup table from (addr, subaddr, fw) to list of candidate cars\n  all_fw_versions = defaultdict(list)\n  for candidate, fw_by_addr in FW_VERSIONS.items():\n    if candidate == exclude:\n      continue\n\n    for addr, fws in fw_by_addr.items():\n      if addr[0] in exclude_types:\n        continue\n      for f in fws:\n        all_fw_versions[(addr[1], addr[2], f)].append(candidate)\n\n  match_count = 0\n  candidate = None\n  for addr, version in fw_versions_dict.items():\n    # All cars that have this FW response on the specified address\n    candidates = all_fw_versions[(addr[0], addr[1], version)]\n\n    if len(candidates) == 1:\n      match_count += 1\n      if candidate is None:\n        candidate = candidates[0]\n      # We uniquely matched two different cars. No fuzzy match possible\n      elif candidate != candidates[0]:\n        return set()\n\n  if match_count >= 2:\n    if log:\n      cloudlog.error(f\"Fingerprinted {candidate} using fuzzy match. {match_count} matching ECUs\")\n    return set([candidate])\n  else:\n    return set()\n\n\ndef match_fw_to_car_exact(fw_versions_dict):\n  \"\"\"Do an exact FW match. Returns all cars that match the given\n  FW versions for a list of \"essential\" ECUs. If an ECU is not considered\n  essential the FW version can be missing to get a fingerprint, but if it's present it\n  needs to match the database.\"\"\"\n  invalid = []\n  candidates = FW_VERSIONS\n\n  for candidate, fws in candidates.items():\n    for ecu, expected_versions in fws.items():\n      ecu_type = ecu[0]\n      addr = ecu[1:]\n      found_version = fw_versions_dict.get(addr, None)\n      ESSENTIAL_ECUS = [Ecu.engine, Ecu.eps, Ecu.esp, Ecu.fwdRadar, Ecu.fwdCamera, Ecu.vsa]\n      if ecu_type == Ecu.esp and candidate in [TOYOTA.RAV4, TOYOTA.COROLLA, TOYOTA.HIGHLANDER] and found_version is None:\n        continue\n\n      # On some Toyota models, the engine can show on two different addresses\n      if ecu_type == Ecu.engine and candidate in [TOYOTA.CAMRY, TOYOTA.COROLLA_TSS2, TOYOTA.CHR, TOYOTA.LEXUS_IS] and found_version is None:\n        continue\n\n      # Ignore non essential ecus\n      if ecu_type not in ESSENTIAL_ECUS and found_version is None:\n        continue\n\n      if found_version not in expected_versions:\n        invalid.append(candidate)\n        break\n\n  return set(candidates.keys()) - set(invalid)\n\n\ndef match_fw_to_car(fw_versions, allow_fuzzy=True):\n  fw_versions_dict = build_fw_dict(fw_versions)\n  matches = match_fw_to_car_exact(fw_versions_dict)\n\n  exact_match = True\n  if allow_fuzzy and len(matches) == 0:\n    matches = match_fw_to_car_fuzzy(fw_versions_dict)\n\n    # Fuzzy match found\n    if len(matches) == 1:\n      exact_match = False\n\n  return exact_match, matches\n\n\ndef get_fw_versions(logcan, sendcan, bus, extra=None, timeout=0.1, debug=False, progress=False):\n  ecu_types = {}\n\n  # Extract ECU addresses to query from fingerprints\n  # ECUs using a subadress need be queried one by one, the rest can be done in parallel\n  addrs = []\n  parallel_addrs = []\n\n  versions = get_attr_from_cars('FW_VERSIONS', combine_brands=False)\n  if extra is not None:\n    versions.update(extra)\n\n  for brand, brand_versions in versions.items():\n    for c in brand_versions.values():\n      for ecu_type, addr, sub_addr in c.keys():\n        a = (brand, addr, sub_addr)\n        if a not in ecu_types:\n          ecu_types[(addr, sub_addr)] = ecu_type\n\n        if sub_addr is None:\n          if a not in parallel_addrs:\n            parallel_addrs.append(a)\n        else:\n          if [a] not in addrs:\n            addrs.append([a])\n\n  addrs.insert(0, parallel_addrs)\n\n  fw_versions = {}\n  for i, addr in enumerate(tqdm(addrs, disable=not progress)):\n    for addr_chunk in chunks(addr):\n      for brand, request, response, response_offset in REQUESTS:\n        try:\n          addrs = [(a, s) for (b, a, s) in addr_chunk if b in (brand, 'any')]\n\n          if addrs:\n            query = IsoTpParallelQuery(sendcan, logcan, bus, addrs, request, response, response_offset, debug=debug)\n            t = 2 * timeout if i == 0 else timeout\n            fw_versions.update(query.get_data(t))\n        except Exception:\n          cloudlog.warning(f\"FW query exception: {traceback.format_exc()}\")\n\n  # Build capnp list to put into CarParams\n  car_fw = []\n  for addr, version in fw_versions.items():\n    f = car.CarParams.CarFw.new_message()\n\n    f.ecu = ecu_types[addr]\n    f.fwVersion = version\n    f.address = addr[0]\n\n    if addr[1] is not None:\n      f.subAddress = addr[1]\n\n    car_fw.append(f)\n\n  return car_fw\n\n\nif __name__ == \"__main__\":\n  import time\n  import argparse\n  import cereal.messaging as messaging\n  from selfdrive.car.vin import get_vin\n  import selfdrive.crash as crash\n\n  parser = argparse.ArgumentParser(description='Get firmware version of ECUs')\n  parser.add_argument('--scan', '-s', action='store_true', help='In-depth scan of ECU\\'s. May cause module faults')\n  parser.add_argument('--debug', '-d', action='store_true')\n  parser.add_argument('--json', '-j', type=str, nargs=2, metavar=('MODEL'), help='fp.\"')\n  args = parser.parse_args()\n\n  logcan = messaging.sub_sock('can')\n  sendcan = messaging.pub_sock('sendcan')\n\n  extra: Any = None\n  if args.scan:\n    extra = {}\n    # Honda\n    for i in range(256):\n      extra[(Ecu.unknown, 0x18da00f1 + (i << 8), None)] = []\n      extra[(Ecu.unknown, 0x700 + i, None)] = []\n      extra[(Ecu.unknown, 0x750, i)] = []\n    extra = {\"any\": {\"debug\": extra}}\n\n  time.sleep(1.)\n\n  t = time.time()\n  print(\"Getting vin...\")\n  addr, vin = get_vin(logcan, sendcan, 1, retry=10, debug=args.debug)\n  print(f\"VIN: {vin}\")\n  print(\"Getting VIN took %.3f s\" % (time.time() - t))\n  print()\n\n  t = time.time()\n  fw_vers = get_fw_versions(logcan, sendcan, 1, extra=extra, debug=args.debug, progress=True)\n  fw_vers = get_fw_versions(logcan, sendcan, 0, extra=extra, debug=args.debug, progress=True)\n  fw_vers += get_fw_versions(logcan, sendcan, 1, extra=extra, debug=args.debug, progress=True)\n  _, candidates = match_fw_to_car(fw_vers)\n\n  versions = []\n  print()\n  print(\"Found FW versions\")\n  print(\"{\")\n  for version in fw_vers:\n    subaddr = None if version.subAddress == 0 else hex(version.subAddress)\n    vers = (f\"  (Ecu.{version.ecu}, {hex(version.address)}, {subaddr}): [{version.fwVersion}]\")\n    versions.append('('+vers+')')\n    print(vers)\n  print(\"}\")\n\n  print()\n  print(\"Possible matches:\", candidates)\n  print(\"Getting fw took %.3f s\" % (time.time() - t))\n\n  if args.json:\n    model = args.json\n    vers_str = ''.join(versions)\n    crash.capture_info('Model is: '+model+'. '+vers_str)\n    print(\"Uploaded JSON & Sentry to fork maintainer\")\n"
  },
  {
    "path": "selfdrive/car/gm/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/gm/carcontroller.py",
    "content": "from cereal import car\nfrom common.realtime import DT_CTRL\nfrom common.numpy_fast import interp\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car import apply_std_steer_torque_limits\nfrom selfdrive.car.gm import gmcan\nfrom selfdrive.car.gm.values import DBC, CanBus, CarControllerParams\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.start_time = 0.\n    self.apply_steer_last = 0\n    self.lka_icon_status_last = (False, False)\n    self.steer_rate_limited = False\n\n    self.params = CarControllerParams()\n\n    self.packer_pt = CANPacker(DBC[CP.carFingerprint]['pt'])\n    self.packer_obj = CANPacker(DBC[CP.carFingerprint]['radar'])\n    self.packer_ch = CANPacker(DBC[CP.carFingerprint]['chassis'])\n\n  def update(self, enabled, CS, frame, actuators,\n             hud_v_cruise, hud_show_lanes, hud_show_car, hud_alert, dragonconf):\n\n    P = self.params\n\n    # Send CAN commands.\n    can_sends = []\n\n    # STEER\n    if (frame % P.STEER_STEP) == 0:\n      lkas_enabled = enabled and not (CS.out.steerWarning or CS.out.steerError) and CS.out.vEgo > P.MIN_STEER_SPEED\n      if lkas_enabled:\n        new_steer = int(round(actuators.steer * P.STEER_MAX))\n        apply_steer = apply_std_steer_torque_limits(new_steer, self.apply_steer_last, CS.out.steeringTorque, P)\n        self.steer_rate_limited = new_steer != apply_steer\n      else:\n        apply_steer = 0\n\n      # dp\n      blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n      if not enabled:\n        self.blinker_end_frame = 0\n      if self.last_blinker_on and not blinker_on:\n        self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n      apply_steer = common_controller_ctrl(enabled,\n                                           dragonconf,\n                                           blinker_on or frame < self.blinker_end_frame,\n                                           apply_steer, CS.out.vEgo)\n      self.last_blinker_on = blinker_on\n\n      self.apply_steer_last = apply_steer\n      idx = (frame // P.STEER_STEP) % 4\n\n      can_sends.append(gmcan.create_steering_control(self.packer_pt, CanBus.POWERTRAIN, apply_steer, idx, lkas_enabled))\n\n    if not enabled:\n      # Stock ECU sends max regen when not enabled.\n      apply_gas = P.MAX_ACC_REGEN\n      apply_brake = 0\n    else:\n      apply_gas = int(round(interp(actuators.accel, P.GAS_LOOKUP_BP, P.GAS_LOOKUP_V)))\n      apply_brake = int(round(interp(actuators.accel, P.BRAKE_LOOKUP_BP, P.BRAKE_LOOKUP_V)))\n\n    # Gas/regen and brakes - all at 25Hz\n    if (frame % 4) == 0:\n      idx = (frame // 4) % 4\n\n      at_full_stop = enabled and CS.out.standstill\n      near_stop = enabled and (CS.out.vEgo < P.NEAR_STOP_BRAKE_PHASE)\n      can_sends.append(gmcan.create_friction_brake_command(self.packer_ch, CanBus.CHASSIS, apply_brake, idx, near_stop, at_full_stop))\n      can_sends.append(gmcan.create_gas_regen_command(self.packer_pt, CanBus.POWERTRAIN, apply_gas, idx, enabled, at_full_stop))\n\n    # Send dashboard UI commands (ACC status), 25hz\n    if (frame % 4) == 0:\n      send_fcw = hud_alert == VisualAlert.fcw\n      can_sends.append(gmcan.create_acc_dashboard_command(self.packer_pt, CanBus.POWERTRAIN, enabled, hud_v_cruise * CV.MS_TO_KPH, hud_show_car, send_fcw))\n\n    # Radar needs to know current speed and yaw rate (50hz),\n    # and that ADAS is alive (10hz)\n    time_and_headlights_step = 10\n    tt = frame * DT_CTRL\n\n    if frame % time_and_headlights_step == 0:\n      idx = (frame // time_and_headlights_step) % 4\n      can_sends.append(gmcan.create_adas_time_status(CanBus.OBSTACLE, int((tt - self.start_time) * 60), idx))\n      can_sends.append(gmcan.create_adas_headlights_status(self.packer_obj, CanBus.OBSTACLE))\n\n    speed_and_accelerometer_step = 2\n    if frame % speed_and_accelerometer_step == 0:\n      idx = (frame // speed_and_accelerometer_step) % 4\n      can_sends.append(gmcan.create_adas_steering_status(CanBus.OBSTACLE, idx))\n      can_sends.append(gmcan.create_adas_accelerometer_speed_status(CanBus.OBSTACLE, CS.out.vEgo, idx))\n\n    if frame % P.ADAS_KEEPALIVE_STEP == 0:\n      can_sends += gmcan.create_adas_keepalive(CanBus.POWERTRAIN)\n\n    # Show green icon when LKA torque is applied, and\n    # alarming orange icon when approaching torque limit.\n    # If not sent again, LKA icon disappears in about 5 seconds.\n    # Conveniently, sending camera message periodically also works as a keepalive.\n    lka_active = CS.lkas_status == 1\n    lka_critical = lka_active and abs(actuators.steer) > 0.9\n    lka_icon_status = (lka_active, lka_critical)\n    if frame % P.CAMERA_KEEPALIVE_STEP == 0 or lka_icon_status != self.lka_icon_status_last:\n      steer_alert = hud_alert in [VisualAlert.steerRequired, VisualAlert.ldw]\n      can_sends.append(gmcan.create_lka_icon_command(CanBus.SW_GMLAN, lka_active, lka_critical, steer_alert))\n      self.lka_icon_status_last = lka_icon_status\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/gm/carstate.py",
    "content": "from cereal import car\nfrom common.numpy_fast import mean\nfrom selfdrive.config import Conversions as CV\nfrom opendbc.can.can_define import CANDefine\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.interfaces import CarStateBase\nfrom selfdrive.car.gm.values import DBC, CAR, AccState, CanBus, \\\n                                    CruiseButtons, STEER_THRESHOLD\n\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n    self.shifter_values = can_define.dv[\"ECMPRDNL\"][\"PRNDL\"]\n\n  def update(self, pt_cp):\n    ret = car.CarState.new_message()\n\n    self.prev_cruise_buttons = self.cruise_buttons\n    self.cruise_buttons = pt_cp.vl[\"ASCMSteeringButton\"][\"ACCButtons\"]\n\n    ret.wheelSpeeds.fl = pt_cp.vl[\"EBCMWheelSpdFront\"][\"FLWheelSpd\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = pt_cp.vl[\"EBCMWheelSpdFront\"][\"FRWheelSpd\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = pt_cp.vl[\"EBCMWheelSpdRear\"][\"RLWheelSpd\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = pt_cp.vl[\"EBCMWheelSpdRear\"][\"RRWheelSpd\"] * CV.KPH_TO_MS\n    ret.vEgoRaw = mean([ret.wheelSpeeds.fl, ret.wheelSpeeds.fr, ret.wheelSpeeds.rl, ret.wheelSpeeds.rr])\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n    ret.standstill = ret.vEgoRaw < 0.01\n\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(pt_cp.vl[\"ECMPRDNL\"][\"PRNDL\"], None))\n    ret.brake = pt_cp.vl[\"EBCMBrakePedalPosition\"][\"BrakePedalPosition\"] / 0xd0\n    # Brake pedal's potentiometer returns near-zero reading even when pedal is not pressed.\n    if ret.brake < 10/0xd0:\n      ret.brake = 0.\n\n    ret.gas = pt_cp.vl[\"AcceleratorPedal\"][\"AcceleratorPedal\"] / 254.\n    ret.gasPressed = ret.gas > 1e-5\n\n    ret.steeringAngleDeg = pt_cp.vl[\"PSCMSteeringAngle\"][\"SteeringWheelAngle\"]\n    ret.steeringRateDeg = pt_cp.vl[\"PSCMSteeringAngle\"][\"SteeringWheelRate\"]\n    ret.steeringTorque = pt_cp.vl[\"PSCMStatus\"][\"LKADriverAppldTrq\"]\n    ret.steeringTorqueEps = pt_cp.vl[\"PSCMStatus\"][\"LKATorqueDelivered\"]\n    ret.steeringPressed = abs(ret.steeringTorque) > STEER_THRESHOLD\n\n    # 0 inactive, 1 active, 2 temporarily limited, 3 failed\n    self.lkas_status = pt_cp.vl[\"PSCMStatus\"][\"LKATorqueDeliveredStatus\"]\n    ret.steerWarning = self.lkas_status == 2\n    ret.steerError = self.lkas_status == 3\n\n    # 1 - open, 0 - closed\n    ret.doorOpen = (pt_cp.vl[\"BCMDoorBeltStatus\"][\"FrontLeftDoor\"] == 1 or\n                    pt_cp.vl[\"BCMDoorBeltStatus\"][\"FrontRightDoor\"] == 1 or\n                    pt_cp.vl[\"BCMDoorBeltStatus\"][\"RearLeftDoor\"] == 1 or\n                    pt_cp.vl[\"BCMDoorBeltStatus\"][\"RearRightDoor\"] == 1)\n\n    # 1 - latched\n    ret.seatbeltUnlatched = pt_cp.vl[\"BCMDoorBeltStatus\"][\"LeftSeatBelt\"] == 0\n    ret.leftBlinker = pt_cp.vl[\"BCMTurnSignals\"][\"TurnSignals\"] == 1\n    ret.rightBlinker = pt_cp.vl[\"BCMTurnSignals\"][\"TurnSignals\"] == 2\n\n    self.park_brake = pt_cp.vl[\"EPBStatus\"][\"EPBClosed\"]\n    ret.cruiseState.available = bool(pt_cp.vl[\"ECMEngineStatus\"][\"CruiseMainOn\"])\n    ret.espDisabled = pt_cp.vl[\"ESPStatus\"][\"TractionControlOn\"] != 1\n    self.pcm_acc_status = pt_cp.vl[\"AcceleratorPedal2\"][\"CruiseState\"]\n\n    ret.brakePressed = ret.brake > 1e-5\n    # Regen braking is braking\n    if self.car_fingerprint == CAR.VOLT:\n      ret.brakePressed = ret.brakePressed or bool(pt_cp.vl[\"EBCMRegenPaddle\"][\"RegenPaddle\"])\n\n    ret.cruiseState.enabled = self.pcm_acc_status != AccState.OFF\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    ret.cruiseState.standstill = self.pcm_acc_status == AccState.STANDSTILL\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    # this function generates lists for signal, messages and initial values\n    signals = [\n      # sig_name, sig_address, default\n      (\"BrakePedalPosition\", \"EBCMBrakePedalPosition\", 0),\n      (\"FrontLeftDoor\", \"BCMDoorBeltStatus\", 0),\n      (\"FrontRightDoor\", \"BCMDoorBeltStatus\", 0),\n      (\"RearLeftDoor\", \"BCMDoorBeltStatus\", 0),\n      (\"RearRightDoor\", \"BCMDoorBeltStatus\", 0),\n      (\"LeftSeatBelt\", \"BCMDoorBeltStatus\", 0),\n      (\"RightSeatBelt\", \"BCMDoorBeltStatus\", 0),\n      (\"TurnSignals\", \"BCMTurnSignals\", 0),\n      (\"AcceleratorPedal\", \"AcceleratorPedal\", 0),\n      (\"CruiseState\", \"AcceleratorPedal2\", 0),\n      (\"ACCButtons\", \"ASCMSteeringButton\", CruiseButtons.UNPRESS),\n      (\"SteeringWheelAngle\", \"PSCMSteeringAngle\", 0),\n      (\"SteeringWheelRate\", \"PSCMSteeringAngle\", 0),\n      (\"FLWheelSpd\", \"EBCMWheelSpdFront\", 0),\n      (\"FRWheelSpd\", \"EBCMWheelSpdFront\", 0),\n      (\"RLWheelSpd\", \"EBCMWheelSpdRear\", 0),\n      (\"RRWheelSpd\", \"EBCMWheelSpdRear\", 0),\n      (\"PRNDL\", \"ECMPRDNL\", 0),\n      (\"LKADriverAppldTrq\", \"PSCMStatus\", 0),\n      (\"LKATorqueDelivered\", \"PSCMStatus\", 0),\n      (\"LKATorqueDeliveredStatus\", \"PSCMStatus\", 0),\n      (\"TractionControlOn\", \"ESPStatus\", 0),\n      (\"EPBClosed\", \"EPBStatus\", 0),\n      (\"CruiseMainOn\", \"ECMEngineStatus\", 0),\n    ]\n\n    checks = [\n      (\"BCMTurnSignals\", 1),\n      (\"ECMPRDNL\", 10),\n      (\"PSCMStatus\", 10),\n      (\"ESPStatus\", 10),\n      (\"BCMDoorBeltStatus\", 10),\n      (\"EPBStatus\", 20),\n      (\"EBCMWheelSpdFront\", 20),\n      (\"EBCMWheelSpdRear\", 20),\n      (\"AcceleratorPedal\", 33),\n      (\"AcceleratorPedal2\", 33),\n      (\"ASCMSteeringButton\", 33),\n      (\"ECMEngineStatus\", 100),\n      (\"PSCMSteeringAngle\", 100),\n      (\"EBCMBrakePedalPosition\", 100),\n    ]\n\n    if CP.carFingerprint == CAR.VOLT:\n      signals += [\n        (\"RegenPaddle\", \"EBCMRegenPaddle\", 0),\n      ]\n      checks += [\n        (\"EBCMRegenPaddle\", 50),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, CanBus.POWERTRAIN)\n"
  },
  {
    "path": "selfdrive/car/gm/gmcan.py",
    "content": "from selfdrive.car import make_can_msg\n\ndef create_steering_control(packer, bus, apply_steer, idx, lkas_active):\n\n  values = {\n    \"LKASteeringCmdActive\": lkas_active,\n    \"LKASteeringCmd\": apply_steer,\n    \"RollingCounter\": idx,\n    \"LKASteeringCmdChecksum\": 0x1000 - (lkas_active << 11) - (apply_steer & 0x7ff) - idx\n  }\n\n  return packer.make_can_msg(\"ASCMLKASteeringCmd\", bus, values)\n\ndef create_adas_keepalive(bus):\n  dat = b\"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\"\n  return [make_can_msg(0x409, dat, bus), make_can_msg(0x40a, dat, bus)]\n\ndef create_gas_regen_command(packer, bus, throttle, idx, acc_engaged, at_full_stop):\n  values = {\n    \"GasRegenCmdActive\": acc_engaged,\n    \"RollingCounter\": idx,\n    \"GasRegenCmdActiveInv\": 1 - acc_engaged,\n    \"GasRegenCmd\": throttle,\n    \"GasRegenFullStopActive\": at_full_stop,\n    \"GasRegenAlwaysOne\": 1,\n    \"GasRegenAlwaysOne2\": 1,\n    \"GasRegenAlwaysOne3\": 1,\n  }\n\n  dat = packer.make_can_msg(\"ASCMGasRegenCmd\", bus, values)[2]\n  values[\"GasRegenChecksum\"] = (((0xff - dat[1]) & 0xff) << 16) | \\\n                               (((0xff - dat[2]) & 0xff) << 8) | \\\n                               ((0x100 - dat[3] - idx) & 0xff)\n\n  return packer.make_can_msg(\"ASCMGasRegenCmd\", bus, values)\n\ndef create_friction_brake_command(packer, bus, apply_brake, idx, near_stop, at_full_stop):\n  mode = 0x1\n  if apply_brake > 0:\n    mode = 0xa\n    if at_full_stop:\n      mode = 0xd\n\n    # TODO: this is to have GM bringing the car to complete stop,\n    # but currently it conflicts with OP controls, so turned off.\n    #elif near_stop:\n    #  mode = 0xb\n\n  brake = (0x1000 - apply_brake) & 0xfff\n  checksum = (0x10000 - (mode << 12) - brake - idx) & 0xffff\n\n  values = {\n    \"RollingCounter\" : idx,\n    \"FrictionBrakeMode\" : mode,\n    \"FrictionBrakeChecksum\": checksum,\n    \"FrictionBrakeCmd\" : -apply_brake\n  }\n\n  return packer.make_can_msg(\"EBCMFrictionBrakeCmd\", bus, values)\n\ndef create_acc_dashboard_command(packer, bus, acc_engaged, target_speed_kph, lead_car_in_sight, fcw):\n  # Not a bit shift, dash can round up based on low 4 bits.\n  target_speed = int(target_speed_kph * 16) & 0xfff\n\n  values = {\n    \"ACCAlwaysOne\" : 1,\n    \"ACCResumeButton\" : 0,\n    \"ACCSpeedSetpoint\" : target_speed,\n    \"ACCGapLevel\" : 3 * acc_engaged,  # 3 \"far\", 0 \"inactive\"\n    \"ACCCmdActive\" : acc_engaged,\n    \"ACCAlwaysOne2\" : 1,\n    \"ACCLeadCar\" : lead_car_in_sight,\n    \"FCWAlert\": 0x3 if fcw else 0\n  }\n\n  return packer.make_can_msg(\"ASCMActiveCruiseControlStatus\", bus, values)\n\ndef create_adas_time_status(bus, tt, idx):\n  dat = [(tt >> 20) & 0xff, (tt >> 12) & 0xff, (tt >> 4) & 0xff,\n    ((tt & 0xf) << 4) + (idx << 2)]\n  chksum = 0x1000 - dat[0] - dat[1] - dat[2] - dat[3]\n  chksum = chksum & 0xfff\n  dat += [0x40 + (chksum >> 8), chksum & 0xff, 0x12]\n  return make_can_msg(0xa1, bytes(dat), bus)\n\ndef create_adas_steering_status(bus, idx):\n  dat = [idx << 6, 0xf0, 0x20, 0, 0, 0]\n  chksum = 0x60 + sum(dat)\n  dat += [chksum >> 8, chksum & 0xff]\n  return make_can_msg(0x306, bytes(dat), bus)\n\ndef create_adas_accelerometer_speed_status(bus, speed_ms, idx):\n  spd = int(speed_ms * 16) & 0xfff\n  accel = 0 & 0xfff\n  # 0 if in park/neutral, 0x10 if in reverse, 0x08 for D/L\n  #stick = 0x08\n  near_range_cutoff = 0x27\n  near_range_mode = 1 if spd <= near_range_cutoff else 0\n  far_range_mode = 1 - near_range_mode\n  dat = [0x08, spd >> 4, ((spd & 0xf) << 4) | (accel >> 8), accel & 0xff, 0]\n  chksum = 0x62 + far_range_mode + (idx << 2) + dat[0] + dat[1] + dat[2] + dat[3] + dat[4]\n  dat += [(idx << 5) + (far_range_mode << 4) + (near_range_mode << 3) + (chksum >> 8), chksum & 0xff]\n  return make_can_msg(0x308, bytes(dat), bus)\n\ndef create_adas_headlights_status(packer, bus):\n  values = {\n    \"Always42\": 0x42,\n    \"Always4\": 0x4,\n  }\n  return packer.make_can_msg(\"ASCMHeadlight\", bus, values)\n\ndef create_lka_icon_command(bus, active, critical, steer):\n  if active and steer == 1:\n    if critical:\n      dat = b\"\\x50\\xc0\\x14\"\n    else:\n      dat = b\"\\x50\\x40\\x18\"\n  elif active:\n    if critical:\n      dat = b\"\\x40\\xc0\\x14\"\n    else:\n      dat = b\"\\x40\\x40\\x18\"\n  else:\n    dat = b\"\\x00\\x00\\x00\"\n  return make_can_msg(0x104c006c, dat, bus)\n"
  },
  {
    "path": "selfdrive/car/gm/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.gm.values import CAR, CruiseButtons, \\\n                                    AccState, CarControllerParams\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\nButtonType = car.CarState.ButtonEvent.Type\nEventName = car.CarEvent.EventName\n\nclass CarInterface(CarInterfaceBase):\n  @staticmethod\n  def get_pid_accel_limits(CP, current_speed, cruise_speed):\n    params = CarControllerParams()\n    return params.ACCEL_MIN, params.ACCEL_MAX\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"gm\"\n    # dp\n    ret.lateralTuning.init('pid')\n    ret.safetyModel = car.CarParams.SafetyModel.gm\n    ret.pcmCruise = False  # stock cruise control is kept off\n\n    # GM port is a community feature\n    # TODO: make a port that uses a car harness and it only intercepts the camera\n    ret.communityFeature = True\n\n    # Presence of a camera on the object bus is ok.\n    # Have to go to read_only if ASCM is online (ACC-enabled cars),\n    # or camera is on powertrain bus (LKA cars without ACC).\n    ret.openpilotLongitudinalControl = True\n    tire_stiffness_factor = 0.444  # not optimized yet\n\n    # Start with a baseline lateral tuning for all GM vehicles. Override tuning as needed in each model section below.\n    ret.minSteerSpeed = 7 * CV.MPH_TO_MS\n    ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n    ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.2], [0.00]]\n    ret.lateralTuning.pid.kf = 0.00004   # full torque for 20 deg at 80mph means 0.00007818594\n    ret.steerRateCost = 1.0\n    ret.steerActuatorDelay = 0.1  # Default delay, not measured yet\n\n    if candidate == CAR.VOLT:\n      # supports stop and go, but initial engage must be above 18mph (which include conservatism)\n      ret.minEnableSpeed = 18 * CV.MPH_TO_MS\n      ret.mass = 1607. + STD_CARGO_KG\n      ret.wheelbase = 2.69\n      ret.steerRatio = 15.7\n      ret.steerRatioRear = 0.\n      ret.centerToFront = ret.wheelbase * 0.4  # wild guess\n\n    elif candidate == CAR.MALIBU:\n      # supports stop and go, but initial engage must be above 18mph (which include conservatism)\n      ret.minEnableSpeed = 18 * CV.MPH_TO_MS\n      ret.mass = 1496. + STD_CARGO_KG\n      ret.wheelbase = 2.83\n      ret.steerRatio = 15.8\n      ret.steerRatioRear = 0.\n      ret.centerToFront = ret.wheelbase * 0.4  # wild guess\n\n    elif candidate == CAR.HOLDEN_ASTRA:\n      ret.mass = 1363. + STD_CARGO_KG\n      ret.wheelbase = 2.662\n      # Remaining parameters copied from Volt for now\n      ret.centerToFront = ret.wheelbase * 0.4\n      ret.minEnableSpeed = 18 * CV.MPH_TO_MS\n      ret.steerRatio = 15.7\n      ret.steerRatioRear = 0.\n\n    elif candidate == CAR.ACADIA:\n      ret.minEnableSpeed = -1.  # engage speed is decided by pcm\n      ret.mass = 4353. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.86\n      ret.steerRatio = 14.4  # end to end is 13.46\n      ret.steerRatioRear = 0.\n      ret.centerToFront = ret.wheelbase * 0.4\n\n    elif candidate == CAR.BUICK_REGAL:\n      ret.minEnableSpeed = 18 * CV.MPH_TO_MS\n      ret.mass = 3779. * CV.LB_TO_KG + STD_CARGO_KG  # (3849+3708)/2\n      ret.wheelbase = 2.83  # 111.4 inches in meters\n      ret.steerRatio = 14.4  # guess for tourx\n      ret.steerRatioRear = 0.\n      ret.centerToFront = ret.wheelbase * 0.4  # guess for tourx\n\n    elif candidate == CAR.CADILLAC_ATS:\n      ret.minEnableSpeed = 18 * CV.MPH_TO_MS\n      ret.mass = 1601. + STD_CARGO_KG\n      ret.wheelbase = 2.78\n      ret.steerRatio = 15.3\n      ret.steerRatioRear = 0.\n      ret.centerToFront = ret.wheelbase * 0.49\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n\n    ret.longitudinalTuning.kpBP = [5., 35.]\n    ret.longitudinalTuning.kpV = [2.4, 1.5]\n    ret.longitudinalTuning.kiBP = [0.]\n    ret.longitudinalTuning.kiV = [0.36]\n\n    ret.startAccel = 0.8\n\n    ret.steerLimitTimer = 0.4\n    ret.radarTimeStep = 0.0667  # GM radar runs at 15Hz instead of standard 20Hz\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    self.cp.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid\n    ret.steeringRateLimited = self.CC.steer_rate_limited if self.CC is not None else False\n\n    buttonEvents = []\n\n    if self.CS.cruise_buttons != self.CS.prev_cruise_buttons and self.CS.prev_cruise_buttons != CruiseButtons.INIT:\n      be = car.CarState.ButtonEvent.new_message()\n      be.type = ButtonType.unknown\n      if self.CS.cruise_buttons != CruiseButtons.UNPRESS:\n        be.pressed = True\n        but = self.CS.cruise_buttons\n      else:\n        be.pressed = False\n        but = self.CS.prev_cruise_buttons\n      if but == CruiseButtons.RES_ACCEL:\n        if not (ret.cruiseState.enabled and ret.standstill):\n          be.type = ButtonType.accelCruise  # Suppress resume button if we're resuming from stop so we don't adjust speed.\n      elif but == CruiseButtons.DECEL_SET:\n        be.type = ButtonType.decelCruise\n      elif but == CruiseButtons.CANCEL:\n        be.type = ButtonType.cancel\n      elif but == CruiseButtons.MAIN:\n        be.type = ButtonType.altButton3\n      buttonEvents.append(be)\n\n    ret.buttonEvents = buttonEvents\n\n    events = self.create_common_events(ret, pcm_enable=False)\n\n    if ret.vEgo < self.CP.minEnableSpeed:\n      events.add(EventName.belowEngageSpeed)\n    if self.CS.park_brake:\n      events.add(EventName.parkBrake)\n    if ret.cruiseState.standstill:\n      events.add(EventName.resumeRequired)\n    if self.CS.pcm_acc_status == AccState.FAULTED:\n      events.add(EventName.accFaulted)\n    if ret.vEgo < self.CP.minSteerSpeed:\n      events.add(car.CarEvent.EventName.belowSteerSpeed)\n\n    # handle button presses\n    for b in ret.buttonEvents:\n      # do enable on both accel and decel buttons\n      if b.type in [ButtonType.accelCruise, ButtonType.decelCruise] and not b.pressed:\n        events.add(EventName.buttonEnable)\n      # do disable on button down\n      if b.type == ButtonType.cancel and b.pressed:\n        events.add(EventName.buttonCancel)\n\n    ret.events = events.to_msg()\n\n    # copy back carState packet to CS\n    self.CS.out = ret.as_reader()\n\n    return self.CS.out\n\n  def apply(self, c):\n    hud_v_cruise = c.hudControl.setSpeed\n    if hud_v_cruise > 70:\n      hud_v_cruise = 0\n\n    # For Openpilot, \"enabled\" includes pre-enable.\n    # In GM, PCM faults out if ACC command overlaps user gas.\n    enabled = c.enabled and not self.CS.out.gasPressed\n\n    can_sends = self.CC.update(enabled, self.CS, self.frame,\n                               c.actuators,\n                               hud_v_cruise, c.hudControl.lanesVisible,\n                               c.hudControl.leadVisible, c.hudControl.visualAlert, self.dragonconf)\n\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/gm/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom __future__ import print_function\nimport math\nfrom cereal import car\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.gm.values import DBC, CAR, CanBus\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nRADAR_HEADER_MSG = 1120\nSLOT_1_MSG = RADAR_HEADER_MSG + 1\nNUM_SLOTS = 20\n\n# Actually it's 0x47f, but can parser only reports\n# messages that are present in DBC\nLAST_RADAR_MSG = RADAR_HEADER_MSG + NUM_SLOTS\n\ndef create_radar_can_parser(car_fingerprint):\n  if car_fingerprint not in (CAR.VOLT, CAR.MALIBU, CAR.HOLDEN_ASTRA, CAR.ACADIA, CAR.CADILLAC_ATS):\n    return None\n\n  # C1A-ARS3-A by Continental\n  radar_targets = list(range(SLOT_1_MSG, SLOT_1_MSG + NUM_SLOTS))\n  signals = list(zip(['FLRRNumValidTargets',\n                 'FLRRSnsrBlckd', 'FLRRYawRtPlsblityFlt',\n                 'FLRRHWFltPrsntInt', 'FLRRAntTngFltPrsnt',\n                 'FLRRAlgnFltPrsnt', 'FLRRSnstvFltPrsntInt'] +\n                ['TrkRange'] * NUM_SLOTS + ['TrkRangeRate'] * NUM_SLOTS +\n                ['TrkRangeAccel'] * NUM_SLOTS + ['TrkAzimuth'] * NUM_SLOTS +\n                ['TrkWidth'] * NUM_SLOTS + ['TrkObjectID'] * NUM_SLOTS,\n                [RADAR_HEADER_MSG] * 7 + radar_targets * 6,\n                [0] * 7 +\n                [0.0] * NUM_SLOTS + [0.0] * NUM_SLOTS +\n                [0.0] * NUM_SLOTS + [0.0] * NUM_SLOTS +\n                [0.0] * NUM_SLOTS + [0] * NUM_SLOTS))\n\n  checks = list({(s[1], 14) for s in signals})\n\n  return CANParser(DBC[car_fingerprint]['radar'], signals, checks, CanBus.OBSTACLE)\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n\n    self.rcp = create_radar_can_parser(CP.carFingerprint)\n\n    self.trigger_msg = LAST_RADAR_MSG\n    self.updated_messages = set()\n    self.radar_ts = CP.radarTimeStep\n\n  def update(self, can_strings):\n    if self.rcp is None:\n      return super().update(None)\n\n    vls = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(vls)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    ret = car.RadarData.new_message()\n    header = self.rcp.vl[RADAR_HEADER_MSG]\n    fault = header['FLRRSnsrBlckd'] or header['FLRRSnstvFltPrsntInt'] or \\\n      header['FLRRYawRtPlsblityFlt'] or header['FLRRHWFltPrsntInt'] or \\\n      header['FLRRAntTngFltPrsnt'] or header['FLRRAlgnFltPrsnt']\n    errors = []\n    if not self.rcp.can_valid:\n      errors.append(\"canError\")\n    if fault:\n      errors.append(\"fault\")\n    ret.errors = errors\n\n    currentTargets = set()\n    num_targets = header['FLRRNumValidTargets']\n\n    # Not all radar messages describe targets,\n    # no need to monitor all of the self.rcp.msgs_upd\n    for ii in self.updated_messages:\n      if ii == RADAR_HEADER_MSG:\n        continue\n\n      if num_targets == 0:\n        break\n\n      cpt = self.rcp.vl[ii]\n      # Zero distance means it's an empty target slot\n      if cpt['TrkRange'] > 0.0:\n        targetId = cpt['TrkObjectID']\n        currentTargets.add(targetId)\n        if targetId not in self.pts:\n          self.pts[targetId] = car.RadarData.RadarPoint.new_message()\n          self.pts[targetId].trackId = targetId\n        distance = cpt['TrkRange']\n        self.pts[targetId].dRel = distance  # from front of car\n        # From driver's pov, left is positive\n        self.pts[targetId].yRel = math.sin(cpt['TrkAzimuth'] * CV.DEG_TO_RAD) * distance\n        self.pts[targetId].vRel = cpt['TrkRangeRate']\n        self.pts[targetId].aRel = float('nan')\n        self.pts[targetId].yvRel = float('nan')\n\n    for oldTarget in list(self.pts.keys()):\n      if oldTarget not in currentTargets:\n        del self.pts[oldTarget]\n\n    ret.points = list(self.pts.values())\n    self.updated_messages.clear()\n    return ret\n"
  },
  {
    "path": "selfdrive/car/gm/values.py",
    "content": "# flake8: noqa\n\nfrom cereal import car\nfrom selfdrive.car import dbc_dict\nEcu = car.CarParams.Ecu\n\nclass CarControllerParams():\n  def __init__(self):\n    self.STEER_MAX = 300\n    self.STEER_STEP = 2              # how often we update the steer cmd\n    self.STEER_DELTA_UP = 7          # ~0.75s time to peak torque (255/50hz/0.75s)\n    self.STEER_DELTA_DOWN = 17       # ~0.3s from peak torque to zero\n    self.MIN_STEER_SPEED = 3.\n    self.STEER_DRIVER_ALLOWANCE = 50   # allowed driver torque before start limiting\n    self.STEER_DRIVER_MULTIPLIER = 4   # weight driver torque heavily\n    self.STEER_DRIVER_FACTOR = 100     # from dbc\n    self.NEAR_STOP_BRAKE_PHASE = 0.5  # m/s, more aggressive braking near full stop\n\n    # Takes case of \"Service Adaptive Cruise\" and \"Service Front Camera\"\n    # dashboard messages.\n    self.ADAS_KEEPALIVE_STEP = 100\n    self.CAMERA_KEEPALIVE_STEP = 100\n\n    # pedal lookups, only for Volt\n    MAX_GAS = 3072              # Only a safety limit\n    ZERO_GAS = 2048\n    MAX_BRAKE = 350             # Should be around 3.5m/s^2, including regen\n\n    self.ACCEL_MAX = 2.0 # m/s^2\n\n    # Allow small margin below -3.5 m/s^2 from ISO 15622:2018 since we\n    # perform the closed loop control, and might need some\n    # to apply some more braking if we're on a downhill slope.\n    # Our controller should still keep the 2 second average above\n    # -3.5 m/s^2 as per planner limits\n    self.ACCEL_MIN = -4.0 # m/s^2\n\n    self.MAX_ACC_REGEN = 1404  # ACC Regen braking is slightly less powerful than max regen paddle\n    self.GAS_LOOKUP_BP = [-1.0, 0., self.ACCEL_MAX]\n    self.GAS_LOOKUP_V = [self.MAX_ACC_REGEN, ZERO_GAS, MAX_GAS]\n    self.BRAKE_LOOKUP_BP = [self.ACCEL_MIN, -1.0]\n    self.BRAKE_LOOKUP_V = [MAX_BRAKE, 0]\n\nclass CAR:\n  HOLDEN_ASTRA = \"HOLDEN ASTRA RS-V BK 2017\"\n  VOLT = \"CHEVROLET VOLT PREMIER 2017\"\n  CADILLAC_ATS = \"CADILLAC ATS Premium Performance 2018\"\n  MALIBU = \"CHEVROLET MALIBU PREMIER 2017\"\n  ACADIA = \"GMC ACADIA DENALI 2018\"\n  BUICK_REGAL = \"BUICK REGAL ESSENCE 2018\"\n\nclass CruiseButtons:\n  INIT = 0\n  UNPRESS = 1\n  RES_ACCEL = 2\n  DECEL_SET = 3\n  MAIN = 5\n  CANCEL = 6\n\nclass AccState:\n  OFF = 0\n  ACTIVE = 1\n  FAULTED = 3\n  STANDSTILL = 4\n\nclass CanBus:\n  POWERTRAIN = 0\n  OBSTACLE = 1\n  CHASSIS = 2\n  SW_GMLAN = 3\n\nFINGERPRINTS = {\n  # Astra BK MY17, ASCM unplugged\n  CAR.HOLDEN_ASTRA: [{\n    190: 8, 193: 8, 197: 8, 199: 4, 201: 8, 209: 7, 211: 8, 241: 6, 249: 8, 288: 5, 298: 8, 304: 1, 309: 8, 311: 8, 313: 8, 320: 3, 328: 1, 352: 5, 381: 6, 384: 4, 386: 8, 388: 8, 393: 8, 398: 8, 401: 8, 413: 8, 417: 8, 419: 8, 422: 1, 426: 7, 431: 8, 442: 8, 451: 8, 452: 8, 453: 8, 455: 7, 456: 8, 458: 5, 479: 8, 481: 7, 485: 8, 489: 8, 497: 8, 499: 3, 500: 8, 501: 8, 508: 8, 528: 5, 532: 6, 554: 3, 560: 8, 562: 8, 563: 5, 564: 5, 565: 5, 567: 5, 647: 5, 707: 8, 715: 8, 723: 8, 753: 5, 761: 7, 806: 1, 810: 8, 840: 5, 842: 5, 844: 8, 866: 4, 961: 8, 969: 8, 977: 8, 979: 8, 985: 5, 1001: 8, 1009: 8, 1011: 6, 1017: 8, 1019: 3, 1020: 8, 1105: 6, 1217: 8, 1221: 5, 1225: 8, 1233: 8, 1249: 8, 1257: 6, 1259: 8, 1261: 7, 1263: 4, 1265: 8, 1267: 8, 1280: 4, 1300: 8, 1328: 4, 1417: 8, 1906: 7, 1907: 7, 1908: 7, 1912: 7, 1919: 7,\n  }],\n  CAR.VOLT: [\n  # Volt Premier w/ ACC 2017\n  {\n    170: 8, 171: 8, 189: 7, 190: 6, 193: 8, 197: 8, 199: 4, 201: 8, 209: 7, 211: 2, 241: 6, 288: 5, 289: 8, 298: 8, 304: 1, 308: 4, 309: 8, 311: 8, 313: 8, 320: 3, 328: 1, 352: 5, 381: 6, 384: 4, 386: 8, 388: 8, 389: 2, 390: 7, 417: 7, 419: 1, 426: 7, 451: 8, 452: 8, 453: 6, 454: 8, 456: 8, 479: 3, 481: 7, 485: 8, 489: 8, 493: 8, 495: 4, 497: 8, 499: 3, 500: 6, 501: 8, 508: 8, 528: 4, 532: 6, 546: 7, 550: 8, 554: 3, 558: 8, 560: 8, 562: 8, 563: 5, 564: 5, 565: 5, 566: 5, 567: 3, 568: 1, 573: 1, 577: 8, 647: 3, 707: 8, 711: 6, 715: 8, 761: 7, 810: 8, 840: 5, 842: 5, 844: 8, 866: 4, 961: 8, 969: 8, 977: 8, 979: 7, 988: 6, 989: 8, 995: 7, 1001: 8, 1005: 6, 1009: 8, 1017: 8, 1019: 2, 1020: 8, 1105: 6, 1187: 4, 1217: 8, 1221: 5, 1223: 3, 1225: 7, 1227: 4, 1233: 8, 1249: 8, 1257: 6, 1265: 8, 1267: 1, 1273: 3, 1275: 3, 1280: 4, 1300: 8, 1322: 6, 1323: 4, 1328: 4, 1417: 8, 1601: 8, 1905: 7, 1906: 7, 1907: 7, 1910: 7, 1912: 7, 1922: 7, 1927: 7, 1928: 7, 2016: 8, 2020: 8, 2024: 8, 2028: 8\n  },\n  # Volt Premier w/ ACC 2018\n  {\n    170: 8, 171: 8, 189: 7, 190: 6, 193: 8, 197: 8, 199: 4, 201: 8, 209: 7, 211: 2, 241: 6, 288: 5, 298: 8, 304: 1, 308: 4, 309: 8, 311: 8, 313: 8, 320: 3, 328: 1, 352: 5, 381: 6, 384: 4, 386: 8, 388: 8, 389: 2, 390: 7, 417: 7, 419: 1, 426: 7, 451: 8, 452: 8, 453: 6, 454: 8, 456: 8, 479: 3, 481: 7, 485: 8, 489: 8, 493: 8, 495: 4, 497: 8, 499: 3, 500: 6, 501: 8, 508: 8, 528: 4, 532: 6, 546: 7, 550: 8, 554: 3, 558: 8, 560: 8, 562: 8, 563: 5, 564: 5, 565: 5, 566: 5, 567: 3, 568: 1, 573: 1, 577: 8, 578: 8, 608: 8, 609: 6, 610: 6, 611: 6, 612: 8, 613: 8, 647: 3, 707: 8, 711: 6, 715: 8, 717: 5, 761: 7, 810: 8, 840: 5, 842: 5, 844: 8, 866: 4, 869: 4, 880: 6, 961: 8, 967: 4, 969: 8, 977: 8, 979: 7, 988: 6, 989: 8, 995: 7, 1001: 8, 1005: 6, 1009: 8, 1017: 8, 1019: 2, 1020: 8, 1033: 7, 1034: 7, 1105: 6, 1187: 4, 1217: 8, 1221: 5, 1223: 3, 1225: 7, 1227: 4, 1233: 8, 1249: 8, 1257: 6, 1265: 8, 1267: 1, 1273: 3, 1275: 3, 1280: 4, 1296: 4, 1300: 8, 1322: 6, 1323: 4, 1328: 4, 1417: 8, 1516: 8, 1601: 8, 1618: 8, 1905: 7, 1906: 7, 1907: 7, 1910: 7, 1912: 7, 1922: 7, 1927: 7, 1930: 7, 2016: 8, 2018: 8, 2020: 8, 2024: 8, 2028: 8\n  }],\n  CAR.BUICK_REGAL : [\n  # Regal TourX Essence w/ ACC 2018\n  {\n    190: 8, 193: 8, 197: 8, 199: 4, 201: 8, 209: 7, 211: 8, 241: 6, 249: 8, 288: 5, 298: 8, 304: 1, 309: 8, 311: 8, 313: 8, 320: 3, 322: 7, 328: 1, 352: 5, 381: 6, 384: 4, 386: 8, 388: 8, 393: 7, 398: 8, 407: 7, 413: 8, 417: 8, 419: 8, 422: 4, 426: 8, 431: 8, 442: 8, 451: 8, 452: 8, 453: 8, 455: 7, 456: 8, 463: 3, 479: 8, 481: 7, 485: 8, 487: 8, 489: 8, 495: 8, 497: 8, 499: 3, 500: 8, 501: 8, 508: 8, 528: 5, 532: 6, 554: 3, 560: 8, 562: 8, 563: 5, 564: 5, 565: 5, 567: 5, 569: 3, 573: 1, 577: 8, 578: 8, 579: 8, 587: 8, 608: 8, 609: 6, 610: 6, 611: 6, 612: 8, 613: 8, 647: 3, 707: 8, 715: 8, 717: 5, 753: 5, 761: 7, 810: 8, 840: 5, 842: 5, 844: 8, 866: 4, 869: 4, 880: 6, 882: 8, 884: 8, 890: 1, 892: 2, 893: 2, 894: 1, 961: 8, 967: 8, 969: 8, 977: 8, 979: 8, 985: 8, 1001: 8, 1005: 6, 1009: 8, 1011: 8, 1013: 3, 1017: 8, 1020: 8, 1024: 8, 1025: 8, 1026: 8, 1027: 8, 1028: 8, 1029: 8, 1030: 8, 1031: 8, 1032: 2, 1033: 7, 1034: 7, 1105: 6, 1217: 8, 1221: 5, 1223: 8, 1225: 7, 1233: 8, 1249: 8, 1257: 6, 1259: 8, 1261: 8, 1263: 8, 1265: 8, 1267: 8, 1271: 8, 1280: 4, 1296: 4, 1300: 8, 1322: 6, 1328: 4, 1417: 8, 1601: 8, 1602: 8, 1603: 7, 1611: 8, 1618: 8, 1906: 8, 1907: 7, 1912: 7, 1914: 7, 1916: 7, 1919: 7, 1930: 7, 2016: 8, 2018: 8, 2019: 8, 2024: 8, 2026: 8\n  }],\n  CAR.CADILLAC_ATS: [\n  # Cadillac ATS Coupe Premium Performance 3.6L RWD w/ ACC 2018\n  {\n    190: 6, 193: 8, 197: 8, 199: 4, 201: 8, 209: 7, 211: 2, 241: 6, 249: 8, 288: 5, 298: 8, 304: 1, 309: 8, 311: 8, 313: 8, 320: 3, 322: 7, 328: 1, 352: 5, 368: 3, 381: 6, 384: 4, 386: 8, 388: 8, 393: 7, 398: 8, 401: 8, 407: 7, 413: 8, 417: 7, 419: 1, 422: 4, 426: 7, 431: 8, 442: 8, 451: 8, 452: 8, 453: 6, 455: 7, 456: 8, 462: 4, 479: 3, 481: 7, 485: 8, 487: 8, 489: 8, 491: 2, 493: 8, 497: 8, 499: 3, 500: 6, 501: 8, 508: 8, 510: 8, 528: 5, 532: 6, 534: 2, 554: 3, 560: 8, 562: 8, 563: 5, 564: 5, 565: 5, 567: 5, 573: 1, 577: 8, 608: 8, 609: 6, 610: 6, 611: 6, 612: 8, 613: 8, 647: 6, 707: 8, 715: 8, 717: 5, 719: 5, 723: 2, 753: 5, 761: 7, 801: 8, 804: 3, 810: 8, 840: 5, 842: 5, 844: 8, 866: 4, 869: 4, 880: 6, 882: 8, 890: 1, 892: 2, 893: 2, 894: 1, 961: 8, 967: 4, 969: 8, 977: 8, 979: 8, 985: 5, 1001: 8, 1005: 6, 1009: 8, 1011: 6, 1013: 3, 1017: 8, 1019: 2, 1020: 8, 1033: 7, 1034: 7, 1105: 6, 1217: 8, 1221: 5, 1223: 3, 1225: 7, 1233: 8, 1241: 3, 1249: 8, 1257: 6, 1259: 8, 1261: 7, 1263: 4, 1265: 8, 1267: 1, 1271: 8, 1280: 4, 1296: 4, 1300: 8, 1322: 6, 1323: 4, 1328: 4, 1417: 8, 1601: 8, 1904: 7, 1906: 7, 1907: 7, 1912: 7, 1916: 7, 1917: 7, 1918: 7, 1919: 7, 1920: 7, 1930: 7, 2016: 8, 2024: 8\n  }],\n  CAR.MALIBU: [\n  # Malibu Premier w/ ACC 2017\n  {\n    190: 6, 193: 8, 197: 8, 199: 4, 201: 8, 209: 7, 211: 2, 241: 6, 249: 8, 288: 5, 298: 8, 304: 1, 309: 8, 311: 8, 313: 8, 320: 3, 328: 1, 352: 5, 381: 6, 384: 4, 386: 8, 388: 8, 393: 7, 398: 8, 407: 7, 413: 8, 417: 7, 419: 1, 422: 4, 426: 7, 431: 8, 442: 8, 451: 8, 452: 8, 453: 6, 455: 7, 456: 8, 479: 3, 481: 7, 485: 8, 487: 8, 489: 8, 495: 4, 497: 8, 499: 3, 500: 6, 501: 8, 508: 8, 510: 8, 528: 5, 532: 6, 554: 3, 560: 8, 562: 8, 563: 5, 564: 5, 565: 5, 567: 5, 573: 1, 577: 8, 608: 8, 609: 6, 610: 6, 611: 6, 612: 8, 613: 8, 647: 6, 707: 8, 715: 8, 717: 5, 753: 5, 761: 7, 810: 8, 840: 5, 842: 5, 844: 8, 866: 4, 869: 4, 880: 6, 961: 8, 969: 8, 977: 8, 979: 8, 985: 5, 1001: 8, 1005: 6, 1009: 8, 1013: 3, 1017: 8, 1019: 2, 1020: 8, 1033: 7, 1034: 7, 1105: 6, 1217: 8, 1221: 5, 1223: 2, 1225: 7, 1233: 8, 1249: 8, 1257: 6, 1265: 8, 1267: 1, 1280: 4, 1296: 4, 1300: 8, 1322: 6, 1323: 4, 1328: 4, 1417: 8, 1601: 8, 1906: 7, 1907: 7, 1912: 7, 1919: 7, 1930: 7, 2016: 8, 2024: 8,\n  }],\n  CAR.ACADIA: [\n  # Acadia Denali w/ACC 2018\n  {\n    190: 6, 192: 5, 193: 8, 197: 8, 199: 4, 201: 6, 208: 8, 209: 7, 211: 2, 241: 6, 249: 8, 288: 5, 289: 1, 290: 1, 298: 8, 304: 8, 309: 8, 313: 8, 320: 8, 322: 7, 328: 1, 352: 7, 368: 8, 381: 8, 384: 8, 386: 8, 388: 8, 393: 8, 398: 8, 413: 8, 417: 7, 419: 1, 422: 4, 426: 7, 431: 8, 442: 8, 451: 8, 452: 8, 453: 6, 454: 8, 455: 7, 458: 8, 460: 4, 462: 4, 463: 3, 479: 3, 481: 7, 485: 8, 489: 5, 497: 8, 499: 3, 500: 6, 501: 8, 508: 8, 510: 8, 512: 3, 530: 8, 532: 6, 534: 2, 554: 3, 560: 8, 562: 8, 563: 5, 564: 5, 567: 5, 568: 2, 573: 1, 608: 8, 609: 6, 610: 6, 611: 6, 612: 8, 613: 8, 647: 6, 707: 8, 715: 8, 717: 5, 753: 5, 761: 7, 789: 5, 800: 6, 801: 8, 803: 8, 804: 3, 805: 8, 832: 8, 840: 5, 842: 5, 844: 8, 866: 4, 869: 4, 880: 6, 961: 8, 969: 8, 977: 8, 979: 8, 985: 5, 1001: 8, 1003: 5, 1005: 6, 1009: 8, 1017: 8, 1020: 8, 1033: 7, 1034: 7, 1105: 6, 1217: 8, 1221: 5, 1225: 8, 1233: 8, 1249: 8, 1257: 6, 1265: 8, 1267: 1, 1280: 4, 1296: 4, 1300: 8, 1322: 6, 1328: 4, 1417: 8, 1906: 7, 1907: 7, 1912: 7, 1914: 7, 1918: 7, 1919: 7, 1920: 7, 1930: 7\n  },\n  # Acadia Denali w/ /ACC 2018\n  {\n    190: 6, 193: 8, 197: 8, 199: 4, 201: 8, 208: 8, 209: 7, 211: 2, 241: 6, 249: 8, 288: 5, 289: 8, 298: 8, 304: 1, 309: 8, 313: 8, 320: 3, 322: 7, 328: 1, 338: 6, 340: 6, 352: 5, 381: 8, 384: 4, 386: 8, 388: 8, 393: 8, 398: 8, 413: 8, 417: 7, 419: 1, 422: 4, 426: 7, 431: 8, 442: 8, 451: 8, 452: 8, 453: 6, 454: 8, 455: 7, 462: 4, 463: 3, 479: 3, 481: 7, 485: 8, 489: 8, 497: 8, 499: 3, 500: 6, 501: 8, 508: 8, 510: 8, 532: 6, 554: 3, 560: 8, 562: 8, 563: 5, 564: 5, 567: 5, 573: 1, 577: 8, 608: 8, 609: 6, 610: 6, 611: 6, 612: 8, 613: 8, 647: 6, 707: 8, 715: 8, 717: 5, 753: 5, 761: 7, 840: 5, 842: 5, 844: 8, 866: 4, 869: 4, 880: 6, 961: 8, 969: 8, 977: 8, 979: 8, 985: 5, 1001: 8, 1005: 6, 1009: 8, 1017: 8, 1020: 8, 1033: 7, 1034: 7, 1105: 6, 1217: 8, 1221: 5, 1225: 8, 1233: 8, 1249: 8, 1257: 6, 1265: 8, 1267: 1, 1280: 4, 1296: 4, 1300: 8, 1322: 6, 1328: 4, 1417: 8, 1601: 8, 1906: 7, 1907: 7, 1912: 7, 1914: 7, 1919: 7, 1920: 7, 1930: 7, 2016: 8, 2024: 8\n  }],\n}\n\nSTEER_THRESHOLD = 1.0\n\nDBC = {\n  CAR.HOLDEN_ASTRA: dbc_dict('gm_global_a_powertrain', 'gm_global_a_object', chassis_dbc='gm_global_a_chassis'),\n  CAR.VOLT: dbc_dict('gm_global_a_powertrain', 'gm_global_a_object', chassis_dbc='gm_global_a_chassis'),\n  CAR.MALIBU: dbc_dict('gm_global_a_powertrain', 'gm_global_a_object', chassis_dbc='gm_global_a_chassis'),\n  CAR.ACADIA: dbc_dict('gm_global_a_powertrain', 'gm_global_a_object', chassis_dbc='gm_global_a_chassis'),\n  CAR.CADILLAC_ATS: dbc_dict('gm_global_a_powertrain', 'gm_global_a_object', chassis_dbc='gm_global_a_chassis'),\n  CAR.BUICK_REGAL: dbc_dict('gm_global_a_powertrain', 'gm_global_a_object', chassis_dbc='gm_global_a_chassis'),\n}\n"
  },
  {
    "path": "selfdrive/car/honda/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/honda/carcontroller.py",
    "content": "from collections import namedtuple\nfrom cereal import car\nfrom common.realtime import DT_CTRL\nfrom selfdrive.controls.lib.drive_helpers import rate_limit\nfrom common.numpy_fast import clip, interp\nfrom selfdrive.car import create_gas_command\nfrom selfdrive.car.honda import hondacan\nfrom selfdrive.car.honda.values import CruiseButtons, VISUAL_HUD, HONDA_BOSCH, HONDA_NIDEC_ALT_PCM_ACCEL, CarControllerParams, CAR\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\nLongCtrlState = car.CarControl.Actuators.LongControlState\n\ndef compute_gb_honda_bosch(accel, speed):\n  #TODO returns 0s, is unused\n  return 0.0, 0.0\n\n\ndef compute_gb_honda_nidec(accel, speed):\n  creep_brake = 0.0\n  creep_speed = 2.3\n  creep_brake_value = 0.15\n  if speed < creep_speed:\n    creep_brake = (creep_speed - speed) / creep_speed * creep_brake_value\n  gb = float(accel) / 4.8 - creep_brake\n  return clip(gb, 0.0, 1.0), clip(-gb, 0.0, 1.0)\n\n\ndef compute_gas_brake(accel, speed, fingerprint):\n  if fingerprint in HONDA_BOSCH:\n    return compute_gb_honda_bosch(accel, speed)\n  else:\n    return compute_gb_honda_nidec(accel, speed)\n\n\n#TODO not clear this does anything useful\ndef actuator_hystereses(brake, braking, brake_steady, v_ego, car_fingerprint):\n  # hyst params\n  brake_hyst_on = 0.02     # to activate brakes exceed this value\n  brake_hyst_off = 0.005   # to deactivate brakes below this value\n  brake_hyst_gap = 0.01    # don't change brake command for small oscillations within this value\n\n  #*** hysteresis logic to avoid brake blinking. go above 0.1 to trigger\n  if (brake < brake_hyst_on and not braking) or brake < brake_hyst_off:\n    brake = 0.\n  braking = brake > 0.\n\n  # for small brake oscillations within brake_hyst_gap, don't change the brake command\n  if brake == 0.:\n    brake_steady = 0.\n  elif brake > brake_steady + brake_hyst_gap:\n    brake_steady = brake - brake_hyst_gap\n  elif brake < brake_steady - brake_hyst_gap:\n    brake_steady = brake + brake_hyst_gap\n  brake = brake_steady\n\n  return brake, braking, brake_steady\n\n\ndef brake_pump_hysteresis(apply_brake, apply_brake_last, last_pump_ts, ts):\n  pump_on = False\n\n  # reset pump timer if:\n  # - there is an increment in brake request\n  # - we are applying steady state brakes and we haven't been running the pump\n  #   for more than 20s (to prevent pressure bleeding)\n  if apply_brake > apply_brake_last or (ts - last_pump_ts > 20. and apply_brake > 0):\n    last_pump_ts = ts\n\n  # once the pump is on, run it for at least 0.2s\n  if ts - last_pump_ts < 0.2 and apply_brake > 0:\n    pump_on = True\n\n  return pump_on, last_pump_ts\n\n\ndef process_hud_alert(hud_alert):\n  # initialize to no alert\n  fcw_display = 0\n  steer_required = 0\n  acc_alert = 0\n\n  # priority is: FCW, steer required, all others\n  if hud_alert == VisualAlert.fcw:\n    fcw_display = VISUAL_HUD[hud_alert.raw]\n  elif hud_alert in [VisualAlert.steerRequired, VisualAlert.ldw]:\n    steer_required = VISUAL_HUD[hud_alert.raw]\n  else:\n    acc_alert = VISUAL_HUD[hud_alert.raw]\n\n  return fcw_display, steer_required, acc_alert\n\n\nHUDData = namedtuple(\"HUDData\",\n                     [\"pcm_accel\", \"v_cruise\", \"car\",\n                     \"lanes\", \"fcw\", \"acc_alert\", \"steer_required\", \"dashed_lanes\"])\n\n\nclass CarController():\n  def rough_speed(self, lead_distance):\n    if self.prev_lead_distance != lead_distance:\n      self.lead_distance_counter_prev = self.lead_distance_counter\n      self.rough_lead_speed += 0.3334 * (\n              (lead_distance - self.prev_lead_distance) / self.lead_distance_counter_prev - self.rough_lead_speed)\n      self.lead_distance_counter = 0.0\n    elif self.lead_distance_counter >= self.lead_distance_counter_prev:\n      self.rough_lead_speed = (self.lead_distance_counter * self.rough_lead_speed) / (self.lead_distance_counter + 1.0)\n    self.lead_distance_counter += 1.0\n    self.prev_lead_distance = lead_distance\n    return self.rough_lead_speed\n\n\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n    self.prev_lead_distance = 0.0\n    self.stopped_lead_distance = 0.0\n    self.lead_distance_counter = 1\n    self.lead_distance_counter_prev = 1\n    self.rough_lead_speed = 0.0\n\n    self.braking = False\n    self.brake_steady = 0.\n    self.brake_last = 0.\n    self.apply_brake_last = 0\n    self.last_pump_ts = 0.\n    self.packer = CANPacker(dbc_name)\n\n    self.params = CarControllerParams(CP)\n\n  def update(self, enabled, CS, frame, actuators,\n             pcm_speed, pcm_override, pcm_cancel_cmd, pcm_accel,\n             hud_v_cruise, hud_show_lanes, dragonconf, hud_show_car, hud_alert):\n\n    P = self.params\n\n    if enabled:\n      accel = actuators.accel\n      gas, brake = compute_gas_brake(actuators.accel, CS.out.vEgo, CS.CP.carFingerprint)\n    else:\n      accel = 0.0\n      gas, brake = 0.0, 0.0\n\n    # *** apply brake hysteresis ***\n    pre_limit_brake, self.braking, self.brake_steady = actuator_hystereses(brake, self.braking, self.brake_steady, CS.out.vEgo, CS.CP.carFingerprint)\n\n    # *** no output if not enabled ***\n    if not enabled and CS.out.cruiseState.enabled:\n      # send pcm acc cancel cmd if drive is disabled but pcm is still on, or if the system can't be activated\n      pcm_cancel_cmd = True\n\n    # Never send cancel command if we never enter cruise state (no cruise if pedal)\n    # Cancel cmd causes brakes to release at a standstill causing grinding\n    pcm_cancel_cmd = pcm_cancel_cmd and CS.CP.pcmCruise\n\n    # *** rate limit after the enable check ***\n    self.brake_last = rate_limit(pre_limit_brake, self.brake_last, -2., DT_CTRL)\n\n    # vehicle hud display, wait for one update from 10Hz 0x304 msg\n    if hud_show_lanes and CS.lkMode:\n      hud_lanes = 1\n    else:\n      hud_lanes = 0\n\n    if enabled:\n      if hud_show_car:\n        hud_car = 2\n      else:\n        hud_car = 1\n    else:\n      hud_car = 0\n\n    fcw_display, steer_required, acc_alert = process_hud_alert(hud_alert)\n\n\n    # **** process the car messages ****\n\n    # steer torque is converted back to CAN reference (positive when steering right)\n    apply_steer = int(interp(-actuators.steer * P.STEER_MAX, P.STEER_LOOKUP_BP, P.STEER_LOOKUP_V))\n\n    lkas_active = enabled and not CS.steer_not_allowed and CS.lkMode\n\n    # Send CAN commands.\n    can_sends = []\n\n    # tester present - w/ no response (keeps radar disabled)\n    if CS.CP.carFingerprint in HONDA_BOSCH and CS.CP.openpilotLongitudinalControl:\n      if (frame % 10) == 0:\n        can_sends.append((0x18DAB0F1, 0, b\"\\x02\\x3E\\x80\\x00\\x00\\x00\\x00\\x00\", 1))\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_steer = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_steer, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    # Send steering command.\n    idx = frame % 4\n    can_sends.append(hondacan.create_steering_control(self.packer, apply_steer,\n      lkas_active, CS.CP.carFingerprint, idx, CS.CP.openpilotLongitudinalControl))\n\n    stopping = actuators.longControlState == LongCtrlState.stopping\n    starting = actuators.longControlState == LongCtrlState.starting\n\n    # Prevent rolling backwards\n    accel = -4.0 if stopping else accel\n\n    # wind brake from air resistance decel at high speed\n    wind_brake = interp(CS.out.vEgo, [0.0, 2.3, 35.0], [0.001, 0.002, 0.15])\n    # all of this is only relevant for HONDA NIDEC\n    max_accel = interp(CS.out.vEgo, P.NIDEC_MAX_ACCEL_BP, P.NIDEC_MAX_ACCEL_V)\n    # TODO this 1.44 is just to maintain previous behavior\n    pcm_speed_BP = [-wind_brake,\n                    -wind_brake*(3/4),\n                      0.0,\n                      0.5]\n    # The Honda ODYSSEY seems to have different PCM_ACCEL\n    # msgs, is it other cars too?\n    if CS.CP.carFingerprint in HONDA_NIDEC_ALT_PCM_ACCEL:\n      pcm_speed_V = [0.0,\n                     clip(CS.out.vEgo - 3.0, 0.0, 100.0),\n                     clip(CS.out.vEgo + 0.0, 0.0, 100.0),\n                     clip(CS.out.vEgo + 5.0, 0.0, 100.0)]\n      pcm_accel = int((1.0) * 0xc6)\n    else:\n      pcm_speed_V = [0.0,\n                     clip(CS.out.vEgo - 2.0, 0.0, 100.0),\n                     clip(CS.out.vEgo + 2.0, 0.0, 100.0),\n                     clip(CS.out.vEgo + 5.0, 0.0, 100.0)]\n      pcm_accel = int(clip((accel/1.44)/max_accel, 0.0, 1.0) * 0xc6)\n\n    pcm_speed = interp(gas-brake, pcm_speed_BP, pcm_speed_V)\n\n    if not CS.CP.openpilotLongitudinalControl:\n      if (frame % 2) == 0:\n        idx = frame // 2\n        can_sends.append(hondacan.create_bosch_supplemental_1(self.packer, CS.CP.carFingerprint, idx))\n      # If using stock ACC, spam cancel command to kill gas when OP disengages.\n      if not dragonconf.dpAllowGas and pcm_cancel_cmd:\n        can_sends.append(hondacan.spam_buttons_command(self.packer, CruiseButtons.CANCEL, idx, CS.CP.carFingerprint))\n      elif CS.out.cruiseState.standstill:\n        if CS.CP.carFingerprint in (CAR.ACCORD, CAR.ACCORDH, CAR.INSIGHT):\n          rough_lead_speed = self.rough_speed(CS.lead_distance)\n          if CS.lead_distance > (self.stopped_lead_distance + 15.0) or rough_lead_speed > 0.1:\n            self.stopped_lead_distance = 0.0\n            can_sends.append(\n              hondacan.spam_buttons_command(self.packer, CruiseButtons.RES_ACCEL, idx, CS.CP.carFingerprint))\n        elif CS.CP.carFingerprint in (CAR.CIVIC_BOSCH, CAR.CRV_HYBRID):\n          if CS.hud_lead == 1:\n            can_sends.append(hondacan.spam_buttons_command(self.packer, CruiseButtons.RES_ACCEL, idx, CS.CP.carFingerprint))\n        else:\n          can_sends.append(hondacan.spam_buttons_command(self.packer, CruiseButtons.RES_ACCEL, idx, CS.CP.carFingerprint))\n      else:\n        self.stopped_lead_distance = CS.lead_distance\n        self.prev_lead_distance = CS.lead_distance\n\n    else:\n      # Send gas and brake commands.\n      if (frame % 2) == 0:\n        idx = frame // 2\n        ts = frame * DT_CTRL\n\n        if dragonconf.dpAtl and dragonconf.dpAtlOpLong and not CS.out.cruiseActualEnabled:\n          accel = 0.\n          gas = 0.\n          self.brake_last = 0.\n\n        if dragonconf.dpAtl and not dragonconf.dpAtlOpLong:\n          pass\n        elif  CS.CP.carFingerprint in HONDA_BOSCH:\n          bosch_gas = interp(accel, P.BOSCH_GAS_LOOKUP_BP, P.BOSCH_GAS_LOOKUP_V)\n          can_sends.extend(hondacan.create_acc_commands(self.packer, enabled, accel, bosch_gas, idx, stopping, starting, CS.CP.carFingerprint))\n\n        else:\n          apply_brake = clip(self.brake_last - wind_brake, 0.0, 1.0)\n          apply_brake = int(clip(apply_brake * P.BRAKE_MAX, 0, P.BRAKE_MAX - 1))\n          if dragonconf.dpAtl and dragonconf.dpAtlOpLong and not CS.out.cruiseActualEnabled:\n            apply_brake = 0\n          pump_on, self.last_pump_ts = brake_pump_hysteresis(apply_brake, self.apply_brake_last, self.last_pump_ts, ts)\n          can_sends.append(hondacan.create_brake_command(self.packer, apply_brake, pump_on,\n            pcm_override, pcm_cancel_cmd, fcw_display, idx, CS.CP.carFingerprint, CS.stock_brake))\n          self.apply_brake_last = apply_brake\n\n          if CS.CP.enableGasInterceptor:\n            # way too aggressive at low speed without this\n            gas_mult = interp(CS.out.vEgo, [0., 10.], [0.4, 1.0])\n            # send exactly zero if apply_gas is zero. Interceptor will send the max between read value and apply_gas.\n            # This prevents unexpected pedal range rescaling\n            apply_gas = clip(gas_mult * gas, 0., 1.)\n            can_sends.append(create_gas_command(self.packer, apply_gas, idx))\n\n    hud = HUDData(int(pcm_accel), int(round(hud_v_cruise)), hud_car,\n                  hud_lanes, fcw_display, acc_alert, steer_required, CS.lkMode)\n\n    # Send dashboard UI commands.\n    if not dragonconf.dpAtl and (frame % 10) == 0:\n      idx = (frame//10) % 4\n      can_sends.extend(hondacan.create_ui_commands(self.packer, pcm_speed, hud, CS.CP.carFingerprint, CS.is_metric, idx, CS.CP.openpilotLongitudinalControl, CS.stock_hud))\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/honda/carstate.py",
    "content": "from cereal import car\nfrom collections import defaultdict\nfrom common.numpy_fast import interp\nfrom opendbc.can.can_define import CANDefine\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import CarStateBase\nfrom selfdrive.car.honda.values import CAR, DBC, STEER_THRESHOLD, SPEED_FACTOR, HONDA_BOSCH, HONDA_BOSCH_ALT_BRAKE_SIGNAL\nfrom common.params import Params\n\nTransmissionType = car.CarParams.TransmissionType\n\n\ndef calc_cruise_offset(offset, speed):\n  # heuristic formula so that speed is controlled to ~ 0.3m/s below pid_speed\n  # constraints to solve for _K0, _K1, _K2 are:\n  # - speed = 0m/s, out = -0.3\n  # - speed = 34m/s, offset = 20, out = -0.25\n  # - speed = 34m/s, offset = -2.5, out = -1.8\n  _K0 = -0.3\n  _K1 = -0.01879\n  _K2 = 0.01013\n  return min(_K0 + _K1 * speed + _K2 * speed * offset, 0.)\n\n\ndef get_can_signals(CP, gearbox_msg=\"GEARBOX\"):\n  # this function generates lists for signal, messages and initial values\n  signals = [\n    (\"XMISSION_SPEED\", \"ENGINE_DATA\", 0),\n    (\"WHEEL_SPEED_FL\", \"WHEEL_SPEEDS\", 0),\n    (\"WHEEL_SPEED_FR\", \"WHEEL_SPEEDS\", 0),\n    (\"WHEEL_SPEED_RL\", \"WHEEL_SPEEDS\", 0),\n    (\"WHEEL_SPEED_RR\", \"WHEEL_SPEEDS\", 0),\n    (\"STEER_ANGLE\", \"STEERING_SENSORS\", 0),\n    (\"STEER_ANGLE_RATE\", \"STEERING_SENSORS\", 0),\n    (\"MOTOR_TORQUE\", \"STEER_MOTOR_TORQUE\", 0),\n    (\"STEER_TORQUE_SENSOR\", \"STEER_STATUS\", 0),\n    (\"LEFT_BLINKER\", \"SCM_FEEDBACK\", 0),\n    (\"RIGHT_BLINKER\", \"SCM_FEEDBACK\", 0),\n    (\"GEAR\", gearbox_msg, 0),\n    (\"SEATBELT_DRIVER_LAMP\", \"SEATBELT_STATUS\", 1),\n    (\"SEATBELT_DRIVER_LATCHED\", \"SEATBELT_STATUS\", 0),\n    (\"BRAKE_PRESSED\", \"POWERTRAIN_DATA\", 0),\n    (\"BRAKE_SWITCH\", \"POWERTRAIN_DATA\", 0),\n    (\"CRUISE_BUTTONS\", \"SCM_BUTTONS\", 0),\n    (\"ESP_DISABLED\", \"VSA_STATUS\", 1),\n    (\"USER_BRAKE\", \"VSA_STATUS\", 0),\n    (\"BRAKE_HOLD_ACTIVE\", \"VSA_STATUS\", 0),\n    (\"STEER_STATUS\", \"STEER_STATUS\", 5),\n    (\"GEAR_SHIFTER\", gearbox_msg, 0),\n    (\"PEDAL_GAS\", \"POWERTRAIN_DATA\", 0),\n    (\"CRUISE_SETTING\", \"SCM_BUTTONS\", 0),\n    (\"ACC_STATUS\", \"POWERTRAIN_DATA\", 0),\n    (\"HUD_LEAD\", \"ACC_HUD\", 0),\n    #dp\n    (\"ENGINE_RPM\", \"POWERTRAIN_DATA\", 0),\n  ]\n\n  checks = [\n    (\"ENGINE_DATA\", 100),\n    (\"WHEEL_SPEEDS\", 50),\n    (\"STEERING_SENSORS\", 100),\n    (\"SEATBELT_STATUS\", 10),\n    (\"CRUISE\", 10),\n    (\"POWERTRAIN_DATA\", 100),\n    (\"VSA_STATUS\", 50),\n    (\"STEER_STATUS\", 100),\n    (\"STEER_MOTOR_TORQUE\", 0), # TODO: not on every car\n  ]\n\n  if CP.carFingerprint == CAR.ODYSSEY_CHN:\n    checks += [\n      (\"SCM_FEEDBACK\", 25),\n      (\"SCM_BUTTONS\", 50),\n    ]\n  else:\n    checks += [\n      (\"SCM_FEEDBACK\", 10),\n      (\"SCM_BUTTONS\", 25),\n    ]\n\n  if CP.carFingerprint in (CAR.CRV_HYBRID, CAR.CIVIC_BOSCH_DIESEL, CAR.ACURA_RDX_3G, CAR.HONDA_E):\n    checks += [\n      (gearbox_msg, 50),\n    ]\n  else:\n    checks += [\n      (gearbox_msg, 100),\n    ]\n\n  if CP.carFingerprint in HONDA_BOSCH_ALT_BRAKE_SIGNAL:\n    signals += [(\"BRAKE_PRESSED\", \"BRAKE_MODULE\", 0)]\n    checks += [(\"BRAKE_MODULE\", 50)]\n\n  if CP.carFingerprint in HONDA_BOSCH:\n    signals += [\n      (\"CAR_GAS\", \"GAS_PEDAL_2\", 0),\n      (\"MAIN_ON\", \"SCM_FEEDBACK\", 0),\n      (\"EPB_STATE\", \"EPB_STATUS\", 0),\n    ]\n    checks += [\n      (\"EPB_STATUS\", 50),\n      (\"GAS_PEDAL_2\", 100),\n    ]\n\n    if not CP.openpilotLongitudinalControl:\n      signals += [\n        (\"CRUISE_CONTROL_LABEL\", \"ACC_HUD\", 0),\n        (\"CRUISE_SPEED\", \"ACC_HUD\", 0),\n        (\"ACCEL_COMMAND\", \"ACC_CONTROL\", 0),\n        (\"AEB_STATUS\", \"ACC_CONTROL\", 0),\n        #brakelights for HONDA BOSCH\n        (\"BRAKE_LIGHTS\", \"ACC_CONTROL\", 0),\n      ]\n      checks += [\n        (\"ACC_HUD\", 10),\n        (\"ACC_CONTROL\", 50),\n      ]\n  else:  # Nidec signals\n    signals += [(\"CRUISE_SPEED_PCM\", \"CRUISE\", 0),\n                (\"CRUISE_SPEED_OFFSET\", \"CRUISE_PARAMS\", 0)]\n\n    if CP.carFingerprint == CAR.ODYSSEY_CHN:\n      checks += [(\"CRUISE_PARAMS\", 10)]\n    else:\n      checks += [(\"CRUISE_PARAMS\", 50)]\n\n  if CP.carFingerprint in (CAR.ACCORD, CAR.ACCORDH, CAR.INSIGHT):\n    signals += [(\"DRIVERS_DOOR_OPEN\", \"SCM_FEEDBACK\", 1),\n                (\"LEAD_DISTANCE\", \"RADAR_HUD\", 0)]\n  if CP.carFingerprint in (CAR.ACCORD, CAR.ACCORDH, CAR.CIVIC_BOSCH, CAR.CIVIC_BOSCH_DIESEL, CAR.CRV_HYBRID, CAR.ACURA_RDX_3G, CAR.HONDA_E):\n    signals += [(\"DRIVERS_DOOR_OPEN\", \"SCM_FEEDBACK\", 1)]\n  elif CP.carFingerprint == CAR.ODYSSEY_CHN:\n    signals += [(\"DRIVERS_DOOR_OPEN\", \"SCM_BUTTONS\", 1)]\n  elif CP.carFingerprint in [CAR.HRV, CAR.JADE]:\n    signals += [(\"DRIVERS_DOOR_OPEN\", \"SCM_BUTTONS\", 1),\n                (\"WHEELS_MOVING\", \"STANDSTILL\", 1)]\n  else:\n    signals += [(\"DOOR_OPEN_FL\", \"DOORS_STATUS\", 1),\n                (\"DOOR_OPEN_FR\", \"DOORS_STATUS\", 1),\n                (\"DOOR_OPEN_RL\", \"DOORS_STATUS\", 1),\n                (\"DOOR_OPEN_RR\", \"DOORS_STATUS\", 1),\n                (\"WHEELS_MOVING\", \"STANDSTILL\", 1)]\n    checks += [\n      (\"DOORS_STATUS\", 3),\n      (\"STANDSTILL\", 50),\n    ]\n\n  if CP.carFingerprint == CAR.CIVIC:\n    signals += [(\"CAR_GAS\", \"GAS_PEDAL_2\", 0),\n                (\"MAIN_ON\", \"SCM_FEEDBACK\", 0),\n                (\"IMPERIAL_UNIT\", \"HUD_SETTING\", 0),\n                (\"EPB_STATE\", \"EPB_STATUS\", 0)]\n    checks += [\n      (\"HUD_SETTING\", 50),\n      (\"EPB_STATUS\", 50),\n      (\"GAS_PEDAL_2\", 100),\n    ]\n  elif CP.carFingerprint == CAR.ACURA_ILX:\n    signals += [(\"CAR_GAS\", \"GAS_PEDAL_2\", 0),\n                (\"MAIN_ON\", \"SCM_BUTTONS\", 0)]\n    checks += [\n      (\"GAS_PEDAL_2\", 100),\n    ]\n  elif CP.carFingerprint in (CAR.CRV, CAR.CRV_EU, CAR.ACURA_RDX, CAR.PILOT_2019, CAR.RIDGELINE):\n    signals += [(\"MAIN_ON\", \"SCM_BUTTONS\", 0)]\n  elif CP.carFingerprint == CAR.FIT:\n    signals += [(\"CAR_GAS\", \"GAS_PEDAL_2\", 0),\n                (\"MAIN_ON\", \"SCM_BUTTONS\", 0),\n                (\"BRAKE_HOLD_ACTIVE\", \"VSA_STATUS\", 0)]\n    checks += [\n      (\"GAS_PEDAL_2\", 100),\n    ]\n  elif CP.carFingerprint in [CAR.HRV, CAR.JADE]:\n    signals += [(\"CAR_GAS\", \"GAS_PEDAL\", 0),\n                (\"MAIN_ON\", \"SCM_BUTTONS\", 0),\n                (\"BRAKE_HOLD_ACTIVE\", \"VSA_STATUS\", 0)]\n  elif CP.carFingerprint == CAR.ODYSSEY:\n    signals += [(\"MAIN_ON\", \"SCM_FEEDBACK\", 0),\n                (\"EPB_STATE\", \"EPB_STATUS\", 0)]\n    checks += [(\"EPB_STATUS\", 50)]\n  elif CP.carFingerprint == CAR.PILOT:\n    signals += [(\"MAIN_ON\", \"SCM_BUTTONS\", 0),\n                (\"CAR_GAS\", \"GAS_PEDAL_2\", 0)]\n    checks += [\n      (\"GAS_PEDAL_2\", 0),  # TODO: fix this freq, seems this signal isn't present at all on some models\n    ]\n  elif CP.carFingerprint == CAR.ODYSSEY_CHN:\n    signals += [(\"MAIN_ON\", \"SCM_BUTTONS\", 0),\n                (\"EPB_STATE\", \"EPB_STATUS\", 0)]\n    checks += [(\"EPB_STATUS\", 50)]\n\n  # add gas interceptor reading if we are using it\n  if CP.enableGasInterceptor:\n    signals.append((\"INTERCEPTOR_GAS\", \"GAS_SENSOR\", 0))\n    signals.append((\"INTERCEPTOR_GAS2\", \"GAS_SENSOR\", 0))\n    checks.append((\"GAS_SENSOR\", 50))\n\n  if CP.openpilotLongitudinalControl:\n    signals += [\n      (\"BRAKE_ERROR_1\", \"STANDSTILL\", 1),\n      (\"BRAKE_ERROR_2\", \"STANDSTILL\", 1)\n    ]\n    checks += [(\"STANDSTILL\", 50)]\n\n  return signals, checks\n\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n    self.gearbox_msg = \"GEARBOX\"\n    if CP.carFingerprint == CAR.ACCORD and CP.transmissionType == TransmissionType.cvt:\n      self.gearbox_msg = \"GEARBOX_15T\"\n\n    self.shifter_values = can_define.dv[self.gearbox_msg][\"GEAR_SHIFTER\"]\n    self.steer_status_values = defaultdict(lambda: \"UNKNOWN\", can_define.dv[\"STEER_STATUS\"][\"STEER_STATUS\"])\n\n    self.brake_switch_prev = 0\n    self.brake_switch_prev_ts = 0\n    self.cruise_setting = 0\n    self.v_cruise_pcm_prev = 0\n\n    #dp\n    self.lkMode = True\n    self.hud_lead = 0\n    self.lead_distance = 0.\n    self.engineRPM = 0\n    self.dp_honda_kmh_display = Params().get_bool('dp_honda_kmh_display')\n\n  def update(self, cp, cp_cam, cp_body):\n    ret = car.CarState.new_message()\n\n    # car params\n    v_weight_v = [0., 1.]  # don't trust smooth speed at low values to avoid premature zero snapping\n    v_weight_bp = [1., 6.]   # smooth blending, below ~0.6m/s the smooth speed snaps to zero\n\n    # update prevs, update must run once per loop\n    self.prev_cruise_buttons = self.cruise_buttons\n    self.prev_cruise_setting = self.cruise_setting\n\n    # ******************* parse out can *******************\n    # TODO: find wheels moving bit in dbc\n    if self.CP.carFingerprint in (CAR.ACCORD, CAR.ACCORDH, CAR.INSIGHT):\n      ret.standstill = cp.vl[\"ENGINE_DATA\"][\"XMISSION_SPEED\"] < 0.1\n      ret.doorOpen = bool(cp.vl[\"SCM_FEEDBACK\"][\"DRIVERS_DOOR_OPEN\"])\n      self.lead_distance = cp.vl[\"RADAR_HUD\"][\"LEAD_DISTANCE\"]\n    elif self.CP.carFingerprint in (CAR.ACCORD, CAR.ACCORDH, CAR.CIVIC_BOSCH, CAR.CIVIC_BOSCH_DIESEL, CAR.CRV_HYBRID, CAR.ACURA_RDX_3G, CAR.HONDA_E):\n      ret.standstill = cp.vl[\"ENGINE_DATA\"][\"XMISSION_SPEED\"] < 0.1\n      ret.doorOpen = bool(cp.vl[\"SCM_FEEDBACK\"][\"DRIVERS_DOOR_OPEN\"])\n    elif self.CP.carFingerprint == CAR.ODYSSEY_CHN:\n      ret.standstill = cp.vl[\"ENGINE_DATA\"][\"XMISSION_SPEED\"] < 0.1\n      ret.doorOpen = bool(cp.vl[\"SCM_BUTTONS\"][\"DRIVERS_DOOR_OPEN\"])\n    elif self.CP.carFingerprint in [CAR.HRV, CAR.JADE]:\n      ret.doorOpen = bool(cp.vl[\"SCM_BUTTONS\"][\"DRIVERS_DOOR_OPEN\"])\n    else:\n      ret.standstill = not cp.vl[\"STANDSTILL\"][\"WHEELS_MOVING\"]\n      ret.doorOpen = any([cp.vl[\"DOORS_STATUS\"][\"DOOR_OPEN_FL\"], cp.vl[\"DOORS_STATUS\"][\"DOOR_OPEN_FR\"],\n                          cp.vl[\"DOORS_STATUS\"][\"DOOR_OPEN_RL\"], cp.vl[\"DOORS_STATUS\"][\"DOOR_OPEN_RR\"]])\n    ret.seatbeltUnlatched = bool(cp.vl[\"SEATBELT_STATUS\"][\"SEATBELT_DRIVER_LAMP\"] or not cp.vl[\"SEATBELT_STATUS\"][\"SEATBELT_DRIVER_LATCHED\"])\n\n    steer_status = self.steer_status_values[cp.vl[\"STEER_STATUS\"][\"STEER_STATUS\"]]\n    ret.steerError = steer_status not in [\"NORMAL\", \"NO_TORQUE_ALERT_1\", \"NO_TORQUE_ALERT_2\", \"LOW_SPEED_LOCKOUT\", \"TMP_FAULT\"]\n    # NO_TORQUE_ALERT_2 can be caused by bump OR steering nudge from driver\n    self.steer_not_allowed = steer_status not in [\"NORMAL\", \"NO_TORQUE_ALERT_2\"]\n    # LOW_SPEED_LOCKOUT is not worth a warning\n    ret.steerWarning = steer_status not in [\"NORMAL\", \"LOW_SPEED_LOCKOUT\", \"NO_TORQUE_ALERT_2\"]\n\n    if not self.CP.openpilotLongitudinalControl:\n      self.brake_error = 0\n    else:\n      self.brake_error = cp.vl[\"STANDSTILL\"][\"BRAKE_ERROR_1\"] or cp.vl[\"STANDSTILL\"][\"BRAKE_ERROR_2\"]\n    ret.espDisabled = cp.vl[\"VSA_STATUS\"][\"ESP_DISABLED\"] != 0\n\n    speed_factor = SPEED_FACTOR.get(self.CP.carFingerprint, 1.)\n    ret.wheelSpeeds.fl = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_FL\"] * CV.KPH_TO_MS * speed_factor\n    ret.wheelSpeeds.fr = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_FR\"] * CV.KPH_TO_MS * speed_factor\n    ret.wheelSpeeds.rl = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_RL\"] * CV.KPH_TO_MS * speed_factor\n    ret.wheelSpeeds.rr = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_RR\"] * CV.KPH_TO_MS * speed_factor\n    v_wheel = (ret.wheelSpeeds.fl + ret.wheelSpeeds.fr + ret.wheelSpeeds.rl + ret.wheelSpeeds.rr)/4.\n\n    # blend in transmission speed at low speed, since it has more low speed accuracy\n    v_weight = interp(v_wheel, v_weight_bp, v_weight_v)\n    ret.vEgoRaw = (1. - v_weight) * cp.vl[\"ENGINE_DATA\"][\"XMISSION_SPEED\"] * CV.KPH_TO_MS * speed_factor + v_weight * v_wheel\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n\n    ret.steeringAngleDeg = cp.vl[\"STEERING_SENSORS\"][\"STEER_ANGLE\"]\n    ret.steeringRateDeg = cp.vl[\"STEERING_SENSORS\"][\"STEER_ANGLE_RATE\"]\n\n    # dp - when user presses LKAS button on steering wheel\n    if self.cruise_setting == 1:\n      if cp.vl[\"SCM_BUTTONS\"][\"CRUISE_SETTING\"] == 0:\n        if self.lkMode:\n          self.lkMode = False\n        else:\n          self.lkMode = True\n\n    self.cruise_setting = cp.vl[\"SCM_BUTTONS\"][\"CRUISE_SETTING\"]\n    self.cruise_buttons = cp.vl[\"SCM_BUTTONS\"][\"CRUISE_BUTTONS\"]\n\n    ret.leftBlinker, ret.rightBlinker = self.update_blinker_from_stalk(\n      250, cp.vl[\"SCM_FEEDBACK\"][\"LEFT_BLINKER\"], cp.vl[\"SCM_FEEDBACK\"][\"RIGHT_BLINKER\"])\n    self.brake_hold = cp.vl[\"VSA_STATUS\"][\"BRAKE_HOLD_ACTIVE\"]\n    #dp\n    self.engineRPM = cp.vl[\"POWERTRAIN_DATA\"]['ENGINE_RPM']\n\n    if self.CP.carFingerprint in (CAR.CIVIC, CAR.ODYSSEY, CAR.CRV_5G, CAR.ACCORD, CAR.ACCORDH, CAR.CIVIC_BOSCH,\n                                  CAR.CIVIC_BOSCH_DIESEL, CAR.CRV_HYBRID, CAR.INSIGHT, CAR.ACURA_RDX_3G, CAR.HONDA_E):\n      self.park_brake = cp.vl[\"EPB_STATUS\"][\"EPB_STATE\"] != 0\n      main_on = cp.vl[\"SCM_FEEDBACK\"][\"MAIN_ON\"]\n    elif self.CP.carFingerprint == CAR.ODYSSEY_CHN:\n      self.park_brake = cp.vl[\"EPB_STATUS\"][\"EPB_STATE\"] != 0\n      main_on = cp.vl[\"SCM_BUTTONS\"][\"MAIN_ON\"]\n    else:\n      self.park_brake = 0  # TODO\n      main_on = cp.vl[\"SCM_BUTTONS\"][\"MAIN_ON\"]\n\n    gear = int(cp.vl[self.gearbox_msg][\"GEAR_SHIFTER\"])\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(gear, None))\n\n    pedal_gas = cp.vl[\"POWERTRAIN_DATA\"][\"PEDAL_GAS\"]\n    # crv doesn't include cruise control\n    if self.CP.carFingerprint in (CAR.CRV, CAR.CRV_EU, CAR.HRV, CAR.ODYSSEY, CAR.ACURA_RDX, CAR.RIDGELINE, CAR.PILOT_2019, CAR.ODYSSEY_CHN, CAR.JADE):\n      ret.gas = pedal_gas / 256.\n    else:\n      ret.gas = cp.vl[\"GAS_PEDAL_2\"][\"CAR_GAS\"] / 256.\n\n    # this is a hack for the interceptor. This is now only used in the simulation\n    # TODO: Replace tests by toyota so this can go away\n    if self.CP.enableGasInterceptor:\n      user_gas = (cp.vl[\"GAS_SENSOR\"][\"INTERCEPTOR_GAS\"] + cp.vl[\"GAS_SENSOR\"][\"INTERCEPTOR_GAS2\"]) / 2.\n      ret.gasPressed = user_gas > 1e-5  # this works because interceptor read < 0 when pedal position is 0. Once calibrated, this will change\n    else:\n      ret.gasPressed = pedal_gas > 1e-5\n\n    ret.steeringTorque = cp.vl[\"STEER_STATUS\"][\"STEER_TORQUE_SENSOR\"]\n    ret.steeringTorqueEps = cp.vl[\"STEER_MOTOR_TORQUE\"][\"MOTOR_TORQUE\"]\n    ret.steeringPressed = abs(ret.steeringTorque) > STEER_THRESHOLD.get(self.CP.carFingerprint, 1200)\n\n    if self.CP.carFingerprint in HONDA_BOSCH:\n      if not self.CP.openpilotLongitudinalControl:\n        ret.cruiseState.nonAdaptive = cp.vl[\"ACC_HUD\"][\"CRUISE_CONTROL_LABEL\"] != 0\n        ret.cruiseState.standstill = cp.vl[\"ACC_HUD\"][\"CRUISE_SPEED\"] == 252.\n\n        # On set, cruise set speed pulses between 254~255 and the set speed prev is set to avoid this.\n        ret.cruiseState.speed = self.v_cruise_pcm_prev if cp.vl[\"ACC_HUD\"][\"CRUISE_SPEED\"] > 160.0 else cp.vl[\"ACC_HUD\"][\"CRUISE_SPEED\"] * CV.KPH_TO_MS\n        self.v_cruise_pcm_prev = ret.cruiseState.speed\n    else:\n      ret.cruiseState.speedOffset = calc_cruise_offset(cp.vl[\"CRUISE_PARAMS\"][\"CRUISE_SPEED_OFFSET\"], ret.vEgo)\n      ret.cruiseState.speed = cp.vl[\"CRUISE\"][\"CRUISE_SPEED_PCM\"] * CV.KPH_TO_MS\n\n    self.brake_switch = cp.vl[\"POWERTRAIN_DATA\"][\"BRAKE_SWITCH\"] != 0\n    if self.CP.carFingerprint in HONDA_BOSCH_ALT_BRAKE_SIGNAL:\n      ret.brakePressed = cp.vl[\"BRAKE_MODULE\"][\"BRAKE_PRESSED\"] != 0\n    else:\n      # brake switch has shown some single time step noise, so only considered when\n      # switch is on for at least 2 consecutive CAN samples\n      # panda safety only checks BRAKE_PRESSED signal\n      ret.brakePressed = bool(cp.vl[\"POWERTRAIN_DATA\"][\"BRAKE_PRESSED\"] or\n                              (self.brake_switch and self.brake_switch_prev and cp.ts[\"POWERTRAIN_DATA\"][\"BRAKE_SWITCH\"] != self.brake_switch_prev_ts))\n\n      self.brake_switch_prev = self.brake_switch\n      self.brake_switch_prev_ts = cp.ts[\"POWERTRAIN_DATA\"][\"BRAKE_SWITCH\"]\n\n    ret.brake = cp.vl[\"VSA_STATUS\"][\"USER_BRAKE\"]\n    ret.cruiseState.enabled = cp.vl[\"POWERTRAIN_DATA\"][\"ACC_STATUS\"] != 0\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    ret.cruiseState.available = bool(main_on)\n\n    # afa feature\n    self.hud_lead = cp.vl[\"ACC_HUD\"]['HUD_LEAD']\n\n    # Gets rid of Pedal Grinding noise when brake is pressed at slow speeds for some models\n    if self.CP.carFingerprint in (CAR.PILOT, CAR.PILOT_2019, CAR.RIDGELINE, CAR.JADE):\n      if ret.brake > 0.05:\n        ret.brakePressed = True\n\n    # TODO: discover the CAN msg that has the imperial unit bit for all other cars\n    if self.CP.carFingerprint in [CAR.JADE]:\n      self.is_metric = True\n    else:\n      self.is_metric = not cp.vl[\"HUD_SETTING\"][\"IMPERIAL_UNIT\"] if self.CP.carFingerprint in (CAR.CIVIC) else False\n\n    if self.dp_honda_kmh_display:\n      self.is_metric = True\n\n    if self.CP.carFingerprint in HONDA_BOSCH:\n      ret.stockAeb = (not self.CP.openpilotLongitudinalControl) and bool(cp.vl[\"ACC_CONTROL\"][\"AEB_STATUS\"] and cp.vl[\"ACC_CONTROL\"][\"ACCEL_COMMAND\"] < -1e-5)\n    else:\n      ret.stockAeb = bool(cp_cam.vl[\"BRAKE_COMMAND\"][\"AEB_REQ_1\"] and cp_cam.vl[\"BRAKE_COMMAND\"][\"COMPUTER_BRAKE\"] > 1e-5)\n\n    if self.CP.carFingerprint in HONDA_BOSCH:\n      self.stock_hud = False\n      ret.stockFcw = False\n\n      #brakelights for HONDA BOSCH\n      self.brake_switch = cp.vl[\"POWERTRAIN_DATA\"]['BRAKE_SWITCH'] != 0\n      self.brake_lights = cp.vl[\"ACC_CONTROL\"]['BRAKE_LIGHTS'] != 0\n      self.user_brake = cp.vl[\"VSA_STATUS\"]['USER_BRAKE']\n\n    else:\n      ret.stockFcw = cp_cam.vl[\"BRAKE_COMMAND\"][\"FCW\"] != 0\n      self.stock_hud = cp_cam.vl[\"ACC_HUD\"]\n      self.stock_brake = cp_cam.vl[\"BRAKE_COMMAND\"]\n\n    if self.CP.enableBsm and self.CP.carFingerprint in (CAR.CRV_5G, CAR.CRV_HYBRID, ):\n      # BSM messages are on B-CAN, requires a panda forwarding B-CAN messages to CAN 0\n      # more info here: https://github.com/commaai/openpilot/pull/1867\n      ret.leftBlindspot = cp_body.vl[\"BSM_STATUS_LEFT\"][\"BSM_ALERT\"] == 1\n      ret.rightBlindspot = cp_body.vl[\"BSM_STATUS_RIGHT\"][\"BSM_ALERT\"] == 1\n\n    return ret\n\n  def get_can_parser(self, CP):\n    signals, checks = get_can_signals(CP, self.gearbox_msg)\n    bus_pt = 1 if CP.carFingerprint in HONDA_BOSCH else 0\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, bus_pt)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    signals = []\n\n    # all hondas except CRV, RDX and 2019 Odyssey@China use 0xe4 for steering\n    checks = [(0xe4, 100)]\n    if CP.carFingerprint in [CAR.CRV, CAR.CRV_EU, CAR.ACURA_RDX, CAR.ODYSSEY_CHN]:\n      checks = [(0x194, 100)]\n\n    if CP.carFingerprint not in HONDA_BOSCH:\n      signals += [(\"COMPUTER_BRAKE\", \"BRAKE_COMMAND\", 0),\n                  (\"AEB_REQ_1\", \"BRAKE_COMMAND\", 0),\n                  (\"FCW\", \"BRAKE_COMMAND\", 0),\n                  (\"CHIME\", \"BRAKE_COMMAND\", 0),\n                  (\"FCM_OFF\", \"ACC_HUD\", 0),\n                  (\"FCM_OFF_2\", \"ACC_HUD\", 0),\n                  (\"FCM_PROBLEM\", \"ACC_HUD\", 0),\n                  (\"ICONS\", \"ACC_HUD\", 0)]\n      checks += [\n        (\"ACC_HUD\", 10),\n        (\"BRAKE_COMMAND\", 50),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n\n  @staticmethod\n  def get_body_can_parser(CP):\n    if CP.enableBsm and CP.carFingerprint in (CAR.CRV_5G, CAR.CRV_HYBRID, ):\n      signals = [(\"BSM_ALERT\", \"BSM_STATUS_RIGHT\", 0),\n                 (\"BSM_ALERT\", \"BSM_STATUS_LEFT\", 0)]\n\n      checks = [\n        (\"BSM_STATUS_LEFT\", 3),\n        (\"BSM_STATUS_RIGHT\", 3),\n      ]\n      bus_body = 0 # B-CAN is forwarded to ACC-CAN radar side (CAN 0 on fake ethernet port)\n      return CANParser(DBC[CP.carFingerprint][\"body\"], signals, checks, bus_body)\n    return None\n"
  },
  {
    "path": "selfdrive/car/honda/hondacan.py",
    "content": "from selfdrive.car.isotp_parallel_query import IsoTpParallelQuery\nfrom selfdrive.car.honda.values import HONDA_BOSCH, CAR\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.swaglog import cloudlog\n\n# CAN bus layout with relay\n# 0 = ACC-CAN - radar side\n# 1 = F-CAN B - powertrain\n# 2 = ACC-CAN - camera side\n# 3 = F-CAN A - OBDII port\n\nRADAR_ADDR = 0x18DAB0F1\nEXT_DIAG_REQUEST = b'\\x10\\x03'\nEXT_DIAG_RESPONSE = b'\\x50\\x03'\nCOM_CONT_REQUEST = b'\\x28\\x83\\x03'\nCOM_CONT_RESPONSE = b''\n\n\ndef get_pt_bus(car_fingerprint):\n  return 1 if car_fingerprint in HONDA_BOSCH else 0\n\n\ndef get_lkas_cmd_bus(car_fingerprint, radar_disabled=False):\n  if radar_disabled:\n    # when radar is disabled, steering commands are sent directly to powertrain bus\n    return get_pt_bus(car_fingerprint)\n  # normally steering commands are sent to radar, which forwards them to powertrain bus\n  return 0\n\n\ndef disable_radar(logcan, sendcan, bus=1, timeout=0.1, debug=False):\n  \"\"\"Silence the radar by disabling sending and receiving messages using UDS 0x28.\n  The radar will stay silent as long as openpilot keeps sending Tester Present.\n  Openpilot will emulate the radar. WARNING: THIS DISABLES AEB!\"\"\"\n  cloudlog.warning(f\"radar disable {hex(RADAR_ADDR)} ...\")\n\n  try:\n    query = IsoTpParallelQuery(sendcan, logcan, bus, [RADAR_ADDR], [EXT_DIAG_REQUEST], [EXT_DIAG_RESPONSE], debug=debug)\n\n    for _, _ in query.get_data(timeout).items():\n      cloudlog.warning(\"radar communication control disable tx/rx ...\")\n\n      query = IsoTpParallelQuery(sendcan, logcan, bus, [RADAR_ADDR], [COM_CONT_REQUEST], [COM_CONT_RESPONSE], debug=debug)\n      query.get_data(0)\n\n      cloudlog.warning(\"radar disabled\")\n      return\n\n  except Exception:\n    cloudlog.exception(\"radar disable exception\")\n  cloudlog.warning(\"radar disable failed\")\n\n\ndef create_brake_command(packer, apply_brake, pump_on, pcm_override, pcm_cancel_cmd, fcw, idx, car_fingerprint, stock_brake):\n  # TODO: do we loose pressure if we keep pump off for long?\n  brakelights = apply_brake > 0\n  brake_rq = apply_brake > 0\n  pcm_fault_cmd = False\n\n  values = {\n    \"COMPUTER_BRAKE\": apply_brake,\n    \"BRAKE_PUMP_REQUEST\": pump_on,\n    \"CRUISE_OVERRIDE\": pcm_override,\n    \"CRUISE_FAULT_CMD\": pcm_fault_cmd,\n    \"CRUISE_CANCEL_CMD\": pcm_cancel_cmd,\n    \"COMPUTER_BRAKE_REQUEST\": brake_rq,\n    \"SET_ME_1\": 1,\n    \"BRAKE_LIGHTS\": brakelights,\n    \"CHIME\": stock_brake[\"CHIME\"] if fcw else 0,  # send the chime for stock fcw\n    \"FCW\": fcw << 1,  # TODO: Why are there two bits for fcw?\n    \"AEB_REQ_1\": 0,\n    \"AEB_REQ_2\": 0,\n    \"AEB_STATUS\": 0,\n  }\n  bus = get_pt_bus(car_fingerprint)\n  return packer.make_can_msg(\"BRAKE_COMMAND\", bus, values, idx)\n\n\ndef create_acc_commands(packer, enabled, accel, gas, idx, stopping, starting, car_fingerprint):\n  commands = []\n  bus = get_pt_bus(car_fingerprint)\n\n  control_on = 5 if enabled else 0\n  # no gas = -30000\n  gas_command = gas if enabled and gas > 0 else -30000\n  accel_command = accel if enabled else 0\n  braking = 1 if enabled and accel < 0 else 0\n  standstill = 1 if enabled and stopping else 0\n  standstill_release = 1 if enabled and starting else 0\n\n  acc_control_values = {\n    # setting CONTROL_ON causes car to set POWERTRAIN_DATA->ACC_STATUS = 1\n    \"CONTROL_ON\": control_on,\n    \"GAS_COMMAND\": gas_command, # used for gas\n    \"ACCEL_COMMAND\": accel_command, # used for brakes\n    \"BRAKE_LIGHTS\": braking,\n    \"BRAKE_REQUEST\": braking,\n    \"STANDSTILL\": standstill,\n    \"STANDSTILL_RELEASE\": standstill_release,\n  }\n  commands.append(packer.make_can_msg(\"ACC_CONTROL\", bus, acc_control_values, idx))\n\n  acc_control_on_values = {\n    \"SET_TO_3\": 0x03,\n    \"CONTROL_ON\": enabled,\n    \"SET_TO_FF\": 0xff,\n    \"SET_TO_75\": 0x75,\n    \"SET_TO_30\": 0x30,\n  }\n  commands.append(packer.make_can_msg(\"ACC_CONTROL_ON\", bus, acc_control_on_values, idx))\n\n  return commands\n\ndef create_steering_control(packer, apply_steer, lkas_active, car_fingerprint, idx, radar_disabled):\n  values = {\n    \"STEER_TORQUE\": apply_steer if lkas_active else 0,\n    \"STEER_TORQUE_REQUEST\": lkas_active,\n  }\n  bus = get_lkas_cmd_bus(car_fingerprint, radar_disabled)\n  return packer.make_can_msg(\"STEERING_CONTROL\", bus, values, idx)\n\n\ndef create_bosch_supplemental_1(packer, car_fingerprint, idx):\n  # non-active params\n  values = {\n    \"SET_ME_X04\": 0x04,\n    \"SET_ME_X80\": 0x80,\n    \"SET_ME_X10\": 0x10,\n  }\n  bus = get_lkas_cmd_bus(car_fingerprint)\n  return packer.make_can_msg(\"BOSCH_SUPPLEMENTAL_1\", bus, values, idx)\n\n\ndef create_ui_commands(packer, pcm_speed, hud, car_fingerprint, is_metric, idx, openpilot_longitudinal_control, stock_hud):\n  commands = []\n  bus_pt = get_pt_bus(car_fingerprint)\n  radar_disabled = car_fingerprint in HONDA_BOSCH and openpilot_longitudinal_control\n  bus_lkas = get_lkas_cmd_bus(car_fingerprint, radar_disabled)\n\n  if openpilot_longitudinal_control:\n    if car_fingerprint in HONDA_BOSCH:\n      acc_hud_values = {\n        'CRUISE_SPEED': hud.v_cruise,\n        'ENABLE_MINI_CAR': 1,\n        'SET_TO_1': 1,\n        'HUD_LEAD': hud.car,\n        'HUD_DISTANCE': 3,\n        'ACC_ON': hud.car != 0,\n        'SET_TO_X1': 1,\n        'IMPERIAL_UNIT': int(not is_metric),\n      }\n    else:\n      acc_hud_values = {\n        'PCM_SPEED': pcm_speed * CV.MS_TO_KPH,\n        'PCM_GAS': hud.pcm_accel,\n        'CRUISE_SPEED': hud.v_cruise,\n        'ENABLE_MINI_CAR': 1,\n        'HUD_LEAD': hud.car,\n        'HUD_DISTANCE': 3,    # max distance setting on display\n        'IMPERIAL_UNIT': int(not is_metric),\n        'SET_ME_X01_2': 1,\n        'SET_ME_X01': 1,\n        \"FCM_OFF\": stock_hud[\"FCM_OFF\"],\n        \"FCM_OFF_2\": stock_hud[\"FCM_OFF_2\"],\n        \"FCM_PROBLEM\": stock_hud[\"FCM_PROBLEM\"],\n        \"ICONS\": stock_hud[\"ICONS\"],\n      }\n    commands.append(packer.make_can_msg(\"ACC_HUD\", bus_pt, acc_hud_values, idx))\n\n  lkas_hud_values = {\n    'SET_ME_X41': 0x41,\n    'SET_ME_X48': 0x48,\n    'STEERING_REQUIRED': hud.steer_required,\n    'SOLID_LANES': hud.lanes,\n    'BEEP': 0,\n  }\n  commands.append(packer.make_can_msg('LKAS_HUD', bus_lkas, lkas_hud_values, idx))\n\n  if radar_disabled and car_fingerprint in HONDA_BOSCH:\n    radar_hud_values = {\n      'SET_TO_1' : 0x01,\n    }\n    commands.append(packer.make_can_msg('RADAR_HUD', bus_pt, radar_hud_values, idx))\n\n    if car_fingerprint == CAR.CIVIC_BOSCH:\n      commands.append(packer.make_can_msg(\"LEGACY_BRAKE_COMMAND\", bus_pt, {}, idx))\n\n  return commands\n\n\ndef spam_buttons_command(packer, button_val, idx, car_fingerprint):\n  values = {\n    'CRUISE_BUTTONS': button_val,\n    'CRUISE_SETTING': 0,\n  }\n  bus = get_pt_bus(car_fingerprint)\n  return packer.make_can_msg(\"SCM_BUTTONS\", bus, values, idx)\n"
  },
  {
    "path": "selfdrive/car/honda/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom panda import Panda\nfrom common.numpy_fast import interp\nfrom common.params import Params\nfrom selfdrive.car.honda.values import CarControllerParams, CruiseButtons, CAR, HONDA_BOSCH, HONDA_BOSCH_ALT_BRAKE_SIGNAL\nfrom selfdrive.car.honda.hondacan import disable_radar\nfrom selfdrive.car import STD_CARGO_KG, CivicParams, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom selfdrive.config import Conversions as CV\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\n\nButtonType = car.CarState.ButtonEvent.Type\nEventName = car.CarEvent.EventName\nTransmissionType = car.CarParams.TransmissionType\n\n\nclass CarInterface(CarInterfaceBase):\n  @staticmethod\n  def get_pid_accel_limits(CP, current_speed, cruise_speed):\n    if CP.carFingerprint in HONDA_BOSCH:\n      return CarControllerParams.BOSCH_ACCEL_MIN, CarControllerParams.BOSCH_ACCEL_MAX\n    else:\n      # NIDECs don't allow acceleration near cruise_speed,\n      # so limit limits of pid to prevent windup\n      ACCEL_MAX_VALS = [CarControllerParams.NIDEC_ACCEL_MAX, 0.2]\n      ACCEL_MAX_BP = [cruise_speed - 2., cruise_speed - .2]\n      return CarControllerParams.NIDEC_ACCEL_MIN, interp(current_speed, ACCEL_MAX_BP, ACCEL_MAX_VALS)\n\n  @staticmethod\n  def calc_accel_override(a_ego, a_target, v_ego, v_target):\n\n    # normalized max accel. Allowing max accel at low speed causes speed overshoots\n    max_accel_bp = [10, 20]    # m/s\n    max_accel_v = [0.714, 1.0]  # unit of max accel\n    max_accel = interp(v_ego, max_accel_bp, max_accel_v)\n\n    # limit the pcm accel cmd if:\n    # - v_ego exceeds v_target, or\n    # - a_ego exceeds a_target and v_ego is close to v_target\n\n    eA = a_ego - a_target\n    valuesA = [1.0, 0.1]\n    bpA = [0.3, 1.1]\n\n    eV = v_ego - v_target\n    valuesV = [1.0, 0.1]\n    bpV = [0.0, 0.5]\n\n    valuesRangeV = [1., 0.]\n    bpRangeV = [-1., 0.]\n\n    # only limit if v_ego is close to v_target\n    speedLimiter = interp(eV, bpV, valuesV)\n    accelLimiter = max(interp(eA, bpA, valuesA), interp(eV, bpRangeV, valuesRangeV))\n\n    # accelOverride is more or less the max throttle allowed to pcm: usually set to a constant\n    # unless aTargetMax is very high and then we scale with it; this help in quicker restart\n\n    return float(max(max_accel, a_target / CarControllerParams.NIDEC_ACCEL_MAX)) * min(speedLimiter, accelLimiter)\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=[]):  # pylint: disable=dangerous-default-value\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"honda\"\n    ret.lateralTuning.init('pid')\n\n    if candidate in HONDA_BOSCH:\n      ret.safetyModel = car.CarParams.SafetyModel.hondaBoschHarness\n      ret.radarOffCan = True\n\n      # Disable the radar and let openpilot control longitudinal\n      # WARNING: THIS DISABLES AEB!\n      ret.openpilotLongitudinalControl = Params().get_bool(\"DisableRadar\")\n\n      ret.pcmCruise = not ret.openpilotLongitudinalControl\n      ret.communityFeature = ret.openpilotLongitudinalControl\n    else:\n      ret.safetyModel = car.CarParams.SafetyModel.hondaNidec\n      ret.enableGasInterceptor = 0x201 in fingerprint[0]\n      ret.openpilotLongitudinalControl = True\n\n      ret.pcmCruise = not ret.enableGasInterceptor\n      ret.communityFeature = ret.enableGasInterceptor\n\n    ret.enableBsm = True\n    #if candidate in (CAR.CRV_5G, CAR.CRV_HYBRID, ):\n      #ret.enableBsm = 0x12f8bfa7 in fingerprint[0]\n\n    # Accord 1.5T CVT has different gearbox message\n    if candidate == CAR.ACCORD and 0x191 in fingerprint[1]:\n      ret.transmissionType = TransmissionType.cvt\n\n    # Certain Hondas have an extra steering sensor at the bottom of the steering rack,\n    # which improves controls quality as it removes the steering column torsion from feedback.\n    # Tire stiffness factor fictitiously lower if it includes the steering column torsion effect.\n    # For modeling details, see p.198-200 in \"The Science of Vehicle Dynamics (2014), M. Guiggiani\"\n    ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0], [0]]\n    ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n    ret.lateralTuning.pid.kf = 0.00006  # conservative feed-forward\n\n    # default longitudinal tuning for all hondas\n    ret.longitudinalTuning.kpBP = [0., 5., 35.]\n    ret.longitudinalTuning.kpV = [1.2, 0.8, 0.5]\n    ret.longitudinalTuning.kiBP = [0., 35.]\n    ret.longitudinalTuning.kiV = [0.18, 0.12]\n\n    eps_modified = False\n    for fw in car_fw:\n      if fw.ecu == \"eps\" and b\",\" in fw.fwVersion:\n        eps_modified = True\n\n    if candidate == CAR.CIVIC:\n      stop_and_go = True\n      ret.mass = CivicParams.MASS\n      ret.wheelbase = CivicParams.WHEELBASE\n      ret.centerToFront = CivicParams.CENTER_TO_FRONT\n      ret.steerRatio = 15.38  # 10.93 is end-to-end spec\n      if eps_modified:\n        # stock request input values:     0x0000, 0x00DE, 0x014D, 0x01EF, 0x0290, 0x0377, 0x0454, 0x0610, 0x06EE\n        # stock request output values:    0x0000, 0x0917, 0x0DC5, 0x1017, 0x119F, 0x140B, 0x1680, 0x1680, 0x1680\n        # modified request output values: 0x0000, 0x0917, 0x0DC5, 0x1017, 0x119F, 0x140B, 0x1680, 0x2880, 0x3180\n        # stock filter output values:     0x009F, 0x0108, 0x0108, 0x0108, 0x0108, 0x0108, 0x0108, 0x0108, 0x0108\n        # modified filter output values:  0x009F, 0x0108, 0x0108, 0x0108, 0x0108, 0x0108, 0x0108, 0x0400, 0x0480\n        # note: max request allowed is 4096, but request is capped at 3840 in firmware, so modifications result in 2x max\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 2560, 8000], [0, 2560, 3840]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.1]]\n      else:\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 2560], [0, 2560]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[1.1], [0.33]]\n      tire_stiffness_factor = 1.\n\n    elif candidate in (CAR.CIVIC_BOSCH, CAR.CIVIC_BOSCH_DIESEL):\n      stop_and_go = True\n      ret.mass = CivicParams.MASS\n      ret.wheelbase = CivicParams.WHEELBASE\n      ret.centerToFront = CivicParams.CENTER_TO_FRONT\n      ret.steerRatio = 15.38  # 10.93 is end-to-end spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 1.\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.8], [0.24]]\n\n    elif candidate in (CAR.ACCORD, CAR.ACCORDH):\n      stop_and_go = True\n      ret.mass = 3279. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.83\n      ret.centerToFront = ret.wheelbase * 0.39\n      ret.steerRatio = 16.33  # 11.82 is spec end-to-end\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.8467\n\n      if eps_modified:\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.09]]\n      else:\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.18]]\n\n    elif candidate == CAR.ACURA_ILX:\n      stop_and_go = False\n      ret.mass = 3095. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.67\n      ret.centerToFront = ret.wheelbase * 0.37\n      ret.steerRatio = 18.61  # 15.3 is spec end-to-end\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 3840], [0, 3840]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.72\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.8], [0.24]]\n\n    elif candidate in (CAR.CRV, CAR.CRV_EU):\n      stop_and_go = False\n      ret.mass = 3572. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.62\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 16.89  # as spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 1000], [0, 1000]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.444\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.8], [0.24]]\n\n    elif candidate == CAR.CRV_5G:\n      stop_and_go = True\n      ret.mass = 3410. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.66\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 16.0  # 12.3 is spec end-to-end\n      if eps_modified:\n        # stock request input values:     0x0000, 0x00DB, 0x01BB, 0x0296, 0x0377, 0x0454, 0x0532, 0x0610, 0x067F\n        # stock request output values:    0x0000, 0x0500, 0x0A15, 0x0E6D, 0x1100, 0x1200, 0x129A, 0x134D, 0x1400\n        # modified request output values: 0x0000, 0x0500, 0x0A15, 0x0E6D, 0x1100, 0x1200, 0x1ACD, 0x239A, 0x2800\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 2560, 10000], [0, 2560, 3840]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.21], [0.07]]\n      else:\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 3840], [0, 3840]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.64], [0.192]]\n      tire_stiffness_factor = 0.677\n\n    elif candidate == CAR.CRV_HYBRID:\n      stop_and_go = True\n      ret.mass = 1667. + STD_CARGO_KG  # mean of 4 models in kg\n      ret.wheelbase = 2.66\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 16.0  # 12.3 is spec end-to-end\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.677\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.18]]\n\n    elif candidate == CAR.FIT:\n      stop_and_go = False\n      ret.mass = 2644. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.53\n      ret.centerToFront = ret.wheelbase * 0.39\n      ret.steerRatio = 13.06\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.75\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.2], [0.05]]\n\n    elif candidate == CAR.HRV:\n      stop_and_go = False\n      ret.mass = 3125 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.61\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 15.2\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]\n      tire_stiffness_factor = 0.5\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.16], [0.025]]\n\n    elif candidate == CAR.ACURA_RDX:\n      stop_and_go = False\n      ret.mass = 3935. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.68\n      ret.centerToFront = ret.wheelbase * 0.38\n      ret.steerRatio = 15.0  # as spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 1000], [0, 1000]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.444\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.8], [0.24]]\n\n    elif candidate == CAR.ACURA_RDX_3G:\n      stop_and_go = True\n      ret.mass = 4068. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.75\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 11.95  # as spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 3840], [0, 3840]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.18]]\n      tire_stiffness_factor = 0.677\n\n    elif candidate == CAR.ODYSSEY:\n      stop_and_go = False\n      ret.mass = 4471. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 3.00\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 14.35  # as spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.82\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.28], [0.08]]\n\n    elif candidate == CAR.ODYSSEY_CHN:\n      stop_and_go = False\n      ret.mass = 1849.2 + STD_CARGO_KG  # mean of 4 models in kg\n      ret.wheelbase = 2.90\n      ret.centerToFront = ret.wheelbase * 0.41  # from CAR.ODYSSEY\n      ret.steerRatio = 14.35\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 32767], [0, 32767]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.82\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.28], [0.08]]\n\n    elif candidate in (CAR.PILOT, CAR.PILOT_2019):\n      stop_and_go = False\n      ret.mass = 4204. * CV.LB_TO_KG + STD_CARGO_KG  # average weight\n      ret.wheelbase = 2.82\n      ret.centerToFront = ret.wheelbase * 0.428\n      ret.steerRatio = 17.25  # as spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.444\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.38], [0.11]]\n\n    elif candidate == CAR.RIDGELINE:\n      stop_and_go = False\n      ret.mass = 4515. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 3.18\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 15.59  # as spec\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.444\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.38], [0.11]]\n\n    elif candidate == CAR.INSIGHT:\n      stop_and_go = True\n      ret.mass = 2987. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.7\n      ret.centerToFront = ret.wheelbase * 0.39\n      ret.steerRatio = 15.0  # 12.58 is spec end-to-end\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.82\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.18]]\n\n    elif candidate == CAR.HONDA_E:\n      stop_and_go = True\n      ret.mass = 3338.8 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.5\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 16.71\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]  # TODO: determine if there is a dead zone at the top end\n      tire_stiffness_factor = 0.82\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.18]] # TODO: can probably use some tuning\n\n    elif candidate == CAR.JADE:\n      stop_and_go = False\n      ret.mass = 1557. + STD_CARGO_KG\n      ret.wheelbase = 2.76\n      ret.centerToFront = ret.wheelbase * 0.41\n      ret.steerRatio = 15.2\n      ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 4096], [0, 4096]]\n      tire_stiffness_factor = 0.5\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.16], [0.025]]\n      ret.longitudinalTuning.kpBP = [0., 5., 35.]\n      ret.longitudinalTuning.kpV = [1.2, 0.8, 0.5]\n      ret.longitudinalTuning.kiBP = [0., 35.]\n      ret.longitudinalTuning.kiV = [0.18, 0.12]\n\n    else:\n      raise ValueError(\"unsupported car %s\" % candidate)\n\n    # These cars use alternate user brake msg (0x1BE)\n    if candidate in HONDA_BOSCH_ALT_BRAKE_SIGNAL:\n      ret.safetyParam |= Panda.FLAG_HONDA_ALT_BRAKE\n\n    if ret.openpilotLongitudinalControl and candidate in HONDA_BOSCH:\n      ret.safetyParam |= Panda.FLAG_HONDA_BOSCH_LONG\n\n    # min speed to enable ACC. if car can do stop and go, then set enabling speed\n    # to a negative value, so it won't matter. Otherwise, add 0.5 mph margin to not\n    # conflict with PCM acc\n    if candidate in [CAR.JADE]:\n      ret.minEnableSpeed = -1. if (ret.enableGasInterceptor) else 30 * CV.KPH_TO_MS\n    else:\n      ret.minEnableSpeed = -1. if (stop_and_go or ret.enableGasInterceptor) else 25.5 * CV.MPH_TO_MS\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n\n    ret.startAccel = 0.5\n\n    ret.steerActuatorDelay = 0.1\n    ret.steerRateCost = 0.5\n    ret.steerLimitTimer = 0.8\n\n    # dp\n    if Params().get('dp_honda_eps_mod') == b'1':\n      if candidate == CAR.CIVIC:\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 2560, 8000], [0, 2560, 3840]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.1]] #tuned by Comma\n      elif candidate in (CAR.CIVIC_BOSCH, CAR.CIVIC_BOSCH_DIESEL):\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 2564, 8000], [0, 2564, 3840]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.09]] #2.5 default mod #Tuned by TMG\n      elif candidate in (CAR.ACCORD, CAR.ACCORDH):\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.09]]\n      elif candidate == CAR.CRV_5G:\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0, 2560, 10000], [0, 2560, 3840]] #tuned by Titanminer (8000)\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.21], [0.07]]\n      elif candidate == CAR.CRV_HYBRID:\n        ret.lateralParams.torqueBP, ret.lateralParams.torqueV = [[0x0, 0xB5, 0x161, 0x2D6, 0x4C0, 0x70D, 0xC42, 0x1058, 0x2C00], [0x0, 0x160, 0x1F0, 0x2E0, 0x378, 0x4A0, 0x5F0, 0x804, 0xF00]]\n        ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.21], [0.07]] #still needs to finish tuning for the new car\n        ret.lateralTuning.pid.kf = 0.00004\n\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  @staticmethod\n  def init(CP, logcan, sendcan):\n    if CP.carFingerprint in HONDA_BOSCH and CP.openpilotLongitudinalControl:\n      disable_radar(logcan, sendcan)\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    # ******************* do can recv *******************\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n    if self.cp_body:\n      self.cp_body.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam, self.cp_body)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.lkMode = self.CS.lkMode\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid and (self.cp_body is None or self.cp_body.can_valid)\n    ret.yawRate = self.VM.yaw_rate(ret.steeringAngleDeg * CV.DEG_TO_RAD, ret.vEgo)\n\n    #dp\n    ret.engineRPM = self.CS.engineRPM\n\n    # dp - brake lights\n    if self.CS.CP.carFingerprint in HONDA_BOSCH:\n     ret.brakeLights = bool(self.CS.brake_switch or\n                            self.CS.brake_lights or self.CS.user_brake > 0.4)\n    else:\n     brakelights_threshold = -0.02 if self.CS.CP.carFingerprint == CAR.CIVIC else -0.1\n     ret.brakeLights = bool(self.CS.brake_switch or\n                            c.actuators.accel < brakelights_threshold)\n\n    buttonEvents = []\n\n    if self.CS.cruise_buttons != self.CS.prev_cruise_buttons:\n      be = car.CarState.ButtonEvent.new_message()\n      be.type = ButtonType.unknown\n      if self.CS.cruise_buttons != 0:\n        be.pressed = True\n        but = self.CS.cruise_buttons\n      else:\n        be.pressed = False\n        but = self.CS.prev_cruise_buttons\n      if but == CruiseButtons.RES_ACCEL:\n        be.type = ButtonType.accelCruise\n      elif but == CruiseButtons.DECEL_SET:\n        be.type = ButtonType.decelCruise\n      elif but == CruiseButtons.CANCEL:\n        be.type = ButtonType.cancel\n      elif but == CruiseButtons.MAIN:\n        be.type = ButtonType.altButton3\n      buttonEvents.append(be)\n\n    if self.CS.cruise_setting != self.CS.prev_cruise_setting:\n      be = car.CarState.ButtonEvent.new_message()\n      be.type = ButtonType.unknown\n      if self.CS.cruise_setting != 0:\n        be.pressed = True\n        but = self.CS.cruise_setting\n      else:\n        be.pressed = False\n        but = self.CS.prev_cruise_setting\n      if but == 1:\n        be.type = ButtonType.altButton1\n      # TODO: more buttons?\n      buttonEvents.append(be)\n    ret.buttonEvents = buttonEvents\n\n    # events\n    events = self.create_common_events(ret, pcm_enable=False)\n    if not self.CS.lkMode or (dragonconf.dpAtl and ret.vEgo <= self.CP.minEnableSpeed):\n      events.add(EventName.manualSteeringRequired)\n    if self.CS.brake_error:\n      events.add(EventName.brakeUnavailable)\n    if self.CS.brake_hold and self.CS.CP.openpilotLongitudinalControl:\n      events.add(EventName.brakeHold)\n    if self.CS.park_brake:\n      events.add(EventName.parkBrake)\n\n    if self.CP.pcmCruise and ret.vEgo < self.CP.minEnableSpeed:\n      events.add(EventName.belowEngageSpeed)\n\n    if self.CP.pcmCruise:\n      # we engage when pcm is active (rising edge)\n      if ret.cruiseState.enabled and not self.CS.out.cruiseState.enabled:\n        events.add(EventName.pcmEnable)\n      elif not ret.cruiseState.enabled and (c.actuators.accel >= 0. or not self.CP.openpilotLongitudinalControl):\n        # it can happen that car cruise disables while comma system is enabled: need to\n        # keep braking if needed or if the speed is very low\n        if ret.vEgo < self.CP.minEnableSpeed + 2.:\n          # non loud alert if cruise disables below 25mph as expected (+ a little margin)\n        #   events.add(EventName.speedTooLow)\n        # else:\n          events.add(EventName.cruiseDisabled)\n    if self.CS.CP.minEnableSpeed > 0 and ret.vEgo < 0.001:\n      events.add(EventName.manualRestart)\n\n    # handle button presses\n    for b in ret.buttonEvents:\n\n      # do enable on both accel and decel buttons\n      if b.type in [ButtonType.accelCruise, ButtonType.decelCruise] and not b.pressed:\n        if not self.CP.pcmCruise:\n          events.add(EventName.buttonEnable)\n\n      # do disable on button down\n      if b.type == ButtonType.cancel and b.pressed:\n        events.add(EventName.buttonCancel)\n\n    ret.events = events.to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  # pass in a car.CarControl\n  # to be called @ 100hz\n  def apply(self, c):\n    if c.hudControl.speedVisible:\n      hud_v_cruise = c.hudControl.setSpeed * CV.MS_TO_KPH\n    else:\n      hud_v_cruise = 255\n\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame,\n                               c.actuators,\n                               c.cruiseControl.speedOverride,\n                               c.cruiseControl.override,\n                               c.cruiseControl.cancel,\n                               c.cruiseControl.accelOverride,\n                               hud_v_cruise,\n                               c.hudControl.lanesVisible,\n                               self.dragonconf,\n                               hud_show_car=c.hudControl.leadVisible,\n                               hud_alert=c.hudControl.visualAlert)\n\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/honda/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.interfaces import RadarInterfaceBase\nfrom selfdrive.car.honda.values import DBC\n\ndef _create_nidec_can_parser(car_fingerprint):\n  radar_messages = [0x400] + list(range(0x430, 0x43A)) + list(range(0x440, 0x446))\n  signals = list(zip(['RADAR_STATE'] +\n                ['LONG_DIST'] * 16 + ['NEW_TRACK'] * 16 + ['LAT_DIST'] * 16 +\n                ['REL_SPEED'] * 16,\n                [0x400] + radar_messages[1:] * 4,\n                [0] + [255] * 16 + [1] * 16 + [0] * 16 + [0] * 16))\n  checks = [(s[1], 20) for s in signals]\n  return CANParser(DBC[car_fingerprint]['radar'], signals, checks, 1)\n\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.track_id = 0\n    self.radar_fault = False\n    self.radar_wrong_config = False\n    self.radar_off_can = CP.radarOffCan\n    self.radar_ts = CP.radarTimeStep\n\n    self.delay = int(round(0.1 / CP.radarTimeStep))   # 0.1s delay of radar\n\n    # Nidec\n    if self.radar_off_can:\n      self.rcp = None\n    else:\n      self.rcp = _create_nidec_can_parser(CP.carFingerprint)\n    self.trigger_msg = 0x445\n    self.updated_messages = set()\n\n  def update(self, can_strings):\n    # in Bosch radar and we are only steering for now, so sleep 0.05s to keep\n    # radard at 20Hz and return no points\n    if self.radar_off_can:\n      return super().update(None)\n\n    vls = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(vls)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    rr = self._update(self.updated_messages)\n    self.updated_messages.clear()\n    return rr\n\n  def _update(self, updated_messages):\n    ret = car.RadarData.new_message()\n\n    for ii in sorted(updated_messages):\n      cpt = self.rcp.vl[ii]\n      if ii == 0x400:\n        # check for radar faults\n        self.radar_fault = cpt['RADAR_STATE'] != 0x79\n        self.radar_wrong_config = cpt['RADAR_STATE'] == 0x69\n      elif cpt['LONG_DIST'] < 255:\n        if ii not in self.pts or cpt['NEW_TRACK']:\n          self.pts[ii] = car.RadarData.RadarPoint.new_message()\n          self.pts[ii].trackId = self.track_id\n          self.track_id += 1\n        self.pts[ii].dRel = cpt['LONG_DIST']  # from front of car\n        self.pts[ii].yRel = -cpt['LAT_DIST']  # in car frame's y axis, left is positive\n        self.pts[ii].vRel = cpt['REL_SPEED']\n        self.pts[ii].aRel = float('nan')\n        self.pts[ii].yvRel = float('nan')\n        self.pts[ii].measured = True\n      else:\n        if ii in self.pts:\n          del self.pts[ii]\n\n    errors = []\n    if not self.rcp.can_valid:\n      errors.append(\"canError\")\n    if self.radar_fault:\n      errors.append(\"fault\")\n    if self.radar_wrong_config:\n      errors.append(\"wrongConfig\")\n    ret.errors = errors\n\n    ret.points = list(self.pts.values())\n\n    return ret\n"
  },
  {
    "path": "selfdrive/car/honda/values.py",
    "content": "from cereal import car\nfrom selfdrive.car import dbc_dict\n\nEcu = car.CarParams.Ecu\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\nclass CarControllerParams():\n  # Allow small margin below -3.5 m/s^2 from ISO 15622:2018 since we\n  # perform the closed loop control, and might need some\n  # to apply some more braking if we're on a downhill slope.\n  # Our controller should still keep the 2 second average above\n  # -3.5 m/s^2 as per planner limits\n  NIDEC_ACCEL_MIN = -4.0 # m/s^2\n  NIDEC_ACCEL_MAX = 1.6 # m/s^2, lower than 2.0 m/s^2 for tuning reasons\n\n  BOSCH_ACCEL_MIN = -3.5 # m/s^2\n  BOSCH_ACCEL_MAX = 2.0 # m/s^2\n\n  def __init__(self, CP):\n    self.BRAKE_MAX = 1024//4\n    self.STEER_MAX = CP.lateralParams.torqueBP[-1]\n    # mirror of list (assuming first item is zero) for interp of signed request values\n    assert(CP.lateralParams.torqueBP[0] == 0)\n    assert(CP.lateralParams.torqueBP[0] == 0)\n    self.STEER_LOOKUP_BP = [v * -1 for v in CP.lateralParams.torqueBP][1:][::-1] + list(CP.lateralParams.torqueBP)\n    self.STEER_LOOKUP_V = [v * -1 for v in CP.lateralParams.torqueV][1:][::-1] + list(CP.lateralParams.torqueV)\n\n    self.NIDEC_ACCEL_LOOKUP_BP = [-1., 0., .6]\n    self.NIDEC_ACCEL_LOOKUP_V = [-4.8, 0., 2.0]\n\n    self.NIDEC_MAX_ACCEL_V = [0.5, 2.4, 1.4, 0.6]\n    self.NIDEC_MAX_ACCEL_BP = [0.0, 4.0, 10., 20.]\n\n    self.BOSCH_GAS_LOOKUP_BP = [0., 2.0]  # 2m/s^2\n    self.BOSCH_GAS_LOOKUP_V = [0, 2000]\n\n\n# Car button codes\nclass CruiseButtons:\n  RES_ACCEL = 4\n  DECEL_SET = 3\n  CANCEL = 2\n  MAIN = 1\n\n# See dbc files for info on values\nVISUAL_HUD = {\n  VisualAlert.none: 0,\n  VisualAlert.fcw: 1,\n  VisualAlert.steerRequired: 1,\n  VisualAlert.ldw: 1,\n  VisualAlert.brakePressed: 10,\n  VisualAlert.wrongGear: 6,\n  VisualAlert.seatbeltUnbuckled: 5,\n  VisualAlert.speedTooHigh: 8\n}\n\nclass CAR:\n  ACCORD = \"HONDA ACCORD 2018\"\n  ACCORDH = \"HONDA ACCORD HYBRID 2018\"\n  CIVIC = \"HONDA CIVIC 2016\"\n  CIVIC_BOSCH = \"HONDA CIVIC (BOSCH) 2019\"\n  CIVIC_BOSCH_DIESEL = \"HONDA CIVIC SEDAN 1.6 DIESEL 2019\"\n  ACURA_ILX = \"ACURA ILX 2016\"\n  CRV = \"HONDA CR-V 2016\"\n  CRV_5G = \"HONDA CR-V 2017\"\n  CRV_EU = \"HONDA CR-V EU 2016\"\n  CRV_HYBRID = \"HONDA CR-V HYBRID 2019\"\n  FIT = \"HONDA FIT 2018\"\n  HRV = \"HONDA HRV 2019\"\n  ODYSSEY = \"HONDA ODYSSEY 2018\"\n  ODYSSEY_CHN = \"HONDA ODYSSEY CHN 2019\"\n  ACURA_RDX = \"ACURA RDX 2018\"\n  ACURA_RDX_3G = \"ACURA RDX 2020\"\n  PILOT = \"HONDA PILOT 2017\"\n  PILOT_2019 = \"HONDA PILOT 2019\"\n  RIDGELINE = \"HONDA RIDGELINE 2017\"\n  INSIGHT = \"HONDA INSIGHT 2019\"\n  HONDA_E = \"HONDA E 2020\"\n  JADE = \"HONDA JADE 2017\"\n\n# diag message that in some Nidec cars only appear with 1s freq if VIN query is performed\nDIAG_MSGS = {1600: 5, 1601: 8}\n\nFINGERPRINTS = {\n  CAR.ACCORDH: [{\n    148: 8, 228: 5, 304: 8, 330: 8, 344: 8, 380: 8, 387: 8, 388: 8, 399: 7, 419: 8, 420: 8, 427: 3, 432: 7, 441: 5, 450: 8, 464: 8, 477: 8, 479: 8, 495: 8, 525: 8, 545: 6, 662: 4, 773: 7, 777: 8, 780: 8, 804: 8, 806: 8, 808: 8, 829: 5, 862: 8, 884: 8, 891: 8, 927: 8, 929: 8, 1302: 8, 1600: 5, 1601: 8, 1652: 8\n  }],\n  CAR.ACURA_RDX: [{\n    57: 3, 145: 8, 229: 4, 308: 5, 316: 8, 342: 6, 344: 8, 380: 8, 392: 6, 398: 3, 399: 6, 404: 4, 420: 8, 422: 8, 426: 8, 432: 7, 464: 8, 474: 5, 476: 4, 487: 4, 490: 8, 506: 8, 512: 6, 513: 6, 542: 7, 545: 4, 597: 8, 660: 8, 773: 7, 777: 8, 780: 8, 800: 8, 804: 8, 808: 8, 819: 7, 821: 5, 829: 5, 882: 2, 884: 7, 887: 8, 888: 8, 892: 8, 923: 2, 929: 4, 963: 8, 965: 8, 966: 8, 967: 8, 983: 8, 985: 3, 1024: 5, 1027: 5, 1029: 8, 1033: 5, 1034: 5, 1036: 8, 1039: 8, 1057: 5, 1064: 7, 1108: 8, 1365: 5, 1424: 5, 1729: 1\n  }],\n  CAR.CIVIC: [{\n    57: 3, 148: 8, 228: 5, 304: 8, 330: 8, 344: 8, 380: 8, 399: 7, 401: 8, 420: 8, 427: 3, 428: 8, 432: 7, 450: 8, 464: 8, 470: 2, 476: 7, 487: 4, 490: 8, 493: 5, 506: 8, 512: 6, 513: 6, 545: 6, 597: 8, 662: 4, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 806: 8, 808: 8, 829: 5, 862: 8, 884: 8, 891: 8, 892: 8, 927: 8, 929: 8, 985: 3, 1024: 5, 1027: 5, 1029: 8, 1036: 8, 1039: 8, 1108: 8, 1302: 8, 1322: 5, 1361: 5, 1365: 5, 1424: 5, 1633: 8,\n  }],\n  CAR.CIVIC_BOSCH: [{\n    57: 3, 148: 8, 228: 5, 304: 8, 330: 8, 344: 8, 380: 8, 399: 7, 401: 8, 420: 8, 427: 3, 428: 8, 432: 7, 441: 5, 450: 8, 460: 3, 464: 8, 470: 2, 476: 7, 477: 8, 479: 8, 490: 8, 493: 5, 495: 8, 506: 8, 545: 6, 597: 8, 662: 4, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 806: 8, 808: 8, 829: 5, 862: 8, 884: 8, 891: 8, 892: 8, 927: 8, 929: 8, 985: 3, 1024: 5, 1027: 5, 1029: 8, 1036: 8, 1039: 8, 1108: 8, 1302: 8, 1322: 5, 1361: 5, 1365: 5, 1424: 5, 1600: 5, 1601: 8, 1625: 5, 1629: 5, 1633: 8,\n  },\n  {\n    57: 3, 148: 8, 228: 5, 304: 8, 330: 8, 344: 8, 380: 8, 399: 7, 401: 8, 420: 8, 423: 2, 427: 3, 428: 8, 432: 7, 441: 5, 450: 8, 464: 8, 470: 2, 476: 7, 477: 8, 479: 8, 490: 8, 493: 5, 495: 8, 506: 8, 545: 6, 597: 8, 662: 4, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 806: 8, 808: 8, 815: 8, 825: 4, 829: 5, 846: 8, 862: 8, 881: 8, 882: 4, 884: 8, 888: 8, 891: 8, 892: 8, 918: 7, 927: 8, 929: 8, 983: 8, 985: 3, 1024: 5, 1027: 5, 1029: 8, 1036: 8, 1039: 8, 1064: 7, 1092: 1, 1108: 8, 1125: 8, 1127: 2, 1296: 8, 1302: 8, 1322: 5, 1361: 5, 1365: 5, 1424: 5, 1600: 5, 1601: 8, 1633: 8\n  }],\n  CAR.CRV_5G: [{\n    57: 3, 148: 8, 199: 4, 228: 5, 231: 5, 232: 7, 304: 8, 330: 8, 340: 8, 344: 8, 380: 8, 399: 7, 401: 8, 420: 8, 423: 2, 427: 3, 428: 8, 432: 7, 441: 5, 446: 3, 450: 8, 464: 8, 467: 2, 469: 3, 470: 2, 474: 8, 476: 7, 477: 8, 479: 8, 490: 8, 493: 5, 495: 8, 507: 1, 545: 6, 597: 8, 661: 4, 662: 4, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 806: 8, 808: 8, 814: 4, 815: 8, 817: 4, 825: 4, 829: 5, 862: 8, 881: 8, 882: 4, 884: 8, 888: 8, 891: 8, 927: 8, 918: 7, 929: 8, 983: 8, 985: 3, 1024: 5, 1027: 5, 1029: 8, 1036: 8, 1039: 8, 1064: 7, 1108: 8, 1092: 1, 1115: 2, 1125: 8, 1127: 2, 1296: 8, 1302: 8, 1322: 5, 1361: 5, 1365: 5, 1424: 5, 1600: 5, 1601: 8, 1618: 5, 1633: 8, 1670: 5\n  }],\n  CAR.ODYSSEY: [{\n    57: 3, 148: 8, 228: 5, 229: 4, 316: 8, 342: 6, 344: 8, 380: 8, 399: 7, 411: 5, 419: 8, 420: 8, 427: 3, 432: 7, 450: 8, 463: 8, 464: 8, 476: 4, 490: 8, 506: 8, 512: 6, 513: 6, 542: 7, 545: 6, 597: 8, 662: 4, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 806: 8, 808: 8, 817: 4, 819: 7, 821: 5, 825: 4, 829: 5, 837: 5, 856: 7, 862: 8, 871: 8, 881: 8, 882: 4, 884: 8, 891: 8, 892: 8, 905: 8, 923: 2, 927: 8, 929: 8, 963: 8, 965: 8, 966: 8, 967: 8, 983: 8, 985: 3, 1029: 8, 1036: 8, 1052: 8, 1064: 7, 1088: 8, 1089: 8, 1092: 1, 1108: 8, 1110: 8, 1125: 8, 1296: 8, 1302: 8, 1600: 5, 1601: 8, 1612: 5, 1613: 5, 1614: 5, 1615: 8, 1616: 5, 1619: 5, 1623: 5, 1668: 5\n  },\n  {\n    57: 3, 148: 8, 228: 5, 229: 4, 304: 8, 342: 6, 344: 8, 380: 8, 399: 7, 411: 5, 419: 8, 420: 8, 427: 3, 432: 7, 440: 8, 450: 8, 463: 8, 464: 8, 476: 4, 490: 8, 506: 8, 507: 1, 542: 7, 545: 6, 597: 8, 662: 4, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 806: 8, 808: 8, 817: 4, 819: 7, 821: 5, 825: 4, 829: 5, 837: 5, 856: 7, 862: 8, 871: 8, 881: 8, 882: 4, 884: 8, 891: 8, 892: 8, 905: 8, 923: 2, 927: 8, 929: 8, 963: 8, 965: 8, 966: 8, 967: 8, 983: 8, 985: 3, 1029: 8, 1036: 8, 1052: 8, 1064: 7, 1088: 8, 1089: 8, 1092: 1, 1108: 8, 1110: 8, 1125: 8, 1296: 8, 1302: 8, 1600: 5, 1601: 8, 1612: 5, 1613: 5, 1614: 5, 1616: 5, 1619: 5, 1623: 5, 1668: 5\n  }],\n  CAR.ODYSSEY_CHN: [{\n    57: 3, 145: 8, 316: 8, 342: 6, 344: 8, 380: 8, 398: 3, 399: 7, 401: 8, 404: 4, 411: 5, 420: 8, 422: 8, 423: 2, 426: 8, 432: 7, 450: 8, 464: 8, 490: 8, 506: 8, 507: 1, 512: 6, 513: 6, 597: 8, 610: 8, 611: 8, 612: 8, 617: 8, 660: 8, 661: 4, 773: 7, 780: 8, 804: 8, 808: 8, 829: 5, 862: 8, 884: 7, 892: 8, 923: 2, 929: 8, 1030: 5, 1137: 8, 1302: 8, 1348: 5, 1361: 5, 1365: 5, 1600: 5, 1601: 8, 1639: 8\n  }],\n  CAR.PILOT_2019: [{\n    57: 3, 145: 8, 228: 5, 308: 5, 316: 8, 334: 8, 342: 6, 344: 8, 379: 8, 380: 8, 399: 7, 411: 5, 419: 8, 420: 8, 422: 8, 425: 8, 426: 8, 427: 3, 432: 7, 463: 8, 464: 8, 476: 4, 490: 8, 506: 8, 512: 6, 513: 6, 538: 3, 542: 7, 545: 5, 546: 3, 597: 8, 660: 8, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 808: 8, 817: 4, 819: 7, 821: 5, 825: 4, 829: 5, 837: 5, 856: 7, 871: 8, 881: 8, 882: 2, 884: 7, 891: 8, 892: 8, 923: 2, 927: 8, 929: 8, 983: 8, 985: 3, 1029: 8, 1052: 8, 1064: 7, 1088: 8, 1089: 8, 1092: 1, 1108: 8, 1110: 8, 1125: 8, 1296: 8, 1424: 5, 1445: 8, 1600: 5, 1601: 8, 1612: 5, 1613: 5, 1614: 5, 1615: 8, 1616: 5, 1617: 8, 1618: 5, 1623: 5, 1668: 5\n  },\n  {\n    57: 3, 145: 8, 228: 5, 229: 4, 308: 5, 316: 8, 339: 7, 342: 6, 344: 8, 380: 8, 392: 6, 399: 7, 411: 5, 419: 8, 420: 8, 422: 8, 425: 8, 426: 8, 427: 3, 432: 7, 464: 8, 476: 4, 490: 8, 506: 8, 512: 6, 513: 6, 542: 7, 545: 5, 546: 3, 597: 8, 660: 8, 773: 7, 777: 8, 780: 8, 795: 8, 800: 8, 804: 8, 808: 8, 817: 4, 819: 7, 821: 5, 829: 5, 871: 8, 881: 8, 882: 2, 884: 7, 891: 8, 892: 8, 923: 2, 927: 8, 929: 8, 963: 8, 965: 8, 966: 8, 967: 8, 983: 8, 985: 3, 1027: 5, 1029: 8, 1039: 8, 1064: 7, 1088: 8, 1089: 8, 1092: 1, 1108: 8, 1125: 8, 1296: 8, 1424: 5, 1445: 8, 1600: 5, 1601: 8, 1612: 5, 1613: 5, 1616: 5, 1617: 8, 1618: 5, 1623: 5, 1668: 5\n  }],\n  CAR.JADE: [{\n    57: 3, 145: 8, 228: 5, 304: 8, 342: 6, 344: 8, 380: 8, 398: 3, 399: 7, 401: 8, 420: 8, 422: 8, 428: 8, 432: 7, 464: 8, 487: 4, 490: 8, 506: 8, 507: 1, 512: 6, 513: 6, 597: 8, 660: 8, 661: 4, 773: 7, 777: 8, 780: 8, 804: 8, 808: 8, 829: 5, 862: 8, 884: 7, 892: 8, 923: 2, 929: 4, 1057: 5, 1365: 5, 1424: 5, 1600: 5, 1601: 8\n  }],\n}\n\n# add DIAG_MSGS to fingerprints\nfor c in FINGERPRINTS:\n  for f, _ in enumerate(FINGERPRINTS[c]):\n    for d in DIAG_MSGS:\n      FINGERPRINTS[c][f][d] = DIAG_MSGS[d]\n\n# TODO: Figure out what is relevant\nFW_VERSIONS = {\n  CAR.ACCORD: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-6A0-A640\\x00\\x00',\n      b'37805-6B2-A550\\x00\\x00',\n      b'37805-6B2-A560\\x00\\x00',\n      b'37805-6B2-A650\\x00\\x00',\n      b'37805-6B2-A660\\x00\\x00',\n      b'37805-6B2-A720\\x00\\x00',\n      b'37805-6B2-A810\\x00\\x00',\n      b'37805-6B2-A820\\x00\\x00',\n      b'37805-6B2-A920\\x00\\x00',\n      b'37805-6B2-M520\\x00\\x00',\n      b'37805-6A0-9520\\x00\\x00',\n      b'37805-6A0-9620\\x00\\x00',\n      b'37805-6A0-9720\\x00\\x00',\n      b'37805-6A0-A540\\x00\\x00',\n      b'37805-6A0-A550\\x00\\x00',\n      b'37805-6A0-A650\\x00\\x00',\n      b'37805-6A0-A740\\x00\\x00',\n      b'37805-6A0-A750\\x00\\x00',\n      b'37805-6A0-A840\\x00\\x00',\n      b'37805-6A0-A850\\x00\\x00',\n      b'37805-6A0-C540\\x00\\x00',\n      b'37805-6A1-H650\\x00\\x00',\n      b'37805-6M4-B730\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TVC-A910\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28102-6B8-A560\\x00\\x00',\n      b'28102-6B8-A570\\x00\\x00',\n      b'28102-6B8-A700\\x00\\x00',\n      b'28102-6B8-A800\\x00\\x00',\n      b'28102-6B8-C560\\x00\\x00',\n      b'28102-6B8-C570\\x00\\x00',\n      b'28102-6B8-M520\\x00\\x00',\n      b'28101-6A7-A220\\x00\\x00',\n      b'28101-6A7-A230\\x00\\x00',\n      b'28101-6A7-A320\\x00\\x00',\n      b'28101-6A7-A330\\x00\\x00',\n      b'28101-6A7-A410\\x00\\x00',\n      b'28101-6A7-A510\\x00\\x00',\n      b'28101-6A9-H140\\x00\\x00',\n      b'28101-6A9-H420\\x00\\x00',\n    ],\n    (Ecu.electricBrakeBooster, 0x18da2bf1, None): [\n      b'46114-TVA-A060\\x00\\x00',\n      b'46114-TVA-A080\\x00\\x00',\n      b'46114-TVA-A120\\x00\\x00',\n      b'46114-TVA-A320\\x00\\x00',\n      b'46114-TVA-A050\\x00\\x00',\n      b'46114-TVE-H550\\x00\\x00',\n      b'46114-TVE-H560\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TVA-C040\\x00\\x00',\n      b'57114-TVA-C050\\x00\\x00',\n      b'57114-TVA-C060\\x00\\x00',\n      b'57114-TVA-C530\\x00\\x00',\n      b'57114-TVA-B040\\x00\\x00',\n      b'57114-TVA-B050\\x00\\x00',\n      b'57114-TVA-B060\\x00\\x00',\n      b'57114-TVE-H250\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TVA,A150\\x00\\x00',\n      b'39990-TVA-A150\\x00\\x00',\n      b'39990-TVA-A160\\x00\\x00',\n      b'39990-TVA-A340\\x00\\x00',\n      b'39990-TVA-X030\\x00\\x00',\n      b'39990-TVA-A140\\x00\\x00',\n      b'39990-TVE-H130\\x00\\x00',\n      b'39990-TBX-H120\\x00\\x00',\n    ],\n    (Ecu.unknown, 0x18da3af1, None): [\n      b'39390-TVA-A020\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TVA-A460\\x00\\x00',\n      b'77959-TVA-L420\\x00\\x00',\n      b'77959-TVA-X330\\x00\\x00',\n      b'77959-TVA-H230\\x00\\x00',\n      b'77959-TBX-H230\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TVC-C010\\x00\\x00',\n      b'78109-TVA-A210\\x00\\x00',\n      b'78109-TVC-A010\\x00\\x00',\n      b'78109-TVC-A020\\x00\\x00',\n      b'78109-TVC-A030\\x00\\x00',\n      b'78109-TVC-A110\\x00\\x00',\n      b'78109-TVC-A130\\x00\\x00',\n      b'78109-TVC-A210\\x00\\x00',\n      b'78109-TVC-A220\\x00\\x00',\n      b'78109-TVC-C110\\x00\\x00',\n      b'78109-TVC-L010\\x00\\x00',\n      b'78109-TVC-L210\\x00\\x00',\n      b'78109-TVC-M510\\x00\\x00',\n      b'78109-TBX-H310\\x00\\x00',\n      b'78109-TVA-A010\\x00\\x00',\n      b'78109-TVA-A020\\x00\\x00',\n      b'78109-TVA-A110\\x00\\x00',\n      b'78109-TVA-A120\\x00\\x00',\n      b'78109-TVA-A220\\x00\\x00',\n      b'78109-TVA-A310\\x00\\x00',\n      b'78109-TVA-C010\\x00\\x00',\n      b'78109-TVA-L010\\x00\\x00',\n      b'78109-TVA-L210\\x00\\x00',\n      b'78109-TVE-H610\\x00\\x00',\n      b'78109-TWA-A210\\x00\\x00',\n    ],\n    (Ecu.hud, 0x18da61f1, None): [\n      b'78209-TVA-A010\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TVA-A160\\x00\\x00',\n      b'36802-TVA-A170\\x00\\x00',\n      b'36802-TVC-A330\\x00\\x00',\n      b'36802-TWA-A070\\x00\\x00',\n      b'36802-TVA-A150\\x00\\x00',\n      b'36802-TVE-H070\\x00\\x00',\n      b'36802-TBX-H140\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TVA-A060\\x00\\x00',\n      b'36161-TVC-A330\\x00\\x00',\n      b'36161-TWA-A070\\x00\\x00',\n      b'36161-TVE-H050\\x00\\x00',\n      b'36161-TBX-H130\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TVA-A010\\x00\\x00',\n      b'38897-TVA-A020\\x00\\x00',\n      b'38897-TVA-A230\\x00\\x00',\n    ],\n  },\n  CAR.ACCORDH: {\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TWA-A120\\x00\\x00',\n      b'38897-TWD-J020\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TWA-A040\\x00\\x00',\n      b'57114-TWA-A050\\x00\\x00',\n      b'57114-TWA-B520\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TWA-A440\\x00\\x00',\n      b'77959-TWA-L420\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TWA-A010\\x00\\x00',\n      b'78109-TWA-A020\\x00\\x00',\n      b'78109-TWA-A030\\x00\\x00',\n      b'78109-TWA-A110\\x00\\x00',\n      b'78109-TWA-A120\\x00\\x00',\n      b'78109-TWA-A210\\x00\\x00',\n      b'78109-TWA-A220\\x00\\x00',\n      b'78109-TWA-L010\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TWA-A910\\x00\\x00',\n    ],\n    (Ecu.hud, 0x18da61f1, None): [\n      b'78209-TVA-A010\\x00\\x00',\n      b'78209-TVA-A110\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TWA-A070\\x00\\x00',\n      b'36161-TWA-A330\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TWA-A080\\x00\\x00',\n      b'36802-TWA-A070\\x00\\x00',\n      b'36802-TWA-A330\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TVA-A160\\x00\\x00',\n      b'39990-TVA-A150\\x00\\x00',\n      b'39990-TVA-A340\\x00\\x00',\n    ],\n  },\n  CAR.CIVIC: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-5AA-A640\\x00\\x00',\n      b'37805-5AA-A650\\x00\\x00',\n      b'37805-5AA-A670\\x00\\x00',\n      b'37805-5AA-A680\\x00\\x00',\n      b'37805-5AA-A810\\x00\\x00',\n      b'37805-5AA-C640\\x00\\x00',\n      b'37805-5AA-C680\\x00\\x00',\n      b'37805-5AA-C820\\x00\\x00',\n      b'37805-5AA-L650\\x00\\x00',\n      b'37805-5AA-L660\\x00\\x00',\n      b'37805-5AA-L680\\x00\\x00',\n      b'37805-5AA-L690\\x00\\x00',\n      b'37805-5AA-L810\\000\\000',\n      b'37805-5AG-Q710\\x00\\x00',\n      b'37805-5AJ-A610\\x00\\x00',\n      b'37805-5AJ-A620\\x00\\x00',\n      b'37805-5AJ-L610\\x00\\x00',\n      b'37805-5BA-A310\\x00\\x00',\n      b'37805-5BA-A510\\x00\\x00',\n      b'37805-5BA-A740\\x00\\x00',\n      b'37805-5BA-A760\\x00\\x00',\n      b'37805-5BA-A930\\x00\\x00',\n      b'37805-5BA-A960\\x00\\x00',\n      b'37805-5BA-C860\\x00\\x00',\n      b'37805-5BA-L410\\x00\\x00',\n      b'37805-5BA-L760\\x00\\x00',\n      b'37805-5BA-L930\\x00\\x00',\n      b'37805-5BA-L940\\x00\\x00',\n      b'37805-5BA-L960\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-5CG-A040\\x00\\x00',\n      b'28101-5CG-A050\\x00\\x00',\n      b'28101-5CG-A070\\x00\\x00',\n      b'28101-5CG-A080\\x00\\x00',\n      b'28101-5CG-A320\\x00\\x00',\n      b'28101-5CG-A810\\x00\\x00',\n      b'28101-5CG-A820\\x00\\x00',\n      b'28101-5DJ-A040\\x00\\x00',\n      b'28101-5DJ-A060\\x00\\x00',\n      b'28101-5DJ-A510\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TBA-A540\\x00\\x00',\n      b'57114-TBA-A550\\x00\\x00',\n      b'57114-TBA-A560\\x00\\x00',\n      b'57114-TBA-A570\\x00\\x00',\n      b'57114-TEA-Q220\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TBA,A030\\x00\\x00', # modified firmware\n      b'39990-TBA-A030\\x00\\x00',\n      b'39990-TBG-A030\\x00\\x00',\n      b'39990-TEA-T020\\x00\\x00',\n      b'39990-TEG-A010\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TBA-A030\\x00\\x00',\n      b'77959-TBA-A040\\x00\\x00',\n      b'77959-TBG-A030\\x00\\x00',\n      b'77959-TEA-Q820\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TBA-A510\\x00\\x00',\n      b'78109-TBA-A520\\x00\\x00',\n      b'78109-TBA-A530\\x00\\x00',\n      b'78109-TBA-C520\\x00\\x00',\n      b'78109-TBC-A310\\x00\\x00',\n      b'78109-TBC-A320\\x00\\x00',\n      b'78109-TBC-A510\\x00\\x00',\n      b'78109-TBC-A520\\x00\\x00',\n      b'78109-TBC-A530\\x00\\x00',\n      b'78109-TBC-C510\\x00\\x00',\n      b'78109-TBC-C520\\x00\\x00',\n      b'78109-TBC-C530\\x00\\x00',\n      b'78109-TBH-A510\\x00\\x00',\n      b'78109-TBH-A530\\x00\\x00',\n      b'78109-TED-Q510\\x00\\x00',\n      b'78109-TEG-A310\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab0f1, None): [\n      b'36161-TBA-A020\\x00\\x00',\n      b'36161-TBA-A030\\x00\\x00',\n      b'36161-TBA-A040\\x00\\x00',\n      b'36161-TBC-A020\\x00\\x00',\n      b'36161-TBC-A030\\x00\\x00',\n      b'36161-TED-Q320\\x00\\x00',\n      b'36161-TEG-A010\\x00\\x00',\n      b'36161-TEG-A020\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TBA-A010\\x00\\x00',\n      b'38897-TBA-A020\\x00\\x00',\n    ],\n  },\n  CAR.CIVIC_BOSCH: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-5AA-A940\\x00\\x00',\n      b'37805-5AA-A950\\x00\\x00',\n      b'37805-5AA-L940\\x00\\x00',\n      b'37805-5AA-L950\\x00\\x00',\n      b'37805-5AG-Z910\\x00\\x00',\n      b'37805-5AJ-A750\\x00\\x00',\n      b'37805-5AJ-L750\\x00\\x00',\n      b'37805-5AN-A750\\x00\\x00',\n      b'37805-5AN-A830\\x00\\x00',\n      b'37805-5AN-A840\\x00\\x00',\n      b'37805-5AN-A930\\x00\\x00',\n      b'37805-5AN-A940\\x00\\x00',\n      b'37805-5AN-A950\\x00\\x00',\n      b'37805-5AN-AG20\\x00\\x00',\n      b'37805-5AN-AH20\\x00\\x00',\n      b'37805-5AN-AJ30\\x00\\x00',\n      b'37805-5AN-AK20\\x00\\x00',\n      b'37805-5AN-AR20\\x00\\x00',\n      b'37805-5AN-CH20\\x00\\x00',\n      b'37805-5AN-E630\\x00\\x00',\n      b'37805-5AN-E720\\x00\\x00',\n      b'37805-5AN-E820\\x00\\x00',\n      b'37805-5AN-J820\\x00\\x00',\n      b'37805-5AN-L840\\x00\\x00',\n      b'37805-5AN-L930\\x00\\x00',\n      b'37805-5AN-L940\\x00\\x00',\n      b'37805-5AN-LF20\\x00\\x00',\n      b'37805-5AN-LH20\\x00\\x00',\n      b'37805-5AN-LJ20\\x00\\x00',\n      b'37805-5AN-LR20\\x00\\x00',\n      b'37805-5AN-LS20\\x00\\x00',\n      b'37805-5AW-G720\\x00\\x00',\n      b'37805-5AZ-E850\\x00\\x00',\n      b'37805-5AZ-G740\\x00\\x00',\n      b'37805-5AZ-G840\\x00\\x00',\n      b'37805-5BB-A530\\x00\\x00',\n      b'37805-5BB-A540\\x00\\x00',\n      b'37805-5BB-A630\\x00\\x00',\n      b'37805-5BB-A640\\x00\\x00',\n      b'37805-5BB-C540\\x00\\x00',\n      b'37805-5BB-C630\\x00\\x00',\n      b'37805-5BB-C640\\x00\\x00',\n      b'37805-5BB-L540\\x00\\x00',\n      b'37805-5BB-L630\\x00\\x00',\n      b'37805-5BB-L640\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-5CG-A920\\x00\\x00',\n      b'28101-5CG-AB10\\x00\\x00',\n      b'28101-5CG-C110\\x00\\x00',\n      b'28101-5CG-C220\\x00\\x00',\n      b'28101-5CG-C320\\x00\\x00',\n      b'28101-5CG-G020\\x00\\x00',\n      b'28101-5CG-L020\\x00\\x00',\n      b'28101-5CK-A130\\x00\\x00',\n      b'28101-5CK-A140\\x00\\x00',\n      b'28101-5CK-A150\\x00\\x00',\n      b'28101-5CK-C130\\x00\\x00',\n      b'28101-5CK-C140\\x00\\x00',\n      b'28101-5CK-C150\\x00\\x00',\n      b'28101-5CK-G210\\x00\\x00',\n      b'28101-5CK-J710\\x00\\x00',\n      b'28101-5CK-Q610\\x00\\x00',\n      b'28101-5DJ-A610\\x00\\x00',\n      b'28101-5DJ-A710\\x00\\x00',\n      b'28101-5DV-E330\\x00\\x00',\n      b'28101-5DV-E610\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TBG-A330\\x00\\x00',\n      b'57114-TBG-A340\\x00\\x00',\n      b'57114-TBG-A350\\x00\\x00',\n      b'57114-TGG-A340\\x00\\x00',\n      b'57114-TGG-C320\\x00\\x00',\n      b'57114-TGG-G320\\x00\\x00',\n      b'57114-TGG-L320\\x00\\x00',\n      b'57114-TGG-L330\\x00\\x00',\n      b'57114-TGK-T320\\x00\\x00',\n      b'57114-TGL-G330\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TBA-C020\\x00\\x00',\n      b'39990-TBA-C120\\x00\\x00',\n      b'39990-TEA-T820\\x00\\x00',\n      b'39990-TEZ-T020\\x00\\x00',\n      b'39990-TGG-A020\\x00\\x00',\n      b'39990-TGG-A120\\x00\\x00',\n      b'39990-TGG-J510\\x00\\x00',\n      b'39990-TGL-E130\\x00\\x00',\n      b'39990-TGN-E120\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TBA-A060\\x00\\x00',\n      b'77959-TBG-A050\\x00\\x00',\n      b'77959-TEA-G020\\x00\\x00',\n      b'77959-TGG-A020\\x00\\x00',\n      b'77959-TGG-A030\\x00\\x00',\n      b'77959-TGG-G010\\x00\\x00',\n      b'77959-TGG-J320\\x00\\x00',\n      b'77959-TGG-Z820\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TBA-A110\\x00\\x00',\n      b'78109-TBA-A910\\x00\\x00',\n      b'78109-TBA-C340\\x00\\x00',\n      b'78109-TBA-C910\\x00\\x00',\n      b'78109-TBC-A740\\x00\\x00',\n      b'78109-TBG-A110\\x00\\x00',\n      b'78109-TEG-A720\\x00\\x00',\n      b'78109-TFJ-G020\\x00\\x00',\n      b'78109-TGG-9020\\x00\\x00',\n      b'78109-TGG-A210\\x00\\x00',\n      b'78109-TGG-A220\\x00\\x00',\n      b'78109-TGG-A310\\x00\\x00',\n      b'78109-TGG-A320\\x00\\x00',\n      b'78109-TGG-A330\\x00\\x00',\n      b'78109-TGG-A610\\x00\\x00',\n      b'78109-TGG-A620\\x00\\x00',\n      b'78109-TGG-A810\\x00\\x00',\n      b'78109-TGG-A820\\x00\\x00',\n      b'78109-TGG-C220\\x00\\x00',\n      b'78109-TGG-G030\\x00\\x00',\n      b'78109-TGG-G230\\x00\\x00',\n      b'78109-TGG-G410\\x00\\x00',\n      b'78109-TGK-Z410\\x00\\x00',\n      b'78109-TGL-G120\\x00\\x00',\n      b'78109-TGL-G130\\x00\\x00',\n      b'78109-TGL-G230\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TBA-A150\\x00\\x00',\n      b'36802-TBA-A160\\x00\\x00',\n      b'36802-TFJ-G060\\x00\\x00',\n      b'36802-TGG-A050\\x00\\x00',\n      b'36802-TGG-A060\\x00\\x00',\n      b'36802-TGG-A130\\x00\\x00',\n      b'36802-TGG-G040\\x00\\x00',\n      b'36802-TGG-G130\\x00\\x00',\n      b'36802-TGK-Q120\\x00\\x00',\n      b'36802-TGL-G040\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TBA-A130\\x00\\x00',\n      b'36161-TBA-A140\\x00\\x00',\n      b'36161-TFJ-G070\\x00\\x00',\n      b'36161-TGG-A060\\x00\\x00',\n      b'36161-TGG-A080\\x00\\x00',\n      b'36161-TGG-A120\\x00\\x00',\n      b'36161-TGG-G050\\x00\\x00',\n      b'36161-TGG-G130\\x00\\x00',\n      b'36161-TGK-Q120\\x00\\x00',\n      b'36161-TGL-G050\\x00\\x00',\n      b'36161-TGL-G070\\x00\\x00',\n      b'36161-TGG-G070\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TBA-A110\\x00\\x00',\n      b'38897-TBA-A020\\x00\\x00',\n    ],\n    (Ecu.electricBrakeBooster, 0x18da2bf1, None): [\n      b'39494-TGL-G030\\x00\\x00',\n    ],\n  },\n  CAR.CIVIC_BOSCH_DIESEL: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-59N-G630\\x00\\x00',\n      b'37805-59N-G830\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-59Y-G220\\x00\\x00',\n      b'28101-59Y-G620\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TGN-E320\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TFK-G020\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TFK-G210\\x00\\x00',\n      b'77959-TGN-G220\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TFK-G020\\x00\\x00',\n      b'78109-TGN-G120\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TFK-G130\\x00\\x00',\n      b'36802-TGN-G130\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TGN-E010\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TFK-G130\\x00\\x00',\n      b'36161-TGN-G130\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TBA-A020\\x00\\x00',\n    ],\n  },\n  CAR.CRV: {\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-T1W-A230\\x00\\x00',\n      b'57114-T1W-A240\\x00\\x00',\n      b'57114-TFF-A940\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-T0A-A230\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-T1W-A210\\x00\\x00',\n      b'78109-T1W-C210\\x00\\x00',\n      b'78109-T1X-A210\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36161-T1W-A830\\x00\\x00',\n      b'36161-T1W-C830\\x00\\x00',\n      b'36161-T1X-A830\\x00\\x00',\n    ],\n  },\n  CAR.CRV_5G: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-5PA-AH20\\x00\\x00',\n      b'37805-5PA-3060\\x00\\x00',\n      b'37805-5PA-3080\\x00\\x00',\n      b'37805-5PA-3180\\x00\\x00',\n      b'37805-5PA-4050\\x00\\x00',\n      b'37805-5PA-4150\\x00\\x00',\n      b'37805-5PA-6520\\x00\\x00',\n      b'37805-5PA-6530\\x00\\x00',\n      b'37805-5PA-6630\\x00\\x00',\n      b'37805-5PA-6640\\x00\\x00',\n      b'37805-5PA-7630\\x00\\x00',\n      b'37805-5PA-9630\\x00\\x00',\n      b'37805-5PA-9640\\x00\\x00',\n      b'37805-5PA-9730\\x00\\x00',\n      b'37805-5PA-9830\\x00\\x00',\n      b'37805-5PA-9840\\x00\\x00',\n      b'37805-5PA-A650\\x00\\x00',\n      b'37805-5PA-A670\\x00\\x00',\n      b'37805-5PA-A680\\x00\\x00',\n      b'37805-5PA-A850\\x00\\x00',\n      b'37805-5PA-A870\\x00\\x00',\n      b'37805-5PA-A880\\x00\\x00',\n      b'37805-5PA-A890\\x00\\x00',\n      b'37805-5PA-AB10\\x00\\x00',\n      b'37805-5PA-AD10\\x00\\x00',\n      b'37805-5PA-AF20\\x00\\x00',\n      b'37805-5PA-C680\\x00\\x00',\n      b'37805-5PD-Q630\\x00\\x00',\n      b'37805-5PF-F730\\x00\\x00',\n      b'37805-5PF-M630\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-5RG-A020\\x00\\x00',\n      b'28101-5RG-A030\\x00\\x00',\n      b'28101-5RG-A040\\x00\\x00',\n      b'28101-5RG-A120\\x00\\x00',\n      b'28101-5RG-A220\\x00\\x00',\n      b'28101-5RH-A020\\x00\\x00',\n      b'28101-5RH-A030\\x00\\x00',\n      b'28101-5RH-A040\\x00\\x00',\n      b'28101-5RH-A120\\x00\\x00',\n      b'28101-5RH-A220\\x00\\x00',\n      b'28101-5RL-Q010\\x00\\x00',\n      b'28101-5RM-F010\\x00\\x00',\n      b'28101-5RM-K010\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TLA-A040\\x00\\x00',\n      b'57114-TLA-A050\\x00\\x00',\n      b'57114-TLA-A060\\x00\\x00',\n      b'57114-TLB-A830\\x00\\x00',\n      b'57114-TMC-Z040\\x00\\x00',\n      b'57114-TMC-Z050\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TLA-A040\\x00\\x00',\n      b'39990-TLA-A110\\x00\\x00',\n      b'39990-TLA-A220\\x00\\x00',\n      b'39990-TLA,A040\\x00\\x00', # modified firmware\n      b'39990-TME-T030\\x00\\x00',\n      b'39990-TME-T120\\x00\\x00',\n      b'39990-TMT-T010\\x00\\x00',\n    ],\n    (Ecu.electricBrakeBooster, 0x18da2bf1, None): [\n      b'46114-TLA-A040\\x00\\x00',\n      b'46114-TLA-A050\\x00\\x00',\n      b'46114-TLA-A930\\x00\\x00',\n      b'46114-TMC-U020\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TLA-A110\\x00\\x00',\n      b'78109-TLA-A120\\x00\\x00',\n      b'78109-TLA-A210\\x00\\x00',\n      b'78109-TLA-A220\\x00\\x00',\n      b'78109-TLA-C110\\x00\\x00',\n      b'78109-TLA-C210\\x00\\x00',\n      b'78109-TLA-C310\\x00\\x00',\n      b'78109-TLB-A020\\x00\\x00',\n      b'78109-TLB-A110\\x00\\x00',\n      b'78109-TLB-A120\\x00\\x00',\n      b'78109-TLB-A210\\x00\\x00',\n      b'78109-TLB-A220\\x00\\x00',\n      b'78109-TMC-Q210\\x00\\x00',\n      b'78109-TMM-F210\\x00\\x00',\n      b'78109-TMM-M110\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TLA-A010\\x00\\x00',\n      b'38897-TLA-A110\\x00\\x00',\n      b'38897-TNY-G010\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TLA-A040\\x00\\x00',\n      b'36802-TLA-A050\\x00\\x00',\n      b'36802-TLA-A060\\x00\\x00',\n      b'36802-TMC-Q040\\x00\\x00',\n      b'36802-TMC-Q070\\x00\\x00',\n      b'36802-TNY-A030\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TLA-A060\\x00\\x00',\n      b'36161-TLA-A070\\x00\\x00',\n      b'36161-TLA-A080\\x00\\x00',\n      b'36161-TMC-Q020\\x00\\x00',\n      b'36161-TMC-Q030\\x00\\x00',\n      b'36161-TMC-Q040\\x00\\x00',\n      b'36161-TNY-A020\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TLA-A240\\x00\\x00',\n      b'77959-TLA-A250\\x00\\x00',\n      b'77959-TLA-A320\\x00\\x00',\n      b'77959-TLA-A410\\x00\\x00',\n      b'77959-TLA-A420\\x00\\x00',\n      b'77959-TLA-Q040\\x00\\x00',\n      b'77959-TLA-Z040\\x00\\x00',\n      b'77959-TMM-F040\\x00\\x00',\n    ],\n  },\n  CAR.CRV_EU: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-R5Z-G740\\x00\\x00',\n      b'37805-R5Z-G780\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [b'57114-T1V-G920\\x00\\x00'],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [b'36161-T1V-G520\\x00\\x00'],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [b'54008-T1V-G010\\x00\\x00'],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-5LH-E120\\x00\\x00',\n      b'28103-5LH-E100\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-T1V-G020\\x00\\x00',\n      b'78109-T1B-3050\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [b'77959-T1G-G940\\x00\\x00'],\n  },\n  CAR.CRV_HYBRID: {\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TPA-G020\\x00\\x00',\n      b'57114-TPG-A020\\x00\\x00',\n      b'57114-TMB-H030\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TPA-G030\\x00\\x00',\n      b'39990-TPG-A020\\x00\\x00',\n      b'39990-TMA-H020\\x00\\x00',\n      b'39990-TMA,H020\\x00\\x00',\n      b'39990,TMA-H020\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TMA-H110\\x00\\x00',\n      b'38897-TPG-A110\\x00\\x00',\n      b'38897-TPG-A210\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TMB-H510\\x00\\x00',\n      b'54008-TMB-H610\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TMB-H040\\x00\\x00',\n      b'36161-TPA-E050\\x00\\x00',\n      b'36161-TPG-A030\\x00\\x00',\n      b'36161-TPG-A040\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TMB-H220\\x00\\x00',\n      b'78109-TPA-G520\\x00\\x00',\n      b'78109-TPG-A110\\x00\\x00',\n      b'78109-TPG-A210\\x00\\x00',\n    ],\n    (Ecu.hud, 0x18da61f1, None): [\n      b'78209-TLA-X010\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TPA-E040\\x00\\x00',\n      b'36802-TPG-A020\\x00\\x00',\n      b'36802-TMB-H040\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TLA-C320\\x00\\x00',\n      b'77959-TLA-C410\\x00\\x00',\n      b'77959-TLA-C420\\x00\\x00',\n      b'77959-TLA-G220\\x00\\x00',\n      b'77959-TLA-H240\\x00\\x00',\n    ],\n  },\n  CAR.FIT: {\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-T5R-L220\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-T5R-C020\\x00\\x00',\n      b'39990-T5R-C030\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-T5A-J010\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-T5A-A410\\x00\\x00',\n      b'78109-T5A-A420\\x00\\x00',\n      b'78109-T5A-A910\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36161-T5R-A240\\x00\\x00',\n      b'36161-T5R-A520\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-T5R-A230\\x00\\x00',\n    ],\n  },\n  CAR.ODYSSEY: {\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-THR-A010\\x00\\x00',\n      b'38897-THR-A020\\x00\\x00',\n    ],\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-5MR-A240\\x00\\x00',\n      b'37805-5MR-A250\\x00\\x00',\n      b'37805-5MR-A310\\x00\\x00',\n      b'37805-5MR-A740\\x00\\x00',\n      b'37805-5MR-A750\\x00\\x00',\n      b'37805-5MR-A840\\x00\\x00',\n      b'37805-5MR-C620\\x00\\x00',\n      b'37805-5MR-D530\\x00\\x00',\n      b'37805-5MR-K730\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-THR-A020\\x00\\x00',\n      b'39990-THR-A030\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-THR-A010\\x00\\x00',\n      b'77959-THR-A110\\x00\\x00',\n      b'77959-THR-X010\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab0f1, None): [\n      b'36161-THR-A020\\x00\\x00',\n      b'36161-THR-A030\\x00\\x00',\n      b'36161-THR-A110\\x00\\x00',\n      b'36161-THR-A720\\x00\\x00',\n      b'36161-THR-A730\\x00\\x00',\n      b'36161-THR-A810\\x00\\x00',\n      b'36161-THR-A910\\x00\\x00',\n      b'36161-THR-C010\\x00\\x00',\n      b'36161-THR-D110\\x00\\x00',\n      b'36161-THR-K020\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-5NZ-A110\\x00\\x00',\n      b'28101-5NZ-A310\\x00\\x00',\n      b'28101-5NZ-C310\\x00\\x00',\n      b'28102-5MX-A001\\x00\\x00',\n      b'28102-5MX-A600\\x00\\x00',\n      b'28102-5MX-A610\\x00\\x00',\n      b'28102-5MX-A710\\x00\\x00',\n      b'28102-5MX-A900\\x00\\x00',\n      b'28102-5MX-A910\\x00\\x00',\n      b'28102-5MX-C001\\x00\\x00',\n      b'28102-5MX-D001\\x00\\x00',\n      b'28102-5MX-D710\\x00\\x00',\n      b'28102-5MX-K610\\x00\\x00',\n      b'28103-5NZ-A100\\x00\\x00',\n      b'28103-5NZ-A300\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-THR-A040\\x00\\x00',\n      b'57114-THR-A110\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-THR-A220\\x00\\x00',\n      b'78109-THR-A230\\x00\\x00',\n      b'78109-THR-A420\\x00\\x00',\n      b'78109-THR-A430\\x00\\x00',\n      b'78109-THR-A720\\x00\\x00',\n      b'78109-THR-A820\\x00\\x00',\n      b'78109-THR-A830\\x00\\x00',\n      b'78109-THR-AB20\\x00\\x00',\n      b'78109-THR-AB30\\x00\\x00',\n      b'78109-THR-AB40\\x00\\x00',\n      b'78109-THR-AC20\\x00\\x00',\n      b'78109-THR-AC40\\x00\\x00',\n      b'78109-THR-AC50\\x00\\x00',\n      b'78109-THR-AE20\\x00\\x00',\n      b'78109-THR-AE40\\x00\\x00',\n      b'78109-THR-AK10\\x00\\x00',\n      b'78109-THR-AL10\\x00\\x00',\n      b'78109-THR-AN10\\x00\\x00',\n      b'78109-THR-C330\\x00\\x00',\n      b'78109-THR-CE20\\x00\\x00',\n      b'78109-THR-DA20\\x00\\x00',\n      b'78109-THR-DA40\\x00\\x00',\n      b'78109-THR-K120\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-THR-A020\\x00\\x00',\n    ],\n  },\n  CAR.PILOT: {\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TG7-A520\\x00\\x00',\n      b'54008-TG7-A530\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28101-5EY-A050\\x00\\x00',\n      b'28101-5EY-A100\\x00\\x00',\n      b'28101-5EZ-A050\\x00\\x00',\n      b'28101-5EZ-A060\\x00\\x00',\n      b'28101-5EZ-A100\\x00\\x00',\n      b'28101-5EZ-A210\\x00\\x00',\n    ],\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-RLV-4060\\x00\\x00',\n      b'37805-RLV-4070\\x00\\x00',\n      b'37805-RLV-A830\\x00\\x00',\n      b'37805-RLV-A840\\x00\\x00',\n      b'37805-RLV-C430\\x00\\x00',\n      b'37805-RLV-C510\\x00\\x00',\n      b'37805-RLV-C520\\x00\\x00',\n      b'37805-RLV-C530\\x00\\x00',\n      b'37805-RLV-C910\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TG7-A030\\x00\\x00',\n      b'39990-TG7-A040\\x00\\x00',\n      b'39990-TG7-A060\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab0f1, None): [\n      b'36161-TG7-A520\\x00\\x00',\n      b'36161-TG7-A720\\x00\\x00',\n      b'36161-TG7-A820\\x00\\x00',\n      b'36161-TG7-C520\\x00\\x00',\n      b'36161-TG7-D520\\x00\\x00',\n      b'36161-TG8-A520\\x00\\x00',\n      b'36161-TG8-A720\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TG7-A110\\x00\\x00',\n      b'77959-TG7-A020\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TG7-A040\\x00\\x00',\n      b'78109-TG7-A050\\x00\\x00',\n      b'78109-TG7-A420\\x00\\x00',\n      b'78109-TG7-A520\\x00\\x00',\n      b'78109-TG7-A720\\x00\\x00',\n      b'78109-TG7-D020\\x00\\x00',\n      b'78109-TG8-A420\\x00\\x00',\n      b'78109-TG8-A520\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TG7-A130\\x00\\x00',\n      b'57114-TG7-A140\\x00\\x00',\n      b'57114-TG7-A230\\x00\\x00',\n      b'57114-TG7-A240\\x00\\x00',\n      b'57114-TG8-A140\\x00\\x00',\n      b'57114-TG8-A240\\x00\\x00',\n    ],\n\n  },\n  CAR.PILOT_2019: {\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TG7-A060\\x00\\x00',\n      b'39990-TG7-A070\\x00\\x00',\n      b'39990-TGS-A230\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TG7-A030\\x00\\x00',\n      b'38897-TG7-A040\\x00\\x00',\n      b'38897-TG7-A110\\x00\\x00',\n      b'38897-TG7-A210\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab0f1, None): [\n      b'36161-TG7-A310\\x00\\x00',\n      b'36161-TG7-A630\\x00\\x00',\n      b'36161-TG7-A930\\x00\\x00',\n      b'36161-TG7-D630\\x00\\x00',\n      b'36161-TG7-Y630\\x00\\x00',\n      b'36161-TG8-A630\\x00\\x00',\n      b'36161-TG8-A830\\x00\\x00',\n      b'36161-TGS-A130\\x00\\x00',\n      b'36161-TGT-A030\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TG7-A210\\x00\\x00',\n      b'77959-TG7-Y210\\x00\\x00',\n      b'77959-TGS-A010\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TG7-AJ10\\x00\\x00',\n      b'78109-TG7-AJ20\\x00\\x00',\n      b'78109-TG7-AK10\\x00\\x00',\n      b'78109-TG7-AK20\\x00\\x00',\n      b'78109-TG7-AM20\\x00\\x00',\n      b'78109-TG7-AP10\\x00\\x00',\n      b'78109-TG7-AP20\\x00\\x00',\n      b'78109-TG7-AS20\\x00\\x00',\n      b'78109-TG7-AU20\\x00\\x00',\n      b'78109-TG7-DJ10\\x00\\x00',\n      b'78109-TG7-YK20\\x00\\x00',\n      b'78109-TG8-AJ10\\x00\\x00',\n      b'78109-TG8-AJ20\\x00\\x00',\n      b'78109-TG8-AK20\\x00\\x00',\n      b'78109-TGS-AK20\\x00\\x00',\n      b'78109-TGS-AP20\\x00\\x00',\n      b'78109-TGT-AJ20\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TG7-A630\\x00\\x00',\n      b'57114-TG7-A730\\x00\\x00',\n      b'57114-TG8-A630\\x00\\x00',\n      b'57114-TG8-A730\\x00\\x00',\n      b'57114-TGS-A530\\x00\\x00',\n      b'57114-TGT-A530\\x00\\x00',\n    ],\n  },\n  CAR.ACURA_RDX: {\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TX5-A220\\x00\\x00',\n      b'57114-TX4-A220\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab0f1, None): [\n      b'36161-TX5-A030\\x00\\x00',\n      b'36161-TX4-A030\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TX4-C010\\x00\\x00',\n      b'77959-TX4-B010\\x00\\x00',\n      b'77959-TX4-C020\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TX5-A310\\x00\\x00',\n      b'78109-TX4-A210\\x00\\x00',\n      b'78109-TX4-A310\\x00\\x00',\n    ],\n  },\n  CAR.ACURA_RDX_3G: {\n    (Ecu.programmedFuelInjection, 0x18da10f1, None): [\n      b'37805-5YF-A230\\x00\\x00',\n      b'37805-5YF-A320\\x00\\x00',\n      b'37805-5YF-A330\\x00\\x00',\n      b'37805-5YF-A420\\x00\\x00',\n      b'37805-5YF-A430\\x00\\x00',\n      b'37805-5YF-A870\\x00\\x00',\n      b'37805-5YF-C210\\x00\\x00',\n      b'37805-5YF-C410\\000\\000',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TJB-A040\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TJB-A040\\x00\\x00',\n      b'36802-TJB-A050\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TJB-A040\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TJB-A520\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x18da1ef1, None): [\n      b'28102-5YK-A630\\x00\\x00',\n      b'28102-5YK-A700\\x00\\x00',\n      b'28102-5YK-A711\\x00\\x00',\n      b'28102-5YL-A700\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TJB-A240\\x00\\x00',\n      b'78109-TJB-AB10\\x00\\x00',\n      b'78109-TJB-AD10\\x00\\x00',\n      b'78109-TJB-AF10\\x00\\x00',\n      b'78109-TJB-AW10\\x00\\x00',\n      b'78109-TJC-AA10\\x00\\x00',\n      b'78109-TJC-AD10\\x00\\x00',\n      b'78109-TJB-AS10\\000\\000',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TJB-A040\\x00\\x00',\n      b'77959-TJB-A210\\x00\\x00',\n    ],\n    (Ecu.electricBrakeBooster, 0x18da2bf1, None): [\n      b'46114-TJB-A050\\x00\\x00',\n      b'46114-TJB-A060\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TJB-A040\\x00\\x00',\n      b'38897-TJB-A110\\x00\\x00',\n      b'38897-TJB-A120\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TJB-A030\\x00\\x00',\n      b'39990-TJB-A040\\x00\\x00',\n      b'39990-TJB-A130\\x00\\x00'\n    ],\n  },\n  CAR.RIDGELINE: {\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-T6Z-A020\\x00\\x00',\n      b'39990-T6Z-A030\\x00\\x00',\n      b'39990-T6Z-A050\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab0f1, None): [\n      b'36161-T6Z-A020\\x00\\x00',\n      b'36161-T6Z-A310\\x00\\x00',\n      b'36161-T6Z-A420\\x00\\x00',\n      b'36161-T6Z-A520\\x00\\x00',\n      b'36161-T6Z-A620\\x00\\x00',\n      b'36161-TJZ-A120\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-T6Z-A010\\x00\\x00',\n      b'38897-T6Z-A110\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-T6Z-A420\\x00\\x00',\n      b'78109-T6Z-A510\\x00\\x00',\n      b'78109-T6Z-A710\\x00\\x00',\n      b'78109-T6Z-A910\\x00\\x00',\n      b'78109-T6Z-AA10\\x00\\x00',\n      b'78109-T6Z-C620\\x00\\x00',\n      b'78109-TJZ-A510\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-T6Z-A020\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-T6Z-A120\\x00\\x00',\n      b'57114-T6Z-A130\\x00\\x00',\n      b'57114-T6Z-A520\\x00\\x00',\n      b'57114-TJZ-A520\\x00\\x00',\n    ],\n  },\n  CAR.INSIGHT: {\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-TXM-A040\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36802-TXM-A070\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x18dab5f1, None): [\n      b'36161-TXM-A050\\x00\\x00',\n      b'36161-TXM-A060\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TXM-A230\\x00\\x00',\n    ],\n    (Ecu.vsa, 0x18da28f1, None): [\n      b'57114-TXM-A030\\x00\\x00',\n      b'57114-TXM-A040\\x00\\x00',\n    ],\n    (Ecu.shiftByWire, 0x18da0bf1, None): [\n      b'54008-TWA-A910\\x00\\x00',\n    ],\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TXM-A020\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-TXM-A010\\x00\\x00',\n      b'78109-TXM-A020\\x00\\x00',\n      b'78109-TXM-A110\\x00\\x00',\n      b'78109-TXM-C010\\x00\\x00',\n      b'78109-TXM-A030\\x00\\x00',\n    ],\n  },\n  CAR.HRV: {\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-T7A-A010\\x00\\x00',\n      b'38897-T7A-A110\\x00\\x00',\n    ],\n    (Ecu.eps, 0x18da30f1, None): [\n      b'39990-THX-A020\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36161-T7A-A140\\x00\\x00',\n      b'36161-T7A-A240\\x00\\x00',\n      b'36161-T7A-C440\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-T7A-A230\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-THX-A110\\x00\\x00',\n      b'78109-THX-A210\\x00\\x00',\n      b'78109-THX-A220\\x00\\x00',\n      b'78109-THX-C220\\x00\\x00',\n    ],\n  },\n  CAR.ACURA_ILX: {\n    (Ecu.gateway, 0x18daeff1, None): [\n      b'38897-TX6-A010\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x18dab0f1, None): [\n      b'36161-TV9-A140\\x00\\x00',\n      b'36161-TX6-A030\\x00\\x00',\n    ],\n    (Ecu.srs, 0x18da53f1, None): [\n      b'77959-TX6-A230\\x00\\x00',\n      b'77959-TX6-C210\\x00\\x00',\n    ],\n    (Ecu.combinationMeter, 0x18da60f1, None): [\n      b'78109-T3R-A120\\x00\\x00',\n      b'78109-T3R-A410\\x00\\x00',\n      b'78109-TV9-A510\\x00\\x00',\n    ],\n  },\n  CAR.HONDA_E:{\n    (Ecu.eps, 0x18DA30F1, None):[\n      b'39990-TYF-N030\\x00\\x00'\n    ],\n    (Ecu.gateway, 0x18DAEFF1, None):[\n      b'38897-TYF-E140\\x00\\x00'\n    ],\n    (Ecu.shiftByWire, 0x18DA0BF1, None):[\n      b'54008-TYF-E010\\x00\\x00'\n    ],\n    (Ecu.srs, 0x18DA53F1, None):[\n      b'77959-TYF-G430\\x00\\x00'\n    ],\n    (Ecu.combinationMeter, 0x18DA60F1, None):[\n      b'78108-TYF-G610\\x00\\x00'\n    ],\n    (Ecu.fwdRadar, 0x18DAB0F1, None):[\n      b'36802-TYF-E030\\x00\\x00'\n    ],\n    (Ecu.fwdCamera, 0x18DAB5F1, None):[\n      b'36161-TYF-E020\\x00\\x00'\n    ],\n    (Ecu.vsa, 0x18DA28F1, None):[\n      b'57114-TYF-E030\\x00\\x00'\n    ],\n  },\n}\n\nDBC = {\n  CAR.ACCORD: dbc_dict('honda_accord_2018_can_generated', None),\n  CAR.ACCORDH: dbc_dict('honda_accord_2018_can_generated', None),\n  CAR.ACURA_ILX: dbc_dict('acura_ilx_2016_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.ACURA_RDX: dbc_dict('acura_rdx_2018_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.ACURA_RDX_3G: dbc_dict('acura_rdx_2020_can_generated', None),\n  CAR.CIVIC: dbc_dict('honda_civic_touring_2016_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.CIVIC_BOSCH: dbc_dict('honda_civic_hatchback_ex_2017_can_generated', None),\n  CAR.CIVIC_BOSCH_DIESEL: dbc_dict('honda_civic_sedan_16_diesel_2019_can_generated', None),\n  CAR.CRV: dbc_dict('honda_crv_touring_2016_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.CRV_5G: dbc_dict('honda_crv_ex_2017_can_generated', None, body_dbc='honda_crv_ex_2017_body_generated'),\n  CAR.CRV_EU: dbc_dict('honda_crv_executive_2016_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.CRV_HYBRID: dbc_dict('honda_crv_hybrid_2019_can_generated', None, body_dbc='honda_crv_ex_2017_body_generated'),\n  CAR.FIT: dbc_dict('honda_fit_ex_2018_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.HRV: dbc_dict('honda_fit_ex_2018_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.ODYSSEY: dbc_dict('honda_odyssey_exl_2018_generated', 'acura_ilx_2016_nidec'),\n  CAR.ODYSSEY_CHN: dbc_dict('honda_odyssey_extreme_edition_2018_china_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.PILOT: dbc_dict('honda_pilot_touring_2017_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.PILOT_2019: dbc_dict('honda_pilot_touring_2017_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.RIDGELINE: dbc_dict('honda_ridgeline_black_edition_2017_can_generated', 'acura_ilx_2016_nidec'),\n  CAR.INSIGHT: dbc_dict('honda_insight_ex_2019_can_generated', None),\n  CAR.HONDA_E: dbc_dict('acura_rdx_2020_can_generated', None),\n  CAR.JADE: dbc_dict('honda_fit_ex_2018_can_generated', 'acura_ilx_2016_nidec'),\n}\n\nSTEER_THRESHOLD = {\n  # default is 1200, overrides go here\n  CAR.ACURA_RDX: 400,\n  CAR.CRV_EU: 400,\n}\n\n# TODO: is this real?\nSPEED_FACTOR = {\n  # default is 1, overrides go here\n  CAR.CRV: 1.025,\n  CAR.CRV_5G: 1.025,\n  CAR.CRV_EU: 1.025,\n  CAR.CRV_HYBRID: 1.025,\n  CAR.HRV: 1.025,\n  CAR.JADE: 1.05,\n}\n\nHONDA_NIDEC_ALT_PCM_ACCEL = set([CAR.ODYSSEY])\nHONDA_BOSCH = set([CAR.ACCORD, CAR.ACCORDH, CAR.CIVIC_BOSCH, CAR.CIVIC_BOSCH_DIESEL, CAR.CRV_5G, CAR.CRV_HYBRID, CAR.INSIGHT, CAR.ACURA_RDX_3G, CAR.HONDA_E])\nHONDA_BOSCH_ALT_BRAKE_SIGNAL = set([CAR.ACCORD, CAR.CRV_5G, CAR.ACURA_RDX_3G])\n"
  },
  {
    "path": "selfdrive/car/hyundai/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/hyundai/carcontroller.py",
    "content": "from cereal import car\nfrom common.realtime import DT_CTRL\nfrom selfdrive.car import apply_std_steer_torque_limits\nfrom selfdrive.car.hyundai.hyundaican import create_lkas11, create_clu11, create_lfahda_mfc\nfrom selfdrive.car.hyundai.values import Buttons, CarControllerParams, CAR\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\nfrom common.params import Params\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\n\ndef process_hud_alert(enabled, fingerprint, visual_alert, left_lane,\n                      right_lane, left_lane_depart, right_lane_depart):\n  sys_warning = (visual_alert in [VisualAlert.steerRequired, VisualAlert.ldw])\n\n  # initialize to no line visible\n  sys_state = 1\n  if left_lane and right_lane or sys_warning:  # HUD alert only display when LKAS status is active\n    sys_state = 3 if enabled or sys_warning else 4\n  elif left_lane:\n    sys_state = 5\n  elif right_lane:\n    sys_state = 6\n\n  # initialize to no warnings\n  left_lane_warning = 0\n  right_lane_warning = 0\n  if left_lane_depart:\n    left_lane_warning = 1 if fingerprint in [CAR.GENESIS_G90, CAR.GENESIS_G80] else 2\n  if right_lane_depart:\n    right_lane_warning = 1 if fingerprint in [CAR.GENESIS_G90, CAR.GENESIS_G80] else 2\n\n  return sys_warning, sys_state, left_lane_warning, right_lane_warning\n\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n    self.dp_hkg_smart_mdps = Params().get('dp_hkg_smart_mdps') == b'1'\n\n    self.p = CarControllerParams(CP)\n    self.packer = CANPacker(dbc_name)\n\n    self.apply_steer_last = 0\n    self.car_fingerprint = CP.carFingerprint\n    self.steer_rate_limited = False\n    self.last_resume_frame = 0\n\n  def update(self, enabled, CS, frame, actuators, pcm_cancel_cmd, visual_alert,\n             left_lane, right_lane, left_lane_depart, right_lane_depart, dragonconf):\n    # Steering Torque\n    new_steer = int(round(actuators.steer * self.p.STEER_MAX))\n    apply_steer = apply_std_steer_torque_limits(new_steer, self.apply_steer_last, CS.out.steeringTorque, self.p)\n    self.steer_rate_limited = new_steer != apply_steer\n\n    # disable when temp fault is active, or below LKA minimum speed\n    lkas_active = enabled and not CS.out.steerWarning and CS.out.vEgo >= CS.CP.minSteerSpeed\n\n    # fix for Genesis hard fault at low speed\n    if not self.dp_hkg_smart_mdps and CS.out.vEgo < 16.7 and self.car_fingerprint == CAR.HYUNDAI_GENESIS:\n      lkas_active = False\n\n    if not lkas_active:\n      apply_steer = 0\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_steer = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_steer, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    self.apply_steer_last = apply_steer\n\n    sys_warning, sys_state, left_lane_warning, right_lane_warning = \\\n      process_hud_alert(enabled, self.car_fingerprint, visual_alert,\n                        left_lane, right_lane, left_lane_depart, right_lane_depart)\n\n    can_sends = []\n    can_sends.append(create_lkas11(self.packer, frame, self.car_fingerprint, apply_steer, lkas_active,\n                                   CS.lkas11, sys_warning, sys_state, enabled,\n                                   left_lane, right_lane,\n                                   left_lane_warning, right_lane_warning))\n\n    if pcm_cancel_cmd:\n      can_sends.append(create_clu11(self.packer, frame, CS.clu11, Buttons.CANCEL))\n    elif CS.out.cruiseState.standstill:\n      # send resume at a max freq of 10Hz\n      if (frame - self.last_resume_frame) * DT_CTRL > 0.1:\n        # send 25 messages at a time to increases the likelihood of resume being accepted\n        can_sends.extend([create_clu11(self.packer, frame, CS.clu11, Buttons.RES_ACCEL)] * 25)\n        self.last_resume_frame = frame\n\n    # 20 Hz LFA MFA message\n    if frame % 5 == 0 and self.car_fingerprint in [CAR.SONATA, CAR.PALISADE, CAR.IONIQ, CAR.KIA_NIRO_EV, CAR.KIA_NIRO_HEV_2021,\n                                                   CAR.IONIQ_EV_2020, CAR.IONIQ_PHEV, CAR.KIA_CEED, CAR.KIA_SELTOS, CAR.KONA_EV,\n                                                   CAR.ELANTRA_2021, CAR.ELANTRA_HEV_2021, CAR.SONATA_HYBRID, CAR.KONA_HEV]:\n      can_sends.append(create_lfahda_mfc(self.packer, enabled))\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/hyundai/carstate.py",
    "content": "import copy\nfrom cereal import car\nfrom selfdrive.car.hyundai.values import DBC, STEER_THRESHOLD, FEATURES, EV_CAR, HYBRID_CAR\nfrom selfdrive.car.interfaces import CarStateBase\nfrom opendbc.can.parser import CANParser\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.config import Conversions as CV\n\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n\n    if self.CP.carFingerprint in FEATURES[\"use_cluster_gears\"]:\n      self.shifter_values = can_define.dv[\"CLU15\"][\"CF_Clu_Gear\"]\n    elif self.CP.carFingerprint in FEATURES[\"use_tcu_gears\"]:\n      self.shifter_values = can_define.dv[\"TCU12\"][\"CUR_GR\"]\n    else:  # preferred and elect gear methods use same definition\n      self.shifter_values = can_define.dv[\"LVR12\"][\"CF_Lvr_Gear\"]\n\n\n  def update(self, cp, cp_cam):\n    ret = car.CarState.new_message()\n\n    ret.doorOpen = any([cp.vl[\"CGW1\"][\"CF_Gway_DrvDrSw\"], cp.vl[\"CGW1\"][\"CF_Gway_AstDrSw\"],\n                        cp.vl[\"CGW2\"][\"CF_Gway_RLDrSw\"], cp.vl[\"CGW2\"][\"CF_Gway_RRDrSw\"]])\n\n    ret.seatbeltUnlatched = cp.vl[\"CGW1\"][\"CF_Gway_DrvSeatBeltSw\"] == 0\n\n    ret.wheelSpeeds.fl = cp.vl[\"WHL_SPD11\"][\"WHL_SPD_FL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = cp.vl[\"WHL_SPD11\"][\"WHL_SPD_FR\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = cp.vl[\"WHL_SPD11\"][\"WHL_SPD_RL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = cp.vl[\"WHL_SPD11\"][\"WHL_SPD_RR\"] * CV.KPH_TO_MS\n    ret.vEgoRaw = (ret.wheelSpeeds.fl + ret.wheelSpeeds.fr + ret.wheelSpeeds.rl + ret.wheelSpeeds.rr) / 4.\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n\n    ret.standstill = ret.vEgoRaw < 0.1\n\n    ret.steeringAngleDeg = cp.vl[\"SAS11\"][\"SAS_Angle\"]\n    ret.steeringRateDeg = cp.vl[\"SAS11\"][\"SAS_Speed\"]\n    ret.yawRate = cp.vl[\"ESP12\"][\"YAW_RATE\"]\n    ret.leftBlinker, ret.rightBlinker = self.update_blinker_from_lamp(\n      50, cp.vl[\"CGW1\"][\"CF_Gway_TurnSigLh\"], cp.vl[\"CGW1\"][\"CF_Gway_TurnSigRh\"])\n    ret.steeringTorque = cp.vl[\"MDPS12\"][\"CR_Mdps_StrColTq\"]\n    ret.steeringTorqueEps = cp.vl[\"MDPS12\"][\"CR_Mdps_OutTq\"]\n    #dp\n    ret.engineRPM = cp.vl[\"TCU_DCT13\"]['Cluster_Engine_RPM']\n    ret.steeringPressed = abs(ret.steeringTorque) > STEER_THRESHOLD\n    ret.steerWarning = cp.vl[\"MDPS12\"][\"CF_Mdps_ToiUnavail\"] != 0 or cp.vl[\"MDPS12\"][\"CF_Mdps_ToiFlt\"] != 0\n\n    # cruise state\n    if self.CP.openpilotLongitudinalControl:\n      ret.cruiseState.available = cp.vl[\"TCS13\"][\"ACCEnable\"] == 0\n      ret.cruiseState.enabled = cp.vl[\"TCS13\"][\"ACC_REQ\"] == 1\n      ret.cruiseState.standstill = False\n    else:\n      ret.cruiseState.available = cp.vl[\"SCC11\"][\"MainMode_ACC\"] == 1\n      ret.cruiseState.enabled = cp.vl[\"SCC12\"][\"ACCMode\"] != 0\n      ret.cruiseState.standstill = cp.vl[\"SCC11\"][\"SCCInfoDisplay\"] == 4.\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n\n    if ret.cruiseState.enabled:\n      speed_conv = CV.MPH_TO_MS if cp.vl[\"CLU11\"][\"CF_Clu_SPEED_UNIT\"] else CV.KPH_TO_MS\n      ret.cruiseState.speed = cp.vl[\"SCC11\"][\"VSetDis\"] * speed_conv\n    else:\n      ret.cruiseState.speed = 0\n\n    # TODO: Find brake pressure\n    ret.brake = 0\n    ret.brakePressed = cp.vl[\"TCS13\"][\"DriverBraking\"] != 0\n\n    if self.CP.carFingerprint in (HYBRID_CAR | EV_CAR):\n      if self.CP.carFingerprint in HYBRID_CAR:\n        ret.gas = cp.vl[\"E_EMS11\"][\"CR_Vcu_AccPedDep_Pos\"] / 254.\n      else:\n        ret.gas = cp.vl[\"E_EMS11\"][\"Accel_Pedal_Pos\"] / 254.\n      ret.gasPressed = ret.gas > 0\n    else:\n      ret.gas = cp.vl[\"EMS12\"][\"PV_AV_CAN\"] / 100.\n      ret.gasPressed = bool(cp.vl[\"EMS16\"][\"CF_Ems_AclAct\"])\n\n    # Gear Selection via Cluster - For those Kia/Hyundai which are not fully discovered, we can use the Cluster Indicator for Gear Selection,\n    # as this seems to be standard over all cars, but is not the preferred method.\n    if self.CP.carFingerprint in FEATURES[\"use_cluster_gears\"]:\n      gear = cp.vl[\"CLU15\"][\"CF_Clu_Gear\"]\n    elif self.CP.carFingerprint in FEATURES[\"use_tcu_gears\"]:\n      gear = cp.vl[\"TCU12\"][\"CUR_GR\"]\n    elif self.CP.carFingerprint in FEATURES[\"use_elect_gears\"]:\n      gear = cp.vl[\"ELECT_GEAR\"][\"Elect_Gear_Shifter\"]\n    else:\n      gear = cp.vl[\"LVR12\"][\"CF_Lvr_Gear\"]\n\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(gear))\n\n    if self.CP.carFingerprint in FEATURES[\"use_fca\"]:\n      ret.stockAeb = cp.vl[\"FCA11\"][\"FCA_CmdAct\"] != 0\n      ret.stockFcw = cp.vl[\"FCA11\"][\"CF_VSM_Warn\"] == 2\n    else:\n      ret.stockAeb = cp.vl[\"SCC12\"][\"AEB_CmdAct\"] != 0\n      ret.stockFcw = cp.vl[\"SCC12\"][\"CF_VSM_Warn\"] == 2\n\n    if self.CP.enableBsm:\n      ret.leftBlindspot = cp.vl[\"LCA11\"][\"CF_Lca_IndLeft\"] != 0\n      ret.rightBlindspot = cp.vl[\"LCA11\"][\"CF_Lca_IndRight\"] != 0\n\n    # save the entire LKAS11 and CLU11\n    self.lkas11 = copy.copy(cp_cam.vl[\"LKAS11\"])\n    self.clu11 = copy.copy(cp.vl[\"CLU11\"])\n    self.park_brake = cp.vl[\"TCS13\"][\"PBRAKE_ACT\"] == 1\n    self.steer_state = cp.vl[\"MDPS12\"][\"CF_Mdps_ToiActive\"]  # 0 NOT ACTIVE, 1 ACTIVE\n    self.lead_distance = cp.vl[\"SCC11\"][\"ACC_ObjDist\"]\n    self.brake_hold = cp.vl[\"TCS15\"][\"AVH_LAMP\"] == 2 # 0 OFF, 1 ERROR, 2 ACTIVE, 3 READY\n    self.brake_error = cp.vl[\"TCS13\"][\"ACCEnable\"] != 0 # 0 ACC CONTROL ENABLED, 1-3 ACC CONTROL DISABLED\n    self.prev_cruise_buttons = self.cruise_buttons\n    self.cruise_buttons = cp.vl[\"CLU11\"][\"CF_Clu_CruiseSwState\"]\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    signals = [\n      # sig_name, sig_address, default\n      (\"WHL_SPD_FL\", \"WHL_SPD11\", 0),\n      (\"WHL_SPD_FR\", \"WHL_SPD11\", 0),\n      (\"WHL_SPD_RL\", \"WHL_SPD11\", 0),\n      (\"WHL_SPD_RR\", \"WHL_SPD11\", 0),\n\n      (\"YAW_RATE\", \"ESP12\", 0),\n\n      (\"CF_Gway_DrvSeatBeltInd\", \"CGW4\", 1),\n\n      (\"CF_Gway_DrvSeatBeltSw\", \"CGW1\", 0),\n      (\"CF_Gway_DrvDrSw\", \"CGW1\", 0),       # Driver Door\n      (\"CF_Gway_AstDrSw\", \"CGW1\", 0),       # Passenger door\n      (\"CF_Gway_RLDrSw\", \"CGW2\", 0),        # Rear reft door\n      (\"CF_Gway_RRDrSw\", \"CGW2\", 0),        # Rear right door\n      (\"CF_Gway_TurnSigLh\", \"CGW1\", 0),\n      (\"CF_Gway_TurnSigRh\", \"CGW1\", 0),\n      (\"CF_Gway_ParkBrakeSw\", \"CGW1\", 0),\n\n      (\"CYL_PRES\", \"ESP12\", 0),\n\n      (\"CF_Clu_CruiseSwState\", \"CLU11\", 0),\n      (\"CF_Clu_CruiseSwMain\", \"CLU11\", 0),\n      (\"CF_Clu_SldMainSW\", \"CLU11\", 0),\n      (\"CF_Clu_ParityBit1\", \"CLU11\", 0),\n      (\"CF_Clu_VanzDecimal\" , \"CLU11\", 0),\n      (\"CF_Clu_Vanz\", \"CLU11\", 0),\n      (\"CF_Clu_SPEED_UNIT\", \"CLU11\", 0),\n      (\"CF_Clu_DetentOut\", \"CLU11\", 0),\n      (\"CF_Clu_RheostatLevel\", \"CLU11\", 0),\n      (\"CF_Clu_CluInfo\", \"CLU11\", 0),\n      (\"CF_Clu_AmpInfo\", \"CLU11\", 0),\n      (\"CF_Clu_AliveCnt1\", \"CLU11\", 0),\n\n      (\"ACCEnable\", \"TCS13\", 0),\n      (\"ACC_REQ\", \"TCS13\", 0),\n      (\"DriverBraking\", \"TCS13\", 0),\n      (\"StandStill\", \"TCS13\", 0),\n      (\"PBRAKE_ACT\", \"TCS13\", 0),\n\n      (\"ESC_Off_Step\", \"TCS15\", 0),\n      (\"AVH_LAMP\", \"TCS15\", 0),\n\n      (\"CR_Mdps_StrColTq\", \"MDPS12\", 0),\n      (\"CF_Mdps_ToiActive\", \"MDPS12\", 0),\n      (\"CF_Mdps_ToiUnavail\", \"MDPS12\", 0),\n      (\"CF_Mdps_ToiFlt\", \"MDPS12\", 0),\n      (\"CR_Mdps_OutTq\", \"MDPS12\", 0),\n\n      (\"SAS_Angle\", \"SAS11\", 0),\n      (\"SAS_Speed\", \"SAS11\", 0),\n\n      (\"MainMode_ACC\", \"SCC11\", 0),\n      (\"VSetDis\", \"SCC11\", 0),\n      (\"SCCInfoDisplay\", \"SCC11\", 0),\n      (\"ACC_ObjDist\", \"SCC11\", 0),\n      (\"ACCMode\", \"SCC12\", 1),\n      #dp\n      (\"Cluster_Engine_RPM\", \"TCU_DCT13\", 0),\n    ]\n\n    checks = [\n      # address, frequency\n      (\"MDPS12\", 50),\n      (\"TCS13\", 50),\n      (\"TCS15\", 10),\n      (\"CLU11\", 50),\n      (\"ESP12\", 100),\n      (\"CGW1\", 10),\n      (\"CGW2\", 5),\n      (\"CGW4\", 5),\n      (\"WHL_SPD11\", 50),\n      (\"SAS11\", 100),\n      (\"TCU_DCT13\", 100),\n    ]\n\n    if not CP.openpilotLongitudinalControl:\n      checks += [\n        (\"SCC11\", 50),\n        (\"SCC12\", 50),\n      ]\n\n    if CP.enableBsm:\n      signals += [\n        (\"CF_Lca_IndLeft\", \"LCA11\", 0),\n        (\"CF_Lca_IndRight\", \"LCA11\", 0),\n      ]\n      checks += [(\"LCA11\", 50)]\n\n    if CP.carFingerprint in (HYBRID_CAR | EV_CAR):\n      if CP.carFingerprint in HYBRID_CAR:\n        signals += [\n          (\"CR_Vcu_AccPedDep_Pos\", \"E_EMS11\", 0)\n        ]\n      else:\n        signals += [\n          (\"Accel_Pedal_Pos\", \"E_EMS11\", 0)\n        ]\n      checks += [\n        (\"E_EMS11\", 50),\n      ]\n    else:\n      signals += [\n        (\"PV_AV_CAN\", \"EMS12\", 0),\n        (\"CF_Ems_AclAct\", \"EMS16\", 0),\n      ]\n      checks += [\n        (\"EMS12\", 100),\n        (\"EMS16\", 100),\n      ]\n\n    if CP.carFingerprint in FEATURES[\"use_cluster_gears\"]:\n      signals += [\n        (\"CF_Clu_Gear\", \"CLU15\", 0),\n      ]\n      checks += [\n        (\"CLU15\", 5)\n      ]\n    elif CP.carFingerprint in FEATURES[\"use_tcu_gears\"]:\n      signals += [\n        (\"CUR_GR\", \"TCU12\", 0)\n      ]\n      checks += [\n        (\"TCU12\", 100)\n      ]\n    elif CP.carFingerprint in FEATURES[\"use_elect_gears\"]:\n      signals += [(\"Elect_Gear_Shifter\", \"ELECT_GEAR\", 0)]\n      checks += [(\"ELECT_GEAR\", 20)]\n    else:\n      signals += [\n        (\"CF_Lvr_Gear\", \"LVR12\", 0)\n      ]\n      checks += [\n        (\"LVR12\", 100)\n      ]\n\n    if CP.carFingerprint in FEATURES[\"use_fca\"]:\n      signals += [\n        (\"FCA_CmdAct\", \"FCA11\", 0),\n        (\"CF_VSM_Warn\", \"FCA11\", 0),\n      ]\n      if not CP.openpilotLongitudinalControl:\n        checks += [(\"FCA11\", 50)]\n    else:\n      signals += [\n        (\"AEB_CmdAct\", \"SCC12\", 0),\n        (\"CF_VSM_Warn\", \"SCC12\", 0),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n\n    signals = [\n      # sig_name, sig_address, default\n      (\"CF_Lkas_LdwsActivemode\", \"LKAS11\", 0),\n      (\"CF_Lkas_LdwsSysState\", \"LKAS11\", 0),\n      (\"CF_Lkas_SysWarning\", \"LKAS11\", 0),\n      (\"CF_Lkas_LdwsLHWarning\", \"LKAS11\", 0),\n      (\"CF_Lkas_LdwsRHWarning\", \"LKAS11\", 0),\n      (\"CF_Lkas_HbaLamp\", \"LKAS11\", 0),\n      (\"CF_Lkas_FcwBasReq\", \"LKAS11\", 0),\n      (\"CF_Lkas_HbaSysState\", \"LKAS11\", 0),\n      (\"CF_Lkas_FcwOpt\", \"LKAS11\", 0),\n      (\"CF_Lkas_HbaOpt\", \"LKAS11\", 0),\n      (\"CF_Lkas_FcwSysState\", \"LKAS11\", 0),\n      (\"CF_Lkas_FcwCollisionWarning\", \"LKAS11\", 0),\n      (\"CF_Lkas_FusionState\", \"LKAS11\", 0),\n      (\"CF_Lkas_FcwOpt_USM\", \"LKAS11\", 0),\n      (\"CF_Lkas_LdwsOpt_USM\", \"LKAS11\", 0),\n    ]\n\n    checks = [\n      (\"LKAS11\", 100)\n    ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n"
  },
  {
    "path": "selfdrive/car/hyundai/hyundaican.py",
    "content": "import crcmod\nfrom selfdrive.car.hyundai.values import CAR, CHECKSUM\n\nhyundai_checksum = crcmod.mkCrcFun(0x11D, initCrc=0xFD, rev=False, xorOut=0xdf)\n\n\ndef create_lkas11(packer, frame, car_fingerprint, apply_steer, steer_req,\n                  lkas11, sys_warning, sys_state, enabled,\n                  left_lane, right_lane,\n                  left_lane_depart, right_lane_depart):\n  values = lkas11\n  values[\"CF_Lkas_LdwsSysState\"] = sys_state\n  values[\"CF_Lkas_SysWarning\"] = 3 if sys_warning else 0\n  values[\"CF_Lkas_LdwsLHWarning\"] = left_lane_depart\n  values[\"CF_Lkas_LdwsRHWarning\"] = right_lane_depart\n  values[\"CR_Lkas_StrToqReq\"] = apply_steer\n  values[\"CF_Lkas_ActToi\"] = steer_req\n  values[\"CF_Lkas_MsgCount\"] = frame % 0x10\n\n  if car_fingerprint in [CAR.SONATA, CAR.PALISADE, CAR.KIA_NIRO_EV, CAR.KIA_NIRO_HEV_2021, CAR.SANTA_FE,\n                         CAR.IONIQ_EV_2020, CAR.IONIQ_PHEV, CAR.KIA_SELTOS, CAR.ELANTRA_2021,\n                         CAR.ELANTRA_HEV_2021, CAR.SONATA_HYBRID, CAR.KONA_EV, CAR.KONA_HEV]:\n    values[\"CF_Lkas_LdwsActivemode\"] = int(left_lane) + (int(right_lane) << 1)\n    values[\"CF_Lkas_LdwsOpt_USM\"] = 2\n\n    # FcwOpt_USM 5 = Orange blinking car + lanes\n    # FcwOpt_USM 4 = Orange car + lanes\n    # FcwOpt_USM 3 = Green blinking car + lanes\n    # FcwOpt_USM 2 = Green car + lanes\n    # FcwOpt_USM 1 = White car + lanes\n    # FcwOpt_USM 0 = No car + lanes\n    values[\"CF_Lkas_FcwOpt_USM\"] = 2 if enabled else 1\n\n    # SysWarning 4 = keep hands on wheel\n    # SysWarning 5 = keep hands on wheel (red)\n    # SysWarning 6 = keep hands on wheel (red) + beep\n    # Note: the warning is hidden while the blinkers are on\n    values[\"CF_Lkas_SysWarning\"] = 4 if sys_warning else 0\n\n  elif car_fingerprint == CAR.HYUNDAI_GENESIS:\n    # This field is actually LdwsActivemode\n    # Genesis and Optima fault when forwarding while engaged\n    values[\"CF_Lkas_LdwsActivemode\"] = 2\n  elif car_fingerprint == CAR.KIA_OPTIMA:\n    values[\"CF_Lkas_LdwsActivemode\"] = 0\n\n  dat = packer.make_can_msg(\"LKAS11\", 0, values)[2]\n\n  if car_fingerprint in CHECKSUM[\"crc8\"]:\n    # CRC Checksum as seen on 2019 Hyundai Santa Fe\n    dat = dat[:6] + dat[7:8]\n    checksum = hyundai_checksum(dat)\n  elif car_fingerprint in CHECKSUM[\"6B\"]:\n    # Checksum of first 6 Bytes, as seen on 2018 Kia Sorento\n    checksum = sum(dat[:6]) % 256\n  else:\n    # Checksum of first 6 Bytes and last Byte as seen on 2018 Kia Stinger\n    checksum = (sum(dat[:6]) + dat[7]) % 256\n\n  values[\"CF_Lkas_Chksum\"] = checksum\n\n  return packer.make_can_msg(\"LKAS11\", 0, values)\n\n\ndef create_clu11(packer, frame, clu11, button):\n  values = clu11\n  values[\"CF_Clu_CruiseSwState\"] = button\n  values[\"CF_Clu_AliveCnt1\"] = frame % 0x10\n  return packer.make_can_msg(\"CLU11\", 0, values)\n\n\ndef create_lfahda_mfc(packer, enabled, hda_set_speed=0):\n  values = {\n    \"LFA_Icon_State\": 2 if enabled else 0,\n    \"HDA_Active\": 1 if hda_set_speed else 0,\n    \"HDA_Icon_State\": 2 if hda_set_speed else 0,\n    \"HDA_VSetReq\": hda_set_speed,\n  }\n  return packer.make_can_msg(\"LFAHDA_MFC\", 0, values)\n\ndef create_acc_commands(packer, enabled, accel, idx, lead_visible, set_speed, stopping):\n  commands = []\n\n  scc11_values = {\n    \"MainMode_ACC\": 1,\n    \"TauGapSet\": 4,\n    \"VSetDis\": set_speed if enabled else 0,\n    \"AliveCounterACC\": idx % 0x10,\n  }\n  commands.append(packer.make_can_msg(\"SCC11\", 0, scc11_values))\n\n  scc12_values = {\n    \"ACCMode\": 1 if enabled else 0,\n    \"StopReq\": 1 if stopping else 0,\n    \"aReqRaw\": accel,\n    \"aReqValue\": accel, # stock ramps up at 1.0/s and down at 0.5/s until it reaches aReqRaw\n    \"CR_VSM_Alive\": idx % 0xF,\n  }\n  scc12_dat = packer.make_can_msg(\"SCC12\", 0, scc12_values)[2]\n  scc12_values[\"CR_VSM_ChkSum\"] = 0x10 - sum([sum(divmod(i, 16)) for i in scc12_dat]) % 0x10\n\n  commands.append(packer.make_can_msg(\"SCC12\", 0, scc12_values))\n\n  scc14_values = {\n    \"ComfortBandUpper\": 0.0, # stock usually is 0 but sometimes uses higher values\n    \"ComfortBandLower\": 0.0, # stock usually is 0 but sometimes uses higher values\n    \"JerkUpperLimit\": 1.0 if enabled else 0, # stock usually is 1.0 but sometimes uses higher values\n    \"JerkLowerLimit\": 0.5 if enabled else 0, # stock usually is 0.5 but sometimes uses higher values\n    \"ACCMode\": 1 if enabled else 4, # stock will always be 4 instead of 0 after first disengage\n    \"ObjGap\": 3 if lead_visible else 0, # TODO: 1-5 based on distance to lead vehicle\n  }\n  commands.append(packer.make_can_msg(\"SCC14\", 0, scc14_values))\n\n  fca11_values = {\n    # seems to count 2,1,0,3,2,1,0,3,2,1,0,3,2,1,0,repeat...\n    # (where first value is aligned to Supplemental_Counter == 0)\n    # test: [(idx % 0xF, -((idx % 0xF) + 2) % 4) for idx in range(0x14)]\n    \"CR_FCA_Alive\": ((-((idx % 0xF) + 2) % 4) << 2) + 1,\n    \"Supplemental_Counter\": idx % 0xF,\n  }\n  fca11_dat = packer.make_can_msg(\"FCA11\", 0, fca11_values)[2]\n  fca11_values[\"CR_FCA_ChkSum\"] = 0x10 - sum([sum(divmod(i, 16)) for i in fca11_dat]) % 0x10\n  commands.append(packer.make_can_msg(\"FCA11\", 0, fca11_values))\n\n  return commands\n\ndef create_acc_opt(packer):\n  commands = []\n\n  scc13_values = {\n    \"SCCDrvModeRValue\": 2,\n    \"SCC_Equip\": 1,\n    \"Lead_Veh_Dep_Alert_USM\": 2,\n  }\n  commands.append(packer.make_can_msg(\"SCC13\", 0, scc13_values))\n\n  fca12_values = {\n    # stock values may be needed if openpilot has vision based AEB some day\n    # for now we are not setting these because there is no AEB for vision only\n    # \"FCA_USM\": 3,\n    # \"FCA_DrvSetState\": 2,\n  }\n  commands.append(packer.make_can_msg(\"FCA12\", 0, fca12_values))\n\n  return commands\n\ndef create_frt_radar_opt(packer):\n  frt_radar11_values = {\n    \"CF_FCA_Equip_Front_Radar\": 1,\n  }\n  return packer.make_can_msg(\"FRT_RADAR11\", 0, frt_radar11_values)\n"
  },
  {
    "path": "selfdrive/car/hyundai/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.hyundai.values import CAR, EV_CAR, HYBRID_CAR\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\nfrom common.params import Params\n\nclass CarInterface(CarInterfaceBase):\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=[]):  # pylint: disable=dangerous-default-value\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n\n    ret.carName = \"hyundai\"\n    ret.safetyModel = car.CarParams.SafetyModel.hyundai\n    ret.radarOffCan = True\n    ret.lateralTuning.init('pid')\n\n    # Most Hyundai car ports are community features for now\n    ret.communityFeature = candidate not in [CAR.SONATA, CAR.PALISADE]\n\n    ret.steerActuatorDelay = 0.1  # Default delay\n    ret.steerRateCost = 0.5\n    ret.steerLimitTimer = 0.4\n    tire_stiffness_factor = 1.\n\n    ret.startAccel = 1.0\n\n    if candidate == CAR.SANTA_FE:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 3982. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.766\n      # Values from optimizer\n      ret.steerRatio = 16.55  # 13.8 is spec end-to-end\n      tire_stiffness_factor = 0.82\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[9., 22.], [9., 22.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.2, 0.35], [0.05, 0.09]]\n    elif candidate in [CAR.SONATA, CAR.SONATA_HYBRID]:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 1513. + STD_CARGO_KG\n      ret.wheelbase = 2.84\n      ret.steerRatio = 13.27 * 1.15   # 15% higher at the center seems reasonable\n      tire_stiffness_factor = 0.65\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.SONATA_LF:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 4497. * CV.LB_TO_KG\n      ret.wheelbase = 2.804\n      ret.steerRatio = 13.27 * 1.15   # 15% higher at the center seems reasonable\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.PALISADE:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 1999. + STD_CARGO_KG\n      ret.wheelbase = 2.90\n      ret.steerRatio = 15.6 * 1.15\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.05]]\n    elif candidate in [CAR.ELANTRA, CAR.ELANTRA_GT_I30]:\n      ret.lateralTuning.pid.kf = 0.00006\n      ret.mass = 1275. + STD_CARGO_KG\n      ret.wheelbase = 2.7\n      ret.steerRatio = 15.4            # 14 is Stock | Settled Params Learner values are steerRatio: 15.401566348670535\n      tire_stiffness_factor = 0.385    # stiffnessFactor settled on 1.0081302973865127\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n      ret.minSteerSpeed = 32 * CV.MPH_TO_MS\n    elif candidate == CAR.ELANTRA_2021:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = (2800. * CV.LB_TO_KG) + STD_CARGO_KG\n      ret.wheelbase = 2.72\n      ret.steerRatio = 12.9\n      tire_stiffness_factor = 0.65\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.ELANTRA_HEV_2021:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = (3017. * CV.LB_TO_KG) + STD_CARGO_KG\n      ret.wheelbase = 2.72\n      ret.steerRatio = 12.9\n      tire_stiffness_factor = 0.65\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.HYUNDAI_GENESIS:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 2060. + STD_CARGO_KG\n      ret.wheelbase = 3.01\n      ret.steerRatio = 16.5\n      ret.lateralTuning.init('indi')\n      ret.lateralTuning.indi.innerLoopGainBP = [0.]\n      ret.lateralTuning.indi.innerLoopGainV = [3.5]\n      ret.lateralTuning.indi.outerLoopGainBP = [0.]\n      ret.lateralTuning.indi.outerLoopGainV = [2.0]\n      ret.lateralTuning.indi.timeConstantBP = [0.]\n      ret.lateralTuning.indi.timeConstantV = [1.4]\n      ret.lateralTuning.indi.actuatorEffectivenessBP = [0.]\n      ret.lateralTuning.indi.actuatorEffectivenessV = [2.3]\n      ret.minSteerSpeed = 60 * CV.KPH_TO_MS\n    elif candidate in [CAR.KONA, CAR.KONA_EV, CAR.KONA_HEV]:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = {CAR.KONA_EV: 1685., CAR.KONA_HEV: 1425.}.get(candidate, 1275.) + STD_CARGO_KG\n      ret.wheelbase = 2.7\n      ret.steerRatio = 13.73 * 1.15  # Spec\n      tire_stiffness_factor = 0.385\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate in [CAR.IONIQ, CAR.IONIQ_EV_LTD, CAR.IONIQ_EV_2020, CAR.IONIQ_PHEV]:\n      ret.lateralTuning.pid.kf = 0.00006\n      ret.mass = 1490. + STD_CARGO_KG  # weight per hyundai site https://www.hyundaiusa.com/ioniq-electric/specifications.aspx\n      ret.wheelbase = 2.7\n      ret.steerRatio = 13.73  # Spec\n      tire_stiffness_factor = 0.385\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n      if candidate not in [CAR.IONIQ_EV_2020, CAR.IONIQ_PHEV]:\n        ret.minSteerSpeed = 32 * CV.MPH_TO_MS\n    elif candidate == CAR.VELOSTER:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 3558. * CV.LB_TO_KG\n      ret.wheelbase = 2.80\n      ret.steerRatio = 13.75 * 1.15\n      tire_stiffness_factor = 0.5\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n\n    # Kia\n    elif candidate == CAR.KIA_SORENTO:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 1985. + STD_CARGO_KG\n      ret.wheelbase = 2.78\n      ret.steerRatio = 14.4 * 1.1   # 10% higher at the center seems reasonable\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate in [CAR.KIA_NIRO_EV, CAR.KIA_NIRO_HEV, CAR.KIA_NIRO_HEV_2021]:\n      ret.lateralTuning.pid.kf = 0.00006\n      ret.mass = 1737. + STD_CARGO_KG\n      ret.wheelbase = 2.7\n      ret.steerRatio = 13.9 if CAR.KIA_NIRO_HEV_2021 else 13.73  # Spec\n      tire_stiffness_factor = 0.385\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n      if candidate == CAR.KIA_NIRO_HEV:\n        ret.minSteerSpeed = 32 * CV.MPH_TO_MS\n    elif candidate == CAR.KIA_SELTOS:\n      ret.mass = 1337. + STD_CARGO_KG\n      ret.wheelbase = 2.63\n      ret.steerRatio = 14.56\n      tire_stiffness_factor = 1\n      ret.lateralTuning.init('indi')\n      ret.lateralTuning.indi.innerLoopGainBP = [0.]\n      ret.lateralTuning.indi.innerLoopGainV = [4.]\n      ret.lateralTuning.indi.outerLoopGainBP = [0.]\n      ret.lateralTuning.indi.outerLoopGainV = [3.]\n      ret.lateralTuning.indi.timeConstantBP = [0.]\n      ret.lateralTuning.indi.timeConstantV = [1.4]\n      ret.lateralTuning.indi.actuatorEffectivenessBP = [0.]\n      ret.lateralTuning.indi.actuatorEffectivenessV = [1.8]\n    elif candidate in [CAR.KIA_OPTIMA, CAR.KIA_OPTIMA_H]:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 3558. * CV.LB_TO_KG\n      ret.wheelbase = 2.80\n      ret.steerRatio = 13.75\n      tire_stiffness_factor = 0.5\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.KIA_STINGER:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 1825. + STD_CARGO_KG\n      ret.wheelbase = 2.78\n      ret.steerRatio = 14.4 * 1.15   # 15% higher at the center seems reasonable\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.KIA_FORTE:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 3558. * CV.LB_TO_KG\n      ret.wheelbase = 2.80\n      ret.steerRatio = 13.75\n      tire_stiffness_factor = 0.5\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n    elif candidate == CAR.KIA_CEED:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 1450. + STD_CARGO_KG\n      ret.wheelbase = 2.65\n      ret.steerRatio = 13.75\n      tire_stiffness_factor = 0.5\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.25], [0.05]]\n\n    # Genesis\n    elif candidate == CAR.GENESIS_G70:\n      ret.lateralTuning.init('indi')\n      ret.lateralTuning.indi.innerLoopGainBP = [0.]\n      ret.lateralTuning.indi.innerLoopGainV = [2.5]\n      ret.lateralTuning.indi.outerLoopGainBP = [0.]\n      ret.lateralTuning.indi.outerLoopGainV = [3.5]\n      ret.lateralTuning.indi.timeConstantBP = [0.]\n      ret.lateralTuning.indi.timeConstantV = [1.4]\n      ret.lateralTuning.indi.actuatorEffectivenessBP = [0.]\n      ret.lateralTuning.indi.actuatorEffectivenessV = [1.8]\n      ret.steerActuatorDelay = 0.1\n      ret.mass = 1640.0 + STD_CARGO_KG\n      ret.wheelbase = 2.84\n      ret.steerRatio = 13.56\n    elif candidate == CAR.GENESIS_G80:\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.mass = 2060. + STD_CARGO_KG\n      ret.wheelbase = 3.01\n      ret.steerRatio = 16.5\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.16], [0.01]]\n      ret.lateralTuning.init('indi')\n      ret.lateralTuning.indi.innerLoopGainV = [3.5]\n      ret.lateralTuning.indi.innerLoopGainBP = [0.]\n      ret.lateralTuning.indi.outerLoopGainV = [2.0]\n      ret.lateralTuning.indi.outerLoopGainBP = [0.]\n      ret.lateralTuning.indi.timeConstantV = [1.4]\n      ret.lateralTuning.indi.actuatorEffectivenessV = [2.3]\n      ret.lateralTuning.indi.actuatorEffectivenessBP = [0.]\n      ret.minSteerSpeed = 60 * CV.KPH_TO_MS\n    elif candidate == CAR.GENESIS_G90:\n      ret.mass = 2200\n      ret.wheelbase = 3.15\n      ret.steerRatio = 12.069\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.16], [0.01]]\n\n    # these cars require a special panda safety mode due to missing counters and checksums in the messages\n    if candidate in [CAR.HYUNDAI_GENESIS, CAR.IONIQ_EV_2020, CAR.IONIQ_EV_LTD, CAR.IONIQ_PHEV, CAR.IONIQ, CAR.KONA_EV, CAR.KIA_SORENTO,\n                     CAR.SONATA_LF, CAR.KIA_NIRO_EV, CAR.KIA_OPTIMA, CAR.VELOSTER, CAR.KIA_STINGER, CAR.KIA_SELTOS,\n                     CAR.GENESIS_G70, CAR.GENESIS_G80, CAR.KIA_CEED, CAR.ELANTRA]:\n      ret.safetyModel = car.CarParams.SafetyModel.hyundaiLegacy\n\n    # set appropriate safety param for gas signal\n    if candidate in HYBRID_CAR:\n      ret.safetyParam = 2\n    elif candidate in EV_CAR:\n      ret.safetyParam = 1\n\n    ret.centerToFront = ret.wheelbase * 0.4\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n\n    ret.enableBsm = 0x58b in fingerprint[0]\n\n    # dp\n    if Params().get('dp_hkg_smart_mdps') == b'1':\n      ret.minSteerSpeed = 0.\n    ret = common_interface_get_params_lqr(ret)\n    return ret\n\n  def update(self, c, can_strings, dragonconf):\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam)\n    # dp\n    self.dragonconf = dragonconf\n    if ret.vEgo >= self.CP.minSteerSpeed:\n      ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n    ret.steeringRateLimited = self.CC.steer_rate_limited if self.CC is not None else False\n\n    events = self.create_common_events(ret)\n\n    if dragonconf.dpAtl:\n      if ret.vEgo < self.CP.minSteerSpeed:\n        events.add(car.CarEvent.EventName.belowSteerSpeed)\n    else:\n      # low speed steer alert hysteresis logic (only for cars with steer cut off above 10 m/s)\n      if ret.vEgo < (self.CP.minSteerSpeed + 2.) and self.CP.minSteerSpeed > 10.:\n        self.low_speed_alert = True\n      if ret.vEgo > (self.CP.minSteerSpeed + 4.):\n        self.low_speed_alert = False\n      if self.low_speed_alert:\n        events.add(car.CarEvent.EventName.belowSteerSpeed)\n\n    ret.events = events.to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  def apply(self, c):\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, c.actuators,\n                               c.cruiseControl.cancel, c.hudControl.visualAlert, c.hudControl.leftLaneVisible,\n                               c.hudControl.rightLaneVisible, c.hudControl.leftLaneDepart, c.hudControl.rightLaneDepart, self.dragonconf)\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/hyundai/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.interfaces import RadarInterfaceBase\nfrom selfdrive.car.hyundai.values import DBC\n\n\ndef get_radar_can_parser(CP):\n  signals = [\n    # sig_name, sig_address, default\n    (\"ACC_ObjStatus\", \"SCC11\", 0),\n    (\"ACC_ObjLatPos\", \"SCC11\", 0),\n    (\"ACC_ObjDist\", \"SCC11\", 0),\n    (\"ACC_ObjRelSpd\", \"SCC11\", 0),\n  ]\n  checks = [\n    # address, frequency\n    (\"SCC11\", 50),\n  ]\n  return CANParser(DBC[CP.carFingerprint]['pt'], signals, checks, 0)\n\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.rcp = get_radar_can_parser(CP)\n    self.updated_messages = set()\n    self.trigger_msg = 0x420\n    self.track_id = 0\n    self.radar_off_can = CP.radarOffCan\n\n  def update(self, can_strings):\n    if self.radar_off_can:\n      return super().update(None)\n\n    vls = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(vls)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    rr = self._update(self.updated_messages)\n    self.updated_messages.clear()\n\n    return rr\n\n  def _update(self, updated_messages):\n    ret = car.RadarData.new_message()\n    cpt = self.rcp.vl\n    errors = []\n    if not self.rcp.can_valid:\n      errors.append(\"canError\")\n    ret.errors = errors\n\n    valid = cpt[\"SCC11\"]['ACC_ObjStatus']\n    if valid:\n      for ii in range(2):\n        if ii not in self.pts:\n          self.pts[ii] = car.RadarData.RadarPoint.new_message()\n          self.pts[ii].trackId = self.track_id\n          self.track_id += 1\n        self.pts[ii].dRel = cpt[\"SCC11\"]['ACC_ObjDist']  # from front of car\n        self.pts[ii].yRel = -cpt[\"SCC11\"]['ACC_ObjLatPos']  # in car frame's y axis, left is negative\n        self.pts[ii].vRel = cpt[\"SCC11\"]['ACC_ObjRelSpd']\n        self.pts[ii].aRel = float('nan')\n        self.pts[ii].yvRel = float('nan')\n        self.pts[ii].measured = True\n\n    ret.points = list(self.pts.values())\n    return ret\n"
  },
  {
    "path": "selfdrive/car/hyundai/values.py",
    "content": "# flake8: noqa\n\nfrom cereal import car\nfrom selfdrive.car import dbc_dict\nEcu = car.CarParams.Ecu\nfrom common.params import Params\n\n# Steer torque limits\nclass CarControllerParams:\n  def __init__(self, CP):\n    if Params().get('dp_hkg_smart_mdps') == b'1':\n      self.STEER_MAX = 384\n    elif CP.carFingerprint in [CAR.SONATA, CAR.PALISADE, CAR.SANTA_FE, CAR.VELOSTER, CAR.GENESIS_G70,\n                             CAR.IONIQ_EV_2020, CAR.KIA_CEED, CAR.KIA_SELTOS, CAR.ELANTRA_2021,\n                             CAR.ELANTRA_HEV_2021, CAR.SONATA_HYBRID, CAR.KONA_HEV]:\n      self.STEER_MAX = 384\n    else:\n      self.STEER_MAX = 255\n    self.STEER_DELTA_UP = 3\n    self.STEER_DELTA_DOWN = 7\n    self.STEER_DRIVER_ALLOWANCE = 50\n    self.STEER_DRIVER_MULTIPLIER = 2\n    self.STEER_DRIVER_FACTOR = 1\n\n\nclass CAR:\n  # Hyundai\n  ELANTRA = \"HYUNDAI ELANTRA 2017\"\n  ELANTRA_2021 = \"HYUNDAI ELANTRA 2021\"\n  ELANTRA_HEV_2021 = \"HYUNDAI ELANTRA HYBRID 2021\"\n  ELANTRA_GT_I30 = \"HYUNDAI I30 N LINE 2019 & GT 2018 DCT\"\n  HYUNDAI_GENESIS = \"HYUNDAI GENESIS 2015-2016\"\n  IONIQ = \"HYUNDAI IONIQ HYBRID 2017-2019\"\n  IONIQ_EV_LTD = \"HYUNDAI IONIQ ELECTRIC LIMITED 2019\"\n  IONIQ_EV_2020 = \"HYUNDAI IONIQ ELECTRIC 2020\"\n  IONIQ_PHEV = \"HYUNDAI IONIQ PHEV 2020\"\n  KONA = \"HYUNDAI KONA 2020\"\n  KONA_EV = \"HYUNDAI KONA ELECTRIC 2019\"\n  KONA_HEV = \"HYUNDAI KONA HYBRID 2020\"\n  SANTA_FE = \"HYUNDAI SANTA FE 2019\"\n  SONATA = \"HYUNDAI SONATA 2020\"\n  SONATA_LF = \"HYUNDAI SONATA 2019\"\n  PALISADE = \"HYUNDAI PALISADE 2020\"\n  VELOSTER = \"HYUNDAI VELOSTER 2019\"\n  SONATA_HYBRID = \"HYUNDAI SONATA HYBRID 2021\"\n\n  # Kia\n  KIA_FORTE = \"KIA FORTE E 2018 & GT 2021\"\n  KIA_NIRO_EV = \"KIA NIRO EV 2020\"\n  KIA_NIRO_HEV = \"KIA NIRO HYBRID 2019\"\n  KIA_NIRO_HEV_2021 = \"KIA NIRO HYBRID 2021\"\n  KIA_OPTIMA = \"KIA OPTIMA SX 2019 & 2016\"\n  KIA_OPTIMA_H = \"KIA OPTIMA HYBRID 2017 & SPORTS 2019\"\n  KIA_SELTOS = \"KIA SELTOS 2021\"\n  KIA_SORENTO = \"KIA SORENTO GT LINE 2018\"\n  KIA_STINGER = \"KIA STINGER GT2 2018\"\n  KIA_CEED = \"KIA CEED INTRO ED 2019\"\n\n  # Genesis\n  GENESIS_G70 = \"GENESIS G70 2018\"\n  GENESIS_G80 = \"GENESIS G80 2017\"\n  GENESIS_G90 = \"GENESIS G90 2017\"\n\n\nclass Buttons:\n  NONE = 0\n  RES_ACCEL = 1\n  SET_DECEL = 2\n  GAP_DIST = 3\n  CANCEL = 4\n\nFINGERPRINTS = {\n  CAR.ELANTRA: [{\n    66: 8, 67: 8, 68: 8, 127: 8, 273: 8, 274: 8, 275: 8, 339: 8, 356: 4, 399: 8, 512: 6, 544: 8, 593: 8, 608: 8, 688: 5, 790: 8, 809: 8, 897: 8, 832: 8, 899: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1170: 8, 1265: 4, 1280: 1, 1282: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1314: 8, 1322: 8, 1345: 8, 1349: 8, 1351: 8, 1353: 8, 1363: 8, 1366: 8, 1367: 8, 1369: 8, 1407: 8, 1415: 8, 1419: 8, 1425: 2, 1427: 6, 1440: 8, 1456: 4, 1472: 8, 1486: 8, 1487: 8, 1491: 8, 1530: 8, 1532: 5, 2001: 8, 2003: 8, 2004: 8, 2009: 8, 2012: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n  }],\n  CAR.ELANTRA_GT_I30: [{\n    66: 8, 67: 8, 68: 8, 127: 8, 128: 8, 129: 8, 273: 8, 274: 8, 275: 8, 339: 8, 354: 3, 356: 4, 399: 8, 512: 6, 544: 8, 593: 8, 608: 8, 688: 5, 790: 8, 809: 8, 884: 8, 897: 8, 899: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1151: 6, 1168: 7, 1170: 8, 1193: 8, 1265: 4, 1280: 1, 1282: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1345: 8, 1348: 8, 1349: 8, 1351: 8, 1353: 8, 1356: 8, 1363: 8, 1365: 8, 1366: 8, 1367: 8, 1369: 8, 1407: 8, 1414: 3, 1415: 8, 1427: 6, 1440: 8, 1456: 4, 1470: 8, 1486: 8, 1487: 8, 1491: 8, 1530: 8, 1952: 8, 1960: 8, 1988: 8, 2000: 8, 2001: 8, 2005: 8, 2008: 8, 2009: 8, 2013: 8, 2017: 8, 2025: 8\n  },\n  {\n    66: 8, 67: 8, 68: 8, 127: 8, 128: 8, 129: 8, 273: 8, 274: 8, 275: 8, 339: 8, 354: 3, 356: 4, 399: 8, 512: 6, 544: 8, 593: 8, 608: 8, 688: 5, 790: 8, 809: 8, 832: 8, 897: 8, 899: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1151: 6, 1168: 7, 1170: 8, 1265: 4, 1280: 1, 1282: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1349: 8, 1351: 8, 1353: 8, 1356: 8, 1363: 8, 1366: 8, 1367: 8, 1369: 8, 1407: 8, 1414: 3, 1415: 8, 1419: 8, 1440: 8, 1456: 4, 1470: 8, 1486: 8, 1487: 8, 1491: 8, 1530: 8\n  },\n  {\n    66: 8, 67: 8, 68: 8, 127: 8, 128: 8, 129: 8, 273: 8, 274: 8, 275: 8, 339: 8, 354: 3, 356: 4, 399: 8, 512: 6, 544: 8, 593: 8, 608: 8, 688: 5, 790: 8, 809: 8, 832: 8, 897: 8, 899: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1151: 6, 1168: 7, 1170: 8, 1265: 4, 1280: 1, 1282: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1349: 8, 1351: 8, 1353: 8, 1356: 8, 1363: 8, 1366: 8, 1367: 8, 1369: 8, 1407: 8, 1414: 3, 1419: 8, 1427: 6, 1440: 8, 1456: 4, 1470: 8, 1486: 8, 1487: 8, 1491: 8, 1960: 8, 1990: 8, 1998: 8, 2000: 8, 2001: 8, 2004: 8, 2005: 8, 2008: 8, 2009: 8, 2012: 8, 2013: 8, 2015: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n  }],\n  CAR.HYUNDAI_GENESIS: [{\n    67: 8, 68: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 7, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 5, 897: 8, 902: 8, 903: 6, 916: 8, 1024: 2, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1287: 4, 1292: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1334: 8, 1335: 8, 1342: 6, 1345: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1378: 4, 1384: 5, 1407: 8, 1419: 8, 1427: 6, 1434: 2, 1456: 4\n  },\n  {\n    67: 8, 68: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 7, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 5, 897: 8, 902: 8, 903: 6, 916: 8, 1024: 2, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1281: 3, 1287: 4, 1292: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1334: 8, 1335: 8, 1345: 8, 1363: 8, 1369: 8, 1370: 8, 1378: 4, 1379: 8, 1384: 5, 1407: 8, 1419: 8, 1427: 6, 1434: 2, 1456: 4\n  },\n  {\n    67: 8, 68: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 7, 593: 8, 608: 8, 688: 5, 809: 8, 854: 7, 870: 7, 871: 8, 872: 5, 897: 8, 902: 8, 903: 6, 912: 7, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1268: 8, 1280: 1, 1281: 3, 1287: 4, 1292: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1334: 8, 1335: 8, 1345: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1378: 4, 1384: 5, 1407: 8, 1419: 8, 1427: 6, 1434: 2, 1437: 8, 1456: 4\n  },\n  {\n    67: 8, 68: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 7, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 5, 897: 8, 902: 8, 903: 6, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1287: 4, 1292: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1334: 8, 1335: 8, 1345: 8, 1363: 8, 1369: 8, 1370: 8, 1378: 4, 1379: 8, 1384: 5, 1407: 8, 1425: 2, 1427: 6, 1437: 8, 1456: 4\n  },\n  {\n    67: 8, 68: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 7, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 5, 897: 8, 902: 8, 903: 6, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1287: 4, 1292: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1334: 8, 1335: 8, 1345: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1378: 4, 1384: 5, 1407: 8, 1419: 8, 1425: 2, 1427: 6, 1437: 8, 1456: 4\n  }],\n  CAR.SANTA_FE: [{\n    67: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 8, 593: 8, 608: 8, 688: 6, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1155: 8, 1156: 8, 1162: 8, 1164: 8, 1168: 7, 1170: 8, 1173: 8, 1183: 8, 1186: 2, 1191: 2, 1227: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1379: 8, 1384: 8, 1407: 8, 1414: 3, 1419: 8, 1427: 6, 1456: 4, 1470: 8\n  },\n  {\n    67: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 8, 593: 8, 608: 8, 688: 6, 764: 8, 809: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1064: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1155: 8, 1162: 8, 1164: 8, 1168: 7, 1170: 8, 1173: 8, 1180: 8, 1183: 8, 1186: 2, 1227: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1371: 8, 1378: 8, 1384: 8, 1407: 8, 1414: 3, 1419: 8, 1427: 6, 1456: 4, 1470: 8, 1988: 8, 2000: 8, 2004: 8, 2008: 8, 2012: 8\n  },\n  {\n    67: 8, 68: 8, 80: 4, 160: 8, 161: 8, 272: 8, 288: 4, 339: 8, 356: 8, 357: 8, 399: 8, 544: 8, 608: 8, 672: 8, 688: 5, 704: 1, 790: 8, 809: 8, 848: 8, 880: 8, 898: 8, 900: 8, 901: 8, 904: 8, 1056: 8, 1064: 8, 1065: 8, 1072: 8, 1075: 8, 1087: 8, 1088: 8, 1151: 8, 1200: 8, 1201: 8, 1232: 4, 1264: 8, 1265: 8, 1266: 8, 1296: 8, 1306: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1348: 8, 1349: 8, 1369: 8, 1370: 8, 1371: 8, 1407: 8, 1415: 8, 1419: 8, 1440: 8, 1442: 4, 1461: 8, 1470: 8\n  }],\n  CAR.SONATA: [\n    {67: 8, 68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 8, 546: 8, 549: 8, 550: 8, 576: 8, 593: 8, 608: 8, 688: 6, 809: 8, 832: 8, 854: 8, 865: 8, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 905: 8, 908: 8, 909: 8, 912: 7, 913: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1089: 5, 1096: 8, 1107: 5, 1108: 8, 1114: 8, 1136: 8, 1145: 8, 1151: 8, 1155: 8, 1156: 8, 1157: 4, 1162: 8, 1164: 8, 1168: 8, 1170: 8, 1173: 8, 1180: 8, 1183: 8, 1184: 8, 1186: 2, 1191: 2, 1193: 8, 1210: 8, 1225: 8, 1227: 8, 1265: 4, 1268: 8, 1280: 8, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1330: 8, 1339: 8, 1342: 6, 1343: 8, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1371: 8, 1378: 8, 1379: 8, 1384: 8, 1394: 8, 1407: 8, 1419: 8, 1427: 6, 1446: 8, 1456: 4, 1460: 8, 1470: 8, 1485: 8, 1504: 3, 1988: 8, 1996: 8, 2000: 8, 2004: 8, 2008: 8, 2012: 8, 2015: 8},\n  ],\n  CAR.SONATA_LF: [\n    {66: 8, 67: 8, 68: 8, 127: 8, 273: 8, 274: 8, 275: 8, 339: 8, 356: 4, 399: 8, 447: 8, 512: 6, 544: 8, 593: 8, 608: 8, 688: 5, 790: 8, 809: 8, 832: 8, 884: 8, 897: 8, 899: 8, 902: 8, 903: 6, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1151: 6, 1168: 7, 1170: 8, 1253: 8, 1254: 8, 1255: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1314: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1342: 6, 1345: 8, 1348: 8, 1349: 8, 1351: 8, 1353: 8, 1363: 8, 1365: 8, 1366: 8, 1367: 8, 1369: 8, 1397: 8, 1407: 8, 1415: 8, 1419: 8, 1425: 2, 1427: 6, 1440: 8, 1456: 4, 1470: 8, 1472: 8, 1486: 8, 1487: 8, 1491: 8, 1530: 8, 1532: 5, 2000: 8, 2001: 8, 2004: 8, 2005: 8, 2008: 8, 2009: 8, 2012: 8, 2013: 8, 2014: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8},\n  ],\n  CAR.KIA_OPTIMA: [{\n    64: 8, 66: 8, 67: 8, 68: 8, 127: 8, 128: 8, 129: 8, 273: 8, 274: 8, 275: 8, 339: 8, 354: 3, 356: 4, 399: 8, 447: 8, 512: 6, 544: 8, 558: 8, 593: 8, 608: 8, 640: 8, 688: 5, 790: 8, 809: 8, 832: 8, 884: 8, 897: 8, 899: 8, 902: 8, 903: 6, 909: 8, 912: 7, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1151: 6, 1168: 7, 1170: 8, 1186: 2, 1191: 2, 1253: 8, 1254: 8, 1255: 8, 1265: 4, 1268: 8, 1280: 1, 1282: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1342: 6, 1345: 8, 1348: 8, 1349: 8, 1351: 8, 1353: 8, 1356: 8, 1363: 8, 1365: 8, 1366: 8, 1367: 8, 1369: 8, 1407: 8, 1414: 3, 1415: 8, 1419: 8, 1425: 2, 1427: 6, 1440: 8, 1456: 4, 1470: 8, 1472: 8, 1486: 8, 1487: 8, 1491: 8, 1492: 8, 1530: 8, 1532: 5, 1792: 8, 1872: 8, 1937: 8, 1953: 8, 1968: 8, 1988: 8, 1996: 8, 2000: 8, 2001: 8, 2004: 8, 2008: 8, 2009: 8, 2012: 8, 2015: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8, 1371: 8, 1397: 8, 1961: 8\n  }],\n  CAR.KIA_SORENTO: [{\n    67: 8, 68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 8, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1064: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1384: 8, 1407: 8, 1411: 8, 1419: 8, 1425: 2, 1427: 6, 1444: 8, 1456: 4, 1470: 8, 1489: 1\n  }],\n  CAR.KIA_STINGER: [{\n    67: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 358: 6, 359: 8, 544: 8, 576: 8, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1064: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1281: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1371: 8, 1378: 4, 1379: 8, 1384: 8, 1407: 8, 1419: 8, 1425: 2, 1427: 6, 1456: 4, 1470: 8\n  }],\n  CAR.GENESIS_G80: [{\n    67: 8, 68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 358: 6, 544: 8, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 916: 8, 1024: 2, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1156: 8, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1191: 2, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1378: 4, 1384: 8, 1407: 8, 1419: 8, 1425: 2, 1427: 6, 1434: 2, 1456: 4, 1470: 8\n  },\n  {\n    67: 8, 68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 358: 6, 359: 8, 544: 8, 546: 8, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1064: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1156: 8, 1157: 4, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1281: 3, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1378: 4, 1384: 8, 1407: 8, 1419: 8, 1425: 2, 1427: 6, 1434: 2, 1437: 8, 1456: 4, 1470: 8\n  },\n  {\n    67: 8, 68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 358: 6, 544: 8, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1064: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1156: 8, 1157: 4, 1162: 8, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1193: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1371: 8, 1378: 4, 1384: 8, 1407: 8, 1419: 8, 1425: 2, 1427: 6, 1437: 8, 1456: 4, 1470: 8\n  }],\n  CAR.GENESIS_G90: [{\n    67: 8, 68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 358: 6, 359: 8, 544: 8, 593: 8, 608: 8, 688: 5, 809: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1151: 6, 1162: 4, 1168: 7, 1170: 8, 1173: 8, 1184: 8, 1265: 4, 1280: 1, 1281: 3, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1370: 8, 1371: 8, 1378: 4, 1384: 8, 1407: 8, 1419: 8, 1425: 2, 1427: 6, 1434: 2, 1456: 4, 1470: 8, 1988: 8, 2000: 8, 2003: 8, 2004: 8, 2005: 8, 2008: 8, 2011: 8, 2012: 8, 2013: 8\n  }],\n  CAR.IONIQ_EV_2020: [{\n    127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 524: 8, 544: 7, 593: 8, 688: 5, 832: 8, 881: 8, 882: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 8, 1151: 6, 1155: 8, 1156: 8, 1157: 4, 1164: 8, 1168: 7, 1173: 8, 1183: 8, 1186: 2, 1191: 2, 1225: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1379: 8, 1407: 8, 1419: 8, 1426: 8, 1427: 6, 1429: 8, 1430: 8, 1456: 4, 1470: 8, 1473: 8, 1507: 8, 1535: 8, 1988: 8, 1996: 8, 2000: 8, 2004: 8, 2005: 8, 2008: 8, 2012: 8, 2013: 8\n  }],\n  CAR.IONIQ_EV_LTD: [{\n    127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 544: 7, 593: 8, 688: 5, 832: 8, 881: 8, 882: 8, 897: 8, 902: 8, 903: 8, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 8, 1151: 6, 1168: 7, 1173: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1294: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1407: 8, 1419: 8, 1425: 2, 1426: 8, 1427: 6, 1429: 8, 1430: 8, 1456: 4, 1470: 8, 1507: 8, 1535: 8\n  }],\n  CAR.IONIQ: [{\n    68:8, 127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 524: 8, 544: 8, 576:8, 593: 8, 688: 5, 832: 8, 881: 8, 882: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 6, 1151: 6, 1155: 8, 1156: 8, 1157: 4, 1164: 8, 1168: 7, 1173: 8, 1183: 8, 1186: 2, 1191: 2, 1225: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1379: 8, 1407: 8, 1419: 8, 1426: 8, 1427: 6, 1429: 8, 1430: 8, 1448: 8, 1456: 4, 1470: 8, 1473: 8, 1476: 8, 1507: 8, 1535: 8, 1988: 8, 1996: 8, 2000: 8, 2004: 8, 2005: 8, 2008: 8, 2012: 8, 2013: 8\n  }],\n  CAR.KONA_EV: [{\n    127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 544: 8, 549: 8, 593: 8, 688: 5, 832: 8, 881: 8, 882: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 8, 1151: 6, 1168: 7, 1173: 8, 1183: 8, 1186: 2, 1191: 2, 1225: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1294: 8, 1307: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1378: 4, 1407: 8, 1419: 8, 1426: 8, 1427: 6, 1429: 8, 1430: 8, 1456: 4, 1470: 8, 1473: 8, 1507: 8, 1535: 8, 2000: 8, 2004: 8, 2008: 8, 2012: 8, 1157: 4, 1193: 8, 1379: 8, 1988: 8, 1996: 8\n  }],\n  CAR.KIA_NIRO_EV: [{\n    127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 516: 8, 544: 8, 593: 8, 688: 5, 832: 8, 881: 8, 882: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 8, 1151: 6, 1156: 8, 1157: 4, 1168: 7, 1173: 8, 1183: 8, 1186: 2, 1191: 2, 1193: 8, 1225: 8, 1260: 8, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1407: 8, 1419: 8, 1426: 8, 1427: 6, 1429: 8, 1430: 8, 1456: 4, 1470: 8, 1473: 8, 1507: 8, 1535: 8, 1990: 8, 1998: 8, 1996: 8, 2000: 8, 2004: 8, 2008: 8, 2012: 8, 2015: 8\n  }],\n  CAR.KIA_FORTE: [{\n    67: 8, 127: 8, 304: 8, 320: 8, 339: 8, 354: 3, 356: 4, 544: 8, 576: 8, 593: 8, 608: 8, 688: 5, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1078: 4, 1107: 5, 1136: 8, 1156: 8, 1170: 8, 1173: 8, 1186: 2, 1191: 2, 1225: 8, 1265: 4, 1280: 4, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1384: 8, 1394: 8, 1407: 8, 1414: 3, 1419: 8, 1427: 6, 1456: 4, 1470: 8, 1988: 8, 1996: 8, 2000: 8, 2004: 8, 2008: 8, 2012: 8, 2015: 8\n  }],\n  CAR.KIA_OPTIMA_H: [{\n    68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 544: 8, 593: 8, 688: 5, 832: 8, 881: 8, 882: 8, 897: 8, 902: 8, 903: 6, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 6, 1151: 6, 1168: 7, 1173: 8, 1236: 2, 1265: 4, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1322: 8, 1331: 8, 1332: 8, 1333: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1371: 8, 1407: 8, 1419: 8, 1427: 6, 1429: 8, 1430: 8, 1448: 8, 1456: 4, 1470: 8, 1476: 8, 1535: 8\n  },\n  {\n    68: 8, 127: 8, 304: 8, 320: 8, 339: 8, 352: 8, 356: 4, 544: 8, 576: 8, 593: 8, 688: 5, 881: 8, 882: 8, 897: 8, 902: 8, 903: 8, 909: 8, 912: 7, 916: 8, 1040: 8, 1056: 8, 1057: 8, 1078: 4, 1136: 6, 1151: 6, 1168: 7, 1173: 8, 1180: 8, 1186: 2, 1191: 2, 1265: 4, 1268: 8, 1280: 1, 1287: 4, 1290: 8, 1291: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1355: 8, 1363: 8, 1369: 8, 1371: 8, 1407: 8, 1419: 8, 1420: 8, 1425: 2, 1427: 6, 1429: 8, 1430: 8, 1448: 8, 1456: 4, 1470: 8, 1476: 8, 1535: 8\n  }],\n  CAR.PALISADE: [{\n    67: 8, 127: 8, 304: 8, 320: 8, 339: 8, 356: 4, 544: 8, 546: 8, 547: 8, 548: 8, 549: 8, 576: 8, 593: 8, 608: 8, 688: 6, 809: 8, 832: 8, 854: 7, 870: 7, 871: 8, 872: 8, 897: 8, 902: 8, 903: 8, 905: 8, 909: 8, 913: 8, 916: 8, 1040: 8, 1042: 8, 1056: 8, 1057: 8, 1064: 8, 1078: 4, 1107: 5, 1123: 8, 1136: 8, 1151: 6, 1155: 8, 1156: 8, 1157: 4, 1162: 8, 1164: 8, 1168: 7, 1170: 8, 1173: 8, 1180: 8, 1186: 2, 1191: 2, 1193: 8, 1210: 8, 1225: 8, 1227: 8, 1265: 4, 1280: 8, 1287: 4, 1290: 8, 1292: 8, 1294: 8, 1312: 8, 1322: 8, 1342: 6, 1345: 8, 1348: 8, 1363: 8, 1369: 8, 1371: 8, 1378: 8, 1384: 8, 1407: 8, 1419: 8, 1427: 6, 1456: 4, 1470: 8, 1988: 8, 1996: 8, 2000: 8, 2004: 8, 2005: 8, 2008: 8, 2012: 8\n  }],\n}\n\n\nFW_VERSIONS = {\n  CAR.IONIQ_PHEV: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\000AEhe SCC FHCUP      1.00 1.02 99110-G2100         ',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\000AE  MDPS C 1.00 1.01 56310/G2510 4APHC101',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\000AEP MFC  AT USA LHD 1.00 1.01 95740-G2600 190819',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x816H6F6051\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x816U3J9051\\000\\000\\xf1\\0006U3H1_C2\\000\\0006U3J9051\\000\\000PAE0G16NL0\\x82zT\\xd2',\n    ],\n  },\n  CAR.IONIQ_EV_2020: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00AEev SCC F-CUP      1.00 1.01 99110-G7000         ',\n      b'\\xf1\\x00AEev SCC F-CUP      1.00 1.00 99110-G7200         ',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00AE  MDPS C 1.00 1.01 56310/G7310 4APEC101',\n      b'\\xf1\\x00AE  MDPS C 1.00 1.01 56310/G7560 4APEC101',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00AEE MFC  AT EUR LHD 1.00 1.01 95740-G2600 190819',\n      b'\\xf1\\x00AEE MFC  AT EUR LHD 1.00 1.03 95740-G2500 190516',\n      b'\\xf1\\x00AEE MFC  AT EUR RHD 1.00 1.01 95740-G2600 190819',\n    ],\n  },\n  CAR.IONIQ_EV_LTD: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00AEev SCC F-CUP      1.00 1.00 96400-G7000         ',\n      b'\\xf1\\x00AEev SCC F-CUP      1.00 1.00 96400-G7100         ',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00AE  MDPS C 1.00 1.02 56310G7300\\x00 4AEEC102',\n      b'\\xf1\\x00AE  MDPS C 1.00 1.04 56310/G7501 4AEEC104',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00AEE MFC  AT EUR LHD 1.00 1.00 95740-G7200 160418',\n      b'\\xf1\\x00AEE MFC  AT USA LHD 1.00 1.00 95740-G2400 180222',\n    ],\n  },\n  CAR.SONATA: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00DN8_ SCC F-CU-      1.00 1.00 99110-L0000         ',\n      b'\\xf1\\x00DN8_ SCC F-CUP      1.00 1.00 99110-L0000         ',\n      b'\\xf1\\x00DN8_ SCC F-CUP      1.00 1.02 99110-L1000         ',\n      b'\\xf1\\x00DN8_ SCC FHCUP      1.00 1.00 99110-L0000         ',\n      b'\\xf1\\x00DN8_ SCC FHCUP      1.00 1.01 99110-L1000         ',\n      b'\\xf1\\x00DN89110-L0000         \\xaa\\xaa\\xaa\\xaa\\xaa\\xaa\\xaa     \\xf1\\xa01.00\\xaa\\xaa\\xaa\\xaa\\xaa\\xaa\\xaa\\x00\\x00\\x00',\n      b'\\xf1\\x00DN8 1.00 99110-L0000         \\xaa\\xaa\\xaa\\xaa\\xaa\\xaa\\xaa     \\xf1\\xa01.00\\xaa\\xaa\\xaa',\n    ],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x00DN ESC \\a 106 \\a\\x01 58910-L0100',\n      b'\\xf1\\x00DN ESC \\x01 102\\x19\\x04\\x13 58910-L1300\\xf1\\xa01.02',\n      b'\\xf1\\x00DN ESC \\x03 100 \\x08\\x01 58910-L0300',\n      b'\\xf1\\x00DN ESC \\x06 104\\x19\\x08\\x01 58910-L0100',\n      b'\\xf1\\x00DN ESC \\x07 104\\x19\\x08\\x01 58910-L0100',\n      b'\\xf1\\x00DN ESC \\x08 103\\x19\\x06\\x01 58910-L1300\\xf1\\xa01.03',\n      b'\\xf1\\x8758910-L0100\\xf1\\x00DN ESC \\a 106 \\a\\x01 58910-L0100\\xf1\\xa01.06',\n      b'\\xf1\\x8758910-L0100\\xf1\\x00DN ESC \\x06 104\\x19\\x08\\x01 58910-L0100\\xf1\\xa01.04',\n      b'\\xf1\\x8758910-L0100\\xf1\\x00DN ESC \\x06 106 \\x07\\x01 58910-L0100\\xf1\\xa01.06',\n      b'\\xf1\\x8758910-L0100\\xf1\\x00DN ESC \\x07 104\\x19\\x08\\x01 58910-L0100\\xf1\\xa01.04',\n      b'\\xf1\\x00DN ESC \\x06 106 \\x07\\x01 58910-L0100',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x81HM6M1_0a0_F00',\n      b'\\xf1\\x82DNBVN5GMCCXXXDCA',\n      b'\\xf1\\x82DNBWN5TMDCXXXG2E',\n      b'\\xf1\\x82DNCVN5GMCCXXXG2B',\n      b'\\xf1\\x87391162M003\\xf1\\xa0000F',\n      b'\\xf1\\x87391162M003\\xf1\\xa00240',\n      b'\\xf1\\x87391162M013\\xf1\\xa00240',\n      b'HM6M1_0a0_F00',\n      b'HM6M2_0a0_BD0',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00DN8 MDPS C 1.00 1.01 \\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00 4DNAC101',\n      b'\\xf1\\x00DN8 MDPS C 1.00 1.01 56310-L0010 4DNAC101',\n      b'\\xf1\\x00DN8 MDPS C 1.00 1.01 56310L0010\\x00 4DNAC101',\n      b'\\xf1\\x00DN8 MDPS R 1.00 1.00 57700-L0000 4DNAP100',\n      b'\\xf1\\x87\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00DN8 MDPS C 1.00 1.01 \\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00 4DNAC101\\xf1\\xa01.01',\n      b'\\xf1\\x8756310-L0010\\xf1\\x00DN8 MDPS C 1.00 1.01 56310-L0010 4DNAC101\\xf1\\xa01.01',\n      b'\\xf1\\x8756310-L0210\\xf1\\x00DN8 MDPS C 1.00 1.01 56310-L0210 4DNAC101\\xf1\\xa01.01',\n      b'\\xf1\\x8756310-L1010\\xf1\\x00DN8 MDPS C 1.00 1.03 56310-L1010 4DNDC103\\xf1\\xa01.03',\n      b'\\xf1\\x8756310-L1030\\xf1\\x00DN8 MDPS C 1.00 1.03 56310-L1030 4DNDC103\\xf1\\xa01.03',\n      b'\\xf1\\x8756310L0010\\x00\\xf1\\x00DN8 MDPS C 1.00 1.01 56310L0010\\x00 4DNAC101\\xf1\\xa01.01',\n      b'\\xf1\\x8756310L0210\\x00\\xf1\\x00DN8 MDPS C 1.00 1.01 56310L0210\\x00 4DNAC101\\xf1\\xa01.01',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00DN8 MFC  AT KOR LHD 1.00 1.02 99211-L1000 190422',\n      b'\\xf1\\x00DN8 MFC  AT RUS LHD 1.00 1.03 99211-L1000 190705',\n      b'\\xf1\\x00DN8 MFC  AT USA LHD 1.00 1.00 99211-L0000 190716',\n      b'\\xf1\\x00DN8 MFC  AT USA LHD 1.00 1.01 99211-L0000 191016',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x00bcsh8p54  U903\\x00\\x00\\x00\\x00\\x00\\x00SDN8T16NB0z{\\xd4v',\n      b'\\xf1\\x00bcsh8p54  U913\\x00\\x00\\x00\\x00\\x00\\x00SDN8T16NB1\\xe3\\xc10\\xa1',\n      b'\\xf1\\x00bcsh8p54  U913\\x00\\x00\\x00\\x00\\x00\\x00SDN8T16NB2\\n\\xdd^\\xbc',\n      b'\\xf1\\x00HT6TA260BLHT6TA800A1TDN8C20KS4\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x00HT6TA260BLHT6TA810A1TDN8M25GS0\\x00\\x00\\x00\\x00\\x00\\x00\\xaa\\x8c\\xd9p',\n      b'\\xf1\\x00HT6WA250BLHT6WA910A1SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x00HT6WA250BLHT6WA910A1SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00\\x96\\xa1\\xf1\\x92',\n      b'\\xf1\\x00HT6WA280BLHT6WAD10A1SDN8G25NB2\\x00\\x00\\x00\\x00\\x00\\x00\\x08\\xc9O:',\n      b'\\xf1\\x00T02601BL  T02730A1  VDN8T25XXX730NS5\\xf7_\\x92\\xf5',\n      b'\\xf1\\x87SALDBA3510954GJ3ww\\x87xUUuWx\\x88\\x87\\x88\\x87w\\x88wvfwfc_\\xf9\\xff\\x98wO\\xffl\\xe0\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA3573534GJ3\\x89\\x98\\x89\\x88EUuWgwvwwwwww\\x88\\x87xTo\\xfa\\xff\\x86f\\x7f\\xffo\\x0e\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA3601464GJ3\\x88\\x88\\x88\\x88ffvggwvwvw\\x87gww\\x87wvo\\xfb\\xff\\x98\\x88\\x7f\\xffjJ\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA3753044GJ3UUeVff\\x86hwwwwvwwgvfgfvo\\xf9\\xfffU_\\xffC\\xae\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA3873834GJ3fefVwuwWx\\x88\\x97\\x88w\\x88\\x97xww\\x87wU_\\xfb\\xff\\x86f\\x8f\\xffN\\x04\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA4525334GJ3\\x89\\x99\\x99\\x99fevWh\\x88\\x86\\x88fwvgw\\x88\\x87xfo\\xfa\\xffuDo\\xff\\xd1>\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA4626804GJ3wwww\\x88\\x87\\x88xx\\x88\\x87\\x88wwgw\\x88\\x88\\x98\\x88\\x95_\\xf9\\xffuDo\\xff|\\xe7\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA4803224GJ3wwwwwvwg\\x88\\x88\\x98\\x88wwww\\x87\\x88\\x88xu\\x9f\\xfc\\xff\\x87f\\x8f\\xff\\xea\\xea\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA6347404GJ3wwwwff\\x86hx\\x88\\x97\\x88\\x88\\x88\\x88\\x88vfgf\\x88?\\xfc\\xff\\x86Uo\\xff\\xec/\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA6901634GJ3UUuWVeVUww\\x87wwwwwvUge\\x86/\\xfb\\xff\\xbb\\x99\\x7f\\xff]2\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SALDBA7077724GJ3\\x98\\x88\\x88\\x88ww\\x97ygwvwww\\x87ww\\x88\\x87x\\x87_\\xfd\\xff\\xba\\x99o\\xff\\x99\\x01\\xf1\\x89HT6WA910A1\\xf1\\x82SDN8G25NB1\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SAMDBA8054504GJ3gw\\x87xffvgffffwwwweUVUf?\\xfc\\xffvU_\\xff\\xddl\\xf1\\x89HT6WAD10A1\\xf1\\x82SDN8G25NB2\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.SONATA_LF: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00LF__ SCC F-CUP      1.00 1.00 96401-C2200         ',\n    ],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x00LF ESC \\f 11 \\x17\\x01\\x13 58920-C2610',\n      b'\\xf1\\x00LF ESC \\t 11 \\x17\\x01\\x13 58920-C2610',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x81606D5051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x81606D5K51\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x81606G1051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00LFF LKAS AT USA LHD 1.00 1.01 95740-C1000 E51',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x87LAHSGN012918KF10\\x98\\x88x\\x87\\x88\\x88x\\x87\\x88\\x88\\x98\\x88\\x87w\\x88w\\x88\\x88\\x98\\x886o\\xf6\\xff\\x98w\\x7f\\xff3\\x00\\xf1\\x816W3B1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3B1051\\x00\\x00TLF0T20NL2\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87LAHSGN012918KF10\\x98\\x88x\\x87\\x88\\x88x\\x87\\x88\\x88\\x98\\x88\\x87w\\x88w\\x88\\x88\\x98\\x886o\\xf6\\xff\\x98w\\x7f\\xff3\\x00\\xf1\\x816W3B1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3B1051\\x00\\x00TLF0T20NL2H\\r\\xbdm',\n      b'\\xf1\\x87\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xf1\\x816T6B4051\\x00\\x00\\xf1\\x006T6H0_C2\\x00\\x006T6B4051\\x00\\x00TLF0G24NL1\\xb0\\x9f\\xee\\xf5',\n      b'\\xf1\\x87\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xf1\\x816T6B4051\\x00\\x00\\xf1\\x006T6H0_C2\\x00\\x006T6B4051\\x00\\x00TLF0G24NL1\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x006T6H0_C2\\x00\\x006T6B4051\\x00\\x00TLF0G24NL1\\xb0\\x9f\\xee\\xf5',\n    ],\n  },\n  CAR.SANTA_FE: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00TM__ SCC F-CUP      1.00 1.01 99110-S2000         \\xf1\\xa01.01',\n      b'\\xf1\\x00TM__ SCC F-CUP      1.00 1.02 99110-S2000         \\xf1\\xa01.02',\n      b'\\xf1\\x00TM__ SCC F-CUP      1.00 1.03 99110-S2000         \\xf1\\xa01.03',\n    ],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x00TM ESC \\r 100\\x18\\x031 58910-S2650\\xf1\\xa01.00',\n      b'\\xf1\\x00TM ESC \\r 103\\x18\\x11\\x08 58910-S2650\\xf1\\xa01.03',\n      b'\\xf1\\x00TM ESC \\r 104\\x19\\a\\b 58910-S2650\\xf1\\xa01.04',\n      b'\\xf1\\x00TM ESC \\x02 100\\x18\\x030 58910-S2600\\xf1\\xa01.00',\n      b'\\xf1\\x00TM ESC \\x02 102\\x18\\x07\\x01 58910-S2600\\xf1\\xa01.02',\n      b'\\xf1\\x00TM ESC \\x02 103\\x18\\x11\\x07 58910-S2600\\xf1\\xa01.03',\n      b'\\xf1\\x00TM ESC \\x02 104\\x19\\x07\\x07 58910-S2600\\xf1\\xa01.04',\n      b'\\xf1\\x00TM ESC \\x03 103\\x18\\x11\\x07 58910-S2600\\xf1\\xa01.03',\n      b'\\xf1\\x00TM ESC \\x0c 103\\x18\\x11\\x08 58910-S2650',\n      b'\\xf1\\x00TM ESC \\x0c 103\\x18\\x11\\x08 58910-S2650\\xf1\\xa01.03',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x81606EA051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x81606G1051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x81606G3051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00TM  MDPS C 1.00 1.00 56340-S2000 8409',\n      b'\\xf1\\x00TM  MDPS C 1.00 1.00 56340-S2000 8A12',\n      b'\\xf1\\x00TM  MDPS C 1.00 1.01 56340-S2000 9129',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00TM  MFC  AT USA LHD 1.00 1.00 99211-S2000 180409',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x87LBJSGA7082574HG0\\x87www\\x98\\x88\\x88\\x88\\x99\\xaa\\xb9\\x9afw\\x86gx\\x99\\xa7\\x89co\\xf8\\xffvU_\\xffR\\xaf\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2T20NS1\\x00\\xa6\\xe0\\x91',\n      b'\\xf1\\x87LBKSGA0458404HG0vfvg\\x87www\\x89\\x99\\xa8\\x99y\\xaa\\xa7\\x9ax\\x88\\xa7\\x88t_\\xf9\\xff\\x86w\\x8f\\xff\\x15x\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2T20NS1\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87LDJUEA6010814HG1\\x87w\\x87x\\x86gvw\\x88\\x88\\x98\\x88gw\\x86wx\\x88\\x97\\x88\\x85o\\xf8\\xff\\x86f_\\xff\\xd37\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM4T20NS0\\xf8\\x19\\x92g',\n      b'\\xf1\\x87LDJUEA6458264HG1ww\\x87x\\x97x\\x87\\x88\\x88\\x99\\x98\\x89g\\x88\\x86xw\\x88\\x97x\\x86o\\xf7\\xffvw\\x8f\\xff3\\x9a\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM4T20NS0\\xf8\\x19\\x92g',\n      b'\\xf1\\x87LDKUEA2045844HG1wwww\\x98\\x88x\\x87\\x88\\x88\\xa8\\x88x\\x99\\x97\\x89x\\x88\\xa7\\x88U\\x7f\\xf8\\xffvfO\\xffC\\x1e\\xf1\\x816W3E0051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E0051\\x00\\x00TTM4T20NS3\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87LDKUEA9993304HG1\\x87www\\x97x\\x87\\x88\\x99\\x99\\xa9\\x99x\\x99\\xa7\\x89w\\x88\\x97x\\x86_\\xf7\\xffwwO\\xffl#\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM4T20NS1R\\x7f\\x90\\n',\n      b'\\xf1\\x87LDLUEA6061564HG1\\xa9\\x99\\x89\\x98\\x87wwwx\\x88\\x97\\x88x\\x99\\xa7\\x89x\\x99\\xa7\\x89sO\\xf9\\xffvU_\\xff<\\xde\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM4T20NS50\\xcb\\xc3\\xed',\n      b'\\xf1\\x87LDLUEA6159884HG1\\x88\\x87hv\\x99\\x99y\\x97\\x89\\xaa\\xb8\\x9ax\\x99\\x87\\x89y\\x99\\xb7\\x99\\xa7?\\xf7\\xff\\x97wo\\xff\\xf3\\x05\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM4T20NS5\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87LDLUEA6852664HG1\\x97wWu\\x97www\\x89\\xaa\\xc8\\x9ax\\x99\\x97\\x89x\\x99\\xa7\\x89SO\\xf7\\xff\\xa8\\x88\\x7f\\xff\\x03z\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM4T20NS50\\xcb\\xc3\\xed',\n      b'\\xf1\\x87LDLUEA6898374HG1fevW\\x87wwwx\\x88\\x97\\x88h\\x88\\x96\\x88x\\x88\\xa7\\x88ao\\xf9\\xff\\x98\\x99\\x7f\\xffD\\xe2\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM4T20NS5\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87LDLUEA6898374HG1fevW\\x87wwwx\\x88\\x97\\x88h\\x88\\x96\\x88x\\x88\\xa7\\x88ao\\xf9\\xff\\x98\\x99\\x7f\\xffD\\xe2\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM4T20NS50\\xcb\\xc3\\xed',\n      b'\\xf1\\x87SBJWAA5842214GG0\\x88\\x87\\x88xww\\x87x\\x89\\x99\\xa8\\x99\\x88\\x99\\x98\\x89w\\x88\\x87xw_\\xfa\\xfffU_\\xff\\xd1\\x8d\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2G24NS1\\x98{|\\xe3',\n      b'\\xf1\\x87SBJWAA5890864GG0\\xa9\\x99\\x89\\x98\\x98\\x87\\x98y\\x89\\x99\\xa8\\x99w\\x88\\x87xww\\x87wvo\\xfb\\xffuD_\\xff\\x9f\\xb5\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2G24NS1\\x98{|\\xe3',\n      b'\\xf1\\x87SBJWAA6562474GG0ffvgeTeFx\\x88\\x97\\x88ww\\x87www\\x87w\\x84o\\xfa\\xff\\x87fO\\xff\\xc2 \\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2G24NS1\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SBJWAA6562474GG0ffvgeTeFx\\x88\\x97\\x88ww\\x87www\\x87w\\x84o\\xfa\\xff\\x87fO\\xff\\xc2 \\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2G24NS1\\x98{|\\xe3',\n      b'\\xf1\\x87SBJWAA7780564GG0wvwgUUeVwwwwx\\x88\\x87\\x88wwwwd_\\xfc\\xff\\x86f\\x7f\\xff\\xd7*\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2G24NS2F\\x84<\\xc0',\n      b'\\xf1\\x87SBJWAA8278284GG0ffvgUU\\x85Xx\\x88\\x87\\x88x\\x88w\\x88ww\\x87w\\x96o\\xfd\\xff\\xa7U_\\xff\\xf2\\xa0\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM2G24NS2F\\x84<\\xc0',\n      b'\\xf1\\x87SBLWAA4363244GG0wvwgwv\\x87hgw\\x86ww\\x88\\x87xww\\x87wdo\\xfb\\xff\\x86f\\x7f\\xff3$\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM2G24NS6\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SBLWAA6622844GG0wwwwff\\x86hwwwwx\\x88\\x87\\x88\\x88\\x88\\x88\\x88\\x98?\\xfd\\xff\\xa9\\x88\\x7f\\xffn\\xe5\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM2G24NS7u\\x1e{\\x1c',\n      b'\\xf1\\x87SDJXAA7656854GG1DEtWUU\\x85X\\x88\\x88\\x98\\x88w\\x88\\x87xx\\x88\\x87\\x88\\x96o\\xfb\\xff\\x86f\\x7f\\xff.\\xca\\xf1\\x816W3C2051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3C2051\\x00\\x00TTM4G24NS2\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SDKXAA2443414GG1vfvgwv\\x87h\\x88\\x88\\x88\\x88ww\\x87wwwww\\x99_\\xfc\\xffvD?\\xffl\\xd2\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM4G24NS6\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x87SBLWAA4899564GG0VfvgUU\\x85Xx\\x88\\x87\\x88vfgf\\x87wxwvO\\xfb\\xff\\x97f\\xb1\\xffSB\\xf1\\x816W3E1051\\x00\\x00\\xf1\\x006W351_C2\\x00\\x006W3E1051\\x00\\x00TTM2G24NS7\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.KIA_STINGER: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00CK__ SCC F_CUP      1.00 1.01 96400-J5100         \\xf1\\xa01.01',\n      b'\\xf1\\x00CK__ SCC F_CUP      1.00 1.03 96400-J5100         \\xf1\\xa01.03',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x81606DE051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x81640E0051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x82CKJN3TMSDE0B\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x82CKKN3TMD_H0A\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00CK  MDPS R 1.00 1.04 57700-J5200 4C2CL104',\n      b'\\xf1\\x00CK  MDPS R 1.00 1.04 57700-J5220 4C2VL104',\n      b'\\xf1\\x00CK  MDPS R 1.00 1.04 57700-J5420 4C4VL104',\n      b'\\xf1\\x00CK  MDPS R 1.00 1.06 57700-J5420 4C4VL106',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00CK  MFC  AT USA LHD 1.00 1.03 95740-J5000 170822',\n      b'\\xf1\\x00CK  MFC  AT USA LHD 1.00 1.04 95740-J5000 180504',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x87VCJLE17622572DK0vd6D\\x99\\x98y\\x97vwVffUfvfC%CuT&Dx\\x87o\\xff{\\x1c\\xf1\\x81E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00SCK0T33NB0\\x88\\xa2\\xe6\\xf0',\n      b'\\xf1\\x87VDHLG17000192DK2xdFffT\\xa5VUD$DwT\\x86wveVeeD&T\\x99\\xba\\x8f\\xff\\xcc\\x99\\xf1\\x81E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00SCK0T33NB0\\x88\\xa2\\xe6\\xf0',\n      b'\\xf1\\x87VDHLG17000192DK2xdFffT\\xa5VUD$DwT\\x86wveVeeD&T\\x99\\xba\\x8f\\xff\\xcc\\x99\\xf1\\x89E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x82SCK0T33NB0',\n      b'\\xf1\\x87VDHLG17034412DK2vD6DfVvVTD$D\\x99w\\x88\\x98EDEDeT6DgfO\\xff\\xc3=\\xf1\\x81E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00SCK0T33NB0\\x88\\xa2\\xe6\\xf0',\n      b'\\xf1\\x87VDHLG17118862DK2\\x8awWwgu\\x96wVfUVwv\\x97xWvfvUTGTx\\x87o\\xff\\xc9\\xed\\xf1\\x81E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00SCK0T33NB0\\x88\\xa2\\xe6\\xf0',\n      b'\\xf1\\x87VDKLJ18675252DK6\\x89vhgwwwwveVU\\x88w\\x87w\\x99vgf\\x97vXfgw_\\xff\\xc2\\xfb\\xf1\\x89E25\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x82TCK0T33NB2',\n      b'\\xf1\\x87WAJTE17552812CH4vfFffvfVeT5DwvvVVdFeegeg\\x88\\x88o\\xff\\x1a]\\xf1\\x81E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  E21\\x00\\x00\\x00\\x00\\x00\\x00\\x00TCK2T20NB1\\x19\\xd2\\x00\\x94',\n    ],\n  },\n  CAR.PALISADE: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\000LX2_ SCC F-CUP      1.00 1.05 99110-S8100         \\xf1\\xa01.05',\n      b'\\xf1\\x00LX2 SCC FHCUP      1.00 1.04 99110-S8100         \\xf1\\xa01.04',\n      b'\\xf1\\x00LX2_ SCC FHCUP      1.00 1.04 99110-S8100         \\xf1\\xa01.04',\n      b'\\xf1\\x00LX2_ SCC FHCUP      1.00 1.05 99110-S8100         \\xf1\\xa01.05',\n    ],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x00LX ESC \\v 102\\x19\\x05\\a 58910-S8330\\xf1\\xa01.02',\n      b'\\xf1\\x00LX ESC \\v 103\\x19\\t\\x10 58910-S8360\\xf1\\xa01.03',\n      b'\\xf1\\x00LX ESC \\x01 103\\x19\\t\\x10 58910-S8360\\xf1\\xa01.03',\n      b'\\xf1\\x00LX ESC \\x01 103\\x31\\t\\020 58910-S8360\\xf1\\xa01.03',\n      b'\\xf1\\x00LX ESC \\x0b 101\\x19\\x03\\x17 58910-S8330\\xf1\\xa01.01',\n      b'\\xf1\\x00LX ESC \\x0b 102\\x19\\x05\\x07 58910-S8330',\n      b'\\xf1\\x00LX ESC \\x0b 103\\x19\\t\\x07 58910-S8330\\xf1\\xa01.03',\n      b'\\xf1\\x00LX ESC \\x0b 103\\x19\\t\\x10 58910-S8360',\n      b'\\xf1\\x00LX ESC \\x0b 104 \\x10\\x16 58910-S8360\\xf1\\xa01.04',\n      b'\\xf1\\x00ON ESC \\x0b 100\\x18\\x12\\x18 58910-S9360\\xf1\\xa01.00',\n      b'\\xf1\\x00ON ESC \\x0b 101\\x19\\t\\x08 58910-S9360\\xf1\\xa01.01',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x81640J0051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x81640K0051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00LX2 MDPS C 1,00 1,03 56310-S8020 4LXDC103', # modified firmware\n      b'\\xf1\\x00LX2 MDPS C 1.00 1.03 56310-S8020 4LXDC103',\n      b'\\xf1\\x00ON  MDPS C 1.00 1.00 56340-S9000 8B13',\n      b'\\xf1\\x00ON  MDPS C 1.00 1.01 56340-S9000 9201',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00LX2 MFC  AT USA LHD 1.00 1.03 99211-S8100 190125',\n      b'\\xf1\\x00LX2 MFC  AT USA LHD 1.00 1.05 99211-S8100 190909',\n      b'\\xf1\\x00LX2 MFC  AT USA LHD 1.00 1.07 99211-S8100 200422',\n      b'\\xf1\\x00LX2 MFC  AT USA LHD 1.00 1.08 99211-S8100 200903',\n      b'\\xf1\\x00ON  MFC  AT USA LHD 1.00 1.01 99211-S9100 181105',\n      b'\\xf1\\x00ON  MFC  AT USA LHD 1.00 1.03 99211-S9100 200720',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x00bcsh8p54  U872\\x00\\x00\\x00\\x00\\x00\\x00TON4G38NB1\\x96z28',\n      b'\\xf1\\x00bcsh8p54  U903\\x00\\x00\\x00\\x00\\x00\\x00TON4G38NB2[v\\\\\\xb6',\n      b'\\xf1\\x87LBLUFN650868KF36\\xa9\\x98\\x89\\x88\\xa8\\x88\\x88\\x88h\\x99\\xa6\\x89fw\\x86gw\\x88\\x97x\\xaa\\x7f\\xf6\\xff\\xbb\\xbb\\x8f\\xff+\\x82\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX2G38NB3\\xd1\\xc3\\xf8\\xa8',\n      b'\\xf1\\x87LBLUFN655162KF36\\x98\\x88\\x88\\x88\\x98\\x88\\x88\\x88x\\x99\\xa7\\x89x\\x99\\xa7\\x89x\\x99\\x97\\x89g\\x7f\\xf7\\xffwU_\\xff\\xe9!\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX2G38NB3\\xd1\\xc3\\xf8\\xa8',\n      b'\\xf1\\x87LBLUFN731381KF36\\xb9\\x99\\x89\\x98\\x98\\x88\\x88\\x88\\x89\\x99\\xa8\\x99\\x88\\x99\\xa8\\x89\\x88\\x88\\x98\\x88V\\177\\xf6\\xff\\x99w\\x8f\\xff\\xad\\xd8\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\000bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX2G38NB3\\xd1\\xc3\\xf8\\xa8',\n      b'\\xf1\\x87LDKVBN382172KF26\\x98\\x88\\x88\\x88\\xa8\\x88\\x88\\x88x\\x99\\xa7\\x89\\x87\\x88\\x98x\\x98\\x99\\xa9\\x89\\xa5_\\xf6\\xffDDO\\xff\\xcd\\x16\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB2\\xafL]\\xe7',\n      b'\\xf1\\x87LDKVBN424201KF26\\xba\\xaa\\x9a\\xa9\\x99\\x99\\x89\\x98\\x89\\x99\\xa8\\x99\\x88\\x99\\x98\\x89\\x88\\x99\\xa8\\x89v\\x7f\\xf7\\xffwf_\\xffq\\xa6\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB2\\xafL]\\xe7',\n      b'\\xf1\\x87LDKVBN540766KF37\\x87wgv\\x87w\\x87xx\\x99\\x97\\x89v\\x88\\x97h\\x88\\x88\\x88\\x88x\\x7f\\xf6\\xffvUo\\xff\\xd3\\x01\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB2\\xafL]\\xe7',\n      b'\\xf1\\x87LDLVBN560098KF26\\x86fff\\x87vgfg\\x88\\x96xfw\\x86gfw\\x86g\\x95\\xf6\\xffeU_\\xff\\x92c\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB2\\xafL]\\xe7',\n      b'\\xf1\\x87LDLVBN645817KF37\\x87www\\x98\\x87xwx\\x99\\x97\\x89\\x99\\x99\\x99\\x99g\\x88\\x96x\\xb6_\\xf7\\xff\\x98fo\\xff\\xe2\\x86\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN662115KF37\\x98\\x88\\x88\\x88\\xa8\\x88\\x88\\x88x\\x99\\x97\\x89x\\x99\\xa7\\x89\\x88\\x99\\xa8\\x89\\x88\\x7f\\xf7\\xfffD_\\xff\\xdc\\x84\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN667933KF37\\xb9\\x99\\x89\\x98\\xb9\\x99\\x99\\x99x\\x88\\x87\\x88w\\x88\\x87x\\x88\\x88\\x98\\x88\\xcbo\\xf7\\xffe3/\\xffQ!\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN673087KF37\\x97www\\x86fvgx\\x99\\x97\\x89\\x99\\xaa\\xa9\\x9ag\\x88\\x86x\\xe9_\\xf8\\xff\\x98w\\x7f\\xff\"\\xad\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN681363KF37\\x98\\x88\\x88\\x88\\x97x\\x87\\x88y\\xaa\\xa7\\x9a\\x88\\x88\\x98\\x88\\x88\\x88\\x88\\x88vo\\xf6\\xffvD\\x7f\\xff%v\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN713890KF26\\xb9\\x99\\x89\\x98\\xa9\\x99\\x99\\x99x\\x99\\x97\\x89\\x88\\x99\\xa8\\x89\\x88\\x99\\xb8\\x89Do\\xf7\\xff\\xa9\\x88o\\xffs\\r\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN733215KF37\\x99\\x98y\\x87\\x97wwwi\\x99\\xa6\\x99x\\x99\\xa7\\x89V\\x88\\x95h\\x86o\\xf7\\xffeDO\\xff\\x12\\xe7\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN750044KF37\\xca\\xa9\\x8a\\x98\\xa7wwwy\\xaa\\xb7\\x9ag\\x88\\x96x\\x88\\x99\\xa8\\x89\\xb9\\x7f\\xf6\\xff\\xa8w\\x7f\\xff\\xbe\\xde\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN752612KF37\\xba\\xaa\\x8a\\xa8\\x87w\\x87xy\\xaa\\xa7\\x9a\\x88\\x99\\x98\\x89x\\x88\\x97\\x88\\x96o\\xf6\\xffvU_\\xffh\\x1b\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDLVBN755553KF37\\x87xw\\x87\\x97w\\x87xy\\x99\\xa7\\x99\\x99\\x99\\xa9\\x99Vw\\x95gwo\\xf6\\xffwUO\\xff\\xb5T\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB3X\\xa8\\xc08',\n      b'\\xf1\\x87LDMVBN778156KF37\\x87vWe\\xa9\\x99\\x99\\x99y\\x99\\xb7\\x99\\x99\\x99\\x99\\x99x\\x99\\x97\\x89\\xa8\\x7f\\xf8\\xffwf\\x7f\\xff\\x82_\\xf1\\x81U922\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U922\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB4\\xd6\\xe8\\xd7\\xa6',\n      b'\\xf1\\x87LDMVBN780576KF37\\x98\\x87hv\\x97x\\x97\\x89x\\x99\\xa7\\x89\\x88\\x99\\x98\\x89w\\x88\\x97x\\x98\\x7f\\xf7\\xff\\xba\\x88\\x8f\\xff\\x1e0\\xf1\\x81U922\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U922\\x00\\x00\\x00\\x00\\x00\\x00SLX4G38NB4\\xd6\\xe8\\xd7\\xa6',\n      b\"\\xf1\\x87LBLUFN622950KF36\\xa8\\x88\\x88\\x88\\x87w\\x87xh\\x99\\x96\\x89\\x88\\x99\\x98\\x89\\x88\\x99\\x98\\x89\\x87o\\xf6\\xff\\x98\\x88o\\xffx'\\xf1\\x81U891\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  U891\\x00\\x00\\x00\\x00\\x00\\x00SLX2G38NB3\\xd1\\xc3\\xf8\\xa8\",\n    ],\n  },\n  CAR.VELOSTER: {\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00JS__ SCC H-CUP      1.00 1.02 95650-J3200         ',\n      b'\\xf1\\x00JS__ SCC HNCUP      1.00 1.02 95650-J3100         ',\n    ],\n    (Ecu.esp, 0x7d1, None): [b'\\xf1\\x00\\x00\\x00\\x00\\x00\\x00\\x00', ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x01TJS-JNU06F200H0A',\n      b'\\x01TJS-JDK06F200H0A',\n    ],\n    (Ecu.eps, 0x7d4, None): [b'\\xf1\\x00JSL MDPS C 1.00 1.03 56340-J3000 8308', ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00JS  LKAS AT USA LHD 1.00 1.02 95740-J3000 K32',\n      b'\\xf1\\x00JS  LKAS AT KOR LHD 1.00 1.03 95740-J3000 K33',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x816U2V8051\\x00\\x00\\xf1\\x006U2V0_C2\\x00\\x006U2V8051\\x00\\x00DJS0T16NS1\\xba\\x02\\xb8\\x80',\n      b'\\xf1\\x816U2V8051\\x00\\x00\\xf1\\x006U2V0_C2\\x00\\x006U2V8051\\x00\\x00DJS0T16NS1\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x816U2V8051\\x00\\x00\\xf1\\x006U2V0_C2\\x00\\x006U2V8051\\x00\\x00DJS0T16KS2\\016\\xba\\036\\xa2',\n    ],\n  },\n  CAR.GENESIS_G70: {\n    (Ecu.fwdRadar, 0x7d0, None): [b'\\xf1\\x00IK__ SCC F-CUP      1.00 1.02 96400-G9100         \\xf1\\xa01.02', ],\n    (Ecu.engine, 0x7e0, None): [b'\\xf1\\x81640F0051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00', ],\n    (Ecu.eps, 0x7d4, None): [b'\\xf1\\x00IK  MDPS R 1.00 1.06 57700-G9420 4I4VL106', ],\n    (Ecu.fwdCamera, 0x7c4, None): [b'\\xf1\\x00IK  MFC  AT USA LHD 1.00 1.01 95740-G9000 170920', ],\n    (Ecu.transmission, 0x7e1, None): [b'\\xf1\\x87VDJLT17895112DN4\\x88fVf\\x99\\x88\\x88\\x88\\x87fVe\\x88vhwwUFU\\x97eFex\\x99\\xff\\xb7\\x82\\xf1\\x81E25\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00bcsh8p54  E25\\x00\\x00\\x00\\x00\\x00\\x00\\x00SIK0T33NB2\\x11\\x1am\\xda', ],\n  },\n  CAR.KONA: {\n    (Ecu.fwdRadar, 0x7d0, None): [b'\\xf1\\x00OS__ SCC F-CUP      1.00 1.00 95655-J9200         \\xf1\\xa01.00', ],\n    (Ecu.esp, 0x7d1, None): [b'\\xf1\\x816V5RAK00018.ELF\\xf1\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\xa01.05', ],\n    (Ecu.engine, 0x7e0, None): [b'\"\\x01TOS-0NU06F301J02', ],\n    (Ecu.eps, 0x7d4, None): [b'\\xf1\\x00OS  MDPS C 1.00 1.05 56310J9030\\x00 4OSDC105', ],\n    (Ecu.fwdCamera, 0x7c4, None): [b'\\xf1\\x00OS9 LKAS AT USA LHD 1.00 1.00 95740-J9300 g21', ],\n    (Ecu.transmission, 0x7e1, None): [b'\\xf1\\x816U2VE051\\x00\\x00\\xf1\\x006U2V0_C2\\x00\\x006U2VE051\\x00\\x00DOS4T16NS3\\x00\\x00\\x00\\x00', ],\n  },\n  CAR.KIA_CEED:  {\n    (Ecu.fwdRadar, 0x7D0, None): [b'\\xf1\\000CD__ SCC F-CUP      1.00 1.02 99110-J7000         ', ],\n    (Ecu.esp, 0x7D4, None): [b'\\xf1\\000CD  MDPS C 1.00 1.06 56310-XX000 4CDEC106', ],\n    (Ecu.fwdCamera, 0x7C4, None): [b'\\xf1\\000CD  LKAS AT EUR LHD 1.00 1.01 99211-J7000 B40', ],\n    (Ecu.engine, 0x7E0, None): [b'\\001TCD-JECU4F202H0K', ],\n    (Ecu.transmission, 0x7E1, None): [b'\\xf1\\x816U2V7051\\000\\000\\xf1\\0006U2V0_C2\\000\\0006U2V7051\\000\\000DCD0T14US1\\000\\000\\000\\000', ],\n    (Ecu.esp, 0x7D1, None): [b'\\xf1\\000CD ESC \\003 102\\030\\b\\005 58920-J7350', ],\n  },\n  CAR.KIA_FORTE: {\n    (Ecu.eps, 0x7D4, None): [\n      b'\\xf1\\x00BD  MDPS C 1.00 1.08 56310M6300\\x00 4BDDC108',\n    ],\n    (Ecu.fwdCamera, 0x7C4, None): [\n      b'\\xf1\\x00BD  LKAS AT USA LHD 1.00 1.04 95740-M6000 J33',\n    ],\n    (Ecu.fwdRadar, 0x7D0, None): [\n      b'\\xf1\\x00BD__ SCC H-CUP      1.00 1.02 99110-M6000         \\xf1\\xa01.02',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x01TBDM1NU06F200H01',\n    ],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x816VGRAH00018.ELF\\xf1\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\xa01.04',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b\"\\xf1\\x816U2VC051\\x00\\x00\\xf1\\x006U2V0_C2\\x00\\x006U2VC051\\x00\\x00DBD0T16SS0\\xcf\\x1e'\\xc3\",\n    ],\n  },\n  CAR.KONA_EV: {\n    (Ecu.esp, 0x7D1, None): [\n      b'\\xf1\\x00OS IEB \\r 105\\x18\\t\\x18 58520-K4000\\xf1\\xa01.05',\n      b'\\xf1\\x00OS IEB \\x01 212 \\x11\\x13 58520-K4000\\xf1\\xa02.12',\n      b'\\xf1\\x00OS IEB \\x02 212 \\x11\\x13 58520-K4000\\xf1\\xa02.12',\n      b'\\xf1\\x00OS IEB \\x03 210 \\x02\\x14 58520-K4000\\xf1\\xa02.10',\n      b'\\xf1\\x00OS IEB \\x03 212 \\x11\\x13 58520-K4000\\xf1\\xa02.12',\n    ],\n    (Ecu.fwdCamera, 0x7C4, None): [\n      b'\\xf1\\x00OE2 LKAS AT EUR LHD 1.00 1.00 95740-K4200 200',\n      b'\\xf1\\x00OSE LKAS AT EUR LHD 1.00 1.00 95740-K4100 W40',\n      b'\\xf1\\x00OSE LKAS AT EUR RHD 1.00 1.00 95740-K4100 W40',\n      b'\\xf1\\x00OSE LKAS AT KOR LHD 1.00 1.00 95740-K4100 W40',\n      b'\\xf1\\x00OSE LKAS AT USA LHD 1.00 1.00 95740-K4300 W50',\n    ],\n    (Ecu.eps, 0x7D4, None): [\n      b'\\xf1\\x00OS  MDPS C 1.00 1.03 56310/K4550 4OEDC103',\n      b'\\xf1\\x00OS  MDPS C 1.00 1.04 56310K4000\\x00 4OEDC104',\n      b'\\xf1\\x00OS  MDPS C 1.00 1.04 56310K4050\\x00 4OEDC104',\n    ],\n    (Ecu.fwdRadar, 0x7D0, None): [\n      b'\\xf1\\x00OSev SCC F-CUP      1.00 1.00 99110-K4000         \\xf1\\xa01.00',\n      b'\\xf1\\x00OSev SCC F-CUP      1.00 1.00 99110-K4100         \\xf1\\xa01.00',\n      b'\\xf1\\x00OSev SCC F-CUP      1.00 1.01 99110-K4000         \\xf1\\xa01.01',\n      b'\\xf1\\x00OSev SCC FNCUP      1.00 1.01 99110-K4000         \\xf1\\xa01.01',\n    ],\n  },\n  CAR.KIA_NIRO_EV: {\n    (Ecu.fwdRadar, 0x7D0, None): [\n      b'\\xf1\\x00DEev SCC F-CUP      1.00 1.00 99110-Q4000         ',\n      b'\\xf1\\x00DEev SCC F-CUP      1.00 1.00 99110-Q4000         \\xf1\\xa01.00',\n      b'\\xf1\\x00DEev SCC F-CUP      1.00 1.03 96400-Q4100         \\xf1\\xa01.03',\n      b'\\xf1\\x00OSev SCC F-CUP      1.00 1.01 99110-K4000         \\xf1\\xa01.01',\n      b'\\xf1\\x8799110Q4000\\xf1\\x00DEev SCC F-CUP      1.00 1.00 99110-Q4000         \\xf1\\xa01.00',\n      b'\\xf1\\x8799110Q4100\\xf1\\x00DEev SCC F-CUP      1.00 1.00 99110-Q4100         \\xf1\\xa01.00',\n      b'\\xf1\\x8799110Q4500\\xf1\\000DEev SCC F-CUP      1.00 1.00 99110-Q4500         \\xf1\\xa01.00',\n    ],\n    (Ecu.esp, 0x7D1, None): [\n      b'\\xf1\\x00OS IEB \\r 212 \\x11\\x13 58520-K4000\\xf1\\xa02.12',\n      b'\\xf1\\x00OS IEB \\r 212 \\x11\\x13 58520-K4000',\n      b'\\xf1\\xa01.06',\n      b'\\xf1\\xa01.07',\n    ],\n    (Ecu.eps, 0x7D4, None): [\n      b'\\xf1\\x00DE  MDPS C 1.00 1.05 56310Q4000\\x00 4DEEC105',\n      b'\\xf1\\x00DE  MDPS C 1.00 1.05 56310Q4100\\x00 4DEEC105',\n      b'\\xf1\\x00OS  MDPS C 1.00 1.04 56310K4050\\x00 4OEDC104',\n    ],\n    (Ecu.fwdCamera, 0x7C4, None): [\n      b'\\xf1\\000DEE MFC  AT EUR LHD 1.00 1.00 99211-Q4100 200706',\n      b'\\xf1\\x00DEE MFC  AT EUR LHD 1.00 1.00 99211-Q4000 191211',\n      b'\\xf1\\x00DEE MFC  AT USA LHD 1.00 1.00 99211-Q4000 191211',\n      b'\\xf1\\x00DEE MFC  AT USA LHD 1.00 1.03 95740-Q4000 180821',\n      b'\\xf1\\x00OSE LKAS AT EUR LHD 1.00 1.00 95740-K4100 W40',\n    ],\n  },\n  CAR.KIA_NIRO_HEV: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x816H6F4051\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b\"\\xf1\\x816U3J2051\\000\\000\\xf1\\0006U3H0_C2\\000\\0006U3J2051\\000\\000PDE0G16NS2\\xf4\\'\\\\\\x91\",\n      b'\\xf1\\x816U3J2051\\000\\000\\xf1\\0006U3H0_C2\\000\\0006U3J2051\\000\\000PDE0G16NS2\\000\\000\\000\\000',\n    ],\n    (Ecu.eps, 0x7D4, None): [\n      b'\\xf1\\000DE  MDPS C 1.00 1.09 56310G5301\\000 4DEHC109',\n    ],\n    (Ecu.fwdCamera, 0x7C4, None): [\n      b'\\xf1\\000DEP MFC  AT USA LHD 1.00 1.01 95740-G5010 170424',\n    ],\n    (Ecu.fwdRadar, 0x7D0, None): [\n      b'\\xf1\\000DEhe SCC H-CUP      1.01 1.02 96400-G5100         ',\n    ],\n  },\n  CAR.KIA_NIRO_HEV_2021: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x816H6G5051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x816U3J9051\\x00\\x00\\xf1\\x006U3H1_C2\\x00\\x006U3J9051\\x00\\x00HDE0G16NL3\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x816U3J9051\\x00\\x00\\xf1\\x006U3H1_C2\\x00\\x006U3J9051\\x00\\x00HDE0G16NL3\\xb9\\xd3\\xfaW',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00DE  MDPS C 1.00 1.01 56310G5520\\x00 4DEPC101',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00DEH MFC  AT USA LHD 1.00 1.07 99211-G5000 201221',\n    ],\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00DEhe SCC FHCUP      1.00 1.00 99110-G5600         ',\n    ],\n  },\n  CAR.KIA_SELTOS: {\n    (Ecu.fwdRadar, 0x7d0, None): [b'\\xf1\\x8799110Q5100\\xf1\\000SP2_ SCC FHCUP      1.01 1.05 99110-Q5100         \\xf1\\xa01.05',],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x8758910-Q5450\\xf1\\000SP ESC \\a 101\\031\\t\\005 58910-Q5450\\xf1\\xa01.01',\n      b'\\xf1\\x8758910-Q5450\\xf1\\000SP ESC \\t 101\\031\\t\\005 58910-Q5450\\xf1\\xa01.01',\n     ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x81616D2051\\000\\000\\000\\000\\000\\000\\000\\000',\n      b'\\xf1\\x81616D5051\\000\\000\\000\\000\\000\\000\\000\\000',\n      b'\\001TSP2KNL06F100J0K',\n      b'\\001TSP2KNL06F200J0K',\n     ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\000SP2 MDPS C 1.00 1.04 56300Q5200          ',\n      b'\\xf1\\000SP2 MDPS C 1.01 1.05 56300Q5200          ',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\000SP2 MFC  AT USA LHD 1.00 1.04 99210-Q5000 191114',\n      b'\\xf1\\000SP2 MFC  AT USA LHD 1.00 1.05 99210-Q5000 201012',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x87CZLUB49370612JF7h\\xa8y\\x87\\x99\\xa7hv\\x99\\x97fv\\x88\\x87x\\x89x\\x96O\\xff\\x88\\xff\\xff\\xff.@\\xf1\\x816V2C2051\\000\\000\\xf1\\0006V2B0_C2\\000\\0006V2C2051\\000\\000CSP4N20NS3\\000\\000\\000\\000',\n      b'\\xf1\\x87954A22D200\\xf1\\x81T01950A1  \\xf1\\000T0190XBL  T01950A1  DSP2T16X4X950NS6\\xd30\\xa5\\xb9',\n      b'\\xf1\\x87954A22D200\\xf1\\x81T01950A1  \\xf1\\000T0190XBL  T01950A1  DSP2T16X4X950NS8\\r\\xfe\\x9c\\x8b',\n     ],\n  },\n  CAR.KIA_OPTIMA: {\n    (Ecu.fwdRadar, 0x7d0, None): [b'\\xf1\\x00JF__ SCC F-CUP      1.00 1.00 96400-D4110         '],\n    (Ecu.esp, 0x7d1, None): [b'\\xf1\\x00JF ESC \\v 11 \\x18\\x030 58920-D5180',],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x01TJFAJNU06F201H03',\n      b'\\xf1\\x89F1JF600AISEIU702\\xf1\\x82F1JF600AISEIU702',\n    ],\n    (Ecu.eps, 0x7d4, None): [b'\\xf1\\x00TM  MDPS C 1.00 1.00 56340-S2000 8409'],\n    (Ecu.fwdCamera, 0x7c4, None): [b'\\xf1\\x00JFA LKAS AT USA LHD 1.00 1.02 95895-D5000 h31'],\n    (Ecu.transmission, 0x7e1, None): [b'\\xf1\\x816U2V8051\\x00\\x00\\xf1\\x006U2V0_C2\\x00\\x006U2V8051\\x00\\x00DJF0T16NL0\\t\\xd2GW'],\n  },\n  CAR.ELANTRA_2021: {\n    (Ecu.fwdRadar, 0x7d0, None): [b'\\xf1\\x00CN7_ SCC FHCUP      1.00 1.01 99110-AA000         '],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x87\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\xf1\\x00CN7 MDPS C 1.00 1.06 \\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00 4CNDC106\\xf1\\xa01.06',\n      b'\\xf1\\x8756310AA050\\x00\\xf1\\x00CN7 MDPS C 1.00 1.06 56310AA050\\x00 4CNDC106\\xf1\\xa01.06',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [b'\\xf1\\x00CN7 MFC  AT USA LHD 1.00 1.00 99210-AB000 200819'],\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x8758910-AB800\\xf1\\x00CN ESC \\t 101 \\x10\\x03 58910-AB800\\xf1\\xa01.01',\n      b'\\xf1\\x00CN ESC \\t 101 \\x10\\x03 58910-AB800',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x00HT6WA280BLHT6VA640A1CCN0N20NS5\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\xf1\\x00HT6WA280BLHT6VA640A1CCN0N20NS5\\x00\\x00\\x00\\x00\\x00\\x00\\xe8\\xba\\xce\\xfa',\n      b'\\xf1\\x87CXMQFM2135005JB2E\\xb9\\x89\\x98W\\xa9y\\x97h\\xa9\\x98\\x99wxvwh\\x87\\177\\xffx\\xff\\xff\\xff,,\\xf1\\x89HT6VA640A1\\xf1\\x82CCN0N20NS5\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [b'\\xf1\\x82CNCWD0AMFCXCSFFA'],\n  },\n  CAR.ELANTRA_HEV_2021: {\n    (Ecu.fwdCamera, 0x7c4, None) : [\n      b'\\xf1\\000CN7HMFC  AT USA LHD 1.00 1.03 99210-AA000 200819'\n    ],\n    (Ecu.fwdRadar, 0x7d0, None) : [\n      b'\\xf1\\000CNhe SCC FHCUP      1.00 1.01 99110-BY000         '\n    ],\n    (Ecu.eps, 0x7d4, None) :[\n      b'\\xf1\\x8756310/BY050\\xf1\\000CN7 MDPS C 1.00 1.02 56310/BY050 4CNHC102\\xf1\\xa01.02'\n    ],\n    (Ecu.transmission, 0x7e1, None) :[\n      b'\\xf1\\x816U3K3051\\000\\000\\xf1\\0006U3L0_C2\\000\\0006U3K3051\\000\\000HCN0G16NS0\\xb9?A\\xaa',\n      b'\\xf1\\x816U3K3051\\000\\000\\xf1\\0006U3L0_C2\\000\\0006U3K3051\\000\\000HCN0G16NS0\\000\\000\\000\\000'\n    ],\n    (Ecu.engine, 0x7e0, None) : [\n      b'\\xf1\\x816H6G5051\\000\\000\\000\\000\\000\\000\\000\\000'\n    ]\n  },\n  CAR.KONA_HEV: {\n    (Ecu.esp, 0x7d1, None): [\n      b'\\xf1\\x00OS IEB \\x01 104 \\x11  58520-CM000\\xf1\\xa01.04',\n    ],\n    (Ecu.fwdRadar, 0x7d0, None): [\n      b'\\xf1\\x00OShe SCC FNCUP      1.00 1.01 99110-CM000         \\xf1\\xa01.01',\n    ],\n    (Ecu.eps, 0x7d4, None): [\n      b'\\xf1\\x00OS  MDPS C 1.00 1.00 56310CM030\\x00 4OHDC100',\n    ],\n    (Ecu.fwdCamera, 0x7c4, None): [\n      b'\\xf1\\x00OSH LKAS AT KOR LHD 1.00 1.01 95740-CM000 l31',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x816U3J9051\\x00\\x00\\xf1\\x006U3H1_C2\\x00\\x006U3J9051\\x00\\x00HOS0G16DS1\\x16\\xc7\\xb0\\xd9',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x816H6F6051\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ]\n  },\n  CAR.SONATA_HYBRID: {\n    (Ecu.fwdRadar, 0x7d0, None): [b'\\xf1\\000DNhe SCC FHCUP      1.00 1.02 99110-L5000         ',],\n    (Ecu.eps, 0x7d4, None): [b'\\xf1\\x8756310-L5500\\xf1\\000DN8 MDPS C 1.00 1.02 56310-L5500 4DNHC102\\xf1\\xa01.02',],\n    (Ecu.fwdCamera, 0x7c4, None): [b'\\xf1\\000DN8HMFC  AT USA LHD 1.00 1.04 99211-L1000 191016',],\n    (Ecu.transmission, 0x7e1, None): [b'\\xf1\\000PSBG2323  E09\\000\\000\\000\\000\\000\\000\\000TDN2H20SA5\\x97R\\x88\\x9e',],\n    (Ecu.engine, 0x7e0, None): [b'\\xf1\\x87391162J012\\xf1\\xa0000R',],\n  },\n}\n\nCHECKSUM = {\n  \"crc8\": [CAR.SANTA_FE, CAR.SONATA, CAR.PALISADE, CAR.KIA_SELTOS, CAR.ELANTRA_2021, CAR.ELANTRA_HEV_2021, CAR.SONATA_HYBRID],\n  \"6B\": [CAR.KIA_SORENTO, CAR.HYUNDAI_GENESIS],\n}\n\nFEATURES = {\n  # which message has the gear\n  \"use_cluster_gears\": set([CAR.ELANTRA, CAR.ELANTRA_GT_I30, CAR.KONA]),\n  \"use_tcu_gears\": set([CAR.KIA_OPTIMA, CAR.SONATA_LF, CAR.VELOSTER]),\n  \"use_elect_gears\": set([CAR.KIA_NIRO_EV, CAR.KIA_NIRO_HEV, CAR.KIA_NIRO_HEV_2021, CAR.KIA_OPTIMA_H, CAR.IONIQ_EV_LTD, CAR.KONA_EV, CAR.IONIQ, CAR.IONIQ_EV_2020, CAR.IONIQ_PHEV, CAR.ELANTRA_HEV_2021,CAR.SONATA_HYBRID, CAR.KONA_HEV]),\n\n  # these cars use the FCA11 message for the AEB and FCW signals, all others use SCC12\n  \"use_fca\": set([CAR.SONATA, CAR.SONATA_HYBRID, CAR.ELANTRA, CAR.ELANTRA_2021, CAR.ELANTRA_HEV_2021, CAR.ELANTRA_GT_I30, CAR.KIA_STINGER, CAR.IONIQ, CAR.IONIQ_EV_2020, CAR.IONIQ_PHEV, CAR.KONA_EV, CAR.KIA_FORTE, CAR.KIA_NIRO_EV, CAR.PALISADE, CAR.GENESIS_G70, CAR.KONA, CAR.SANTA_FE, CAR.KIA_SELTOS, CAR.KONA_HEV]),\n}\n\nHYBRID_CAR = set([CAR.IONIQ_PHEV, CAR.ELANTRA_HEV_2021, CAR.KIA_NIRO_HEV, CAR.KIA_NIRO_HEV_2021, CAR.SONATA_HYBRID, CAR.KONA_HEV])  # these cars use a different gas signal\nEV_CAR = set([CAR.IONIQ_EV_2020, CAR.IONIQ_EV_LTD, CAR.IONIQ, CAR.KONA_EV, CAR.KIA_NIRO_EV])\n\nDBC = {\n  CAR.ELANTRA: dbc_dict('hyundai_kia_generic', None),\n  CAR.ELANTRA_2021: dbc_dict('hyundai_kia_generic', None),\n  CAR.ELANTRA_HEV_2021: dbc_dict('hyundai_kia_generic', None),\n  CAR.ELANTRA_GT_I30: dbc_dict('hyundai_kia_generic', None),\n  CAR.GENESIS_G70: dbc_dict('hyundai_kia_generic', None),\n  CAR.GENESIS_G80: dbc_dict('hyundai_kia_generic', None),\n  CAR.GENESIS_G90: dbc_dict('hyundai_kia_generic', None),\n  CAR.HYUNDAI_GENESIS: dbc_dict('hyundai_kia_generic', None),\n  CAR.IONIQ_PHEV: dbc_dict('hyundai_kia_generic', None),\n  CAR.IONIQ_EV_2020: dbc_dict('hyundai_kia_generic', None),\n  CAR.IONIQ_EV_LTD: dbc_dict('hyundai_kia_generic', None),\n  CAR.IONIQ: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_FORTE: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_NIRO_EV: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_NIRO_HEV: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_NIRO_HEV_2021: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_OPTIMA: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_OPTIMA_H: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_SELTOS: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_SORENTO: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_STINGER: dbc_dict('hyundai_kia_generic', None),\n  CAR.KONA: dbc_dict('hyundai_kia_generic', None),\n  CAR.KONA_EV: dbc_dict('hyundai_kia_generic', None),\n  CAR.KONA_HEV: dbc_dict('hyundai_kia_generic', None),\n  CAR.SANTA_FE: dbc_dict('hyundai_kia_generic', None),\n  CAR.SONATA: dbc_dict('hyundai_kia_generic', None),\n  CAR.SONATA_LF: dbc_dict('hyundai_kia_generic', None),\n  CAR.PALISADE: dbc_dict('hyundai_kia_generic', None),\n  CAR.VELOSTER: dbc_dict('hyundai_kia_generic', None),\n  CAR.KIA_CEED: dbc_dict('hyundai_kia_generic', None),\n  CAR.SONATA_HYBRID: dbc_dict('hyundai_kia_generic', None),\n}\n\nSTEER_THRESHOLD = 150\n"
  },
  {
    "path": "selfdrive/car/interfaces.py",
    "content": "import os\nimport time\nfrom typing import Dict\n\nfrom cereal import car\nfrom common.kalman.simple_kalman import KF1D\nfrom common.realtime import DT_CTRL\nfrom selfdrive.car import gen_empty_fingerprint\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.controls.lib.drive_helpers import V_CRUISE_MAX\nfrom selfdrive.controls.lib.events import Events\nfrom selfdrive.controls.lib.vehicle_model import VehicleModel\n\nGearShifter = car.CarState.GearShifter\nEventName = car.CarEvent.EventName\n\n# WARNING: this value was determined based on the model's training distribution,\n#          model predictions above this speed can be unpredictable\nMAX_CTRL_SPEED = (V_CRUISE_MAX + 4) * CV.KPH_TO_MS  # 135 + 4 = 86 mph\nACCEL_MAX = 2.0\nACCEL_MIN = -3.5\n\n\n# generic car and radar interfaces\n\n\nclass CarInterfaceBase():\n  def __init__(self, CP, CarController, CarState):\n    self.CP = CP\n    self.VM = VehicleModel(CP)\n\n    self.frame = 0\n    self.steer_warning = 0\n    self.steering_unpressed = 0\n    self.low_speed_alert = False\n\n    self.dragonconf = None\n\n    if CarState is not None:\n      self.CS = CarState(CP)\n      self.cp = self.CS.get_can_parser(CP)\n      self.cp_cam = self.CS.get_cam_can_parser(CP)\n      self.cp_body = self.CS.get_body_can_parser(CP)\n\n    self.CC = None\n    if CarController is not None:\n      self.CC = CarController(self.cp.dbc_name, CP, self.VM)\n\n    self.dragonconf = None\n\n  @staticmethod\n  def get_pid_accel_limits(CP, current_speed, cruise_speed):\n    return ACCEL_MIN, ACCEL_MAX\n\n  @staticmethod\n  def calc_accel_override(a_ego, a_target, v_ego, v_target):\n    return 1.\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    raise NotImplementedError\n\n  @staticmethod\n  def init(CP, logcan, sendcan):\n    pass\n\n  # returns a set of default params to avoid repetition in car specific params\n  @staticmethod\n  def get_std_params(candidate, fingerprint):\n    ret = car.CarParams.new_message()\n    ret.carFingerprint = candidate\n\n    # standard ALC params\n    ret.steerControlType = car.CarParams.SteerControlType.torque\n    ret.steerMaxBP = [0.]\n    ret.steerMaxV = [1.]\n    ret.minSteerSpeed = 0.\n\n    ret.pcmCruise = True     # openpilot's state is tied to the PCM's cruise state on most cars\n    ret.minEnableSpeed = -1. # enable is done by stock ACC, so ignore this\n    ret.steerRatioRear = 0.  # no rear steering, at least on the listed cars aboveA\n    ret.openpilotLongitudinalControl = False\n    ret.startAccel = 0.0\n    ret.minSpeedCan = 0.3\n    ret.stoppingDecelRate = 0.8 # brake_travel/s while trying to stop\n    ret.startingAccelRate = 3.2 # brake_travel/s while releasing on restart\n    ret.stoppingControl = True\n    ret.longitudinalTuning.deadzoneBP = [0.]\n    ret.longitudinalTuning.deadzoneV = [0.]\n    ret.longitudinalTuning.kpBP = [0.]\n    ret.longitudinalTuning.kpV = [1.]\n    ret.longitudinalTuning.kiBP = [0.]\n    ret.longitudinalTuning.kiV = [1.]\n    ret.longitudinalActuatorDelay = 0.15\n    return ret\n\n  # returns a car.CarState, pass in car.CarControl\n  def update(self, c, can_strings, dragonconf):\n    raise NotImplementedError\n\n  # return sendcan, pass in a car.CarControl\n  def apply(self, c):\n    raise NotImplementedError\n\n  def create_common_events(self, cs_out, extra_gears=None, gas_resume_speed=-1, pcm_enable=True):\n    events = Events()\n\n    if cs_out.doorOpen:\n      events.add(EventName.doorOpen)\n    if cs_out.seatbeltUnlatched:\n      events.add(EventName.seatbeltNotLatched)\n    if self.dragonconf.dpGearCheck and cs_out.gearShifter not in (GearShifter.drive, GearShifter.sport, GearShifter.eco, GearShifter.low) and (extra_gears is None or\n         cs_out.gearShifter not in extra_gears):\n      events.add(EventName.wrongGear)\n    if cs_out.gearShifter == GearShifter.reverse:\n      events.add(EventName.reverseGear)\n    if not cs_out.cruiseState.available and not self.dragonconf.dpAtl:\n      events.add(EventName.wrongCarMode)\n    if cs_out.espDisabled:\n      events.add(EventName.espDisabled)\n    if cs_out.gasPressed and not self.dragonconf.dpAllowGas:\n      events.add(EventName.gasPressed)\n    if cs_out.stockFcw:\n      events.add(EventName.stockFcw)\n    if cs_out.stockAeb:\n      events.add(EventName.stockAeb)\n    if cs_out.vEgo > MAX_CTRL_SPEED and self.dragonconf.dpSpeedCheck:\n      events.add(EventName.speedTooHigh)\n    if cs_out.cruiseState.nonAdaptive and not self.dragonconf.dpAtl:\n      events.add(EventName.wrongCruiseMode)\n\n    self.steer_warning = self.steer_warning + 1 if cs_out.steerWarning else 0\n    self.steering_unpressed = 0 if cs_out.steeringPressed else self.steering_unpressed + 1\n\n    # Handle permanent and temporary steering faults\n    if (cs_out.leftBlinker or cs_out.rightBlinker) and self.dragonconf.dpLateralMode == 0:\n      events.add(EventName.manualSteeringRequiredBlinkersOn)\n    elif cs_out.steerError:\n      events.add(EventName.steerUnavailable)\n    elif cs_out.steerWarning:\n      # only escalate to the harsher alert after the condition has\n      # persisted for 0.5s and we're certain that the user isn't overriding\n      if self.steering_unpressed > int(0.5/DT_CTRL) and self.steer_warning > int(0.5/DT_CTRL):\n        events.add(EventName.steerTempUnavailable)\n      else:\n        events.add(EventName.steerTempUnavailableSilent)\n\n    # Disable on rising edge of gas or brake. Also disable on brake when speed > 0.\n    # Optionally allow to press gas at zero speed to resume.\n    # e.g. Chrysler does not spam the resume button yet, so resuming with gas is handy. FIXME!\n    if self.dragonconf.dpAtl:\n      pass\n    elif self.dragonconf.dpAllowGas:\n      if cs_out.brakePressed and (not self.CS.out.brakePressed or not cs_out.standstill):\n        events.add(EventName.pedalPressed)\n    else:\n      if (cs_out.gasPressed and (not self.CS.out.gasPressed) and cs_out.vEgo > gas_resume_speed) or \\\n              (cs_out.brakePressed and (not self.CS.out.brakePressed or not cs_out.standstill)):\n        events.add(EventName.pedalPressed)\n\n    # we engage when pcm is active (rising edge)\n    if pcm_enable:\n      if cs_out.cruiseState.enabled and not self.CS.out.cruiseState.enabled:\n        events.add(EventName.pcmEnable)\n      elif not cs_out.cruiseState.enabled:\n        events.add(EventName.pcmDisable)\n\n    return events\n\n\nclass RadarInterfaceBase():\n  def __init__(self, CP):\n    self.pts = {}\n    self.delay = 0\n    self.radar_ts = CP.radarTimeStep\n    self.no_radar_sleep = 'NO_RADAR_SLEEP' in os.environ\n\n  def update(self, can_strings):\n    ret = car.RadarData.new_message()\n    if not self.no_radar_sleep:\n      time.sleep(self.radar_ts)  # radard runs on RI updates\n    return ret\n\n\nclass CarStateBase:\n  def __init__(self, CP):\n    self.CP = CP\n    self.car_fingerprint = CP.carFingerprint\n    self.out = car.CarState.new_message()\n\n    self.cruise_buttons = 0\n    self.left_blinker_cnt = 0\n    self.right_blinker_cnt = 0\n    self.left_blinker_prev = False\n    self.right_blinker_prev = False\n\n    # Q = np.matrix([[10.0, 0.0], [0.0, 100.0]])\n    # R = 1e3\n    self.v_ego_kf = KF1D(x0=[[0.0], [0.0]],\n                         A=[[1.0, DT_CTRL], [0.0, 1.0]],\n                         C=[1.0, 0.0],\n                         K=[[0.12287673], [0.29666309]])\n\n  def update_speed_kf(self, v_ego_raw):\n    if abs(v_ego_raw - self.v_ego_kf.x[0][0]) > 2.0:  # Prevent large accelerations when car starts at non zero speed\n      self.v_ego_kf.x = [[v_ego_raw], [0.0]]\n\n    v_ego_x = self.v_ego_kf.update(v_ego_raw)\n    return float(v_ego_x[0]), float(v_ego_x[1])\n\n  def update_blinker_from_lamp(self, blinker_time: int, left_blinker_lamp: bool, right_blinker_lamp: bool):\n    \"\"\"Update blinkers from lights. Enable output when light was seen within the last `blinker_time`\n    iterations\"\"\"\n    # TODO: Handle case when switching direction. Now both blinkers can be on at the same time\n    self.left_blinker_cnt = blinker_time if left_blinker_lamp else max(self.left_blinker_cnt - 1, 0)\n    self.right_blinker_cnt = blinker_time if right_blinker_lamp else max(self.right_blinker_cnt - 1, 0)\n    return self.left_blinker_cnt > 0, self.right_blinker_cnt > 0\n\n  def update_blinker_from_stalk(self, blinker_time: int, left_blinker_stalk: bool, right_blinker_stalk: bool):\n    \"\"\"Update blinkers from stalk position. When stalk is seen the blinker will be on for at least blinker_time,\n    or until the stalk is turned off, whichever is longer. If the opposite stalk direction is seen the blinker\n    is forced to the other side. On a rising edge of the stalk the timeout is reset.\"\"\"\n\n    if left_blinker_stalk:\n      self.right_blinker_cnt = 0\n      if not self.left_blinker_prev:\n        self.left_blinker_cnt = blinker_time\n\n    if right_blinker_stalk:\n      self.left_blinker_cnt = 0\n      if not self.right_blinker_prev:\n        self.right_blinker_cnt = blinker_time\n\n    self.left_blinker_cnt = max(self.left_blinker_cnt - 1, 0)\n    self.right_blinker_cnt = max(self.right_blinker_cnt - 1, 0)\n\n    self.left_blinker_prev = left_blinker_stalk\n    self.right_blinker_prev = right_blinker_stalk\n\n    return bool(left_blinker_stalk or self.left_blinker_cnt > 0), bool(right_blinker_stalk or self.right_blinker_cnt > 0)\n\n  @staticmethod\n  def parse_gear_shifter(gear: str) -> car.CarState.GearShifter:\n    d: Dict[str, car.CarState.GearShifter] = {\n        'P': GearShifter.park, 'R': GearShifter.reverse, 'N': GearShifter.neutral,\n        'E': GearShifter.eco, 'T': GearShifter.manumatic, 'D': GearShifter.drive,\n        'S': GearShifter.sport, 'L': GearShifter.low, 'B': GearShifter.brake\n    }\n    return d.get(gear, GearShifter.unknown)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    return None\n\n  @staticmethod\n  def get_body_can_parser(CP):\n    return None\n"
  },
  {
    "path": "selfdrive/car/isotp_parallel_query.py",
    "content": "import time\nfrom collections import defaultdict\nfrom functools import partial\nfrom typing import Optional\n\nimport cereal.messaging as messaging\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.boardd.boardd import can_list_to_can_capnp\nfrom panda.python.uds import CanClient, IsoTpMessage, FUNCTIONAL_ADDRS, get_rx_addr_for_tx_addr\n\n\nclass IsoTpParallelQuery:\n  def __init__(self, sendcan, logcan, bus, addrs, request, response, response_offset=0x8, functional_addr=False, debug=False):\n    self.sendcan = sendcan\n    self.logcan = logcan\n    self.bus = bus\n    self.request = request\n    self.response = response\n    self.debug = debug\n    self.functional_addr = functional_addr\n\n    self.real_addrs = []\n    for a in addrs:\n      if isinstance(a, tuple):\n        self.real_addrs.append(a)\n      else:\n        self.real_addrs.append((a, None))\n\n    self.msg_addrs = {tx_addr: get_rx_addr_for_tx_addr(tx_addr[0], rx_offset=response_offset) for tx_addr in self.real_addrs}\n    self.msg_buffer = defaultdict(list)\n\n  def rx(self):\n    \"\"\"Drain can socket and sort messages into buffers based on address\"\"\"\n    can_packets = messaging.drain_sock(self.logcan, wait_for_one=True)\n\n    for packet in can_packets:\n      for msg in packet.can:\n        if msg.src == self.bus:\n          if self.functional_addr:\n            if (0x7E8 <= msg.address <= 0x7EF) or (0x18DAF100 <= msg.address <= 0x18DAF1FF):\n              fn_addr = next(a for a in FUNCTIONAL_ADDRS if msg.address - a <= 32)\n              self.msg_buffer[fn_addr].append((msg.address, msg.busTime, msg.dat, msg.src))\n          elif msg.address in self.msg_addrs.values():\n            self.msg_buffer[msg.address].append((msg.address, msg.busTime, msg.dat, msg.src))\n\n  def _can_tx(self, tx_addr, dat, bus):\n    \"\"\"Helper function to send single message\"\"\"\n    msg = [tx_addr, 0, dat, bus]\n    self.sendcan.send(can_list_to_can_capnp([msg], msgtype='sendcan'))\n\n  def _can_rx(self, addr, sub_addr=None):\n    \"\"\"Helper function to retrieve message with specified address and subadress from buffer\"\"\"\n    keep_msgs = []\n\n    if sub_addr is None:\n      msgs = self.msg_buffer[addr]\n    else:\n      # Filter based on subadress\n      msgs = []\n      for m in self.msg_buffer[addr]:\n        first_byte = m[2][0]\n        if first_byte == sub_addr:\n          msgs.append(m)\n        else:\n          keep_msgs.append(m)\n\n    self.msg_buffer[addr] = keep_msgs\n    return msgs\n\n  def _drain_rx(self):\n    messaging.drain_sock(self.logcan)\n    self.msg_buffer = defaultdict(list)\n\n  def get_data(self, timeout):\n    self._drain_rx()\n\n    # Create message objects\n    msgs = {}\n    request_counter = {}\n    request_done = {}\n    for tx_addr, rx_addr in self.msg_addrs.items():\n      # rx_addr not set when using functional tx addr\n      id_addr = rx_addr or tx_addr[0]\n      sub_addr = tx_addr[1]\n\n      can_client = CanClient(self._can_tx, partial(self._can_rx, id_addr, sub_addr=sub_addr), tx_addr[0], rx_addr,\n                             self.bus, sub_addr=sub_addr, debug=self.debug)\n\n      max_len = 8 if sub_addr is None else 7\n\n      msg = IsoTpMessage(can_client, timeout=0, max_len=max_len, debug=self.debug)\n      msg.send(self.request[0])\n\n      msgs[tx_addr] = msg\n      request_counter[tx_addr] = 0\n      request_done[tx_addr] = False\n\n    results = {}\n    start_time = time.time()\n    while True:\n      self.rx()\n\n      if all(request_done.values()):\n        break\n\n      for tx_addr, msg in msgs.items():\n        dat: Optional[bytes] = msg.recv()\n\n        if not dat:\n          continue\n\n        counter = request_counter[tx_addr]\n        expected_response = self.response[counter]\n        response_valid = dat[:len(expected_response)] == expected_response\n\n        if response_valid:\n          if counter + 1 < len(self.request):\n            msg.send(self.request[counter + 1])\n            request_counter[tx_addr] += 1\n          else:\n            results[tx_addr] = dat[len(expected_response):]\n            request_done[tx_addr] = True\n        else:\n          request_done[tx_addr] = True\n          cloudlog.warning(f\"iso-tp query bad response: 0x{dat.hex()}\")\n\n      if time.time() - start_time > timeout:\n        break\n\n    return results\n"
  },
  {
    "path": "selfdrive/car/mazda/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/mazda/carcontroller.py",
    "content": "from selfdrive.car.mazda import mazdacan\nfrom selfdrive.car.mazda.values import CarControllerParams, Buttons\nfrom opendbc.can.packer import CANPacker\nfrom selfdrive.car import apply_std_steer_torque_limits\nfrom common.dp_common import common_controller_ctrl\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.apply_steer_last = 0\n    self.packer = CANPacker(dbc_name)\n    self.steer_rate_limited = False\n\n  def update(self, enabled, CS, frame, actuators, dragonconf):\n    \"\"\" Controls thread \"\"\"\n\n    can_sends = []\n\n    ### STEER ###\n\n    if enabled:\n      # calculate steer and also set limits due to driver torque\n      new_steer = int(round(actuators.steer * CarControllerParams.STEER_MAX))\n      apply_steer = apply_std_steer_torque_limits(new_steer, self.apply_steer_last,\n                                                  CS.out.steeringTorque, CarControllerParams)\n      self.steer_rate_limited = new_steer != apply_steer\n\n      if CS.out.standstill and frame % 5 == 0:\n        # Mazda Stop and Go requires a RES button (or gas) press if the car stops more than 3 seconds\n        # Send Resume button at 20hz if we're engaged at standstill to support full stop and go!\n        # TODO: improve the resume trigger logic by looking at actual radar data\n        can_sends.append(mazdacan.create_button_cmd(self.packer, CS.CP.carFingerprint, Buttons.RESUME))\n    else:\n      apply_steer = 0\n      self.steer_rate_limited = False\n      if CS.out.cruiseState.enabled and frame % 20 == 0:\n        # Cancel Stock ACC if it's enabled while OP is disengaged\n        # Send at a rate of 5hz until we sync with stock ACC state\n        can_sends.append(mazdacan.create_button_cmd(self.packer, CS.CP.carFingerprint, Buttons.CANCEL))\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_steer = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_steer, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    self.apply_steer_last = apply_steer\n\n    can_sends.append(mazdacan.create_steering_control(self.packer, CS.CP.carFingerprint,\n                                                      frame, apply_steer, CS.cam_lkas))\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/mazda/carstate.py",
    "content": "from cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom opendbc.can.can_define import CANDefine\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.interfaces import CarStateBase\nfrom selfdrive.car.mazda.values import DBC, LKAS_LIMITS, GEN1\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n    self.shifter_values = can_define.dv[\"GEAR\"][\"GEAR\"]\n\n    self.cruise_speed = 0\n    self.acc_active_last = False\n    self.low_speed_lockout = True\n    self.low_speed_alert = False\n    self.lkas_allowed = False\n\n  def update(self, cp, cp_cam):\n\n    ret = car.CarState.new_message()\n    ret.wheelSpeeds.fl = cp.vl[\"WHEEL_SPEEDS\"][\"FL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = cp.vl[\"WHEEL_SPEEDS\"][\"FR\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = cp.vl[\"WHEEL_SPEEDS\"][\"RL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = cp.vl[\"WHEEL_SPEEDS\"][\"RR\"] * CV.KPH_TO_MS\n    ret.vEgoRaw = (ret.wheelSpeeds.fl + ret.wheelSpeeds.fr + ret.wheelSpeeds.rl + ret.wheelSpeeds.rr) / 4.\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n\n    # Match panda speed reading\n    speed_kph = cp.vl[\"ENGINE_DATA\"][\"SPEED\"]\n    ret.standstill = speed_kph < .1\n\n    can_gear = int(cp.vl[\"GEAR\"][\"GEAR\"])\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(can_gear, None))\n\n    ret.leftBlinker = cp.vl[\"BLINK_INFO\"][\"LEFT_BLINK\"] == 1\n    ret.rightBlinker = cp.vl[\"BLINK_INFO\"][\"RIGHT_BLINK\"] == 1\n\n    ret.steeringAngleDeg = cp.vl[\"STEER\"][\"STEER_ANGLE\"]\n    ret.steeringTorque = cp.vl[\"STEER_TORQUE\"][\"STEER_TORQUE_SENSOR\"]\n    ret.steeringPressed = abs(ret.steeringTorque) > LKAS_LIMITS.STEER_THRESHOLD\n\n    ret.steeringTorqueEps = cp.vl[\"STEER_TORQUE\"][\"STEER_TORQUE_MOTOR\"]\n    ret.steeringRateDeg = cp.vl[\"STEER_RATE\"][\"STEER_ANGLE_RATE\"]\n\n    ret.brakePressed = cp.vl[\"PEDALS\"][\"BRAKE_ON\"] == 1\n    ret.brake = cp.vl[\"BRAKE\"][\"BRAKE_PRESSURE\"]\n\n    ret.seatbeltUnlatched = cp.vl[\"SEATBELT\"][\"DRIVER_SEATBELT\"] == 0\n    ret.doorOpen = any([cp.vl[\"DOORS\"][\"FL\"], cp.vl[\"DOORS\"][\"FR\"],\n                        cp.vl[\"DOORS\"][\"BL\"], cp.vl[\"DOORS\"][\"BR\"]])\n\n    ret.gas = cp.vl[\"ENGINE_DATA\"][\"PEDAL_GAS\"]\n    ret.gasPressed = ret.gas > 0\n\n    ret.leftBlindspot = cp.vl[\"BSM\"][\"LEFT_BS1\"] == 1\n    ret.rightBlindspot = cp.vl[\"BSM\"][\"RIGHT_BS1\"] == 1\n\n    # LKAS is enabled at 52kph going up and disabled at 45kph going down\n    if speed_kph > LKAS_LIMITS.ENABLE_SPEED:\n      self.lkas_allowed = True\n    elif speed_kph < LKAS_LIMITS.DISABLE_SPEED:\n      self.lkas_allowed = False\n\n    # if any of the cruize buttons is pressed force state update\n    if any([cp.vl[\"CRZ_BTNS\"][\"RES\"],\n                cp.vl[\"CRZ_BTNS\"][\"SET_P\"],\n                cp.vl[\"CRZ_BTNS\"][\"SET_M\"]]):\n      self.cruise_speed = ret.vEgoRaw\n\n    ret.cruiseState.available = True\n    ret.cruiseState.enabled = cp.vl[\"CRZ_CTRL\"][\"CRZ_ACTIVE\"] == 1\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    ret.cruiseState.speed = self.cruise_speed\n\n    if ret.cruiseState.enabled:\n      if not self.lkas_allowed:\n        if not self.acc_active_last:\n          self.low_speed_lockout = True\n        else:\n          self.low_speed_alert = True\n      else:\n        self.low_speed_lockout = False\n        self.low_speed_alert = False\n\n    # On if no driver torque the last 5 seconds\n    ret.steerWarning = cp.vl[\"STEER_RATE\"][\"HANDS_OFF_5_SECONDS\"] == 1\n\n    self.acc_active_last = ret.cruiseState.enabled\n\n    self.cam_lkas = cp_cam.vl[\"CAM_LKAS\"]\n    ret.steerError = cp_cam.vl[\"CAM_LKAS\"][\"ERR_BIT_1\"] == 1\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    # this function generates lists for signal, messages and initial values\n    signals = [\n      # sig_name, sig_address, default\n      (\"LEFT_BLINK\", \"BLINK_INFO\", 0),\n      (\"RIGHT_BLINK\", \"BLINK_INFO\", 0),\n      (\"STEER_ANGLE\", \"STEER\", 0),\n      (\"STEER_ANGLE_RATE\", \"STEER_RATE\", 0),\n      (\"STEER_TORQUE_SENSOR\", \"STEER_TORQUE\", 0),\n      (\"STEER_TORQUE_MOTOR\", \"STEER_TORQUE\", 0),\n      (\"FL\", \"WHEEL_SPEEDS\", 0),\n      (\"FR\", \"WHEEL_SPEEDS\", 0),\n      (\"RL\", \"WHEEL_SPEEDS\", 0),\n      (\"RR\", \"WHEEL_SPEEDS\", 0),\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"BLINK_INFO\", 10),\n      (\"STEER\", 67),\n      (\"STEER_RATE\", 83),\n      (\"STEER_TORQUE\", 83),\n      (\"WHEEL_SPEEDS\", 100),\n    ]\n\n    if CP.carFingerprint in GEN1:\n      signals += [\n        (\"LKAS_BLOCK\", \"STEER_RATE\", 0),\n        (\"LKAS_TRACK_STATE\", \"STEER_RATE\", 0),\n        (\"HANDS_OFF_5_SECONDS\", \"STEER_RATE\", 0),\n        (\"CRZ_ACTIVE\", \"CRZ_CTRL\", 0),\n        (\"STANDSTILL\", \"PEDALS\", 0),\n        (\"BRAKE_ON\", \"PEDALS\", 0),\n        (\"BRAKE_PRESSURE\", \"BRAKE\", 0),\n        (\"GEAR\", \"GEAR\", 0),\n        (\"DRIVER_SEATBELT\", \"SEATBELT\", 0),\n        (\"FL\", \"DOORS\", 0),\n        (\"FR\", \"DOORS\", 0),\n        (\"BL\", \"DOORS\", 0),\n        (\"BR\", \"DOORS\", 0),\n        (\"PEDAL_GAS\", \"ENGINE_DATA\", 0),\n        (\"SPEED\", \"ENGINE_DATA\", 0),\n        (\"RES\", \"CRZ_BTNS\", 0),\n        (\"SET_P\", \"CRZ_BTNS\", 0),\n        (\"SET_M\", \"CRZ_BTNS\", 0),\n        (\"CTR\", \"CRZ_BTNS\", 0),\n        (\"LEFT_BS1\", \"BSM\", 0),\n        (\"RIGHT_BS1\", \"BSM\", 0),\n      ]\n\n      checks += [\n        (\"ENGINE_DATA\", 100),\n        (\"CRZ_CTRL\", 50),\n        (\"CRZ_BTNS\", 10),\n        (\"PEDALS\", 50),\n        (\"BRAKE\", 50),\n        (\"SEATBELT\", 10),\n        (\"DOORS\", 10),\n        (\"GEAR\", 20),\n        (\"BSM\", 10),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    signals = []\n    checks = []\n\n    if CP.carFingerprint in GEN1:\n      signals += [\n        # sig_name, sig_address, default\n        (\"LKAS_REQUEST\",     \"CAM_LKAS\", 0),\n        (\"CTR\",              \"CAM_LKAS\", 0),\n        (\"ERR_BIT_1\",        \"CAM_LKAS\", 0),\n        (\"LINE_NOT_VISIBLE\", \"CAM_LKAS\", 0),\n        (\"LDW\",              \"CAM_LKAS\", 0),\n        (\"BIT_1\",            \"CAM_LKAS\", 1),\n        (\"ERR_BIT_2\",        \"CAM_LKAS\", 0),\n        (\"STEERING_ANGLE\",   \"CAM_LKAS\", 0),\n        (\"ANGLE_ENABLED\",    \"CAM_LKAS\", 0),\n        (\"CHKSUM\",           \"CAM_LKAS\", 0),\n      ]\n\n      checks += [\n        # sig_address, frequency\n        (\"CAM_LKAS\",      16),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n"
  },
  {
    "path": "selfdrive/car/mazda/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.mazda.values import CAR, LKAS_LIMITS\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\nButtonType = car.CarState.ButtonEvent.Type\nEventName = car.CarEvent.EventName\n\nclass CarInterface(CarInterfaceBase):\n\n  @staticmethod\n  def compute_gb(accel, speed):\n    return float(accel) / 4.0\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n\n    ret.carName = \"mazda\"\n    ret.safetyModel = car.CarParams.SafetyModel.mazda\n    ret.lateralTuning.init('pid')\n    ret.radarOffCan = True\n\n    ret.communityFeature = True\n    ret.dashcamOnly = True\n\n    ret.steerActuatorDelay = 0.1\n    ret.steerRateCost = 1.0\n    ret.steerLimitTimer = 0.8\n    tire_stiffness_factor = 0.70   # not optimized yet\n\n    if candidate == CAR.CX5:\n      ret.mass = 3655 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.7\n      ret.steerRatio = 15.5\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.19], [0.019]]\n      ret.lateralTuning.pid.kf = 0.00006\n    elif candidate in [CAR.CX9, CAR.CX9_2021]:\n      ret.mass = 4217 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 3.1\n      ret.steerRatio = 17.6\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.19], [0.019]]\n      ret.lateralTuning.pid.kf = 0.00006\n    elif candidate == CAR.MAZDA3:\n      ret.mass = 2875 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.7\n      ret.steerRatio = 14.0\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.19], [0.019]]\n      ret.lateralTuning.pid.kf = 0.00006\n    elif candidate == CAR.MAZDA6:\n      ret.mass = 3443 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.wheelbase = 2.83\n      ret.steerRatio = 15.5\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.19], [0.019]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    # No steer below disable speed\n    ret.minSteerSpeed = LKAS_LIMITS.DISABLE_SPEED * CV.KPH_TO_MS\n\n    ret.centerToFront = ret.wheelbase * 0.41\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n\n    # events\n    events = self.create_common_events(ret)\n\n    if self.CS.low_speed_lockout:\n      events.add(EventName.belowEngageSpeed)\n\n    if self.CS.low_speed_alert:\n      events.add(EventName.belowSteerSpeed)\n\n    ret.events = events.to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  def apply(self, c):\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, c.actuators, self.dragonconf)\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/mazda/mazdacan.py",
    "content": "from selfdrive.car.mazda.values import GEN1, Buttons\n\ndef create_steering_control(packer, car_fingerprint, frame, apply_steer, lkas):\n\n  tmp = apply_steer + 2048\n\n  lo = tmp & 0xFF\n  hi = tmp >> 8\n\n  b1 = int(lkas[\"BIT_1\"])\n  ldw = int(lkas[\"LDW\"])\n  er1 = int(lkas[\"ERR_BIT_1\"])\n  lnv = 0\n  er2 = int(lkas[\"ERR_BIT_2\"])\n\n  # Some older models do have these, newer models don't.\n  # Either way, they all work just fine if set to zero.\n  steering_angle = 0\n  b2 = 0\n\n  tmp = steering_angle + 2048\n  ahi = tmp >> 10\n  amd = (tmp & 0x3FF) >> 2\n  amd = (amd >> 4) | (( amd & 0xF) << 4)\n  alo = (tmp & 0x3) << 2\n\n  ctr = frame % 16\n  # bytes:     [    1  ] [ 2 ] [             3               ]  [           4         ]\n  csum = 249 - ctr - hi - lo - (lnv << 3) - er1 - (ldw << 7) - ( er2 << 4) - (b1 << 5)\n\n  #bytes       [ 5 ] [ 6 ] [    7   ]\n  csum = csum - ahi - amd - alo - b2\n\n  if ahi == 1:\n    csum = csum + 15\n\n  if csum < 0:\n    if csum < -256:\n      csum = csum + 512\n    else:\n      csum = csum + 256\n\n  csum = csum % 256\n\n  if car_fingerprint in GEN1:\n    values = {\n      \"LKAS_REQUEST\"     : apply_steer,\n      \"CTR\"              : ctr,\n      \"ERR_BIT_1\"        : er1,\n      \"LINE_NOT_VISIBLE\" : lnv,\n      \"LDW\"              : ldw,\n      \"BIT_1\"            : b1,\n      \"ERR_BIT_2\"        : er2,\n      \"STEERING_ANGLE\"   : steering_angle,\n      \"ANGLE_ENABLED\"    : b2,\n      \"CHKSUM\"           : csum\n    }\n\n  return packer.make_can_msg(\"CAM_LKAS\", 0, values)\n\n\ndef create_button_cmd(packer, car_fingerprint, button):\n\n  if button == Buttons.CANCEL:\n    can = 1\n    res = 0\n  elif button == Buttons.RESUME:\n    can = 0\n    res = 1\n  else:\n    can = 0\n    res = 0\n\n  if car_fingerprint in GEN1:\n    values = {\n      \"CAN_OFF\"           : can,\n      \"CAN_OFF_INV\"       : (can + 1) % 2,\n\n      \"SET_P\"             : 0,\n      \"SET_P_INV\"         : 1,\n\n      \"RES\"               : res,\n      \"RES_INV\"           : (res + 1) % 2,\n\n      \"SET_M\"             : 0,\n      \"SET_M_INV\"         : 1,\n\n      \"DISTANCE_LESS\"     : 0,\n      \"DISTANCE_LESS_INV\" : 1,\n\n      \"DISTANCE_MORE\"     : 0,\n      \"DISTANCE_MORE_INV\" : 1,\n\n      \"MODE_X\"            : 0,\n      \"MODE_X_INV\"        : 1,\n\n      \"MODE_Y\"            : 0,\n      \"MODE_Y_INV\"        : 1,\n\n      \"BIT1\"              : 1,\n      \"BIT2\"              : 1,\n      \"BIT3\"              : 1,\n      \"CTR\"               : 0\n    }\n\n    return packer.make_can_msg(\"CRZ_BTNS\", 0, values)\n"
  },
  {
    "path": "selfdrive/car/mazda/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nclass RadarInterface(RadarInterfaceBase):\n  pass\n"
  },
  {
    "path": "selfdrive/car/mazda/values.py",
    "content": "# flake8: noqa\n\nfrom selfdrive.car import dbc_dict\nfrom cereal import car\nEcu = car.CarParams.Ecu\n\n\n# Steer torque limits\n\nclass CarControllerParams:\n  STEER_MAX = 800                # theoretical max_steer 2047\n  STEER_DELTA_UP = 10             # torque increase per refresh\n  STEER_DELTA_DOWN = 25           # torque decrease per refresh\n  STEER_DRIVER_ALLOWANCE = 15     # allowed driver torque before start limiting\n  STEER_DRIVER_MULTIPLIER = 1     # weight driver torque\n  STEER_DRIVER_FACTOR = 1         # from dbc\n  STEER_ERROR_MAX = 350           # max delta between torque cmd and torque motor\n\nclass CAR:\n  CX5 = \"MAZDA CX-5\"\n  CX9 = \"MAZDA CX-9\"\n  MAZDA3 = \"MAZDA 3\"\n  MAZDA6 = \"MAZDA 6\"\n  CX9_2021 = \"Mazda CX-9 2021\"   # No Steer Lockout\n\nclass LKAS_LIMITS:\n  STEER_THRESHOLD = 15\n  DISABLE_SPEED = 45    # kph\n  ENABLE_SPEED = 52     # kph\n\nclass Buttons:\n  NONE = 0\n  SET_PLUS = 1\n  SET_MINUS = 2\n  RESUME = 3\n  CANCEL = 4\n\n\nFW_VERSIONS = {\n  CAR.CX5: {\n    (Ecu.eps, 0x730, None): [\n      b'KJ01-3210X-G-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KJ01-3210X-J-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KJ01-3210X-M-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K319-3210X-A-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'PA53-188K2-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYNF-188K2-F\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYFA-188K2-J\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYFC-188K2-J\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYFD-188K2-J\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX2G-188K2-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX2H-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX2H-188K2-D\\0x0\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX38-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX42-188K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX68-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'SHKT-188K2-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x764, None): [\n      b'K123-67XK2-F\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-E\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x760, None): [\n      b'K123-437K2-E\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KL2K-437K2-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KN0W-437K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KBJ5-437K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x706, None): [\n      b'B61L-67XK2-T\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-R\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-S\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-V\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GSH7-67XK2-J\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GSH7-67XK2-N\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'PA66-21PS1-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX39-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYB1-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYB1-21PS1-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX68-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYNC-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYB2-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYB2-21PS1-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYB2-21PS1-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYB2-21PS1-G\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'SH9T-21PS1-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n  },\n\n  CAR.CX9 : {\n    (Ecu.eps, 0x730, None): [\n      b'K070-3210X-C-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KJ01-3210X-G-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KJ01-3210X-L-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'PYFM-188K2-F\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYD7-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX23-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX24-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PXN8-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x764, None): [\n      b'TK80-67XK2-E\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K123-67XK2-F\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x760, None): [\n      b'TK79-437K2-E\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'TM53-437K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'TN40-437K2-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'TA0B-437K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x706, None): [\n      b'TK80-67XK2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-P\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-V\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GSH7-67XK2-K\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'PYFM-21PS1-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYD5-21PS1-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYD5-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYD6-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PXM7-21PS1-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n  },\n\n  CAR.MAZDA3: {\n    (Ecu.eps, 0x730, None): [\n      b'K070-3210X-C-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'KR11-3210X-K-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'BHN1-3210X-J-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'P5JD-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYKC-188K2-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYKE-188K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PY2P-188K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x764, None): [\n      b'GHP9-67Y10---41\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B63C-67XK2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x760, None): [\n      b'B45A-437AS-0-08\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x706, None): [\n      b'B61L-67XK2-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-P\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'B61L-67XK2-T\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'PY2S-21PS1-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'P52G-21PS1-F\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYKE-21PS1-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYKE-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n  },\n\n  CAR.MAZDA6: {\n    (Ecu.eps, 0x730, None): [\n      b'GBEF-3210X-B-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GFBC-3210X-A-00\\000\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'PYH7-188K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PX4F-188K2-D\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.fwdRadar, 0x764, None): [\n      b'K131-67XK2-A\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'K131-67XK2-E\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.esp, 0x760, None): [\n      b'GBVH-437K2-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GDDM-437K2-A\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.fwdCamera, 0x706, None): [\n      b'B61L-67XK2-S\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GSH7-67XK2-P\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'PYH7-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PYH3-21PS1-D\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000',\n    ],\n  },\n\n  CAR.CX9_2021 : {\n    (Ecu.eps, 0x730, None): [\n      b'TC3M-3210X-A-00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'PXM4-188K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'PXM4-188K2-D\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x764, None): [\n      b'K131-67XK2-E\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x760, None): [\n      b'TA0B-437K2-C\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x706, None): [\n      b'GSH7-67XK2-M\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'GSH7-67XK2-N\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'PXM4-21PS1-B\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n  }\n}\n\n\nDBC = {\n  CAR.CX5: dbc_dict('mazda_2017', None),\n  CAR.CX9: dbc_dict('mazda_2017', None),\n  CAR.MAZDA3: dbc_dict('mazda_2017', None),\n  CAR.MAZDA6: dbc_dict('mazda_2017', None),\n  CAR.CX9_2021: dbc_dict('mazda_2017', None),\n}\n\n# Gen 1 hardware: same CAN messages and same camera\nGEN1 = set([CAR.CX5, CAR.CX9, CAR.CX9_2021, CAR.MAZDA3, CAR.MAZDA6])\n\n# Cars with a steering lockout\nSTEER_LOCKOUT_CAR = set([CAR.CX5, CAR.CX9, CAR.MAZDA3, CAR.MAZDA6])\n"
  },
  {
    "path": "selfdrive/car/mock/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/mock/interface.py",
    "content": "#!/usr/bin/env python3\nimport math\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.swaglog import cloudlog\nimport cereal.messaging as messaging\nfrom selfdrive.car import gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\n\n# mocked car interface to work with chffrplus\nTS = 0.01  # 100Hz\nYAW_FR = 0.2  # ~0.8s time constant on yaw rate filter\n# low pass gain\nLPG = 2 * math.pi * YAW_FR * TS / (1 + 2 * math.pi * YAW_FR * TS)\n\n\nclass CarInterface(CarInterfaceBase):\n  def __init__(self, CP, CarController, CarState):\n    super().__init__(CP, CarController, CarState)\n\n    cloudlog.debug(\"Using Mock Car Interface\")\n\n    # TODO: subscribe to phone sensor\n    self.sensor = messaging.sub_sock('sensorEvents')\n    self.gps = messaging.sub_sock('gpsLocationExternal')\n\n    self.speed = 0.\n    self.prev_speed = 0.\n    self.yaw_rate = 0.\n    self.yaw_rate_meas = 0.\n\n  @staticmethod\n  def compute_gb(accel, speed):\n    return accel\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"mock\"\n    ret.safetyModel = car.CarParams.SafetyModel.noOutput\n    ret.mass = 1700.\n    ret.rotationalInertia = 2500.\n    ret.wheelbase = 2.70\n    ret.centerToFront = ret.wheelbase * 0.5\n    ret.steerRatio = 13.  # reasonable\n    ret.tireStiffnessFront = 1e6    # very stiff to neglect slip\n    ret.tireStiffnessRear = 1e6     # very stiff to neglect slip\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    # get basic data from phone and gps since CAN isn't connected\n    sensors = messaging.recv_sock(self.sensor)\n    if sensors is not None:\n      for sensor in sensors.sensorEvents:\n        if sensor.type == 4:  # gyro\n          self.yaw_rate_meas = -sensor.gyro.v[0]\n\n    gps = messaging.recv_sock(self.gps)\n    if gps is not None:\n      self.prev_speed = self.speed\n      self.speed = gps.gpsLocationExternal.speed\n\n    # create message\n    ret = car.CarState.new_message()\n    ret.canValid = True\n\n    # speeds\n    ret.vEgo = self.speed\n    ret.vEgoRaw = self.speed\n    a = self.speed - self.prev_speed\n\n    ret.aEgo = a\n    ret.brakePressed = a < -0.5\n\n    ret.standstill = self.speed < 0.01\n    ret.wheelSpeeds.fl = self.speed\n    ret.wheelSpeeds.fr = self.speed\n    ret.wheelSpeeds.rl = self.speed\n    ret.wheelSpeeds.rr = self.speed\n\n    self.yawRate = LPG * self.yaw_rate_meas + (1. - LPG) * self.yaw_rate\n    curvature = self.yaw_rate / max(self.speed, 1.)\n    ret.steeringAngleDeg = curvature * self.CP.steerRatio * self.CP.wheelbase * CV.RAD_TO_DEG\n\n    return ret.as_reader()\n\n  def apply(self, c):\n    # in mock no carcontrols\n    return []\n"
  },
  {
    "path": "selfdrive/car/mock/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nclass RadarInterface(RadarInterfaceBase):\n  pass\n"
  },
  {
    "path": "selfdrive/car/mock/values.py",
    "content": "class CAR:\n  MOCK = 'mock'\n"
  },
  {
    "path": "selfdrive/car/nissan/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/nissan/carcontroller.py",
    "content": "from cereal import car\nfrom common.numpy_fast import clip, interp\nfrom selfdrive.car.nissan import nissancan\nfrom opendbc.can.packer import CANPacker\nfrom selfdrive.car.nissan.values import CAR, CarControllerParams\nfrom common.dp_common import common_controller_ctrl\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.CP = CP\n    self.car_fingerprint = CP.carFingerprint\n\n    self.lkas_max_torque = 0\n    self.last_angle = 0\n\n    self.packer = CANPacker(dbc_name)\n\n  def update(self, enabled, CS, frame, actuators, cruise_cancel, hud_alert,\n             left_line, right_line, left_lane_depart, right_lane_depart, dragonconf):\n    \"\"\" Controls thread \"\"\"\n\n    # Send CAN commands.\n    can_sends = []\n\n    ### STEER ###\n    acc_active = bool(CS.out.cruiseState.enabled)\n    lkas_hud_msg = CS.lkas_hud_msg\n    lkas_hud_info_msg = CS.lkas_hud_info_msg\n    apply_angle = actuators.steeringAngleDeg\n\n    steer_hud_alert = 1 if hud_alert in [VisualAlert.steerRequired, VisualAlert.ldw] else 0\n\n    if enabled:\n      # # windup slower\n      if self.last_angle * apply_angle > 0. and abs(apply_angle) > abs(self.last_angle):\n        angle_rate_lim = interp(CS.out.vEgo, CarControllerParams.ANGLE_DELTA_BP, CarControllerParams.ANGLE_DELTA_V)\n      else:\n        angle_rate_lim = interp(CS.out.vEgo, CarControllerParams.ANGLE_DELTA_BP, CarControllerParams.ANGLE_DELTA_VU)\n\n      apply_angle = clip(apply_angle, self.last_angle - angle_rate_lim, self.last_angle + angle_rate_lim)\n\n      # Max torque from driver before EPS will give up and not apply torque\n      if not bool(CS.out.steeringPressed):\n        self.lkas_max_torque = CarControllerParams.LKAS_MAX_TORQUE\n      else:\n        # Scale max torque based on how much torque the driver is applying to the wheel\n        self.lkas_max_torque = max(\n          # Scale max torque down to half LKAX_MAX_TORQUE as a minimum\n          CarControllerParams.LKAS_MAX_TORQUE * 0.5,\n          # Start scaling torque at STEER_THRESHOLD\n          CarControllerParams.LKAS_MAX_TORQUE - 0.6 * max(0, abs(CS.out.steeringTorque) - CarControllerParams.STEER_THRESHOLD)\n        )\n\n    else:\n      apply_angle = CS.out.steeringAngleDeg\n      self.lkas_max_torque = 0\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_angle = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_angle, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    self.last_angle = apply_angle\n\n    if not enabled and acc_active:\n      # send acc cancel cmd if drive is disabled but pcm is still on, or if the system can't be activated\n      cruise_cancel = 1\n\n    if self.CP.carFingerprint in [CAR.ROGUE, CAR.XTRAIL, CAR.ALTIMA] and cruise_cancel:\n        can_sends.append(nissancan.create_acc_cancel_cmd(self.packer, self.car_fingerprint, CS.cruise_throttle_msg, frame))\n\n    # TODO: Find better way to cancel!\n    # For some reason spamming the cancel button is unreliable on the Leaf\n    # We now cancel by making propilot think the seatbelt is unlatched,\n    # this generates a beep and a warning message every time you disengage\n    if self.CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC] and frame % 2 == 0:\n        can_sends.append(nissancan.create_cancel_msg(self.packer, CS.cancel_msg, cruise_cancel))\n\n    can_sends.append(nissancan.create_steering_control(\n        self.packer, apply_angle, frame, enabled, self.lkas_max_torque))\n\n    if lkas_hud_msg and lkas_hud_info_msg:\n      if frame % 2 == 0:\n        can_sends.append(nissancan.create_lkas_hud_msg(\n          self.packer, lkas_hud_msg, enabled, left_line, right_line, left_lane_depart, right_lane_depart))\n\n      if frame % 50 == 0:\n        can_sends.append(nissancan.create_lkas_hud_info_msg(\n          self.packer, lkas_hud_info_msg, steer_hud_alert\n        ))\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/nissan/carstate.py",
    "content": "import copy\nfrom collections import deque\nfrom cereal import car\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.car.interfaces import CarStateBase\nfrom selfdrive.config import Conversions as CV\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.nissan.values import CAR, DBC, CarControllerParams\n\nTORQUE_SAMPLES = 12\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n\n    self.lkas_hud_msg = None\n    self.lkas_hud_info_msg = None\n\n    self.steeringTorqueSamples = deque(TORQUE_SAMPLES*[0], TORQUE_SAMPLES)\n    self.shifter_values = can_define.dv[\"GEARBOX\"][\"GEAR_SHIFTER\"]\n\n  def update(self, cp, cp_adas, cp_cam):\n    ret = car.CarState.new_message()\n\n    if self.CP.carFingerprint in [CAR.ROGUE, CAR.XTRAIL, CAR.ALTIMA]:\n      ret.gas = cp.vl[\"GAS_PEDAL\"][\"GAS_PEDAL\"]\n    elif self.CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC]:\n      ret.gas = cp.vl[\"CRUISE_THROTTLE\"][\"GAS_PEDAL\"]\n\n    ret.gasPressed = bool(ret.gas > 3)\n\n    if self.CP.carFingerprint in [CAR.ROGUE, CAR.XTRAIL, CAR.ALTIMA]:\n      ret.brakePressed = bool(cp.vl[\"DOORS_LIGHTS\"][\"USER_BRAKE_PRESSED\"])\n    elif self.CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC]:\n      ret.brakePressed = bool(cp.vl[\"BRAKE_PEDAL\"][\"BRAKE_PEDAL\"] > 3)\n\n    ret.wheelSpeeds.fl = cp.vl[\"WHEEL_SPEEDS_FRONT\"][\"WHEEL_SPEED_FL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = cp.vl[\"WHEEL_SPEEDS_FRONT\"][\"WHEEL_SPEED_FR\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = cp.vl[\"WHEEL_SPEEDS_REAR\"][\"WHEEL_SPEED_RL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = cp.vl[\"WHEEL_SPEEDS_REAR\"][\"WHEEL_SPEED_RR\"] * CV.KPH_TO_MS\n\n    ret.vEgoRaw = (ret.wheelSpeeds.fl + ret.wheelSpeeds.fr + ret.wheelSpeeds.rl + ret.wheelSpeeds.rr) / 4.\n\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n    ret.standstill = ret.vEgoRaw < 0.01\n\n    if self.CP.carFingerprint == CAR.ALTIMA:\n      ret.cruiseState.enabled = bool(cp.vl[\"CRUISE_STATE\"][\"CRUISE_ENABLED\"])\n    else:\n      ret.cruiseState.enabled = bool(cp_adas.vl[\"CRUISE_STATE\"][\"CRUISE_ENABLED\"])\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n\n    if self.CP.carFingerprint in [CAR.ROGUE, CAR.XTRAIL]:\n      ret.seatbeltUnlatched = cp.vl[\"HUD\"][\"SEATBELT_DRIVER_LATCHED\"] == 0\n      ret.cruiseState.available = bool(cp_cam.vl[\"PRO_PILOT\"][\"CRUISE_ON\"])\n    elif self.CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC]:\n      if self.CP.carFingerprint == CAR.LEAF:\n        ret.seatbeltUnlatched = cp.vl[\"SEATBELT\"][\"SEATBELT_DRIVER_LATCHED\"] == 0\n      elif self.CP.carFingerprint == CAR.LEAF_IC:\n        ret.seatbeltUnlatched = cp.vl[\"CANCEL_MSG\"][\"CANCEL_SEATBELT\"] == 1\n      ret.cruiseState.available = bool(cp.vl[\"CRUISE_THROTTLE\"][\"CRUISE_AVAILABLE\"])\n    elif self.CP.carFingerprint == CAR.ALTIMA:\n      ret.seatbeltUnlatched = cp.vl[\"HUD\"][\"SEATBELT_DRIVER_LATCHED\"] == 0\n      ret.cruiseState.available = bool(cp_adas.vl[\"PRO_PILOT\"][\"CRUISE_ON\"])\n\n    if self.CP.carFingerprint == CAR.ALTIMA:\n      speed = cp.vl[\"PROPILOT_HUD\"][\"SET_SPEED\"]\n    else:\n      speed = cp_adas.vl[\"PROPILOT_HUD\"][\"SET_SPEED\"]\n\n    if speed != 255:\n      if self.CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC]:\n        conversion = CV.MPH_TO_MS if cp.vl[\"HUD_SETTINGS\"][\"SPEED_MPH\"] else CV.KPH_TO_MS\n      else:\n        conversion = CV.MPH_TO_MS if cp.vl[\"HUD\"][\"SPEED_MPH\"] else CV.KPH_TO_MS\n      speed -= 1  # Speed on HUD is always 1 lower than actually sent on can bus\n      ret.cruiseState.speed = speed * conversion\n\n    if self.CP.carFingerprint == CAR.ALTIMA:\n      ret.steeringTorque = cp_cam.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_TORQUE_DRIVER\"]\n    else:\n      ret.steeringTorque = cp.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_TORQUE_DRIVER\"]\n\n    self.steeringTorqueSamples.append(ret.steeringTorque)\n    # Filtering driver torque to prevent steeringPressed false positives\n    ret.steeringPressed = bool(abs(sum(self.steeringTorqueSamples) / TORQUE_SAMPLES) > CarControllerParams.STEER_THRESHOLD)\n\n    ret.steeringAngleDeg = cp.vl[\"STEER_ANGLE_SENSOR\"][\"STEER_ANGLE\"]\n\n    ret.leftBlinker = bool(cp.vl[\"LIGHTS\"][\"LEFT_BLINKER\"])\n    ret.rightBlinker = bool(cp.vl[\"LIGHTS\"][\"RIGHT_BLINKER\"])\n\n    ret.doorOpen = any([cp.vl[\"DOORS_LIGHTS\"][\"DOOR_OPEN_RR\"],\n                        cp.vl[\"DOORS_LIGHTS\"][\"DOOR_OPEN_RL\"],\n                        cp.vl[\"DOORS_LIGHTS\"][\"DOOR_OPEN_FR\"],\n                        cp.vl[\"DOORS_LIGHTS\"][\"DOOR_OPEN_FL\"]])\n\n    ret.espDisabled = bool(cp.vl[\"ESP\"][\"ESP_DISABLED\"])\n\n    can_gear = int(cp.vl[\"GEARBOX\"][\"GEAR_SHIFTER\"])\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(can_gear, None))\n\n    if self.CP.carFingerprint == CAR.ALTIMA:\n      self.lkas_enabled = bool(cp.vl[\"LKAS_SETTINGS\"][\"LKAS_ENABLED\"])\n    else:\n      self.lkas_enabled = bool(cp_adas.vl[\"LKAS_SETTINGS\"][\"LKAS_ENABLED\"])\n\n    self.cruise_throttle_msg = copy.copy(cp.vl[\"CRUISE_THROTTLE\"])\n\n    if self.CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC]:\n      self.cancel_msg = copy.copy(cp.vl[\"CANCEL_MSG\"])\n\n    if self.CP.carFingerprint != CAR.ALTIMA:\n      self.lkas_hud_msg = copy.copy(cp_adas.vl[\"PROPILOT_HUD\"])\n      self.lkas_hud_info_msg = copy.copy(cp_adas.vl[\"PROPILOT_HUD_INFO_MSG\"])\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    # this function generates lists for signal, messages and initial values\n    signals = [\n      # sig_name, sig_address, default\n      (\"WHEEL_SPEED_FL\", \"WHEEL_SPEEDS_FRONT\", 0),\n      (\"WHEEL_SPEED_FR\", \"WHEEL_SPEEDS_FRONT\", 0),\n      (\"WHEEL_SPEED_RL\", \"WHEEL_SPEEDS_REAR\", 0),\n      (\"WHEEL_SPEED_RR\", \"WHEEL_SPEEDS_REAR\", 0),\n\n      (\"STEER_ANGLE\", \"STEER_ANGLE_SENSOR\", 0),\n\n      (\"DOOR_OPEN_FR\", \"DOORS_LIGHTS\", 1),\n      (\"DOOR_OPEN_FL\", \"DOORS_LIGHTS\", 1),\n      (\"DOOR_OPEN_RR\", \"DOORS_LIGHTS\", 1),\n      (\"DOOR_OPEN_RL\", \"DOORS_LIGHTS\", 1),\n\n      (\"RIGHT_BLINKER\", \"LIGHTS\", 0),\n      (\"LEFT_BLINKER\", \"LIGHTS\", 0),\n\n      (\"ESP_DISABLED\", \"ESP\", 0),\n\n      (\"GEAR_SHIFTER\", \"GEARBOX\", 0),\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"STEER_ANGLE_SENSOR\", 100),\n      (\"WHEEL_SPEEDS_REAR\", 50),\n      (\"WHEEL_SPEEDS_FRONT\", 50),\n      (\"ESP\", 25),\n      (\"GEARBOX\", 25),\n      (\"DOORS_LIGHTS\", 10),\n      (\"LIGHTS\", 10),\n    ]\n\n    if CP.carFingerprint in [CAR.ROGUE, CAR.XTRAIL, CAR.ALTIMA]:\n      signals += [\n        (\"USER_BRAKE_PRESSED\", \"DOORS_LIGHTS\", 1),\n\n        (\"GAS_PEDAL\", \"GAS_PEDAL\", 0),\n        (\"SEATBELT_DRIVER_LATCHED\", \"HUD\", 0),\n        (\"SPEED_MPH\", \"HUD\", 0),\n\n        (\"PROPILOT_BUTTON\", \"CRUISE_THROTTLE\", 0),\n        (\"CANCEL_BUTTON\", \"CRUISE_THROTTLE\", 0),\n        (\"GAS_PEDAL_INVERTED\", \"CRUISE_THROTTLE\", 0),\n        (\"SET_BUTTON\", \"CRUISE_THROTTLE\", 0),\n        (\"RES_BUTTON\", \"CRUISE_THROTTLE\", 0),\n        (\"FOLLOW_DISTANCE_BUTTON\", \"CRUISE_THROTTLE\", 0),\n        (\"NO_BUTTON_PRESSED\", \"CRUISE_THROTTLE\", 0),\n        (\"GAS_PEDAL\", \"CRUISE_THROTTLE\", 0),\n        (\"USER_BRAKE_PRESSED\", \"CRUISE_THROTTLE\", 0),\n        (\"NEW_SIGNAL_2\", \"CRUISE_THROTTLE\", 0),\n        (\"GAS_PRESSED_INVERTED\", \"CRUISE_THROTTLE\", 0),\n        (\"unsure1\", \"CRUISE_THROTTLE\", 0),\n        (\"unsure2\", \"CRUISE_THROTTLE\", 0),\n        (\"unsure3\", \"CRUISE_THROTTLE\", 0),\n      ]\n\n      checks += [\n        (\"GAS_PEDAL\", 100),\n        (\"CRUISE_THROTTLE\", 50),\n        (\"HUD\", 25),\n      ]\n\n    elif CP.carFingerprint in [CAR.LEAF, CAR.LEAF_IC]:\n      signals += [\n        (\"BRAKE_PEDAL\", \"BRAKE_PEDAL\", 0),\n\n        (\"GAS_PEDAL\", \"CRUISE_THROTTLE\", 0),\n        (\"CRUISE_AVAILABLE\", \"CRUISE_THROTTLE\", 0),\n        (\"SPEED_MPH\", \"HUD_SETTINGS\", 0),\n        (\"SEATBELT_DRIVER_LATCHED\", \"SEATBELT\", 0),\n\n        # Copy other values, we use this to cancel\n        (\"CANCEL_SEATBELT\", \"CANCEL_MSG\", 0),\n        (\"NEW_SIGNAL_1\", \"CANCEL_MSG\", 0),\n        (\"NEW_SIGNAL_2\", \"CANCEL_MSG\", 0),\n        (\"NEW_SIGNAL_3\", \"CANCEL_MSG\", 0),\n      ]\n      checks += [\n        (\"BRAKE_PEDAL\", 100),\n        (\"CRUISE_THROTTLE\", 50),\n        (\"CANCEL_MSG\", 50),\n        (\"HUD_SETTINGS\", 25),\n        (\"SEATBELT\", 10),\n      ]\n\n    if CP.carFingerprint == CAR.ALTIMA:\n      signals += [\n        (\"LKAS_ENABLED\", \"LKAS_SETTINGS\", 0),\n        (\"CRUISE_ENABLED\", \"CRUISE_STATE\", 0),\n        (\"SET_SPEED\", \"PROPILOT_HUD\", 0),\n      ]\n      checks += [\n        (\"CRUISE_STATE\", 10),\n        (\"LKAS_SETTINGS\", 10),\n        (\"PROPILOT_HUD\", 50),\n      ]\n      return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 1)\n\n    signals += [\n      (\"STEER_TORQUE_DRIVER\", \"STEER_TORQUE_SENSOR\", 0),\n    ]\n    checks += [\n      (\"STEER_TORQUE_SENSOR\", 100),\n    ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n  @staticmethod\n  def get_adas_can_parser(CP):\n    # this function generates lists for signal, messages and initial values\n\n    if CP.carFingerprint == CAR.ALTIMA:\n      signals = [\n        (\"DESIRED_ANGLE\", \"LKAS\", 0),\n        (\"SET_0x80_2\", \"LKAS\", 0),\n        (\"MAX_TORQUE\", \"LKAS\", 0),\n        (\"SET_0x80\", \"LKAS\", 0),\n        (\"COUNTER\", \"LKAS\", 0),\n        (\"LKA_ACTIVE\", \"LKAS\", 0),\n\n        (\"CRUISE_ON\", \"PRO_PILOT\", 0),\n      ]\n      checks = [\n        (\"LKAS\", 100),\n        (\"PRO_PILOT\", 100),\n      ]\n    else:\n      signals = [\n        # sig_name, sig_address, default\n        (\"LKAS_ENABLED\", \"LKAS_SETTINGS\", 0),\n\n        (\"CRUISE_ENABLED\", \"CRUISE_STATE\", 0),\n\n        (\"DESIRED_ANGLE\", \"LKAS\", 0),\n        (\"SET_0x80_2\", \"LKAS\", 0),\n        (\"MAX_TORQUE\", \"LKAS\", 0),\n        (\"SET_0x80\", \"LKAS\", 0),\n        (\"COUNTER\", \"LKAS\", 0),\n        (\"LKA_ACTIVE\", \"LKAS\", 0),\n\n        # Below are the HUD messages. We copy the stock message and modify\n        (\"LARGE_WARNING_FLASHING\", \"PROPILOT_HUD\", 0),\n        (\"SIDE_RADAR_ERROR_FLASHING1\", \"PROPILOT_HUD\", 0),\n        (\"SIDE_RADAR_ERROR_FLASHING2\", \"PROPILOT_HUD\", 0),\n        (\"LEAD_CAR\", \"PROPILOT_HUD\", 0),\n        (\"LEAD_CAR_ERROR\", \"PROPILOT_HUD\", 0),\n        (\"FRONT_RADAR_ERROR\", \"PROPILOT_HUD\", 0),\n        (\"FRONT_RADAR_ERROR_FLASHING\", \"PROPILOT_HUD\", 0),\n        (\"SIDE_RADAR_ERROR_FLASHING3\", \"PROPILOT_HUD\", 0),\n        (\"LKAS_ERROR_FLASHING\", \"PROPILOT_HUD\", 0),\n        (\"SAFETY_SHIELD_ACTIVE\", \"PROPILOT_HUD\", 0),\n        (\"RIGHT_LANE_GREEN_FLASH\", \"PROPILOT_HUD\", 0),\n        (\"LEFT_LANE_GREEN_FLASH\", \"PROPILOT_HUD\", 0),\n        (\"FOLLOW_DISTANCE\", \"PROPILOT_HUD\", 0),\n        (\"AUDIBLE_TONE\", \"PROPILOT_HUD\", 0),\n        (\"SPEED_SET_ICON\", \"PROPILOT_HUD\", 0),\n        (\"SMALL_STEERING_WHEEL_ICON\", \"PROPILOT_HUD\", 0),\n        (\"unknown59\", \"PROPILOT_HUD\", 0),\n        (\"unknown55\", \"PROPILOT_HUD\", 0),\n        (\"unknown26\", \"PROPILOT_HUD\", 0),\n        (\"unknown28\", \"PROPILOT_HUD\", 0),\n        (\"unknown31\", \"PROPILOT_HUD\", 0),\n        (\"SET_SPEED\", \"PROPILOT_HUD\", 0),\n        (\"unknown43\", \"PROPILOT_HUD\", 0),\n        (\"unknown08\", \"PROPILOT_HUD\", 0),\n        (\"unknown05\", \"PROPILOT_HUD\", 0),\n        (\"unknown02\", \"PROPILOT_HUD\", 0),\n\n        (\"NA_HIGH_ACCEL_TEMP\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_RADAR_NA_HIGH_CABIN_TEMP\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_RADAR_MALFUNCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"LKAS_MALFUNCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"FRONT_RADAR_MALFUNCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_RADAR_NA_CLEAN_REAR_CAMERA\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"NA_POOR_ROAD_CONDITIONS\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"CURRENTLY_UNAVAILABLE\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SAFETY_SHIELD_OFF\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"FRONT_COLLISION_NA_FRONT_RADAR_OBSTRUCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"PEDAL_MISSAPPLICATION_SYSTEM_ACTIVATED\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_IMPACT_NA_RADAR_OBSTRUCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"WARNING_DO_NOT_ENTER\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_IMPACT_SYSTEM_OFF\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_IMPACT_MALFUNCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"FRONT_COLLISION_MALFUNCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"SIDE_RADAR_MALFUNCTION2\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"LKAS_MALFUNCTION2\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"FRONT_RADAR_MALFUNCTION2\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"PROPILOT_NA_MSGS\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"BOTTOM_MSG\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"HANDS_ON_WHEEL_WARNING\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"WARNING_STEP_ON_BRAKE_NOW\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"PROPILOT_NA_FRONT_CAMERA_OBSTRUCTED\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"PROPILOT_NA_HIGH_CABIN_TEMP\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"WARNING_PROPILOT_MALFUNCTION\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"ACC_UNAVAILABLE_HIGH_CABIN_TEMP\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"ACC_NA_FRONT_CAMERA_IMPARED\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown07\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown10\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown15\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown23\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown19\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown31\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown32\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown46\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown61\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown55\", \"PROPILOT_HUD_INFO_MSG\", 0),\n        (\"unknown50\", \"PROPILOT_HUD_INFO_MSG\", 0),\n      ]\n\n      checks = [\n        (\"PROPILOT_HUD_INFO_MSG\", 2),\n        (\"LKAS_SETTINGS\", 10),\n        (\"CRUISE_STATE\", 50),\n        (\"PROPILOT_HUD\", 50),\n        (\"LKAS\", 100),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    signals = []\n    checks = []\n\n    if CP.carFingerprint in [CAR.ROGUE, CAR.XTRAIL]:\n      signals += [\n        (\"CRUISE_ON\", \"PRO_PILOT\", 0),\n      ]\n      checks += [\n        (\"PRO_PILOT\", 100),\n      ]\n    elif CP.carFingerprint == CAR.ALTIMA:\n      signals += [\n        (\"STEER_TORQUE_DRIVER\", \"STEER_TORQUE_SENSOR\", 0),\n      ]\n      checks += [\n        (\"STEER_TORQUE_SENSOR\", 100),\n      ]\n      return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 1)\n"
  },
  {
    "path": "selfdrive/car/nissan/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.car.nissan.values import CAR\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\nclass CarInterface(CarInterfaceBase):\n  def __init__(self, CP, CarController, CarState):\n    super().__init__(CP, CarController, CarState)\n    self.cp_adas = self.CS.get_adas_can_parser(CP)\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"nissan\"\n    ret.safetyModel = car.CarParams.SafetyModel.nissan\n    ret.lateralTuning.init('pid')\n\n    # Nissan port is a community feature, since we don't own one to test\n    ret.communityFeature = True\n\n    ret.steerLimitAlert = False\n    ret.steerRateCost = 0.5\n\n    ret.steerActuatorDelay = 0.1\n\n    if candidate in [CAR.ROGUE, CAR.XTRAIL]:\n      ret.mass = 1610 + STD_CARGO_KG\n      ret.wheelbase = 2.705\n      ret.centerToFront = ret.wheelbase * 0.44\n      ret.steerRatio = 17\n    elif candidate in [CAR.LEAF, CAR.LEAF_IC]:\n      ret.mass = 1610 + STD_CARGO_KG\n      ret.wheelbase = 2.705\n      ret.centerToFront = ret.wheelbase * 0.44\n      ret.steerRatio = 17\n    elif candidate == CAR.ALTIMA:\n      # Altima has EPS on C-CAN unlike the others that have it on V-CAN\n      ret.safetyParam = 1 # EPS is on alternate bus\n      ret.mass = 1492 + STD_CARGO_KG\n      ret.wheelbase = 2.824\n      ret.centerToFront = ret.wheelbase * 0.44\n      ret.steerRatio = 17\n\n    ret.steerControlType = car.CarParams.SteerControlType.angle\n    ret.radarOffCan = True\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront)\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n    self.cp_adas.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_adas, self.cp_cam)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid and self.cp_adas.can_valid and self.cp_cam.can_valid\n\n    buttonEvents = []\n    be = car.CarState.ButtonEvent.new_message()\n    be.type = car.CarState.ButtonEvent.Type.accelCruise\n    buttonEvents.append(be)\n\n    events = self.create_common_events(ret)\n\n    if self.CS.lkas_enabled:\n      events.add(car.CarEvent.EventName.invalidLkasSetting)\n\n    ret.events = events.to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  def apply(self, c):\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, c.actuators,\n                               c.cruiseControl.cancel, c.hudControl.visualAlert,\n                               c.hudControl.leftLaneVisible, c.hudControl.rightLaneVisible,\n                               c.hudControl.leftLaneDepart, c.hudControl.rightLaneDepart, self.dragonconf)\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/nissan/nissancan.py",
    "content": "import copy\nimport crcmod\nfrom selfdrive.car.nissan.values import CAR\n\nnissan_checksum = crcmod.mkCrcFun(0x11d, initCrc=0x00, rev=False, xorOut=0xff)\n\n\ndef create_steering_control(packer, apply_steer, frame, steer_on, lkas_max_torque):\n  idx = (frame % 16)\n  values = {\n    \"DESIRED_ANGLE\": apply_steer,\n    \"SET_0x80_2\": 0x80,\n    \"SET_0x80\": 0x80,\n    \"MAX_TORQUE\": lkas_max_torque if steer_on else 0,\n    \"COUNTER\": idx,\n    \"LKA_ACTIVE\": steer_on,\n  }\n\n  dat = packer.make_can_msg(\"LKAS\", 0, values)[2]\n\n  values[\"CHECKSUM\"] = nissan_checksum(dat[:7])\n  return packer.make_can_msg(\"LKAS\", 0, values)\n\n\ndef create_acc_cancel_cmd(packer, car_fingerprint, cruise_throttle_msg, frame):\n  values = copy.copy(cruise_throttle_msg)\n  can_bus = 2\n\n  if car_fingerprint == CAR.ALTIMA:\n    can_bus = 1\n\n  values[\"CANCEL_BUTTON\"] = 1\n  values[\"NO_BUTTON_PRESSED\"] = 0\n  values[\"PROPILOT_BUTTON\"] = 0\n  values[\"SET_BUTTON\"] = 0\n  values[\"RES_BUTTON\"] = 0\n  values[\"FOLLOW_DISTANCE_BUTTON\"] = 0\n  values[\"COUNTER\"] = (frame % 4)\n\n  return packer.make_can_msg(\"CRUISE_THROTTLE\", can_bus, values)\n\n\ndef create_cancel_msg(packer, cancel_msg, cruise_cancel):\n  values = copy.copy(cancel_msg)\n\n  if cruise_cancel:\n    values[\"CANCEL_SEATBELT\"] = 1\n\n  return packer.make_can_msg(\"CANCEL_MSG\", 2, values)\n\n\ndef create_lkas_hud_msg(packer, lkas_hud_msg, enabled, left_line, right_line, left_lane_depart, right_lane_depart):\n  values = lkas_hud_msg\n\n  values[\"RIGHT_LANE_YELLOW_FLASH\"] = 1 if right_lane_depart else 0\n  values[\"LEFT_LANE_YELLOW_FLASH\"] = 1 if left_lane_depart else 0\n\n  values[\"LARGE_STEERING_WHEEL_ICON\"] = 2 if enabled else 0\n  values[\"RIGHT_LANE_GREEN\"] = 1 if right_line and enabled else 0\n  values[\"LEFT_LANE_GREEN\"] = 1 if left_line and enabled else 0\n\n  return packer.make_can_msg(\"PROPILOT_HUD\", 0, values)\n\n\ndef create_lkas_hud_info_msg(packer, lkas_hud_info_msg, steer_hud_alert):\n  values = lkas_hud_info_msg\n\n  if steer_hud_alert:\n    values[\"HANDS_ON_WHEEL_WARNING\"] = 1\n\n  return packer.make_can_msg(\"PROPILOT_HUD_INFO_MSG\", 0, values)\n"
  },
  {
    "path": "selfdrive/car/nissan/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nclass RadarInterface(RadarInterfaceBase):\n  pass\n"
  },
  {
    "path": "selfdrive/car/nissan/values.py",
    "content": "# flake8: noqa\n\nfrom selfdrive.car import dbc_dict\n\n\nclass CarControllerParams:\n  ANGLE_DELTA_BP = [0., 5., 15.]\n  ANGLE_DELTA_V = [5., .8, .15]     # windup limit\n  ANGLE_DELTA_VU = [5., 3.5, 0.4]   # unwind limit\n  LKAS_MAX_TORQUE = 1               # A value of 1 is easy to overpower\n  STEER_THRESHOLD = 1.0\n\nclass CAR:\n  XTRAIL = \"NISSAN X-TRAIL 2017\"\n  LEAF = \"NISSAN LEAF 2018\"\n  # Leaf with ADAS ECU found behind instrument cluster instead of glovebox\n  # Currently the only known difference between them is the inverted seatbelt signal.\n  LEAF_IC = \"NISSAN LEAF 2018 Instrument Cluster\"\n  ROGUE = \"NISSAN ROGUE 2019\"\n  ALTIMA = \"NISSAN ALTIMA 2020\"\n\n\nFINGERPRINTS = {\n  CAR.XTRAIL: [\n    {\n      2: 5, 42: 6, 346: 6, 347: 5, 348: 8, 349: 7, 361: 8, 386: 8, 389: 8, 397: 8, 398: 8, 403: 8, 520: 2, 523: 6, 548: 8, 645: 8, 658: 8, 665: 8, 666: 8, 674: 2, 682: 8, 683: 8, 689: 8, 723: 8, 758: 3, 768: 2, 783: 3, 851: 8, 855: 8, 1041: 8, 1055: 2, 1104: 4, 1105: 6, 1107: 4, 1108: 8, 1111: 4, 1227: 8, 1228: 8, 1247: 4, 1266: 8, 1273: 7, 1342: 1, 1376: 6, 1401: 8, 1474: 2, 1497: 3, 1821: 8, 1823: 8, 1837: 8, 2015: 8, 2016: 8, 2024: 8\n    },\n    {\n      2: 5, 42: 6, 346: 6, 347: 5, 348: 8, 349: 7, 361: 8, 386: 8, 389: 8, 397: 8, 398: 8, 403: 8, 520: 2, 523: 6, 527: 1, 548: 8, 637: 4, 645: 8, 658: 8, 665: 8, 666: 8, 674: 2, 682: 8, 683: 8, 689: 8, 723: 8, 758: 3, 768: 6, 783: 3, 851: 8, 855: 8, 1041: 8, 1055: 2, 1104: 4, 1105: 6, 1107: 4, 1108: 8, 1111: 4, 1227: 8, 1228: 8, 1247: 4, 1266: 8, 1273: 7, 1342: 1, 1376: 6, 1401: 8, 1474: 8, 1497: 3, 1534: 6, 1792: 8, 1821: 8, 1823: 8, 1837: 8, 1872: 8, 1937: 8, 1953: 8, 1968: 8, 2015: 8, 2016: 8, 2024: 8\n    },\n  ],\n  CAR.LEAF: [\n    {\n      2: 5, 42: 6, 264: 3, 361: 8, 372: 8, 384: 8, 389: 8, 403: 8, 459: 7, 460: 4, 470: 8, 520: 1, 569: 8, 581: 8, 634: 7, 640: 8, 644: 8, 645: 8, 646: 5, 658: 8, 682: 8, 683: 8, 689: 8, 724: 6, 758: 3, 761: 2, 783: 3, 852: 8, 853: 8, 856: 8, 861: 8, 944: 1, 976: 6, 1008: 7, 1011: 7, 1057: 3, 1227: 8, 1228: 8, 1261: 5, 1342: 1, 1354: 8, 1361: 8, 1459: 8, 1477: 8, 1497: 3, 1549: 8, 1573: 6, 1821: 8, 1837: 8, 1856: 8, 1859: 8, 1861: 8, 1864: 8, 1874: 8, 1888: 8, 1891: 8, 1893: 8, 1906: 8, 1947: 8, 1949: 8, 1979: 8, 1981: 8, 2016: 8, 2017: 8, 2021: 8, 643: 5, 1792: 8, 1872: 8, 1937: 8, 1953: 8, 1968: 8, 1988: 8, 2000: 8, 2001: 8, 2004: 8, 2005: 8, 2015: 8\n    },\n    # 2020 Leaf SV Plus\n    {\n      2: 5, 42: 8, 264: 3, 361: 8, 372: 8, 384: 8, 389: 8, 403: 8, 459: 7, 460: 4, 470: 8, 520: 1, 569: 8, 581: 8, 634: 7, 640: 8, 643: 5, 644: 8, 645: 8, 646: 5, 658: 8, 682: 8, 683: 8, 689: 8, 724: 6, 758: 3, 761: 2, 772: 8, 773: 6, 774: 7, 775: 8, 776: 6, 777: 7, 778: 6, 783: 3, 852: 8, 853: 8, 856: 8, 861: 8, 943: 8, 944: 1, 976: 6, 1008: 7, 1009: 8, 1010: 8, 1011: 7, 1012: 8, 1013: 8, 1019: 8, 1020: 8, 1021: 8, 1022: 8, 1057: 3, 1227: 8, 1228: 8, 1261: 5, 1342: 1, 1354: 8, 1361: 8, 1402: 8, 1459: 8, 1477: 8, 1497: 3, 1549: 8, 1573: 6, 1821: 8, 1837: 8\n    },\n  ],\n  CAR.LEAF_IC: [\n    {\n      2: 5, 42: 6, 264: 3, 282: 8, 361: 8, 372: 8, 384: 8, 389: 8, 403: 8, 459: 7, 460: 4, 470: 8, 520: 1, 569: 8, 581: 8, 634: 7, 640: 8, 643: 5, 644: 8, 645: 8, 646: 5, 658: 8, 682: 8, 683: 8, 689: 8, 756: 5, 758: 3, 761: 2, 783: 3, 830: 2, 852: 8, 853: 8, 856: 8, 861: 8, 943: 8, 944: 1, 1001: 6, 1057: 3, 1227: 8, 1228: 8, 1229: 8, 1342: 1, 1354: 8, 1361: 8, 1459: 8, 1477: 8, 1497: 3, 1514: 6, 1549: 8, 1573: 6, 1792: 8, 1821: 8, 1822: 8, 1837: 8, 1838: 8, 1872: 8, 1937: 8, 1953: 8, 1968: 8, 1988: 8, 2000: 8, 2001: 8, 2004: 8, 2005: 8, 2015: 8, 2016: 8, 2017: 8\n    },\n  ],\n  CAR.ROGUE: [\n    {\n      2: 5, 42: 6, 346: 6, 347: 5, 348: 8, 349: 7, 361: 8, 386: 8, 389: 8, 397: 8, 398: 8, 403: 8, 520: 2, 523: 6, 548: 8, 634: 7, 643: 5, 645: 8, 658: 8, 665: 8, 666: 8, 674: 2, 682: 8, 683: 8, 689: 8, 723: 8, 758: 3, 772: 8, 773: 6, 774: 7, 775: 8, 776: 6, 777: 7, 778: 6, 783: 3, 851: 8, 855: 8, 1041: 8, 1042: 8, 1055: 2, 1104: 4, 1105: 6, 1107: 4, 1108: 8, 1110: 7, 1111: 7, 1227: 8, 1228: 8, 1247: 4, 1266: 8, 1273: 7, 1342: 1, 1376: 6, 1401: 8, 1474: 2, 1497: 3, 1534: 7, 1792: 8, 1821: 8, 1823: 8, 1837: 8, 1839: 8, 1872: 8, 1937: 8, 1953: 8, 1968: 8, 1988: 8, 2000: 8, 2001: 8, 2004: 8, 2005: 8, 2015: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n    },\n  ],\n  CAR.ALTIMA: [\n    {\n      2: 5, 42: 6, 346: 6, 347: 5, 348: 8, 349: 7, 361: 8, 386: 8, 389: 8, 397: 8, 398: 8, 403: 8, 438: 8, 451: 8, 517: 8, 520: 2, 522: 8, 523: 6, 539: 8, 541: 7, 542: 8, 543: 8, 544: 8, 545: 8, 546: 8, 547: 8, 548: 8, 570: 8, 576: 8, 577: 8, 582: 8, 583: 8, 584: 8, 586: 8, 587: 8, 588: 8, 589: 8, 590: 8, 591: 8, 592: 8, 600: 8, 601: 8, 610: 8, 611: 8, 612: 8, 614: 8, 615: 8, 616: 8, 617: 8, 622: 8, 623: 8, 634: 7, 638: 8, 645: 8, 648: 5, 654: 6, 658: 8, 659: 8, 660: 8, 661: 8, 665: 8, 666: 8, 674: 2, 675: 8, 676: 8, 682: 8, 683: 8, 684: 8, 685: 8, 686: 8, 687: 8, 689: 8, 690: 8, 703: 8, 708: 7, 709: 7, 711: 7, 712: 7, 713: 7, 714: 8, 715: 8, 716: 8, 717: 7, 718: 7, 719: 7, 720: 7, 723: 8, 726: 7, 727: 7, 728: 7, 735: 8, 746: 8, 748: 6, 749: 6, 750: 8, 758: 3, 772: 8, 773: 6, 774: 7, 775: 8, 776: 6, 777: 7, 778: 6, 779: 7, 781: 7, 782: 7, 783: 3, 851: 8, 855: 5, 1001: 6, 1041: 8, 1042: 8, 1055: 3, 1100: 7, 1104: 4, 1105: 6, 1107: 4, 1108: 8, 1110: 7, 1111: 7, 1144: 7, 1145: 7, 1227: 8, 1228: 8, 1229: 8, 1232: 8, 1247: 4, 1258: 8, 1259: 8, 1266: 8, 1273: 7, 1306: 1, 1314: 8, 1323: 8, 1324: 8, 1342: 1, 1376: 8, 1401: 8, 1454: 8, 1497: 3, 1514: 6, 1526: 8, 1527: 5, 1792: 8, 1821: 8, 1823: 8, 1837: 8, 1872: 8, 1937: 8, 1953: 8, 1968: 8, 1988: 8, 2000: 8, 2001: 8, 2004: 8, 2005: 8, 2015: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n    },\n  ]\n}\n\nDBC = {\n  CAR.XTRAIL: dbc_dict('nissan_x_trail_2017', None),\n  CAR.LEAF: dbc_dict('nissan_leaf_2018', None),\n  CAR.LEAF_IC: dbc_dict('nissan_leaf_2018', None),\n  CAR.ROGUE: dbc_dict('nissan_x_trail_2017', None),\n  CAR.ALTIMA: dbc_dict('nissan_x_trail_2017', None),\n}\n"
  },
  {
    "path": "selfdrive/car/subaru/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/subaru/carcontroller.py",
    "content": "from selfdrive.car import apply_std_steer_torque_limits\nfrom selfdrive.car.subaru import subarucan\nfrom selfdrive.car.subaru.values import DBC, PREGLOBAL_CARS, CarControllerParams\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.apply_steer_last = 0\n    self.es_distance_cnt = -1\n    self.es_accel_cnt = -1\n    self.es_lkas_cnt = -1\n    self.cruise_button_prev = 0\n    self.steer_rate_limited = False\n\n    self.packer = CANPacker(DBC[CP.carFingerprint]['pt'])\n\n  def update(self, enabled, CS, frame, actuators, pcm_cancel_cmd, visual_alert, left_line, right_line, left_lane_depart, right_lane_depart, dragonconf):\n\n    can_sends = []\n\n    # *** steering ***\n    if (frame % CarControllerParams.STEER_STEP) == 0:\n\n      apply_steer = int(round(actuators.steer * CarControllerParams.STEER_MAX))\n\n      # limits due to driver torque\n\n      new_steer = int(round(apply_steer))\n      apply_steer = apply_std_steer_torque_limits(new_steer, self.apply_steer_last, CS.out.steeringTorque, CarControllerParams)\n      self.steer_rate_limited = new_steer != apply_steer\n\n      if not enabled:\n        apply_steer = 0\n\n      # dp\n      blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n      if not enabled:\n        self.blinker_end_frame = 0\n      if self.last_blinker_on and not blinker_on:\n        self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n      apply_steer = common_controller_ctrl(enabled,\n                                           dragonconf,\n                                           blinker_on or frame < self.blinker_end_frame,\n                                           apply_steer, CS.out.vEgo)\n      self.last_blinker_on = blinker_on\n\n      if CS.CP.carFingerprint in PREGLOBAL_CARS:\n        can_sends.append(subarucan.create_preglobal_steering_control(self.packer, apply_steer, frame, CarControllerParams.STEER_STEP))\n      else:\n        can_sends.append(subarucan.create_steering_control(self.packer, apply_steer, frame, CarControllerParams.STEER_STEP))\n\n      self.apply_steer_last = apply_steer\n\n\n    # *** alerts and pcm cancel ***\n\n    if CS.CP.carFingerprint in PREGLOBAL_CARS:\n      if self.es_accel_cnt != CS.es_accel_msg[\"Counter\"]:\n        # 1 = main, 2 = set shallow, 3 = set deep, 4 = resume shallow, 5 = resume deep\n        # disengage ACC when OP is disengaged\n        if pcm_cancel_cmd:\n          cruise_button = 1\n        # turn main on if off and past start-up state\n        elif not CS.out.cruiseState.available and CS.ready:\n          cruise_button = 1\n        else:\n          cruise_button = CS.cruise_button\n\n        # unstick previous mocked button press\n        if cruise_button == 1 and self.cruise_button_prev == 1:\n          cruise_button = 0\n        self.cruise_button_prev = cruise_button\n\n        can_sends.append(subarucan.create_es_throttle_control(self.packer, cruise_button, CS.es_accel_msg))\n        self.es_accel_cnt = CS.es_accel_msg[\"Counter\"]\n\n    else:\n      if self.es_distance_cnt != CS.es_distance_msg[\"Counter\"]:\n        can_sends.append(subarucan.create_es_distance(self.packer, CS.es_distance_msg, pcm_cancel_cmd))\n        self.es_distance_cnt = CS.es_distance_msg[\"Counter\"]\n\n      if self.es_lkas_cnt != CS.es_lkas_msg[\"Counter\"]:\n        can_sends.append(subarucan.create_es_lkas(self.packer, CS.es_lkas_msg, enabled, visual_alert, left_line, right_line, left_lane_depart, right_lane_depart))\n        self.es_lkas_cnt = CS.es_lkas_msg[\"Counter\"]\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/subaru/carstate.py",
    "content": "import copy\nfrom cereal import car\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import CarStateBase\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.subaru.values import DBC, STEER_THRESHOLD, CAR, PREGLOBAL_CARS\n\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n    self.shifter_values = can_define.dv[\"Transmission\"][\"Gear\"]\n\n  def update(self, cp, cp_cam):\n    ret = car.CarState.new_message()\n\n    ret.gas = cp.vl[\"Throttle\"][\"Throttle_Pedal\"] / 255.\n    ret.gasPressed = ret.gas > 1e-5\n    if self.car_fingerprint in PREGLOBAL_CARS:\n      ret.brakePressed = cp.vl[\"Brake_Pedal\"][\"Brake_Pedal\"] > 2\n    else:\n      ret.brakePressed = cp.vl[\"Brake_Pedal\"][\"Brake_Pedal\"] > 1e-5\n\n    ret.wheelSpeeds.fl = cp.vl[\"Wheel_Speeds\"][\"FL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = cp.vl[\"Wheel_Speeds\"][\"FR\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = cp.vl[\"Wheel_Speeds\"][\"RL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = cp.vl[\"Wheel_Speeds\"][\"RR\"] * CV.KPH_TO_MS\n    ret.vEgoRaw = (ret.wheelSpeeds.fl + ret.wheelSpeeds.fr + ret.wheelSpeeds.rl + ret.wheelSpeeds.rr) / 4.\n    # Kalman filter, even though Subaru raw wheel speed is heaviliy filtered by default\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n    ret.standstill = ret.vEgoRaw < 0.01\n\n    # continuous blinker signals for assisted lane change\n    ret.leftBlinker, ret.rightBlinker = self.update_blinker_from_lamp(\n      50, cp.vl[\"Dashlights\"][\"LEFT_BLINKER\"], cp.vl[\"Dashlights\"][\"RIGHT_BLINKER\"])\n\n    if self.CP.enableBsm:\n      ret.leftBlindspot = (cp.vl[\"BSD_RCTA\"][\"L_ADJACENT\"] == 1) or (cp.vl[\"BSD_RCTA\"][\"L_APPROACHING\"] == 1)\n      ret.rightBlindspot = (cp.vl[\"BSD_RCTA\"][\"R_ADJACENT\"] == 1) or (cp.vl[\"BSD_RCTA\"][\"R_APPROACHING\"] == 1)\n\n    can_gear = int(cp.vl[\"Transmission\"][\"Gear\"])\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(can_gear, None))\n\n    ret.steeringAngleDeg = cp.vl[\"Steering_Torque\"][\"Steering_Angle\"]\n    ret.steeringTorque = cp.vl[\"Steering_Torque\"][\"Steer_Torque_Sensor\"]\n    ret.steeringPressed = abs(ret.steeringTorque) > STEER_THRESHOLD[self.car_fingerprint]\n\n    ret.cruiseState.enabled = cp.vl[\"CruiseControl\"][\"Cruise_Activated\"] != 0\n    ret.cruiseState.available = cp.vl[\"CruiseControl\"][\"Cruise_On\"] != 0\n    ret.cruiseState.speed = cp_cam.vl[\"ES_DashStatus\"][\"Cruise_Set_Speed\"] * CV.KPH_TO_MS\n\n    if (self.car_fingerprint in PREGLOBAL_CARS and cp.vl[\"Dash_State2\"][\"UNITS\"] == 1) or \\\n       (self.car_fingerprint not in PREGLOBAL_CARS and cp.vl[\"Dashlights\"][\"UNITS\"] == 1):\n      ret.cruiseState.speed *= CV.MPH_TO_KPH\n\n    ret.seatbeltUnlatched = cp.vl[\"Dashlights\"][\"SEATBELT_FL\"] == 1\n    ret.doorOpen = any([cp.vl[\"BodyInfo\"][\"DOOR_OPEN_RR\"],\n                        cp.vl[\"BodyInfo\"][\"DOOR_OPEN_RL\"],\n                        cp.vl[\"BodyInfo\"][\"DOOR_OPEN_FR\"],\n                        cp.vl[\"BodyInfo\"][\"DOOR_OPEN_FL\"]])\n    ret.steerError = cp.vl[\"Steering_Torque\"][\"Steer_Error_1\"] == 1\n\n    if self.car_fingerprint in PREGLOBAL_CARS:\n      self.cruise_button = cp_cam.vl[\"ES_CruiseThrottle\"][\"Cruise_Button\"]\n      self.ready = not cp_cam.vl[\"ES_DashStatus\"][\"Not_Ready_Startup\"]\n      self.es_accel_msg = copy.copy(cp_cam.vl[\"ES_CruiseThrottle\"])\n    else:\n      ret.steerWarning = cp.vl[\"Steering_Torque\"][\"Steer_Warning\"] == 1\n      ret.cruiseState.nonAdaptive = cp_cam.vl[\"ES_DashStatus\"][\"Conventional_Cruise\"] == 1\n      self.es_distance_msg = copy.copy(cp_cam.vl[\"ES_Distance\"])\n      self.es_lkas_msg = copy.copy(cp_cam.vl[\"ES_LKAS_State\"])\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    # this function generates lists for signal, messages and initial values\n    signals = [\n      # sig_name, sig_address, default\n      (\"Steer_Torque_Sensor\", \"Steering_Torque\", 0),\n      (\"Steering_Angle\", \"Steering_Torque\", 0),\n      (\"Steer_Error_1\", \"Steering_Torque\", 0),\n      (\"Cruise_On\", \"CruiseControl\", 0),\n      (\"Cruise_Activated\", \"CruiseControl\", 0),\n      (\"Brake_Pedal\", \"Brake_Pedal\", 0),\n      (\"Throttle_Pedal\", \"Throttle\", 0),\n      (\"LEFT_BLINKER\", \"Dashlights\", 0),\n      (\"RIGHT_BLINKER\", \"Dashlights\", 0),\n      (\"SEATBELT_FL\", \"Dashlights\", 0),\n      (\"FL\", \"Wheel_Speeds\", 0),\n      (\"FR\", \"Wheel_Speeds\", 0),\n      (\"RL\", \"Wheel_Speeds\", 0),\n      (\"RR\", \"Wheel_Speeds\", 0),\n      (\"DOOR_OPEN_FR\", \"BodyInfo\", 1),\n      (\"DOOR_OPEN_FL\", \"BodyInfo\", 1),\n      (\"DOOR_OPEN_RR\", \"BodyInfo\", 1),\n      (\"DOOR_OPEN_RL\", \"BodyInfo\", 1),\n      (\"Gear\", \"Transmission\", 0),\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"Throttle\", 100),\n      (\"Dashlights\", 10),\n      (\"Brake_Pedal\", 50),\n      (\"Wheel_Speeds\", 50),\n      (\"Transmission\", 100),\n      (\"Steering_Torque\", 50),\n      (\"BodyInfo\", 1),\n    ]\n\n    if CP.enableBsm:\n      signals += [\n        (\"L_ADJACENT\", \"BSD_RCTA\", 0),\n        (\"R_ADJACENT\", \"BSD_RCTA\", 0),\n        (\"L_APPROACHING\", \"BSD_RCTA\", 0),\n        (\"R_APPROACHING\", \"BSD_RCTA\", 0),\n      ]\n      checks += [\n        (\"BSD_RCTA\", 17),\n      ]\n\n    if CP.carFingerprint not in PREGLOBAL_CARS:\n      signals += [\n        (\"Steer_Warning\", \"Steering_Torque\", 0),\n        (\"UNITS\", \"Dashlights\", 0),\n      ]\n\n      checks += [\n        (\"Dashlights\", 10),\n        (\"BodyInfo\", 10),\n        (\"CruiseControl\", 20),\n      ]\n    else:\n      signals += [\n        (\"UNITS\", \"Dash_State2\", 0),\n      ]\n\n      checks += [\n        (\"Dash_State2\", 1),\n      ]\n\n    if CP.carFingerprint == CAR.FORESTER_PREGLOBAL:\n      checks += [\n        (\"Dashlights\", 20),\n        (\"BodyInfo\", 1),\n        (\"CruiseControl\", 50),\n      ]\n\n    if CP.carFingerprint in [CAR.LEGACY_PREGLOBAL, CAR.OUTBACK_PREGLOBAL, CAR.OUTBACK_PREGLOBAL_2018]:\n      checks += [\n        (\"Dashlights\", 10),\n        (\"CruiseControl\", 50),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    if CP.carFingerprint in PREGLOBAL_CARS:\n      signals = [\n        (\"Cruise_Set_Speed\", \"ES_DashStatus\", 0),\n        (\"Not_Ready_Startup\", \"ES_DashStatus\", 0),\n\n        (\"Throttle_Cruise\", \"ES_CruiseThrottle\", 0),\n        (\"Signal1\", \"ES_CruiseThrottle\", 0),\n        (\"Cruise_Activated\", \"ES_CruiseThrottle\", 0),\n        (\"Signal2\", \"ES_CruiseThrottle\", 0),\n        (\"Brake_On\", \"ES_CruiseThrottle\", 0),\n        (\"Distance_Swap\", \"ES_CruiseThrottle\", 0),\n        (\"Standstill\", \"ES_CruiseThrottle\", 0),\n        (\"Signal3\", \"ES_CruiseThrottle\", 0),\n        (\"Close_Distance\", \"ES_CruiseThrottle\", 0),\n        (\"Signal4\", \"ES_CruiseThrottle\", 0),\n        (\"Standstill_2\", \"ES_CruiseThrottle\", 0),\n        (\"Cruise_Fault\", \"ES_CruiseThrottle\", 0),\n        (\"Signal5\", \"ES_CruiseThrottle\", 0),\n        (\"Counter\", \"ES_CruiseThrottle\", 0),\n        (\"Signal6\", \"ES_CruiseThrottle\", 0),\n        (\"Cruise_Button\", \"ES_CruiseThrottle\", 0),\n        (\"Signal7\", \"ES_CruiseThrottle\", 0),\n      ]\n\n      checks = [\n        (\"ES_DashStatus\", 20),\n        (\"ES_CruiseThrottle\", 20),\n      ]\n    else:\n      signals = [\n        (\"Cruise_Set_Speed\", \"ES_DashStatus\", 0),\n        (\"Conventional_Cruise\", \"ES_DashStatus\", 0),\n\n        (\"Counter\", \"ES_Distance\", 0),\n        (\"Signal1\", \"ES_Distance\", 0),\n        (\"Cruise_Fault\", \"ES_Distance\", 0),\n        (\"Cruise_Throttle\", \"ES_Distance\", 0),\n        (\"Signal2\", \"ES_Distance\", 0),\n        (\"Car_Follow\", \"ES_Distance\", 0),\n        (\"Signal3\", \"ES_Distance\", 0),\n        (\"Cruise_Brake_Active\", \"ES_Distance\", 0),\n        (\"Distance_Swap\", \"ES_Distance\", 0),\n        (\"Cruise_EPB\", \"ES_Distance\", 0),\n        (\"Signal4\", \"ES_Distance\", 0),\n        (\"Close_Distance\", \"ES_Distance\", 0),\n        (\"Signal5\", \"ES_Distance\", 0),\n        (\"Cruise_Cancel\", \"ES_Distance\", 0),\n        (\"Cruise_Set\", \"ES_Distance\", 0),\n        (\"Cruise_Resume\", \"ES_Distance\", 0),\n        (\"Signal6\", \"ES_Distance\", 0),\n\n        (\"Counter\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Alert_Msg\", \"ES_LKAS_State\", 0),\n        (\"Signal1\", \"ES_LKAS_State\", 0),\n        (\"LKAS_ACTIVE\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Dash_State\", \"ES_LKAS_State\", 0),\n        (\"Signal2\", \"ES_LKAS_State\", 0),\n        (\"Backward_Speed_Limit_Menu\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Left_Line_Enable\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Left_Line_Light_Blink\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Right_Line_Enable\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Right_Line_Light_Blink\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Left_Line_Visible\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Right_Line_Visible\", \"ES_LKAS_State\", 0),\n        (\"LKAS_Alert\", \"ES_LKAS_State\", 0),\n        (\"Signal3\", \"ES_LKAS_State\", 0),\n      ]\n\n      checks = [\n        (\"ES_DashStatus\", 10),\n        (\"ES_Distance\", 20),\n        (\"ES_LKAS_State\", 10),\n      ]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n"
  },
  {
    "path": "selfdrive/car/subaru/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.car.subaru.values import CAR, PREGLOBAL_CARS\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\nclass CarInterface(CarInterfaceBase):\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n\n    ret.carName = \"subaru\"\n    ret.radarOffCan = True\n    ret.lateralTuning.init('pid')\n\n    if candidate in PREGLOBAL_CARS:\n      ret.safetyModel = car.CarParams.SafetyModel.subaruLegacy\n      ret.enableBsm = 0x25c in fingerprint[0]\n    else:\n      ret.safetyModel = car.CarParams.SafetyModel.subaru\n      ret.enableBsm = 0x228 in fingerprint[0]\n\n    # Subaru port is a community feature, since we don't own one to test\n    ret.communityFeature = True\n    ret.dashcamOnly = candidate in PREGLOBAL_CARS\n\n    ret.steerRateCost = 0.7\n    ret.steerLimitTimer = 0.4\n\n    if candidate == CAR.ASCENT:\n      ret.mass = 2031. + STD_CARGO_KG\n      ret.wheelbase = 2.89\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 13.5\n      ret.steerActuatorDelay = 0.3   # end-to-end angle controller\n      ret.lateralTuning.pid.kf = 0.00003\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0., 20.], [0., 20.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.0025, 0.1], [0.00025, 0.01]]\n\n    if candidate == CAR.IMPREZA:\n      ret.mass = 1568. + STD_CARGO_KG\n      ret.wheelbase = 2.67\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 15\n      ret.steerActuatorDelay = 0.4   # end-to-end angle controller\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0., 20.], [0., 20.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.2, 0.3], [0.02, 0.03]]\n\n    if candidate == CAR.FORESTER:\n      ret.mass = 1568. + STD_CARGO_KG\n      ret.wheelbase = 2.67\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 17           # learned, 14 stock\n      ret.steerActuatorDelay = 0.1\n      ret.lateralTuning.pid.kf = 0.000038\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0., 14., 23.], [0., 14., 23.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.01, 0.065, 0.2], [0.001, 0.015, 0.025]]\n\n    if candidate in [CAR.FORESTER_PREGLOBAL, CAR.OUTBACK_PREGLOBAL_2018]:\n      ret.safetyParam = 1  # Outback 2018-2019 and Forester have reversed driver torque signal\n      ret.mass = 1568 + STD_CARGO_KG\n      ret.wheelbase = 2.67\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 20           # learned, 14 stock\n      ret.steerActuatorDelay = 0.1\n      ret.lateralTuning.pid.kf = 0.000039\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0., 10., 20.], [0., 10., 20.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.01, 0.05, 0.2], [0.003, 0.018, 0.025]]\n\n    if candidate == CAR.LEGACY_PREGLOBAL:\n      ret.mass = 1568 + STD_CARGO_KG\n      ret.wheelbase = 2.67\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 12.5   # 14.5 stock\n      ret.steerActuatorDelay = 0.15\n      ret.lateralTuning.pid.kf = 0.00005\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0., 20.], [0., 20.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.1, 0.2], [0.01, 0.02]]\n\n    if candidate == CAR.OUTBACK_PREGLOBAL:\n      ret.mass = 1568 + STD_CARGO_KG\n      ret.wheelbase = 2.67\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 20           # learned, 14 stock\n      ret.steerActuatorDelay = 0.1\n      ret.lateralTuning.pid.kf = 0.000039\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0., 10., 20.], [0., 10., 20.]]\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.01, 0.05, 0.2], [0.003, 0.018, 0.025]]\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront)\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n    ret.steeringRateLimited = self.CC.steer_rate_limited if self.CC is not None else False\n\n    ret.events = self.create_common_events(ret).to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  def apply(self, c):\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, c.actuators,\n                               c.cruiseControl.cancel, c.hudControl.visualAlert,\n                               c.hudControl.leftLaneVisible, c.hudControl.rightLaneVisible, c.hudControl.leftLaneDepart, c.hudControl.rightLaneDepart, self.dragonconf)\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/subaru/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nclass RadarInterface(RadarInterfaceBase):\n  pass\n"
  },
  {
    "path": "selfdrive/car/subaru/subarucan.py",
    "content": "import copy\nfrom cereal import car\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\ndef create_steering_control(packer, apply_steer, frame, steer_step):\n\n  idx = (frame / steer_step) % 16\n\n  values = {\n    \"Counter\": idx,\n    \"LKAS_Output\": apply_steer,\n    \"LKAS_Request\": 1 if apply_steer != 0 else 0,\n    \"SET_1\": 1\n  }\n\n  return packer.make_can_msg(\"ES_LKAS\", 0, values)\n\ndef create_steering_status(packer, apply_steer, frame, steer_step):\n  return packer.make_can_msg(\"ES_LKAS_State\", 0, {})\n\ndef create_es_distance(packer, es_distance_msg, pcm_cancel_cmd):\n\n  values = copy.copy(es_distance_msg)\n  if pcm_cancel_cmd:\n    values[\"Cruise_Cancel\"] = 1\n\n  return packer.make_can_msg(\"ES_Distance\", 0, values)\n\ndef create_es_lkas(packer, es_lkas_msg, enabled, visual_alert, left_line, right_line, left_lane_depart, right_lane_depart):\n\n  values = copy.copy(es_lkas_msg)\n\n  # Filter the stock LKAS \"Keep hands on wheel\" alert\n  if values[\"LKAS_Alert_Msg\"] == 1:\n    values[\"LKAS_Alert_Msg\"] = 0\n\n  # Filter the stock LKAS sending an audible alert when it turns off LKAS\n  if values[\"LKAS_Alert\"] == 27:\n    values[\"LKAS_Alert\"] = 0\n\n  # Show Keep hands on wheel alert for openpilot steerRequired alert\n  if visual_alert == VisualAlert.steerRequired:\n    values[\"LKAS_Alert_Msg\"] = 1\n\n  # Ensure we don't overwrite potentially more important alerts from stock (e.g. FCW)\n  if visual_alert == VisualAlert.ldw and values[\"LKAS_Alert\"] == 0:\n    if left_lane_depart:\n      values[\"LKAS_Alert\"] = 12 # Left lane departure dash alert\n    elif right_lane_depart:\n      values[\"LKAS_Alert\"] = 11 # Right lane departure dash alert\n\n  if enabled:\n    values[\"LKAS_ACTIVE\"] = 1 # Show LKAS lane lines\n    values[\"LKAS_Dash_State\"] = 2 # Green enabled indicator\n  else:\n     values[\"LKAS_Dash_State\"] = 0 # LKAS Not enabled\n\n  values[\"LKAS_Left_Line_Visible\"] = int(left_line)\n  values[\"LKAS_Right_Line_Visible\"] = int(right_line)\n\n  return packer.make_can_msg(\"ES_LKAS_State\", 0, values)\n\n# *** Subaru Pre-global ***\n\ndef subaru_preglobal_checksum(packer, values, addr):\n  dat = packer.make_can_msg(addr, 0, values)[2]\n  return (sum(dat[:7])) % 256\n\ndef create_preglobal_steering_control(packer, apply_steer, frame, steer_step):\n\n  idx = (frame / steer_step) % 8\n\n  values = {\n    \"Counter\": idx,\n    \"LKAS_Command\": apply_steer,\n    \"LKAS_Active\": 1 if apply_steer != 0 else 0\n  }\n  values[\"Checksum\"] = subaru_preglobal_checksum(packer, values, \"ES_LKAS\")\n\n  return packer.make_can_msg(\"ES_LKAS\", 0, values)\n\ndef create_es_throttle_control(packer, cruise_button, es_accel_msg):\n\n  values = copy.copy(es_accel_msg)\n  values[\"Cruise_Button\"] = cruise_button\n\n  values[\"Checksum\"] = subaru_preglobal_checksum(packer, values, \"ES_CruiseThrottle\")\n\n  return packer.make_can_msg(\"ES_CruiseThrottle\", 0, values)\n"
  },
  {
    "path": "selfdrive/car/subaru/values.py",
    "content": "# flake8: noqa\n\nfrom selfdrive.car import dbc_dict\nfrom cereal import car\nEcu = car.CarParams.Ecu\n\nclass CarControllerParams:\n  STEER_MAX = 2047              # max_steer 4095\n  STEER_STEP = 2                # how often we update the steer cmd\n  STEER_DELTA_UP = 50           # torque increase per refresh, 0.8s to max\n  STEER_DELTA_DOWN = 70         # torque decrease per refresh\n  STEER_DRIVER_ALLOWANCE = 60   # allowed driver torque before start limiting\n  STEER_DRIVER_MULTIPLIER = 10  # weight driver torque heavily\n  STEER_DRIVER_FACTOR = 1       # from dbc\n\nclass CAR:\n  ASCENT = \"SUBARU ASCENT LIMITED 2019\"\n  IMPREZA = \"SUBARU IMPREZA LIMITED 2019\"\n  FORESTER = \"SUBARU FORESTER 2019\"\n  FORESTER_PREGLOBAL = \"SUBARU FORESTER 2017 - 2018\"\n  LEGACY_PREGLOBAL = \"SUBARU LEGACY 2015 - 2018\"\n  OUTBACK_PREGLOBAL = \"SUBARU OUTBACK 2015 - 2017\"\n  OUTBACK_PREGLOBAL_2018 = \"SUBARU OUTBACK 2018 - 2019\"\n\nFINGERPRINTS = {\n  CAR.ASCENT: [{\n  # SUBARU ASCENT LIMITED 2019\n    2: 8, 64: 8, 65: 8, 72: 8, 73: 8, 280: 8, 281: 8, 290: 8, 312: 8, 313: 8, 314: 8, 315: 8, 316: 8, 326: 8, 544: 8, 545: 8, 546: 8, 552: 8, 554: 8, 557: 8, 576: 8, 577: 8, 722: 8, 801: 8, 802: 8, 805: 8, 808: 8, 811: 8, 816: 8, 826: 8, 837: 8, 838: 8, 839: 8, 842: 8, 912: 8, 915: 8, 940: 8, 1614: 8, 1617: 8, 1632: 8, 1650: 8, 1657: 8, 1658: 8, 1677: 8, 1722: 8, 1743: 8, 1759: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8\n  }],\n  CAR.IMPREZA: [{\n    2: 8, 64: 8, 65: 8, 72: 8, 73: 8, 280: 8, 281: 8, 290: 8, 312: 8, 313: 8, 314: 8, 315: 8, 316: 8, 326: 8, 372: 8, 544: 8, 545: 8, 546: 8, 552: 8, 554: 8, 557: 8, 576: 8, 577: 8, 722: 8, 801: 8, 802: 8, 805: 8, 808: 8, 811: 8, 816: 8, 826: 8, 827: 8, 837: 8, 838: 8, 839: 8, 842: 8, 912: 8, 915: 8, 940: 8, 1614: 8, 1617: 8, 1632: 8, 1650: 8, 1657: 8, 1658: 8, 1677: 8, 1697: 8, 1722: 8, 1743: 8, 1759: 8, 1786: 5, 1787: 5, 1788: 8, 1809: 8, 1813: 8, 1817: 8, 1821: 8, 1840: 8, 1848: 8, 1924: 8, 1932: 8, 1952: 8, 1960: 8\n  }],\n  CAR.FORESTER: [{\n  # Forester 2019-2020\n    2: 8, 64: 8, 65: 8, 72: 8, 73: 8, 280: 8, 281: 8, 282: 8, 290: 8, 312: 8, 313: 8, 314: 8, 315: 8, 316: 8, 326: 8, 372: 8, 544: 8, 545: 8, 546: 8, 552: 8, 554: 8, 557: 8, 576: 8, 577: 8, 722: 8, 801: 8, 802: 8, 803: 8, 805: 8, 808: 8, 811: 8, 816: 8, 826: 8, 837: 8, 838: 8, 839: 8, 842: 8, 912: 8, 915: 8, 940: 8, 961: 8, 984: 8, 1614: 8, 1617: 8, 1632: 8, 1650: 8, 1651: 8, 1657: 8, 1658: 8, 1677: 8, 1697: 8, 1698: 8, 1722: 8, 1743: 8, 1759: 8, 1787: 5, 1788: 8, 1809: 8, 1813: 8, 1817: 8, 1821: 8, 1840: 8, 1848: 8, 1924: 8, 1932: 8, 1952: 8, 1960: 8\n  }],\n  CAR.OUTBACK_PREGLOBAL: [{\n  # OUTBACK PREMIUM 2.5i 2015\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 346: 8, 352: 8, 353: 8, 354: 8, 356: 8, 358: 8, 359: 8, 392: 8, 640: 8, 642: 8, 644: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 977: 8, 1632: 8, 1745: 8, 1786: 5, 1882: 8, 2015: 8, 2016: 8, 2024: 8, 604: 8, 885: 8, 1788: 8, 316: 8, 1614: 8, 1640: 8, 1657: 8, 1658: 8, 1672: 8, 1743: 8, 1785: 5, 1787: 5\n  },\n  # OUTBACK PREMIUM 3.6i 2015\n  {\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 392: 8, 604: 8, 640: 8, 642: 8, 644: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 977: 8, 1632: 8, 1745: 8, 1779: 8, 1786: 5\n  },\n  # OUTBACK LIMITED 2.5i 2018\n  {\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 316: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 352: 8, 353: 8, 354: 8, 356: 8, 358: 8, 359: 8, 392: 8, 554: 8, 604: 8, 640: 8, 642: 8, 644: 8, 805: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 977: 8, 1614: 8, 1632: 8, 1657: 8, 1658: 8, 1672: 8, 1722: 8, 1736: 8, 1743: 8, 1745: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8\n  }],\n  CAR.OUTBACK_PREGLOBAL_2018: [{\n  # OUTBACK LIMITED 3.6R 2019\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 316: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 352: 8, 353: 8, 354: 8, 356: 8, 358: 8, 359: 8, 392: 8, 554: 8, 604: 8, 640: 8, 642: 8, 644: 8, 805: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 886: 2, 977: 8, 1614: 8, 1632: 8, 1657: 8, 1658: 8, 1672: 8, 1736: 8, 1743: 8, 1745: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8, 1862: 8, 1870: 8, 1920: 8, 1927: 8, 1928: 8, 1935: 8, 1968: 8, 1976: 8, 2016: 8, 2017: 8, 2024: 8, 2025: 8\n  },\n  # OUTBACK 2.5i-ES 2019 - Taiwan\n  {\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 316: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 346: 8, 352: 8, 353: 8, 354: 8, 356: 8, 358: 8, 359: 8, 392: 8, 554: 8, 604: 8, 640: 8, 642: 8, 644: 8, 805: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 886: 2, 977: 8, 1614: 8, 1632: 8, 1640: 8, 1657: 8, 1658: 8, 1672: 8, 1722: 8, 1736: 8, 1745: 8, 1786: 5, 1787: 5\n  }],\n  CAR.FORESTER_PREGLOBAL: [{\n  # FORESTER PREMIUM 2.5i 2017\n    2: 8, 112: 8, 117: 8, 128: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 340: 7, 342: 8, 352: 8, 353: 8, 354: 8, 355: 8, 356: 8, 554: 8, 604: 8, 640: 8, 641: 8, 642: 8, 805: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 886: 1, 888: 8, 977: 8, 1398: 8, 1632: 8, 1743: 8, 1744: 8, 1745: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8, 1882: 8, 1895: 8, 1903: 8, 1986: 8, 1994: 8, 2015: 8, 2016: 8, 2024: 8, 644:8, 890:8, 1736:8\n  }],\n  CAR.LEGACY_PREGLOBAL: [{\n  # LEGACY 2.5i 2017\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 392: 8, 604: 8, 640: 8, 642: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 977: 8, 1632: 8, 1640: 8, 1736: 8, 1745: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8, 352: 8, 353: 8, 354: 8, 356: 8, 358: 8, 359: 8, 644: 8\n  },\n  # LEGACY 2018\n  {\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 316: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 392: 8, 604: 8, 640: 8, 642: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 977: 8, 1614: 8, 1632: 8, 1640: 8, 1657: 8, 1658: 8, 1672: 8, 1722: 8, 1743: 8, 1745: 8, 1778: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8, 2015: 8, 2016: 8, 2024: 8\n  },\n  # LEGACY 2018\n  {\n    2: 8, 208: 8, 209: 4, 210: 8, 211: 7, 212: 8, 316: 8, 320: 8, 321: 8, 324: 8, 328: 8, 329: 8, 336: 2, 338: 8, 342: 8, 352: 8, 353: 8, 354: 8, 356: 8, 358: 8, 359: 8, 392: 8, 554: 8, 604: 8, 640: 8, 642: 8, 805: 8, 864: 8, 865: 8, 866: 8, 872: 8, 880: 8, 881: 8, 882: 8, 884: 8, 885: 8, 977: 8, 1614: 8, 1632: 8, 1640: 8, 1657: 8, 1658: 8, 1672: 8, 1722: 8, 1743: 8, 1745: 8, 1785: 5, 1786: 5, 1787: 5, 1788: 8, 2015: 8, 2016: 8, 2024: 8\n  }],\n}\n\nSTEER_THRESHOLD = {\n  CAR.ASCENT: 80,\n  CAR.IMPREZA: 80,\n  CAR.FORESTER: 80,\n  CAR.FORESTER_PREGLOBAL: 75,\n  CAR.LEGACY_PREGLOBAL: 75,\n  CAR.OUTBACK_PREGLOBAL: 75,\n  CAR.OUTBACK_PREGLOBAL_2018: 75,\n}\n\nDBC = {\n  CAR.ASCENT: dbc_dict('subaru_global_2017_generated', None),\n  CAR.IMPREZA: dbc_dict('subaru_global_2017_generated', None),\n  CAR.FORESTER: dbc_dict('subaru_global_2017_generated', None),\n  CAR.FORESTER_PREGLOBAL: dbc_dict('subaru_forester_2017_generated', None),\n  CAR.LEGACY_PREGLOBAL: dbc_dict('subaru_outback_2015_generated', None),\n  CAR.OUTBACK_PREGLOBAL: dbc_dict('subaru_outback_2015_generated', None),\n  CAR.OUTBACK_PREGLOBAL_2018: dbc_dict('subaru_outback_2019_generated', None),\n}\n\nPREGLOBAL_CARS = [CAR.FORESTER_PREGLOBAL, CAR.LEGACY_PREGLOBAL, CAR.OUTBACK_PREGLOBAL, CAR.OUTBACK_PREGLOBAL_2018]\n"
  },
  {
    "path": "selfdrive/car/tesla/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/tesla/carcontroller.py",
    "content": "from common.numpy_fast import clip, interp\nfrom selfdrive.car.tesla.teslacan import TeslaCAN\nfrom opendbc.can.packer import CANPacker\nfrom selfdrive.car.tesla.values import CANBUS, CarControllerParams\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    self.CP = CP\n    self.last_angle = 0\n    self.packer = CANPacker(dbc_name)\n    self.tesla_can = TeslaCAN(dbc_name, self.packer)\n\n  def update(self, enabled, CS, frame, actuators, cruise_cancel):\n    can_sends = []\n\n    # Temp disable steering on a hands_on_fault, and allow for user override\n    hands_on_fault = (CS.steer_warning == \"EAC_ERROR_HANDS_ON\" and CS.hands_on_level >= 3)\n    lkas_enabled = enabled and (not hands_on_fault)\n\n    if lkas_enabled:\n      apply_angle = actuators.steeringAngleDeg\n\n      # Angular rate limit based on speed\n      steer_up = (self.last_angle * apply_angle > 0. and abs(apply_angle) > abs(self.last_angle))\n      rate_limit = CarControllerParams.RATE_LIMIT_UP if steer_up else CarControllerParams.RATE_LIMIT_DOWN\n      max_angle_diff = interp(CS.out.vEgo, rate_limit.speed_points, rate_limit.max_angle_diff_points)\n      apply_angle = clip(apply_angle, (self.last_angle - max_angle_diff), (self.last_angle + max_angle_diff))\n\n      # To not fault the EPS\n      apply_angle = clip(apply_angle, (CS.out.steeringAngleDeg - 20), (CS.out.steeringAngleDeg + 20))\n    else:\n      apply_angle = CS.out.steeringAngleDeg\n\n    self.last_angle = apply_angle\n    can_sends.append(self.tesla_can.create_steering_control(apply_angle, lkas_enabled, frame))\n\n    # Cancel on user steering override, since there is no steering torque blending\n    if hands_on_fault:\n      cruise_cancel = True\n\n    # Cancel when openpilot is not enabled anymore\n    if not enabled and bool(CS.out.cruiseState.enabled):\n      cruise_cancel = True\n\n    if ((frame % 10) == 0 and cruise_cancel):\n      # Spam every possible counter value, otherwise it might not be accepted\n      for counter in range(16):\n        can_sends.append(self.tesla_can.create_action_request(CS.msg_stw_actn_req, cruise_cancel, CANBUS.chassis, counter))\n        can_sends.append(self.tesla_can.create_action_request(CS.msg_stw_actn_req, cruise_cancel, CANBUS.autopilot, counter))\n\n    # TODO: HUD control\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/tesla/carstate.py",
    "content": "import copy\nfrom cereal import car\nfrom selfdrive.car.tesla.values import DBC, CANBUS, GEAR_MAP, DOORS, BUTTONS\nfrom selfdrive.car.interfaces import CarStateBase\nfrom opendbc.can.parser import CANParser\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.config import Conversions as CV\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.button_states = {button.event_type: False for button in BUTTONS}\n    self.can_define = CANDefine(DBC[CP.carFingerprint]['chassis'])\n\n    # Needed by carcontroller\n    self.msg_stw_actn_req = None\n    self.hands_on_level = 0\n    self.steer_warning = None\n\n  def update(self, cp, cp_cam):\n    ret = car.CarState.new_message()\n\n    # Vehicle speed\n    ret.vEgoRaw = cp.vl[\"ESP_B\"][\"ESP_vehicleSpeed\"] * CV.KPH_TO_MS\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n    ret.standstill = (ret.vEgo < 0.1)\n\n    # Gas pedal\n    ret.gas = cp.vl[\"DI_torque1\"][\"DI_pedalPos\"] / 100.0\n    ret.gasPressed = (ret.gas > 0)\n\n    # Brake pedal\n    ret.brake = 0\n    ret.brakePressed = bool(cp.vl[\"BrakeMessage\"][\"driverBrakeStatus\"] != 1)\n\n    # Steering wheel\n    self.hands_on_level = cp.vl[\"EPAS_sysStatus\"][\"EPAS_handsOnLevel\"]\n    self.steer_warning = self.can_define.dv[\"EPAS_sysStatus\"][\"EPAS_eacErrorCode\"].get(int(cp.vl[\"EPAS_sysStatus\"][\"EPAS_eacErrorCode\"]), None)\n    steer_status = self.can_define.dv[\"EPAS_sysStatus\"][\"EPAS_eacStatus\"].get(int(cp.vl[\"EPAS_sysStatus\"][\"EPAS_eacStatus\"]), None)\n\n    ret.steeringAngleDeg = -cp.vl[\"EPAS_sysStatus\"][\"EPAS_internalSAS\"]\n    ret.steeringRateDeg = -cp.vl[\"STW_ANGLHP_STAT\"][\"StW_AnglHP_Spd\"] # This is from a different angle sensor, and at different rate\n    ret.steeringTorque = -cp.vl[\"EPAS_sysStatus\"][\"EPAS_torsionBarTorque\"]\n    ret.steeringPressed = (self.hands_on_level > 0)\n    ret.steerError = steer_status == \"EAC_FAULT\"\n    ret.steerWarning = self.steer_warning in [\"EAC_ERROR_MAX_SPEED\", \"EAC_ERROR_MIN_SPEED\", \"EAC_ERROR_TMP_FAULT\", \"SNA\"]  # TODO: not sure if this list is complete\n\n    # Cruise state\n    cruise_state = self.can_define.dv[\"DI_state\"][\"DI_cruiseState\"].get(int(cp.vl[\"DI_state\"][\"DI_cruiseState\"]), None)\n    speed_units = self.can_define.dv[\"DI_state\"][\"DI_speedUnits\"].get(int(cp.vl[\"DI_state\"][\"DI_speedUnits\"]), None)\n\n    acc_enabled = (cruise_state in [\"ENABLED\", \"STANDSTILL\", \"OVERRIDE\", \"PRE_FAULT\", \"PRE_CANCEL\"])\n\n    ret.cruiseState.enabled = acc_enabled\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    if speed_units == \"KPH\":\n      ret.cruiseState.speed = cp.vl[\"DI_state\"][\"DI_digitalSpeed\"] * CV.KPH_TO_MS\n    elif speed_units == \"MPH\":\n      ret.cruiseState.speed = cp.vl[\"DI_state\"][\"DI_digitalSpeed\"] * CV.MPH_TO_MS\n    ret.cruiseState.available = ((cruise_state == \"STANDBY\") or ret.cruiseState.enabled)\n    ret.cruiseState.standstill = (cruise_state == \"STANDSTILL\")\n\n    # Gear\n    ret.gearShifter = GEAR_MAP[self.can_define.dv[\"DI_torque2\"][\"DI_gear\"].get(int(cp.vl[\"DI_torque2\"][\"DI_gear\"]), \"DI_GEAR_INVALID\")]\n\n    # Buttons\n    buttonEvents = []\n    for button in BUTTONS:\n      state = (cp.vl[button.can_addr][button.can_msg] in button.values)\n      if self.button_states[button.event_type] != state:\n        event = car.CarState.ButtonEvent.new_message()\n        event.type = button.event_type\n        event.pressed = state\n        buttonEvents.append(event)\n      self.button_states[button.event_type] = state\n    ret.buttonEvents = buttonEvents\n\n    # Doors\n    ret.doorOpen = any([(self.can_define.dv[\"GTW_carState\"][door].get(int(cp.vl[\"GTW_carState\"][door]), \"OPEN\") == \"OPEN\") for door in DOORS])\n\n    # Blinkers\n    ret.leftBlinker = (cp.vl[\"GTW_carState\"][\"BC_indicatorLStatus\"] == 1)\n    ret.rightBlinker = (cp.vl[\"GTW_carState\"][\"BC_indicatorRStatus\"] == 1)\n\n    # Seatbelt\n    ret.seatbeltUnlatched = (cp.vl[\"SDM1\"][\"SDM_bcklDrivStatus\"] != 1)\n\n    # TODO: blindspot\n\n    # Messages needed by carcontroller\n    self.msg_stw_actn_req = copy.copy(cp.vl[\"STW_ACTN_RQ\"])\n\n    # dp - brake lights\n    ret.brakeLights = ret.brakePressed\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    signals = [\n      # sig_name, sig_address, default\n      (\"ESP_vehicleSpeed\", \"ESP_B\", 0),\n      (\"DI_pedalPos\", \"DI_torque1\", 0),\n      (\"DI_brakePedal\", \"DI_torque2\", 0),\n      (\"StW_AnglHP\", \"STW_ANGLHP_STAT\", 0),\n      (\"StW_AnglHP_Spd\", \"STW_ANGLHP_STAT\", 0),\n      (\"EPAS_handsOnLevel\", \"EPAS_sysStatus\", 0),\n      (\"EPAS_torsionBarTorque\", \"EPAS_sysStatus\", 0),\n      (\"EPAS_internalSAS\", \"EPAS_sysStatus\", 0),\n      (\"EPAS_eacStatus\", \"EPAS_sysStatus\", 1),\n      (\"EPAS_eacErrorCode\", \"EPAS_sysStatus\", 0),\n      (\"DI_cruiseState\", \"DI_state\", 0),\n      (\"DI_digitalSpeed\", \"DI_state\", 0),\n      (\"DI_speedUnits\", \"DI_state\", 0),\n      (\"DI_gear\", \"DI_torque2\", 0),\n      (\"DOOR_STATE_FL\", \"GTW_carState\", 1),\n      (\"DOOR_STATE_FR\", \"GTW_carState\", 1),\n      (\"DOOR_STATE_RL\", \"GTW_carState\", 1),\n      (\"DOOR_STATE_RR\", \"GTW_carState\", 1),\n      (\"DOOR_STATE_FrontTrunk\", \"GTW_carState\", 1),\n      (\"BOOT_STATE\", \"GTW_carState\", 1),\n      (\"BC_indicatorLStatus\", \"GTW_carState\", 1),\n      (\"BC_indicatorRStatus\", \"GTW_carState\", 1),\n      (\"SDM_bcklDrivStatus\", \"SDM1\", 0),\n      (\"driverBrakeStatus\", \"BrakeMessage\", 0),\n\n      # We copy this whole message when spamming cancel\n      (\"SpdCtrlLvr_Stat\", \"STW_ACTN_RQ\", 0),\n      (\"VSL_Enbl_Rq\", \"STW_ACTN_RQ\", 0),\n      (\"SpdCtrlLvrStat_Inv\", \"STW_ACTN_RQ\", 0),\n      (\"DTR_Dist_Rq\", \"STW_ACTN_RQ\", 0),\n      (\"TurnIndLvr_Stat\", \"STW_ACTN_RQ\", 0),\n      (\"HiBmLvr_Stat\", \"STW_ACTN_RQ\", 0),\n      (\"WprWashSw_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"WprWash_R_Sw_Posn_V2\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Lvr_Stat\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Cond_Flt\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Cond_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"HrnSw_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw00_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw01_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw02_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw03_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw04_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw05_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw06_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw07_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw08_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw09_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw10_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw11_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw12_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw13_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw14_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"StW_Sw15_Psd\", \"STW_ACTN_RQ\", 0),\n      (\"WprSw6Posn\", \"STW_ACTN_RQ\", 0),\n      (\"MC_STW_ACTN_RQ\", \"STW_ACTN_RQ\", 0),\n      (\"CRC_STW_ACTN_RQ\", \"STW_ACTN_RQ\", 0),\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"ESP_B\", 50),\n      (\"DI_torque1\", 100),\n      (\"DI_torque2\", 100),\n      (\"STW_ANGLHP_STAT\", 100),\n      (\"EPAS_sysStatus\", 25),\n      (\"DI_state\", 10),\n      (\"STW_ACTN_RQ\", 10),\n      (\"GTW_carState\", 10),\n      (\"SDM1\", 10),\n      (\"BrakeMessage\", 50),\n    ]\n\n    return CANParser(DBC[CP.carFingerprint]['chassis'], signals, checks, CANBUS.chassis)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n    signals = [\n      # sig_name, sig_address, default\n    ]\n    checks = [\n      # sig_address, frequency\n    ]\n    return CANParser(DBC[CP.carFingerprint]['chassis'], signals, checks, CANBUS.autopilot)\n"
  },
  {
    "path": "selfdrive/car/tesla/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.car.tesla.values import CAR\nfrom selfdrive.car import STD_CARGO_KG, gen_empty_fingerprint, scale_rot_inertia, scale_tire_stiffness\nfrom selfdrive.car.interfaces import CarInterfaceBase\n\n\nclass CarInterface(CarInterfaceBase):\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"tesla\"\n    ret.safetyModel = car.CarParams.SafetyModel.tesla\n\n    # There is no safe way to do steer blending with user torque,\n    # so the steering behaves like autopilot. This is not\n    # how openpilot should be, hence dashcamOnly\n    ret.dashcamOnly = True\n\n    ret.steerControlType = car.CarParams.SteerControlType.angle\n    ret.openpilotLongitudinalControl = False\n    ret.communityFeature = True\n\n    ret.steerActuatorDelay = 0.1\n    ret.steerRateCost = 0.5\n\n    if candidate in [CAR.AP2_MODELS, CAR.AP1_MODELS]:\n      ret.mass = 2100. + STD_CARGO_KG\n      ret.wheelbase = 2.959\n      ret.centerToFront = ret.wheelbase * 0.5\n      ret.steerRatio = 13.5\n    else:\n      raise ValueError(f\"Unsupported car: {candidate}\")\n\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront)\n\n    return ret\n\n  def update(self, c, can_strings):\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam)\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n\n    events = self.create_common_events(ret)\n\n    ret.events = events.to_msg()\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  def apply(self, c):\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, c.actuators, c.cruiseControl.cancel)\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/tesla/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.car.tesla.values import DBC, CANBUS\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nRADAR_MSGS_A = list(range(0x310, 0x36E, 3))\nRADAR_MSGS_B = list(range(0x311, 0x36F, 3))\nNUM_POINTS = len(RADAR_MSGS_A)\n\ndef get_radar_can_parser(CP):\n  # Status messages\n  signals = [\n    ('RADC_HWFail', 'TeslaRadarSguInfo', 0),\n    ('RADC_SGUFail', 'TeslaRadarSguInfo', 0),\n    ('RADC_SensorDirty', 'TeslaRadarSguInfo', 0),\n  ]\n\n  checks = [\n    ('TeslaRadarSguInfo', 10),\n  ]\n\n  # Radar tracks. There are also raw point clouds available,\n  # we don't use those.\n  for i in range(NUM_POINTS):\n    msg_id_a = RADAR_MSGS_A[i]\n    msg_id_b = RADAR_MSGS_B[i]\n\n    # There is a bunch more info in the messages,\n    # but these are the only things actually used in openpilot\n    signals.extend([\n      ('LongDist', msg_id_a, 255),\n      ('LongSpeed', msg_id_a, 0),\n      ('LatDist', msg_id_a, 0),\n      ('LongAccel', msg_id_a, 0),\n      ('Meas', msg_id_a, 0),\n      ('Tracked', msg_id_a, 0),\n      ('Index', msg_id_a, 0),\n\n      ('LatSpeed', msg_id_b, 0),\n      ('Index2', msg_id_b, 0),\n    ])\n\n    checks.extend([\n      (msg_id_a, 8),\n      (msg_id_b, 8),\n    ])\n\n  return CANParser(DBC[CP.carFingerprint]['radar'], signals, checks, CANBUS.radar)\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.rcp = get_radar_can_parser(CP)\n    self.updated_messages = set()\n    self.track_id = 0\n    self.trigger_msg = RADAR_MSGS_B[-1]\n\n  def update(self, can_strings):\n    if self.rcp is None:\n      return super().update(None)\n\n    values = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(values)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    ret = car.RadarData.new_message()\n\n    # Errors\n    errors = []\n    sgu_info = self.rcp.vl['TeslaRadarSguInfo']\n    if not self.rcp.can_valid:\n      errors.append('canError')\n    if sgu_info['RADC_HWFail'] or sgu_info['RADC_SGUFail'] or sgu_info['RADC_SensorDirty']:\n      errors.append('fault')\n    ret.errors = errors\n\n    # Radar tracks\n    for i in range(NUM_POINTS):\n      msg_a = self.rcp.vl[RADAR_MSGS_A[i]]\n      msg_b = self.rcp.vl[RADAR_MSGS_B[i]]\n\n      # Make sure msg A and B are together\n      if msg_a['Index'] != msg_b['Index2']:\n        continue\n\n      # Check if it's a valid track\n      if not msg_a['Tracked']:\n        if i in self.pts:\n          del self.pts[i]\n        continue\n\n      # New track!\n      if i not in self.pts:\n        self.pts[i] = car.RadarData.RadarPoint.new_message()\n        self.pts[i].trackId = self.track_id\n        self.track_id += 1\n\n      # Parse track data\n      self.pts[i].dRel = msg_a['LongDist']\n      self.pts[i].yRel = msg_a['LatDist']\n      self.pts[i].vRel = msg_a['LongSpeed']\n      self.pts[i].aRel = msg_a['LongAccel']\n      self.pts[i].yvRel = msg_b['LatSpeed']\n      self.pts[i].measured = bool(msg_a['Meas'])\n\n    ret.points = list(self.pts.values())\n    self.updated_messages.clear()\n    return ret\n"
  },
  {
    "path": "selfdrive/car/tesla/teslacan.py",
    "content": "import copy\nimport crcmod\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.car.tesla.values import CANBUS\n\n\nclass TeslaCAN:\n  def __init__(self, dbc_name, packer):\n    self.can_define = CANDefine(dbc_name)\n    self.packer = packer\n    self.crc = crcmod.mkCrcFun(0x11d, initCrc=0x00, rev=False, xorOut=0xff)\n\n  @staticmethod\n  def checksum(msg_id, dat):\n    # TODO: get message ID from name instead\n    ret = (msg_id & 0xFF) + ((msg_id >> 8) & 0xFF)\n    ret += sum(dat)\n    return ret & 0xFF\n\n  def create_steering_control(self, angle, enabled, frame):\n    values = {\n      \"DAS_steeringAngleRequest\": -angle,\n      \"DAS_steeringHapticRequest\": 0,\n      \"DAS_steeringControlType\": 1 if enabled else 0,\n      \"DAS_steeringControlCounter\": (frame % 16),\n    }\n\n    data = self.packer.make_can_msg(\"DAS_steeringControl\", CANBUS.chassis, values)[2]\n    values[\"DAS_steeringControlChecksum\"] = self.checksum(0x488, data[:3])\n    return self.packer.make_can_msg(\"DAS_steeringControl\", CANBUS.chassis, values)\n\n  def create_action_request(self, msg_stw_actn_req, cancel, bus, counter):\n    values = copy.copy(msg_stw_actn_req)\n\n    if cancel:\n      values[\"SpdCtrlLvr_Stat\"] = 1\n      values[\"MC_STW_ACTN_RQ\"] = counter\n\n    data = self.packer.make_can_msg(\"STW_ACTN_RQ\", bus, values)[2]\n    values[\"CRC_STW_ACTN_RQ\"] = self.crc(data[:7])\n    return self.packer.make_can_msg(\"STW_ACTN_RQ\", bus, values)\n"
  },
  {
    "path": "selfdrive/car/tesla/values.py",
    "content": "# flake8: noqa\n\nfrom collections import namedtuple\nfrom selfdrive.car import dbc_dict\nfrom cereal import car\n\nButton = namedtuple('Button', ['event_type', 'can_addr', 'can_msg', 'values'])\nAngleRateLimit = namedtuple('AngleRateLimit', ['speed_points', 'max_angle_diff_points'])\n\nclass CAR:\n  AP1_MODELS = 'TESLA AP1 MODEL S'\n  AP2_MODELS = 'TESLA AP2 MODEL S'\n\nFINGERPRINTS = {\n  CAR.AP2_MODELS: [\n    {\n      1: 8, 3: 8, 14: 8, 21: 4, 69: 8, 109: 4, 257: 3, 264: 8, 277: 6, 280: 6, 293: 4, 296: 4, 309: 5, 325: 8, 328: 5, 336: 8, 341: 8, 360: 7, 373: 8, 389: 8, 415: 8, 513: 5, 516: 8, 518: 8, 520: 4, 522: 8, 524: 8, 526: 8, 532: 3, 536: 8, 537: 3, 542: 8, 551: 5, 552: 2, 556: 8, 558: 8, 568: 8, 569: 8, 574: 8, 577: 8, 582: 5, 583: 8, 584: 4, 585: 8, 590: 8, 601: 8, 606: 8, 608: 1, 622: 8, 627: 6, 638: 8, 641: 8, 643: 8, 692: 8, 693: 8, 695: 8, 696: 8, 697: 8, 699: 8, 700: 8, 701: 8, 702: 8, 703: 8, 704: 8, 708: 8, 709: 8, 710: 8, 711: 8, 712: 8, 728: 8, 744: 8, 760: 8, 772: 8, 775: 8, 776: 8, 777: 8, 778: 8, 782: 8, 788: 8, 791: 8, 792: 8, 796: 2, 797: 8, 798: 6, 799: 8, 804: 8, 805: 8, 807: 8, 808: 1, 811: 8, 812: 8, 813: 8, 814: 5, 815: 8, 820: 8, 823: 8, 824: 8, 829: 8, 830: 5, 836: 8, 840: 8, 845: 8, 846: 5, 848: 8, 852: 8, 853: 8, 856: 4, 857: 6, 861: 8, 862: 5, 872: 8, 876: 8, 877: 8, 879: 8, 880: 8, 882: 8, 884: 8, 888: 8, 893: 8, 894: 8, 901: 6, 904: 3, 905: 8, 906: 8, 908: 2, 909: 8, 910: 8, 912: 8, 920: 8, 921: 8, 925: 4, 926: 6, 936: 8, 941: 8, 949: 8, 952: 8, 953: 6, 968: 8, 969: 6, 970: 8, 971: 8, 977: 8, 984: 8, 987: 8, 990: 8, 1000: 8, 1001: 8, 1006: 8, 1007: 8, 1008: 8, 1010: 6, 1014: 1, 1015: 8, 1016: 8, 1017: 8, 1018: 8, 1020: 8, 1026: 8, 1028: 8, 1029: 8, 1030: 8, 1032: 1, 1033: 1, 1034: 8, 1048: 1, 1049: 8, 1061: 8, 1064: 8, 1065: 8, 1070: 8, 1080: 8, 1081: 8, 1097: 8, 1113: 8, 1129: 8, 1145: 8, 1160: 4, 1177: 8, 1281: 8, 1328: 8, 1329: 8, 1332: 8, 1335: 8, 1337: 8, 1353: 8, 1368: 8, 1412: 8, 1436: 8, 1476: 8, 1481: 8, 1497: 8, 1513: 8, 1519: 8, 1601: 8, 1605: 8, 1617: 8, 1621: 8, 1800: 4, 1804: 8, 1812: 8, 1815: 8, 1816: 8, 1824: 8, 1828: 8, 1831: 8, 1832: 8, 1864: 8, 1880: 8, 1892: 8, 1896: 8, 1912: 8, 1960: 8, 1992: 8, 2008: 3, 2043: 5, 2045: 4\n    },\n  ],\n  CAR.AP1_MODELS: [\n    {\n      1: 8, 3: 8, 14: 8, 21: 4, 69: 8, 109: 4, 257: 3, 264: 8, 267: 5, 277: 6, 280: 6, 283: 5, 293: 4, 296: 4, 309: 5, 325: 8, 328: 5, 336: 8, 341: 8, 360: 7, 373: 8, 389: 8, 415: 8, 513: 5, 516: 8, 520: 4, 522: 8, 524: 8, 526: 8, 532: 3, 536: 8, 537: 3, 542: 8, 551: 5, 552: 2, 556: 8, 558: 8, 568: 8, 569: 8, 574: 8, 577: 8, 582: 5, 584: 4, 585: 8, 590: 8, 606: 8, 622: 8, 627: 6, 638: 8, 641: 8, 643: 8, 660: 5, 693: 8, 696: 8, 697: 8, 712: 8, 728: 8, 744: 8, 760: 8, 772: 8, 775: 8, 776: 8, 777: 8, 778: 8, 782: 8, 788: 8, 791: 8, 792: 8, 796: 2, 797: 8, 798: 6, 799: 8, 804: 8, 805: 8, 807: 8, 808: 1, 809: 8, 812: 8, 813: 8, 814: 5, 815: 8, 820: 8, 823: 8, 824: 8, 829: 8, 830: 5, 836: 8, 840: 8, 841: 8, 845: 8, 846: 5, 852: 8, 856: 4, 857: 6, 861: 8, 862: 5, 872: 8, 873: 8, 877: 8, 878: 8, 879: 8, 880: 8, 884: 8, 888: 8, 889: 8, 893: 8, 896: 8, 901: 6, 904: 3, 905: 8, 908: 2, 909: 8, 920: 8, 921: 8, 925: 4, 936: 8, 937: 8, 941: 8, 949: 8, 952: 8, 953: 6, 957: 8, 968: 8, 973: 8, 984: 8, 987: 8, 989: 8, 990: 8, 1000: 8, 1001: 8, 1006: 8, 1016: 8, 1026: 8, 1028: 8, 1029: 8, 1030: 8, 1032: 1, 1033: 1, 1034: 8, 1048: 1, 1064: 8, 1070: 8, 1080: 8, 1160: 4, 1281: 8, 1329: 8, 1332: 8, 1335: 8, 1337: 8, 1368: 8, 1412: 8, 1436: 8, 1465: 8, 1476: 8, 1497: 8, 1524: 8, 1527: 8, 1601: 8, 1605: 8, 1611: 8, 1614: 8, 1617: 8, 1621: 8, 1627: 8, 1630: 8, 1800: 4, 1804: 8, 1812: 8, 1815: 8, 1816: 8, 1828: 8, 1831: 8, 1832: 8, 1840: 8, 1848: 8, 1864: 8, 1880: 8, 1892: 8, 1896: 8, 1912: 8, 1960: 8, 1992: 8, 2008: 3, 2043: 5, 2045: 4\n    },\n  ],\n}\n\nDBC = {\n  CAR.AP2_MODELS: dbc_dict(None, 'tesla_radar', chassis_dbc='tesla_can'),\n  CAR.AP1_MODELS: dbc_dict(None, 'tesla_radar', chassis_dbc='tesla_can'),\n}\n\nclass CANBUS:\n  chassis = 0\n  autopilot = 2\n  radar = 1\n\nGEAR_MAP = {\n  \"DI_GEAR_INVALID\": car.CarState.GearShifter.unknown,\n  \"DI_GEAR_P\": car.CarState.GearShifter.park,\n  \"DI_GEAR_R\": car.CarState.GearShifter.reverse,\n  \"DI_GEAR_N\": car.CarState.GearShifter.neutral,\n  \"DI_GEAR_D\": car.CarState.GearShifter.drive,\n  \"DI_GEAR_SNA\": car.CarState.GearShifter.unknown,\n}\n\nDOORS = [\"DOOR_STATE_FL\", \"DOOR_STATE_FR\", \"DOOR_STATE_RL\", \"DOOR_STATE_RR\", \"DOOR_STATE_FrontTrunk\", \"BOOT_STATE\"]\n\n# Make sure the message and addr is also in the CAN parser!\nBUTTONS = [\n  Button(car.CarState.ButtonEvent.Type.leftBlinker, \"STW_ACTN_RQ\", \"TurnIndLvr_Stat\", [1]),\n  Button(car.CarState.ButtonEvent.Type.rightBlinker, \"STW_ACTN_RQ\", \"TurnIndLvr_Stat\", [2]),\n  Button(car.CarState.ButtonEvent.Type.accelCruise, \"STW_ACTN_RQ\", \"SpdCtrlLvr_Stat\", [4, 16]),\n  Button(car.CarState.ButtonEvent.Type.decelCruise, \"STW_ACTN_RQ\", \"SpdCtrlLvr_Stat\", [8, 32]),\n  Button(car.CarState.ButtonEvent.Type.cancel, \"STW_ACTN_RQ\", \"SpdCtrlLvr_Stat\", [2]),\n  Button(car.CarState.ButtonEvent.Type.resumeCruise, \"STW_ACTN_RQ\", \"SpdCtrlLvr_Stat\", [1]),\n]\n\nclass CarControllerParams:\n  RATE_LIMIT_UP = AngleRateLimit(speed_points=[0., 5., 15.], max_angle_diff_points=[5., .8, .15])\n  RATE_LIMIT_DOWN = AngleRateLimit(speed_points=[0., 5., 15.], max_angle_diff_points=[5., 3.5, 0.4])\n\n"
  },
  {
    "path": "selfdrive/car/tests/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/tests/test_car_interfaces.py",
    "content": "#!/usr/bin/env python3\nimport unittest\nimport importlib\nfrom parameterized import parameterized\n\nfrom cereal import car\nfrom selfdrive.car.fingerprints import all_known_cars\nfrom selfdrive.car.car_helpers import interfaces\nfrom selfdrive.car.fingerprints import _FINGERPRINTS as FINGERPRINTS\n\nclass TestCarInterfaces(unittest.TestCase):\n\n  @parameterized.expand([(car,) for car in all_known_cars()])\n  def test_car_interfaces(self, car_name):\n    print(car_name)\n    if car_name in FINGERPRINTS:\n      fingerprint = FINGERPRINTS[car_name][0]\n    else:\n      fingerprint = {}\n\n    CarInterface, CarController, CarState = interfaces[car_name]\n    fingerprints = {\n      0: fingerprint,\n      1: fingerprint,\n      2: fingerprint,\n    }\n\n    car_fw = []\n\n    car_params = CarInterface.get_params(car_name, fingerprints, car_fw)\n    car_interface = CarInterface(car_params, CarController, CarState)\n    assert car_params\n    assert car_interface\n\n    self.assertGreater(car_params.mass, 1)\n    self.assertGreater(car_params.steerRateCost, 1e-3)\n\n    if car_params.steerControlType != car.CarParams.SteerControlType.angle:\n      tuning = car_params.lateralTuning.which()\n      if tuning == 'pid':\n        self.assertTrue(len(car_params.lateralTuning.pid.kpV))\n      elif tuning == 'lqr':\n        self.assertTrue(len(car_params.lateralTuning.lqr.a))\n      elif tuning == 'indi':\n        self.assertTrue(len(car_params.lateralTuning.indi.outerLoopGainV))\n\n    # Run car interface\n    CC = car.CarControl.new_message()\n    for _ in range(10):\n      car_interface.update(CC, [])\n      car_interface.apply(CC)\n      car_interface.apply(CC)\n\n    CC = car.CarControl.new_message()\n    CC.enabled = True\n    for _ in range(10):\n      car_interface.update(CC, [])\n      car_interface.apply(CC)\n      car_interface.apply(CC)\n\n    # Test radar interface\n    RadarInterface = importlib.import_module('selfdrive.car.%s.radar_interface' % car_params.carName).RadarInterface\n    radar_interface = RadarInterface(car_params)\n    assert radar_interface\n\n    # Run radar interface once\n    radar_interface.update([])\n    if not car_params.radarOffCan and hasattr(radar_interface, '_update') and hasattr(radar_interface, 'trigger_msg'):\n      radar_interface._update([radar_interface.trigger_msg])\n\nif __name__ == \"__main__\":\n  unittest.main()\n"
  },
  {
    "path": "selfdrive/car/toyota/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/toyota/carcontroller.py",
    "content": "from cereal import car\nfrom common.numpy_fast import clip, interp\nfrom selfdrive.car import apply_toyota_steer_torque_limits, create_gas_command, make_can_msg\nfrom selfdrive.car.toyota.toyotacan import create_steer_command, create_ui_command, \\\n                                           create_accel_command, create_acc_cancel_command, \\\n                                           create_fcw_command, create_lta_steer_command\nfrom selfdrive.car.toyota.values import CAR, STATIC_DSU_MSGS, NO_STOP_TIMER_CAR, TSS2_CAR, \\\n                                        MIN_ACC_SPEED, PEDAL_HYST_GAP, PEDAL_SCALE, CarControllerParams\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\n\ndef accel_hysteresis(accel, accel_steady, enabled):\n\n  # for small accel oscillations within ACCEL_HYST_GAP, don't change the accel command\n  if not enabled:\n    # send 0 when disabled, otherwise acc faults\n    accel_steady = 0.\n  elif accel > accel_steady + CarControllerParams.ACCEL_HYST_GAP:\n    accel_steady = accel - CarControllerParams.ACCEL_HYST_GAP\n  elif accel < accel_steady - CarControllerParams.ACCEL_HYST_GAP:\n    accel_steady = accel + CarControllerParams.ACCEL_HYST_GAP\n  accel = accel_steady\n\n  return accel, accel_steady\n\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.last_steer = 0\n    self.accel_steady = 0.\n    self.alert_active = False\n    self.last_standstill = False\n    self.standstill_req = False\n    self.steer_rate_limited = False\n    self.use_interceptor = False\n\n    self.packer = CANPacker(dbc_name)\n\n  def update(self, enabled, CS, frame, actuators, pcm_cancel_cmd, hud_alert,\n             left_line, right_line, lead, left_lane_depart, right_lane_depart, dragonconf):\n\n    # *** compute control surfaces ***\n\n    # gas and brake\n    interceptor_gas_cmd = 0.\n    pcm_accel_cmd = actuators.accel\n\n    if CS.CP.enableGasInterceptor:\n      # handle hysteresis when around the minimum acc speed\n      if CS.out.vEgo < MIN_ACC_SPEED:\n        self.use_interceptor = True\n      elif CS.out.vEgo > MIN_ACC_SPEED + PEDAL_HYST_GAP:\n        self.use_interceptor = False\n\n      if self.use_interceptor and enabled:\n        # only send negative accel when using interceptor. gas handles acceleration\n        # +0.18 m/s^2 offset to reduce ABS pump usage when OP is engaged\n        MAX_INTERCEPTOR_GAS = interp(CS.out.vEgo, [0.0, MIN_ACC_SPEED], [0.2, 0.5])\n        interceptor_gas_cmd = clip(actuators.accel / PEDAL_SCALE, 0., MAX_INTERCEPTOR_GAS)\n        pcm_accel_cmd = 0.18 - max(0, -actuators.accel)\n\n    pcm_accel_cmd, self.accel_steady = accel_hysteresis(pcm_accel_cmd, self.accel_steady, enabled)\n    pcm_accel_cmd = clip(pcm_accel_cmd, CarControllerParams.ACCEL_MIN, CarControllerParams.ACCEL_MAX)\n\n    # steer torque\n    new_steer = int(round(actuators.steer * CarControllerParams.STEER_MAX))\n    apply_steer = apply_toyota_steer_torque_limits(new_steer, self.last_steer, CS.out.steeringTorqueEps, CarControllerParams)\n    self.steer_rate_limited = new_steer != apply_steer\n\n    # Cut steering while we're in a known fault state (2s)\n    if not enabled or CS.steer_state in [9, 25] or abs(CS.out.steeringRateDeg) > 100 or (abs(CS.out.steeringAngleDeg) > 150 and CS.CP.carFingerprint in [CAR.RAV4H, CAR.PRIUS]):\n      apply_steer = 0\n      apply_steer_req = 0\n    else:\n      apply_steer_req = 1\n\n    if not enabled and CS.pcm_acc_status:\n      # send pcm acc cancel cmd if drive is disabled but pcm is still on, or if the system can't be activated\n      pcm_cancel_cmd = 1\n\n    # on entering standstill, send standstill request\n    if not dragonconf.dpToyotaSng and CS.out.standstill and not self.last_standstill and CS.CP.carFingerprint not in NO_STOP_TIMER_CAR:\n      self.standstill_req = True\n    if CS.pcm_acc_status != 8:\n      # pcm entered standstill or it's disabled\n      self.standstill_req = False\n\n    # dp\n    blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n    if not enabled:\n      self.blinker_end_frame = 0\n    if self.last_blinker_on and not blinker_on:\n      self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n    apply_steer = common_controller_ctrl(enabled,\n                                         dragonconf,\n                                         blinker_on or frame < self.blinker_end_frame,\n                                         apply_steer, CS.out.vEgo)\n    self.last_blinker_on = blinker_on\n\n    self.last_steer = apply_steer\n    self.last_accel = pcm_accel_cmd\n    self.last_standstill = CS.out.standstill\n\n    can_sends = []\n\n    #*** control msgs ***\n    #print(\"steer {0} {1} {2} {3}\".format(apply_steer, min_lim, max_lim, CS.steer_torque_motor)\n\n    # toyota can trace shows this message at 42Hz, with counter adding alternatively 1 and 2;\n    # sending it at 100Hz seem to allow a higher rate limit, as the rate limit seems imposed\n    # on consecutive messages\n    can_sends.append(create_steer_command(self.packer, apply_steer, apply_steer_req, frame))\n    if frame % 2 == 0 and CS.CP.carFingerprint in TSS2_CAR:\n      can_sends.append(create_lta_steer_command(self.packer, 0, 0, frame // 2))\n\n    # LTA mode. Set ret.steerControlType = car.CarParams.SteerControlType.angle and whitelist 0x191 in the panda\n    # if frame % 2 == 0:\n    #   can_sends.append(create_steer_command(self.packer, 0, 0, frame // 2))\n    #   can_sends.append(create_lta_steer_command(self.packer, actuators.steeringAngleDeg, apply_steer_req, frame // 2))\n\n    if dragonconf.dpAtl and dragonconf.dpAtlOpLong and not CS.out.cruiseActualEnabled:\n      pcm_accel_cmd = 0.\n      if CS.CP.enableGasInterceptor:\n        interceptor_gas_cmd = 0.\n\n    # we can spam can to cancel the system even if we are using lat only control\n    if (frame % 3 == 0 and CS.CP.openpilotLongitudinalControl) or pcm_cancel_cmd:\n      lead = lead or CS.out.vEgo < 12.    # at low speed we always assume the lead is present do ACC can be engaged\n\n      if dragonconf.dpAtl and not dragonconf.dpAtlOpLong:\n        pass\n      # Lexus IS uses a different cancellation message\n      elif pcm_cancel_cmd and CS.CP.carFingerprint == CAR.LEXUS_IS:\n        can_sends.append(create_acc_cancel_command(self.packer))\n      elif CS.CP.openpilotLongitudinalControl:\n        can_sends.append(create_accel_command(self.packer, pcm_accel_cmd, pcm_cancel_cmd, self.standstill_req, lead, CS.acc_type, CS.distance))\n      else:\n        can_sends.append(create_accel_command(self.packer, 0, pcm_cancel_cmd, False, lead, CS.acc_type, CS.distance))\n\n    if frame % 2 == 0 and CS.CP.enableGasInterceptor:\n      # send exactly zero if gas cmd is zero. Interceptor will send the max between read value and gas cmd.\n      # This prevents unexpected pedal range rescaling\n      can_sends.append(create_gas_command(self.packer, interceptor_gas_cmd, frame // 2))\n\n    # ui mesg is at 100Hz but we send asap if:\n    # - there is something to display\n    # - there is something to stop displaying\n    fcw_alert = hud_alert == VisualAlert.fcw\n    steer_alert = hud_alert in [VisualAlert.steerRequired, VisualAlert.ldw]\n\n    send_ui = False\n    if ((fcw_alert or steer_alert) and not self.alert_active) or \\\n       (not (fcw_alert or steer_alert) and self.alert_active):\n      send_ui = True\n      self.alert_active = not self.alert_active\n    elif pcm_cancel_cmd:\n      # forcing the pcm to disengage causes a bad fault sound so play a good sound instead\n      send_ui = True\n\n    # dp\n    if not dragonconf.dpToyotaLdw:\n      left_lane_depart = False\n      right_lane_depart = False\n\n    if (frame % 100 == 0 or send_ui):\n      can_sends.append(create_ui_command(self.packer, steer_alert, pcm_cancel_cmd, left_line, right_line, left_lane_depart, right_lane_depart))\n\n    if frame % 100 == 0 and CS.CP.enableDsu:\n      can_sends.append(create_fcw_command(self.packer, fcw_alert))\n\n    #*** static msgs ***\n\n    for (addr, cars, bus, fr_step, vl) in STATIC_DSU_MSGS:\n      if frame % fr_step == 0 and CS.CP.enableDsu and CS.CP.carFingerprint in cars:\n        can_sends.append(make_can_msg(addr, vl, bus))\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/toyota/carstate.py",
    "content": "import time\nfrom math import floor\nfrom cereal import car\nfrom common.numpy_fast import mean\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.car.interfaces import CarStateBase\nfrom opendbc.can.parser import CANParser\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.toyota.values import CAR, DBC, STEER_THRESHOLD, NO_STOP_TIMER_CAR, TSS2_CAR\nfrom common.params import Params, put_nonblocking\n\n# dp\nDP_ACCEL_ECO = 0\nDP_ACCEL_NORMAL = 1\nDP_ACCEL_SPORT = 2\n_TRAFFIC_SINGAL_MAP = {\n  1: \"kph\",\n  36: \"mph\",\n  65: \"No overtake\",\n  66: \"No overtake\"\n}\n\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC[CP.carFingerprint][\"pt\"])\n    self.shifter_values = can_define.dv[\"GEAR_PACKET\"][\"GEAR\"]\n\n    # On cars with cp.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_ANGLE\"]\n    # the signal is zeroed to where the steering angle is at start.\n    # Need to apply an offset as soon as the steering angle measurements are both received\n    self.needs_angle_offset = True\n    self.accurate_steer_angle_seen = False\n    self.angle_offset = 0.\n    self._init_traffic_signals()\n\n    # dp\n    self.read_distance_lines = 0\n    self.read_distance_lines_init = False\n    self.distance = 0\n\n    self.dp_toyota_zss = Params().get_bool('dp_toyota_zss')\n    self.dp_accel_profile = None\n    self.dp_accel_profile_prev = None\n    self.dp_accel_profile_init = False\n\n    self.low_speed_lockout = False\n    self.acc_type = 1\n    self.dp_toyota_fp_btn_link = Params().get_bool('dp_toyota_fp_btn_link')\n    self.dp_toyota_ap_btn_link = Params().get_bool('dp_toyota_ap_btn_link')\n\n  def update(self, cp, cp_cam):\n    ret = car.CarState.new_message()\n\n    ret.doorOpen = any([cp.vl[\"SEATS_DOORS\"][\"DOOR_OPEN_FL\"], cp.vl[\"SEATS_DOORS\"][\"DOOR_OPEN_FR\"],\n                        cp.vl[\"SEATS_DOORS\"][\"DOOR_OPEN_RL\"], cp.vl[\"SEATS_DOORS\"][\"DOOR_OPEN_RR\"]])\n    ret.seatbeltUnlatched = cp.vl[\"SEATS_DOORS\"][\"SEATBELT_DRIVER_UNLATCHED\"] != 0\n\n    ret.brakePressed = cp.vl[\"BRAKE_MODULE\"][\"BRAKE_PRESSED\"] != 0\n    ret.brakeLights = bool(cp.vl[\"ESP_CONTROL\"]['BRAKE_LIGHTS_ACC'] or cp.vl[\"BRAKE_MODULE\"][\"BRAKE_PRESSED\"] != 0)\n    if self.CP.enableGasInterceptor:\n      ret.gas = (cp.vl[\"GAS_SENSOR\"][\"INTERCEPTOR_GAS\"] + cp.vl[\"GAS_SENSOR\"][\"INTERCEPTOR_GAS2\"]) / 2.\n      ret.gasPressed = ret.gas > 15\n    else:\n      if self.CP.carFingerprint == CAR.LEXUS_ISH:\n        ret.gas = cp.vl[\"GAS_PEDAL_ALT\"]['GAS_PEDAL']\n      else:\n        ret.gas = cp.vl[\"GAS_PEDAL\"]['GAS_PEDAL']\n      ret.gasPressed = cp.vl[\"PCM_CRUISE\"][\"GAS_RELEASED\"] == 0\n\n    ret.wheelSpeeds.fl = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_FL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_FR\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_RL\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = cp.vl[\"WHEEL_SPEEDS\"][\"WHEEL_SPEED_RR\"] * CV.KPH_TO_MS\n    ret.vEgoRaw = mean([ret.wheelSpeeds.fl, ret.wheelSpeeds.fr, ret.wheelSpeeds.rl, ret.wheelSpeeds.rr])\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n\n    ret.standstill = ret.vEgoRaw < 0.001\n\n    # Some newer models have a more accurate angle measurement in the TORQUE_SENSOR message. Use if non-zero\n    if self.dp_toyota_zss or abs(cp.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_ANGLE\"]) > 1e-3:\n      self.accurate_steer_angle_seen = True\n\n    if self.accurate_steer_angle_seen:\n      if self.dp_toyota_zss:\n        ret.steeringAngleDeg = cp.vl[\"SECONDARY_STEER_ANGLE\"][\"ZORRO_STEER\"] - self.angle_offset\n      else:\n        ret.steeringAngleDeg = cp.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_ANGLE\"] - self.angle_offset\n      if self.needs_angle_offset:\n        angle_wheel = cp.vl[\"STEER_ANGLE_SENSOR\"][\"STEER_ANGLE\"] + cp.vl[\"STEER_ANGLE_SENSOR\"][\"STEER_FRACTION\"]\n        if abs(angle_wheel) > 1e-3:\n          self.needs_angle_offset = False\n          self.angle_offset = ret.steeringAngleDeg - angle_wheel\n    else:\n      ret.steeringAngleDeg = cp.vl[\"STEER_ANGLE_SENSOR\"][\"STEER_ANGLE\"] + cp.vl[\"STEER_ANGLE_SENSOR\"][\"STEER_FRACTION\"]\n\n    ret.steeringRateDeg = cp.vl[\"STEER_ANGLE_SENSOR\"][\"STEER_RATE\"]\n\n    can_gear = int(cp.vl[\"GEAR_PACKET\"][\"GEAR\"])\n    ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(can_gear, None))\n\n    #dp: Thank you Arne (acceleration)\n    if self.dp_toyota_ap_btn_link:\n      if self.CP.carFingerprint in [CAR.LEXUS_ESH_TSS2, CAR.RAV4H_TSS2, CAR.CHRH, CAR.PRIUS_TSS2, CAR.HIGHLANDERH_TSS2]:\n        sport_on = cp.vl[\"GEAR_PACKET2\"]['SPORT_ON']\n        econ_on = cp.vl[\"GEAR_PACKET2\"]['ECON_ON']\n      else:\n        try:\n          econ_on = cp.vl[\"GEAR_PACKET\"]['ECON_ON']\n        except KeyError:\n          econ_on = 0\n        if self.CP.carFingerprint == CAR.RAV4_TSS2:\n          sport_on = cp.vl[\"GEAR_PACKET\"]['SPORT_ON_2']\n        else:\n          try:\n            sport_on = cp.vl[\"GEAR_PACKET\"]['SPORT_ON']\n          except KeyError:\n            sport_on = 0\n      if sport_on == 0 and econ_on == 0:\n        self.dp_accel_profile = DP_ACCEL_NORMAL\n      elif sport_on == 1:\n        self.dp_accel_profile = DP_ACCEL_SPORT\n      elif econ_on == 1:\n        self.dp_accel_profile = DP_ACCEL_ECO\n\n      # if init is false, we sync profile with whatever mode we have on car\n      if not self.dp_accel_profile_init or self.dp_accel_profile != self.dp_accel_profile_prev:\n        put_nonblocking('dp_accel_profile', str(self.dp_accel_profile))\n        put_nonblocking('dp_last_modified',str(floor(time.time())))\n        self.dp_accel_profile_init = True\n      self.dp_accel_profile_prev = self.dp_accel_profile\n\n    #dp: Thank you Arne (distance button)\n    if self.dp_toyota_fp_btn_link:\n      if not self.read_distance_lines_init or self.read_distance_lines != cp.vl[\"PCM_CRUISE_SM\"]['DISTANCE_LINES']:\n        self.read_distance_lines_init = True\n        self.read_distance_lines = cp.vl[\"PCM_CRUISE_SM\"]['DISTANCE_LINES']\n        put_nonblocking('dp_following_profile', str(int(max(self.read_distance_lines - 1, 0))))\n        put_nonblocking('dp_last_modified',str(floor(time.time())))\n\n    ret.leftBlinker = cp.vl[\"STEERING_LEVERS\"][\"TURN_SIGNALS\"] == 1\n    ret.rightBlinker = cp.vl[\"STEERING_LEVERS\"][\"TURN_SIGNALS\"] == 2\n\n    ret.steeringTorque = cp.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_TORQUE_DRIVER\"]\n    ret.steeringTorqueEps = cp.vl[\"STEER_TORQUE_SENSOR\"][\"STEER_TORQUE_EPS\"]\n    #dp\n    ret.engineRPM = cp.vl[\"ENGINE_RPM\"]['RPM']\n\n    # we could use the override bit from dbc, but it's triggered at too high torque values\n    ret.steeringPressed = abs(ret.steeringTorque) > STEER_THRESHOLD\n    ret.steerWarning = cp.vl[\"EPS_STATUS\"][\"LKA_STATE\"] not in [1, 5]\n\n    if self.CP.carFingerprint in [CAR.LEXUS_IS, CAR.LEXUS_ISH]:\n      ret.cruiseState.available = cp.vl[\"DSU_CRUISE\"][\"MAIN_ON\"] != 0\n      ret.cruiseState.speed = cp.vl[\"DSU_CRUISE\"][\"SET_SPEED\"] * CV.KPH_TO_MS\n    else:\n      ret.cruiseState.available = cp.vl[\"PCM_CRUISE_2\"][\"MAIN_ON\"] != 0\n      ret.cruiseState.speed = cp.vl[\"PCM_CRUISE_2\"][\"SET_SPEED\"] * CV.KPH_TO_MS\n\n    if self.CP.carFingerprint in TSS2_CAR:\n      self.acc_type = cp_cam.vl[\"ACC_CONTROL\"][\"ACC_TYPE\"]\n\n    # some TSS2 cars have low speed lockout permanently set, so ignore on those cars\n    # these cars are identified by an ACC_TYPE value of 2.\n    # TODO: it may be possible to avoid the lockout and gain stop and go if you\n    # send your own ACC_CONTROL msg on startup with ACC_TYPE set to 1\n    if (self.CP.carFingerprint not in TSS2_CAR and self.CP.carFingerprint not in [CAR.LEXUS_IS, CAR.LEXUS_ISH]) or \\\n       (self.CP.carFingerprint in TSS2_CAR and self.acc_type == 1):\n      self.low_speed_lockout = cp.vl[\"PCM_CRUISE_2\"][\"LOW_SPEED_LOCKOUT\"] == 2\n\n    self.pcm_acc_status = cp.vl[\"PCM_CRUISE\"][\"CRUISE_STATE\"]\n    if self.CP.carFingerprint in NO_STOP_TIMER_CAR or self.CP.enableGasInterceptor:\n      # ignore standstill in hybrid vehicles, since pcm allows to restart without\n      # receiving any special command. Also if interceptor is detected\n      ret.cruiseState.standstill = False\n    else:\n      ret.cruiseState.standstill = self.pcm_acc_status == 7\n    ret.cruiseState.enabled = bool(cp.vl[\"PCM_CRUISE\"][\"CRUISE_ACTIVE\"])\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n    ret.cruiseState.nonAdaptive = cp.vl[\"PCM_CRUISE\"][\"CRUISE_STATE\"] in [1, 2, 3, 4, 5, 6]\n    ret.genericToggle = bool(cp.vl[\"LIGHT_STALK\"][\"AUTO_HIGH_BEAM\"])\n    ret.stockAeb = bool(cp_cam.vl[\"PRE_COLLISION\"][\"PRECOLLISION_ACTIVE\"] and cp_cam.vl[\"PRE_COLLISION\"][\"FORCE\"] < -1e-5)\n\n    ret.espDisabled = cp.vl[\"ESP_CONTROL\"][\"TC_DISABLED\"] != 0\n    # 2 is standby, 10 is active. TODO: check that everything else is really a faulty state\n    self.steer_state = cp.vl[\"EPS_STATUS\"][\"LKA_STATE\"]\n\n    if self.CP.enableBsm:\n      ret.leftBlindspot = (cp.vl[\"BSM\"][\"L_ADJACENT\"] == 1) or (cp.vl[\"BSM\"][\"L_APPROACHING\"] == 1)\n      ret.rightBlindspot = (cp.vl[\"BSM\"][\"R_ADJACENT\"] == 1) or (cp.vl[\"BSM\"][\"R_APPROACHING\"] == 1)\n\n    # dp\n    # distance button\n    self.distance = cp_cam.vl[\"ACC_CONTROL\"]['DISTANCE']\n    self._update_traffic_signals(cp_cam)\n    ret.cruiseState.speedLimit = self._calculate_speed_limit()\n\n    return ret\n\n  def _init_traffic_signals(self):\n    self._tsgn1 = None\n    self._spdval1 = None\n    self._splsgn1 = None\n    self._tsgn2 = None\n    self._splsgn2 = None\n    self._tsgn3 = None\n    self._splsgn3 = None\n    self._tsgn4 = None\n    self._splsgn4 = None\n\n  def _update_traffic_signals(self, cp_cam):\n    # Print out car signals for traffic signal detection\n    tsgn1 = cp_cam.vl[\"RSA1\"]['TSGN1']\n    spdval1 = cp_cam.vl[\"RSA1\"]['SPDVAL1']\n    splsgn1 = cp_cam.vl[\"RSA1\"]['SPLSGN1']\n    tsgn2 = cp_cam.vl[\"RSA1\"]['TSGN2']\n    splsgn2 = cp_cam.vl[\"RSA1\"]['SPLSGN2']\n    tsgn3 = cp_cam.vl[\"RSA2\"]['TSGN3']\n    splsgn3 = cp_cam.vl[\"RSA2\"]['SPLSGN3']\n    tsgn4 = cp_cam.vl[\"RSA2\"]['TSGN4']\n    splsgn4 = cp_cam.vl[\"RSA2\"]['SPLSGN4']\n\n    has_changed = tsgn1 != self._tsgn1 \\\n      or spdval1 != self._spdval1 \\\n      or splsgn1 != self._splsgn1 \\\n      or tsgn2 != self._tsgn2 \\\n      or splsgn2 != self._splsgn2 \\\n      or tsgn3 != self._tsgn3 \\\n      or splsgn3 != self._splsgn3 \\\n      or tsgn4 != self._tsgn4 \\\n      or splsgn4 != self._splsgn4\n\n    self._tsgn1 = tsgn1\n    self._spdval1 = spdval1\n    self._splsgn1 = splsgn1\n    self._tsgn2 = tsgn2\n    self._splsgn2 = splsgn2\n    self._tsgn3 = tsgn3\n    self._splsgn3 = splsgn3\n    self._tsgn4 = tsgn4\n    self._splsgn4 = splsgn4\n\n    if not has_changed:\n      return\n\n    print('---- TRAFFIC SIGNAL UPDATE -----')\n    if tsgn1 is not None and tsgn1 != 0:\n      print(f'TSGN1: {self._traffic_signal_description(tsgn1)}')\n    if spdval1 is not None and spdval1 != 0:\n      print(f'SPDVAL1: {spdval1}')\n    if splsgn1 is not None and splsgn1 != 0:\n      print(f'SPLSGN1: {splsgn1}')\n    if tsgn2 is not None and tsgn2 != 0:\n      print(f'TSGN2: {self._traffic_signal_description(tsgn2)}')\n    if splsgn2 is not None and splsgn2 != 0:\n      print(f'SPLSGN2: {splsgn2}')\n    if tsgn3 is not None and tsgn3 != 0:\n      print(f'TSGN3: {self._traffic_signal_description(tsgn3)}')\n    if splsgn3 is not None and splsgn3 != 0:\n      print(f'SPLSGN3: {splsgn3}')\n    if tsgn4 is not None and tsgn4 != 0:\n      print(f'TSGN4: {self._traffic_signal_description(tsgn4)}')\n    if splsgn4 is not None and splsgn4 != 0:\n      print(f'SPLSGN4: {splsgn4}')\n    print('------------------------')\n\n  def _traffic_signal_description(self, tsgn):\n    desc = _TRAFFIC_SINGAL_MAP.get(int(tsgn))\n    return f'{tsgn}: {desc}' if desc is not None else f'{tsgn}'\n\n  def _calculate_speed_limit(self):\n    if self._tsgn1 == 1:\n      return self._spdval1 * CV.KPH_TO_MS\n    if self._tsgn1 == 36:\n      return self._spdval1 * CV.MPH_TO_MS\n    return 0\n\n  @staticmethod\n  def get_can_parser(CP):\n\n    signals = [\n      # sig_name, sig_address, default\n      (\"STEER_ANGLE\", \"STEER_ANGLE_SENSOR\", 0),\n      (\"GEAR\", \"GEAR_PACKET\", 0),\n      (\"BRAKE_PRESSED\", \"BRAKE_MODULE\", 0),\n      (\"WHEEL_SPEED_FL\", \"WHEEL_SPEEDS\", 0),\n      (\"WHEEL_SPEED_FR\", \"WHEEL_SPEEDS\", 0),\n      (\"WHEEL_SPEED_RL\", \"WHEEL_SPEEDS\", 0),\n      (\"WHEEL_SPEED_RR\", \"WHEEL_SPEEDS\", 0),\n      (\"DOOR_OPEN_FL\", \"SEATS_DOORS\", 1),\n      (\"DOOR_OPEN_FR\", \"SEATS_DOORS\", 1),\n      (\"DOOR_OPEN_RL\", \"SEATS_DOORS\", 1),\n      (\"DOOR_OPEN_RR\", \"SEATS_DOORS\", 1),\n      (\"SEATBELT_DRIVER_UNLATCHED\", \"SEATS_DOORS\", 1),\n      (\"TC_DISABLED\", \"ESP_CONTROL\", 1),\n      (\"STEER_FRACTION\", \"STEER_ANGLE_SENSOR\", 0),\n      (\"STEER_RATE\", \"STEER_ANGLE_SENSOR\", 0),\n      (\"CRUISE_ACTIVE\", \"PCM_CRUISE\", 0),\n      (\"CRUISE_STATE\", \"PCM_CRUISE\", 0),\n      (\"GAS_RELEASED\", \"PCM_CRUISE\", 1),\n      (\"STEER_TORQUE_DRIVER\", \"STEER_TORQUE_SENSOR\", 0),\n      (\"STEER_TORQUE_EPS\", \"STEER_TORQUE_SENSOR\", 0),\n      (\"STEER_ANGLE\", \"STEER_TORQUE_SENSOR\", 0),\n      (\"TURN_SIGNALS\", \"STEERING_LEVERS\", 3),   # 3 is no blinkers\n      (\"LKA_STATE\", \"EPS_STATUS\", 0),\n      (\"AUTO_HIGH_BEAM\", \"LIGHT_STALK\", 0),\n      #dp\n      (\"SPORT_ON\", \"GEAR_PACKET\", 0),\n      (\"ECON_ON\", \"GEAR_PACKET\", 1),\n      (\"DISTANCE_LINES\", \"PCM_CRUISE_SM\", 0),\n      (\"RPM\", \"ENGINE_RPM\", 0),\n      (\"BRAKE_LIGHTS_ACC\", \"ESP_CONTROL\", 0),\n    ]\n\n    checks = [\n      (\"GEAR_PACKET\", 1),\n      (\"LIGHT_STALK\", 1),\n      (\"STEERING_LEVERS\", 0.15),\n      (\"SEATS_DOORS\", 3),\n      (\"ESP_CONTROL\", 3),\n      (\"EPS_STATUS\", 25),\n      (\"BRAKE_MODULE\", 40),\n      (\"WHEEL_SPEEDS\", 80),\n      (\"STEER_ANGLE_SENSOR\", 80),\n      (\"PCM_CRUISE\", 33),\n      (\"STEER_TORQUE_SENSOR\", 50),\n      #dp\n      (\"ENGINE_RPM\", 100),\n    ]\n\n    #dp acceleration\n    if CP.carFingerprint == CAR.RAV4_TSS2:\n      signals.append((\"SPORT_ON_2\", \"GEAR_PACKET\", 0))\n\n    if CP.carFingerprint in [CAR.LEXUS_ESH_TSS2, CAR.RAV4H_TSS2, CAR.CHRH, CAR.PRIUS_TSS2, CAR.HIGHLANDERH_TSS2]:\n      signals.append((\"SPORT_ON\", \"GEAR_PACKET2\", 0))\n      signals.append((\"ECON_ON\", \"GEAR_PACKET2\", 0))\n\n    if CP.carFingerprint in [CAR.LEXUS_IS, CAR.LEXUS_ISH]:\n      signals.append((\"MAIN_ON\", \"DSU_CRUISE\", 0))\n      signals.append((\"SET_SPEED\", \"DSU_CRUISE\", 0))\n      checks.append((\"DSU_CRUISE\", 5))\n    else:\n      signals.append((\"MAIN_ON\", \"PCM_CRUISE_2\", 0))\n      signals.append((\"SET_SPEED\", \"PCM_CRUISE_2\", 0))\n      signals.append((\"LOW_SPEED_LOCKOUT\", \"PCM_CRUISE_2\", 0))\n      checks.append((\"PCM_CRUISE_2\", 33))\n\n    if CP.carFingerprint == CAR.LEXUS_ISH:\n      signals.append((\"GAS_PEDAL\", \"GAS_PEDAL_ALT\", 0))\n      checks.append((\"GAS_PEDAL_ALT\", 33))\n    else:\n      signals.append((\"GAS_PEDAL\", \"GAS_PEDAL\", 0))\n      checks.append((\"GAS_PEDAL\", 33))\n\n    # add gas interceptor reading if we are using it\n    if CP.enableGasInterceptor:\n      signals.append((\"INTERCEPTOR_GAS\", \"GAS_SENSOR\", 0))\n      signals.append((\"INTERCEPTOR_GAS2\", \"GAS_SENSOR\", 0))\n      checks.append((\"GAS_SENSOR\", 50))\n\n    if CP.enableBsm:\n      signals += [\n        (\"L_ADJACENT\", \"BSM\", 0),\n        (\"L_APPROACHING\", \"BSM\", 0),\n        (\"R_ADJACENT\", \"BSM\", 0),\n        (\"R_APPROACHING\", \"BSM\", 0),\n      ]\n      checks += [\n        (\"BSM\", 1)\n      ]\n\n    if Params().get('dp_toyota_zss') == b'1':\n      signals += [(\"ZORRO_STEER\", \"SECONDARY_STEER_ANGLE\", 0)]\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 0)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n\n    signals = [\n      (\"FORCE\", \"PRE_COLLISION\", 0),\n      (\"PRECOLLISION_ACTIVE\", \"PRE_COLLISION\", 0),\n      #dp\n      (\"DISTANCE\", \"ACC_CONTROL\", 0),\n    ]\n\n    # Include traffic singal signals.\n    signals += [\n      (\"TSGN1\", \"RSA1\", 0),\n      (\"SPDVAL1\", \"RSA1\", 0),\n      (\"SPLSGN1\", \"RSA1\", 0),\n      (\"TSGN2\", \"RSA1\", 0),\n      (\"SPLSGN2\", \"RSA1\", 0),\n      (\"TSGN3\", \"RSA2\", 0),\n      (\"SPLSGN3\", \"RSA2\", 0),\n      (\"TSGN4\", \"RSA2\", 0),\n      (\"SPLSGN4\", \"RSA2\", 0),\n    ]\n\n    # use steering message to check if panda is connected to frc\n    checks = [\n      (\"STEERING_LKA\", 42),\n      (\"RSA1\", 0),\n      (\"RSA2\", 0),\n      (\"PRE_COLLISION\", 0), # TODO: figure out why freq is inconsistent\n    ]\n\n    if CP.carFingerprint in TSS2_CAR:\n      signals.append((\"ACC_TYPE\", \"ACC_CONTROL\", 0))\n      checks.append((\"ACC_CONTROL\", 33))\n\n    return CANParser(DBC[CP.carFingerprint][\"pt\"], signals, checks, 2)\n"
  },
  {
    "path": "selfdrive/car/toyota/interface.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.toyota.values import Ecu, CAR, TSS2_CAR, NO_DSU_CAR, MIN_ACC_SPEED, PEDAL_HYST_GAP, CarControllerParams\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\nfrom common.params import Params\n\nEventName = car.CarEvent.EventName\nGearShifter = car.CarState.GearShifter\n\nclass CarInterface(CarInterfaceBase):\n  def __init__(self, CP, CarController, CarState):\n    super().__init__(CP, CarController, CarState)\n\n    # dp\n    self.dp_cruise_speed = 0.\n\n  @staticmethod\n  def get_pid_accel_limits(CP, current_speed, cruise_speed):\n    return CarControllerParams.ACCEL_MIN, CarControllerParams.ACCEL_MAX\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=[]):  # pylint: disable=dangerous-default-value\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n\n    ret.carName = \"toyota\"\n    ret.safetyModel = car.CarParams.SafetyModel.toyota\n\n    ret.steerActuatorDelay = 0.12  # Default delay, Prius has larger delay\n    ret.steerLimitTimer = 0.4\n\n    ret.stoppingControl = False # Toyota starts braking more when it thinks you want to stop\n\n    if candidate not in [CAR.PRIUS, CAR.RAV4, CAR.RAV4H]:  # These cars use LQR/INDI\n      ret.lateralTuning.init('pid')\n      ret.lateralTuning.pid.kiBP, ret.lateralTuning.pid.kpBP = [[0.], [0.]]\n\n    if candidate == CAR.PRIUS:\n      stop_and_go = True\n      ret.safetyParam = 66  # see conversion factor for STEER_TORQUE_EPS in dbc file\n      ret.wheelbase = 2.70\n      ret.steerRatio = 15.74   # unknown end-to-end spec\n      tire_stiffness_factor = 0.6371   # hand-tune\n      ret.mass = 3045. * CV.LB_TO_KG + STD_CARGO_KG\n\n      ret.lateralTuning.init('indi')\n      ret.lateralTuning.indi.innerLoopGainBP = [0.]\n      ret.lateralTuning.indi.innerLoopGainV = [4.0]\n      ret.lateralTuning.indi.outerLoopGainBP = [0.]\n      ret.lateralTuning.indi.outerLoopGainV = [3.0]\n      ret.lateralTuning.indi.timeConstantBP = [0.]\n      ret.lateralTuning.indi.timeConstantV = [1.0]\n      ret.lateralTuning.indi.actuatorEffectivenessBP = [0.]\n      ret.lateralTuning.indi.actuatorEffectivenessV = [1.0]\n      ret.steerActuatorDelay = 0.3\n\n    elif candidate in [CAR.RAV4, CAR.RAV4H]:\n      stop_and_go = True if (candidate in CAR.RAV4H) else False\n      ret.safetyParam = 73\n      ret.wheelbase = 2.65\n      ret.steerRatio = 16.88   # 14.5 is spec end-to-end\n      tire_stiffness_factor = 0.5533\n      ret.mass = 3650. * CV.LB_TO_KG + STD_CARGO_KG  # mean between normal and hybrid\n      if ret.enableGasInterceptor:\n        ret.longitudinalTuning.kpV = [0.4, 0.36, 0.325]  # arne's tune.\n        ret.longitudinalTuning.kiV = [0.195, 0.10]\n      ret.lateralTuning.init('lqr')\n\n      ret.lateralTuning.lqr.scale = 1500.0\n      ret.lateralTuning.lqr.ki = 0.05\n\n      ret.lateralTuning.lqr.a = [0., 1., -0.22619643, 1.21822268]\n      ret.lateralTuning.lqr.b = [-1.92006585e-04, 3.95603032e-05]\n      ret.lateralTuning.lqr.c = [1., 0.]\n      ret.lateralTuning.lqr.k = [-110.73572306, 451.22718255]\n      ret.lateralTuning.lqr.l = [0.3233671, 0.3185757]\n      ret.lateralTuning.lqr.dcGain = 0.002237852961363602\n\n    elif candidate == CAR.COROLLA:\n      stop_and_go = False\n      ret.safetyParam = 88\n      ret.wheelbase = 2.70\n      ret.steerRatio = 18.27\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 2860. * CV.LB_TO_KG + STD_CARGO_KG  # mean between normal and hybrid\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.2], [0.05]]\n      ret.lateralTuning.pid.kf = 0.00003   # full torque for 20 deg at 80mph means 0.00007818594\n\n    elif candidate == CAR.LEXUS_RX:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.79\n      ret.steerRatio = 14.8\n      tire_stiffness_factor = 0.5533\n      ret.mass = 4387. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.05]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate == CAR.LEXUS_RXH:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.79\n      ret.steerRatio = 16.  # 14.8 is spec end-to-end\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 4481. * CV.LB_TO_KG + STD_CARGO_KG  # mean between min and max\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00006   # full torque for 10 deg at 80mph means 0.00007818594\n\n    elif candidate == CAR.LEXUS_RX_TSS2:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.79\n      ret.steerRatio = 14.8\n      tire_stiffness_factor = 0.5533  # not optimized yet\n      ret.mass = 4387. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate == CAR.LEXUS_RXH_TSS2:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.79\n      ret.steerRatio = 16.0  # 14.8 is spec end-to-end\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 4481.0 * CV.LB_TO_KG + STD_CARGO_KG  # mean between min and max\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.15]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate in [CAR.CHR, CAR.CHRH]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.63906\n      ret.steerRatio = 13.6\n      tire_stiffness_factor = 0.7933\n      ret.mass = 3300. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.723], [0.0428]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate in [CAR.CAMRY, CAR.CAMRYH, CAR.CAMRY_TSS2, CAR.CAMRYH_TSS2]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.82448\n      ret.steerRatio = 13.7\n      tire_stiffness_factor = 0.7933\n      ret.mass = 3400. * CV.LB_TO_KG + STD_CARGO_KG  # mean between normal and hybrid\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate in [CAR.HIGHLANDER_TSS2, CAR.HIGHLANDERH_TSS2]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.84988  # 112.2 in = 2.84988 m\n      ret.steerRatio = 16.0\n      tire_stiffness_factor = 0.8\n      ret.mass = 4700. * CV.LB_TO_KG + STD_CARGO_KG  # 4260 + 4-5 people\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.18], [0.015]]  # community tuning\n      ret.lateralTuning.pid.kf = 0.00012  # community tuning\n\n    elif candidate in [CAR.HIGHLANDER, CAR.HIGHLANDERH]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.78\n      ret.steerRatio = 16.0\n      tire_stiffness_factor = 0.8\n      ret.mass = 4607. * CV.LB_TO_KG + STD_CARGO_KG  # mean between normal and hybrid limited\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.18], [0.015]]  # community tuning\n      ret.lateralTuning.pid.kf = 0.00012  # community tuning\n\n    elif candidate in [CAR.AVALON, CAR.AVALON_2019, CAR.AVALONH_2019]:\n      stop_and_go = False\n      ret.safetyParam = 73\n      ret.wheelbase = 2.82\n      ret.steerRatio = 14.8  # Found at https://pressroom.toyota.com/releases/2016+avalon+product+specs.download\n      tire_stiffness_factor = 0.7983\n      ret.mass = 3505. * CV.LB_TO_KG + STD_CARGO_KG  # mean between normal and hybrid\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.17], [0.03]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate in [CAR.RAV4_TSS2, CAR.RAV4H_TSS2]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.68986\n      ret.steerRatio = 14.3\n      tire_stiffness_factor = 0.7933\n      ret.mass = 3585. * CV.LB_TO_KG + STD_CARGO_KG # Average between ICE and Hybrid\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n      # 2019+ Rav4 TSS2 uses two different steering racks and specific tuning seems to be necessary.\n      # See https://github.com/commaai/openpilot/pull/21429#issuecomment-873652891\n      for fw in car_fw:\n        if fw.ecu == \"eps\" and (fw.fwVersion.startswith(b'\\x02') or fw.fwVersion in [b'8965B42181\\x00\\x00\\x00\\x00\\x00\\x00']):\n          ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.15], [0.05]]\n          ret.lateralTuning.pid.kf = 0.00004\n          break\n\n    elif candidate in [CAR.COROLLA_TSS2, CAR.COROLLAH_TSS2]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.67  # Average between 2.70 for sedan and 2.64 for hatchback\n      ret.steerRatio = 13.9\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 3060. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate in [CAR.LEXUS_ES_TSS2, CAR.LEXUS_ESH_TSS2]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.8702\n      ret.steerRatio = 16.0  # not optimized\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 3704. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate == CAR.LEXUS_ESH:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.8190\n      ret.steerRatio = 16.06\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 3682. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate == CAR.SIENNA:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 3.03\n      ret.steerRatio = 15.5\n      tire_stiffness_factor = 0.444\n      ret.mass = 4590. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.19], [0.02]]\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate == CAR.LEXUS_IS:\n      stop_and_go = False\n      ret.safetyParam = 77\n      ret.wheelbase = 2.79908\n      ret.steerRatio = 13.3\n      tire_stiffness_factor = 0.444\n      ret.mass = 3736.8 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.05]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate == CAR.LEXUS_CTH:\n      stop_and_go = True\n      ret.safetyParam = 100\n      ret.wheelbase = 2.60\n      ret.steerRatio = 18.6\n      tire_stiffness_factor = 0.517\n      ret.mass = 3108 * CV.LB_TO_KG + STD_CARGO_KG  # mean between min and max\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.05]]\n      ret.lateralTuning.pid.kf = 0.00007\n\n    elif candidate in [CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.LEXUS_NX_TSS2]:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.66\n      ret.steerRatio = 14.7\n      tire_stiffness_factor = 0.444  # not optimized yet\n      ret.mass = 4070 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate == CAR.PRIUS_TSS2:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.70002  # from toyota online sepc.\n      ret.steerRatio = 13.4   # True steerRation from older prius\n      tire_stiffness_factor = 0.6371   # hand-tune\n      ret.mass = 3115. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.init('indi')\n      ret.lateralTuning.indi.innerLoopGainBP = [20, 24, 30]\n      ret.lateralTuning.indi.innerLoopGainV = [7.25, 7.5, 9]\n      ret.lateralTuning.indi.outerLoopGainBP = [20, 24, 30]\n      ret.lateralTuning.indi.outerLoopGainV = [6, 7.25, 6]\n      ret.lateralTuning.indi.timeConstantBP = [20, 24]\n      ret.lateralTuning.indi.timeConstantV = [2.0, 2.2]\n      ret.lateralTuning.indi.actuatorEffectivenessBP = [20, 24]\n      ret.lateralTuning.indi.actuatorEffectivenessV = [2, 3]\n      ret.steerActuatorDelay = 0.3\n      ret.steerRateCost = 1.25\n      ret.steerLimitTimer = 0.5\n\n    elif candidate == CAR.MIRAI:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 2.91\n      ret.steerRatio = 14.8\n      tire_stiffness_factor = 0.8\n      ret.mass = 4300. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.6], [0.1]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate == CAR.ALPHARD_TSS2:\n      stop_and_go = True\n      ret.safetyParam = 73\n      ret.wheelbase = 3.00\n      ret.steerRatio = 14.2\n      tire_stiffness_factor = 0.444\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.19], [0.02]]\n      ret.mass = 4305. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kf = 0.00007818594\n\n    elif candidate == CAR.LEXUS_ISH:\n      stop_and_go = True\n      ret.safetyParam = 130\n      ret.wheelbase = 2.79908\n      ret.steerRatio = 13.3\n      tire_stiffness_factor = 0.444\n      ret.mass = 3736.8 * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.3], [0.05]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    elif candidate in [CAR.PRIUS_ALPHA]:\n      stop_and_go = False\n      ret.safetyParam = 73\n      ret.wheelbase = 2.78\n      ret.steerRatio = 18\n      tire_stiffness_factor = 0.5533\n      ret.mass = 4387. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.pid.kpV, ret.lateralTuning.pid.kiV = [[0.2], [0.05]]\n      ret.lateralTuning.pid.kf = 0.00006\n\n    ret.steerRateCost = 1.\n    ret.centerToFront = ret.wheelbase * 0.44\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n\n    ret.enableBsm = 0x3F6 in fingerprint[0] and candidate in TSS2_CAR\n    # Detect smartDSU, which intercepts ACC_CMD from the DSU allowing openpilot to send it\n    smartDsu = 0x2FF in fingerprint[0]\n    # In TSS2 cars the camera does long control\n    found_ecus = [fw.ecu for fw in car_fw]\n    ret.enableDsu = (len(found_ecus) > 0) and (Ecu.dsu not in found_ecus) and (candidate not in NO_DSU_CAR)\n    ret.enableGasInterceptor = 0x201 in fingerprint[0]\n    # if the smartDSU is detected, openpilot can send ACC_CMD (and the smartDSU will block it from the DSU) or not (the DSU is \"connected\")\n    ret.openpilotLongitudinalControl = smartDsu or ret.enableDsu or candidate in TSS2_CAR\n    if Params().get_bool('dp_atl') and not Params().get_bool('dp_atl_op_long'):\n      ret.openpilotLongitudinalControl = False\n\n    # min speed to enable ACC. if car can do stop and go, then set enabling speed\n    # to a negative value, so it won't matter.\n    ret.minEnableSpeed = -1. if (stop_and_go or ret.enableGasInterceptor) else MIN_ACC_SPEED\n\n    # removing the DSU disables AEB and it's considered a community maintained feature\n    # intercepting the DSU is a community feature since it requires unofficial hardware\n    ret.communityFeature = ret.enableGasInterceptor or ret.enableDsu or smartDsu\n\n    if ret.enableGasInterceptor:\n      ret.longitudinalTuning.kpBP = [0., 5., MIN_ACC_SPEED, MIN_ACC_SPEED + PEDAL_HYST_GAP, 35.]\n      ret.longitudinalTuning.kpV = [1.2, 0.8, 0.765, 2.255, 1.5]\n      ret.longitudinalTuning.kiBP = [0., MIN_ACC_SPEED, MIN_ACC_SPEED + PEDAL_HYST_GAP, 35.]\n      ret.longitudinalTuning.kiV = [0.18, 0.165, 0.489, 0.36]\n    elif candidate in [CAR.COROLLA_TSS2, CAR.COROLLAH_TSS2, CAR.RAV4_TSS2, CAR.RAV4H_TSS2, CAR.LEXUS_NX_TSS2, CAR.PRIUS_TSS2]:\n      # Improved longitudinal tune\n      ret.longitudinalTuning.deadzoneBP = [0., 8.05]\n      ret.longitudinalTuning.deadzoneV = [.0, .14]\n      ret.longitudinalTuning.kpBP = [0., 5., 20.]\n      ret.longitudinalTuning.kpV = [1.3, 1.0, 0.7]\n      ret.longitudinalTuning.kiBP = [0., 5., 12., 20., 27.]\n      ret.longitudinalTuning.kiV = [.35, .23, .20, .17, .1]\n      ret.stoppingDecelRate = 0.3  # reach stopping target smoothly\n      ret.startingAccelRate = 6.0  # release brakes fast\n      ret.startAccel = 1.2  # Accelerate from 0 faster\n    else:\n      # Default longitudinal tune\n      ret.longitudinalTuning.deadzoneBP = [0., 9.]\n      ret.longitudinalTuning.deadzoneV = [0., .15]\n      ret.longitudinalTuning.kpBP = [0., 5., 35.]\n      ret.longitudinalTuning.kiBP = [0., 35.]\n      ret.longitudinalTuning.kpV = [3.6, 2.4, 1.5]\n      ret.longitudinalTuning.kiV = [0.54, 0.36]\n\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n    if candidate == CAR.PRIUS and Params().get('dp_toyota_zss') == b'1':\n      ret.mass = 3370. * CV.LB_TO_KG + STD_CARGO_KG\n      ret.lateralTuning.indi.timeConstantV = [0.1]\n      ret.lateralTuning.indi.timeConstantBP = [0.]\n      ret.steerRateCost = 0.5\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    # ******************* do can recv *******************\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n\n    # low speed re-write\n    if ret.cruiseState.enabled and dragonconf.dpToyotaCruiseOverride and ret.cruiseState.speed < dragonconf.dpToyotaCruiseOverrideAt * CV.KPH_TO_MS:\n      if dragonconf.dpToyotaCruiseOverrideVego:\n        if self.dp_cruise_speed == 0.:\n          ret.cruiseState.speed = self.dp_cruise_speed = max( dragonconf.dpToyotaCruiseOverrideSpeed * CV.KPH_TO_MS,ret.vEgo)\n        else:\n          ret.cruiseState.speed = self.dp_cruise_speed\n      else:\n        ret.cruiseState.speed = dragonconf.dpToyotaCruiseOverrideSpeed * CV.KPH_TO_MS\n    else:\n      self.dp_cruise_speed = 0.\n\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n    ret.steeringRateLimited = self.CC.steer_rate_limited if self.CC is not None else False\n\n    # gear except P, R\n    extra_gears = [GearShifter.neutral, GearShifter.eco, GearShifter.manumatic, GearShifter.drive, GearShifter.sport, GearShifter.low, GearShifter.brake, GearShifter.unknown]\n\n    # events\n    events = self.create_common_events(ret, extra_gears)\n\n    if self.CS.low_speed_lockout and self.CP.openpilotLongitudinalControl:\n      events.add(EventName.lowSpeedLockout)\n    if ret.vEgo < self.CP.minEnableSpeed and self.CP.openpilotLongitudinalControl:\n      events.add(EventName.belowEngageSpeed)\n      if c.actuators.accel > 0.3:\n        # some margin on the actuator to not false trigger cancellation while stopping\n        events.add(EventName.speedTooLow)\n      if ret.vEgo < 0.001:\n        # while in standstill, send a user alert\n        events.add(EventName.manualRestart)\n\n    ret.events = events.to_msg()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  # pass in a car.CarControl\n  # to be called @ 100hz\n  def apply(self, c):\n\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame,\n                               c.actuators, c.cruiseControl.cancel,\n                               c.hudControl.visualAlert, c.hudControl.leftLaneVisible,\n                               c.hudControl.rightLaneVisible, c.hudControl.leadVisible,\n                               c.hudControl.leftLaneDepart, c.hudControl.rightLaneDepart, self.dragonconf)\n\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/toyota/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom opendbc.can.parser import CANParser\nfrom cereal import car\nfrom selfdrive.car.toyota.values import NO_DSU_CAR, DBC, TSS2_CAR\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\ndef _create_radar_can_parser(car_fingerprint):\n  if car_fingerprint in TSS2_CAR:\n    RADAR_A_MSGS = list(range(0x180, 0x190))\n    RADAR_B_MSGS = list(range(0x190, 0x1a0))\n  else:\n    RADAR_A_MSGS = list(range(0x210, 0x220))\n    RADAR_B_MSGS = list(range(0x220, 0x230))\n\n  msg_a_n = len(RADAR_A_MSGS)\n  msg_b_n = len(RADAR_B_MSGS)\n\n  signals = list(zip(['LONG_DIST'] * msg_a_n + ['NEW_TRACK'] * msg_a_n + ['LAT_DIST'] * msg_a_n +\n                ['REL_SPEED'] * msg_a_n + ['VALID'] * msg_a_n + ['SCORE'] * msg_b_n,\n                RADAR_A_MSGS * 5 + RADAR_B_MSGS,\n                [255] * msg_a_n + [1] * msg_a_n + [0] * msg_a_n + [0] * msg_a_n + [0] * msg_a_n + [0] * msg_b_n))\n\n  checks = list(zip(RADAR_A_MSGS + RADAR_B_MSGS, [20]*(msg_a_n + msg_b_n)))\n\n  return CANParser(DBC[car_fingerprint]['radar'], signals, checks, 1)\n\nclass RadarInterface(RadarInterfaceBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    self.track_id = 0\n    self.radar_ts = CP.radarTimeStep\n\n    if CP.carFingerprint in TSS2_CAR:\n      self.RADAR_A_MSGS = list(range(0x180, 0x190))\n      self.RADAR_B_MSGS = list(range(0x190, 0x1a0))\n    else:\n      self.RADAR_A_MSGS = list(range(0x210, 0x220))\n      self.RADAR_B_MSGS = list(range(0x220, 0x230))\n\n    self.valid_cnt = {key: 0 for key in self.RADAR_A_MSGS}\n\n    self.rcp = _create_radar_can_parser(CP.carFingerprint)\n    self.trigger_msg = self.RADAR_B_MSGS[-1]\n    self.updated_messages = set()\n\n    # No radar dbc for cars without DSU which are not TSS 2.0\n    # TODO: make a adas dbc file for dsu-less models\n    self.no_radar = CP.carFingerprint in NO_DSU_CAR and CP.carFingerprint not in TSS2_CAR\n\n  def update(self, can_strings):\n    if self.no_radar:\n      return super().update(None)\n\n    vls = self.rcp.update_strings(can_strings)\n    self.updated_messages.update(vls)\n\n    if self.trigger_msg not in self.updated_messages:\n      return None\n\n    rr = self._update(self.updated_messages)\n    self.updated_messages.clear()\n\n    return rr\n\n  def _update(self, updated_messages):\n    ret = car.RadarData.new_message()\n    errors = []\n    if not self.rcp.can_valid:\n      errors.append(\"canError\")\n    ret.errors = errors\n\n    for ii in sorted(updated_messages):\n      if ii in self.RADAR_A_MSGS:\n        cpt = self.rcp.vl[ii]\n\n        if cpt['LONG_DIST'] >= 255 or cpt['NEW_TRACK']:\n          self.valid_cnt[ii] = 0    # reset counter\n        if cpt['VALID'] and cpt['LONG_DIST'] < 255:\n          self.valid_cnt[ii] += 1\n        else:\n          self.valid_cnt[ii] = max(self.valid_cnt[ii] - 1, 0)\n\n        score = self.rcp.vl[ii+16]['SCORE']\n        # print ii, self.valid_cnt[ii], score, cpt['VALID'], cpt['LONG_DIST'], cpt['LAT_DIST']\n\n        # radar point only valid if it's a valid measurement and score is above 50\n        if cpt['VALID'] or (score > 50 and cpt['LONG_DIST'] < 255 and self.valid_cnt[ii] > 0):\n          if ii not in self.pts or cpt['NEW_TRACK']:\n            self.pts[ii] = car.RadarData.RadarPoint.new_message()\n            self.pts[ii].trackId = self.track_id\n            self.track_id += 1\n          self.pts[ii].dRel = cpt['LONG_DIST']  # from front of car\n          self.pts[ii].yRel = -cpt['LAT_DIST']  # in car frame's y axis, left is positive\n          self.pts[ii].vRel = cpt['REL_SPEED']\n          self.pts[ii].aRel = float('nan')\n          self.pts[ii].yvRel = float('nan')\n          self.pts[ii].measured = bool(cpt['VALID'])\n        else:\n          if ii in self.pts:\n            del self.pts[ii]\n\n    ret.points = list(self.pts.values())\n    return ret\n"
  },
  {
    "path": "selfdrive/car/toyota/toyotacan.py",
    "content": "def create_steer_command(packer, steer, steer_req, raw_cnt):\n  \"\"\"Creates a CAN message for the Toyota Steer Command.\"\"\"\n\n  values = {\n    \"STEER_REQUEST\": steer_req,\n    \"STEER_TORQUE_CMD\": steer,\n    \"COUNTER\": raw_cnt,\n    \"SET_ME_1\": 1,\n  }\n  return packer.make_can_msg(\"STEERING_LKA\", 0, values)\n\n\ndef create_lta_steer_command(packer, steer, steer_req, raw_cnt):\n  \"\"\"Creates a CAN message for the Toyota LTA Steer Command.\"\"\"\n\n  values = {\n    \"COUNTER\": raw_cnt + 128,\n    \"SETME_X1\": 1,\n    \"SETME_X3\": 3,\n    \"PERCENTAGE\": 100,\n    \"SETME_X64\": 0x64,\n    \"ANGLE\": 0,  # Rate limit? Lower values seeem to work better, but needs more testing\n    \"STEER_ANGLE_CMD\": steer,\n    \"STEER_REQUEST\": steer_req,\n    \"STEER_REQUEST_2\": steer_req,\n    \"BIT\": 0,\n  }\n  return packer.make_can_msg(\"STEERING_LTA\", 0, values)\n\n\ndef create_accel_command(packer, accel, pcm_cancel, standstill_req, lead, acc_type, distance):\n  # TODO: find the exact canceling bit that does not create a chime\n  values = {\n    \"ACCEL_CMD\": accel,\n    \"ACC_TYPE\": acc_type,\n    \"DISTANCE\": distance,\n    \"MINI_CAR\": lead,\n    \"SET_ME_X3\": 3,\n    \"PERMIT_BRAKING\": 1,\n    \"RELEASE_STANDSTILL\": not standstill_req,\n    \"CANCEL_REQ\": pcm_cancel,\n  }\n  return packer.make_can_msg(\"ACC_CONTROL\", 0, values)\n\n\ndef create_acc_cancel_command(packer):\n  values = {\n    \"GAS_RELEASED\": 0,\n    \"CRUISE_ACTIVE\": 0,\n    \"STANDSTILL_ON\": 0,\n    \"ACCEL_NET\": 0,\n    \"CRUISE_STATE\": 0,\n    \"CANCEL_REQ\": 1,\n  }\n  return packer.make_can_msg(\"PCM_CRUISE\", 0, values)\n\n\ndef create_fcw_command(packer, fcw):\n  values = {\n    \"FCW\": fcw,\n    \"SET_ME_X20\": 0x20,\n    \"SET_ME_X10\": 0x10,\n    \"SET_ME_X80\": 0x80,\n  }\n  return packer.make_can_msg(\"ACC_HUD\", 0, values)\n\n\ndef create_ui_command(packer, steer, chime, left_line, right_line, left_lane_depart, right_lane_depart):\n  values = {\n    \"RIGHT_LINE\": 3 if right_lane_depart else 1 if right_line else 2,\n    \"LEFT_LINE\": 3 if left_lane_depart else 1 if left_line else 2,\n    \"BARRIERS\" : 3 if left_lane_depart else 2 if right_lane_depart else 0,\n    \"SET_ME_X0C\": 0x0c,\n    \"SET_ME_X2C\": 0x2c,\n    \"SET_ME_X38\": 0x38,\n    \"SET_ME_X02\": 0x02,\n    \"SET_ME_X01\": 1,\n    \"SET_ME_X01_2\": 1,\n    \"REPEATED_BEEPS\": 0,\n    \"TWO_BEEPS\": chime,\n    \"LDA_ALERT\": steer,\n  }\n  return packer.make_can_msg(\"LKAS_HUD\", 0, values)\n"
  },
  {
    "path": "selfdrive/car/toyota/values.py",
    "content": "# flake8: noqa\n\nfrom cereal import car\nfrom selfdrive.car import dbc_dict\nfrom selfdrive.config import Conversions as CV\n\nEcu = car.CarParams.Ecu\nMIN_ACC_SPEED = 19. * CV.MPH_TO_MS\n\nPEDAL_HYST_GAP = 3. * CV.MPH_TO_MS\nPEDAL_SCALE = 3.0\n\nclass CarControllerParams:\n  ACCEL_HYST_GAP = 0.06  # don't change accel command for small oscilalitons within this value\n  ACCEL_MAX = 1.5  # m/s2, lower than allowed 2.0 m/s2 for tuning reasons\n  ACCEL_MIN = -3.5  # m/s2\n\n  STEER_MAX = 1500\n  STEER_DELTA_UP = 10       # 1.5s time to peak torque\n  STEER_DELTA_DOWN = 25     # always lower than 45 otherwise the Rav4 faults (Prius seems ok with 50)\n  STEER_ERROR_MAX = 350     # max delta between torque cmd and torque motor\n\nclass CAR:\n  PRIUS = \"TOYOTA PRIUS 2017\"\n  PRIUS_TSS2 = \"TOYOTA PRIUS TSS2 2021\"\n  RAV4H = \"TOYOTA RAV4 HYBRID 2017\"\n  RAV4 = \"TOYOTA RAV4 2017\"\n  COROLLA = \"TOYOTA COROLLA 2017\"\n  LEXUS_RX = \"LEXUS RX 2016\"\n  LEXUS_RXH = \"LEXUS RX HYBRID 2017\"\n  LEXUS_RX_TSS2 = \"LEXUS RX 2020\"\n  LEXUS_RXH_TSS2 = \"LEXUS RX HYBRID 2020\"\n  CHR = \"TOYOTA C-HR 2018\"\n  CHRH = \"TOYOTA C-HR HYBRID 2018\"\n  CAMRY = \"TOYOTA CAMRY 2018\"\n  CAMRYH = \"TOYOTA CAMRY HYBRID 2018\"\n  CAMRY_TSS2 = \"TOYOTA CAMRY 2021\"  # TSS 2.5\n  CAMRYH_TSS2 = \"TOYOTA CAMRY HYBRID 2021\"\n  HIGHLANDER = \"TOYOTA HIGHLANDER 2017\"\n  HIGHLANDER_TSS2 = \"TOYOTA HIGHLANDER 2020\"\n  HIGHLANDERH = \"TOYOTA HIGHLANDER HYBRID 2018\"\n  HIGHLANDERH_TSS2 = \"TOYOTA HIGHLANDER HYBRID 2020\"\n  AVALON = \"TOYOTA AVALON 2016\"\n  AVALON_2019 = \"TOYOTA AVALON 2019\"\n  AVALONH_2019 = \"TOYOTA AVALON HYBRID 2019\"\n  RAV4_TSS2 = \"TOYOTA RAV4 2019\"\n  COROLLA_TSS2 = \"TOYOTA COROLLA TSS2 2019\"\n  # LSS2 Lexus UX Hybrid is same as a TSS2 Corolla Hybrid\n  COROLLAH_TSS2 = \"TOYOTA COROLLA HYBRID TSS2 2019\"\n  LEXUS_ES_TSS2 = \"LEXUS ES 2019\"\n  LEXUS_ESH_TSS2 = \"LEXUS ES HYBRID 2019\"\n  LEXUS_ESH = \"LEXUS ES HYBRID 2018\"\n  SIENNA = \"TOYOTA SIENNA 2018\"\n  LEXUS_IS = \"LEXUS IS 2018\"\n  LEXUS_CTH = \"LEXUS CT HYBRID 2018\"\n  RAV4H_TSS2 = \"TOYOTA RAV4 HYBRID 2019\"\n  LEXUS_NXH = \"LEXUS NX HYBRID 2018\"\n  LEXUS_NX = \"LEXUS NX 2018\"\n  LEXUS_NX_TSS2 = \"LEXUS NX 2020\"\n  MIRAI = \"TOYOTA MIRAI 2021\" # TSS 2.5\n  ALPHARD_TSS2 = \"TOYOTA ALPHARD 2020\"\n  LEXUS_ISH = \"LEXUS ISH 2017\"\n  PRIUS_ALPHA = \"TOYOTA PRIUS ALPHA 2017\"\n\n# (addr, cars, bus, 1/freq*100, vl)\nSTATIC_DSU_MSGS = [\n  (0x128, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.AVALON), 1,   3, b'\\xf4\\x01\\x90\\x83\\x00\\x37'),\n  (0x128, (CAR.HIGHLANDER, CAR.HIGHLANDERH, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH), 1,   3, b'\\x03\\x00\\x20\\x00\\x00\\x52'),\n  (0x141, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.HIGHLANDER, CAR.HIGHLANDERH, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 1,   2, b'\\x00\\x00\\x00\\x46'),\n  (0x160, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.HIGHLANDER, CAR.HIGHLANDERH, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 1,   7, b'\\x00\\x00\\x08\\x12\\x01\\x31\\x9c\\x51'),\n  (0x161, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.AVALON, CAR.LEXUS_RX), 1,   7, b'\\x00\\x1e\\x00\\x00\\x00\\x80\\x07'),\n  (0X161, (CAR.HIGHLANDERH, CAR.HIGHLANDER, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH), 1,  7, b'\\x00\\x1e\\x00\\xd4\\x00\\x00\\x5b'),\n  (0x283, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.HIGHLANDER, CAR.HIGHLANDERH, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 0,   3, b'\\x00\\x00\\x00\\x00\\x00\\x00\\x8c'),\n  (0x2E6, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH), 0,   3, b'\\xff\\xf8\\x00\\x08\\x7f\\xe0\\x00\\x4e'),\n  (0x2E7, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH), 0,   3, b'\\xa8\\x9c\\x31\\x9c\\x00\\x00\\x00\\x02'),\n  (0x33E, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH), 0,  20, b'\\x0f\\xff\\x26\\x40\\x00\\x1f\\x00'),\n  (0x344, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.HIGHLANDER, CAR.HIGHLANDERH, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 0,   5, b'\\x00\\x00\\x01\\x00\\x00\\x00\\x00\\x50'),\n  (0x365, (CAR.PRIUS, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.HIGHLANDERH), 0,  20, b'\\x00\\x00\\x00\\x80\\x03\\x00\\x08'),\n  (0x365, (CAR.RAV4, CAR.RAV4H, CAR.COROLLA, CAR.HIGHLANDER, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 0,  20, b'\\x00\\x00\\x00\\x80\\xfc\\x00\\x08'),\n  (0x366, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.HIGHLANDERH), 0,  20, b'\\x00\\x00\\x4d\\x82\\x40\\x02\\x00'),\n  (0x366, (CAR.RAV4, CAR.COROLLA, CAR.HIGHLANDER, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 0,  20, b'\\x00\\x72\\x07\\xff\\x09\\xfe\\x00'),\n  (0x470, (CAR.PRIUS, CAR.LEXUS_RXH), 1, 100, b'\\x00\\x00\\x02\\x7a'),\n  (0x470, (CAR.HIGHLANDER, CAR.HIGHLANDERH, CAR.RAV4H, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH), 1,  100, b'\\x00\\x00\\x01\\x79'),\n  (0x4CB, (CAR.PRIUS, CAR.RAV4H, CAR.LEXUS_RXH, CAR.LEXUS_NXH, CAR.LEXUS_NX, CAR.RAV4, CAR.COROLLA, CAR.HIGHLANDERH, CAR.HIGHLANDER, CAR.AVALON, CAR.SIENNA, CAR.LEXUS_CTH, CAR.LEXUS_ESH, CAR.LEXUS_RX), 0, 100, b'\\x0c\\x00\\x00\\x00\\x00\\x00\\x00\\x00'),\n]\n\n\nFINGERPRINTS = {\n  CAR.RAV4: [{\n    36: 8, 37: 8, 170: 8, 180: 8, 186: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 512: 6, 513: 6, 547: 8, 548: 8, 552: 4, 562: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 897: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 918: 7, 921: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 4, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1005: 2, 1008: 2, 1014: 8, 1017: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1227: 8, 1228: 8, 1235: 8, 1237: 8, 1263: 8, 1264: 8, 1279: 8, 1408: 8, 1409: 8, 1410: 8, 1552: 8, 1553: 8, 1554: 8, 1555: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1596: 8, 1597: 8, 1600: 8, 1656: 8, 1664: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8, 2015: 8, 2024: 8\n  }],\n  CAR.RAV4H: [{\n    36: 8, 37: 8, 170: 8, 180: 8, 186: 4, 296: 8, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 547: 8, 548: 8, 550: 8, 552: 4, 560: 7, 562: 4, 581: 5, 608: 8, 610: 5, 643: 7, 705: 8, 713: 8, 725: 2, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 897: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 918: 7, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 3, 955: 8, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1005: 2, 1008: 2, 1014: 8, 1017: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1184: 8, 1185: 8, 1186: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1212: 8, 1227: 8, 1228: 8, 1232: 8, 1235: 8, 1237: 8, 1263: 8, 1264: 8, 1279: 8, 1408: 8, 1409: 8, 1410: 8, 1552: 8, 1553: 8, 1554: 8, 1555: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1596: 8, 1597: 8, 1600: 8, 1656: 8, 1664: 8, 1728: 8, 1745: 8, 1779: 8, 1872: 8, 1880: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  # Chinese RAV4\n  {\n    36: 8, 37: 8, 170: 8, 180: 8, 186: 4, 355: 5, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 512: 6, 513: 6, 547: 8, 548: 8, 552: 4, 562: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 742: 8, 743: 8, 767: 4, 800: 8, 830: 7, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 897: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 921: 8, 922: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1008: 2, 1017: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1207: 8, 1227: 8, 1235: 8, 1263: 8, 1279: 8, 1552: 8, 1553: 8, 1554: 8, 1555: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1596: 8, 1597: 8, 1600: 8, 1664: 8, 1728: 8, 1745: 8, 1779: 8\n  }],\n  CAR.PRIUS: [{\n    35: 8, 36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 512: 6, 513: 6, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 614: 8, 643: 7, 658: 8, 713: 8, 740: 5, 742: 8, 743: 8, 767: 4, 800: 8, 810: 2, 814: 8, 824: 2, 829: 2, 830: 7, 835: 8, 836: 8, 845: 5, 863: 8, 869: 7, 870: 7, 871: 2, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 918: 8, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 974: 8, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1005: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1082: 8, 1083: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1175: 8, 1227: 8, 1228: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1777: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  #2019 LE\n  {\n    35: 8, 36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 614: 8, 643: 7, 658: 8, 713: 8, 740: 5, 742: 8, 743: 8, 767: 4, 800: 8, 810: 2, 814: 8, 829: 2, 830: 7, 835: 8, 836: 8, 863: 8, 865: 8, 869: 7, 870: 7, 871: 2, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 918: 8, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1082: 8, 1083: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1175: 8, 1227: 8, 1228: 8, 1235: 8, 1237: 8, 1279: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1595: 8, 1777: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  # 2020 Prius Prime LE\n  {\n    35: 8, 36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 740: 5, 742: 8, 743: 8, 764: 8, 767: 4, 800: 8, 810: 2, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 863: 8, 865: 8, 869: 7, 870: 7, 871: 2, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 974: 8, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1227: 8, 1235: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1595: 8, 1649: 8, 1777: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  #2020 Prius Prime Limited\n  {\n    35: 8, 36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 614: 8, 643: 7, 658: 8, 713: 8, 740: 5, 742: 8, 743: 8, 767: 4, 800: 8, 810: 2, 814: 8, 824: 2, 829: 2, 830: 7, 835: 8, 836: 8, 863: 8, 865: 8, 869: 7, 870: 7, 871: 2, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 918: 8, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 974: 8, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1082: 8, 1083: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1175: 8, 1227: 8, 1228: 8, 1235: 8, 1237: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1595: 8, 1649: 8, 1777: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8, 2015: 8, 2024: 8, 2026: 8, 2027: 8, 2029: 8, 2030: 8, 2031: 8\n  },\n  #2020 Central Europe Prime\n  {\n    35: 8, 36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 740: 5, 742: 8, 743: 8, 764: 8, 767: 4, 800: 8, 810: 2, 818: 8, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 845: 5, 863: 8, 865: 8, 869: 7, 870: 7, 871: 2, 889: 8, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 8, 974: 8, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1227: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1595: 8, 1777: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8\n  },\n  #2017 German Prius\n  {\n    35: 8, 36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 614: 8, 643: 7, 658: 8, 713: 8, 740: 5, 742: 8, 743: 8, 767: 4, 800: 8, 810: 2, 814: 8, 829: 2, 830: 7, 835: 8, 836: 8, 845: 5, 863: 8, 869: 7, 870: 7, 871: 2, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 918: 8, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1005: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1077: 8, 1082: 8, 1083: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1175: 8, 1227: 8, 1228: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1777: 8, 1779: 8, 1792: 8, 1767: 4, 1863: 8, 1904: 8, 1912: 8, 1984: 8, 1988: 8, 1990: 8, 1992: 8, 1996: 8, 1998: 8, 2002: 8, 2010: 8, 2015: 8, 2016: 8, 2018: 8, 2024: 8, 2026: 8, 2030: 8\n  }],\n  CAR.PRIUS_TSS2: [{\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 401: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 614: 8, 643: 7, 658: 8, 713: 8, 740: 5, 742: 8, 743: 8, 764: 8, 765: 8, 800: 8, 810: 2, 814: 8, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 863: 8, 865: 8, 869: 7, 870: 7, 871: 2, 877: 8, 881: 8, 882: 8, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1082: 8, 1083: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1172: 8, 1175: 8, 1228: 8, 1235: 8, 1237: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1593: 8, 1595: 8, 1649: 8, 1653: 8, 1654: 8, 1655: 8, 1775: 8, 1777: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  }],\n  #Corolla w/ added Pedal Support (512L and 513L)\n  CAR.COROLLA: [{\n    36: 8, 37: 8, 170: 8, 180: 8, 186: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 512: 6, 513: 6, 547: 8, 548: 8, 552: 4, 608: 8, 610: 5, 643: 7, 705: 8, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 897: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 2, 921: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 4, 956: 8, 979: 2, 992: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1017: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1196: 8, 1227: 8, 1235: 8, 1279: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1596: 8, 1597: 8, 1600: 8, 1664: 8, 1728: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8, 2016: 8, 2017: 8, 2018: 8, 2019: 8, 2020: 8, 2021: 8, 2022: 8, 2023: 8, 2024: 8\n  }],\n  CAR.CAMRY: [\n  #XLE and LE\n  {\n    36: 8, 37: 8, 119: 6, 170: 8, 180: 8, 186: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 550: 8, 552: 4, 562: 6, 608: 8, 610: 8, 643: 7, 658: 8, 705: 8, 728: 8, 740: 5, 761: 8, 764: 8, 767: 4, 800: 8, 810: 2, 812: 8, 814: 8, 818: 8, 822: 8, 824: 8, 830: 7, 835: 8, 836: 8, 869: 7, 870: 7, 871: 2, 888: 8, 889: 8, 891: 8, 898: 8, 900: 6, 902: 6, 905: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 976: 1, 983: 8, 984: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1011: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1059: 1, 1076: 8, 1077: 8, 1082: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1228: 8, 1235: 8, 1237: 8, 1263: 8, 1264: 8, 1279: 8, 1412: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1808: 8, 1816: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  #XSE and SE\n  # TODO: get proper fingerprint in stock mode\n  {\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 550: 8, 552: 4, 562: 6, 608: 8, 610: 8, 643: 7, 658: 8, 705: 8, 728: 8, 740: 5, 761: 8, 764: 8, 767: 4, 800: 8, 810: 2, 812: 8, 814: 8, 818: 8, 822: 8, 824: 8, 830: 7, 835: 8, 836: 8, 869: 7, 870: 7, 888: 8, 889: 8, 891: 8, 898: 8, 900: 6, 902: 6, 905: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 976: 1, 983: 8, 984: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1011: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1056: 8, 1059: 1, 1076: 8, 1077: 8, 1082: 8, 1114: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1228: 8, 1237: 8, 1263: 8, 1264: 8, 1279: 8, 1412: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1808: 8, 1816: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  {\n  # 2019 XSE\n    36: 8, 37: 8, 170: 8, 180: 8, 186: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 550: 8, 552: 4, 562: 6, 608: 8, 610: 8, 643: 7, 658: 8, 705: 8, 728: 8, 740: 5, 761: 8, 764: 8, 767: 4, 800: 8, 810: 2, 812: 8, 814: 8, 818: 8, 822: 8, 824: 8, 830: 7, 835: 8, 836: 8, 865: 8, 869: 7, 870: 7, 871: 2, 888: 8, 889: 8, 891: 8, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 942: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 976: 1, 983: 8, 984: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1011: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1059: 1, 1076: 8, 1077: 8, 1082: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1228: 8, 1235: 8, 1237: 8, 1263: 8, 1264: 8, 1279: 8, 1412: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1594: 8, 1595: 8, 1649: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1792: 8, 1767: 4, 1808: 8, 1816: 8, 1872: 8, 1880: 8, 1904: 8, 1912: 8, 1937: 8, 1945: 8, 1953: 8, 1961: 8, 1968: 8, 1976: 8, 1990: 8, 1998: 8, 2015: 8, 2016: 8, 2024: 8\n  }],\n  CAR.CAMRYH: [\n  #SE, LE and LE with Blindspot Monitor\n  {\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 728: 8, 740: 5, 761: 8, 764: 8, 767: 4, 800: 8, 810: 2, 812: 8, 818: 8, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 865: 8, 869: 7, 870: 7, 871: 2, 889: 8, 896: 8, 898: 8, 900: 6, 902: 6, 905: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 983: 8, 984: 8, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1011: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1594: 8, 1595: 8, 1649: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1808: 8, 1810: 8, 1816: 8, 1818: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  #SL\n  {\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 728: 8, 740: 5, 761: 8, 764: 8, 767: 4, 800: 8, 810: 2, 812: 8, 818: 8, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 869: 7, 870: 7, 871: 2, 888: 8, 889: 8, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1228: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  #XLE\n  {\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 658: 8, 713: 8, 728: 8, 740: 5, 761: 8, 764: 8, 767: 4, 800: 8, 810: 2, 812: 8, 814: 8, 818: 8, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 869: 7, 870: 7, 871: 2, 888: 8, 889: 8, 898: 8, 900: 6, 902: 6, 905: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 983: 8, 984: 8, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1011: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1082: 8, 1084: 8, 1085: 8, 1086: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1228: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  # 2018 Chinese Camry Hybrid\n  {\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 728: 8, 740: 5, 761: 8, 764: 8, 800: 8, 810: 2, 812: 8, 818: 8, 824: 8, 829: 2, 830: 7, 835: 8, 836: 8, 869: 7, 870: 7, 871: 2, 888: 8, 889: 8, 898: 8, 900: 6, 902: 6, 905: 8, 913: 8, 918: 8, 921: 8, 933: 8, 934: 8, 935: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 993: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1076: 8, 1077: 8, 1084: 8, 1085: 8, 1086: 8, 1112: 8, 1114: 8, 1132: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1235: 8, 1264: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1595: 8, 1745: 8, 1779: 8, 1786: 8, 1787: 8, 1788: 8, 1789: 8\n  }],\n  CAR.HIGHLANDER: [{\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 238: 4, 355: 5, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 545: 5, 550: 8, 552: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 921: 8, 922: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1008: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1182: 8, 1183: 8, 1189: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1206: 8, 1207: 8, 1212: 8, 1227: 8, 1235: 8, 1237: 8, 1279: 8, 1408: 8, 1409: 8, 1410: 8, 1552: 8, 1553: 8, 1554: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1599: 8, 1656: 8, 1666: 8, 1667: 8, 1728: 8, 1745: 8, 1779: 8, 1872: 8, 1880: 8, 1904: 8, 1912: 8, 1984: 8, 1988: 8, 1992: 8, 1996: 8, 1990: 8, 1998: 8\n  },\n  # 2019 Highlander XLE\n  {\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 238: 4, 355: 5, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 545: 5, 550: 8, 552: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 921: 8, 922: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 992: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1008: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1076: 8, 1077: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1182: 8, 1183: 8, 1189: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1206: 8, 1207: 8, 1212: 8, 1227: 8, 1235: 8, 1237: 8, 1279: 8, 1408: 8, 1409: 8, 1410: 8, 1552: 8, 1553: 8, 1554: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1599: 8, 1656: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  # 2017 Highlander Limited\n  {\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 238: 4, 355: 5, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 545: 5, 550: 8, 552: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 918: 7, 921: 8, 922: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1005: 2, 1008: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1182: 8, 1183: 8, 1189: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1206: 8, 1207: 8, 1212: 8, 1227: 8, 1235: 8, 1237: 8, 1264: 8, 1279: 8, 1408: 8, 1409: 8, 1410: 8, 1552: 8, 1553: 8, 1554: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1599: 8, 1656: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  # 2018 Highlander Limited Platinum\n  {\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 238: 4, 355: 5, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 545: 5, 550: 8, 552: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 918: 7, 921: 8, 922: 8, 933: 8, 944: 8, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1008: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1182: 8, 1183: 8, 1189: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1206: 8, 1207: 8, 1212: 8, 1227: 8, 1235: 8, 1237: 8, 1263: 8, 1279: 8, 1408: 8, 1409: 8, 1410: 8, 1552: 8, 1553: 8, 1554: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1585: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1599: 8, 1656: 8, 1728: 8, 1745: 8, 1779: 8, 1872: 8, 1880: 8, 1904: 8, 1912: 8, 1988: 8, 1990: 8, 1996: 8, 1998: 8, 2015: 8, 2016: 8, 2024: 8\n  }],\n  CAR.HIGHLANDERH: [{\n    36: 8, 37: 8, 170: 8, 180: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 581: 5, 608: 8, 610: 5, 643: 7, 713: 8, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 897: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 918: 7, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 3, 955: 8, 956: 8, 979: 2, 998: 5, 999: 7, 1000: 8, 1001: 8, 1005: 2, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1059: 1, 1112: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1184: 8, 1185: 8, 1186: 8, 1189: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1206: 8, 1212: 8, 1227: 8, 1232: 8, 1235: 8, 1237: 8, 1263: 8, 1264: 8, 1279: 8, 1552: 8, 1553: 8, 1554: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1599: 8, 1656: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  {\n  # 2019 Highlander Hybrid Limited Platinum\n    36: 8, 37: 8, 170: 8, 180: 8, 296: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 581: 5, 608: 8, 610: 5, 643: 7, 713: 8, 740: 5, 767: 4, 800: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 897: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 3, 918: 7, 921: 8, 933: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 3, 955: 8, 956: 8, 979: 2, 992: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1043: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1076: 8, 1077: 8, 1112: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1184: 8, 1185: 8, 1186: 8, 1189: 8, 1190: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1206: 8, 1212: 8, 1227: 8, 1232: 8, 1235: 8, 1237: 8, 1263: 8, 1279: 8, 1552: 8, 1553: 8, 1554: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1599: 8, 1656: 8, 1666: 8, 1667: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  }],\n  CAR.COROLLAH_TSS2: [\n  # 2019 Taiwan Altis Hybrid\n  {\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 401: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 728: 8, 740: 5, 742: 8, 743: 8, 761: 8, 765: 8, 767: 4, 800: 8, 810: 2, 829: 2, 830: 7, 835: 8, 836: 8, 865: 8, 869: 7, 870: 7, 871: 2, 877: 8, 881: 8, 885: 8, 896: 8, 898: 8, 918: 7, 921: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 987: 8, 993: 8, 1002: 8, 1014: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1082: 8, 1112: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1172: 8, 1235: 8, 1237: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1594: 8, 1595: 8, 1745: 8, 1775: 8, 1779: 8\n  },\n  # 2019 Chinese Levin Hybrid\n  {\n    36: 8, 37: 8, 166: 8, 170: 8, 180: 8, 295: 8, 296: 8, 401: 8, 426: 6, 452: 8, 466: 8, 467: 8, 550: 8, 552: 4, 560: 7, 562: 6, 581: 5, 608: 8, 610: 8, 643: 7, 713: 8, 728: 8, 740: 5, 742: 8, 743: 8, 761: 8, 765: 8, 767: 4, 800: 8, 810: 2, 812: 8, 829: 2, 830: 7, 835: 8, 836: 8, 865: 8, 869: 7, 870: 7, 871: 2, 877: 8, 881: 8, 885: 8, 896: 8, 898: 8, 921: 8, 944: 8, 945: 8, 950: 8, 951: 8, 953: 8, 955: 8, 956: 8, 971: 7, 975: 5, 993: 8, 1002: 8, 1017: 8, 1020: 8, 1041: 8, 1042: 8, 1044: 8, 1056: 8, 1057: 8, 1059: 1, 1071: 8, 1114: 8, 1161: 8, 1162: 8, 1163: 8, 1172: 8, 1235: 8, 1279: 8, 1541: 8, 1552: 8, 1553: 8, 1556: 8, 1557: 8, 1568: 8, 1570: 8, 1571: 8, 1572: 8, 1592: 8, 1594: 8, 1595: 8, 1600: 8, 1649: 8, 1745: 8, 1775: 8, 1779: 8\n  }\n  ],\n  CAR.SIENNA: [\n  {\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 545: 5, 548: 8, 550: 8, 552: 4, 562: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 764: 8, 767: 4, 800: 8, 824: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 888: 8, 896: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 1, 918: 7, 921: 8, 933: 8, 944: 6, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 992: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1008: 2, 1014: 8, 1017: 8, 1041: 8, 1042: 8, 1043: 8, 1056: 8, 1059: 1, 1076: 8, 1077: 8, 1114: 8, 1160: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1182: 8, 1183: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1200: 8, 1201: 8, 1202: 8, 1203: 8, 1212: 8, 1227: 8, 1228: 8, 1235: 8, 1237: 8, 1279: 8, 1552: 8, 1553: 8, 1555: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1656: 8, 1664: 8, 1666: 8, 1667: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  },\n  # XLE AWD 2018\n  {\n    36: 8, 37: 8, 114: 5, 119: 6, 120: 4, 170: 8, 180: 8, 186: 4, 238: 4, 426: 6, 452: 8, 464: 8, 466: 8, 467: 8, 544: 4, 545: 5, 548: 8, 550: 8, 552: 4, 562: 4, 608: 8, 610: 5, 643: 7, 705: 8, 725: 2, 740: 5, 764: 8, 767: 4, 800: 8, 824: 8, 835: 8, 836: 8, 849: 4, 869: 7, 870: 7, 871: 2, 896: 8, 900: 6, 902: 6, 905: 8, 911: 8, 916: 1, 921: 8, 933: 8, 944: 6, 945: 8, 951: 8, 955: 8, 956: 8, 979: 2, 992: 8, 998: 5, 999: 7, 1000: 8, 1001: 8, 1002: 8, 1008: 2, 1014: 8, 1017: 8, 1041: 8, 1042: 8, 1043: 8, 1056: 8, 1059: 1, 1076: 8, 1077: 8, 1114: 8, 1160: 8, 1161: 8, 1162: 8, 1163: 8, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1176: 8, 1177: 8, 1178: 8, 1179: 8, 1180: 8, 1181: 8, 1182: 8, 1183: 8, 1191: 8, 1192: 8, 1196: 8, 1197: 8, 1198: 8, 1199: 8, 1200: 8, 1201: 8, 1202: 8, 1203: 8, 1212: 8, 1227: 8, 1235: 8, 1237: 8, 1279: 8, 1552: 8, 1553: 8, 1555: 8, 1556: 8, 1557: 8, 1561: 8, 1562: 8, 1568: 8, 1569: 8, 1570: 8, 1571: 8, 1572: 8, 1584: 8, 1589: 8, 1592: 8, 1593: 8, 1595: 8, 1656: 8, 1664: 8, 1666: 8, 1667: 8, 1728: 8, 1745: 8, 1779: 8, 1904: 8, 1912: 8, 1990: 8, 1998: 8\n  }],\n  # dp - fake values, for generate car selection\n  CAR.LEXUS_ISH: [{ 65535: 1 }],\n  CAR.PRIUS_ALPHA: [{ 65535: 1 }],\n}\n\n\nFW_VERSIONS = {\n  CAR.AVALON: {\n    (Ecu.esp, 0x7b0, None): [\n      b'F152607060\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881510701300\\x00\\x00\\x00\\x00',\n      b'881510705100\\x00\\x00\\x00\\x00',\n      b'881510705200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B41051\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0230721100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0C01000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230721200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0C01000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702000\\x00\\x00\\x00\\x00',\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0701100\\x00\\x00\\x00\\x00',\n      b'8646F0703000\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.AVALON_2019: {\n    (Ecu.esp, 0x7b0, None): [\n      b'F152607140\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152607171\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152607110\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152607180\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881510703200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B41080\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B07010\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B41090\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630735100\\x00\\x00\\x00\\x00',\n      b'\\x01896630725300\\x00\\x00\\x00\\x00',\n      b'\\x01896630738000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0702100\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.AVALONH_2019: {\n    (Ecu.esp, 0x7b0, None): [\n      b'F152641040\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152641061\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152641050\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881510704200\\x00\\x00\\x00\\x00',\n      b'881514107100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B07010\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B41090\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B41070\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x700, None): [\n      b'\\x02896630724000\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x02896630737000\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x02896630728000\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0702100\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.CAMRY: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x018966306L3100\\x00\\x00\\x00\\x00',\n      b'\\x018966306L4200\\x00\\x00\\x00\\x00',\n      b'\\x018966306L5200\\x00\\x00\\x00\\x00',\n      b'\\x018966306P8000\\x00\\x00\\x00\\x00',\n      b'\\x018966306Q3100\\x00\\x00\\x00\\x00',\n      b'\\x018966306Q4000\\x00\\x00\\x00\\x00',\n      b'\\x018966306Q4100\\x00\\x00\\x00\\x00',\n      b'\\x018966306Q4200\\x00\\x00\\x00\\x00',\n      b'\\x018966333Q9200\\x00\\x00\\x00\\x00',\n      b'\\x018966333P3100\\x00\\x00\\x00\\x00',\n      b'\\x018966333P3200\\x00\\x00\\x00\\x00',\n      b'\\x018966333P4200\\x00\\x00\\x00\\x00',\n      b'\\x018966333P4300\\x00\\x00\\x00\\x00',\n      b'\\x018966333P4400\\x00\\x00\\x00\\x00',\n      b'\\x018966333P4500\\x00\\x00\\x00\\x00',\n      b'\\x018966333P4700\\x00\\x00\\x00\\x00',\n      b'\\x018966333Q6000\\x00\\x00\\x00\\x00',\n      b'\\x018966333Q6200\\x00\\x00\\x00\\x00',\n      b'\\x018966333Q6300\\x00\\x00\\x00\\x00',\n      b'\\x018966333W6000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x02333P1100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'8821F0601200    ',\n      b'8821F0601300    ',\n      b'8821F0602000    ',\n      b'8821F0603300    ',\n      b'8821F0604100    ',\n      b'8821F0605200    ',\n      b'8821F0607200    ',\n      b'8821F0608000    ',\n      b'8821F0608200    ',\n      b'8821F0609100    ',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152606210\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152606230\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152606270\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152606290\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152606410\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633540\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633A10\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633A20\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B33540\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33542\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33580\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33581\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33621\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [  # Same as 0x791\n      b'8821F0601200    ',\n      b'8821F0601300    ',\n      b'8821F0602000    ',\n      b'8821F0603300    ',\n      b'8821F0604100    ',\n      b'8821F0605200    ',\n      b'8821F0607200    ',\n      b'8821F0608000    ',\n      b'8821F0608200    ',\n      b'8821F0609100    ',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0601200    ',\n      b'8646F0601300    ',\n      b'8646F0601400    ',\n      b'8646F0603400    ',\n      b'8646F0604100    ',\n      b'8646F0605000    ',\n      b'8646F0606000    ',\n      b'8646F0606100    ',\n      b'8646F0607100    ',\n    ],\n  },\n  CAR.CAMRYH: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x018966306Q6000\\x00\\x00\\x00\\x00',\n      b'\\x018966333N1100\\x00\\x00\\x00\\x00',\n      b'\\x018966333N4300\\x00\\x00\\x00\\x00',\n      b'\\x018966333X0000\\x00\\x00\\x00\\x00',\n      b'\\x018966333X4000\\x00\\x00\\x00\\x00',\n      b'\\x01896633T16000\\x00\\x00\\x00\\x00',\n      b'\\x028966306B2100\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306B2300\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306N8100\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306N8200\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306N8300\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306N8400\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306R5000\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306R5000\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x028966306R6000\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966306R6000\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x028966306S0000\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x028966306S0100\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x028966306S1100\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152633214\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633660\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633712\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633713\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633B51\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633B60\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'8821F0601200    ',\n      b'8821F0601300    ',\n      b'8821F0603400    ',\n      b'8821F0604000    ',\n      b'8821F0604200    ',\n      b'8821F0605200    ',\n      b'8821F0606200    ',\n      b'8821F0607200    ',\n      b'8821F0608000    ',\n      b'8821F0608200    ',\n      b'8821F0609000    ',\n      b'8821F0609100    ',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B33540\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33542\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33550\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33551\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33580\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33581\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33611\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33621\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [  # Same as 0x791\n      b'8821F0601200    ',\n      b'8821F0601300    ',\n      b'8821F0603400    ',\n      b'8821F0604000    ',\n      b'8821F0604200    ',\n      b'8821F0605200    ',\n      b'8821F0606200    ',\n      b'8821F0607200    ',\n      b'8821F0608000    ',\n      b'8821F0608200    ',\n      b'8821F0609000    ',\n      b'8821F0609100    ',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0601200    ',\n      b'8646F0601300    ',\n      b'8646F0601400    ',\n      b'8646F0603400    ',\n      b'8646F0603500    ',\n      b'8646F0604100    ',\n      b'8646F0605000    ',\n      b'8646F0606000    ',\n      b'8646F0606100    ',\n      b'8646F0607000    ',\n      b'8646F0607100    ',\n    ],\n  },\n  CAR.CAMRY_TSS2: {\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B33630\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F152606370\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152606390\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152606400\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x700, None): [\n      b'\\x018966306Q5000\\x00\\x00\\x00\\x00',\n      b'\\x018966306T3100\\x00\\x00\\x00\\x00',\n      b'\\x018966306T3200\\x00\\x00\\x00\\x00',\n      b'\\x018966306T4100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 15): [\n      b'\\x018821F6201200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 109): [\n      b'\\x028646F3305200\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',\n      b'\\x028646F3305300\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.CAMRYH_TSS2: {\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B33630\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152633D00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x700, None): [\n      b'\\x018966306Q6000\\x00\\x00\\x00\\x00',\n      b'\\x018966306Q7000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 15): [\n      b'\\x018821F6201200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 109): [\n      b'\\x028646F3305200\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',\n      b'\\x028646F3305300\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.CHR: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896631017100\\x00\\x00\\x00\\x00',\n      b'\\x01896631017200\\x00\\x00\\x00\\x00',\n      b'\\x0189663F413100\\x00\\x00\\x00\\x00',\n      b'\\x0189663F414100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'8821F0W01000    ',\n      b'8821F0W01100    ',\n      b'8821FF401600    ',\n      b'8821FF404000    ',\n      b'8821FF404100    ',\n      b'8821FF405100    ',\n      b'8821FF406000    ',\n      b'8821FF407100    ',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152610020\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610153\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610210\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F1526F4034\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F1526F4044\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F1526F4073\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F1526F4121\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F1526F4122\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B10011\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B10040\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B10070\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0331024000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203202\\x00\\x00\\x00\\x00',\n      b'\\x0331024000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203302\\x00\\x00\\x00\\x00',\n      b'\\x0331036000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203302\\x00\\x00\\x00\\x00',\n      b'\\x033F401100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203102\\x00\\x00\\x00\\x00',\n      b'\\x033F424000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203202\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F0W01000    ',\n      b'8821FF401600    ',\n      b'8821FF404000    ',\n      b'8821FF404100    ',\n      b'8821FF405100    ',\n      b'8821FF406000    ',\n      b'8821FF407100    ',\n      b'8821F0W01100    ',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646FF401800    ',\n      b'8646FF404000    ',\n      b'8646FF406000    ',\n      b'8646FF407000    ',\n    ],\n  },\n  CAR.CHRH: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x02896631013200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x0289663F405000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x0289663F418000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x0289663F423000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x0289663F431000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x0189663F438000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152610013\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610014\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610040\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610190\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610200\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152610230\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'8821F0W01000    ',\n      b'8821FF402300    ',\n      b'8821FF402400    ',\n      b'8821FF404000    ',\n      b'8821FF406000    ',\n      b'8821FF407100    ',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B10011\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B10020\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B10040\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B10050\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F0W01000    ',\n      b'8821FF402300    ',\n      b'8821FF402400    ',\n      b'8821FF404000    ',\n      b'8821FF406000    ',\n      b'8821FF407100    ',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646FF402100    ',\n      b'8646FF404000    ',\n      b'8646FF406000    ',\n      b'8646FF407000    ',\n    ],\n  },\n  CAR.COROLLA: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0230ZC2000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC2100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC2200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC2300\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC3000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC3100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC3200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230ZC3300\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0330ZC1200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0050212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203202\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881510201100\\x00\\x00\\x00\\x00',\n      b'881510201200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152602190\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152602191\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B02181\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B02191\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48150\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0201101\\x00\\x00\\x00\\x00',\n      b'8646F0201200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.COROLLA_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630ZG2000\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZG5000\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZG5100\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZG5200\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZG5300\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZP2000\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZQ5000\\x00\\x00\\x00\\x00',\n      b'\\x018966312L8000\\x00\\x00\\x00\\x00',\n      b'\\x018966312M0000\\x00\\x00\\x00\\x00',\n      b'\\x018966312M9000\\x00\\x00\\x00\\x00',\n      b'\\x018966312P9000\\x00\\x00\\x00\\x00',\n      b'\\x018966312P9100\\x00\\x00\\x00\\x00',\n      b'\\x018966312P9200\\x00\\x00\\x00\\x00',\n      b'\\x018966312Q2300\\x00\\x00\\x00\\x00',\n      b'\\x018966312R0000\\x00\\x00\\x00\\x00',\n      b'\\x018966312R0100\\x00\\x00\\x00\\x00',\n      b'\\x018966312R1000\\x00\\x00\\x00\\x00',\n      b'\\x018966312R1100\\x00\\x00\\x00\\x00',\n      b'\\x018966312R3100\\x00\\x00\\x00\\x00',\n      b'\\x018966312S5000\\x00\\x00\\x00\\x00',\n      b'\\x018966312S7000\\x00\\x00\\x00\\x00',\n      b'\\x018966312W3000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0230ZN4000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x03312M3000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203402\\x00\\x00\\x00\\x00',\n      b'\\x03312N6000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203202\\x00\\x00\\x00\\x00',\n      b'\\x03312N6000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203302\\x00\\x00\\x00\\x00',\n      b'\\x03312N6000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203402\\x00\\x00\\x00\\x00',\n      b'\\x03312N6100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203302\\x00\\x00\\x00\\x00',\n      b'\\x03312N6100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00895231203402\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'\\x018965B12350\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12470\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12490\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12500\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12520\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12530\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B1255000\\x00\\x00\\x00\\x00',\n      b'8965B12361\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F152602280\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152602560\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152602590\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152602650\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612641\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612651\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612B10\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612B51\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612B60\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612B61\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612B90\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152612C00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152602191\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301200\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301300\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F12010D0\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201100\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201200\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201300\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201400\\x00\\x00\\x00\\x008646G2601500\\x00\\x00\\x00\\x00',\n      b'\\x028646F1202000\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F1202100\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F1202200\\x00\\x00\\x00\\x008646G2601500\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.COROLLAH_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630ZJ1000\\x00\\x00\\x00\\x00',\n      b'\\x01896630ZU8000\\x00\\x00\\x00\\x00',\n      b'\\x01896637621000\\x00\\x00\\x00\\x00',\n      b'\\x01896637624000\\x00\\x00\\x00\\x00',\n      b'\\x01896637626000\\x00\\x00\\x00\\x00',\n      b'\\x01896637648000\\x00\\x00\\x00\\x00',\n      b'\\x02896630ZJ5000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896630ZN8000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896630ZQ3000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896630ZR2000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896630ZT8000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896630ZT9000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x028966312Q3000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x028966312Q4000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x038966312L7000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF1205001\\x00\\x00\\x00\\x00',\n      b'\\x038966312N1000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF1203001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B12361\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B12451\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B76012\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B76050\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12350\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12470\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12490\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12500\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12520\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x018965B12530\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152612590\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612691\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612692\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612700\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612710\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612790\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612800\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612820\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612840\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612A00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612A10\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642540\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152676293\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152676303\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152676304\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152612D00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301200\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301300\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F12010D0\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201100\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201300\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F1201400\\x00\\x00\\x00\\x008646G2601500\\x00\\x00\\x00\\x00',\n      b'\\x028646F1202000\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F1202100\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203400\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F76020C0\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F7603100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F7603200\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.HIGHLANDER: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630E09000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E43000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E43100\\x00\\x00\\x00\\x00',\n      b'\\x01896630E43200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E44200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E45000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E45100\\x00\\x00\\x00\\x00',\n      b'\\x01896630E45200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E46200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E74000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E75000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E76000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E77000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E83000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E84000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E85000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E86000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E88000\\x00\\x00\\x00\\x00',\n      b'\\x01896630EA0000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B48140\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48150\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48210\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [b'F15260E011\\x00\\x00\\x00\\x00\\x00\\x00'],\n    (Ecu.dsu, 0x791, None): [\n      b'881510E01100\\x00\\x00\\x00\\x00',\n      b'881510E01200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0E01200\\x00\\x00\\x00\\x00',\n      b'8646F0E01300\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.HIGHLANDERH: {\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B48160\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152648541\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648542\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0230E40000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230E40100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230EA2000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0230EA2100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0E01200\\x00\\x00\\x00\\x00',\n      b'8646F0E01300\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.HIGHLANDER_TSS2: {\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B48241\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48310\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F15260E051\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260E110\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630E62100\\x00\\x00\\x00\\x00',\n      b'\\x01896630E62200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E64100\\x00\\x00\\x00\\x00',\n      b'\\x01896630E64200\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB1000\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB1100\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB1200\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB2000\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB2100\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB2200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n      b'\\x018821F6201200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F0E02100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4803000\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.HIGHLANDERH_TSS2: {\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B48241\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48310\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F15264872300\\x00\\x00\\x00\\x00',\n      b'\\x01F15264872400\\x00\\x00\\x00\\x00',\n      b'\\x01F15264872500\\x00\\x00\\x00\\x00',\n      b'\\x01F152648C6300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630EA1000\\000\\000\\000\\000',\n      b'\\x01896630EA1000\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n      b'\\x02896630E66000\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n      b'\\x02896630EB3000\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n      b'\\x02896630EB3100\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n      b'\\x018821F6201200\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F0E02100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4803000\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_IS: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x018966353M7100\\x00\\x00\\x00\\x00',\n      b'\\x018966353Q2000\\x00\\x00\\x00\\x00',\n      b'\\x018966353Q2300\\x00\\x00\\x00\\x00',\n      b'\\x018966353R1100\\x00\\x00\\x00\\x00',\n      b'\\x018966353R7100\\x00\\x00\\x00\\x00',\n      b'\\x018966353R8100\\x00\\x00\\x00\\x00',\n      b'\\x018966353Q4000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0232480000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02353P7000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00530J5000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02353P9000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00553C1000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152653301\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152653310\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152653330\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881515306200\\x00\\x00\\x00\\x00',\n      b'881515306400\\x00\\x00\\x00\\x00',\n      b'881515306500\\x00\\x00\\x00\\x00',\n      b'881515307400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B53270\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B53271\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B53280\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B53281\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B53311\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F5301300\\x00\\x00\\x00\\x00',\n      b'8646F5301400\\x00\\x00\\x00\\x00',\n      b'8646F5301200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.PRIUS: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x02896634761000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634761100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634761200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634762000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634763000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634763100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634765000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634765100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634769100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634769200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634770000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634774000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634774100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634774200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634782000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x02896634784000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x028966347A0000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x028966347A5000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x028966347A8000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x028966347B0000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x03896634759100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701003\\x00\\x00\\x00\\x00',\n      b'\\x03896634759200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701003\\x00\\x00\\x00\\x00',\n      b'\\x03896634759200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701004\\x00\\x00\\x00\\x00',\n      b'\\x03896634759300\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701004\\x00\\x00\\x00\\x00',\n      b'\\x03896634760000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701002\\x00\\x00\\x00\\x00',\n      b'\\x03896634760000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701003\\x00\\x00\\x00\\x00',\n      b'\\x03896634760000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701004\\x00\\x00\\x00\\x00',\n      b'\\x03896634760100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701003\\x00\\x00\\x00\\x00',\n      b'\\x03896634760200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701003\\x00\\x00\\x00\\x00',\n      b'\\x03896634760200\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701004\\x00\\x00\\x00\\x00',\n      b'\\x03896634760300\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701004\\x00\\x00\\x00\\x00',\n      b'\\x03896634768000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4703001\\x00\\x00\\x00\\x00',\n      b'\\x03896634768000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4703002\\x00\\x00\\x00\\x00',\n      b'\\x03896634768100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4703002\\x00\\x00\\x00\\x00',\n      b'\\x03896634785000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4705001\\x00\\x00\\x00\\x00',\n      b'\\x03896634785000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4710001\\x00\\x00\\x00\\x00',\n      b'\\x03896634786000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4705001\\x00\\x00\\x00\\x00',\n      b'\\x03896634786000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4710001\\x00\\x00\\x00\\x00',\n      b'\\x03896634789000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4703002\\x00\\x00\\x00\\x00',\n      b'\\x038966347A3000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4701003\\x00\\x00\\x00\\x00',\n      b'\\x038966347A3000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4707001\\x00\\x00\\x00\\x00',\n      b'\\x038966347B6000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4710001\\x00\\x00\\x00\\x00',\n      b'\\x038966347B7000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4710001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B47021\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B47022\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B47023\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B47050\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B47060\\x00\\x00\\x00\\x00\\x00\\x00',  # This is the EPS with good angle sensor\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152647290\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647300\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647310\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647414\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647415\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647416\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647417\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647470\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647490\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647683\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647684\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647862\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647863\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647864\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647865\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881514702300\\x00\\x00\\x00\\x00',\n      b'881514703100\\x00\\x00\\x00\\x00',\n      b'881514704100\\x00\\x00\\x00\\x00',\n      b'881514706000\\x00\\x00\\x00\\x00',\n      b'881514706100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702000\\x00\\x00\\x00\\x00',\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F4701300\\x00\\x00\\x00\\x00',\n      b'8646F4702001\\x00\\x00\\x00\\x00',\n      b'8646F4702100\\x00\\x00\\x00\\x00',\n      b'8646F4702200\\x00\\x00\\x00\\x00',\n      b'8646F4705000\\x00\\x00\\x00\\x00',\n      b'8646F4705200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.RAV4: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x02342Q1000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q1100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q1200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q1300\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054212000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q2000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054213000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q2100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054213000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q2200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054213000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342Q4000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0054215000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B42063\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42073\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42082\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42083\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F15260R102\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F15260R103\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642493\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642492\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881514201200\\x00\\x00\\x00\\x00',\n      b'881514201300\\x00\\x00\\x00\\x00',\n      b'881514201400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702000\\x00\\x00\\x00\\x00',\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F4201200\\x00\\x00\\x00\\x00',\n      b'8646F4202001\\x00\\x00\\x00\\x00',\n      b'8646F4202100\\x00\\x00\\x00\\x00',\n      b'8646F4204000\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.RAV4H: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x02342N9000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342N9100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02342P0000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B42102\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42103\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42112\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42162\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42163\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152642090\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642110\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642120\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642400\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881514202200\\x00\\x00\\x00\\x00',\n      b'881514202300\\x00\\x00\\x00\\x00',\n      b'881514202400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702000\\x00\\x00\\x00\\x00',\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F4201100\\x00\\x00\\x00\\x00',\n      b'8646F4201200\\x00\\x00\\x00\\x00',\n      b'8646F4202001\\x00\\x00\\x00\\x00',\n      b'8646F4202100\\x00\\x00\\x00\\x00',\n      b'8646F4204000\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.RAV4_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630R58000\\x00\\x00\\x00\\x00',\n      b'\\x01896630R58100\\x00\\x00\\x00\\x00',\n      b'\\x018966342E2000\\x00\\x00\\x00\\x00',\n      b'\\x018966342M8000\\x00\\x00\\x00\\x00',\n      b'\\x018966342S9000\\x00\\x00\\x00\\x00',\n      b'\\x018966342T1000\\x00\\x00\\x00\\x00',\n      b'\\x018966342T6000\\x00\\x00\\x00\\x00',\n      b'\\x018966342T9000\\x00\\x00\\x00\\x00',\n      b'\\x018966342U4000\\x00\\x00\\x00\\x00',\n      b'\\x018966342U4100\\x00\\x00\\x00\\x00',\n      b'\\x018966342V3000\\x00\\x00\\x00\\x00',\n      b'\\x018966342V3100\\x00\\x00\\x00\\x00',\n      b'\\x018966342V3200\\x00\\x00\\x00\\x00',\n      b'\\x01896634A05000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A19000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A19100\\x00\\x00\\x00\\x00',\n      b'\\x01896634A20000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A20100\\x00\\x00\\x00\\x00',\n      b'\\x01896634A22000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A22100\\x00\\x00\\x00\\x00',\n      b'\\x01896634A30000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A44000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A45000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A46000\\x00\\x00\\x00\\x00',\n      b'\\x028966342M7000\\x00\\x00\\x00\\x00897CF1201001\\x00\\x00\\x00\\x00',\n      b'\\x028966342T0000\\x00\\x00\\x00\\x00897CF1201001\\x00\\x00\\x00\\x00',\n      b'\\x028966342V1000\\x00\\x00\\x00\\x00897CF1202001\\x00\\x00\\x00\\x00',\n      b'\\x028966342Y8000\\x00\\x00\\x00\\x00897CF1201001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A18000\\x00\\x00\\x00\\x00897CF1201001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A18100\\x00\\x00\\x00\\x00897CF1201001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A43000\\x00\\x00\\x00\\x00897CF4201001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A47000\\x00\\x00\\x00\\x00897CF4201001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F15260R210\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260R220\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260R290\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260R300\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642551\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642561\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642700\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642701\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642710\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642711\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642750\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152642751\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B42170\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42171\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42180\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42181\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x028965B0R01200\\x00\\x00\\x00\\x008965B0R02200\\x00\\x00\\x00\\x00',\n      b'\\x028965B0R01300\\x00\\x00\\x00\\x008965B0R02300\\x00\\x00\\x00\\x00',\n      b'\\x028965B0R01400\\x00\\x00\\x00\\x008965B0R02400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301200\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301300\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F4203200\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203300\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203400\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203500\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203700\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203800\\x00\\x00\\x00\\x008646G2601500\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.RAV4H_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896634A15000\\x00\\x00\\x00\\x00',\n      b'\\x018966342M5000\\x00\\x00\\x00\\x00',\n      b'\\x018966342W8000\\x00\\x00\\x00\\x00',\n      b'\\x018966342X5000\\x00\\x00\\x00\\x00',\n      b'\\x018966342X6000\\x00\\x00\\x00\\x00',\n      b'\\x01896634A25000\\x00\\x00\\x00\\x00',\n      b'\\x018966342W5000\\x00\\x00\\x00\\x00',\n      b'\\x028966342W4001\\x00\\x00\\x00\\x00897CF1203001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A13001\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A13101\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A14001\\x00\\x00\\x00\\x00897CF1203001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A23001\\x00\\x00\\x00\\x00897CF1203001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A14001\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n      b'\\x02896634A14101\\x00\\x00\\x00\\x00897CF4801001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152642291\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642290\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642330\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642331\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642531\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642532\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642520\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642521\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642540\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642541\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152642542\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B42170\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42171\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42180\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B42181\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x028965B0R01200\\x00\\x00\\x00\\x008965B0R02200\\x00\\x00\\x00\\x00',\n      b'\\x028965B0R01300\\x00\\x00\\x00\\x008965B0R02300\\x00\\x00\\x00\\x00',\n      b'\\x028965B0R01400\\x00\\x00\\x00\\x008965B0R02400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301200\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301300\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F4203200\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203300\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203400\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203500\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203700\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F4203800\\x00\\x00\\x00\\x008646G2601500\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_ES_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630EC9100\\x00\\x00\\x00\\x00',\n      b'\\x018966333T5000\\x00\\x00\\x00\\x00',\n      b'\\x018966333T5100\\x00\\x00\\x00\\x00',\n      b'\\x018966333X6000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F152606281\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152606340\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260E031\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B33252\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33590\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48271\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301200\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F33030D0\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F3303200\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F3304100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F4810200\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.SIENNA: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630832100\\x00\\x00\\x00\\x00',\n      b'\\x01896630832200\\x00\\x00\\x00\\x00',\n      b'\\x01896630838000\\x00\\x00\\x00\\x00',\n      b'\\x01896630838100\\x00\\x00\\x00\\x00',\n      b'\\x01896630842000\\x00\\x00\\x00\\x00',\n      b'\\x01896630843000\\x00\\x00\\x00\\x00',\n      b'\\x01896630851000\\x00\\x00\\x00\\x00',\n      b'\\x01896630851100\\x00\\x00\\x00\\x00',\n      b'\\x01896630852100\\x00\\x00\\x00\\x00',\n      b'\\x01896630859000\\x00\\x00\\x00\\x00',\n      b'\\x01896630860000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B45070\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B45080\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B45082\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152608130\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881510801100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702200\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F0801100\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_CTH: {\n    (Ecu.dsu, 0x791, None): [\n      b'881517601100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152676144\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0237635000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F7601100\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_ESH_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x028966333S8000\\x00\\x00\\x00\\x00897CF3302002\\x00\\x00\\x00\\x00',\n      b'\\x028966333T0100\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x028966333V4000\\x00\\x00\\x00\\x00897CF3305001\\x00\\x00\\x00\\x00',\n      b'\\x02896633T09000\\x00\\x00\\x00\\x00897CF3307001\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152633423\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633680\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152633681\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B33252\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33590\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B33690\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301200\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301300\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F33030D0\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F3303100\\x00\\x00\\x00\\x008646G26011A0\\x00\\x00\\x00\\x00',\n      b'\\x028646F3304100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F3304200\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_ESH: {\n      (Ecu.engine, 0x7e0, None): [\n        b'\\x02333M4200\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      ],\n      (Ecu.esp, 0x7b0, None): [\n        b'F152633171\\x00\\x00\\x00\\x00\\x00\\x00',\n      ],\n      (Ecu.dsu, 0x791, None): [\n        b'881513310400\\x00\\x00\\x00\\x00',\n      ],\n      (Ecu.eps, 0x7a1, None): [\n        b'8965B33512\\x00\\x00\\x00\\x00\\x00\\x00',\n      ],\n      (Ecu.fwdRadar, 0x750, 0xf): [\n        b'8821F4701100\\x00\\x00\\x00\\x00',\n        b'8821F4701300\\x00\\x00\\x00\\x00',\n      ],\n      (Ecu.fwdCamera, 0x750, 0x6d): [\n        b'8646F3302001\\x00\\x00\\x00\\x00',\n        b'8646F3302200\\x00\\x00\\x00\\x00',\n      ],\n  },\n  CAR.LEXUS_NX: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896637851000\\x00\\x00\\x00\\x00',\n      b'\\x01896637852000\\x00\\x00\\x00\\x00',\n      b'\\x01896637854000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152678130\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152678140\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881517803100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B78060\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B78080\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F7801100\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_NX_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x018966378B2100\\x00\\x00\\x00\\x00',\n      b'\\x018966378G3000\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F152678221\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B78120\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b\"\\x018821F3301400\\x00\\x00\\x00\\x00\",\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F78030A0\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n      b'\\x028646F7803100\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.PRIUS_ALPHA: {\n    (Ecu.esp, 0x7b0, None): [\n      b'F152647280\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0234781000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881514705100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F4703300\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_NXH: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x0237882000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0237841000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0237886000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0237880000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4701000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152678160\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152678170\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152678171\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881517804300\\x00\\x00\\x00\\x00',\n      b'881517804100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B78060\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B78080\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B78100\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4702300\\x00\\x00\\x00\\x00',\n      b'8821F4702100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F7801300\\x00\\x00\\x00\\x00',\n      b'8646F7801100\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_RX: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630E36200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E36300\\x00\\x00\\x00\\x00',\n      b'\\x01896630E37200\\x00\\x00\\x00\\x00',\n      b'\\x01896630E37300\\x00\\x00\\x00\\x00',\n      b'\\x01896630E41000\\x00\\x00\\x00\\x00',\n      b'\\x01896630E41100\\x00\\x00\\x00\\x00',\n      b'\\x01896630E41200\\x00\\x00\\x00\\x00',\n      b'\\x01896630EA3100\\x00\\x00\\x00\\x00',\n      b'\\x01896630EA4100\\x00\\x00\\x00\\x00',\n      b'\\x01896630EA4300\\x00\\x00\\x00\\x00',\n      b'\\x01896630EA6300\\x00\\x00\\x00\\x00',\n      b'\\x018966348R1300\\x00\\x00\\x00\\x00',\n      b'\\x018966348R8500\\x00\\x00\\x00\\x00',\n      b'\\x018966348W1300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152648472\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648473\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648492\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648493\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648474\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648630\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648494\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881514810300\\x00\\x00\\x00\\x00',\n      b'881514810500\\x00\\x00\\x00\\x00',\n      b'881514810700\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B0E011\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B0E012\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48102\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48112\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4701000\\x00\\x00\\x00\\x00',\n      b'8821F4701100\\x00\\x00\\x00\\x00',\n      b'8821F4701200\\x00\\x00\\x00\\x00',\n      b'8821F4701300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F4801100\\x00\\x00\\x00\\x00',\n      b'8646F4801200\\x00\\x00\\x00\\x00',\n      b'8646F4802001\\x00\\x00\\x00\\x00',\n      b'8646F4802100\\x00\\x00\\x00\\x00',\n      b'8646F4802200\\x00\\x00\\x00\\x00',\n      b'8646F4809000\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_RXH: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x02348J7000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348N0000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348Q4000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348Q4100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348T1100\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348T3000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348V6000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x02348Z3000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152648361\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648501\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648502\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648504\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648740\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648A30\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.dsu, 0x791, None): [\n      b'881514811300\\x00\\x00\\x00\\x00',\n      b'881514811500\\x00\\x00\\x00\\x00',\n      b'881514811700\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B0E011\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B0E012\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48111\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'8965B48112\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'8821F4701000\\x00\\x00\\x00\\x00',\n      b'8821F4701100\\x00\\x00\\x00\\x00',\n      b'8821F4701200\\x00\\x00\\x00\\x00',\n      b'8821F4701300\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'8646F4801200\\x00\\x00\\x00\\x00',\n      b'8646F4802001\\x00\\x00\\x00\\x00',\n      b'8646F4802100\\x00\\x00\\x00\\x00',\n      b'8646F4802200\\x00\\x00\\x00\\x00',\n      b'8646F4809000\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_RX_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x01896630EC9000\\x00\\x00\\x00\\x00',\n      b'\\x01896634D12000\\x00\\x00\\x00\\x00',\n      b'\\x01896630EB0000\\x00\\x00\\x00\\x00',\n      b'\\x01896630EA9000\\x00\\x00\\x00\\x00',\n      b'\\x01896630ED0000\\x00\\x00\\x00\\x00',\n      b'\\x018966348W9000\\x00\\x00\\x00\\x00',\n      b'\\x01896634D12100\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'\\x01F152648801\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260E031\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F15260E041\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x01F152648781\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B48271\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301100\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301300\\x00\\x00\\x00\\x00',\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F4810200\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F4810100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.LEXUS_RXH_TSS2: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\x02348X8000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0234D14000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'\\x0234D16000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A4802000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152648831\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648D00\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152648D60\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B48271\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F4810200\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F4810100\\x00\\x00\\x00\\x008646G2601200\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.PRIUS_TSS2: {\n    (Ecu.engine, 0x700, None): [\n      b'\\x028966347C8000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00',\n      b'\\x038966347C0000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4710101\\x00\\x00\\x00\\x00',\n      b'\\x038966347C1000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4710101\\x00\\x00\\x00\\x00',\n      b'\\x038966347C5000\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4707101\\x00\\x00\\x00\\x00',\n      b'\\x038966347C5100\\x00\\x00\\x00\\x008966A4703000\\x00\\x00\\x00\\x00897CF4707101\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.esp, 0x7b0, None): [\n      b'F152647500\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647510\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647520\\x00\\x00\\x00\\x00\\x00\\x00',\n      b'F152647521\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.eps, 0x7a1, None): [\n      b'8965B47070\\x00\\x00\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdRadar, 0x750, 0xf): [\n      b'\\x018821F3301400\\x00\\x00\\x00\\x00',\n    ],\n    (Ecu.fwdCamera, 0x750, 0x6d): [\n      b'\\x028646F4707000\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',\n      b'\\x028646F4710000\\x00\\x00\\x00\\x008646G2601500\\x00\\x00\\x00\\x00',\n    ],\n  },\n  CAR.MIRAI: {\n    (Ecu.esp, 0x7D1, None): [b'\\x01898A36203000\\x00\\x00\\x00\\x00',],\n    (Ecu.esp, 0x7B0, None): [b'\\x01F15266203200\\x00\\x00\\x00\\x00',], # a second ESP ECU\n    (Ecu.eps, 0x7A1, None): [b'\\x028965B6204100\\x00\\x00\\x00\\x008965B6203100\\x00\\x00\\x00\\x00',],\n    (Ecu.fwdRadar, 0x750, 0xf): [b'\\x018821F6201200\\x00\\x00\\x00\\x00',],\n    (Ecu.fwdCamera, 0x750, 0x6d): [b'\\x028646F6201400\\x00\\x00\\x00\\x008646G5301200\\x00\\x00\\x00\\x00',],\n  },\n  CAR.ALPHARD_TSS2: {\n    (Ecu.engine, 0x7e0, None): [b'\\x0235883000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00A0202000\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00',],\n    (Ecu.eps, 0x7a1, None): [b'8965B58040\\x00\\x00\\x00\\x00\\x00\\x00',],\n    (Ecu.fwdRadar, 0x750, 0xf): [b'\\x018821F3301400\\x00\\x00\\x00\\x00',],\n    (Ecu.fwdCamera, 0x750, 0x6d): [b'\\x028646F5803200\\x00\\x00\\x00\\x008646G2601400\\x00\\x00\\x00\\x00',],\n  },\n}\n\nSTEER_THRESHOLD = 100\n\nDBC = {\n  CAR.RAV4H: dbc_dict('toyota_rav4_hybrid_2017_pt_generated', 'toyota_adas'),\n  CAR.RAV4: dbc_dict('toyota_rav4_2017_pt_generated', 'toyota_adas'),\n  CAR.PRIUS: dbc_dict('toyota_prius_2017_pt_generated', 'toyota_adas'),\n  CAR.COROLLA: dbc_dict('toyota_corolla_2017_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_RX: dbc_dict('lexus_rx_350_2016_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_RXH: dbc_dict('lexus_rx_hybrid_2017_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_RX_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.LEXUS_RXH_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.CHR: dbc_dict('toyota_nodsu_pt_generated', 'toyota_adas'),\n  CAR.CHRH: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_adas'),\n  CAR.CAMRY: dbc_dict('toyota_nodsu_pt_generated', 'toyota_adas'),\n  CAR.CAMRYH: dbc_dict('toyota_camry_hybrid_2018_pt_generated', 'toyota_adas'),\n  CAR.CAMRY_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.CAMRYH_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.HIGHLANDER: dbc_dict('toyota_highlander_2017_pt_generated', 'toyota_adas'),\n  CAR.HIGHLANDER_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.HIGHLANDERH: dbc_dict('toyota_highlander_hybrid_2018_pt_generated', 'toyota_adas'),\n  CAR.HIGHLANDERH_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.AVALON: dbc_dict('toyota_avalon_2017_pt_generated', 'toyota_adas'),\n  CAR.AVALON_2019: dbc_dict('toyota_nodsu_pt_generated', 'toyota_adas'),\n  CAR.AVALONH_2019: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_adas'),\n  CAR.RAV4_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.COROLLA_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.COROLLAH_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.LEXUS_ES_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.LEXUS_ESH_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.LEXUS_ESH: dbc_dict('lexus_ct200h_2018_pt_generated', 'toyota_adas'),\n  CAR.SIENNA: dbc_dict('toyota_sienna_xle_2018_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_IS: dbc_dict('lexus_is_2018_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_CTH: dbc_dict('lexus_ct200h_2018_pt_generated', 'toyota_adas'),\n  CAR.RAV4H_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.LEXUS_NXH: dbc_dict('lexus_nx300h_2018_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_NX: dbc_dict('lexus_nx300_2018_pt_generated', 'toyota_adas'),\n  CAR.LEXUS_NX_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.PRIUS_TSS2: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.MIRAI: dbc_dict('toyota_nodsu_hybrid_pt_generated', 'toyota_tss2_adas'),\n  CAR.ALPHARD_TSS2: dbc_dict('toyota_nodsu_pt_generated', 'toyota_tss2_adas'),\n  CAR.LEXUS_ISH: dbc_dict('lexus_is300h_2017_pt_generated', 'toyota_adas'),\n  CAR.PRIUS_ALPHA: dbc_dict('toyota_prius_alpha_2017_pt_generated', 'toyota_adas'),\n}\n\n\n# Toyota/Lexus Safety Sense 2.0 and 2.5\nTSS2_CAR = set([CAR.RAV4_TSS2, CAR.COROLLA_TSS2, CAR.COROLLAH_TSS2, CAR.LEXUS_ES_TSS2, CAR.LEXUS_ESH_TSS2, CAR.RAV4H_TSS2,\n                CAR.LEXUS_RX_TSS2, CAR.LEXUS_RXH_TSS2, CAR.HIGHLANDER_TSS2, CAR.HIGHLANDERH_TSS2, CAR.PRIUS_TSS2, CAR.CAMRY_TSS2, CAR.CAMRYH_TSS2,\n                CAR.MIRAI, CAR.LEXUS_NX_TSS2, CAR.ALPHARD_TSS2])\n\nNO_DSU_CAR = TSS2_CAR | set([CAR.CHR, CAR.CHRH, CAR.CAMRY, CAR.CAMRYH])\n\n# no resume button press required\nNO_STOP_TIMER_CAR = TSS2_CAR | set([CAR.PRIUS_ALPHA, CAR.RAV4H, CAR.HIGHLANDERH, CAR.HIGHLANDER, CAR.SIENNA, CAR.LEXUS_ESH])\n"
  },
  {
    "path": "selfdrive/car/vin.py",
    "content": "#!/usr/bin/env python3\nimport traceback\n\nimport cereal.messaging as messaging\nfrom panda.python.uds import FUNCTIONAL_ADDRS\nfrom selfdrive.car.isotp_parallel_query import IsoTpParallelQuery\nfrom selfdrive.swaglog import cloudlog\n\nVIN_REQUEST = b'\\x09\\x02'\nVIN_RESPONSE = b'\\x49\\x02\\x01'\nVIN_UNKNOWN = \"0\" * 17\n\n\ndef get_vin(logcan, sendcan, bus, timeout=0.1, retry=5, debug=False):\n  for i in range(retry):\n    try:\n      query = IsoTpParallelQuery(sendcan, logcan, bus, FUNCTIONAL_ADDRS, [VIN_REQUEST], [VIN_RESPONSE], functional_addr=True, debug=debug)\n      for addr, vin in query.get_data(timeout).items():\n        return addr[0], vin.decode()\n      print(f\"vin query retry ({i+1}) ...\")\n    except Exception:\n      cloudlog.warning(f\"VIN query exception: {traceback.format_exc()}\")\n\n  return 0, VIN_UNKNOWN\n\n\nif __name__ == \"__main__\":\n  import time\n  sendcan = messaging.pub_sock('sendcan')\n  logcan = messaging.sub_sock('can')\n  time.sleep(1)\n  addr, vin = get_vin(logcan, sendcan, 1, debug=False)\n  print(hex(addr), vin)\n"
  },
  {
    "path": "selfdrive/car/volkswagen/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/car/volkswagen/carcontroller.py",
    "content": "from cereal import car\nfrom selfdrive.car import apply_std_steer_torque_limits\nfrom selfdrive.car.volkswagen import volkswagencan\nfrom selfdrive.car.volkswagen.values import DBC_FILES, CANBUS, MQB_LDW_MESSAGES, BUTTON_STATES, CarControllerParams as P\nfrom opendbc.can.packer import CANPacker\nfrom common.dp_common import common_controller_ctrl\n\nVisualAlert = car.CarControl.HUDControl.VisualAlert\n\nclass CarController():\n  def __init__(self, dbc_name, CP, VM):\n    # dp\n    self.last_blinker_on = False\n    self.blinker_end_frame = 0.\n\n    self.apply_steer_last = 0\n\n    self.packer_pt = CANPacker(DBC_FILES.mqb)\n\n    self.hcaSameTorqueCount = 0\n    self.hcaEnabledFrameCount = 0\n    self.graButtonStatesToSend = None\n    self.graMsgSentCount = 0\n    self.graMsgStartFramePrev = 0\n    self.graMsgBusCounterPrev = 0\n\n    self.steer_rate_limited = False\n\n  def update(self, enabled, CS, frame, ext_bus, actuators, visual_alert, left_lane_visible, right_lane_visible, left_lane_depart, right_lane_depart, dragonconf):\n    \"\"\" Controls thread \"\"\"\n\n    can_sends = []\n\n    # **** Steering Controls ************************************************ #\n\n    if frame % P.HCA_STEP == 0:\n      # Logic to avoid HCA state 4 \"refused\":\n      #   * Don't steer unless HCA is in state 3 \"ready\" or 5 \"active\"\n      #   * Don't steer at standstill\n      #   * Don't send > 3.00 Newton-meters torque\n      #   * Don't send the same torque for > 6 seconds\n      #   * Don't send uninterrupted steering for > 360 seconds\n      # One frame of HCA disabled is enough to reset the timer, without zeroing the\n      # torque value. Do that anytime we happen to have 0 torque, or failing that,\n      # when exceeding ~1/3 the 360 second timer.\n\n      if enabled and not (CS.out.standstill or CS.out.steerError or CS.out.steerWarning):\n        new_steer = int(round(actuators.steer * P.STEER_MAX))\n        apply_steer = apply_std_steer_torque_limits(new_steer, self.apply_steer_last, CS.out.steeringTorque, P)\n        self.steer_rate_limited = new_steer != apply_steer\n        if apply_steer == 0:\n          hcaEnabled = False\n          self.hcaEnabledFrameCount = 0\n        else:\n          self.hcaEnabledFrameCount += 1\n          if self.hcaEnabledFrameCount >= 118 * (100 / P.HCA_STEP):  # 118s\n            hcaEnabled = False\n            self.hcaEnabledFrameCount = 0\n          else:\n            hcaEnabled = True\n            if self.apply_steer_last == apply_steer:\n              self.hcaSameTorqueCount += 1\n              if self.hcaSameTorqueCount > 1.9 * (100 / P.HCA_STEP):  # 1.9s\n                apply_steer -= (1, -1)[apply_steer < 0]\n                self.hcaSameTorqueCount = 0\n            else:\n              self.hcaSameTorqueCount = 0\n      else:\n        hcaEnabled = False\n        apply_steer = 0\n\n      # dp\n      if CS.out.stopSteering:\n        apply_steer = 0\n      blinker_on = CS.out.leftBlinker or CS.out.rightBlinker\n      if not enabled:\n        self.blinker_end_frame = 0\n      if self.last_blinker_on and not blinker_on:\n        self.blinker_end_frame = frame + dragonconf.dpSignalOffDelay\n      apply_steer = common_controller_ctrl(enabled,\n                                           dragonconf,\n                                           blinker_on or frame < self.blinker_end_frame,\n                                           apply_steer, CS.out.vEgo)\n      self.last_blinker_on = blinker_on\n\n      self.apply_steer_last = apply_steer\n      idx = (frame / P.HCA_STEP) % 16\n      can_sends.append(volkswagencan.create_mqb_steering_control(self.packer_pt, CANBUS.pt, apply_steer,\n                                                                 idx, hcaEnabled))\n\n    # **** HUD Controls ***************************************************** #\n\n    if frame % P.LDW_STEP == 0:\n      if visual_alert in [VisualAlert.steerRequired, VisualAlert.ldw]:\n        hud_alert = MQB_LDW_MESSAGES[\"laneAssistTakeOverSilent\"]\n      else:\n        hud_alert = MQB_LDW_MESSAGES[\"none\"]\n\n      can_sends.append(volkswagencan.create_mqb_hud_control(self.packer_pt, CANBUS.pt, enabled,\n                                                            CS.out.steeringPressed, hud_alert, left_lane_visible,\n                                                            right_lane_visible, CS.ldw_lane_warning_left,\n                                                            CS.ldw_lane_warning_right, CS.ldw_side_dlc_tlc,\n                                                            CS.ldw_dlc, CS.ldw_tlc, CS.out.standstill,\n                                                            left_lane_depart, right_lane_depart))\n\n    # **** ACC Button Controls ********************************************** #\n\n    # FIXME: this entire section is in desperate need of refactoring\n\n    if frame > self.graMsgStartFramePrev + P.GRA_VBP_STEP:\n      if not enabled and CS.out.cruiseState.enabled:\n        # Cancel ACC if it's engaged with OP disengaged.\n        self.graButtonStatesToSend = BUTTON_STATES.copy()\n        self.graButtonStatesToSend[\"cancel\"] = True\n      elif enabled and CS.out.standstill:\n        # Blip the Resume button if we're engaged at standstill.\n        # FIXME: This is a naive implementation, improve with visiond or radar input.\n        # A subset of MQBs like to \"creep\" too aggressively with this implementation.\n        self.graButtonStatesToSend = BUTTON_STATES.copy()\n        self.graButtonStatesToSend[\"resumeCruise\"] = True\n\n    if CS.graMsgBusCounter != self.graMsgBusCounterPrev:\n      self.graMsgBusCounterPrev = CS.graMsgBusCounter\n      if self.graButtonStatesToSend is not None:\n        if self.graMsgSentCount == 0:\n          self.graMsgStartFramePrev = frame\n        idx = (CS.graMsgBusCounter + 1) % 16\n        can_sends.append(volkswagencan.create_mqb_acc_buttons_control(self.packer_pt, ext_bus, self.graButtonStatesToSend, CS, idx))\n        self.graMsgSentCount += 1\n        if self.graMsgSentCount >= P.GRA_VBP_COUNT:\n          self.graButtonStatesToSend = None\n          self.graMsgSentCount = 0\n\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/volkswagen/carstate.py",
    "content": "import numpy as np\nfrom cereal import car\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.car.interfaces import CarStateBase\nfrom opendbc.can.parser import CANParser\nfrom opendbc.can.can_define import CANDefine\nfrom selfdrive.car.volkswagen.values import DBC_FILES, CANBUS, NetworkLocation, TransmissionType, GearShifter, BUTTON_STATES, CarControllerParams\n\nclass CarState(CarStateBase):\n  def __init__(self, CP):\n    super().__init__(CP)\n    can_define = CANDefine(DBC_FILES.mqb)\n    if CP.transmissionType == TransmissionType.automatic:\n      self.shifter_values = can_define.dv[\"Getriebe_11\"][\"GE_Fahrstufe\"]\n    elif CP.transmissionType == TransmissionType.direct:\n      self.shifter_values = can_define.dv[\"EV_Gearshift\"][\"GearPosition\"]\n    self.hca_status_values = can_define.dv[\"LH_EPS_03\"][\"EPS_HCA_Status\"]\n    self.buttonStates = BUTTON_STATES.copy()\n\n  def update(self, pt_cp, cam_cp, ext_cp, trans_type):\n    ret = car.CarState.new_message()\n    # Update vehicle speed and acceleration from ABS wheel speeds.\n    ret.wheelSpeeds.fl = pt_cp.vl[\"ESP_19\"][\"ESP_VL_Radgeschw_02\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.fr = pt_cp.vl[\"ESP_19\"][\"ESP_VR_Radgeschw_02\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rl = pt_cp.vl[\"ESP_19\"][\"ESP_HL_Radgeschw_02\"] * CV.KPH_TO_MS\n    ret.wheelSpeeds.rr = pt_cp.vl[\"ESP_19\"][\"ESP_HR_Radgeschw_02\"] * CV.KPH_TO_MS\n\n    ret.vEgoRaw = float(np.mean([ret.wheelSpeeds.fl, ret.wheelSpeeds.fr, ret.wheelSpeeds.rl, ret.wheelSpeeds.rr]))\n    ret.vEgo, ret.aEgo = self.update_speed_kf(ret.vEgoRaw)\n\n    # dp addition - Fix stop and go acc self-resume +1\n    ret.standstill = bool(pt_cp.vl[\"ESP_21\"][\"ESP_Haltebestaetigung\"]) and ret.vEgoRaw < 0.01\n\n    # Update steering angle, rate, yaw rate, and driver input torque. VW send\n    # the sign/direction in a separate signal so they must be recombined.\n    ret.steeringAngleDeg = pt_cp.vl[\"LH_EPS_03\"][\"EPS_Berechneter_LW\"] * (1, -1)[int(pt_cp.vl[\"LH_EPS_03\"][\"EPS_VZ_BLW\"])]\n    ret.steeringRateDeg = pt_cp.vl[\"LWI_01\"][\"LWI_Lenkradw_Geschw\"] * (1, -1)[int(pt_cp.vl[\"LWI_01\"][\"LWI_VZ_Lenkradw_Geschw\"])]\n    ret.steeringTorque = pt_cp.vl[\"LH_EPS_03\"][\"EPS_Lenkmoment\"] * (1, -1)[int(pt_cp.vl[\"LH_EPS_03\"][\"EPS_VZ_Lenkmoment\"])]\n    ret.steeringPressed = abs(ret.steeringTorque) > CarControllerParams.STEER_DRIVER_ALLOWANCE\n    ret.yawRate = pt_cp.vl[\"ESP_02\"][\"ESP_Gierrate\"] * (1, -1)[int(pt_cp.vl[\"ESP_02\"][\"ESP_VZ_Gierrate\"])] * CV.DEG_TO_RAD\n\n    # Verify EPS readiness to accept steering commands\n    hca_status = self.hca_status_values.get(pt_cp.vl[\"LH_EPS_03\"][\"EPS_HCA_Status\"])\n    ret.steerError = hca_status in [\"DISABLED\", \"FAULT\"]\n    ret.steerWarning = hca_status in [\"INITIALIZING\", \"REJECTED\"]\n\n    # Update gas, brakes, and gearshift.\n    ret.gas = pt_cp.vl[\"Motor_20\"][\"MO_Fahrpedalrohwert_01\"] / 100.0\n    ret.gasPressed = ret.gas > 0\n    ret.brake = pt_cp.vl[\"ESP_05\"][\"ESP_Bremsdruck\"] / 250.0  # FIXME: this is pressure in Bar, not sure what OP expects\n    ret.brakePressed = bool(pt_cp.vl[\"ESP_05\"][\"ESP_Fahrer_bremst\"])\n    ret.brakeLights = bool(pt_cp.vl[\"ESP_05\"]['ESP_Status_Bremsdruck'])\n\n    # Update gear and/or clutch position data.\n    if trans_type == TransmissionType.automatic:\n      ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(pt_cp.vl[\"Getriebe_11\"][\"GE_Fahrstufe\"], None))\n    elif trans_type == TransmissionType.direct:\n      ret.gearShifter = self.parse_gear_shifter(self.shifter_values.get(pt_cp.vl[\"EV_Gearshift\"][\"GearPosition\"], None))\n    elif trans_type == TransmissionType.manual:\n      ret.clutchPressed = not pt_cp.vl[\"Motor_14\"][\"MO_Kuppl_schalter\"]\n      if bool(pt_cp.vl[\"Gateway_72\"][\"BCM1_Rueckfahrlicht_Schalter\"]):\n        ret.gearShifter = GearShifter.reverse\n      else:\n        ret.gearShifter = GearShifter.drive\n\n    # Update door and trunk/hatch lid open status.\n    ret.doorOpen = any([pt_cp.vl[\"Gateway_72\"][\"ZV_FT_offen\"],\n                        pt_cp.vl[\"Gateway_72\"][\"ZV_BT_offen\"],\n                        pt_cp.vl[\"Gateway_72\"][\"ZV_HFS_offen\"],\n                        pt_cp.vl[\"Gateway_72\"][\"ZV_HBFS_offen\"],\n                        pt_cp.vl[\"Gateway_72\"][\"ZV_HD_offen\"]])\n\n    # Update seatbelt fastened status.\n    ret.seatbeltUnlatched = pt_cp.vl[\"Airbag_02\"][\"AB_Gurtschloss_FA\"] != 3\n\n    # Update driver preference for metric. VW stores many different unit\n    # preferences, including separate units for for distance vs. speed.\n    # We use the speed preference for OP.\n    self.displayMetricUnits = not pt_cp.vl[\"Einheiten_01\"][\"KBI_MFA_v_Einheit_02\"]\n\n    # Consume blind-spot monitoring info/warning LED states, if available.\n    # Infostufe: BSM LED on, Warnung: BSM LED flashing\n    if self.CP.enableBsm:\n      ret.leftBlindspot = bool(ext_cp.vl[\"SWA_01\"][\"SWA_Infostufe_SWA_li\"]) or bool(ext_cp.vl[\"SWA_01\"][\"SWA_Warnung_SWA_li\"])\n      ret.rightBlindspot = bool(ext_cp.vl[\"SWA_01\"][\"SWA_Infostufe_SWA_re\"]) or bool(ext_cp.vl[\"SWA_01\"][\"SWA_Warnung_SWA_re\"])\n\n    # Consume factory LDW data relevant for factory SWA (Lane Change Assist)\n    # and capture it for forwarding to the blind spot radar controller\n    self.ldw_lane_warning_left = bool(cam_cp.vl[\"LDW_02\"][\"LDW_SW_Warnung_links\"])\n    self.ldw_lane_warning_right = bool(cam_cp.vl[\"LDW_02\"][\"LDW_SW_Warnung_rechts\"])\n    self.ldw_side_dlc_tlc = bool(cam_cp.vl[\"LDW_02\"][\"LDW_Seite_DLCTLC\"])\n    self.ldw_dlc = cam_cp.vl[\"LDW_02\"][\"LDW_DLC\"]\n    self.ldw_tlc = cam_cp.vl[\"LDW_02\"][\"LDW_TLC\"]\n\n    # Stock FCW is considered active if the release bit for brake-jerk warning\n    # is set. Stock AEB considered active if the partial braking or target\n    # braking release bits are set.\n    # Refer to VW Self Study Program 890253: Volkswagen Driver Assistance\n    # Systems, chapter on Front Assist with Braking: Golf Family for all MQB\n    ret.stockFcw = bool(ext_cp.vl[\"ACC_10\"][\"AWV2_Freigabe\"])\n    ret.stockAeb = bool(ext_cp.vl[\"ACC_10\"][\"ANB_Teilbremsung_Freigabe\"]) or bool(ext_cp.vl[\"ACC_10\"][\"ANB_Zielbremsung_Freigabe\"])\n\n    # Update ACC radar status.\n    accStatus = pt_cp.vl[\"TSK_06\"][\"TSK_Status\"]\n    if accStatus == 2:\n      # ACC okay and enabled, but not currently engaged\n      ret.cruiseState.available = True\n      ret.cruiseState.enabled = False\n    elif accStatus in [3, 4, 5]:\n      # ACC okay and enabled, currently engaged and regulating speed (3) or engaged with driver accelerating (4) or overrun (5)\n      ret.cruiseState.available = True\n      ret.cruiseState.enabled = True\n    else:\n      # ACC okay but disabled (1), or a radar visibility or other fault/disruption (6 or 7)\n      ret.cruiseState.available = False\n      ret.cruiseState.enabled = False\n    # dp\n    ret.cruiseActualEnabled = ret.cruiseState.enabled\n\n    # Update ACC setpoint. When the setpoint is zero or there's an error, the\n    # radar sends a set-speed of ~90.69 m/s / 203mph.\n    ret.cruiseState.speed = ext_cp.vl[\"ACC_02\"][\"ACC_Wunschgeschw\"] * CV.KPH_TO_MS\n    if ret.cruiseState.speed > 90:\n      ret.cruiseState.speed = 0\n\n    # Update control button states for turn signals and ACC controls.\n    self.buttonStates[\"accelCruise\"] = bool(pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Tip_Hoch\"])\n    self.buttonStates[\"decelCruise\"] = bool(pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Tip_Runter\"])\n    self.buttonStates[\"cancel\"] = bool(pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Abbrechen\"])\n    self.buttonStates[\"setCruise\"] = bool(pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Tip_Setzen\"])\n    self.buttonStates[\"resumeCruise\"] = bool(pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Tip_Wiederaufnahme\"])\n    self.buttonStates[\"gapAdjustCruise\"] = bool(pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Verstellung_Zeitluecke\"])\n    ret.leftBlinker = bool(pt_cp.vl[\"Blinkmodi_02\"][\"Comfort_Signal_Left\"])\n    ret.rightBlinker = bool(pt_cp.vl[\"Blinkmodi_02\"][\"Comfort_Signal_Right\"])\n\n    # Read ACC hardware button type configuration info that has to pass thru\n    # to the radar. Ends up being different for steering wheel buttons vs\n    # third stalk type controls.\n    self.graHauptschalter = pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Hauptschalter\"]\n    self.graTypHauptschalter = pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Typ_Hauptschalter\"]\n    self.graButtonTypeInfo = pt_cp.vl[\"GRA_ACC_01\"][\"GRA_ButtonTypeInfo\"]\n    self.graTipStufe2 = pt_cp.vl[\"GRA_ACC_01\"][\"GRA_Tip_Stufe_2\"]\n    # Pick up the GRA_ACC_01 CAN message counter so we can sync to it for\n    # later cruise-control button spamming.\n    self.graMsgBusCounter = pt_cp.vl[\"GRA_ACC_01\"][\"COUNTER\"]\n\n    # Additional safety checks performed in CarInterface.\n    self.parkingBrakeSet = bool(pt_cp.vl[\"Kombi_01\"][\"KBI_Handbremse\"])  # FIXME: need to include an EPB check as well\n    ret.espDisabled = pt_cp.vl[\"ESP_21\"][\"ESP_Tastung_passiv\"] != 0\n\n    return ret\n\n  @staticmethod\n  def get_can_parser(CP):\n    # this function generates lists for signal, messages and initial values\n    signals = [\n      # sig_name, sig_address, default\n      (\"EPS_Berechneter_LW\", \"LH_EPS_03\", 0),       # Absolute steering angle\n      (\"EPS_VZ_BLW\", \"LH_EPS_03\", 0),               # Steering angle sign\n      (\"LWI_Lenkradw_Geschw\", \"LWI_01\", 0),         # Absolute steering rate\n      (\"LWI_VZ_Lenkradw_Geschw\", \"LWI_01\", 0),      # Steering rate sign\n      (\"ESP_VL_Radgeschw_02\", \"ESP_19\", 0),         # ABS wheel speed, front left\n      (\"ESP_VR_Radgeschw_02\", \"ESP_19\", 0),         # ABS wheel speed, front right\n      (\"ESP_HL_Radgeschw_02\", \"ESP_19\", 0),         # ABS wheel speed, rear left\n      (\"ESP_HR_Radgeschw_02\", \"ESP_19\", 0),         # ABS wheel speed, rear right\n      (\"ESP_Gierrate\", \"ESP_02\", 0),                # Absolute yaw rate\n      (\"ESP_VZ_Gierrate\", \"ESP_02\", 0),             # Yaw rate sign\n      (\"ZV_FT_offen\", \"Gateway_72\", 0),             # Door open, driver\n      (\"ZV_BT_offen\", \"Gateway_72\", 0),             # Door open, passenger\n      (\"ZV_HFS_offen\", \"Gateway_72\", 0),            # Door open, rear left\n      (\"ZV_HBFS_offen\", \"Gateway_72\", 0),           # Door open, rear right\n      (\"ZV_HD_offen\", \"Gateway_72\", 0),             # Trunk or hatch open\n      (\"Comfort_Signal_Left\", \"Blinkmodi_02\", 0),   # Left turn signal including comfort blink interval\n      (\"Comfort_Signal_Right\", \"Blinkmodi_02\", 0),  # Right turn signal including comfort blink interval\n      (\"AB_Gurtschloss_FA\", \"Airbag_02\", 0),        # Seatbelt status, driver\n      (\"AB_Gurtschloss_BF\", \"Airbag_02\", 0),        # Seatbelt status, passenger\n      (\"ESP_Fahrer_bremst\", \"ESP_05\", 0),           # Brake pedal pressed\n      (\"ESP_Status_Bremsdruck\", \"ESP_05\", 0),       # Brakes applied\n      (\"ESP_Bremsdruck\", \"ESP_05\", 0),              # Brake pressure applied\n      (\"MO_Fahrpedalrohwert_01\", \"Motor_20\", 0),    # Accelerator pedal value\n      (\"EPS_Lenkmoment\", \"LH_EPS_03\", 0),           # Absolute driver torque input\n      (\"EPS_VZ_Lenkmoment\", \"LH_EPS_03\", 0),        # Driver torque input sign\n      (\"EPS_HCA_Status\", \"LH_EPS_03\", 3),           # EPS HCA control status\n      (\"ESP_Tastung_passiv\", \"ESP_21\", 0),          # Stability control disabled\n      (\"ESP_Haltebestaetigung\", \"ESP_21\", 0),       # prevents set point creep\n      (\"KBI_MFA_v_Einheit_02\", \"Einheiten_01\", 0),  # MPH vs KMH speed display\n      (\"KBI_Handbremse\", \"Kombi_01\", 0),            # Manual handbrake applied\n      (\"TSK_Status\", \"TSK_06\", 0),                  # ACC engagement status from drivetrain coordinator\n      (\"GRA_Hauptschalter\", \"GRA_ACC_01\", 0),       # ACC button, on/off\n      (\"GRA_Abbrechen\", \"GRA_ACC_01\", 0),           # ACC button, cancel\n      (\"GRA_Tip_Setzen\", \"GRA_ACC_01\", 0),          # ACC button, set\n      (\"GRA_Tip_Hoch\", \"GRA_ACC_01\", 0),            # ACC button, increase or accel\n      (\"GRA_Tip_Runter\", \"GRA_ACC_01\", 0),          # ACC button, decrease or decel\n      (\"GRA_Tip_Wiederaufnahme\", \"GRA_ACC_01\", 0),  # ACC button, resume\n      (\"GRA_Verstellung_Zeitluecke\", \"GRA_ACC_01\", 0),  # ACC button, time gap adj\n      (\"GRA_Typ_Hauptschalter\", \"GRA_ACC_01\", 0),   # ACC main button type\n      (\"GRA_Tip_Stufe_2\", \"GRA_ACC_01\", 0),         # unknown related to stalk type\n      (\"GRA_ButtonTypeInfo\", \"GRA_ACC_01\", 0),      # unknown related to stalk type\n      (\"COUNTER\", \"GRA_ACC_01\", 0),                 # GRA_ACC_01 CAN message counter\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"LWI_01\", 100),      # From J500 Steering Assist with integrated sensors\n      (\"LH_EPS_03\", 100),   # From J500 Steering Assist with integrated sensors\n      (\"ESP_19\", 100),      # From J104 ABS/ESP controller\n      (\"ESP_05\", 50),       # From J104 ABS/ESP controller\n      (\"ESP_21\", 50),       # From J104 ABS/ESP controller\n      (\"Motor_20\", 50),     # From J623 Engine control module\n      (\"TSK_06\", 50),       # From J623 Engine control module\n      (\"ESP_02\", 50),       # From J104 ABS/ESP controller\n      (\"GRA_ACC_01\", 33),   # From J533 CAN gateway (via LIN from steering wheel controls)\n      (\"Gateway_72\", 10),   # From J533 CAN gateway (aggregated data)\n      (\"Airbag_02\", 5),     # From J234 Airbag control module\n      (\"Kombi_01\", 2),      # From J285 Instrument cluster\n      (\"Blinkmodi_02\", 1),  # From J519 BCM (sent at 1Hz when no lights active, 50Hz when active)\n      (\"Einheiten_01\", 1),  # From J??? not known if gateway, cluster, or BCM\n    ]\n\n    if CP.transmissionType == TransmissionType.automatic:\n      signals += [(\"GE_Fahrstufe\", \"Getriebe_11\", 0)]  # Auto trans gear selector position\n      checks += [(\"Getriebe_11\", 20)]  # From J743 Auto transmission control module\n    elif CP.transmissionType == TransmissionType.direct:\n      signals += [(\"GearPosition\", \"EV_Gearshift\", 0)]  # EV gear selector position\n      checks += [(\"EV_Gearshift\", 10)]  # From J??? unknown EV control module\n    elif CP.transmissionType == TransmissionType.manual:\n      signals += [(\"MO_Kuppl_schalter\", \"Motor_14\", 0),  # Clutch switch\n                  (\"BCM1_Rueckfahrlicht_Schalter\", \"Gateway_72\", 0)]  # Reverse light from BCM\n      checks += [(\"Motor_14\", 10)]  # From J623 Engine control module\n\n    if CP.networkLocation == NetworkLocation.fwdCamera:\n      # Radars are here on CANBUS.pt\n      signals += MqbExtraSignals.fwd_radar_signals\n      checks += MqbExtraSignals.fwd_radar_checks\n      if CP.enableBsm:\n        signals += MqbExtraSignals.bsm_radar_signals\n        checks += MqbExtraSignals.bsm_radar_checks\n\n    return CANParser(DBC_FILES.mqb, signals, checks, CANBUS.pt)\n\n  @staticmethod\n  def get_cam_can_parser(CP):\n\n    signals = [\n      # sig_name, sig_address, default\n      (\"LDW_SW_Warnung_links\", \"LDW_02\", 0),          # Blind spot in warning mode on left side due to lane departure\n      (\"LDW_SW_Warnung_rechts\", \"LDW_02\", 0),         # Blind spot in warning mode on right side due to lane departure\n      (\"LDW_Seite_DLCTLC\", \"LDW_02\", 0),              # Direction of most likely lane departure (left or right)\n      (\"LDW_DLC\", \"LDW_02\", 0),                       # Lane departure, distance to line crossing\n      (\"LDW_TLC\", \"LDW_02\", 0),                       # Lane departure, time to line crossing\n    ]\n\n    checks = [\n      # sig_address, frequency\n      (\"LDW_02\", 10)        # From R242 Driver assistance camera\n    ]\n\n    if CP.networkLocation == NetworkLocation.gateway:\n      # Radars are here on CANBUS.cam\n      signals += MqbExtraSignals.fwd_radar_signals\n      checks += MqbExtraSignals.fwd_radar_checks\n      if CP.enableBsm:\n        signals += MqbExtraSignals.bsm_radar_signals\n        checks += MqbExtraSignals.bsm_radar_checks\n\n    return CANParser(DBC_FILES.mqb, signals, checks, CANBUS.cam)\n\nclass MqbExtraSignals:\n  # Additional signal and message lists for optional or bus-portable controllers\n  fwd_radar_signals = [\n    (\"ACC_Wunschgeschw\", \"ACC_02\", 0),              # ACC set speed\n    (\"AWV2_Freigabe\", \"ACC_10\", 0),                 # FCW brake jerk release\n    (\"ANB_Teilbremsung_Freigabe\", \"ACC_10\", 0),     # AEB partial braking release\n    (\"ANB_Zielbremsung_Freigabe\", \"ACC_10\", 0),     # AEB target braking release\n  ]\n  fwd_radar_checks = [\n    (\"ACC_10\", 50),                                 # From J428 ACC radar control module\n    (\"ACC_02\", 17),                                 # From J428 ACC radar control module\n  ]\n  bsm_radar_signals = [\n    (\"SWA_Infostufe_SWA_li\", \"SWA_01\", 0),          # Blind spot object info, left\n    (\"SWA_Warnung_SWA_li\", \"SWA_01\", 0),            # Blind spot object warning, left\n    (\"SWA_Infostufe_SWA_re\", \"SWA_01\", 0),          # Blind spot object info, right\n    (\"SWA_Warnung_SWA_re\", \"SWA_01\", 0),            # Blind spot object warning, right\n  ]\n  bsm_radar_checks = [\n    (\"SWA_01\", 20),                                 # From J1086 Lane Change Assist\n  ]\n"
  },
  {
    "path": "selfdrive/car/volkswagen/interface.py",
    "content": "from cereal import car\nfrom selfdrive.car.volkswagen.values import CAR, BUTTON_STATES, CANBUS, NetworkLocation, TransmissionType, GearShifter\nfrom selfdrive.car import STD_CARGO_KG, scale_rot_inertia, scale_tire_stiffness, gen_empty_fingerprint\nfrom selfdrive.car.interfaces import CarInterfaceBase\nfrom common.dp_common import common_interface_atl, common_interface_get_params_lqr\n\nEventName = car.CarEvent.EventName\n\n\nclass CarInterface(CarInterfaceBase):\n  def __init__(self, CP, CarController, CarState):\n    super().__init__(CP, CarController, CarState)\n\n    self.displayMetricUnitsPrev = None\n    self.buttonStatesPrev = BUTTON_STATES.copy()\n\n    if CP.networkLocation == NetworkLocation.fwdCamera:\n      self.ext_bus = CANBUS.pt\n      self.cp_ext = self.cp\n    else:\n      self.ext_bus = CANBUS.cam\n      self.cp_ext = self.cp_cam\n\n    # timebomb_counter mod\n    self.cruise_enabled_prev = False\n    self.timebomb_counter = 0\n    self.wheel_grabbed = False\n    self.timebomb_bypass_counter = 0\n\n  @staticmethod\n  def get_params(candidate, fingerprint=gen_empty_fingerprint(), car_fw=None):\n    ret = CarInterfaceBase.get_std_params(candidate, fingerprint)\n    ret.carName = \"volkswagen\"\n    ret.communityFeature = True\n    ret.radarOffCan = True\n\n    if True:  # pylint: disable=using-constant-test\n      # Set global MQB parameters\n      ret.safetyModel = car.CarParams.SafetyModel.volkswagen\n      ret.enableBsm = 0x30F in fingerprint[0]\n\n      if 0xAD in fingerprint[0]:  # Getriebe_11\n        ret.transmissionType = TransmissionType.automatic\n      elif 0x187 in fingerprint[0]:  # EV_Gearshift\n        ret.transmissionType = TransmissionType.direct\n      else:  # No trans message at all, must be a true stick-shift manual\n        ret.transmissionType = TransmissionType.manual\n\n      if 0x86 in fingerprint[1]:  # LWI_01 seen on bus 1, we're wired to the CAN gateway\n        ret.networkLocation = NetworkLocation.gateway\n      # dp - we need this for chinese vw?\n      if 0xFD in fingerprint[1]:\n        ret.networkLocation = NetworkLocation.gateway\n      else:  # We're wired to the LKAS camera\n        ret.networkLocation = NetworkLocation.fwdCamera\n\n    # Global tuning defaults, can be overridden per-vehicle\n\n    ret.steerActuatorDelay = 0.05\n    ret.steerRateCost = 1.0\n    ret.steerLimitTimer = 0.4\n    ret.steerRatio = 15.6  # Let the params learner figure this out\n    tire_stiffness_factor = 1.0  # Let the params learner figure this out\n    ret.lateralTuning.pid.kpBP = [0.]\n    ret.lateralTuning.pid.kiBP = [0.]\n    ret.lateralTuning.pid.kf = 0.00006\n    ret.lateralTuning.pid.kpV = [0.6]\n    ret.lateralTuning.pid.kiV = [0.2]\n\n    # Per-chassis tuning values, override tuning defaults here if desired\n\n    if candidate == CAR.ATLAS_MK1:\n      ret.mass = 2011 + STD_CARGO_KG\n      ret.wheelbase = 2.98\n\n    elif candidate == CAR.GOLF_MK7:\n      ret.mass = 1397 + STD_CARGO_KG\n      ret.wheelbase = 2.62\n\n    elif candidate == CAR.JETTA_MK7:\n      ret.mass = 1328 + STD_CARGO_KG\n      ret.wheelbase = 2.71\n\n    elif candidate == CAR.PASSAT_MK8:\n      ret.mass = 1551 + STD_CARGO_KG\n      ret.wheelbase = 2.79\n\n    elif candidate == CAR.TCROSS_MK1:\n      ret.mass = 1150 + STD_CARGO_KG\n      ret.wheelbase = 2.60\n\n    elif candidate == CAR.TIGUAN_MK2:\n      ret.mass = 1715 + STD_CARGO_KG\n      ret.wheelbase = 2.74\n\n    elif candidate == CAR.TOURAN_MK2:\n      ret.mass = 1516 + STD_CARGO_KG\n      ret.wheelbase = 2.79\n\n    elif candidate == CAR.AUDI_A3_MK3:\n      ret.mass = 1335 + STD_CARGO_KG\n      ret.wheelbase = 2.61\n\n    elif candidate == CAR.AUDI_Q2_MK1:\n      ret.mass = 1205 + STD_CARGO_KG\n      ret.wheelbase = 2.61\n\n    elif candidate == CAR.SEAT_ATECA_MK1:\n      ret.mass = 1900 + STD_CARGO_KG\n      ret.wheelbase = 2.64\n\n    elif candidate == CAR.SEAT_LEON_MK3:\n      ret.mass = 1227 + STD_CARGO_KG\n      ret.wheelbase = 2.64\n\n    elif candidate == CAR.SKODA_KODIAQ_MK1:\n      ret.mass = 1569 + STD_CARGO_KG\n      ret.wheelbase = 2.79\n\n    elif candidate == CAR.SKODA_OCTAVIA_MK3:\n      ret.mass = 1388 + STD_CARGO_KG\n      ret.wheelbase = 2.68\n\n    elif candidate == CAR.SKODA_SCALA_MK1:\n      ret.mass = 1192 + STD_CARGO_KG\n      ret.wheelbase = 2.65\n\n    elif candidate == CAR.SKODA_SUPERB_MK3:\n      ret.mass = 1505 + STD_CARGO_KG\n      ret.wheelbase = 2.84\n\n    # TODO: get actual value, for now starting with reasonable value for\n    # civic and scaling by mass and wheelbase\n    ret.rotationalInertia = scale_rot_inertia(ret.mass, ret.wheelbase)\n\n    # TODO: start from empirically derived lateral slip stiffness for the civic and scale by\n    # mass and CG position, so all cars will have approximately similar dyn behaviors\n    ret.centerToFront = ret.wheelbase * 0.45\n    ret.tireStiffnessFront, ret.tireStiffnessRear = scale_tire_stiffness(ret.mass, ret.wheelbase, ret.centerToFront,\n                                                                         tire_stiffness_factor=tire_stiffness_factor)\n    # dp\n    ret = common_interface_get_params_lqr(ret)\n\n    return ret\n\n  # returns a car.CarState\n  def update(self, c, can_strings, dragonconf):\n    buttonEvents = []\n\n    # Process the most recent CAN message traffic, and check for validity\n    # The camera CAN has no signals we use at this time, but we process it\n    # anyway so we can test connectivity with can_valid\n    self.cp.update_strings(can_strings)\n    self.cp_cam.update_strings(can_strings)\n\n    ret = self.CS.update(self.cp, self.cp_cam, self.cp_ext, self.CP.transmissionType)\n    # dp\n    self.dragonconf = dragonconf\n    ret.cruiseState.enabled = common_interface_atl(ret, dragonconf.dpAtl)\n    ret.canValid = self.cp.can_valid and self.cp_cam.can_valid\n    ret.steeringRateLimited = self.CC.steer_rate_limited if self.CC is not None else False\n\n    # TODO: add a field for this to carState, car interface code shouldn't write params\n    # Update the device metric configuration to match the car at first startup,\n    # or if there's been a change.\n    #if self.CS.displayMetricUnits != self.displayMetricUnitsPrev:\n    #  put_nonblocking(\"IsMetric\", \"1\" if self.CS.displayMetricUnits else \"0\")\n\n    # Check for and process state-change events (button press or release) from\n    # the turn stalk switch or ACC steering wheel/control stalk buttons.\n    for button in self.CS.buttonStates:\n      if self.CS.buttonStates[button] != self.buttonStatesPrev[button]:\n        be = car.CarState.ButtonEvent.new_message()\n        be.type = button\n        be.pressed = self.CS.buttonStates[button]\n        buttonEvents.append(be)\n\n    events = self.create_common_events(ret, extra_gears=[GearShifter.eco, GearShifter.sport, GearShifter.manumatic])\n\n    # Vehicle health and operation safety checks\n    if self.CS.parkingBrakeSet:\n      events.add(EventName.parkBrake)\n\n    if dragonconf.dpVwTimebombAssist:\n      ret.stopSteering = False\n      if ret.cruiseState.enabled:\n        self.timebomb_counter += 1\n      else:\n        self.timebomb_counter = 0\n        self.timebomb_bypass_counter = 0\n\n      if self.timebomb_counter >= 33000: # 330*100 time in seconds until counter threshold for timebombWarn alert\n        if not self.wheel_grabbed:\n          events.add(EventName.timebombWarn)\n        if self.wheel_grabbed or ret.steeringPressed:\n          self.wheel_grabbed = True\n          ret.stopSteering = True\n          self.timebomb_bypass_counter += 1\n          if self.timebomb_bypass_counter >= 300: # 3*100 time alloted for bypass\n            self.wheel_grabbed = False\n            self.timebomb_counter = 0\n            self.timebomb_bypass_counter = 0\n            events.add(EventName.timebombBypassed)\n          else:\n            events.add(EventName.timebombBypassing)\n\n    ret.events = events.to_msg()\n    ret.buttonEvents = buttonEvents\n\n    # update previous car states\n    self.displayMetricUnitsPrev = self.CS.displayMetricUnits\n    self.buttonStatesPrev = self.CS.buttonStates.copy()\n\n    self.CS.out = ret.as_reader()\n    return self.CS.out\n\n  def apply(self, c):\n    can_sends = self.CC.update(c.enabled, self.CS, self.frame, self.ext_bus, c.actuators,\n                   c.hudControl.visualAlert,\n                   c.hudControl.leftLaneVisible,\n                   c.hudControl.rightLaneVisible,\n                   c.hudControl.leftLaneDepart,\n                   c.hudControl.rightLaneDepart,\n                               self.dragonconf)\n    self.frame += 1\n    return can_sends\n"
  },
  {
    "path": "selfdrive/car/volkswagen/radar_interface.py",
    "content": "#!/usr/bin/env python3\nfrom selfdrive.car.interfaces import RadarInterfaceBase\n\nclass RadarInterface(RadarInterfaceBase):\n  pass\n"
  },
  {
    "path": "selfdrive/car/volkswagen/values.py",
    "content": "# flake8: noqa\n\nfrom collections import defaultdict\nfrom typing import Dict\n\nfrom cereal import car\nfrom selfdrive.car import dbc_dict\n\nEcu = car.CarParams.Ecu\nNetworkLocation = car.CarParams.NetworkLocation\nTransmissionType = car.CarParams.TransmissionType\nGearShifter = car.CarState.GearShifter\n\nclass CarControllerParams:\n  HCA_STEP = 2                   # HCA_01 message frequency 50Hz\n  LDW_STEP = 10                  # LDW_02 message frequency 10Hz\n  GRA_ACC_STEP = 3               # GRA_ACC_01 message frequency 33Hz\n\n  GRA_VBP_STEP = 100             # Send ACC virtual button presses once a second\n  GRA_VBP_COUNT = 16             # Send VBP messages for ~0.5s (GRA_ACC_STEP * 16)\n\n  # Observed documented MQB limits: 3.00 Nm max, rate of change 5.00 Nm/sec.\n  # Limiting rate-of-change based on real-world testing and Comma's safety\n  # requirements for minimum time to lane departure.\n  STEER_MAX = 300                # Max heading control assist torque 3.00 Nm\n  STEER_DELTA_UP = 4             # Max HCA reached in 1.50s (STEER_MAX / (50Hz * 1.50))\n  STEER_DELTA_DOWN = 10          # Min HCA reached in 0.60s (STEER_MAX / (50Hz * 0.60))\n  STEER_DRIVER_ALLOWANCE = 80\n  STEER_DRIVER_MULTIPLIER = 3    # weight driver torque heavily\n  STEER_DRIVER_FACTOR = 1        # from dbc\n\nclass CANBUS:\n  pt = 0\n  cam = 2\n\nclass DBC_FILES:\n  mqb = \"vw_mqb_2010\"  # Used for all cars with MQB-style CAN messaging\n\nDBC = defaultdict(lambda: dbc_dict(DBC_FILES.mqb, None))  # type: Dict[str, Dict[str, str]]\n\nBUTTON_STATES = {\n  \"accelCruise\": False,\n  \"decelCruise\": False,\n  \"cancel\": False,\n  \"setCruise\": False,\n  \"resumeCruise\": False,\n  \"gapAdjustCruise\": False\n}\n\nMQB_LDW_MESSAGES = {\n  \"none\": 0,                            # Nothing to display\n  \"laneAssistUnavailChime\": 1,          # \"Lane Assist currently not available.\" with chime\n  \"laneAssistUnavailNoSensorChime\": 3,  # \"Lane Assist not available. No sensor view.\" with chime\n  \"laneAssistTakeOverUrgent\": 4,        # \"Lane Assist: Please Take Over Steering\" with urgent beep\n  \"emergencyAssistUrgent\": 6,           # \"Emergency Assist: Please Take Over Steering\" with urgent beep\n  \"laneAssistTakeOverChime\": 7,         # \"Lane Assist: Please Take Over Steering\" with chime\n  \"laneAssistTakeOverSilent\": 8,        # \"Lane Assist: Please Take Over Steering\" silent\n  \"emergencyAssistChangingLanes\": 9,    # \"Emergency Assist: Changing lanes...\" with urgent beep\n  \"laneAssistDeactivated\": 10,          # \"Lane Assist deactivated.\" silent with persistent icon afterward\n}\n\n# Check the 7th and 8th characters of the VIN before adding a new CAR. If the\n# chassis code is already listed below, don't add a new CAR, just add to the\n# FW_VERSIONS for that existing CAR.\n# Exception: SEAT Leon and SEAT Ateca share a chassis code\n\nclass CAR:\n  ATLAS_MK1 = \"VOLKSWAGEN ATLAS 1ST GEN\"      # Chassis CA, Mk1 VW Atlas and Atlas Cross Sport\n  GOLF_MK7 = \"VOLKSWAGEN GOLF 7TH GEN\"        # Chassis 5G/AU/BA/BE, Mk7 VW Golf and variants\n  JETTA_MK7 = \"VOLKSWAGEN JETTA 7TH GEN\"      # Chassis BU, Mk7 Jetta\n  PASSAT_MK8 = \"VOLKSWAGEN PASSAT 8TH GEN\"    # Chassis 3G, Mk8 Passat and variants\n  TCROSS_MK1 = \"VOLKSWAGEN T-CROSS 1ST GEN\"   # Chassis C1, Mk1 VW T-Cross SWB and LWB variants\n  TIGUAN_MK2 = \"VOLKSWAGEN TIGUAN 2ND GEN\"    # Chassis AD/BW, Mk2 VW Tiguan and variants\n  TOURAN_MK2 = \"VOLKSWAGEN TOURAN 2ND GEN\"    # Chassis 1T, Mk2 VW Touran and variants\n  AUDI_A3_MK3 = \"AUDI A3 3RD GEN\"             # Chassis 8V/FF, Mk3 Audi A3 and variants\n  AUDI_Q2_MK1 = \"AUDI Q2 1ST GEN\"             # Chassis GA, Mk1 Audi Q2 (RoW) and Q2L (China only)\n  SEAT_ATECA_MK1 = \"SEAT ATECA 1ST GEN\"       # Chassis 5F, Mk1 SEAT Ateca and CUPRA Ateca\n  SEAT_LEON_MK3 = \"SEAT LEON 3RD GEN\"         # Chassis 5F, Mk3 SEAT Leon and variants\n  SKODA_KODIAQ_MK1 = \"SKODA KODIAQ 1ST GEN\"   # Chassis NS, Mk1 Skoda Kodiaq\n  SKODA_SCALA_MK1 = \"SKODA SCALA 1ST GEN\"     # Chassis NW, Mk1 Skoda Scala and Skoda Kamiq\n  SKODA_SUPERB_MK3 = \"SKODA SUPERB 3RD GEN\"   # Chassis 3V/NP, Mk3 Skoda Superb and variants\n  SKODA_OCTAVIA_MK3 = \"SKODA OCTAVIA 3RD GEN\" # Chassis NE, Mk3 Skoda Octavia and variants\n\n# All supported cars should return FW from the engine, srs, eps, and fwdRadar. Cars\n# with a manual trans won't return transmission firmware, but all other cars will.\n#\n# The 0xF187 SW part number query should return in the form of N[NX][NX] NNN NNN [X[X]],\n# where N=number, X=letter, and the trailing two letters are optional. Performance\n# tuners sometimes tamper with that field (e.g. 8V0 9C0 BB0 1 from COBB/EQT). Tampered\n# ECU SW part numbers are invalid for vehicle ID and compatibility checks. Try to have\n# them repaired by the tuner before including them in openpilot.\n\nFW_VERSIONS = {\n  CAR.ATLAS_MK1: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8703H906026AA\\xf1\\x899970',\n      b'\\xf1\\x8703H906026F \\xf1\\x896696',\n      b'\\xf1\\x8703H906026F \\xf1\\x899970',\n      b'\\xf1\\x8703H906026S \\xf1\\x896693',\n      b'\\xf1\\x8703H906026S \\xf1\\x899970',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x8709G927158A \\xf1\\x893387',\n      b'\\xf1\\x8709G927158DR\\xf1\\x893536',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x873Q0959655BC\\xf1\\x890503\\xf1\\x82\\0161914151912001103111122031200',\n      b'\\xf1\\x873Q0959655BN\\xf1\\x890713\\xf1\\x82\\0162214152212001105141122052900',\n      b'\\xf1\\x873Q0959655DB\\xf1\\x890720\\xf1\\x82\\0162214152212001105141122052900',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x873QF909144B \\xf1\\x891582\\xf1\\x82\\00571B60924A1',\n      b'\\xf1\\x875Q0909143P \\xf1\\x892051\\xf1\\x820528B6090105',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x875Q0907572H \\xf1\\x890620',\n      b'\\xf1\\x875Q0907572J \\xf1\\x890654',\n      b'\\xf1\\x875Q0907572P \\xf1\\x890682',\n    ],\n  },\n  CAR.GOLF_MK7: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906016A \\xf1\\x897697',\n      b'\\xf1\\x8704E906016AD\\xf1\\x895758',\n      b'\\xf1\\x8704E906023AG\\xf1\\x891726',\n      b'\\xf1\\x8704E906023BN\\xf1\\x894518',\n      b'\\xf1\\x8704E906024K \\xf1\\x896811',\n      b'\\xf1\\x8704E906027GR\\xf1\\x892394',\n      b'\\xf1\\x8704E906027HD\\xf1\\x893742',\n      b'\\xf1\\x8704E906027MA\\xf1\\x894958',\n      b'\\xf1\\x8704L906026BP\\xf1\\x897608',\n      b'\\xf1\\x8704L906026NF\\xf1\\x899528',\n      b'\\xf1\\x8704L906056CL\\xf1\\x893823',\n      b'\\xf1\\x8704L906056CR\\xf1\\x895813',\n      b'\\xf1\\x8704L906056HE\\xf1\\x893758',\n      b'\\xf1\\x870EA906016A \\xf1\\x898343',\n      b'\\xf1\\x870EA906016F \\xf1\\x895002',\n      b'\\xf1\\x870EA906016S \\xf1\\x897207',\n      b'\\xf1\\x875G0906259  \\xf1\\x890007',\n      b'\\xf1\\x875G0906259J \\xf1\\x890002',\n      b'\\xf1\\x875G0906259L \\xf1\\x890002',\n      b'\\xf1\\x875G0906259N \\xf1\\x890003',\n      b'\\xf1\\x875G0906259Q \\xf1\\x890002',\n      b'\\xf1\\x875G0906259Q \\xf1\\x892313',\n      b'\\xf1\\x878V0906259H \\xf1\\x890002',\n      b'\\xf1\\x878V0906259J \\xf1\\x890003',\n      b'\\xf1\\x878V0906259K \\xf1\\x890001',\n      b'\\xf1\\x878V0906259P \\xf1\\x890001',\n      b'\\xf1\\x878V0906259Q \\xf1\\x890002',\n      b'\\xf1\\x878V0906264F \\xf1\\x890003',\n      b'\\xf1\\x878V0906264L \\xf1\\x890002',\n      b'\\xf1\\x878V0906264M \\xf1\\x890001',\n      b'\\xf1\\x878V09C0BB01 \\xf1\\x890001',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x8709G927749AP\\xf1\\x892943',\n      b'\\xf1\\x8709S927158A \\xf1\\x893585',\n      b'\\xf1\\x870CW300041H \\xf1\\x891010',\n      b'\\xf1\\x870CW300042F \\xf1\\x891604',\n      b'\\xf1\\x870CW300043B \\xf1\\x891601',\n      b'\\xf1\\x870CW300045  \\xf1\\x894531',\n      b'\\xf1\\x870CW300047D \\xf1\\x895261',\n      b'\\xf1\\x870CW300048J \\xf1\\x890611',\n      b'\\xf1\\x870D9300012  \\xf1\\x894904',\n      b'\\xf1\\x870D9300012  \\xf1\\x894913',\n      b'\\xf1\\x870D9300012  \\xf1\\x894937',\n      b'\\xf1\\x870D9300012  \\xf1\\x895045',\n      b'\\xf1\\x870D9300014M \\xf1\\x895004',\n      b'\\xf1\\x870D9300020S \\xf1\\x895201',\n      b'\\xf1\\x870D9300040S \\xf1\\x894311',\n      b'\\xf1\\x870D9300041H \\xf1\\x895220',\n      b'\\xf1\\x870DD300045K \\xf1\\x891120',\n      b'\\xf1\\x870DD300046F \\xf1\\x891601',\n      b'\\xf1\\x870GC300012A \\xf1\\x891403',\n      b'\\xf1\\x870GC300014B \\xf1\\x892401',\n      b'\\xf1\\x870GC300014B \\xf1\\x892405',\n      b'\\xf1\\x870GC300020G \\xf1\\x892401',\n      b'\\xf1\\x870GC300020G \\xf1\\x892403',\n      b'\\xf1\\x870GC300020G \\xf1\\x892404',\n      b'\\xf1\\x870GC300043T \\xf1\\x899999',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655AA\\xf1\\x890386\\xf1\\x82\\0211413001113120043114317121C111C9113',\n      b'\\xf1\\x875Q0959655AA\\xf1\\x890386\\xf1\\x82\\0211413001113120053114317121C111C9113',\n      b'\\xf1\\x875Q0959655AA\\xf1\\x890388\\xf1\\x82\\0211413001113120043114317121C111C9113',\n      b'\\xf1\\x875Q0959655AA\\xf1\\x890388\\xf1\\x82\\0211413001113120043114417121411149113',\n      b'\\xf1\\x875Q0959655AA\\xf1\\x890388\\xf1\\x82\\0211413001113120053114317121C111C9113',\n      b'\\xf1\\x875Q0959655BH\\xf1\\x890336\\xf1\\x82\\02314160011123300314211012230229333463100',\n      b'\\xf1\\x875Q0959655BT\\xf1\\x890403\\xf1\\x82\\023141600111233003142404A2252229333463100',\n      b'\\xf1\\x875Q0959655BT\\xf1\\x890403\\xf1\\x82\\023141600111233003142405A2252229333463100',\n      b'\\xf1\\x875Q0959655D \\xf1\\x890388\\xf1\\x82\\0211413001113120006110417121A101A9113',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890830\\xf1\\x82\\023271112111312--071104171825102591131211',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890830\\xf1\\x82\\023271212111312--071104171838103891131211',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890830\\xf1\\x82\\023341512112212--071104172328102891131211',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890830\\xf1\\x82\\x13272512111312--07110417182C102C91131211',\n      b'\\xf1\\x875Q0959655M \\xf1\\x890361\\xf1\\x82\\0211413001112120041114115121611169112',\n      b'\\xf1\\x875Q0959655S \\xf1\\x890870\\xf1\\x82\\02315120011211200621143171717111791132111',\n      b'\\xf1\\x875Q0959655S \\xf1\\x890870\\xf1\\x82\\02324230011211200061104171724102491132111',\n      b'\\xf1\\x875Q0959655S \\xf1\\x890870\\xf1\\x82\\02324230011211200621143171724112491132111',\n      b'\\xf1\\x875Q0959655S \\xf1\\x890870\\xf1\\x82\\x1315120011211200061104171717101791132111',\n      b'\\xf1\\x875Q0959655T \\xf1\\x890825\\xf1\\x82\\023271200111312--071104171837103791132111',\n      b'\\xf1\\x875Q0959655T \\xf1\\x890830\\xf1\\x82\\x13271100111312--071104171826102691131211',\n      b'\\xf1\\x875QD959655  \\xf1\\x890388\\xf1\\x82\\x111413001113120006110417121D101D9112',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x873Q0909144F \\xf1\\x895043\\xf1\\x82\\00561A01612A0',\n      b'\\xf1\\x873Q0909144H \\xf1\\x895061\\xf1\\x82\\00566A0J612A1',\n      b'\\xf1\\x873Q0909144J \\xf1\\x895063\\xf1\\x82\\00566A00514A1',\n      b'\\xf1\\x873Q0909144J \\xf1\\x895063\\xf1\\x82\\00566A0J712A1',\n      b'\\xf1\\x873Q0909144K \\xf1\\x895072\\xf1\\x82\\00571A0J714A1',\n      b'\\xf1\\x873Q0909144L \\xf1\\x895081\\xf1\\x82\\x0571A0JA15A1',\n      b'\\xf1\\x873Q0909144M \\xf1\\x895082\\xf1\\x82\\00571A01A18A1',\n      b'\\xf1\\x873Q0909144M \\xf1\\x895082\\xf1\\x82\\00571A0JA16A1',\n      b'\\xf1\\x875Q0909143K \\xf1\\x892033\\xf1\\x820519A9040203',\n      b'\\xf1\\x875Q0909144AA\\xf1\\x891081\\xf1\\x82\\00521A00441A1',\n      b'\\xf1\\x875Q0909144AA\\xf1\\x891081\\xf1\\x82\\x0521A00641A1',\n      b'\\xf1\\x875Q0909144AB\\xf1\\x891082\\xf1\\x82\\00521A00442A1',\n      b'\\xf1\\x875Q0909144AB\\xf1\\x891082\\xf1\\x82\\00521A00642A1',\n      b'\\xf1\\x875Q0909144AB\\xf1\\x891082\\xf1\\x82\\00521A07B05A1',\n      b'\\xf1\\x875Q0909144L \\xf1\\x891021\\xf1\\x82\\00522A00402A0',\n      b'\\xf1\\x875Q0909144P \\xf1\\x891043\\xf1\\x82\\00511A00403A0',\n      b'\\xf1\\x875Q0909144R \\xf1\\x891061\\xf1\\x82\\00516A00604A1',\n      b'\\xf1\\x875Q0909144S \\xf1\\x891063\\xf1\\x82\\00516A00604A1',\n      b'\\xf1\\x875Q0909144S \\xf1\\x891063\\xf1\\x82\\00516A07A02A1',\n      b'\\xf1\\x875Q0909144T \\xf1\\x891072\\xf1\\x82\\00521A00507A1',\n      b'\\xf1\\x875Q0909144T \\xf1\\x891072\\xf1\\x82\\00521A20B03A1',\n      b'\\xf1\\x875QD909144B \\xf1\\x891072\\xf1\\x82\\x0521A00507A1',\n      b'\\xf1\\x875QM909144A \\xf1\\x891072\\xf1\\x82\\x0521A20B03A1',\n      b'\\xf1\\x875QM909144B \\xf1\\x891081\\xf1\\x82\\00521A00442A1',\n      b'\\xf1\\x875QN909144A \\xf1\\x895081\\xf1\\x82\\00571A01A16A1',\n      b'\\xf1\\x875QN909144A \\xf1\\x895081\\xf1\\x82\\00571A01A18A1',\n      b'\\xf1\\x875QN909144A \\xf1\\x895081\\xf1\\x82\\x0571A01A17A1',\n      b'\\xf1\\x875QN909144B \\xf1\\x895082\\xf1\\x82\\00571A01A18A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x875Q0907572A \\xf1\\x890141\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572B \\xf1\\x890200\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572C \\xf1\\x890210\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572D \\xf1\\x890304\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572F \\xf1\\x890400\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572G \\xf1\\x890571',\n      b'\\xf1\\x875Q0907572H \\xf1\\x890620',\n      b'\\xf1\\x875Q0907572J \\xf1\\x890654',\n      b'\\xf1\\x875Q0907572P \\xf1\\x890682',\n      b'\\xf1\\x875Q0907572R \\xf1\\x890771',\n    ],\n  },\n  CAR.JETTA_MK7: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906024AK\\xf1\\x899937',\n      b'\\xf1\\x8704E906024AS\\xf1\\x899912',\n      b'\\xf1\\x8704E906024B \\xf1\\x895594',\n      b'\\xf1\\x8704E906024L \\xf1\\x895595',\n      b'\\xf1\\x8704E906027MS\\xf1\\x896223',\n      b'\\xf1\\x875G0906259T \\xf1\\x890003',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x8709G927158BQ\\xf1\\x893545',\n      b'\\xf1\\x8709S927158BS\\xf1\\x893642',\n      b'\\xf1\\x8709S927158R \\xf1\\x893552',\n      b'\\xf1\\x8709S927158R \\xf1\\x893587',\n      b'\\xf1\\x870GC300020N \\xf1\\x892803',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655AG\\xf1\\x890336\\xf1\\x82\\02314171231313500314611011630169333463100',\n      b'\\xf1\\x875Q0959655BM\\xf1\\x890403\\xf1\\x82\\02314171231313500314642011650169333463100',\n      b'\\xf1\\x875Q0959655BM\\xf1\\x890403\\xf1\\x82\\02314171231313500314643011650169333463100',\n      b'\\xf1\\x875Q0959655BR\\xf1\\x890403\\xf1\\x82\\02311170031313300314240011150119333433100',\n      b'\\xf1\\x875Q0959655BR\\xf1\\x890403\\xf1\\x82\\02319170031313300314240011550159333463100',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875QM909144B \\xf1\\x891081\\xf1\\x82\\00521A10A01A1',\n      b'\\xf1\\x875QM909144B \\xf1\\x891081\\xf1\\x82\\x0521B00404A1',\n      b'\\xf1\\x875QM909144C \\xf1\\x891082\\xf1\\x82\\00521A00642A1',\n      b'\\xf1\\x875QM909144C \\xf1\\x891082\\xf1\\x82\\00521A10A01A1',\n      b'\\xf1\\x875QN909144B \\xf1\\x895082\\xf1\\x82\\00571A10A11A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x875Q0907572N \\xf1\\x890681',\n      b'\\xf1\\x875Q0907572R \\xf1\\x890771',\n    ],\n  },\n  CAR.PASSAT_MK8: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906023AH\\xf1\\x893379',\n      b'\\xf1\\x8704L906026GA\\xf1\\x892013',\n      b'\\xf1\\x873G0906264  \\xf1\\x890004',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300048R \\xf1\\x890610',\n      b'\\xf1\\x870D9300014L \\xf1\\x895002',\n      b'\\xf1\\x870DD300045T \\xf1\\x891601',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x873Q0959655AN\\xf1\\x890306\\xf1\\x82\\r58160058140013036914110311',\n      b'\\xf1\\x873Q0959655BB\\xf1\\x890195\\xf1\\x82\\r56140056130012026612120211',\n      b'\\xf1\\x875Q0959655S \\xf1\\x890870\\xf1\\x82\\02315120011111200631145171716121691132111',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909143M \\xf1\\x892041\\xf1\\x820522B0080803',\n      b'\\xf1\\x875Q0909144S \\xf1\\x891063\\xf1\\x82\\00516B00501A1',\n      b'\\xf1\\x875Q0909144T \\xf1\\x891072\\xf1\\x82\\00521B00703A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x873Q0907572B \\xf1\\x890192',\n      b'\\xf1\\x873Q0907572C \\xf1\\x890195',\n      b'\\xf1\\x875Q0907572R \\xf1\\x890771',\n    ],\n  },\n  CAR.TCROSS_MK1: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704C906025AK\\xf1\\x897053',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300050E \\xf1\\x891903',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x872Q0959655AJ\\xf1\\x890250\\xf1\\x82\\02212130411110411--04041104141311152H14',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x872Q1909144M \\xf1\\x896041',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x872Q0907572T \\xf1\\x890383',\n    ],\n  },\n  CAR.TIGUAN_MK2: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704L906026EJ\\xf1\\x893661',\n      b'\\xf1\\x8704L906027G \\xf1\\x899893',\n      b'\\xf1\\x875N0906259  \\xf1\\x890002',\n      b'\\xf1\\x8783A907115B \\xf1\\x890005',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x8709G927158DT\\xf1\\x893698',\n      b'\\xf1\\x870DL300011N \\xf1\\x892001',\n      b'\\xf1\\x870DL300011N \\xf1\\x892012',\n      b'\\xf1\\x870DL300013A \\xf1\\x893005',\n      b'\\xf1\\x870DL300013G \\xf1\\x892120',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655AR\\xf1\\x890317\\xf1\\x82\\02331310031333334313132573732379333313100',\n      b'\\xf1\\x875Q0959655BM\\xf1\\x890403\\xf1\\x82\\02316143231313500314641011750179333423100',\n      b'\\xf1\\x875Q0959655BT\\xf1\\x890403\\xf1\\x82\\02312110031333300314240583752379333423100',\n      b'\\xf1\\x875Q0959655BT\\xf1\\x890403\\xf1\\x82\\02331310031333336313140013950399333423100',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909143M \\xf1\\x892041\\xf1\\x820529A6060603',\n      b'\\xf1\\x875QF909144B \\xf1\\x895582\\xf1\\x82\\00571A60634A1',\n      b'\\xf1\\x875QM909144B \\xf1\\x891081\\xf1\\x82\\x0521A60604A1',\n      b'\\xf1\\x875QM909144C \\xf1\\x891082\\xf1\\x82\\00521A60804A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x872Q0907572J \\xf1\\x890156',\n      b'\\xf1\\x872Q0907572Q \\xf1\\x890342',\n      b'\\xf1\\x872Q0907572R \\xf1\\x890372',\n    ],\n  },\n  CAR.TOURAN_MK2: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704L906026HM\\xf1\\x893017',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300041E \\xf1\\x891005',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655AS\\xf1\\x890318\\xf1\\x82\\023363500213533353141324C4732479333313100',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909143P \\xf1\\x892051\\xf1\\x820531B0062105',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x873Q0907572C \\xf1\\x890195',\n    ],\n  },\n  CAR.AUDI_A3_MK3: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906023AN\\xf1\\x893695',\n      b'\\xf1\\x8704E906023AR\\xf1\\x893440',\n      b'\\xf1\\x8704E906023BL\\xf1\\x895190',\n      b'\\xf1\\x8704E906027CJ\\xf1\\x897798',\n      b'\\xf1\\x8704L997022N \\xf1\\x899459',\n      b'\\xf1\\x875G0906259L \\xf1\\x890002',\n      b'\\xf1\\x875G0906259Q \\xf1\\x890002',\n      b'\\xf1\\x878V0906264B \\xf1\\x890003',\n      b'\\xf1\\x878V0907115B \\xf1\\x890007',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300044T \\xf1\\x895245',\n      b'\\xf1\\x870CW300048  \\xf1\\x895201',\n      b'\\xf1\\x870D9300013B \\xf1\\x894931',\n      b'\\xf1\\x870D9300041N \\xf1\\x894512',\n      b'\\xf1\\x870DD300046A \\xf1\\x891602',\n      b'\\xf1\\x870DD300046F \\xf1\\x891602',\n      b'\\xf1\\x870DD300046G \\xf1\\x891601',\n      b'\\xf1\\x870GC300013M \\xf1\\x892402',\n      b'\\xf1\\x870GC300042J \\xf1\\x891402',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655AM\\xf1\\x890315\\xf1\\x82\\x1311111111111111311411011231129321212100',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890825\\xf1\\x82\\023111112111111--171115141112221291163221',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890830\\xf1\\x82\\023121111111211--261117141112231291163221',\n      b'\\xf1\\x875Q0959655J \\xf1\\x890830\\xf1\\x82\\x13121111111111--341117141212231291163221',\n      b'\\xf1\\x875Q0959655N \\xf1\\x890361\\xf1\\x82\\0211212001112110004110411111421149114',\n      b'\\xf1\\x875Q0959655N \\xf1\\x890361\\xf1\\x82\\0211212001112111104110411111521159114',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909144AB\\xf1\\x891082\\xf1\\x82\\00521G0G809A1',\n      b'\\xf1\\x875Q0909144P \\xf1\\x891043\\xf1\\x82\\00503G00303A0',\n      b'\\xf1\\x875Q0909144P \\xf1\\x891043\\xf1\\x82\\00503G00803A0',\n      b'\\xf1\\x875Q0909144R \\xf1\\x891061\\xf1\\x82\\00516G00804A1',\n      b'\\xf1\\x875Q0909144T \\xf1\\x891072\\xf1\\x82\\00521G00807A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x875Q0907572D \\xf1\\x890304\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572G \\xf1\\x890571',\n      b'\\xf1\\x875Q0907572H \\xf1\\x890620',\n      b'\\xf1\\x875Q0907572P \\xf1\\x890682',\n    ],\n  },\n  CAR.AUDI_Q2_MK1: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906027JT\\xf1\\x894145',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300041F \\xf1\\x891006',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655BD\\xf1\\x890336\\xf1\\x82\\x1311111111111100311211011231129321312111',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x873Q0909144K \\xf1\\x895072\\xf1\\x82\\x0571F60511A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x872Q0907572M \\xf1\\x890233',\n    ],\n  },\n  CAR.SEAT_ATECA_MK1: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906027KA\\xf1\\x893749',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870D9300014S \\xf1\\x895202',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x873Q0959655BH\\xf1\\x890703\\xf1\\x82\\0161212001211001305121211052900',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x873Q0909144L \\xf1\\x895081\\xf1\\x82\\00571N60511A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x872Q0907572M \\xf1\\x890233',\n    ],\n  },\n  CAR.SEAT_LEON_MK3: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704L906021EL\\xf1\\x897542',\n      b'\\xf1\\x8704L906026BP\\xf1\\x891198',\n      b'\\xf1\\x8704L906026BP\\xf1\\x897608',\n      b'\\xf1\\x8705E906018AS\\xf1\\x899596',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300050J \\xf1\\x891908',\n      b'\\xf1\\x870D9300042M \\xf1\\x895016',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x873Q0959655AC\\xf1\\x890189\\xf1\\x82\\r11110011110011021511110200',\n      b'\\xf1\\x873Q0959655AS\\xf1\\x890200\\xf1\\x82\\r12110012120012021612110200',\n      b'\\xf1\\x873Q0959655CM\\xf1\\x890720\\xf1\\x82\\0161312001313001305171311052900',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909144AB\\xf1\\x891082\\xf1\\x82\\00521N01342A1',\n      b'\\xf1\\x875Q0909144P \\xf1\\x891043\\xf1\\x82\\00511N01805A0',\n      b'\\xf1\\x875Q0909144T \\xf1\\x891072\\xf1\\x82\\00521N05808A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x875Q0907572B \\xf1\\x890200\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572H \\xf1\\x890620',\n      b'\\xf1\\x875Q0907572P \\xf1\\x890682',\n    ],\n  },\n  CAR.SKODA_KODIAQ_MK1: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906027DD\\xf1\\x893123',\n      b'\\xf1\\x8704L906026DE\\xf1\\x895418',\n      b'\\xf1\\x875NA907115E \\xf1\\x890003',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870D9300043  \\xf1\\x895202',\n      b'\\xf1\\x870DL300012M \\xf1\\x892107',\n      b'\\xf1\\x870DL300012N \\xf1\\x892110',\n      b'\\xf1\\x870DL300013G \\xf1\\x892119',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x873Q0959655BJ\\xf1\\x890703\\xf1\\x82\\0161213001211001205212111052100',\n      b'\\xf1\\x873Q0959655CN\\xf1\\x890720\\xf1\\x82\\0161213001211001205212112052100',\n      b'\\xf1\\x873Q0959655CQ\\xf1\\x890720\\xf1\\x82\\x0e1213111211001205212112052111',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909143P \\xf1\\x892051\\xf1\\x820527T6050405',\n      b'\\xf1\\x875Q0909143P \\xf1\\x892051\\xf1\\x820527T6060405',\n      b'\\xf1\\x875Q0910143C \\xf1\\x892211\\xf1\\x82\\x0567T600G600',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x872Q0907572Q \\xf1\\x890342',\n      b'\\xf1\\x872Q0907572R \\xf1\\x890372',\n    ],\n  },\n  CAR.SKODA_OCTAVIA_MK3: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704E906016ER\\xf1\\x895823',\n      b'\\xf1\\x8704E906027HD\\xf1\\x893742',\n      b'\\xf1\\x8704L906021DT\\xf1\\x898127',\n      b'\\xf1\\x8704L906026BS\\xf1\\x891541',\n      b'\\xf1\\x875G0906259C \\xf1\\x890002',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300041N \\xf1\\x891605',\n      b'\\xf1\\x870CW300043B \\xf1\\x891601',\n      b'\\xf1\\x870D9300041C \\xf1\\x894936',\n      b'\\xf1\\x870D9300041J \\xf1\\x894902',\n      b'\\xf1\\x870D9300041P \\xf1\\x894507',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x873Q0959655AC\\xf1\\x890200\\xf1\\x82\\r11120011100010022212110200',\n      b'\\xf1\\x873Q0959655AQ\\xf1\\x890200\\xf1\\x82\\r11120011100010312212113100',\n      b'\\xf1\\x873Q0959655AS\\xf1\\x890200\\xf1\\x82\\r11120011100010022212110200',\n      b'\\xf1\\x873Q0959655BH\\xf1\\x890703\\xf1\\x82\\0163221003221002105755331052100',\n      b'\\xf1\\x873Q0959655CN\\xf1\\x890720\\xf1\\x82\\x0e3221003221002105755331052100',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x873Q0909144J \\xf1\\x895063\\xf1\\x82\\00566A01513A1',\n      b'\\xf1\\x875Q0909144AA\\xf1\\x891081\\xf1\\x82\\00521T00403A1',\n      b'\\xf1\\x875Q0909144AB\\xf1\\x891082\\xf1\\x82\\x0521T00403A1',\n      b'\\xf1\\x875Q0909144R \\xf1\\x891061\\xf1\\x82\\x0516A00604A1',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x875Q0907572D \\xf1\\x890304\\xf1\\x82\\x0101',\n      b'\\xf1\\x875Q0907572F \\xf1\\x890400\\xf1\\x82\\00101',\n      b'\\xf1\\x875Q0907572J \\xf1\\x890654',\n      b'\\xf1\\x875Q0907572P \\xf1\\x890682',\n    ],\n  },\n  CAR.SKODA_SCALA_MK1: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704C906025AK\\xf1\\x897053',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300050  \\xf1\\x891709',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x872Q0959655AM\\xf1\\x890351\\xf1\\x82\\022111104111104112104040404111111112H14',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x872Q1909144M \\xf1\\x896041',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x872Q0907572R \\xf1\\x890372',\n    ],\n  },\n  CAR.SKODA_SUPERB_MK3: {\n    (Ecu.engine, 0x7e0, None): [\n      b'\\xf1\\x8704L906026FP\\xf1\\x891196',\n      b'\\xf1\\x8704L906026KB\\xf1\\x894071',\n      b'\\xf1\\x873G0906259B \\xf1\\x890002',\n      b'\\xf1\\x873G0906264A \\xf1\\x890002',\n    ],\n    (Ecu.transmission, 0x7e1, None): [\n      b'\\xf1\\x870CW300042H \\xf1\\x891601',\n      b'\\xf1\\x870D9300011T \\xf1\\x894801',\n      b'\\xf1\\x870D9300012  \\xf1\\x894940',\n    ],\n    (Ecu.srs, 0x715, None): [\n      b'\\xf1\\x875Q0959655AE\\xf1\\x890130\\xf1\\x82\\022111200111121001121118112231292221111',\n      b'\\xf1\\x875Q0959655AK\\xf1\\x890130\\xf1\\x82\\022111200111121001121110012211292221111',\n      b'\\xf1\\x875Q0959655BH\\xf1\\x890336\\xf1\\x82\\02331310031313100313131013141319331413100',\n    ],\n    (Ecu.eps, 0x712, None): [\n      b'\\xf1\\x875Q0909143K \\xf1\\x892033\\xf1\\x820514UZ070203',\n      b'\\xf1\\x875Q0909143M \\xf1\\x892041\\xf1\\x820522UZ070303',\n      b'\\xf1\\x875Q0910143B \\xf1\\x892201\\xf1\\x82\\00563UZ060700',\n      b'\\xf1\\x875Q0910143B \\xf1\\x892201\\xf1\\x82\\x0563UZ060600',\n    ],\n    (Ecu.fwdRadar, 0x757, None): [\n      b'\\xf1\\x873Q0907572B \\xf1\\x890192',\n      b'\\xf1\\x873Q0907572B \\xf1\\x890194',\n      b'\\xf1\\x873Q0907572C \\xf1\\x890195',\n    ],\n  },\n}\n"
  },
  {
    "path": "selfdrive/car/volkswagen/volkswagencan.py",
    "content": "# CAN controls for MQB platform Volkswagen, Audi, Skoda and SEAT.\n# PQ35/PQ46/NMS, and any future MLB, to come later.\n\ndef create_mqb_steering_control(packer, bus, apply_steer, idx, lkas_enabled):\n  values = {\n    \"SET_ME_0X3\": 0x3,\n    \"Assist_Torque\": abs(apply_steer),\n    \"Assist_Requested\": lkas_enabled,\n    \"Assist_VZ\": 1 if apply_steer < 0 else 0,\n    \"HCA_Available\": 1,\n    \"HCA_Standby\": not lkas_enabled,\n    \"HCA_Active\": lkas_enabled,\n    \"SET_ME_0XFE\": 0xFE,\n    \"SET_ME_0X07\": 0x07,\n  }\n  return packer.make_can_msg(\"HCA_01\", bus, values, idx)\n\ndef create_mqb_hud_control(packer, bus, enabled, steering_pressed, hud_alert, left_lane_visible, right_lane_visible,\n                           ldw_lane_warning_left, ldw_lane_warning_right, ldw_side_dlc_tlc, ldw_dlc, ldw_tlc,\n                           standstill, left_lane_depart, right_lane_depart):\n  # Lane color reference:\n  # 0 (LKAS disabled) - off \n  # 1 (LKAS enabled, no lane detected) - dark gray \n  # 2 (LKAS enabled, lane detected) - light gray on VW, green or white on Audi depending on year or virtual cockpit.  On a color MFD on a 2015 A3 TDI it is white, virtual cockpit on a 2018 A3 e-Tron its green. \n  # 3 (LKAS enabled, lane departure detected) - white on VW, red on Audi \n\n  values = {\n    \"LDW_Status_LED_gelb\": 1 if enabled and steering_pressed else 0,\n    \"LDW_Status_LED_gruen\": 1 if enabled and not steering_pressed else 0,\n    \"LDW_Lernmodus_links\": 3 if enabled and left_lane_visible else 1 + left_lane_visible,\n    \"LDW_Lernmodus_rechts\": 3 if enabled and right_lane_visible else 1 + right_lane_visible,\n    \"LDW_Texte\": hud_alert,\n    \"LDW_SW_Warnung_links\": ldw_lane_warning_left,\n    \"LDW_SW_Warnung_rechts\": ldw_lane_warning_right,\n    \"LDW_Seite_DLCTLC\": ldw_side_dlc_tlc,\n    \"LDW_DLC\": ldw_dlc,\n    \"LDW_TLC\": ldw_tlc\n  }\n  return packer.make_can_msg(\"LDW_02\", bus, values)\n\ndef create_mqb_acc_buttons_control(packer, bus, buttonStatesToSend, CS, idx):\n  values = {\n    \"GRA_Hauptschalter\": CS.graHauptschalter,\n    \"GRA_Abbrechen\": buttonStatesToSend[\"cancel\"],\n    \"GRA_Tip_Setzen\": buttonStatesToSend[\"setCruise\"],\n    \"GRA_Tip_Hoch\": buttonStatesToSend[\"accelCruise\"],\n    \"GRA_Tip_Runter\": buttonStatesToSend[\"decelCruise\"],\n    \"GRA_Tip_Wiederaufnahme\": buttonStatesToSend[\"resumeCruise\"],\n    \"GRA_Verstellung_Zeitluecke\": 3 if buttonStatesToSend[\"gapAdjustCruise\"] else 0,\n    \"GRA_Typ_Hauptschalter\": CS.graTypHauptschalter,\n    \"GRA_Codierung\": 2,\n    \"GRA_Tip_Stufe_2\": CS.graTipStufe2,\n    \"GRA_ButtonTypeInfo\": CS.graButtonTypeInfo\n  }\n  return packer.make_can_msg(\"GRA_ACC_01\", bus, values, idx)\n"
  },
  {
    "path": "selfdrive/common/SConscript",
    "content": "Import('env', 'arch', 'SHARED')\n\nif SHARED:\n  fxn = env.SharedLibrary\nelse:\n  fxn = env.Library\n\ncommon_libs = [\n  'params.cc',\n  'swaglog.cc',\n  'util.cc',\n  'gpio.cc',\n  'i2c.cc',\n  'watchdog.cc',\n]\n\n_common = fxn('common', common_libs, LIBS=\"json11\")\n\nfiles = [\n  'clutil.cc',\n  'glutil.cc',\n  'visionimg.cc',\n]\n\nif arch == \"aarch64\":\n  files += [\n    'framebuffer.cc',\n    'touch.c',\n  ]\n  _gpu_libs = ['gui', 'adreno_utils']\nelif arch == \"larch64\" or arch == \"jarch64\":\n  _gpu_libs = [\"GLESv2\"]\nelse:\n  _gpu_libs = [\"GL\"]\n\n_gpucommon = fxn('gpucommon', files, LIBS=_gpu_libs)\nExport('_common', '_gpucommon', '_gpu_libs')\n\nif GetOption('test'):\n  env.Program('tests/test_util', ['tests/test_util.cc'], LIBS=[_common])\n"
  },
  {
    "path": "selfdrive/common/clutil.cc",
    "content": "#include \"selfdrive/common/clutil.h\"\n\n#include <sys/stat.h>\n\n#include <cassert>\n#include <cstring>\n#include <iostream>\n#include <memory>\n#include <vector>\n\n#include \"selfdrive/common/util.h\"\n\nnamespace {  // helper functions\n\ntemplate <typename Func, typename Id, typename Name>\nstd::string get_info(Func get_info_func, Id id, Name param_name) {\n  size_t size = 0;\n  CL_CHECK(get_info_func(id, param_name, 0, NULL, &size));\n  std::string info(size, '\\0');\n  CL_CHECK(get_info_func(id, param_name, size, info.data(), NULL));\n  return info;\n}\ninline std::string get_platform_info(cl_platform_id id, cl_platform_info name) { return get_info(&clGetPlatformInfo, id, name); }\ninline std::string get_device_info(cl_device_id id, cl_device_info name) { return get_info(&clGetDeviceInfo, id, name); }\n\nvoid cl_print_info(cl_platform_id platform, cl_device_id device) {\n  size_t work_group_size = 0;\n  cl_device_type device_type = 0;\n  clGetDeviceInfo(device, CL_DEVICE_MAX_WORK_GROUP_SIZE, sizeof(work_group_size), &work_group_size, NULL);\n  clGetDeviceInfo(device, CL_DEVICE_TYPE, sizeof(device_type), &device_type, NULL);\n  const char *type_str = \"Other...\";\n  switch (device_type) {\n    case CL_DEVICE_TYPE_CPU: type_str =\"CL_DEVICE_TYPE_CPU\"; break;\n    case CL_DEVICE_TYPE_GPU: type_str = \"CL_DEVICE_TYPE_GPU\"; break;\n    case CL_DEVICE_TYPE_ACCELERATOR: type_str = \"CL_DEVICE_TYPE_ACCELERATOR\"; break;\n  }\n\n  std::cout << \"vendor: \" << get_platform_info(platform, CL_PLATFORM_VENDOR) << std::endl\n            << \"platform version: \" << get_platform_info(platform, CL_PLATFORM_VERSION) << std::endl\n            << \"profile: \" << get_platform_info(platform, CL_PLATFORM_PROFILE) << std::endl\n            << \"extensions: \" << get_platform_info(platform, CL_PLATFORM_EXTENSIONS) << std::endl\n            << \"name :\" << get_device_info(device, CL_DEVICE_NAME) << std::endl\n            << \"device version :\" << get_device_info(device, CL_DEVICE_VERSION) << std::endl\n            << \"max work group size :\" << work_group_size << std::endl\n            << \"type = \" << device_type << \" = \" << type_str << std::endl;\n}\n\nvoid cl_print_build_errors(cl_program program, cl_device_id device) {\n  cl_build_status status;\n  clGetProgramBuildInfo(program, device, CL_PROGRAM_BUILD_STATUS, sizeof(status), &status, NULL);\n  size_t log_size;\n  clGetProgramBuildInfo(program, device, CL_PROGRAM_BUILD_LOG, 0, NULL, &log_size);\n  std::string log(log_size, '\\0');\n  clGetProgramBuildInfo(program, device, CL_PROGRAM_BUILD_LOG, log_size, &log[0], NULL);\n\n  std::cout << \"build failed; status=\" << status << \", log:\" << std::endl << log << std::endl; \n}\n\n}  // namespace\n\ncl_device_id cl_get_device_id(cl_device_type device_type) {\n  cl_uint num_platforms = 0;\n  CL_CHECK(clGetPlatformIDs(0, NULL, &num_platforms));\n  std::unique_ptr<cl_platform_id[]> platform_ids = std::make_unique<cl_platform_id[]>(num_platforms);\n  CL_CHECK(clGetPlatformIDs(num_platforms, &platform_ids[0], NULL));\n\n  for (size_t i = 0; i < num_platforms; ++i) {\n    std::cout << \"platform[\" << i << \"] CL_PLATFORM_NAME: \" << get_platform_info(platform_ids[i], CL_PLATFORM_NAME) << std::endl;\n    // Get first device\n    if (cl_device_id device_id = NULL; clGetDeviceIDs(platform_ids[i], device_type, 1, &device_id, NULL) == 0 && device_id) {\n      cl_print_info(platform_ids[i], device_id);\n      return device_id;\n    }\n  }\n  std::cout << \"No valid openCL platform found\" << std::endl;\n  assert(0);\n  return nullptr;\n}\n\ncl_program cl_program_from_file(cl_context ctx, cl_device_id device_id, const char* path, const char* args) {\n  std::string src = util::read_file(path);\n  assert(src.length() > 0);\n  cl_program prg = CL_CHECK_ERR(clCreateProgramWithSource(ctx, 1, (const char*[]){src.c_str()}, NULL, &err));\n  if (int err = clBuildProgram(prg, 1, &device_id, args, NULL, NULL); err != 0) {\n    cl_print_build_errors(prg, device_id);\n    assert(0);\n  }\n  return prg;\n}\n\n// Given a cl code and return a string representation\n#define CL_ERR_TO_STR(err) case err: return #err\nconst char* cl_get_error_string(int err) {\n  switch (err) {\n    CL_ERR_TO_STR(CL_SUCCESS);\n    CL_ERR_TO_STR(CL_DEVICE_NOT_FOUND);\n    CL_ERR_TO_STR(CL_DEVICE_NOT_AVAILABLE);\n    CL_ERR_TO_STR(CL_COMPILER_NOT_AVAILABLE);\n    CL_ERR_TO_STR(CL_MEM_OBJECT_ALLOCATION_FAILURE);\n    CL_ERR_TO_STR(CL_OUT_OF_RESOURCES);\n    CL_ERR_TO_STR(CL_OUT_OF_HOST_MEMORY);\n    CL_ERR_TO_STR(CL_PROFILING_INFO_NOT_AVAILABLE);\n    CL_ERR_TO_STR(CL_MEM_COPY_OVERLAP);\n    CL_ERR_TO_STR(CL_IMAGE_FORMAT_MISMATCH);\n    CL_ERR_TO_STR(CL_IMAGE_FORMAT_NOT_SUPPORTED);\n    CL_ERR_TO_STR(CL_MAP_FAILURE);\n    CL_ERR_TO_STR(CL_MISALIGNED_SUB_BUFFER_OFFSET);\n    CL_ERR_TO_STR(CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST);\n    CL_ERR_TO_STR(CL_COMPILE_PROGRAM_FAILURE);\n    CL_ERR_TO_STR(CL_LINKER_NOT_AVAILABLE);\n    CL_ERR_TO_STR(CL_LINK_PROGRAM_FAILURE);\n    CL_ERR_TO_STR(CL_DEVICE_PARTITION_FAILED);\n    CL_ERR_TO_STR(CL_KERNEL_ARG_INFO_NOT_AVAILABLE);\n    CL_ERR_TO_STR(CL_INVALID_VALUE);\n    CL_ERR_TO_STR(CL_INVALID_DEVICE_TYPE);\n    CL_ERR_TO_STR(CL_INVALID_PLATFORM);\n    CL_ERR_TO_STR(CL_INVALID_DEVICE);\n    CL_ERR_TO_STR(CL_INVALID_CONTEXT);\n    CL_ERR_TO_STR(CL_INVALID_QUEUE_PROPERTIES);\n    CL_ERR_TO_STR(CL_INVALID_COMMAND_QUEUE);\n    CL_ERR_TO_STR(CL_INVALID_HOST_PTR);\n    CL_ERR_TO_STR(CL_INVALID_MEM_OBJECT);\n    CL_ERR_TO_STR(CL_INVALID_IMAGE_FORMAT_DESCRIPTOR);\n    CL_ERR_TO_STR(CL_INVALID_IMAGE_SIZE);\n    CL_ERR_TO_STR(CL_INVALID_SAMPLER);\n    CL_ERR_TO_STR(CL_INVALID_BINARY);\n    CL_ERR_TO_STR(CL_INVALID_BUILD_OPTIONS);\n    CL_ERR_TO_STR(CL_INVALID_PROGRAM);\n    CL_ERR_TO_STR(CL_INVALID_PROGRAM_EXECUTABLE);\n    CL_ERR_TO_STR(CL_INVALID_KERNEL_NAME);\n    CL_ERR_TO_STR(CL_INVALID_KERNEL_DEFINITION);\n    CL_ERR_TO_STR(CL_INVALID_KERNEL);\n    CL_ERR_TO_STR(CL_INVALID_ARG_INDEX);\n    CL_ERR_TO_STR(CL_INVALID_ARG_VALUE);\n    CL_ERR_TO_STR(CL_INVALID_ARG_SIZE);\n    CL_ERR_TO_STR(CL_INVALID_KERNEL_ARGS);\n    CL_ERR_TO_STR(CL_INVALID_WORK_DIMENSION);\n    CL_ERR_TO_STR(CL_INVALID_WORK_GROUP_SIZE);\n    CL_ERR_TO_STR(CL_INVALID_WORK_ITEM_SIZE);\n    CL_ERR_TO_STR(CL_INVALID_GLOBAL_OFFSET);\n    CL_ERR_TO_STR(CL_INVALID_EVENT_WAIT_LIST);\n    CL_ERR_TO_STR(CL_INVALID_EVENT);\n    CL_ERR_TO_STR(CL_INVALID_OPERATION);\n    CL_ERR_TO_STR(CL_INVALID_GL_OBJECT);\n    CL_ERR_TO_STR(CL_INVALID_BUFFER_SIZE);\n    CL_ERR_TO_STR(CL_INVALID_MIP_LEVEL);\n    CL_ERR_TO_STR(CL_INVALID_GLOBAL_WORK_SIZE);\n    CL_ERR_TO_STR(CL_INVALID_PROPERTY);\n    CL_ERR_TO_STR(CL_INVALID_IMAGE_DESCRIPTOR);\n    CL_ERR_TO_STR(CL_INVALID_COMPILER_OPTIONS);\n    CL_ERR_TO_STR(CL_INVALID_LINKER_OPTIONS);\n    CL_ERR_TO_STR(CL_INVALID_DEVICE_PARTITION_COUNT);\n    case -69: return \"CL_INVALID_PIPE_SIZE\";\n    case -70: return \"CL_INVALID_DEVICE_QUEUE\";\n    case -71: return \"CL_INVALID_SPEC_ID\";\n    case -72: return \"CL_MAX_SIZE_RESTRICTION_EXCEEDED\";\n    case -1002: return \"CL_INVALID_D3D10_DEVICE_KHR\";\n    case -1003: return \"CL_INVALID_D3D10_RESOURCE_KHR\";\n    case -1004: return \"CL_D3D10_RESOURCE_ALREADY_ACQUIRED_KHR\";\n    case -1005: return \"CL_D3D10_RESOURCE_NOT_ACQUIRED_KHR\";\n    case -1006: return \"CL_INVALID_D3D11_DEVICE_KHR\";\n    case -1007: return \"CL_INVALID_D3D11_RESOURCE_KHR\";\n    case -1008: return \"CL_D3D11_RESOURCE_ALREADY_ACQUIRED_KHR\";\n    case -1009: return \"CL_D3D11_RESOURCE_NOT_ACQUIRED_KHR\";\n    case -1010: return \"CL_INVALID_DX9_MEDIA_ADAPTER_KHR\";\n    case -1011: return \"CL_INVALID_DX9_MEDIA_SURFACE_KHR\";\n    case -1012: return \"CL_DX9_MEDIA_SURFACE_ALREADY_ACQUIRED_KHR\";\n    case -1013: return \"CL_DX9_MEDIA_SURFACE_NOT_ACQUIRED_KHR\";\n    case -1093: return \"CL_INVALID_EGL_OBJECT_KHR\";\n    case -1092: return \"CL_EGL_RESOURCE_NOT_ACQUIRED_KHR\";\n    case -1001: return \"CL_PLATFORM_NOT_FOUND_KHR\";\n    case -1057: return \"CL_DEVICE_PARTITION_FAILED_EXT\";\n    case -1058: return \"CL_INVALID_PARTITION_COUNT_EXT\";\n    case -1059: return \"CL_INVALID_PARTITION_NAME_EXT\";\n    case -1094: return \"CL_INVALID_ACCELERATOR_INTEL\";\n    case -1095: return \"CL_INVALID_ACCELERATOR_TYPE_INTEL\";\n    case -1096: return \"CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL\";\n    case -1097: return \"CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL\";\n    case -1000: return \"CL_INVALID_GL_SHAREGROUP_REFERENCE_KHR\";\n    case -1098: return \"CL_INVALID_VA_API_MEDIA_ADAPTER_INTEL\";\n    case -1099: return \"CL_INVALID_VA_API_MEDIA_SURFACE_INTEL\";\n    case -1100: return \"CL_VA_API_MEDIA_SURFACE_ALREADY_ACQUIRED_INTEL\";\n    case -1101: return \"CL_VA_API_MEDIA_SURFACE_NOT_ACQUIRED_INTEL\";\n    default: return \"CL_UNKNOWN_ERROR\";\n  }\n}\n"
  },
  {
    "path": "selfdrive/common/clutil.h",
    "content": "#pragma once\n\n#include <cstdint>\n#include <cstdlib>\n\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\n\n#define CL_CHECK(_expr)          \\\n  do {                           \\\n    assert(CL_SUCCESS == (_expr)); \\\n  } while (0)\n\n#define CL_CHECK_ERR(_expr)           \\\n  ({                                  \\\n    cl_int err = CL_INVALID_VALUE;    \\\n    __typeof__(_expr) _ret = _expr;   \\\n    assert(_ret&& err == CL_SUCCESS); \\\n    _ret;                             \\\n  })\n\ncl_device_id cl_get_device_id(cl_device_type device_type);\ncl_program cl_program_from_file(cl_context ctx, cl_device_id device_id, const char* path, const char* args);\nconst char* cl_get_error_string(int err);\n"
  },
  {
    "path": "selfdrive/common/framebuffer.cc",
    "content": "#include \"selfdrive/common/framebuffer.h\"\n\n#include <cstdio>\n#include <cassert>\n\n#include \"selfdrive/common/util.h\"\n\n#include <ui/DisplayInfo.h>\n\n#include <gui/ISurfaceComposer.h>\n#include <gui/Surface.h>\n#include <gui/SurfaceComposerClient.h>\n#include <GLES2/gl2.h>\n#include <EGL/eglext.h>\n\n#define BACKLIGHT_LEVEL 205\n\nusing namespace android;\n\nstruct FramebufferState {\n    sp<SurfaceComposerClient> session;\n    sp<IBinder> dtoken;\n    DisplayInfo dinfo;\n    sp<SurfaceControl> control;\n\n    sp<Surface> s;\n    EGLDisplay display;\n\n    EGLint egl_major, egl_minor;\n    EGLConfig config;\n    EGLSurface surface;\n    EGLContext context;\n};\n\nvoid FrameBuffer::swap() {\n  eglSwapBuffers(s->display, s->surface);\n  assert(glGetError() == GL_NO_ERROR);\n}\n\nbool set_brightness(int brightness) {\n  char bright[64];\n  snprintf(bright, sizeof(bright), \"%d\", brightness);\n  return 0 == util::write_file(\"/sys/class/leds/lcd-backlight/brightness\", bright, strlen(bright));\n}\n\nvoid FrameBuffer::set_power(int mode) {\n  SurfaceComposerClient::setDisplayPowerMode(s->dtoken, mode);\n}\n\nFrameBuffer::FrameBuffer(const char *name, uint32_t layer, int alpha, int *out_w, int *out_h) {\n  s = new FramebufferState;\n\n  s->session = new SurfaceComposerClient();\n  assert(s->session != NULL);\n\n  s->dtoken = SurfaceComposerClient::getBuiltInDisplay(\n                ISurfaceComposer::eDisplayIdMain);\n  assert(s->dtoken != NULL);\n\n  status_t status = SurfaceComposerClient::getDisplayInfo(s->dtoken, &s->dinfo);\n  assert(status == 0);\n\n  //int orientation = 3; // rotate framebuffer 270 degrees\n  int orientation = 1; // rotate framebuffer 90 degrees\n  if(orientation == 1 || orientation == 3) {\n      int temp = s->dinfo.h;\n      s->dinfo.h = s->dinfo.w;\n      s->dinfo.w = temp;\n  }\n\n  printf(\"dinfo %dx%d\\n\", s->dinfo.w, s->dinfo.h);\n\n  Rect destRect(s->dinfo.w, s->dinfo.h);\n  s->session->setDisplayProjection(s->dtoken, orientation, destRect, destRect);\n\n  s->control = s->session->createSurface(String8(name),\n                  s->dinfo.w, s->dinfo.h, PIXEL_FORMAT_RGBX_8888);\n  assert(s->control != NULL);\n\n  SurfaceComposerClient::openGlobalTransaction();\n  status = s->control->setLayer(layer);\n  SurfaceComposerClient::closeGlobalTransaction();\n  assert(status == 0);\n\n  s->s = s->control->getSurface();\n  assert(s->s != NULL);\n\n  // init opengl and egl\n  const EGLint attribs[] = {\n    EGL_RED_SIZE,     8,\n    EGL_GREEN_SIZE,   8,\n    EGL_BLUE_SIZE,    8,\n    EGL_ALPHA_SIZE,   alpha ? 8 : 0,\n    EGL_DEPTH_SIZE,   0,\n    EGL_STENCIL_SIZE, 8,\n    EGL_RENDERABLE_TYPE, EGL_OPENGL_ES3_BIT_KHR,\n    // enable MSAA\n    EGL_SAMPLE_BUFFERS, 1,\n    EGL_SAMPLES, 4,\n    EGL_NONE,\n  };\n\n  s->display = eglGetDisplay(EGL_DEFAULT_DISPLAY);\n  assert(s->display != EGL_NO_DISPLAY);\n\n  int success = eglInitialize(s->display, &s->egl_major, &s->egl_minor);\n  assert(success);\n\n  printf(\"egl version %d.%d\\n\", s->egl_major, s->egl_minor);\n\n  EGLint num_configs;\n  success = eglChooseConfig(s->display, attribs, &s->config, 1, &num_configs);\n  assert(success);\n\n  s->surface = eglCreateWindowSurface(s->display, s->config, s->s.get(), NULL);\n  assert(s->surface != EGL_NO_SURFACE);\n\n  const EGLint context_attribs[] = {\n    EGL_CONTEXT_CLIENT_VERSION, 3,\n    EGL_NONE,\n  };\n  s->context = eglCreateContext(s->display, s->config, NULL, context_attribs);\n  assert(s->context != EGL_NO_CONTEXT);\n\n  EGLint w, h;\n  eglQuerySurface(s->display, s->surface, EGL_WIDTH, &w);\n  eglQuerySurface(s->display, s->surface, EGL_HEIGHT, &h);\n  printf(\"egl w %d h %d\\n\", w, h);\n\n  success = eglMakeCurrent(s->display, s->surface, s->surface, s->context);\n  assert(success);\n\n  printf(\"gl version %s\\n\", glGetString(GL_VERSION));\n\n  set_brightness(BACKLIGHT_LEVEL);\n\n  if (out_w) *out_w = w;\n  if (out_h) *out_h = h;\n}\n\nFrameBuffer::~FrameBuffer() {\n  eglDestroyContext(s->display, s->context);\n  eglDestroySurface(s->display, s->surface);\n  eglTerminate(s->display);\n  delete s;\n}\n"
  },
  {
    "path": "selfdrive/common/framebuffer.h",
    "content": "#pragma once\n\n#include <cstdlib>\n\n#include \"hardware/hwcomposer_defs.h\"\n\nbool set_brightness(int brightness);\n\nstruct FramebufferState;\nclass FrameBuffer {\n public:\n  FrameBuffer(const char *name, uint32_t layer, int alpha, int *out_w, int *out_h);\n  ~FrameBuffer();\n  void set_power(int mode);\n  void swap();\nprivate:\n  FramebufferState *s;\n};\n"
  },
  {
    "path": "selfdrive/common/glutil.cc",
    "content": "#include \"selfdrive/common/glutil.h\"\n\n#include <cassert>\n#include <cstdio>\n#include <cstdlib>\n#include <string>\n\nstatic GLuint load_shader(GLenum shaderType, const char *src) {\n  GLint status = 0, len = 0;\n  GLuint shader = glCreateShader(shaderType);\n  assert(shader != 0);\n\n  glShaderSource(shader, 1, &src, NULL);\n  glCompileShader(shader);\n  glGetShaderiv(shader, GL_COMPILE_STATUS, &status);\n  if (!status) {\n    glGetShaderiv(shader, GL_INFO_LOG_LENGTH, &len);\n    if (len) {\n      std::string msg(len, '\\0');\n      glGetShaderInfoLog(shader, len, NULL, msg.data());\n      fprintf(stderr, \"error compiling shader:\\n%s\\n\", msg.c_str());\n    }\n    assert(0);\n  }\n  return shader;\n}\n\nGLShader::GLShader(const char *vert_src, const char *frag_src) {\n  GLint status = 0, len = 0;\n  prog = glCreateProgram();\n  assert(prog != 0);\n\n  vert = load_shader(GL_VERTEX_SHADER, vert_src);\n  frag = load_shader(GL_FRAGMENT_SHADER, frag_src);\n  glAttachShader(prog, vert);\n  glAttachShader(prog, frag);\n  glLinkProgram(prog);\n\n  glGetProgramiv(prog, GL_LINK_STATUS, &status);\n  if (!status) {\n    glGetProgramiv(prog, GL_INFO_LOG_LENGTH, &len);\n    if (len) {\n      std::string msg(len, '\\0');\n      glGetProgramInfoLog(prog, len, NULL, msg.data());\n      fprintf(stderr, \"error linking program:\\n%s\\n\", msg.c_str());\n    }\n    assert(0);\n  }\n}\n\nGLShader::~GLShader() {\n  glDeleteProgram(prog);\n  glDeleteShader(frag);\n  glDeleteShader(vert);\n}\n\nGLuint GLShader::getUniformLocation(const char *name) {\n  auto it = uniform_loc_map.find(name);\n  if (it == uniform_loc_map.end()) {\n    it = uniform_loc_map.insert(it, {name, glGetUniformLocation(prog, name)});\n  }\n  return it->second;\n}\n"
  },
  {
    "path": "selfdrive/common/glutil.h",
    "content": "#pragma once\n\n#include <map>\n\n#ifdef __APPLE__\n#include <OpenGL/gl3.h>\n#else\n#include <GLES3/gl3.h>\n#endif\n\nclass GLShader {\npublic:\n  GLShader(const char *vert_src, const char *frag_src);\n  ~GLShader();\n  GLuint getUniformLocation(const char * name);\n  GLuint prog = 0;\n\nprivate:\n  GLuint vert = 0, frag = 0;\n  std::map<const char*, GLint> uniform_loc_map;\n};\n"
  },
  {
    "path": "selfdrive/common/gpio.cc",
    "content": "#include \"selfdrive/common/gpio.h\"\n\n#include <fcntl.h>\n#include <unistd.h>\n\n#include <cstring>\n\n#include \"selfdrive/common/util.h\"\n\n// We assume that all pins have already been exported on boot,\n// and that we have permission to write to them.\n\nint gpio_init(int pin_nr, bool output) {\n  char pin_dir_path[50];\n  int pin_dir_path_len = snprintf(pin_dir_path, sizeof(pin_dir_path),\n                           \"/sys/class/gpio/gpio%d/direction\", pin_nr);\n  if(pin_dir_path_len <= 0) {\n    return -1;\n  }\n  const char *value = output ? \"out\" : \"in\";\n  return util::write_file(pin_dir_path, (void*)value, strlen(value));\n}\n\nint gpio_set(int pin_nr, bool high) {\n  char pin_val_path[50];\n  int pin_val_path_len = snprintf(pin_val_path, sizeof(pin_val_path),\n                           \"/sys/class/gpio/gpio%d/value\", pin_nr);\n  if(pin_val_path_len <= 0) {\n    return -1;\n  }\n  return util::write_file(pin_val_path, (void*)(high ? \"1\" : \"0\"), 1);\n}\n"
  },
  {
    "path": "selfdrive/common/gpio.h",
    "content": "#pragma once\n\n// Pin definitions\n#ifdef QCOM2\n  #define GPIO_HUB_RST_N        30\n  #define GPIO_UBLOX_RST_N      32\n  #define GPIO_UBLOX_SAFEBOOT_N 33\n  #define GPIO_UBLOX_PWR_EN     34\n  #define GPIO_STM_RST_N        124\n  #define GPIO_STM_BOOT0        134\n#else\n  #define GPIO_HUB_RST_N        0\n  #define GPIO_UBLOX_RST_N      0\n  #define GPIO_UBLOX_SAFEBOOT_N 0\n  #define GPIO_UBLOX_PWR_EN     0\n  #define GPIO_STM_RST_N        0\n  #define GPIO_STM_BOOT0        0\n#endif\n\nint gpio_init(int pin_nr, bool output);\nint gpio_set(int pin_nr, bool high);\n"
  },
  {
    "path": "selfdrive/common/i2c.cc",
    "content": "#include \"selfdrive/common/i2c.h\"\n\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cstdio>\n#include <stdexcept>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n\n#define UNUSED(x) (void)(x)\n\n#ifdef QCOM2\n// TODO: decide if we want to isntall libi2c-dev everywhere\nextern \"C\" {\n  #include <linux/i2c-dev.h>\n  #include <i2c/smbus.h>\n}\n\nI2CBus::I2CBus(uint8_t bus_id) {\n  char bus_name[20];\n  snprintf(bus_name, 20, \"/dev/i2c-%d\", bus_id);\n\n  i2c_fd = HANDLE_EINTR(open(bus_name, O_RDWR));\n  if(i2c_fd < 0) {\n    throw std::runtime_error(\"Failed to open I2C bus\");\n  }\n}\n\nI2CBus::~I2CBus() {\n  if(i2c_fd >= 0) { close(i2c_fd); }\n}\n\nint I2CBus::read_register(uint8_t device_address, uint register_address, uint8_t *buffer, uint8_t len) {\n  int ret = 0;\n\n  ret = HANDLE_EINTR(ioctl(i2c_fd, I2C_SLAVE, device_address));\n  if(ret < 0) { goto fail; }\n\n  ret = i2c_smbus_read_i2c_block_data(i2c_fd, register_address, len, buffer);\n  if((ret < 0) || (ret != len)) { goto fail; }\n\nfail:\n  return ret;\n}\n\nint I2CBus::set_register(uint8_t device_address, uint register_address, uint8_t data) {\n  int ret = 0;\n\n  ret = HANDLE_EINTR(ioctl(i2c_fd, I2C_SLAVE, device_address));\n  if(ret < 0) { goto fail; }\n\n  ret = i2c_smbus_write_byte_data(i2c_fd, register_address, data);\n  if(ret < 0) { goto fail; }\n\nfail:\n  return ret;\n}\n\n#else\n\nI2CBus::I2CBus(uint8_t bus_id) {\n  UNUSED(bus_id);\n  i2c_fd = -1;\n}\n\nI2CBus::~I2CBus() {}\n\nint I2CBus::read_register(uint8_t device_address, uint register_address, uint8_t *buffer, uint8_t len) {\n  UNUSED(device_address);\n  UNUSED(register_address);\n  UNUSED(buffer);\n  UNUSED(len);\n  return -1;\n}\n\nint I2CBus::set_register(uint8_t device_address, uint register_address, uint8_t data) {\n  UNUSED(device_address);\n  UNUSED(register_address);\n  UNUSED(data);\n  return -1;\n}\n#endif\n"
  },
  {
    "path": "selfdrive/common/i2c.h",
    "content": "#pragma once\n\n#include <cstdint>\n\n#include <sys/types.h>\n\nclass I2CBus {\n  private:\n    int i2c_fd;\n\n  public:\n    I2CBus(uint8_t bus_id);\n    ~I2CBus();\n\n    int read_register(uint8_t device_address, uint register_address, uint8_t *buffer, uint8_t len);\n    int set_register(uint8_t device_address, uint register_address, uint8_t data);\n};\n"
  },
  {
    "path": "selfdrive/common/mat.h",
    "content": "#pragma once\n\ntypedef struct vec3 {\n\tfloat v[3];\n} vec3;\n\ntypedef struct vec4 {\n  float v[4];\n} vec4;\n\ntypedef struct mat3 {\n\tfloat v[3*3];\n} mat3;\n\ntypedef struct mat4 {\n  float v[4*4];\n} mat4;\n\nstatic inline mat3 matmul3(const mat3 &a, const mat3 &b) {\n  mat3 ret = {{0.0}};\n  for (int r=0; r<3; r++) {\n    for (int c=0; c<3; c++) {\n      float v = 0.0;\n      for (int k=0; k<3; k++) {\n        v += a.v[r*3+k] * b.v[k*3+c];\n      }\n      ret.v[r*3+c] = v;\n    }\n  }\n  return ret;\n}\n\nstatic inline vec3 matvecmul3(const mat3 &a, const vec3 &b) {\n  vec3 ret = {{0.0}};\n  for (int r=0; r<3; r++) {\n    for (int c=0; c<3; c++) {\n      ret.v[r] += a.v[r*3+c] * b.v[c];\n    }\n  }\n  return ret;\n}\n\nstatic inline mat4 matmul(const mat4 &a, const mat4 &b) {\n  mat4 ret = {{0.0}};\n  for (int r=0; r<4; r++) {\n    for (int c=0; c<4; c++) {\n      float v = 0.0;\n      for (int k=0; k<4; k++) {\n        v += a.v[r*4+k] * b.v[k*4+c];\n      }\n      ret.v[r*4+c] = v;\n    }\n  }\n  return ret;\n}\n\nstatic inline vec4 matvecmul(const mat4 &a, const vec4 &b) {\n  vec4 ret = {{0.0}};\n  for (int r=0; r<4; r++) {\n    for (int c=0; c<4; c++) {\n      ret.v[r] += a.v[r*4+c] * b.v[c];\n    }\n  }\n  return ret;\n}\n\n// scales the input and output space of a transformation matrix\n// that assumes pixel-center origin.\nstatic inline mat3 transform_scale_buffer(const mat3 &in, float s) {\n  // in_pt = ( transform(out_pt/s + 0.5) - 0.5) * s\n\n  mat3 transform_out = {{\n    1.0f/s, 0.0f, 0.5f,\n    0.0f, 1.0f/s, 0.5f,\n    0.0f, 0.0f, 1.0f,\n  }};\n\n  mat3 transform_in = {{\n    s,  0.0f, -0.5f*s,\n    0.0f, s, -0.5f*s,\n    0.0f, 0.0f, 1.0f,\n  }};\n\n  return matmul3(transform_in, matmul3(in, transform_out));\n}\n"
  },
  {
    "path": "selfdrive/common/modeldata.h",
    "content": "#pragma once\nconst int  TRAJECTORY_SIZE = 33;\nconst int LAT_MPC_N = 16;\nconst int LON_MPC_N = 32;\nconst float MIN_DRAW_DISTANCE = 10.0;\nconst float MAX_DRAW_DISTANCE = 100.0;\n\nconst double T_IDXS[TRAJECTORY_SIZE] = {\n        0.        ,  0.00976562,  0.0390625 ,  0.08789062,  0.15625   ,\n        0.24414062,  0.3515625 ,  0.47851562,  0.625     ,  0.79101562,\n        0.9765625 ,  1.18164062,  1.40625   ,  1.65039062,  1.9140625 ,\n        2.19726562,  2.5       ,  2.82226562,  3.1640625 ,  3.52539062,\n        3.90625   ,  4.30664062,  4.7265625 ,  5.16601562,  5.625     ,\n        6.10351562,  6.6015625 ,  7.11914062,  7.65625   ,  8.21289062,\n        8.7890625 ,  9.38476562, 10.};\nconst double X_IDXS[TRAJECTORY_SIZE] = {\n         0.    ,   0.1875,   0.75  ,   1.6875,   3.    ,   4.6875,\n         6.75  ,   9.1875,  12.    ,  15.1875,  18.75  ,  22.6875,\n        27.    ,  31.6875,  36.75  ,  42.1875,  48.    ,  54.1875,\n        60.75  ,  67.6875,  75.    ,  82.6875,  90.75  ,  99.1875,\n       108.    , 117.1875, 126.75  , 136.6875, 147.    , 157.6875,\n       168.75  , 180.1875, 192.};\n\n#ifdef __cplusplus\n\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/hardware/hw.h\"\nconst mat3 fcam_intrinsic_matrix =\n    Hardware::TICI() ? (mat3){{2648.0, 0.0, 1928.0 / 2,\n                               0.0, 2648.0, 1208.0 / 2,\n                               0.0, 0.0, 1.0}}\n                     : (mat3){{910., 0., 1164.0 / 2,\n                               0., 910., 874.0 / 2,\n                               0., 0., 1.}};\n\n// without unwarp, focal length is for center portion only\nconst mat3 ecam_intrinsic_matrix = (mat3){{620.0, 0.0, 1928.0 / 2,\n                                           0.0, 620.0, 1208.0 / 2,\n                                           0.0, 0.0, 1.0}};\n\nstatic inline mat3 get_model_yuv_transform(bool bayer = true) {\n  float db_s = Hardware::TICI() ? 1.0 : 0.5; // debayering does a 2x downscale on EON\n  const mat3 transform = (mat3){{\n    1.0, 0.0, 0.0,\n    0.0, 1.0, 0.0,\n    0.0, 0.0, 1.0\n  }};\n  return bayer ? transform_scale_buffer(transform, db_s) : transform;\n}\n\n#endif\n"
  },
  {
    "path": "selfdrive/common/params.cc",
    "content": "#include \"selfdrive/common/params.h\"\n\n#ifndef _GNU_SOURCE\n#define _GNU_SOURCE\n#endif  // _GNU_SOURCE\n\n#include <dirent.h>\n#include <sys/file.h>\n#include <sys/stat.h>\n#include <unistd.h>\n\n#include <csignal>\n#include <cstdio>\n#include <cstdlib>\n#include <cstring>\n#include <mutex>\n#include <unordered_map>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n\nnamespace {\n\nvolatile sig_atomic_t params_do_exit = 0;\nvoid params_sig_handler(int signal) {\n  params_do_exit = 1;\n}\n\nint fsync_dir(const char* path) {\n  int fd = HANDLE_EINTR(open(path, O_RDONLY, 0755));\n  if (fd < 0) {\n    return -1;\n  }\n\n  int result = fsync(fd);\n  int result_close = close(fd);\n  if (result_close < 0) {\n    result = result_close;\n  }\n  return result;\n}\n\nint mkdir_p(std::string path) {\n  char * _path = (char *)path.c_str();\n\n  for (char *p = _path + 1; *p; p++) {\n    if (*p == '/') {\n      *p = '\\0'; // Temporarily truncate\n      if (mkdir(_path, 0777) != 0) {\n        if (errno != EEXIST) return -1;\n      }\n      *p = '/';\n    }\n  }\n  if (mkdir(_path, 0777) != 0) {\n    if (errno != EEXIST) return -1;\n  }\n  return 0;\n}\n\nbool create_params_path(const std::string &param_path, const std::string &key_path) {\n  // Make sure params path exists\n  if (!util::file_exists(param_path) && mkdir_p(param_path) != 0) {\n    return false;\n  }\n\n  // See if the symlink exists, otherwise create it\n  if (!util::file_exists(key_path)) {\n    // 1) Create temp folder\n    // 2) Set permissions\n    // 3) Symlink it to temp link\n    // 4) Move symlink to <params>/d\n\n    std::string tmp_path = param_path + \"/.tmp_XXXXXX\";\n    // this should be OK since mkdtemp just replaces characters in place\n    char *tmp_dir = mkdtemp((char *)tmp_path.c_str());\n    if (tmp_dir == NULL) {\n      return false;\n    }\n\n    std::string link_path = std::string(tmp_dir) + \".link\";\n    if (symlink(tmp_dir, link_path.c_str()) != 0) {\n      return false;\n    }\n\n    // don't return false if it has been created by other\n    if (rename(link_path.c_str(), key_path.c_str()) != 0 && errno != EEXIST) {\n      return false;\n    }\n  }\n\n  return true;\n}\n\nvoid ensure_params_path(const std::string &params_path) {\n  if (!create_params_path(params_path, params_path + \"/d\")) {\n    throw std::runtime_error(util::string_format(\"Failed to ensure params path, errno=%d\", errno));\n  }\n}\n\nclass FileLock {\n public:\n  FileLock(const std::string& file_name, int op) : fn_(file_name), op_(op) {}\n\n  void lock() {\n    fd_ = HANDLE_EINTR(open(fn_.c_str(), O_CREAT, 0777));\n    if (fd_ < 0) {\n      LOGE(\"Failed to open lock file %s, errno=%d\", fn_.c_str(), errno);\n      return;\n    }\n    if (HANDLE_EINTR(flock(fd_, op_)) < 0) {\n      LOGE(\"Failed to lock file %s, errno=%d\", fn_.c_str(), errno);\n    }\n  }\n\n  void unlock() { close(fd_); }\n\nprivate:\n  int fd_ = -1, op_;\n  std::string fn_;\n};\n\nstd::unordered_map<std::string, uint32_t> keys = {\n    {\"AccessToken\", CLEAR_ON_MANAGER_START | DONT_LOG},\n    {\"ApiCache_DriveStats\", PERSISTENT},\n    {\"ApiCache_Device\", PERSISTENT},\n    {\"ApiCache_Owner\", PERSISTENT},\n    {\"ApiCache_NavDestinations\", PERSISTENT},\n    {\"AthenadPid\", PERSISTENT},\n    {\"CalibrationParams\", PERSISTENT},\n    {\"CarBatteryCapacity\", PERSISTENT},\n    {\"CarParams\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT | CLEAR_ON_IGNITION_ON},\n    {\"CarParamsCache\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT},\n    {\"CarVin\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT | CLEAR_ON_IGNITION_ON},\n    {\"CommunityFeaturesToggle\", PERSISTENT},\n    {\"ControlsReady\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT | CLEAR_ON_IGNITION_ON},\n    {\"CurrentRoute\", CLEAR_ON_MANAGER_START | CLEAR_ON_IGNITION_ON},\n    {\"DisableRadar\", PERSISTENT}, // WARNING: THIS DISABLES AEB\n    {\"EndToEndToggle\", PERSISTENT},\n    {\"CompletedTrainingVersion\", PERSISTENT},\n    {\"DisablePowerDown\", PERSISTENT},\n    {\"DisableUpdates\", PERSISTENT},\n    {\"EnableWideCamera\", CLEAR_ON_MANAGER_START},\n    {\"DoUninstall\", CLEAR_ON_MANAGER_START},\n    {\"DongleId\", PERSISTENT},\n    {\"GitDiff\", PERSISTENT},\n    {\"GitBranch\", PERSISTENT},\n    {\"GitCommit\", PERSISTENT},\n    {\"GitRemote\", PERSISTENT},\n    {\"GithubSshKeys\", PERSISTENT},\n    {\"GithubUsername\", PERSISTENT},\n    {\"GsmRoaming\", PERSISTENT},\n    {\"HardwareSerial\", PERSISTENT},\n    {\"HasAcceptedTerms\", PERSISTENT},\n    {\"IsDriverViewEnabled\", CLEAR_ON_MANAGER_START},\n    {\"IMEI\", PERSISTENT},\n    {\"IsLdwEnabled\", PERSISTENT},\n    {\"IsMetric\", PERSISTENT},\n    {\"IsOffroad\", CLEAR_ON_MANAGER_START},\n    {\"IsOnroad\", PERSISTENT},\n    {\"IsRHD\", PERSISTENT},\n    {\"IsTakingSnapshot\", CLEAR_ON_MANAGER_START},\n    {\"IsUpdateAvailable\", CLEAR_ON_MANAGER_START},\n    {\"UploadRaw\", PERSISTENT},\n    {\"LastAthenaPingTime\", CLEAR_ON_MANAGER_START},\n    {\"LastGPSPosition\", PERSISTENT},\n    {\"LastUpdateException\", PERSISTENT},\n    {\"LastUpdateTime\", PERSISTENT},\n    {\"LiveParameters\", PERSISTENT},\n    {\"MapboxToken\", PERSISTENT | DONT_LOG},\n    {\"NavDestination\", CLEAR_ON_MANAGER_START | CLEAR_ON_IGNITION_OFF},\n    {\"NavSettingTime24h\", PERSISTENT},\n    {\"OpenpilotEnabledToggle\", PERSISTENT},\n    {\"PandaFirmware\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT},\n    {\"PandaFirmwareHex\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT},\n    {\"PandaDongleId\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT},\n    {\"PandaHeartbeatLost\", CLEAR_ON_MANAGER_START | CLEAR_ON_IGNITION_OFF},\n    {\"Passive\", PERSISTENT},\n    {\"PrimeRedirected\", PERSISTENT},\n    {\"RecordFront\", PERSISTENT},\n    {\"RecordFrontLock\", PERSISTENT},  // for the internal fleet\n    {\"ReleaseNotes\", PERSISTENT},\n    {\"ShouldDoUpdate\", CLEAR_ON_MANAGER_START},\n    {\"ShowDebugUI\", PERSISTENT},\n    {\"SpeedLimitControl\", PERSISTENT},\n    {\"SpeedLimitPercOffset\", PERSISTENT},\n    {\"SubscriberInfo\", PERSISTENT},\n    {\"SshEnabled\", PERSISTENT},\n    {\"TermsVersion\", PERSISTENT},\n    {\"Timezone\", PERSISTENT},\n    {\"TrainingVersion\", PERSISTENT},\n    {\"TurnSpeedControl\", PERSISTENT},\n    {\"TurnVisionControl\", PERSISTENT},\n    {\"UpdateAvailable\", CLEAR_ON_MANAGER_START},\n    {\"UpdateFailedCount\", CLEAR_ON_MANAGER_START},\n    {\"Version\", PERSISTENT},\n    {\"VisionRadarToggle\", PERSISTENT},\n    {\"Offroad_ChargeDisabled\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT},\n    {\"Offroad_ConnectivityNeeded\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_ConnectivityNeededPrompt\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_TemperatureTooHigh\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_PandaFirmwareMismatch\", CLEAR_ON_MANAGER_START | CLEAR_ON_PANDA_DISCONNECT},\n    {\"Offroad_InvalidTime\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_IsTakingSnapshot\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_NeosUpdate\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_UpdateFailed\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_HardwareUnsupported\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_UnofficialHardware\", CLEAR_ON_MANAGER_START},\n    {\"Offroad_NvmeMissing\", CLEAR_ON_MANAGER_START},\n    {\"ForcePowerDown\", CLEAR_ON_MANAGER_START},\n    {\"JoystickDebugMode\", CLEAR_ON_MANAGER_START | CLEAR_ON_IGNITION_OFF},\n    // dp\n    {\"dp_api_custom\", PERSISTENT},\n    {\"dp_api_custom_url\", PERSISTENT},\n    {\"dp_atl\", PERSISTENT},\n    {\"dp_atl_op_long\", PERSISTENT},\n    {\"dp_dashcamd\", PERSISTENT},\n    {\"dp_auto_shutdown\", PERSISTENT},\n    {\"dp_auto_shutdown_in\", PERSISTENT},\n    {\"dp_updated\", PERSISTENT},\n    {\"dp_logger\", PERSISTENT},\n    {\"dp_athenad\", PERSISTENT},\n    {\"dp_uploader\", PERSISTENT},\n    {\"dp_hotspot_on_boot\", PERSISTENT},\n    {\"dp_lateral_mode\", PERSISTENT},\n    {\"dp_signal_off_delay\", PERSISTENT},\n    {\"dp_lc_min_mph\", PERSISTENT},\n    {\"dp_lc_auto_min_mph\", PERSISTENT},\n    {\"dp_lc_auto_delay\", PERSISTENT},\n    {\"dp_lane_less_mode_ctrl\", PERSISTENT},\n    {\"dp_lane_less_mode\", PERSISTENT},\n    {\"dp_allow_gas\", PERSISTENT},\n    {\"dp_following_profile_ctrl\", PERSISTENT},\n    {\"dp_following_profile\", PERSISTENT},\n    {\"dp_accel_profile_ctrl\", PERSISTENT},\n    {\"dp_accel_profile\", PERSISTENT},\n    {\"dp_gear_check\", PERSISTENT},\n    {\"dp_speed_check\", PERSISTENT},\n    {\"dp_temp_monitor\", PERSISTENT},\n    {\"dp_ui_display_mode\", PERSISTENT},\n    {\"dp_ui_speed\", PERSISTENT},\n    {\"dp_ui_event\", PERSISTENT},\n    {\"dp_ui_max_speed\", PERSISTENT},\n    {\"dp_ui_face\", PERSISTENT},\n    {\"dp_ui_lane\", PERSISTENT},\n    {\"dp_ui_lead\", PERSISTENT},\n    {\"dp_ui_side\", PERSISTENT},\n    {\"dp_ui_top\", PERSISTENT},\n    {\"dp_ui_blinker\", PERSISTENT},\n    {\"dp_ui_brightness\", PERSISTENT},\n    {\"dp_ui_volume\", PERSISTENT},\n    {\"dp_lexus_rx_rpm_fix\", PERSISTENT},\n    {\"dp_toyota_ldw\", PERSISTENT},\n    {\"dp_toyota_sng\", PERSISTENT},\n    {\"dp_toyota_zss\", PERSISTENT},\n    {\"dp_toyota_fp_btn_link\", PERSISTENT},\n    {\"dp_toyota_ap_btn_link\", PERSISTENT},\n    {\"dp_toyota_disable_relay\", PERSISTENT},\n    {\"dp_toyota_cruise_override\", PERSISTENT},\n    {\"dp_toyota_cruise_override_vego\", PERSISTENT},\n    {\"dp_toyota_cruise_override_at\", PERSISTENT},\n    {\"dp_toyota_cruise_override_speed\", PERSISTENT},\n    {\"dp_hkg_smart_mdps\", PERSISTENT},\n    {\"dp_honda_eps_mod\", PERSISTENT},\n    {\"dp_honda_kmh_display\", PERSISTENT},\n    {\"dp_vw_panda\", PERSISTENT},\n    {\"dp_vw_timebomb_assist\", PERSISTENT},\n    {\"dp_fan_mode\", PERSISTENT},\n    {\"dp_last_modified\", PERSISTENT},\n    {\"dp_camera_offset\", PERSISTENT},\n    {\"dp_path_offset\", PERSISTENT},\n    {\"dp_locale\", PERSISTENT},\n    {\"dp_reg\", PERSISTENT},\n    {\"dp_sr_learner\", PERSISTENT},\n    {\"dp_sr_custom\", PERSISTENT},\n    {\"dp_sr_stock\", PERSISTENT},\n    {\"dp_lqr\", PERSISTENT},\n    {\"dp_reset_live_param_on_start\", PERSISTENT},\n    {\"dp_appd\", PERSISTENT},\n    {\"dp_jetson\", PERSISTENT},\n    {\"dp_car_assigned\", PERSISTENT},\n    {\"dp_car_list\", PERSISTENT},\n    {\"dp_no_batt\", PERSISTENT},\n    {\"dp_last_candidate\", PERSISTENT},\n    {\"dp_prebuilt\", PERSISTENT},\n    {\"dp_gpxd\", PERSISTENT},\n    {\"dp_mapd\", PERSISTENT},\n    {\"dp_otisserv\", PERSISTENT},\n    {\"dp_mapbox_token_pk\", PERSISTENT},\n    {\"dp_mapbox_token_sk\", PERSISTENT},\n    {\"dp_mapbox_full_screen\", PERSISTENT},\n    {\"dp_mapbox_traffic\", PERSISTENT},\n    {\"dp_mapbox_gmap_enable\", PERSISTENT},\n    {\"dp_mapbox_gmap_key\", PERSISTENT},\n};\n\n} // namespace\n\nParams::Params() : params_path(Path::params()) {\n  static std::once_flag once_flag;\n  std::call_once(once_flag, ensure_params_path, params_path);\n}\n\nParams::Params(const std::string &path) : params_path(path) {\n  ensure_params_path(params_path);\n}\n\nbool Params::checkKey(const std::string &key) {\n  return keys.find(key) != keys.end();\n}\n\nParamKeyType Params::getKeyType(const std::string &key) {\n  return static_cast<ParamKeyType>(keys[key]);\n}\n\nint Params::put(const char* key, const char* value, size_t value_size) {\n  // Information about safely and atomically writing a file: https://lwn.net/Articles/457667/\n  // 1) Create temp file\n  // 2) Write data to temp file\n  // 3) fsync() the temp file\n  // 4) rename the temp file to the real name\n  // 5) fsync() the containing directory\n  std::string tmp_path = params_path + \"/.tmp_value_XXXXXX\";\n  int tmp_fd = mkstemp((char*)tmp_path.c_str());\n  if (tmp_fd < 0) return -1;\n\n  int result = -1;\n  do {\n    // Write value to temp.\n    ssize_t bytes_written = HANDLE_EINTR(write(tmp_fd, value, value_size));\n    if (bytes_written < 0 || (size_t)bytes_written != value_size) {\n      result = -20;\n      break;\n    }\n\n    // fsync to force persist the changes.\n    if ((result = fsync(tmp_fd)) < 0) break;\n\n    FileLock file_lock(params_path + \"/.lock\", LOCK_EX);\n    std::lock_guard<FileLock> lk(file_lock);\n\n    // Move temp into place.\n    std::string path = params_path + \"/d/\" + std::string(key);\n    if ((result = rename(tmp_path.c_str(), path.c_str())) < 0) break;\n\n    // fsync parent directory\n    path = params_path + \"/d\";\n    result = fsync_dir(path.c_str());\n  } while (false);\n\n  close(tmp_fd);\n  ::unlink(tmp_path.c_str());\n  return result;\n}\n\nint Params::remove(const char *key) {\n  FileLock file_lock(params_path + \"/.lock\", LOCK_EX);\n  std::lock_guard<FileLock> lk(file_lock);\n  // Delete value.\n  std::string path = params_path + \"/d/\" + key;\n  int result = unlink(path.c_str());\n  if (result != 0) {\n    return result;\n  }\n  // fsync parent directory\n  path = params_path + \"/d\";\n  return fsync_dir(path.c_str());\n}\n\nstd::string Params::get(const char *key, bool block) {\n  std::string path = params_path + \"/d/\" + key;\n  if (!block) {\n    return util::read_file(path);\n  } else {\n    // blocking read until successful\n    params_do_exit = 0;\n    void (*prev_handler_sigint)(int) = std::signal(SIGINT, params_sig_handler);\n    void (*prev_handler_sigterm)(int) = std::signal(SIGTERM, params_sig_handler);\n\n    std::string value;\n    while (!params_do_exit) {\n      if (value = util::read_file(path); !value.empty()) {\n        break;\n      }\n      util::sleep_for(100);  // 0.1 s\n    }\n\n    std::signal(SIGINT, prev_handler_sigint);\n    std::signal(SIGTERM, prev_handler_sigterm);\n    return value;\n  }\n}\n\nstd::map<std::string, std::string> Params::readAll() {\n  FileLock file_lock(params_path + \"/.lock\", LOCK_SH);\n  std::lock_guard<FileLock> lk(file_lock);\n\n  std::string key_path = params_path + \"/d\";\n  return util::read_files_in_dir(key_path);\n}\n\nvoid Params::clearAll(ParamKeyType key_type) {\n  FileLock file_lock(params_path + \"/.lock\", LOCK_EX);\n  std::lock_guard<FileLock> lk(file_lock);\n\n  std::string path;\n  for (auto &[key, type] : keys) {\n    if (type & key_type) {\n      path = params_path + \"/d/\" + key;\n      unlink(path.c_str());\n    }\n  }\n\n  // fsync parent directory\n  path = params_path + \"/d\";\n  fsync_dir(path.c_str());\n}\n\nstd::string Params::get_params_path() {\n  return params_path;\n}\n"
  },
  {
    "path": "selfdrive/common/params.h",
    "content": "#pragma once\n\n#include <map>\n#include <sstream>\n#include <string>\n\nenum ParamKeyType {\n  PERSISTENT = 0x02,\n  CLEAR_ON_MANAGER_START = 0x04,\n  CLEAR_ON_PANDA_DISCONNECT = 0x08,\n  CLEAR_ON_IGNITION_ON = 0x10,\n  CLEAR_ON_IGNITION_OFF = 0x20,\n  DONT_LOG = 0x40,\n  ALL = 0xFFFFFFFF\n};\n\nclass Params {\npublic:\n  Params();\n  Params(const std::string &path);\n\n  bool checkKey(const std::string &key);\n  ParamKeyType getKeyType(const std::string &key);\n\n  // Delete a value\n  int remove(const char *key);\n  inline int remove(const std::string &key) {\n    return remove (key.c_str());\n  }\n  void clearAll(ParamKeyType type);\n\n  // read all values\n  std::map<std::string, std::string> readAll();\n\n  // helpers for reading values\n  std::string get(const char *key, bool block = false);\n\n  inline std::string get(const std::string &key, bool block = false) {\n    return get(key.c_str(), block);\n  }\n\n  inline std::string getParamsPath() {\n    return params_path;\n  }\n\n  inline std::string getParamPath(std::string key) {\n    return params_path + \"/d/\" + key;\n  }\n\n  template <class T>\n  std::optional<T> get(const char *key, bool block = false) {\n    std::istringstream iss(get(key, block));\n    T value{};\n    iss >> value;\n    return iss.fail() ? std::nullopt : std::optional(value);\n  }\n\n  inline bool getBool(const std::string &key) {\n    return getBool(key.c_str());\n  }\n\n  inline bool getBool(const char *key) {\n    return get(key) == \"1\";\n  }\n\n  // helpers for writing values\n  int put(const char* key, const char* val, size_t value_size);\n\n  inline int put(const std::string &key, const std::string &val) {\n    return put(key.c_str(), val.data(), val.size());\n  }\n\n  inline int putBool(const char *key, bool val) {\n    return put(key, val ? \"1\" : \"0\", 1);\n  }\n\n  inline int putBool(const std::string &key, bool val) {\n    return putBool(key.c_str(), val);\n  }\n\n  inline std::string get_params_path();\n\nprivate:\n  const std::string params_path;\n};\n"
  },
  {
    "path": "selfdrive/common/queue.h",
    "content": "#pragma once\n\n#include <condition_variable>\n#include <mutex>\n#include <queue>\n\ntemplate <class T>\nclass SafeQueue {\npublic:\n  SafeQueue() = default;\n\n  void push(const T& v) {\n    {\n      std::unique_lock lk(m);\n      q.push(v);\n    }\n    cv.notify_one();\n  }\n\n  T pop() {\n    std::unique_lock lk(m);\n    cv.wait(lk, [this] { return !q.empty(); });\n    T v = q.front();\n    q.pop();\n    return v;\n  }\n\n  bool try_pop(T& v, int timeout_ms = 0) {\n    std::unique_lock lk(m);\n    if (!cv.wait_for(lk, std::chrono::milliseconds(timeout_ms), [this] { return !q.empty(); })) {\n      return false;\n    }\n    v = q.front();\n    q.pop();\n    return true;\n  }\n\n  bool empty() const {\n    std::scoped_lock lk(m);\n    return q.empty();\n  }\n\n  size_t size() const {\n    std::scoped_lock lk(m);\n    return q.size();\n  }\n\nprivate:\n  mutable std::mutex m;\n  std::condition_variable cv;\n  std::queue<T> q;\n};\n"
  },
  {
    "path": "selfdrive/common/swaglog.cc",
    "content": "#ifndef _GNU_SOURCE\n#define _GNU_SOURCE\n#endif\n\n#include \"selfdrive/common/swaglog.h\"\n\n#include <cassert>\n#include <cstring>\n#include <mutex>\n#include <string>\n\n#include <zmq.h>\n#include \"json11.hpp\"\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/version.h\"\n#include \"selfdrive/hardware/hw.h\"\n\nclass LogState {\n public:\n  LogState() = default;\n  ~LogState();\n  std::mutex lock;\n  bool inited;\n  json11::Json::object ctx_j;\n  void *zctx;\n  void *sock;\n  int print_level;\n};\n\nLogState::~LogState() {\n  zmq_close(sock);\n  zmq_ctx_destroy(zctx);\n}\n\nstatic LogState s = {};\n\nstatic void cloudlog_bind_locked(const char* k, const char* v) {\n  s.ctx_j[k] = v;\n}\n\nstatic void cloudlog_init() {\n  if (s.inited) return;\n  s.ctx_j = json11::Json::object {};\n  s.zctx = zmq_ctx_new();\n  s.sock = zmq_socket(s.zctx, ZMQ_PUSH);\n\n  int timeout = 100; // 100 ms timeout on shutdown for messages to be received by logmessaged\n  zmq_setsockopt(s.sock, ZMQ_LINGER, &timeout, sizeof(timeout));\n\n  zmq_connect(s.sock, \"ipc:///tmp/logmessage\");\n\n  s.print_level = CLOUDLOG_WARNING;\n  const char* print_level = getenv(\"LOGPRINT\");\n  if (print_level) {\n    if (strcmp(print_level, \"debug\") == 0) {\n      s.print_level = CLOUDLOG_DEBUG;\n    } else if (strcmp(print_level, \"info\") == 0) {\n      s.print_level = CLOUDLOG_INFO;\n    } else if (strcmp(print_level, \"warning\") == 0) {\n      s.print_level = CLOUDLOG_WARNING;\n    }\n  }\n\n  // openpilot bindings\n  char* dongle_id = getenv(\"DONGLE_ID\");\n  if (dongle_id) {\n    cloudlog_bind_locked(\"dongle_id\", dongle_id);\n  }\n  cloudlog_bind_locked(\"version\", COMMA_VERSION);\n  s.ctx_j[\"dirty\"] = !getenv(\"CLEAN\");\n\n  // device type\n  if (Hardware::EON()) {\n    cloudlog_bind_locked(\"device\", \"eon\");\n  } else if (Hardware::TICI()) {\n    cloudlog_bind_locked(\"device\", \"tici\");\n  } else if (Hardware::JETSON()) {\n    cloudlog_bind_locked(\"device\", \"jetson\");\n  } else {\n    cloudlog_bind_locked(\"device\", \"pc\");\n  }\n\n  s.inited = true;\n}\n\nvoid log(int levelnum, const char* filename, int lineno, const char* func, const char* msg, const std::string& log_s) {\n  std::lock_guard lk(s.lock);\n  cloudlog_init();\n  if (levelnum >= s.print_level) {\n    printf(\"%s: %s\\n\", filename, msg);\n  }\n  char levelnum_c = levelnum;\n  zmq_send(s.sock, (levelnum_c + log_s).c_str(), log_s.length() + 1, ZMQ_NOBLOCK);\n}\n\nvoid cloudlog_e(int levelnum, const char* filename, int lineno, const char* func,\n                const char* fmt, ...) {\n  char* msg_buf = nullptr;\n  va_list args;\n  va_start(args, fmt);\n  vasprintf(&msg_buf, fmt, args);\n  va_end(args);\n\n  if (!msg_buf) return;\n\n  json11::Json log_j = json11::Json::object {\n    {\"msg\", msg_buf},\n    {\"ctx\", s.ctx_j},\n    {\"levelnum\", levelnum},\n    {\"filename\", filename},\n    {\"lineno\", lineno},\n    {\"funcname\", func},\n    {\"created\", seconds_since_epoch()}\n  };\n  std::string log_s = log_j.dump();\n  log(levelnum, filename, lineno, func, msg_buf, log_s);\n  free(msg_buf);\n}\n\nvoid cloudlog_bind(const char* k, const char* v) {\n  std::lock_guard lk(s.lock);\n  cloudlog_init();\n  cloudlog_bind_locked(k, v);\n}\n"
  },
  {
    "path": "selfdrive/common/swaglog.h",
    "content": "#pragma once\n\n#include \"selfdrive/common/timing.h\"\n\n#define CLOUDLOG_DEBUG 10\n#define CLOUDLOG_INFO 20\n#define CLOUDLOG_WARNING 30\n#define CLOUDLOG_ERROR 40\n#define CLOUDLOG_CRITICAL 50\n\nvoid cloudlog_e(int levelnum, const char* filename, int lineno, const char* func,\n                const char* fmt, ...) /*__attribute__ ((format (printf, 6, 7)))*/;\n\nvoid cloudlog_bind(const char* k, const char* v);\n\n#define cloudlog(lvl, fmt, ...) cloudlog_e(lvl, __FILE__, __LINE__, \\\n                                           __func__, \\\n                                           fmt, ## __VA_ARGS__)\n\n#define cloudlog_rl(burst, millis, lvl, fmt, ...)   \\\n{                                                   \\\n  static uint64_t __begin = 0;                      \\\n  static int __printed = 0;                         \\\n  static int __missed = 0;                          \\\n                                                    \\\n  int __burst = (burst);                            \\\n  int __millis = (millis);                          \\\n  uint64_t __ts = nanos_since_boot();               \\\n                                                    \\\n  if (!__begin) __begin = __ts;                     \\\n                                                    \\\n  if (__begin + __millis*1000000ULL < __ts) {       \\\n    if (__missed) {                                 \\\n      cloudlog(CLOUDLOG_WARNING, \"cloudlog: %d messages suppressed\", __missed); \\\n    }                                               \\\n    __begin = 0;                                    \\\n    __printed = 0;                                  \\\n    __missed = 0;                                   \\\n  }                                                 \\\n                                                    \\\n  if (__printed < __burst) {                        \\\n    cloudlog(lvl, fmt, ## __VA_ARGS__);             \\\n    __printed++;                                    \\\n  } else {                                          \\\n    __missed++;                                     \\\n  }                                                 \\\n}\n\n#define LOGD(fmt, ...) cloudlog(CLOUDLOG_DEBUG, fmt, ## __VA_ARGS__)\n#define LOG(fmt, ...) cloudlog(CLOUDLOG_INFO, fmt, ## __VA_ARGS__)\n#define LOGW(fmt, ...) cloudlog(CLOUDLOG_WARNING, fmt, ## __VA_ARGS__)\n#define LOGE(fmt, ...) cloudlog(CLOUDLOG_ERROR, fmt, ## __VA_ARGS__)\n\n#define LOGD_100(fmt, ...) cloudlog_rl(2, 100, CLOUDLOG_DEBUG, fmt, ## __VA_ARGS__)\n#define LOG_100(fmt, ...) cloudlog_rl(2, 100, CLOUDLOG_INFO, fmt, ## __VA_ARGS__)\n#define LOGW_100(fmt, ...) cloudlog_rl(2, 100, CLOUDLOG_WARNING, fmt, ## __VA_ARGS__)\n#define LOGE_100(fmt, ...) cloudlog_rl(2, 100, CLOUDLOG_ERROR, fmt, ## __VA_ARGS__)\n"
  },
  {
    "path": "selfdrive/common/timing.h",
    "content": "#pragma once\n\n#include <cstdint>\n#include <ctime>\n\n#ifdef __APPLE__\n#define CLOCK_BOOTTIME CLOCK_MONOTONIC\n#endif\n\nstatic inline uint64_t nanos_since_boot() {\n  struct timespec t;\n  clock_gettime(CLOCK_BOOTTIME, &t);\n  return t.tv_sec * 1000000000ULL + t.tv_nsec;\n}\n\nstatic inline double millis_since_boot() {\n  struct timespec t;\n  clock_gettime(CLOCK_BOOTTIME, &t);\n  return t.tv_sec * 1000.0 + t.tv_nsec * 1e-6;\n}\n\nstatic inline double seconds_since_boot() {\n  struct timespec t;\n  clock_gettime(CLOCK_BOOTTIME, &t);\n  return (double)t.tv_sec + t.tv_nsec * 1e-9;\n}\n\nstatic inline uint64_t nanos_since_epoch() {\n  struct timespec t;\n  clock_gettime(CLOCK_REALTIME, &t);\n  return t.tv_sec * 1000000000ULL + t.tv_nsec;\n}\n\nstatic inline double seconds_since_epoch() {\n  struct timespec t;\n  clock_gettime(CLOCK_REALTIME, &t);\n  return (double)t.tv_sec + t.tv_nsec * 1e-9;\n}\n\n// you probably should use nanos_since_boot instead\nstatic inline uint64_t nanos_monotonic() {\n  struct timespec t;\n  clock_gettime(CLOCK_MONOTONIC, &t);\n  return t.tv_sec * 1000000000ULL + t.tv_nsec;\n}\n\nstatic inline uint64_t nanos_monotonic_raw() {\n  struct timespec t;\n  clock_gettime(CLOCK_MONOTONIC_RAW, &t);\n  return t.tv_sec * 1000000000ULL + t.tv_nsec;\n}\n"
  },
  {
    "path": "selfdrive/common/touch.c",
    "content": "#include \"selfdrive/common/touch.h\"\n\n#include <assert.h>\n#include <dirent.h>\n#include <fcntl.h>\n#include <linux/input.h>\n#include <stdbool.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/poll.h>\n#include <unistd.h>\n\n/* this macro is used to tell if \"bit\" is set in \"array\"\n * it selects a byte from the array, and does a boolean AND\n * operation with a byte that only has the relevant bit set.\n * eg. to check for the 12th bit, we do (array[1] & 1<<4)\n */\n#define test_bit(bit, array)    (array[bit/8] & (1<<(bit%8)))\n\nstatic int find_dev() {\n  int err;\n\n  int ret = -1;\n\n  DIR *dir = opendir(\"/dev/input\");\n  assert(dir);\n  struct dirent* de = NULL;\n  while ((de = readdir(dir))) {\n    if (strncmp(de->d_name, \"event\", 5)) continue;\n\n    int fd = openat(dirfd(dir), de->d_name, O_RDONLY);\n    assert(fd >= 0);\n\n    unsigned char ev_bits[KEY_MAX / 8 + 1];\n    err = ioctl(fd, EVIOCGBIT(EV_ABS, sizeof(ev_bits)), ev_bits);\n    assert(err >= 0);\n\n    if (test_bit(ABS_MT_POSITION_X, ev_bits) && test_bit(ABS_MT_POSITION_Y, ev_bits)) {\n      ret = fd;\n      break;\n    }\n    close(fd);\n  }\n  closedir(dir);\n\n  return ret;\n}\n\nvoid touch_init(TouchState *s) {\n  s->fd = find_dev();\n  assert(s->fd >= 0);\n}\n\nint touch_poll(TouchState *s, int* out_x, int* out_y, int timeout) {\n  assert(out_x && out_y);\n  bool up = false;\n  while (true) {\n    struct pollfd polls[] = {{\n      .fd = s->fd,\n      .events = POLLIN,\n    }};\n    int err = poll(polls, 1, timeout);\n    if (err < 0) {\n      return -1;\n    }\n    if (!(polls[0].revents & POLLIN)) {\n      break;\n    }\n\n    struct input_event event;\n    err = read(polls[0].fd, &event, sizeof(event));\n    if (err < sizeof(event)) {\n      return -1;\n    }\n\n    switch (event.type) {\n    case EV_ABS:\n      if (event.code == ABS_MT_POSITION_X) {\n        s->last_x = event.value;\n      } else if (event.code == ABS_MT_POSITION_Y) {\n        s->last_y = event.value;\n      } else if (event.code == ABS_MT_TRACKING_ID && event.value != -1) {\n        up = true;\n      }\n      break;\n    default:\n      break;\n    }\n  }\n  if (up) {\n    // adjust for flippening\n    *out_x = s->last_y;\n    *out_y = 1080 - s->last_x;\n  }\n  return up;\n}\n"
  },
  {
    "path": "selfdrive/common/touch.h",
    "content": "#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef struct TouchState {\n  int fd;\n  int last_x, last_y;\n} TouchState;\n\nvoid touch_init(TouchState *s);\nint touch_poll(TouchState *s, int *out_x, int *out_y, int timeout);\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "selfdrive/common/util.cc",
    "content": "#include \"selfdrive/common/util.h\"\n\n#include <sys/stat.h>\n\n#include <cassert>\n#include <cerrno>\n#include <cstring>\n#include <dirent.h>\n#include <fstream>\n#include <sstream>\n#include <iomanip>\n\n#ifdef __linux__\n#include <sys/prctl.h>\n#include <sys/syscall.h>\n#ifndef __USE_GNU\n#define __USE_GNU\n#endif\n#include <sched.h>\n#endif  // __linux__\n\nvoid set_thread_name(const char* name) {\n#ifdef __linux__\n  // pthread_setname_np is dumb (fails instead of truncates)\n  prctl(PR_SET_NAME, (unsigned long)name, 0, 0, 0);\n#endif\n}\n\nint set_realtime_priority(int level) {\n#ifdef __linux__\n  long tid = syscall(SYS_gettid);\n\n  // should match python using chrt\n  struct sched_param sa;\n  memset(&sa, 0, sizeof(sa));\n  sa.sched_priority = level;\n  return sched_setscheduler(tid, SCHED_FIFO, &sa);\n#else\n  return -1;\n#endif\n}\n\nint set_core_affinity(int core) {\n#ifdef __linux__\n  long tid = syscall(SYS_gettid);\n  cpu_set_t rt_cpu;\n\n  CPU_ZERO(&rt_cpu);\n  CPU_SET(core, &rt_cpu);\n  return sched_setaffinity(tid, sizeof(rt_cpu), &rt_cpu);\n#else\n  return -1;\n#endif\n}\n\nnamespace util {\n\nstd::string read_file(const std::string& fn) {\n  std::ifstream f(fn, std::ios::binary | std::ios::in);\n  if (f.is_open()) {\n    f.seekg(0, std::ios::end);\n    int size = f.tellg();\n    if (f.good() && size > 0) {\n      std::string result(size, '\\0');\n      f.seekg(0, std::ios::beg);\n      f.read(result.data(), size);\n      // return either good() or has reached end-of-file (e.g. /sys/power/wakeup_count)\n      if (f.good() || f.eof()) {\n        result.resize(f.gcount());\n        return result;\n      }\n    }\n    // fallback for files created on read, e.g. procfs\n    std::stringstream buffer;\n    buffer << f.rdbuf();\n    return buffer.str();\n  }\n  return std::string();\n}\n\nstd::map<std::string, std::string> read_files_in_dir(const std::string &path) {\n  std::map<std::string, std::string> ret;\n  DIR *d = opendir(path.c_str());\n  if (!d) return ret;\n\n  struct dirent *de = NULL;\n  while ((de = readdir(d))) {\n    if (de->d_type != DT_DIR) {\n      ret[de->d_name] = util::read_file(path + \"/\" + de->d_name);\n    }\n  }\n\n  closedir(d);\n  return ret;\n}\n\nint write_file(const char* path, const void* data, size_t size, int flags, mode_t mode) {\n  int fd = HANDLE_EINTR(open(path, flags, mode));\n  if (fd == -1) {\n    return -1;\n  }\n  ssize_t n = HANDLE_EINTR(write(fd, data, size));\n  close(fd);\n  return (n >= 0 && (size_t)n == size) ? 0 : -1;\n}\n\nstd::string readlink(const std::string &path) {\n  char buff[4096];\n  ssize_t len = ::readlink(path.c_str(), buff, sizeof(buff)-1);\n  if (len != -1) {\n    buff[len] = '\\0';\n    return std::string(buff);\n  }\n  return \"\";\n}\n\nbool file_exists(const std::string& fn) {\n  struct stat st = {};\n  return stat(fn.c_str(), &st) != -1;\n}\n\nstd::string getenv(const char* key, const char* default_val) {\n  const char* val = ::getenv(key);\n  return val ? val : default_val;\n}\n\nint getenv(const char* key, int default_val) {\n  const char* val = ::getenv(key);\n  return val ? atoi(val) : default_val;\n}\n\nfloat getenv(const char* key, float default_val) {\n  const char* val = ::getenv(key);\n  return val ? atof(val) : default_val;\n}\n\nstd::string tohex(const uint8_t *buf, size_t buf_size) {\n  std::unique_ptr<char[]> hexbuf(new char[buf_size * 2 + 1]);\n  for (size_t i = 0; i < buf_size; i++) {\n    sprintf(&hexbuf[i * 2], \"%02x\", buf[i]);\n  }\n  hexbuf[buf_size * 2] = 0;\n  return std::string(hexbuf.get(), hexbuf.get() + buf_size * 2);\n}\n\nstd::string hexdump(const std::string& in) {\n    std::stringstream ss;\n    ss << std::hex << std::setfill('0');\n    for (size_t i = 0; i < in.size(); i++) {\n        ss << std::setw(2) << static_cast<unsigned int>(static_cast<unsigned char>(in[i]));\n    }\n    return ss.str();\n}\n\nstd::string base_name(std::string const &path) {\n  size_t pos = path.find_last_of(\"/\");\n  if (pos == std::string::npos) return path;\n  return path.substr(pos + 1);\n}\n\nstd::string dir_name(std::string const &path) {\n  size_t pos = path.find_last_of(\"/\");\n  if (pos == std::string::npos) return \"\";\n  return path.substr(0, pos);\n}\n\nstruct tm get_time() {\n  time_t rawtime;\n  time(&rawtime);\n\n  struct tm sys_time;\n  gmtime_r(&rawtime, &sys_time);\n\n  return sys_time;\n}\n\nbool time_valid(struct tm sys_time) {\n  int year = 1900 + sys_time.tm_year;\n  int month = 1 + sys_time.tm_mon;\n  return (year > 2021) || (year == 2021 && month >= 6);\n}\n\n}  // namespace util\n"
  },
  {
    "path": "selfdrive/common/util.h",
    "content": "#pragma once\n\n#include <fcntl.h>\n#include <unistd.h>\n\n#include <algorithm>\n#include <atomic>\n#include <chrono>\n#include <csignal>\n#include <ctime>\n#include <map>\n#include <memory>\n#include <string>\n#include <thread>\n\n// keep trying if x gets interrupted by a signal\n#define HANDLE_EINTR(x)                                       \\\n  ({                                                          \\\n    decltype(x) ret;                                          \\\n    int try_cnt = 0;                                          \\\n    do {                                                      \\\n      ret = (x);                                              \\\n    } while (ret == -1 && errno == EINTR && try_cnt++ < 100); \\\n    ret;                                                      \\\n  })\n\n#ifndef sighandler_t\ntypedef void (*sighandler_t)(int sig);\n#endif\n\nvoid set_thread_name(const char* name);\n\nint set_realtime_priority(int level);\nint set_core_affinity(int core);\n\nnamespace util {\n\n// ***** Time helpers *****\nstruct tm get_time();\nbool time_valid(struct tm sys_time);\n\n// ***** math helpers *****\n\n// map x from [a1, a2] to [b1, b2]\ntemplate <typename T>\nT map_val(T x, T a1, T a2, T b1, T b2) {\n  x = std::clamp(x, a1, a2);\n  T ra = a2 - a1;\n  T rb = b2 - b1;\n  return (x - a1) * rb / ra + b1;\n}\n\n// ***** string helpers *****\n\ntemplate <typename... Args>\nstd::string string_format(const std::string& format, Args... args) {\n  size_t size = snprintf(nullptr, 0, format.c_str(), args...) + 1;\n  std::unique_ptr<char[]> buf(new char[size]);\n  snprintf(buf.get(), size, format.c_str(), args...);\n  return std::string(buf.get(), buf.get() + size - 1);\n}\n\nstd::string getenv(const char* key, const char* default_val = \"\");\nint getenv(const char* key, int default_val);\nfloat getenv(const char* key, float default_val);\n\nstd::string tohex(const uint8_t* buf, size_t buf_size);\nstd::string hexdump(const std::string& in);\nstd::string base_name(std::string const& path);\nstd::string dir_name(std::string const& path);\n\n// **** file fhelpers *****\nstd::string read_file(const std::string& fn);\nstd::map<std::string, std::string> read_files_in_dir(const std::string& path);\nint write_file(const char* path, const void* data, size_t size, int flags = O_WRONLY, mode_t mode = 0664);\nstd::string readlink(const std::string& path);\nbool file_exists(const std::string& fn);\n\ninline void sleep_for(const int milliseconds) {\n  std::this_thread::sleep_for(std::chrono::milliseconds(milliseconds));\n}\n\n}  // namespace util\n\nclass ExitHandler {\npublic:\n  ExitHandler() {\n    std::signal(SIGINT, (sighandler_t)set_do_exit);\n    std::signal(SIGTERM, (sighandler_t)set_do_exit);\n\n#ifndef __APPLE__\n    std::signal(SIGPWR, (sighandler_t)set_do_exit);\n#endif\n  };\n  inline static std::atomic<bool> power_failure = false;\n  inline static std::atomic<int> signal = 0;\n  inline operator bool() { return do_exit; }\n  inline ExitHandler& operator=(bool v) {\n    signal = 0;\n    do_exit = v;\n    return *this;\n  }\nprivate:\n  static void set_do_exit(int sig) {\n#ifndef __APPLE__\n    power_failure = (sig == SIGPWR);\n#endif\n    signal = sig;\n    do_exit = true;\n  }\n  inline static std::atomic<bool> do_exit = false;\n};\n\nstruct unique_fd {\n  unique_fd(int fd = -1) : fd_(fd) {}\n  unique_fd& operator=(unique_fd&& uf) {\n    fd_ = uf.fd_;\n    uf.fd_ = -1;\n    return *this;\n  }\n  ~unique_fd() {\n    if (fd_ != -1) close(fd_);\n  }\n  operator int() const { return fd_; }\n  int fd_;\n};\n\nclass FirstOrderFilter {\npublic:\n  FirstOrderFilter(float x0, float ts, float dt) {\n    k_ = (dt / ts) / (1.0 + dt / ts);\n    x_ = x0;\n  }\n  inline float update(float x) {\n    x_ = (1. - k_) * x_ + k_ * x;\n    return x_;\n  }\n  inline void reset(float x) { x_ = x; }\n  inline float x(){ return x_; }\n\nprivate:\n  float x_, k_;\n};\n\ntemplate<typename T>\nvoid update_max_atomic(std::atomic<T>& max, T const& value) {\n  T prev = max;\n  while(prev < value && !max.compare_exchange_weak(prev, value)) {}\n}\n"
  },
  {
    "path": "selfdrive/common/version.h",
    "content": "#define COMMA_VERSION \"0.8.9-xnxpilot\"\n"
  },
  {
    "path": "selfdrive/common/visionimg.cc",
    "content": "#include \"selfdrive/common/visionimg.h\"\n\n#include <cassert>\n\n#ifdef QCOM\n#include <gralloc_priv.h>\n#include <system/graphics.h>\n#include <ui/GraphicBuffer.h>\n#include <ui/PixelFormat.h>\n#define GL_GLEXT_PROTOTYPES\n#include <GLES2/gl2ext.h>\nusing namespace android;\n\nEGLImageTexture::EGLImageTexture(const VisionBuf *buf) {\n  const int bpp = 3;\n  assert((buf->len % buf->stride) == 0);\n  assert((buf->stride % bpp) == 0);\n\n  const int format = HAL_PIXEL_FORMAT_RGB_888;\n  private_handle = new private_handle_t(buf->fd, buf->len,\n                             private_handle_t::PRIV_FLAGS_USES_ION|private_handle_t::PRIV_FLAGS_FRAMEBUFFER,\n                             0, format,\n                             buf->stride/bpp, buf->len/buf->stride,\n                             buf->width, buf->height);\n\n  // GraphicBuffer is ref counted by EGLClientBuffer(ANativeWindowBuffer), no need and not possible to release.\t\n  GraphicBuffer* gb = new GraphicBuffer(buf->width, buf->height, (PixelFormat)format,\n                                        GraphicBuffer::USAGE_HW_TEXTURE, buf->stride/bpp, (private_handle_t*)private_handle, false);\n\n  EGLDisplay display = eglGetDisplay(EGL_DEFAULT_DISPLAY);\n  assert(display != EGL_NO_DISPLAY);\n\n  EGLint img_attrs[] = {EGL_IMAGE_PRESERVED_KHR, EGL_TRUE, EGL_NONE};\n  img_khr = eglCreateImageKHR(display, EGL_NO_CONTEXT,\n                              EGL_NATIVE_BUFFER_ANDROID, gb->getNativeBuffer(), img_attrs);\n  assert(img_khr != EGL_NO_IMAGE_KHR);\n\n  glGenTextures(1, &frame_tex);\n  glBindTexture(GL_TEXTURE_2D, frame_tex);\n  glEGLImageTargetTexture2DOES(GL_TEXTURE_2D, img_khr);\n}\n\nEGLImageTexture::~EGLImageTexture() {\n  glDeleteTextures(1, &frame_tex);\n  EGLDisplay display = eglGetDisplay(EGL_DEFAULT_DISPLAY);\n  assert(display != EGL_NO_DISPLAY);\n  eglDestroyImageKHR(display, img_khr);\n  delete (private_handle_t*)private_handle;\n}\n\n#else // ifdef QCOM\n\nEGLImageTexture::EGLImageTexture(const VisionBuf *buf) {\n  glGenTextures(1, &frame_tex);\n  glBindTexture(GL_TEXTURE_2D, frame_tex);\n  glTexImage2D(GL_TEXTURE_2D, 0, GL_RGB, buf->width, buf->height, 0, GL_RGB, GL_UNSIGNED_BYTE, buf->addr);\n  glGenerateMipmap(GL_TEXTURE_2D);\n}\n\nEGLImageTexture::~EGLImageTexture() {\n  glDeleteTextures(1, &frame_tex);\n}\n#endif // ifdef QCOM\n"
  },
  {
    "path": "selfdrive/common/visionimg.h",
    "content": "#pragma once\n\n#include \"cereal/visionipc/visionbuf.h\"\n\n#ifdef __APPLE__\n#include <OpenGL/gl3.h>\n#else\n#include <GLES3/gl3.h>\n#endif\n\n#ifdef QCOM\n#include <EGL/egl.h>\n#define EGL_EGLEXT_PROTOTYPES\n#include <EGL/eglext.h>\n#undef Status\n#endif\n\nclass EGLImageTexture {\n public:\n  EGLImageTexture(const VisionBuf *buf);\n  ~EGLImageTexture();\n  GLuint frame_tex = 0;\n#ifdef QCOM\n  void *private_handle = nullptr;\n  EGLImageKHR img_khr = 0;\n#endif\n};\n"
  },
  {
    "path": "selfdrive/common/watchdog.cc",
    "content": "#include \"selfdrive/common/watchdog.h\"\n\n#include <unistd.h>\n\n#include <cstdint>\n#include <string>\n\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n\nconst std::string watchdog_fn_prefix = \"/dev/shm/wd_\";  // + <pid>\n\nbool watchdog_kick() {\n  std::string fn = watchdog_fn_prefix + std::to_string(getpid());\n  std::string cur_t = std::to_string(nanos_since_boot());\n\n  int r = util::write_file(fn.c_str(), cur_t.data(), cur_t.length(), O_WRONLY | O_CREAT);\n  return r == 0;\n}\n"
  },
  {
    "path": "selfdrive/common/watchdog.h",
    "content": "#pragma once\n\nbool watchdog_kick();\n"
  },
  {
    "path": "selfdrive/config.py",
    "content": "import numpy as np\n\nclass Conversions:\n  #Speed\n  MPH_TO_KPH = 1.609344\n  KPH_TO_MPH = 1. / MPH_TO_KPH\n  MS_TO_KPH = 3.6\n  KPH_TO_MS = 1. / MS_TO_KPH\n  MS_TO_MPH = MS_TO_KPH * KPH_TO_MPH\n  MPH_TO_MS = MPH_TO_KPH * KPH_TO_MS\n  MS_TO_KNOTS = 1.9438\n  KNOTS_TO_MS = 1. / MS_TO_KNOTS\n  #Angle\n  DEG_TO_RAD = np.pi / 180.\n  RAD_TO_DEG = 1. / DEG_TO_RAD\n  #Mass\n  LB_TO_KG = 0.453592\n  #Distance\n  MT_TO_FT = 3.28084\n\n\nRADAR_TO_CENTER = 2.7   # (deprecated) RADAR is ~ 2.7m ahead from center of car\nRADAR_TO_CAMERA = 1.52   # RADAR is ~ 1.5m ahead from center of mesh frame\n\nclass UIParams:\n  lidar_x, lidar_y, lidar_zoom = 384, 960, 6\n  lidar_car_x, lidar_car_y = lidar_x / 2., lidar_y / 1.1\n  car_hwidth = 1.7272 / 2 * lidar_zoom\n  car_front = 2.6924 * lidar_zoom\n  car_back = 1.8796 * lidar_zoom\n  car_color = 110\n"
  },
  {
    "path": "selfdrive/controls/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/controls/controlsd.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport math\nfrom numbers import Number\n\nfrom cereal import car, log\nfrom common.numpy_fast import clip\nfrom common.realtime import sec_since_boot, config_realtime_process, Priority, Ratekeeper, DT_CTRL\nfrom common.profiler import Profiler\nfrom common.params import Params, put_nonblocking\nimport cereal.messaging as messaging\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.boardd.boardd import can_list_to_can_capnp\nfrom selfdrive.car.car_helpers import get_car, get_startup_event, get_one_can\nfrom selfdrive.controls.lib.lane_planner import CAMERA_OFFSET\nfrom selfdrive.controls.lib.drive_helpers import update_v_cruise, initialize_v_cruise\nfrom selfdrive.controls.lib.drive_helpers import get_lag_adjusted_curvature\nfrom selfdrive.controls.lib.longcontrol import LongControl, STARTING_TARGET_SPEED\nfrom selfdrive.controls.lib.latcontrol_pid import LatControlPID\nfrom selfdrive.controls.lib.latcontrol_indi import LatControlINDI\nfrom selfdrive.controls.lib.latcontrol_lqr import LatControlLQR\nfrom selfdrive.controls.lib.latcontrol_angle import LatControlAngle\nfrom selfdrive.controls.lib.events import Events, ET\nfrom selfdrive.controls.lib.alertmanager import AlertManager\nfrom selfdrive.controls.lib.vehicle_model import VehicleModel\nfrom selfdrive.locationd.calibrationd import Calibration\nfrom selfdrive.hardware import HARDWARE, TICI, EON, JETSON\nfrom selfdrive.manager.process_config import managed_processes\n\nLDW_MIN_SPEED = 31 * CV.MPH_TO_MS\nLANE_DEPARTURE_THRESHOLD = 0.1\nSTEER_ANGLE_SATURATION_TIMEOUT = 1.0 / DT_CTRL\nSTEER_ANGLE_SATURATION_THRESHOLD = 2.5  # Degrees\n\nSIMULATION = \"SIMULATION\" in os.environ\nNOSENSOR = \"NOSENSOR\" in os.environ\nIGNORE_PROCESSES = {\"rtshield\", \"uploader\", \"deleter\", \"loggerd\", \"logmessaged\", \"tombstoned\",\n                    \"logcatd\", \"proclogd\", \"clocksd\", \"updated\", \"timezoned\", \"manage_athenad\", \"dragonConf\"} | \\\n                    {k for k, v in managed_processes.items() if not v.enabled}\n\nACTUATOR_FIELDS = set(car.CarControl.Actuators.schema.fields.keys())\n\nThermalStatus = log.DeviceState.ThermalStatus\nState = log.ControlsState.OpenpilotState\nPandaType = log.PandaState.PandaType\nDesire = log.LateralPlan.Desire\nLaneChangeState = log.LateralPlan.LaneChangeState\nLaneChangeDirection = log.LateralPlan.LaneChangeDirection\nEventName = car.CarEvent.EventName\n\n\nclass Controls:\n  def __init__(self, sm=None, pm=None, can_sock=None):\n    params = Params()\n    self.dp_jetson = params.get_bool('dp_jetson')\n    self.dp_lexus_rx_rpm_fix = params.get_bool('dp_lexus_rx_rpm_fix')\n    config_realtime_process(4 if TICI else 3, Priority.CTRL_HIGH)\n\n    # Setup sockets\n    self.pm = pm\n    if self.pm is None:\n      self.pm = messaging.PubMaster(['sendcan', 'controlsState', 'carState',\n                                     'carControl', 'carEvents', 'carParams'])\n\n    self.camera_packets = [\"roadCameraState\", \"driverCameraState\"]\n    if TICI:\n      self.camera_packets.append(\"wideRoadCameraState\")\n\n    params = Params()\n    self.joystick_mode = params.get_bool(\"JoystickDebugMode\")\n    joystick_packet = ['testJoystick'] if self.joystick_mode else []\n\n    self.sm = sm\n    if self.sm is None:\n      ignore = ['driverCameraState', 'managerState'] if SIMULATION else None\n      if self.dp_jetson:\n        ignore = ['driverCameraState', 'driverMonitoringState'] if ignore is None else ignore + ['driverCameraState', 'driverMonitoringState']\n      self.sm = messaging.SubMaster(['deviceState', 'pandaState', 'modelV2', 'liveCalibration',\n                                     'driverMonitoringState', 'longitudinalPlan', 'lateralPlan', 'liveLocationKalman',\n                                     'managerState', 'liveParameters', 'radarState', 'dragonConf'] + self.camera_packets + joystick_packet,\n                                     ignore_alive=ignore, ignore_avg_freq=['radarState', 'longitudinalPlan'])\n\n    self.can_sock = can_sock\n    if can_sock is None:\n      can_timeout = None if os.environ.get('NO_CAN_TIMEOUT', False) else 100\n      self.can_sock = messaging.sub_sock('can', timeout=can_timeout)\n\n    if TICI:\n      self.log_sock = messaging.sub_sock('androidLog')\n\n    # wait for one pandaState and one CAN packet\n    print(\"Waiting for CAN messages...\")\n    get_one_can(self.can_sock)\n\n    self.CI, self.CP = get_car(self.can_sock, self.pm.sock['sendcan'])\n\n    # read params\n    self.is_metric = params.get_bool(\"IsMetric\")\n    self.is_ldw_enabled = params.get_bool(\"IsLdwEnabled\")\n    community_feature_toggle = params.get_bool(\"CommunityFeaturesToggle\")\n    openpilot_enabled_toggle = params.get_bool(\"OpenpilotEnabledToggle\")\n    passive = params.get_bool(\"Passive\") or not openpilot_enabled_toggle\n\n    # detect sound card presence and ensure successful init\n    sounds_available = HARDWARE.get_sound_card_online()\n\n    car_recognized = self.CP.carName != 'mock'\n\n    controller_available = self.CI.CC is not None and not passive and not self.CP.dashcamOnly\n    community_feature = self.CP.communityFeature or \\\n                        self.CP.fingerprintSource == car.CarParams.FingerprintSource.can\n    community_feature_disallowed = community_feature and (not community_feature_toggle)\n    self.read_only = not car_recognized or not controller_available or \\\n                       self.CP.dashcamOnly or community_feature_disallowed\n    if self.read_only:\n      self.CP.safetyModel = car.CarParams.SafetyModel.noOutput\n\n    # Write CarParams for radard\n    cp_bytes = self.CP.to_bytes()\n    params.put(\"CarParams\", cp_bytes)\n    put_nonblocking(\"CarParamsCache\", cp_bytes)\n\n    self.CC = car.CarControl.new_message()\n    self.AM = AlertManager()\n    self.events = Events()\n\n    self.LoC = LongControl(self.CP)\n    self.VM = VehicleModel(self.CP)\n\n    if params.get_bool('dp_lqr'):\n      self.LaC = LatControlLQR(self.CP)\n    elif self.CP.steerControlType == car.CarParams.SteerControlType.angle:\n      self.LaC = LatControlAngle(self.CP)\n    elif self.CP.lateralTuning.which() == 'pid':\n      self.LaC = LatControlPID(self.CP)\n    elif self.CP.lateralTuning.which() == 'indi':\n      self.LaC = LatControlINDI(self.CP)\n    elif self.CP.lateralTuning.which() == 'lqr':\n      self.LaC = LatControlLQR(self.CP)\n\n    self.initialized = False\n    self.state = State.disabled\n    self.enabled = False\n    self.active = False\n    self.can_rcv_error = False\n    self.soft_disable_timer = 0\n    self.v_cruise_kph = 255\n    self.v_cruise_kph_last = 0\n    self.mismatch_counter = 0\n    self.can_error_counter = 0\n    self.last_blinker_frame = 0\n    self.saturated_count = 0\n    self.distance_traveled = 0\n    self.last_functional_fan_frame = 0\n    self.events_prev = []\n    self.current_alert_types = [ET.PERMANENT]\n    self.logged_comm_issue = False\n    self.v_target = 0.0\n    self.a_target = 0.0\n\n    self.led_state = False\n    self.led_state_prev = False\n\n    # TODO: no longer necessary, aside from process replay\n    self.sm['liveParameters'].valid = True\n\n    self.startup_event = get_startup_event(car_recognized, controller_available, self.CP.fuzzyFingerprint,\n                                           len(self.CP.carFw) > 0)\n\n    # if not sounds_available:\n    #   self.events.add(EventName.soundsUnavailable, static=True)\n    if community_feature_disallowed and car_recognized and not self.CP.dashcamOnly:\n      self.events.add(EventName.communityFeatureDisallowed, static=True)\n    if not car_recognized:\n      self.events.add(EventName.carUnrecognized, static=True)\n    elif self.read_only:\n      self.events.add(EventName.dashcamMode, static=True)\n    elif self.joystick_mode:\n      self.events.add(EventName.joystickDebug, static=True)\n      self.startup_event = None\n\n    # controlsd is driven by can recv, expected at 100Hz\n    self.rk = Ratekeeper(100, print_delay_threshold=None)\n    self.prof = Profiler(False)  # off by default\n\n    # dp\n    self.sm['dragonConf'].dpAtl = False\n    self.sm['dragonConf'].dpSrCustom = self.CP.steerRatio\n    self.sm['dragonConf'].dpSrLearner = True\n\n  def update_events(self, CS):\n    \"\"\"Compute carEvents from carState\"\"\"\n\n    self.events.clear()\n    self.events.add_from_msg(CS.events)\n    if not self.dp_jetson:\n      self.events.add_from_msg(self.sm['driverMonitoringState'].events)\n    self.events.add_from_msg(self.sm['longitudinalPlan'].eventsDEPRECATED)\n\n    # Handle startup event\n    if self.startup_event is not None:\n      self.events.add(self.startup_event)\n      self.startup_event = None\n\n    # Don't add any more events if not initialized\n    if not self.initialized:\n      self.events.add(EventName.controlsInitializing)\n      return\n\n    # Create events for battery, temperature, disk space, and memory\n    # if self.sm['deviceState'].batteryPercent < 1 and self.sm['deviceState'].chargingError:\n    #   # at zero percent battery, while discharging, OP should not allowed\n    #   self.events.add(EventName.lowBattery)\n    if self.sm['deviceState'].thermalStatus >= ThermalStatus.red:\n      self.events.add(EventName.overheat)\n    if self.sm['deviceState'].freeSpacePercent < 7 and not SIMULATION:\n      # under 7% of space free no enable allowed\n      self.events.add(EventName.outOfSpace)\n    # TODO: make tici threshold the same\n    if self.sm['deviceState'].memoryUsagePercent > (90 if TICI or JETSON else 65) and not SIMULATION:\n      self.events.add(EventName.lowMemory)\n    cpus = list(self.sm['deviceState'].cpuUsagePercent)[:(-1 if EON else None)]\n    if max(cpus, default=0) > 95 and not SIMULATION:\n      self.events.add(EventName.highCpuUsage)\n\n    # Alert if fan isn't spinning for 5 seconds\n    if self.sm['pandaState'].pandaType in [PandaType.uno, PandaType.dos]:\n      if self.sm['pandaState'].fanSpeedRpm == 0 and self.sm['deviceState'].fanSpeedPercentDesired > 50:\n        if (self.sm.frame - self.last_functional_fan_frame) * DT_CTRL > 5.0:\n          self.events.add(EventName.fanMalfunction)\n      else:\n        self.last_functional_fan_frame = self.sm.frame\n\n    # Handle calibration status\n    cal_status = self.sm['liveCalibration'].calStatus\n    if cal_status != Calibration.CALIBRATED:\n      if cal_status == Calibration.UNCALIBRATED:\n        self.events.add(EventName.calibrationIncomplete)\n      else:\n        self.events.add(EventName.calibrationInvalid)\n\n    # Handle lane change\n    if self.sm['lateralPlan'].laneChangeState == LaneChangeState.preLaneChange:\n      direction = self.sm['lateralPlan'].laneChangeDirection\n      if (CS.leftBlindspot and direction == LaneChangeDirection.left) or \\\n         (CS.rightBlindspot and direction == LaneChangeDirection.right):\n        self.events.add(EventName.laneChangeBlocked)\n      elif self.sm['lateralPlan'].dpALCAStartIn > 0:\n        self.events.add(EventName.autoLaneChange)\n      else:\n        if direction == LaneChangeDirection.left:\n          self.events.add(EventName.preLaneChangeLeft)\n        else:\n          self.events.add(EventName.preLaneChangeRight)\n    elif self.sm['lateralPlan'].laneChangeState in [LaneChangeState.laneChangeStarting,\n                                                 LaneChangeState.laneChangeFinishing]:\n      self.events.add(EventName.laneChange)\n\n    if self.can_rcv_error or not CS.canValid:\n      self.events.add(EventName.pcmDisable if self.sm['dragonConf'].dpAtl else EventName.canError)\n\n    safety_mismatch = self.sm['pandaState'].safetyModel != self.CP.safetyModel or self.sm['pandaState'].safetyParam != self.CP.safetyParam\n    if safety_mismatch or self.mismatch_counter >= 200:\n      self.events.add(EventName.controlsMismatch)\n\n    if not self.sm['liveParameters'].valid:\n      self.events.add(EventName.vehicleModelInvalid)\n\n    if len(self.sm['radarState'].radarErrors):\n      self.events.add(EventName.radarFault)\n    elif not self.sm.valid[\"pandaState\"]:\n      self.events.add(EventName.usbError)\n    elif not self.dp_jetson and not self.sm.all_alive_and_valid():\n      self.events.add(EventName.commIssue)\n      if not self.logged_comm_issue:\n        invalid = [s for s, valid in self.sm.valid.items() if not valid]\n        not_alive = [s for s, alive in self.sm.alive.items() if not alive]\n        cloudlog.event(\"commIssue\", invalid=invalid, not_alive=not_alive)\n        self.logged_comm_issue = True\n    else:\n      self.logged_comm_issue = False\n\n    if not self.sm['lateralPlan'].mpcSolutionValid:\n      self.events.add(EventName.steerTempUnavailable if self.sm['dragonConf'].dpAtl else EventName.plannerError)\n    if not self.sm['liveLocationKalman'].sensorsOK and not NOSENSOR:\n      if self.sm.frame > 5 / DT_CTRL:  # Give locationd some time to receive all the inputs\n        self.events.add(EventName.sensorDataInvalid)\n    if not self.sm['liveLocationKalman'].posenetOK:\n      self.events.add(EventName.posenetInvalid)\n    if not self.sm['liveLocationKalman'].deviceStable:\n      self.events.add(EventName.deviceFalling)\n    if log.PandaState.FaultType.relayMalfunction in self.sm['pandaState'].faults:\n      self.events.add(EventName.relayMalfunction)\n    if self.sm['longitudinalPlan'].fcw or (self.enabled and self.sm['modelV2'].meta.hardBrakePredicted):\n      self.events.add(EventName.fcw)\n\n    if TICI:\n      logs = messaging.drain_sock(self.log_sock, wait_for_one=False)\n      messages = []\n      for m in logs:\n        try:\n          messages.append(m.androidLog.message)\n        except UnicodeDecodeError:\n          pass\n\n      for err in [\"ERROR_CRC\", \"ERROR_ECC\", \"ERROR_STREAM_UNDERFLOW\", \"APPLY FAILED\"]:\n        for m in messages:\n          if err not in m:\n            continue\n\n          csid = m.split(\"CSID:\")[-1].split(\" \")[0]\n          evt = {\"0\": EventName.roadCameraError, \"1\": EventName.wideRoadCameraError,\n                 \"2\": EventName.driverCameraError}.get(csid, None)\n          if evt is not None:\n            self.events.add(evt)\n\n    # TODO: fix simulator\n    if not SIMULATION:\n      # if not NOSENSOR:\n      #   if not self.sm['liveLocationKalman'].gpsOK and (self.distance_traveled > 1000):\n      #     # Not show in first 1 km to allow for driving out of garage. This event shows after 5 minutes\n      #     self.events.add(EventName.noGps)\n      if not self.dp_jetson and not self.sm.all_alive(self.camera_packets):\n        self.events.add(EventName.cameraMalfunction)\n      if self.sm['modelV2'].frameDropPerc > 20:\n        self.events.add(EventName.modeldLagging)\n      if self.sm['liveLocationKalman'].excessiveResets:\n        self.events.add(EventName.localizerMalfunction)\n\n      # Check if all manager processes are running\n      # not_running = set(p.name for p in self.sm['managerState'].processes if not p.running)\n      # if self.sm.rcv_frame['managerState'] and (not_running - IGNORE_PROCESSES):\n      #   self.events.add(EventName.processNotRunning)\n\n    # Only allow engagement with brake pressed when stopped behind another stopped car\n    speeds = self.sm['longitudinalPlan'].speeds\n    if len(speeds) > 1:\n      v_future = speeds[-1]\n    else:\n      v_future = 100.0\n    if not self.sm['dragonConf'].dpAtl and CS.brakePressed and v_future >= STARTING_TARGET_SPEED \\\n      and self.CP.openpilotLongitudinalControl and CS.vEgo < 0.3:\n      self.events.add(EventName.noTarget)\n\n  def data_sample(self):\n    \"\"\"Receive data from sockets and update carState\"\"\"\n\n    # Update carState from CAN\n    can_strs = messaging.drain_sock_raw(self.can_sock, wait_for_one=True)\n    CS = self.CI.update(self.CC, can_strs, self.sm['dragonConf'])\n\n    self.sm.update(0)\n\n    all_valid = CS.canValid and self.sm.all_alive_and_valid()\n    if not self.initialized and (all_valid or self.sm.frame * DT_CTRL > 3.5 or SIMULATION):\n      self.CI.init(self.CP, self.can_sock, self.pm.sock['sendcan'])\n      self.initialized = True\n      Params().put_bool(\"ControlsReady\", True)\n\n    # Check for CAN timeout\n    if not can_strs:\n      self.can_error_counter += 1\n      self.can_rcv_error = True\n    else:\n      self.can_rcv_error = False\n\n    # When the panda and controlsd do not agree on controls_allowed\n    # we want to disengage openpilot. However the status from the panda goes through\n    # another socket other than the CAN messages and one can arrive earlier than the other.\n    # Therefore we allow a mismatch for two samples, then we trigger the disengagement.\n    if not self.enabled:\n      self.mismatch_counter = 0\n\n    if not self.sm['dragonConf'].dpAtl and not self.sm['pandaState'].controlsAllowed and self.enabled:\n      self.mismatch_counter += 1\n\n    self.distance_traveled += CS.vEgo * DT_CTRL\n\n    return CS\n\n  def state_transition(self, CS):\n    \"\"\"Compute conditional state transitions and execute actions on state transitions\"\"\"\n\n    self.v_cruise_kph_last = self.v_cruise_kph\n\n    # if stock cruise is completely disabled, then we can use our own set speed logic\n    if not self.CP.pcmCruise:\n      self.v_cruise_kph = update_v_cruise(self.v_cruise_kph, CS.buttonEvents, self.enabled)\n    elif self.CP.pcmCruise and CS.cruiseState.enabled:\n      self.v_cruise_kph = CS.cruiseState.speed * CV.MS_TO_KPH\n\n    # decrease the soft disable timer at every step, as it's reset on\n    # entrance in SOFT_DISABLING state\n    self.soft_disable_timer = max(0, self.soft_disable_timer - 1)\n\n    self.current_alert_types = [ET.PERMANENT]\n\n    # ENABLED, PRE ENABLING, SOFT DISABLING\n    if self.state != State.disabled:\n      # user and immediate disable always have priority in a non-disabled state\n      if self.events.any(ET.USER_DISABLE):\n        self.state = State.disabled\n        self.current_alert_types.append(ET.USER_DISABLE)\n\n      elif self.events.any(ET.IMMEDIATE_DISABLE):\n        self.state = State.disabled\n        self.current_alert_types.append(ET.IMMEDIATE_DISABLE)\n\n      else:\n        # ENABLED\n        if self.state == State.enabled:\n          if self.events.any(ET.SOFT_DISABLE):\n            self.state = State.softDisabling\n            self.soft_disable_timer = 300   # 3s\n            self.current_alert_types.append(ET.SOFT_DISABLE)\n\n        # SOFT DISABLING\n        elif self.state == State.softDisabling:\n          if not self.events.any(ET.SOFT_DISABLE):\n            # no more soft disabling condition, so go back to ENABLED\n            self.state = State.enabled\n\n          elif self.events.any(ET.SOFT_DISABLE) and self.soft_disable_timer > 0:\n            self.current_alert_types.append(ET.SOFT_DISABLE)\n\n          elif self.soft_disable_timer <= 0:\n            self.state = State.disabled\n\n        # PRE ENABLING\n        elif self.state == State.preEnabled:\n          if not self.events.any(ET.PRE_ENABLE):\n            self.state = State.enabled\n          else:\n            self.current_alert_types.append(ET.PRE_ENABLE)\n\n    # DISABLED\n    elif self.state == State.disabled:\n      if self.events.any(ET.ENABLE):\n        if self.events.any(ET.NO_ENTRY):\n          self.current_alert_types.append(ET.NO_ENTRY)\n\n        else:\n          if self.events.any(ET.PRE_ENABLE):\n            self.state = State.preEnabled\n          else:\n            self.state = State.enabled\n          self.current_alert_types.append(ET.ENABLE)\n          self.v_cruise_kph = initialize_v_cruise(CS.vEgo, CS.buttonEvents, self.v_cruise_kph_last)\n\n    # Check if actuators are enabled\n    self.active = self.state == State.enabled or self.state == State.softDisabling\n    if self.active:\n      self.current_alert_types.append(ET.WARNING)\n\n    # Check if openpilot is engaged\n    self.enabled = self.active or self.state == State.preEnabled\n\n  def state_control(self, CS):\n    \"\"\"Given the state, this function returns an actuators packet\"\"\"\n\n    # Update VehicleModel\n    params = self.sm['liveParameters']\n    x = max(params.stiffnessFactor, 0.1)\n    sr = max(params.steerRatio, 0.1)\n    if not self.sm['dragonConf'].dpSrLearner:\n      if self.sm['dragonConf'].dpSrCustom >= 10:\n        sr = self.sm['dragonConf'].dpSrCustom\n      else:\n        sr = self.CP.steerRatio\n    self.VM.update_params(x, sr)\n\n    lat_plan = self.sm['lateralPlan']\n    long_plan = self.sm['longitudinalPlan']\n\n    actuators = car.CarControl.Actuators.new_message()\n    actuators.longControlState = self.LoC.long_control_state\n\n    if CS.leftBlinker or CS.rightBlinker:\n      self.last_blinker_frame = self.sm.frame\n\n    # State specific actions\n\n    if not self.active:\n      self.LaC.reset()\n      self.LoC.reset(v_pid=CS.vEgo)\n\n    if not self.joystick_mode:\n      # accel PID loop\n      pid_accel_limits = self.CI.get_pid_accel_limits(self.CP, CS.vEgo, self.v_cruise_kph * CV.KPH_TO_MS)\n      actuators.accel, self.v_target, self.a_target = self.LoC.update(self.active, CS, self.CP, long_plan, pid_accel_limits)\n\n      # Steering PID loop and lateral MPC\n      desired_curvature, desired_curvature_rate = get_lag_adjusted_curvature(self.CP, CS.vEgo,\n                                                                             lat_plan.psis,\n                                                                             lat_plan.curvatures,\n                                                                             lat_plan.curvatureRates)\n      actuators.steer, actuators.steeringAngleDeg, lac_log = self.LaC.update(self.active, CS, self.CP, self.VM, params,\n                                                                             desired_curvature, desired_curvature_rate)\n    else:\n      lac_log = log.ControlsState.LateralDebugState.new_message()\n      if self.sm.rcv_frame['testJoystick'] > 0 and self.active:\n        actuators.accel = 4.0*clip(self.sm['testJoystick'].axes[0], -1, 1)\n\n        steer = clip(self.sm['testJoystick'].axes[1], -1, 1)\n        # max angle is 45 for angle-based cars\n        actuators.steer, actuators.steeringAngleDeg = steer, steer * 45.\n\n        lac_log.active = True\n        lac_log.steeringAngleDeg = CS.steeringAngleDeg\n        lac_log.output = steer\n        lac_log.saturated = abs(steer) >= 0.9\n\n    # Check for difference between desired angle and angle for angle based control\n    angle_control_saturated = self.CP.steerControlType == car.CarParams.SteerControlType.angle and \\\n      abs(actuators.steeringAngleDeg - CS.steeringAngleDeg) > STEER_ANGLE_SATURATION_THRESHOLD\n\n    if angle_control_saturated and not CS.steeringPressed and self.active:\n      self.saturated_count += 1\n    else:\n      self.saturated_count = 0\n\n    # Send a \"steering required alert\" if saturation count has reached the limit\n    if (lac_log.saturated and not CS.steeringPressed) or \\\n       (self.saturated_count > STEER_ANGLE_SATURATION_TIMEOUT):\n\n      if len(lat_plan.dPathPoints):\n        # Check if we deviated from the path\n        left_deviation = actuators.steer > 0 and lat_plan.dPathPoints[0] < -0.1\n        right_deviation = actuators.steer < 0 and lat_plan.dPathPoints[0] > 0.1\n\n        if left_deviation or right_deviation:\n          self.events.add(EventName.steerSaturated)\n\n    # Ensure no NaNs/Infs\n    for p in ACTUATOR_FIELDS:\n      attr = getattr(actuators, p)\n      if not isinstance(attr, Number):\n        continue\n\n      if not math.isfinite(attr):\n        cloudlog.error(f\"actuators.{p} not finite {actuators.to_dict()}\")\n        setattr(actuators, p, 0.0)\n\n    return actuators, lac_log\n\n  def publish_logs(self, CS, start_time, actuators, lac_log):\n    \"\"\"Send actuators and hud commands to the car, send controlsstate and MPC logging\"\"\"\n\n    CC = car.CarControl.new_message()\n    CC.enabled = self.enabled\n    CC.actuators = actuators\n\n    CC.cruiseControl.override = True\n    CC.cruiseControl.cancel = not self.CP.pcmCruise or (not self.enabled and CS.cruiseState.enabled)\n    if self.joystick_mode and self.sm.rcv_frame['testJoystick'] > 0 and self.sm['testJoystick'].buttons[0]:\n      CC.cruiseControl.cancel = True\n\n    # TODO remove car specific stuff in controls\n    # Some override values for Honda\n    # brake discount removes a sharp nonlinearity\n    brake_discount = (1.0 - clip(-actuators.accel * (3.0/4.0), 0.0, 1.0))\n    speed_override = max(0.0, (self.LoC.v_pid + CS.cruiseState.speedOffset) * brake_discount)\n    CC.cruiseControl.speedOverride = float(speed_override if self.CP.pcmCruise else 0.0)\n    CC.cruiseControl.accelOverride = float(self.CI.calc_accel_override(CS.aEgo, self.a_target,\n                                                                       CS.vEgo, self.v_target))\n\n    CC.hudControl.setSpeed = float(self.v_cruise_kph * CV.KPH_TO_MS)\n    CC.hudControl.speedVisible = self.enabled\n    CC.hudControl.lanesVisible = self.enabled\n    CC.hudControl.leadVisible = self.sm['longitudinalPlan'].hasLead\n\n    right_lane_visible = self.sm['lateralPlan'].rProb > 0.5\n    left_lane_visible = self.sm['lateralPlan'].lProb > 0.5\n    CC.hudControl.rightLaneVisible = bool(right_lane_visible)\n    CC.hudControl.leftLaneVisible = bool(left_lane_visible)\n\n    recent_blinker = (self.sm.frame - self.last_blinker_frame) * DT_CTRL < 5.0  # 5s blinker cooldown\n    ldw_allowed = self.is_ldw_enabled and CS.vEgo > LDW_MIN_SPEED and not recent_blinker \\\n                    and not self.active and self.sm['liveCalibration'].calStatus == Calibration.CALIBRATED\n\n    meta = self.sm['modelV2'].meta\n    if len(meta.desirePrediction) and ldw_allowed:\n      l_lane_change_prob = meta.desirePrediction[Desire.laneChangeLeft - 1]\n      r_lane_change_prob = meta.desirePrediction[Desire.laneChangeRight - 1]\n      l_lane_close = left_lane_visible and (self.sm['modelV2'].laneLines[1].y[0] > -(1.08 + CAMERA_OFFSET))\n      r_lane_close = right_lane_visible and (self.sm['modelV2'].laneLines[2].y[0] < (1.08 - CAMERA_OFFSET))\n\n      CC.hudControl.leftLaneDepart = bool(l_lane_change_prob > LANE_DEPARTURE_THRESHOLD and l_lane_close)\n      CC.hudControl.rightLaneDepart = bool(r_lane_change_prob > LANE_DEPARTURE_THRESHOLD and r_lane_close)\n\n    if CC.hudControl.rightLaneDepart or CC.hudControl.leftLaneDepart:\n      self.events.add(EventName.ldw)\n\n    clear_event = ET.WARNING if ET.WARNING not in self.current_alert_types else None\n    alerts = self.events.create_alerts(self.current_alert_types, [self.CP, self.sm, self.is_metric])\n    self.AM.add_many(self.sm.frame, alerts, self.enabled)\n    self.AM.process_alerts(self.sm.frame, clear_event)\n    CC.hudControl.visualAlert = self.AM.visual_alert\n\n    if not self.read_only and self.initialized:\n      # send car controls over can\n      can_sends = self.CI.apply(CC)\n      self.pm.send('sendcan', can_list_to_can_capnp(can_sends, msgtype='sendcan', valid=CS.canValid))\n\n    force_decel = False if self.dp_jetson else (self.sm['driverMonitoringState'].awarenessStatus < 0.) or \\\n                    (self.state == State.softDisabling)\n\n    # Curvature & Steering angle\n    params = self.sm['liveParameters']\n    steer_angle_without_offset = math.radians(CS.steeringAngleDeg - params.angleOffsetAverageDeg)\n    curvature = -self.VM.calc_curvature(steer_angle_without_offset, CS.vEgo)\n\n    # controlsState\n    dat = messaging.new_message('controlsState')\n    dat.valid = CS.canValid\n    controlsState = dat.controlsState\n    controlsState.alertText1 = self.AM.alert_text_1\n    controlsState.alertText2 = self.AM.alert_text_2\n    controlsState.alertSize = self.AM.alert_size\n    controlsState.alertStatus = self.AM.alert_status\n    controlsState.alertBlinkingRate = self.AM.alert_rate\n    controlsState.alertType = self.AM.alert_type\n    controlsState.alertSound = self.AM.audible_alert\n    controlsState.canMonoTimes = list(CS.canMonoTimes)\n    controlsState.longitudinalPlanMonoTime = self.sm.logMonoTime['longitudinalPlan']\n    controlsState.lateralPlanMonoTime = self.sm.logMonoTime['lateralPlan']\n    controlsState.enabled = self.enabled\n    controlsState.active = self.active\n    controlsState.curvature = curvature\n    controlsState.state = self.state\n    controlsState.engageable = not self.events.any(ET.NO_ENTRY)\n    controlsState.longControlState = self.LoC.long_control_state\n    controlsState.vPid = float(self.LoC.v_pid)\n    controlsState.vCruise = float(self.v_cruise_kph)\n    controlsState.upAccelCmd = float(self.LoC.pid.p)\n    controlsState.uiAccelCmd = float(self.LoC.pid.i)\n    controlsState.ufAccelCmd = float(self.LoC.pid.f)\n    controlsState.cumLagMs = -self.rk.remaining * 1000.\n    controlsState.startMonoTime = int(start_time * 1e9)\n    controlsState.forceDecel = bool(force_decel)\n    controlsState.canErrorCounter = self.can_error_counter\n\n    # dp - RX Patch: https://github.com/LexusRXopenpilotUG/openpilot\n    if self.dp_lexus_rx_rpm_fix:\n      # Hack for reasonable gears/reasonable RPMs on Lexus RX. No upstreaming!\n      # Setting speed may be iffy still\n      if self.v_cruise_kph != 255:\n        controlsState.vCruise = controlsState.vCruise * 0.974\n    # dp - for ui\n    controlsState.angleSteers = CS.steeringAngleDeg\n    controlsState.steeringAngleDesiredDeg = actuators.steeringAngleDeg\n\n    if self.joystick_mode:\n      controlsState.lateralControlState.debugState = lac_log\n    elif self.CP.steerControlType == car.CarParams.SteerControlType.angle:\n      controlsState.lateralControlState.angleState = lac_log\n    elif self.CP.lateralTuning.which() == 'pid':\n      controlsState.lateralControlState.pidState = lac_log\n    elif self.CP.lateralTuning.which() == 'lqr':\n      controlsState.lateralControlState.lqrState = lac_log\n    elif self.CP.lateralTuning.which() == 'indi':\n      controlsState.lateralControlState.indiState = lac_log\n    self.pm.send('controlsState', dat)\n\n    # carState\n    car_events = self.events.to_msg()\n    cs_send = messaging.new_message('carState')\n    cs_send.valid = CS.canValid\n    cs_send.carState = CS\n    cs_send.carState.events = car_events\n    self.pm.send('carState', cs_send)\n\n    # carEvents - logged every second or on change\n    if (self.sm.frame % int(1. / DT_CTRL) == 0) or (self.events.names != self.events_prev):\n      ce_send = messaging.new_message('carEvents', len(self.events))\n      ce_send.carEvents = car_events\n      self.pm.send('carEvents', ce_send)\n    self.events_prev = self.events.names.copy()\n\n    # carParams - logged every 50 seconds (> 1 per segment)\n    if (self.sm.frame % int(50. / DT_CTRL) == 0):\n      cp_send = messaging.new_message('carParams')\n      cp_send.carParams = self.CP\n      self.pm.send('carParams', cp_send)\n\n    # carControl\n    cc_send = messaging.new_message('carControl')\n    cc_send.valid = CS.canValid\n    cc_send.carControl = CC\n    self.pm.send('carControl', cc_send)\n\n    # copy CarControl to pass to CarInterface on the next iteration\n    self.CC = CC\n\n  def step(self):\n    start_time = sec_since_boot()\n    self.prof.checkpoint(\"Ratekeeper\", ignore=True)\n\n    # Sample data from sockets and get a carState\n    CS = self.data_sample()\n    self.prof.checkpoint(\"Sample\")\n\n    self.update_events(CS)\n\n    if not self.read_only and self.initialized:\n      # Update control state\n      self.state_transition(CS)\n      self.prof.checkpoint(\"State transition\")\n\n    # Compute actuators (runs PID loops and lateral MPC)\n    actuators, lac_log = self.state_control(CS)\n\n    self.prof.checkpoint(\"State Control\")\n\n    # Publish data\n    self.publish_logs(CS, start_time, actuators, lac_log)\n    self.prof.checkpoint(\"Sent\")\n\n  def controlsd_thread(self):\n    while True:\n      self.step()\n      self.rk.monitor_time()\n      self.prof.display()\n\ndef main(sm=None, pm=None, logcan=None):\n  controls = Controls(sm, pm, logcan)\n  controls.controlsd_thread()\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/controls/lib/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/controls/lib/alertmanager.py",
    "content": "import os\nimport copy\nimport json\nfrom typing import List, Optional\n\nfrom cereal import car, log\nfrom common.basedir import BASEDIR\nfrom common.params import Params\nfrom common.realtime import DT_CTRL\nfrom selfdrive.controls.lib.events import Alert\nfrom selfdrive.swaglog import cloudlog\n\n\nwith open(os.path.join(BASEDIR, \"selfdrive/controls/lib/alerts_offroad.json\")) as f:\n  OFFROAD_ALERTS = json.load(f)\n\n\ndef set_offroad_alert(alert: str, show_alert: bool, extra_text: Optional[str] = None) -> None:\n  if show_alert:\n    a = OFFROAD_ALERTS[alert]\n    if extra_text is not None:\n      a = copy.copy(OFFROAD_ALERTS[alert])\n      a['text'] += extra_text\n    Params().put(alert, json.dumps(a))\n  else:\n    Params().delete(alert)\n\n\nclass AlertManager:\n\n  def __init__(self):\n    self.activealerts: List[Alert] = []\n    self.clear_current_alert()\n\n  def clear_current_alert(self) -> None:\n    self.alert_type: str = \"\"\n    self.alert_text_1: str = \"\"\n    self.alert_text_2: str = \"\"\n    self.alert_status = log.ControlsState.AlertStatus.normal\n    self.alert_size = log.ControlsState.AlertSize.none\n    self.visual_alert = car.CarControl.HUDControl.VisualAlert.none\n    self.audible_alert = car.CarControl.HUDControl.AudibleAlert.none\n    self.alert_rate: float = 0.\n\n  def add_many(self, frame: int, alerts: List[Alert], enabled: bool = True) -> None:\n    for alert in alerts:\n      added_alert = copy.copy(alert)\n      added_alert.start_time = frame * DT_CTRL\n\n      # if new alert is higher priority, log it\n      if not len(self.activealerts) or added_alert.alert_priority > self.activealerts[0].alert_priority:\n        cloudlog.event('alert_add', alert_type=added_alert.alert_type, enabled=enabled)\n\n      self.activealerts.append(added_alert)\n\n  def process_alerts(self, frame: int, clear_event_type=None) -> None:\n    cur_time = frame * DT_CTRL\n\n    # first get rid of all the expired alerts\n    self.activealerts = [a for a in self.activealerts if a.event_type != clear_event_type and\n                         a.start_time + max(a.duration_sound, a.duration_hud_alert, a.duration_text) > cur_time]\n\n    # sort by priority first and then by start_time\n    self.activealerts.sort(key=lambda k: (k.alert_priority, k.start_time), reverse=True)\n\n    # start with assuming no alerts\n    self.clear_current_alert()\n\n    if len(self.activealerts):\n      current_alert = self.activealerts[0]\n\n      self.alert_type = current_alert.alert_type\n\n      if current_alert.start_time + current_alert.duration_sound > cur_time:\n        self.audible_alert = current_alert.audible_alert\n\n      if current_alert.start_time + current_alert.duration_hud_alert > cur_time:\n        self.visual_alert = current_alert.visual_alert\n\n      if current_alert.start_time + current_alert.duration_text > cur_time:\n        self.alert_text_1 = current_alert.alert_text_1\n        self.alert_text_2 = current_alert.alert_text_2\n        self.alert_status = current_alert.alert_status\n        self.alert_size = current_alert.alert_size\n        self.alert_rate = current_alert.alert_rate\n"
  },
  {
    "path": "selfdrive/controls/lib/alerts_offroad.json",
    "content": "{\n  \"Offroad_ChargeDisabled\": {\n    \"text\": \"EON charging disabled after car being off for more than 30 hours. Turn ignition on to start charging again.\",\n    \"severity\": 0\n  },\n  \"Offroad_TemperatureTooHigh\": {\n    \"text\": \"Device temperature too high. System won't start.\",\n    \"severity\": 1\n  },\n  \"Offroad_ConnectivityNeededPrompt\": {\n    \"text\": \"Immediately connect to the internet to check for updates. If you do not connect to the internet, openpilot won't engage in \",\n    \"severity\": 0,\n    \"_comment\": \"Append the number of days at the end of the text\"\n  },\n  \"Offroad_ConnectivityNeeded\": {\n    \"text\": \"Connect to internet to check for updates. openpilot won't start until it connects to internet to check for updates.\",\n    \"severity\": 1\n  },\n  \"Offroad_UpdateFailed\": {\n    \"text\": \"Unable to download updates\\n\",\n    \"severity\": 1,\n    \"_comment\": \"Append the command and error to the text.\"\n  },\n  \"Offroad_PandaFirmwareMismatch\": {\n    \"text\": \"Unexpected panda firmware version. System won't start. Reboot your device to reflash panda.\",\n    \"severity\": 1\n  },\n  \"Offroad_InvalidTime\": {\n    \"text\": \"Invalid date and time settings, system won't start. Connect to internet to set time.\",\n    \"severity\": 1\n  },\n  \"Offroad_IsTakingSnapshot\": {\n    \"text\": \"Taking camera snapshots. System won't start until finished.\",\n    \"severity\": 0\n  },\n  \"Offroad_NeosUpdate\": {\n    \"text\": \"An update to your device's operating system is downloading in the background. You will be prompted to update when it's ready to install.\",\n    \"severity\": 0\n  },\n  \"Offroad_HardwareUnsupported\": {\n    \"text\": \"White and grey panda are unsupported. Upgrade to comma two or black panda.\",\n    \"severity\": 0\n  },\n  \"Offroad_UnofficialHardware\": {\n    \"text\": \"Device failed to register. It will not connect to or upload to comma.ai servers, and receives no support from comma.ai. If this is an official device, contact support@comma.ai.\",\n    \"severity\": 1\n  },\n  \"Offroad_NvmeMissing\": {\n    \"text\": \"NVME drive not mounted.\",\n    \"severity\": 1\n  }\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/LICENSE",
    "content": "﻿Copyright:\n  * fastcluster_dm.cpp & fastcluster_R_dm.cpp:\n     © 2011 Daniel Müllner <http://danifold.net>\n  * fastcluster.(h|cpp) & demo.cpp & plotresult.r:\n     © 2018 Christoph Dalitz <http://www.hsnr.de/ipattern/>\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.\n  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/README",
    "content": "C++ interface to fast hierarchical clustering algorithms\n========================================================\n\nThis is a simplified C++ interface to fast implementations of hierarchical\nclustering by Daniel Müllner. The original library with interfaces to R\nand Python is described in:\n\nDaniel Müllner: \"fastcluster: Fast Hierarchical, Agglomerative Clustering\nRoutines for R and Python.\" Journal of Statistical Software 53 (2013),\nno. 9, pp. 1–18, http://www.jstatsoft.org/v53/i09/\n\n\nUsage of the library\n--------------------\n\nFor using the library, the following source files are needed:\n\nfastcluster_dm.cpp, fastcluster_R_dm.cpp\n   original code by Daniel Müllner\n   these are included by fastcluster.cpp via #include, and therefore\n   need not be compiled to object code\n\nfastcluster.[h|cpp]\n   simplified C++ interface\n   fastcluster.cpp is the only file that must be compiled\n\nThe library provides the clustering function *hclust_fast* for\ncreating the dendrogram information in an encoding as used by the\nR function *hclust*. For a description of the parameters, see fastcluster.h.\nIts parameter *method* can be one of\n\nHCLUST_METHOD_SINGLE\n  single link with the minimum spanning tree algorithm (Rohlf, 1973)\n\nHHCLUST_METHOD_COMPLETE\n  complete link with the nearest-neighbor-chain algorithm (Murtagh, 1984)\n\nHCLUST_METHOD_AVERAGE\n  complete link with the nearest-neighbor-chain algorithm (Murtagh, 1984)\n\nHCLUST_METHOD_MEDIAN\n  median link with the generic algorithm (Müllner, 2011)\n\nFor splitting the dendrogram into clusters, the two functions *cutree_k*\nand *cutree_cdist* are provided.\n\nNote that output parameters must be allocated beforehand, e.g.\n  int* merge = new int[2*(npoints-1)];\nFor a complete usage example, see lines 135-142 of demo.cpp.\n\n\nDemonstration program\n---------------------\n\nA simple demo is implemented in demo.cpp, which can be compiled and run with\n\n   make\n   ./hclust-demo -m complete lines.csv\n\nIt creates two clusters of line segments such that the segment angle between\nline segments of different clusters have a maximum (cosine) dissimilarity.\nFor visualizing the result, plotresult.r can be used as follows\n(requires R <https://r-project.org> to be installed):\n\n  ./hclust-demo -m complete lines.csv | Rscript plotresult.r\n\n\nAuthors & Copyright\n-------------------\n\nDaniel Müllner, 2011, <http://danifold.net>\nChristoph Dalitz, 2018, <http://www.hsnr.de/ipattern/>\n\n\nLicense\n-------\n\nThis code is provided under a BSD-style license.\nSee the file LICENSE for details.\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/SConscript",
    "content": "Import('env')\n\nfc = env.SharedLibrary(\"fastcluster\", \"fastcluster.cpp\")\n\n# TODO: how do I gate on test\n#env.Program(\"test\", [\"test.cpp\"], LIBS=[fc])\n#valgrind --leak-check=full ./test\n\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/controls/lib/cluster/fastcluster.cpp",
    "content": "//\n// C++ standalone verion of fastcluster by Daniel Müllner\n//\n// Copyright: Christoph Dalitz, 2018\n//            Daniel Müllner, 2011\n// License:   BSD style license\n//            (see the file LICENSE for details)\n//\n\n\n#include <vector>\n#include <algorithm>\n#include <cmath>\n\n\nextern \"C\" {\n#include \"fastcluster.h\"\n}\n\n// Code by Daniel Müllner\n// workaround to make it usable as a standalone version (without R)\nbool fc_isnan(double x) { return false; }\n#include \"fastcluster_dm.cpp\"\n#include \"fastcluster_R_dm.cpp\"\n\nextern \"C\" {\n//\n// Assigns cluster labels (0, ..., nclust-1) to the n points such\n// that the cluster result is split into nclust clusters.\n//\n// Input arguments:\n//   n      = number of observables\n//   merge  = clustering result in R format\n//   nclust = number of clusters\n// Output arguments:\n//   labels = allocated integer array of size n for result\n//\n  void cutree_k(int n, const int* merge, int nclust, int* labels) {\n\n    int k,m1,m2,j,l;\n\n    if (nclust > n || nclust < 2) {\n      for (j=0; j<n; j++) labels[j] = 0;\n      return;\n    }\n\n    // assign to each observable the number of its last merge step\n    // beware: indices of observables in merge start at 1 (R convention)\n    std::vector<int> last_merge(n, 0);\n    for (k=1; k<=(n-nclust); k++) {\n      // (m1,m2) = merge[k,]\n      m1 = merge[k-1];\n      m2 = merge[n-1+k-1];\n      if (m1 < 0 && m2 < 0) { // both single observables\n        last_merge[-m1-1] = last_merge[-m2-1] = k;\n      }\n      else if (m1 < 0 || m2 < 0) { // one is a cluster\n        if(m1 < 0) { j = -m1; m1 = m2; } else j = -m2;\n        // merging single observable and cluster\n        for(l = 0; l < n; l++)\n          if (last_merge[l] == m1)\n            last_merge[l] = k;\n        last_merge[j-1] = k;\n      }\n      else { // both cluster\n        for(l=0; l < n; l++) {\n          if( last_merge[l] == m1 || last_merge[l] == m2 )\n            last_merge[l] = k;\n        }\n      }\n    }\n\n    // assign cluster labels\n    int label = 0;\n    std::vector<int> z(n,-1);\n    for (j=0; j<n; j++) {\n      if (last_merge[j] == 0) { // still singleton\n        labels[j] = label++;\n      } else {\n        if (z[last_merge[j]] < 0) {\n          z[last_merge[j]] = label++;\n        }\n        labels[j] = z[last_merge[j]];\n      }\n    }\n  }\n\n  //\n  // Assigns cluster labels (0, ..., nclust-1) to the n points such\n  // that the hierarchical clustering is stopped when cluster distance >= cdist\n  //\n  // Input arguments:\n  //   n      = number of observables\n  //   merge  = clustering result in R format\n  //   height = cluster distance at each merge step\n  //   cdist  = cutoff cluster distance\n  // Output arguments:\n  //   labels = allocated integer array of size n for result\n  //\n  void cutree_cdist(int n, const int* merge, double* height, double cdist, int* labels) {\n\n    int k;\n\n    for (k=0; k<(n-1); k++) {\n      if (height[k] >= cdist) {\n        break;\n      }\n    }\n    cutree_k(n, merge, n-k, labels);\n  }\n\n\n  //\n  // Hierarchical clustering with one of Daniel Muellner's fast algorithms\n  //\n  // Input arguments:\n  //   n       = number of observables\n  //   distmat = condensed distance matrix, i.e. an n*(n-1)/2 array representing\n  //             the upper triangle (without diagonal elements) of the distance\n  //             matrix, e.g. for n=4:\n  //               d00 d01 d02 d03\n  //               d10 d11 d12 d13   ->  d01 d02 d03 d12 d13 d23\n  //               d20 d21 d22 d23\n  //               d30 d31 d32 d33\n  //   method  = cluster metric (see enum method_code)\n  // Output arguments:\n  //   merge   = allocated (n-1)x2 matrix (2*(n-1) array) for storing result.\n  //             Result follows R hclust convention:\n  //              - observabe indices start with one\n  //              - merge[i][] contains the merged nodes in step i\n  //              - merge[i][j] is negative when the node is an atom\n  //   height  = allocated (n-1) array with distances at each merge step\n  // Return code:\n  //   0 = ok\n  //   1 = invalid method\n  //\n  int hclust_fast(int n, double* distmat, int method, int* merge, double* height) {\n\n    // call appropriate culstering function\n    cluster_result Z2(n-1);\n    if (method == HCLUST_METHOD_SINGLE) {\n      // single link\n      MST_linkage_core(n, distmat, Z2);\n    }\n    else if (method == HCLUST_METHOD_COMPLETE) {\n      // complete link\n      NN_chain_core<METHOD_METR_COMPLETE, t_float>(n, distmat, NULL, Z2);\n    }\n    else if (method == HCLUST_METHOD_AVERAGE) {\n      // best average distance\n      double* members = new double[n];\n      for (int i=0; i<n; i++) members[i] = 1;\n      NN_chain_core<METHOD_METR_AVERAGE, t_float>(n, distmat, members, Z2);\n      delete[] members;\n    }\n    else if (method == HCLUST_METHOD_MEDIAN) {\n      // best median distance (beware: O(n^3))\n      generic_linkage<METHOD_METR_MEDIAN, t_float>(n, distmat, NULL, Z2);\n    }\n    else if (method == HCLUST_METHOD_CENTROID) {\n      // best centroid distance (beware: O(n^3))\n      double* members = new double[n];\n      for (int i=0; i<n; i++) members[i] = 1;\n      generic_linkage<METHOD_METR_CENTROID, t_float>(n, distmat, members, Z2);\n      delete[] members;\n    }\n    else {\n      return 1;\n    }\n\n    int* order = new int[n];\n    if (method == HCLUST_METHOD_MEDIAN || method == HCLUST_METHOD_CENTROID) {\n      generate_R_dendrogram<true>(merge, height, order, Z2, n);\n    } else {\n      generate_R_dendrogram<false>(merge, height, order, Z2, n);\n    }\n    delete[] order; // only needed for visualization\n\n    return 0;\n  }\n\n\n  // Build condensed distance matrix\n  // Input arguments:\n  //   n  = number of observables\n  //   m  = dimension of observable\n  // Output arguments:\n  //   out = allocated integer array of size n * (n - 1) / 2 for result\n  void hclust_pdist(int n, int m, double* pts, double* out) {\n    int ii = 0;\n    for (int i = 0; i < n; i++) {\n      for (int j = i + 1; j < n; j++) {\n        // Compute euclidian distance\n        double d = 0;\n        for (int k = 0; k < m; k ++) {\n          double error = pts[i * m + k] - pts[j * m + k];\n          d += (error * error);\n        }\n        out[ii] = d;//sqrt(d);\n        ii++;\n      }\n    }\n  }\n\n  void cluster_points_centroid(int n, int m, double* pts, double dist, int* idx) {\n    double* pdist = new double[n * (n - 1) / 2];\n    int* merge = new int[2 * (n - 1)];\n    double* height = new double[n - 1];\n\n    hclust_pdist(n, m, pts, pdist);\n    hclust_fast(n, pdist, HCLUST_METHOD_CENTROID, merge, height);\n    cutree_cdist(n, merge, height, dist, idx);\n\n    delete[] pdist;\n    delete[] merge;\n    delete[] height;\n  }\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/fastcluster.h",
    "content": "//\n// C++ standalone verion of fastcluster by Daniel Muellner\n//\n// Copyright: Daniel Muellner, 2011\n//            Christoph Dalitz, 2018\n// License:   BSD style license\n//            (see the file LICENSE for details)\n//\n\n#ifndef fastclustercpp_H\n#define fastclustercpp_H\n\n//\n// Assigns cluster labels (0, ..., nclust-1) to the n points such\n// that the cluster result is split into nclust clusters.\n//\n// Input arguments:\n//   n      = number of observables\n//   merge  = clustering result in R format\n//   nclust = number of clusters\n// Output arguments:\n//   labels = allocated integer array of size n for result\n//\nvoid cutree_k(int n, const int* merge, int nclust, int* labels);\n\n//\n// Assigns cluster labels (0, ..., nclust-1) to the n points such\n// that the hierarchical clsutering is stopped at cluster distance cdist\n//\n// Input arguments:\n//   n      = number of observables\n//   merge  = clustering result in R format\n//   height = cluster distance at each merge step\n//   cdist  = cutoff cluster distance\n// Output arguments:\n//   labels = allocated integer array of size n for result\n//\nvoid cutree_cdist(int n, const int* merge, double* height, double cdist, int* labels);\n\n//\n// Hierarchical clustering with one of Daniel Muellner's fast algorithms\n//\n// Input arguments:\n//   n       = number of observables\n//   distmat = condensed distance matrix, i.e. an n*(n-1)/2 array representing\n//             the upper triangle (without diagonal elements) of the distance\n//             matrix, e.g. for n=4:\n//               d00 d01 d02 d03\n//               d10 d11 d12 d13   ->  d01 d02 d03 d12 d13 d23\n//               d20 d21 d22 d23\n//               d30 d31 d32 d33\n//   method  = cluster metric (see enum method_code)\n// Output arguments:\n//   merge   = allocated (n-1)x2 matrix (2*(n-1) array) for storing result.\n//             Result follows R hclust convention:\n//              - observabe indices start with one\n//              - merge[i][] contains the merged nodes in step i\n//              - merge[i][j] is negative when the node is an atom\n//   height  = allocated (n-1) array with distances at each merge step\n// Return code:\n//   0 = ok\n//   1 = invalid method\n//\nint hclust_fast(int n, double* distmat, int method, int* merge, double* height);\nenum hclust_fast_methods {\n  HCLUST_METHOD_SINGLE = 0,\n  HCLUST_METHOD_COMPLETE = 1,\n  HCLUST_METHOD_AVERAGE = 2,\n  HCLUST_METHOD_MEDIAN = 3,\n  HCLUST_METHOD_CENTROID = 5,\n};\n\nvoid hclust_pdist(int n, int m, double* pts, double* out);\nvoid cluster_points_centroid(int n, int m, double* pts, double dist, int* idx);\n\n\n#endif\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/fastcluster_R_dm.cpp",
    "content": "//\n// Excerpt from fastcluster_R.cpp\n//\n// Copyright: Daniel Müllner, 2011 <http://danifold.net>\n//\n\nstruct pos_node {\n  t_index pos;\n  int node;\n};\n\nvoid order_nodes(const int N, const int * const merge, const t_index * const node_size, int * const order) {\n  /* Parameters:\n     N         : number of data points\n     merge     : (N-1)×2 array which specifies the node indices which are\n                 merged in each step of the clustering procedure.\n                 Negative entries -1...-N point to singleton nodes, while\n                 positive entries 1...(N-1) point to nodes which are themselves\n                 parents of other nodes.\n     node_size : array of node sizes - makes it easier\n     order     : output array of size N\n\n     Runtime: Θ(N)\n  */\n  auto_array_ptr<pos_node> queue(N/2);\n\n  int parent;\n  int child;\n  t_index pos = 0;\n\n  queue[0].pos = 0;\n  queue[0].node = N-2;\n  t_index idx = 1;\n\n  do {\n    --idx;\n    pos = queue[idx].pos;\n    parent = queue[idx].node;\n\n    // First child\n    child = merge[parent];\n    if (child<0) { // singleton node, write this into the 'order' array.\n      order[pos] = -child;\n      ++pos;\n    }\n    else { /* compound node: put it on top of the queue and decompose it\n              in a later iteration. */\n      queue[idx].pos = pos;\n      queue[idx].node = child-1; // convert index-1 based to index-0 based\n      ++idx;\n      pos += node_size[child-1];\n    }\n    // Second child\n    child = merge[parent+N-1];\n    if (child<0) {\n      order[pos] = -child;\n    }\n    else {\n      queue[idx].pos = pos;\n      queue[idx].node = child-1;\n      ++idx;\n    }\n  } while (idx>0);\n}\n\n#define size_(r_) ( ((r_<N) ? 1 : node_size[r_-N]) )\n\ntemplate <const bool sorted>\nvoid generate_R_dendrogram(int * const merge, double * const height, int * const order, cluster_result & Z2, const int N) {\n  // The array \"nodes\" is a union-find data structure for the cluster\n  // identites (only needed for unsorted cluster_result input).\n  union_find nodes(sorted ? 0 : N);\n  if (!sorted) {\n    std::stable_sort(Z2[0], Z2[N-1]);\n  }\n\n  t_index node1, node2;\n  auto_array_ptr<t_index> node_size(N-1);\n\n  for (t_index i=0; i<N-1; ++i) {\n    // Get two data points whose clusters are merged in step i.\n    // Find the cluster identifiers for these points.\n    if (sorted) {\n      node1 = Z2[i]->node1;\n      node2 = Z2[i]->node2;\n    }\n    else {\n      node1 = nodes.Find(Z2[i]->node1);\n      node2 = nodes.Find(Z2[i]->node2);\n      // Merge the nodes in the union-find data structure by making them\n      // children of a new node.\n      nodes.Union(node1, node2);\n    }\n    // Sort the nodes in the output array.\n    if (node1>node2) {\n      t_index tmp = node1;\n      node1 = node2;\n      node2 = tmp;\n    }\n    /* Conversion between labeling conventions.\n       Input:  singleton nodes 0,...,N-1\n               compound nodes  N,...,2N-2\n       Output: singleton nodes -1,...,-N\n               compound nodes  1,...,N\n    */\n    merge[i]     = (node1<N) ? -static_cast<int>(node1)-1\n                              : static_cast<int>(node1)-N+1;\n    merge[i+N-1] = (node2<N) ? -static_cast<int>(node2)-1\n                              : static_cast<int>(node2)-N+1;\n    height[i] = Z2[i]->dist;\n    node_size[i] = size_(node1) + size_(node2);\n  }\n\n  order_nodes(N, merge, node_size, order);\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/fastcluster_dm.cpp",
    "content": "/*\n  fastcluster: Fast hierarchical clustering routines for R and Python\n\n  Copyright © 2011 Daniel Müllner\n  <http://danifold.net>\n\n  This library implements various fast algorithms for hierarchical,\n  agglomerative clustering methods:\n\n  (1) Algorithms for the \"stored matrix approach\": the input is the array of\n      pairwise dissimilarities.\n\n      MST_linkage_core: single linkage clustering with the \"minimum spanning\n      tree algorithm (Rohlfs)\n\n      NN_chain_core: nearest-neighbor-chain algorithm, suitable for single,\n      complete, average, weighted and Ward linkage (Murtagh)\n\n      generic_linkage: generic algorithm, suitable for all distance update\n      formulas (Müllner)\n\n  (2) Algorithms for the \"stored data approach\": the input are points in a\n      vector space.\n\n      MST_linkage_core_vector: single linkage clustering for vector data\n\n      generic_linkage_vector: generic algorithm for vector data, suitable for\n      the Ward, centroid and median methods.\n\n      generic_linkage_vector_alternative: alternative scheme for updating the\n      nearest neighbors. This method seems faster than \"generic_linkage_vector\"\n      for the centroid and median methods but slower for the Ward method.\n\n  All these implementation treat infinity values correctly. They throw an\n  exception if a NaN distance value occurs.\n*/\n\n// Older versions of Microsoft Visual Studio do not have the fenv header.\n#ifdef _MSC_VER\n#if (_MSC_VER == 1500 || _MSC_VER == 1600)\n#define NO_INCLUDE_FENV\n#endif\n#endif\n// NaN detection via fenv might not work on systems with software\n// floating-point emulation (bug report for Debian armel).\n#ifdef __SOFTFP__\n#define NO_INCLUDE_FENV\n#endif\n#ifdef NO_INCLUDE_FENV\n#pragma message(\"Do not use fenv header.\")\n#else\n//#pragma message(\"Use fenv header. If there is a warning about unknown #pragma STDC FENV_ACCESS, this can be ignored.\")\n//#pragma STDC FENV_ACCESS on\n#include <fenv.h>\n#endif\n\n#include <cmath> // for std::pow, std::sqrt\n#include <cstddef> // for std::ptrdiff_t\n#include <limits> // for std::numeric_limits<...>::infinity()\n#include <algorithm> // for std::fill_n\n#include <stdexcept> // for std::runtime_error\n#include <string> // for std::string\n\n#include <cfloat> // also for DBL_MAX, DBL_MIN\n#ifndef DBL_MANT_DIG\n#error The constant DBL_MANT_DIG could not be defined.\n#endif\n#define T_FLOAT_MANT_DIG DBL_MANT_DIG\n\n#ifndef LONG_MAX\n#include <climits>\n#endif\n#ifndef LONG_MAX\n#error The constant LONG_MAX could not be defined.\n#endif\n#ifndef INT_MAX\n#error The constant INT_MAX could not be defined.\n#endif\n\n#ifndef INT32_MAX\n#ifdef _MSC_VER\n#if _MSC_VER >= 1600\n#define __STDC_LIMIT_MACROS\n#include <stdint.h>\n#else\ntypedef __int32 int_fast32_t;\ntypedef __int64 int64_t;\n#endif\n#else\n#define __STDC_LIMIT_MACROS\n#include <stdint.h>\n#endif\n#endif\n\n#define FILL_N std::fill_n\n#ifdef _MSC_VER\n#if _MSC_VER < 1600\n#undef FILL_N\n#define FILL_N stdext::unchecked_fill_n\n#endif\n#endif\n\n// Suppress warnings about (potentially) uninitialized variables.\n#ifdef _MSC_VER\n\t#pragma warning (disable:4700)\n#endif\n\n#ifndef HAVE_DIAGNOSTIC\n#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ >= 6))\n#define HAVE_DIAGNOSTIC 1\n#endif\n#endif\n\n#ifndef HAVE_VISIBILITY\n#if __GNUC__ >= 4\n#define HAVE_VISIBILITY 1\n#endif\n#endif\n\n/* Since the public interface is given by the Python respectively R interface,\n * we do not want other symbols than the interface initalization routines to be\n * visible in the shared object file. The \"visibility\" switch is a GCC concept.\n * Hiding symbols keeps the relocation table small and decreases startup time.\n * See http://gcc.gnu.org/wiki/Visibility\n */\n#if HAVE_VISIBILITY\n#pragma GCC visibility push(hidden)\n#endif\n\ntypedef int_fast32_t t_index;\n#ifndef INT32_MAX\n#define MAX_INDEX 0x7fffffffL\n#else\n#define MAX_INDEX INT32_MAX\n#endif\n#if (LONG_MAX < MAX_INDEX)\n#error The integer format \"t_index\" must not have a greater range than \"long int\".\n#endif\n#if (INT_MAX > MAX_INDEX)\n#error The integer format \"int\" must not have a greater range than \"t_index\".\n#endif\ntypedef double t_float;\n\n/* Method codes.\n\n   These codes must agree with the METHODS array in fastcluster.R and the\n   dictionary mthidx in fastcluster.py.\n*/\nenum method_codes {\n  // non-Euclidean methods\n  METHOD_METR_SINGLE           = 0,\n  METHOD_METR_COMPLETE         = 1,\n  METHOD_METR_AVERAGE          = 2,\n  METHOD_METR_WEIGHTED         = 3,\n  METHOD_METR_WARD             = 4,\n  METHOD_METR_WARD_D           = METHOD_METR_WARD,\n  METHOD_METR_CENTROID         = 5,\n  METHOD_METR_MEDIAN           = 6,\n  METHOD_METR_WARD_D2          = 7,\n\n  MIN_METHOD_CODE              = 0,\n  MAX_METHOD_CODE              = 7\n};\n\nenum method_codes_vector {\n  // Euclidean methods\n  METHOD_VECTOR_SINGLE         = 0,\n  METHOD_VECTOR_WARD           = 1,\n  METHOD_VECTOR_CENTROID       = 2,\n  METHOD_VECTOR_MEDIAN         = 3,\n\n  MIN_METHOD_VECTOR_CODE       = 0,\n  MAX_METHOD_VECTOR_CODE       = 3\n};\n\n// self-destructing array pointer\ntemplate <typename type>\nclass auto_array_ptr{\nprivate:\n  type * ptr;\n  auto_array_ptr(auto_array_ptr const &); // non construction-copyable\n  auto_array_ptr& operator=(auto_array_ptr const &); // non copyable\npublic:\n  auto_array_ptr()\n    : ptr(NULL)\n  { }\n  template <typename index>\n  auto_array_ptr(index const size)\n    : ptr(new type[size])\n  { }\n  template <typename index, typename value>\n  auto_array_ptr(index const size, value const val)\n    : ptr(new type[size])\n  {\n    FILL_N(ptr, size, val);\n  }\n  ~auto_array_ptr() {\n    delete [] ptr; }\n  void free() {\n    delete [] ptr;\n    ptr = NULL;\n  }\n  template <typename index>\n  void init(index const size) {\n    ptr = new type [size];\n  }\n  template <typename index, typename value>\n  void init(index const size, value const val) {\n    init(size);\n    FILL_N(ptr, size, val);\n  }\n  inline operator type *() const { return ptr; }\n};\n\nstruct node {\n  t_index node1, node2;\n  t_float dist;\n};\n\ninline bool operator< (const node a, const node b) {\n  return (a.dist < b.dist);\n}\n\nclass cluster_result {\nprivate:\n  auto_array_ptr<node> Z;\n  t_index pos;\n\npublic:\n  cluster_result(const t_index size)\n    : Z(size)\n    , pos(0)\n  {}\n\n  void append(const t_index node1, const t_index node2, const t_float dist) {\n    Z[pos].node1 = node1;\n    Z[pos].node2 = node2;\n    Z[pos].dist  = dist;\n    ++pos;\n  }\n\n  node * operator[] (const t_index idx) const { return Z + idx; }\n\n  /* Define several methods to postprocess the distances. All these functions\n     are monotone, so they do not change the sorted order of distances. */\n\n  void sqrt() const {\n    for (node * ZZ=Z; ZZ!=Z+pos; ++ZZ) {\n      ZZ->dist = std::sqrt(ZZ->dist);\n    }\n  }\n\n  void sqrt(const t_float) const { // ignore the argument\n    sqrt();\n  }\n\n  void sqrtdouble(const t_float) const { // ignore the argument\n    for (node * ZZ=Z; ZZ!=Z+pos; ++ZZ) {\n      ZZ->dist = std::sqrt(2*ZZ->dist);\n    }\n  }\n\n  #ifdef R_pow\n  #define my_pow R_pow\n  #else\n  #define my_pow std::pow\n  #endif\n\n  void power(const t_float p) const {\n    t_float const q = 1/p;\n    for (node * ZZ=Z; ZZ!=Z+pos; ++ZZ) {\n      ZZ->dist = my_pow(ZZ->dist,q);\n    }\n  }\n\n  void plusone(const t_float) const { // ignore the argument\n    for (node * ZZ=Z; ZZ!=Z+pos; ++ZZ) {\n      ZZ->dist += 1;\n    }\n  }\n\n  void divide(const t_float denom) const {\n    for (node * ZZ=Z; ZZ!=Z+pos; ++ZZ) {\n      ZZ->dist /= denom;\n    }\n  }\n};\n\nclass doubly_linked_list {\n  /*\n    Class for a doubly linked list. Initially, the list is the integer range\n    [0, size]. We provide a forward iterator and a method to delete an index\n    from the list.\n\n    Typical use: for (i=L.start; L<size; i=L.succ[I])\n    or\n    for (i=somevalue; L<size; i=L.succ[I])\n  */\npublic:\n  t_index start;\n  auto_array_ptr<t_index> succ;\n\nprivate:\n  auto_array_ptr<t_index> pred;\n  // Not necessarily private, we just do not need it in this instance.\n\npublic:\n  doubly_linked_list(const t_index size)\n    // Initialize to the given size.\n    : start(0)\n    , succ(size+1)\n    , pred(size+1)\n  {\n    for (t_index i=0; i<size; ++i) {\n      pred[i+1] = i;\n      succ[i] = i+1;\n    }\n    // pred[0] is never accessed!\n    //succ[size] is never accessed!\n  }\n\n  ~doubly_linked_list() {}\n\n  void remove(const t_index idx) {\n    // Remove an index from the list.\n    if (idx==start) {\n      start = succ[idx];\n    }\n    else {\n      succ[pred[idx]] = succ[idx];\n      pred[succ[idx]] = pred[idx];\n    }\n    succ[idx] = 0; // Mark as inactive\n  }\n\n  bool is_inactive(t_index idx) const {\n    return (succ[idx]==0);\n  }\n};\n\n// Indexing functions\n// D is the upper triangular part of a symmetric (NxN)-matrix\n// We require r_ < c_ !\n#define D_(r_,c_) ( D[(static_cast<std::ptrdiff_t>(2*N-3-(r_))*(r_)>>1)+(c_)-1] )\n// Z is an ((N-1)x4)-array\n#define Z_(_r, _c) (Z[(_r)*4 + (_c)])\n\n/*\n  Lookup function for a union-find data structure.\n\n  The function finds the root of idx by going iteratively through all\n  parent elements until a root is found. An element i is a root if\n  nodes[i] is zero. To make subsequent searches faster, the entry for\n  idx and all its parents is updated with the root element.\n */\nclass union_find {\nprivate:\n  auto_array_ptr<t_index> parent;\n  t_index nextparent;\n\npublic:\n  union_find(const t_index size)\n    : parent(size>0 ? 2*size-1 : 0, 0)\n    , nextparent(size)\n  { }\n\n  t_index Find (t_index idx) const {\n    if (parent[idx] != 0 ) { // a → b\n      t_index p = idx;\n      idx = parent[idx];\n      if (parent[idx] != 0 ) { // a → b → c\n        do {\n          idx = parent[idx];\n        } while (parent[idx] != 0);\n        do {\n          t_index tmp = parent[p];\n          parent[p] = idx;\n          p = tmp;\n        } while (parent[p] != idx);\n      }\n    }\n    return idx;\n  }\n\n  void Union (const t_index node1, const t_index node2) {\n    parent[node1] = parent[node2] = nextparent++;\n  }\n};\n\nclass nan_error{};\n#ifdef FE_INVALID\nclass fenv_error{};\n#endif\n\nstatic void MST_linkage_core(const t_index N, const t_float * const D,\n                             cluster_result & Z2) {\n/*\n    N: integer, number of data points\n    D: condensed distance matrix N*(N-1)/2\n    Z2: output data structure\n\n    The basis of this algorithm is an algorithm by Rohlf:\n\n    F. James Rohlf, Hierarchical clustering using the minimum spanning tree,\n    The Computer Journal, vol. 16, 1973, p. 93–95.\n*/\n  t_index i;\n  t_index idx2;\n  doubly_linked_list active_nodes(N);\n  auto_array_ptr<t_float> d(N);\n\n  t_index prev_node;\n  t_float min;\n\n  // first iteration\n  idx2 = 1;\n  min = std::numeric_limits<t_float>::infinity();\n  for (i=1; i<N; ++i) {\n    d[i] = D[i-1];\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n    if (d[i] < min) {\n      min = d[i];\n      idx2 = i;\n    }\n    else if (fc_isnan(d[i]))\n      throw (nan_error());\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  }\n  Z2.append(0, idx2, min);\n\n  for (t_index j=1; j<N-1; ++j) {\n    prev_node = idx2;\n    active_nodes.remove(prev_node);\n\n    idx2 = active_nodes.succ[0];\n    min = d[idx2];\n    for (i=idx2; i<prev_node; i=active_nodes.succ[i]) {\n      t_float tmp = D_(i, prev_node);\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n      if (tmp < d[i])\n        d[i] = tmp;\n      else if (fc_isnan(tmp))\n        throw (nan_error());\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n      if (d[i] < min) {\n        min = d[i];\n        idx2 = i;\n      }\n    }\n    for (; i<N; i=active_nodes.succ[i]) {\n      t_float tmp = D_(prev_node, i);\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n      if (d[i] > tmp)\n        d[i] = tmp;\n      else if (fc_isnan(tmp))\n        throw (nan_error());\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n      if (d[i] < min) {\n        min = d[i];\n        idx2 = i;\n      }\n    }\n    Z2.append(prev_node, idx2, min);\n  }\n}\n\n/* Functions for the update of the dissimilarity array */\n\ninline static void f_single( t_float * const b, const t_float a ) {\n  if (*b > a) *b = a;\n}\ninline static void f_complete( t_float * const b, const t_float a ) {\n  if (*b < a) *b = a;\n}\ninline static void f_average( t_float * const b, const t_float a, const t_float s, const t_float t) {\n  *b = s*a + t*(*b);\n  #ifndef FE_INVALID\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n  if (fc_isnan(*b)) {\n    throw(nan_error());\n  }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  #endif\n}\ninline static void f_weighted( t_float * const b, const t_float a) {\n  *b = (a+*b)*.5;\n  #ifndef FE_INVALID\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n  if (fc_isnan(*b)) {\n    throw(nan_error());\n  }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  #endif\n}\ninline static void f_ward( t_float * const b, const t_float a, const t_float c, const t_float s, const t_float t, const t_float v) {\n  *b = ( (v+s)*a - v*c + (v+t)*(*b) ) / (s+t+v);\n  //*b = a+(*b)-(t*a+s*(*b)+v*c)/(s+t+v);\n  #ifndef FE_INVALID\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n  if (fc_isnan(*b)) {\n    throw(nan_error());\n  }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  #endif\n}\ninline static void f_centroid( t_float * const b, const t_float a, const t_float stc, const t_float s, const t_float t) {\n  *b = s*a - stc + t*(*b);\n  #ifndef FE_INVALID\n  if (fc_isnan(*b)) {\n    throw(nan_error());\n  }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  #endif\n}\ninline static void f_median( t_float * const b, const t_float a, const t_float c_4) {\n  *b = (a+(*b))*.5 - c_4;\n  #ifndef FE_INVALID\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n  if (fc_isnan(*b)) {\n    throw(nan_error());\n  }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  #endif\n}\n\ntemplate <method_codes method, typename t_members>\nstatic void NN_chain_core(const t_index N, t_float * const D, t_members * const members, cluster_result & Z2) {\n/*\n    N: integer\n    D: condensed distance matrix N*(N-1)/2\n    Z2: output data structure\n\n    This is the NN-chain algorithm, described on page 86 in the following book:\n\n    Fionn Murtagh, Multidimensional Clustering Algorithms,\n    Vienna, Würzburg: Physica-Verlag, 1985.\n*/\n  t_index i;\n\n  auto_array_ptr<t_index> NN_chain(N);\n  t_index NN_chain_tip = 0;\n\n  t_index idx1, idx2;\n\n  t_float size1, size2;\n  doubly_linked_list active_nodes(N);\n\n  t_float min;\n\n  for (t_float const * DD=D; DD!=D+(static_cast<std::ptrdiff_t>(N)*(N-1)>>1);\n       ++DD) {\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n    if (fc_isnan(*DD)) {\n      throw(nan_error());\n    }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  }\n\n  #ifdef FE_INVALID\n  if (feclearexcept(FE_INVALID)) throw fenv_error();\n  #endif\n\n  for (t_index j=0; j<N-1; ++j) {\n    if (NN_chain_tip <= 3) {\n      NN_chain[0] = idx1 = active_nodes.start;\n      NN_chain_tip = 1;\n\n      idx2 = active_nodes.succ[idx1];\n      min = D_(idx1,idx2);\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i]) {\n        if (D_(idx1,i) < min) {\n          min = D_(idx1,i);\n          idx2 = i;\n        }\n      }\n    }  // a: idx1   b: idx2\n    else {\n      NN_chain_tip -= 3;\n      idx1 = NN_chain[NN_chain_tip-1];\n      idx2 = NN_chain[NN_chain_tip];\n      min = idx1<idx2 ? D_(idx1,idx2) : D_(idx2,idx1);\n    }  // a: idx1   b: idx2\n\n    do {\n      NN_chain[NN_chain_tip] = idx2;\n\n      for (i=active_nodes.start; i<idx2; i=active_nodes.succ[i]) {\n        if (D_(i,idx2) < min) {\n          min = D_(i,idx2);\n          idx1 = i;\n        }\n      }\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i]) {\n        if (D_(idx2,i) < min) {\n          min = D_(idx2,i);\n          idx1 = i;\n        }\n      }\n\n      idx2 = idx1;\n      idx1 = NN_chain[NN_chain_tip++];\n\n    } while (idx2 != NN_chain[NN_chain_tip-2]);\n\n    Z2.append(idx1, idx2, min);\n\n    if (idx1>idx2) {\n      t_index tmp = idx1;\n      idx1 = idx2;\n      idx2 = tmp;\n    }\n\n    if (method==METHOD_METR_AVERAGE ||\n        method==METHOD_METR_WARD) {\n      size1 = static_cast<t_float>(members[idx1]);\n      size2 = static_cast<t_float>(members[idx2]);\n      members[idx2] += members[idx1];\n    }\n\n    // Remove the smaller index from the valid indices (active_nodes).\n    active_nodes.remove(idx1);\n\n    switch (method) {\n    case METHOD_METR_SINGLE:\n      /*\n      Single linkage.\n\n      Characteristic: new distances are never longer than the old distances.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (i=active_nodes.start; i<idx1; i=active_nodes.succ[i])\n        f_single(&D_(i, idx2), D_(i, idx1) );\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; i<idx2; i=active_nodes.succ[i])\n        f_single(&D_(i, idx2), D_(idx1, i) );\n      // Update the distance matrix in the range (idx2, N).\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i])\n        f_single(&D_(idx2, i), D_(idx1, i) );\n      break;\n\n    case METHOD_METR_COMPLETE:\n      /*\n      Complete linkage.\n\n      Characteristic: new distances are never shorter than the old distances.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (i=active_nodes.start; i<idx1; i=active_nodes.succ[i])\n        f_complete(&D_(i, idx2), D_(i, idx1) );\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; i<idx2; i=active_nodes.succ[i])\n        f_complete(&D_(i, idx2), D_(idx1, i) );\n      // Update the distance matrix in the range (idx2, N).\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i])\n        f_complete(&D_(idx2, i), D_(idx1, i) );\n      break;\n\n    case METHOD_METR_AVERAGE: {\n      /*\n      Average linkage.\n\n      Shorter and longer distances can occur.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      t_float s = size1/(size1+size2);\n      t_float t = size2/(size1+size2);\n      for (i=active_nodes.start; i<idx1; i=active_nodes.succ[i])\n        f_average(&D_(i, idx2), D_(i, idx1), s, t );\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; i<idx2; i=active_nodes.succ[i])\n        f_average(&D_(i, idx2), D_(idx1, i), s, t );\n      // Update the distance matrix in the range (idx2, N).\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i])\n        f_average(&D_(idx2, i), D_(idx1, i), s, t );\n      break;\n    }\n\n    case METHOD_METR_WEIGHTED:\n      /*\n      Weighted linkage.\n\n      Shorter and longer distances can occur.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (i=active_nodes.start; i<idx1; i=active_nodes.succ[i])\n        f_weighted(&D_(i, idx2), D_(i, idx1) );\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; i<idx2; i=active_nodes.succ[i])\n        f_weighted(&D_(i, idx2), D_(idx1, i) );\n      // Update the distance matrix in the range (idx2, N).\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i])\n        f_weighted(&D_(idx2, i), D_(idx1, i) );\n      break;\n\n    case METHOD_METR_WARD:\n      /*\n      Ward linkage.\n\n      Shorter and longer distances can occur, not smaller than min(d1,d2)\n      but maybe bigger than max(d1,d2).\n      */\n      // Update the distance matrix in the range [start, idx1).\n      //t_float v = static_cast<t_float>(members[i]);\n      for (i=active_nodes.start; i<idx1; i=active_nodes.succ[i])\n        f_ward(&D_(i, idx2), D_(i, idx1), min,\n               size1, size2, static_cast<t_float>(members[i]) );\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; i<idx2; i=active_nodes.succ[i])\n        f_ward(&D_(i, idx2), D_(idx1, i), min,\n               size1, size2, static_cast<t_float>(members[i]) );\n      // Update the distance matrix in the range (idx2, N).\n      for (i=active_nodes.succ[idx2]; i<N; i=active_nodes.succ[i])\n        f_ward(&D_(idx2, i), D_(idx1, i), min,\n               size1, size2, static_cast<t_float>(members[i]) );\n      break;\n\n    default:\n      throw std::runtime_error(std::string(\"Invalid method.\"));\n    }\n  }\n  #ifdef FE_INVALID\n  if (fetestexcept(FE_INVALID)) throw fenv_error();\n  #endif\n}\n\nclass binary_min_heap {\n  /*\n  Class for a binary min-heap. The data resides in an array A. The elements of\n  A are not changed but two lists I and R of indices are generated which point\n  to elements of A and backwards.\n\n  The heap tree structure is\n\n     H[2*i+1]     H[2*i+2]\n         \\            /\n          \\          /\n           ≤        ≤\n            \\      /\n             \\    /\n              H[i]\n\n  where the children must be less or equal than their parent. Thus, H[0]\n  contains the minimum. The lists I and R are made such that H[i] = A[I[i]]\n  and R[I[i]] = i.\n\n  This implementation is not designed to handle NaN values.\n  */\nprivate:\n  t_float * const A;\n  t_index size;\n  auto_array_ptr<t_index> I;\n  auto_array_ptr<t_index> R;\n\n  // no default constructor\n  binary_min_heap();\n  // noncopyable\n  binary_min_heap(binary_min_heap const &);\n  binary_min_heap & operator=(binary_min_heap const &);\n\npublic:\n  binary_min_heap(t_float * const A_, const t_index size_)\n    : A(A_), size(size_), I(size), R(size)\n  { // Allocate memory and initialize the lists I and R to the identity. This\n    // does not make it a heap. Call heapify afterwards!\n    for (t_index i=0; i<size; ++i)\n      R[i] = I[i] = i;\n  }\n\n  binary_min_heap(t_float * const A_, const t_index size1, const t_index size2,\n                  const t_index start)\n    : A(A_), size(size1), I(size1), R(size2)\n  { // Allocate memory and initialize the lists I and R to the identity. This\n    // does not make it a heap. Call heapify afterwards!\n    for (t_index i=0; i<size; ++i) {\n      R[i+start] = i;\n      I[i] = i + start;\n    }\n  }\n\n  ~binary_min_heap() {}\n\n  void heapify() {\n    // Arrange the indices I and R so that H[i] := A[I[i]] satisfies the heap\n    // condition H[i] < H[2*i+1] and H[i] < H[2*i+2] for each i.\n    //\n    // Complexity: Θ(size)\n    // Reference: Cormen, Leiserson, Rivest, Stein, Introduction to Algorithms,\n    // 3rd ed., 2009, Section 6.3 “Building a heap”\n    t_index idx;\n    for (idx=(size>>1); idx>0; ) {\n      --idx;\n      update_geq_(idx);\n    }\n  }\n\n  inline t_index argmin() const {\n    // Return the minimal element.\n    return I[0];\n  }\n\n  void heap_pop() {\n    // Remove the minimal element from the heap.\n    --size;\n    I[0] = I[size];\n    R[I[0]] = 0;\n    update_geq_(0);\n  }\n\n  void remove(t_index idx) {\n    // Remove an element from the heap.\n    --size;\n    R[I[size]] = R[idx];\n    I[R[idx]] = I[size];\n    if ( H(size)<=A[idx] ) {\n      update_leq_(R[idx]);\n    }\n    else {\n      update_geq_(R[idx]);\n    }\n  }\n\n  void replace ( const t_index idxold, const t_index idxnew,\n                 const t_float val) {\n    R[idxnew] = R[idxold];\n    I[R[idxnew]] = idxnew;\n    if (val<=A[idxold])\n      update_leq(idxnew, val);\n    else\n      update_geq(idxnew, val);\n  }\n\n  void update ( const t_index idx, const t_float val ) const {\n    // Update the element A[i] with val and re-arrange the indices to preserve\n    // the heap condition.\n    if (val<=A[idx])\n      update_leq(idx, val);\n    else\n      update_geq(idx, val);\n  }\n\n  void update_leq ( const t_index idx, const t_float val ) const {\n    // Use this when the new value is not more than the old value.\n    A[idx] = val;\n    update_leq_(R[idx]);\n  }\n\n  void update_geq ( const t_index idx, const t_float val ) const {\n    // Use this when the new value is not less than the old value.\n    A[idx] = val;\n    update_geq_(R[idx]);\n  }\n\nprivate:\n  void update_leq_ (t_index i) const {\n    t_index j;\n    for ( ; (i>0) && ( H(i)<H(j=(i-1)>>1) ); i=j)\n      heap_swap(i,j);\n  }\n\n  void update_geq_ (t_index i) const {\n    t_index j;\n    for ( ; (j=2*i+1)<size; i=j) {\n      if ( H(j)>=H(i) ) {\n        ++j;\n        if ( j>=size || H(j)>=H(i) ) break;\n      }\n      else if ( j+1<size && H(j+1)<H(j) ) ++j;\n      heap_swap(i, j);\n    }\n  }\n\n  void heap_swap(const t_index i, const t_index j) const {\n    // Swap two indices.\n    t_index tmp = I[i];\n    I[i] = I[j];\n    I[j] = tmp;\n    R[I[i]] = i;\n    R[I[j]] = j;\n  }\n\n  inline t_float H(const t_index i) const {\n    return A[I[i]];\n  }\n\n};\n\ntemplate <method_codes method, typename t_members>\nstatic void generic_linkage(const t_index N, t_float * const D, t_members * const members, cluster_result & Z2) {\n  /*\n    N: integer, number of data points\n    D: condensed distance matrix N*(N-1)/2\n    Z2: output data structure\n  */\n\n  const t_index N_1 = N-1;\n  t_index i, j; // loop variables\n  t_index idx1, idx2; // row and column indices\n\n  auto_array_ptr<t_index> n_nghbr(N_1); // array of nearest neighbors\n  auto_array_ptr<t_float> mindist(N_1); // distances to the nearest neighbors\n  auto_array_ptr<t_index> row_repr(N); // row_repr[i]: node number that the\n                                       // i-th row represents\n  doubly_linked_list active_nodes(N);\n  binary_min_heap nn_distances(&*mindist, N_1); // minimum heap structure for\n                        // the distance to the nearest neighbor of each point\n  t_index node1, node2; // node numbers in the output\n  t_float size1, size2; // and their cardinalities\n\n  t_float min; // minimum and row index for nearest-neighbor search\n  t_index idx;\n\n  for (i=0; i<N; ++i)\n    // Build a list of row ↔ node label assignments.\n    // Initially i ↦ i\n    row_repr[i] = i;\n\n  // Initialize the minimal distances:\n  // Find the nearest neighbor of each point.\n  // n_nghbr[i] = argmin_{j>i} D(i,j) for i in range(N-1)\n  t_float const * DD = D;\n  for (i=0; i<N_1; ++i) {\n    min = std::numeric_limits<t_float>::infinity();\n    for (idx=j=i+1; j<N; ++j, ++DD) {\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n      if (*DD<min) {\n        min = *DD;\n        idx = j;\n      }\n      else if (fc_isnan(*DD))\n        throw(nan_error());\n    }\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n    mindist[i] = min;\n    n_nghbr[i] = idx;\n  }\n\n  // Put the minimal distances into a heap structure to make the repeated\n  // global minimum searches fast.\n  nn_distances.heapify();\n\n  #ifdef FE_INVALID\n  if (feclearexcept(FE_INVALID)) throw fenv_error();\n  #endif\n\n  // Main loop: We have N-1 merging steps.\n  for (i=0; i<N_1; ++i) {\n    /*\n      Here is a special feature that allows fast bookkeeping and updates of the\n      minimal distances.\n\n      mindist[i] stores a lower bound on the minimum distance of the point i to\n      all points of higher index:\n\n          mindist[i] ≥ min_{j>i} D(i,j)\n\n      Normally, we have equality. However, this minimum may become invalid due\n      to the updates in the distance matrix. The rules are:\n\n      1) If mindist[i] is equal to D(i, n_nghbr[i]), this is the correct\n         minimum and n_nghbr[i] is a nearest neighbor.\n\n      2) If mindist[i] is smaller than D(i, n_nghbr[i]), this might not be the\n         correct minimum. The minimum needs to be recomputed.\n\n      3) mindist[i] is never bigger than the true minimum. Hence, we never\n         miss the true minimum if we take the smallest mindist entry,\n         re-compute the value if necessary (thus maybe increasing it) and\n         looking for the now smallest mindist entry until a valid minimal\n         entry is found. This step is done in the lines below.\n\n      The update process for D below takes care that these rules are\n      fulfilled. This makes sure that the minima in the rows D(i,i+1:)of D are\n      re-calculated when necessary but re-calculation is avoided whenever\n      possible.\n\n      The re-calculation of the minima makes the worst-case runtime of this\n      algorithm cubic in N. We avoid this whenever possible, and in most cases\n      the runtime appears to be quadratic.\n    */\n    idx1 = nn_distances.argmin();\n    if (method != METHOD_METR_SINGLE) {\n      while ( mindist[idx1] < D_(idx1, n_nghbr[idx1]) ) {\n        // Recompute the minimum mindist[idx1] and n_nghbr[idx1].\n        n_nghbr[idx1] = j = active_nodes.succ[idx1]; // exists, maximally N-1\n        min = D_(idx1,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          if (D_(idx1,j)<min) {\n            min = D_(idx1,j);\n            n_nghbr[idx1] = j;\n          }\n        }\n        /* Update the heap with the new true minimum and search for the\n           (possibly different) minimal entry. */\n        nn_distances.update_geq(idx1, min);\n        idx1 = nn_distances.argmin();\n      }\n    }\n\n    nn_distances.heap_pop(); // Remove the current minimum from the heap.\n    idx2 = n_nghbr[idx1];\n\n    // Write the newly found minimal pair of nodes to the output array.\n    node1 = row_repr[idx1];\n    node2 = row_repr[idx2];\n\n    if (method==METHOD_METR_AVERAGE ||\n        method==METHOD_METR_WARD ||\n        method==METHOD_METR_CENTROID) {\n      size1 = static_cast<t_float>(members[idx1]);\n      size2 = static_cast<t_float>(members[idx2]);\n      members[idx2] += members[idx1];\n    }\n    Z2.append(node1, node2, mindist[idx1]);\n\n    // Remove idx1 from the list of active indices (active_nodes).\n    active_nodes.remove(idx1);\n    // Index idx2 now represents the new (merged) node with label N+i.\n    row_repr[idx2] = N+i;\n\n    // Update the distance matrix\n    switch (method) {\n    case METHOD_METR_SINGLE:\n      /*\n        Single linkage.\n\n        Characteristic: new distances are never longer than the old distances.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_single(&D_(j, idx2), D_(j, idx1));\n        if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j]) {\n        f_single(&D_(j, idx2), D_(idx1, j));\n        // If the new value is below the old minimum in a row, update\n        // the mindist and n_nghbr arrays.\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n      }\n      // Update the distance matrix in the range (idx2, N).\n      // Recompute the minimum mindist[idx2] and n_nghbr[idx2].\n      if (idx2<N_1) {\n        min = mindist[idx2];\n        for (j=active_nodes.succ[idx2]; j<N; j=active_nodes.succ[j]) {\n          f_single(&D_(idx2, j), D_(idx1, j) );\n          if (D_(idx2, j) < min) {\n            n_nghbr[idx2] = j;\n            min = D_(idx2, j);\n          }\n        }\n        nn_distances.update_leq(idx2, min);\n      }\n      break;\n\n    case METHOD_METR_COMPLETE:\n      /*\n        Complete linkage.\n\n        Characteristic: new distances are never shorter than the old distances.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_complete(&D_(j, idx2), D_(j, idx1) );\n        if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j])\n        f_complete(&D_(j, idx2), D_(idx1, j) );\n      // Update the distance matrix in the range (idx2, N).\n      for (j=active_nodes.succ[idx2]; j<N; j=active_nodes.succ[j])\n        f_complete(&D_(idx2, j), D_(idx1, j) );\n      break;\n\n    case METHOD_METR_AVERAGE: {\n      /*\n        Average linkage.\n\n        Shorter and longer distances can occur.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      t_float s = size1/(size1+size2);\n      t_float t = size2/(size1+size2);\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_average(&D_(j, idx2), D_(j, idx1), s, t);\n        if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j]) {\n        f_average(&D_(j, idx2), D_(idx1, j), s, t);\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n      }\n      // Update the distance matrix in the range (idx2, N).\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        f_average(&D_(idx2, j), D_(idx1, j), s, t);\n        min = D_(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          f_average(&D_(idx2, j), D_(idx1, j), s, t);\n          if (D_(idx2,j) < min) {\n            min = D_(idx2,j);\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n      break;\n    }\n\n    case METHOD_METR_WEIGHTED:\n      /*\n        Weighted linkage.\n\n        Shorter and longer distances can occur.\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_weighted(&D_(j, idx2), D_(j, idx1) );\n        if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j]) {\n        f_weighted(&D_(j, idx2), D_(idx1, j) );\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n      }\n      // Update the distance matrix in the range (idx2, N).\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        f_weighted(&D_(idx2, j), D_(idx1, j) );\n        min = D_(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          f_weighted(&D_(idx2, j), D_(idx1, j) );\n          if (D_(idx2,j) < min) {\n            min = D_(idx2,j);\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n      break;\n\n    case METHOD_METR_WARD:\n      /*\n        Ward linkage.\n\n        Shorter and longer distances can occur, not smaller than min(d1,d2)\n        but maybe bigger than max(d1,d2).\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_ward(&D_(j, idx2), D_(j, idx1), mindist[idx1],\n               size1, size2, static_cast<t_float>(members[j]) );\n        if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j]) {\n        f_ward(&D_(j, idx2), D_(idx1, j), mindist[idx1], size1, size2,\n               static_cast<t_float>(members[j]) );\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n      }\n      // Update the distance matrix in the range (idx2, N).\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        f_ward(&D_(idx2, j), D_(idx1, j), mindist[idx1],\n               size1, size2, static_cast<t_float>(members[j]) );\n        min = D_(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          f_ward(&D_(idx2, j), D_(idx1, j), mindist[idx1],\n                 size1, size2, static_cast<t_float>(members[j]) );\n          if (D_(idx2,j) < min) {\n            min = D_(idx2,j);\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n      break;\n\n    case METHOD_METR_CENTROID: {\n      /*\n        Centroid linkage.\n\n        Shorter and longer distances can occur, not bigger than max(d1,d2)\n        but maybe smaller than min(d1,d2).\n      */\n      // Update the distance matrix in the range [start, idx1).\n      t_float s = size1/(size1+size2);\n      t_float t = size2/(size1+size2);\n      t_float stc = s*t*mindist[idx1];\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_centroid(&D_(j, idx2), D_(j, idx1), stc, s, t);\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n        else if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j]) {\n        f_centroid(&D_(j, idx2), D_(idx1, j), stc, s, t);\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n      }\n      // Update the distance matrix in the range (idx2, N).\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        f_centroid(&D_(idx2, j), D_(idx1, j), stc, s, t);\n        min = D_(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          f_centroid(&D_(idx2, j), D_(idx1, j), stc, s, t);\n          if (D_(idx2,j) < min) {\n            min = D_(idx2,j);\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n      break;\n    }\n\n    case METHOD_METR_MEDIAN: {\n      /*\n        Median linkage.\n\n        Shorter and longer distances can occur, not bigger than max(d1,d2)\n        but maybe smaller than min(d1,d2).\n      */\n      // Update the distance matrix in the range [start, idx1).\n      t_float c_4 = mindist[idx1]*.25;\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        f_median(&D_(j, idx2), D_(j, idx1), c_4 );\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n        else if (n_nghbr[j] == idx1)\n          n_nghbr[j] = idx2;\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for (; j<idx2; j=active_nodes.succ[j]) {\n        f_median(&D_(j, idx2), D_(idx1, j), c_4 );\n        if (D_(j, idx2) < mindist[j]) {\n          nn_distances.update_leq(j, D_(j, idx2));\n          n_nghbr[j] = idx2;\n        }\n      }\n      // Update the distance matrix in the range (idx2, N).\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        f_median(&D_(idx2, j), D_(idx1, j), c_4 );\n        min = D_(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          f_median(&D_(idx2, j), D_(idx1, j), c_4 );\n          if (D_(idx2,j) < min) {\n            min = D_(idx2,j);\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n      break;\n    }\n\n    default:\n      throw std::runtime_error(std::string(\"Invalid method.\"));\n    }\n  }\n  #ifdef FE_INVALID\n  if (fetestexcept(FE_INVALID)) throw fenv_error();\n  #endif\n}\n\n/*\n  Clustering methods for vector data\n*/\n\ntemplate <typename t_dissimilarity>\nstatic void MST_linkage_core_vector(const t_index N,\n                                    t_dissimilarity & dist,\n                                    cluster_result & Z2) {\n/*\n    N: integer, number of data points\n    dist: function pointer to the metric\n    Z2: output data structure\n\n    The basis of this algorithm is an algorithm by Rohlf:\n\n    F. James Rohlf, Hierarchical clustering using the minimum spanning tree,\n    The Computer Journal, vol. 16, 1973, p. 93–95.\n*/\n  t_index i;\n  t_index idx2;\n  doubly_linked_list active_nodes(N);\n  auto_array_ptr<t_float> d(N);\n\n  t_index prev_node;\n  t_float min;\n\n  // first iteration\n  idx2 = 1;\n  min = std::numeric_limits<t_float>::infinity();\n  for (i=1; i<N; ++i) {\n    d[i] = dist(0,i);\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n    if (d[i] < min) {\n      min = d[i];\n      idx2 = i;\n    }\n    else if (fc_isnan(d[i]))\n      throw (nan_error());\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n  }\n\n  Z2.append(0, idx2, min);\n\n  for (t_index j=1; j<N-1; ++j) {\n    prev_node = idx2;\n    active_nodes.remove(prev_node);\n\n    idx2 = active_nodes.succ[0];\n    min = d[idx2];\n\n    for (i=idx2; i<N; i=active_nodes.succ[i]) {\n      t_float tmp = dist(i, prev_node);\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wfloat-equal\"\n#endif\n      if (d[i] > tmp)\n        d[i] = tmp;\n      else if (fc_isnan(tmp))\n        throw (nan_error());\n#if HAVE_DIAGNOSTIC\n#pragma GCC diagnostic pop\n#endif\n      if (d[i] < min) {\n        min = d[i];\n        idx2 = i;\n      }\n    }\n    Z2.append(prev_node, idx2, min);\n  }\n}\n\ntemplate <method_codes_vector method, typename t_dissimilarity>\nstatic void generic_linkage_vector(const t_index N,\n                                   t_dissimilarity & dist,\n                                   cluster_result & Z2) {\n  /*\n    N: integer, number of data points\n    dist: function pointer to the metric\n    Z2: output data structure\n\n    This algorithm is valid for the distance update methods\n    \"Ward\", \"centroid\" and \"median\" only!\n  */\n  const t_index N_1 = N-1;\n  t_index i, j; // loop variables\n  t_index idx1, idx2; // row and column indices\n\n  auto_array_ptr<t_index> n_nghbr(N_1); // array of nearest neighbors\n  auto_array_ptr<t_float> mindist(N_1); // distances to the nearest neighbors\n  auto_array_ptr<t_index> row_repr(N); // row_repr[i]: node number that the\n                                       // i-th row represents\n  doubly_linked_list active_nodes(N);\n  binary_min_heap nn_distances(&*mindist, N_1); // minimum heap structure for\n                        // the distance to the nearest neighbor of each point\n  t_index node1, node2;     // node numbers in the output\n  t_float min; // minimum and row index for nearest-neighbor search\n\n  for (i=0; i<N; ++i)\n    // Build a list of row ↔ node label assignments.\n    // Initially i ↦ i\n    row_repr[i] = i;\n\n  // Initialize the minimal distances:\n  // Find the nearest neighbor of each point.\n  // n_nghbr[i] = argmin_{j>i} D(i,j) for i in range(N-1)\n  for (i=0; i<N_1; ++i) {\n    min = std::numeric_limits<t_float>::infinity();\n    t_index idx;\n    for (idx=j=i+1; j<N; ++j) {\n      t_float tmp;\n      switch (method) {\n      case METHOD_VECTOR_WARD:\n        tmp = dist.ward_initial(i,j);\n        break;\n      default:\n        tmp = dist.template sqeuclidean<true>(i,j);\n      }\n      if (tmp<min) {\n        min = tmp;\n        idx = j;\n      }\n    }\n    switch (method) {\n    case METHOD_VECTOR_WARD:\n      mindist[i] = t_dissimilarity::ward_initial_conversion(min);\n      break;\n    default:\n      mindist[i] = min;\n    }\n    n_nghbr[i] = idx;\n  }\n\n  // Put the minimal distances into a heap structure to make the repeated\n  // global minimum searches fast.\n  nn_distances.heapify();\n\n  // Main loop: We have N-1 merging steps.\n  for (i=0; i<N_1; ++i) {\n    idx1 = nn_distances.argmin();\n\n    while ( active_nodes.is_inactive(n_nghbr[idx1]) ) {\n      // Recompute the minimum mindist[idx1] and n_nghbr[idx1].\n      n_nghbr[idx1] = j = active_nodes.succ[idx1]; // exists, maximally N-1\n      switch (method) {\n      case METHOD_VECTOR_WARD:\n        min = dist.ward(idx1,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          t_float const tmp = dist.ward(idx1,j);\n          if (tmp<min) {\n            min = tmp;\n            n_nghbr[idx1] = j;\n          }\n        }\n        break;\n      default:\n        min = dist.template sqeuclidean<true>(idx1,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          t_float const tmp = dist.template sqeuclidean<true>(idx1,j);\n          if (tmp<min) {\n            min = tmp;\n            n_nghbr[idx1] = j;\n          }\n        }\n      }\n      /* Update the heap with the new true minimum and search for the (possibly\n         different) minimal entry. */\n      nn_distances.update_geq(idx1, min);\n      idx1 = nn_distances.argmin();\n    }\n\n    nn_distances.heap_pop(); // Remove the current minimum from the heap.\n    idx2 = n_nghbr[idx1];\n\n    // Write the newly found minimal pair of nodes to the output array.\n    node1 = row_repr[idx1];\n    node2 = row_repr[idx2];\n\n    Z2.append(node1, node2, mindist[idx1]);\n\n    switch (method) {\n    case METHOD_VECTOR_WARD:\n    case METHOD_VECTOR_CENTROID:\n      dist.merge_inplace(idx1, idx2);\n      break;\n    case METHOD_VECTOR_MEDIAN:\n      dist.merge_inplace_weighted(idx1, idx2);\n      break;\n    default:\n      throw std::runtime_error(std::string(\"Invalid method.\"));\n    }\n\n    // Index idx2 now represents the new (merged) node with label N+i.\n    row_repr[idx2] = N+i;\n    // Remove idx1 from the list of active indices (active_nodes).\n    active_nodes.remove(idx1);  // TBD later!!!\n\n    // Update the distance matrix\n    switch (method) {\n    case METHOD_VECTOR_WARD:\n      /*\n        Ward linkage.\n\n        Shorter and longer distances can occur, not smaller than min(d1,d2)\n        but maybe bigger than max(d1,d2).\n      */\n      // Update the distance matrix in the range [start, idx1).\n      for (j=active_nodes.start; j<idx1; j=active_nodes.succ[j]) {\n        if (n_nghbr[j] == idx2) {\n          n_nghbr[j] = idx1; // invalidate\n        }\n      }\n      // Update the distance matrix in the range (idx1, idx2).\n      for ( ; j<idx2; j=active_nodes.succ[j]) {\n        t_float const tmp = dist.ward(j, idx2);\n        if (tmp < mindist[j]) {\n          nn_distances.update_leq(j, tmp);\n          n_nghbr[j] = idx2;\n        }\n        else if (n_nghbr[j]==idx2) {\n          n_nghbr[j] = idx1; // invalidate\n        }\n      }\n      // Find the nearest neighbor for idx2.\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        min = dist.ward(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          t_float const tmp = dist.ward(idx2,j);\n          if (tmp < min) {\n            min = tmp;\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n      break;\n\n    default:\n      /*\n        Centroid and median linkage.\n\n        Shorter and longer distances can occur, not bigger than max(d1,d2)\n        but maybe smaller than min(d1,d2).\n      */\n      for (j=active_nodes.start; j<idx2; j=active_nodes.succ[j]) {\n        t_float const tmp = dist.template sqeuclidean<true>(j, idx2);\n        if (tmp < mindist[j]) {\n          nn_distances.update_leq(j, tmp);\n          n_nghbr[j] = idx2;\n        }\n        else if (n_nghbr[j] == idx2)\n          n_nghbr[j] = idx1; // invalidate\n      }\n      // Find the nearest neighbor for idx2.\n      if (idx2<N_1) {\n        n_nghbr[idx2] = j = active_nodes.succ[idx2]; // exists, maximally N-1\n        min = dist.template sqeuclidean<true>(idx2,j);\n        for (j=active_nodes.succ[j]; j<N; j=active_nodes.succ[j]) {\n          t_float const tmp = dist.template sqeuclidean<true>(idx2, j);\n          if (tmp < min) {\n            min = tmp;\n            n_nghbr[idx2] = j;\n          }\n        }\n        nn_distances.update(idx2, min);\n      }\n    }\n  }\n}\n\ntemplate <method_codes_vector method, typename t_dissimilarity>\nstatic void generic_linkage_vector_alternative(const t_index N,\n                                               t_dissimilarity & dist,\n                                               cluster_result & Z2) {\n  /*\n    N: integer, number of data points\n    dist: function pointer to the metric\n    Z2: output data structure\n\n    This algorithm is valid for the distance update methods\n    \"Ward\", \"centroid\" and \"median\" only!\n  */\n  const t_index N_1 = N-1;\n  t_index i, j=0; // loop variables\n  t_index idx1, idx2; // row and column indices\n\n  auto_array_ptr<t_index> n_nghbr(2*N-2); // array of nearest neighbors\n  auto_array_ptr<t_float> mindist(2*N-2); // distances to the nearest neighbors\n\n  doubly_linked_list active_nodes(N+N_1);\n  binary_min_heap nn_distances(&*mindist, N_1, 2*N-2, 1); // minimum heap\n      // structure for the distance to the nearest neighbor of each point\n\n  t_float min; // minimum for nearest-neighbor searches\n\n  // Initialize the minimal distances:\n  // Find the nearest neighbor of each point.\n  // n_nghbr[i] = argmin_{j>i} D(i,j) for i in range(N-1)\n  for (i=1; i<N; ++i) {\n    min = std::numeric_limits<t_float>::infinity();\n    t_index idx;\n    for (idx=j=0; j<i; ++j) {\n      t_float tmp;\n      switch (method) {\n      case METHOD_VECTOR_WARD:\n        tmp = dist.ward_initial(i,j);\n        break;\n      default:\n        tmp = dist.template sqeuclidean<true>(i,j);\n      }\n      if (tmp<min) {\n        min = tmp;\n        idx = j;\n      }\n    }\n    switch (method) {\n    case METHOD_VECTOR_WARD:\n      mindist[i] = t_dissimilarity::ward_initial_conversion(min);\n      break;\n    default:\n      mindist[i] = min;\n    }\n    n_nghbr[i] = idx;\n  }\n\n  // Put the minimal distances into a heap structure to make the repeated\n  // global minimum searches fast.\n  nn_distances.heapify();\n\n  // Main loop: We have N-1 merging steps.\n  for (i=N; i<N+N_1; ++i) {\n    /*\n      The bookkeeping is different from the \"stored matrix approach\" algorithm\n      generic_linkage.\n\n      mindist[i] stores a lower bound on the minimum distance of the point i to\n      all points of *lower* index:\n\n          mindist[i] ≥ min_{j<i} D(i,j)\n\n      Moreover, new nodes do not re-use one of the old indices, but they are\n      given a new, unique index (SciPy convention: initial nodes are 0,…,N−1,\n      new nodes are N,…,2N−2).\n\n      Invalid nearest neighbors are not recognized by the fact that the stored\n      distance is smaller than the actual distance, but the list active_nodes\n      maintains a flag whether a node is inactive. If n_nghbr[i] points to an\n      active node, the entries nn_distances[i] and n_nghbr[i] are valid,\n      otherwise they must be recomputed.\n    */\n    idx1 = nn_distances.argmin();\n    while ( active_nodes.is_inactive(n_nghbr[idx1]) ) {\n      // Recompute the minimum mindist[idx1] and n_nghbr[idx1].\n      n_nghbr[idx1] = j = active_nodes.start;\n      switch (method) {\n      case METHOD_VECTOR_WARD:\n        min = dist.ward_extended(idx1,j);\n        for (j=active_nodes.succ[j]; j<idx1; j=active_nodes.succ[j]) {\n          t_float tmp = dist.ward_extended(idx1,j);\n          if (tmp<min) {\n            min = tmp;\n            n_nghbr[idx1] = j;\n          }\n        }\n        break;\n      default:\n        min = dist.sqeuclidean_extended(idx1,j);\n        for (j=active_nodes.succ[j]; j<idx1; j=active_nodes.succ[j]) {\n          t_float const tmp = dist.sqeuclidean_extended(idx1,j);\n          if (tmp<min) {\n            min = tmp;\n            n_nghbr[idx1] = j;\n          }\n        }\n      }\n      /* Update the heap with the new true minimum and search for the (possibly\n         different) minimal entry. */\n      nn_distances.update_geq(idx1, min);\n      idx1 = nn_distances.argmin();\n    }\n\n    idx2 = n_nghbr[idx1];\n    active_nodes.remove(idx1);\n    active_nodes.remove(idx2);\n\n    Z2.append(idx1, idx2, mindist[idx1]);\n\n    if (i<2*N_1) {\n      switch (method) {\n      case METHOD_VECTOR_WARD:\n      case METHOD_VECTOR_CENTROID:\n        dist.merge(idx1, idx2, i);\n        break;\n\n      case METHOD_VECTOR_MEDIAN:\n        dist.merge_weighted(idx1, idx2, i);\n        break;\n\n      default:\n        throw std::runtime_error(std::string(\"Invalid method.\"));\n      }\n\n      n_nghbr[i] = active_nodes.start;\n      if (method==METHOD_VECTOR_WARD) {\n        /*\n          Ward linkage.\n\n          Shorter and longer distances can occur, not smaller than min(d1,d2)\n          but maybe bigger than max(d1,d2).\n        */\n        min = dist.ward_extended(active_nodes.start, i);\n        for (j=active_nodes.succ[active_nodes.start]; j<i;\n             j=active_nodes.succ[j]) {\n          t_float tmp = dist.ward_extended(j, i);\n          if (tmp < min) {\n            min = tmp;\n            n_nghbr[i] = j;\n          }\n        }\n      }\n      else {\n        /*\n          Centroid and median linkage.\n\n          Shorter and longer distances can occur, not bigger than max(d1,d2)\n          but maybe smaller than min(d1,d2).\n        */\n        min = dist.sqeuclidean_extended(active_nodes.start, i);\n        for (j=active_nodes.succ[active_nodes.start]; j<i;\n             j=active_nodes.succ[j]) {\n          t_float tmp = dist.sqeuclidean_extended(j, i);\n          if (tmp < min) {\n            min = tmp;\n            n_nghbr[i] = j;\n          }\n        }\n      }\n      if (idx2<active_nodes.start)  {\n        nn_distances.remove(active_nodes.start);\n      } else {\n        nn_distances.remove(idx2);\n      }\n      nn_distances.replace(idx1, i, min);\n    }\n  }\n}\n\n#if HAVE_VISIBILITY\n#pragma GCC visibility pop\n#endif\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/fastcluster_py.py",
    "content": "import os\nimport numpy as np\n\nfrom cffi import FFI\nfrom common.ffi_wrapper import suffix\n\ncluster_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)))\ncluster_fn = os.path.join(cluster_dir, \"libfastcluster\"+suffix())\n\nffi = FFI()\nffi.cdef(\"\"\"\nint hclust_fast(int n, double* distmat, int method, int* merge, double* height);\nvoid cutree_cdist(int n, const int* merge, double* height, double cdist, int* labels);\nvoid hclust_pdist(int n, int m, double* pts, double* out);\nvoid cluster_points_centroid(int n, int m, double* pts, double dist, int* idx);\n\"\"\")\n\nhclust = ffi.dlopen(cluster_fn)\n\n\ndef cluster_points_centroid(pts, dist):\n  pts = np.ascontiguousarray(pts, dtype=np.float64)\n  pts_ptr = ffi.cast(\"double *\", pts.ctypes.data)\n  n, m = pts.shape\n\n  labels_ptr = ffi.new(\"int[]\", n)\n  hclust.cluster_points_centroid(n, m, pts_ptr, dist**2, labels_ptr)\n  return list(labels_ptr)\n"
  },
  {
    "path": "selfdrive/controls/lib/cluster/test.cpp",
    "content": "#include <cassert>\n\nextern \"C\" {\n#include \"fastcluster.h\"\n}\n\n\nint main(int argc, const char* argv[]) {\n  const int n = 11;\n  const int m = 3;\n  double* pts = new double[n*m]{59.26000137, -9.35999966, -5.42500019,\n                                91.61999817, -0.31999999, -2.75,\n                                31.38000031, 0.40000001, -0.2,\n                                89.57999725, -8.07999992, -18.04999924,\n                                53.42000122, 0.63999999, -0.175,\n                                31.38000031, 0.47999999, -0.2,\n                                36.33999939, 0.16, -0.2,\n                                53.33999939, 0.95999998, -0.175,\n                                59.26000137, -9.76000023, -5.44999981,\n                                33.93999977, 0.40000001, -0.22499999,\n                                106.74000092, -5.76000023, -18.04999924};\n\n  int * idx = new int[n];\n  int * correct_idx = new int[n]{0, 1, 2, 3, 4, 2, 5, 4, 0, 5, 6};\n\n  cluster_points_centroid(n, m, pts, 2.5 * 2.5, idx);\n\n  for (int i = 0; i < n; i++) {\n    assert(idx[i] == correct_idx[i]);\n  }\n\n  delete[] idx;\n  delete[] correct_idx;\n  delete[] pts;\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/drive_helpers.py",
    "content": "from cereal import car\nfrom common.numpy_fast import clip, interp\nfrom common.realtime import DT_MDL\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.modeld.constants import T_IDXS\n\n\n# kph\nV_CRUISE_MAX = 135\nV_CRUISE_MIN = 8\nV_CRUISE_DELTA = 8\nV_CRUISE_ENABLE_MIN = 40\nLAT_MPC_N = 16\nLON_MPC_N = 32\nCONTROL_N = 17\nCAR_ROTATION_RADIUS = 0.0\n\n# this corresponds to 80deg/s and 20deg/s steering angle in a toyota corolla\nMAX_CURVATURE_RATES = [0.03762194918267951, 0.003441203371932992]\nMAX_CURVATURE_RATE_SPEEDS = [0, 35]\n\n# Constants for Limit controllers.\nLIMIT_ADAPT_ACC = -0.6  # (closer to zero ealier it decel) m/s^2 Ideal acceleration for the adapting (braking) phase when approaching speed limits.\nLIMIT_MIN_ACC = -1.0  # m/s^2 Maximum deceleration allowed for limit controllers to provide.\nLIMIT_MAX_ACC = 1.0   # m/s^2 Maximum acelration allowed for limit controllers to provide while active.\nLIMIT_MIN_SPEED = 8.33  # m/s, Minimum speed limit to provide as solution on limit controllers.\nLIMIT_SPEED_OFFSET_TH = -1.  # m/s Maximum offset between speed limit and current speed for adapting state.\nLIMIT_MAX_MAP_DATA_AGE = 10.  # s Maximum time to hold to map data, then consider it invalid inside limits controllers.\n\n\nclass MPC_COST_LAT:\n  PATH = 1.0\n  HEADING = 1.0\n  STEER_RATE = 1.0\n\n\nclass MPC_COST_LONG:\n  TTC = 5.5\n  DISTANCE = 0.1\n  ACCELERATION = 10.0\n  JERK = 20.0\n\n\ndef rate_limit(new_value, last_value, dw_step, up_step):\n  return clip(new_value, last_value + dw_step, last_value + up_step)\n\n\ndef get_steer_max(CP, v_ego):\n  return interp(v_ego, CP.steerMaxBP, CP.steerMaxV)\n\n\ndef update_v_cruise(v_cruise_kph, buttonEvents, enabled):\n  # handle button presses. TODO: this should be in state_control, but a decelCruise press\n  # would have the effect of both enabling and changing speed is checked after the state transition\n  for b in buttonEvents:\n    if enabled and not b.pressed:\n      if b.type == car.CarState.ButtonEvent.Type.accelCruise:\n        v_cruise_kph += V_CRUISE_DELTA - (v_cruise_kph % V_CRUISE_DELTA)\n      elif b.type == car.CarState.ButtonEvent.Type.decelCruise:\n        v_cruise_kph -= V_CRUISE_DELTA - ((V_CRUISE_DELTA - v_cruise_kph) % V_CRUISE_DELTA)\n      v_cruise_kph = clip(v_cruise_kph, V_CRUISE_MIN, V_CRUISE_MAX)\n\n  return v_cruise_kph\n\n\ndef initialize_v_cruise(v_ego, buttonEvents, v_cruise_last):\n  for b in buttonEvents:\n    # 250kph or above probably means we never had a set speed\n    if b.type == car.CarState.ButtonEvent.Type.accelCruise and v_cruise_last < 250:\n      return v_cruise_last\n\n  return int(round(clip(v_ego * CV.MS_TO_KPH, V_CRUISE_ENABLE_MIN, V_CRUISE_MAX)))\n\n\ndef get_lag_adjusted_curvature(CP, v_ego, psis, curvatures, curvature_rates):\n  if len(psis) != CONTROL_N:\n    psis = [0.0 for i in range(CONTROL_N)]\n    curvatures = [0.0 for i in range(CONTROL_N)]\n    curvature_rates = [0.0 for i in range(CONTROL_N)]\n\n  # TODO this needs more thought, use .2s extra for now to estimate other delays\n  delay = CP.steerActuatorDelay + .2\n  current_curvature = curvatures[0]\n  psi = interp(delay, T_IDXS[:CONTROL_N], psis)\n  desired_curvature_rate = curvature_rates[0]\n\n  # MPC can plan to turn the wheel and turn back before t_delay. This means\n  # in high delay cases some corrections never even get commanded. So just use\n  # psi to calculate a simple linearization of desired curvature\n  curvature_diff_from_psi = psi / (max(v_ego, 1e-1) * delay) - current_curvature\n  desired_curvature = current_curvature + 2 * curvature_diff_from_psi\n\n  max_curvature_rate = interp(v_ego, MAX_CURVATURE_RATE_SPEEDS, MAX_CURVATURE_RATES)\n  safe_desired_curvature_rate = clip(desired_curvature_rate,\n                                          -max_curvature_rate,\n                                          max_curvature_rate)\n  safe_desired_curvature = clip(desired_curvature,\n                                     current_curvature - max_curvature_rate/DT_MDL,\n                                     current_curvature + max_curvature_rate/DT_MDL)\n  return safe_desired_curvature, safe_desired_curvature_rate\n"
  },
  {
    "path": "selfdrive/controls/lib/events.py",
    "content": "# This Python file uses the following encoding: utf-8\n# -*- coding: utf-8 -*-\nfrom enum import IntEnum\nfrom typing import Dict, Union, Callable, Any\n\nfrom cereal import log, car\nimport cereal.messaging as messaging\nfrom common.realtime import DT_CTRL\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.locationd.calibrationd import MIN_SPEED_FILTER\nfrom common.i18n import events\n_ = events()\n\nAlertSize = log.ControlsState.AlertSize\nAlertStatus = log.ControlsState.AlertStatus\nVisualAlert = car.CarControl.HUDControl.VisualAlert\nAudibleAlert = car.CarControl.HUDControl.AudibleAlert\nEventName = car.CarEvent.EventName\n\n\n# Alert priorities\nclass Priority(IntEnum):\n  LOWEST = 0\n  LOWER = 1\n  LOW = 2\n  MID = 3\n  HIGH = 4\n  HIGHEST = 5\n\n\n# Event types\nclass ET:\n  ENABLE = 'enable'\n  PRE_ENABLE = 'preEnable'\n  NO_ENTRY = 'noEntry'\n  WARNING = 'warning'\n  USER_DISABLE = 'userDisable'\n  SOFT_DISABLE = 'softDisable'\n  IMMEDIATE_DISABLE = 'immediateDisable'\n  PERMANENT = 'permanent'\n\n\n# get event name from enum\nEVENT_NAME = {v: k for k, v in EventName.schema.enumerants.items()}\n\n\nclass Events:\n  def __init__(self):\n    self.events = []\n    self.static_events = []\n    self.events_prev = dict.fromkeys(EVENTS.keys(), 0)\n\n  @property\n  def names(self):\n    return self.events\n\n  def __len__(self):\n    return len(self.events)\n\n  def add(self, event_name, static=False):\n    if static:\n      self.static_events.append(event_name)\n    self.events.append(event_name)\n\n  def clear(self):\n    self.events_prev = {k: (v + 1 if k in self.events else 0) for k, v in self.events_prev.items()}\n    self.events = self.static_events.copy()\n\n  def any(self, event_type):\n    for e in self.events:\n      if event_type in EVENTS.get(e, {}).keys():\n        return True\n    return False\n\n  def create_alerts(self, event_types, callback_args=None):\n    if callback_args is None:\n      callback_args = []\n\n    ret = []\n    for e in self.events:\n      types = EVENTS[e].keys()\n      for et in event_types:\n        if et in types:\n          alert = EVENTS[e][et]\n          if not isinstance(alert, Alert):\n            alert = alert(*callback_args)\n\n          if DT_CTRL * (self.events_prev[e] + 1) >= alert.creation_delay:\n            alert.alert_type = f\"{EVENT_NAME[e]}/{et}\"\n            alert.event_type = et\n            ret.append(alert)\n    return ret\n\n  def add_from_msg(self, events):\n    for e in events:\n      self.events.append(e.name.raw)\n\n  def to_msg(self):\n    ret = []\n    for event_name in self.events:\n      event = car.CarEvent.new_message()\n      event.name = event_name\n      for event_type in EVENTS.get(event_name, {}).keys():\n        setattr(event, event_type, True)\n      ret.append(event)\n    return ret\n\n\nclass Alert:\n  def __init__(self,\n               alert_text_1: str,\n               alert_text_2: str,\n               alert_status: log.ControlsState.AlertStatus,\n               alert_size: log.ControlsState.AlertSize,\n               alert_priority: Priority,\n               visual_alert: car.CarControl.HUDControl.VisualAlert,\n               audible_alert: car.CarControl.HUDControl.AudibleAlert,\n               duration_sound: float,\n               duration_hud_alert: float,\n               duration_text: float,\n               alert_rate: float = 0.,\n               creation_delay: float = 0.):\n\n    self.alert_text_1 = alert_text_1\n    self.alert_text_2 = alert_text_2\n    self.alert_status = alert_status\n    self.alert_size = alert_size\n    self.alert_priority = alert_priority\n    self.visual_alert = visual_alert\n    self.audible_alert = audible_alert\n\n    self.duration_sound = duration_sound\n    self.duration_hud_alert = duration_hud_alert\n    self.duration_text = duration_text\n\n    self.alert_rate = alert_rate\n    self.creation_delay = creation_delay\n\n    self.start_time = 0.\n    self.alert_type = \"\"\n    self.event_type = None\n\n  def __str__(self) -> str:\n    return f\"{self.alert_text_1}/{self.alert_text_2} {self.alert_priority} {self.visual_alert} {self.audible_alert}\"\n\n  def __gt__(self, alert2) -> bool:\n    return self.alert_priority > alert2.alert_priority\n\n\nclass NoEntryAlert(Alert):\n  def __init__(self, alert_text_2, audible_alert=AudibleAlert.chimeError,\n               visual_alert=VisualAlert.none, duration_hud_alert=2.):\n    super().__init__(_(\"openpilot Unavailable\"), alert_text_2, AlertStatus.normal,\n                     AlertSize.mid, Priority.LOW, visual_alert,\n                     audible_alert, .4, duration_hud_alert, 3.)\n\n\nclass SoftDisableAlert(Alert):\n  def __init__(self, alert_text_2):\n    super().__init__(_(\"TAKE CONTROL IMMEDIATELY\"), alert_text_2,\n                     AlertStatus.critical, AlertSize.full,\n                     Priority.MID, VisualAlert.steerRequired,\n                     AudibleAlert.chimeWarningRepeat, .1, 2., 2.),\n\n\nclass ImmediateDisableAlert(Alert):\n  def __init__(self, alert_text_2, alert_text_1=_(\"TAKE CONTROL IMMEDIATELY\")):\n    super().__init__(alert_text_1, alert_text_2,\n                     AlertStatus.critical, AlertSize.full,\n                     Priority.HIGHEST, VisualAlert.steerRequired,\n                     AudibleAlert.chimeWarningRepeat, 2.2, 3., 4.),\n\n\nclass EngagementAlert(Alert):\n  def __init__(self, audible_alert=True):\n    super().__init__(\"\", \"\",\n                     AlertStatus.normal, AlertSize.none,\n                     Priority.MID, VisualAlert.none,\n                     audible_alert, 1., 0., 0.),\n\n\nclass NormalPermanentAlert(Alert):\n  def __init__(self, alert_text_1: str, alert_text_2: str, duration_text: float = 0.2):\n    super().__init__(alert_text_1, alert_text_2,\n                     AlertStatus.normal, AlertSize.mid if len(alert_text_2) else AlertSize.small,\n                     Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., duration_text),\n\n\n# ********** alert callback functions **********\ndef below_steer_speed_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  speed = int(round(CP.minSteerSpeed * (CV.MS_TO_KPH if metric else CV.MS_TO_MPH)))\n  unit = \"km/h\" if metric else \"mph\"\n  return Alert(\n    _(\"TAKE CONTROL\"),\n    _(\"Steer Unavailable Below %(speed)d %(unit)s\") % ({\"speed\": speed, \"unit\": unit}),\n    AlertStatus.userPrompt, AlertSize.mid,\n    Priority.MID, VisualAlert.steerRequired, AudibleAlert.chimePrompt, 0., 0.4, .3)\n\n\ndef calibration_incomplete_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  speed = int(MIN_SPEED_FILTER * (CV.MS_TO_KPH if metric else CV.MS_TO_MPH))\n  unit = \"km/h\" if metric else \"mph\"\n  return Alert(\n    _(\"Calibration in Progress: %d%%\") % sm['liveCalibration'].calPerc,\n    _(\"Drive Above %(speed)d %(unit)s\") % ({\"speed\": speed, \"unit\": unit}),\n    AlertStatus.normal, AlertSize.mid,\n    Priority.LOWEST, VisualAlert.none, AudibleAlert.none, 0., 0., .2)\n\n\ndef no_gps_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  gps_integrated = sm['pandaState'].pandaType in [log.PandaState.PandaType.uno, log.PandaState.PandaType.dos]\n  return Alert(\n    _(\"Poor GPS reception\"),\n    _(\"If sky is visible, contact support\") if gps_integrated else _(\"Check GPS antenna placement\"),\n    AlertStatus.normal, AlertSize.mid,\n    Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2, creation_delay=300.)\n\n\ndef wrong_car_mode_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  text = _(\"Cruise Mode Disabled\")\n  if CP.carName == \"honda\":\n    text = _(\"Main Switch Off\")\n  return NoEntryAlert(text, duration_hud_alert=0.)\n\n\ndef startup_fuzzy_fingerprint_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  return Alert(\n    _(\"WARNING: No Exact Match on Car Model\"),\n    f\"Closest Match: {CP.carFingerprint.title()[:40]}\",\n    AlertStatus.userPrompt, AlertSize.mid,\n    Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 10.)\n\n\ndef joystick_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  axes = sm['testJoystick'].axes\n  gb, steer = list(axes)[:2] if len(axes) else (0., 0.)\n  return Alert(\n    _(\"Joystick Mode\"),\n    f\"Gas: {round(gb * 100.)}%, Steer: {round(steer * 100.)}%\",\n    AlertStatus.normal, AlertSize.mid,\n    Priority.LOW, VisualAlert.none, AudibleAlert.none, 0., 0., .1)\n\ndef alca_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  return Alert(\n    _(\"Auto Lane Change starts in %.1f secs\") % float(sm['lateralPlan'].dpALCAStartIn),\n    _(\"Monitor Other Vehicles\"),\n    AlertStatus.normal, AlertSize.mid,\n    Priority.LOWER, VisualAlert.steerRequired, AudibleAlert.none, 0., .1, .1, alert_rate=0.1)\n\ndef speed_limit_adjust_alert(CP: car.CarParams, sm: messaging.SubMaster, metric: bool) -> Alert:\n  speedLimit = sm['longitudinalPlan'].speedLimit\n  speed = round(speedLimit * (CV.MS_TO_KPH if metric else CV.MS_TO_MPH))\n  message = f'Adjusting to {speed} {\"km/h\" if metric else \"mph\"} speed limit'\n  return Alert(\n    message,\n    \"\",\n    AlertStatus.normal, AlertSize.small,\n    Priority.LOW, VisualAlert.none, AudibleAlert.none, 0., 0., 4.)\n\nEVENTS: Dict[int, Dict[str, Union[Alert, Callable[[Any, messaging.SubMaster, bool], Alert]]]] = {\n  # ********** events with no alerts **********\n\n  EventName.stockFcw: {},\n\n  # ********** events only containing alerts displayed in all states **********\n\n  EventName.joystickDebug: {\n    ET.WARNING: joystick_alert,\n    ET.PERMANENT: Alert(\n      _(\"Joystick Mode\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 0.1),\n  },\n\n  EventName.controlsInitializing: {\n    ET.NO_ENTRY: NoEntryAlert(\"Controls Initializing\"),\n  },\n\n  EventName.startup: {\n    ET.PERMANENT: Alert(\n      _(\"Be ready to take over at any time\"),\n      _(\"Always keep hands on wheel and eyes on road\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 5.),\n  },\n\n  EventName.startupMaster: {\n    ET.PERMANENT: Alert(\n      _(\"WARNING: This branch is not tested\"),\n      _(\"Always keep hands on wheel and eyes on road\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 10.),\n  },\n\n  # Car is recognized, but marked as dashcam only\n  EventName.startupNoControl: {\n    ET.PERMANENT: Alert(\n      _(\"Dashcam mode\"),\n      _(\"Always keep hands on wheel and eyes on road\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 10.),\n  },\n\n  # Car is not recognized\n  EventName.startupNoCar: {\n    ET.PERMANENT: Alert(\n      _(\"Dashcam mode for unsupported car\"),\n      _(\"Always keep hands on wheel and eyes on road\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 10.),\n  },\n\n  # openpilot uses the version strings from various ECUs to detect the correct car model.\n  # Usually all ECUs are recognized and an exact match to a car model can be made. Sometimes\n  # one or two ECUs have unrecognized versions, but the others are present in the database.\n  # If openpilot is confident about the match to a car model, it fingerprints anyway.\n  # In this case an alert is thrown since there is a small chance the wrong car was detected\n  # and the user should pay extra attention.\n  # This alert can be prevented by adding all ECU firmware version to openpilot:\n  # https://github.com/commaai/openpilot/wiki/Fingerprinting\n  EventName.startupFuzzyFingerprint: {\n    ET.PERMANENT: startup_fuzzy_fingerprint_alert,\n  },\n\n  EventName.startupNoFw: {\n    ET.PERMANENT: Alert(\n      _(\"Car Unrecognized\"),\n      _(\"Check All Connections\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., 10.),\n  },\n\n  EventName.dashcamMode: {\n    ET.PERMANENT: Alert(\n      _(\"Dashcam Mode\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWEST, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n  },\n\n  EventName.invalidLkasSetting: {\n    ET.PERMANENT: Alert(\n      _(\"Stock LKAS is turned on\"),\n      _(\"Turn off stock LKAS to engage\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n  },\n\n  # Some features or cars are marked as community features. If openpilot\n  # detects the use of a community feature it switches to dashcam mode\n  # until these features are allowed using a toggle in settings.\n  EventName.communityFeatureDisallowed: {\n    # LOW priority to overcome Cruise Error\n    ET.PERMANENT: Alert(\n      _(\"openpilot Not Available\"),\n      _(\"Enable Community Features in Settings to Engage\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n  },\n\n  # openpilot doesn't recognize the car. This switches openpilot into a\n  # read-only mode. This can be solved by adding your fingerprint.\n  # See https://github.com/commaai/openpilot/wiki/Fingerprinting for more information\n  EventName.carUnrecognized: {\n    ET.PERMANENT: Alert(\n      _(\"Dashcam Mode\"),\n      _(\"Car Unrecognized\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOWEST, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n  },\n\n  EventName.stockAeb: {\n    ET.PERMANENT: Alert(\n      _(\"BRAKE!\"),\n      _(\"Stock AEB: Risk of Collision\"),\n      AlertStatus.critical, AlertSize.full,\n      Priority.HIGHEST, VisualAlert.fcw, AudibleAlert.none, 1., 2., 2.),\n    ET.NO_ENTRY: NoEntryAlert(\"Stock AEB: Risk of Collision\"),\n  },\n\n  EventName.fcw: {\n    ET.PERMANENT: Alert(\n      _(\"BRAKE!\"),\n      _(\"Risk of Collision\"),\n      AlertStatus.critical, AlertSize.full,\n      Priority.HIGHEST, VisualAlert.fcw, AudibleAlert.chimeWarningRepeat, 1., 2., 2.),\n  },\n\n  EventName.ldw: {\n    ET.PERMANENT: Alert(\n      _(\"TAKE CONTROL\"),\n      _(\"Lane Departure Detected\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.LOW, VisualAlert.ldw, AudibleAlert.chimePrompt, 1., 2., 3.),\n  },\n\n  # ********** events only containing alerts that display while engaged **********\n\n  EventName.gasPressed: {\n    ET.PRE_ENABLE: Alert(\n      _(\"openpilot will not brake while gas pressed\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWEST, VisualAlert.none, AudibleAlert.none, .0, .0, .1, creation_delay=1.),\n  },\n\n  # openpilot tries to learn certain parameters about your car by observing\n  # how the car behaves to steering inputs from both human and openpilot driving.\n  # This includes:\n  # - steer ratio: gear ratio of the steering rack. Steering angle divided by tire angle\n  # - tire stiffness: how much grip your tires have\n  # - angle offset: most steering angle sensors are offset and measure a non zero angle when driving straight\n  # This alert is thrown when any of these values exceed a sanity check. This can be caused by\n  # bad alignment or bad sensor data. If this happens consistently consider creating an issue on GitHub\n  EventName.vehicleModelInvalid: {\n    ET.NO_ENTRY: NoEntryAlert(\"Vehicle Parameter Identification Failed\"),\n    ET.SOFT_DISABLE: SoftDisableAlert(\"Vehicle Parameter Identification Failed\"),\n    ET.WARNING: Alert(\n      _(\"Vehicle Parameter Identification Failed\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWEST, VisualAlert.steerRequired, AudibleAlert.none, .0, .0, .1),\n  },\n\n  EventName.steerTempUnavailableSilent: {\n    ET.WARNING: Alert(\n      _(\"Steering Temporarily Unavailable\"),\n      \"\",\n      AlertStatus.userPrompt, AlertSize.small,\n      Priority.LOW, VisualAlert.steerRequired, AudibleAlert.chimePrompt, 1., 1., 1.),\n  },\n\n  EventName.preDriverDistracted: {\n    ET.WARNING: Alert(\n      _(\"KEEP EYES ON ROAD: Driver Distracted\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, .0, .1, .1),\n  },\n\n  EventName.promptDriverDistracted: {\n    ET.WARNING: Alert(\n      _(\"KEEP EYES ON ROAD\"),\n      _(\"Driver Distracted\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.MID, VisualAlert.steerRequired, AudibleAlert.chimeWarning2Repeat, 1., .1, .1),\n  },\n\n  EventName.driverDistracted: {\n    ET.WARNING: Alert(\n      _(\"DISENGAGE IMMEDIATELY\"),\n      _(\"Driver Distracted\"),\n      AlertStatus.critical, AlertSize.full,\n      Priority.HIGH, VisualAlert.steerRequired, AudibleAlert.chimeWarningRepeat, .1, .1, .1),\n  },\n\n  EventName.preDriverUnresponsive: {\n    ET.WARNING: Alert(\n      _(\"TOUCH STEERING WHEEL: No Face Detected\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.steerRequired, AudibleAlert.none, .0, .1, .1, alert_rate=0.75),\n  },\n\n  EventName.promptDriverUnresponsive: {\n    ET.WARNING: Alert(\n      _(\"TOUCH STEERING WHEEL\"),\n      _(\"Driver Unresponsive\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.MID, VisualAlert.steerRequired, AudibleAlert.chimeWarning2Repeat, 1., .1, .1),\n  },\n\n  EventName.driverUnresponsive: {\n    ET.WARNING: Alert(\n      _(\"DISENGAGE IMMEDIATELY\"),\n      _(\"Driver Unresponsive\"),\n      AlertStatus.critical, AlertSize.full,\n      Priority.HIGH, VisualAlert.steerRequired, AudibleAlert.chimeWarningRepeat, .1, .1, .1),\n  },\n\n  EventName.manualRestart: {\n    ET.WARNING: Alert(\n      _(\"TAKE CONTROL\"),\n      _(\"Resume Driving Manually\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n  },\n\n  EventName.resumeRequired: {\n    ET.WARNING: Alert(\n      _(\"STOPPED\"),\n      _(\"Press Resume to Move\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n  },\n\n  EventName.belowSteerSpeed: {\n    ET.WARNING: below_steer_speed_alert,\n  },\n\n  EventName.preLaneChangeLeft: {\n    ET.WARNING: Alert(\n      _(\"Steer Left to Start Lane Change Once Safe\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, .0, .1, .1, alert_rate=0.75),\n  },\n\n  EventName.preLaneChangeRight: {\n    ET.WARNING: Alert(\n      _(\"Steer Right to Start Lane Change Once Safe\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, .0, .1, .1, alert_rate=0.75),\n  },\n\n  EventName.laneChangeBlocked: {\n    ET.WARNING: Alert(\n      _(\"Car Detected in Blindspot\"),\n      \"\",\n      AlertStatus.userPrompt, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.chimePrompt, .1, .1, .1),\n  },\n\n  EventName.laneChange: {\n    ET.WARNING: Alert(\n      _(\"Changing Lanes\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, .0, .1, .1),\n  },\n\n  EventName.steerSaturated: {\n    ET.WARNING: Alert(\n      _(\"TAKE CONTROL\"),\n      _(\"Turn Exceeds Steering Limit\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.LOW, VisualAlert.steerRequired, AudibleAlert.chimePrompt, 1., 1., 1.),\n  },\n\n  # Thrown when the fan is driven at >50% but is not rotating\n  EventName.fanMalfunction: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Fan Malfunction\"), _(\"Contact Support\")),\n  },\n\n  # Camera is not outputting frames at a constant framerate\n  EventName.cameraMalfunction: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Camera Malfunction\"), _(\"Contact Support\")),\n  },\n\n  # Unused\n  EventName.gpsMalfunction: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"GPS Malfunction\"), _(\"Contact Support\")),\n  },\n\n  # When the GPS position and localizer diverge the localizer is reset to the\n  # current GPS position. This alert is thrown when the localizer is reset\n  # more often than expected.\n  EventName.localizerMalfunction: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Sensor Malfunction\"), _(\"Contact Support\")),\n  },\n\n  EventName.speedLimitActive: {\n    ET.WARNING: Alert(\n      \"Cruise set to speed limit\",\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, 1., 0., 2.),\n  },\n\n  EventName.speedLimitValueChange: {\n    ET.WARNING: speed_limit_adjust_alert,\n  },\n\n  # ********** events that affect controls state transitions **********\n\n  EventName.pcmEnable: {\n    ET.ENABLE: EngagementAlert(AudibleAlert.chimeEngage),\n  },\n\n  EventName.buttonEnable: {\n    ET.ENABLE: EngagementAlert(AudibleAlert.chimeEngage),\n  },\n\n  EventName.pcmDisable: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n  },\n\n  EventName.buttonCancel: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n  },\n\n  EventName.brakeHold: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Brake Hold Active\")),\n  },\n\n  EventName.parkBrake: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Park Brake Engaged\")),\n  },\n\n  EventName.pedalPressed: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Pedal Pressed During Attempt\"),\n                              visual_alert=VisualAlert.brakePressed),\n  },\n\n  EventName.wrongCarMode: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n    ET.NO_ENTRY: wrong_car_mode_alert,\n  },\n\n  EventName.wrongCruiseMode: {\n    ET.USER_DISABLE: EngagementAlert(AudibleAlert.chimeDisengage),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Enable Adaptive Cruise\")),\n  },\n\n  EventName.steerTempUnavailable: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Steering Temporarily Unavailable\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Steering Temporarily Unavailable\"),\n                              duration_hud_alert=0.),\n  },\n\n  EventName.outOfSpace: {\n    ET.PERMANENT: Alert(\n      _(\"Out of Storage\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Out of Storage Space\"),\n                              duration_hud_alert=0.),\n  },\n\n  EventName.belowEngageSpeed: {\n    ET.NO_ENTRY: NoEntryAlert(_(\"Speed Too Low\")),\n  },\n\n  EventName.sensorDataInvalid: {\n    ET.PERMANENT: Alert(\n      _(\"No Data from Device Sensors\"),\n      _(\"Reboot your Device\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2, creation_delay=1.),\n    ET.NO_ENTRY: NoEntryAlert(_(\"No Data from Device Sensors\")),\n  },\n\n  EventName.noGps: {\n    ET.PERMANENT: no_gps_alert,\n  },\n\n  EventName.soundsUnavailable: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Speaker not found\"), _(\"Reboot your Device\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Speaker not found\")),\n  },\n\n  EventName.tooDistracted: {\n    ET.NO_ENTRY: NoEntryAlert(_(\"Distraction Level Too High\")),\n  },\n\n  EventName.overheat: {\n    ET.PERMANENT: Alert(\n      _(\"System Overheated\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"System Overheated\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"System Overheated\")),\n  },\n\n  EventName.wrongGear: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Gear not D\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Gear not D\")),\n  },\n\n  # This alert is thrown when the calibration angles are outside of the acceptable range.\n  # For example if the device is pointed too much to the left or the right.\n  # Usually this can only be solved by removing the mount from the windshield completely,\n  # and attaching while making sure the device is pointed straight forward and is level.\n  # See https://comma.ai/setup for more information\n  EventName.calibrationInvalid: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Calibration Invalid\"), _(\"Remount Device and Recalibrate\")),\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Calibration Invalid: Remount Device & Recalibrate\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Calibration Invalid: Remount Device & Recalibrate\")),\n  },\n\n  EventName.calibrationIncomplete: {\n    ET.PERMANENT: calibration_incomplete_alert,\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Calibration in Progress\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Calibration in Progress\")),\n  },\n\n  EventName.doorOpen: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Door Open\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Door Open\")),\n  },\n\n  EventName.seatbeltNotLatched: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Seatbelt Unlatched\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Seatbelt Unlatched\")),\n  },\n\n  EventName.espDisabled: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"ESP Off\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"ESP Off\")),\n  },\n\n  EventName.lowBattery: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Low Battery\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Low Battery\")),\n  },\n\n  # Different openpilot services communicate between each other at a certain\n  # interval. If communication does not follow the regular schedule this alert\n  # is thrown. This can mean a service crashed, did not broadcast a message for\n  # ten times the regular interval, or the average interval is more than 10% too high.\n  EventName.commIssue: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Communication Issue between Processes\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Communication Issue between Processes\"),\n                              audible_alert=AudibleAlert.chimeDisengage),\n  },\n\n  # Thrown when manager detects a service exited unexpectedly while driving\n  EventName.processNotRunning: {\n    ET.NO_ENTRY: NoEntryAlert(_(\"System Malfunction: Reboot Your Device\"),\n                              audible_alert=AudibleAlert.chimeDisengage),\n  },\n\n  EventName.radarFault: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Radar Error: Restart the Car\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Radar Error: Restart the Car\")),\n  },\n\n  # Every frame from the camera should be processed by the model. If modeld\n  # is not processing frames fast enough they have to be dropped. This alert is\n  # thrown when over 20% of frames are dropped.\n  EventName.modeldLagging: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Driving model lagging\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Driving model lagging\")),\n  },\n\n  # Besides predicting the path, lane lines and lead car data the model also\n  # predicts the current velocity and rotation speed of the car. If the model is\n  # very uncertain about the current velocity while the car is moving, this\n  # usually means the model has trouble understanding the scene. This is used\n  # as a heuristic to warn the driver.\n  EventName.posenetInvalid: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Model Output Uncertain\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Model Output Uncertain\")),\n  },\n\n  # When the localizer detects an acceleration of more than 40 m/s^2 (~4G) we\n  # alert the driver the device might have fallen from the windshield.\n  EventName.deviceFalling: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Device Fell Off Mount\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Device Fell Off Mount\")),\n  },\n\n  EventName.lowMemory: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"Low Memory: Reboot Your Device\")),\n    ET.PERMANENT: NormalPermanentAlert(_(\"Low Memory\"), _(\"Reboot your Device\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Low Memory: Reboot Your Device\"),\n                              audible_alert=AudibleAlert.chimeDisengage),\n  },\n\n  EventName.highCpuUsage: {\n    #ET.SOFT_DISABLE: SoftDisableAlert(\"System Malfunction: Reboot Your Device\"),\n    #ET.PERMANENT: NormalPermanentAlert(\"System Malfunction\", \"Reboot your Device\"),\n    ET.NO_ENTRY: NoEntryAlert(\"System Malfunction: Reboot Your Device\",\n                              audible_alert=AudibleAlert.chimeDisengage),\n  },\n\n  EventName.accFaulted: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Cruise Faulted\")),\n    ET.PERMANENT: NormalPermanentAlert(_(\"Cruise Faulted\"), \"\"),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Cruise Faulted\")),\n  },\n\n  EventName.controlsMismatch: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Controls Mismatch\")),\n  },\n\n  EventName.roadCameraError: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Road Camera Error\"), \"\",\n                                       duration_text=10.),\n  },\n\n  EventName.driverCameraError: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Driver Camera Error\"), \"\",\n                                       duration_text=10.),\n  },\n\n  EventName.wideRoadCameraError: {\n    ET.PERMANENT: NormalPermanentAlert(_(\"Wide Road Camera Error\"), \"\",\n                                       duration_text=10.),\n  },\n\n  # Sometimes the USB stack on the device can get into a bad state\n  # causing the connection to the panda to be lost\n  EventName.usbError: {\n    ET.SOFT_DISABLE: SoftDisableAlert(_(\"USB Error: Reboot Your Device\")),\n    ET.PERMANENT: NormalPermanentAlert(_(\"USB Error: Reboot Your Device\"), \"\"),\n    ET.NO_ENTRY: NoEntryAlert(_(\"USB Error: Reboot Your Device\")),\n  },\n\n  # This alert can be thrown for the following reasons:\n  # - No CAN data received at all\n  # - CAN data is received, but some message are not received at the right frequency\n  # If you're not writing a new car port, this is usually cause by faulty wiring\n  EventName.canError: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"CAN Error: Check Connections\")),\n    ET.PERMANENT: Alert(\n      _(\"CAN Error: Check Connections\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, 0., 0., .2, creation_delay=1.),\n    ET.NO_ENTRY: NoEntryAlert(_(\"CAN Error: Check Connections\")),\n  },\n\n  EventName.steerUnavailable: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"LKAS Fault: Restart the Car\")),\n    ET.PERMANENT: Alert(\n      _(\"LKAS Fault: Restart the car to engage\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n    ET.NO_ENTRY: NoEntryAlert(_(\"LKAS Fault: Restart the Car\")),\n  },\n\n  EventName.brakeUnavailable: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Cruise Fault: Restart the Car\")),\n    ET.PERMANENT: Alert(\n      _(\"Cruise Fault: Restart the car to engage\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Cruise Fault: Restart the Car\")),\n  },\n\n  EventName.reverseGear: {\n    ET.PERMANENT: Alert(\n      _(\"Reverse\\nGear\"),\n      \"\",\n      AlertStatus.normal, AlertSize.full,\n      Priority.LOWEST, VisualAlert.none, AudibleAlert.none, 0., 0., .2, creation_delay=0.5),\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Reverse Gear\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Reverse Gear\")),\n  },\n\n  # On cars that use stock ACC the car can decide to cancel ACC for various reasons.\n  # When this happens we can no long control the car so the user needs to be warned immediately.\n  EventName.cruiseDisabled: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Cruise Is Off\")),\n  },\n\n  # For planning the trajectory Model Predictive Control (MPC) is used. This is\n  # an optimization algorithm that is not guaranteed to find a feasible solution.\n  # If no solution is found or the solution has a very high cost this alert is thrown.\n  EventName.plannerError: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Planner Solution Error\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Planner Solution Error\")),\n  },\n\n  # When the relay in the harness box opens the CAN bus between the LKAS camera\n  # and the rest of the car is separated. When messages from the LKAS camera\n  # are received on the car side this usually means the relay hasn't opened correctly\n  # and this alert is thrown.\n  EventName.relayMalfunction: {\n    ET.IMMEDIATE_DISABLE: ImmediateDisableAlert(_(\"Harness Malfunction\")),\n    ET.PERMANENT: NormalPermanentAlert(_(\"Harness Malfunction\"), _(\"Check Hardware\")),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Harness Malfunction\")),\n  },\n\n  EventName.noTarget: {\n    ET.IMMEDIATE_DISABLE: Alert(\n      _(\"openpilot Canceled\"),\n      _(\"No close lead car\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.HIGH, VisualAlert.none, AudibleAlert.chimeDisengage, .4, 2., 3.),\n    ET.NO_ENTRY: NoEntryAlert(_(\"No Close Lead Car\")),\n  },\n\n  EventName.speedTooLow: {\n    ET.IMMEDIATE_DISABLE: Alert(\n      _(\"openpilot Canceled\"),\n      _(\"Speed too low\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.HIGH, VisualAlert.none, AudibleAlert.chimeDisengage, .4, 2., 3.),\n  },\n\n  # When the car is driving faster than most cars in the training data the model outputs can be unpredictable\n  EventName.speedTooHigh: {\n    ET.WARNING: Alert(\n      _(\"Speed Too High\"),\n      _(\"Model uncertain at this speed\"),\n      AlertStatus.userPrompt, AlertSize.mid,\n      Priority.HIGH, VisualAlert.steerRequired, AudibleAlert.chimeWarning2Repeat, 2.2, 3., 4.),\n    ET.NO_ENTRY: Alert(\n      _(\"Speed Too High\"),\n      _(\"Slow down to engage\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOW, VisualAlert.none, AudibleAlert.chimeError, .4, 2., 3.),\n  },\n\n  EventName.lowSpeedLockout: {\n    ET.PERMANENT: Alert(\n      _(\"Cruise Fault: Restart the car to engage\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOWER, VisualAlert.none, AudibleAlert.none, 0., 0., .2),\n    ET.NO_ENTRY: NoEntryAlert(_(\"Cruise Fault: Restart the Car\")),\n  },\n\n  # dp\n  EventName.autoLaneChange: {\n    ET.WARNING: alca_alert,\n  },\n\n  EventName.manualSteeringRequired: {\n    ET.WARNING: Alert(\n      _(\"STEERING REQUIRED: Lane Keeping OFF\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, .0, .1, .1, alert_rate=0.25),\n  },\n\n  EventName.manualSteeringRequiredBlinkersOn: {\n    ET.WARNING: Alert(\n      _(\"STEERING REQUIRED: Blinkers ON\"),\n      \"\",\n      AlertStatus.normal, AlertSize.small,\n      Priority.LOW, VisualAlert.none, AudibleAlert.none, .0, .1, .1, alert_rate=0.25),\n  },\n\n  # timebomb\n  EventName.timebombWarn: {\n    ET.WARNING: Alert(\n      _(\"WARNING\"),\n      _(\"Grab wheel to start bypass\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOW, VisualAlert.steerRequired, AudibleAlert.chimeWarning1, .4, 2., 3.),\n  },\n\n  EventName.timebombBypassing: {\n    ET.WARNING: Alert(\n      _(\"BYPASSING\"),\n      _(\"HOLD WHEEL\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOW, VisualAlert.steerRequired, AudibleAlert.chimeWarning1, .4, 2., 3.),\n  },\n\n  EventName.timebombBypassed: {\n    ET.WARNING: Alert(\n      _(\"Bypassed!\"),\n      _(\"Release wheel when ready\"),\n      AlertStatus.normal, AlertSize.mid,\n      Priority.LOW, VisualAlert.steerRequired, AudibleAlert.chimeWarning1, 3., 2., 3.),\n  },\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/fcw.py",
    "content": "import math\nfrom collections import defaultdict\n\nfrom common.numpy_fast import interp\n\n_FCW_A_ACT_V = [-3., -2.]\n_FCW_A_ACT_BP = [0., 30.]\n\n\nclass FCWChecker():\n  def __init__(self):\n    self.reset_lead(0.0)\n    self.common_counters = defaultdict(lambda: 0)\n\n  def reset_lead(self, cur_time):\n    self.last_fcw_a = 0.0\n    self.v_lead_max = 0.0\n    self.lead_seen_t = cur_time\n    self.last_fcw_time = 0.0\n    self.last_min_a = 0.0\n\n    self.counters = defaultdict(lambda: 0)\n\n  @staticmethod\n  def calc_ttc(v_ego, a_ego, x_lead, v_lead, a_lead):\n    max_ttc = 5.0\n\n    v_rel = v_ego - v_lead\n    a_rel = a_ego - a_lead\n\n    # assuming that closing gap ARel comes from lead vehicle decel,\n    # then limit ARel so that v_lead will get to zero in no sooner than t_decel.\n    # This helps underweighting ARel when v_lead is close to zero.\n    t_decel = 2.\n    a_rel = min(a_rel, v_lead / t_decel)\n\n    # delta of the quadratic equation to solve for ttc\n    delta = v_rel**2 + 2 * x_lead * a_rel\n\n    # assign an arbitrary high ttc value if there is no solution to ttc\n    if delta < 0.1 or (math.sqrt(delta) + v_rel < 0.1):\n      ttc = max_ttc\n    else:\n      ttc = min(2 * x_lead / (math.sqrt(delta) + v_rel), max_ttc)\n    return ttc\n\n  def update(self, mpc_solution, cur_time, active, v_ego, a_ego, x_lead, v_lead, a_lead, y_lead, vlat_lead, fcw_lead, blinkers):\n    mpc_solution_a = list(mpc_solution[0].a_ego)\n\n    self.last_min_a = min(mpc_solution_a)\n    self.v_lead_max = max(self.v_lead_max, v_lead)\n\n    self.common_counters['blinkers'] = self.common_counters['blinkers'] + 10.0 / (20 * 3.0) if not blinkers else 0\n    self.common_counters['v_ego'] = self.common_counters['v_ego'] + 1 if v_ego > 5.0 else 0\n\n    if (fcw_lead > 0.99):\n      ttc = self.calc_ttc(v_ego, a_ego, x_lead, v_lead, a_lead)\n      self.counters['ttc'] = self.counters['ttc'] + 1 if ttc < 2.5 else 0\n      self.counters['v_lead_max'] = self.counters['v_lead_max'] + 1 if self.v_lead_max > 2.5 else 0\n      self.counters['v_ego_lead'] = self.counters['v_ego_lead'] + 1 if v_ego > v_lead else 0\n      self.counters['lead_seen'] = self.counters['lead_seen'] + 0.33\n      self.counters['y_lead'] = self.counters['y_lead'] + 1 if abs(y_lead) < 1.0 else 0\n      self.counters['vlat_lead'] = self.counters['vlat_lead'] + 1 if abs(vlat_lead) < 0.4 else 0\n\n      a_thr = interp(v_lead, _FCW_A_ACT_BP, _FCW_A_ACT_V)\n      a_delta = min(mpc_solution_a[:15]) - min(0.0, a_ego)\n\n      future_fcw_allowed = all(c >= 10 for c in self.counters.values())\n      future_fcw_allowed = future_fcw_allowed and all(c >= 10 for c in self.common_counters.values())\n      future_fcw = (self.last_min_a < -3.0 or a_delta < a_thr) and future_fcw_allowed\n\n      if future_fcw and (self.last_fcw_time + 5.0 < cur_time):\n        self.last_fcw_time = cur_time\n        self.last_fcw_a = self.last_min_a\n        return True\n\n    return False\n"
  },
  {
    "path": "selfdrive/controls/lib/lane_planner.py",
    "content": "import numpy as np\nfrom cereal import log\nfrom common.filter_simple import FirstOrderFilter\nfrom common.numpy_fast import interp\nfrom common.realtime import DT_MDL\nfrom selfdrive.hardware import EON, TICI\nfrom selfdrive.swaglog import cloudlog\n\n\nTRAJECTORY_SIZE = 33\n# camera offset is meters from center car to camera\nif EON:\n  CAMERA_OFFSET = 0.06\n  PATH_OFFSET = 0.0\nelif TICI:\n  CAMERA_OFFSET = -0.04\n  PATH_OFFSET = -0.04\nelse:\n  CAMERA_OFFSET = 0.0\n  PATH_OFFSET = 0.0\n\n\nclass LanePlanner:\n  def __init__(self, wide_camera=False):\n    self.ll_t = np.zeros((TRAJECTORY_SIZE,))\n    self.ll_x = np.zeros((TRAJECTORY_SIZE,))\n    self.lll_y = np.zeros((TRAJECTORY_SIZE,))\n    self.rll_y = np.zeros((TRAJECTORY_SIZE,))\n    self.lane_width_estimate = FirstOrderFilter(3.7, 9.95, DT_MDL)\n    self.lane_width_certainty = FirstOrderFilter(1.0, 0.95, DT_MDL)\n    self.lane_width = 3.7\n\n    self.lll_prob = 0.\n    self.rll_prob = 0.\n    self.d_prob = 0.\n\n    self.lll_std = 0.\n    self.rll_std = 0.\n\n    self.l_lane_change_prob = 0.\n    self.r_lane_change_prob = 0.\n\n    self.camera_offset = -CAMERA_OFFSET if wide_camera else CAMERA_OFFSET\n    self.path_offset = -PATH_OFFSET if wide_camera else PATH_OFFSET\n\n    self.dp_camera_offset = None\n    self.dp_path_offset = None\n\n  def update_dp_set_offsets(self, camera_offset, path_offset):\n    if self.dp_camera_offset != camera_offset:\n      self.dp_camera_offset = camera_offset\n      self.camera_offset = camera_offset / 100\n\n    if self.dp_path_offset != path_offset:\n      self.dp_path_offset = path_offset\n      self.path_offset = path_offset / 100\n\n  def parse_model(self, md):\n    if len(md.laneLines) == 4 and len(md.laneLines[0].t) == TRAJECTORY_SIZE:\n      self.ll_t = (np.array(md.laneLines[1].t) + np.array(md.laneLines[2].t))/2\n      # left and right ll x is the same\n      self.ll_x = md.laneLines[1].x\n      # only offset left and right lane lines; offsetting path does not make sense\n      self.lll_y = np.array(md.laneLines[1].y) - self.camera_offset\n      self.rll_y = np.array(md.laneLines[2].y) - self.camera_offset\n      self.lll_prob = md.laneLineProbs[1]\n      self.rll_prob = md.laneLineProbs[2]\n      self.lll_std = md.laneLineStds[1]\n      self.rll_std = md.laneLineStds[2]\n\n    if len(md.meta.desireState):\n      self.l_lane_change_prob = md.meta.desireState[log.LateralPlan.Desire.laneChangeLeft]\n      self.r_lane_change_prob = md.meta.desireState[log.LateralPlan.Desire.laneChangeRight]\n\n  def get_d_path(self, v_ego, path_t, path_xyz):\n    # Reduce reliance on lanelines that are too far apart or\n    # will be in a few seconds\n    path_xyz[:, 1] -= self.path_offset\n    l_prob, r_prob = self.lll_prob, self.rll_prob\n    width_pts = self.rll_y - self.lll_y\n    prob_mods = []\n    for t_check in [0.0, 1.5, 3.0]:\n      width_at_t = interp(t_check * (v_ego + 7), self.ll_x, width_pts)\n      prob_mods.append(interp(width_at_t, [4.0, 5.0], [1.0, 0.0]))\n    mod = min(prob_mods)\n    l_prob *= mod\n    r_prob *= mod\n\n    # Reduce reliance on uncertain lanelines\n    l_std_mod = interp(self.lll_std, [.15, .3], [1.0, 0.0])\n    r_std_mod = interp(self.rll_std, [.15, .3], [1.0, 0.0])\n    l_prob *= l_std_mod\n    r_prob *= r_std_mod\n\n    # Find current lanewidth\n    self.lane_width_certainty.update(l_prob * r_prob)\n    current_lane_width = abs(self.rll_y[0] - self.lll_y[0])\n    self.lane_width_estimate.update(current_lane_width)\n    speed_lane_width = interp(v_ego, [0., 31.], [2.8, 3.5])\n    self.lane_width = self.lane_width_certainty.x * self.lane_width_estimate.x + \\\n                      (1 - self.lane_width_certainty.x) * speed_lane_width\n\n    clipped_lane_width = min(4.0, self.lane_width)\n    path_from_left_lane = self.lll_y + clipped_lane_width / 2.0\n    path_from_right_lane = self.rll_y - clipped_lane_width / 2.0\n\n    self.d_prob = l_prob + r_prob - l_prob * r_prob\n    lane_path_y = (l_prob * path_from_left_lane + r_prob * path_from_right_lane) / (l_prob + r_prob + 0.0001)\n    safe_idxs = np.isfinite(self.ll_t)\n    if safe_idxs[0]:\n      lane_path_y_interp = np.interp(path_t, self.ll_t[safe_idxs], lane_path_y[safe_idxs])\n      path_xyz[:,1] = self.d_prob * lane_path_y_interp + (1.0 - self.d_prob) * path_xyz[:,1]\n    else:\n      cloudlog.warning(\"Lateral mpc - NaNs in laneline times, ignoring\")\n    return path_xyz\n"
  },
  {
    "path": "selfdrive/controls/lib/latcontrol_angle.py",
    "content": "import math\nfrom cereal import log\n\n\nclass LatControlAngle():\n  def __init__(self, CP):\n    pass\n\n  def reset(self):\n    pass\n\n  def update(self, active, CS, CP, VM, params, desired_curvature, desired_curvature_rate):\n    angle_log = log.ControlsState.LateralAngleState.new_message()\n\n    if CS.vEgo < 0.3 or not active:\n      angle_log.active = False\n      angle_steers_des = float(CS.steeringAngleDeg)\n    else:\n      angle_log.active = True\n      angle_steers_des = math.degrees(VM.get_steer_from_curvature(-desired_curvature, CS.vEgo))\n      angle_steers_des += params.angleOffsetDeg\n\n    angle_log.saturated = False\n    angle_log.steeringAngleDeg = angle_steers_des\n    return 0, float(angle_steers_des), angle_log\n"
  },
  {
    "path": "selfdrive/controls/lib/latcontrol_indi.py",
    "content": "import math\nimport numpy as np\n\nfrom cereal import log\nfrom common.filter_simple import FirstOrderFilter\nfrom common.numpy_fast import clip, interp\nfrom common.realtime import DT_CTRL\nfrom selfdrive.car import apply_toyota_steer_torque_limits\nfrom selfdrive.car.toyota.values import CarControllerParams\nfrom selfdrive.controls.lib.drive_helpers import get_steer_max\n\n\nclass LatControlINDI():\n  def __init__(self, CP):\n    self.angle_steers_des = 0.\n\n    A = np.array([[1.0, DT_CTRL, 0.0],\n                  [0.0, 1.0, DT_CTRL],\n                  [0.0, 0.0, 1.0]])\n    C = np.array([[1.0, 0.0, 0.0],\n                  [0.0, 1.0, 0.0]])\n\n    # Q = np.matrix([[1e-2, 0.0, 0.0], [0.0, 1.0, 0.0], [0.0, 0.0, 10.0]])\n    # R = np.matrix([[1e-2, 0.0], [0.0, 1e3]])\n\n    # (x, l, K) = control.dare(np.transpose(A), np.transpose(C), Q, R)\n    # K = np.transpose(K)\n    K = np.array([[7.30262179e-01, 2.07003658e-04],\n                  [7.29394177e+00, 1.39159419e-02],\n                  [1.71022442e+01, 3.38495381e-02]])\n\n    self.speed = 0.\n\n    self.K = K\n    self.A_K = A - np.dot(K, C)\n    self.x = np.array([[0.], [0.], [0.]])\n\n    self.enforce_rate_limit = CP.carName == \"toyota\"\n\n    self._RC = (CP.lateralTuning.indi.timeConstantBP, CP.lateralTuning.indi.timeConstantV)\n    self._G = (CP.lateralTuning.indi.actuatorEffectivenessBP, CP.lateralTuning.indi.actuatorEffectivenessV)\n    self._outer_loop_gain = (CP.lateralTuning.indi.outerLoopGainBP, CP.lateralTuning.indi.outerLoopGainV)\n    self._inner_loop_gain = (CP.lateralTuning.indi.innerLoopGainBP, CP.lateralTuning.indi.innerLoopGainV)\n\n    self.sat_count_rate = 1.0 * DT_CTRL\n    self.sat_limit = CP.steerLimitTimer\n    self.steer_filter = FirstOrderFilter(0., self.RC, DT_CTRL)\n\n    self.reset()\n\n  @property\n  def RC(self):\n    return interp(self.speed, self._RC[0], self._RC[1])\n\n  @property\n  def G(self):\n    return interp(self.speed, self._G[0], self._G[1])\n\n  @property\n  def outer_loop_gain(self):\n    return interp(self.speed, self._outer_loop_gain[0], self._outer_loop_gain[1])\n\n  @property\n  def inner_loop_gain(self):\n    return interp(self.speed, self._inner_loop_gain[0], self._inner_loop_gain[1])\n\n  def reset(self):\n    self.steer_filter.x = 0.\n    self.output_steer = 0.\n    self.sat_count = 0.\n    self.speed = 0.\n\n  def _check_saturation(self, control, check_saturation, limit):\n    saturated = abs(control) == limit\n\n    if saturated and check_saturation:\n      self.sat_count += self.sat_count_rate\n    else:\n      self.sat_count -= self.sat_count_rate\n\n    self.sat_count = clip(self.sat_count, 0.0, 1.0)\n\n    return self.sat_count > self.sat_limit\n\n  def update(self, active, CS, CP, VM, params, curvature, curvature_rate):\n    self.speed = CS.vEgo\n    # Update Kalman filter\n    y = np.array([[math.radians(CS.steeringAngleDeg)], [math.radians(CS.steeringRateDeg)]])\n    self.x = np.dot(self.A_K, self.x) + np.dot(self.K, y)\n\n    indi_log = log.ControlsState.LateralINDIState.new_message()\n    indi_log.steeringAngleDeg = math.degrees(self.x[0])\n    indi_log.steeringRateDeg = math.degrees(self.x[1])\n    indi_log.steeringAccelDeg = math.degrees(self.x[2])\n\n    steers_des = VM.get_steer_from_curvature(-curvature, CS.vEgo)\n    steers_des += math.radians(params.angleOffsetDeg)\n    if CS.vEgo < 0.3 or not active:\n      indi_log.active = False\n      self.output_steer = 0.0\n      self.steer_filter.x = 0.0\n    else:\n\n      rate_des = VM.get_steer_from_curvature(-curvature_rate, CS.vEgo)\n\n      # Expected actuator value\n      self.steer_filter.update_alpha(self.RC)\n      self.steer_filter.update(self.output_steer)\n\n      # Compute acceleration error\n      rate_sp = self.outer_loop_gain * (steers_des - self.x[0]) + rate_des\n      accel_sp = self.inner_loop_gain * (rate_sp - self.x[1])\n      accel_error = accel_sp - self.x[2]\n\n      # Compute change in actuator\n      g_inv = 1. / self.G\n      delta_u = g_inv * accel_error\n\n      # If steering pressed, only allow wind down\n      if CS.steeringPressed and (delta_u * self.output_steer > 0):\n        delta_u = 0\n\n      # Enforce rate limit\n      if self.enforce_rate_limit:\n        steer_max = float(CarControllerParams.STEER_MAX)\n        new_output_steer_cmd = steer_max * (self.steer_filter.x + delta_u)\n        prev_output_steer_cmd = steer_max * self.output_steer\n        new_output_steer_cmd = apply_toyota_steer_torque_limits(new_output_steer_cmd, prev_output_steer_cmd, prev_output_steer_cmd, CarControllerParams)\n        self.output_steer = new_output_steer_cmd / steer_max\n      else:\n        self.output_steer = self.steer_filter.x + delta_u\n\n      steers_max = get_steer_max(CP, CS.vEgo)\n      self.output_steer = clip(self.output_steer, -steers_max, steers_max)\n\n      indi_log.active = True\n      indi_log.rateSetPoint = float(rate_sp)\n      indi_log.accelSetPoint = float(accel_sp)\n      indi_log.accelError = float(accel_error)\n      indi_log.delayedOutput = float(self.steer_filter.x)\n      indi_log.delta = float(delta_u)\n      indi_log.output = float(self.output_steer)\n\n      check_saturation = (CS.vEgo > 10.) and not CS.steeringRateLimited and not CS.steeringPressed\n      indi_log.saturated = self._check_saturation(self.output_steer, check_saturation, steers_max)\n\n    return float(self.output_steer), float(steers_des), indi_log\n"
  },
  {
    "path": "selfdrive/controls/lib/latcontrol_lqr.py",
    "content": "import math\nimport numpy as np\n\nfrom common.numpy_fast import clip\nfrom common.realtime import DT_CTRL\nfrom cereal import log\nfrom selfdrive.controls.lib.drive_helpers import get_steer_max\n\n\nclass LatControlLQR():\n  def __init__(self, CP):\n    self.scale = CP.lateralTuning.lqr.scale\n    self.ki = CP.lateralTuning.lqr.ki\n\n    self.A = np.array(CP.lateralTuning.lqr.a).reshape((2, 2))\n    self.B = np.array(CP.lateralTuning.lqr.b).reshape((2, 1))\n    self.C = np.array(CP.lateralTuning.lqr.c).reshape((1, 2))\n    self.K = np.array(CP.lateralTuning.lqr.k).reshape((1, 2))\n    self.L = np.array(CP.lateralTuning.lqr.l).reshape((2, 1))\n    self.dc_gain = CP.lateralTuning.lqr.dcGain\n\n    self.x_hat = np.array([[0], [0]])\n    self.i_unwind_rate = 0.3 * DT_CTRL\n    self.i_rate = 1.0 * DT_CTRL\n\n    self.sat_count_rate = 1.0 * DT_CTRL\n    self.sat_limit = CP.steerLimitTimer\n\n    self.reset()\n\n  def reset(self):\n    self.i_lqr = 0.0\n    self.sat_count = 0.0\n\n  def _check_saturation(self, control, check_saturation, limit):\n    saturated = abs(control) == limit\n\n    if saturated and check_saturation:\n      self.sat_count += self.sat_count_rate\n    else:\n      self.sat_count -= self.sat_count_rate\n\n    self.sat_count = clip(self.sat_count, 0.0, 1.0)\n\n    return self.sat_count > self.sat_limit\n\n  def update(self, active, CS, CP, VM, params, desired_curvature, desired_curvature_rate):\n    lqr_log = log.ControlsState.LateralLQRState.new_message()\n\n    steers_max = get_steer_max(CP, CS.vEgo)\n    torque_scale = (0.45 + CS.vEgo / 60.0)**2  # Scale actuator model with speed\n\n    # Subtract offset. Zero angle should correspond to zero torque\n    steering_angle_no_offset = CS.steeringAngleDeg - params.angleOffsetAverageDeg\n\n    desired_angle = math.degrees(VM.get_steer_from_curvature(-desired_curvature, CS.vEgo))\n\n    instant_offset = params.angleOffsetDeg - params.angleOffsetAverageDeg\n    desired_angle += instant_offset  # Only add offset that originates from vehicle model errors\n\n    # Update Kalman filter\n    angle_steers_k = float(self.C.dot(self.x_hat))\n    e = steering_angle_no_offset - angle_steers_k\n    self.x_hat = self.A.dot(self.x_hat) + self.B.dot(CS.steeringTorqueEps / torque_scale) + self.L.dot(e)\n\n    if CS.vEgo < 0.3 or not active:\n      lqr_log.active = False\n      lqr_output = 0.\n      output_steer = 0.\n      self.reset()\n    else:\n      lqr_log.active = True\n\n      # LQR\n      u_lqr = float(desired_angle / self.dc_gain - self.K.dot(self.x_hat))\n      lqr_output = torque_scale * u_lqr / self.scale\n\n      # Integrator\n      if CS.steeringPressed:\n        self.i_lqr -= self.i_unwind_rate * float(np.sign(self.i_lqr))\n      else:\n        error = desired_angle - angle_steers_k\n        i = self.i_lqr + self.ki * self.i_rate * error\n        control = lqr_output + i\n\n        if (error >= 0 and (control <= steers_max or i < 0.0)) or \\\n           (error <= 0 and (control >= -steers_max or i > 0.0)):\n          self.i_lqr = i\n\n      output_steer = lqr_output + self.i_lqr\n      output_steer = clip(output_steer, -steers_max, steers_max)\n\n    check_saturation = (CS.vEgo > 10) and not CS.steeringRateLimited and not CS.steeringPressed\n    saturated = self._check_saturation(output_steer, check_saturation, steers_max)\n\n    lqr_log.steeringAngleDeg = angle_steers_k + params.angleOffsetAverageDeg\n    lqr_log.i = self.i_lqr\n    lqr_log.output = output_steer\n    lqr_log.lqrOutput = lqr_output\n    lqr_log.saturated = saturated\n    return output_steer, desired_angle, lqr_log\n"
  },
  {
    "path": "selfdrive/controls/lib/latcontrol_pid.py",
    "content": "import math\n\nfrom selfdrive.controls.lib.pid import PIController\nfrom selfdrive.controls.lib.drive_helpers import get_steer_max\nfrom cereal import log\n\n\nclass LatControlPID():\n  def __init__(self, CP):\n    self.pid = PIController((CP.lateralTuning.pid.kpBP, CP.lateralTuning.pid.kpV),\n                            (CP.lateralTuning.pid.kiBP, CP.lateralTuning.pid.kiV),\n                            k_f=CP.lateralTuning.pid.kf, pos_limit=1.0, neg_limit=-1.0,\n                            sat_limit=CP.steerLimitTimer)\n\n  def reset(self):\n    self.pid.reset()\n\n  def update(self, active, CS, CP, VM, params, desired_curvature, desired_curvature_rate):\n    pid_log = log.ControlsState.LateralPIDState.new_message()\n    pid_log.steeringAngleDeg = float(CS.steeringAngleDeg)\n    pid_log.steeringRateDeg = float(CS.steeringRateDeg)\n\n    angle_steers_des_no_offset = math.degrees(VM.get_steer_from_curvature(-desired_curvature, CS.vEgo))\n    angle_steers_des = angle_steers_des_no_offset + params.angleOffsetDeg\n\n    pid_log.angleError = angle_steers_des - CS.steeringAngleDeg \n    if CS.vEgo < 0.3 or not active:\n      output_steer = 0.0\n      pid_log.active = False\n      self.pid.reset()\n    else:\n      steers_max = get_steer_max(CP, CS.vEgo)\n      self.pid.pos_limit = steers_max\n      self.pid.neg_limit = -steers_max\n\n      # TODO: feedforward something based on lat_plan.rateSteers\n      steer_feedforward = angle_steers_des_no_offset  # offset does not contribute to resistive torque\n      steer_feedforward *= CS.vEgo**2  # proportional to realigning tire momentum (~ lateral accel)\n\n      deadzone = 0.0\n\n      check_saturation = (CS.vEgo > 10) and not CS.steeringRateLimited and not CS.steeringPressed\n      output_steer = self.pid.update(angle_steers_des, CS.steeringAngleDeg, check_saturation=check_saturation, override=CS.steeringPressed,\n                                     feedforward=steer_feedforward, speed=CS.vEgo, deadzone=deadzone)\n      pid_log.active = True\n      pid_log.p = self.pid.p\n      pid_log.i = self.pid.i\n      pid_log.f = self.pid.f\n      pid_log.output = output_steer\n      pid_log.saturated = bool(self.pid.saturated)\n\n    return output_steer, angle_steers_des, pid_log\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/.gitignore",
    "content": "generator\nlib_qp/\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/SConscript",
    "content": "Import('env', 'arch')\n\ncpp_path = [\n  \"#\",\n  \"#selfdrive\",\n  \"#phonelibs/acado/include\",\n  \"#phonelibs/acado/include/acado\",\n  \"#phonelibs/qpoases/INCLUDE\",\n  \"#phonelibs/qpoases/INCLUDE/EXTRAS\",\n  \"#phonelibs/qpoases/SRC/\",\n  \"#phonelibs/qpoases\",\n  \"lib_mpc_export\",\n]\n\ngenerated_c = [\n  'lib_mpc_export/acado_auxiliary_functions.c',\n  'lib_mpc_export/acado_qpoases_interface.cpp',\n  'lib_mpc_export/acado_integrator.c',\n  'lib_mpc_export/acado_solver.c',\n]\n\ngenerated_h = [\n  'lib_mpc_export/acado_common.h',\n  'lib_mpc_export/acado_auxiliary_functions.h',\n  'lib_mpc_export/acado_qpoases_interface.hpp',\n]\n\ninterface_dir = Dir('lib_mpc_export')\n\nSConscript(['#phonelibs/qpoases/SConscript'], variant_dir='lib_qp', exports=['interface_dir'])\n\nif GetOption('mpc_generate'):\n    generator_cpp = File('generator.cpp')\n\n    acado_libs = [File(f\"#phonelibs/acado/{arch}/lib/libacado_toolkit.a\"),\n                  File(f\"#phonelibs/acado/{arch}/lib/libacado_casadi.a\"),\n                  File(f\"#phonelibs/acado/{arch}/lib/libacado_csparse.a\")]\n\n    generator = env.Program('generator', generator_cpp, LIBS=acado_libs, CPPPATH=cpp_path,\n                            CCFLAGS=env['CCFLAGS'] + [\"-Wno-deprecated\", \"-Wno-overloaded-shift-op-parentheses\"])\n\n    cmd = f\"cd {Dir('.').get_abspath()} && {generator[0].get_abspath()}\"\n    env.Command(generated_c + generated_h, generator, cmd)\n\n\n\nmpc_files = [\"lateral_mpc.c\"] + generated_c\nenv.SharedLibrary('mpc', mpc_files, LIBS=['m', 'qpoases'], LIBPATH=['lib_qp'], CPPPATH=cpp_path)\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/generator.cpp",
    "content": "#include <math.h>\n#include <acado_code_generation.hpp>\n#include \"selfdrive/common/modeldata.h\"\n\n#define deg2rad(d) (d/180.0*M_PI)\n\nusing namespace std;\n\nint main( )\n{\n  USING_NAMESPACE_ACADO\n\n\n  DifferentialEquation f;\n\n  DifferentialState xx; // x position\n  DifferentialState yy; // y position\n  DifferentialState psi; // vehicle heading\n  DifferentialState curvature;\n\n  OnlineData v_ego;\n  OnlineData rotation_radius;\n\n  Control curvature_rate;\n\n\n  // Equations of motion\n  f << dot(xx) == v_ego * cos(psi);\n  f << dot(yy) == v_ego * sin(psi);\n  // disable rotation radius for now\n  //f << dot(xx) == v_ego * cos(psi) - rotation_radius * sin(psi) * (v_ego * curvature);\n  //f << dot(yy) == v_ego * sin(psi) + rotation_radius * cos(psi) * (v_ego * curvature);\n  f << dot(psi) == v_ego * curvature;\n  f << dot(curvature) == curvature_rate;\n\n  // Running cost\n  Function h;\n\n  // Distance errors\n  h << yy;\n\n  // Heading error\n  h << (v_ego + 5.0 ) * psi;\n\n  // Angular rate error\n  h << (v_ego + 5.0) * 4 * curvature_rate;\n\n  BMatrix Q(3,3); Q.setAll(true);\n  // Q(0,0) = 1.0;\n  // Q(1,1) = 1.0;\n  // Q(2,2) = 1.0;\n  // Q(3,3) = 1.0;\n  // Q(4,4) = 2.0;\n\n  // Terminal cost\n  Function hN;\n\n  // Distance errors\n  hN << yy;\n\n  // Heading errors\n  hN << (2.0 * v_ego + 5.0 ) * psi;\n\n  BMatrix QN(2,2); QN.setAll(true);\n  // QN(0,0) = 1.0;\n  // QN(1,1) = 1.0;\n  // QN(2,2) = 1.0;\n  // QN(3,3) = 1.0;\n\n  double T_IDXS_ARR[LAT_MPC_N + 1];\n  memcpy(T_IDXS_ARR, T_IDXS, (LAT_MPC_N + 1) * sizeof(double));\n  Grid times(LAT_MPC_N + 1, T_IDXS_ARR);\n  OCP ocp(times);\n  ocp.subjectTo(f);\n\n  ocp.minimizeLSQ(Q, h);\n  ocp.minimizeLSQEndTerm(QN, hN);\n\n  // car can't go backward to avoid \"circles\"\n  ocp.subjectTo( deg2rad(-90) <= psi <= deg2rad(90));\n  // more than absolute max steer angle\n  ocp.subjectTo( deg2rad(-50) <= curvature <= deg2rad(50));\n  ocp.setNOD(2);\n\n  OCPexport mpc(ocp);\n  mpc.set( HESSIAN_APPROXIMATION, GAUSS_NEWTON );\n  mpc.set( DISCRETIZATION_TYPE, MULTIPLE_SHOOTING );\n  mpc.set( INTEGRATOR_TYPE, INT_RK4 );\n  mpc.set( NUM_INTEGRATOR_STEPS, 1000);\n  mpc.set( MAX_NUM_QP_ITERATIONS, 50);\n  mpc.set( CG_USE_VARIABLE_WEIGHTING_MATRIX, YES);\n\n  mpc.set( SPARSE_QP_SOLUTION, CONDENSING );\n  mpc.set( QP_SOLVER, QP_QPOASES );\n  mpc.set( HOTSTART_QP, YES );\n  mpc.set( GENERATE_TEST_FILE, NO);\n  mpc.set( GENERATE_MAKE_FILE, NO );\n  mpc.set( GENERATE_MATLAB_INTERFACE, NO );\n  mpc.set( GENERATE_SIMULINK_INTERFACE, NO );\n\n  if (mpc.exportCode( \"lib_mpc_export\" ) != SUCCESSFUL_RETURN)\n    exit( EXIT_FAILURE );\n\n  mpc.printDimensionsQP( );\n\n  return EXIT_SUCCESS;\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lateral_mpc.c",
    "content": "#include \"acado_common.h\"\n#include \"acado_auxiliary_functions.h\"\n#include \"common/modeldata.h\"\n#include <stdio.h>\n\n#define NX          ACADO_NX  /* Number of differential state variables.  */\n#define NXA         ACADO_NXA /* Number of algebraic variables. */\n#define NU          ACADO_NU  /* Number of control inputs. */\n#define NOD         ACADO_NOD  /* Number of online data values. */\n\n#define NY          ACADO_NY  /* Number of measurements/references on nodes 0..N - 1. */\n#define NYN         ACADO_NYN /* Number of measurements/references on node N. */\n\n#define N           ACADO_N   /* Number of intervals in the horizon. */\n\nACADOvariables acadoVariables;\nACADOworkspace acadoWorkspace;\n\ntypedef struct {\n  double x, y, psi, tire_angle, tire_angle_rate;\n} state_t;\n\ntypedef struct {\n  double x[N+1];\n  double y[N+1];\n  double psi[N+1];\n  double curvature[N+1];\n  double curvature_rate[N];\n  double cost;\n} log_t;\n\nvoid set_weights(double pathCost, double headingCost, double steerRateCost){\n  int    i;\n  const int STEP_MULTIPLIER = 3.0;\n\n  for (i = 0; i < N; i++) {\n    double f = 20 * (T_IDXS[i+1] - T_IDXS[i]);\n    // Setup diagonal entries\n    acadoVariables.W[NY*NY*i + (NY+1)*0] = pathCost * f;\n    acadoVariables.W[NY*NY*i + (NY+1)*1] = headingCost * f;\n    acadoVariables.W[NY*NY*i + (NY+1)*2] = steerRateCost * f;\n  }\n  acadoVariables.WN[(NYN+1)*0] = pathCost * STEP_MULTIPLIER;\n  acadoVariables.WN[(NYN+1)*1] = headingCost * STEP_MULTIPLIER;\n}\n\nvoid init(){\n  acado_initializeSolver();\n  int    i;\n\n  /* Initialize the states and controls. */\n  for (i = 0; i < NX * (N + 1); ++i)  acadoVariables.x[ i ] = 0.0;\n  for (i = 0; i < NU * N; ++i)  acadoVariables.u[ i ] = 0.0;\n\n  /* Initialize the measurements/reference. */\n  for (i = 0; i < NY * N; ++i)  acadoVariables.y[ i ] = 0.0;\n  for (i = 0; i < NYN; ++i)  acadoVariables.yN[ i ] = 0.0;\n\n  /* MPC: initialize the current state feedback. */\n  for (i = 0; i < NX; ++i) acadoVariables.x0[ i ] = 0.0;\n}\n\nint run_mpc(state_t * x0, log_t * solution, double v_ego,\n             double rotation_radius, double target_y[N+1], double target_psi[N+1]){\n\n  int    i;\n\n  for (i = 0; i <= NOD * N; i+= NOD){\n    acadoVariables.od[i] = v_ego;\n    acadoVariables.od[i+1] = rotation_radius;\n  }\n  for (i = 0; i < N; i+= 1){\n    acadoVariables.y[NY*i + 0] = target_y[i];\n    acadoVariables.y[NY*i + 1] = (v_ego + 5.0) * target_psi[i];\n    acadoVariables.y[NY*i + 2] = 0.0;\n  }\n  acadoVariables.yN[0] = target_y[N];\n  acadoVariables.yN[1] = (2.0 * v_ego + 5.0) * target_psi[N];\n\n  acadoVariables.x0[0] = x0->x;\n  acadoVariables.x0[1] = x0->y;\n  acadoVariables.x0[2] = x0->psi;\n  acadoVariables.x0[3] = x0->tire_angle;\n\n\n  acado_preparationStep();\n  acado_feedbackStep();\n\n  /* printf(\"lat its: %d\\n\", acado_getNWSR());  // n iterations\n  printf(\"Objective: %.6f\\n\", acado_getObjective());  // solution cost */\n\n  for (i = 0; i <= N; i++){\n    solution->x[i] = acadoVariables.x[i*NX];\n    solution->y[i] = acadoVariables.x[i*NX+1];\n    solution->psi[i] = acadoVariables.x[i*NX+2];\n    solution->curvature[i] = acadoVariables.x[i*NX+3];\n    if (i < N){\n      solution->curvature_rate[i] = acadoVariables.u[i];\n    }\n  }\n  solution->cost = acado_getObjective();\n\n  // Dont shift states here. Current solution is closer to next timestep than if\n  // we use the old solution as a starting point\n  //acado_shiftStates(2, 0, 0);\n  //acado_shiftControls( 0 );\n\n  return acado_getNWSR();\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_auxiliary_functions.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_auxiliary_functions.h\"\n\n#include <stdio.h>\n\nreal_t* acado_getVariablesX( )\n{\n\treturn acadoVariables.x;\n}\n\nreal_t* acado_getVariablesU( )\n{\n\treturn acadoVariables.u;\n}\n\n#if ACADO_NY > 0\nreal_t* acado_getVariablesY( )\n{\n\treturn acadoVariables.y;\n}\n#endif\n\n#if ACADO_NYN > 0\nreal_t* acado_getVariablesYN( )\n{\n\treturn acadoVariables.yN;\n}\n#endif\n\nreal_t* acado_getVariablesX0( )\n{\n#if ACADO_INITIAL_VALUE_FIXED\n\treturn acadoVariables.x0;\n#else\n\treturn 0;\n#endif\n}\n\n/** Print differential variables. */\nvoid acado_printDifferentialVariables( )\n{\n\tint i, j;\n\tprintf(\"\\nDifferential variables:\\n[\\n\");\n\tfor (i = 0; i < ACADO_N + 1; ++i)\n\t{\n\t\tfor (j = 0; j < ACADO_NX; ++j)\n\t\t\tprintf(\"\\t%e\", acadoVariables.x[i * ACADO_NX + j]);\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"]\\n\\n\");\n}\n\n/** Print control variables. */\nvoid acado_printControlVariables( )\n{\n\tint i, j;\n\tprintf(\"\\nControl variables:\\n[\\n\");\n\tfor (i = 0; i < ACADO_N; ++i)\n\t{\n\t\tfor (j = 0; j < ACADO_NU; ++j)\n\t\t\tprintf(\"\\t%e\", acadoVariables.u[i * ACADO_NU + j]);\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"]\\n\\n\");\n}\n\n/** Print ACADO code generation notice. */\nvoid acado_printHeader( )\n{\n\tprintf(\n\t\t\"\\nACADO Toolkit -- A Toolkit for Automatic Control and Dynamic Optimization.\\n\"\n\t\t\"Copyright (C) 2008-2015 by Boris Houska, Hans Joachim Ferreau,\\n\" \n\t\t\"Milan Vukov and Rien Quirynen, KU Leuven.\\n\"\n\t);\n\t\n\tprintf(\n\t\t\"Developed within the Optimization in Engineering Center (OPTEC) under\\n\"\n\t\t\"supervision of Moritz Diehl. All rights reserved.\\n\\n\"\n\t\t\"ACADO Toolkit is distributed under the terms of the GNU Lesser\\n\"\n\t\t\"General Public License 3 in the hope that it will be useful,\\n\"\n\t\t\"but WITHOUT ANY WARRANTY; without even the implied warranty of\\n\"\n\t\t\"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\\n\"\n\t\t\"GNU Lesser General Public License for more details.\\n\\n\"\n\t);\n}\n\n#if !(defined _DSPACE)\n#if (defined _WIN32 || defined _WIN64) && !(defined __MINGW32__ || defined __MINGW64__)\n\nvoid acado_tic( acado_timer* t )\n{\n\tQueryPerformanceFrequency(&t->freq);\n\tQueryPerformanceCounter(&t->tic);\n}\n\nreal_t acado_toc( acado_timer* t )\n{\n\tQueryPerformanceCounter(&t->toc);\n\treturn ((t->toc.QuadPart - t->tic.QuadPart) / (real_t)t->freq.QuadPart);\n}\n\n\n#elif (defined __APPLE__)\n\nvoid acado_tic( acado_timer* t )\n{\n    /* read current clock cycles */\n    t->tic = mach_absolute_time();\n}\n\nreal_t acado_toc( acado_timer* t )\n{\n\n    uint64_t duration; /* elapsed time in clock cycles*/\n    \n    t->toc = mach_absolute_time();\n    duration = t->toc - t->tic;\n    \n    /*conversion from clock cycles to nanoseconds*/\n    mach_timebase_info(&(t->tinfo));\n    duration *= t->tinfo.numer;\n    duration /= t->tinfo.denom;\n\n    return (real_t)duration / 1e9;\n}\n\n#else\n\n#if __STDC_VERSION__ >= 199901L\n/* C99 mode */\n\n/* read current time */\nvoid acado_tic( acado_timer* t )\n{\n\tgettimeofday(&t->tic, 0);\n}\n\n/* return time passed since last call to tic on this timer */\nreal_t acado_toc( acado_timer* t )\n{\n\tstruct timeval temp;\n\t\n\tgettimeofday(&t->toc, 0);\n    \n\tif ((t->toc.tv_usec - t->tic.tv_usec) < 0)\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec - 1;\n\t\ttemp.tv_usec = 1000000 + t->toc.tv_usec - t->tic.tv_usec;\n\t}\n\telse\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec;\n\t\ttemp.tv_usec = t->toc.tv_usec - t->tic.tv_usec;\n\t}\n\t\n\treturn (real_t)temp.tv_sec + (real_t)temp.tv_usec / 1e6;\n}\n\n#else\n/* ANSI */\n\n/* read current time */\nvoid acado_tic( acado_timer* t )\n{\n\tclock_gettime(CLOCK_MONOTONIC, &t->tic);\n}\n\n\n/* return time passed since last call to tic on this timer */\nreal_t acado_toc( acado_timer* t )\n{\n\tstruct timespec temp;\n    \n\tclock_gettime(CLOCK_MONOTONIC, &t->toc);\t\n    \n\tif ((t->toc.tv_nsec - t->tic.tv_nsec) < 0)\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec - 1;\n\t\ttemp.tv_nsec = 1000000000+t->toc.tv_nsec - t->tic.tv_nsec;\n\t}\n\telse\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec;\n\t\ttemp.tv_nsec = t->toc.tv_nsec - t->tic.tv_nsec;\n\t}\n\t\n\treturn (real_t)temp.tv_sec + (real_t)temp.tv_nsec / 1e9;\n}\n\n#endif /* __STDC_VERSION__ >= 199901L */\n\n#endif /* (defined _WIN32 || _WIN64) */\n\n#endif\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_auxiliary_functions.h",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef ACADO_AUXILIARY_FUNCTIONS_H\n#define ACADO_AUXILIARY_FUNCTIONS_H\n\n#include \"acado_common.h\"\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n/** Get pointer to the matrix with differential variables. */\nreal_t* acado_getVariablesX( );\n\n/** Get pointer to the matrix with control variables. */\nreal_t* acado_getVariablesU( );\n\n#if ACADO_NY > 0\n/** Get pointer to the matrix with references/measurements. */\nreal_t* acado_getVariablesY( );\n#endif\n\n#if ACADO_NYN > 0\n/** Get pointer to the vector with references/measurement on the last node. */\nreal_t* acado_getVariablesYN( );\n#endif\n\n/** Get pointer to the current state feedback vector. Only applicable for NMPC. */\nreal_t* acado_getVariablesX0( );\n\n/** Print differential variables. */\nvoid acado_printDifferentialVariables( );\n\n/** Print control variables. */\nvoid acado_printControlVariables( );\n\n/** Print ACADO code generation notice. */\nvoid acado_printHeader( );\n\n/*\n * A huge thanks goes to Alexander Domahidi from ETHZ, Switzerland, for \n * providing us with the following timing routines.\n */\n\n#if !(defined _DSPACE)\n#if (defined _WIN32 || defined _WIN64) && !(defined __MINGW32__ || defined __MINGW64__)\n\n/* Use Windows QueryPerformanceCounter for timing. */\n#include <Windows.h>\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tLARGE_INTEGER tic;\n\tLARGE_INTEGER toc;\n\tLARGE_INTEGER freq;\n} acado_timer;\n\n\n#elif (defined __APPLE__)\n\n#include \"unistd.h\"\n#include <mach/mach_time.h>\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tuint64_t tic;\n\tuint64_t toc;\n\tmach_timebase_info_data_t tinfo;\n} acado_timer;\n\n#else\n\n/* Use POSIX clock_gettime() for timing on non-Windows machines. */\n#include <time.h>\n\n#if __STDC_VERSION__ >= 199901L\n/* C99 mode of operation. */\n\n#include <sys/stat.h>\n#include <sys/time.h>\n\ntypedef struct acado_timer_\n{\n\tstruct timeval tic;\n\tstruct timeval toc;\n} acado_timer;\n\n#else\n/* ANSI C */\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tstruct timespec tic;\n\tstruct timespec toc;\n} acado_timer;\n\n#endif /* __STDC_VERSION__ >= 199901L */\n\n#endif /* (defined _WIN32 || defined _WIN64) */\n\n/** A function for measurement of the current time. */\nvoid acado_tic( acado_timer* t );\n\n/** A function which returns the elapsed time. */\nreal_t acado_toc( acado_timer* t );\n\n#endif\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\n} /* extern \"C\" */\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n#endif /* ACADO_AUXILIARY_FUNCTIONS_H */\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_common.h",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef ACADO_COMMON_H\n#define ACADO_COMMON_H\n\n#include <math.h>\n#include <string.h>\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n/** \\defgroup ACADO ACADO CGT generated module. */\n/** @{ */\n\n/** qpOASES QP solver indicator. */\n#define ACADO_QPOASES  0\n#define ACADO_QPOASES3 1\n/** FORCES QP solver indicator.*/\n#define ACADO_FORCES   2\n/** qpDUNES QP solver indicator.*/\n#define ACADO_QPDUNES  3\n/** HPMPC QP solver indicator. */\n#define ACADO_HPMPC    4\n#define ACADO_GENERIC    5\n\n/** Indicator for determining the QP solver used by the ACADO solver code. */\n#define ACADO_QP_SOLVER ACADO_QPOASES\n\n#include \"acado_qpoases_interface.hpp\"\n\n\n/*\n * Common definitions\n */\n/** User defined block based condensing. */\n#define ACADO_BLOCK_CONDENSING 0\n/** Compute covariance matrix of the last state estimate. */\n#define ACADO_COMPUTE_COVARIANCE_MATRIX 0\n/** Flag indicating whether constraint values are hard-coded or not. */\n#define ACADO_HARDCODED_CONSTRAINT_VALUES 1\n/** Indicator for fixed initial state. */\n#define ACADO_INITIAL_STATE_FIXED 1\n/** Number of control/estimation intervals. */\n#define ACADO_N 16\n/** Number of online data values. */\n#define ACADO_NOD 2\n/** Number of path constraints. */\n#define ACADO_NPAC 0\n/** Number of control variables. */\n#define ACADO_NU 1\n/** Number of differential variables. */\n#define ACADO_NX 4\n/** Number of algebraic variables. */\n#define ACADO_NXA 0\n/** Number of differential derivative variables. */\n#define ACADO_NXD 0\n/** Number of references/measurements per node on the first N nodes. */\n#define ACADO_NY 3\n/** Number of references/measurements on the last (N + 1)st node. */\n#define ACADO_NYN 2\n/** Total number of QP optimization variables. */\n#define ACADO_QP_NV 20\n/** Number of Runge-Kutta stages per integration step. */\n#define ACADO_RK_NSTAGES 4\n/** Providing interface for arrival cost. */\n#define ACADO_USE_ARRIVAL_COST 0\n/** Indicator for usage of non-hard-coded linear terms in the objective. */\n#define ACADO_USE_LINEAR_TERMS 0\n/** Indicator for type of fixed weighting matrices. */\n#define ACADO_WEIGHTING_MATRICES_TYPE 2\n\n\n/*\n * Globally used structure definitions\n */\n\n/** The structure containing the user data.\n * \n *  Via this structure the user \"communicates\" with the solver code.\n */\ntypedef struct ACADOvariables_\n{\nint dummy;\n/** Matrix of size: 17 x 4 (row major format)\n * \n *  Matrix containing 17 differential variable vectors.\n */\nreal_t x[ 68 ];\n\n/** Column vector of size: 16\n * \n *  Matrix containing 16 control variable vectors.\n */\nreal_t u[ 16 ];\n\n/** Matrix of size: 17 x 2 (row major format)\n * \n *  Matrix containing 17 online data vectors.\n */\nreal_t od[ 34 ];\n\n/** Column vector of size: 48\n * \n *  Matrix containing 16 reference/measurement vectors of size 3 for first 16 nodes.\n */\nreal_t y[ 48 ];\n\n/** Column vector of size: 2\n * \n *  Reference/measurement vector for the 17. node.\n */\nreal_t yN[ 2 ];\n\n/** Matrix of size: 48 x 3 (row major format) */\nreal_t W[ 144 ];\n\n/** Matrix of size: 2 x 2 (row major format) */\nreal_t WN[ 4 ];\n\n/** Column vector of size: 4\n * \n *  Current state feedback vector.\n */\nreal_t x0[ 4 ];\n\n\n} ACADOvariables;\n\n/** Private workspace used by the auto-generated code.\n * \n *  Data members of this structure are private to the solver.\n *  In other words, the user code should not modify values of this \n *  structure. \n */\ntypedef struct ACADOworkspace_\n{\n/** Column vector of size: 14 */\nreal_t rhs_aux[ 14 ];\n\nreal_t rk_ttt;\n\n/** Row vector of size: 27 */\nreal_t rk_xxx[ 27 ];\n\n/** Matrix of size: 4 x 24 (row major format) */\nreal_t rk_kkk[ 96 ];\n\n/** Row vector of size: 27 */\nreal_t state[ 27 ];\n\n/** Column vector of size: 64 */\nreal_t d[ 64 ];\n\n/** Column vector of size: 48 */\nreal_t Dy[ 48 ];\n\n/** Column vector of size: 2 */\nreal_t DyN[ 2 ];\n\n/** Matrix of size: 64 x 4 (row major format) */\nreal_t evGx[ 256 ];\n\n/** Column vector of size: 64 */\nreal_t evGu[ 64 ];\n\n/** Row vector of size: 7 */\nreal_t objValueIn[ 7 ];\n\n/** Row vector of size: 18 */\nreal_t objValueOut[ 18 ];\n\n/** Matrix of size: 64 x 4 (row major format) */\nreal_t Q1[ 256 ];\n\n/** Matrix of size: 64 x 3 (row major format) */\nreal_t Q2[ 192 ];\n\n/** Column vector of size: 16 */\nreal_t R1[ 16 ];\n\n/** Matrix of size: 16 x 3 (row major format) */\nreal_t R2[ 48 ];\n\n/** Column vector of size: 64 */\nreal_t S1[ 64 ];\n\n/** Matrix of size: 4 x 4 (row major format) */\nreal_t QN1[ 16 ];\n\n/** Matrix of size: 4 x 2 (row major format) */\nreal_t QN2[ 8 ];\n\n/** Column vector of size: 4 */\nreal_t Dx0[ 4 ];\n\n/** Matrix of size: 4 x 4 (row major format) */\nreal_t T[ 16 ];\n\n/** Column vector of size: 544 */\nreal_t E[ 544 ];\n\n/** Column vector of size: 544 */\nreal_t QE[ 544 ];\n\n/** Matrix of size: 64 x 4 (row major format) */\nreal_t QGx[ 256 ];\n\n/** Column vector of size: 64 */\nreal_t Qd[ 64 ];\n\n/** Column vector of size: 68 */\nreal_t QDy[ 68 ];\n\n/** Matrix of size: 16 x 4 (row major format) */\nreal_t H10[ 64 ];\n\n/** Matrix of size: 20 x 20 (row major format) */\nreal_t H[ 400 ];\n\n/** Matrix of size: 32 x 20 (row major format) */\nreal_t A[ 640 ];\n\n/** Column vector of size: 20 */\nreal_t g[ 20 ];\n\n/** Column vector of size: 20 */\nreal_t lb[ 20 ];\n\n/** Column vector of size: 20 */\nreal_t ub[ 20 ];\n\n/** Column vector of size: 32 */\nreal_t lbA[ 32 ];\n\n/** Column vector of size: 32 */\nreal_t ubA[ 32 ];\n\n/** Column vector of size: 20 */\nreal_t x[ 20 ];\n\n/** Column vector of size: 52 */\nreal_t y[ 52 ];\n\n\n} ACADOworkspace;\n\n/* \n * Forward function declarations. \n */\n\n\n/** Performs the integration and sensitivity propagation for one shooting interval.\n *\n *  \\param rk_eta Working array to pass the input values and return the results.\n *  \\param resetIntegrator The internal memory of the integrator can be reset.\n *  \\param rk_index Number of the shooting interval.\n *\n *  \\return Status code of the integrator.\n */\nint acado_integrate( real_t* const rk_eta, int resetIntegrator, int rk_index );\n\n/** Export of an ACADO symbolic function.\n *\n *  \\param in Input to the exported function.\n *  \\param out Output of the exported function.\n */\nvoid acado_rhs_forw(const real_t* in, real_t* out);\n\n/** Preparation step of the RTI scheme.\n *\n *  \\return Status of the integration module. =0: OK, otherwise the error code.\n */\nint acado_preparationStep(  );\n\n/** Feedback/estimation step of the RTI scheme.\n *\n *  \\return Status code of the qpOASES QP solver.\n */\nint acado_feedbackStep(  );\n\n/** Solver initialization. Must be called once before any other function call.\n *\n *  \\return =0: OK, otherwise an error code of a QP solver.\n */\nint acado_initializeSolver(  );\n\n/** Initialize shooting nodes by a forward simulation starting from the first node.\n */\nvoid acado_initializeNodesByForwardSimulation(  );\n\n/** Shift differential variables vector by one interval.\n *\n *  \\param strategy Shifting strategy: 1. Initialize node 17 with xEnd. 2. Initialize node 17 by forward simulation.\n *  \\param xEnd Value for the x vector on the last node. If =0 the old value is used.\n *  \\param uEnd Value for the u vector on the second to last node. If =0 the old value is used.\n */\nvoid acado_shiftStates( int strategy, real_t* const xEnd, real_t* const uEnd );\n\n/** Shift controls vector by one interval.\n *\n *  \\param uEnd Value for the u vector on the second to last node. If =0 the old value is used.\n */\nvoid acado_shiftControls( real_t* const uEnd );\n\n/** Get the KKT tolerance of the current iterate.\n *\n *  \\return The KKT tolerance value.\n */\nreal_t acado_getKKT(  );\n\n/** Calculate the objective value.\n *\n *  \\return Value of the objective function.\n */\nreal_t acado_getObjective(  );\n\n\n/* \n * Extern declarations. \n */\n\nextern ACADOworkspace acadoWorkspace;\nextern ACADOvariables acadoVariables;\n\n/** @} */\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\n} /* extern \"C\" */\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n#endif /* ACADO_COMMON_H */\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_integrator.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_common.h\"\n\n\nvoid acado_rhs_forw(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 24;\nconst real_t* od = in + 25;\n/* Vector of auxiliary variables; number of elements: 14. */\nreal_t* a = acadoWorkspace.rhs_aux;\n\n/* Compute intermediate quantities: */\na[0] = (cos(xd[2]));\na[1] = (sin(xd[2]));\na[2] = ((real_t)(-1.0000000000000000e+00)*(sin(xd[2])));\na[3] = (xd[12]*a[2]);\na[4] = (xd[13]*a[2]);\na[5] = (xd[14]*a[2]);\na[6] = (xd[15]*a[2]);\na[7] = (cos(xd[2]));\na[8] = (xd[12]*a[7]);\na[9] = (xd[13]*a[7]);\na[10] = (xd[14]*a[7]);\na[11] = (xd[15]*a[7]);\na[12] = (xd[22]*a[2]);\na[13] = (xd[22]*a[7]);\n\n/* Compute outputs: */\nout[0] = (od[0]*a[0]);\nout[1] = (od[0]*a[1]);\nout[2] = (od[0]*xd[3]);\nout[3] = u[0];\nout[4] = (od[0]*a[3]);\nout[5] = (od[0]*a[4]);\nout[6] = (od[0]*a[5]);\nout[7] = (od[0]*a[6]);\nout[8] = (od[0]*a[8]);\nout[9] = (od[0]*a[9]);\nout[10] = (od[0]*a[10]);\nout[11] = (od[0]*a[11]);\nout[12] = (od[0]*xd[16]);\nout[13] = (od[0]*xd[17]);\nout[14] = (od[0]*xd[18]);\nout[15] = (od[0]*xd[19]);\nout[16] = (real_t)(0.0000000000000000e+00);\nout[17] = (real_t)(0.0000000000000000e+00);\nout[18] = (real_t)(0.0000000000000000e+00);\nout[19] = (real_t)(0.0000000000000000e+00);\nout[20] = (od[0]*a[12]);\nout[21] = (od[0]*a[13]);\nout[22] = (od[0]*xd[23]);\nout[23] = (real_t)(1.0000000000000000e+00);\n}\n\n/* Fixed step size:0.0025 */\nint acado_integrate( real_t* const rk_eta, int resetIntegrator, int rk_index )\n{\nint error;\n\nint run1;\nint numSteps[16] = {4, 12, 20, 27, 35, 43, 51, 59, 66, 74, 82, 90, 98, 105, 113, 121};\nint numInts = numSteps[rk_index];\nacadoWorkspace.rk_ttt = 0.0000000000000000e+00;\nrk_eta[4] = 1.0000000000000000e+00;\nrk_eta[5] = 0.0000000000000000e+00;\nrk_eta[6] = 0.0000000000000000e+00;\nrk_eta[7] = 0.0000000000000000e+00;\nrk_eta[8] = 0.0000000000000000e+00;\nrk_eta[9] = 1.0000000000000000e+00;\nrk_eta[10] = 0.0000000000000000e+00;\nrk_eta[11] = 0.0000000000000000e+00;\nrk_eta[12] = 0.0000000000000000e+00;\nrk_eta[13] = 0.0000000000000000e+00;\nrk_eta[14] = 1.0000000000000000e+00;\nrk_eta[15] = 0.0000000000000000e+00;\nrk_eta[16] = 0.0000000000000000e+00;\nrk_eta[17] = 0.0000000000000000e+00;\nrk_eta[18] = 0.0000000000000000e+00;\nrk_eta[19] = 1.0000000000000000e+00;\nrk_eta[20] = 0.0000000000000000e+00;\nrk_eta[21] = 0.0000000000000000e+00;\nrk_eta[22] = 0.0000000000000000e+00;\nrk_eta[23] = 0.0000000000000000e+00;\nacadoWorkspace.rk_xxx[24] = rk_eta[24];\nacadoWorkspace.rk_xxx[25] = rk_eta[25];\nacadoWorkspace.rk_xxx[26] = rk_eta[26];\n\nfor (run1 = 0; run1 < 1; ++run1)\n{\nfor(run1 = 0; run1 < numInts; run1++ ) {\nacadoWorkspace.rk_xxx[0] = + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + rk_eta[23];\nacado_rhs_forw( acadoWorkspace.rk_xxx, acadoWorkspace.rk_kkk );\nacadoWorkspace.rk_xxx[0] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[0] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[1] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[2] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[3] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[4] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[5] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[6] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[7] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[8] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[9] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[10] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[11] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[12] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[13] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[14] + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[15] + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[16] + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[17] + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[18] + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[19] + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[20] + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[21] + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[22] + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[23] + rk_eta[23];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 24 ]) );\nacadoWorkspace.rk_xxx[0] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[24] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[25] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[26] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[27] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[28] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[29] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[30] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[31] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[32] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[33] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[34] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[35] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[36] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[37] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[38] + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[39] + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[40] + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[41] + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[42] + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[43] + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[44] + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[45] + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[46] + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + (real_t)1.2500000000000000e-03*acadoWorkspace.rk_kkk[47] + rk_eta[23];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 48 ]) );\nacadoWorkspace.rk_xxx[0] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[48] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[49] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[50] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[51] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[52] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[53] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[54] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[55] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[56] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[57] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[58] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[59] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[60] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[61] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[62] + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[63] + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[64] + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[65] + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[66] + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[67] + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[68] + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[69] + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[70] + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + (real_t)2.5000000000000001e-03*acadoWorkspace.rk_kkk[71] + rk_eta[23];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 72 ]) );\nrk_eta[0] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[0] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[24] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[48] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[72];\nrk_eta[1] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[1] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[25] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[49] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[73];\nrk_eta[2] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[2] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[26] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[50] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[74];\nrk_eta[3] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[3] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[27] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[51] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[75];\nrk_eta[4] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[4] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[28] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[52] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[76];\nrk_eta[5] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[5] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[29] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[53] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[77];\nrk_eta[6] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[6] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[30] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[54] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[78];\nrk_eta[7] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[7] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[31] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[55] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[79];\nrk_eta[8] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[8] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[32] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[56] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[80];\nrk_eta[9] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[9] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[33] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[57] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[81];\nrk_eta[10] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[10] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[34] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[58] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[82];\nrk_eta[11] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[11] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[35] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[59] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[83];\nrk_eta[12] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[12] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[36] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[60] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[84];\nrk_eta[13] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[13] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[37] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[61] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[85];\nrk_eta[14] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[14] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[38] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[62] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[86];\nrk_eta[15] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[15] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[39] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[63] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[87];\nrk_eta[16] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[16] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[40] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[64] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[88];\nrk_eta[17] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[17] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[41] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[65] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[89];\nrk_eta[18] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[18] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[42] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[66] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[90];\nrk_eta[19] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[19] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[43] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[67] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[91];\nrk_eta[20] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[20] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[44] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[68] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[92];\nrk_eta[21] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[21] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[45] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[69] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[93];\nrk_eta[22] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[22] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[46] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[70] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[94];\nrk_eta[23] += + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[23] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[47] + (real_t)8.3333333333333328e-04*acadoWorkspace.rk_kkk[71] + (real_t)4.1666666666666664e-04*acadoWorkspace.rk_kkk[95];\nacadoWorkspace.rk_ttt += 1.0000000000000000e+00;\n}\n}\nerror = 0;\nreturn error;\n}\n\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_qpoases_interface.cpp",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\nextern \"C\"\n{\n#include \"acado_common.h\"\n}\n\n#include \"INCLUDE/QProblem.hpp\"\n\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\n#include \"INCLUDE/EXTRAS/SolutionAnalysis.hpp\"\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\nstatic int acado_nWSR;\n\n\n\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\nstatic SolutionAnalysis acado_sa;\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\nint acado_solve( void )\n{\n\tacado_nWSR = QPOASES_NWSRMAX;\n\n\tQProblem qp(20, 32);\n\t\n\treturnValue retVal = qp.init(acadoWorkspace.H, acadoWorkspace.g, acadoWorkspace.A, acadoWorkspace.lb, acadoWorkspace.ub, acadoWorkspace.lbA, acadoWorkspace.ubA, acado_nWSR, acadoWorkspace.y);\n\n    qp.getPrimalSolution( acadoWorkspace.x );\n    qp.getDualSolution( acadoWorkspace.y );\n\t\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\n\n\tif (retVal != SUCCESSFUL_RETURN)\n\t\treturn (int)retVal;\n\t\t\n\tretVal = acado_sa.getHessianInverse( &qp,var );\n\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\n\treturn (int)retVal;\n}\n\nint acado_getNWSR( void )\n{\n\treturn acado_nWSR;\n}\n\nconst char* acado_getErrorString( int error )\n{\n\treturn MessageHandling::getErrorString( error );\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_qpoases_interface.hpp",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef QPOASES_HEADER\n#define QPOASES_HEADER\n\n#ifdef PC_DEBUG\n#include <stdio.h>\n#endif /* PC_DEBUG */\n\n#include <math.h>\n\n#ifdef __cplusplus\n#define EXTERNC extern \"C\"\n#else\n#define EXTERNC\n#endif\n\n/*\n * A set of options for qpOASES\n */\n\n/** Maximum number of optimization variables. */\n#define QPOASES_NVMAX      20\n/** Maximum number of constraints. */\n#define QPOASES_NCMAX      32\n/** Maximum number of working set recalculations. */\n#define QPOASES_NWSRMAX    50\n/** Print level for qpOASES. */\n#define QPOASES_PRINTLEVEL PL_NONE\n/** The value of EPS */\n#define QPOASES_EPS        2.221e-16\n/** Internally used floating point type */\ntypedef double real_t;\n\n/*\n * Forward function declarations\n */\n\n/** A function that calls the QP solver */\nEXTERNC int acado_solve( void );\n\n/** Get the number of active set changes */\nEXTERNC int acado_getNWSR( void );\n\n/** Get the error string. */\nconst char* acado_getErrorString( int error );\n\n#endif /* QPOASES_HEADER */\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/lib_mpc_export/acado_solver.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_common.h\"\n\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/* ACADO code generation                                                      */\n/*                                                                            */\n/******************************************************************************/\n\n\nint acado_modelSimulation(  )\n{\nint ret;\n\nint lRun1;\nret = 0;\nfor (lRun1 = 0; lRun1 < 16; ++lRun1)\n{\nacadoWorkspace.state[0] = acadoVariables.x[lRun1 * 4];\nacadoWorkspace.state[1] = acadoVariables.x[lRun1 * 4 + 1];\nacadoWorkspace.state[2] = acadoVariables.x[lRun1 * 4 + 2];\nacadoWorkspace.state[3] = acadoVariables.x[lRun1 * 4 + 3];\n\nacadoWorkspace.state[24] = acadoVariables.u[lRun1];\nacadoWorkspace.state[25] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.state[26] = acadoVariables.od[lRun1 * 2 + 1];\n\nret = acado_integrate(acadoWorkspace.state, 1, lRun1);\n\nacadoWorkspace.d[lRun1 * 4] = acadoWorkspace.state[0] - acadoVariables.x[lRun1 * 4 + 4];\nacadoWorkspace.d[lRun1 * 4 + 1] = acadoWorkspace.state[1] - acadoVariables.x[lRun1 * 4 + 5];\nacadoWorkspace.d[lRun1 * 4 + 2] = acadoWorkspace.state[2] - acadoVariables.x[lRun1 * 4 + 6];\nacadoWorkspace.d[lRun1 * 4 + 3] = acadoWorkspace.state[3] - acadoVariables.x[lRun1 * 4 + 7];\n\nacadoWorkspace.evGx[lRun1 * 16] = acadoWorkspace.state[4];\nacadoWorkspace.evGx[lRun1 * 16 + 1] = acadoWorkspace.state[5];\nacadoWorkspace.evGx[lRun1 * 16 + 2] = acadoWorkspace.state[6];\nacadoWorkspace.evGx[lRun1 * 16 + 3] = acadoWorkspace.state[7];\nacadoWorkspace.evGx[lRun1 * 16 + 4] = acadoWorkspace.state[8];\nacadoWorkspace.evGx[lRun1 * 16 + 5] = acadoWorkspace.state[9];\nacadoWorkspace.evGx[lRun1 * 16 + 6] = acadoWorkspace.state[10];\nacadoWorkspace.evGx[lRun1 * 16 + 7] = acadoWorkspace.state[11];\nacadoWorkspace.evGx[lRun1 * 16 + 8] = acadoWorkspace.state[12];\nacadoWorkspace.evGx[lRun1 * 16 + 9] = acadoWorkspace.state[13];\nacadoWorkspace.evGx[lRun1 * 16 + 10] = acadoWorkspace.state[14];\nacadoWorkspace.evGx[lRun1 * 16 + 11] = acadoWorkspace.state[15];\nacadoWorkspace.evGx[lRun1 * 16 + 12] = acadoWorkspace.state[16];\nacadoWorkspace.evGx[lRun1 * 16 + 13] = acadoWorkspace.state[17];\nacadoWorkspace.evGx[lRun1 * 16 + 14] = acadoWorkspace.state[18];\nacadoWorkspace.evGx[lRun1 * 16 + 15] = acadoWorkspace.state[19];\n\nacadoWorkspace.evGu[lRun1 * 4] = acadoWorkspace.state[20];\nacadoWorkspace.evGu[lRun1 * 4 + 1] = acadoWorkspace.state[21];\nacadoWorkspace.evGu[lRun1 * 4 + 2] = acadoWorkspace.state[22];\nacadoWorkspace.evGu[lRun1 * 4 + 3] = acadoWorkspace.state[23];\n}\nreturn ret;\n}\n\nvoid acado_evaluateLSQ(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 4;\nconst real_t* od = in + 5;\n\n/* Compute outputs: */\nout[0] = xd[1];\nout[1] = ((od[0]+(real_t)(5.0000000000000000e+00))*xd[2]);\nout[2] = (((od[0]+(real_t)(5.0000000000000000e+00))*(real_t)(4.0000000000000000e+00))*u[0]);\nout[3] = (real_t)(0.0000000000000000e+00);\nout[4] = (real_t)(1.0000000000000000e+00);\nout[5] = (real_t)(0.0000000000000000e+00);\nout[6] = (real_t)(0.0000000000000000e+00);\nout[7] = (real_t)(0.0000000000000000e+00);\nout[8] = (real_t)(0.0000000000000000e+00);\nout[9] = (od[0]+(real_t)(5.0000000000000000e+00));\nout[10] = (real_t)(0.0000000000000000e+00);\nout[11] = (real_t)(0.0000000000000000e+00);\nout[12] = (real_t)(0.0000000000000000e+00);\nout[13] = (real_t)(0.0000000000000000e+00);\nout[14] = (real_t)(0.0000000000000000e+00);\nout[15] = (real_t)(0.0000000000000000e+00);\nout[16] = (real_t)(0.0000000000000000e+00);\nout[17] = ((od[0]+(real_t)(5.0000000000000000e+00))*(real_t)(4.0000000000000000e+00));\n}\n\nvoid acado_evaluateLSQEndTerm(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* od = in + 4;\n\n/* Compute outputs: */\nout[0] = xd[1];\nout[1] = ((((real_t)(2.0000000000000000e+00)*od[0])+(real_t)(5.0000000000000000e+00))*xd[2]);\nout[2] = (real_t)(0.0000000000000000e+00);\nout[3] = (real_t)(1.0000000000000000e+00);\nout[4] = (real_t)(0.0000000000000000e+00);\nout[5] = (real_t)(0.0000000000000000e+00);\nout[6] = (real_t)(0.0000000000000000e+00);\nout[7] = (real_t)(0.0000000000000000e+00);\nout[8] = (((real_t)(2.0000000000000000e+00)*od[0])+(real_t)(5.0000000000000000e+00));\nout[9] = (real_t)(0.0000000000000000e+00);\n}\n\nvoid acado_setObjQ1Q2( real_t* const tmpFx, real_t* const tmpObjS, real_t* const tmpQ1, real_t* const tmpQ2 )\n{\ntmpQ2[0] = + tmpFx[0]*tmpObjS[0] + tmpFx[4]*tmpObjS[3] + tmpFx[8]*tmpObjS[6];\ntmpQ2[1] = + tmpFx[0]*tmpObjS[1] + tmpFx[4]*tmpObjS[4] + tmpFx[8]*tmpObjS[7];\ntmpQ2[2] = + tmpFx[0]*tmpObjS[2] + tmpFx[4]*tmpObjS[5] + tmpFx[8]*tmpObjS[8];\ntmpQ2[3] = + tmpFx[1]*tmpObjS[0] + tmpFx[5]*tmpObjS[3] + tmpFx[9]*tmpObjS[6];\ntmpQ2[4] = + tmpFx[1]*tmpObjS[1] + tmpFx[5]*tmpObjS[4] + tmpFx[9]*tmpObjS[7];\ntmpQ2[5] = + tmpFx[1]*tmpObjS[2] + tmpFx[5]*tmpObjS[5] + tmpFx[9]*tmpObjS[8];\ntmpQ2[6] = + tmpFx[2]*tmpObjS[0] + tmpFx[6]*tmpObjS[3] + tmpFx[10]*tmpObjS[6];\ntmpQ2[7] = + tmpFx[2]*tmpObjS[1] + tmpFx[6]*tmpObjS[4] + tmpFx[10]*tmpObjS[7];\ntmpQ2[8] = + tmpFx[2]*tmpObjS[2] + tmpFx[6]*tmpObjS[5] + tmpFx[10]*tmpObjS[8];\ntmpQ2[9] = + tmpFx[3]*tmpObjS[0] + tmpFx[7]*tmpObjS[3] + tmpFx[11]*tmpObjS[6];\ntmpQ2[10] = + tmpFx[3]*tmpObjS[1] + tmpFx[7]*tmpObjS[4] + tmpFx[11]*tmpObjS[7];\ntmpQ2[11] = + tmpFx[3]*tmpObjS[2] + tmpFx[7]*tmpObjS[5] + tmpFx[11]*tmpObjS[8];\ntmpQ1[0] = + tmpQ2[0]*tmpFx[0] + tmpQ2[1]*tmpFx[4] + tmpQ2[2]*tmpFx[8];\ntmpQ1[1] = + tmpQ2[0]*tmpFx[1] + tmpQ2[1]*tmpFx[5] + tmpQ2[2]*tmpFx[9];\ntmpQ1[2] = + tmpQ2[0]*tmpFx[2] + tmpQ2[1]*tmpFx[6] + tmpQ2[2]*tmpFx[10];\ntmpQ1[3] = + tmpQ2[0]*tmpFx[3] + tmpQ2[1]*tmpFx[7] + tmpQ2[2]*tmpFx[11];\ntmpQ1[4] = + tmpQ2[3]*tmpFx[0] + tmpQ2[4]*tmpFx[4] + tmpQ2[5]*tmpFx[8];\ntmpQ1[5] = + tmpQ2[3]*tmpFx[1] + tmpQ2[4]*tmpFx[5] + tmpQ2[5]*tmpFx[9];\ntmpQ1[6] = + tmpQ2[3]*tmpFx[2] + tmpQ2[4]*tmpFx[6] + tmpQ2[5]*tmpFx[10];\ntmpQ1[7] = + tmpQ2[3]*tmpFx[3] + tmpQ2[4]*tmpFx[7] + tmpQ2[5]*tmpFx[11];\ntmpQ1[8] = + tmpQ2[6]*tmpFx[0] + tmpQ2[7]*tmpFx[4] + tmpQ2[8]*tmpFx[8];\ntmpQ1[9] = + tmpQ2[6]*tmpFx[1] + tmpQ2[7]*tmpFx[5] + tmpQ2[8]*tmpFx[9];\ntmpQ1[10] = + tmpQ2[6]*tmpFx[2] + tmpQ2[7]*tmpFx[6] + tmpQ2[8]*tmpFx[10];\ntmpQ1[11] = + tmpQ2[6]*tmpFx[3] + tmpQ2[7]*tmpFx[7] + tmpQ2[8]*tmpFx[11];\ntmpQ1[12] = + tmpQ2[9]*tmpFx[0] + tmpQ2[10]*tmpFx[4] + tmpQ2[11]*tmpFx[8];\ntmpQ1[13] = + tmpQ2[9]*tmpFx[1] + tmpQ2[10]*tmpFx[5] + tmpQ2[11]*tmpFx[9];\ntmpQ1[14] = + tmpQ2[9]*tmpFx[2] + tmpQ2[10]*tmpFx[6] + tmpQ2[11]*tmpFx[10];\ntmpQ1[15] = + tmpQ2[9]*tmpFx[3] + tmpQ2[10]*tmpFx[7] + tmpQ2[11]*tmpFx[11];\n}\n\nvoid acado_setObjR1R2( real_t* const tmpFu, real_t* const tmpObjS, real_t* const tmpR1, real_t* const tmpR2 )\n{\ntmpR2[0] = + tmpFu[0]*tmpObjS[0] + tmpFu[1]*tmpObjS[3] + tmpFu[2]*tmpObjS[6];\ntmpR2[1] = + tmpFu[0]*tmpObjS[1] + tmpFu[1]*tmpObjS[4] + tmpFu[2]*tmpObjS[7];\ntmpR2[2] = + tmpFu[0]*tmpObjS[2] + tmpFu[1]*tmpObjS[5] + tmpFu[2]*tmpObjS[8];\ntmpR1[0] = + tmpR2[0]*tmpFu[0] + tmpR2[1]*tmpFu[1] + tmpR2[2]*tmpFu[2];\n}\n\nvoid acado_setObjQN1QN2( real_t* const tmpFx, real_t* const tmpObjSEndTerm, real_t* const tmpQN1, real_t* const tmpQN2 )\n{\ntmpQN2[0] = + tmpFx[0]*tmpObjSEndTerm[0] + tmpFx[4]*tmpObjSEndTerm[2];\ntmpQN2[1] = + tmpFx[0]*tmpObjSEndTerm[1] + tmpFx[4]*tmpObjSEndTerm[3];\ntmpQN2[2] = + tmpFx[1]*tmpObjSEndTerm[0] + tmpFx[5]*tmpObjSEndTerm[2];\ntmpQN2[3] = + tmpFx[1]*tmpObjSEndTerm[1] + tmpFx[5]*tmpObjSEndTerm[3];\ntmpQN2[4] = + tmpFx[2]*tmpObjSEndTerm[0] + tmpFx[6]*tmpObjSEndTerm[2];\ntmpQN2[5] = + tmpFx[2]*tmpObjSEndTerm[1] + tmpFx[6]*tmpObjSEndTerm[3];\ntmpQN2[6] = + tmpFx[3]*tmpObjSEndTerm[0] + tmpFx[7]*tmpObjSEndTerm[2];\ntmpQN2[7] = + tmpFx[3]*tmpObjSEndTerm[1] + tmpFx[7]*tmpObjSEndTerm[3];\ntmpQN1[0] = + tmpQN2[0]*tmpFx[0] + tmpQN2[1]*tmpFx[4];\ntmpQN1[1] = + tmpQN2[0]*tmpFx[1] + tmpQN2[1]*tmpFx[5];\ntmpQN1[2] = + tmpQN2[0]*tmpFx[2] + tmpQN2[1]*tmpFx[6];\ntmpQN1[3] = + tmpQN2[0]*tmpFx[3] + tmpQN2[1]*tmpFx[7];\ntmpQN1[4] = + tmpQN2[2]*tmpFx[0] + tmpQN2[3]*tmpFx[4];\ntmpQN1[5] = + tmpQN2[2]*tmpFx[1] + tmpQN2[3]*tmpFx[5];\ntmpQN1[6] = + tmpQN2[2]*tmpFx[2] + tmpQN2[3]*tmpFx[6];\ntmpQN1[7] = + tmpQN2[2]*tmpFx[3] + tmpQN2[3]*tmpFx[7];\ntmpQN1[8] = + tmpQN2[4]*tmpFx[0] + tmpQN2[5]*tmpFx[4];\ntmpQN1[9] = + tmpQN2[4]*tmpFx[1] + tmpQN2[5]*tmpFx[5];\ntmpQN1[10] = + tmpQN2[4]*tmpFx[2] + tmpQN2[5]*tmpFx[6];\ntmpQN1[11] = + tmpQN2[4]*tmpFx[3] + tmpQN2[5]*tmpFx[7];\ntmpQN1[12] = + tmpQN2[6]*tmpFx[0] + tmpQN2[7]*tmpFx[4];\ntmpQN1[13] = + tmpQN2[6]*tmpFx[1] + tmpQN2[7]*tmpFx[5];\ntmpQN1[14] = + tmpQN2[6]*tmpFx[2] + tmpQN2[7]*tmpFx[6];\ntmpQN1[15] = + tmpQN2[6]*tmpFx[3] + tmpQN2[7]*tmpFx[7];\n}\n\nvoid acado_evaluateObjective(  )\n{\nint runObj;\nfor (runObj = 0; runObj < 16; ++runObj)\n{\nacadoWorkspace.objValueIn[0] = acadoVariables.x[runObj * 4];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[runObj * 4 + 1];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[runObj * 4 + 2];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[runObj * 4 + 3];\nacadoWorkspace.objValueIn[4] = acadoVariables.u[runObj];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[runObj * 2];\nacadoWorkspace.objValueIn[6] = acadoVariables.od[runObj * 2 + 1];\n\nacado_evaluateLSQ( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\nacadoWorkspace.Dy[runObj * 3] = acadoWorkspace.objValueOut[0];\nacadoWorkspace.Dy[runObj * 3 + 1] = acadoWorkspace.objValueOut[1];\nacadoWorkspace.Dy[runObj * 3 + 2] = acadoWorkspace.objValueOut[2];\n\nacado_setObjQ1Q2( &(acadoWorkspace.objValueOut[ 3 ]), &(acadoVariables.W[ runObj * 9 ]), &(acadoWorkspace.Q1[ runObj * 16 ]), &(acadoWorkspace.Q2[ runObj * 12 ]) );\n\nacado_setObjR1R2( &(acadoWorkspace.objValueOut[ 15 ]), &(acadoVariables.W[ runObj * 9 ]), &(acadoWorkspace.R1[ runObj ]), &(acadoWorkspace.R2[ runObj * 3 ]) );\n\n}\nacadoWorkspace.objValueIn[0] = acadoVariables.x[64];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[65];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[66];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[67];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[32];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[33];\nacado_evaluateLSQEndTerm( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\n\nacadoWorkspace.DyN[0] = acadoWorkspace.objValueOut[0];\nacadoWorkspace.DyN[1] = acadoWorkspace.objValueOut[1];\n\nacado_setObjQN1QN2( &(acadoWorkspace.objValueOut[ 2 ]), acadoVariables.WN, acadoWorkspace.QN1, acadoWorkspace.QN2 );\n\n}\n\nvoid acado_multGxd( real_t* const dOld, real_t* const Gx1, real_t* const dNew )\n{\ndNew[0] += + Gx1[0]*dOld[0] + Gx1[1]*dOld[1] + Gx1[2]*dOld[2] + Gx1[3]*dOld[3];\ndNew[1] += + Gx1[4]*dOld[0] + Gx1[5]*dOld[1] + Gx1[6]*dOld[2] + Gx1[7]*dOld[3];\ndNew[2] += + Gx1[8]*dOld[0] + Gx1[9]*dOld[1] + Gx1[10]*dOld[2] + Gx1[11]*dOld[3];\ndNew[3] += + Gx1[12]*dOld[0] + Gx1[13]*dOld[1] + Gx1[14]*dOld[2] + Gx1[15]*dOld[3];\n}\n\nvoid acado_moveGxT( real_t* const Gx1, real_t* const Gx2 )\n{\nGx2[0] = Gx1[0];\nGx2[1] = Gx1[1];\nGx2[2] = Gx1[2];\nGx2[3] = Gx1[3];\nGx2[4] = Gx1[4];\nGx2[5] = Gx1[5];\nGx2[6] = Gx1[6];\nGx2[7] = Gx1[7];\nGx2[8] = Gx1[8];\nGx2[9] = Gx1[9];\nGx2[10] = Gx1[10];\nGx2[11] = Gx1[11];\nGx2[12] = Gx1[12];\nGx2[13] = Gx1[13];\nGx2[14] = Gx1[14];\nGx2[15] = Gx1[15];\n}\n\nvoid acado_multGxGx( real_t* const Gx1, real_t* const Gx2, real_t* const Gx3 )\n{\nGx3[0] = + Gx1[0]*Gx2[0] + Gx1[1]*Gx2[4] + Gx1[2]*Gx2[8] + Gx1[3]*Gx2[12];\nGx3[1] = + Gx1[0]*Gx2[1] + Gx1[1]*Gx2[5] + Gx1[2]*Gx2[9] + Gx1[3]*Gx2[13];\nGx3[2] = + Gx1[0]*Gx2[2] + Gx1[1]*Gx2[6] + Gx1[2]*Gx2[10] + Gx1[3]*Gx2[14];\nGx3[3] = + Gx1[0]*Gx2[3] + Gx1[1]*Gx2[7] + Gx1[2]*Gx2[11] + Gx1[3]*Gx2[15];\nGx3[4] = + Gx1[4]*Gx2[0] + Gx1[5]*Gx2[4] + Gx1[6]*Gx2[8] + Gx1[7]*Gx2[12];\nGx3[5] = + Gx1[4]*Gx2[1] + Gx1[5]*Gx2[5] + Gx1[6]*Gx2[9] + Gx1[7]*Gx2[13];\nGx3[6] = + Gx1[4]*Gx2[2] + Gx1[5]*Gx2[6] + Gx1[6]*Gx2[10] + Gx1[7]*Gx2[14];\nGx3[7] = + Gx1[4]*Gx2[3] + Gx1[5]*Gx2[7] + Gx1[6]*Gx2[11] + Gx1[7]*Gx2[15];\nGx3[8] = + Gx1[8]*Gx2[0] + Gx1[9]*Gx2[4] + Gx1[10]*Gx2[8] + Gx1[11]*Gx2[12];\nGx3[9] = + Gx1[8]*Gx2[1] + Gx1[9]*Gx2[5] + Gx1[10]*Gx2[9] + Gx1[11]*Gx2[13];\nGx3[10] = + Gx1[8]*Gx2[2] + Gx1[9]*Gx2[6] + Gx1[10]*Gx2[10] + Gx1[11]*Gx2[14];\nGx3[11] = + Gx1[8]*Gx2[3] + Gx1[9]*Gx2[7] + Gx1[10]*Gx2[11] + Gx1[11]*Gx2[15];\nGx3[12] = + Gx1[12]*Gx2[0] + Gx1[13]*Gx2[4] + Gx1[14]*Gx2[8] + Gx1[15]*Gx2[12];\nGx3[13] = + Gx1[12]*Gx2[1] + Gx1[13]*Gx2[5] + Gx1[14]*Gx2[9] + Gx1[15]*Gx2[13];\nGx3[14] = + Gx1[12]*Gx2[2] + Gx1[13]*Gx2[6] + Gx1[14]*Gx2[10] + Gx1[15]*Gx2[14];\nGx3[15] = + Gx1[12]*Gx2[3] + Gx1[13]*Gx2[7] + Gx1[14]*Gx2[11] + Gx1[15]*Gx2[15];\n}\n\nvoid acado_multGxGu( real_t* const Gx1, real_t* const Gu1, real_t* const Gu2 )\n{\nGu2[0] = + Gx1[0]*Gu1[0] + Gx1[1]*Gu1[1] + Gx1[2]*Gu1[2] + Gx1[3]*Gu1[3];\nGu2[1] = + Gx1[4]*Gu1[0] + Gx1[5]*Gu1[1] + Gx1[6]*Gu1[2] + Gx1[7]*Gu1[3];\nGu2[2] = + Gx1[8]*Gu1[0] + Gx1[9]*Gu1[1] + Gx1[10]*Gu1[2] + Gx1[11]*Gu1[3];\nGu2[3] = + Gx1[12]*Gu1[0] + Gx1[13]*Gu1[1] + Gx1[14]*Gu1[2] + Gx1[15]*Gu1[3];\n}\n\nvoid acado_moveGuE( real_t* const Gu1, real_t* const Gu2 )\n{\nGu2[0] = Gu1[0];\nGu2[1] = Gu1[1];\nGu2[2] = Gu1[2];\nGu2[3] = Gu1[3];\n}\n\nvoid acado_setBlockH11( int iRow, int iCol, real_t* const Gu1, real_t* const Gu2 )\n{\nacadoWorkspace.H[(iRow * 20 + 80) + (iCol + 4)] += + Gu1[0]*Gu2[0] + Gu1[1]*Gu2[1] + Gu1[2]*Gu2[2] + Gu1[3]*Gu2[3];\n}\n\nvoid acado_setBlockH11_R1( int iRow, int iCol, real_t* const R11 )\n{\nacadoWorkspace.H[(iRow * 20 + 80) + (iCol + 4)] = R11[0];\n}\n\nvoid acado_zeroBlockH11( int iRow, int iCol )\n{\nacadoWorkspace.H[(iRow * 20 + 80) + (iCol + 4)] = 0.0000000000000000e+00;\n}\n\nvoid acado_copyHTH( int iRow, int iCol )\n{\nacadoWorkspace.H[(iRow * 20 + 80) + (iCol + 4)] = acadoWorkspace.H[(iCol * 20 + 80) + (iRow + 4)];\n}\n\nvoid acado_multQ1d( real_t* const Gx1, real_t* const dOld, real_t* const dNew )\n{\ndNew[0] = + Gx1[0]*dOld[0] + Gx1[1]*dOld[1] + Gx1[2]*dOld[2] + Gx1[3]*dOld[3];\ndNew[1] = + Gx1[4]*dOld[0] + Gx1[5]*dOld[1] + Gx1[6]*dOld[2] + Gx1[7]*dOld[3];\ndNew[2] = + Gx1[8]*dOld[0] + Gx1[9]*dOld[1] + Gx1[10]*dOld[2] + Gx1[11]*dOld[3];\ndNew[3] = + Gx1[12]*dOld[0] + Gx1[13]*dOld[1] + Gx1[14]*dOld[2] + Gx1[15]*dOld[3];\n}\n\nvoid acado_multQN1d( real_t* const QN1, real_t* const dOld, real_t* const dNew )\n{\ndNew[0] = + acadoWorkspace.QN1[0]*dOld[0] + acadoWorkspace.QN1[1]*dOld[1] + acadoWorkspace.QN1[2]*dOld[2] + acadoWorkspace.QN1[3]*dOld[3];\ndNew[1] = + acadoWorkspace.QN1[4]*dOld[0] + acadoWorkspace.QN1[5]*dOld[1] + acadoWorkspace.QN1[6]*dOld[2] + acadoWorkspace.QN1[7]*dOld[3];\ndNew[2] = + acadoWorkspace.QN1[8]*dOld[0] + acadoWorkspace.QN1[9]*dOld[1] + acadoWorkspace.QN1[10]*dOld[2] + acadoWorkspace.QN1[11]*dOld[3];\ndNew[3] = + acadoWorkspace.QN1[12]*dOld[0] + acadoWorkspace.QN1[13]*dOld[1] + acadoWorkspace.QN1[14]*dOld[2] + acadoWorkspace.QN1[15]*dOld[3];\n}\n\nvoid acado_multRDy( real_t* const R2, real_t* const Dy1, real_t* const RDy1 )\n{\nRDy1[0] = + R2[0]*Dy1[0] + R2[1]*Dy1[1] + R2[2]*Dy1[2];\n}\n\nvoid acado_multQDy( real_t* const Q2, real_t* const Dy1, real_t* const QDy1 )\n{\nQDy1[0] = + Q2[0]*Dy1[0] + Q2[1]*Dy1[1] + Q2[2]*Dy1[2];\nQDy1[1] = + Q2[3]*Dy1[0] + Q2[4]*Dy1[1] + Q2[5]*Dy1[2];\nQDy1[2] = + Q2[6]*Dy1[0] + Q2[7]*Dy1[1] + Q2[8]*Dy1[2];\nQDy1[3] = + Q2[9]*Dy1[0] + Q2[10]*Dy1[1] + Q2[11]*Dy1[2];\n}\n\nvoid acado_multEQDy( real_t* const E1, real_t* const QDy1, real_t* const U1 )\n{\nU1[0] += + E1[0]*QDy1[0] + E1[1]*QDy1[1] + E1[2]*QDy1[2] + E1[3]*QDy1[3];\n}\n\nvoid acado_multQETGx( real_t* const E1, real_t* const Gx1, real_t* const H101 )\n{\nH101[0] += + E1[0]*Gx1[0] + E1[1]*Gx1[4] + E1[2]*Gx1[8] + E1[3]*Gx1[12];\nH101[1] += + E1[0]*Gx1[1] + E1[1]*Gx1[5] + E1[2]*Gx1[9] + E1[3]*Gx1[13];\nH101[2] += + E1[0]*Gx1[2] + E1[1]*Gx1[6] + E1[2]*Gx1[10] + E1[3]*Gx1[14];\nH101[3] += + E1[0]*Gx1[3] + E1[1]*Gx1[7] + E1[2]*Gx1[11] + E1[3]*Gx1[15];\n}\n\nvoid acado_zeroBlockH10( real_t* const H101 )\n{\n{ int lCopy; for (lCopy = 0; lCopy < 4; lCopy++) H101[ lCopy ] = 0; }\n}\n\nvoid acado_multEDu( real_t* const E1, real_t* const U1, real_t* const dNew )\n{\ndNew[0] += + E1[0]*U1[0];\ndNew[1] += + E1[1]*U1[0];\ndNew[2] += + E1[2]*U1[0];\ndNew[3] += + E1[3]*U1[0];\n}\n\nvoid acado_zeroBlockH00(  )\n{\nacadoWorkspace.H[0] = 0.0000000000000000e+00;\nacadoWorkspace.H[1] = 0.0000000000000000e+00;\nacadoWorkspace.H[2] = 0.0000000000000000e+00;\nacadoWorkspace.H[3] = 0.0000000000000000e+00;\nacadoWorkspace.H[20] = 0.0000000000000000e+00;\nacadoWorkspace.H[21] = 0.0000000000000000e+00;\nacadoWorkspace.H[22] = 0.0000000000000000e+00;\nacadoWorkspace.H[23] = 0.0000000000000000e+00;\nacadoWorkspace.H[40] = 0.0000000000000000e+00;\nacadoWorkspace.H[41] = 0.0000000000000000e+00;\nacadoWorkspace.H[42] = 0.0000000000000000e+00;\nacadoWorkspace.H[43] = 0.0000000000000000e+00;\nacadoWorkspace.H[60] = 0.0000000000000000e+00;\nacadoWorkspace.H[61] = 0.0000000000000000e+00;\nacadoWorkspace.H[62] = 0.0000000000000000e+00;\nacadoWorkspace.H[63] = 0.0000000000000000e+00;\n}\n\nvoid acado_multCTQC( real_t* const Gx1, real_t* const Gx2 )\n{\nacadoWorkspace.H[0] += + Gx1[0]*Gx2[0] + Gx1[4]*Gx2[4] + Gx1[8]*Gx2[8] + Gx1[12]*Gx2[12];\nacadoWorkspace.H[1] += + Gx1[0]*Gx2[1] + Gx1[4]*Gx2[5] + Gx1[8]*Gx2[9] + Gx1[12]*Gx2[13];\nacadoWorkspace.H[2] += + Gx1[0]*Gx2[2] + Gx1[4]*Gx2[6] + Gx1[8]*Gx2[10] + Gx1[12]*Gx2[14];\nacadoWorkspace.H[3] += + Gx1[0]*Gx2[3] + Gx1[4]*Gx2[7] + Gx1[8]*Gx2[11] + Gx1[12]*Gx2[15];\nacadoWorkspace.H[20] += + Gx1[1]*Gx2[0] + Gx1[5]*Gx2[4] + Gx1[9]*Gx2[8] + Gx1[13]*Gx2[12];\nacadoWorkspace.H[21] += + Gx1[1]*Gx2[1] + Gx1[5]*Gx2[5] + Gx1[9]*Gx2[9] + Gx1[13]*Gx2[13];\nacadoWorkspace.H[22] += + Gx1[1]*Gx2[2] + Gx1[5]*Gx2[6] + Gx1[9]*Gx2[10] + Gx1[13]*Gx2[14];\nacadoWorkspace.H[23] += + Gx1[1]*Gx2[3] + Gx1[5]*Gx2[7] + Gx1[9]*Gx2[11] + Gx1[13]*Gx2[15];\nacadoWorkspace.H[40] += + Gx1[2]*Gx2[0] + Gx1[6]*Gx2[4] + Gx1[10]*Gx2[8] + Gx1[14]*Gx2[12];\nacadoWorkspace.H[41] += + Gx1[2]*Gx2[1] + Gx1[6]*Gx2[5] + Gx1[10]*Gx2[9] + Gx1[14]*Gx2[13];\nacadoWorkspace.H[42] += + Gx1[2]*Gx2[2] + Gx1[6]*Gx2[6] + Gx1[10]*Gx2[10] + Gx1[14]*Gx2[14];\nacadoWorkspace.H[43] += + Gx1[2]*Gx2[3] + Gx1[6]*Gx2[7] + Gx1[10]*Gx2[11] + Gx1[14]*Gx2[15];\nacadoWorkspace.H[60] += + Gx1[3]*Gx2[0] + Gx1[7]*Gx2[4] + Gx1[11]*Gx2[8] + Gx1[15]*Gx2[12];\nacadoWorkspace.H[61] += + Gx1[3]*Gx2[1] + Gx1[7]*Gx2[5] + Gx1[11]*Gx2[9] + Gx1[15]*Gx2[13];\nacadoWorkspace.H[62] += + Gx1[3]*Gx2[2] + Gx1[7]*Gx2[6] + Gx1[11]*Gx2[10] + Gx1[15]*Gx2[14];\nacadoWorkspace.H[63] += + Gx1[3]*Gx2[3] + Gx1[7]*Gx2[7] + Gx1[11]*Gx2[11] + Gx1[15]*Gx2[15];\n}\n\nvoid acado_macCTSlx( real_t* const C0, real_t* const g0 )\n{\ng0[0] += 0.0;\n;\ng0[1] += 0.0;\n;\ng0[2] += 0.0;\n;\ng0[3] += 0.0;\n;\n}\n\nvoid acado_macETSlu( real_t* const E0, real_t* const g1 )\n{\ng1[0] += 0.0;\n;\n}\n\nvoid acado_condensePrep(  )\n{\nint lRun1;\nint lRun2;\nint lRun3;\nint lRun4;\nint lRun5;\n/** Row vector of size: 32 */\nstatic const int xBoundIndices[ 32 ] = \n{ 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, 39, 42, 43, 46, 47, 50, 51, 54, 55, 58, 59, 62, 63, 66, 67 };\nacado_moveGuE( acadoWorkspace.evGu, acadoWorkspace.E );\nacado_moveGxT( &(acadoWorkspace.evGx[ 16 ]), acadoWorkspace.T );\nacado_multGxd( acadoWorkspace.d, &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.d[ 4 ]) );\nacado_multGxGx( acadoWorkspace.T, acadoWorkspace.evGx, &(acadoWorkspace.evGx[ 16 ]) );\n\nacado_multGxGu( acadoWorkspace.T, acadoWorkspace.E, &(acadoWorkspace.E[ 4 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 4 ]), &(acadoWorkspace.E[ 8 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 32 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 4 ]), &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.d[ 8 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.evGx[ 32 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 4 ]), &(acadoWorkspace.E[ 12 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 8 ]), &(acadoWorkspace.E[ 16 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 8 ]), &(acadoWorkspace.E[ 20 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 48 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 8 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.d[ 12 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.evGx[ 48 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.E[ 24 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 16 ]), &(acadoWorkspace.E[ 28 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 20 ]), &(acadoWorkspace.E[ 32 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 12 ]), &(acadoWorkspace.E[ 36 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 64 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 12 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.d[ 16 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.evGx[ 64 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.E[ 40 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.E[ 44 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 32 ]), &(acadoWorkspace.E[ 48 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.E[ 52 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 16 ]), &(acadoWorkspace.E[ 56 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 80 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 16 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.d[ 20 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.evGx[ 80 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.E[ 60 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.E[ 64 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.E[ 68 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 52 ]), &(acadoWorkspace.E[ 72 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 56 ]), &(acadoWorkspace.E[ 76 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 20 ]), &(acadoWorkspace.E[ 80 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 96 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 20 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.d[ 24 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.evGx[ 96 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.E[ 84 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.E[ 88 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.E[ 92 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.E[ 96 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 76 ]), &(acadoWorkspace.E[ 100 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 80 ]), &(acadoWorkspace.E[ 104 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 24 ]), &(acadoWorkspace.E[ 108 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 112 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 24 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.d[ 28 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.evGx[ 112 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.E[ 112 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.E[ 116 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.E[ 120 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.E[ 124 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.E[ 128 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 104 ]), &(acadoWorkspace.E[ 132 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.E[ 136 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 28 ]), &(acadoWorkspace.E[ 140 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 128 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 28 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.d[ 32 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.evGx[ 128 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.E[ 144 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.E[ 148 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.E[ 152 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.E[ 156 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.E[ 160 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.E[ 164 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 136 ]), &(acadoWorkspace.E[ 168 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 140 ]), &(acadoWorkspace.E[ 172 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 32 ]), &(acadoWorkspace.E[ 176 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 32 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.d[ 36 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.evGx[ 144 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.E[ 180 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.E[ 184 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.E[ 188 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.E[ 192 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.E[ 196 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.E[ 200 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.E[ 204 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 172 ]), &(acadoWorkspace.E[ 208 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 176 ]), &(acadoWorkspace.E[ 212 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 36 ]), &(acadoWorkspace.E[ 216 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 160 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 36 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.d[ 40 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.evGx[ 160 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.E[ 220 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.E[ 224 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.E[ 228 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.E[ 232 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.E[ 236 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.E[ 240 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.E[ 244 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.E[ 248 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 212 ]), &(acadoWorkspace.E[ 252 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.E[ 256 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 40 ]), &(acadoWorkspace.E[ 260 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 176 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 40 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.d[ 44 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.evGx[ 176 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.E[ 264 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.E[ 268 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.E[ 272 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.E[ 276 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.E[ 280 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.E[ 284 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.E[ 288 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.E[ 292 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.E[ 296 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 256 ]), &(acadoWorkspace.E[ 300 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 260 ]), &(acadoWorkspace.E[ 304 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 44 ]), &(acadoWorkspace.E[ 308 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 192 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 44 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.d[ 48 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.evGx[ 192 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.E[ 312 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.E[ 316 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.E[ 320 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.E[ 324 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.E[ 328 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.E[ 332 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.E[ 336 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.E[ 340 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.E[ 344 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.E[ 348 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 304 ]), &(acadoWorkspace.E[ 352 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 308 ]), &(acadoWorkspace.E[ 356 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 48 ]), &(acadoWorkspace.E[ 360 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 208 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 48 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.d[ 52 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.evGx[ 208 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.E[ 364 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.E[ 368 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.E[ 372 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.E[ 376 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.E[ 380 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.E[ 384 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.E[ 388 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.E[ 392 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.E[ 396 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.E[ 400 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.E[ 404 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 356 ]), &(acadoWorkspace.E[ 408 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.E[ 412 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 52 ]), &(acadoWorkspace.E[ 416 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 224 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 52 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.d[ 56 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.evGx[ 224 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.E[ 420 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.E[ 424 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.E[ 428 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.E[ 432 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.E[ 436 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.E[ 440 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.E[ 444 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.E[ 448 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.E[ 452 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.E[ 456 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.E[ 460 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.E[ 464 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 412 ]), &(acadoWorkspace.E[ 468 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 416 ]), &(acadoWorkspace.E[ 472 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 56 ]), &(acadoWorkspace.E[ 476 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 240 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 56 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.d[ 60 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.evGx[ 240 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.E[ 480 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.E[ 484 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.E[ 488 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.E[ 492 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.E[ 496 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.E[ 500 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.E[ 504 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.E[ 508 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.E[ 512 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.E[ 516 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.E[ 520 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.E[ 524 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.E[ 528 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 472 ]), &(acadoWorkspace.E[ 532 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 476 ]), &(acadoWorkspace.E[ 536 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 60 ]), &(acadoWorkspace.E[ 540 ]) );\n\nacado_multGxGx( &(acadoWorkspace.Q1[ 16 ]), acadoWorkspace.evGx, acadoWorkspace.QGx );\nacado_multGxGx( &(acadoWorkspace.Q1[ 32 ]), &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.QGx[ 16 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.QGx[ 32 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.QGx[ 48 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.QGx[ 64 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.QGx[ 80 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.QGx[ 96 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.QGx[ 112 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.QGx[ 128 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.QGx[ 144 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.QGx[ 160 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.QGx[ 176 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.QGx[ 192 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.QGx[ 208 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.QGx[ 224 ]) );\nacado_multGxGx( acadoWorkspace.QN1, &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.QGx[ 240 ]) );\n\nacado_multGxGu( &(acadoWorkspace.Q1[ 16 ]), acadoWorkspace.E, acadoWorkspace.QE );\nacado_multGxGu( &(acadoWorkspace.Q1[ 32 ]), &(acadoWorkspace.E[ 4 ]), &(acadoWorkspace.QE[ 4 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 32 ]), &(acadoWorkspace.E[ 8 ]), &(acadoWorkspace.QE[ 8 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 12 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.E[ 16 ]), &(acadoWorkspace.QE[ 16 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.E[ 20 ]), &(acadoWorkspace.QE[ 20 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 24 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.QE[ 28 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.E[ 32 ]), &(acadoWorkspace.QE[ 32 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QE[ 40 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.QE[ 44 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.E[ 52 ]), &(acadoWorkspace.QE[ 52 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.E[ 56 ]), &(acadoWorkspace.QE[ 56 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QE[ 64 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.QE[ 68 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.E[ 76 ]), &(acadoWorkspace.QE[ 76 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.E[ 80 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 84 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 88 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QE[ 92 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.QE[ 100 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 104 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 112 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 116 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QE[ 124 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.QE[ 128 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 136 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.E[ 140 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 148 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 152 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QE[ 160 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 172 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 176 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 184 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 188 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 196 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 212 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 220 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 224 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 232 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 236 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 256 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.E[ 260 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 268 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 272 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 280 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 304 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.E[ 308 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 316 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 320 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 328 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 356 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 364 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 368 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 376 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 380 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 412 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.E[ 416 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 424 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 428 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 436 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 472 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.E[ 476 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 484 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 488 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 496 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 500 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 508 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 512 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 516 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 520 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QE[ 524 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 532 ]), &(acadoWorkspace.QE[ 532 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 536 ]), &(acadoWorkspace.QE[ 536 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_zeroBlockH00(  );\nacado_multCTQC( acadoWorkspace.evGx, acadoWorkspace.QGx );\nacado_multCTQC( &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.QGx[ 16 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.QGx[ 32 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.QGx[ 48 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.QGx[ 64 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.QGx[ 80 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.QGx[ 96 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.QGx[ 112 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.QGx[ 128 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.QGx[ 144 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.QGx[ 160 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.QGx[ 176 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.QGx[ 192 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.QGx[ 208 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.QGx[ 224 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.QGx[ 240 ]) );\n\nacado_zeroBlockH10( acadoWorkspace.H10 );\nacado_multQETGx( acadoWorkspace.QE, acadoWorkspace.evGx, acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 4 ]), &(acadoWorkspace.evGx[ 16 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 12 ]), &(acadoWorkspace.evGx[ 32 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 24 ]), &(acadoWorkspace.evGx[ 48 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 40 ]), &(acadoWorkspace.evGx[ 64 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 60 ]), &(acadoWorkspace.evGx[ 80 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 84 ]), &(acadoWorkspace.evGx[ 96 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 112 ]), &(acadoWorkspace.evGx[ 112 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 144 ]), &(acadoWorkspace.evGx[ 128 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 180 ]), &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 220 ]), &(acadoWorkspace.evGx[ 160 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 264 ]), &(acadoWorkspace.evGx[ 176 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 312 ]), &(acadoWorkspace.evGx[ 192 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 364 ]), &(acadoWorkspace.evGx[ 208 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 420 ]), &(acadoWorkspace.evGx[ 224 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 480 ]), &(acadoWorkspace.evGx[ 240 ]), acadoWorkspace.H10 );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 8 ]), &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 16 ]), &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 28 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 44 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 64 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 88 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 116 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 148 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 184 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 224 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 268 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 316 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 368 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 424 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 484 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 4 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 20 ]), &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 32 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 48 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 68 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 92 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 120 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 152 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 188 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 228 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 272 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 320 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 372 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 428 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 488 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 8 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 36 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 52 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 72 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 96 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 124 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 156 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 192 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 232 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 276 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 324 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 376 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 432 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 492 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 56 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 76 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 100 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 128 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 160 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 196 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 236 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 280 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 328 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 380 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 436 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 496 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 16 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 80 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 104 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 132 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 164 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 200 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 240 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 284 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 332 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 384 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 440 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 500 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 20 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 108 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 136 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 168 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 204 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 244 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 288 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 336 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 388 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 444 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 504 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 140 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 172 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 208 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 248 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 292 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 340 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 392 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 448 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 508 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 28 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 176 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 212 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 252 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 296 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 344 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 396 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 452 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 512 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 32 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 216 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 256 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 300 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 348 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 400 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 456 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 516 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 40 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 260 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.H10[ 40 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 304 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 40 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 352 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 40 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 404 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 40 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 460 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 40 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 520 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 40 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 44 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 308 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.H10[ 44 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 356 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 44 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 408 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 44 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 464 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 44 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 524 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 44 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 360 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 412 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 468 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 528 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 52 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 416 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.H10[ 52 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 472 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 52 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 532 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 52 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 56 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 476 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.H10[ 56 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 536 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 56 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 60 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 540 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.H10[ 60 ]) );\n\nacadoWorkspace.H[4] = acadoWorkspace.H10[0];\nacadoWorkspace.H[5] = acadoWorkspace.H10[4];\nacadoWorkspace.H[6] = acadoWorkspace.H10[8];\nacadoWorkspace.H[7] = acadoWorkspace.H10[12];\nacadoWorkspace.H[8] = acadoWorkspace.H10[16];\nacadoWorkspace.H[9] = acadoWorkspace.H10[20];\nacadoWorkspace.H[10] = acadoWorkspace.H10[24];\nacadoWorkspace.H[11] = acadoWorkspace.H10[28];\nacadoWorkspace.H[12] = acadoWorkspace.H10[32];\nacadoWorkspace.H[13] = acadoWorkspace.H10[36];\nacadoWorkspace.H[14] = acadoWorkspace.H10[40];\nacadoWorkspace.H[15] = acadoWorkspace.H10[44];\nacadoWorkspace.H[16] = acadoWorkspace.H10[48];\nacadoWorkspace.H[17] = acadoWorkspace.H10[52];\nacadoWorkspace.H[18] = acadoWorkspace.H10[56];\nacadoWorkspace.H[19] = acadoWorkspace.H10[60];\nacadoWorkspace.H[24] = acadoWorkspace.H10[1];\nacadoWorkspace.H[25] = acadoWorkspace.H10[5];\nacadoWorkspace.H[26] = acadoWorkspace.H10[9];\nacadoWorkspace.H[27] = acadoWorkspace.H10[13];\nacadoWorkspace.H[28] = acadoWorkspace.H10[17];\nacadoWorkspace.H[29] = acadoWorkspace.H10[21];\nacadoWorkspace.H[30] = acadoWorkspace.H10[25];\nacadoWorkspace.H[31] = acadoWorkspace.H10[29];\nacadoWorkspace.H[32] = acadoWorkspace.H10[33];\nacadoWorkspace.H[33] = acadoWorkspace.H10[37];\nacadoWorkspace.H[34] = acadoWorkspace.H10[41];\nacadoWorkspace.H[35] = acadoWorkspace.H10[45];\nacadoWorkspace.H[36] = acadoWorkspace.H10[49];\nacadoWorkspace.H[37] = acadoWorkspace.H10[53];\nacadoWorkspace.H[38] = acadoWorkspace.H10[57];\nacadoWorkspace.H[39] = acadoWorkspace.H10[61];\nacadoWorkspace.H[44] = acadoWorkspace.H10[2];\nacadoWorkspace.H[45] = acadoWorkspace.H10[6];\nacadoWorkspace.H[46] = acadoWorkspace.H10[10];\nacadoWorkspace.H[47] = acadoWorkspace.H10[14];\nacadoWorkspace.H[48] = acadoWorkspace.H10[18];\nacadoWorkspace.H[49] = acadoWorkspace.H10[22];\nacadoWorkspace.H[50] = acadoWorkspace.H10[26];\nacadoWorkspace.H[51] = acadoWorkspace.H10[30];\nacadoWorkspace.H[52] = acadoWorkspace.H10[34];\nacadoWorkspace.H[53] = acadoWorkspace.H10[38];\nacadoWorkspace.H[54] = acadoWorkspace.H10[42];\nacadoWorkspace.H[55] = acadoWorkspace.H10[46];\nacadoWorkspace.H[56] = acadoWorkspace.H10[50];\nacadoWorkspace.H[57] = acadoWorkspace.H10[54];\nacadoWorkspace.H[58] = acadoWorkspace.H10[58];\nacadoWorkspace.H[59] = acadoWorkspace.H10[62];\nacadoWorkspace.H[64] = acadoWorkspace.H10[3];\nacadoWorkspace.H[65] = acadoWorkspace.H10[7];\nacadoWorkspace.H[66] = acadoWorkspace.H10[11];\nacadoWorkspace.H[67] = acadoWorkspace.H10[15];\nacadoWorkspace.H[68] = acadoWorkspace.H10[19];\nacadoWorkspace.H[69] = acadoWorkspace.H10[23];\nacadoWorkspace.H[70] = acadoWorkspace.H10[27];\nacadoWorkspace.H[71] = acadoWorkspace.H10[31];\nacadoWorkspace.H[72] = acadoWorkspace.H10[35];\nacadoWorkspace.H[73] = acadoWorkspace.H10[39];\nacadoWorkspace.H[74] = acadoWorkspace.H10[43];\nacadoWorkspace.H[75] = acadoWorkspace.H10[47];\nacadoWorkspace.H[76] = acadoWorkspace.H10[51];\nacadoWorkspace.H[77] = acadoWorkspace.H10[55];\nacadoWorkspace.H[78] = acadoWorkspace.H10[59];\nacadoWorkspace.H[79] = acadoWorkspace.H10[63];\n\nacado_setBlockH11_R1( 0, 0, acadoWorkspace.R1 );\nacado_setBlockH11( 0, 0, acadoWorkspace.E, acadoWorkspace.QE );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 4 ]), &(acadoWorkspace.QE[ 4 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 12 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 24 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QE[ 40 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 84 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 112 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 220 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 364 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 480 ]) );\n\nacado_zeroBlockH11( 0, 1 );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 4 ]), &(acadoWorkspace.QE[ 8 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 16 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 28 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QE[ 44 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 64 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 88 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 116 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 148 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 184 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 224 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 268 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 316 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 368 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 424 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 484 ]) );\n\nacado_zeroBlockH11( 0, 2 );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 20 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 32 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 68 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 92 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 152 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 188 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 272 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 320 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 428 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 488 ]) );\n\nacado_zeroBlockH11( 0, 3 );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QE[ 52 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 124 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 232 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 376 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 492 ]) );\n\nacado_zeroBlockH11( 0, 4 );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QE[ 56 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 76 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 100 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 128 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 160 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 196 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 236 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 280 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 328 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 380 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 436 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 496 ]) );\n\nacado_zeroBlockH11( 0, 5 );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 500 ]) );\n\nacado_zeroBlockH11( 0, 6 );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 0, 7 );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 0, 8 );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 0, 9 );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 0, 10 );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 0, 11 );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 0, 12 );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 0, 13 );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 0, 14 );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 0, 15 );\nacado_setBlockH11( 0, 15, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 1, 1, &(acadoWorkspace.R1[ 1 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 8 ]), &(acadoWorkspace.QE[ 8 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 16 ]), &(acadoWorkspace.QE[ 16 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.QE[ 28 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.QE[ 44 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QE[ 64 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 88 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 116 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 148 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 184 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 224 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 268 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 316 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 368 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 424 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 484 ]) );\n\nacado_zeroBlockH11( 1, 2 );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 16 ]), &(acadoWorkspace.QE[ 20 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.QE[ 32 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QE[ 68 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 92 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 152 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 188 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 272 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 320 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 428 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 488 ]) );\n\nacado_zeroBlockH11( 1, 3 );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.QE[ 52 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 124 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 232 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 376 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 492 ]) );\n\nacado_zeroBlockH11( 1, 4 );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.QE[ 56 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QE[ 76 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 100 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 128 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 160 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 196 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 236 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 280 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 328 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 380 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 436 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 496 ]) );\n\nacado_zeroBlockH11( 1, 5 );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 500 ]) );\n\nacado_zeroBlockH11( 1, 6 );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 1, 7 );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 1, 8 );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 1, 9 );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 1, 10 );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 1, 11 );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 1, 12 );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 1, 13 );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 1, 14 );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 1, 15 );\nacado_setBlockH11( 1, 15, &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 2, 2, &(acadoWorkspace.R1[ 2 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 20 ]), &(acadoWorkspace.QE[ 20 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 32 ]), &(acadoWorkspace.QE[ 32 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.QE[ 68 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QE[ 92 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 152 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 188 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 272 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 320 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 428 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 488 ]) );\n\nacado_zeroBlockH11( 2, 3 );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 32 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 52 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 124 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 232 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 376 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 492 ]) );\n\nacado_zeroBlockH11( 2, 4 );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 56 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.QE[ 76 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QE[ 100 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 128 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 160 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 196 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 236 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 280 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 328 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 380 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 436 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 496 ]) );\n\nacado_zeroBlockH11( 2, 5 );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 500 ]) );\n\nacado_zeroBlockH11( 2, 6 );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 2, 7 );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 2, 8 );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 2, 9 );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 2, 10 );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 2, 11 );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 2, 12 );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 2, 13 );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 2, 14 );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 2, 15 );\nacado_setBlockH11( 2, 15, &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 3, 3, &(acadoWorkspace.R1[ 3 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 52 ]), &(acadoWorkspace.QE[ 52 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QE[ 124 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 232 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 376 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 492 ]) );\n\nacado_zeroBlockH11( 3, 4 );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 52 ]), &(acadoWorkspace.QE[ 56 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 76 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 100 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QE[ 128 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 160 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 196 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 236 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 280 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 328 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 380 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 436 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 496 ]) );\n\nacado_zeroBlockH11( 3, 5 );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 500 ]) );\n\nacado_zeroBlockH11( 3, 6 );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 3, 7 );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 3, 8 );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 3, 9 );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 3, 10 );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 3, 11 );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 3, 12 );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 3, 13 );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 3, 14 );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 3, 15 );\nacado_setBlockH11( 3, 15, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 4, 4, &(acadoWorkspace.R1[ 4 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 56 ]), &(acadoWorkspace.QE[ 56 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 76 ]), &(acadoWorkspace.QE[ 76 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.QE[ 100 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.QE[ 128 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QE[ 160 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 196 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 236 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 280 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 328 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 380 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 436 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 496 ]) );\n\nacado_zeroBlockH11( 4, 5 );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 76 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 500 ]) );\n\nacado_zeroBlockH11( 4, 6 );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 4, 7 );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 4, 8 );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 4, 9 );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 4, 10 );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 4, 11 );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 4, 12 );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 4, 13 );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 4, 14 );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 4, 15 );\nacado_setBlockH11( 4, 15, &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 5, 5, &(acadoWorkspace.R1[ 5 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 80 ]), &(acadoWorkspace.QE[ 80 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 104 ]), &(acadoWorkspace.QE[ 104 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.QE[ 164 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QE[ 200 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 284 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 332 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 440 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 500 ]) );\n\nacado_zeroBlockH11( 5, 6 );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 104 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 5, 7 );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 5, 8 );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 5, 9 );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 5, 10 );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 5, 11 );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 5, 12 );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 5, 13 );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 5, 14 );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 5, 15 );\nacado_setBlockH11( 5, 15, &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 6, 6, &(acadoWorkspace.R1[ 6 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 136 ]), &(acadoWorkspace.QE[ 136 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QE[ 244 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 388 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 504 ]) );\n\nacado_zeroBlockH11( 6, 7 );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 136 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 6, 8 );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 6, 9 );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 6, 10 );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 6, 11 );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 6, 12 );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 6, 13 );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 6, 14 );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 6, 15 );\nacado_setBlockH11( 6, 15, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 7, 7, &(acadoWorkspace.R1[ 7 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 140 ]), &(acadoWorkspace.QE[ 140 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 172 ]), &(acadoWorkspace.QE[ 172 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.QE[ 208 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.QE[ 248 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QE[ 292 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 340 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 392 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 448 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 508 ]) );\n\nacado_zeroBlockH11( 7, 8 );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 172 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 7, 9 );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 7, 10 );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 7, 11 );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 7, 12 );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 7, 13 );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 7, 14 );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 7, 15 );\nacado_setBlockH11( 7, 15, &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 8, 8, &(acadoWorkspace.R1[ 8 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 176 ]), &(acadoWorkspace.QE[ 176 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 212 ]), &(acadoWorkspace.QE[ 212 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.QE[ 296 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QE[ 344 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 452 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 512 ]) );\n\nacado_zeroBlockH11( 8, 9 );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 212 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 8, 10 );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 8, 11 );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 8, 12 );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 8, 13 );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 8, 14 );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 8, 15 );\nacado_setBlockH11( 8, 15, &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 9, 9, &(acadoWorkspace.R1[ 9 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 256 ]), &(acadoWorkspace.QE[ 256 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QE[ 400 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 516 ]) );\n\nacado_zeroBlockH11( 9, 10 );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 256 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 9, 11 );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 9, 12 );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 9, 13 );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 9, 14 );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 9, 15 );\nacado_setBlockH11( 9, 15, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 10, 10, &(acadoWorkspace.R1[ 10 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 260 ]), &(acadoWorkspace.QE[ 260 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 304 ]), &(acadoWorkspace.QE[ 304 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.QE[ 352 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.QE[ 404 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QE[ 460 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 520 ]) );\n\nacado_zeroBlockH11( 10, 11 );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 304 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 10, 12 );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 10, 13 );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 10, 14 );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 10, 15 );\nacado_setBlockH11( 10, 15, &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 11, 11, &(acadoWorkspace.R1[ 11 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 308 ]), &(acadoWorkspace.QE[ 308 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 356 ]), &(acadoWorkspace.QE[ 356 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.QE[ 464 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QE[ 524 ]) );\n\nacado_zeroBlockH11( 11, 12 );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 356 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 11, 13 );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 11, 14 );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 11, 15 );\nacado_setBlockH11( 11, 15, &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 12, 12, &(acadoWorkspace.R1[ 12 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 412 ]), &(acadoWorkspace.QE[ 412 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 528 ]) );\n\nacado_zeroBlockH11( 12, 13 );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 412 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 12, 14 );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 12, 15 );\nacado_setBlockH11( 12, 15, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 13, 13, &(acadoWorkspace.R1[ 13 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 416 ]), &(acadoWorkspace.QE[ 416 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 472 ]), &(acadoWorkspace.QE[ 472 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 532 ]), &(acadoWorkspace.QE[ 532 ]) );\n\nacado_zeroBlockH11( 13, 14 );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 472 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 532 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 13, 15 );\nacado_setBlockH11( 13, 15, &(acadoWorkspace.E[ 532 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 14, 14, &(acadoWorkspace.R1[ 14 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 476 ]), &(acadoWorkspace.QE[ 476 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 536 ]), &(acadoWorkspace.QE[ 536 ]) );\n\nacado_zeroBlockH11( 14, 15 );\nacado_setBlockH11( 14, 15, &(acadoWorkspace.E[ 536 ]), &(acadoWorkspace.QE[ 540 ]) );\n\nacado_setBlockH11_R1( 15, 15, &(acadoWorkspace.R1[ 15 ]) );\nacado_setBlockH11( 15, 15, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 540 ]) );\n\n\nacado_copyHTH( 1, 0 );\nacado_copyHTH( 2, 0 );\nacado_copyHTH( 2, 1 );\nacado_copyHTH( 3, 0 );\nacado_copyHTH( 3, 1 );\nacado_copyHTH( 3, 2 );\nacado_copyHTH( 4, 0 );\nacado_copyHTH( 4, 1 );\nacado_copyHTH( 4, 2 );\nacado_copyHTH( 4, 3 );\nacado_copyHTH( 5, 0 );\nacado_copyHTH( 5, 1 );\nacado_copyHTH( 5, 2 );\nacado_copyHTH( 5, 3 );\nacado_copyHTH( 5, 4 );\nacado_copyHTH( 6, 0 );\nacado_copyHTH( 6, 1 );\nacado_copyHTH( 6, 2 );\nacado_copyHTH( 6, 3 );\nacado_copyHTH( 6, 4 );\nacado_copyHTH( 6, 5 );\nacado_copyHTH( 7, 0 );\nacado_copyHTH( 7, 1 );\nacado_copyHTH( 7, 2 );\nacado_copyHTH( 7, 3 );\nacado_copyHTH( 7, 4 );\nacado_copyHTH( 7, 5 );\nacado_copyHTH( 7, 6 );\nacado_copyHTH( 8, 0 );\nacado_copyHTH( 8, 1 );\nacado_copyHTH( 8, 2 );\nacado_copyHTH( 8, 3 );\nacado_copyHTH( 8, 4 );\nacado_copyHTH( 8, 5 );\nacado_copyHTH( 8, 6 );\nacado_copyHTH( 8, 7 );\nacado_copyHTH( 9, 0 );\nacado_copyHTH( 9, 1 );\nacado_copyHTH( 9, 2 );\nacado_copyHTH( 9, 3 );\nacado_copyHTH( 9, 4 );\nacado_copyHTH( 9, 5 );\nacado_copyHTH( 9, 6 );\nacado_copyHTH( 9, 7 );\nacado_copyHTH( 9, 8 );\nacado_copyHTH( 10, 0 );\nacado_copyHTH( 10, 1 );\nacado_copyHTH( 10, 2 );\nacado_copyHTH( 10, 3 );\nacado_copyHTH( 10, 4 );\nacado_copyHTH( 10, 5 );\nacado_copyHTH( 10, 6 );\nacado_copyHTH( 10, 7 );\nacado_copyHTH( 10, 8 );\nacado_copyHTH( 10, 9 );\nacado_copyHTH( 11, 0 );\nacado_copyHTH( 11, 1 );\nacado_copyHTH( 11, 2 );\nacado_copyHTH( 11, 3 );\nacado_copyHTH( 11, 4 );\nacado_copyHTH( 11, 5 );\nacado_copyHTH( 11, 6 );\nacado_copyHTH( 11, 7 );\nacado_copyHTH( 11, 8 );\nacado_copyHTH( 11, 9 );\nacado_copyHTH( 11, 10 );\nacado_copyHTH( 12, 0 );\nacado_copyHTH( 12, 1 );\nacado_copyHTH( 12, 2 );\nacado_copyHTH( 12, 3 );\nacado_copyHTH( 12, 4 );\nacado_copyHTH( 12, 5 );\nacado_copyHTH( 12, 6 );\nacado_copyHTH( 12, 7 );\nacado_copyHTH( 12, 8 );\nacado_copyHTH( 12, 9 );\nacado_copyHTH( 12, 10 );\nacado_copyHTH( 12, 11 );\nacado_copyHTH( 13, 0 );\nacado_copyHTH( 13, 1 );\nacado_copyHTH( 13, 2 );\nacado_copyHTH( 13, 3 );\nacado_copyHTH( 13, 4 );\nacado_copyHTH( 13, 5 );\nacado_copyHTH( 13, 6 );\nacado_copyHTH( 13, 7 );\nacado_copyHTH( 13, 8 );\nacado_copyHTH( 13, 9 );\nacado_copyHTH( 13, 10 );\nacado_copyHTH( 13, 11 );\nacado_copyHTH( 13, 12 );\nacado_copyHTH( 14, 0 );\nacado_copyHTH( 14, 1 );\nacado_copyHTH( 14, 2 );\nacado_copyHTH( 14, 3 );\nacado_copyHTH( 14, 4 );\nacado_copyHTH( 14, 5 );\nacado_copyHTH( 14, 6 );\nacado_copyHTH( 14, 7 );\nacado_copyHTH( 14, 8 );\nacado_copyHTH( 14, 9 );\nacado_copyHTH( 14, 10 );\nacado_copyHTH( 14, 11 );\nacado_copyHTH( 14, 12 );\nacado_copyHTH( 14, 13 );\nacado_copyHTH( 15, 0 );\nacado_copyHTH( 15, 1 );\nacado_copyHTH( 15, 2 );\nacado_copyHTH( 15, 3 );\nacado_copyHTH( 15, 4 );\nacado_copyHTH( 15, 5 );\nacado_copyHTH( 15, 6 );\nacado_copyHTH( 15, 7 );\nacado_copyHTH( 15, 8 );\nacado_copyHTH( 15, 9 );\nacado_copyHTH( 15, 10 );\nacado_copyHTH( 15, 11 );\nacado_copyHTH( 15, 12 );\nacado_copyHTH( 15, 13 );\nacado_copyHTH( 15, 14 );\n\nacadoWorkspace.H[80] = acadoWorkspace.H10[0];\nacadoWorkspace.H[81] = acadoWorkspace.H10[1];\nacadoWorkspace.H[82] = acadoWorkspace.H10[2];\nacadoWorkspace.H[83] = acadoWorkspace.H10[3];\nacadoWorkspace.H[100] = acadoWorkspace.H10[4];\nacadoWorkspace.H[101] = acadoWorkspace.H10[5];\nacadoWorkspace.H[102] = acadoWorkspace.H10[6];\nacadoWorkspace.H[103] = acadoWorkspace.H10[7];\nacadoWorkspace.H[120] = acadoWorkspace.H10[8];\nacadoWorkspace.H[121] = acadoWorkspace.H10[9];\nacadoWorkspace.H[122] = acadoWorkspace.H10[10];\nacadoWorkspace.H[123] = acadoWorkspace.H10[11];\nacadoWorkspace.H[140] = acadoWorkspace.H10[12];\nacadoWorkspace.H[141] = acadoWorkspace.H10[13];\nacadoWorkspace.H[142] = acadoWorkspace.H10[14];\nacadoWorkspace.H[143] = acadoWorkspace.H10[15];\nacadoWorkspace.H[160] = acadoWorkspace.H10[16];\nacadoWorkspace.H[161] = acadoWorkspace.H10[17];\nacadoWorkspace.H[162] = acadoWorkspace.H10[18];\nacadoWorkspace.H[163] = acadoWorkspace.H10[19];\nacadoWorkspace.H[180] = acadoWorkspace.H10[20];\nacadoWorkspace.H[181] = acadoWorkspace.H10[21];\nacadoWorkspace.H[182] = acadoWorkspace.H10[22];\nacadoWorkspace.H[183] = acadoWorkspace.H10[23];\nacadoWorkspace.H[200] = acadoWorkspace.H10[24];\nacadoWorkspace.H[201] = acadoWorkspace.H10[25];\nacadoWorkspace.H[202] = acadoWorkspace.H10[26];\nacadoWorkspace.H[203] = acadoWorkspace.H10[27];\nacadoWorkspace.H[220] = acadoWorkspace.H10[28];\nacadoWorkspace.H[221] = acadoWorkspace.H10[29];\nacadoWorkspace.H[222] = acadoWorkspace.H10[30];\nacadoWorkspace.H[223] = acadoWorkspace.H10[31];\nacadoWorkspace.H[240] = acadoWorkspace.H10[32];\nacadoWorkspace.H[241] = acadoWorkspace.H10[33];\nacadoWorkspace.H[242] = acadoWorkspace.H10[34];\nacadoWorkspace.H[243] = acadoWorkspace.H10[35];\nacadoWorkspace.H[260] = acadoWorkspace.H10[36];\nacadoWorkspace.H[261] = acadoWorkspace.H10[37];\nacadoWorkspace.H[262] = acadoWorkspace.H10[38];\nacadoWorkspace.H[263] = acadoWorkspace.H10[39];\nacadoWorkspace.H[280] = acadoWorkspace.H10[40];\nacadoWorkspace.H[281] = acadoWorkspace.H10[41];\nacadoWorkspace.H[282] = acadoWorkspace.H10[42];\nacadoWorkspace.H[283] = acadoWorkspace.H10[43];\nacadoWorkspace.H[300] = acadoWorkspace.H10[44];\nacadoWorkspace.H[301] = acadoWorkspace.H10[45];\nacadoWorkspace.H[302] = acadoWorkspace.H10[46];\nacadoWorkspace.H[303] = acadoWorkspace.H10[47];\nacadoWorkspace.H[320] = acadoWorkspace.H10[48];\nacadoWorkspace.H[321] = acadoWorkspace.H10[49];\nacadoWorkspace.H[322] = acadoWorkspace.H10[50];\nacadoWorkspace.H[323] = acadoWorkspace.H10[51];\nacadoWorkspace.H[340] = acadoWorkspace.H10[52];\nacadoWorkspace.H[341] = acadoWorkspace.H10[53];\nacadoWorkspace.H[342] = acadoWorkspace.H10[54];\nacadoWorkspace.H[343] = acadoWorkspace.H10[55];\nacadoWorkspace.H[360] = acadoWorkspace.H10[56];\nacadoWorkspace.H[361] = acadoWorkspace.H10[57];\nacadoWorkspace.H[362] = acadoWorkspace.H10[58];\nacadoWorkspace.H[363] = acadoWorkspace.H10[59];\nacadoWorkspace.H[380] = acadoWorkspace.H10[60];\nacadoWorkspace.H[381] = acadoWorkspace.H10[61];\nacadoWorkspace.H[382] = acadoWorkspace.H10[62];\nacadoWorkspace.H[383] = acadoWorkspace.H10[63];\n\nacado_multQ1d( &(acadoWorkspace.Q1[ 16 ]), acadoWorkspace.d, acadoWorkspace.Qd );\nacado_multQ1d( &(acadoWorkspace.Q1[ 32 ]), &(acadoWorkspace.d[ 4 ]), &(acadoWorkspace.Qd[ 4 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.d[ 8 ]), &(acadoWorkspace.Qd[ 8 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.d[ 12 ]), &(acadoWorkspace.Qd[ 12 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.d[ 16 ]), &(acadoWorkspace.Qd[ 16 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.d[ 20 ]), &(acadoWorkspace.Qd[ 20 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.d[ 24 ]), &(acadoWorkspace.Qd[ 24 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.d[ 28 ]), &(acadoWorkspace.Qd[ 28 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.d[ 32 ]), &(acadoWorkspace.Qd[ 32 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.d[ 36 ]), &(acadoWorkspace.Qd[ 36 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.d[ 40 ]), &(acadoWorkspace.Qd[ 40 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.d[ 44 ]), &(acadoWorkspace.Qd[ 44 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.d[ 48 ]), &(acadoWorkspace.Qd[ 48 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.d[ 52 ]), &(acadoWorkspace.Qd[ 52 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.d[ 56 ]), &(acadoWorkspace.Qd[ 56 ]) );\nacado_multQN1d( acadoWorkspace.QN1, &(acadoWorkspace.d[ 60 ]), &(acadoWorkspace.Qd[ 60 ]) );\n\nacado_macCTSlx( acadoWorkspace.evGx, acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 16 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 32 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 48 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 64 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 80 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 96 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 112 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 128 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 160 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 176 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 192 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 208 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 224 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 240 ]), acadoWorkspace.g );\nacado_macETSlu( acadoWorkspace.QE, &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 4 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 12 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 24 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 40 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 60 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 84 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 112 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 144 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 180 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 220 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 264 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 312 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 364 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 420 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 480 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 8 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 16 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 28 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 44 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 64 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 88 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 116 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 148 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 184 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 224 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 268 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 316 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 368 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 424 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 484 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 20 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 32 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 48 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 68 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 92 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 120 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 152 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 188 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 228 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 272 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 320 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 372 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 428 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 488 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 36 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 52 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 72 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 96 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 124 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 156 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 192 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 232 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 276 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 324 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 376 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 432 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 492 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 56 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 76 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 100 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 128 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 160 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 196 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 236 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 280 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 328 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 380 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 436 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 496 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 80 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 104 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 132 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 164 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 200 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 240 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 284 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 332 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 384 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 440 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 500 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 108 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 136 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 168 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 204 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 244 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 288 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 336 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 388 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 444 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 504 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 140 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 172 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 208 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 248 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 292 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 340 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 392 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 448 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 508 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 176 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 212 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 252 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 296 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 344 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 396 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 452 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 512 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 216 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 256 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 300 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 348 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 400 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 456 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 516 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 260 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 304 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 352 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 404 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 460 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 520 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 308 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 356 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 408 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 464 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 524 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 360 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 412 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 468 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 528 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 416 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 472 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 532 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 476 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 536 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 540 ]), &(acadoWorkspace.g[ 19 ]) );\nacadoWorkspace.lb[4] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[0];\nacadoWorkspace.lb[5] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[1];\nacadoWorkspace.lb[6] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[2];\nacadoWorkspace.lb[7] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[3];\nacadoWorkspace.lb[8] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[4];\nacadoWorkspace.lb[9] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[5];\nacadoWorkspace.lb[10] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[6];\nacadoWorkspace.lb[11] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[7];\nacadoWorkspace.lb[12] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[8];\nacadoWorkspace.lb[13] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[9];\nacadoWorkspace.lb[14] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[10];\nacadoWorkspace.lb[15] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[11];\nacadoWorkspace.lb[16] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[12];\nacadoWorkspace.lb[17] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[13];\nacadoWorkspace.lb[18] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[14];\nacadoWorkspace.lb[19] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[15];\nacadoWorkspace.ub[4] = (real_t)1.0000000000000000e+12 - acadoVariables.u[0];\nacadoWorkspace.ub[5] = (real_t)1.0000000000000000e+12 - acadoVariables.u[1];\nacadoWorkspace.ub[6] = (real_t)1.0000000000000000e+12 - acadoVariables.u[2];\nacadoWorkspace.ub[7] = (real_t)1.0000000000000000e+12 - acadoVariables.u[3];\nacadoWorkspace.ub[8] = (real_t)1.0000000000000000e+12 - acadoVariables.u[4];\nacadoWorkspace.ub[9] = (real_t)1.0000000000000000e+12 - acadoVariables.u[5];\nacadoWorkspace.ub[10] = (real_t)1.0000000000000000e+12 - acadoVariables.u[6];\nacadoWorkspace.ub[11] = (real_t)1.0000000000000000e+12 - acadoVariables.u[7];\nacadoWorkspace.ub[12] = (real_t)1.0000000000000000e+12 - acadoVariables.u[8];\nacadoWorkspace.ub[13] = (real_t)1.0000000000000000e+12 - acadoVariables.u[9];\nacadoWorkspace.ub[14] = (real_t)1.0000000000000000e+12 - acadoVariables.u[10];\nacadoWorkspace.ub[15] = (real_t)1.0000000000000000e+12 - acadoVariables.u[11];\nacadoWorkspace.ub[16] = (real_t)1.0000000000000000e+12 - acadoVariables.u[12];\nacadoWorkspace.ub[17] = (real_t)1.0000000000000000e+12 - acadoVariables.u[13];\nacadoWorkspace.ub[18] = (real_t)1.0000000000000000e+12 - acadoVariables.u[14];\nacadoWorkspace.ub[19] = (real_t)1.0000000000000000e+12 - acadoVariables.u[15];\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nlRun3 = xBoundIndices[ lRun1 ] - 4;\nlRun4 = ((lRun3) / (4)) + (1);\nacadoWorkspace.A[lRun1 * 20] = acadoWorkspace.evGx[lRun3 * 4];\nacadoWorkspace.A[lRun1 * 20 + 1] = acadoWorkspace.evGx[lRun3 * 4 + 1];\nacadoWorkspace.A[lRun1 * 20 + 2] = acadoWorkspace.evGx[lRun3 * 4 + 2];\nacadoWorkspace.A[lRun1 * 20 + 3] = acadoWorkspace.evGx[lRun3 * 4 + 3];\nfor (lRun2 = 0; lRun2 < lRun4; ++lRun2)\n{\nlRun5 = (((((lRun4) * (lRun4-1)) / (2)) + (lRun2)) * (4)) + ((lRun3) % (4));\nacadoWorkspace.A[(lRun1 * 20) + (lRun2 + 4)] = acadoWorkspace.E[lRun5];\n}\n}\n\n}\n\nvoid acado_condenseFdb(  )\n{\nreal_t tmp;\n\nacadoWorkspace.Dx0[0] = acadoVariables.x0[0] - acadoVariables.x[0];\nacadoWorkspace.Dx0[1] = acadoVariables.x0[1] - acadoVariables.x[1];\nacadoWorkspace.Dx0[2] = acadoVariables.x0[2] - acadoVariables.x[2];\nacadoWorkspace.Dx0[3] = acadoVariables.x0[3] - acadoVariables.x[3];\n\nacadoWorkspace.Dy[0] -= acadoVariables.y[0];\nacadoWorkspace.Dy[1] -= acadoVariables.y[1];\nacadoWorkspace.Dy[2] -= acadoVariables.y[2];\nacadoWorkspace.Dy[3] -= acadoVariables.y[3];\nacadoWorkspace.Dy[4] -= acadoVariables.y[4];\nacadoWorkspace.Dy[5] -= acadoVariables.y[5];\nacadoWorkspace.Dy[6] -= acadoVariables.y[6];\nacadoWorkspace.Dy[7] -= acadoVariables.y[7];\nacadoWorkspace.Dy[8] -= acadoVariables.y[8];\nacadoWorkspace.Dy[9] -= acadoVariables.y[9];\nacadoWorkspace.Dy[10] -= acadoVariables.y[10];\nacadoWorkspace.Dy[11] -= acadoVariables.y[11];\nacadoWorkspace.Dy[12] -= acadoVariables.y[12];\nacadoWorkspace.Dy[13] -= acadoVariables.y[13];\nacadoWorkspace.Dy[14] -= acadoVariables.y[14];\nacadoWorkspace.Dy[15] -= acadoVariables.y[15];\nacadoWorkspace.Dy[16] -= acadoVariables.y[16];\nacadoWorkspace.Dy[17] -= acadoVariables.y[17];\nacadoWorkspace.Dy[18] -= acadoVariables.y[18];\nacadoWorkspace.Dy[19] -= acadoVariables.y[19];\nacadoWorkspace.Dy[20] -= acadoVariables.y[20];\nacadoWorkspace.Dy[21] -= acadoVariables.y[21];\nacadoWorkspace.Dy[22] -= acadoVariables.y[22];\nacadoWorkspace.Dy[23] -= acadoVariables.y[23];\nacadoWorkspace.Dy[24] -= acadoVariables.y[24];\nacadoWorkspace.Dy[25] -= acadoVariables.y[25];\nacadoWorkspace.Dy[26] -= acadoVariables.y[26];\nacadoWorkspace.Dy[27] -= acadoVariables.y[27];\nacadoWorkspace.Dy[28] -= acadoVariables.y[28];\nacadoWorkspace.Dy[29] -= acadoVariables.y[29];\nacadoWorkspace.Dy[30] -= acadoVariables.y[30];\nacadoWorkspace.Dy[31] -= acadoVariables.y[31];\nacadoWorkspace.Dy[32] -= acadoVariables.y[32];\nacadoWorkspace.Dy[33] -= acadoVariables.y[33];\nacadoWorkspace.Dy[34] -= acadoVariables.y[34];\nacadoWorkspace.Dy[35] -= acadoVariables.y[35];\nacadoWorkspace.Dy[36] -= acadoVariables.y[36];\nacadoWorkspace.Dy[37] -= acadoVariables.y[37];\nacadoWorkspace.Dy[38] -= acadoVariables.y[38];\nacadoWorkspace.Dy[39] -= acadoVariables.y[39];\nacadoWorkspace.Dy[40] -= acadoVariables.y[40];\nacadoWorkspace.Dy[41] -= acadoVariables.y[41];\nacadoWorkspace.Dy[42] -= acadoVariables.y[42];\nacadoWorkspace.Dy[43] -= acadoVariables.y[43];\nacadoWorkspace.Dy[44] -= acadoVariables.y[44];\nacadoWorkspace.Dy[45] -= acadoVariables.y[45];\nacadoWorkspace.Dy[46] -= acadoVariables.y[46];\nacadoWorkspace.Dy[47] -= acadoVariables.y[47];\nacadoWorkspace.DyN[0] -= acadoVariables.yN[0];\nacadoWorkspace.DyN[1] -= acadoVariables.yN[1];\n\nacado_multRDy( acadoWorkspace.R2, acadoWorkspace.Dy, &(acadoWorkspace.g[ 4 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 3 ]), &(acadoWorkspace.Dy[ 3 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 6 ]), &(acadoWorkspace.Dy[ 6 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 9 ]), &(acadoWorkspace.Dy[ 9 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 12 ]), &(acadoWorkspace.Dy[ 12 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 15 ]), &(acadoWorkspace.Dy[ 15 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 18 ]), &(acadoWorkspace.Dy[ 18 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 21 ]), &(acadoWorkspace.Dy[ 21 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 24 ]), &(acadoWorkspace.Dy[ 24 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 27 ]), &(acadoWorkspace.Dy[ 27 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 30 ]), &(acadoWorkspace.Dy[ 30 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 33 ]), &(acadoWorkspace.Dy[ 33 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 36 ]), &(acadoWorkspace.Dy[ 36 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 39 ]), &(acadoWorkspace.Dy[ 39 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 42 ]), &(acadoWorkspace.Dy[ 42 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 45 ]), &(acadoWorkspace.Dy[ 45 ]), &(acadoWorkspace.g[ 19 ]) );\n\nacado_multQDy( acadoWorkspace.Q2, acadoWorkspace.Dy, acadoWorkspace.QDy );\nacado_multQDy( &(acadoWorkspace.Q2[ 12 ]), &(acadoWorkspace.Dy[ 3 ]), &(acadoWorkspace.QDy[ 4 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 24 ]), &(acadoWorkspace.Dy[ 6 ]), &(acadoWorkspace.QDy[ 8 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 36 ]), &(acadoWorkspace.Dy[ 9 ]), &(acadoWorkspace.QDy[ 12 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 48 ]), &(acadoWorkspace.Dy[ 12 ]), &(acadoWorkspace.QDy[ 16 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 60 ]), &(acadoWorkspace.Dy[ 15 ]), &(acadoWorkspace.QDy[ 20 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 72 ]), &(acadoWorkspace.Dy[ 18 ]), &(acadoWorkspace.QDy[ 24 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 84 ]), &(acadoWorkspace.Dy[ 21 ]), &(acadoWorkspace.QDy[ 28 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 96 ]), &(acadoWorkspace.Dy[ 24 ]), &(acadoWorkspace.QDy[ 32 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 108 ]), &(acadoWorkspace.Dy[ 27 ]), &(acadoWorkspace.QDy[ 36 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 120 ]), &(acadoWorkspace.Dy[ 30 ]), &(acadoWorkspace.QDy[ 40 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 132 ]), &(acadoWorkspace.Dy[ 33 ]), &(acadoWorkspace.QDy[ 44 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 144 ]), &(acadoWorkspace.Dy[ 36 ]), &(acadoWorkspace.QDy[ 48 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 156 ]), &(acadoWorkspace.Dy[ 39 ]), &(acadoWorkspace.QDy[ 52 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 168 ]), &(acadoWorkspace.Dy[ 42 ]), &(acadoWorkspace.QDy[ 56 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 180 ]), &(acadoWorkspace.Dy[ 45 ]), &(acadoWorkspace.QDy[ 60 ]) );\n\nacadoWorkspace.QDy[64] = + acadoWorkspace.QN2[0]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[1]*acadoWorkspace.DyN[1];\nacadoWorkspace.QDy[65] = + acadoWorkspace.QN2[2]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[3]*acadoWorkspace.DyN[1];\nacadoWorkspace.QDy[66] = + acadoWorkspace.QN2[4]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[5]*acadoWorkspace.DyN[1];\nacadoWorkspace.QDy[67] = + acadoWorkspace.QN2[6]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[7]*acadoWorkspace.DyN[1];\n\nacadoWorkspace.QDy[4] += acadoWorkspace.Qd[0];\nacadoWorkspace.QDy[5] += acadoWorkspace.Qd[1];\nacadoWorkspace.QDy[6] += acadoWorkspace.Qd[2];\nacadoWorkspace.QDy[7] += acadoWorkspace.Qd[3];\nacadoWorkspace.QDy[8] += acadoWorkspace.Qd[4];\nacadoWorkspace.QDy[9] += acadoWorkspace.Qd[5];\nacadoWorkspace.QDy[10] += acadoWorkspace.Qd[6];\nacadoWorkspace.QDy[11] += acadoWorkspace.Qd[7];\nacadoWorkspace.QDy[12] += acadoWorkspace.Qd[8];\nacadoWorkspace.QDy[13] += acadoWorkspace.Qd[9];\nacadoWorkspace.QDy[14] += acadoWorkspace.Qd[10];\nacadoWorkspace.QDy[15] += acadoWorkspace.Qd[11];\nacadoWorkspace.QDy[16] += acadoWorkspace.Qd[12];\nacadoWorkspace.QDy[17] += acadoWorkspace.Qd[13];\nacadoWorkspace.QDy[18] += acadoWorkspace.Qd[14];\nacadoWorkspace.QDy[19] += acadoWorkspace.Qd[15];\nacadoWorkspace.QDy[20] += acadoWorkspace.Qd[16];\nacadoWorkspace.QDy[21] += acadoWorkspace.Qd[17];\nacadoWorkspace.QDy[22] += acadoWorkspace.Qd[18];\nacadoWorkspace.QDy[23] += acadoWorkspace.Qd[19];\nacadoWorkspace.QDy[24] += acadoWorkspace.Qd[20];\nacadoWorkspace.QDy[25] += acadoWorkspace.Qd[21];\nacadoWorkspace.QDy[26] += acadoWorkspace.Qd[22];\nacadoWorkspace.QDy[27] += acadoWorkspace.Qd[23];\nacadoWorkspace.QDy[28] += acadoWorkspace.Qd[24];\nacadoWorkspace.QDy[29] += acadoWorkspace.Qd[25];\nacadoWorkspace.QDy[30] += acadoWorkspace.Qd[26];\nacadoWorkspace.QDy[31] += acadoWorkspace.Qd[27];\nacadoWorkspace.QDy[32] += acadoWorkspace.Qd[28];\nacadoWorkspace.QDy[33] += acadoWorkspace.Qd[29];\nacadoWorkspace.QDy[34] += acadoWorkspace.Qd[30];\nacadoWorkspace.QDy[35] += acadoWorkspace.Qd[31];\nacadoWorkspace.QDy[36] += acadoWorkspace.Qd[32];\nacadoWorkspace.QDy[37] += acadoWorkspace.Qd[33];\nacadoWorkspace.QDy[38] += acadoWorkspace.Qd[34];\nacadoWorkspace.QDy[39] += acadoWorkspace.Qd[35];\nacadoWorkspace.QDy[40] += acadoWorkspace.Qd[36];\nacadoWorkspace.QDy[41] += acadoWorkspace.Qd[37];\nacadoWorkspace.QDy[42] += acadoWorkspace.Qd[38];\nacadoWorkspace.QDy[43] += acadoWorkspace.Qd[39];\nacadoWorkspace.QDy[44] += acadoWorkspace.Qd[40];\nacadoWorkspace.QDy[45] += acadoWorkspace.Qd[41];\nacadoWorkspace.QDy[46] += acadoWorkspace.Qd[42];\nacadoWorkspace.QDy[47] += acadoWorkspace.Qd[43];\nacadoWorkspace.QDy[48] += acadoWorkspace.Qd[44];\nacadoWorkspace.QDy[49] += acadoWorkspace.Qd[45];\nacadoWorkspace.QDy[50] += acadoWorkspace.Qd[46];\nacadoWorkspace.QDy[51] += acadoWorkspace.Qd[47];\nacadoWorkspace.QDy[52] += acadoWorkspace.Qd[48];\nacadoWorkspace.QDy[53] += acadoWorkspace.Qd[49];\nacadoWorkspace.QDy[54] += acadoWorkspace.Qd[50];\nacadoWorkspace.QDy[55] += acadoWorkspace.Qd[51];\nacadoWorkspace.QDy[56] += acadoWorkspace.Qd[52];\nacadoWorkspace.QDy[57] += acadoWorkspace.Qd[53];\nacadoWorkspace.QDy[58] += acadoWorkspace.Qd[54];\nacadoWorkspace.QDy[59] += acadoWorkspace.Qd[55];\nacadoWorkspace.QDy[60] += acadoWorkspace.Qd[56];\nacadoWorkspace.QDy[61] += acadoWorkspace.Qd[57];\nacadoWorkspace.QDy[62] += acadoWorkspace.Qd[58];\nacadoWorkspace.QDy[63] += acadoWorkspace.Qd[59];\nacadoWorkspace.QDy[64] += acadoWorkspace.Qd[60];\nacadoWorkspace.QDy[65] += acadoWorkspace.Qd[61];\nacadoWorkspace.QDy[66] += acadoWorkspace.Qd[62];\nacadoWorkspace.QDy[67] += acadoWorkspace.Qd[63];\n\nacadoWorkspace.g[0] = + acadoWorkspace.evGx[0]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[4]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[8]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[12]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[16]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[20]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[24]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[28]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[32]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[36]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[40]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[44]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[48]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[52]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[56]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[60]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[64]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[68]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[72]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[76]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[80]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[84]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[88]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[92]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[96]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[100]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[104]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[108]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[112]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[116]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[120]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[124]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[128]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[132]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[136]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[140]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[144]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[148]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[152]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[156]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[160]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[164]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[168]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[172]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[176]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[180]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[184]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[188]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[192]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[196]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[200]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[204]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[208]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[212]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[216]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[220]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[224]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[228]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[232]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[236]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[240]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[244]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[248]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[252]*acadoWorkspace.QDy[67];\nacadoWorkspace.g[1] = + acadoWorkspace.evGx[1]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[5]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[9]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[13]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[17]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[21]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[25]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[29]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[33]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[37]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[41]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[45]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[49]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[53]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[57]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[61]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[65]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[69]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[73]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[77]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[81]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[85]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[89]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[93]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[97]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[101]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[105]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[109]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[113]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[117]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[121]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[125]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[129]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[133]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[137]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[141]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[145]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[149]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[153]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[157]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[161]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[165]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[169]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[173]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[177]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[181]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[185]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[189]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[193]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[197]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[201]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[205]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[209]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[213]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[217]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[221]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[225]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[229]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[233]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[237]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[241]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[245]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[249]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[253]*acadoWorkspace.QDy[67];\nacadoWorkspace.g[2] = + acadoWorkspace.evGx[2]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[6]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[10]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[14]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[18]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[22]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[26]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[30]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[34]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[38]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[42]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[46]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[50]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[54]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[58]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[62]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[66]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[70]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[74]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[78]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[82]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[86]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[90]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[94]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[98]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[102]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[106]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[110]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[114]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[118]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[122]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[126]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[130]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[134]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[138]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[142]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[146]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[150]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[154]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[158]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[162]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[166]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[170]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[174]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[178]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[182]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[186]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[190]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[194]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[198]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[202]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[206]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[210]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[214]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[218]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[222]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[226]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[230]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[234]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[238]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[242]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[246]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[250]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[254]*acadoWorkspace.QDy[67];\nacadoWorkspace.g[3] = + acadoWorkspace.evGx[3]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[7]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[11]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[15]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[19]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[23]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[27]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[31]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[35]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[39]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[43]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[47]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[51]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[55]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[59]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[63]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[67]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[71]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[75]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[79]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[83]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[87]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[91]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[95]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[99]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[103]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[107]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[111]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[115]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[119]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[123]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[127]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[131]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[135]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[139]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[143]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[147]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[151]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[155]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[159]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[163]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[167]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[171]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[175]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[179]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[183]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[187]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[191]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[195]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[199]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[203]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[207]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[211]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[215]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[219]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[223]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[227]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[231]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[235]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[239]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[243]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[247]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[251]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[255]*acadoWorkspace.QDy[67];\n\n\nacado_multEQDy( acadoWorkspace.E, &(acadoWorkspace.QDy[ 4 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 4 ]), &(acadoWorkspace.QDy[ 8 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QDy[ 16 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.QDy[ 20 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 8 ]), &(acadoWorkspace.QDy[ 8 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 16 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.QDy[ 16 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.QDy[ 20 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 20 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 32 ]), &(acadoWorkspace.QDy[ 16 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QDy[ 20 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QDy[ 16 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 52 ]), &(acadoWorkspace.QDy[ 20 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 56 ]), &(acadoWorkspace.QDy[ 20 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 76 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 80 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 104 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QDy[ 28 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 136 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 140 ]), &(acadoWorkspace.QDy[ 32 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 172 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 176 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 212 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QDy[ 40 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 256 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 260 ]), &(acadoWorkspace.QDy[ 44 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 304 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 308 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 356 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QDy[ 52 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 412 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 416 ]), &(acadoWorkspace.QDy[ 56 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 472 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 532 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 476 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 536 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QDy[ 64 ]), &(acadoWorkspace.g[ 19 ]) );\n\nacadoWorkspace.lb[0] = acadoWorkspace.Dx0[0];\nacadoWorkspace.lb[1] = acadoWorkspace.Dx0[1];\nacadoWorkspace.lb[2] = acadoWorkspace.Dx0[2];\nacadoWorkspace.lb[3] = acadoWorkspace.Dx0[3];\nacadoWorkspace.ub[0] = acadoWorkspace.Dx0[0];\nacadoWorkspace.ub[1] = acadoWorkspace.Dx0[1];\nacadoWorkspace.ub[2] = acadoWorkspace.Dx0[2];\nacadoWorkspace.ub[3] = acadoWorkspace.Dx0[3];\ntmp = acadoVariables.x[6] + acadoWorkspace.d[2];\nacadoWorkspace.lbA[0] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[0] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[7] + acadoWorkspace.d[3];\nacadoWorkspace.lbA[1] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[1] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[10] + acadoWorkspace.d[6];\nacadoWorkspace.lbA[2] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[2] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[11] + acadoWorkspace.d[7];\nacadoWorkspace.lbA[3] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[3] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[14] + acadoWorkspace.d[10];\nacadoWorkspace.lbA[4] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[4] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[15] + acadoWorkspace.d[11];\nacadoWorkspace.lbA[5] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[5] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[18] + acadoWorkspace.d[14];\nacadoWorkspace.lbA[6] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[6] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[19] + acadoWorkspace.d[15];\nacadoWorkspace.lbA[7] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[7] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[22] + acadoWorkspace.d[18];\nacadoWorkspace.lbA[8] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[8] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[23] + acadoWorkspace.d[19];\nacadoWorkspace.lbA[9] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[9] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[26] + acadoWorkspace.d[22];\nacadoWorkspace.lbA[10] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[10] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[27] + acadoWorkspace.d[23];\nacadoWorkspace.lbA[11] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[11] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[30] + acadoWorkspace.d[26];\nacadoWorkspace.lbA[12] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[12] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[31] + acadoWorkspace.d[27];\nacadoWorkspace.lbA[13] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[13] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[34] + acadoWorkspace.d[30];\nacadoWorkspace.lbA[14] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[14] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[35] + acadoWorkspace.d[31];\nacadoWorkspace.lbA[15] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[15] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[38] + acadoWorkspace.d[34];\nacadoWorkspace.lbA[16] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[16] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[39] + acadoWorkspace.d[35];\nacadoWorkspace.lbA[17] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[17] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[42] + acadoWorkspace.d[38];\nacadoWorkspace.lbA[18] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[18] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[43] + acadoWorkspace.d[39];\nacadoWorkspace.lbA[19] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[19] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[46] + acadoWorkspace.d[42];\nacadoWorkspace.lbA[20] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[20] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[47] + acadoWorkspace.d[43];\nacadoWorkspace.lbA[21] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[21] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[50] + acadoWorkspace.d[46];\nacadoWorkspace.lbA[22] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[22] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[51] + acadoWorkspace.d[47];\nacadoWorkspace.lbA[23] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[23] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[54] + acadoWorkspace.d[50];\nacadoWorkspace.lbA[24] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[24] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[55] + acadoWorkspace.d[51];\nacadoWorkspace.lbA[25] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[25] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[58] + acadoWorkspace.d[54];\nacadoWorkspace.lbA[26] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[26] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[59] + acadoWorkspace.d[55];\nacadoWorkspace.lbA[27] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[27] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[62] + acadoWorkspace.d[58];\nacadoWorkspace.lbA[28] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[28] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[63] + acadoWorkspace.d[59];\nacadoWorkspace.lbA[29] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[29] = (real_t)8.7266462599716477e-01 - tmp;\ntmp = acadoVariables.x[66] + acadoWorkspace.d[62];\nacadoWorkspace.lbA[30] = (real_t)-1.5707963267948966e+00 - tmp;\nacadoWorkspace.ubA[30] = (real_t)1.5707963267948966e+00 - tmp;\ntmp = acadoVariables.x[67] + acadoWorkspace.d[63];\nacadoWorkspace.lbA[31] = (real_t)-8.7266462599716477e-01 - tmp;\nacadoWorkspace.ubA[31] = (real_t)8.7266462599716477e-01 - tmp;\n\n}\n\nvoid acado_expand(  )\n{\nacadoVariables.x[0] += acadoWorkspace.x[0];\nacadoVariables.x[1] += acadoWorkspace.x[1];\nacadoVariables.x[2] += acadoWorkspace.x[2];\nacadoVariables.x[3] += acadoWorkspace.x[3];\n\nacadoVariables.u[0] += acadoWorkspace.x[4];\nacadoVariables.u[1] += acadoWorkspace.x[5];\nacadoVariables.u[2] += acadoWorkspace.x[6];\nacadoVariables.u[3] += acadoWorkspace.x[7];\nacadoVariables.u[4] += acadoWorkspace.x[8];\nacadoVariables.u[5] += acadoWorkspace.x[9];\nacadoVariables.u[6] += acadoWorkspace.x[10];\nacadoVariables.u[7] += acadoWorkspace.x[11];\nacadoVariables.u[8] += acadoWorkspace.x[12];\nacadoVariables.u[9] += acadoWorkspace.x[13];\nacadoVariables.u[10] += acadoWorkspace.x[14];\nacadoVariables.u[11] += acadoWorkspace.x[15];\nacadoVariables.u[12] += acadoWorkspace.x[16];\nacadoVariables.u[13] += acadoWorkspace.x[17];\nacadoVariables.u[14] += acadoWorkspace.x[18];\nacadoVariables.u[15] += acadoWorkspace.x[19];\n\nacadoVariables.x[4] += + acadoWorkspace.evGx[0]*acadoWorkspace.x[0] + acadoWorkspace.evGx[1]*acadoWorkspace.x[1] + acadoWorkspace.evGx[2]*acadoWorkspace.x[2] + acadoWorkspace.evGx[3]*acadoWorkspace.x[3] + acadoWorkspace.d[0];\nacadoVariables.x[5] += + acadoWorkspace.evGx[4]*acadoWorkspace.x[0] + acadoWorkspace.evGx[5]*acadoWorkspace.x[1] + acadoWorkspace.evGx[6]*acadoWorkspace.x[2] + acadoWorkspace.evGx[7]*acadoWorkspace.x[3] + acadoWorkspace.d[1];\nacadoVariables.x[6] += + acadoWorkspace.evGx[8]*acadoWorkspace.x[0] + acadoWorkspace.evGx[9]*acadoWorkspace.x[1] + acadoWorkspace.evGx[10]*acadoWorkspace.x[2] + acadoWorkspace.evGx[11]*acadoWorkspace.x[3] + acadoWorkspace.d[2];\nacadoVariables.x[7] += + acadoWorkspace.evGx[12]*acadoWorkspace.x[0] + acadoWorkspace.evGx[13]*acadoWorkspace.x[1] + acadoWorkspace.evGx[14]*acadoWorkspace.x[2] + acadoWorkspace.evGx[15]*acadoWorkspace.x[3] + acadoWorkspace.d[3];\nacadoVariables.x[8] += + acadoWorkspace.evGx[16]*acadoWorkspace.x[0] + acadoWorkspace.evGx[17]*acadoWorkspace.x[1] + acadoWorkspace.evGx[18]*acadoWorkspace.x[2] + acadoWorkspace.evGx[19]*acadoWorkspace.x[3] + acadoWorkspace.d[4];\nacadoVariables.x[9] += + acadoWorkspace.evGx[20]*acadoWorkspace.x[0] + acadoWorkspace.evGx[21]*acadoWorkspace.x[1] + acadoWorkspace.evGx[22]*acadoWorkspace.x[2] + acadoWorkspace.evGx[23]*acadoWorkspace.x[3] + acadoWorkspace.d[5];\nacadoVariables.x[10] += + acadoWorkspace.evGx[24]*acadoWorkspace.x[0] + acadoWorkspace.evGx[25]*acadoWorkspace.x[1] + acadoWorkspace.evGx[26]*acadoWorkspace.x[2] + acadoWorkspace.evGx[27]*acadoWorkspace.x[3] + acadoWorkspace.d[6];\nacadoVariables.x[11] += + acadoWorkspace.evGx[28]*acadoWorkspace.x[0] + acadoWorkspace.evGx[29]*acadoWorkspace.x[1] + acadoWorkspace.evGx[30]*acadoWorkspace.x[2] + acadoWorkspace.evGx[31]*acadoWorkspace.x[3] + acadoWorkspace.d[7];\nacadoVariables.x[12] += + acadoWorkspace.evGx[32]*acadoWorkspace.x[0] + acadoWorkspace.evGx[33]*acadoWorkspace.x[1] + acadoWorkspace.evGx[34]*acadoWorkspace.x[2] + acadoWorkspace.evGx[35]*acadoWorkspace.x[3] + acadoWorkspace.d[8];\nacadoVariables.x[13] += + acadoWorkspace.evGx[36]*acadoWorkspace.x[0] + acadoWorkspace.evGx[37]*acadoWorkspace.x[1] + acadoWorkspace.evGx[38]*acadoWorkspace.x[2] + acadoWorkspace.evGx[39]*acadoWorkspace.x[3] + acadoWorkspace.d[9];\nacadoVariables.x[14] += + acadoWorkspace.evGx[40]*acadoWorkspace.x[0] + acadoWorkspace.evGx[41]*acadoWorkspace.x[1] + acadoWorkspace.evGx[42]*acadoWorkspace.x[2] + acadoWorkspace.evGx[43]*acadoWorkspace.x[3] + acadoWorkspace.d[10];\nacadoVariables.x[15] += + acadoWorkspace.evGx[44]*acadoWorkspace.x[0] + acadoWorkspace.evGx[45]*acadoWorkspace.x[1] + acadoWorkspace.evGx[46]*acadoWorkspace.x[2] + acadoWorkspace.evGx[47]*acadoWorkspace.x[3] + acadoWorkspace.d[11];\nacadoVariables.x[16] += + acadoWorkspace.evGx[48]*acadoWorkspace.x[0] + acadoWorkspace.evGx[49]*acadoWorkspace.x[1] + acadoWorkspace.evGx[50]*acadoWorkspace.x[2] + acadoWorkspace.evGx[51]*acadoWorkspace.x[3] + acadoWorkspace.d[12];\nacadoVariables.x[17] += + acadoWorkspace.evGx[52]*acadoWorkspace.x[0] + acadoWorkspace.evGx[53]*acadoWorkspace.x[1] + acadoWorkspace.evGx[54]*acadoWorkspace.x[2] + acadoWorkspace.evGx[55]*acadoWorkspace.x[3] + acadoWorkspace.d[13];\nacadoVariables.x[18] += + acadoWorkspace.evGx[56]*acadoWorkspace.x[0] + acadoWorkspace.evGx[57]*acadoWorkspace.x[1] + acadoWorkspace.evGx[58]*acadoWorkspace.x[2] + acadoWorkspace.evGx[59]*acadoWorkspace.x[3] + acadoWorkspace.d[14];\nacadoVariables.x[19] += + acadoWorkspace.evGx[60]*acadoWorkspace.x[0] + acadoWorkspace.evGx[61]*acadoWorkspace.x[1] + acadoWorkspace.evGx[62]*acadoWorkspace.x[2] + acadoWorkspace.evGx[63]*acadoWorkspace.x[3] + acadoWorkspace.d[15];\nacadoVariables.x[20] += + acadoWorkspace.evGx[64]*acadoWorkspace.x[0] + acadoWorkspace.evGx[65]*acadoWorkspace.x[1] + acadoWorkspace.evGx[66]*acadoWorkspace.x[2] + acadoWorkspace.evGx[67]*acadoWorkspace.x[3] + acadoWorkspace.d[16];\nacadoVariables.x[21] += + acadoWorkspace.evGx[68]*acadoWorkspace.x[0] + acadoWorkspace.evGx[69]*acadoWorkspace.x[1] + acadoWorkspace.evGx[70]*acadoWorkspace.x[2] + acadoWorkspace.evGx[71]*acadoWorkspace.x[3] + acadoWorkspace.d[17];\nacadoVariables.x[22] += + acadoWorkspace.evGx[72]*acadoWorkspace.x[0] + acadoWorkspace.evGx[73]*acadoWorkspace.x[1] + acadoWorkspace.evGx[74]*acadoWorkspace.x[2] + acadoWorkspace.evGx[75]*acadoWorkspace.x[3] + acadoWorkspace.d[18];\nacadoVariables.x[23] += + acadoWorkspace.evGx[76]*acadoWorkspace.x[0] + acadoWorkspace.evGx[77]*acadoWorkspace.x[1] + acadoWorkspace.evGx[78]*acadoWorkspace.x[2] + acadoWorkspace.evGx[79]*acadoWorkspace.x[3] + acadoWorkspace.d[19];\nacadoVariables.x[24] += + acadoWorkspace.evGx[80]*acadoWorkspace.x[0] + acadoWorkspace.evGx[81]*acadoWorkspace.x[1] + acadoWorkspace.evGx[82]*acadoWorkspace.x[2] + acadoWorkspace.evGx[83]*acadoWorkspace.x[3] + acadoWorkspace.d[20];\nacadoVariables.x[25] += + acadoWorkspace.evGx[84]*acadoWorkspace.x[0] + acadoWorkspace.evGx[85]*acadoWorkspace.x[1] + acadoWorkspace.evGx[86]*acadoWorkspace.x[2] + acadoWorkspace.evGx[87]*acadoWorkspace.x[3] + acadoWorkspace.d[21];\nacadoVariables.x[26] += + acadoWorkspace.evGx[88]*acadoWorkspace.x[0] + acadoWorkspace.evGx[89]*acadoWorkspace.x[1] + acadoWorkspace.evGx[90]*acadoWorkspace.x[2] + acadoWorkspace.evGx[91]*acadoWorkspace.x[3] + acadoWorkspace.d[22];\nacadoVariables.x[27] += + acadoWorkspace.evGx[92]*acadoWorkspace.x[0] + acadoWorkspace.evGx[93]*acadoWorkspace.x[1] + acadoWorkspace.evGx[94]*acadoWorkspace.x[2] + acadoWorkspace.evGx[95]*acadoWorkspace.x[3] + acadoWorkspace.d[23];\nacadoVariables.x[28] += + acadoWorkspace.evGx[96]*acadoWorkspace.x[0] + acadoWorkspace.evGx[97]*acadoWorkspace.x[1] + acadoWorkspace.evGx[98]*acadoWorkspace.x[2] + acadoWorkspace.evGx[99]*acadoWorkspace.x[3] + acadoWorkspace.d[24];\nacadoVariables.x[29] += + acadoWorkspace.evGx[100]*acadoWorkspace.x[0] + acadoWorkspace.evGx[101]*acadoWorkspace.x[1] + acadoWorkspace.evGx[102]*acadoWorkspace.x[2] + acadoWorkspace.evGx[103]*acadoWorkspace.x[3] + acadoWorkspace.d[25];\nacadoVariables.x[30] += + acadoWorkspace.evGx[104]*acadoWorkspace.x[0] + acadoWorkspace.evGx[105]*acadoWorkspace.x[1] + acadoWorkspace.evGx[106]*acadoWorkspace.x[2] + acadoWorkspace.evGx[107]*acadoWorkspace.x[3] + acadoWorkspace.d[26];\nacadoVariables.x[31] += + acadoWorkspace.evGx[108]*acadoWorkspace.x[0] + acadoWorkspace.evGx[109]*acadoWorkspace.x[1] + acadoWorkspace.evGx[110]*acadoWorkspace.x[2] + acadoWorkspace.evGx[111]*acadoWorkspace.x[3] + acadoWorkspace.d[27];\nacadoVariables.x[32] += + acadoWorkspace.evGx[112]*acadoWorkspace.x[0] + acadoWorkspace.evGx[113]*acadoWorkspace.x[1] + acadoWorkspace.evGx[114]*acadoWorkspace.x[2] + acadoWorkspace.evGx[115]*acadoWorkspace.x[3] + acadoWorkspace.d[28];\nacadoVariables.x[33] += + acadoWorkspace.evGx[116]*acadoWorkspace.x[0] + acadoWorkspace.evGx[117]*acadoWorkspace.x[1] + acadoWorkspace.evGx[118]*acadoWorkspace.x[2] + acadoWorkspace.evGx[119]*acadoWorkspace.x[3] + acadoWorkspace.d[29];\nacadoVariables.x[34] += + acadoWorkspace.evGx[120]*acadoWorkspace.x[0] + acadoWorkspace.evGx[121]*acadoWorkspace.x[1] + acadoWorkspace.evGx[122]*acadoWorkspace.x[2] + acadoWorkspace.evGx[123]*acadoWorkspace.x[3] + acadoWorkspace.d[30];\nacadoVariables.x[35] += + acadoWorkspace.evGx[124]*acadoWorkspace.x[0] + acadoWorkspace.evGx[125]*acadoWorkspace.x[1] + acadoWorkspace.evGx[126]*acadoWorkspace.x[2] + acadoWorkspace.evGx[127]*acadoWorkspace.x[3] + acadoWorkspace.d[31];\nacadoVariables.x[36] += + acadoWorkspace.evGx[128]*acadoWorkspace.x[0] + acadoWorkspace.evGx[129]*acadoWorkspace.x[1] + acadoWorkspace.evGx[130]*acadoWorkspace.x[2] + acadoWorkspace.evGx[131]*acadoWorkspace.x[3] + acadoWorkspace.d[32];\nacadoVariables.x[37] += + acadoWorkspace.evGx[132]*acadoWorkspace.x[0] + acadoWorkspace.evGx[133]*acadoWorkspace.x[1] + acadoWorkspace.evGx[134]*acadoWorkspace.x[2] + acadoWorkspace.evGx[135]*acadoWorkspace.x[3] + acadoWorkspace.d[33];\nacadoVariables.x[38] += + acadoWorkspace.evGx[136]*acadoWorkspace.x[0] + acadoWorkspace.evGx[137]*acadoWorkspace.x[1] + acadoWorkspace.evGx[138]*acadoWorkspace.x[2] + acadoWorkspace.evGx[139]*acadoWorkspace.x[3] + acadoWorkspace.d[34];\nacadoVariables.x[39] += + acadoWorkspace.evGx[140]*acadoWorkspace.x[0] + acadoWorkspace.evGx[141]*acadoWorkspace.x[1] + acadoWorkspace.evGx[142]*acadoWorkspace.x[2] + acadoWorkspace.evGx[143]*acadoWorkspace.x[3] + acadoWorkspace.d[35];\nacadoVariables.x[40] += + acadoWorkspace.evGx[144]*acadoWorkspace.x[0] + acadoWorkspace.evGx[145]*acadoWorkspace.x[1] + acadoWorkspace.evGx[146]*acadoWorkspace.x[2] + acadoWorkspace.evGx[147]*acadoWorkspace.x[3] + acadoWorkspace.d[36];\nacadoVariables.x[41] += + acadoWorkspace.evGx[148]*acadoWorkspace.x[0] + acadoWorkspace.evGx[149]*acadoWorkspace.x[1] + acadoWorkspace.evGx[150]*acadoWorkspace.x[2] + acadoWorkspace.evGx[151]*acadoWorkspace.x[3] + acadoWorkspace.d[37];\nacadoVariables.x[42] += + acadoWorkspace.evGx[152]*acadoWorkspace.x[0] + acadoWorkspace.evGx[153]*acadoWorkspace.x[1] + acadoWorkspace.evGx[154]*acadoWorkspace.x[2] + acadoWorkspace.evGx[155]*acadoWorkspace.x[3] + acadoWorkspace.d[38];\nacadoVariables.x[43] += + acadoWorkspace.evGx[156]*acadoWorkspace.x[0] + acadoWorkspace.evGx[157]*acadoWorkspace.x[1] + acadoWorkspace.evGx[158]*acadoWorkspace.x[2] + acadoWorkspace.evGx[159]*acadoWorkspace.x[3] + acadoWorkspace.d[39];\nacadoVariables.x[44] += + acadoWorkspace.evGx[160]*acadoWorkspace.x[0] + acadoWorkspace.evGx[161]*acadoWorkspace.x[1] + acadoWorkspace.evGx[162]*acadoWorkspace.x[2] + acadoWorkspace.evGx[163]*acadoWorkspace.x[3] + acadoWorkspace.d[40];\nacadoVariables.x[45] += + acadoWorkspace.evGx[164]*acadoWorkspace.x[0] + acadoWorkspace.evGx[165]*acadoWorkspace.x[1] + acadoWorkspace.evGx[166]*acadoWorkspace.x[2] + acadoWorkspace.evGx[167]*acadoWorkspace.x[3] + acadoWorkspace.d[41];\nacadoVariables.x[46] += + acadoWorkspace.evGx[168]*acadoWorkspace.x[0] + acadoWorkspace.evGx[169]*acadoWorkspace.x[1] + acadoWorkspace.evGx[170]*acadoWorkspace.x[2] + acadoWorkspace.evGx[171]*acadoWorkspace.x[3] + acadoWorkspace.d[42];\nacadoVariables.x[47] += + acadoWorkspace.evGx[172]*acadoWorkspace.x[0] + acadoWorkspace.evGx[173]*acadoWorkspace.x[1] + acadoWorkspace.evGx[174]*acadoWorkspace.x[2] + acadoWorkspace.evGx[175]*acadoWorkspace.x[3] + acadoWorkspace.d[43];\nacadoVariables.x[48] += + acadoWorkspace.evGx[176]*acadoWorkspace.x[0] + acadoWorkspace.evGx[177]*acadoWorkspace.x[1] + acadoWorkspace.evGx[178]*acadoWorkspace.x[2] + acadoWorkspace.evGx[179]*acadoWorkspace.x[3] + acadoWorkspace.d[44];\nacadoVariables.x[49] += + acadoWorkspace.evGx[180]*acadoWorkspace.x[0] + acadoWorkspace.evGx[181]*acadoWorkspace.x[1] + acadoWorkspace.evGx[182]*acadoWorkspace.x[2] + acadoWorkspace.evGx[183]*acadoWorkspace.x[3] + acadoWorkspace.d[45];\nacadoVariables.x[50] += + acadoWorkspace.evGx[184]*acadoWorkspace.x[0] + acadoWorkspace.evGx[185]*acadoWorkspace.x[1] + acadoWorkspace.evGx[186]*acadoWorkspace.x[2] + acadoWorkspace.evGx[187]*acadoWorkspace.x[3] + acadoWorkspace.d[46];\nacadoVariables.x[51] += + acadoWorkspace.evGx[188]*acadoWorkspace.x[0] + acadoWorkspace.evGx[189]*acadoWorkspace.x[1] + acadoWorkspace.evGx[190]*acadoWorkspace.x[2] + acadoWorkspace.evGx[191]*acadoWorkspace.x[3] + acadoWorkspace.d[47];\nacadoVariables.x[52] += + acadoWorkspace.evGx[192]*acadoWorkspace.x[0] + acadoWorkspace.evGx[193]*acadoWorkspace.x[1] + acadoWorkspace.evGx[194]*acadoWorkspace.x[2] + acadoWorkspace.evGx[195]*acadoWorkspace.x[3] + acadoWorkspace.d[48];\nacadoVariables.x[53] += + acadoWorkspace.evGx[196]*acadoWorkspace.x[0] + acadoWorkspace.evGx[197]*acadoWorkspace.x[1] + acadoWorkspace.evGx[198]*acadoWorkspace.x[2] + acadoWorkspace.evGx[199]*acadoWorkspace.x[3] + acadoWorkspace.d[49];\nacadoVariables.x[54] += + acadoWorkspace.evGx[200]*acadoWorkspace.x[0] + acadoWorkspace.evGx[201]*acadoWorkspace.x[1] + acadoWorkspace.evGx[202]*acadoWorkspace.x[2] + acadoWorkspace.evGx[203]*acadoWorkspace.x[3] + acadoWorkspace.d[50];\nacadoVariables.x[55] += + acadoWorkspace.evGx[204]*acadoWorkspace.x[0] + acadoWorkspace.evGx[205]*acadoWorkspace.x[1] + acadoWorkspace.evGx[206]*acadoWorkspace.x[2] + acadoWorkspace.evGx[207]*acadoWorkspace.x[3] + acadoWorkspace.d[51];\nacadoVariables.x[56] += + acadoWorkspace.evGx[208]*acadoWorkspace.x[0] + acadoWorkspace.evGx[209]*acadoWorkspace.x[1] + acadoWorkspace.evGx[210]*acadoWorkspace.x[2] + acadoWorkspace.evGx[211]*acadoWorkspace.x[3] + acadoWorkspace.d[52];\nacadoVariables.x[57] += + acadoWorkspace.evGx[212]*acadoWorkspace.x[0] + acadoWorkspace.evGx[213]*acadoWorkspace.x[1] + acadoWorkspace.evGx[214]*acadoWorkspace.x[2] + acadoWorkspace.evGx[215]*acadoWorkspace.x[3] + acadoWorkspace.d[53];\nacadoVariables.x[58] += + acadoWorkspace.evGx[216]*acadoWorkspace.x[0] + acadoWorkspace.evGx[217]*acadoWorkspace.x[1] + acadoWorkspace.evGx[218]*acadoWorkspace.x[2] + acadoWorkspace.evGx[219]*acadoWorkspace.x[3] + acadoWorkspace.d[54];\nacadoVariables.x[59] += + acadoWorkspace.evGx[220]*acadoWorkspace.x[0] + acadoWorkspace.evGx[221]*acadoWorkspace.x[1] + acadoWorkspace.evGx[222]*acadoWorkspace.x[2] + acadoWorkspace.evGx[223]*acadoWorkspace.x[3] + acadoWorkspace.d[55];\nacadoVariables.x[60] += + acadoWorkspace.evGx[224]*acadoWorkspace.x[0] + acadoWorkspace.evGx[225]*acadoWorkspace.x[1] + acadoWorkspace.evGx[226]*acadoWorkspace.x[2] + acadoWorkspace.evGx[227]*acadoWorkspace.x[3] + acadoWorkspace.d[56];\nacadoVariables.x[61] += + acadoWorkspace.evGx[228]*acadoWorkspace.x[0] + acadoWorkspace.evGx[229]*acadoWorkspace.x[1] + acadoWorkspace.evGx[230]*acadoWorkspace.x[2] + acadoWorkspace.evGx[231]*acadoWorkspace.x[3] + acadoWorkspace.d[57];\nacadoVariables.x[62] += + acadoWorkspace.evGx[232]*acadoWorkspace.x[0] + acadoWorkspace.evGx[233]*acadoWorkspace.x[1] + acadoWorkspace.evGx[234]*acadoWorkspace.x[2] + acadoWorkspace.evGx[235]*acadoWorkspace.x[3] + acadoWorkspace.d[58];\nacadoVariables.x[63] += + acadoWorkspace.evGx[236]*acadoWorkspace.x[0] + acadoWorkspace.evGx[237]*acadoWorkspace.x[1] + acadoWorkspace.evGx[238]*acadoWorkspace.x[2] + acadoWorkspace.evGx[239]*acadoWorkspace.x[3] + acadoWorkspace.d[59];\nacadoVariables.x[64] += + acadoWorkspace.evGx[240]*acadoWorkspace.x[0] + acadoWorkspace.evGx[241]*acadoWorkspace.x[1] + acadoWorkspace.evGx[242]*acadoWorkspace.x[2] + acadoWorkspace.evGx[243]*acadoWorkspace.x[3] + acadoWorkspace.d[60];\nacadoVariables.x[65] += + acadoWorkspace.evGx[244]*acadoWorkspace.x[0] + acadoWorkspace.evGx[245]*acadoWorkspace.x[1] + acadoWorkspace.evGx[246]*acadoWorkspace.x[2] + acadoWorkspace.evGx[247]*acadoWorkspace.x[3] + acadoWorkspace.d[61];\nacadoVariables.x[66] += + acadoWorkspace.evGx[248]*acadoWorkspace.x[0] + acadoWorkspace.evGx[249]*acadoWorkspace.x[1] + acadoWorkspace.evGx[250]*acadoWorkspace.x[2] + acadoWorkspace.evGx[251]*acadoWorkspace.x[3] + acadoWorkspace.d[62];\nacadoVariables.x[67] += + acadoWorkspace.evGx[252]*acadoWorkspace.x[0] + acadoWorkspace.evGx[253]*acadoWorkspace.x[1] + acadoWorkspace.evGx[254]*acadoWorkspace.x[2] + acadoWorkspace.evGx[255]*acadoWorkspace.x[3] + acadoWorkspace.d[63];\n\nacado_multEDu( acadoWorkspace.E, &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 4 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 4 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 8 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 8 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 8 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 16 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 20 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 16 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 28 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 16 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 32 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 16 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 16 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 40 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 20 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 44 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 20 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 20 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 52 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 20 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 56 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 20 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 64 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 68 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 76 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 80 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 88 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 92 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 100 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 104 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 28 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 112 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 116 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 124 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 128 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 136 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 140 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 32 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 148 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 152 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 160 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 164 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 172 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 176 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 36 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 184 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 188 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 196 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 200 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 208 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 212 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 40 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 220 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 224 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 232 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 236 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 244 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 248 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 256 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 260 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 44 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 268 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 272 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 280 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 284 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 292 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 296 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 304 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 308 ]), &(acadoWorkspace.x[ 15 ]), &(acadoVariables.x[ 48 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 316 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 320 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 328 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 332 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 340 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 344 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 352 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 356 ]), &(acadoWorkspace.x[ 15 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.x[ 16 ]), &(acadoVariables.x[ 52 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 364 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 368 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 376 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 380 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 388 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 392 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 400 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 404 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.x[ 15 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 412 ]), &(acadoWorkspace.x[ 16 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 416 ]), &(acadoWorkspace.x[ 17 ]), &(acadoVariables.x[ 56 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 424 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 428 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 436 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 440 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 448 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 452 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 460 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 464 ]), &(acadoWorkspace.x[ 15 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.x[ 16 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 472 ]), &(acadoWorkspace.x[ 17 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 476 ]), &(acadoWorkspace.x[ 18 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 484 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 488 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 496 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 500 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 508 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 512 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 520 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 524 ]), &(acadoWorkspace.x[ 15 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.x[ 16 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 532 ]), &(acadoWorkspace.x[ 17 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 536 ]), &(acadoWorkspace.x[ 18 ]), &(acadoVariables.x[ 64 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.x[ 19 ]), &(acadoVariables.x[ 64 ]) );\n}\n\nint acado_preparationStep(  )\n{\nint ret;\n\nret = acado_modelSimulation();\nacado_evaluateObjective(  );\nacado_condensePrep(  );\nreturn ret;\n}\n\nint acado_feedbackStep(  )\n{\nint tmp;\n\nacado_condenseFdb(  );\n\ntmp = acado_solve( );\n\nacado_expand(  );\nreturn tmp;\n}\n\nint acado_initializeSolver(  )\n{\nint ret;\n\n/* This is a function which must be called once before any other function call! */\n\n\nret = 0;\n\nmemset(&acadoWorkspace, 0, sizeof( acadoWorkspace ));\nreturn ret;\n}\n\nvoid acado_initializeNodesByForwardSimulation(  )\n{\nint index;\nfor (index = 0; index < 16; ++index)\n{\nacadoWorkspace.state[0] = acadoVariables.x[index * 4];\nacadoWorkspace.state[1] = acadoVariables.x[index * 4 + 1];\nacadoWorkspace.state[2] = acadoVariables.x[index * 4 + 2];\nacadoWorkspace.state[3] = acadoVariables.x[index * 4 + 3];\nacadoWorkspace.state[24] = acadoVariables.u[index];\nacadoWorkspace.state[25] = acadoVariables.od[index * 2];\nacadoWorkspace.state[26] = acadoVariables.od[index * 2 + 1];\n\nacado_integrate(acadoWorkspace.state, index == 0, index);\n\nacadoVariables.x[index * 4 + 4] = acadoWorkspace.state[0];\nacadoVariables.x[index * 4 + 5] = acadoWorkspace.state[1];\nacadoVariables.x[index * 4 + 6] = acadoWorkspace.state[2];\nacadoVariables.x[index * 4 + 7] = acadoWorkspace.state[3];\n}\n}\n\nvoid acado_shiftStates( int strategy, real_t* const xEnd, real_t* const uEnd )\n{\nint index;\nfor (index = 0; index < 16; ++index)\n{\nacadoVariables.x[index * 4] = acadoVariables.x[index * 4 + 4];\nacadoVariables.x[index * 4 + 1] = acadoVariables.x[index * 4 + 5];\nacadoVariables.x[index * 4 + 2] = acadoVariables.x[index * 4 + 6];\nacadoVariables.x[index * 4 + 3] = acadoVariables.x[index * 4 + 7];\n}\n\nif (strategy == 1 && xEnd != 0)\n{\nacadoVariables.x[64] = xEnd[0];\nacadoVariables.x[65] = xEnd[1];\nacadoVariables.x[66] = xEnd[2];\nacadoVariables.x[67] = xEnd[3];\n}\nelse if (strategy == 2) \n{\nacadoWorkspace.state[0] = acadoVariables.x[64];\nacadoWorkspace.state[1] = acadoVariables.x[65];\nacadoWorkspace.state[2] = acadoVariables.x[66];\nacadoWorkspace.state[3] = acadoVariables.x[67];\nif (uEnd != 0)\n{\nacadoWorkspace.state[24] = uEnd[0];\n}\nelse\n{\nacadoWorkspace.state[24] = acadoVariables.u[15];\n}\nacadoWorkspace.state[25] = acadoVariables.od[32];\nacadoWorkspace.state[26] = acadoVariables.od[33];\n\nacado_integrate(acadoWorkspace.state, 1, 15);\n\nacadoVariables.x[64] = acadoWorkspace.state[0];\nacadoVariables.x[65] = acadoWorkspace.state[1];\nacadoVariables.x[66] = acadoWorkspace.state[2];\nacadoVariables.x[67] = acadoWorkspace.state[3];\n}\n}\n\nvoid acado_shiftControls( real_t* const uEnd )\n{\nint index;\nfor (index = 0; index < 15; ++index)\n{\nacadoVariables.u[index] = acadoVariables.u[index + 1];\n}\n\nif (uEnd != 0)\n{\nacadoVariables.u[15] = uEnd[0];\n}\n}\n\nreal_t acado_getKKT(  )\n{\nreal_t kkt;\n\nint index;\nreal_t prd;\n\nkkt = + acadoWorkspace.g[0]*acadoWorkspace.x[0] + acadoWorkspace.g[1]*acadoWorkspace.x[1] + acadoWorkspace.g[2]*acadoWorkspace.x[2] + acadoWorkspace.g[3]*acadoWorkspace.x[3] + acadoWorkspace.g[4]*acadoWorkspace.x[4] + acadoWorkspace.g[5]*acadoWorkspace.x[5] + acadoWorkspace.g[6]*acadoWorkspace.x[6] + acadoWorkspace.g[7]*acadoWorkspace.x[7] + acadoWorkspace.g[8]*acadoWorkspace.x[8] + acadoWorkspace.g[9]*acadoWorkspace.x[9] + acadoWorkspace.g[10]*acadoWorkspace.x[10] + acadoWorkspace.g[11]*acadoWorkspace.x[11] + acadoWorkspace.g[12]*acadoWorkspace.x[12] + acadoWorkspace.g[13]*acadoWorkspace.x[13] + acadoWorkspace.g[14]*acadoWorkspace.x[14] + acadoWorkspace.g[15]*acadoWorkspace.x[15] + acadoWorkspace.g[16]*acadoWorkspace.x[16] + acadoWorkspace.g[17]*acadoWorkspace.x[17] + acadoWorkspace.g[18]*acadoWorkspace.x[18] + acadoWorkspace.g[19]*acadoWorkspace.x[19];\nkkt = fabs( kkt );\nfor (index = 0; index < 20; ++index)\n{\nprd = acadoWorkspace.y[index];\nif (prd > 1e-12)\nkkt += fabs(acadoWorkspace.lb[index] * prd);\nelse if (prd < -1e-12)\nkkt += fabs(acadoWorkspace.ub[index] * prd);\n}\nfor (index = 0; index < 32; ++index)\n{\nprd = acadoWorkspace.y[index + 20];\nif (prd > 1e-12)\nkkt += fabs(acadoWorkspace.lbA[index] * prd);\nelse if (prd < -1e-12)\nkkt += fabs(acadoWorkspace.ubA[index] * prd);\n}\nreturn kkt;\n}\n\nreal_t acado_getObjective(  )\n{\nreal_t objVal;\n\nint lRun1;\n/** Row vector of size: 3 */\nreal_t tmpDy[ 3 ];\n\n/** Row vector of size: 2 */\nreal_t tmpDyN[ 2 ];\n\nfor (lRun1 = 0; lRun1 < 16; ++lRun1)\n{\nacadoWorkspace.objValueIn[0] = acadoVariables.x[lRun1 * 4];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[lRun1 * 4 + 1];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[lRun1 * 4 + 2];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[lRun1 * 4 + 3];\nacadoWorkspace.objValueIn[4] = acadoVariables.u[lRun1];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.objValueIn[6] = acadoVariables.od[lRun1 * 2 + 1];\n\nacado_evaluateLSQ( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\nacadoWorkspace.Dy[lRun1 * 3] = acadoWorkspace.objValueOut[0] - acadoVariables.y[lRun1 * 3];\nacadoWorkspace.Dy[lRun1 * 3 + 1] = acadoWorkspace.objValueOut[1] - acadoVariables.y[lRun1 * 3 + 1];\nacadoWorkspace.Dy[lRun1 * 3 + 2] = acadoWorkspace.objValueOut[2] - acadoVariables.y[lRun1 * 3 + 2];\n}\nacadoWorkspace.objValueIn[0] = acadoVariables.x[64];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[65];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[66];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[67];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[32];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[33];\nacado_evaluateLSQEndTerm( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\nacadoWorkspace.DyN[0] = acadoWorkspace.objValueOut[0] - acadoVariables.yN[0];\nacadoWorkspace.DyN[1] = acadoWorkspace.objValueOut[1] - acadoVariables.yN[1];\nobjVal = 0.0000000000000000e+00;\nfor (lRun1 = 0; lRun1 < 16; ++lRun1)\n{\ntmpDy[0] = + acadoWorkspace.Dy[lRun1 * 3]*acadoVariables.W[lRun1 * 9] + acadoWorkspace.Dy[lRun1 * 3 + 1]*acadoVariables.W[lRun1 * 9 + 3] + acadoWorkspace.Dy[lRun1 * 3 + 2]*acadoVariables.W[lRun1 * 9 + 6];\ntmpDy[1] = + acadoWorkspace.Dy[lRun1 * 3]*acadoVariables.W[lRun1 * 9 + 1] + acadoWorkspace.Dy[lRun1 * 3 + 1]*acadoVariables.W[lRun1 * 9 + 4] + acadoWorkspace.Dy[lRun1 * 3 + 2]*acadoVariables.W[lRun1 * 9 + 7];\ntmpDy[2] = + acadoWorkspace.Dy[lRun1 * 3]*acadoVariables.W[lRun1 * 9 + 2] + acadoWorkspace.Dy[lRun1 * 3 + 1]*acadoVariables.W[lRun1 * 9 + 5] + acadoWorkspace.Dy[lRun1 * 3 + 2]*acadoVariables.W[lRun1 * 9 + 8];\nobjVal += + acadoWorkspace.Dy[lRun1 * 3]*tmpDy[0] + acadoWorkspace.Dy[lRun1 * 3 + 1]*tmpDy[1] + acadoWorkspace.Dy[lRun1 * 3 + 2]*tmpDy[2];\n}\n\ntmpDyN[0] = + acadoWorkspace.DyN[0]*acadoVariables.WN[0] + acadoWorkspace.DyN[1]*acadoVariables.WN[2];\ntmpDyN[1] = + acadoWorkspace.DyN[0]*acadoVariables.WN[1] + acadoWorkspace.DyN[1]*acadoVariables.WN[3];\nobjVal += + acadoWorkspace.DyN[0]*tmpDyN[0] + acadoWorkspace.DyN[1]*tmpDyN[1];\n\nobjVal *= 0.5;\nreturn objVal;\n}\n\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_mpc/libmpc_py.py",
    "content": "import os\n\nfrom cffi import FFI\nfrom common.ffi_wrapper import suffix\n\nmpc_dir = os.path.dirname(os.path.abspath(__file__))\nlibmpc_fn = os.path.join(mpc_dir, \"libmpc\"+suffix())\n\nffi = FFI()\nffi.cdef(\"\"\"\ntypedef struct {\n    double x, y, psi, curvature, curvature_rate;\n} state_t;\nint N = 16;\n\ntypedef struct {\n    double x[N+1];\n    double y[N+1];\n    double psi[N+1];\n    double curvature[N+1];\n    double curvature_rate[N];\n    double cost;\n} log_t;\n\nvoid init();\nvoid set_weights(double pathCost, double headingCost, double steerRateCost);\nint run_mpc(state_t * x0, log_t * solution,\n             double v_ego, double rotation_radius,\n             double target_y[N+1], double target_psi[N+1]);\n\"\"\")\n\nlibmpc = ffi.dlopen(libmpc_fn)\n"
  },
  {
    "path": "selfdrive/controls/lib/lateral_planner.py",
    "content": "import math\nimport numpy as np\nfrom common.realtime import sec_since_boot, DT_MDL\nfrom common.numpy_fast import interp\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.controls.lib.lateral_mpc import libmpc_py\nfrom selfdrive.controls.lib.drive_helpers import CONTROL_N, MPC_COST_LAT, LAT_MPC_N, CAR_ROTATION_RADIUS\nfrom selfdrive.controls.lib.lane_planner import LanePlanner, TRAJECTORY_SIZE\nfrom selfdrive.config import Conversions as CV\nimport cereal.messaging as messaging\nfrom cereal import log\n\nLaneChangeState = log.LateralPlan.LaneChangeState\nLaneChangeDirection = log.LateralPlan.LaneChangeDirection\n\nLANE_CHANGE_SPEED_MIN = 30 * CV.MPH_TO_MS\nLANE_CHANGE_TIME_MAX = 10.\n\nDESIRES = {\n  LaneChangeDirection.none: {\n    LaneChangeState.off: log.LateralPlan.Desire.none,\n    LaneChangeState.preLaneChange: log.LateralPlan.Desire.none,\n    LaneChangeState.laneChangeStarting: log.LateralPlan.Desire.none,\n    LaneChangeState.laneChangeFinishing: log.LateralPlan.Desire.none,\n  },\n  LaneChangeDirection.left: {\n    LaneChangeState.off: log.LateralPlan.Desire.none,\n    LaneChangeState.preLaneChange: log.LateralPlan.Desire.none,\n    LaneChangeState.laneChangeStarting: log.LateralPlan.Desire.laneChangeLeft,\n    LaneChangeState.laneChangeFinishing: log.LateralPlan.Desire.laneChangeLeft,\n  },\n  LaneChangeDirection.right: {\n    LaneChangeState.off: log.LateralPlan.Desire.none,\n    LaneChangeState.preLaneChange: log.LateralPlan.Desire.none,\n    LaneChangeState.laneChangeStarting: log.LateralPlan.Desire.laneChangeRight,\n    LaneChangeState.laneChangeFinishing: log.LateralPlan.Desire.laneChangeRight,\n  },\n}\n\n\nclass LateralPlanner():\n  def __init__(self, CP, use_lanelines=True, wide_camera=False):\n    self.use_lanelines = use_lanelines\n    self.LP = LanePlanner(wide_camera)\n\n    self.last_cloudlog_t = 0\n    self.steer_rate_cost = CP.steerRateCost\n\n    self.setup_mpc()\n    self.solution_invalid_cnt = 0\n    self.lane_change_state = LaneChangeState.off\n    self.lane_change_direction = LaneChangeDirection.none\n    self.lane_change_timer = 0.0\n    self.lane_change_ll_prob = 1.0\n    self.keep_pulse_timer = 0.0\n    self.prev_one_blinker = False\n    self.desire = log.LateralPlan.Desire.none\n\n    self.path_xyz = np.zeros((TRAJECTORY_SIZE,3))\n    self.path_xyz_stds = np.ones((TRAJECTORY_SIZE,3))\n    self.plan_yaw = np.zeros((TRAJECTORY_SIZE,))\n    self.t_idxs = np.arange(TRAJECTORY_SIZE)\n    self.y_pts = np.zeros(TRAJECTORY_SIZE)\n    self.d_path_w_lines_xyz = np.zeros((TRAJECTORY_SIZE, 3))\n\n    # dp\n    self.dp_torque_apply_length = 1.5 # secs of torque we apply for\n    self.dp_lc_auto_start = 0. # time to start alc\n    self.dp_lc_auto_start_in = 0. # remaining time to start alc\n    self.dp_lc_auto_torque_end = 0. # time to end applying torque\n    self.dp_torque_apply = False # should we apply torque?\n\n    self.laneless_mode = 2 # AUTO\n    self.laneless_mode_status = False\n    self.laneless_mode_status_buffer = False\n\n  def setup_mpc(self):\n    self.libmpc = libmpc_py.libmpc\n    self.libmpc.init()\n\n    self.mpc_solution = libmpc_py.ffi.new(\"log_t *\")\n    self.cur_state = libmpc_py.ffi.new(\"state_t *\")\n    self.cur_state[0].x = 0.0\n    self.cur_state[0].y = 0.0\n    self.cur_state[0].psi = 0.0\n    self.cur_state[0].curvature = 0.0\n\n    self.desired_curvature = 0.0\n    self.safe_desired_curvature = 0.0\n    self.desired_curvature_rate = 0.0\n    self.safe_desired_curvature_rate = 0.0\n\n  def update(self, sm, CP):\n    self.use_lanelines = not sm['dragonConf'].dpLaneLessModeCtrl\n    self.laneless_mode = sm['dragonConf'].dpLaneLessMode\n    v_ego = sm['carState'].vEgo\n    active = sm['controlsState'].active\n    measured_curvature = sm['controlsState'].curvature\n    self.LP.update_dp_set_offsets(sm['dragonConf'].dpCameraOffset, sm['dragonConf'].dpPathOffset)\n\n    md = sm['modelV2']\n    self.LP.parse_model(sm['modelV2'])\n    if len(md.position.x) == TRAJECTORY_SIZE and len(md.orientation.x) == TRAJECTORY_SIZE:\n      self.path_xyz = np.column_stack([md.position.x, md.position.y, md.position.z])\n      self.t_idxs = np.array(md.position.t)\n      self.plan_yaw = list(md.orientation.z)\n    if len(md.orientation.xStd) == TRAJECTORY_SIZE:\n      self.path_xyz_stds = np.column_stack([md.position.xStd, md.position.yStd, md.position.zStd])\n\n    # Lane change logic\n    one_blinker = sm['carState'].leftBlinker != sm['carState'].rightBlinker\n    below_lane_change_speed = v_ego < (sm['dragonConf'].dpLcMinMph * CV.MPH_TO_MS)\n\n    if (not active) or (self.lane_change_timer > LANE_CHANGE_TIME_MAX):\n      self.lane_change_state = LaneChangeState.off\n      self.lane_change_direction = LaneChangeDirection.none\n    else:\n      reset = False\n      if one_blinker:\n        cur_time = sec_since_boot()\n        # reach auto lc condition\n        if not below_lane_change_speed and sm['dragonConf'].dpLateralMode == 2 and v_ego >= (sm['dragonConf'].dpLcAutoMinMph * CV.MPH_TO_MS):\n          # work out alc start time and torque apply end time\n          if self.dp_lc_auto_start == 0.:\n            self.dp_lc_auto_start = cur_time + sm['dragonConf'].dpLcAutoDelay\n            self.dp_lc_auto_torque_end = self.dp_lc_auto_start + self.dp_torque_apply_length\n          else:\n            # work out how long til alc start\n            # for display only\n            self.dp_lc_auto_start_in = self.dp_lc_auto_start - cur_time\n            self.dp_torque_apply = True if self.dp_lc_auto_start < cur_time <= self.dp_lc_auto_torque_end else False\n      else:\n        reset = True\n\n      # reset all vals\n      if not active or reset:\n        self.dp_lc_auto_start = 0.\n        self.dp_lc_auto_start_in = 0.\n        self.dp_lc_auto_torque_end = 0.\n        self.dp_torque_apply = False\n\n      # LaneChangeState.off\n      if self.lane_change_state == LaneChangeState.off and one_blinker and not self.prev_one_blinker and not below_lane_change_speed:\n        self.lane_change_state = LaneChangeState.preLaneChange\n        self.lane_change_ll_prob = 1.0\n\n      # LaneChangeState.preLaneChange\n      elif self.lane_change_state == LaneChangeState.preLaneChange:\n        # Set lane change direction\n        if sm['carState'].leftBlinker:\n          self.lane_change_direction = LaneChangeDirection.left\n        elif sm['carState'].rightBlinker:\n          self.lane_change_direction = LaneChangeDirection.right\n        else:  # If there are no blinkers we will go back to LaneChangeState.off\n          self.lane_change_direction = LaneChangeDirection.none\n\n        torque_applied = sm['carState'].steeringPressed and \\\n                        ((sm['carState'].steeringTorque > 0 and self.lane_change_direction == LaneChangeDirection.left) or\n                          (sm['carState'].steeringTorque < 0 and self.lane_change_direction == LaneChangeDirection.right))\n\n        blindspot_detected = ((sm['carState'].leftBlindspot and self.lane_change_direction == LaneChangeDirection.left) or\n                              (sm['carState'].rightBlindspot and self.lane_change_direction == LaneChangeDirection.right))\n\n        # if human made lane change prior alca, we should stop alca until new blinker (off -> on)\n        self.dp_lc_auto_start = self.dp_lc_auto_torque_end if torque_applied else self.dp_lc_auto_start\n        torque_applied = self.dp_torque_apply if self.dp_torque_apply else torque_applied\n        if not one_blinker or below_lane_change_speed:\n          self.lane_change_state = LaneChangeState.off\n        elif torque_applied and not blindspot_detected:\n          self.lane_change_state = LaneChangeState.laneChangeStarting\n\n      # LaneChangeState.laneChangeStarting\n      elif self.lane_change_state == LaneChangeState.laneChangeStarting:\n        # fade out over .5s\n        self.lane_change_ll_prob = max(self.lane_change_ll_prob - 2*DT_MDL, 0.0)\n\n        # 98% certainty\n        lane_change_prob = self.LP.l_lane_change_prob + self.LP.r_lane_change_prob\n        if lane_change_prob < 0.02 and self.lane_change_ll_prob < 0.01:\n          self.lane_change_state = LaneChangeState.laneChangeFinishing\n\n      # LaneChangeState.laneChangeFinishing\n      elif self.lane_change_state == LaneChangeState.laneChangeFinishing:\n        # fade in laneline over 1s\n        self.lane_change_ll_prob = min(self.lane_change_ll_prob + DT_MDL, 1.0)\n        if one_blinker and self.lane_change_ll_prob > 0.99:\n          self.lane_change_state = LaneChangeState.preLaneChange\n        elif self.lane_change_ll_prob > 0.99:\n          self.lane_change_state = LaneChangeState.off\n\n    if self.lane_change_state in [LaneChangeState.off, LaneChangeState.preLaneChange]:\n      self.lane_change_timer = 0.0\n    else:\n      self.lane_change_timer += DT_MDL\n\n    self.prev_one_blinker = one_blinker\n\n    self.desire = DESIRES[self.lane_change_direction][self.lane_change_state]\n\n    # Send keep pulse once per second during LaneChangeStart.preLaneChange\n    if self.lane_change_state in [LaneChangeState.off, LaneChangeState.laneChangeStarting]:\n      self.keep_pulse_timer = 0.0\n    elif self.lane_change_state == LaneChangeState.preLaneChange:\n      self.keep_pulse_timer += DT_MDL\n      if self.keep_pulse_timer > 1.0:\n        self.keep_pulse_timer = 0.0\n      elif self.desire in [log.LateralPlan.Desire.keepLeft, log.LateralPlan.Desire.keepRight]:\n        self.desire = log.LateralPlan.Desire.none\n\n    # Turn off lanes during lane change\n    if self.desire == log.LateralPlan.Desire.laneChangeRight or self.desire == log.LateralPlan.Desire.laneChangeLeft:\n      self.LP.lll_prob *= self.lane_change_ll_prob\n      self.LP.rll_prob *= self.lane_change_ll_prob\n    self.d_path_w_lines_xyz = self.LP.get_d_path(v_ego, self.t_idxs, self.path_xyz)\n    if self.use_lanelines:\n      d_path_xyz = self.d_path_w_lines_xyz\n      self.libmpc.set_weights(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, CP.steerRateCost)\n      self.laneless_mode_status = False\n    elif self.laneless_mode == 0:\n      d_path_xyz = self.LP.get_d_path(v_ego, self.t_idxs, self.path_xyz)\n      self.libmpc.set_weights(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, CP.steerRateCost)\n      self.laneless_mode_status = False\n    elif self.laneless_mode == 1:\n      d_path_xyz = self.path_xyz\n      path_cost = np.clip(abs(self.path_xyz[0,1]/self.path_xyz_stds[0,1]), 0.5, 5.0) * MPC_COST_LAT.PATH\n      # Heading cost is useful at low speed, otherwise end of plan can be off-heading\n      heading_cost = interp(v_ego, [5.0, 10.0], [MPC_COST_LAT.HEADING, 0.0])\n      self.libmpc.set_weights(path_cost, heading_cost, CP.steerRateCost)\n      self.laneless_mode_status = True\n    elif self.laneless_mode == 2 and ((self.LP.lll_prob + self.LP.rll_prob)/2 < 0.3) and self.lane_change_state == LaneChangeState.off:\n      d_path_xyz = self.path_xyz\n      path_cost = np.clip(abs(self.path_xyz[0,1]/self.path_xyz_stds[0,1]), 0.5, 5.0) * MPC_COST_LAT.PATH\n      # Heading cost is useful at low speed, otherwise end of plan can be off-heading\n      heading_cost = interp(v_ego, [5.0, 10.0], [MPC_COST_LAT.HEADING, 0.0])\n      self.libmpc.set_weights(path_cost, heading_cost, CP.steerRateCost)\n      self.laneless_mode_status = True\n      self.laneless_mode_status_buffer = True\n    elif self.laneless_mode == 2 and ((self.LP.lll_prob + self.LP.rll_prob)/2 > 0.5) and \\\n     self.laneless_mode_status_buffer and self.lane_change_state == LaneChangeState.off:\n      d_path_xyz = self.LP.get_d_path(v_ego, self.t_idxs, self.path_xyz)\n      self.libmpc.set_weights(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, CP.steerRateCost)\n      self.laneless_mode_status = False\n      self.laneless_mode_status_buffer = False\n    elif self.laneless_mode == 2 and self.laneless_mode_status_buffer == True and self.lane_change_state == LaneChangeState.off:\n      d_path_xyz = self.path_xyz\n      path_cost = np.clip(abs(self.path_xyz[0,1]/self.path_xyz_stds[0,1]), 0.5, 5.0) * MPC_COST_LAT.PATH\n      # Heading cost is useful at low speed, otherwise end of plan can be off-heading\n      heading_cost = interp(v_ego, [5.0, 10.0], [MPC_COST_LAT.HEADING, 0.0])\n      self.libmpc.set_weights(path_cost, heading_cost, CP.steerRateCost)\n      self.laneless_mode_status = True\n    else:\n      d_path_xyz = self.LP.get_d_path(v_ego, self.t_idxs, self.path_xyz)\n      self.libmpc.set_weights(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, CP.steerRateCost)\n      self.laneless_mode_status = False\n      self.laneless_mode_status_buffer = False\n\n    y_pts = np.interp(v_ego * self.t_idxs[:LAT_MPC_N + 1], np.linalg.norm(d_path_xyz, axis=1), d_path_xyz[:,1])\n    heading_pts = np.interp(v_ego * self.t_idxs[:LAT_MPC_N + 1], np.linalg.norm(self.path_xyz, axis=1), self.plan_yaw)\n    self.y_pts = y_pts\n\n    assert len(y_pts) == LAT_MPC_N + 1\n    assert len(heading_pts) == LAT_MPC_N + 1\n    # for now CAR_ROTATION_RADIUS is disabled\n    # to use it, enable it in the MPC\n    assert abs(CAR_ROTATION_RADIUS) < 1e-3\n    self.libmpc.run_mpc(self.cur_state, self.mpc_solution,\n                        float(v_ego),\n                        CAR_ROTATION_RADIUS,\n                        list(y_pts),\n                        list(heading_pts))\n    # init state for next\n    self.cur_state.x = 0.0\n    self.cur_state.y = 0.0\n    self.cur_state.psi = 0.0\n    self.cur_state.curvature = interp(DT_MDL, self.t_idxs[:LAT_MPC_N + 1], self.mpc_solution.curvature)\n\n    #  Check for infeasable MPC solution\n    mpc_nans = any(math.isnan(x) for x in self.mpc_solution.curvature)\n    t = sec_since_boot()\n    if mpc_nans:\n      self.libmpc.init()\n      self.cur_state.curvature = measured_curvature\n\n      if t > self.last_cloudlog_t + 5.0:\n        self.last_cloudlog_t = t\n        cloudlog.warning(\"Lateral mpc - nan: True\")\n\n    if self.mpc_solution[0].cost > 20000. or mpc_nans:   # TODO: find a better way to detect when MPC did not converge\n      self.solution_invalid_cnt += 1\n    else:\n      self.solution_invalid_cnt = 0\n\n  def publish(self, sm, pm):\n    plan_solution_valid = self.solution_invalid_cnt < 2\n    plan_send = messaging.new_message('lateralPlan')\n    plan_send.valid = sm.all_alive_and_valid(service_list=['carState', 'controlsState', 'modelV2', 'dragonConf'])\n    plan_send.lateralPlan.laneWidth = float(self.LP.lane_width)\n    plan_send.lateralPlan.dPathPoints = [float(x) for x in self.y_pts]\n    plan_send.lateralPlan.psis = [float(x) for x in self.mpc_solution.psi[0:CONTROL_N]]\n    plan_send.lateralPlan.curvatures = [float(x) for x in self.mpc_solution.curvature[0:CONTROL_N]]\n    plan_send.lateralPlan.curvatureRates = [float(x) for x in self.mpc_solution.curvature_rate[0:CONTROL_N-1]] +[0.0]\n    plan_send.lateralPlan.lProb = float(self.LP.lll_prob)\n    plan_send.lateralPlan.rProb = float(self.LP.rll_prob)\n    plan_send.lateralPlan.dProb = float(self.LP.d_prob)\n\n    plan_send.lateralPlan.mpcSolutionValid = bool(plan_solution_valid)\n\n    plan_send.lateralPlan.desire = self.desire\n    plan_send.lateralPlan.laneChangeState = self.lane_change_state\n    plan_send.lateralPlan.laneChangeDirection = self.lane_change_direction\n    plan_send.lateralPlan.dpALCAStartIn = self.dp_lc_auto_start_in\n\n    plan_send.lateralPlan.dPathWLinesX = [float(x) for x in self.d_path_w_lines_xyz[:, 0]]\n    plan_send.lateralPlan.dPathWLinesY = [float(y) for y in self.d_path_w_lines_xyz[:, 1]]\n\n    plan_send.lateralPlan.dpLaneLessModeStatus = bool(self.laneless_mode_status)\n\n    plan_send.lateralPlan.dPathWLinesX = [float(x) for x in self.d_path_w_lines_xyz[:, 0]]\n    plan_send.lateralPlan.dPathWLinesY = [float(y) for y in self.d_path_w_lines_xyz[:, 1]]\n\n    pm.send('lateralPlan', plan_send)\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc.py",
    "content": "import math\nimport numpy as np\nfrom common.numpy_fast import interp\nfrom common.realtime import sec_since_boot\nfrom selfdrive.modeld.constants import T_IDXS\nfrom selfdrive.controls.lib.radar_helpers import _LEAD_ACCEL_TAU\nfrom selfdrive.controls.lib.lead_mpc_lib import libmpc_py\nfrom selfdrive.controls.lib.drive_helpers import MPC_COST_LONG, CONTROL_N\nfrom selfdrive.swaglog import cloudlog\n\nMPC_T = list(np.arange(0,1.,.2)) + list(np.arange(1.,10.6,.6))\n\n\nclass LeadMpc():\n  def __init__(self, mpc_id):\n    self.lead_id = mpc_id\n\n    self.reset_mpc()\n    self.prev_lead_status = False\n    self.prev_lead_x = 0.0\n    self.new_lead = False\n\n    self.last_cloudlog_t = 0.0\n    self.n_its = 0\n    self.duration = 0\n    self.status = False\n\n    self.v_solution = np.zeros(CONTROL_N)\n    self.a_solution = np.zeros(CONTROL_N)\n    self.j_solution = np.zeros(CONTROL_N)\n\n    # dp\n    self.following_distance = 1.8\n    self.following_distance_last = None\n\n  def set_following_distance(self, following_distance):\n    self.following_distance = following_distance\n    if self.following_distance != self.following_distance_last:\n      self.reset_mpc()\n    self.following_distance_last = self.following_distance\n\n  def reset_mpc(self):\n    ffi, self.libmpc = libmpc_py.get_libmpc(self.lead_id)\n    self.libmpc.init(MPC_COST_LONG.TTC, MPC_COST_LONG.DISTANCE,\n                     MPC_COST_LONG.ACCELERATION, MPC_COST_LONG.JERK)\n\n    self.mpc_solution = ffi.new(\"log_t *\")\n    self.cur_state = ffi.new(\"state_t *\")\n    self.cur_state[0].v_ego = 0\n    self.cur_state[0].a_ego = 0\n    self.a_lead_tau = _LEAD_ACCEL_TAU\n\n  def set_cur_state(self, v, a):\n    v_safe = max(v, 1e-3)\n    a_safe = a\n    self.cur_state[0].v_ego = v_safe\n    self.cur_state[0].a_ego = a_safe\n\n  def update(self, CS, radarstate, v_cruise, a_target, active):\n    v_ego = CS.vEgo\n    if self.lead_id == 0:\n      lead = radarstate.leadOne\n    else:\n      lead = radarstate.leadTwo\n    self.status = lead.status\n\n    # Setup current mpc state\n    self.cur_state[0].x_ego = 0.0\n\n    if lead is not None and lead.status:\n      x_lead = lead.dRel\n      v_lead = max(0.0, lead.vLead)\n      a_lead = lead.aLeadK\n\n      if (v_lead < 0.1 or -a_lead / 2.0 > v_lead):\n        v_lead = 0.0\n        a_lead = 0.0\n\n      self.a_lead_tau = lead.aLeadTau\n      self.new_lead = False\n      if not self.prev_lead_status or abs(x_lead - self.prev_lead_x) > 2.5:\n        self.libmpc.init_with_simulation(v_ego, x_lead, v_lead, a_lead, self.a_lead_tau)\n        self.new_lead = True\n\n      self.prev_lead_status = True\n      self.prev_lead_x = x_lead\n      self.cur_state[0].x_l = x_lead\n      self.cur_state[0].v_l = v_lead\n    else:\n      self.prev_lead_status = False\n      # Fake a fast lead car, so mpc keeps running\n      self.cur_state[0].x_l = 50.0\n      self.cur_state[0].v_l = v_ego + 10.0\n      a_lead = 0.0\n      self.a_lead_tau = _LEAD_ACCEL_TAU\n\n    # Calculate mpc\n    t = sec_since_boot()\n    self.n_its = self.libmpc.run_mpc(self.cur_state, self.mpc_solution, self.a_lead_tau, a_lead, self.following_distance)\n    self.v_solution = interp(T_IDXS[:CONTROL_N], MPC_T, self.mpc_solution.v_ego)\n    self.a_solution = interp(T_IDXS[:CONTROL_N], MPC_T, self.mpc_solution.a_ego)\n    self.j_solution = interp(T_IDXS[:CONTROL_N], MPC_T[:-1], self.mpc_solution.j_ego)\n    self.duration = int((sec_since_boot() - t) * 1e9)\n\n    # Reset if NaN or goes through lead car\n    crashing = any(lead - ego < -50 for (lead, ego) in zip(self.mpc_solution[0].x_l, self.mpc_solution[0].x_ego))\n    nans = any(math.isnan(x) for x in self.mpc_solution[0].v_ego)\n    backwards = min(self.mpc_solution[0].v_ego) < -0.15\n\n    if ((backwards or crashing) and self.prev_lead_status) or nans:\n      if t > self.last_cloudlog_t + 5.0:\n        self.last_cloudlog_t = t\n        cloudlog.warning(\"Longitudinal mpc %d reset - backwards: %s crashing: %s nan: %s\" % (\n                          self.lead_id, backwards, crashing, nans))\n\n      self.libmpc.init(MPC_COST_LONG.TTC, MPC_COST_LONG.DISTANCE,\n                       MPC_COST_LONG.ACCELERATION, MPC_COST_LONG.JERK)\n      self.cur_state[0].v_ego = v_ego\n      self.cur_state[0].a_ego = 0.0\n      self.a_mpc = CS.aEgo\n      self.prev_lead_status = False\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/.gitignore",
    "content": "generator\nlib_qp/\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/SConscript",
    "content": "Import('env', 'arch')\n\n\ncpp_path = [\n    \"#phonelibs/acado/include\",\n    \"#phonelibs/acado/include/acado\",\n    \"#phonelibs/qpoases/INCLUDE\",\n    \"#phonelibs/qpoases/INCLUDE/EXTRAS\",\n    \"#phonelibs/qpoases/SRC/\",\n    \"#phonelibs/qpoases\",\n    \"lib_mpc_export\",\n]\n\ngenerated_c = [\n    'lib_mpc_export/acado_auxiliary_functions.c',\n    'lib_mpc_export/acado_qpoases_interface.cpp',\n    'lib_mpc_export/acado_integrator.c',\n    'lib_mpc_export/acado_solver.c',\n]\n\ngenerated_h = [\n    'lib_mpc_export/acado_common.h',\n    'lib_mpc_export/acado_auxiliary_functions.h',\n    'lib_mpc_export/acado_qpoases_interface.hpp',\n]\n\n\ninterface_dir = Dir('lib_mpc_export')\n\nSConscript(['#phonelibs/qpoases/SConscript'], variant_dir='lib_qp', exports=['interface_dir'])\n\nif GetOption('mpc_generate'):\n    generator_cpp = File('generator.cpp')\n\n    acado_libs = [File(f\"#phonelibs/acado/{arch}/lib/libacado_toolkit.a\"),\n                  File(f\"#phonelibs/acado/{arch}/lib/libacado_casadi.a\"),\n                  File(f\"#phonelibs/acado/{arch}/lib/libacado_csparse.a\")]\n\n    generator = env.Program('generator', generator_cpp, LIBS=acado_libs, CPPPATH=cpp_path,\n                            CCFLAGS=env['CCFLAGS'] + [\"-Wno-deprecated\", \"-Wno-overloaded-shift-op-parentheses\"])\n\n    cmd = f\"cd {Dir('.').get_abspath()} && {generator[0].get_abspath()}\"\n    env.Command(generated_c + generated_h, generator, cmd)\n\n\nmpc_files = [\"longitudinal_mpc.c\"] + generated_c\nenv.SharedLibrary('mpc0', mpc_files, LIBS=['m', 'qpoases'], LIBPATH=['lib_qp'], CPPPATH=cpp_path)\nenv.SharedLibrary('mpc1', mpc_files, LIBS=['m', 'qpoases'], LIBPATH=['lib_qp'], CPPPATH=cpp_path)\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/generator.cpp",
    "content": "#include <acado_code_generation.hpp>\n\nconst int controlHorizon = 50;\n\nusing namespace std;\n\n#define G 9.81\n#define TR 1.8\n\n#define RW(v_ego, v_l) (v_ego * TR - (v_l - v_ego) * TR + v_ego*v_ego/(2*G) - v_l*v_l / (2*G))\n#define NORM_RW_ERROR(v_ego, v_l, p) ((RW(v_ego, v_l) + 4.0 - p)/(sqrt(v_ego + 0.5) + 0.1))\n\nint main( )\n{\n  USING_NAMESPACE_ACADO\n\n\n  DifferentialEquation f;\n\n  DifferentialState x_ego, v_ego, a_ego;\n  OnlineData x_l, v_l;\n\n  Control j_ego;\n\n  auto desired = 4.0 + RW(v_ego, v_l);\n  auto d_l = x_l - x_ego;\n\n  // Equations of motion\n  f << dot(x_ego) == v_ego;\n  f << dot(v_ego) == a_ego;\n  f << dot(a_ego) == j_ego;\n\n  // Running cost\n  Function h;\n  h << exp(0.3 * NORM_RW_ERROR(v_ego, v_l, d_l)) - 1;\n  h << (d_l - desired) / (0.05 * v_ego + 0.5);\n  h << a_ego * (0.1 * v_ego + 1.0);\n  h << j_ego * (0.1 * v_ego + 1.0);\n\n  // Weights are defined in mpc.\n  BMatrix Q(4,4); Q.setAll(true);\n\n  // Terminal cost\n  Function hN;\n  hN << exp(0.3 * NORM_RW_ERROR(v_ego, v_l, d_l)) - 1;\n  hN << (d_l - desired) / (0.05 * v_ego + 0.5);\n  hN << a_ego * (0.1 * v_ego + 1.0);\n\n  // Weights are defined in mpc.\n  BMatrix QN(3,3); QN.setAll(true);\n\n  // Non uniform time grid\n  // First 5 timesteps are 0.2, after that it's 0.6\n  DMatrix numSteps(20, 1);\n  for (int i = 0; i < 5; i++){\n    numSteps(i) = 1;\n  }\n  for (int i = 5; i < 20; i++){\n    numSteps(i) = 3;\n  }\n\n  // Setup Optimal Control Problem\n  const double tStart = 0.0;\n  const double tEnd   = 10.0;\n\n  OCP ocp( tStart, tEnd, numSteps);\n  ocp.subjectTo(f);\n\n  ocp.minimizeLSQ(Q, h);\n  ocp.minimizeLSQEndTerm(QN, hN);\n\n  ocp.subjectTo( -0.1 <= v_ego);\n  ocp.setNOD(2);\n\n  OCPexport mpc(ocp);\n  mpc.set( HESSIAN_APPROXIMATION, GAUSS_NEWTON );\n  mpc.set( DISCRETIZATION_TYPE, MULTIPLE_SHOOTING );\n  mpc.set( INTEGRATOR_TYPE, INT_RK4 );\n  mpc.set( NUM_INTEGRATOR_STEPS, controlHorizon);\n  mpc.set( MAX_NUM_QP_ITERATIONS, 50);\n  mpc.set( CG_USE_VARIABLE_WEIGHTING_MATRIX, YES);\n\n  mpc.set( SPARSE_QP_SOLUTION, CONDENSING );\n  mpc.set( QP_SOLVER, QP_QPOASES );\n  mpc.set( HOTSTART_QP, YES );\n  mpc.set( GENERATE_TEST_FILE, NO);\n  mpc.set( GENERATE_MAKE_FILE, NO );\n  mpc.set( GENERATE_MATLAB_INTERFACE, NO );\n  mpc.set( GENERATE_SIMULINK_INTERFACE, NO );\n\n  if (mpc.exportCode( \"lib_mpc_export\" ) != SUCCESSFUL_RETURN)\n    exit( EXIT_FAILURE );\n\n  mpc.printDimensionsQP( );\n\n  return EXIT_SUCCESS;\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_auxiliary_functions.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_auxiliary_functions.h\"\n\n#include <stdio.h>\n\nreal_t* acado_getVariablesX( )\n{\n\treturn acadoVariables.x;\n}\n\nreal_t* acado_getVariablesU( )\n{\n\treturn acadoVariables.u;\n}\n\n#if ACADO_NY > 0\nreal_t* acado_getVariablesY( )\n{\n\treturn acadoVariables.y;\n}\n#endif\n\n#if ACADO_NYN > 0\nreal_t* acado_getVariablesYN( )\n{\n\treturn acadoVariables.yN;\n}\n#endif\n\nreal_t* acado_getVariablesX0( )\n{\n#if ACADO_INITIAL_VALUE_FIXED\n\treturn acadoVariables.x0;\n#else\n\treturn 0;\n#endif\n}\n\n/** Print differential variables. */\nvoid acado_printDifferentialVariables( )\n{\n\tint i, j;\n\tprintf(\"\\nDifferential variables:\\n[\\n\");\n\tfor (i = 0; i < ACADO_N + 1; ++i)\n\t{\n\t\tfor (j = 0; j < ACADO_NX; ++j)\n\t\t\tprintf(\"\\t%e\", acadoVariables.x[i * ACADO_NX + j]);\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"]\\n\\n\");\n}\n\n/** Print control variables. */\nvoid acado_printControlVariables( )\n{\n\tint i, j;\n\tprintf(\"\\nControl variables:\\n[\\n\");\n\tfor (i = 0; i < ACADO_N; ++i)\n\t{\n\t\tfor (j = 0; j < ACADO_NU; ++j)\n\t\t\tprintf(\"\\t%e\", acadoVariables.u[i * ACADO_NU + j]);\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"]\\n\\n\");\n}\n\n/** Print ACADO code generation notice. */\nvoid acado_printHeader( )\n{\n\tprintf(\n\t\t\"\\nACADO Toolkit -- A Toolkit for Automatic Control and Dynamic Optimization.\\n\"\n\t\t\"Copyright (C) 2008-2015 by Boris Houska, Hans Joachim Ferreau,\\n\" \n\t\t\"Milan Vukov and Rien Quirynen, KU Leuven.\\n\"\n\t);\n\t\n\tprintf(\n\t\t\"Developed within the Optimization in Engineering Center (OPTEC) under\\n\"\n\t\t\"supervision of Moritz Diehl. All rights reserved.\\n\\n\"\n\t\t\"ACADO Toolkit is distributed under the terms of the GNU Lesser\\n\"\n\t\t\"General Public License 3 in the hope that it will be useful,\\n\"\n\t\t\"but WITHOUT ANY WARRANTY; without even the implied warranty of\\n\"\n\t\t\"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\\n\"\n\t\t\"GNU Lesser General Public License for more details.\\n\\n\"\n\t);\n}\n\n#if !(defined _DSPACE)\n#if (defined _WIN32 || defined _WIN64) && !(defined __MINGW32__ || defined __MINGW64__)\n\nvoid acado_tic( acado_timer* t )\n{\n\tQueryPerformanceFrequency(&t->freq);\n\tQueryPerformanceCounter(&t->tic);\n}\n\nreal_t acado_toc( acado_timer* t )\n{\n\tQueryPerformanceCounter(&t->toc);\n\treturn ((t->toc.QuadPart - t->tic.QuadPart) / (real_t)t->freq.QuadPart);\n}\n\n\n#elif (defined __APPLE__)\n\nvoid acado_tic( acado_timer* t )\n{\n    /* read current clock cycles */\n    t->tic = mach_absolute_time();\n}\n\nreal_t acado_toc( acado_timer* t )\n{\n\n    uint64_t duration; /* elapsed time in clock cycles*/\n    \n    t->toc = mach_absolute_time();\n    duration = t->toc - t->tic;\n    \n    /*conversion from clock cycles to nanoseconds*/\n    mach_timebase_info(&(t->tinfo));\n    duration *= t->tinfo.numer;\n    duration /= t->tinfo.denom;\n\n    return (real_t)duration / 1e9;\n}\n\n#else\n\n#if __STDC_VERSION__ >= 199901L\n/* C99 mode */\n\n/* read current time */\nvoid acado_tic( acado_timer* t )\n{\n\tgettimeofday(&t->tic, 0);\n}\n\n/* return time passed since last call to tic on this timer */\nreal_t acado_toc( acado_timer* t )\n{\n\tstruct timeval temp;\n\t\n\tgettimeofday(&t->toc, 0);\n    \n\tif ((t->toc.tv_usec - t->tic.tv_usec) < 0)\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec - 1;\n\t\ttemp.tv_usec = 1000000 + t->toc.tv_usec - t->tic.tv_usec;\n\t}\n\telse\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec;\n\t\ttemp.tv_usec = t->toc.tv_usec - t->tic.tv_usec;\n\t}\n\t\n\treturn (real_t)temp.tv_sec + (real_t)temp.tv_usec / 1e6;\n}\n\n#else\n/* ANSI */\n\n/* read current time */\nvoid acado_tic( acado_timer* t )\n{\n\tclock_gettime(CLOCK_MONOTONIC, &t->tic);\n}\n\n\n/* return time passed since last call to tic on this timer */\nreal_t acado_toc( acado_timer* t )\n{\n\tstruct timespec temp;\n    \n\tclock_gettime(CLOCK_MONOTONIC, &t->toc);\t\n    \n\tif ((t->toc.tv_nsec - t->tic.tv_nsec) < 0)\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec - 1;\n\t\ttemp.tv_nsec = 1000000000+t->toc.tv_nsec - t->tic.tv_nsec;\n\t}\n\telse\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec;\n\t\ttemp.tv_nsec = t->toc.tv_nsec - t->tic.tv_nsec;\n\t}\n\t\n\treturn (real_t)temp.tv_sec + (real_t)temp.tv_nsec / 1e9;\n}\n\n#endif /* __STDC_VERSION__ >= 199901L */\n\n#endif /* (defined _WIN32 || _WIN64) */\n\n#endif\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_auxiliary_functions.h",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef ACADO_AUXILIARY_FUNCTIONS_H\n#define ACADO_AUXILIARY_FUNCTIONS_H\n\n#include \"acado_common.h\"\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n/** Get pointer to the matrix with differential variables. */\nreal_t* acado_getVariablesX( );\n\n/** Get pointer to the matrix with control variables. */\nreal_t* acado_getVariablesU( );\n\n#if ACADO_NY > 0\n/** Get pointer to the matrix with references/measurements. */\nreal_t* acado_getVariablesY( );\n#endif\n\n#if ACADO_NYN > 0\n/** Get pointer to the vector with references/measurement on the last node. */\nreal_t* acado_getVariablesYN( );\n#endif\n\n/** Get pointer to the current state feedback vector. Only applicable for NMPC. */\nreal_t* acado_getVariablesX0( );\n\n/** Print differential variables. */\nvoid acado_printDifferentialVariables( );\n\n/** Print control variables. */\nvoid acado_printControlVariables( );\n\n/** Print ACADO code generation notice. */\nvoid acado_printHeader( );\n\n/*\n * A huge thanks goes to Alexander Domahidi from ETHZ, Switzerland, for \n * providing us with the following timing routines.\n */\n\n#if !(defined _DSPACE)\n#if (defined _WIN32 || defined _WIN64) && !(defined __MINGW32__ || defined __MINGW64__)\n\n/* Use Windows QueryPerformanceCounter for timing. */\n#include <Windows.h>\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tLARGE_INTEGER tic;\n\tLARGE_INTEGER toc;\n\tLARGE_INTEGER freq;\n} acado_timer;\n\n\n#elif (defined __APPLE__)\n\n#include \"unistd.h\"\n#include <mach/mach_time.h>\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tuint64_t tic;\n\tuint64_t toc;\n\tmach_timebase_info_data_t tinfo;\n} acado_timer;\n\n#else\n\n/* Use POSIX clock_gettime() for timing on non-Windows machines. */\n#include <time.h>\n\n#if __STDC_VERSION__ >= 199901L\n/* C99 mode of operation. */\n\n#include <sys/stat.h>\n#include <sys/time.h>\n\ntypedef struct acado_timer_\n{\n\tstruct timeval tic;\n\tstruct timeval toc;\n} acado_timer;\n\n#else\n/* ANSI C */\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tstruct timespec tic;\n\tstruct timespec toc;\n} acado_timer;\n\n#endif /* __STDC_VERSION__ >= 199901L */\n\n#endif /* (defined _WIN32 || defined _WIN64) */\n\n/** A function for measurement of the current time. */\nvoid acado_tic( acado_timer* t );\n\n/** A function which returns the elapsed time. */\nreal_t acado_toc( acado_timer* t );\n\n#endif\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\n} /* extern \"C\" */\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n#endif /* ACADO_AUXILIARY_FUNCTIONS_H */\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_common.h",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef ACADO_COMMON_H\n#define ACADO_COMMON_H\n\n#include <math.h>\n#include <string.h>\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n/** \\defgroup ACADO ACADO CGT generated module. */\n/** @{ */\n\n/** qpOASES QP solver indicator. */\n#define ACADO_QPOASES  0\n#define ACADO_QPOASES3 1\n/** FORCES QP solver indicator.*/\n#define ACADO_FORCES   2\n/** qpDUNES QP solver indicator.*/\n#define ACADO_QPDUNES  3\n/** HPMPC QP solver indicator. */\n#define ACADO_HPMPC    4\n#define ACADO_GENERIC    5\n\n/** Indicator for determining the QP solver used by the ACADO solver code. */\n#define ACADO_QP_SOLVER ACADO_QPOASES\n\n#include \"acado_qpoases_interface.hpp\"\n\n\n/*\n * Common definitions\n */\n/** User defined block based condensing. */\n#define ACADO_BLOCK_CONDENSING 0\n/** Compute covariance matrix of the last state estimate. */\n#define ACADO_COMPUTE_COVARIANCE_MATRIX 0\n/** Flag indicating whether constraint values are hard-coded or not. */\n#define ACADO_HARDCODED_CONSTRAINT_VALUES 1\n/** Indicator for fixed initial state. */\n#define ACADO_INITIAL_STATE_FIXED 1\n/** Number of control/estimation intervals. */\n#define ACADO_N 20\n/** Number of online data values. */\n#define ACADO_NOD 2\n/** Number of path constraints. */\n#define ACADO_NPAC 0\n/** Number of control variables. */\n#define ACADO_NU 1\n/** Number of differential variables. */\n#define ACADO_NX 3\n/** Number of algebraic variables. */\n#define ACADO_NXA 0\n/** Number of differential derivative variables. */\n#define ACADO_NXD 0\n/** Number of references/measurements per node on the first N nodes. */\n#define ACADO_NY 4\n/** Number of references/measurements on the last (N + 1)st node. */\n#define ACADO_NYN 3\n/** Total number of QP optimization variables. */\n#define ACADO_QP_NV 23\n/** Number of Runge-Kutta stages per integration step. */\n#define ACADO_RK_NSTAGES 4\n/** Providing interface for arrival cost. */\n#define ACADO_USE_ARRIVAL_COST 0\n/** Indicator for usage of non-hard-coded linear terms in the objective. */\n#define ACADO_USE_LINEAR_TERMS 0\n/** Indicator for type of fixed weighting matrices. */\n#define ACADO_WEIGHTING_MATRICES_TYPE 2\n\n\n/*\n * Globally used structure definitions\n */\n\n/** The structure containing the user data.\n * \n *  Via this structure the user \"communicates\" with the solver code.\n */\ntypedef struct ACADOvariables_\n{\nint dummy;\n/** Matrix of size: 21 x 3 (row major format)\n * \n *  Matrix containing 21 differential variable vectors.\n */\nreal_t x[ 63 ];\n\n/** Column vector of size: 20\n * \n *  Matrix containing 20 control variable vectors.\n */\nreal_t u[ 20 ];\n\n/** Matrix of size: 21 x 2 (row major format)\n * \n *  Matrix containing 21 online data vectors.\n */\nreal_t od[ 42 ];\n\n/** Column vector of size: 80\n * \n *  Matrix containing 20 reference/measurement vectors of size 4 for first 20 nodes.\n */\nreal_t y[ 80 ];\n\n/** Column vector of size: 3\n * \n *  Reference/measurement vector for the 21. node.\n */\nreal_t yN[ 3 ];\n\n/** Matrix of size: 80 x 4 (row major format) */\nreal_t W[ 320 ];\n\n/** Matrix of size: 3 x 3 (row major format) */\nreal_t WN[ 9 ];\n\n/** Column vector of size: 3\n * \n *  Current state feedback vector.\n */\nreal_t x0[ 3 ];\n\n\n} ACADOvariables;\n\n/** Private workspace used by the auto-generated code.\n * \n *  Data members of this structure are private to the solver.\n *  In other words, the user code should not modify values of this \n *  structure. \n */\ntypedef struct ACADOworkspace_\n{\nreal_t rk_ttt;\n\n/** Row vector of size: 18 */\nreal_t rk_xxx[ 18 ];\n\n/** Matrix of size: 4 x 15 (row major format) */\nreal_t rk_kkk[ 60 ];\n\n/** Row vector of size: 18 */\nreal_t state[ 18 ];\n\n/** Column vector of size: 60 */\nreal_t d[ 60 ];\n\n/** Column vector of size: 80 */\nreal_t Dy[ 80 ];\n\n/** Column vector of size: 3 */\nreal_t DyN[ 3 ];\n\n/** Matrix of size: 60 x 3 (row major format) */\nreal_t evGx[ 180 ];\n\n/** Column vector of size: 60 */\nreal_t evGu[ 60 ];\n\n/** Column vector of size: 13 */\nreal_t objAuxVar[ 13 ];\n\n/** Row vector of size: 6 */\nreal_t objValueIn[ 6 ];\n\n/** Row vector of size: 20 */\nreal_t objValueOut[ 20 ];\n\n/** Matrix of size: 60 x 3 (row major format) */\nreal_t Q1[ 180 ];\n\n/** Matrix of size: 60 x 4 (row major format) */\nreal_t Q2[ 240 ];\n\n/** Column vector of size: 20 */\nreal_t R1[ 20 ];\n\n/** Matrix of size: 20 x 4 (row major format) */\nreal_t R2[ 80 ];\n\n/** Column vector of size: 60 */\nreal_t S1[ 60 ];\n\n/** Matrix of size: 3 x 3 (row major format) */\nreal_t QN1[ 9 ];\n\n/** Matrix of size: 3 x 3 (row major format) */\nreal_t QN2[ 9 ];\n\n/** Column vector of size: 3 */\nreal_t Dx0[ 3 ];\n\n/** Matrix of size: 3 x 3 (row major format) */\nreal_t T[ 9 ];\n\n/** Column vector of size: 630 */\nreal_t E[ 630 ];\n\n/** Column vector of size: 630 */\nreal_t QE[ 630 ];\n\n/** Matrix of size: 60 x 3 (row major format) */\nreal_t QGx[ 180 ];\n\n/** Column vector of size: 60 */\nreal_t Qd[ 60 ];\n\n/** Column vector of size: 63 */\nreal_t QDy[ 63 ];\n\n/** Matrix of size: 20 x 3 (row major format) */\nreal_t H10[ 60 ];\n\n/** Matrix of size: 23 x 23 (row major format) */\nreal_t H[ 529 ];\n\n/** Matrix of size: 20 x 23 (row major format) */\nreal_t A[ 460 ];\n\n/** Column vector of size: 23 */\nreal_t g[ 23 ];\n\n/** Column vector of size: 23 */\nreal_t lb[ 23 ];\n\n/** Column vector of size: 23 */\nreal_t ub[ 23 ];\n\n/** Column vector of size: 20 */\nreal_t lbA[ 20 ];\n\n/** Column vector of size: 20 */\nreal_t ubA[ 20 ];\n\n/** Column vector of size: 23 */\nreal_t x[ 23 ];\n\n/** Column vector of size: 43 */\nreal_t y[ 43 ];\n\n\n} ACADOworkspace;\n\n/* \n * Forward function declarations. \n */\n\n\n/** Performs the integration and sensitivity propagation for one shooting interval.\n *\n *  \\param rk_eta Working array to pass the input values and return the results.\n *  \\param resetIntegrator The internal memory of the integrator can be reset.\n *  \\param rk_index Number of the shooting interval.\n *\n *  \\return Status code of the integrator.\n */\nint acado_integrate( real_t* const rk_eta, int resetIntegrator, int rk_index );\n\n/** Export of an ACADO symbolic function.\n *\n *  \\param in Input to the exported function.\n *  \\param out Output of the exported function.\n */\nvoid acado_rhs_forw(const real_t* in, real_t* out);\n\n/** Preparation step of the RTI scheme.\n *\n *  \\return Status of the integration module. =0: OK, otherwise the error code.\n */\nint acado_preparationStep(  );\n\n/** Feedback/estimation step of the RTI scheme.\n *\n *  \\return Status code of the qpOASES QP solver.\n */\nint acado_feedbackStep(  );\n\n/** Solver initialization. Must be called once before any other function call.\n *\n *  \\return =0: OK, otherwise an error code of a QP solver.\n */\nint acado_initializeSolver(  );\n\n/** Initialize shooting nodes by a forward simulation starting from the first node.\n */\nvoid acado_initializeNodesByForwardSimulation(  );\n\n/** Shift differential variables vector by one interval.\n *\n *  \\param strategy Shifting strategy: 1. Initialize node 21 with xEnd. 2. Initialize node 21 by forward simulation.\n *  \\param xEnd Value for the x vector on the last node. If =0 the old value is used.\n *  \\param uEnd Value for the u vector on the second to last node. If =0 the old value is used.\n */\nvoid acado_shiftStates( int strategy, real_t* const xEnd, real_t* const uEnd );\n\n/** Shift controls vector by one interval.\n *\n *  \\param uEnd Value for the u vector on the second to last node. If =0 the old value is used.\n */\nvoid acado_shiftControls( real_t* const uEnd );\n\n/** Get the KKT tolerance of the current iterate.\n *\n *  \\return The KKT tolerance value.\n */\nreal_t acado_getKKT(  );\n\n/** Calculate the objective value.\n *\n *  \\return Value of the objective function.\n */\nreal_t acado_getObjective(  );\n\n\n/* \n * Extern declarations. \n */\n\nextern ACADOworkspace acadoWorkspace;\nextern ACADOvariables acadoVariables;\n\n/** @} */\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\n} /* extern \"C\" */\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n#endif /* ACADO_COMMON_H */\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_integrator.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_common.h\"\n\n\nvoid acado_rhs_forw(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 15;\n\n/* Compute outputs: */\nout[0] = xd[1];\nout[1] = xd[2];\nout[2] = u[0];\nout[3] = xd[6];\nout[4] = xd[7];\nout[5] = xd[8];\nout[6] = xd[9];\nout[7] = xd[10];\nout[8] = xd[11];\nout[9] = (real_t)(0.0000000000000000e+00);\nout[10] = (real_t)(0.0000000000000000e+00);\nout[11] = (real_t)(0.0000000000000000e+00);\nout[12] = xd[13];\nout[13] = xd[14];\nout[14] = (real_t)(1.0000000000000000e+00);\n}\n\n/* Fixed step size:0.2 */\nint acado_integrate( real_t* const rk_eta, int resetIntegrator, int rk_index )\n{\nint error;\n\nint run1;\nint numSteps[20] = {1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3};\nint numInts = numSteps[rk_index];\nacadoWorkspace.rk_ttt = 0.0000000000000000e+00;\nrk_eta[3] = 1.0000000000000000e+00;\nrk_eta[4] = 0.0000000000000000e+00;\nrk_eta[5] = 0.0000000000000000e+00;\nrk_eta[6] = 0.0000000000000000e+00;\nrk_eta[7] = 1.0000000000000000e+00;\nrk_eta[8] = 0.0000000000000000e+00;\nrk_eta[9] = 0.0000000000000000e+00;\nrk_eta[10] = 0.0000000000000000e+00;\nrk_eta[11] = 1.0000000000000000e+00;\nrk_eta[12] = 0.0000000000000000e+00;\nrk_eta[13] = 0.0000000000000000e+00;\nrk_eta[14] = 0.0000000000000000e+00;\nacadoWorkspace.rk_xxx[15] = rk_eta[15];\nacadoWorkspace.rk_xxx[16] = rk_eta[16];\nacadoWorkspace.rk_xxx[17] = rk_eta[17];\n\nfor (run1 = 0; run1 < 1; ++run1)\n{\nfor(run1 = 0; run1 < numInts; run1++ ) {\nacadoWorkspace.rk_xxx[0] = + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + rk_eta[14];\nacado_rhs_forw( acadoWorkspace.rk_xxx, acadoWorkspace.rk_kkk );\nacadoWorkspace.rk_xxx[0] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[0] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[1] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[2] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[3] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[4] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[5] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[6] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[7] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[8] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[9] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[10] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[11] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[12] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[13] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[14] + rk_eta[14];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 15 ]) );\nacadoWorkspace.rk_xxx[0] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[15] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[16] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[17] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[18] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[19] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[20] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[21] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[22] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[23] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[24] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[25] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[26] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[27] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[28] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)9.9999999999999964e-02*acadoWorkspace.rk_kkk[29] + rk_eta[14];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 30 ]) );\nacadoWorkspace.rk_xxx[0] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[30] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[31] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[32] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[33] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[34] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[35] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[36] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[37] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[38] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[39] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[40] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[41] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[42] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[43] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)1.9999999999999993e-01*acadoWorkspace.rk_kkk[44] + rk_eta[14];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 45 ]) );\nrk_eta[0] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[0] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[15] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[30] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[45];\nrk_eta[1] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[1] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[16] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[31] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[46];\nrk_eta[2] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[2] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[17] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[32] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[47];\nrk_eta[3] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[3] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[18] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[33] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[48];\nrk_eta[4] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[4] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[19] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[34] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[49];\nrk_eta[5] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[5] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[20] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[35] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[50];\nrk_eta[6] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[6] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[21] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[36] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[51];\nrk_eta[7] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[7] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[22] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[37] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[52];\nrk_eta[8] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[8] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[23] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[38] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[53];\nrk_eta[9] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[9] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[24] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[39] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[54];\nrk_eta[10] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[10] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[25] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[40] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[55];\nrk_eta[11] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[11] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[26] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[41] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[56];\nrk_eta[12] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[12] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[27] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[42] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[57];\nrk_eta[13] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[13] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[28] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[43] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[58];\nrk_eta[14] += + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[14] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[29] + (real_t)6.6666666666666638e-02*acadoWorkspace.rk_kkk[44] + (real_t)3.3333333333333319e-02*acadoWorkspace.rk_kkk[59];\nacadoWorkspace.rk_ttt += 1.0000000000000000e+00;\n}\n}\nerror = 0;\nreturn error;\n}\n\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_qpoases_interface.cpp",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\nextern \"C\"\n{\n#include \"acado_common.h\"\n}\n\n#include \"INCLUDE/QProblem.hpp\"\n\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\n#include \"INCLUDE/EXTRAS/SolutionAnalysis.hpp\"\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\nstatic int acado_nWSR;\n\n\n\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\nstatic SolutionAnalysis acado_sa;\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\nint acado_solve( void )\n{\n\tacado_nWSR = QPOASES_NWSRMAX;\n\n\tQProblem qp(23, 20);\n\t\n\treturnValue retVal = qp.init(acadoWorkspace.H, acadoWorkspace.g, acadoWorkspace.A, acadoWorkspace.lb, acadoWorkspace.ub, acadoWorkspace.lbA, acadoWorkspace.ubA, acado_nWSR, acadoWorkspace.y);\n\n    qp.getPrimalSolution( acadoWorkspace.x );\n    qp.getDualSolution( acadoWorkspace.y );\n\t\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\n\n\tif (retVal != SUCCESSFUL_RETURN)\n\t\treturn (int)retVal;\n\t\t\n\tretVal = acado_sa.getHessianInverse( &qp,var );\n\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\n\treturn (int)retVal;\n}\n\nint acado_getNWSR( void )\n{\n\treturn acado_nWSR;\n}\n\nconst char* acado_getErrorString( int error )\n{\n\treturn MessageHandling::getErrorString( error );\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_qpoases_interface.hpp",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef QPOASES_HEADER\n#define QPOASES_HEADER\n\n#ifdef PC_DEBUG\n#include <stdio.h>\n#endif /* PC_DEBUG */\n\n#include <math.h>\n\n#ifdef __cplusplus\n#define EXTERNC extern \"C\"\n#else\n#define EXTERNC\n#endif\n\n/*\n * A set of options for qpOASES\n */\n\n/** Maximum number of optimization variables. */\n#define QPOASES_NVMAX      23\n/** Maximum number of constraints. */\n#define QPOASES_NCMAX      20\n/** Maximum number of working set recalculations. */\n#define QPOASES_NWSRMAX    50\n/** Print level for qpOASES. */\n#define QPOASES_PRINTLEVEL PL_NONE\n/** The value of EPS */\n#define QPOASES_EPS        2.221e-16\n/** Internally used floating point type */\ntypedef double real_t;\n\n/*\n * Forward function declarations\n */\n\n/** A function that calls the QP solver */\nEXTERNC int acado_solve( void );\n\n/** Get the number of active set changes */\nEXTERNC int acado_getNWSR( void );\n\n/** Get the error string. */\nconst char* acado_getErrorString( int error );\n\n#endif /* QPOASES_HEADER */\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/lib_mpc_export/acado_solver.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_common.h\"\n\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/* ACADO code generation                                                      */\n/*                                                                            */\n/******************************************************************************/\n\n\nint acado_modelSimulation(  )\n{\nint ret;\n\nint lRun1;\nret = 0;\nfor (lRun1 = 0; lRun1 < 20; ++lRun1)\n{\nacadoWorkspace.state[0] = acadoVariables.x[lRun1 * 3];\nacadoWorkspace.state[1] = acadoVariables.x[lRun1 * 3 + 1];\nacadoWorkspace.state[2] = acadoVariables.x[lRun1 * 3 + 2];\n\nacadoWorkspace.state[15] = acadoVariables.u[lRun1];\nacadoWorkspace.state[16] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.state[17] = acadoVariables.od[lRun1 * 2 + 1];\n\nret = acado_integrate(acadoWorkspace.state, 1, lRun1);\n\nacadoWorkspace.d[lRun1 * 3] = acadoWorkspace.state[0] - acadoVariables.x[lRun1 * 3 + 3];\nacadoWorkspace.d[lRun1 * 3 + 1] = acadoWorkspace.state[1] - acadoVariables.x[lRun1 * 3 + 4];\nacadoWorkspace.d[lRun1 * 3 + 2] = acadoWorkspace.state[2] - acadoVariables.x[lRun1 * 3 + 5];\n\nacadoWorkspace.evGx[lRun1 * 9] = acadoWorkspace.state[3];\nacadoWorkspace.evGx[lRun1 * 9 + 1] = acadoWorkspace.state[4];\nacadoWorkspace.evGx[lRun1 * 9 + 2] = acadoWorkspace.state[5];\nacadoWorkspace.evGx[lRun1 * 9 + 3] = acadoWorkspace.state[6];\nacadoWorkspace.evGx[lRun1 * 9 + 4] = acadoWorkspace.state[7];\nacadoWorkspace.evGx[lRun1 * 9 + 5] = acadoWorkspace.state[8];\nacadoWorkspace.evGx[lRun1 * 9 + 6] = acadoWorkspace.state[9];\nacadoWorkspace.evGx[lRun1 * 9 + 7] = acadoWorkspace.state[10];\nacadoWorkspace.evGx[lRun1 * 9 + 8] = acadoWorkspace.state[11];\n\nacadoWorkspace.evGu[lRun1 * 3] = acadoWorkspace.state[12];\nacadoWorkspace.evGu[lRun1 * 3 + 1] = acadoWorkspace.state[13];\nacadoWorkspace.evGu[lRun1 * 3 + 2] = acadoWorkspace.state[14];\n}\nreturn ret;\n}\n\nvoid acado_evaluateLSQ(const real_t* in, real_t* out, double TR)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 3;\nconst real_t* od = in + 4;\n/* Vector of auxiliary variables; number of elements: 13. */\nreal_t* a = acadoWorkspace.objAuxVar;\n\n/* Compute intermediate quantities: */\na[0] = (sqrt((xd[1]+(real_t)(5.0000000000000000e-01))));\na[1] = (exp(((real_t)(2.9999999999999999e-01)*(((((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))+(real_t)(4.0000000000000000e+00))-(od[0]-xd[0]))/(a[0]+(real_t)(1.0000000000000001e-01))))));\na[2] = ((real_t)(1.0000000000000000e+00)/(a[0]+(real_t)(1.0000000000000001e-01)));\na[3] = (exp(((real_t)(2.9999999999999999e-01)*(((((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))+(real_t)(4.0000000000000000e+00))-(od[0]-xd[0]))/(a[0]+(real_t)(1.0000000000000001e-01))))));\na[4] = (((real_t)(2.9999999999999999e-01)*(((real_t)(0.0000000000000000e+00)-((real_t)(0.0000000000000000e+00)-(real_t)(1.0000000000000000e+00)))*a[2]))*a[3]);\na[5] = ((real_t)(1.0000000000000000e+00)/(real_t)(1.9620000000000001e+01));\na[6] = (1.0/sqrt((xd[1]+(real_t)(5.0000000000000000e-01))));\na[7] = (a[6]*(real_t)(5.0000000000000000e-01));\na[8] = (a[2]*a[2]);\na[9] = (((real_t)(2.9999999999999999e-01)*(((((real_t)(TR)-((real_t)(-TR)))+((xd[1]+xd[1])*a[5]))*a[2])-((((((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))+(real_t)(4.0000000000000000e+00))-(od[0]-xd[0]))*a[7])*a[8])))*a[3]);\na[10] = ((real_t)(1.0000000000000000e+00)/(((real_t)(5.0000000000000003e-02)*xd[1])+(real_t)(5.0000000000000000e-01)));\na[11] = ((real_t)(1.0000000000000000e+00)/(real_t)(1.9620000000000001e+01));\na[12] = (a[10]*a[10]);\n\n/* Compute outputs: */\nout[0] = (a[1]-(real_t)(1.0000000000000000e+00));\nout[1] = (((od[0]-xd[0])-((real_t)(4.0000000000000000e+00)+((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))))/(((real_t)(5.0000000000000003e-02)*xd[1])+(real_t)(5.0000000000000000e-01)));\nout[2] = (xd[2]*(((real_t)(1.0000000000000001e-01)*xd[1])+(real_t)(1.0000000000000000e+00)));\nout[3] = (u[0]*(((real_t)(1.0000000000000001e-01)*xd[1])+(real_t)(1.0000000000000000e+00)));\nout[4] = a[4];\nout[5] = a[9];\nout[6] = (real_t)(0.0000000000000000e+00);\nout[7] = (((real_t)(0.0000000000000000e+00)-(real_t)(1.0000000000000000e+00))*a[10]);\nout[8] = ((((real_t)(0.0000000000000000e+00)-(((real_t)(TR)-((real_t)(-TR)))+((xd[1]+xd[1])*a[11])))*a[10])-((((od[0]-xd[0])-((real_t)(4.0000000000000000e+00)+((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))))*(real_t)(5.0000000000000003e-02))*a[12]));\nout[9] = (real_t)(0.0000000000000000e+00);\nout[10] = (real_t)(0.0000000000000000e+00);\nout[11] = (xd[2]*(real_t)(1.0000000000000001e-01));\nout[12] = (((real_t)(1.0000000000000001e-01)*xd[1])+(real_t)(1.0000000000000000e+00));\nout[13] = (real_t)(0.0000000000000000e+00);\nout[14] = (u[0]*(real_t)(1.0000000000000001e-01));\nout[15] = (real_t)(0.0000000000000000e+00);\nout[16] = (real_t)(0.0000000000000000e+00);\nout[17] = (real_t)(0.0000000000000000e+00);\nout[18] = (real_t)(0.0000000000000000e+00);\nout[19] = (((real_t)(1.0000000000000001e-01)*xd[1])+(real_t)(1.0000000000000000e+00));\n}\n\nvoid acado_evaluateLSQEndTerm(const real_t* in, real_t* out, double TR)\n{\nconst real_t* xd = in;\nconst real_t* od = in + 3;\n/* Vector of auxiliary variables; number of elements: 13. */\nreal_t* a = acadoWorkspace.objAuxVar;\n\n/* Compute intermediate quantities: */\na[0] = (sqrt((xd[1]+(real_t)(5.0000000000000000e-01))));\na[1] = (exp(((real_t)(2.9999999999999999e-01)*(((((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))+(real_t)(4.0000000000000000e+00))-(od[0]-xd[0]))/(a[0]+(real_t)(1.0000000000000001e-01))))));\na[2] = ((real_t)(1.0000000000000000e+00)/(a[0]+(real_t)(1.0000000000000001e-01)));\na[3] = (exp(((real_t)(2.9999999999999999e-01)*(((((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))+(real_t)(4.0000000000000000e+00))-(od[0]-xd[0]))/(a[0]+(real_t)(1.0000000000000001e-01))))));\na[4] = (((real_t)(2.9999999999999999e-01)*(((real_t)(0.0000000000000000e+00)-((real_t)(0.0000000000000000e+00)-(real_t)(1.0000000000000000e+00)))*a[2]))*a[3]);\na[5] = ((real_t)(1.0000000000000000e+00)/(real_t)(1.9620000000000001e+01));\na[6] = (1.0/sqrt((xd[1]+(real_t)(5.0000000000000000e-01))));\na[7] = (a[6]*(real_t)(5.0000000000000000e-01));\na[8] = (a[2]*a[2]);\na[9] = (((real_t)(2.9999999999999999e-01)*(((((real_t)(TR)-((real_t)(-TR)))+((xd[1]+xd[1])*a[5]))*a[2])-((((((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))+(real_t)(4.0000000000000000e+00))-(od[0]-xd[0]))*a[7])*a[8])))*a[3]);\na[10] = ((real_t)(1.0000000000000000e+00)/(((real_t)(5.0000000000000003e-02)*xd[1])+(real_t)(5.0000000000000000e-01)));\na[11] = ((real_t)(1.0000000000000000e+00)/(real_t)(1.9620000000000001e+01));\na[12] = (a[10]*a[10]);\n\n/* Compute outputs: */\nout[0] = (a[1]-(real_t)(1.0000000000000000e+00));\nout[1] = (((od[0]-xd[0])-((real_t)(4.0000000000000000e+00)+((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))))/(((real_t)(5.0000000000000003e-02)*xd[1])+(real_t)(5.0000000000000000e-01)));\nout[2] = (xd[2]*(((real_t)(1.0000000000000001e-01)*xd[1])+(real_t)(1.0000000000000000e+00)));\nout[3] = a[4];\nout[4] = a[9];\nout[5] = (real_t)(0.0000000000000000e+00);\nout[6] = (((real_t)(0.0000000000000000e+00)-(real_t)(1.0000000000000000e+00))*a[10]);\nout[7] = ((((real_t)(0.0000000000000000e+00)-(((real_t)(TR)-((real_t)(-TR)))+((xd[1]+xd[1])*a[11])))*a[10])-((((od[0]-xd[0])-((real_t)(4.0000000000000000e+00)+((((xd[1]*(real_t)(TR))-((od[1]-xd[1])*(real_t)(TR)))+((xd[1]*xd[1])/(real_t)(1.9620000000000001e+01)))-((od[1]*od[1])/(real_t)(1.9620000000000001e+01)))))*(real_t)(5.0000000000000003e-02))*a[12]));\nout[8] = (real_t)(0.0000000000000000e+00);\nout[9] = (real_t)(0.0000000000000000e+00);\nout[10] = (xd[2]*(real_t)(1.0000000000000001e-01));\nout[11] = (((real_t)(1.0000000000000001e-01)*xd[1])+(real_t)(1.0000000000000000e+00));\n}\n\nvoid acado_setObjQ1Q2( real_t* const tmpFx, real_t* const tmpObjS, real_t* const tmpQ1, real_t* const tmpQ2 )\n{\ntmpQ2[0] = + tmpFx[0]*tmpObjS[0] + tmpFx[3]*tmpObjS[4] + tmpFx[6]*tmpObjS[8] + tmpFx[9]*tmpObjS[12];\ntmpQ2[1] = + tmpFx[0]*tmpObjS[1] + tmpFx[3]*tmpObjS[5] + tmpFx[6]*tmpObjS[9] + tmpFx[9]*tmpObjS[13];\ntmpQ2[2] = + tmpFx[0]*tmpObjS[2] + tmpFx[3]*tmpObjS[6] + tmpFx[6]*tmpObjS[10] + tmpFx[9]*tmpObjS[14];\ntmpQ2[3] = + tmpFx[0]*tmpObjS[3] + tmpFx[3]*tmpObjS[7] + tmpFx[6]*tmpObjS[11] + tmpFx[9]*tmpObjS[15];\ntmpQ2[4] = + tmpFx[1]*tmpObjS[0] + tmpFx[4]*tmpObjS[4] + tmpFx[7]*tmpObjS[8] + tmpFx[10]*tmpObjS[12];\ntmpQ2[5] = + tmpFx[1]*tmpObjS[1] + tmpFx[4]*tmpObjS[5] + tmpFx[7]*tmpObjS[9] + tmpFx[10]*tmpObjS[13];\ntmpQ2[6] = + tmpFx[1]*tmpObjS[2] + tmpFx[4]*tmpObjS[6] + tmpFx[7]*tmpObjS[10] + tmpFx[10]*tmpObjS[14];\ntmpQ2[7] = + tmpFx[1]*tmpObjS[3] + tmpFx[4]*tmpObjS[7] + tmpFx[7]*tmpObjS[11] + tmpFx[10]*tmpObjS[15];\ntmpQ2[8] = + tmpFx[2]*tmpObjS[0] + tmpFx[5]*tmpObjS[4] + tmpFx[8]*tmpObjS[8] + tmpFx[11]*tmpObjS[12];\ntmpQ2[9] = + tmpFx[2]*tmpObjS[1] + tmpFx[5]*tmpObjS[5] + tmpFx[8]*tmpObjS[9] + tmpFx[11]*tmpObjS[13];\ntmpQ2[10] = + tmpFx[2]*tmpObjS[2] + tmpFx[5]*tmpObjS[6] + tmpFx[8]*tmpObjS[10] + tmpFx[11]*tmpObjS[14];\ntmpQ2[11] = + tmpFx[2]*tmpObjS[3] + tmpFx[5]*tmpObjS[7] + tmpFx[8]*tmpObjS[11] + tmpFx[11]*tmpObjS[15];\ntmpQ1[0] = + tmpQ2[0]*tmpFx[0] + tmpQ2[1]*tmpFx[3] + tmpQ2[2]*tmpFx[6] + tmpQ2[3]*tmpFx[9];\ntmpQ1[1] = + tmpQ2[0]*tmpFx[1] + tmpQ2[1]*tmpFx[4] + tmpQ2[2]*tmpFx[7] + tmpQ2[3]*tmpFx[10];\ntmpQ1[2] = + tmpQ2[0]*tmpFx[2] + tmpQ2[1]*tmpFx[5] + tmpQ2[2]*tmpFx[8] + tmpQ2[3]*tmpFx[11];\ntmpQ1[3] = + tmpQ2[4]*tmpFx[0] + tmpQ2[5]*tmpFx[3] + tmpQ2[6]*tmpFx[6] + tmpQ2[7]*tmpFx[9];\ntmpQ1[4] = + tmpQ2[4]*tmpFx[1] + tmpQ2[5]*tmpFx[4] + tmpQ2[6]*tmpFx[7] + tmpQ2[7]*tmpFx[10];\ntmpQ1[5] = + tmpQ2[4]*tmpFx[2] + tmpQ2[5]*tmpFx[5] + tmpQ2[6]*tmpFx[8] + tmpQ2[7]*tmpFx[11];\ntmpQ1[6] = + tmpQ2[8]*tmpFx[0] + tmpQ2[9]*tmpFx[3] + tmpQ2[10]*tmpFx[6] + tmpQ2[11]*tmpFx[9];\ntmpQ1[7] = + tmpQ2[8]*tmpFx[1] + tmpQ2[9]*tmpFx[4] + tmpQ2[10]*tmpFx[7] + tmpQ2[11]*tmpFx[10];\ntmpQ1[8] = + tmpQ2[8]*tmpFx[2] + tmpQ2[9]*tmpFx[5] + tmpQ2[10]*tmpFx[8] + tmpQ2[11]*tmpFx[11];\n}\n\nvoid acado_setObjR1R2( real_t* const tmpFu, real_t* const tmpObjS, real_t* const tmpR1, real_t* const tmpR2 )\n{\ntmpR2[0] = + tmpFu[0]*tmpObjS[0] + tmpFu[1]*tmpObjS[4] + tmpFu[2]*tmpObjS[8] + tmpFu[3]*tmpObjS[12];\ntmpR2[1] = + tmpFu[0]*tmpObjS[1] + tmpFu[1]*tmpObjS[5] + tmpFu[2]*tmpObjS[9] + tmpFu[3]*tmpObjS[13];\ntmpR2[2] = + tmpFu[0]*tmpObjS[2] + tmpFu[1]*tmpObjS[6] + tmpFu[2]*tmpObjS[10] + tmpFu[3]*tmpObjS[14];\ntmpR2[3] = + tmpFu[0]*tmpObjS[3] + tmpFu[1]*tmpObjS[7] + tmpFu[2]*tmpObjS[11] + tmpFu[3]*tmpObjS[15];\ntmpR1[0] = + tmpR2[0]*tmpFu[0] + tmpR2[1]*tmpFu[1] + tmpR2[2]*tmpFu[2] + tmpR2[3]*tmpFu[3];\n}\n\nvoid acado_setObjQN1QN2( real_t* const tmpFx, real_t* const tmpObjSEndTerm, real_t* const tmpQN1, real_t* const tmpQN2 )\n{\ntmpQN2[0] = + tmpFx[0]*tmpObjSEndTerm[0] + tmpFx[3]*tmpObjSEndTerm[3] + tmpFx[6]*tmpObjSEndTerm[6];\ntmpQN2[1] = + tmpFx[0]*tmpObjSEndTerm[1] + tmpFx[3]*tmpObjSEndTerm[4] + tmpFx[6]*tmpObjSEndTerm[7];\ntmpQN2[2] = + tmpFx[0]*tmpObjSEndTerm[2] + tmpFx[3]*tmpObjSEndTerm[5] + tmpFx[6]*tmpObjSEndTerm[8];\ntmpQN2[3] = + tmpFx[1]*tmpObjSEndTerm[0] + tmpFx[4]*tmpObjSEndTerm[3] + tmpFx[7]*tmpObjSEndTerm[6];\ntmpQN2[4] = + tmpFx[1]*tmpObjSEndTerm[1] + tmpFx[4]*tmpObjSEndTerm[4] + tmpFx[7]*tmpObjSEndTerm[7];\ntmpQN2[5] = + tmpFx[1]*tmpObjSEndTerm[2] + tmpFx[4]*tmpObjSEndTerm[5] + tmpFx[7]*tmpObjSEndTerm[8];\ntmpQN2[6] = + tmpFx[2]*tmpObjSEndTerm[0] + tmpFx[5]*tmpObjSEndTerm[3] + tmpFx[8]*tmpObjSEndTerm[6];\ntmpQN2[7] = + tmpFx[2]*tmpObjSEndTerm[1] + tmpFx[5]*tmpObjSEndTerm[4] + tmpFx[8]*tmpObjSEndTerm[7];\ntmpQN2[8] = + tmpFx[2]*tmpObjSEndTerm[2] + tmpFx[5]*tmpObjSEndTerm[5] + tmpFx[8]*tmpObjSEndTerm[8];\ntmpQN1[0] = + tmpQN2[0]*tmpFx[0] + tmpQN2[1]*tmpFx[3] + tmpQN2[2]*tmpFx[6];\ntmpQN1[1] = + tmpQN2[0]*tmpFx[1] + tmpQN2[1]*tmpFx[4] + tmpQN2[2]*tmpFx[7];\ntmpQN1[2] = + tmpQN2[0]*tmpFx[2] + tmpQN2[1]*tmpFx[5] + tmpQN2[2]*tmpFx[8];\ntmpQN1[3] = + tmpQN2[3]*tmpFx[0] + tmpQN2[4]*tmpFx[3] + tmpQN2[5]*tmpFx[6];\ntmpQN1[4] = + tmpQN2[3]*tmpFx[1] + tmpQN2[4]*tmpFx[4] + tmpQN2[5]*tmpFx[7];\ntmpQN1[5] = + tmpQN2[3]*tmpFx[2] + tmpQN2[4]*tmpFx[5] + tmpQN2[5]*tmpFx[8];\ntmpQN1[6] = + tmpQN2[6]*tmpFx[0] + tmpQN2[7]*tmpFx[3] + tmpQN2[8]*tmpFx[6];\ntmpQN1[7] = + tmpQN2[6]*tmpFx[1] + tmpQN2[7]*tmpFx[4] + tmpQN2[8]*tmpFx[7];\ntmpQN1[8] = + tmpQN2[6]*tmpFx[2] + tmpQN2[7]*tmpFx[5] + tmpQN2[8]*tmpFx[8];\n}\n\nvoid acado_evaluateObjective( double TR )\n{\nint runObj;\nfor (runObj = 0; runObj < 20; ++runObj)\n{\nacadoWorkspace.objValueIn[0] = acadoVariables.x[runObj * 3];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[runObj * 3 + 1];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[runObj * 3 + 2];\nacadoWorkspace.objValueIn[3] = acadoVariables.u[runObj];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[runObj * 2];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[runObj * 2 + 1];\n\nacado_evaluateLSQ( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut, TR );\nacadoWorkspace.Dy[runObj * 4] = acadoWorkspace.objValueOut[0];\nacadoWorkspace.Dy[runObj * 4 + 1] = acadoWorkspace.objValueOut[1];\nacadoWorkspace.Dy[runObj * 4 + 2] = acadoWorkspace.objValueOut[2];\nacadoWorkspace.Dy[runObj * 4 + 3] = acadoWorkspace.objValueOut[3];\n\nacado_setObjQ1Q2( &(acadoWorkspace.objValueOut[ 4 ]), &(acadoVariables.W[ runObj * 16 ]), &(acadoWorkspace.Q1[ runObj * 9 ]), &(acadoWorkspace.Q2[ runObj * 12 ]) );\n\nacado_setObjR1R2( &(acadoWorkspace.objValueOut[ 16 ]), &(acadoVariables.W[ runObj * 16 ]), &(acadoWorkspace.R1[ runObj ]), &(acadoWorkspace.R2[ runObj * 4 ]) );\n\n}\nacadoWorkspace.objValueIn[0] = acadoVariables.x[60];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[61];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[62];\nacadoWorkspace.objValueIn[3] = acadoVariables.od[40];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[41];\nacado_evaluateLSQEndTerm( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut, TR );\n\nacadoWorkspace.DyN[0] = acadoWorkspace.objValueOut[0];\nacadoWorkspace.DyN[1] = acadoWorkspace.objValueOut[1];\nacadoWorkspace.DyN[2] = acadoWorkspace.objValueOut[2];\n\nacado_setObjQN1QN2( &(acadoWorkspace.objValueOut[ 3 ]), acadoVariables.WN, acadoWorkspace.QN1, acadoWorkspace.QN2 );\n\n}\n\nvoid acado_multGxd( real_t* const dOld, real_t* const Gx1, real_t* const dNew )\n{\ndNew[0] += + Gx1[0]*dOld[0] + Gx1[1]*dOld[1] + Gx1[2]*dOld[2];\ndNew[1] += + Gx1[3]*dOld[0] + Gx1[4]*dOld[1] + Gx1[5]*dOld[2];\ndNew[2] += + Gx1[6]*dOld[0] + Gx1[7]*dOld[1] + Gx1[8]*dOld[2];\n}\n\nvoid acado_moveGxT( real_t* const Gx1, real_t* const Gx2 )\n{\nGx2[0] = Gx1[0];\nGx2[1] = Gx1[1];\nGx2[2] = Gx1[2];\nGx2[3] = Gx1[3];\nGx2[4] = Gx1[4];\nGx2[5] = Gx1[5];\nGx2[6] = Gx1[6];\nGx2[7] = Gx1[7];\nGx2[8] = Gx1[8];\n}\n\nvoid acado_multGxGx( real_t* const Gx1, real_t* const Gx2, real_t* const Gx3 )\n{\nGx3[0] = + Gx1[0]*Gx2[0] + Gx1[1]*Gx2[3] + Gx1[2]*Gx2[6];\nGx3[1] = + Gx1[0]*Gx2[1] + Gx1[1]*Gx2[4] + Gx1[2]*Gx2[7];\nGx3[2] = + Gx1[0]*Gx2[2] + Gx1[1]*Gx2[5] + Gx1[2]*Gx2[8];\nGx3[3] = + Gx1[3]*Gx2[0] + Gx1[4]*Gx2[3] + Gx1[5]*Gx2[6];\nGx3[4] = + Gx1[3]*Gx2[1] + Gx1[4]*Gx2[4] + Gx1[5]*Gx2[7];\nGx3[5] = + Gx1[3]*Gx2[2] + Gx1[4]*Gx2[5] + Gx1[5]*Gx2[8];\nGx3[6] = + Gx1[6]*Gx2[0] + Gx1[7]*Gx2[3] + Gx1[8]*Gx2[6];\nGx3[7] = + Gx1[6]*Gx2[1] + Gx1[7]*Gx2[4] + Gx1[8]*Gx2[7];\nGx3[8] = + Gx1[6]*Gx2[2] + Gx1[7]*Gx2[5] + Gx1[8]*Gx2[8];\n}\n\nvoid acado_multGxGu( real_t* const Gx1, real_t* const Gu1, real_t* const Gu2 )\n{\nGu2[0] = + Gx1[0]*Gu1[0] + Gx1[1]*Gu1[1] + Gx1[2]*Gu1[2];\nGu2[1] = + Gx1[3]*Gu1[0] + Gx1[4]*Gu1[1] + Gx1[5]*Gu1[2];\nGu2[2] = + Gx1[6]*Gu1[0] + Gx1[7]*Gu1[1] + Gx1[8]*Gu1[2];\n}\n\nvoid acado_moveGuE( real_t* const Gu1, real_t* const Gu2 )\n{\nGu2[0] = Gu1[0];\nGu2[1] = Gu1[1];\nGu2[2] = Gu1[2];\n}\n\nvoid acado_setBlockH11( int iRow, int iCol, real_t* const Gu1, real_t* const Gu2 )\n{\nacadoWorkspace.H[(iRow * 23 + 69) + (iCol + 3)] += + Gu1[0]*Gu2[0] + Gu1[1]*Gu2[1] + Gu1[2]*Gu2[2];\n}\n\nvoid acado_setBlockH11_R1( int iRow, int iCol, real_t* const R11 )\n{\nacadoWorkspace.H[(iRow * 23 + 69) + (iCol + 3)] = R11[0];\n}\n\nvoid acado_zeroBlockH11( int iRow, int iCol )\n{\nacadoWorkspace.H[(iRow * 23 + 69) + (iCol + 3)] = 0.0000000000000000e+00;\n}\n\nvoid acado_copyHTH( int iRow, int iCol )\n{\nacadoWorkspace.H[(iRow * 23 + 69) + (iCol + 3)] = acadoWorkspace.H[(iCol * 23 + 69) + (iRow + 3)];\n}\n\nvoid acado_multQ1d( real_t* const Gx1, real_t* const dOld, real_t* const dNew )\n{\ndNew[0] = + Gx1[0]*dOld[0] + Gx1[1]*dOld[1] + Gx1[2]*dOld[2];\ndNew[1] = + Gx1[3]*dOld[0] + Gx1[4]*dOld[1] + Gx1[5]*dOld[2];\ndNew[2] = + Gx1[6]*dOld[0] + Gx1[7]*dOld[1] + Gx1[8]*dOld[2];\n}\n\nvoid acado_multQN1d( real_t* const QN1, real_t* const dOld, real_t* const dNew )\n{\ndNew[0] = + acadoWorkspace.QN1[0]*dOld[0] + acadoWorkspace.QN1[1]*dOld[1] + acadoWorkspace.QN1[2]*dOld[2];\ndNew[1] = + acadoWorkspace.QN1[3]*dOld[0] + acadoWorkspace.QN1[4]*dOld[1] + acadoWorkspace.QN1[5]*dOld[2];\ndNew[2] = + acadoWorkspace.QN1[6]*dOld[0] + acadoWorkspace.QN1[7]*dOld[1] + acadoWorkspace.QN1[8]*dOld[2];\n}\n\nvoid acado_multRDy( real_t* const R2, real_t* const Dy1, real_t* const RDy1 )\n{\nRDy1[0] = + R2[0]*Dy1[0] + R2[1]*Dy1[1] + R2[2]*Dy1[2] + R2[3]*Dy1[3];\n}\n\nvoid acado_multQDy( real_t* const Q2, real_t* const Dy1, real_t* const QDy1 )\n{\nQDy1[0] = + Q2[0]*Dy1[0] + Q2[1]*Dy1[1] + Q2[2]*Dy1[2] + Q2[3]*Dy1[3];\nQDy1[1] = + Q2[4]*Dy1[0] + Q2[5]*Dy1[1] + Q2[6]*Dy1[2] + Q2[7]*Dy1[3];\nQDy1[2] = + Q2[8]*Dy1[0] + Q2[9]*Dy1[1] + Q2[10]*Dy1[2] + Q2[11]*Dy1[3];\n}\n\nvoid acado_multEQDy( real_t* const E1, real_t* const QDy1, real_t* const U1 )\n{\nU1[0] += + E1[0]*QDy1[0] + E1[1]*QDy1[1] + E1[2]*QDy1[2];\n}\n\nvoid acado_multQETGx( real_t* const E1, real_t* const Gx1, real_t* const H101 )\n{\nH101[0] += + E1[0]*Gx1[0] + E1[1]*Gx1[3] + E1[2]*Gx1[6];\nH101[1] += + E1[0]*Gx1[1] + E1[1]*Gx1[4] + E1[2]*Gx1[7];\nH101[2] += + E1[0]*Gx1[2] + E1[1]*Gx1[5] + E1[2]*Gx1[8];\n}\n\nvoid acado_zeroBlockH10( real_t* const H101 )\n{\n{ int lCopy; for (lCopy = 0; lCopy < 3; lCopy++) H101[ lCopy ] = 0; }\n}\n\nvoid acado_multEDu( real_t* const E1, real_t* const U1, real_t* const dNew )\n{\ndNew[0] += + E1[0]*U1[0];\ndNew[1] += + E1[1]*U1[0];\ndNew[2] += + E1[2]*U1[0];\n}\n\nvoid acado_zeroBlockH00(  )\n{\nacadoWorkspace.H[0] = 0.0000000000000000e+00;\nacadoWorkspace.H[1] = 0.0000000000000000e+00;\nacadoWorkspace.H[2] = 0.0000000000000000e+00;\nacadoWorkspace.H[23] = 0.0000000000000000e+00;\nacadoWorkspace.H[24] = 0.0000000000000000e+00;\nacadoWorkspace.H[25] = 0.0000000000000000e+00;\nacadoWorkspace.H[46] = 0.0000000000000000e+00;\nacadoWorkspace.H[47] = 0.0000000000000000e+00;\nacadoWorkspace.H[48] = 0.0000000000000000e+00;\n}\n\nvoid acado_multCTQC( real_t* const Gx1, real_t* const Gx2 )\n{\nacadoWorkspace.H[0] += + Gx1[0]*Gx2[0] + Gx1[3]*Gx2[3] + Gx1[6]*Gx2[6];\nacadoWorkspace.H[1] += + Gx1[0]*Gx2[1] + Gx1[3]*Gx2[4] + Gx1[6]*Gx2[7];\nacadoWorkspace.H[2] += + Gx1[0]*Gx2[2] + Gx1[3]*Gx2[5] + Gx1[6]*Gx2[8];\nacadoWorkspace.H[23] += + Gx1[1]*Gx2[0] + Gx1[4]*Gx2[3] + Gx1[7]*Gx2[6];\nacadoWorkspace.H[24] += + Gx1[1]*Gx2[1] + Gx1[4]*Gx2[4] + Gx1[7]*Gx2[7];\nacadoWorkspace.H[25] += + Gx1[1]*Gx2[2] + Gx1[4]*Gx2[5] + Gx1[7]*Gx2[8];\nacadoWorkspace.H[46] += + Gx1[2]*Gx2[0] + Gx1[5]*Gx2[3] + Gx1[8]*Gx2[6];\nacadoWorkspace.H[47] += + Gx1[2]*Gx2[1] + Gx1[5]*Gx2[4] + Gx1[8]*Gx2[7];\nacadoWorkspace.H[48] += + Gx1[2]*Gx2[2] + Gx1[5]*Gx2[5] + Gx1[8]*Gx2[8];\n}\n\nvoid acado_macCTSlx( real_t* const C0, real_t* const g0 )\n{\ng0[0] += 0.0;\n;\ng0[1] += 0.0;\n;\ng0[2] += 0.0;\n;\n}\n\nvoid acado_macETSlu( real_t* const E0, real_t* const g1 )\n{\ng1[0] += 0.0;\n;\n}\n\nvoid acado_condensePrep(  )\n{\nint lRun1;\nint lRun2;\nint lRun3;\nint lRun4;\nint lRun5;\n/** Row vector of size: 20 */\nstatic const int xBoundIndices[ 20 ] = \n{ 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 43, 46, 49, 52, 55, 58, 61 };\nacado_moveGuE( acadoWorkspace.evGu, acadoWorkspace.E );\nacado_moveGxT( &(acadoWorkspace.evGx[ 9 ]), acadoWorkspace.T );\nacado_multGxd( acadoWorkspace.d, &(acadoWorkspace.evGx[ 9 ]), &(acadoWorkspace.d[ 3 ]) );\nacado_multGxGx( acadoWorkspace.T, acadoWorkspace.evGx, &(acadoWorkspace.evGx[ 9 ]) );\n\nacado_multGxGu( acadoWorkspace.T, acadoWorkspace.E, &(acadoWorkspace.E[ 3 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 3 ]), &(acadoWorkspace.E[ 6 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 18 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 3 ]), &(acadoWorkspace.evGx[ 18 ]), &(acadoWorkspace.d[ 6 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 9 ]), &(acadoWorkspace.evGx[ 18 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 3 ]), &(acadoWorkspace.E[ 9 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 6 ]), &(acadoWorkspace.E[ 12 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 6 ]), &(acadoWorkspace.E[ 15 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 27 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 6 ]), &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.d[ 9 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 18 ]), &(acadoWorkspace.evGx[ 27 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.E[ 18 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.E[ 21 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 15 ]), &(acadoWorkspace.E[ 24 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 9 ]), &(acadoWorkspace.E[ 27 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 36 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 9 ]), &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.d[ 12 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.evGx[ 36 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.E[ 30 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.E[ 33 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.E[ 36 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 27 ]), &(acadoWorkspace.E[ 39 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 12 ]), &(acadoWorkspace.E[ 42 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 45 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 12 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.d[ 15 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.evGx[ 45 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.E[ 45 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.E[ 48 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.E[ 51 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 39 ]), &(acadoWorkspace.E[ 54 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 42 ]), &(acadoWorkspace.E[ 57 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 15 ]), &(acadoWorkspace.E[ 60 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 54 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 15 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.d[ 18 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.evGx[ 54 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.E[ 63 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.E[ 66 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.E[ 69 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.E[ 72 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 57 ]), &(acadoWorkspace.E[ 75 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.E[ 78 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 18 ]), &(acadoWorkspace.E[ 81 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 63 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 18 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.d[ 21 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.evGx[ 63 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.E[ 84 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.E[ 87 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.E[ 90 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.E[ 93 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.E[ 96 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 78 ]), &(acadoWorkspace.E[ 99 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 81 ]), &(acadoWorkspace.E[ 102 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 21 ]), &(acadoWorkspace.E[ 105 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 72 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 21 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.d[ 24 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.evGx[ 72 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.E[ 108 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.E[ 111 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.E[ 114 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.E[ 117 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.E[ 120 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.E[ 123 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 102 ]), &(acadoWorkspace.E[ 126 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 105 ]), &(acadoWorkspace.E[ 129 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 24 ]), &(acadoWorkspace.E[ 132 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 81 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 24 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.d[ 27 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.evGx[ 81 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.E[ 135 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.E[ 138 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.E[ 141 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.E[ 144 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.E[ 147 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.E[ 150 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.E[ 153 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 129 ]), &(acadoWorkspace.E[ 156 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.E[ 159 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 27 ]), &(acadoWorkspace.E[ 162 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 90 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 27 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.d[ 30 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.evGx[ 90 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.E[ 165 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.E[ 168 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.E[ 171 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.E[ 174 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.E[ 177 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.E[ 180 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.E[ 183 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.E[ 186 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 159 ]), &(acadoWorkspace.E[ 189 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 162 ]), &(acadoWorkspace.E[ 192 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 30 ]), &(acadoWorkspace.E[ 195 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 99 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 30 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.d[ 33 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.evGx[ 99 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.E[ 198 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.E[ 201 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.E[ 204 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.E[ 207 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.E[ 210 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.E[ 213 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.E[ 216 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.E[ 219 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 189 ]), &(acadoWorkspace.E[ 222 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.E[ 225 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 195 ]), &(acadoWorkspace.E[ 228 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 33 ]), &(acadoWorkspace.E[ 231 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 108 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 33 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.d[ 36 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.evGx[ 108 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.E[ 234 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.E[ 237 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.E[ 240 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.E[ 243 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.E[ 246 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.E[ 249 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.E[ 252 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.E[ 255 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.E[ 258 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 225 ]), &(acadoWorkspace.E[ 261 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.E[ 264 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 231 ]), &(acadoWorkspace.E[ 267 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 36 ]), &(acadoWorkspace.E[ 270 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 117 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 36 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.d[ 39 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.evGx[ 117 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.E[ 273 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.E[ 276 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.E[ 279 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.E[ 282 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.E[ 285 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.E[ 288 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.E[ 291 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.E[ 294 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.E[ 297 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.E[ 300 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.E[ 303 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 267 ]), &(acadoWorkspace.E[ 306 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 270 ]), &(acadoWorkspace.E[ 309 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 39 ]), &(acadoWorkspace.E[ 312 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 126 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 39 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.d[ 42 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.evGx[ 126 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.E[ 315 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.E[ 318 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.E[ 321 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.E[ 324 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.E[ 327 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.E[ 330 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.E[ 333 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.E[ 336 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.E[ 339 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.E[ 342 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.E[ 345 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 306 ]), &(acadoWorkspace.E[ 348 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 309 ]), &(acadoWorkspace.E[ 351 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.E[ 354 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 42 ]), &(acadoWorkspace.E[ 357 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 135 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 42 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.d[ 45 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.evGx[ 135 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.E[ 360 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.E[ 363 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.E[ 366 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.E[ 369 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.E[ 372 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.E[ 375 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.E[ 378 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.E[ 381 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.E[ 384 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.E[ 387 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.E[ 390 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.E[ 393 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 351 ]), &(acadoWorkspace.E[ 396 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 354 ]), &(acadoWorkspace.E[ 399 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 357 ]), &(acadoWorkspace.E[ 402 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 45 ]), &(acadoWorkspace.E[ 405 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 45 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.d[ 48 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.evGx[ 144 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.E[ 408 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.E[ 411 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.E[ 414 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.E[ 417 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.E[ 420 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.E[ 423 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.E[ 426 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.E[ 429 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.E[ 432 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.E[ 435 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.E[ 438 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.E[ 441 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.E[ 444 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 399 ]), &(acadoWorkspace.E[ 447 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 402 ]), &(acadoWorkspace.E[ 450 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 405 ]), &(acadoWorkspace.E[ 453 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 48 ]), &(acadoWorkspace.E[ 456 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 153 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 48 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.d[ 51 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.evGx[ 153 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.E[ 459 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.E[ 462 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.E[ 465 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.E[ 468 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.E[ 471 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.E[ 474 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.E[ 477 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.E[ 480 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.E[ 483 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.E[ 486 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.E[ 489 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.E[ 492 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.E[ 495 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.E[ 498 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 450 ]), &(acadoWorkspace.E[ 501 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 453 ]), &(acadoWorkspace.E[ 504 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.E[ 507 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 51 ]), &(acadoWorkspace.E[ 510 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 162 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 51 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.d[ 54 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.evGx[ 162 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.E[ 513 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.E[ 516 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.E[ 519 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.E[ 522 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.E[ 525 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.E[ 528 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.E[ 531 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.E[ 534 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.E[ 537 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.E[ 540 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.E[ 543 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.E[ 546 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.E[ 549 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.E[ 552 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.E[ 555 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.E[ 558 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 507 ]), &(acadoWorkspace.E[ 561 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 510 ]), &(acadoWorkspace.E[ 564 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 54 ]), &(acadoWorkspace.E[ 567 ]) );\n\nacado_moveGxT( &(acadoWorkspace.evGx[ 171 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ 54 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.d[ 57 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.evGx[ 171 ]) );\n\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.E[ 570 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.E[ 573 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.E[ 576 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.E[ 579 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.E[ 582 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.E[ 585 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.E[ 588 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.E[ 591 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.E[ 594 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.E[ 597 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.E[ 600 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.E[ 603 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.E[ 606 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.E[ 609 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.E[ 612 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.E[ 615 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.E[ 618 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 564 ]), &(acadoWorkspace.E[ 621 ]) );\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ 567 ]), &(acadoWorkspace.E[ 624 ]) );\n\nacado_moveGuE( &(acadoWorkspace.evGu[ 57 ]), &(acadoWorkspace.E[ 627 ]) );\n\nacado_multGxGx( &(acadoWorkspace.Q1[ 9 ]), acadoWorkspace.evGx, acadoWorkspace.QGx );\nacado_multGxGx( &(acadoWorkspace.Q1[ 18 ]), &(acadoWorkspace.evGx[ 9 ]), &(acadoWorkspace.QGx[ 9 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 27 ]), &(acadoWorkspace.evGx[ 18 ]), &(acadoWorkspace.QGx[ 18 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 36 ]), &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.QGx[ 27 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.QGx[ 36 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.QGx[ 45 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.QGx[ 54 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.QGx[ 63 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.QGx[ 72 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.QGx[ 81 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.QGx[ 90 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.QGx[ 99 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.QGx[ 108 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.QGx[ 117 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.QGx[ 126 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.QGx[ 135 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.QGx[ 144 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.QGx[ 153 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.QGx[ 162 ]) );\nacado_multGxGx( acadoWorkspace.QN1, &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.QGx[ 171 ]) );\n\nacado_multGxGu( &(acadoWorkspace.Q1[ 9 ]), acadoWorkspace.E, acadoWorkspace.QE );\nacado_multGxGu( &(acadoWorkspace.Q1[ 18 ]), &(acadoWorkspace.E[ 3 ]), &(acadoWorkspace.QE[ 3 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 18 ]), &(acadoWorkspace.E[ 6 ]), &(acadoWorkspace.QE[ 6 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 27 ]), &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.QE[ 9 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 27 ]), &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 12 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 27 ]), &(acadoWorkspace.E[ 15 ]), &(acadoWorkspace.QE[ 15 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 36 ]), &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.QE[ 18 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 36 ]), &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.QE[ 21 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 36 ]), &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 24 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 36 ]), &(acadoWorkspace.E[ 27 ]), &(acadoWorkspace.QE[ 27 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QE[ 30 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.QE[ 33 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.E[ 39 ]), &(acadoWorkspace.QE[ 39 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.E[ 42 ]), &(acadoWorkspace.QE[ 42 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 45 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.QE[ 51 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.QE[ 54 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.E[ 57 ]), &(acadoWorkspace.QE[ 57 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 63 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 66 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QE[ 69 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.QE[ 75 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 78 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.E[ 81 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 84 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 87 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 90 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QE[ 93 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 102 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.E[ 105 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 111 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 114 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 117 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 129 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 135 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 138 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 141 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 147 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 159 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.E[ 162 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 165 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 171 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 174 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 177 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 189 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.E[ 195 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 198 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 201 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 207 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 210 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 225 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.E[ 231 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 234 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 237 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 243 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 246 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 267 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.E[ 270 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 273 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 279 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 282 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 285 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 306 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 309 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 315 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 318 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 321 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 327 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 351 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 354 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.E[ 357 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 363 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 366 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 369 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 399 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 402 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.E[ 405 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 411 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 414 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 417 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 450 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 453 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 459 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 462 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 465 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 471 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 507 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.E[ 510 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 513 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 516 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 519 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 522 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 525 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 564 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_multGxGu( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.E[ 567 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 570 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 573 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 576 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 579 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 582 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 585 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 588 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 591 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 594 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 597 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 600 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 603 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 606 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 609 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 612 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QE[ 615 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.QE[ 618 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 621 ]), &(acadoWorkspace.QE[ 621 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 624 ]), &(acadoWorkspace.QE[ 624 ]) );\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ 627 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_zeroBlockH00(  );\nacado_multCTQC( acadoWorkspace.evGx, acadoWorkspace.QGx );\nacado_multCTQC( &(acadoWorkspace.evGx[ 9 ]), &(acadoWorkspace.QGx[ 9 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 18 ]), &(acadoWorkspace.QGx[ 18 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.QGx[ 27 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.QGx[ 36 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.QGx[ 45 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.QGx[ 54 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.QGx[ 63 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.QGx[ 72 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.QGx[ 81 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.QGx[ 90 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.QGx[ 99 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.QGx[ 108 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.QGx[ 117 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.QGx[ 126 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.QGx[ 135 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.QGx[ 144 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.QGx[ 153 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.QGx[ 162 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.QGx[ 171 ]) );\n\nacado_zeroBlockH10( acadoWorkspace.H10 );\nacado_multQETGx( acadoWorkspace.QE, acadoWorkspace.evGx, acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 3 ]), &(acadoWorkspace.evGx[ 9 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 9 ]), &(acadoWorkspace.evGx[ 18 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 18 ]), &(acadoWorkspace.evGx[ 27 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 30 ]), &(acadoWorkspace.evGx[ 36 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 45 ]), &(acadoWorkspace.evGx[ 45 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 63 ]), &(acadoWorkspace.evGx[ 54 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 84 ]), &(acadoWorkspace.evGx[ 63 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 108 ]), &(acadoWorkspace.evGx[ 72 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 135 ]), &(acadoWorkspace.evGx[ 81 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 165 ]), &(acadoWorkspace.evGx[ 90 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 198 ]), &(acadoWorkspace.evGx[ 99 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 234 ]), &(acadoWorkspace.evGx[ 108 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 273 ]), &(acadoWorkspace.evGx[ 117 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 315 ]), &(acadoWorkspace.evGx[ 126 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 360 ]), &(acadoWorkspace.evGx[ 135 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 408 ]), &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 459 ]), &(acadoWorkspace.evGx[ 153 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 513 ]), &(acadoWorkspace.evGx[ 162 ]), acadoWorkspace.H10 );\nacado_multQETGx( &(acadoWorkspace.QE[ 570 ]), &(acadoWorkspace.evGx[ 171 ]), acadoWorkspace.H10 );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 6 ]), &(acadoWorkspace.evGx[ 9 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 12 ]), &(acadoWorkspace.evGx[ 18 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 21 ]), &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 33 ]), &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 48 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 66 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 87 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 111 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 138 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 168 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 201 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 237 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 276 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 318 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 363 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 411 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 462 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 516 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 573 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 3 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 15 ]), &(acadoWorkspace.evGx[ 18 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 24 ]), &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 36 ]), &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 51 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 69 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 90 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 114 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 141 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 171 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 204 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 240 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 279 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 321 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 366 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 414 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 465 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 519 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 576 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 6 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 27 ]), &(acadoWorkspace.evGx[ 27 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 39 ]), &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 54 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 72 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 93 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 117 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 144 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 174 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 207 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 243 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 282 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 324 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 369 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 417 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 468 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 522 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 579 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 9 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 42 ]), &(acadoWorkspace.evGx[ 36 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 57 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 75 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 96 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 120 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 147 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 177 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 210 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 246 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 285 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 327 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 372 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 420 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 471 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 525 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 582 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 12 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 60 ]), &(acadoWorkspace.evGx[ 45 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 78 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 99 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 123 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 150 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 180 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 213 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 249 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 288 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 330 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 375 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 423 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 474 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 528 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 585 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 15 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 81 ]), &(acadoWorkspace.evGx[ 54 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 102 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 126 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 153 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 183 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 216 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 252 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 291 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 333 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 378 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 426 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 477 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 531 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 588 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 18 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 105 ]), &(acadoWorkspace.evGx[ 63 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 129 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 156 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 186 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 219 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 255 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 294 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 336 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 381 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 429 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 480 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 534 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 591 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 21 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 132 ]), &(acadoWorkspace.evGx[ 72 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 159 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 189 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 222 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 258 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 297 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 339 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 384 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 432 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 483 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 537 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 594 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 24 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 162 ]), &(acadoWorkspace.evGx[ 81 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 192 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 225 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 261 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 300 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 342 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 387 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 435 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 486 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 540 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 597 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 27 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 195 ]), &(acadoWorkspace.evGx[ 90 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 228 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 264 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 303 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 345 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 390 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 438 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 489 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 543 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 600 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 30 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 231 ]), &(acadoWorkspace.evGx[ 99 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 267 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 306 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 348 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 393 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 441 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 492 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 546 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 603 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 33 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 270 ]), &(acadoWorkspace.evGx[ 108 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 309 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 351 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 396 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 444 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 495 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 549 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 606 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 36 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 312 ]), &(acadoWorkspace.evGx[ 117 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 354 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 399 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 447 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 498 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 552 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 609 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 39 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 42 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 357 ]), &(acadoWorkspace.evGx[ 126 ]), &(acadoWorkspace.H10[ 42 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 402 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 42 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 450 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 42 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 501 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 42 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 555 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 42 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 612 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 42 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 45 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 405 ]), &(acadoWorkspace.evGx[ 135 ]), &(acadoWorkspace.H10[ 45 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 453 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 45 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 504 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 45 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 558 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 45 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 615 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 45 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 456 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 507 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 561 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 618 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 48 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 51 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 510 ]), &(acadoWorkspace.evGx[ 153 ]), &(acadoWorkspace.H10[ 51 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 564 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 51 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 621 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 51 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 54 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 567 ]), &(acadoWorkspace.evGx[ 162 ]), &(acadoWorkspace.H10[ 54 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 624 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 54 ]) );\nacado_zeroBlockH10( &(acadoWorkspace.H10[ 57 ]) );\nacado_multQETGx( &(acadoWorkspace.QE[ 627 ]), &(acadoWorkspace.evGx[ 171 ]), &(acadoWorkspace.H10[ 57 ]) );\n\nacadoWorkspace.H[3] = acadoWorkspace.H10[0];\nacadoWorkspace.H[4] = acadoWorkspace.H10[3];\nacadoWorkspace.H[5] = acadoWorkspace.H10[6];\nacadoWorkspace.H[6] = acadoWorkspace.H10[9];\nacadoWorkspace.H[7] = acadoWorkspace.H10[12];\nacadoWorkspace.H[8] = acadoWorkspace.H10[15];\nacadoWorkspace.H[9] = acadoWorkspace.H10[18];\nacadoWorkspace.H[10] = acadoWorkspace.H10[21];\nacadoWorkspace.H[11] = acadoWorkspace.H10[24];\nacadoWorkspace.H[12] = acadoWorkspace.H10[27];\nacadoWorkspace.H[13] = acadoWorkspace.H10[30];\nacadoWorkspace.H[14] = acadoWorkspace.H10[33];\nacadoWorkspace.H[15] = acadoWorkspace.H10[36];\nacadoWorkspace.H[16] = acadoWorkspace.H10[39];\nacadoWorkspace.H[17] = acadoWorkspace.H10[42];\nacadoWorkspace.H[18] = acadoWorkspace.H10[45];\nacadoWorkspace.H[19] = acadoWorkspace.H10[48];\nacadoWorkspace.H[20] = acadoWorkspace.H10[51];\nacadoWorkspace.H[21] = acadoWorkspace.H10[54];\nacadoWorkspace.H[22] = acadoWorkspace.H10[57];\nacadoWorkspace.H[26] = acadoWorkspace.H10[1];\nacadoWorkspace.H[27] = acadoWorkspace.H10[4];\nacadoWorkspace.H[28] = acadoWorkspace.H10[7];\nacadoWorkspace.H[29] = acadoWorkspace.H10[10];\nacadoWorkspace.H[30] = acadoWorkspace.H10[13];\nacadoWorkspace.H[31] = acadoWorkspace.H10[16];\nacadoWorkspace.H[32] = acadoWorkspace.H10[19];\nacadoWorkspace.H[33] = acadoWorkspace.H10[22];\nacadoWorkspace.H[34] = acadoWorkspace.H10[25];\nacadoWorkspace.H[35] = acadoWorkspace.H10[28];\nacadoWorkspace.H[36] = acadoWorkspace.H10[31];\nacadoWorkspace.H[37] = acadoWorkspace.H10[34];\nacadoWorkspace.H[38] = acadoWorkspace.H10[37];\nacadoWorkspace.H[39] = acadoWorkspace.H10[40];\nacadoWorkspace.H[40] = acadoWorkspace.H10[43];\nacadoWorkspace.H[41] = acadoWorkspace.H10[46];\nacadoWorkspace.H[42] = acadoWorkspace.H10[49];\nacadoWorkspace.H[43] = acadoWorkspace.H10[52];\nacadoWorkspace.H[44] = acadoWorkspace.H10[55];\nacadoWorkspace.H[45] = acadoWorkspace.H10[58];\nacadoWorkspace.H[49] = acadoWorkspace.H10[2];\nacadoWorkspace.H[50] = acadoWorkspace.H10[5];\nacadoWorkspace.H[51] = acadoWorkspace.H10[8];\nacadoWorkspace.H[52] = acadoWorkspace.H10[11];\nacadoWorkspace.H[53] = acadoWorkspace.H10[14];\nacadoWorkspace.H[54] = acadoWorkspace.H10[17];\nacadoWorkspace.H[55] = acadoWorkspace.H10[20];\nacadoWorkspace.H[56] = acadoWorkspace.H10[23];\nacadoWorkspace.H[57] = acadoWorkspace.H10[26];\nacadoWorkspace.H[58] = acadoWorkspace.H10[29];\nacadoWorkspace.H[59] = acadoWorkspace.H10[32];\nacadoWorkspace.H[60] = acadoWorkspace.H10[35];\nacadoWorkspace.H[61] = acadoWorkspace.H10[38];\nacadoWorkspace.H[62] = acadoWorkspace.H10[41];\nacadoWorkspace.H[63] = acadoWorkspace.H10[44];\nacadoWorkspace.H[64] = acadoWorkspace.H10[47];\nacadoWorkspace.H[65] = acadoWorkspace.H10[50];\nacadoWorkspace.H[66] = acadoWorkspace.H10[53];\nacadoWorkspace.H[67] = acadoWorkspace.H10[56];\nacadoWorkspace.H[68] = acadoWorkspace.H10[59];\n\nacado_setBlockH11_R1( 0, 0, acadoWorkspace.R1 );\nacado_setBlockH11( 0, 0, acadoWorkspace.E, acadoWorkspace.QE );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 3 ]), &(acadoWorkspace.QE[ 3 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.QE[ 9 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.QE[ 18 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QE[ 30 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 45 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 63 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 84 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 108 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 135 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 165 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 198 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 234 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 273 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 315 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 360 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 408 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 459 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 513 ]) );\nacado_setBlockH11( 0, 0, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 570 ]) );\n\nacado_zeroBlockH11( 0, 1 );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 3 ]), &(acadoWorkspace.QE[ 6 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.QE[ 12 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.QE[ 21 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QE[ 33 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 66 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 87 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 111 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 138 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 201 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 237 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 318 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 363 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 411 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 462 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 516 ]) );\nacado_setBlockH11( 0, 1, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 573 ]) );\n\nacado_zeroBlockH11( 0, 2 );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.QE[ 15 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.QE[ 24 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 51 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 69 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 90 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 114 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 141 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 171 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 279 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 321 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 366 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 414 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 465 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 519 ]) );\nacado_setBlockH11( 0, 2, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 576 ]) );\n\nacado_zeroBlockH11( 0, 3 );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.QE[ 27 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QE[ 39 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 54 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 93 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 117 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 174 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 207 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 243 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 282 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 369 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 417 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 522 ]) );\nacado_setBlockH11( 0, 3, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 579 ]) );\n\nacado_zeroBlockH11( 0, 4 );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QE[ 42 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 57 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 75 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 147 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 177 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 210 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 246 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 285 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 327 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 471 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 525 ]) );\nacado_setBlockH11( 0, 4, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 582 ]) );\n\nacado_zeroBlockH11( 0, 5 );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_setBlockH11( 0, 5, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 585 ]) );\n\nacado_zeroBlockH11( 0, 6 );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 0, 6, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 0, 7 );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 0, 7, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 0, 8 );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 0, 8, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 0, 9 );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 0, 9, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 0, 10 );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 0, 10, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 0, 11 );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 0, 11, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 0, 12 );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 0, 12, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 0, 13 );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 0, 13, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 0, 14 );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 0, 14, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 0, 15 );\nacado_setBlockH11( 0, 15, &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 0, 15, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 0, 15, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 0, 15, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 0, 15, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 0, 16 );\nacado_setBlockH11( 0, 16, &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 0, 16, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 0, 16, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 0, 16, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 0, 17 );\nacado_setBlockH11( 0, 17, &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 0, 17, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 0, 17, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 0, 18 );\nacado_setBlockH11( 0, 18, &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 0, 18, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 0, 19 );\nacado_setBlockH11( 0, 19, &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 1, 1, &(acadoWorkspace.R1[ 1 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 6 ]), &(acadoWorkspace.QE[ 6 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 12 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.QE[ 21 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.QE[ 33 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 48 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 66 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 87 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 111 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 138 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 168 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 201 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 237 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 276 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 318 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 363 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 411 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 462 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 516 ]) );\nacado_setBlockH11( 1, 1, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 573 ]) );\n\nacado_zeroBlockH11( 1, 2 );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QE[ 15 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.QE[ 24 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 51 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 69 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 90 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 114 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 141 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 171 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 279 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 321 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 366 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 414 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 465 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 519 ]) );\nacado_setBlockH11( 1, 2, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 576 ]) );\n\nacado_zeroBlockH11( 1, 3 );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.QE[ 27 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.QE[ 39 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 54 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 93 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 117 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 174 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 207 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 243 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 282 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 369 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 417 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 522 ]) );\nacado_setBlockH11( 1, 3, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 579 ]) );\n\nacado_zeroBlockH11( 1, 4 );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.QE[ 42 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 57 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 75 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 147 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 177 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 210 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 246 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 285 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 327 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 471 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 525 ]) );\nacado_setBlockH11( 1, 4, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 582 ]) );\n\nacado_zeroBlockH11( 1, 5 );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_setBlockH11( 1, 5, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 585 ]) );\n\nacado_zeroBlockH11( 1, 6 );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 1, 6, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 1, 7 );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 1, 7, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 1, 8 );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 1, 8, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 1, 9 );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 1, 9, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 1, 10 );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 1, 10, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 1, 11 );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 1, 11, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 1, 12 );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 1, 12, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 1, 13 );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 1, 13, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 1, 14 );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 1, 14, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 1, 15 );\nacado_setBlockH11( 1, 15, &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 1, 15, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 1, 15, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 1, 15, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 1, 15, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 1, 16 );\nacado_setBlockH11( 1, 16, &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 1, 16, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 1, 16, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 1, 16, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 1, 17 );\nacado_setBlockH11( 1, 17, &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 1, 17, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 1, 17, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 1, 18 );\nacado_setBlockH11( 1, 18, &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 1, 18, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 1, 19 );\nacado_setBlockH11( 1, 19, &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 2, 2, &(acadoWorkspace.R1[ 2 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 15 ]), &(acadoWorkspace.QE[ 15 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 24 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QE[ 36 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.QE[ 51 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QE[ 69 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 90 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 114 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 141 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 171 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 204 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 240 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 279 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 321 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 366 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 414 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 465 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 519 ]) );\nacado_setBlockH11( 2, 2, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 576 ]) );\n\nacado_zeroBlockH11( 2, 3 );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QE[ 27 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QE[ 39 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.QE[ 54 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 93 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 117 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 174 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 207 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 243 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 282 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 369 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 417 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 522 ]) );\nacado_setBlockH11( 2, 3, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 579 ]) );\n\nacado_zeroBlockH11( 2, 4 );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QE[ 42 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.QE[ 57 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QE[ 75 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 147 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 177 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 210 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 246 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 285 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 327 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 471 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 525 ]) );\nacado_setBlockH11( 2, 4, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 582 ]) );\n\nacado_zeroBlockH11( 2, 5 );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_setBlockH11( 2, 5, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 585 ]) );\n\nacado_zeroBlockH11( 2, 6 );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 2, 6, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 2, 7 );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 2, 7, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 2, 8 );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 2, 8, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 2, 9 );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 2, 9, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 2, 10 );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 2, 10, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 2, 11 );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 2, 11, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 2, 12 );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 2, 12, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 2, 13 );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 2, 13, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 2, 14 );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 2, 14, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 2, 15 );\nacado_setBlockH11( 2, 15, &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 2, 15, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 2, 15, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 2, 15, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 2, 15, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 2, 16 );\nacado_setBlockH11( 2, 16, &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 2, 16, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 2, 16, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 2, 16, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 2, 17 );\nacado_setBlockH11( 2, 17, &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 2, 17, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 2, 17, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 2, 18 );\nacado_setBlockH11( 2, 18, &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 2, 18, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 2, 19 );\nacado_setBlockH11( 2, 19, &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 3, 3, &(acadoWorkspace.R1[ 3 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 27 ]), &(acadoWorkspace.QE[ 27 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 39 ]), &(acadoWorkspace.QE[ 39 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.QE[ 54 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 72 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QE[ 93 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 117 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 144 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 174 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 207 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 243 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 282 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 324 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 369 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 417 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 468 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 522 ]) );\nacado_setBlockH11( 3, 3, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 579 ]) );\n\nacado_zeroBlockH11( 3, 4 );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 39 ]), &(acadoWorkspace.QE[ 42 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.QE[ 57 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 75 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 147 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 177 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 210 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 246 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 285 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 327 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 471 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 525 ]) );\nacado_setBlockH11( 3, 4, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 582 ]) );\n\nacado_zeroBlockH11( 3, 5 );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_setBlockH11( 3, 5, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 585 ]) );\n\nacado_zeroBlockH11( 3, 6 );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 3, 6, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 3, 7 );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 3, 7, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 3, 8 );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 3, 8, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 3, 9 );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 3, 9, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 3, 10 );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 3, 10, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 3, 11 );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 3, 11, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 3, 12 );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 3, 12, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 3, 13 );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 3, 13, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 3, 14 );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 3, 14, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 3, 15 );\nacado_setBlockH11( 3, 15, &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 3, 15, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 3, 15, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 3, 15, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 3, 15, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 3, 16 );\nacado_setBlockH11( 3, 16, &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 3, 16, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 3, 16, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 3, 16, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 3, 17 );\nacado_setBlockH11( 3, 17, &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 3, 17, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 3, 17, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 3, 18 );\nacado_setBlockH11( 3, 18, &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 3, 18, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 3, 19 );\nacado_setBlockH11( 3, 19, &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 4, 4, &(acadoWorkspace.R1[ 4 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 42 ]), &(acadoWorkspace.QE[ 42 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 57 ]), &(acadoWorkspace.QE[ 57 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.QE[ 75 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 96 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 120 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 147 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 177 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 210 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 246 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 285 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 327 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 372 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 420 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 471 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 525 ]) );\nacado_setBlockH11( 4, 4, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 582 ]) );\n\nacado_zeroBlockH11( 4, 5 );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 57 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_setBlockH11( 4, 5, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 585 ]) );\n\nacado_zeroBlockH11( 4, 6 );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 4, 6, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 4, 7 );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 4, 7, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 4, 8 );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 4, 8, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 4, 9 );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 4, 9, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 4, 10 );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 4, 10, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 4, 11 );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 4, 11, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 4, 12 );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 4, 12, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 4, 13 );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 4, 13, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 4, 14 );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 4, 14, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 4, 15 );\nacado_setBlockH11( 4, 15, &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 4, 15, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 4, 15, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 4, 15, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 4, 15, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 4, 16 );\nacado_setBlockH11( 4, 16, &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 4, 16, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 4, 16, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 4, 16, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 4, 17 );\nacado_setBlockH11( 4, 17, &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 4, 17, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 4, 17, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 4, 18 );\nacado_setBlockH11( 4, 18, &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 4, 18, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 4, 19 );\nacado_setBlockH11( 4, 19, &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 5, 5, &(acadoWorkspace.R1[ 5 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QE[ 60 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 78 ]), &(acadoWorkspace.QE[ 78 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.QE[ 99 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.QE[ 123 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QE[ 150 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 180 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 213 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 249 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 288 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 330 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 375 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 423 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 474 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 528 ]) );\nacado_setBlockH11( 5, 5, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 585 ]) );\n\nacado_zeroBlockH11( 5, 6 );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 78 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 5, 6, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 5, 7 );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 5, 7, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 5, 8 );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 5, 8, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 5, 9 );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 5, 9, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 5, 10 );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 5, 10, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 5, 11 );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 5, 11, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 5, 12 );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 5, 12, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 5, 13 );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 5, 13, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 5, 14 );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 5, 14, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 5, 15 );\nacado_setBlockH11( 5, 15, &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 5, 15, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 5, 15, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 5, 15, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 5, 15, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 5, 16 );\nacado_setBlockH11( 5, 16, &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 5, 16, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 5, 16, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 5, 16, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 5, 17 );\nacado_setBlockH11( 5, 17, &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 5, 17, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 5, 17, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 5, 18 );\nacado_setBlockH11( 5, 18, &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 5, 18, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 5, 19 );\nacado_setBlockH11( 5, 19, &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 6, 6, &(acadoWorkspace.R1[ 6 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 81 ]), &(acadoWorkspace.QE[ 81 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 102 ]), &(acadoWorkspace.QE[ 102 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.QE[ 126 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.QE[ 153 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QE[ 183 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 216 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 252 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 291 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 333 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 378 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 426 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 477 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 531 ]) );\nacado_setBlockH11( 6, 6, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 588 ]) );\n\nacado_zeroBlockH11( 6, 7 );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 102 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 6, 7, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 6, 8 );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 6, 8, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 6, 9 );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 6, 9, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 6, 10 );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 6, 10, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 6, 11 );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 6, 11, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 6, 12 );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 6, 12, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 6, 13 );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 6, 13, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 6, 14 );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 6, 14, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 6, 15 );\nacado_setBlockH11( 6, 15, &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 6, 15, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 6, 15, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 6, 15, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 6, 15, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 6, 16 );\nacado_setBlockH11( 6, 16, &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 6, 16, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 6, 16, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 6, 16, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 6, 17 );\nacado_setBlockH11( 6, 17, &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 6, 17, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 6, 17, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 6, 18 );\nacado_setBlockH11( 6, 18, &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 6, 18, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 6, 19 );\nacado_setBlockH11( 6, 19, &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 7, 7, &(acadoWorkspace.R1[ 7 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 105 ]), &(acadoWorkspace.QE[ 105 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 129 ]), &(acadoWorkspace.QE[ 129 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 156 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.QE[ 186 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QE[ 219 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 255 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 294 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 336 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 381 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 429 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 480 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 534 ]) );\nacado_setBlockH11( 7, 7, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 591 ]) );\n\nacado_zeroBlockH11( 7, 8 );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 129 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 7, 8, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 7, 9 );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 7, 9, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 7, 10 );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 7, 10, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 7, 11 );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 7, 11, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 7, 12 );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 7, 12, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 7, 13 );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 7, 13, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 7, 14 );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 7, 14, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 7, 15 );\nacado_setBlockH11( 7, 15, &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 7, 15, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 7, 15, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 7, 15, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 7, 15, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 7, 16 );\nacado_setBlockH11( 7, 16, &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 7, 16, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 7, 16, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 7, 16, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 7, 17 );\nacado_setBlockH11( 7, 17, &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 7, 17, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 7, 17, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 7, 18 );\nacado_setBlockH11( 7, 18, &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 7, 18, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 7, 19 );\nacado_setBlockH11( 7, 19, &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 8, 8, &(acadoWorkspace.R1[ 8 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QE[ 132 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 159 ]), &(acadoWorkspace.QE[ 159 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 189 ]), &(acadoWorkspace.QE[ 189 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.QE[ 222 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QE[ 258 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 297 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 339 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 384 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 432 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 483 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 537 ]) );\nacado_setBlockH11( 8, 8, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 594 ]) );\n\nacado_zeroBlockH11( 8, 9 );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 159 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 189 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 8, 9, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 8, 10 );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 189 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 8, 10, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 8, 11 );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 8, 11, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 8, 12 );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 8, 12, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 8, 13 );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 8, 13, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 8, 14 );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 8, 14, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 8, 15 );\nacado_setBlockH11( 8, 15, &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 8, 15, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 8, 15, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 8, 15, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 8, 15, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 8, 16 );\nacado_setBlockH11( 8, 16, &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 8, 16, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 8, 16, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 8, 16, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 8, 17 );\nacado_setBlockH11( 8, 17, &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 8, 17, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 8, 17, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 8, 18 );\nacado_setBlockH11( 8, 18, &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 8, 18, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 8, 19 );\nacado_setBlockH11( 8, 19, &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 9, 9, &(acadoWorkspace.R1[ 9 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 162 ]), &(acadoWorkspace.QE[ 162 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 192 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 225 ]), &(acadoWorkspace.QE[ 225 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.QE[ 261 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 300 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 342 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 387 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 435 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 486 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 540 ]) );\nacado_setBlockH11( 9, 9, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 597 ]) );\n\nacado_zeroBlockH11( 9, 10 );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 225 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 9, 10, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 9, 11 );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 225 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 9, 11, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 9, 12 );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 9, 12, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 9, 13 );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 9, 13, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 9, 14 );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 9, 14, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 9, 15 );\nacado_setBlockH11( 9, 15, &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 9, 15, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 9, 15, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 9, 15, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 9, 15, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 9, 16 );\nacado_setBlockH11( 9, 16, &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 9, 16, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 9, 16, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 9, 16, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 9, 17 );\nacado_setBlockH11( 9, 17, &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 9, 17, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 9, 17, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 9, 18 );\nacado_setBlockH11( 9, 18, &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 9, 18, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 9, 19 );\nacado_setBlockH11( 9, 19, &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 10, 10, &(acadoWorkspace.R1[ 10 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 195 ]), &(acadoWorkspace.QE[ 195 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 228 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 264 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.QE[ 303 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QE[ 345 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 390 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 438 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 489 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 543 ]) );\nacado_setBlockH11( 10, 10, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 600 ]) );\n\nacado_zeroBlockH11( 10, 11 );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 10, 11, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 10, 12 );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 10, 12, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 10, 13 );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 10, 13, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 10, 14 );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 10, 14, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 10, 15 );\nacado_setBlockH11( 10, 15, &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 10, 15, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 10, 15, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 10, 15, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 10, 15, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 10, 16 );\nacado_setBlockH11( 10, 16, &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 10, 16, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 10, 16, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 10, 16, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 10, 17 );\nacado_setBlockH11( 10, 17, &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 10, 17, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 10, 17, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 10, 18 );\nacado_setBlockH11( 10, 18, &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 10, 18, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 10, 19 );\nacado_setBlockH11( 10, 19, &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 11, 11, &(acadoWorkspace.R1[ 11 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 231 ]), &(acadoWorkspace.QE[ 231 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 267 ]), &(acadoWorkspace.QE[ 267 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 306 ]), &(acadoWorkspace.QE[ 306 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 348 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QE[ 393 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 441 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 492 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 546 ]) );\nacado_setBlockH11( 11, 11, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 603 ]) );\n\nacado_zeroBlockH11( 11, 12 );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 267 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 306 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 11, 12, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 11, 13 );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 306 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 11, 13, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 11, 14 );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 11, 14, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 11, 15 );\nacado_setBlockH11( 11, 15, &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 11, 15, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 11, 15, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 11, 15, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 11, 15, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 11, 16 );\nacado_setBlockH11( 11, 16, &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 11, 16, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 11, 16, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 11, 16, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 11, 17 );\nacado_setBlockH11( 11, 17, &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 11, 17, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 11, 17, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 11, 18 );\nacado_setBlockH11( 11, 18, &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 11, 18, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 11, 19 );\nacado_setBlockH11( 11, 19, &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 12, 12, &(acadoWorkspace.R1[ 12 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 270 ]), &(acadoWorkspace.QE[ 270 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 309 ]), &(acadoWorkspace.QE[ 309 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 351 ]), &(acadoWorkspace.QE[ 351 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 396 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 444 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 495 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 549 ]) );\nacado_setBlockH11( 12, 12, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 606 ]) );\n\nacado_zeroBlockH11( 12, 13 );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 309 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 351 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 12, 13, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 12, 14 );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 351 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 12, 14, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 12, 15 );\nacado_setBlockH11( 12, 15, &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 12, 15, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 12, 15, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 12, 15, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 12, 15, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 12, 16 );\nacado_setBlockH11( 12, 16, &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 12, 16, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 12, 16, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 12, 16, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 12, 17 );\nacado_setBlockH11( 12, 17, &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 12, 17, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 12, 17, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 12, 18 );\nacado_setBlockH11( 12, 18, &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 12, 18, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 12, 19 );\nacado_setBlockH11( 12, 19, &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 13, 13, &(acadoWorkspace.R1[ 13 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QE[ 312 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 354 ]), &(acadoWorkspace.QE[ 354 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 399 ]), &(acadoWorkspace.QE[ 399 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.QE[ 447 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QE[ 498 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 552 ]) );\nacado_setBlockH11( 13, 13, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 609 ]) );\n\nacado_zeroBlockH11( 13, 14 );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 354 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 399 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 13, 14, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 13, 15 );\nacado_setBlockH11( 13, 15, &(acadoWorkspace.E[ 399 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 13, 15, &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 13, 15, &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 13, 15, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 13, 15, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 13, 16 );\nacado_setBlockH11( 13, 16, &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 13, 16, &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 13, 16, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 13, 16, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 13, 17 );\nacado_setBlockH11( 13, 17, &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 13, 17, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 13, 17, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 13, 18 );\nacado_setBlockH11( 13, 18, &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 13, 18, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 13, 19 );\nacado_setBlockH11( 13, 19, &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 14, 14, &(acadoWorkspace.R1[ 14 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 357 ]), &(acadoWorkspace.QE[ 357 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 402 ]), &(acadoWorkspace.QE[ 402 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 450 ]), &(acadoWorkspace.QE[ 450 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.QE[ 501 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QE[ 555 ]) );\nacado_setBlockH11( 14, 14, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 612 ]) );\n\nacado_zeroBlockH11( 14, 15 );\nacado_setBlockH11( 14, 15, &(acadoWorkspace.E[ 402 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 14, 15, &(acadoWorkspace.E[ 450 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 14, 15, &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 14, 15, &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 14, 15, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 14, 16 );\nacado_setBlockH11( 14, 16, &(acadoWorkspace.E[ 450 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 14, 16, &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 14, 16, &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 14, 16, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 14, 17 );\nacado_setBlockH11( 14, 17, &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 14, 17, &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 14, 17, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 14, 18 );\nacado_setBlockH11( 14, 18, &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 14, 18, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 14, 19 );\nacado_setBlockH11( 14, 19, &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 15, 15, &(acadoWorkspace.R1[ 15 ]) );\nacado_setBlockH11( 15, 15, &(acadoWorkspace.E[ 405 ]), &(acadoWorkspace.QE[ 405 ]) );\nacado_setBlockH11( 15, 15, &(acadoWorkspace.E[ 453 ]), &(acadoWorkspace.QE[ 453 ]) );\nacado_setBlockH11( 15, 15, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 504 ]) );\nacado_setBlockH11( 15, 15, &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.QE[ 558 ]) );\nacado_setBlockH11( 15, 15, &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QE[ 615 ]) );\n\nacado_zeroBlockH11( 15, 16 );\nacado_setBlockH11( 15, 16, &(acadoWorkspace.E[ 453 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 15, 16, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 15, 16, &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 15, 16, &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 15, 17 );\nacado_setBlockH11( 15, 17, &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 15, 17, &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 15, 17, &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 15, 18 );\nacado_setBlockH11( 15, 18, &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 15, 18, &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 15, 19 );\nacado_setBlockH11( 15, 19, &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 16, 16, &(acadoWorkspace.R1[ 16 ]) );\nacado_setBlockH11( 16, 16, &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QE[ 456 ]) );\nacado_setBlockH11( 16, 16, &(acadoWorkspace.E[ 507 ]), &(acadoWorkspace.QE[ 507 ]) );\nacado_setBlockH11( 16, 16, &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.QE[ 561 ]) );\nacado_setBlockH11( 16, 16, &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.QE[ 618 ]) );\n\nacado_zeroBlockH11( 16, 17 );\nacado_setBlockH11( 16, 17, &(acadoWorkspace.E[ 507 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 16, 17, &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 16, 17, &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 16, 18 );\nacado_setBlockH11( 16, 18, &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 16, 18, &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 16, 19 );\nacado_setBlockH11( 16, 19, &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 17, 17, &(acadoWorkspace.R1[ 17 ]) );\nacado_setBlockH11( 17, 17, &(acadoWorkspace.E[ 510 ]), &(acadoWorkspace.QE[ 510 ]) );\nacado_setBlockH11( 17, 17, &(acadoWorkspace.E[ 564 ]), &(acadoWorkspace.QE[ 564 ]) );\nacado_setBlockH11( 17, 17, &(acadoWorkspace.E[ 621 ]), &(acadoWorkspace.QE[ 621 ]) );\n\nacado_zeroBlockH11( 17, 18 );\nacado_setBlockH11( 17, 18, &(acadoWorkspace.E[ 564 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 17, 18, &(acadoWorkspace.E[ 621 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 17, 19 );\nacado_setBlockH11( 17, 19, &(acadoWorkspace.E[ 621 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 18, 18, &(acadoWorkspace.R1[ 18 ]) );\nacado_setBlockH11( 18, 18, &(acadoWorkspace.E[ 567 ]), &(acadoWorkspace.QE[ 567 ]) );\nacado_setBlockH11( 18, 18, &(acadoWorkspace.E[ 624 ]), &(acadoWorkspace.QE[ 624 ]) );\n\nacado_zeroBlockH11( 18, 19 );\nacado_setBlockH11( 18, 19, &(acadoWorkspace.E[ 624 ]), &(acadoWorkspace.QE[ 627 ]) );\n\nacado_setBlockH11_R1( 19, 19, &(acadoWorkspace.R1[ 19 ]) );\nacado_setBlockH11( 19, 19, &(acadoWorkspace.E[ 627 ]), &(acadoWorkspace.QE[ 627 ]) );\n\n\nacado_copyHTH( 1, 0 );\nacado_copyHTH( 2, 0 );\nacado_copyHTH( 2, 1 );\nacado_copyHTH( 3, 0 );\nacado_copyHTH( 3, 1 );\nacado_copyHTH( 3, 2 );\nacado_copyHTH( 4, 0 );\nacado_copyHTH( 4, 1 );\nacado_copyHTH( 4, 2 );\nacado_copyHTH( 4, 3 );\nacado_copyHTH( 5, 0 );\nacado_copyHTH( 5, 1 );\nacado_copyHTH( 5, 2 );\nacado_copyHTH( 5, 3 );\nacado_copyHTH( 5, 4 );\nacado_copyHTH( 6, 0 );\nacado_copyHTH( 6, 1 );\nacado_copyHTH( 6, 2 );\nacado_copyHTH( 6, 3 );\nacado_copyHTH( 6, 4 );\nacado_copyHTH( 6, 5 );\nacado_copyHTH( 7, 0 );\nacado_copyHTH( 7, 1 );\nacado_copyHTH( 7, 2 );\nacado_copyHTH( 7, 3 );\nacado_copyHTH( 7, 4 );\nacado_copyHTH( 7, 5 );\nacado_copyHTH( 7, 6 );\nacado_copyHTH( 8, 0 );\nacado_copyHTH( 8, 1 );\nacado_copyHTH( 8, 2 );\nacado_copyHTH( 8, 3 );\nacado_copyHTH( 8, 4 );\nacado_copyHTH( 8, 5 );\nacado_copyHTH( 8, 6 );\nacado_copyHTH( 8, 7 );\nacado_copyHTH( 9, 0 );\nacado_copyHTH( 9, 1 );\nacado_copyHTH( 9, 2 );\nacado_copyHTH( 9, 3 );\nacado_copyHTH( 9, 4 );\nacado_copyHTH( 9, 5 );\nacado_copyHTH( 9, 6 );\nacado_copyHTH( 9, 7 );\nacado_copyHTH( 9, 8 );\nacado_copyHTH( 10, 0 );\nacado_copyHTH( 10, 1 );\nacado_copyHTH( 10, 2 );\nacado_copyHTH( 10, 3 );\nacado_copyHTH( 10, 4 );\nacado_copyHTH( 10, 5 );\nacado_copyHTH( 10, 6 );\nacado_copyHTH( 10, 7 );\nacado_copyHTH( 10, 8 );\nacado_copyHTH( 10, 9 );\nacado_copyHTH( 11, 0 );\nacado_copyHTH( 11, 1 );\nacado_copyHTH( 11, 2 );\nacado_copyHTH( 11, 3 );\nacado_copyHTH( 11, 4 );\nacado_copyHTH( 11, 5 );\nacado_copyHTH( 11, 6 );\nacado_copyHTH( 11, 7 );\nacado_copyHTH( 11, 8 );\nacado_copyHTH( 11, 9 );\nacado_copyHTH( 11, 10 );\nacado_copyHTH( 12, 0 );\nacado_copyHTH( 12, 1 );\nacado_copyHTH( 12, 2 );\nacado_copyHTH( 12, 3 );\nacado_copyHTH( 12, 4 );\nacado_copyHTH( 12, 5 );\nacado_copyHTH( 12, 6 );\nacado_copyHTH( 12, 7 );\nacado_copyHTH( 12, 8 );\nacado_copyHTH( 12, 9 );\nacado_copyHTH( 12, 10 );\nacado_copyHTH( 12, 11 );\nacado_copyHTH( 13, 0 );\nacado_copyHTH( 13, 1 );\nacado_copyHTH( 13, 2 );\nacado_copyHTH( 13, 3 );\nacado_copyHTH( 13, 4 );\nacado_copyHTH( 13, 5 );\nacado_copyHTH( 13, 6 );\nacado_copyHTH( 13, 7 );\nacado_copyHTH( 13, 8 );\nacado_copyHTH( 13, 9 );\nacado_copyHTH( 13, 10 );\nacado_copyHTH( 13, 11 );\nacado_copyHTH( 13, 12 );\nacado_copyHTH( 14, 0 );\nacado_copyHTH( 14, 1 );\nacado_copyHTH( 14, 2 );\nacado_copyHTH( 14, 3 );\nacado_copyHTH( 14, 4 );\nacado_copyHTH( 14, 5 );\nacado_copyHTH( 14, 6 );\nacado_copyHTH( 14, 7 );\nacado_copyHTH( 14, 8 );\nacado_copyHTH( 14, 9 );\nacado_copyHTH( 14, 10 );\nacado_copyHTH( 14, 11 );\nacado_copyHTH( 14, 12 );\nacado_copyHTH( 14, 13 );\nacado_copyHTH( 15, 0 );\nacado_copyHTH( 15, 1 );\nacado_copyHTH( 15, 2 );\nacado_copyHTH( 15, 3 );\nacado_copyHTH( 15, 4 );\nacado_copyHTH( 15, 5 );\nacado_copyHTH( 15, 6 );\nacado_copyHTH( 15, 7 );\nacado_copyHTH( 15, 8 );\nacado_copyHTH( 15, 9 );\nacado_copyHTH( 15, 10 );\nacado_copyHTH( 15, 11 );\nacado_copyHTH( 15, 12 );\nacado_copyHTH( 15, 13 );\nacado_copyHTH( 15, 14 );\nacado_copyHTH( 16, 0 );\nacado_copyHTH( 16, 1 );\nacado_copyHTH( 16, 2 );\nacado_copyHTH( 16, 3 );\nacado_copyHTH( 16, 4 );\nacado_copyHTH( 16, 5 );\nacado_copyHTH( 16, 6 );\nacado_copyHTH( 16, 7 );\nacado_copyHTH( 16, 8 );\nacado_copyHTH( 16, 9 );\nacado_copyHTH( 16, 10 );\nacado_copyHTH( 16, 11 );\nacado_copyHTH( 16, 12 );\nacado_copyHTH( 16, 13 );\nacado_copyHTH( 16, 14 );\nacado_copyHTH( 16, 15 );\nacado_copyHTH( 17, 0 );\nacado_copyHTH( 17, 1 );\nacado_copyHTH( 17, 2 );\nacado_copyHTH( 17, 3 );\nacado_copyHTH( 17, 4 );\nacado_copyHTH( 17, 5 );\nacado_copyHTH( 17, 6 );\nacado_copyHTH( 17, 7 );\nacado_copyHTH( 17, 8 );\nacado_copyHTH( 17, 9 );\nacado_copyHTH( 17, 10 );\nacado_copyHTH( 17, 11 );\nacado_copyHTH( 17, 12 );\nacado_copyHTH( 17, 13 );\nacado_copyHTH( 17, 14 );\nacado_copyHTH( 17, 15 );\nacado_copyHTH( 17, 16 );\nacado_copyHTH( 18, 0 );\nacado_copyHTH( 18, 1 );\nacado_copyHTH( 18, 2 );\nacado_copyHTH( 18, 3 );\nacado_copyHTH( 18, 4 );\nacado_copyHTH( 18, 5 );\nacado_copyHTH( 18, 6 );\nacado_copyHTH( 18, 7 );\nacado_copyHTH( 18, 8 );\nacado_copyHTH( 18, 9 );\nacado_copyHTH( 18, 10 );\nacado_copyHTH( 18, 11 );\nacado_copyHTH( 18, 12 );\nacado_copyHTH( 18, 13 );\nacado_copyHTH( 18, 14 );\nacado_copyHTH( 18, 15 );\nacado_copyHTH( 18, 16 );\nacado_copyHTH( 18, 17 );\nacado_copyHTH( 19, 0 );\nacado_copyHTH( 19, 1 );\nacado_copyHTH( 19, 2 );\nacado_copyHTH( 19, 3 );\nacado_copyHTH( 19, 4 );\nacado_copyHTH( 19, 5 );\nacado_copyHTH( 19, 6 );\nacado_copyHTH( 19, 7 );\nacado_copyHTH( 19, 8 );\nacado_copyHTH( 19, 9 );\nacado_copyHTH( 19, 10 );\nacado_copyHTH( 19, 11 );\nacado_copyHTH( 19, 12 );\nacado_copyHTH( 19, 13 );\nacado_copyHTH( 19, 14 );\nacado_copyHTH( 19, 15 );\nacado_copyHTH( 19, 16 );\nacado_copyHTH( 19, 17 );\nacado_copyHTH( 19, 18 );\n\nacadoWorkspace.H[69] = acadoWorkspace.H10[0];\nacadoWorkspace.H[70] = acadoWorkspace.H10[1];\nacadoWorkspace.H[71] = acadoWorkspace.H10[2];\nacadoWorkspace.H[92] = acadoWorkspace.H10[3];\nacadoWorkspace.H[93] = acadoWorkspace.H10[4];\nacadoWorkspace.H[94] = acadoWorkspace.H10[5];\nacadoWorkspace.H[115] = acadoWorkspace.H10[6];\nacadoWorkspace.H[116] = acadoWorkspace.H10[7];\nacadoWorkspace.H[117] = acadoWorkspace.H10[8];\nacadoWorkspace.H[138] = acadoWorkspace.H10[9];\nacadoWorkspace.H[139] = acadoWorkspace.H10[10];\nacadoWorkspace.H[140] = acadoWorkspace.H10[11];\nacadoWorkspace.H[161] = acadoWorkspace.H10[12];\nacadoWorkspace.H[162] = acadoWorkspace.H10[13];\nacadoWorkspace.H[163] = acadoWorkspace.H10[14];\nacadoWorkspace.H[184] = acadoWorkspace.H10[15];\nacadoWorkspace.H[185] = acadoWorkspace.H10[16];\nacadoWorkspace.H[186] = acadoWorkspace.H10[17];\nacadoWorkspace.H[207] = acadoWorkspace.H10[18];\nacadoWorkspace.H[208] = acadoWorkspace.H10[19];\nacadoWorkspace.H[209] = acadoWorkspace.H10[20];\nacadoWorkspace.H[230] = acadoWorkspace.H10[21];\nacadoWorkspace.H[231] = acadoWorkspace.H10[22];\nacadoWorkspace.H[232] = acadoWorkspace.H10[23];\nacadoWorkspace.H[253] = acadoWorkspace.H10[24];\nacadoWorkspace.H[254] = acadoWorkspace.H10[25];\nacadoWorkspace.H[255] = acadoWorkspace.H10[26];\nacadoWorkspace.H[276] = acadoWorkspace.H10[27];\nacadoWorkspace.H[277] = acadoWorkspace.H10[28];\nacadoWorkspace.H[278] = acadoWorkspace.H10[29];\nacadoWorkspace.H[299] = acadoWorkspace.H10[30];\nacadoWorkspace.H[300] = acadoWorkspace.H10[31];\nacadoWorkspace.H[301] = acadoWorkspace.H10[32];\nacadoWorkspace.H[322] = acadoWorkspace.H10[33];\nacadoWorkspace.H[323] = acadoWorkspace.H10[34];\nacadoWorkspace.H[324] = acadoWorkspace.H10[35];\nacadoWorkspace.H[345] = acadoWorkspace.H10[36];\nacadoWorkspace.H[346] = acadoWorkspace.H10[37];\nacadoWorkspace.H[347] = acadoWorkspace.H10[38];\nacadoWorkspace.H[368] = acadoWorkspace.H10[39];\nacadoWorkspace.H[369] = acadoWorkspace.H10[40];\nacadoWorkspace.H[370] = acadoWorkspace.H10[41];\nacadoWorkspace.H[391] = acadoWorkspace.H10[42];\nacadoWorkspace.H[392] = acadoWorkspace.H10[43];\nacadoWorkspace.H[393] = acadoWorkspace.H10[44];\nacadoWorkspace.H[414] = acadoWorkspace.H10[45];\nacadoWorkspace.H[415] = acadoWorkspace.H10[46];\nacadoWorkspace.H[416] = acadoWorkspace.H10[47];\nacadoWorkspace.H[437] = acadoWorkspace.H10[48];\nacadoWorkspace.H[438] = acadoWorkspace.H10[49];\nacadoWorkspace.H[439] = acadoWorkspace.H10[50];\nacadoWorkspace.H[460] = acadoWorkspace.H10[51];\nacadoWorkspace.H[461] = acadoWorkspace.H10[52];\nacadoWorkspace.H[462] = acadoWorkspace.H10[53];\nacadoWorkspace.H[483] = acadoWorkspace.H10[54];\nacadoWorkspace.H[484] = acadoWorkspace.H10[55];\nacadoWorkspace.H[485] = acadoWorkspace.H10[56];\nacadoWorkspace.H[506] = acadoWorkspace.H10[57];\nacadoWorkspace.H[507] = acadoWorkspace.H10[58];\nacadoWorkspace.H[508] = acadoWorkspace.H10[59];\n\nacado_multQ1d( &(acadoWorkspace.Q1[ 9 ]), acadoWorkspace.d, acadoWorkspace.Qd );\nacado_multQ1d( &(acadoWorkspace.Q1[ 18 ]), &(acadoWorkspace.d[ 3 ]), &(acadoWorkspace.Qd[ 3 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 27 ]), &(acadoWorkspace.d[ 6 ]), &(acadoWorkspace.Qd[ 6 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 36 ]), &(acadoWorkspace.d[ 9 ]), &(acadoWorkspace.Qd[ 9 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 45 ]), &(acadoWorkspace.d[ 12 ]), &(acadoWorkspace.Qd[ 12 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 54 ]), &(acadoWorkspace.d[ 15 ]), &(acadoWorkspace.Qd[ 15 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 63 ]), &(acadoWorkspace.d[ 18 ]), &(acadoWorkspace.Qd[ 18 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 72 ]), &(acadoWorkspace.d[ 21 ]), &(acadoWorkspace.Qd[ 21 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 81 ]), &(acadoWorkspace.d[ 24 ]), &(acadoWorkspace.Qd[ 24 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 90 ]), &(acadoWorkspace.d[ 27 ]), &(acadoWorkspace.Qd[ 27 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 99 ]), &(acadoWorkspace.d[ 30 ]), &(acadoWorkspace.Qd[ 30 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 108 ]), &(acadoWorkspace.d[ 33 ]), &(acadoWorkspace.Qd[ 33 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 117 ]), &(acadoWorkspace.d[ 36 ]), &(acadoWorkspace.Qd[ 36 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 126 ]), &(acadoWorkspace.d[ 39 ]), &(acadoWorkspace.Qd[ 39 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 135 ]), &(acadoWorkspace.d[ 42 ]), &(acadoWorkspace.Qd[ 42 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.d[ 45 ]), &(acadoWorkspace.Qd[ 45 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 153 ]), &(acadoWorkspace.d[ 48 ]), &(acadoWorkspace.Qd[ 48 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 162 ]), &(acadoWorkspace.d[ 51 ]), &(acadoWorkspace.Qd[ 51 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 171 ]), &(acadoWorkspace.d[ 54 ]), &(acadoWorkspace.Qd[ 54 ]) );\nacado_multQN1d( acadoWorkspace.QN1, &(acadoWorkspace.d[ 57 ]), &(acadoWorkspace.Qd[ 57 ]) );\n\nacado_macCTSlx( acadoWorkspace.evGx, acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 9 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 18 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 27 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 36 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 45 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 54 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 63 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 72 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 81 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 90 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 99 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 108 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 117 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 126 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 135 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 153 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 162 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 171 ]), acadoWorkspace.g );\nacado_macETSlu( acadoWorkspace.QE, &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 3 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 9 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 18 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 30 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 45 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 63 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 84 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 108 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 135 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 165 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 198 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 234 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 273 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 315 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 360 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 408 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 459 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 513 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 570 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 6 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 12 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 21 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 33 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 48 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 66 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 87 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 111 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 138 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 168 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 201 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 237 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 276 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 318 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 363 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 411 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 462 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 516 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 573 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 15 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 24 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 36 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 51 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 69 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 90 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 114 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 141 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 171 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 204 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 240 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 279 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 321 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 366 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 414 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 465 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 519 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 576 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 27 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 39 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 54 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 72 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 93 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 117 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 144 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 174 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 207 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 243 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 282 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 324 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 369 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 417 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 468 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 522 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 579 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 42 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 57 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 75 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 96 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 120 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 147 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 177 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 210 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 246 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 285 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 327 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 372 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 420 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 471 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 525 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 582 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 60 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 78 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 99 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 123 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 150 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 180 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 213 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 249 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 288 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 330 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 375 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 423 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 474 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 528 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 585 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 81 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 102 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 126 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 153 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 183 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 216 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 252 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 291 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 333 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 378 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 426 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 477 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 531 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 588 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 105 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 129 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 156 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 186 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 219 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 255 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 294 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 336 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 381 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 429 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 480 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 534 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 591 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 132 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 159 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 189 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 222 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 258 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 297 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 339 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 384 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 432 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 483 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 537 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 594 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 162 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 192 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 225 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 261 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 300 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 342 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 387 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 435 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 486 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 540 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 597 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 195 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 228 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 264 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 303 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 345 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 390 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 438 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 489 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 543 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 600 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 231 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 267 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 306 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 348 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 393 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 441 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 492 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 546 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 603 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 270 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 309 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 351 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 396 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 444 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 495 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 549 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 606 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 312 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 354 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 399 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 447 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 498 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 552 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 609 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 357 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 402 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 450 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 501 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 555 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 612 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 405 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 453 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 504 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 558 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 615 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 456 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 507 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 561 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 618 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 510 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 564 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 621 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 567 ]), &(acadoWorkspace.g[ 21 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 624 ]), &(acadoWorkspace.g[ 21 ]) );\nacado_macETSlu( &(acadoWorkspace.QE[ 627 ]), &(acadoWorkspace.g[ 22 ]) );\nacadoWorkspace.lb[3] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[0];\nacadoWorkspace.lb[4] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[1];\nacadoWorkspace.lb[5] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[2];\nacadoWorkspace.lb[6] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[3];\nacadoWorkspace.lb[7] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[4];\nacadoWorkspace.lb[8] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[5];\nacadoWorkspace.lb[9] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[6];\nacadoWorkspace.lb[10] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[7];\nacadoWorkspace.lb[11] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[8];\nacadoWorkspace.lb[12] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[9];\nacadoWorkspace.lb[13] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[10];\nacadoWorkspace.lb[14] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[11];\nacadoWorkspace.lb[15] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[12];\nacadoWorkspace.lb[16] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[13];\nacadoWorkspace.lb[17] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[14];\nacadoWorkspace.lb[18] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[15];\nacadoWorkspace.lb[19] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[16];\nacadoWorkspace.lb[20] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[17];\nacadoWorkspace.lb[21] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[18];\nacadoWorkspace.lb[22] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[19];\nacadoWorkspace.ub[3] = (real_t)1.0000000000000000e+12 - acadoVariables.u[0];\nacadoWorkspace.ub[4] = (real_t)1.0000000000000000e+12 - acadoVariables.u[1];\nacadoWorkspace.ub[5] = (real_t)1.0000000000000000e+12 - acadoVariables.u[2];\nacadoWorkspace.ub[6] = (real_t)1.0000000000000000e+12 - acadoVariables.u[3];\nacadoWorkspace.ub[7] = (real_t)1.0000000000000000e+12 - acadoVariables.u[4];\nacadoWorkspace.ub[8] = (real_t)1.0000000000000000e+12 - acadoVariables.u[5];\nacadoWorkspace.ub[9] = (real_t)1.0000000000000000e+12 - acadoVariables.u[6];\nacadoWorkspace.ub[10] = (real_t)1.0000000000000000e+12 - acadoVariables.u[7];\nacadoWorkspace.ub[11] = (real_t)1.0000000000000000e+12 - acadoVariables.u[8];\nacadoWorkspace.ub[12] = (real_t)1.0000000000000000e+12 - acadoVariables.u[9];\nacadoWorkspace.ub[13] = (real_t)1.0000000000000000e+12 - acadoVariables.u[10];\nacadoWorkspace.ub[14] = (real_t)1.0000000000000000e+12 - acadoVariables.u[11];\nacadoWorkspace.ub[15] = (real_t)1.0000000000000000e+12 - acadoVariables.u[12];\nacadoWorkspace.ub[16] = (real_t)1.0000000000000000e+12 - acadoVariables.u[13];\nacadoWorkspace.ub[17] = (real_t)1.0000000000000000e+12 - acadoVariables.u[14];\nacadoWorkspace.ub[18] = (real_t)1.0000000000000000e+12 - acadoVariables.u[15];\nacadoWorkspace.ub[19] = (real_t)1.0000000000000000e+12 - acadoVariables.u[16];\nacadoWorkspace.ub[20] = (real_t)1.0000000000000000e+12 - acadoVariables.u[17];\nacadoWorkspace.ub[21] = (real_t)1.0000000000000000e+12 - acadoVariables.u[18];\nacadoWorkspace.ub[22] = (real_t)1.0000000000000000e+12 - acadoVariables.u[19];\n\nfor (lRun1 = 0; lRun1 < 20; ++lRun1)\n{\nlRun3 = xBoundIndices[ lRun1 ] - 3;\nlRun4 = ((lRun3) / (3)) + (1);\nacadoWorkspace.A[lRun1 * 23] = acadoWorkspace.evGx[lRun3 * 3];\nacadoWorkspace.A[lRun1 * 23 + 1] = acadoWorkspace.evGx[lRun3 * 3 + 1];\nacadoWorkspace.A[lRun1 * 23 + 2] = acadoWorkspace.evGx[lRun3 * 3 + 2];\nfor (lRun2 = 0; lRun2 < lRun4; ++lRun2)\n{\nlRun5 = (((((lRun4) * (lRun4-1)) / (2)) + (lRun2)) * (3)) + ((lRun3) % (3));\nacadoWorkspace.A[(lRun1 * 23) + (lRun2 + 3)] = acadoWorkspace.E[lRun5];\n}\n}\n\n}\n\nvoid acado_condenseFdb(  )\n{\nreal_t tmp;\n\nacadoWorkspace.Dx0[0] = acadoVariables.x0[0] - acadoVariables.x[0];\nacadoWorkspace.Dx0[1] = acadoVariables.x0[1] - acadoVariables.x[1];\nacadoWorkspace.Dx0[2] = acadoVariables.x0[2] - acadoVariables.x[2];\n\nacadoWorkspace.Dy[0] -= acadoVariables.y[0];\nacadoWorkspace.Dy[1] -= acadoVariables.y[1];\nacadoWorkspace.Dy[2] -= acadoVariables.y[2];\nacadoWorkspace.Dy[3] -= acadoVariables.y[3];\nacadoWorkspace.Dy[4] -= acadoVariables.y[4];\nacadoWorkspace.Dy[5] -= acadoVariables.y[5];\nacadoWorkspace.Dy[6] -= acadoVariables.y[6];\nacadoWorkspace.Dy[7] -= acadoVariables.y[7];\nacadoWorkspace.Dy[8] -= acadoVariables.y[8];\nacadoWorkspace.Dy[9] -= acadoVariables.y[9];\nacadoWorkspace.Dy[10] -= acadoVariables.y[10];\nacadoWorkspace.Dy[11] -= acadoVariables.y[11];\nacadoWorkspace.Dy[12] -= acadoVariables.y[12];\nacadoWorkspace.Dy[13] -= acadoVariables.y[13];\nacadoWorkspace.Dy[14] -= acadoVariables.y[14];\nacadoWorkspace.Dy[15] -= acadoVariables.y[15];\nacadoWorkspace.Dy[16] -= acadoVariables.y[16];\nacadoWorkspace.Dy[17] -= acadoVariables.y[17];\nacadoWorkspace.Dy[18] -= acadoVariables.y[18];\nacadoWorkspace.Dy[19] -= acadoVariables.y[19];\nacadoWorkspace.Dy[20] -= acadoVariables.y[20];\nacadoWorkspace.Dy[21] -= acadoVariables.y[21];\nacadoWorkspace.Dy[22] -= acadoVariables.y[22];\nacadoWorkspace.Dy[23] -= acadoVariables.y[23];\nacadoWorkspace.Dy[24] -= acadoVariables.y[24];\nacadoWorkspace.Dy[25] -= acadoVariables.y[25];\nacadoWorkspace.Dy[26] -= acadoVariables.y[26];\nacadoWorkspace.Dy[27] -= acadoVariables.y[27];\nacadoWorkspace.Dy[28] -= acadoVariables.y[28];\nacadoWorkspace.Dy[29] -= acadoVariables.y[29];\nacadoWorkspace.Dy[30] -= acadoVariables.y[30];\nacadoWorkspace.Dy[31] -= acadoVariables.y[31];\nacadoWorkspace.Dy[32] -= acadoVariables.y[32];\nacadoWorkspace.Dy[33] -= acadoVariables.y[33];\nacadoWorkspace.Dy[34] -= acadoVariables.y[34];\nacadoWorkspace.Dy[35] -= acadoVariables.y[35];\nacadoWorkspace.Dy[36] -= acadoVariables.y[36];\nacadoWorkspace.Dy[37] -= acadoVariables.y[37];\nacadoWorkspace.Dy[38] -= acadoVariables.y[38];\nacadoWorkspace.Dy[39] -= acadoVariables.y[39];\nacadoWorkspace.Dy[40] -= acadoVariables.y[40];\nacadoWorkspace.Dy[41] -= acadoVariables.y[41];\nacadoWorkspace.Dy[42] -= acadoVariables.y[42];\nacadoWorkspace.Dy[43] -= acadoVariables.y[43];\nacadoWorkspace.Dy[44] -= acadoVariables.y[44];\nacadoWorkspace.Dy[45] -= acadoVariables.y[45];\nacadoWorkspace.Dy[46] -= acadoVariables.y[46];\nacadoWorkspace.Dy[47] -= acadoVariables.y[47];\nacadoWorkspace.Dy[48] -= acadoVariables.y[48];\nacadoWorkspace.Dy[49] -= acadoVariables.y[49];\nacadoWorkspace.Dy[50] -= acadoVariables.y[50];\nacadoWorkspace.Dy[51] -= acadoVariables.y[51];\nacadoWorkspace.Dy[52] -= acadoVariables.y[52];\nacadoWorkspace.Dy[53] -= acadoVariables.y[53];\nacadoWorkspace.Dy[54] -= acadoVariables.y[54];\nacadoWorkspace.Dy[55] -= acadoVariables.y[55];\nacadoWorkspace.Dy[56] -= acadoVariables.y[56];\nacadoWorkspace.Dy[57] -= acadoVariables.y[57];\nacadoWorkspace.Dy[58] -= acadoVariables.y[58];\nacadoWorkspace.Dy[59] -= acadoVariables.y[59];\nacadoWorkspace.Dy[60] -= acadoVariables.y[60];\nacadoWorkspace.Dy[61] -= acadoVariables.y[61];\nacadoWorkspace.Dy[62] -= acadoVariables.y[62];\nacadoWorkspace.Dy[63] -= acadoVariables.y[63];\nacadoWorkspace.Dy[64] -= acadoVariables.y[64];\nacadoWorkspace.Dy[65] -= acadoVariables.y[65];\nacadoWorkspace.Dy[66] -= acadoVariables.y[66];\nacadoWorkspace.Dy[67] -= acadoVariables.y[67];\nacadoWorkspace.Dy[68] -= acadoVariables.y[68];\nacadoWorkspace.Dy[69] -= acadoVariables.y[69];\nacadoWorkspace.Dy[70] -= acadoVariables.y[70];\nacadoWorkspace.Dy[71] -= acadoVariables.y[71];\nacadoWorkspace.Dy[72] -= acadoVariables.y[72];\nacadoWorkspace.Dy[73] -= acadoVariables.y[73];\nacadoWorkspace.Dy[74] -= acadoVariables.y[74];\nacadoWorkspace.Dy[75] -= acadoVariables.y[75];\nacadoWorkspace.Dy[76] -= acadoVariables.y[76];\nacadoWorkspace.Dy[77] -= acadoVariables.y[77];\nacadoWorkspace.Dy[78] -= acadoVariables.y[78];\nacadoWorkspace.Dy[79] -= acadoVariables.y[79];\nacadoWorkspace.DyN[0] -= acadoVariables.yN[0];\nacadoWorkspace.DyN[1] -= acadoVariables.yN[1];\nacadoWorkspace.DyN[2] -= acadoVariables.yN[2];\n\nacado_multRDy( acadoWorkspace.R2, acadoWorkspace.Dy, &(acadoWorkspace.g[ 3 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 4 ]), &(acadoWorkspace.Dy[ 4 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 8 ]), &(acadoWorkspace.Dy[ 8 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 12 ]), &(acadoWorkspace.Dy[ 12 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 16 ]), &(acadoWorkspace.Dy[ 16 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 20 ]), &(acadoWorkspace.Dy[ 20 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 24 ]), &(acadoWorkspace.Dy[ 24 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 28 ]), &(acadoWorkspace.Dy[ 28 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 32 ]), &(acadoWorkspace.Dy[ 32 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 36 ]), &(acadoWorkspace.Dy[ 36 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 40 ]), &(acadoWorkspace.Dy[ 40 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 44 ]), &(acadoWorkspace.Dy[ 44 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 48 ]), &(acadoWorkspace.Dy[ 48 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 52 ]), &(acadoWorkspace.Dy[ 52 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 56 ]), &(acadoWorkspace.Dy[ 56 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 60 ]), &(acadoWorkspace.Dy[ 60 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 64 ]), &(acadoWorkspace.Dy[ 64 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 68 ]), &(acadoWorkspace.Dy[ 68 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 72 ]), &(acadoWorkspace.Dy[ 72 ]), &(acadoWorkspace.g[ 21 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 76 ]), &(acadoWorkspace.Dy[ 76 ]), &(acadoWorkspace.g[ 22 ]) );\n\nacado_multQDy( acadoWorkspace.Q2, acadoWorkspace.Dy, acadoWorkspace.QDy );\nacado_multQDy( &(acadoWorkspace.Q2[ 12 ]), &(acadoWorkspace.Dy[ 4 ]), &(acadoWorkspace.QDy[ 3 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 24 ]), &(acadoWorkspace.Dy[ 8 ]), &(acadoWorkspace.QDy[ 6 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 36 ]), &(acadoWorkspace.Dy[ 12 ]), &(acadoWorkspace.QDy[ 9 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 48 ]), &(acadoWorkspace.Dy[ 16 ]), &(acadoWorkspace.QDy[ 12 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 60 ]), &(acadoWorkspace.Dy[ 20 ]), &(acadoWorkspace.QDy[ 15 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 72 ]), &(acadoWorkspace.Dy[ 24 ]), &(acadoWorkspace.QDy[ 18 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 84 ]), &(acadoWorkspace.Dy[ 28 ]), &(acadoWorkspace.QDy[ 21 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 96 ]), &(acadoWorkspace.Dy[ 32 ]), &(acadoWorkspace.QDy[ 24 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 108 ]), &(acadoWorkspace.Dy[ 36 ]), &(acadoWorkspace.QDy[ 27 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 120 ]), &(acadoWorkspace.Dy[ 40 ]), &(acadoWorkspace.QDy[ 30 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 132 ]), &(acadoWorkspace.Dy[ 44 ]), &(acadoWorkspace.QDy[ 33 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 144 ]), &(acadoWorkspace.Dy[ 48 ]), &(acadoWorkspace.QDy[ 36 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 156 ]), &(acadoWorkspace.Dy[ 52 ]), &(acadoWorkspace.QDy[ 39 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 168 ]), &(acadoWorkspace.Dy[ 56 ]), &(acadoWorkspace.QDy[ 42 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 180 ]), &(acadoWorkspace.Dy[ 60 ]), &(acadoWorkspace.QDy[ 45 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 192 ]), &(acadoWorkspace.Dy[ 64 ]), &(acadoWorkspace.QDy[ 48 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 204 ]), &(acadoWorkspace.Dy[ 68 ]), &(acadoWorkspace.QDy[ 51 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 216 ]), &(acadoWorkspace.Dy[ 72 ]), &(acadoWorkspace.QDy[ 54 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 228 ]), &(acadoWorkspace.Dy[ 76 ]), &(acadoWorkspace.QDy[ 57 ]) );\n\nacadoWorkspace.QDy[60] = + acadoWorkspace.QN2[0]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[1]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[2]*acadoWorkspace.DyN[2];\nacadoWorkspace.QDy[61] = + acadoWorkspace.QN2[3]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[4]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[5]*acadoWorkspace.DyN[2];\nacadoWorkspace.QDy[62] = + acadoWorkspace.QN2[6]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[7]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[8]*acadoWorkspace.DyN[2];\n\nacadoWorkspace.QDy[3] += acadoWorkspace.Qd[0];\nacadoWorkspace.QDy[4] += acadoWorkspace.Qd[1];\nacadoWorkspace.QDy[5] += acadoWorkspace.Qd[2];\nacadoWorkspace.QDy[6] += acadoWorkspace.Qd[3];\nacadoWorkspace.QDy[7] += acadoWorkspace.Qd[4];\nacadoWorkspace.QDy[8] += acadoWorkspace.Qd[5];\nacadoWorkspace.QDy[9] += acadoWorkspace.Qd[6];\nacadoWorkspace.QDy[10] += acadoWorkspace.Qd[7];\nacadoWorkspace.QDy[11] += acadoWorkspace.Qd[8];\nacadoWorkspace.QDy[12] += acadoWorkspace.Qd[9];\nacadoWorkspace.QDy[13] += acadoWorkspace.Qd[10];\nacadoWorkspace.QDy[14] += acadoWorkspace.Qd[11];\nacadoWorkspace.QDy[15] += acadoWorkspace.Qd[12];\nacadoWorkspace.QDy[16] += acadoWorkspace.Qd[13];\nacadoWorkspace.QDy[17] += acadoWorkspace.Qd[14];\nacadoWorkspace.QDy[18] += acadoWorkspace.Qd[15];\nacadoWorkspace.QDy[19] += acadoWorkspace.Qd[16];\nacadoWorkspace.QDy[20] += acadoWorkspace.Qd[17];\nacadoWorkspace.QDy[21] += acadoWorkspace.Qd[18];\nacadoWorkspace.QDy[22] += acadoWorkspace.Qd[19];\nacadoWorkspace.QDy[23] += acadoWorkspace.Qd[20];\nacadoWorkspace.QDy[24] += acadoWorkspace.Qd[21];\nacadoWorkspace.QDy[25] += acadoWorkspace.Qd[22];\nacadoWorkspace.QDy[26] += acadoWorkspace.Qd[23];\nacadoWorkspace.QDy[27] += acadoWorkspace.Qd[24];\nacadoWorkspace.QDy[28] += acadoWorkspace.Qd[25];\nacadoWorkspace.QDy[29] += acadoWorkspace.Qd[26];\nacadoWorkspace.QDy[30] += acadoWorkspace.Qd[27];\nacadoWorkspace.QDy[31] += acadoWorkspace.Qd[28];\nacadoWorkspace.QDy[32] += acadoWorkspace.Qd[29];\nacadoWorkspace.QDy[33] += acadoWorkspace.Qd[30];\nacadoWorkspace.QDy[34] += acadoWorkspace.Qd[31];\nacadoWorkspace.QDy[35] += acadoWorkspace.Qd[32];\nacadoWorkspace.QDy[36] += acadoWorkspace.Qd[33];\nacadoWorkspace.QDy[37] += acadoWorkspace.Qd[34];\nacadoWorkspace.QDy[38] += acadoWorkspace.Qd[35];\nacadoWorkspace.QDy[39] += acadoWorkspace.Qd[36];\nacadoWorkspace.QDy[40] += acadoWorkspace.Qd[37];\nacadoWorkspace.QDy[41] += acadoWorkspace.Qd[38];\nacadoWorkspace.QDy[42] += acadoWorkspace.Qd[39];\nacadoWorkspace.QDy[43] += acadoWorkspace.Qd[40];\nacadoWorkspace.QDy[44] += acadoWorkspace.Qd[41];\nacadoWorkspace.QDy[45] += acadoWorkspace.Qd[42];\nacadoWorkspace.QDy[46] += acadoWorkspace.Qd[43];\nacadoWorkspace.QDy[47] += acadoWorkspace.Qd[44];\nacadoWorkspace.QDy[48] += acadoWorkspace.Qd[45];\nacadoWorkspace.QDy[49] += acadoWorkspace.Qd[46];\nacadoWorkspace.QDy[50] += acadoWorkspace.Qd[47];\nacadoWorkspace.QDy[51] += acadoWorkspace.Qd[48];\nacadoWorkspace.QDy[52] += acadoWorkspace.Qd[49];\nacadoWorkspace.QDy[53] += acadoWorkspace.Qd[50];\nacadoWorkspace.QDy[54] += acadoWorkspace.Qd[51];\nacadoWorkspace.QDy[55] += acadoWorkspace.Qd[52];\nacadoWorkspace.QDy[56] += acadoWorkspace.Qd[53];\nacadoWorkspace.QDy[57] += acadoWorkspace.Qd[54];\nacadoWorkspace.QDy[58] += acadoWorkspace.Qd[55];\nacadoWorkspace.QDy[59] += acadoWorkspace.Qd[56];\nacadoWorkspace.QDy[60] += acadoWorkspace.Qd[57];\nacadoWorkspace.QDy[61] += acadoWorkspace.Qd[58];\nacadoWorkspace.QDy[62] += acadoWorkspace.Qd[59];\n\nacadoWorkspace.g[0] = + acadoWorkspace.evGx[0]*acadoWorkspace.QDy[3] + acadoWorkspace.evGx[3]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[6]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[9]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[12]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[15]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[18]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[21]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[24]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[27]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[30]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[33]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[36]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[39]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[42]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[45]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[48]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[51]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[54]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[57]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[60]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[63]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[66]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[69]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[72]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[75]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[78]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[81]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[84]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[87]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[90]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[93]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[96]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[99]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[102]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[105]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[108]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[111]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[114]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[117]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[120]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[123]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[126]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[129]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[132]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[135]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[138]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[141]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[144]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[147]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[150]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[153]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[156]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[159]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[162]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[165]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[168]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[171]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[174]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[177]*acadoWorkspace.QDy[62];\nacadoWorkspace.g[1] = + acadoWorkspace.evGx[1]*acadoWorkspace.QDy[3] + acadoWorkspace.evGx[4]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[7]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[10]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[13]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[16]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[19]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[22]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[25]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[28]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[31]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[34]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[37]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[40]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[43]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[46]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[49]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[52]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[55]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[58]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[61]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[64]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[67]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[70]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[73]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[76]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[79]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[82]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[85]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[88]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[91]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[94]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[97]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[100]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[103]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[106]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[109]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[112]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[115]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[118]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[121]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[124]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[127]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[130]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[133]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[136]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[139]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[142]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[145]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[148]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[151]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[154]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[157]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[160]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[163]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[166]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[169]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[172]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[175]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[178]*acadoWorkspace.QDy[62];\nacadoWorkspace.g[2] = + acadoWorkspace.evGx[2]*acadoWorkspace.QDy[3] + acadoWorkspace.evGx[5]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[8]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[11]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[14]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[17]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[20]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[23]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[26]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[29]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[32]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[35]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[38]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[41]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[44]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[47]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[50]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[53]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[56]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[59]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[62]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[65]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[68]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[71]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[74]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[77]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[80]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[83]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[86]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[89]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[92]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[95]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[98]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[101]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[104]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[107]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[110]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[113]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[116]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[119]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[122]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[125]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[128]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[131]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[134]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[137]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[140]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[143]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[146]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[149]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[152]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[155]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[158]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[161]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[164]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[167]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[170]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[173]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[176]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[179]*acadoWorkspace.QDy[62];\n\n\nacado_multEQDy( acadoWorkspace.E, &(acadoWorkspace.QDy[ 3 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 3 ]), &(acadoWorkspace.QDy[ 6 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.QDy[ 9 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.QDy[ 15 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.QDy[ 18 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 165 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 198 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 234 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 273 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 315 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 360 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 408 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 459 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 513 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 3 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 6 ]), &(acadoWorkspace.QDy[ 6 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.QDy[ 9 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.QDy[ 15 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.QDy[ 18 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 138 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 168 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 201 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 237 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 276 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 318 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 363 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 411 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 462 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 516 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 4 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 15 ]), &(acadoWorkspace.QDy[ 9 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.QDy[ 15 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.QDy[ 18 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 141 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 171 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 204 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 240 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 279 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 321 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 366 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 414 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 465 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 519 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 5 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 27 ]), &(acadoWorkspace.QDy[ 12 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 39 ]), &(acadoWorkspace.QDy[ 15 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.QDy[ 18 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 144 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 174 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 207 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 243 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 282 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 324 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 369 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 417 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 468 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 522 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 42 ]), &(acadoWorkspace.QDy[ 15 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 57 ]), &(acadoWorkspace.QDy[ 18 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 147 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 177 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 210 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 246 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 285 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 327 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 372 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 420 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 471 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 525 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 7 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.QDy[ 18 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 78 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 150 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 180 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 213 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 249 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 288 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 330 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 375 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 423 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 474 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 528 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 81 ]), &(acadoWorkspace.QDy[ 21 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 102 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 153 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 183 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 216 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 252 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 291 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 333 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 378 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 426 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 477 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 531 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 9 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 105 ]), &(acadoWorkspace.QDy[ 24 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 129 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 156 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 186 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 219 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 255 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 294 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 336 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 381 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 429 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 480 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 534 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.QDy[ 27 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 159 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 189 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 222 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 258 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 297 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 339 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 384 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 432 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 483 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 537 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 11 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 162 ]), &(acadoWorkspace.QDy[ 30 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 192 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 225 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 261 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 300 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 342 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 387 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 435 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 486 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 540 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 195 ]), &(acadoWorkspace.QDy[ 33 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 228 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 264 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 303 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 345 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 390 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 438 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 489 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 543 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 13 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 231 ]), &(acadoWorkspace.QDy[ 36 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 267 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 306 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 348 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 393 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 441 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 492 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 546 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 270 ]), &(acadoWorkspace.QDy[ 39 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 309 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 351 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 396 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 444 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 495 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 549 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 15 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 312 ]), &(acadoWorkspace.QDy[ 42 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 354 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 399 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 447 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 498 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 552 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 357 ]), &(acadoWorkspace.QDy[ 45 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 402 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 450 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 501 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 555 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 17 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 405 ]), &(acadoWorkspace.QDy[ 48 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 453 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 504 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 456 ]), &(acadoWorkspace.QDy[ 51 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 507 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 19 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 510 ]), &(acadoWorkspace.QDy[ 54 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 564 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 621 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 567 ]), &(acadoWorkspace.QDy[ 57 ]), &(acadoWorkspace.g[ 21 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 624 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 21 ]) );\nacado_multEQDy( &(acadoWorkspace.E[ 627 ]), &(acadoWorkspace.QDy[ 60 ]), &(acadoWorkspace.g[ 22 ]) );\n\nacadoWorkspace.lb[0] = acadoWorkspace.Dx0[0];\nacadoWorkspace.lb[1] = acadoWorkspace.Dx0[1];\nacadoWorkspace.lb[2] = acadoWorkspace.Dx0[2];\nacadoWorkspace.ub[0] = acadoWorkspace.Dx0[0];\nacadoWorkspace.ub[1] = acadoWorkspace.Dx0[1];\nacadoWorkspace.ub[2] = acadoWorkspace.Dx0[2];\ntmp = acadoVariables.x[4] + acadoWorkspace.d[1];\nacadoWorkspace.lbA[0] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[0] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[7] + acadoWorkspace.d[4];\nacadoWorkspace.lbA[1] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[1] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[10] + acadoWorkspace.d[7];\nacadoWorkspace.lbA[2] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[2] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[13] + acadoWorkspace.d[10];\nacadoWorkspace.lbA[3] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[3] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[16] + acadoWorkspace.d[13];\nacadoWorkspace.lbA[4] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[4] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[19] + acadoWorkspace.d[16];\nacadoWorkspace.lbA[5] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[5] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[22] + acadoWorkspace.d[19];\nacadoWorkspace.lbA[6] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[6] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[25] + acadoWorkspace.d[22];\nacadoWorkspace.lbA[7] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[7] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[28] + acadoWorkspace.d[25];\nacadoWorkspace.lbA[8] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[8] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[31] + acadoWorkspace.d[28];\nacadoWorkspace.lbA[9] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[9] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[34] + acadoWorkspace.d[31];\nacadoWorkspace.lbA[10] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[10] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[37] + acadoWorkspace.d[34];\nacadoWorkspace.lbA[11] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[11] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[40] + acadoWorkspace.d[37];\nacadoWorkspace.lbA[12] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[12] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[43] + acadoWorkspace.d[40];\nacadoWorkspace.lbA[13] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[13] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[46] + acadoWorkspace.d[43];\nacadoWorkspace.lbA[14] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[14] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[49] + acadoWorkspace.d[46];\nacadoWorkspace.lbA[15] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[15] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[52] + acadoWorkspace.d[49];\nacadoWorkspace.lbA[16] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[16] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[55] + acadoWorkspace.d[52];\nacadoWorkspace.lbA[17] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[17] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[58] + acadoWorkspace.d[55];\nacadoWorkspace.lbA[18] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[18] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[61] + acadoWorkspace.d[58];\nacadoWorkspace.lbA[19] = (real_t)-1.0000000000000001e-01 - tmp;\nacadoWorkspace.ubA[19] = (real_t)1.0000000000000000e+12 - tmp;\n\n}\n\nvoid acado_expand(  )\n{\nacadoVariables.x[0] += acadoWorkspace.x[0];\nacadoVariables.x[1] += acadoWorkspace.x[1];\nacadoVariables.x[2] += acadoWorkspace.x[2];\n\nacadoVariables.u[0] += acadoWorkspace.x[3];\nacadoVariables.u[1] += acadoWorkspace.x[4];\nacadoVariables.u[2] += acadoWorkspace.x[5];\nacadoVariables.u[3] += acadoWorkspace.x[6];\nacadoVariables.u[4] += acadoWorkspace.x[7];\nacadoVariables.u[5] += acadoWorkspace.x[8];\nacadoVariables.u[6] += acadoWorkspace.x[9];\nacadoVariables.u[7] += acadoWorkspace.x[10];\nacadoVariables.u[8] += acadoWorkspace.x[11];\nacadoVariables.u[9] += acadoWorkspace.x[12];\nacadoVariables.u[10] += acadoWorkspace.x[13];\nacadoVariables.u[11] += acadoWorkspace.x[14];\nacadoVariables.u[12] += acadoWorkspace.x[15];\nacadoVariables.u[13] += acadoWorkspace.x[16];\nacadoVariables.u[14] += acadoWorkspace.x[17];\nacadoVariables.u[15] += acadoWorkspace.x[18];\nacadoVariables.u[16] += acadoWorkspace.x[19];\nacadoVariables.u[17] += acadoWorkspace.x[20];\nacadoVariables.u[18] += acadoWorkspace.x[21];\nacadoVariables.u[19] += acadoWorkspace.x[22];\n\nacadoVariables.x[3] += + acadoWorkspace.evGx[0]*acadoWorkspace.x[0] + acadoWorkspace.evGx[1]*acadoWorkspace.x[1] + acadoWorkspace.evGx[2]*acadoWorkspace.x[2] + acadoWorkspace.d[0];\nacadoVariables.x[4] += + acadoWorkspace.evGx[3]*acadoWorkspace.x[0] + acadoWorkspace.evGx[4]*acadoWorkspace.x[1] + acadoWorkspace.evGx[5]*acadoWorkspace.x[2] + acadoWorkspace.d[1];\nacadoVariables.x[5] += + acadoWorkspace.evGx[6]*acadoWorkspace.x[0] + acadoWorkspace.evGx[7]*acadoWorkspace.x[1] + acadoWorkspace.evGx[8]*acadoWorkspace.x[2] + acadoWorkspace.d[2];\nacadoVariables.x[6] += + acadoWorkspace.evGx[9]*acadoWorkspace.x[0] + acadoWorkspace.evGx[10]*acadoWorkspace.x[1] + acadoWorkspace.evGx[11]*acadoWorkspace.x[2] + acadoWorkspace.d[3];\nacadoVariables.x[7] += + acadoWorkspace.evGx[12]*acadoWorkspace.x[0] + acadoWorkspace.evGx[13]*acadoWorkspace.x[1] + acadoWorkspace.evGx[14]*acadoWorkspace.x[2] + acadoWorkspace.d[4];\nacadoVariables.x[8] += + acadoWorkspace.evGx[15]*acadoWorkspace.x[0] + acadoWorkspace.evGx[16]*acadoWorkspace.x[1] + acadoWorkspace.evGx[17]*acadoWorkspace.x[2] + acadoWorkspace.d[5];\nacadoVariables.x[9] += + acadoWorkspace.evGx[18]*acadoWorkspace.x[0] + acadoWorkspace.evGx[19]*acadoWorkspace.x[1] + acadoWorkspace.evGx[20]*acadoWorkspace.x[2] + acadoWorkspace.d[6];\nacadoVariables.x[10] += + acadoWorkspace.evGx[21]*acadoWorkspace.x[0] + acadoWorkspace.evGx[22]*acadoWorkspace.x[1] + acadoWorkspace.evGx[23]*acadoWorkspace.x[2] + acadoWorkspace.d[7];\nacadoVariables.x[11] += + acadoWorkspace.evGx[24]*acadoWorkspace.x[0] + acadoWorkspace.evGx[25]*acadoWorkspace.x[1] + acadoWorkspace.evGx[26]*acadoWorkspace.x[2] + acadoWorkspace.d[8];\nacadoVariables.x[12] += + acadoWorkspace.evGx[27]*acadoWorkspace.x[0] + acadoWorkspace.evGx[28]*acadoWorkspace.x[1] + acadoWorkspace.evGx[29]*acadoWorkspace.x[2] + acadoWorkspace.d[9];\nacadoVariables.x[13] += + acadoWorkspace.evGx[30]*acadoWorkspace.x[0] + acadoWorkspace.evGx[31]*acadoWorkspace.x[1] + acadoWorkspace.evGx[32]*acadoWorkspace.x[2] + acadoWorkspace.d[10];\nacadoVariables.x[14] += + acadoWorkspace.evGx[33]*acadoWorkspace.x[0] + acadoWorkspace.evGx[34]*acadoWorkspace.x[1] + acadoWorkspace.evGx[35]*acadoWorkspace.x[2] + acadoWorkspace.d[11];\nacadoVariables.x[15] += + acadoWorkspace.evGx[36]*acadoWorkspace.x[0] + acadoWorkspace.evGx[37]*acadoWorkspace.x[1] + acadoWorkspace.evGx[38]*acadoWorkspace.x[2] + acadoWorkspace.d[12];\nacadoVariables.x[16] += + acadoWorkspace.evGx[39]*acadoWorkspace.x[0] + acadoWorkspace.evGx[40]*acadoWorkspace.x[1] + acadoWorkspace.evGx[41]*acadoWorkspace.x[2] + acadoWorkspace.d[13];\nacadoVariables.x[17] += + acadoWorkspace.evGx[42]*acadoWorkspace.x[0] + acadoWorkspace.evGx[43]*acadoWorkspace.x[1] + acadoWorkspace.evGx[44]*acadoWorkspace.x[2] + acadoWorkspace.d[14];\nacadoVariables.x[18] += + acadoWorkspace.evGx[45]*acadoWorkspace.x[0] + acadoWorkspace.evGx[46]*acadoWorkspace.x[1] + acadoWorkspace.evGx[47]*acadoWorkspace.x[2] + acadoWorkspace.d[15];\nacadoVariables.x[19] += + acadoWorkspace.evGx[48]*acadoWorkspace.x[0] + acadoWorkspace.evGx[49]*acadoWorkspace.x[1] + acadoWorkspace.evGx[50]*acadoWorkspace.x[2] + acadoWorkspace.d[16];\nacadoVariables.x[20] += + acadoWorkspace.evGx[51]*acadoWorkspace.x[0] + acadoWorkspace.evGx[52]*acadoWorkspace.x[1] + acadoWorkspace.evGx[53]*acadoWorkspace.x[2] + acadoWorkspace.d[17];\nacadoVariables.x[21] += + acadoWorkspace.evGx[54]*acadoWorkspace.x[0] + acadoWorkspace.evGx[55]*acadoWorkspace.x[1] + acadoWorkspace.evGx[56]*acadoWorkspace.x[2] + acadoWorkspace.d[18];\nacadoVariables.x[22] += + acadoWorkspace.evGx[57]*acadoWorkspace.x[0] + acadoWorkspace.evGx[58]*acadoWorkspace.x[1] + acadoWorkspace.evGx[59]*acadoWorkspace.x[2] + acadoWorkspace.d[19];\nacadoVariables.x[23] += + acadoWorkspace.evGx[60]*acadoWorkspace.x[0] + acadoWorkspace.evGx[61]*acadoWorkspace.x[1] + acadoWorkspace.evGx[62]*acadoWorkspace.x[2] + acadoWorkspace.d[20];\nacadoVariables.x[24] += + acadoWorkspace.evGx[63]*acadoWorkspace.x[0] + acadoWorkspace.evGx[64]*acadoWorkspace.x[1] + acadoWorkspace.evGx[65]*acadoWorkspace.x[2] + acadoWorkspace.d[21];\nacadoVariables.x[25] += + acadoWorkspace.evGx[66]*acadoWorkspace.x[0] + acadoWorkspace.evGx[67]*acadoWorkspace.x[1] + acadoWorkspace.evGx[68]*acadoWorkspace.x[2] + acadoWorkspace.d[22];\nacadoVariables.x[26] += + acadoWorkspace.evGx[69]*acadoWorkspace.x[0] + acadoWorkspace.evGx[70]*acadoWorkspace.x[1] + acadoWorkspace.evGx[71]*acadoWorkspace.x[2] + acadoWorkspace.d[23];\nacadoVariables.x[27] += + acadoWorkspace.evGx[72]*acadoWorkspace.x[0] + acadoWorkspace.evGx[73]*acadoWorkspace.x[1] + acadoWorkspace.evGx[74]*acadoWorkspace.x[2] + acadoWorkspace.d[24];\nacadoVariables.x[28] += + acadoWorkspace.evGx[75]*acadoWorkspace.x[0] + acadoWorkspace.evGx[76]*acadoWorkspace.x[1] + acadoWorkspace.evGx[77]*acadoWorkspace.x[2] + acadoWorkspace.d[25];\nacadoVariables.x[29] += + acadoWorkspace.evGx[78]*acadoWorkspace.x[0] + acadoWorkspace.evGx[79]*acadoWorkspace.x[1] + acadoWorkspace.evGx[80]*acadoWorkspace.x[2] + acadoWorkspace.d[26];\nacadoVariables.x[30] += + acadoWorkspace.evGx[81]*acadoWorkspace.x[0] + acadoWorkspace.evGx[82]*acadoWorkspace.x[1] + acadoWorkspace.evGx[83]*acadoWorkspace.x[2] + acadoWorkspace.d[27];\nacadoVariables.x[31] += + acadoWorkspace.evGx[84]*acadoWorkspace.x[0] + acadoWorkspace.evGx[85]*acadoWorkspace.x[1] + acadoWorkspace.evGx[86]*acadoWorkspace.x[2] + acadoWorkspace.d[28];\nacadoVariables.x[32] += + acadoWorkspace.evGx[87]*acadoWorkspace.x[0] + acadoWorkspace.evGx[88]*acadoWorkspace.x[1] + acadoWorkspace.evGx[89]*acadoWorkspace.x[2] + acadoWorkspace.d[29];\nacadoVariables.x[33] += + acadoWorkspace.evGx[90]*acadoWorkspace.x[0] + acadoWorkspace.evGx[91]*acadoWorkspace.x[1] + acadoWorkspace.evGx[92]*acadoWorkspace.x[2] + acadoWorkspace.d[30];\nacadoVariables.x[34] += + acadoWorkspace.evGx[93]*acadoWorkspace.x[0] + acadoWorkspace.evGx[94]*acadoWorkspace.x[1] + acadoWorkspace.evGx[95]*acadoWorkspace.x[2] + acadoWorkspace.d[31];\nacadoVariables.x[35] += + acadoWorkspace.evGx[96]*acadoWorkspace.x[0] + acadoWorkspace.evGx[97]*acadoWorkspace.x[1] + acadoWorkspace.evGx[98]*acadoWorkspace.x[2] + acadoWorkspace.d[32];\nacadoVariables.x[36] += + acadoWorkspace.evGx[99]*acadoWorkspace.x[0] + acadoWorkspace.evGx[100]*acadoWorkspace.x[1] + acadoWorkspace.evGx[101]*acadoWorkspace.x[2] + acadoWorkspace.d[33];\nacadoVariables.x[37] += + acadoWorkspace.evGx[102]*acadoWorkspace.x[0] + acadoWorkspace.evGx[103]*acadoWorkspace.x[1] + acadoWorkspace.evGx[104]*acadoWorkspace.x[2] + acadoWorkspace.d[34];\nacadoVariables.x[38] += + acadoWorkspace.evGx[105]*acadoWorkspace.x[0] + acadoWorkspace.evGx[106]*acadoWorkspace.x[1] + acadoWorkspace.evGx[107]*acadoWorkspace.x[2] + acadoWorkspace.d[35];\nacadoVariables.x[39] += + acadoWorkspace.evGx[108]*acadoWorkspace.x[0] + acadoWorkspace.evGx[109]*acadoWorkspace.x[1] + acadoWorkspace.evGx[110]*acadoWorkspace.x[2] + acadoWorkspace.d[36];\nacadoVariables.x[40] += + acadoWorkspace.evGx[111]*acadoWorkspace.x[0] + acadoWorkspace.evGx[112]*acadoWorkspace.x[1] + acadoWorkspace.evGx[113]*acadoWorkspace.x[2] + acadoWorkspace.d[37];\nacadoVariables.x[41] += + acadoWorkspace.evGx[114]*acadoWorkspace.x[0] + acadoWorkspace.evGx[115]*acadoWorkspace.x[1] + acadoWorkspace.evGx[116]*acadoWorkspace.x[2] + acadoWorkspace.d[38];\nacadoVariables.x[42] += + acadoWorkspace.evGx[117]*acadoWorkspace.x[0] + acadoWorkspace.evGx[118]*acadoWorkspace.x[1] + acadoWorkspace.evGx[119]*acadoWorkspace.x[2] + acadoWorkspace.d[39];\nacadoVariables.x[43] += + acadoWorkspace.evGx[120]*acadoWorkspace.x[0] + acadoWorkspace.evGx[121]*acadoWorkspace.x[1] + acadoWorkspace.evGx[122]*acadoWorkspace.x[2] + acadoWorkspace.d[40];\nacadoVariables.x[44] += + acadoWorkspace.evGx[123]*acadoWorkspace.x[0] + acadoWorkspace.evGx[124]*acadoWorkspace.x[1] + acadoWorkspace.evGx[125]*acadoWorkspace.x[2] + acadoWorkspace.d[41];\nacadoVariables.x[45] += + acadoWorkspace.evGx[126]*acadoWorkspace.x[0] + acadoWorkspace.evGx[127]*acadoWorkspace.x[1] + acadoWorkspace.evGx[128]*acadoWorkspace.x[2] + acadoWorkspace.d[42];\nacadoVariables.x[46] += + acadoWorkspace.evGx[129]*acadoWorkspace.x[0] + acadoWorkspace.evGx[130]*acadoWorkspace.x[1] + acadoWorkspace.evGx[131]*acadoWorkspace.x[2] + acadoWorkspace.d[43];\nacadoVariables.x[47] += + acadoWorkspace.evGx[132]*acadoWorkspace.x[0] + acadoWorkspace.evGx[133]*acadoWorkspace.x[1] + acadoWorkspace.evGx[134]*acadoWorkspace.x[2] + acadoWorkspace.d[44];\nacadoVariables.x[48] += + acadoWorkspace.evGx[135]*acadoWorkspace.x[0] + acadoWorkspace.evGx[136]*acadoWorkspace.x[1] + acadoWorkspace.evGx[137]*acadoWorkspace.x[2] + acadoWorkspace.d[45];\nacadoVariables.x[49] += + acadoWorkspace.evGx[138]*acadoWorkspace.x[0] + acadoWorkspace.evGx[139]*acadoWorkspace.x[1] + acadoWorkspace.evGx[140]*acadoWorkspace.x[2] + acadoWorkspace.d[46];\nacadoVariables.x[50] += + acadoWorkspace.evGx[141]*acadoWorkspace.x[0] + acadoWorkspace.evGx[142]*acadoWorkspace.x[1] + acadoWorkspace.evGx[143]*acadoWorkspace.x[2] + acadoWorkspace.d[47];\nacadoVariables.x[51] += + acadoWorkspace.evGx[144]*acadoWorkspace.x[0] + acadoWorkspace.evGx[145]*acadoWorkspace.x[1] + acadoWorkspace.evGx[146]*acadoWorkspace.x[2] + acadoWorkspace.d[48];\nacadoVariables.x[52] += + acadoWorkspace.evGx[147]*acadoWorkspace.x[0] + acadoWorkspace.evGx[148]*acadoWorkspace.x[1] + acadoWorkspace.evGx[149]*acadoWorkspace.x[2] + acadoWorkspace.d[49];\nacadoVariables.x[53] += + acadoWorkspace.evGx[150]*acadoWorkspace.x[0] + acadoWorkspace.evGx[151]*acadoWorkspace.x[1] + acadoWorkspace.evGx[152]*acadoWorkspace.x[2] + acadoWorkspace.d[50];\nacadoVariables.x[54] += + acadoWorkspace.evGx[153]*acadoWorkspace.x[0] + acadoWorkspace.evGx[154]*acadoWorkspace.x[1] + acadoWorkspace.evGx[155]*acadoWorkspace.x[2] + acadoWorkspace.d[51];\nacadoVariables.x[55] += + acadoWorkspace.evGx[156]*acadoWorkspace.x[0] + acadoWorkspace.evGx[157]*acadoWorkspace.x[1] + acadoWorkspace.evGx[158]*acadoWorkspace.x[2] + acadoWorkspace.d[52];\nacadoVariables.x[56] += + acadoWorkspace.evGx[159]*acadoWorkspace.x[0] + acadoWorkspace.evGx[160]*acadoWorkspace.x[1] + acadoWorkspace.evGx[161]*acadoWorkspace.x[2] + acadoWorkspace.d[53];\nacadoVariables.x[57] += + acadoWorkspace.evGx[162]*acadoWorkspace.x[0] + acadoWorkspace.evGx[163]*acadoWorkspace.x[1] + acadoWorkspace.evGx[164]*acadoWorkspace.x[2] + acadoWorkspace.d[54];\nacadoVariables.x[58] += + acadoWorkspace.evGx[165]*acadoWorkspace.x[0] + acadoWorkspace.evGx[166]*acadoWorkspace.x[1] + acadoWorkspace.evGx[167]*acadoWorkspace.x[2] + acadoWorkspace.d[55];\nacadoVariables.x[59] += + acadoWorkspace.evGx[168]*acadoWorkspace.x[0] + acadoWorkspace.evGx[169]*acadoWorkspace.x[1] + acadoWorkspace.evGx[170]*acadoWorkspace.x[2] + acadoWorkspace.d[56];\nacadoVariables.x[60] += + acadoWorkspace.evGx[171]*acadoWorkspace.x[0] + acadoWorkspace.evGx[172]*acadoWorkspace.x[1] + acadoWorkspace.evGx[173]*acadoWorkspace.x[2] + acadoWorkspace.d[57];\nacadoVariables.x[61] += + acadoWorkspace.evGx[174]*acadoWorkspace.x[0] + acadoWorkspace.evGx[175]*acadoWorkspace.x[1] + acadoWorkspace.evGx[176]*acadoWorkspace.x[2] + acadoWorkspace.d[58];\nacadoVariables.x[62] += + acadoWorkspace.evGx[177]*acadoWorkspace.x[0] + acadoWorkspace.evGx[178]*acadoWorkspace.x[1] + acadoWorkspace.evGx[179]*acadoWorkspace.x[2] + acadoWorkspace.d[59];\n\nacado_multEDu( acadoWorkspace.E, &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 3 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 3 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 6 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 6 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 6 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 9 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 9 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 12 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 9 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 15 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 9 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 18 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 21 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 24 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 27 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 12 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 30 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 15 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 33 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 15 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 36 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 15 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 39 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 15 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 42 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 15 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 45 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 18 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 48 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 18 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 51 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 18 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 54 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 18 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 57 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 18 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 60 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 18 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 63 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 66 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 69 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 72 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 75 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 78 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 81 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 21 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 84 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 87 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 90 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 93 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 96 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 99 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 102 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 105 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 24 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 108 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 111 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 114 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 117 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 120 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 123 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 126 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 129 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 132 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 27 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 135 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 30 ]) 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);\nacado_multEDu( &(acadoWorkspace.E[ 558 ]), &(acadoWorkspace.x[ 18 ]), &(acadoVariables.x[ 57 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 561 ]), &(acadoWorkspace.x[ 19 ]), &(acadoVariables.x[ 57 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 564 ]), &(acadoWorkspace.x[ 20 ]), &(acadoVariables.x[ 57 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 567 ]), &(acadoWorkspace.x[ 21 ]), &(acadoVariables.x[ 57 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 570 ]), &(acadoWorkspace.x[ 3 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 573 ]), &(acadoWorkspace.x[ 4 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 576 ]), &(acadoWorkspace.x[ 5 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 579 ]), &(acadoWorkspace.x[ 6 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 582 ]), &(acadoWorkspace.x[ 7 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 585 ]), &(acadoWorkspace.x[ 8 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 588 ]), &(acadoWorkspace.x[ 9 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 591 ]), &(acadoWorkspace.x[ 10 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 594 ]), &(acadoWorkspace.x[ 11 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 597 ]), &(acadoWorkspace.x[ 12 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 600 ]), &(acadoWorkspace.x[ 13 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 603 ]), &(acadoWorkspace.x[ 14 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 606 ]), &(acadoWorkspace.x[ 15 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 609 ]), &(acadoWorkspace.x[ 16 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 612 ]), &(acadoWorkspace.x[ 17 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 615 ]), &(acadoWorkspace.x[ 18 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 618 ]), &(acadoWorkspace.x[ 19 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 621 ]), &(acadoWorkspace.x[ 20 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 624 ]), &(acadoWorkspace.x[ 21 ]), &(acadoVariables.x[ 60 ]) );\nacado_multEDu( &(acadoWorkspace.E[ 627 ]), &(acadoWorkspace.x[ 22 ]), &(acadoVariables.x[ 60 ]) );\n}\n\nint acado_preparationStep( double TR )\n{\nint ret;\n\nret = acado_modelSimulation();\nacado_evaluateObjective( TR );\nacado_condensePrep(  );\nreturn ret;\n}\n\nint acado_feedbackStep(  )\n{\nint tmp;\n\nacado_condenseFdb(  );\n\ntmp = acado_solve( );\n\nacado_expand(  );\nreturn tmp;\n}\n\nint acado_initializeSolver(  )\n{\nint ret;\n\n/* This is a function which must be called once before any other function call! */\n\n\nret = 0;\n\nmemset(&acadoWorkspace, 0, sizeof( acadoWorkspace ));\nreturn ret;\n}\n\nvoid acado_initializeNodesByForwardSimulation(  )\n{\nint index;\nfor (index = 0; index < 20; ++index)\n{\nacadoWorkspace.state[0] = acadoVariables.x[index * 3];\nacadoWorkspace.state[1] = acadoVariables.x[index * 3 + 1];\nacadoWorkspace.state[2] = acadoVariables.x[index * 3 + 2];\nacadoWorkspace.state[15] = acadoVariables.u[index];\nacadoWorkspace.state[16] = acadoVariables.od[index * 2];\nacadoWorkspace.state[17] = acadoVariables.od[index * 2 + 1];\n\nacado_integrate(acadoWorkspace.state, index == 0, index);\n\nacadoVariables.x[index * 3 + 3] = acadoWorkspace.state[0];\nacadoVariables.x[index * 3 + 4] = acadoWorkspace.state[1];\nacadoVariables.x[index * 3 + 5] = acadoWorkspace.state[2];\n}\n}\n\nvoid acado_shiftStates( int strategy, real_t* const xEnd, real_t* const uEnd )\n{\nint index;\nfor (index = 0; index < 20; ++index)\n{\nacadoVariables.x[index * 3] = acadoVariables.x[index * 3 + 3];\nacadoVariables.x[index * 3 + 1] = acadoVariables.x[index * 3 + 4];\nacadoVariables.x[index * 3 + 2] = acadoVariables.x[index * 3 + 5];\n}\n\nif (strategy == 1 && xEnd != 0)\n{\nacadoVariables.x[60] = xEnd[0];\nacadoVariables.x[61] = xEnd[1];\nacadoVariables.x[62] = xEnd[2];\n}\nelse if (strategy == 2) \n{\nacadoWorkspace.state[0] = acadoVariables.x[60];\nacadoWorkspace.state[1] = acadoVariables.x[61];\nacadoWorkspace.state[2] = acadoVariables.x[62];\nif (uEnd != 0)\n{\nacadoWorkspace.state[15] = uEnd[0];\n}\nelse\n{\nacadoWorkspace.state[15] = acadoVariables.u[19];\n}\nacadoWorkspace.state[16] = acadoVariables.od[40];\nacadoWorkspace.state[17] = acadoVariables.od[41];\n\nacado_integrate(acadoWorkspace.state, 1, 19);\n\nacadoVariables.x[60] = acadoWorkspace.state[0];\nacadoVariables.x[61] = acadoWorkspace.state[1];\nacadoVariables.x[62] = acadoWorkspace.state[2];\n}\n}\n\nvoid acado_shiftControls( real_t* const uEnd )\n{\nint index;\nfor (index = 0; index < 19; ++index)\n{\nacadoVariables.u[index] = acadoVariables.u[index + 1];\n}\n\nif (uEnd != 0)\n{\nacadoVariables.u[19] = uEnd[0];\n}\n}\n\nreal_t acado_getKKT(  )\n{\nreal_t kkt;\n\nint index;\nreal_t prd;\n\nkkt = + acadoWorkspace.g[0]*acadoWorkspace.x[0] + acadoWorkspace.g[1]*acadoWorkspace.x[1] + acadoWorkspace.g[2]*acadoWorkspace.x[2] + acadoWorkspace.g[3]*acadoWorkspace.x[3] + acadoWorkspace.g[4]*acadoWorkspace.x[4] + acadoWorkspace.g[5]*acadoWorkspace.x[5] + acadoWorkspace.g[6]*acadoWorkspace.x[6] + acadoWorkspace.g[7]*acadoWorkspace.x[7] + acadoWorkspace.g[8]*acadoWorkspace.x[8] + acadoWorkspace.g[9]*acadoWorkspace.x[9] + acadoWorkspace.g[10]*acadoWorkspace.x[10] + acadoWorkspace.g[11]*acadoWorkspace.x[11] + acadoWorkspace.g[12]*acadoWorkspace.x[12] + acadoWorkspace.g[13]*acadoWorkspace.x[13] + acadoWorkspace.g[14]*acadoWorkspace.x[14] + acadoWorkspace.g[15]*acadoWorkspace.x[15] + acadoWorkspace.g[16]*acadoWorkspace.x[16] + acadoWorkspace.g[17]*acadoWorkspace.x[17] + acadoWorkspace.g[18]*acadoWorkspace.x[18] + acadoWorkspace.g[19]*acadoWorkspace.x[19] + acadoWorkspace.g[20]*acadoWorkspace.x[20] + acadoWorkspace.g[21]*acadoWorkspace.x[21] + acadoWorkspace.g[22]*acadoWorkspace.x[22];\nkkt = fabs( kkt );\nfor (index = 0; index < 23; ++index)\n{\nprd = acadoWorkspace.y[index];\nif (prd > 1e-12)\nkkt += fabs(acadoWorkspace.lb[index] * prd);\nelse if (prd < -1e-12)\nkkt += fabs(acadoWorkspace.ub[index] * prd);\n}\nfor (index = 0; index < 20; ++index)\n{\nprd = acadoWorkspace.y[index + 23];\nif (prd > 1e-12)\nkkt += fabs(acadoWorkspace.lbA[index] * prd);\nelse if (prd < -1e-12)\nkkt += fabs(acadoWorkspace.ubA[index] * prd);\n}\nreturn kkt;\n}\n\nreal_t acado_getObjective( TR )\n{\nreal_t objVal;\n\nint lRun1;\n/** Row vector of size: 4 */\nreal_t tmpDy[ 4 ];\n\n/** Row vector of size: 3 */\nreal_t tmpDyN[ 3 ];\n\nfor (lRun1 = 0; lRun1 < 20; ++lRun1)\n{\nacadoWorkspace.objValueIn[0] = acadoVariables.x[lRun1 * 3];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[lRun1 * 3 + 1];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[lRun1 * 3 + 2];\nacadoWorkspace.objValueIn[3] = acadoVariables.u[lRun1];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[lRun1 * 2 + 1];\n\nacado_evaluateLSQ( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut, TR );\nacadoWorkspace.Dy[lRun1 * 4] = acadoWorkspace.objValueOut[0] - acadoVariables.y[lRun1 * 4];\nacadoWorkspace.Dy[lRun1 * 4 + 1] = acadoWorkspace.objValueOut[1] - acadoVariables.y[lRun1 * 4 + 1];\nacadoWorkspace.Dy[lRun1 * 4 + 2] = acadoWorkspace.objValueOut[2] - acadoVariables.y[lRun1 * 4 + 2];\nacadoWorkspace.Dy[lRun1 * 4 + 3] = acadoWorkspace.objValueOut[3] - acadoVariables.y[lRun1 * 4 + 3];\n}\nacadoWorkspace.objValueIn[0] = acadoVariables.x[60];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[61];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[62];\nacadoWorkspace.objValueIn[3] = acadoVariables.od[40];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[41];\nacado_evaluateLSQEndTerm( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut, TR );\nacadoWorkspace.DyN[0] = acadoWorkspace.objValueOut[0] - acadoVariables.yN[0];\nacadoWorkspace.DyN[1] = acadoWorkspace.objValueOut[1] - acadoVariables.yN[1];\nacadoWorkspace.DyN[2] = acadoWorkspace.objValueOut[2] - acadoVariables.yN[2];\nobjVal = 0.0000000000000000e+00;\nfor (lRun1 = 0; lRun1 < 20; ++lRun1)\n{\ntmpDy[0] = + acadoWorkspace.Dy[lRun1 * 4]*acadoVariables.W[lRun1 * 16] + acadoWorkspace.Dy[lRun1 * 4 + 1]*acadoVariables.W[lRun1 * 16 + 4] + acadoWorkspace.Dy[lRun1 * 4 + 2]*acadoVariables.W[lRun1 * 16 + 8] + acadoWorkspace.Dy[lRun1 * 4 + 3]*acadoVariables.W[lRun1 * 16 + 12];\ntmpDy[1] = + acadoWorkspace.Dy[lRun1 * 4]*acadoVariables.W[lRun1 * 16 + 1] + acadoWorkspace.Dy[lRun1 * 4 + 1]*acadoVariables.W[lRun1 * 16 + 5] + acadoWorkspace.Dy[lRun1 * 4 + 2]*acadoVariables.W[lRun1 * 16 + 9] + acadoWorkspace.Dy[lRun1 * 4 + 3]*acadoVariables.W[lRun1 * 16 + 13];\ntmpDy[2] = + acadoWorkspace.Dy[lRun1 * 4]*acadoVariables.W[lRun1 * 16 + 2] + acadoWorkspace.Dy[lRun1 * 4 + 1]*acadoVariables.W[lRun1 * 16 + 6] + acadoWorkspace.Dy[lRun1 * 4 + 2]*acadoVariables.W[lRun1 * 16 + 10] + acadoWorkspace.Dy[lRun1 * 4 + 3]*acadoVariables.W[lRun1 * 16 + 14];\ntmpDy[3] = + acadoWorkspace.Dy[lRun1 * 4]*acadoVariables.W[lRun1 * 16 + 3] + acadoWorkspace.Dy[lRun1 * 4 + 1]*acadoVariables.W[lRun1 * 16 + 7] + acadoWorkspace.Dy[lRun1 * 4 + 2]*acadoVariables.W[lRun1 * 16 + 11] + acadoWorkspace.Dy[lRun1 * 4 + 3]*acadoVariables.W[lRun1 * 16 + 15];\nobjVal += + acadoWorkspace.Dy[lRun1 * 4]*tmpDy[0] + acadoWorkspace.Dy[lRun1 * 4 + 1]*tmpDy[1] + acadoWorkspace.Dy[lRun1 * 4 + 2]*tmpDy[2] + acadoWorkspace.Dy[lRun1 * 4 + 3]*tmpDy[3];\n}\n\ntmpDyN[0] = + acadoWorkspace.DyN[0]*acadoVariables.WN[0] + acadoWorkspace.DyN[1]*acadoVariables.WN[3] + acadoWorkspace.DyN[2]*acadoVariables.WN[6];\ntmpDyN[1] = + acadoWorkspace.DyN[0]*acadoVariables.WN[1] + acadoWorkspace.DyN[1]*acadoVariables.WN[4] + acadoWorkspace.DyN[2]*acadoVariables.WN[7];\ntmpDyN[2] = + acadoWorkspace.DyN[0]*acadoVariables.WN[2] + acadoWorkspace.DyN[1]*acadoVariables.WN[5] + acadoWorkspace.DyN[2]*acadoVariables.WN[8];\nobjVal += + acadoWorkspace.DyN[0]*tmpDyN[0] + acadoWorkspace.DyN[1]*tmpDyN[1] + acadoWorkspace.DyN[2]*tmpDyN[2];\n\nobjVal *= 0.5;\nreturn objVal;\n}\n\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/libmpc_py.py",
    "content": "import os\n\nfrom cffi import FFI\nfrom common.ffi_wrapper import suffix\n\nmpc_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)))\n\ndef _get_libmpc(mpc_id):\n    libmpc_fn = os.path.join(mpc_dir, \"libmpc%d%s\" % (mpc_id, suffix()))\n\n    ffi = FFI()\n    ffi.cdef(\"\"\"\n    typedef struct {\n    double x_ego, v_ego, a_ego, x_l, v_l, a_l;\n    } state_t;\n\n\n    typedef struct {\n    double x_ego[21];\n    double v_ego[21];\n    double a_ego[21];\n    double j_ego[20];\n    double x_l[21];\n    double v_l[21];\n    double a_l[21];\n    double t[21];\n    double cost;\n    } log_t;\n\n    void init(double ttcCost, double distanceCost, double accelerationCost, double jerkCost);\n    void init_with_simulation(double v_ego, double x_l, double v_l, double a_l, double l);\n    void change_tr(double ttcCost, double distanceCost, double accelerationCost, double jerkCost);\n    int run_mpc(state_t * x0, log_t * solution,\n                double l, double a_l_0, double TR);\n    \"\"\")\n\n    return (ffi, ffi.dlopen(libmpc_fn))\n\nmpcs = [_get_libmpc(0), _get_libmpc(1)]\n\ndef get_libmpc(mpc_id):\n    return mpcs[mpc_id]\n"
  },
  {
    "path": "selfdrive/controls/lib/lead_mpc_lib/longitudinal_mpc.c",
    "content": "#include \"acado_common.h\"\n#include \"acado_auxiliary_functions.h\"\n\n#include <stdio.h>\n#include <math.h>\n\n#define NX          ACADO_NX  /* Number of differential state variables.  */\n#define NXA         ACADO_NXA /* Number of algebraic variables. */\n#define NU          ACADO_NU  /* Number of control inputs. */\n#define NOD         ACADO_NOD  /* Number of online data values. */\n\n#define NY          ACADO_NY  /* Number of measurements/references on nodes 0..N - 1. */\n#define NYN         ACADO_NYN /* Number of measurements/references on node N. */\n\n#define N           ACADO_N   /* Number of intervals in the horizon. */\n\nACADOvariables acadoVariables;\nACADOworkspace acadoWorkspace;\n\ntypedef struct {\n  double x_ego, v_ego, a_ego, x_l, v_l, a_l;\n} state_t;\n\n\ntypedef struct {\n  double x_ego[N+1];\n  double v_ego[N+1];\n  double a_ego[N+1];\n  double j_ego[N];\n  double x_l[N+1];\n  double v_l[N+1];\n  double a_l[N+1];\n  double t[N+1];\n  double cost;\n} log_t;\n\nvoid init(double ttcCost, double distanceCost, double accelerationCost, double jerkCost){\n  acado_initializeSolver();\n  int    i;\n  const int STEP_MULTIPLIER = 3;\n\n  /* Initialize the states and controls. */\n  for (i = 0; i < NX * (N + 1); ++i)  acadoVariables.x[ i ] = 0.0;\n  for (i = 0; i < NU * N; ++i)  acadoVariables.u[ i ] = 0.0;\n\n  /* Initialize the measurements/reference. */\n  for (i = 0; i < NY * N; ++i)  acadoVariables.y[ i ] = 0.0;\n  for (i = 0; i < NYN; ++i)  acadoVariables.yN[ i ] = 0.0;\n\n  /* MPC: initialize the current state feedback. */\n  for (i = 0; i < NX; ++i) acadoVariables.x0[ i ] = 0.0;\n  // Set weights\n\n  for (i = 0; i < N; i++) {\n    int f = 1;\n    if (i > 4){\n      f = STEP_MULTIPLIER;\n    }\n    // Setup diagonal entries\n    acadoVariables.W[NY*NY*i + (NY+1)*0] = ttcCost * f; // exponential cost for time-to-collision (ttc)\n    acadoVariables.W[NY*NY*i + (NY+1)*1] = distanceCost * f; // desired distance\n    acadoVariables.W[NY*NY*i + (NY+1)*2] = accelerationCost * f; // acceleration\n    acadoVariables.W[NY*NY*i + (NY+1)*3] = jerkCost * f; // jerk\n  }\n  acadoVariables.WN[(NYN+1)*0] = ttcCost * STEP_MULTIPLIER; // exponential cost for danger zone\n  acadoVariables.WN[(NYN+1)*1] = distanceCost * STEP_MULTIPLIER; // desired distance\n  acadoVariables.WN[(NYN+1)*2] = accelerationCost * STEP_MULTIPLIER; // acceleration\n\n}\n\nvoid change_tr(double ttcCost, double distanceCost, double accelerationCost, double jerkCost){\n  int    i;\n  const int STEP_MULTIPLIER = 3;\n\n  for (i = 0; i < N; i++) {\n    int f = 1;\n    if (i > 4){\n      f = STEP_MULTIPLIER;\n    }\n    acadoVariables.W[16 * i + 0] = ttcCost * f; // exponential cost for time-to-collision (ttc)\n    acadoVariables.W[16 * i + 5] = distanceCost * f; // desired distance\n    acadoVariables.W[16 * i + 10] = accelerationCost * f; // acceleration\n    acadoVariables.W[16 * i + 15] = jerkCost * f; // jerk\n  }\n  acadoVariables.WN[0] = ttcCost * STEP_MULTIPLIER; // exponential cost for danger zone\n  acadoVariables.WN[4] = distanceCost * STEP_MULTIPLIER; // desired distance\n  acadoVariables.WN[8] = accelerationCost * STEP_MULTIPLIER; // acceleration\n}\n\nvoid init_with_simulation(double v_ego, double x_l_0, double v_l_0, double a_l_0, double l){\n  int i;\n\n  double x_l = x_l_0;\n  double v_l = v_l_0;\n  double a_l = a_l_0;\n\n  double x_ego = 0.0;\n  double a_ego = -(v_ego - v_l) * (v_ego - v_l) / (2.0 * x_l + 0.01) + a_l;\n\n  if (a_ego > 0){\n    a_ego = 0.0;\n  }\n\n\n  double dt = 0.2;\n  double t = 0.;\n\n  for (i = 0; i < N + 1; ++i){\n    if (i > 4){\n      dt = 0.6;\n    }\n\n    /* printf(\"%.2f\\t%.2f\\t%.2f\\t%.2f\\n\", t, x_ego, v_ego, a_l); */\n    acadoVariables.x[i*NX] = x_ego;\n    acadoVariables.x[i*NX+1] = v_ego;\n    acadoVariables.x[i*NX+2] = a_ego;\n\n    v_ego += a_ego * dt;\n\n    if (v_ego <= 0.0) {\n      v_ego = 0.0;\n      a_ego = 0.0;\n    }\n\n    x_ego += v_ego * dt;\n    t += dt;\n  }\n\n  for (i = 0; i < NU * N; ++i)  acadoVariables.u[ i ] = 0.0;\n  for (i = 0; i < NY * N; ++i)  acadoVariables.y[ i ] = 0.0;\n  for (i = 0; i < NYN; ++i)  acadoVariables.yN[ i ] = 0.0;\n}\n\nint run_mpc(state_t * x0, log_t * solution, double l, double a_l_0, double TR){\n  // Calculate lead vehicle predictions\n  int i;\n  double t = 0.;\n  double dt = 0.2;\n  double x_l = x0->x_l;\n  double v_l = x0->v_l;\n  double a_l = a_l_0;\n\n  /* printf(\"t\\tx_l\\t_v_l\\t_al\\n\"); */\n  for (i = 0; i < N + 1; ++i){\n    if (i > 4){\n      dt = 0.6;\n    }\n\n    /* printf(\"%.2f\\t%.2f\\t%.2f\\t%.2f\\n\", t, x_l, v_l, a_l); */\n\n    acadoVariables.od[i*NOD] = x_l;\n    acadoVariables.od[i*NOD+1] = v_l;\n\n    solution->x_l[i] = x_l;\n    solution->v_l[i] = v_l;\n    solution->a_l[i] = a_l;\n    solution->t[i] = t;\n\n    a_l = a_l_0 * exp(-l * t * t / 2);\n    x_l += v_l * dt;\n    v_l += a_l * dt;\n    if (v_l < 0.0){\n      a_l = 0.0;\n      v_l = 0.0;\n    }\n\n    t += dt;\n  }\n\n  acadoVariables.x[0] = acadoVariables.x0[0] = x0->x_ego;\n  acadoVariables.x[1] = acadoVariables.x0[1] = x0->v_ego;\n  acadoVariables.x[2] = acadoVariables.x0[2] = x0->a_ego;\n\n  acado_preparationStep(TR);\n  acado_feedbackStep();\n\n  for (i = 0; i <= N; i++){\n    solution->x_ego[i] = acadoVariables.x[i*NX];\n    solution->v_ego[i] = acadoVariables.x[i*NX+1];\n    solution->a_ego[i] = acadoVariables.x[i*NX+2];\n\n    if (i < N){\n      solution->j_ego[i] = acadoVariables.u[i];\n    }\n  }\n  solution->cost = acado_getObjective(TR);\n\n  // Dont shift states here. Current solution is closer to next timestep than if\n  // we shift by 0.2 seconds.\n\n  return acado_getNWSR();\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/limits_long_mpc.py",
    "content": "import numpy as np\nimport math\n\nfrom selfdrive.swaglog import cloudlog\nfrom common.realtime import sec_since_boot\nfrom selfdrive.controls.lib.longitudinal_mpc_lib import libmpc_py\nfrom selfdrive.controls.lib.drive_helpers import LON_MPC_N\nfrom selfdrive.modeld.constants import T_IDXS\n\n\nclass LimitsLongitudinalMpc():\n  def __init__(self):\n    self.reset_mpc()\n    self.last_cloudlog_t = 0.0\n    self.ts = list(range(10))\n    self.status = True\n    self.min_a = -1.2\n    self.max_a = 1.2\n\n  def reset_mpc(self):\n    self.libmpc = libmpc_py.libmpc\n    self.libmpc.init(0.0, 10.0, 0.0, 50.0, 10000.0)\n\n    self.mpc_solution = libmpc_py.ffi.new(\"log_t *\")\n    self.cur_state = libmpc_py.ffi.new(\"state_t *\")\n\n    self.cur_state[0].x_ego = 0\n    self.cur_state[0].v_ego = 0\n    self.cur_state[0].a_ego = 0\n\n    self.v_solution = [0.0 for i in range(len(T_IDXS))]\n    self.a_solution = [0.0 for i in range(len(T_IDXS))]\n    self.j_solution = [0.0 for i in range(len(T_IDXS) - 1)]\n\n  def set_accel_limits(self, min_a, max_a):\n    self.min_a = min_a\n    self.max_a = max_a\n\n  def set_cur_state(self, v, a):\n    v_safe = max(v, 1e-2)\n    a_safe = min(a, self.max_a - 1e-2)\n    a_safe = max(a_safe, self.min_a + 1e-2)\n    self.cur_state[0].x_ego = 0.0\n    self.cur_state[0].v_ego = v_safe\n    self.cur_state[0].a_ego = a_safe\n\n  def update(self, carstate, model, v_cruise, a_target, active):\n    t = np.array(T_IDXS[:LON_MPC_N + 1])\n    v_ego = self.cur_state[0].v_ego\n\n    # If active, provide targets for a constant acceleration following a_target\n    # otherwise just target cruising at current speed\n    if active:\n      poss = v_ego * t + a_target * t**2 / 2.\n      speeds = v_ego + a_target * t\n      accels = a_target + np.ones(LON_MPC_N + 1)\n    else:\n      poss = v_ego * t\n      speeds = v_ego * np.ones(LON_MPC_N + 1)\n      accels = np.zeros(LON_MPC_N + 1)\n\n    # Calculate mpc\n    self.libmpc.run_mpc(self.cur_state, self.mpc_solution,\n                        list(poss), list(speeds), list(accels),\n                        self.min_a, self.max_a)\n\n    self.v_solution = list(self.mpc_solution.v_ego)\n    self.a_solution = list(self.mpc_solution.a_ego)\n    self.j_solution = list(self.mpc_solution.j_ego)\n\n    # Reset if NaN or goes through lead car\n    nans = any(math.isnan(x) for x in self.mpc_solution[0].v_ego)\n\n    t = sec_since_boot()\n    if nans:\n      if t > self.last_cloudlog_t + 5.0:\n        self.last_cloudlog_t = t\n        cloudlog.warning(\"Longitudinal model mpc reset - nans\")\n      self.reset_mpc()\n"
  },
  {
    "path": "selfdrive/controls/lib/long_mpc.py",
    "content": "import numpy as np\nimport math\n\nfrom selfdrive.swaglog import cloudlog\nfrom common.realtime import sec_since_boot\nfrom selfdrive.controls.lib.longitudinal_mpc_lib import libmpc_py\nfrom selfdrive.controls.lib.drive_helpers import LON_MPC_N\nfrom selfdrive.modeld.constants import T_IDXS\n\n\nclass LongitudinalMpc():\n  def __init__(self):\n    self.reset_mpc()\n    self.last_cloudlog_t = 0.0\n    self.ts = list(range(10))\n    self.status = True\n    self.min_a = -1.2\n    self.max_a = 1.2\n\n\n  def reset_mpc(self):\n    self.libmpc = libmpc_py.libmpc\n    self.libmpc.init(0.0, 1.0, 0.0, 50.0, 10000.0)\n\n    self.mpc_solution = libmpc_py.ffi.new(\"log_t *\")\n    self.cur_state = libmpc_py.ffi.new(\"state_t *\")\n\n    self.cur_state[0].x_ego = 0\n    self.cur_state[0].v_ego = 0\n    self.cur_state[0].a_ego = 0\n\n    self.v_solution = [0.0 for i in range(len(T_IDXS))]\n    self.a_solution = [0.0 for i in range(len(T_IDXS))]\n    self.j_solution = [0.0 for i in range(len(T_IDXS)-1)]\n\n  def set_accel_limits(self, min_a, max_a):\n    self.min_a = min_a\n    self.max_a = max_a\n\n  def set_cur_state(self, v, a):\n    v_safe = max(v, 1e-2)\n    a_safe = min(a, self.max_a - 1e-2)\n    a_safe = max(a_safe, self.min_a + 1e-2)\n    self.cur_state[0].x_ego = 0.0\n    self.cur_state[0].v_ego = v_safe\n    self.cur_state[0].a_ego = a_safe\n\n  def update(self, carstate, radarstate, v_cruise, a_target, active):\n    v_cruise_clipped = np.clip(v_cruise, self.cur_state[0].v_ego - 10., self.cur_state[0].v_ego + 10.0)\n    poss = v_cruise_clipped * np.array(T_IDXS[:LON_MPC_N+1])\n    speeds = v_cruise_clipped * np.ones(LON_MPC_N+1)\n    accels = np.zeros(LON_MPC_N+1)\n    self.update_with_xva(poss, speeds, accels)\n\n  def update_with_xva(self, poss, speeds, accels):\n    # Calculate mpc\n    self.libmpc.run_mpc(self.cur_state, self.mpc_solution,\n                        list(poss), list(speeds), list(accels),\n                        self.min_a, self.max_a)\n\n    self.v_solution = list(self.mpc_solution.v_ego)\n    self.a_solution = list(self.mpc_solution.a_ego)\n    self.j_solution = list(self.mpc_solution.j_ego)\n\n    # Reset if NaN or goes through lead car\n    nans = any(math.isnan(x) for x in self.mpc_solution[0].v_ego)\n\n    t = sec_since_boot()\n    if nans:\n      if t > self.last_cloudlog_t + 5.0:\n        self.last_cloudlog_t = t\n        cloudlog.warning(\"Longitudinal model mpc reset - nans\")\n      self.reset_mpc()\n"
  },
  {
    "path": "selfdrive/controls/lib/longcontrol.py",
    "content": "from cereal import car\nfrom common.numpy_fast import clip, interp\nfrom selfdrive.controls.lib.pid import PIController\nfrom selfdrive.controls.lib.drive_helpers import CONTROL_N\nfrom selfdrive.modeld.constants import T_IDXS\n\nLongCtrlState = car.CarControl.Actuators.LongControlState\n\nSTOPPING_EGO_SPEED = 0.5\nSTOPPING_TARGET_SPEED_OFFSET = 0.01\nSTARTING_TARGET_SPEED = 0.5\nDECEL_THRESHOLD_TO_PID = 0.8\n\nDECEL_STOPPING_TARGET = 2.0  # apply at least this amount of brake to maintain the vehicle stationary\n\nRATE = 100.0\n\n# As per ISO 15622:2018 for all speeds\nACCEL_MIN_ISO = -3.5 # m/s^2\nACCEL_MAX_ISO = 2.0 # m/s^2\n\n\n# TODO this logic isn't really car independent, does not belong here\ndef long_control_state_trans(active, long_control_state, v_ego, v_target, v_pid,\n                             output_accel, brake_pressed, cruise_standstill, min_speed_can):\n  \"\"\"Update longitudinal control state machine\"\"\"\n  stopping_target_speed = min_speed_can + STOPPING_TARGET_SPEED_OFFSET\n  stopping_condition = (v_ego < 2.0 and cruise_standstill) or \\\n                       (v_ego < STOPPING_EGO_SPEED and\n                        ((v_pid < stopping_target_speed and v_target < stopping_target_speed) or\n                         brake_pressed))\n\n  starting_condition = v_target > STARTING_TARGET_SPEED and not cruise_standstill\n\n  if not active:\n    long_control_state = LongCtrlState.off\n\n  else:\n    if long_control_state == LongCtrlState.off:\n      if active:\n        long_control_state = LongCtrlState.pid\n\n    elif long_control_state == LongCtrlState.pid:\n      if stopping_condition:\n        long_control_state = LongCtrlState.stopping\n\n    elif long_control_state == LongCtrlState.stopping:\n      if starting_condition:\n        long_control_state = LongCtrlState.starting\n\n    elif long_control_state == LongCtrlState.starting:\n      if stopping_condition:\n        long_control_state = LongCtrlState.stopping\n      elif output_accel >= -DECEL_THRESHOLD_TO_PID:\n        long_control_state = LongCtrlState.pid\n\n  return long_control_state\n\n\nclass LongControl():\n  def __init__(self, CP):\n    self.long_control_state = LongCtrlState.off  # initialized to off\n    self.pid = PIController((CP.longitudinalTuning.kpBP, CP.longitudinalTuning.kpV),\n                            (CP.longitudinalTuning.kiBP, CP.longitudinalTuning.kiV),\n                            rate=RATE,\n                            sat_limit=0.8)\n    self.v_pid = 0.0\n    self.last_output_accel = 0.0\n\n  def reset(self, v_pid):\n    \"\"\"Reset PID controller and change setpoint\"\"\"\n    self.pid.reset()\n    self.v_pid = v_pid\n\n  def update(self, active, CS, CP, long_plan, accel_limits):\n    \"\"\"Update longitudinal control. This updates the state machine and runs a PID loop\"\"\"\n    # Interp control trajectory\n    # TODO estimate car specific lag, use .15s for now\n    if len(long_plan.speeds) == CONTROL_N:\n      v_target = interp(CP.longitudinalActuatorDelay, T_IDXS[:CONTROL_N], long_plan.speeds)\n      v_target_future = long_plan.speeds[-1]\n      a_target = 2 * (v_target - long_plan.speeds[0])/CP.longitudinalActuatorDelay - long_plan.accels[0]\n    else:\n      v_target = 0.0\n      v_target_future = 0.0\n      a_target = 0.0\n\n    # TODO: This check is not complete and needs to be enforced by MPC\n    a_target = clip(a_target, ACCEL_MIN_ISO, ACCEL_MAX_ISO)\n\n    self.pid.neg_limit = accel_limits[0]\n    self.pid.pos_limit = accel_limits[1]\n\n    # Update state machine\n    output_accel = self.last_output_accel\n    self.long_control_state = long_control_state_trans(active, self.long_control_state, CS.vEgo,\n                                                       v_target_future, self.v_pid, output_accel,\n                                                       CS.brakePressed, CS.cruiseState.standstill, CP.minSpeedCan)\n\n    v_ego_pid = max(CS.vEgo, CP.minSpeedCan)  # Without this we get jumps, CAN bus reports 0 when speed < 0.3\n\n    if self.long_control_state == LongCtrlState.off or CS.gasPressed:\n      self.reset(v_ego_pid)\n      output_accel = 0.\n\n    # tracking objects and driving\n    elif self.long_control_state == LongCtrlState.pid:\n      self.v_pid = v_target\n\n      # Toyota starts braking more when it thinks you want to stop\n      # Freeze the integrator so we don't accelerate to compensate, and don't allow positive acceleration\n      prevent_overshoot = not CP.stoppingControl and CS.vEgo < 1.5 and v_target_future < 0.7\n      deadzone = interp(v_ego_pid, CP.longitudinalTuning.deadzoneBP, CP.longitudinalTuning.deadzoneV)\n      freeze_integrator = prevent_overshoot\n\n      output_accel = self.pid.update(self.v_pid, v_ego_pid, speed=v_ego_pid, deadzone=deadzone, feedforward=a_target, freeze_integrator=freeze_integrator)\n\n      if prevent_overshoot:\n        output_accel = min(output_accel, 0.0)\n\n    # Intention is to stop, switch to a different brake control until we stop\n    elif self.long_control_state == LongCtrlState.stopping:\n      # Keep applying brakes until the car is stopped\n      if not CS.standstill or output_accel > -DECEL_STOPPING_TARGET:\n        output_accel -= CP.stoppingDecelRate / RATE\n      output_accel = clip(output_accel, accel_limits[0], accel_limits[1])\n\n      self.reset(CS.vEgo)\n\n    # Intention is to move again, release brake fast before handing control to PID\n    elif self.long_control_state == LongCtrlState.starting:\n      if output_accel < -DECEL_THRESHOLD_TO_PID:\n        output_accel += CP.startingAccelRate / RATE\n      self.reset(CS.vEgo)\n\n    self.last_output_accel = output_accel\n    final_accel = clip(output_accel, accel_limits[0], accel_limits[1])\n\n    return final_accel, v_target, a_target\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/.gitignore",
    "content": "generator\nlib_qp/\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/SConscript",
    "content": "Import('env', 'arch')\n\ncpp_path = [\n    \"#\",\n    \"#selfdrive\",\n    \"#phonelibs/acado/include\",\n    \"#phonelibs/acado/include/acado\",\n    \"#phonelibs/qpoases/INCLUDE\",\n    \"#phonelibs/qpoases/INCLUDE/EXTRAS\",\n    \"#phonelibs/qpoases/SRC/\",\n    \"#phonelibs/qpoases\",\n    \"lib_mpc_export\",\n]\n\ngenerated_c = [\n    'lib_mpc_export/acado_auxiliary_functions.c',\n    'lib_mpc_export/acado_qpoases_interface.cpp',\n    'lib_mpc_export/acado_integrator.c',\n    'lib_mpc_export/acado_solver.c',\n]\n\ngenerated_h = [\n    'lib_mpc_export/acado_common.h',\n    'lib_mpc_export/acado_auxiliary_functions.h',\n    'lib_mpc_export/acado_qpoases_interface.hpp',\n]\n\ninterface_dir = Dir('lib_mpc_export')\n\nSConscript(['#phonelibs/qpoases/SConscript'], variant_dir='lib_qp', exports=['interface_dir'])\n\nif GetOption('mpc_generate'):\n  generator_cpp = File('generator.cpp')\n\n  acado_libs = [File(f\"#phonelibs/acado/{arch}/lib/libacado_toolkit.a\"),\n                File(f\"#phonelibs/acado/{arch}/lib/libacado_casadi.a\"),\n                File(f\"#phonelibs/acado/{arch}/lib/libacado_csparse.a\")]\n\n  generator = env.Program('generator', generator_cpp, LIBS=acado_libs, CPPPATH=cpp_path,\n                          CCFLAGS=env['CCFLAGS'] + [\"-Wno-deprecated\", \"-Wno-overloaded-shift-op-parentheses\"])\n\n  cmd = f\"cd {Dir('.').get_abspath()} && {generator[0].get_abspath()}\"\n  env.Command(generated_c + generated_h, generator, cmd)\n\n\nmpc_files = [\"longitudinal_mpc.c\"] + generated_c\nenv.SharedLibrary('mpc', mpc_files, LIBS=['m', 'qpoases'], LIBPATH=['lib_qp'], CPPPATH=cpp_path)\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/generator.cpp",
    "content": "#include <acado_code_generation.hpp>\n#include \"selfdrive/common/modeldata.h\"\n\nusing namespace std;\n\n\nint main( )\n{\n  USING_NAMESPACE_ACADO\n\n\n  DifferentialEquation f;\n\n  DifferentialState x_ego, v_ego, a_ego;\n  DifferentialState dummy_0;\n  OnlineData min_a, max_a;\n\n  Control j_ego, accel_slack;\n\n  // Equations of motion\n  f << dot(x_ego) == v_ego;\n  f << dot(v_ego) == a_ego;\n  f << dot(a_ego) == j_ego;\n  f << dot(dummy_0) == accel_slack;\n\n  // Running cost\n  Function h;\n  h << x_ego;\n  h << v_ego;\n  h << a_ego;\n  h << j_ego;\n  h << accel_slack;\n\n  // Weights are defined in mpc.\n  BMatrix Q(5,5); Q.setAll(true);\n\n  // Terminal cost\n  Function hN;\n  hN << x_ego;\n  hN << v_ego;\n  hN << a_ego;\n\n  // Weights are defined in mpc.\n  BMatrix QN(3,3); QN.setAll(true);\n\n  double T_IDXS_ARR[LON_MPC_N + 1];\n  memcpy(T_IDXS_ARR, T_IDXS, (LON_MPC_N + 1) * sizeof(double));\n  Grid times(LON_MPC_N + 1, T_IDXS_ARR);\n  OCP ocp(times);\n  ocp.subjectTo(f);\n\n  ocp.minimizeLSQ(Q, h);\n  ocp.minimizeLSQEndTerm(QN, hN);\n\n  ocp.subjectTo( 0.0 <= v_ego);\n  ocp.subjectTo( 0.0 <= a_ego - min_a + accel_slack);\n  ocp.subjectTo( a_ego - max_a + accel_slack <= 0.0);\n  ocp.setNOD(2);\n\n  OCPexport mpc(ocp);\n  mpc.set( HESSIAN_APPROXIMATION, GAUSS_NEWTON );\n  mpc.set( DISCRETIZATION_TYPE, MULTIPLE_SHOOTING );\n  mpc.set( INTEGRATOR_TYPE, INT_RK4 );\n  mpc.set( NUM_INTEGRATOR_STEPS, 1000);\n  mpc.set( MAX_NUM_QP_ITERATIONS, 50);\n  mpc.set( CG_USE_VARIABLE_WEIGHTING_MATRIX, YES);\n\n  mpc.set( SPARSE_QP_SOLUTION, CONDENSING );\n  mpc.set( QP_SOLVER, QP_QPOASES );\n  mpc.set( HOTSTART_QP, YES );\n  mpc.set( GENERATE_TEST_FILE, NO);\n  mpc.set( GENERATE_MAKE_FILE, NO );\n  mpc.set( GENERATE_MATLAB_INTERFACE, NO );\n  mpc.set( GENERATE_SIMULINK_INTERFACE, NO );\n\n  if (mpc.exportCode( \"lib_mpc_export\" ) != SUCCESSFUL_RETURN)\n    exit( EXIT_FAILURE );\n\n  mpc.printDimensionsQP( );\n\n  return EXIT_SUCCESS;\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_auxiliary_functions.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_auxiliary_functions.h\"\n\n#include <stdio.h>\n\nreal_t* acado_getVariablesX( )\n{\n\treturn acadoVariables.x;\n}\n\nreal_t* acado_getVariablesU( )\n{\n\treturn acadoVariables.u;\n}\n\n#if ACADO_NY > 0\nreal_t* acado_getVariablesY( )\n{\n\treturn acadoVariables.y;\n}\n#endif\n\n#if ACADO_NYN > 0\nreal_t* acado_getVariablesYN( )\n{\n\treturn acadoVariables.yN;\n}\n#endif\n\nreal_t* acado_getVariablesX0( )\n{\n#if ACADO_INITIAL_VALUE_FIXED\n\treturn acadoVariables.x0;\n#else\n\treturn 0;\n#endif\n}\n\n/** Print differential variables. */\nvoid acado_printDifferentialVariables( )\n{\n\tint i, j;\n\tprintf(\"\\nDifferential variables:\\n[\\n\");\n\tfor (i = 0; i < ACADO_N + 1; ++i)\n\t{\n\t\tfor (j = 0; j < ACADO_NX; ++j)\n\t\t\tprintf(\"\\t%e\", acadoVariables.x[i * ACADO_NX + j]);\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"]\\n\\n\");\n}\n\n/** Print control variables. */\nvoid acado_printControlVariables( )\n{\n\tint i, j;\n\tprintf(\"\\nControl variables:\\n[\\n\");\n\tfor (i = 0; i < ACADO_N; ++i)\n\t{\n\t\tfor (j = 0; j < ACADO_NU; ++j)\n\t\t\tprintf(\"\\t%e\", acadoVariables.u[i * ACADO_NU + j]);\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"]\\n\\n\");\n}\n\n/** Print ACADO code generation notice. */\nvoid acado_printHeader( )\n{\n\tprintf(\n\t\t\"\\nACADO Toolkit -- A Toolkit for Automatic Control and Dynamic Optimization.\\n\"\n\t\t\"Copyright (C) 2008-2015 by Boris Houska, Hans Joachim Ferreau,\\n\" \n\t\t\"Milan Vukov and Rien Quirynen, KU Leuven.\\n\"\n\t);\n\t\n\tprintf(\n\t\t\"Developed within the Optimization in Engineering Center (OPTEC) under\\n\"\n\t\t\"supervision of Moritz Diehl. All rights reserved.\\n\\n\"\n\t\t\"ACADO Toolkit is distributed under the terms of the GNU Lesser\\n\"\n\t\t\"General Public License 3 in the hope that it will be useful,\\n\"\n\t\t\"but WITHOUT ANY WARRANTY; without even the implied warranty of\\n\"\n\t\t\"MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\\n\"\n\t\t\"GNU Lesser General Public License for more details.\\n\\n\"\n\t);\n}\n\n#if !(defined _DSPACE)\n#if (defined _WIN32 || defined _WIN64) && !(defined __MINGW32__ || defined __MINGW64__)\n\nvoid acado_tic( acado_timer* t )\n{\n\tQueryPerformanceFrequency(&t->freq);\n\tQueryPerformanceCounter(&t->tic);\n}\n\nreal_t acado_toc( acado_timer* t )\n{\n\tQueryPerformanceCounter(&t->toc);\n\treturn ((t->toc.QuadPart - t->tic.QuadPart) / (real_t)t->freq.QuadPart);\n}\n\n\n#elif (defined __APPLE__)\n\nvoid acado_tic( acado_timer* t )\n{\n    /* read current clock cycles */\n    t->tic = mach_absolute_time();\n}\n\nreal_t acado_toc( acado_timer* t )\n{\n\n    uint64_t duration; /* elapsed time in clock cycles*/\n    \n    t->toc = mach_absolute_time();\n    duration = t->toc - t->tic;\n    \n    /*conversion from clock cycles to nanoseconds*/\n    mach_timebase_info(&(t->tinfo));\n    duration *= t->tinfo.numer;\n    duration /= t->tinfo.denom;\n\n    return (real_t)duration / 1e9;\n}\n\n#else\n\n#if __STDC_VERSION__ >= 199901L\n/* C99 mode */\n\n/* read current time */\nvoid acado_tic( acado_timer* t )\n{\n\tgettimeofday(&t->tic, 0);\n}\n\n/* return time passed since last call to tic on this timer */\nreal_t acado_toc( acado_timer* t )\n{\n\tstruct timeval temp;\n\t\n\tgettimeofday(&t->toc, 0);\n    \n\tif ((t->toc.tv_usec - t->tic.tv_usec) < 0)\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec - 1;\n\t\ttemp.tv_usec = 1000000 + t->toc.tv_usec - t->tic.tv_usec;\n\t}\n\telse\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec;\n\t\ttemp.tv_usec = t->toc.tv_usec - t->tic.tv_usec;\n\t}\n\t\n\treturn (real_t)temp.tv_sec + (real_t)temp.tv_usec / 1e6;\n}\n\n#else\n/* ANSI */\n\n/* read current time */\nvoid acado_tic( acado_timer* t )\n{\n\tclock_gettime(CLOCK_MONOTONIC, &t->tic);\n}\n\n\n/* return time passed since last call to tic on this timer */\nreal_t acado_toc( acado_timer* t )\n{\n\tstruct timespec temp;\n    \n\tclock_gettime(CLOCK_MONOTONIC, &t->toc);\t\n    \n\tif ((t->toc.tv_nsec - t->tic.tv_nsec) < 0)\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec - 1;\n\t\ttemp.tv_nsec = 1000000000+t->toc.tv_nsec - t->tic.tv_nsec;\n\t}\n\telse\n\t{\n\t\ttemp.tv_sec = t->toc.tv_sec - t->tic.tv_sec;\n\t\ttemp.tv_nsec = t->toc.tv_nsec - t->tic.tv_nsec;\n\t}\n\t\n\treturn (real_t)temp.tv_sec + (real_t)temp.tv_nsec / 1e9;\n}\n\n#endif /* __STDC_VERSION__ >= 199901L */\n\n#endif /* (defined _WIN32 || _WIN64) */\n\n#endif\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_auxiliary_functions.h",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef ACADO_AUXILIARY_FUNCTIONS_H\n#define ACADO_AUXILIARY_FUNCTIONS_H\n\n#include \"acado_common.h\"\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n/** Get pointer to the matrix with differential variables. */\nreal_t* acado_getVariablesX( );\n\n/** Get pointer to the matrix with control variables. */\nreal_t* acado_getVariablesU( );\n\n#if ACADO_NY > 0\n/** Get pointer to the matrix with references/measurements. */\nreal_t* acado_getVariablesY( );\n#endif\n\n#if ACADO_NYN > 0\n/** Get pointer to the vector with references/measurement on the last node. */\nreal_t* acado_getVariablesYN( );\n#endif\n\n/** Get pointer to the current state feedback vector. Only applicable for NMPC. */\nreal_t* acado_getVariablesX0( );\n\n/** Print differential variables. */\nvoid acado_printDifferentialVariables( );\n\n/** Print control variables. */\nvoid acado_printControlVariables( );\n\n/** Print ACADO code generation notice. */\nvoid acado_printHeader( );\n\n/*\n * A huge thanks goes to Alexander Domahidi from ETHZ, Switzerland, for \n * providing us with the following timing routines.\n */\n\n#if !(defined _DSPACE)\n#if (defined _WIN32 || defined _WIN64) && !(defined __MINGW32__ || defined __MINGW64__)\n\n/* Use Windows QueryPerformanceCounter for timing. */\n#include <Windows.h>\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tLARGE_INTEGER tic;\n\tLARGE_INTEGER toc;\n\tLARGE_INTEGER freq;\n} acado_timer;\n\n\n#elif (defined __APPLE__)\n\n#include \"unistd.h\"\n#include <mach/mach_time.h>\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tuint64_t tic;\n\tuint64_t toc;\n\tmach_timebase_info_data_t tinfo;\n} acado_timer;\n\n#else\n\n/* Use POSIX clock_gettime() for timing on non-Windows machines. */\n#include <time.h>\n\n#if __STDC_VERSION__ >= 199901L\n/* C99 mode of operation. */\n\n#include <sys/stat.h>\n#include <sys/time.h>\n\ntypedef struct acado_timer_\n{\n\tstruct timeval tic;\n\tstruct timeval toc;\n} acado_timer;\n\n#else\n/* ANSI C */\n\n/** A structure for keeping internal timer data. */\ntypedef struct acado_timer_\n{\n\tstruct timespec tic;\n\tstruct timespec toc;\n} acado_timer;\n\n#endif /* __STDC_VERSION__ >= 199901L */\n\n#endif /* (defined _WIN32 || defined _WIN64) */\n\n/** A function for measurement of the current time. */\nvoid acado_tic( acado_timer* t );\n\n/** A function which returns the elapsed time. */\nreal_t acado_toc( acado_timer* t );\n\n#endif\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\n} /* extern \"C\" */\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n#endif /* ACADO_AUXILIARY_FUNCTIONS_H */\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_common.h",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef ACADO_COMMON_H\n#define ACADO_COMMON_H\n\n#include <math.h>\n#include <string.h>\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n/** \\defgroup ACADO ACADO CGT generated module. */\n/** @{ */\n\n/** qpOASES QP solver indicator. */\n#define ACADO_QPOASES  0\n#define ACADO_QPOASES3 1\n/** FORCES QP solver indicator.*/\n#define ACADO_FORCES   2\n/** qpDUNES QP solver indicator.*/\n#define ACADO_QPDUNES  3\n/** HPMPC QP solver indicator. */\n#define ACADO_HPMPC    4\n#define ACADO_GENERIC    5\n\n/** Indicator for determining the QP solver used by the ACADO solver code. */\n#define ACADO_QP_SOLVER ACADO_QPOASES\n\n#include \"acado_qpoases_interface.hpp\"\n\n\n/*\n * Common definitions\n */\n/** User defined block based condensing. */\n#define ACADO_BLOCK_CONDENSING 0\n/** Compute covariance matrix of the last state estimate. */\n#define ACADO_COMPUTE_COVARIANCE_MATRIX 0\n/** Flag indicating whether constraint values are hard-coded or not. */\n#define ACADO_HARDCODED_CONSTRAINT_VALUES 1\n/** Indicator for fixed initial state. */\n#define ACADO_INITIAL_STATE_FIXED 1\n/** Number of control/estimation intervals. */\n#define ACADO_N 32\n/** Number of online data values. */\n#define ACADO_NOD 2\n/** Number of path constraints. */\n#define ACADO_NPAC 2\n/** Number of control variables. */\n#define ACADO_NU 2\n/** Number of differential variables. */\n#define ACADO_NX 4\n/** Number of algebraic variables. */\n#define ACADO_NXA 0\n/** Number of differential derivative variables. */\n#define ACADO_NXD 0\n/** Number of references/measurements per node on the first N nodes. */\n#define ACADO_NY 5\n/** Number of references/measurements on the last (N + 1)st node. */\n#define ACADO_NYN 3\n/** Total number of QP optimization variables. */\n#define ACADO_QP_NV 68\n/** Number of Runge-Kutta stages per integration step. */\n#define ACADO_RK_NSTAGES 4\n/** Providing interface for arrival cost. */\n#define ACADO_USE_ARRIVAL_COST 0\n/** Indicator for usage of non-hard-coded linear terms in the objective. */\n#define ACADO_USE_LINEAR_TERMS 0\n/** Indicator for type of fixed weighting matrices. */\n#define ACADO_WEIGHTING_MATRICES_TYPE 2\n\n\n/*\n * Globally used structure definitions\n */\n\n/** The structure containing the user data.\n * \n *  Via this structure the user \"communicates\" with the solver code.\n */\ntypedef struct ACADOvariables_\n{\nint dummy;\n/** Matrix of size: 33 x 4 (row major format)\n * \n *  Matrix containing 33 differential variable vectors.\n */\nreal_t x[ 132 ];\n\n/** Matrix of size: 32 x 2 (row major format)\n * \n *  Matrix containing 32 control variable vectors.\n */\nreal_t u[ 64 ];\n\n/** Matrix of size: 33 x 2 (row major format)\n * \n *  Matrix containing 33 online data vectors.\n */\nreal_t od[ 66 ];\n\n/** Column vector of size: 160\n * \n *  Matrix containing 32 reference/measurement vectors of size 5 for first 32 nodes.\n */\nreal_t y[ 160 ];\n\n/** Column vector of size: 3\n * \n *  Reference/measurement vector for the 33. node.\n */\nreal_t yN[ 3 ];\n\n/** Matrix of size: 160 x 5 (row major format) */\nreal_t W[ 800 ];\n\n/** Matrix of size: 3 x 3 (row major format) */\nreal_t WN[ 9 ];\n\n/** Column vector of size: 4\n * \n *  Current state feedback vector.\n */\nreal_t x0[ 4 ];\n\n\n} ACADOvariables;\n\n/** Private workspace used by the auto-generated code.\n * \n *  Data members of this structure are private to the solver.\n *  In other words, the user code should not modify values of this \n *  structure. \n */\ntypedef struct ACADOworkspace_\n{\nreal_t rk_ttt;\n\n/** Row vector of size: 32 */\nreal_t rk_xxx[ 32 ];\n\n/** Matrix of size: 4 x 28 (row major format) */\nreal_t rk_kkk[ 112 ];\n\n/** Row vector of size: 32 */\nreal_t state[ 32 ];\n\n/** Column vector of size: 128 */\nreal_t d[ 128 ];\n\n/** Column vector of size: 160 */\nreal_t Dy[ 160 ];\n\n/** Column vector of size: 3 */\nreal_t DyN[ 3 ];\n\n/** Matrix of size: 128 x 4 (row major format) */\nreal_t evGx[ 512 ];\n\n/** Matrix of size: 128 x 2 (row major format) */\nreal_t evGu[ 256 ];\n\n/** Row vector of size: 8 */\nreal_t objValueIn[ 8 ];\n\n/** Row vector of size: 5 */\nreal_t objValueOut[ 5 ];\n\n/** Matrix of size: 128 x 4 (row major format) */\nreal_t Q1[ 512 ];\n\n/** Matrix of size: 128 x 5 (row major format) */\nreal_t Q2[ 640 ];\n\n/** Matrix of size: 64 x 2 (row major format) */\nreal_t R1[ 128 ];\n\n/** Matrix of size: 64 x 5 (row major format) */\nreal_t R2[ 320 ];\n\n/** Matrix of size: 128 x 2 (row major format) */\nreal_t S1[ 256 ];\n\n/** Matrix of size: 4 x 4 (row major format) */\nreal_t QN1[ 16 ];\n\n/** Matrix of size: 4 x 3 (row major format) */\nreal_t QN2[ 12 ];\n\n/** Column vector of size: 12 */\nreal_t conAuxVar[ 12 ];\n\n/** Row vector of size: 8 */\nreal_t conValueIn[ 8 ];\n\n/** Row vector of size: 14 */\nreal_t conValueOut[ 14 ];\n\n/** Column vector of size: 64 */\nreal_t evH[ 64 ];\n\n/** Matrix of size: 64 x 4 (row major format) */\nreal_t evHx[ 256 ];\n\n/** Matrix of size: 64 x 2 (row major format) */\nreal_t evHu[ 128 ];\n\n/** Column vector of size: 2 */\nreal_t evHxd[ 2 ];\n\n/** Column vector of size: 4 */\nreal_t Dx0[ 4 ];\n\n/** Matrix of size: 4 x 4 (row major format) */\nreal_t T[ 16 ];\n\n/** Matrix of size: 2112 x 2 (row major format) */\nreal_t E[ 4224 ];\n\n/** Matrix of size: 2112 x 2 (row major format) */\nreal_t QE[ 4224 ];\n\n/** Matrix of size: 128 x 4 (row major format) */\nreal_t QGx[ 512 ];\n\n/** Column vector of size: 128 */\nreal_t Qd[ 128 ];\n\n/** Column vector of size: 132 */\nreal_t QDy[ 132 ];\n\n/** Matrix of size: 64 x 4 (row major format) */\nreal_t H10[ 256 ];\n\n/** Matrix of size: 68 x 68 (row major format) */\nreal_t H[ 4624 ];\n\n/** Matrix of size: 96 x 68 (row major format) */\nreal_t A[ 6528 ];\n\n/** Column vector of size: 68 */\nreal_t g[ 68 ];\n\n/** Column vector of size: 68 */\nreal_t lb[ 68 ];\n\n/** Column vector of size: 68 */\nreal_t ub[ 68 ];\n\n/** Column vector of size: 96 */\nreal_t lbA[ 96 ];\n\n/** Column vector of size: 96 */\nreal_t ubA[ 96 ];\n\n/** Column vector of size: 68 */\nreal_t x[ 68 ];\n\n/** Column vector of size: 164 */\nreal_t y[ 164 ];\n\n\n} ACADOworkspace;\n\n/* \n * Forward function declarations. \n */\n\n\n/** Performs the integration and sensitivity propagation for one shooting interval.\n *\n *  \\param rk_eta Working array to pass the input values and return the results.\n *  \\param resetIntegrator The internal memory of the integrator can be reset.\n *  \\param rk_index Number of the shooting interval.\n *\n *  \\return Status code of the integrator.\n */\nint acado_integrate( real_t* const rk_eta, int resetIntegrator, int rk_index );\n\n/** Export of an ACADO symbolic function.\n *\n *  \\param in Input to the exported function.\n *  \\param out Output of the exported function.\n */\nvoid acado_rhs_forw(const real_t* in, real_t* out);\n\n/** Preparation step of the RTI scheme.\n *\n *  \\return Status of the integration module. =0: OK, otherwise the error code.\n */\nint acado_preparationStep(  );\n\n/** Feedback/estimation step of the RTI scheme.\n *\n *  \\return Status code of the qpOASES QP solver.\n */\nint acado_feedbackStep(  );\n\n/** Solver initialization. Must be called once before any other function call.\n *\n *  \\return =0: OK, otherwise an error code of a QP solver.\n */\nint acado_initializeSolver(  );\n\n/** Initialize shooting nodes by a forward simulation starting from the first node.\n */\nvoid acado_initializeNodesByForwardSimulation(  );\n\n/** Shift differential variables vector by one interval.\n *\n *  \\param strategy Shifting strategy: 1. Initialize node 33 with xEnd. 2. Initialize node 33 by forward simulation.\n *  \\param xEnd Value for the x vector on the last node. If =0 the old value is used.\n *  \\param uEnd Value for the u vector on the second to last node. If =0 the old value is used.\n */\nvoid acado_shiftStates( int strategy, real_t* const xEnd, real_t* const uEnd );\n\n/** Shift controls vector by one interval.\n *\n *  \\param uEnd Value for the u vector on the second to last node. If =0 the old value is used.\n */\nvoid acado_shiftControls( real_t* const uEnd );\n\n/** Get the KKT tolerance of the current iterate.\n *\n *  \\return The KKT tolerance value.\n */\nreal_t acado_getKKT(  );\n\n/** Calculate the objective value.\n *\n *  \\return Value of the objective function.\n */\nreal_t acado_getObjective(  );\n\n\n/* \n * Extern declarations. \n */\n\nextern ACADOworkspace acadoWorkspace;\nextern ACADOvariables acadoVariables;\n\n/** @} */\n\n#ifndef __MATLAB__\n#ifdef __cplusplus\n} /* extern \"C\" */\n#endif /* __cplusplus */\n#endif /* __MATLAB__ */\n\n#endif /* ACADO_COMMON_H */\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_integrator.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_common.h\"\n\n\nvoid acado_rhs_forw(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 28;\n\n/* Compute outputs: */\nout[0] = xd[1];\nout[1] = xd[2];\nout[2] = u[0];\nout[3] = u[1];\nout[4] = xd[8];\nout[5] = xd[9];\nout[6] = xd[10];\nout[7] = xd[11];\nout[8] = xd[12];\nout[9] = xd[13];\nout[10] = xd[14];\nout[11] = xd[15];\nout[12] = (real_t)(0.0000000000000000e+00);\nout[13] = (real_t)(0.0000000000000000e+00);\nout[14] = (real_t)(0.0000000000000000e+00);\nout[15] = (real_t)(0.0000000000000000e+00);\nout[16] = (real_t)(0.0000000000000000e+00);\nout[17] = (real_t)(0.0000000000000000e+00);\nout[18] = (real_t)(0.0000000000000000e+00);\nout[19] = (real_t)(0.0000000000000000e+00);\nout[20] = xd[22];\nout[21] = xd[23];\nout[22] = xd[24];\nout[23] = xd[25];\nout[24] = (real_t)(1.0000000000000000e+00);\nout[25] = (real_t)(0.0000000000000000e+00);\nout[26] = (real_t)(0.0000000000000000e+00);\nout[27] = (real_t)(1.0000000000000000e+00);\n}\n\n/* Fixed step size:0.01 */\nint acado_integrate( real_t* const rk_eta, int resetIntegrator, int rk_index )\n{\nint error;\n\nint run1;\nint numSteps[32] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62};\nint numInts = numSteps[rk_index];\nacadoWorkspace.rk_ttt = 0.0000000000000000e+00;\nrk_eta[4] = 1.0000000000000000e+00;\nrk_eta[5] = 0.0000000000000000e+00;\nrk_eta[6] = 0.0000000000000000e+00;\nrk_eta[7] = 0.0000000000000000e+00;\nrk_eta[8] = 0.0000000000000000e+00;\nrk_eta[9] = 1.0000000000000000e+00;\nrk_eta[10] = 0.0000000000000000e+00;\nrk_eta[11] = 0.0000000000000000e+00;\nrk_eta[12] = 0.0000000000000000e+00;\nrk_eta[13] = 0.0000000000000000e+00;\nrk_eta[14] = 1.0000000000000000e+00;\nrk_eta[15] = 0.0000000000000000e+00;\nrk_eta[16] = 0.0000000000000000e+00;\nrk_eta[17] = 0.0000000000000000e+00;\nrk_eta[18] = 0.0000000000000000e+00;\nrk_eta[19] = 1.0000000000000000e+00;\nrk_eta[20] = 0.0000000000000000e+00;\nrk_eta[21] = 0.0000000000000000e+00;\nrk_eta[22] = 0.0000000000000000e+00;\nrk_eta[23] = 0.0000000000000000e+00;\nrk_eta[24] = 0.0000000000000000e+00;\nrk_eta[25] = 0.0000000000000000e+00;\nrk_eta[26] = 0.0000000000000000e+00;\nrk_eta[27] = 0.0000000000000000e+00;\nacadoWorkspace.rk_xxx[28] = rk_eta[28];\nacadoWorkspace.rk_xxx[29] = rk_eta[29];\nacadoWorkspace.rk_xxx[30] = rk_eta[30];\nacadoWorkspace.rk_xxx[31] = rk_eta[31];\n\nfor (run1 = 0; run1 < 1; ++run1)\n{\nfor(run1 = 0; run1 < numInts; run1++ ) {\nacadoWorkspace.rk_xxx[0] = + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + rk_eta[23];\nacadoWorkspace.rk_xxx[24] = + rk_eta[24];\nacadoWorkspace.rk_xxx[25] = + rk_eta[25];\nacadoWorkspace.rk_xxx[26] = + rk_eta[26];\nacadoWorkspace.rk_xxx[27] = + rk_eta[27];\nacado_rhs_forw( acadoWorkspace.rk_xxx, acadoWorkspace.rk_kkk );\nacadoWorkspace.rk_xxx[0] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[0] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[1] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[2] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[3] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[4] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[5] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[6] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[7] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[8] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[9] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[10] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[11] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[12] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[13] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[14] + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[15] + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[16] + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[17] + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[18] + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[19] + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[20] + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[21] + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[22] + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[23] + rk_eta[23];\nacadoWorkspace.rk_xxx[24] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[24] + rk_eta[24];\nacadoWorkspace.rk_xxx[25] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[25] + rk_eta[25];\nacadoWorkspace.rk_xxx[26] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[26] + rk_eta[26];\nacadoWorkspace.rk_xxx[27] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[27] + rk_eta[27];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 28 ]) );\nacadoWorkspace.rk_xxx[0] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[28] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[29] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[30] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[31] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[32] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[33] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[34] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[35] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[36] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[37] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[38] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[39] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[40] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[41] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[42] + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[43] + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[44] + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[45] + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[46] + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[47] + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[48] + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[49] + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[50] + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[51] + rk_eta[23];\nacadoWorkspace.rk_xxx[24] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[52] + rk_eta[24];\nacadoWorkspace.rk_xxx[25] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[53] + rk_eta[25];\nacadoWorkspace.rk_xxx[26] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[54] + rk_eta[26];\nacadoWorkspace.rk_xxx[27] = + (real_t)5.0000000000000001e-03*acadoWorkspace.rk_kkk[55] + rk_eta[27];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 56 ]) );\nacadoWorkspace.rk_xxx[0] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[56] + rk_eta[0];\nacadoWorkspace.rk_xxx[1] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[57] + rk_eta[1];\nacadoWorkspace.rk_xxx[2] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[58] + rk_eta[2];\nacadoWorkspace.rk_xxx[3] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[59] + rk_eta[3];\nacadoWorkspace.rk_xxx[4] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[60] + rk_eta[4];\nacadoWorkspace.rk_xxx[5] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[61] + rk_eta[5];\nacadoWorkspace.rk_xxx[6] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[62] + rk_eta[6];\nacadoWorkspace.rk_xxx[7] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[63] + rk_eta[7];\nacadoWorkspace.rk_xxx[8] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[64] + rk_eta[8];\nacadoWorkspace.rk_xxx[9] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[65] + rk_eta[9];\nacadoWorkspace.rk_xxx[10] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[66] + rk_eta[10];\nacadoWorkspace.rk_xxx[11] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[67] + rk_eta[11];\nacadoWorkspace.rk_xxx[12] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[68] + rk_eta[12];\nacadoWorkspace.rk_xxx[13] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[69] + rk_eta[13];\nacadoWorkspace.rk_xxx[14] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[70] + rk_eta[14];\nacadoWorkspace.rk_xxx[15] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[71] + rk_eta[15];\nacadoWorkspace.rk_xxx[16] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[72] + rk_eta[16];\nacadoWorkspace.rk_xxx[17] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[73] + rk_eta[17];\nacadoWorkspace.rk_xxx[18] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[74] + rk_eta[18];\nacadoWorkspace.rk_xxx[19] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[75] + rk_eta[19];\nacadoWorkspace.rk_xxx[20] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[76] + rk_eta[20];\nacadoWorkspace.rk_xxx[21] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[77] + rk_eta[21];\nacadoWorkspace.rk_xxx[22] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[78] + rk_eta[22];\nacadoWorkspace.rk_xxx[23] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[79] + rk_eta[23];\nacadoWorkspace.rk_xxx[24] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[80] + rk_eta[24];\nacadoWorkspace.rk_xxx[25] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[81] + rk_eta[25];\nacadoWorkspace.rk_xxx[26] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[82] + rk_eta[26];\nacadoWorkspace.rk_xxx[27] = + (real_t)1.0000000000000000e-02*acadoWorkspace.rk_kkk[83] + rk_eta[27];\nacado_rhs_forw( acadoWorkspace.rk_xxx, &(acadoWorkspace.rk_kkk[ 84 ]) );\nrk_eta[0] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[0] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[28] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[56] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[84];\nrk_eta[1] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[1] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[29] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[57] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[85];\nrk_eta[2] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[2] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[30] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[58] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[86];\nrk_eta[3] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[3] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[31] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[59] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[87];\nrk_eta[4] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[4] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[32] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[60] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[88];\nrk_eta[5] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[5] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[33] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[61] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[89];\nrk_eta[6] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[6] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[34] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[62] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[90];\nrk_eta[7] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[7] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[35] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[63] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[91];\nrk_eta[8] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[8] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[36] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[64] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[92];\nrk_eta[9] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[9] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[37] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[65] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[93];\nrk_eta[10] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[10] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[38] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[66] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[94];\nrk_eta[11] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[11] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[39] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[67] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[95];\nrk_eta[12] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[12] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[40] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[68] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[96];\nrk_eta[13] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[13] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[41] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[69] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[97];\nrk_eta[14] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[14] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[42] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[70] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[98];\nrk_eta[15] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[15] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[43] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[71] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[99];\nrk_eta[16] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[16] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[44] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[72] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[100];\nrk_eta[17] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[17] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[45] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[73] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[101];\nrk_eta[18] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[18] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[46] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[74] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[102];\nrk_eta[19] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[19] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[47] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[75] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[103];\nrk_eta[20] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[20] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[48] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[76] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[104];\nrk_eta[21] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[21] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[49] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[77] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[105];\nrk_eta[22] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[22] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[50] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[78] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[106];\nrk_eta[23] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[23] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[51] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[79] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[107];\nrk_eta[24] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[24] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[52] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[80] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[108];\nrk_eta[25] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[25] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[53] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[81] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[109];\nrk_eta[26] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[26] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[54] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[82] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[110];\nrk_eta[27] += + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[27] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[55] + (real_t)3.3333333333333331e-03*acadoWorkspace.rk_kkk[83] + (real_t)1.6666666666666666e-03*acadoWorkspace.rk_kkk[111];\nacadoWorkspace.rk_ttt += 1.0000000000000000e+00;\n}\n}\nerror = 0;\nreturn error;\n}\n\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_qpoases_interface.cpp",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\nextern \"C\"\n{\n#include \"acado_common.h\"\n}\n\n#include \"INCLUDE/QProblem.hpp\"\n\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\n#include \"INCLUDE/EXTRAS/SolutionAnalysis.hpp\"\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\nstatic int acado_nWSR;\n\n\n\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\nstatic SolutionAnalysis acado_sa;\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\nint acado_solve( void )\n{\n\tacado_nWSR = QPOASES_NWSRMAX;\n\n\tQProblem qp(68, 96);\n\t\n\treturnValue retVal = qp.init(acadoWorkspace.H, acadoWorkspace.g, acadoWorkspace.A, acadoWorkspace.lb, acadoWorkspace.ub, acadoWorkspace.lbA, acadoWorkspace.ubA, acado_nWSR, acadoWorkspace.y);\n\n    qp.getPrimalSolution( acadoWorkspace.x );\n    qp.getDualSolution( acadoWorkspace.y );\n\t\n#if ACADO_COMPUTE_COVARIANCE_MATRIX == 1\n\n\tif (retVal != SUCCESSFUL_RETURN)\n\t\treturn (int)retVal;\n\t\t\n\tretVal = acado_sa.getHessianInverse( &qp,var );\n\n#endif /* ACADO_COMPUTE_COVARIANCE_MATRIX */\n\n\treturn (int)retVal;\n}\n\nint acado_getNWSR( void )\n{\n\treturn acado_nWSR;\n}\n\nconst char* acado_getErrorString( int error )\n{\n\treturn MessageHandling::getErrorString( error );\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_qpoases_interface.hpp",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#ifndef QPOASES_HEADER\n#define QPOASES_HEADER\n\n#ifdef PC_DEBUG\n#include <stdio.h>\n#endif /* PC_DEBUG */\n\n#include <math.h>\n\n#ifdef __cplusplus\n#define EXTERNC extern \"C\"\n#else\n#define EXTERNC\n#endif\n\n/*\n * A set of options for qpOASES\n */\n\n/** Maximum number of optimization variables. */\n#define QPOASES_NVMAX      68\n/** Maximum number of constraints. */\n#define QPOASES_NCMAX      96\n/** Maximum number of working set recalculations. */\n#define QPOASES_NWSRMAX    50\n/** Print level for qpOASES. */\n#define QPOASES_PRINTLEVEL PL_NONE\n/** The value of EPS */\n#define QPOASES_EPS        2.221e-16\n/** Internally used floating point type */\ntypedef double real_t;\n\n/*\n * Forward function declarations\n */\n\n/** A function that calls the QP solver */\nEXTERNC int acado_solve( void );\n\n/** Get the number of active set changes */\nEXTERNC int acado_getNWSR( void );\n\n/** Get the error string. */\nconst char* acado_getErrorString( int error );\n\n#endif /* QPOASES_HEADER */\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/lib_mpc_export/acado_solver.c",
    "content": "/*\n *    This file was auto-generated using the ACADO Toolkit.\n *    \n *    While ACADO Toolkit is free software released under the terms of\n *    the GNU Lesser General Public License (LGPL), the generated code\n *    as such remains the property of the user who used ACADO Toolkit\n *    to generate this code. In particular, user dependent data of the code\n *    do not inherit the GNU LGPL license. On the other hand, parts of the\n *    generated code that are a direct copy of source code from the\n *    ACADO Toolkit or the software tools it is based on, remain, as derived\n *    work, automatically covered by the LGPL license.\n *    \n *    ACADO Toolkit is distributed in the hope that it will be useful,\n *    but WITHOUT ANY WARRANTY; without even the implied warranty of\n *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n *    \n */\n\n\n#include \"acado_common.h\"\n\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/* ACADO code generation                                                      */\n/*                                                                            */\n/******************************************************************************/\n\n\nint acado_modelSimulation(  )\n{\nint ret;\n\nint lRun1;\nret = 0;\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nacadoWorkspace.state[0] = acadoVariables.x[lRun1 * 4];\nacadoWorkspace.state[1] = acadoVariables.x[lRun1 * 4 + 1];\nacadoWorkspace.state[2] = acadoVariables.x[lRun1 * 4 + 2];\nacadoWorkspace.state[3] = acadoVariables.x[lRun1 * 4 + 3];\n\nacadoWorkspace.state[28] = acadoVariables.u[lRun1 * 2];\nacadoWorkspace.state[29] = acadoVariables.u[lRun1 * 2 + 1];\nacadoWorkspace.state[30] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.state[31] = acadoVariables.od[lRun1 * 2 + 1];\n\nret = acado_integrate(acadoWorkspace.state, 1, lRun1);\n\nacadoWorkspace.d[lRun1 * 4] = acadoWorkspace.state[0] - acadoVariables.x[lRun1 * 4 + 4];\nacadoWorkspace.d[lRun1 * 4 + 1] = acadoWorkspace.state[1] - acadoVariables.x[lRun1 * 4 + 5];\nacadoWorkspace.d[lRun1 * 4 + 2] = acadoWorkspace.state[2] - acadoVariables.x[lRun1 * 4 + 6];\nacadoWorkspace.d[lRun1 * 4 + 3] = acadoWorkspace.state[3] - acadoVariables.x[lRun1 * 4 + 7];\n\nacadoWorkspace.evGx[lRun1 * 16] = acadoWorkspace.state[4];\nacadoWorkspace.evGx[lRun1 * 16 + 1] = acadoWorkspace.state[5];\nacadoWorkspace.evGx[lRun1 * 16 + 2] = acadoWorkspace.state[6];\nacadoWorkspace.evGx[lRun1 * 16 + 3] = acadoWorkspace.state[7];\nacadoWorkspace.evGx[lRun1 * 16 + 4] = acadoWorkspace.state[8];\nacadoWorkspace.evGx[lRun1 * 16 + 5] = acadoWorkspace.state[9];\nacadoWorkspace.evGx[lRun1 * 16 + 6] = acadoWorkspace.state[10];\nacadoWorkspace.evGx[lRun1 * 16 + 7] = acadoWorkspace.state[11];\nacadoWorkspace.evGx[lRun1 * 16 + 8] = acadoWorkspace.state[12];\nacadoWorkspace.evGx[lRun1 * 16 + 9] = acadoWorkspace.state[13];\nacadoWorkspace.evGx[lRun1 * 16 + 10] = acadoWorkspace.state[14];\nacadoWorkspace.evGx[lRun1 * 16 + 11] = acadoWorkspace.state[15];\nacadoWorkspace.evGx[lRun1 * 16 + 12] = acadoWorkspace.state[16];\nacadoWorkspace.evGx[lRun1 * 16 + 13] = acadoWorkspace.state[17];\nacadoWorkspace.evGx[lRun1 * 16 + 14] = acadoWorkspace.state[18];\nacadoWorkspace.evGx[lRun1 * 16 + 15] = acadoWorkspace.state[19];\n\nacadoWorkspace.evGu[lRun1 * 8] = acadoWorkspace.state[20];\nacadoWorkspace.evGu[lRun1 * 8 + 1] = acadoWorkspace.state[21];\nacadoWorkspace.evGu[lRun1 * 8 + 2] = acadoWorkspace.state[22];\nacadoWorkspace.evGu[lRun1 * 8 + 3] = acadoWorkspace.state[23];\nacadoWorkspace.evGu[lRun1 * 8 + 4] = acadoWorkspace.state[24];\nacadoWorkspace.evGu[lRun1 * 8 + 5] = acadoWorkspace.state[25];\nacadoWorkspace.evGu[lRun1 * 8 + 6] = acadoWorkspace.state[26];\nacadoWorkspace.evGu[lRun1 * 8 + 7] = acadoWorkspace.state[27];\n}\nreturn ret;\n}\n\nvoid acado_evaluateLSQ(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 4;\n\n/* Compute outputs: */\nout[0] = xd[0];\nout[1] = xd[1];\nout[2] = xd[2];\nout[3] = u[0];\nout[4] = u[1];\n}\n\nvoid acado_evaluateLSQEndTerm(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\n\n/* Compute outputs: */\nout[0] = xd[0];\nout[1] = xd[1];\nout[2] = xd[2];\n}\n\nvoid acado_setObjQ1Q2( real_t* const tmpObjS, real_t* const tmpQ1, real_t* const tmpQ2 )\n{\ntmpQ2[0] = +tmpObjS[0];\ntmpQ2[1] = +tmpObjS[1];\ntmpQ2[2] = +tmpObjS[2];\ntmpQ2[3] = +tmpObjS[3];\ntmpQ2[4] = +tmpObjS[4];\ntmpQ2[5] = +tmpObjS[5];\ntmpQ2[6] = +tmpObjS[6];\ntmpQ2[7] = +tmpObjS[7];\ntmpQ2[8] = +tmpObjS[8];\ntmpQ2[9] = +tmpObjS[9];\ntmpQ2[10] = +tmpObjS[10];\ntmpQ2[11] = +tmpObjS[11];\ntmpQ2[12] = +tmpObjS[12];\ntmpQ2[13] = +tmpObjS[13];\ntmpQ2[14] = +tmpObjS[14];\ntmpQ2[15] = 0.0;\n;\ntmpQ2[16] = 0.0;\n;\ntmpQ2[17] = 0.0;\n;\ntmpQ2[18] = 0.0;\n;\ntmpQ2[19] = 0.0;\n;\ntmpQ1[0] = + tmpQ2[0];\ntmpQ1[1] = + tmpQ2[1];\ntmpQ1[2] = + tmpQ2[2];\ntmpQ1[3] = 0.0;\n;\ntmpQ1[4] = + tmpQ2[5];\ntmpQ1[5] = + tmpQ2[6];\ntmpQ1[6] = + tmpQ2[7];\ntmpQ1[7] = 0.0;\n;\ntmpQ1[8] = + tmpQ2[10];\ntmpQ1[9] = + tmpQ2[11];\ntmpQ1[10] = + tmpQ2[12];\ntmpQ1[11] = 0.0;\n;\ntmpQ1[12] = + tmpQ2[15];\ntmpQ1[13] = + tmpQ2[16];\ntmpQ1[14] = + tmpQ2[17];\ntmpQ1[15] = 0.0;\n;\n}\n\nvoid acado_setObjR1R2( real_t* const tmpObjS, real_t* const tmpR1, real_t* const tmpR2 )\n{\ntmpR2[0] = +tmpObjS[15];\ntmpR2[1] = +tmpObjS[16];\ntmpR2[2] = +tmpObjS[17];\ntmpR2[3] = +tmpObjS[18];\ntmpR2[4] = +tmpObjS[19];\ntmpR2[5] = +tmpObjS[20];\ntmpR2[6] = +tmpObjS[21];\ntmpR2[7] = +tmpObjS[22];\ntmpR2[8] = +tmpObjS[23];\ntmpR2[9] = +tmpObjS[24];\ntmpR1[0] = + tmpR2[3];\ntmpR1[1] = + tmpR2[4];\ntmpR1[2] = + tmpR2[8];\ntmpR1[3] = + tmpR2[9];\n}\n\nvoid acado_setObjQN1QN2( real_t* const tmpObjSEndTerm, real_t* const tmpQN1, real_t* const tmpQN2 )\n{\ntmpQN2[0] = +tmpObjSEndTerm[0];\ntmpQN2[1] = +tmpObjSEndTerm[1];\ntmpQN2[2] = +tmpObjSEndTerm[2];\ntmpQN2[3] = +tmpObjSEndTerm[3];\ntmpQN2[4] = +tmpObjSEndTerm[4];\ntmpQN2[5] = +tmpObjSEndTerm[5];\ntmpQN2[6] = +tmpObjSEndTerm[6];\ntmpQN2[7] = +tmpObjSEndTerm[7];\ntmpQN2[8] = +tmpObjSEndTerm[8];\ntmpQN2[9] = 0.0;\n;\ntmpQN2[10] = 0.0;\n;\ntmpQN2[11] = 0.0;\n;\ntmpQN1[0] = + tmpQN2[0];\ntmpQN1[1] = + tmpQN2[1];\ntmpQN1[2] = + tmpQN2[2];\ntmpQN1[3] = 0.0;\n;\ntmpQN1[4] = + tmpQN2[3];\ntmpQN1[5] = + tmpQN2[4];\ntmpQN1[6] = + tmpQN2[5];\ntmpQN1[7] = 0.0;\n;\ntmpQN1[8] = + tmpQN2[6];\ntmpQN1[9] = + tmpQN2[7];\ntmpQN1[10] = + tmpQN2[8];\ntmpQN1[11] = 0.0;\n;\ntmpQN1[12] = + tmpQN2[9];\ntmpQN1[13] = + tmpQN2[10];\ntmpQN1[14] = + tmpQN2[11];\ntmpQN1[15] = 0.0;\n;\n}\n\nvoid acado_evaluateObjective(  )\n{\nint runObj;\nfor (runObj = 0; runObj < 32; ++runObj)\n{\nacadoWorkspace.objValueIn[0] = acadoVariables.x[runObj * 4];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[runObj * 4 + 1];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[runObj * 4 + 2];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[runObj * 4 + 3];\nacadoWorkspace.objValueIn[4] = acadoVariables.u[runObj * 2];\nacadoWorkspace.objValueIn[5] = acadoVariables.u[runObj * 2 + 1];\nacadoWorkspace.objValueIn[6] = acadoVariables.od[runObj * 2];\nacadoWorkspace.objValueIn[7] = acadoVariables.od[runObj * 2 + 1];\n\nacado_evaluateLSQ( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\nacadoWorkspace.Dy[runObj * 5] = acadoWorkspace.objValueOut[0];\nacadoWorkspace.Dy[runObj * 5 + 1] = acadoWorkspace.objValueOut[1];\nacadoWorkspace.Dy[runObj * 5 + 2] = acadoWorkspace.objValueOut[2];\nacadoWorkspace.Dy[runObj * 5 + 3] = acadoWorkspace.objValueOut[3];\nacadoWorkspace.Dy[runObj * 5 + 4] = acadoWorkspace.objValueOut[4];\n\nacado_setObjQ1Q2( &(acadoVariables.W[ runObj * 25 ]), &(acadoWorkspace.Q1[ runObj * 16 ]), &(acadoWorkspace.Q2[ runObj * 20 ]) );\n\nacado_setObjR1R2( &(acadoVariables.W[ runObj * 25 ]), &(acadoWorkspace.R1[ runObj * 4 ]), &(acadoWorkspace.R2[ runObj * 10 ]) );\n\n}\nacadoWorkspace.objValueIn[0] = acadoVariables.x[128];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[129];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[130];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[131];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[64];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[65];\nacado_evaluateLSQEndTerm( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\n\nacadoWorkspace.DyN[0] = acadoWorkspace.objValueOut[0];\nacadoWorkspace.DyN[1] = acadoWorkspace.objValueOut[1];\nacadoWorkspace.DyN[2] = acadoWorkspace.objValueOut[2];\n\nacado_setObjQN1QN2( acadoVariables.WN, acadoWorkspace.QN1, acadoWorkspace.QN2 );\n\n}\n\nvoid acado_multGxd( real_t* const dOld, real_t* const Gx1, real_t* const dNew )\n{\ndNew[0] += + Gx1[0]*dOld[0] + Gx1[1]*dOld[1] + Gx1[2]*dOld[2] + Gx1[3]*dOld[3];\ndNew[1] += + Gx1[4]*dOld[0] + Gx1[5]*dOld[1] + Gx1[6]*dOld[2] + Gx1[7]*dOld[3];\ndNew[2] += + Gx1[8]*dOld[0] + Gx1[9]*dOld[1] + Gx1[10]*dOld[2] + Gx1[11]*dOld[3];\ndNew[3] += + Gx1[12]*dOld[0] + Gx1[13]*dOld[1] + Gx1[14]*dOld[2] + Gx1[15]*dOld[3];\n}\n\nvoid acado_moveGxT( real_t* const Gx1, real_t* const Gx2 )\n{\nGx2[0] = Gx1[0];\nGx2[1] = Gx1[1];\nGx2[2] = Gx1[2];\nGx2[3] = Gx1[3];\nGx2[4] = Gx1[4];\nGx2[5] = Gx1[5];\nGx2[6] = Gx1[6];\nGx2[7] = Gx1[7];\nGx2[8] = Gx1[8];\nGx2[9] = Gx1[9];\nGx2[10] = Gx1[10];\nGx2[11] = Gx1[11];\nGx2[12] = Gx1[12];\nGx2[13] = Gx1[13];\nGx2[14] = Gx1[14];\nGx2[15] = Gx1[15];\n}\n\nvoid acado_multGxGx( real_t* const Gx1, real_t* const Gx2, real_t* const Gx3 )\n{\nGx3[0] = + Gx1[0]*Gx2[0] + Gx1[1]*Gx2[4] + Gx1[2]*Gx2[8] + Gx1[3]*Gx2[12];\nGx3[1] = + Gx1[0]*Gx2[1] + Gx1[1]*Gx2[5] + Gx1[2]*Gx2[9] + Gx1[3]*Gx2[13];\nGx3[2] = + Gx1[0]*Gx2[2] + Gx1[1]*Gx2[6] + Gx1[2]*Gx2[10] + Gx1[3]*Gx2[14];\nGx3[3] = + Gx1[0]*Gx2[3] + Gx1[1]*Gx2[7] + Gx1[2]*Gx2[11] + Gx1[3]*Gx2[15];\nGx3[4] = + Gx1[4]*Gx2[0] + Gx1[5]*Gx2[4] + Gx1[6]*Gx2[8] + Gx1[7]*Gx2[12];\nGx3[5] = + Gx1[4]*Gx2[1] + Gx1[5]*Gx2[5] + Gx1[6]*Gx2[9] + Gx1[7]*Gx2[13];\nGx3[6] = + Gx1[4]*Gx2[2] + Gx1[5]*Gx2[6] + Gx1[6]*Gx2[10] + Gx1[7]*Gx2[14];\nGx3[7] = + Gx1[4]*Gx2[3] + Gx1[5]*Gx2[7] + Gx1[6]*Gx2[11] + Gx1[7]*Gx2[15];\nGx3[8] = + Gx1[8]*Gx2[0] + Gx1[9]*Gx2[4] + Gx1[10]*Gx2[8] + Gx1[11]*Gx2[12];\nGx3[9] = + Gx1[8]*Gx2[1] + Gx1[9]*Gx2[5] + Gx1[10]*Gx2[9] + Gx1[11]*Gx2[13];\nGx3[10] = + Gx1[8]*Gx2[2] + Gx1[9]*Gx2[6] + Gx1[10]*Gx2[10] + Gx1[11]*Gx2[14];\nGx3[11] = + Gx1[8]*Gx2[3] + Gx1[9]*Gx2[7] + Gx1[10]*Gx2[11] + Gx1[11]*Gx2[15];\nGx3[12] = + Gx1[12]*Gx2[0] + Gx1[13]*Gx2[4] + Gx1[14]*Gx2[8] + Gx1[15]*Gx2[12];\nGx3[13] = + Gx1[12]*Gx2[1] + Gx1[13]*Gx2[5] + Gx1[14]*Gx2[9] + Gx1[15]*Gx2[13];\nGx3[14] = + Gx1[12]*Gx2[2] + Gx1[13]*Gx2[6] + Gx1[14]*Gx2[10] + Gx1[15]*Gx2[14];\nGx3[15] = + Gx1[12]*Gx2[3] + Gx1[13]*Gx2[7] + Gx1[14]*Gx2[11] + Gx1[15]*Gx2[15];\n}\n\nvoid acado_multGxGu( real_t* const Gx1, real_t* const Gu1, real_t* const Gu2 )\n{\nGu2[0] = + Gx1[0]*Gu1[0] + Gx1[1]*Gu1[2] + Gx1[2]*Gu1[4] + Gx1[3]*Gu1[6];\nGu2[1] = + Gx1[0]*Gu1[1] + Gx1[1]*Gu1[3] + Gx1[2]*Gu1[5] + Gx1[3]*Gu1[7];\nGu2[2] = + Gx1[4]*Gu1[0] + Gx1[5]*Gu1[2] + Gx1[6]*Gu1[4] + Gx1[7]*Gu1[6];\nGu2[3] = + Gx1[4]*Gu1[1] + Gx1[5]*Gu1[3] + Gx1[6]*Gu1[5] + Gx1[7]*Gu1[7];\nGu2[4] = + Gx1[8]*Gu1[0] + Gx1[9]*Gu1[2] + Gx1[10]*Gu1[4] + Gx1[11]*Gu1[6];\nGu2[5] = + Gx1[8]*Gu1[1] + Gx1[9]*Gu1[3] + Gx1[10]*Gu1[5] + Gx1[11]*Gu1[7];\nGu2[6] = + Gx1[12]*Gu1[0] + Gx1[13]*Gu1[2] + Gx1[14]*Gu1[4] + Gx1[15]*Gu1[6];\nGu2[7] = + Gx1[12]*Gu1[1] + Gx1[13]*Gu1[3] + Gx1[14]*Gu1[5] + Gx1[15]*Gu1[7];\n}\n\nvoid acado_moveGuE( real_t* const Gu1, real_t* const Gu2 )\n{\nGu2[0] = Gu1[0];\nGu2[1] = Gu1[1];\nGu2[2] = Gu1[2];\nGu2[3] = Gu1[3];\nGu2[4] = Gu1[4];\nGu2[5] = Gu1[5];\nGu2[6] = Gu1[6];\nGu2[7] = Gu1[7];\n}\n\nvoid acado_setBlockH11( int iRow, int iCol, real_t* const Gu1, real_t* const Gu2 )\n{\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 4)] += + Gu1[0]*Gu2[0] + Gu1[2]*Gu2[2] + Gu1[4]*Gu2[4] + Gu1[6]*Gu2[6];\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 5)] += + Gu1[0]*Gu2[1] + Gu1[2]*Gu2[3] + Gu1[4]*Gu2[5] + Gu1[6]*Gu2[7];\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 4)] += + Gu1[1]*Gu2[0] + Gu1[3]*Gu2[2] + Gu1[5]*Gu2[4] + Gu1[7]*Gu2[6];\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 5)] += + Gu1[1]*Gu2[1] + Gu1[3]*Gu2[3] + Gu1[5]*Gu2[5] + Gu1[7]*Gu2[7];\n}\n\nvoid acado_setBlockH11_R1( int iRow, int iCol, real_t* const R11 )\n{\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 4)] = R11[0];\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 5)] = R11[1];\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 4)] = R11[2];\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 5)] = R11[3];\n}\n\nvoid acado_zeroBlockH11( int iRow, int iCol )\n{\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 4)] = 0.0000000000000000e+00;\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 5)] = 0.0000000000000000e+00;\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 4)] = 0.0000000000000000e+00;\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 5)] = 0.0000000000000000e+00;\n}\n\nvoid acado_copyHTH( int iRow, int iCol )\n{\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 4)] = acadoWorkspace.H[(iCol * 136 + 272) + (iRow * 2 + 4)];\nacadoWorkspace.H[(iRow * 136 + 272) + (iCol * 2 + 5)] = acadoWorkspace.H[(iCol * 136 + 340) + (iRow * 2 + 4)];\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 4)] = acadoWorkspace.H[(iCol * 136 + 272) + (iRow * 2 + 5)];\nacadoWorkspace.H[(iRow * 136 + 340) + (iCol * 2 + 5)] = acadoWorkspace.H[(iCol * 136 + 340) + (iRow * 2 + 5)];\n}\n\nvoid acado_multQ1d( real_t* const Gx1, real_t* const dOld, real_t* const dNew )\n{\ndNew[0] = + Gx1[0]*dOld[0] + Gx1[1]*dOld[1] + Gx1[2]*dOld[2] + Gx1[3]*dOld[3];\ndNew[1] = + Gx1[4]*dOld[0] + Gx1[5]*dOld[1] + Gx1[6]*dOld[2] + Gx1[7]*dOld[3];\ndNew[2] = + Gx1[8]*dOld[0] + Gx1[9]*dOld[1] + Gx1[10]*dOld[2] + Gx1[11]*dOld[3];\ndNew[3] = + Gx1[12]*dOld[0] + Gx1[13]*dOld[1] + Gx1[14]*dOld[2] + Gx1[15]*dOld[3];\n}\n\nvoid acado_multQN1d( real_t* const QN1, real_t* const dOld, real_t* const dNew )\n{\ndNew[0] = + acadoWorkspace.QN1[0]*dOld[0] + acadoWorkspace.QN1[1]*dOld[1] + acadoWorkspace.QN1[2]*dOld[2] + acadoWorkspace.QN1[3]*dOld[3];\ndNew[1] = + acadoWorkspace.QN1[4]*dOld[0] + acadoWorkspace.QN1[5]*dOld[1] + acadoWorkspace.QN1[6]*dOld[2] + acadoWorkspace.QN1[7]*dOld[3];\ndNew[2] = + acadoWorkspace.QN1[8]*dOld[0] + acadoWorkspace.QN1[9]*dOld[1] + acadoWorkspace.QN1[10]*dOld[2] + acadoWorkspace.QN1[11]*dOld[3];\ndNew[3] = + acadoWorkspace.QN1[12]*dOld[0] + acadoWorkspace.QN1[13]*dOld[1] + acadoWorkspace.QN1[14]*dOld[2] + acadoWorkspace.QN1[15]*dOld[3];\n}\n\nvoid acado_multRDy( real_t* const R2, real_t* const Dy1, real_t* const RDy1 )\n{\nRDy1[0] = + R2[0]*Dy1[0] + R2[1]*Dy1[1] + R2[2]*Dy1[2] + R2[3]*Dy1[3] + R2[4]*Dy1[4];\nRDy1[1] = + R2[5]*Dy1[0] + R2[6]*Dy1[1] + R2[7]*Dy1[2] + R2[8]*Dy1[3] + R2[9]*Dy1[4];\n}\n\nvoid acado_multQDy( real_t* const Q2, real_t* const Dy1, real_t* const QDy1 )\n{\nQDy1[0] = + Q2[0]*Dy1[0] + Q2[1]*Dy1[1] + Q2[2]*Dy1[2] + Q2[3]*Dy1[3] + Q2[4]*Dy1[4];\nQDy1[1] = + Q2[5]*Dy1[0] + Q2[6]*Dy1[1] + Q2[7]*Dy1[2] + Q2[8]*Dy1[3] + Q2[9]*Dy1[4];\nQDy1[2] = + Q2[10]*Dy1[0] + Q2[11]*Dy1[1] + Q2[12]*Dy1[2] + Q2[13]*Dy1[3] + Q2[14]*Dy1[4];\nQDy1[3] = + Q2[15]*Dy1[0] + Q2[16]*Dy1[1] + Q2[17]*Dy1[2] + Q2[18]*Dy1[3] + Q2[19]*Dy1[4];\n}\n\nvoid acado_multEQDy( real_t* const E1, real_t* const QDy1, real_t* const U1 )\n{\nU1[0] += + E1[0]*QDy1[0] + E1[2]*QDy1[1] + E1[4]*QDy1[2] + E1[6]*QDy1[3];\nU1[1] += + E1[1]*QDy1[0] + E1[3]*QDy1[1] + E1[5]*QDy1[2] + E1[7]*QDy1[3];\n}\n\nvoid acado_multQETGx( real_t* const E1, real_t* const Gx1, real_t* const H101 )\n{\nH101[0] += + E1[0]*Gx1[0] + E1[2]*Gx1[4] + E1[4]*Gx1[8] + E1[6]*Gx1[12];\nH101[1] += + E1[0]*Gx1[1] + E1[2]*Gx1[5] + E1[4]*Gx1[9] + E1[6]*Gx1[13];\nH101[2] += + E1[0]*Gx1[2] + E1[2]*Gx1[6] + E1[4]*Gx1[10] + E1[6]*Gx1[14];\nH101[3] += + E1[0]*Gx1[3] + E1[2]*Gx1[7] + E1[4]*Gx1[11] + E1[6]*Gx1[15];\nH101[4] += + E1[1]*Gx1[0] + E1[3]*Gx1[4] + E1[5]*Gx1[8] + E1[7]*Gx1[12];\nH101[5] += + E1[1]*Gx1[1] + E1[3]*Gx1[5] + E1[5]*Gx1[9] + E1[7]*Gx1[13];\nH101[6] += + E1[1]*Gx1[2] + E1[3]*Gx1[6] + E1[5]*Gx1[10] + E1[7]*Gx1[14];\nH101[7] += + E1[1]*Gx1[3] + E1[3]*Gx1[7] + E1[5]*Gx1[11] + E1[7]*Gx1[15];\n}\n\nvoid acado_zeroBlockH10( real_t* const H101 )\n{\n{ int lCopy; for (lCopy = 0; lCopy < 8; lCopy++) H101[ lCopy ] = 0; }\n}\n\nvoid acado_multEDu( real_t* const E1, real_t* const U1, real_t* const dNew )\n{\ndNew[0] += + E1[0]*U1[0] + E1[1]*U1[1];\ndNew[1] += + E1[2]*U1[0] + E1[3]*U1[1];\ndNew[2] += + E1[4]*U1[0] + E1[5]*U1[1];\ndNew[3] += + E1[6]*U1[0] + E1[7]*U1[1];\n}\n\nvoid acado_zeroBlockH00(  )\n{\nacadoWorkspace.H[0] = 0.0000000000000000e+00;\nacadoWorkspace.H[1] = 0.0000000000000000e+00;\nacadoWorkspace.H[2] = 0.0000000000000000e+00;\nacadoWorkspace.H[3] = 0.0000000000000000e+00;\nacadoWorkspace.H[68] = 0.0000000000000000e+00;\nacadoWorkspace.H[69] = 0.0000000000000000e+00;\nacadoWorkspace.H[70] = 0.0000000000000000e+00;\nacadoWorkspace.H[71] = 0.0000000000000000e+00;\nacadoWorkspace.H[136] = 0.0000000000000000e+00;\nacadoWorkspace.H[137] = 0.0000000000000000e+00;\nacadoWorkspace.H[138] = 0.0000000000000000e+00;\nacadoWorkspace.H[139] = 0.0000000000000000e+00;\nacadoWorkspace.H[204] = 0.0000000000000000e+00;\nacadoWorkspace.H[205] = 0.0000000000000000e+00;\nacadoWorkspace.H[206] = 0.0000000000000000e+00;\nacadoWorkspace.H[207] = 0.0000000000000000e+00;\n}\n\nvoid acado_multCTQC( real_t* const Gx1, real_t* const Gx2 )\n{\nacadoWorkspace.H[0] += + Gx1[0]*Gx2[0] + Gx1[4]*Gx2[4] + Gx1[8]*Gx2[8] + Gx1[12]*Gx2[12];\nacadoWorkspace.H[1] += + Gx1[0]*Gx2[1] + Gx1[4]*Gx2[5] + Gx1[8]*Gx2[9] + Gx1[12]*Gx2[13];\nacadoWorkspace.H[2] += + Gx1[0]*Gx2[2] + Gx1[4]*Gx2[6] + Gx1[8]*Gx2[10] + Gx1[12]*Gx2[14];\nacadoWorkspace.H[3] += + Gx1[0]*Gx2[3] + Gx1[4]*Gx2[7] + Gx1[8]*Gx2[11] + Gx1[12]*Gx2[15];\nacadoWorkspace.H[68] += + Gx1[1]*Gx2[0] + Gx1[5]*Gx2[4] + Gx1[9]*Gx2[8] + Gx1[13]*Gx2[12];\nacadoWorkspace.H[69] += + Gx1[1]*Gx2[1] + Gx1[5]*Gx2[5] + Gx1[9]*Gx2[9] + Gx1[13]*Gx2[13];\nacadoWorkspace.H[70] += + Gx1[1]*Gx2[2] + Gx1[5]*Gx2[6] + Gx1[9]*Gx2[10] + Gx1[13]*Gx2[14];\nacadoWorkspace.H[71] += + Gx1[1]*Gx2[3] + Gx1[5]*Gx2[7] + Gx1[9]*Gx2[11] + Gx1[13]*Gx2[15];\nacadoWorkspace.H[136] += + Gx1[2]*Gx2[0] + Gx1[6]*Gx2[4] + Gx1[10]*Gx2[8] + Gx1[14]*Gx2[12];\nacadoWorkspace.H[137] += + Gx1[2]*Gx2[1] + Gx1[6]*Gx2[5] + Gx1[10]*Gx2[9] + Gx1[14]*Gx2[13];\nacadoWorkspace.H[138] += + Gx1[2]*Gx2[2] + Gx1[6]*Gx2[6] + Gx1[10]*Gx2[10] + Gx1[14]*Gx2[14];\nacadoWorkspace.H[139] += + Gx1[2]*Gx2[3] + Gx1[6]*Gx2[7] + Gx1[10]*Gx2[11] + Gx1[14]*Gx2[15];\nacadoWorkspace.H[204] += + Gx1[3]*Gx2[0] + Gx1[7]*Gx2[4] + Gx1[11]*Gx2[8] + Gx1[15]*Gx2[12];\nacadoWorkspace.H[205] += + Gx1[3]*Gx2[1] + Gx1[7]*Gx2[5] + Gx1[11]*Gx2[9] + Gx1[15]*Gx2[13];\nacadoWorkspace.H[206] += + Gx1[3]*Gx2[2] + Gx1[7]*Gx2[6] + Gx1[11]*Gx2[10] + Gx1[15]*Gx2[14];\nacadoWorkspace.H[207] += + Gx1[3]*Gx2[3] + Gx1[7]*Gx2[7] + Gx1[11]*Gx2[11] + Gx1[15]*Gx2[15];\n}\n\nvoid acado_multHxC( real_t* const Hx, real_t* const Gx, real_t* const A01 )\n{\nA01[0] = + Hx[0]*Gx[0] + Hx[1]*Gx[4] + Hx[2]*Gx[8] + Hx[3]*Gx[12];\nA01[1] = + Hx[0]*Gx[1] + Hx[1]*Gx[5] + Hx[2]*Gx[9] + Hx[3]*Gx[13];\nA01[2] = + Hx[0]*Gx[2] + Hx[1]*Gx[6] + Hx[2]*Gx[10] + Hx[3]*Gx[14];\nA01[3] = + Hx[0]*Gx[3] + Hx[1]*Gx[7] + Hx[2]*Gx[11] + Hx[3]*Gx[15];\nA01[68] = + Hx[4]*Gx[0] + Hx[5]*Gx[4] + Hx[6]*Gx[8] + Hx[7]*Gx[12];\nA01[69] = + Hx[4]*Gx[1] + Hx[5]*Gx[5] + Hx[6]*Gx[9] + Hx[7]*Gx[13];\nA01[70] = + Hx[4]*Gx[2] + Hx[5]*Gx[6] + Hx[6]*Gx[10] + Hx[7]*Gx[14];\nA01[71] = + Hx[4]*Gx[3] + Hx[5]*Gx[7] + Hx[6]*Gx[11] + Hx[7]*Gx[15];\n}\n\nvoid acado_multHxE( real_t* const Hx, real_t* const E, int row, int col )\n{\nacadoWorkspace.A[(row * 136 + 2176) + (col * 2 + 4)] = + Hx[0]*E[0] + Hx[1]*E[2] + Hx[2]*E[4] + Hx[3]*E[6];\nacadoWorkspace.A[(row * 136 + 2176) + (col * 2 + 5)] = + Hx[0]*E[1] + Hx[1]*E[3] + Hx[2]*E[5] + Hx[3]*E[7];\nacadoWorkspace.A[(row * 136 + 2244) + (col * 2 + 4)] = + Hx[4]*E[0] + Hx[5]*E[2] + Hx[6]*E[4] + Hx[7]*E[6];\nacadoWorkspace.A[(row * 136 + 2244) + (col * 2 + 5)] = + Hx[4]*E[1] + Hx[5]*E[3] + Hx[6]*E[5] + Hx[7]*E[7];\n}\n\nvoid acado_macHxd( real_t* const Hx, real_t* const tmpd, real_t* const lbA, real_t* const ubA )\n{\nacadoWorkspace.evHxd[0] = + Hx[0]*tmpd[0] + Hx[1]*tmpd[1] + Hx[2]*tmpd[2] + Hx[3]*tmpd[3];\nacadoWorkspace.evHxd[1] = + Hx[4]*tmpd[0] + Hx[5]*tmpd[1] + Hx[6]*tmpd[2] + Hx[7]*tmpd[3];\nlbA[0] -= acadoWorkspace.evHxd[0];\nlbA[1] -= acadoWorkspace.evHxd[1];\nubA[0] -= acadoWorkspace.evHxd[0];\nubA[1] -= acadoWorkspace.evHxd[1];\n}\n\nvoid acado_evaluatePathConstraints(const real_t* in, real_t* out)\n{\nconst real_t* xd = in;\nconst real_t* u = in + 4;\nconst real_t* od = in + 6;\n/* Vector of auxiliary variables; number of elements: 12. */\nreal_t* a = acadoWorkspace.conAuxVar;\n\n/* Compute intermediate quantities: */\na[0] = (real_t)(0.0000000000000000e+00);\na[1] = (real_t)(0.0000000000000000e+00);\na[2] = (real_t)(1.0000000000000000e+00);\na[3] = (real_t)(0.0000000000000000e+00);\na[4] = (real_t)(0.0000000000000000e+00);\na[5] = (real_t)(0.0000000000000000e+00);\na[6] = (real_t)(1.0000000000000000e+00);\na[7] = (real_t)(0.0000000000000000e+00);\na[8] = (real_t)(0.0000000000000000e+00);\na[9] = (real_t)(1.0000000000000000e+00);\na[10] = (real_t)(0.0000000000000000e+00);\na[11] = (real_t)(1.0000000000000000e+00);\n\n/* Compute outputs: */\nout[0] = ((xd[2]-od[0])+u[1]);\nout[1] = ((xd[2]-od[1])+u[1]);\nout[2] = a[0];\nout[3] = a[1];\nout[4] = a[2];\nout[5] = a[3];\nout[6] = a[4];\nout[7] = a[5];\nout[8] = a[6];\nout[9] = a[7];\nout[10] = a[8];\nout[11] = a[9];\nout[12] = a[10];\nout[13] = a[11];\n}\n\nvoid acado_macCTSlx( real_t* const C0, real_t* const g0 )\n{\ng0[0] += 0.0;\n;\ng0[1] += 0.0;\n;\ng0[2] += 0.0;\n;\ng0[3] += 0.0;\n;\n}\n\nvoid acado_macETSlu( real_t* const E0, real_t* const g1 )\n{\ng1[0] += 0.0;\n;\ng1[1] += 0.0;\n;\n}\n\nvoid acado_condensePrep(  )\n{\nint lRun1;\nint lRun2;\nint lRun3;\nint lRun4;\nint lRun5;\n/** Row vector of size: 32 */\nstatic const int xBoundIndices[ 32 ] = \n{ 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129 };\nacado_moveGuE( acadoWorkspace.evGu, acadoWorkspace.E );\nfor (lRun1 = 1; lRun1 < 32; ++lRun1)\n{\nacado_moveGxT( &(acadoWorkspace.evGx[ lRun1 * 16 ]), acadoWorkspace.T );\nacado_multGxd( &(acadoWorkspace.d[ lRun1 * 4-4 ]), &(acadoWorkspace.evGx[ lRun1 * 16 ]), &(acadoWorkspace.d[ lRun1 * 4 ]) );\nacado_multGxGx( acadoWorkspace.T, &(acadoWorkspace.evGx[ lRun1 * 16-16 ]), &(acadoWorkspace.evGx[ lRun1 * 16 ]) );\nfor (lRun2 = 0; lRun2 < lRun1; ++lRun2)\n{\nlRun4 = (((lRun1) * (lRun1-1)) / (2)) + (lRun2);\nlRun3 = (((lRun1 + 1) * (lRun1)) / (2)) + (lRun2);\nacado_multGxGu( acadoWorkspace.T, &(acadoWorkspace.E[ lRun4 * 8 ]), &(acadoWorkspace.E[ lRun3 * 8 ]) );\n}\nlRun3 = (((lRun1 + 1) * (lRun1)) / (2)) + (lRun2);\nacado_moveGuE( &(acadoWorkspace.evGu[ lRun1 * 8 ]), &(acadoWorkspace.E[ lRun3 * 8 ]) );\n}\n\nacado_multGxGx( &(acadoWorkspace.Q1[ 16 ]), acadoWorkspace.evGx, acadoWorkspace.QGx );\nacado_multGxGx( &(acadoWorkspace.Q1[ 32 ]), &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.QGx[ 16 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.QGx[ 32 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.QGx[ 48 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.QGx[ 64 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.QGx[ 80 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.QGx[ 96 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.QGx[ 112 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.QGx[ 128 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.QGx[ 144 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.QGx[ 160 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.QGx[ 176 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.QGx[ 192 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.QGx[ 208 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.QGx[ 224 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 256 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.QGx[ 240 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 272 ]), &(acadoWorkspace.evGx[ 256 ]), &(acadoWorkspace.QGx[ 256 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 288 ]), &(acadoWorkspace.evGx[ 272 ]), &(acadoWorkspace.QGx[ 272 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 304 ]), &(acadoWorkspace.evGx[ 288 ]), &(acadoWorkspace.QGx[ 288 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 320 ]), &(acadoWorkspace.evGx[ 304 ]), &(acadoWorkspace.QGx[ 304 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 336 ]), &(acadoWorkspace.evGx[ 320 ]), &(acadoWorkspace.QGx[ 320 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 352 ]), &(acadoWorkspace.evGx[ 336 ]), &(acadoWorkspace.QGx[ 336 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 368 ]), &(acadoWorkspace.evGx[ 352 ]), &(acadoWorkspace.QGx[ 352 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 384 ]), &(acadoWorkspace.evGx[ 368 ]), &(acadoWorkspace.QGx[ 368 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 400 ]), &(acadoWorkspace.evGx[ 384 ]), &(acadoWorkspace.QGx[ 384 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 416 ]), &(acadoWorkspace.evGx[ 400 ]), &(acadoWorkspace.QGx[ 400 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 432 ]), &(acadoWorkspace.evGx[ 416 ]), &(acadoWorkspace.QGx[ 416 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 448 ]), &(acadoWorkspace.evGx[ 432 ]), &(acadoWorkspace.QGx[ 432 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 464 ]), &(acadoWorkspace.evGx[ 448 ]), &(acadoWorkspace.QGx[ 448 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 480 ]), &(acadoWorkspace.evGx[ 464 ]), &(acadoWorkspace.QGx[ 464 ]) );\nacado_multGxGx( &(acadoWorkspace.Q1[ 496 ]), &(acadoWorkspace.evGx[ 480 ]), &(acadoWorkspace.QGx[ 480 ]) );\nacado_multGxGx( acadoWorkspace.QN1, &(acadoWorkspace.evGx[ 496 ]), &(acadoWorkspace.QGx[ 496 ]) );\n\nfor (lRun1 = 0; lRun1 < 31; ++lRun1)\n{\nfor (lRun2 = 0; lRun2 < lRun1 + 1; ++lRun2)\n{\nlRun3 = (((lRun1 + 1) * (lRun1)) / (2)) + (lRun2);\nacado_multGxGu( &(acadoWorkspace.Q1[ lRun1 * 16 + 16 ]), &(acadoWorkspace.E[ lRun3 * 8 ]), &(acadoWorkspace.QE[ lRun3 * 8 ]) );\n}\n}\n\nfor (lRun2 = 0; lRun2 < lRun1 + 1; ++lRun2)\n{\nlRun3 = (((lRun1 + 1) * (lRun1)) / (2)) + (lRun2);\nacado_multGxGu( acadoWorkspace.QN1, &(acadoWorkspace.E[ lRun3 * 8 ]), &(acadoWorkspace.QE[ lRun3 * 8 ]) );\n}\n\nacado_zeroBlockH00(  );\nacado_multCTQC( acadoWorkspace.evGx, acadoWorkspace.QGx );\nacado_multCTQC( &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.QGx[ 16 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.QGx[ 32 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.QGx[ 48 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.QGx[ 64 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.QGx[ 80 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.QGx[ 96 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.QGx[ 112 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.QGx[ 128 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.QGx[ 144 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.QGx[ 160 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.QGx[ 176 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.QGx[ 192 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.QGx[ 208 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.QGx[ 224 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.QGx[ 240 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 256 ]), &(acadoWorkspace.QGx[ 256 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 272 ]), &(acadoWorkspace.QGx[ 272 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 288 ]), &(acadoWorkspace.QGx[ 288 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 304 ]), &(acadoWorkspace.QGx[ 304 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 320 ]), &(acadoWorkspace.QGx[ 320 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 336 ]), &(acadoWorkspace.QGx[ 336 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 352 ]), &(acadoWorkspace.QGx[ 352 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 368 ]), &(acadoWorkspace.QGx[ 368 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 384 ]), &(acadoWorkspace.QGx[ 384 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 400 ]), &(acadoWorkspace.QGx[ 400 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 416 ]), &(acadoWorkspace.QGx[ 416 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 432 ]), &(acadoWorkspace.QGx[ 432 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 448 ]), &(acadoWorkspace.QGx[ 448 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 464 ]), &(acadoWorkspace.QGx[ 464 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 480 ]), &(acadoWorkspace.QGx[ 480 ]) );\nacado_multCTQC( &(acadoWorkspace.evGx[ 496 ]), &(acadoWorkspace.QGx[ 496 ]) );\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nacado_zeroBlockH10( &(acadoWorkspace.H10[ lRun1 * 8 ]) );\nfor (lRun2 = lRun1; lRun2 < 32; ++lRun2)\n{\nlRun3 = (((lRun2 + 1) * (lRun2)) / (2)) + (lRun1);\nacado_multQETGx( &(acadoWorkspace.QE[ lRun3 * 8 ]), &(acadoWorkspace.evGx[ lRun2 * 16 ]), &(acadoWorkspace.H10[ lRun1 * 8 ]) );\n}\n}\n\nfor (lRun2 = 0;lRun2 < 4; ++lRun2)\nfor (lRun3 = 0;lRun3 < 64; ++lRun3)\nacadoWorkspace.H[(lRun2 * 68) + (lRun3 + 4)] = acadoWorkspace.H10[(lRun3 * 4) + (lRun2)];\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nacado_setBlockH11_R1( lRun1, lRun1, &(acadoWorkspace.R1[ lRun1 * 4 ]) );\nlRun2 = lRun1;\nfor (lRun3 = lRun1; lRun3 < 32; ++lRun3)\n{\nlRun4 = (((lRun3 + 1) * (lRun3)) / (2)) + (lRun1);\nlRun5 = (((lRun3 + 1) * (lRun3)) / (2)) + (lRun2);\nacado_setBlockH11( lRun1, lRun2, &(acadoWorkspace.E[ lRun4 * 8 ]), &(acadoWorkspace.QE[ lRun5 * 8 ]) );\n}\nfor (lRun2 = lRun1 + 1; lRun2 < 32; ++lRun2)\n{\nacado_zeroBlockH11( lRun1, lRun2 );\nfor (lRun3 = lRun2; lRun3 < 32; ++lRun3)\n{\nlRun4 = (((lRun3 + 1) * (lRun3)) / (2)) + (lRun1);\nlRun5 = (((lRun3 + 1) * (lRun3)) / (2)) + (lRun2);\nacado_setBlockH11( lRun1, lRun2, &(acadoWorkspace.E[ lRun4 * 8 ]), &(acadoWorkspace.QE[ lRun5 * 8 ]) );\n}\n}\n}\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nfor (lRun2 = 0; lRun2 < lRun1; ++lRun2)\n{\nacado_copyHTH( lRun1, lRun2 );\n}\n}\n\nfor (lRun2 = 0;lRun2 < 64; ++lRun2)\nfor (lRun3 = 0;lRun3 < 4; ++lRun3)\nacadoWorkspace.H[(lRun2 * 68 + 272) + (lRun3)] = acadoWorkspace.H10[(lRun2 * 4) + (lRun3)];\n\nacado_multQ1d( &(acadoWorkspace.Q1[ 16 ]), acadoWorkspace.d, acadoWorkspace.Qd );\nacado_multQ1d( &(acadoWorkspace.Q1[ 32 ]), &(acadoWorkspace.d[ 4 ]), &(acadoWorkspace.Qd[ 4 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 48 ]), &(acadoWorkspace.d[ 8 ]), &(acadoWorkspace.Qd[ 8 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 64 ]), &(acadoWorkspace.d[ 12 ]), &(acadoWorkspace.Qd[ 12 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 80 ]), &(acadoWorkspace.d[ 16 ]), &(acadoWorkspace.Qd[ 16 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 96 ]), &(acadoWorkspace.d[ 20 ]), &(acadoWorkspace.Qd[ 20 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 112 ]), &(acadoWorkspace.d[ 24 ]), &(acadoWorkspace.Qd[ 24 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 128 ]), &(acadoWorkspace.d[ 28 ]), &(acadoWorkspace.Qd[ 28 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 144 ]), &(acadoWorkspace.d[ 32 ]), &(acadoWorkspace.Qd[ 32 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 160 ]), &(acadoWorkspace.d[ 36 ]), &(acadoWorkspace.Qd[ 36 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 176 ]), &(acadoWorkspace.d[ 40 ]), &(acadoWorkspace.Qd[ 40 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 192 ]), &(acadoWorkspace.d[ 44 ]), &(acadoWorkspace.Qd[ 44 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 208 ]), &(acadoWorkspace.d[ 48 ]), &(acadoWorkspace.Qd[ 48 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 224 ]), &(acadoWorkspace.d[ 52 ]), &(acadoWorkspace.Qd[ 52 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 240 ]), &(acadoWorkspace.d[ 56 ]), &(acadoWorkspace.Qd[ 56 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 256 ]), &(acadoWorkspace.d[ 60 ]), &(acadoWorkspace.Qd[ 60 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 272 ]), &(acadoWorkspace.d[ 64 ]), &(acadoWorkspace.Qd[ 64 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 288 ]), &(acadoWorkspace.d[ 68 ]), &(acadoWorkspace.Qd[ 68 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 304 ]), &(acadoWorkspace.d[ 72 ]), &(acadoWorkspace.Qd[ 72 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 320 ]), &(acadoWorkspace.d[ 76 ]), &(acadoWorkspace.Qd[ 76 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 336 ]), &(acadoWorkspace.d[ 80 ]), &(acadoWorkspace.Qd[ 80 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 352 ]), &(acadoWorkspace.d[ 84 ]), &(acadoWorkspace.Qd[ 84 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 368 ]), &(acadoWorkspace.d[ 88 ]), &(acadoWorkspace.Qd[ 88 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 384 ]), &(acadoWorkspace.d[ 92 ]), &(acadoWorkspace.Qd[ 92 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 400 ]), &(acadoWorkspace.d[ 96 ]), &(acadoWorkspace.Qd[ 96 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 416 ]), &(acadoWorkspace.d[ 100 ]), &(acadoWorkspace.Qd[ 100 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 432 ]), &(acadoWorkspace.d[ 104 ]), &(acadoWorkspace.Qd[ 104 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 448 ]), &(acadoWorkspace.d[ 108 ]), &(acadoWorkspace.Qd[ 108 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 464 ]), &(acadoWorkspace.d[ 112 ]), &(acadoWorkspace.Qd[ 112 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 480 ]), &(acadoWorkspace.d[ 116 ]), &(acadoWorkspace.Qd[ 116 ]) );\nacado_multQ1d( &(acadoWorkspace.Q1[ 496 ]), &(acadoWorkspace.d[ 120 ]), &(acadoWorkspace.Qd[ 120 ]) );\nacado_multQN1d( acadoWorkspace.QN1, &(acadoWorkspace.d[ 124 ]), &(acadoWorkspace.Qd[ 124 ]) );\n\nacado_macCTSlx( acadoWorkspace.evGx, acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 16 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 32 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 48 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 64 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 80 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 96 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 112 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 128 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 144 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 160 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 176 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 192 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 208 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 224 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 240 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 256 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 272 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 288 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 304 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 320 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 336 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 352 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 368 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 384 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 400 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 416 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 432 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 448 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 464 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 480 ]), acadoWorkspace.g );\nacado_macCTSlx( &(acadoWorkspace.evGx[ 496 ]), acadoWorkspace.g );\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nfor (lRun2 = lRun1; lRun2 < 32; ++lRun2)\n{\nlRun3 = (((lRun2 + 1) * (lRun2)) / (2)) + (lRun1);\nacado_macETSlu( &(acadoWorkspace.QE[ lRun3 * 8 ]), &(acadoWorkspace.g[ lRun1 * 2 + 4 ]) );\n}\n}\nacadoWorkspace.lb[4] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[0];\nacadoWorkspace.lb[5] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[1];\nacadoWorkspace.lb[6] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[2];\nacadoWorkspace.lb[7] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[3];\nacadoWorkspace.lb[8] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[4];\nacadoWorkspace.lb[9] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[5];\nacadoWorkspace.lb[10] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[6];\nacadoWorkspace.lb[11] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[7];\nacadoWorkspace.lb[12] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[8];\nacadoWorkspace.lb[13] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[9];\nacadoWorkspace.lb[14] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[10];\nacadoWorkspace.lb[15] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[11];\nacadoWorkspace.lb[16] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[12];\nacadoWorkspace.lb[17] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[13];\nacadoWorkspace.lb[18] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[14];\nacadoWorkspace.lb[19] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[15];\nacadoWorkspace.lb[20] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[16];\nacadoWorkspace.lb[21] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[17];\nacadoWorkspace.lb[22] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[18];\nacadoWorkspace.lb[23] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[19];\nacadoWorkspace.lb[24] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[20];\nacadoWorkspace.lb[25] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[21];\nacadoWorkspace.lb[26] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[22];\nacadoWorkspace.lb[27] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[23];\nacadoWorkspace.lb[28] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[24];\nacadoWorkspace.lb[29] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[25];\nacadoWorkspace.lb[30] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[26];\nacadoWorkspace.lb[31] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[27];\nacadoWorkspace.lb[32] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[28];\nacadoWorkspace.lb[33] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[29];\nacadoWorkspace.lb[34] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[30];\nacadoWorkspace.lb[35] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[31];\nacadoWorkspace.lb[36] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[32];\nacadoWorkspace.lb[37] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[33];\nacadoWorkspace.lb[38] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[34];\nacadoWorkspace.lb[39] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[35];\nacadoWorkspace.lb[40] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[36];\nacadoWorkspace.lb[41] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[37];\nacadoWorkspace.lb[42] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[38];\nacadoWorkspace.lb[43] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[39];\nacadoWorkspace.lb[44] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[40];\nacadoWorkspace.lb[45] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[41];\nacadoWorkspace.lb[46] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[42];\nacadoWorkspace.lb[47] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[43];\nacadoWorkspace.lb[48] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[44];\nacadoWorkspace.lb[49] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[45];\nacadoWorkspace.lb[50] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[46];\nacadoWorkspace.lb[51] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[47];\nacadoWorkspace.lb[52] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[48];\nacadoWorkspace.lb[53] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[49];\nacadoWorkspace.lb[54] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[50];\nacadoWorkspace.lb[55] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[51];\nacadoWorkspace.lb[56] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[52];\nacadoWorkspace.lb[57] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[53];\nacadoWorkspace.lb[58] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[54];\nacadoWorkspace.lb[59] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[55];\nacadoWorkspace.lb[60] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[56];\nacadoWorkspace.lb[61] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[57];\nacadoWorkspace.lb[62] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[58];\nacadoWorkspace.lb[63] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[59];\nacadoWorkspace.lb[64] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[60];\nacadoWorkspace.lb[65] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[61];\nacadoWorkspace.lb[66] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[62];\nacadoWorkspace.lb[67] = (real_t)-1.0000000000000000e+12 - acadoVariables.u[63];\nacadoWorkspace.ub[4] = (real_t)1.0000000000000000e+12 - acadoVariables.u[0];\nacadoWorkspace.ub[5] = (real_t)1.0000000000000000e+12 - acadoVariables.u[1];\nacadoWorkspace.ub[6] = (real_t)1.0000000000000000e+12 - acadoVariables.u[2];\nacadoWorkspace.ub[7] = (real_t)1.0000000000000000e+12 - acadoVariables.u[3];\nacadoWorkspace.ub[8] = (real_t)1.0000000000000000e+12 - acadoVariables.u[4];\nacadoWorkspace.ub[9] = (real_t)1.0000000000000000e+12 - acadoVariables.u[5];\nacadoWorkspace.ub[10] = (real_t)1.0000000000000000e+12 - acadoVariables.u[6];\nacadoWorkspace.ub[11] = (real_t)1.0000000000000000e+12 - acadoVariables.u[7];\nacadoWorkspace.ub[12] = (real_t)1.0000000000000000e+12 - acadoVariables.u[8];\nacadoWorkspace.ub[13] = (real_t)1.0000000000000000e+12 - acadoVariables.u[9];\nacadoWorkspace.ub[14] = (real_t)1.0000000000000000e+12 - acadoVariables.u[10];\nacadoWorkspace.ub[15] = (real_t)1.0000000000000000e+12 - acadoVariables.u[11];\nacadoWorkspace.ub[16] = (real_t)1.0000000000000000e+12 - acadoVariables.u[12];\nacadoWorkspace.ub[17] = (real_t)1.0000000000000000e+12 - acadoVariables.u[13];\nacadoWorkspace.ub[18] = (real_t)1.0000000000000000e+12 - acadoVariables.u[14];\nacadoWorkspace.ub[19] = (real_t)1.0000000000000000e+12 - acadoVariables.u[15];\nacadoWorkspace.ub[20] = (real_t)1.0000000000000000e+12 - acadoVariables.u[16];\nacadoWorkspace.ub[21] = (real_t)1.0000000000000000e+12 - acadoVariables.u[17];\nacadoWorkspace.ub[22] = (real_t)1.0000000000000000e+12 - acadoVariables.u[18];\nacadoWorkspace.ub[23] = (real_t)1.0000000000000000e+12 - acadoVariables.u[19];\nacadoWorkspace.ub[24] = (real_t)1.0000000000000000e+12 - acadoVariables.u[20];\nacadoWorkspace.ub[25] = (real_t)1.0000000000000000e+12 - acadoVariables.u[21];\nacadoWorkspace.ub[26] = (real_t)1.0000000000000000e+12 - acadoVariables.u[22];\nacadoWorkspace.ub[27] = (real_t)1.0000000000000000e+12 - acadoVariables.u[23];\nacadoWorkspace.ub[28] = (real_t)1.0000000000000000e+12 - acadoVariables.u[24];\nacadoWorkspace.ub[29] = (real_t)1.0000000000000000e+12 - acadoVariables.u[25];\nacadoWorkspace.ub[30] = (real_t)1.0000000000000000e+12 - acadoVariables.u[26];\nacadoWorkspace.ub[31] = (real_t)1.0000000000000000e+12 - acadoVariables.u[27];\nacadoWorkspace.ub[32] = (real_t)1.0000000000000000e+12 - acadoVariables.u[28];\nacadoWorkspace.ub[33] = (real_t)1.0000000000000000e+12 - acadoVariables.u[29];\nacadoWorkspace.ub[34] = (real_t)1.0000000000000000e+12 - acadoVariables.u[30];\nacadoWorkspace.ub[35] = (real_t)1.0000000000000000e+12 - acadoVariables.u[31];\nacadoWorkspace.ub[36] = (real_t)1.0000000000000000e+12 - acadoVariables.u[32];\nacadoWorkspace.ub[37] = (real_t)1.0000000000000000e+12 - acadoVariables.u[33];\nacadoWorkspace.ub[38] = (real_t)1.0000000000000000e+12 - acadoVariables.u[34];\nacadoWorkspace.ub[39] = (real_t)1.0000000000000000e+12 - acadoVariables.u[35];\nacadoWorkspace.ub[40] = (real_t)1.0000000000000000e+12 - acadoVariables.u[36];\nacadoWorkspace.ub[41] = (real_t)1.0000000000000000e+12 - acadoVariables.u[37];\nacadoWorkspace.ub[42] = (real_t)1.0000000000000000e+12 - acadoVariables.u[38];\nacadoWorkspace.ub[43] = (real_t)1.0000000000000000e+12 - acadoVariables.u[39];\nacadoWorkspace.ub[44] = (real_t)1.0000000000000000e+12 - acadoVariables.u[40];\nacadoWorkspace.ub[45] = (real_t)1.0000000000000000e+12 - acadoVariables.u[41];\nacadoWorkspace.ub[46] = (real_t)1.0000000000000000e+12 - acadoVariables.u[42];\nacadoWorkspace.ub[47] = (real_t)1.0000000000000000e+12 - acadoVariables.u[43];\nacadoWorkspace.ub[48] = (real_t)1.0000000000000000e+12 - acadoVariables.u[44];\nacadoWorkspace.ub[49] = (real_t)1.0000000000000000e+12 - acadoVariables.u[45];\nacadoWorkspace.ub[50] = (real_t)1.0000000000000000e+12 - acadoVariables.u[46];\nacadoWorkspace.ub[51] = (real_t)1.0000000000000000e+12 - acadoVariables.u[47];\nacadoWorkspace.ub[52] = (real_t)1.0000000000000000e+12 - acadoVariables.u[48];\nacadoWorkspace.ub[53] = (real_t)1.0000000000000000e+12 - acadoVariables.u[49];\nacadoWorkspace.ub[54] = (real_t)1.0000000000000000e+12 - acadoVariables.u[50];\nacadoWorkspace.ub[55] = (real_t)1.0000000000000000e+12 - acadoVariables.u[51];\nacadoWorkspace.ub[56] = (real_t)1.0000000000000000e+12 - acadoVariables.u[52];\nacadoWorkspace.ub[57] = (real_t)1.0000000000000000e+12 - acadoVariables.u[53];\nacadoWorkspace.ub[58] = (real_t)1.0000000000000000e+12 - acadoVariables.u[54];\nacadoWorkspace.ub[59] = (real_t)1.0000000000000000e+12 - acadoVariables.u[55];\nacadoWorkspace.ub[60] = (real_t)1.0000000000000000e+12 - acadoVariables.u[56];\nacadoWorkspace.ub[61] = (real_t)1.0000000000000000e+12 - acadoVariables.u[57];\nacadoWorkspace.ub[62] = (real_t)1.0000000000000000e+12 - acadoVariables.u[58];\nacadoWorkspace.ub[63] = (real_t)1.0000000000000000e+12 - acadoVariables.u[59];\nacadoWorkspace.ub[64] = (real_t)1.0000000000000000e+12 - acadoVariables.u[60];\nacadoWorkspace.ub[65] = (real_t)1.0000000000000000e+12 - acadoVariables.u[61];\nacadoWorkspace.ub[66] = (real_t)1.0000000000000000e+12 - acadoVariables.u[62];\nacadoWorkspace.ub[67] = (real_t)1.0000000000000000e+12 - acadoVariables.u[63];\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nlRun3 = xBoundIndices[ lRun1 ] - 4;\nlRun4 = ((lRun3) / (4)) + (1);\nacadoWorkspace.A[lRun1 * 68] = acadoWorkspace.evGx[lRun3 * 4];\nacadoWorkspace.A[lRun1 * 68 + 1] = acadoWorkspace.evGx[lRun3 * 4 + 1];\nacadoWorkspace.A[lRun1 * 68 + 2] = acadoWorkspace.evGx[lRun3 * 4 + 2];\nacadoWorkspace.A[lRun1 * 68 + 3] = acadoWorkspace.evGx[lRun3 * 4 + 3];\nfor (lRun2 = 0; lRun2 < lRun4; ++lRun2)\n{\nlRun5 = (((((lRun4) * (lRun4-1)) / (2)) + (lRun2)) * (4)) + ((lRun3) % (4));\nacadoWorkspace.A[(lRun1 * 68) + (lRun2 * 2 + 4)] = acadoWorkspace.E[lRun5 * 2];\nacadoWorkspace.A[(lRun1 * 68) + (lRun2 * 2 + 5)] = acadoWorkspace.E[lRun5 * 2 + 1];\n}\n}\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nacadoWorkspace.conValueIn[0] = acadoVariables.x[lRun1 * 4];\nacadoWorkspace.conValueIn[1] = acadoVariables.x[lRun1 * 4 + 1];\nacadoWorkspace.conValueIn[2] = acadoVariables.x[lRun1 * 4 + 2];\nacadoWorkspace.conValueIn[3] = acadoVariables.x[lRun1 * 4 + 3];\nacadoWorkspace.conValueIn[4] = acadoVariables.u[lRun1 * 2];\nacadoWorkspace.conValueIn[5] = acadoVariables.u[lRun1 * 2 + 1];\nacadoWorkspace.conValueIn[6] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.conValueIn[7] = acadoVariables.od[lRun1 * 2 + 1];\nacado_evaluatePathConstraints( acadoWorkspace.conValueIn, acadoWorkspace.conValueOut );\nacadoWorkspace.evH[lRun1 * 2] = acadoWorkspace.conValueOut[0];\nacadoWorkspace.evH[lRun1 * 2 + 1] = acadoWorkspace.conValueOut[1];\n\nacadoWorkspace.evHx[lRun1 * 8] = acadoWorkspace.conValueOut[2];\nacadoWorkspace.evHx[lRun1 * 8 + 1] = acadoWorkspace.conValueOut[3];\nacadoWorkspace.evHx[lRun1 * 8 + 2] = acadoWorkspace.conValueOut[4];\nacadoWorkspace.evHx[lRun1 * 8 + 3] = acadoWorkspace.conValueOut[5];\nacadoWorkspace.evHx[lRun1 * 8 + 4] = acadoWorkspace.conValueOut[6];\nacadoWorkspace.evHx[lRun1 * 8 + 5] = acadoWorkspace.conValueOut[7];\nacadoWorkspace.evHx[lRun1 * 8 + 6] = acadoWorkspace.conValueOut[8];\nacadoWorkspace.evHx[lRun1 * 8 + 7] = acadoWorkspace.conValueOut[9];\nacadoWorkspace.evHu[lRun1 * 4] = acadoWorkspace.conValueOut[10];\nacadoWorkspace.evHu[lRun1 * 4 + 1] = acadoWorkspace.conValueOut[11];\nacadoWorkspace.evHu[lRun1 * 4 + 2] = acadoWorkspace.conValueOut[12];\nacadoWorkspace.evHu[lRun1 * 4 + 3] = acadoWorkspace.conValueOut[13];\n}\n\nacadoWorkspace.A[2176] = acadoWorkspace.evHx[0];\nacadoWorkspace.A[2177] = acadoWorkspace.evHx[1];\nacadoWorkspace.A[2178] = acadoWorkspace.evHx[2];\nacadoWorkspace.A[2179] = acadoWorkspace.evHx[3];\nacadoWorkspace.A[2244] = acadoWorkspace.evHx[4];\nacadoWorkspace.A[2245] = acadoWorkspace.evHx[5];\nacadoWorkspace.A[2246] = acadoWorkspace.evHx[6];\nacadoWorkspace.A[2247] = acadoWorkspace.evHx[7];\n\nacado_multHxC( &(acadoWorkspace.evHx[ 8 ]), acadoWorkspace.evGx, &(acadoWorkspace.A[ 2312 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 16 ]), &(acadoWorkspace.evGx[ 16 ]), &(acadoWorkspace.A[ 2448 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 24 ]), &(acadoWorkspace.evGx[ 32 ]), &(acadoWorkspace.A[ 2584 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 32 ]), &(acadoWorkspace.evGx[ 48 ]), &(acadoWorkspace.A[ 2720 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 40 ]), &(acadoWorkspace.evGx[ 64 ]), &(acadoWorkspace.A[ 2856 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 48 ]), &(acadoWorkspace.evGx[ 80 ]), &(acadoWorkspace.A[ 2992 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 56 ]), &(acadoWorkspace.evGx[ 96 ]), &(acadoWorkspace.A[ 3128 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 64 ]), &(acadoWorkspace.evGx[ 112 ]), &(acadoWorkspace.A[ 3264 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 72 ]), &(acadoWorkspace.evGx[ 128 ]), &(acadoWorkspace.A[ 3400 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 80 ]), &(acadoWorkspace.evGx[ 144 ]), &(acadoWorkspace.A[ 3536 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 88 ]), &(acadoWorkspace.evGx[ 160 ]), &(acadoWorkspace.A[ 3672 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 96 ]), &(acadoWorkspace.evGx[ 176 ]), &(acadoWorkspace.A[ 3808 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 104 ]), &(acadoWorkspace.evGx[ 192 ]), &(acadoWorkspace.A[ 3944 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 112 ]), &(acadoWorkspace.evGx[ 208 ]), &(acadoWorkspace.A[ 4080 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 120 ]), &(acadoWorkspace.evGx[ 224 ]), &(acadoWorkspace.A[ 4216 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 128 ]), &(acadoWorkspace.evGx[ 240 ]), &(acadoWorkspace.A[ 4352 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 136 ]), &(acadoWorkspace.evGx[ 256 ]), &(acadoWorkspace.A[ 4488 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 144 ]), &(acadoWorkspace.evGx[ 272 ]), &(acadoWorkspace.A[ 4624 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 152 ]), &(acadoWorkspace.evGx[ 288 ]), &(acadoWorkspace.A[ 4760 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 160 ]), &(acadoWorkspace.evGx[ 304 ]), &(acadoWorkspace.A[ 4896 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 168 ]), &(acadoWorkspace.evGx[ 320 ]), &(acadoWorkspace.A[ 5032 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 176 ]), &(acadoWorkspace.evGx[ 336 ]), &(acadoWorkspace.A[ 5168 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 184 ]), &(acadoWorkspace.evGx[ 352 ]), &(acadoWorkspace.A[ 5304 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 192 ]), &(acadoWorkspace.evGx[ 368 ]), &(acadoWorkspace.A[ 5440 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 200 ]), &(acadoWorkspace.evGx[ 384 ]), &(acadoWorkspace.A[ 5576 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 208 ]), &(acadoWorkspace.evGx[ 400 ]), &(acadoWorkspace.A[ 5712 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 216 ]), &(acadoWorkspace.evGx[ 416 ]), &(acadoWorkspace.A[ 5848 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 224 ]), &(acadoWorkspace.evGx[ 432 ]), &(acadoWorkspace.A[ 5984 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 232 ]), &(acadoWorkspace.evGx[ 448 ]), &(acadoWorkspace.A[ 6120 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 240 ]), &(acadoWorkspace.evGx[ 464 ]), &(acadoWorkspace.A[ 6256 ]) );\nacado_multHxC( &(acadoWorkspace.evHx[ 248 ]), &(acadoWorkspace.evGx[ 480 ]), &(acadoWorkspace.A[ 6392 ]) );\n\nfor (lRun2 = 0; lRun2 < 31; ++lRun2)\n{\nfor (lRun3 = 0; lRun3 < lRun2 + 1; ++lRun3)\n{\nlRun4 = (((lRun2 + 1) * (lRun2)) / (2)) + (lRun3);\nlRun5 = lRun2 + 1;\nacado_multHxE( &(acadoWorkspace.evHx[ lRun2 * 8 + 8 ]), &(acadoWorkspace.E[ lRun4 * 8 ]), lRun5, lRun3 );\n}\n}\n\nacadoWorkspace.A[2180] = acadoWorkspace.evHu[0];\nacadoWorkspace.A[2181] = acadoWorkspace.evHu[1];\nacadoWorkspace.A[2248] = acadoWorkspace.evHu[2];\nacadoWorkspace.A[2249] = acadoWorkspace.evHu[3];\nacadoWorkspace.A[2318] = acadoWorkspace.evHu[4];\nacadoWorkspace.A[2319] = acadoWorkspace.evHu[5];\nacadoWorkspace.A[2386] = acadoWorkspace.evHu[6];\nacadoWorkspace.A[2387] = acadoWorkspace.evHu[7];\nacadoWorkspace.A[2456] = acadoWorkspace.evHu[8];\nacadoWorkspace.A[2457] = acadoWorkspace.evHu[9];\nacadoWorkspace.A[2524] = acadoWorkspace.evHu[10];\nacadoWorkspace.A[2525] = acadoWorkspace.evHu[11];\nacadoWorkspace.A[2594] = acadoWorkspace.evHu[12];\nacadoWorkspace.A[2595] = acadoWorkspace.evHu[13];\nacadoWorkspace.A[2662] = acadoWorkspace.evHu[14];\nacadoWorkspace.A[2663] = acadoWorkspace.evHu[15];\nacadoWorkspace.A[2732] = acadoWorkspace.evHu[16];\nacadoWorkspace.A[2733] = acadoWorkspace.evHu[17];\nacadoWorkspace.A[2800] = acadoWorkspace.evHu[18];\nacadoWorkspace.A[2801] = acadoWorkspace.evHu[19];\nacadoWorkspace.A[2870] = acadoWorkspace.evHu[20];\nacadoWorkspace.A[2871] = acadoWorkspace.evHu[21];\nacadoWorkspace.A[2938] = acadoWorkspace.evHu[22];\nacadoWorkspace.A[2939] = acadoWorkspace.evHu[23];\nacadoWorkspace.A[3008] = acadoWorkspace.evHu[24];\nacadoWorkspace.A[3009] = acadoWorkspace.evHu[25];\nacadoWorkspace.A[3076] = acadoWorkspace.evHu[26];\nacadoWorkspace.A[3077] = acadoWorkspace.evHu[27];\nacadoWorkspace.A[3146] = acadoWorkspace.evHu[28];\nacadoWorkspace.A[3147] = acadoWorkspace.evHu[29];\nacadoWorkspace.A[3214] = acadoWorkspace.evHu[30];\nacadoWorkspace.A[3215] = acadoWorkspace.evHu[31];\nacadoWorkspace.A[3284] = acadoWorkspace.evHu[32];\nacadoWorkspace.A[3285] = acadoWorkspace.evHu[33];\nacadoWorkspace.A[3352] = acadoWorkspace.evHu[34];\nacadoWorkspace.A[3353] = acadoWorkspace.evHu[35];\nacadoWorkspace.A[3422] = acadoWorkspace.evHu[36];\nacadoWorkspace.A[3423] = acadoWorkspace.evHu[37];\nacadoWorkspace.A[3490] = acadoWorkspace.evHu[38];\nacadoWorkspace.A[3491] = acadoWorkspace.evHu[39];\nacadoWorkspace.A[3560] = acadoWorkspace.evHu[40];\nacadoWorkspace.A[3561] = acadoWorkspace.evHu[41];\nacadoWorkspace.A[3628] = acadoWorkspace.evHu[42];\nacadoWorkspace.A[3629] = acadoWorkspace.evHu[43];\nacadoWorkspace.A[3698] = acadoWorkspace.evHu[44];\nacadoWorkspace.A[3699] = acadoWorkspace.evHu[45];\nacadoWorkspace.A[3766] = acadoWorkspace.evHu[46];\nacadoWorkspace.A[3767] = acadoWorkspace.evHu[47];\nacadoWorkspace.A[3836] = acadoWorkspace.evHu[48];\nacadoWorkspace.A[3837] = acadoWorkspace.evHu[49];\nacadoWorkspace.A[3904] = acadoWorkspace.evHu[50];\nacadoWorkspace.A[3905] = acadoWorkspace.evHu[51];\nacadoWorkspace.A[3974] = acadoWorkspace.evHu[52];\nacadoWorkspace.A[3975] = acadoWorkspace.evHu[53];\nacadoWorkspace.A[4042] = acadoWorkspace.evHu[54];\nacadoWorkspace.A[4043] = acadoWorkspace.evHu[55];\nacadoWorkspace.A[4112] = acadoWorkspace.evHu[56];\nacadoWorkspace.A[4113] = acadoWorkspace.evHu[57];\nacadoWorkspace.A[4180] = acadoWorkspace.evHu[58];\nacadoWorkspace.A[4181] = acadoWorkspace.evHu[59];\nacadoWorkspace.A[4250] = acadoWorkspace.evHu[60];\nacadoWorkspace.A[4251] = acadoWorkspace.evHu[61];\nacadoWorkspace.A[4318] = acadoWorkspace.evHu[62];\nacadoWorkspace.A[4319] = acadoWorkspace.evHu[63];\nacadoWorkspace.A[4388] = acadoWorkspace.evHu[64];\nacadoWorkspace.A[4389] = acadoWorkspace.evHu[65];\nacadoWorkspace.A[4456] = acadoWorkspace.evHu[66];\nacadoWorkspace.A[4457] = acadoWorkspace.evHu[67];\nacadoWorkspace.A[4526] = acadoWorkspace.evHu[68];\nacadoWorkspace.A[4527] = acadoWorkspace.evHu[69];\nacadoWorkspace.A[4594] = acadoWorkspace.evHu[70];\nacadoWorkspace.A[4595] = acadoWorkspace.evHu[71];\nacadoWorkspace.A[4664] = acadoWorkspace.evHu[72];\nacadoWorkspace.A[4665] = acadoWorkspace.evHu[73];\nacadoWorkspace.A[4732] = acadoWorkspace.evHu[74];\nacadoWorkspace.A[4733] = acadoWorkspace.evHu[75];\nacadoWorkspace.A[4802] = acadoWorkspace.evHu[76];\nacadoWorkspace.A[4803] = acadoWorkspace.evHu[77];\nacadoWorkspace.A[4870] = acadoWorkspace.evHu[78];\nacadoWorkspace.A[4871] = acadoWorkspace.evHu[79];\nacadoWorkspace.A[4940] = acadoWorkspace.evHu[80];\nacadoWorkspace.A[4941] = acadoWorkspace.evHu[81];\nacadoWorkspace.A[5008] = acadoWorkspace.evHu[82];\nacadoWorkspace.A[5009] = acadoWorkspace.evHu[83];\nacadoWorkspace.A[5078] = acadoWorkspace.evHu[84];\nacadoWorkspace.A[5079] = acadoWorkspace.evHu[85];\nacadoWorkspace.A[5146] = acadoWorkspace.evHu[86];\nacadoWorkspace.A[5147] = acadoWorkspace.evHu[87];\nacadoWorkspace.A[5216] = acadoWorkspace.evHu[88];\nacadoWorkspace.A[5217] = acadoWorkspace.evHu[89];\nacadoWorkspace.A[5284] = acadoWorkspace.evHu[90];\nacadoWorkspace.A[5285] = acadoWorkspace.evHu[91];\nacadoWorkspace.A[5354] = acadoWorkspace.evHu[92];\nacadoWorkspace.A[5355] = acadoWorkspace.evHu[93];\nacadoWorkspace.A[5422] = acadoWorkspace.evHu[94];\nacadoWorkspace.A[5423] = acadoWorkspace.evHu[95];\nacadoWorkspace.A[5492] = acadoWorkspace.evHu[96];\nacadoWorkspace.A[5493] = acadoWorkspace.evHu[97];\nacadoWorkspace.A[5560] = acadoWorkspace.evHu[98];\nacadoWorkspace.A[5561] = acadoWorkspace.evHu[99];\nacadoWorkspace.A[5630] = acadoWorkspace.evHu[100];\nacadoWorkspace.A[5631] = acadoWorkspace.evHu[101];\nacadoWorkspace.A[5698] = acadoWorkspace.evHu[102];\nacadoWorkspace.A[5699] = acadoWorkspace.evHu[103];\nacadoWorkspace.A[5768] = acadoWorkspace.evHu[104];\nacadoWorkspace.A[5769] = acadoWorkspace.evHu[105];\nacadoWorkspace.A[5836] = acadoWorkspace.evHu[106];\nacadoWorkspace.A[5837] = acadoWorkspace.evHu[107];\nacadoWorkspace.A[5906] = acadoWorkspace.evHu[108];\nacadoWorkspace.A[5907] = acadoWorkspace.evHu[109];\nacadoWorkspace.A[5974] = acadoWorkspace.evHu[110];\nacadoWorkspace.A[5975] = acadoWorkspace.evHu[111];\nacadoWorkspace.A[6044] = acadoWorkspace.evHu[112];\nacadoWorkspace.A[6045] = acadoWorkspace.evHu[113];\nacadoWorkspace.A[6112] = acadoWorkspace.evHu[114];\nacadoWorkspace.A[6113] = acadoWorkspace.evHu[115];\nacadoWorkspace.A[6182] = acadoWorkspace.evHu[116];\nacadoWorkspace.A[6183] = acadoWorkspace.evHu[117];\nacadoWorkspace.A[6250] = acadoWorkspace.evHu[118];\nacadoWorkspace.A[6251] = acadoWorkspace.evHu[119];\nacadoWorkspace.A[6320] = acadoWorkspace.evHu[120];\nacadoWorkspace.A[6321] = acadoWorkspace.evHu[121];\nacadoWorkspace.A[6388] = acadoWorkspace.evHu[122];\nacadoWorkspace.A[6389] = acadoWorkspace.evHu[123];\nacadoWorkspace.A[6458] = acadoWorkspace.evHu[124];\nacadoWorkspace.A[6459] = acadoWorkspace.evHu[125];\nacadoWorkspace.A[6526] = acadoWorkspace.evHu[126];\nacadoWorkspace.A[6527] = acadoWorkspace.evHu[127];\nacadoWorkspace.lbA[32] = - acadoWorkspace.evH[0];\nacadoWorkspace.lbA[33] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[1];\nacadoWorkspace.lbA[34] = - acadoWorkspace.evH[2];\nacadoWorkspace.lbA[35] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[3];\nacadoWorkspace.lbA[36] = - acadoWorkspace.evH[4];\nacadoWorkspace.lbA[37] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[5];\nacadoWorkspace.lbA[38] = - acadoWorkspace.evH[6];\nacadoWorkspace.lbA[39] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[7];\nacadoWorkspace.lbA[40] = - acadoWorkspace.evH[8];\nacadoWorkspace.lbA[41] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[9];\nacadoWorkspace.lbA[42] = - acadoWorkspace.evH[10];\nacadoWorkspace.lbA[43] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[11];\nacadoWorkspace.lbA[44] = - acadoWorkspace.evH[12];\nacadoWorkspace.lbA[45] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[13];\nacadoWorkspace.lbA[46] = - acadoWorkspace.evH[14];\nacadoWorkspace.lbA[47] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[15];\nacadoWorkspace.lbA[48] = - acadoWorkspace.evH[16];\nacadoWorkspace.lbA[49] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[17];\nacadoWorkspace.lbA[50] = - acadoWorkspace.evH[18];\nacadoWorkspace.lbA[51] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[19];\nacadoWorkspace.lbA[52] = - acadoWorkspace.evH[20];\nacadoWorkspace.lbA[53] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[21];\nacadoWorkspace.lbA[54] = - acadoWorkspace.evH[22];\nacadoWorkspace.lbA[55] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[23];\nacadoWorkspace.lbA[56] = - acadoWorkspace.evH[24];\nacadoWorkspace.lbA[57] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[25];\nacadoWorkspace.lbA[58] = - acadoWorkspace.evH[26];\nacadoWorkspace.lbA[59] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[27];\nacadoWorkspace.lbA[60] = - acadoWorkspace.evH[28];\nacadoWorkspace.lbA[61] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[29];\nacadoWorkspace.lbA[62] = - acadoWorkspace.evH[30];\nacadoWorkspace.lbA[63] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[31];\nacadoWorkspace.lbA[64] = - acadoWorkspace.evH[32];\nacadoWorkspace.lbA[65] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[33];\nacadoWorkspace.lbA[66] = - acadoWorkspace.evH[34];\nacadoWorkspace.lbA[67] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[35];\nacadoWorkspace.lbA[68] = - acadoWorkspace.evH[36];\nacadoWorkspace.lbA[69] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[37];\nacadoWorkspace.lbA[70] = - acadoWorkspace.evH[38];\nacadoWorkspace.lbA[71] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[39];\nacadoWorkspace.lbA[72] = - acadoWorkspace.evH[40];\nacadoWorkspace.lbA[73] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[41];\nacadoWorkspace.lbA[74] = - acadoWorkspace.evH[42];\nacadoWorkspace.lbA[75] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[43];\nacadoWorkspace.lbA[76] = - acadoWorkspace.evH[44];\nacadoWorkspace.lbA[77] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[45];\nacadoWorkspace.lbA[78] = - acadoWorkspace.evH[46];\nacadoWorkspace.lbA[79] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[47];\nacadoWorkspace.lbA[80] = - acadoWorkspace.evH[48];\nacadoWorkspace.lbA[81] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[49];\nacadoWorkspace.lbA[82] = - acadoWorkspace.evH[50];\nacadoWorkspace.lbA[83] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[51];\nacadoWorkspace.lbA[84] = - acadoWorkspace.evH[52];\nacadoWorkspace.lbA[85] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[53];\nacadoWorkspace.lbA[86] = - acadoWorkspace.evH[54];\nacadoWorkspace.lbA[87] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[55];\nacadoWorkspace.lbA[88] = - acadoWorkspace.evH[56];\nacadoWorkspace.lbA[89] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[57];\nacadoWorkspace.lbA[90] = - acadoWorkspace.evH[58];\nacadoWorkspace.lbA[91] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[59];\nacadoWorkspace.lbA[92] = - acadoWorkspace.evH[60];\nacadoWorkspace.lbA[93] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[61];\nacadoWorkspace.lbA[94] = - acadoWorkspace.evH[62];\nacadoWorkspace.lbA[95] = (real_t)-1.0000000000000000e+12 - acadoWorkspace.evH[63];\n\nacadoWorkspace.ubA[32] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[0];\nacadoWorkspace.ubA[33] = - acadoWorkspace.evH[1];\nacadoWorkspace.ubA[34] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[2];\nacadoWorkspace.ubA[35] = - acadoWorkspace.evH[3];\nacadoWorkspace.ubA[36] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[4];\nacadoWorkspace.ubA[37] = - acadoWorkspace.evH[5];\nacadoWorkspace.ubA[38] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[6];\nacadoWorkspace.ubA[39] = - acadoWorkspace.evH[7];\nacadoWorkspace.ubA[40] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[8];\nacadoWorkspace.ubA[41] = - acadoWorkspace.evH[9];\nacadoWorkspace.ubA[42] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[10];\nacadoWorkspace.ubA[43] = - acadoWorkspace.evH[11];\nacadoWorkspace.ubA[44] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[12];\nacadoWorkspace.ubA[45] = - acadoWorkspace.evH[13];\nacadoWorkspace.ubA[46] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[14];\nacadoWorkspace.ubA[47] = - acadoWorkspace.evH[15];\nacadoWorkspace.ubA[48] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[16];\nacadoWorkspace.ubA[49] = - acadoWorkspace.evH[17];\nacadoWorkspace.ubA[50] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[18];\nacadoWorkspace.ubA[51] = - acadoWorkspace.evH[19];\nacadoWorkspace.ubA[52] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[20];\nacadoWorkspace.ubA[53] = - acadoWorkspace.evH[21];\nacadoWorkspace.ubA[54] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[22];\nacadoWorkspace.ubA[55] = - acadoWorkspace.evH[23];\nacadoWorkspace.ubA[56] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[24];\nacadoWorkspace.ubA[57] = - acadoWorkspace.evH[25];\nacadoWorkspace.ubA[58] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[26];\nacadoWorkspace.ubA[59] = - acadoWorkspace.evH[27];\nacadoWorkspace.ubA[60] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[28];\nacadoWorkspace.ubA[61] = - acadoWorkspace.evH[29];\nacadoWorkspace.ubA[62] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[30];\nacadoWorkspace.ubA[63] = - acadoWorkspace.evH[31];\nacadoWorkspace.ubA[64] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[32];\nacadoWorkspace.ubA[65] = - acadoWorkspace.evH[33];\nacadoWorkspace.ubA[66] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[34];\nacadoWorkspace.ubA[67] = - acadoWorkspace.evH[35];\nacadoWorkspace.ubA[68] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[36];\nacadoWorkspace.ubA[69] = - acadoWorkspace.evH[37];\nacadoWorkspace.ubA[70] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[38];\nacadoWorkspace.ubA[71] = - acadoWorkspace.evH[39];\nacadoWorkspace.ubA[72] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[40];\nacadoWorkspace.ubA[73] = - acadoWorkspace.evH[41];\nacadoWorkspace.ubA[74] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[42];\nacadoWorkspace.ubA[75] = - acadoWorkspace.evH[43];\nacadoWorkspace.ubA[76] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[44];\nacadoWorkspace.ubA[77] = - acadoWorkspace.evH[45];\nacadoWorkspace.ubA[78] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[46];\nacadoWorkspace.ubA[79] = - acadoWorkspace.evH[47];\nacadoWorkspace.ubA[80] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[48];\nacadoWorkspace.ubA[81] = - acadoWorkspace.evH[49];\nacadoWorkspace.ubA[82] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[50];\nacadoWorkspace.ubA[83] = - acadoWorkspace.evH[51];\nacadoWorkspace.ubA[84] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[52];\nacadoWorkspace.ubA[85] = - acadoWorkspace.evH[53];\nacadoWorkspace.ubA[86] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[54];\nacadoWorkspace.ubA[87] = - acadoWorkspace.evH[55];\nacadoWorkspace.ubA[88] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[56];\nacadoWorkspace.ubA[89] = - acadoWorkspace.evH[57];\nacadoWorkspace.ubA[90] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[58];\nacadoWorkspace.ubA[91] = - acadoWorkspace.evH[59];\nacadoWorkspace.ubA[92] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[60];\nacadoWorkspace.ubA[93] = - acadoWorkspace.evH[61];\nacadoWorkspace.ubA[94] = (real_t)1.0000000000000000e+12 - acadoWorkspace.evH[62];\nacadoWorkspace.ubA[95] = - acadoWorkspace.evH[63];\n\nacado_macHxd( &(acadoWorkspace.evHx[ 8 ]), acadoWorkspace.d, &(acadoWorkspace.lbA[ 34 ]), &(acadoWorkspace.ubA[ 34 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 16 ]), &(acadoWorkspace.d[ 4 ]), &(acadoWorkspace.lbA[ 36 ]), &(acadoWorkspace.ubA[ 36 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 24 ]), &(acadoWorkspace.d[ 8 ]), &(acadoWorkspace.lbA[ 38 ]), &(acadoWorkspace.ubA[ 38 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 32 ]), &(acadoWorkspace.d[ 12 ]), &(acadoWorkspace.lbA[ 40 ]), &(acadoWorkspace.ubA[ 40 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 40 ]), &(acadoWorkspace.d[ 16 ]), &(acadoWorkspace.lbA[ 42 ]), &(acadoWorkspace.ubA[ 42 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 48 ]), &(acadoWorkspace.d[ 20 ]), &(acadoWorkspace.lbA[ 44 ]), &(acadoWorkspace.ubA[ 44 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 56 ]), &(acadoWorkspace.d[ 24 ]), &(acadoWorkspace.lbA[ 46 ]), &(acadoWorkspace.ubA[ 46 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 64 ]), &(acadoWorkspace.d[ 28 ]), &(acadoWorkspace.lbA[ 48 ]), &(acadoWorkspace.ubA[ 48 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 72 ]), &(acadoWorkspace.d[ 32 ]), &(acadoWorkspace.lbA[ 50 ]), &(acadoWorkspace.ubA[ 50 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 80 ]), &(acadoWorkspace.d[ 36 ]), &(acadoWorkspace.lbA[ 52 ]), &(acadoWorkspace.ubA[ 52 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 88 ]), &(acadoWorkspace.d[ 40 ]), &(acadoWorkspace.lbA[ 54 ]), &(acadoWorkspace.ubA[ 54 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 96 ]), &(acadoWorkspace.d[ 44 ]), &(acadoWorkspace.lbA[ 56 ]), &(acadoWorkspace.ubA[ 56 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 104 ]), &(acadoWorkspace.d[ 48 ]), &(acadoWorkspace.lbA[ 58 ]), &(acadoWorkspace.ubA[ 58 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 112 ]), &(acadoWorkspace.d[ 52 ]), &(acadoWorkspace.lbA[ 60 ]), &(acadoWorkspace.ubA[ 60 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 120 ]), &(acadoWorkspace.d[ 56 ]), &(acadoWorkspace.lbA[ 62 ]), &(acadoWorkspace.ubA[ 62 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 128 ]), &(acadoWorkspace.d[ 60 ]), &(acadoWorkspace.lbA[ 64 ]), &(acadoWorkspace.ubA[ 64 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 136 ]), &(acadoWorkspace.d[ 64 ]), &(acadoWorkspace.lbA[ 66 ]), &(acadoWorkspace.ubA[ 66 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 144 ]), &(acadoWorkspace.d[ 68 ]), &(acadoWorkspace.lbA[ 68 ]), &(acadoWorkspace.ubA[ 68 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 152 ]), &(acadoWorkspace.d[ 72 ]), &(acadoWorkspace.lbA[ 70 ]), &(acadoWorkspace.ubA[ 70 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 160 ]), &(acadoWorkspace.d[ 76 ]), &(acadoWorkspace.lbA[ 72 ]), &(acadoWorkspace.ubA[ 72 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 168 ]), &(acadoWorkspace.d[ 80 ]), &(acadoWorkspace.lbA[ 74 ]), &(acadoWorkspace.ubA[ 74 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 176 ]), &(acadoWorkspace.d[ 84 ]), &(acadoWorkspace.lbA[ 76 ]), &(acadoWorkspace.ubA[ 76 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 184 ]), &(acadoWorkspace.d[ 88 ]), &(acadoWorkspace.lbA[ 78 ]), &(acadoWorkspace.ubA[ 78 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 192 ]), &(acadoWorkspace.d[ 92 ]), &(acadoWorkspace.lbA[ 80 ]), &(acadoWorkspace.ubA[ 80 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 200 ]), &(acadoWorkspace.d[ 96 ]), &(acadoWorkspace.lbA[ 82 ]), &(acadoWorkspace.ubA[ 82 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 208 ]), &(acadoWorkspace.d[ 100 ]), &(acadoWorkspace.lbA[ 84 ]), &(acadoWorkspace.ubA[ 84 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 216 ]), &(acadoWorkspace.d[ 104 ]), &(acadoWorkspace.lbA[ 86 ]), &(acadoWorkspace.ubA[ 86 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 224 ]), &(acadoWorkspace.d[ 108 ]), &(acadoWorkspace.lbA[ 88 ]), &(acadoWorkspace.ubA[ 88 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 232 ]), &(acadoWorkspace.d[ 112 ]), &(acadoWorkspace.lbA[ 90 ]), &(acadoWorkspace.ubA[ 90 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 240 ]), &(acadoWorkspace.d[ 116 ]), &(acadoWorkspace.lbA[ 92 ]), &(acadoWorkspace.ubA[ 92 ]) );\nacado_macHxd( &(acadoWorkspace.evHx[ 248 ]), &(acadoWorkspace.d[ 120 ]), &(acadoWorkspace.lbA[ 94 ]), &(acadoWorkspace.ubA[ 94 ]) );\n\n}\n\nvoid acado_condenseFdb(  )\n{\nint lRun1;\nint lRun2;\nint lRun3;\nreal_t tmp;\n\nacadoWorkspace.Dx0[0] = acadoVariables.x0[0] - acadoVariables.x[0];\nacadoWorkspace.Dx0[1] = acadoVariables.x0[1] - acadoVariables.x[1];\nacadoWorkspace.Dx0[2] = acadoVariables.x0[2] - acadoVariables.x[2];\nacadoWorkspace.Dx0[3] = acadoVariables.x0[3] - acadoVariables.x[3];\n\nfor (lRun2 = 0; lRun2 < 160; ++lRun2)\nacadoWorkspace.Dy[lRun2] -= acadoVariables.y[lRun2];\n\nacadoWorkspace.DyN[0] -= acadoVariables.yN[0];\nacadoWorkspace.DyN[1] -= acadoVariables.yN[1];\nacadoWorkspace.DyN[2] -= acadoVariables.yN[2];\n\nacado_multRDy( acadoWorkspace.R2, acadoWorkspace.Dy, &(acadoWorkspace.g[ 4 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 10 ]), &(acadoWorkspace.Dy[ 5 ]), &(acadoWorkspace.g[ 6 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 20 ]), &(acadoWorkspace.Dy[ 10 ]), &(acadoWorkspace.g[ 8 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 30 ]), &(acadoWorkspace.Dy[ 15 ]), &(acadoWorkspace.g[ 10 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 40 ]), &(acadoWorkspace.Dy[ 20 ]), &(acadoWorkspace.g[ 12 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 50 ]), &(acadoWorkspace.Dy[ 25 ]), &(acadoWorkspace.g[ 14 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 60 ]), &(acadoWorkspace.Dy[ 30 ]), &(acadoWorkspace.g[ 16 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 70 ]), &(acadoWorkspace.Dy[ 35 ]), &(acadoWorkspace.g[ 18 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 80 ]), &(acadoWorkspace.Dy[ 40 ]), &(acadoWorkspace.g[ 20 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 90 ]), &(acadoWorkspace.Dy[ 45 ]), &(acadoWorkspace.g[ 22 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 100 ]), &(acadoWorkspace.Dy[ 50 ]), &(acadoWorkspace.g[ 24 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 110 ]), &(acadoWorkspace.Dy[ 55 ]), &(acadoWorkspace.g[ 26 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 120 ]), &(acadoWorkspace.Dy[ 60 ]), &(acadoWorkspace.g[ 28 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 130 ]), &(acadoWorkspace.Dy[ 65 ]), &(acadoWorkspace.g[ 30 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 140 ]), &(acadoWorkspace.Dy[ 70 ]), &(acadoWorkspace.g[ 32 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 150 ]), &(acadoWorkspace.Dy[ 75 ]), &(acadoWorkspace.g[ 34 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 160 ]), &(acadoWorkspace.Dy[ 80 ]), &(acadoWorkspace.g[ 36 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 170 ]), &(acadoWorkspace.Dy[ 85 ]), &(acadoWorkspace.g[ 38 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 180 ]), &(acadoWorkspace.Dy[ 90 ]), &(acadoWorkspace.g[ 40 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 190 ]), &(acadoWorkspace.Dy[ 95 ]), &(acadoWorkspace.g[ 42 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 200 ]), &(acadoWorkspace.Dy[ 100 ]), &(acadoWorkspace.g[ 44 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 210 ]), &(acadoWorkspace.Dy[ 105 ]), &(acadoWorkspace.g[ 46 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 220 ]), &(acadoWorkspace.Dy[ 110 ]), &(acadoWorkspace.g[ 48 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 230 ]), &(acadoWorkspace.Dy[ 115 ]), &(acadoWorkspace.g[ 50 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 240 ]), &(acadoWorkspace.Dy[ 120 ]), &(acadoWorkspace.g[ 52 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 250 ]), &(acadoWorkspace.Dy[ 125 ]), &(acadoWorkspace.g[ 54 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 260 ]), &(acadoWorkspace.Dy[ 130 ]), &(acadoWorkspace.g[ 56 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 270 ]), &(acadoWorkspace.Dy[ 135 ]), &(acadoWorkspace.g[ 58 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 280 ]), &(acadoWorkspace.Dy[ 140 ]), &(acadoWorkspace.g[ 60 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 290 ]), &(acadoWorkspace.Dy[ 145 ]), &(acadoWorkspace.g[ 62 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 300 ]), &(acadoWorkspace.Dy[ 150 ]), &(acadoWorkspace.g[ 64 ]) );\nacado_multRDy( &(acadoWorkspace.R2[ 310 ]), &(acadoWorkspace.Dy[ 155 ]), &(acadoWorkspace.g[ 66 ]) );\n\nacado_multQDy( acadoWorkspace.Q2, acadoWorkspace.Dy, acadoWorkspace.QDy );\nacado_multQDy( &(acadoWorkspace.Q2[ 20 ]), &(acadoWorkspace.Dy[ 5 ]), &(acadoWorkspace.QDy[ 4 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 40 ]), &(acadoWorkspace.Dy[ 10 ]), &(acadoWorkspace.QDy[ 8 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 60 ]), &(acadoWorkspace.Dy[ 15 ]), &(acadoWorkspace.QDy[ 12 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 80 ]), &(acadoWorkspace.Dy[ 20 ]), &(acadoWorkspace.QDy[ 16 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 100 ]), &(acadoWorkspace.Dy[ 25 ]), &(acadoWorkspace.QDy[ 20 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 120 ]), &(acadoWorkspace.Dy[ 30 ]), &(acadoWorkspace.QDy[ 24 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 140 ]), &(acadoWorkspace.Dy[ 35 ]), &(acadoWorkspace.QDy[ 28 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 160 ]), &(acadoWorkspace.Dy[ 40 ]), &(acadoWorkspace.QDy[ 32 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 180 ]), &(acadoWorkspace.Dy[ 45 ]), &(acadoWorkspace.QDy[ 36 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 200 ]), &(acadoWorkspace.Dy[ 50 ]), &(acadoWorkspace.QDy[ 40 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 220 ]), &(acadoWorkspace.Dy[ 55 ]), &(acadoWorkspace.QDy[ 44 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 240 ]), &(acadoWorkspace.Dy[ 60 ]), &(acadoWorkspace.QDy[ 48 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 260 ]), &(acadoWorkspace.Dy[ 65 ]), &(acadoWorkspace.QDy[ 52 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 280 ]), &(acadoWorkspace.Dy[ 70 ]), &(acadoWorkspace.QDy[ 56 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 300 ]), &(acadoWorkspace.Dy[ 75 ]), &(acadoWorkspace.QDy[ 60 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 320 ]), &(acadoWorkspace.Dy[ 80 ]), &(acadoWorkspace.QDy[ 64 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 340 ]), &(acadoWorkspace.Dy[ 85 ]), &(acadoWorkspace.QDy[ 68 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 360 ]), &(acadoWorkspace.Dy[ 90 ]), &(acadoWorkspace.QDy[ 72 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 380 ]), &(acadoWorkspace.Dy[ 95 ]), &(acadoWorkspace.QDy[ 76 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 400 ]), &(acadoWorkspace.Dy[ 100 ]), &(acadoWorkspace.QDy[ 80 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 420 ]), &(acadoWorkspace.Dy[ 105 ]), &(acadoWorkspace.QDy[ 84 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 440 ]), &(acadoWorkspace.Dy[ 110 ]), &(acadoWorkspace.QDy[ 88 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 460 ]), &(acadoWorkspace.Dy[ 115 ]), &(acadoWorkspace.QDy[ 92 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 480 ]), &(acadoWorkspace.Dy[ 120 ]), &(acadoWorkspace.QDy[ 96 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 500 ]), &(acadoWorkspace.Dy[ 125 ]), &(acadoWorkspace.QDy[ 100 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 520 ]), &(acadoWorkspace.Dy[ 130 ]), &(acadoWorkspace.QDy[ 104 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 540 ]), &(acadoWorkspace.Dy[ 135 ]), &(acadoWorkspace.QDy[ 108 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 560 ]), &(acadoWorkspace.Dy[ 140 ]), &(acadoWorkspace.QDy[ 112 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 580 ]), &(acadoWorkspace.Dy[ 145 ]), &(acadoWorkspace.QDy[ 116 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 600 ]), &(acadoWorkspace.Dy[ 150 ]), &(acadoWorkspace.QDy[ 120 ]) );\nacado_multQDy( &(acadoWorkspace.Q2[ 620 ]), &(acadoWorkspace.Dy[ 155 ]), &(acadoWorkspace.QDy[ 124 ]) );\n\nacadoWorkspace.QDy[128] = + acadoWorkspace.QN2[0]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[1]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[2]*acadoWorkspace.DyN[2];\nacadoWorkspace.QDy[129] = + acadoWorkspace.QN2[3]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[4]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[5]*acadoWorkspace.DyN[2];\nacadoWorkspace.QDy[130] = + acadoWorkspace.QN2[6]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[7]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[8]*acadoWorkspace.DyN[2];\nacadoWorkspace.QDy[131] = + acadoWorkspace.QN2[9]*acadoWorkspace.DyN[0] + acadoWorkspace.QN2[10]*acadoWorkspace.DyN[1] + acadoWorkspace.QN2[11]*acadoWorkspace.DyN[2];\n\nfor (lRun2 = 0; lRun2 < 128; ++lRun2)\nacadoWorkspace.QDy[lRun2 + 4] += acadoWorkspace.Qd[lRun2];\n\n\nacadoWorkspace.g[0] = + acadoWorkspace.evGx[0]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[4]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[8]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[12]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[16]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[20]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[24]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[28]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[32]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[36]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[40]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[44]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[48]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[52]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[56]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[60]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[64]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[68]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[72]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[76]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[80]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[84]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[88]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[92]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[96]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[100]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[104]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[108]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[112]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[116]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[120]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[124]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[128]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[132]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[136]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[140]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[144]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[148]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[152]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[156]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[160]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[164]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[168]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[172]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[176]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[180]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[184]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[188]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[192]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[196]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[200]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[204]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[208]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[212]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[216]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[220]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[224]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[228]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[232]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[236]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[240]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[244]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[248]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[252]*acadoWorkspace.QDy[67] + acadoWorkspace.evGx[256]*acadoWorkspace.QDy[68] + acadoWorkspace.evGx[260]*acadoWorkspace.QDy[69] + acadoWorkspace.evGx[264]*acadoWorkspace.QDy[70] + acadoWorkspace.evGx[268]*acadoWorkspace.QDy[71] + acadoWorkspace.evGx[272]*acadoWorkspace.QDy[72] + acadoWorkspace.evGx[276]*acadoWorkspace.QDy[73] + acadoWorkspace.evGx[280]*acadoWorkspace.QDy[74] + acadoWorkspace.evGx[284]*acadoWorkspace.QDy[75] + acadoWorkspace.evGx[288]*acadoWorkspace.QDy[76] + acadoWorkspace.evGx[292]*acadoWorkspace.QDy[77] + acadoWorkspace.evGx[296]*acadoWorkspace.QDy[78] + acadoWorkspace.evGx[300]*acadoWorkspace.QDy[79] + acadoWorkspace.evGx[304]*acadoWorkspace.QDy[80] + acadoWorkspace.evGx[308]*acadoWorkspace.QDy[81] + acadoWorkspace.evGx[312]*acadoWorkspace.QDy[82] + acadoWorkspace.evGx[316]*acadoWorkspace.QDy[83] + acadoWorkspace.evGx[320]*acadoWorkspace.QDy[84] + acadoWorkspace.evGx[324]*acadoWorkspace.QDy[85] + acadoWorkspace.evGx[328]*acadoWorkspace.QDy[86] + acadoWorkspace.evGx[332]*acadoWorkspace.QDy[87] + acadoWorkspace.evGx[336]*acadoWorkspace.QDy[88] + acadoWorkspace.evGx[340]*acadoWorkspace.QDy[89] + acadoWorkspace.evGx[344]*acadoWorkspace.QDy[90] + acadoWorkspace.evGx[348]*acadoWorkspace.QDy[91] + acadoWorkspace.evGx[352]*acadoWorkspace.QDy[92] + acadoWorkspace.evGx[356]*acadoWorkspace.QDy[93] + acadoWorkspace.evGx[360]*acadoWorkspace.QDy[94] + acadoWorkspace.evGx[364]*acadoWorkspace.QDy[95] + acadoWorkspace.evGx[368]*acadoWorkspace.QDy[96] + acadoWorkspace.evGx[372]*acadoWorkspace.QDy[97] + acadoWorkspace.evGx[376]*acadoWorkspace.QDy[98] + acadoWorkspace.evGx[380]*acadoWorkspace.QDy[99] + acadoWorkspace.evGx[384]*acadoWorkspace.QDy[100] + acadoWorkspace.evGx[388]*acadoWorkspace.QDy[101] + acadoWorkspace.evGx[392]*acadoWorkspace.QDy[102] + acadoWorkspace.evGx[396]*acadoWorkspace.QDy[103] + acadoWorkspace.evGx[400]*acadoWorkspace.QDy[104] + acadoWorkspace.evGx[404]*acadoWorkspace.QDy[105] + acadoWorkspace.evGx[408]*acadoWorkspace.QDy[106] + acadoWorkspace.evGx[412]*acadoWorkspace.QDy[107] + acadoWorkspace.evGx[416]*acadoWorkspace.QDy[108] + acadoWorkspace.evGx[420]*acadoWorkspace.QDy[109] + acadoWorkspace.evGx[424]*acadoWorkspace.QDy[110] + acadoWorkspace.evGx[428]*acadoWorkspace.QDy[111] + acadoWorkspace.evGx[432]*acadoWorkspace.QDy[112] + acadoWorkspace.evGx[436]*acadoWorkspace.QDy[113] + acadoWorkspace.evGx[440]*acadoWorkspace.QDy[114] + acadoWorkspace.evGx[444]*acadoWorkspace.QDy[115] + acadoWorkspace.evGx[448]*acadoWorkspace.QDy[116] + acadoWorkspace.evGx[452]*acadoWorkspace.QDy[117] + acadoWorkspace.evGx[456]*acadoWorkspace.QDy[118] + acadoWorkspace.evGx[460]*acadoWorkspace.QDy[119] + acadoWorkspace.evGx[464]*acadoWorkspace.QDy[120] + acadoWorkspace.evGx[468]*acadoWorkspace.QDy[121] + acadoWorkspace.evGx[472]*acadoWorkspace.QDy[122] + acadoWorkspace.evGx[476]*acadoWorkspace.QDy[123] + acadoWorkspace.evGx[480]*acadoWorkspace.QDy[124] + acadoWorkspace.evGx[484]*acadoWorkspace.QDy[125] + acadoWorkspace.evGx[488]*acadoWorkspace.QDy[126] + acadoWorkspace.evGx[492]*acadoWorkspace.QDy[127] + acadoWorkspace.evGx[496]*acadoWorkspace.QDy[128] + acadoWorkspace.evGx[500]*acadoWorkspace.QDy[129] + acadoWorkspace.evGx[504]*acadoWorkspace.QDy[130] + acadoWorkspace.evGx[508]*acadoWorkspace.QDy[131];\nacadoWorkspace.g[1] = + acadoWorkspace.evGx[1]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[5]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[9]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[13]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[17]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[21]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[25]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[29]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[33]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[37]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[41]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[45]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[49]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[53]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[57]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[61]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[65]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[69]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[73]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[77]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[81]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[85]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[89]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[93]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[97]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[101]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[105]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[109]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[113]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[117]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[121]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[125]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[129]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[133]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[137]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[141]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[145]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[149]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[153]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[157]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[161]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[165]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[169]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[173]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[177]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[181]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[185]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[189]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[193]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[197]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[201]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[205]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[209]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[213]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[217]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[221]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[225]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[229]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[233]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[237]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[241]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[245]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[249]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[253]*acadoWorkspace.QDy[67] + acadoWorkspace.evGx[257]*acadoWorkspace.QDy[68] + acadoWorkspace.evGx[261]*acadoWorkspace.QDy[69] + acadoWorkspace.evGx[265]*acadoWorkspace.QDy[70] + acadoWorkspace.evGx[269]*acadoWorkspace.QDy[71] + acadoWorkspace.evGx[273]*acadoWorkspace.QDy[72] + acadoWorkspace.evGx[277]*acadoWorkspace.QDy[73] + acadoWorkspace.evGx[281]*acadoWorkspace.QDy[74] + acadoWorkspace.evGx[285]*acadoWorkspace.QDy[75] + acadoWorkspace.evGx[289]*acadoWorkspace.QDy[76] + acadoWorkspace.evGx[293]*acadoWorkspace.QDy[77] + acadoWorkspace.evGx[297]*acadoWorkspace.QDy[78] + acadoWorkspace.evGx[301]*acadoWorkspace.QDy[79] + acadoWorkspace.evGx[305]*acadoWorkspace.QDy[80] + acadoWorkspace.evGx[309]*acadoWorkspace.QDy[81] + acadoWorkspace.evGx[313]*acadoWorkspace.QDy[82] + acadoWorkspace.evGx[317]*acadoWorkspace.QDy[83] + acadoWorkspace.evGx[321]*acadoWorkspace.QDy[84] + acadoWorkspace.evGx[325]*acadoWorkspace.QDy[85] + acadoWorkspace.evGx[329]*acadoWorkspace.QDy[86] + acadoWorkspace.evGx[333]*acadoWorkspace.QDy[87] + acadoWorkspace.evGx[337]*acadoWorkspace.QDy[88] + acadoWorkspace.evGx[341]*acadoWorkspace.QDy[89] + acadoWorkspace.evGx[345]*acadoWorkspace.QDy[90] + acadoWorkspace.evGx[349]*acadoWorkspace.QDy[91] + acadoWorkspace.evGx[353]*acadoWorkspace.QDy[92] + acadoWorkspace.evGx[357]*acadoWorkspace.QDy[93] + acadoWorkspace.evGx[361]*acadoWorkspace.QDy[94] + acadoWorkspace.evGx[365]*acadoWorkspace.QDy[95] + acadoWorkspace.evGx[369]*acadoWorkspace.QDy[96] + acadoWorkspace.evGx[373]*acadoWorkspace.QDy[97] + acadoWorkspace.evGx[377]*acadoWorkspace.QDy[98] + acadoWorkspace.evGx[381]*acadoWorkspace.QDy[99] + acadoWorkspace.evGx[385]*acadoWorkspace.QDy[100] + acadoWorkspace.evGx[389]*acadoWorkspace.QDy[101] + acadoWorkspace.evGx[393]*acadoWorkspace.QDy[102] + acadoWorkspace.evGx[397]*acadoWorkspace.QDy[103] + acadoWorkspace.evGx[401]*acadoWorkspace.QDy[104] + acadoWorkspace.evGx[405]*acadoWorkspace.QDy[105] + acadoWorkspace.evGx[409]*acadoWorkspace.QDy[106] + acadoWorkspace.evGx[413]*acadoWorkspace.QDy[107] + acadoWorkspace.evGx[417]*acadoWorkspace.QDy[108] + acadoWorkspace.evGx[421]*acadoWorkspace.QDy[109] + acadoWorkspace.evGx[425]*acadoWorkspace.QDy[110] + acadoWorkspace.evGx[429]*acadoWorkspace.QDy[111] + acadoWorkspace.evGx[433]*acadoWorkspace.QDy[112] + acadoWorkspace.evGx[437]*acadoWorkspace.QDy[113] + acadoWorkspace.evGx[441]*acadoWorkspace.QDy[114] + acadoWorkspace.evGx[445]*acadoWorkspace.QDy[115] + acadoWorkspace.evGx[449]*acadoWorkspace.QDy[116] + acadoWorkspace.evGx[453]*acadoWorkspace.QDy[117] + acadoWorkspace.evGx[457]*acadoWorkspace.QDy[118] + acadoWorkspace.evGx[461]*acadoWorkspace.QDy[119] + acadoWorkspace.evGx[465]*acadoWorkspace.QDy[120] + acadoWorkspace.evGx[469]*acadoWorkspace.QDy[121] + acadoWorkspace.evGx[473]*acadoWorkspace.QDy[122] + acadoWorkspace.evGx[477]*acadoWorkspace.QDy[123] + acadoWorkspace.evGx[481]*acadoWorkspace.QDy[124] + acadoWorkspace.evGx[485]*acadoWorkspace.QDy[125] + acadoWorkspace.evGx[489]*acadoWorkspace.QDy[126] + acadoWorkspace.evGx[493]*acadoWorkspace.QDy[127] + acadoWorkspace.evGx[497]*acadoWorkspace.QDy[128] + acadoWorkspace.evGx[501]*acadoWorkspace.QDy[129] + acadoWorkspace.evGx[505]*acadoWorkspace.QDy[130] + acadoWorkspace.evGx[509]*acadoWorkspace.QDy[131];\nacadoWorkspace.g[2] = + acadoWorkspace.evGx[2]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[6]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[10]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[14]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[18]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[22]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[26]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[30]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[34]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[38]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[42]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[46]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[50]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[54]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[58]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[62]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[66]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[70]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[74]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[78]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[82]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[86]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[90]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[94]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[98]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[102]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[106]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[110]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[114]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[118]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[122]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[126]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[130]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[134]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[138]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[142]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[146]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[150]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[154]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[158]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[162]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[166]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[170]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[174]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[178]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[182]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[186]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[190]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[194]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[198]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[202]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[206]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[210]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[214]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[218]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[222]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[226]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[230]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[234]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[238]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[242]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[246]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[250]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[254]*acadoWorkspace.QDy[67] + acadoWorkspace.evGx[258]*acadoWorkspace.QDy[68] + acadoWorkspace.evGx[262]*acadoWorkspace.QDy[69] + acadoWorkspace.evGx[266]*acadoWorkspace.QDy[70] + acadoWorkspace.evGx[270]*acadoWorkspace.QDy[71] + acadoWorkspace.evGx[274]*acadoWorkspace.QDy[72] + acadoWorkspace.evGx[278]*acadoWorkspace.QDy[73] + acadoWorkspace.evGx[282]*acadoWorkspace.QDy[74] + acadoWorkspace.evGx[286]*acadoWorkspace.QDy[75] + acadoWorkspace.evGx[290]*acadoWorkspace.QDy[76] + acadoWorkspace.evGx[294]*acadoWorkspace.QDy[77] + acadoWorkspace.evGx[298]*acadoWorkspace.QDy[78] + acadoWorkspace.evGx[302]*acadoWorkspace.QDy[79] + acadoWorkspace.evGx[306]*acadoWorkspace.QDy[80] + acadoWorkspace.evGx[310]*acadoWorkspace.QDy[81] + acadoWorkspace.evGx[314]*acadoWorkspace.QDy[82] + acadoWorkspace.evGx[318]*acadoWorkspace.QDy[83] + acadoWorkspace.evGx[322]*acadoWorkspace.QDy[84] + acadoWorkspace.evGx[326]*acadoWorkspace.QDy[85] + acadoWorkspace.evGx[330]*acadoWorkspace.QDy[86] + acadoWorkspace.evGx[334]*acadoWorkspace.QDy[87] + acadoWorkspace.evGx[338]*acadoWorkspace.QDy[88] + acadoWorkspace.evGx[342]*acadoWorkspace.QDy[89] + acadoWorkspace.evGx[346]*acadoWorkspace.QDy[90] + acadoWorkspace.evGx[350]*acadoWorkspace.QDy[91] + acadoWorkspace.evGx[354]*acadoWorkspace.QDy[92] + acadoWorkspace.evGx[358]*acadoWorkspace.QDy[93] + acadoWorkspace.evGx[362]*acadoWorkspace.QDy[94] + acadoWorkspace.evGx[366]*acadoWorkspace.QDy[95] + acadoWorkspace.evGx[370]*acadoWorkspace.QDy[96] + acadoWorkspace.evGx[374]*acadoWorkspace.QDy[97] + acadoWorkspace.evGx[378]*acadoWorkspace.QDy[98] + acadoWorkspace.evGx[382]*acadoWorkspace.QDy[99] + acadoWorkspace.evGx[386]*acadoWorkspace.QDy[100] + acadoWorkspace.evGx[390]*acadoWorkspace.QDy[101] + acadoWorkspace.evGx[394]*acadoWorkspace.QDy[102] + acadoWorkspace.evGx[398]*acadoWorkspace.QDy[103] + acadoWorkspace.evGx[402]*acadoWorkspace.QDy[104] + acadoWorkspace.evGx[406]*acadoWorkspace.QDy[105] + acadoWorkspace.evGx[410]*acadoWorkspace.QDy[106] + acadoWorkspace.evGx[414]*acadoWorkspace.QDy[107] + acadoWorkspace.evGx[418]*acadoWorkspace.QDy[108] + acadoWorkspace.evGx[422]*acadoWorkspace.QDy[109] + acadoWorkspace.evGx[426]*acadoWorkspace.QDy[110] + acadoWorkspace.evGx[430]*acadoWorkspace.QDy[111] + acadoWorkspace.evGx[434]*acadoWorkspace.QDy[112] + acadoWorkspace.evGx[438]*acadoWorkspace.QDy[113] + acadoWorkspace.evGx[442]*acadoWorkspace.QDy[114] + acadoWorkspace.evGx[446]*acadoWorkspace.QDy[115] + acadoWorkspace.evGx[450]*acadoWorkspace.QDy[116] + acadoWorkspace.evGx[454]*acadoWorkspace.QDy[117] + acadoWorkspace.evGx[458]*acadoWorkspace.QDy[118] + acadoWorkspace.evGx[462]*acadoWorkspace.QDy[119] + acadoWorkspace.evGx[466]*acadoWorkspace.QDy[120] + acadoWorkspace.evGx[470]*acadoWorkspace.QDy[121] + acadoWorkspace.evGx[474]*acadoWorkspace.QDy[122] + acadoWorkspace.evGx[478]*acadoWorkspace.QDy[123] + acadoWorkspace.evGx[482]*acadoWorkspace.QDy[124] + acadoWorkspace.evGx[486]*acadoWorkspace.QDy[125] + acadoWorkspace.evGx[490]*acadoWorkspace.QDy[126] + acadoWorkspace.evGx[494]*acadoWorkspace.QDy[127] + acadoWorkspace.evGx[498]*acadoWorkspace.QDy[128] + acadoWorkspace.evGx[502]*acadoWorkspace.QDy[129] + acadoWorkspace.evGx[506]*acadoWorkspace.QDy[130] + acadoWorkspace.evGx[510]*acadoWorkspace.QDy[131];\nacadoWorkspace.g[3] = + acadoWorkspace.evGx[3]*acadoWorkspace.QDy[4] + acadoWorkspace.evGx[7]*acadoWorkspace.QDy[5] + acadoWorkspace.evGx[11]*acadoWorkspace.QDy[6] + acadoWorkspace.evGx[15]*acadoWorkspace.QDy[7] + acadoWorkspace.evGx[19]*acadoWorkspace.QDy[8] + acadoWorkspace.evGx[23]*acadoWorkspace.QDy[9] + acadoWorkspace.evGx[27]*acadoWorkspace.QDy[10] + acadoWorkspace.evGx[31]*acadoWorkspace.QDy[11] + acadoWorkspace.evGx[35]*acadoWorkspace.QDy[12] + acadoWorkspace.evGx[39]*acadoWorkspace.QDy[13] + acadoWorkspace.evGx[43]*acadoWorkspace.QDy[14] + acadoWorkspace.evGx[47]*acadoWorkspace.QDy[15] + acadoWorkspace.evGx[51]*acadoWorkspace.QDy[16] + acadoWorkspace.evGx[55]*acadoWorkspace.QDy[17] + acadoWorkspace.evGx[59]*acadoWorkspace.QDy[18] + acadoWorkspace.evGx[63]*acadoWorkspace.QDy[19] + acadoWorkspace.evGx[67]*acadoWorkspace.QDy[20] + acadoWorkspace.evGx[71]*acadoWorkspace.QDy[21] + acadoWorkspace.evGx[75]*acadoWorkspace.QDy[22] + acadoWorkspace.evGx[79]*acadoWorkspace.QDy[23] + acadoWorkspace.evGx[83]*acadoWorkspace.QDy[24] + acadoWorkspace.evGx[87]*acadoWorkspace.QDy[25] + acadoWorkspace.evGx[91]*acadoWorkspace.QDy[26] + acadoWorkspace.evGx[95]*acadoWorkspace.QDy[27] + acadoWorkspace.evGx[99]*acadoWorkspace.QDy[28] + acadoWorkspace.evGx[103]*acadoWorkspace.QDy[29] + acadoWorkspace.evGx[107]*acadoWorkspace.QDy[30] + acadoWorkspace.evGx[111]*acadoWorkspace.QDy[31] + acadoWorkspace.evGx[115]*acadoWorkspace.QDy[32] + acadoWorkspace.evGx[119]*acadoWorkspace.QDy[33] + acadoWorkspace.evGx[123]*acadoWorkspace.QDy[34] + acadoWorkspace.evGx[127]*acadoWorkspace.QDy[35] + acadoWorkspace.evGx[131]*acadoWorkspace.QDy[36] + acadoWorkspace.evGx[135]*acadoWorkspace.QDy[37] + acadoWorkspace.evGx[139]*acadoWorkspace.QDy[38] + acadoWorkspace.evGx[143]*acadoWorkspace.QDy[39] + acadoWorkspace.evGx[147]*acadoWorkspace.QDy[40] + acadoWorkspace.evGx[151]*acadoWorkspace.QDy[41] + acadoWorkspace.evGx[155]*acadoWorkspace.QDy[42] + acadoWorkspace.evGx[159]*acadoWorkspace.QDy[43] + acadoWorkspace.evGx[163]*acadoWorkspace.QDy[44] + acadoWorkspace.evGx[167]*acadoWorkspace.QDy[45] + acadoWorkspace.evGx[171]*acadoWorkspace.QDy[46] + acadoWorkspace.evGx[175]*acadoWorkspace.QDy[47] + acadoWorkspace.evGx[179]*acadoWorkspace.QDy[48] + acadoWorkspace.evGx[183]*acadoWorkspace.QDy[49] + acadoWorkspace.evGx[187]*acadoWorkspace.QDy[50] + acadoWorkspace.evGx[191]*acadoWorkspace.QDy[51] + acadoWorkspace.evGx[195]*acadoWorkspace.QDy[52] + acadoWorkspace.evGx[199]*acadoWorkspace.QDy[53] + acadoWorkspace.evGx[203]*acadoWorkspace.QDy[54] + acadoWorkspace.evGx[207]*acadoWorkspace.QDy[55] + acadoWorkspace.evGx[211]*acadoWorkspace.QDy[56] + acadoWorkspace.evGx[215]*acadoWorkspace.QDy[57] + acadoWorkspace.evGx[219]*acadoWorkspace.QDy[58] + acadoWorkspace.evGx[223]*acadoWorkspace.QDy[59] + acadoWorkspace.evGx[227]*acadoWorkspace.QDy[60] + acadoWorkspace.evGx[231]*acadoWorkspace.QDy[61] + acadoWorkspace.evGx[235]*acadoWorkspace.QDy[62] + acadoWorkspace.evGx[239]*acadoWorkspace.QDy[63] + acadoWorkspace.evGx[243]*acadoWorkspace.QDy[64] + acadoWorkspace.evGx[247]*acadoWorkspace.QDy[65] + acadoWorkspace.evGx[251]*acadoWorkspace.QDy[66] + acadoWorkspace.evGx[255]*acadoWorkspace.QDy[67] + acadoWorkspace.evGx[259]*acadoWorkspace.QDy[68] + acadoWorkspace.evGx[263]*acadoWorkspace.QDy[69] + acadoWorkspace.evGx[267]*acadoWorkspace.QDy[70] + acadoWorkspace.evGx[271]*acadoWorkspace.QDy[71] + acadoWorkspace.evGx[275]*acadoWorkspace.QDy[72] + acadoWorkspace.evGx[279]*acadoWorkspace.QDy[73] + acadoWorkspace.evGx[283]*acadoWorkspace.QDy[74] + acadoWorkspace.evGx[287]*acadoWorkspace.QDy[75] + acadoWorkspace.evGx[291]*acadoWorkspace.QDy[76] + acadoWorkspace.evGx[295]*acadoWorkspace.QDy[77] + acadoWorkspace.evGx[299]*acadoWorkspace.QDy[78] + acadoWorkspace.evGx[303]*acadoWorkspace.QDy[79] + acadoWorkspace.evGx[307]*acadoWorkspace.QDy[80] + acadoWorkspace.evGx[311]*acadoWorkspace.QDy[81] + acadoWorkspace.evGx[315]*acadoWorkspace.QDy[82] + acadoWorkspace.evGx[319]*acadoWorkspace.QDy[83] + acadoWorkspace.evGx[323]*acadoWorkspace.QDy[84] + acadoWorkspace.evGx[327]*acadoWorkspace.QDy[85] + acadoWorkspace.evGx[331]*acadoWorkspace.QDy[86] + acadoWorkspace.evGx[335]*acadoWorkspace.QDy[87] + acadoWorkspace.evGx[339]*acadoWorkspace.QDy[88] + acadoWorkspace.evGx[343]*acadoWorkspace.QDy[89] + acadoWorkspace.evGx[347]*acadoWorkspace.QDy[90] + acadoWorkspace.evGx[351]*acadoWorkspace.QDy[91] + acadoWorkspace.evGx[355]*acadoWorkspace.QDy[92] + acadoWorkspace.evGx[359]*acadoWorkspace.QDy[93] + acadoWorkspace.evGx[363]*acadoWorkspace.QDy[94] + acadoWorkspace.evGx[367]*acadoWorkspace.QDy[95] + acadoWorkspace.evGx[371]*acadoWorkspace.QDy[96] + acadoWorkspace.evGx[375]*acadoWorkspace.QDy[97] + acadoWorkspace.evGx[379]*acadoWorkspace.QDy[98] + acadoWorkspace.evGx[383]*acadoWorkspace.QDy[99] + acadoWorkspace.evGx[387]*acadoWorkspace.QDy[100] + acadoWorkspace.evGx[391]*acadoWorkspace.QDy[101] + acadoWorkspace.evGx[395]*acadoWorkspace.QDy[102] + acadoWorkspace.evGx[399]*acadoWorkspace.QDy[103] + acadoWorkspace.evGx[403]*acadoWorkspace.QDy[104] + acadoWorkspace.evGx[407]*acadoWorkspace.QDy[105] + acadoWorkspace.evGx[411]*acadoWorkspace.QDy[106] + acadoWorkspace.evGx[415]*acadoWorkspace.QDy[107] + acadoWorkspace.evGx[419]*acadoWorkspace.QDy[108] + acadoWorkspace.evGx[423]*acadoWorkspace.QDy[109] + acadoWorkspace.evGx[427]*acadoWorkspace.QDy[110] + acadoWorkspace.evGx[431]*acadoWorkspace.QDy[111] + acadoWorkspace.evGx[435]*acadoWorkspace.QDy[112] + acadoWorkspace.evGx[439]*acadoWorkspace.QDy[113] + acadoWorkspace.evGx[443]*acadoWorkspace.QDy[114] + acadoWorkspace.evGx[447]*acadoWorkspace.QDy[115] + acadoWorkspace.evGx[451]*acadoWorkspace.QDy[116] + acadoWorkspace.evGx[455]*acadoWorkspace.QDy[117] + acadoWorkspace.evGx[459]*acadoWorkspace.QDy[118] + acadoWorkspace.evGx[463]*acadoWorkspace.QDy[119] + acadoWorkspace.evGx[467]*acadoWorkspace.QDy[120] + acadoWorkspace.evGx[471]*acadoWorkspace.QDy[121] + acadoWorkspace.evGx[475]*acadoWorkspace.QDy[122] + acadoWorkspace.evGx[479]*acadoWorkspace.QDy[123] + acadoWorkspace.evGx[483]*acadoWorkspace.QDy[124] + acadoWorkspace.evGx[487]*acadoWorkspace.QDy[125] + acadoWorkspace.evGx[491]*acadoWorkspace.QDy[126] + acadoWorkspace.evGx[495]*acadoWorkspace.QDy[127] + acadoWorkspace.evGx[499]*acadoWorkspace.QDy[128] + acadoWorkspace.evGx[503]*acadoWorkspace.QDy[129] + acadoWorkspace.evGx[507]*acadoWorkspace.QDy[130] + acadoWorkspace.evGx[511]*acadoWorkspace.QDy[131];\n\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nfor (lRun2 = lRun1; lRun2 < 32; ++lRun2)\n{\nlRun3 = (((lRun2 + 1) * (lRun2)) / (2)) + (lRun1);\nacado_multEQDy( &(acadoWorkspace.E[ lRun3 * 8 ]), &(acadoWorkspace.QDy[ lRun2 * 4 + 4 ]), &(acadoWorkspace.g[ lRun1 * 2 + 4 ]) );\n}\n}\n\nacadoWorkspace.lb[0] = acadoWorkspace.Dx0[0];\nacadoWorkspace.lb[1] = acadoWorkspace.Dx0[1];\nacadoWorkspace.lb[2] = acadoWorkspace.Dx0[2];\nacadoWorkspace.lb[3] = acadoWorkspace.Dx0[3];\nacadoWorkspace.ub[0] = acadoWorkspace.Dx0[0];\nacadoWorkspace.ub[1] = acadoWorkspace.Dx0[1];\nacadoWorkspace.ub[2] = acadoWorkspace.Dx0[2];\nacadoWorkspace.ub[3] = acadoWorkspace.Dx0[3];\ntmp = acadoVariables.x[5] + acadoWorkspace.d[1];\nacadoWorkspace.lbA[0] = - tmp;\nacadoWorkspace.ubA[0] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[9] + acadoWorkspace.d[5];\nacadoWorkspace.lbA[1] = - tmp;\nacadoWorkspace.ubA[1] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[13] + acadoWorkspace.d[9];\nacadoWorkspace.lbA[2] = - tmp;\nacadoWorkspace.ubA[2] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[17] + acadoWorkspace.d[13];\nacadoWorkspace.lbA[3] = - tmp;\nacadoWorkspace.ubA[3] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[21] + acadoWorkspace.d[17];\nacadoWorkspace.lbA[4] = - tmp;\nacadoWorkspace.ubA[4] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[25] + acadoWorkspace.d[21];\nacadoWorkspace.lbA[5] = - tmp;\nacadoWorkspace.ubA[5] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[29] + acadoWorkspace.d[25];\nacadoWorkspace.lbA[6] = - tmp;\nacadoWorkspace.ubA[6] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[33] + acadoWorkspace.d[29];\nacadoWorkspace.lbA[7] = - tmp;\nacadoWorkspace.ubA[7] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[37] + acadoWorkspace.d[33];\nacadoWorkspace.lbA[8] = - tmp;\nacadoWorkspace.ubA[8] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[41] + acadoWorkspace.d[37];\nacadoWorkspace.lbA[9] = - tmp;\nacadoWorkspace.ubA[9] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[45] + acadoWorkspace.d[41];\nacadoWorkspace.lbA[10] = - tmp;\nacadoWorkspace.ubA[10] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[49] + acadoWorkspace.d[45];\nacadoWorkspace.lbA[11] = - tmp;\nacadoWorkspace.ubA[11] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[53] + acadoWorkspace.d[49];\nacadoWorkspace.lbA[12] = - tmp;\nacadoWorkspace.ubA[12] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[57] + acadoWorkspace.d[53];\nacadoWorkspace.lbA[13] = - tmp;\nacadoWorkspace.ubA[13] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[61] + acadoWorkspace.d[57];\nacadoWorkspace.lbA[14] = - tmp;\nacadoWorkspace.ubA[14] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[65] + acadoWorkspace.d[61];\nacadoWorkspace.lbA[15] = - tmp;\nacadoWorkspace.ubA[15] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[69] + acadoWorkspace.d[65];\nacadoWorkspace.lbA[16] = - tmp;\nacadoWorkspace.ubA[16] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[73] + acadoWorkspace.d[69];\nacadoWorkspace.lbA[17] = - tmp;\nacadoWorkspace.ubA[17] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[77] + acadoWorkspace.d[73];\nacadoWorkspace.lbA[18] = - tmp;\nacadoWorkspace.ubA[18] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[81] + acadoWorkspace.d[77];\nacadoWorkspace.lbA[19] = - tmp;\nacadoWorkspace.ubA[19] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[85] + acadoWorkspace.d[81];\nacadoWorkspace.lbA[20] = - tmp;\nacadoWorkspace.ubA[20] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[89] + acadoWorkspace.d[85];\nacadoWorkspace.lbA[21] = - tmp;\nacadoWorkspace.ubA[21] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[93] + acadoWorkspace.d[89];\nacadoWorkspace.lbA[22] = - tmp;\nacadoWorkspace.ubA[22] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[97] + acadoWorkspace.d[93];\nacadoWorkspace.lbA[23] = - tmp;\nacadoWorkspace.ubA[23] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[101] + acadoWorkspace.d[97];\nacadoWorkspace.lbA[24] = - tmp;\nacadoWorkspace.ubA[24] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[105] + acadoWorkspace.d[101];\nacadoWorkspace.lbA[25] = - tmp;\nacadoWorkspace.ubA[25] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[109] + acadoWorkspace.d[105];\nacadoWorkspace.lbA[26] = - tmp;\nacadoWorkspace.ubA[26] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[113] + acadoWorkspace.d[109];\nacadoWorkspace.lbA[27] = - tmp;\nacadoWorkspace.ubA[27] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[117] + acadoWorkspace.d[113];\nacadoWorkspace.lbA[28] = - tmp;\nacadoWorkspace.ubA[28] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[121] + acadoWorkspace.d[117];\nacadoWorkspace.lbA[29] = - tmp;\nacadoWorkspace.ubA[29] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[125] + acadoWorkspace.d[121];\nacadoWorkspace.lbA[30] = - tmp;\nacadoWorkspace.ubA[30] = (real_t)1.0000000000000000e+12 - tmp;\ntmp = acadoVariables.x[129] + acadoWorkspace.d[125];\nacadoWorkspace.lbA[31] = - tmp;\nacadoWorkspace.ubA[31] = (real_t)1.0000000000000000e+12 - tmp;\n\n}\n\nvoid acado_expand(  )\n{\nint lRun1;\nint lRun2;\nint lRun3;\nacadoVariables.x[0] += acadoWorkspace.x[0];\nacadoVariables.x[1] += acadoWorkspace.x[1];\nacadoVariables.x[2] += acadoWorkspace.x[2];\nacadoVariables.x[3] += acadoWorkspace.x[3];\n\nacadoVariables.u[0] += acadoWorkspace.x[4];\nacadoVariables.u[1] += acadoWorkspace.x[5];\nacadoVariables.u[2] += acadoWorkspace.x[6];\nacadoVariables.u[3] += acadoWorkspace.x[7];\nacadoVariables.u[4] += acadoWorkspace.x[8];\nacadoVariables.u[5] += acadoWorkspace.x[9];\nacadoVariables.u[6] += acadoWorkspace.x[10];\nacadoVariables.u[7] += acadoWorkspace.x[11];\nacadoVariables.u[8] += acadoWorkspace.x[12];\nacadoVariables.u[9] += acadoWorkspace.x[13];\nacadoVariables.u[10] += acadoWorkspace.x[14];\nacadoVariables.u[11] += acadoWorkspace.x[15];\nacadoVariables.u[12] += acadoWorkspace.x[16];\nacadoVariables.u[13] += acadoWorkspace.x[17];\nacadoVariables.u[14] += acadoWorkspace.x[18];\nacadoVariables.u[15] += acadoWorkspace.x[19];\nacadoVariables.u[16] += acadoWorkspace.x[20];\nacadoVariables.u[17] += acadoWorkspace.x[21];\nacadoVariables.u[18] += acadoWorkspace.x[22];\nacadoVariables.u[19] += acadoWorkspace.x[23];\nacadoVariables.u[20] += acadoWorkspace.x[24];\nacadoVariables.u[21] += acadoWorkspace.x[25];\nacadoVariables.u[22] += acadoWorkspace.x[26];\nacadoVariables.u[23] += acadoWorkspace.x[27];\nacadoVariables.u[24] += acadoWorkspace.x[28];\nacadoVariables.u[25] += acadoWorkspace.x[29];\nacadoVariables.u[26] += acadoWorkspace.x[30];\nacadoVariables.u[27] += acadoWorkspace.x[31];\nacadoVariables.u[28] += acadoWorkspace.x[32];\nacadoVariables.u[29] += acadoWorkspace.x[33];\nacadoVariables.u[30] += acadoWorkspace.x[34];\nacadoVariables.u[31] += acadoWorkspace.x[35];\nacadoVariables.u[32] += acadoWorkspace.x[36];\nacadoVariables.u[33] += acadoWorkspace.x[37];\nacadoVariables.u[34] += acadoWorkspace.x[38];\nacadoVariables.u[35] += acadoWorkspace.x[39];\nacadoVariables.u[36] += acadoWorkspace.x[40];\nacadoVariables.u[37] += acadoWorkspace.x[41];\nacadoVariables.u[38] += acadoWorkspace.x[42];\nacadoVariables.u[39] += acadoWorkspace.x[43];\nacadoVariables.u[40] += acadoWorkspace.x[44];\nacadoVariables.u[41] += acadoWorkspace.x[45];\nacadoVariables.u[42] += acadoWorkspace.x[46];\nacadoVariables.u[43] += acadoWorkspace.x[47];\nacadoVariables.u[44] += acadoWorkspace.x[48];\nacadoVariables.u[45] += acadoWorkspace.x[49];\nacadoVariables.u[46] += acadoWorkspace.x[50];\nacadoVariables.u[47] += acadoWorkspace.x[51];\nacadoVariables.u[48] += acadoWorkspace.x[52];\nacadoVariables.u[49] += acadoWorkspace.x[53];\nacadoVariables.u[50] += acadoWorkspace.x[54];\nacadoVariables.u[51] += acadoWorkspace.x[55];\nacadoVariables.u[52] += acadoWorkspace.x[56];\nacadoVariables.u[53] += acadoWorkspace.x[57];\nacadoVariables.u[54] += acadoWorkspace.x[58];\nacadoVariables.u[55] += acadoWorkspace.x[59];\nacadoVariables.u[56] += acadoWorkspace.x[60];\nacadoVariables.u[57] += acadoWorkspace.x[61];\nacadoVariables.u[58] += acadoWorkspace.x[62];\nacadoVariables.u[59] += acadoWorkspace.x[63];\nacadoVariables.u[60] += acadoWorkspace.x[64];\nacadoVariables.u[61] += acadoWorkspace.x[65];\nacadoVariables.u[62] += acadoWorkspace.x[66];\nacadoVariables.u[63] += acadoWorkspace.x[67];\n\nacadoVariables.x[4] += + acadoWorkspace.evGx[0]*acadoWorkspace.x[0] + acadoWorkspace.evGx[1]*acadoWorkspace.x[1] + acadoWorkspace.evGx[2]*acadoWorkspace.x[2] + acadoWorkspace.evGx[3]*acadoWorkspace.x[3] + acadoWorkspace.d[0];\nacadoVariables.x[5] += + acadoWorkspace.evGx[4]*acadoWorkspace.x[0] + acadoWorkspace.evGx[5]*acadoWorkspace.x[1] + acadoWorkspace.evGx[6]*acadoWorkspace.x[2] + acadoWorkspace.evGx[7]*acadoWorkspace.x[3] + acadoWorkspace.d[1];\nacadoVariables.x[6] += + acadoWorkspace.evGx[8]*acadoWorkspace.x[0] + acadoWorkspace.evGx[9]*acadoWorkspace.x[1] + acadoWorkspace.evGx[10]*acadoWorkspace.x[2] + acadoWorkspace.evGx[11]*acadoWorkspace.x[3] + acadoWorkspace.d[2];\nacadoVariables.x[7] += + acadoWorkspace.evGx[12]*acadoWorkspace.x[0] + acadoWorkspace.evGx[13]*acadoWorkspace.x[1] + acadoWorkspace.evGx[14]*acadoWorkspace.x[2] + acadoWorkspace.evGx[15]*acadoWorkspace.x[3] + acadoWorkspace.d[3];\nacadoVariables.x[8] += + acadoWorkspace.evGx[16]*acadoWorkspace.x[0] + acadoWorkspace.evGx[17]*acadoWorkspace.x[1] + acadoWorkspace.evGx[18]*acadoWorkspace.x[2] + acadoWorkspace.evGx[19]*acadoWorkspace.x[3] + acadoWorkspace.d[4];\nacadoVariables.x[9] += + acadoWorkspace.evGx[20]*acadoWorkspace.x[0] + acadoWorkspace.evGx[21]*acadoWorkspace.x[1] + acadoWorkspace.evGx[22]*acadoWorkspace.x[2] + acadoWorkspace.evGx[23]*acadoWorkspace.x[3] + acadoWorkspace.d[5];\nacadoVariables.x[10] += + acadoWorkspace.evGx[24]*acadoWorkspace.x[0] + acadoWorkspace.evGx[25]*acadoWorkspace.x[1] + acadoWorkspace.evGx[26]*acadoWorkspace.x[2] + acadoWorkspace.evGx[27]*acadoWorkspace.x[3] + acadoWorkspace.d[6];\nacadoVariables.x[11] += + acadoWorkspace.evGx[28]*acadoWorkspace.x[0] + acadoWorkspace.evGx[29]*acadoWorkspace.x[1] + acadoWorkspace.evGx[30]*acadoWorkspace.x[2] + acadoWorkspace.evGx[31]*acadoWorkspace.x[3] + acadoWorkspace.d[7];\nacadoVariables.x[12] += + acadoWorkspace.evGx[32]*acadoWorkspace.x[0] + acadoWorkspace.evGx[33]*acadoWorkspace.x[1] + acadoWorkspace.evGx[34]*acadoWorkspace.x[2] + acadoWorkspace.evGx[35]*acadoWorkspace.x[3] + acadoWorkspace.d[8];\nacadoVariables.x[13] += + acadoWorkspace.evGx[36]*acadoWorkspace.x[0] + acadoWorkspace.evGx[37]*acadoWorkspace.x[1] + acadoWorkspace.evGx[38]*acadoWorkspace.x[2] + acadoWorkspace.evGx[39]*acadoWorkspace.x[3] + acadoWorkspace.d[9];\nacadoVariables.x[14] += + acadoWorkspace.evGx[40]*acadoWorkspace.x[0] + acadoWorkspace.evGx[41]*acadoWorkspace.x[1] + acadoWorkspace.evGx[42]*acadoWorkspace.x[2] + acadoWorkspace.evGx[43]*acadoWorkspace.x[3] + acadoWorkspace.d[10];\nacadoVariables.x[15] += + acadoWorkspace.evGx[44]*acadoWorkspace.x[0] + acadoWorkspace.evGx[45]*acadoWorkspace.x[1] + acadoWorkspace.evGx[46]*acadoWorkspace.x[2] + acadoWorkspace.evGx[47]*acadoWorkspace.x[3] + acadoWorkspace.d[11];\nacadoVariables.x[16] += + acadoWorkspace.evGx[48]*acadoWorkspace.x[0] + acadoWorkspace.evGx[49]*acadoWorkspace.x[1] + acadoWorkspace.evGx[50]*acadoWorkspace.x[2] + acadoWorkspace.evGx[51]*acadoWorkspace.x[3] + acadoWorkspace.d[12];\nacadoVariables.x[17] += + acadoWorkspace.evGx[52]*acadoWorkspace.x[0] + acadoWorkspace.evGx[53]*acadoWorkspace.x[1] + acadoWorkspace.evGx[54]*acadoWorkspace.x[2] + acadoWorkspace.evGx[55]*acadoWorkspace.x[3] + acadoWorkspace.d[13];\nacadoVariables.x[18] += + acadoWorkspace.evGx[56]*acadoWorkspace.x[0] + acadoWorkspace.evGx[57]*acadoWorkspace.x[1] + acadoWorkspace.evGx[58]*acadoWorkspace.x[2] + acadoWorkspace.evGx[59]*acadoWorkspace.x[3] + acadoWorkspace.d[14];\nacadoVariables.x[19] += + acadoWorkspace.evGx[60]*acadoWorkspace.x[0] + acadoWorkspace.evGx[61]*acadoWorkspace.x[1] + acadoWorkspace.evGx[62]*acadoWorkspace.x[2] + acadoWorkspace.evGx[63]*acadoWorkspace.x[3] + acadoWorkspace.d[15];\nacadoVariables.x[20] += + acadoWorkspace.evGx[64]*acadoWorkspace.x[0] + acadoWorkspace.evGx[65]*acadoWorkspace.x[1] + acadoWorkspace.evGx[66]*acadoWorkspace.x[2] + acadoWorkspace.evGx[67]*acadoWorkspace.x[3] + acadoWorkspace.d[16];\nacadoVariables.x[21] += + acadoWorkspace.evGx[68]*acadoWorkspace.x[0] + acadoWorkspace.evGx[69]*acadoWorkspace.x[1] + acadoWorkspace.evGx[70]*acadoWorkspace.x[2] + acadoWorkspace.evGx[71]*acadoWorkspace.x[3] + acadoWorkspace.d[17];\nacadoVariables.x[22] += + acadoWorkspace.evGx[72]*acadoWorkspace.x[0] + acadoWorkspace.evGx[73]*acadoWorkspace.x[1] + acadoWorkspace.evGx[74]*acadoWorkspace.x[2] + acadoWorkspace.evGx[75]*acadoWorkspace.x[3] + acadoWorkspace.d[18];\nacadoVariables.x[23] += + acadoWorkspace.evGx[76]*acadoWorkspace.x[0] + acadoWorkspace.evGx[77]*acadoWorkspace.x[1] + acadoWorkspace.evGx[78]*acadoWorkspace.x[2] + acadoWorkspace.evGx[79]*acadoWorkspace.x[3] + acadoWorkspace.d[19];\nacadoVariables.x[24] += + acadoWorkspace.evGx[80]*acadoWorkspace.x[0] + acadoWorkspace.evGx[81]*acadoWorkspace.x[1] + acadoWorkspace.evGx[82]*acadoWorkspace.x[2] + acadoWorkspace.evGx[83]*acadoWorkspace.x[3] + acadoWorkspace.d[20];\nacadoVariables.x[25] += + acadoWorkspace.evGx[84]*acadoWorkspace.x[0] + acadoWorkspace.evGx[85]*acadoWorkspace.x[1] + acadoWorkspace.evGx[86]*acadoWorkspace.x[2] + acadoWorkspace.evGx[87]*acadoWorkspace.x[3] + acadoWorkspace.d[21];\nacadoVariables.x[26] += + acadoWorkspace.evGx[88]*acadoWorkspace.x[0] + acadoWorkspace.evGx[89]*acadoWorkspace.x[1] + acadoWorkspace.evGx[90]*acadoWorkspace.x[2] + acadoWorkspace.evGx[91]*acadoWorkspace.x[3] + acadoWorkspace.d[22];\nacadoVariables.x[27] += + acadoWorkspace.evGx[92]*acadoWorkspace.x[0] + acadoWorkspace.evGx[93]*acadoWorkspace.x[1] + acadoWorkspace.evGx[94]*acadoWorkspace.x[2] + acadoWorkspace.evGx[95]*acadoWorkspace.x[3] + acadoWorkspace.d[23];\nacadoVariables.x[28] += + acadoWorkspace.evGx[96]*acadoWorkspace.x[0] + acadoWorkspace.evGx[97]*acadoWorkspace.x[1] + acadoWorkspace.evGx[98]*acadoWorkspace.x[2] + acadoWorkspace.evGx[99]*acadoWorkspace.x[3] + acadoWorkspace.d[24];\nacadoVariables.x[29] += + acadoWorkspace.evGx[100]*acadoWorkspace.x[0] + acadoWorkspace.evGx[101]*acadoWorkspace.x[1] + acadoWorkspace.evGx[102]*acadoWorkspace.x[2] + acadoWorkspace.evGx[103]*acadoWorkspace.x[3] + acadoWorkspace.d[25];\nacadoVariables.x[30] += + acadoWorkspace.evGx[104]*acadoWorkspace.x[0] + acadoWorkspace.evGx[105]*acadoWorkspace.x[1] + acadoWorkspace.evGx[106]*acadoWorkspace.x[2] + acadoWorkspace.evGx[107]*acadoWorkspace.x[3] + acadoWorkspace.d[26];\nacadoVariables.x[31] += + acadoWorkspace.evGx[108]*acadoWorkspace.x[0] + acadoWorkspace.evGx[109]*acadoWorkspace.x[1] + acadoWorkspace.evGx[110]*acadoWorkspace.x[2] + acadoWorkspace.evGx[111]*acadoWorkspace.x[3] + acadoWorkspace.d[27];\nacadoVariables.x[32] += + acadoWorkspace.evGx[112]*acadoWorkspace.x[0] + acadoWorkspace.evGx[113]*acadoWorkspace.x[1] + acadoWorkspace.evGx[114]*acadoWorkspace.x[2] + acadoWorkspace.evGx[115]*acadoWorkspace.x[3] + acadoWorkspace.d[28];\nacadoVariables.x[33] += + acadoWorkspace.evGx[116]*acadoWorkspace.x[0] + acadoWorkspace.evGx[117]*acadoWorkspace.x[1] + acadoWorkspace.evGx[118]*acadoWorkspace.x[2] + acadoWorkspace.evGx[119]*acadoWorkspace.x[3] + acadoWorkspace.d[29];\nacadoVariables.x[34] += + acadoWorkspace.evGx[120]*acadoWorkspace.x[0] + acadoWorkspace.evGx[121]*acadoWorkspace.x[1] + acadoWorkspace.evGx[122]*acadoWorkspace.x[2] + acadoWorkspace.evGx[123]*acadoWorkspace.x[3] + acadoWorkspace.d[30];\nacadoVariables.x[35] += + acadoWorkspace.evGx[124]*acadoWorkspace.x[0] + acadoWorkspace.evGx[125]*acadoWorkspace.x[1] + acadoWorkspace.evGx[126]*acadoWorkspace.x[2] + acadoWorkspace.evGx[127]*acadoWorkspace.x[3] + acadoWorkspace.d[31];\nacadoVariables.x[36] += + acadoWorkspace.evGx[128]*acadoWorkspace.x[0] + acadoWorkspace.evGx[129]*acadoWorkspace.x[1] + acadoWorkspace.evGx[130]*acadoWorkspace.x[2] + acadoWorkspace.evGx[131]*acadoWorkspace.x[3] + acadoWorkspace.d[32];\nacadoVariables.x[37] += + acadoWorkspace.evGx[132]*acadoWorkspace.x[0] + acadoWorkspace.evGx[133]*acadoWorkspace.x[1] + acadoWorkspace.evGx[134]*acadoWorkspace.x[2] + acadoWorkspace.evGx[135]*acadoWorkspace.x[3] + acadoWorkspace.d[33];\nacadoVariables.x[38] += + acadoWorkspace.evGx[136]*acadoWorkspace.x[0] + acadoWorkspace.evGx[137]*acadoWorkspace.x[1] + acadoWorkspace.evGx[138]*acadoWorkspace.x[2] + acadoWorkspace.evGx[139]*acadoWorkspace.x[3] + acadoWorkspace.d[34];\nacadoVariables.x[39] += + acadoWorkspace.evGx[140]*acadoWorkspace.x[0] + acadoWorkspace.evGx[141]*acadoWorkspace.x[1] + acadoWorkspace.evGx[142]*acadoWorkspace.x[2] + acadoWorkspace.evGx[143]*acadoWorkspace.x[3] + acadoWorkspace.d[35];\nacadoVariables.x[40] += + acadoWorkspace.evGx[144]*acadoWorkspace.x[0] + acadoWorkspace.evGx[145]*acadoWorkspace.x[1] + acadoWorkspace.evGx[146]*acadoWorkspace.x[2] + acadoWorkspace.evGx[147]*acadoWorkspace.x[3] + acadoWorkspace.d[36];\nacadoVariables.x[41] += + acadoWorkspace.evGx[148]*acadoWorkspace.x[0] + acadoWorkspace.evGx[149]*acadoWorkspace.x[1] + acadoWorkspace.evGx[150]*acadoWorkspace.x[2] + acadoWorkspace.evGx[151]*acadoWorkspace.x[3] + acadoWorkspace.d[37];\nacadoVariables.x[42] += + acadoWorkspace.evGx[152]*acadoWorkspace.x[0] + acadoWorkspace.evGx[153]*acadoWorkspace.x[1] + acadoWorkspace.evGx[154]*acadoWorkspace.x[2] + acadoWorkspace.evGx[155]*acadoWorkspace.x[3] + acadoWorkspace.d[38];\nacadoVariables.x[43] += + acadoWorkspace.evGx[156]*acadoWorkspace.x[0] + acadoWorkspace.evGx[157]*acadoWorkspace.x[1] + acadoWorkspace.evGx[158]*acadoWorkspace.x[2] + acadoWorkspace.evGx[159]*acadoWorkspace.x[3] + acadoWorkspace.d[39];\nacadoVariables.x[44] += + acadoWorkspace.evGx[160]*acadoWorkspace.x[0] + acadoWorkspace.evGx[161]*acadoWorkspace.x[1] + acadoWorkspace.evGx[162]*acadoWorkspace.x[2] + acadoWorkspace.evGx[163]*acadoWorkspace.x[3] + acadoWorkspace.d[40];\nacadoVariables.x[45] += + acadoWorkspace.evGx[164]*acadoWorkspace.x[0] + acadoWorkspace.evGx[165]*acadoWorkspace.x[1] + acadoWorkspace.evGx[166]*acadoWorkspace.x[2] + acadoWorkspace.evGx[167]*acadoWorkspace.x[3] + acadoWorkspace.d[41];\nacadoVariables.x[46] += + acadoWorkspace.evGx[168]*acadoWorkspace.x[0] + acadoWorkspace.evGx[169]*acadoWorkspace.x[1] + acadoWorkspace.evGx[170]*acadoWorkspace.x[2] + acadoWorkspace.evGx[171]*acadoWorkspace.x[3] + acadoWorkspace.d[42];\nacadoVariables.x[47] += + acadoWorkspace.evGx[172]*acadoWorkspace.x[0] + acadoWorkspace.evGx[173]*acadoWorkspace.x[1] + acadoWorkspace.evGx[174]*acadoWorkspace.x[2] + acadoWorkspace.evGx[175]*acadoWorkspace.x[3] + acadoWorkspace.d[43];\nacadoVariables.x[48] += + acadoWorkspace.evGx[176]*acadoWorkspace.x[0] + acadoWorkspace.evGx[177]*acadoWorkspace.x[1] + acadoWorkspace.evGx[178]*acadoWorkspace.x[2] + acadoWorkspace.evGx[179]*acadoWorkspace.x[3] + acadoWorkspace.d[44];\nacadoVariables.x[49] += + acadoWorkspace.evGx[180]*acadoWorkspace.x[0] + acadoWorkspace.evGx[181]*acadoWorkspace.x[1] + acadoWorkspace.evGx[182]*acadoWorkspace.x[2] + acadoWorkspace.evGx[183]*acadoWorkspace.x[3] + acadoWorkspace.d[45];\nacadoVariables.x[50] += + acadoWorkspace.evGx[184]*acadoWorkspace.x[0] + acadoWorkspace.evGx[185]*acadoWorkspace.x[1] + acadoWorkspace.evGx[186]*acadoWorkspace.x[2] + acadoWorkspace.evGx[187]*acadoWorkspace.x[3] + acadoWorkspace.d[46];\nacadoVariables.x[51] += + acadoWorkspace.evGx[188]*acadoWorkspace.x[0] + acadoWorkspace.evGx[189]*acadoWorkspace.x[1] + acadoWorkspace.evGx[190]*acadoWorkspace.x[2] + acadoWorkspace.evGx[191]*acadoWorkspace.x[3] + acadoWorkspace.d[47];\nacadoVariables.x[52] += + acadoWorkspace.evGx[192]*acadoWorkspace.x[0] + acadoWorkspace.evGx[193]*acadoWorkspace.x[1] + acadoWorkspace.evGx[194]*acadoWorkspace.x[2] + acadoWorkspace.evGx[195]*acadoWorkspace.x[3] + acadoWorkspace.d[48];\nacadoVariables.x[53] += + acadoWorkspace.evGx[196]*acadoWorkspace.x[0] + acadoWorkspace.evGx[197]*acadoWorkspace.x[1] + acadoWorkspace.evGx[198]*acadoWorkspace.x[2] + acadoWorkspace.evGx[199]*acadoWorkspace.x[3] + acadoWorkspace.d[49];\nacadoVariables.x[54] += + acadoWorkspace.evGx[200]*acadoWorkspace.x[0] + acadoWorkspace.evGx[201]*acadoWorkspace.x[1] + acadoWorkspace.evGx[202]*acadoWorkspace.x[2] + acadoWorkspace.evGx[203]*acadoWorkspace.x[3] + acadoWorkspace.d[50];\nacadoVariables.x[55] += + acadoWorkspace.evGx[204]*acadoWorkspace.x[0] + acadoWorkspace.evGx[205]*acadoWorkspace.x[1] + acadoWorkspace.evGx[206]*acadoWorkspace.x[2] + acadoWorkspace.evGx[207]*acadoWorkspace.x[3] + acadoWorkspace.d[51];\nacadoVariables.x[56] += + acadoWorkspace.evGx[208]*acadoWorkspace.x[0] + acadoWorkspace.evGx[209]*acadoWorkspace.x[1] + acadoWorkspace.evGx[210]*acadoWorkspace.x[2] + acadoWorkspace.evGx[211]*acadoWorkspace.x[3] + acadoWorkspace.d[52];\nacadoVariables.x[57] += + acadoWorkspace.evGx[212]*acadoWorkspace.x[0] + acadoWorkspace.evGx[213]*acadoWorkspace.x[1] + acadoWorkspace.evGx[214]*acadoWorkspace.x[2] + acadoWorkspace.evGx[215]*acadoWorkspace.x[3] + acadoWorkspace.d[53];\nacadoVariables.x[58] += + acadoWorkspace.evGx[216]*acadoWorkspace.x[0] + acadoWorkspace.evGx[217]*acadoWorkspace.x[1] + acadoWorkspace.evGx[218]*acadoWorkspace.x[2] + acadoWorkspace.evGx[219]*acadoWorkspace.x[3] + acadoWorkspace.d[54];\nacadoVariables.x[59] += + acadoWorkspace.evGx[220]*acadoWorkspace.x[0] + acadoWorkspace.evGx[221]*acadoWorkspace.x[1] + acadoWorkspace.evGx[222]*acadoWorkspace.x[2] + acadoWorkspace.evGx[223]*acadoWorkspace.x[3] + acadoWorkspace.d[55];\nacadoVariables.x[60] += + acadoWorkspace.evGx[224]*acadoWorkspace.x[0] + acadoWorkspace.evGx[225]*acadoWorkspace.x[1] + acadoWorkspace.evGx[226]*acadoWorkspace.x[2] + acadoWorkspace.evGx[227]*acadoWorkspace.x[3] + acadoWorkspace.d[56];\nacadoVariables.x[61] += + acadoWorkspace.evGx[228]*acadoWorkspace.x[0] + acadoWorkspace.evGx[229]*acadoWorkspace.x[1] + acadoWorkspace.evGx[230]*acadoWorkspace.x[2] + acadoWorkspace.evGx[231]*acadoWorkspace.x[3] + acadoWorkspace.d[57];\nacadoVariables.x[62] += + acadoWorkspace.evGx[232]*acadoWorkspace.x[0] + acadoWorkspace.evGx[233]*acadoWorkspace.x[1] + acadoWorkspace.evGx[234]*acadoWorkspace.x[2] + acadoWorkspace.evGx[235]*acadoWorkspace.x[3] + acadoWorkspace.d[58];\nacadoVariables.x[63] += + acadoWorkspace.evGx[236]*acadoWorkspace.x[0] + acadoWorkspace.evGx[237]*acadoWorkspace.x[1] + acadoWorkspace.evGx[238]*acadoWorkspace.x[2] + acadoWorkspace.evGx[239]*acadoWorkspace.x[3] + acadoWorkspace.d[59];\nacadoVariables.x[64] += + acadoWorkspace.evGx[240]*acadoWorkspace.x[0] + acadoWorkspace.evGx[241]*acadoWorkspace.x[1] + acadoWorkspace.evGx[242]*acadoWorkspace.x[2] + acadoWorkspace.evGx[243]*acadoWorkspace.x[3] + acadoWorkspace.d[60];\nacadoVariables.x[65] += + acadoWorkspace.evGx[244]*acadoWorkspace.x[0] + acadoWorkspace.evGx[245]*acadoWorkspace.x[1] + acadoWorkspace.evGx[246]*acadoWorkspace.x[2] + acadoWorkspace.evGx[247]*acadoWorkspace.x[3] + acadoWorkspace.d[61];\nacadoVariables.x[66] += + acadoWorkspace.evGx[248]*acadoWorkspace.x[0] + acadoWorkspace.evGx[249]*acadoWorkspace.x[1] + acadoWorkspace.evGx[250]*acadoWorkspace.x[2] + acadoWorkspace.evGx[251]*acadoWorkspace.x[3] + acadoWorkspace.d[62];\nacadoVariables.x[67] += + acadoWorkspace.evGx[252]*acadoWorkspace.x[0] + acadoWorkspace.evGx[253]*acadoWorkspace.x[1] + acadoWorkspace.evGx[254]*acadoWorkspace.x[2] + acadoWorkspace.evGx[255]*acadoWorkspace.x[3] + acadoWorkspace.d[63];\nacadoVariables.x[68] += + acadoWorkspace.evGx[256]*acadoWorkspace.x[0] + acadoWorkspace.evGx[257]*acadoWorkspace.x[1] + acadoWorkspace.evGx[258]*acadoWorkspace.x[2] + acadoWorkspace.evGx[259]*acadoWorkspace.x[3] + acadoWorkspace.d[64];\nacadoVariables.x[69] += + acadoWorkspace.evGx[260]*acadoWorkspace.x[0] + acadoWorkspace.evGx[261]*acadoWorkspace.x[1] + acadoWorkspace.evGx[262]*acadoWorkspace.x[2] + acadoWorkspace.evGx[263]*acadoWorkspace.x[3] + acadoWorkspace.d[65];\nacadoVariables.x[70] += + acadoWorkspace.evGx[264]*acadoWorkspace.x[0] + acadoWorkspace.evGx[265]*acadoWorkspace.x[1] + acadoWorkspace.evGx[266]*acadoWorkspace.x[2] + acadoWorkspace.evGx[267]*acadoWorkspace.x[3] + acadoWorkspace.d[66];\nacadoVariables.x[71] += + acadoWorkspace.evGx[268]*acadoWorkspace.x[0] + acadoWorkspace.evGx[269]*acadoWorkspace.x[1] + acadoWorkspace.evGx[270]*acadoWorkspace.x[2] + acadoWorkspace.evGx[271]*acadoWorkspace.x[3] + acadoWorkspace.d[67];\nacadoVariables.x[72] += + acadoWorkspace.evGx[272]*acadoWorkspace.x[0] + acadoWorkspace.evGx[273]*acadoWorkspace.x[1] + acadoWorkspace.evGx[274]*acadoWorkspace.x[2] + acadoWorkspace.evGx[275]*acadoWorkspace.x[3] + acadoWorkspace.d[68];\nacadoVariables.x[73] += + acadoWorkspace.evGx[276]*acadoWorkspace.x[0] + acadoWorkspace.evGx[277]*acadoWorkspace.x[1] + acadoWorkspace.evGx[278]*acadoWorkspace.x[2] + acadoWorkspace.evGx[279]*acadoWorkspace.x[3] + acadoWorkspace.d[69];\nacadoVariables.x[74] += + acadoWorkspace.evGx[280]*acadoWorkspace.x[0] + acadoWorkspace.evGx[281]*acadoWorkspace.x[1] + acadoWorkspace.evGx[282]*acadoWorkspace.x[2] + acadoWorkspace.evGx[283]*acadoWorkspace.x[3] + acadoWorkspace.d[70];\nacadoVariables.x[75] += + acadoWorkspace.evGx[284]*acadoWorkspace.x[0] + acadoWorkspace.evGx[285]*acadoWorkspace.x[1] + acadoWorkspace.evGx[286]*acadoWorkspace.x[2] + acadoWorkspace.evGx[287]*acadoWorkspace.x[3] + acadoWorkspace.d[71];\nacadoVariables.x[76] += + acadoWorkspace.evGx[288]*acadoWorkspace.x[0] + acadoWorkspace.evGx[289]*acadoWorkspace.x[1] + acadoWorkspace.evGx[290]*acadoWorkspace.x[2] + acadoWorkspace.evGx[291]*acadoWorkspace.x[3] + acadoWorkspace.d[72];\nacadoVariables.x[77] += + acadoWorkspace.evGx[292]*acadoWorkspace.x[0] + acadoWorkspace.evGx[293]*acadoWorkspace.x[1] + acadoWorkspace.evGx[294]*acadoWorkspace.x[2] + acadoWorkspace.evGx[295]*acadoWorkspace.x[3] + acadoWorkspace.d[73];\nacadoVariables.x[78] += + acadoWorkspace.evGx[296]*acadoWorkspace.x[0] + acadoWorkspace.evGx[297]*acadoWorkspace.x[1] + acadoWorkspace.evGx[298]*acadoWorkspace.x[2] + acadoWorkspace.evGx[299]*acadoWorkspace.x[3] + acadoWorkspace.d[74];\nacadoVariables.x[79] += + acadoWorkspace.evGx[300]*acadoWorkspace.x[0] + acadoWorkspace.evGx[301]*acadoWorkspace.x[1] + acadoWorkspace.evGx[302]*acadoWorkspace.x[2] + acadoWorkspace.evGx[303]*acadoWorkspace.x[3] + acadoWorkspace.d[75];\nacadoVariables.x[80] += + acadoWorkspace.evGx[304]*acadoWorkspace.x[0] + acadoWorkspace.evGx[305]*acadoWorkspace.x[1] + acadoWorkspace.evGx[306]*acadoWorkspace.x[2] + acadoWorkspace.evGx[307]*acadoWorkspace.x[3] + acadoWorkspace.d[76];\nacadoVariables.x[81] += + acadoWorkspace.evGx[308]*acadoWorkspace.x[0] + acadoWorkspace.evGx[309]*acadoWorkspace.x[1] + acadoWorkspace.evGx[310]*acadoWorkspace.x[2] + acadoWorkspace.evGx[311]*acadoWorkspace.x[3] + acadoWorkspace.d[77];\nacadoVariables.x[82] += + acadoWorkspace.evGx[312]*acadoWorkspace.x[0] + acadoWorkspace.evGx[313]*acadoWorkspace.x[1] + acadoWorkspace.evGx[314]*acadoWorkspace.x[2] + acadoWorkspace.evGx[315]*acadoWorkspace.x[3] + acadoWorkspace.d[78];\nacadoVariables.x[83] += + acadoWorkspace.evGx[316]*acadoWorkspace.x[0] + acadoWorkspace.evGx[317]*acadoWorkspace.x[1] + acadoWorkspace.evGx[318]*acadoWorkspace.x[2] + acadoWorkspace.evGx[319]*acadoWorkspace.x[3] + acadoWorkspace.d[79];\nacadoVariables.x[84] += + acadoWorkspace.evGx[320]*acadoWorkspace.x[0] + acadoWorkspace.evGx[321]*acadoWorkspace.x[1] + acadoWorkspace.evGx[322]*acadoWorkspace.x[2] + acadoWorkspace.evGx[323]*acadoWorkspace.x[3] + acadoWorkspace.d[80];\nacadoVariables.x[85] += + acadoWorkspace.evGx[324]*acadoWorkspace.x[0] + acadoWorkspace.evGx[325]*acadoWorkspace.x[1] + acadoWorkspace.evGx[326]*acadoWorkspace.x[2] + acadoWorkspace.evGx[327]*acadoWorkspace.x[3] + acadoWorkspace.d[81];\nacadoVariables.x[86] += + acadoWorkspace.evGx[328]*acadoWorkspace.x[0] + acadoWorkspace.evGx[329]*acadoWorkspace.x[1] + acadoWorkspace.evGx[330]*acadoWorkspace.x[2] + acadoWorkspace.evGx[331]*acadoWorkspace.x[3] + acadoWorkspace.d[82];\nacadoVariables.x[87] += + acadoWorkspace.evGx[332]*acadoWorkspace.x[0] + acadoWorkspace.evGx[333]*acadoWorkspace.x[1] + acadoWorkspace.evGx[334]*acadoWorkspace.x[2] + acadoWorkspace.evGx[335]*acadoWorkspace.x[3] + acadoWorkspace.d[83];\nacadoVariables.x[88] += + acadoWorkspace.evGx[336]*acadoWorkspace.x[0] + acadoWorkspace.evGx[337]*acadoWorkspace.x[1] + acadoWorkspace.evGx[338]*acadoWorkspace.x[2] + acadoWorkspace.evGx[339]*acadoWorkspace.x[3] + acadoWorkspace.d[84];\nacadoVariables.x[89] += + acadoWorkspace.evGx[340]*acadoWorkspace.x[0] + acadoWorkspace.evGx[341]*acadoWorkspace.x[1] + acadoWorkspace.evGx[342]*acadoWorkspace.x[2] + acadoWorkspace.evGx[343]*acadoWorkspace.x[3] + acadoWorkspace.d[85];\nacadoVariables.x[90] += + acadoWorkspace.evGx[344]*acadoWorkspace.x[0] + acadoWorkspace.evGx[345]*acadoWorkspace.x[1] + acadoWorkspace.evGx[346]*acadoWorkspace.x[2] + acadoWorkspace.evGx[347]*acadoWorkspace.x[3] + acadoWorkspace.d[86];\nacadoVariables.x[91] += + acadoWorkspace.evGx[348]*acadoWorkspace.x[0] + acadoWorkspace.evGx[349]*acadoWorkspace.x[1] + acadoWorkspace.evGx[350]*acadoWorkspace.x[2] + acadoWorkspace.evGx[351]*acadoWorkspace.x[3] + acadoWorkspace.d[87];\nacadoVariables.x[92] += + acadoWorkspace.evGx[352]*acadoWorkspace.x[0] + acadoWorkspace.evGx[353]*acadoWorkspace.x[1] + acadoWorkspace.evGx[354]*acadoWorkspace.x[2] + acadoWorkspace.evGx[355]*acadoWorkspace.x[3] + acadoWorkspace.d[88];\nacadoVariables.x[93] += + acadoWorkspace.evGx[356]*acadoWorkspace.x[0] + acadoWorkspace.evGx[357]*acadoWorkspace.x[1] + acadoWorkspace.evGx[358]*acadoWorkspace.x[2] + acadoWorkspace.evGx[359]*acadoWorkspace.x[3] + acadoWorkspace.d[89];\nacadoVariables.x[94] += + acadoWorkspace.evGx[360]*acadoWorkspace.x[0] + acadoWorkspace.evGx[361]*acadoWorkspace.x[1] + acadoWorkspace.evGx[362]*acadoWorkspace.x[2] + acadoWorkspace.evGx[363]*acadoWorkspace.x[3] + acadoWorkspace.d[90];\nacadoVariables.x[95] += + acadoWorkspace.evGx[364]*acadoWorkspace.x[0] + acadoWorkspace.evGx[365]*acadoWorkspace.x[1] + acadoWorkspace.evGx[366]*acadoWorkspace.x[2] + acadoWorkspace.evGx[367]*acadoWorkspace.x[3] + acadoWorkspace.d[91];\nacadoVariables.x[96] += + acadoWorkspace.evGx[368]*acadoWorkspace.x[0] + acadoWorkspace.evGx[369]*acadoWorkspace.x[1] + acadoWorkspace.evGx[370]*acadoWorkspace.x[2] + acadoWorkspace.evGx[371]*acadoWorkspace.x[3] + acadoWorkspace.d[92];\nacadoVariables.x[97] += + acadoWorkspace.evGx[372]*acadoWorkspace.x[0] + acadoWorkspace.evGx[373]*acadoWorkspace.x[1] + acadoWorkspace.evGx[374]*acadoWorkspace.x[2] + acadoWorkspace.evGx[375]*acadoWorkspace.x[3] + acadoWorkspace.d[93];\nacadoVariables.x[98] += + acadoWorkspace.evGx[376]*acadoWorkspace.x[0] + acadoWorkspace.evGx[377]*acadoWorkspace.x[1] + acadoWorkspace.evGx[378]*acadoWorkspace.x[2] + acadoWorkspace.evGx[379]*acadoWorkspace.x[3] + acadoWorkspace.d[94];\nacadoVariables.x[99] += + acadoWorkspace.evGx[380]*acadoWorkspace.x[0] + acadoWorkspace.evGx[381]*acadoWorkspace.x[1] + acadoWorkspace.evGx[382]*acadoWorkspace.x[2] + acadoWorkspace.evGx[383]*acadoWorkspace.x[3] + acadoWorkspace.d[95];\nacadoVariables.x[100] += + acadoWorkspace.evGx[384]*acadoWorkspace.x[0] + acadoWorkspace.evGx[385]*acadoWorkspace.x[1] + acadoWorkspace.evGx[386]*acadoWorkspace.x[2] + acadoWorkspace.evGx[387]*acadoWorkspace.x[3] + acadoWorkspace.d[96];\nacadoVariables.x[101] += + acadoWorkspace.evGx[388]*acadoWorkspace.x[0] + acadoWorkspace.evGx[389]*acadoWorkspace.x[1] + acadoWorkspace.evGx[390]*acadoWorkspace.x[2] + acadoWorkspace.evGx[391]*acadoWorkspace.x[3] + acadoWorkspace.d[97];\nacadoVariables.x[102] += + acadoWorkspace.evGx[392]*acadoWorkspace.x[0] + acadoWorkspace.evGx[393]*acadoWorkspace.x[1] + acadoWorkspace.evGx[394]*acadoWorkspace.x[2] + acadoWorkspace.evGx[395]*acadoWorkspace.x[3] + acadoWorkspace.d[98];\nacadoVariables.x[103] += + acadoWorkspace.evGx[396]*acadoWorkspace.x[0] + acadoWorkspace.evGx[397]*acadoWorkspace.x[1] + acadoWorkspace.evGx[398]*acadoWorkspace.x[2] + acadoWorkspace.evGx[399]*acadoWorkspace.x[3] + acadoWorkspace.d[99];\nacadoVariables.x[104] += + acadoWorkspace.evGx[400]*acadoWorkspace.x[0] + acadoWorkspace.evGx[401]*acadoWorkspace.x[1] + acadoWorkspace.evGx[402]*acadoWorkspace.x[2] + acadoWorkspace.evGx[403]*acadoWorkspace.x[3] + acadoWorkspace.d[100];\nacadoVariables.x[105] += + acadoWorkspace.evGx[404]*acadoWorkspace.x[0] + acadoWorkspace.evGx[405]*acadoWorkspace.x[1] + acadoWorkspace.evGx[406]*acadoWorkspace.x[2] + acadoWorkspace.evGx[407]*acadoWorkspace.x[3] + acadoWorkspace.d[101];\nacadoVariables.x[106] += + acadoWorkspace.evGx[408]*acadoWorkspace.x[0] + acadoWorkspace.evGx[409]*acadoWorkspace.x[1] + acadoWorkspace.evGx[410]*acadoWorkspace.x[2] + acadoWorkspace.evGx[411]*acadoWorkspace.x[3] + acadoWorkspace.d[102];\nacadoVariables.x[107] += + acadoWorkspace.evGx[412]*acadoWorkspace.x[0] + acadoWorkspace.evGx[413]*acadoWorkspace.x[1] + acadoWorkspace.evGx[414]*acadoWorkspace.x[2] + acadoWorkspace.evGx[415]*acadoWorkspace.x[3] + acadoWorkspace.d[103];\nacadoVariables.x[108] += + acadoWorkspace.evGx[416]*acadoWorkspace.x[0] + acadoWorkspace.evGx[417]*acadoWorkspace.x[1] + acadoWorkspace.evGx[418]*acadoWorkspace.x[2] + acadoWorkspace.evGx[419]*acadoWorkspace.x[3] + acadoWorkspace.d[104];\nacadoVariables.x[109] += + acadoWorkspace.evGx[420]*acadoWorkspace.x[0] + acadoWorkspace.evGx[421]*acadoWorkspace.x[1] + acadoWorkspace.evGx[422]*acadoWorkspace.x[2] + acadoWorkspace.evGx[423]*acadoWorkspace.x[3] + acadoWorkspace.d[105];\nacadoVariables.x[110] += + acadoWorkspace.evGx[424]*acadoWorkspace.x[0] + acadoWorkspace.evGx[425]*acadoWorkspace.x[1] + acadoWorkspace.evGx[426]*acadoWorkspace.x[2] + acadoWorkspace.evGx[427]*acadoWorkspace.x[3] + acadoWorkspace.d[106];\nacadoVariables.x[111] += + acadoWorkspace.evGx[428]*acadoWorkspace.x[0] + acadoWorkspace.evGx[429]*acadoWorkspace.x[1] + acadoWorkspace.evGx[430]*acadoWorkspace.x[2] + acadoWorkspace.evGx[431]*acadoWorkspace.x[3] + acadoWorkspace.d[107];\nacadoVariables.x[112] += + acadoWorkspace.evGx[432]*acadoWorkspace.x[0] + acadoWorkspace.evGx[433]*acadoWorkspace.x[1] + acadoWorkspace.evGx[434]*acadoWorkspace.x[2] + acadoWorkspace.evGx[435]*acadoWorkspace.x[3] + acadoWorkspace.d[108];\nacadoVariables.x[113] += + acadoWorkspace.evGx[436]*acadoWorkspace.x[0] + acadoWorkspace.evGx[437]*acadoWorkspace.x[1] + acadoWorkspace.evGx[438]*acadoWorkspace.x[2] + acadoWorkspace.evGx[439]*acadoWorkspace.x[3] + acadoWorkspace.d[109];\nacadoVariables.x[114] += + acadoWorkspace.evGx[440]*acadoWorkspace.x[0] + acadoWorkspace.evGx[441]*acadoWorkspace.x[1] + acadoWorkspace.evGx[442]*acadoWorkspace.x[2] + acadoWorkspace.evGx[443]*acadoWorkspace.x[3] + acadoWorkspace.d[110];\nacadoVariables.x[115] += + acadoWorkspace.evGx[444]*acadoWorkspace.x[0] + acadoWorkspace.evGx[445]*acadoWorkspace.x[1] + acadoWorkspace.evGx[446]*acadoWorkspace.x[2] + acadoWorkspace.evGx[447]*acadoWorkspace.x[3] + acadoWorkspace.d[111];\nacadoVariables.x[116] += + acadoWorkspace.evGx[448]*acadoWorkspace.x[0] + acadoWorkspace.evGx[449]*acadoWorkspace.x[1] + acadoWorkspace.evGx[450]*acadoWorkspace.x[2] + acadoWorkspace.evGx[451]*acadoWorkspace.x[3] + acadoWorkspace.d[112];\nacadoVariables.x[117] += + acadoWorkspace.evGx[452]*acadoWorkspace.x[0] + acadoWorkspace.evGx[453]*acadoWorkspace.x[1] + acadoWorkspace.evGx[454]*acadoWorkspace.x[2] + acadoWorkspace.evGx[455]*acadoWorkspace.x[3] + acadoWorkspace.d[113];\nacadoVariables.x[118] += + acadoWorkspace.evGx[456]*acadoWorkspace.x[0] + acadoWorkspace.evGx[457]*acadoWorkspace.x[1] + acadoWorkspace.evGx[458]*acadoWorkspace.x[2] + acadoWorkspace.evGx[459]*acadoWorkspace.x[3] + acadoWorkspace.d[114];\nacadoVariables.x[119] += + acadoWorkspace.evGx[460]*acadoWorkspace.x[0] + acadoWorkspace.evGx[461]*acadoWorkspace.x[1] + acadoWorkspace.evGx[462]*acadoWorkspace.x[2] + acadoWorkspace.evGx[463]*acadoWorkspace.x[3] + acadoWorkspace.d[115];\nacadoVariables.x[120] += + acadoWorkspace.evGx[464]*acadoWorkspace.x[0] + acadoWorkspace.evGx[465]*acadoWorkspace.x[1] + acadoWorkspace.evGx[466]*acadoWorkspace.x[2] + acadoWorkspace.evGx[467]*acadoWorkspace.x[3] + acadoWorkspace.d[116];\nacadoVariables.x[121] += + acadoWorkspace.evGx[468]*acadoWorkspace.x[0] + acadoWorkspace.evGx[469]*acadoWorkspace.x[1] + acadoWorkspace.evGx[470]*acadoWorkspace.x[2] + acadoWorkspace.evGx[471]*acadoWorkspace.x[3] + acadoWorkspace.d[117];\nacadoVariables.x[122] += + acadoWorkspace.evGx[472]*acadoWorkspace.x[0] + acadoWorkspace.evGx[473]*acadoWorkspace.x[1] + acadoWorkspace.evGx[474]*acadoWorkspace.x[2] + acadoWorkspace.evGx[475]*acadoWorkspace.x[3] + acadoWorkspace.d[118];\nacadoVariables.x[123] += + acadoWorkspace.evGx[476]*acadoWorkspace.x[0] + acadoWorkspace.evGx[477]*acadoWorkspace.x[1] + acadoWorkspace.evGx[478]*acadoWorkspace.x[2] + acadoWorkspace.evGx[479]*acadoWorkspace.x[3] + acadoWorkspace.d[119];\nacadoVariables.x[124] += + acadoWorkspace.evGx[480]*acadoWorkspace.x[0] + acadoWorkspace.evGx[481]*acadoWorkspace.x[1] + acadoWorkspace.evGx[482]*acadoWorkspace.x[2] + acadoWorkspace.evGx[483]*acadoWorkspace.x[3] + acadoWorkspace.d[120];\nacadoVariables.x[125] += + acadoWorkspace.evGx[484]*acadoWorkspace.x[0] + acadoWorkspace.evGx[485]*acadoWorkspace.x[1] + acadoWorkspace.evGx[486]*acadoWorkspace.x[2] + acadoWorkspace.evGx[487]*acadoWorkspace.x[3] + acadoWorkspace.d[121];\nacadoVariables.x[126] += + acadoWorkspace.evGx[488]*acadoWorkspace.x[0] + acadoWorkspace.evGx[489]*acadoWorkspace.x[1] + acadoWorkspace.evGx[490]*acadoWorkspace.x[2] + acadoWorkspace.evGx[491]*acadoWorkspace.x[3] + acadoWorkspace.d[122];\nacadoVariables.x[127] += + acadoWorkspace.evGx[492]*acadoWorkspace.x[0] + acadoWorkspace.evGx[493]*acadoWorkspace.x[1] + acadoWorkspace.evGx[494]*acadoWorkspace.x[2] + acadoWorkspace.evGx[495]*acadoWorkspace.x[3] + acadoWorkspace.d[123];\nacadoVariables.x[128] += + acadoWorkspace.evGx[496]*acadoWorkspace.x[0] + acadoWorkspace.evGx[497]*acadoWorkspace.x[1] + acadoWorkspace.evGx[498]*acadoWorkspace.x[2] + acadoWorkspace.evGx[499]*acadoWorkspace.x[3] + acadoWorkspace.d[124];\nacadoVariables.x[129] += + acadoWorkspace.evGx[500]*acadoWorkspace.x[0] + acadoWorkspace.evGx[501]*acadoWorkspace.x[1] + acadoWorkspace.evGx[502]*acadoWorkspace.x[2] + acadoWorkspace.evGx[503]*acadoWorkspace.x[3] + acadoWorkspace.d[125];\nacadoVariables.x[130] += + acadoWorkspace.evGx[504]*acadoWorkspace.x[0] + acadoWorkspace.evGx[505]*acadoWorkspace.x[1] + acadoWorkspace.evGx[506]*acadoWorkspace.x[2] + acadoWorkspace.evGx[507]*acadoWorkspace.x[3] + acadoWorkspace.d[126];\nacadoVariables.x[131] += + acadoWorkspace.evGx[508]*acadoWorkspace.x[0] + acadoWorkspace.evGx[509]*acadoWorkspace.x[1] + acadoWorkspace.evGx[510]*acadoWorkspace.x[2] + acadoWorkspace.evGx[511]*acadoWorkspace.x[3] + acadoWorkspace.d[127];\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nfor (lRun2 = 0; lRun2 < lRun1 + 1; ++lRun2)\n{\nlRun3 = (((lRun1 + 1) * (lRun1)) / (2)) + (lRun2);\nacado_multEDu( &(acadoWorkspace.E[ lRun3 * 8 ]), &(acadoWorkspace.x[ lRun2 * 2 + 4 ]), &(acadoVariables.x[ lRun1 * 4 + 4 ]) );\n}\n}\n}\n\nint acado_preparationStep(  )\n{\nint ret;\n\nret = acado_modelSimulation();\nacado_evaluateObjective(  );\nacado_condensePrep(  );\nreturn ret;\n}\n\nint acado_feedbackStep(  )\n{\nint tmp;\n\nacado_condenseFdb(  );\n\ntmp = acado_solve( );\n\nacado_expand(  );\nreturn tmp;\n}\n\nint acado_initializeSolver(  )\n{\nint ret;\n\n/* This is a function which must be called once before any other function call! */\n\n\nret = 0;\n\nmemset(&acadoWorkspace, 0, sizeof( acadoWorkspace ));\nreturn ret;\n}\n\nvoid acado_initializeNodesByForwardSimulation(  )\n{\nint index;\nfor (index = 0; index < 32; ++index)\n{\nacadoWorkspace.state[0] = acadoVariables.x[index * 4];\nacadoWorkspace.state[1] = acadoVariables.x[index * 4 + 1];\nacadoWorkspace.state[2] = acadoVariables.x[index * 4 + 2];\nacadoWorkspace.state[3] = acadoVariables.x[index * 4 + 3];\nacadoWorkspace.state[28] = acadoVariables.u[index * 2];\nacadoWorkspace.state[29] = acadoVariables.u[index * 2 + 1];\nacadoWorkspace.state[30] = acadoVariables.od[index * 2];\nacadoWorkspace.state[31] = acadoVariables.od[index * 2 + 1];\n\nacado_integrate(acadoWorkspace.state, index == 0, index);\n\nacadoVariables.x[index * 4 + 4] = acadoWorkspace.state[0];\nacadoVariables.x[index * 4 + 5] = acadoWorkspace.state[1];\nacadoVariables.x[index * 4 + 6] = acadoWorkspace.state[2];\nacadoVariables.x[index * 4 + 7] = acadoWorkspace.state[3];\n}\n}\n\nvoid acado_shiftStates( int strategy, real_t* const xEnd, real_t* const uEnd )\n{\nint index;\nfor (index = 0; index < 32; ++index)\n{\nacadoVariables.x[index * 4] = acadoVariables.x[index * 4 + 4];\nacadoVariables.x[index * 4 + 1] = acadoVariables.x[index * 4 + 5];\nacadoVariables.x[index * 4 + 2] = acadoVariables.x[index * 4 + 6];\nacadoVariables.x[index * 4 + 3] = acadoVariables.x[index * 4 + 7];\n}\n\nif (strategy == 1 && xEnd != 0)\n{\nacadoVariables.x[128] = xEnd[0];\nacadoVariables.x[129] = xEnd[1];\nacadoVariables.x[130] = xEnd[2];\nacadoVariables.x[131] = xEnd[3];\n}\nelse if (strategy == 2) \n{\nacadoWorkspace.state[0] = acadoVariables.x[128];\nacadoWorkspace.state[1] = acadoVariables.x[129];\nacadoWorkspace.state[2] = acadoVariables.x[130];\nacadoWorkspace.state[3] = acadoVariables.x[131];\nif (uEnd != 0)\n{\nacadoWorkspace.state[28] = uEnd[0];\nacadoWorkspace.state[29] = uEnd[1];\n}\nelse\n{\nacadoWorkspace.state[28] = acadoVariables.u[62];\nacadoWorkspace.state[29] = acadoVariables.u[63];\n}\nacadoWorkspace.state[30] = acadoVariables.od[64];\nacadoWorkspace.state[31] = acadoVariables.od[65];\n\nacado_integrate(acadoWorkspace.state, 1, 31);\n\nacadoVariables.x[128] = acadoWorkspace.state[0];\nacadoVariables.x[129] = acadoWorkspace.state[1];\nacadoVariables.x[130] = acadoWorkspace.state[2];\nacadoVariables.x[131] = acadoWorkspace.state[3];\n}\n}\n\nvoid acado_shiftControls( real_t* const uEnd )\n{\nint index;\nfor (index = 0; index < 31; ++index)\n{\nacadoVariables.u[index * 2] = acadoVariables.u[index * 2 + 2];\nacadoVariables.u[index * 2 + 1] = acadoVariables.u[index * 2 + 3];\n}\n\nif (uEnd != 0)\n{\nacadoVariables.u[62] = uEnd[0];\nacadoVariables.u[63] = uEnd[1];\n}\n}\n\nreal_t acado_getKKT(  )\n{\nreal_t kkt;\n\nint index;\nreal_t prd;\n\nkkt = + acadoWorkspace.g[0]*acadoWorkspace.x[0] + acadoWorkspace.g[1]*acadoWorkspace.x[1] + acadoWorkspace.g[2]*acadoWorkspace.x[2] + acadoWorkspace.g[3]*acadoWorkspace.x[3] + acadoWorkspace.g[4]*acadoWorkspace.x[4] + acadoWorkspace.g[5]*acadoWorkspace.x[5] + acadoWorkspace.g[6]*acadoWorkspace.x[6] + acadoWorkspace.g[7]*acadoWorkspace.x[7] + acadoWorkspace.g[8]*acadoWorkspace.x[8] + acadoWorkspace.g[9]*acadoWorkspace.x[9] + acadoWorkspace.g[10]*acadoWorkspace.x[10] + acadoWorkspace.g[11]*acadoWorkspace.x[11] + acadoWorkspace.g[12]*acadoWorkspace.x[12] + acadoWorkspace.g[13]*acadoWorkspace.x[13] + acadoWorkspace.g[14]*acadoWorkspace.x[14] + acadoWorkspace.g[15]*acadoWorkspace.x[15] + acadoWorkspace.g[16]*acadoWorkspace.x[16] + acadoWorkspace.g[17]*acadoWorkspace.x[17] + acadoWorkspace.g[18]*acadoWorkspace.x[18] + acadoWorkspace.g[19]*acadoWorkspace.x[19] + acadoWorkspace.g[20]*acadoWorkspace.x[20] + acadoWorkspace.g[21]*acadoWorkspace.x[21] + acadoWorkspace.g[22]*acadoWorkspace.x[22] + acadoWorkspace.g[23]*acadoWorkspace.x[23] + acadoWorkspace.g[24]*acadoWorkspace.x[24] + acadoWorkspace.g[25]*acadoWorkspace.x[25] + acadoWorkspace.g[26]*acadoWorkspace.x[26] + acadoWorkspace.g[27]*acadoWorkspace.x[27] + acadoWorkspace.g[28]*acadoWorkspace.x[28] + acadoWorkspace.g[29]*acadoWorkspace.x[29] + acadoWorkspace.g[30]*acadoWorkspace.x[30] + acadoWorkspace.g[31]*acadoWorkspace.x[31] + acadoWorkspace.g[32]*acadoWorkspace.x[32] + acadoWorkspace.g[33]*acadoWorkspace.x[33] + acadoWorkspace.g[34]*acadoWorkspace.x[34] + acadoWorkspace.g[35]*acadoWorkspace.x[35] + acadoWorkspace.g[36]*acadoWorkspace.x[36] + acadoWorkspace.g[37]*acadoWorkspace.x[37] + acadoWorkspace.g[38]*acadoWorkspace.x[38] + acadoWorkspace.g[39]*acadoWorkspace.x[39] + acadoWorkspace.g[40]*acadoWorkspace.x[40] + acadoWorkspace.g[41]*acadoWorkspace.x[41] + acadoWorkspace.g[42]*acadoWorkspace.x[42] + acadoWorkspace.g[43]*acadoWorkspace.x[43] + acadoWorkspace.g[44]*acadoWorkspace.x[44] + acadoWorkspace.g[45]*acadoWorkspace.x[45] + acadoWorkspace.g[46]*acadoWorkspace.x[46] + acadoWorkspace.g[47]*acadoWorkspace.x[47] + acadoWorkspace.g[48]*acadoWorkspace.x[48] + acadoWorkspace.g[49]*acadoWorkspace.x[49] + acadoWorkspace.g[50]*acadoWorkspace.x[50] + acadoWorkspace.g[51]*acadoWorkspace.x[51] + acadoWorkspace.g[52]*acadoWorkspace.x[52] + acadoWorkspace.g[53]*acadoWorkspace.x[53] + acadoWorkspace.g[54]*acadoWorkspace.x[54] + acadoWorkspace.g[55]*acadoWorkspace.x[55] + acadoWorkspace.g[56]*acadoWorkspace.x[56] + acadoWorkspace.g[57]*acadoWorkspace.x[57] + acadoWorkspace.g[58]*acadoWorkspace.x[58] + acadoWorkspace.g[59]*acadoWorkspace.x[59] + acadoWorkspace.g[60]*acadoWorkspace.x[60] + acadoWorkspace.g[61]*acadoWorkspace.x[61] + acadoWorkspace.g[62]*acadoWorkspace.x[62] + acadoWorkspace.g[63]*acadoWorkspace.x[63] + acadoWorkspace.g[64]*acadoWorkspace.x[64] + acadoWorkspace.g[65]*acadoWorkspace.x[65] + acadoWorkspace.g[66]*acadoWorkspace.x[66] + acadoWorkspace.g[67]*acadoWorkspace.x[67];\nkkt = fabs( kkt );\nfor (index = 0; index < 68; ++index)\n{\nprd = acadoWorkspace.y[index];\nif (prd > 1e-12)\nkkt += fabs(acadoWorkspace.lb[index] * prd);\nelse if (prd < -1e-12)\nkkt += fabs(acadoWorkspace.ub[index] * prd);\n}\nfor (index = 0; index < 96; ++index)\n{\nprd = acadoWorkspace.y[index + 68];\nif (prd > 1e-12)\nkkt += fabs(acadoWorkspace.lbA[index] * prd);\nelse if (prd < -1e-12)\nkkt += fabs(acadoWorkspace.ubA[index] * prd);\n}\nreturn kkt;\n}\n\nreal_t acado_getObjective(  )\n{\nreal_t objVal;\n\nint lRun1;\n/** Row vector of size: 5 */\nreal_t tmpDy[ 5 ];\n\n/** Row vector of size: 3 */\nreal_t tmpDyN[ 3 ];\n\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\nacadoWorkspace.objValueIn[0] = acadoVariables.x[lRun1 * 4];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[lRun1 * 4 + 1];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[lRun1 * 4 + 2];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[lRun1 * 4 + 3];\nacadoWorkspace.objValueIn[4] = acadoVariables.u[lRun1 * 2];\nacadoWorkspace.objValueIn[5] = acadoVariables.u[lRun1 * 2 + 1];\nacadoWorkspace.objValueIn[6] = acadoVariables.od[lRun1 * 2];\nacadoWorkspace.objValueIn[7] = acadoVariables.od[lRun1 * 2 + 1];\n\nacado_evaluateLSQ( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\nacadoWorkspace.Dy[lRun1 * 5] = acadoWorkspace.objValueOut[0] - acadoVariables.y[lRun1 * 5];\nacadoWorkspace.Dy[lRun1 * 5 + 1] = acadoWorkspace.objValueOut[1] - acadoVariables.y[lRun1 * 5 + 1];\nacadoWorkspace.Dy[lRun1 * 5 + 2] = acadoWorkspace.objValueOut[2] - acadoVariables.y[lRun1 * 5 + 2];\nacadoWorkspace.Dy[lRun1 * 5 + 3] = acadoWorkspace.objValueOut[3] - acadoVariables.y[lRun1 * 5 + 3];\nacadoWorkspace.Dy[lRun1 * 5 + 4] = acadoWorkspace.objValueOut[4] - acadoVariables.y[lRun1 * 5 + 4];\n}\nacadoWorkspace.objValueIn[0] = acadoVariables.x[128];\nacadoWorkspace.objValueIn[1] = acadoVariables.x[129];\nacadoWorkspace.objValueIn[2] = acadoVariables.x[130];\nacadoWorkspace.objValueIn[3] = acadoVariables.x[131];\nacadoWorkspace.objValueIn[4] = acadoVariables.od[64];\nacadoWorkspace.objValueIn[5] = acadoVariables.od[65];\nacado_evaluateLSQEndTerm( acadoWorkspace.objValueIn, acadoWorkspace.objValueOut );\nacadoWorkspace.DyN[0] = acadoWorkspace.objValueOut[0] - acadoVariables.yN[0];\nacadoWorkspace.DyN[1] = acadoWorkspace.objValueOut[1] - acadoVariables.yN[1];\nacadoWorkspace.DyN[2] = acadoWorkspace.objValueOut[2] - acadoVariables.yN[2];\nobjVal = 0.0000000000000000e+00;\nfor (lRun1 = 0; lRun1 < 32; ++lRun1)\n{\ntmpDy[0] = + acadoWorkspace.Dy[lRun1 * 5]*acadoVariables.W[lRun1 * 25] + acadoWorkspace.Dy[lRun1 * 5 + 1]*acadoVariables.W[lRun1 * 25 + 5] + acadoWorkspace.Dy[lRun1 * 5 + 2]*acadoVariables.W[lRun1 * 25 + 10] + acadoWorkspace.Dy[lRun1 * 5 + 3]*acadoVariables.W[lRun1 * 25 + 15] + acadoWorkspace.Dy[lRun1 * 5 + 4]*acadoVariables.W[lRun1 * 25 + 20];\ntmpDy[1] = + acadoWorkspace.Dy[lRun1 * 5]*acadoVariables.W[lRun1 * 25 + 1] + acadoWorkspace.Dy[lRun1 * 5 + 1]*acadoVariables.W[lRun1 * 25 + 6] + acadoWorkspace.Dy[lRun1 * 5 + 2]*acadoVariables.W[lRun1 * 25 + 11] + acadoWorkspace.Dy[lRun1 * 5 + 3]*acadoVariables.W[lRun1 * 25 + 16] + acadoWorkspace.Dy[lRun1 * 5 + 4]*acadoVariables.W[lRun1 * 25 + 21];\ntmpDy[2] = + acadoWorkspace.Dy[lRun1 * 5]*acadoVariables.W[lRun1 * 25 + 2] + acadoWorkspace.Dy[lRun1 * 5 + 1]*acadoVariables.W[lRun1 * 25 + 7] + acadoWorkspace.Dy[lRun1 * 5 + 2]*acadoVariables.W[lRun1 * 25 + 12] + acadoWorkspace.Dy[lRun1 * 5 + 3]*acadoVariables.W[lRun1 * 25 + 17] + acadoWorkspace.Dy[lRun1 * 5 + 4]*acadoVariables.W[lRun1 * 25 + 22];\ntmpDy[3] = + acadoWorkspace.Dy[lRun1 * 5]*acadoVariables.W[lRun1 * 25 + 3] + acadoWorkspace.Dy[lRun1 * 5 + 1]*acadoVariables.W[lRun1 * 25 + 8] + acadoWorkspace.Dy[lRun1 * 5 + 2]*acadoVariables.W[lRun1 * 25 + 13] + acadoWorkspace.Dy[lRun1 * 5 + 3]*acadoVariables.W[lRun1 * 25 + 18] + acadoWorkspace.Dy[lRun1 * 5 + 4]*acadoVariables.W[lRun1 * 25 + 23];\ntmpDy[4] = + acadoWorkspace.Dy[lRun1 * 5]*acadoVariables.W[lRun1 * 25 + 4] + acadoWorkspace.Dy[lRun1 * 5 + 1]*acadoVariables.W[lRun1 * 25 + 9] + acadoWorkspace.Dy[lRun1 * 5 + 2]*acadoVariables.W[lRun1 * 25 + 14] + acadoWorkspace.Dy[lRun1 * 5 + 3]*acadoVariables.W[lRun1 * 25 + 19] + acadoWorkspace.Dy[lRun1 * 5 + 4]*acadoVariables.W[lRun1 * 25 + 24];\nobjVal += + acadoWorkspace.Dy[lRun1 * 5]*tmpDy[0] + acadoWorkspace.Dy[lRun1 * 5 + 1]*tmpDy[1] + acadoWorkspace.Dy[lRun1 * 5 + 2]*tmpDy[2] + acadoWorkspace.Dy[lRun1 * 5 + 3]*tmpDy[3] + acadoWorkspace.Dy[lRun1 * 5 + 4]*tmpDy[4];\n}\n\ntmpDyN[0] = + acadoWorkspace.DyN[0]*acadoVariables.WN[0] + acadoWorkspace.DyN[1]*acadoVariables.WN[3] + acadoWorkspace.DyN[2]*acadoVariables.WN[6];\ntmpDyN[1] = + acadoWorkspace.DyN[0]*acadoVariables.WN[1] + acadoWorkspace.DyN[1]*acadoVariables.WN[4] + acadoWorkspace.DyN[2]*acadoVariables.WN[7];\ntmpDyN[2] = + acadoWorkspace.DyN[0]*acadoVariables.WN[2] + acadoWorkspace.DyN[1]*acadoVariables.WN[5] + acadoWorkspace.DyN[2]*acadoVariables.WN[8];\nobjVal += + acadoWorkspace.DyN[0]*tmpDyN[0] + acadoWorkspace.DyN[1]*tmpDyN[1] + acadoWorkspace.DyN[2]*tmpDyN[2];\n\nobjVal *= 0.5;\nreturn objVal;\n}\n\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/libmpc_py.py",
    "content": "import os\n\nfrom cffi import FFI\nfrom common.ffi_wrapper import suffix\n\nmpc_dir = os.path.join(os.path.dirname(os.path.abspath(__file__)))\nlibmpc_fn = os.path.join(mpc_dir, \"libmpc\"+suffix())\n\nffi = FFI()\nffi.cdef(\"\"\"\nconst int MPC_N = 32;\n\ntypedef struct {\ndouble x_ego, v_ego, a_ego;\n} state_t;\n\n\ntypedef struct {\ndouble x_ego[MPC_N+1];\ndouble v_ego[MPC_N+1];\ndouble a_ego[MPC_N+1];\ndouble t[MPC_N+1];\ndouble j_ego[MPC_N];\ndouble cost;\n} log_t;\n\n\nvoid init(double xCost, double vCost, double aCost, double jerkCost, double constraintCost);\nint run_mpc(state_t * x0, log_t * solution,\n            double target_x[MPC_N+1], double target_v[MPC_N+1], double target_a[MPC_N+1],\n            double min_a, double max_a);\n\"\"\")\n\nlibmpc = ffi.dlopen(libmpc_fn)\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_mpc_lib/longitudinal_mpc.c",
    "content": "#include \"acado_common.h\"\n#include \"acado_auxiliary_functions.h\"\n#include \"common/modeldata.h\"\n\n#include <stdio.h>\n#include <math.h>\n\n#define NX          ACADO_NX  /* Number of differential state variables.  */\n#define NXA         ACADO_NXA /* Number of algebraic variables. */\n#define NU          ACADO_NU  /* Number of control inputs. */\n#define NOD         ACADO_NOD  /* Number of online data values. */\n\n#define NY          ACADO_NY  /* Number of measurements/references on nodes 0..N - 1. */\n#define NYN         ACADO_NYN /* Number of measurements/references on node N. */\n\n#define N           ACADO_N   /* Number of intervals in the horizon. */\n\nACADOvariables acadoVariables;\nACADOworkspace acadoWorkspace;\n\ntypedef struct {\n  double x_ego, v_ego, a_ego;\n} state_t;\n\n\ntypedef struct {\n  double x_ego[N+1];\n  double v_ego[N+1];\n  double a_ego[N+1];\n  double t[N+1];\n  double j_ego[N];\n  double cost;\n} log_t;\n\nvoid init(double xCost, double vCost, double aCost, double jerkCost, double constraintCost){\n  acado_initializeSolver();\n  int    i;\n  const int STEP_MULTIPLIER = 3;\n\n  /* Initialize the states and controls. */\n  for (i = 0; i < NX * (N + 1); ++i)  acadoVariables.x[ i ] = 0.0;\n  for (i = 0; i < NU * N; ++i)  acadoVariables.u[ i ] = 0.0;\n\n  /* Initialize the measurements/reference. */\n  for (i = 0; i < NY * N; ++i)  acadoVariables.y[ i ] = 0.0;\n  for (i = 0; i < NYN; ++i)  acadoVariables.yN[ i ] = 0.0;\n\n  /* MPC: initialize the current state feedback. */\n  for (i = 0; i < NX; ++i) acadoVariables.x0[ i ] = 0.0;\n  \n  // Set weights\n  for (i = 0; i < N; i++) {\n    double f = 20 * (T_IDXS[i+1] - T_IDXS[i]);\n    // Setup diagonal entries\n    acadoVariables.W[NY*NY*i + (NY+1)*0] = xCost * f;\n    acadoVariables.W[NY*NY*i + (NY+1)*1] = vCost * f;\n    acadoVariables.W[NY*NY*i + (NY+1)*2] = aCost * f;\n    acadoVariables.W[NY*NY*i + (NY+1)*3] = jerkCost * f;\n    acadoVariables.W[NY*NY*i + (NY+1)*4] = constraintCost * f;\n  }\n  acadoVariables.WN[(NYN+1)*0] = xCost * STEP_MULTIPLIER;\n  acadoVariables.WN[(NYN+1)*1] = vCost * STEP_MULTIPLIER;\n  acadoVariables.WN[(NYN+1)*2] = aCost * STEP_MULTIPLIER;\n\n}\n\n\nint run_mpc(state_t * x0, log_t * solution,\n            double target_x[N+1], double target_v[N+1], double target_a[N+1],\n            double min_a, double max_a){\n  int i;\n  for (i = 0; i < N + 1; ++i){\n    acadoVariables.od[i*NOD] = min_a;\n    acadoVariables.od[i*NOD+1] = max_a;\n  }\n  for (i = 0; i < N; i+= 1){\n    acadoVariables.y[NY*i + 0] = target_x[i];\n    acadoVariables.y[NY*i + 1] = target_v[i];\n    acadoVariables.y[NY*i + 2] = target_a[i];\n    acadoVariables.y[NY*i + 3] = 0.0;\n    acadoVariables.y[NY*i + 4] = 0.0;\n  }\n  acadoVariables.yN[0] = target_x[N];\n  acadoVariables.yN[1] = target_v[N];\n  acadoVariables.yN[2] = target_a[N];\n\n  acadoVariables.x0[0] = x0->x_ego;\n  acadoVariables.x0[1] = x0->v_ego;\n  acadoVariables.x0[2] = x0->a_ego;\n\n  acado_preparationStep();\n  acado_feedbackStep();\n\n  for (i = 0; i <= N; i++) {\n    solution->x_ego[i] = acadoVariables.x[i*NX];\n    solution->v_ego[i] = acadoVariables.x[i*NX+1];\n    solution->a_ego[i] = acadoVariables.x[i*NX+2];\n\n    if (i < N) {\n      solution->j_ego[i] = acadoVariables.u[i*NU];\n    }\n  }\n  solution->cost = acado_getObjective();\n\n  // Dont shift states here. Current solution is closer to next timestep than if\n  // we shift by 0.1 seconds.\n  return acado_getNWSR();\n}\n"
  },
  {
    "path": "selfdrive/controls/lib/longitudinal_planner.py",
    "content": "#!/usr/bin/env python3\nimport math\nimport numpy as np\nfrom common.numpy_fast import interp\n\nimport cereal.messaging as messaging\nfrom cereal import log\nfrom common.realtime import DT_MDL\nfrom common.realtime import sec_since_boot\nfrom selfdrive.modeld.constants import T_IDXS\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.controls.lib.fcw import FCWChecker\nfrom selfdrive.controls.lib.longcontrol import LongCtrlState\nfrom selfdrive.controls.lib.lead_mpc import LeadMpc\nfrom selfdrive.controls.lib.long_mpc import LongitudinalMpc\nfrom selfdrive.controls.lib.limits_long_mpc import LimitsLongitudinalMpc\nfrom selfdrive.controls.lib.drive_helpers import V_CRUISE_MAX, CONTROL_N\nfrom selfdrive.controls.lib.vision_turn_controller import VisionTurnController\nfrom selfdrive.controls.lib.speed_limit_controller import SpeedLimitController, SpeedLimitResolver\nfrom selfdrive.controls.lib.turn_speed_controller import TurnSpeedController\nfrom selfdrive.controls.lib.events import Events\nfrom selfdrive.swaglog import cloudlog\n\nLON_MPC_STEP = 0.2  # first step is 0.2s\nAWARENESS_DECEL = -0.2     # car smoothly decel at .2m/s^2 when user is distracted\nA_CRUISE_MIN = -1.2\nA_CRUISE_MAX_VALS = [1.2, 1.2, 0.8, 0.6]\nA_CRUISE_MAX_BP = [0., 15., 25., 40.]\n\n# Lookup table for turns\n_A_TOTAL_MAX_V = [1.7, 3.2]\n_A_TOTAL_MAX_BP = [20., 40.]\n\nDP_FOLLOWING_DIST = {\n  0: 1.2,\n  1: 1.5,\n  2: 1.8,\n  3: 2.2,\n}\n\nDP_ACCEL_ECO = 0\nDP_ACCEL_NORMAL = 1\nDP_ACCEL_SPORT = 2\n\n# accel profile by @arne182 modified by @wer5lcy\n_DP_CRUISE_MIN_V = [-2.0, -1.8, -1.6, -1.4, -1.2]\n_DP_CRUISE_MIN_V_ECO = [-2.0, -1.6, -1.4, -1.2, -1.0]\n_DP_CRUISE_MIN_V_SPORT = [-3.0, -2.6, -2.3, -2.0, -1.0]\n_DP_CRUISE_MIN_BP = [0.0, 5.0, 10.0, 20.0, 55.0]\n\n_DP_CRUISE_MAX_V = [1.6, 1.4, 1.0, 0.6, 0.3]\n_DP_CRUISE_MAX_V_ECO = [1.5, 1.3, 0.8, 0.4, 0.2]\n_DP_CRUISE_MAX_V_SPORT = [3.0, 3.5, 3.0, 2.0, 2.0]\n_DP_CRUISE_MAX_BP = [0., 5., 10., 20., 55.]\n\ndef dp_calc_cruise_accel_limits(v_ego, dp_profile):\n  if dp_profile == DP_ACCEL_ECO:\n    a_cruise_min = interp(v_ego, _DP_CRUISE_MIN_BP, _DP_CRUISE_MIN_V_ECO)\n    a_cruise_max = interp(v_ego, _DP_CRUISE_MAX_BP, _DP_CRUISE_MAX_V_ECO)\n  elif dp_profile == DP_ACCEL_SPORT:\n    a_cruise_min = interp(v_ego, _DP_CRUISE_MIN_BP, _DP_CRUISE_MIN_V_SPORT)\n    a_cruise_max = interp(v_ego, _DP_CRUISE_MAX_BP, _DP_CRUISE_MAX_V_SPORT)\n  else:\n    a_cruise_min = interp(v_ego, _DP_CRUISE_MIN_BP, _DP_CRUISE_MIN_V)\n    a_cruise_max = interp(v_ego, _DP_CRUISE_MAX_BP, _DP_CRUISE_MAX_V)\n  return a_cruise_min, a_cruise_max\n\ndef get_max_accel(v_ego):\n  return interp(v_ego, A_CRUISE_MAX_BP, A_CRUISE_MAX_VALS)\n\n\ndef limit_accel_in_turns(v_ego, angle_steers, a_target, CP):\n  \"\"\"\n  This function returns a limited long acceleration allowed, depending on the existing lateral acceleration\n  this should avoid accelerating when losing the target in turns\n  \"\"\"\n\n  a_total_max = interp(v_ego, _A_TOTAL_MAX_BP, _A_TOTAL_MAX_V)\n  a_y = v_ego**2 * angle_steers * CV.DEG_TO_RAD / (CP.steerRatio * CP.wheelbase)\n  a_x_allowed = math.sqrt(max(a_total_max**2 - a_y**2, 0.))\n\n  return [a_target[0], min(a_target[1], a_x_allowed)]\n\n\nclass Planner():\n  def __init__(self, CP):\n    self.CP = CP\n    self.mpcs = {}\n    self.mpcs['lead0'] = LeadMpc(0)\n    self.mpcs['lead1'] = LeadMpc(1)\n    self.mpcs['cruise'] = LongitudinalMpc()\n    self.mpcs['custom'] = LimitsLongitudinalMpc()\n\n    self.fcw = False\n    self.fcw_checker = FCWChecker()\n\n    self.v_desired = 0.0\n    self.a_desired = 0.0\n    self.longitudinalPlanSource = 'cruise'\n    self.alpha = np.exp(-DT_MDL/2.0)\n    self.lead_0 = log.ModelDataV2.LeadDataV3.new_message()\n    self.lead_1 = log.ModelDataV2.LeadDataV3.new_message()\n\n    self.v_desired_trajectory = np.zeros(CONTROL_N)\n    self.a_desired_trajectory = np.zeros(CONTROL_N)\n\n    # dp\n    self.dp_accel_profile_ctrl = False\n    self.dp_accel_profile = DP_ACCEL_ECO\n    self.dp_following_profile_ctrl = False\n    self.dp_following_profile = 3\n    self.dp_following_dist = 2.2 # default val\n    self.vision_turn_controller = VisionTurnController(CP)\n    self.speed_limit_controller = SpeedLimitController()\n    self.events = Events()\n    self.turn_speed_controller = TurnSpeedController()\n\n  def update(self, sm, CP):\n    # dp\n    self.dp_accel_profile_ctrl = sm['dragonConf'].dpAccelProfileCtrl\n    self.dp_accel_profile = sm['dragonConf'].dpAccelProfile\n    self.dp_following_profile_ctrl = sm['dragonConf'].dpFollowingProfileCtrl\n    self.dp_following_profile = sm['dragonConf'].dpFollowingProfile\n    self.dp_following_dist = DP_FOLLOWING_DIST[0 if not self.dp_following_profile_ctrl else self.dp_following_profile]\n    self.mpcs['lead0'].set_following_distance(self.dp_following_dist)\n    self.mpcs['lead1'].set_following_distance(self.dp_following_dist)\n\n    cur_time = sec_since_boot()\n    v_ego = sm['carState'].vEgo\n    a_ego = sm['carState'].aEgo\n\n    v_cruise_kph = sm['controlsState'].vCruise\n    v_cruise_kph = min(v_cruise_kph, V_CRUISE_MAX)\n    v_cruise = v_cruise_kph * CV.KPH_TO_MS\n\n    long_control_state = sm['controlsState'].longControlState\n    force_slow_decel = sm['controlsState'].forceDecel\n\n    self.lead_0 = sm['radarState'].leadOne\n    self.lead_1 = sm['radarState'].leadTwo\n\n    enabled = (long_control_state == LongCtrlState.pid) or (long_control_state == LongCtrlState.stopping)\n    if not enabled or sm['carState'].gasPressed:\n      self.v_desired = v_ego\n      self.a_desired = a_ego\n\n    # Prevent divergence, smooth in current v_ego\n    self.v_desired = self.alpha * self.v_desired + (1 - self.alpha) * v_ego\n    self.v_desired = max(0.0, self.v_desired)\n\n    # Get acceleration and active solutions for custom long mpc.\n    a_mpc, active_mpc, c_source = self.mpc_solutions(enabled, self.v_desired, self.a_desired, v_cruise, sm)\n\n\n    if not self.dp_accel_profile_ctrl:\n      accel_limits = [A_CRUISE_MIN, get_max_accel(v_ego)]\n    else:\n      accel_limits = dp_calc_cruise_accel_limits(v_cruise, self.dp_accel_profile)\n    accel_limits_turns = limit_accel_in_turns(v_ego, sm['carState'].steeringAngleDeg, accel_limits, self.CP)\n    if force_slow_decel:\n      # if required so, force a smooth deceleration\n      accel_limits_turns[1] = min(accel_limits_turns[1], AWARENESS_DECEL)\n      accel_limits_turns[0] = min(accel_limits_turns[0], accel_limits_turns[1])\n\n    # clip limits, cannot init MPC outside of bounds\n    accel_limits_turns[0] = min(accel_limits_turns[0], self.a_desired)\n    accel_limits_turns[1] = max(accel_limits_turns[1], self.a_desired)\n    self.mpcs['cruise'].set_accel_limits(accel_limits_turns[0], accel_limits_turns[1])\n\n    # ensure lower accel limit (for braking) is lower than target acc for custom controllers.\n    accel_limits = [min(accel_limits_turns[0], a_mpc['custom']), accel_limits_turns[1]]\n    self.mpcs['custom'].set_accel_limits(accel_limits[0], accel_limits[1])\n\n    next_a = np.inf\n    for key in self.mpcs:\n      self.mpcs[key].set_cur_state(self.v_desired, self.a_desired)\n      self.mpcs[key].update(sm['carState'], sm['radarState'], v_cruise, a_mpc[key], active_mpc[key])\n      # picks slowest solution from accel in ~0.2 seconds\n      if self.mpcs[key].status and active_mpc[key] and self.mpcs[key].a_solution[5] < next_a:\n        self.longitudinalPlanSource = c_source if key == 'custom' else key\n        self.v_desired_trajectory = self.mpcs[key].v_solution[:CONTROL_N]\n        self.a_desired_trajectory = self.mpcs[key].a_solution[:CONTROL_N]\n        self.j_desired_trajectory = self.mpcs[key].j_solution[:CONTROL_N]\n        next_a = self.mpcs[key].a_solution[5]\n\n    # determine fcw\n    if self.mpcs['lead0'].new_lead:\n      self.fcw_checker.reset_lead(cur_time)\n    blinkers = sm['carState'].leftBlinker or sm['carState'].rightBlinker\n    self.fcw = self.fcw_checker.update(self.mpcs['lead0'].mpc_solution, cur_time,\n                                       sm['controlsState'].active,\n                                       v_ego, sm['carState'].aEgo,\n                                       self.lead_1.dRel, self.lead_1.vLead, self.lead_1.aLeadK,\n                                       self.lead_1.yRel, self.lead_1.vLat,\n                                       self.lead_1.fcw, blinkers) and not sm['carState'].brakePressed\n    if self.fcw:\n      cloudlog.info(\"FCW triggered %s\", self.fcw_checker.counters)\n\n    # Interpolate 0.05 seconds and save as starting point for next iteration\n    a_prev = self.a_desired\n    self.a_desired = float(interp(DT_MDL, T_IDXS[:CONTROL_N], self.a_desired_trajectory))\n    self.v_desired = self.v_desired + DT_MDL * (self.a_desired + a_prev)/2.0\n\n  def publish(self, sm, pm):\n    plan_send = messaging.new_message('longitudinalPlan')\n\n    plan_send.valid = sm.all_alive_and_valid(service_list=['carState', 'controlsState'])\n\n    longitudinalPlan = plan_send.longitudinalPlan\n    longitudinalPlan.modelMonoTime = sm.logMonoTime['modelV2']\n    longitudinalPlan.processingDelay = (plan_send.logMonoTime / 1e9) - sm.logMonoTime['modelV2']\n\n    longitudinalPlan.speeds = [float(x) for x in self.v_desired_trajectory]\n    longitudinalPlan.accels = [float(x) for x in self.a_desired_trajectory]\n    longitudinalPlan.jerks = [float(x) for x in self.j_desired_trajectory]\n\n    longitudinalPlan.hasLead = self.mpcs['lead0'].status\n    longitudinalPlan.longitudinalPlanSource = self.longitudinalPlanSource\n    longitudinalPlan.fcw = self.fcw\n\n    longitudinalPlan.visionTurnControllerState = self.vision_turn_controller.state\n    longitudinalPlan.visionTurnSpeed = float(self.vision_turn_controller.v_turn)\n\n    longitudinalPlan.speedLimitControlState = self.speed_limit_controller.state\n    longitudinalPlan.speedLimit = float(self.speed_limit_controller.speed_limit)\n    longitudinalPlan.speedLimitOffset = float(self.speed_limit_controller.speed_limit_offset)\n    longitudinalPlan.distToSpeedLimit = float(self.speed_limit_controller.distance)\n    longitudinalPlan.isMapSpeedLimit = bool(self.speed_limit_controller.source == SpeedLimitResolver.Source.map_data)\n    longitudinalPlan.eventsDEPRECATED = self.events.to_msg()\n\n    longitudinalPlan.turnSpeedControlState = self.turn_speed_controller.state\n    longitudinalPlan.turnSpeed = float(self.turn_speed_controller.speed_limit)\n    longitudinalPlan.distToTurn = float(self.turn_speed_controller.distance)\n    longitudinalPlan.turnSign = int(self.turn_speed_controller.turn_sign)\n\n    pm.send('longitudinalPlan', plan_send)\n\n  def mpc_solutions(self, enabled, v_ego, a_ego, v_cruise, sm):\n    # Update controllers\n    self.vision_turn_controller.update(enabled, v_ego, a_ego, v_cruise, sm)\n    self.events = Events()\n    self.speed_limit_controller.update(enabled, v_ego, a_ego, sm, v_cruise, self.events)\n    self.turn_speed_controller.update(enabled, v_ego, a_ego, sm)\n\n    # Pick solution with lowest acceleration target.\n    a_solutions = {None: float(\"inf\")}\n\n    if self.vision_turn_controller.is_active:\n      a_solutions['turn'] = self.vision_turn_controller.a_target\n\n    if self.speed_limit_controller.is_active:\n      a_solutions['limit'] = self.speed_limit_controller.a_target\n\n    if self.turn_speed_controller.is_active:\n      a_solutions['turnlimit'] = self.turn_speed_controller.a_target\n\n    source = min(a_solutions, key=a_solutions.get)\n\n    a_sol = {\n      'cruise': a_ego,  # Irrelevant\n      'lead0': a_ego,   # Irrelevant\n      'lead1': a_ego,   # Irrelevant\n      'custom': 0. if source is None else a_solutions[source],\n    }\n\n    active_sol = {\n      'cruise': True,  # Irrelevant\n      'lead0': True,   # Irrelevant\n      'lead1': True,   # Irrelevant\n      'custom': source is not None,\n    }\n\n    return a_sol, active_sol, source\n"
  },
  {
    "path": "selfdrive/controls/lib/pid.py",
    "content": "import numpy as np\nfrom numbers import Number\n\nfrom common.numpy_fast import clip, interp\n\ndef apply_deadzone(error, deadzone):\n  if error > deadzone:\n    error -= deadzone\n  elif error < - deadzone:\n    error += deadzone\n  else:\n    error = 0.\n  return error\n\nclass PIController():\n  def __init__(self, k_p, k_i, k_f=1., pos_limit=None, neg_limit=None, rate=100, sat_limit=0.8):\n    self._k_p = k_p  # proportional gain\n    self._k_i = k_i  # integral gain\n    self.k_f = k_f   # feedforward gain\n    if isinstance(self._k_p, Number):\n      self._k_p = [[0], [self._k_p]]\n    if isinstance(self._k_i, Number):\n      self._k_i = [[0], [self._k_i]]\n\n    self.pos_limit = pos_limit\n    self.neg_limit = neg_limit\n\n    self.sat_count_rate = 1.0 / rate\n    self.i_unwind_rate = 0.3 / rate\n    self.i_rate = 1.0 / rate\n    self.sat_limit = sat_limit\n\n    self.reset()\n\n  @property\n  def k_p(self):\n    return interp(self.speed, self._k_p[0], self._k_p[1])\n\n  @property\n  def k_i(self):\n    return interp(self.speed, self._k_i[0], self._k_i[1])\n\n  def _check_saturation(self, control, check_saturation, error):\n    saturated = (control < self.neg_limit) or (control > self.pos_limit)\n\n    if saturated and check_saturation and abs(error) > 0.1:\n      self.sat_count += self.sat_count_rate\n    else:\n      self.sat_count -= self.sat_count_rate\n\n    self.sat_count = clip(self.sat_count, 0.0, 1.0)\n\n    return self.sat_count > self.sat_limit\n\n  def reset(self):\n    self.p = 0.0\n    self.i = 0.0\n    self.f = 0.0\n    self.sat_count = 0.0\n    self.saturated = False\n    self.control = 0\n\n  def update(self, setpoint, measurement, speed=0.0, check_saturation=True, override=False, feedforward=0., deadzone=0., freeze_integrator=False):\n    self.speed = speed\n\n    error = float(apply_deadzone(setpoint - measurement, deadzone))\n    self.p = error * self.k_p\n    self.f = feedforward * self.k_f\n\n    if override:\n      self.i -= self.i_unwind_rate * float(np.sign(self.i))\n    else:\n      i = self.i + error * self.k_i * self.i_rate\n      control = self.p + self.f + i\n\n      # Update when changing i will move the control away from the limits\n      # or when i will move towards the sign of the error\n      if ((error >= 0 and (control <= self.pos_limit or i < 0.0)) or\n          (error <= 0 and (control >= self.neg_limit or i > 0.0))) and \\\n         not freeze_integrator:\n        self.i = i\n\n    control = self.p + self.f + self.i\n    self.saturated = self._check_saturation(control, check_saturation, error)\n\n    self.control = clip(control, self.neg_limit, self.pos_limit)\n    return self.control\n"
  },
  {
    "path": "selfdrive/controls/lib/radar_helpers.py",
    "content": "from common.numpy_fast import mean\nfrom common.kalman.simple_kalman import KF1D\nfrom selfdrive.config import RADAR_TO_CAMERA\n\n\n# the longer lead decels, the more likely it will keep decelerating\n# TODO is this a good default?\n_LEAD_ACCEL_TAU = 1.5\n\n# radar tracks\nSPEED, ACCEL = 0, 1   # Kalman filter states enum\n\n# stationary qualification parameters\nv_ego_stationary = 4.   # no stationary object flag below this speed\n\n\nclass Track():\n  def __init__(self, v_lead, kalman_params):\n    self.cnt = 0\n    self.aLeadTau = _LEAD_ACCEL_TAU\n    self.K_A = kalman_params.A\n    self.K_C = kalman_params.C\n    self.K_K = kalman_params.K\n    self.kf = KF1D([[v_lead], [0.0]], self.K_A, self.K_C, self.K_K)\n\n  def update(self, d_rel, y_rel, v_rel, v_lead, measured):\n    # relative values, copy\n    self.dRel = d_rel   # LONG_DIST\n    self.yRel = y_rel   # -LAT_DIST\n    self.vRel = v_rel   # REL_SPEED\n    self.vLead = v_lead\n    self.measured = measured   # measured or estimate\n\n    # computed velocity and accelerations\n    if self.cnt > 0:\n      self.kf.update(self.vLead)\n\n    self.vLeadK = float(self.kf.x[SPEED][0])\n    self.aLeadK = float(self.kf.x[ACCEL][0])\n\n    # Learn if constant acceleration\n    if abs(self.aLeadK) < 0.5:\n      self.aLeadTau = _LEAD_ACCEL_TAU\n    else:\n      self.aLeadTau *= 0.9\n\n    self.cnt += 1\n\n  def get_key_for_cluster(self):\n    # Weigh y higher since radar is inaccurate in this dimension\n    return [self.dRel, self.yRel*2, self.vRel]\n\n  def reset_a_lead(self, aLeadK, aLeadTau):\n    self.kf = KF1D([[self.vLead], [aLeadK]], self.K_A, self.K_C, self.K_K)\n    self.aLeadK = aLeadK\n    self.aLeadTau = aLeadTau\n\n\nclass Cluster():\n  def __init__(self):\n    self.tracks = set()\n\n  def add(self, t):\n    # add the first track\n    self.tracks.add(t)\n\n  # TODO: make generic\n  @property\n  def dRel(self):\n    return mean([t.dRel for t in self.tracks])\n\n  @property\n  def yRel(self):\n    return mean([t.yRel for t in self.tracks])\n\n  @property\n  def vRel(self):\n    return mean([t.vRel for t in self.tracks])\n\n  @property\n  def aRel(self):\n    return mean([t.aRel for t in self.tracks])\n\n  @property\n  def vLead(self):\n    return mean([t.vLead for t in self.tracks])\n\n  @property\n  def dPath(self):\n    return mean([t.dPath for t in self.tracks])\n\n  @property\n  def vLat(self):\n    return mean([t.vLat for t in self.tracks])\n\n  @property\n  def vLeadK(self):\n    return mean([t.vLeadK for t in self.tracks])\n\n  @property\n  def aLeadK(self):\n    if all(t.cnt <= 1 for t in self.tracks):\n      return 0.\n    else:\n      return mean([t.aLeadK for t in self.tracks if t.cnt > 1])\n\n  @property\n  def aLeadTau(self):\n    if all(t.cnt <= 1 for t in self.tracks):\n      return _LEAD_ACCEL_TAU\n    else:\n      return mean([t.aLeadTau for t in self.tracks if t.cnt > 1])\n\n  @property\n  def measured(self):\n    return any(t.measured for t in self.tracks)\n\n  def get_RadarState(self, model_prob=0.0):\n    return {\n      \"dRel\": float(self.dRel),\n      \"yRel\": float(self.yRel),\n      \"vRel\": float(self.vRel),\n      \"vLead\": float(self.vLead),\n      \"vLeadK\": float(self.vLeadK),\n      \"aLeadK\": float(self.aLeadK),\n      \"status\": True,\n      \"fcw\": self.is_potential_fcw(model_prob),\n      \"modelProb\": model_prob,\n      \"radar\": True,\n      \"aLeadTau\": float(self.aLeadTau)\n    }\n\n  def get_RadarState_from_vision(self, lead_msg, v_ego):\n    return {\n      \"dRel\": float(lead_msg.x[0] - RADAR_TO_CAMERA),\n      \"yRel\": float(-lead_msg.y[0]),\n      \"vRel\": float(lead_msg.v[0] - v_ego),\n      \"vLead\": float(lead_msg.v[0]),\n      \"vLeadK\": float(lead_msg.v[0]),\n      \"aLeadK\": float(0),\n      \"aLeadTau\": _LEAD_ACCEL_TAU,\n      \"fcw\": False,\n      \"modelProb\": float(lead_msg.prob),\n      \"radar\": False,\n      \"status\": True\n    }\n\n  def __str__(self):\n    ret = \"x: %4.1f  y: %4.1f  v: %4.1f  a: %4.1f\" % (self.dRel, self.yRel, self.vRel, self.aLeadK)\n    return ret\n\n  def potential_low_speed_lead(self, v_ego):\n    # stop for stuff in front of you and low speed, even without model confirmation\n    return abs(self.yRel) < 1.5 and (v_ego < v_ego_stationary) and self.dRel < 25\n\n  def is_potential_fcw(self, model_prob):\n    return model_prob > .9\n"
  },
  {
    "path": "selfdrive/controls/lib/speed_limit_controller.py",
    "content": "import numpy as np\nimport time\nfrom common.numpy_fast import interp\nfrom enum import IntEnum\nfrom cereal import log, car\nfrom common.params import Params\nfrom common.realtime import sec_since_boot\nfrom selfdrive.controls.lib.drive_helpers import LIMIT_ADAPT_ACC, LIMIT_MIN_ACC, LIMIT_MAX_ACC, LIMIT_SPEED_OFFSET_TH, \\\n  LIMIT_MAX_MAP_DATA_AGE, CONTROL_N\nfrom selfdrive.controls.lib.events import Events\nfrom selfdrive.modeld.constants import T_IDXS\n\n\n_PARAMS_UPDATE_PERIOD = 2.  # secs. Time between parameter updates.\n_TEMP_INACTIVE_GUARD_PERIOD = 1.  # secs. Time to wait after activation before considering temp deactivation signal.\n\n# Lookup table for speed limit percent offset depending on speed.\n_LIMIT_PERC_OFFSET_V = [0.0, 0.1, 0.125,  0.2, 0.21, 0.23]  # 25, 33, 45, 60, 67, 70 mph\n_LIMIT_PERC_OFFSET_BP = [11.0, 13.4, 20.1, 22.3, 24.58, 29.0]  # 25, 30, 40 50, 55, 65 mph\n\n#_LIMIT_PERC_OFFSET_V = [0.28, 0.038]  # 55, 105, 135 km/h 96, 129\n#_LIMIT_PERC_OFFSET_BP = [13.9, 36.1]  # 50, 100, 130 km/h\n\nSpeedLimitControlState = log.LongitudinalPlan.SpeedLimitControlState\nEventName = car.CarEvent.EventName\n\n_DEBUG = False\n\n\ndef _debug(msg):\n  if not _DEBUG:\n    return\n  print(msg)\n\n\ndef _description_for_state(speed_limit_control_state):\n  if speed_limit_control_state == SpeedLimitControlState.inactive:\n    return 'INACTIVE'\n  if speed_limit_control_state == SpeedLimitControlState.tempInactive:\n    return 'TEMP_INACTIVE'\n  if speed_limit_control_state == SpeedLimitControlState.adapting:\n    return 'ADAPTING'\n  if speed_limit_control_state == SpeedLimitControlState.active:\n    return 'ACTIVE'\n\n\nclass SpeedLimitResolver():\n  class Source(IntEnum):\n    none = 0\n    car_state = 1\n    map_data = 2\n\n  class Policy(IntEnum):\n    car_state_only = 0\n    map_data_only = 1\n    car_state_priority = 2\n    map_data_priority = 3\n    combined = 4\n\n  def __init__(self, policy=Policy.map_data_priority):\n    self._limit_solutions = {}  # Store for speed limit solutions from different sources\n    self._distance_solutions = {}  # Store for distance to current speed limit start for different sources\n    self._v_ego = 0.\n    self._current_speed_limit = 0.\n    self._policy = policy\n    self._next_speed_limit_prev = 0.\n    self.speed_limit = 0.\n    self.distance = 0.\n    self.source = SpeedLimitResolver.Source.none\n\n  def resolve(self, v_ego, current_speed_limit, sm):\n    self._v_ego = v_ego\n    self._current_speed_limit = current_speed_limit\n    self._sm = sm\n\n    self._get_from_car_state()\n    self._get_from_map_data()\n    self._consolidate()\n\n    return self.speed_limit, self.distance, self.source\n\n  def _get_from_car_state(self):\n    self._limit_solutions[SpeedLimitResolver.Source.car_state] = self._sm['carState'].cruiseState.speedLimit\n    self._distance_solutions[SpeedLimitResolver.Source.car_state] = 0.\n\n  def _get_from_map_data(self):\n    # Ignore if no live map data\n    sock = 'liveMapData'\n    if self._sm.logMonoTime[sock] is None:\n      self._limit_solutions[SpeedLimitResolver.Source.map_data] = 0.\n      self._distance_solutions[SpeedLimitResolver.Source.map_data] = 0.\n      _debug('SL: No map data for speed limit')\n      return\n\n    # Load limits from map_data\n    map_data = self._sm[sock]\n    speed_limit = map_data.speedLimit if map_data.speedLimitValid else 0.\n    next_speed_limit = map_data.speedLimitAhead if map_data.speedLimitAheadValid else 0.\n\n    # Calculate the age of the gps fix. Ignore if too old.\n    gps_fix_age = time.time() - map_data.lastGpsTimestamp * 1e-3\n    if gps_fix_age > LIMIT_MAX_MAP_DATA_AGE:\n      self._limit_solutions[SpeedLimitResolver.Source.map_data] = 0.\n      self._distance_solutions[SpeedLimitResolver.Source.map_data] = 0.\n      _debug(f'SL: Ignoring map data as is too old. Age: {gps_fix_age}')\n      return\n\n    # When we have no ahead speed limit to consider or it is greater than current speed limit\n    # or car has stopped, then provide current value and reset tracking.\n    if next_speed_limit == 0. or self._v_ego <= 0. or next_speed_limit > self._current_speed_limit:\n      self._limit_solutions[SpeedLimitResolver.Source.map_data] = speed_limit\n      self._distance_solutions[SpeedLimitResolver.Source.map_data] = 0.\n      self._next_speed_limit_prev = 0.\n      return\n\n    # Calculate the actual distance to the speed limit ahead corrected by gps_fix_age\n    distance_since_fix = self._v_ego * gps_fix_age\n    distance_to_speed_limit_ahead = max(0., map_data.speedLimitAheadDistance - distance_since_fix)\n\n    # When we have a next_speed_limit value that has not changed from a provided next speed limit value\n    # in previous resolutions, we keep providing it.\n    if next_speed_limit == self._next_speed_limit_prev:\n      self._limit_solutions[SpeedLimitResolver.Source.map_data] = next_speed_limit\n      self._distance_solutions[SpeedLimitResolver.Source.map_data] = distance_to_speed_limit_ahead\n      return\n\n    # Reset tracking\n    self._next_speed_limit_prev = 0.\n\n    # Calculated the time needed to adapt to the new limit and the corresponding distance.\n    adapt_time = (next_speed_limit - self._v_ego) / LIMIT_ADAPT_ACC\n    adapt_distance = self._v_ego * adapt_time + 0.5 * LIMIT_ADAPT_ACC * adapt_time**2\n\n    # When we detect we are close enough, we provide the next limit value and track it.\n    if distance_to_speed_limit_ahead <= adapt_distance:\n      self._limit_solutions[SpeedLimitResolver.Source.map_data] = next_speed_limit\n      self._distance_solutions[SpeedLimitResolver.Source.map_data] = distance_to_speed_limit_ahead\n      self._next_speed_limit_prev = next_speed_limit\n      return\n\n    # Otherwise we just provide the map data speed limit.\n    self.distance_to_map_speed_limit = 0.\n    self._limit_solutions[SpeedLimitResolver.Source.map_data] = speed_limit\n    self._distance_solutions[SpeedLimitResolver.Source.map_data] = 0.\n\n  def _consolidate(self):\n    limits = np.array([], dtype=float)\n    distances = np.array([], dtype=float)\n    sources = np.array([], dtype=int)\n\n    if self._policy == SpeedLimitResolver.Policy.car_state_only or \\\n       self._policy == SpeedLimitResolver.Policy.car_state_priority or \\\n       self._policy == SpeedLimitResolver.Policy.combined:\n      limits = np.append(limits, self._limit_solutions[SpeedLimitResolver.Source.car_state])\n      distances = np.append(distances, self._distance_solutions[SpeedLimitResolver.Source.car_state])\n      sources = np.append(sources, SpeedLimitResolver.Source.car_state.value)\n\n    if self._policy == SpeedLimitResolver.Policy.map_data_only or \\\n       self._policy == SpeedLimitResolver.Policy.map_data_priority or \\\n       self._policy == SpeedLimitResolver.Policy.combined:\n      limits = np.append(limits, self._limit_solutions[SpeedLimitResolver.Source.map_data])\n      distances = np.append(distances, self._distance_solutions[SpeedLimitResolver.Source.map_data])\n      sources = np.append(sources, SpeedLimitResolver.Source.map_data.value)\n\n    if np.amax(limits) == 0.:\n      if self._policy == SpeedLimitResolver.Policy.car_state_priority:\n        limits = np.append(limits, self._limit_solutions[SpeedLimitResolver.Source.map_data])\n        distances = np.append(distances, self._distance_solutions[SpeedLimitResolver.Source.map_data])\n        sources = np.append(sources, SpeedLimitResolver.Source.map_data.value)\n\n      elif self._policy == SpeedLimitResolver.Policy.map_data_priority:\n        limits = np.append(limits, self._limit_solutions[SpeedLimitResolver.Source.car_state])\n        distances = np.append(distances, self._distance_solutions[SpeedLimitResolver.Source.car_state])\n        sources = np.append(sources, SpeedLimitResolver.Source.car_state.value)\n\n    # Get all non-zero values and set the minimum if any, otherwise 0.\n    mask = limits > 0.\n    limits = limits[mask]\n    distances = distances[mask]\n    sources = sources[mask]\n\n    if len(limits) > 0:\n      min_idx = np.argmin(limits)\n      self.speed_limit = limits[min_idx]\n      self.distance = distances[min_idx]\n      self.source = SpeedLimitResolver.Source(sources[min_idx])\n    else:\n      self.speed_limit = 0.\n      self.distance = 0.\n      self.source = SpeedLimitResolver.Source.none\n\n    _debug(f'SL: *** Speed Limit set: {self.speed_limit}, distance: {self.distance}, source: {self.source}')\n\n\nclass SpeedLimitController():\n  def __init__(self):\n    self._params = Params()\n    self._resolver = SpeedLimitResolver()\n    self._last_params_update = 0.0\n    self._last_op_enabled_time = 0.0\n    self._is_metric = self._params.get_bool(\"IsMetric\")\n    self._is_enabled = self._params.get_bool(\"SpeedLimitControl\")\n    self._offset_enabled = self._params.get_bool(\"SpeedLimitPercOffset\")\n    self._op_enabled = False\n    self._op_enabled_prev = False\n    self._v_ego = 0.\n    self._a_ego = 0.\n    self._v_offset = 0.\n    self._v_cruise_setpoint = 0.\n    self._v_cruise_setpoint_prev = 0.\n    self._v_cruise_setpoint_changed = False\n    self._speed_limit = 0.\n    self._speed_limit_prev = 0.\n    self._speed_limit_changed = False\n    self._distance = 0.\n    self._source = SpeedLimitResolver.Source.none\n    self._state = SpeedLimitControlState.inactive\n    self._state_prev = SpeedLimitControlState.inactive\n    self._gas_pressed = False\n    self._a_target = 0.\n\n  @property\n  def a_target(self):\n    return self._a_target if self.is_active else self._a_ego\n\n  @property\n  def state(self):\n    return self._state\n\n  @state.setter\n  def state(self, value):\n    if value != self._state:\n      _debug(f'Speed Limit Controller state: {_description_for_state(value)}')\n\n      if value == SpeedLimitControlState.tempInactive:\n        # Reset previous speed limit to current value as to prevent going out of tempInactive in\n        # a single cycle when the speed limit changes at the same time the user has temporarily deactivate it.\n        self._speed_limit_prev = self._speed_limit\n\n    self._state = value\n\n  @property\n  def is_active(self):\n    return self.state > SpeedLimitControlState.tempInactive\n\n  @property\n  def speed_limit_offseted(self):\n    return self._speed_limit + self.speed_limit_offset\n\n  @property\n  def speed_limit_offset(self):\n    if self._offset_enabled:\n      return interp(self._speed_limit, _LIMIT_PERC_OFFSET_BP, _LIMIT_PERC_OFFSET_V) * self._speed_limit\n    return 0.\n\n  @property\n  def speed_limit(self):\n    return self._speed_limit\n\n  @property\n  def distance(self):\n    return self._distance\n\n  @property\n  def source(self):\n    return self._source\n\n  def _update_params(self):\n    time = sec_since_boot()\n    if time > self._last_params_update + _PARAMS_UPDATE_PERIOD:\n      self._is_enabled = self._params.get_bool(\"SpeedLimitControl\")\n      self._offset_enabled = self._params.get_bool(\"SpeedLimitPercOffset\")\n      _debug(f'Updated Speed limit params. enabled: {self._is_enabled}, with offset: {self._offset_enabled}')\n      self._last_params_update = time\n\n  def _update_calculations(self):\n    # Update current velocity offset (error)\n    self._v_offset = self.speed_limit_offseted - self._v_ego\n\n    # Track the time op becomes active to prevent going to tempInactive right away after\n    # op enabling since controlsd will change the cruise speed every time on enabling and this will\n    # cause a temp inactive transition if the controller is updated before controlsd sets actual cruise\n    # speed.\n    if not self._op_enabled_prev and self._op_enabled:\n      self._last_op_enabled_time = sec_since_boot()\n\n    # Update change tracking variables\n    self._speed_limit_changed = self._speed_limit != self._speed_limit_prev\n    self._v_cruise_setpoint_changed = self._v_cruise_setpoint != self._v_cruise_setpoint_prev\n    self._speed_limit_prev = self._speed_limit\n    self._v_cruise_setpoint_prev = self._v_cruise_setpoint\n    self._op_enabled_prev = self._op_enabled\n\n  def _state_transition(self):\n    self._state_prev = self._state\n\n    # In any case, if op is disabled, or speed limit control is disabled\n    # or the reported speed limit is 0 or gas is pressed, deactivate.\n    if not self._op_enabled or not self._is_enabled or self._speed_limit == 0 or self._gas_pressed:\n      self.state = SpeedLimitControlState.inactive\n      return\n\n    # In any case, we deactivate the speed limit controller temporarily if the user changes the cruise speed.\n    # Ignore if a minimum ammount of time has not passed since activation. This is to prevent temp inactivations\n    # due to controlsd logic changing cruise setpoint when going active.\n    if self._v_cruise_setpoint_changed and \\\n       sec_since_boot() > (self._last_op_enabled_time + _TEMP_INACTIVE_GUARD_PERIOD):\n      self.state = SpeedLimitControlState.tempInactive\n      return\n\n    # inactive\n    if self.state == SpeedLimitControlState.inactive:\n      # If the limit speed offset is negative (i.e. reduce speed) and lower than threshold\n      # we go to adapting state to quickly reduce speed, otherwise we go directly to active\n      if self._v_offset < LIMIT_SPEED_OFFSET_TH:\n        self.state = SpeedLimitControlState.adapting\n      else:\n        self.state = SpeedLimitControlState.active\n    # tempInactive\n    elif self.state == SpeedLimitControlState.tempInactive:\n      # if speed limit changes, transition to inactive,\n      # proper active state will be set on next iteration.\n      if self._speed_limit_changed:\n        self.state = SpeedLimitControlState.inactive\n    # adapting\n    elif self.state == SpeedLimitControlState.adapting:\n      # Go to active once the speed offset is over threshold.\n      if self._v_offset >= LIMIT_SPEED_OFFSET_TH:\n        self.state = SpeedLimitControlState.active\n    # active\n    elif self.state == SpeedLimitControlState.active:\n      # Go to adapting if the speed offset goes below threshold.\n      if self._v_offset < LIMIT_SPEED_OFFSET_TH:\n        self.state = SpeedLimitControlState.adapting\n\n  def _update_solution(self):\n    # inactive or tempInactive state\n    if self.state <= SpeedLimitControlState.tempInactive:\n      # Preserve current values\n      a_target = self._a_ego\n    # adapting\n    elif self.state == SpeedLimitControlState.adapting:\n      # When adapting we target to achieve the speed limit on the distance if not there yet,\n      # otherwise try to keep the speed constant around the control time horizon.\n      if self.distance > 0:\n        a_target = (self.speed_limit_offseted**2 - self._v_ego**2) / (2. * self.distance)\n      else:\n        a_target = self._v_offset / T_IDXS[CONTROL_N]\n    # active\n    elif self.state == SpeedLimitControlState.active:\n      # When active we are trying to keep the speed constant around the control time horizon.\n      a_target = self._v_offset / T_IDXS[CONTROL_N]\n\n    # Keep solution limited.\n    self._a_target = np.clip(a_target, LIMIT_MIN_ACC, LIMIT_MAX_ACC)\n\n  def _update_events(self, events):\n    if not self.is_active:\n      # no event while inactive\n      return\n\n    if self._state_prev <= SpeedLimitControlState.tempInactive:\n      events.add(EventName.speedLimitActive)\n    elif self._speed_limit_changed != 0:\n      events.add(EventName.speedLimitValueChange)\n\n  def update(self, enabled, v_ego, a_ego, sm, v_cruise_setpoint, events=Events()):\n    self._op_enabled = enabled\n    self._v_ego = v_ego\n    self._a_ego = a_ego\n    self._v_cruise_setpoint = v_cruise_setpoint\n    self._gas_pressed = sm['carState'].gasPressed\n\n    self._speed_limit, self._distance, self._source = self._resolver.resolve(v_ego, self.speed_limit, sm)\n\n    self._update_params()\n    self._update_calculations()\n    self._state_transition()\n    self._update_solution()\n    self._update_events(events)\n"
  },
  {
    "path": "selfdrive/controls/lib/turn_speed_controller.py",
    "content": "import numpy as np\nimport time\nfrom common.params import Params\nfrom cereal import log\nfrom common.realtime import sec_since_boot\nfrom selfdrive.controls.lib.drive_helpers import LIMIT_ADAPT_ACC, LIMIT_MIN_SPEED, LIMIT_MAX_MAP_DATA_AGE, \\\n  LIMIT_SPEED_OFFSET_TH, CONTROL_N, LIMIT_MIN_ACC, LIMIT_MAX_ACC\nfrom selfdrive.modeld.constants import T_IDXS\n\n\n_ACTIVE_LIMIT_MIN_ACC = -0.5  # m/s^2 Maximum deceleration allowed while active.\n_ACTIVE_LIMIT_MAX_ACC = 0.5   # m/s^2 Maximum acelration allowed while active.\n\n\n_DEBUG = False\n\nTurnSpeedControlState = log.LongitudinalPlan.SpeedLimitControlState\n\n\ndef _debug(msg):\n  if not _DEBUG:\n    return\n  print(msg)\n\n\ndef _description_for_state(turn_speed_control_state):\n  if turn_speed_control_state == TurnSpeedControlState.inactive:\n    return 'INACTIVE'\n  if turn_speed_control_state == TurnSpeedControlState.tempInactive:\n    return 'TEMP INACTIVE'\n  if turn_speed_control_state == TurnSpeedControlState.adapting:\n    return 'ADAPTING'\n  if turn_speed_control_state == TurnSpeedControlState.active:\n    return 'ACTIVE'\n\n\nclass TurnSpeedController():\n  def __init__(self):\n    self._params = Params()\n    self._last_params_update = 0.\n    self._is_enabled = self._params.get_bool(\"TurnSpeedControl\")\n    self._op_enabled = False\n    self._v_ego = 0.\n    self._a_ego = 0.\n    self._v_cruise_setpoint = 0.\n\n    self._v_offset = 0.\n    self._speed_limit = 0.\n    self._speed_limit_temp_inactive = 0.\n    self._distance = 0.\n    self._turn_sign = 0\n    self._state = TurnSpeedControlState.inactive\n\n    self._next_speed_limit_prev = 0.\n\n    self._a_target = 0.\n\n  @property\n  def a_target(self):\n    return self._a_target if self.is_active else self._a_ego\n\n  @property\n  def state(self):\n    return self._state\n\n  @state.setter\n  def state(self, value):\n    if value != self._state:\n      _debug(f'Turn Speed Controller state: {_description_for_state(value)}')\n\n      if value == TurnSpeedControlState.adapting:\n        _debug('TSC: Enteriing Adapting as speed offset is below threshold')\n        _debug(f'_v_offset: {self._v_offset * 3.6}\\nspeed_limit: {self.speed_limit * 3.6}')\n        _debug(f'_v_ego: {self._v_ego * 3.6}\\ndistance: {self.distance}')\n\n      if value == TurnSpeedControlState.tempInactive:\n        # Track the speed limit value when controller was set to temp inactive.\n        self._speed_limit_temp_inactive = self._speed_limit\n\n    self._state = value\n\n  @property\n  def is_active(self):\n    return self.state > TurnSpeedControlState.tempInactive\n\n  @property\n  def speed_limit(self):\n    return max(self._speed_limit, LIMIT_MIN_SPEED) if self._speed_limit > 0. else 0.\n\n  @property\n  def distance(self):\n    return max(self._distance, 0.)\n\n  @property\n  def turn_sign(self):\n    return self._turn_sign\n\n  def _get_limit_from_map_data(self, sm):\n    \"\"\"Provides the speed limit, distance and turn sign to it for turns based on map data.\n    \"\"\"\n    # Ignore if no live map data\n    sock = 'liveMapData'\n    if sm.logMonoTime[sock] is None:\n      _debug('TS: No map data for turn speed limit')\n      return 0., 0., 0\n\n    # Load map_data and initialize\n    map_data = sm[sock]\n    speed_limit = 0.\n\n    # Calculate the age of the gps fix. Ignore if too old.\n    gps_fix_age = time.time() - map_data.lastGpsTimestamp * 1e-3\n    if gps_fix_age > LIMIT_MAX_MAP_DATA_AGE:\n      _debug(f'TS: Ignoring map data as is too old. Age: {gps_fix_age}')\n      return 0., 0., 0\n\n    # Load turn ahead sections info from map_data with distances corrected by gps_fix_age\n    distance_since_fix = self._v_ego * gps_fix_age\n    distances_to_sections_ahead = np.maximum(0., np.array(map_data.turnSpeedLimitsAheadDistances) - distance_since_fix)\n    speed_limit_in_sections_ahead = map_data.turnSpeedLimitsAhead\n    turn_signs_in_sections_ahead = map_data.turnSpeedLimitsAheadSigns\n\n    # Ensure current speed limit is considered only if we are inside the section.\n    if map_data.turnSpeedLimitValid and self._v_ego > 0.:\n      speed_limit_end_time = (map_data.turnSpeedLimitEndDistance / self._v_ego) - gps_fix_age\n      if speed_limit_end_time > 0.:\n        speed_limit = map_data.turnSpeedLimit\n\n    # When we have no ahead speed limit to consider or all are greater than current speed limit\n    # or car has stopped, then provide current value and reset tracking.\n    turn_sign = map_data.turnSpeedLimitSign if map_data.turnSpeedLimitValid else 0\n    if len(speed_limit_in_sections_ahead) == 0 or self._v_ego <= 0. or \\\n       (speed_limit > 0 and np.amin(speed_limit_in_sections_ahead) > speed_limit):\n      self._next_speed_limit_prev = 0.\n      return speed_limit, 0., turn_sign\n\n    # Calculated the time needed to adapt to the limits ahead and the corresponding distances.\n    adapt_times = (np.maximum(speed_limit_in_sections_ahead, LIMIT_MIN_SPEED) - self._v_ego) / LIMIT_ADAPT_ACC\n    adapt_distances = self._v_ego * adapt_times + 0.5 * LIMIT_ADAPT_ACC * adapt_times**2\n    distance_gaps = distances_to_sections_ahead - adapt_distances\n\n    # We select as next speed limit, the one that have the lowest distance gap.\n    next_idx = np.argmin(distance_gaps)\n    next_speed_limit = speed_limit_in_sections_ahead[next_idx]\n    distance_to_section_ahead = distances_to_sections_ahead[next_idx]\n    next_turn_sign = turn_signs_in_sections_ahead[next_idx]\n    distance_gap = distance_gaps[next_idx]\n\n    # When we have a next_speed_limit value that has not changed from a provided next speed limit value\n    # in previous resolutions, we keep providing it along with the udpated distance to it.\n    if next_speed_limit == self._next_speed_limit_prev:\n      return next_speed_limit, distance_to_section_ahead, next_turn_sign\n\n    # Reset tracking\n    self._next_speed_limit_prev = 0.\n\n    # When we detect we are close enough, we provide the next limit value and track it.\n    if distance_gap <= 0.:\n      self._next_speed_limit_prev = next_speed_limit\n      return next_speed_limit, distance_to_section_ahead, next_turn_sign\n\n    # Otherwise we just provide the calculated speed_limit\n    return speed_limit, 0., turn_sign\n\n  def _update_params(self):\n    time = sec_since_boot()\n    if time > self._last_params_update + 5.0:\n      self._is_enabled = self._params.get_bool(\"TurnSpeedControl\")\n      self._last_params_update = time\n\n  def _update_calculations(self):\n    # Update current velocity offset (error)\n    self._v_offset = self.speed_limit - self._v_ego\n\n  def _state_transition(self, sm):\n    # In any case, if op is disabled, or turn speed limit control is disabled\n    # or the reported speed limit is 0, deactivate.\n    if not self._op_enabled or not self._is_enabled or self.speed_limit == 0.:\n      self.state = TurnSpeedControlState.inactive\n      return\n\n    # In any case, we deactivate the speed limit controller temporarily\n    # if gas is pressed (to support gas override implementations).\n    if sm['carState'].gasPressed:\n      self.state = TurnSpeedControlState.tempInactive\n      return\n\n    # inactive\n    if self.state == TurnSpeedControlState.inactive:\n      # If the limit speed offset is negative (i.e. reduce speed) and lower than threshold and distanct to turn limit\n      # is positive (not in turn yet) we go to adapting state to reduce speed, otherwise we go directly to active\n      if self._v_offset < LIMIT_SPEED_OFFSET_TH and self.distance > 0.:\n        self.state = TurnSpeedControlState.adapting\n      else:\n        self.state = TurnSpeedControlState.active\n    # tempInactive\n    elif self.state == TurnSpeedControlState.tempInactive:\n      # if the speed limit recorded when going to temp Inactive changes\n      # then set to inactive, activation will happen on next cycle\n      if self._speed_limit != self._speed_limit_temp_inactive:\n        self.state = TurnSpeedControlState.inactive\n    # adapting\n    elif self.state == TurnSpeedControlState.adapting:\n      # Go to active once the speed offset is over threshold or the distance to turn is now 0.\n      if self._v_offset >= LIMIT_SPEED_OFFSET_TH or self.distance == 0.:\n        self.state = TurnSpeedControlState.active\n    # active\n    elif self.state == TurnSpeedControlState.active:\n      # Go to adapting if the speed offset goes below threshold as long as the distance to turn is still positive.\n      if self._v_offset < LIMIT_SPEED_OFFSET_TH and self.distance > 0.:\n        self.state = TurnSpeedControlState.adapting\n\n  def _update_solution(self):\n    # inactive or tempInactive state\n    if self.state <= TurnSpeedControlState.tempInactive:\n      # Preserve current values\n      a_target = self._a_ego\n    # adapting\n    elif self.state == TurnSpeedControlState.adapting:\n      # When adapting we target to achieve the speed limit on the distance.\n      a_target = (self.speed_limit**2 - self._v_ego**2) / (2. * self.distance)\n      a_target = np.clip(a_target, LIMIT_MIN_ACC, LIMIT_MAX_ACC)\n    # active\n    elif self.state == TurnSpeedControlState.active:\n      # When active we are trying to keep the speed constant around the control time horizon.\n      # but under constrained acceleration limits since we are in a turn.\n      a_target = self._v_offset / T_IDXS[CONTROL_N]\n      a_target = np.clip(a_target, _ACTIVE_LIMIT_MIN_ACC, _ACTIVE_LIMIT_MAX_ACC)\n\n    # update solution values.\n    self._a_target = a_target\n\n  def update(self, enabled, v_ego, a_ego, sm):\n    self._op_enabled = enabled\n    self._v_ego = v_ego\n    self._a_ego = a_ego\n\n    # Get the speed limit from Map Data\n    self._speed_limit, self._distance, self._turn_sign = self._get_limit_from_map_data(sm)\n\n    self._update_params()\n    self._update_calculations()\n    self._state_transition(sm)\n    self._update_solution()\n"
  },
  {
    "path": "selfdrive/controls/lib/vehicle_model.py",
    "content": "#!/usr/bin/env python3\n\"\"\"\nDynamic bicycle model from \"The Science of Vehicle Dynamics (2014), M. Guiggiani\"\n\nThe state is x = [v, r]^T\nwith v lateral speed [m/s], and r rotational speed [rad/s]\n\nThe input u is the steering angle [rad]\n\nThe system is defined by\nx_dot = A*x + B*u\n\nA depends on longitudinal speed, u [m/s], and vehicle parameters CP\n\"\"\"\nfrom typing import Tuple\n\nimport numpy as np\nfrom numpy.linalg import solve\n\nfrom cereal import car\nfrom common.params import Params\n\nclass VehicleModel:\n  def __init__(self, CP: car.CarParams):\n    \"\"\"\n    Args:\n      CP: Car Parameters\n    \"\"\"\n    # for math readability, convert long names car params into short names\n    self.m = CP.mass\n    self.j = CP.rotationalInertia\n    self.l = CP.wheelbase\n    self.aF = CP.centerToFront\n    self.aR = CP.wheelbase - CP.centerToFront\n    self.chi = CP.steerRatioRear\n\n    self.cF_orig = CP.tireStiffnessFront\n    self.cR_orig = CP.tireStiffnessRear\n    self.update_params(1.0, CP.steerRatio)\n\n  def update_params(self, stiffness_factor: float, steer_ratio: float) -> None:\n    \"\"\"Update the vehicle model with a new stiffness factor and steer ratio\"\"\"\n    self.cF = stiffness_factor * self.cF_orig\n    self.cR = stiffness_factor * self.cR_orig\n    self.sR = steer_ratio\n\n  def steady_state_sol(self, sa: float, u: float) -> np.ndarray:\n    \"\"\"Returns the steady state solution.\n\n    If the speed is too low we can't use the dynamic model (tire slip is undefined),\n    we then have to use the kinematic model\n\n    Args:\n      sa: Steering wheel angle [rad]\n      u: Speed [m/s]\n\n    Returns:\n      2x1 matrix with steady state solution (lateral speed, rotational speed)\n    \"\"\"\n    if u > 0.1:\n      return dyn_ss_sol(sa, u, self)\n    else:\n      return kin_ss_sol(sa, u, self)\n\n  def calc_curvature(self, sa: float, u: float) -> float:\n    \"\"\"Returns the curvature. Multiplied by the speed this will give the yaw rate.\n\n    Args:\n      sa: Steering wheel angle [rad]\n      u: Speed [m/s]\n\n    Returns:\n      Curvature factor [1/m]\n    \"\"\"\n    return self.curvature_factor(u) * sa / self.sR\n\n  def curvature_factor(self, u: float) -> float:\n    \"\"\"Returns the curvature factor.\n    Multiplied by wheel angle (not steering wheel angle) this will give the curvature.\n\n    Args:\n      u: Speed [m/s]\n\n    Returns:\n      Curvature factor [1/m]\n    \"\"\"\n    sf = calc_slip_factor(self)\n    return (1. - self.chi) / (1. - sf * u**2) / self.l\n\n  def get_steer_from_curvature(self, curv: float, u: float) -> float:\n    \"\"\"Calculates the required steering wheel angle for a given curvature\n\n    Args:\n      curv: Desired curvature [1/m]\n      u: Speed [m/s]\n\n    Returns:\n      Steering wheel angle [rad]\n    \"\"\"\n\n    return curv * self.sR * 1.0 / self.curvature_factor(u)\n\n  def get_steer_from_yaw_rate(self, yaw_rate: float, u: float) -> float:\n    \"\"\"Calculates the required steering wheel angle for a given yaw_rate\n\n    Args:\n      yaw_rate: Desired yaw rate [rad/s]\n      u: Speed [m/s]\n\n    Returns:\n      Steering wheel angle [rad]\n    \"\"\"\n    curv = yaw_rate / u\n    return self.get_steer_from_curvature(curv, u)\n\n  def yaw_rate(self, sa: float, u: float) -> float:\n    \"\"\"Calculate yaw rate\n\n    Args:\n      sa: Steering wheel angle [rad]\n      u: Speed [m/s]\n\n    Returns:\n      Yaw rate [rad/s]\n    \"\"\"\n    return self.calc_curvature(sa, u) * u\n\n\ndef kin_ss_sol(sa: float, u: float, VM: VehicleModel) -> np.ndarray:\n  \"\"\"Calculate the steady state solution at low speeds\n  At low speeds the tire slip is undefined, so a kinematic\n  model is used.\n\n  Args:\n    sa: Steering angle [rad]\n    u: Speed [m/s]\n    VM: Vehicle model\n\n  Returns:\n    2x1 matrix with steady state solution\n  \"\"\"\n  K = np.zeros((2, 1))\n  K[0, 0] = VM.aR / VM.sR / VM.l * u\n  K[1, 0] = 1. / VM.sR / VM.l * u\n  return K * sa\n\n\ndef create_dyn_state_matrices(u: float, VM: VehicleModel) -> Tuple[np.ndarray, np.ndarray]:\n  \"\"\"Returns the A and B matrix for the dynamics system\n\n  Args:\n    u: Vehicle speed [m/s]\n    VM: Vehicle model\n\n  Returns:\n    A tuple with the 2x2 A matrix, and 2x1 B matrix\n\n  Parameters in the vehicle model:\n    cF: Tire stiffness Front [N/rad]\n    cR: Tire stiffness Front [N/rad]\n    aF: Distance from CG to front wheels [m]\n    aR: Distance from CG to rear wheels [m]\n    m: Mass [kg]\n    j: Rotational inertia [kg m^2]\n    sR: Steering ratio [-]\n    chi: Steer ratio rear [-]\n  \"\"\"\n  A = np.zeros((2, 2))\n  B = np.zeros((2, 1))\n  A[0, 0] = - (VM.cF + VM.cR) / (VM.m * u)\n  A[0, 1] = - (VM.cF * VM.aF - VM.cR * VM.aR) / (VM.m * u) - u\n  A[1, 0] = - (VM.cF * VM.aF - VM.cR * VM.aR) / (VM.j * u)\n  A[1, 1] = - (VM.cF * VM.aF**2 + VM.cR * VM.aR**2) / (VM.j * u)\n  B[0, 0] = (VM.cF + VM.chi * VM.cR) / VM.m / VM.sR\n  B[1, 0] = (VM.cF * VM.aF - VM.chi * VM.cR * VM.aR) / VM.j / VM.sR\n  return A, B\n\n\ndef dyn_ss_sol(sa: float, u: float, VM: VehicleModel) -> np.ndarray:\n  \"\"\"Calculate the steady state solution when x_dot = 0,\n  Ax + Bu = 0 => x = -A^{-1} B u\n\n  Args:\n    sa: Steering angle [rad]\n    u: Speed [m/s]\n    VM: Vehicle model\n\n  Returns:\n    2x1 matrix with steady state solution\n  \"\"\"\n  A, B = create_dyn_state_matrices(u, VM)\n  return -solve(A, B) * sa\n\n\ndef calc_slip_factor(VM):\n  \"\"\"The slip factor is a measure of how the curvature changes with speed\n  it's positive for Oversteering vehicle, negative (usual case) otherwise.\n  \"\"\"\n  return VM.m * (VM.cF * VM.aF - VM.cR * VM.aR) / (VM.l**2 * VM.cF * VM.cR)\n"
  },
  {
    "path": "selfdrive/controls/lib/vision_turn_controller.py",
    "content": "import numpy as np\nimport math\nfrom cereal import log\nfrom common.numpy_fast import interp\nfrom common.params import Params\nfrom common.realtime import sec_since_boot\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.controls.lib.lane_planner import TRAJECTORY_SIZE\nfrom selfdrive.controls.lib.drive_helpers import V_CRUISE_MAX\n\n\n_MIN_V = 5.6  # Do not operate under 20km/h\n\n_ENTERING_PRED_LAT_ACC_TH = 1.3  # Predicted Lat Acc threshold to trigger entering turn state.\n_ABORT_ENTERING_PRED_LAT_ACC_TH = 1.1  # Predicted Lat Acc threshold to abort entering state if speed drops.\n\n_TURNING_LAT_ACC_TH = 1.6  # Lat Acc threshold to trigger turning turn state.\n\n_LEAVING_LAT_ACC_TH = 1.3  # Lat Acc threshold to trigger leaving turn state.\n_FINISH_LAT_ACC_TH = 1.1  # Lat Acc threshold to trigger end of turn cycle.\n\n_EVAL_STEP = 5.  # mts. Resolution of the curvature evaluation.\n_EVAL_START = 20.  # mts. Distance ahead where to start evaluating vision curvature.\n_EVAL_LENGHT = 150.  # mts. Distance ahead where to stop evaluating vision curvature.\n_EVAL_RANGE = np.arange(_EVAL_START, _EVAL_LENGHT, _EVAL_STEP)\n\n_A_LAT_REG_MAX = 2.  # Maximum lateral acceleration\n\n# Lookup table for the minimum smooth deceleration during the ENTERING state\n# depending on the actual maximum absolute lateral acceleration predicted on the turn ahead.\n_ENTERING_SMOOTH_DECEL_V = [-0.2, -1.]  # min decel value allowed on ENTERING state\n_ENTERING_SMOOTH_DECEL_BP = [1.3, 3.]  # absolute value of lat acc ahead\n\n# Lookup table for the acceleration for the TURNING state\n# depending on the current lateral acceleration of the vehicle.\n_TURNING_ACC_V = [0.5, 0., -0.4]  # acc value\n_TURNING_ACC_BP = [1.5, 2.3, 3.]  # absolute value of current lat acc\n\n_LEAVING_ACC = 0.5  # Confortble acceleration to regain speed while leaving a turn.\n\n_MIN_LANE_PROB = 0.6  # Minimum lanes probability to allow curvature prediction based on lanes.\n\n_DEBUG = False\n\n\ndef _debug(msg):\n  if not _DEBUG:\n    return\n  print(msg)\n\n\nVisionTurnControllerState = log.LongitudinalPlan.VisionTurnControllerState\n\n\ndef eval_curvature(poly, x_vals):\n  \"\"\"\n  This function returns a vector with the curvature based on path defined by `poly`\n  evaluated on distance vector `x_vals`\n  \"\"\"\n  # https://en.wikipedia.org/wiki/Curvature#  Local_expressions\n  def curvature(x):\n    a = abs(2 * poly[1] + 6 * poly[0] * x) / (1 + (3 * poly[0] * x**2 + 2 * poly[1] * x + poly[2])**2)**(1.5)\n    return a\n\n  return np.vectorize(curvature)(x_vals)\n\n\ndef eval_lat_acc(v_ego, x_curv):\n  \"\"\"\n  This function returns a vector with the lateral acceleration based\n  for the provided speed `v_ego` evaluated over curvature vector `x_curv`\n  \"\"\"\n\n  def lat_acc(curv):\n    a = v_ego**2 * curv\n    return a\n\n  return np.vectorize(lat_acc)(x_curv)\n\n\ndef _description_for_state(turn_controller_state):\n  if turn_controller_state == VisionTurnControllerState.disabled:\n    return 'DISABLED'\n  if turn_controller_state == VisionTurnControllerState.entering:\n    return 'ENTERING'\n  if turn_controller_state == VisionTurnControllerState.turning:\n    return 'TURNING'\n  if turn_controller_state == VisionTurnControllerState.leaving:\n    return 'LEAVING'\n\n\nclass VisionTurnController():\n  def __init__(self, CP):\n    self._params = Params()\n    self._CP = CP\n    self._op_enabled = False\n    self._gas_pressed = False\n    self._is_enabled = self._params.get_bool(\"TurnVisionControl\")\n    self._last_params_update = 0.\n    self._v_cruise_setpoint = 0.\n    self._v_ego = 0.\n    self._a_ego = 0.\n    self._a_target = 0.\n    self._v_overshoot = 0.\n    self._state = VisionTurnControllerState.disabled\n\n    self._reset()\n\n  @property\n  def state(self):\n    return self._state\n\n  @state.setter\n  def state(self, value):\n    if value != self._state:\n      _debug(f'TVC: TurnVisionController state: {_description_for_state(value)}')\n      if value == VisionTurnControllerState.disabled:\n        self._reset()\n    self._state = value\n\n  @property\n  def a_target(self):\n    return self._a_target if self.is_active else self._a_ego\n\n  @property\n  def v_turn(self):\n    return self._v_overshoot if self.is_active and self._lat_acc_overshoot_ahead else self._v_ego\n\n  @property\n  def is_active(self):\n    return self._state != VisionTurnControllerState.disabled\n\n  def _reset(self):\n    self._current_lat_acc = 0.\n    self._max_v_for_current_curvature = 0.\n    self._max_pred_lat_acc = 0.\n    self._v_overshoot_distance = 200.\n    self._lat_acc_overshoot_ahead = False\n\n  def _update_params(self):\n    time = sec_since_boot()\n    if time > self._last_params_update + 5.0:\n      self._is_enabled = self._params.get_bool(\"TurnVisionControl\")\n      self._last_params_update = time\n\n  def _update_calculations(self, sm):\n    # Get path polynomial aproximation for curvature estimation from model data.\n    path_poly = None\n    model_data = sm['modelV2'] if sm.valid.get('modelV2', False) else None\n    lat_planner_data = sm['lateralPlan'] if sm.valid.get('lateralPlan', False) else None\n\n    # 1. When the probability of lanes is good enough, compute polynomial from lanes as they are way more stable\n    # on current mode than drving path.\n    if model_data is not None and len(model_data.laneLines) == 4 and len(model_data.laneLines[0].t) == TRAJECTORY_SIZE:\n      ll_x = model_data.laneLines[1].x  # left and right ll x is the same\n      lll_y = np.array(model_data.laneLines[1].y)\n      rll_y = np.array(model_data.laneLines[2].y)\n      l_prob = model_data.laneLineProbs[1]\n      r_prob = model_data.laneLineProbs[2]\n      lll_std = model_data.laneLineStds[1]\n      rll_std = model_data.laneLineStds[2]\n\n      # Reduce reliance on lanelines that are too far apart or will be in a few seconds\n      width_pts = rll_y - lll_y\n      prob_mods = []\n      for t_check in [0.0, 1.5, 3.0]:\n        width_at_t = interp(t_check * (self._v_ego + 7), ll_x, width_pts)\n        prob_mods.append(interp(width_at_t, [4.0, 5.0], [1.0, 0.0]))\n      mod = min(prob_mods)\n      l_prob *= mod\n      r_prob *= mod\n\n      # Reduce reliance on uncertain lanelines\n      l_std_mod = interp(lll_std, [.15, .3], [1.0, 0.0])\n      r_std_mod = interp(rll_std, [.15, .3], [1.0, 0.0])\n      l_prob *= l_std_mod\n      r_prob *= r_std_mod\n\n      # Find path from lanes as the average center lane only if min probability on both lanes is above threshold.\n      if l_prob > _MIN_LANE_PROB and r_prob > _MIN_LANE_PROB:\n        c_y = width_pts / 2 + lll_y\n        path_poly = np.polyfit(ll_x, c_y, 3)\n\n    # 2. If not polynomial derived from lanes, then derive it from compensated driving path with lanes as\n    # provided by `lateralPlanner`.\n    if path_poly is None and lat_planner_data is not None and len(lat_planner_data.dPathWLinesX) > 0 \\\n       and lat_planner_data.dPathWLinesX[0] > 0:\n      path_poly = np.polyfit(lat_planner_data.dPathWLinesX, lat_planner_data.dPathWLinesY, 3)\n\n    # 3. If no polynomial derived from lanes or driving path, then provide a straight line poly.\n    if path_poly is None:\n      path_poly = np.array([0., 0., 0., 0.])\n\n    current_curvature = abs(\n      sm['carState'].steeringAngleDeg * CV.DEG_TO_RAD / (self._CP.steerRatio * self._CP.wheelbase))\n    self._current_lat_acc = current_curvature * self._v_ego**2\n    self._max_v_for_current_curvature = math.sqrt(_A_LAT_REG_MAX / current_curvature) if current_curvature > 0 \\\n      else V_CRUISE_MAX * CV.KPH_TO_MS\n\n    pred_curvatures = eval_curvature(path_poly, _EVAL_RANGE)\n    max_pred_curvature = np.amax(pred_curvatures)\n    self._max_pred_lat_acc = self._v_ego**2 * max_pred_curvature\n\n    max_curvature_for_vego = _A_LAT_REG_MAX / max(self._v_ego, 0.1)**2\n    lat_acc_overshoot_idxs = np.nonzero(pred_curvatures >= max_curvature_for_vego)[0]\n    self._lat_acc_overshoot_ahead = len(lat_acc_overshoot_idxs) > 0\n\n    if self._lat_acc_overshoot_ahead:\n      self._v_overshoot = min(math.sqrt(_A_LAT_REG_MAX / max_pred_curvature), self._v_cruise_setpoint)\n      self._v_overshoot_distance = max(lat_acc_overshoot_idxs[0] * _EVAL_STEP + _EVAL_START, _EVAL_STEP)\n      _debug(f'TVC: High LatAcc. Dist: {self._v_overshoot_distance:.2f}, v: {self._v_overshoot * CV.MS_TO_KPH:.2f}')\n\n  def _state_transition(self):\n    # In any case, if system is disabled or the feature is disabeld or gas is pressed, disable.\n    if not self._op_enabled or not self._is_enabled or self._gas_pressed:\n      self.state = VisionTurnControllerState.disabled\n      return\n\n    # DISABLED\n    if self.state == VisionTurnControllerState.disabled:\n      # Do not enter a turn control cycle if speed is low.\n      if self._v_ego <= _MIN_V:\n        pass\n      # If substantial lateral acceleration is predicted ahead, then move to Entering turn state.\n      elif self._max_pred_lat_acc >= _ENTERING_PRED_LAT_ACC_TH:\n        self.state = VisionTurnControllerState.entering\n    # ENTERING\n    elif self.state == VisionTurnControllerState.entering:\n      # Transition to Turning if current lateral acceleration is over the threshold.\n      if self._current_lat_acc >= _TURNING_LAT_ACC_TH:\n        self.state = VisionTurnControllerState.turning\n      # Abort if the predicted lateral acceleration drops\n      elif self._max_pred_lat_acc < _ABORT_ENTERING_PRED_LAT_ACC_TH:\n        self.state = VisionTurnControllerState.disabled\n    # TURNING\n    elif self.state == VisionTurnControllerState.turning:\n      # Transition to Leaving if current lateral acceleration drops drops below threshold.\n      if self._current_lat_acc <= _LEAVING_LAT_ACC_TH:\n        self.state = VisionTurnControllerState.leaving\n    # LEAVING\n    elif self.state == VisionTurnControllerState.leaving:\n      # Transition back to Turning if current lateral acceleration goes back over the threshold.\n      if self._current_lat_acc >= _TURNING_LAT_ACC_TH:\n        self.state = VisionTurnControllerState.turning\n      # Finish if current lateral acceleration goes below threshold.\n      elif self._current_lat_acc < _FINISH_LAT_ACC_TH:\n        self.state = VisionTurnControllerState.disabled\n\n  def _update_solution(self):\n    # DISABLED\n    if self.state == VisionTurnControllerState.disabled:\n      # when not overshooting, calculate v_turn as the speed at the prediction horizon when following\n        # the smooth deceleration.\n      a_target = self._a_ego\n    # ENTERING\n    elif self.state == VisionTurnControllerState.entering:\n      # when not overshooting, target a smooth deceleration in preparation for a sharp turn to come.\n      a_target = interp(self._max_pred_lat_acc, _ENTERING_SMOOTH_DECEL_BP, _ENTERING_SMOOTH_DECEL_V)\n      if self._lat_acc_overshoot_ahead:\n        # when overshooting, target the acceleration needed to achieve the overshoot speed at\n        # the required distance\n        a_target = min((self._v_overshoot**2 - self._v_ego**2) / (2 * self._v_overshoot_distance), a_target)\n      _debug(f'TVC Entering: Overshooting: {self._lat_acc_overshoot_ahead}')\n      _debug(f'    Decel: {a_target:.2f}, target v: {self.v_turn * CV.MS_TO_KPH}')\n    # TURNING\n    elif self.state == VisionTurnControllerState.turning:\n      # When turning we provide a target acceleration that is confortable for the lateral accelearation felt.\n      a_target = interp(self._current_lat_acc, _TURNING_ACC_BP, _TURNING_ACC_V)\n    # LEAVING\n    elif self.state == VisionTurnControllerState.leaving:\n      # When leaving we provide a confortable acceleration to regain speed.\n      a_target = _LEAVING_ACC\n\n    # update solution values.\n    self._a_target = a_target\n\n  def update(self, enabled, v_ego, a_ego, v_cruise_setpoint, sm):\n    self._op_enabled = enabled\n    self._gas_pressed = sm['carState'].gasPressed\n    self._v_ego = v_ego\n    self._a_ego = a_ego\n    self._v_cruise_setpoint = v_cruise_setpoint\n\n    self._update_params()\n    self._update_calculations(sm)\n    self._state_transition()\n    self._update_solution()\n"
  },
  {
    "path": "selfdrive/controls/plannerd.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom common.params import Params\nfrom common.realtime import Priority, config_realtime_process\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.controls.lib.longitudinal_planner import Planner\nfrom selfdrive.controls.lib.lateral_planner import LateralPlanner\nfrom selfdrive.hardware import TICI, JETSON\nimport cereal.messaging as messaging\n\n\ndef plannerd_thread(sm=None, pm=None):\n  config_realtime_process(5 if TICI else 4 if JETSON else 2, Priority.CTRL_LOW)\n\n  cloudlog.info(\"plannerd is waiting for CarParams\")\n  params = Params()\n  CP = car.CarParams.from_bytes(params.get(\"CarParams\", block=True))\n  cloudlog.info(\"plannerd got CarParams: %s\", CP.carName)\n\n  use_lanelines = not params.get_bool('EndToEndToggle')\n  wide_camera = params.get_bool('EnableWideCamera') if TICI else False\n\n  cloudlog.event(\"e2e mode\", on=use_lanelines)\n\n  longitudinal_planner = Planner(CP)\n  lateral_planner = LateralPlanner(CP, use_lanelines=use_lanelines, wide_camera=wide_camera)\n\n  if sm is None:\n    sm = messaging.SubMaster(['carState', 'controlsState', 'radarState', 'modelV2', 'dragonConf', 'liveMapData'],\n                             poll=['radarState', 'modelV2'], ignore_avg_freq=['radarState'])\n\n  if pm is None:\n    pm = messaging.PubMaster(['longitudinalPlan', 'liveLongitudinalMpc', 'lateralPlan', 'liveMpc'])\n\n  while True:\n    sm.update()\n\n    if sm.updated['modelV2']:\n      lateral_planner.update(sm, CP)\n      lateral_planner.publish(sm, pm)\n    if sm.updated['radarState']:\n      longitudinal_planner.update(sm, CP)\n      longitudinal_planner.publish(sm, pm)\n\n\ndef main(sm=None, pm=None):\n  plannerd_thread(sm, pm)\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/controls/radard.py",
    "content": "#!/usr/bin/env python3\nimport importlib\nimport math\nfrom collections import defaultdict, deque\n\nimport cereal.messaging as messaging\nfrom cereal import car\nfrom common.numpy_fast import interp\nfrom common.params import Params\nfrom common.realtime import Ratekeeper, Priority, config_realtime_process\nfrom selfdrive.config import RADAR_TO_CAMERA\nfrom selfdrive.controls.lib.cluster.fastcluster_py import cluster_points_centroid\nfrom selfdrive.controls.lib.radar_helpers import Cluster, Track\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.hardware import TICI, JETSON\n\n\nclass KalmanParams():\n  def __init__(self, dt):\n    # Lead Kalman Filter params, calculating K from A, C, Q, R requires the control library.\n    # hardcoding a lookup table to compute K for values of radar_ts between 0.1s and 1.0s\n    assert dt > .01 and dt < .1, \"Radar time step must be between .01s and 0.1s\"\n    self.A = [[1.0, dt], [0.0, 1.0]]\n    self.C = [1.0, 0.0]\n    #Q = np.matrix([[10., 0.0], [0.0, 100.]])\n    #R = 1e3\n    #K = np.matrix([[ 0.05705578], [ 0.03073241]])\n    dts = [dt * 0.01 for dt in range(1, 11)]\n    K0 = [0.12288, 0.14557, 0.16523, 0.18282, 0.19887, 0.21372, 0.22761, 0.24069, 0.2531, 0.26491]\n    K1 = [0.29666, 0.29331, 0.29043, 0.28787, 0.28555, 0.28342, 0.28144, 0.27958, 0.27783, 0.27617]\n    self.K = [[interp(dt, dts, K0)], [interp(dt, dts, K1)]]\n\n\ndef laplacian_cdf(x, mu, b):\n  b = max(b, 1e-4)\n  return math.exp(-abs(x-mu)/b)\n\n\ndef match_vision_to_cluster(v_ego, lead, clusters):\n  # match vision point to best statistical cluster match\n  offset_vision_dist = lead.x[0] - RADAR_TO_CAMERA\n\n  def prob(c):\n    prob_d = laplacian_cdf(c.dRel, offset_vision_dist, lead.xStd[0])\n    prob_y = laplacian_cdf(c.yRel, -lead.y[0], lead.yStd[0])\n    prob_v = laplacian_cdf(c.vRel + v_ego, lead.v[0], lead.vStd[0])\n\n    # This is isn't exactly right, but good heuristic\n    return prob_d * prob_y * prob_v\n\n  cluster = max(clusters, key=prob)\n\n  # if no 'sane' match is found return -1\n  # stationary radar points can be false positives\n  dist_sane = abs(cluster.dRel - offset_vision_dist) < max([(offset_vision_dist)*.25, 5.0])\n  vel_sane = (abs(cluster.vRel + v_ego - lead.v[0]) < 10) or (v_ego + cluster.vRel > 3)\n  if dist_sane and vel_sane:\n    return cluster\n  else:\n    return None\n\n\ndef get_lead(v_ego, ready, clusters, lead_msg, low_speed_override=True):\n  # Determine leads, this is where the essential logic happens\n  if len(clusters) > 0 and ready and lead_msg.prob > .5:\n    cluster = match_vision_to_cluster(v_ego, lead_msg, clusters)\n  else:\n    cluster = None\n\n  lead_dict = {'status': False}\n  if cluster is not None:\n    lead_dict = cluster.get_RadarState(lead_msg.prob)\n  elif (cluster is None) and ready and (lead_msg.prob > .5):\n    lead_dict = Cluster().get_RadarState_from_vision(lead_msg, v_ego)\n\n  if low_speed_override:\n    low_speed_clusters = [c for c in clusters if c.potential_low_speed_lead(v_ego)]\n    if len(low_speed_clusters) > 0:\n      closest_cluster = min(low_speed_clusters, key=lambda c: c.dRel)\n\n      # Only choose new cluster if it is actually closer than the previous one\n      if (not lead_dict['status']) or (closest_cluster.dRel < lead_dict['dRel']):\n        lead_dict = closest_cluster.get_RadarState()\n\n  return lead_dict\n\n\nclass RadarD():\n  def __init__(self, radar_ts, delay=0):\n    self.current_time = 0\n\n    self.tracks = defaultdict(dict)\n    self.kalman_params = KalmanParams(radar_ts)\n\n    # v_ego\n    self.v_ego = 0.\n    self.v_ego_hist = deque([0], maxlen=delay+1)\n\n    self.ready = False\n\n  def update(self, sm, rr, enable_lead):\n    self.current_time = 1e-9*max(sm.logMonoTime.values())\n\n    if sm.updated['carState']:\n      self.v_ego = sm['carState'].vEgo\n      self.v_ego_hist.append(self.v_ego)\n    if sm.updated['modelV2']:\n      self.ready = True\n\n    ar_pts = {}\n    for pt in rr.points:\n      ar_pts[pt.trackId] = [pt.dRel, pt.yRel, pt.vRel, pt.measured]\n\n    # *** remove missing points from meta data ***\n    for ids in list(self.tracks.keys()):\n      if ids not in ar_pts:\n        self.tracks.pop(ids, None)\n\n    # *** compute the tracks ***\n    for ids in ar_pts:\n      rpt = ar_pts[ids]\n\n      # align v_ego by a fixed time to align it with the radar measurement\n      v_lead = rpt[2] + self.v_ego_hist[0]\n\n      # create the track if it doesn't exist or it's a new track\n      if ids not in self.tracks:\n        self.tracks[ids] = Track(v_lead, self.kalman_params)\n      self.tracks[ids].update(rpt[0], rpt[1], rpt[2], v_lead, rpt[3])\n\n    idens = list(sorted(self.tracks.keys()))\n    track_pts = list([self.tracks[iden].get_key_for_cluster() for iden in idens])\n\n    # If we have multiple points, cluster them\n    if len(track_pts) > 1:\n      cluster_idxs = cluster_points_centroid(track_pts, 2.5)\n      clusters = [None] * (max(cluster_idxs) + 1)\n\n      for idx in range(len(track_pts)):\n        cluster_i = cluster_idxs[idx]\n        if clusters[cluster_i] is None:\n          clusters[cluster_i] = Cluster()\n        clusters[cluster_i].add(self.tracks[idens[idx]])\n    elif len(track_pts) == 1:\n      # FIXME: cluster_point_centroid hangs forever if len(track_pts) == 1\n      cluster_idxs = [0]\n      clusters = [Cluster()]\n      clusters[0].add(self.tracks[idens[0]])\n    else:\n      clusters = []\n\n    # if a new point, reset accel to the rest of the cluster\n    for idx in range(len(track_pts)):\n      if self.tracks[idens[idx]].cnt <= 1:\n        aLeadK = clusters[cluster_idxs[idx]].aLeadK\n        aLeadTau = clusters[cluster_idxs[idx]].aLeadTau\n        self.tracks[idens[idx]].reset_a_lead(aLeadK, aLeadTau)\n\n    # *** publish radarState ***\n    dat = messaging.new_message('radarState')\n    dat.valid = sm.all_alive_and_valid() and len(rr.errors) == 0\n    radarState = dat.radarState\n    radarState.mdMonoTime = sm.logMonoTime['modelV2']\n    radarState.canMonoTimes = list(rr.canMonoTimes)\n    radarState.radarErrors = list(rr.errors)\n    radarState.carStateMonoTime = sm.logMonoTime['carState']\n\n    if enable_lead:\n      if len(sm['modelV2'].leadsV3) > 1:\n        radarState.leadOne = get_lead(self.v_ego, self.ready, clusters, sm['modelV2'].leadsV3[0], low_speed_override=True)\n        radarState.leadTwo = get_lead(self.v_ego, self.ready, clusters, sm['modelV2'].leadsV3[1], low_speed_override=False)\n    return dat\n\n\n# fuses camera and radar data for best lead detection\ndef radard_thread(sm=None, pm=None, can_sock=None):\n  config_realtime_process(5 if TICI else 4 if JETSON else 2, Priority.CTRL_LOW)\n\n  # wait for stats about the car to come in from controls\n  cloudlog.info(\"radard is waiting for CarParams\")\n  CP = car.CarParams.from_bytes(Params().get(\"CarParams\", block=True))\n  cloudlog.info(\"radard got CarParams\")\n\n  # import the radar from the fingerprint\n  cloudlog.info(\"radard is importing %s\", CP.carName)\n  RadarInterface = importlib.import_module('selfdrive.car.%s.radar_interface' % CP.carName).RadarInterface\n\n  # *** setup messaging\n  if can_sock is None:\n    can_sock = messaging.sub_sock('can')\n  if sm is None:\n    sm = messaging.SubMaster(['modelV2', 'carState'], ignore_avg_freq=['modelV2', 'carState'])  # Can't check average frequency, since radar determines timing\n  if pm is None:\n    pm = messaging.PubMaster(['radarState', 'liveTracks'])\n\n  RI = RadarInterface(CP)\n\n  rk = Ratekeeper(1.0 / CP.radarTimeStep, print_delay_threshold=None)\n  RD = RadarD(CP.radarTimeStep, RI.delay)\n\n  # TODO: always log leads once we can hide them conditionally\n  enable_lead = True #CP.openpilotLongitudinalControl or not CP.radarOffCan\n\n  while 1:\n    can_strings = messaging.drain_sock_raw(can_sock, wait_for_one=True)\n    rr = RI.update(can_strings)\n\n    if rr is None:\n      continue\n\n    sm.update(0)\n\n    dat = RD.update(sm, rr, enable_lead)\n    dat.radarState.cumLagMs = -rk.remaining*1000.\n\n    pm.send('radarState', dat)\n\n    # *** publish tracks for UI debugging (keep last) ***\n    tracks = RD.tracks\n    dat = messaging.new_message('liveTracks', len(tracks))\n\n    for cnt, ids in enumerate(sorted(tracks.keys())):\n      dat.liveTracks[cnt] = {\n        \"trackId\": ids,\n        \"dRel\": float(tracks[ids].dRel),\n        \"yRel\": float(tracks[ids].yRel),\n        \"vRel\": float(tracks[ids].vRel),\n      }\n    pm.send('liveTracks', dat)\n\n    rk.monitor_time()\n\n\ndef main(sm=None, pm=None, can_sock=None):\n  radard_thread(sm, pm, can_sock)\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/crash.py",
    "content": "\"\"\"Install exception handler for process crash.\"\"\"\nimport os\nimport sys\nimport capnp\nimport traceback\nimport requests\nfrom cereal import car\nfrom datetime import datetime\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.version import version\nfrom selfdrive.version import version, branch, origin, branch, dirty, commit, get_git_commit\nfrom common.params import Params\n\nimport sentry_sdk\nfrom sentry_sdk import set_tag\nfrom sentry_sdk.integrations.threading import ThreadingIntegration\n\nCRASHES_DIR = '/data/community/crashes'\n\ndef save_exception(exc_text):\n  if not os.path.exists(CRASHES_DIR):\n    os.makedirs(CRASHES_DIR)\n\n  log_file = '{}/{}'.format(CRASHES_DIR, datetime.now().strftime('%m-%d-%Y--%I:%M.%S-%p.log'))\n  with open(log_file, 'w') as f:\n    f.write(exc_text)\n  print('Logged current crash to {}'.format(log_file))\n\nret = car.CarParams.new_message()\ncandidate = ret.carFingerprint\n\nparams = Params()\n#uniqueID = op_params.get('uniqueID')\ntry:\n  dongle_id = params.get(\"DongleId\").decode('utf8')\nexcept AttributeError:\n  dongle_id = \"None\"\ntry:\n  gitname = Params().get(\"GithubUsername\", encoding='utf-8')\nexcept:\n  gitname = \"\"\ntry:\n  ip = requests.get('https://checkip.amazonaws.com/').text.strip()\nexcept Exception:\n  ip = \"255.255.255.255\"\nerror_tags = {'dirty': dirty, 'dongle_id': dongle_id, 'branch': branch, 'remote': origin, 'fingerprintedAs': candidate, 'gitname':gitname}\n\ndongle_id = Params().get(\"DongleId\", encoding='utf-8')\n\ndef capture_exception(*args, **kwargs):\n  save_exception(traceback.format_exc())\n  exc_info = sys.exc_info()\n  if not exc_info[0] is capnp.lib.capnp.KjException:\n    save_exception(traceback.format_exc())\n    sentry_sdk.capture_exception(*args, **kwargs)\n    sentry_sdk.flush()  # https://github.com/getsentry/sentry-python/issues/291\n  cloudlog.error(\"crash\", exc_info=kwargs.get('exc_info', 1))\n\ndef bind_user(**kwargs) -> None:\n    sentry_sdk.set_user(kwargs)\n\ndef capture_warning(warning_string):\n  bind_user(id=dongle_id, ip_address=ip, name=gitname)\n  sentry_sdk.capture_message(warning_string, level='warning')\n\ndef capture_info(info_string):\n  bind_user(id=dongle_id, ip_address=ip, name=gitname)\n  sentry_sdk.capture_message(info_string, level='info')\n\ndef bind_extra(**kwargs) -> None:\n  for k, v in kwargs.items():\n    sentry_sdk.set_tag(k, v)\n\ndef init() -> None:\n  sentry_sdk.init(\"https://980a0cba712a4c3593c33c78a12446e1:fecab286bcaf4dba8b04f7cff0188e2d@sentry.io/1488600\",\n                  default_integrations=False, integrations=[ThreadingIntegration(propagate_hub=True)],\n                  release=version)\n\nsentry_sdk.set_user({\"id\": dongle_id})\nsentry_sdk.set_user({\"name\": gitname})\nsentry_sdk.set_tag(\"dirty\", dirty)\nsentry_sdk.set_tag(\"origin\", origin)\nsentry_sdk.set_tag(\"branch\", branch)\nsentry_sdk.set_tag(\"commit\", commit)\n"
  },
  {
    "path": "selfdrive/debug/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/debug/can_print_changes.py",
    "content": "#!/usr/bin/env python3\nimport binascii\nimport sys\nfrom collections import defaultdict\n\nimport cereal.messaging as messaging\nfrom common.realtime import sec_since_boot\n\n\ndef can_printer(bus=0):\n  \"\"\"Collects messages and prints when a new bit transition is observed.\n  This is very useful to find signals based on user triggered actions, such as blinkers and seatbelt.\n  Leave the script running until no new transitions are seen, then perform the action.\"\"\"\n  logcan = messaging.sub_sock('can')\n\n  low_to_high = defaultdict(int)\n  high_to_low = defaultdict(int)\n\n  while 1:\n    can_recv = messaging.drain_sock(logcan, wait_for_one=True)\n    for x in can_recv:\n      for y in x.can:\n        if y.src == bus:\n          i = int.from_bytes(y.dat, byteorder='big')\n\n          l_h = low_to_high[y.address]\n          h_l = high_to_low[y.address]\n\n          change = None\n          if (i | l_h) != l_h:\n            low_to_high[y.address] = i | l_h\n            change = \"+\"\n\n          if (~i | h_l) != h_l:\n            high_to_low[y.address] = ~i | h_l\n            change = \"-\"\n\n          if change:\n            print(f\"{sec_since_boot():.2f}\\t{hex(y.address)} ({y.address})\\t{change}{binascii.hexlify(y.dat)}\")\n\n\nif __name__ == \"__main__\":\n  if len(sys.argv) > 1:\n    can_printer(int(sys.argv[1]))\n  else:\n    can_printer()\n"
  },
  {
    "path": "selfdrive/debug/can_printer.py",
    "content": "#!/usr/bin/env python3\nimport binascii\nimport os\nimport sys\nfrom collections import defaultdict\n\nimport cereal.messaging as messaging\nfrom common.realtime import sec_since_boot\n\n\ndef can_printer(bus=0, max_msg=None, addr=\"127.0.0.1\"):\n  logcan = messaging.sub_sock('can', addr=addr)\n\n  start = sec_since_boot()\n  lp = sec_since_boot()\n  msgs = defaultdict(list)\n  canbus = int(os.getenv(\"CAN\", bus))\n  while 1:\n    can_recv = messaging.drain_sock(logcan, wait_for_one=True)\n    for x in can_recv:\n      for y in x.can:\n        if y.src == canbus:\n          msgs[y.address].append(y.dat)\n\n    if sec_since_boot() - lp > 0.1:\n      dd = chr(27) + \"[2J\"\n      dd += \"%5.2f\\n\" % (sec_since_boot() - start)\n      for k, v in sorted(zip(msgs.keys(), map(lambda x: binascii.hexlify(x[-1]), msgs.values()))):\n        if max_msg is None or k < max_msg:\n          dd += \"%s(%6d) %s\\n\" % (\"%04X(%4d)\" % (k, k), len(msgs[k]), v.decode('ascii'))\n      print(dd)\n      lp = sec_since_boot()\n\nif __name__ == \"__main__\":\n  if len(sys.argv) > 3:\n    can_printer(int(sys.argv[1]), int(sys.argv[2]), sys.argv[3])\n  elif len(sys.argv) > 2:\n    can_printer(int(sys.argv[1]), int(sys.argv[2]))\n  elif len(sys.argv) > 1:\n    can_printer(int(sys.argv[1]))\n  else:\n    can_printer()\n"
  },
  {
    "path": "selfdrive/debug/check_freq.py",
    "content": "#!/usr/bin/env python3\n# type: ignore\n\nimport argparse\nimport numpy as np\nfrom collections import defaultdict, deque\nfrom common.realtime import sec_since_boot\nimport cereal.messaging as messaging\n\n\nif __name__ == \"__main__\":\n  context = messaging.Context()\n  poller = messaging.Poller()\n\n  parser = argparse.ArgumentParser()\n  parser.add_argument(\"socket\", type=str, nargs='*', help=\"socket name\")\n  args = parser.parse_args()\n\n  socket_names = args.socket\n  sockets = {}\n\n  rcv_times = defaultdict(lambda: deque(maxlen=100))\n  valids = defaultdict(lambda: deque(maxlen=100))\n\n  t = sec_since_boot()\n  for name in socket_names:\n    sock = messaging.sub_sock(name, poller=poller)\n    sockets[sock] = name\n\n  prev_print = t\n  while True:\n    for socket in poller.poll(100):\n      msg = messaging.recv_one(socket)\n      name = msg.which()\n\n      t = sec_since_boot()\n      rcv_times[name].append(msg.logMonoTime / 1e9)\n      valids[name].append(msg.valid)\n\n    if t - prev_print > 1:\n      print()\n      for name in socket_names:\n        dts = np.diff(rcv_times[name])\n        mean = np.mean(dts)\n        print(\"%s: Freq %.2f Hz, Min %.2f%%, Max %.2f%%, valid \" % (name, 1.0 / mean, np.min(dts) / mean * 100, np.max(dts) / mean * 100), all(valids[name]))\n\n      prev_print = t\n"
  },
  {
    "path": "selfdrive/debug/check_lag.py",
    "content": "#!/usr/bin/env python3\n# type: ignore\n\nimport cereal.messaging as messaging\nfrom cereal.services import service_list\n\nTO_CHECK = ['carState']\n\n\nif __name__ == \"__main__\":\n  sm = messaging.SubMaster(TO_CHECK)\n\n  prev_t = {}\n\n  while True:\n    sm.update()\n\n    for s in TO_CHECK:\n      if sm.updated[s]:\n        t = sm.logMonoTime[s] / 1e9\n\n        if s in prev_t:\n          expected = 1.0 / (service_list[s].frequency)\n          dt = t - prev_t[s]\n          if dt > 10 * expected:\n            print(t, s, dt)\n\n        prev_t[s] = t\n"
  },
  {
    "path": "selfdrive/debug/check_timings.py",
    "content": "#!/usr/bin/env python3\n# type: ignore\nimport sys\nimport time\nimport numpy as np\nfrom collections import defaultdict, deque\n\nimport cereal.messaging as messaging\n\nsocks = {s: messaging.sub_sock(s, conflate=False) for s in sys.argv[1:]}\nts = defaultdict(lambda: deque(maxlen=100))\n\nif __name__ == \"__main__\":\n  while True:\n    print()\n    for s, sock in socks.items():\n      msgs = messaging.drain_sock(sock)\n      for m in msgs:\n        ts[s].append(m.logMonoTime / 1e6)\n\n      if len(ts[s]) == ts[s].maxlen:\n        d = np.diff(ts[s])\n        print(f\"{s:17} {np.mean(d):.2f} {np.std(d):.2f} {np.max(d):.2f} {np.min(d):.2f}\")\n    time.sleep(1)\n"
  },
  {
    "path": "selfdrive/debug/compare_fingerprints.py",
    "content": "#!/usr/bin/env python3\n# flake8: noqa\n\n# put 2 fingeprints and print the diffs\nf1 = {\n168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 520: 8, 528: 8, 532: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 701: 8, 703: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 906: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8, 1537: 8, 1538: 8, 1562: 8\n}\n\nf2 = {\n168: 8, 257: 5, 258: 8, 264: 8, 268: 8, 270: 8, 274: 2, 280: 8, 284: 8, 288: 7, 290: 6, 291: 8, 292: 8, 294: 8, 300: 8, 308: 8, 320: 8, 324: 8, 331: 8, 332: 8, 344: 8, 368: 8, 376: 3, 384: 8, 388: 4, 448: 6, 456: 4, 464: 8, 469: 8, 480: 8, 500: 8, 501: 8, 512: 8, 514: 8, 515: 7, 516: 7, 517: 7, 518: 7, 520: 8, 528: 8, 532: 8, 542: 8, 544: 8, 557: 8, 559: 8, 560: 8, 564: 8, 571: 3, 579: 8, 584: 8, 608: 8, 624: 8, 625: 8, 632: 8, 639: 8, 653: 8, 654: 8, 655: 8, 658: 6, 660: 8, 669: 3, 671: 8, 672: 8, 678: 8, 680: 8, 701: 8, 703: 8, 704: 8, 705: 8, 706: 8, 709: 8, 710: 8, 719: 8, 720: 6, 729: 5, 736: 8, 737: 8, 746: 5, 752: 2, 754: 8, 760: 8, 764: 8, 766: 8, 770: 8, 773: 8, 779: 8, 782: 8, 784: 8, 792: 8, 799: 8, 800: 8, 804: 8, 816: 8, 817: 8, 820: 8, 825: 2, 826: 8, 832: 8, 838: 2, 848: 8, 853: 8, 856: 4, 860: 6, 863: 8, 878: 8, 882: 8, 897: 8, 906: 8, 908: 8, 924: 8, 926: 3, 929: 8, 937: 8, 938: 8, 939: 8, 940: 8, 941: 8, 942: 8, 943: 8, 947: 8, 948: 8, 958: 8, 959: 8, 962: 8, 969: 4, 973: 8, 974: 5, 979: 8, 980: 8, 981: 8, 982: 8, 983: 8, 984: 8, 992: 8, 993: 7, 995: 8, 996: 8, 1000: 8, 1001: 8, 1002: 8, 1003: 8, 1008: 8, 1009: 8, 1010: 8, 1011: 8, 1012: 8, 1013: 8, 1014: 8, 1015: 8, 1024: 8, 1025: 8, 1026: 8, 1031: 8, 1033: 8, 1050: 8, 1059: 8, 1082: 8, 1083: 8, 1098: 8, 1100: 8\n}\n\nfor k in f1:\n  if k not in f2 or f1[k] != f2[k]:\n    print(k, \"not in f2\")\n\nfor k in f2:\n  if k not in f1 or f2[k] != f1[k]:\n    print(k, \"not in f1\")\n"
  },
  {
    "path": "selfdrive/debug/count_events.py",
    "content": "#!/usr/bin/env python3\nimport sys\nfrom collections import Counter\nfrom pprint import pprint\nfrom tqdm import tqdm\n\nfrom tools.lib.route import Route\nfrom tools.lib.logreader import LogReader\n\nif __name__ == \"__main__\":\n  r = Route(sys.argv[1])\n\n  cnt_valid: Counter = Counter()\n  cnt_events: Counter = Counter()\n\n  for q in tqdm(r.qlog_paths()):\n    lr = list(LogReader(q))\n    for msg in lr:\n      if msg.which() == 'carEvents':\n        for e in msg.carEvents:\n          cnt_events[e.name] += 1\n      if not msg.valid:\n        cnt_valid[msg.which()] += 1\n\n  print(\"Events\")\n  pprint(cnt_events)\n\n  print(\"\\n\\n\")\n  print(\"Not valid\")\n  pprint(cnt_valid)\n"
  },
  {
    "path": "selfdrive/debug/cpu_usage_stat.py",
    "content": "#!/usr/bin/env python3\n# type: ignore\n'''\nSystem tools like top/htop can only show current cpu usage values, so I write this script to do statistics jobs.\n  Features:\n    Use psutil library to sample cpu usage(avergage for all cores) of openpilot processes, at a rate of 5 samples/sec.\n    Do cpu usage statistics periodically, 5 seconds as a cycle.\n    Caculate the average cpu usage within this cycle.\n    Caculate minumium/maximium/accumulated_average cpu usage as long term inspections.\n    Monitor multiple processes simuteneously.\n  Sample usage:\n    root@localhost:/data/openpilot$ python selfdrive/debug/cpu_usage_stat.py boardd,ubloxd\n    ('Add monitored proc:', './boardd')\n    ('Add monitored proc:', 'python locationd/ubloxd.py')\n    boardd: 1.96%, min: 1.96%, max: 1.96%, acc: 1.96%\n    ubloxd.py: 0.39%, min: 0.39%, max: 0.39%, acc: 0.39%\n'''\nimport psutil\nimport time\nimport os\nimport sys\nimport numpy as np\nimport argparse\nimport re\nfrom collections import defaultdict\n\nfrom selfdrive.manager.process_config import managed_processes\n\n# Do statistics every 5 seconds\nPRINT_INTERVAL = 5\nSLEEP_INTERVAL = 0.2\n\nmonitored_proc_names = [\n  # android procs\n  'SurfaceFlinger', 'sensors.qcom'\n] + list(managed_processes.keys())\n\ncpu_time_names = ['user', 'system', 'children_user', 'children_system']\n\ntimer = getattr(time, 'monotonic', time.time)\n\n\ndef get_arg_parser():\n  parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)\n\n  parser.add_argument(\"proc_names\", nargs=\"?\", default='',\n                      help=\"Process names to be monitored, comma separated\")\n  parser.add_argument(\"--list_all\", action='store_true',\n                      help=\"Show all running processes' cmdline\")\n  parser.add_argument(\"--detailed_times\", action='store_true',\n                      help=\"show cpu time details (split by user, system, child user, child system)\")\n  return parser\n\n\nif __name__ == \"__main__\":\n  args = get_arg_parser().parse_args(sys.argv[1:])\n  if args.list_all:\n    for p in psutil.process_iter():\n      print('cmdline', p.cmdline(), 'name', p.name())\n    sys.exit(0)\n\n  if len(args.proc_names) > 0:\n    monitored_proc_names = args.proc_names.split(',')\n  monitored_procs = []\n  stats = {}\n  for p in psutil.process_iter():\n    if p == psutil.Process():\n      continue\n    matched = any([l for l in p.cmdline() if any([pn for pn in monitored_proc_names if re.match(r'.*{}.*'.format(pn), l, re.M | re.I)])])\n    if matched:\n      k = ' '.join(p.cmdline())\n      print('Add monitored proc:', k)\n      stats[k] = {'cpu_samples': defaultdict(list), 'min': defaultdict(lambda: None), 'max': defaultdict(lambda: None),\n                  'avg': defaultdict(lambda: 0.0), 'last_cpu_times': None, 'last_sys_time': None}\n      stats[k]['last_sys_time'] = timer()\n      stats[k]['last_cpu_times'] = p.cpu_times()\n      monitored_procs.append(p)\n  i = 0\n  interval_int = int(PRINT_INTERVAL / SLEEP_INTERVAL)\n  while True:\n    for p in monitored_procs:\n      k = ' '.join(p.cmdline())\n      cur_sys_time = timer()\n      cur_cpu_times = p.cpu_times()\n      cpu_times = np.subtract(cur_cpu_times, stats[k]['last_cpu_times']) / (cur_sys_time - stats[k]['last_sys_time'])\n      stats[k]['last_sys_time'] = cur_sys_time\n      stats[k]['last_cpu_times'] = cur_cpu_times\n      cpu_percent = 0\n      for num, name in enumerate(cpu_time_names):\n        stats[k]['cpu_samples'][name].append(cpu_times[num])\n        cpu_percent += cpu_times[num]\n      stats[k]['cpu_samples']['total'].append(cpu_percent)\n    time.sleep(SLEEP_INTERVAL)\n    i += 1\n    if i % interval_int == 0:\n      l = []\n      for k, stat in stats.items():\n        if len(stat['cpu_samples']) <= 0:\n          continue\n        for name, samples in stat['cpu_samples'].items():\n          samples = np.array(samples)\n          avg = samples.mean()\n          c = samples.size\n          min_cpu = np.amin(samples)\n          max_cpu = np.amax(samples)\n          if stat['min'][name] is None or min_cpu < stat['min'][name]:\n            stat['min'][name] = min_cpu\n          if stat['max'][name] is None or max_cpu > stat['max'][name]:\n            stat['max'][name] = max_cpu\n          stat['avg'][name] = (stat['avg'][name] * (i - c) + avg * c) / (i)\n          stat['cpu_samples'][name] = []\n\n        msg = 'avg: {1:.2%}, min: {2:.2%}, max: {3:.2%} {0}'.format(os.path.basename(k), stat['avg']['total'], stat['min']['total'], stat['max']['total'])\n        if args.detailed_times:\n          for stat_type in ['avg', 'min', 'max']:\n            msg += '\\n {}: {}'.format(stat_type, [name + ':' + str(round(stat[stat_type][name]*100, 2)) for name in cpu_time_names])\n        l.append((os.path.basename(k), stat['avg']['total'], msg))\n      l.sort(key=lambda x: -x[1])\n      for x in l:\n        print(x[2])\n      print('avg sum: {0:.2%} over {1} samples {2} seconds\\n'.format(\n        sum([stat['avg']['total'] for k, stat in stats.items()]), i, i * SLEEP_INTERVAL\n      ))\n"
  },
  {
    "path": "selfdrive/debug/cycle_alerts.py",
    "content": "#!/usr/bin/env python3\n# flake8: noqa\n# pylint: skip-file\n# type: ignore\n\nimport time\n\nfrom cereal import car\nimport cereal.messaging as messaging\nfrom selfdrive.car.honda.interface import CarInterface\nfrom selfdrive.controls.lib.events import ET, EVENTS, Events\nfrom selfdrive.controls.lib.alertmanager import AlertManager\n\nEventName = car.CarEvent.EventName\n\ndef cycle_alerts(duration=2000, is_metric=False):\n  alerts = list(EVENTS.keys())\n  print(alerts)\n\n  #alerts = [EventName.preDriverDistracted, EventName.promptDriverDistracted, EventName.driverDistracted]\n  alerts = [EventName.preLaneChangeLeft, EventName.preLaneChangeRight]\n\n  CP = CarInterface.get_params(\"HONDA CIVIC 2016\")\n  sm = messaging.SubMaster(['deviceState', 'pandaState', 'roadCameraState', 'modelV2', 'liveCalibration',\n                            'driverMonitoringState', 'longitudinalPlan', 'lateralPlan', 'liveLocationKalman'])\n\n  pm = messaging.PubMaster(['controlsState', 'pandaState', 'deviceState'])\n\n  events = Events()\n  AM = AlertManager()\n\n  frame = 0\n  idx, last_alert_millis = 0, 0\n  while 1:\n    if frame % duration == 0:\n      idx = (idx + 1) % len(alerts)\n      events.clear()\n      events.add(alerts[idx])\n\n\n    current_alert_types = [ET.PERMANENT, ET.USER_DISABLE, ET.IMMEDIATE_DISABLE,\n                           ET.SOFT_DISABLE, ET.PRE_ENABLE, ET.NO_ENTRY,\n                           ET.ENABLE, ET.WARNING]\n    a = events.create_alerts(current_alert_types, [CP, sm, is_metric])\n    AM.add_many(frame, a)\n    AM.process_alerts(frame)\n\n    dat = messaging.new_message()\n    dat.init('controlsState')\n    dat.controlsState.alertText1 = AM.alert_text_1\n    dat.controlsState.alertText2 = AM.alert_text_2\n    dat.controlsState.alertSize = AM.alert_size\n    dat.controlsState.alertStatus = AM.alert_status\n    dat.controlsState.alertBlinkingRate = AM.alert_rate\n    dat.controlsState.alertType = AM.alert_type\n    dat.controlsState.alertSound = AM.audible_alert\n    pm.send('controlsState', dat)\n\n    dat = messaging.new_message()\n    dat.init('deviceState')\n    dat.deviceState.started = True\n    pm.send('deviceState', dat)\n\n    dat = messaging.new_message()\n    dat.init('pandaState')\n    dat.pandaState.ignitionLine = True\n    pm.send('pandaState', dat)\n\n    time.sleep(0.01)\n\nif __name__ == '__main__':\n  cycle_alerts()\n"
  },
  {
    "path": "selfdrive/debug/disable_ecu.py",
    "content": "#!/usr/bin/env python3\nimport traceback\n\nimport cereal.messaging as messaging\nfrom selfdrive.car.isotp_parallel_query import IsoTpParallelQuery\nfrom selfdrive.swaglog import cloudlog\n\nEXT_DIAG_REQUEST = b'\\x10\\x03'\nEXT_DIAG_RESPONSE = b'\\x50\\x03'\nCOM_CONT_REQUEST = b'\\x28\\x83\\x03'\nCOM_CONT_RESPONSE = b''\n\ndef disable_ecu(ecu_addr, logcan, sendcan, bus, timeout=0.1, retry=5, debug=False):\n  print(f\"ecu disable {hex(ecu_addr)} ...\")\n  for i in range(retry):\n    try:\n      # enter extended diagnostic session\n      query = IsoTpParallelQuery(sendcan, logcan, bus, [ecu_addr], [EXT_DIAG_REQUEST], [EXT_DIAG_RESPONSE], debug=debug)\n      for addr, dat in query.get_data(timeout).items(): # pylint: disable=unused-variable\n        print(\"ecu communication control disable tx/rx ...\")\n        # communication control disable tx and rx\n        query = IsoTpParallelQuery(sendcan, logcan, bus, [ecu_addr], [COM_CONT_REQUEST], [COM_CONT_RESPONSE], debug=debug)\n        query.get_data(0)\n        return True\n      print(f\"ecu disable retry ({i+1}) ...\")\n    except Exception:\n      cloudlog.warning(f\"ecu disable exception: {traceback.format_exc()}\")\n\n  return False\n\n\nif __name__ == \"__main__\":\n  import time\n  sendcan = messaging.pub_sock('sendcan')\n  logcan = messaging.sub_sock('can')\n  time.sleep(1)\n\n  # honda bosch radar disable\n  disabled = disable_ecu(0x18DAB0F1, logcan, sendcan, 1, debug=False)\n  print(f\"disabled: {disabled}\")\n"
  },
  {
    "path": "selfdrive/debug/dump.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport sys\nimport argparse\nimport json\nfrom hexdump import hexdump\nimport codecs\ncodecs.register_error(\"strict\", codecs.backslashreplace_errors)\n\nfrom cereal import log\nimport cereal.messaging as messaging\nfrom cereal.services import service_list\n\nif __name__ == \"__main__\":\n\n  parser = argparse.ArgumentParser(description='Sniff a communcation socket')\n  parser.add_argument('--pipe', action='store_true')\n  parser.add_argument('--raw', action='store_true')\n  parser.add_argument('--json', action='store_true')\n  parser.add_argument('--dump-json', action='store_true')\n  parser.add_argument('--no-print', action='store_true')\n  parser.add_argument('--addr', default='127.0.0.1')\n  parser.add_argument('--values', help='values to monitor (instead of entire event)')\n  parser.add_argument(\"socket\", type=str, nargs='*', help=\"socket name\")\n  args = parser.parse_args()\n\n  if args.addr != \"127.0.0.1\":\n    os.environ[\"ZMQ\"] = \"1\"\n    messaging.context = messaging.Context()\n\n  poller = messaging.Poller()\n\n  for m in args.socket if len(args.socket) > 0 else service_list:\n    messaging.sub_sock(m, poller, addr=args.addr)\n\n  values = None\n  if args.values:\n    values = [s.strip().split(\".\") for s in args.values.split(\",\")]\n\n  while 1:\n    polld = poller.poll(100)\n    for sock in polld:\n      msg = sock.receive()\n      evt = log.Event.from_bytes(msg)\n\n      if not args.no_print:\n        if args.pipe:\n          sys.stdout.write(msg)\n          sys.stdout.flush()\n        elif args.raw:\n          hexdump(msg)\n        elif args.json:\n          print(json.loads(msg))\n        elif args.dump_json:\n          print(json.dumps(evt.to_dict()))\n        elif values:\n          print(\"logMonotime = {}\".format(evt.logMonoTime))\n          for value in values:\n            if hasattr(evt, value[0]):\n              item = evt\n              for key in value:\n                item = getattr(item, key)\n              print(\"{} = {}\".format(\".\".join(value), item))\n          print(\"\")\n        else:\n          try:\n            print(evt)\n          except UnicodeDecodeError:\n            w = evt.which()\n            s = f\"( logMonoTime {evt.logMonoTime} \\n  {w} = \"\n            s += str(evt.__getattr__(w))\n            s += f\"\\n  valid = {evt.valid} )\"\n            print(s)\n"
  },
  {
    "path": "selfdrive/debug/filter_log_message.py",
    "content": "#!/usr/bin/env python3\nimport argparse\nimport json\n\nimport cereal.messaging as messaging\nfrom tools.lib.logreader import LogReader\nfrom tools.lib.route import Route\n\nLEVELS = {\n  \"DEBUG\": 10,\n  \"INFO\": 20,\n  \"WARNING\": 30,\n  \"ERROR\": 40,\n  \"CRITICAL\": 50,\n}\n\nANDROID_LOG_SOURCE = {\n  0: \"MAIN\",\n  1: \"RADIO\",\n  2: \"EVENTS\",\n  3: \"SYSTEM\",\n  4: \"CRASH\",\n  5: \"KERNEL\",\n}\n\n\ndef print_logmessage(t, msg, min_level):\n  try:\n    log = json.loads(msg)\n    if log['levelnum'] >= min_level:\n      print(f\"[{t / 1e9:.6f}] {log['filename']}:{log.get('lineno', '')} - {log.get('funcname', '')}: {log['msg']}\")\n      if 'exc_info' in log:\n        print(log['exc_info'])\n  except json.decoder.JSONDecodeError:\n    print(f\"[{t / 1e9:.6f}] decode error: {msg}\")\n\n\ndef print_androidlog(t, msg):\n  source = ANDROID_LOG_SOURCE[msg.id]\n  try:\n    m = json.loads(msg.message)['MESSAGE']\n  except Exception:\n    m = msg.message\n\n  print(f\"[{t / 1e9:.6f}] {source} {msg.pid} {msg.tag} - {m}\")\n\n\nif __name__ == \"__main__\":\n\n  parser = argparse.ArgumentParser()\n  parser.add_argument('--level', default='DEBUG')\n  parser.add_argument('--addr', default='127.0.0.1')\n  parser.add_argument(\"route\", type=str, nargs='*', help=\"route name + segment number for offline usage\")\n  args = parser.parse_args()\n\n  logs = None\n  if len(args.route):\n    r = Route(args.route[0])\n    logs = [q if r is None else r for (q, r) in zip(r.qlog_paths(), r.log_paths())]\n\n  if len(args.route) == 2 and logs:\n    n = int(args.route[1])\n    logs = [logs[n]]\n\n  min_level = LEVELS[args.level]\n\n  if logs:\n    for log in logs:\n      if log:\n        lr = LogReader(log)\n        for m in lr:\n          if m.which() == 'logMessage':\n            print_logmessage(m.logMonoTime, m.logMessage, min_level)\n          elif m.which() == 'androidLog':\n            print_androidlog(m.logMonoTime, m.androidLog)\n  else:\n    sm = messaging.SubMaster(['logMessage', 'androidLog'], addr=args.addr)\n    while True:\n      sm.update()\n\n      if sm.updated['logMessage']:\n        print_logmessage(sm.logMonoTime['logMessage'], sm['logMessage'], min_level)\n\n      if sm.updated['androidLog']:\n        print_androidlog(sm.logMonoTime['androidLog'], sm['androidLog'])\n"
  },
  {
    "path": "selfdrive/debug/fingerprint_from_route.py",
    "content": "#!/usr/bin/env python3\n\nimport sys\nfrom tools.lib.route import Route\nfrom tools.lib.logreader import MultiLogIterator\n\n\ndef get_fingerprint(lr):\n  # TODO: make this a nice tool for car ports. should also work with qlogs for FW\n\n  fw = None\n  msgs = {}\n  for msg in lr:\n    if msg.which() == 'carParams':\n      fw = msg.carParams.carFw\n    elif msg.which() == 'can':\n      for c in msg.can:\n        # read also msgs sent by EON on CAN bus 0x80 and filter out the\n        # addr with more than 11 bits\n        if c.src % 0x80 == 0 and c.address < 0x800:\n          msgs[c.address] = len(c.dat)\n\n  # show CAN fingerprint\n  fingerprint = ', '.join(\"%d: %d\" % v for v in sorted(msgs.items()))\n  print(f\"\\nfound {len(msgs)} messages. CAN fingerprint:\\n\")\n  print(fingerprint)\n\n  # TODO: also print the fw fingerprint merged with the existing ones\n  # show FW fingerprint\n  print(\"\\nFW fingerprint:\\n\")\n  for f in fw:\n    print(f\"    (Ecu.{f.ecu}, {hex(f.address)}, {None if f.subAddress == 0 else f.subAddress}): [\")\n    print(f\"      {f.fwVersion},\")\n    print(\"    ],\")\n  print()\n\n\nif __name__ == \"__main__\":\n  if len(sys.argv) < 2:\n    print(\"Usage: ./fingerprint_from_route.py <route>\")\n    sys.exit(1)\n\n  route = Route(sys.argv[1])\n  lr = MultiLogIterator(route.log_paths()[:5], wraparound=False)\n  get_fingerprint(lr)\n"
  },
  {
    "path": "selfdrive/debug/get_fingerprint.py",
    "content": "#!/usr/bin/env python3\n\n# simple script to get a vehicle fingerprint.\n\n# Instructions:\n# - connect to a Panda\n# - run selfdrive/boardd/boardd\n# - launching this script\n#   Note: it's very important that the car is in stock mode, in order to collect a complete fingerprint\n# - since some messages are published at low frequency, keep this script running for at least 30s,\n#   until all messages are received at least once\n\nimport cereal.messaging as messaging\n\nlogcan = messaging.sub_sock('can')\nmsgs = {}\nwhile True:\n  lc = messaging.recv_sock(logcan, True)\n  if lc is None:\n    continue\n\n  for c in lc.can:\n    # read also msgs sent by EON on CAN bus 0x80 and filter out the\n    # addr with more than 11 bits\n    if c.src in [0, 2] and c.address < 0x800:\n      msgs[c.address] = len(c.dat)\n\n  fingerprint = ', '.join(\"%d: %d\" % v for v in sorted(msgs.items()))\n\n  print(\"number of messages {0}:\".format(len(msgs)))\n  print(\"fingerprint {0}\".format(fingerprint))\n"
  },
  {
    "path": "selfdrive/debug/live_cpu_and_temp.py",
    "content": "#!/usr/bin/env python3\nimport argparse\n\nfrom cereal.messaging import SubMaster\nfrom common.numpy_fast import mean\n\n\ndef cputime_total(ct):\n  return ct.user + ct.nice + ct.system + ct.idle + ct.iowait + ct.irq + ct.softirq\n\n\ndef cputime_busy(ct):\n  return ct.user + ct.nice + ct.system + ct.irq + ct.softirq\n\n\ndef proc_cputime_total(ct):\n  return ct.cpuUser + ct.cpuSystem + ct.cpuChildrenUser + ct.cpuChildrenSystem\n\n\ndef proc_name(proc):\n  name = proc.name\n  if len(proc.cmdline):\n    name = proc.cmdline[0]\n  if len(proc.exe):\n    name = proc.exe + \" - \" + name\n\n  return name\n\n\nif __name__ == \"__main__\":\n  parser = argparse.ArgumentParser()\n  parser.add_argument('--mem', action='store_true')\n  parser.add_argument('--cpu', action='store_true')\n  args = parser.parse_args()\n\n  sm = SubMaster(['deviceState', 'procLog'])\n\n  last_temp = 0.0\n  last_mem = 0.0\n  total_times = [0., 0., 0., 0.]\n  busy_times = [0., 0., 0.0, 0.]\n\n  prev_proclog = None\n  prev_proclog_t = None\n\n  while True:\n    sm.update()\n\n    if sm.updated['deviceState']:\n      t = sm['deviceState']\n      last_temp = mean(t.cpuTempC)\n      last_mem = t.memoryUsagePercent\n\n    if sm.updated['procLog']:\n      m = sm['procLog']\n\n      cores = [0., 0., 0., 0.]\n      total_times_new = [0., 0., 0., 0.]\n      busy_times_new = [0., 0., 0.0, 0.]\n\n      for c in m.cpuTimes:\n        n = c.cpuNum\n        total_times_new[n] = cputime_total(c)\n        busy_times_new[n] = cputime_busy(c)\n\n      for n in range(4):\n        t_busy = busy_times_new[n] - busy_times[n]\n        t_total = total_times_new[n] - total_times[n]\n        cores[n] = t_busy / t_total\n\n      total_times = total_times_new[:]\n      busy_times = busy_times_new[:]\n\n      print(\"CPU %.2f%% - RAM: %.2f - Temp %.2f\" % (100. * mean(cores), last_mem, last_temp))\n\n      if args.cpu and prev_proclog is not None:\n        procs = {}\n        dt = (sm.logMonoTime['procLog'] - prev_proclog_t) / 1e9\n        for proc in m.procs:\n          try:\n            name = proc_name(proc)\n            prev_proc = [p for p in prev_proclog.procs if proc.pid == p.pid][0]\n            cpu_time = proc_cputime_total(proc) - proc_cputime_total(prev_proc)\n            cpu_usage = cpu_time / dt * 100.\n            procs[name] = cpu_usage\n          except IndexError:\n            pass\n\n        print(\"Top CPU usage:\")\n        for k, v in sorted(procs.items(), key=lambda item: item[1], reverse=True)[:10]:\n          print(f\"{k.rjust(70)}   {v:.2f} %\")\n        print()\n\n      if args.mem:\n        mems = {}\n        for proc in m.procs:\n          name = proc_name(proc)\n          mems[name] = float(proc.memRss) / 1e6\n        print(\"Top memory usage:\")\n        for k, v in sorted(mems.items(), key=lambda item: item[1], reverse=True)[:10]:\n          print(f\"{k.rjust(70)}   {v:.2f} MB\")\n        print()\n\n      prev_proclog = m\n      prev_proclog_t = sm.logMonoTime['procLog']\n"
  },
  {
    "path": "selfdrive/debug/run_process_on_route.py",
    "content": "#!/usr/bin/env python3\n\nimport argparse\n\nfrom selfdrive.test.process_replay.compare_logs import save_log\nfrom selfdrive.test.process_replay.process_replay import CONFIGS, replay_process\nfrom tools.lib.logreader import MultiLogIterator\nfrom tools.lib.route import Route\n\nif __name__ == \"__main__\":\n  parser = argparse.ArgumentParser(description=\"Run process on route and create new logs\",\n                                   formatter_class=argparse.ArgumentDefaultsHelpFormatter)\n  parser.add_argument(\"route\", help=\"The route name to use\")\n  parser.add_argument(\"process\", help=\"The process to run\")\n  args = parser.parse_args()\n\n  cfg = [c for c in CONFIGS if c.proc_name == args.process][0]\n\n  route = Route(args.route)\n  lr = MultiLogIterator(route.log_paths(), wraparound=False)\n  inputs = list(lr)\n\n  outputs = replay_process(cfg, inputs)\n\n  # Remove message generated by the process under test and merge in the new messages\n  produces = set(o.which() for o in outputs)\n  inputs = [i for i in inputs if i.which() not in produces]\n  outputs = sorted(inputs + outputs, key=lambda x: x.logMonoTime)\n\n  fn = f\"{args.route}_{args.process}.bz2\"\n  save_log(fn, outputs)\n"
  },
  {
    "path": "selfdrive/debug/set_car_params.py",
    "content": "#!/usr/bin/env python3\nimport sys\n\nfrom common.params import Params\nfrom tools.lib.route import Route\nfrom tools.lib.logreader import LogReader\n\nif __name__ == \"__main__\":\n  r = Route(sys.argv[1])\n  cp = [m for m in LogReader(r.qlog_paths()[0]) if m.which() == 'carParams']\n  Params().put(\"CarParams\", cp[0].carParams.as_builder().to_bytes())\n"
  },
  {
    "path": "selfdrive/debug/show_matching_cars.py",
    "content": "#!/usr/bin/env python3\nfrom selfdrive.car.fingerprints import eliminate_incompatible_cars, all_legacy_fingerprint_cars\nimport cereal.messaging as messaging\n\n\n# rav4 2019 and corolla tss2\nfingerprint = {896: 8, 898: 8, 900: 6, 976: 1, 1541: 8, 902: 6, 905: 8, 810: 2, 1164: 8, 1165: 8, 1166: 8, 1167: 8, 1552: 8, 1553: 8, 1556: 8, 1571: 8, 921: 8, 1056: 8, 544: 4, 1570: 8, 1059: 1, 36: 8, 37: 8, 550: 8, 935: 8, 552: 4, 170: 8, 812: 8, 944: 8, 945: 8, 562: 6, 180: 8, 1077: 8, 951: 8, 1592: 8, 1076: 8, 186: 4, 955: 8, 956: 8, 1001: 8, 705: 8, 452: 8, 1788: 8, 464: 8, 824: 8, 466: 8, 467: 8, 761: 8, 728: 8, 1572: 8, 1114: 8, 933: 8, 800: 8, 608: 8, 865: 8, 610: 8, 1595: 8, 934: 8, 998: 5, 1745: 8, 1000: 8, 764: 8, 1002: 8, 999: 7, 1789: 8, 1649: 8, 1779: 8, 1568: 8, 1017: 8, 1786: 8, 1787: 8, 1020: 8, 426: 6, 1279: 8}\n\ncandidate_cars = all_legacy_fingerprint_cars()\n\n\nfor addr, l in fingerprint.items():\n    dat = messaging.new_message('can', 1)\n\n    msg = dat.can[0]\n    msg.address = addr\n    msg.dat = \" \" * l\n\n    candidate_cars = eliminate_incompatible_cars(msg, candidate_cars)\n    print(candidate_cars)\n"
  },
  {
    "path": "selfdrive/debug/test_fw_query_on_routes.py",
    "content": "#!/usr/bin/env python3\n# type: ignore\n\nfrom collections import defaultdict\nimport argparse\nimport os\nimport traceback\nfrom tqdm import tqdm\nfrom tools.lib.logreader import LogReader\nfrom tools.lib.route import Route\nfrom selfdrive.car.car_helpers import interface_names\nfrom selfdrive.car.fw_versions import match_fw_to_car_exact, match_fw_to_car_fuzzy, build_fw_dict\nfrom selfdrive.car.toyota.values import FW_VERSIONS as TOYOTA_FW_VERSIONS\nfrom selfdrive.car.honda.values import FW_VERSIONS as HONDA_FW_VERSIONS\nfrom selfdrive.car.hyundai.values import FW_VERSIONS as HYUNDAI_FW_VERSIONS\nfrom selfdrive.car.volkswagen.values import FW_VERSIONS as VW_FW_VERSIONS\nfrom selfdrive.car.mazda.values import FW_VERSIONS as MAZDA_FW_VERSIONS\n\n\nNO_API = \"NO_API\" in os.environ\nSUPPORTED_CARS = set(interface_names['toyota'])\nSUPPORTED_CARS |= set(interface_names['honda'])\nSUPPORTED_CARS |= set(interface_names['hyundai'])\nSUPPORTED_CARS |= set(interface_names['volkswagen'])\nSUPPORTED_CARS |= set(interface_names['mazda'])\n\ntry:\n  from xx.pipeline.c.CarState import migration\nexcept ImportError:\n  migration = {}\n\nif __name__ == \"__main__\":\n  parser = argparse.ArgumentParser(description='Run FW fingerprint on Qlog of route or list of routes')\n  parser.add_argument('route', help='Route or file with list of routes')\n  parser.add_argument('--car', help='Force comparison fingerprint to known car')\n  args = parser.parse_args()\n\n  if os.path.exists(args.route):\n    routes = list(open(args.route))\n  else:\n    routes = [args.route]\n\n  mismatches = defaultdict(list)\n\n  not_fingerprinted = 0\n  solved_by_fuzzy = 0\n\n  good_exact = 0\n  wrong_fuzzy = 0\n  good_fuzzy = 0\n\n  dongles = []\n  for route in tqdm(routes):\n    route = route.rstrip()\n    dongle_id, time = route.split('|')\n\n    if dongle_id in dongles:\n      continue\n\n    if NO_API:\n      qlog_path = f\"cd:/{dongle_id}/{time}/0/qlog.bz2\"\n    else:\n      route = Route(route)\n      qlog_path = route.qlog_paths()[0]\n\n    if qlog_path is None:\n      continue\n\n    try:\n      lr = LogReader(qlog_path)\n      dongles.append(dongle_id)\n\n      for msg in lr:\n        if msg.which() == \"pandaState\":\n          if msg.pandaState.pandaType not in ['uno', 'blackPanda', 'dos']:\n            break\n\n        elif msg.which() == \"carParams\":\n          bts = msg.carParams.as_builder().to_bytes()\n\n          car_fw = msg.carParams.carFw\n          if len(car_fw) == 0:\n            break\n\n          live_fingerprint = msg.carParams.carFingerprint\n          live_fingerprint = migration.get(live_fingerprint, live_fingerprint)\n\n          if args.car is not None:\n            live_fingerprint = args.car\n\n          if live_fingerprint not in SUPPORTED_CARS:\n            break\n\n          fw_versions_dict = build_fw_dict(car_fw)\n          exact_matches = match_fw_to_car_exact(fw_versions_dict)\n          fuzzy_matches = match_fw_to_car_fuzzy(fw_versions_dict)\n\n          if (len(exact_matches) == 1) and (list(exact_matches)[0] == live_fingerprint):\n            good_exact += 1\n            print(f\"Correct! Live: {live_fingerprint} - Fuzzy: {fuzzy_matches}\")\n\n            # Check if fuzzy match was correct\n            if len(fuzzy_matches) == 1:\n              if list(fuzzy_matches)[0] != live_fingerprint:\n                wrong_fuzzy += 1\n                print(f\"{dongle_id}|{time}\")\n                print(\"Fuzzy match wrong! Fuzzy:\", fuzzy_matches, \"Live:\", live_fingerprint)\n              else:\n                good_fuzzy += 1\n            break\n\n          print(f\"{dongle_id}|{time}\")\n          print(\"Old style:\", live_fingerprint, \"Vin\", msg.carParams.carVin)\n          print(\"New style (exact):\", exact_matches)\n          print(\"New style (fuzzy):\", fuzzy_matches)\n\n          for version in car_fw:\n            subaddr = None if version.subAddress == 0 else hex(version.subAddress)\n            print(f\"  (Ecu.{version.ecu}, {hex(version.address)}, {subaddr}): [{version.fwVersion}],\")\n\n          print(\"Mismatches\")\n          found = False\n          for car_fws in [TOYOTA_FW_VERSIONS, HONDA_FW_VERSIONS, HYUNDAI_FW_VERSIONS, VW_FW_VERSIONS, MAZDA_FW_VERSIONS]:\n            if live_fingerprint in car_fws:\n              found = True\n              expected = car_fws[live_fingerprint]\n              for (_, expected_addr, expected_sub_addr), v in expected.items():\n                for version in car_fw:\n                  sub_addr = None if version.subAddress == 0 else version.subAddress\n                  addr = version.address\n\n                  if (addr, sub_addr) == (expected_addr, expected_sub_addr):\n                    if version.fwVersion not in v:\n                      print(f\"({hex(addr)}, {'None' if sub_addr is None else hex(sub_addr)}) - {version.fwVersion}\")\n\n                      # Add to global list of mismatches\n                      mismatch = (addr, sub_addr, version.fwVersion)\n                      if mismatch not in mismatches[live_fingerprint]:\n                        mismatches[live_fingerprint].append(mismatch)\n\n          # No FW versions for this car yet, add them all to mismatch list\n          if not found:\n            for version in car_fw:\n              sub_addr = None if version.subAddress == 0 else version.subAddress\n              addr = version.address\n              mismatch = (addr, sub_addr, version.fwVersion)\n              if mismatch not in mismatches[live_fingerprint]:\n                mismatches[live_fingerprint].append(mismatch)\n\n          print()\n          not_fingerprinted += 1\n\n          if len(fuzzy_matches) == 1:\n            if list(fuzzy_matches)[0] == live_fingerprint:\n              solved_by_fuzzy += 1\n            else:\n              wrong_fuzzy += 1\n              print(\"Fuzzy match wrong! Fuzzy:\", fuzzy_matches, \"Live:\", live_fingerprint)\n\n          break\n    except Exception:\n      traceback.print_exc()\n    except KeyboardInterrupt:\n      break\n\n  print()\n  # Print FW versions that need to be added seperated out by car and address\n  for car, m in sorted(mismatches.items()):\n    print(car)\n    addrs = defaultdict(list)\n    for (addr, sub_addr, version) in m:\n      addrs[(addr, sub_addr)].append(version)\n\n    for (addr, sub_addr), versions in addrs.items():\n      print(f\"  ({hex(addr)}, {'None' if sub_addr is None else hex(sub_addr)}): [\")\n      for v in versions:\n        print(f\"    {v},\")\n      print(\"  ]\")\n    print()\n\n  print()\n  print(f\"Number of dongle ids checked: {len(dongles)}\")\n  print(f\"Fingerprinted:                {good_exact}\")\n  print(f\"Not fingerprinted:            {not_fingerprinted}\")\n  print(f\"  of which had a fuzzy match: {solved_by_fuzzy}\")\n\n  print()\n  print(f\"Correct fuzzy matches:        {good_fuzzy}\")\n  print(f\"Wrong fuzzy matches:          {wrong_fuzzy}\")\n  print()\n\n"
  },
  {
    "path": "selfdrive/debug/toyota_eps_factor.py",
    "content": "#!/usr/bin/env python3\nimport sys\nimport numpy as np\nimport matplotlib.pyplot as plt\nfrom sklearn import linear_model  # pylint: disable=import-error\nfrom selfdrive.car.toyota.values import STEER_THRESHOLD\n\nfrom tools.lib.route import Route\nfrom tools.lib.logreader import MultiLogIterator\n\nMIN_SAMPLES = 30 * 100\n\n\ndef to_signed(n, bits):\n  if n >= (1 << max((bits - 1), 0)):\n    n = n - (1 << max(bits, 0))\n  return n\n\n\ndef get_eps_factor(lr, plot=False):\n  engaged = False\n  steering_pressed = False\n  torque_cmd, eps_torque = None, None\n  cmds, eps = [], []\n\n  for msg in lr:\n    if msg.which() != 'can':\n      continue\n\n    for m in msg.can:\n      if m.address == 0x2e4 and m.src == 128:\n        engaged = bool(m.dat[0] & 1)\n        torque_cmd = to_signed((m.dat[1] << 8) | m.dat[2], 16)\n      elif m.address == 0x260 and m.src == 0:\n        eps_torque = to_signed((m.dat[5] << 8) | m.dat[6], 16)\n        steering_pressed = abs(to_signed((m.dat[1] << 8) | m.dat[2], 16)) > STEER_THRESHOLD\n\n    if engaged and torque_cmd is not None and eps_torque is not None and not steering_pressed:\n      cmds.append(torque_cmd)\n      eps.append(eps_torque)\n    else:\n      if len(cmds) > MIN_SAMPLES:\n        break\n      cmds, eps = [], []\n\n  if len(cmds) < MIN_SAMPLES:\n    raise Exception(\"too few samples found in route\")\n\n  lm = linear_model.LinearRegression(fit_intercept=False)\n  lm.fit(np.array(cmds).reshape(-1, 1), eps)\n  scale_factor = 1. / lm.coef_[0]\n\n  if plot:\n    plt.plot(np.array(eps) * scale_factor)\n    plt.plot(cmds)\n    plt.show()\n  return scale_factor\n\n\nif __name__ == \"__main__\":\n  r = Route(sys.argv[1])\n  lr = MultiLogIterator(r.log_paths(), wraparound=False)\n  n = get_eps_factor(lr, plot=\"--plot\" in sys.argv)\n  print(\"EPS torque factor: \", n)\n"
  },
  {
    "path": "selfdrive/debug/uiview.py",
    "content": "#!/usr/bin/env python3\nimport time\nimport cereal.messaging as messaging\nfrom selfdrive.manager.process_config import managed_processes\n\nif __name__ == \"__main__\":\n  services = ['controlsState', 'deviceState', 'pandaState']  # the services needed to be spoofed to start ui offroad\n  procs = ['camerad', 'ui', 'modeld', 'calibrationd']\n\n  for p in procs:\n    managed_processes[p].start()\n\n  pm = messaging.PubMaster(services)\n\n  msgs = {s: messaging.new_message(s) for s in services}\n  msgs['deviceState'].deviceState.started = True\n  msgs['pandaState'].pandaState.ignitionLine = True\n\n  try:\n    while True:\n      time.sleep(1 / 100)  # continually send, rate doesn't matter\n      for s in msgs:\n        pm.send(s, msgs[s])\n  except KeyboardInterrupt:\n    for p in procs:\n      managed_processes[p].stop()\n"
  },
  {
    "path": "selfdrive/dragonpilot/HOWTO-APPD.md",
    "content": "What is appd\n------\nAppd is a service that runs specific android apps when on road, and then close the when offroad.\n\nHow to use appd\n------\n1. Create a folder: /data/media/0/appd/\n2. Place apks in /data/media/0/appd/\n3. Copy /data/openpilot/dragonpilot/appd_example.json over to /data/media/0/appd/ and rename to appd.json\n4. Update appd.json as per example."
  },
  {
    "path": "selfdrive/dragonpilot/LICENSE.md",
    "content": "The MIT License\n\nCopyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE."
  },
  {
    "path": "selfdrive/dragonpilot/appd.py",
    "content": "#!/usr/bin/env python3.8\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\nimport subprocess\nimport os\nimport json\n\nFILE = '/data/media/0/appd/appd.json'\n\nclass Appd():\n\n  def __init__(self):\n    self.started = False\n\n    if os.path.exists(FILE):\n      with open(FILE) as f:\n        self.app_data = json.load(f)\n    else:\n      self.app_data = None\n\n  def update(self, started):\n    if self.app_data is not None:\n      if started:\n        if not self.started:\n          self.started = True\n          self.onroad()\n      else:\n        if self.started:\n          self.started = False\n          self.offroad()\n\n  def onroad(self):\n    for app in self.app_data:\n      if app['app'] == 'lan.rick.pandagpsservice' and self.installed(app['app']):\n        self.system('pm uninstall lan.rick.pandagpsservice')\n        pass\n      if not self.installed(app['app']) and os.path.exists(app['apk']):\n        self.system(\"pm install -r %s\" % app['apk'])\n      for cmd in app['onroad_cmd']:\n        self.system(cmd)\n\n  def offroad(self):\n    for app in self.app_data:\n      if self.installed(app['app']):\n        for cmd in app['offroad_cmd']:\n          self.system(cmd)\n\n  def installed(self, app_name):\n    try:\n      result = subprocess.check_output([\"dumpsys\", \"package\", app_name, \"|\", \"grep\", \"versionName\"], encoding='utf8')\n      if len(result) > 12:\n        return True\n    except:\n      pass\n    return False\n\n  def system(self, cmd):\n    try:\n      subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True)\n    except:\n      pass"
  },
  {
    "path": "selfdrive/dragonpilot/appd_example.json",
    "content": "[\n  {\n    \"app\": \"com.tomtom.speedcams.android.map\",\n    \"apk\": \"/data/media/0/appd/com.tomtom.speedcams.android.map.apk\",\n    \"offroad_cmd\": [\n      \"pm disable com.tomtom.speedcams.android.map\"\n    ],\n    \"onroad_cmd\": [\n      \"pm enable com.tomtom.speedcams.android.map\",\n      \"LD_LIBRARY_PATH= appops set com.tomtom.speedcams.android.map android.permission.ACCESS_FINE_LOCATION allow\",\n      \"LD_LIBRARY_PATH= appops set com.tomtom.speedcams.android.map android.permission.ACCESS_COARSE_LOCATION allow\",\n      \"LD_LIBRARY_PATH= appops set com.tomtom.speedcams.android.map android.permission.READ_EXTERNAL_STORAGE allow\",\n      \"LD_LIBRARY_PATH= appops set com.tomtom.speedcams.android.map android.permission.WRITE_EXTERNAL_STORAGE allow\",\n      \"am start -n com.tomtom.speedcams.android.map/com.tomtom.speedcams.android.activities.SpeedCamActivity\"\n    ]\n  }\n]"
  },
  {
    "path": "selfdrive/dragonpilot/dashcamd.py",
    "content": "#!/usr/bin/env python3.7\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\nimport os\nimport datetime\nfrom common.realtime import sec_since_boot\n\nDASHCAM_VIDEOS_PATH = '/data/media/0/dashcam/'\nDASHCAM_DURATION = 180 # max is 180\nDASHCAM_BIT_RATES = 4000000 # max is 4000000\nDASHCAM_MAX_SIZE_PER_FILE = DASHCAM_BIT_RATES/8*DASHCAM_DURATION # 4Mbps / 8 * 180 = 90MB per 180 seconds\nDASHCAM_FREESPACE_LIMIT = 0.15 # we start cleaning up footage when freespace is below 15%\nDASHCAM_KEPT = DASHCAM_MAX_SIZE_PER_FILE * 240 # 12 hrs of video = 21GB\n\nclass Dashcamd():\n  def __init__(self):\n    self.dashcam_folder_exists = False\n    self.dashcam_mkdir_retry = 0\n    self.dashcam_next_time = 0\n    self.started = False\n    self.free_space = 1.\n\n  def run(self, started, free_space):\n    self.free_space = free_space\n    if self.started and not started:\n      self.stop()\n    self.started = started\n    self.make_folder()\n    if self.dashcam_folder_exists:\n      self.start()\n      self.clean_up()\n\n  def stop(self):\n    os.system(\"killall -SIGINT screenrecord\")\n    self.dashcam_next_time = 0\n\n  def make_folder(self):\n    if not self.dashcam_folder_exists and self.dashcam_mkdir_retry <= 5:\n      # create dashcam folder if not exist\n      try:\n        if not os.path.exists(DASHCAM_VIDEOS_PATH):\n          os.makedirs(DASHCAM_VIDEOS_PATH)\n        else:\n          self.dashcam_folder_exists = True\n      except OSError:\n        self.dashcam_folder_exists = False\n        self.dashcam_mkdir_retry += 1\n\n  def start(self):\n    # start recording\n    if self.started:\n      ts = sec_since_boot()\n      if ts >= self.dashcam_next_time:\n        now = datetime.datetime.now()\n        file_name = now.strftime(\"%Y-%m-%d_%H-%M-%S\")\n        os.system(\"LD_LIBRARY_PATH= screenrecord --bit-rate %s --time-limit %s %s%s.mp4 &\" % (DASHCAM_BIT_RATES, DASHCAM_DURATION, DASHCAM_VIDEOS_PATH, file_name))\n        self.dashcam_next_time = ts + DASHCAM_DURATION - 1\n    else:\n      self.dashcam_next_time = 0\n\n  def clean_up(self):\n    # clean up\n    if (self.free_space < DASHCAM_FREESPACE_LIMIT) or (self.get_used_spaces() > DASHCAM_KEPT):\n      try:\n        files = [f for f in sorted(os.listdir(DASHCAM_VIDEOS_PATH)) if os.path.isfile(DASHCAM_VIDEOS_PATH + f)]\n        os.system(\"rm -fr %s &\" % (DASHCAM_VIDEOS_PATH + files[0]))\n      except (IndexError, FileNotFoundError, OSError):\n        pass\n\n  def get_used_spaces(self):\n    try:\n      val = sum(os.path.getsize(DASHCAM_VIDEOS_PATH + f) for f in os.listdir(DASHCAM_VIDEOS_PATH) if os.path.isfile(DASHCAM_VIDEOS_PATH + f))\n    except (IndexError, FileNotFoundError, OSError):\n      val = 0\n    return val"
  },
  {
    "path": "selfdrive/dragonpilot/fonts.xml",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<!--\n    NOTE: this is the newer (L) version of the system font configuration,\n    supporting richer weight selection. Some apps will expect the older\n    version, so please keep system_fonts.xml and fallback_fonts.xml in sync\n    with any changes, even though framework will only read this file.\n\n    All fonts withohut names are added to the default list. Fonts are chosen\n    based on a match: full BCP-47 language tag including script, then just\n    language, and finally order (the first font containing the glyph).\n\n    Order of appearance is also the tiebreaker for weight matching. This is\n    the reason why the 900 weights of Roboto precede the 700 weights - we\n    prefer the former when an 800 weight is requested. Since bold spans\n    effectively add 300 to the weight, this ensures that 900 is the bold\n    paired with the 500 weight, ensuring adequate contrast.\n-->\n<familyset version=\"22\">\n    <!-- first font is default -->\n    <family name=\"sans-serif\">\n        <font weight=\"100\" style=\"normal\">Roboto-Thin.ttf</font>\n        <font weight=\"100\" style=\"italic\">Roboto-ThinItalic.ttf</font>\n        <font weight=\"300\" style=\"normal\">Roboto-Light.ttf</font>\n        <font weight=\"300\" style=\"italic\">Roboto-LightItalic.ttf</font>\n        <font weight=\"400\" style=\"normal\">Roboto-Regular.ttf</font>\n        <font weight=\"400\" style=\"italic\">Roboto-Italic.ttf</font>\n        <font weight=\"500\" style=\"normal\">Roboto-Medium.ttf</font>\n        <font weight=\"500\" style=\"italic\">Roboto-MediumItalic.ttf</font>\n        <font weight=\"900\" style=\"normal\">Roboto-Black.ttf</font>\n        <font weight=\"900\" style=\"italic\">Roboto-BlackItalic.ttf</font>\n        <font weight=\"700\" style=\"normal\">Roboto-Bold.ttf</font>\n        <font weight=\"700\" style=\"italic\">Roboto-BoldItalic.ttf</font>\n    </family>\n\n    <!-- Note that aliases must come after the fonts they reference. -->\n    <alias name=\"sans-serif-thin\" to=\"sans-serif\" weight=\"100\" />\n    <alias name=\"sans-serif-light\" to=\"sans-serif\" weight=\"300\" />\n    <alias name=\"sans-serif-medium\" to=\"sans-serif\" weight=\"500\" />\n    <alias name=\"sans-serif-black\" to=\"sans-serif\" weight=\"900\" />\n    <alias name=\"arial\" to=\"sans-serif\" />\n    <alias name=\"helvetica\" to=\"sans-serif\" />\n    <alias name=\"tahoma\" to=\"sans-serif\" />\n    <alias name=\"verdana\" to=\"sans-serif\" />\n\n    <family name=\"sans-serif-condensed\">\n        <font weight=\"300\" style=\"normal\">RobotoCondensed-Light.ttf</font>\n        <font weight=\"300\" style=\"italic\">RobotoCondensed-LightItalic.ttf</font>\n        <font weight=\"400\" style=\"normal\">RobotoCondensed-Regular.ttf</font>\n        <font weight=\"400\" style=\"italic\">RobotoCondensed-Italic.ttf</font>\n        <font weight=\"700\" style=\"normal\">RobotoCondensed-Bold.ttf</font>\n        <font weight=\"700\" style=\"italic\">RobotoCondensed-BoldItalic.ttf</font>\n    </family>\n    <alias name=\"sans-serif-condensed-light\" to=\"sans-serif-condensed\" weight=\"300\" />\n\n    <family name=\"serif\">\n        <font weight=\"400\" style=\"normal\">NotoSerif-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSerif-Bold.ttf</font>\n        <font weight=\"400\" style=\"italic\">NotoSerif-Italic.ttf</font>\n        <font weight=\"700\" style=\"italic\">NotoSerif-BoldItalic.ttf</font>\n    </family>\n    <alias name=\"times\" to=\"serif\" />\n    <alias name=\"times new roman\" to=\"serif\" />\n    <alias name=\"palatino\" to=\"serif\" />\n    <alias name=\"georgia\" to=\"serif\" />\n    <alias name=\"baskerville\" to=\"serif\" />\n    <alias name=\"goudy\" to=\"serif\" />\n    <alias name=\"fantasy\" to=\"serif\" />\n    <alias name=\"ITC Stone Serif\" to=\"serif\" />\n\n    <family name=\"monospace\">\n        <font weight=\"400\" style=\"normal\">DroidSansMono.ttf</font>\n    </family>\n    <alias name=\"sans-serif-monospace\" to=\"monospace\" />\n    <alias name=\"monaco\" to=\"monospace\" />\n\n    <family name=\"serif-monospace\">\n        <font weight=\"400\" style=\"normal\">CutiveMono.ttf</font>\n    </family>\n    <alias name=\"courier\" to=\"serif-monospace\" />\n    <alias name=\"courier new\" to=\"serif-monospace\" />\n\n    <family name=\"casual\">\n        <font weight=\"400\" style=\"normal\">ComingSoon.ttf</font>\n    </family>\n\n    <family name=\"cursive\">\n        <font weight=\"400\" style=\"normal\">DancingScript-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">DancingScript-Bold.ttf</font>\n    </family>\n\n    <family name=\"sans-serif-smallcaps\">\n        <font weight=\"400\" style=\"normal\">CarroisGothicSC-Regular.ttf</font>\n    </family>\n\n    <!-- fallback fonts -->\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoNaskhArabic-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoNaskhArabic-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoNaskhArabicUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoNaskhArabicUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansEthiopic-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansEthiopic-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansHebrew-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansHebrew-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansThai-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansThai-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansThaiUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansThaiUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansArmenian-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansArmenian-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansGeorgian-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGeorgian-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansDevanagari-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansDevanagari-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansDevanagariUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansDevanagariUI-Bold.ttf</font>\n    </family>\n    <!-- Gujarati should come after Devanagari -->\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansGujarati-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGujarati-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansGujaratiUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGujaratiUI-Bold.ttf</font>\n    </family>\n    <!-- Gurmukhi should come after Devanagari -->\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansGurmukhi-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGurmukhi-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansGurmukhiUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansGurmukhiUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansTamil-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTamil-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansTamilUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTamilUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansMalayalam-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMalayalam-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansMalayalamUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMalayalamUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansBengali-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansBengali-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansBengaliUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansBengaliUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansTelugu-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTelugu-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansTeluguUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTeluguUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansKannada-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKannada-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansKannadaUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKannadaUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansOriya-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansOriya-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansOriyaUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansOriyaUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSinhala-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansSinhala-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansKhmer-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKhmer-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansKhmerUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKhmerUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansLao-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansLao-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansLaoUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansLaoUI-Bold.ttf</font>\n    </family>\n    <family variant=\"elegant\">\n        <font weight=\"400\" style=\"normal\">NotoSansMyanmar-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMyanmar-Bold.ttf</font>\n    </family>\n    <family variant=\"compact\">\n        <font weight=\"400\" style=\"normal\">NotoSansMyanmarUI-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansMyanmarUI-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansThaana-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansThaana-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCham-Regular.ttf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansCham-Bold.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBalinese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBamum-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBatak-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBuginese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansBuhid-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCanadianAboriginal-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCherokee-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansCoptic-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansGlagolitic-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansHanunoo-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansJavanese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansKayahLi-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansLepcha-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansLimbu-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansLisu-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansMandaic-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansMeeteiMayek-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansNewTaiLue-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansNKo-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansOlChiki-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansRejang-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSaurashtra-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSundanese-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSylotiNagri-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSyriacEstrangela-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTagbanwa-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTaiTham-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTaiViet-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTibetan-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTifinagh-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansVai-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansYi-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansSymbols-Regular-Subsetted.ttf</font>\n    </family>\n    <family lang=\"ja\">\n        <font weight=\"400\" style=\"normal\">NotoSansJP-Regular.otf</font>\n    </family>\n    <family lang=\"ko\">\n        <font weight=\"400\" style=\"normal\">NotoSansKR-Regular.otf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NanumGothic.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoColorEmoji.ttf</font>\n    </family>\n    <family lang=\"zh-Hans\">\n        <font weight=\"300\" style=\"normal\">NotoSansSC-Light.otf</font>\n        <font weight=\"400\" style=\"normal\">NotoSansSC-Regular.otf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansSC-Bold.otf</font>\n    </family>\n    <family lang=\"zh-Hant\">\n        <font weight=\"300\" style=\"normal\">NotoSansTC-Light.otf</font>\n        <font weight=\"400\" style=\"normal\">NotoSansTC-Regular.otf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansTC-Bold.otf</font>\n    </family>\n    <family lang=\"ja\">\n        <font weight=\"300\" style=\"normal\">NotoSansJP-Light.otf</font>\n        <font weight=\"400\" style=\"normal\">NotoSansJP-Regular.otf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansJP-Bold.otf</font>\n    </family>\n    <family lang=\"ko\">\n        <font weight=\"300\" style=\"normal\">NotoSansKR-Light.otf</font>\n        <font weight=\"400\" style=\"normal\">NotoSansKR-Regular.otf</font>\n        <font weight=\"700\" style=\"normal\">NotoSansKR-Bold.otf</font>\n    </family>\n    <!--\n        Tai Le and Mongolian are intentionally kept last, to make sure they don't override\n        the East Asian punctuation for Chinese.\n    -->\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansTaiLe-Regular.ttf</font>\n    </family>\n    <family>\n        <font weight=\"400\" style=\"normal\">NotoSansMongolian-Regular.ttf</font>\n    </family>\n</familyset>\n"
  },
  {
    "path": "selfdrive/dragonpilot/gpx_uploader.py",
    "content": "#!/usr/bin/env python3\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\nimport os\nimport time\nfrom common.params import Params\n\n# for uploader\nfrom selfdrive.loggerd.xattr_cache import getxattr, setxattr\nimport glob\nimport requests\n\n# customisable values\nGPX_LOG_PATH = '/data/media/0/gpx_logs/'\nLOG_HERTZ = 1/10 # 0.1 Hz = 10 sec, higher for higher accuracy, 10hz seems fine\n\n# uploader\nUPLOAD_ATTR_NAME = 'user.upload'\nUPLOAD_ATTR_VALUE = b'1'\nLOG_PATH = '/data/media/0/gpx_logs/'\n\n# osm api\nAPI_HEADER = {'Authorization': 'Bearer 2pvUyXfk9vizuh7PwQFSEYBtFWcM-Pu7vxApUjSA0fc'}\nVERSION_URL = 'https://api.openstreetmap.org/api/versions'\nUPLOAD_URL = 'https://api.openstreetmap.org/api/0.6/gpx/create'\n\n_DEBUG = False\n\ndef _debug(msg):\n  if not _DEBUG:\n    return\n  print(msg, flush=True)\n\nclass GpxUploader():\n  def __init__(self):\n    self._delete_after_upload = not Params().get_bool('dp_gpxd')\n    self._car_model = Params().get(\"dp_last_candidate\", encoding='utf8')\n    _debug(\"GpxUploader init - _delete_after_upload = %s\" % self._delete_after_upload)\n    _debug(\"GpxUploader init - _car_model = %s\" % self._car_model)\n\n  def _is_online(self):\n    try:\n      r = requests.get(VERSION_URL, headers=API_HEADER)\n      _debug(\"is_online? status_code = %s\" % r.status_code)\n      return r.status_code >= 200\n    except:\n      return False\n\n  def _get_is_uploaded(self, filename):\n    _debug(\"%s is uploaded: %s\" % (filename, getxattr(filename, UPLOAD_ATTR_NAME) is not None))\n    return getxattr(filename, UPLOAD_ATTR_NAME) is not None\n\n  def _set_is_uploaded(self, filename):\n    _debug(\"%s set to uploaded\" % filename)\n    setxattr(filename, UPLOAD_ATTR_NAME, UPLOAD_ATTR_VALUE)\n\n  def _get_files(self):\n    return sorted( filter( os.path.isfile, glob.glob(LOG_PATH + '*') ) )\n\n  def _get_files_to_be_uploaded(self):\n    files = self._get_files()\n    files_to_be_uploaded = []\n    for file in files:\n      if not self._get_is_uploaded(file):\n        files_to_be_uploaded.append(file)\n    return files_to_be_uploaded\n\n  def _do_upload(self, filename):\n    fn = os.path.basename(filename)\n    data = {\n      'description': \"Routes from dragonpilot (%s).\" % self._car_model,\n      'visibility': 'identifiable'\n    }\n    files = {\n      \"file\": (fn, open(filename, 'rb'))\n    }\n    try:\n      r = requests.post(UPLOAD_URL, files=files, data=data, headers=API_HEADER)\n      _debug(\"do_upload - %s - %s\" % (filename, r.status_code))\n      return r.status_code == 200\n    except:\n      return False\n\n  def run(self):\n    while True:\n      files = self._get_files_to_be_uploaded()\n      if len(files) == 0 or not self._is_online():\n        _debug(\"run - not online or no files\")\n      else:\n        for file in files:\n          if self._do_upload(file):\n            if self._delete_after_upload:\n              _debug(\"run - _delete_after_upload\")\n              os.remove(file)\n            else:\n              _debug(\"run - set_is_uploaded\")\n              self._set_is_uploaded(file)\n      # sleep for 300 secs if offroad\n      # otherwise sleep 60 secs\n      time.sleep(300 if Params().get_bool(\"IsOffroad\") else 60)\n\ndef gpx_uploader_thread():\n  gpx_uploader = GpxUploader()\n  gpx_uploader.run()\n\ndef main():\n  gpx_uploader_thread()\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/dragonpilot/gpxd.py",
    "content": "#!/usr/bin/env python3\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\nimport cereal.messaging as messaging\nimport os\nimport datetime\nimport signal\nimport threading\nfrom common.realtime import Ratekeeper\n\n# customisable values\nGPX_LOG_PATH = '/data/media/0/gpx_logs/'\nLOG_HERTZ = 10 # 10 hz = 0.1 sec, higher for higher accuracy, 10hz seems fine\nLOG_LENGTH = 10 # mins, higher means it keeps more data in the memory, will take more time to write into a file too.\nLOST_SIGNAL_COUNT_LENGTH = 30 # secs, output log file if we lost signal for this long\n\n# do not change\nLOST_SIGNAL_COUNT_MAX = LOST_SIGNAL_COUNT_LENGTH * LOG_HERTZ # secs,\nLOGS_PER_FILE = LOG_LENGTH * 60 * LOG_HERTZ # e.g. 10 * 60 * 10 = 6000 points per file\n\nclass WaitTimeHelper:\n  ready_event = threading.Event()\n  shutdown = False\n\n  def __init__(self):\n    signal.signal(signal.SIGTERM, self.graceful_shutdown)\n    signal.signal(signal.SIGINT, self.graceful_shutdown)\n    signal.signal(signal.SIGHUP, self.graceful_shutdown)\n\n  def graceful_shutdown(self, signum, frame):\n    self.shutdown = True\n    self.ready_event.set()\n\nclass GpxD():\n  def __init__(self):\n    self.log_count = 0\n    self.logs = list()\n    self.lost_signal_count = 0\n    self.wait_helper = WaitTimeHelper()\n    self.started_time = datetime.datetime.utcnow().isoformat()\n    self.v_ego_prev = 0.\n    self.pause = False\n\n  def log(self, sm):\n    gps = sm['gpsLocationExternal']\n    v_ego = sm['carState'].vEgo\n\n    if abs(v_ego) > 0.:\n      self.pause = False\n\n    # do not log when no fix or accuracy is too low, add lost_signal_count\n    if gps.flags % 2 == 0 or gps.accuracy > 5.:\n      if self.log_count > 0:\n        self.lost_signal_count += 1\n    elif self.pause:\n      pass\n    else:\n      self.logs.append([datetime.datetime.utcfromtimestamp(gps.timestamp*0.001).isoformat(), str(gps.latitude), str(gps.longitude), str(gps.altitude)])\n      self.log_count += 1\n      self.lost_signal_count = 0\n\n    if v_ego == 0. and abs(self.v_ego_prev) > 0.:\n      self.pause = True\n\n    self.v_ego_prev = v_ego\n\n  def write_log(self, force = False):\n    if self.log_count == 0:\n      return\n\n    if force or (self.log_count >= LOGS_PER_FILE or self.lost_signal_count >= LOST_SIGNAL_COUNT_MAX):\n      self._write_gpx()\n      self.lost_signal_count = 0\n      self.log_count = 0\n      self.logs.clear()\n      self.started_time = datetime.datetime.utcnow().isoformat()\n\n  def _write_gpx(self):\n    if len(self.logs) > 1:\n      if not os.path.exists(GPX_LOG_PATH):\n        os.makedirs(GPX_LOG_PATH)\n      filename = self.started_time.replace(':','-')\n      str = ''\n      str += \"<?xml version=\\\"1.0\\\" encoding=\\\"utf-8\\\" standalone=\\\"yes\\\"?>\\n\"\n      str += \"<gpx version=\\\"1.1\\\" creator=\\\"dragonpilot https://github.com/dragonpilot-community/dragonpilot\\\" xmlns=\\\"http://www.topografix.com/GPX/1/1\\\" xmlns:xsi=\\\"http://www.w3.org/2001/XMLSchema-instance\\\" xsi:schemaLocation=\\\"http://www.topografix.com/GPX/1/1 http://www.topografix.com/GPX/1/1/gpx.xsd\\\">\\n\"\n      str += \"<trk>\\n\"\n      str += \"  <name>\" + self.started_time + \"</name>\"\n      str += \"  <trkseg>\\n\"\n      for trkpt in self.logs:\n        str += self._trkpt_template(trkpt[1], trkpt[2], trkpt[3], trkpt[0])\n      str += \"  </trkseg>\\n\"\n      str += \"</trk>\\n\"\n      str += \"</gpx>\\n\"\n      try:\n        f = open('%s%sZ.gpx' % (GPX_LOG_PATH, filename), 'w')\n        f.write(str)\n        f.close()\n      except:\n        pass\n\n  def _trkpt_template(self, lat, lon, ele, time):\n    str = \"\"\n    str += \"    <trkpt lat=\\\"\" + lat + \"\\\" lon=\\\"\" + lon + \"\\\">\\n\"\n    str += \"      <ele>\" + ele + \"</ele>\\n\"\n    str += \"      <time>\" + time + \"</time>\\n\"\n    str += \"    </trkpt>\\n\"\n    return str\n\ndef gpxd_thread(sm=None, pm=None):\n  if sm is None:\n    sm = messaging.SubMaster(['gpsLocationExternal', 'carState'])\n\n  wait_helper = WaitTimeHelper()\n  gpxd = GpxD()\n  rk = Ratekeeper(LOG_HERTZ, print_delay_threshold=None)\n\n  while True:\n    sm.update(0)\n    gpxd.log(sm)\n    gpxd.write_log()\n    if wait_helper.shutdown:\n      gpxd.write_log(True)\n      break\n    rk.keep_time()\n\ndef main(sm=None, pm=None):\n  gpxd_thread(sm, pm)\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/dragonpilot/otisserv.py",
    "content": "#!/usr/bin/env python3.8\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\nfrom http.server import BaseHTTPRequestHandler, HTTPServer\nfrom cgi import parse_header, parse_multipart\nfrom urllib.parse import parse_qs, unquote\nimport json\nimport requests\nfrom common.basedir import BASEDIR\nfrom common.params import Params\nparams = Params()\n\nhostName = \"\"\nserverPort = 8082\n\nclass OtisServ(BaseHTTPRequestHandler):\n  def do_GET(self):\n    use_gmap = params.get_bool('dp_mapbox_gmap_enable')\n    if self.path == '/logo.png':\n      self.get_logo()\n      return\n    if self.path == '/?reset=1':\n      params.put(\"NavDestination\", \"\")\n    if use_gmap:\n      if self.path == '/style.css':\n        self.send_response(200)\n        self.send_header(\"Content-type\", \"text/css\")\n        self.end_headers()\n        self.get_gmap_css()\n        return\n      elif self.path == '/index.js':\n        self.send_response(200)\n        self.send_header(\"Content-type\", \"text/javascript\")\n        self.end_headers()\n        self.get_gmap_js()\n        return\n      else:\n        self.send_response(200)\n        self.send_header(\"Content-type\", \"text/html\")\n        self.end_headers()\n        if self.get_gmap_key() is None:\n          self.display_page_gmap_key()\n          return\n        if self.get_app_token() is None:\n          self.display_page_app_token()\n          return\n        self.display_page_gmap()\n    else:\n      self.send_response(200)\n      self.send_header(\"Content-type\", \"text/html\")\n      self.end_headers()\n      if self.get_public_token() is None:\n        self.display_page_public_token()\n        return\n      if self.get_app_token() is None:\n        self.display_page_app_token()\n        return\n      self.display_page_addr_input()\n\n  def do_POST(self):\n    use_gmap = params.get_bool('dp_mapbox_gmap_enable')\n    postvars = self.parse_POST()\n    self.send_response(200)\n    self.send_header(\"Content-type\", \"text/html\")\n    self.end_headers()\n\n    if use_gmap:\n      # gmap token\n      if self.get_gmap_key() is None:\n        if postvars is None or \"gmap_key_val\" not in postvars or postvars.get(\"gmap_key_val\")[0] == \"\":\n          self.display_page_gmap_key()\n          return\n        params.put('dp_mapbox_gmap_key', postvars.get(\"gmap_key_val\")[0])\n\n    else:\n      # mapbox public key\n      if self.get_public_token() is None:\n        if postvars is None or \"pk_token_val\" not in postvars or postvars.get(\"pk_token_val\")[0] == \"\":\n          self.display_page_public_token()\n          return\n        token = postvars.get(\"pk_token_val\")[0]\n        if \"pk.\" not in token:\n          self.display_page_public_token(\"Your token was incorrect!\")\n          return\n        params.put('dp_mapbox_token_pk', token)\n\n    # app key\n    if self.get_app_token() is None:\n      if postvars is None or \"sk_token_val\" not in postvars or postvars.get(\"sk_token_val\")[0] == \"\":\n        self.display_page_app_token()\n        return\n      token = postvars.get(\"sk_token_val\")[0]\n      if \"sk.\" not in token:\n        self.display_page_app_token(\"Your token was incorrect!\")\n        return\n      params.put('dp_mapbox_token_sk', token)\n\n    # nav confirmed\n    if postvars is not None:\n      if \"lat\" in postvars and postvars.get(\"lat\")[0] != \"\" and \"lon\" in postvars and postvars.get(\"lon\")[0] != \"\":\n        params.put('NavDestination', \"{\\\"latitude\\\": %f, \\\"longitude\\\": %f}\" % (float(postvars.get(\"lat\")[0]), float(postvars.get(\"lon\")[0])))\n\n      # search\n      if not use_gmap and \"addr_val\" in postvars:\n        addr = postvars.get(\"addr_val\")[0]\n        if addr != \"\":\n          real_addr, lat, lon = self.query_addr(addr)\n          if real_addr is not None:\n            self.display_page_nav_confirmation(real_addr, lon, lat)\n            return\n          else:\n            self.display_page_addr_input(\"Place Not Found\")\n            return\n\n    if not use_gmap:\n      # display addr input\n      self.display_page_addr_input()\n    else:\n      self.display_page_gmap()\n\n  def get_logo(self):\n    self.send_response(200)\n    self.send_header('Content-type','image/png')\n    self.end_headers()\n    f = open(\"%s/selfdrive/assets/img_spinner_comma.png\" % BASEDIR, \"rb\")\n    self.wfile.write(f.read())\n    f.close()\n\n  def get_gmap_css(self):\n    self.wfile.write(bytes(self.get_parsed_template(\"gmap_style.css\"), \"utf-8\"))\n\n  def get_gmap_js(self):\n    lon, lat = self.get_last_lon_lat()\n    self.wfile.write(bytes(self.get_parsed_template(\"gmap_index.js\", {\"{{lat}}\": lat, \"{{lon}}\": lon}), \"utf-8\"))\n\n  def display_page_gmap(self):\n    self.wfile.write(bytes(self.get_parsed_template(\"gmap_index.html\", {\"{{gmap_key}}\": self.get_gmap_key()}), \"utf-8\"))\n\n  def get_gmap_key(self):\n    token = params.get(\"dp_mapbox_gmap_key\", encoding='utf8')\n    if token is not None and token != \"\":\n      return token.rstrip('\\x00')\n    return None\n\n  def get_public_token(self):\n    token = params.get(\"dp_mapbox_token_pk\", encoding='utf8')\n    if token is not None and token != \"\":\n      return token.rstrip('\\x00')\n    return None\n\n  def get_app_token(self):\n    token = params.get(\"dp_mapbox_token_sk\", encoding='utf8')\n    if token is not None and token != \"\":\n      return token.rstrip('\\x00')\n    return None\n\n  def get_last_lon_lat(self):\n    last_pos = Params().get(\"LastGPSPosition\")\n    if last_pos is not None and last_pos != \"\":\n      l = json.loads(last_pos)\n      return l[\"longitude\"], l[\"latitude\"]\n    return \"\", \"\"\n\n  def display_page_gmap_key(self):\n    self.wfile.write(bytes(self.get_parsed_template(\"body\", {\"{{content}}\": self.get_parsed_template(\"gmap_key_input\")}), \"utf-8\"))\n\n  def display_page_public_token(self, msg = \"\"):\n    self.wfile.write(bytes(self.get_parsed_template(\"body\", {\"{{content}}\": self.get_parsed_template(\"public_token_input\", {\"{{msg}}\": msg})}), \"utf-8\"))\n\n  def display_page_app_token(self, msg = \"\"):\n    self.wfile.write(bytes(self.get_parsed_template(\"body\", {\"{{content}}\": self.get_parsed_template(\"app_token_input\", {\"{{msg}}\": msg})}), \"utf-8\"))\n\n  def display_page_addr_input(self, msg = \"\"):\n    self.wfile.write(bytes(self.get_parsed_template(\"body\", {\"{{content}}\": self.get_parsed_template(\"addr_input\", {\"{{msg}}\": msg})}), \"utf-8\"))\n\n  def display_page_nav_confirmation(self, addr, lon, lat):\n    content = self.get_parsed_template(\"addr_input\", {\"{{msg}}\": \"\"}) + self.get_parsed_template(\"nav_confirmation\", {\"{{token}}\": self.get_public_token(), \"{{lon}}\": lon, \"{{lat}}\": lat, \"{{addr}}\": addr})\n    self.wfile.write(bytes(self.get_parsed_template(\"body\", {\"{{content}}\": content }), \"utf-8\"))\n\n  def get_parsed_template(self, name, replace = {}):\n    f = open('%s/selfdrive/dragonpilot/tpl/%s.tpl' % (BASEDIR, name), mode='r', encoding='utf-8')\n    content = f.read()\n    for key in replace:\n      content = content.replace(key, str(replace[key]))\n    f.close()\n    return content\n\n  def query_addr(self, addr):\n    if addr == \"\":\n      return None, None, None\n    query = \"https://api.mapbox.com/geocoding/v5/mapbox.places/\" + unquote(addr) + \".json?access_token=\" + self.get_public_token() + \"&limit=1\"\n    # focus on place around last gps position\n    last_pos = Params().get(\"LastGPSPosition\")\n    if last_pos is not None and last_pos != \"\":\n      l = json.loads(last_pos)\n      query += \"&proximity=%s,%s\" % (l[\"longitude\"], l[\"latitude\"])\n\n    r = requests.get(query)\n    if r.status_code != 200:\n      return None, None, None\n\n    j = json.loads(r.text)\n    if not j[\"features\"]:\n      return None, None, None\n\n    feature = j[\"features\"][0]\n    return feature[\"place_name\"], feature[\"center\"][1], feature[\"center\"][0]\n\n  def parse_POST(self):\n    ctype, pdict = parse_header(self.headers['content-type'])\n    if ctype == 'application/x-www-form-urlencoded':\n      length = int(self.headers['content-length'])\n      postvars = parse_qs(\n        self.rfile.read(length).decode('utf-8'),\n        keep_blank_values=1)\n    else:\n      postvars = {}\n    return postvars\n\ndef main():\n  webServer = HTTPServer((hostName, serverPort), OtisServ)\n\n  try:\n    webServer.serve_forever()\n  except KeyboardInterrupt:\n    pass\n\n  webServer.server_close()\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/dragonpilot/systemd.py",
    "content": "#!/usr/bin/env python3\n# The MIT License\n#\n# Copyright (c) 2019-, Rick Lan, dragonpilot community, and a number of other of contributors.\n#\n# Permission is hereby granted, free of charge, to any person obtaining a copy\n# of this software and associated documentation files (the \"Software\"), to deal\n# in the Software without restriction, including without limitation the rights\n# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n# copies of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included in\n# all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n# THE SOFTWARE.\n\n'''\nThis is a service that broadcast dp config values to openpilot's messaging queues\n'''\nimport cereal.messaging as messaging\n\nfrom common.dp_conf import confs, get_struct_name, to_struct_val\nfrom common.params import Params, put_nonblocking\nimport os\nfrom selfdrive.hardware import HARDWARE\nparams = Params()\nfrom common.dp_common import param_get, get_last_modified\nfrom common.dp_time import LAST_MODIFIED_SYSTEMD\nfrom selfdrive.dragonpilot.dashcamd import Dashcamd\nfrom selfdrive.dragonpilot.appd import Appd\nfrom selfdrive.hardware import EON\nimport socket\nfrom common.realtime import Ratekeeper\nimport threading\nfrom selfdrive.dragonpilot.gpx_uploader import gpx_uploader_thread\n\nPARAM_PATH = params.get_params_path() + '/d/'\n\nHERTZ = 1\n\nlast_modified_confs = {}\n\ndef confd_thread():\n  sm = messaging.SubMaster(['deviceState'])\n  pm = messaging.PubMaster(['dragonConf'])\n\n  last_dp_msg = None\n  frame = 0\n  update_params = False\n  modified = None\n  last_modified = None\n  last_modified_check = None\n  started = False\n  free_space = 1\n  battery_percent = 0\n  overheat = False\n  last_started = False\n  dashcamd = Dashcamd()\n  appd = Appd()\n  is_eon = EON\n  rk = Ratekeeper(HERTZ, print_delay_threshold=None)  # Keeps rate at 2 hz\n  uploader_thread = None\n\n  while True:\n    if uploader_thread is None:\n      uploader_thread = threading.Thread(target=gpx_uploader_thread)\n      uploader_thread.start()\n\n    msg = messaging.new_message('dragonConf')\n    if last_dp_msg is not None:\n      msg.dragonConf = last_dp_msg\n\n    '''\n    ===================================================\n    load thermald data every 3 seconds\n    ===================================================\n    '''\n    if frame % (HERTZ * 3) == 0:\n      started, free_space, battery_percent, overheat = pull_thermald(frame, sm, started, free_space, battery_percent, overheat)\n    setattr(msg.dragonConf, get_struct_name('dp_thermal_started'), started)\n    setattr(msg.dragonConf, get_struct_name('dp_thermal_overheat'), overheat)\n    '''\n    ===================================================\n    hotspot on boot\n    we do it after 30 secs just in case\n    ===================================================\n    '''\n    if is_eon and frame == (HERTZ * 30) and param_get(\"dp_hotspot_on_boot\", \"bool\", False):\n      os.system(\"service call wifi 37 i32 0 i32 1 &\")\n    '''\n    ===================================================\n    check dp_last_modified every second\n    ===================================================\n    '''\n    if not update_params:\n      last_modified_check, modified = get_last_modified(LAST_MODIFIED_SYSTEMD, last_modified_check, modified)\n      if last_modified != modified:\n        update_params = True\n        last_modified = modified\n    '''\n    ===================================================\n    conditionally set update_params to true \n    ===================================================\n    '''\n    # force updating param when `started` changed\n    if last_started != started:\n      update_params = True\n\n    if frame == 0:\n      update_params = True\n    '''\n    ===================================================\n    push param vals to message\n    ===================================================\n    '''\n    if update_params:\n      msg = update_conf_all(confs, msg, frame == 0)\n      update_params = False\n    '''\n    ===================================================\n    push once\n    ===================================================\n    '''\n    if frame == 0:\n      setattr(msg.dragonConf, get_struct_name('dp_locale'), params.get(\"dp_locale\"))\n      # mirror EndToEndToggle to dp_lane_less_model_ctrl first time, after all\n      put_nonblocking('dp_lane_less_mode_ctrl', params.get('EndToEndToggle'))\n    '''\n    ===================================================\n    push ip addr every 10 secs\n    ===================================================\n    '''\n    if frame % (HERTZ * 10) == 0:\n      msg = update_ip(msg)\n    '''\n    ===================================================\n    update msg based on some custom logic\n    ===================================================\n    '''\n    msg = update_custom_logic(msg)\n    '''\n    ===================================================\n    battery ctrl every 30 secs\n    PowerMonitor in thermald turns back on every mins\n    so lets turn it off more frequent\n    ===================================================\n    '''\n    # if frame % (HERTZ * 30) == 0:\n    #   last_charging_ctrl = process_charging_ctrl(msg, last_charging_ctrl, battery_percent)\n    '''\n    ===================================================\n    dashcam\n    ===================================================\n    '''\n    if msg.dragonConf.dpDashcamd and frame % HERTZ == 0:\n      dashcamd.run(started, free_space)\n    '''\n    ===================================================\n    appd\n    ===================================================\n    '''\n    if msg.dragonConf.dpAppd:\n      appd.update(started)\n    '''\n    ===================================================\n    finalise\n    ===================================================\n    '''\n    last_dp_msg = msg.dragonConf\n    last_started = started\n    pm.send('dragonConf', msg)\n    frame += 1\n    rk.keep_time()\n\ndef update_conf(msg, conf, first_run = False):\n  conf_type = conf.get('conf_type')\n\n  # skip checking since modified date time hasn't been changed.\n  if (last_modified_confs.get(conf['name'])) is not None and last_modified_confs.get(conf['name']) == os.stat(PARAM_PATH + conf['name']).st_mtime:\n    return msg\n\n  if 'param' in conf_type and 'struct' in conf_type:\n    update_this_conf = True\n\n    if not first_run:\n      update_once = conf.get('update_once')\n      if update_once is not None and update_once is True:\n        return msg\n      if update_this_conf:\n        update_this_conf = check_dependencies(msg, conf)\n\n    if update_this_conf:\n      msg = set_message(msg, conf)\n      if os.path.isfile(PARAM_PATH + conf['name']):\n        last_modified_confs[conf['name']] = os.stat(PARAM_PATH + conf['name']).st_mtime\n  return msg\n\ndef update_conf_all(confs, msg, first_run = False):\n  for conf in confs:\n    msg = update_conf(msg, conf, first_run)\n  return msg\n\ndef process_charging_ctrl(msg, last_charging_ctrl, battery_percent):\n  charging_ctrl = msg.dragonConf.dpChargingCtrl\n  if last_charging_ctrl != charging_ctrl:\n    HARDWARE.set_battery_charging(True)\n  if charging_ctrl:\n    if battery_percent >= msg.dragonConf.dpDischargingAt and HARDWARE.get_battery_charging():\n      HARDWARE.set_battery_charging(False)\n    elif battery_percent <= msg.dragonConf.dpChargingAt and not HARDWARE.get_battery_charging():\n      HARDWARE.set_battery_charging(True)\n  return charging_ctrl\n\n\ndef pull_thermald(frame, sm, started, free_space, battery_percent, overheat):\n  sm.update(0)\n  if sm.updated['deviceState']:\n    started = sm['deviceState'].started\n    free_space = sm['deviceState'].freeSpacePercent\n    battery_percent = sm['deviceState'].batteryPercent\n    overheat = sm['deviceState'].thermalStatus >= 2\n  return started, free_space, battery_percent, overheat\n\ndef update_custom_logic(msg):\n  if msg.dragonConf.dpAtl:\n    msg.dragonConf.dpAllowGas = True\n    msg.dragonConf.dpGearCheck = False\n    if not msg.dragonConf.dpAtlOpLong:\n      msg.dragonConf.dpFollowingProfileCtrl = False\n      msg.dragonConf.dpAccelProfileCtrl = False\n  if msg.dragonConf.dpLcMinMph > msg.dragonConf.dpLcAutoMinMph:\n    put_nonblocking('dp_lc_auto_min_mph', str(msg.dragonConf.dpLcMinMph))\n    msg.dragonConf.dpLcAutoMinMph = msg.dragonConf.dpLcMinMph\n  # if msg.dragonConf.dpSrCustom <= 4.99 and msg.dragonConf.dpSrStock > 0:\n  #   put_nonblocking('dp_sr_custom', str(msg.dragonConf.dpSrStock))\n  #   msg.dragonConf.dpSrCustom = msg.dragonConf.dpSrStock\n  # if msg.dragonConf.dpAppWaze or msg.dragonConf.dpAppHr:\n  #   msg.dragonConf.dpDrivingUi = False\n  # if not msg.dragonConf.dpDriverMonitor:\n  #   msg.dragonConf.dpUiFace = False\n  return msg\n\n\ndef update_ip(msg):\n  val = 'N/A'\n  s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)\n  try:\n    # doesn't even have to be reachable\n    s.connect(('10.255.255.255', 1))\n    IP = s.getsockname()[0]\n  except:\n    IP = 'N/A'\n  finally:\n    s.close()\n  setattr(msg.dragonConf, get_struct_name('dp_ip_addr'), IP)\n  return msg\n\n\ndef set_message(msg, conf):\n  val = params.get(conf['name'], encoding='utf8')\n  if val is not None:\n    val = val.rstrip('\\x00')\n  else:\n    val = conf.get('default')\n    params.put(conf['name'], str(val))\n  struct_val = to_struct_val(conf['name'], val)\n  orig_val = struct_val\n  if struct_val is not None:\n    if conf.get('min') is not None:\n      struct_val = max(struct_val, conf.get('min'))\n    if conf.get('max') is not None:\n      struct_val = min(struct_val, conf.get('max'))\n  if orig_val != struct_val:\n    params.put(conf['name'], str(struct_val))\n  setattr(msg.dragonConf, get_struct_name(conf['name']), struct_val)\n  return msg\n\ndef check_dependencies(msg, conf):\n  passed = True\n  # if has dependency and the depend param val is not in depend_vals, we dont update that conf val\n  # this should reduce chance of reading unnecessary params\n  dependencies = conf.get('depends')\n  if dependencies is not None:\n    for dependency in dependencies:\n      if getattr(msg.dragonConf, get_struct_name(dependency['name'])) not in dependency['vals']:\n        passed = False\n        break\n  return passed\n\ndef main():\n  confd_thread()\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/addr_input.tpl",
    "content": "<form style=\"width: 80%;\" name=\"searchForm\" method=\"post\">\n<div style=\"padding: 5px;\"><input style=\"width: 100%; height: 20px;\" type=\"text\" name=\"addr_val\" placeholder=\"Search Place\" /></div>\n<div style=\"padding: 5px; color: red; font-weight: bold;\" align=\"center\">{{msg}}</div>\n<div style=\"padding: 5px;\" align=\"center\"><input type=\"submit\" value=\"Search\"></div>\n</form>"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/app_token_input.tpl",
    "content": "<div style=\"padding: 5px;\">Set your mapbox <b>APP TOKEN</b></div>\n<div style=\"padding: 5px;\">(begin with <b>sk.</b>)\n<div style=\"padding: 5px; color: red; font-weight: bold;\">{{msg}}</div>\n<form name=\"setSkTokenForm\" method=\"post\">\n<div style=\"padding: 5px;\"><input type=\"text\" name=\"sk_token_val\" placeholder=\"Your Token\"><input type=\"submit\" value=\"Set\"></div>\n<div style=\"padding: 5px;\"></div>\n</form>"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/body.tpl",
    "content": "<!DOCTYPE html>\n<html>\n<head>\n  <meta charset=\"utf-8\">\n  <title>dragonpilot</title>\n  <meta name=\"viewport\" content=\"initial-scale=1,maximum-scale=1,user-scalable=no\">\n</head>\n<body style=\"margin: 0; padding: 0;\">\n  <div style=\"display: grid; place-items: center;\">\n  <div style=\"padding: 5px; font-weight: bold;\" align=\"center\"><a href=\"?reset=1\"><img style=\"width: 100px; height: 100px; background-color: black;\" src=\"logo.png\"></a></div>\n  {{content}}\n  </div>\n</body>\n</html>"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/gmap_index.html.tpl",
    "content": "<!DOCTYPE html>\n<html>\n  <head>\n    <title>dragonpilot</title>\n    <script src=\"https://polyfill.io/v3/polyfill.min.js?features=default\"></script>\n    <link rel=\"stylesheet\" type=\"text/css\" href=\"./style.css\" />\n    <script src=\"./index.js\"></script>\n    <meta name=\"viewport\" content=\"width=device-width\">\n  </head>\n  <body>\n    <div style=\"place-items: center; padding: 5px; font-weight: bold;\" align=\"center\"><a href=\"?reset=1\"><img style=\"width: 100px; height: 100px; background-color: black;\" src=\"logo.png\"></a></div>\n    <input\n      id=\"pac-input\"\n      class=\"controls\"\n      type=\"text\"\n      placeholder=\"Search Box\"\n    />\n    <div id=\"map\"></div>\n\n    <!-- Async script executes immediately and must be after any DOM elements used in callback. -->\n    <script\n      src=\"https://maps.googleapis.com/maps/api/js?key={{gmap_key}}&callback=initAutocomplete&libraries=places&v=weekly\"\n      async\n    ></script>\n  </body>\n</html>"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/gmap_index.js.tpl",
    "content": "// This example adds a search box to a map, using the Google Place Autocomplete\n// feature. People can enter geographical searches. The search box will return a\n// pick list containing a mix of places and predicted search terms.\n// This example requires the Places library. Include the libraries=places\n// parameter when you first load the API. For example:\n// <script src=\"https://maps.googleapis.com/maps/api/js?key=YOUR_API_KEY&libraries=places\">\nfunction initAutocomplete() {\n  const map = new google.maps.Map(document.getElementById(\"map\"), {\n    center: { lat: {{lat}}, lng: {{lon}} },\n    zoom: 13,\n    mapTypeId: \"roadmap\",\n    disableDefaultUI: true\n  });\n  // Create the search box and link it to the UI element.\n  const input = document.getElementById(\"pac-input\");\n  const searchBox = new google.maps.places.SearchBox(input);\n\n  map.controls[google.maps.ControlPosition.TOP_LEFT].push(input);\n  // Bias the SearchBox results towards current map's viewport.\n  map.addListener(\"bounds_changed\", () => {\n    searchBox.setBounds(map.getBounds());\n  });\n\n  let markers = [];\n\n  // Listen for the event fired when the user selects a prediction and retrieve\n  // more details for that place.\n  searchBox.addListener(\"places_changed\", () => {\n    const places = searchBox.getPlaces();\n\n    if (places.length == 0) {\n      return;\n    }\n\n    // Clear out the old markers.\n    markers.forEach((marker) => {\n      marker.setMap(null);\n    });\n    markers = [];\n\n    // For each place, get the icon, name and location.\n    const bounds = new google.maps.LatLngBounds();\n\n    places.slice(-1).forEach((place) => {\n      if (!place.geometry || !place.geometry.location) {\n        console.log(\"Returned place contains no geometry\");\n        return;\n      }\n\n      const icon = {\n        url: place.icon,\n        size: new google.maps.Size(71, 71),\n        origin: new google.maps.Point(0, 0),\n        anchor: new google.maps.Point(17, 34),\n        scaledSize: new google.maps.Size(25, 25),\n      };\n\n      // Create a marker for each place.\n      markers.push(\n        new google.maps.Marker({\n          map,\n          icon,\n          title: place.name,\n          position: place.geometry.location,\n        })\n      );\n\n      // set nav\n      var http = new XMLHttpRequest();\n      http.open(\"POST\", \"/\", true);\n      http.setRequestHeader(\"Content-type\",\"application/x-www-form-urlencoded\");\n      var params = \"lat=\" + place.geometry.location.lat() + \"&lon=\" + place.geometry.location.lng();\n      http.send(params);\n\n      if (place.geometry.viewport) {\n        // Only geocodes have viewport.\n        bounds.union(place.geometry.viewport);\n      } else {\n        bounds.extend(place.geometry.location);\n      }\n      return;\n    });\n    map.fitBounds(bounds);\n  });\n}\n"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/gmap_key_input.tpl",
    "content": "<div style=\"padding: 5px;\">Set your Google Map API Key</div>\n<form name=\"setGmapTokenForm\" method=\"post\">\n<div style=\"padding: 5px;\"><input type=\"text\" name=\"gmap_key_val\" placeholder=\"Your Key\"><input type=\"submit\" value=\"Set\"></div>\n<div style=\"padding: 5px;\"></div>\n</form>"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/gmap_style.css.tpl",
    "content": "/* Always set the map height explicitly to define the size of the div\n       * element that contains the map. */\n#map {\n  height: 100%;\n}\n\n/* Optional: Makes the sample page fill the window. */\nhtml,\nbody {\n  height: 80%;\n  margin: 0;\n  padding: 0;\n}\n\n#description {\n  font-family: Roboto;\n  font-size: 15px;\n  font-weight: 300;\n}\n\n#infowindow-content .title {\n  font-weight: bold;\n}\n\n#infowindow-content {\n  display: none;\n}\n\n#map #infowindow-content {\n  display: inline;\n}\n\n.pac-card {\n  background-color: #fff;\n  border: 0;\n  border-radius: 2px;\n  box-shadow: 0 1px 4px -1px rgba(0, 0, 0, 0.3);\n  margin: 10px;\n  padding: 0 0.5em;\n  font: 400 18px Roboto, Arial, sans-serif;\n  overflow: hidden;\n  font-family: Roboto;\n  padding: 0;\n}\n\n#pac-container {\n  padding-bottom: 12px;\n  margin-right: 12px;\n}\n\n.pac-controls {\n  display: inline-block;\n  padding: 5px 11px;\n}\n\n.pac-controls label {\n  font-family: Roboto;\n  font-size: 13px;\n  font-weight: 300;\n}\n\n#pac-input {\n  background-color: #fff;\n  font-family: Roboto;\n  font-size: 20px;\n  font-weight: 300;\n  margin-left: 12px;\n  padding: 0 11px 0 13px;\n  text-overflow: ellipsis;\n  width: 200px;\n  height: 30px;\n}\n\n#pac-input:focus {\n  border-color: #4d90fe;\n}\n\n#title {\n  color: #fff;\n  background-color: #4d90fe;\n  font-size: 25px;\n  font-weight: 500;\n  padding: 6px 12px;\n}\n\n#target {\n  width: 345px;\n}\n"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/nav_confirmation.tpl",
    "content": "<div><img src=\"https://api.mapbox.com/styles/v1/mapbox/streets-v11/static/pin-s-l+000({{lon}},{{lat}})/{{lon}},{{lat}},14/300x300?access_token={{token}}\" /></div>\n<div style=\"padding: 5px; font-size: 10px;\">{{addr}}</div>\n<form name=\"navForm\" method=\"post\">\n  <input type=\"hidden\" name=\"addr\" value=\"{{addr}}\">\n  <input type=\"hidden\" name=\"lat\" value=\"{{lat}}\">\n  <input type=\"hidden\" name=\"lon\" value=\"{{lon}}\">\n  <div style=\"padding: 5px;\"><input type=\"submit\" value=\"Start Navigation\" ></div>\n</form>"
  },
  {
    "path": "selfdrive/dragonpilot/tpl/public_token_input.tpl",
    "content": "<div style=\"padding: 5px;\">Set your mapbox <b>PUBLIC TOKEN</b></div>\n<div style=\"padding: 5px;\">(begin with <b>pk.</b>)</div>\n<div style=\"padding: 5px; color: red; font-weight: bold;\">{{msg}}</div>\n<form name=\"setPkTokenForm\" method=\"post\">\n<div style=\"padding: 5px;\"><input type=\"text\" name=\"pk_token_val\" placeholder=\"Your Token\"><input type=\"submit\" value=\"Set\"></div>\n<div style=\"padding: 5px;\"></div>\n</form>"
  },
  {
    "path": "selfdrive/hardware/__init__.py",
    "content": "import os\nfrom typing import cast\n\nfrom selfdrive.hardware.base import HardwareBase\nfrom selfdrive.hardware.eon.hardware import Android\nfrom selfdrive.hardware.tici.hardware import Tici\nfrom selfdrive.hardware.pc.hardware import Pc\nfrom selfdrive.hardware.jetson.hardware import Jetson\n\nEON = os.path.isfile('/EON')\nTICI = os.path.isfile('/TICI')\nJETSON = os.path.isfile('/JETSON')\nPC = not (EON or TICI or JETSON)\n\n\nif EON:\n  HARDWARE = cast(HardwareBase, Android())\nelif TICI:\n  HARDWARE = cast(HardwareBase, Tici())\nelif JETSON:\n  HARDWARE = cast(HardwareBase, Jetson())\nelse:\n  HARDWARE = cast(HardwareBase, Pc())\n"
  },
  {
    "path": "selfdrive/hardware/base.h",
    "content": "#pragma once\n\n#include <cstdlib>\n#include <fstream>\n\n// no-op base hw class\nclass HardwareNone {\npublic:\n  static constexpr float MAX_VOLUME = 0;\n  static constexpr float MIN_VOLUME = 0;\n\n  static std::string get_os_version() { return \"\"; }\n\n  static void reboot() {}\n  static void poweroff() {}\n  static void set_brightness(int percent) {}\n  static void set_display_power(bool on) {}\n\n  static bool get_ssh_enabled() { return false; }\n  static void set_ssh_enabled(bool enabled) {}\n\n  static bool PC() { return false; }\n  static bool EON() { return false; }\n  static bool TICI() { return false; }\n  static bool JETSON() { return false; }\n};\n"
  },
  {
    "path": "selfdrive/hardware/base.py",
    "content": "from abc import abstractmethod\nfrom collections import namedtuple\n\nThermalConfig = namedtuple('ThermalConfig', ['cpu', 'gpu', 'mem', 'bat', 'ambient'])\n\nclass HardwareBase:\n  @staticmethod\n  def get_cmdline():\n    with open('/proc/cmdline') as f:\n      cmdline = f.read()\n    return {kv[0]: kv[1] for kv in [s.split('=') for s in cmdline.split(' ')] if len(kv) == 2}\n\n  @staticmethod\n  def read_param_file(path, parser, default=0):\n    try:\n      with open(path) as f:\n        return parser(f.read())\n    except Exception:\n      return default\n\n  @abstractmethod\n  def reboot(self, reason=None):\n    pass\n\n  @abstractmethod\n  def uninstall(self):\n    pass\n\n  @abstractmethod\n  def get_os_version(self):\n    pass\n\n  @abstractmethod\n  def get_device_type(self):\n    pass\n\n  @abstractmethod\n  def get_sound_card_online(self):\n    pass\n\n  @abstractmethod\n  def get_imei(self, slot):\n    pass\n\n  @abstractmethod\n  def get_serial(self):\n    pass\n\n  @abstractmethod\n  def get_subscriber_info(self):\n    pass\n\n  @abstractmethod\n  def get_network_info(self):\n    pass\n\n  @abstractmethod\n  def get_network_type(self):\n    pass\n\n  @abstractmethod\n  def get_sim_info(self):\n    pass\n\n  @abstractmethod\n  def get_network_strength(self, network_type):\n    pass\n\n  @abstractmethod\n  def get_battery_capacity(self):\n    pass\n\n  @abstractmethod\n  def get_battery_status(self):\n    pass\n\n  @abstractmethod\n  def get_battery_current(self):\n    pass\n\n  @abstractmethod\n  def get_battery_voltage(self):\n    pass\n\n  @abstractmethod\n  def get_battery_charging(self):\n    pass\n\n  @abstractmethod\n  def set_battery_charging(self, on):\n    pass\n\n  @abstractmethod\n  def get_usb_present(self):\n    pass\n\n  @abstractmethod\n  def get_current_power_draw(self):\n    pass\n\n  @abstractmethod\n  def shutdown(self):\n    pass\n\n  @abstractmethod\n  def get_thermal_config(self):\n    pass\n\n  @abstractmethod\n  def set_screen_brightness(self, percentage):\n    pass\n\n  @abstractmethod\n  def set_power_save(self, powersave_enabled):\n    pass\n\n  @abstractmethod\n  def get_gpu_usage_percent(self):\n    pass\n\n  @abstractmethod\n  def get_modem_version(self):\n    pass\n\n  @abstractmethod\n  def initialize_hardware(self):\n    pass\n\n  @abstractmethod\n  def get_networks(self):\n    pass"
  },
  {
    "path": "selfdrive/hardware/eon/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/hardware/eon/androidd.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport time\nimport psutil\nfrom typing import Optional\n\nfrom common.realtime import set_core_affinity, set_realtime_priority\nfrom selfdrive.swaglog import cloudlog\n\n\nMAX_MODEM_CRASHES = 3\nMODEM_PATH = \"/sys/devices/soc/2080000.qcom,mss/subsys5\"\nWATCHED_PROCS = [\"zygote\", \"zygote64\", \"/system/bin/servicemanager\", \"/system/bin/surfaceflinger\"]\n\n\ndef get_modem_crash_count() -> Optional[int]:\n  try:\n    with open(os.path.join(MODEM_PATH, \"crash_count\")) as f:\n      return int(f.read())\n  except Exception:\n    cloudlog.exception(\"Error reading modem crash count\")\n  return None\n\ndef get_modem_state() -> str:\n  try:\n    with open(os.path.join(MODEM_PATH, \"state\")) as f:\n      return f.read().strip()\n  except Exception:\n    cloudlog.exception(\"Error reading modem state\")\n  return \"\"\n\ndef main():\n  set_core_affinity(1)\n  set_realtime_priority(1)\n\n  procs = {}\n  crash_count = 0\n  modem_killed = False\n  modem_state = \"ONLINE\"\n  while True:\n    # check critical android services\n    if any(p is None or not p.is_running() for p in procs.values()) or not len(procs):\n      cur = {p: None for p in WATCHED_PROCS}\n      for p in psutil.process_iter(attrs=['cmdline']):\n        cmdline = None if not len(p.info['cmdline']) else p.info['cmdline'][0]\n        if cmdline in WATCHED_PROCS:\n          cur[cmdline] = p\n\n      if len(procs):\n        for p in WATCHED_PROCS:\n          if cur[p] != procs[p]:\n            cloudlog.event(\"android service pid changed\", proc=p, cur=cur[p], prev=procs[p])\n      procs.update(cur)\n\n    # check modem state\n    state = get_modem_state()\n    if state != modem_state and not modem_killed:\n      cloudlog.event(\"modem state changed\", state=state)\n    modem_state = state\n\n    # check modem crashes\n    cnt = get_modem_crash_count()\n    if cnt is not None:\n      if cnt > crash_count:\n        cloudlog.event(\"modem crash\", count=cnt)\n      crash_count = cnt\n\n    # handle excessive modem crashes\n    if crash_count > MAX_MODEM_CRASHES and not modem_killed:\n      cloudlog.event(\"killing modem\")\n      with open(\"/sys/kernel/debug/msm_subsys/modem\", \"w\") as f:\n        f.write(\"put\")\n      modem_killed = True\n\n    time.sleep(1)\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/hardware/eon/hardware.h",
    "content": "#pragma once\n\n#include <cstdlib>\n#include <fstream>\n\n#include <gui/ISurfaceComposer.h>\n#include <gui/SurfaceComposerClient.h>\n#include <hardware/hwcomposer_defs.h>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/base.h\"\n\nclass HardwareEon : public HardwareNone {\npublic:\n  static constexpr float MAX_VOLUME = 1.0;\n  static constexpr float MIN_VOLUME = 0.5;\n\n  static bool EON() { return true; }\n  static std::string get_os_version() {\n    return \"NEOS \" + util::read_file(\"/VERSION\");\n  };\n\n  static void reboot() { std::system(\"reboot\"); };\n  static void poweroff() { std::system(\"LD_LIBRARY_PATH= svc power shutdown\"); };\n  static void set_brightness(int percent) {\n    std::ofstream brightness_control(\"/sys/class/leds/lcd-backlight/brightness\");\n    if (brightness_control.is_open()) {\n      brightness_control << (int)(percent * (255/100.)) << \"\\n\";\n      brightness_control.close();\n    }\n  };\n  static void set_display_power(bool on) {\n    auto dtoken = android::SurfaceComposerClient::getBuiltInDisplay(android::ISurfaceComposer::eDisplayIdMain);\n    android::SurfaceComposerClient::setDisplayPowerMode(dtoken, on ? HWC_POWER_MODE_NORMAL : HWC_POWER_MODE_OFF);\n  };\n\n  static bool get_ssh_enabled() {\n    return std::system(\"getprop persist.neos.ssh | grep -qF '1'\") == 0;\n  };\n  static void set_ssh_enabled(bool enabled) {\n    std::string cmd = util::string_format(\"setprop persist.neos.ssh %d\", enabled ? 1 : 0);\n    std::system(cmd.c_str());\n  };\n\n  // android only\n  inline static bool launched_activity = false;\n  static void check_activity() {\n    int ret = std::system(\"dumpsys SurfaceFlinger --list | grep -Fq 'com.android.settings'\");\n    launched_activity = ret == 0;\n  }\n\n  static void close_activities() {\n    if(launched_activity) {\n      std::system(\"pm disable com.android.settings && pm enable com.android.settings\");\n    }\n  }\n\n  static void launch_activity(std::string activity, std::string opts = \"\") {\n    if (!launched_activity) {\n      std::string cmd = \"am start -n \" + activity + \" \" + opts +\n                        \" --ez extra_prefs_show_button_bar true \\\n                         --es extra_prefs_set_next_text ''\";\n      std::system(cmd.c_str());\n    }\n    launched_activity = true;\n  }\n  static void launch_wifi() {\n    launch_activity(\"com.android.settings/.wifi.WifiPickerActivity\", \"-a android.net.wifi.PICK_WIFI_NETWORK\");\n  }\n  static void launch_tethering() {\n    launch_activity(\"com.android.settings/.TetherSettings\");\n  }\n  static void launch_locale() {\n    // am start -a android.settings.LOCALE_SETTINGS --es extra_prefs_set_next_text 'Close' --es extra_prefs_set_back_text 'Close'\n    launch_activity(\"com.android.settings/.Settings\\\\$LocalePickerActivity\");\n  }\n  static void launch_vol() {\n    // am start -a android.settings.SOUND_SETTINGS --ez extra_prefs_show_button_bar true --es extra_prefs_set_next_text 'Close' --es extra_prefs_set_back_text 'Close'\n    launch_activity(\"com.android.settings/.Settings\\\\$SoundSettingsActivity\");\n  }\n  static void launch_datetime() {\n    // am start -a android.settings.DATE_SETTINGS --ez extra_prefs_show_button_bar true --es extra_prefs_set_next_text 'Close' --es extra_prefs_set_back_text 'Close'\n    launch_activity(\"com.android.settings/.Settings\\\\$DateTimeSettingsActivity\");\n  }\n};\n"
  },
  {
    "path": "selfdrive/hardware/eon/hardware.py",
    "content": "import binascii\nimport itertools\nimport os\nimport re\nimport serial\nimport struct\nimport subprocess\nfrom typing import List, Union\n\nfrom cereal import log\nfrom selfdrive.hardware.base import HardwareBase, ThermalConfig\n\nNetworkType = log.DeviceState.NetworkType\nNetworkStrength = log.DeviceState.NetworkStrength\n\nMODEM_PATH = \"/dev/smd11\"\n\ndef service_call(call: List[str]) -> Union[bytes, None]:\n  try:\n    ret = subprocess.check_output([\"service\", \"call\", *call], encoding='utf8').strip()\n    if 'Parcel' not in ret:\n      return None\n    return parse_service_call_bytes(ret)\n  except subprocess.CalledProcessError:\n    return None\n\n\ndef parse_service_call_unpack(r, fmt) -> Union[bytes, None]:\n  try:\n    return struct.unpack(fmt, r)[0]\n  except Exception:\n    return None\n\n\ndef parse_service_call_string(r: bytes) -> Union[str, None]:\n  try:\n    r = r[8:]  # Cut off length field\n    r_str = r.decode('utf_16_be')\n\n    # All pairs of two characters seem to be swapped. Not sure why\n    result = \"\"\n    for a, b, in itertools.zip_longest(r_str[::2], r_str[1::2], fillvalue='\\x00'):\n      result += b + a\n\n    return result.replace('\\x00', '')\n  except Exception:\n    return None\n\n\ndef parse_service_call_bytes(ret: str) -> Union[bytes, None]:\n  try:\n    r = b\"\"\n    for hex_part in re.findall(r'[ (]([0-9a-f]{8})', ret):\n      r += binascii.unhexlify(hex_part)\n    return r\n  except Exception:\n    return None\n\n\ndef getprop(key: str) -> Union[str, None]:\n  try:\n    return subprocess.check_output([\"getprop\", key], encoding='utf8').strip()\n  except subprocess.CalledProcessError:\n    return None\n\n\nclass Android(HardwareBase):\n  def get_os_version(self):\n    with open(\"/VERSION\") as f:\n      return f.read().strip()\n\n  def get_device_type(self):\n    return \"eon\"\n\n  def get_sound_card_online(self):\n    return (os.path.isfile('/proc/asound/card0/state') and\n            open('/proc/asound/card0/state').read().strip() == 'ONLINE')\n\n  def get_imei(self, slot):\n    slot = str(slot)\n    if slot not in (\"0\", \"1\"):\n      raise ValueError(\"SIM slot must be 0 or 1\")\n\n    return parse_service_call_string(service_call([\"iphonesubinfo\", \"3\", \"i32\", str(slot)]))\n\n  def get_serial(self):\n    ret = getprop(\"ro.serialno\")\n    if len(ret) == 0:\n      ret = \"cccccccc\"\n    return ret\n\n  def get_subscriber_info(self):\n    ret = parse_service_call_string(service_call([\"iphonesubinfo\", \"7\"]))\n    if ret is None or len(ret) < 8:\n      return \"\"\n    return ret\n\n  def reboot(self, reason=None):\n    # e.g. reason=\"recovery\" to go into recover mode\n    if reason is None:\n      reason_args = [\"null\"]\n    else:\n      reason_args = [\"s16\", reason]\n\n    subprocess.check_output([\n      \"service\", \"call\", \"power\", \"16\",  # IPowerManager.reboot\n      \"i32\", \"0\",  # no confirmation,\n      *reason_args,\n      \"i32\", \"1\"  # wait\n    ])\n\n  def uninstall(self):\n    with open('/cache/recovery/command', 'w') as f:\n      f.write('--wipe_data\\n')\n    # IPowerManager.reboot(confirm=false, reason=\"recovery\", wait=true)\n    self.reboot(reason=\"recovery\")\n\n  def get_sim_info(self):\n    # Used for athena\n    # TODO: build using methods from this class\n    sim_state = getprop(\"gsm.sim.state\").split(\",\")\n    network_type = getprop(\"gsm.network.type\").split(',')\n    mcc_mnc = getprop(\"gsm.sim.operator.numeric\") or None\n\n    sim_id = parse_service_call_string(service_call(['iphonesubinfo', '11']))\n    cell_data_state = parse_service_call_unpack(service_call(['phone', '46']), \">q\")\n    cell_data_connected = (cell_data_state == 2)\n\n    return {\n      'sim_id': sim_id,\n      'mcc_mnc': mcc_mnc,\n      'network_type': network_type,\n      'sim_state': sim_state,\n      'data_connected': cell_data_connected\n    }\n\n  def get_network_info(self):\n    msg = log.DeviceState.NetworkInfo.new_message()\n    msg.state = getprop(\"gsm.sim.state\") or \"\"\n    msg.technology = getprop(\"gsm.network.type\") or \"\"\n    msg.operator = getprop(\"gsm.sim.operator.numeric\") or \"\"\n\n    try:\n      modem = serial.Serial(MODEM_PATH, 115200, timeout=0.1)\n      modem.write(b\"AT$QCRSRP?\\r\")\n      msg.extra = modem.read_until(b\"OK\\r\\n\").decode('utf-8')\n\n      rsrp = msg.extra.split(\"$QCRSRP: \")[1].split(\"\\r\")[0].split(\",\")\n      msg.channel = int(rsrp[1])\n    except Exception:\n      pass\n\n    return msg\n\n  def get_network_type(self):\n    wifi_check = parse_service_call_string(service_call([\"connectivity\", \"2\"]))\n    if wifi_check is None:\n      return NetworkType.none\n    elif 'WIFI' in wifi_check:\n      return NetworkType.wifi\n    else:\n      cell_check = parse_service_call_unpack(service_call(['phone', '59']), \">q\")\n      # from TelephonyManager.java\n      cell_networks = {\n        0: NetworkType.none,\n        1: NetworkType.cell2G,\n        2: NetworkType.cell2G,\n        3: NetworkType.cell3G,\n        4: NetworkType.cell2G,\n        5: NetworkType.cell3G,\n        6: NetworkType.cell3G,\n        7: NetworkType.cell3G,\n        8: NetworkType.cell3G,\n        9: NetworkType.cell3G,\n        10: NetworkType.cell3G,\n        11: NetworkType.cell2G,\n        12: NetworkType.cell3G,\n        13: NetworkType.cell4G,\n        14: NetworkType.cell4G,\n        15: NetworkType.cell3G,\n        16: NetworkType.cell2G,\n        17: NetworkType.cell3G,\n        18: NetworkType.cell4G,\n        19: NetworkType.cell4G\n      }\n      return cell_networks.get(cell_check, NetworkType.none)\n\n  def get_network_strength(self, network_type):\n    network_strength = NetworkStrength.unknown\n\n    # from SignalStrength.java\n    def get_lte_level(rsrp, rssnr):\n      INT_MAX = 2147483647\n      if rsrp == INT_MAX:\n        lvl_rsrp = NetworkStrength.unknown\n      elif rsrp >= -95:\n        lvl_rsrp = NetworkStrength.great\n      elif rsrp >= -105:\n        lvl_rsrp = NetworkStrength.good\n      elif rsrp >= -115:\n        lvl_rsrp = NetworkStrength.moderate\n      else:\n        lvl_rsrp = NetworkStrength.poor\n      if rssnr == INT_MAX:\n        lvl_rssnr = NetworkStrength.unknown\n      elif rssnr >= 45:\n        lvl_rssnr = NetworkStrength.great\n      elif rssnr >= 10:\n        lvl_rssnr = NetworkStrength.good\n      elif rssnr >= -30:\n        lvl_rssnr = NetworkStrength.moderate\n      else:\n        lvl_rssnr = NetworkStrength.poor\n      return max(lvl_rsrp, lvl_rssnr)\n\n    def get_tdscdma_level(tdscmadbm):\n      lvl = NetworkStrength.unknown\n      if tdscmadbm > -25:\n        lvl = NetworkStrength.unknown\n      elif tdscmadbm >= -49:\n        lvl = NetworkStrength.great\n      elif tdscmadbm >= -73:\n        lvl = NetworkStrength.good\n      elif tdscmadbm >= -97:\n        lvl = NetworkStrength.moderate\n      elif tdscmadbm >= -110:\n        lvl = NetworkStrength.poor\n      return lvl\n\n    def get_gsm_level(asu):\n      if asu <= 2 or asu == 99:\n        lvl = NetworkStrength.unknown\n      elif asu >= 12:\n        lvl = NetworkStrength.great\n      elif asu >= 8:\n        lvl = NetworkStrength.good\n      elif asu >= 5:\n        lvl = NetworkStrength.moderate\n      else:\n        lvl = NetworkStrength.poor\n      return lvl\n\n    def get_evdo_level(evdodbm, evdosnr):\n      lvl_evdodbm = NetworkStrength.unknown\n      lvl_evdosnr = NetworkStrength.unknown\n      if evdodbm >= -65:\n        lvl_evdodbm = NetworkStrength.great\n      elif evdodbm >= -75:\n        lvl_evdodbm = NetworkStrength.good\n      elif evdodbm >= -90:\n        lvl_evdodbm = NetworkStrength.moderate\n      elif evdodbm >= -105:\n        lvl_evdodbm = NetworkStrength.poor\n      if evdosnr >= 7:\n        lvl_evdosnr = NetworkStrength.great\n      elif evdosnr >= 5:\n        lvl_evdosnr = NetworkStrength.good\n      elif evdosnr >= 3:\n        lvl_evdosnr = NetworkStrength.moderate\n      elif evdosnr >= 1:\n        lvl_evdosnr = NetworkStrength.poor\n      return max(lvl_evdodbm, lvl_evdosnr)\n\n    def get_cdma_level(cdmadbm, cdmaecio):\n      lvl_cdmadbm = NetworkStrength.unknown\n      lvl_cdmaecio = NetworkStrength.unknown\n      if cdmadbm >= -75:\n        lvl_cdmadbm = NetworkStrength.great\n      elif cdmadbm >= -85:\n        lvl_cdmadbm = NetworkStrength.good\n      elif cdmadbm >= -95:\n        lvl_cdmadbm = NetworkStrength.moderate\n      elif cdmadbm >= -100:\n        lvl_cdmadbm = NetworkStrength.poor\n      if cdmaecio >= -90:\n        lvl_cdmaecio = NetworkStrength.great\n      elif cdmaecio >= -110:\n        lvl_cdmaecio = NetworkStrength.good\n      elif cdmaecio >= -130:\n        lvl_cdmaecio = NetworkStrength.moderate\n      elif cdmaecio >= -150:\n        lvl_cdmaecio = NetworkStrength.poor\n      return max(lvl_cdmadbm, lvl_cdmaecio)\n\n    if network_type == NetworkType.none:\n      return network_strength\n    if network_type == NetworkType.wifi:\n      out = subprocess.check_output('dumpsys connectivity', shell=True).decode('utf-8')\n      network_strength = NetworkStrength.unknown\n      for line in out.split('\\n'):\n        signal_str = \"SignalStrength: \"\n        if signal_str in line:\n          lvl_idx_start = line.find(signal_str) + len(signal_str)\n          lvl_idx_end = line.find(']', lvl_idx_start)\n          lvl = int(line[lvl_idx_start : lvl_idx_end])\n          if lvl >= -50:\n            network_strength = NetworkStrength.great\n          elif lvl >= -60:\n            network_strength = NetworkStrength.good\n          elif lvl >= -70:\n            network_strength = NetworkStrength.moderate\n          else:\n            network_strength = NetworkStrength.poor\n      return network_strength\n    else:\n      # check cell strength\n      out = subprocess.check_output('dumpsys telephony.registry', shell=True).decode('utf-8')\n      for line in out.split('\\n'):\n        if \"mSignalStrength\" in line:\n          arr = line.split(' ')\n          ns = 0\n          if (\"gsm\" in arr[14]):\n            rsrp = int(arr[9])\n            rssnr = int(arr[11])\n            ns = get_lte_level(rsrp, rssnr)\n            if ns == NetworkStrength.unknown:\n              tdscmadbm = int(arr[13])\n              ns = get_tdscdma_level(tdscmadbm)\n              if ns == NetworkStrength.unknown:\n                asu = int(arr[1])\n                ns = get_gsm_level(asu)\n          else:\n            cdmadbm = int(arr[3])\n            cdmaecio = int(arr[4])\n            evdodbm = int(arr[5])\n            evdosnr = int(arr[7])\n            lvl_cdma = get_cdma_level(cdmadbm, cdmaecio)\n            lvl_edmo = get_evdo_level(evdodbm, evdosnr)\n            if lvl_edmo == NetworkStrength.unknown:\n              ns = lvl_cdma\n            elif lvl_cdma == NetworkStrength.unknown:\n              ns = lvl_edmo\n            else:\n              ns = min(lvl_cdma, lvl_edmo)\n          network_strength = max(network_strength, ns)\n\n      return network_strength\n\n  def get_battery_capacity(self):\n    return self.read_param_file(\"/sys/class/power_supply/battery/capacity\", int, 100)\n\n  def get_battery_status(self):\n    # This does not correspond with actual charging or not.\n    # If a USB cable is plugged in, it responds with 'Charging', even when charging is disabled\n    return self.read_param_file(\"/sys/class/power_supply/battery/status\", lambda x: x.strip(), '')\n\n  def get_battery_current(self):\n    return self.read_param_file(\"/sys/class/power_supply/battery/current_now\", int)\n\n  def get_battery_voltage(self):\n    return self.read_param_file(\"/sys/class/power_supply/battery/voltage_now\", int)\n\n  def get_battery_charging(self):\n    # This does correspond with actually charging\n    return self.read_param_file(\"/sys/class/power_supply/battery/charge_type\", lambda x: x.strip() != \"N/A\", True)\n\n  def set_battery_charging(self, on):\n    with open('/sys/class/power_supply/battery/charging_enabled', 'w') as f:\n      f.write(f\"{1 if on else 0}\\n\")\n\n  def get_usb_present(self):\n    return self.read_param_file(\"/sys/class/power_supply/usb/present\", lambda x: bool(int(x)), False)\n\n  def get_current_power_draw(self):\n    # We don't have a good direct way to measure this on android\n    return None\n\n  def shutdown(self):\n    os.system('LD_LIBRARY_PATH=\"\" svc power shutdown')\n\n  def get_thermal_config(self):\n    return ThermalConfig(cpu=((5, 7, 10, 12), 10), gpu=((16,), 10), mem=(2, 10), bat=(29, 1000), ambient=(25, 1))\n\n  def set_screen_brightness(self, percentage):\n    with open(\"/sys/class/leds/lcd-backlight/brightness\", \"w\") as f:\n      f.write(str(int(percentage * 2.55)))\n\n  def set_power_save(self, powersave_enabled):\n    pass\n\n  def get_gpu_usage_percent(self):\n    try:\n      used, total = open('/sys/devices/soc/b00000.qcom,kgsl-3d0/kgsl/kgsl-3d0/gpubusy').read().strip().split()\n      perc = 100.0 * int(used) / int(total)\n      return min(max(perc, 0), 100)\n    except Exception:\n      return 0\n\n  def get_modem_version(self):\n    return None\n\n  def initialize_hardware(self):\n    pass\n\n  def get_networks(self):\n    return None"
  },
  {
    "path": "selfdrive/hardware/hw.h",
    "content": "#pragma once\n\n#include \"selfdrive/hardware/base.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/params.h\"\n\n#ifdef QCOM\n#include \"selfdrive/hardware/eon/hardware.h\"\n#define Hardware HardwareEon\n#elif QCOM2\n#include \"selfdrive/hardware/tici/hardware.h\"\n#define Hardware HardwareTici\n#elif XNX\n#include \"selfdrive/hardware/jetson/hardware.h\"\n#define Hardware HardwareJetson\n#else\nclass HardwarePC : public HardwareNone {\npublic:\n  static std::string get_os_version() { return \"openpilot for PC\"; }\n  static bool PC() { return true; }\n};\n#define Hardware HardwarePC\n#endif\n\nnamespace Path {\ninline static std::string HOME = util::getenv(\"HOME\");\ninline std::string log_root() {\n  if (const char *env = getenv(\"LOG_ROOT\")) {\n    return env;\n  }\n  if (Params().getBool(\"dp_atl\") || Params().getBool(\"dp_jetson\")) {\n    return \"/data/media/0/fakedata\";\n  } else {\n    return Hardware::PC() ? HOME + \"/.comma/media/0/realdata\" : \"/data/media/0/realdata\";\n  }\n}\ninline std::string params() {\n  return Hardware::PC() ? HOME + \"/.comma/params\" : \"/data/params\";\n}\ninline std::string rsa_file() {\n  return Hardware::PC() ? HOME + \"/.comma/persist/comma/id_rsa\" : \"/persist/comma/id_rsa\";\n}\n}  // namespace Path\n"
  },
  {
    "path": "selfdrive/hardware/jetson/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/hardware/jetson/hardware.h",
    "content": "#pragma once\n\n#include <cstdlib>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/base.h\"\n\nclass HardwareJetson : public HardwareNone {\npublic:\n\n  static bool JETSON() { return true; }\n\n  static void reboot() { std::system(\"sudo reboot\"); };\n  static void poweroff() { std::system(\"sudo poweroff\"); };\n};\n"
  },
  {
    "path": "selfdrive/hardware/jetson/hardware.py",
    "content": "import random\nimport os\n\nfrom cereal import log\nfrom selfdrive.hardware.base import HardwareBase, ThermalConfig\n\nNetworkType = log.DeviceState.NetworkType\nNetworkStrength = log.DeviceState.NetworkStrength\n\n\nclass Jetson(HardwareBase):\n\n\n  def get_os_version(self):\n    return None\n\n  def get_device_type(self):\n    return \"jetson\"\n\n  def get_sound_card_online(self):\n    return True\n\n  def reboot(self, reason=None):\n    os.system(\"sudo reboot\")\n\n  def uninstall(self):\n    pass\n\n  def get_imei(self, slot):\n    return \"%015d\" % random.randint(0, 1 << 32)\n\n  def get_serial(self):\n    return \"cccccccc\"\n\n  def get_subscriber_info(self):\n    return \"\"\n\n  def get_network_type(self):\n    return NetworkType.wifi\n\n  def get_sim_info(self):\n    return {\n      'sim_id': '',\n      'mcc_mnc': None,\n      'network_type': [\"Unknown\"],\n      'sim_state': [\"ABSENT\"],\n      'data_connected': False\n    }\n\n  def get_network_strength(self, network_type):\n    return NetworkStrength.unknown\n\n  def get_battery_capacity(self):\n    return 100\n\n  def get_battery_status(self):\n    return \"\"\n\n  def get_battery_current(self):\n    return 0\n\n  def get_battery_voltage(self):\n    return 0\n\n  def get_battery_charging(self):\n    return True\n\n  def set_battery_charging(self, on):\n    pass\n\n  def get_usb_present(self):\n    return True\n\n  def get_current_power_draw(self):\n    return 0\n\n  def shutdown(self):\n    os.system(\"sudo poweroff\")\n\n  def get_thermal_config(self):\n    # 0 = CPU\n    # 1 = GPU\n    # 2 = AUX\n    # 3 = AO (always on rail)\n    # 4 = PMIC-Die\n    # 5 = Thermal-fan-est\n    return ThermalConfig(cpu=((0,), 1000), gpu=((1,), 1000), mem=(4, 1000), bat=(None, 1), ambient=(3, 1000))\n\n  def set_screen_brightness(self, percentage):\n    pass\n\n  def set_power_save(self, enabled):\n    pass\n\n  def get_gpu_usage_percent(self):\n    return 0\n\n  def get_modem_version(self):\n    return None\n\n  def initialize_hardware(self):\n    pass\n\n  def get_networks(self):\n    return None\n"
  },
  {
    "path": "selfdrive/hardware/pc/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/hardware/pc/hardware.py",
    "content": "import random\n\nfrom cereal import log\nfrom selfdrive.hardware.base import HardwareBase, ThermalConfig\n\nNetworkType = log.DeviceState.NetworkType\nNetworkStrength = log.DeviceState.NetworkStrength\n\n\nclass Pc(HardwareBase):\n  def get_os_version(self):\n    return None\n\n  def get_device_type(self):\n    return \"pc\"\n\n  def get_sound_card_online(self):\n    return True\n\n  def reboot(self, reason=None):\n    print(\"REBOOT!\")\n\n  def uninstall(self):\n    print(\"uninstall\")\n\n  def get_imei(self, slot):\n    return \"%015d\" % random.randint(0, 1 << 32)\n\n  def get_serial(self):\n    return \"cccccccc\"\n\n  def get_subscriber_info(self):\n    return \"\"\n\n  def get_network_info(self):\n    return None\n\n  def get_network_type(self):\n    return NetworkType.wifi\n\n  def get_sim_info(self):\n    return {\n      'sim_id': '',\n      'mcc_mnc': None,\n      'network_type': [\"Unknown\"],\n      'sim_state': [\"ABSENT\"],\n      'data_connected': False\n    }\n\n  def get_network_strength(self, network_type):\n    return NetworkStrength.unknown\n\n  def get_battery_capacity(self):\n    return 100\n\n  def get_battery_status(self):\n    return \"\"\n\n  def get_battery_current(self):\n    return 0\n\n  def get_battery_voltage(self):\n    return 0\n\n  def get_battery_charging(self):\n    return True\n\n  def set_battery_charging(self, on):\n    pass\n\n  def get_usb_present(self):\n    return False\n\n  def get_current_power_draw(self):\n    return 0\n\n  def shutdown(self):\n    print(\"SHUTDOWN!\")\n\n  def get_thermal_config(self):\n    return ThermalConfig(cpu=((None,), 1), gpu=((None,), 1), mem=(None, 1), bat=(None, 1), ambient=(None, 1))\n\n  def set_screen_brightness(self, percentage):\n    pass\n\n  def set_power_save(self, powersave_enabled):\n    pass\n\n  def get_gpu_usage_percent(self):\n    return 0\n\n  def get_modem_version(self):\n    return None\n\n  def initialize_hardware(self):\n    pass\n\n  def get_networks(self):\n    return None"
  },
  {
    "path": "selfdrive/hardware/tici/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/hardware/tici/agnos.json",
    "content": "[\n  {\n    \"name\": \"boot\",\n    \"url\": \"https://commadist.azureedge.net/agnosupdate/boot-e992b0461fc7705ce54f556247cd721b04d4d28885a461cd536389fd0bcb7e9c.img.xz\",\n    \"hash\": \"e992b0461fc7705ce54f556247cd721b04d4d28885a461cd536389fd0bcb7e9c\",\n    \"hash_raw\": \"e992b0461fc7705ce54f556247cd721b04d4d28885a461cd536389fd0bcb7e9c\",\n    \"size\": 14772224,\n    \"sparse\": false,\n    \"full_check\": true,\n    \"has_ab\": true\n  },\n  {\n    \"name\": \"abl\",\n    \"url\": \"https://commadist.azureedge.net/agnosupdate/abl-ab4068f005ed9cb7fbca55c6d658880df1abfb1a4e6afb64f3fc5e64dac6fc82.img.xz\",\n    \"hash\": \"ab4068f005ed9cb7fbca55c6d658880df1abfb1a4e6afb64f3fc5e64dac6fc82\",\n    \"hash_raw\": \"ab4068f005ed9cb7fbca55c6d658880df1abfb1a4e6afb64f3fc5e64dac6fc82\",\n    \"size\": 274432,\n    \"sparse\": false,\n    \"full_check\": true,\n    \"has_ab\": true\n  },\n  {\n    \"name\": \"xbl\",\n    \"url\": \"https://commadist.azureedge.net/agnosupdate/xbl-2b1b67aa918cd127f2b0b4ed0a372f3a93676cf9d270bd3e56329516efdc5a35.img.xz\",\n    \"hash\": \"2b1b67aa918cd127f2b0b4ed0a372f3a93676cf9d270bd3e56329516efdc5a35\",\n    \"hash_raw\": \"2b1b67aa918cd127f2b0b4ed0a372f3a93676cf9d270bd3e56329516efdc5a35\",\n    \"size\": 3670016,\n    \"sparse\": false,\n    \"full_check\": true,\n    \"has_ab\": true\n  },\n  {\n    \"name\": \"xbl_config\",\n    \"url\": \"https://commadist.azureedge.net/agnosupdate/xbl_config-3aa926394b4cec464300bfc0e7ab77d50889b38041138c60cd84c397930b38ad.img.xz\",\n    \"hash\": \"3aa926394b4cec464300bfc0e7ab77d50889b38041138c60cd84c397930b38ad\",\n    \"hash_raw\": \"3aa926394b4cec464300bfc0e7ab77d50889b38041138c60cd84c397930b38ad\",\n    \"size\": 364544,\n    \"sparse\": false,\n    \"full_check\": true,\n    \"has_ab\": true\n  },\n  {\n    \"name\": \"system\",\n    \"url\": \"https://commadist.azureedge.net/agnosupdate/system-c4e5875c90b2a74e075d555cba9d8b50839fd85d76ac71b89884e5b37312cffc.img.xz\",\n    \"hash\": \"93ee8c5eac72289ebae245c1e48707865c5ead7e8ae53f9066bae8a0a58d1a48\",\n    \"hash_raw\": \"c4e5875c90b2a74e075d555cba9d8b50839fd85d76ac71b89884e5b37312cffc\",\n    \"size\": 10737418240,\n    \"sparse\": true,\n    \"full_check\": false,\n    \"has_ab\": true\n  }\n]\n"
  },
  {
    "path": "selfdrive/hardware/tici/agnos.py",
    "content": "#!/usr/bin/env python3\nimport json\nimport lzma\nimport hashlib\nimport requests\nimport struct\nimport subprocess\nimport os\nfrom typing import Generator\n\nSPARSE_CHUNK_FMT = struct.Struct('H2xI4x')\n\n\nclass StreamingDecompressor:\n  def __init__(self, url: str) -> None:\n    self.buf = b\"\"\n\n    self.req = requests.get(url, stream=True, headers={'Accept-Encoding': None})\n    self.it = self.req.iter_content(chunk_size=1024 * 1024)\n    self.decompressor = lzma.LZMADecompressor(format=lzma.FORMAT_AUTO)\n    self.eof = False\n    self.sha256 = hashlib.sha256()\n\n  def read(self, length: int) -> bytes:\n    while len(self.buf) < length:\n      self.req.raise_for_status()\n\n      try:\n        compressed = next(self.it)\n      except StopIteration:\n        self.eof = True\n        break\n      out = self.decompressor.decompress(compressed)\n      self.buf += out\n\n    result = self.buf[:length]\n    self.buf = self.buf[length:]\n\n    self.sha256.update(result)\n    return result\n\n\ndef unsparsify(f: StreamingDecompressor) -> Generator[bytes, None, None]:\n  # https://source.android.com/devices/bootloader/images#sparse-format\n  magic = struct.unpack(\"I\", f.read(4))[0]\n  assert(magic == 0xed26ff3a)\n\n  # Version\n  major = struct.unpack(\"H\", f.read(2))[0]\n  minor = struct.unpack(\"H\", f.read(2))[0]\n  assert(major == 1 and minor == 0)\n\n  f.read(2)  # file header size\n  f.read(2)  # chunk header size\n\n  block_sz = struct.unpack(\"I\", f.read(4))[0]\n  f.read(4)  # total blocks\n  num_chunks = struct.unpack(\"I\", f.read(4))[0]\n  f.read(4)  # crc checksum\n\n  for _ in range(num_chunks):\n    chunk_type, out_blocks = SPARSE_CHUNK_FMT.unpack(f.read(12))\n\n    if chunk_type == 0xcac1:  # Raw\n      # TODO: yield in smaller chunks. Yielding only block_sz is too slow. Largest observed data chunk is 252 MB.\n      yield f.read(out_blocks * block_sz)\n    elif chunk_type == 0xcac2:  # Fill\n      filler = f.read(4) * (block_sz // 4)\n      for _ in range(out_blocks):\n        yield filler\n    elif chunk_type == 0xcac3:  # Don't care\n      yield b\"\"\n    else:\n      raise Exception(\"Unhandled sparse chunk type\")\n\n\ndef get_target_slot_number() -> int:\n  current_slot = subprocess.check_output([\"abctl\", \"--boot_slot\"], encoding='utf-8').strip()\n  return 1 if current_slot == \"_a\" else 0\n\n\ndef slot_number_to_suffix(slot_number: int) -> str:\n  assert slot_number in (0, 1)\n  return '_a' if slot_number == 0 else '_b'\n\n\ndef get_partition_path(target_slot_number: int, partition: dict) -> str:\n  path = f\"/dev/disk/by-partlabel/{partition['name']}\"\n\n  if partition.get('has_ab', True):\n    path += slot_number_to_suffix(target_slot_number)\n\n  return path\n\n\ndef verify_partition(target_slot_number: int, partition: dict) -> bool:\n  full_check = partition['full_check']\n  path = get_partition_path(target_slot_number, partition)\n  partition_size = partition['size']\n\n  with open(path, 'rb+') as out:\n    if full_check:\n      raw_hash = hashlib.sha256()\n\n      pos = 0\n      chunk_size = 1024 * 1024\n      while pos < partition_size:\n        n = min(chunk_size, partition_size - pos)\n        raw_hash.update(out.read(n))\n        pos += n\n\n      return raw_hash.hexdigest().lower() == partition['hash_raw'].lower()\n    else:\n      out.seek(partition_size)\n      return out.read(64) == partition['hash_raw'].lower().encode()\n\n\ndef clear_partition_hash(target_slot_number: int, partition: dict) -> None:\n  path = get_partition_path(target_slot_number, partition)\n  with open(path, 'wb+') as out:\n    partition_size = partition['size']\n\n    out.seek(partition_size)\n    out.write(b\"\\x00\" * 64)\n    os.sync()\n\n\ndef flash_partition(target_slot_number: int, partition: dict, cloudlog):\n  cloudlog.info(f\"Downloading and writing {partition['name']}\")\n\n  if verify_partition(target_slot_number, partition):\n    cloudlog.info(f\"Already flashed {partition['name']}\")\n    return\n\n  downloader = StreamingDecompressor(partition['url'])\n\n  # Clear hash before flashing in case we get interrupted\n  full_check = partition['full_check']\n  if not full_check:\n    clear_partition_hash(target_slot_number, partition)\n\n  path = get_partition_path(target_slot_number, partition)\n  with open(path, 'wb+') as out:\n    partition_size = partition['size']\n\n    # Flash partition\n    if partition['sparse']:\n      raw_hash = hashlib.sha256()\n      for chunk in unsparsify(downloader):\n        raw_hash.update(chunk)\n        out.write(chunk)\n        p = int(out.tell() / partition_size * 100)\n        print(f\"Installing {partition['name']}: {p}\")\n\n      if raw_hash.hexdigest().lower() != partition['hash_raw'].lower():\n        raise Exception(f\"Unsparse hash mismatch '{raw_hash.hexdigest().lower()}'\")\n    else:\n      while not downloader.eof:\n        out.write(downloader.read(1024 * 1024))\n\n    if downloader.sha256.hexdigest().lower() != partition['hash'].lower():\n      raise Exception(\"Uncompressed hash mismatch\")\n\n    if out.tell() != partition['size']:\n      raise Exception(\"Uncompressed size mismatch\")\n\n    # Write hash after successfull flash\n    os.sync()\n    if not full_check:\n      out.write(partition['hash_raw'].lower().encode())\n\n\ndef swap(manifest_path: str, target_slot_number: int, cloudlog) -> None:\n  update = json.load(open(manifest_path))\n  for partition in update:\n    if not partition.get('full_check', False):\n      clear_partition_hash(target_slot_number, partition)\n\n  while True:\n    out = subprocess.check_output(f\"abctl --set_active {target_slot_number}\", shell=True, stderr=subprocess.STDOUT, encoding='utf8')\n    if (\"No such file or directory\" not in out) and (\"lun as boot lun\" in out):\n      cloudlog.info(f\"Swap successfull {out}\")\n      break\n    else:\n      cloudlog.error(f\"Swap failed {out}\")\n\n\ndef flash_agnos_update(manifest_path: str, target_slot_number: int, cloudlog) -> None:\n  update = json.load(open(manifest_path))\n\n  cloudlog.info(f\"Target slot {target_slot_number}\")\n\n  # set target slot as unbootable\n  os.system(f\"abctl --set_unbootable {target_slot_number}\")\n\n  for partition in update:\n    success = False\n\n    for retries in range(10):\n      try:\n        flash_partition(target_slot_number, partition, cloudlog)\n        success = True\n        break\n\n      except requests.exceptions.RequestException:\n        cloudlog.exception(\"Failed\")\n        cloudlog.info(f\"Failed to download {partition['name']}, retrying ({retries})\")\n        time.sleep(10)\n\n    if not success:\n      cloudlog.info(f\"Failed to flash {partition['name']}, aborting\")\n      raise Exception(\"Maximum retries exceeded\")\n\n  cloudlog.info(f\"AGNOS ready on slot {target_slot_number}\")\n\n\ndef verify_agnos_update(manifest_path: str, target_slot_number: int) -> bool:\n  update = json.load(open(manifest_path))\n  return all(verify_partition(target_slot_number, partition) for partition in update)\n\n\nif __name__ == \"__main__\":\n  import logging\n  import time\n  import argparse\n\n  parser = argparse.ArgumentParser(description=\"Flash and verify AGNOS update\",\n                                   formatter_class=argparse.ArgumentDefaultsHelpFormatter)\n\n  parser.add_argument(\"--verify\", action=\"store_true\", help=\"Verify and perform swap if update ready\")\n  parser.add_argument(\"--swap\", action=\"store_true\", help=\"Verify and perform swap, downloads if necessary\")\n  parser.add_argument(\"manifest\", help=\"Manifest json\")\n  args = parser.parse_args()\n\n  logging.basicConfig(level=logging.INFO)\n\n  target_slot_number = get_target_slot_number()\n  if args.verify:\n    if verify_agnos_update(args.manifest, target_slot_number):\n      swap(args.manifest, target_slot_number, logging)\n      exit(0)\n    exit(1)\n  elif args.swap:\n    while not verify_agnos_update(args.manifest, target_slot_number):\n      logging.error(\"Verification failed. Flashing AGNOS\")\n      flash_agnos_update(args.manifest, target_slot_number, logging)\n\n    logging.warning(f\"Verification succeeded. Swapping to slot {target_slot_number}\")\n    swap(args.manifest, target_slot_number, logging)\n  else:\n    flash_agnos_update(args.manifest, target_slot_number, logging)\n"
  },
  {
    "path": "selfdrive/hardware/tici/amplifier.py",
    "content": "#!/usr/bin/env python\nfrom smbus2 import SMBus\nfrom collections import namedtuple\n\n# https://datasheets.maximintegrated.com/en/ds/MAX98089.pdf\n\nAmpConfig = namedtuple('AmpConfig', ['name', 'value', 'register', 'offset', 'mask'])\nEQParams = namedtuple('EQParams', ['K', 'k1', 'k2', 'c1', 'c2'])\n\ndef configs_from_eq_params(base, eq_params):\n  return [\n    AmpConfig(\"K (high)\", (eq_params.K >> 8), base, 0, 0xFF),\n    AmpConfig(\"K (low)\", (eq_params.K & 0xFF), base + 1, 0, 0xFF),\n    AmpConfig(\"k1 (high)\", (eq_params.k1 >> 8), base + 2, 0, 0xFF),\n    AmpConfig(\"k1 (low)\", (eq_params.k1 & 0xFF), base + 3, 0, 0xFF),\n    AmpConfig(\"k2 (high)\", (eq_params.k2 >> 8), base + 4, 0, 0xFF),\n    AmpConfig(\"k2 (low)\", (eq_params.k2 & 0xFF), base + 5, 0, 0xFF),\n    AmpConfig(\"c1 (high)\", (eq_params.c1 >> 8), base + 6, 0, 0xFF),\n    AmpConfig(\"c1 (low)\", (eq_params.c1 & 0xFF), base + 7, 0, 0xFF),\n    AmpConfig(\"c2 (high)\", (eq_params.c2 >> 8), base + 8, 0, 0xFF),\n    AmpConfig(\"c2 (low)\", (eq_params.c2 & 0xFF), base + 9, 0, 0xFF),\n  ]\n\nBASE_CONFIG = [\n  AmpConfig(\"MCLK prescaler\", 0b01, 0x10, 4, 0b00110000),\n  AmpConfig(\"PM: enable speakers\", 0b11, 0x4D, 4, 0b00110000),\n  AmpConfig(\"PM: enable DACs\", 0b11, 0x4D, 0, 0b00000011),\n  AmpConfig(\"Right speaker output from right DAC\", 0b1, 0x2C, 0, 0b11111111),\n  AmpConfig(\"Right Speaker Mixer Gain\", 0b00, 0x2D, 2, 0b00001100),\n  AmpConfig(\"Enable PLL1\", 0b1, 0x12, 7, 0b10000000),\n  AmpConfig(\"Enable PLL2\", 0b1, 0x1A, 7, 0b10000000),\n  AmpConfig(\"DAI1: I2S mode\", 0b00100, 0x14, 2, 0b01111100),\n  AmpConfig(\"DAI2: I2S mode\", 0b00100, 0x1C, 2, 0b01111100),\n  AmpConfig(\"Right speaker output volume\", 0x1a, 0x3E, 0, 0b00011111),\n  AmpConfig(\"DAI1 Passband filtering: music mode\", 0b1, 0x18, 7, 0b10000000),\n  AmpConfig(\"DAI1 voice mode gain (DV1G)\", 0b00, 0x2F, 4, 0b00110000),\n  AmpConfig(\"DAI1 attenuation (DV1)\", 0x0, 0x2F, 0, 0b00001111),\n  AmpConfig(\"DAI2 attenuation (DV2)\", 0x0, 0x31, 0, 0b00001111),\n  AmpConfig(\"DAI2: DC blocking\", 0b1, 0x20, 0, 0b00000001),\n  AmpConfig(\"DAI2: High sample rate\", 0b0, 0x20, 3, 0b00001000),\n  AmpConfig(\"ALC enable\", 0b0, 0x43, 7, 0b10000000),\n  AmpConfig(\"ALC/excursion limiter release time\", 0b101, 0x43, 4, 0b01110000),\n  AmpConfig(\"DAI1 EQ enable\", 0b0, 0x49, 0, 0b00000001),\n  AmpConfig(\"DAI2 EQ enable\", 0b0, 0x49, 1, 0b00000010),\n  AmpConfig(\"DAI2 EQ clip detection disabled\", 0b1, 0x32, 4, 0b00010000),\n  AmpConfig(\"DAI2 EQ attenuation\", 0x5, 0x32, 0, 0b00001111),\n  AmpConfig(\"Excursion limiter upper corner freq\", 0b100, 0x41, 4, 0b01110000),\n  AmpConfig(\"Excursion limiter lower corner freq\", 0b00, 0x41, 0, 0b00000011),\n  AmpConfig(\"Excursion limiter threshold\", 0b000, 0x42, 0, 0b00001111),\n  AmpConfig(\"Distortion limit (THDCLP)\", 0x6, 0x46, 4, 0b11110000),\n  AmpConfig(\"Distortion limiter release time constant\", 0b0, 0x46, 0, 0b00000001),\n  AmpConfig(\"Right DAC input mixer: DAI1 left\", 0b0, 0x22, 3, 0b00001000),\n  AmpConfig(\"Right DAC input mixer: DAI1 right\", 0b0, 0x22, 2, 0b00000100),\n  AmpConfig(\"Right DAC input mixer: DAI2 left\", 0b1, 0x22, 1, 0b00000010),\n  AmpConfig(\"Right DAC input mixer: DAI2 right\", 0b0, 0x22, 0, 0b00000001),\n  AmpConfig(\"DAI1 audio port selector\", 0b10, 0x16, 6, 0b11000000),\n  AmpConfig(\"DAI2 audio port selector\", 0b01, 0x1E, 6, 0b11000000),\n  AmpConfig(\"Enable left digital microphone\", 0b1, 0x48, 5, 0b00100000),\n  AmpConfig(\"Enable right digital microphone\", 0b1, 0x48, 4, 0b00010000),\n  AmpConfig(\"Enhanced volume smoothing disabled\", 0b0, 0x49, 7, 0b10000000),\n  AmpConfig(\"Volume adjustment smoothing disabled\", 0b0, 0x49, 6, 0b01000000),\n  AmpConfig(\"Zero-crossing detection disabled\", 0b0, 0x49, 5, 0b00100000),\n]\n\nBASE_CONFIG += configs_from_eq_params(0x84, EQParams(0x65C4, 0xC07C, 0x3D66, 0x07D9, 0x120F))\nBASE_CONFIG += configs_from_eq_params(0x8E, EQParams(0x1009, 0xC6BF, 0x2952, 0x1C97, 0x30DF))\nBASE_CONFIG += configs_from_eq_params(0x98, EQParams(0x2822, 0xC1C7, 0x3B50, 0x0EF8, 0x180A))\nBASE_CONFIG += configs_from_eq_params(0xA2, EQParams(0x1009, 0xC5C2, 0x271F, 0x1A87, 0x32A6))\nBASE_CONFIG += configs_from_eq_params(0xAC, EQParams(0x2000, 0xCA1E, 0x4000, 0x2287, 0x0000))\n\nclass Amplifier:\n  AMP_I2C_BUS = 0\n  AMP_ADDRESS = 0x10\n\n  def __init__(self, debug=False):\n    self.debug = debug\n\n  def set_config(self, config):\n    with SMBus(self.AMP_I2C_BUS) as bus:\n      if self.debug:\n        print(f\"Setting \\\"{config.name}\\\" to {config.value}:\")\n\n      old_value = bus.read_byte_data(self.AMP_ADDRESS, config.register, force=True)\n      new_value = (old_value & (~config.mask)) | ((config.value << config.offset) & config.mask)\n      bus.write_byte_data(self.AMP_ADDRESS, config.register, new_value, force=True)\n\n      if self.debug:\n        print(f\"  Changed {hex(config.register)}: {hex(old_value)} -> {hex(new_value)}\")\n\n  def set_global_shutdown(self, amp_disabled):\n    self.set_config(AmpConfig(\"Global shutdown\", 0b0 if amp_disabled else 0b1, 0x51, 7, 0b10000000))\n\n  def initialize_configuration(self):\n    self.set_global_shutdown(amp_disabled=True)\n\n    for config in BASE_CONFIG:\n      self.set_config(config)\n\n    self.set_global_shutdown(amp_disabled=False)\n\n\nif __name__ == \"__main__\":\n  Amplifier(debug=True).initialize_configuration()\n"
  },
  {
    "path": "selfdrive/hardware/tici/hardware.h",
    "content": "#pragma once\n\n#include <cstdlib>\n#include <fstream>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/base.h\"\n\nclass HardwareTici : public HardwareNone {\npublic:\n  static constexpr float MAX_VOLUME = 1.0;\n  static constexpr float MIN_VOLUME = 0.4;\n  static bool TICI() { return true; }\n  static std::string get_os_version() {\n    return \"AGNOS \" + util::read_file(\"/VERSION\");\n  };\n\n  static void reboot() { std::system(\"sudo reboot\"); };\n  static void poweroff() { std::system(\"sudo poweroff\"); };\n  static void set_brightness(int percent) {\n    std::ofstream brightness_control(\"/sys/class/backlight/panel0-backlight/brightness\");\n    if (brightness_control.is_open()) {\n      brightness_control << (percent * (int)(1023/100.)) << \"\\n\";\n      brightness_control.close();\n    }\n  };\n  static void set_display_power(bool on) {\n    std::ofstream bl_power_control(\"/sys/class/backlight/panel0-backlight/bl_power\");\n    if (bl_power_control.is_open()) {\n      bl_power_control << (on ? \"0\" : \"4\") << \"\\n\";\n      bl_power_control.close();\n    }\n  };\n\n  static bool get_ssh_enabled() { return Params().getBool(\"SshEnabled\"); };\n  static void set_ssh_enabled(bool enabled) { Params().putBool(\"SshEnabled\", enabled); };\n};\n"
  },
  {
    "path": "selfdrive/hardware/tici/hardware.py",
    "content": "import os\nfrom functools import cached_property\nfrom enum import IntEnum\nimport subprocess\nfrom pathlib import Path\n\nfrom cereal import log\nfrom selfdrive.hardware.base import HardwareBase, ThermalConfig\nfrom selfdrive.hardware.tici.amplifier import Amplifier\nfrom selfdrive.hardware.tici import iwlist\n\nNM = 'org.freedesktop.NetworkManager'\nNM_CON_ACT = NM + '.Connection.Active'\nNM_DEV_WL = NM + '.Device.Wireless'\nNM_AP = NM + '.AccessPoint'\nDBUS_PROPS = 'org.freedesktop.DBus.Properties'\n\nMM = 'org.freedesktop.ModemManager1'\nMM_MODEM = MM + \".Modem\"\nMM_MODEM_SIMPLE = MM + \".Modem.Simple\"\nMM_SIM = MM + \".Sim\"\n\nclass MM_MODEM_STATE(IntEnum):\n       FAILED        = -1\n       UNKNOWN       = 0\n       INITIALIZING  = 1\n       LOCKED        = 2\n       DISABLED      = 3\n       DISABLING     = 4\n       ENABLING      = 5\n       ENABLED       = 6\n       SEARCHING     = 7\n       REGISTERED    = 8\n       DISCONNECTING = 9\n       CONNECTING    = 10\n       CONNECTED     = 11\n\nTIMEOUT = 0.1\n\nNetworkType = log.DeviceState.NetworkType\nNetworkStrength = log.DeviceState.NetworkStrength\n\n# https://developer.gnome.org/ModemManager/unstable/ModemManager-Flags-and-Enumerations.html#MMModemAccessTechnology\nMM_MODEM_ACCESS_TECHNOLOGY_UMTS = 1 << 5\nMM_MODEM_ACCESS_TECHNOLOGY_LTE = 1 << 14\n\nclass Tici(HardwareBase):\n  @cached_property\n  def bus(self):\n    import dbus  # pylint: disable=import-error\n    return dbus.SystemBus()\n\n  @cached_property\n  def nm(self):\n    return self.bus.get_object(NM, '/org/freedesktop/NetworkManager')\n\n  @cached_property\n  def mm(self):\n    return self.bus.get_object(MM, '/org/freedesktop/ModemManager1')\n\n  @cached_property\n  def amplifier(self):\n    return Amplifier()\n\n  def get_os_version(self):\n    with open(\"/VERSION\") as f:\n      return f.read().strip()\n\n  def get_device_type(self):\n    return \"tici\"\n\n  def get_sound_card_online(self):\n    return (os.path.isfile('/proc/asound/card0/state') and\n            open('/proc/asound/card0/state').read().strip() == 'ONLINE')\n\n  def reboot(self, reason=None):\n    subprocess.check_output([\"sudo\", \"reboot\"])\n\n  def uninstall(self):\n    Path(\"/data/__system_reset__\").touch()\n    os.sync()\n    self.reboot()\n\n  def get_serial(self):\n    return self.get_cmdline()['androidboot.serialno']\n\n  def get_network_type(self):\n    try:\n      primary_connection = self.nm.Get(NM, 'PrimaryConnection', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n      primary_connection = self.bus.get_object(NM, primary_connection)\n      primary_type = primary_connection.Get(NM_CON_ACT, 'Type', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n      primary_id = primary_connection.Get(NM_CON_ACT, 'Id', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n\n      if primary_type == '802-3-ethernet':\n        return NetworkType.ethernet\n      elif primary_type == '802-11-wireless' and primary_id != 'Hotspot':\n        return NetworkType.wifi\n      else:\n        active_connections = self.nm.Get(NM, 'ActiveConnections', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n        for conn in active_connections:\n          c = self.bus.get_object(NM, conn)\n          tp = c.Get(NM_CON_ACT, 'Type', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n          if tp == 'gsm':\n            modem = self.get_modem()\n            access_t = modem.Get(MM_MODEM, 'AccessTechnologies', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n            if access_t >= MM_MODEM_ACCESS_TECHNOLOGY_LTE:\n              return NetworkType.cell4G\n            elif access_t >= MM_MODEM_ACCESS_TECHNOLOGY_UMTS:\n              return NetworkType.cell3G\n            else:\n              return NetworkType.cell2G\n    except Exception:\n      pass\n\n    return NetworkType.none\n\n  def get_modem(self):\n    objects = self.mm.GetManagedObjects(dbus_interface=\"org.freedesktop.DBus.ObjectManager\", timeout=TIMEOUT)\n    modem_path = list(objects.keys())[0]\n    return self.bus.get_object(MM, modem_path)\n\n  def get_wlan(self):\n    wlan_path = self.nm.GetDeviceByIpIface('wlan0', dbus_interface=NM, timeout=TIMEOUT)\n    return self.bus.get_object(NM, wlan_path)\n\n  def get_sim_info(self):\n    modem = self.get_modem()\n    sim_path = modem.Get(MM_MODEM, 'Sim', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n\n    if sim_path == \"/\":\n      return {\n        'sim_id': '',\n        'mcc_mnc': None,\n        'network_type': [\"Unknown\"],\n        'sim_state': [\"ABSENT\"],\n        'data_connected': False\n      }\n    else:\n      sim = self.bus.get_object(MM, sim_path)\n      return {\n        'sim_id': str(sim.Get(MM_SIM, 'SimIdentifier', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)),\n        'mcc_mnc': str(sim.Get(MM_SIM, 'OperatorIdentifier', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)),\n        'network_type': [\"Unknown\"],\n        'sim_state': [\"READY\"],\n        'data_connected': modem.Get(MM_MODEM, 'State', dbus_interface=DBUS_PROPS, timeout=TIMEOUT) == MM_MODEM_STATE.CONNECTED,\n      }\n\n  def get_subscriber_info(self):\n    return \"\"\n\n  def get_imei(self, slot):\n    if slot != 0:\n      return \"\"\n\n    return str(self.get_modem().Get(MM_MODEM, 'EquipmentIdentifier', dbus_interface=DBUS_PROPS, timeout=TIMEOUT))\n\n  def get_network_info(self):\n    modem = self.get_modem()\n    try:\n      info = modem.Command(\"AT+QNWINFO\", int(TIMEOUT * 1000), dbus_interface=MM_MODEM, timeout=TIMEOUT)\n      extra = modem.Command('AT+QENG=\"servingcell\"', int(TIMEOUT * 1000), dbus_interface=MM_MODEM, timeout=TIMEOUT)\n      state = modem.Get(MM_MODEM, 'State', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n    except Exception:\n      return None\n\n    if info and info.startswith('+QNWINFO: '):\n      info = info.replace('+QNWINFO: ', '').replace('\"', '').split(',')\n      extra = \"\" if extra is None else extra.replace('+QENG: \"servingcell\",', '').replace('\"', '')\n      state = \"\" if state is None else MM_MODEM_STATE(state).name\n\n      if len(info) != 4:\n        return None\n\n      technology, operator, band, channel = info\n\n      return({\n        'technology': technology,\n        'operator': operator,\n        'band': band,\n        'channel': int(channel),\n        'extra': extra,\n        'state': state,\n      })\n    else:\n      return None\n\n  def parse_strength(self, percentage):\n      if percentage < 25:\n        return NetworkStrength.poor\n      elif percentage < 50:\n        return NetworkStrength.moderate\n      elif percentage < 75:\n        return NetworkStrength.good\n      else:\n        return NetworkStrength.great\n\n  def get_network_strength(self, network_type):\n    network_strength = NetworkStrength.unknown\n\n    try:\n      if network_type == NetworkType.none:\n        pass\n      elif network_type == NetworkType.wifi:\n        wlan = self.get_wlan()\n        active_ap_path = wlan.Get(NM_DEV_WL, 'ActiveAccessPoint', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n        if active_ap_path != \"/\":\n          active_ap = self.bus.get_object(NM, active_ap_path)\n          strength = int(active_ap.Get(NM_AP, 'Strength', dbus_interface=DBUS_PROPS, timeout=TIMEOUT))\n          network_strength = self.parse_strength(strength)\n      else:  # Cellular\n        modem = self.get_modem()\n        strength = int(modem.Get(MM_MODEM, 'SignalQuality', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)[0])\n        network_strength = self.parse_strength(strength)\n    except Exception:\n      pass\n\n    return network_strength\n\n  def get_modem_version(self):\n    try:\n      modem = self.get_modem()\n      return modem.Get(MM_MODEM, 'Revision', dbus_interface=DBUS_PROPS, timeout=TIMEOUT)\n    except Exception:\n      return None\n\n  # We don't have a battery, so let's use some sane constants\n  def get_battery_capacity(self):\n    return 100\n\n  def get_battery_status(self):\n    return \"\"\n\n  def get_battery_current(self):\n    return 0\n\n  def get_battery_voltage(self):\n    return 0\n\n  def get_battery_charging(self):\n    return True\n\n  def set_battery_charging(self, on):\n    pass\n\n  def get_usb_present(self):\n    # Not sure if relevant on tici, but the file exists\n    return self.read_param_file(\"/sys/class/power_supply/usb/present\", lambda x: bool(int(x)), False)\n\n  def get_current_power_draw(self):\n    return (self.read_param_file(\"/sys/class/hwmon/hwmon1/power1_input\", int) / 1e6)\n\n  def shutdown(self):\n    # Note that for this to work and have the device stay powered off, the panda needs to be in UsbPowerMode::CLIENT!\n    os.system(\"sudo poweroff\")\n\n  def get_thermal_config(self):\n    return ThermalConfig(cpu=((1, 2, 3, 4, 5, 6, 7, 8), 1000), gpu=((48,49), 1000), mem=(15, 1000), bat=(None, 1), ambient=(65, 1000))\n\n  def set_screen_brightness(self, percentage):\n    try:\n      with open(\"/sys/class/backlight/panel0-backlight/brightness\", \"w\") as f:\n        f.write(str(int(percentage * 10.23)))\n    except Exception:\n      pass\n\n  def set_power_save(self, powersave_enabled):\n    # amplifier, 100mW at idle\n    self.amplifier.set_global_shutdown(amp_disabled=powersave_enabled)\n    if not powersave_enabled:\n      self.amplifier.initialize_configuration()\n\n    # offline big cluster, leave core 4 online for boardd\n    for i in range(5, 8):\n      # TODO: fix permissions with udev\n      val = \"0\" if powersave_enabled else \"1\"\n      os.system(f\"sudo su -c 'echo {val} > /sys/devices/system/cpu/cpu{i}/online'\")\n\n  def get_gpu_usage_percent(self):\n    try:\n      used, total = open('/sys/class/kgsl/kgsl-3d0/gpubusy').read().strip().split()\n      return 100.0 * int(used) / int(total)\n    except Exception:\n      return 0\n\n  def initialize_hardware(self):\n    self.amplifier.initialize_configuration()\n\n  def get_networks(self):\n    r = {}\n\n    wlan = iwlist.scan()\n    if wlan is not None:\n      r['wlan'] = wlan\n\n    lte_info = self.get_network_info()\n    if lte_info is not None:\n      extra = lte_info['extra']\n\n      # <state>,\"LTE\",<is_tdd>,<mcc>,<mnc>,<cellid>,<pcid>,<earfcn>,<freq_band_ind>,\n      # <ul_bandwidth>,<dl_bandwidth>,<tac>,<rsrp>,<rsrq>,<rssi>,<sinr>,<srxlev>\n      if 'LTE' in extra:\n        extra = extra.split(',')\n        try:\n          r['lte'] = [{\n            \"mcc\": int(extra[3]),\n            \"mnc\": int(extra[4]),\n            \"cid\": int(extra[5], 16),\n            \"nmr\": [{\"pci\": int(extra[6]), \"earfcn\": int(extra[7])}],\n          }]\n        except (ValueError, IndexError):\n          pass\n\n    return r"
  },
  {
    "path": "selfdrive/hardware/tici/iwlist.py",
    "content": "import subprocess\n\n\ndef scan(interface=\"wlan0\"):\n  result = []\n  try:\n    r = subprocess.check_output([\"iwlist\", interface, \"scan\"], encoding='utf8')\n\n    mac = None\n    for line in r.split('\\n'):\n      if \"Address\" in line:\n        # Based on the adapter eithere a percentage or dBm is returned\n        # Add previous network in case no dBm signal level was seen\n        if mac is not None:\n          result.append({\"mac\": mac})\n          mac = None\n\n        mac = line.split(' ')[-1]\n      elif \"dBm\" in line:\n        try:\n          level = line.split('Signal level=')[1]\n          rss = int(level.split(' ')[0])\n          result.append({\"mac\": mac, \"rss\": rss})\n          mac = None\n        except ValueError:\n          continue\n\n    # Add last network if no dBm was found\n    if mac is not None:\n      result.append({\"mac\": mac})\n\n    return result\n\n  except Exception:\n    return None\n"
  },
  {
    "path": "selfdrive/hardware/tici/pins.py",
    "content": "# TODO: these are also defined in a header\n# GPIO pin definitions\nGPIO_HUB_RST_N = 30\nGPIO_UBLOX_RST_N = 32\nGPIO_UBLOX_SAFEBOOT_N = 33\nGPIO_UBLOX_PWR_EN = 34\nGPIO_STM_RST_N = 124\nGPIO_STM_BOOT0 = 134\n"
  },
  {
    "path": "selfdrive/logcatd/SConscript",
    "content": "Import('env', 'cereal', 'messaging', 'common', 'arch')\n\nif arch == \"aarch64\":\n  env.Program('logcatd', 'logcatd_android.cc', LIBS=[cereal, messaging, common, 'cutils', 'zmq', 'capnp', 'kj'])\nelse:\n  env.Program('logcatd', 'logcatd_systemd.cc', LIBS=[cereal, messaging, common, 'zmq', 'capnp', 'kj', 'systemd', 'json11'])\n"
  },
  {
    "path": "selfdrive/logcatd/logcatd_android.cc",
    "content": "#include <sys/time.h>\n#include <sys/resource.h>\n\n#include <android/log.h>\n#include <log/logger.h>\n#include <log/logprint.h>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/util.h\"\n\nint main() {\n  setpriority(PRIO_PROCESS, 0, -15);\n\n  ExitHandler do_exit;\n  PubMaster pm({\"androidLog\"});\n\n  log_time last_log_time = {};\n  logger_list *logger_list = android_logger_list_alloc(ANDROID_LOG_RDONLY | ANDROID_LOG_NONBLOCK, 0, 0);\n\n  while (!do_exit) {\n    // setup android logging\n    if (!logger_list) {\n      logger_list = android_logger_list_alloc_time(ANDROID_LOG_RDONLY | ANDROID_LOG_NONBLOCK, last_log_time, 0);\n    }\n    assert(logger_list);\n\n    struct logger *main_logger = android_logger_open(logger_list, LOG_ID_MAIN);\n    assert(main_logger);\n    struct logger *radio_logger = android_logger_open(logger_list, LOG_ID_RADIO);\n    assert(radio_logger);\n    struct logger *system_logger = android_logger_open(logger_list, LOG_ID_SYSTEM);\n    assert(system_logger);\n    struct logger *crash_logger = android_logger_open(logger_list, LOG_ID_CRASH);\n    assert(crash_logger);\n    struct logger *kernel_logger = android_logger_open(logger_list, (log_id_t)5); // LOG_ID_KERNEL\n    assert(kernel_logger);\n\n    while (!do_exit) {\n      log_msg log_msg;\n      int err = android_logger_list_read(logger_list, &log_msg);\n      if (err <= 0) break;\n\n      AndroidLogEntry entry;\n      err = android_log_processLogBuffer(&log_msg.entry_v1, &entry);\n      if (err < 0) continue;\n      last_log_time.tv_sec = entry.tv_sec;\n      last_log_time.tv_nsec = entry.tv_nsec;\n\n      MessageBuilder msg;\n      auto androidEntry = msg.initEvent().initAndroidLog();\n      androidEntry.setId(log_msg.id());\n      androidEntry.setTs(entry.tv_sec * 1000000000ULL + entry.tv_nsec);\n      androidEntry.setPriority(entry.priority);\n      androidEntry.setPid(entry.pid);\n      androidEntry.setTid(entry.tid);\n      androidEntry.setTag(entry.tag);\n      androidEntry.setMessage(entry.message);\n\n      pm.send(\"androidLog\", msg);\n    }\n\n    android_logger_list_free(logger_list);\n    logger_list = NULL;\n    util::sleep_for(500);\n  }\n\n  if (logger_list) {\n    android_logger_list_free(logger_list);\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/logcatd/logcatd_systemd.cc",
    "content": "#include <systemd/sd-journal.h>\n\n#include <cassert>\n#include <csignal>\n#include <map>\n#include <string>\n\n#include \"json11.hpp\"\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n\nExitHandler do_exit;\nint main(int argc, char *argv[]) {\n\n  PubMaster pm({\"androidLog\"});\n\n  sd_journal *journal;\n  int err = sd_journal_open(&journal, 0);\n  assert(err >= 0);\n  err = sd_journal_get_fd(journal); // needed so sd_journal_wait() works properly if files rotate\n  assert(err >= 0);\n  err = sd_journal_seek_tail(journal);\n  assert(err >= 0);\n\n  while (!do_exit) {\n    err = sd_journal_next(journal);\n    assert(err >= 0);\n\n    // Wait for new message if we didn't receive anything\n    if (err == 0) {\n      err = sd_journal_wait(journal, 1000 * 1000);\n      assert (err >= 0);\n      continue; // Try again\n    }\n\n    uint64_t timestamp = 0;\n    err = sd_journal_get_realtime_usec(journal, &timestamp);\n    assert(err >= 0);\n\n    const void *data;\n    size_t length;\n    std::map<std::string, std::string> kv;\n\n    SD_JOURNAL_FOREACH_DATA(journal, data, length) {\n      std::string str((char*)data, length);\n\n      // Split \"KEY=VALUE\"\" on \"=\" and put in map\n      std::size_t found = str.find(\"=\");\n      if (found != std::string::npos) {\n        kv[str.substr(0, found)] = str.substr(found + 1, std::string::npos);\n      }\n    }\n\n    MessageBuilder msg;\n\n    // Build message\n    auto androidEntry = msg.initEvent().initAndroidLog();\n    androidEntry.setTs(timestamp);\n    androidEntry.setMessage(json11::Json(kv).dump());\n    if (kv.count(\"_PID\")) androidEntry.setPid(std::atoi(kv[\"_PID\"].c_str()));\n    if (kv.count(\"PRIORITY\")) androidEntry.setPriority(std::atoi(kv[\"PRIORITY\"].c_str()));\n    if (kv.count(\"SYSLOG_IDENTIFIER\")) androidEntry.setTag(kv[\"SYSLOG_IDENTIFIER\"]);\n\n    pm.send(\"androidLog\", msg);\n  }\n\n  sd_journal_close(journal);\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/loggerd/SConscript",
    "content": "Import('env', 'arch', 'cereal', 'messaging', 'common', 'visionipc', 'gpucommon')\n\n\nlogger_lib = env.Library('logger', [\"logger.cc\"])\nlibs = [logger_lib, common, cereal, messaging, visionipc,\n        'zmq', 'capnp', 'kj', 'z',\n        'avformat', 'avcodec', 'swscale', 'avutil',\n        'yuv', 'bz2', 'OpenCL']\n\nsrc = ['loggerd.cc']\nif arch in [\"aarch64\", \"larch64\"]:\n  src += ['omx_encoder.cc']\n  libs += ['OmxCore', 'gsl', 'CB'] + gpucommon\n  if arch == \"aarch64\":\n    libs += ['OmxVenc', 'cutils']\n  else:\n    libs += ['pthread']\nelse:\n  src += ['raw_logger.cc']\n  libs += ['pthread']\n\nif arch == \"Darwin\":\n  # fix OpenCL\n  del libs[libs.index('OpenCL')]\n  env['FRAMEWORKS'] = ['OpenCL']\n\nenv.Program(src, LIBS=libs)\nenv.Program('bootlog.cc', LIBS=libs)\n\nif GetOption('test'):\n  env.Program('tests/test_logger', ['tests/test_runner.cc', 'tests/test_logger.cc'], LIBS=[libs])\n"
  },
  {
    "path": "selfdrive/loggerd/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/loggerd/bootlog.cc",
    "content": "#include <cassert>\n#include <string>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/loggerd/logger.h\"\n\nstatic kj::Array<capnp::word> build_boot_log() {\n  MessageBuilder msg;\n  auto boot = msg.initEvent().initBoot();\n\n  boot.setWallTimeNanos(nanos_since_epoch());\n\n  std::string pstore = \"/sys/fs/pstore\";\n  std::map<std::string, std::string> pstore_map = util::read_files_in_dir(pstore);\n\n  const std::vector<std::string> log_keywords = {\"Kernel panic\"};\n  auto lpstore = boot.initPstore().initEntries(pstore_map.size());\n  int i = 0;\n  for (auto& kv : pstore_map) {\n    auto lentry = lpstore[i];\n    lentry.setKey(kv.first);\n    lentry.setValue(capnp::Data::Reader((const kj::byte*)kv.second.data(), kv.second.size()));\n    i++;\n\n    for (auto &k : log_keywords) {\n      if (kv.second.find(k) != std::string::npos) {\n        LOGE(\"%s: found '%s'\", kv.first.c_str(), k.c_str());\n      }\n    }\n  }\n\n  boot.setLaunchLog(util::read_file(\"/tmp/launch_log\"));\n  return capnp::messageToFlatArray(msg);\n}\n\nint main(int argc, char** argv) {\n\n  const std::string path = LOG_ROOT + \"/boot/\" + logger_get_route_name() + \".bz2\";\n  LOGW(\"bootlog to %s\", path.c_str());\n\n  // Open bootlog\n  int r = logger_mkpath((char*)path.c_str());\n  assert(r == 0);\n\n  BZFile bz_file(path.c_str());\n\n  // Write initdata\n  bz_file.write(logger_build_init_data().asBytes());\n\n  // Write bootlog\n  bz_file.write(build_boot_log().asBytes());\n\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/loggerd/config.py",
    "content": "import os\nfrom pathlib import Path\nfrom selfdrive.hardware import PC\nfrom common.params import Params\n\nif os.environ.get('LOG_ROOT', False):\n  ROOT = os.environ['LOG_ROOT']\nelif PC:\n  ROOT = os.path.join(str(Path.home()), \".comma\", \"media\", \"0\", \"realdata\")\nelse:\n  if Params().get_bool('dp_atl') or Params().get('dp_jetson'):\n    ROOT = '/data/media/0/fakedata/'\n  else:\n    ROOT = '/data/media/0/realdata/'\n\n\nCAMERA_FPS = 20\nSEGMENT_LENGTH = 60\n\n\ndef get_available_percent(default=None):\n  try:\n    statvfs = os.statvfs(ROOT)\n    available_percent = 100.0 * statvfs.f_bavail / statvfs.f_blocks\n  except OSError:\n    available_percent = default\n\n  return available_percent\n\n\ndef get_available_bytes(default=None):\n  try:\n    statvfs = os.statvfs(ROOT)\n    available_bytes = statvfs.f_bavail * statvfs.f_frsize\n  except OSError:\n    available_bytes = default\n\n  return available_bytes\n"
  },
  {
    "path": "selfdrive/loggerd/deleter.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport shutil\nimport threading\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.loggerd.config import ROOT, get_available_bytes, get_available_percent\nfrom selfdrive.loggerd.uploader import listdir_by_creation\n\nMIN_BYTES = 5 * 1024 * 1024 * 1024\nMIN_PERCENT = 10\n\nDELETE_LAST = ['boot', 'crash']\n\n\ndef deleter_thread(exit_event):\n  while not exit_event.is_set():\n    out_of_bytes = get_available_bytes(default=MIN_BYTES + 1) < MIN_BYTES\n    out_of_percent = get_available_percent(default=MIN_PERCENT + 1) < MIN_PERCENT\n\n    if out_of_percent or out_of_bytes:\n      # remove the earliest directory we can\n      dirs = sorted(listdir_by_creation(ROOT), key=lambda x: x in DELETE_LAST)\n      for delete_dir in dirs:\n        delete_path = os.path.join(ROOT, delete_dir)\n\n        if any(name.endswith(\".lock\") for name in os.listdir(delete_path)):\n          continue\n\n        try:\n          cloudlog.info(\"deleting %s\" % delete_path)\n          shutil.rmtree(delete_path)\n          break\n        except OSError:\n          cloudlog.exception(\"issue deleting %s\" % delete_path)\n      exit_event.wait(.1)\n    else:\n      exit_event.wait(30)\n\n\ndef main():\n  deleter_thread(threading.Event())\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/loggerd/encoder.h",
    "content": "#pragma once\n\n#include <cstdint>\n\nclass VideoEncoder {\npublic:\n  virtual ~VideoEncoder() {}\n  virtual int encode_frame(const uint8_t *y_ptr, const uint8_t *u_ptr, const uint8_t *v_ptr,\n                           int in_width, int in_height, uint64_t ts) = 0;\n  virtual void encoder_open(const char* path) = 0;\n  virtual void encoder_close() = 0;\n};\n"
  },
  {
    "path": "selfdrive/loggerd/include/msm_media_info.h",
    "content": "#ifndef __MEDIA_INFO_H__\n#define __MEDIA_INFO_H__\n\n#ifndef MSM_MEDIA_ALIGN\n#define MSM_MEDIA_ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1)))\n#endif\n\n#ifndef MSM_MEDIA_ROUNDUP\n#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r))\n#endif\n\n#ifndef MSM_MEDIA_MAX\n#define MSM_MEDIA_MAX(__a, __b) ((__a) > (__b)?(__a):(__b))\n#endif\n\nenum color_fmts {\n\t/* Venus NV12:\n\t * YUV 4:2:0 image with a plane of 8 bit Y samples followed\n\t * by an interleaved U/V plane containing 8 bit 2x2 subsampled\n\t * colour difference samples.\n\t *\n\t * <-------- Y/UV_Stride -------->\n\t * <------- Width ------->\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  ^           ^\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  Height      |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |          Y_Scanlines\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  V           |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              V\n\t * U V U V U V U V U V U V . . . .  ^\n\t * U V U V U V U V U V U V . . . .  |\n\t * U V U V U V U V U V U V . . . .  |\n\t * U V U V U V U V U V U V . . . .  UV_Scanlines\n\t * . . . . . . . . . . . . . . . .  |\n\t * . . . . . . . . . . . . . . . .  V\n\t * . . . . . . . . . . . . . . . .  --> Buffer size alignment\n\t *\n\t * Y_Stride : Width aligned to 128\n\t * UV_Stride : Width aligned to 128\n\t * Y_Scanlines: Height aligned to 32\n\t * UV_Scanlines: Height/2 aligned to 16\n\t * Extradata: Arbitrary (software-imposed) padding\n\t * Total size = align((Y_Stride * Y_Scanlines\n\t *          + UV_Stride * UV_Scanlines\n\t *          + max(Extradata, Y_Stride * 8), 4096)\n\t */\n\tCOLOR_FMT_NV12,\n\n\t/* Venus NV21:\n\t * YUV 4:2:0 image with a plane of 8 bit Y samples followed\n\t * by an interleaved V/U plane containing 8 bit 2x2 subsampled\n\t * colour difference samples.\n\t *\n\t * <-------- Y/UV_Stride -------->\n\t * <------- Width ------->\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  ^           ^\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  Height      |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |          Y_Scanlines\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  V           |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              V\n\t * V U V U V U V U V U V U . . . .  ^\n\t * V U V U V U V U V U V U . . . .  |\n\t * V U V U V U V U V U V U . . . .  |\n\t * V U V U V U V U V U V U . . . .  UV_Scanlines\n\t * . . . . . . . . . . . . . . . .  |\n\t * . . . . . . . . . . . . . . . .  V\n\t * . . . . . . . . . . . . . . . .  --> Padding & Buffer size alignment\n\t *\n\t * Y_Stride : Width aligned to 128\n\t * UV_Stride : Width aligned to 128\n\t * Y_Scanlines: Height aligned to 32\n\t * UV_Scanlines: Height/2 aligned to 16\n\t * Extradata: Arbitrary (software-imposed) padding\n\t * Total size = align((Y_Stride * Y_Scanlines\n\t *          + UV_Stride * UV_Scanlines\n\t *          + max(Extradata, Y_Stride * 8), 4096)\n\t */\n\tCOLOR_FMT_NV21,\n\t/* Venus NV12_MVTB:\n\t * Two YUV 4:2:0 images/views one after the other\n\t * in a top-bottom layout, same as NV12\n\t * with a plane of 8 bit Y samples followed\n\t * by an interleaved U/V plane containing 8 bit 2x2 subsampled\n\t * colour difference samples.\n\t *\n\t *\n\t * <-------- Y/UV_Stride -------->\n\t * <------- Width ------->\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  ^           ^               ^\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  Height      |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |          Y_Scanlines      |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  V           |               |\n\t * . . . . . . . . . . . . . . . .              |             View_1\n\t * . . . . . . . . . . . . . . . .              |               |\n\t * . . . . . . . . . . . . . . . .              |               |\n\t * . . . . . . . . . . . . . . . .              V               |\n\t * U V U V U V U V U V U V . . . .  ^                           |\n\t * U V U V U V U V U V U V . . . .  |                           |\n\t * U V U V U V U V U V U V . . . .  |                           |\n\t * U V U V U V U V U V U V . . . .  UV_Scanlines                |\n\t * . . . . . . . . . . . . . . . .  |                           |\n\t * . . . . . . . . . . . . . . . .  V                           V\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  ^           ^               ^\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  Height      |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |          Y_Scanlines      |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |               |\n\t * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  V           |               |\n\t * . . . . . . . . . . . . . . . .              |             View_2\n\t * . . . . . . . . . . . . . . . .              |               |\n\t * . . . . . . . . . . . . . . . .              |               |\n\t * . . . . . . . . . . . . . . . .              V               |\n\t * U V U V U V U V U V U V . . . .  ^                           |\n\t * U V U V U V U V U V U V . . . .  |                           |\n\t * U V U V U V U V U V U V . . . .  |                           |\n\t * U V U V U V U V U V U V . . . .  UV_Scanlines                |\n\t * . . . . . . . . . . . . . . . .  |                           |\n\t * . . . . . . . . . . . . . . . .  V                           V\n\t * . . . . . . . . . . . . . . . .  --> Buffer size alignment\n\t *\n\t * Y_Stride : Width aligned to 128\n\t * UV_Stride : Width aligned to 128\n\t * Y_Scanlines: Height aligned to 32\n\t * UV_Scanlines: Height/2 aligned to 16\n\t * View_1 begin at: 0 (zero)\n\t * View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines\n\t * Extradata: Arbitrary (software-imposed) padding\n\t * Total size = align((2*(Y_Stride * Y_Scanlines)\n\t *          + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096)\n\t */\n\tCOLOR_FMT_NV12_MVTB,\n\t/* Venus NV12 UBWC:\n\t * Compressed Macro-tile format for NV12.\n\t * Contains 4 planes in the following order -\n\t * (A) Y_Meta_Plane\n\t * (B) Y_UBWC_Plane\n\t * (C) UV_Meta_Plane\n\t * (D) UV_UBWC_Plane\n\t *\n\t * Y_Meta_Plane consists of meta information to decode compressed\n\t * tile data in Y_UBWC_Plane.\n\t * Y_UBWC_Plane consists of Y data in compressed macro-tile format.\n\t * UBWC decoder block will use the Y_Meta_Plane data together with\n\t * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples.\n\t *\n\t * UV_Meta_Plane consists of meta information to decode compressed\n\t * tile data in UV_UBWC_Plane.\n\t * UV_UBWC_Plane consists of UV data in compressed macro-tile format.\n\t * UBWC decoder block will use UV_Meta_Plane data together with\n\t * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2\n\t * subsampled color difference samples.\n\t *\n\t * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable\n\t * and randomly accessible. There is no dependency between tiles.\n\t *\n\t * <----- Y_Meta_Stride ---->\n\t * <-------- Width ------>\n\t * M M M M M M M M M M M M . .      ^           ^\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      Height      |\n\t * M M M M M M M M M M M M . .      |         Meta_Y_Scanlines\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      V           |\n\t * . . . . . . . . . . . . . .                  |\n\t * . . . . . . . . . . . . . .                  |\n\t * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k\n\t * . . . . . . . . . . . . . .                  V\n\t * <--Compressed tile Y Stride--->\n\t * <------- Width ------->\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  ^           ^\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  Height      |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |        Macro_tile_Y_Scanlines\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  V           |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .  -------> Buffer size aligned to 4k\n\t * . . . . . . . . . . . . . . . .              V\n\t * <----- UV_Meta_Stride ---->\n\t * M M M M M M M M M M M M . .      ^\n\t * M M M M M M M M M M M M . .      |\n\t * M M M M M M M M M M M M . .      |\n\t * M M M M M M M M M M M M . .      M_UV_Scanlines\n\t * . . . . . . . . . . . . . .      |\n\t * . . . . . . . . . . . . . .      V\n\t * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k\n\t * <--Compressed tile UV Stride--->\n\t * U* V* U* V* U* V* U* V* . . . .  ^\n\t * U* V* U* V* U* V* U* V* . . . .  |\n\t * U* V* U* V* U* V* U* V* . . . .  |\n\t * U* V* U* V* U* V* U* V* . . . .  UV_Scanlines\n\t * . . . . . . . . . . . . . . . .  |\n\t * . . . . . . . . . . . . . . . .  V\n\t * . . . . . . . . . . . . . . . .  -------> Buffer size aligned to 4k\n\t *\n\t * Y_Stride = align(Width, 128)\n\t * UV_Stride = align(Width, 128)\n\t * Y_Scanlines = align(Height, 32)\n\t * UV_Scanlines = align(Height/2, 16)\n\t * Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096)\n\t * UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096)\n\t * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)\n\t * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)\n\t * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)\n\t * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)\n\t * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)\n\t * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)\n\t * Extradata = 8k\n\t *\n\t * Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size +\n\t *           Y_Meta_Plane_size + UV_Meta_Plane_size\n\t *           + max(Extradata, Y_Stride * 48), 4096)\n\t */\n\tCOLOR_FMT_NV12_UBWC,\n\t/* Venus NV12 10-bit UBWC:\n\t * Compressed Macro-tile format for NV12.\n\t * Contains 4 planes in the following order -\n\t * (A) Y_Meta_Plane\n\t * (B) Y_UBWC_Plane\n\t * (C) UV_Meta_Plane\n\t * (D) UV_UBWC_Plane\n\t *\n\t * Y_Meta_Plane consists of meta information to decode compressed\n\t * tile data in Y_UBWC_Plane.\n\t * Y_UBWC_Plane consists of Y data in compressed macro-tile format.\n\t * UBWC decoder block will use the Y_Meta_Plane data together with\n\t * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples.\n\t *\n\t * UV_Meta_Plane consists of meta information to decode compressed\n\t * tile data in UV_UBWC_Plane.\n\t * UV_UBWC_Plane consists of UV data in compressed macro-tile format.\n\t * UBWC decoder block will use UV_Meta_Plane data together with\n\t * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2\n\t * subsampled color difference samples.\n\t *\n\t * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable\n\t * and randomly accessible. There is no dependency between tiles.\n\t *\n\t * <----- Y_Meta_Stride ----->\n\t * <-------- Width ------>\n\t * M M M M M M M M M M M M . .      ^           ^\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      Height      |\n\t * M M M M M M M M M M M M . .      |         Meta_Y_Scanlines\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      V           |\n\t * . . . . . . . . . . . . . .                  |\n\t * . . . . . . . . . . . . . .                  |\n\t * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k\n\t * . . . . . . . . . . . . . .                  V\n\t * <--Compressed tile Y Stride--->\n\t * <------- Width ------->\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  ^           ^\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  Height      |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |        Macro_tile_Y_Scanlines\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |\n\t * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  V           |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .  -------> Buffer size aligned to 4k\n\t * . . . . . . . . . . . . . . . .              V\n\t * <----- UV_Meta_Stride ---->\n\t * M M M M M M M M M M M M . .      ^\n\t * M M M M M M M M M M M M . .      |\n\t * M M M M M M M M M M M M . .      |\n\t * M M M M M M M M M M M M . .      M_UV_Scanlines\n\t * . . . . . . . . . . . . . .      |\n\t * . . . . . . . . . . . . . .      V\n\t * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k\n\t * <--Compressed tile UV Stride--->\n\t * U* V* U* V* U* V* U* V* . . . .  ^\n\t * U* V* U* V* U* V* U* V* . . . .  |\n\t * U* V* U* V* U* V* U* V* . . . .  |\n\t * U* V* U* V* U* V* U* V* . . . .  UV_Scanlines\n\t * . . . . . . . . . . . . . . . .  |\n\t * . . . . . . . . . . . . . . . .  V\n\t * . . . . . . . . . . . . . . . .  -------> Buffer size aligned to 4k\n\t *\n\t *\n\t * Y_Stride = align(Width * 4/3, 128)\n\t * UV_Stride = align(Width * 4/3, 128)\n\t * Y_Scanlines = align(Height, 32)\n\t * UV_Scanlines = align(Height/2, 16)\n\t * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096)\n\t * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096)\n\t * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)\n\t * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)\n\t * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)\n\t * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)\n\t * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)\n\t * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)\n\t * Extradata = 8k\n\t *\n\t * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size +\n\t *           Y_Meta_Plane_size + UV_Meta_Plane_size\n\t *           + max(Extradata, Y_Stride * 48), 4096)\n\t */\n\tCOLOR_FMT_NV12_BPP10_UBWC,\n\t/* Venus RGBA8888 format:\n\t * Contains 1 plane in the following order -\n\t * (A) RGBA plane\n\t *\n\t * <-------- RGB_Stride -------->\n\t * <------- Width ------->\n\t * R R R R R R R R R R R R . . . .  ^           ^\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  Height      |\n\t * R R R R R R R R R R R R . . . .  |       RGB_Scanlines\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  V           |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              V\n\t *\n\t * RGB_Stride = align(Width * 4, 128)\n\t * RGB_Scanlines = align(Height, 32)\n\t * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)\n\t * Extradata = 8k\n\t *\n\t * Total size = align(RGB_Plane_size + Extradata, 4096)\n\t */\n\tCOLOR_FMT_RGBA8888,\n\t/* Venus RGBA8888 UBWC format:\n\t * Contains 2 planes in the following order -\n\t * (A) Meta plane\n\t * (B) RGBA plane\n\t *\n\t * <--- RGB_Meta_Stride ---->\n\t * <-------- Width ------>\n\t * M M M M M M M M M M M M . .      ^           ^\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      Height      |\n\t * M M M M M M M M M M M M . .      |       Meta_RGB_Scanlines\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      |           |\n\t * M M M M M M M M M M M M . .      V           |\n\t * . . . . . . . . . . . . . .                  |\n\t * . . . . . . . . . . . . . .                  |\n\t * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k\n\t * . . . . . . . . . . . . . .                  V\n\t * <-------- RGB_Stride -------->\n\t * <------- Width ------->\n\t * R R R R R R R R R R R R . . . .  ^           ^\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  Height      |\n\t * R R R R R R R R R R R R . . . .  |       RGB_Scanlines\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  |           |\n\t * R R R R R R R R R R R R . . . .  V           |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .              |\n\t * . . . . . . . . . . . . . . . .    -------> Buffer size aligned to 4k\n\t * . . . . . . . . . . . . . . . .              V\n\t *\n\t * RGB_Stride = align(Width * 4, 128)\n\t * RGB_Scanlines = align(Height, 32)\n\t * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)\n\t * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64)\n\t * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16)\n\t * RGB_Meta_Plane_size = align(RGB_Meta_Stride *\n\t *\t\tRGB_Meta_Scanlines, 4096)\n\t * Extradata = 8k\n\t *\n\t * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size +\n\t *\t\tExtradata, 4096)\n\t */\n\tCOLOR_FMT_RGBA8888_UBWC,\n};\n\nstatic inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height)\n{\n\t(void)height;\n\t(void)width;\n\n\t/*\n\t * In the future, calculate the size based on the w/h but just\n\t * hardcode it for now since 16K satisfies all current usecases.\n\t */\n\treturn 16 * 1024;\n}\n\nstatic inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width)\n{\n\tunsigned int alignment, stride = 0;\n\tif (!width)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV21:\n\tcase COLOR_FMT_NV12:\n\tcase COLOR_FMT_NV12_MVTB:\n\tcase COLOR_FMT_NV12_UBWC:\n\t\talignment = 128;\n\t\tstride = MSM_MEDIA_ALIGN(width, alignment);\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\talignment = 256;\n\t\tstride = MSM_MEDIA_ALIGN(width, 192);\n\t\tstride = MSM_MEDIA_ALIGN(stride * 4/3, alignment);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ninvalid_input:\n\treturn stride;\n}\n\nstatic inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width)\n{\n\tunsigned int alignment, stride = 0;\n\tif (!width)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV21:\n\tcase COLOR_FMT_NV12:\n\tcase COLOR_FMT_NV12_MVTB:\n\tcase COLOR_FMT_NV12_UBWC:\n\t\talignment = 128;\n\t\tstride = MSM_MEDIA_ALIGN(width, alignment);\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\talignment = 256;\n\t\tstride = MSM_MEDIA_ALIGN(width, 192);\n\t\tstride = MSM_MEDIA_ALIGN(stride * 4/3, alignment);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ninvalid_input:\n\treturn stride;\n}\n\nstatic inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height)\n{\n\tunsigned int alignment, sclines = 0;\n\tif (!height)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV21:\n\tcase COLOR_FMT_NV12:\n\tcase COLOR_FMT_NV12_MVTB:\n\tcase COLOR_FMT_NV12_UBWC:\n\t\talignment = 32;\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\talignment = 16;\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\tsclines = MSM_MEDIA_ALIGN(height, alignment);\ninvalid_input:\n\treturn sclines;\n}\n\nstatic inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height)\n{\n\tunsigned int alignment, sclines = 0;\n\tif (!height)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV21:\n\tcase COLOR_FMT_NV12:\n\tcase COLOR_FMT_NV12_MVTB:\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\talignment = 16;\n\t\tbreak;\n\tcase COLOR_FMT_NV12_UBWC:\n\t\talignment = 32;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\tsclines = MSM_MEDIA_ALIGN(height / 2, alignment);\n\ninvalid_input:\n\treturn sclines;\n}\n\nstatic inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width)\n{\n\tint y_tile_width = 0, y_meta_stride = 0;\n\n\tif (!width)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV12_UBWC:\n\t\ty_tile_width = 32;\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\ty_tile_width = 48;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\ty_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width);\n\ty_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64);\n\ninvalid_input:\n\treturn y_meta_stride;\n}\n\nstatic inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height)\n{\n\tint y_tile_height = 0, y_meta_scanlines = 0;\n\n\tif (!height)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV12_UBWC:\n\t\ty_tile_height = 8;\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\ty_tile_height = 4;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\ty_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height);\n\ty_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16);\n\ninvalid_input:\n\treturn y_meta_scanlines;\n}\n\nstatic inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width)\n{\n\tint uv_tile_width = 0, uv_meta_stride = 0;\n\n\tif (!width)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV12_UBWC:\n\t\tuv_tile_width = 16;\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\tuv_tile_width = 24;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\tuv_meta_stride = MSM_MEDIA_ROUNDUP(width / 2, uv_tile_width);\n\tuv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64);\n\ninvalid_input:\n\treturn uv_meta_stride;\n}\n\nstatic inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height)\n{\n\tint uv_tile_height = 0, uv_meta_scanlines = 0;\n\n\tif (!height)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV12_UBWC:\n\t\tuv_tile_height = 8;\n\t\tbreak;\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\tuv_tile_height = 4;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\tuv_meta_scanlines = MSM_MEDIA_ROUNDUP(height / 2, uv_tile_height);\n\tuv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16);\n\ninvalid_input:\n\treturn uv_meta_scanlines;\n}\n\nstatic inline unsigned int VENUS_RGB_STRIDE(int color_fmt, int width)\n{\n\tunsigned int alignment = 0, stride = 0;\n\tif (!width)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_RGBA8888:\n\t\talignment = 128;\n\t\tbreak;\n\tcase COLOR_FMT_RGBA8888_UBWC:\n\t\talignment = 256;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\tstride = MSM_MEDIA_ALIGN(width * 4, alignment);\n\ninvalid_input:\n\treturn stride;\n}\n\nstatic inline unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height)\n{\n\tunsigned int alignment = 0, scanlines = 0;\n\n\tif (!height)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_RGBA8888:\n\t\talignment = 32;\n\t\tbreak;\n\tcase COLOR_FMT_RGBA8888_UBWC:\n\t\talignment = 16;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\tscanlines = MSM_MEDIA_ALIGN(height, alignment);\n\ninvalid_input:\n\treturn scanlines;\n}\n\nstatic inline unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width)\n{\n\tint rgb_tile_width = 0, rgb_meta_stride = 0;\n\n\tif (!width)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_RGBA8888_UBWC:\n\t\trgb_tile_width = 16;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\trgb_meta_stride = MSM_MEDIA_ROUNDUP(width, rgb_tile_width);\n\trgb_meta_stride = MSM_MEDIA_ALIGN(rgb_meta_stride, 64);\n\ninvalid_input:\n\treturn rgb_meta_stride;\n}\n\nstatic inline unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height)\n{\n\tint rgb_tile_height = 0, rgb_meta_scanlines = 0;\n\n\tif (!height)\n\t\tgoto invalid_input;\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_RGBA8888_UBWC:\n\t\trgb_tile_height = 4;\n\t\tbreak;\n\tdefault:\n\t\tgoto invalid_input;\n\t}\n\n\trgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, rgb_tile_height);\n\trgb_meta_scanlines = MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16);\n\ninvalid_input:\n\treturn rgb_meta_scanlines;\n}\n\nstatic inline unsigned int VENUS_BUFFER_SIZE(\n\tint color_fmt, int width, int height)\n{\n\tconst unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height);\n\tunsigned int uv_alignment = 0, size = 0;\n\tunsigned int y_plane, uv_plane, y_stride,\n\t\tuv_stride, y_sclines, uv_sclines;\n\tunsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0;\n\tunsigned int y_meta_stride = 0, y_meta_scanlines = 0;\n\tunsigned int uv_meta_stride = 0, uv_meta_scanlines = 0;\n\tunsigned int y_meta_plane = 0, uv_meta_plane = 0;\n\tunsigned int rgb_stride = 0, rgb_scanlines = 0;\n\tunsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane = 0;\n\tunsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0;\n\n\tif (!width || !height)\n\t\tgoto invalid_input;\n\n\ty_stride = VENUS_Y_STRIDE(color_fmt, width);\n\tuv_stride = VENUS_UV_STRIDE(color_fmt, width);\n\ty_sclines = VENUS_Y_SCANLINES(color_fmt, height);\n\tuv_sclines = VENUS_UV_SCANLINES(color_fmt, height);\n\trgb_stride = VENUS_RGB_STRIDE(color_fmt, width);\n\trgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height);\n\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV21:\n\tcase COLOR_FMT_NV12:\n\t\tuv_alignment = 4096;\n\t\ty_plane = y_stride * y_sclines;\n\t\tuv_plane = uv_stride * uv_sclines + uv_alignment;\n\t\tsize = y_plane + uv_plane +\n\t\t\t\tMSM_MEDIA_MAX(extra_size, 8 * y_stride);\n\t\tsize = MSM_MEDIA_ALIGN(size, 4096);\n\t\tbreak;\n\tcase COLOR_FMT_NV12_MVTB:\n\t\tuv_alignment = 4096;\n\t\ty_plane = y_stride * y_sclines;\n\t\tuv_plane = uv_stride * uv_sclines + uv_alignment;\n\t\tsize = y_plane + uv_plane;\n\t\tsize = 2 * size + extra_size;\n\t\tsize = MSM_MEDIA_ALIGN(size, 4096);\n\t\tbreak;\n\tcase COLOR_FMT_NV12_UBWC:\n\tcase COLOR_FMT_NV12_BPP10_UBWC:\n\t\ty_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096);\n\t\tuv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096);\n\t\ty_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width);\n\t\ty_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height);\n\t\ty_meta_plane = MSM_MEDIA_ALIGN(\n\t\t\t\ty_meta_stride * y_meta_scanlines, 4096);\n\t\tuv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width);\n\t\tuv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height);\n\t\tuv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride *\n\t\t\t\t\tuv_meta_scanlines, 4096);\n\n\t\tsize = y_ubwc_plane + uv_ubwc_plane + y_meta_plane +\n\t\t\tuv_meta_plane +\n\t\t\tMSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride);\n\t\tsize = MSM_MEDIA_ALIGN(size, 4096);\n\t\tbreak;\n\tcase COLOR_FMT_RGBA8888:\n\t\trgb_plane = MSM_MEDIA_ALIGN(rgb_stride  * rgb_scanlines, 4096);\n\t\tsize = rgb_plane;\n\t\tsize =  MSM_MEDIA_ALIGN(size, 4096);\n\t\tbreak;\n\tcase COLOR_FMT_RGBA8888_UBWC:\n\t\trgb_ubwc_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines,\n\t\t\t\t\t\t\t4096);\n\t\trgb_meta_stride = VENUS_RGB_META_STRIDE(color_fmt, width);\n\t\trgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color_fmt,\n\t\t\t\t\theight);\n\t\trgb_meta_plane = MSM_MEDIA_ALIGN(rgb_meta_stride *\n\t\t\t\t\trgb_meta_scanlines, 4096);\n\t\tsize = rgb_ubwc_plane + rgb_meta_plane;\n\t\tsize = MSM_MEDIA_ALIGN(size, 4096);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ninvalid_input:\n\treturn size;\n}\n\nstatic inline unsigned int VENUS_VIEW2_OFFSET(\n\tint color_fmt, int width, int height)\n{\n\tunsigned int offset = 0;\n\tunsigned int y_plane, uv_plane, y_stride,\n\t\tuv_stride, y_sclines, uv_sclines;\n\tif (!width || !height)\n\t\tgoto invalid_input;\n\n\ty_stride = VENUS_Y_STRIDE(color_fmt, width);\n\tuv_stride = VENUS_UV_STRIDE(color_fmt, width);\n\ty_sclines = VENUS_Y_SCANLINES(color_fmt, height);\n\tuv_sclines = VENUS_UV_SCANLINES(color_fmt, height);\n\tswitch (color_fmt) {\n\tcase COLOR_FMT_NV12_MVTB:\n\t\ty_plane = y_stride * y_sclines;\n\t\tuv_plane = uv_stride * uv_sclines;\n\t\toffset = y_plane + uv_plane;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ninvalid_input:\n\treturn offset;\n}\n\n#endif\n"
  },
  {
    "path": "selfdrive/loggerd/logger.cc",
    "content": "#include \"selfdrive/loggerd/logger.h\"\n\n#include <sys/stat.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cerrno>\n#include <cstdint>\n#include <cstdio>\n#include <cstdlib>\n#include <cstring>\n#include <ctime>\n#include <fstream>\n#include <iostream>\n#include <streambuf>\n#ifdef QCOM\n#include <cutils/properties.h>\n#endif\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/version.h\"\n\n// ***** logging helpers *****\n\nvoid append_property(const char* key, const char* value, void *cookie) {\n  std::vector<std::pair<std::string, std::string> > *properties =\n    (std::vector<std::pair<std::string, std::string> > *)cookie;\n\n  properties->push_back(std::make_pair(std::string(key), std::string(value)));\n}\n\nint logger_mkpath(char* file_path) {\n  assert(file_path && *file_path);\n  char* p;\n  for (p=strchr(file_path+1, '/'); p; p=strchr(p+1, '/')) {\n    *p = '\\0';\n    if (mkdir(file_path, 0775)==-1) {\n      if (errno != EEXIST) {\n        *p = '/';\n        return -1;\n      }\n    }\n    *p = '/';\n  }\n  return 0;\n}\n\n// ***** log metadata *****\nkj::Array<capnp::word> logger_build_init_data() {\n  MessageBuilder msg;\n  auto init = msg.initEvent().initInitData();\n\n  if (Hardware::EON()) {\n    init.setDeviceType(cereal::InitData::DeviceType::NEO);\n  } else if (Hardware::TICI()) {\n    init.setDeviceType(cereal::InitData::DeviceType::TICI);\n  } else {\n    init.setDeviceType(cereal::InitData::DeviceType::PC);\n  }\n\n  init.setVersion(COMMA_VERSION);\n\n  std::ifstream cmdline_stream(\"/proc/cmdline\");\n  std::vector<std::string> kernel_args;\n  std::string buf;\n  while (cmdline_stream >> buf) {\n    kernel_args.push_back(buf);\n  }\n\n  auto lkernel_args = init.initKernelArgs(kernel_args.size());\n  for (int i=0; i<kernel_args.size(); i++) {\n    lkernel_args.set(i, kernel_args[i]);\n  }\n\n  init.setKernelVersion(util::read_file(\"/proc/version\"));\n  init.setOsVersion(util::read_file(\"/VERSION\"));\n\n#ifdef QCOM\n  {\n    std::vector<std::pair<std::string, std::string> > properties;\n    property_list(append_property, (void*)&properties);\n\n    auto lentries = init.initAndroidProperties().initEntries(properties.size());\n    for (int i=0; i<properties.size(); i++) {\n      auto lentry = lentries[i];\n      lentry.setKey(properties[i].first);\n      lentry.setValue(properties[i].second);\n    }\n  }\n#endif\n\n  init.setDirty(!getenv(\"CLEAN\"));\n\n  // log params\n  auto params = Params();\n  std::map<std::string, std::string> params_map = params.readAll();\n\n  init.setGitCommit(params_map[\"GitCommit\"]);\n  init.setGitBranch(params_map[\"GitBranch\"]);\n  init.setGitRemote(params_map[\"GitRemote\"]);\n  init.setPassive(params.getBool(\"Passive\"));\n  init.setDongleId(params_map[\"DongleId\"]);\n\n  auto lparams = init.initParams().initEntries(params_map.size());\n  int i = 0;\n  for (auto& [key, value] : params_map) {\n    auto lentry = lparams[i];\n    lentry.setKey(key);\n    if ( !(params.getKeyType(key) & DONT_LOG) ) {\n      lentry.setValue(capnp::Data::Reader((const kj::byte*)value.data(), value.size()));\n    }\n    i++;\n\n  }\n  return capnp::messageToFlatArray(msg);\n}\n\nstd::string logger_get_route_name() {\n  char route_name[64] = {'\\0'};\n  time_t rawtime = time(NULL);\n  struct tm timeinfo;\n  localtime_r(&rawtime, &timeinfo);\n  strftime(route_name, sizeof(route_name), \"%Y-%m-%d--%H-%M-%S\", &timeinfo);\n  return route_name;\n}\n\nvoid log_init_data(LoggerState *s) {\n  auto bytes = s->init_data.asBytes();\n  logger_log(s, bytes.begin(), bytes.size(), s->has_qlog);\n}\n\n\nstatic void lh_log_sentinel(LoggerHandle *h, SentinelType type) {\n  MessageBuilder msg;\n  auto sen = msg.initEvent().initSentinel();\n  sen.setType(type);\n  sen.setSignal(h->exit_signal);\n  auto bytes = msg.toBytes();\n\n  lh_log(h, bytes.begin(), bytes.size(), true);\n}\n\n// ***** logging functions *****\n\nvoid logger_init(LoggerState *s, const char* log_name, bool has_qlog) {\n  pthread_mutex_init(&s->lock, NULL);\n\n  s->part = -1;\n  s->has_qlog = has_qlog;\n  s->route_name = logger_get_route_name();\n  snprintf(s->log_name, sizeof(s->log_name), \"%s\", log_name);\n  s->init_data = logger_build_init_data();\n}\n\nstatic LoggerHandle* logger_open(LoggerState *s, const char* root_path) {\n  int err;\n\n  LoggerHandle *h = NULL;\n  for (int i=0; i<LOGGER_MAX_HANDLES; i++) {\n    if (s->handles[i].refcnt == 0) {\n      h = &s->handles[i];\n      break;\n    }\n  }\n  assert(h);\n\n  snprintf(h->segment_path, sizeof(h->segment_path),\n          \"%s/%s--%d\", root_path, s->route_name.c_str(), s->part);\n\n  snprintf(h->log_path, sizeof(h->log_path), \"%s/%s.bz2\", h->segment_path, s->log_name);\n  snprintf(h->qlog_path, sizeof(h->qlog_path), \"%s/qlog.bz2\", h->segment_path);\n  snprintf(h->lock_path, sizeof(h->lock_path), \"%s.lock\", h->log_path);\n  h->end_sentinel_type = SentinelType::END_OF_SEGMENT;\n  h->exit_signal = 0;\n\n  err = logger_mkpath(h->log_path);\n  if (err) return NULL;\n\n  FILE* lock_file = fopen(h->lock_path, \"wb\");\n  if (lock_file == NULL) return NULL;\n  fclose(lock_file);\n\n  h->log = std::make_unique<BZFile>(h->log_path);\n  if (s->has_qlog) {\n    h->q_log = std::make_unique<BZFile>(h->qlog_path);\n  }\n\n  pthread_mutex_init(&h->lock, NULL);\n  h->refcnt++;\n  return h;\n}\n\nint logger_next(LoggerState *s, const char* root_path,\n                            char* out_segment_path, size_t out_segment_path_len,\n                            int* out_part) {\n  bool is_start_of_route = !s->cur_handle;\n\n  pthread_mutex_lock(&s->lock);\n  s->part++;\n\n  LoggerHandle* next_h = logger_open(s, root_path);\n  if (!next_h) {\n    pthread_mutex_unlock(&s->lock);\n    return -1;\n  }\n\n  if (s->cur_handle) {\n    lh_close(s->cur_handle);\n  }\n  s->cur_handle = next_h;\n\n  if (out_segment_path) {\n    snprintf(out_segment_path, out_segment_path_len, \"%s\", next_h->segment_path);\n  }\n  if (out_part) {\n    *out_part = s->part;\n  }\n\n  pthread_mutex_unlock(&s->lock);\n\n  // write beggining of log metadata\n  log_init_data(s);\n  lh_log_sentinel(s->cur_handle, is_start_of_route ? SentinelType::START_OF_ROUTE : SentinelType::START_OF_SEGMENT);\n  return 0;\n}\n\nLoggerHandle* logger_get_handle(LoggerState *s) {\n  pthread_mutex_lock(&s->lock);\n  LoggerHandle* h = s->cur_handle;\n  if (h) {\n    pthread_mutex_lock(&h->lock);\n    h->refcnt++;\n    pthread_mutex_unlock(&h->lock);\n  }\n  pthread_mutex_unlock(&s->lock);\n  return h;\n}\n\nvoid logger_log(LoggerState *s, uint8_t* data, size_t data_size, bool in_qlog) {\n  pthread_mutex_lock(&s->lock);\n  if (s->cur_handle) {\n    lh_log(s->cur_handle, data, data_size, in_qlog);\n  }\n  pthread_mutex_unlock(&s->lock);\n}\n\nvoid logger_close(LoggerState *s, ExitHandler *exit_handler) {\n  pthread_mutex_lock(&s->lock);\n  if (s->cur_handle) {\n    s->cur_handle->exit_signal = exit_handler && exit_handler->signal.load();\n    s->cur_handle->end_sentinel_type = SentinelType::END_OF_ROUTE;\n    lh_close(s->cur_handle);\n  }\n  pthread_mutex_unlock(&s->lock);\n}\n\nvoid lh_log(LoggerHandle* h, uint8_t* data, size_t data_size, bool in_qlog) {\n  pthread_mutex_lock(&h->lock);\n  assert(h->refcnt > 0);\n  h->log->write(data, data_size);\n  if (in_qlog && h->q_log) {\n    h->q_log->write(data, data_size);\n  }\n  pthread_mutex_unlock(&h->lock);\n}\n\nvoid lh_close(LoggerHandle* h) {\n  pthread_mutex_lock(&h->lock);\n  assert(h->refcnt > 0);\n  if (h->refcnt == 1) {\n    // a very ugly hack. only here can guarantee sentinel is the last msg\n    pthread_mutex_unlock(&h->lock);\n    lh_log_sentinel(h, h->end_sentinel_type);\n    pthread_mutex_lock(&h->lock);\n  }\n  h->refcnt--;\n  if (h->refcnt == 0) {\n    h->log.reset(nullptr);\n    h->q_log.reset(nullptr);\n    unlink(h->lock_path);\n    pthread_mutex_unlock(&h->lock);\n    pthread_mutex_destroy(&h->lock);\n    return;\n  }\n  pthread_mutex_unlock(&h->lock);\n}\n"
  },
  {
    "path": "selfdrive/loggerd/logger.h",
    "content": "#pragma once\n\n#include <cassert>\n#include <pthread.h>\n\n#include <cstdint>\n#include <cstdio>\n#include <memory>\n\n#include <bzlib.h>\n#include <capnp/serialize.h>\n#include <kj/array.h>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/hardware/hw.h\"\n\nconst std::string LOG_ROOT = Path::log_root();\n\n#define LOGGER_MAX_HANDLES 16\n\nclass BZFile {\n public:\n  BZFile(const char* path) {\n    file = fopen(path, \"wb\");\n    assert(file != nullptr);\n    int bzerror;\n    bz_file = BZ2_bzWriteOpen(&bzerror, file, 9, 0, 30);\n    assert(bzerror == BZ_OK);\n  }\n  ~BZFile() {\n    int bzerror;\n    BZ2_bzWriteClose(&bzerror, bz_file, 0, nullptr, nullptr);\n    if (bzerror != BZ_OK) {\n      LOGE(\"BZ2_bzWriteClose error, bzerror=%d\", bzerror);\n    }\n    int err = fclose(file);\n    assert(err == 0);\n  }\n  inline void write(void* data, size_t size) {\n    int bzerror;\n    do {\n      BZ2_bzWrite(&bzerror, bz_file, data, size);\n    } while (bzerror == BZ_IO_ERROR && errno == EINTR);\n\n    if (bzerror != BZ_OK && !error_logged) {\n      LOGE(\"BZ2_bzWrite error, bzerror=%d\", bzerror);\n      error_logged = true;\n    }\n  }\n  inline void write(kj::ArrayPtr<capnp::byte> array) { write(array.begin(), array.size()); }\n\n private:\n  bool error_logged = false;\n  FILE* file = nullptr;\n  BZFILE* bz_file = nullptr;\n};\n\ntypedef cereal::Sentinel::SentinelType SentinelType;\n\ntypedef struct LoggerHandle {\n  pthread_mutex_t lock;\n  SentinelType end_sentinel_type;\n  int exit_signal;\n  int refcnt;\n  char segment_path[4096];\n  char log_path[4096];\n  char qlog_path[4096];\n  char lock_path[4096];\n  std::unique_ptr<BZFile> log, q_log;\n} LoggerHandle;\n\ntypedef struct LoggerState {\n  pthread_mutex_t lock;\n  int part;\n  kj::Array<capnp::word> init_data;\n  std::string route_name;\n  char log_name[64];\n  bool has_qlog;\n\n  LoggerHandle handles[LOGGER_MAX_HANDLES];\n  LoggerHandle* cur_handle;\n} LoggerState;\n\nint logger_mkpath(char* file_path);\nkj::Array<capnp::word> logger_build_init_data();\nstd::string logger_get_route_name();\nvoid logger_init(LoggerState *s, const char* log_name, bool has_qlog);\nint logger_next(LoggerState *s, const char* root_path,\n                            char* out_segment_path, size_t out_segment_path_len,\n                            int* out_part);\nLoggerHandle* logger_get_handle(LoggerState *s);\nvoid logger_close(LoggerState *s, ExitHandler *exit_handler=nullptr);\nvoid logger_log(LoggerState *s, uint8_t* data, size_t data_size, bool in_qlog);\n\nvoid lh_log(LoggerHandle* h, uint8_t* data, size_t data_size, bool in_qlog);\nvoid lh_close(LoggerHandle* h);\n"
  },
  {
    "path": "selfdrive/loggerd/loggerd.cc",
    "content": "#include <ftw.h>\n#include <pthread.h>\n#include <sys/resource.h>\n#include <unistd.h>\n\n#include <atomic>\n#include <cassert>\n#include <cerrno>\n#include <condition_variable>\n#include <cstdint>\n#include <cstdio>\n#include <cstdlib>\n#include <cstring>\n#include <mutex>\n#include <random>\n#include <string>\n#include <thread>\n#include <unordered_map>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"cereal/services.h\"\n#include \"cereal/visionipc/visionipc.h\"\n#include \"cereal/visionipc/visionipc_client.h\"\n#include \"selfdrive/camerad/cameras/camera_common.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n\n#include \"selfdrive/loggerd/encoder.h\"\n#include \"selfdrive/loggerd/logger.h\"\n#if defined(QCOM) || defined(QCOM2)\n#include \"selfdrive/loggerd/omx_encoder.h\"\n#define Encoder OmxEncoder\n#else\n#include \"selfdrive/loggerd/raw_logger.h\"\n#define Encoder RawLogger\n#endif\n\nnamespace {\n\nconstexpr int MAIN_FPS = 20;\nconst int MAIN_BITRATE = Hardware::TICI() ? 10000000 : 5000000;\nconst int DCAM_BITRATE = Hardware::TICI() ? MAIN_BITRATE : 2500000;\n\n#define NO_CAMERA_PATIENCE 500 // fall back to time-based rotation if all cameras are dead\n\nconst bool LOGGERD_TEST = getenv(\"LOGGERD_TEST\");\nconst int SEGMENT_LENGTH = LOGGERD_TEST ? atoi(getenv(\"LOGGERD_SEGMENT_LENGTH\")) : 60;\n\nExitHandler do_exit;\n\nconst LogCameraInfo cameras_logged[] = {\n  {\n    .type = RoadCam,\n    .stream_type = VISION_STREAM_YUV_BACK,\n    .filename = \"fcamera.hevc\",\n    .frame_packet_name = \"roadCameraState\",\n    .fps = MAIN_FPS,\n    .bitrate = MAIN_BITRATE,\n    .is_h265 = true,\n    .downscale = false,\n    .has_qcamera = true,\n    .trigger_rotate = true,\n    .enable = true,\n  },\n  {\n    .type = DriverCam,\n    .stream_type = VISION_STREAM_YUV_FRONT,\n    .filename = \"dcamera.hevc\",\n    .frame_packet_name = \"driverCameraState\",\n    .fps = MAIN_FPS, // on EONs, more compressed this way\n    .bitrate = DCAM_BITRATE,\n    .is_h265 = true,\n    .downscale = false,\n    .has_qcamera = false,\n    .trigger_rotate = Hardware::TICI(),\n    .enable = !Hardware::PC() && !Hardware::JETSON() && Params().getBool(\"RecordFront\"),\n  },\n  {\n    .type = WideRoadCam,\n    .stream_type = VISION_STREAM_YUV_WIDE,\n    .filename = \"ecamera.hevc\",\n    .frame_packet_name = \"wideRoadCameraState\",\n    .fps = MAIN_FPS,\n    .bitrate = MAIN_BITRATE,\n    .is_h265 = true,\n    .downscale = false,\n    .has_qcamera = false,\n    .trigger_rotate = true,\n    .enable = Hardware::TICI(),\n  },\n};\nconst LogCameraInfo qcam_info = {\n  .filename = \"qcamera.ts\",\n  .fps = MAIN_FPS,\n  .bitrate = 256000,\n  .is_h265 = false,\n  .downscale = true,\n  .frame_width = Hardware::TICI() ? 526 : 480,\n  .frame_height = Hardware::TICI() ? 330 : 360 // keep pixel count the same?\n};\n\nstruct LoggerdState {\n  Context *ctx;\n  LoggerState logger = {};\n  char segment_path[4096];\n  std::mutex rotate_lock;\n  std::condition_variable rotate_cv;\n  std::atomic<int> rotate_segment;\n  std::atomic<double> last_camera_seen_tms;\n  std::atomic<int> waiting_rotate;\n  int max_waiting = 0;\n  double last_rotate_tms = 0.;\n\n  // Sync logic for startup\n  std::atomic<bool> encoders_synced;\n  std::atomic<int> encoders_ready;\n  std::atomic<uint32_t> start_frame_id;\n  std::atomic<uint32_t> latest_frame_id;\n};\nLoggerdState s;\n\nvoid encoder_thread(const LogCameraInfo &cam_info) {\n  set_thread_name(cam_info.filename);\n\n  int cnt = 0, cur_seg = -1;\n  int encode_idx = 0;\n  LoggerHandle *lh = NULL;\n  std::vector<Encoder *> encoders;\n  VisionIpcClient vipc_client = VisionIpcClient(\"camerad\", cam_info.stream_type, false);\n\n  bool ready = false;\n\n  while (!do_exit) {\n    if (!vipc_client.connect(false)) {\n      util::sleep_for(5);\n      continue;\n    }\n\n    // init encoders\n    if (encoders.empty()) {\n      VisionBuf buf_info = vipc_client.buffers[0];\n      LOGD(\"encoder init %dx%d\", buf_info.width, buf_info.height);\n\n      // main encoder\n      encoders.push_back(new Encoder(cam_info.filename, buf_info.width, buf_info.height,\n                                     cam_info.fps, cam_info.bitrate, cam_info.is_h265, cam_info.downscale));\n      // qcamera encoder\n      if (cam_info.has_qcamera) {\n        encoders.push_back(new Encoder(qcam_info.filename, qcam_info.frame_width, qcam_info.frame_height,\n                                       qcam_info.fps, qcam_info.bitrate, qcam_info.is_h265, qcam_info.downscale));\n      }\n    }\n\n    while (!do_exit) {\n      VisionIpcBufExtra extra;\n      VisionBuf* buf = vipc_client.recv(&extra);\n      if (buf == nullptr) continue;\n\n      if (cam_info.trigger_rotate && (s.max_waiting > 1)) {\n        if (!ready) {\n          LOGE(\"%s encoder ready\", cam_info.filename);\n          ++s.encoders_ready;\n          ready = true;\n        }\n\n        if (!s.encoders_synced) {\n          update_max_atomic(s.latest_frame_id, extra.frame_id);\n          continue;\n        } else {\n          // Wait for all encoders to reach the same frame id\n          if (extra.frame_id < s.start_frame_id) {\n            LOGE(\"%s waiting for frame %d, cur %d\", cam_info.filename, s.start_frame_id.load(), extra.frame_id);\n            continue;\n          }\n        }\n      }\n\n      if (cam_info.trigger_rotate) {\n        s.last_camera_seen_tms = millis_since_boot();\n      }\n\n      if (cam_info.trigger_rotate && (cnt >= SEGMENT_LENGTH * MAIN_FPS)) {\n        // trigger rotate and wait logger rotated to new segment\n        ++s.waiting_rotate;\n        std::unique_lock lk(s.rotate_lock);\n        s.rotate_cv.wait(lk, [&] { return s.rotate_segment > cur_seg || do_exit; });\n      }\n      if (do_exit) break;\n\n      // rotate the encoder if the logger is on a newer segment\n      if (s.rotate_segment > cur_seg) {\n        cur_seg = s.rotate_segment;\n        cnt = 0;\n\n        LOGW(\"camera %d rotate encoder to %s\", cam_info.type, s.segment_path);\n        for (auto &e : encoders) {\n          e->encoder_close();\n          e->encoder_open(s.segment_path);\n        }\n        if (lh) {\n          lh_close(lh);\n        }\n        lh = logger_get_handle(&s.logger);\n      }\n\n      // encode a frame\n      for (int i = 0; i < encoders.size(); ++i) {\n        int out_id = encoders[i]->encode_frame(buf->y, buf->u, buf->v,\n                                               buf->width, buf->height, extra.timestamp_eof);\n        \n        if (out_id == -1) {\n          LOGE(\"Failed to encode frame. frame_id: %d encode_id: %d\", extra.frame_id, encode_idx);\n        }\n\n        // publish encode index\n        if (i == 0 && out_id != -1) {\n          MessageBuilder msg;\n          // this is really ugly\n          auto eidx = cam_info.type == DriverCam ? msg.initEvent().initDriverEncodeIdx() :\n                     (cam_info.type == WideRoadCam ? msg.initEvent().initWideRoadEncodeIdx() : msg.initEvent().initRoadEncodeIdx());\n          eidx.setFrameId(extra.frame_id);\n          eidx.setTimestampSof(extra.timestamp_sof);\n          eidx.setTimestampEof(extra.timestamp_eof);\n          if (Hardware::TICI()) {\n            eidx.setType(cereal::EncodeIndex::Type::FULL_H_E_V_C);\n          } else {\n            eidx.setType(cam_info.type == DriverCam ? cereal::EncodeIndex::Type::FRONT : cereal::EncodeIndex::Type::FULL_H_E_V_C);\n          }\n          eidx.setEncodeId(encode_idx);\n          eidx.setSegmentNum(cur_seg);\n          eidx.setSegmentId(out_id);\n          if (lh) {\n            // TODO: this should read cereal/services.h for qlog decimation\n            auto bytes = msg.toBytes();\n            lh_log(lh, bytes.begin(), bytes.size(), true);\n          }\n        }\n      }\n\n      cnt++;\n      encode_idx++;\n    }\n\n    if (lh) {\n      lh_close(lh);\n      lh = NULL;\n    }\n  }\n\n  LOG(\"encoder destroy\");\n  for(auto &e : encoders) {\n    e->encoder_close();\n    delete e;\n  }\n}\n\nint clear_locks_fn(const char* fpath, const struct stat *sb, int tyupeflag) {\n  const char* dot = strrchr(fpath, '.');\n  if (dot && strcmp(dot, \".lock\") == 0) {\n    unlink(fpath);\n  }\n  return 0;\n}\n\nvoid clear_locks() {\n  ftw(LOG_ROOT.c_str(), clear_locks_fn, 16);\n}\n\nvoid logger_rotate() {\n  {\n    std::unique_lock lk(s.rotate_lock);\n    int segment = -1;\n    int err = logger_next(&s.logger, LOG_ROOT.c_str(), s.segment_path, sizeof(s.segment_path), &segment);\n    assert(err == 0);\n    s.rotate_segment = segment;\n    s.waiting_rotate = 0;\n    s.last_rotate_tms = millis_since_boot();\n  }\n  s.rotate_cv.notify_all();\n  LOGW((s.logger.part == 0) ? \"logging to %s\" : \"rotated to %s\", s.segment_path);\n}\n\nvoid rotate_if_needed() {\n  if (s.waiting_rotate == s.max_waiting) {\n    logger_rotate();\n  }\n\n  double tms = millis_since_boot();\n  if ((tms - s.last_rotate_tms) > SEGMENT_LENGTH * 1000 &&\n      (tms - s.last_camera_seen_tms) > NO_CAMERA_PATIENCE &&\n      !LOGGERD_TEST) {\n    LOGW(\"no camera packet seen. auto rotating\");\n    logger_rotate();\n  }\n}\n\n} // namespace\n\nint main(int argc, char** argv) {\n  setpriority(PRIO_PROCESS, 0, -20);\n\n  clear_locks();\n\n  // setup messaging\n  typedef struct QlogState {\n    int counter, freq;\n  } QlogState;\n  std::unordered_map<SubSocket*, QlogState> qlog_states;\n\n  s.ctx = Context::create();\n  Poller * poller = Poller::create();\n\n  // subscribe to all socks\n  for (const auto& it : services) {\n    if (!it.should_log) continue;\n\n    SubSocket * sock = SubSocket::create(s.ctx, it.name);\n    assert(sock != NULL);\n    poller->registerSocket(sock);\n    qlog_states[sock] = {.counter = 0, .freq = it.decimation};\n  }\n\n  // init logger\n  logger_init(&s.logger, \"rlog\", true);\n  logger_rotate();\n  Params().put(\"CurrentRoute\", s.logger.route_name);\n\n  // init encoders\n  s.last_camera_seen_tms = millis_since_boot();\n  std::vector<std::thread> encoder_threads;\n  for (const auto &ci : cameras_logged) {\n    if (ci.enable) {\n      encoder_threads.push_back(std::thread(encoder_thread, ci));\n      if (ci.trigger_rotate) s.max_waiting++;\n    }\n  }\n\n  uint64_t msg_count = 0, bytes_count = 0;\n  double start_ts = millis_since_boot();\n  while (!do_exit) {\n    // Check if all encoders are ready and start encoding at the same time\n    if ((s.max_waiting > 1) && !s.encoders_synced && (s.encoders_ready == s.max_waiting)) {\n      // Small margin in case one of the encoders already dropped the next frame\n      s.start_frame_id = s.latest_frame_id + 2;\n      s.encoders_synced = true;\n      LOGE(\"starting encoders at frame id %d\", s.start_frame_id.load());\n    }\n\n\n    // poll for new messages on all sockets\n    for (auto sock : poller->poll(1000)) {\n      // drain socket\n      QlogState &qs = qlog_states[sock];\n      Message *msg = nullptr;\n      while (!do_exit && (msg = sock->receive(true))) {\n        const bool in_qlog = qs.freq != -1 && (qs.counter++ % qs.freq == 0);\n        logger_log(&s.logger, (uint8_t *)msg->getData(), msg->getSize(), in_qlog);\n        bytes_count += msg->getSize();\n        delete msg;\n\n        rotate_if_needed();\n\n        if ((++msg_count % 1000) == 0) {\n          double seconds = (millis_since_boot() - start_ts) / 1000.0;\n          LOGD(\"%lu messages, %.2f msg/sec, %.2f KB/sec\", msg_count, msg_count / seconds, bytes_count * 0.001 / seconds);\n        }\n      }\n    }\n  }\n\n  LOGW(\"closing encoders\");\n  s.rotate_cv.notify_all();\n  for (auto &t : encoder_threads) t.join();\n\n  LOGW(\"closing logger\");\n  logger_close(&s.logger, &do_exit);\n\n  if (do_exit.power_failure) {\n    LOGE(\"power failure\");\n    sync();\n    LOGE(\"sync done\");\n  }\n\n  // messaging cleanup\n  for (auto &[sock, qs] : qlog_states) delete sock;\n  delete poller;\n  delete s.ctx;\n\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/loggerd/omx_encoder.cc",
    "content": "#pragma clang diagnostic ignored \"-Wdeprecated-declarations\"\n\n#include \"selfdrive/loggerd/omx_encoder.h\"\n\n#include <fcntl.h>\n#include <sys/stat.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cstdlib>\n#include <cstdio>\n\n#include <OMX_Component.h>\n#include <OMX_IndexExt.h>\n#include <OMX_QCOMExtns.h>\n#include <OMX_VideoExt.h>\n#include \"libyuv.h\"\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/loggerd/include/msm_media_info.h\"\n\n// Check the OMX error code and assert if an error occurred.\n#define OMX_CHECK(_expr)              \\\n  do {                                \\\n    assert(OMX_ErrorNone == (_expr)); \\\n  } while (0)\n\nextern ExitHandler do_exit;\n\n// ***** OMX callback functions *****\n\nvoid OmxEncoder::wait_for_state(OMX_STATETYPE state) {\n  std::unique_lock lk(this->state_lock);\n  while (this->state != state) {\n    this->state_cv.wait(lk);\n  }\n}\n\nstatic OMX_CALLBACKTYPE omx_callbacks = {\n  .EventHandler = OmxEncoder::event_handler,\n  .EmptyBufferDone = OmxEncoder::empty_buffer_done,\n  .FillBufferDone = OmxEncoder::fill_buffer_done,\n};\n\nOMX_ERRORTYPE OmxEncoder::event_handler(OMX_HANDLETYPE component, OMX_PTR app_data, OMX_EVENTTYPE event,\n                                   OMX_U32 data1, OMX_U32 data2, OMX_PTR event_data) {\n  OmxEncoder *e = (OmxEncoder*)app_data;\n  if (event == OMX_EventCmdComplete) {\n    assert(data1 == OMX_CommandStateSet);\n    LOG(\"set state event 0x%x\", data2);\n    {\n      std::unique_lock lk(e->state_lock);\n      e->state = (OMX_STATETYPE)data2;\n    }\n    e->state_cv.notify_all();\n  } else if (event == OMX_EventError) {\n    LOGE(\"OMX error 0x%08x\", data1);\n  } else {\n    LOGE(\"OMX unhandled event %d\", event);\n    assert(false);\n  }\n\n  return OMX_ErrorNone;\n}\n\nOMX_ERRORTYPE OmxEncoder::empty_buffer_done(OMX_HANDLETYPE component, OMX_PTR app_data,\n                                                   OMX_BUFFERHEADERTYPE *buffer) {\n  // printf(\"empty_buffer_done\\n\");\n  OmxEncoder *e = (OmxEncoder*)app_data;\n  e->free_in.push(buffer);\n  return OMX_ErrorNone;\n}\n\nOMX_ERRORTYPE OmxEncoder::fill_buffer_done(OMX_HANDLETYPE component, OMX_PTR app_data,\n                                                  OMX_BUFFERHEADERTYPE *buffer) {\n  // printf(\"fill_buffer_done\\n\");\n  OmxEncoder *e = (OmxEncoder*)app_data;\n  e->done_out.push(buffer);\n  return OMX_ErrorNone;\n}\n\n#define PORT_INDEX_IN 0\n#define PORT_INDEX_OUT 1\n\nstatic const char* omx_color_fomat_name(uint32_t format) __attribute__((unused));\nstatic const char* omx_color_fomat_name(uint32_t format) {\n  switch (format) {\n  case OMX_COLOR_FormatUnused: return \"OMX_COLOR_FormatUnused\";\n  case OMX_COLOR_FormatMonochrome: return \"OMX_COLOR_FormatMonochrome\";\n  case OMX_COLOR_Format8bitRGB332: return \"OMX_COLOR_Format8bitRGB332\";\n  case OMX_COLOR_Format12bitRGB444: return \"OMX_COLOR_Format12bitRGB444\";\n  case OMX_COLOR_Format16bitARGB4444: return \"OMX_COLOR_Format16bitARGB4444\";\n  case OMX_COLOR_Format16bitARGB1555: return \"OMX_COLOR_Format16bitARGB1555\";\n  case OMX_COLOR_Format16bitRGB565: return \"OMX_COLOR_Format16bitRGB565\";\n  case OMX_COLOR_Format16bitBGR565: return \"OMX_COLOR_Format16bitBGR565\";\n  case OMX_COLOR_Format18bitRGB666: return \"OMX_COLOR_Format18bitRGB666\";\n  case OMX_COLOR_Format18bitARGB1665: return \"OMX_COLOR_Format18bitARGB1665\";\n  case OMX_COLOR_Format19bitARGB1666: return \"OMX_COLOR_Format19bitARGB1666\";\n  case OMX_COLOR_Format24bitRGB888: return \"OMX_COLOR_Format24bitRGB888\";\n  case OMX_COLOR_Format24bitBGR888: return \"OMX_COLOR_Format24bitBGR888\";\n  case OMX_COLOR_Format24bitARGB1887: return \"OMX_COLOR_Format24bitARGB1887\";\n  case OMX_COLOR_Format25bitARGB1888: return \"OMX_COLOR_Format25bitARGB1888\";\n  case OMX_COLOR_Format32bitBGRA8888: return \"OMX_COLOR_Format32bitBGRA8888\";\n  case OMX_COLOR_Format32bitARGB8888: return \"OMX_COLOR_Format32bitARGB8888\";\n  case OMX_COLOR_FormatYUV411Planar: return \"OMX_COLOR_FormatYUV411Planar\";\n  case OMX_COLOR_FormatYUV411PackedPlanar: return \"OMX_COLOR_FormatYUV411PackedPlanar\";\n  case OMX_COLOR_FormatYUV420Planar: return \"OMX_COLOR_FormatYUV420Planar\";\n  case OMX_COLOR_FormatYUV420PackedPlanar: return \"OMX_COLOR_FormatYUV420PackedPlanar\";\n  case OMX_COLOR_FormatYUV420SemiPlanar: return \"OMX_COLOR_FormatYUV420SemiPlanar\";\n  case OMX_COLOR_FormatYUV422Planar: return \"OMX_COLOR_FormatYUV422Planar\";\n  case OMX_COLOR_FormatYUV422PackedPlanar: return \"OMX_COLOR_FormatYUV422PackedPlanar\";\n  case OMX_COLOR_FormatYUV422SemiPlanar: return \"OMX_COLOR_FormatYUV422SemiPlanar\";\n  case OMX_COLOR_FormatYCbYCr: return \"OMX_COLOR_FormatYCbYCr\";\n  case OMX_COLOR_FormatYCrYCb: return \"OMX_COLOR_FormatYCrYCb\";\n  case OMX_COLOR_FormatCbYCrY: return \"OMX_COLOR_FormatCbYCrY\";\n  case OMX_COLOR_FormatCrYCbY: return \"OMX_COLOR_FormatCrYCbY\";\n  case OMX_COLOR_FormatYUV444Interleaved: return \"OMX_COLOR_FormatYUV444Interleaved\";\n  case OMX_COLOR_FormatRawBayer8bit: return \"OMX_COLOR_FormatRawBayer8bit\";\n  case OMX_COLOR_FormatRawBayer10bit: return \"OMX_COLOR_FormatRawBayer10bit\";\n  case OMX_COLOR_FormatRawBayer8bitcompressed: return \"OMX_COLOR_FormatRawBayer8bitcompressed\";\n  case OMX_COLOR_FormatL2: return \"OMX_COLOR_FormatL2\";\n  case OMX_COLOR_FormatL4: return \"OMX_COLOR_FormatL4\";\n  case OMX_COLOR_FormatL8: return \"OMX_COLOR_FormatL8\";\n  case OMX_COLOR_FormatL16: return \"OMX_COLOR_FormatL16\";\n  case OMX_COLOR_FormatL24: return \"OMX_COLOR_FormatL24\";\n  case OMX_COLOR_FormatL32: return \"OMX_COLOR_FormatL32\";\n  case OMX_COLOR_FormatYUV420PackedSemiPlanar: return \"OMX_COLOR_FormatYUV420PackedSemiPlanar\";\n  case OMX_COLOR_FormatYUV422PackedSemiPlanar: return \"OMX_COLOR_FormatYUV422PackedSemiPlanar\";\n  case OMX_COLOR_Format18BitBGR666: return \"OMX_COLOR_Format18BitBGR666\";\n  case OMX_COLOR_Format24BitARGB6666: return \"OMX_COLOR_Format24BitARGB6666\";\n  case OMX_COLOR_Format24BitABGR6666: return \"OMX_COLOR_Format24BitABGR6666\";\n\n  case OMX_COLOR_FormatAndroidOpaque: return \"OMX_COLOR_FormatAndroidOpaque\";\n  case OMX_TI_COLOR_FormatYUV420PackedSemiPlanar: return \"OMX_TI_COLOR_FormatYUV420PackedSemiPlanar\";\n  case OMX_QCOM_COLOR_FormatYVU420SemiPlanar: return \"OMX_QCOM_COLOR_FormatYVU420SemiPlanar\";\n  case OMX_QCOM_COLOR_FormatYUV420PackedSemiPlanar64x32Tile2m8ka: return \"OMX_QCOM_COLOR_FormatYUV420PackedSemiPlanar64x32Tile2m8ka\";\n  case OMX_SEC_COLOR_FormatNV12Tiled: return \"OMX_SEC_COLOR_FormatNV12Tiled\";\n  case OMX_QCOM_COLOR_FormatYUV420PackedSemiPlanar32m: return \"OMX_QCOM_COLOR_FormatYUV420PackedSemiPlanar32m\";\n\n  // case QOMX_COLOR_FormatYVU420SemiPlanar: return \"QOMX_COLOR_FormatYVU420SemiPlanar\";\n  case QOMX_COLOR_FormatYVU420PackedSemiPlanar32m4ka: return \"QOMX_COLOR_FormatYVU420PackedSemiPlanar32m4ka\";\n  case QOMX_COLOR_FormatYUV420PackedSemiPlanar16m2ka: return \"QOMX_COLOR_FormatYUV420PackedSemiPlanar16m2ka\";\n  // case QOMX_COLOR_FormatYUV420PackedSemiPlanar64x32Tile2m8ka: return \"QOMX_COLOR_FormatYUV420PackedSemiPlanar64x32Tile2m8ka\";\n  // case QOMX_COLOR_FORMATYUV420PackedSemiPlanar32m: return \"QOMX_COLOR_FORMATYUV420PackedSemiPlanar32m\";\n  case QOMX_COLOR_FORMATYUV420PackedSemiPlanar32mMultiView: return \"QOMX_COLOR_FORMATYUV420PackedSemiPlanar32mMultiView\";\n  case QOMX_COLOR_FORMATYUV420PackedSemiPlanar32mCompressed: return \"QOMX_COLOR_FORMATYUV420PackedSemiPlanar32mCompressed\";\n  case QOMX_COLOR_Format32bitRGBA8888: return \"QOMX_COLOR_Format32bitRGBA8888\";\n  case QOMX_COLOR_Format32bitRGBA8888Compressed: return \"QOMX_COLOR_Format32bitRGBA8888Compressed\";\n\n  default:\n    return \"unkn\";\n  }\n}\n\n\n// ***** encoder functions *****\n\nOmxEncoder::OmxEncoder(const char* filename, int width, int height, int fps, int bitrate, bool h265, bool downscale) {\n  this->filename = filename;\n  this->width = width;\n  this->height = height;\n  this->fps = fps;\n  this->remuxing = !h265;\n\n  this->downscale = downscale;\n  if (this->downscale) {\n    this->y_ptr2 = (uint8_t *)malloc(this->width*this->height);\n    this->u_ptr2 = (uint8_t *)malloc(this->width*this->height/4);\n    this->v_ptr2 = (uint8_t *)malloc(this->width*this->height/4);\n  }\n\n  auto component = (OMX_STRING)(h265 ? \"OMX.qcom.video.encoder.hevc\" : \"OMX.qcom.video.encoder.avc\");\n  int err = OMX_GetHandle(&this->handle, component, this, &omx_callbacks);\n  if (err != OMX_ErrorNone) {\n    LOGE(\"error getting codec: %x\", err);\n  }\n  assert(err == OMX_ErrorNone);\n  // printf(\"handle: %p\\n\", this->handle);\n\n  // setup input port\n\n  OMX_PARAM_PORTDEFINITIONTYPE in_port = {0};\n  in_port.nSize = sizeof(in_port);\n  in_port.nPortIndex = (OMX_U32) PORT_INDEX_IN;\n  OMX_CHECK(OMX_GetParameter(this->handle, OMX_IndexParamPortDefinition, (OMX_PTR) &in_port));\n\n  in_port.format.video.nFrameWidth = this->width;\n  in_port.format.video.nFrameHeight = this->height;\n  in_port.format.video.nStride = VENUS_Y_STRIDE(COLOR_FMT_NV12, this->width);\n  in_port.format.video.nSliceHeight = this->height;\n  // in_port.nBufferSize = (this->width * this->height * 3) / 2;\n  in_port.nBufferSize = VENUS_BUFFER_SIZE(COLOR_FMT_NV12, this->width, this->height);\n  in_port.format.video.xFramerate = (this->fps * 65536);\n  in_port.format.video.eCompressionFormat = OMX_VIDEO_CodingUnused;\n  // in_port.format.video.eColorFormat = OMX_COLOR_FormatYUV420SemiPlanar;\n  in_port.format.video.eColorFormat = (OMX_COLOR_FORMATTYPE)QOMX_COLOR_FORMATYUV420PackedSemiPlanar32m;\n\n  OMX_CHECK(OMX_SetParameter(this->handle, OMX_IndexParamPortDefinition, (OMX_PTR) &in_port));\n  OMX_CHECK(OMX_GetParameter(this->handle, OMX_IndexParamPortDefinition, (OMX_PTR) &in_port));\n  this->in_buf_headers.resize(in_port.nBufferCountActual);\n\n  // setup output port\n\n  OMX_PARAM_PORTDEFINITIONTYPE out_port = {0};\n  out_port.nSize = sizeof(out_port);\n  out_port.nPortIndex = (OMX_U32) PORT_INDEX_OUT;\n  OMX_CHECK(OMX_GetParameter(this->handle, OMX_IndexParamPortDefinition, (OMX_PTR)&out_port));\n  out_port.format.video.nFrameWidth = this->width;\n  out_port.format.video.nFrameHeight = this->height;\n  out_port.format.video.xFramerate = 0;\n  out_port.format.video.nBitrate = bitrate;\n  if (h265) {\n    out_port.format.video.eCompressionFormat = OMX_VIDEO_CodingHEVC;\n  } else {\n    out_port.format.video.eCompressionFormat = OMX_VIDEO_CodingAVC;\n  }\n  out_port.format.video.eColorFormat = OMX_COLOR_FormatUnused;\n\n  OMX_CHECK(OMX_SetParameter(this->handle, OMX_IndexParamPortDefinition, (OMX_PTR) &out_port));\n\n  OMX_CHECK(OMX_GetParameter(this->handle, OMX_IndexParamPortDefinition, (OMX_PTR) &out_port));\n  this->out_buf_headers.resize(out_port.nBufferCountActual);\n\n  OMX_VIDEO_PARAM_BITRATETYPE bitrate_type = {0};\n  bitrate_type.nSize = sizeof(bitrate_type);\n  bitrate_type.nPortIndex = (OMX_U32) PORT_INDEX_OUT;\n  OMX_CHECK(OMX_GetParameter(this->handle, OMX_IndexParamVideoBitrate, (OMX_PTR) &bitrate_type));\n  bitrate_type.eControlRate = OMX_Video_ControlRateVariable;\n  bitrate_type.nTargetBitrate = bitrate;\n\n  OMX_CHECK(OMX_SetParameter(this->handle, OMX_IndexParamVideoBitrate, (OMX_PTR) &bitrate_type));\n\n  if (h265) {\n    // setup HEVC\n  #ifndef QCOM2\n    OMX_VIDEO_PARAM_HEVCTYPE hevc_type = {0};\n    OMX_INDEXTYPE index_type = (OMX_INDEXTYPE) OMX_IndexParamVideoHevc;\n  #else\n    OMX_VIDEO_PARAM_PROFILELEVELTYPE hevc_type = {0};\n    OMX_INDEXTYPE index_type = OMX_IndexParamVideoProfileLevelCurrent;\n  #endif\n    hevc_type.nSize = sizeof(hevc_type);\n    hevc_type.nPortIndex = (OMX_U32) PORT_INDEX_OUT;\n    OMX_CHECK(OMX_GetParameter(this->handle, index_type, (OMX_PTR) &hevc_type));\n\n    hevc_type.eProfile = OMX_VIDEO_HEVCProfileMain;\n    hevc_type.eLevel = OMX_VIDEO_HEVCHighTierLevel5;\n\n    OMX_CHECK(OMX_SetParameter(this->handle, index_type, (OMX_PTR) &hevc_type));\n  } else {\n    // setup h264\n    OMX_VIDEO_PARAM_AVCTYPE avc = { 0 };\n    avc.nSize = sizeof(avc);\n    avc.nPortIndex = (OMX_U32) PORT_INDEX_OUT;\n    OMX_CHECK(OMX_GetParameter(this->handle, OMX_IndexParamVideoAvc, &avc));\n\n    avc.nBFrames = 0;\n    avc.nPFrames = 15;\n\n    avc.eProfile = OMX_VIDEO_AVCProfileHigh;\n    avc.eLevel = OMX_VIDEO_AVCLevel31;\n\n    avc.nAllowedPictureTypes |= OMX_VIDEO_PictureTypeB;\n    avc.eLoopFilterMode = OMX_VIDEO_AVCLoopFilterEnable;\n\n    avc.nRefFrames = 1;\n    avc.bUseHadamard = OMX_TRUE;\n    avc.bEntropyCodingCABAC = OMX_TRUE;\n    avc.bWeightedPPrediction = OMX_TRUE;\n    avc.bconstIpred = OMX_TRUE;\n\n    OMX_CHECK(OMX_SetParameter(this->handle, OMX_IndexParamVideoAvc, &avc));\n  }\n\n\n  // for (int i = 0; ; i++) {\n  //   OMX_VIDEO_PARAM_PORTFORMATTYPE video_port_format = {0};\n  //   video_port_format.nSize = sizeof(video_port_format);\n  //   video_port_format.nIndex = i;\n  //   video_port_format.nPortIndex = PORT_INDEX_IN;\n  //   if (OMX_GetParameter(this->handle, OMX_IndexParamVideoPortFormat, &video_port_format) != OMX_ErrorNone)\n  //       break;\n  //   printf(\"in %d: compression 0x%x format 0x%x %s\\n\", i,\n  //          video_port_format.eCompressionFormat, video_port_format.eColorFormat,\n  //          omx_color_fomat_name(video_port_format.eColorFormat));\n  // }\n\n  // for (int i=0; i<32; i++) {\n  //   OMX_VIDEO_PARAM_PROFILELEVELTYPE params = {0};\n  //   params.nSize = sizeof(params);\n  //   params.nPortIndex = PORT_INDEX_OUT;\n  //   params.nProfileIndex = i;\n  //   if (OMX_GetParameter(this->handle, OMX_IndexParamVideoProfileLevelQuerySupported, &params) != OMX_ErrorNone)\n  //       break;\n  //   printf(\"profile %d level 0x%x\\n\", params.eProfile, params.eLevel);\n  // }\n\n  OMX_CHECK(OMX_SendCommand(this->handle, OMX_CommandStateSet, OMX_StateIdle, NULL));\n\n  for (auto &buf : this->in_buf_headers) {\n    OMX_CHECK(OMX_AllocateBuffer(this->handle, &buf, PORT_INDEX_IN, this,\n                             in_port.nBufferSize));\n  }\n\n  for (auto &buf : this->out_buf_headers) {\n    OMX_CHECK(OMX_AllocateBuffer(this->handle, &buf, PORT_INDEX_OUT, this,\n                             out_port.nBufferSize));\n  }\n\n  wait_for_state(OMX_StateIdle);\n\n  OMX_CHECK(OMX_SendCommand(this->handle, OMX_CommandStateSet, OMX_StateExecuting, NULL));\n\n  wait_for_state(OMX_StateExecuting);\n\n  // give omx all the output buffers\n  for (auto &buf : this->out_buf_headers) {\n    // printf(\"fill %p\\n\", this->out_buf_headers[i]);\n    OMX_CHECK(OMX_FillThisBuffer(this->handle, buf));\n  }\n\n  // fill the input free queue\n  for (auto &buf : this->in_buf_headers) {\n    this->free_in.push(buf);\n  }\n}\n\nvoid OmxEncoder::handle_out_buf(OmxEncoder *e, OMX_BUFFERHEADERTYPE *out_buf) {\n  int err;\n  uint8_t *buf_data = out_buf->pBuffer + out_buf->nOffset;\n\n  if (out_buf->nFlags & OMX_BUFFERFLAG_CODECCONFIG) {\n    if (e->codec_config_len < out_buf->nFilledLen) {\n      e->codec_config = (uint8_t *)realloc(e->codec_config, out_buf->nFilledLen);\n    }\n    e->codec_config_len = out_buf->nFilledLen;\n    memcpy(e->codec_config, buf_data, out_buf->nFilledLen);\n#ifdef QCOM2\n    out_buf->nTimeStamp = 0;\n#endif\n  }\n\n  if (e->of) {\n    //printf(\"write %d flags 0x%x\\n\", out_buf->nFilledLen, out_buf->nFlags);\n    fwrite(buf_data, out_buf->nFilledLen, 1, e->of);\n  }\n\n  if (e->remuxing) {\n    if (!e->wrote_codec_config && e->codec_config_len > 0) {\n      // extradata will be freed by av_free() in avcodec_free_context()\n      e->codec_ctx->extradata = (uint8_t*)av_mallocz(e->codec_config_len + AV_INPUT_BUFFER_PADDING_SIZE);\n      e->codec_ctx->extradata_size = e->codec_config_len;\n      memcpy(e->codec_ctx->extradata, e->codec_config, e->codec_config_len);\n\n      err = avcodec_parameters_from_context(e->out_stream->codecpar, e->codec_ctx);\n      assert(err >= 0);\n      err = avformat_write_header(e->ofmt_ctx, NULL);\n      assert(err >= 0);\n\n      e->wrote_codec_config = true;\n    }\n\n    if (out_buf->nTimeStamp > 0) {\n      // input timestamps are in microseconds\n      AVRational in_timebase = {1, 1000000};\n\n      AVPacket pkt;\n      av_init_packet(&pkt);\n      pkt.data = buf_data;\n      pkt.size = out_buf->nFilledLen;\n\n      enum AVRounding rnd = static_cast<enum AVRounding>(AV_ROUND_NEAR_INF|AV_ROUND_PASS_MINMAX);\n      pkt.pts = pkt.dts = av_rescale_q_rnd(out_buf->nTimeStamp, in_timebase, e->ofmt_ctx->streams[0]->time_base, rnd);\n      pkt.duration = av_rescale_q(50*1000, in_timebase, e->ofmt_ctx->streams[0]->time_base);\n\n      if (out_buf->nFlags & OMX_BUFFERFLAG_SYNCFRAME) {\n        pkt.flags |= AV_PKT_FLAG_KEY;\n      }\n\n      err = av_write_frame(e->ofmt_ctx, &pkt);\n      if (err < 0) { LOGW(\"ts encoder write issue\"); }\n\n      av_free_packet(&pkt);\n    }\n  }\n\n  // give omx back the buffer\n#ifdef QCOM2\n  if (out_buf->nFlags & OMX_BUFFERFLAG_EOS) {\n    out_buf->nTimeStamp = 0;\n  }\n#endif\n  OMX_CHECK(OMX_FillThisBuffer(e->handle, out_buf));\n}\n\nint OmxEncoder::encode_frame(const uint8_t *y_ptr, const uint8_t *u_ptr, const uint8_t *v_ptr,\n                             int in_width, int in_height, uint64_t ts) {\n  int err;\n  if (!this->is_open) {\n    return -1;\n  }\n\n  // this sometimes freezes... put it outside the encoder lock so we can still trigger rotates...\n  // THIS IS A REALLY BAD IDEA, but apparently the race has to happen 30 times to trigger this\n  //pthread_mutex_unlock(&this->lock);\n  OMX_BUFFERHEADERTYPE* in_buf = nullptr;\n  while (!this->free_in.try_pop(in_buf, 20)) {\n    if (do_exit) {\n      return -1;\n    }\n  }\n\n  //pthread_mutex_lock(&this->lock);\n\n  int ret = this->counter;\n\n  uint8_t *in_buf_ptr = in_buf->pBuffer;\n  // printf(\"in_buf ptr %p\\n\", in_buf_ptr);\n\n  uint8_t *in_y_ptr = in_buf_ptr;\n  int in_y_stride = VENUS_Y_STRIDE(COLOR_FMT_NV12, this->width);\n  int in_uv_stride = VENUS_UV_STRIDE(COLOR_FMT_NV12, this->width);\n  // uint8_t *in_uv_ptr = in_buf_ptr + (this->width * this->height);\n  uint8_t *in_uv_ptr = in_buf_ptr + (in_y_stride * VENUS_Y_SCANLINES(COLOR_FMT_NV12, this->height));\n\n  if (this->downscale) {\n    I420Scale(y_ptr, in_width,\n              u_ptr, in_width/2,\n              v_ptr, in_width/2,\n              in_width, in_height,\n              this->y_ptr2, this->width,\n              this->u_ptr2, this->width/2,\n              this->v_ptr2, this->width/2,\n              this->width, this->height,\n              libyuv::kFilterNone);\n    y_ptr = this->y_ptr2;\n    u_ptr = this->u_ptr2;\n    v_ptr = this->v_ptr2;\n  }\n  err = libyuv::I420ToNV12(y_ptr, this->width,\n                   u_ptr, this->width/2,\n                   v_ptr, this->width/2,\n                   in_y_ptr, in_y_stride,\n                   in_uv_ptr, in_uv_stride,\n                   this->width, this->height);\n  assert(err == 0);\n\n  // in_buf->nFilledLen = (this->width*this->height) + (this->width*this->height/2);\n  in_buf->nFilledLen = VENUS_BUFFER_SIZE(COLOR_FMT_NV12, this->width, this->height);\n  in_buf->nFlags = OMX_BUFFERFLAG_ENDOFFRAME;\n  in_buf->nOffset = 0;\n  in_buf->nTimeStamp = ts/1000LL;  // OMX_TICKS, in microseconds\n  this->last_t = in_buf->nTimeStamp;\n\n  OMX_CHECK(OMX_EmptyThisBuffer(this->handle, in_buf));\n\n  // pump output\n  while (true) {\n    OMX_BUFFERHEADERTYPE *out_buf;\n    if (!this->done_out.try_pop(out_buf)) {\n      break;\n    }\n    handle_out_buf(this, out_buf);\n  }\n\n  this->dirty = true;\n\n  this->counter++;\n\n  return ret;\n}\n\nvoid OmxEncoder::encoder_open(const char* path) {\n  int err;\n\n  snprintf(this->vid_path, sizeof(this->vid_path), \"%s/%s\", path, this->filename);\n  LOGD(\"encoder_open %s remuxing:%d\", this->vid_path, this->remuxing);\n\n  if (this->remuxing) {\n    avformat_alloc_output_context2(&this->ofmt_ctx, NULL, NULL, this->vid_path);\n    assert(this->ofmt_ctx);\n\n    this->out_stream = avformat_new_stream(this->ofmt_ctx, NULL);\n    assert(this->out_stream);\n\n    // set codec correctly\n    av_register_all();\n\n    AVCodec *codec = NULL;\n    codec = avcodec_find_encoder(AV_CODEC_ID_H264);\n    assert(codec);\n\n    this->codec_ctx = avcodec_alloc_context3(codec);\n    assert(this->codec_ctx);\n    this->codec_ctx->width = this->width;\n    this->codec_ctx->height = this->height;\n    this->codec_ctx->pix_fmt = AV_PIX_FMT_YUV420P;\n    this->codec_ctx->time_base = (AVRational){ 1, this->fps };\n\n    err = avio_open(&this->ofmt_ctx->pb, this->vid_path, AVIO_FLAG_WRITE);\n    assert(err >= 0);\n\n    this->wrote_codec_config = false;\n  } else {\n    this->of = fopen(this->vid_path, \"wb\");\n    assert(this->of);\n#ifndef QCOM2\n    if (this->codec_config_len > 0) {\n      fwrite(this->codec_config, this->codec_config_len, 1, this->of);\n    }\n#endif\n  }\n\n  // create camera lock file\n  snprintf(this->lock_path, sizeof(this->lock_path), \"%s/%s.lock\", path, this->filename);\n  int lock_fd = HANDLE_EINTR(open(this->lock_path, O_RDWR | O_CREAT, 0664));\n  assert(lock_fd >= 0);\n  close(lock_fd);\n\n  this->is_open = true;\n  this->counter = 0;\n}\n\nvoid OmxEncoder::encoder_close() {\n  if (this->is_open) {\n    if (this->dirty) {\n      // drain output only if there could be frames in the encoder\n\n      OMX_BUFFERHEADERTYPE* in_buf = this->free_in.pop();\n      in_buf->nFilledLen = 0;\n      in_buf->nOffset = 0;\n      in_buf->nFlags = OMX_BUFFERFLAG_EOS;\n      in_buf->nTimeStamp = this->last_t + 1000000LL/this->fps;\n\n      OMX_CHECK(OMX_EmptyThisBuffer(this->handle, in_buf));\n\n      while (true) {\n        OMX_BUFFERHEADERTYPE *out_buf = this->done_out.pop();\n\n        handle_out_buf(this, out_buf);\n\n        if (out_buf->nFlags & OMX_BUFFERFLAG_EOS) {\n          break;\n        }\n      }\n      this->dirty = false;\n    }\n\n    if (this->remuxing) {\n      av_write_trailer(this->ofmt_ctx);\n      avcodec_free_context(&this->codec_ctx);\n      avio_closep(&this->ofmt_ctx->pb);\n      avformat_free_context(this->ofmt_ctx);\n    } else {\n      fclose(this->of);\n      this->of = nullptr;\n    }\n    unlink(this->lock_path);\n  }\n  this->is_open = false;\n}\n\nOmxEncoder::~OmxEncoder() {\n  assert(!this->is_open);\n\n  OMX_CHECK(OMX_SendCommand(this->handle, OMX_CommandStateSet, OMX_StateIdle, NULL));\n\n  wait_for_state(OMX_StateIdle);\n\n  OMX_CHECK(OMX_SendCommand(this->handle, OMX_CommandStateSet, OMX_StateLoaded, NULL));\n\n  for (auto &buf : this->in_buf_headers) {\n    OMX_CHECK(OMX_FreeBuffer(this->handle, PORT_INDEX_IN, buf));\n  }\n\n  for (auto &buf : this->out_buf_headers) {\n    OMX_CHECK(OMX_FreeBuffer(this->handle, PORT_INDEX_OUT, buf));\n  }\n\n  wait_for_state(OMX_StateLoaded);\n\n  OMX_CHECK(OMX_FreeHandle(this->handle));\n\n  OMX_BUFFERHEADERTYPE *out_buf;\n  while (this->free_in.try_pop(out_buf));\n  while (this->done_out.try_pop(out_buf));\n\n  if (this->codec_config) {\n    free(this->codec_config);\n  }\n\n  if (this->downscale) {\n    free(this->y_ptr2);\n    free(this->u_ptr2);\n    free(this->v_ptr2);\n  }\n}\n"
  },
  {
    "path": "selfdrive/loggerd/omx_encoder.h",
    "content": "#pragma once\n\n#include <cstdint>\n#include <cstdio>\n#include <vector>\n\n#include <OMX_Component.h>\nextern \"C\" {\n#include <libavformat/avformat.h>\n}\n\n#include \"selfdrive/common/queue.h\"\n#include \"selfdrive/loggerd/encoder.h\"\n\n// OmxEncoder, lossey codec using hardware hevc\nclass OmxEncoder : public VideoEncoder {\npublic:\n  OmxEncoder(const char* filename, int width, int height, int fps, int bitrate, bool h265, bool downscale);\n  ~OmxEncoder();\n  int encode_frame(const uint8_t *y_ptr, const uint8_t *u_ptr, const uint8_t *v_ptr,\n                   int in_width, int in_height, uint64_t ts);\n  void encoder_open(const char* path);\n  void encoder_close();\n\n  // OMX callbacks\n  static OMX_ERRORTYPE event_handler(OMX_HANDLETYPE component, OMX_PTR app_data, OMX_EVENTTYPE event,\n                                     OMX_U32 data1, OMX_U32 data2, OMX_PTR event_data);\n  static OMX_ERRORTYPE empty_buffer_done(OMX_HANDLETYPE component, OMX_PTR app_data,\n                                         OMX_BUFFERHEADERTYPE *buffer);\n  static OMX_ERRORTYPE fill_buffer_done(OMX_HANDLETYPE component, OMX_PTR app_data,\n                                        OMX_BUFFERHEADERTYPE *buffer);\n\nprivate:\n  void wait_for_state(OMX_STATETYPE state);\n  static void handle_out_buf(OmxEncoder *e, OMX_BUFFERHEADERTYPE *out_buf);\n\n  int width, height, fps;\n  char vid_path[1024];\n  char lock_path[1024];\n  bool is_open = false;\n  bool dirty = false;\n  int counter = 0;\n\n  const char* filename;\n  FILE *of;\n\n  size_t codec_config_len;\n  uint8_t *codec_config = NULL;\n  bool wrote_codec_config;\n\n  std::mutex state_lock;\n  std::condition_variable state_cv;\n  OMX_STATETYPE state = OMX_StateLoaded;\n\n  OMX_HANDLETYPE handle;\n\n  std::vector<OMX_BUFFERHEADERTYPE *> in_buf_headers;\n  std::vector<OMX_BUFFERHEADERTYPE *> out_buf_headers;\n\n  uint64_t last_t;\n\n  SafeQueue<OMX_BUFFERHEADERTYPE *> free_in;\n  SafeQueue<OMX_BUFFERHEADERTYPE *> done_out;\n\n  AVFormatContext *ofmt_ctx;\n  AVCodecContext *codec_ctx;\n  AVStream *out_stream;\n  bool remuxing;\n\n  bool downscale;\n  uint8_t *y_ptr2, *u_ptr2, *v_ptr2;\n};\n"
  },
  {
    "path": "selfdrive/loggerd/raw_logger.cc",
    "content": "#pragma clang diagnostic ignored \"-Wdeprecated-declarations\"\n\n#include \"selfdrive/loggerd/raw_logger.h\"\n\n#include <fcntl.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cstdio>\n#include <cstdlib>\n\n#define __STDC_CONSTANT_MACROS\n\nextern \"C\" {\n#include <libavcodec/avcodec.h>\n#include <libavformat/avformat.h>\n#include <libavutil/imgutils.h>\n}\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n\nRawLogger::RawLogger(const char* filename, int width, int height, int fps,\n                     int bitrate, bool h265, bool downscale)\n  : filename(filename),\n    fps(fps) {\n\n  av_register_all();\n  codec = avcodec_find_encoder(AV_CODEC_ID_FFVHUFF);\n  // codec = avcodec_find_encoder(AV_CODEC_ID_FFV1);\n  assert(codec);\n\n  codec_ctx = avcodec_alloc_context3(codec);\n  assert(codec_ctx);\n  codec_ctx->width = width;\n  codec_ctx->height = height;\n  codec_ctx->pix_fmt = AV_PIX_FMT_YUV420P;\n\n  // codec_ctx->thread_count = 2;\n\n  // ffv1enc doesn't respect AV_PICTURE_TYPE_I. make every frame a key frame for now.\n  // codec_ctx->gop_size = 0;\n\n  codec_ctx->time_base = (AVRational){ 1, fps };\n\n  int err = avcodec_open2(codec_ctx, codec, NULL);\n  assert(err >= 0);\n\n  frame = av_frame_alloc();\n  assert(frame);\n  frame->format = codec_ctx->pix_fmt;\n  frame->width = width;\n  frame->height = height;\n  frame->linesize[0] = width;\n  frame->linesize[1] = width/2;\n  frame->linesize[2] = width/2;\n}\n\nRawLogger::~RawLogger() {\n  av_frame_free(&frame);\n  avcodec_close(codec_ctx);\n  av_free(codec_ctx);\n}\n\nvoid RawLogger::encoder_open(const char* path) {\n  vid_path = util::string_format(\"%s/%s.mkv\", path, filename);\n\n  // create camera lock file\n  lock_path = util::string_format(\"%s/%s.lock\", path, filename);\n\n  LOG(\"open %s\\n\", lock_path.c_str());\n\n  int lock_fd = HANDLE_EINTR(open(lock_path.c_str(), O_RDWR | O_CREAT, 0664));\n  assert(lock_fd >= 0);\n  close(lock_fd);\n\n  format_ctx = NULL;\n  avformat_alloc_output_context2(&format_ctx, NULL, NULL, vid_path.c_str());\n  assert(format_ctx);\n\n  stream = avformat_new_stream(format_ctx, codec);\n  // AVStream *stream = avformat_new_stream(format_ctx, NULL);\n  assert(stream);\n  stream->id = 0;\n  stream->time_base = (AVRational){ 1, fps };\n  // codec_ctx->time_base = stream->time_base;\n\n  int err = avcodec_parameters_from_context(stream->codecpar, codec_ctx);\n  assert(err >= 0);\n\n  err = avio_open(&format_ctx->pb, vid_path.c_str(), AVIO_FLAG_WRITE);\n  assert(err >= 0);\n\n  err = avformat_write_header(format_ctx, NULL);\n  assert(err >= 0);\n\n  is_open = true;\n  counter = 0;\n}\n\nvoid RawLogger::encoder_close() {\n  if (!is_open) return;\n\n  int err = av_write_trailer(format_ctx);\n  assert(err == 0);\n\n  avcodec_close(stream->codec);\n\n  err = avio_closep(&format_ctx->pb);\n  assert(err == 0);\n\n  avformat_free_context(format_ctx);\n  format_ctx = NULL;\n\n  unlink(lock_path.c_str());\n  is_open = false;\n}\n\nint RawLogger::encode_frame(const uint8_t *y_ptr, const uint8_t *u_ptr, const uint8_t *v_ptr,\n                            int in_width, int in_height, uint64_t ts) {\n  AVPacket pkt;\n  av_init_packet(&pkt);\n  pkt.data = NULL;\n  pkt.size = 0;\n\n  frame->data[0] = (uint8_t*)y_ptr;\n  frame->data[1] = (uint8_t*)u_ptr;\n  frame->data[2] = (uint8_t*)v_ptr;\n  frame->pts = ts;\n\n  int ret = counter;\n\n  int got_output = 0;\n  int err = avcodec_encode_video2(codec_ctx, &pkt, frame, &got_output);\n  if (err) {\n    LOGE(\"encoding error\\n\");\n    ret = -1;\n  } else if (got_output) {\n    av_packet_rescale_ts(&pkt, codec_ctx->time_base, stream->time_base);\n    pkt.stream_index = 0;\n\n    err = av_interleaved_write_frame(format_ctx, &pkt);\n    if (err < 0) {\n      LOGE(\"encoder writer error\\n\");\n      ret = -1;\n    } else {\n      counter++;\n    }\n  }\n\n  return ret;\n}\n"
  },
  {
    "path": "selfdrive/loggerd/raw_logger.h",
    "content": "#pragma once\n\n#include <cstdio>\n#include <cstdlib>\n#include <string>\n#include <vector>\n\nextern \"C\" {\n#include <libavcodec/avcodec.h>\n#include <libavformat/avformat.h>\n#include <libavutil/imgutils.h>\n}\n\n#include \"selfdrive/loggerd/encoder.h\"\n\nclass RawLogger : public VideoEncoder {\n public:\n  RawLogger(const char* filename, int width, int height, int fps,\n            int bitrate, bool h265, bool downscale);\n  ~RawLogger();\n  int encode_frame(const uint8_t *y_ptr, const uint8_t *u_ptr, const uint8_t *v_ptr,\n                   int in_width, int in_height, uint64_t ts);\n  void encoder_open(const char* path);\n  void encoder_close();\n\nprivate:\n  const char* filename;\n  int fps;\n  int counter = 0;\n  bool is_open = false;\n\n  std::string vid_path, lock_path;\n\n  AVCodec *codec = NULL;\n  AVCodecContext *codec_ctx = NULL;\n\n  AVStream *stream = NULL;\n  AVFormatContext *format_ctx = NULL;\n\n  AVFrame *frame = NULL;\n};\n"
  },
  {
    "path": "selfdrive/loggerd/uploader.py",
    "content": "#!/usr/bin/env python3\nimport json\nimport os\nimport random\nimport requests\nimport threading\nimport time\nimport traceback\nfrom pathlib import Path\n\nfrom cereal import log\nimport cereal.messaging as messaging\nfrom common.api import Api\nfrom common.params import Params\nfrom selfdrive.hardware import TICI\nfrom selfdrive.loggerd.xattr_cache import getxattr, setxattr\nfrom selfdrive.loggerd.config import ROOT\nfrom selfdrive.swaglog import cloudlog\n\nNetworkType = log.DeviceState.NetworkType\nUPLOAD_ATTR_NAME = 'user.upload'\nUPLOAD_ATTR_VALUE = b'1'\n\nallow_sleep = bool(os.getenv(\"UPLOADER_SLEEP\", \"1\"))\nforce_wifi = os.getenv(\"FORCEWIFI\") is not None\nfake_upload = os.getenv(\"FAKEUPLOAD\") is not None\n\n\ndef get_directory_sort(d):\n  return list(map(lambda s: s.rjust(10, '0'), d.rsplit('--', 1)))\n\ndef listdir_by_creation(d):\n  try:\n    paths = os.listdir(d)\n    paths = sorted(paths, key=get_directory_sort)\n    return paths\n  except OSError:\n    cloudlog.exception(\"listdir_by_creation failed\")\n    return list()\n\ndef clear_locks(root):\n  for logname in os.listdir(root):\n    path = os.path.join(root, logname)\n    try:\n      for fname in os.listdir(path):\n        if fname.endswith(\".lock\"):\n          os.unlink(os.path.join(path, fname))\n    except OSError:\n      cloudlog.exception(\"clear_locks failed\")\n\n\nclass Uploader():\n  def __init__(self, dongle_id, root):\n    self.dongle_id = dongle_id\n    self.api = Api(dongle_id)\n    self.root = root\n\n    self.upload_thread = None\n\n    self.last_resp = None\n    self.last_exc = None\n\n    self.raw_size = 0\n    self.raw_count = 0\n    self.immediate_size = 0\n    self.immediate_count = 0\n\n    # stats for last successfully uploaded file\n    self.last_time = 0\n    self.last_speed = 0\n    self.last_filename = \"\"\n\n    self.immediate_folders = [\"crash/\", \"boot/\"]\n    self.immediate_priority = {\"qlog.bz2\": 0, \"qcamera.ts\": 1}\n    self.high_priority = {\"rlog.bz2\": 0, \"fcamera.hevc\": 1, \"dcamera.hevc\": 2, \"ecamera.hevc\": 3}\n\n  def get_upload_sort(self, name):\n    if name in self.immediate_priority:\n      return self.immediate_priority[name]\n    if name in self.high_priority:\n      return self.high_priority[name] + 100\n    return 1000\n\n  def list_upload_files(self):\n    if not os.path.isdir(self.root):\n      return\n\n    self.raw_size = 0\n    self.raw_count = 0\n    self.immediate_size = 0\n    self.immediate_count = 0\n\n    for logname in listdir_by_creation(self.root):\n      path = os.path.join(self.root, logname)\n      try:\n        names = os.listdir(path)\n      except OSError:\n        continue\n\n      if any(name.endswith(\".lock\") for name in names):\n        continue\n\n      for name in sorted(names, key=self.get_upload_sort):\n        key = os.path.join(logname, name)\n        fn = os.path.join(path, name)\n        # skip files already uploaded\n        try:\n          is_uploaded = getxattr(fn, UPLOAD_ATTR_NAME)\n        except OSError:\n          cloudlog.event(\"uploader_getxattr_failed\", exc=self.last_exc, key=key, fn=fn)\n          is_uploaded = True  # deleter could have deleted\n        if is_uploaded:\n          continue\n\n        try:\n          if name in self.immediate_priority:\n            self.immediate_count += 1\n            self.immediate_size += os.path.getsize(fn)\n          else:\n            self.raw_count += 1\n            self.raw_size += os.path.getsize(fn)\n        except OSError:\n          pass\n\n        yield (name, key, fn)\n\n  def next_file_to_upload(self, with_raw):\n    upload_files = list(self.list_upload_files())\n\n    # try to upload qlog files first\n    for name, key, fn in upload_files:\n      if name in self.immediate_priority or any(f in fn for f in self.immediate_folders):\n        return (key, fn)\n\n    if with_raw:\n      # then upload the full log files, rear and front camera files\n      for name, key, fn in upload_files:\n        if name in self.high_priority:\n          return (key, fn)\n\n      # then upload other files\n      for name, key, fn in upload_files:\n        if not name.endswith('.lock') and not name.endswith(\".tmp\"):\n          return (key, fn)\n\n    return None\n\n  def do_upload(self, key, fn):\n    try:\n      url_resp = self.api.get(\"v1.3/\"+self.dongle_id+\"/upload_url/\", timeout=10, path=key, access_token=self.api.get_token())\n      if url_resp.status_code == 412:\n        self.last_resp = url_resp\n        return\n\n      url_resp_json = json.loads(url_resp.text)\n      url = url_resp_json['url']\n      headers = url_resp_json['headers']\n      cloudlog.debug(\"upload_url v1.3 %s %s\", url, str(headers))\n\n      if fake_upload:\n        cloudlog.debug(\"*** WARNING, THIS IS A FAKE UPLOAD TO %s ***\" % url)\n\n        class FakeResponse():\n          def __init__(self):\n            self.status_code = 200\n\n        self.last_resp = FakeResponse()\n      else:\n        with open(fn, \"rb\") as f:\n          self.last_resp = requests.put(url, data=f, headers=headers, timeout=10)\n    except Exception as e:\n      self.last_exc = (e, traceback.format_exc())\n      raise\n\n  def normal_upload(self, key, fn):\n    self.last_resp = None\n    self.last_exc = None\n\n    try:\n      self.do_upload(key, fn)\n    except Exception:\n      pass\n\n    return self.last_resp\n\n  def upload(self, key, fn):\n    try:\n      sz = os.path.getsize(fn)\n    except OSError:\n      cloudlog.exception(\"upload: getsize failed\")\n      return False\n\n    cloudlog.event(\"upload\", key=key, fn=fn, sz=sz)\n\n    cloudlog.debug(\"checking %r with size %r\", key, sz)\n\n    if sz == 0:\n      try:\n        # tag files of 0 size as uploaded\n        setxattr(fn, UPLOAD_ATTR_NAME, UPLOAD_ATTR_VALUE)\n      except OSError:\n        cloudlog.event(\"uploader_setxattr_failed\", exc=self.last_exc, key=key, fn=fn, sz=sz)\n      success = True\n    else:\n      start_time = time.monotonic()\n      cloudlog.debug(\"uploading %r\", fn)\n      stat = self.normal_upload(key, fn)\n      if stat is not None and stat.status_code in (200, 201, 403, 412):\n        cloudlog.event(\"upload_success\" if stat.status_code != 412 else \"upload_ignored\", key=key, fn=fn, sz=sz, debug=True)\n        try:\n          # tag file as uploaded\n          setxattr(fn, UPLOAD_ATTR_NAME, UPLOAD_ATTR_VALUE)\n        except OSError:\n          cloudlog.event(\"uploader_setxattr_failed\", exc=self.last_exc, key=key, fn=fn, sz=sz)\n\n        self.last_filename = fn\n        self.last_time = time.monotonic() - start_time\n        self.last_speed = (sz / 1e6) / self.last_time\n        success = True\n      else:\n        cloudlog.event(\"upload_failed\", stat=stat, exc=self.last_exc, key=key, fn=fn, sz=sz, debug=True)\n        success = False\n\n    return success\n\n  def get_msg(self):\n    msg = messaging.new_message(\"uploaderState\")\n    us = msg.uploaderState\n    us.rawQueueSize = int(self.raw_size / 1e6)\n    us.rawQueueCount = self.raw_count\n    us.immediateQueueSize = int(self.immediate_size / 1e6)\n    us.immediateQueueCount = self.immediate_count\n    us.lastTime = self.last_time\n    us.lastSpeed = self.last_speed\n    us.lastFilename = self.last_filename\n    return msg\n\ndef uploader_fn(exit_event):\n  params = Params()\n  dongle_id = params.get(\"DongleId\", encoding='utf8')\n\n  if dongle_id is None:\n    return\n\n  if TICI and not Path(\"/data/media\").is_mount():\n    cloudlog.warning(\"NVME not mounted\")\n\n  sm = messaging.SubMaster(['deviceState'])\n  pm = messaging.PubMaster(['uploaderState'])\n  uploader = Uploader(dongle_id, ROOT)\n\n  backoff = 0.1\n  while not exit_event.is_set():\n    sm.update(0)\n    offroad = params.get_bool(\"IsOffroad\")\n    network_type = sm['deviceState'].networkType if not force_wifi else NetworkType.wifi\n    if network_type == NetworkType.none:\n      if allow_sleep:\n        time.sleep(60 if offroad else 5)\n      continue\n\n    on_wifi = network_type == NetworkType.wifi\n    allow_raw_upload = params.get_bool(\"UploadRaw\")\n\n    d = uploader.next_file_to_upload(with_raw=allow_raw_upload and on_wifi and offroad)\n    if d is None:  # Nothing to upload\n      if allow_sleep:\n        time.sleep(60 if offroad else 5)\n      continue\n\n    key, fn = d\n\n    cloudlog.debug(\"upload %r over %s\", d, network_type)\n    success = uploader.upload(key, fn)\n    if success:\n      backoff = 0.1\n    elif allow_sleep:\n      cloudlog.info(\"upload backoff %r\", backoff)\n      time.sleep(backoff + random.uniform(0, backoff))\n      backoff = min(backoff*2, 120)\n\n    pm.send(\"uploaderState\", uploader.get_msg())\n    cloudlog.info(\"upload done, success=%r\", success)\n\ndef main():\n  uploader_fn(threading.Event())\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/loggerd/xattr_cache.py",
    "content": "from common.xattr import getxattr as getattr1\nfrom common.xattr import setxattr as setattr1\n\ncached_attributes = {}\ndef getxattr(path, attr_name):\n  if (path, attr_name) not in cached_attributes:\n    response = getattr1(path, attr_name)\n    cached_attributes[(path, attr_name)] = response\n  return cached_attributes[(path, attr_name)]\n\ndef setxattr(path, attr_name, attr_value):\n  cached_attributes.pop((path, attr_name), None)\n  return setattr1(path, attr_name, attr_value)\n"
  },
  {
    "path": "selfdrive/logmessaged.py",
    "content": "#!/usr/bin/env python3\nimport zmq\nfrom typing import NoReturn\n\nimport cereal.messaging as messaging\nfrom common.logging_extra import SwagLogFileFormatter\nfrom selfdrive.swaglog import get_file_handler\n\n\ndef main() -> NoReturn:\n  log_handler = get_file_handler()\n  log_handler.setFormatter(SwagLogFileFormatter(None))\n  log_level = 20  # logging.INFO\n\n  ctx = zmq.Context().instance()\n  sock = ctx.socket(zmq.PULL)\n  sock.bind(\"ipc:///tmp/logmessage\")\n\n  # and we publish them\n  pub_sock = messaging.pub_sock('logMessage')\n\n  while True:\n    dat = b''.join(sock.recv_multipart())\n    level = dat[0]\n    record = dat[1:].decode(\"utf-8\")\n    if level >= log_level:\n      log_handler.emit(record)\n\n    # then we publish them\n    msg = messaging.new_message()\n    msg.logMessage = record\n    pub_sock.send(msg.to_bytes())\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/manager/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/manager/build.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport subprocess\nimport sys\nimport time\nimport textwrap\nfrom pathlib import Path\nimport re\n\n# NOTE: Do NOT import anything here that needs be built (e.g. params)\nfrom common.basedir import BASEDIR\nfrom common.spinner import Spinner\nfrom common.text_window import TextWindow\nfrom selfdrive.hardware import TICI\nfrom selfdrive.swaglog import cloudlog, add_file_handler\nfrom selfdrive.version import dirty\n\nMAX_CACHE_SIZE = 2e9\nCACHE_DIR = Path(\"/data/scons_cache\" if TICI else \"/tmp/scons_cache\")\n\nTOTAL_SCONS_NODES = 2405\nMAX_BUILD_PROGRESS = 100\nPREBUILT = os.path.exists(os.path.join(BASEDIR, 'prebuilt'))\n\n\ndef build(spinner, dirty=False):\n  env = os.environ.copy()\n  env['SCONS_PROGRESS'] = \"1\"\n  nproc = os.cpu_count()\n  j_flag = \"\" if nproc is None else f\"-j{nproc - 1}\"\n\n  for retry in [True, False]:\n    scons = subprocess.Popen([\"scons\", j_flag, \"--cache-populate\"], cwd=BASEDIR, env=env, stderr=subprocess.PIPE)\n\n    compile_output = []\n\n    # Read progress from stderr and update spinner\n    while scons.poll() is None:\n      try:\n        line = scons.stderr.readline()\n        if line is None:\n          continue\n        line = line.rstrip()\n\n        prefix = b'progress: '\n        if line.startswith(prefix):\n          i = int(line[len(prefix):])\n          spinner.update_progress(MAX_BUILD_PROGRESS * min(1., i / TOTAL_SCONS_NODES), 100.)\n        elif len(line):\n          compile_output.append(line)\n          print(line.decode('utf8', 'replace'))\n      except Exception:\n        pass\n\n    if scons.returncode != 0:\n      # Read remaining output\n      r = scons.stderr.read().split(b'\\n')\n      compile_output += r\n\n      if retry and (not dirty):\n        if not os.getenv(\"CI\"):\n          print(\"scons build failed, cleaning in\")\n          for i in range(3, -1, -1):\n            print(\"....%d\" % i)\n            time.sleep(1)\n          subprocess.check_call([\"scons\", \"-c\"], cwd=BASEDIR, env=env)\n        else:\n          print(\"scons build failed after retry\")\n          sys.exit(1)\n      else:\n        # Build failed log errors\n        errors = [line.decode('utf8', 'replace') for line in compile_output\n                  if any([err in line for err in [b'error: ', b'not found, needed by target']])]\n        error_s = \"\\n\".join(errors)\n        add_file_handler(cloudlog)\n        cloudlog.error(\"scons build failed\\n\" + error_s)\n\n        try:\n          result = subprocess.check_output([\"ifconfig\", \"wlan0\"], encoding='utf8')\n          ip = re.findall(r\"inet addr:((\\d+\\.){3}\\d+)\", result)[0][0]\n        except:\n          ip = 'N/A'\n\n        # Show TextWindow\n        spinner.close()\n        if not os.getenv(\"CI\"):\n          error_s = \"\\n \\n\".join([\"\\n\".join(textwrap.wrap(e, 65)) for e in errors])\n          with TextWindow((\"openpilot failed to build (IP: %s)\\n \\n\" % ip) + error_s) as t:\n            t.wait_for_exit()\n        exit(1)\n    else:\n      break\n\n  # enforce max cache size\n  cache_files = [f for f in CACHE_DIR.rglob('*') if f.is_file()]\n  cache_files.sort(key=lambda f: f.stat().st_mtime)\n  cache_size = sum(f.stat().st_size for f in cache_files)\n  for f in cache_files:\n    if cache_size < MAX_CACHE_SIZE:\n      break\n    cache_size -= f.stat().st_size\n    f.unlink()\n\n\nif __name__ == \"__main__\" and not PREBUILT:\n  spinner = Spinner()\n  spinner.update_progress(0, 100)\n  build(spinner, dirty)\n"
  },
  {
    "path": "selfdrive/manager/custom_dep.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport sys\nimport errno\nimport shutil\nfrom urllib.request import urlopen\nfrom glob import glob\nimport subprocess\nimport importlib.util\n\n# NOTE: Do NOT import anything here that needs be built (e.g. params)\nfrom common.basedir import BASEDIR\nfrom common.spinner import Spinner\nfrom selfdrive.hardware import TICI\n\n\nOPSPLINE_SPEC = importlib.util.find_spec('opspline') or importlib.util.find_spec('scipy')\nOVERPY_SPEC = importlib.util.find_spec('overpy')\nMAX_BUILD_PROGRESS = 100\nTMP_DIR = '/data/tmp'\nPYEXTRA_DIR = '/data/openpilot/pyextra'\n\n\ndef wait_for_internet_connection():\n  while True:\n    try:\n      _ = urlopen('https://www.google.com/', timeout=10)\n      return\n    except Exception:\n      pass\n\n\ndef install_dep(spinner):\n  wait_for_internet_connection()\n\n  if TICI:\n    TOTAL_PIP_STEPS = 2986\n\n    try:\n      os.makedirs(TMP_DIR)\n    except OSError as e:\n      if e.errno != errno.EEXIST:\n        raise\n    my_env = os.environ.copy()\n    my_env['TMPDIR'] = TMP_DIR\n\n    pip_target = [f'--target={PYEXTRA_DIR}']\n    packages = []\n    if OPSPLINE_SPEC is None:\n      packages.append('scipy==1.7.1')\n    if OVERPY_SPEC is None:\n      packages.append('overpy==0.6')\n\n    pip = subprocess.Popen([sys.executable, \"-m\", \"pip\", \"install\", \"-v\"] + pip_target + packages,\n                           stdout=subprocess.PIPE, env=my_env)\n  else:\n    TOTAL_PIP_STEPS = 24\n    # mount system rw so apt and pip can do its thing\n    subprocess.check_call(['mount', '-o', 'rw,remount', '/system'])\n\n    # Run preparation script for pip installation\n    subprocess.check_call(['sh', './install_gfortran.sh'], cwd=os.path.join(BASEDIR, 'installer/custom/'))\n\n    # install pip from git\n    package = 'git+https://github.com/move-fast/opspline.git@master'\n    pip = subprocess.Popen([sys.executable, \"-m\", \"pip\", \"install\", \"-v\", package], stdout=subprocess.PIPE)\n\n  # Read progress from pip and update spinner\n  steps = 0\n  while True:\n    output = pip.stdout.readline()\n    if pip.poll() is not None:\n      break\n    if output:\n      steps += 1\n      spinner.update_progress(MAX_BUILD_PROGRESS * min(1., steps / TOTAL_PIP_STEPS), 100.)\n      print(output.decode('utf8', 'replace'))\n  if TICI:\n    shutil.rmtree(TMP_DIR)\n    os.unsetenv('TMPDIR')\n\n    # remove numpy installed to PYEXTRA_DIR since numpy is already present in the AGNOS image\n    if OPSPLINE_SPEC is None:\n      for directory in glob(f'{PYEXTRA_DIR}/numpy*'):\n        shutil.rmtree(directory)\n      shutil.rmtree(f'{PYEXTRA_DIR}/bin')\n\n\nif __name__ == \"__main__\" and (OPSPLINE_SPEC is None or OVERPY_SPEC is None):\n  spinner = Spinner()\n  spinner.update_progress(0, 100)\n  install_dep(spinner)\n"
  },
  {
    "path": "selfdrive/manager/helpers.py",
    "content": "import os\nimport sys\nimport fcntl\nimport errno\nimport signal\n\n\ndef unblock_stdout():\n  # get a non-blocking stdout\n  child_pid, child_pty = os.forkpty()\n  if child_pid != 0:  # parent\n\n    # child is in its own process group, manually pass kill signals\n    signal.signal(signal.SIGINT, lambda signum, frame: os.kill(child_pid, signal.SIGINT))\n    signal.signal(signal.SIGTERM, lambda signum, frame: os.kill(child_pid, signal.SIGTERM))\n\n    fcntl.fcntl(sys.stdout, fcntl.F_SETFL, fcntl.fcntl(sys.stdout, fcntl.F_GETFL) | os.O_NONBLOCK)\n\n    while True:\n      try:\n        dat = os.read(child_pty, 4096)\n      except OSError as e:\n        if e.errno == errno.EIO:\n          break\n        continue\n\n      if not dat:\n        break\n\n      try:\n        sys.stdout.write(dat.decode('utf8'))\n      except (OSError, IOError, UnicodeDecodeError):\n        pass\n\n    # os.wait() returns a tuple with the pid and a 16 bit value\n    # whose low byte is the signal number and whose high byte is the exit satus\n    exit_status = os.wait()[1] >> 8\n    os._exit(exit_status)\n"
  },
  {
    "path": "selfdrive/manager/manager.py",
    "content": "#!/usr/bin/env python3\nimport datetime\nimport os\nimport signal\nimport subprocess\nimport sys\nimport traceback\n\nimport cereal.messaging as messaging\nimport selfdrive.crash as crash\nfrom common.basedir import BASEDIR\nfrom common.params import Params, ParamKeyType\nfrom common.text_window import TextWindow\nfrom selfdrive.boardd.set_time import set_time\nfrom selfdrive.hardware import HARDWARE, PC, EON\nfrom selfdrive.manager.helpers import unblock_stdout\nfrom selfdrive.manager.process import ensure_running\nfrom selfdrive.manager.process_config import managed_processes\nfrom selfdrive.athena.registration import register, UNREGISTERED_DONGLE_ID\nfrom selfdrive.swaglog import cloudlog, add_file_handler\nfrom selfdrive.version import dirty, get_git_commit, version, origin, branch, commit, \\\n                              terms_version, training_version, comma_remote, \\\n                              get_git_branch, get_git_remote\nfrom common.dp_conf import init_params_vals\n\n\nsys.path.append(os.path.join(BASEDIR, \"pyextra\"))\n\ndef manager_init():\n\n  # update system time from panda\n  set_time(cloudlog)\n\n  params = Params()\n  params.clear_all(ParamKeyType.CLEAR_ON_MANAGER_START)\n\n  default_params = [\n    (\"CompletedTrainingVersion\", \"0\"),\n    (\"HasAcceptedTerms\", \"0\"),\n    (\"OpenpilotEnabledToggle\", \"1\"),\n    (\"EndToEndToggle\", \"0\"),\n    (\"ShowDebugUI\", \"0\"),\n    (\"SpeedLimitControl\", \"0\"),\n    (\"SpeedLimitPercOffset\", \"0\"),\n    (\"TurnSpeedControl\", \"0\"),\n    (\"TurnVisionControl\", \"0\"),\n  ]\n  if not PC:\n    default_params.append((\"LastUpdateTime\", datetime.datetime.utcnow().isoformat().encode('utf8')))\n\n  if params.get_bool(\"RecordFrontLock\"):\n    params.put_bool(\"RecordFront\", True)\n\n  # set unset params\n  for k, v in default_params:\n    if params.get(k) is None:\n      params.put(k, v)\n\n  # dp init params\n  init_params_vals(params)\n\n  # is this dashcam?\n  if os.getenv(\"PASSIVE\") is not None:\n    params.put_bool(\"Passive\", bool(int(os.getenv(\"PASSIVE\"))))\n\n  if params.get(\"Passive\") is None:\n    raise Exception(\"Passive must be set to continue\")\n\n  # Create folders needed for msgq\n  try:\n    os.mkdir(\"/dev/shm\")\n  except FileExistsError:\n    pass\n  except PermissionError:\n    print(\"WARNING: failed to make /dev/shm\")\n\n  # set version params\n  params.put(\"Version\", version)\n  params.put(\"TermsVersion\", terms_version)\n  params.put(\"TrainingVersion\", training_version)\n  params.put(\"GitCommit\", get_git_commit(default=\"\"))\n  params.put(\"GitBranch\", get_git_branch(default=\"\"))\n  params.put(\"GitRemote\", get_git_remote(default=\"\"))\n\n  # set dongle id\n  reg_res = register(show_spinner=True)\n  if reg_res:\n    dongle_id = reg_res\n  else:\n    serial = params.get(\"HardwareSerial\")\n    raise Exception(f\"Registration failed for device {serial}\")\n  os.environ['DONGLE_ID'] = dongle_id  # Needed for swaglog\n\n  if not dirty:\n    os.environ['CLEAN'] = '1'\n\n  cloudlog.bind_global(dongle_id=dongle_id, version=version, dirty=dirty,\n                       device=HARDWARE.get_device_type())\n\n  if comma_remote and not (os.getenv(\"NOLOG\") or os.getenv(\"NOCRASH\") or PC):\n    crash.init()\n  crash.bind_user(id=dongle_id)\n  crash.bind_extra(dirty=dirty, origin=origin, branch=branch, commit=commit,\n                   device=HARDWARE.get_device_type())\n\n\ndef manager_prepare():\n  for p in managed_processes.values():\n    p.prepare()\n\n\ndef manager_cleanup():\n  for p in managed_processes.values():\n    p.stop()\n\n  cloudlog.info(\"everything is dead\")\n\n\ndef manager_thread():\n  cloudlog.info(\"manager start\")\n  cloudlog.info({\"environ\": os.environ})\n\n  # save boot log\n  subprocess.call(\"./bootlog\", cwd=os.path.join(BASEDIR, \"selfdrive/loggerd\"))\n\n  params = Params()\n\n  dp_reg = params.get_bool('dp_reg')\n  dp_logger = params.get_bool('dp_logger')\n  dp_athenad = params.get_bool('dp_athenad')\n  dp_uploader = params.get_bool('dp_uploader')\n  dp_atl = params.get_bool('dp_atl')\n  dp_jetson = params.get_bool('dp_jetson')\n  dp_otisserv = params.get_bool('dp_otisserv')\n  dp_mapd = params.get_bool('dp_mapd')\n  if not params.get_bool('dp_api_custom') and dp_atl:\n    dp_reg = False\n  if not dp_reg:\n    dp_athenad = False\n    dp_uploader = False\n  # save boot log\n  if dp_logger:\n    subprocess.call(\"./bootlog\", cwd=os.path.join(BASEDIR, \"selfdrive/loggerd\"))\n\n  ignore = []\n  if dp_jetson:\n    ignore += ['dmonitoringmodeld', 'dmonitoringd']\n  if not params.get_bool('dp_dashcamd'):\n    ignore += ['dashcamd']\n  if not params.get_bool('dp_updated'):\n    ignore += ['updated']\n  if not dp_logger:\n    ignore += ['logcatd', 'loggerd', 'proclogd', 'logmessaged', 'tombstoned']\n  if not dp_athenad:\n    ignore += ['manage_athenad']\n  if not dp_athenad and not dp_uploader:\n    ignore += ['deleter']\n  if not dp_mapd:\n    ignore += ['mapd']\n  if not dp_otisserv:\n    ignore += ['otisserv']\n  if not dp_mapd and not dp_otisserv and not params.get_bool('dp_gpxd'):\n    ignore += ['gpxd']\n  if params.get(\"DongleId\", encoding='utf8') == UNREGISTERED_DONGLE_ID:\n    ignore += [\"manage_athenad\", \"uploader\"]\n  if os.getenv(\"NOBOARD\") is not None:\n    ignore.append(\"pandad\")\n  if os.getenv(\"BLOCK\") is not None:\n    ignore += os.getenv(\"BLOCK\").split(\",\")\n\n  ensure_running(managed_processes.values(), started=False, not_run=ignore)\n\n  started_prev = False\n  sm = messaging.SubMaster(['deviceState'])\n  pm = messaging.PubMaster(['managerState'])\n\n  while True:\n    sm.update()\n    not_run = ignore[:]\n\n    if sm['deviceState'].freeSpacePercent < 5:\n      not_run.append(\"loggerd\")\n\n    started = sm['deviceState'].started\n    driverview = params.get_bool(\"IsDriverViewEnabled\")\n    ensure_running(managed_processes.values(), started, driverview, not_run)\n\n    # trigger an update after going offroad\n    if started_prev and not started and 'updated' in managed_processes:\n      os.sync()\n      managed_processes['updated'].signal(signal.SIGHUP)\n\n    started_prev = started\n\n    running_list = [\"%s%s\\u001b[0m\" % (\"\\u001b[32m\" if p.proc.is_alive() else \"\\u001b[31m\", p.name)\n                    for p in managed_processes.values() if p.proc]\n    cloudlog.debug(' '.join(running_list))\n\n    # send managerState\n    msg = messaging.new_message('managerState')\n    msg.managerState.processes = [p.get_process_state_msg() for p in managed_processes.values()]\n    pm.send('managerState', msg)\n\n    # TODO: let UI handle this\n    # Exit main loop when uninstall is needed\n    if params.get_bool(\"DoUninstall\"):\n      break\n\n\ndef main():\n  prepare_only = os.getenv(\"PREPAREONLY\") is not None\n\n  manager_init()\n\n  # Start UI early so prepare can happen in the background\n  if not prepare_only:\n    managed_processes['ui'].start()\n\n  manager_prepare()\n\n  if prepare_only:\n    return\n\n  # SystemExit on sigterm\n  signal.signal(signal.SIGTERM, lambda signum, frame: sys.exit(1))\n\n  try:\n    manager_thread()\n  except Exception:\n    traceback.print_exc()\n    crash.capture_exception()\n  finally:\n    manager_cleanup()\n\n  if Params().get_bool(\"DoUninstall\"):\n    cloudlog.warning(\"uninstalling\")\n    HARDWARE.uninstall()\n\n\nif __name__ == \"__main__\":\n  unblock_stdout()\n\n  try:\n    main()\n  except Exception:\n    add_file_handler(cloudlog)\n    cloudlog.exception(\"Manager failed to start\")\n\n    # Show last 3 lines of traceback\n    error = traceback.format_exc(-3)\n    error = \"Manager failed to start\\n\\n\" + error\n    with TextWindow(error) as t:\n      t.wait_for_exit()\n\n    raise\n\n  # manual exit because we are forked\n  sys.exit(0)\n"
  },
  {
    "path": "selfdrive/manager/process.py",
    "content": "import importlib\nimport os\nimport signal\nimport time\nimport subprocess\nfrom abc import ABC, abstractmethod\nfrom multiprocessing import Process\n\nfrom setproctitle import setproctitle  # pylint: disable=no-name-in-module\n\nimport cereal.messaging as messaging\nimport selfdrive.crash as crash\nfrom common.basedir import BASEDIR\nfrom common.params import Params\nfrom common.realtime import sec_since_boot\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.hardware import HARDWARE\nfrom cereal import log\n\nWATCHDOG_FN = \"/dev/shm/wd_\"\nENABLE_WATCHDOG = os.getenv(\"NO_WATCHDOG\") is None\n\n\ndef launcher(proc):\n  try:\n    # import the process\n    mod = importlib.import_module(proc)\n\n    # rename the process\n    setproctitle(proc)\n\n    # create new context since we forked\n    messaging.context = messaging.Context()\n\n    # exec the process\n    mod.main()\n  except KeyboardInterrupt:\n    cloudlog.warning(\"child %s got SIGINT\" % proc)\n  except Exception:\n    # can't install the crash handler because sys.excepthook doesn't play nice\n    # with threads, so catch it here.\n    crash.capture_exception()\n    raise\n\n\ndef nativelauncher(pargs, cwd):\n  # exec the process\n  os.chdir(cwd)\n  os.execvp(pargs[0], pargs)\n\n\ndef join_process(process, timeout):\n  # Process().join(timeout) will hang due to a python 3 bug: https://bugs.python.org/issue28382\n  # We have to poll the exitcode instead\n  t = time.monotonic()\n  while time.monotonic() - t < timeout and process.exitcode is None:\n    time.sleep(0.001)\n\n\nclass ManagerProcess(ABC):\n  unkillable = False\n  daemon = False\n  sigkill = False\n  proc = None\n  enabled = True\n  name = \"\"\n\n  last_watchdog_time = 0\n  watchdog_max_dt = None\n  watchdog_seen = False\n  shutting_down = False\n\n  @abstractmethod\n  def prepare(self):\n    pass\n\n  @abstractmethod\n  def start(self):\n    pass\n\n  def restart(self):\n    self.stop()\n    self.start()\n\n  def check_watchdog(self, started):\n    if self.watchdog_max_dt is None or self.proc is None:\n      return\n\n    try:\n      fn = WATCHDOG_FN + str(self.proc.pid)\n      self.last_watchdog_time = int(open(fn).read())\n    except Exception:\n      pass\n\n    dt = sec_since_boot() - self.last_watchdog_time / 1e9\n\n    if dt > self.watchdog_max_dt:\n      # Only restart while offroad for now\n      if self.watchdog_seen and ENABLE_WATCHDOG:\n        cloudlog.error(f\"Watchdog timeout for {self.name} (exitcode {self.proc.exitcode}) restarting ({started=})\")\n        self.restart()\n    else:\n      self.watchdog_seen = True\n\n  def stop(self, retry=True, block=True):\n    if self.proc is None:\n      return\n\n    if self.proc.exitcode is None:\n      if not self.shutting_down:\n        cloudlog.info(f\"killing {self.name}\")\n        sig = signal.SIGKILL if self.sigkill else signal.SIGINT\n        self.signal(sig)\n        self.shutting_down = True\n\n        if not block:\n          return\n\n      join_process(self.proc, 5)\n\n      # If process failed to die send SIGKILL or reboot\n      if self.proc.exitcode is None and retry:\n        if self.unkillable:\n          cloudlog.critical(f\"unkillable process {self.name} failed to exit! rebooting in 15 if it doesn't die\")\n          join_process(self.proc, 15)\n\n          if self.proc.exitcode is None:\n            cloudlog.critical(f\"unkillable process {self.name} failed to die!\")\n            os.system(\"date >> /data/unkillable_reboot\")\n            os.sync()\n            HARDWARE.reboot()\n            raise RuntimeError\n        else:\n          cloudlog.info(f\"killing {self.name} with SIGKILL\")\n          self.signal(signal.SIGKILL)\n          self.proc.join()\n\n    ret = self.proc.exitcode\n    cloudlog.info(f\"{self.name} is dead with {ret}\")\n\n    if self.proc.exitcode is not None:\n      self.shutting_down = False\n      self.proc = None\n\n    return ret\n\n  def signal(self, sig):\n    if self.proc is None:\n      return\n\n    # Don't signal if already exited\n    if self.proc.exitcode is not None and self.proc.pid is not None:\n      return\n\n    cloudlog.info(f\"sending signal {sig} to {self.name}\")\n    os.kill(self.proc.pid, sig)\n\n  def get_process_state_msg(self):\n    state = log.ManagerState.ProcessState.new_message()\n    state.name = self.name\n    if self.proc:\n      state.running = self.proc.is_alive()\n      state.pid = self.proc.pid or 0\n      state.exitCode = self.proc.exitcode or 0\n    return state\n\n\nclass NativeProcess(ManagerProcess):\n  def __init__(self, name, cwd, cmdline, enabled=True, persistent=False, driverview=False, unkillable=False, sigkill=False, watchdog_max_dt=None):\n    self.name = name\n    self.cwd = cwd\n    self.cmdline = cmdline\n    self.enabled = enabled\n    self.persistent = persistent\n    self.driverview = driverview\n    self.unkillable = unkillable\n    self.sigkill = sigkill\n    self.watchdog_max_dt = watchdog_max_dt\n\n  def prepare(self):\n    pass\n\n  def start(self):\n    # In case we only tried a non blocking stop we need to stop it before restarting\n    if self.shutting_down:\n        self.stop()\n\n    if self.proc is not None:\n      return\n\n    cwd = os.path.join(BASEDIR, self.cwd)\n    cloudlog.info(\"starting process %s\" % self.name)\n    self.proc = Process(name=self.name, target=nativelauncher, args=(self.cmdline, cwd))\n    self.proc.start()\n    self.watchdog_seen = False\n    self.shutting_down = False\n\n\nclass PythonProcess(ManagerProcess):\n  def __init__(self, name, module, enabled=True, persistent=False, driverview=False, unkillable=False, sigkill=False, watchdog_max_dt=None):\n    self.name = name\n    self.module = module\n    self.enabled = enabled\n    self.persistent = persistent\n    self.driverview = driverview\n    self.unkillable = unkillable\n    self.sigkill = sigkill\n    self.watchdog_max_dt = watchdog_max_dt\n\n  def prepare(self):\n    if self.enabled:\n      cloudlog.info(\"preimporting %s\" % self.module)\n      importlib.import_module(self.module)\n\n  def start(self):\n    # In case we only tried a non blocking stop we need to stop it before restarting\n    if self.shutting_down:\n        self.stop()\n\n    if self.proc is not None:\n      return\n\n    cloudlog.info(\"starting python %s\" % self.module)\n    self.proc = Process(name=self.name, target=launcher, args=(self.module,))\n    self.proc.start()\n    self.watchdog_seen = False\n    self.shutting_down = False\n\n\nclass DaemonProcess(ManagerProcess):\n  \"\"\"Python process that has to stay running across manager restart.\n  This is used for athena so you don't lose SSH access when restarting manager.\"\"\"\n  def __init__(self, name, module, param_name, enabled=True):\n    self.name = name\n    self.module = module\n    self.param_name = param_name\n    self.enabled = enabled\n    self.persistent = True\n\n  def prepare(self):\n    pass\n\n  def start(self):\n    params = Params()\n    pid = params.get(self.param_name, encoding='utf-8')\n\n    if pid is not None:\n      try:\n        os.kill(int(pid), 0)\n        with open(f'/proc/{pid}/cmdline') as f:\n          if self.module in f.read():\n            # daemon is running\n            return\n      except (OSError, FileNotFoundError):\n        # process is dead\n        pass\n\n    cloudlog.info(\"starting daemon %s\" % self.name)\n    proc = subprocess.Popen(['python', '-m', self.module],  # pylint: disable=subprocess-popen-preexec-fn\n                               stdin=open('/dev/null', 'r'),\n                               stdout=open('/dev/null', 'w'),\n                               stderr=open('/dev/null', 'w'),\n                               preexec_fn=os.setpgrp)\n\n    params.put(self.param_name, str(proc.pid))\n\n  def stop(self, retry=True, block=True):\n    pass\n\n\ndef ensure_running(procs, started, driverview=False, not_run=None):\n  if not_run is None:\n    not_run = []\n\n  for p in procs:\n    if p.name in not_run:\n      p.stop(block=False)\n    elif not p.enabled:\n      p.stop(block=False)\n    elif p.persistent:\n      p.start()\n    elif p.driverview and driverview:\n      p.start()\n    elif started:\n      p.start()\n    else:\n      p.stop(block=False)\n\n    p.check_watchdog(started)\n\n"
  },
  {
    "path": "selfdrive/manager/process_config.py",
    "content": "import os\n\nfrom selfdrive.manager.process import PythonProcess, NativeProcess, DaemonProcess\nfrom selfdrive.hardware import EON, TICI, PC\n\nWEBCAM = os.getenv(\"USE_WEBCAM\") is not None\nMIPI = os.getenv(\"USE_MIPI\") is not None\n\nprocs = [\n  DaemonProcess(\"manage_athenad\", \"selfdrive.athena.manage_athenad\", \"AthenadPid\"),\n  # due to qualcomm kernel bugs SIGKILLing camerad sometimes causes page table corruption\n  NativeProcess(\"camerad\", \"selfdrive/camerad\", [\"./camerad\"], unkillable=True, driverview=True),\n  NativeProcess(\"clocksd\", \"selfdrive/clocksd\", [\"./clocksd\"]),\n  NativeProcess(\"dmonitoringmodeld\", \"selfdrive/modeld\", [\"./dmonitoringmodeld\"], enabled=not MIPI and (not PC or WEBCAM), driverview=True),\n  NativeProcess(\"logcatd\", \"selfdrive/logcatd\", [\"./logcatd\"]),\n  NativeProcess(\"loggerd\", \"selfdrive/loggerd\", [\"./loggerd\"]),\n  NativeProcess(\"modeld\", \"selfdrive/modeld\", [\"./modeld\"]),\n  NativeProcess(\"proclogd\", \"selfdrive/proclogd\", [\"./proclogd\"]),\n  NativeProcess(\"sensord\", \"selfdrive/sensord\", [\"./sensord\"], enabled=not PC and not MIPI, persistent=EON, sigkill=EON),\n  NativeProcess(\"ubloxd\", \"selfdrive/locationd\", [\"./ubloxd\"], enabled=(not PC or WEBCAM)),\n  NativeProcess(\"ui\", \"selfdrive/ui\", [\"./ui\"], persistent=True, watchdog_max_dt=(5 if TICI else None)),\n  NativeProcess(\"soundd\", \"selfdrive/ui\", [\"./soundd\"], enabled= not MIPI),\n  NativeProcess(\"locationd\", \"selfdrive/locationd\", [\"./locationd\"]),\n  NativeProcess(\"boardd\", \"selfdrive/boardd\", [\"./boardd\"], enabled=False),\n  PythonProcess(\"calibrationd\", \"selfdrive.locationd.calibrationd\"),\n  PythonProcess(\"controlsd\", \"selfdrive.controls.controlsd\"),\n  PythonProcess(\"deleter\", \"selfdrive.loggerd.deleter\", persistent=True),\n  PythonProcess(\"dmonitoringd\", \"selfdrive.monitoring.dmonitoringd\", enabled=not MIPI and (not PC or WEBCAM), driverview=True),\n  PythonProcess(\"logmessaged\", \"selfdrive.logmessaged\", persistent=True),\n  PythonProcess(\"pandad\", \"selfdrive.pandad\", persistent=True),\n  PythonProcess(\"paramsd\", \"selfdrive.locationd.paramsd\"),\n  PythonProcess(\"plannerd\", \"selfdrive.controls.plannerd\"),\n  PythonProcess(\"radard\", \"selfdrive.controls.radard\"),\n  PythonProcess(\"thermald\", \"selfdrive.thermald.thermald\", persistent=True),\n  PythonProcess(\"timezoned\", \"selfdrive.timezoned\", enabled=TICI, persistent=True),\n  PythonProcess(\"tombstoned\", \"selfdrive.tombstoned\", enabled=not PC and not MIPI, persistent=True),\n  PythonProcess(\"updated\", \"selfdrive.updated\", enabled=not PC, persistent=True),\n  PythonProcess(\"uploader\", \"selfdrive.loggerd.uploader\", enabled=not MIPI, persistent=True),\n  PythonProcess(\"mapd\", \"selfdrive.mapd.mapd\"),\n\n  # EON only\n  PythonProcess(\"rtshield\", \"selfdrive.rtshield\", enabled=EON),\n  PythonProcess(\"androidd\", \"selfdrive.hardware.eon.androidd\", enabled=EON, persistent=True),\n\n  # dp\n  PythonProcess(\"systemd\", \"selfdrive.dragonpilot.systemd\", persistent=True),\n  PythonProcess(\"gpxd\", \"selfdrive.dragonpilot.gpxd\"),\n  PythonProcess(\"otisserv\", \"selfdrive.dragonpilot.otisserv\", persistent=True),\n]\n\nmanaged_processes = {p.name: p for p in procs}\n"
  },
  {
    "path": "selfdrive/manager/test/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/manager/test/test_manager.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport signal\nimport time\nimport unittest\n\nimport selfdrive.manager.manager as manager\nfrom selfdrive.hardware import EON\nfrom selfdrive.manager.process import DaemonProcess\nfrom selfdrive.manager.process_config import managed_processes\n\nos.environ['FAKEUPLOAD'] = \"1\"\n\n# TODO: make eon fast\nMAX_STARTUP_TIME = 30 if EON else 15\nALL_PROCESSES = [p.name for p in managed_processes.values() if (type(p) is not DaemonProcess) and p.enabled and (p.name not in ['updated', 'pandad'])]\n\n\nclass TestManager(unittest.TestCase):\n  def setUp(self):\n    os.environ['PASSIVE'] = '0'\n\n  def tearDown(self):\n    manager.manager_cleanup()\n\n  def test_manager_prepare(self):\n    os.environ['PREPAREONLY'] = '1'\n    manager.main()\n\n  def test_startup_time(self):\n    for _ in range(10):\n      start = time.monotonic()\n      os.environ['PREPAREONLY'] = '1'\n      manager.main()\n      t = time.monotonic() - start\n      assert t < MAX_STARTUP_TIME, f\"startup took {t}s, expected <{MAX_STARTUP_TIME}s\"\n\n  # ensure all processes exit cleanly\n  def test_clean_exit(self):\n    manager.manager_prepare()\n\n    for p in ALL_PROCESSES:\n      managed_processes[p].start()\n\n    time.sleep(10)\n\n    for p in reversed(ALL_PROCESSES):\n      state = managed_processes[p].get_process_state_msg()\n      self.assertTrue(state.running, f\"{p} not running\")\n\n      exit_code = managed_processes[p].stop(retry=False)\n      if (p == 'ui') or (EON and p == 'logcatd'):\n        # TODO: make Qt UI exit gracefully\n        continue\n\n      # Make sure the process is actually dead\n      managed_processes[p].stop()\n\n      # TODO: interrupted blocking read exits with 1 in cereal. use a more unique return code\n      exit_codes = [0, 1]\n      if managed_processes[p].sigkill:\n        exit_codes = [-signal.SIGKILL]\n      assert exit_code in exit_codes, f\"{p} died with {exit_code}\"\n\n\nif __name__ == \"__main__\":\n  unittest.main()\n"
  },
  {
    "path": "selfdrive/manager.py",
    "content": ""
  },
  {
    "path": "selfdrive/mapd/README.md",
    "content": "# MapD\nThe OpenStreetMap based speed logical by the [move-fast team](https://github.com/move-fast)\n\n[opsline](https://github.com/move-fast/opspline) which is the pkg needed to run OSM on EON/C2 by [move-fast team](https://github.com/move-fast).\nThe c3 uses regular SciPy. We upload gps tracks to improve OSM mapping. Better mapping better osm experience you will have.\n\n## customization\nTo change the speed offset go to `/selfdrive/controls/lib/speed_limit_controller.py` L18,19. `LIMIT_PERC_OFFSET_V` is % you add your set speed. `_LIMIT_PERC_OFFSET_BP` is the speed in m/s you to detect the change at. For example, you want to go 33mph in speedzone of 30mph zone `LIMIT_PERC_OFFSET_V = [0.1]` adds 10% more to based and `_LIMIT_PERC_OFFSET_BP = [13.4]` is 13.4 m/s(30mph) add those together and you get a set speed of 33mph. You may also change the breaking to make it brake earlier or slower by editing `selfdrive/controls/lib/drive_helpers.py` L23-L28.\n\nOther controls can be customized at `/selfdrive/controls/lib/turn_speed_controller.py` and `/selfdrive/controls/lib/vision_turn_controller.py`.\n\n\n\n\n\n\n  © OpenStreetMap contributors\n"
  },
  {
    "path": "selfdrive/mapd/config.py",
    "content": "# Map query config\n\nQUERY_RADIUS = 3000  # mts. Radius to use on OSM data queries.\nMIN_DISTANCE_FOR_NEW_QUERY = 1000  # mts. Minimum distance to query area edge before issuing a new query.\nFULL_STOP_MAX_SPEED = 1.39  # m/s Max speed for considering car is stopped.\nLOOK_AHEAD_HORIZON_TIME = 15.  # s. Time horizon for look ahead of turn speed sections to provide on liveMapData msg.\nLANE_WIDTH = 3.7  # Lane width estimate. Used for detecting departures from way.\n"
  },
  {
    "path": "selfdrive/mapd/lib/NodesData.py",
    "content": "import numpy as np\nfrom enum import Enum\nfrom selfdrive.mapd.lib.geo import DIRECTION, R, vectors\n\nfrom selfdrive.hardware import EON\n\nif EON:\n  from opspline import splev, splprep  # pylint: disable=E0401\nelse:\n  from scipy.interpolate import splev, splprep\n\n\n_TURN_CURVATURE_THRESHOLD = 0.002  # 1/mts. A curvature over this value will generate a speed limit section.\n_MAX_LAT_ACC = 2.3  # Maximum lateral acceleration in turns.\n_SPLINE_EVAL_STEP = 5  # mts for spline evaluation for curvature calculation\n_MIN_SPEED_SECTION_LENGHT = 100.  # mts. Sections below this value will not be split in smaller sections.\n_MAX_CURV_DEVIATION_FOR_SPLIT = 2.  # Split a speed section if the max curvature deviates from mean by this factor.\n_MAX_CURV_SPLIT_ARC_ANGLE = 90.  # degrees. Arc section to split into new speed section around max curvature.\n_MIN_NODE_DISTANCE = 50.  # mts. Minimum distance between nodes for spline evaluation. Data is enhanced if not met.\n_ADDED_NODES_DIST = 15.  # mts. Distance between added nodes when data is enhanced for spline evaluation.\n_DIVERTION_SEARCH_RANGE = [-200., 50.]  # mt. Range of distance to current location for divertion search.\n\n\ndef nodes_raw_data_array_for_wr(wr, drop_last=False):\n  \"\"\"Provides an array of raw node data (id, lat, lon, speed_limit) for all nodes in way relation\n  \"\"\"\n  sl = wr.speed_limit\n  data = np.array([(n.id, n.lat, n.lon, sl) for n in wr.way.nodes], dtype=float)\n\n  # reverse the order if way direction is backwards\n  if wr.direction == DIRECTION.BACKWARD:\n    data = np.flip(data, axis=0)\n\n  # drop last if requested\n  return data[:-1] if drop_last else data\n\n\ndef node_calculations(points):\n  \"\"\"Provides node calculations based on an array of (lat, lon) points in radians.\n     points is a (N x 1) array where N >= 3\n  \"\"\"\n  if len(points) < 3:\n    raise(IndexError)\n\n  # Get the vector representation of node points in cartesian plane.\n  # (N-1, 2) array. Not including (0., 0.)\n  v = vectors(points) * R\n\n  # Calculate the vector magnitudes (or distance)\n  # (N-1, 1) array. No distance for v[-1]\n  d = np.linalg.norm(v, axis=1)\n\n  # Calculate the bearing (from true north clockwise) for every node.\n  # (N-1, 1) array. No bearing for v[-1]\n  b = np.arctan2(v[:, 0], v[:, 1])\n\n  # Add origin to vector space. (i.e first node in list)\n  v = np.concatenate(([[0., 0.]], v))\n\n  # Provide distance to previous node and distance to next node\n  dp = np.concatenate(([0.], d))\n  dn = np.concatenate((d, [0.]))\n\n  # Provide cumulative distance on route\n  dr = np.cumsum(dp, axis=0)\n\n  # Bearing of last node should keep bearing from previous.\n  b = np.concatenate((b, [b[-1]]))\n\n  return v, dp, dn, dr, b\n\n\ndef spline_curvature_calculations(vect, dist_prev):\n  \"\"\"Provides an array of curvatures and its distances by applying a spline interpolation\n  to the path described by the nodes data.\n  \"\"\"\n  # We need to artificially enhance the data before applying spline interpolation to avoid getting\n  # inexistent curvature values close to irregularities on the road when the resolution of nodes data\n  # approaching the irregularity is low.\n\n  # - Find indexes where dist_prev is greater than threshold\n  too_far_idxs = np.nonzero(dist_prev >= _MIN_NODE_DISTANCE)[0]\n\n  # - Traversing in reverse order, enhance data by adding points at the found indexes.\n  for idx in too_far_idxs[::-1]:\n    dp = dist_prev[idx]  # distance of vector that needs to be replaced by higher resolution vectors.\n    n = int(np.ceil(dp / _ADDED_NODES_DIST))  # number of vectors that need to be added.\n    new_v = vect[idx, :] / n  # new relative vector to insert.\n    vect = np.delete(vect, idx, axis=0)  # remove the relative vector to be replaced by the insertion of new vectors.\n    vect = np.insert(vect, [idx] * n, [new_v] * n, axis=0)  # insert n new relative vectors\n\n  # Data is now enhanced, we can proceed with curvature evaluation.\n  # - Create cumulative arrays for distance traveled and vector (x, y)\n  ds = np.cumsum(dist_prev, axis=0)\n  vs = np.cumsum(vect, axis=0)\n\n  # - spline interpolation\n  tck, u = splprep([vs[:, 0], vs[:, 1]])\n\n  # - evaluate every _SPLINE_EVAL_STEP mts.\n  n = max(int(ds[-1] / _SPLINE_EVAL_STEP), len(u))\n  unew = np.arange(0, n + 1) / n\n\n  # - get derivatives\n  d1 = splev(unew, tck, der=1)\n  d2 = splev(unew, tck, der=2)\n\n  # - calculate curvatures\n  num = d1[0] * d2[1] - d1[1] * d2[0]\n  den = (d1[0]**2 + d1[1]**2)**(1.5)\n  curv = num / den\n  curv_ds = unew * ds[-1]\n\n  return curv, curv_ds\n\n\ndef speed_section(curv_sec):\n  \"\"\"Map curvature section data into turn speed sections data.\n    Returns: [section start distance, section end distance, speed limit based on max curvature, sing of curvature]\n  \"\"\"\n  max_curv_idx = np.argmax(curv_sec[:, 0])\n  start = np.amin(curv_sec[:, 2])\n  end = np.amax(curv_sec[:, 2])\n\n  return np.array([start, end, np.sqrt(_MAX_LAT_ACC / curv_sec[max_curv_idx, 0]), curv_sec[max_curv_idx, 1]])\n\n\ndef split_speed_section_by_sign(curv_sec):\n  \"\"\"Will split the given curvature section in subsections if there is a change of sign on the curvature value\n  in the section.\n  \"\"\"\n  # Find the indexes where the curvatures change signs (if any).\n  c_idx = np.nonzero(np.diff(curv_sec[:, 1]))[0] + 1\n\n  # Split section base on change of sign.\n  return np.split(curv_sec, c_idx)\n\n\ndef split_speed_section_by_curv_degree(curv_sec):\n  \"\"\"Will split the given curvature section in subsections as to isolate peaks of turn with substantially\n  higher curvature values. This will aid on preventing having very long turn sections with low speed limit\n  that is only really necessary for a small region of the section.\n  \"\"\"\n  # Only consider spliting a section if long enough.\n  lenght = curv_sec[-1, 2] - curv_sec[0, 2]\n  if lenght <= _MIN_SPEED_SECTION_LENGHT:\n    return [curv_sec]\n\n  # Only split if max curvature deviates substantially from mean curvature.\n  max_curv_idx = np.argmax(curv_sec[:, 0])\n  max_curv = curv_sec[max_curv_idx, 0]\n  mean_curv = np.mean(curv_sec[:, 0])\n  if max_curv / mean_curv <= _MAX_CURV_DEVIATION_FOR_SPLIT:\n    return [curv_sec]\n\n  # Calcualate where to split as to isolate a curve section around the max curvature peak.\n  arc_side = (np.radians(_MAX_CURV_SPLIT_ARC_ANGLE) / max_curv) / 2.\n  arc_side_idx_lenght = int(np.ceil(arc_side / _SPLINE_EVAL_STEP))\n  split_idxs = [max_curv_idx - arc_side_idx_lenght, max_curv_idx + arc_side_idx_lenght]\n  split_idxs = list(filter(lambda idx: idx > 0 and idx < len(curv_sec) - 1, split_idxs))\n\n  # If the arc section to split extendes outside the section, then no need to split.\n  if len(split_idxs) == 0:\n    return [curv_sec]\n\n  # Create the splits and split the resulting sections recursevly.\n  splits = [split_speed_section_by_curv_degree(cs) for cs in np.split(curv_sec, split_idxs)]\n\n  # Flatten the results and return the new list of curvature sections.\n  curv_secs = [cs for split in splits for cs in split]\n  return curv_secs\n\n\ndef speed_limits_for_curvatures_data(curv, dist):\n  \"\"\"Provides the calculations for the speed limits from the curvatures array and distances,\n    by providing distances to curvature sections and correspoinding speed limit values as well as\n    curvature direction/sign.\n  \"\"\"\n  # Prepare a data array for processing with absolute curvature values, curvature sign and distances.\n  curv_abs = np.abs(curv)\n  data = np.column_stack((curv_abs, np.sign(curv), dist))\n\n  # Find where curvatures overshoot turn curvature threshold and define as section\n  is_section = curv_abs >= _TURN_CURVATURE_THRESHOLD\n\n  # Find the indexes where the sections start and end. i.e. change indexes.\n  c_idx = np.nonzero(np.diff(is_section))[0] + 1\n\n  # Create independent arrays for each split section base on change indexes.\n  splits = np.array(np.split(data, c_idx), dtype=object)\n\n  # Filter the splits to keep only the curvature section arrays by getting the odd or even split arrays depending\n  # on whether the first split is a curvature split or not.\n  curv_sec_idxs = np.arange(0 if is_section[0] else 1, len(splits), 2, dtype=int)\n  curv_secs = splits[curv_sec_idxs]\n\n  # Further split the curv sections by sign change\n  sub_secs = [split_speed_section_by_sign(cs) for cs in curv_secs]\n  curv_secs = [cs for sub_sec in sub_secs for cs in sub_sec]\n\n  # Further split the curv sections by degree of curvature\n  sub_secs = [split_speed_section_by_curv_degree(cs) for cs in curv_secs]\n  curv_secs = [cs for sub_sec in sub_secs for cs in sub_sec]\n\n  # Return an array where each row represents a turn speed limit section.\n  # [start, end, speed_limit, curvature_sign]\n  return np.array([speed_section(cs) for cs in curv_secs])\n\ndef is_wr_a_valid_divertion_from_node(wr, node_id, wr_ids):\n  \"\"\"\n  Evaluates if the way relation `wr` is a valid divertion from node with id `node_id`.\n  A valid divertion is a way relation with an edge node with the given `node_id` that is not already included\n  in the list of way relations in the route (`wr_ids`) and that can be travaled in the direction as if starting \n  from node with id `node_id`\n  \"\"\"\n  if wr.id in wr_ids:\n    return False\n  wr.update_direction_from_starting_node(node_id)\n  return not wr.is_prohibited\n\n\nclass SpeedLimitSection():\n  \"\"\"And object representing a speed limited road section ahead.\n  provides the start and end distance and the speed limit value\n  \"\"\"\n  def __init__(self, start, end, value):\n    self.start = start\n    self.end = end\n    self.value = value\n\n  def __repr__(self):\n    return f'from: {self.start}, to: {self.end}, limit: {self.value}'\n\n\nclass TurnSpeedLimitSection(SpeedLimitSection):\n  def __init__(self, start, end, value, sign):\n      super().__init__(start, end, value)\n      self.curv_sign = sign\n\n  def __repr__(self):\n    return f'{super().__repr__()}, sign: {self.curv_sign}'\n\n\nclass NodeDataIdx(Enum):\n  \"\"\"Column index for data elements on NodesData underlying data store.\n  \"\"\"\n  node_id = 0\n  lat = 1\n  lon = 2\n  speed_limit = 3\n  x = 4             # x value of cartesian vector representing the section between last node and this node.\n  y = 5             # y value of cartesian vector representing the section between last node and this node.\n  dist_prev = 6     # distance to previous node.\n  dist_next = 7     # distance to next node\n  dist_route = 8    # cumulative distance on route\n  bearing = 9       # bearing of the vector departing from this node.\n\n\nclass NodesData:\n  \"\"\"Container for the list of node data from a ordered list of way relations to be used in a Route\n  \"\"\"\n  def __init__(self, way_relations, wr_index):\n    self._nodes_data = np.array([])\n    self._divertions = [[]]\n    self._curvature_speed_sections_data = np.array([])\n\n    way_count = len(way_relations)\n    if way_count == 0:\n      return\n\n    # We want all the nodes from the last way section\n    nodes_data = nodes_raw_data_array_for_wr(way_relations[-1])\n\n    # For the ways before the last in the route we want all the nodes but the last, as that one is the first on\n    # the next section. Collect them, append last way node data and concatenate the numpy arrays.\n    if way_count > 1:\n      wrs_data = tuple([nodes_raw_data_array_for_wr(wr, drop_last=True) for wr in way_relations[:-1]])\n      wrs_data += (nodes_data,)\n      nodes_data = np.concatenate(wrs_data)\n\n    # Get a subarray with lat, lon to compute the remaining node values.\n    lat_lon_array = nodes_data[:, [1, 2]]\n    points = np.radians(lat_lon_array)\n    # Ensure we have more than 3 points, if not calculations are not possible.\n    if len(points) <= 3:\n      return\n    vect, dist_prev, dist_next, dist_route, bearing = node_calculations(points)\n\n    # append calculations to nodes_data\n    # nodes_data structure: [id, lat, lon, speed_limit, x, y, dist_prev, dist_next, dist_route, bearing]\n    self._nodes_data = np.column_stack((nodes_data, vect, dist_prev, dist_next, dist_route, bearing))\n\n    # Build route divertion options data from the wr_index.\n    wr_ids = [wr.id for wr in way_relations]\n    self._divertions = [[wr for wr in wr_index.way_relations_with_edge_node_id(node_id)\n                        if is_wr_a_valid_divertion_from_node(wr, node_id, wr_ids)]\n                        for node_id in nodes_data[:, 0]]\n\n    # Store calculcations for curvature sections speed limits. We need more than 3 points to be able to process.\n    # _curvature_speed_sections_data structure: [dist_start, dist_stop, speed_limits, curv_sign]\n    if len(vect) > 3:\n      curv, curv_ds = spline_curvature_calculations(vect, dist_prev)\n      self._curvature_speed_sections_data = speed_limits_for_curvatures_data(curv, curv_ds)\n\n  @property\n  def count(self):\n    return len(self._nodes_data)\n\n  def get(self, node_data_idx):\n    \"\"\"Returns the array containing all the elements of a specific NodeDataIdx type.\n    \"\"\"\n    if len(self._nodes_data) == 0 or node_data_idx.value >= self._nodes_data.shape[1]:\n      return np.array([])\n\n    return self._nodes_data[:, node_data_idx.value]\n\n  def speed_limits_ahead(self, ahead_idx, distance_to_node_ahead):\n    \"\"\"Returns and array of SpeedLimitSection objects for the actual route ahead of current location\n    \"\"\"\n    if len(self._nodes_data) == 0 or ahead_idx is None:\n      return []\n\n    # Find the cumulative distances where speed limit changes. Build Speed limit sections for those.\n    dist = np.concatenate(([distance_to_node_ahead], self.get(NodeDataIdx.dist_next)[ahead_idx:]))\n    dist = np.cumsum(dist, axis=0)\n    sl = self.get(NodeDataIdx.speed_limit)[ahead_idx - 1:]\n    sl_next = np.concatenate((sl[1:], [0.]))\n\n    # Create a boolean mask where speed limit changes and filter values\n    sl_change = sl != sl_next\n    distances = dist[sl_change]\n    speed_limits = sl[sl_change]\n\n    # Create speed limits sections combining all continious nodes that have same speed limit value.\n    start = 0.\n    limits_ahead = []\n    for idx, end in enumerate(distances):\n      limits_ahead.append(SpeedLimitSection(start, end, speed_limits[idx]))\n      start = end\n\n    return limits_ahead\n\n  def distance_to_end(self, ahead_idx, distance_to_node_ahead):\n    if len(self._nodes_data) == 0 or ahead_idx is None:\n      return None\n\n    return np.sum(np.concatenate(([distance_to_node_ahead], self.get(NodeDataIdx.dist_next)[ahead_idx:])))\n\n  def curvatures_speed_limit_sections_ahead(self, ahead_idx, distance_to_node_ahead):\n    \"\"\"Returns and array of TurnSpeedLimitSection objects for the actual route ahead of current location for\n       speed limit sections due to curvatures in the road.\n    \"\"\"\n    if len(self._curvature_speed_sections_data) == 0 or ahead_idx is None:\n      return []\n\n    # Find the current distance traveled so far on the route.\n    dist_curr = self.get(NodeDataIdx.dist_route)[ahead_idx] - distance_to_node_ahead\n\n    # Filter the sections to get only those where the stop distance is ahead of current.\n    sec_filter = self._curvature_speed_sections_data[:, 1] > dist_curr\n    data = self._curvature_speed_sections_data[sec_filter]\n\n    # Offset distances to current distance.\n    data[:, [0, 1]] -= dist_curr\n\n    # Create speed limits sections\n    limits_ahead = [TurnSpeedLimitSection(max(0., d[0]), d[1], d[2], d[3]) for d in data]\n\n    return limits_ahead\n\n  def possible_divertions(self, ahead_idx, distance_to_node_ahead):\n    \"\"\" Returns and array with the way relations the route could possible divert to by finding\n        the alternative way divertions on the nodes in the vicinity of the current location.\n    \"\"\"\n    if len(self._nodes_data) == 0 or ahead_idx is None:\n      return []\n\n    dist_route = self.get(NodeDataIdx.dist_route)\n    rel_dist = dist_route - dist_route[ahead_idx] + distance_to_node_ahead\n    valid_idxs = np.nonzero(np.logical_and(rel_dist >= _DIVERTION_SEARCH_RANGE[0],\n                            rel_dist <= _DIVERTION_SEARCH_RANGE[1]))[0]\n    valid_divertions = [self._divertions[i] for i in valid_idxs]\n\n    return [wr for wrs in valid_divertions for wr in wrs]  # flatten.\n\n  def distance_to_node(self, node_id, ahead_idx, distance_to_node_ahead):\n    \"\"\"\n    Provides the distance to a specific node in the route identified by `node_id` in reference to the node ahead\n    (`ahead_idx`) and the distance from current location to the node ahead (`distance_to_node_ahead`).\n    \"\"\"\n    node_ids = self.get(NodeDataIdx.node_id)\n    node_idxs = np.nonzero(node_ids == node_id)[0]\n    if len(self._nodes_data) == 0 or ahead_idx is None or len(node_idxs) == 0:\n      return None\n\n    return self.get(NodeDataIdx.dist_route)[node_idxs[0]] - self.get(NodeDataIdx.dist_route)[ahead_idx] + \\\n      distance_to_node_ahead\n"
  },
  {
    "path": "selfdrive/mapd/lib/Route.py",
    "content": "from selfdrive.mapd.lib.NodesData import NodesData, NodeDataIdx\nfrom selfdrive.mapd.config import QUERY_RADIUS\nfrom selfdrive.mapd.lib.geo import ref_vectors, R, distance_to_points\nfrom itertools import compress\nimport numpy as np\n\n\n_ACCEPTABLE_BEARING_DELTA_COSINE = -0.7  # Continuation paths with a bearing of 180 +/- 45 degrees.\n_MAX_ALLOWED_BEARING_DELTA_COSINE_AT_EDGE = -0.3420  # bearing delta at route edge must be 180 +/- 70 degrees.\n_MAP_DATA_EDGE_DISTANCE = 50  # mts. Consider edge of map data from this distance to edge of query radius.\n\n\nclass Route():\n  \"\"\"A set of consecutive way relations forming a default driving route.\n  \"\"\"\n  def __init__(self, current, wr_index, way_collection_id, query_center):\n    \"\"\"Create a Route object from a given `wr_index` (Way relation index)\n\n    Args:\n        current (WayRelation): The Way Relation that is currently located. It must be active.\n        wr_index (WayRelationIndex): The indexes of WayRelations by node id.\n        way_collection_id (UUID): The id of the Way Collection that created this Route.\n        query_center (Numpy Array): lat, lon] numpy array in radians indicating the center of the data query.\n    \"\"\"\n    self.way_collection_id = way_collection_id\n    self._ordered_way_relations = []\n    self._nodes_data = None\n    self._reset()\n\n    # An active current way is needed to be able to build a route\n    if not current.active:\n      return\n\n    # Build the route by finding iteratavely the best matching ways continuing after the end of the\n    # current (last_wr) way. Use the index to find the continuation posibilities on each iteration.\n    last_wr = current\n    ordered_way_ids = []\n    split_wrs = []\n    while True:\n      # - Append current element to the route list of ordered way relations.\n      self._ordered_way_relations.append(last_wr)\n      ordered_way_ids.append(last_wr.id)\n\n      # - Get the id of the node at the end of the way and then fetch the way relations that share the end node id.\n      last_node_id = last_wr.last_node.id\n      way_relations = wr_index.way_relations_with_edge_node_id(last_node_id)\n\n      # - Add split way relations when necessary and remove parent way relations.\n      split_wrs_to_add = [wr for wr in split_wrs if last_node_id in wr.edge_nodes_ids]\n      way_relations.extend(split_wrs_to_add)\n      parent_ids = [wr.parent_wr_id for wr in split_wrs_to_add]\n      way_relations = [wr for wr in way_relations if wr.id not in parent_ids]\n\n      # - If no more way_relations than last_wr, we have to check if we join another wr on an internal node, and\n      # if we do, we replace such way relation with the split of it and continue.\n      if len(way_relations) == 1:\n        way_relations = wr_index.way_relations_with_node_id(last_node_id)\n        # If no more way_relations than last_wr, we got to the end.\n        if len(way_relations) == 1:\n          break\n\n        # If we join a wr on an internal node, then we artificially split the wr in two and pass both wrs as\n        # candidates to the wr selection code below.\n        wr_to_split = [wr for wr in way_relations if wr is not last_wr][0]\n        next_split_way_id = -len(split_wrs) - 1  # Keep split wrs ids unique on Route\n        new_wrs = wr_to_split.split(last_node_id, [next_split_way_id, next_split_way_id - 1])\n        # If it could not be splited, we are done.\n        if len(new_wrs) != 2:\n          break\n\n        # Replace the original way relation for the splitted version on way_relations and track splited wrs.\n        split_wrs.extend(new_wrs)\n        way_relations.remove(wr_to_split)\n        way_relations.extend(new_wrs)\n\n      # - Get the coordinates for the edge node and build the array of coordinates for the nodes before the edge node\n      # on each of the common way relations, then get the vectors in cartesian plane for the end sections of each way.\n      ref_point = last_wr.last_node_coordinates\n      points = np.array([wr.node_before_edge_coordinates(last_node_id) for wr in way_relations])\n      v = ref_vectors(ref_point, points) * R\n\n      # - Calculate the bearing (from true north clockwise) for every end section of each way.\n      b = np.arctan2(v[:, 0], v[:, 1])\n\n      # - Find index of las_wr section and calculate deltas of bearings to the other sections.\n      last_wr_idx = way_relations.index(last_wr)\n      b_ref = b[last_wr_idx]\n      delta = b - b_ref\n\n      # - Update the direction of the possible route continuation ways as starting from last_node_id.\n      # Make sure to exclude any ways already included in the ordered list as to not modify direction when there\n      # are looping roads (like roundabouts). A way will never be included twice in a route anyway.\n      for wr in way_relations:\n        if wr.id not in ordered_way_ids:\n          wr.update_direction_from_starting_node(last_node_id)\n\n      # - Filter the possible route continuation way relations:\n      #   - exclude any way already added to the ordered list.\n      #   - exclude all way relations that are prohibited due to traffic direction.\n      mask = [wr.id not in ordered_way_ids and not wr.is_prohibited for wr in way_relations]\n      way_relations = list(compress(way_relations, mask))\n      delta = delta[mask]\n\n      # if no options left, we got to the end.\n      if len(way_relations) == 0:\n        break\n\n      # - The cosine of the bearing delta will aid us in choosing the way that continues. The cosine is\n      # minimum (-1) for a perfect straight continuation as delta would be pi or -pi.\n      cos_delta = np.cos(delta)\n\n      def pick_best_idx(cos_delta):\n        \"\"\"Selects the best index on `cos_delta` array for a way that continues the route.\n        In principle we want to choose the way that continues as straight as possible.\n        Bue we need to make sure that if there are 2 or more ways continuing relatively straight, then we\n        need to disambiguate, either by matching the `ref` or `name` value of the continuing way with the\n        last way selected.\n        This can prevent cases where the chosen route could be for instance an exit ramp of a way due to the fact\n        that the ramp has a better match on bearing to previous way. We choose to stay on the road with the same `ref`\n        or `name` value if available.\n        If there is no ambiguity or there are no `name` or `ref` values to disambiguate, then we pick the one with\n        the straightest following direction.\n        \"\"\"\n        # Find the indexes of the cosine of the deltas that are considered straight enough to continue.\n        idxs = np.nonzero(cos_delta < _ACCEPTABLE_BEARING_DELTA_COSINE)[0]\n\n        # If no amiguity or no way to break it, just return the straightest line.\n        if len(idxs) <= 1 or (last_wr.ref is None and last_wr.name is None):\n          # The section with the best continuation is the one with a bearing delta closest to pi. This is equivalent\n          # to taking the one with the smallest cosine of the bearing delta, as cosine is minimum (-1) on both pi\n          # and -pi.\n          return np.argmin(cos_delta)\n\n        wrs = [way_relations[idx] for idx in idxs]\n\n        # If we find a continuation way with the same reference we just choose it.\n        refs = list(map(lambda wr: wr.ref, wrs))\n        if last_wr.ref is not None:\n          idx = next((idx for idx, ref in enumerate(refs) if ref == last_wr.ref), None)\n          if idx is not None:\n            return idxs[idx]\n\n        # If we find a continuation way with the same name we just choose it.\n        names = list(map(lambda wr: wr.name, wrs))\n        if last_wr.name is not None:\n          idx = next((idx for idx, name in enumerate(names) if name == last_wr.name), None)\n          if idx is not None:\n            return idxs[idx]\n\n        # We did not manage to deambiguate, choose straightest path.\n        return np.argmin(cos_delta)\n\n      # Get the index of the continuation way.\n      best_idx = pick_best_idx(cos_delta)\n\n      # - Make sure to not select as route continuation a way that turns too much if we are close to the border of\n      # map data queried. This is to avoid building a route that takes a sharp turn just because we do not have the\n      # data for the way that actually continues straight.\n      if cos_delta[best_idx] > _MAX_ALLOWED_BEARING_DELTA_COSINE_AT_EDGE:\n        dist_to_center = distance_to_points(query_center, np.array([ref_point]))[0]\n        if dist_to_center > QUERY_RADIUS - _MAP_DATA_EDGE_DISTANCE:\n          break\n\n      # - Select next way.\n      last_wr = way_relations[best_idx]\n\n    # Build the node data from the ordered list of way relations\n    self._nodes_data = NodesData(self._ordered_way_relations, wr_index)\n\n    # Locate where we are in the route node list.\n    self._locate()\n\n  def __repr__(self):\n    count = self._nodes_data.count if self._nodes_data is not None else None\n    return f'Route: {self.way_collection_id}, idx ahead: {self._ahead_idx} of {count}'\n\n  def _reset(self):\n    self._limits_ahead = None\n    self._cuvature_limits_ahead = None\n    self._curvatures_ahead = None\n    self._ahead_idx = None\n    self._distance_to_node_ahead = None\n\n  @property\n  def located(self):\n    return self._ahead_idx is not None\n\n  def _locate(self):\n    \"\"\"Will resolve the index in the nodes_data list for the node ahead of the current location.\n       It updates as well the distance from the current location to the node ahead.\n    \"\"\"\n    current = self.current_wr\n    if current is None:\n      return\n\n    node_ahead_id = current.node_ahead.id\n    self._distance_to_node_ahead = current.distance_to_node_ahead\n    start_idx = self._ahead_idx if self._ahead_idx is not None else 1\n    self._ahead_idx = None\n\n    ids = self._nodes_data.get(NodeDataIdx.node_id)\n    for idx in range(start_idx, len(ids)):\n      if ids[idx] == node_ahead_id:\n        self._ahead_idx = idx\n        break\n\n  @property\n  def current_wr(self):\n    return self._ordered_way_relations[0] if len(self._ordered_way_relations) else None\n\n  def update(self, location_rad, bearing_rad, location_stdev):\n    \"\"\"Will update the route structure based on the given `location_rad` and `bearing_rad` assuming progress on the\n    route on the original direction. If direction has changed or active point on the route can not be found, the route\n    will become invalid.\n    \"\"\"\n    if len(self._ordered_way_relations) == 0 or location_rad is None or bearing_rad is None:\n      return\n\n    # Skip if no update on location or bearing.\n    if np.array_equal(self.current_wr.location_rad, location_rad) and self.current_wr.bearing_rad == bearing_rad:\n      return\n\n    # Transverse the way relations on the actual order until we find an active one. From there, rebuild the route\n    # with the way relations remaining ahead.\n    for idx, wr in enumerate(self._ordered_way_relations):\n      active_direction = wr.direction\n      wr.update(location_rad, bearing_rad, location_stdev)\n\n      if not wr.active:\n        continue\n\n      if wr.direction != active_direction:\n        # Driving direction on the route has changed. stop.\n        break\n\n      # We have now the current wr. Repopulate from here till the end and locate\n      self._ordered_way_relations = self._ordered_way_relations[idx:]\n      self._reset()\n      self._locate()\n\n      # If the active way is diverting, check whether there are posibilities to divert from the route in the\n      # vecinity of the current location. If there are possibilities, then stop here to loose the route as we are\n      # most likely driving away. If there are no possibilites, then stick to the route as the diversion is probably\n      # just a matter of GPS accuracy. (It can happen after driving under a bridge)\n      if wr.diverting and len(self._nodes_data.possible_divertions(self._ahead_idx, self._distance_to_node_ahead)) > 0:\n        break\n\n      # The current location in route is valid, return.\n      return\n\n    # if we got here, there is no new active way relation or driving direction has changed. Reset.\n    self._reset()\n\n  @property\n  def speed_limits_ahead(self):\n    \"\"\"Returns and array of SpeedLimitSection objects for the actual route ahead of current location\n    \"\"\"\n    if self._limits_ahead is not None:\n      return self._limits_ahead\n\n    if self._nodes_data is None or self._ahead_idx is None:\n      return []\n\n    self._limits_ahead = self._nodes_data.speed_limits_ahead(self._ahead_idx, self._distance_to_node_ahead)\n    return self._limits_ahead\n\n  @property\n  def curvature_speed_limits_ahead(self):\n    \"\"\"Returns and array of TurnSpeedLimitSection objects for the actual route ahead of current location due\n    to curvatures\n    \"\"\"\n    if self._cuvature_limits_ahead is not None:\n      return self._cuvature_limits_ahead\n\n    if self._nodes_data is None or self._ahead_idx is None:\n      return []\n\n    self._cuvature_limits_ahead = self._nodes_data. \\\n      curvatures_speed_limit_sections_ahead(self._ahead_idx, self._distance_to_node_ahead)\n\n    return self._cuvature_limits_ahead\n\n  @property\n  def current_speed_limit(self):\n    if not self.located:\n      return None\n\n    limits_ahead = self.speed_limits_ahead\n    if len(limits_ahead) == 0 or limits_ahead[0].start != 0:\n      return None\n\n    return limits_ahead[0].value\n\n  @property\n  def current_curvature_speed_limit_section(self):\n    if not self.located:\n      return None\n\n    limits_ahead = self.curvature_speed_limits_ahead\n    if len(limits_ahead) == 0 or limits_ahead[0].start != 0:\n      return None\n\n    return limits_ahead[0]\n\n  @property\n  def next_speed_limit_section(self):\n    if not self.located:\n      return None\n\n    limits_ahead = self.speed_limits_ahead\n    if len(limits_ahead) == 0:\n      return None\n\n    # Find the first section that does not start in 0. i.e. the next section\n    for section in limits_ahead:\n      if section.start > 0:\n        return section\n\n    return None\n\n  def next_curvature_speed_limit_sections(self, horizon_mts):\n    if not self.located:\n      return []\n\n    # Provide the curvature speed sections that start ahead (> 0) and up to horizon\n    return list(filter(lambda la: la.start > 0 and la.start <= horizon_mts, self.curvature_speed_limits_ahead))\n\n  @property\n  def distance_to_end(self):\n    if not self.located:\n      return None\n\n    return self._nodes_data.distance_to_end(self._ahead_idx, self._distance_to_node_ahead)\n\n  @property\n  def current_road_name(self):\n    return self.current_wr.road_name if self.located else None\n"
  },
  {
    "path": "selfdrive/mapd/lib/WayCollection.py",
    "content": "from selfdrive.mapd.lib.WayRelation import WayRelation\nfrom selfdrive.mapd.lib.WayRelationIndex import WayRelationIndex\nfrom selfdrive.mapd.lib.Route import Route\nfrom selfdrive.mapd.config import LANE_WIDTH\nimport uuid\n\n\n_ACCEPTABLE_BEARING_DELTA_IND = 0.7071067811865475  # sin(pi/4) | 45 degrees acceptable bearing delta\n\n\nclass WayCollection():\n  \"\"\"A collection of WayRelations to use for maps data analysis.\n  \"\"\"\n  def __init__(self, ways, query_center):\n    \"\"\"Creates a WayCollection with a set of OSM way objects.\n\n    Args:\n        ways (Array): Collection of Way objects fetched from OSM in a radius around `query_center`\n        query_center (Numpy Array): [lat, lon] numpy array in radians indicating the center of the data query.\n    \"\"\"\n    self.id = uuid.uuid4()\n    self.way_relations = [WayRelation(way) for way in ways]\n    self.query_center = query_center\n\n    self.wr_index = WayRelationIndex(self.way_relations)\n\n  def get_route(self, location_rad, bearing_rad, location_stdev):\n    \"\"\"Provides the best route found in the way collection based on current location and bearing.\n    \"\"\"\n    if location_rad is None or bearing_rad is None or location_stdev is None:\n      return None\n\n    # Update all way relations in collection to the provided location and bearing.\n    for wr in self.way_relations:\n      wr.update(location_rad, bearing_rad, location_stdev)\n\n    # Get the way relations where a match was found. i.e. those now marked as active as long as the direction of\n    # travel is valid.\n    valid_way_relations = [wr for wr in self.way_relations if wr.active and not wr.is_prohibited]\n\n    # If no active, then we could not find a current way to build a route.\n    if len(valid_way_relations) == 0:\n      return None\n\n    # If only one valid, then pick it as current.\n    if len(valid_way_relations) == 1:\n      current = valid_way_relations[0]\n\n    # If more than one is valid, filter out any valid way relation where the bearing delta indicator is too high.\n    else:\n      wr_acceptable_bearing = list(filter(lambda wr: wr.active_bearing_delta <= _ACCEPTABLE_BEARING_DELTA_IND,\n                                          valid_way_relations))\n\n      # If delta bearing indicator is too high for all, then use as current the one that has the shorter one.\n      if len(wr_acceptable_bearing) == 0:\n        valid_way_relations.sort(key=lambda wr: wr.active_bearing_delta)\n        current = valid_way_relations[0]\n\n      # If only one with acceptable bearing, use it.\n      elif len(wr_acceptable_bearing) == 1:\n        current = wr_acceptable_bearing[0]\n\n      else:\n        # If more than one with acceptable bearing, filter the ones with distance to way lower than 2 standard\n        # deviation from GPS accuracy (95%) + half the road width estimate.\n        wr_accurate_distance = [wr for wr in wr_acceptable_bearing\n                                if wr.distance_to_way <= 2. * location_stdev + wr.lanes * LANE_WIDTH / 2.]\n\n        # If none with accurate distance to way, then select the closest to the way\n        if len(wr_accurate_distance) == 0:\n          wr_acceptable_bearing.sort(key=lambda wr: wr.distance_to_way)\n          current = wr_acceptable_bearing[0]\n\n        # If only one with distance under accuracy, select this one.\n        elif len(wr_accurate_distance) == 1:\n          current = wr_accurate_distance[0]\n\n        # If more than one with distance under accuracy. Then select the one with lowest highway rank.\n        # i.e. prefere motorways over other roads and so on. This is to prevent selecting a small paralel\n        # road to a main road when the accuracy is poor.\n        else:\n          wr_accurate_distance.sort(key=lambda wr: wr.highway_rank)\n          current = wr_accurate_distance[0]\n\n    return Route(current, self.wr_index, self.id, self.query_center)\n"
  },
  {
    "path": "selfdrive/mapd/lib/WayRelation.py",
    "content": "from selfdrive.mapd.lib.geo import DIRECTION, R, vectors, bearing_to_points, distance_to_points\nfrom selfdrive.mapd.lib.osm import create_way\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.mapd.config import LANE_WIDTH\nfrom common.basedir import BASEDIR\nfrom datetime import datetime as dt\nimport numpy as np\nimport re\nimport json\n\n\n_WAY_BBOX_PADING = 80. / R  # 80 mts of pading to bounding box. (expressed in radians)\n\n\nwith open(BASEDIR + \"/selfdrive/mapd/lib/default_speeds.json\", \"rb\") as f:\n  _COUNTRY_LIMITS = json.loads(f.read())\n\n\n_WD = {\n  'Mo': 0,\n  'Tu': 1,\n  'We': 2,\n  'Th': 3,\n  'Fr': 4,\n  'Sa': 5,\n  'Su': 6\n}\n\n_HIGHWAY_RANK = {\n  'motorway': 0,\n  'motorway_link': 1,\n  'trunk': 10,\n  'trunk_link': 11,\n  'primary': 20,\n  'primary_link': 21,\n  'secondary': 30,\n  'secondary_link': 31,\n  'tertiary': 40,\n  'tertiary_link': 41,\n  'unclassified': 50,\n  'residential': 60,\n  'living_street': 61,\n  None: 100,\n}\n\n\ndef is_osm_time_condition_active(condition_string):\n  \"\"\"\n  Will indicate if a time condition for a restriction as described\n  @ https://wiki.openstreetmap.org/wiki/Conditional_restrictions\n  is active for the current date and time of day.\n  \"\"\"\n  now = dt.now().astimezone()\n  today = now.date()\n  week_days = []\n\n  # Look for days of week matched and validate if today matches criteria.\n  dr = re.findall(r'(Mo|Tu|We|Th|Fr|Sa|Su[-,\\s]*?)', condition_string)\n\n  if len(dr) == 1:\n    week_days = [_WD[dr[0]]]\n  # If two or more matches condider it a range of days between 1st and 2nd element.\n  elif len(dr) > 1:\n    week_days = list(range(_WD[dr[0]], _WD[dr[1]] + 1))\n\n  # If valid week days list is not empy and today day is not in the list, then the time-date range is not active.\n  if len(week_days) > 0 and now.weekday() not in week_days:\n    return False\n\n  # Look for time ranges on the day. No time range, means all day\n  tr = re.findall(r'([0-9]{1,2}:[0-9]{2})\\s*?-\\s*?([0-9]{1,2}:[0-9]{2})', condition_string)\n\n  # if no time range but there were week days set, consider it active during the whole day\n  if len(tr) == 0:\n    return len(dr) > 0\n\n  # Search among time ranges matched, one where now time belongs too. If found range is active.\n  for times_tup in tr:\n    times = list(map(lambda tt: dt.\n                 combine(today, dt.strptime(tt, '%H:%M').time().replace(tzinfo=now.tzinfo)), times_tup))\n    if now >= times[0] and now <= times[1]:\n      return True\n\n  return False\n\n\ndef speed_limit_value_for_limit_string(limit_string):\n  # Look for matches of speed by default in kph, or in mph when explicitly noted.\n  v = re.match(r'^\\s*([0-9]{1,3})\\s*?(mph)?\\s*$', limit_string)\n  if v is None:\n    return None\n  conv = CV.MPH_TO_MS if v[2] is not None and v[2] == \"mph\" else CV.KPH_TO_MS\n  return conv * float(v[1])\n\n\ndef speed_limit_for_osm_tag_limit_string(limit_string):\n  # https://wiki.openstreetmap.org/wiki/Key:maxspeed\n  if limit_string is None:\n    # When limit is set to 0. is considered not existing.\n    return 0.\n\n  # Attempt to parse limit as simple numeric value considering units.\n  limit = speed_limit_value_for_limit_string(limit_string)\n  if limit is not None:\n    return limit\n\n  # Look for matches of speed with country implicit values.\n  v = re.match(r'^\\s*([A-Z]{2}):([a-z_]+):?([0-9]{1,3})?(\\s+)?(mph)?\\s*', limit_string)\n  if v is None:\n    return 0.\n\n  if v[2] == \"zone\" and v[3] is not None:\n    conv = CV.MPH_TO_MS if v[5] is not None and v[5] == \"mph\" else CV.KPH_TO_MS\n    limit = conv * float(v[3])\n  elif f'{v[1]}:{v[2]}' in _COUNTRY_LIMITS:\n    limit = speed_limit_value_for_limit_string(_COUNTRY_LIMITS[f'{v[1]}:{v[2]}'])\n\n  return limit if limit is not None else 0.\n\n\ndef conditional_speed_limit_for_osm_tag_limit_string(limit_string):\n  if limit_string is None:\n    # When limit is set to 0. is considered not existing.\n    return 0.\n\n  # Look for matches of the `<restriction-value> @ (<condition>)` format\n  v = re.match(r'^(.*)@\\s*\\((.*)\\).*$', limit_string)\n  if v is None:\n    return 0.  # No valid format match\n\n  value = speed_limit_for_osm_tag_limit_string(v[1])\n  if value == 0.:\n    return 0.  # Invalid speed limit value\n\n  # Look for date-time conditions separated by semicolon\n  v = re.findall(r'(?:;|^)([^;]*)', v[2])\n  for datetime_condition in v:\n    if is_osm_time_condition_active(datetime_condition):\n      return value\n\n  # If we get here, no current date-time conditon is active.\n  return 0.\n\n\nclass WayRelation():\n  \"\"\"A class that represent the relationship of an OSM way and a given `location` and `bearing` of a driving vehicle.\n  \"\"\"\n  def __init__(self, way, parent=None):\n    self.way = way\n    self.parent_wr_id = parent.id if parent is not None else None  # For WRs created as splits of other WRs\n    self.reset_location_variables()\n    self.direction = DIRECTION.NONE\n    self._speed_limit = None\n    self._one_way = way.tags.get(\"oneway\")\n    self.name = way.tags.get('name')\n    self.ref = way.tags.get('ref')\n    self.highway_type = way.tags.get(\"highway\")\n    self.highway_rank = _HIGHWAY_RANK.get(self.highway_type)\n    try:\n      self.lanes = int(way.tags.get('lanes'))\n    except Exception:\n      self.lanes = 2\n\n    # Create numpy arrays with nodes data to support calculations.\n    self._nodes_np = np.radians(np.array([[nd.lat, nd.lon] for nd in way.nodes], dtype=float))\n    self._nodes_ids = np.array([nd.id for nd in way .nodes], dtype=int)\n\n    # Get the vectors representation of the segments betwheen consecutive nodes. (N-1, 2)\n    v = vectors(self._nodes_np) * R\n\n    # Calculate the vector magnitudes (or distance) between nodes. (N-1)\n    self._way_distances = np.linalg.norm(v, axis=1)\n\n    # Calculate the bearing (from true north clockwise) for every section of the way (vectors between nodes). (N-1)\n    self._way_bearings = np.arctan2(v[:, 0], v[:, 1])\n\n    # Define bounding box to ease the process of locating a node in a way.\n    # [[min_lat, min_lon], [max_lat, max_lon]]\n    self.bbox = np.row_stack((np.amin(self._nodes_np, 0) - _WAY_BBOX_PADING,\n                              np.amax(self._nodes_np, 0) + _WAY_BBOX_PADING))\n\n    # Get the edge nodes ids.\n    self.edge_nodes_ids = [way.nodes[0].id, way.nodes[-1].id]\n\n  def __repr__(self):\n    return f'(id: {self.id}, between {self.behind_idx} and {self.ahead_idx}, {self.direction}, active: {self.active})'\n\n  def __eq__(self, other):\n    if isinstance(other, WayRelation):\n        return self.id == other.id\n    return False\n\n  def reset_location_variables(self):\n    self.distance_to_node_ahead = 0.\n    self.location_rad = None\n    self.bearing_rad = None\n    self.active = False\n    self.diverting = False\n    self.ahead_idx = None\n    self.behind_idx = None\n    self._active_bearing_delta = None\n    self._distance_to_way = None\n\n  @property\n  def id(self):\n    return self.way.id\n\n  @property\n  def road_name(self):\n    if self.name is not None:\n      return self.name\n    return self.ref\n\n  def update(self, location_rad, bearing_rad, location_stdev):\n    \"\"\"Will update and validate the associated way with a given `location_rad` and `bearing_rad`.\n       Specifically it will find the nodes behind and ahead of the current location and bearing.\n       If no proper fit to the way geometry, the way relation is marked as invalid.\n    \"\"\"\n    self.reset_location_variables()\n\n    # Ignore if location not in way bounding box\n    if not self.is_location_in_bbox(location_rad):\n      return\n\n    # - Get the distance and bearings from location to all nodes. (N)\n    bearings = bearing_to_points(location_rad, self._nodes_np)\n    distances = distance_to_points(location_rad, self._nodes_np)\n\n    # - Get absolute bearing delta to current driving bearing. (N)\n    delta = np.abs(bearing_rad - bearings)\n\n    # - Nodes are ahead if the cosine of the delta is positive (N)\n    is_ahead = np.cos(delta) >= 0.\n\n    # - Possible locations on the way are those where adjacent nodes change from ahead to behind or viceversa.\n    possible_idxs = np.nonzero(np.diff(is_ahead))[0]\n\n    # - when no possible locations found, then the location is not in this way.\n    if len(possible_idxs) == 0:\n      return\n\n    # - Find then angle formed between the vectors from the current location to consecutive nodes. This is the\n    # value of the difference in the bearings of the vectors.\n    teta = np.diff(bearings)\n\n    # - When two consecutive nodes will be ahead and behind, they will form a triangle with the current location.\n    # We find the closest distance to the way by solving the area of the triangle and finding the height (h).\n    # We must use the abolute value of the sin of the angle in the formula, which is equivalent to ensure we\n    # are considering the smallest of the two angles formed between the two vectors.\n    # https://www.mathsisfun.com/algebra/trig-area-triangle-without-right-angle.html\n    h = distances[:-1] * distances[1:] * np.abs(np.sin(teta)) / self._way_distances\n\n    # - Calculate the delta between driving bearing and way bearings. (N-1)\n    bw_delta = self._way_bearings - bearing_rad\n\n    # - The absolut value of the sin of `bw_delta` indicates how close the bearings match independent of direction.\n    # We will use this value along the distance to the way to aid on way selection. (N-1)\n    abs_sin_bw_delta = np.abs(np.sin(bw_delta))\n\n    # - Get the delta to way bearing indicators and the distance to the way for the possible locations.\n    abs_sin_bw_delta_possible = abs_sin_bw_delta[possible_idxs]\n    h_possible = h[possible_idxs]\n\n    # - Get the index where the distance to the way is minimum. That is the chosen location.\n    min_h_possible_idx = np.argmin(h_possible)\n    min_delta_idx = possible_idxs[min_h_possible_idx]\n\n    # - If the distance to the way is over 4 standard deviations of the gps accuracy + half the maximum road width\n    # estimate, then we are way too far to stick to this way (i.e. we are not on this way anymore)\n    half_road_width_estimate = self.lanes * LANE_WIDTH / 2.\n    if h_possible[min_h_possible_idx] > 4. * location_stdev + half_road_width_estimate:\n      return\n\n    # - If the distance to the road is greater than 2 standard deviations of the gps accuracy + half the maximum road\n    # width estimate then we are most likely diverting from this route.\n    diverting = h_possible[min_h_possible_idx] > 2. * location_stdev + half_road_width_estimate\n\n    # Populate location variables with result\n    if is_ahead[min_delta_idx]:\n      self.direction = DIRECTION.BACKWARD\n      self.ahead_idx = min_delta_idx\n      self.behind_idx = min_delta_idx + 1\n    else:\n      self.direction = DIRECTION.FORWARD\n      self.ahead_idx = min_delta_idx + 1\n      self.behind_idx = min_delta_idx\n\n    self._distance_to_way = h[min_delta_idx]\n    self._active_bearing_delta = abs_sin_bw_delta_possible[min_h_possible_idx]\n    # TODO: The distance to node ahead currently represent the distance from the GPS fix location.\n    # It would be perhaps more accurate to use the distance on the projection over the direct line between\n    # the two nodes.\n    self.distance_to_node_ahead = distances[self.ahead_idx]\n    self.active = True\n    self.diverting = diverting\n    self.location_rad = location_rad\n    self.bearing_rad = bearing_rad\n    self._speed_limit = None\n\n  def update_direction_from_starting_node(self, start_node_id):\n    self._speed_limit = None\n    if self.edge_nodes_ids[0] == start_node_id:\n      self.direction = DIRECTION.FORWARD\n    elif self.edge_nodes_ids[-1] == start_node_id:\n      self.direction = DIRECTION.BACKWARD\n    else:\n      self.direction = DIRECTION.NONE\n\n  def is_location_in_bbox(self, location_rad):\n    \"\"\"Indicates if a given location is contained in the bounding box surrounding the way.\n       self.bbox = [[min_lat, min_lon], [max_lat, max_lon]]\n    \"\"\"\n    is_g = np.greater_equal(location_rad, self.bbox[0, :])\n    is_l = np.less_equal(location_rad, self.bbox[1, :])\n\n    return np.all(np.concatenate((is_g, is_l)))\n\n  @property\n  def speed_limit(self):\n    if self._speed_limit is not None:\n      return self._speed_limit\n\n    # Get string from corresponding tag, consider conditional limits first.\n    limit_string = self.way.tags.get(\"maxspeed:conditional\")\n    if limit_string is None:\n      if self.direction == DIRECTION.FORWARD:\n        limit_string = self.way.tags.get(\"maxspeed:forward:conditional\")\n      elif self.direction == DIRECTION.BACKWARD:\n        limit_string = self.way.tags.get(\"maxspeed:backward:conditional\")\n\n    limit = conditional_speed_limit_for_osm_tag_limit_string(limit_string)\n\n    # When no conditional limit set, attempt to get from regular speed limit tags.\n    if limit == 0.:\n      limit_string = self.way.tags.get(\"maxspeed\")\n      if limit_string is None:\n        if self.direction == DIRECTION.FORWARD:\n          limit_string = self.way.tags.get(\"maxspeed:forward\")\n        elif self.direction == DIRECTION.BACKWARD:\n          limit_string = self.way.tags.get(\"maxspeed:backward\")\n\n      limit = speed_limit_for_osm_tag_limit_string(limit_string)\n\n    self._speed_limit = limit\n    return self._speed_limit\n\n  @property\n  def active_bearing_delta(self):\n    \"\"\"Returns the sine of the delta between the current location bearing and the exact\n       bearing of the portion of way we are currentluy located at.\n    \"\"\"\n    return self._active_bearing_delta\n\n  @property\n  def is_one_way(self):\n    return self._one_way in ['yes'] or self.highway_type in [\"motorway\"]\n\n  @property\n  def is_prohibited(self):\n    # Direction must be defined to asses this property. Default to `True` if not.\n    if self.direction == DIRECTION.NONE:\n      return True\n    return self.is_one_way and self.direction == DIRECTION.BACKWARD\n\n  @property\n  def distance_to_way(self):\n    \"\"\"Returns the perpendicular (i.e. minimum) distance between current location and the way\n    \"\"\"\n    return self._distance_to_way\n\n  @property\n  def node_ahead(self):\n    return self.way.nodes[self.ahead_idx] if self.ahead_idx is not None else None\n\n  @property\n  def last_node(self):\n    \"\"\"Returns the last node on the way considering the traveling direction\n    \"\"\"\n    if self.direction == DIRECTION.FORWARD:\n      return self.way.nodes[-1]\n    if self.direction == DIRECTION.BACKWARD:\n      return self.way.nodes[0]\n    return None\n\n  @property\n  def last_node_coordinates(self):\n    \"\"\"Returns the coordinates for the last node on the way considering the traveling direction. (in radians)\n    \"\"\"\n    if self.direction == DIRECTION.FORWARD:\n      return self._nodes_np[-1]\n    if self.direction == DIRECTION.BACKWARD:\n      return self._nodes_np[0]\n    return None\n\n  def node_before_edge_coordinates(self, node_id):\n    \"\"\"Returns the coordinates of the node before the edge node identifeid with `node_id`. (in radians)\n    \"\"\"\n    if self.edge_nodes_ids[0] == node_id:\n      return self._nodes_np[1]\n\n    if self.edge_nodes_ids[-1] == node_id:\n      return self._nodes_np[-2]\n\n    return np.array([0., 0.])\n\n  def split(self, node_id, way_ids=None):\n    \"\"\" Returns and array with the way relations resulting from spliting the current way relation at node_id\n    \"\"\"\n    idxs = np.nonzero(self._nodes_ids == node_id)[0]\n    if len(idxs) == 0:\n      return []\n\n    idx = idxs[0]\n    if idx == 0 or idx == len(self._nodes_ids) - 1:\n      return [self]\n\n    if not isinstance(way_ids, list):\n      way_ids = [-1, -2]  # Default id values.\n\n    ways = [create_way(way_ids[0], node_ids=self._nodes_ids[:idx + 1], from_way=self.way),\n            create_way(way_ids[1], node_ids=self._nodes_ids[idx:], from_way=self.way)]\n    return [WayRelation(way, parent=self) for way in ways]\n"
  },
  {
    "path": "selfdrive/mapd/lib/WayRelationIndex.py",
    "content": "\n\nclass WayRelationIndex():\n  \"\"\"\n  A class containing an index of WayRelations by node ids of internal nodes and edge nodes.\n  \"\"\"\n  def __init__(self, way_relations):\n    self._edge_nodes_index_dict = {}\n    self._full_nodes_index_dict = {}\n\n    for wr in way_relations:\n      self.add(wr)\n\n  def add(self, way_relation):\n    for node in way_relation.way.nodes:\n      node_id = node.id\n      self._full_nodes_index_dict[node_id] = self._full_nodes_index_dict.get(node_id, []) + [way_relation]\n      if node_id in way_relation.edge_nodes_ids:\n        self._edge_nodes_index_dict[node_id] = self._edge_nodes_index_dict.get(node_id, []) + [way_relation]\n\n  def remove(self, way_relation):\n    for node in way_relation.way.nodes:\n      node_id = node.id\n      self._full_nodes_index_dict[node_id] = [wr for wr in self._full_nodes_index_dict.get(node_id, [])\n                                              if wr is not way_relation]\n      if node_id in way_relation.edge_nodes_ids:\n        self._edge_nodes_index_dict[node_id] = [wr for wr in self._edge_nodes_index_dict.get(node_id, [])\n                                                if wr is not way_relation]\n\n  def way_relations_with_edge_node_id(self, node_id):\n    return self._edge_nodes_index_dict.get(node_id, [])\n\n  def way_relations_with_node_id(self, node_id):\n    return self._full_nodes_index_dict.get(node_id, [])\n"
  },
  {
    "path": "selfdrive/mapd/lib/default_speeds.json",
    "content": "{\n  \"_comment\": \"These speeds are from https://wiki.openstreetmap.org/wiki/Speed_limits  Special cases have been stripped\",\n  \"AR:urban\": \"40\",\n  \"AR:urban:primary\": \"60\",\n  \"AR:urban:secondary\": \"60\",\n  \"AR:rural\": \"110\",\n  \"AT:urban\": \"50\",\n  \"AT:rural\": \"100\",\n  \"AT:trunk\": \"100\",\n  \"AT:motorway\": \"130\",\n  \"BE:urban\": \"50\",\n  \"BE-VLG:rural\": \"70\",\n  \"BE-WAL:rural\": \"90\",\n  \"BE:trunk\": \"120\",\n  \"BE:motorway\": \"120\",\n  \"CH:urban[1]\": \"50\",\n  \"CH:rural\": \"80\",\n  \"CH:trunk\": \"100\",\n  \"CH:motorway\": \"120\",\n  \"CZ:pedestrian_zone\": \"20\",\n  \"CZ:living_street\": \"20\",\n  \"CZ:urban\": \"50\",\n  \"CZ:urban_trunk\": \"80\",\n  \"CZ:urban_motorway\": \"80\",\n  \"CZ:rural\": \"90\",\n  \"CZ:trunk\": \"110\",\n  \"CZ:motorway\": \"130\",\n  \"DK:urban\": \"50\",\n  \"DK:rural\": \"80\",\n  \"DK:motorway\": \"130\",\n  \"DE:living_street\": \"7\",\n  \"DE:residential\": \"30\",\n  \"DE:urban\": \"50\",\n  \"DE:rural\": \"100\",\n  \"DE:trunk\": \"none\",\n  \"DE:motorway\": \"none\",\n  \"FI:urban\": \"50\",\n  \"FI:rural\": \"80\",\n  \"FI:trunk\": \"100\",\n  \"FI:motorway\": \"120\",\n  \"FR:urban\": \"50\",\n  \"FR:rural\": \"80\",\n  \"FR:trunk\": \"110\",\n  \"FR:motorway\": \"130\",\n  \"GR:urban\": \"50\",\n  \"GR:rural\": \"90\",\n  \"GR:trunk\": \"110\",\n  \"GR:motorway\": \"130\",\n  \"HU:urban\": \"50\",\n  \"HU:rural\": \"90\",\n  \"HU:trunk\": \"110\",\n  \"HU:motorway\": \"130\",\n  \"IT:urban\": \"50\",\n  \"IT:rural\": \"90\",\n  \"IT:trunk\": \"110\",\n  \"IT:motorway\": \"130\",\n  \"JP:national\": \"60\",\n  \"JP:motorway\": \"100\",\n  \"LT:living_street\": \"20\",\n  \"LT:urban\": \"50\",\n  \"LT:rural\": \"90\",\n  \"LT:trunk\": \"120\",\n  \"LT:motorway\": \"130\",\n  \"PL:living_street\": \"20\",\n  \"PL:urban\": \"50\",\n  \"PL:rural\": \"90\",\n  \"PL:trunk\": \"100\",\n  \"PL:motorway\": \"140\",\n  \"RO:urban\": \"50\",\n  \"RO:rural\": \"90\",\n  \"RO:trunk\": \"100\",\n  \"RO:motorway\": \"130\",\n  \"RU:living_street\": \"20\",\n  \"RU:urban\": \"60\",\n  \"RU:rural\": \"90\",\n  \"RU:motorway\": \"110\",\n  \"SK:urban\": \"50\",\n  \"SK:rural\": \"90\",\n  \"SK:trunk\": \"90\",\n  \"SK:motorway\": \"90\",\n  \"SI:urban\": \"50\",\n  \"SI:rural\": \"90\",\n  \"SI:trunk\": \"110\",\n  \"SI:motorway\": \"130\",\n  \"ES:living_street\": \"20\",\n  \"ES:urban\": \"50\",\n  \"ES:rural\": \"50\",\n  \"ES:trunk\": \"90\",\n  \"ES:motorway\": \"120\",\n  \"SE:urban\": \"50\",\n  \"SE:rural\": \"70\",\n  \"SE:trunk\": \"90\",\n  \"SE:motorway\": \"110\",\n  \"GB:nsl_restricted\": \"30 mph\",\n  \"GB:nsl_single\": \"60 mph\",\n  \"GB:nsl_dual\": \"70 mph\",\n  \"GB:motorway\": \"70 mph\",\n  \"UA:urban\": \"50\",\n  \"UA:rural\": \"90\",\n  \"UA:trunk\": \"110\",\n  \"UA:motorway\": \"130\",\n  \"UZ:living_street\": \"30\",\n  \"UZ:urban\": \"70\",\n  \"UZ:rural\": \"100\",\n  \"UZ:motorway\": \"110\",\n  \"ZA:trunk\": \"120\",\n  \"ZA:residential\": \"60\",\n  \"ZA:rural\": \"100\",\n  \"ZA:urban\": \"60\",\n  \"ZA:motorway\": \"120\"\n}\n"
  },
  {
    "path": "selfdrive/mapd/lib/geo.py",
    "content": "from enum import Enum\nimport numpy as np\n\n\nR = 6373000.0  # approximate radius of earth in mts\n\n\ndef vectors(points):\n  \"\"\"Provides a array of vectors on cartesian space (x, y).\n     Each vector represents the path from a point in `points` to the next.\n     `points` must by a (N, 2) array of [lat, lon] pairs in radians.\n  \"\"\"\n  latA = points[:-1, 0]\n  latB = points[1:, 0]\n  delta = np.diff(points, axis=0)\n  dlon = delta[:, 1]\n\n  x = np.sin(dlon) * np.cos(latB)\n  y = np.cos(latA) * np.sin(latB) - (np.sin(latA) * np.cos(latB) * np.cos(dlon))\n\n  return np.column_stack((x, y))\n\n\ndef ref_vectors(ref, points):\n  \"\"\"Provides a array of vectors on cartesian space (x, y).\n     Each vector represents the path from ref to a point in `points`.\n     `points` must by a (N, 2) array of [lat, lon] pairs in radians.\n  \"\"\"\n  latA = ref[0]\n  latB = points[:, 0]\n  delta = points - ref\n  dlon = delta[:, 1]\n\n  x = np.sin(dlon) * np.cos(latB)\n  y = np.cos(latA) * np.sin(latB) - (np.sin(latA) * np.cos(latB) * np.cos(dlon))\n\n  return np.column_stack((x, y))\n\n\ndef bearing_to_points(point, points):\n  \"\"\"Calculate the bearings (angle from true north clockwise) of the vectors between `point` and each\n  one of the entries in `points`. Both `point` and `points` elements are 2 element arrays containing a latitud,\n  longitude pair in radians.\n  \"\"\"\n  delta = points - point\n  x = np.sin(delta[:, 1]) * np.cos(points[:, 0])\n  y = np.cos(point[0]) * np.sin(points[:, 0]) - (np.sin(point[0]) * np.cos(points[:, 0]) * np.cos(delta[:, 1]))\n  return np.arctan2(x, y)\n\n\ndef distance_to_points(point, points):\n  \"\"\"Calculate the distance of the vectors between `point` and each one of the entries in `points`.\n  Both `point` and `points` elements are 2 element arrays containing a latitud, longitude pair in radians.\n  \"\"\"\n  delta = points - point\n  a = np.sin(delta[:, 0] / 2)**2 + np.cos(point[0]) * np.cos(points[:, 0]) * np.sin(delta[:, 1] / 2)**2\n  c = 2 * np.arctan2(np.sqrt(a), np.sqrt(1 - a))\n  return c * R\n\n\nclass DIRECTION(Enum):\n  NONE = 0\n  AHEAD = 1\n  BEHIND = 2\n  FORWARD = 3\n  BACKWARD = 4\n"
  },
  {
    "path": "selfdrive/mapd/lib/osm.py",
    "content": "import overpy\nimport numpy as np\nfrom selfdrive.mapd.lib.geo import R\n\n\ndef create_way(way_id, node_ids, from_way):\n  \"\"\"\n  Creates and OSM Way with the given `way_id` and list of `node_ids`, copying attributes and tags from `from_way`\n  \"\"\"\n  return overpy.Way(way_id, node_ids=node_ids, attributes={}, result=from_way._result,\n                    tags=from_way.tags)\n\n\nclass OSM():\n  def __init__(self):\n    self.api = overpy.Overpass()\n    # self.api = overpy.Overpass(url='https://z.overpass-api.de/api/interpreter')\n\n  def fetch_road_ways_around_location(self, lat, lon, radius):\n    # Calculate the bounding box coordinates for the bbox containing the circle around location.\n    bbox_angle = np.degrees(radius / R)\n    # fetch all ways and nodes on this ways in bbox\n    bbox_str = f'{str(lat - bbox_angle)},{str(lon - bbox_angle)},{str(lat + bbox_angle)},{str(lon + bbox_angle)}'\n    q = \"\"\"\n        way(\"\"\" + bbox_str + \"\"\")\n          [highway]\n          [highway!~\"^(footway|path|corridor|bridleway|steps|cycleway|construction|bus_guideway|escape|service|track)$\"];\n        (._;>;);\n        out;\n        \"\"\"\n    try:\n      ways = self.api.query(q).ways\n    except Exception as e:\n      print(f'Exception while querying OSM:\\n{e}')\n      ways = []\n\n    return ways\n"
  },
  {
    "path": "selfdrive/mapd/mapd.py",
    "content": "#!/usr/bin/env python3\nimport threading\nfrom traceback import print_exception\nimport numpy as np\nfrom time import strftime, gmtime\nimport cereal.messaging as messaging\nfrom common.realtime import Ratekeeper\nfrom selfdrive.mapd.lib.osm import OSM\nfrom selfdrive.mapd.lib.geo import distance_to_points\nfrom selfdrive.mapd.lib.WayCollection import WayCollection\nfrom selfdrive.mapd.config import QUERY_RADIUS, MIN_DISTANCE_FOR_NEW_QUERY, FULL_STOP_MAX_SPEED, LOOK_AHEAD_HORIZON_TIME\n\n\n_DEBUG = False\n\n\ndef _debug(msg):\n  if not _DEBUG:\n    return\n  print(msg)\n\n\ndef excepthook(args):\n  _debug(f'MapD: Threading exception:\\n{args}')\n  print_exception(args.exc_type, args.exc_value, args.exc_traceback)\n\n\nthreading.excepthook = excepthook\n\n\nclass MapD():\n  def __init__(self):\n    self.osm = OSM()\n    self.way_collection = None\n    self.route = None\n    self.last_gps_fix_timestamp = 0\n    self.last_gps = None\n    self.location_deg = None  # The current location in degrees.\n    self.location_rad = None  # The current location in radians as a Numpy array.\n    self.bearing_rad = None\n    self.location_stdev = None  # The current location accuracy in mts. 1 standard devitation.\n    self.gps_speed = 0.\n    self.last_fetch_location = None\n    self.last_route_update_fix_timestamp = 0\n    self.last_publish_fix_timestamp = 0\n    self._op_enabled = False\n    self._disengaging = False\n    self._query_thread = None\n    self._lock = threading.RLock()\n\n  def udpate_state(self, sm):\n    sock = 'controlsState'\n    if not sm.updated[sock] or not sm.valid[sock]:\n      return\n\n    controls_state = sm[sock]\n    self._disengaging = not controls_state.enabled and self._op_enabled\n    self._op_enabled = controls_state.enabled\n\n  def update_gps(self, sm):\n    sock = 'gpsLocationExternal'\n    if not sm.updated[sock] or not sm.valid[sock]:\n      return\n\n    log = sm[sock]\n    self.last_gps = log\n\n    # ignore the message if the fix is invalid\n    if log.flags % 2 == 0:\n      return\n\n    self.last_gps_fix_timestamp = log.timestamp  # Unix TS. Milliseconds since January 1, 1970.\n    self.location_rad = np.radians(np.array([log.latitude, log.longitude], dtype=float))\n    self.location_deg = (log.latitude, log.longitude)\n    self.bearing_rad = np.radians(log.bearingDeg, dtype=float)\n    self.gps_speed = log.speed\n    self.location_stdev = log.accuracy  # log accuracies are presumably 1 standard deviation.\n\n    _debug('Mapd: ********* Got GPS fix'\n           f'Pos: {self.location_deg} +/- {self.location_stdev * 2.} mts.\\n'\n           f'Bearing: {log.bearingDeg} +/- {log.bearingAccuracyDeg * 2.} deg.\\n'\n           f'timestamp: {strftime(\"%d-%m-%y %H:%M:%S\", gmtime(self.last_gps_fix_timestamp * 1e-3))}'\n           f'*******')\n\n  def _query_osm_not_blocking(self):\n    def query(osm, location_deg, location_rad, radius):\n      _debug(f'Mapd: Start query for OSM map data at {location_deg}')\n      lat, lon = location_deg\n      ways = osm.fetch_road_ways_around_location(lat, lon, radius)\n      _debug(f'Mapd: Query to OSM finished with {len(ways)} ways')\n\n      # Only issue an update if we received some ways. Otherwise it is most likely a conectivity issue.\n      # Will retry on next loop.\n      if len(ways) > 0:\n        new_way_collection = WayCollection(ways, location_rad)\n\n        # Use the lock to update the way_collection as it might be being used to update the route.\n        _debug('Mapd: Locking to write results from osm.')\n        with self._lock:\n          self.way_collection = new_way_collection\n          self.last_fetch_location = location_rad\n          _debug(f'Mapd: Updated map data @ {location_deg} - got {len(ways)} ways')\n\n        _debug('Mapd: Releasing Lock to write results from osm')\n\n    # Ignore if we have a query thread already running.\n    if self._query_thread is not None and self._query_thread.is_alive():\n      return\n\n    self._query_thread = threading.Thread(target=query, args=(self.osm, self.location_deg, self.location_rad,\n                                                              QUERY_RADIUS))\n    self._query_thread.start()\n\n  def updated_osm_data(self):\n    if self.route is not None:\n      distance_to_end = self.route.distance_to_end\n      if distance_to_end is not None and distance_to_end >= MIN_DISTANCE_FOR_NEW_QUERY:\n        # do not query as long as we have a route with enough distance ahead.\n        return\n\n    if self.location_rad is None:\n      return\n\n    if self.last_fetch_location is not None:\n      distance_since_last = distance_to_points(self.last_fetch_location, np.array([self.location_rad]))[0]\n      if distance_since_last < QUERY_RADIUS - MIN_DISTANCE_FOR_NEW_QUERY:\n        # do not query if are still not close to the border of previous query area\n        return\n\n    self._query_osm_not_blocking()\n\n  def update_route(self):\n    def update_proc():\n      # Ensure we clear the route on op disengage, this way we can correct possible incorrect map data due\n      # to wrongly locating or picking up the wrong route.\n      if self._disengaging:\n        self.route = None\n        _debug('Mapd *****: Clearing Route as system is disengaging. ********')\n\n      if self.way_collection is None or self.location_rad is None or self.bearing_rad is None:\n        _debug('Mapd *****: Can not update route. Missing WayCollection, location or bearing ********')\n        return\n\n      if self.route is not None and self.last_route_update_fix_timestamp == self.last_gps_fix_timestamp:\n        _debug('Mapd *****: Skipping route update. No new fix since last update ********')\n        return\n\n      self.last_route_update_fix_timestamp = self.last_gps_fix_timestamp\n\n      # Create the route if not existent or if it was generated by an older way collection\n      if self.route is None or self.route.way_collection_id != self.way_collection.id:\n        self.route = self.way_collection.get_route(self.location_rad, self.bearing_rad, self.location_stdev)\n        _debug(f'Mapd *****: Route created: \\n{self.route}\\n********')\n        return\n\n      # Do not attempt to update the route if the car is going close to a full stop, as the bearing can start\n      # jumping and creating unnecesary loosing of the route. Since the route update timestamp has been updated\n      # a new liveMapData message will be published with the current values (which is desirable)\n      if self.gps_speed < FULL_STOP_MAX_SPEED:\n        _debug('Mapd *****: Route Not updated as car has Stopped ********')\n        return\n\n      self.route.update(self.location_rad, self.bearing_rad, self.location_stdev)\n      if self.route.located:\n        _debug(f'Mapd *****: Route updated: \\n{self.route}\\n********')\n        return\n\n      # if an old route did not mange to locate, attempt to regenerate form way collection.\n      self.route = self.way_collection.get_route(self.location_rad, self.bearing_rad, self.location_stdev)\n      _debug(f'Mapd *****: Failed to update location in route. Regenerated with route: \\n{self.route}\\n********')\n\n    # We use the lock when updating the route, as it reads `way_collection` which can ben updated by\n    # a new query result from the _query_thread.\n    _debug('Mapd: Locking to update route.')\n    with self._lock:\n      update_proc()\n\n    _debug('Mapd: Releasing Lock to update route')\n\n  def publish(self, pm, sm):\n    # Ensure we have a route currently located\n    if self.route is None or not self.route.located:\n      return\n\n    # Ensure we have a route update since last publish\n    if self.last_publish_fix_timestamp == self.last_route_update_fix_timestamp:\n      return\n\n    self.last_publish_fix_timestamp = self.last_route_update_fix_timestamp\n\n    speed_limit = self.route.current_speed_limit\n    next_speed_limit_section = self.route.next_speed_limit_section\n    turn_speed_limit_section = self.route.current_curvature_speed_limit_section\n    horizon_mts = self.gps_speed * LOOK_AHEAD_HORIZON_TIME\n    next_turn_speed_limit_sections = self.route.next_curvature_speed_limit_sections(horizon_mts)\n    current_road_name = self.route.current_road_name\n\n    map_data_msg = messaging.new_message('liveMapData')\n    map_data_msg.valid = sm.all_alive_and_valid(service_list=['gpsLocationExternal'])\n\n    map_data_msg.liveMapData.lastGpsTimestamp = self.last_gps.timestamp\n    map_data_msg.liveMapData.speedLimitValid = bool(speed_limit is not None)\n    map_data_msg.liveMapData.speedLimit = float(speed_limit if speed_limit is not None else 0.0)\n    map_data_msg.liveMapData.speedLimitAheadValid = bool(next_speed_limit_section is not None)\n    map_data_msg.liveMapData.speedLimitAhead = float(next_speed_limit_section.value\n                                                     if next_speed_limit_section is not None else 0.0)\n    map_data_msg.liveMapData.speedLimitAheadDistance = float(next_speed_limit_section.start\n                                                             if next_speed_limit_section is not None else 0.0)\n\n    map_data_msg.liveMapData.turnSpeedLimitValid = bool(turn_speed_limit_section is not None)\n    map_data_msg.liveMapData.turnSpeedLimit = float(turn_speed_limit_section.value\n                                                    if turn_speed_limit_section is not None else 0.0)\n    map_data_msg.liveMapData.turnSpeedLimitSign = int(turn_speed_limit_section.curv_sign\n                                                      if turn_speed_limit_section is not None else 0)\n    map_data_msg.liveMapData.turnSpeedLimitEndDistance = float(turn_speed_limit_section.end\n                                                               if turn_speed_limit_section is not None else 0.0)\n    map_data_msg.liveMapData.turnSpeedLimitsAhead = [float(s.value) for s in next_turn_speed_limit_sections]\n    map_data_msg.liveMapData.turnSpeedLimitsAheadDistances = [float(s.start) for s in next_turn_speed_limit_sections]\n    map_data_msg.liveMapData.turnSpeedLimitsAheadSigns = [float(s.curv_sign) for s in next_turn_speed_limit_sections]\n\n    map_data_msg.liveMapData.currentRoadName = str(current_road_name if current_road_name is not None else \"\")\n\n    pm.send('liveMapData', map_data_msg)\n    _debug(f'Mapd *****: Publish: \\n{map_data_msg}\\n********')\n\n\n# provides live map data information\ndef mapd_thread(sm=None, pm=None):\n  mapd = MapD()\n  rk = Ratekeeper(1., print_delay_threshold=None)  # Keeps rate at 1 hz\n\n  # *** setup messaging\n  if sm is None:\n    sm = messaging.SubMaster(['gpsLocationExternal', 'controlsState'])\n  if pm is None:\n    pm = messaging.PubMaster(['liveMapData'])\n\n  while True:\n    sm.update()\n    mapd.udpate_state(sm)\n    mapd.update_gps(sm)\n    mapd.updated_osm_data()\n    mapd.update_route()\n    mapd.publish(pm, sm)\n    rk.keep_time()\n\n\ndef main(sm=None, pm=None):\n  mapd_thread(sm, pm)\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/mapd/test/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/mapd/test/mock_data.py",
    "content": "from selfdrive.mapd.lib.WayCollection import WayCollection\nfrom selfdrive.mapd.lib.geo import vectors, R\nfrom selfdrive.mapd.lib.NodesData import _MIN_NODE_DISTANCE, _ADDED_NODES_DIST, _SPLINE_EVAL_STEP, \\\n  _MIN_SPEED_SECTION_LENGHT, nodes_raw_data_array_for_wr, node_calculations, is_wr_a_valid_divertion_from_node, \\\n  spline_curvature_calculations, speed_limits_for_curvatures_data\nfrom scipy.interpolate import splev, splprep\nimport numpy as np\nimport overpy\n\n\nclass MockNodesData():\n  def __init__(self, way_coords):\n    self.degrees = np.array(way_coords)\n    self.radians = np.radians(self.degrees)\n\n    # *****************\n    # Expected code implementation nodes_data\n    self.v = vectors(self.radians) * R\n    self.d = np.linalg.norm(self.v, axis=1)\n    self.b = np.arctan2(self.v[:, 0], self.v[:, 1])\n    self.v = np.concatenate(([[0., 0.]], self.v))\n    self.dp = np.concatenate(([0.], self.d))\n    self.dn = np.concatenate((self.d, [0.]))\n    self.dr = np.cumsum(self.dp, axis=0)\n    self.b = np.concatenate((self.b, [self.b[-1]]))\n\n    # Expected code implementation spline_curvature_calculations\n    vect = self.v\n    dist_prev = self.dp\n    too_far_idxs = np.nonzero(self.dp >= _MIN_NODE_DISTANCE)[0]\n    for idx in too_far_idxs[::-1]:\n      dp = dist_prev[idx]  # distance of vector that needs to be replaced by higher resolution vectors.\n      n = int(np.ceil(dp / _ADDED_NODES_DIST))  # number of vectors that need to be added.\n      new_v = vect[idx, :] / n  # new relative vector to insert.\n      vect = np.delete(vect, idx, axis=0)  # remove the relative vector to be replaced by the insertion of new vectors.\n      vect = np.insert(vect, [idx] * n, [new_v] * n, axis=0)  # insert n new relative vectors\n    ds = np.cumsum(dist_prev, axis=0)\n    vs = np.cumsum(vect, axis=0)\n    tck, u = splprep([vs[:, 0], vs[:, 1]])  # pylint: disable=W0632\n    n = max(int(ds[-1] / _SPLINE_EVAL_STEP), len(u))\n    unew = np.arange(0, n + 1) / n\n    d1 = splev(unew, tck, der=1)\n    d2 = splev(unew, tck, der=2)\n    num = d1[0] * d2[1] - d1[1] * d2[0]\n    den = (d1[0]**2 + d1[1]**2)**(1.5)\n    self.curv = num / den\n    self.curv_ds = unew * ds[-1]\n    # *****************\n\n\nclass MockCurveSection():\n  def __init__(self, func, di=0., df=1000., step=10.):\n    self.di = di\n    self.df = df\n    self.n = (df - di) // step\n    self.u = np.arange(0, self.n + 1) / self.n\n    self.curv_ds = self.u * (df - di) + di\n    self.curv = func(self.u)\n    self.curv_abs = np.abs(self.curv)\n    self.curv_sec = np.column_stack((self.curv_abs, np.sign(self.curv), self.curv_ds))\n\n\nclass MockOSMQueryResponse():\n  def __init__(self, xml_path, query_center):\n    self.api = overpy.Overpass()\n    self.query_center = np.radians(np.array(query_center))\n\n    with open(xml_path, 'r') as f:\n      overpass_xml = f.read()\n      self.ways = self.api.parse_xml(overpass_xml).ways\n\n    self.wayCollection = WayCollection(self.ways, self.query_center)\n\nclass MockRouteData():\n  def __init__(self, way_ids, way_collection, first_node_id):  # way)ids must be in order forming a route.\n    self.wrs = [next(wr for wr in way_collection.way_relations if wr.id == way_id) for way_id in way_ids]\n    self.way_collection = way_collection\n    self.first_node_id = first_node_id\n\n  def reset(self):\n    way_relations = self.wrs\n    wr_index = self.way_collection.wr_index\n\n    # Nodes Data processing expects way relations to be updated with direction before running.\n    for idx, wr in enumerate(way_relations):\n      if idx == 0:\n        wr.update_direction_from_starting_node(self.first_node_id)\n      else:\n        wr.update_direction_from_starting_node(way_relations[idx - 1].last_node.id)\n\n    # ***** Expected calculations\n    self._nodes_data = np.array([])\n    self._divertions = [[]]\n    self._curvature_speed_sections_data = np.array([])\n    way_count = len(way_relations)\n    if way_count == 0:\n      return\n    # We want all the nodes from the last way section\n    nodes_data = nodes_raw_data_array_for_wr(way_relations[-1])\n    # For the ways before the last in the route we want all the nodes but the last, as that one is the first on\n    # the next section. Collect them, append last way node data and concatenate the numpy arrays.\n    if way_count > 1:\n      wrs_data = tuple([nodes_raw_data_array_for_wr(wr, drop_last=True) for wr in way_relations[:-1]])\n      wrs_data += (nodes_data,)\n      nodes_data = np.concatenate(wrs_data)\n    # Get a subarray with lat, lon to compute the remaining node values.\n    lat_lon_array = nodes_data[:, [1, 2]]\n    points = np.radians(lat_lon_array)\n    # Ensure we have more than 3 points, if not calculations are not possible.\n    if len(points) <= 3:\n      return\n    vect, dist_prev, dist_next, dist_route, bearing = node_calculations(points)\n    # append calculations to nodes_data\n    # nodes_data structure: [id, lat, lon, speed_limit, x, y, dist_prev, dist_next, dist_route, bearing]\n    self._nodes_data = np.column_stack((nodes_data, vect, dist_prev, dist_next, dist_route, bearing))\n    # Build route divertion options data from the wr_index.\n    wr_ids = [wr.id for wr in way_relations]\n    self._divertions = [[wr for wr in wr_index.way_relations_with_edge_node_id(node_id)\n                        if is_wr_a_valid_divertion_from_node(wr, node_id, wr_ids)]\n                        for node_id in nodes_data[:, 0]]\n    # Store calculcations for curvature sections speed limits. We need more than 3 points to be able to process.\n    # _curvature_speed_sections_data structure: [dist_start, dist_stop, speed_limits, curv_sign]\n    if len(vect) > 3:\n      self._curv, self._curv_ds = spline_curvature_calculations(vect, dist_prev)\n      self._curvature_speed_sections_data = speed_limits_for_curvatures_data(self._curv, self._curv_ds)\n    # *****\n\n\n# Test data in degrees from this road:\n# https://www.google.de/maps/@52.209263,13.8723137,13z\n_WAY_NODES_COORDS_01 = [\n  [52.1933703, 13.8723799],\n  [52.1939477, 13.8711273],\n  [52.1942004, 13.8705818],\n  [52.1945408, 13.8698496],\n  [52.1948447, 13.8691873],\n  [52.1950772, 13.8685726],\n  [52.1951168, 13.8684641],\n  [52.1956681, 13.8670323],\n  [52.1958716, 13.8664936],\n  [52.1964366, 13.8649875],\n  [52.1969283, 13.8636040],\n  [52.1970203, 13.8634430],\n  [52.1975486, 13.8626307],\n  [52.1976354, 13.8624971],\n  [52.1977827, 13.8621795],\n  [52.1978564, 13.8619220],\n  [52.1981843, 13.8604497],\n  [52.1982614, 13.8602140],\n  [52.1983351, 13.8600595],\n  [52.1992768, 13.8579824],\n  [52.1995107, 13.8574321],\n  [52.1995948, 13.8572604],\n  [52.1996818, 13.8571155],\n  [52.1998000, 13.8570029],\n  [52.2000659, 13.8568236],\n  [52.2003868, 13.8566005],\n  [52.2007182, 13.8564460],\n  [52.2008760, 13.8564117],\n  [52.2009865, 13.8564117],\n  [52.2011390, 13.8564202],\n  [52.2012267, 13.8564496],\n  [52.2012544, 13.8564577],\n  [52.2013179, 13.8564803],\n  [52.2020491, 13.8571756],\n  [52.2026014, 13.8576991],\n  [52.2027592, 13.8578879],\n  [52.2027960, 13.8579309],\n  [52.2028960, 13.8580939],\n  [52.2030170, 13.8583343],\n  [52.2036587, 13.8597076],\n  [52.2052946, 13.8633039],\n  [52.2064332, 13.8658435],\n  [52.2067856, 13.8666332],\n  [52.2068961, 13.8668477],\n  [52.2070777, 13.8670890],\n  [52.2073723, 13.8674409],\n  [52.2077457, 13.8679387],\n  [52.2083874, 13.8687455],\n  [52.2093341, 13.8699214],\n  [52.2099652, 13.8707540],\n  [52.2102282, 13.8712089],\n  [52.2104228, 13.8715694],\n  [52.2106122, 13.8718955],\n  [52.2107619, 13.8721756],\n  [52.2108695, 13.8723771],\n  [52.2110747, 13.8727610],\n  [52.2111514, 13.8729047],\n  [52.2114010, 13.8733718],\n  [52.2114694, 13.8735006],\n  [52.2115430, 13.8736636],\n  [52.2116086, 13.8737571],\n  [52.2116770, 13.8738172],\n  [52.2117611, 13.8738515],\n  [52.2118664, 13.8738566],\n  [52.2119322, 13.8738439],\n  [52.2121058, 13.8737924],\n  [52.2122583, 13.8737495],\n  [52.2123265, 13.8737260],\n  [52.2124213, 13.8736894],\n  [52.2127466, 13.8734888],\n  [52.2128263, 13.8734491],\n  [52.2131313, 13.8733117],\n  [52.2133943, 13.8731830],\n  [52.2136625, 13.8731057],\n  [52.2139465, 13.8730456],\n  [52.2143619, 13.8730113],\n  [52.2148773, 13.8729942],\n  [52.2152275, 13.8730325],\n  [52.2153110, 13.8730398],\n  [52.2157442, 13.8730848],\n  [52.2158833, 13.8731036]]\n\n\nmockNodesData01 = MockNodesData(_WAY_NODES_COORDS_01)\n\n# OSM Query around B96 south of Berlin\nmockOSMResponse01 = MockOSMQueryResponse('selfdrive/mapd/test/mock_osm_response_01.xml',\n                                         [52.31400353586984, 13.447158941786366])\n\n# OSM Query on curvy town area south of Germany.\nmockOSMResponse02 = MockOSMQueryResponse('selfdrive/mapd/test/mock_osm_response_02.xml',\n                                         [48.16573269276522, 9.81418473659117])\n\nmockWayCollection01 = WayCollection(mockOSMResponse01.ways, mockOSMResponse01.query_center)\nmockWayCollection02 = WayCollection(mockOSMResponse02.ways, mockOSMResponse02.query_center)\n\n# Normal curvy Way. way id: 179532213 with 35 Nodes.\nmockOSMWay_01_01_LongCurvy = next(way for way in mockOSMResponse01.ways if way.id == 179532213)\n\n# Looped way. way id: 29233907\nmockOSMWay_01_02_Loop = next(way for way in mockOSMResponse01.ways if way.id == 29233907)\n\n# Complex curvy road through town with intersections. way id:178450395\nmockOSMWay_02_01_CurvyTownWithIntersections = next(way for way in mockOSMResponse02.ways if way.id == 178450395)\n\n# Valid divertion for way 02_01 at node: 34785115. way id: 27955186\nmockOSMWay_02_02_Divertion_34785115 = next(way for way in mockOSMResponse02.ways if way.id == 27955186)\n\n# 3 node way. way id: 807781992\nmockOSMWay_02_03_Short_3_node_way = next(way for way in mockOSMResponse02.ways if way.id == 807781992)\n\n# data composing route 01 in way collection 02\nmockRouteData_02_01 = MockRouteData([60890967, 737120246, 601406617, 60890971, 178450395], mockWayCollection02,\n                                    first_node_id=201962346)\n\n# data composing route 02 in way collection 02. Single WR\nmockRouteData_02_02_single_wr = MockRouteData([178450395], mockWayCollection02, first_node_id=762086638)\n\n# data composing route 03 in way collection 02. Multiple speed limits\nmockRouteData_02_03 = MockRouteData([158799549, 798805532, 28707704, 158797898, 602249535, 602249536, 825823509,\n                                     178449088, 916462523, 158796386], mockWayCollection02,\n                                    first_node_id=252601829)\n\n# 1000mt section with one full sin cycle as curv values.\nmockCurveSectionSin = MockCurveSection(lambda x: np.sin(x * 2 * np.pi))\n\n# 200mt section with changing curvature rate.\nmockCurveSteepCurvChange = MockCurveSection(lambda x: 0.05 * x**3 - 0.007 * x**2 + 0.001 * x, df=200)\n\n# _MIN_SPEED_SECTION_LENGHT section with changing curvature rate.\nmockCurveSteepCurvChangeShort = MockCurveSection(\n  lambda x: 0.05 * x**3 - 0.007 * x**2 + 0.001 * x, df=_MIN_SPEED_SECTION_LENGHT)\n\n# 200mt section with smooth changing curvature rate. no deviation over 2.\nmockCurveSmoothCurveChange = MockCurveSection(lambda x: 0.0002 * x**3 - 0.001 * x**2 + 0.6 * x, df=200)\n"
  },
  {
    "path": "selfdrive/mapd/test/mock_osm_response_01.xml",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<!-- \n  OSM response to below query 6 Sept 2021.\n\n  way(around:3000.0,52.31400353586984, 13.447158941786366)\n    [highway]\n    [highway!~\"^(footway|path|corridor|bridleway|steps|cycleway|construction|bus_guideway|escape|service|track)$\"];\n  (._;>;);\n  out;\n -->\n<osm version=\"0.6\" generator=\"Overpass API 0.7.56.9 76e5016d\">\n<note>The data included in this document is from www.openstreetmap.org. The data is made available under ODbL.</note>\n<meta osm_base=\"2021-09-06T11:30:13Z\"/>\n\n  <node id=\"21483089\" lat=\"52.3060080\" lon=\"13.4264867\"/>\n  <node id=\"26808325\" lat=\"52.3179880\" lon=\"13.4439053\"/>\n  <node id=\"26808420\" lat=\"52.3434001\" lon=\"13.4348269\"/>\n  <node id=\"26808421\" lat=\"52.3233243\" lon=\"13.4378904\"/>\n  <node id=\"27487353\" lat=\"52.3058554\" lon=\"13.4265520\"/>\n  <node id=\"27487359\" lat=\"52.3067414\" lon=\"13.4460405\">\n    <tag k=\"highway\" v=\"motorway_junction\"/>\n    <tag k=\"name\" v=\"Rangsdorf\"/>\n    <tag k=\"ref\" v=\"12\"/>\n  </node>\n  <node id=\"29553842\" lat=\"52.3288409\" lon=\"13.4110145\"/>\n  <node id=\"29648371\" lat=\"52.2998722\" lon=\"13.4541580\"/>\n  <node id=\"29648373\" lat=\"52.2992972\" lon=\"13.4529638\"/>\n  <node id=\"29648375\" lat=\"52.2990331\" lon=\"13.4524330\">\n    <tag k=\"bus\" v=\"yes\"/>\n    <tag k=\"name\" v=\"Hochwaldpromenade\"/>\n    <tag k=\"public_transport\" v=\"stop_position\"/>\n  </node>\n  <node id=\"29648377\" lat=\"52.2987875\" lon=\"13.4518793\"/>\n  <node id=\"29648380\" lat=\"52.2985028\" lon=\"13.4512416\"/>\n  <node id=\"29648382\" lat=\"52.2984226\" lon=\"13.4507492\"/>\n  <node id=\"29648384\" lat=\"52.2984773\" lon=\"13.4503687\"/>\n  <node id=\"29648399\" lat=\"52.2942995\" lon=\"13.4320701\"/>\n  <node id=\"29648409\" lat=\"52.2920170\" lon=\"13.4250484\"/>\n  <node id=\"29648411\" lat=\"52.2919204\" lon=\"13.4239579\"/>\n  <node id=\"29648428\" lat=\"52.3061188\" lon=\"13.4776488\"/>\n  <node id=\"29648429\" lat=\"52.3061731\" lon=\"13.4778805\"/>\n  <node id=\"29648430\" lat=\"52.3062774\" lon=\"13.4796253\"/>\n  <node id=\"29648431\" lat=\"52.3073899\" lon=\"13.4810048\"/>\n  <node id=\"29648432\" lat=\"52.3075404\" lon=\"13.4814070\"/>\n  <node id=\"29648435\" lat=\"52.3077663\" lon=\"13.4837979\"/>\n  <node id=\"29648454\" lat=\"52.3175383\" lon=\"13.4738377\">\n    <tag k=\"access\" v=\"private\"/>\n    <tag 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v=\"Kastanienallee\"/>\n    <tag k=\"oneway\" v=\"no\"/>\n    <tag k=\"sidewalk\" v=\"none\"/>\n  </way>\n  <way id=\"884124824\">\n    <nd ref=\"370463240\"/>\n    <nd ref=\"29648471\"/>\n    <tag k=\"bicycle\" v=\"use_sidepath\"/>\n    <tag k=\"cycleway:right\" v=\"separate\"/>\n    <tag k=\"foot\" v=\"use_sidepath\"/>\n    <tag k=\"highway\" v=\"secondary\"/>\n    <tag k=\"lanes\" v=\"2\"/>\n    <tag k=\"maxspeed\" v=\"50\"/>\n    <tag k=\"name\" v=\"Groß Kienitzer Landstraße\"/>\n    <tag k=\"ref\" v=\"L 402\"/>\n    <tag k=\"sidewalk:right\" v=\"separate\"/>\n    <tag k=\"smoothness\" v=\"good\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n  <way id=\"884124825\">\n    <nd ref=\"1909854864\"/>\n    <nd ref=\"8222316494\"/>\n    <nd ref=\"1909854853\"/>\n    <nd ref=\"2684927826\"/>\n    <tag k=\"bicycle\" v=\"use_sidepath\"/>\n    <tag k=\"cycleway:right\" v=\"separate\"/>\n    <tag k=\"foot\" v=\"use_sidepath\"/>\n    <tag k=\"highway\" v=\"secondary\"/>\n    <tag k=\"maxspeed\" v=\"50\"/>\n    <tag k=\"name\" v=\"Groß Kienitzer Dorfstraße\"/>\n    <tag k=\"old_name\" v=\"Dorfstraße\"/>\n    <tag k=\"postal_code\" v=\"15831\"/>\n    <tag k=\"ref\" v=\"L 402\"/>\n    <tag k=\"sidewalk:right\" v=\"separate\"/>\n    <tag k=\"smoothness\" v=\"good\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n  <way id=\"914630487\">\n    <nd ref=\"8496353098\"/>\n    <nd ref=\"706934448\"/>\n    <nd ref=\"3335487151\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"maxspeed\" v=\"50\"/>\n    <tag k=\"name\" v=\"Kastanienallee\"/>\n    <tag k=\"oneway\" v=\"no\"/>\n  </way>\n  <way id=\"914630494\">\n    <nd ref=\"8496358638\"/>\n    <nd ref=\"8496358641\"/>\n    <nd ref=\"8496358639\"/>\n    <tag k=\"highway\" v=\"razed\"/>\n  </way>\n  <way id=\"937844324\">\n    <nd ref=\"1704521855\"/>\n    <nd ref=\"8688733048\"/>\n    <tag k=\"access\" v=\"yes\"/>\n    <tag k=\"bicycle\" v=\"no\"/>\n    <tag k=\"cycleway\" v=\"no\"/>\n    <tag k=\"foot\" v=\"no\"/>\n    <tag k=\"highway\" v=\"primary\"/>\n    <tag k=\"lanes\" v=\"2\"/>\n    <tag k=\"maxspeed\" v=\"70\"/>\n    <tag k=\"oneway\" v=\"yes\"/>\n    <tag k=\"ref\" v=\"B 96\"/>\n    <tag k=\"smoothness\" v=\"good\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n    <tag k=\"toll:N3\" v=\"yes\"/>\n    <tag k=\"toll:hgv\" v=\"yes\"/>\n    <tag k=\"toll:operator\" v=\"Toll Collect\"/>\n    <tag k=\"turn:lanes\" v=\"none|none|merge_to_left\"/>\n  </way>\n  <way id=\"938135207\">\n    <nd ref=\"393875323\"/>\n    <nd ref=\"393875320\"/>\n    <nd ref=\"3183693705\"/>\n    <nd ref=\"254333911\"/>\n    <tag k=\"construction\" v=\"residential\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"name\" v=\"Rangsdorfer Weg\"/>\n    <tag k=\"surface\" v=\"paved\"/>\n  </way>\n  <way id=\"942898940\">\n    <nd ref=\"370956957\"/>\n    <nd ref=\"3183693704\"/>\n    <nd ref=\"393875417\"/>\n    <nd ref=\"370956956\"/>\n    <nd ref=\"8731220877\"/>\n    <nd ref=\"8731220878\"/>\n    <nd ref=\"8731220886\"/>\n    <nd ref=\"8731220879\"/>\n    <nd ref=\"8731220880\"/>\n    <nd ref=\"8731220881\"/>\n    <nd ref=\"8731220885\"/>\n    <nd ref=\"8731220882\"/>\n    <nd ref=\"254334574\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"maxspeed\" v=\"30\"/>\n    <tag k=\"name\" v=\"Gutsbahntrasse\"/>\n    <tag k=\"source\" v=\"survey\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n  <way id=\"942906302\">\n    <nd ref=\"256006923\"/>\n    <nd ref=\"8829853678\"/>\n    <nd ref=\"8731270134\"/>\n    <nd ref=\"8731270135\"/>\n    <nd ref=\"256006902\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"maxspeed\" v=\"30\"/>\n    <tag k=\"name\" v=\"Lankenschlag\"/>\n    <tag k=\"postal_code\" v=\"15827\"/>\n  </way>\n  <way id=\"943221313\">\n    <nd ref=\"734142915\"/>\n    <nd ref=\"8733710280\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"lanes\" v=\"1\"/>\n    <tag k=\"maxspeed\" v=\"50\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n  <way id=\"954014221\">\n    <nd ref=\"4395091772\"/>\n    <nd ref=\"3183549383\"/>\n    <nd ref=\"8829870707\"/>\n    <tag k=\"cycleway:both\" v=\"no\"/>\n    <tag k=\"highway\" v=\"unclassified\"/>\n    <tag k=\"lane_markings\" v=\"no\"/>\n    <tag k=\"name\" v=\"Am Bahnhofsschlag\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n  <way id=\"955124183\">\n    <nd ref=\"8840204905\"/>\n    <nd ref=\"8840204899\"/>\n    <nd ref=\"8840204903\"/>\n    <nd ref=\"8840204902\"/>\n    <tag k=\"highway\" v=\"unclassified\"/>\n  </way>\n  <way id=\"955124184\">\n    <nd ref=\"268107487\"/>\n    <nd ref=\"268107726\"/>\n    <nd ref=\"473224518\"/>\n    <tag k=\"cycleway\" v=\"no\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"maxspeed\" v=\"50\"/>\n    <tag k=\"name\" v=\"Nymphenseeweg\"/>\n    <tag k=\"postal_code\" v=\"15834\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n\n</osm>\n\n"
  },
  {
    "path": "selfdrive/mapd/test/mock_osm_response_02.xml",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<!-- \n  OSM response to below query 8 Sept 2021.\n\n  way(around:3000.0,48.16573269276522, 9.81418473659117)\n    [highway]\n    [highway!~\"^(footway|path|corridor|bridleway|steps|cycleway|construction|bus_guideway|escape|service|track)$\"];\n  (._;>;);\n  out;\n -->\n<osm version=\"0.6\" generator=\"Overpass API 0.7.56.9 76e5016d\">\n<note>The data included in this document is from www.openstreetmap.org. The data is made available under ODbL.</note>\n<meta osm_base=\"2021-09-08T07:52:43Z\"/>\n\n  <node id=\"25970404\" lat=\"48.1885590\" lon=\"9.8287360\">\n    <tag k=\"railway\" v=\"level_crossing\"/>\n  </node>\n  <node id=\"25970454\" lat=\"48.1632977\" lon=\"9.8166374\"/>\n  <node id=\"25970455\" lat=\"48.1627989\" lon=\"9.8173762\"/>\n  <node id=\"25970458\" lat=\"48.1606851\" lon=\"9.8213863\"/>\n  <node id=\"31388925\" lat=\"48.1736206\" lon=\"9.8600805\"/>\n  <node id=\"31388926\" lat=\"48.1731598\" lon=\"9.8597680\"/>\n  <node id=\"31388927\" lat=\"48.1721314\" lon=\"9.8593198\"/>\n  <node id=\"31388928\" lat=\"48.1709070\" lon=\"9.8590855\"/>\n  <node id=\"31388929\" lat=\"48.1663372\" lon=\"9.8592708\"/>\n  <node id=\"31388930\" lat=\"48.1649145\" lon=\"9.8588664\"/>\n  <node id=\"31388931\" lat=\"48.1637849\" lon=\"9.8582248\"/>\n  <node id=\"31388932\" lat=\"48.1608526\" lon=\"9.8552561\"/>\n  <node id=\"31388933\" lat=\"48.1587234\" lon=\"9.8520885\"/>\n  <node id=\"31388934\" lat=\"48.1518921\" lon=\"9.8372782\"/>\n  <node id=\"31388935\" lat=\"48.1504584\" lon=\"9.8351512\">\n    <tag k=\"highway\" v=\"motorway_junction\"/>\n    <tag k=\"name\" v=\"Biberach-Nord\"/>\n  </node>\n  <node id=\"31388936\" lat=\"48.1494083\" lon=\"9.8340030\"/>\n  <node id=\"31388937\" lat=\"48.1485658\" lon=\"9.8332713\"/>\n  <node id=\"31388938\" lat=\"48.1465900\" lon=\"9.8320239\"/>\n  <node id=\"31388939\" lat=\"48.1443124\" lon=\"9.8306441\"/>\n  <node id=\"31388940\" lat=\"48.1424589\" lon=\"9.8289207\"/>\n  <node id=\"31388941\" lat=\"48.1406704\" lon=\"9.8270881\"/>\n  <node id=\"31388942\" lat=\"48.1392575\" lon=\"9.8257995\"/>\n  <node id=\"31388943\" lat=\"48.1383410\" lon=\"9.8250923\"/>\n  <node id=\"31388944\" lat=\"48.1357992\" lon=\"9.8236436\"/>\n  <node id=\"31388945\" lat=\"48.1341655\" lon=\"9.8230177\"/>\n  <node id=\"31388946\" lat=\"48.1325443\" lon=\"9.8226467\"/>\n  <node id=\"31388947\" lat=\"48.1308448\" lon=\"9.8224914\"/>\n  <node id=\"31388948\" lat=\"48.1288747\" lon=\"9.8226007\"/>\n  <node id=\"31388949\" lat=\"48.1268225\" lon=\"9.8230782\"/>\n  <node id=\"31388950\" lat=\"48.1248031\" lon=\"9.8239018\"/>\n  <node id=\"31388951\" lat=\"48.1219770\" lon=\"9.8257389\">\n    <tag k=\"created_by\" v=\"JOSM\"/>\n  </node>\n  <node id=\"31388952\" lat=\"48.1168411\" lon=\"9.8305125\"/>\n  <node id=\"31389011\" lat=\"48.1168690\" lon=\"9.8306449\"/>\n  <node id=\"31389012\" lat=\"48.1220839\" lon=\"9.8258201\"/>\n  <node id=\"31389014\" lat=\"48.1284902\" lon=\"9.8228105\"/>\n  <node id=\"31389015\" lat=\"48.1309367\" lon=\"9.8226289\"/>\n  <node id=\"31389016\" lat=\"48.1325688\" lon=\"9.8227883\"/>\n  <node id=\"31389017\" lat=\"48.1341921\" lon=\"9.8231816\"/>\n  <node id=\"31389018\" lat=\"48.1357600\" lon=\"9.8237745\"/>\n  <node id=\"31389019\" lat=\"48.1382146\" lon=\"9.8251728\"/>\n  <node id=\"31389020\" lat=\"48.1391976\" lon=\"9.8259176\"/>\n  <node id=\"31389021\" lat=\"48.1406059\" lon=\"9.8271990\"/>\n  <node id=\"31389022\" lat=\"48.1424131\" lon=\"9.8290562\"/>\n  <node id=\"31389023\" lat=\"48.1441783\" lon=\"9.8307088\"/>\n  <node id=\"31389024\" lat=\"48.1466224\" lon=\"9.8322041\"/>\n  <node id=\"31389025\" lat=\"48.1489696\" lon=\"9.8338048\"/>\n  <node id=\"31389026\" lat=\"48.1494811\" lon=\"9.8342865\"/>\n  <node id=\"31389027\" lat=\"48.1505021\" lon=\"9.8354325\"/>\n  <node id=\"31389028\" lat=\"48.1517950\" lon=\"9.8373712\"/>\n  <node id=\"31389029\" lat=\"48.1586333\" lon=\"9.8521964\"/>\n  <node id=\"31389030\" lat=\"48.1608186\" lon=\"9.8554086\"/>\n  <node id=\"31389031\" lat=\"48.1637648\" lon=\"9.8583758\"/>\n  <node id=\"31389032\" lat=\"48.1650997\" lon=\"9.8590921\"/>\n  <node id=\"31389034\" lat=\"48.1709095\" lon=\"9.8592402\"/>\n  <node id=\"31389035\" lat=\"48.1721341\" lon=\"9.8594762\"/>\n  <node id=\"31389036\" lat=\"48.1732038\" lon=\"9.8599705\"/>\n  <node id=\"31389037\" lat=\"48.1735888\" lon=\"9.8602494\"/>\n  <node id=\"34666339\" lat=\"48.1450172\" lon=\"9.8282092\">\n    <tag k=\"railway\" v=\"level_crossing\"/>\n  </node>\n  <node id=\"34668956\" lat=\"48.1459158\" lon=\"9.8316495\"/>\n  <node id=\"34668957\" lat=\"48.1459581\" lon=\"9.8318374\"/>\n  <node id=\"34668958\" lat=\"48.1446372\" lon=\"9.8266337\">\n    <tag k=\"railway\" v=\"level_crossing\"/>\n  </node>\n  <node id=\"34668959\" lat=\"48.1392414\" lon=\"9.8082292\">\n    <tag k=\"railway\" v=\"level_crossing\"/>\n  </node>\n  <node id=\"34785041\" lat=\"48.1841681\" lon=\"9.7824813\"/>\n  <node id=\"34785042\" lat=\"48.1838528\" lon=\"9.7832283\"/>\n  <node id=\"34785043\" lat=\"48.1836289\" lon=\"9.7836237\"/>\n  <node id=\"34785045\" lat=\"48.1833908\" lon=\"9.7838754\"/>\n  <node id=\"34785046\" lat=\"48.1830723\" lon=\"9.7841167\"/>\n  <node id=\"34785049\" lat=\"48.1818136\" lon=\"9.7848216\"/>\n  <node id=\"34785051\" lat=\"48.1815724\" lon=\"9.7850424\"/>\n  <node id=\"34785052\" lat=\"48.1812696\" lon=\"9.7853570\">\n    <tag k=\"maxspeed\" v=\"70\"/>\n    <tag k=\"traffic_sign\" v=\"maxspeed\"/>\n    <tag k=\"traffic_sign:direction\" v=\"backward\"/>\n  </node>\n  <node id=\"34785061\" lat=\"48.1781775\" lon=\"9.7911320\"/>\n  <node id=\"34785066\" lat=\"48.1748925\" lon=\"9.7894497\"/>\n  <node id=\"34785115\" lat=\"48.1742142\" lon=\"9.7959565\"/>\n  <node id=\"34785120\" lat=\"48.1732898\" lon=\"9.7974734\"/>\n  <node id=\"34785122\" lat=\"48.1731164\" lon=\"9.7978035\"/>\n  <node id=\"34785124\" lat=\"48.1730727\" lon=\"9.7981809\"/>\n  <node id=\"34785125\" lat=\"48.1733688\" lon=\"9.8004662\"/>\n  <node id=\"34785126\" lat=\"48.1732914\" lon=\"9.8010653\"/>\n  <node id=\"34785129\" lat=\"48.1731372\" lon=\"9.8018945\"/>\n  <node id=\"34785130\" lat=\"48.1726927\" lon=\"9.8026338\"/>\n  <node id=\"34785131\" lat=\"48.1725253\" lon=\"9.8031180\"/>\n  <node id=\"34785132\" lat=\"48.1724770\" lon=\"9.8041302\"/>\n  <node id=\"34785136\" lat=\"48.1726007\" lon=\"9.8056606\"/>\n  <node id=\"34785138\" lat=\"48.1724403\" lon=\"9.8060175\"/>\n  <node id=\"34785139\" lat=\"48.1722038\" lon=\"9.8063727\"/>\n  <node id=\"34785140\" lat=\"48.1720343\" lon=\"9.8065682\"/>\n  <node id=\"34785141\" lat=\"48.1718781\" lon=\"9.8066087\"/>\n  <node id=\"34785143\" lat=\"48.1713448\" lon=\"9.8065539\"/>\n  <node id=\"34785144\" lat=\"48.1712207\" lon=\"9.8066597\"/>\n  <node id=\"34785148\" lat=\"48.1662451\" lon=\"9.8137483\"/>\n  <node id=\"34785153\" lat=\"48.1564315\" lon=\"9.8382180\"/>\n  <node id=\"34785154\" lat=\"48.1560588\" lon=\"9.8414659\"/>\n  <node id=\"34785156\" lat=\"48.1556586\" lon=\"9.8425553\"/>\n  <node id=\"34785157\" lat=\"48.1550493\" lon=\"9.8435208\"/>\n  <node id=\"34785158\" lat=\"48.1545788\" lon=\"9.8441348\"/>\n  <node id=\"34785159\" lat=\"48.1536265\" lon=\"9.8453093\"/>\n  <node id=\"34785161\" lat=\"48.1521743\" lon=\"9.8465498\"/>\n  <node id=\"34785162\" lat=\"48.1524415\" lon=\"9.8476864\"/>\n  <node id=\"49435831\" lat=\"48.1514946\" lon=\"9.8429764\"/>\n  <node id=\"49436782\" lat=\"48.1512686\" lon=\"9.8421567\"/>\n  <node id=\"49436786\" lat=\"48.1500873\" lon=\"9.8382467\"/>\n  <node id=\"49436789\" lat=\"48.1497430\" lon=\"9.8364049\"/>\n  <node id=\"49436799\" lat=\"48.1494829\" lon=\"9.8347754\"/>\n  <node id=\"49436802\" lat=\"48.1493122\" lon=\"9.8353277\"/>\n  <node id=\"49436805\" lat=\"48.1490237\" lon=\"9.8353907\"/>\n  <node id=\"49436813\" lat=\"48.1483072\" lon=\"9.8347740\"/>\n  <node id=\"49436817\" lat=\"48.1479532\" lon=\"9.8342453\"/>\n  <node id=\"49436824\" lat=\"48.1480257\" lon=\"9.8336753\"/>\n  <node id=\"49436828\" lat=\"48.1481026\" lon=\"9.8335600\"/>\n  <node id=\"49436832\" lat=\"48.1482890\" lon=\"9.8334510\"/>\n  <node id=\"49436839\" lat=\"48.1483957\" lon=\"9.8334539\"/>\n  <node id=\"57567810\" lat=\"48.1364174\" lon=\"9.7932383\"/>\n  <node id=\"57567813\" lat=\"48.1365436\" lon=\"9.7931799\"/>\n  <node id=\"57567817\" lat=\"48.1370004\" lon=\"9.7929309\"/>\n  <node id=\"57567818\" lat=\"48.1373903\" lon=\"9.7926742\"/>\n  <node id=\"57567820\" lat=\"48.1390079\" lon=\"9.7915219\"/>\n  <node id=\"57567822\" lat=\"48.1397988\" lon=\"9.7910940\"/>\n  <node id=\"57567823\" lat=\"48.1402749\" lon=\"9.7909295\"/>\n  <node id=\"57567824\" lat=\"48.1409574\" lon=\"9.7908032\"/>\n  <node id=\"57567827\" lat=\"48.1419825\" lon=\"9.7907268\"/>\n  <node id=\"57567829\" lat=\"48.1438978\" lon=\"9.7905671\"/>\n  <node id=\"57567831\" lat=\"48.1450695\" lon=\"9.7904103\"/>\n  <node id=\"57567834\" lat=\"48.1464156\" lon=\"9.7902086\"/>\n  <node id=\"57567837\" lat=\"48.1473402\" lon=\"9.7901835\"/>\n  <node id=\"57567838\" lat=\"48.1479640\" lon=\"9.7902059\">\n    <tag k=\"created_by\" v=\"JOSM\"/>\n  </node>\n  <node id=\"57567840\" lat=\"48.1493104\" lon=\"9.7902454\"/>\n  <node id=\"57567844\" lat=\"48.1505347\" lon=\"9.7902139\"/>\n  <node id=\"57567847\" lat=\"48.1511125\" lon=\"9.7900937\"/>\n  <node id=\"57567852\" lat=\"48.1528512\" lon=\"9.7895811\"/>\n  <node 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v=\"30\"/>\n    <tag k=\"name\" v=\"Lindenstraße\"/>\n    <tag k=\"oneway\" v=\"yes\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n    <tag k=\"traffic_sign\" v=\"DE:274.1[30]\"/>\n    <tag k=\"zone:maxspeed\" v=\"DE:30\"/>\n  </way>\n  <way id=\"930636859\">\n    <nd ref=\"3182562523\"/>\n    <nd ref=\"8628970287\"/>\n    <nd ref=\"8628970286\"/>\n    <nd ref=\"8628970285\"/>\n    <nd ref=\"8628970283\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"lanes\" v=\"1\"/>\n    <tag k=\"maxspeed\" v=\"30\"/>\n    <tag k=\"name\" v=\"Lindenstraße\"/>\n    <tag k=\"oneway\" v=\"yes\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n    <tag k=\"traffic_sign\" v=\"DE:274.1[30]\"/>\n    <tag k=\"zone:maxspeed\" v=\"DE:30\"/>\n  </way>\n  <way id=\"935522644\">\n    <nd ref=\"433029709\"/>\n    <nd ref=\"433029711\"/>\n    <nd ref=\"433029713\"/>\n    <nd ref=\"433029715\"/>\n    <nd ref=\"433029716\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"name\" v=\"Rißhöfer Weg\"/>\n    <tag k=\"surface\" v=\"paved\"/>\n    <tag k=\"width\" v=\"3\"/>\n  </way>\n  <way id=\"935534196\">\n    <nd ref=\"316465100\"/>\n    <nd ref=\"3160927612\"/>\n    <nd ref=\"3160927613\"/>\n    <nd ref=\"316465099\"/>\n    <nd ref=\"316465098\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"lcn\" v=\"yes\"/>\n    <tag k=\"maxspeed\" v=\"30\"/>\n    <tag k=\"name\" v=\"Eichenbergstraße\"/>\n    <tag k=\"surface\" v=\"asphalt\"/>\n  </way>\n  <way id=\"938132626\">\n    <nd ref=\"289698098\"/>\n    <nd ref=\"289698099\"/>\n    <nd ref=\"289698100\"/>\n    <nd ref=\"289698101\"/>\n    <nd ref=\"2934633165\"/>\n    <nd ref=\"2934633167\"/>\n    <nd ref=\"289698103\"/>\n    <tag k=\"highway\" v=\"unclassified\"/>\n    <tag k=\"lanes\" v=\"2\"/>\n    <tag k=\"maxspeed\" v=\"100\"/>\n    <tag k=\"surface\" v=\"paved\"/>\n    <tag k=\"width\" v=\"5\"/>\n  </way>\n  <way id=\"938132627\">\n    <nd ref=\"294194946\"/>\n    <nd ref=\"319881157\"/>\n    <nd ref=\"319881198\"/>\n    <nd ref=\"319881199\"/>\n    <nd ref=\"319881201\"/>\n    <nd ref=\"319881220\"/>\n    <nd ref=\"319881221\"/>\n    <nd ref=\"319881222\"/>\n    <nd ref=\"319881274\"/>\n    <nd ref=\"319881280\"/>\n    <nd ref=\"768060046\"/>\n    <nd ref=\"294194949\"/>\n    <tag k=\"highway\" v=\"unclassified\"/>\n    <tag k=\"lcn\" v=\"yes\"/>\n    <tag k=\"width\" v=\"4\"/>\n  </way>\n  <way id=\"943780290\">\n    <nd ref=\"319879003\"/>\n    <nd ref=\"307077733\"/>\n    <tag k=\"highway\" v=\"residential\"/>\n    <tag k=\"maxspeed\" v=\"30\"/>\n    <tag k=\"maxweight\" v=\"5\"/>\n    <tag k=\"name\" v=\"Alte Straße\"/>\n    <tag k=\"oneway\" v=\"yes\"/>\n  </way>\n\n</osm>\n"
  },
  {
    "path": "selfdrive/mapd/test/test_NodesData.py",
    "content": "import unittest\nimport numpy as np\nfrom selfdrive.mapd.lib.geo import DIRECTION\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.mapd.lib.WayRelation import WayRelation\nfrom selfdrive.mapd.lib.NodesData import nodes_raw_data_array_for_wr, node_calculations, \\\n  spline_curvature_calculations, split_speed_section_by_sign, split_speed_section_by_curv_degree, speed_section, \\\n  speed_limits_for_curvatures_data, is_wr_a_valid_divertion_from_node, SpeedLimitSection, TurnSpeedLimitSection, \\\n  NodesData, NodeDataIdx\nfrom selfdrive.mapd.test.mock_data import mockOSMWay_01_01_LongCurvy, mockNodesData01, mockCurveSectionSin, \\\n  mockCurveSteepCurvChange, mockCurveSteepCurvChangeShort, mockCurveSmoothCurveChange, \\\n  mockOSMWay_02_01_CurvyTownWithIntersections, mockOSMWay_02_02_Divertion_34785115, mockOSMWay_02_03_Short_3_node_way, \\\n  mockRouteData_02_01, mockRouteData_02_02_single_wr, mockRouteData_02_03\nfrom numpy.testing import assert_array_almost_equal\n\n\nclass TestNodesDataFileFunctions(unittest.TestCase):\n  def test_nodes_raw_data_array_for_wr(self):\n    wr = WayRelation(mockOSMWay_01_01_LongCurvy)\n    data_e = np.array([(n.id, n.lat, n.lon, wr.speed_limit) for n in wr.way.nodes], dtype=float)\n    data = nodes_raw_data_array_for_wr(wr)\n\n    assert_array_almost_equal(data, data_e)\n\n  def test_nodes_raw_data_array_for_wr_flips_when_backwards(self):\n    wr = WayRelation(mockOSMWay_01_01_LongCurvy)\n    wr.direction = DIRECTION.BACKWARD\n\n    data_e = np.array([(n.id, n.lat, n.lon, wr.speed_limit) for n in wr.way.nodes], dtype=float)\n    data_e = np.flip(data_e, axis=0)\n\n    data = nodes_raw_data_array_for_wr(wr)\n\n    assert_array_almost_equal(data, data_e)\n\n  def test_nodes_raw_data_array_for_wr_drops_last(self):\n    wr = WayRelation(mockOSMWay_01_01_LongCurvy)\n    data_e = np.array([(n.id, n.lat, n.lon, wr.speed_limit) for n in wr.way.nodes], dtype=float)[:-1]\n    data = nodes_raw_data_array_for_wr(wr, drop_last=True)\n\n    assert_array_almost_equal(data, data_e)\n\n  def test_node_calculations(self):\n    points = mockNodesData01.radians\n\n    v, dp, dn, dr, b = node_calculations(points)\n\n    assert_array_almost_equal(v, mockNodesData01.v)\n    assert_array_almost_equal(dp, mockNodesData01.dp)\n    assert_array_almost_equal(dn, mockNodesData01.dn)\n    assert_array_almost_equal(dr, mockNodesData01.dr)\n    assert_array_almost_equal(b, mockNodesData01.b)\n\n  def test_node_calculations_index_error(self):\n    points = mockNodesData01.radians[:2]\n\n    with self.assertRaises(IndexError):\n      node_calculations(points)\n\n  def test_spline_curvature_calculations(self):\n    vect = mockNodesData01.v\n    dist_prev = mockNodesData01.dp\n\n    curv, curv_ds = spline_curvature_calculations(vect, dist_prev)\n\n    assert_array_almost_equal(curv, mockNodesData01.curv)\n    assert_array_almost_equal(curv_ds, mockNodesData01.curv_ds)\n\n  def test_spline_curvature_calculations_with_route_data(self):\n    mockRouteData_02_01.reset()\n    nodes_data = mockRouteData_02_01._nodes_data\n    vect = np.column_stack((nodes_data[:, 4], nodes_data[:, 5]))\n    dist_prev = nodes_data[:, 6]\n\n    curv, curv_ds = spline_curvature_calculations(vect, dist_prev)\n\n    assert_array_almost_equal(curv, mockRouteData_02_01._curv)\n    assert_array_almost_equal(curv_ds, mockRouteData_02_01._curv_ds)\n\n  def test_split_speed_section_by_sign(self):\n    curv_sec = mockCurveSectionSin.curv_sec\n    new_secs = split_speed_section_by_sign(curv_sec)\n\n    # 3 sections with matching initial and final distance\n    self.assertEqual(len(new_secs), 3)\n    self.assertEqual(new_secs[0][0][2], mockCurveSectionSin.di)\n    self.assertEqual(new_secs[2][-1][2], mockCurveSectionSin.df)\n\n    # All new sections has same sign internally\n    for sec in new_secs:\n      self.assertEqual(np.average(sec, axis=0)[1], sec[0][1])\n\n    # Sections change sign\n    for idx in range(2):\n      self.assertNotEqual(new_secs[idx][0][1], new_secs[idx + 1][0][1])\n\n    # total items consistency\n    lenghts = [len(sec) for sec in new_secs]\n    self.assertEqual(len(curv_sec), sum(lenghts))\n\n  def test_split_speed_section_by_curv_degree(self):\n    curv_sec = mockCurveSteepCurvChange.curv_sec\n    new_secs = split_speed_section_by_curv_degree(curv_sec)\n\n    # 3 sections with matching initial and final distance\n    self.assertEqual(len(new_secs), 3)\n    self.assertEqual(new_secs[0][0][2], mockCurveSteepCurvChange.di)\n    self.assertEqual(new_secs[2][-1][2], mockCurveSteepCurvChange.df)\n\n    # Sections split at the right points\n    split_dist = [sec[-1][2] for sec in new_secs]\n    self.assertListEqual(split_dist, [50., 150., 200.])\n\n  def test_split_speed_section_by_curv_degree_does_nothing_if_short(self):\n    curv_sec = mockCurveSteepCurvChangeShort.curv_sec\n    new_secs = split_speed_section_by_curv_degree(curv_sec)\n\n    self.assertEqual(len(new_secs), 1)\n    assert_array_almost_equal(curv_sec, new_secs[0])\n\n  def test_split_speed_section_by_curv_degree_does_nothing_if_no_substantial_change(self):\n    curv_sec = mockCurveSmoothCurveChange.curv_sec\n    new_secs = split_speed_section_by_curv_degree(curv_sec)\n\n    self.assertEqual(len(new_secs), 1)\n    assert_array_almost_equal(curv_sec, new_secs[0])\n\n  def test_speed_section(self):\n    curv_sec = mockCurveSectionSin.curv_sec\n\n    speed_secs = speed_section(curv_sec)\n    expected = np.array([0., 1000., 1.51657509, 1.])\n\n    assert_array_almost_equal(speed_secs, expected)\n\n  def test_speed_limits_for_curvatures_data(self):\n    curv = mockCurveSectionSin.curv\n    curv_ds = mockCurveSectionSin.curv_ds\n\n    expected = np.array([\n      [10., 490., 1.51657509, 1.],\n      [510., 990., 1.51657509, -1.]])\n    limits = speed_limits_for_curvatures_data(curv, curv_ds)\n\n    assert_array_almost_equal(limits, expected)\n\n  def test_is_wr_a_valid_divertion_from_node(self):\n    wr = WayRelation(mockOSMWay_02_01_CurvyTownWithIntersections)\n    mockOSMWay_02_02_Divertion_34785115.tags['oneway'] = 'yes'\n    wr_div = WayRelation(mockOSMWay_02_02_Divertion_34785115)\n\n    # False if id already in route\n    wr_ids = [wr.id, wr_div.id]\n    self.assertFalse(is_wr_a_valid_divertion_from_node(wr_div, 34785115, wr_ids))\n\n    # True if id not in route, node_id is edge and not prohibited\n    wr_ids = [wr.id, 11111, 22222]\n    self.assertTrue(is_wr_a_valid_divertion_from_node(wr_div, 34785115, wr_ids))\n\n    # False if id not in route, node_id is edge but prohibited (wrong direction from node 319503453)\n    self.assertFalse(is_wr_a_valid_divertion_from_node(wr_div, 319503453, wr_ids))\n\n    # False if id not in route, node_id is not edge\n    self.assertFalse(is_wr_a_valid_divertion_from_node(wr_div, 44444, wr_ids))\n\n\nclass TestSpeedLimitSection(unittest.TestCase):\n  def test_speed_limit_section_init(self):\n    section = SpeedLimitSection(10., 20., 50.)\n\n    self.assertEqual(section.start, 10.)\n    self.assertEqual(section.end, 20.)\n    self.assertEqual(section.value, 50.)\n\n\nclass TestTurnSpeedLimitSection(unittest.TestCase):\n  def test_turn_speed_limit_section_init(self):\n    section = TurnSpeedLimitSection(10., 20., 50., -1.)\n\n    self.assertEqual(section.start, 10.)\n    self.assertEqual(section.end, 20.)\n    self.assertEqual(section.value, 50.)\n    self.assertEqual(section.curv_sign, -1.)\n\n\nclass TestNodesData(unittest.TestCase):\n  def test_init_with_empty_list(self):\n    nd = NodesData([], {})\n\n    self.assertEqual(len(nd._nodes_data), 0)\n    num_diverstions = sum([len(d) for d in nd._divertions])\n    self.assertEqual(num_diverstions, 0)\n    self.assertEqual(len(nd._curvature_speed_sections_data), 0)\n\n  def test_init_with_single_wr_includes_all_wr_nodes(self):\n    mockRouteData_02_02_single_wr.reset()\n    way_relations = mockRouteData_02_02_single_wr.wrs\n    wr_index = mockRouteData_02_02_single_wr.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n\n    assert_array_almost_equal(nd._nodes_data, mockRouteData_02_02_single_wr._nodes_data)\n    assert_array_almost_equal(nd._curvature_speed_sections_data,\n                              mockRouteData_02_02_single_wr._curvature_speed_sections_data)\n    self.assertListEqual(nd._divertions, mockRouteData_02_02_single_wr._divertions)\n    self.assertEqual(len(nd._nodes_data), len(way_relations[0].way.nodes))\n    self.assertEqual(len(nd._curvature_speed_sections_data), 6)\n    num_diverstions = sum([len(d) for d in nd._divertions])\n    self.assertEqual(num_diverstions, 6)\n\n  def test_init_with_less_than_4_nodes(self):\n    wr_t = WayRelation(mockOSMWay_02_03_Short_3_node_way)\n\n    nd = NodesData([wr_t], {})\n\n    self.assertEqual(len(nd._nodes_data), 0)\n    num_diverstions = sum([len(d) for d in nd._divertions])\n    self.assertEqual(num_diverstions, 0)\n    self.assertEqual(len(nd._curvature_speed_sections_data), 0)\n\n  def test_init_with_multiple_wr(self):\n    mockRouteData_02_01.reset()\n    way_relations = mockRouteData_02_01.wrs\n    wr_index = mockRouteData_02_01.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n\n    assert_array_almost_equal(nd._nodes_data, mockRouteData_02_01._nodes_data)\n    assert_array_almost_equal(nd._curvature_speed_sections_data, mockRouteData_02_01._curvature_speed_sections_data)\n    self.assertListEqual(nd._divertions, mockRouteData_02_01._divertions)\n    self.assertEqual(len(nd._curvature_speed_sections_data), 9)\n    num_diverstions = sum([len(d) for d in nd._divertions])\n    self.assertEqual(num_diverstions, 14)\n\n  def test_count(self):\n    mockRouteData_02_01.reset()\n    way_relations = mockRouteData_02_01.wrs\n    wr_index = mockRouteData_02_01.way_collection.wr_index\n    num_n = sum([len(wr.way.nodes) for wr in way_relations]) - len(way_relations) + 1\n\n    nd = NodesData(way_relations, wr_index)\n\n    self.assertEqual(nd.count, num_n)\n\n  def test_get_on_empty(self):\n    wr_t = WayRelation(mockOSMWay_02_03_Short_3_node_way)\n\n    nd = NodesData([wr_t], {})\n    assert_array_almost_equal(nd.get(NodeDataIdx.node_id), np.array([]))\n\n  def test_get_values(self):\n    mockRouteData_02_01.reset()\n    way_relations = mockRouteData_02_01.wrs\n    wr_index = mockRouteData_02_01.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n\n    assert_array_almost_equal(nd.get(NodeDataIdx.node_id), mockRouteData_02_01._nodes_data[:, 0])\n    assert_array_almost_equal(nd.get(NodeDataIdx.lat), mockRouteData_02_01._nodes_data[:, 1])\n    assert_array_almost_equal(nd.get(NodeDataIdx.lon), mockRouteData_02_01._nodes_data[:, 2])\n    assert_array_almost_equal(nd.get(NodeDataIdx.speed_limit), mockRouteData_02_01._nodes_data[:, 3])\n    assert_array_almost_equal(nd.get(NodeDataIdx.x), mockRouteData_02_01._nodes_data[:, 4])\n    assert_array_almost_equal(nd.get(NodeDataIdx.y), mockRouteData_02_01._nodes_data[:, 5])\n    assert_array_almost_equal(nd.get(NodeDataIdx.dist_prev), mockRouteData_02_01._nodes_data[:, 6])\n    assert_array_almost_equal(nd.get(NodeDataIdx.dist_next), mockRouteData_02_01._nodes_data[:, 7])\n    assert_array_almost_equal(nd.get(NodeDataIdx.dist_route), mockRouteData_02_01._nodes_data[:, 8])\n    assert_array_almost_equal(nd.get(NodeDataIdx.bearing), mockRouteData_02_01._nodes_data[:, 9])\n\n  def test_speed_limits_ahead_from_empty(self):\n    wr_t = WayRelation(mockOSMWay_02_03_Short_3_node_way)\n\n    nd = NodesData([wr_t], {})\n    self.assertEqual(len(nd.speed_limits_ahead(1, 10.)), 0)\n\n  def test_speed_limits_ahead(self):\n    mockRouteData_02_03.reset()\n    way_relations = mockRouteData_02_03.wrs\n    wr_index = mockRouteData_02_03.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n\n    # empty when ahead_idx is none.\n    self.assertEqual(len(nd.speed_limits_ahead(None, 10.)), 0)\n\n    # All limist from 0\n    all_limits = nd.speed_limits_ahead(1, nd.get(NodeDataIdx.dist_next)[0])\n    self.assertEqual(len(all_limits), 4)  # 4 limits on this mock road.\n    self.assertListEqual([sl.value for sl in all_limits], [v * CV.KPH_TO_MS for v in [50, 100, 50, 100]])\n    for idx, sl in enumerate(all_limits):\n      self.assertTrue(sl.end > sl.start)\n      self.assertTrue(sl.value > 0.)\n      if idx == 0:\n        self.assertEqual(sl.start, 0.)\n      else:\n        self.assertEqual(sl.start, all_limits[idx - 1].end)\n        self.assertNotEqual(sl.value, all_limits[idx - 1].value)\n\n  def test_distance_to_end_from_empty(self):\n    wr_t = WayRelation(mockOSMWay_02_03_Short_3_node_way)\n\n    nd = NodesData([wr_t], {})\n    self.assertIsNone(nd.distance_to_end(1, 10.))\n\n  def test_distance_to_end(self):\n    mockRouteData_02_03.reset()\n    way_relations = mockRouteData_02_03.wrs\n    wr_index = mockRouteData_02_03.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n\n    # none when ahead_idx is none.\n    self.assertIsNone(nd.distance_to_end(None, 10.))\n\n    # From the begining\n    expected = np.sum(nd.get(NodeDataIdx.dist_next))\n    self.assertAlmostEqual(nd.distance_to_end(1, nd.get(NodeDataIdx.dist_next)[0]), expected)\n    self.assertAlmostEqual(nd.get(NodeDataIdx.dist_route)[-1], expected)\n\n    # From the node next to last\n    expected = nd.get(NodeDataIdx.dist_next)[-2]\n    self.assertAlmostEqual(nd.distance_to_end(nd.count - 2, 0.), expected)\n\n  def test_distance_to_node(self):\n    mockRouteData_02_03.reset()\n    way_relations = mockRouteData_02_03.wrs\n    wr_index = mockRouteData_02_03.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n    dist_to_node_ahead = 10.\n    node_id = 1887995486  # Some node id in the middle of the way. idx 50\n    node_idx = np.nonzero(nd.get(NodeDataIdx.node_id) == node_id)[0][0]\n\n    # none when ahead_idx is none.\n    self.assertIsNone(nd.distance_to_node(node_id, None, dist_to_node_ahead))\n\n    # From the begining\n    expected = nd.get(NodeDataIdx.dist_route)[node_idx]\n    self.assertAlmostEqual(nd.distance_to_node(node_id, 1, nd.get(NodeDataIdx.dist_next)[0]), expected)\n\n    # From the end\n    expected = -np.sum(nd.get(NodeDataIdx.dist_next)[node_idx:])\n    self.assertAlmostEqual(nd.distance_to_node(node_id, len(nd.get(NodeDataIdx.node_id)) - 1, 0.), expected)\n\n    # From some node behind including dist to node ahead\n    ahead_idx = node_idx - 10\n    expected = np.sum(nd.get(NodeDataIdx.dist_next)[ahead_idx:node_idx]) + dist_to_node_ahead\n    self.assertAlmostEqual(nd.distance_to_node(node_id, ahead_idx, dist_to_node_ahead), expected)\n\n    # From some node ahead including dist to node ahead\n    ahead_idx = node_idx + 10\n    expected = -np.sum(nd.get(NodeDataIdx.dist_next)[node_idx:ahead_idx]) + dist_to_node_ahead\n    self.assertAlmostEqual(nd.distance_to_node(node_id, ahead_idx, dist_to_node_ahead), expected)\n\n  def test_test(self):\n    mockRouteData_03_01.reset()\n    way_relations = mockRouteData_03_01.wrs\n    wr_index = mockRouteData_03_01.way_collection.wr_index\n\n    nd = NodesData(way_relations, wr_index)\n\n    print(nd._nodes_data[:, 0])\n\n    all_limits = nd.curvatures_speed_limit_sections_ahead(16, 0.)\n    print(all_limits)\n\n# TODO: Missing tests for curvatures_speed_limit_sections_ahead and possible_divertions\n"
  },
  {
    "path": "selfdrive/mapd/test/test_WayRelation.py",
    "content": "import copy\nimport unittest\nimport numpy as np\nfrom unittest import mock\nfrom numpy.testing import assert_array_almost_equal\nfrom datetime import datetime as dt, timezone, timedelta\nfrom selfdrive.config import Conversions as CV\nfrom selfdrive.mapd.lib.WayRelation import WayRelation, is_osm_time_condition_active, \\\n  conditional_speed_limit_for_osm_tag_limit_string, speed_limit_for_osm_tag_limit_string\nfrom selfdrive.mapd.config import LANE_WIDTH\nfrom selfdrive.mapd.lib.geo import DIRECTION, R, vectors\nfrom selfdrive.mapd.test.mock_data import mockOSMWay_01_01_LongCurvy, mockOSMWay_01_02_Loop, \\\n  mockOSMWay_02_01_CurvyTownWithIntersections\n\n\nclass TestWayRelationFileFunctions(unittest.TestCase):\n  def test_speed_limit_for_osm_tag_limit_string(self):\n    values = [\n      None,  # Invalid\n      \"1000\",  # Invalid\n      \"60 kph\",  # Invalid\n      \"100\",\n      \"30 mph\",\n      \"DE:zone:40\",\n      \"DE:zone:50 mph\",\n      \"AR:urban\",\n      \"CZ:pedestrian_zone\",\n      \"DK:urban\",\n      \"DK:rural\",\n      \"DK:motorway\",\n      \"DE:living_street\",\n      \"DE:residential\",\n      \"DE:urban\",\n      \"DE:rural\",\n      \"DE:trunk\",  # No limit\n      \"DE:motorway\",  # No limit\n      \"GB:nsl_restricted\",\n      \"GB:nsl_single\",\n      \"GB:nsl_dual\",\n      \"GB:motorway\",\n      \"GB:invalid\",  # Invalid\n    ]\n\n    expected = [\n      0.,\n      0.,\n      0.,\n      100. * CV.KPH_TO_MS,\n      30. * CV.MPH_TO_MS,\n      40. * CV.KPH_TO_MS,\n      50. * CV.MPH_TO_MS,\n      40. * CV.KPH_TO_MS,\n      20. * CV.KPH_TO_MS,\n      50. * CV.KPH_TO_MS,\n      80. * CV.KPH_TO_MS,\n      130. * CV.KPH_TO_MS,\n      7. * CV.KPH_TO_MS,\n      30. * CV.KPH_TO_MS,\n      50. * CV.KPH_TO_MS,\n      100. * CV.KPH_TO_MS,\n      0.,\n      0.,\n      30. * CV.MPH_TO_MS,\n      60. * CV.MPH_TO_MS,\n      70. * CV.MPH_TO_MS,\n      70. * CV.MPH_TO_MS,\n      0.,\n    ]\n\n    result = [speed_limit_for_osm_tag_limit_string(sls) for sls in values]\n\n    self.assertEqual(result, expected)\n\n  @mock.patch('selfdrive.mapd.lib.WayRelation.dt')\n  def test_is_osm_time_condition_active(self, mock_dt):\n    tz = timezone(timedelta(hours=1), 'berlin')\n    wed_10_10_am = dt(2021, 9, 1, 10, 10, 0)\n    mock_dt.now.return_value = wed_10_10_am\n    mock_dt.tzinfo = tz\n    mock_dt.combine = dt.combine\n    mock_dt.strptime = dt.strptime\n\n    values = [\n      \"WE\",  # Invalid\n      \"We\",\n      \"Mo\",\n      \"Fr\",\n      \"Tu-Th\",\n      \"10:00\",  # Invalid\n      \"10:00-10:30\",\n      \"We 10:00-10:30\",\n      \"SU 10:00-10:30\",  # Valid, SU string not considered a day string.\n      \"Sa 10:00-10:30\",\n      \"Tu-Th 10:00-10:30\",\n    ]\n\n    expected = [\n      False,  # Invalid\n      True,\n      False,\n      False,\n      True,\n      False,  # Invalid\n      True,\n      True,\n      True,\n      False,\n      True,\n    ]\n\n    result = [is_osm_time_condition_active(cs) for cs in values]\n\n    self.assertEqual(result, expected)\n\n  @mock.patch('selfdrive.mapd.lib.WayRelation.dt')\n  def test_conditional_speed_limit_for_osm_tag_limit_string(self, mock_dt):\n    tz = timezone(timedelta(hours=1), 'berlin')\n    wed_10_10_am = dt(2021, 9, 1, 10, 10, 0)\n    mock_dt.now.return_value = wed_10_10_am\n    mock_dt.tzinfo = tz\n    mock_dt.combine = dt.combine\n    mock_dt.strptime = dt.strptime\n\n    values = [\n      None,  # Invalid\n      \"Hola\",  # Invalid\n      \"100 @ (WE)\",  # Invalid\n      \"x @ (We)\",  # Invalid\n      \"100 @ (We)\",\n      \"100 @ (Mo)\",\n      \"100 @ (Fr)\",\n      \"100 @ (Tu-Th)\",\n      \"100 @ (10:00)\",  # Invalid\n      \"100 @ (10:00-10:30)\",\n      \"100 @ (We 10:00-10:30)\",\n      \"100 @ (SU 10:00-10:30)\",  # Valid, SU string not considered a day string.\n      \"100 @ (Sa 10:00-10:30)\",\n      \"100 @ (Tu-Th 10:00-10:30)\",\n      \"100 @ (Mo-Th;Su)\",\n      \"100 @ (Mo Th;Fr-Sa)\",\n      \"100 @ (Fr-Su;Mo-Tu)\",\n      \"100 @ (10:00-10:30;15:00-16:00)\",\n      \"100 @ (We;Mo-Tu)\",\n      \"100 @ (We 10:00-10:30;Th 15:00-16:00)\",\n      \"100 @ (Tu 10:00-10:30;Th 15:00-16:00)\",\n    ]\n\n    _100 = 100. * CV.KPH_TO_MS\n\n    expected = [\n      0.,  # Invalid\n      0.,  # Invalid\n      0.,  # Invalid\n      0.,  # Invalid\n      _100,\n      0.,\n      0.,\n      _100,\n      0.,  # Invalid\n      _100,\n      _100,\n      _100,\n      0.,\n      _100,\n      _100,\n      _100,\n      0.,\n      _100,\n      _100,\n      _100,\n      0.\n    ]\n\n    result = [conditional_speed_limit_for_osm_tag_limit_string(ls) for ls in values]\n\n    self.assertEqual(result, expected)\n\n\nclass TestWayRelation(unittest.TestCase):\n  def test_way_relation_init(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n\n    nodes_np_expected = np.radians(np.array([[nd.lat, nd.lon] for nd in wayRelation.way.nodes], dtype=float))\n    v = vectors(wayRelation._nodes_np)\n    way_distances_expected = np.linalg.norm(v * R, axis=1)\n    way_bearings_expected = np.arctan2(v[:, 0], v[:, 1])\n    bbox_expected = np.array([\n      [0.91321784, 0.2346417],\n      [0.91344672, 0.23475751]])\n\n    self.assertEqual(wayRelation.way.id, 179532213)\n    self.assertIsNone(wayRelation.parent_wr_id)\n    self.assertEqual(wayRelation.direction, DIRECTION.NONE)\n    self.assertEqual(wayRelation._speed_limit, None)\n    self.assertEqual(wayRelation._one_way, 'yes')\n    self.assertEqual(wayRelation.name, None)\n    self.assertEqual(wayRelation.ref, 'B 96')\n    self.assertEqual(wayRelation.highway_type, 'trunk')\n    self.assertEqual(wayRelation.highway_rank, 10)\n    self.assertEqual(wayRelation.lanes, 2)\n    assert_array_almost_equal(wayRelation._nodes_np, nodes_np_expected)\n    assert_array_almost_equal(wayRelation._way_distances, way_distances_expected)\n    assert_array_almost_equal(wayRelation._way_bearings, way_bearings_expected)\n    assert_array_almost_equal(wayRelation.bbox, bbox_expected)\n    self.assertEqual(wayRelation.edge_nodes_ids, [wayRelation.way.nodes[0].id, wayRelation.way.nodes[-1].id])\n\n  def test_way_relation_init_with_parent(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy, parent=WayRelation(mockOSMWay_01_02_Loop))\n\n    self.assertEqual(wayRelation.way.id, 179532213)\n    self.assertEqual(wayRelation.parent_wr_id, 29233907)\n\n  def test_way_relation_equality(self):\n    wayRelation1 = WayRelation(mockOSMWay_01_01_LongCurvy)\n    wayRelation2 = copy.copy(wayRelation1)\n    wayRelation3 = copy.deepcopy(wayRelation1)\n    wayRelation3.way.id = 123\n\n    self.assertEqual(wayRelation1, wayRelation2)\n    self.assertNotEqual(wayRelation1, wayRelation3)\n\n  def test_way_relation_reset_location_variables(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    self.make_wayRelation_location_dirty(wayRelation)\n\n    wayRelation.reset_location_variables()\n\n    self.assert_wayRelation_variables_reset(wayRelation)\n\n  def test_way_relation_id(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n\n    self.assertEqual(wayRelation.id, 179532213)\n\n  def test_way_relation_road_name(self):\n    # road name when no tag for name or ref\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n    self.assertIsNone(wayRelation.road_name)\n    # road name based on ref tag\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    self.assertEqual(wayRelation.road_name, \"B 96\")\n    # road name based on name tag\n    wayRelation = WayRelation(mockOSMWay_02_01_CurvyTownWithIntersections)\n    self.assertEqual(wayRelation.road_name, \"Hauptstraße\")\n\n  def test_way_relation_update_resets_on_update(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    self.make_wayRelation_location_dirty(wayRelation)\n    location_rad = np.array([0., 0.])  # Location outside bbox\n\n    wayRelation.update(location_rad, 0., 10.)\n\n    self.assertFalse(wayRelation.is_location_in_bbox(location_rad))\n    self.assert_wayRelation_variables_reset(wayRelation)\n\n  def test_way_relation_update_only_resets_if_no_possible_found(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    location_rad = wayRelation.bbox[0]  # Location inside bbox but outside actual way (due to padding)\n\n    wayRelation.update(location_rad, 0., 10.)\n\n    self.assertTrue(wayRelation.is_location_in_bbox(location_rad))\n    self.assert_wayRelation_variables_reset(wayRelation)\n\n  def test_way_relation_updates_in_the_correct_direction_with_correct_property_values(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    location_rad = np.radians(np.array([52.32855593146639, 13.445320150125069]))\n    bearing_rad = 0.\n\n    wayRelation.update(location_rad, bearing_rad, 10.)\n\n    self.assertTrue(wayRelation.is_location_in_bbox(location_rad))\n    self.assertEqual(wayRelation.direction, DIRECTION.FORWARD)\n    self.assertEqual(wayRelation.ahead_idx, 17)\n    self.assertEqual(wayRelation.behind_idx, 16)\n    self.assertAlmostEqual(wayRelation._distance_to_way, 3.43290781621360)\n    self.assertAlmostEqual(wayRelation._active_bearing_delta, 0.320717420388962)\n    self.assertAlmostEqual(wayRelation.distance_to_node_ahead, 25.4998961709014)\n    self.assertTrue(wayRelation.active)\n    self.assertFalse(wayRelation.diverting)\n    assert_array_almost_equal(wayRelation.location_rad, location_rad)\n    self.assertEqual(wayRelation.bearing_rad, bearing_rad)\n    self.assertIsNone(wayRelation._speed_limit)\n\n    bearing_rad = 180.\n\n    wayRelation.update(location_rad, bearing_rad, 10.)\n\n    self.assertTrue(wayRelation.is_location_in_bbox(location_rad))\n    self.assertEqual(wayRelation.direction, DIRECTION.BACKWARD)\n    self.assertEqual(wayRelation.ahead_idx, 16)\n    self.assertEqual(wayRelation.behind_idx, 17)\n    self.assertAlmostEqual(wayRelation._distance_to_way, 3.43290781621360)\n    self.assertAlmostEqual(wayRelation._active_bearing_delta, 0.9507682562504284)\n    self.assertAlmostEqual(wayRelation.distance_to_node_ahead, 11.11623371145368)\n    self.assertTrue(wayRelation.active)\n    self.assertFalse(wayRelation.diverting)\n    assert_array_almost_equal(wayRelation.location_rad, location_rad)\n    self.assertEqual(wayRelation.bearing_rad, bearing_rad)\n    self.assertIsNone(wayRelation._speed_limit)\n\n  def test_way_relation_updates_with_location_closest_to_way_when_multiple_possible(self):\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n    location_rad = np.radians(np.array([52.313303275461564, 13.437729236325788]))\n    bearing_rad = np.radians(10.)\n\n    wayRelation.update(location_rad, bearing_rad, 10.)\n\n    self.assertTrue(wayRelation.is_location_in_bbox(location_rad))\n    self.assertEqual(wayRelation.direction, DIRECTION.BACKWARD)\n    self.assertEqual(wayRelation.ahead_idx, 26)\n    self.assertEqual(wayRelation.behind_idx, 27)\n    self.assertAlmostEqual(wayRelation._distance_to_way, 10.151775235257011)\n    self.assertAlmostEqual(wayRelation._active_bearing_delta, 0.06371131069242782)\n    self.assertAlmostEqual(wayRelation.distance_to_node_ahead, 10.174073707120915)\n    self.assertTrue(wayRelation.active)\n    self.assertFalse(wayRelation.diverting)\n    assert_array_almost_equal(wayRelation.location_rad, location_rad)\n    self.assertEqual(wayRelation.bearing_rad, bearing_rad)\n    self.assertIsNone(wayRelation._speed_limit)\n\n  def test_way_relation_updates_will_become_inactive_if_too_far_from_way(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    # Location is 24.9 mts away from the way. There are 2 Lanes in this way.\n    location_rad = np.radians(np.array([52.328634560607746, 13.445609877522788]))\n    location_stdev = 5.5  # threshold is 4 * location_stdev + LANE_WIDTH\n    distance_threshold = 4. * location_stdev + wayRelation.lanes * LANE_WIDTH / 2.\n\n    wayRelation.update(location_rad, 0., location_stdev)\n    self.assertTrue(wayRelation.active)\n    self.assertLess(wayRelation._distance_to_way, distance_threshold)\n\n    location_stdev = 5.\n\n    wayRelation.update(location_rad, 0., location_stdev)\n    self.assertFalse(wayRelation.active)\n\n  def test_way_relation_updates_will_update_diverting_correctly(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    # Location is 24.9 mts away from the way. There are 2 Lanes in this way.\n    location_rad = np.radians(np.array([52.328634560607746, 13.445609877522788]))\n    location_stdev = 11.\n    distance_threshold = 2. * location_stdev + wayRelation.lanes * LANE_WIDTH / 2.\n\n    wayRelation.update(location_rad, 0., location_stdev)\n\n    self.assertLess(wayRelation._distance_to_way, distance_threshold)\n    self.assertFalse(wayRelation.diverting)\n\n    location_stdev = 10.\n    distance_threshold = 2. * location_stdev + wayRelation.lanes * LANE_WIDTH / 2.\n\n    wayRelation.update(location_rad, 0., location_stdev)\n\n    self.assertGreater(wayRelation._distance_to_way, distance_threshold)\n    self.assertTrue(wayRelation.diverting)\n\n  def test_way_relation_update_direction_from_starting_node_resets_speed_limit(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    wayRelation._speed_limit = 10.\n\n    wayRelation.update_direction_from_starting_node(wayRelation.way.nodes[0].id)\n\n    self.assertIsNone(wayRelation._speed_limit)\n\n  def test_way_relation_update_direction_from_starting_node_updates_correctly(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    wayRelation.update_direction_from_starting_node(wayRelation.way.nodes[0].id)\n    self.assertEqual(wayRelation.direction, DIRECTION.FORWARD)\n\n    wayRelation.update_direction_from_starting_node(wayRelation.way.nodes[-1].id)\n    self.assertEqual(wayRelation.direction, DIRECTION.BACKWARD)\n\n    wayRelation.update_direction_from_starting_node(0)\n    self.assertEqual(wayRelation.direction, DIRECTION.NONE)\n\n  def test_way_relation_is_location_in_bbox(self):\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n    bbox = wayRelation.bbox\n\n    loc_avg = np.average(bbox, axis=0)\n    loc_min = np.min(bbox, axis=0)\n    loc_max = np.max(bbox, axis=0)\n\n    locations = [\n      loc_avg,\n      loc_min,\n      loc_max,\n      [loc_avg[0], loc_min[1]],\n      [loc_avg[0], loc_max[1]],\n      [loc_min[0], loc_avg[1]],\n      [loc_max[0], loc_avg[1]],\n      loc_min - 0.1,\n      loc_max + 0.1,\n      [loc_avg[0], loc_min[1] - 0.1],\n      [loc_avg[0], loc_max[1] + 0.1],\n      [loc_min[0] - 0.1, loc_avg[1]],\n      [loc_max[0] + 0.1, loc_avg[1]],\n    ]\n\n    is_in = [wayRelation.is_location_in_bbox(loc) for loc in locations]\n\n    self.assertEqual(is_in, [True, True, True, True, True, True, True, False, False, False, False, False, False])\n\n  def test_way_relation_speed_limit_when_set(self):\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n    wayRelation._speed_limit = 10.\n\n    self.assertEqual(wayRelation.speed_limit, 10.)\n\n  @mock.patch('selfdrive.mapd.lib.WayRelation.dt')\n  def test_way_relation_speed_limit_conditional(self, mock_dt):\n    tz = timezone(timedelta(hours=1), 'berlin')\n    wed_10_10_am = dt(2021, 9, 1, 10, 10, 0)\n    mock_dt.now.return_value = wed_10_10_am\n    mock_dt.tzinfo = tz\n    mock_dt.combine = dt.combine\n    mock_dt.strptime = dt.strptime\n\n    # Reset all tags before teting\n    mockOSMWay_01_02_Loop.tags = {}\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n\n    # No Value\n    self.assertEqual(wayRelation.speed_limit, 0.)\n\n    # Value on both directions\n    wayRelation._speed_limit = None\n    wayRelation.way.tags[\"maxspeed:conditional\"] = \"100 @ (We 10:00-10:30)\"\n    self.assertEqual(wayRelation.speed_limit, 100. * CV.KPH_TO_MS)\n\n    # Value on forward\n    wayRelation.way.tags.pop(\"maxspeed:conditional\")\n    wayRelation._speed_limit = None\n    wayRelation.direction = DIRECTION.FORWARD\n    self.assertEqual(wayRelation.speed_limit, 0.)\n\n    wayRelation._speed_limit = None\n    wayRelation.way.tags[\"maxspeed:forward:conditional\"] = \"100 @ (We 10:00-10:30)\"\n    self.assertEqual(wayRelation.speed_limit, 100. * CV.KPH_TO_MS)\n\n    # Value on backward\n    wayRelation._speed_limit = None\n    wayRelation.direction = DIRECTION.BACKWARD\n    self.assertEqual(wayRelation.speed_limit, 0.)\n\n    wayRelation._speed_limit = None\n    wayRelation.way.tags[\"maxspeed:backward:conditional\"] = \"100 @ (We 10:00-10:30)\"\n    self.assertEqual(wayRelation.speed_limit, 100. * CV.KPH_TO_MS)\n\n  def test_way_relation_speed_limit_maxspeed(self):\n    # Reset all tags before teting\n    mockOSMWay_01_02_Loop.tags = {}\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n\n    # No Value\n    self.assertEqual(wayRelation.speed_limit, 0.)\n\n    # Value on both directions\n    wayRelation._speed_limit = None\n    wayRelation.way.tags[\"maxspeed\"] = \"100\"\n    self.assertEqual(wayRelation.speed_limit, 100. * CV.KPH_TO_MS)\n\n    # Value on forward\n    wayRelation.way.tags.pop(\"maxspeed\")\n    wayRelation._speed_limit = None\n    wayRelation.direction = DIRECTION.FORWARD\n    self.assertEqual(wayRelation.speed_limit, 0.)\n\n    wayRelation._speed_limit = None\n    wayRelation.way.tags[\"maxspeed:forward\"] = \"100\"\n    self.assertEqual(wayRelation.speed_limit, 100. * CV.KPH_TO_MS)\n\n    # Value on backward\n    wayRelation._speed_limit = None\n    wayRelation.direction = DIRECTION.BACKWARD\n    self.assertEqual(wayRelation.speed_limit, 0.)\n\n    wayRelation._speed_limit = None\n    wayRelation.way.tags[\"maxspeed:backward\"] = \"100\"\n    self.assertEqual(wayRelation.speed_limit, 100. * CV.KPH_TO_MS)\n\n  def test_way_relation_active_bearing_delta_reflects_internal_value(self):\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n    wayRelation._active_bearing_delta = 10.\n    self.assertEqual(wayRelation.active_bearing_delta, 10.)\n\n  def test_way_relation_is_one_way(self):\n    # Setup initial tags\n    mockOSMWay_01_02_Loop.tags = {\n      'oneway': 'yes',\n      'highway': 'unclassified'\n    }\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n\n    # oneway = yes\n    self.assertTrue(wayRelation.is_one_way)\n\n    # oneway non existing\n    wayRelation._one_way = None\n    self.assertFalse(wayRelation.is_one_way)\n\n    # highway = motorway\n    wayRelation.highway_type = 'motorway'\n    self.assertTrue(wayRelation.is_one_way)\n\n  def test_way_relation_is_prohibited(self):\n    # Setup initial tags\n    mockOSMWay_01_02_Loop.tags = {\n      'oneway': 'yes'\n    }\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n\n    # Direction undefined\n    wayRelation.direction = DIRECTION.NONE\n    self.assertTrue(wayRelation.is_prohibited)\n\n    # oneway = yes\n    wayRelation.direction = DIRECTION.BACKWARD\n    self.assertTrue(wayRelation.is_prohibited)\n\n    wayRelation.direction = DIRECTION.FORWARD\n    self.assertFalse(wayRelation.is_prohibited)\n\n    # oneway non existing\n    wayRelation._one_way = None\n    self.assertFalse(wayRelation.is_one_way)\n\n    wayRelation.direction = DIRECTION.BACKWARD\n    self.assertFalse(wayRelation.is_prohibited)\n\n  def test_way_relation_distance_to_way_reflects_internal_value(self):\n    wayRelation = WayRelation(mockOSMWay_01_02_Loop)\n    wayRelation._distance_to_way = 10.\n    self.assertEqual(wayRelation.distance_to_way, 10.)\n\n  def test_way_relation_node_ahead(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    # ahead_ids is None on init\n    self.assertIsNone(wayRelation.node_ahead)\n\n    wayRelation.ahead_idx = 15\n    self.assertEqual(wayRelation.node_ahead, wayRelation.way.nodes[15])\n\n  def test_way_relation_last_node(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    # direction is NONE on init\n    self.assertIsNone(wayRelation.last_node)\n\n    # forward\n    wayRelation.direction = DIRECTION.FORWARD\n    self.assertEqual(wayRelation.last_node, wayRelation.way.nodes[-1])\n\n    # backward\n    wayRelation.direction = DIRECTION.BACKWARD\n    self.assertEqual(wayRelation.last_node, wayRelation.way.nodes[0])\n\n  def test_way_relation_last_node_coordinates(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    # direction is NONE on init\n    self.assertIsNone(wayRelation.last_node_coordinates)\n\n    # forward\n    wayRelation.direction = DIRECTION.FORWARD\n    coords = np.radians(np.array([wayRelation.way.nodes[-1].lat, wayRelation.way.nodes[-1].lon], dtype=float))\n    assert_array_almost_equal(wayRelation.last_node_coordinates, coords)\n\n    # backward\n    wayRelation.direction = DIRECTION.BACKWARD\n    coords = np.radians(np.array([wayRelation.way.nodes[0].lat, wayRelation.way.nodes[0].lon], dtype=float))\n    assert_array_almost_equal(wayRelation.last_node_coordinates, coords)\n\n  def test_way_relation_node_before_edge_coordinates(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n\n    coords = wayRelation.node_before_edge_coordinates(0)\n    assert_array_almost_equal(coords, np.array([0., 0.]))\n\n    coords = wayRelation.node_before_edge_coordinates(wayRelation.way.nodes[0].id)\n    coords_e = np.radians(np.array([wayRelation.way.nodes[1].lat, wayRelation.way.nodes[1].lon], dtype=float))\n    assert_array_almost_equal(coords, coords_e)\n\n    coords = wayRelation.node_before_edge_coordinates(wayRelation.way.nodes[-1].id)\n    coords_e = np.radians(np.array([wayRelation.way.nodes[-2].lat, wayRelation.way.nodes[-2].lon], dtype=float))\n    assert_array_almost_equal(coords, coords_e)\n\n  def test_way_relation_split_no_matching_node(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n\n    wrs = wayRelation.split(0)\n    self.assertEqual(len(wrs), 0)\n\n  def test_way_relation_split_use_correct_ids(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n\n    wrs = wayRelation.split(wayRelation._nodes_ids[5], [-100, -200])\n    self.assertEqual(wrs[0].id, -100)\n    self.assertEqual(wrs[1].id, -200)\n\n  def test_way_relation_split_on_edge_node(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    edge_node_ids = wayRelation.edge_nodes_ids\n\n    for edge_node_id in edge_node_ids:\n      wrs = wayRelation.split(edge_node_id)\n      self.assertEqual(len(wrs), 1)\n      self.assertEqual(wrs[0], wayRelation)\n      self.assertEqual(wrs[0].way.tags, wayRelation.way.tags)\n\n  def test_way_relation_split_on_internal_node(self):\n    wayRelation = WayRelation(mockOSMWay_01_01_LongCurvy)\n    way_ids = [-10, -20]\n\n    for idx, node_id in enumerate(wayRelation._nodes_ids):\n      if idx == 0 or idx == len(wayRelation._nodes_ids) - 1:\n        continue\n      wrs = wayRelation.split(node_id, way_ids)\n      self.assertEqual(len(wrs), 2)\n      assert_array_almost_equal(wrs[0]._nodes_ids, wayRelation._nodes_ids[:idx + 1])\n      assert_array_almost_equal(wrs[1]._nodes_ids, wayRelation._nodes_ids[idx:])\n      self.assertIn(node_id, wrs[0].edge_nodes_ids)\n      self.assertIn(node_id, wrs[1].edge_nodes_ids)\n      self.assertEqual(wrs[0].way.tags, wayRelation.way.tags)\n      self.assertEqual(wrs[1].way.tags, wayRelation.way.tags)\n      self.assertEqual(way_ids, [wr.id for wr in wrs])\n\n  # Helpers\n  def make_wayRelation_location_dirty(self, wayRelation):\n    wayRelation.distance_to_node_ahead = 10.\n    wayRelation.location_rad = 0.8\n    wayRelation.bearing_rad = 2.\n    wayRelation.active = True\n    wayRelation.diverting = True\n    wayRelation.ahead_idx = 5\n    wayRelation.behind_idx = 4\n    wayRelation._active_bearing_delta = 3.\n    wayRelation._distance_to_way = 20.\n\n  def assert_wayRelation_variables_reset(self, wayRelation):\n    self.assertEqual(wayRelation.distance_to_node_ahead, 0.)\n    self.assertIsNone(wayRelation.location_rad)\n    self.assertIsNone(wayRelation.bearing_rad)\n    self.assertFalse(wayRelation.active)\n    self.assertFalse(wayRelation.diverting)\n    self.assertIsNone(wayRelation.ahead_idx)\n    self.assertIsNone(wayRelation.behind_idx)\n    self.assertIsNone(wayRelation._active_bearing_delta)\n    self.assertIsNone(wayRelation._distance_to_way)\n\n  def wayRelation_mid_point_rad(self, wayRelation):\n    return np.average(wayRelation.bbox, axis=0)\n"
  },
  {
    "path": "selfdrive/mapd/test/test_geo.py",
    "content": "import unittest\nfrom selfdrive.mapd.lib.geo import vectors, ref_vectors, bearing_to_points, distance_to_points\nimport numpy as np\nfrom numpy.testing import assert_array_almost_equal\nfrom selfdrive.mapd.test.mock_data import mockNodesData01\n\n\nclass TestMapsdGeoLibrary(unittest.TestCase):\n  def test_vectors(self):\n    points = mockNodesData01.radians\n    expected = np.array([\n      [-1.34011951e-05, 1.00776468e-05],\n      [-5.83610920e-06, 4.41046897e-06],\n      [-7.83348567e-06, 5.94114032e-06],\n      [-7.08560788e-06, 5.30408795e-06],\n      [-6.57632550e-06, 4.05791838e-06],\n      [-1.16077872e-06, 6.91151252e-07],\n      [-1.53178098e-05, 9.62215139e-06],\n      [-5.76314175e-06, 3.55176643e-06],\n      [-1.61124141e-05, 9.86127759e-06],\n      [-1.48006628e-05, 8.58192512e-06],\n      [-1.72237209e-06, 1.60570482e-06],\n      [-8.68985228e-06, 9.22062311e-06],\n      [-1.42922812e-06, 1.51494711e-06],\n      [-3.39761486e-06, 2.57087743e-06],\n      [-2.75467373e-06, 1.28631255e-06],\n      [-1.57501989e-05, 5.72309451e-06],\n      [-2.52143954e-06, 1.34565295e-06],\n      [-1.65278643e-06, 1.28630942e-06],\n      [-2.22196114e-05, 1.64360838e-05],\n      [-5.88675934e-06, 4.08234746e-06],\n      [-1.83673390e-06, 1.46782408e-06],\n      [-1.55004206e-06, 1.51843800e-06],\n      [-1.20451533e-06, 2.06298011e-06],\n      [-1.91801338e-06, 4.64083285e-06],\n      [-2.38653483e-06, 5.60076524e-06],\n      [-1.65269781e-06, 5.78402290e-06],\n      [-3.66908309e-07, 2.75412965e-06],\n      [0.00000000e+00, 1.92858882e-06],\n      [9.09242615e-08, 2.66162711e-06],\n      [3.14490354e-07, 1.53065382e-06],\n      [8.66452477e-08, 4.83456208e-07],\n      [2.41750593e-07, 1.10828411e-06],\n      [7.43745228e-06, 1.27618831e-05],\n      [5.59968054e-06, 9.63947367e-06],\n      [2.01951467e-06, 2.75413219e-06],\n      [4.59952643e-07, 6.42281301e-07],\n      [1.74353749e-06, 1.74533121e-06],\n      [2.57144338e-06, 2.11185266e-06],\n      [1.46893187e-05, 1.11999169e-05],\n      [3.84659229e-05, 2.85527952e-05],\n      [2.71627936e-05, 1.98727946e-05],\n      [8.44632540e-06, 6.15058628e-06],\n      [2.29420323e-06, 1.92859222e-06],\n      [2.58083439e-06, 3.16952222e-06],\n      [3.76373643e-06, 5.14174911e-06],\n      [5.32416098e-06, 6.51707770e-06],\n      [8.62890928e-06, 1.11998258e-05],\n      [1.25762497e-05, 1.65231340e-05],\n      [8.90452991e-06, 1.10148240e-05],\n      [4.86505726e-06, 4.59023120e-06],\n      [3.85545276e-06, 3.39642031e-06],\n      [3.48753893e-06, 3.30566145e-06],\n      [2.99557303e-06, 2.61276368e-06],\n      [2.15496788e-06, 1.87797727e-06],\n      [4.10564937e-06, 3.58142649e-06],\n      [1.53680853e-06, 1.33866906e-06],\n      [4.99540175e-06, 4.35635790e-06],\n      [1.37744970e-06, 1.19380643e-06],\n      [1.74319821e-06, 1.28456429e-06],\n      [9.99931238e-07, 1.14493663e-06],\n      [6.42735560e-07, 1.19380547e-06],\n      [3.66818436e-07, 1.46782199e-06],\n      [5.45413874e-08, 1.83783170e-06],\n      [-1.35818548e-07, 1.14842666e-06],\n      [-5.50758101e-07, 3.02989178e-06],\n      [-4.58785270e-07, 2.66162724e-06],\n      [-2.51315555e-07, 1.19031459e-06],\n      [-3.91409773e-07, 1.65457223e-06],\n      [-2.14525206e-06, 5.67755902e-06],\n      [-4.24558096e-07, 1.39102753e-06],\n      [-1.46936730e-06, 5.32325561e-06],\n      [-1.37632061e-06, 4.59021715e-06],\n      [-8.26642899e-07, 4.68097349e-06],\n      [-6.42702724e-07, 4.95673534e-06],\n      [-3.66796960e-07, 7.25009780e-06],\n      [-1.82861669e-07, 8.99542699e-06],\n      [4.09564134e-07, 6.11214315e-06],\n      [7.80629912e-08, 1.45734993e-06],\n      [4.81205526e-07, 7.56076647e-06],\n      [2.01036346e-07, 2.42775302e-06]])\n\n    v = vectors(points)\n    assert_array_almost_equal(v, expected)\n\n  def test_ref_vectors(self):\n    points = mockNodesData01.radians\n    expected = np.array([\n      [1.59924145e-04, -1.07153714e-04],\n      [1.46520873e-04, -9.70788297e-05],\n      [1.40683931e-04, -9.26694631e-05],\n      [1.32849368e-04, -8.67297434e-05],\n      [1.25762852e-04, -8.14268689e-05],\n      [1.19185869e-04, -7.73700167e-05],\n      [1.18024984e-04, -7.66790438e-05],\n      [1.02705711e-04, -6.70592230e-05],\n      [9.69420991e-05, -6.35082196e-05],\n      [8.08284530e-05, -5.36489556e-05],\n      [6.60268961e-05, -4.50685727e-05],\n      [6.43043874e-05, -4.34630144e-05],\n      [5.56137708e-05, -3.42431117e-05],\n      [5.41844341e-05, -3.27282671e-05],\n      [5.07866397e-05, -3.01576270e-05],\n      [4.80318817e-05, -2.88714948e-05],\n      [3.22813286e-05, -2.31493755e-05],\n      [2.97598330e-05, -2.18038275e-05],\n      [2.81069973e-05, -2.05175815e-05],\n      [5.88679032e-06, -4.08230278e-06],\n      [0.00000000e+00, 0.00000000e+00],\n      [-1.83673390e-06, 1.46782408e-06],\n      [-3.38677236e-06, 2.98626574e-06],\n      [-4.59127869e-06, 5.04925111e-06],\n      [-6.50926460e-06, 9.69009532e-06],\n      [-8.89575243e-06, 1.52908806e-05],\n      [-1.05483839e-05, 2.10749224e-05],\n      [-1.09152548e-05, 2.38290571e-05],\n      [-1.09152276e-05, 2.57576459e-05],\n      [-1.08242659e-05, 2.84192717e-05],\n      [-1.05097542e-05, 2.99499212e-05],\n      [-1.04231024e-05, 3.04333762e-05],\n      [-1.01813369e-05, 3.15416571e-05],\n      [-2.74371711e-06, 4.43034426e-05],\n      [2.85599752e-06, 5.39428964e-05],\n      [4.87550206e-06, 5.66970360e-05],\n      [5.33545066e-06, 5.73393202e-05],\n      [7.07897615e-06, 5.90846634e-05],\n      [9.65040026e-06, 6.11965396e-05],\n      [2.43395796e-05, 7.23966392e-05],\n      [6.28046063e-05, 1.00950641e-04],\n      [8.99657904e-05, 1.20825635e-04],\n      [9.84114021e-05, 1.26977201e-04],\n      [1.00705361e-04, 1.28906084e-04],\n      [1.03285783e-04, 1.32075942e-04],\n      [1.07048835e-04, 1.37218192e-04],\n      [1.12372096e-04, 1.43736004e-04],\n      [1.20999382e-04, 1.54937080e-04],\n      [1.33573053e-04, 1.71462176e-04],\n      [1.42475686e-04, 1.82478533e-04],\n      [1.47339899e-04, 1.87069658e-04],\n      [1.51194707e-04, 1.90466811e-04],\n      [1.54681601e-04, 1.93773152e-04],\n      [1.57676653e-04, 1.96386513e-04],\n      [1.59831239e-04, 1.98264929e-04],\n      [1.63936150e-04, 2.01847201e-04],\n      [1.65472675e-04, 2.03186195e-04],\n      [1.70467147e-04, 2.07543619e-04],\n      [1.71844334e-04, 2.08737728e-04],\n      [1.73587247e-04, 2.10022678e-04],\n      [1.74586922e-04, 2.11167839e-04],\n      [1.75229389e-04, 2.12361789e-04],\n      [1.75595876e-04, 2.13829694e-04],\n      [1.75650001e-04, 2.15667538e-04],\n      [1.75513922e-04, 2.16815933e-04],\n      [1.74962478e-04, 2.19845700e-04],\n      [1.74503092e-04, 2.22507224e-04],\n      [1.74251509e-04, 2.23697482e-04],\n      [1.73859727e-04, 2.25351966e-04],\n      [1.71713202e-04, 2.31029044e-04],\n      [1.71288336e-04, 2.32419977e-04],\n      [1.69817793e-04, 2.37742908e-04],\n      [1.68440467e-04, 2.42332824e-04],\n      [1.67612807e-04, 2.47013617e-04],\n      [1.66969033e-04, 2.51970213e-04],\n      [1.66600674e-04, 2.59220232e-04],\n      [1.66415880e-04, 2.68215619e-04],\n      [1.66824132e-04, 2.74327850e-04],\n      [1.66901881e-04, 2.75785216e-04],\n      [1.67381459e-04, 2.83346086e-04],\n      [1.67581971e-04, 2.85773882e-04]])\n\n    v = ref_vectors(points[20], points)\n    assert_array_almost_equal(v, expected)\n\n  def test_bearing_to_points(self):\n    points = mockNodesData01.radians\n    expected = np.array([\n      2.16112265, 2.15595027, 2.15326799, 2.14916735, 2.14538642,\n      2.14657678, 2.14694997, 2.1492257, 2.1507589, 2.15676899,\n      2.16973441, 2.1651606, 2.12270237, 2.11416356, 2.10665211,\n      2.11201708, 2.19291574, 2.2031069, 2.20136186, 2.17712517,\n      0., -0.8965745, -0.84815954, -0.73792895, -0.59150953,\n      -0.5269061, -0.46406215, -0.42954043, -0.4008254, -0.36391371,\n      -0.33748609, -0.32996807, -0.31223189, -0.06185112, 0.05289544,\n      0.08578116, 0.0927833, 0.11924233, 0.15640718, 0.32432622,\n      0.55653415, 0.64003094, 0.6593301, 0.66319086, 0.66367982,\n      0.66251077, 0.66354137, 0.66302176, 0.66181884, 0.66291139,\n      0.66714676, 0.67095594, 0.67367984, 0.6765003, 0.67847961,\n      0.68212344, 0.68345356, 0.68762778, 0.68876073, 0.69070183,\n      0.69085143, 0.68988665, 0.68753177, 0.68348884, 0.68051081,\n      0.67220053, 0.66506824, 0.66177969, 0.65712162, 0.63916951,\n      0.6351146, 0.62025347, 0.60741567, 0.59618923, 0.58521935,\n      0.57122582, 0.55532475, 0.54636839, 0.54422542, 0.53357655,\n      0.53037033])\n\n    v = bearing_to_points(points[20], points)\n    assert_array_almost_equal(v, expected)\n\n  def test_distance_to_points(self):\n    points = mockNodesData01.radians\n    expected = np.array([\n      1226.82569068, 1120.13820773, 1073.61121415, 1011.10016574,\n      954.81557436, 905.58045038, 896.97734399, 781.7102819,\n      738.58271117, 618.26145463, 509.47052142, 494.6403804,\n      416.22483123, 403.42108699, 376.42615499, 357.15106681,\n      253.15957483, 235.11572972, 221.77439728, 45.65465979,\n      0., 14.98414, 28.77606056, 43.49299446,\n      74.39463425, 112.74005248, 150.19482607, 167.03665191,\n      178.28443483, 193.80834084, 202.28154097, 205.01173833,\n      211.22777104, 282.88676739, 344.25957352, 362.66370657,\n      367.00206795, 379.23951996, 394.82505328, 486.76073331,\n      757.70254732, 960.03439155, 1023.81434529, 1042.49401713,\n      1068.53770096, 1109.12696535, 1162.74555108, 1252.847351,\n      1385.17179405, 1475.42502599, 1517.57849916, 1549.79838056,\n      1580.12405964, 1605.05483058, 1622.98937809, 1657.19268821,\n      1669.99157205, 1711.63883132, 1723.09133393, 1736.47655688,\n      1746.16073119, 1754.63481838, 1763.34186103, 1772.62691273,\n      1777.76189094, 1790.62024447, 1802.11488235, 1807.1040605,\n      1813.90756815, 1834.49265566, 1840.00708445, 1861.96087374,\n      1880.81678093, 1902.42091191, 1926.37194131, 1963.78301115,\n      2011.62679077, 2046.18028824, 2054.37811294, 2097.30347724,\n      2111.28586072])\n\n    v = distance_to_points(points[20], points)\n    assert_array_almost_equal(v, expected)\n"
  },
  {
    "path": "selfdrive/modeld/SConscript",
    "content": "Import('env', 'arch', 'cereal', 'messaging', 'common', 'gpucommon', 'visionipc')\nlenv = env.Clone()\n\nlibs = [cereal, messaging, common, visionipc, gpucommon,\n        'OpenCL', 'SNPE', 'symphony-cpu', 'capnp', 'zmq', 'kj', 'yuv']\n\ndef get_dlsym_offset():\n  \"\"\"Returns the offset between dlopen and dlsym in libdl.so\"\"\"\n  import ctypes\n  libdl = ctypes.PyDLL('libdl.so')\n  dlopen = ctypes.cast(libdl.dlopen, ctypes.c_void_p).value\n  dlsym = ctypes.cast(libdl.dlsym, ctypes.c_void_p).value\n  return dlsym - dlopen\n\n\ncommon_src = [\n  \"models/commonmodel.cc\",\n  \"runners/snpemodel.cc\",\n  \"transforms/loadyuv.cc\",\n  \"transforms/transform.cc\"\n]\n\nthneed_src = [\n  \"thneed/thneed.cc\",\n  \"thneed/serialize.cc\",\n  \"runners/thneedmodel.cc\",\n]\n\nuse_thneed = not GetOption('no_thneed')\n\nif arch == \"aarch64\" or arch == \"larch64\":\n  libs += ['gsl', 'CB']\n  libs += ['gnustl_shared'] if arch == \"aarch64\" else ['pthread', 'dl']\n\n  if use_thneed:\n    common_src += thneed_src\n    dlsym_offset = get_dlsym_offset()\n    lenv['CXXFLAGS'].append(\"-DUSE_THNEED\")\n    lenv['CXXFLAGS'].append(f\"-DDLSYM_OFFSET={dlsym_offset}\")\nelse:\n  libs += ['pthread']\n\n  if not GetOption('snpe'):\n    # for onnx support\n    common_src += ['runners/onnxmodel.cc']\n\n    # tell runners to use onnx\n    lenv['CFLAGS'].append(\"-DUSE_ONNX_MODEL\")\n    lenv['CXXFLAGS'].append(\"-DUSE_ONNX_MODEL\")\n\n  if arch == \"Darwin\":\n    # fix OpenCL\n    del libs[libs.index('OpenCL')]\n    lenv['FRAMEWORKS'] = ['OpenCL']\n\n    # no SNPE on Mac\n    del libs[libs.index('SNPE')]\n    del libs[libs.index('symphony-cpu')]\n    del common_src[common_src.index('runners/snpemodel.cc')]\n\n  elif arch == \"jarch64\":\n    # no SNPE on arm64 linux\n    del libs[libs.index('SNPE')]\n    del libs[libs.index('symphony-cpu')]\n    del common_src[common_src.index('runners/snpemodel.cc')]\n\ncommon_model = lenv.Object(common_src)\n\n# build thneed model\nif use_thneed and arch in (\"aarch64\", \"larch64\"):\n  compiler = lenv.Program('thneed/compile', [\"thneed/compile.cc\"]+common_model, LIBS=libs)\n  cmd = f\"cd {Dir('.').abspath} && {compiler[0].abspath} ../../models/supercombo.dlc ../../models/supercombo.thneed --binary\"\n\n  lib_paths = ':'.join([Dir(p).abspath for p in lenv[\"LIBPATH\"]])\n  cenv = Environment(ENV={'LD_LIBRARY_PATH': f\"{lib_paths}:{lenv['ENV']['LD_LIBRARY_PATH']}\"})\n  cenv.Command(\"../../models/supercombo.thneed\", [\"../../models/supercombo.dlc\", compiler], cmd)\n\nif arch != \"jarch64\":\n  lenv.Program('_dmonitoringmodeld', [\n      \"dmonitoringmodeld.cc\",\n      \"models/dmonitoring.cc\",\n    ]+common_model, LIBS=libs)\n\nlenv.Program('_modeld', [\n    \"modeld.cc\",\n    \"models/driving.cc\",\n  ]+common_model, LIBS=libs)\n"
  },
  {
    "path": "selfdrive/modeld/constants.py",
    "content": "IDX_N = 33\n\ndef index_function(idx, max_val=192):\n  return (max_val/1024)*(idx**2)\n\n\nT_IDXS = [index_function(idx, max_val=10.0) for idx in range(IDX_N)]\n"
  },
  {
    "path": "selfdrive/modeld/dmonitoringmodeld",
    "content": "#!/bin/sh\n\nDIR=\"$(cd \"$(dirname \"${BASH_SOURCE[0]}\")\" >/dev/null && pwd)\"\ncd $DIR\n\nif [ -d /system ]; then\n  if [ -f /TICI ]; then # QCOM2\n    export LD_LIBRARY_PATH=\"/usr/lib/aarch64-linux-gnu:/data/pythonpath/phonelibs/snpe/larch64:$LD_LIBRARY_PATH\"\n  else # QCOM\n    export LD_LIBRARY_PATH=\"/data/pythonpath/phonelibs/snpe/aarch64/:$LD_LIBRARY_PATH\"\n  fi\n  export ADSP_LIBRARY_PATH=\"/data/pythonpath/phonelibs/snpe/dsp/\"\nelse\n  # PC\n  export LD_LIBRARY_PATH=\"$DIR/../../phonelibs/snpe/x86_64-linux-clang:$DIR/../../openpilot/phonelibs/snpe/x86_64:$LD_LIBRARY_PATH\"\nfi\nexec ./_dmonitoringmodeld\n"
  },
  {
    "path": "selfdrive/modeld/dmonitoringmodeld.cc",
    "content": "#include <sys/resource.h>\n#include <limits.h>\n\n#include <cstdio>\n#include <cstdlib>\n\n#include \"cereal/visionipc/visionipc_client.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/modeld/models/dmonitoring.h\"\n\nExitHandler do_exit;\n\nvoid run_model(DMonitoringModelState &model, VisionIpcClient &vipc_client) {\n  PubMaster pm({\"driverState\"});\n  double last = 0;\n\n  while (!do_exit) {\n    VisionIpcBufExtra extra = {};\n    VisionBuf *buf = vipc_client.recv(&extra);\n    if (buf == nullptr) continue;\n\n    double t1 = millis_since_boot();\n    DMonitoringResult res = dmonitoring_eval_frame(&model, buf->addr, buf->width, buf->height);\n    double t2 = millis_since_boot();\n\n    // send dm packet\n    dmonitoring_publish(pm, extra.frame_id, res, (t2 - t1) / 1000.0, model.output);\n\n    //printf(\"dmonitoring process: %.2fms, from last %.2fms\\n\", t2 - t1, t1 - last);\n    last = t1;\n  }\n}\n\nint main(int argc, char **argv) {\n  setpriority(PRIO_PROCESS, 0, -15);\n\n  // init the models\n  DMonitoringModelState model;\n  dmonitoring_init(&model);\n\n  VisionIpcClient vipc_client = VisionIpcClient(\"camerad\", VISION_STREAM_YUV_FRONT, true);\n  while (!do_exit && !vipc_client.connect(false)) {\n    util::sleep_for(100);\n  }\n\n  // run the models\n  if (vipc_client.connected) {\n    LOGW(\"connected with buffer size: %d\", vipc_client.buffers[0].len);\n    run_model(model, vipc_client);\n  }\n\n  dmonitoring_free(&model);\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/modeld/modeld",
    "content": "#!/bin/sh\n\nDIR=\"$(cd \"$(dirname \"${BASH_SOURCE[0]}\")\" >/dev/null && pwd)\"\ncd $DIR\n\nif [ -d /system ]; then\n  if [ -f /TICI ]; then # QCOM2\n    export LD_LIBRARY_PATH=\"/usr/lib/aarch64-linux-gnu:/data/pythonpath/phonelibs/snpe/larch64:$LD_LIBRARY_PATH\"\n  else # QCOM\n    export LD_LIBRARY_PATH=\"/data/pythonpath/phonelibs/snpe/aarch64/:$LD_LIBRARY_PATH\"\n  fi\nelse\n  if [ -f /JETSON ]; then # Jetson\n    sleep 3\n    export LD_LIBRARY_PATH=\"/usr/lib/aarch64-linux-gnu:$LD_LIBRARY_PATH\"\n  else\n    # PC\n    export LD_LIBRARY_PATH=\"$DIR/../../phonelibs/snpe/x86_64-linux-clang:$DIR/../../openpilot/phonelibs/snpe/x86_64:$LD_LIBRARY_PATH\"\n  fi\nfi\nexec ./_modeld\n"
  },
  {
    "path": "selfdrive/modeld/modeld.cc",
    "content": "#include <cstdio>\n#include <cstdlib>\n#include <mutex>\n\n#include <eigen3/Eigen/Dense>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"cereal/visionipc/visionipc_client.h\"\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/modeld/models/driving.h\"\n\nExitHandler do_exit;\n// globals\nbool live_calib_seen;\nmat3 cur_transform;\nstd::mutex transform_lock;\n\nvoid calibration_thread(bool wide_camera) {\n  set_thread_name(\"calibration\");\n  set_realtime_priority(50);\n\n  SubMaster sm({\"liveCalibration\"});\n\n  /*\n     import numpy as np\n     from common.transformations.model import medmodel_frame_from_road_frame\n     medmodel_frame_from_ground = medmodel_frame_from_road_frame[:, (0, 1, 3)]\n     ground_from_medmodel_frame = np.linalg.inv(medmodel_frame_from_ground)\n  */\n  Eigen::Matrix<float, 3, 3> ground_from_medmodel_frame;\n  ground_from_medmodel_frame <<\n    0.00000000e+00, 0.00000000e+00, 1.00000000e+00,\n    -1.09890110e-03, 0.00000000e+00, 2.81318681e-01,\n    -1.84808520e-20, 9.00738606e-04,-4.28751576e-02;\n\n  Eigen::Matrix<float, 3, 3> cam_intrinsics = Eigen::Matrix<float, 3, 3, Eigen::RowMajor>(wide_camera ? ecam_intrinsic_matrix.v : fcam_intrinsic_matrix.v);\n  const mat3 yuv_transform = get_model_yuv_transform();\n\n  while (!do_exit) {\n    sm.update(100);\n    if(sm.updated(\"liveCalibration\")) {\n      auto extrinsic_matrix = sm[\"liveCalibration\"].getLiveCalibration().getExtrinsicMatrix();\n      Eigen::Matrix<float, 3, 4> extrinsic_matrix_eigen;\n      for (int i = 0; i < 4*3; i++) {\n        extrinsic_matrix_eigen(i / 4, i % 4) = extrinsic_matrix[i];\n      }\n\n      auto camera_frame_from_road_frame = cam_intrinsics * extrinsic_matrix_eigen;\n      Eigen::Matrix<float, 3, 3> camera_frame_from_ground;\n      camera_frame_from_ground.col(0) = camera_frame_from_road_frame.col(0);\n      camera_frame_from_ground.col(1) = camera_frame_from_road_frame.col(1);\n      camera_frame_from_ground.col(2) = camera_frame_from_road_frame.col(3);\n\n      auto warp_matrix = camera_frame_from_ground * ground_from_medmodel_frame;\n      mat3 transform = {};\n      for (int i=0; i<3*3; i++) {\n        transform.v[i] = warp_matrix(i / 3, i % 3);\n      }\n      mat3 model_transform = matmul3(yuv_transform, transform);\n      std::lock_guard lk(transform_lock);\n      cur_transform = model_transform;\n      live_calib_seen = true;\n    }\n  }\n}\n\nvoid run_model(ModelState &model, VisionIpcClient &vipc_client) {\n  // messaging\n  PubMaster pm({\"modelV2\", \"cameraOdometry\"});\n  SubMaster sm({\"lateralPlan\", \"roadCameraState\"});\n\n  // setup filter to track dropped frames\n  FirstOrderFilter frame_dropped_filter(0., 10., 1. / MODEL_FREQ);\n\n  uint32_t frame_id = 0, last_vipc_frame_id = 0;\n  double last = 0;\n  uint32_t run_count = 0;\n\n  while (!do_exit) {\n    VisionIpcBufExtra extra = {};\n    VisionBuf *buf = vipc_client.recv(&extra);\n    if (buf == nullptr) continue;\n\n    transform_lock.lock();\n    mat3 model_transform = cur_transform;\n    const bool run_model_this_iter = live_calib_seen;\n    transform_lock.unlock();\n\n    // TODO: path planner timeout?\n    sm.update(0);\n    int desire = ((int)sm[\"lateralPlan\"].getLateralPlan().getDesire());\n    frame_id = sm[\"roadCameraState\"].getRoadCameraState().getFrameId();\n\n    if (run_model_this_iter) {\n      run_count++;\n\n      float vec_desire[DESIRE_LEN] = {0};\n      if (desire >= 0 && desire < DESIRE_LEN) {\n        vec_desire[desire] = 1.0;\n      }\n\n      double mt1 = millis_since_boot();\n      ModelDataRaw model_buf = model_eval_frame(&model, buf->buf_cl, buf->width, buf->height,\n                                                model_transform, vec_desire);\n      double mt2 = millis_since_boot();\n      float model_execution_time = (mt2 - mt1) / 1000.0;\n\n      // tracked dropped frames\n      uint32_t vipc_dropped_frames = extra.frame_id - last_vipc_frame_id - 1;\n      float frames_dropped = frame_dropped_filter.update((float)std::min(vipc_dropped_frames, 10U));\n      if (run_count < 10) { // let frame drops warm up\n        frame_dropped_filter.reset(0);\n        frames_dropped = 0.;\n      }\n\n      float frame_drop_ratio = frames_dropped / (1 + frames_dropped);\n\n      model_publish(pm, extra.frame_id, frame_id, frame_drop_ratio, model_buf, extra.timestamp_eof, model_execution_time,\n                    kj::ArrayPtr<const float>(model.output.data(), model.output.size()));\n      posenet_publish(pm, extra.frame_id, vipc_dropped_frames, model_buf, extra.timestamp_eof);\n\n      //printf(\"model process: %.2fms, from last %.2fms, vipc_frame_id %u, frame_id, %u, frame_drop %.3f\\n\", mt2 - mt1, mt1 - last, extra.frame_id, frame_id, frame_drop_ratio);\n      last = mt1;\n      last_vipc_frame_id = extra.frame_id;\n    }\n  }\n}\n\nint main(int argc, char **argv) {\n  set_realtime_priority(54);\n\n  if (Hardware::EON()) {\n    set_core_affinity(2);\n  } else if (Hardware::TICI()) {\n    set_core_affinity(7);  \n  } else if (Hardware::JETSON()) {\n    set_core_affinity(1);\n  }\n  bool wide_camera = Hardware::TICI() ? Params().getBool(\"EnableWideCamera\") : false;\n\n  // start calibration thread\n  std::thread thread = std::thread(calibration_thread, wide_camera);\n\n  // cl init\n  #ifdef XNX\n  cl_device_id device_id = cl_get_device_id(CL_DEVICE_TYPE_GPU);\n  #else\n  cl_device_id device_id = cl_get_device_id(CL_DEVICE_TYPE_DEFAULT);\n  #endif\n  cl_context context = CL_CHECK_ERR(clCreateContext(NULL, 1, &device_id, NULL, NULL, &err));\n\n  // init the models\n  ModelState model;\n  model_init(&model, device_id, context);\n  LOGW(\"models loaded, modeld starting\");\n\n  VisionIpcClient vipc_client = VisionIpcClient(\"camerad\", wide_camera ? VISION_STREAM_YUV_WIDE : VISION_STREAM_YUV_BACK, true, device_id, context);\n  while (!do_exit && !vipc_client.connect(false)) {\n    util::sleep_for(100);\n  }\n\n  // run the models\n  // vipc_client.connected is false only when do_exit is true\n  if (vipc_client.connected) {\n    const VisionBuf *b = &vipc_client.buffers[0];\n    LOGW(\"connected with buffer size: %d (%d x %d)\", b->len, b->width, b->height);\n    run_model(model, vipc_client);\n  }\n\n  model_free(&model);\n  LOG(\"joining calibration thread\");\n  thread.join();\n  CL_CHECK(clReleaseContext(context));\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/modeld/models/commonmodel.cc",
    "content": "#include \"selfdrive/modeld/models/commonmodel.h\"\n\n#include <algorithm>\n#include <cassert>\n#include <cmath>\n#include <cstring>\n\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/timing.h\"\n\nModelFrame::ModelFrame(cl_device_id device_id, cl_context context) {\n  input_frames = std::make_unique<float[]>(buf_size);\n\n  q = CL_CHECK_ERR(clCreateCommandQueue(context, device_id, 0, &err));\n  y_cl = CL_CHECK_ERR(clCreateBuffer(context, CL_MEM_READ_WRITE, MODEL_WIDTH * MODEL_HEIGHT, NULL, &err));\n  u_cl = CL_CHECK_ERR(clCreateBuffer(context, CL_MEM_READ_WRITE, (MODEL_WIDTH / 2) * (MODEL_HEIGHT / 2), NULL, &err));\n  v_cl = CL_CHECK_ERR(clCreateBuffer(context, CL_MEM_READ_WRITE, (MODEL_WIDTH / 2) * (MODEL_HEIGHT / 2), NULL, &err));\n  net_input_cl = CL_CHECK_ERR(clCreateBuffer(context, CL_MEM_READ_WRITE, MODEL_FRAME_SIZE * sizeof(float), NULL, &err));\n\n  transform_init(&transform, context, device_id);\n  loadyuv_init(&loadyuv, context, device_id, MODEL_WIDTH, MODEL_HEIGHT);\n}\n\nfloat* ModelFrame::prepare(cl_mem yuv_cl, int frame_width, int frame_height, const mat3 &transform) {\n  transform_queue(&this->transform, q,\n                  yuv_cl, frame_width, frame_height,\n                  y_cl, u_cl, v_cl, MODEL_WIDTH, MODEL_HEIGHT, transform);\n  loadyuv_queue(&loadyuv, q, y_cl, u_cl, v_cl, net_input_cl);\n\n  std::memmove(&input_frames[0], &input_frames[MODEL_FRAME_SIZE], sizeof(float) * MODEL_FRAME_SIZE);\n  clEnqueueReadBuffer(q, net_input_cl, CL_TRUE, 0, MODEL_FRAME_SIZE * sizeof(float), &input_frames[MODEL_FRAME_SIZE], 0, nullptr, nullptr);\n  clFinish(q);\n  return &input_frames[0];\n}\n\nModelFrame::~ModelFrame() {\n  transform_destroy(&transform);\n  loadyuv_destroy(&loadyuv);\n  CL_CHECK(clReleaseMemObject(net_input_cl));\n  CL_CHECK(clReleaseMemObject(v_cl));\n  CL_CHECK(clReleaseMemObject(u_cl));\n  CL_CHECK(clReleaseMemObject(y_cl));\n  CL_CHECK(clReleaseCommandQueue(q));\n}\n\nvoid softmax(const float* input, float* output, size_t len) {\n  const float max_val = *std::max_element(input, input + len);\n  float denominator = 0;\n  for(int i = 0; i < len; i++) {\n    float const v_exp = expf(input[i] - max_val);\n    denominator += v_exp;\n    output[i] = v_exp;\n  }\n\n  const float inv_denominator = 1. / denominator;\n  for(int i = 0; i < len; i++) {\n    output[i] *= inv_denominator;\n  }\n}\n\nfloat sigmoid(float input) {\n  return 1 / (1 + expf(-input));\n}\n\nfloat softplus(float input) {\n  return log1p(expf(input));\n}\n"
  },
  {
    "path": "selfdrive/modeld/models/commonmodel.h",
    "content": "#pragma once\n\n#include <cfloat>\n#include <cstdlib>\n\n#include <memory>\n\n#define CL_USE_DEPRECATED_OPENCL_1_2_APIS\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\n\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/modeld/transforms/loadyuv.h\"\n#include \"selfdrive/modeld/transforms/transform.h\"\n\nconstexpr int MODEL_WIDTH = 512;\nconstexpr int MODEL_HEIGHT = 256;\nconstexpr int MODEL_FRAME_SIZE = MODEL_WIDTH * MODEL_HEIGHT * 3 / 2;\n\nconst bool send_raw_pred = getenv(\"SEND_RAW_PRED\") != NULL;\n\nvoid softmax(const float* input, float* output, size_t len);\nfloat softplus(float input);\nfloat sigmoid(float input);\n\nclass ModelFrame {\n public:\n  ModelFrame(cl_device_id device_id, cl_context context);\n  ~ModelFrame();\n  float* prepare(cl_mem yuv_cl, int width, int height, const mat3& transform);\n\n  const int buf_size = MODEL_FRAME_SIZE * 2;\n\n private:\n  Transform transform;\n  LoadYUVState loadyuv;\n  cl_command_queue q;\n  cl_mem y_cl, u_cl, v_cl, net_input_cl;\n  std::unique_ptr<float[]> input_frames;\n};\n"
  },
  {
    "path": "selfdrive/modeld/models/dmonitoring.cc",
    "content": "#include <cstring>\n\n#include \"libyuv.h\"\n\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/hardware/hw.h\"\n\n#include \"selfdrive/modeld/models/dmonitoring.h\"\n\n#define MODEL_WIDTH 320\n#define MODEL_HEIGHT 640\n#define FULL_W 852 // should get these numbers from camerad\n\nvoid dmonitoring_init(DMonitoringModelState* s) {\n  s->is_rhd = Params().getBool(\"IsRHD\");\n  for (int x = 0; x < std::size(s->tensor); ++x) {\n    s->tensor[x] = (x - 128.f) * 0.0078125f;\n  }\n\n#ifdef USE_ONNX_MODEL\n  s->m = new ONNXModel(\"../../models/dmonitoring_model.onnx\", &s->output[0], OUTPUT_SIZE, USE_DSP_RUNTIME);\n#else\n  s->m = new SNPEModel(\"../../models/dmonitoring_model_q.dlc\", &s->output[0], OUTPUT_SIZE, USE_DSP_RUNTIME);\n#endif\n}\n\ntemplate <class T>\nstatic inline T *get_buffer(std::vector<T> &buf, const size_t size) {\n  if (buf.size() < size) buf.resize(size);\n  return buf.data();\n}\n\nstatic inline auto get_yuv_buf(std::vector<uint8_t> &buf, const int width, int height) {\n  uint8_t *y = get_buffer(buf, width * height * 3 / 2);\n  uint8_t *u = y + width * height;\n  uint8_t *v = u + (width /2) * (height / 2);\n  return std::make_tuple(y, u, v);\n}\n\nstruct Rect {int x, y, w, h;};\nvoid crop_yuv(uint8_t *raw, int width, int height, uint8_t *y, uint8_t *u, uint8_t *v, const Rect &rect) {\n  uint8_t *raw_y = raw;\n  uint8_t *raw_u = raw_y + (width * height);\n  uint8_t *raw_v = raw_u + ((width / 2) * (height / 2));\n  for (int r = 0; r < rect.h / 2; r++) {\n    memcpy(y + 2 * r * rect.w, raw_y + (2 * r + rect.y) * width + rect.x, rect.w);\n    memcpy(y + (2 * r + 1) * rect.w, raw_y + (2 * r + rect.y + 1) * width + rect.x, rect.w);\n    memcpy(u + r * (rect.w / 2), raw_u + (r + (rect.y / 2)) * width / 2 + (rect.x / 2), rect.w / 2);\n    memcpy(v + r * (rect.w / 2), raw_v + (r + (rect.y / 2)) * width / 2 + (rect.x / 2), rect.w / 2);\n  }\n}\n\nDMonitoringResult dmonitoring_eval_frame(DMonitoringModelState* s, void* stream_buf, int width, int height) {\n  Rect crop_rect;\n  if (Hardware::TICI()) {\n    const int full_width_tici = 1928;\n    const int full_height_tici = 1208;\n    const int adapt_width_tici = 668;\n    const int cropped_height = adapt_width_tici / 1.33;\n    crop_rect = {full_width_tici / 2 - adapt_width_tici / 2,\n                 full_height_tici / 2 - cropped_height / 2 - 196,\n                 cropped_height / 2,\n                 cropped_height};\n    if (!s->is_rhd) {\n      crop_rect.x += adapt_width_tici - crop_rect.w + 32;\n    }\n\n  } else {\n    crop_rect = {0, 0, height / 2, height};\n    if (!s->is_rhd) {\n      crop_rect.x += width - crop_rect.w;\n    }\n  }\n\n  int resized_width = MODEL_WIDTH;\n  int resized_height = MODEL_HEIGHT;\n\n  auto [cropped_y, cropped_u, cropped_v] = get_yuv_buf(s->cropped_buf, crop_rect.w, crop_rect.h);\n  if (!s->is_rhd) {\n    crop_yuv((uint8_t *)stream_buf, width, height, cropped_y, cropped_u, cropped_v, crop_rect);\n  } else {\n    auto [mirror_y, mirror_u, mirror_v] = get_yuv_buf(s->premirror_cropped_buf, crop_rect.w, crop_rect.h);\n    crop_yuv((uint8_t *)stream_buf, width, height, mirror_y, mirror_u, mirror_v, crop_rect);\n    libyuv::I420Mirror(mirror_y, crop_rect.w,\n                       mirror_u, crop_rect.w / 2,\n                       mirror_v, crop_rect.w / 2,\n                       cropped_y, crop_rect.w,\n                       cropped_u, crop_rect.w / 2,\n                       cropped_v, crop_rect.w / 2,\n                       crop_rect.w, crop_rect.h);\n  }\n\n  auto [resized_buf, resized_u, resized_v] = get_yuv_buf(s->resized_buf, resized_width, resized_height);\n  uint8_t *resized_y = resized_buf;\n  libyuv::FilterMode mode = libyuv::FilterModeEnum::kFilterBilinear;\n  libyuv::I420Scale(cropped_y, crop_rect.w,\n                    cropped_u, crop_rect.w / 2,\n                    cropped_v, crop_rect.w / 2,\n                    crop_rect.w, crop_rect.h,\n                    resized_y, resized_width,\n                    resized_u, resized_width / 2,\n                    resized_v, resized_width / 2,\n                    resized_width, resized_height,\n                    mode);\n\n  int yuv_buf_len = (MODEL_WIDTH/2) * (MODEL_HEIGHT/2) * 6; // Y|u|v -> y|y|y|y|u|v\n  float *net_input_buf = get_buffer(s->net_input_buf, yuv_buf_len);\n  // one shot conversion, O(n) anyway\n  // yuvframe2tensor, normalize\n  for (int r = 0; r < MODEL_HEIGHT/2; r++) {\n    for (int c = 0; c < MODEL_WIDTH/2; c++) {\n      // Y_ul\n      net_input_buf[(r*MODEL_WIDTH/2) + c + (0*(MODEL_WIDTH/2)*(MODEL_HEIGHT/2))] = s->tensor[resized_y[(2*r)*resized_width + 2*c]];\n      // Y_dl\n      net_input_buf[(r*MODEL_WIDTH/2) + c + (1*(MODEL_WIDTH/2)*(MODEL_HEIGHT/2))] = s->tensor[resized_y[(2*r+1)*resized_width + 2*c]];\n      // Y_ur\n      net_input_buf[(r*MODEL_WIDTH/2) + c + (2*(MODEL_WIDTH/2)*(MODEL_HEIGHT/2))] = s->tensor[resized_y[(2*r)*resized_width + 2*c+1]];\n      // Y_dr\n      net_input_buf[(r*MODEL_WIDTH/2) + c + (3*(MODEL_WIDTH/2)*(MODEL_HEIGHT/2))] = s->tensor[resized_y[(2*r+1)*resized_width + 2*c+1]];\n      // U\n      net_input_buf[(r*MODEL_WIDTH/2) + c + (4*(MODEL_WIDTH/2)*(MODEL_HEIGHT/2))] = s->tensor[resized_u[r*resized_width/2 + c]];\n      // V\n      net_input_buf[(r*MODEL_WIDTH/2) + c + (5*(MODEL_WIDTH/2)*(MODEL_HEIGHT/2))] = s->tensor[resized_v[r*resized_width/2 + c]];\n    }\n  }\n\n  //printf(\"preprocess completed. %d \\n\", yuv_buf_len);\n  //FILE *dump_yuv_file = fopen(\"/tmp/rawdump.yuv\", \"wb\");\n  //fwrite(raw_buf, height*width*3/2, sizeof(uint8_t), dump_yuv_file);\n  //fclose(dump_yuv_file);\n\n  // *** testing ***\n  // idat = np.frombuffer(open(\"/tmp/inputdump.yuv\", \"rb\").read(), np.float32).reshape(6, 160, 320)\n  // imshow(cv2.cvtColor(tensor_to_frames(idat[None]/0.0078125+128)[0], cv2.COLOR_YUV2RGB_I420))\n\n  //FILE *dump_yuv_file2 = fopen(\"/tmp/inputdump.yuv\", \"wb\");\n  //fwrite(net_input_buf, MODEL_HEIGHT*MODEL_WIDTH*3/2, sizeof(float), dump_yuv_file2);\n  //fclose(dump_yuv_file2);\n\n  double t1 = millis_since_boot();\n  s->m->execute(net_input_buf, yuv_buf_len);\n  double t2 = millis_since_boot();\n\n  DMonitoringResult ret = {0};\n  for (int i = 0; i < 3; ++i) {\n    ret.face_orientation[i] = s->output[i];\n    ret.face_orientation_meta[i] = softplus(s->output[6 + i]);\n  }\n  for (int i = 0; i < 2; ++i) {\n    ret.face_position[i] = s->output[3 + i];\n    ret.face_position_meta[i] = softplus(s->output[9 + i]);\n  }\n  ret.face_prob = s->output[12];\n  ret.left_eye_prob = s->output[21];\n  ret.right_eye_prob = s->output[30];\n  ret.left_blink_prob = s->output[31];\n  ret.right_blink_prob = s->output[32];\n  ret.sg_prob = s->output[33];\n  ret.poor_vision = s->output[34];\n  ret.partial_face = s->output[35];\n  ret.distracted_pose = s->output[36];\n  ret.distracted_eyes = s->output[37];\n  ret.dsp_execution_time = (t2 - t1) / 1000.;\n  return ret;\n}\n\nvoid dmonitoring_publish(PubMaster &pm, uint32_t frame_id, const DMonitoringResult &res, float execution_time, kj::ArrayPtr<const float> raw_pred) {\n  // make msg\n  MessageBuilder msg;\n  auto framed = msg.initEvent().initDriverState();\n  framed.setFrameId(frame_id);\n  framed.setModelExecutionTime(execution_time);\n  framed.setDspExecutionTime(res.dsp_execution_time);\n\n  framed.setFaceOrientation(res.face_orientation);\n  framed.setFaceOrientationStd(res.face_orientation_meta);\n  framed.setFacePosition(res.face_position);\n  framed.setFacePositionStd(res.face_position_meta);\n  framed.setFaceProb(res.face_prob);\n  framed.setLeftEyeProb(res.left_eye_prob);\n  framed.setRightEyeProb(res.right_eye_prob);\n  framed.setLeftBlinkProb(res.left_blink_prob);\n  framed.setRightBlinkProb(res.right_blink_prob);\n  framed.setSunglassesProb(res.sg_prob);\n  framed.setPoorVision(res.poor_vision);\n  framed.setPartialFace(res.partial_face);\n  framed.setDistractedPose(res.distracted_pose);\n  framed.setDistractedEyes(res.distracted_eyes);\n  if (send_raw_pred) {\n    framed.setRawPredictions(raw_pred.asBytes());\n  }\n\n  pm.send(\"driverState\", msg);\n}\n\nvoid dmonitoring_free(DMonitoringModelState* s) {\n  delete s->m;\n}\n"
  },
  {
    "path": "selfdrive/modeld/models/dmonitoring.h",
    "content": "#pragma once\n\n#include <vector>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/modeld/models/commonmodel.h\"\n#include \"selfdrive/modeld/runners/run.h\"\n\n#define OUTPUT_SIZE 38\n\ntypedef struct DMonitoringResult {\n  float face_orientation[3];\n  float face_orientation_meta[3];\n  float face_position[2];\n  float face_position_meta[2];\n  float face_prob;\n  float left_eye_prob;\n  float right_eye_prob;\n  float left_blink_prob;\n  float right_blink_prob;\n  float sg_prob;\n  float poor_vision;\n  float partial_face;\n  float distracted_pose;\n  float distracted_eyes;\n  float dsp_execution_time;\n} DMonitoringResult;\n\ntypedef struct DMonitoringModelState {\n  RunModel *m;\n  bool is_rhd;\n  float output[OUTPUT_SIZE];\n  std::vector<uint8_t> resized_buf;\n  std::vector<uint8_t> cropped_buf;\n  std::vector<uint8_t> premirror_cropped_buf;\n  std::vector<float> net_input_buf;\n  float tensor[UINT8_MAX + 1];\n} DMonitoringModelState;\n\nvoid dmonitoring_init(DMonitoringModelState* s);\nDMonitoringResult dmonitoring_eval_frame(DMonitoringModelState* s, void* stream_buf, int width, int height);\nvoid dmonitoring_publish(PubMaster &pm, uint32_t frame_id, const DMonitoringResult &res, float execution_time, kj::ArrayPtr<const float> raw_pred);\nvoid dmonitoring_free(DMonitoringModelState* s);\n\n"
  },
  {
    "path": "selfdrive/modeld/models/driving.cc",
    "content": "#include \"selfdrive/modeld/models/driving.h\"\n\n#include <fcntl.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <cstring>\n\n#include <eigen3/Eigen/Dense>\n\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/timing.h\"\n\nconstexpr int DESIRE_PRED_SIZE = 32;\nconstexpr int OTHER_META_SIZE = 48;\nconstexpr int NUM_META_INTERVALS = 5;\nconstexpr int META_STRIDE = 7;\n\nconstexpr int PLAN_MHP_N = 5;\nconstexpr int PLAN_MHP_COLUMNS = 15;\nconstexpr int PLAN_MHP_VALS = 15*33;\nconstexpr int PLAN_MHP_SELECTION = 1;\nconstexpr int PLAN_MHP_GROUP_SIZE =  (2*PLAN_MHP_VALS + PLAN_MHP_SELECTION);\n\nconstexpr int LEAD_MHP_N = 2;\nconstexpr int LEAD_TRAJ_LEN = 6;\nconstexpr int LEAD_PRED_DIM = 4;\nconstexpr int LEAD_MHP_VALS = LEAD_PRED_DIM*LEAD_TRAJ_LEN;\nconstexpr int LEAD_MHP_SELECTION = 3;\nconstexpr int LEAD_MHP_GROUP_SIZE = (2*LEAD_MHP_VALS + LEAD_MHP_SELECTION);\n\nconstexpr int POSE_SIZE = 12;\n\nconstexpr int PLAN_IDX = 0;\nconstexpr int LL_IDX = PLAN_IDX + PLAN_MHP_N*PLAN_MHP_GROUP_SIZE;\nconstexpr int LL_PROB_IDX = LL_IDX + 4*2*2*33;\nconstexpr int RE_IDX = LL_PROB_IDX + 8;\nconstexpr int LEAD_IDX = RE_IDX + 2*2*2*33;\nconstexpr int LEAD_PROB_IDX = LEAD_IDX + LEAD_MHP_N*(LEAD_MHP_GROUP_SIZE);\nconstexpr int DESIRE_STATE_IDX = LEAD_PROB_IDX + 3;\nconstexpr int META_IDX = DESIRE_STATE_IDX + DESIRE_LEN;\nconstexpr int POSE_IDX = META_IDX + OTHER_META_SIZE + DESIRE_PRED_SIZE;\nconstexpr int OUTPUT_SIZE =  POSE_IDX + POSE_SIZE;\n#ifdef TEMPORAL\n  constexpr int TEMPORAL_SIZE = 512;\n#else\n  constexpr int TEMPORAL_SIZE = 0;\n#endif\n\nconstexpr float FCW_THRESHOLD_5MS2_HIGH = 0.15;\nconstexpr float FCW_THRESHOLD_5MS2_LOW = 0.05;\nconstexpr float FCW_THRESHOLD_3MS2 = 0.7;\n\nfloat prev_brake_5ms2_probs[5] = {0,0,0,0,0};\nfloat prev_brake_3ms2_probs[3] = {0,0,0};\n\n// #define DUMP_YUV\n\nvoid model_init(ModelState* s, cl_device_id device_id, cl_context context) {\n  s->frame = new ModelFrame(device_id, context);\n\n  constexpr int output_size = OUTPUT_SIZE + TEMPORAL_SIZE;\n  s->output.resize(output_size);\n\n#ifdef USE_THNEED\n  s->m = std::make_unique<ThneedModel>(\"../../models/supercombo.thneed\", &s->output[0], output_size, USE_GPU_RUNTIME);\n#elif USE_ONNX_MODEL\n  s->m = std::make_unique<ONNXModel>(\"../../models/supercombo.onnx\", &s->output[0], output_size, USE_GPU_RUNTIME);\n#else\n  s->m = std::make_unique<SNPEModel>(\"../../models/supercombo.dlc\", &s->output[0], output_size, USE_GPU_RUNTIME);\n#endif\n\n#ifdef TEMPORAL\n  s->m->addRecurrent(&s->output[OUTPUT_SIZE], TEMPORAL_SIZE);\n#endif\n\n#ifdef DESIRE\n  s->m->addDesire(s->pulse_desire, DESIRE_LEN);\n#endif\n\n#ifdef TRAFFIC_CONVENTION\n  const int idx = Params().getBool(\"IsRHD\") ? 1 : 0;\n  s->traffic_convention[idx] = 1.0;\n  s->m->addTrafficConvention(s->traffic_convention, TRAFFIC_CONVENTION_LEN);\n#endif\n}\n\nModelDataRaw model_eval_frame(ModelState* s, cl_mem yuv_cl, int width, int height,\n                           const mat3 &transform, float *desire_in) {\n#ifdef DESIRE\n  if (desire_in != NULL) {\n    for (int i = 1; i < DESIRE_LEN; i++) {\n      // Model decides when action is completed\n      // so desire input is just a pulse triggered on rising edge\n      if (desire_in[i] - s->prev_desire[i] > .99) {\n        s->pulse_desire[i] = desire_in[i];\n      } else {\n        s->pulse_desire[i] = 0.0;\n      }\n      s->prev_desire[i] = desire_in[i];\n    }\n  }\n#endif\n\n  //for (int i = 0; i < OUTPUT_SIZE + TEMPORAL_SIZE; i++) { printf(\"%f \", s->output[i]); } printf(\"\\n\");\n\n  auto net_input_buf = s->frame->prepare(yuv_cl, width, height, transform);\n  s->m->execute(net_input_buf, s->frame->buf_size);\n\n  // net outputs\n  ModelDataRaw net_outputs;\n  net_outputs.plan = &s->output[PLAN_IDX];\n  net_outputs.lane_lines = &s->output[LL_IDX];\n  net_outputs.lane_lines_prob = &s->output[LL_PROB_IDX];\n  net_outputs.road_edges = &s->output[RE_IDX];\n  net_outputs.lead = &s->output[LEAD_IDX];\n  net_outputs.lead_prob = &s->output[LEAD_PROB_IDX];\n  net_outputs.meta = &s->output[DESIRE_STATE_IDX];\n  net_outputs.pose = &s->output[POSE_IDX];\n  return net_outputs;\n}\n\nvoid model_free(ModelState* s) {\n  delete s->frame;\n}\n\nstatic const float *get_best_data(const float *data, int size, int group_size, int offset) {\n  int max_idx = 0;\n  for (int i = 1; i < size; i++) {\n    if (data[(i + 1) * group_size + offset] >\n        data[(max_idx + 1) * group_size + offset]) {\n      max_idx = i;\n    }\n  }\n  return &data[max_idx * group_size];\n}\n\nstatic const float *get_plan_data(float *plan) {\n  return get_best_data(plan, PLAN_MHP_N, PLAN_MHP_GROUP_SIZE, -1);\n}\n\nstatic const float *get_lead_data(const float *lead, int t_offset) {\n  return get_best_data(lead, LEAD_MHP_N, LEAD_MHP_GROUP_SIZE, t_offset - LEAD_MHP_SELECTION);\n}\n\n\nvoid fill_sigmoid(const float *input, float *output, int len, int stride) {\n  for (int i=0; i<len; i++) {\n    output[i] = sigmoid(input[i*stride]);\n  }\n}\n\nvoid fill_lead_v3(cereal::ModelDataV2::LeadDataV3::Builder lead, const float *lead_data, const float *prob, int t_offset, float prob_t) {\n  float t[LEAD_TRAJ_LEN] = {0.0, 2.0, 4.0, 6.0, 8.0, 10.0};\n  const float *data = get_lead_data(lead_data, t_offset);\n  lead.setProb(sigmoid(prob[t_offset]));\n  lead.setProbTime(prob_t);\n  float x_arr[LEAD_TRAJ_LEN];\n  float y_arr[LEAD_TRAJ_LEN];\n  float v_arr[LEAD_TRAJ_LEN];\n  float a_arr[LEAD_TRAJ_LEN];\n  float x_stds_arr[LEAD_TRAJ_LEN];\n  float y_stds_arr[LEAD_TRAJ_LEN];\n  float v_stds_arr[LEAD_TRAJ_LEN];\n  float a_stds_arr[LEAD_TRAJ_LEN];\n  for (int i=0; i<LEAD_TRAJ_LEN; i++) {\n    x_arr[i] = data[i*LEAD_PRED_DIM+0];\n    y_arr[i] = data[i*LEAD_PRED_DIM+1];\n    v_arr[i] = data[i*LEAD_PRED_DIM+2];\n    a_arr[i] = data[i*LEAD_PRED_DIM+3];\n    x_stds_arr[i] = exp(data[LEAD_MHP_VALS + i*LEAD_PRED_DIM+0]);\n    y_stds_arr[i] = exp(data[LEAD_MHP_VALS + i*LEAD_PRED_DIM+1]);\n    v_stds_arr[i] = exp(data[LEAD_MHP_VALS + i*LEAD_PRED_DIM+2]);\n    a_stds_arr[i] = exp(data[LEAD_MHP_VALS + i*LEAD_PRED_DIM+3]);\n  }\n  lead.setT(t);\n  lead.setX(x_arr);\n  lead.setY(y_arr);\n  lead.setV(v_arr);\n  lead.setA(a_arr);\n  lead.setXStd(x_stds_arr);\n  lead.setYStd(y_stds_arr);\n  lead.setVStd(v_stds_arr);\n  lead.setAStd(a_stds_arr);\n}\n\nvoid fill_meta(cereal::ModelDataV2::MetaData::Builder meta, const float *meta_data) {\n  float desire_state_softmax[DESIRE_LEN];\n  float desire_pred_softmax[4*DESIRE_LEN];\n  softmax(&meta_data[0], desire_state_softmax, DESIRE_LEN);\n  for (int i=0; i<4; i++) {\n    softmax(&meta_data[DESIRE_LEN + OTHER_META_SIZE + i*DESIRE_LEN],\n            &desire_pred_softmax[i*DESIRE_LEN], DESIRE_LEN);\n  }\n\n  float gas_disengage_sigmoid[NUM_META_INTERVALS];\n  float brake_disengage_sigmoid[NUM_META_INTERVALS];\n  float steer_override_sigmoid[NUM_META_INTERVALS];\n  float brake_3ms2_sigmoid[NUM_META_INTERVALS];\n  float brake_4ms2_sigmoid[NUM_META_INTERVALS];\n  float brake_5ms2_sigmoid[NUM_META_INTERVALS];\n\n  fill_sigmoid(&meta_data[DESIRE_LEN+1], gas_disengage_sigmoid, NUM_META_INTERVALS, META_STRIDE);\n  fill_sigmoid(&meta_data[DESIRE_LEN+2], brake_disengage_sigmoid, NUM_META_INTERVALS, META_STRIDE);\n  fill_sigmoid(&meta_data[DESIRE_LEN+3], steer_override_sigmoid, NUM_META_INTERVALS, META_STRIDE);\n  fill_sigmoid(&meta_data[DESIRE_LEN+4], brake_3ms2_sigmoid, NUM_META_INTERVALS, META_STRIDE);\n  fill_sigmoid(&meta_data[DESIRE_LEN+5], brake_4ms2_sigmoid, NUM_META_INTERVALS, META_STRIDE);\n  fill_sigmoid(&meta_data[DESIRE_LEN+6], brake_5ms2_sigmoid, NUM_META_INTERVALS, META_STRIDE);\n    //fill_sigmoid(&meta_data[DESIRE_LEN+7], GAS PRESSED, NUM_META_INTERVALS, META_STRIDE);\n\n  std::memmove(prev_brake_5ms2_probs, &prev_brake_5ms2_probs[1], 4*sizeof(float));\n  std::memmove(prev_brake_3ms2_probs, &prev_brake_3ms2_probs[1], 2*sizeof(float));\n  prev_brake_5ms2_probs[4] = brake_5ms2_sigmoid[0];\n  prev_brake_3ms2_probs[2] = brake_3ms2_sigmoid[0];\n\n  bool above_fcw_threshold = true;\n  for (int i=0; i<5; i++) {\n    float threshold = i < 2 ? FCW_THRESHOLD_5MS2_LOW : FCW_THRESHOLD_5MS2_HIGH;\n    above_fcw_threshold = above_fcw_threshold && prev_brake_5ms2_probs[i] > threshold;\n  }\n  for (int i=0; i<3; i++) {\n    above_fcw_threshold = above_fcw_threshold && prev_brake_3ms2_probs[i] > FCW_THRESHOLD_3MS2;\n  }\n\n  auto disengage = meta.initDisengagePredictions();\n  disengage.setT({2,4,6,8,10});\n  disengage.setGasDisengageProbs(gas_disengage_sigmoid);\n  disengage.setBrakeDisengageProbs(brake_disengage_sigmoid);\n  disengage.setSteerOverrideProbs(steer_override_sigmoid);\n  disengage.setBrake3MetersPerSecondSquaredProbs(brake_3ms2_sigmoid);\n  disengage.setBrake4MetersPerSecondSquaredProbs(brake_4ms2_sigmoid);\n  disengage.setBrake5MetersPerSecondSquaredProbs(brake_5ms2_sigmoid);\n\n  meta.setEngagedProb(sigmoid(meta_data[DESIRE_LEN]));\n  meta.setDesirePrediction(desire_pred_softmax);\n  meta.setDesireState(desire_state_softmax);\n  meta.setHardBrakePredicted(above_fcw_threshold);\n}\n\nvoid fill_xyzt(cereal::ModelDataV2::XYZTData::Builder xyzt, const float * data,\n               int columns, int column_offset, float * plan_t_arr, bool fill_std) {\n  float x_arr[TRAJECTORY_SIZE] = {};\n  float y_arr[TRAJECTORY_SIZE] = {};\n  float z_arr[TRAJECTORY_SIZE] = {};\n  float x_std_arr[TRAJECTORY_SIZE];\n  float y_std_arr[TRAJECTORY_SIZE];\n  float z_std_arr[TRAJECTORY_SIZE];\n  float t_arr[TRAJECTORY_SIZE];\n  for (int i=0; i<TRAJECTORY_SIZE; i++) {\n    // column_offset == -1 means this data is X indexed not T indexed\n    if (column_offset >= 0) {\n      t_arr[i] = T_IDXS[i];\n      x_arr[i] = data[i*columns + 0 + column_offset];\n      x_std_arr[i] = data[columns*(TRAJECTORY_SIZE + i) + 0 + column_offset];\n    } else {\n      t_arr[i] = plan_t_arr[i];\n      x_arr[i] = X_IDXS[i];\n      x_std_arr[i] = NAN;\n    }\n    y_arr[i] = data[i*columns + 1 + column_offset];\n    y_std_arr[i] = data[columns*(TRAJECTORY_SIZE + i) + 1 + column_offset];\n    z_arr[i] = data[i*columns + 2 + column_offset];\n    z_std_arr[i] = data[columns*(TRAJECTORY_SIZE + i) + 2 + column_offset];\n  }\n  xyzt.setX(x_arr);\n  xyzt.setY(y_arr);\n  xyzt.setZ(z_arr);\n  xyzt.setT(t_arr);\n  if (fill_std) {\n    xyzt.setXStd(x_std_arr);\n    xyzt.setYStd(y_std_arr);\n    xyzt.setZStd(z_std_arr);\n  }\n}\n\nvoid fill_model(cereal::ModelDataV2::Builder &framed, const ModelDataRaw &net_outputs) {\n  // plan\n  const float *best_plan = get_plan_data(net_outputs.plan);\n  float plan_t_arr[TRAJECTORY_SIZE];\n  std::fill_n(plan_t_arr, TRAJECTORY_SIZE, NAN);\n  plan_t_arr[0] = 0.0;\n  for (int xidx=1, tidx=0; xidx<TRAJECTORY_SIZE; xidx++) {\n    // increment tidx until we find an element that's further away than the current xidx\n    while (tidx < TRAJECTORY_SIZE-1 && best_plan[(tidx+1)*PLAN_MHP_COLUMNS] < X_IDXS[xidx]) {\n      tidx++;\n    }\n    float current_x_val = best_plan[tidx*PLAN_MHP_COLUMNS];\n    float next_x_val = best_plan[(tidx+1)*PLAN_MHP_COLUMNS];\n    if (next_x_val < X_IDXS[xidx]) {\n      // if the plan doesn't extend far enough, set plan_t to the max value (10s), then break\n      plan_t_arr[xidx] = T_IDXS[TRAJECTORY_SIZE-1];\n      break;\n    } else {\n      // otherwise, interpolate to find `t` for the current xidx\n      float p = (X_IDXS[xidx] - current_x_val) / (next_x_val - current_x_val);\n      plan_t_arr[xidx] = p * T_IDXS[tidx+1] + (1 - p) * T_IDXS[tidx];\n    }\n  }\n\n  fill_xyzt(framed.initPosition(), best_plan, PLAN_MHP_COLUMNS, 0, plan_t_arr, true);\n  fill_xyzt(framed.initVelocity(), best_plan, PLAN_MHP_COLUMNS, 3, plan_t_arr, false);\n  fill_xyzt(framed.initOrientation(), best_plan, PLAN_MHP_COLUMNS, 9, plan_t_arr, false);\n  fill_xyzt(framed.initOrientationRate(), best_plan, PLAN_MHP_COLUMNS, 12, plan_t_arr, false);\n\n  // lane lines\n  auto lane_lines = framed.initLaneLines(4);\n  float lane_line_probs_arr[4];\n  float lane_line_stds_arr[4];\n  for (int i = 0; i < 4; i++) {\n    fill_xyzt(lane_lines[i], &net_outputs.lane_lines[i*TRAJECTORY_SIZE*2], 2, -1, plan_t_arr, false);\n    lane_line_probs_arr[i] = sigmoid(net_outputs.lane_lines_prob[i*2+1]);\n    lane_line_stds_arr[i] = exp(net_outputs.lane_lines[2*TRAJECTORY_SIZE*(4 + i)]);\n  }\n  framed.setLaneLineProbs(lane_line_probs_arr);\n  framed.setLaneLineStds(lane_line_stds_arr);\n\n  // road edges\n  auto road_edges = framed.initRoadEdges(2);\n  float road_edge_stds_arr[2];\n  for (int i = 0; i < 2; i++) {\n    fill_xyzt(road_edges[i], &net_outputs.road_edges[i*TRAJECTORY_SIZE*2], 2, -1, plan_t_arr, false);\n    road_edge_stds_arr[i] = exp(net_outputs.road_edges[2*TRAJECTORY_SIZE*(2 + i)]);\n  }\n  framed.setRoadEdgeStds(road_edge_stds_arr);\n\n  // meta\n  fill_meta(framed.initMeta(), net_outputs.meta);\n\n  // leads\n  auto leads = framed.initLeadsV3(LEAD_MHP_SELECTION);\n  float t_offsets[LEAD_MHP_SELECTION] = {0.0, 2.0, 4.0};\n  for (int t_offset=0; t_offset<LEAD_MHP_SELECTION; t_offset++) {\n    fill_lead_v3(leads[t_offset], net_outputs.lead, net_outputs.lead_prob, t_offset, t_offsets[t_offset]);\n  }\n}\n\nvoid model_publish(PubMaster &pm, uint32_t vipc_frame_id, uint32_t frame_id, float frame_drop,\n                   const ModelDataRaw &net_outputs, uint64_t timestamp_eof,\n                   float model_execution_time, kj::ArrayPtr<const float> raw_pred) {\n  const uint32_t frame_age = (frame_id > vipc_frame_id) ? (frame_id - vipc_frame_id) : 0;\n  MessageBuilder msg;\n  auto framed = msg.initEvent().initModelV2();\n  framed.setFrameId(vipc_frame_id);\n  framed.setFrameAge(frame_age);\n  framed.setFrameDropPerc(frame_drop * 100);\n  framed.setTimestampEof(timestamp_eof);\n  framed.setModelExecutionTime(model_execution_time);\n  if (send_raw_pred) {\n    framed.setRawPredictions(raw_pred.asBytes());\n  }\n  fill_model(framed, net_outputs);\n  pm.send(\"modelV2\", msg);\n}\n\nvoid posenet_publish(PubMaster &pm, uint32_t vipc_frame_id, uint32_t vipc_dropped_frames,\n                     const ModelDataRaw &net_outputs, uint64_t timestamp_eof) {\n  float trans_arr[3];\n  float trans_std_arr[3];\n  float rot_arr[3];\n  float rot_std_arr[3];\n\n  for (int i =0; i < 3; i++) {\n    trans_arr[i] = net_outputs.pose[i];\n    trans_std_arr[i] = exp(net_outputs.pose[6 + i]);\n\n    rot_arr[i] = net_outputs.pose[3 + i];\n    rot_std_arr[i] = exp(net_outputs.pose[9 + i]);\n  }\n\n  MessageBuilder msg;\n  auto posenetd = msg.initEvent(vipc_dropped_frames < 1).initCameraOdometry();\n  posenetd.setTrans(trans_arr);\n  posenetd.setRot(rot_arr);\n  posenetd.setTransStd(trans_std_arr);\n  posenetd.setRotStd(rot_std_arr);\n\n  posenetd.setTimestampEof(timestamp_eof);\n  posenetd.setFrameId(vipc_frame_id);\n\n  pm.send(\"cameraOdometry\", msg);\n}\n"
  },
  {
    "path": "selfdrive/modeld/models/driving.h",
    "content": "#pragma once\n\n// gate this here\n#define TEMPORAL\n#define DESIRE\n#define TRAFFIC_CONVENTION\n\n#include <memory>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/modeldata.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/modeld/models/commonmodel.h\"\n#include \"selfdrive/modeld/runners/run.h\"\n\nconstexpr int DESIRE_LEN = 8;\nconstexpr int TRAFFIC_CONVENTION_LEN = 2;\nconstexpr int MODEL_FREQ = 20;\n\nstruct ModelDataRaw {\n  float *plan;\n  float *lane_lines;\n  float *lane_lines_prob;\n  float *road_edges;\n  float *lead;\n  float *lead_prob;\n  float *desire_state;\n  float *meta;\n  float *desire_pred;\n  float *pose;\n};\n\ntypedef struct ModelState {\n  ModelFrame *frame;\n  std::vector<float> output;\n  std::unique_ptr<RunModel> m;\n#ifdef DESIRE\n  float prev_desire[DESIRE_LEN] = {};\n  float pulse_desire[DESIRE_LEN] = {};\n#endif\n#ifdef TRAFFIC_CONVENTION\n  float traffic_convention[TRAFFIC_CONVENTION_LEN] = {};\n#endif\n} ModelState;\n\nvoid model_init(ModelState* s, cl_device_id device_id, cl_context context);\nModelDataRaw model_eval_frame(ModelState* s, cl_mem yuv_cl, int width, int height,\n                           const mat3 &transform, float *desire_in);\nvoid model_free(ModelState* s);\nvoid poly_fit(float *in_pts, float *in_stds, float *out);\nvoid model_publish(PubMaster &pm, uint32_t vipc_frame_id, uint32_t frame_id, float frame_drop,\n                   const ModelDataRaw &net_outputs, uint64_t timestamp_eof,\n                   float model_execution_time, kj::ArrayPtr<const float> raw_pred);\nvoid posenet_publish(PubMaster &pm, uint32_t vipc_frame_id, uint32_t vipc_dropped_frames,\n                     const ModelDataRaw &net_outputs, uint64_t timestamp_eof);\n"
  },
  {
    "path": "selfdrive/modeld/runners/onnx_runner.py",
    "content": "#!/usr/bin/env python3\n\nimport os\nimport sys\nimport numpy as np\n\nos.environ[\"OMP_NUM_THREADS\"] = \"4\"\n\nimport onnxruntime as ort\n\ndef read(sz):\n  dd = []\n  gt = 0\n  while gt < sz * 4:\n    st = os.read(0, sz * 4 - gt)\n    assert(len(st) > 0)\n    dd.append(st)\n    gt += len(st)\n  return np.frombuffer(b''.join(dd), dtype=np.float32)\n\ndef write(d):\n  os.write(1, d.tobytes())\n\ndef run_loop(m):\n  ishapes = [[1]+ii.shape[1:] for ii in m.get_inputs()]\n  keys = [x.name for x in m.get_inputs()]\n  print(\"ready to run onnx model\", keys, ishapes, file=sys.stderr)\n  while 1:\n    inputs = []\n    for shp in ishapes:\n      ts = np.product(shp)\n      #print(\"reshaping %s with offset %d\" % (str(shp), offset), file=sys.stderr)\n      inputs.append(read(ts).reshape(shp))\n    ret = m.run(None, dict(zip(keys, inputs)))\n    #print(ret, file=sys.stderr)\n    for r in ret:\n      write(r)\n\n\nif __name__ == \"__main__\":\n  print(ort.get_available_providers(), file=sys.stderr)\n  if 'OpenVINOExecutionProvider' in ort.get_available_providers() and 'ONNXCPU' not in os.environ:\n    print(\"OnnxJit is using openvino\", file=sys.stderr)\n    options = ort.SessionOptions()\n    options.graph_optimization_level = ort.GraphOptimizationLevel.ORT_DISABLE_ALL\n    provider = 'OpenVINOExecutionProvider'\n  elif 'CUDAExecutionProvider' in ort.get_available_providers():\n    print(\"OnnxJit is using CUDA\", file=sys.stderr)\n    options = ort.SessionOptions()\n    options.graph_optimization_level = ort.GraphOptimizationLevel.ORT_DISABLE_ALL\n    provider = 'CUDAExecutionProvider'\n  else:\n    print(\"OnnxJit is using CPU\", file=sys.stderr)\n    options = ort.SessionOptions()\n    options.intra_op_num_threads = 4\n    options.inter_op_num_threads = 8\n    options.execution_mode = ort.ExecutionMode.ORT_SEQUENTIAL\n    options.graph_optimization_level = ort.GraphOptimizationLevel.ORT_ENABLE_ALL\n\n    provider = 'CPUExecutionProvider'\n\n  ort_session = ort.InferenceSession(sys.argv[1], options)\n  ort_session.set_providers([provider], None)\n  run_loop(ort_session)\n"
  },
  {
    "path": "selfdrive/modeld/runners/onnxmodel.cc",
    "content": "#include \"selfdrive/modeld/runners/onnxmodel.h\"\n\n#include <poll.h>\n#include <unistd.h>\n\n#include <cassert>\n#include <csignal>\n#include <cstdio>\n#include <cstdlib>\n#include <cstring>\n#include <stdexcept>\n#include <string>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n\nONNXModel::ONNXModel(const char *path, float *_output, size_t _output_size, int runtime) {\n  LOGD(\"loading model %s\", path);\n\n  output = _output;\n  output_size = _output_size;\n\n  int err = pipe(pipein);\n  assert(err == 0);\n  err = pipe(pipeout);\n  assert(err == 0);\n\n  std::string exe_dir = util::dir_name(util::readlink(\"/proc/self/exe\"));\n  std::string onnx_runner = exe_dir + \"/runners/onnx_runner.py\";\n\n  proc_pid = fork();\n  if (proc_pid == 0) {\n    LOGD(\"spawning onnx process %s\", onnx_runner.c_str());\n    char *argv[] = {(char*)onnx_runner.c_str(), (char*)path, nullptr};\n    dup2(pipein[0], 0);\n    dup2(pipeout[1], 1);\n    close(pipein[0]);\n    close(pipein[1]);\n    close(pipeout[0]);\n    close(pipeout[1]);\n    execvp(onnx_runner.c_str(), argv);\n  }\n\n  // parent\n  close(pipein[0]);\n  close(pipeout[1]);\n}\n\nONNXModel::~ONNXModel() {\n  close(pipein[1]);\n  close(pipeout[0]);\n  kill(proc_pid, SIGTERM);\n}\n\nvoid ONNXModel::pwrite(float *buf, int size) {\n  char *cbuf = (char *)buf;\n  int tw = size*sizeof(float);\n  while (tw > 0) {\n    int err = write(pipein[1], cbuf, tw);\n    //printf(\"host write %d\\n\", err);\n    assert(err >= 0);\n    cbuf += err;\n    tw -= err;\n  }\n  LOGD(\"host write of size %d done\", size);\n}\n\nvoid ONNXModel::pread(float *buf, int size) {\n  char *cbuf = (char *)buf;\n  int tr = size*sizeof(float);\n  struct pollfd fds[1];\n  fds[0].fd = pipeout[0];\n  fds[0].events = POLLIN;\n  while (tr > 0) {\n    int err;\n    err = poll(fds, 1, 10000);  // 10 second timeout\n    assert(err == 1 || (err == -1 && errno == EINTR));\n    LOGD(\"host read remaining %d/%d poll %d\", tr, size*sizeof(float), err);\n    err = read(pipeout[0], cbuf, tr);\n    assert(err > 0 || (err == 0 && errno == EINTR));\n    cbuf += err;\n    tr -= err;\n  }\n  LOGD(\"host read done\");\n}\n\nvoid ONNXModel::addRecurrent(float *state, int state_size) {\n  rnn_input_buf = state;\n  rnn_state_size = state_size;\n}\n\nvoid ONNXModel::addDesire(float *state, int state_size) {\n  desire_input_buf = state;\n  desire_state_size = state_size;\n}\n\nvoid ONNXModel::addTrafficConvention(float *state, int state_size) {\n  traffic_convention_input_buf = state;\n  traffic_convention_size = state_size;\n}\n\nvoid ONNXModel::execute(float *net_input_buf, int buf_size) {\n  // order must be this\n  pwrite(net_input_buf, buf_size);\n  if (desire_input_buf != NULL) {\n    pwrite(desire_input_buf, desire_state_size);\n  }\n  if (traffic_convention_input_buf != NULL) {\n    pwrite(traffic_convention_input_buf, traffic_convention_size);\n  }\n  if (rnn_input_buf != NULL) {\n    pwrite(rnn_input_buf, rnn_state_size);\n  }\n  pread(output, output_size);\n}\n\n"
  },
  {
    "path": "selfdrive/modeld/runners/onnxmodel.h",
    "content": "#pragma once\n\n#include <stdlib.h>\n\n#include \"selfdrive/modeld/runners/runmodel.h\"\n\nclass ONNXModel : public RunModel {\npublic:\n  ONNXModel(const char *path, float *output, size_t output_size, int runtime);\n\t~ONNXModel();\n  void addRecurrent(float *state, int state_size);\n  void addDesire(float *state, int state_size);\n  void addTrafficConvention(float *state, int state_size);\n  void execute(float *net_input_buf, int buf_size);\nprivate:\n  int proc_pid;\n\n  float *output;\n  size_t output_size;\n\n  float *rnn_input_buf = NULL;\n  int rnn_state_size;\n  float *desire_input_buf = NULL;\n  int desire_state_size;\n  float *traffic_convention_input_buf = NULL;\n  int traffic_convention_size;\n\n  // pipe to communicate to keras subprocess\n  void pread(float *buf, int size);\n  void pwrite(float *buf, int size);\n  int pipein[2];\n  int pipeout[2];\n};\n\n"
  },
  {
    "path": "selfdrive/modeld/runners/run.h",
    "content": "#pragma once\n\n#include \"runmodel.h\"\n#include \"snpemodel.h\"\n\n#if defined(USE_THNEED)\n#include \"thneedmodel.h\"\n#elif defined(USE_ONNX_MODEL)\n#include \"onnxmodel.h\"\n#endif\n"
  },
  {
    "path": "selfdrive/modeld/runners/runmodel.h",
    "content": "#pragma once\nclass RunModel {\npublic:\n  virtual void addRecurrent(float *state, int state_size) {}\n  virtual void addDesire(float *state, int state_size) {}\n  virtual void addTrafficConvention(float *state, int state_size) {}\n  virtual void execute(float *net_input_buf, int buf_size) {}\n};\n\n"
  },
  {
    "path": "selfdrive/modeld/runners/snpemodel.cc",
    "content": "#pragma clang diagnostic ignored \"-Wexceptions\"\n\n#include \"selfdrive/modeld/runners/snpemodel.h\"\n\n#include <cassert>\n#include <cstdlib>\n#include <cstring>\n\n#include \"selfdrive/common/util.h\"\n\nvoid PrintErrorStringAndExit() {\n  std::cerr << zdl::DlSystem::getLastErrorString() << std::endl;\n  std::exit(EXIT_FAILURE);\n}\n\nSNPEModel::SNPEModel(const char *path, float *loutput, size_t loutput_size, int runtime) {\n  output = loutput;\n  output_size = loutput_size;\n#if defined(QCOM) || defined(QCOM2)\n  if (runtime==USE_GPU_RUNTIME) {\n    Runtime = zdl::DlSystem::Runtime_t::GPU;\n  } else if (runtime==USE_DSP_RUNTIME) {\n    Runtime = zdl::DlSystem::Runtime_t::DSP;\n  } else {\n    Runtime = zdl::DlSystem::Runtime_t::CPU;\n  }\n  assert(zdl::SNPE::SNPEFactory::isRuntimeAvailable(Runtime));\n#endif\n  model_data = util::read_file(path);\n  assert(model_data.size() > 0);\n\n  // load model\n  std::unique_ptr<zdl::DlContainer::IDlContainer> container = zdl::DlContainer::IDlContainer::open((uint8_t*)model_data.data(), model_data.size());\n  if (!container) { PrintErrorStringAndExit(); }\n  printf(\"loaded model with size: %lu\\n\", model_data.size());\n\n  // create model runner\n  zdl::SNPE::SNPEBuilder snpeBuilder(container.get());\n  while (!snpe) {\n#if defined(QCOM) || defined(QCOM2)\n    snpe = snpeBuilder.setOutputLayers({})\n                      .setRuntimeProcessor(Runtime)\n                      .setUseUserSuppliedBuffers(true)\n                      .setPerformanceProfile(zdl::DlSystem::PerformanceProfile_t::HIGH_PERFORMANCE)\n                      .build();\n#else\n    snpe = snpeBuilder.setOutputLayers({})\n                      .setUseUserSuppliedBuffers(true)\n                      .setPerformanceProfile(zdl::DlSystem::PerformanceProfile_t::HIGH_PERFORMANCE)\n                      .build();\n#endif\n    if (!snpe) std::cerr << zdl::DlSystem::getLastErrorString() << std::endl;\n  }\n\n  // get input and output names\n  const auto &strListi_opt = snpe->getInputTensorNames();\n  if (!strListi_opt) throw std::runtime_error(\"Error obtaining Input tensor names\");\n  const auto &strListi = *strListi_opt;\n  //assert(strListi.size() == 1);\n  const char *input_tensor_name = strListi.at(0);\n\n  const auto &strListo_opt = snpe->getOutputTensorNames();\n  if (!strListo_opt) throw std::runtime_error(\"Error obtaining Output tensor names\");\n  const auto &strListo = *strListo_opt;\n  assert(strListo.size() == 1);\n  const char *output_tensor_name = strListo.at(0);\n\n  printf(\"model: %s -> %s\\n\", input_tensor_name, output_tensor_name);\n\n  zdl::DlSystem::UserBufferEncodingFloat userBufferEncodingFloat;\n  zdl::DlSystem::IUserBufferFactory& ubFactory = zdl::SNPE::SNPEFactory::getUserBufferFactory();\n\n  // create input buffer\n  {\n    const auto &inputDims_opt = snpe->getInputDimensions(input_tensor_name);\n    const zdl::DlSystem::TensorShape& bufferShape = *inputDims_opt;\n    std::vector<size_t> strides(bufferShape.rank());\n    strides[strides.size() - 1] = sizeof(float);\n    size_t product = 1;\n    for (size_t i = 0; i < bufferShape.rank(); i++) product *= bufferShape[i];\n    size_t stride = strides[strides.size() - 1];\n    for (size_t i = bufferShape.rank() - 1; i > 0; i--) {\n      stride *= bufferShape[i];\n      strides[i-1] = stride;\n    }\n    printf(\"input product is %lu\\n\", product);\n    inputBuffer = ubFactory.createUserBuffer(NULL, product*sizeof(float), strides, &userBufferEncodingFloat);\n\n    inputMap.add(input_tensor_name, inputBuffer.get());\n  }\n\n  // create output buffer\n  {\n    const zdl::DlSystem::TensorShape& bufferShape = snpe->getInputOutputBufferAttributes(output_tensor_name)->getDims();\n    if (output_size != 0) {\n      assert(output_size == bufferShape[1]);\n    } else {\n      output_size = bufferShape[1];\n    }\n\n    std::vector<size_t> outputStrides = {output_size * sizeof(float), sizeof(float)};\n    outputBuffer = ubFactory.createUserBuffer(output, output_size * sizeof(float), outputStrides, &userBufferEncodingFloat);\n    outputMap.add(output_tensor_name, outputBuffer.get());\n  }\n}\n\nvoid SNPEModel::addRecurrent(float *state, int state_size) {\n  recurrent = state;\n  recurrent_size = state_size;\n  recurrentBuffer = this->addExtra(state, state_size, 3);\n}\n\nvoid SNPEModel::addTrafficConvention(float *state, int state_size) {\n  trafficConvention = state;\n  trafficConventionBuffer = this->addExtra(state, state_size, 2);\n}\n\nvoid SNPEModel::addDesire(float *state, int state_size) {\n  desire = state;\n  desireBuffer = this->addExtra(state, state_size, 1);\n}\n\nstd::unique_ptr<zdl::DlSystem::IUserBuffer> SNPEModel::addExtra(float *state, int state_size, int idx) {\n  // get input and output names\n  const auto &strListi_opt = snpe->getInputTensorNames();\n  if (!strListi_opt) throw std::runtime_error(\"Error obtaining Input tensor names\");\n  const auto &strListi = *strListi_opt;\n  const char *input_tensor_name = strListi.at(idx);\n  printf(\"adding index %d: %s\\n\", idx, input_tensor_name);\n\n  zdl::DlSystem::UserBufferEncodingFloat userBufferEncodingFloat;\n  zdl::DlSystem::IUserBufferFactory& ubFactory = zdl::SNPE::SNPEFactory::getUserBufferFactory();\n  std::vector<size_t> retStrides = {state_size * sizeof(float), sizeof(float)};\n  auto ret = ubFactory.createUserBuffer(state, state_size * sizeof(float), retStrides, &userBufferEncodingFloat);\n  inputMap.add(input_tensor_name, ret.get());\n  return ret;\n}\n\nvoid SNPEModel::execute(float *net_input_buf, int buf_size) {\n#ifdef USE_THNEED\n  if (Runtime == zdl::DlSystem::Runtime_t::GPU) {\n    float *inputs[4] = {recurrent, trafficConvention, desire, net_input_buf};\n    if (thneed == NULL) {\n      bool ret = inputBuffer->setBufferAddress(net_input_buf);\n      assert(ret == true);\n      if (!snpe->execute(inputMap, outputMap)) {\n        PrintErrorStringAndExit();\n      }\n      memset(recurrent, 0, recurrent_size*sizeof(float));\n      thneed = new Thneed();\n      if (!snpe->execute(inputMap, outputMap)) {\n        PrintErrorStringAndExit();\n      }\n      thneed->stop();\n      printf(\"thneed cached\\n\");\n\n      // doing self test\n      float *outputs_golden = (float *)malloc(output_size*sizeof(float));\n      memcpy(outputs_golden, output, output_size*sizeof(float));\n      memset(output, 0, output_size*sizeof(float));\n      memset(recurrent, 0, recurrent_size*sizeof(float));\n      thneed->execute(inputs, output);\n\n      if (memcmp(output, outputs_golden, output_size*sizeof(float)) == 0) {\n        printf(\"thneed selftest passed\\n\");\n      } else {\n        for (int i = 0; i < output_size; i++) {\n          printf(\"mismatch %3d: %f %f\\n\", i, output[i], outputs_golden[i]);\n        }\n        assert(false);\n      }\n      free(outputs_golden);\n    } else {\n      thneed->execute(inputs, output);\n    }\n  } else {\n#endif\n    bool ret = inputBuffer->setBufferAddress(net_input_buf);\n    assert(ret == true);\n    if (!snpe->execute(inputMap, outputMap)) {\n      PrintErrorStringAndExit();\n    }\n#ifdef USE_THNEED\n  }\n#endif\n}\n\n"
  },
  {
    "path": "selfdrive/modeld/runners/snpemodel.h",
    "content": "#pragma once\n\n#include <DlContainer/IDlContainer.hpp>\n#include <DlSystem/DlError.hpp>\n#include <DlSystem/ITensor.hpp>\n#include <DlSystem/ITensorFactory.hpp>\n#include <DlSystem/IUserBuffer.hpp>\n#include <DlSystem/IUserBufferFactory.hpp>\n#include <SNPE/SNPE.hpp>\n#include <SNPE/SNPEBuilder.hpp>\n#include <SNPE/SNPEFactory.hpp>\n\n#include \"runmodel.h\"\n\n#define USE_CPU_RUNTIME 0\n#define USE_GPU_RUNTIME 1\n#define USE_DSP_RUNTIME 2\n\n#ifdef USE_THNEED\n#include \"selfdrive/modeld/thneed/thneed.h\"\n#endif\n\nclass SNPEModel : public RunModel {\npublic:\n  SNPEModel(const char *path, float *loutput, size_t loutput_size, int runtime);\n  void addRecurrent(float *state, int state_size);\n  void addTrafficConvention(float *state, int state_size);\n  void addDesire(float *state, int state_size);\n  void execute(float *net_input_buf, int buf_size);\n\n#ifdef USE_THNEED\n  Thneed *thneed = NULL;\n#endif\n\nprivate:\n  std::string model_data;\n\n#if defined(QCOM) || defined(QCOM2)\n  zdl::DlSystem::Runtime_t Runtime;\n#endif\n\n  // snpe model stuff\n  std::unique_ptr<zdl::SNPE::SNPE> snpe;\n\n  // snpe input stuff\n  zdl::DlSystem::UserBufferMap inputMap;\n  std::unique_ptr<zdl::DlSystem::IUserBuffer> inputBuffer;\n\n  // snpe output stuff\n  zdl::DlSystem::UserBufferMap outputMap;\n  std::unique_ptr<zdl::DlSystem::IUserBuffer> outputBuffer;\n  float *output;\n  size_t output_size;\n\n  // recurrent and desire\n  std::unique_ptr<zdl::DlSystem::IUserBuffer> addExtra(float *state, int state_size, int idx);\n  float *recurrent;\n  size_t recurrent_size;\n  std::unique_ptr<zdl::DlSystem::IUserBuffer> recurrentBuffer;\n  float *trafficConvention;\n  std::unique_ptr<zdl::DlSystem::IUserBuffer> trafficConventionBuffer;\n  float *desire;\n  std::unique_ptr<zdl::DlSystem::IUserBuffer> desireBuffer;\n};\n"
  },
  {
    "path": "selfdrive/modeld/runners/thneedmodel.cc",
    "content": "#include \"selfdrive/modeld/runners/thneedmodel.h\"\n\n#include <cassert>\n\nThneedModel::ThneedModel(const char *path, float *loutput, size_t loutput_size, int runtime) {\n  thneed = new Thneed(true);\n  thneed->record = 0;\n  thneed->load(path);\n  thneed->clexec();\n  thneed->find_inputs_outputs();\n\n  recorded = false;\n  output = loutput;\n}\n\nvoid ThneedModel::addRecurrent(float *state, int state_size) {\n  recurrent = state;\n}\n\nvoid ThneedModel::addTrafficConvention(float *state, int state_size) {\n  trafficConvention = state;\n}\n\nvoid ThneedModel::addDesire(float *state, int state_size) {\n  desire = state;\n}\n\nvoid ThneedModel::execute(float *net_input_buf, int buf_size) {\n  float *inputs[4] = {recurrent, trafficConvention, desire, net_input_buf};\n  if (!recorded) {\n    thneed->record = THNEED_RECORD;\n    thneed->copy_inputs(inputs);\n    thneed->clexec();\n    thneed->copy_output(output);\n    thneed->stop();\n\n    recorded = true;\n  } else {\n    thneed->execute(inputs, output);\n  }\n}\n\n"
  },
  {
    "path": "selfdrive/modeld/runners/thneedmodel.h",
    "content": "#pragma once\n\n#include \"selfdrive/modeld/runners/runmodel.h\"\n#include \"selfdrive/modeld/thneed/thneed.h\"\n\nclass ThneedModel : public RunModel {\npublic:\n  ThneedModel(const char *path, float *loutput, size_t loutput_size, int runtime);\n  void addRecurrent(float *state, int state_size);\n  void addTrafficConvention(float *state, int state_size);\n  void addDesire(float *state, int state_size);\n  void execute(float *net_input_buf, int buf_size);\nprivate:\n  Thneed *thneed = NULL;\n  bool recorded;\n\n  float *output;\n\n  // recurrent and desire\n  float *recurrent;\n  float *trafficConvention;\n  float *desire;\n};\n\n"
  },
  {
    "path": "selfdrive/modeld/thneed/compile.cc",
    "content": "#include <cstring>\n\n#include \"selfdrive/modeld/runners/snpemodel.h\"\n#include \"selfdrive/modeld/thneed/thneed.h\"\n\n#define TEMPORAL_SIZE 512\n#define DESIRE_LEN 8\n#define TRAFFIC_CONVENTION_LEN 2\n\n// TODO: This should probably use SNPE directly.\nint main(int argc, char* argv[]) {\n  #define OUTPUT_SIZE 0x10000\n  float *output = (float*)calloc(OUTPUT_SIZE, sizeof(float));\n  SNPEModel mdl(argv[1], output, 0, USE_GPU_RUNTIME);\n\n  float state[TEMPORAL_SIZE] = {0};\n  float desire[DESIRE_LEN] = {0};\n  float traffic_convention[TRAFFIC_CONVENTION_LEN] = {0};\n  float *input = (float*)calloc(0x1000000, sizeof(float));\n\n  mdl.addRecurrent(state, TEMPORAL_SIZE);\n  mdl.addDesire(desire, DESIRE_LEN);\n  mdl.addTrafficConvention(traffic_convention, TRAFFIC_CONVENTION_LEN);\n\n  // first run\n  printf(\"************** execute 1 **************\\n\");\n  memset(output, 0, OUTPUT_SIZE * sizeof(float));\n  mdl.execute(input, 0);\n\n  // save model\n  bool save_binaries = (argc > 3) && (strcmp(argv[3], \"--binary\") == 0);\n  mdl.thneed->save(argv[2], save_binaries);\n  return 0;\n}\n\n"
  },
  {
    "path": "selfdrive/modeld/thneed/include/msm_kgsl.h",
    "content": "#ifndef _UAPI_MSM_KGSL_H\n#define _UAPI_MSM_KGSL_H\n\n#include <linux/types.h>\n#include <linux/ioctl.h>\n\n/*\n * The KGSL version has proven not to be very useful in userspace if features\n * are cherry picked into other trees out of order so it is frozen as of 3.14.\n * It is left here for backwards compatabilty and as a reminder that\n * software releases are never linear. Also, I like pie.\n */\n\n#define KGSL_VERSION_MAJOR        3\n#define KGSL_VERSION_MINOR        14\n\n/*\n * We have traditionally mixed context and issueibcmds / command batch flags\n * together into a big flag stew. This worked fine until we started adding a\n * lot more command batch flags and we started running out of bits. Turns out\n * we have a bit of room in the context type / priority mask that we could use\n * for command batches, but that means we need to split out the flags into two\n * coherent sets.\n *\n * If any future definitions are for both context and cmdbatch add both defines\n * and link the cmdbatch to the context define as we do below. Otherwise feel\n * free to add exclusive bits to either set.\n */\n\n/* --- context flags --- */\n#define KGSL_CONTEXT_SAVE_GMEM\t\t0x00000001\n#define KGSL_CONTEXT_NO_GMEM_ALLOC\t0x00000002\n/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */\n#define KGSL_CONTEXT_SUBMIT_IB_LIST\t0x00000004\n#define KGSL_CONTEXT_CTX_SWITCH\t\t0x00000008\n#define KGSL_CONTEXT_PREAMBLE\t\t0x00000010\n#define KGSL_CONTEXT_TRASH_STATE\t0x00000020\n#define KGSL_CONTEXT_PER_CONTEXT_TS\t0x00000040\n#define KGSL_CONTEXT_USER_GENERATED_TS\t0x00000080\n/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */\n#define KGSL_CONTEXT_END_OF_FRAME\t0x00000100\n#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200\n/* This is a cmdbatch exclusive flag - use the CMDBATCH equivalent instead */\n#define KGSL_CONTEXT_SYNC               0x00000400\n#define KGSL_CONTEXT_PWR_CONSTRAINT     0x00000800\n\n#define KGSL_CONTEXT_PRIORITY_MASK      0x0000F000\n#define KGSL_CONTEXT_PRIORITY_SHIFT     12\n#define KGSL_CONTEXT_PRIORITY_UNDEF     0\n\n#define KGSL_CONTEXT_IFH_NOP            0x00010000\n#define KGSL_CONTEXT_SECURE             0x00020000\n\n#define KGSL_CONTEXT_PREEMPT_STYLE_MASK       0x0E000000\n#define KGSL_CONTEXT_PREEMPT_STYLE_SHIFT      25\n#define KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT    0x0\n#define KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER 0x1\n#define KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN  0x2\n\n#define KGSL_CONTEXT_TYPE_MASK          0x01F00000\n#define KGSL_CONTEXT_TYPE_SHIFT         20\n#define KGSL_CONTEXT_TYPE_ANY\t\t0\n#define KGSL_CONTEXT_TYPE_GL\t\t1\n#define KGSL_CONTEXT_TYPE_CL\t\t2\n#define KGSL_CONTEXT_TYPE_C2D\t\t3\n#define KGSL_CONTEXT_TYPE_RS\t\t4\n#define KGSL_CONTEXT_TYPE_UNKNOWN\t0x1E\n\n#define KGSL_CONTEXT_INVALID 0xffffffff\n\n/*\n * --- command batch flags ---\n * The bits that are linked to a KGSL_CONTEXT equivalent are either legacy\n * definitions or bits that are valid for both contexts and cmdbatches.  To be\n * safe the other 8 bits that are still available in the context field should be\n * omitted here in case we need to share - the other bits are available for\n * cmdbatch only flags as needed\n */\n#define KGSL_CMDBATCH_MEMLIST\t\t0x00000001\n#define KGSL_CMDBATCH_MARKER\t\t0x00000002\n#define KGSL_CMDBATCH_SUBMIT_IB_LIST\tKGSL_CONTEXT_SUBMIT_IB_LIST /* 0x004 */\n#define KGSL_CMDBATCH_CTX_SWITCH\tKGSL_CONTEXT_CTX_SWITCH     /* 0x008 */\n#define KGSL_CMDBATCH_PROFILING\t\t0x00000010\n#define KGSL_CMDBATCH_PROFILING_KTIME\t0x00000020\n#define KGSL_CMDBATCH_END_OF_FRAME\tKGSL_CONTEXT_END_OF_FRAME   /* 0x100 */\n#define KGSL_CMDBATCH_SYNC\t\tKGSL_CONTEXT_SYNC           /* 0x400 */\n#define KGSL_CMDBATCH_PWR_CONSTRAINT\tKGSL_CONTEXT_PWR_CONSTRAINT /* 0x800 */\n\n/*\n * Reserve bits [16:19] and bits [28:31] for possible bits shared between\n * contexts and command batches.  Update this comment as new flags are added.\n */\n\n/*\n * gpu_command_object flags - these flags communicate the type of command or\n * memory object being submitted for a GPU command\n */\n\n/* Flags for GPU command objects */\n#define KGSL_CMDLIST_IB                  0x00000001U\n#define KGSL_CMDLIST_CTXTSWITCH_PREAMBLE 0x00000002U\n#define KGSL_CMDLIST_IB_PREAMBLE         0x00000004U\n\n/* Flags for GPU command memory objects */\n#define KGSL_OBJLIST_MEMOBJ  0x00000008U\n#define KGSL_OBJLIST_PROFILE 0x00000010U\n\n/* Flags for GPU command sync points */\n#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0\n#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1\n\n/* --- Memory allocation flags --- */\n\n/* General allocation hints */\n#define KGSL_MEMFLAGS_SECURE      0x00000008ULL\n#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000U\n#define KGSL_MEMFLAGS_GPUWRITEONLY 0x02000000U\n#define KGSL_MEMFLAGS_FORCE_32BIT 0x100000000ULL\n\n/* Memory caching hints */\n#define KGSL_CACHEMODE_MASK       0x0C000000U\n#define KGSL_CACHEMODE_SHIFT 26\n\n#define KGSL_CACHEMODE_WRITECOMBINE 0\n#define KGSL_CACHEMODE_UNCACHED 1\n#define KGSL_CACHEMODE_WRITETHROUGH 2\n#define KGSL_CACHEMODE_WRITEBACK 3\n\n#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000ULL\n\n/* Memory types for which allocations are made */\n#define KGSL_MEMTYPE_MASK\t\t0x0000FF00\n#define KGSL_MEMTYPE_SHIFT\t\t8\n\n#define KGSL_MEMTYPE_OBJECTANY\t\t\t0\n#define KGSL_MEMTYPE_FRAMEBUFFER\t\t1\n#define KGSL_MEMTYPE_RENDERBUFFER\t\t2\n#define KGSL_MEMTYPE_ARRAYBUFFER\t\t3\n#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER\t\t4\n#define KGSL_MEMTYPE_VERTEXARRAYBUFFER\t\t5\n#define KGSL_MEMTYPE_TEXTURE\t\t\t6\n#define KGSL_MEMTYPE_SURFACE\t\t\t7\n#define KGSL_MEMTYPE_EGL_SURFACE\t\t8\n#define KGSL_MEMTYPE_GL\t\t\t\t9\n#define KGSL_MEMTYPE_CL\t\t\t\t10\n#define KGSL_MEMTYPE_CL_BUFFER_MAP\t\t11\n#define KGSL_MEMTYPE_CL_BUFFER_NOMAP\t\t12\n#define KGSL_MEMTYPE_CL_IMAGE_MAP\t\t13\n#define KGSL_MEMTYPE_CL_IMAGE_NOMAP\t\t14\n#define KGSL_MEMTYPE_CL_KERNEL_STACK\t\t15\n#define KGSL_MEMTYPE_COMMAND\t\t\t16\n#define KGSL_MEMTYPE_2D\t\t\t\t17\n#define KGSL_MEMTYPE_EGL_IMAGE\t\t\t18\n#define KGSL_MEMTYPE_EGL_SHADOW\t\t\t19\n#define KGSL_MEMTYPE_MULTISAMPLE\t\t20\n#define KGSL_MEMTYPE_KERNEL\t\t\t255\n\n/*\n * Alignment hint, passed as the power of 2 exponent.\n * i.e 4k (2^12) would be 12, 64k (2^16)would be 16.\n */\n#define KGSL_MEMALIGN_MASK\t\t0x00FF0000\n#define KGSL_MEMALIGN_SHIFT\t\t16\n\nenum kgsl_user_mem_type {\n\tKGSL_USER_MEM_TYPE_PMEM\t\t= 0x00000000,\n\tKGSL_USER_MEM_TYPE_ASHMEM\t= 0x00000001,\n\tKGSL_USER_MEM_TYPE_ADDR\t\t= 0x00000002,\n\tKGSL_USER_MEM_TYPE_ION\t\t= 0x00000003,\n\t/*\n\t * ION type is retained for backwards compatibilty but Ion buffers are\n\t * dma-bufs so try to use that naming if we can\n\t */\n\tKGSL_USER_MEM_TYPE_DMABUF       = 0x00000003,\n\tKGSL_USER_MEM_TYPE_MAX\t\t= 0x00000007,\n};\n#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0\n#define KGSL_MEMFLAGS_USERMEM_SHIFT 5\n\n/*\n * Unfortunately, enum kgsl_user_mem_type starts at 0 which does not\n * leave a good value for allocated memory. In the flags we use\n * 0 to indicate allocated memory and thus need to add 1 to the enum\n * values.\n */\n#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT)\n\n#define KGSL_MEMFLAGS_NOT_USERMEM 0\n#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM)\n#define KGSL_MEMFLAGS_USERMEM_ASHMEM \\\n\t\tKGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM)\n#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR)\n#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION)\n\n/* --- generic KGSL flag values --- */\n\n#define KGSL_FLAGS_NORMALMODE  0x00000000\n#define KGSL_FLAGS_SAFEMODE    0x00000001\n#define KGSL_FLAGS_INITIALIZED0 0x00000002\n#define KGSL_FLAGS_INITIALIZED 0x00000004\n#define KGSL_FLAGS_STARTED     0x00000008\n#define KGSL_FLAGS_ACTIVE      0x00000010\n#define KGSL_FLAGS_RESERVED0   0x00000020\n#define KGSL_FLAGS_RESERVED1   0x00000040\n#define KGSL_FLAGS_RESERVED2   0x00000080\n#define KGSL_FLAGS_SOFT_RESET  0x00000100\n#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200\n\n/* Server Side Sync Timeout in milliseconds */\n#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000\n\n/*\n * Reset status values for context\n */\nenum kgsl_ctx_reset_stat {\n\tKGSL_CTX_STAT_NO_ERROR\t\t\t\t= 0x00000000,\n\tKGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT\t\t= 0x00000001,\n\tKGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT\t= 0x00000002,\n\tKGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT\t\t= 0x00000003\n};\n\n#define KGSL_CONVERT_TO_MBPS(val) \\\n\t(val*1000*1000U)\n\n/* device id */\nenum kgsl_deviceid {\n\tKGSL_DEVICE_3D0\t\t= 0x00000000,\n\tKGSL_DEVICE_MAX\n};\n\nstruct kgsl_devinfo {\n\n\tunsigned int device_id;\n\t/* chip revision id\n\t* coreid:8 majorrev:8 minorrev:8 patch:8\n\t*/\n\tunsigned int chip_id;\n\tunsigned int mmu_enabled;\n\tunsigned long gmem_gpubaseaddr;\n\t/*\n\t* This field contains the adreno revision\n\t* number 200, 205, 220, etc...\n\t*/\n\tunsigned int gpu_id;\n\tsize_t gmem_sizebytes;\n};\n\n/*\n * struct kgsl_devmemstore - this structure defines the region of memory\n * that can be mmap()ed from this driver. The timestamp fields are volatile\n * because they are written by the GPU\n * @soptimestamp: Start of pipeline timestamp written by GPU before the\n * commands in concern are processed\n * @sbz: Unused, kept for 8 byte alignment\n * @eoptimestamp: End of pipeline timestamp written by GPU after the\n * commands in concern are processed\n * @sbz2: Unused, kept for 8 byte alignment\n * @preempted: Indicates if the context was preempted\n * @sbz3: Unused, kept for 8 byte alignment\n * @ref_wait_ts: Timestamp on which to generate interrupt, unused now.\n * @sbz4: Unused, kept for 8 byte alignment\n * @current_context: The current context the GPU is working on\n * @sbz5: Unused, kept for 8 byte alignment\n */\nstruct kgsl_devmemstore {\n\tvolatile unsigned int soptimestamp;\n\tunsigned int sbz;\n\tvolatile unsigned int eoptimestamp;\n\tunsigned int sbz2;\n\tvolatile unsigned int preempted;\n\tunsigned int sbz3;\n\tvolatile unsigned int ref_wait_ts;\n\tunsigned int sbz4;\n\tunsigned int current_context;\n\tunsigned int sbz5;\n};\n\n#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \\\n\t((ctxt_id)*sizeof(struct kgsl_devmemstore) + \\\n\t offsetof(struct kgsl_devmemstore, field))\n\n/* timestamp id*/\nenum kgsl_timestamp_type {\n\tKGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */\n\tKGSL_TIMESTAMP_RETIRED  = 0x00000002, /* end-of-pipeline timestamp*/\n\tKGSL_TIMESTAMP_QUEUED   = 0x00000003,\n};\n\n/* property types - used with kgsl_device_getproperty */\n#define KGSL_PROP_DEVICE_INFO\t\t0x1\n#define KGSL_PROP_DEVICE_SHADOW\t\t0x2\n#define KGSL_PROP_DEVICE_POWER\t\t0x3\n#define KGSL_PROP_SHMEM\t\t\t0x4\n#define KGSL_PROP_SHMEM_APERTURES\t0x5\n#define KGSL_PROP_MMU_ENABLE\t\t0x6\n#define KGSL_PROP_INTERRUPT_WAITS\t0x7\n#define KGSL_PROP_VERSION\t\t0x8\n#define KGSL_PROP_GPU_RESET_STAT\t0x9\n#define KGSL_PROP_PWRCTRL\t\t0xE\n#define KGSL_PROP_PWR_CONSTRAINT\t0x12\n#define KGSL_PROP_UCHE_GMEM_VADDR\t0x13\n#define KGSL_PROP_SP_GENERIC_MEM\t0x14\n#define KGSL_PROP_UCODE_VERSION\t\t0x15\n#define KGSL_PROP_GPMU_VERSION\t\t0x16\n#define KGSL_PROP_DEVICE_BITNESS\t0x18\n\nstruct kgsl_shadowprop {\n\tunsigned long gpuaddr;\n\tsize_t size;\n\tunsigned int flags; /* contains KGSL_FLAGS_ values */\n};\n\nstruct kgsl_version {\n\tunsigned int drv_major;\n\tunsigned int drv_minor;\n\tunsigned int dev_major;\n\tunsigned int dev_minor;\n};\n\nstruct kgsl_sp_generic_mem {\n\tuint64_t local;\n\tuint64_t pvt;\n};\n\nstruct kgsl_ucode_version {\n\tunsigned int pfp;\n\tunsigned int pm4;\n};\n\nstruct kgsl_gpmu_version {\n\tunsigned int major;\n\tunsigned int minor;\n\tunsigned int features;\n};\n\n/* Performance counter groups */\n\n#define KGSL_PERFCOUNTER_GROUP_CP 0x0\n#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1\n#define KGSL_PERFCOUNTER_GROUP_PC 0x2\n#define KGSL_PERFCOUNTER_GROUP_VFD 0x3\n#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4\n#define KGSL_PERFCOUNTER_GROUP_VPC 0x5\n#define KGSL_PERFCOUNTER_GROUP_TSE 0x6\n#define KGSL_PERFCOUNTER_GROUP_RAS 0x7\n#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8\n#define KGSL_PERFCOUNTER_GROUP_TP 0x9\n#define KGSL_PERFCOUNTER_GROUP_SP 0xA\n#define KGSL_PERFCOUNTER_GROUP_RB 0xB\n#define KGSL_PERFCOUNTER_GROUP_PWR 0xC\n#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD\n#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE\n#define KGSL_PERFCOUNTER_GROUP_MH 0xF\n#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10\n#define KGSL_PERFCOUNTER_GROUP_SQ 0x11\n#define KGSL_PERFCOUNTER_GROUP_SX 0x12\n#define KGSL_PERFCOUNTER_GROUP_TCF 0x13\n#define KGSL_PERFCOUNTER_GROUP_TCM 0x14\n#define KGSL_PERFCOUNTER_GROUP_TCR 0x15\n#define KGSL_PERFCOUNTER_GROUP_L2 0x16\n#define KGSL_PERFCOUNTER_GROUP_VSC 0x17\n#define KGSL_PERFCOUNTER_GROUP_CCU 0x18\n#define KGSL_PERFCOUNTER_GROUP_LRZ 0x19\n#define KGSL_PERFCOUNTER_GROUP_CMP 0x1A\n#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B\n#define KGSL_PERFCOUNTER_GROUP_SP_PWR 0x1C\n#define KGSL_PERFCOUNTER_GROUP_TP_PWR 0x1D\n#define KGSL_PERFCOUNTER_GROUP_RB_PWR 0x1E\n#define KGSL_PERFCOUNTER_GROUP_CCU_PWR 0x1F\n#define KGSL_PERFCOUNTER_GROUP_UCHE_PWR 0x20\n#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21\n#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22\n#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23\n#define KGSL_PERFCOUNTER_GROUP_MAX 0x24\n\n#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF\n#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE\n\n/* structure holds list of ibs */\nstruct kgsl_ibdesc {\n\tunsigned long gpuaddr;\n\tunsigned long __pad;\n\tsize_t sizedwords;\n\tunsigned int ctrl;\n};\n\n/**\n * struct kgsl_cmdbatch_profiling_buffer\n * @wall_clock_s: Ringbuffer submission time (seconds).\n *                If KGSL_CMDBATCH_PROFILING_KTIME is set, time is provided\n *                in kernel clocks, otherwise wall clock time is used.\n * @wall_clock_ns: Ringbuffer submission time (nanoseconds).\n *                 If KGSL_CMDBATCH_PROFILING_KTIME is set time is provided\n *                 in kernel clocks, otherwise wall clock time is used.\n * @gpu_ticks_queued: GPU ticks at ringbuffer submission\n * @gpu_ticks_submitted: GPU ticks when starting cmdbatch execution\n * @gpu_ticks_retired: GPU ticks when finishing cmdbatch execution\n *\n * This structure defines the profiling buffer used to measure cmdbatch\n * execution time\n */\nstruct kgsl_cmdbatch_profiling_buffer {\n\tuint64_t wall_clock_s;\n\tuint64_t wall_clock_ns;\n\tuint64_t gpu_ticks_queued;\n\tuint64_t gpu_ticks_submitted;\n\tuint64_t gpu_ticks_retired;\n};\n\n/* ioctls */\n#define KGSL_IOC_TYPE 0x09\n\n/* get misc info about the GPU\n   type should be a value from enum kgsl_property_type\n   value points to a structure that varies based on type\n   sizebytes is sizeof() that structure\n   for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo\n   this structure contaings hardware versioning info.\n   for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop\n   this is used to find mmap() offset and sizes for mapping\n   struct kgsl_memstore into userspace.\n*/\nstruct kgsl_device_getproperty {\n\tunsigned int type;\n\tvoid __user *value;\n\tsize_t sizebytes;\n};\n\n#define IOCTL_KGSL_DEVICE_GETPROPERTY \\\n\t_IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)\n\n/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012\n */\n\n/* block until the GPU has executed past a given timestamp\n * timeout is in milliseconds.\n */\nstruct kgsl_device_waittimestamp {\n\tunsigned int timestamp;\n\tunsigned int timeout;\n};\n\n#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \\\n\t_IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)\n\nstruct kgsl_device_waittimestamp_ctxtid {\n\tunsigned int context_id;\n\tunsigned int timestamp;\n\tunsigned int timeout;\n};\n\n#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \\\n\t_IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid)\n\n/* DEPRECATED: issue indirect commands to the GPU.\n * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE\n * ibaddr and sizedwords must specify a subset of a buffer created\n * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM\n * flags may be a mask of KGSL_CONTEXT_ values\n * timestamp is a returned counter value which can be passed to\n * other ioctls to determine when the commands have been executed by\n * the GPU.\n *\n * This fucntion is deprecated - consider using IOCTL_KGSL_SUBMIT_COMMANDS\n * instead\n */\nstruct kgsl_ringbuffer_issueibcmds {\n\tunsigned int drawctxt_id;\n\tunsigned long ibdesc_addr;\n\tunsigned int numibs;\n\tunsigned int timestamp; /*output param */\n\tunsigned int flags;\n};\n\n#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \\\n\t_IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)\n\n/* read the most recently executed timestamp value\n * type should be a value from enum kgsl_timestamp_type\n */\nstruct kgsl_cmdstream_readtimestamp {\n\tunsigned int type;\n\tunsigned int timestamp; /*output param */\n};\n\n#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \\\n\t_IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)\n\n#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \\\n\t_IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)\n\n/* free memory when the GPU reaches a given timestamp.\n * gpuaddr specify a memory region created by a\n * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call\n * type should be a value from enum kgsl_timestamp_type\n */\nstruct kgsl_cmdstream_freememontimestamp {\n\tunsigned long gpuaddr;\n\tunsigned int type;\n\tunsigned int timestamp;\n};\n\n#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \\\n\t_IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)\n\n/* Previous versions of this header had incorrectly defined\n   IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead\n   of a write only ioctl.  To ensure binary compatability, the following\n   #define will be used to intercept the incorrect ioctl\n*/\n\n#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \\\n\t_IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)\n\n/* create a draw context, which is used to preserve GPU state.\n * The flags field may contain a mask KGSL_CONTEXT_*  values\n */\nstruct kgsl_drawctxt_create {\n\tunsigned int flags;\n\tunsigned int drawctxt_id; /*output param */\n};\n\n#define IOCTL_KGSL_DRAWCTXT_CREATE \\\n\t_IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)\n\n/* destroy a draw context */\nstruct kgsl_drawctxt_destroy {\n\tunsigned int drawctxt_id;\n};\n\n#define IOCTL_KGSL_DRAWCTXT_DESTROY \\\n\t_IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)\n\n/* add a block of pmem, fb, ashmem or user allocated address\n * into the GPU address space */\nstruct kgsl_map_user_mem {\n\tint fd;\n\tunsigned long gpuaddr;   /*output param */\n\tsize_t len;\n\tsize_t offset;\n\tunsigned long hostptr;   /*input param */\n\tenum kgsl_user_mem_type memtype;\n\tunsigned int flags;\n};\n\n#define IOCTL_KGSL_MAP_USER_MEM \\\n\t_IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem)\n\nstruct kgsl_cmdstream_readtimestamp_ctxtid {\n\tunsigned int context_id;\n\tunsigned int type;\n\tunsigned int timestamp; /*output param */\n};\n\n#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \\\n\t_IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid)\n\nstruct kgsl_cmdstream_freememontimestamp_ctxtid {\n\tunsigned int context_id;\n\tunsigned long gpuaddr;\n\tunsigned int type;\n\tunsigned int timestamp;\n};\n\n#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \\\n\t_IOW(KGSL_IOC_TYPE, 0x17, \\\n\tstruct kgsl_cmdstream_freememontimestamp_ctxtid)\n\n/* add a block of pmem or fb into the GPU address space */\nstruct kgsl_sharedmem_from_pmem {\n        int pmem_fd;\n        unsigned long gpuaddr;  /*output param */\n        unsigned int len;\n        unsigned int offset;\n};\n\n#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \\\n        _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem)\n\n/* remove memory from the GPU's address space */\nstruct kgsl_sharedmem_free {\n\tunsigned long gpuaddr;\n};\n\n#define IOCTL_KGSL_SHAREDMEM_FREE \\\n\t_IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)\n\nstruct kgsl_cff_user_event {\n\tunsigned char cff_opcode;\n\tunsigned int op1;\n\tunsigned int op2;\n\tunsigned int op3;\n\tunsigned int op4;\n\tunsigned int op5;\n\tunsigned int __pad[2];\n};\n\n#define IOCTL_KGSL_CFF_USER_EVENT \\\n\t_IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event)\n\nstruct kgsl_gmem_desc {\n\tunsigned int x;\n\tunsigned int y;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int pitch;\n};\n\nstruct kgsl_buffer_desc {\n\tvoid \t\t\t*hostptr;\n\tunsigned long\tgpuaddr;\n\tint\t\t\t\tsize;\n\tunsigned int\tformat;\n\tunsigned int  \tpitch;\n\tunsigned int  \tenabled;\n};\n\nstruct kgsl_bind_gmem_shadow {\n\tunsigned int drawctxt_id;\n\tstruct kgsl_gmem_desc gmem_desc;\n\tunsigned int shadow_x;\n\tunsigned int shadow_y;\n\tstruct kgsl_buffer_desc shadow_buffer;\n\tunsigned int buffer_id;\n};\n\n#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \\\n    _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)\n\n/* add a block of memory into the GPU address space */\n\n/*\n * IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC deprecated 09/2012\n * use IOCTL_KGSL_GPUMEM_ALLOC instead\n */\n\nstruct kgsl_sharedmem_from_vmalloc {\n\tunsigned long gpuaddr;\t/*output param */\n\tunsigned int hostptr;\n\tunsigned int flags;\n};\n\n#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \\\n\t_IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)\n\n/*\n * This is being deprecated in favor of IOCTL_KGSL_GPUMEM_CACHE_SYNC which\n * supports both directions (flush and invalidate). This code will still\n * work, but by definition it will do a flush of the cache which might not be\n * what you want to have happen on a buffer following a GPU operation.  It is\n * safer to go with IOCTL_KGSL_GPUMEM_CACHE_SYNC\n */\n\n#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \\\n\t_IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)\n\nstruct kgsl_drawctxt_set_bin_base_offset {\n\tunsigned int drawctxt_id;\n\tunsigned int offset;\n};\n\n#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \\\n\t_IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)\n\nenum kgsl_cmdwindow_type {\n\tKGSL_CMDWINDOW_MIN     = 0x00000000,\n\tKGSL_CMDWINDOW_2D      = 0x00000000,\n\tKGSL_CMDWINDOW_3D      = 0x00000001, /* legacy */\n\tKGSL_CMDWINDOW_MMU     = 0x00000002,\n\tKGSL_CMDWINDOW_ARBITER = 0x000000FF,\n\tKGSL_CMDWINDOW_MAX     = 0x000000FF,\n};\n\n/* write to the command window */\nstruct kgsl_cmdwindow_write {\n\tenum kgsl_cmdwindow_type target;\n\tunsigned int addr;\n\tunsigned int data;\n};\n\n#define IOCTL_KGSL_CMDWINDOW_WRITE \\\n\t_IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)\n\nstruct kgsl_gpumem_alloc {\n\tunsigned long gpuaddr; /* output param */\n\tsize_t size;\n\tunsigned int flags;\n};\n\n#define IOCTL_KGSL_GPUMEM_ALLOC \\\n\t_IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc)\n\nstruct kgsl_cff_syncmem {\n\tunsigned long gpuaddr;\n\tsize_t len;\n\tunsigned int __pad[2]; /* For future binary compatibility */\n};\n\n#define IOCTL_KGSL_CFF_SYNCMEM \\\n\t_IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem)\n\n/*\n * A timestamp event allows the user space to register an action following an\n * expired timestamp. Note IOCTL_KGSL_TIMESTAMP_EVENT has been redefined to\n * _IOWR to support fences which need to return a fd for the priv parameter.\n */\n\nstruct kgsl_timestamp_event {\n\tint type;                /* Type of event (see list below) */\n\tunsigned int timestamp;  /* Timestamp to trigger event on */\n\tunsigned int context_id; /* Context for the timestamp */\n\tvoid __user *priv;\t /* Pointer to the event specific blob */\n\tsize_t len;              /* Size of the event specific blob */\n};\n\n#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD \\\n\t_IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event)\n\n/* A genlock timestamp event releases an existing lock on timestamp expire */\n\n#define KGSL_TIMESTAMP_EVENT_GENLOCK 1\n\nstruct kgsl_timestamp_event_genlock {\n\tint handle; /* Handle of the genlock lock to release */\n};\n\n/* A fence timestamp event releases an existing lock on timestamp expire */\n\n#define KGSL_TIMESTAMP_EVENT_FENCE 2\n\nstruct kgsl_timestamp_event_fence {\n\tint fence_fd; /* Fence to signal */\n};\n\n/*\n * Set a property within the kernel.  Uses the same structure as\n * IOCTL_KGSL_GETPROPERTY\n */\n\n#define IOCTL_KGSL_SETPROPERTY \\\n\t_IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty)\n\n#define IOCTL_KGSL_TIMESTAMP_EVENT \\\n\t_IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event)\n\n/**\n * struct kgsl_gpumem_alloc_id - argument to IOCTL_KGSL_GPUMEM_ALLOC_ID\n * @id: returned id value for this allocation.\n * @flags: mask of KGSL_MEM* values requested and actual flags on return.\n * @size: requested size of the allocation and actual size on return.\n * @mmapsize: returned size to pass to mmap() which may be larger than 'size'\n * @gpuaddr: returned GPU address for the allocation\n *\n * Allocate memory for access by the GPU. The flags and size fields are echoed\n * back by the kernel, so that the caller can know if the request was\n * adjusted.\n *\n * Supported flags:\n * KGSL_MEMFLAGS_GPUREADONLY: the GPU will be unable to write to the buffer\n * KGSL_MEMTYPE*: usage hint for debugging aid\n * KGSL_MEMALIGN*: alignment hint, may be ignored or adjusted by the kernel.\n * KGSL_MEMFLAGS_USE_CPU_MAP: If set on call and return, the returned GPU\n * address will be 0. Calling mmap() will set the GPU address.\n */\nstruct kgsl_gpumem_alloc_id {\n\tunsigned int id;\n\tunsigned int flags;\n\tsize_t size;\n\tsize_t mmapsize;\n\tunsigned long gpuaddr;\n/* private: reserved for future use*/\n\tunsigned long __pad[2];\n};\n\n#define IOCTL_KGSL_GPUMEM_ALLOC_ID \\\n\t_IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id)\n\n/**\n * struct kgsl_gpumem_free_id - argument to IOCTL_KGSL_GPUMEM_FREE_ID\n * @id: GPU allocation id to free\n *\n * Free an allocation by id, in case a GPU address has not been assigned or\n * is unknown. Freeing an allocation by id with this ioctl or by GPU address\n * with IOCTL_KGSL_SHAREDMEM_FREE are equivalent.\n */\nstruct kgsl_gpumem_free_id {\n\tunsigned int id;\n/* private: reserved for future use*/\n\tunsigned int __pad;\n};\n\n#define IOCTL_KGSL_GPUMEM_FREE_ID \\\n\t_IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id)\n\n/**\n * struct kgsl_gpumem_get_info - argument to IOCTL_KGSL_GPUMEM_GET_INFO\n * @gpuaddr: GPU address to query. Also set on return.\n * @id: GPU allocation id to query. Also set on return.\n * @flags: returned mask of KGSL_MEM* values.\n * @size: returned size of the allocation.\n * @mmapsize: returned size to pass mmap(), which may be larger than 'size'\n * @useraddr: returned address of the userspace mapping for this buffer\n *\n * This ioctl allows querying of all user visible attributes of an existing\n * allocation, by either the GPU address or the id returned by a previous\n * call to IOCTL_KGSL_GPUMEM_ALLOC_ID. Legacy allocation ioctls may not\n * return all attributes so this ioctl can be used to look them up if needed.\n *\n */\nstruct kgsl_gpumem_get_info {\n\tunsigned long gpuaddr;\n\tunsigned int id;\n\tunsigned int flags;\n\tsize_t size;\n\tsize_t mmapsize;\n\tunsigned long useraddr;\n/* private: reserved for future use*/\n\tunsigned long __pad[4];\n};\n\n#define IOCTL_KGSL_GPUMEM_GET_INFO\\\n\t_IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info)\n\n/**\n * struct kgsl_gpumem_sync_cache - argument to IOCTL_KGSL_GPUMEM_SYNC_CACHE\n * @gpuaddr: GPU address of the buffer to sync.\n * @id: id of the buffer to sync. Either gpuaddr or id is sufficient.\n * @op: a mask of KGSL_GPUMEM_CACHE_* values\n * @offset: offset into the buffer\n * @length: number of bytes starting from offset to perform\n * the cache operation on\n *\n * Sync the L2 cache for memory headed to and from the GPU - this replaces\n * KGSL_SHAREDMEM_FLUSH_CACHE since it can handle cache management for both\n * directions\n *\n */\nstruct kgsl_gpumem_sync_cache {\n\tunsigned long gpuaddr;\n\tunsigned int id;\n\tunsigned int op;\n\tsize_t offset;\n\tsize_t length;\n};\n\n#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0)\n#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN\n\n#define KGSL_GPUMEM_CACHE_INV (1 << 1)\n#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV\n\n#define KGSL_GPUMEM_CACHE_FLUSH \\\n\t(KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV)\n\n/* Flag to ensure backwards compatibility of kgsl_gpumem_sync_cache struct */\n#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U)\n\n#define IOCTL_KGSL_GPUMEM_SYNC_CACHE \\\n\t_IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache)\n\n/**\n * struct kgsl_perfcounter_get - argument to IOCTL_KGSL_PERFCOUNTER_GET\n * @groupid: Performance counter group ID\n * @countable: Countable to select within the group\n * @offset: Return offset of the reserved LO counter\n * @offset_hi: Return offset of the reserved HI counter\n *\n * Get an available performance counter from a specified groupid.  The offset\n * of the performance counter will be returned after successfully assigning\n * the countable to the counter for the specified group.  An error will be\n * returned and an offset of 0 if the groupid is invalid or there are no\n * more counters left.  After successfully getting a perfcounter, the user\n * must call kgsl_perfcounter_put(groupid, contable) when finished with\n * the perfcounter to clear up perfcounter resources.\n *\n */\nstruct kgsl_perfcounter_get {\n\tunsigned int groupid;\n\tunsigned int countable;\n\tunsigned int offset;\n\tunsigned int offset_hi;\n/* private: reserved for future use */\n\tunsigned int __pad; /* For future binary compatibility */\n};\n\n#define IOCTL_KGSL_PERFCOUNTER_GET \\\n\t_IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get)\n\n/**\n * struct kgsl_perfcounter_put - argument to IOCTL_KGSL_PERFCOUNTER_PUT\n * @groupid: Performance counter group ID\n * @countable: Countable to release within the group\n *\n * Put an allocated performance counter to allow others to have access to the\n * resource that was previously taken.  This is only to be called after\n * successfully getting a performance counter from kgsl_perfcounter_get().\n *\n */\nstruct kgsl_perfcounter_put {\n\tunsigned int groupid;\n\tunsigned int countable;\n/* private: reserved for future use */\n\tunsigned int __pad[2]; /* For future binary compatibility */\n};\n\n#define IOCTL_KGSL_PERFCOUNTER_PUT \\\n\t_IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put)\n\n/**\n * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY\n * @groupid: Performance counter group ID\n * @countable: Return active countables array\n * @size: Size of active countables array\n * @max_counters: Return total number counters for the group ID\n *\n * Query the available performance counters given a groupid.  The array\n * *countables is used to return the current active countables in counters.\n * The size of the array is passed in so the kernel will only write at most\n * size or counter->size for the group id.  The total number of available\n * counters for the group ID is returned in max_counters.\n * If the array or size passed in are invalid, then only the maximum number\n * of counters will be returned, no data will be written to *countables.\n * If the groupid is invalid an error code will be returned.\n *\n */\nstruct kgsl_perfcounter_query {\n\tunsigned int groupid;\n\t/* Array to return the current countable for up to size counters */\n\tunsigned int __user *countables;\n\tunsigned int count;\n\tunsigned int max_counters;\n/* private: reserved for future use */\n\tunsigned int __pad[2]; /* For future binary compatibility */\n};\n\n#define IOCTL_KGSL_PERFCOUNTER_QUERY \\\n\t_IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query)\n\n/**\n * struct kgsl_perfcounter_query - argument to IOCTL_KGSL_PERFCOUNTER_QUERY\n * @groupid: Performance counter group IDs\n * @countable: Performance counter countable IDs\n * @value: Return performance counter reads\n * @size: Size of all arrays (groupid/countable pair and return value)\n *\n * Read in the current value of a performance counter given by the groupid\n * and countable.\n *\n */\n\nstruct kgsl_perfcounter_read_group {\n\tunsigned int groupid;\n\tunsigned int countable;\n\tunsigned long long value;\n};\n\nstruct kgsl_perfcounter_read {\n\tstruct kgsl_perfcounter_read_group __user *reads;\n\tunsigned int count;\n/* private: reserved for future use */\n\tunsigned int __pad[2]; /* For future binary compatibility */\n};\n\n#define IOCTL_KGSL_PERFCOUNTER_READ \\\n\t_IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read)\n/*\n * struct kgsl_gpumem_sync_cache_bulk - argument to\n * IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK\n * @id_list: list of GPU buffer ids of the buffers to sync\n * @count: number of GPU buffer ids in id_list\n * @op: a mask of KGSL_GPUMEM_CACHE_* values\n *\n * Sync the cache for memory headed to and from the GPU. Certain\n * optimizations can be made on the cache operation based on the total\n * size of the working set of memory to be managed.\n */\nstruct kgsl_gpumem_sync_cache_bulk {\n\tunsigned int __user *id_list;\n\tunsigned int count;\n\tunsigned int op;\n/* private: reserved for future use */\n\tunsigned int __pad[2]; /* For future binary compatibility */\n};\n\n#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK \\\n\t_IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk)\n\n/*\n * struct kgsl_cmd_syncpoint_timestamp\n * @context_id: ID of a KGSL context\n * @timestamp: GPU timestamp\n *\n * This structure defines a syncpoint comprising a context/timestamp pair. A\n * list of these may be passed by IOCTL_KGSL_SUBMIT_COMMANDS to define\n * dependencies that must be met before the command can be submitted to the\n * hardware\n */\nstruct kgsl_cmd_syncpoint_timestamp {\n\tunsigned int context_id;\n\tunsigned int timestamp;\n};\n\nstruct kgsl_cmd_syncpoint_fence {\n\tint fd;\n};\n\n/**\n * struct kgsl_cmd_syncpoint - Define a sync point for a command batch\n * @type: type of sync point defined here\n * @priv: Pointer to the type specific buffer\n * @size: Size of the type specific buffer\n *\n * This structure contains pointers defining a specific command sync point.\n * The pointer and size should point to a type appropriate structure.\n */\nstruct kgsl_cmd_syncpoint {\n\tint type;\n\tvoid __user *priv;\n\tsize_t size;\n};\n\n/* Flag to indicate that the cmdlist may contain memlists */\n#define KGSL_IBDESC_MEMLIST 0x1\n\n/* Flag to point out the cmdbatch profiling buffer in the memlist */\n#define KGSL_IBDESC_PROFILING_BUFFER 0x2\n\n/**\n * struct kgsl_submit_commands - Argument to IOCTL_KGSL_SUBMIT_COMMANDS\n * @context_id: KGSL context ID that owns the commands\n * @flags:\n * @cmdlist: User pointer to a list of kgsl_ibdesc structures\n * @numcmds: Number of commands listed in cmdlist\n * @synclist: User pointer to a list of kgsl_cmd_syncpoint structures\n * @numsyncs: Number of sync points listed in synclist\n * @timestamp: On entry the a user defined timestamp, on exist the timestamp\n * assigned to the command batch\n *\n * This structure specifies a command to send to the GPU hardware.  This is\n * similar to kgsl_issueibcmds expect that it doesn't support the legacy way to\n * submit IB lists and it adds sync points to block the IB until the\n * dependencies are satisified.  This entry point is the new and preferred way\n * to submit commands to the GPU. The memory list can be used to specify all\n * memory that is referrenced in the current set of commands.\n */\n\nstruct kgsl_submit_commands {\n\tunsigned int context_id;\n\tunsigned int flags;\n\tstruct kgsl_ibdesc __user *cmdlist;\n\tunsigned int numcmds;\n\tstruct kgsl_cmd_syncpoint __user *synclist;\n\tunsigned int numsyncs;\n\tunsigned int timestamp;\n/* private: reserved for future use */\n\tunsigned int __pad[4];\n};\n\n#define IOCTL_KGSL_SUBMIT_COMMANDS \\\n\t_IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands)\n\n/**\n * struct kgsl_device_constraint - device constraint argument\n * @context_id: KGSL context ID\n * @type: type of constraint i.e pwrlevel/none\n * @data: constraint data\n * @size: size of the constraint data\n */\nstruct kgsl_device_constraint {\n\tunsigned int type;\n\tunsigned int context_id;\n\tvoid __user *data;\n\tsize_t size;\n};\n\n/* Constraint Type*/\n#define KGSL_CONSTRAINT_NONE 0\n#define KGSL_CONSTRAINT_PWRLEVEL 1\n\n/* PWRLEVEL constraint level*/\n/* set to min frequency */\n#define KGSL_CONSTRAINT_PWR_MIN    0\n/* set to max frequency */\n#define KGSL_CONSTRAINT_PWR_MAX    1\n\nstruct kgsl_device_constraint_pwrlevel {\n\tunsigned int level;\n};\n\n/**\n * struct kgsl_syncsource_create - Argument to IOCTL_KGSL_SYNCSOURCE_CREATE\n * @id: returned id for the syncsource that was created.\n *\n * This ioctl creates a userspace sync timeline.\n */\n\nstruct kgsl_syncsource_create {\n\tunsigned int id;\n/* private: reserved for future use */\n\tunsigned int __pad[3];\n};\n\n#define IOCTL_KGSL_SYNCSOURCE_CREATE \\\n\t_IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create)\n\n/**\n * struct kgsl_syncsource_destroy - Argument to IOCTL_KGSL_SYNCSOURCE_DESTROY\n * @id: syncsource id to destroy\n *\n * This ioctl creates a userspace sync timeline.\n */\n\nstruct kgsl_syncsource_destroy {\n\tunsigned int id;\n/* private: reserved for future use */\n\tunsigned int __pad[3];\n};\n\n#define IOCTL_KGSL_SYNCSOURCE_DESTROY \\\n\t_IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy)\n\n/**\n * struct kgsl_syncsource_create_fence - Argument to\n *     IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE\n * @id: syncsource id\n * @fence_fd: returned sync_fence fd\n *\n * Create a fence that may be signaled by userspace by calling\n * IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE. There are no order dependencies between\n * these fences.\n */\nstruct kgsl_syncsource_create_fence {\n\tunsigned int id;\n\tint fence_fd;\n/* private: reserved for future use */\n\tunsigned int __pad[4];\n};\n\n/**\n * struct kgsl_syncsource_signal_fence - Argument to\n *     IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE\n * @id: syncsource id\n * @fence_fd: sync_fence fd to signal\n *\n * Signal a fence that was created by a IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE\n * call using the same syncsource id. This allows a fence to be shared\n * to other processes but only signaled by the process owning the fd\n * used to create the fence.\n */\n#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE \\\n\t_IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence)\n\nstruct kgsl_syncsource_signal_fence {\n\tunsigned int id;\n\tint fence_fd;\n/* private: reserved for future use */\n\tunsigned int __pad[4];\n};\n\n#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE \\\n\t_IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence)\n\n/**\n * struct kgsl_cff_sync_gpuobj - Argument to IOCTL_KGSL_CFF_SYNC_GPUOBJ\n * @offset: Offset into the GPU object to sync\n * @length: Number of bytes to sync\n * @id: ID of the GPU object to sync\n */\nstruct kgsl_cff_sync_gpuobj {\n\tuint64_t offset;\n\tuint64_t length;\n\tunsigned int id;\n};\n\n#define IOCTL_KGSL_CFF_SYNC_GPUOBJ \\\n\t_IOW(KGSL_IOC_TYPE, 0x44, struct kgsl_cff_sync_gpuobj)\n\n/**\n * struct kgsl_gpuobj_alloc - Argument to IOCTL_KGSL_GPUOBJ_ALLOC\n * @size: Size in bytes of the object to allocate\n * @flags: mask of KGSL_MEMFLAG_* bits\n * @va_len: Size in bytes of the virtual region to allocate\n * @mmapsize: Returns the mmap() size of the object\n * @id: Returns the GPU object ID of the new object\n * @metadata_len: Length of the metdata to copy from the user\n * @metadata: Pointer to the user specified metadata to store for the object\n */\nstruct kgsl_gpuobj_alloc {\n\tuint64_t size;\n\tuint64_t flags;\n\tuint64_t va_len;\n\tuint64_t mmapsize;\n\tunsigned int id;\n\tunsigned int metadata_len;\n\tuint64_t metadata;\n};\n\n/* Let the user know that this header supports the gpuobj metadata */\n#define KGSL_GPUOBJ_ALLOC_METADATA_MAX 64\n\n#define IOCTL_KGSL_GPUOBJ_ALLOC \\\n\t_IOWR(KGSL_IOC_TYPE, 0x45, struct kgsl_gpuobj_alloc)\n\n/**\n * struct kgsl_gpuobj_free - Argument to IOCTL_KGLS_GPUOBJ_FREE\n * @flags: Mask of: KGSL_GUPOBJ_FREE_ON_EVENT\n * @priv: Pointer to the private object if KGSL_GPUOBJ_FREE_ON_EVENT is\n * specified\n * @id: ID of the GPU object to free\n * @type: If KGSL_GPUOBJ_FREE_ON_EVENT is specified, the type of asynchronous\n * event to free on\n * @len: Length of the data passed in priv\n */\nstruct kgsl_gpuobj_free {\n\tuint64_t flags;\n\tuint64_t __user priv;\n\tunsigned int id;\n\tunsigned int type;\n\tunsigned int len;\n};\n\n#define KGSL_GPUOBJ_FREE_ON_EVENT 1\n\n#define KGSL_GPU_EVENT_TIMESTAMP 1\n#define KGSL_GPU_EVENT_FENCE     2\n\n/**\n * struct kgsl_gpu_event_timestamp - Specifies a timestamp event to free a GPU\n * object on\n * @context_id: ID of the timestamp event to wait for\n * @timestamp: Timestamp of the timestamp event to wait for\n */\nstruct kgsl_gpu_event_timestamp {\n\tunsigned int context_id;\n\tunsigned int timestamp;\n};\n\n/**\n * struct kgsl_gpu_event_fence - Specifies a fence ID to to free a GPU object on\n * @fd: File descriptor for the fence\n */\nstruct kgsl_gpu_event_fence {\n\tint fd;\n};\n\n#define IOCTL_KGSL_GPUOBJ_FREE \\\n\t_IOW(KGSL_IOC_TYPE, 0x46, struct kgsl_gpuobj_free)\n\n/**\n * struct kgsl_gpuobj_info - argument to IOCTL_KGSL_GPUOBJ_INFO\n * @gpuaddr: GPU address of the object\n * @flags: Current flags for the object\n * @size: Size of the object\n * @va_len: VA size of the object\n * @va_addr: Virtual address of the object (if it is mapped)\n * id - GPU object ID of the object to query\n */\nstruct kgsl_gpuobj_info {\n\tuint64_t gpuaddr;\n\tuint64_t flags;\n\tuint64_t size;\n\tuint64_t va_len;\n\tuint64_t va_addr;\n\tunsigned int id;\n};\n\n#define IOCTL_KGSL_GPUOBJ_INFO \\\n\t_IOWR(KGSL_IOC_TYPE, 0x47, struct kgsl_gpuobj_info)\n\n/**\n * struct kgsl_gpuobj_import - argument to IOCTL_KGSL_GPUOBJ_IMPORT\n * @priv: Pointer to the private data for the import type\n * @priv_len: Length of the private data\n * @flags: Mask of KGSL_MEMFLAG_ flags\n * @type: Type of the import (KGSL_USER_MEM_TYPE_*)\n * @id: Returns the ID of the new GPU object\n */\nstruct kgsl_gpuobj_import {\n\tuint64_t __user priv;\n\tuint64_t priv_len;\n\tuint64_t flags;\n\tunsigned int type;\n\tunsigned int id;\n};\n\n/**\n * struct kgsl_gpuobj_import_dma_buf - import a dmabuf object\n * @fd: File descriptor for the dma-buf object\n */\nstruct kgsl_gpuobj_import_dma_buf {\n\tint fd;\n};\n\n/**\n * struct kgsl_gpuobj_import_useraddr - import an object based on a useraddr\n * @virtaddr: Virtual address of the object to import\n */\nstruct kgsl_gpuobj_import_useraddr {\n\tuint64_t virtaddr;\n};\n\n#define IOCTL_KGSL_GPUOBJ_IMPORT \\\n\t_IOWR(KGSL_IOC_TYPE, 0x48, struct kgsl_gpuobj_import)\n\n/**\n * struct kgsl_gpuobj_sync_obj - Individual GPU object to sync\n * @offset: Offset within the GPU object to sync\n * @length: Number of bytes to sync\n * @id: ID of the GPU object to sync\n * @op: Cache operation to execute\n */\n\nstruct kgsl_gpuobj_sync_obj {\n\tuint64_t offset;\n\tuint64_t length;\n\tunsigned int id;\n\tunsigned int op;\n};\n\n/**\n * struct kgsl_gpuobj_sync - Argument for IOCTL_KGSL_GPUOBJ_SYNC\n * @objs: Pointer to an array of kgsl_gpuobj_sync_obj structs\n * @obj_len: Size of each item in the array\n * @count: Number of items in the array\n */\n\nstruct kgsl_gpuobj_sync {\n\tuint64_t __user objs;\n\tunsigned int obj_len;\n\tunsigned int count;\n};\n\n#define IOCTL_KGSL_GPUOBJ_SYNC \\\n\t_IOW(KGSL_IOC_TYPE, 0x49, struct kgsl_gpuobj_sync)\n\n/**\n * struct kgsl_command_object - GPU command object\n * @offset: GPU address offset of the object\n * @gpuaddr: GPU address of the object\n * @size: Size of the object\n * @flags: Current flags for the object\n * @id - GPU command object ID\n */\nstruct kgsl_command_object {\n\tuint64_t offset;\n\tuint64_t gpuaddr;\n\tuint64_t size;\n\tunsigned int flags;\n\tunsigned int id;\n};\n\n/**\n * struct kgsl_command_syncpoint - GPU syncpoint object\n * @priv: Pointer to the type specific buffer\n * @size: Size of the type specific buffer\n * @type: type of sync point defined here\n */\nstruct kgsl_command_syncpoint {\n\tuint64_t __user priv;\n\tuint64_t size;\n\tunsigned int type;\n};\n\n/**\n * struct kgsl_command_object - Argument for IOCTL_KGSL_GPU_COMMAND\n * @flags: Current flags for the object\n * @cmdlist: List of kgsl_command_objects for submission\n * @cmd_size: Size of kgsl_command_objects structure\n * @numcmds: Number of kgsl_command_objects in command list\n * @objlist: List of kgsl_command_objects for tracking\n * @obj_size: Size of kgsl_command_objects structure\n * @numobjs: Number of kgsl_command_objects in object list\n * @synclist: List of kgsl_command_syncpoints\n * @sync_size: Size of kgsl_command_syncpoint structure\n * @numsyncs: Number of kgsl_command_syncpoints in syncpoint list\n * @context_id: Context ID submittin ghte kgsl_gpu_command\n * @timestamp: Timestamp for the submitted commands\n */\nstruct kgsl_gpu_command {\n\tuint64_t flags;\n\tuint64_t __user cmdlist;\n\tunsigned int cmdsize;\n\tunsigned int numcmds;\n\tuint64_t __user objlist;\n\tunsigned int objsize;\n\tunsigned int numobjs;\n\tuint64_t __user synclist;\n\tunsigned int syncsize;\n\tunsigned int numsyncs;\n\tunsigned int context_id;\n\tunsigned int timestamp;\n};\n\n#define IOCTL_KGSL_GPU_COMMAND \\\n\t_IOWR(KGSL_IOC_TYPE, 0x4A, struct kgsl_gpu_command)\n\n/**\n * struct kgsl_preemption_counters_query - argument to\n * IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY\n * @counters: Return preemption counters array\n * @size_user: Size allocated by userspace\n * @size_priority_level: Size of preemption counters for each\n * priority level\n * @max_priority_level: Return max number of priority levels\n *\n * Query the available preemption counters. The array counters\n * is used to return preemption counters. The size of the array\n * is passed in so the kernel will only write at most size_user\n * or max available preemption counters.  The total number of\n * preemption counters is returned in max_priority_level. If the\n * array or size passed in are invalid, then an error is\n * returned back.\n */\nstruct kgsl_preemption_counters_query {\n\tuint64_t __user counters;\n\tunsigned int size_user;\n\tunsigned int size_priority_level;\n\tunsigned int max_priority_level;\n};\n\n#define IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY \\\n\t_IOWR(KGSL_IOC_TYPE, 0x4B, struct kgsl_preemption_counters_query)\n\n/**\n * struct kgsl_gpuobj_set_info - argument for IOCTL_KGSL_GPUOBJ_SET_INFO\n * @flags: Flags to indicate which paramaters to change\n * @metadata:  If KGSL_GPUOBJ_SET_INFO_METADATA is set, a pointer to the new\n * metadata\n * @id: GPU memory object ID to change\n * @metadata_len:  If KGSL_GPUOBJ_SET_INFO_METADATA is set, the length of the\n * new metadata string\n * @type: If KGSL_GPUOBJ_SET_INFO_TYPE is set, the new type of the memory object\n */\n\n#define KGSL_GPUOBJ_SET_INFO_METADATA (1 << 0)\n#define KGSL_GPUOBJ_SET_INFO_TYPE (1 << 1)\n\nstruct kgsl_gpuobj_set_info {\n\tuint64_t flags;\n\tuint64_t metadata;\n\tunsigned int id;\n\tunsigned int metadata_len;\n\tunsigned int type;\n};\n\n#define IOCTL_KGSL_GPUOBJ_SET_INFO \\\n\t_IOW(KGSL_IOC_TYPE, 0x4C, struct kgsl_gpuobj_set_info)\n\n#endif /* _UAPI_MSM_KGSL_H */\n"
  },
  {
    "path": "selfdrive/modeld/thneed/serialize.cc",
    "content": "#include <cassert>\n#include <set>\n\n#include \"json11.hpp\"\n#include \"selfdrive/modeld/thneed/thneed.h\"\nusing namespace json11;\n\nextern map<cl_program, string> g_program_source;\n\nvoid Thneed::load(const char *filename) {\n  printf(\"Thneed::load: loading from %s\\n\", filename);\n\n  FILE *f = fopen(filename, \"rb\");\n  fseek(f, 0L, SEEK_END);\n  int sz = ftell(f);\n  fseek(f, 0L, SEEK_SET);\n  char *buf = (char*)malloc(sz);\n  fread(buf, 1, sz, f);\n  fclose(f);\n\n  int jsz = *(int *)buf;\n  string jj(buf+4, jsz);\n  string err;\n  Json jdat = Json::parse(jj, err);\n\n  map<cl_mem, cl_mem> real_mem;\n  real_mem[NULL] = NULL;\n\n  int ptr = 4+jsz;\n  for (auto &obj : jdat[\"objects\"].array_items()) {\n    auto mobj = obj.object_items();\n    int sz = mobj[\"size\"].int_value();\n    cl_mem clbuf = NULL;\n\n    if (mobj[\"buffer_id\"].string_value().size() > 0) {\n      // image buffer must already be allocated\n      clbuf = real_mem[*(cl_mem*)(mobj[\"buffer_id\"].string_value().data())];\n      assert(mobj[\"needs_load\"].bool_value() == false);\n    } else {\n      if (mobj[\"needs_load\"].bool_value()) {\n        //printf(\"loading %p %d @ 0x%X\\n\", clbuf, sz, ptr);\n        clbuf = clCreateBuffer(context, CL_MEM_COPY_HOST_PTR | CL_MEM_READ_WRITE, sz, &buf[ptr], NULL);\n        ptr += sz;\n      } else {\n        clbuf = clCreateBuffer(context, CL_MEM_READ_WRITE, sz, NULL, NULL);\n      }\n    }\n    assert(clbuf != NULL);\n\n    if (mobj[\"arg_type\"] == \"image2d_t\" || mobj[\"arg_type\"] == \"image1d_t\") {\n      cl_image_desc desc = {0};\n      desc.image_type = (mobj[\"arg_type\"] == \"image2d_t\") ? CL_MEM_OBJECT_IMAGE2D : CL_MEM_OBJECT_IMAGE1D_BUFFER;\n      desc.image_width = mobj[\"width\"].int_value();\n      desc.image_height = mobj[\"height\"].int_value();\n      desc.image_row_pitch = mobj[\"row_pitch\"].int_value();\n      desc.buffer = clbuf;\n\n      cl_image_format format;\n      format.image_channel_order = CL_RGBA;\n      format.image_channel_data_type = CL_HALF_FLOAT;\n\n      clbuf = clCreateImage(context, CL_MEM_READ_WRITE, &format, &desc, NULL, NULL);\n      assert(clbuf != NULL);\n    }\n\n    real_mem[*(cl_mem*)(mobj[\"id\"].string_value().data())] = clbuf;\n  }\n\n  map<string, cl_program> g_programs;\n  for (auto &obj : jdat[\"programs\"].object_items()) {\n    const char *srcs[1];\n    srcs[0] = (const char *)obj.second.string_value().c_str();\n    size_t length = obj.second.string_value().size();\n\n    if (record & THNEED_DEBUG) printf(\"building %s with size %zu\\n\", obj.first.c_str(), length);\n\n    cl_program program = clCreateProgramWithSource(context, 1, srcs, &length, NULL);\n    int err = clBuildProgram(program, 1, &device_id, \"\", NULL, NULL);\n    if (err != 0) {\n      printf(\"got err %d\\n\", err);\n      size_t length;\n      char buffer[2048];\n      clGetProgramBuildInfo(program, device_id, CL_PROGRAM_BUILD_LOG, sizeof(buffer), buffer, &length);\n      buffer[length] = '\\0';\n      printf(\"%s\\n\", buffer);\n    }\n    assert(err == 0);\n\n    g_programs[obj.first] = program;\n  }\n\n  for (auto &obj : jdat[\"binaries\"].array_items()) {\n    string name = obj[\"name\"].string_value();\n    size_t length = obj[\"length\"].int_value();\n    const unsigned char *srcs[1];\n    srcs[0] = (const unsigned char *)&buf[ptr];\n    ptr += length;\n\n    if (record & THNEED_DEBUG) printf(\"binary %s with size %zu\\n\", name.c_str(), length);\n\n    cl_int err;\n    cl_program program = clCreateProgramWithBinary(context, 1, &device_id, &length, srcs, NULL, &err);\n    assert(program != NULL && err == CL_SUCCESS);\n    err = clBuildProgram(program, 1, &device_id, \"\", NULL, NULL);\n    assert(err == CL_SUCCESS);\n\n    g_programs[name] = program;\n  }\n\n  for (auto &obj : jdat[\"kernels\"].array_items()) {\n    auto gws = obj[\"global_work_size\"];\n    auto lws = obj[\"local_work_size\"];\n    auto kk = shared_ptr<CLQueuedKernel>(new CLQueuedKernel(this));\n\n    kk->name = obj[\"name\"].string_value();\n    kk->program = g_programs[kk->name];\n    kk->work_dim = obj[\"work_dim\"].int_value();\n    for (int i = 0; i < kk->work_dim; i++) {\n      kk->global_work_size[i] = gws[i].int_value();\n      kk->local_work_size[i] = lws[i].int_value();\n    }\n    kk->num_args = obj[\"num_args\"].int_value();\n    for (int i = 0; i < kk->num_args; i++) {\n      string arg = obj[\"args\"].array_items()[i].string_value();\n      int arg_size = obj[\"args_size\"].array_items()[i].int_value();\n      kk->args_size.push_back(arg_size);\n      if (arg_size == 8) {\n        cl_mem val = *(cl_mem*)(arg.data());\n        val = real_mem[val];\n        kk->args.push_back(string((char*)&val, sizeof(val)));\n      } else {\n        kk->args.push_back(arg);\n      }\n    }\n    kq.push_back(kk);\n  }\n\n  free(buf);\n  clFinish(command_queue);\n}\n\nvoid Thneed::save(const char *filename, bool save_binaries) {\n  printf(\"Thneed::save: saving to %s\\n\", filename);\n\n  // get kernels\n  std::vector<Json> kernels;\n  std::set<string> saved_objects;\n  std::vector<Json> objects;\n  std::map<string, string> programs;\n  std::map<string, string> binaries;\n\n  for (auto &k : kq) {\n    kernels.push_back(k->to_json());\n\n    // check args for objects\n    int i = 0;\n    for (auto &a : k->args) {\n      if (a.size() == 8) {\n        if (saved_objects.find(a) == saved_objects.end()) {\n          saved_objects.insert(a);\n          cl_mem val = *(cl_mem*)(a.data());\n          if (val != NULL) {\n            bool needs_load = k->arg_names[i] == \"weights\" || k->arg_names[i] == \"biases\";\n\n            auto jj = Json::object({\n              {\"id\", a},\n              {\"arg_type\", k->arg_types[i]},\n            });\n\n            if (k->arg_types[i] == \"image2d_t\" || k->arg_types[i] == \"image1d_t\") {\n              cl_mem buf;\n              clGetImageInfo(val, CL_IMAGE_BUFFER, sizeof(buf), &buf, NULL);\n              string aa = string((char *)&buf, sizeof(buf));\n              jj[\"buffer_id\"] = aa;\n\n              size_t width, height, row_pitch;\n              clGetImageInfo(val, CL_IMAGE_WIDTH, sizeof(width), &width, NULL);\n              clGetImageInfo(val, CL_IMAGE_HEIGHT, sizeof(height), &height, NULL);\n              clGetImageInfo(val, CL_IMAGE_ROW_PITCH, sizeof(row_pitch), &row_pitch, NULL);\n              jj[\"width\"] = (int)width;\n              jj[\"height\"] = (int)height;\n              jj[\"row_pitch\"] = (int)row_pitch;\n              jj[\"size\"] = (int)(height * row_pitch);\n              jj[\"needs_load\"] = false;\n\n              if (saved_objects.find(aa) == saved_objects.end()) {\n                saved_objects.insert(aa);\n                size_t sz;\n                clGetMemObjectInfo(buf, CL_MEM_SIZE, sizeof(sz), &sz, NULL);\n                // save the buffer\n                objects.push_back(Json::object({\n                  {\"id\", aa},\n                  {\"arg_type\", \"<image buffer>\"},\n                  {\"needs_load\", needs_load},\n                  {\"size\", (int)sz}\n                }));\n                if (needs_load) assert(sz == height * row_pitch);\n              }\n            } else {\n              size_t sz = 0;\n              clGetMemObjectInfo(val, CL_MEM_SIZE, sizeof(sz), &sz, NULL);\n              jj[\"size\"] = (int)sz;\n              jj[\"needs_load\"] = needs_load;\n            }\n\n            objects.push_back(jj);\n          }\n        }\n      }\n      i++;\n    }\n\n    if (save_binaries) {\n      int err;\n      size_t binary_size = 0;\n      err = clGetProgramInfo(k->program, CL_PROGRAM_BINARY_SIZES, sizeof(binary_size), &binary_size, NULL);\n      assert(err == 0);\n      assert(binary_size > 0);\n      string sv(binary_size, '\\x00');\n\n      uint8_t* bufs[1] = { (uint8_t*)sv.data(), };\n      err = clGetProgramInfo(k->program, CL_PROGRAM_BINARIES, sizeof(bufs), &bufs, NULL);\n      assert(err == 0);\n\n      binaries[k->name] = sv;\n    } else {\n      programs[k->name] = g_program_source[k->program];\n    }\n  }\n\n  vector<string> saved_buffers;\n  for (auto &obj : objects) {\n    auto mobj = obj.object_items();\n    cl_mem val = *(cl_mem*)(mobj[\"id\"].string_value().data());\n    int sz = mobj[\"size\"].int_value();\n    if (mobj[\"needs_load\"].bool_value()) {\n      char *buf = (char *)malloc(sz);\n      if (mobj[\"arg_type\"] == \"image2d_t\" || mobj[\"arg_type\"] == \"image1d_t\") {\n        assert(false);\n      } else {\n        // buffers allocated with CL_MEM_HOST_WRITE_ONLY, hence this hack\n        //hexdump((uint32_t*)val, 0x100);\n\n        // the worst hack in thneed, the flags are at 0x14\n        ((uint32_t*)val)[0x14] &= ~CL_MEM_HOST_WRITE_ONLY;\n        cl_int ret = clEnqueueReadBuffer(command_queue, val, CL_TRUE, 0, sz, buf, 0, NULL, NULL);\n        assert(ret == CL_SUCCESS);\n      }\n      //printf(\"saving buffer: %d %p %s\\n\", sz, buf, mobj[\"arg_type\"].string_value().c_str());\n      saved_buffers.push_back(string(buf, sz));\n      free(buf);\n    }\n  }\n\n  std::vector<Json> jbinaries;\n  for (auto &obj : binaries) {\n    jbinaries.push_back(Json::object({{\"name\", obj.first}, {\"length\", (int)obj.second.size()}}));\n    saved_buffers.push_back(obj.second);\n  }\n\n  Json jdat = Json::object({\n    {\"kernels\", kernels},\n    {\"objects\", objects},\n    {\"programs\", programs},\n    {\"binaries\", jbinaries},\n  });\n\n  string str = jdat.dump();\n  int jsz = str.length();\n\n  FILE *f = fopen(filename, \"wb\");\n  fwrite(&jsz, 1, sizeof(jsz), f);\n  fwrite(str.data(), 1, jsz, f);\n  for (auto &s : saved_buffers) {\n    fwrite(s.data(), 1, s.length(), f);\n  }\n  fclose(f);\n}\n\nJson CLQueuedKernel::to_json() const {\n  return Json::object {\n    { \"name\", name },\n    { \"work_dim\", (int)work_dim },\n    { \"global_work_size\", Json::array { (int)global_work_size[0], (int)global_work_size[1], (int)global_work_size[2] } },\n    { \"local_work_size\", Json::array { (int)local_work_size[0], (int)local_work_size[1], (int)local_work_size[2] } },\n    { \"num_args\", (int)num_args },\n    { \"args\", args },\n    { \"args_size\", args_size },\n  };\n}\n\n"
  },
  {
    "path": "selfdrive/modeld/thneed/thneed.cc",
    "content": "#include \"selfdrive/modeld/thneed/thneed.h\"\n\n#include <dlfcn.h>\n#include <sys/mman.h>\n\n#include <cassert>\n#include <cerrno>\n#include <cstring>\n#include <map>\n#include <string>\n\n#include \"selfdrive/common/clutil.h\"\n#include \"selfdrive/common/timing.h\"\n\n//#define RUN_DISASSEMBLER\n//#define RUN_OPTIMIZER\n\nThneed *g_thneed = NULL;\nint g_fd = -1;\nmap<pair<cl_kernel, int>, string> g_args;\nmap<pair<cl_kernel, int>, int> g_args_size;\nmap<cl_program, string> g_program_source;\n\nvoid hexdump(uint32_t *d, int len) {\n  assert((len%4) == 0);\n  printf(\"  dumping %p len 0x%x\\n\", d, len);\n  for (int i = 0; i < len/4; i++) {\n    if (i != 0 && (i%0x10) == 0) printf(\"\\n\");\n    printf(\"%8x \", d[i]);\n  }\n  printf(\"\\n\");\n}\n\n// *********** ioctl interceptor ***********\n\nextern \"C\" {\n\nint (*my_ioctl)(int filedes, unsigned long request, void *argp) = NULL;\n#undef ioctl\nint ioctl(int filedes, unsigned long request, void *argp) {\n  request &= 0xFFFFFFFF;  // needed on QCOM2\n  if (my_ioctl == NULL) my_ioctl = reinterpret_cast<decltype(my_ioctl)>(dlsym(RTLD_NEXT, \"ioctl\"));\n  Thneed *thneed = g_thneed;\n\n  // save the fd\n  if (request == IOCTL_KGSL_GPUOBJ_ALLOC) g_fd = filedes;\n\n  // note that this runs always, even without a thneed object\n  if (request == IOCTL_KGSL_DRAWCTXT_CREATE) {\n    struct kgsl_drawctxt_create *create = (struct kgsl_drawctxt_create *)argp;\n    create->flags &= ~KGSL_CONTEXT_PRIORITY_MASK;\n    create->flags |= 1 << KGSL_CONTEXT_PRIORITY_SHIFT;   // priority from 1-15, 1 is max priority\n    printf(\"IOCTL_KGSL_DRAWCTXT_CREATE: creating context with flags 0x%x\\n\", create->flags);\n  }\n\n  if (thneed != NULL) {\n    if (request == IOCTL_KGSL_GPU_COMMAND) {\n      struct kgsl_gpu_command *cmd = (struct kgsl_gpu_command *)argp;\n      if (thneed->record & THNEED_RECORD) {\n        thneed->timestamp = cmd->timestamp;\n        thneed->context_id = cmd->context_id;\n        thneed->cmds.push_back(unique_ptr<CachedCommand>(new CachedCommand(thneed, cmd)));\n      }\n      if (thneed->record & THNEED_DEBUG) {\n        printf(\"IOCTL_KGSL_GPU_COMMAND(%2zu): flags: 0x%lx    context_id: %u  timestamp: %u  numcmds: %d  numobjs: %d\\n\",\n            thneed->cmds.size(),\n            cmd->flags,\n            cmd->context_id, cmd->timestamp, cmd->numcmds, cmd->numobjs);\n      }\n    } else if (request == IOCTL_KGSL_GPUOBJ_SYNC) {\n      struct kgsl_gpuobj_sync *cmd = (struct kgsl_gpuobj_sync *)argp;\n      struct kgsl_gpuobj_sync_obj *objs = (struct kgsl_gpuobj_sync_obj *)(cmd->objs);\n\n      if (thneed->record & THNEED_DEBUG) {\n        printf(\"IOCTL_KGSL_GPUOBJ_SYNC count:%d \", cmd->count);\n        for (int i = 0; i < cmd->count; i++) {\n          printf(\" -- offset:0x%lx len:0x%lx id:%d op:%d  \", objs[i].offset, objs[i].length, objs[i].id, objs[i].op);\n        }\n        printf(\"\\n\");\n      }\n\n      if (thneed->record & THNEED_RECORD) {\n        thneed->cmds.push_back(unique_ptr<CachedSync>(new\n              CachedSync(thneed, string((char *)objs, sizeof(struct kgsl_gpuobj_sync_obj)*cmd->count))));\n      }\n    } else if (request == IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID) {\n      struct kgsl_device_waittimestamp_ctxtid *cmd = (struct kgsl_device_waittimestamp_ctxtid *)argp;\n      if (thneed->record & THNEED_DEBUG) {\n        printf(\"IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID: context_id: %d  timestamp: %d  timeout: %d\\n\",\n            cmd->context_id, cmd->timestamp, cmd->timeout);\n      }\n    } else if (request == IOCTL_KGSL_SETPROPERTY) {\n      if (thneed->record & THNEED_DEBUG) {\n        struct kgsl_device_getproperty *prop = (struct kgsl_device_getproperty *)argp;\n        printf(\"IOCTL_KGSL_SETPROPERTY: 0x%x sizebytes:%zu\\n\", prop->type, prop->sizebytes);\n        if (thneed->record & THNEED_VERBOSE_DEBUG) {\n          hexdump((uint32_t *)prop->value, prop->sizebytes);\n          if (prop->type == KGSL_PROP_PWR_CONSTRAINT) {\n            struct kgsl_device_constraint *constraint = (struct kgsl_device_constraint *)prop->value;\n            hexdump((uint32_t *)constraint->data, constraint->size);\n          }\n        }\n      }\n    } else if (request == IOCTL_KGSL_DRAWCTXT_CREATE || request == IOCTL_KGSL_DRAWCTXT_DESTROY) {\n      // this happens\n    } else if (request == IOCTL_KGSL_GPUOBJ_ALLOC || request == IOCTL_KGSL_GPUOBJ_FREE) {\n      // this happens\n    } else {\n      if (thneed->record & THNEED_DEBUG) {\n        printf(\"other ioctl %lx\\n\", request);\n      }\n    }\n  }\n\n  int ret = my_ioctl(filedes, request, argp);\n  if (ret != 0) printf(\"ioctl returned %d with errno %d\\n\", ret, errno);\n  return ret;\n}\n\n}\n\n// *********** GPUMalloc ***********\n\nGPUMalloc::GPUMalloc(int size, int fd) {\n  struct kgsl_gpuobj_alloc alloc;\n  memset(&alloc, 0, sizeof(alloc));\n  alloc.size = size;\n  alloc.flags = 0x10000a00;\n  ioctl(fd, IOCTL_KGSL_GPUOBJ_ALLOC, &alloc);\n  void *addr = mmap64(NULL, alloc.mmapsize, 0x3, 0x1, fd, alloc.id*0x1000);\n  assert(addr != MAP_FAILED);\n\n  base = (uint64_t)addr;\n  remaining = size;\n}\n\nGPUMalloc::~GPUMalloc() {\n  // TODO: free the GPU malloced area\n}\n\nvoid *GPUMalloc::alloc(int size) {\n  void *ret = (void*)base;\n  size = (size+0xff) & (~0xFF);\n  assert(size <= remaining);\n  remaining -= size;\n  base += size;\n  return ret;\n}\n\n// *********** CachedSync, at the ioctl layer ***********\n\nvoid CachedSync::exec() {\n  struct kgsl_gpuobj_sync cmd;\n\n  cmd.objs = (uint64_t)data.data();\n  cmd.obj_len = data.length();\n  cmd.count = data.length() / sizeof(struct kgsl_gpuobj_sync_obj);\n\n  int ret = ioctl(thneed->fd, IOCTL_KGSL_GPUOBJ_SYNC, &cmd);\n  assert(ret == 0);\n}\n\n// *********** CachedCommand, at the ioctl layer ***********\n\nCachedCommand::CachedCommand(Thneed *lthneed, struct kgsl_gpu_command *cmd) {\n  thneed = lthneed;\n  assert(cmd->numsyncs == 0);\n\n  memcpy(&cache, cmd, sizeof(cache));\n\n  if (cmd->numcmds > 0) {\n    cmds = make_unique<struct kgsl_command_object[]>(cmd->numcmds);\n    memcpy(cmds.get(), (void *)cmd->cmdlist, sizeof(struct kgsl_command_object)*cmd->numcmds);\n    cache.cmdlist = (uint64_t)cmds.get();\n    for (int i = 0; i < cmd->numcmds; i++) {\n      void *nn = thneed->ram->alloc(cmds[i].size);\n      memcpy(nn, (void*)cmds[i].gpuaddr, cmds[i].size);\n      cmds[i].gpuaddr = (uint64_t)nn;\n    }\n  }\n\n  if (cmd->numobjs > 0) {\n    objs = make_unique<struct kgsl_command_object[]>(cmd->numobjs);\n    memcpy(objs.get(), (void *)cmd->objlist, sizeof(struct kgsl_command_object)*cmd->numobjs);\n    cache.objlist = (uint64_t)objs.get();\n    for (int i = 0; i < cmd->numobjs; i++) {\n      void *nn = thneed->ram->alloc(objs[i].size);\n      memset(nn, 0, objs[i].size);\n      objs[i].gpuaddr = (uint64_t)nn;\n    }\n  }\n\n  kq = thneed->ckq;\n  thneed->ckq.clear();\n}\n\nvoid CachedCommand::exec() {\n  cache.timestamp = ++thneed->timestamp;\n  int ret = ioctl(thneed->fd, IOCTL_KGSL_GPU_COMMAND, &cache);\n\n  if (thneed->record & THNEED_DEBUG) printf(\"CachedCommand::exec got %d\\n\", ret);\n\n  if (thneed->record & THNEED_VERBOSE_DEBUG) {\n    for (auto &it : kq) {\n      it->debug_print(false);\n    }\n    #ifdef RUN_DISASSEMBLER\n      // assuming 2 commands\n      disassemble(0);\n      disassemble(1);\n    #endif\n  }\n\n  assert(ret == 0);\n}\n\n// *********** Thneed ***********\n\nThneed::Thneed(bool do_clinit) {\n  if (do_clinit) clinit();\n  assert(g_fd != -1);\n  fd = g_fd;\n  ram = make_unique<GPUMalloc>(0x80000, fd);\n  record = THNEED_RECORD;\n  timestamp = -1;\n  g_thneed = this;\n}\n\nvoid Thneed::stop() {\n  find_inputs_outputs();\n  printf(\"Thneed::stop: recorded %lu commands\\n\", cmds.size());\n  record = 0;\n}\n\nvoid Thneed::find_inputs_outputs() {\n  cl_int err;\n  if (inputs.size() > 0) return;\n\n  // save the global inputs/outputs\n  for (auto &k : kq) {\n    for (int i = 0; i < k->num_args; i++) {\n      if (k->name == \"zero_pad_image_float\" && k->arg_names[i] == \"input\") {\n        cl_mem aa = *(cl_mem*)(k->args[i].data());\n\n        size_t sz;\n        clGetMemObjectInfo(aa, CL_MEM_SIZE, sizeof(sz), &sz, NULL);\n        input_sizes.push_back(sz);\n\n        void *ret = clEnqueueMapBuffer(command_queue, aa, CL_TRUE, CL_MAP_WRITE, 0, sz, 0, NULL, NULL, &err);\n        assert(err == CL_SUCCESS);\n        inputs.push_back(ret);\n      }\n\n      if (k->name == \"image2d_to_buffer_float\" && k->arg_names[i] == \"output\") {\n        output = *(cl_mem*)(k->args[i].data());\n      }\n    }\n  }\n}\n\nvoid Thneed::copy_inputs(float **finputs) {\n  //cl_int ret;\n  for (int idx = 0; idx < inputs.size(); ++idx) {\n    if (record & THNEED_DEBUG) printf(\"copying %lu -- %p -> %p\\n\", input_sizes[idx], finputs[idx], inputs[idx]);\n    memcpy(inputs[idx], finputs[idx], input_sizes[idx]);\n  }\n}\n\nvoid Thneed::copy_output(float *foutput) {\n  if (output != NULL) {\n    size_t sz;\n    clGetMemObjectInfo(output, CL_MEM_SIZE, sizeof(sz), &sz, NULL);\n    if (record & THNEED_DEBUG) printf(\"copying %lu for output %p -> %p\\n\", sz, output, foutput);\n    clEnqueueReadBuffer(command_queue, output, CL_TRUE, 0, sz, foutput, 0, NULL, NULL);\n  } else {\n    printf(\"CAUTION: model output is NULL, does it have no outputs?\\n\");\n  }\n}\n\nvoid Thneed::wait() {\n  struct kgsl_device_waittimestamp_ctxtid wait;\n  wait.context_id = context_id;\n  wait.timestamp = timestamp;\n  wait.timeout = -1;\n\n  uint64_t tb = nanos_since_boot();\n  int wret = ioctl(fd, IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID, &wait);\n  uint64_t te = nanos_since_boot();\n\n  if (record & THNEED_DEBUG) printf(\"wait %d after %lu us\\n\", wret, (te-tb)/1000);\n}\n\nvoid Thneed::execute(float **finputs, float *foutput, bool slow) {\n  uint64_t tb, te;\n  if (record & THNEED_DEBUG) tb = nanos_since_boot();\n\n  // ****** copy inputs\n  copy_inputs(finputs);\n\n  // ****** set power constraint\n  int ret;\n  struct kgsl_device_constraint_pwrlevel pwrlevel;\n  pwrlevel.level = KGSL_CONSTRAINT_PWR_MAX;\n\n  struct kgsl_device_constraint constraint;\n  constraint.type = KGSL_CONSTRAINT_PWRLEVEL;\n  constraint.context_id = context_id;\n  constraint.data = (void*)&pwrlevel;\n  constraint.size = sizeof(pwrlevel);\n\n  struct kgsl_device_getproperty prop;\n  prop.type = KGSL_PROP_PWR_CONSTRAINT;\n  prop.value = (void*)&constraint;\n  prop.sizebytes = sizeof(constraint);\n  ret = ioctl(fd, IOCTL_KGSL_SETPROPERTY, &prop);\n  assert(ret == 0);\n\n  // ****** run commands\n  int i = 0;\n  for (auto &it : cmds) {\n    ++i;\n    if (record & THNEED_DEBUG) printf(\"run %2d @ %7lu us: \", i, (nanos_since_boot()-tb)/1000);\n    it->exec();\n    if ((i == cmds.size()) || slow) wait();\n  }\n\n  // ****** copy outputs\n  copy_output(foutput);\n\n  // ****** unset power constraint\n  constraint.type = KGSL_CONSTRAINT_NONE;\n  constraint.data = NULL;\n  constraint.size = 0;\n\n  ret = ioctl(fd, IOCTL_KGSL_SETPROPERTY, &prop);\n  assert(ret == 0);\n\n  if (record & THNEED_DEBUG) {\n    te = nanos_since_boot();\n    printf(\"model exec in %lu us\\n\", (te-tb)/1000);\n  }\n}\n\nvoid Thneed::clinit() {\n  device_id = cl_get_device_id(CL_DEVICE_TYPE_DEFAULT);\n  context = CL_CHECK_ERR(clCreateContext(NULL, 1, &device_id, NULL, NULL, &err));\n  //cl_command_queue_properties props[3] = {CL_QUEUE_PROPERTIES, CL_QUEUE_PROFILING_ENABLE, 0};\n  cl_command_queue_properties props[3] = {CL_QUEUE_PROPERTIES, 0, 0};\n  command_queue = CL_CHECK_ERR(clCreateCommandQueueWithProperties(context, device_id, props, &err));\n  printf(\"Thneed::clinit done\\n\");\n}\n\ncl_int Thneed::clexec() {\n  printf(\"Thneed::clexec: running %lu queued kernels\\n\", kq.size());\n  for (auto &k : kq) {\n    if (record & THNEED_RECORD) ckq.push_back(k);\n    cl_int ret = k->exec();\n    assert(ret == CL_SUCCESS);\n  }\n  return clFinish(command_queue);\n}\n\n// *********** OpenCL interceptor ***********\n\ncl_int thneed_clSetKernelArg(cl_kernel kernel, cl_uint arg_index, size_t arg_size, const void *arg_value) {\n  g_args_size[make_pair(kernel, arg_index)] = arg_size;\n  if (arg_value != NULL) {\n    g_args[make_pair(kernel, arg_index)] = string((char*)arg_value, arg_size);\n  } else {\n    g_args[make_pair(kernel, arg_index)] = string(\"\");\n  }\n  cl_int ret = clSetKernelArg(kernel, arg_index, arg_size, arg_value);\n  return ret;\n}\n\ncl_int thneed_clEnqueueNDRangeKernel(cl_command_queue command_queue,\n  cl_kernel kernel,\n  cl_uint work_dim,\n  const size_t *global_work_offset,\n  const size_t *global_work_size,\n  const size_t *local_work_size,\n  cl_uint num_events_in_wait_list,\n  const cl_event *event_wait_list,\n  cl_event *event) {\n\n  Thneed *thneed = g_thneed;\n\n  // SNPE doesn't use these\n  assert(num_events_in_wait_list == 0);\n  assert(global_work_offset == NULL);\n  assert(event_wait_list == NULL);\n\n  cl_int ret = 0;\n  if (thneed != NULL && thneed->record & THNEED_RECORD) {\n    if (thneed->context == NULL) {\n      thneed->command_queue = command_queue;\n      clGetKernelInfo(kernel, CL_KERNEL_CONTEXT, sizeof(thneed->context), &thneed->context, NULL);\n      clGetContextInfo(thneed->context, CL_CONTEXT_DEVICES, sizeof(thneed->device_id), &thneed->device_id, NULL);\n    }\n\n    // if we are recording, we don't actually enqueue the kernel\n    thneed->kq.push_back(unique_ptr<CLQueuedKernel>(new CLQueuedKernel(thneed, kernel, work_dim, global_work_size, local_work_size)));\n    *event = NULL;\n  } else {\n    ret = clEnqueueNDRangeKernel(command_queue, kernel, work_dim,\n      global_work_offset, global_work_size, local_work_size,\n      num_events_in_wait_list, event_wait_list, event);\n  }\n\n  return ret;\n}\n\ncl_int thneed_clFinish(cl_command_queue command_queue) {\n  Thneed *thneed = g_thneed;\n\n  if (thneed != NULL && thneed->record & THNEED_RECORD) {\n    #ifdef RUN_OPTIMIZER\n      thneed->optimize();\n    #endif\n    return thneed->clexec();\n  } else {\n    return clFinish(command_queue);\n  }\n}\n\ncl_program thneed_clCreateProgramWithSource(cl_context context, cl_uint count, const char **strings, const size_t *lengths, cl_int *errcode_ret) {\n  assert(count == 1);\n  cl_program ret = clCreateProgramWithSource(context, count, strings, lengths, errcode_ret);\n  g_program_source[ret] = strings[0];\n  return ret;\n}\n\nvoid *dlsym(void *handle, const char *symbol) {\n#if defined(QCOM) || defined(QCOM2)\n  void *(*my_dlsym)(void *handle, const char *symbol) = (void *(*)(void *handle, const char *symbol))((uintptr_t)dlopen + DLSYM_OFFSET);\n#else\n  #error \"Unsupported platform for thneed\"\n#endif\n  if (memcmp(\"REAL_\", symbol, 5) == 0) {\n    return my_dlsym(handle, symbol+5);\n  } else if (strcmp(\"clFinish\", symbol) == 0) {\n    return (void*)thneed_clFinish;\n  } else if (strcmp(\"clEnqueueNDRangeKernel\", symbol) == 0) {\n    return (void*)thneed_clEnqueueNDRangeKernel;\n  } else if (strcmp(\"clSetKernelArg\", symbol) == 0) {\n    return (void*)thneed_clSetKernelArg;\n  } else if (strcmp(\"clCreateProgramWithSource\", symbol) == 0) {\n    return (void*)thneed_clCreateProgramWithSource;\n  } else {\n    return my_dlsym(handle, symbol);\n  }\n}\n\n// *********** CLQueuedKernel ***********\n\nCLQueuedKernel::CLQueuedKernel(Thneed *lthneed,\n                               cl_kernel _kernel,\n                               cl_uint _work_dim,\n                               const size_t *_global_work_size,\n                               const size_t *_local_work_size) {\n  thneed = lthneed;\n  kernel = _kernel;\n  work_dim = _work_dim;\n  assert(work_dim <= 3);\n  for (int i = 0; i < work_dim; i++) {\n    global_work_size[i] = _global_work_size[i];\n    local_work_size[i] = _local_work_size[i];\n  }\n\n  char _name[0x100];\n  clGetKernelInfo(kernel, CL_KERNEL_FUNCTION_NAME, sizeof(_name), _name, NULL);\n  name = string(_name);\n  clGetKernelInfo(kernel, CL_KERNEL_NUM_ARGS, sizeof(num_args), &num_args, NULL);\n\n  // get args\n  for (int i = 0; i < num_args; i++) {\n    char arg_name[0x100];\n    clGetKernelArgInfo(kernel, i, CL_KERNEL_ARG_NAME, sizeof(arg_name), arg_name, NULL);\n    arg_names.push_back(string(arg_name));\n    clGetKernelArgInfo(kernel, i, CL_KERNEL_ARG_TYPE_NAME, sizeof(arg_name), arg_name, NULL);\n    arg_types.push_back(string(arg_name));\n\n    args.push_back(g_args[make_pair(kernel, i)]);\n    args_size.push_back(g_args_size[make_pair(kernel, i)]);\n  }\n\n  // get program\n  clGetKernelInfo(kernel, CL_KERNEL_PROGRAM, sizeof(program), &program, NULL);\n}\n\nint CLQueuedKernel::get_arg_num(const char *search_arg_name) {\n  for (int i = 0; i < num_args; i++) {\n    if (arg_names[i] == search_arg_name) return i;\n  }\n  printf(\"failed to find %s in %s\\n\", search_arg_name, name.c_str());\n  assert(false);\n}\n\ncl_int CLQueuedKernel::exec() {\n  if (kernel == NULL) {\n    kernel = clCreateKernel(program, name.c_str(), NULL);\n    arg_names.clear();\n    arg_types.clear();\n\n    for (int j = 0; j < num_args; j++) {\n      char arg_name[0x100];\n      clGetKernelArgInfo(kernel, j, CL_KERNEL_ARG_NAME, sizeof(arg_name), arg_name, NULL);\n      arg_names.push_back(string(arg_name));\n      clGetKernelArgInfo(kernel, j, CL_KERNEL_ARG_TYPE_NAME, sizeof(arg_name), arg_name, NULL);\n      arg_types.push_back(string(arg_name));\n\n      cl_int ret;\n      if (args[j].size() != 0) {\n        assert(args[j].size() == args_size[j]);\n        ret = thneed_clSetKernelArg(kernel, j, args[j].size(), args[j].data());\n      } else {\n        ret = thneed_clSetKernelArg(kernel, j, args_size[j], NULL);\n      }\n      assert(ret == CL_SUCCESS);\n    }\n  }\n\n  if (thneed->record & THNEED_DEBUG) {\n    debug_print(thneed->record & THNEED_VERBOSE_DEBUG);\n  }\n\n  return clEnqueueNDRangeKernel(thneed->command_queue,\n    kernel, work_dim, NULL, global_work_size, local_work_size, 0, NULL, NULL);\n}\n\nvoid CLQueuedKernel::debug_print(bool verbose) {\n  printf(\"%p %56s -- \", kernel, name.c_str());\n  for (int i = 0; i < work_dim; i++) {\n    printf(\"%4zu \", global_work_size[i]);\n  }\n  printf(\" -- \");\n  for (int i = 0; i < work_dim; i++) {\n    printf(\"%4zu \", local_work_size[i]);\n  }\n  printf(\"\\n\");\n\n  if (verbose) {\n    for (int i = 0; i < num_args; i++) {\n      string arg = args[i];\n      printf(\"  %s %s\", arg_types[i].c_str(), arg_names[i].c_str());\n      void *arg_value = (void*)arg.data();\n      int arg_size = arg.size();\n      if (arg_size == 0) {\n        printf(\" (size) %d\", args_size[i]);\n      } else if (arg_size == 1) {\n        printf(\" = %d\", *((char*)arg_value));\n      } else if (arg_size == 2) {\n        printf(\" = %d\", *((short*)arg_value));\n      } else if (arg_size == 4) {\n        if (arg_types[i] == \"float\") {\n          printf(\" = %f\", *((float*)arg_value));\n        } else {\n          printf(\" = %d\", *((int*)arg_value));\n        }\n      } else if (arg_size == 8) {\n        cl_mem val = (cl_mem)(*((uintptr_t*)arg_value));\n        printf(\" = %p\", val);\n        if (val != NULL) {\n          if (arg_types[i] == \"image2d_t\" || arg_types[i] == \"image1d_t\") {\n            cl_image_format format;\n            size_t width, height, depth, array_size, row_pitch, slice_pitch;\n            cl_mem buf;\n            clGetImageInfo(val, CL_IMAGE_FORMAT, sizeof(format), &format, NULL);\n            assert(format.image_channel_order == CL_RGBA);\n            assert(format.image_channel_data_type == CL_HALF_FLOAT);\n            clGetImageInfo(val, CL_IMAGE_WIDTH, sizeof(width), &width, NULL);\n            clGetImageInfo(val, CL_IMAGE_HEIGHT, sizeof(height), &height, NULL);\n            clGetImageInfo(val, CL_IMAGE_ROW_PITCH, sizeof(row_pitch), &row_pitch, NULL);\n            clGetImageInfo(val, CL_IMAGE_DEPTH, sizeof(depth), &depth, NULL);\n            clGetImageInfo(val, CL_IMAGE_ARRAY_SIZE, sizeof(array_size), &array_size, NULL);\n            clGetImageInfo(val, CL_IMAGE_SLICE_PITCH, sizeof(slice_pitch), &slice_pitch, NULL);\n            assert(depth == 0);\n            assert(array_size == 0);\n            assert(slice_pitch == 0);\n\n            clGetImageInfo(val, CL_IMAGE_BUFFER, sizeof(buf), &buf, NULL);\n            size_t sz;\n            clGetMemObjectInfo(buf, CL_MEM_SIZE, sizeof(sz), &sz, NULL);\n            printf(\" image %zu x %zu rp %zu @ %p buffer %zu\", width, height, row_pitch, buf, sz);\n          } else {\n            size_t sz;\n            clGetMemObjectInfo(val, CL_MEM_SIZE, sizeof(sz), &sz, NULL);\n            printf(\" buffer %zu\", sz);\n          }\n        }\n      }\n      printf(\"\\n\");\n    }\n  }\n}\n"
  },
  {
    "path": "selfdrive/modeld/thneed/thneed.h",
    "content": "#pragma once\n\n#ifndef __user\n#define __user __attribute__(())\n#endif\n\n#include <cstdint>\n#include <cstdlib>\n#include <memory>\n#include <string>\n#include <vector>\n\n#include <CL/cl.h>\n\n#include \"selfdrive/modeld/thneed/include/msm_kgsl.h\"\n\n#define THNEED_RECORD 1\n#define THNEED_DEBUG 2\n#define THNEED_VERBOSE_DEBUG 4\n\nusing namespace std;\n\nnamespace json11 {\n  class Json;\n}\nclass Thneed;\n\nclass GPUMalloc {\n  public:\n    GPUMalloc(int size, int fd);\n    ~GPUMalloc();\n    void *alloc(int size);\n  private:\n    uint64_t base;\n    int remaining;\n};\n\nclass CLQueuedKernel {\n  public:\n    CLQueuedKernel(Thneed *lthneed) { thneed = lthneed; }\n    CLQueuedKernel(Thneed *lthneed,\n                   cl_kernel _kernel,\n                   cl_uint _work_dim,\n                   const size_t *_global_work_size,\n                   const size_t *_local_work_size);\n    cl_int exec();\n    void debug_print(bool verbose);\n    int get_arg_num(const char *search_arg_name);\n    cl_program program;\n    string name;\n    cl_uint num_args;\n    vector<string> arg_names;\n    vector<string> arg_types;\n    vector<string> args;\n    vector<int> args_size;\n    cl_kernel kernel = NULL;\n    json11::Json to_json() const;\n\n    cl_uint work_dim;\n    size_t global_work_size[3] = {0};\n    size_t local_work_size[3] = {0};\n  private:\n    Thneed *thneed;\n};\n\nclass CachedIoctl {\n  public:\n    virtual void exec() {}\n};\n\nclass CachedSync: public CachedIoctl {\n  public:\n    CachedSync(Thneed *lthneed, string ldata) { thneed = lthneed; data = ldata; }\n    void exec();\n  private:\n    Thneed *thneed;\n    string data;\n};\n\nclass CachedCommand: public CachedIoctl {\n  public:\n    CachedCommand(Thneed *lthneed, struct kgsl_gpu_command *cmd);\n    void exec();\n  private:\n    void disassemble(int cmd_index);\n    struct kgsl_gpu_command cache;\n    unique_ptr<kgsl_command_object[]> cmds;\n    unique_ptr<kgsl_command_object[]> objs;\n    Thneed *thneed;\n    vector<shared_ptr<CLQueuedKernel> > kq;\n};\n\nclass Thneed {\n  public:\n    Thneed(bool do_clinit=false);\n    void stop();\n    void execute(float **finputs, float *foutput, bool slow=false);\n    void wait();\n    int optimize();\n\n    vector<void *> inputs;\n    vector<size_t> input_sizes;\n    cl_mem output = NULL;\n\n    cl_context context = NULL;\n    cl_command_queue command_queue;\n    cl_device_id device_id;\n    int context_id;\n\n    // protected?\n    int record;\n    int timestamp;\n    unique_ptr<GPUMalloc> ram;\n    vector<unique_ptr<CachedIoctl> > cmds;\n    int fd;\n\n    // all CL kernels\n    void find_inputs_outputs();\n    void copy_inputs(float **finputs);\n    void copy_output(float *foutput);\n    cl_int clexec();\n    vector<shared_ptr<CLQueuedKernel> > kq;\n\n    // pending CL kernels\n    vector<shared_ptr<CLQueuedKernel> > ckq;\n\n    // loading and saving\n    void load(const char *filename);\n    void save(const char *filename, bool save_binaries=false);\n  private:\n    void clinit();\n};\n\n"
  },
  {
    "path": "selfdrive/modeld/transforms/loadyuv.cc",
    "content": "#include \"selfdrive/modeld/transforms/loadyuv.h\"\n\n#include <cassert>\n#include <cstdio>\n#include <cstring>\n\nvoid loadyuv_init(LoadYUVState* s, cl_context ctx, cl_device_id device_id, int width, int height) {\n  memset(s, 0, sizeof(*s));\n\n  s->width = width;\n  s->height = height;\n\n  char args[1024];\n  snprintf(args, sizeof(args),\n           \"-cl-fast-relaxed-math -cl-denorms-are-zero \"\n           \"-DTRANSFORMED_WIDTH=%d -DTRANSFORMED_HEIGHT=%d\",\n           width, height);\n  cl_program prg = cl_program_from_file(ctx, device_id, \"transforms/loadyuv.cl\", args);\n\n  s->loadys_krnl = CL_CHECK_ERR(clCreateKernel(prg, \"loadys\", &err));\n  s->loaduv_krnl = CL_CHECK_ERR(clCreateKernel(prg, \"loaduv\", &err));\n\n  // done with this\n  CL_CHECK(clReleaseProgram(prg));\n}\n\nvoid loadyuv_destroy(LoadYUVState* s) {\n  CL_CHECK(clReleaseKernel(s->loadys_krnl));\n  CL_CHECK(clReleaseKernel(s->loaduv_krnl));\n}\n\nvoid loadyuv_queue(LoadYUVState* s, cl_command_queue q,\n                   cl_mem y_cl, cl_mem u_cl, cl_mem v_cl,\n                   cl_mem out_cl) {\n  CL_CHECK(clSetKernelArg(s->loadys_krnl, 0, sizeof(cl_mem), &y_cl));\n  CL_CHECK(clSetKernelArg(s->loadys_krnl, 1, sizeof(cl_mem), &out_cl));\n\n  const size_t loadys_work_size = (s->width*s->height)/8;\n  CL_CHECK(clEnqueueNDRangeKernel(q, s->loadys_krnl, 1, NULL,\n                               &loadys_work_size, NULL, 0, 0, NULL));\n\n  const size_t loaduv_work_size = ((s->width/2)*(s->height/2))/8;\n  cl_int loaduv_out_off = (s->width*s->height);\n\n  CL_CHECK(clSetKernelArg(s->loaduv_krnl, 0, sizeof(cl_mem), &u_cl));\n  CL_CHECK(clSetKernelArg(s->loaduv_krnl, 1, sizeof(cl_mem), &out_cl));\n  CL_CHECK(clSetKernelArg(s->loaduv_krnl, 2, sizeof(cl_int), &loaduv_out_off));\n\n  CL_CHECK(clEnqueueNDRangeKernel(q, s->loaduv_krnl, 1, NULL,\n                               &loaduv_work_size, NULL, 0, 0, NULL));\n\n  loaduv_out_off += (s->width/2)*(s->height/2);\n\n  CL_CHECK(clSetKernelArg(s->loaduv_krnl, 0, sizeof(cl_mem), &v_cl));\n  CL_CHECK(clSetKernelArg(s->loaduv_krnl, 1, sizeof(cl_mem), &out_cl));\n  CL_CHECK(clSetKernelArg(s->loaduv_krnl, 2, sizeof(cl_int), &loaduv_out_off));\n\n  CL_CHECK(clEnqueueNDRangeKernel(q, s->loaduv_krnl, 1, NULL,\n                               &loaduv_work_size, NULL, 0, 0, NULL));\n}\n"
  },
  {
    "path": "selfdrive/modeld/transforms/loadyuv.cl",
    "content": "#define UV_SIZE ((TRANSFORMED_WIDTH/2)*(TRANSFORMED_HEIGHT/2))\n\n__kernel void loadys(__global uchar8 const * const Y,\n                     __global float * out)\n{\n    const int gid = get_global_id(0);\n    const int ois = gid * 8;\n    const int oy = ois / TRANSFORMED_WIDTH;\n    const int ox = ois % TRANSFORMED_WIDTH;\n\n    const uchar8 ys = Y[gid];\n    const float8 ysf = convert_float8(ys);\n\n    // 02\n    // 13\n\n    __global float* outy0;\n    __global float* outy1;\n    if ((oy & 1) == 0) {\n      outy0 = out; //y0\n      outy1 = out + UV_SIZE*2; //y2\n    } else {\n      outy0 = out + UV_SIZE; //y1\n      outy1 = out + UV_SIZE*3; //y3\n    }\n\n    vstore4(ysf.s0246, 0, outy0 + (oy/2) * (TRANSFORMED_WIDTH/2) + ox/2);\n    vstore4(ysf.s1357, 0, outy1 + (oy/2) * (TRANSFORMED_WIDTH/2) + ox/2);\n}\n\n__kernel void loaduv(__global uchar8 const * const in,\n                     __global float8 * out,\n                     int out_offset)\n{\n  const int gid = get_global_id(0);\n  const uchar8 inv = in[gid];\n  const float8 outv  = convert_float8(inv);\n  out[gid + out_offset / 8] = outv;\n}\n"
  },
  {
    "path": "selfdrive/modeld/transforms/loadyuv.h",
    "content": "#pragma once\n\n#include \"selfdrive/common/clutil.h\"\n\ntypedef struct {\n  int width, height;\n  cl_kernel loadys_krnl, loaduv_krnl;\n} LoadYUVState;\n\nvoid loadyuv_init(LoadYUVState* s, cl_context ctx, cl_device_id device_id, int width, int height);\n\nvoid loadyuv_destroy(LoadYUVState* s);\n\nvoid loadyuv_queue(LoadYUVState* s, cl_command_queue q,\n                   cl_mem y_cl, cl_mem u_cl, cl_mem v_cl,\n                   cl_mem out_cl);\n"
  },
  {
    "path": "selfdrive/modeld/transforms/transform.cc",
    "content": "#include \"selfdrive/modeld/transforms/transform.h\"\n\n#include <cassert>\n#include <cstring>\n\n#include \"selfdrive/common/clutil.h\"\n\nvoid transform_init(Transform* s, cl_context ctx, cl_device_id device_id) {\n  memset(s, 0, sizeof(*s));\n\n  cl_program prg = cl_program_from_file(ctx, device_id, \"transforms/transform.cl\", \"\");\n  s->krnl = CL_CHECK_ERR(clCreateKernel(prg, \"warpPerspective\", &err));\n  // done with this\n  CL_CHECK(clReleaseProgram(prg));\n\n  s->m_y_cl = CL_CHECK_ERR(clCreateBuffer(ctx, CL_MEM_READ_WRITE, 3*3*sizeof(float), NULL, &err));\n  s->m_uv_cl = CL_CHECK_ERR(clCreateBuffer(ctx, CL_MEM_READ_WRITE, 3*3*sizeof(float), NULL, &err));\n}\n\nvoid transform_destroy(Transform* s) {\n  CL_CHECK(clReleaseMemObject(s->m_y_cl));\n  CL_CHECK(clReleaseMemObject(s->m_uv_cl));\n  CL_CHECK(clReleaseKernel(s->krnl));\n}\n\nvoid transform_queue(Transform* s,\n                     cl_command_queue q,\n                     cl_mem in_yuv, int in_width, int in_height,\n                     cl_mem out_y, cl_mem out_u, cl_mem out_v,\n                     int out_width, int out_height,\n                     const mat3& projection) {\n  const int zero = 0;\n\n  // sampled using pixel center origin\n  // (because thats how fastcv and opencv does it)\n\n  mat3 projection_y = projection;\n\n  // in and out uv is half the size of y.\n  mat3 projection_uv = transform_scale_buffer(projection, 0.5);\n\n  CL_CHECK(clEnqueueWriteBuffer(q, s->m_y_cl, CL_TRUE, 0, 3*3*sizeof(float), (void*)projection_y.v, 0, NULL, NULL));\n  CL_CHECK(clEnqueueWriteBuffer(q, s->m_uv_cl, CL_TRUE, 0, 3*3*sizeof(float), (void*)projection_uv.v, 0, NULL, NULL));\n\n  const int in_y_width = in_width;\n  const int in_y_height = in_height;\n  const int in_uv_width = in_width/2;\n  const int in_uv_height = in_height/2;\n  const int in_y_offset = 0;\n  const int in_u_offset = in_y_offset + in_y_width*in_y_height;\n  const int in_v_offset = in_u_offset + in_uv_width*in_uv_height;\n\n  const int out_y_width = out_width;\n  const int out_y_height = out_height;\n  const int out_uv_width = out_width/2;\n  const int out_uv_height = out_height/2;\n\n  CL_CHECK(clSetKernelArg(s->krnl, 0, sizeof(cl_mem), &in_yuv));\n  CL_CHECK(clSetKernelArg(s->krnl, 1, sizeof(cl_int), &in_y_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 2, sizeof(cl_int), &in_y_offset));\n  CL_CHECK(clSetKernelArg(s->krnl, 3, sizeof(cl_int), &in_y_height));\n  CL_CHECK(clSetKernelArg(s->krnl, 4, sizeof(cl_int), &in_y_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 5, sizeof(cl_mem), &out_y));\n  CL_CHECK(clSetKernelArg(s->krnl, 6, sizeof(cl_int), &out_y_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 7, sizeof(cl_int), &zero));\n  CL_CHECK(clSetKernelArg(s->krnl, 8, sizeof(cl_int), &out_y_height));\n  CL_CHECK(clSetKernelArg(s->krnl, 9, sizeof(cl_int), &out_y_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 10, sizeof(cl_mem), &s->m_y_cl));\n\n  const size_t work_size_y[2] = {(size_t)out_y_width, (size_t)out_y_height};\n\n  CL_CHECK(clEnqueueNDRangeKernel(q, s->krnl, 2, NULL,\n                              (const size_t*)&work_size_y, NULL, 0, 0, NULL));\n\n  const size_t work_size_uv[2] = {(size_t)out_uv_width, (size_t)out_uv_height};\n\n  CL_CHECK(clSetKernelArg(s->krnl, 1, sizeof(cl_int), &in_uv_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 2, sizeof(cl_int), &in_u_offset));\n  CL_CHECK(clSetKernelArg(s->krnl, 3, sizeof(cl_int), &in_uv_height));\n  CL_CHECK(clSetKernelArg(s->krnl, 4, sizeof(cl_int), &in_uv_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 5, sizeof(cl_mem), &out_u));\n  CL_CHECK(clSetKernelArg(s->krnl, 6, sizeof(cl_int), &out_uv_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 7, sizeof(cl_int), &zero));\n  CL_CHECK(clSetKernelArg(s->krnl, 8, sizeof(cl_int), &out_uv_height));\n  CL_CHECK(clSetKernelArg(s->krnl, 9, sizeof(cl_int), &out_uv_width));\n  CL_CHECK(clSetKernelArg(s->krnl, 10, sizeof(cl_mem), &s->m_uv_cl));\n  \n  CL_CHECK(clEnqueueNDRangeKernel(q, s->krnl, 2, NULL,\n                              (const size_t*)&work_size_uv, NULL, 0, 0, NULL));\n  CL_CHECK(clSetKernelArg(s->krnl, 2, sizeof(cl_int), &in_v_offset));\n  CL_CHECK(clSetKernelArg(s->krnl, 5, sizeof(cl_mem), &out_v));\n\n  CL_CHECK(clEnqueueNDRangeKernel(q, s->krnl, 2, NULL,\n                              (const size_t*)&work_size_uv, NULL, 0, 0, NULL));\n}\n"
  },
  {
    "path": "selfdrive/modeld/transforms/transform.cl",
    "content": "#define INTER_BITS 5\n#define INTER_TAB_SIZE (1 << INTER_BITS)\n#define INTER_SCALE 1.f / INTER_TAB_SIZE\n\n#define INTER_REMAP_COEF_BITS 15\n#define INTER_REMAP_COEF_SCALE (1 << INTER_REMAP_COEF_BITS)\n\n__kernel void warpPerspective(__global const uchar * src,\n                              int src_step, int src_offset, int src_rows, int src_cols,\n                              __global uchar * dst,\n                              int dst_step, int dst_offset, int dst_rows, int dst_cols,\n                              __constant float * M)\n{\n    int dx = get_global_id(0);\n    int dy = get_global_id(1);\n\n    if (dx < dst_cols && dy < dst_rows)\n    {\n        float X0 = M[0] * dx + M[1] * dy + M[2];\n        float Y0 = M[3] * dx + M[4] * dy + M[5];\n        float W = M[6] * dx + M[7] * dy + M[8];\n        W = W != 0.0f ? INTER_TAB_SIZE / W : 0.0f;\n        int X = rint(X0 * W), Y = rint(Y0 * W);\n\n        short sx = convert_short_sat(X >> INTER_BITS);\n        short sy = convert_short_sat(Y >> INTER_BITS);\n        short ay = (short)(Y & (INTER_TAB_SIZE - 1));\n        short ax = (short)(X & (INTER_TAB_SIZE - 1));\n\n        int v0 = (sx >= 0 && sx < src_cols && sy >= 0 && sy < src_rows) ?\n            convert_int(src[mad24(sy, src_step, src_offset + sx)]) : 0;\n        int v1 = (sx+1 >= 0 && sx+1 < src_cols && sy >= 0 && sy < src_rows) ?\n            convert_int(src[mad24(sy, src_step, src_offset + (sx+1))]) : 0;\n        int v2 = (sx >= 0 && sx < src_cols && sy+1 >= 0 && sy+1 < src_rows) ?\n            convert_int(src[mad24(sy+1, src_step, src_offset + sx)]) : 0;\n        int v3 = (sx+1 >= 0 && sx+1 < src_cols && sy+1 >= 0 && sy+1 < src_rows) ?\n            convert_int(src[mad24(sy+1, src_step, src_offset + (sx+1))]) : 0;\n\n        float taby = 1.f/INTER_TAB_SIZE*ay;\n        float tabx = 1.f/INTER_TAB_SIZE*ax;\n\n        int dst_index = mad24(dy, dst_step, dst_offset + dx);\n\n        int itab0 = convert_short_sat_rte( (1.0f-taby)*(1.0f-tabx) * INTER_REMAP_COEF_SCALE );\n        int itab1 = convert_short_sat_rte( (1.0f-taby)*tabx * INTER_REMAP_COEF_SCALE );\n        int itab2 = convert_short_sat_rte( taby*(1.0f-tabx) * INTER_REMAP_COEF_SCALE );\n        int itab3 = convert_short_sat_rte( taby*tabx * INTER_REMAP_COEF_SCALE );\n\n        int val = v0 * itab0 +  v1 * itab1 + v2 * itab2 + v3 * itab3;\n\n        uchar pix = convert_uchar_sat((val + (1 << (INTER_REMAP_COEF_BITS-1))) >> INTER_REMAP_COEF_BITS);\n        dst[dst_index] = pix;\n    }\n}\n"
  },
  {
    "path": "selfdrive/modeld/transforms/transform.h",
    "content": "#pragma once\n\n#define CL_USE_DEPRECATED_OPENCL_1_2_APIS\n#ifdef __APPLE__\n#include <OpenCL/cl.h>\n#else\n#include <CL/cl.h>\n#endif\n\n#include \"selfdrive/common/mat.h\"\n\ntypedef struct {\n  cl_kernel krnl;\n  cl_mem m_y_cl, m_uv_cl;\n} Transform;\n\nvoid transform_init(Transform* s, cl_context ctx, cl_device_id device_id);\n\nvoid transform_destroy(Transform* transform);\n\nvoid transform_queue(Transform* s, cl_command_queue q,\n                     cl_mem yuv, int in_width, int in_height,\n                     cl_mem out_y, cl_mem out_u, cl_mem out_v,\n                     int out_width, int out_height,\n                     const mat3& projection);\n"
  },
  {
    "path": "selfdrive/monitoring/dmonitoringd.py",
    "content": "#!/usr/bin/env python3\nfrom cereal import car\nfrom common.params import Params\nimport cereal.messaging as messaging\nfrom selfdrive.controls.lib.events import Events\nfrom selfdrive.monitoring.driver_monitor import DriverStatus\nfrom selfdrive.locationd.calibrationd import Calibration\n\n\ndef dmonitoringd_thread(sm=None, pm=None):\n  if pm is None:\n    pm = messaging.PubMaster(['driverMonitoringState'])\n\n  if sm is None:\n    sm = messaging.SubMaster(['driverState', 'liveCalibration', 'carState', 'controlsState', 'modelV2'], poll=['driverState'])\n\n  driver_status = DriverStatus(rhd=Params().get_bool(\"IsRHD\"))\n\n  sm['liveCalibration'].calStatus = Calibration.INVALID\n  sm['liveCalibration'].rpyCalib = [0, 0, 0]\n  sm['carState'].buttonEvents = []\n  sm['carState'].standstill = True\n\n  v_cruise_last = 0\n  driver_engaged = False\n\n  # 10Hz <- dmonitoringmodeld\n  while True:\n    sm.update()\n\n    if not sm.updated['driverState']:\n      continue\n\n    # Get interaction\n    if sm.updated['carState']:\n      v_cruise = sm['carState'].cruiseState.speed\n      driver_engaged = len(sm['carState'].buttonEvents) > 0 or \\\n                        v_cruise != v_cruise_last or \\\n                        sm['carState'].steeringPressed or \\\n                        sm['carState'].gasPressed or \\\n                        sm['carState'].brakePressed\n      if driver_engaged:\n        driver_status.update(Events(), True, sm['controlsState'].enabled, sm['carState'].standstill)\n      v_cruise_last = v_cruise\n\n    if sm.updated['modelV2']:\n      driver_status.set_policy(sm['modelV2'])\n\n    # Get data from dmonitoringmodeld\n    events = Events()\n    driver_status.get_pose(sm['driverState'], sm['liveCalibration'].rpyCalib, sm['carState'].vEgo, sm['controlsState'].enabled)\n\n    # Block engaging after max number of distrations\n    if driver_status.terminal_alert_cnt >= driver_status.settings._MAX_TERMINAL_ALERTS or \\\n       driver_status.terminal_time >= driver_status.settings._MAX_TERMINAL_DURATION:\n      events.add(car.CarEvent.EventName.tooDistracted)\n\n    # Update events from driver state\n    driver_status.update(events, driver_engaged, sm['controlsState'].enabled, sm['carState'].standstill)\n\n    # build driverMonitoringState packet\n    dat = messaging.new_message('driverMonitoringState')\n    dat.driverMonitoringState = {\n      \"events\": events.to_msg(),\n      \"faceDetected\": driver_status.face_detected,\n      \"isDistracted\": driver_status.driver_distracted,\n      \"awarenessStatus\": driver_status.awareness,\n      \"posePitchOffset\": driver_status.pose.pitch_offseter.filtered_stat.mean(),\n      \"posePitchValidCount\": driver_status.pose.pitch_offseter.filtered_stat.n,\n      \"poseYawOffset\": driver_status.pose.yaw_offseter.filtered_stat.mean(),\n      \"poseYawValidCount\": driver_status.pose.yaw_offseter.filtered_stat.n,\n      \"stepChange\": driver_status.step_change,\n      \"awarenessActive\": driver_status.awareness_active,\n      \"awarenessPassive\": driver_status.awareness_passive,\n      \"isLowStd\": driver_status.pose.low_std,\n      \"hiStdCount\": driver_status.hi_stds,\n      \"isActiveMode\": driver_status.active_monitoring_mode,\n    }\n    pm.send('driverMonitoringState', dat)\n\ndef main(sm=None, pm=None):\n  dmonitoringd_thread(sm, pm)\n\nif __name__ == '__main__':\n  main()\n"
  },
  {
    "path": "selfdrive/monitoring/driver_monitor.py",
    "content": "from math import atan2, sqrt\n\nfrom cereal import car\nfrom common.numpy_fast import interp\nfrom common.realtime import DT_DMON\nfrom selfdrive.hardware import TICI\nfrom common.filter_simple import FirstOrderFilter\nfrom common.stat_live import RunningStatFilter\n\nEventName = car.CarEvent.EventName\n\n# ******************************************************************************************\n#  NOTE: To fork maintainers.\n#  Disabling or nerfing safety features will get you and your users banned from our servers.\n#  We recommend that you do not change these numbers from the defaults.\n# ******************************************************************************************\n\nclass DRIVER_MONITOR_SETTINGS():\n  def __init__(self, TICI=TICI, DT_DMON=DT_DMON):\n    self._DT_DMON = DT_DMON\n    self._AWARENESS_TIME = 35. # passive wheeltouch total timeout\n    self._AWARENESS_PRE_TIME_TILL_TERMINAL = 12.\n    self._AWARENESS_PROMPT_TIME_TILL_TERMINAL = 6.\n    self._DISTRACTED_TIME = 11. # active monitoring total timeout\n    self._DISTRACTED_PRE_TIME_TILL_TERMINAL = 8.\n    self._DISTRACTED_PROMPT_TIME_TILL_TERMINAL = 6.\n\n    self._FACE_THRESHOLD = 0.5\n    self._PARTIAL_FACE_THRESHOLD = 0.765 if TICI else 0.455\n    self._EYE_THRESHOLD = 0.25 if TICI else 0.57\n    self._SG_THRESHOLD = 0.83\n    self._BLINK_THRESHOLD = 0.62 if TICI else 0.68\n    self._BLINK_THRESHOLD_SLACK = 0.82 if TICI else 0.88\n    self._BLINK_THRESHOLD_STRICT = 0.62 if TICI else 0.68\n    self._PITCH_WEIGHT = 1.175 if TICI else 1.35  # pitch matters a lot more\n    self._POSESTD_THRESHOLD = 0.2 if TICI else 0.175\n    self._E2E_POSE_THRESHOLD = 0.95 if TICI else 0.9\n    self._E2E_EYES_THRESHOLD = 0.75\n\n    self._METRIC_THRESHOLD = 0.55 if TICI else 0.48\n    self._METRIC_THRESHOLD_SLACK = 0.75 if TICI else 0.66\n    self._METRIC_THRESHOLD_STRICT = 0.55 if TICI else 0.48\n    self._PITCH_POS_ALLOWANCE = 0.12  # rad, to not be too sensitive on positive pitch\n    self._PITCH_NATURAL_OFFSET = 0.02  # people don't seem to look straight when they drive relaxed, rather a bit up\n    self._YAW_NATURAL_OFFSET = 0.08  # people don't seem to look straight when they drive relaxed, rather a bit to the right (center of car)\n\n    self._HI_STD_FALLBACK_TIME = int(10  / self._DT_DMON)  # fall back to wheel touch if model is uncertain for 10s\n    self._DISTRACTED_FILTER_TS = 0.25  # 0.6Hz\n\n    self._POSE_CALIB_MIN_SPEED = 13  # 30 mph\n    self._POSE_OFFSET_MIN_COUNT = int(60 / self._DT_DMON)  # valid data counts before calibration completes, 1min cumulative\n    self._POSE_OFFSET_MAX_COUNT = int(360 / self._DT_DMON)  # stop deweighting new data after 6 min, aka \"short term memory\"\n\n    self._RECOVERY_FACTOR_MAX = 5.  # relative to minus step change\n    self._RECOVERY_FACTOR_MIN = 1.25  # relative to minus step change\n\n    self._MAX_TERMINAL_ALERTS = 3  # not allowed to engage after 3 terminal alerts\n    self._MAX_TERMINAL_DURATION = int(30 / self._DT_DMON)  # not allowed to engage after 30s of terminal alerts\n\n\n# model output refers to center of cropped image, so need to apply the x displacement offset\nRESIZED_FOCAL = 320.0\nH, W, FULL_W = 320, 160, 426\n\nclass DistractedType:\n  NOT_DISTRACTED = 0\n  BAD_POSE = 1\n  BAD_BLINK = 2\n\ndef face_orientation_from_net(angles_desc, pos_desc, rpy_calib, is_rhd):\n  # the output of these angles are in device frame\n  # so from driver's perspective, pitch is up and yaw is right\n\n  pitch_net, yaw_net, roll_net = angles_desc\n\n  face_pixel_position = ((pos_desc[0] + .5)*W - W + FULL_W, (pos_desc[1]+.5)*H)\n  yaw_focal_angle = atan2(face_pixel_position[0] - FULL_W//2, RESIZED_FOCAL)\n  pitch_focal_angle = atan2(face_pixel_position[1] - H//2, RESIZED_FOCAL)\n\n  pitch = pitch_net + pitch_focal_angle\n  yaw = -yaw_net + yaw_focal_angle\n\n  # no calib for roll\n  pitch -= rpy_calib[1]\n  yaw -= rpy_calib[2] * (1 - 2 * int(is_rhd))  # lhd -> -=, rhd -> +=\n  return roll_net, pitch, yaw\n\nclass DriverPose():\n  def __init__(self, max_trackable):\n    self.yaw = 0.\n    self.pitch = 0.\n    self.roll = 0.\n    self.yaw_std = 0.\n    self.pitch_std = 0.\n    self.roll_std = 0.\n    self.pitch_offseter = RunningStatFilter(max_trackable=max_trackable)\n    self.yaw_offseter = RunningStatFilter(max_trackable=max_trackable)\n    self.low_std = True\n    self.cfactor = 1.\n\nclass DriverBlink():\n  def __init__(self):\n    self.left_blink = 0.\n    self.right_blink = 0.\n    self.cfactor = 1.\n\nclass DriverStatus():\n  def __init__(self, rhd=False, settings=DRIVER_MONITOR_SETTINGS()):\n    # init policy settings\n    self.settings = settings\n\n    # init driver status\n    self.is_rhd_region = rhd\n    self.pose = DriverPose(self.settings._POSE_OFFSET_MAX_COUNT)\n    self.pose_calibrated = False\n    self.blink = DriverBlink()\n    self.awareness = 1.\n    self.awareness_active = 1.\n    self.awareness_passive = 1.\n    self.driver_distracted = False\n    self.driver_distraction_filter = FirstOrderFilter(0., self.settings._DISTRACTED_FILTER_TS, self.settings._DT_DMON)\n    self.face_detected = False\n    self.face_partial = False\n    self.terminal_alert_cnt = 0\n    self.terminal_time = 0\n    self.step_change = 0.\n    self.active_monitoring_mode = True\n    self.is_model_uncertain = False\n    self.hi_stds = 0\n    self.threshold_pre = self.settings._DISTRACTED_PRE_TIME_TILL_TERMINAL / self.settings._DISTRACTED_TIME\n    self.threshold_prompt = self.settings._DISTRACTED_PROMPT_TIME_TILL_TERMINAL / self.settings._DISTRACTED_TIME\n\n    self._set_timers(active_monitoring=True)\n\n  def _set_timers(self, active_monitoring):\n    if self.active_monitoring_mode and self.awareness <= self.threshold_prompt:\n      if active_monitoring:\n        self.step_change = self.settings._DT_DMON / self.settings._DISTRACTED_TIME\n      else:\n        self.step_change = 0.\n      return  # no exploit after orange alert\n    elif self.awareness <= 0.:\n      return\n\n    if active_monitoring:\n      # when falling back from passive mode to active mode, reset awareness to avoid false alert\n      if not self.active_monitoring_mode:\n        self.awareness_passive = self.awareness\n        self.awareness = self.awareness_active\n\n      self.threshold_pre = self.settings._DISTRACTED_PRE_TIME_TILL_TERMINAL / self.settings._DISTRACTED_TIME\n      self.threshold_prompt = self.settings._DISTRACTED_PROMPT_TIME_TILL_TERMINAL / self.settings._DISTRACTED_TIME\n      self.step_change = self.settings._DT_DMON / self.settings._DISTRACTED_TIME\n      self.active_monitoring_mode = True\n    else:\n      if self.active_monitoring_mode:\n        self.awareness_active = self.awareness\n        self.awareness = self.awareness_passive\n\n      self.threshold_pre = self.settings._AWARENESS_PRE_TIME_TILL_TERMINAL / self.settings._AWARENESS_TIME\n      self.threshold_prompt = self.settings._AWARENESS_PROMPT_TIME_TILL_TERMINAL / self.settings._AWARENESS_TIME\n      self.step_change = self.settings._DT_DMON / self.settings._AWARENESS_TIME\n      self.active_monitoring_mode = False\n\n  def _is_driver_distracted(self, pose, blink):\n    if not self.pose_calibrated:\n      pitch_error = pose.pitch - self.settings._PITCH_NATURAL_OFFSET\n      yaw_error = pose.yaw - self.settings._YAW_NATURAL_OFFSET\n    else:\n      pitch_error = pose.pitch - self.pose.pitch_offseter.filtered_stat.mean()\n      yaw_error = pose.yaw - self.pose.yaw_offseter.filtered_stat.mean()\n\n    # positive pitch allowance\n    if pitch_error > 0.:\n      pitch_error = max(pitch_error - self.settings._PITCH_POS_ALLOWANCE, 0.)\n    pitch_error *= self.settings._PITCH_WEIGHT\n    pose_metric = sqrt(yaw_error**2 + pitch_error**2)\n\n    if pose_metric > self.settings._METRIC_THRESHOLD*pose.cfactor:\n      return DistractedType.BAD_POSE\n    elif (blink.left_blink + blink.right_blink)*0.5 > self.settings._BLINK_THRESHOLD*blink.cfactor:\n      return DistractedType.BAD_BLINK\n    else:\n      return DistractedType.NOT_DISTRACTED\n\n  def set_policy(self, model_data):\n    ep = min(model_data.meta.engagedProb, 0.8) / 0.8\n    self.pose.cfactor = interp(ep, [0, 0.5, 1],\n                                           [self.settings._METRIC_THRESHOLD_STRICT,\n                                            self.settings. _METRIC_THRESHOLD,\n                                            self.settings._METRIC_THRESHOLD_SLACK]) / self.settings._METRIC_THRESHOLD\n    self.blink.cfactor = interp(ep, [0, 0.5, 1],\n                                           [self.settings._BLINK_THRESHOLD_STRICT,\n                                            self.settings._BLINK_THRESHOLD,\n                                            self.settings._BLINK_THRESHOLD_SLACK]) / self.settings._BLINK_THRESHOLD\n\n  def get_pose(self, driver_state, cal_rpy, car_speed, op_engaged):\n    if not all(len(x) > 0 for x in [driver_state.faceOrientation, driver_state.facePosition,\n                                    driver_state.faceOrientationStd, driver_state.facePositionStd]):\n      return\n\n    self.face_partial = driver_state.partialFace > self.settings._PARTIAL_FACE_THRESHOLD\n    self.face_detected = driver_state.faceProb > self.settings._FACE_THRESHOLD or self.face_partial\n    self.pose.roll, self.pose.pitch, self.pose.yaw = face_orientation_from_net(driver_state.faceOrientation, driver_state.facePosition, cal_rpy, self.is_rhd_region)\n    self.pose.pitch_std = driver_state.faceOrientationStd[0]\n    self.pose.yaw_std = driver_state.faceOrientationStd[1]\n    # self.pose.roll_std = driver_state.faceOrientationStd[2]\n    model_std_max = max(self.pose.pitch_std, self.pose.yaw_std)\n    self.pose.low_std = model_std_max < self.settings._POSESTD_THRESHOLD and not self.face_partial\n    self.blink.left_blink = driver_state.leftBlinkProb * (driver_state.leftEyeProb > self.settings._EYE_THRESHOLD) * (driver_state.sunglassesProb < self.settings._SG_THRESHOLD)\n    self.blink.right_blink = driver_state.rightBlinkProb * (driver_state.rightEyeProb > self.settings._EYE_THRESHOLD) * (driver_state.sunglassesProb < self.settings._SG_THRESHOLD)\n\n    distracted_normal = self._is_driver_distracted(self.pose, self.blink) > 0 and \\\n                                   driver_state.faceProb > self.settings._FACE_THRESHOLD and self.pose.low_std\n    distracted_E2E = (driver_state.distractedPose > self.settings._E2E_POSE_THRESHOLD or driver_state.distractedEyes > self.settings._E2E_EYES_THRESHOLD) and \\\n                              (self.face_detected and not self.face_partial)\n    self.driver_distracted = distracted_normal or distracted_E2E\n    self.driver_distraction_filter.update(self.driver_distracted)\n\n    # update offseter\n    # only update when driver is actively driving the car above a certain speed\n    if self.face_detected and car_speed > self.settings._POSE_CALIB_MIN_SPEED and self.pose.low_std and (not op_engaged or not self.driver_distracted):\n      self.pose.pitch_offseter.push_and_update(self.pose.pitch)\n      self.pose.yaw_offseter.push_and_update(self.pose.yaw)\n\n    self.pose_calibrated = self.pose.pitch_offseter.filtered_stat.n > self.settings._POSE_OFFSET_MIN_COUNT and \\\n                                       self.pose.yaw_offseter.filtered_stat.n > self.settings._POSE_OFFSET_MIN_COUNT\n\n    self.is_model_uncertain = self.hi_stds > self.settings._HI_STD_FALLBACK_TIME\n    self._set_timers(self.face_detected and not self.is_model_uncertain)\n    if self.face_detected and not self.pose.low_std and not self.driver_distracted:\n      self.hi_stds += 1\n    elif self.face_detected and self.pose.low_std:\n      self.hi_stds = 0\n\n  def update(self, events, driver_engaged, ctrl_active, standstill):\n    if (driver_engaged and self.awareness > 0) or not ctrl_active:\n      # reset only when on disengagement if red reached\n      self.awareness = 1.\n      self.awareness_active = 1.\n      self.awareness_passive = 1.\n      return\n\n    driver_attentive = self.driver_distraction_filter.x < 0.37\n    awareness_prev = self.awareness\n\n    if (driver_attentive and self.face_detected and self.pose.low_std and self.awareness > 0):\n      # only restore awareness when paying attention and alert is not red\n      self.awareness = min(self.awareness + ((self.settings._RECOVERY_FACTOR_MAX-self.settings._RECOVERY_FACTOR_MIN)*(1.-self.awareness)+self.settings._RECOVERY_FACTOR_MIN)*self.step_change, 1.)\n      if self.awareness == 1.:\n        self.awareness_passive = min(self.awareness_passive + self.step_change, 1.)\n      # don't display alert banner when awareness is recovering and has cleared orange\n      if self.awareness > self.threshold_prompt:\n        return\n\n    standstill_exemption = standstill and self.awareness - self.step_change <= self.threshold_prompt\n    certainly_distracted = self.driver_distraction_filter.x > 0.63 and self.driver_distracted and self.face_detected\n    maybe_distracted = self.hi_stds > self.settings._HI_STD_FALLBACK_TIME or not self.face_detected\n    if certainly_distracted or maybe_distracted:\n      # should always be counting if distracted unless at standstill and reaching orange\n      if not standstill_exemption:\n        self.awareness = max(self.awareness - self.step_change, -0.1)\n\n    alert = None\n    if self.awareness <= 0.:\n      # terminal red alert: disengagement required\n      alert = EventName.driverDistracted if self.active_monitoring_mode else EventName.driverUnresponsive\n      self.terminal_time += 1\n      if awareness_prev > 0.:\n        self.terminal_alert_cnt += 1\n    elif self.awareness <= self.threshold_prompt:\n      # prompt orange alert\n      alert = EventName.promptDriverDistracted if self.active_monitoring_mode else EventName.promptDriverUnresponsive\n    elif self.awareness <= self.threshold_pre:\n      # pre green alert\n      alert = EventName.preDriverDistracted if self.active_monitoring_mode else EventName.preDriverUnresponsive\n\n    if alert is not None:\n      events.add(alert)\n"
  },
  {
    "path": "selfdrive/pandad.py",
    "content": "#!/usr/bin/env python3\n# simple boardd wrapper that updates the panda first\nimport os\nimport time\n\nfrom panda import BASEDIR as PANDA_BASEDIR, Panda, PandaDFU\nfrom common.basedir import BASEDIR\nfrom common.params import Params\nfrom selfdrive.swaglog import cloudlog\n\nPANDA_FW_FN = os.path.join(PANDA_BASEDIR, \"board\", \"obj\", \"panda.bin.signed\")\n\n\ndef get_expected_signature() -> bytes:\n  try:\n    return Panda.get_signature_from_firmware(PANDA_FW_FN)\n  except Exception:\n    cloudlog.exception(\"Error computing expected signature\")\n    return b\"\"\n\n\ndef update_panda() -> Panda:\n  panda = None\n  panda_dfu = None\n\n  cloudlog.info(\"Connecting to panda\")\n\n  while True:\n    # break on normal mode Panda\n    panda_list = Panda.list()\n    if len(panda_list) > 0:\n      cloudlog.info(\"Panda found, connecting\")\n      panda = Panda(panda_list[0])\n      break\n\n    # flash on DFU mode Panda\n    panda_dfu = PandaDFU.list()\n    if len(panda_dfu) > 0:\n      cloudlog.info(\"Panda in DFU mode found, flashing recovery\")\n      panda_dfu = PandaDFU(panda_dfu[0])\n      panda_dfu.recover()\n\n    time.sleep(1)\n\n  fw_signature = get_expected_signature()\n\n  try:\n    serial = panda.get_serial()[0].decode(\"utf-8\")\n  except Exception:\n    serial = None\n\n  panda_version = \"bootstub\" if panda.bootstub else panda.get_version()\n  panda_signature = b\"\" if panda.bootstub else panda.get_signature()\n  cloudlog.warning(\"Panda %s connected, version: %s, signature %s, expected %s\" % (\n    serial,\n    panda_version,\n    panda_signature.hex(),\n    fw_signature.hex(),\n  ))\n\n  if panda.bootstub or panda_signature != fw_signature:\n    cloudlog.info(\"Panda firmware out of date, update required\")\n    panda.flash()\n    cloudlog.info(\"Done flashing\")\n\n  if panda.bootstub:\n    bootstub_version = panda.get_version()\n    cloudlog.info(f\"Flashed firmware not booting, flashing development bootloader. Bootstub version: {bootstub_version}\")\n    panda.recover()\n    cloudlog.info(\"Done flashing bootloader\")\n\n  if panda.bootstub:\n    cloudlog.info(\"Panda still not booting, exiting\")\n    raise AssertionError\n\n  panda_signature = panda.get_signature()\n  if panda_signature != fw_signature:\n    cloudlog.info(\"Version mismatch after flashing, exiting\")\n    raise AssertionError\n\n  return panda\n\n\ndef main() -> None:\n  panda = update_panda()\n\n  # check health for lost heartbeat\n  health = panda.health()\n  if health[\"heartbeat_lost\"]:\n    Params().put_bool(\"PandaHeartbeatLost\", True)\n    cloudlog.event(\"heartbeat lost\", deviceState=health)\n\n  cloudlog.info(\"Resetting panda\")\n  panda.reset()\n\n  os.chdir(os.path.join(BASEDIR, \"selfdrive/boardd\"))\n  os.execvp(\"./boardd\", [\"./boardd\"])\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/proclogd/SConscript",
    "content": "Import('env', 'cereal', 'messaging', 'common')\nlibs = [cereal, messaging, 'pthread', 'zmq', 'capnp', 'kj', 'common', 'zmq', 'json11']\nenv.Program('proclogd', ['main.cc', 'proclog.cc'], LIBS=libs)\n\nif GetOption('test'):\n  env.Program('tests/test_proclog', ['tests/test_proclog.cc', 'proclog.cc'], LIBS=libs)\n"
  },
  {
    "path": "selfdrive/proclogd/main.cc",
    "content": "\n#include <sys/resource.h>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/proclogd/proclog.h\"\n\nExitHandler do_exit;\n\nint main(int argc, char **argv) {\n  setpriority(PRIO_PROCESS, 0, -15);\n\n  PubMaster publisher({\"procLog\"});\n  while (!do_exit) {\n    MessageBuilder msg;\n    buildProcLogMessage(msg);\n    publisher.send(\"procLog\", msg);\n\n    util::sleep_for(2000);  // 2 secs\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/proclogd/proclog.cc",
    "content": "#include \"selfdrive/proclogd/proclog.h\"\n\n#include <dirent.h>\n\n#include <cassert>\n#include <fstream>\n#include <iterator>\n#include <sstream>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n\nnamespace Parser {\n\n// parse /proc/stat\nstd::vector<CPUTime> cpuTimes(std::istream &stream) {\n  std::vector<CPUTime> cpu_times;\n  std::string line;\n  // skip the first line for cpu total\n  std::getline(stream, line);\n  while (std::getline(stream, line)) {\n    if (line.compare(0, 3, \"cpu\") != 0) break;\n\n    CPUTime t = {};\n    std::istringstream iss(line);\n    if (iss.ignore(3) >> t.id >> t.utime >> t.ntime >> t.stime >> t.itime >> t.iowtime >> t.irqtime >> t.sirqtime)\n      cpu_times.push_back(t);\n  }\n  return cpu_times;\n}\n\n// parse /proc/meminfo\nstd::unordered_map<std::string, uint64_t> memInfo(std::istream &stream) {\n  std::unordered_map<std::string, uint64_t> mem_info;\n  std::string line, key;\n  while (std::getline(stream, line)) {\n    uint64_t val = 0;\n    std::istringstream iss(line);\n    if (iss >> key >> val) {\n      mem_info[key] = val * 1024;\n    }\n  }\n  return mem_info;\n}\n\n// field position (https://man7.org/linux/man-pages/man5/proc.5.html)\nenum StatPos {\n  pid = 1,\n  state = 3,\n  ppid = 4,\n  utime = 14,\n  stime = 15,\n  cutime = 16,\n  cstime = 17,\n  priority = 18,\n  nice = 19,\n  num_threads = 20,\n  starttime = 22,\n  vsize = 23,\n  rss = 24,\n  processor = 39,\n  MAX_FIELD = 52,\n};\n\n// parse /proc/pid/stat\nstd::optional<ProcStat> procStat(std::string stat) {\n  // To avoid being fooled by names containing a closing paren, scan backwards.\n  auto open_paren = stat.find('(');\n  auto close_paren = stat.rfind(')');\n  if (open_paren == std::string::npos || close_paren == std::string::npos || open_paren > close_paren) {\n    return std::nullopt;\n  }\n\n  std::string name = stat.substr(open_paren + 1, close_paren - open_paren - 1);\n  // repace space in name with _\n  std::replace(&stat[open_paren], &stat[close_paren], ' ', '_');\n  std::istringstream iss(stat);\n  std::vector<std::string> v{std::istream_iterator<std::string>(iss),\n                             std::istream_iterator<std::string>()};\n  try {\n    if (v.size() != StatPos::MAX_FIELD) {\n      throw std::invalid_argument(\"stat\");\n    }\n    ProcStat p = {\n      .name = name,\n      .pid = stoi(v[StatPos::pid - 1]),\n      .state = v[StatPos::state - 1][0],\n      .ppid = stoi(v[StatPos::ppid - 1]),\n      .utime = stoul(v[StatPos::utime - 1]),\n      .stime = stoul(v[StatPos::stime - 1]),\n      .cutime = stol(v[StatPos::cutime - 1]),\n      .cstime = stol(v[StatPos::cstime - 1]),\n      .priority = stol(v[StatPos::priority - 1]),\n      .nice = stol(v[StatPos::nice - 1]),\n      .num_threads = stol(v[StatPos::num_threads - 1]),\n      .starttime = stoull(v[StatPos::starttime - 1]),\n      .vms = stoul(v[StatPos::vsize - 1]),\n      .rss = stoul(v[StatPos::rss - 1]),\n      .processor = stoi(v[StatPos::processor - 1]),\n    };\n    return p;\n  } catch (const std::invalid_argument &e) {\n    LOGE(\"failed to parse procStat (%s) :%s\", e.what(), stat.c_str());\n  } catch (const std::out_of_range &e) {\n    LOGE(\"failed to parse procStat (%s) :%s\", e.what(), stat.c_str());\n  }\n  return std::nullopt;\n}\n\n// return list of PIDs from /proc\nstd::vector<int> pids() {\n  std::vector<int> ids;\n  DIR *d = opendir(\"/proc\");\n  assert(d);\n  char *p_end;\n  struct dirent *de = NULL;\n  while ((de = readdir(d))) {\n    if (de->d_type == DT_DIR) {\n      int pid = strtol(de->d_name, &p_end, 10);\n      if (p_end == (de->d_name + strlen(de->d_name))) {\n        ids.push_back(pid);\n      }\n    }\n  }\n  closedir(d);\n  return ids;\n}\n\n// null-delimited cmdline arguments to vector\nstd::vector<std::string> cmdline(std::istream &stream) {\n  std::vector<std::string> ret;\n  std::string line;\n  while (std::getline(stream, line, '\\0')) {\n    if (!line.empty()) {\n      ret.push_back(line);\n    }\n  }\n  return ret;\n}\n\nconst ProcCache &getProcExtraInfo(int pid, const std::string &name) {\n  static std::unordered_map<pid_t, ProcCache> proc_cache;\n  ProcCache &cache = proc_cache[pid];\n  if (cache.pid != pid || cache.name != name) {\n    cache.pid = pid;\n    cache.name = name;\n    std::string proc_path = \"/proc/\" + std::to_string(pid);\n    cache.exe = util::readlink(proc_path + \"/exe\");\n    std::ifstream stream(proc_path + \"/cmdline\");\n    cache.cmdline = cmdline(stream);\n  }\n  return cache;\n}\n\n}  // namespace Parser\n\nconst double jiffy = sysconf(_SC_CLK_TCK);\nconst size_t page_size = sysconf(_SC_PAGE_SIZE);\n\nvoid buildCPUTimes(cereal::ProcLog::Builder &builder) {\n  std::ifstream stream(\"/proc/stat\");\n  std::vector<CPUTime> stats = Parser::cpuTimes(stream);\n\n  auto log_cpu_times = builder.initCpuTimes(stats.size());\n  for (int i = 0; i < stats.size(); ++i) {\n    auto l = log_cpu_times[i];\n    const CPUTime &r = stats[i];\n    l.setCpuNum(r.id);\n    l.setUser(r.utime / jiffy);\n    l.setNice(r.ntime / jiffy);\n    l.setSystem(r.stime / jiffy);\n    l.setIdle(r.itime / jiffy);\n    l.setIowait(r.iowtime / jiffy);\n    l.setIrq(r.irqtime / jiffy);\n    l.setSoftirq(r.sirqtime / jiffy);\n  }\n}\n\nvoid buildMemInfo(cereal::ProcLog::Builder &builder) {\n  std::ifstream stream(\"/proc/meminfo\");\n  auto mem_info = Parser::memInfo(stream);\n\n  auto mem = builder.initMem();\n  mem.setTotal(mem_info[\"MemTotal:\"]);\n  mem.setFree(mem_info[\"MemFree:\"]);\n  mem.setAvailable(mem_info[\"MemAvailable:\"]);\n  mem.setBuffers(mem_info[\"Buffers:\"]);\n  mem.setCached(mem_info[\"Cached:\"]);\n  mem.setActive(mem_info[\"Active:\"]);\n  mem.setInactive(mem_info[\"Inactive:\"]);\n  mem.setShared(mem_info[\"Shmem:\"]);\n}\n\nvoid buildProcs(cereal::ProcLog::Builder &builder) {\n  auto pids = Parser::pids();\n  std::vector<ProcStat> proc_stats;\n  proc_stats.reserve(pids.size());\n  for (int pid : pids) {\n    std::string path = \"/proc/\" + std::to_string(pid) + \"/stat\";\n    if (auto stat = Parser::procStat(util::read_file(path))) {\n      proc_stats.push_back(*stat);\n    }\n  }\n\n  auto procs = builder.initProcs(proc_stats.size());\n  for (size_t i = 0; i < proc_stats.size(); i++) {\n    auto l = procs[i];\n    const ProcStat &r = proc_stats[i];\n    l.setPid(r.pid);\n    l.setState(r.state);\n    l.setPpid(r.ppid);\n    l.setCpuUser(r.utime / jiffy);\n    l.setCpuSystem(r.stime / jiffy);\n    l.setCpuChildrenUser(r.cutime / jiffy);\n    l.setCpuChildrenSystem(r.cstime / jiffy);\n    l.setPriority(r.priority);\n    l.setNice(r.nice);\n    l.setNumThreads(r.num_threads);\n    l.setStartTime(r.starttime / jiffy);\n    l.setMemVms(r.vms);\n    l.setMemRss((uint64_t)r.rss * page_size);\n    l.setProcessor(r.processor);\n    l.setName(r.name);\n\n    const ProcCache &extra_info = Parser::getProcExtraInfo(r.pid, r.name);\n    l.setExe(extra_info.exe);\n    auto lcmdline = l.initCmdline(extra_info.cmdline.size());\n    for (size_t i = 0; i < lcmdline.size(); i++) {\n      lcmdline.set(i, extra_info.cmdline[i]);\n    }\n  }\n}\n\nvoid buildProcLogMessage(MessageBuilder &msg) {\n  auto procLog = msg.initEvent().initProcLog();\n  buildProcs(procLog);\n  buildCPUTimes(procLog);\n  buildMemInfo(procLog);\n}\n"
  },
  {
    "path": "selfdrive/proclogd/proclog.h",
    "content": "#include <optional>\n#include <string>\n#include <unordered_map>\n#include <vector>\n\n#include \"cereal/messaging/messaging.h\"\n\nstruct CPUTime {\n  int id;\n  unsigned long utime, ntime, stime, itime;\n  unsigned long iowtime, irqtime, sirqtime;\n};\n\nstruct ProcCache {\n  int pid;\n  std::string name, exe;\n  std::vector<std::string> cmdline;\n};\n\nstruct ProcStat {\n  int pid, ppid, processor;\n  char state;\n  long cutime, cstime, priority, nice, num_threads;\n  unsigned long utime, stime, vms, rss;\n  unsigned long long starttime;\n  std::string name;\n};\n\nnamespace Parser {\n\nstd::vector<int> pids();\nstd::optional<ProcStat> procStat(std::string stat);\nstd::vector<std::string> cmdline(std::istream &stream);\nstd::vector<CPUTime> cpuTimes(std::istream &stream);\nstd::unordered_map<std::string, uint64_t> memInfo(std::istream &stream);\nconst ProcCache &getProcExtraInfo(int pid, const std::string &name);\n\n};  // namespace Parser\n\nvoid buildProcLogMessage(MessageBuilder &msg);\n"
  },
  {
    "path": "selfdrive/rtshield.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport time\nfrom typing import NoReturn\n\nfrom common.realtime import set_core_affinity, set_realtime_priority\n\n# RT shield - ensure CPU 3 always remains available for RT processes\n#   runs as SCHED_FIFO with minimum priority to ensure kthreads don't\n#   get scheduled onto CPU 3, but it's always preemptible by realtime\n#   openpilot processes\n\ndef main() -> NoReturn:\n  set_core_affinity(int(os.getenv(\"CORE\", \"3\")))\n  set_realtime_priority(1)\n\n  while True:\n    time.sleep(0.000001)\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/sensord/SConscript",
    "content": "Import('env', 'arch', 'common', 'cereal', 'messaging')\n\nif arch == \"aarch64\":\n  env.Program('_sensord', 'sensors_qcom.cc', LIBS=['hardware', common, cereal, messaging, 'capnp', 'zmq', 'kj'])\nelse:\n  sensors = [\n    'sensors/file_sensor.cc',\n    'sensors/i2c_sensor.cc',\n    'sensors/light_sensor.cc',\n    'sensors/bmx055_accel.cc',\n    'sensors/bmx055_gyro.cc',\n    'sensors/bmx055_magn.cc',\n    'sensors/bmx055_temp.cc',\n    'sensors/lsm6ds3_accel.cc',\n    'sensors/lsm6ds3_gyro.cc',\n    'sensors/lsm6ds3_temp.cc',\n    'sensors/mmc5603nj_magn.cc',\n  ]\n  libs = [common, cereal, messaging, 'capnp', 'zmq', 'kj']\n  if arch == \"larch64\":\n    libs.append('i2c')\n  env.Program('_sensord', ['sensors_qcom2.cc'] + sensors, LIBS=libs)\n"
  },
  {
    "path": "selfdrive/sensord/libdiag.h",
    "content": "#pragma once\n\n#include <stdint.h>\n#include <stdbool.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define DIAG_MAX_RX_PKT_SIZ 4096\n\nbool Diag_LSM_Init(uint8_t* pIEnv);\nbool Diag_LSM_DeInit(void);\n\n// DCI\n\n#define DIAG_CON_APSS 0x001\n#define DIAG_CON_MPSS 0x002\n#define DIAG_CON_LPASS 0x004\n#define DIAG_CON_WCNSS 0x008\n\nenum {\n  DIAG_DCI_NO_ERROR = 1001,\n} diag_dci_error_type;\n\nint diag_register_dci_client(int*, uint16_t*, int, void*);\nint diag_log_stream_config(int client_id, int set_mask, uint16_t log_codes_array[], int num_codes);\nint diag_register_dci_stream(void (*func_ptr_logs)(unsigned char *ptr, int len), void (*func_ptr_events)(unsigned char *ptr, int len));\nint diag_release_dci_client(int*);\n\nint diag_send_dci_async_req(int client_id, unsigned char buf[], int bytes, unsigned char *rsp_ptr, int rsp_len,\n                            void (*func_ptr)(unsigned char *ptr, int len, void *data_ptr), void *data_ptr);\n\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "selfdrive/sensord/sensord",
    "content": "#!/bin/sh\ncd \"$(dirname \"$0\")\"\nexport LD_LIBRARY_PATH=\"/system/lib64:$LD_LIBRARY_PATH\"\nexec ./_sensord\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_accel.cc",
    "content": "#include \"bmx055_accel.h\"\n\n#include <cassert>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n\nBMX055_Accel::BMX055_Accel(I2CBus *bus) : I2CSensor(bus) {}\n\nint BMX055_Accel::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret = read_register(BMX055_ACCEL_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != BMX055_ACCEL_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], BMX055_ACCEL_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\n  // High bandwidth\n  // ret = set_register(BMX055_ACCEL_I2C_REG_HBW, BMX055_ACCEL_HBW_ENABLE);\n  // if (ret < 0) {\n  //   goto fail;\n  // }\n\n  // Low bandwidth\n  ret = set_register(BMX055_ACCEL_I2C_REG_HBW, BMX055_ACCEL_HBW_DISABLE);\n  if (ret < 0) {\n    goto fail;\n  }\n  ret = set_register(BMX055_ACCEL_I2C_REG_BW, BMX055_ACCEL_BW_125HZ);\n  if (ret < 0) {\n    goto fail;\n  }\n\nfail:\n  return ret;\n}\n\nvoid BMX055_Accel::get_event(cereal::SensorEventData::Builder &event) {\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[6];\n  int len = read_register(BMX055_ACCEL_I2C_REG_X_LSB, buffer, sizeof(buffer));\n  assert(len == 6);\n\n  // 12 bit = +-2g\n  float scale = 9.81 * 2.0f / (1 << 11);\n  float x = -read_12_bit(buffer[0], buffer[1]) * scale;\n  float y = -read_12_bit(buffer[2], buffer[3]) * scale;\n  float z = read_12_bit(buffer[4], buffer[5]) * scale;\n\n  event.setSource(cereal::SensorEventData::SensorSource::BMX055);\n  event.setVersion(1);\n  event.setSensor(SENSOR_ACCELEROMETER);\n  event.setType(SENSOR_TYPE_ACCELEROMETER);\n  event.setTimestamp(start_time);\n\n  float xyz[] = {x, y, z};\n  auto svec = event.initAcceleration();\n  svec.setV(xyz);\n  svec.setStatus(true);\n\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_accel.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define BMX055_ACCEL_I2C_ADDR       0x18\n\n// Registers of the chip\n#define BMX055_ACCEL_I2C_REG_ID     0x00\n#define BMX055_ACCEL_I2C_REG_X_LSB  0x02\n#define BMX055_ACCEL_I2C_REG_TEMP   0x08\n#define BMX055_ACCEL_I2C_REG_BW     0x10\n#define BMX055_ACCEL_I2C_REG_HBW    0x13\n#define BMX055_ACCEL_I2C_REG_FIFO   0x3F\n\n// Constants\n#define BMX055_ACCEL_CHIP_ID        0xFA\n\n#define BMX055_ACCEL_HBW_ENABLE       0b10000000\n#define BMX055_ACCEL_HBW_DISABLE      0b00000000\n\n#define BMX055_ACCEL_BW_7_81HZ  0b01000\n#define BMX055_ACCEL_BW_15_63HZ 0b01001\n#define BMX055_ACCEL_BW_31_25HZ 0b01010\n#define BMX055_ACCEL_BW_62_5HZ  0b01011\n#define BMX055_ACCEL_BW_125HZ   0b01100\n#define BMX055_ACCEL_BW_250HZ   0b01101\n#define BMX055_ACCEL_BW_500HZ   0b01110\n#define BMX055_ACCEL_BW_1000HZ  0b01111\n\nclass BMX055_Accel : public I2CSensor {\n  uint8_t get_device_address() {return BMX055_ACCEL_I2C_ADDR;}\npublic:\n  BMX055_Accel(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_gyro.cc",
    "content": "#include \"bmx055_gyro.h\"\n\n#include <cassert>\n#include <cmath>\n\n#include \"selfdrive/common/swaglog.h\"\n\n#define DEG2RAD(x) ((x) * M_PI / 180.0)\n\n\nBMX055_Gyro::BMX055_Gyro(I2CBus *bus) : I2CSensor(bus) {}\n\nint BMX055_Gyro::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret =read_register(BMX055_GYRO_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != BMX055_GYRO_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], BMX055_GYRO_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\n  // High bandwidth\n  // ret = set_register(BMX055_GYRO_I2C_REG_HBW, BMX055_GYRO_HBW_ENABLE);\n  // if (ret < 0) {\n  //   goto fail;\n  // }\n\n  // Low bandwidth\n  ret = set_register(BMX055_GYRO_I2C_REG_HBW, BMX055_GYRO_HBW_DISABLE);\n  if (ret < 0) {\n    goto fail;\n  }\n\n  // 116 Hz filter\n  ret = set_register(BMX055_GYRO_I2C_REG_BW, BMX055_GYRO_BW_116HZ);\n  if (ret < 0) {\n    goto fail;\n  }\n\n  // +- 125 deg/s range\n  ret = set_register(BMX055_GYRO_I2C_REG_RANGE, BMX055_GYRO_RANGE_125);\n  if (ret < 0) {\n    goto fail;\n  }\n\nfail:\n  return ret;\n}\n\nvoid BMX055_Gyro::get_event(cereal::SensorEventData::Builder &event) {\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[6];\n  int len = read_register(BMX055_GYRO_I2C_REG_RATE_X_LSB, buffer, sizeof(buffer));\n  assert(len == 6);\n\n  // 16 bit = +- 125 deg/s\n  float scale = 125.0f / (1 << 15);\n  float x = -DEG2RAD(read_16_bit(buffer[0], buffer[1]) * scale);\n  float y = -DEG2RAD(read_16_bit(buffer[2], buffer[3]) * scale);\n  float z = DEG2RAD(read_16_bit(buffer[4], buffer[5]) * scale);\n\n  event.setSource(cereal::SensorEventData::SensorSource::BMX055);\n  event.setVersion(1);\n  event.setSensor(SENSOR_GYRO_UNCALIBRATED);\n  event.setType(SENSOR_TYPE_GYROSCOPE_UNCALIBRATED);\n  event.setTimestamp(start_time);\n\n  float xyz[] = {x, y, z};\n  auto svec = event.initGyroUncalibrated();\n  svec.setV(xyz);\n  svec.setStatus(true);\n\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_gyro.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define BMX055_GYRO_I2C_ADDR        0x68\n\n// Registers of the chip\n#define BMX055_GYRO_I2C_REG_ID         0x00\n#define BMX055_GYRO_I2C_REG_RATE_X_LSB 0x02\n#define BMX055_GYRO_I2C_REG_RANGE      0x0F\n#define BMX055_GYRO_I2C_REG_BW         0x10\n#define BMX055_GYRO_I2C_REG_HBW        0x13\n#define BMX055_GYRO_I2C_REG_FIFO       0x3F\n\n// Constants\n#define BMX055_GYRO_CHIP_ID         0x0F\n\n#define BMX055_GYRO_HBW_ENABLE       0b10000000\n#define BMX055_GYRO_HBW_DISABLE      0b00000000\n\n#define BMX055_GYRO_RANGE_2000      0b000\n#define BMX055_GYRO_RANGE_1000      0b001\n#define BMX055_GYRO_RANGE_500       0b010\n#define BMX055_GYRO_RANGE_250       0b011\n#define BMX055_GYRO_RANGE_125       0b100\n\n#define BMX055_GYRO_BW_116HZ 0b0010\n\n\nclass BMX055_Gyro : public I2CSensor {\n  uint8_t get_device_address() {return BMX055_GYRO_I2C_ADDR;}\npublic:\n  BMX055_Gyro(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_magn.cc",
    "content": "#include \"bmx055_magn.h\"\n\n#include <unistd.h>\n\n#include <algorithm>\n#include <cassert>\n#include <cstdio>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n\nstatic int16_t compensate_x(trim_data_t trim_data, int16_t mag_data_x, uint16_t data_rhall) {\n  uint16_t process_comp_x0 = data_rhall;\n  int32_t process_comp_x1 = ((int32_t)trim_data.dig_xyz1) * 16384;\n  uint16_t process_comp_x2 = ((uint16_t)(process_comp_x1 / process_comp_x0)) - ((uint16_t)0x4000);\n  int16_t retval = ((int16_t)process_comp_x2);\n  int32_t process_comp_x3 = (((int32_t)retval) * ((int32_t)retval));\n  int32_t process_comp_x4 = (((int32_t)trim_data.dig_xy2) * (process_comp_x3 / 128));\n  int32_t process_comp_x5 = (int32_t)(((int16_t)trim_data.dig_xy1) * 128);\n  int32_t process_comp_x6 = ((int32_t)retval) * process_comp_x5;\n  int32_t process_comp_x7 = (((process_comp_x4 + process_comp_x6) / 512) + ((int32_t)0x100000));\n  int32_t process_comp_x8 = ((int32_t)(((int16_t)trim_data.dig_x2) + ((int16_t)0xA0)));\n  int32_t process_comp_x9 = ((process_comp_x7 * process_comp_x8) / 4096);\n  int32_t process_comp_x10 = ((int32_t)mag_data_x) * process_comp_x9;\n  retval = ((int16_t)(process_comp_x10 / 8192));\n  retval = (retval + (((int16_t)trim_data.dig_x1) * 8)) / 16;\n\n  return retval;\n}\n\nstatic int16_t compensate_y(trim_data_t trim_data, int16_t mag_data_y, uint16_t data_rhall) {\n  uint16_t process_comp_y0 = trim_data.dig_xyz1;\n  int32_t process_comp_y1 = (((int32_t)trim_data.dig_xyz1) * 16384) / process_comp_y0;\n  uint16_t process_comp_y2 = ((uint16_t)process_comp_y1) - ((uint16_t)0x4000);\n  int16_t retval = ((int16_t)process_comp_y2);\n  int32_t process_comp_y3 = ((int32_t) retval) * ((int32_t)retval);\n  int32_t process_comp_y4 = ((int32_t)trim_data.dig_xy2) * (process_comp_y3 / 128);\n  int32_t process_comp_y5 = ((int32_t)(((int16_t)trim_data.dig_xy1) * 128));\n  int32_t process_comp_y6 = ((process_comp_y4 + (((int32_t)retval) * process_comp_y5)) / 512);\n  int32_t process_comp_y7 = ((int32_t)(((int16_t)trim_data.dig_y2) + ((int16_t)0xA0)));\n  int32_t process_comp_y8 = (((process_comp_y6 + ((int32_t)0x100000)) * process_comp_y7) / 4096);\n  int32_t process_comp_y9 = (((int32_t)mag_data_y) * process_comp_y8);\n  retval = (int16_t)(process_comp_y9 / 8192);\n  retval = (retval + (((int16_t)trim_data.dig_y1) * 8)) / 16;\n\n  return retval;\n}\n\nstatic int16_t compensate_z(trim_data_t trim_data, int16_t mag_data_z, uint16_t data_rhall) {\n  int16_t process_comp_z0 = ((int16_t)data_rhall) - ((int16_t) trim_data.dig_xyz1);\n  int32_t process_comp_z1 = (((int32_t)trim_data.dig_z3) * ((int32_t)(process_comp_z0))) / 4;\n  int32_t process_comp_z2 = (((int32_t)(mag_data_z - trim_data.dig_z4)) * 32768);\n  int32_t process_comp_z3 = ((int32_t)trim_data.dig_z1) * (((int16_t)data_rhall) * 2);\n  int16_t process_comp_z4 = (int16_t)((process_comp_z3 + (32768)) / 65536);\n  int32_t retval = ((process_comp_z2 - process_comp_z1) / (trim_data.dig_z2 + process_comp_z4));\n\n  /* saturate result to +/- 2 micro-tesla */\n  retval = std::clamp(retval, -32767, 32767);\n\n  /* Conversion of LSB to micro-tesla*/\n  retval = retval / 16;\n\n  return (int16_t)retval;\n}\n\nBMX055_Magn::BMX055_Magn(I2CBus *bus) : I2CSensor(bus) {}\n\nint BMX055_Magn::init() {\n  int ret;\n  uint8_t buffer[1];\n  uint8_t trim_x1y1[2] = {0};\n  uint8_t trim_x2y2[2] = {0};\n  uint8_t trim_xy1xy2[2] = {0};\n  uint8_t trim_z1[2] = {0};\n  uint8_t trim_z2[2] = {0};\n  uint8_t trim_z3[2] = {0};\n  uint8_t trim_z4[2] = {0};\n  uint8_t trim_xyz1[2] = {0};\n\n  // suspend -> sleep\n  ret = set_register(BMX055_MAGN_I2C_REG_PWR_0, 0x01);\n  if(ret < 0) {\n    LOGE(\"Enabling power failed: %d\", ret);\n    goto fail;\n  }\n  util::sleep_for(5); // wait until the chip is powered on\n\n  // read chip ID\n  ret = read_register(BMX055_MAGN_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != BMX055_MAGN_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], BMX055_MAGN_CHIP_ID);\n    return -1;\n  }\n\n  // Load magnetometer trim\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_X1, trim_x1y1, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_X2, trim_x2y2, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_XY2, trim_xy1xy2, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_Z1_LSB, trim_z1, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_Z2_LSB, trim_z2, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_Z3_LSB, trim_z3, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_Z4_LSB, trim_z4, 2);\n  if(ret < 0) goto fail;\n  ret = read_register(BMX055_MAGN_I2C_REG_DIG_XYZ1_LSB, trim_xyz1, 2);\n  if(ret < 0) goto fail;\n\n  // Read trim data\n  trim_data.dig_x1 = trim_x1y1[0];\n  trim_data.dig_y1 = trim_x1y1[1];\n\n  trim_data.dig_x2 = trim_x2y2[0];\n  trim_data.dig_y2 = trim_x2y2[1];\n\n  trim_data.dig_xy1 = trim_xy1xy2[1]; // NB: MSB/LSB swapped\n  trim_data.dig_xy2 = trim_xy1xy2[0];\n\n  trim_data.dig_z1 = read_16_bit(trim_z1[0], trim_z1[1]);\n  trim_data.dig_z2 = read_16_bit(trim_z2[0], trim_z2[1]);\n  trim_data.dig_z3 = read_16_bit(trim_z3[0], trim_z3[1]);\n  trim_data.dig_z4 = read_16_bit(trim_z4[0], trim_z4[1]);\n\n  trim_data.dig_xyz1 = read_16_bit(trim_xyz1[0], trim_xyz1[1] & 0x7f);\n  assert(trim_data.dig_xyz1 != 0);\n\n  perform_self_test();\n\n  // f_max = 1 / (145us * nXY + 500us * NZ + 980us)\n  // Chose NXY = 7, NZ = 12, which gives 125 Hz,\n  // and has the same ratio as the high accuracy preset\n  ret = set_register(BMX055_MAGN_I2C_REG_REPXY, (7 - 1) / 2);\n  if (ret < 0) {\n    goto fail;\n  }\n\n  ret = set_register(BMX055_MAGN_I2C_REG_REPZ, 12 - 1);\n  if (ret < 0) {\n    goto fail;\n  }\n\n\n  return 0;\n\n fail:\n  return ret;\n}\n\nbool BMX055_Magn::perform_self_test() {\n  uint8_t buffer[8];\n  int16_t x, y;\n  int16_t neg_z, pos_z;\n\n  // Increase z reps for less false positives (~30 Hz ODR)\n  set_register(BMX055_MAGN_I2C_REG_REPXY, 1);\n  set_register(BMX055_MAGN_I2C_REG_REPZ, 64 - 1);\n\n  // Clean existing measurement\n  read_register(BMX055_MAGN_I2C_REG_DATAX_LSB, buffer, sizeof(buffer));\n\n  uint8_t forced = BMX055_MAGN_FORCED;\n\n  // Negative current\n\tset_register(BMX055_MAGN_I2C_REG_MAG, forced | (uint8_t(0b10) << 6));\n\tutil::sleep_for(100);\n\n\tread_register(BMX055_MAGN_I2C_REG_DATAX_LSB, buffer, sizeof(buffer));\n\tparse_xyz(buffer, &x, &y, &neg_z);\n\n  // Positive current\n\tset_register(BMX055_MAGN_I2C_REG_MAG, forced | (uint8_t(0b11) << 6));\n\tutil::sleep_for(100);\n\n\tread_register(BMX055_MAGN_I2C_REG_DATAX_LSB, buffer, sizeof(buffer));\n  parse_xyz(buffer, &x, &y, &pos_z);\n\n  // Put back in normal mode\n  set_register(BMX055_MAGN_I2C_REG_MAG, 0);\n\n  int16_t diff = pos_z - neg_z;\n  bool passed = (diff > 180) && (diff < 240);\n\n  if (!passed) {\n    LOGE(\"self test failed: neg %d pos %d diff %d\", neg_z, pos_z, diff);\n  }\n\n  return passed;\n}\n\nbool BMX055_Magn::parse_xyz(uint8_t buffer[8], int16_t *x, int16_t *y, int16_t *z) {\n  bool ready = buffer[6] & 0x1;\n  if (ready) {\n    int16_t mdata_x = (int16_t) (((int16_t)buffer[1] << 8) | buffer[0]) >> 3;\n    int16_t mdata_y = (int16_t) (((int16_t)buffer[3] << 8) | buffer[2]) >> 3;\n    int16_t mdata_z = (int16_t) (((int16_t)buffer[5] << 8) | buffer[4]) >> 1;\n    uint16_t data_r = (uint16_t) (((uint16_t)buffer[7] << 8) | buffer[6]) >> 2;\n    assert(data_r != 0);\n\n\t\t*x = compensate_x(trim_data, mdata_x, data_r);\n\t\t*y = compensate_y(trim_data, mdata_y, data_r);\n\t\t*z = compensate_z(trim_data, mdata_z, data_r);\n  }\n  return ready;\n}\n\n\nvoid BMX055_Magn::get_event(cereal::SensorEventData::Builder &event) {\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[8];\n  int16_t _x, _y, x, y, z;\n\n  int len = read_register(BMX055_MAGN_I2C_REG_DATAX_LSB, buffer, sizeof(buffer));\n  assert(len == sizeof(buffer));\n\n  if (parse_xyz(buffer, &_x, &_y, &z)) {\n    event.setSource(cereal::SensorEventData::SensorSource::BMX055);\n    event.setVersion(2);\n    event.setSensor(SENSOR_MAGNETOMETER_UNCALIBRATED);\n    event.setType(SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED);\n    event.setTimestamp(start_time);\n\n    // Move magnetometer into same reference frame as accel/gryo\n    x = -_y;\n    y = _x;\n\n    // Axis convention\n    x = -x;\n    y = -y;\n\n    float xyz[] = {(float)x, (float)y, (float)z};\n    auto svec = event.initMagneticUncalibrated();\n    svec.setV(xyz);\n    svec.setStatus(true);\n  }\n\n  // The BMX055 Magnetometer has no FIFO mode. Self running mode only goes\n  // up to 30 Hz. Therefore we put in forced mode, and request measurements\n  // at a 100 Hz. When reading the registers we have to check the ready bit\n  // To verify the measurement was completed this cycle.\n  set_register(BMX055_MAGN_I2C_REG_MAG, BMX055_MAGN_FORCED);\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_magn.h",
    "content": "#pragma once\n#include <tuple>\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define BMX055_MAGN_I2C_ADDR        0x10\n\n// Registers of the chip\n#define BMX055_MAGN_I2C_REG_ID        0x40\n#define BMX055_MAGN_I2C_REG_PWR_0     0x4B\n#define BMX055_MAGN_I2C_REG_MAG       0x4C\n#define BMX055_MAGN_I2C_REG_DATAX_LSB 0x42\n#define BMX055_MAGN_I2C_REG_RHALL_LSB 0x48\n#define BMX055_MAGN_I2C_REG_REPXY     0x51\n#define BMX055_MAGN_I2C_REG_REPZ      0x52\n\n#define BMX055_MAGN_I2C_REG_DIG_X1       0x5D\n#define BMX055_MAGN_I2C_REG_DIG_Y1       0x5E\n#define BMX055_MAGN_I2C_REG_DIG_Z4_LSB   0x62\n#define BMX055_MAGN_I2C_REG_DIG_Z4_MSB   0x63\n#define BMX055_MAGN_I2C_REG_DIG_X2       0x64\n#define BMX055_MAGN_I2C_REG_DIG_Y2       0x65\n#define BMX055_MAGN_I2C_REG_DIG_Z2_LSB   0x68\n#define BMX055_MAGN_I2C_REG_DIG_Z2_MSB   0x69\n#define BMX055_MAGN_I2C_REG_DIG_Z1_LSB   0x6A\n#define BMX055_MAGN_I2C_REG_DIG_Z1_MSB   0x6B\n#define BMX055_MAGN_I2C_REG_DIG_XYZ1_LSB 0x6C\n#define BMX055_MAGN_I2C_REG_DIG_XYZ1_MSB 0x6D\n#define BMX055_MAGN_I2C_REG_DIG_Z3_LSB   0x6E\n#define BMX055_MAGN_I2C_REG_DIG_Z3_MSB   0x6F\n#define BMX055_MAGN_I2C_REG_DIG_XY2      0x70\n#define BMX055_MAGN_I2C_REG_DIG_XY1      0x71\n\n// Constants\n#define BMX055_MAGN_CHIP_ID     0x32\n#define BMX055_MAGN_FORCED      (0b01 << 1)\n\nstruct trim_data_t {\n    int8_t dig_x1;\n    int8_t dig_y1;\n    int8_t dig_x2;\n    int8_t dig_y2;\n    uint16_t dig_z1;\n    int16_t dig_z2;\n    int16_t dig_z3;\n    int16_t dig_z4;\n    uint8_t dig_xy1;\n    int8_t dig_xy2;\n    uint16_t dig_xyz1;\n};\n\n\nclass BMX055_Magn : public I2CSensor{\n  uint8_t get_device_address() {return BMX055_MAGN_I2C_ADDR;}\n  trim_data_t trim_data = {0};\n  bool perform_self_test();\n  bool parse_xyz(uint8_t buffer[8], int16_t *x, int16_t *y, int16_t *z);\npublic:\n  BMX055_Magn(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_temp.cc",
    "content": "#include \"bmx055_temp.h\"\n\n#include <cassert>\n\n#include \"selfdrive/sensord/sensors/bmx055_accel.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n\nBMX055_Temp::BMX055_Temp(I2CBus *bus) : I2CSensor(bus) {}\n\nint BMX055_Temp::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret = read_register(BMX055_ACCEL_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != BMX055_ACCEL_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], BMX055_ACCEL_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\nfail:\n  return ret;\n}\n\nvoid BMX055_Temp::get_event(cereal::SensorEventData::Builder &event) {\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[1];\n  int len = read_register(BMX055_ACCEL_I2C_REG_TEMP, buffer, sizeof(buffer));\n  assert(len == sizeof(buffer));\n\n  float temp = 23.0f + int8_t(buffer[0]) / 2.0f;\n\n  event.setSource(cereal::SensorEventData::SensorSource::BMX055);\n  event.setVersion(1);\n  event.setType(SENSOR_TYPE_AMBIENT_TEMPERATURE);\n  event.setTimestamp(start_time);\n  event.setTemperature(temp);\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/bmx055_temp.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/bmx055_accel.h\"\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\nclass BMX055_Temp : public I2CSensor {\n  uint8_t get_device_address() {return BMX055_ACCEL_I2C_ADDR;}\npublic:\n  BMX055_Temp(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/constants.h",
    "content": "#pragma once\n\n\n#define SENSOR_ACCELEROMETER 1\n#define SENSOR_MAGNETOMETER 2\n#define SENSOR_MAGNETOMETER_UNCALIBRATED 3\n#define SENSOR_GYRO 4\n#define SENSOR_GYRO_UNCALIBRATED 5\n#define SENSOR_LIGHT 7\n\n#define SENSOR_TYPE_ACCELEROMETER 1\n#define SENSOR_TYPE_GEOMAGNETIC_FIELD 2\n#define SENSOR_TYPE_GYROSCOPE 4\n#define SENSOR_TYPE_LIGHT 5\n#define SENSOR_TYPE_AMBIENT_TEMPERATURE 13\n#define SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED 14\n#define SENSOR_TYPE_MAGNETIC_FIELD  SENSOR_TYPE_GEOMAGNETIC_FIELD\n#define SENSOR_TYPE_GYROSCOPE_UNCALIBRATED 16\n"
  },
  {
    "path": "selfdrive/sensord/sensors/file_sensor.cc",
    "content": "#include \"file_sensor.h\"\n\n#include <string>\n\nFileSensor::FileSensor(std::string filename) : file(filename) {\n}\n\nint FileSensor::init() {\n  return file.is_open() ? 0 : 1;\n}\n\nFileSensor::~FileSensor() {\n  file.close();\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/file_sensor.h",
    "content": "#pragma once\n\n#include <fstream>\n#include <string>\n\n#include \"cereal/gen/cpp/log.capnp.h\"\n#include \"selfdrive/sensord/sensors/sensor.h\"\n\nclass FileSensor : public Sensor {\nprotected:\n  std::ifstream file;\n\npublic:\n  FileSensor(std::string filename);\n  ~FileSensor();\n  int init();\n  virtual void get_event(cereal::SensorEventData::Builder &event) = 0;\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/i2c_sensor.cc",
    "content": "#include \"i2c_sensor.h\"\n\nint16_t read_12_bit(uint8_t lsb, uint8_t msb) {\n  uint16_t combined = (uint16_t(msb) << 8) | uint16_t(lsb & 0xF0);\n  return int16_t(combined) / (1 << 4);\n}\n\nint16_t read_16_bit(uint8_t lsb, uint8_t msb) {\n  uint16_t combined = (uint16_t(msb) << 8) | uint16_t(lsb);\n  return int16_t(combined);\n}\n\nint32_t read_20_bit(uint8_t b2, uint8_t b1, uint8_t b0) {\n  uint32_t combined = (uint32_t(b0) << 16) | (uint32_t(b1) << 8) | uint32_t(b2);\n  return int32_t(combined) / (1 << 4);\n}\n\n\nI2CSensor::I2CSensor(I2CBus *bus) : bus(bus) {\n}\n\nint I2CSensor::read_register(uint register_address, uint8_t *buffer, uint8_t len) {\n  return bus->read_register(get_device_address(), register_address, buffer, len);\n}\n\nint I2CSensor::set_register(uint register_address, uint8_t data) {\n  return bus->set_register(get_device_address(), register_address, data);\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/i2c_sensor.h",
    "content": "#pragma once\n\n#include <cstdint>\n\n#include \"cereal/gen/cpp/log.capnp.h\"\n#include \"selfdrive/common/i2c.h\"\n#include \"selfdrive/sensord/sensors/constants.h\"\n#include \"selfdrive/sensord/sensors/sensor.h\"\n\nint16_t read_12_bit(uint8_t lsb, uint8_t msb);\nint16_t read_16_bit(uint8_t lsb, uint8_t msb);\nint32_t read_20_bit(uint8_t b2, uint8_t b1, uint8_t b0);\n\n\nclass I2CSensor : public Sensor {\nprivate:\n  I2CBus *bus;\n  virtual uint8_t get_device_address() = 0;\n\npublic:\n  I2CSensor(I2CBus *bus);\n  int read_register(uint register_address, uint8_t *buffer, uint8_t len);\n  int set_register(uint register_address, uint8_t data);\n  virtual int init() = 0;\n  virtual void get_event(cereal::SensorEventData::Builder &event) = 0;\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/light_sensor.cc",
    "content": "#include \"light_sensor.h\"\n\n#include <string>\n\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/sensord/sensors/constants.h\"\n\nvoid LightSensor::get_event(cereal::SensorEventData::Builder &event) {\n  uint64_t start_time = nanos_since_boot();\n  file.clear();\n  file.seekg(0);\n\n  int value;\n  file >> value;\n\n  event.setSource(cereal::SensorEventData::SensorSource::RPR0521);\n  event.setVersion(1);\n  event.setSensor(SENSOR_LIGHT);\n  event.setType(SENSOR_TYPE_LIGHT);\n  event.setTimestamp(start_time);\n  event.setLight(value);\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/light_sensor.h",
    "content": "#pragma once\n#include \"file_sensor.h\"\n\nclass LightSensor : public FileSensor {\npublic:\n  LightSensor(std::string filename) : FileSensor(filename){};\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/lsm6ds3_accel.cc",
    "content": "#include \"lsm6ds3_accel.h\"\n\n#include <cassert>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n\nLSM6DS3_Accel::LSM6DS3_Accel(I2CBus *bus) : I2CSensor(bus) {}\n\nint LSM6DS3_Accel::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret = read_register(LSM6DS3_ACCEL_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != LSM6DS3_ACCEL_CHIP_ID && buffer[0] != LSM6DS3TRC_ACCEL_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], LSM6DS3_ACCEL_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\n  if (buffer[0] == LSM6DS3TRC_ACCEL_CHIP_ID) {\n    source = cereal::SensorEventData::SensorSource::LSM6DS3TRC;\n  }\n\n  // TODO: set scale and bandwith. Default is +- 2G, 50 Hz\n  ret = set_register(LSM6DS3_ACCEL_I2C_REG_CTRL1_XL, LSM6DS3_ACCEL_ODR_104HZ);\n  if (ret < 0) {\n    goto fail;\n  }\n\n\nfail:\n  return ret;\n}\n\nvoid LSM6DS3_Accel::get_event(cereal::SensorEventData::Builder &event) {\n\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[6];\n  int len = read_register(LSM6DS3_ACCEL_I2C_REG_OUTX_L_XL, buffer, sizeof(buffer));\n  assert(len == sizeof(buffer));\n\n  float scale = 9.81 * 2.0f / (1 << 15);\n  float x = read_16_bit(buffer[0], buffer[1]) * scale;\n  float y = read_16_bit(buffer[2], buffer[3]) * scale;\n  float z = read_16_bit(buffer[4], buffer[5]) * scale;\n\n  event.setSource(source);\n  event.setVersion(1);\n  event.setSensor(SENSOR_ACCELEROMETER);\n  event.setType(SENSOR_TYPE_ACCELEROMETER);\n  event.setTimestamp(start_time);\n\n  float xyz[] = {y, -x, z};\n  auto svec = event.initAcceleration();\n  svec.setV(xyz);\n  svec.setStatus(true);\n\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/lsm6ds3_accel.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define LSM6DS3_ACCEL_I2C_ADDR       0x6A\n\n// Registers of the chip\n#define LSM6DS3_ACCEL_I2C_REG_ID        0x0F\n#define LSM6DS3_ACCEL_I2C_REG_CTRL1_XL  0x10\n#define LSM6DS3_ACCEL_I2C_REG_OUTX_L_XL 0x28\n\n// Constants\n#define LSM6DS3_ACCEL_CHIP_ID        0x69\n#define LSM6DS3TRC_ACCEL_CHIP_ID     0x6A\n#define LSM6DS3_ACCEL_ODR_104HZ      (0b0100 << 4)\n\n\nclass LSM6DS3_Accel : public I2CSensor {\n  uint8_t get_device_address() {return LSM6DS3_ACCEL_I2C_ADDR;}\n  cereal::SensorEventData::SensorSource source = cereal::SensorEventData::SensorSource::LSM6DS3;\npublic:\n  LSM6DS3_Accel(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/lsm6ds3_gyro.cc",
    "content": "#include \"lsm6ds3_gyro.h\"\n\n#include <cassert>\n#include <cmath>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n\n#define DEG2RAD(x) ((x) * M_PI / 180.0)\n\n\nLSM6DS3_Gyro::LSM6DS3_Gyro(I2CBus *bus) : I2CSensor(bus) {}\n\nint LSM6DS3_Gyro::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret = read_register(LSM6DS3_GYRO_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != LSM6DS3_GYRO_CHIP_ID && buffer[0] != LSM6DS3TRC_GYRO_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], LSM6DS3_GYRO_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\n  if (buffer[0] == LSM6DS3TRC_GYRO_CHIP_ID) {\n    source = cereal::SensorEventData::SensorSource::LSM6DS3TRC;\n  }\n\n  // TODO: set scale. Default is +- 250 deg/s\n  ret = set_register(LSM6DS3_GYRO_I2C_REG_CTRL2_G, LSM6DS3_GYRO_ODR_104HZ);\n  if (ret < 0) {\n    goto fail;\n  }\n\n\nfail:\n  return ret;\n}\n\nvoid LSM6DS3_Gyro::get_event(cereal::SensorEventData::Builder &event) {\n\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[6];\n  int len = read_register(LSM6DS3_GYRO_I2C_REG_OUTX_L_G, buffer, sizeof(buffer));\n  assert(len == sizeof(buffer));\n\n  float scale = 8.75 / 1000.0;\n  float x = DEG2RAD(read_16_bit(buffer[0], buffer[1]) * scale);\n  float y = DEG2RAD(read_16_bit(buffer[2], buffer[3]) * scale);\n  float z = DEG2RAD(read_16_bit(buffer[4], buffer[5]) * scale);\n\n  event.setSource(source);\n  event.setVersion(2);\n  event.setSensor(SENSOR_GYRO_UNCALIBRATED);\n  event.setType(SENSOR_TYPE_GYROSCOPE_UNCALIBRATED);\n  event.setTimestamp(start_time);\n\n  float xyz[] = {y, -x, z};\n  auto svec = event.initGyroUncalibrated();\n  svec.setV(xyz);\n  svec.setStatus(true);\n\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/lsm6ds3_gyro.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define LSM6DS3_GYRO_I2C_ADDR       0x6A\n\n// Registers of the chip\n#define LSM6DS3_GYRO_I2C_REG_ID        0x0F\n#define LSM6DS3_GYRO_I2C_REG_CTRL2_G   0x11\n#define LSM6DS3_GYRO_I2C_REG_OUTX_L_G  0x22\n\n// Constants\n#define LSM6DS3_GYRO_CHIP_ID        0x69\n#define LSM6DS3TRC_GYRO_CHIP_ID     0x6A\n#define LSM6DS3_GYRO_ODR_104HZ      (0b0100 << 4)\n\n\nclass LSM6DS3_Gyro : public I2CSensor {\n  uint8_t get_device_address() {return LSM6DS3_GYRO_I2C_ADDR;}\n  cereal::SensorEventData::SensorSource source = cereal::SensorEventData::SensorSource::LSM6DS3;\npublic:\n  LSM6DS3_Gyro(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/lsm6ds3_temp.cc",
    "content": "#include \"lsm6ds3_temp.h\"\n\n#include <cassert>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n\nLSM6DS3_Temp::LSM6DS3_Temp(I2CBus *bus) : I2CSensor(bus) {}\n\nint LSM6DS3_Temp::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret = read_register(LSM6DS3_TEMP_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != LSM6DS3_TEMP_CHIP_ID && buffer[0] != LSM6DS3TRC_TEMP_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], LSM6DS3_TEMP_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\n  if (buffer[0] == LSM6DS3TRC_TEMP_CHIP_ID) {\n    source = cereal::SensorEventData::SensorSource::LSM6DS3TRC;\n  }\n\nfail:\n  return ret;\n}\n\nvoid LSM6DS3_Temp::get_event(cereal::SensorEventData::Builder &event) {\n\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[2];\n  int len = read_register(LSM6DS3_TEMP_I2C_REG_OUT_TEMP_L, buffer, sizeof(buffer));\n  assert(len == sizeof(buffer));\n\n  float scale = (source == cereal::SensorEventData::SensorSource::LSM6DS3TRC) ? 256.0f : 16.0f;\n  float temp = 25.0f + read_16_bit(buffer[0], buffer[1]) / scale;\n\n  event.setSource(source);\n  event.setVersion(1);\n  event.setType(SENSOR_TYPE_AMBIENT_TEMPERATURE);\n  event.setTimestamp(start_time);\n  event.setTemperature(temp);\n\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/lsm6ds3_temp.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define LSM6DS3_TEMP_I2C_ADDR       0x6A\n\n// Registers of the chip\n#define LSM6DS3_TEMP_I2C_REG_ID           0x0F\n#define LSM6DS3_TEMP_I2C_REG_OUT_TEMP_L   0x20\n\n// Constants\n#define LSM6DS3_TEMP_CHIP_ID        0x69\n#define LSM6DS3TRC_TEMP_CHIP_ID     0x6A\n\n\nclass LSM6DS3_Temp : public I2CSensor {\n  uint8_t get_device_address() {return LSM6DS3_TEMP_I2C_ADDR;}\n  cereal::SensorEventData::SensorSource source = cereal::SensorEventData::SensorSource::LSM6DS3;\n\npublic:\n  LSM6DS3_Temp(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/mmc5603nj_magn.cc",
    "content": "#include \"mmc5603nj_magn.h\"\n\n#include <cassert>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n\nMMC5603NJ_Magn::MMC5603NJ_Magn(I2CBus *bus) : I2CSensor(bus) {}\n\nint MMC5603NJ_Magn::init() {\n  int ret = 0;\n  uint8_t buffer[1];\n\n  ret = read_register(MMC5603NJ_I2C_REG_ID, buffer, 1);\n  if(ret < 0) {\n    LOGE(\"Reading chip ID failed: %d\", ret);\n    goto fail;\n  }\n\n  if(buffer[0] != MMC5603NJ_CHIP_ID) {\n    LOGE(\"Chip ID wrong. Got: %d, Expected %d\", buffer[0], MMC5603NJ_CHIP_ID);\n    ret = -1;\n    goto fail;\n  }\n\n  // Set 100 Hz\n  ret = set_register(MMC5603NJ_I2C_REG_ODR, 100);\n  if (ret < 0) {\n    goto fail;\n  }\n\n  // Set BW to 0b01 for 1-150 Hz operation\n  ret = set_register(MMC5603NJ_I2C_REG_INTERNAL_1, 0b01);\n  if (ret < 0) {\n    goto fail;\n  }\n\n  // Set compute measurement rate\n  ret = set_register(MMC5603NJ_I2C_REG_INTERNAL_0, MMC5603NJ_CMM_FREQ_EN | MMC5603NJ_AUTO_SR_EN);\n  if (ret < 0) {\n    goto fail;\n  }\n\n  // Enable continuous mode, set every 100 measurements\n  ret = set_register(MMC5603NJ_I2C_REG_INTERNAL_2, MMC5603NJ_CMM_EN | MMC5603NJ_EN_PRD_SET | 0b11);\n  if (ret < 0) {\n    goto fail;\n  }\n\nfail:\n  return ret;\n}\n\nvoid MMC5603NJ_Magn::get_event(cereal::SensorEventData::Builder &event) {\n\n  uint64_t start_time = nanos_since_boot();\n  uint8_t buffer[9];\n  int len = read_register(MMC5603NJ_I2C_REG_XOUT0, buffer, sizeof(buffer));\n  assert(len == sizeof(buffer));\n\n  float scale = 1.0 / 16384.0;\n  float x = read_20_bit(buffer[6], buffer[1], buffer[0]) * scale;\n  float y = read_20_bit(buffer[7], buffer[3], buffer[2]) * scale;\n  float z = read_20_bit(buffer[8], buffer[5], buffer[4]) * scale;\n\n  event.setSource(cereal::SensorEventData::SensorSource::MMC5603NJ);\n  event.setVersion(1);\n  event.setSensor(SENSOR_MAGNETOMETER_UNCALIBRATED);\n  event.setType(SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED);\n  event.setTimestamp(start_time);\n\n  float xyz[] = {x, y, z};\n  auto svec = event.initMagneticUncalibrated();\n  svec.setV(xyz);\n  svec.setStatus(true);\n\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors/mmc5603nj_magn.h",
    "content": "#pragma once\n\n#include \"selfdrive/sensord/sensors/i2c_sensor.h\"\n\n// Address of the chip on the bus\n#define MMC5603NJ_I2C_ADDR       0x30\n\n// Registers of the chip\n#define MMC5603NJ_I2C_REG_XOUT0       0x00\n#define MMC5603NJ_I2C_REG_ODR         0x1A\n#define MMC5603NJ_I2C_REG_INTERNAL_0  0x1B\n#define MMC5603NJ_I2C_REG_INTERNAL_1  0x1C\n#define MMC5603NJ_I2C_REG_INTERNAL_2  0x1D\n#define MMC5603NJ_I2C_REG_ID          0x39\n\n// Constants\n#define MMC5603NJ_CHIP_ID        0x10\n#define MMC5603NJ_CMM_FREQ_EN    (1 << 7)\n#define MMC5603NJ_AUTO_SR_EN     (1 << 5)\n#define MMC5603NJ_CMM_EN         (1 << 4)\n#define MMC5603NJ_EN_PRD_SET     (1 << 3)\n\nclass MMC5603NJ_Magn : public I2CSensor {\n  uint8_t get_device_address() {return MMC5603NJ_I2C_ADDR;}\npublic:\n  MMC5603NJ_Magn(I2CBus *bus);\n  int init();\n  void get_event(cereal::SensorEventData::Builder &event);\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors/sensor.h",
    "content": "#pragma once\n\n#include \"cereal/gen/cpp/log.capnp.h\"\n\nclass Sensor {\npublic:\n  virtual ~Sensor() {};\n  virtual int init() = 0;\n  virtual void get_event(cereal::SensorEventData::Builder &event) = 0;\n};\n"
  },
  {
    "path": "selfdrive/sensord/sensors_qcom.cc",
    "content": "#include <cutils/log.h>\n#include <hardware/sensors.h>\n#include <sys/cdefs.h>\n#include <sys/resource.h>\n#include <sys/time.h>\n#include <sys/types.h>\n#include <unistd.h>\n#include <utils/Timers.h>\n\n#include <cassert>\n#include <cstdint>\n#include <cstdio>\n#include <cstdlib>\n#include <cstring>\n#include <map>\n#include <set>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n\n// ACCELEROMETER_UNCALIBRATED is only in Android O\n// https://developer.android.com/reference/android/hardware/Sensor.html#STRING_TYPE_ACCELEROMETER_UNCALIBRATED\n\n#define SENSOR_ACCELEROMETER 1\n#define SENSOR_MAGNETOMETER 2\n#define SENSOR_GYRO 4\n#define SENSOR_MAGNETOMETER_UNCALIBRATED 3\n#define SENSOR_GYRO_UNCALIBRATED 5\n#define SENSOR_PROXIMITY 6\n#define SENSOR_LIGHT 7\n\nExitHandler do_exit;\nvolatile sig_atomic_t re_init_sensors = 0;\n\nnamespace {\n\nvoid sigpipe_handler(int sig) {\n  LOGE(\"SIGPIPE received\");\n  re_init_sensors = true;\n}\n\nvoid sensor_loop() {\n  LOG(\"*** sensor loop\");\n\n  uint64_t frame = 0;\n  bool low_power_mode = false;\n\n  while (!do_exit) {\n    SubMaster sm({\"deviceState\"});\n    PubMaster pm({\"sensorEvents\"});\n\n    struct sensors_poll_device_t* device;\n    struct sensors_module_t* module;\n\n    hw_get_module(SENSORS_HARDWARE_MODULE_ID, (hw_module_t const**)&module);\n    sensors_open(&module->common, &device);\n\n    // required\n    struct sensor_t const* list;\n    int count = module->get_sensors_list(module, &list);\n    LOG(\"%d sensors found\", count);\n\n    if (getenv(\"SENSOR_TEST\")) {\n      exit(count);\n    }\n\n    for (int i = 0; i < count; i++) {\n      LOGD(\"sensor %4d: %4d %60s  %d-%ld us\", i, list[i].handle, list[i].name, list[i].minDelay, list[i].maxDelay);\n    }\n\n    std::set<int> sensor_types = {\n      SENSOR_TYPE_ACCELEROMETER,\n      SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED,\n      SENSOR_TYPE_MAGNETIC_FIELD,\n      SENSOR_TYPE_GYROSCOPE_UNCALIBRATED,\n      SENSOR_TYPE_GYROSCOPE,\n      SENSOR_TYPE_PROXIMITY,\n      SENSOR_TYPE_LIGHT,\n    };\n\n    std::map<int, int64_t> sensors = {\n      {SENSOR_GYRO_UNCALIBRATED, ms2ns(10)},\n      {SENSOR_MAGNETOMETER_UNCALIBRATED, ms2ns(100)},\n      {SENSOR_ACCELEROMETER, ms2ns(10)},\n      {SENSOR_GYRO, ms2ns(10)},\n      {SENSOR_MAGNETOMETER, ms2ns(100)},\n      {SENSOR_PROXIMITY, ms2ns(100)},\n      {SENSOR_LIGHT, ms2ns(100)}\n    };\n\n    // sensors needed while offroad\n    std::set<int> offroad_sensors = {\n      SENSOR_LIGHT,\n      SENSOR_ACCELEROMETER,\n      SENSOR_GYRO_UNCALIBRATED,\n    };\n\n    // init all the sensors\n    for (auto &s : sensors) {\n      device->activate(device, s.first, 0);\n      device->activate(device, s.first, 1);\n      device->setDelay(device, s.first, s.second);\n    }\n\n    // TODO: why is this 16?\n    static const size_t numEvents = 16;\n    sensors_event_t buffer[numEvents];\n\n    while (!do_exit) {\n      int n = device->poll(device, buffer, numEvents);\n      if (n == 0) continue;\n      if (n < 0) {\n        LOG(\"sensor_loop poll failed: %d\", n);\n        continue;\n      }\n\n      int log_events = 0;\n      for (int i=0; i < n; i++) {\n        if (sensor_types.find(buffer[i].type) != sensor_types.end()) {\n          log_events++;\n        }\n      }\n\n      MessageBuilder msg;\n      auto sensor_events = msg.initEvent().initSensorEvents(log_events);\n\n      int log_i = 0;\n      for (int i = 0; i < n; i++) {\n\n        const sensors_event_t& data = buffer[i];\n\n        if (sensor_types.find(data.type) == sensor_types.end()) {\n          continue;\n        }\n\n        auto log_event = sensor_events[log_i];\n        log_event.setSource(cereal::SensorEventData::SensorSource::ANDROID);\n        log_event.setVersion(data.version);\n        log_event.setSensor(data.sensor);\n        log_event.setType(data.type);\n        log_event.setTimestamp(data.timestamp);\n\n        switch (data.type) {\n        case SENSOR_TYPE_ACCELEROMETER: {\n          auto svec = log_event.initAcceleration();\n          svec.setV(data.acceleration.v);\n          svec.setStatus(data.acceleration.status);\n          break;\n        }\n        case SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED: {\n          auto svec = log_event.initMagneticUncalibrated();\n          // assuming the uncalib and bias floats are contiguous in memory\n          kj::ArrayPtr<const float> vs(&data.uncalibrated_magnetic.uncalib[0], 6);\n          svec.setV(vs);\n          break;\n        }\n        case SENSOR_TYPE_MAGNETIC_FIELD: {\n          auto svec = log_event.initMagnetic();\n          svec.setV(data.magnetic.v);\n          svec.setStatus(data.magnetic.status);\n          break;\n        }\n        case SENSOR_TYPE_GYROSCOPE_UNCALIBRATED: {\n          auto svec = log_event.initGyroUncalibrated();\n          // assuming the uncalib and bias floats are contiguous in memory\n          kj::ArrayPtr<const float> vs(&data.uncalibrated_gyro.uncalib[0], 6);\n          svec.setV(vs);\n          break;\n        }\n        case SENSOR_TYPE_GYROSCOPE: {\n          auto svec = log_event.initGyro();\n          svec.setV(data.gyro.v);\n          svec.setStatus(data.gyro.status);\n          break;\n        }\n        case SENSOR_TYPE_PROXIMITY: {\n          log_event.setProximity(data.distance);\n          break;\n        }\n        case SENSOR_TYPE_LIGHT:\n          log_event.setLight(data.light);\n          break;\n        }\n\n        log_i++;\n      }\n\n      pm.send(\"sensorEvents\", msg);\n\n      if (re_init_sensors) {\n        LOGE(\"Resetting sensors\");\n        re_init_sensors = false;\n        break;\n      }\n\n      // Check whether to go into low power mode at 5Hz\n      if (frame % 20 == 0) {\n        sm.update(0);\n        bool offroad = !sm[\"deviceState\"].getDeviceState().getStarted();\n        if (low_power_mode != offroad) {\n          for (auto &s : sensors) {\n            device->activate(device, s.first, 0);\n            if (!offroad || offroad_sensors.find(s.first) != offroad_sensors.end()) {\n              device->activate(device, s.first, 1);\n            }\n          }\n          low_power_mode = offroad;\n        }\n      }\n\n      frame++;\n    }\n    sensors_close(device);\n  }\n}\n\n}// Namespace end\n\nint main(int argc, char *argv[]) {\n  setpriority(PRIO_PROCESS, 0, -18);\n  signal(SIGPIPE, (sighandler_t)sigpipe_handler);\n\n  sensor_loop();\n\n  return 0;\n}\n"
  },
  {
    "path": "selfdrive/sensord/sensors_qcom2.cc",
    "content": "#include <sys/resource.h>\n\n#include <chrono>\n#include <thread>\n#include <vector>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/i2c.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/sensord/sensors/bmx055_accel.h\"\n#include \"selfdrive/sensord/sensors/bmx055_gyro.h\"\n#include \"selfdrive/sensord/sensors/bmx055_magn.h\"\n#include \"selfdrive/sensord/sensors/bmx055_temp.h\"\n#include \"selfdrive/sensord/sensors/constants.h\"\n#include \"selfdrive/sensord/sensors/light_sensor.h\"\n#include \"selfdrive/sensord/sensors/lsm6ds3_accel.h\"\n#include \"selfdrive/sensord/sensors/lsm6ds3_gyro.h\"\n#include \"selfdrive/sensord/sensors/lsm6ds3_temp.h\"\n#include \"selfdrive/sensord/sensors/mmc5603nj_magn.h\"\n#include \"selfdrive/sensord/sensors/sensor.h\"\n\n#define I2C_BUS_IMU 1\n\nExitHandler do_exit;\n\nint sensor_loop() {\n  I2CBus *i2c_bus_imu;\n\n  try {\n    i2c_bus_imu = new I2CBus(I2C_BUS_IMU);\n  } catch (std::exception &e) {\n    LOGE(\"I2CBus init failed\");\n    return -1;\n  }\n\n  BMX055_Accel bmx055_accel(i2c_bus_imu);\n  BMX055_Gyro bmx055_gyro(i2c_bus_imu);\n  BMX055_Magn bmx055_magn(i2c_bus_imu);\n  BMX055_Temp bmx055_temp(i2c_bus_imu);\n\n  LSM6DS3_Accel lsm6ds3_accel(i2c_bus_imu);\n  LSM6DS3_Gyro lsm6ds3_gyro(i2c_bus_imu);\n  LSM6DS3_Temp lsm6ds3_temp(i2c_bus_imu);\n\n  MMC5603NJ_Magn mmc5603nj_magn(i2c_bus_imu);\n\n  LightSensor light(\"/sys/class/i2c-adapter/i2c-2/2-0038/iio:device1/in_intensity_both_raw\");\n\n  // Sensor init\n  std::vector<std::pair<Sensor *, bool>> sensors_init; // Sensor, required\n  sensors_init.push_back({&bmx055_accel, true});\n  sensors_init.push_back({&bmx055_gyro, true});\n  sensors_init.push_back({&bmx055_magn, true});\n  sensors_init.push_back({&bmx055_temp, true});\n\n  sensors_init.push_back({&lsm6ds3_accel, true});\n  sensors_init.push_back({&lsm6ds3_gyro, true});\n  sensors_init.push_back({&lsm6ds3_temp, true});\n\n  sensors_init.push_back({&mmc5603nj_magn, false});\n\n  sensors_init.push_back({&light, true});\n\n\n  // Initialize sensors\n  std::vector<Sensor *> sensors;\n  for (auto &sensor : sensors_init) {\n    int err = sensor.first->init();\n    if (err < 0) {\n      // Fail on required sensors\n      if (sensor.second) {\n        LOGE(\"Error initializing sensors\");\n        return -1;\n      }\n    } else {\n      sensors.push_back(sensor.first);\n    }\n  }\n\n  PubMaster pm({\"sensorEvents\"});\n\n  while (!do_exit) {\n    std::chrono::steady_clock::time_point begin = std::chrono::steady_clock::now();\n\n    const int num_events = sensors.size();\n    MessageBuilder msg;\n    auto sensor_events = msg.initEvent().initSensorEvents(num_events);\n\n    for (int i = 0; i < num_events; i++) {\n      auto event = sensor_events[i];\n      sensors[i]->get_event(event);\n    }\n\n    pm.send(\"sensorEvents\", msg);\n\n    std::chrono::steady_clock::time_point end = std::chrono::steady_clock::now();\n    std::this_thread::sleep_for(std::chrono::milliseconds(10) - (end - begin));\n  }\n  return 0;\n}\n\nint main(int argc, char *argv[]) {\n  setpriority(PRIO_PROCESS, 0, -18);\n  return sensor_loop();\n}\n"
  },
  {
    "path": "selfdrive/swaglog.py",
    "content": "import logging\nimport os\nimport time\nfrom pathlib import Path\nfrom logging.handlers import BaseRotatingHandler\n\nimport zmq\n\nfrom common.logging_extra import SwagLogger, SwagFormatter, SwagLogFileFormatter\nfrom selfdrive.hardware import PC\n\nif PC:\n  SWAGLOG_DIR = os.path.join(str(Path.home()), \".comma\", \"log\")\nelse:\n  SWAGLOG_DIR = \"/data/log/\"\n\ndef get_file_handler():\n  Path(SWAGLOG_DIR).mkdir(parents=True, exist_ok=True)\n  base_filename = os.path.join(SWAGLOG_DIR, \"swaglog\")\n  handler = SwaglogRotatingFileHandler(base_filename)\n  return handler\n\nclass SwaglogRotatingFileHandler(BaseRotatingHandler):\n  def __init__(self, base_filename, interval=60, max_bytes=1024*256, backup_count=2500, encoding=None):\n    super().__init__(base_filename, mode=\"a\", encoding=encoding, delay=True)\n    self.base_filename = base_filename\n    self.interval = interval # seconds\n    self.max_bytes = max_bytes\n    self.backup_count = backup_count\n    self.log_files = self.get_existing_logfiles()\n    log_indexes = [f.split(\".\")[-1] for f in self.log_files]\n    self.last_file_idx = max([int(i) for i in log_indexes if i.isdigit()] or [-1])\n    self.last_rollover = None\n    self.doRollover()\n\n  def _open(self):\n    self.last_rollover = time.monotonic()\n    self.last_file_idx += 1\n    next_filename = f\"{self.base_filename}.{self.last_file_idx:010}\"\n    stream = open(next_filename, self.mode, encoding=self.encoding)\n    self.log_files.insert(0, next_filename)\n    return stream\n\n  def get_existing_logfiles(self):\n    log_files = list()\n    base_dir = os.path.dirname(self.base_filename)\n    for fn in os.listdir(base_dir):\n      fp = os.path.join(base_dir, fn)\n      if fp.startswith(self.base_filename) and os.path.isfile(fp):\n        log_files.append(fp)\n    return sorted(log_files)\n\n  def shouldRollover(self, record):\n    size_exceeded = self.max_bytes > 0 and self.stream.tell() >= self.max_bytes\n    time_exceeded = self.interval > 0 and self.last_rollover + self.interval <= time.monotonic()\n    return size_exceeded or time_exceeded\n\n  def doRollover(self):\n    if self.stream:\n      self.stream.close()\n    self.stream = self._open()\n\n    if self.backup_count > 0:\n      while len(self.log_files) > self.backup_count:\n        to_delete = self.log_files.pop()\n        if os.path.exists(to_delete): # just being safe, should always exist\n          os.remove(to_delete)\n\nclass UnixDomainSocketHandler(logging.Handler):\n  def __init__(self, formatter):\n    logging.Handler.__init__(self)\n    self.setFormatter(formatter)\n    self.pid = None\n\n  def connect(self):\n    self.zctx = zmq.Context()\n    self.sock = self.zctx.socket(zmq.PUSH)\n    self.sock.setsockopt(zmq.LINGER, 10)\n    self.sock.connect(\"ipc:///tmp/logmessage\")\n    self.pid = os.getpid()\n\n  def emit(self, record):\n    if os.getpid() != self.pid:\n      self.connect()\n\n    msg = self.format(record).rstrip('\\n')\n    # print(\"SEND\".format(repr(msg)))\n    try:\n      s = chr(record.levelno)+msg\n      self.sock.send(s.encode('utf8'), zmq.NOBLOCK)\n    except zmq.error.Again:\n      # drop :/\n      pass\n\n\ndef add_file_handler(log):\n  \"\"\"\n  Function to add the file log handler to swaglog.\n  This can be used to store logs when logmessaged is not running.\n  \"\"\"\n  handler = get_file_handler()\n  handler.setFormatter(SwagLogFileFormatter(log))\n  log.addHandler(handler)\n\n\ncloudlog = log = SwagLogger()\nlog.setLevel(logging.DEBUG)\n\nouthandler = logging.StreamHandler()\nlog.addHandler(outhandler)\n# logs are sent through IPC before writing to disk to prevent disk I/O blocking\nlog.addHandler(UnixDomainSocketHandler(SwagFormatter(log)))\n"
  },
  {
    "path": "selfdrive/test/__init__.py",
    "content": ""
  },
  {
    "path": "selfdrive/test/helpers.py",
    "content": "import time\nfrom functools import wraps\nfrom nose.tools import nottest\n\nfrom selfdrive.hardware import PC\nfrom selfdrive.version import training_version, terms_version\nfrom selfdrive.manager.process_config import managed_processes\n\n\ndef set_params_enabled():\n  from common.params import Params\n  params = Params()\n  params.put(\"HasAcceptedTerms\", terms_version)\n  params.put(\"CompletedTrainingVersion\", training_version)\n  params.put_bool(\"OpenpilotEnabledToggle\", True)\n  params.put_bool(\"CommunityFeaturesToggle\", True)\n  params.put_bool(\"Passive\", False)\n\n\ndef phone_only(x):\n  if PC:\n    return nottest(x)\n  else:\n    return x\n\n\ndef with_processes(processes, init_time=0, ignore_stopped=None):\n  ignore_stopped = [] if ignore_stopped is None else ignore_stopped\n\n  def wrapper(func):\n    @wraps(func)\n    def wrap(*args, **kwargs):\n      # start and assert started\n      for n, p in enumerate(processes):\n        managed_processes[p].start()\n        if n < len(processes) - 1:\n          time.sleep(init_time)\n      assert all(managed_processes[name].proc.exitcode is None for name in processes)\n\n      # call the function\n      try:\n        func(*args, **kwargs)\n        # assert processes are still started\n        assert all(managed_processes[name].proc.exitcode is None for name in processes if name not in ignore_stopped)\n      finally:\n        for p in processes:\n          managed_processes[p].stop()\n\n    return wrap\n  return wrapper\n"
  },
  {
    "path": "selfdrive/test/setup_device_ci.sh",
    "content": "#!/usr/bin/bash -e\n\nif [ -z \"$SOURCE_DIR\" ]; then\n  echo \"SOURCE_DIR must be set\"\n  exit 1\nfi\n\nif [ -z \"$GIT_COMMIT\" ]; then\n  echo \"GIT_COMMIT must be set\"\n  exit 1\nfi\n\nif [ -z \"$TEST_DIR\" ]; then\n  echo \"TEST_DIR must be set\"\n  exit 1\nfi\n\numount /data/safe_staging/merged/ || true\nsudo umount /data/safe_staging/merged/ || true\n\nif [ -f \"/EON\" ]; then\n  rm -rf /data/core\n  rm -rf /data/neoupdate\n  rm -rf /data/safe_staging\nfi\n\n# set up environment\ncd $SOURCE_DIR\ngit reset --hard\ngit fetch\nfind . -maxdepth 1 -not -path './.git' -not -name '.' -not -name '..' -exec rm -rf '{}' \\;\ngit fetch --verbose origin $GIT_COMMIT\ngit reset --hard $GIT_COMMIT\ngit checkout $GIT_COMMIT\ngit clean -xdf\ngit submodule update --init --recursive\ngit submodule foreach --recursive \"git reset --hard && git clean -xdf\"\n\necho \"git checkout done, t=$SECONDS\"\n\nrsync -a --delete $SOURCE_DIR $TEST_DIR\n\necho \"$TEST_DIR synced with $GIT_COMMIT, t=$SECONDS\"\n"
  },
  {
    "path": "selfdrive/test/test_fingerprints.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport sys\nfrom common.basedir import BASEDIR\n\n# messages reserved for CAN based ignition (see can_ignition_hook function in panda/board/drivers/can)\n# (addr, len)\nCAN_IGNITION_MSGS = {\n  'gm': [(0x1F1, 8), (0x160, 5)],\n  #'tesla' : [(0x348, 8)],\n}\n\ndef _get_fingerprints():\n  # read all the folders in selfdrive/car and return a dict where:\n  # - keys are all the car names that which we have a fingerprint dict for\n  # - values are dicts of fingeprints for each trim\n  fingerprints = {}\n  for car_folder in [x[0] for x in os.walk(BASEDIR + '/selfdrive/car')]:\n    car_name = car_folder.split('/')[-1]\n    try:\n      fingerprints[car_name] = __import__('selfdrive.car.%s.values' % car_name, fromlist=['FINGERPRINTS']).FINGERPRINTS\n    except (ImportError, IOError, AttributeError):\n      pass\n\n  return fingerprints\n\n\ndef check_fingerprint_consistency(f1, f2):\n  # return false if it finds a fingerprint fully included in another\n  # max message worth checking is 1800, as above that they usually come too infrequently and not\n  # usable for fingerprinting\n\n  max_msg = 1800\n\n  is_f1_in_f2 = True\n  for k in f1:\n    if (k not in f2 or f1[k] != f2[k]) and k < max_msg:\n       is_f1_in_f2 = False\n\n  is_f2_in_f1 = True\n  for k in f2:\n    if (k not in f1 or f2[k] != f1[k]) and k < max_msg:\n       is_f2_in_f1 = False\n\n  return not is_f1_in_f2 and not is_f2_in_f1\n\n\ndef check_can_ignition_conflicts(fingerprints, brands):\n  # loops through all the fingerprints and exits if CAN ignition dedicated messages\n  # are found in unexpected fingerprints\n\n  for brand_can, msgs_can in CAN_IGNITION_MSGS.items():\n    for i, f in enumerate(fingerprints):\n      for msg_can in msgs_can:\n        if brand_can != brands[i] and msg_can[0] in f and msg_can[1] == f[msg_can[0]]:\n          print(\"CAN ignition dedicated msg %d with len %d found in %s fingerprints!\" % (msg_can[0], msg_can[1], brands[i]))\n          print(\"TEST FAILED\")\n          sys.exit(1)\n\n\nfingerprints = _get_fingerprints()\n\nfingerprints_flat = []\ncar_names = []\nbrand_names = []\nfor brand in fingerprints:\n  for car in fingerprints[brand]:\n    fingerprints_flat += fingerprints[brand][car]\n    for i in range(len(fingerprints[brand][car])):\n      car_names.append(car)\n      brand_names.append(brand)\n\n# first check if CAN ignition specific messages are unexpectedly included in other fingerprints\ncheck_can_ignition_conflicts(fingerprints_flat, brand_names)\n\nvalid = True\nfor idx1, f1 in enumerate(fingerprints_flat):\n  for idx2, f2 in enumerate(fingerprints_flat):\n    if idx1 < idx2 and not check_fingerprint_consistency(f1, f2):\n      valid = False\n      print(\"Those two fingerprints are inconsistent {0} {1}\".format(car_names[idx1], car_names[idx2]))\n      print(\"\")\n      print(', '.join(\"%d: %d\" % v for v in sorted(f1.items())))\n      print(\"\")\n      print(', '.join(\"%d: %d\" % v for v in sorted(f2.items())))\n      print(\"\")\n\nprint(\"Found {0} individual fingerprints\".format(len(fingerprints_flat)))\nif not valid or len(fingerprints_flat) == 0:\n  print(\"TEST FAILED\")\n  sys.exit(1)\nelse:\n  print(\"TEST SUCESSFUL\")\n"
  },
  {
    "path": "selfdrive/test/test_onroad.py",
    "content": "#!/usr/bin/env python3\nimport json\nimport os\nimport subprocess\nimport time\nimport numpy as np\nimport unittest\nfrom collections import Counter\nfrom pathlib import Path\n\nimport cereal.messaging as messaging\nfrom cereal.services import service_list\nfrom common.basedir import BASEDIR\nfrom common.timeout import Timeout\nfrom common.params import Params\nfrom selfdrive.hardware import EON, TICI\nfrom selfdrive.loggerd.config import ROOT\nfrom selfdrive.test.helpers import set_params_enabled\nfrom tools.lib.logreader import LogReader\n\n# Baseline CPU usage by process\nPROCS = {\n  \"selfdrive.controls.controlsd\": 50.0,\n  \"./loggerd\": 45.0,\n  \"./locationd\": 9.1,\n  \"selfdrive.controls.plannerd\": 20.0,\n  \"./_ui\": 15.0,\n  \"selfdrive.locationd.paramsd\": 9.1,\n  \"./camerad\": 7.07,\n  \"./_sensord\": 6.17,\n  \"selfdrive.controls.radard\": 5.67,\n  \"./_modeld\": 4.48,\n  \"./boardd\": 3.63,\n  \"./_dmonitoringmodeld\": 2.67,\n  \"selfdrive.thermald.thermald\": 2.41,\n  \"selfdrive.locationd.calibrationd\": 2.0,\n  \"./_soundd\": 2.0,\n  \"selfdrive.monitoring.dmonitoringd\": 1.90,\n  \"./proclogd\": 1.54,\n  \"selfdrive.logmessaged\": 0.2,\n  \"./clocksd\": 0.02,\n  \"./ubloxd\": 0.02,\n  \"selfdrive.tombstoned\": 0,\n  \"./logcatd\": 0,\n}\n\nif EON:\n  PROCS.update({\n    \"selfdrive.hardware.eon.androidd\": 0.4,\n  })\n\nif TICI:\n  PROCS.update({\n    \"./loggerd\": 60.0,\n    \"selfdrive.controls.controlsd\": 28.0,\n    \"./camerad\": 31.0,\n    \"./_ui\": 21.0,\n    \"selfdrive.controls.plannerd\": 12.0,\n    \"selfdrive.locationd.paramsd\": 5.0,\n    \"./_dmonitoringmodeld\": 10.0,\n    \"selfdrive.thermald.thermald\": 1.5,\n  })\n\n\ndef cputime_total(ct):\n  return ct.cpuUser + ct.cpuSystem + ct.cpuChildrenUser + ct.cpuChildrenSystem\n\n\ndef check_cpu_usage(first_proc, last_proc):\n  result =  \"------------------------------------------------\\n\"\n  result += \"------------------ CPU Usage -------------------\\n\"\n  result += \"------------------------------------------------\\n\"\n\n  r = True\n  dt = (last_proc.logMonoTime - first_proc.logMonoTime) / 1e9\n  for proc_name, normal_cpu_usage in PROCS.items():\n    first, last = None, None\n    try:\n      first = [p for p in first_proc.procLog.procs if proc_name in p.cmdline][0]\n      last = [p for p in last_proc.procLog.procs if proc_name in p.cmdline][0]\n      cpu_time = cputime_total(last) - cputime_total(first)\n      cpu_usage = cpu_time / dt * 100.\n      if cpu_usage > max(normal_cpu_usage * 1.15, normal_cpu_usage + 5.0):\n        # cpu usage is high while playing sounds\n        if proc_name == \"./_soundd\" and cpu_usage < 25.:\n          continue\n        result += f\"Warning {proc_name} using more CPU than normal\\n\"\n        r = False\n      elif cpu_usage < min(normal_cpu_usage * 0.65, max(normal_cpu_usage - 1.0, 0.0)):\n        result += f\"Warning {proc_name} using less CPU than normal\\n\"\n        r = False\n      result += f\"{proc_name.ljust(35)}  {cpu_usage:.2f}%\\n\"\n    except IndexError:\n      result += f\"{proc_name.ljust(35)}  NO METRICS FOUND {first=} {last=}\\n\"\n      r = False\n  result += \"------------------------------------------------\\n\"\n  print(result)\n  return r\n\n\nclass TestOnroad(unittest.TestCase):\n\n  @classmethod\n  def setUpClass(cls):\n    os.environ['SKIP_FW_QUERY'] = \"1\"\n    os.environ['FINGERPRINT'] = \"TOYOTA COROLLA TSS2 2019\"\n    set_params_enabled()\n\n    # Make sure athena isn't running\n    Params().delete(\"DongleId\")\n    Params().delete(\"AthenadPid\")\n    os.system(\"pkill -9 -f athena\")\n\n    logger_root = Path(ROOT)\n    initial_segments = set()\n    if logger_root.exists():\n      initial_segments = set(Path(ROOT).iterdir())\n\n    # start manager and run openpilot for a minute\n    try:\n      manager_path = os.path.join(BASEDIR, \"selfdrive/manager/manager.py\")\n      proc = subprocess.Popen([\"python\", manager_path])\n\n      sm = messaging.SubMaster(['carState'])\n      with Timeout(150, \"controls didn't start\"):\n        while sm.rcv_frame['carState'] < 0:\n          sm.update(1000)\n\n      # make sure we get at least two full segments\n      cls.segments = []\n      with Timeout(300, \"timed out waiting for logs\"):\n        while len(cls.segments) < 3:\n          new_paths = set()\n          if logger_root.exists():\n            new_paths = set(logger_root.iterdir()) - initial_segments\n          segs = [p for p in new_paths if \"--\" in str(p)]\n          cls.segments = sorted(segs, key=lambda s: int(str(s).rsplit('--')[-1]))\n          time.sleep(5)\n\n    finally:\n      proc.terminate()\n      if proc.wait(60) is None:\n        proc.kill()\n\n    cls.lr = list(LogReader(os.path.join(str(cls.segments[1]), \"rlog.bz2\")))\n\n  def test_cloudlog_size(self):\n    msgs = [m for m in self.lr if m.which() == 'logMessage']\n\n    total_size = sum(len(m.as_builder().to_bytes()) for m in msgs)\n    self.assertLess(total_size, 3.5e5)\n\n    cnt = Counter([json.loads(m.logMessage)['filename'] for m in msgs])\n    big_logs = [f for f, n in cnt.most_common(3) if n / sum(cnt.values()) > 30.]\n    self.assertEqual(len(big_logs), 0, f\"Log spam: {big_logs}\")\n\n  def test_cpu_usage(self):\n    proclogs = [m for m in self.lr if m.which() == 'procLog']\n    self.assertGreater(len(proclogs), service_list['procLog'].frequency * 45, \"insufficient samples\")\n    cpu_ok = check_cpu_usage(proclogs[0], proclogs[-1])\n    self.assertTrue(cpu_ok)\n\n  def test_model_timings(self):\n    #TODO this went up when plannerd cpu usage increased, why?\n    cfgs = [(\"modelV2\", 0.038, 0.036), (\"driverState\", 0.028, 0.026)]\n    for (s, instant_max, avg_max) in cfgs:\n      ts = [getattr(getattr(m, s), \"modelExecutionTime\") for m in self.lr if m.which() == s]\n      self.assertLess(min(ts), instant_max, f\"high '{s}' execution time: {min(ts)}\")\n      self.assertLess(np.mean(ts), avg_max, f\"high avg '{s}' execution time: {np.mean(ts)}\")\n\nif __name__ == \"__main__\":\n  unittest.main()\n"
  },
  {
    "path": "selfdrive/thermald/power_monitoring.py",
    "content": "import random\nimport threading\nimport time\nfrom statistics import mean\n\nfrom cereal import log\nfrom common.params import Params, put_nonblocking\nfrom common.realtime import sec_since_boot\nfrom selfdrive.hardware import HARDWARE\nfrom selfdrive.swaglog import cloudlog\n\nCAR_VOLTAGE_LOW_PASS_K = 0.091 # LPF gain for 5s tau (dt/tau / (dt/tau + 1))\n\n# A C2 uses about 1W while idling, and 30h seens like a good shutoff for most cars\n# While driving, a battery charges completely in about 30-60 minutes\nCAR_BATTERY_CAPACITY_uWh = 30e6\nCAR_CHARGING_RATE_W = 45\n\nVBATT_PAUSE_CHARGING = 11.0           # Lower limit on the LPF car battery voltage\nVBATT_INSTANT_PAUSE_CHARGING = 7.0    # Lower limit on the instant car battery voltage measurements to avoid triggering on instant power loss\nMAX_TIME_OFFROAD_S = 30*3600\nMIN_ON_TIME_S = 3600\n\nclass PowerMonitoring:\n  def __init__(self):\n    self.params = Params()\n    self.last_measurement_time = None           # Used for integration delta\n    self.last_save_time = 0                     # Used for saving current value in a param\n    self.power_used_uWh = 0                     # Integrated power usage in uWh since going into offroad\n    self.next_pulsed_measurement_time = None\n    self.car_voltage_mV = 12e3                  # Low-passed version of pandaState voltage\n    self.car_voltage_instant_mV = 12e3          # Last value of pandaState voltage\n    self.integration_lock = threading.Lock()\n\n    car_battery_capacity_uWh = self.params.get(\"CarBatteryCapacity\")\n    if car_battery_capacity_uWh is None:\n      car_battery_capacity_uWh = 0\n\n    # Reset capacity if it's low\n    self.car_battery_capacity_uWh = max((CAR_BATTERY_CAPACITY_uWh / 10), int(car_battery_capacity_uWh))\n\n\n  # Calculation tick\n  def calculate(self, pandaState):\n    try:\n      now = sec_since_boot()\n\n      # If pandaState is None, we're probably not in a car, so we don't care\n      if pandaState is None or pandaState.pandaState.pandaType == log.PandaState.PandaType.unknown:\n        with self.integration_lock:\n          self.last_measurement_time = None\n          self.next_pulsed_measurement_time = None\n          self.power_used_uWh = 0\n        return\n\n      # Low-pass battery voltage\n      self.car_voltage_instant_mV = pandaState.pandaState.voltage\n      self.car_voltage_mV = ((pandaState.pandaState.voltage * CAR_VOLTAGE_LOW_PASS_K) + (self.car_voltage_mV * (1 -  CAR_VOLTAGE_LOW_PASS_K)))\n\n      # Cap the car battery power and save it in a param every 10-ish seconds\n      self.car_battery_capacity_uWh = max(self.car_battery_capacity_uWh, 0)\n      self.car_battery_capacity_uWh = min(self.car_battery_capacity_uWh, CAR_BATTERY_CAPACITY_uWh)\n      if now - self.last_save_time >= 10:\n        put_nonblocking(\"CarBatteryCapacity\", str(int(self.car_battery_capacity_uWh)))\n        self.last_save_time = now\n\n      # First measurement, set integration time\n      with self.integration_lock:\n        if self.last_measurement_time is None:\n          self.last_measurement_time = now\n          return\n\n      if (pandaState.pandaState.ignitionLine or pandaState.pandaState.ignitionCan):\n        # If there is ignition, we integrate the charging rate of the car\n        with self.integration_lock:\n          self.power_used_uWh = 0\n          integration_time_h = (now - self.last_measurement_time) / 3600\n          if integration_time_h < 0:\n            raise ValueError(f\"Negative integration time: {integration_time_h}h\")\n          self.car_battery_capacity_uWh += (CAR_CHARGING_RATE_W * 1e6 * integration_time_h)\n          self.last_measurement_time = now\n      else:\n        # No ignition, we integrate the offroad power used by the device\n        is_uno = pandaState.pandaState.pandaType == log.PandaState.PandaType.uno\n        # Get current power draw somehow\n        current_power = HARDWARE.get_current_power_draw() # pylint: disable=assignment-from-none\n        if current_power is not None:\n          pass\n        elif HARDWARE.get_battery_status() == 'Discharging':\n          # If the battery is discharging, we can use this measurement\n          # On C2: this is low by about 10-15%, probably mostly due to UNO draw not being factored in\n          current_power = ((HARDWARE.get_battery_voltage() / 1000000) * (HARDWARE.get_battery_current() / 1000000))\n        elif (self.next_pulsed_measurement_time is not None) and (self.next_pulsed_measurement_time <= now):\n          # TODO: Figure out why this is off by a factor of 3/4???\n          FUDGE_FACTOR = 1.33\n\n          # Turn off charging for about 10 sec in a thread that does not get killed on SIGINT, and perform measurement here to avoid blocking thermal\n          def perform_pulse_measurement(now):\n            try:\n              HARDWARE.set_battery_charging(False)\n              time.sleep(5)\n\n              # Measure for a few sec to get a good average\n              voltages = []\n              currents = []\n              for _ in range(6):\n                voltages.append(HARDWARE.get_battery_voltage())\n                currents.append(HARDWARE.get_battery_current())\n                time.sleep(1)\n              current_power = ((mean(voltages) / 1000000) * (mean(currents) / 1000000))\n\n              self._perform_integration(now, current_power * FUDGE_FACTOR)\n\n              # Enable charging again\n              HARDWARE.set_battery_charging(True)\n            except Exception:\n              cloudlog.exception(\"Pulsed power measurement failed\")\n\n          # Start pulsed measurement and return\n          threading.Thread(target=perform_pulse_measurement, args=(now,)).start()\n          self.next_pulsed_measurement_time = None\n          return\n\n        elif self.next_pulsed_measurement_time is None and not is_uno:\n          # On a charging EON with black panda, or drawing more than 400mA out of a white/grey one\n          # Only way to get the power draw is to turn off charging for a few sec and check what the discharging rate is\n          # We shouldn't do this very often, so make sure it has been some long-ish random time interval\n          self.next_pulsed_measurement_time = now + random.randint(120, 180)\n          return\n        else:\n          # Do nothing\n          return\n\n        # Do the integration\n        self._perform_integration(now, current_power)\n    except Exception:\n      cloudlog.exception(\"Power monitoring calculation failed\")\n\n  def _perform_integration(self, t, current_power):\n    with self.integration_lock:\n      try:\n        if self.last_measurement_time:\n          integration_time_h = (t - self.last_measurement_time) / 3600\n          power_used = (current_power * 1000000) * integration_time_h\n          if power_used < 0:\n            raise ValueError(f\"Negative power used! Integration time: {integration_time_h} h Current Power: {power_used} uWh\")\n          self.power_used_uWh += power_used\n          self.car_battery_capacity_uWh -= power_used\n          self.last_measurement_time = t\n      except Exception:\n        cloudlog.exception(\"Integration failed\")\n\n  # Get the power usage\n  def get_power_used(self):\n    return int(self.power_used_uWh)\n\n  def get_car_battery_capacity(self):\n    return int(self.car_battery_capacity_uWh)\n\n  # See if we need to disable charging\n  def should_disable_charging(self, pandaState, offroad_timestamp):\n    if pandaState is None or offroad_timestamp is None:\n      return False\n\n    now = sec_since_boot()\n    disable_charging = False\n    disable_charging |= (now - offroad_timestamp) > MAX_TIME_OFFROAD_S\n    disable_charging |= (self.car_voltage_mV < (VBATT_PAUSE_CHARGING * 1e3)) and (self.car_voltage_instant_mV > (VBATT_INSTANT_PAUSE_CHARGING * 1e3))\n    disable_charging |= (self.car_battery_capacity_uWh <= 0)\n    disable_charging &= (not pandaState.pandaState.ignitionLine and not pandaState.pandaState.ignitionCan)\n    disable_charging &= (not self.params.get_bool(\"DisablePowerDown\"))\n    disable_charging &= (pandaState.pandaState.harnessStatus != log.PandaState.HarnessStatus.notConnected)\n    disable_charging |= self.params.get_bool(\"ForcePowerDown\")\n    return disable_charging\n\n  # See if we need to shutdown\n  def should_shutdown(self, pandaState, offroad_timestamp, started_seen, LEON):\n    if pandaState is None or offroad_timestamp is None:\n      return False\n\n    now = sec_since_boot()\n    panda_charging = (pandaState.pandaState.usbPowerMode != log.PandaState.UsbPowerMode.client)\n    BATT_PERC_OFF = 10 if LEON else 3\n\n    should_shutdown = False\n    # Wait until we have shut down charging before powering down\n    should_shutdown |= (not panda_charging and self.should_disable_charging(pandaState, offroad_timestamp))\n    should_shutdown |= ((HARDWARE.get_battery_capacity() < BATT_PERC_OFF) and (not HARDWARE.get_battery_charging()) and ((now - offroad_timestamp) > 60))\n    should_shutdown &= started_seen or (now > MIN_ON_TIME_S)\n    return should_shutdown\n"
  },
  {
    "path": "selfdrive/thermald/thermald.py",
    "content": "#!/usr/bin/env python3\nimport datetime\nimport os\nimport time\nfrom pathlib import Path\nfrom typing import Dict, Optional, Tuple\nfrom collections import namedtuple, OrderedDict\n\nimport psutil\nfrom smbus2 import SMBus\n\nimport cereal.messaging as messaging\nfrom cereal import log\nfrom common.filter_simple import FirstOrderFilter\nfrom common.numpy_fast import interp\nfrom common.params import Params, ParamKeyType\nfrom common.realtime import DT_TRML, sec_since_boot\n# from common.dict_helpers import strip_deprecated_keys\nfrom selfdrive.controls.lib.alertmanager import set_offroad_alert\nfrom selfdrive.controls.lib.pid import PIController\nfrom selfdrive.hardware import EON, TICI, PC, HARDWARE, JETSON\nfrom selfdrive.loggerd.config import get_available_percent\nfrom selfdrive.pandad import get_expected_signature\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.thermald.power_monitoring import PowerMonitoring\nfrom selfdrive.version import tested_branch, terms_version, training_version\n\nFW_SIGNATURE = get_expected_signature()\n\nThermalStatus = log.DeviceState.ThermalStatus\nNetworkType = log.DeviceState.NetworkType\nNetworkStrength = log.DeviceState.NetworkStrength\nCURRENT_TAU = 15.   # 15s time constant\nTEMP_TAU = 5.   # 5s time constant\nDAYS_NO_CONNECTIVITY_MAX = 7  # do not allow to engage after a week without internet\nDAYS_NO_CONNECTIVITY_PROMPT = 4  # send an offroad prompt after 4 days with no internet\nDISCONNECT_TIMEOUT = 5.  # wait 5 seconds before going offroad after disconnect so you get an alert\n\nThermalBand = namedtuple(\"ThermalBand\", ['min_temp', 'max_temp'])\n\n# List of thermal bands. We will stay within this region as long as we are within the bounds.\n# When exiting the bounds, we'll jump to the lower or higher band. Bands are ordered in the dict.\nTHERMAL_BANDS = OrderedDict({\n  ThermalStatus.green: ThermalBand(None, 80.0),\n  ThermalStatus.yellow: ThermalBand(75.0, 96.0),\n  ThermalStatus.red: ThermalBand(80.0, 107.),\n  ThermalStatus.danger: ThermalBand(94.0, None),\n})\n\n# Override to highest thermal band when offroad and above this temp\nOFFROAD_DANGER_TEMP = 70.0\n\nprev_offroad_states: Dict[str, Tuple[bool, Optional[str]]] = {}\n\nparams = Params()\nfrom common.dp_time import LAST_MODIFIED_THERMALD\nfrom common.dp_common import get_last_modified, param_get_if_updated\nLEON = False\n\ndef read_tz(x):\n  if x is None:\n    return 0\n\n  try:\n    with open(f\"/sys/devices/virtual/thermal/thermal_zone{x}/temp\") as f:\n      return int(f.read())\n  except FileNotFoundError:\n    return 0\n\n\ndef read_thermal(thermal_config):\n  dat = messaging.new_message('deviceState')\n  dat.deviceState.cpuTempC = [read_tz(z) / thermal_config.cpu[1] for z in thermal_config.cpu[0]]\n  dat.deviceState.gpuTempC = [read_tz(z) / thermal_config.gpu[1] for z in thermal_config.gpu[0]]\n  dat.deviceState.memoryTempC = read_tz(thermal_config.mem[0]) / thermal_config.mem[1]\n  dat.deviceState.ambientTempC = read_tz(thermal_config.ambient[0]) / thermal_config.ambient[1]\n  return dat\n\n\ndef setup_eon_fan():\n  global LEON\n\n  os.system(\"echo 2 > /sys/module/dwc3_msm/parameters/otg_switch\")\n\n  bus = SMBus(7, force=True)\n  try:\n    bus.write_byte_data(0x21, 0x10, 0xf)   # mask all interrupts\n    bus.write_byte_data(0x21, 0x03, 0x1)   # set drive current and global interrupt disable\n    bus.write_byte_data(0x21, 0x02, 0x2)   # needed?\n    bus.write_byte_data(0x21, 0x04, 0x4)   # manual override source\n  except IOError:\n    print(\"LEON detected\")\n    LEON = True\n  bus.close()\n\n\nlast_eon_fan_val = None\ndef set_eon_fan(val):\n  global LEON, last_eon_fan_val\n\n  if last_eon_fan_val is None or last_eon_fan_val != val:\n    bus = SMBus(7, force=True)\n    if LEON:\n      try:\n        i = [0x1, 0x3 | 0, 0x3 | 0x08, 0x3 | 0x10][val]\n        bus.write_i2c_block_data(0x3d, 0, [i])\n      except IOError:\n        # tusb320\n        if val == 0:\n          bus.write_i2c_block_data(0x67, 0xa, [0])\n          #bus.write_i2c_block_data(0x67, 0x45, [1<<2])\n        else:\n          #bus.write_i2c_block_data(0x67, 0x45, [0])\n          bus.write_i2c_block_data(0x67, 0xa, [0x20])\n          bus.write_i2c_block_data(0x67, 0x8, [(val - 1) << 6])\n    else:\n      bus.write_byte_data(0x21, 0x04, 0x2)\n      bus.write_byte_data(0x21, 0x03, (val*2)+1)\n      bus.write_byte_data(0x21, 0x04, 0x4)\n    bus.close()\n    last_eon_fan_val = val\n\n\n# temp thresholds to control fan speed - high hysteresis\n_TEMP_THRS_H = [50., 65., 80., 10000]\n# temp thresholds to control fan speed - low hysteresis\n_TEMP_THRS_L = [42.5, 57.5, 72.5, 10000]\n# fan speed options\n_FAN_SPEEDS = [0, 16384, 32768, 65535]\n\n\ndef handle_fan_eon(dp_fan_mode, controller, max_cpu_temp, fan_speed, ignition):\n  _fan_speed = _FAN_SPEEDS\n  if dp_fan_mode == 2:\n    _fan_speed = [0, 65535, 65535, 65535]\n    _bat_temp_threshold = 15.\n  elif dp_fan_mode == 1:\n    _fan_speed = [0, 16384, 16384, 32768]\n\n  new_speed_h = next(speed for speed, temp_h in zip(_fan_speed, _TEMP_THRS_H) if temp_h > max_cpu_temp)\n  new_speed_l = next(speed for speed, temp_l in zip(_fan_speed, _TEMP_THRS_L) if temp_l > max_cpu_temp)\n\n  if new_speed_h > fan_speed:\n    # update speed if using the high thresholds results in fan speed increment\n    fan_speed = new_speed_h\n  elif new_speed_l < fan_speed:\n    # update speed if using the low thresholds results in fan speed decrement\n    fan_speed = new_speed_l\n\n  set_eon_fan(fan_speed // 16384)\n\n  return fan_speed\n\n\ndef handle_fan_uno(dp_fan_mode, controller, max_cpu_temp, fan_speed, ignition):\n  if dp_fan_mode == 2:\n    new_speed = 80\n  elif dp_fan_mode == 1:\n    new_speed = int(interp(max_cpu_temp, [65.0, 80.0, 90.0], [0, 20, 60]))\n  else:\n    new_speed = int(interp(max_cpu_temp, [40.0, 80.0], [0, 80]))\n\n  if not ignition:\n    new_speed = min(10 if dp_fan_mode == 2 else 30, new_speed)\n\n  return new_speed\n\n\ndef handle_fan_tici(dp_fan_mode, controller, max_cpu_temp, fan_speed, ignition):\n  controller.neg_limit = -(80 if ignition else 30)\n  controller.pos_limit = -(30 if ignition else 0)\n\n  fan_pwr_out = -int(controller.update(\n                     setpoint=(75 if ignition else (OFFROAD_DANGER_TEMP - 2)),\n                     measurement=max_cpu_temp,\n                     feedforward=interp(max_cpu_temp, [60.0, 100.0], [0, -80])\n                  ))\n\n  return fan_pwr_out\n\ndef handle_fan_jetson(dp_fan_mode, controller, max_cpu_temp, fan_speed, ignition):\n  new_speed = int(interp(max_cpu_temp, [40.0, 80.0], [100, 255]))\n\n  if not ignition:\n    new_speed = min(100, new_speed)\n\n  if fan_speed != new_speed:\n    os.system(\"echo %s > /sys/devices/pwm-fan/target_pwm\" % new_speed)\n\n  return new_speed\n\ndef set_offroad_alert_if_changed(offroad_alert: str, show_alert: bool, extra_text: Optional[str]=None):\n  if prev_offroad_states.get(offroad_alert, None) == (show_alert, extra_text):\n    return\n  prev_offroad_states[offroad_alert] = (show_alert, extra_text)\n  set_offroad_alert(offroad_alert, show_alert, extra_text)\n\n\ndef thermald_thread():\n\n  pm = messaging.PubMaster(['deviceState'])\n\n  pandaState_timeout = int(1000 * 2.5 * DT_TRML)  # 2.5x the expected pandaState frequency\n  pandaState_sock = messaging.sub_sock('pandaState', timeout=pandaState_timeout)\n  location_sock = messaging.sub_sock('gpsLocationExternal')\n  managerState_sock = messaging.sub_sock('managerState', conflate=True)\n\n  fan_speed = 0\n  count = 0\n\n  startup_conditions = {\n    \"ignition\": False,\n  }\n  startup_conditions_prev = startup_conditions.copy()\n\n  off_ts = None\n  started_ts = None\n  started_seen = False\n  thermal_status = ThermalStatus.green\n  usb_power = True\n\n  network_type = NetworkType.none\n  network_strength = NetworkStrength.unknown\n  network_info = None\n  modem_version = None\n  registered_count = 0\n\n  current_filter = FirstOrderFilter(0., CURRENT_TAU, DT_TRML)\n  temp_filter = FirstOrderFilter(0., TEMP_TAU, DT_TRML)\n  pandaState_prev = None\n  should_start_prev = False\n  handle_fan = None\n  is_uno = False\n  ui_running_prev = False\n\n  power_monitor = PowerMonitoring()\n  no_panda_cnt = 0\n\n  HARDWARE.initialize_hardware()\n  thermal_config = HARDWARE.get_thermal_config()\n\n  # TODO: use PI controller for UNO\n  controller = PIController(k_p=0, k_i=2e-3, neg_limit=-80, pos_limit=0, rate=(1 / DT_TRML))\n\n  if params.get_bool(\"IsOnroad\"):\n    cloudlog.event(\"onroad flag not cleared\")\n\n  # dp\n  dp_no_batt = params.get_bool(\"dp_no_batt\")\n  dp_temp_monitor = True\n  dp_last_modified_temp_monitor = None\n\n  dp_auto_shutdown = False\n  dp_last_modified_auto_shutdown = None\n  dp_auto_shutdown_last = False\n\n  dp_auto_shutdown_in = 90\n  dp_last_modified_auto_shutdown_in = None\n  dp_auto_shutdown_in_last = 90\n\n  dp_fan_mode = 0\n  dp_fan_mode_last = None\n\n  modified = None\n  last_modified = None\n  last_modified_check = None\n\n  #dp\n  prebuilt_file = '/data/openpilot/prebuilt'\n  dp_prebuilt = params.get_bool(\"dp_prebuilt\")\n  if not os.path.isfile(prebuilt_file) and dp_prebuilt:\n    os.system(\"touch /data/openpilot/prebuilt\")\n  elif os.path.isfile(prebuilt_file) and not dp_prebuilt:\n    os.system(\"rm -fr /data/openpilot/prebuilt\")\n\n  # CPR3 logging\n  if EON:\n    base_path = \"/sys/kernel/debug/cpr3-regulator/\"\n    cpr_files = [p for p in Path(base_path).glob(\"**/*\") if p.is_file()]\n    cpr_files = [\"/sys/kernel/debug/regulator/pm8994_s11/voltage\"] + cpr_files\n    cpr_data = {}\n    for cf in cpr_files:\n      with open(cf, \"r\") as f:\n        try:\n          cpr_data[str(cf)] = f.read().strip()\n        except Exception:\n          pass\n    cloudlog.event(\"CPR\", data=cpr_data)\n\n  if JETSON:\n    handle_fan = handle_fan_jetson\n    # give it some time to get everything ready in case ign is already on.\n    time.sleep(10)\n  while 1:\n\n    # dp - load temp monitor conf\n    last_modified_check, modified = get_last_modified(LAST_MODIFIED_THERMALD, last_modified_check, modified)\n    if last_modified != modified:\n      dp_temp_monitor, dp_last_modified_temp_monitor = param_get_if_updated(\"dp_temp_monitor\", \"bool\", dp_temp_monitor, dp_last_modified_temp_monitor)\n      dp_auto_shutdown, dp_last_modified_auto_shutdown = param_get_if_updated(\"dp_auto_shutdown\", \"bool\", dp_auto_shutdown, dp_last_modified_auto_shutdown)\n      dp_auto_shutdown_in, dp_last_modified_auto_shutdown_in = param_get_if_updated(\"dp_auto_shutdown_in\", \"int\", dp_auto_shutdown_in, dp_last_modified_auto_shutdown_in)\n      dp_fan_mode, dp_fan_mode_last = param_get_if_updated(\"dp_fan_mode\", \"int\", dp_fan_mode, dp_fan_mode_last)\n      last_modified = modified\n\n    pandaState = messaging.recv_sock(pandaState_sock, wait=True)\n    msg = read_thermal(thermal_config)\n\n    if pandaState is not None:\n      usb_power = pandaState.pandaState.usbPowerMode != log.PandaState.UsbPowerMode.client\n\n      # If we lose connection to the panda, wait 5 seconds before going offroad\n      if pandaState.pandaState.pandaType == log.PandaState.PandaType.unknown:\n        no_panda_cnt += 1\n        if no_panda_cnt > DISCONNECT_TIMEOUT / DT_TRML:\n          if startup_conditions[\"ignition\"]:\n            cloudlog.error(\"Lost panda connection while onroad\")\n          startup_conditions[\"ignition\"] = False\n      else:\n        no_panda_cnt = 0\n        startup_conditions[\"ignition\"] = pandaState.pandaState.ignitionLine or pandaState.pandaState.ignitionCan\n\n      startup_conditions[\"hardware_supported\"] = pandaState.pandaState.pandaType not in [log.PandaState.PandaType.whitePanda,\n                                                                                         log.PandaState.PandaType.greyPanda]\n      set_offroad_alert_if_changed(\"Offroad_HardwareUnsupported\", not startup_conditions[\"hardware_supported\"])\n\n      # Setup fan handler on first connect to panda\n      if not JETSON and handle_fan is None and pandaState.pandaState.pandaType != log.PandaState.PandaType.unknown:\n        is_uno = pandaState.pandaState.pandaType == log.PandaState.PandaType.uno\n\n        if TICI:\n          cloudlog.info(\"Setting up TICI fan handler\")\n          handle_fan = handle_fan_tici\n        elif is_uno or PC:\n          cloudlog.info(\"Setting up UNO fan handler\")\n          handle_fan = handle_fan_uno\n        else:\n          cloudlog.info(\"Setting up EON fan handler\")\n          setup_eon_fan()\n          handle_fan = handle_fan_eon\n\n      # Handle disconnect\n      if pandaState_prev is not None:\n        if pandaState.pandaState.pandaType == log.PandaState.PandaType.unknown and \\\n          pandaState_prev.pandaState.pandaType != log.PandaState.PandaType.unknown:\n          params.clear_all(ParamKeyType.CLEAR_ON_PANDA_DISCONNECT)\n      pandaState_prev = pandaState\n\n    # get_network_type is an expensive call. update every 10s\n    if (count % int(10. / DT_TRML)) == 0:\n      try:\n        network_type = HARDWARE.get_network_type()\n        network_strength = HARDWARE.get_network_strength(network_type)\n        network_info = HARDWARE.get_network_info()  # pylint: disable=assignment-from-none\n\n        # Log modem version once\n        if modem_version is None:\n          modem_version = HARDWARE.get_modem_version()  # pylint: disable=assignment-from-none\n          if modem_version is not None:\n            cloudlog.warning(f\"Modem version: {modem_version}\")\n\n        if TICI and (network_info.get('state', None) == \"REGISTERED\"):\n          registered_count += 1\n        else:\n          registered_count = 0\n\n        if registered_count > 10:\n          cloudlog.warning(f\"Modem stuck in registered state {network_info}. nmcli conn up lte\")\n          os.system(\"nmcli conn up lte\")\n          registered_count = 0\n\n      except Exception:\n        cloudlog.exception(\"Error getting network status\")\n\n    msg.deviceState.freeSpacePercent = get_available_percent(default=100.0)\n    msg.deviceState.memoryUsagePercent = int(round(psutil.virtual_memory().percent))\n    msg.deviceState.cpuUsagePercent = [int(round(n)) for n in psutil.cpu_percent(percpu=True)]\n    msg.deviceState.gpuUsagePercent = int(round(HARDWARE.get_gpu_usage_percent()))\n    msg.deviceState.networkType = network_type\n    msg.deviceState.networkStrength = network_strength\n    if network_info is not None:\n      msg.deviceState.networkInfo = network_info\n\n    msg.deviceState.batteryPercent = HARDWARE.get_battery_capacity()\n    msg.deviceState.batteryCurrent = HARDWARE.get_battery_current()\n    msg.deviceState.usbOnline = HARDWARE.get_usb_present()\n\n    # Fake battery levels on uno for frame\n    if dp_no_batt:\n      msg.deviceState.batteryPercent = 100\n\n    current_filter.update(msg.deviceState.batteryCurrent / 1e6)\n\n    max_comp_temp = temp_filter.update(\n      max(max(msg.deviceState.cpuTempC), msg.deviceState.memoryTempC, max(msg.deviceState.gpuTempC))\n    )\n\n    if handle_fan is not None:\n      fan_speed = handle_fan(dp_fan_mode, controller, max_comp_temp, fan_speed, startup_conditions[\"ignition\"])\n      msg.deviceState.fanSpeedPercentDesired = fan_speed\n\n    is_offroad_for_5_min = (started_ts is None) and ((not started_seen) or (off_ts is None) or (sec_since_boot() - off_ts > 60 * 5))\n    if is_offroad_for_5_min and max_comp_temp > OFFROAD_DANGER_TEMP:\n      # If device is offroad we want to cool down before going onroad\n      # since going onroad increases load and can make temps go over 107\n      thermal_status = ThermalStatus.danger\n    else:\n      current_band = THERMAL_BANDS[thermal_status]\n      band_idx = list(THERMAL_BANDS.keys()).index(thermal_status)\n      if current_band.min_temp is not None and max_comp_temp < current_band.min_temp:\n        thermal_status = list(THERMAL_BANDS.keys())[band_idx - 1]\n      elif current_band.max_temp is not None and max_comp_temp > current_band.max_temp:\n        thermal_status = list(THERMAL_BANDS.keys())[band_idx + 1]\n\n    if not dp_temp_monitor and thermal_status in [ThermalStatus.red, ThermalStatus.danger]:\n      thermal_status = ThermalStatus.yellow\n    # **** starting logic ****\n\n    # Check for last update time and display alerts if needed\n    # now = datetime.datetime.utcnow()\n    #\n    # # show invalid date/time alert\n    # startup_conditions[\"time_valid\"] = (now.year > 2020) or (now.year == 2020 and now.month >= 10)\n    # set_offroad_alert_if_changed(\"Offroad_InvalidTime\", (not startup_conditions[\"time_valid\"]))\n    #\n    # # Show update prompt\n    # try:\n    #   last_update = datetime.datetime.fromisoformat(params.get(\"LastUpdateTime\", encoding='utf8'))\n    # except (TypeError, ValueError):\n    #   last_update = now\n    # dt = now - last_update\n    #\n    # update_failed_count = params.get(\"UpdateFailedCount\")\n    # update_failed_count = 0 if update_failed_count is None else int(update_failed_count)\n    # last_update_exception = params.get(\"LastUpdateException\", encoding='utf8')\n    #\n    # if update_failed_count > 15 and last_update_exception is not None:\n    #   if tested_branch:\n    #     extra_text = \"Ensure the software is correctly installed\"\n    #   else:\n    #     extra_text = last_update_exception\n    #\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeeded\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeededPrompt\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_UpdateFailed\", True, extra_text=extra_text)\n    # elif dt.days > DAYS_NO_CONNECTIVITY_MAX and update_failed_count > 1:\n    #   set_offroad_alert_if_changed(\"Offroad_UpdateFailed\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeededPrompt\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeeded\", True)\n    # elif dt.days > DAYS_NO_CONNECTIVITY_PROMPT:\n    #   remaining_time = str(max(DAYS_NO_CONNECTIVITY_MAX - dt.days, 0))\n    #   set_offroad_alert_if_changed(\"Offroad_UpdateFailed\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeeded\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeededPrompt\", True, extra_text=f\"{remaining_time} days.\")\n    # else:\n    #   set_offroad_alert_if_changed(\"Offroad_UpdateFailed\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeeded\", False)\n    #   set_offroad_alert_if_changed(\"Offroad_ConnectivityNeededPrompt\", False)\n\n    startup_conditions[\"up_to_date\"] = params.get(\"Offroad_ConnectivityNeeded\") is None or params.get_bool(\"DisableUpdates\")\n    startup_conditions[\"not_uninstalling\"] = not params.get_bool(\"DoUninstall\")\n    startup_conditions[\"accepted_terms\"] = params.get(\"HasAcceptedTerms\") == terms_version\n\n    panda_signature = params.get(\"PandaFirmware\")\n    startup_conditions[\"fw_version_match\"] = (panda_signature is None) or (panda_signature == FW_SIGNATURE)   # don't show alert is no panda is connected (None)\n    set_offroad_alert_if_changed(\"Offroad_PandaFirmwareMismatch\", (not startup_conditions[\"fw_version_match\"]))\n\n    # with 2% left, we killall, otherwise the phone will take a long time to boot\n    startup_conditions[\"free_space\"] = msg.deviceState.freeSpacePercent > 2\n    startup_conditions[\"completed_training\"] = params.get(\"CompletedTrainingVersion\") == training_version or \\\n                                               params.get_bool(\"Passive\")\n    startup_conditions[\"not_driver_view\"] = not params.get_bool(\"IsDriverViewEnabled\")\n    startup_conditions[\"not_taking_snapshot\"] = not params.get_bool(\"IsTakingSnapshot\")\n    # if any CPU gets above 107 or the battery gets above 63, kill all processes\n    # controls will warn with CPU above 95 or battery above 60\n    startup_conditions[\"device_temp_good\"] = thermal_status < ThermalStatus.danger\n    set_offroad_alert_if_changed(\"Offroad_TemperatureTooHigh\", (not startup_conditions[\"device_temp_good\"]))\n\n    if TICI:\n      set_offroad_alert_if_changed(\"Offroad_NvmeMissing\", (not Path(\"/data/media\").is_mount()))\n\n    # Handle offroad/onroad transition\n    should_start = all(startup_conditions.values())\n    if should_start != should_start_prev or (count == 0):\n      params.put_bool(\"IsOnroad\", should_start)\n      params.put_bool(\"IsOffroad\", not should_start)\n      HARDWARE.set_power_save(not should_start)\n\n    if should_start:\n      off_ts = None\n      if started_ts is None:\n        started_ts = sec_since_boot()\n        started_seen = True\n    else:\n      if startup_conditions[\"ignition\"] and (startup_conditions != startup_conditions_prev):\n        cloudlog.event(\"Startup blocked\", startup_conditions=startup_conditions)\n\n      started_ts = None\n      if off_ts is None:\n        off_ts = sec_since_boot()\n\n    # Offroad power monitoring\n    if not dp_no_batt:\n      power_monitor.calculate(pandaState)\n      msg.deviceState.offroadPowerUsageUwh = power_monitor.get_power_used()\n      msg.deviceState.carBatteryCapacityUwh = max(0, power_monitor.get_car_battery_capacity())\n\n    # Check if we need to disable charging (handled by boardd)\n    msg.deviceState.chargingDisabled = power_monitor.should_disable_charging(pandaState, off_ts)\n\n    # Check if we need to shut down\n    if power_monitor.should_shutdown(pandaState, off_ts, started_seen, LEON):\n      cloudlog.info(f\"shutting device down, offroad since {off_ts}\")\n      # TODO: add function for blocking cloudlog instead of sleep\n      time.sleep(10)\n      HARDWARE.shutdown()\n\n    # dp - auto shutdown\n    # reset off_ts if we change auto shutdown related params\n    if off_ts is not None:\n      if dp_auto_shutdown:\n        shutdown_sec = dp_auto_shutdown_in * 60\n        sec_now = sec_since_boot() - off_ts\n        if (shutdown_sec - 5) < sec_now:\n          msg.deviceState.chargingDisabled = True\n        if shutdown_sec < sec_now:\n          time.sleep(10)\n          HARDWARE.shutdown()\n\n      if dp_auto_shutdown_in_last != dp_auto_shutdown_in or dp_auto_shutdown_last != dp_auto_shutdown:\n        off_ts = sec_since_boot()\n      dp_auto_shutdown_last = dp_auto_shutdown\n      dp_auto_shutdown_in_last = dp_auto_shutdown_in\n\n    # If UI has crashed, set the brightness to reasonable non-zero value\n    manager_state = messaging.recv_one_or_none(managerState_sock)\n    if manager_state is not None:\n      ui_running = \"ui\" in (p.name for p in manager_state.managerState.processes if p.running)\n      if ui_running_prev and not ui_running:\n        HARDWARE.set_screen_brightness(20)\n      ui_running_prev = ui_running\n\n    msg.deviceState.chargingError = current_filter.x > 0. and msg.deviceState.batteryPercent < 90  # if current is positive, then battery is being discharged\n    msg.deviceState.started = started_ts is not None\n    msg.deviceState.startedMonoTime = int(1e9*(started_ts or 0))\n\n    last_ping = params.get(\"LastAthenaPingTime\")\n    if last_ping is not None:\n      msg.deviceState.lastAthenaPingTime = int(last_ping)\n\n    msg.deviceState.thermalStatus = thermal_status\n    pm.send(\"deviceState\", msg)\n\n    if EON and not is_uno:\n      set_offroad_alert_if_changed(\"Offroad_ChargeDisabled\", (not usb_power))\n\n    should_start_prev = should_start\n    startup_conditions_prev = startup_conditions.copy()\n\n    # report to server once every 10 minutes\n    # if (count % int(600. / DT_TRML)) == 0:\n    #   if EON and started_ts is None and msg.deviceState.memoryUsagePercent > 40:\n    #     cloudlog.event(\"High offroad memory usage\", mem=msg.deviceState.memoryUsagePercent)\n    #\n    #   location = messaging.recv_sock(location_sock)\n    #   cloudlog.event(\"STATUS_PACKET\",\n    #                  count=count,\n    #                  pandaState=(strip_deprecated_keys(pandaState.to_dict()) if pandaState else None),\n    #                  location=(strip_deprecated_keys(location.gpsLocationExternal.to_dict()) if location else None),\n    #                  deviceState=strip_deprecated_keys(msg.to_dict()))\n\n    count += 1\n\n\ndef main():\n  thermald_thread()\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/timezoned.py",
    "content": "#!/usr/bin/env python3\nimport json\nimport os\nimport time\nimport subprocess\n\nimport requests\nfrom timezonefinder import TimezoneFinder\n\nfrom common.params import Params\nfrom selfdrive.hardware import TICI\nfrom selfdrive.swaglog import cloudlog\n\n\ndef set_timezone(valid_timezones, timezone):\n  if timezone not in valid_timezones:\n    cloudlog.error(f\"Timezone not supported {timezone}\")\n    return\n\n  cloudlog.debug(f\"Setting timezone to {timezone}\")\n  try:\n    if TICI:\n      tzpath = os.path.join(\"/usr/share/zoneinfo/\", timezone)\n      subprocess.check_call(f'sudo su -c \"ln -snf {tzpath} /data/etc/tmptime && \\\n                              mv /data/etc/tmptime /data/etc/localtime\"', shell=True)\n      subprocess.check_call(f'sudo su -c \"echo \\\"{timezone}\\\" > /data/etc/timezone\"', shell=True)\n    else:\n      subprocess.check_call(f'sudo timedatectl set-timezone {timezone}', shell=True)\n  except subprocess.CalledProcessError:\n    cloudlog.exception(f\"Error setting timezone to {timezone}\")\n\n\ndef main():\n  params = Params()\n  tf = TimezoneFinder()\n\n  # Get allowed timezones\n  valid_timezones = subprocess.check_output('timedatectl list-timezones', shell=True, encoding='utf8').strip().split('\\n')\n\n  while True:\n    time.sleep(60)\n\n    is_onroad = not params.get_bool(\"IsOffroad\")\n    if is_onroad:\n      continue\n\n    # Set based on param\n    timezone = params.get(\"Timezone\", encoding='utf8')\n    if timezone is not None:\n      cloudlog.debug(\"Setting timezone based on param\")\n      set_timezone(valid_timezones, timezone)\n      continue\n\n    location = params.get(\"LastGPSPosition\", encoding='utf8')\n\n    # Find timezone based on IP geolocation if no gps location is available\n    if location is None:\n      cloudlog.debug(\"Setting timezone based on IP lookup\")\n      try:\n        r = requests.get(\"https://ipapi.co/timezone\", timeout=10)\n        if r.status_code == 200:\n          set_timezone(valid_timezones, r.text)\n        else:\n          cloudlog.error(f\"Unexpected status code from api {r.status_code}\")\n\n        time.sleep(3600)  # Don't make too many API requests\n      except requests.exceptions.RequestException:\n        cloudlog.exception(\"Error getting timezone based on IP\")\n        continue\n\n    # Find timezone by reverse geocoding the last known gps location\n    else:\n      cloudlog.debug(\"Setting timezone based on GPS location\")\n      try:\n        location = json.loads(location)\n      except Exception:\n        cloudlog.exception(\"Error parsing location\")\n        continue\n\n      timezone = tf.timezone_at(lng=location['longitude'], lat=location['latitude'])\n      if timezone is None:\n        cloudlog.error(f\"No timezone found based on location, {location}\")\n        continue\n      set_timezone(valid_timezones, timezone)\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/tombstoned.py",
    "content": "#!/usr/bin/env python3\nimport datetime\nimport os\nimport re\nimport shutil\nimport signal\nimport subprocess\nimport time\nimport glob\n\nimport sentry_sdk\n\nfrom common.params import Params\nfrom common.file_helpers import mkdirs_exists_ok\nfrom selfdrive.hardware import TICI, HARDWARE\nfrom selfdrive.loggerd.config import ROOT\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.version import branch, commit, dirty, origin, version\n\nMAX_SIZE = 100000 * 10  # mal size is 40-100k, allow up to 1M\nif TICI:\n  MAX_SIZE = MAX_SIZE * 100  # Allow larger size for tici since files contain coredump\nMAX_TOMBSTONE_FN_LEN = 62  # 85 - 23 (\"<dongle id>/crash/\")\n\nTOMBSTONE_DIR = \"/data/tombstones/\"\nAPPORT_DIR = \"/var/crash/\"\n\n\ndef safe_fn(s):\n  extra = ['_']\n  return \"\".join(c for c in s if c.isalnum() or c in extra).rstrip()\n\n\ndef sentry_report(fn, message, contents):\n  cloudlog.error({'tombstone': message})\n\n  with sentry_sdk.configure_scope() as scope:\n      scope.set_extra(\"tombstone_fn\", fn)\n      scope.set_extra(\"tombstone\", contents)\n      sentry_sdk.capture_message(message=message)\n      sentry_sdk.flush()\n\n\ndef clear_apport_folder():\n  for f in glob.glob(APPORT_DIR + '*'):\n    try:\n      os.remove(f)\n    except Exception:\n      pass\n\n\ndef get_apport_stacktrace(fn):\n  try:\n    cmd = f'apport-retrace -s <(cat <(echo \"Package: openpilot\") \"{fn}\")'\n    return subprocess.check_output(cmd, shell=True, encoding='utf8', timeout=30, executable='/bin/bash')  # pylint: disable=unexpected-keyword-arg\n  except subprocess.CalledProcessError:\n    return \"Error getting stacktrace\"\n  except subprocess.TimeoutExpired:\n    return \"Timeout getting stacktrace\"\n\n\ndef get_tombstones():\n  \"\"\"Returns list of (filename, ctime) for all tombstones in /data/tombstones\n  and apport crashlogs in /var/crash\"\"\"\n  files = []\n  for folder in [TOMBSTONE_DIR, APPORT_DIR]:\n    if os.path.exists(folder):\n      with os.scandir(folder) as d:\n\n        # Loop over first 1000 directory entries\n        for _, f in zip(range(1000), d):\n          if f.name.startswith(\"tombstone\"):\n            files.append((f.path, int(f.stat().st_ctime)))\n          elif f.name.endswith(\".crash\") and f.stat().st_mode == 0o100640:\n            files.append((f.path, int(f.stat().st_ctime)))\n  return files\n\n\ndef report_tombstone_android(fn):\n  f_size = os.path.getsize(fn)\n  if f_size > MAX_SIZE:\n    cloudlog.error(f\"Tombstone {fn} too big, {f_size}. Skipping...\")\n    return\n\n  with open(fn, encoding='ISO-8859-1') as f:\n    contents = f.read()\n\n  message = \" \".join(contents.split('\\n')[5:7])\n\n  # Cut off pid/tid, since that varies per run\n  name_idx = message.find('name')\n  if name_idx >= 0:\n    message = message[name_idx:]\n\n  executable = \"\"\n  start_exe_idx = message.find('>>> ')\n  end_exe_idx = message.find(' <<<')\n  if start_exe_idx >= 0 and end_exe_idx >= 0:\n    executable = message[start_exe_idx + 4:end_exe_idx]\n\n  # Cut off fault addr\n  fault_idx = message.find(', fault addr')\n  if fault_idx >= 0:\n    message = message[:fault_idx]\n\n  sentry_report(fn, message, contents)\n\n  # Copy crashlog to upload folder\n  clean_path = executable.replace('./', '').replace('/', '_')\n  date = datetime.datetime.now().strftime(\"%Y-%m-%d--%H-%M-%S\")\n\n  new_fn = f\"{date}_{commit[:8]}_{safe_fn(clean_path)}\"[:MAX_TOMBSTONE_FN_LEN]\n\n  crashlog_dir = os.path.join(ROOT, \"crash\")\n  mkdirs_exists_ok(crashlog_dir)\n\n  shutil.copy(fn, os.path.join(crashlog_dir, new_fn))\n\n\ndef report_tombstone_apport(fn):\n  f_size = os.path.getsize(fn)\n  if f_size > MAX_SIZE:\n    cloudlog.error(f\"Tombstone {fn} too big, {f_size}. Skipping...\")\n    return\n\n  message = \"\"  # One line description of the crash\n  contents = \"\"  # Full file contents without coredump\n  path = \"\"  # File path relative to openpilot directory\n\n  proc_maps = False\n\n  with open(fn) as f:\n    for line in f:\n      if \"CoreDump\" in line:\n        break\n      elif \"ProcMaps\" in line:\n        proc_maps = True\n      elif \"ProcStatus\" in line:\n        proc_maps = False\n\n      if not proc_maps:\n        contents += line\n\n      if \"ExecutablePath\" in line:\n        path = line.strip().split(': ')[-1]\n        path = path.replace('/data/openpilot/', '')\n        message += path\n      elif \"Signal\" in line:\n        message += \" - \" + line.strip()\n\n        try:\n          sig_num = int(line.strip().split(': ')[-1])\n          message += \" (\" + signal.Signals(sig_num).name + \")\"  # pylint: disable=no-member\n        except ValueError:\n          pass\n\n  stacktrace = get_apport_stacktrace(fn)\n  stacktrace_s = stacktrace.split('\\n')\n  crash_function = \"No stacktrace\"\n\n  if len(stacktrace_s) > 2:\n    found = False\n\n    # Try to find first entry in openpilot, fall back to first line\n    for line in stacktrace_s:\n      if \"at selfdrive/\" in line:\n          crash_function = line\n          found = True\n          break\n\n    if not found:\n      crash_function = stacktrace_s[1]\n\n    # Remove arguments that can contain pointers to make sentry one-liner unique\n    crash_function = \" \".join(x for x in crash_function.split(' ')[1:] if not x.startswith('0x'))\n    crash_function = re.sub(r'\\(.*?\\)', '', crash_function)\n\n  contents = stacktrace + \"\\n\\n\" + contents\n  message = message + \" - \" + crash_function\n  sentry_report(fn, message, contents)\n\n  # Copy crashlog to upload folder\n  clean_path = path.replace('/', '_')\n  date = datetime.datetime.now().strftime(\"%Y-%m-%d--%H-%M-%S\")\n\n  new_fn = f\"{date}_{commit[:8]}_{safe_fn(clean_path)}\"[:MAX_TOMBSTONE_FN_LEN]\n\n  crashlog_dir = os.path.join(ROOT, \"crash\")\n  mkdirs_exists_ok(crashlog_dir)\n\n  # Files could be on different filesystems, copy, then delete\n  shutil.copy(fn, os.path.join(crashlog_dir, new_fn))\n\n  try:\n    os.remove(fn)\n  except PermissionError:\n    pass\n\n\ndef main():\n  clear_apport_folder()  # Clear apport folder on start, otherwise duplicate crashes won't register\n  initial_tombstones = set(get_tombstones())\n\n  sentry_sdk.utils.MAX_STRING_LENGTH = 8192\n  sentry_sdk.init(\"https://980a0cba712a4c3593c33c78a12446e1:fecab286bcaf4dba8b04f7cff0188e2d@sentry.io/1488600\",\n                  default_integrations=False, release=version)\n\n  dongle_id = Params().get(\"DongleId\", encoding='utf-8')\n  gitname = Params().get(\"GithubUsername\", encoding='utf-8')\n  sentry_sdk.set_user({\"id\": dongle_id})\n  sentry_sdk.set_user({\"name\": gitname})\n  sentry_sdk.set_tag(\"dirty\", dirty)\n  sentry_sdk.set_tag(\"origin\", origin)\n  sentry_sdk.set_tag(\"branch\", branch)\n  sentry_sdk.set_tag(\"commit\", commit)\n  sentry_sdk.set_tag(\"device\", HARDWARE.get_device_type())\n\n  while True:\n    now_tombstones = set(get_tombstones())\n\n    for fn, _ in (now_tombstones - initial_tombstones):\n      try:\n        cloudlog.info(f\"reporting new tombstone {fn}\")\n        if fn.endswith(\".crash\"):\n          report_tombstone_apport(fn)\n        else:\n          report_tombstone_android(fn)\n      except Exception:\n        cloudlog.exception(f\"Error reporting tombstone {fn}\")\n\n    initial_tombstones = now_tombstones\n    time.sleep(5)\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/ui/.gitignore",
    "content": "moc_*\n*.moc\n\ninstaller/installers/*\n\nreplay/replay\nqt/text\nqt/spinner\nqt/setup/setup\nqt/setup/reset\nqt/setup/wifi\nqt/setup/updater\n"
  },
  {
    "path": "selfdrive/ui/SConscript",
    "content": "import os\nImport('qt_env', 'arch', 'common', 'messaging', 'gpucommon', 'visionipc',\n       'cereal', 'transformations')\n\nbase_libs = [gpucommon, common, messaging, cereal, visionipc, transformations, 'zmq',\n             'capnp', 'kj', 'm', 'OpenCL', 'ssl', 'crypto', 'pthread'] + qt_env[\"LIBS\"]\n\nmaps = arch in ['larch64', 'x86_64']\n\nif arch == 'aarch64':\n  base_libs += ['log', 'utils', 'gui', 'ui', 'CB', 'gsl', 'adreno_utils', 'cutils', 'uuid']\n\nif maps and arch == 'x86_64':\n  rpath = [Dir(f\"#phonelibs/mapbox-gl-native-qt/{arch}\").srcnode().abspath]\n  qt_env[\"RPATH\"] += rpath\n\nif arch == \"Darwin\":\n  del base_libs[base_libs.index('OpenCL')]\n  qt_env['FRAMEWORKS'] += ['OpenCL']\n\nwidgets_src = [\"qt/util.cc\", \"qt/widgets/input.cc\", \"qt/widgets/drive_stats.cc\",\n               \"qt/widgets/ssh_keys.cc\", \"qt/widgets/toggle.cc\", \"qt/widgets/controls.cc\",\n               \"qt/widgets/offroad_alerts.cc\", \"qt/widgets/prime.cc\", \"qt/widgets/keyboard.cc\",\n               \"qt/widgets/scrollview.cc\", \"qt/widgets/cameraview.cc\", \"#phonelibs/qrcode/QrCode.cc\", \"qt/api.cc\",\n               \"qt/request_repeater.cc\"]\n\nif arch != 'aarch64':\n  widgets_src += [\"qt/offroad/networking.cc\", \"qt/offroad/wifiManager.cc\"]\n\nqt_env['CPPDEFINES'] = []\nif maps:\n  base_libs += ['qmapboxgl']\n  widgets_src += [\"qt/maps/map_helpers.cc\", \"qt/maps/map_settings.cc\", \"qt/maps/map.cc\"]\n  qt_env['CPPDEFINES'] += [\"ENABLE_MAPS\"]\n\nwidgets = qt_env.Library(\"qt_widgets\", widgets_src, LIBS=base_libs)\nqt_libs = [widgets] + base_libs\n\n# build assets\nassets = \"#selfdrive/assets/assets.cc\"\nassets_src = \"#selfdrive/assets/assets.qrc\"\nqt_env.Command(assets, assets_src, f\"rcc $SOURCES -o $TARGET\")\nqt_env.Depends(assets, Glob('#selfdrive/assets/*', exclude=[assets, assets_src, \"#selfdrive/assets/assets.o\"]))\nasset_obj = qt_env.Object(\"assets\", assets)\n\n# build soundd\nif not os.path.isfile(\"/JETSON\"):\n  qt_env.Program(\"_soundd\", \"soundd.cc\", LIBS=base_libs)\n\n# spinner and text window\nqt_env.Program(\"qt/text\", [\"qt/text.cc\"], LIBS=qt_libs)\nqt_env.Program(\"qt/spinner\", [\"qt/spinner.cc\"], LIBS=qt_libs)\n\n# build main UI\nqt_src = [\"main.cc\", \"ui.cc\", \"paint.cc\", \"qt/sidebar.cc\", \"qt/onroad.cc\",\n          \"qt/window.cc\", \"qt/home.cc\", \"qt/offroad/settings.cc\",\n          \"qt/offroad/onboarding.cc\", \"qt/offroad/driverview.cc\",\n          \"#phonelibs/nanovg/nanovg.c\"]\nqt_env.Program(\"_ui\", qt_src + [asset_obj], LIBS=qt_libs)\n\n\n# setup, factory resetter, and agnos updater\nif arch != 'aarch64' and GetOption('setup'):\n\n  qt_env.Program(\"qt/setup/reset\", [\"qt/setup/reset.cc\"], LIBS=qt_libs)\n  qt_env.Program(\"qt/setup/updater\", [\"qt/setup/updater.cc\", asset_obj], LIBS=qt_libs)\n  qt_env.Program(\"qt/setup/setup\", [\"qt/setup/setup.cc\", asset_obj],\n                 LIBS=qt_libs + ['curl', 'common', 'json11'])\n\n\n# build installers\nif GetOption('setup'):\n  senv = qt_env.Clone()\n  senv['LINKFLAGS'].append('-Wl,-strip-debug')\n\n  release = \"release3\" if arch == 'larch64' else \"release2\"\n  dashcam = \"dashcam3\" if arch == 'larch64' else \"dashcam\"\n  installers = [\n    (\"openpilot\", release),\n    (\"openpilot_test\", f\"{release}-staging\"),\n    (\"openpilot_nightly\", \"master-ci\"),\n    (\"openpilot_internal\", \"master\"),\n    (\"dashcam\", dashcam),\n    (\"dashcam_test\", f\"{dashcam}-staging\"),\n  ]\n\n  cont = {}\n  for brand in (\"openpilot\", \"dashcam\"):\n    cont[brand] = senv.Command(f\"installer/continue_{brand}.o\", f\"installer/continue_{brand}.sh\",\n                               \"ld -r -b binary -o $TARGET $SOURCE\")\n  for name, branch in installers:\n    brand = \"dashcam\" if \"dashcam\" in branch else \"openpilot\"\n    d = {'BRANCH': f\"'\\\"{branch}\\\"'\", 'BRAND': f\"'\\\"{brand}\\\"'\"}\n    if \"internal\" in name:\n      d['INTERNAL'] = \"1\"\n\n      import requests\n      r = requests.get(\"https://github.com/commaci2.keys\")\n      r.raise_for_status()\n      d['SSH_KEYS'] = f'\\\\\"{r.text.strip()}\\\\\"'\n    obj = senv.Object(f\"installer/installers/installer_{name}.o\", [\"installer/installer.cc\"], CPPDEFINES=d)\n    f = senv.Program(f\"installer/installers/installer_{name}\", [obj, cont[brand]], LIBS=qt_libs)\n    # keep installers small\n    assert f[0].get_size() < 300*1e3\n\n\n# build headless replay\nif arch in ['x86_64', 'Darwin'] and os.path.exists(Dir(\"#tools/\").get_abspath()):\n  qt_env['CXXFLAGS'] += [\"-Wno-deprecated-declarations\"]\n\n  replay_lib_src = [\"replay/replay.cc\", \"replay/filereader.cc\", \"replay/framereader.cc\"]\n\n  replay_lib = qt_env.Library(\"qt_replay\", replay_lib_src, LIBS=base_libs)\n  replay_libs = [replay_lib, 'avutil', 'avcodec', 'avformat', 'swscale', 'bz2'] + qt_libs\n  qt_env.Program(\"replay/replay\", [\"replay/main.cc\"], LIBS=replay_libs)\n"
  },
  {
    "path": "selfdrive/ui/main.cc",
    "content": "#include <sys/resource.h>\n\n#include <QApplication>\n#include <QSslConfiguration>\n\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/window.h\"\n\nint main(int argc, char *argv[]) {\n  setpriority(PRIO_PROCESS, 0, -20);\n\n  qInstallMessageHandler(swagLogMessageHandler);\n  initApp();\n\n  if (Hardware::EON()) {\n    QSslConfiguration ssl = QSslConfiguration::defaultConfiguration();\n    ssl.setCaCertificates(QSslCertificate::fromPath(\"/usr/etc/tls/cert.pem\"));\n    QSslConfiguration::setDefaultConfiguration(ssl);\n  }\n\n  QApplication a(argc, argv);\n  MainWindow w;\n  setMainWindow(&w);\n  a.installEventFilter(&w);\n  return a.exec();\n}\n"
  },
  {
    "path": "selfdrive/ui/paint.cc",
    "content": "#include \"selfdrive/ui/paint.h\"\n\n#include <algorithm>\n#include <cassert>\n\n#ifdef __APPLE__\n#include <OpenGL/gl3.h>\n#define NANOVG_GL3_IMPLEMENTATION\n#define nvgCreate nvgCreateGL3\n#else\n#include <GLES3/gl3.h>\n#define NANOVG_GLES3_IMPLEMENTATION\n#define nvgCreate nvgCreateGLES3\n#endif\n\n#define NANOVG_GLES3_IMPLEMENTATION\n#include <nanovg_gl.h>\n#include <nanovg_gl_utils.h>\n\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n\n#include \"selfdrive/ui/ui.h\"\n\nstatic void ui_draw_text(const UIState *s, float x, float y, const char *string, float size, NVGcolor color, const char *font_name) {\n  nvgFontFace(s->vg, font_name);\n  nvgFontSize(s->vg, size);\n  nvgFillColor(s->vg, color);\n  nvgText(s->vg, x, y, string, NULL);\n}\n\nstatic void draw_chevron(UIState *s, float x, float y, float sz, NVGcolor fillColor, NVGcolor glowColor) {\n  // glow\n  float g_xo = sz/5;\n  float g_yo = sz/10;\n  nvgBeginPath(s->vg);\n  nvgMoveTo(s->vg, x+(sz*1.35)+g_xo, y+sz+g_yo);\n  nvgLineTo(s->vg, x, y-g_xo);\n  nvgLineTo(s->vg, x-(sz*1.35)-g_xo, y+sz+g_yo);\n  nvgClosePath(s->vg);\n  nvgFillColor(s->vg, glowColor);\n  nvgFill(s->vg);\n\n  // chevron\n  nvgBeginPath(s->vg);\n  nvgMoveTo(s->vg, x+(sz*1.25), y+sz);\n  nvgLineTo(s->vg, x, y);\n  nvgLineTo(s->vg, x-(sz*1.25), y+sz);\n  nvgClosePath(s->vg);\n  nvgFillColor(s->vg, fillColor);\n  nvgFill(s->vg);\n}\n\nstatic void ui_draw_circle_image(const UIState *s, int center_x, int center_y, int radius, const char *image, NVGcolor color, float img_alpha) {\n  nvgBeginPath(s->vg);\n  nvgCircle(s->vg, center_x, center_y, radius);\n  nvgFillColor(s->vg, color);\n  nvgFill(s->vg);\n  const int img_size = radius * 1.5;\n  ui_draw_image(s, {center_x - (img_size / 2), center_y - (img_size / 2), img_size, img_size}, image, img_alpha);\n}\n\nstatic void ui_draw_circle_image(const UIState *s, int center_x, int center_y, int radius, const char *image, bool active) {\n  float bg_alpha = active ? 0.3f : 0.1f;\n  float img_alpha = active ? 1.0f : 0.15f;\n  ui_draw_circle_image(s, center_x, center_y, radius, image, nvgRGBA(0, 0, 0, (255 * bg_alpha)), img_alpha);\n}\n\nstatic void draw_lead(UIState *s, const cereal::ModelDataV2::LeadDataV3::Reader &lead_data, const vertex_data &vd) {\n  // Draw lead car indicator\n  auto [x, y] = vd;\n\n  float fillAlpha = 0;\n  float speedBuff = 10.;\n  float leadBuff = 40.;\n  float d_rel = lead_data.getX()[0];\n  float v_rel = lead_data.getV()[0];\n  if (d_rel < leadBuff) {\n    fillAlpha = 255*(1.0-(d_rel/leadBuff));\n    if (v_rel < 0) {\n      fillAlpha += 255*(-1*(v_rel/speedBuff));\n    }\n    fillAlpha = (int)(fmin(fillAlpha, 255));\n  }\n\n  float sz = std::clamp((25 * 30) / (d_rel / 3 + 30), 15.0f, 30.0f) * 2.35;\n  x = std::clamp(x, 0.f, s->fb_w - sz / 2);\n  y = std::fmin(s->fb_h - sz * .6, y);\n  draw_chevron(s, x, y, sz, nvgRGBA(201, 34, 49, fillAlpha), COLOR_YELLOW);\n}\n\nstatic void ui_draw_line(UIState *s, const line_vertices_data &vd, NVGcolor *color, NVGpaint *paint) {\n  if (vd.cnt == 0) return;\n\n  const vertex_data *v = &vd.v[0];\n  nvgBeginPath(s->vg);\n  nvgMoveTo(s->vg, v[0].x, v[0].y);\n  for (int i = 1; i < vd.cnt; i++) {\n    nvgLineTo(s->vg, v[i].x, v[i].y);\n  }\n  nvgClosePath(s->vg);\n  if (color) {\n    nvgFillColor(s->vg, *color);\n  } else if (paint) {\n    nvgFillPaint(s->vg, *paint);\n  }\n  nvgFill(s->vg);\n}\n\nstatic void draw_vision_frame(UIState *s) {\n  glBindVertexArray(s->frame_vao);\n  mat4 *out_mat = &s->rear_frame_mat;\n  glActiveTexture(GL_TEXTURE0);\n\n  if (s->last_frame) {\n    glBindTexture(GL_TEXTURE_2D, s->texture[s->last_frame->idx]->frame_tex);\n    if (!Hardware::EON()) {\n      // this is handled in ion on QCOM\n      glTexImage2D(GL_TEXTURE_2D, 0, GL_RGB, s->last_frame->width, s->last_frame->height,\n                   0, GL_RGB, GL_UNSIGNED_BYTE, s->last_frame->addr);\n    }\n  }\n\n  glUseProgram(s->gl_shader->prog);\n  glUniform1i(s->gl_shader->getUniformLocation(\"uTexture\"), 0);\n  glUniformMatrix4fv(s->gl_shader->getUniformLocation(\"uTransform\"), 1, GL_TRUE, out_mat->v);\n\n  assert(glGetError() == GL_NO_ERROR);\n  glEnableVertexAttribArray(0);\n  glDrawElements(GL_TRIANGLES, 6, GL_UNSIGNED_BYTE, (const void *)0);\n  glDisableVertexAttribArray(0);\n  glBindVertexArray(0);\n}\n\nstatic void ui_draw_vision_lane_lines(UIState *s) {\n  const UIScene &scene = s->scene;\n  NVGpaint track_bg;\n  if (!scene.end_to_end) {\n    // paint lanelines\n    for (int i = 0; i < std::size(scene.lane_line_vertices); i++) {\n      NVGcolor color = nvgRGBAf(1.0, 1.0, 1.0, scene.lane_line_probs[i]);\n      ui_draw_line(s, scene.lane_line_vertices[i], &color, nullptr);\n    }\n\n    // paint road edges\n    for (int i = 0; i < std::size(scene.road_edge_vertices); i++) {\n      NVGcolor color = nvgRGBAf(1.0, 0.0, 0.0, std::clamp<float>(1.0 - scene.road_edge_stds[i], 0.0, 1.0));\n      ui_draw_line(s, scene.road_edge_vertices[i], &color, nullptr);\n    }\n    track_bg = nvgLinearGradient(s->vg, s->fb_w, s->fb_h, s->fb_w, s->fb_h * .4,\n                                          COLOR_WHITE, COLOR_WHITE_ALPHA(0));\n  } else {\n    track_bg = nvgLinearGradient(s->vg, s->fb_w, s->fb_h, s->fb_w, s->fb_h * .4,\n                                          COLOR_RED, COLOR_RED_ALPHA(0));\n  }\n  // paint path\n  ui_draw_line(s, scene.track_vertices, nullptr, &track_bg);\n}\n\n// Draw all world space objects.\nstatic void ui_draw_world(UIState *s) {\n  nvgScissor(s->vg, 0, 0, s->fb_w, s->fb_h);\n\n  // Draw lane edges and vision/mpc tracks\n  ui_draw_vision_lane_lines(s);\n\n  // Draw lead indicators if openpilot is handling longitudinal\n  if (s->scene.longitudinal_control) {\n    auto lead_one = (*s->sm)[\"modelV2\"].getModelV2().getLeadsV3()[0];\n    auto lead_two = (*s->sm)[\"modelV2\"].getModelV2().getLeadsV3()[1];\n    if (lead_one.getProb() > .5) {\n      draw_lead(s, lead_one, s->scene.lead_vertices[0]);\n    }\n   if (lead_two.getProb() > .5 && (std::abs(lead_one.getX()[0] - lead_two.getX()[0]) > 3.0)) {\n      draw_lead(s, lead_two, s->scene.lead_vertices[1]);\n    }\n  }\n  nvgResetScissor(s->vg);\n}\n\nstatic void ui_draw_vision_maxspeed(UIState *s) {\n  const int SET_SPEED_NA = 255;\n  float maxspeed = (*s->sm)[\"controlsState\"].getControlsState().getVCruise();\n  const bool is_cruise_set = maxspeed != 0 && maxspeed != SET_SPEED_NA;\n  if (is_cruise_set && !s->scene.is_metric) { maxspeed *= 0.6225; }\n\n  const Rect rect = {bdr_s * 2, int(bdr_s * 1.5), 184, 202};\n  ui_fill_rect(s->vg, rect, COLOR_BLACK_ALPHA(100), 30.);\n  ui_draw_rect(s->vg, rect, COLOR_WHITE_ALPHA(100), 10, 20.);\n\n  nvgTextAlign(s->vg, NVG_ALIGN_CENTER | NVG_ALIGN_BASELINE);\n  ui_draw_text(s, rect.centerX(), 118, \"MAX\", 26 * 2.5, COLOR_WHITE_ALPHA(is_cruise_set ? 200 : 100), \"sans-regular\");\n  if (is_cruise_set) {\n    const std::string maxspeed_str = std::to_string((int)std::nearbyint(maxspeed));\n    ui_draw_text(s, rect.centerX(), 212, maxspeed_str.c_str(), 48 * 2.5, COLOR_WHITE, \"sans-bold\");\n  } else {\n    ui_draw_text(s, rect.centerX(), 212, \"N/A\", 42 * 2.5, COLOR_WHITE_ALPHA(100), \"sans-semibold\");\n  }\n}\n\nstatic void ui_draw_vision_speed(UIState *s) {\n  const float speed = std::max(0.0, (*s->sm)[\"carState\"].getCarState().getVEgo() * (s->scene.is_metric ? 3.6 : 2.2369363));\n  const std::string speed_str = std::to_string((int)std::nearbyint(speed));\n  nvgTextAlign(s->vg, NVG_ALIGN_CENTER | NVG_ALIGN_BASELINE);\n  ui_draw_text(s, s->fb_w/2, 210, speed_str.c_str(), 96 * 2.5, COLOR_WHITE, \"sans-bold\");\n  ui_draw_text(s, s->fb_w/2, 290, s->scene.is_metric ? \"km/h\" : \"mph\", 36 * 2.5, COLOR_WHITE_ALPHA(200), \"sans-regular\");\n}\n\nstatic void ui_draw_vision_event(UIState *s) {\n  if (s->scene.engageable) {\n    // draw steering wheel\n    const int radius = 96;\n    const int center_x = s->fb_w - radius - bdr_s * 2;\n    const int center_y = radius  + (bdr_s * 1.5);\n    const QColor &color = bg_colors[s->status];\n    NVGcolor nvg_color = nvgRGBA(color.red(), color.green(), color.blue(), color.alpha());\n    ui_draw_circle_image(s, center_x, center_y, radius, \"wheel\", nvg_color, 1.0f);\n  }\n}\n\nstatic void ui_draw_vision_face(UIState *s) {\n  const int radius = 96;\n  const int center_x = radius + (bdr_s * 2);\n  const int center_y = s->fb_h - footer_h / 2;\n  ui_draw_circle_image(s, center_x, center_y, radius, \"driver_face\", s->scene.dm_active);\n}\n\nstatic void ui_draw_vision_header(UIState *s) {\n  NVGpaint gradient = nvgLinearGradient(s->vg, 0, header_h - (header_h / 2.5), 0, header_h,\n                                        nvgRGBAf(0, 0, 0, 0.45), nvgRGBAf(0, 0, 0, 0));\n  ui_fill_rect(s->vg, {0, 0, s->fb_w , header_h}, gradient);\n  ui_draw_vision_maxspeed(s);\n  ui_draw_vision_speed(s);\n  ui_draw_vision_event(s);\n}\n\nstatic void ui_draw_vision(UIState *s) {\n  const UIScene *scene = &s->scene;\n  // Draw augmented elements\n  if (scene->world_objects_visible) {\n    ui_draw_world(s);\n  }\n  // Set Speed, Current Speed, Status/Events\n  ui_draw_vision_header(s);\n  if ((*s->sm)[\"controlsState\"].getControlsState().getAlertSize() == cereal::ControlsState::AlertSize::NONE) {\n    ui_draw_vision_face(s);\n  }\n}\n\nvoid ui_draw(UIState *s, int w, int h) {\n  const bool draw_vision = s->scene.started && s->vipc_client->connected;\n\n  glViewport(0, 0, s->fb_w, s->fb_h);\n  if (draw_vision) {\n    draw_vision_frame(s);\n  }\n  glEnable(GL_BLEND);\n  glBlendFunc(GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);\n  // NVG drawing functions - should be no GL inside NVG frame\n  nvgBeginFrame(s->vg, s->fb_w, s->fb_h, 1.0f);\n  if (draw_vision) {\n    ui_draw_vision(s);\n  }\n  nvgEndFrame(s->vg);\n  glDisable(GL_BLEND);\n}\n\nvoid ui_draw_image(const UIState *s, const Rect &r, const char *name, float alpha) {\n  nvgBeginPath(s->vg);\n  NVGpaint imgPaint = nvgImagePattern(s->vg, r.x, r.y, r.w, r.h, 0, s->images.at(name), alpha);\n  nvgRect(s->vg, r.x, r.y, r.w, r.h);\n  nvgFillPaint(s->vg, imgPaint);\n  nvgFill(s->vg);\n}\n\nvoid ui_draw_rect(NVGcontext *vg, const Rect &r, NVGcolor color, int width, float radius) {\n  nvgBeginPath(vg);\n  radius > 0 ? nvgRoundedRect(vg, r.x, r.y, r.w, r.h, radius) : nvgRect(vg, r.x, r.y, r.w, r.h);\n  nvgStrokeColor(vg, color);\n  nvgStrokeWidth(vg, width);\n  nvgStroke(vg);\n}\n\nstatic inline void fill_rect(NVGcontext *vg, const Rect &r, const NVGcolor *color, const NVGpaint *paint, float radius) {\n  nvgBeginPath(vg);\n  radius > 0 ? nvgRoundedRect(vg, r.x, r.y, r.w, r.h, radius) : nvgRect(vg, r.x, r.y, r.w, r.h);\n  if (color) nvgFillColor(vg, *color);\n  if (paint) nvgFillPaint(vg, *paint);\n  nvgFill(vg);\n}\nvoid ui_fill_rect(NVGcontext *vg, const Rect &r, const NVGcolor &color, float radius) {\n  fill_rect(vg, r, &color, nullptr, radius);\n}\nvoid ui_fill_rect(NVGcontext *vg, const Rect &r, const NVGpaint &paint, float radius) {\n  fill_rect(vg, r, nullptr, &paint, radius);\n}\n\nstatic const char frame_vertex_shader[] =\n#ifdef NANOVG_GL3_IMPLEMENTATION\n  \"#version 150 core\\n\"\n#else\n  \"#version 300 es\\n\"\n#endif\n  \"in vec4 aPosition;\\n\"\n  \"in vec4 aTexCoord;\\n\"\n  \"uniform mat4 uTransform;\\n\"\n  \"out vec4 vTexCoord;\\n\"\n  \"void main() {\\n\"\n  \"  gl_Position = uTransform * aPosition;\\n\"\n  \"  vTexCoord = aTexCoord;\\n\"\n  \"}\\n\";\n\nstatic const char frame_fragment_shader[] =\n#ifdef NANOVG_GL3_IMPLEMENTATION\n  \"#version 150 core\\n\"\n#else\n  \"#version 300 es\\n\"\n#endif\n  \"precision mediump float;\\n\"\n  \"uniform sampler2D uTexture;\\n\"\n  \"in vec4 vTexCoord;\\n\"\n  \"out vec4 colorOut;\\n\"\n  \"void main() {\\n\"\n  \"  colorOut = texture(uTexture, vTexCoord.xy);\\n\"\n#ifdef QCOM\n  \"  vec3 dz = vec3(0.0627f, 0.0627f, 0.0627f);\\n\"\n  \"  colorOut.rgb = ((vec3(1.0f, 1.0f, 1.0f) - dz) * colorOut.rgb / vec3(1.0f, 1.0f, 1.0f)) + dz;\\n\"\n#endif\n  \"}\\n\";\n\nstatic const mat4 device_transform = {{\n  1.0,  0.0, 0.0, 0.0,\n  0.0,  1.0, 0.0, 0.0,\n  0.0,  0.0, 1.0, 0.0,\n  0.0,  0.0, 0.0, 1.0,\n}};\n\nvoid ui_nvg_init(UIState *s) {\n  // init drawing\n\n  // on EON, we enable MSAA\n  s->vg = Hardware::EON() ? nvgCreate(0) : nvgCreate(NVG_ANTIALIAS | NVG_STENCIL_STROKES | NVG_DEBUG);\n  assert(s->vg);\n\n  // init fonts\n  std::pair<const char *, const char *> fonts[] = {\n      {\"sans-regular\", \"../assets/fonts/opensans_regular.ttf\"},\n      {\"sans-semibold\", \"../assets/fonts/opensans_semibold.ttf\"},\n      {\"sans-bold\", \"../assets/fonts/opensans_bold.ttf\"},\n  };\n  for (auto [name, file] : fonts) {\n    int font_id = nvgCreateFont(s->vg, name, file);\n    assert(font_id >= 0);\n  }\n\n  // init images\n  std::vector<std::pair<const char *, const char *>> images = {\n    {\"wheel\", \"../assets/img_chffr_wheel.png\"},\n    {\"driver_face\", \"../assets/img_driver_face.png\"},\n  };\n  for (auto [name, file] : images) {\n    s->images[name] = nvgCreateImage(s->vg, file, 1);\n    assert(s->images[name] != 0);\n  }\n\n  // init gl\n  s->gl_shader = std::make_unique<GLShader>(frame_vertex_shader, frame_fragment_shader);\n  GLint frame_pos_loc = glGetAttribLocation(s->gl_shader->prog, \"aPosition\");\n  GLint frame_texcoord_loc = glGetAttribLocation(s->gl_shader->prog, \"aTexCoord\");\n\n  glViewport(0, 0, s->fb_w, s->fb_h);\n\n  glDisable(GL_DEPTH_TEST);\n\n  assert(glGetError() == GL_NO_ERROR);\n\n  float x1 = 1.0, x2 = 0.0, y1 = 1.0, y2 = 0.0;\n  const uint8_t frame_indicies[] = {0, 1, 2, 0, 2, 3};\n  const float frame_coords[4][4] = {\n    {-1.0, -1.0, x2, y1}, //bl\n    {-1.0,  1.0, x2, y2}, //tl\n    { 1.0,  1.0, x1, y2}, //tr\n    { 1.0, -1.0, x1, y1}, //br\n  };\n\n  glGenVertexArrays(1, &s->frame_vao);\n  glBindVertexArray(s->frame_vao);\n  glGenBuffers(1, &s->frame_vbo);\n  glBindBuffer(GL_ARRAY_BUFFER, s->frame_vbo);\n  glBufferData(GL_ARRAY_BUFFER, sizeof(frame_coords), frame_coords, GL_STATIC_DRAW);\n  glEnableVertexAttribArray(frame_pos_loc);\n  glVertexAttribPointer(frame_pos_loc, 2, GL_FLOAT, GL_FALSE,\n                        sizeof(frame_coords[0]), (const void *)0);\n  glEnableVertexAttribArray(frame_texcoord_loc);\n  glVertexAttribPointer(frame_texcoord_loc, 2, GL_FLOAT, GL_FALSE,\n                        sizeof(frame_coords[0]), (const void *)(sizeof(float) * 2));\n  glGenBuffers(1, &s->frame_ibo);\n  glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, s->frame_ibo);\n  glBufferData(GL_ELEMENT_ARRAY_BUFFER, sizeof(frame_indicies), frame_indicies, GL_STATIC_DRAW);\n  glBindBuffer(GL_ARRAY_BUFFER, 0);\n  glBindVertexArray(0);\n\n  ui_resize(s, s->fb_w, s->fb_h);\n}\n\nvoid ui_resize(UIState *s, int width, int height) {\n  s->fb_w = width;\n  s->fb_h = height;\n\n  auto intrinsic_matrix = s->wide_camera ? ecam_intrinsic_matrix : fcam_intrinsic_matrix;\n\n  float zoom = ZOOM / intrinsic_matrix.v[0];\n\n  if (s->wide_camera) {\n    zoom *= 0.5;\n  }\n\n  float zx = zoom * 2 * intrinsic_matrix.v[2] / width;\n  float zy = zoom * 2 * intrinsic_matrix.v[5] / height;\n\n  const mat4 frame_transform = {{\n    zx, 0.0, 0.0, 0.0,\n    0.0, zy, 0.0, -y_offset / height * 2,\n    0.0, 0.0, 1.0, 0.0,\n    0.0, 0.0, 0.0, 1.0,\n  }};\n\n  s->rear_frame_mat = matmul(device_transform, frame_transform);\n\n  // Apply transformation such that video pixel coordinates match video\n  // 1) Put (0, 0) in the middle of the video\n  nvgTranslate(s->vg, width / 2, height / 2 + y_offset);\n  // 2) Apply same scaling as video\n  nvgScale(s->vg, zoom, zoom);\n  // 3) Put (0, 0) in top left corner of video\n  nvgTranslate(s->vg, -intrinsic_matrix.v[2], -intrinsic_matrix.v[5]);\n\n  nvgCurrentTransform(s->vg, s->car_space_transform);\n  nvgResetTransform(s->vg);\n}\n"
  },
  {
    "path": "selfdrive/ui/paint.h",
    "content": "#pragma once\n\n#include \"selfdrive/ui/ui.h\"\n\nvoid ui_draw(UIState *s, int w, int h);\nvoid ui_draw_image(const UIState *s, const Rect &r, const char *name, float alpha);\nvoid ui_draw_rect(NVGcontext *vg, const Rect &r, NVGcolor color, int width, float radius = 0);\nvoid ui_fill_rect(NVGcontext *vg, const Rect &r, const NVGpaint &paint, float radius = 0);\nvoid ui_fill_rect(NVGcontext *vg, const Rect &r, const NVGcolor &color, float radius = 0);\nvoid ui_nvg_init(UIState *s);\nvoid ui_resize(UIState *s, int width, int height);\n"
  },
  {
    "path": "selfdrive/ui/qt/api.cc",
    "content": "#include \"selfdrive/ui/qt/api.h\"\n\n#include <openssl/bio.h>\n#include <openssl/pem.h>\n#include <openssl/rsa.h>\n\n#include <QCryptographicHash>\n#include <QDateTime>\n#include <QDebug>\n#include <QFile>\n#include <QJsonDocument>\n#include <QNetworkRequest>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/util.h\"\n\nnamespace CommaApi {\n\nQByteArray rsa_sign(const QByteArray &data) {\n  auto file = QFile(Path::rsa_file().c_str());\n  if (!file.open(QIODevice::ReadOnly)) {\n    qDebug() << \"No RSA private key found, please run manager.py or registration.py\";\n    return QByteArray();\n  }\n  auto key = file.readAll();\n  file.close();\n  file.deleteLater();\n  BIO* mem = BIO_new_mem_buf(key.data(), key.size());\n  assert(mem);\n  RSA* rsa_private = PEM_read_bio_RSAPrivateKey(mem, NULL, NULL, NULL);\n  assert(rsa_private);\n  auto sig = QByteArray();\n  sig.resize(RSA_size(rsa_private));\n  unsigned int sig_len;\n  int ret = RSA_sign(NID_sha256, (unsigned char*)data.data(), data.size(), (unsigned char*)sig.data(), &sig_len, rsa_private);\n  assert(ret == 1);\n  assert(sig_len == sig.size());\n  BIO_free(mem);\n  RSA_free(rsa_private);\n  return sig;\n}\n\nQString create_jwt(const QJsonObject &payloads, int expiry) {\n  QJsonObject header = {{\"alg\", \"RS256\"}};\n\n  auto t = QDateTime::currentSecsSinceEpoch();\n  QJsonObject payload = {{\"identity\", getDongleId().value_or(\"\")}, {\"nbf\", t}, {\"iat\", t}, {\"exp\", t + expiry}};\n  for (auto it = payloads.begin(); it != payloads.end(); ++it) {\n    payload.insert(it.key(), it.value());\n  }\n\n  auto b64_opts = QByteArray::Base64UrlEncoding | QByteArray::OmitTrailingEquals;\n  QString jwt = QJsonDocument(header).toJson(QJsonDocument::Compact).toBase64(b64_opts) + '.' +\n                QJsonDocument(payload).toJson(QJsonDocument::Compact).toBase64(b64_opts);\n\n  auto hash = QCryptographicHash::hash(jwt.toUtf8(), QCryptographicHash::Sha256);\n  auto sig = rsa_sign(hash);\n  jwt += '.' + sig.toBase64(b64_opts);\n  return jwt;\n}\n\n}  // namespace CommaApi\n\nHttpRequest::HttpRequest(QObject *parent, bool create_jwt, int timeout) : create_jwt(create_jwt), QObject(parent) {\n  networkAccessManager = new QNetworkAccessManager(this);\n\n  networkTimer = new QTimer(this);\n  networkTimer->setSingleShot(true);\n  networkTimer->setInterval(timeout);\n  connect(networkTimer, &QTimer::timeout, this, &HttpRequest::requestTimeout);\n}\n\nbool HttpRequest::active() {\n  return reply != nullptr;\n}\n\nvoid HttpRequest::sendRequest(const QString &requestURL, const HttpRequest::Method method) {\n  if (active()) {\n    qDebug() << \"HttpRequest is active\";\n    return;\n  }\n  QString token;\n  if(create_jwt) {\n    token = CommaApi::create_jwt();\n  } else {\n    QString token_json = QString::fromStdString(util::read_file(util::getenv(\"HOME\") + \"/.comma/auth.json\"));\n    QJsonDocument json_d = QJsonDocument::fromJson(token_json.toUtf8());\n    token = json_d[\"access_token\"].toString();\n  }\n\n  QNetworkRequest request;\n  request.setUrl(QUrl(requestURL));\n  request.setRawHeader(QByteArray(\"Authorization\"), (\"JWT \" + token).toUtf8());\n\n  if (method == HttpRequest::Method::GET) {\n    reply = networkAccessManager->get(request);\n  } else if (method == HttpRequest::Method::DELETE) {\n    reply = networkAccessManager->deleteResource(request);\n  }\n\n  networkTimer->start();\n  connect(reply, &QNetworkReply::finished, this, &HttpRequest::requestFinished);\n}\n\nvoid HttpRequest::requestTimeout() {\n  reply->abort();\n}\n\n// This function should always emit something\nvoid HttpRequest::requestFinished() {\n  bool success = false;\n  if (reply->error() != QNetworkReply::OperationCanceledError) {\n    networkTimer->stop();\n    QString response = reply->readAll();\n\n    if (reply->error() == QNetworkReply::NoError) {\n      success = true;\n      emit receivedResponse(response);\n    } else {\n      qDebug() << reply->errorString();\n      emit failedResponse(reply->errorString());\n    }\n  } else {\n    networkAccessManager->clearAccessCache();\n    networkAccessManager->clearConnectionCache();\n    emit timeoutResponse(\"timeout\");\n  }\n  emit requestDone(success);\n  reply->deleteLater();\n  reply = nullptr;\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/api.h",
    "content": "#pragma once\n\n#include <QJsonObject>\n#include <QNetworkReply>\n#include <QString>\n#include <QTimer>\n\n#include \"selfdrive/common/util.h\"\n\nnamespace CommaApi {\n\nconst QString BASE_URL = util::getenv(\"API_HOST\", \"https://api.commadotai.com\").c_str();\nQByteArray rsa_sign(const QByteArray &data);\nQString create_jwt(const QJsonObject &payloads = {}, int expiry = 3600);\n\n}  // namespace CommaApi\n\n/**\n * Makes a request to the request endpoint.\n */\n\nclass HttpRequest : public QObject {\n  Q_OBJECT\n\npublic:\n  enum class Method {GET, DELETE};\n\n  explicit HttpRequest(QObject* parent, bool create_jwt = true, int timeout = 20000);\n  void sendRequest(const QString &requestURL, const Method method = Method::GET);\n  bool active();\n\nprotected:\n  QNetworkReply *reply = nullptr;\n\nprivate:\n  QNetworkAccessManager *networkAccessManager = nullptr;\n  QTimer *networkTimer = nullptr;\n  bool create_jwt;\n\nprivate slots:\n  void requestTimeout();\n  void requestFinished();\n\nsignals:\n  void requestDone(bool success);\n  void receivedResponse(const QString &response);\n  void failedResponse(const QString &errorString);\n  void timeoutResponse(const QString &errorString);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/home.cc",
    "content": "#include \"selfdrive/ui/qt/home.h\"\n\n#include <QDateTime>\n#include <QHBoxLayout>\n#include <QMouseEvent>\n#include <QVBoxLayout>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/widgets/drive_stats.h\"\n#include \"selfdrive/ui/qt/widgets/prime.h\"\n\n// HomeWindow: the container for the offroad and onroad UIs\n\nHomeWindow::HomeWindow(QWidget* parent) : QWidget(parent) {\n  QHBoxLayout *main_layout = new QHBoxLayout(this);\n  main_layout->setMargin(0);\n  main_layout->setSpacing(0);\n\n  sidebar = new Sidebar(this);\n  main_layout->addWidget(sidebar);\n  QObject::connect(this, &HomeWindow::update, sidebar, &Sidebar::updateState);\n  QObject::connect(sidebar, &Sidebar::openSettings, this, &HomeWindow::openSettings);\n\n  slayout = new QStackedLayout();\n  main_layout->addLayout(slayout);\n\n  home = new OffroadHome();\n  slayout->addWidget(home);\n\n  onroad = new OnroadWindow(this);\n  slayout->addWidget(onroad);\n\n  QObject::connect(this, &HomeWindow::update, onroad, &OnroadWindow::updateStateSignal);\n  QObject::connect(this, &HomeWindow::offroadTransitionSignal, onroad, &OnroadWindow::offroadTransitionSignal);\n\n  driver_view = new DriverViewWindow(this);\n  connect(driver_view, &DriverViewWindow::done, [=] {\n    showDriverView(false);\n  });\n  slayout->addWidget(driver_view);\n  setAttribute(Qt::WA_NoSystemBackground);\n}\n\nvoid HomeWindow::showSidebar(bool show) {\n  sidebar->setVisible(show);\n}\n\nvoid HomeWindow::offroadTransition(bool offroad) {\n  sidebar->setVisible(offroad);\n  if (offroad) {\n    slayout->setCurrentWidget(home);\n  } else {\n    slayout->setCurrentWidget(onroad);\n  }\n  emit offroadTransitionSignal(offroad);\n}\n\nvoid HomeWindow::showDriverView(bool show) {\n  if (show) {\n    emit closeSettings();\n    slayout->setCurrentWidget(driver_view);\n  } else {\n    slayout->setCurrentWidget(home);\n  }\n  sidebar->setVisible(show == false);\n}\n\nvoid HomeWindow::mousePressEvent(QMouseEvent* e) {\n  // Handle sidebar collapsing\n  if (onroad->isVisible() && (!sidebar->isVisible() || e->x() > sidebar->width())) {\n    sidebar->setVisible(!sidebar->isVisible() && !onroad->isMapVisible());\n  }\n}\n\n// OffroadHome: the offroad home page\n\nOffroadHome::OffroadHome(QWidget* parent) : QFrame(parent) {\n  QVBoxLayout* main_layout = new QVBoxLayout(this);\n  main_layout->setContentsMargins(40, 40, 40, 45);\n\n  // top header\n  QHBoxLayout* header_layout = new QHBoxLayout();\n  header_layout->setContentsMargins(15, 15, 15, 0);\n  header_layout->setSpacing(16);\n\n  date = new QLabel();\n  header_layout->addWidget(date, 1, Qt::AlignHCenter | Qt::AlignLeft);\n\n  update_notif = new QPushButton(\"UPDATE\");\n  update_notif->setVisible(false);\n  update_notif->setStyleSheet(\"background-color: #364DEF;\");\n  QObject::connect(update_notif, &QPushButton::clicked, [=]() { center_layout->setCurrentIndex(1); });\n  header_layout->addWidget(update_notif, 0, Qt::AlignHCenter | Qt::AlignRight);\n\n  alert_notif = new QPushButton();\n  alert_notif->setVisible(false);\n  alert_notif->setStyleSheet(\"background-color: #E22C2C;\");\n  QObject::connect(alert_notif, &QPushButton::clicked, [=] { center_layout->setCurrentIndex(2); });\n  header_layout->addWidget(alert_notif, 0, Qt::AlignHCenter | Qt::AlignRight);\n\n  header_layout->addWidget(new QLabel(getBrandVersion()), 0, Qt::AlignHCenter | Qt::AlignRight);\n\n  main_layout->addLayout(header_layout);\n\n  // main content\n  main_layout->addSpacing(25);\n  center_layout = new QStackedLayout();\n\n  QWidget* statsAndSetupWidget = new QWidget(this);\n  QHBoxLayout* statsAndSetup = new QHBoxLayout(statsAndSetupWidget);\n  statsAndSetup->setMargin(0);\n  statsAndSetup->setSpacing(30);\n  statsAndSetup->addWidget(new DriveStats, 1);\n  statsAndSetup->addWidget(new SetupWidget);\n\n  center_layout->addWidget(statsAndSetupWidget);\n\n  // add update & alerts widgets\n  update_widget = new UpdateAlert();\n  QObject::connect(update_widget, &UpdateAlert::dismiss, [=]() { center_layout->setCurrentIndex(0); });\n  center_layout->addWidget(update_widget);\n  alerts_widget = new OffroadAlert();\n  QObject::connect(alerts_widget, &OffroadAlert::dismiss, [=]() { center_layout->setCurrentIndex(0); });\n  center_layout->addWidget(alerts_widget);\n\n  main_layout->addLayout(center_layout, 1);\n\n  // set up refresh timer\n  timer = new QTimer(this);\n  timer->callOnTimeout(this, &OffroadHome::refresh);\n\n  setStyleSheet(R\"(\n    * {\n     color: white;\n    }\n    OffroadHome {\n      background-color: black;\n    }\n    OffroadHome > QPushButton {\n      padding: 15px 30px;\n      border-radius: 5px;\n      font-size: 40px;\n      font-weight: 500;\n    }\n    OffroadHome > QLabel {\n      font-size: 55px;\n    }\n  )\");\n}\n\nvoid OffroadHome::showEvent(QShowEvent *event) {\n  refresh();\n  timer->start(10 * 1000);\n}\n\nvoid OffroadHome::hideEvent(QHideEvent *event) {\n  timer->stop();\n}\n\nvoid OffroadHome::refresh() {\n  date->setText(QDateTime::currentDateTime().toString(\"dddd, MMMM d\"));\n\n  bool updateAvailable = update_widget->refresh();\n  int alerts = alerts_widget->refresh();\n\n  // pop-up new notification\n  int idx = center_layout->currentIndex();\n  if (!updateAvailable && !alerts) {\n    idx = 0;\n  } else if (updateAvailable && (!update_notif->isVisible() || (!alerts && idx == 2))) {\n    idx = 1;\n  } else if (alerts && (!alert_notif->isVisible() || (!updateAvailable && idx == 1))) {\n    idx = 2;\n  }\n  center_layout->setCurrentIndex(idx);\n\n  update_notif->setVisible(updateAvailable);\n  alert_notif->setVisible(alerts);\n  if (alerts) {\n    alert_notif->setText(QString::number(alerts) + \" ALERT\" + (alerts > 1 ? \"S\" : \"\"));\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/home.h",
    "content": "#pragma once\n\n#include <QFrame>\n#include <QLabel>\n#include <QPushButton>\n#include <QStackedLayout>\n#include <QTimer>\n#include <QWidget>\n\n#include \"selfdrive/ui/qt/offroad/driverview.h\"\n#include \"selfdrive/ui/qt/onroad.h\"\n#include \"selfdrive/ui/qt/sidebar.h\"\n#include \"selfdrive/ui/qt/widgets/offroad_alerts.h\"\n#include \"selfdrive/ui/ui.h\"\n\nclass OffroadHome : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit OffroadHome(QWidget* parent = 0);\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n  void hideEvent(QHideEvent *event) override;\n  void refresh();\n\n  QTimer* timer;\n  QLabel* date;\n  QStackedLayout* center_layout;\n  UpdateAlert *update_widget;\n  OffroadAlert* alerts_widget;\n  QPushButton* alert_notif;\n  QPushButton* update_notif;\n};\n\nclass HomeWindow : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit HomeWindow(QWidget* parent = 0);\n\nsignals:\n  void openSettings();\n  void closeSettings();\n\n  // forwarded signals\n  void displayPowerChanged(bool on);\n  void update(const UIState &s);\n  void offroadTransitionSignal(bool offroad);\n\npublic slots:\n  void offroadTransition(bool offroad);\n  void showDriverView(bool show);\n  void showSidebar(bool show);\n\nprotected:\n  void mousePressEvent(QMouseEvent* e) override;\n\nprivate:\n  Sidebar *sidebar;\n  OffroadHome *home;\n  OnroadWindow *onroad;\n  DriverViewWindow *driver_view;\n  QStackedLayout *slayout;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/maps/map.cc",
    "content": "#include \"selfdrive/ui/qt/maps/map.h\"\n\n#include <cmath>\n\n#include <QDebug>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/ui/ui.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/maps/map_helpers.h\"\n#include \"selfdrive/ui/qt/request_repeater.h\"\n\n\nconst int PAN_TIMEOUT = 100;\nconst qreal REROUTE_DISTANCE = 25;\nconst float MANEUVER_TRANSITION_THRESHOLD = 10;\n\nconst float MAX_ZOOM = 17;\nconst float MIN_ZOOM = 14;\nconst float MAX_PITCH = 50;\nconst float MIN_PITCH = 0;\nconst float MAP_SCALE = 2;\n\n\nMapWindow::MapWindow(const QMapboxGLSettings &settings) :\n  m_settings(settings), velocity_filter(0, 10, 0.1) {\n  sm = new SubMaster({\"liveLocationKalman\"});\n\n  timer = new QTimer(this);\n  QObject::connect(timer, SIGNAL(timeout()), this, SLOT(timerUpdate()));\n  timer->start(100);\n\n  recompute_timer = new QTimer(this);\n  QObject::connect(recompute_timer, SIGNAL(timeout()), this, SLOT(recomputeRoute()));\n  recompute_timer->start(1000);\n\n  // Instructions\n  map_instructions = new MapInstructions(this);\n  QObject::connect(this, &MapWindow::instructionsChanged, map_instructions, &MapInstructions::updateInstructions);\n  QObject::connect(this, &MapWindow::distanceChanged, map_instructions, &MapInstructions::updateDistance);\n  map_instructions->setFixedWidth(width());\n  map_instructions->setVisible(false);\n\n  map_eta = new MapETA(this);\n  QObject::connect(this, &MapWindow::ETAChanged, map_eta, &MapETA::updateETA);\n\n  const int h = 120;\n  map_eta->setFixedHeight(h);\n  map_eta->move(25, 1080 - h - bdr_s*2);\n  map_eta->setVisible(false);\n\n  // Routing\n  QVariantMap parameters;\n  parameters[\"mapbox.access_token\"] = m_settings.accessToken();\n\n  geoservice_provider = new QGeoServiceProvider(\"mapbox\", parameters);\n  routing_manager = geoservice_provider->routingManager();\n  if (routing_manager == nullptr) {\n    qDebug() << geoservice_provider->errorString();\n    assert(routing_manager);\n  }\n  QObject::connect(routing_manager, &QGeoRoutingManager::finished, this, &MapWindow::routeCalculated);\n\n  auto last_gps_position = coordinate_from_param(\"LastGPSPosition\");\n  if (last_gps_position) {\n    last_position = *last_gps_position;\n  }\n\n  grabGesture(Qt::GestureType::PinchGesture);\n}\n\nMapWindow::~MapWindow() {\n  makeCurrent();\n}\n\nvoid MapWindow::initLayers() {\n  // This doesn't work from initializeGL\n  if (!m_map->layerExists(\"modelPathLayer\")) {\n    qDebug() << \"Initializing modelPathLayer\";\n    QVariantMap modelPath;\n    modelPath[\"id\"] = \"modelPathLayer\";\n    modelPath[\"type\"] = \"line\";\n    modelPath[\"source\"] = \"modelPathSource\";\n    m_map->addLayer(modelPath);\n    m_map->setPaintProperty(\"modelPathLayer\", \"line-color\", QColor(\"red\"));\n    m_map->setPaintProperty(\"modelPathLayer\", \"line-width\", 5.0);\n    m_map->setLayoutProperty(\"modelPathLayer\", \"line-cap\", \"round\");\n  }\n  if (!m_map->layerExists(\"navLayer\")) {\n    qDebug() << \"Initializing navLayer\";\n    QVariantMap nav;\n    nav[\"id\"] = \"navLayer\";\n    nav[\"type\"] = \"line\";\n    nav[\"source\"] = \"navSource\";\n    m_map->addLayer(nav, \"road-intersection\");\n    m_map->setPaintProperty(\"navLayer\", \"line-color\", QColor(\"#31a1ee\"));\n    m_map->setPaintProperty(\"navLayer\", \"line-width\", 7.5);\n    m_map->setLayoutProperty(\"navLayer\", \"line-cap\", \"round\");\n  }\n  if (!m_map->layerExists(\"carPosLayer\")) {\n    qDebug() << \"Initializing carPosLayer\";\n    m_map->addImage(\"label-arrow\", QImage(\"../assets/images/triangle.svg\"));\n\n    QVariantMap carPos;\n    carPos[\"id\"] = \"carPosLayer\";\n    carPos[\"type\"] = \"symbol\";\n    carPos[\"source\"] = \"carPosSource\";\n    m_map->addLayer(carPos);\n    m_map->setLayoutProperty(\"carPosLayer\", \"icon-pitch-alignment\", \"map\");\n    m_map->setLayoutProperty(\"carPosLayer\", \"icon-image\", \"label-arrow\");\n    m_map->setLayoutProperty(\"carPosLayer\", \"icon-size\", 0.5);\n    m_map->setLayoutProperty(\"carPosLayer\", \"icon-ignore-placement\", true);\n    m_map->setLayoutProperty(\"carPosLayer\", \"icon-allow-overlap\", true);\n    m_map->setLayoutProperty(\"carPosLayer\", \"symbol-sort-key\", 0);\n  }\n}\n\nvoid MapWindow::timerUpdate() {\n  if (!QUIState::ui_state.scene.started) {\n    return;\n  }\n\n  if (isVisible()) {\n    update();\n  }\n\n  sm->update(0);\n  if (sm->updated(\"liveLocationKalman\")) {\n    auto location = (*sm)[\"liveLocationKalman\"].getLiveLocationKalman();\n    gps_ok = location.getGpsOK();\n\n    localizer_valid = location.getStatus() == cereal::LiveLocationKalman::Status::VALID;\n\n    if (localizer_valid) {\n      auto pos = location.getPositionGeodetic();\n      auto orientation = location.getCalibratedOrientationNED();\n\n      float velocity = location.getVelocityCalibrated().getValue()[0];\n      float bearing = RAD2DEG(orientation.getValue()[2]);\n      auto coordinate = QMapbox::Coordinate(pos.getValue()[0], pos.getValue()[1]);\n\n      last_position = coordinate;\n      last_bearing = bearing;\n      velocity_filter.update(velocity);\n    }\n  }\n\n  if (m_map.isNull()) {\n    return;\n  }\n\n  loaded_once = loaded_once || m_map->isFullyLoaded();\n  if (!loaded_once) {\n    map_instructions->showError(\"Map Loading\");\n    return;\n  }\n\n  initLayers();\n\n  if (!localizer_valid) {\n    map_instructions->showError(\"Waiting for GPS\");\n    return;\n  }\n\n  if (pan_counter == 0) {\n    if (last_position) m_map->setCoordinate(*last_position);\n    if (last_bearing) m_map->setBearing(*last_bearing);\n  } else {\n    pan_counter--;\n  }\n\n  if (zoom_counter == 0) {\n    m_map->setZoom(util::map_val<float>(velocity_filter.x(), 0, 30, MAX_ZOOM, MIN_ZOOM));\n  } else {\n    zoom_counter--;\n  }\n\n  // Update current location marker\n  auto point = coordinate_to_collection(*last_position);\n  QMapbox::Feature feature1(QMapbox::Feature::PointType, point, {}, {});\n  QVariantMap carPosSource;\n  carPosSource[\"type\"] = \"geojson\";\n  carPosSource[\"data\"] = QVariant::fromValue<QMapbox::Feature>(feature1);\n  m_map->updateSource(\"carPosSource\", carPosSource);\n\n  // Show route instructions\n  if (segment.isValid()) {\n    auto cur_maneuver = segment.maneuver();\n    auto attrs = cur_maneuver.extendedAttributes();\n    if (cur_maneuver.isValid() && attrs.contains(\"mapbox.banner_instructions\")) {\n      float along_geometry = distance_along_geometry(segment.path(), to_QGeoCoordinate(*last_position));\n      float distance_to_maneuver = segment.distance() - along_geometry;\n      emit distanceChanged(std::max(0.0f, distance_to_maneuver));\n\n      m_map->setPitch(MAX_PITCH); // TODO: smooth pitching based on maneuver distance\n\n      auto banner = attrs[\"mapbox.banner_instructions\"].toList();\n      if (banner.size()) {\n        auto banner_0 = banner[0].toMap();\n        float show_at = banner_0[\"distance_along_geometry\"].toDouble();\n        emit instructionsChanged(banner_0, distance_to_maneuver < show_at);\n      }\n\n      // Transition to next route segment\n      if (!shouldRecompute() && (distance_to_maneuver < -MANEUVER_TRANSITION_THRESHOLD)) {\n        auto next_segment = segment.nextRouteSegment();\n        if (next_segment.isValid()) {\n          segment = next_segment;\n\n          recompute_backoff = std::max(0, recompute_backoff - 1);\n          recompute_countdown = 0;\n        } else {\n          qWarning() << \"Destination reached\";\n          Params().remove(\"NavDestination\");\n\n          // Clear route if driving away from destination\n          float d = segment.maneuver().position().distanceTo(to_QGeoCoordinate(*last_position));\n          if (d > REROUTE_DISTANCE) {\n            clearRoute();\n          }\n        }\n      }\n    }\n  }\n}\n\nvoid MapWindow::resizeGL(int w, int h) {\n  m_map->resize(size() / MAP_SCALE);\n  map_instructions->setFixedWidth(width());\n}\n\nvoid MapWindow::initializeGL() {\n  m_map.reset(new QMapboxGL(this, m_settings, size(), 1));\n\n  if (last_position) {\n    m_map->setCoordinateZoom(*last_position, MAX_ZOOM);\n  } else {\n    m_map->setCoordinateZoom(QMapbox::Coordinate(64.31990695292795, -149.79038934046247), MIN_ZOOM);\n  }\n\n  m_map->setMargins({0, 350, 0, 50});\n  m_map->setPitch(MIN_PITCH);\n  m_map->setStyleUrl(\"mapbox://styles/commaai/ckr64tlwp0azb17nqvr9fj13s\");\n\n  connect(m_map.data(), SIGNAL(needsRendering()), this, SLOT(update()));\n  QObject::connect(m_map.data(), &QMapboxGL::mapChanged, [=](QMapboxGL::MapChange change) {\n    if (change == QMapboxGL::MapChange::MapChangeDidFinishLoadingMap) {\n      loaded_once = true;\n    }\n  });\n}\n\nvoid MapWindow::paintGL() {\n  if (!isVisible()) return;\n  m_map->render();\n}\n\nstatic float get_time_typical(const QGeoRouteSegment &segment) {\n  auto maneuver = segment.maneuver();\n  auto attrs = maneuver.extendedAttributes();\n  return attrs.contains(\"mapbox.duration_typical\") ? attrs[\"mapbox.duration_typical\"].toDouble() : segment.travelTime();\n}\n\n\nvoid MapWindow::recomputeRoute() {\n  if (!QUIState::ui_state.scene.started) {\n    return;\n  }\n\n  if (!last_position) {\n    return;\n  }\n\n  auto new_destination = coordinate_from_param(\"NavDestination\");\n  if (!new_destination) {\n    clearRoute();\n    return;\n  }\n\n  bool should_recompute = shouldRecompute();\n  if (*new_destination != nav_destination) {\n    qWarning() << \"Got new destination from NavDestination param\" << *new_destination;\n\n    // Only open the map on setting destination the first time\n    if (allow_open) {\n      setVisible(true); // Show map on destination set/change\n      allow_open = false;\n    }\n\n    // TODO: close sidebar\n\n    should_recompute = true;\n  }\n\n  if (!should_recompute) updateETA(); // ETA is updated after recompute\n\n  if (!gps_ok && segment.isValid()) return; // Don't recompute when gps drifts in tunnels\n\n  // Only do API request when map is fully loaded\n  if (loaded_once) {\n    if (recompute_countdown == 0 && should_recompute) {\n      recompute_countdown = std::pow(2, recompute_backoff);\n      recompute_backoff = std::min(7, recompute_backoff + 1);\n      calculateRoute(*new_destination);\n    } else {\n      recompute_countdown = std::max(0, recompute_countdown - 1);\n    }\n  }\n}\n\nvoid MapWindow::updateETA() {\n  if (segment.isValid()) {\n    float progress = distance_along_geometry(segment.path(), to_QGeoCoordinate(*last_position)) / segment.distance();\n    float total_distance = segment.distance() * (1.0 - progress);\n    float total_time = segment.travelTime() * (1.0 - progress);\n    float total_time_typical = get_time_typical(segment) * (1.0 - progress);\n\n    auto s = segment.nextRouteSegment();\n    while (s.isValid()) {\n      total_distance += s.distance();\n      total_time += s.travelTime();\n      total_time_typical += get_time_typical(s);\n\n      s = s.nextRouteSegment();\n    }\n\n    emit ETAChanged(total_time, total_time_typical, total_distance);\n  }\n}\n\nvoid MapWindow::calculateRoute(QMapbox::Coordinate destination) {\n  qWarning() << \"Calculating route\" << *last_position << \"->\" << destination;\n\n  nav_destination = destination;\n  QGeoRouteRequest request(to_QGeoCoordinate(*last_position), to_QGeoCoordinate(destination));\n  request.setFeatureWeight(QGeoRouteRequest::TrafficFeature, QGeoRouteRequest::AvoidFeatureWeight);\n\n  if (last_bearing) {\n    QVariantMap params;\n    int bearing = ((int)(*last_bearing) + 360) % 360;\n    params[\"bearing\"] = bearing;\n    request.setWaypointsMetadata({params});\n  }\n\n  routing_manager->calculateRoute(request);\n}\n\nvoid MapWindow::routeCalculated(QGeoRouteReply *reply) {\n  bool got_route = false;\n  if (reply->error() == QGeoRouteReply::NoError) {\n    if (reply->routes().size() != 0) {\n      qWarning() << \"Got route response\";\n\n      route = reply->routes().at(0);\n      segment = route.firstRouteSegment();\n\n      auto route_points = coordinate_list_to_collection(route.path());\n      QMapbox::Feature feature(QMapbox::Feature::LineStringType, route_points, {}, {});\n      QVariantMap navSource;\n      navSource[\"type\"] = \"geojson\";\n      navSource[\"data\"] = QVariant::fromValue<QMapbox::Feature>(feature);\n      m_map->updateSource(\"navSource\", navSource);\n      m_map->setLayoutProperty(\"navLayer\", \"visibility\", \"visible\");\n      got_route = true;\n\n      updateETA();\n    } else {\n      qWarning() << \"Got empty route response\";\n    }\n  } else {\n    qWarning() << \"Got error in route reply\" << reply->errorString();\n  }\n\n  if (!got_route) {\n    map_instructions->showError(\"Failed to Route\");\n  }\n\n  reply->deleteLater();\n}\n\nvoid MapWindow::clearRoute() {\n  segment = QGeoRouteSegment();\n  nav_destination = QMapbox::Coordinate();\n\n  if (!m_map.isNull()) {\n    m_map->setLayoutProperty(\"navLayer\", \"visibility\", \"none\");\n    m_map->setPitch(MIN_PITCH);\n  }\n\n  map_instructions->hideIfNoError();\n  map_eta->setVisible(false);\n  allow_open = true;\n}\n\n\nbool MapWindow::shouldRecompute() {\n  if (!segment.isValid()) {\n    return true;\n  }\n\n  // Compute closest distance to all line segments in the current path\n  float min_d = REROUTE_DISTANCE + 1;\n  auto path = segment.path();\n  auto cur = to_QGeoCoordinate(*last_position);\n  for (size_t i = 0; i < path.size() - 1; i++) {\n    auto a = path[i];\n    auto b = path[i+1];\n    if (a.distanceTo(b) < 1.0) {\n      continue;\n    }\n    min_d = std::min(min_d, minimum_distance(a, b, cur));\n  }\n  return min_d > REROUTE_DISTANCE;\n\n  // TODO: Check for going wrong way in segment\n}\n\nvoid MapWindow::mousePressEvent(QMouseEvent *ev) {\n  m_lastPos = ev->localPos();\n  ev->accept();\n}\n\nvoid MapWindow::mouseDoubleClickEvent(QMouseEvent *ev) {\n  if (last_position) m_map->setCoordinate(*last_position);\n  if (last_bearing) m_map->setBearing(*last_bearing);\n  m_map->setZoom(util::map_val<float>(velocity_filter.x(), 0, 30, MAX_ZOOM, MIN_ZOOM));\n\n  pan_counter = 0;\n  zoom_counter = 0;\n}\n\nvoid MapWindow::mouseMoveEvent(QMouseEvent *ev) {\n  QPointF delta = ev->localPos() - m_lastPos;\n\n  if (!delta.isNull()) {\n    pan_counter = PAN_TIMEOUT;\n    m_map->moveBy(delta / MAP_SCALE);\n  }\n\n  m_lastPos = ev->localPos();\n  ev->accept();\n}\n\nvoid MapWindow::wheelEvent(QWheelEvent *ev) {\n  if (ev->orientation() == Qt::Horizontal) {\n      return;\n  }\n\n  float factor = ev->delta() / 1200.;\n  if (ev->delta() < 0) {\n      factor = factor > -1 ? factor : 1 / factor;\n  }\n\n  m_map->scaleBy(1 + factor, ev->pos() / MAP_SCALE);\n  zoom_counter = PAN_TIMEOUT;\n  ev->accept();\n}\n\nbool MapWindow::event(QEvent *event) {\n  if (event->type() == QEvent::Gesture) {\n    return gestureEvent(static_cast<QGestureEvent*>(event));\n  }\n\n  return QWidget::event(event);\n}\n\nbool MapWindow::gestureEvent(QGestureEvent *event) {\n  if (QGesture *pinch = event->gesture(Qt::PinchGesture)) {\n    pinchTriggered(static_cast<QPinchGesture *>(pinch));\n  }\n  return true;\n}\n\nvoid MapWindow::pinchTriggered(QPinchGesture *gesture) {\n  QPinchGesture::ChangeFlags changeFlags = gesture->changeFlags();\n  if (changeFlags & QPinchGesture::ScaleFactorChanged) {\n    // TODO: figure out why gesture centerPoint doesn't work\n    m_map->scaleBy(gesture->scaleFactor(), {width() / 2.0 / MAP_SCALE, height() / 2.0 / MAP_SCALE});\n    zoom_counter = PAN_TIMEOUT;\n  }\n}\n\nvoid MapWindow::offroadTransition(bool offroad) {\n  if (!offroad) {\n    auto dest = coordinate_from_param(\"NavDestination\");\n    setVisible(dest.has_value());\n  }\n  last_bearing = {};\n}\n\nMapInstructions::MapInstructions(QWidget * parent) : QWidget(parent) {\n  QHBoxLayout *main_layout = new QHBoxLayout(this);\n  main_layout->setContentsMargins(11, 50, 11, 11);\n  {\n    QVBoxLayout *layout = new QVBoxLayout;\n    icon_01 = new QLabel;\n    layout->addWidget(icon_01);\n    layout->addStretch();\n    main_layout->addLayout(layout);\n  }\n\n  {\n    QWidget *w = new QWidget;\n    QVBoxLayout *layout = new QVBoxLayout(w);\n\n    distance = new QLabel;\n    distance->setStyleSheet(R\"(font-size: 90px;)\");\n    layout->addWidget(distance);\n\n    primary = new QLabel;\n    primary->setStyleSheet(R\"(font-size: 60px;)\");\n    primary->setWordWrap(true);\n    layout->addWidget(primary);\n\n    secondary = new QLabel;\n    secondary->setStyleSheet(R\"(font-size: 50px;)\");\n    secondary->setWordWrap(true);\n    layout->addWidget(secondary);\n\n    lane_layout = new QHBoxLayout;\n    layout->addLayout(lane_layout);\n\n    main_layout->addWidget(w);\n  }\n\n  setStyleSheet(R\"(\n    * {\n      color: white;\n      font-family: \"Inter\";\n    }\n  )\");\n\n  QPalette pal = palette();\n  pal.setColor(QPalette::Background, QColor(0, 0, 0, 150));\n  setAutoFillBackground(true);\n  setPalette(pal);\n}\n\nvoid MapInstructions::updateDistance(float d) {\n  QString distance_str;\n\n  if (QUIState::ui_state.scene.is_metric) {\n    if (d > 500) {\n      distance_str.setNum(d / 1000, 'f', 1);\n      distance_str += \" km\";\n    } else {\n      distance_str.setNum(50 * int(d / 50));\n      distance_str += \" m\";\n    }\n  } else {\n    float miles = d * METER_2_MILE;\n    float feet = d * METER_2_FOOT;\n\n    if (feet > 500) {\n      distance_str.setNum(miles, 'f', 1);\n      distance_str += \" mi\";\n    } else {\n      distance_str.setNum(50 * int(feet / 50));\n      distance_str += \" ft\";\n    }\n  }\n\n  distance->setAlignment(Qt::AlignLeft);\n  distance->setText(distance_str);\n}\n\nvoid MapInstructions::showError(QString error) {\n  primary->setText(\"\");\n  distance->setText(error);\n  distance->setAlignment(Qt::AlignCenter);\n\n  secondary->setVisible(false);\n  icon_01->setVisible(false);\n\n  last_banner = {};\n  error = true;\n\n  setVisible(true);\n  adjustSize();\n}\n\nvoid MapInstructions::updateInstructions(QMap<QString, QVariant> banner, bool full) {\n  // Need multiple calls to adjustSize for it to properly resize\n  // seems like it takes a little bit of time for the images to change and\n  // the size can only be changed afterwards\n  adjustSize();\n\n  // Word wrap widgets need fixed width\n  primary->setFixedWidth(width() - 250);\n  secondary->setFixedWidth(width() - 250);\n\n  if (banner == last_banner) return;\n  QString primary_str, secondary_str;\n\n  auto p = banner[\"primary\"].toMap();\n  primary_str += p[\"text\"].toString();\n\n  // Show arrow with direction\n  if (p.contains(\"type\")) {\n    QString fn = \"../assets/navigation/direction_\" + p[\"type\"].toString();\n    if (p.contains(\"modifier\")) {\n      fn += \"_\" + p[\"modifier\"].toString();\n    }\n    fn +=  + \".png\";\n    fn = fn.replace(' ', '_');\n\n    QPixmap pix(fn);\n    icon_01->setPixmap(pix.scaledToWidth(200, Qt::SmoothTransformation));\n    icon_01->setSizePolicy(QSizePolicy(QSizePolicy::Fixed, QSizePolicy::Fixed));\n    icon_01->setVisible(true);\n  }\n\n  // Parse components (e.g. lanes, exit number)\n  auto components = p[\"components\"].toList();\n  QString icon_fn;\n  for (auto &c : components) {\n    auto cc = c.toMap();\n    if (cc[\"type\"].toString() == \"icon\") {\n      icon_fn = cc[\"imageBaseURL\"].toString() + \"@3x.png\";\n    }\n  }\n\n  if (banner.contains(\"secondary\") && full) {\n    auto s = banner[\"secondary\"].toMap();\n    secondary_str += s[\"text\"].toString();\n  }\n\n  clearLayout(lane_layout);\n  bool has_lanes = false;\n\n  if (banner.contains(\"sub\") && full) {\n    auto s = banner[\"sub\"].toMap();\n    auto components = s[\"components\"].toList();\n    for (auto &c : components) {\n      auto cc = c.toMap();\n      if (cc[\"type\"].toString() == \"lane\") {\n        has_lanes = true;\n\n        bool left = false;\n        bool straight = false;\n        bool right = false;\n        bool active = cc[\"active\"].toBool();\n\n        for (auto &dir : cc[\"directions\"].toList()) {\n          auto d = dir.toString();\n          left |= d.contains(\"left\");\n          straight |= d.contains(\"straight\");\n          right |= d.contains(\"right\");\n        }\n\n        // TODO: Make more images based on active direction and combined directions\n        QString fn = \"../assets/navigation/direction_\";\n        if (left) {\n          fn += \"turn_left\";\n        } else if (right) {\n          fn += \"turn_right\";\n        } else if (straight) {\n          fn += \"turn_straight\";\n        }\n\n        QPixmap pix(fn + \".png\");\n        auto icon = new QLabel;\n        icon->setPixmap(pix.scaledToWidth(active ? 125 : 75, Qt::SmoothTransformation));\n        icon->setSizePolicy(QSizePolicy(QSizePolicy::Fixed, QSizePolicy::Fixed));\n        lane_layout->addWidget(icon);\n      }\n    }\n  }\n\n  primary->setText(primary_str);\n  secondary->setVisible(secondary_str.length() > 0);\n  secondary->setText(secondary_str);\n\n  last_banner = banner;\n  error = false;\n\n  show();\n  adjustSize();\n}\n\nvoid MapInstructions::hideIfNoError() {\n  if (!error) {\n    hide();\n  }\n}\n\nMapETA::MapETA(QWidget * parent) : QWidget(parent) {\n  QHBoxLayout *main_layout = new QHBoxLayout(this);\n  main_layout->setContentsMargins(40, 25, 40, 25);\n\n  {\n    QHBoxLayout *layout = new QHBoxLayout;\n    eta = new QLabel;\n    eta->setAlignment(Qt::AlignCenter);\n    eta->setStyleSheet(\"font-weight:600\");\n\n    eta_unit = new QLabel;\n    eta_unit->setAlignment(Qt::AlignCenter);\n\n    layout->addWidget(eta);\n    layout->addWidget(eta_unit);\n    main_layout->addLayout(layout);\n  }\n  main_layout->addSpacing(40);\n  {\n    QHBoxLayout *layout = new QHBoxLayout;\n    time = new QLabel;\n    time->setAlignment(Qt::AlignCenter);\n\n    time_unit = new QLabel;\n    time_unit->setAlignment(Qt::AlignCenter);\n\n    layout->addWidget(time);\n    layout->addWidget(time_unit);\n    main_layout->addLayout(layout);\n  }\n  main_layout->addSpacing(40);\n  {\n    QHBoxLayout *layout = new QHBoxLayout;\n    distance = new QLabel;\n    distance->setAlignment(Qt::AlignCenter);\n    distance->setStyleSheet(\"font-weight:600\");\n\n    distance_unit = new QLabel;\n    distance_unit->setAlignment(Qt::AlignCenter);\n\n    layout->addWidget(distance);\n    layout->addWidget(distance_unit);\n    main_layout->addLayout(layout);\n  }\n\n  setStyleSheet(R\"(\n    * {\n      color: white;\n      font-family: \"Inter\";\n      font-size: 70px;\n    }\n  )\");\n\n  QPalette pal = palette();\n  pal.setColor(QPalette::Background, QColor(0, 0, 0, 150));\n  setAutoFillBackground(true);\n  setPalette(pal);\n}\n\n\nvoid MapETA::updateETA(float s, float s_typical, float d) {\n  if (d < MANEUVER_TRANSITION_THRESHOLD) {\n    hide();\n    return;\n  }\n\n  // ETA\n  auto eta_time = QDateTime::currentDateTime().addSecs(s).time();\n  if (params.getBool(\"NavSettingTime24h\")) {\n    eta->setText(eta_time.toString(\"HH:mm\"));\n    eta_unit->setText(\"eta\");\n  } else {\n    auto t = eta_time.toString(\"h:mm a\").split(' ');\n    eta->setText(t[0]);\n    eta_unit->setText(t[1]);\n  }\n\n  // Remaining time\n  if (s < 3600) {\n    time->setText(QString::number(int(s / 60)));\n    time_unit->setText(\"min\");\n  } else {\n    int hours = int(s) / 3600;\n    time->setText(QString::number(hours) + \":\" + QString::number(int((s - hours * 3600) / 60)).rightJustified(2, '0'));\n    time_unit->setText(\"hr\");\n  }\n\n  QString color;\n  if (s / s_typical > 1.5) {\n    color = \"#DA3025\";\n  } else if (s / s_typical > 1.2) {\n    color = \"#DAA725\";\n  } else {\n    color = \"#25DA6E\";\n  }\n\n  time->setStyleSheet(QString(R\"(color: %1; font-weight:600;)\").arg(color));\n  time_unit->setStyleSheet(QString(R\"(color: %1;)\").arg(color));\n\n  // Distance\n  QString distance_str;\n  float num = 0;\n  if (QUIState::ui_state.scene.is_metric) {\n    num = d / 1000.0;\n    distance_unit->setText(\"km\");\n  } else {\n    num = d * METER_2_MILE;\n    distance_unit->setText(\"mi\");\n  }\n\n  distance_str.setNum(num, 'f', num < 100 ? 1 : 0);\n  distance->setText(distance_str);\n\n  show();\n  adjustSize();\n  repaint();\n  adjustSize();\n\n  // Rounded corners\n  const int radius = 25;\n  const auto r = rect();\n\n  // Top corners rounded\n  QPainterPath path;\n  path.setFillRule(Qt::WindingFill);\n  path.addRoundedRect(r, radius, radius);\n\n  // Bottom corners not rounded\n  path.addRect(r.marginsRemoved(QMargins(0, radius, 0, 0)));\n\n  // Set clipping mask\n  QRegion mask = QRegion(path.simplified().toFillPolygon().toPolygon());\n  setMask(mask);\n\n  // Center\n  move(static_cast<QWidget*>(parent())->width() / 2 - width() / 2, 1080 - height() - bdr_s*2);\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/maps/map.h",
    "content": "#pragma once\n\n#include <optional>\n\n#include <QGeoCoordinate>\n#include <QGeoManeuver>\n#include <QGeoRouteRequest>\n#include <QGeoRouteSegment>\n#include <QGeoRoutingManager>\n#include <QGeoServiceProvider>\n#include <QGestureEvent>\n#include <QHBoxLayout>\n#include <QVBoxLayout>\n#include <QLabel>\n#include <QMapboxGL>\n#include <QMouseEvent>\n#include <QOpenGLWidget>\n#include <QScopedPointer>\n#include <QString>\n#include <QtGlobal>\n#include <QTimer>\n#include <QWheelEvent>\n#include <QMap>\n#include <QPixmap>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/util.h\"\n#include \"cereal/messaging/messaging.h\"\n\nclass MapInstructions : public QWidget {\n  Q_OBJECT\n\nprivate:\n  QLabel *distance;\n  QLabel *primary;\n  QLabel *secondary;\n  QLabel *icon_01;\n  QHBoxLayout *lane_layout;\n  QMap<QString, QVariant> last_banner;\n  bool error = false;\n\npublic:\n  MapInstructions(QWidget * parent=nullptr);\n  void showError(QString error);\n  void hideIfNoError();\n\npublic slots:\n  void updateDistance(float d);\n  void updateInstructions(QMap<QString, QVariant> banner, bool full);\n};\n\nclass MapETA : public QWidget {\n  Q_OBJECT\n\nprivate:\n  QLabel *eta;\n  QLabel *eta_unit;\n  QLabel *time;\n  QLabel *time_unit;\n  QLabel *distance;\n  QLabel *distance_unit;\n  Params params;\n\npublic:\n  MapETA(QWidget * parent=nullptr);\n\npublic slots:\n  void updateETA(float seconds, float seconds_typical, float distance);\n};\n\nclass MapWindow : public QOpenGLWidget {\n  Q_OBJECT\n\npublic:\n  MapWindow(const QMapboxGLSettings &);\n  ~MapWindow();\n\nprivate:\n  void initializeGL() final;\n  void paintGL() final;\n  void resizeGL(int w, int h) override;\n\n  QMapboxGLSettings m_settings;\n  QScopedPointer<QMapboxGL> m_map;\n\n  void initLayers();\n\n  void mousePressEvent(QMouseEvent *ev) final;\n  void mouseDoubleClickEvent(QMouseEvent *ev) final;\n  void mouseMoveEvent(QMouseEvent *ev) final;\n  void wheelEvent(QWheelEvent *ev) final;\n  bool event(QEvent *event) final;\n  bool gestureEvent(QGestureEvent *event);\n  void pinchTriggered(QPinchGesture *gesture);\n\n  bool m_sourceAdded = false;\n  SubMaster *sm;\n  QTimer* timer;\n\n  bool loaded_once = false;\n\n  // Panning\n  QPointF m_lastPos;\n  int pan_counter = 0;\n  int zoom_counter = 0;\n\n  // Position\n  std::optional<QMapbox::Coordinate> last_position;\n  std::optional<float> last_bearing;\n  FirstOrderFilter velocity_filter;\n  bool localizer_valid = false;\n\n  // Route\n  bool allow_open = true;\n  bool gps_ok = false;\n  QGeoServiceProvider *geoservice_provider;\n  QGeoRoutingManager *routing_manager;\n  QGeoRoute route;\n  QGeoRouteSegment segment;\n\n  MapInstructions* map_instructions;\n  MapETA* map_eta;\n\n  QMapbox::Coordinate nav_destination;\n\n  // Route recompute\n  QTimer* recompute_timer;\n  int recompute_backoff = 0;\n  int recompute_countdown = 0;\n  void calculateRoute(QMapbox::Coordinate destination);\n  void clearRoute();\n  bool shouldRecompute();\n  void updateETA();\n\nprivate slots:\n  void timerUpdate();\n  void routeCalculated(QGeoRouteReply *reply);\n  void recomputeRoute();\n\npublic slots:\n  void offroadTransition(bool offroad);\n\nsignals:\n  void distanceChanged(float distance);\n  void instructionsChanged(QMap<QString, QVariant> banner, bool full);\n  void ETAChanged(float seconds, float seconds_typical, float distance);\n};\n\n"
  },
  {
    "path": "selfdrive/ui/qt/maps/map_helpers.cc",
    "content": "#include \"selfdrive/ui/qt/maps/map_helpers.h\"\n\n#include <QJsonDocument>\n#include <QJsonObject>\n\n#include \"selfdrive/common/params.h\"\n\n\nQGeoCoordinate to_QGeoCoordinate(const QMapbox::Coordinate &in) {\n  return QGeoCoordinate(in.first, in.second);\n}\n\nQMapbox::CoordinatesCollections model_to_collection(\n  const cereal::LiveLocationKalman::Measurement::Reader &calibratedOrientationECEF,\n  const cereal::LiveLocationKalman::Measurement::Reader &positionECEF,\n  const cereal::ModelDataV2::XYZTData::Reader &line){\n\n  Eigen::Vector3d ecef(positionECEF.getValue()[0], positionECEF.getValue()[1], positionECEF.getValue()[2]);\n  Eigen::Vector3d orient(calibratedOrientationECEF.getValue()[0], calibratedOrientationECEF.getValue()[1], calibratedOrientationECEF.getValue()[2]);\n  Eigen::Matrix3d ecef_from_local = euler2rot(orient);\n\n  QMapbox::Coordinates coordinates;\n  auto x = line.getX();\n  auto y = line.getY();\n  auto z = line.getZ();\n  for (int i = 0; i < x.size(); i++) {\n    Eigen::Vector3d point_ecef = ecef_from_local * Eigen::Vector3d(x[i], y[i], z[i]) + ecef;\n    Geodetic point_geodetic = ecef2geodetic((ECEF){.x = point_ecef[0], .y = point_ecef[1], .z = point_ecef[2]});\n    QMapbox::Coordinate coordinate(point_geodetic.lat, point_geodetic.lon);\n    coordinates.push_back(coordinate);\n  }\n\n  QMapbox::CoordinatesCollection collection;\n  collection.push_back(coordinates);\n\n  QMapbox::CoordinatesCollections collections;\n  collections.push_back(collection);\n  return collections;\n}\n\nQMapbox::CoordinatesCollections coordinate_to_collection(QMapbox::Coordinate c) {\n  QMapbox::Coordinates coordinates;\n  coordinates.push_back(c);\n\n  QMapbox::CoordinatesCollection collection;\n  collection.push_back(coordinates);\n\n  QMapbox::CoordinatesCollections collections;\n  collections.push_back(collection);\n  return collections;\n}\n\nQMapbox::CoordinatesCollections coordinate_list_to_collection(QList<QGeoCoordinate> coordinate_list) {\n  QMapbox::Coordinates coordinates;\n\n  for (auto &c : coordinate_list) {\n    QMapbox::Coordinate coordinate(c.latitude(), c.longitude());\n    coordinates.push_back(coordinate);\n  }\n\n  QMapbox::CoordinatesCollection collection;\n  collection.push_back(coordinates);\n\n  QMapbox::CoordinatesCollections collections;\n  collections.push_back(collection);\n  return collections;\n}\n\nstatic QGeoCoordinate sub(QGeoCoordinate v, QGeoCoordinate w) {\n  return QGeoCoordinate(v.latitude() - w.latitude(), v.longitude() - w.longitude());\n}\n\nstatic QGeoCoordinate add(QGeoCoordinate v, QGeoCoordinate w) {\n  return QGeoCoordinate(v.latitude() + w.latitude(), v.longitude() + w.longitude());\n}\n\nstatic QGeoCoordinate mul(QGeoCoordinate v, float c) {\n  return QGeoCoordinate(c * v.latitude(), c * v.longitude());\n}\n\nstatic float dot(QGeoCoordinate v, QGeoCoordinate w) {\n  return v.latitude() * w.latitude() + v.longitude() * w.longitude();\n}\n\nfloat minimum_distance(QGeoCoordinate a, QGeoCoordinate b, QGeoCoordinate p) {\n  const QGeoCoordinate ap = sub(p, a);\n  const QGeoCoordinate ab = sub(b, a);\n  const float t = std::clamp(dot(ap, ab) / dot(ab, ab), 0.0f, 1.0f);\n  const QGeoCoordinate projection = add(a, mul(ab, t));\n  return projection.distanceTo(p);\n}\n\nfloat distance_along_geometry(QList<QGeoCoordinate> geometry, QGeoCoordinate pos) {\n  if (geometry.size() <= 2) {\n    return geometry[0].distanceTo(pos);\n  }\n\n  // 1. Find segment that is closest to current position\n  // 2. Total distance is sum of distance to start of closest segment\n  //    + all previous segments\n  double total_distance = 0;\n  double total_distance_closest = 0;\n  double closest_distance = std::numeric_limits<double>::max();\n\n  for (int i = 0; i < geometry.size() - 1; i++) {\n    double d = minimum_distance(geometry[i], geometry[i+1], pos);\n    if (d < closest_distance) {\n      closest_distance = d;\n      total_distance_closest = total_distance + geometry[i].distanceTo(pos);\n    }\n    total_distance += geometry[i].distanceTo(geometry[i+1]);\n  }\n\n  return total_distance_closest;\n}\n\nstd::optional<QMapbox::Coordinate> coordinate_from_param(std::string param) {\n  QString json_str = QString::fromStdString(Params().get(param));\n  if (json_str.isEmpty()) return {};\n\n  QJsonDocument doc = QJsonDocument::fromJson(json_str.toUtf8());\n  if (doc.isNull()) return {};\n\n  QJsonObject json = doc.object();\n  if (json[\"latitude\"].isDouble() && json[\"longitude\"].isDouble()) {\n    QMapbox::Coordinate coord(json[\"latitude\"].toDouble(), json[\"longitude\"].toDouble());\n    return coord;\n  } else {\n    return {};\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/maps/map_helpers.h",
    "content": "#pragma once\n\n#include <optional>\n#include <eigen3/Eigen/Dense>\n#include <QMapboxGL>\n#include <QGeoCoordinate>\n\n#include \"common/transformations/coordinates.hpp\"\n#include \"common/transformations/orientation.hpp\"\n#include \"cereal/messaging/messaging.h\"\n\nconst float METER_2_MILE = 0.000621371;\nconst float METER_2_FOOT = 3.28084;\n#define RAD2DEG(x) ((x) * 180.0 / M_PI)\n\nQGeoCoordinate to_QGeoCoordinate(const QMapbox::Coordinate &in);\nQMapbox::CoordinatesCollections model_to_collection(\n  const cereal::LiveLocationKalman::Measurement::Reader &calibratedOrientationECEF,\n  const cereal::LiveLocationKalman::Measurement::Reader &positionECEF,\n  const cereal::ModelDataV2::XYZTData::Reader &line);\nQMapbox::CoordinatesCollections coordinate_to_collection(QMapbox::Coordinate c);\nQMapbox::CoordinatesCollections coordinate_list_to_collection(QList<QGeoCoordinate> coordinate_list);\n\nfloat minimum_distance(QGeoCoordinate a, QGeoCoordinate b, QGeoCoordinate p);\nstd::optional<QMapbox::Coordinate> coordinate_from_param(std::string param);\nfloat distance_along_geometry(QList<QGeoCoordinate> geometry, QGeoCoordinate pos);\n"
  },
  {
    "path": "selfdrive/ui/qt/maps/map_settings.cc",
    "content": "#include \"map_settings.h\"\n\n#include <QDebug>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/request_repeater.h\"\n#include \"selfdrive/ui/qt/widgets/controls.h\"\n#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n\nstatic QString shorten(const QString &str, int max_len) {\n  return str.size() > max_len ? str.left(max_len).trimmed() + \"…\" : str;\n}\n\nMapPanel::MapPanel(QWidget* parent) : QWidget(parent) {\n  stack = new QStackedWidget;\n\n  QWidget * main_widget = new QWidget;\n  QVBoxLayout *main_layout = new QVBoxLayout(main_widget);\n  const int icon_size = 200;\n\n  // Home\n  QHBoxLayout *home_layout = new QHBoxLayout;\n  home_button = new QPushButton;\n  home_button->setIconSize(QSize(icon_size, icon_size));\n  home_layout->addWidget(home_button);\n\n  home_address = new QLabel;\n  home_address->setWordWrap(true);\n  home_layout->addSpacing(30);\n  home_layout->addWidget(home_address);\n  home_layout->addStretch();\n\n  // Work\n  QHBoxLayout *work_layout = new QHBoxLayout;\n  work_button = new QPushButton;\n  work_button->setIconSize(QSize(icon_size, icon_size));\n  work_layout->addWidget(work_button);\n\n  work_address = new QLabel;\n  work_address->setWordWrap(true);\n  work_layout->addSpacing(30);\n  work_layout->addWidget(work_address);\n  work_layout->addStretch();\n\n  // Home & Work layout\n  QHBoxLayout *home_work_layout = new QHBoxLayout;\n  home_work_layout->addLayout(home_layout, 1);\n  home_work_layout->addSpacing(50);\n  home_work_layout->addLayout(work_layout, 1);\n\n  main_layout->addLayout(home_work_layout);\n  main_layout->addSpacing(20);\n  main_layout->addWidget(horizontal_line());\n  main_layout->addSpacing(20);\n\n  // Current route\n  {\n    current_widget = new QWidget(this);\n    QVBoxLayout *current_layout = new QVBoxLayout(current_widget);\n\n    QLabel *title = new QLabel(\"Current Destination\");\n    title->setStyleSheet(\"font-size: 55px\");\n    current_layout->addWidget(title);\n\n    current_route = new ButtonControl(\"\", \"CLEAR\");\n    current_route->setStyleSheet(\"padding-left: 40px;\");\n    current_layout->addWidget(current_route);\n    QObject::connect(current_route, &ButtonControl::clicked, [=]() {\n      params.remove(\"NavDestination\");\n      updateCurrentRoute();\n    });\n\n    current_layout->addSpacing(10);\n    current_layout->addWidget(horizontal_line());\n    current_layout->addSpacing(20);\n  }\n  main_layout->addWidget(current_widget);\n\n  // Recents\n  QLabel *recents_title = new QLabel(\"Recent Destinations\");\n  recents_title->setStyleSheet(\"font-size: 55px\");\n  main_layout->addWidget(recents_title);\n  main_layout->addSpacing(20);\n\n  recent_layout = new QVBoxLayout;\n  QWidget *recent_widget = new LayoutWidget(recent_layout, this);\n  ScrollView *recent_scroller = new ScrollView(recent_widget, this);\n  main_layout->addWidget(recent_scroller);\n\n  // No prime upsell\n  QWidget * no_prime_widget = new QWidget;\n  {\n    QVBoxLayout *no_prime_layout = new QVBoxLayout(no_prime_widget);\n    QLabel *signup_header = new QLabel(\"Try the Navigation Beta\");\n    signup_header->setStyleSheet(R\"(font-size: 75px; color: white; font-weight:600;)\");\n    signup_header->setAlignment(Qt::AlignCenter);\n\n    no_prime_layout->addWidget(signup_header);\n    no_prime_layout->addSpacing(50);\n\n    QLabel *screenshot = new QLabel;\n    QPixmap pm = QPixmap(\"../assets/navigation/screenshot.png\");\n    screenshot->setPixmap(pm.scaledToWidth(vwp_w * 0.5, Qt::SmoothTransformation));\n    no_prime_layout->addWidget(screenshot, 0, Qt::AlignHCenter);\n\n    QLabel *signup = new QLabel(\"Get turn-by-turn directions displayed and more with a comma \\nprime subscription. Sign up now: https://connect.comma.ai\");\n    signup->setStyleSheet(R\"(font-size: 45px; color: white; font-weight:300;)\");\n    signup->setAlignment(Qt::AlignCenter);\n\n    no_prime_layout->addSpacing(20);\n    no_prime_layout->addWidget(signup);\n    no_prime_layout->addStretch();\n  }\n\n  stack->addWidget(main_widget);\n  stack->addWidget(no_prime_widget);\n  stack->setCurrentIndex(1);\n  QVBoxLayout *wrapper = new QVBoxLayout(this);\n  wrapper->addWidget(stack);\n\n  clear();\n\n  if (auto dongle_id = getDongleId()) {\n    // Fetch favorite and recent locations\n    {\n      QString url = CommaApi::BASE_URL + \"/v1/navigation/\" + *dongle_id + \"/locations\";\n      RequestRepeater* repeater = new RequestRepeater(this, url, \"ApiCache_NavDestinations\", 30, true);\n      QObject::connect(repeater, &RequestRepeater::receivedResponse, this, &MapPanel::parseResponse);\n      QObject::connect(repeater, &RequestRepeater::failedResponse, this, &MapPanel::failedResponse);\n    }\n\n    // Destination set while offline\n    {\n      QString url = CommaApi::BASE_URL + \"/v1/navigation/\" + *dongle_id + \"/next\";\n      RequestRepeater* repeater = new RequestRepeater(this, url, \"\", 10, true);\n      HttpRequest* deleter = new HttpRequest(this);\n\n      QObject::connect(repeater, &RequestRepeater::receivedResponse, [=](QString resp) {\n        auto params = Params();\n        if (resp != \"null\") {\n          if (params.get(\"NavDestination\").empty()) {\n            qWarning() << \"Setting NavDestination from /next\" << resp;\n            params.put(\"NavDestination\", resp.toStdString());\n          } else {\n            qWarning() << \"Got location from /next, but NavDestination already set\";\n          }\n\n          // Send DELETE to clear destination server side\n          deleter->sendRequest(url, HttpRequest::Method::DELETE);\n        }\n      });\n    }\n  }\n}\n\nvoid MapPanel::showEvent(QShowEvent *event) {\n  updateCurrentRoute();\n}\n\nvoid MapPanel::clear() {\n  home_button->setIcon(QPixmap(\"../assets/navigation/home_inactive.png\"));\n  home_address->setStyleSheet(R\"(font-size: 50px; color: grey;)\");\n  home_address->setText(\"No home\\nlocation set\");\n  home_button->disconnect();\n\n  work_button->setIcon(QPixmap(\"../assets/navigation/work_inactive.png\"));\n  work_address->setStyleSheet(R\"(font-size: 50px; color: grey;)\");\n  work_address->setText(\"No work\\nlocation set\");\n  work_button->disconnect();\n\n  clearLayout(recent_layout);\n}\n\nvoid MapPanel::updateCurrentRoute() {\n  auto dest = QString::fromStdString(params.get(\"NavDestination\"));\n  QJsonDocument doc = QJsonDocument::fromJson(dest.trimmed().toUtf8());\n  if (dest.size() && !doc.isNull()) {\n    auto name = doc[\"place_name\"].toString();\n    auto details = doc[\"place_details\"].toString();\n    current_route->setTitle(shorten(name + \" \" + details, 42));\n  }\n  current_widget->setVisible(dest.size() && !doc.isNull());\n}\n\nvoid MapPanel::parseResponse(const QString &response) {\n  QJsonDocument doc = QJsonDocument::fromJson(response.trimmed().toUtf8());\n  if (doc.isNull()) {\n    qDebug() << \"JSON Parse failed on navigation locations\";\n    return;\n  }\n\n  clear();\n\n  bool has_recents = false;\n  for (auto &save_type: {\"favorite\", \"recent\"}) {\n    for (auto location : doc.array()) {\n      auto obj = location.toObject();\n\n      auto type = obj[\"save_type\"].toString();\n      auto label = obj[\"label\"].toString();\n      auto name = obj[\"place_name\"].toString();\n      auto details = obj[\"place_details\"].toString();\n\n      if (type != save_type) continue;\n\n      if (type == \"favorite\" && label == \"home\") {\n        home_address->setText(name);\n        home_address->setStyleSheet(R\"(font-size: 50px; color: white;)\");\n        home_button->setIcon(QPixmap(\"../assets/navigation/home.png\"));\n        QObject::connect(home_button, &QPushButton::clicked, [=]() {\n          navigateTo(obj);\n          emit closeSettings();\n        });\n      } else if (type == \"favorite\" && label == \"work\") {\n        work_address->setText(name);\n        work_address->setStyleSheet(R\"(font-size: 50px; color: white;)\");\n        work_button->setIcon(QPixmap(\"../assets/navigation/work.png\"));\n        QObject::connect(work_button, &QPushButton::clicked, [=]() {\n          navigateTo(obj);\n          emit closeSettings();\n        });\n      } else {\n        ClickableWidget *widget = new ClickableWidget;\n        QHBoxLayout *layout = new QHBoxLayout(widget);\n        layout->setContentsMargins(15, 14, 40, 14);\n\n        QLabel *star = new QLabel(\"★\");\n        auto sp = star->sizePolicy();\n        sp.setRetainSizeWhenHidden(true);\n        star->setSizePolicy(sp);\n\n        star->setVisible(type == \"favorite\");\n        star->setStyleSheet(R\"(font-size: 60px;)\");\n        layout->addWidget(star);\n        layout->addSpacing(10);\n\n\n        QLabel *recent_label = new QLabel(shorten(name + \" \" + details, 45));\n        recent_label->setStyleSheet(R\"(font-size: 50px;)\");\n\n        layout->addWidget(recent_label);\n        layout->addStretch();\n\n        QLabel *arrow = new QLabel(\"→\");\n        arrow->setStyleSheet(R\"(font-size: 60px;)\");\n        layout->addWidget(arrow);\n\n        widget->setStyleSheet(R\"(\n          .ClickableWidget {\n            border-radius: 10px;\n            border-width: 1px;\n            border-style: solid;\n            border-color: gray;\n          }\n          QWidget {\n            background-color: #393939;\n            color: #9c9c9c;\n          }\n        )\");\n\n        QObject::connect(widget, &ClickableWidget::clicked, [=]() {\n          navigateTo(obj);\n          emit closeSettings();\n        });\n\n        recent_layout->addWidget(widget);\n        recent_layout->addSpacing(10);\n        has_recents = true;\n      }\n    }\n\n  }\n\n  if (!has_recents) {\n    QLabel *no_recents = new QLabel(\"no recent destinations\");\n    no_recents->setStyleSheet(R\"(font-size: 50px; color: #9c9c9c)\");\n    recent_layout->addWidget(no_recents);\n  }\n\n  recent_layout->addStretch();\n  stack->setCurrentIndex(0);\n  repaint();\n}\n\nvoid MapPanel::failedResponse(const QString &response) {\n  stack->setCurrentIndex(1);\n}\n\nvoid MapPanel::navigateTo(const QJsonObject &place) {\n  QJsonDocument doc(place);\n  params.put(\"NavDestination\", doc.toJson().toStdString());\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/maps/map_settings.h",
    "content": "#pragma once\n#include <QJsonArray>\n#include <QJsonDocument>\n#include <QJsonObject>\n#include <QLabel>\n#include <QPushButton>\n#include <QVBoxLayout>\n#include <QWidget>\n#include <QStackedWidget>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/widgets/controls.h\"\n\nclass MapPanel : public QWidget {\n  Q_OBJECT\npublic:\n  explicit MapPanel(QWidget* parent = nullptr);\n\n  void navigateTo(const QJsonObject &place);\n  void parseResponse(const QString &response);\n  void failedResponse(const QString &response);\n  void updateCurrentRoute();\n  void clear();\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n\n  Params params;\n  QStackedWidget *stack;\n  QPushButton *home_button, *work_button;\n  QLabel *home_address, *work_address;\n  QVBoxLayout *recent_layout;\n  QWidget *current_widget;\n  ButtonControl *current_route;\n\nsignals:\n  void closeSettings();\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/driverview.cc",
    "content": "#include \"selfdrive/ui/qt/offroad/driverview.h\"\n\n#include <QPainter>\n\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/util.h\"\n\nconst int FACE_IMG_SIZE = 130;\n\nDriverViewWindow::DriverViewWindow(QWidget* parent) : QWidget(parent) {\n  setAttribute(Qt::WA_OpaquePaintEvent);\n  layout = new QStackedLayout(this);\n  layout->setStackingMode(QStackedLayout::StackAll);\n\n  cameraView = new CameraViewWidget(VISION_STREAM_RGB_FRONT, true, this);\n  layout->addWidget(cameraView);\n\n  scene = new DriverViewScene(this);\n  connect(cameraView, &CameraViewWidget::frameUpdated, scene, &DriverViewScene::frameUpdated);\n  layout->addWidget(scene);\n  layout->setCurrentWidget(scene);\n}\n\nvoid DriverViewWindow::mouseReleaseEvent(QMouseEvent* e) {\n  emit done();\n}\n\nDriverViewScene::DriverViewScene(QWidget* parent) : sm({\"driverState\"}), QWidget(parent) {\n  face_img = QImage(\"../assets/img_driver_face.png\").scaled(FACE_IMG_SIZE, FACE_IMG_SIZE, Qt::KeepAspectRatio, Qt::SmoothTransformation);\n}\n\nvoid DriverViewScene::showEvent(QShowEvent* event) {\n  frame_updated = false;\n  is_rhd = params.getBool(\"IsRHD\");\n  params.putBool(\"IsDriverViewEnabled\", true);\n}\n\nvoid DriverViewScene::hideEvent(QHideEvent* event) {\n  params.putBool(\"IsDriverViewEnabled\", false);\n}\n\nvoid DriverViewScene::frameUpdated() {\n  frame_updated = true;\n  sm.update(0);\n  update();\n}\n\nvoid DriverViewScene::paintEvent(QPaintEvent* event) {\n  QPainter p(this);\n\n  // startup msg\n  if (!frame_updated) {\n    p.setPen(Qt::white);\n    p.setRenderHint(QPainter::TextAntialiasing);\n    configFont(p, \"Inter\", 100, \"Bold\");\n    p.drawText(geometry(), Qt::AlignCenter, \"camera starting\");\n    return;\n  }\n\n  const int width = 4 * height() / 3;\n  const QRect rect2 = {rect().center().x() - width / 2, rect().top(), width, rect().height()};\n  const QRect valid_rect = {is_rhd ? rect2.right() - rect2.height() / 2 : rect2.left(), rect2.top(), rect2.height() / 2, rect2.height()};\n\n  // blackout\n  const QColor bg(0, 0, 0, 140);\n  const QRect& blackout_rect = Hardware::TICI() ? rect() : rect2;\n  p.fillRect(blackout_rect.adjusted(0, 0, valid_rect.left() - blackout_rect.right(), 0), bg);\n  p.fillRect(blackout_rect.adjusted(valid_rect.right() - blackout_rect.left(), 0, 0, 0), bg);\n\n  // face bounding box\n  cereal::DriverState::Reader driver_state = sm[\"driverState\"].getDriverState();\n  bool face_detected = driver_state.getFaceProb() > 0.4;\n  if (face_detected) {\n    auto fxy_list = driver_state.getFacePosition();\n    float face_x = fxy_list[0];\n    float face_y = fxy_list[1];\n\n    float alpha = 0.2;\n    float x = std::abs(face_x), y = std::abs(face_y);\n    if (x <= 0.35 && y <= 0.4) {\n      alpha = 0.8 - std::max(x, y) * 0.6 / 0.375;\n    }\n    const int box_size = 0.6 * rect2.height() / 2;\n    int fbox_x = valid_rect.center().x() + (is_rhd ? face_x : -face_x) * valid_rect.width();\n    int fbox_y = valid_rect.center().y() + face_y * valid_rect.height();\n    p.setPen(QPen(QColor(255, 255, 255, alpha * 255), 10));\n    p.drawRoundedRect(fbox_x - box_size / 2, fbox_y - box_size / 2, box_size, box_size, 35.0, 35.0);\n  }\n\n  // icon\n  const int img_offset = 30;\n  const int img_x = is_rhd ? rect2.right() - FACE_IMG_SIZE - img_offset : rect2.left() + img_offset;\n  const int img_y = rect2.bottom() - FACE_IMG_SIZE - img_offset;\n  p.setOpacity(face_detected ? 1.0 : 0.3);\n  p.drawImage(img_x, img_y, face_img);\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/driverview.h",
    "content": "#pragma once\n\n#include <memory>\n\n#include <QStackedLayout>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/ui/qt/widgets/cameraview.h\"\n\nclass DriverViewScene : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit DriverViewScene(QWidget *parent);\n\npublic slots:\n  void frameUpdated();\n\nprotected:\n  void showEvent(QShowEvent *event) override;\n  void hideEvent(QHideEvent *event) override;\n  void paintEvent(QPaintEvent *event) override;\n\nprivate:\n  Params params;\n  SubMaster sm;\n  QImage face_img;\n  bool is_rhd = false;\n  bool frame_updated = false;\n};\n\nclass DriverViewWindow : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit DriverViewWindow(QWidget *parent);\n\nsignals:\n  void done();\n\nprotected:\n  void mouseReleaseEvent(QMouseEvent* e) override;\n\nprivate:\n  CameraViewWidget *cameraView;\n  DriverViewScene *scene;\n  QStackedLayout *layout;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/networking.cc",
    "content": "#include \"selfdrive/ui/qt/offroad/networking.h\"\n\n#include <algorithm>\n\n#include <QDebug>\n#include <QHBoxLayout>\n#include <QLabel>\n#include <QPainter>\n#include <QScrollBar>\n\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n\n\n// Networking functions\n\nNetworking::Networking(QWidget* parent, bool show_advanced) : QFrame(parent) {\n  main_layout = new QStackedLayout(this);\n\n  wifi = new WifiManager(this);\n  connect(wifi, &WifiManager::refreshSignal, this, &Networking::refresh);\n  connect(wifi, &WifiManager::wrongPassword, this, &Networking::wrongPassword);\n\n  QWidget* wifiScreen = new QWidget(this);\n  QVBoxLayout* vlayout = new QVBoxLayout(wifiScreen);\n  vlayout->setContentsMargins(20, 20, 20, 20);\n  if (show_advanced) {\n    QPushButton* advancedSettings = new QPushButton(\"Advanced\");\n    advancedSettings->setObjectName(\"advancedBtn\");\n    advancedSettings->setStyleSheet(\"margin-right: 30px;\");\n    advancedSettings->setFixedSize(350, 100);\n    connect(advancedSettings, &QPushButton::clicked, [=]() { main_layout->setCurrentWidget(an); });\n    vlayout->addSpacing(10);\n    vlayout->addWidget(advancedSettings, 0, Qt::AlignRight);\n    vlayout->addSpacing(10);\n  }\n\n  wifiWidget = new WifiUI(this, wifi);\n  wifiWidget->setObjectName(\"wifiWidget\");\n  connect(wifiWidget, &WifiUI::connectToNetwork, this, &Networking::connectToNetwork);\n\n  ScrollView *wifiScroller = new ScrollView(wifiWidget, this);\n  wifiScroller->setVerticalScrollBarPolicy(Qt::ScrollBarAsNeeded);\n  vlayout->addWidget(wifiScroller, 1);\n  main_layout->addWidget(wifiScreen);\n\n  an = new AdvancedNetworking(this, wifi);\n  connect(an, &AdvancedNetworking::backPress, [=]() { main_layout->setCurrentWidget(wifiScreen); });\n  main_layout->addWidget(an);\n\n  QPalette pal = palette();\n  pal.setColor(QPalette::Window, QColor(0x29, 0x29, 0x29));\n  setAutoFillBackground(true);\n  setPalette(pal);\n\n  // TODO: revisit pressed colors\n  setStyleSheet(R\"(\n    #wifiWidget > QPushButton, #back_btn, #advancedBtn {\n      font-size: 50px;\n      margin: 0px;\n      padding: 15px;\n      border-width: 0;\n      border-radius: 30px;\n      color: #dddddd;\n      background-color: #444444;\n    }\n  )\");\n  main_layout->setCurrentWidget(wifiScreen);\n}\n\nvoid Networking::refresh() {\n  wifiWidget->refresh();\n  an->refresh();\n}\n\nvoid Networking::connectToNetwork(const Network &n) {\n  if (wifi->isKnownConnection(n.ssid)) {\n    wifi->activateWifiConnection(n.ssid);\n    wifiWidget->refresh();\n  } else if (n.security_type == SecurityType::OPEN) {\n    wifi->connect(n);\n  } else if (n.security_type == SecurityType::WPA) {\n    QString pass = InputDialog::getText(\"Enter password\", this, \"for \\\"\" + n.ssid + \"\\\"\", true, 8);\n    if (!pass.isEmpty()) {\n      wifi->connect(n, pass);\n    }\n  }\n}\n\nvoid Networking::wrongPassword(const QString &ssid) {\n  if (wifi->seenNetworks.contains(ssid)) {\n    const Network &n = wifi->seenNetworks.value(ssid);\n    QString pass = InputDialog::getText(\"Wrong password\", this, \"for \\\"\" + n.ssid +\"\\\"\", true, 8);\n    if (!pass.isEmpty()) {\n      wifi->connect(n, pass);\n    }\n  }\n}\n\nvoid Networking::showEvent(QShowEvent* event) {\n  // Wait to refresh to avoid delay when showing Networking widget\n  QTimer::singleShot(300, this, [=]() {\n    if (this->isVisible()) {\n      wifi->refreshNetworks();\n      refresh();\n    }\n  });\n}\n\n// AdvancedNetworking functions\n\nAdvancedNetworking::AdvancedNetworking(QWidget* parent, WifiManager* wifi): QWidget(parent), wifi(wifi) {\n\n  QVBoxLayout* main_layout = new QVBoxLayout(this);\n  main_layout->setMargin(40);\n  main_layout->setSpacing(20);\n\n  // Back button\n  QPushButton* back = new QPushButton(\"Back\");\n  back->setObjectName(\"back_btn\");\n  back->setFixedSize(500, 100);\n  connect(back, &QPushButton::clicked, [=]() { emit backPress(); });\n  main_layout->addWidget(back, 0, Qt::AlignLeft);\n\n  // Enable tethering layout\n  tetheringToggle = new ToggleControl(\"Enable Tethering\", \"\", \"\", wifi->isTetheringEnabled());\n  main_layout->addWidget(tetheringToggle);\n  QObject::connect(tetheringToggle, &ToggleControl::toggleFlipped, this, &AdvancedNetworking::toggleTethering);\n  main_layout->addWidget(horizontal_line(), 0);\n\n  // Change tethering password\n  ButtonControl *editPasswordButton = new ButtonControl(\"Tethering Password\", \"EDIT\");\n  connect(editPasswordButton, &ButtonControl::clicked, [=]() {\n    QString pass = InputDialog::getText(\"Enter new tethering password\", this, \"\", true, 8, wifi->getTetheringPassword());\n    if (!pass.isEmpty()) {\n      wifi->changeTetheringPassword(pass);\n    }\n  });\n  main_layout->addWidget(editPasswordButton, 0);\n  main_layout->addWidget(horizontal_line(), 0);\n\n  // IP address\n  ipLabel = new LabelControl(\"IP Address\", wifi->ipv4_address);\n  main_layout->addWidget(ipLabel, 0);\n  main_layout->addWidget(horizontal_line(), 0);\n\n  // SSH keys\n  main_layout->addWidget(new SshToggle());\n  main_layout->addWidget(horizontal_line(), 0);\n  main_layout->addWidget(new SshControl());\n  main_layout->addWidget(horizontal_line(), 0);\n\n  // Roaming toggle\n  const bool roamingEnabled = params.getBool(\"GsmRoaming\");\n  wifi->setRoamingEnabled(roamingEnabled);\n  ToggleControl *roamingToggle = new ToggleControl(\"Enable Roaming\", \"\", \"\", roamingEnabled);\n  QObject::connect(roamingToggle, &SshToggle::toggleFlipped, [=](bool state) {\n    params.putBool(\"GsmRoaming\", state);\n    wifi->setRoamingEnabled(state);\n  });\n  main_layout->addWidget(roamingToggle);\n\n  main_layout->addStretch(1);\n}\n\nvoid AdvancedNetworking::refresh() {\n  ipLabel->setText(wifi->ipv4_address);\n  tetheringToggle->setEnabled(true);\n  update();\n}\n\nvoid AdvancedNetworking::toggleTethering(bool enabled) {\n  wifi->setTetheringEnabled(enabled);\n  tetheringToggle->setEnabled(false);\n}\n\n// WifiUI functions\n\nWifiUI::WifiUI(QWidget *parent, WifiManager* wifi) : QWidget(parent), wifi(wifi) {\n  main_layout = new QVBoxLayout(this);\n  main_layout->setContentsMargins(0, 0, 0, 0);\n  main_layout->setSpacing(0);\n\n  // load imgs\n  for (const auto &s : {\"low\", \"medium\", \"high\", \"full\"}) {\n    QPixmap pix(ASSET_PATH + \"/offroad/icon_wifi_strength_\" + s + \".svg\");\n    strengths.push_back(pix.scaledToHeight(68, Qt::SmoothTransformation));\n  }\n  lock = QPixmap(ASSET_PATH + \"offroad/icon_lock_closed.svg\").scaledToWidth(49, Qt::SmoothTransformation);\n  checkmark = QPixmap(ASSET_PATH + \"offroad/icon_checkmark.svg\").scaledToWidth(49, Qt::SmoothTransformation);\n  circled_slash = QPixmap(ASSET_PATH + \"img_circled_slash.svg\").scaledToWidth(49, Qt::SmoothTransformation);\n\n  QLabel *scanning = new QLabel(\"Scanning for networks...\");\n  scanning->setStyleSheet(\"font-size: 65px;\");\n  main_layout->addWidget(scanning, 0, Qt::AlignCenter);\n\n  setStyleSheet(R\"(\n    QScrollBar::handle:vertical {\n      min-height: 0px;\n      border-radius: 4px;\n      background-color: #8A8A8A;\n    }\n    #forgetBtn {\n      font-size: 32px;\n      font-weight: 600;\n      color: #292929;\n      background-color: #BDBDBD;\n      border-width: 1px solid #828282;\n      border-radius: 5px;\n      padding: 40px;\n      padding-bottom: 16px;\n      padding-top: 16px;\n    }\n    #connecting {\n      font-size: 32px;\n      font-weight: 600;\n      color: white;\n      border-radius: 0;\n      padding: 27px;\n      padding-left: 43px;\n      padding-right: 43px;\n      background-color: black;\n    }\n    #ssidLabel {\n      font-size: 55px;\n      font-weight: 300;\n      text-align: left;\n      border: none;\n      padding-top: 50px;\n      padding-bottom: 50px;\n    }\n    #ssidLabel[disconnected=false] {\n      font-weight: 500;\n    }\n    #ssidLabel:disabled {\n      color: #696969;\n    }\n  )\");\n}\n\nvoid WifiUI::refresh() {\n  // TODO: don't rebuild this every time\n  clearLayout(main_layout);\n\n  if (wifi->seenNetworks.size() == 0) {\n    QLabel *scanning = new QLabel(\"Scanning for networks...\");\n    scanning->setStyleSheet(\"font-size: 65px;\");\n    main_layout->addWidget(scanning, 0, Qt::AlignCenter);\n    return;\n  }\n  QList<Network> sortedNetworks = wifi->seenNetworks.values();\n  std::sort(sortedNetworks.begin(), sortedNetworks.end(), compare_by_strength);\n\n  // add networks\n  int i = 0;\n  for (Network &network : sortedNetworks) {\n    QHBoxLayout *hlayout = new QHBoxLayout;\n    hlayout->setContentsMargins(44, 0, 73, 0);\n    hlayout->setSpacing(50);\n\n    // Clickable SSID label\n    ElidedLabel *ssidLabel = new ElidedLabel(network.ssid);\n    ssidLabel->setObjectName(\"ssidLabel\");\n    ssidLabel->setEnabled(network.security_type != SecurityType::UNSUPPORTED);\n    ssidLabel->setProperty(\"disconnected\", network.connected == ConnectedType::DISCONNECTED);\n    if (network.connected == ConnectedType::DISCONNECTED) {\n      QObject::connect(ssidLabel, &ElidedLabel::clicked, this, [=]() { emit connectToNetwork(network); });\n    }\n    hlayout->addWidget(ssidLabel, network.connected == ConnectedType::CONNECTING ? 0 : 1);\n\n    if (network.connected == ConnectedType::CONNECTING) {\n      QPushButton *connecting = new QPushButton(\"CONNECTING...\");\n      connecting->setObjectName(\"connecting\");\n      hlayout->addWidget(connecting, 2, Qt::AlignLeft);\n    }\n\n    // Forget button\n    if (wifi->isKnownConnection(network.ssid) && !wifi->isTetheringEnabled()) {\n      QPushButton *forgetBtn = new QPushButton(\"FORGET\");\n      forgetBtn->setObjectName(\"forgetBtn\");\n      QObject::connect(forgetBtn, &QPushButton::clicked, [=]() {\n        if (ConfirmationDialog::confirm(\"Forget WiFi Network \\\"\" + QString::fromUtf8(network.ssid) + \"\\\"?\", this)) {\n          wifi->forgetConnection(network.ssid);\n        }\n      });\n      hlayout->addWidget(forgetBtn, 0, Qt::AlignRight);\n    }\n\n    // Status icon\n    if (network.connected == ConnectedType::CONNECTED) {\n      QLabel *connectIcon = new QLabel();\n      connectIcon->setPixmap(checkmark);\n      hlayout->addWidget(connectIcon, 0, Qt::AlignRight);\n    } else if (network.security_type == SecurityType::UNSUPPORTED) {\n      QLabel *unsupportedIcon = new QLabel();\n      unsupportedIcon->setPixmap(circled_slash);\n      hlayout->addWidget(unsupportedIcon, 0, Qt::AlignRight);\n    } else if (network.security_type == SecurityType::WPA) {\n      QLabel *lockIcon = new QLabel();\n      lockIcon->setPixmap(lock);\n      hlayout->addWidget(lockIcon, 0, Qt::AlignRight);\n    } else {\n      hlayout->addSpacing(lock.width() + hlayout->spacing());\n    }\n\n    // Strength indicator\n    QLabel *strength = new QLabel();\n    strength->setPixmap(strengths[std::clamp((int)round(network.strength / 33.), 0, 3)]);\n    hlayout->addWidget(strength, 0, Qt::AlignRight);\n\n    main_layout->addLayout(hlayout);\n\n    // Don't add the last horizontal line\n    if (i+1 < wifi->seenNetworks.size()) {\n      main_layout->addWidget(horizontal_line(), 0);\n    }\n    i++;\n  }\n  main_layout->addStretch(1);\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/networking.h",
    "content": "#pragma once\n\n#include <QButtonGroup>\n#include <QMovie>\n#include <QVBoxLayout>\n#include <QWidget>\n\n#include \"selfdrive/ui/qt/offroad/wifiManager.h\"\n#include \"selfdrive/ui/qt/widgets/input.h\"\n#include \"selfdrive/ui/qt/widgets/ssh_keys.h\"\n#include \"selfdrive/ui/qt/widgets/toggle.h\"\n\nclass WifiUI : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit WifiUI(QWidget *parent = 0, WifiManager* wifi = 0);\n\nprivate:\n  WifiManager *wifi = nullptr;\n  QVBoxLayout* main_layout;\n  QPixmap lock;\n  QPixmap checkmark;\n  QPixmap circled_slash;\n  QVector<QPixmap> strengths;\n\nsignals:\n  void connectToNetwork(const Network &n);\n\npublic slots:\n  void refresh();\n};\n\nclass AdvancedNetworking : public QWidget {\n  Q_OBJECT\npublic:\n  explicit AdvancedNetworking(QWidget* parent = 0, WifiManager* wifi = 0);\n\nprivate:\n  LabelControl* ipLabel;\n  ToggleControl* tetheringToggle;\n  WifiManager* wifi = nullptr;\n  Params params;\n\nsignals:\n  void backPress();\n\npublic slots:\n  void toggleTethering(bool enabled);\n  void refresh();\n};\n\nclass Networking : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit Networking(QWidget* parent = 0, bool show_advanced = true);\n  WifiManager* wifi = nullptr;\n\nprivate:\n  QStackedLayout* main_layout = nullptr;\n  QWidget* wifiScreen = nullptr;\n  AdvancedNetworking* an = nullptr;\n\n  WifiUI* wifiWidget;\n\nprotected:\n  void showEvent(QShowEvent* event) override;\n\npublic slots:\n  void refresh();\n\nprivate slots:\n  void connectToNetwork(const Network &n);\n  void wrongPassword(const QString &ssid);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/networkmanager.h",
    "content": "/**\n * We are using a NetworkManager DBUS API : https://developer.gnome.org/NetworkManager/1.26/spec.html\n * */\n\n// https://developer.gnome.org/NetworkManager/1.26/nm-dbus-types.html#NM80211ApFlags\nconst int NM_802_11_AP_FLAGS_NONE = 0x00000000;\nconst int NM_802_11_AP_FLAGS_PRIVACY = 0x00000001;\nconst int NM_802_11_AP_FLAGS_WPS = 0x00000002;\n\n// https://developer.gnome.org/NetworkManager/1.26/nm-dbus-types.html#NM80211ApSecurityFlags\nconst int NM_802_11_AP_SEC_PAIR_WEP40      = 0x00000001;\nconst int NM_802_11_AP_SEC_PAIR_WEP104     = 0x00000002;\nconst int NM_802_11_AP_SEC_GROUP_WEP40     = 0x00000010;\nconst int NM_802_11_AP_SEC_GROUP_WEP104    = 0x00000020;\nconst int NM_802_11_AP_SEC_KEY_MGMT_PSK    = 0x00000100;\nconst int NM_802_11_AP_SEC_KEY_MGMT_802_1X = 0x00000200;\n\nconst QString NM_DBUS_PATH                          = \"/org/freedesktop/NetworkManager\";\nconst QString NM_DBUS_PATH_SETTINGS                 = \"/org/freedesktop/NetworkManager/Settings\";\n\nconst QString NM_DBUS_INTERFACE                     = \"org.freedesktop.NetworkManager\";\nconst QString NM_DBUS_INTERFACE_PROPERTIES          = \"org.freedesktop.DBus.Properties\";\nconst QString NM_DBUS_INTERFACE_SETTINGS            = \"org.freedesktop.NetworkManager.Settings\";\nconst QString NM_DBUS_INTERFACE_SETTINGS_CONNECTION = \"org.freedesktop.NetworkManager.Settings.Connection\";\nconst QString NM_DBUS_INTERFACE_DEVICE              = \"org.freedesktop.NetworkManager.Device\";\nconst QString NM_DBUS_INTERFACE_DEVICE_WIRELESS     = \"org.freedesktop.NetworkManager.Device.Wireless\";\nconst QString NM_DBUS_INTERFACE_ACCESS_POINT        = \"org.freedesktop.NetworkManager.AccessPoint\";\nconst QString NM_DBUS_INTERFACE_ACTIVE_CONNECTION   = \"org.freedesktop.NetworkManager.Connection.Active\";\nconst QString NM_DBUS_INTERFACE_IP4_CONFIG          = \"org.freedesktop.NetworkManager.IP4Config\";\n\nconst QString NM_DBUS_SERVICE                        = \"org.freedesktop.NetworkManager\";\n\nconst int NM_DEVICE_STATE_ACTIVATED = 100;\nconst int NM_DEVICE_STATE_NEED_AUTH = 60;\nconst int NM_DEVICE_TYPE_WIFI = 2;\nconst int NM_DEVICE_STATE_REASON_SUPPLICANT_DISCONNECT = 8;\nconst int DBUS_TIMEOUT = 100;\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/onboarding.cc",
    "content": "#include \"selfdrive/ui/qt/offroad/onboarding.h\"\n\n#include <QLabel>\n#include <QPainter>\n#include <QQmlContext>\n#include <QQuickWidget>\n#include <QVBoxLayout>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/widgets/input.h\"\n\nTrainingGuide::TrainingGuide(QWidget *parent) : QFrame(parent) {\n  setAttribute(Qt::WA_OpaquePaintEvent);\n}\n\nvoid TrainingGuide::mouseReleaseEvent(QMouseEvent *e) {\n  if (boundingRect[currentIndex].contains(e->x(), e->y())) {\n    if (currentIndex == 9) {\n      const QRect yes = QRect(692, 842, 492, 148);\n      Params().putBool(\"RecordFront\", yes.contains(e->x(), e->y()));\n    }\n    currentIndex += 1;\n  } else if (currentIndex == (boundingRect.size() - 2) && boundingRect.last().contains(e->x(), e->y())) {\n    currentIndex = 0;\n  }\n\n  if (currentIndex >= (boundingRect.size() - 1)) {\n    emit completedTraining();\n  } else {\n    image.load(IMG_PATH + \"step\" + QString::number(currentIndex) + \".png\");\n    update();\n  }\n}\n\nvoid TrainingGuide::showEvent(QShowEvent *event) {\n  currentIndex = 0;\n  image.load(IMG_PATH + \"step0.png\");\n}\n\nvoid TrainingGuide::paintEvent(QPaintEvent *event) {\n  QPainter painter(this);\n\n  QRect bg(0, 0, painter.device()->width(), painter.device()->height());\n  painter.fillRect(bg, QColor(\"#000000\"));\n\n  QRect rect(image.rect());\n  rect.moveCenter(bg.center());\n  painter.drawImage(rect.topLeft(), image);\n\n  // progress bar\n  if (currentIndex > 0 && currentIndex < (boundingRect.size() - 2)) {\n    const int h = 20;\n    const int w = (currentIndex / (float)(boundingRect.size() - 2)) * width();\n    painter.fillRect(QRect(0, height() - h, w, h), QColor(\"#465BEA\"));\n  }\n}\n\nvoid TermsPage::showEvent(QShowEvent *event) {\n  // late init, building QML widget takes 200ms\n  if (layout()) {\n    return;\n  }\n\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n  main_layout->setContentsMargins(45, 35, 45, 45);\n  main_layout->setSpacing(0);\n\n  QLabel *title = new QLabel(\"Terms & Conditions\");\n  title->setStyleSheet(\"font-size: 90px; font-weight: 600;\");\n  main_layout->addWidget(title);\n\n  main_layout->addSpacing(30);\n\n  QQuickWidget *text = new QQuickWidget(this);\n  text->setResizeMode(QQuickWidget::SizeRootObjectToView);\n  text->setSizePolicy(QSizePolicy::Expanding, QSizePolicy::Expanding);\n  text->setAttribute(Qt::WA_AlwaysStackOnTop);\n  text->setClearColor(QColor(\"#1B1B1B\"));\n\n  QString text_view = util::read_file(\"../assets/offroad/tc.html\").c_str();\n  text->rootContext()->setContextProperty(\"text_view\", text_view);\n\n  text->setSource(QUrl::fromLocalFile(\"qt/offroad/text_view.qml\"));\n\n  main_layout->addWidget(text, 1);\n  main_layout->addSpacing(50);\n\n  QObject *obj = (QObject*)text->rootObject();\n  QObject::connect(obj, SIGNAL(scroll()), SLOT(enableAccept()));\n\n  QHBoxLayout* buttons = new QHBoxLayout;\n  buttons->setMargin(0);\n  buttons->setSpacing(45);\n  main_layout->addLayout(buttons);\n\n  QPushButton *decline_btn = new QPushButton(\"Decline\");\n  buttons->addWidget(decline_btn);\n  QObject::connect(decline_btn, &QPushButton::clicked, this, &TermsPage::declinedTerms);\n\n  accept_btn = new QPushButton(\"Scroll to accept\");\n  accept_btn->setEnabled(false);\n  accept_btn->setStyleSheet(R\"(\n    QPushButton {\n      background-color: #465BEA;\n    }\n    QPushButton:disabled {\n      background-color: #4F4F4F;\n    }\n  )\");\n  buttons->addWidget(accept_btn);\n  QObject::connect(accept_btn, &QPushButton::clicked, this, &TermsPage::acceptedTerms);\n}\n\nvoid TermsPage::enableAccept() {\n  accept_btn->setText(\"Agree\");\n  accept_btn->setEnabled(true);\n}\n\nvoid DeclinePage::showEvent(QShowEvent *event) {\n  if (layout()) {\n    return;\n  }\n\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n  main_layout->setMargin(45);\n  main_layout->setSpacing(40);\n\n  QLabel *text = new QLabel(this);\n  text->setText(\"You must accept the Terms and Conditions in order to use openpilot.\");\n  text->setStyleSheet(R\"(font-size: 80px; font-weight: 300; margin: 200px;)\");\n  text->setWordWrap(true);\n  main_layout->addWidget(text, 0, Qt::AlignCenter);\n\n  QHBoxLayout* buttons = new QHBoxLayout;\n  buttons->setSpacing(45);\n  main_layout->addLayout(buttons);\n\n  QPushButton *back_btn = new QPushButton(\"Back\");\n  buttons->addWidget(back_btn);\n\n  QObject::connect(back_btn, &QPushButton::clicked, this, &DeclinePage::getBack);\n\n  QPushButton *uninstall_btn = new QPushButton(\"Decline, uninstall \" + getBrand());\n  uninstall_btn->setStyleSheet(\"background-color: #B73D3D\");\n  buttons->addWidget(uninstall_btn);\n  QObject::connect(uninstall_btn, &QPushButton::clicked, [=]() {\n    Params().putBool(\"DoUninstall\", true);\n  });\n}\n\nvoid OnboardingWindow::updateActiveScreen() {\n  bool accepted_terms = params.get(\"HasAcceptedTerms\") == current_terms_version;\n  bool training_done = params.get(\"CompletedTrainingVersion\") == current_training_version;\n  if (!accepted_terms) {\n    setCurrentIndex(0);\n  } else if (!training_done && !params.getBool(\"Passive\")) {\n    setCurrentIndex(1);\n  } else {\n    emit onboardingDone();\n  }\n}\n\nOnboardingWindow::OnboardingWindow(QWidget *parent) : QStackedWidget(parent) {\n  current_terms_version = params.get(\"TermsVersion\");\n  current_training_version = params.get(\"TrainingVersion\");\n\n  TermsPage* terms = new TermsPage(this);\n  addWidget(terms);\n  connect(terms, &TermsPage::acceptedTerms, [=]() {\n    Params().put(\"HasAcceptedTerms\", current_terms_version);\n    updateActiveScreen();\n  });\n  connect(terms, &TermsPage::declinedTerms, [=]() { setCurrentIndex(2); });\n\n  TrainingGuide* tr = new TrainingGuide(this);\n  addWidget(tr);\n  connect(tr, &TrainingGuide::completedTraining, [=]() {\n    Params().put(\"CompletedTrainingVersion\", current_training_version);\n    updateActiveScreen();\n  });\n\n  DeclinePage* declinePage = new DeclinePage(this);\n  addWidget(declinePage);\n  connect(declinePage, &DeclinePage::getBack, [=]() { updateActiveScreen(); });\n\n  setStyleSheet(R\"(\n    * {\n      color: white;\n      background-color: black;\n    }\n    QPushButton {\n      height: 160px;\n      font-size: 55px;\n      font-weight: 400;\n      border-radius: 10px;\n      background-color: #4F4F4F;\n    }\n  )\");\n}\n\nvoid OnboardingWindow::showEvent(QShowEvent *event) {\n  updateActiveScreen();\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/onboarding.h",
    "content": "#pragma once\n\n#include <QImage>\n#include <QMouseEvent>\n#include <QPushButton>\n#include <QStackedWidget>\n#include <QWidget>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n\nclass TrainingGuide : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit TrainingGuide(QWidget *parent = 0);\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n  void paintEvent(QPaintEvent *event) override;\n  void mouseReleaseEvent(QMouseEvent* e) override;\n\n  QImage image;\n  int currentIndex = 0;\n\n  // Bounding boxes for each training guide step\n  const QRect continueBtnStandard = {1610, 0, 310, 1080};\n  QVector<QRect> boundingRectStandard {\n    QRect(650, 710, 720, 190),\n    continueBtnStandard,\n    continueBtnStandard,\n    QRect(1442, 565, 230, 310),\n    QRect(1515, 562, 133, 60),\n    continueBtnStandard,\n    QRect(1580, 630, 215, 130),\n    QRect(1210, 0, 485, 590),\n    QRect(1460, 400, 375, 210),\n    QRect(166, 842, 1019, 148),\n    QRect(1460, 210, 300, 310),\n    continueBtnStandard,\n    QRect(1375, 80, 545, 1000),\n    continueBtnStandard,\n    QRect(1610, 130, 280, 800),\n    QRect(1385, 485, 400, 270),\n    continueBtnStandard,\n    continueBtnStandard,\n    QRect(1036, 769, 718, 189),\n    QRect(201, 769, 718, 189),\n  };\n\n  const QRect continueBtnWide = {1850, 0, 310, 1080};\n  QVector<QRect> boundingRectWide {\n    QRect(654, 721, 718, 189),\n    continueBtnWide,\n    continueBtnWide,\n    QRect(1690, 570, 165, 300),\n    QRect(1690, 560, 133, 60),\n    continueBtnWide,\n    QRect(1820, 630, 180, 155),\n    QRect(1360, 0, 460, 620),\n    QRect(1570, 400, 375, 215),\n    QRect(167, 842, 1018, 148),\n    QRect(1610, 210, 295, 310),\n    continueBtnWide,\n    QRect(1555, 90, 610, 990),\n    continueBtnWide,\n    QRect(1600, 140, 280, 790),\n    QRect(1385, 490, 750, 270),\n    continueBtnWide,\n    continueBtnWide,\n    QRect(1138, 755, 718, 189),\n    QRect(303, 755, 718, 189),\n  };\n\n  const QString IMG_PATH = WIDE_UI ? \"../assets/training_wide/\" : \"../assets/training/\";\n  const QVector<QRect> boundingRect = WIDE_UI ? boundingRectWide : boundingRectStandard;\n\nsignals:\n  void completedTraining();\n};\n\n\nclass TermsPage : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit TermsPage(QWidget *parent = 0) : QFrame(parent) {};\n\npublic slots:\n  void enableAccept();\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n\n  QPushButton *accept_btn;\n\nsignals:\n  void acceptedTerms();\n  void declinedTerms();\n};\n\nclass DeclinePage : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit DeclinePage(QWidget *parent = 0) : QFrame(parent) {};\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n\nsignals:\n  void getBack();\n};\n\nclass OnboardingWindow : public QStackedWidget {\n  Q_OBJECT\n\npublic:\n  explicit OnboardingWindow(QWidget *parent = 0);\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n  void updateActiveScreen();\n\n  Params params;\n  std::string current_terms_version;\n  std::string current_training_version;\n\nsignals:\n  void onboardingDone();\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/settings.cc",
    "content": "#include \"selfdrive/ui/qt/offroad/settings.h\"\n\n#include <cassert>\n#include <string>\n\n#include <QDebug>\n\n#ifndef QCOM\n#include \"selfdrive/ui/qt/offroad/networking.h\"\n#endif\n\n#ifdef ENABLE_MAPS\n#include \"selfdrive/ui/qt/maps/map_settings.h\"\n#endif\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/widgets/controls.h\"\n#include \"selfdrive/ui/qt/widgets/input.h\"\n#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n#include \"selfdrive/ui/qt/widgets/ssh_keys.h\"\n#include \"selfdrive/ui/qt/widgets/toggle.h\"\n#include \"selfdrive/ui/ui.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n\nTogglesPanel::TogglesPanel(QWidget *parent) : QWidget(parent) {\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n\n  QList<ParamControl*> toggles;\n\n  toggles.append(new ParamControl(\"OpenpilotEnabledToggle\",\n                                  \"Enable openpilot\",\n                                  \"Use the openpilot system for adaptive cruise control and lane keep driver assistance. Your attention is required at all times to use this feature. Changing this setting takes effect when the car is powered off.\",\n                                  \"../assets/offroad/icon_openpilot.png\",\n                                  this));\n  toggles.append(new ParamControl(\"IsLdwEnabled\",\n                                  \"Enable Lane Departure Warnings\",\n                                  \"Receive alerts to steer back into the lane when your vehicle drifts over a detected lane line without a turn signal activated while driving over 31mph (50kph).\",\n                                  \"../assets/offroad/icon_warning.png\",\n                                  this));\n  toggles.append(new ParamControl(\"IsRHD\",\n                                  \"Enable Right-Hand Drive\",\n                                  \"Allow openpilot to obey left-hand traffic conventions and perform driver monitoring on right driver seat.\",\n                                  \"../assets/offroad/icon_openpilot_mirrored.png\",\n                                  this));\n  toggles.append(new ParamControl(\"IsMetric\",\n                                  \"Use Metric System\",\n                                  \"Display speed in km/h instead of mp/h.\",\n                                  \"../assets/offroad/icon_metric.png\",\n                                  this));\n  toggles.append(new ParamControl(\"CommunityFeaturesToggle\",\n                                  \"Enable Community Features\",\n                                  \"Use features from the open source community that are not maintained or supported by comma.ai and have not been confirmed to meet the standard safety model. These features include community supported cars and community supported hardware. Be extra cautious when using these features\",\n                                  \"../assets/offroad/icon_shell.png\",\n                                  this));\n\n  toggles.append(new ParamControl(\"UploadRaw\",\n                                  \"Upload Raw Logs\",\n                                  \"Upload full logs and full resolution video by default while on WiFi. If not enabled, individual logs can be marked for upload at my.comma.ai/useradmin.\",\n                                  \"../assets/offroad/icon_network.png\",\n                                  this));\n\n  ParamControl *record_toggle = new ParamControl(\"RecordFront\",\n                                                 \"Record and Upload Driver Camera\",\n                                                 \"Upload data from the driver facing camera and help improve the driver monitoring algorithm.\",\n                                                 \"../assets/offroad/icon_monitoring.png\",\n                                                 this);\n  toggles.append(record_toggle);\n  toggles.append(new ParamControl(\"EndToEndToggle\",\n                                  \"\\U0001f96c Disable use of lanelines (Alpha) \\U0001f96c\",\n                                  \"In this mode openpilot will ignore lanelines and just drive how it thinks a human would.\",\n                                  \"../assets/offroad/icon_road.png\",\n                                  this));\n\n#ifdef ENABLE_MAPS\n  toggles.append(new ParamControl(\"NavSettingTime24h\",\n                                  \"Show ETA in 24h format\",\n                                  \"Use 24h format instead of am/pm\",\n                                  \"../assets/offroad/icon_metric.png\",\n                                  this));\n#endif\n\n  bool record_lock = Params().getBool(\"RecordFrontLock\");\n  record_toggle->setEnabled(!record_lock);\n\n  for(ParamControl *toggle : toggles) {\n    if(main_layout->count() != 0) {\n      main_layout->addWidget(horizontal_line());\n    }\n    main_layout->addWidget(toggle);\n  }\n}\n\nDevicePanel::DevicePanel(QWidget* parent) : QWidget(parent) {\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n  Params params = Params();\n  main_layout->addWidget(new LabelControl(\"Dongle ID\", getDongleId().value_or(\"N/A\")));\n  main_layout->addWidget(horizontal_line());\n\n  QString serial = QString::fromStdString(params.get(\"HardwareSerial\", false));\n  main_layout->addWidget(new LabelControl(\"Serial\", serial));\n\n  // offroad-only buttons\n\n  auto dcamBtn = new ButtonControl(\"Driver Camera\", \"PREVIEW\",\n                                        \"Preview the driver facing camera to help optimize device mounting position for best driver monitoring experience. (vehicle must be off)\");\n  connect(dcamBtn, &ButtonControl::clicked, [=]() { emit showDriverView(); });\n\n  QString resetCalibDesc = \"openpilot requires the device to be mounted within 4° left or right and within 5° up or down. openpilot is continuously calibrating, resetting is rarely required.\";\n  auto resetCalibBtn = new ButtonControl(\"Reset Calibration\", \"RESET\", resetCalibDesc);\n  connect(resetCalibBtn, &ButtonControl::clicked, [=]() {\n    if (ConfirmationDialog::confirm(\"Are you sure you want to reset calibration?\", this)) {\n      Params().remove(\"CalibrationParams\");\n    }\n  });\n  connect(resetCalibBtn, &ButtonControl::showDescription, [=]() {\n    QString desc = resetCalibDesc;\n    std::string calib_bytes = Params().get(\"CalibrationParams\");\n    if (!calib_bytes.empty()) {\n      try {\n        AlignedBuffer aligned_buf;\n        capnp::FlatArrayMessageReader cmsg(aligned_buf.align(calib_bytes.data(), calib_bytes.size()));\n        auto calib = cmsg.getRoot<cereal::Event>().getLiveCalibration();\n        if (calib.getCalStatus() != 0) {\n          double pitch = calib.getRpyCalib()[1] * (180 / M_PI);\n          double yaw = calib.getRpyCalib()[2] * (180 / M_PI);\n          desc += QString(\" Your device is pointed %1° %2 and %3° %4.\")\n                                .arg(QString::number(std::abs(pitch), 'g', 1), pitch > 0 ? \"up\" : \"down\",\n                                     QString::number(std::abs(yaw), 'g', 1), yaw > 0 ? \"right\" : \"left\");\n        }\n      } catch (kj::Exception) {\n        qInfo() << \"invalid CalibrationParams\";\n      }\n    }\n    resetCalibBtn->setDescription(desc);\n  });\n\n  ButtonControl *retrainingBtn = nullptr;\n  if (!params.getBool(\"Passive\")) {\n    retrainingBtn = new ButtonControl(\"Review Training Guide\", \"REVIEW\", \"Review the rules, features, and limitations of openpilot\");\n    connect(retrainingBtn, &ButtonControl::clicked, [=]() {\n      if (ConfirmationDialog::confirm(\"Are you sure you want to review the training guide?\", this)) {\n        Params().remove(\"CompletedTrainingVersion\");\n        emit reviewTrainingGuide();\n      }\n    });\n  }\n\n  ButtonControl *regulatoryBtn = nullptr;\n  if (Hardware::TICI()) {\n    regulatoryBtn = new ButtonControl(\"Regulatory\", \"VIEW\", \"\");\n    connect(regulatoryBtn, &ButtonControl::clicked, [=]() {\n      const std::string txt = util::read_file(ASSET_PATH.toStdString() + \"/offroad/fcc.html\");\n      RichTextDialog::alert(QString::fromStdString(txt), this);\n    });\n  }\n\n  for (auto btn : {dcamBtn, resetCalibBtn, retrainingBtn, regulatoryBtn}) {\n    if (btn) {\n      main_layout->addWidget(horizontal_line());\n      connect(parent, SIGNAL(offroadTransition(bool)), btn, SLOT(setEnabled(bool)));\n      main_layout->addWidget(btn);\n    }\n  }\n\n  // power buttons\n  QHBoxLayout *power_layout = new QHBoxLayout();\n  power_layout->setSpacing(30);\n\n  QPushButton *reboot_btn = new QPushButton(\"Reboot\");\n  reboot_btn->setObjectName(\"reboot_btn\");\n  power_layout->addWidget(reboot_btn);\n  QObject::connect(reboot_btn, &QPushButton::clicked, [=]() {\n    if (ConfirmationDialog::confirm(\"Are you sure you want to reboot?\", this)) {\n      Hardware::reboot();\n    }\n  });\n\n  QPushButton *poweroff_btn = new QPushButton(\"Power Off\");\n  poweroff_btn->setObjectName(\"poweroff_btn\");\n  power_layout->addWidget(poweroff_btn);\n  QObject::connect(poweroff_btn, &QPushButton::clicked, [=]() {\n    if (ConfirmationDialog::confirm(\"Are you sure you want to power off?\", this)) {\n      Hardware::poweroff();\n    }\n  });\n\n  setStyleSheet(R\"(\n    QPushButton {\n      height: 120px;\n      border-radius: 15px;\n    }\n    #reboot_btn { background-color: #393939; }\n    #reboot_btn:pressed { background-color: #4a4a4a; }\n    #poweroff_btn { background-color: #E22C2C; }\n    #poweroff_btn:pressed { background-color: #FF2424; }\n  )\");\n  main_layout->addLayout(power_layout);\n}\n\nSoftwarePanel::SoftwarePanel(QWidget* parent) : QWidget(parent) {\n  gitBranchLbl = new LabelControl(\"Git Branch\");\n  gitCommitLbl = new LabelControl(\"Git Commit\");\n  osVersionLbl = new LabelControl(\"OS Version\");\n  versionLbl = new LabelControl(\"Version\", \"\", QString::fromStdString(params.get(\"ReleaseNotes\")).trimmed());\n  lastUpdateLbl = new LabelControl(\"Last Update Check\", \"\", \"The last time openpilot successfully checked for an update. The updater only runs while the car is off.\");\n  updateBtn = new ButtonControl(\"Check for Update\", \"\");\n  connect(updateBtn, &ButtonControl::clicked, [=]() {\n    if (params.getBool(\"IsOffroad\")) {\n      fs_watch->addPath(QString::fromStdString(params.getParamPath(\"LastUpdateTime\")));\n      fs_watch->addPath(QString::fromStdString(params.getParamPath(\"UpdateFailedCount\")));\n      updateBtn->setText(\"CHECKING\");\n      updateBtn->setEnabled(false);\n    }\n    std::system(\"pkill -1 -f selfdrive.updated\");\n  });\n\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n  QWidget *widgets[] = {versionLbl, lastUpdateLbl, updateBtn, gitBranchLbl, gitCommitLbl, osVersionLbl};\n  for (int i = 0; i < std::size(widgets); ++i) {\n    main_layout->addWidget(widgets[i]);\n    main_layout->addWidget(horizontal_line());\n  }\n\n  auto uninstallBtn = new ButtonControl(\"Uninstall \" + getBrand(), \"UNINSTALL\");\n  connect(uninstallBtn, &ButtonControl::clicked, [=]() {\n    if (ConfirmationDialog::confirm(\"Are you sure you want to uninstall?\", this)) {\n      Params().putBool(\"DoUninstall\", true);\n    }\n  });\n  connect(parent, SIGNAL(offroadTransition(bool)), uninstallBtn, SLOT(setEnabled(bool)));\n  main_layout->addWidget(uninstallBtn);\n\n  fs_watch = new QFileSystemWatcher(this);\n  QObject::connect(fs_watch, &QFileSystemWatcher::fileChanged, [=](const QString path) {\n    int update_failed_count = params.get<int>(\"UpdateFailedCount\").value_or(0);\n    if (path.contains(\"UpdateFailedCount\") && update_failed_count > 0) {\n      lastUpdateLbl->setText(\"failed to fetch update\");\n      updateBtn->setText(\"CHECK\");\n      updateBtn->setEnabled(true);\n    } else if (path.contains(\"LastUpdateTime\")) {\n      updateLabels();\n    }\n  });\n}\n\nvoid SoftwarePanel::showEvent(QShowEvent *event) {\n  updateLabels();\n}\n\nvoid SoftwarePanel::updateLabels() {\n  QString lastUpdate = \"\";\n  auto tm = params.get(\"LastUpdateTime\");\n  if (!tm.empty()) {\n    lastUpdate = timeAgo(QDateTime::fromString(QString::fromStdString(tm + \"Z\"), Qt::ISODate));\n  }\n\n  versionLbl->setText(getBrandVersion());\n  lastUpdateLbl->setText(lastUpdate);\n  updateBtn->setText(\"CHECK\");\n  updateBtn->setEnabled(true);\n  gitBranchLbl->setText(QString::fromStdString(params.get(\"GitBranch\")));\n  gitCommitLbl->setText(QString::fromStdString(params.get(\"GitCommit\")).left(10));\n  osVersionLbl->setText(QString::fromStdString(Hardware::get_os_version()).trimmed());\n}\n\nQWidget * network_panel(QWidget * parent) {\n#ifdef QCOM\n  QWidget *w = new QWidget(parent);\n  QVBoxLayout *layout = new QVBoxLayout(w);\n  layout->setSpacing(30);\n\n  // wifi + tethering buttons\n  auto wifiBtn = new ButtonControl(\"WiFi Settings\", \"OPEN\");\n  QObject::connect(wifiBtn, &ButtonControl::clicked, [=]() { HardwareEon::launch_wifi(); });\n  layout->addWidget(wifiBtn);\n  layout->addWidget(horizontal_line());\n\n  auto tetheringBtn = new ButtonControl(\"Tethering Settings\", \"OPEN\");\n  QObject::connect(tetheringBtn, &ButtonControl::clicked, [=]() { HardwareEon::launch_tethering(); });\n  layout->addWidget(tetheringBtn);\n  layout->addWidget(horizontal_line());\n\n  // SSH key management\n  layout->addWidget(new SshToggle());\n  layout->addWidget(horizontal_line());\n  layout->addWidget(new SshControl());\n\n  layout->addStretch(1);\n#else\n  Networking *w = new Networking(parent);\n#endif\n  return w;\n}\n\nvoid SettingsWindow::showEvent(QShowEvent *event) {\n  panel_widget->setCurrentIndex(0);\n  nav_btns->buttons()[0]->setChecked(true);\n}\n\nSettingsWindow::SettingsWindow(QWidget *parent) : QFrame(parent) {\n\n  // setup two main layouts\n  sidebar_widget = new QWidget;\n  QVBoxLayout *sidebar_layout = new QVBoxLayout(sidebar_widget);\n  sidebar_layout->setMargin(0);\n  panel_widget = new QStackedWidget();\n  panel_widget->setStyleSheet(R\"(\n    border-radius: 30px;\n    background-color: #292929;\n  )\");\n\n  // close button\n  QPushButton *close_btn = new QPushButton(\"×\");\n  close_btn->setStyleSheet(R\"(\n    QPushButton {\n      font-size: 140px;\n      padding-bottom: 20px;\n      font-weight: bold;\n      border 1px grey solid;\n      border-radius: 100px;\n      background-color: #292929;\n      font-weight: 400;\n    }\n    QPushButton:pressed {\n      background-color: #3B3B3B;\n    }\n  )\");\n  close_btn->setFixedSize(200, 200);\n  sidebar_layout->addSpacing(45);\n  sidebar_layout->addWidget(close_btn, 0, Qt::AlignCenter);\n  QObject::connect(close_btn, &QPushButton::clicked, this, &SettingsWindow::closeSettings);\n\n  // setup panels\n  DevicePanel *device = new DevicePanel(this);\n  QObject::connect(device, &DevicePanel::reviewTrainingGuide, this, &SettingsWindow::reviewTrainingGuide);\n  QObject::connect(device, &DevicePanel::showDriverView, this, &SettingsWindow::showDriverView);\n\n  QList<QPair<QString, QWidget *>> panels = {\n    {\"Device\", device},\n    {\"Network\", network_panel(this)},\n    {\"Toggles\", new TogglesPanel(this)},\n    {\"Software\", new SoftwarePanel(this)},\n  };\n\n#ifdef ENABLE_MAPS\n  auto map_panel = new MapPanel(this);\n  panels.push_back({\"Navigation\", map_panel});\n  QObject::connect(map_panel, &MapPanel::closeSettings, this, &SettingsWindow::closeSettings);\n#endif\n\n  const int padding = panels.size() > 3 ? 25 : 35;\n\n  nav_btns = new QButtonGroup();\n  for (auto &[name, panel] : panels) {\n    QPushButton *btn = new QPushButton(name);\n    btn->setCheckable(true);\n    btn->setChecked(nav_btns->buttons().size() == 0);\n    btn->setStyleSheet(QString(R\"(\n      QPushButton {\n        color: grey;\n        border: none;\n        background: none;\n        font-size: 65px;\n        font-weight: 500;\n        padding-top: %1px;\n        padding-bottom: %1px;\n      }\n      QPushButton:checked {\n        color: white;\n      }\n      QPushButton:pressed {\n        color: #ADADAD;\n      }\n    )\").arg(padding));\n\n    nav_btns->addButton(btn);\n    sidebar_layout->addWidget(btn, 0, Qt::AlignRight);\n\n    const int lr_margin = name != \"Network\" ? 50 : 0;  // Network panel handles its own margins\n    panel->setContentsMargins(lr_margin, 25, lr_margin, 25);\n\n    ScrollView *panel_frame = new ScrollView(panel, this);\n    panel_widget->addWidget(panel_frame);\n\n    QObject::connect(btn, &QPushButton::clicked, [=, w = panel_frame]() {\n      btn->setChecked(true);\n      panel_widget->setCurrentWidget(w);\n    });\n  }\n  sidebar_layout->setContentsMargins(50, 50, 100, 50);\n\n  // main settings layout, sidebar + main panel\n  QHBoxLayout *main_layout = new QHBoxLayout(this);\n\n  sidebar_widget->setFixedWidth(500);\n  main_layout->addWidget(sidebar_widget);\n  main_layout->addWidget(panel_widget);\n\n  setStyleSheet(R\"(\n    * {\n      color: white;\n      font-size: 50px;\n    }\n    SettingsWindow {\n      background-color: black;\n    }\n  )\");\n}\n\nvoid SettingsWindow::hideEvent(QHideEvent *event) {\n#ifdef QCOM\n  HardwareEon::close_activities();\n#endif\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/settings.h",
    "content": "#pragma once\n\n#include <QButtonGroup>\n#include <QFileSystemWatcher>\n#include <QFrame>\n#include <QLabel>\n#include <QPushButton>\n#include <QStackedWidget>\n#include <QWidget>\n\n\n#include \"selfdrive/ui/qt/widgets/controls.h\"\n\n// ********** settings window + top-level panels **********\n\nclass DevicePanel : public QWidget {\n  Q_OBJECT\npublic:\n  explicit DevicePanel(QWidget* parent = nullptr);\nsignals:\n  void reviewTrainingGuide();\n  void showDriverView();\n};\n\nclass TogglesPanel : public QWidget {\n  Q_OBJECT\npublic:\n  explicit TogglesPanel(QWidget *parent = nullptr);\n};\n\nclass SoftwarePanel : public QWidget {\n  Q_OBJECT\npublic:\n  explicit SoftwarePanel(QWidget* parent = nullptr);\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n  void updateLabels();\n\n  LabelControl *gitBranchLbl;\n  LabelControl *gitCommitLbl;\n  LabelControl *osVersionLbl;\n  LabelControl *versionLbl;\n  LabelControl *lastUpdateLbl;\n  ButtonControl *updateBtn;\n\n  Params params;\n  QFileSystemWatcher *fs_watch;\n};\n\nclass SettingsWindow : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit SettingsWindow(QWidget *parent = 0);\n\nprotected:\n  void hideEvent(QHideEvent *event) override;\n  void showEvent(QShowEvent *event) override;\n\nsignals:\n  void closeSettings();\n  void offroadTransition(bool offroad);\n  void reviewTrainingGuide();\n  void showDriverView();\n\nprivate:\n  QPushButton *sidebar_alert_widget;\n  QWidget *sidebar_widget;\n  QButtonGroup *nav_btns;\n  QStackedWidget *panel_widget;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/text_view.qml",
    "content": "import QtQuick 2.0\n\nItem {\n  id: root\n  signal scroll()\n\n  Flickable {\n    id: flickArea\n    objectName: \"flickArea\"\n    anchors.fill: parent\n    contentHeight: helpText.height\n    contentWidth: width - (leftMargin + rightMargin)\n    bottomMargin: 50\n    topMargin: 50\n    rightMargin: 50\n    leftMargin: 50\n    flickableDirection: Flickable.VerticalFlick\n    flickDeceleration: 7500.0\n    maximumFlickVelocity: 10000.0\n    pixelAligned: true\n\n    onAtYEndChanged: root.scroll()\n\n    Text {\n      id: helpText\n      width: flickArea.contentWidth\n      font.family: \"Inter\"\n      font.weight: \"Light\"\n      font.pixelSize: 50\n      textFormat: Text.RichText\n      color: \"#C9C9C9\"\n      wrapMode: Text.Wrap\n      text: text_view\n    }\n  }\n\n  Rectangle {\n    id: scrollbar\n    anchors.right: flickArea.right\n    anchors.rightMargin: 20\n    y: flickArea.topMargin + flickArea.visibleArea.yPosition * (flickArea.height - flickArea.bottomMargin - flickArea.topMargin)\n    width: 12\n    radius: 6\n    height: flickArea.visibleArea.heightRatio * (flickArea.height - flickArea.bottomMargin - flickArea.topMargin)\n    color: \"#808080\"\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/wifiManager.cc",
    "content": "#include \"selfdrive/ui/qt/offroad/wifiManager.h\"\n\n#include <algorithm>\n#include <set>\n#include <cstdlib>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/ui/qt/util.h\"\n\ntemplate <typename T>\nT get_response(QDBusMessage response) {\n  QVariant first =  response.arguments().at(0);\n  QDBusVariant dbvFirst = first.value<QDBusVariant>();\n  QVariant vFirst = dbvFirst.variant();\n  if (vFirst.canConvert<T>()) {\n    return vFirst.value<T>();\n  } else {\n    LOGE(\"Variant unpacking failure\");\n    return T();\n  }\n}\n\nbool compare_by_strength(const Network &a, const Network &b) {\n  if (a.connected == ConnectedType::CONNECTED) return true;\n  if (b.connected == ConnectedType::CONNECTED) return false;\n  if (a.connected == ConnectedType::CONNECTING) return true;\n  if (b.connected == ConnectedType::CONNECTING) return false;\n  return a.strength > b.strength;\n}\n\nWifiManager::WifiManager(QWidget* parent) : QWidget(parent) {\n  qDBusRegisterMetaType<Connection>();\n  qDBusRegisterMetaType<IpConfig>();\n  connecting_to_network = \"\";\n\n  // Set tethering ssid as \"weedle\" + first 4 characters of a dongle id\n  tethering_ssid = \"weedle\";\n  if (auto dongle_id = getDongleId()) {\n    tethering_ssid += \"-\" + dongle_id->left(4);\n  }\n\n  adapter = getAdapter();\n  if (!adapter.isEmpty()) {\n    setup();\n  } else {\n    bus.connect(NM_DBUS_SERVICE, NM_DBUS_PATH, NM_DBUS_INTERFACE, \"DeviceAdded\", this, SLOT(deviceAdded(QDBusObjectPath)));\n  }\n\n  QTimer* timer = new QTimer(this);\n  QObject::connect(timer, &QTimer::timeout, this, [=]() {\n    if (!adapter.isEmpty() && this->isVisible()) {\n      requestScan();\n    }\n  });\n  timer->start(5000);\n}\n\nvoid WifiManager::setup() {\n  QDBusInterface nm(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_DEVICE, bus);\n  bus.connect(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_DEVICE, \"StateChanged\", this, SLOT(stateChange(unsigned int, unsigned int, unsigned int)));\n  bus.connect(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_PROPERTIES, \"PropertiesChanged\", this, SLOT(propertyChange(QString, QVariantMap, QStringList)));\n\n  bus.connect(NM_DBUS_SERVICE, NM_DBUS_PATH_SETTINGS, NM_DBUS_INTERFACE_SETTINGS, \"ConnectionRemoved\", this, SLOT(connectionRemoved(QDBusObjectPath)));\n  bus.connect(NM_DBUS_SERVICE, NM_DBUS_PATH_SETTINGS, NM_DBUS_INTERFACE_SETTINGS, \"NewConnection\", this, SLOT(newConnection(QDBusObjectPath)));\n\n  QDBusInterface device_props(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  device_props.setTimeout(DBUS_TIMEOUT);\n  QDBusMessage response = device_props.call(\"Get\", NM_DBUS_INTERFACE_DEVICE, \"State\");\n  raw_adapter_state = get_response<uint>(response);\n\n  initActiveAp();\n  initConnections();\n  requestScan();\n}\n\nvoid WifiManager::refreshNetworks() {\n  if (adapter.isEmpty()) {\n    return;\n  }\n  seenNetworks.clear();\n  ipv4_address = get_ipv4_address();\n\n  QDBusInterface nm(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_DEVICE_WIRELESS, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n\n  const QDBusReply<QList<QDBusObjectPath>> &response = nm.call(\"GetAllAccessPoints\");\n  for (const QDBusObjectPath &path : response.value()) {\n    const QByteArray &ssid = get_property(path.path(), \"Ssid\");\n    unsigned int strength = get_ap_strength(path.path());\n    if (ssid.isEmpty() || (seenNetworks.contains(ssid) &&\n        strength <= seenNetworks.value(ssid).strength)) {\n      continue;\n    }\n    SecurityType security = getSecurityType(path.path());\n    ConnectedType ctype;\n    QString activeSsid = (activeAp != \"\" && activeAp != \"/\") ? get_property(activeAp, \"Ssid\") : \"\";\n    if (ssid != activeSsid) {\n      ctype = ConnectedType::DISCONNECTED;\n    } else {\n      if (ssid == connecting_to_network) {\n        ctype = ConnectedType::CONNECTING;\n      } else {\n        ctype = ConnectedType::CONNECTED;\n      }\n    }\n    Network network = {ssid, strength, ctype, security};\n    seenNetworks[ssid] = network;\n  }\n}\n\nQString WifiManager::get_ipv4_address() {\n  if (raw_adapter_state != NM_DEVICE_STATE_ACTIVATED) {\n    return \"\";\n  }\n  QVector<QDBusObjectPath> conns = get_active_connections();\n  for (auto &p : conns) {\n    QDBusInterface nm(NM_DBUS_SERVICE, p.path(), NM_DBUS_INTERFACE_PROPERTIES, bus);\n    nm.setTimeout(DBUS_TIMEOUT);\n\n    QDBusObjectPath pth = get_response<QDBusObjectPath>(nm.call(\"Get\", NM_DBUS_INTERFACE_ACTIVE_CONNECTION, \"Ip4Config\"));\n    QString ip4config = pth.path();\n\n    QString type = get_response<QString>(nm.call(\"Get\", NM_DBUS_INTERFACE_ACTIVE_CONNECTION, \"Type\"));\n\n    if (type == \"802-11-wireless\") {\n      QDBusInterface nm2(NM_DBUS_SERVICE, ip4config, NM_DBUS_INTERFACE_PROPERTIES, bus);\n      nm2.setTimeout(DBUS_TIMEOUT);\n\n      const QDBusArgument &arr = get_response<QDBusArgument>(nm2.call(\"Get\", NM_DBUS_INTERFACE_IP4_CONFIG, \"AddressData\"));\n      QMap<QString, QVariant> pth2;\n      arr.beginArray();\n      while (!arr.atEnd()) {\n        arr >> pth2;\n        QString ipv4 = pth2.value(\"address\").value<QString>();\n        arr.endArray();\n        return ipv4;\n      }\n      arr.endArray();\n    }\n  }\n  return \"\";\n}\n\nSecurityType WifiManager::getSecurityType(const QString &path) {\n  int sflag = get_property(path, \"Flags\").toInt();\n  int wpaflag = get_property(path, \"WpaFlags\").toInt();\n  int rsnflag = get_property(path, \"RsnFlags\").toInt();\n  int wpa_props = wpaflag | rsnflag;\n\n  // obtained by looking at flags of networks in the office as reported by an Android phone\n  const int supports_wpa = NM_802_11_AP_SEC_PAIR_WEP40 | NM_802_11_AP_SEC_PAIR_WEP104 | NM_802_11_AP_SEC_GROUP_WEP40 | NM_802_11_AP_SEC_GROUP_WEP104 | NM_802_11_AP_SEC_KEY_MGMT_PSK;\n\n  if ((sflag == NM_802_11_AP_FLAGS_NONE) || ((sflag & NM_802_11_AP_FLAGS_WPS) && !(wpa_props & supports_wpa))) {\n    return SecurityType::OPEN;\n  } else if ((sflag & NM_802_11_AP_FLAGS_PRIVACY) && (wpa_props & supports_wpa) && !(wpa_props & NM_802_11_AP_SEC_KEY_MGMT_802_1X)) {\n    return SecurityType::WPA;\n  } else {\n    LOGW(\"Unsupported network! sflag: %d, wpaflag: %d, rsnflag: %d\", sflag, wpaflag, rsnflag);\n    return SecurityType::UNSUPPORTED;\n  }\n}\n\nvoid WifiManager::connect(const Network &n) {\n  return connect(n, \"\", \"\");\n}\n\nvoid WifiManager::connect(const Network &n, const QString &password) {\n  return connect(n, \"\", password);\n}\n\nvoid WifiManager::connect(const Network &n, const QString &username, const QString &password) {\n  connecting_to_network = n.ssid;\n  // disconnect();\n  forgetConnection(n.ssid); //Clear all connections that may already exist to the network we are connecting\n  connect(n.ssid, username, password, n.security_type);\n}\n\nvoid WifiManager::connect(const QByteArray &ssid, const QString &username, const QString &password, SecurityType security_type) {\n  Connection connection;\n  connection[\"connection\"][\"type\"] = \"802-11-wireless\";\n  connection[\"connection\"][\"uuid\"] = QUuid::createUuid().toString().remove('{').remove('}');\n  connection[\"connection\"][\"id\"] = \"openpilot connection \"+QString::fromStdString(ssid.toStdString());\n  connection[\"connection\"][\"autoconnect-retries\"] = 0;\n\n  connection[\"802-11-wireless\"][\"ssid\"] = ssid;\n  connection[\"802-11-wireless\"][\"mode\"] = \"infrastructure\";\n\n  if (security_type == SecurityType::WPA) {\n    connection[\"802-11-wireless-security\"][\"key-mgmt\"] = \"wpa-psk\";\n    connection[\"802-11-wireless-security\"][\"auth-alg\"] = \"open\";\n    connection[\"802-11-wireless-security\"][\"psk\"] = password;\n  }\n\n  connection[\"ipv4\"][\"method\"] = \"auto\";\n  connection[\"ipv4\"][\"dns-priority\"] = 600;\n  connection[\"ipv6\"][\"method\"] = \"ignore\";\n\n  QDBusInterface nm_settings(NM_DBUS_SERVICE, NM_DBUS_PATH_SETTINGS, NM_DBUS_INTERFACE_SETTINGS, bus);\n  nm_settings.setTimeout(DBUS_TIMEOUT);\n\n  nm_settings.call(\"AddConnection\", QVariant::fromValue(connection));\n}\n\nvoid WifiManager::deactivateConnection(const QString &ssid) {\n  for (QDBusObjectPath active_connection_raw : get_active_connections()) {\n    QString active_connection = active_connection_raw.path();\n    QDBusInterface nm(NM_DBUS_SERVICE, active_connection, NM_DBUS_INTERFACE_PROPERTIES, bus);\n    nm.setTimeout(DBUS_TIMEOUT);\n\n    QDBusObjectPath pth = get_response<QDBusObjectPath>(nm.call(\"Get\", NM_DBUS_INTERFACE_ACTIVE_CONNECTION, \"SpecificObject\"));\n    if (pth.path() != \"\" && pth.path() != \"/\") {\n      QString Ssid = get_property(pth.path(), \"Ssid\");\n      if (Ssid == ssid) {\n        QDBusInterface nm2(NM_DBUS_SERVICE, NM_DBUS_PATH, NM_DBUS_INTERFACE, bus);\n        nm2.setTimeout(DBUS_TIMEOUT);\n        nm2.call(\"DeactivateConnection\", QVariant::fromValue(active_connection_raw));\n      }\n    }\n  }\n}\n\nQVector<QDBusObjectPath> WifiManager::get_active_connections() {\n  QDBusInterface nm(NM_DBUS_SERVICE, NM_DBUS_PATH, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n\n  QDBusMessage response = nm.call(\"Get\", NM_DBUS_INTERFACE, \"ActiveConnections\");\n  const QDBusArgument &arr = get_response<QDBusArgument>(response);\n  QVector<QDBusObjectPath> conns;\n\n  QDBusObjectPath path;\n  arr.beginArray();\n  while (!arr.atEnd()) {\n    arr >> path;\n    conns.push_back(path);\n  }\n  arr.endArray();\n  return conns;\n}\n\nbool WifiManager::isKnownConnection(const QString &ssid) {\n  return !getConnectionPath(ssid).path().isEmpty();\n}\n\nvoid WifiManager::forgetConnection(const QString &ssid) {\n  const QDBusObjectPath &path = getConnectionPath(ssid);\n  if (!path.path().isEmpty()) {\n    QDBusInterface nm2(NM_DBUS_SERVICE, path.path(), NM_DBUS_INTERFACE_SETTINGS_CONNECTION, bus);\n    nm2.call(\"Delete\");\n  }\n}\n\nbool WifiManager::isWirelessAdapter(const QDBusObjectPath &path) {\n  QDBusInterface device_props(NM_DBUS_SERVICE, path.path(), NM_DBUS_INTERFACE_PROPERTIES, bus);\n  device_props.setTimeout(DBUS_TIMEOUT);\n  const uint deviceType = get_response<uint>(device_props.call(\"Get\", NM_DBUS_INTERFACE_DEVICE, \"DeviceType\"));\n  return deviceType == NM_DEVICE_TYPE_WIFI;\n}\n\nvoid WifiManager::requestScan() {\n  QDBusInterface nm(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_DEVICE_WIRELESS, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n  nm.call(\"RequestScan\", QVariantMap());\n}\n\nuint WifiManager::get_wifi_device_state() {\n  QDBusInterface device_props(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  device_props.setTimeout(DBUS_TIMEOUT);\n\n  QDBusMessage response = device_props.call(\"Get\", NM_DBUS_INTERFACE_DEVICE, \"State\");\n  uint resp = get_response<uint>(response);\n  return resp;\n}\n\nQByteArray WifiManager::get_property(const QString &network_path , const QString &property) {\n  QDBusInterface device_props(NM_DBUS_SERVICE, network_path, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  device_props.setTimeout(DBUS_TIMEOUT);\n\n  QDBusMessage response = device_props.call(\"Get\", NM_DBUS_INTERFACE_ACCESS_POINT, property);\n  return get_response<QByteArray>(response);\n}\n\nunsigned int WifiManager::get_ap_strength(const QString &network_path) {\n  QDBusInterface device_props(NM_DBUS_SERVICE, network_path, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  device_props.setTimeout(DBUS_TIMEOUT);\n\n  QDBusMessage response = device_props.call(\"Get\", NM_DBUS_INTERFACE_ACCESS_POINT, \"Strength\");\n  return get_response<unsigned int>(response);\n}\n\nQString WifiManager::getAdapter() {\n  QDBusInterface nm(NM_DBUS_SERVICE, NM_DBUS_PATH, NM_DBUS_INTERFACE, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n\n  const QDBusReply<QList<QDBusObjectPath>> &response = nm.call(\"GetDevices\");\n  for (const QDBusObjectPath &path : response.value()) {\n    if (isWirelessAdapter(path)) {\n      return path.path();\n    }\n  }\n  return \"\";\n}\n\nvoid WifiManager::stateChange(unsigned int new_state, unsigned int previous_state, unsigned int change_reason) {\n  raw_adapter_state = new_state;\n  if (new_state == NM_DEVICE_STATE_NEED_AUTH && change_reason == NM_DEVICE_STATE_REASON_SUPPLICANT_DISCONNECT && !connecting_to_network.isEmpty()) {\n    forgetConnection(connecting_to_network);\n    emit wrongPassword(connecting_to_network);\n  } else if (new_state == NM_DEVICE_STATE_ACTIVATED) {\n    connecting_to_network = \"\";\n    if (this->isVisible()) {\n      refreshNetworks();\n      emit refreshSignal();\n    }\n  }\n}\n\n// https://developer.gnome.org/NetworkManager/stable/gdbus-org.freedesktop.NetworkManager.Device.Wireless.html\nvoid WifiManager::propertyChange(const QString &interface, const QVariantMap &props, const QStringList &invalidated_props) {\n  if (interface == NM_DBUS_INTERFACE_DEVICE_WIRELESS && props.contains(\"LastScan\")) {\n    if (this->isVisible() || firstScan) {\n      refreshNetworks();\n      emit refreshSignal();\n      firstScan = false;\n    }\n  } else if (interface == NM_DBUS_INTERFACE_DEVICE_WIRELESS && props.contains(\"ActiveAccessPoint\")) {\n    const QDBusObjectPath &path = props.value(\"ActiveAccessPoint\").value<QDBusObjectPath>();\n    activeAp = path.path();\n  }\n}\n\nvoid WifiManager::deviceAdded(const QDBusObjectPath &path) {\n  if (isWirelessAdapter(path) && (adapter.isEmpty() || adapter == \"/\")) {\n    adapter = path.path();\n    setup();\n  }\n}\n\nvoid WifiManager::connectionRemoved(const QDBusObjectPath &path) {\n  knownConnections.remove(path);\n}\n\nvoid WifiManager::newConnection(const QDBusObjectPath &path) {\n  const Connection &settings = getConnectionSettings(path);\n  if (settings.value(\"connection\").value(\"type\") == \"802-11-wireless\") {\n    knownConnections[path] = settings.value(\"802-11-wireless\").value(\"ssid\").toString();\n    if (knownConnections[path] != tethering_ssid) {\n      activateWifiConnection(knownConnections[path]);\n    }\n  }\n}\n\nvoid WifiManager::disconnect() {\n  if (activeAp != \"\" && activeAp != \"/\") {\n    deactivateConnection(get_property(activeAp, \"Ssid\"));\n  }\n}\n\nQDBusObjectPath WifiManager::getConnectionPath(const QString &ssid) {\n  for (const QString &conn_ssid : knownConnections) {\n    if (ssid == conn_ssid) {\n      return knownConnections.key(conn_ssid);\n    }\n  }\n  return QDBusObjectPath();\n}\n\nConnection WifiManager::getConnectionSettings(const QDBusObjectPath &path) {\n  QDBusInterface nm(NM_DBUS_SERVICE, path.path(), NM_DBUS_INTERFACE_SETTINGS_CONNECTION, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n  return QDBusReply<Connection>(nm.call(\"GetSettings\")).value();\n}\n\nvoid WifiManager::initConnections() {\n  QDBusInterface nm(NM_DBUS_SERVICE, NM_DBUS_PATH_SETTINGS, NM_DBUS_INTERFACE_SETTINGS, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n\n  const QDBusReply<QList<QDBusObjectPath>> response = nm.call(\"ListConnections\");\n  for (const QDBusObjectPath &path : response.value()) {\n    const Connection &settings = getConnectionSettings(path);\n    if (settings.value(\"connection\").value(\"type\") == \"802-11-wireless\") {\n      knownConnections[path] = settings.value(\"802-11-wireless\").value(\"ssid\").toString();\n    } else if (path.path() != \"/\") {\n      lteConnectionPath = path.path();\n    }\n  }\n}\n\nvoid WifiManager::activateWifiConnection(const QString &ssid) {\n  const QDBusObjectPath &path = getConnectionPath(ssid);\n  if (!path.path().isEmpty()) {\n    connecting_to_network = ssid;\n    QDBusInterface nm3(NM_DBUS_SERVICE, NM_DBUS_PATH, NM_DBUS_INTERFACE, bus);\n    nm3.setTimeout(DBUS_TIMEOUT);\n    nm3.call(\"ActivateConnection\", QVariant::fromValue(path), QVariant::fromValue(QDBusObjectPath(adapter)), QVariant::fromValue(QDBusObjectPath(\"/\")));\n  }\n}\n\n// function matches tici/hardware.py\nNetworkType WifiManager::currentNetworkType() {\n  QDBusInterface nm(NM_DBUS_SERVICE, NM_DBUS_PATH, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n  const QDBusObjectPath &path = get_response<QDBusObjectPath>(nm.call(\"Get\", NM_DBUS_INTERFACE, \"PrimaryConnection\"));\n\n  QDBusInterface nm2(NM_DBUS_SERVICE, path.path(), NM_DBUS_INTERFACE_PROPERTIES, bus);\n  nm.setTimeout(DBUS_TIMEOUT);\n  const QString &type = get_response<QString>(nm2.call(\"Get\", NM_DBUS_INTERFACE_ACTIVE_CONNECTION, \"Type\"));\n\n  if (type == \"802-3-ethernet\") {\n    return NetworkType::ETHERNET;\n  } else if (type == \"802-11-wireless\" && !isTetheringEnabled()) {\n    return NetworkType::WIFI;\n  } else {\n    for (const QDBusObjectPath &path : get_active_connections()) {\n      QDBusInterface nm3(NM_DBUS_SERVICE, path.path(), NM_DBUS_INTERFACE_PROPERTIES, bus);\n      nm3.setTimeout(DBUS_TIMEOUT);\n      const QString &type = get_response<QString>(nm3.call(\"Get\", NM_DBUS_INTERFACE_ACTIVE_CONNECTION, \"Type\"));\n      if (type == \"gsm\") {\n        return NetworkType::CELL;\n      }\n    }\n  }\n  return NetworkType::NONE;\n}\n\nvoid WifiManager::setRoamingEnabled(bool roaming) {\n  if (!lteConnectionPath.isEmpty()) {\n    QDBusInterface nm(NM_DBUS_SERVICE, lteConnectionPath, NM_DBUS_INTERFACE_SETTINGS_CONNECTION, bus);\n    nm.setTimeout(DBUS_TIMEOUT);\n\n    Connection settings = QDBusReply<Connection>(nm.call(\"GetSettings\")).value();\n    if (settings.value(\"gsm\").value(\"home-only\").toBool() == roaming) {\n      settings[\"gsm\"][\"home-only\"] = !roaming;\n      nm.call(\"UpdateUnsaved\", QVariant::fromValue(settings));  // update is temporary\n    }\n  }\n}\n\n// Functions for tethering\nvoid WifiManager::addTetheringConnection() {\n  Connection connection;\n  connection[\"connection\"][\"id\"] = \"Hotspot\";\n  connection[\"connection\"][\"uuid\"] = QUuid::createUuid().toString().remove('{').remove('}');\n  connection[\"connection\"][\"type\"] = \"802-11-wireless\";\n  connection[\"connection\"][\"interface-name\"] = \"wlan0\";\n  connection[\"connection\"][\"autoconnect\"] = false;\n\n  connection[\"802-11-wireless\"][\"band\"] = \"bg\";\n  connection[\"802-11-wireless\"][\"mode\"] = \"ap\";\n  connection[\"802-11-wireless\"][\"ssid\"] = tethering_ssid.toUtf8();\n\n  connection[\"802-11-wireless-security\"][\"group\"] = QStringList(\"ccmp\");\n  connection[\"802-11-wireless-security\"][\"key-mgmt\"] = \"wpa-psk\";\n  connection[\"802-11-wireless-security\"][\"pairwise\"] = QStringList(\"ccmp\");\n  connection[\"802-11-wireless-security\"][\"proto\"] = QStringList(\"rsn\");\n  connection[\"802-11-wireless-security\"][\"psk\"] = defaultTetheringPassword;\n\n  connection[\"ipv4\"][\"method\"] = \"shared\";\n  QMap<QString,QVariant> address;\n  address[\"address\"] = \"192.168.43.1\";\n  address[\"prefix\"] = 24u;\n  connection[\"ipv4\"][\"address-data\"] = QVariant::fromValue(IpConfig() << address);\n  connection[\"ipv4\"][\"gateway\"] = \"192.168.43.1\";\n  connection[\"ipv4\"][\"route-metric\"] = 1100;\n  connection[\"ipv6\"][\"method\"] = \"ignore\";\n\n  QDBusInterface nm_settings(NM_DBUS_SERVICE, NM_DBUS_PATH_SETTINGS, NM_DBUS_INTERFACE_SETTINGS, bus);\n  nm_settings.setTimeout(DBUS_TIMEOUT);\n  nm_settings.call(\"AddConnection\", QVariant::fromValue(connection));\n}\n\nvoid WifiManager::setTetheringEnabled(bool enabled) {\n  if (enabled) {\n    if (!isKnownConnection(tethering_ssid)) {\n      addTetheringConnection();\n    }\n    activateWifiConnection(tethering_ssid);\n  } else {\n    deactivateConnection(tethering_ssid);\n  }\n}\n\nvoid WifiManager::initActiveAp() {\n  QDBusInterface device_props(NM_DBUS_SERVICE, adapter, NM_DBUS_INTERFACE_PROPERTIES, bus);\n  device_props.setTimeout(DBUS_TIMEOUT);\n\n  const QDBusMessage &response = device_props.call(\"Get\", NM_DBUS_INTERFACE_DEVICE_WIRELESS, \"ActiveAccessPoint\");\n  activeAp = get_response<QDBusObjectPath>(response).path();\n}\n\n\nbool WifiManager::isTetheringEnabled() {\n  if (activeAp != \"\" && activeAp != \"/\") {\n    return get_property(activeAp, \"Ssid\") == tethering_ssid;\n  }\n  return false;\n}\n\nQString WifiManager::getTetheringPassword() {\n  if (!isKnownConnection(tethering_ssid)) {\n    addTetheringConnection();\n  }\n  const QDBusObjectPath &path = getConnectionPath(tethering_ssid);\n  if (!path.path().isEmpty()) {\n    QDBusInterface nm(NM_DBUS_INTERFACE, path.path(), NM_DBUS_INTERFACE_SETTINGS_CONNECTION, bus);\n    nm.setTimeout(DBUS_TIMEOUT);\n\n    const QDBusReply<QMap<QString, QMap<QString, QVariant>>> response = nm.call(\"GetSecrets\", \"802-11-wireless-security\");\n    return response.value().value(\"802-11-wireless-security\").value(\"psk\").toString();\n  }\n  return \"\";\n}\n\nvoid WifiManager::changeTetheringPassword(const QString &newPassword) {\n  const QDBusObjectPath &path = getConnectionPath(tethering_ssid);\n  if (!path.path().isEmpty()) {\n    QDBusInterface nm(NM_DBUS_INTERFACE, path.path(), NM_DBUS_INTERFACE_SETTINGS_CONNECTION, bus);\n    nm.setTimeout(DBUS_TIMEOUT);\n\n    Connection settings = QDBusReply<Connection>(nm.call(\"GetSettings\")).value();\n    settings[\"802-11-wireless-security\"][\"psk\"] = newPassword;\n    nm.call(\"Update\", QVariant::fromValue(settings));\n\n    if (isTetheringEnabled()) {\n      activateWifiConnection(tethering_ssid);\n    }\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/offroad/wifiManager.h",
    "content": "#pragma once\n\n#include <QtDBus>\n#include <QWidget>\n\n#include \"selfdrive/ui/qt/offroad/networkmanager.h\"\n\nenum class SecurityType {\n  OPEN,\n  WPA,\n  UNSUPPORTED\n};\nenum class ConnectedType {\n  DISCONNECTED,\n  CONNECTING,\n  CONNECTED\n};\nenum class NetworkType {\n  NONE,\n  WIFI,\n  CELL,\n  ETHERNET\n};\n\ntypedef QMap<QString, QMap<QString, QVariant>> Connection;\ntypedef QVector<QMap<QString, QVariant>> IpConfig;\n\nstruct Network {\n  QByteArray ssid;\n  unsigned int strength;\n  ConnectedType connected;\n  SecurityType security_type;\n};\nbool compare_by_strength(const Network &a, const Network &b);\n\nclass WifiManager : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit WifiManager(QWidget* parent);\n\n  void requestScan();\n  QMap<QString, Network> seenNetworks;\n  QMap<QDBusObjectPath, QString> knownConnections;\n  QString lteConnectionPath;\n  QString ipv4_address;\n\n  void refreshNetworks();\n  void forgetConnection(const QString &ssid);\n  bool isKnownConnection(const QString &ssid);\n  void activateWifiConnection(const QString &ssid);\n  NetworkType currentNetworkType();\n  void setRoamingEnabled(bool roaming);\n\n  void connect(const Network &ssid);\n  void connect(const Network &ssid, const QString &password);\n  void connect(const Network &ssid, const QString &username, const QString &password);\n  void disconnect();\n\n  // Tethering functions\n  void setTetheringEnabled(bool enabled);\n  bool isTetheringEnabled();\n  void addTetheringConnection();\n  void changeTetheringPassword(const QString &newPassword);\n  QString getTetheringPassword();\n\nprivate:\n  QString adapter;  // Path to network manager wifi-device\n  QDBusConnection bus = QDBusConnection::systemBus();\n  unsigned int raw_adapter_state;  // Connection status https://developer.gnome.org/NetworkManager/1.26/nm-dbus-types.html#NMDeviceState\n  QString connecting_to_network;\n  QString tethering_ssid;\n  const QString defaultTetheringPassword = \"swagswagcomma\";\n\n  bool firstScan = true;\n  QString getAdapter();\n  bool isWirelessAdapter(const QDBusObjectPath &path);\n  QString get_ipv4_address();\n  void connect(const QByteArray &ssid, const QString &username, const QString &password, SecurityType security_type);\n  QString activeAp;\n  void initActiveAp();\n  void deactivateConnection(const QString &ssid);\n  QVector<QDBusObjectPath> get_active_connections();\n  uint get_wifi_device_state();\n  QByteArray get_property(const QString &network_path, const QString &property);\n  unsigned int get_ap_strength(const QString &network_path);\n  SecurityType getSecurityType(const QString &path);\n  QDBusObjectPath getConnectionPath(const QString &ssid);\n  Connection getConnectionSettings(const QDBusObjectPath &path);\n  void initConnections();\n  void setup();\n\nsignals:\n  void wrongPassword(const QString &ssid);\n  void refreshSignal();\n\nprivate slots:\n  void stateChange(unsigned int new_state, unsigned int previous_state, unsigned int change_reason);\n  void propertyChange(const QString &interface, const QVariantMap &props, const QStringList &invalidated_props);\n  void deviceAdded(const QDBusObjectPath &path);\n  void connectionRemoved(const QDBusObjectPath &path);\n  void newConnection(const QDBusObjectPath &path);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/onroad.cc",
    "content": "#include \"selfdrive/ui/qt/onroad.h\"\n\n#include <iostream>\n#include <QDebug>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/timing.h\"\n#include \"selfdrive/ui/paint.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#ifdef ENABLE_MAPS\n#include \"selfdrive/ui/qt/maps/map.h\"\n#endif\n\nOnroadWindow::OnroadWindow(QWidget *parent) : QWidget(parent) {\n  QVBoxLayout *main_layout  = new QVBoxLayout(this);\n  main_layout->setMargin(bdr_s);\n  QStackedLayout *stacked_layout = new QStackedLayout;\n  stacked_layout->setStackingMode(QStackedLayout::StackAll);\n  main_layout->addLayout(stacked_layout);\n\n  // old UI on bottom\n  nvg = new NvgWindow(this);\n  QObject::connect(this, &OnroadWindow::updateStateSignal, nvg, &NvgWindow::updateState);\n\n  QWidget * split_wrapper = new QWidget;\n  split = new QHBoxLayout(split_wrapper);\n  split->setContentsMargins(0, 0, 0, 0);\n  split->setSpacing(0);\n  split->addWidget(nvg);\n\n  stacked_layout->addWidget(split_wrapper);\n\n  alerts = new OnroadAlerts(this);\n  alerts->setAttribute(Qt::WA_TransparentForMouseEvents, true);\n  stacked_layout->addWidget(alerts);\n\n  // setup stacking order\n  alerts->raise();\n\n  setAttribute(Qt::WA_OpaquePaintEvent);\n  QObject::connect(this, &OnroadWindow::updateStateSignal, this, &OnroadWindow::updateState);\n  QObject::connect(this, &OnroadWindow::offroadTransitionSignal, this, &OnroadWindow::offroadTransition);\n}\n\nvoid OnroadWindow::updateState(const UIState &s) {\n  SubMaster &sm = *(s.sm);\n  QColor bgColor = bg_colors[s.status];\n  if (sm.updated(\"controlsState\")) {\n    const cereal::ControlsState::Reader &cs = sm[\"controlsState\"].getControlsState();\n    alerts->updateAlert({QString::fromStdString(cs.getAlertText1()),\n                 QString::fromStdString(cs.getAlertText2()),\n                 QString::fromStdString(cs.getAlertType()),\n                 cs.getAlertSize(), cs.getAlertSound()}, bgColor);\n  } else if ((sm.frame - s.scene.started_frame) > 5 * UI_FREQ) {\n    // Handle controls timeout\n    if (sm.rcv_frame(\"controlsState\") < s.scene.started_frame) {\n      // car is started, but controlsState hasn't been seen at all\n      alerts->updateAlert(CONTROLS_WAITING_ALERT, bgColor);\n    } else if ((nanos_since_boot() - sm.rcv_time(\"controlsState\")) / 1e9 > CONTROLS_TIMEOUT) {\n      // car is started, but controls is lagging or died\n      bgColor = bg_colors[STATUS_ALERT];\n      alerts->updateAlert(CONTROLS_UNRESPONSIVE_ALERT, bgColor);\n    }\n  }\n  if (bg != bgColor) {\n    // repaint border\n    bg = bgColor;\n    update();\n  }\n}\n\nvoid OnroadWindow::mousePressEvent(QMouseEvent* e) {\n  if (map != nullptr) {\n    bool sidebarVisible = geometry().x() > 0;\n    map->setVisible(!sidebarVisible && !map->isVisible());\n  }\n  // propagation event to parent(HomeWindow)\n  QWidget::mousePressEvent(e);\n}\n\nvoid OnroadWindow::offroadTransition(bool offroad) {\n#ifdef ENABLE_MAPS\n  if (!offroad) {\n    QString token = QString::fromStdString(Params().get(\"MapboxToken\"));\n    if (map == nullptr && !token.isEmpty()) {\n      QMapboxGLSettings settings;\n      if (!Hardware::PC() && !Hardware::JETSON()) {\n        settings.setCacheDatabasePath(\"/data/mbgl-cache.db\");\n      }\n      settings.setCacheDatabaseMaximumSize(20 * 1024 * 1024);\n      settings.setAccessToken(token.trimmed());\n\n      MapWindow * m = new MapWindow(settings);\n      m->setFixedWidth(width() / 2 - bdr_s);\n      QObject::connect(this, &OnroadWindow::offroadTransitionSignal, m, &MapWindow::offroadTransition);\n      split->addWidget(m, 0, Qt::AlignRight);\n      map = m;\n    }\n  }\n#endif\n\n  alerts->updateAlert({}, bg);\n}\n\nvoid OnroadWindow::paintEvent(QPaintEvent *event) {\n  QPainter p(this);\n  p.fillRect(rect(), QColor(bg.red(), bg.green(), bg.blue(), 255));\n}\n\n// ***** onroad widgets *****\n\nvoid OnroadAlerts::updateAlert(const Alert &a, const QColor &color) {\n  if (!alert.equal(a) || color != bg) {\n    alert = a;\n    bg = color;\n    update();\n  }\n}\n\nvoid OnroadAlerts::paintEvent(QPaintEvent *event) {\n  if (alert.size == cereal::ControlsState::AlertSize::NONE) {\n    return;\n  }\n  static std::map<cereal::ControlsState::AlertSize, const int> alert_sizes = {\n    {cereal::ControlsState::AlertSize::SMALL, 271},\n    {cereal::ControlsState::AlertSize::MID, 420},\n    {cereal::ControlsState::AlertSize::FULL, height()},\n  };\n  int h = alert_sizes[alert.size];\n  QRect r = QRect(0, height() - h, width(), h);\n\n  QPainter p(this);\n\n  // draw background + gradient\n  p.setPen(Qt::NoPen);\n  p.setCompositionMode(QPainter::CompositionMode_SourceOver);\n\n  p.setBrush(QBrush(bg));\n  p.drawRect(r);\n\n  QLinearGradient g(0, r.y(), 0, r.bottom());\n  g.setColorAt(0, QColor::fromRgbF(0, 0, 0, 0.05));\n  g.setColorAt(1, QColor::fromRgbF(0, 0, 0, 0.35));\n\n  p.setCompositionMode(QPainter::CompositionMode_DestinationOver);\n  p.setBrush(QBrush(g));\n  p.fillRect(r, g);\n  p.setCompositionMode(QPainter::CompositionMode_SourceOver);\n\n  // text\n  const QPoint c = r.center();\n  p.setPen(QColor(0xff, 0xff, 0xff));\n  p.setRenderHint(QPainter::TextAntialiasing);\n  if (alert.size == cereal::ControlsState::AlertSize::SMALL) {\n    configFont(p, \"Open Sans\", 74, \"SemiBold\");\n    p.drawText(r, Qt::AlignCenter, alert.text1);\n  } else if (alert.size == cereal::ControlsState::AlertSize::MID) {\n    configFont(p, \"Open Sans\", 88, \"Bold\");\n    p.drawText(QRect(0, c.y() - 125, width(), 150), Qt::AlignHCenter | Qt::AlignTop, alert.text1);\n    configFont(p, \"Open Sans\", 66, \"Regular\");\n    p.drawText(QRect(0, c.y() + 21, width(), 90), Qt::AlignHCenter, alert.text2);\n  } else if (alert.size == cereal::ControlsState::AlertSize::FULL) {\n    bool l = alert.text1.length() > 15;\n    configFont(p, \"Open Sans\", l ? 132 : 177, \"Bold\");\n    p.drawText(QRect(0, r.y() + (l ? 240 : 270), width(), 600), Qt::AlignHCenter | Qt::TextWordWrap, alert.text1);\n    configFont(p, \"Open Sans\", 88, \"Regular\");\n    p.drawText(QRect(0, r.height() - (l ? 361 : 420), width(), 300), Qt::AlignHCenter | Qt::TextWordWrap, alert.text2);\n  }\n}\n\n\nNvgWindow::NvgWindow(QWidget *parent) : QOpenGLWidget(parent) {\n  setAttribute(Qt::WA_OpaquePaintEvent);\n}\n\nNvgWindow::~NvgWindow() {\n  makeCurrent();\n  doneCurrent();\n}\n\nvoid NvgWindow::initializeGL() {\n  initializeOpenGLFunctions();\n  qInfo() << \"OpenGL version:\" << QString((const char*)glGetString(GL_VERSION));\n  qInfo() << \"OpenGL vendor:\" << QString((const char*)glGetString(GL_VENDOR));\n  qInfo() << \"OpenGL renderer:\" << QString((const char*)glGetString(GL_RENDERER));\n  qInfo() << \"OpenGL language version:\" << QString((const char*)glGetString(GL_SHADING_LANGUAGE_VERSION));\n\n  ui_nvg_init(&QUIState::ui_state);\n  prev_draw_t = millis_since_boot();\n}\n\nvoid NvgWindow::updateState(const UIState &s) {\n  // Connecting to visionIPC requires opengl to be current\n  if (s.vipc_client->connected) {\n    makeCurrent();\n  }\n  if (isVisible() != s.vipc_client->connected) {\n    setVisible(s.vipc_client->connected);\n  }\n  repaint();\n}\n\nvoid NvgWindow::resizeGL(int w, int h) {\n  ui_resize(&QUIState::ui_state, w, h);\n}\n\nvoid NvgWindow::paintGL() {\n  ui_draw(&QUIState::ui_state, width(), height());\n\n  double cur_draw_t = millis_since_boot();\n  double dt = cur_draw_t - prev_draw_t;\n  if (dt > 66) {\n    // warn on sub 15fps\n    LOGW(\"slow frame time: %.2f\", dt);\n  }\n  prev_draw_t = cur_draw_t;\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/onroad.h",
    "content": "#pragma once\n\n#include <QOpenGLFunctions>\n#include <QOpenGLWidget>\n#include <QStackedLayout>\n#include <QWidget>\n\n#include \"cereal/gen/cpp/log.capnp.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/ui.h\"\n\n\n// ***** onroad widgets *****\n\nclass OnroadAlerts : public QWidget {\n  Q_OBJECT\n\npublic:\n  OnroadAlerts(QWidget *parent = 0) : QWidget(parent) {};\n  void updateAlert(const Alert &a, const QColor &color);\n\nprotected:\n  void paintEvent(QPaintEvent*) override;\n\nprivate:\n  QColor bg;\n  Alert alert = {};\n};\n\n// container window for the NVG UI\nclass NvgWindow : public QOpenGLWidget, protected QOpenGLFunctions {\n  Q_OBJECT\n\npublic:\n  using QOpenGLWidget::QOpenGLWidget;\n  explicit NvgWindow(QWidget* parent = 0);\n  ~NvgWindow();\n\nprotected:\n  void paintGL() override;\n  void initializeGL() override;\n  void resizeGL(int w, int h) override;\n\nprivate:\n  double prev_draw_t = 0;\n\npublic slots:\n  void updateState(const UIState &s);\n};\n\n// container for all onroad widgets\nclass OnroadWindow : public QWidget {\n  Q_OBJECT\n\npublic:\n  OnroadWindow(QWidget* parent = 0);\n  bool isMapVisible() const { return map && map->isVisible(); }\n\nprivate:\n  void paintEvent(QPaintEvent *event);\n  void mousePressEvent(QMouseEvent* e) override;\n  OnroadAlerts *alerts;\n  NvgWindow *nvg;\n  QColor bg = bg_colors[STATUS_DISENGAGED];\n  QWidget *map = nullptr;\n  QHBoxLayout* split;\n\nsignals:\n  void updateStateSignal(const UIState &s);\n  void offroadTransitionSignal(bool offroad);\n\nprivate slots:\n  void offroadTransition(bool offroad);\n  void updateState(const UIState &s);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/qt_window.h",
    "content": "#pragma once\n\n#include <string>\n\n#include <QApplication>\n#include <QWidget>\n\n#ifdef QCOM2\n#include <qpa/qplatformnativeinterface.h>\n#include <wayland-client-protocol.h>\n#include <QPlatformSurfaceEvent>\n#endif\n\n#include \"selfdrive/hardware/hw.h\"\n\nconst QString ASSET_PATH = \":/\";\n\nconst bool WIDE_UI = Hardware::TICI() || getenv(\"WIDE_UI\") != nullptr;\nconst int vwp_w = WIDE_UI ? 2160 : 1920;\nconst int vwp_h = 1080;\n\ninline void setMainWindow(QWidget *w) {\n  const float scale = util::getenv(\"SCALE\", 1.0f);\n  w->setFixedSize(vwp_w*scale, vwp_h*scale);\n#ifdef XNX\n  w->showFullScreen();\n#else\n  w->show();\n#endif\n\n#ifdef QCOM2\n  QPlatformNativeInterface *native = QGuiApplication::platformNativeInterface();\n  wl_surface *s = reinterpret_cast<wl_surface*>(native->nativeResourceForWindow(\"surface\", w->windowHandle()));\n  wl_surface_set_buffer_transform(s, WL_OUTPUT_TRANSFORM_270);\n  wl_surface_commit(s);\n  w->showFullScreen();\n#endif\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/request_repeater.cc",
    "content": "#include \"selfdrive/ui/qt/request_repeater.h\"\n\nRequestRepeater::RequestRepeater(QObject *parent, const QString &requestURL, const QString &cacheKey,\n                                 int period, bool while_onroad) : HttpRequest(parent) {\n  timer = new QTimer(this);\n  timer->setTimerType(Qt::VeryCoarseTimer);\n  QObject::connect(timer, &QTimer::timeout, [=]() {\n    if ((!QUIState::ui_state.scene.started || while_onroad) && QUIState::ui_state.awake && !active()) {\n      sendRequest(requestURL);\n    }\n  });\n\n  timer->start(period * 1000);\n\n  if (!cacheKey.isEmpty()) {\n    prevResp = QString::fromStdString(params.get(cacheKey.toStdString()));\n    if (!prevResp.isEmpty()) {\n      QTimer::singleShot(500, [=]() { emit receivedResponse(prevResp); });\n    }\n    QObject::connect(this, &HttpRequest::receivedResponse, [=](const QString &resp) {\n      if (resp != prevResp) {\n        params.put(cacheKey.toStdString(), resp.toStdString());\n        prevResp = resp;\n      }\n    });\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/request_repeater.h",
    "content": "#pragma once\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/ui/qt/api.h\"\n#include \"selfdrive/ui/ui.h\"\n\nclass RequestRepeater : public HttpRequest {\npublic:\n  RequestRepeater(QObject *parent, const QString &requestURL, const QString &cacheKey = \"\", int period = 0, bool while_onroad=false);\n\nprivate:\n  Params params;\n  QTimer *timer;\n  QString prevResp;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/sidebar.cc",
    "content": "#include \"selfdrive/ui/qt/sidebar.h\"\n\n#include <QMouseEvent>\n\n#include \"selfdrive/ui/qt/util.h\"\n\nvoid Sidebar::drawMetric(QPainter &p, const QString &label, QColor c, int y) {\n  const QRect rect = {30, y, 240, label.contains(\"\\n\") ? 124 : 100};\n\n  p.setPen(Qt::NoPen);\n  p.setBrush(QBrush(c));\n  p.setClipRect(rect.x() + 6, rect.y(), 18, rect.height(), Qt::ClipOperation::ReplaceClip);\n  p.drawRoundedRect(QRect(rect.x() + 6, rect.y() + 6, 100, rect.height() - 12), 10, 10);\n  p.setClipping(false);\n\n  QPen pen = QPen(QColor(0xff, 0xff, 0xff, 0x55));\n  pen.setWidth(2);\n  p.setPen(pen);\n  p.setBrush(Qt::NoBrush);\n  p.drawRoundedRect(rect, 20, 20);\n\n  p.setPen(QColor(0xff, 0xff, 0xff));\n  configFont(p, \"Open Sans\", 35, \"Bold\");\n  const QRect r = QRect(rect.x() + 30, rect.y(), rect.width() - 40, rect.height());\n  p.drawText(r, Qt::AlignCenter, label);\n}\n\nSidebar::Sidebar(QWidget *parent) : QFrame(parent) {\n  home_img = QImage(\"../assets/images/button_home.png\").scaled(180, 180, Qt::KeepAspectRatio, Qt::SmoothTransformation);\n  settings_img = QImage(\"../assets/images/button_settings.png\").scaled(settings_btn.width(), settings_btn.height(), Qt::IgnoreAspectRatio, Qt::SmoothTransformation);\n\n  connect(this, &Sidebar::valueChanged, [=] { update(); });\n\n  setAttribute(Qt::WA_OpaquePaintEvent);\n  setSizePolicy(QSizePolicy::Fixed, QSizePolicy::Expanding);\n  setFixedWidth(300);\n}\n\nvoid Sidebar::mouseReleaseEvent(QMouseEvent *event) {\n  if (settings_btn.contains(event->pos())) {\n    emit openSettings();\n  }\n}\n\nvoid Sidebar::updateState(const UIState &s) {\n  auto &sm = *(s.sm);\n\n  auto deviceState = sm[\"deviceState\"].getDeviceState();\n  setProperty(\"netType\", network_type[deviceState.getNetworkType()]);\n  int strength = (int)deviceState.getNetworkStrength();\n  setProperty(\"netStrength\", strength > 0 ? strength + 1 : 0);\n\n  ItemStatus connectStatus;\n  auto last_ping = deviceState.getLastAthenaPingTime();\n  if (last_ping == 0) {\n    connectStatus = params.getBool(\"PrimeRedirected\") ? ItemStatus{\"NO\\nPRIME\", danger_color} : ItemStatus{\"CONNECT\\nOFFLINE\", warning_color};\n  } else {\n    connectStatus = nanos_since_boot() - last_ping < 80e9 ? ItemStatus{\"CONNECT\\nONLINE\", good_color} : ItemStatus{\"CONNECT\\nERROR\", danger_color};\n  }\n  setProperty(\"connectStatus\", QVariant::fromValue(connectStatus));\n\n  ItemStatus tempStatus = {\"HIGH\\nTEMP\", danger_color};\n  auto ts = deviceState.getThermalStatus();\n  if (ts == cereal::DeviceState::ThermalStatus::GREEN) {\n    tempStatus = {\"GOOD\\nTEMP\", good_color};\n  } else if (ts == cereal::DeviceState::ThermalStatus::YELLOW) {\n    tempStatus = {\"OK\\nTEMP\", warning_color};\n  }\n  setProperty(\"tempStatus\", QVariant::fromValue(tempStatus));\n\n  ItemStatus pandaStatus = {\"VEHICLE\\nONLINE\", good_color};\n  if (s.scene.pandaType == cereal::PandaState::PandaType::UNKNOWN) {\n    pandaStatus = {\"NO\\nPANDA\", danger_color};\n  } else if (s.scene.started && !sm[\"liveLocationKalman\"].getLiveLocationKalman().getGpsOK()) {\n    pandaStatus = {\"GPS\\nSEARCHING\", warning_color};\n  }\n  setProperty(\"pandaStatus\", QVariant::fromValue(pandaStatus));\n}\n\nvoid Sidebar::paintEvent(QPaintEvent *event) {\n  QPainter p(this);\n  p.setPen(Qt::NoPen);\n  p.setRenderHint(QPainter::Antialiasing);\n\n  p.fillRect(rect(), QColor(57, 57, 57));\n\n  // static imgs\n  p.setOpacity(0.65);\n  p.drawImage(settings_btn.x(), settings_btn.y(), settings_img);\n  p.setOpacity(1.0);\n  p.drawImage(60, 1080 - 180 - 40, home_img);\n\n  // network\n  int x = 58;\n  const QColor gray(0x54, 0x54, 0x54);\n  for (int i = 0; i < 5; ++i) {\n    p.setBrush(i < net_strength ? Qt::white : gray);\n    p.drawEllipse(x, 196, 27, 27);\n    x += 37;\n  }\n\n  configFont(p, \"Open Sans\", 35, \"Regular\");\n  p.setPen(QColor(0xff, 0xff, 0xff));\n  const QRect r = QRect(50, 247, 100, 50);\n  p.drawText(r, Qt::AlignCenter, net_type);\n\n  // metrics\n  drawMetric(p, temp_status.first, temp_status.second, 338);\n  drawMetric(p, panda_status.first, panda_status.second, 496);\n  drawMetric(p, connect_status.first, connect_status.second, 654);\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/sidebar.h",
    "content": "#pragma once\n\n#include <QFrame>\n#include <QMap>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/ui.h\"\n\ntypedef QPair<QString, QColor> ItemStatus;\nQ_DECLARE_METATYPE(ItemStatus);\n\nclass Sidebar : public QFrame {\n  Q_OBJECT\n  Q_PROPERTY(ItemStatus connectStatus MEMBER connect_status NOTIFY valueChanged);\n  Q_PROPERTY(ItemStatus pandaStatus MEMBER panda_status NOTIFY valueChanged);\n  Q_PROPERTY(ItemStatus tempStatus MEMBER temp_status NOTIFY valueChanged);\n  Q_PROPERTY(QString netType MEMBER net_type NOTIFY valueChanged);\n  Q_PROPERTY(int netStrength MEMBER net_strength NOTIFY valueChanged);\n\npublic:\n  explicit Sidebar(QWidget* parent = 0);\n\nsignals:\n  void openSettings();\n  void valueChanged();\n\npublic slots:\n  void updateState(const UIState &s);\n\nprotected:\n  void paintEvent(QPaintEvent *event) override;\n  void mouseReleaseEvent(QMouseEvent *event) override;\n  void drawMetric(QPainter &p, const QString &label, QColor c, int y);\n\n  QImage home_img, settings_img;\n  const QMap<cereal::DeviceState::NetworkType, QString> network_type = {\n    {cereal::DeviceState::NetworkType::NONE, \"--\"},\n    {cereal::DeviceState::NetworkType::WIFI, \"WiFi\"},\n    {cereal::DeviceState::NetworkType::ETHERNET, \"ETH\"},\n    {cereal::DeviceState::NetworkType::CELL2_G, \"2G\"},\n    {cereal::DeviceState::NetworkType::CELL3_G, \"3G\"},\n    {cereal::DeviceState::NetworkType::CELL4_G, \"LTE\"},\n    {cereal::DeviceState::NetworkType::CELL5_G, \"5G\"}\n  };\n\n  const QRect settings_btn = QRect(50, 35, 200, 117);\n  const QColor good_color = QColor(255, 255, 255);\n  const QColor warning_color = QColor(218, 202, 37);\n  const QColor danger_color = QColor(201, 34, 49);\n\n  Params params;\n  ItemStatus connect_status, panda_status, temp_status;\n  QString net_type;\n  int net_strength = 0;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/spinner.cc",
    "content": "#include \"selfdrive/ui/qt/spinner.h\"\n\n#include <cstdio>\n#include <iostream>\n#include <string>\n\n#include <QApplication>\n#include <QGridLayout>\n#include <QPainter>\n#include <QString>\n#include <QTransform>\n\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/util.h\"\n\nTrackWidget::TrackWidget(QWidget *parent) : QWidget(parent) {\n  setAttribute(Qt::WA_OpaquePaintEvent);\n  setFixedSize(spinner_size);\n\n  // pre-compute all the track imgs. make this a gif instead?\n  QPixmap comma_img = QPixmap(\"../assets/img_spinner_comma.png\").scaled(spinner_size, Qt::KeepAspectRatio, Qt::SmoothTransformation);\n  QPixmap track_img = QPixmap(\"../assets/img_spinner_track.png\").scaled(spinner_size, Qt::KeepAspectRatio, Qt::SmoothTransformation);\n\n  QTransform transform(1, 0, 0, 1, width() / 2, height() / 2);\n  QPixmap pm(spinner_size);\n  QPainter p(&pm);\n  p.setRenderHint(QPainter::SmoothPixmapTransform);\n  for (int i = 0; i < track_imgs.size(); ++i) {\n    p.resetTransform();\n    p.fillRect(0, 0, spinner_size.width(), spinner_size.height(), Qt::black);\n    p.drawPixmap(0, 0, comma_img);\n    p.setTransform(transform.rotate(360 / spinner_fps));\n    p.drawPixmap(-width() / 2, -height() / 2, track_img);\n    track_imgs[i] = pm.copy();\n  }\n\n  m_anim.setDuration(1000);\n  m_anim.setStartValue(0);\n  m_anim.setEndValue(int(track_imgs.size() -1));\n  m_anim.setLoopCount(-1);\n  m_anim.start();\n  connect(&m_anim, SIGNAL(valueChanged(QVariant)), SLOT(update()));\n}\n\nvoid TrackWidget::paintEvent(QPaintEvent *event) {\n  QPainter painter(this);\n  painter.drawPixmap(0, 0, track_imgs[m_anim.currentValue().toInt()]);\n}\n\n// Spinner\n\nSpinner::Spinner(QWidget *parent) : QWidget(parent) {\n  QGridLayout *main_layout = new QGridLayout(this);\n  main_layout->setSpacing(0);\n  main_layout->setMargin(200);\n\n  main_layout->addWidget(new TrackWidget(this), 0, 0, Qt::AlignHCenter | Qt::AlignVCenter);\n\n  text = new QLabel();\n  text->setWordWrap(true);\n  text->setVisible(false);\n  text->setAlignment(Qt::AlignCenter);\n  main_layout->addWidget(text, 1, 0, Qt::AlignHCenter);\n\n  progress_bar = new QProgressBar();\n  progress_bar->setRange(5, 100);\n  progress_bar->setTextVisible(false);\n  progress_bar->setVisible(false);\n  progress_bar->setFixedHeight(20);\n  main_layout->addWidget(progress_bar, 1, 0, Qt::AlignHCenter);\n\n  setStyleSheet(R\"(\n    Spinner {\n      background-color: black;\n    }\n    QLabel {\n      color: white;\n      font-size: 80px;\n      background-color: transparent;\n    }\n    QProgressBar {\n      background-color: #373737;\n      width: 1000px;\n      border solid white;\n      border-radius: 10px;\n    }\n    QProgressBar::chunk {\n      border-radius: 10px;\n      background-color: white;\n    }\n  )\");\n\n  notifier = new QSocketNotifier(fileno(stdin), QSocketNotifier::Read);\n  QObject::connect(notifier, &QSocketNotifier::activated, this, &Spinner::update);\n};\n\nvoid Spinner::update(int n) {\n  std::string line;\n  std::getline(std::cin, line);\n\n  if (line.length()) {\n    bool number = std::all_of(line.begin(), line.end(), ::isdigit);\n    text->setVisible(!number);\n    progress_bar->setVisible(number);\n    text->setText(QString::fromStdString(line));\n    if (number) {\n      progress_bar->setValue(std::stoi(line));\n    }\n  }\n}\n\nint main(int argc, char *argv[]) {\n  initApp();\n  QApplication a(argc, argv);\n  Spinner spinner;\n  setMainWindow(&spinner);\n  return a.exec();\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/spinner.h",
    "content": "#include <array>\n\n#include <QLabel>\n#include <QPixmap>\n#include <QProgressBar>\n#include <QSocketNotifier>\n#include <QVariantAnimation>\n#include <QWidget>\n\nconstexpr int spinner_fps = 30;\nconstexpr QSize spinner_size = QSize(360, 360);\n\nclass TrackWidget : public QWidget  {\n  Q_OBJECT\npublic:\n  TrackWidget(QWidget *parent = nullptr);\n\nprivate:\n  void paintEvent(QPaintEvent *event) override;\n  std::array<QPixmap, spinner_fps> track_imgs;\n  QVariantAnimation m_anim;\n};\n\nclass Spinner : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit Spinner(QWidget *parent = 0);\n\nprivate:\n  QLabel *text;\n  QProgressBar *progress_bar;\n  QSocketNotifier *notifier;\n\npublic slots:\n  void update(int n);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/text.cc",
    "content": "#include <QApplication>\n#include <QLabel>\n#include <QPushButton>\n#include <QScrollBar>\n#include <QVBoxLayout>\n#include <QWidget>\n\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n\nint main(int argc, char *argv[]) {\n  initApp();\n  QApplication a(argc, argv);\n  QWidget window;\n  setMainWindow(&window);\n\n  QGridLayout *main_layout = new QGridLayout(&window);\n  main_layout->setMargin(50);\n\n  QLabel *label = new QLabel(argv[1]);\n  label->setWordWrap(true);\n  label->setSizePolicy(QSizePolicy::Preferred, QSizePolicy::MinimumExpanding);\n  ScrollView *scroll = new ScrollView(label);\n  scroll->setVerticalScrollBarPolicy(Qt::ScrollBarAsNeeded);\n  main_layout->addWidget(scroll, 0, 0, Qt::AlignTop);\n\n  // Scroll to the bottom\n  QObject::connect(scroll->verticalScrollBar(), &QAbstractSlider::rangeChanged, [=]() {\n    scroll->verticalScrollBar()->setValue(scroll->verticalScrollBar()->maximum());\n  });\n\n  QPushButton *btn = new QPushButton();\n#ifdef __aarch64__\n  btn->setText(\"Reboot\");\n  QObject::connect(btn, &QPushButton::clicked, [=]() {\n    Hardware::reboot();\n  });\n#else\n  btn->setText(\"Exit\");\n  QObject::connect(btn, &QPushButton::clicked, &a, &QApplication::quit);\n#endif\n  main_layout->addWidget(btn, 0, 0, Qt::AlignRight | Qt::AlignBottom);\n\n  window.setStyleSheet(R\"(\n    * {\n      outline: none;\n      color: white;\n      background-color: black;\n      font-size: 60px;\n    }\n    QPushButton {\n      padding: 50px;\n      padding-right: 100px;\n      padding-left: 100px;\n      border: 2px solid white;\n      border-radius: 20px;\n      margin-right: 40px;\n    }\n  )\");\n\n  return a.exec();\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/util.cc",
    "content": "#include \"selfdrive/ui/qt/util.h\"\n\n#include <QApplication>\n#include <QLayoutItem>\n#include <QStyleOption>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/hardware/hw.h\"\n\nQString getBrand() {\n  return Params().getBool(\"Passive\") ? \"dashcam\" : \"openpilot\";\n}\n\nQString getBrandVersion() {\n  return getBrand() + \" v\" + QString::fromStdString(Params().get(\"Version\")).left(14).trimmed();\n}\n\nstd::optional<QString> getDongleId() {\n  std::string id = Params().get(\"DongleId\");\n\n  if (!id.empty() && (id != \"UnregisteredDevice\")) {\n    return QString::fromStdString(id);\n  } else {\n    return {};\n  }\n}\n\nvoid configFont(QPainter &p, const QString &family, int size, const QString &style) {\n  QFont f(family);\n  f.setPixelSize(size);\n  f.setStyleName(style);\n  p.setFont(f);\n}\n\nvoid clearLayout(QLayout* layout) {\n  while (QLayoutItem* item = layout->takeAt(0)) {\n    if (QWidget* widget = item->widget()) {\n      widget->deleteLater();\n    }\n    if (QLayout* childLayout = item->layout()) {\n      clearLayout(childLayout);\n    }\n    delete item;\n  }\n}\n\nQString timeAgo(const QDateTime &date) {\n  int diff = date.secsTo(QDateTime::currentDateTimeUtc());\n\n  QString s;\n  if (diff < 60) {\n    s = \"now\";\n  } else if (diff < 60 * 60) {\n    int minutes = diff / 60;\n    s = QString(\"%1 minute%2 ago\").arg(minutes).arg(minutes > 1 ? \"s\" : \"\");\n  } else if (diff < 60 * 60 * 24) {\n    int hours = diff / (60 * 60);\n    s = QString(\"%1 hour%2 ago\").arg(hours).arg(hours > 1 ? \"s\" : \"\");\n  } else if (diff < 3600 * 24 * 7) {\n    int days = diff / (60 * 60 * 24);\n    s = QString(\"%1 day%2 ago\").arg(days).arg(days > 1 ? \"s\" : \"\");\n  } else {\n    s = date.date().toString();\n  }\n\n  return s;\n}\n\nvoid setQtSurfaceFormat() {\n  QSurfaceFormat fmt;\n#ifdef __APPLE__\n  fmt.setVersion(3, 2);\n  fmt.setProfile(QSurfaceFormat::OpenGLContextProfile::CoreProfile);\n  fmt.setRenderableType(QSurfaceFormat::OpenGL);\n#else\n  fmt.setRenderableType(QSurfaceFormat::OpenGLES);\n#endif\n  QSurfaceFormat::setDefaultFormat(fmt);\n}\n\nvoid initApp() {\n  Hardware::set_display_power(true);\n  Hardware::set_brightness(65);\n  setQtSurfaceFormat();\n  if (Hardware::EON()) {\n    QApplication::setAttribute(Qt::AA_ShareOpenGLContexts);\n  }\n}\n\nClickableWidget::ClickableWidget(QWidget *parent) : QWidget(parent) { }\n\nvoid ClickableWidget::mouseReleaseEvent(QMouseEvent *event) {\n  emit clicked();\n}\n\n// Fix stylesheets\nvoid ClickableWidget::paintEvent(QPaintEvent *) {\n  QStyleOption opt;\n  opt.init(this);\n  QPainter p(this);\n  style()->drawPrimitive(QStyle::PE_Widget, &opt, &p, this);\n}\n\n\nvoid swagLogMessageHandler(QtMsgType type, const QMessageLogContext &context, const QString &msg) {\n  static std::map<QtMsgType, int> levels = {\n    {QtMsgType::QtDebugMsg, CLOUDLOG_DEBUG},\n    {QtMsgType::QtInfoMsg, CLOUDLOG_INFO},\n    {QtMsgType::QtWarningMsg, CLOUDLOG_WARNING},\n    {QtMsgType::QtCriticalMsg, CLOUDLOG_ERROR},\n    {QtMsgType::QtSystemMsg, CLOUDLOG_ERROR},\n    {QtMsgType::QtFatalMsg, CLOUDLOG_CRITICAL},\n  };\n\n  std::string file, function;\n  if (context.file != nullptr) file = context.file;\n  if (context.function != nullptr) function = context.function;\n\n  auto bts = msg.toUtf8();\n  cloudlog_e(levels[type], file.c_str(), context.line, function.c_str(), \"%s\", bts.constData());\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/util.h",
    "content": "#pragma once\n\n#include <optional>\n\n#include <QDateTime>\n#include <QLayout>\n#include <QMouseEvent>\n#include <QPainter>\n#include <QSurfaceFormat>\n#include <QWidget>\n\nQString getBrand();\nQString getBrandVersion();\nstd::optional<QString> getDongleId();\nvoid configFont(QPainter &p, const QString &family, int size, const QString &style);\nvoid clearLayout(QLayout* layout);\nvoid setQtSurfaceFormat();\nQString timeAgo(const QDateTime &date);\nvoid swagLogMessageHandler(QtMsgType type, const QMessageLogContext &context, const QString &msg);\nvoid initApp();\n\n\n// convenience class for wrapping layouts\nclass LayoutWidget : public QWidget {\n  Q_OBJECT\n\npublic:\n  LayoutWidget(QLayout *l, QWidget *parent = nullptr) : QWidget(parent) {\n    setLayout(l);\n  };\n};\n\nclass ClickableWidget : public QWidget {\n  Q_OBJECT\n\npublic:\n  ClickableWidget(QWidget *parent = nullptr);\n\nprotected:\n  void mouseReleaseEvent(QMouseEvent *event) override;\n  void paintEvent(QPaintEvent *) override;\n\nsignals:\n  void clicked();\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/cameraview.cc",
    "content": "#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/widgets/cameraview.h\"\n\nnamespace {\n\nconst char frame_vertex_shader[] =\n#ifdef NANOVG_GL3_IMPLEMENTATION\n  \"#version 150 core\\n\"\n#else\n  \"#version 300 es\\n\"\n#endif\n  \"in vec4 aPosition;\\n\"\n  \"in vec4 aTexCoord;\\n\"\n  \"uniform mat4 uTransform;\\n\"\n  \"out vec4 vTexCoord;\\n\"\n  \"void main() {\\n\"\n  \"  gl_Position = uTransform * aPosition;\\n\"\n  \"  vTexCoord = aTexCoord;\\n\"\n  \"}\\n\";\n\nconst char frame_fragment_shader[] =\n#ifdef NANOVG_GL3_IMPLEMENTATION\n  \"#version 150 core\\n\"\n#else\n  \"#version 300 es\\n\"\n#endif\n  \"precision mediump float;\\n\"\n  \"uniform sampler2D uTexture;\\n\"\n  \"in vec4 vTexCoord;\\n\"\n  \"out vec4 colorOut;\\n\"\n  \"void main() {\\n\"\n  \"  colorOut = texture(uTexture, vTexCoord.xy);\\n\"\n#ifdef QCOM\n  \"  vec3 dz = vec3(0.0627f, 0.0627f, 0.0627f);\\n\"\n  \"  colorOut.rgb = ((vec3(1.0f, 1.0f, 1.0f) - dz) * colorOut.rgb / vec3(1.0f, 1.0f, 1.0f)) + dz;\\n\"\n#endif\n  \"}\\n\";\n\nconst mat4 device_transform = {{\n  1.0,  0.0, 0.0, 0.0,\n  0.0,  1.0, 0.0, 0.0,\n  0.0,  0.0, 1.0, 0.0,\n  0.0,  0.0, 0.0, 1.0,\n}};\n\nmat4 get_driver_view_transform() {\n  const float driver_view_ratio = 1.333;\n  mat4 transform;\n  if (Hardware::TICI()) {\n    // from dmonitoring.cc\n    const int full_width_tici = 1928;\n    const int full_height_tici = 1208;\n    const int adapt_width_tici = 668;\n    const int crop_x_offset = 32;\n    const int crop_y_offset = -196;\n    const float yscale = full_height_tici * driver_view_ratio / adapt_width_tici;\n    const float xscale = yscale*(1080)/(2160)*full_width_tici/full_height_tici;\n    transform = (mat4){{\n      xscale,  0.0, 0.0, xscale*crop_x_offset/full_width_tici*2,\n      0.0,  yscale, 0.0, yscale*crop_y_offset/full_height_tici*2,\n      0.0,  0.0, 1.0, 0.0,\n      0.0,  0.0, 0.0, 1.0,\n    }};\n  } else {\n    // frame from 4/3 to 16/9 display\n    transform = (mat4){{\n      driver_view_ratio*(1080)/(1920),  0.0, 0.0, 0.0,\n      0.0,  1.0, 0.0, 0.0,\n      0.0,  0.0, 1.0, 0.0,\n      0.0,  0.0, 0.0, 1.0,\n    }};\n  }\n  return transform;\n}\n\nmat4 get_fit_view_transform(float widget_aspect_ratio, float frame_aspect_ratio) {\n  float zx = 1, zy = 1;\n  if (frame_aspect_ratio > widget_aspect_ratio) {\n    zy = widget_aspect_ratio / frame_aspect_ratio;\n  } else {\n    zx = frame_aspect_ratio / widget_aspect_ratio;\n  }\n\n  const mat4 frame_transform = {{\n    zx, 0.0, 0.0, 0.0,\n    0.0, zy, 0.0, 0.0,\n    0.0, 0.0, 1.0, 0.0,\n    0.0, 0.0, 0.0, 1.0,\n  }};\n  return frame_transform;\n}\n\n} // namespace\n\nCameraViewWidget::CameraViewWidget(VisionStreamType stream_type, bool zoom, QWidget* parent) :\n                                   stream_type(stream_type), zoomed_view(zoom), QOpenGLWidget(parent) {\n  setAttribute(Qt::WA_OpaquePaintEvent);\n\n  timer = new QTimer(this);\n  connect(timer, &QTimer::timeout, this, &CameraViewWidget::updateFrame);\n}\n\nCameraViewWidget::~CameraViewWidget() {\n  makeCurrent();\n  if (isValid()) {\n    glDeleteVertexArrays(1, &frame_vao);\n    glDeleteBuffers(1, &frame_vbo);\n    glDeleteBuffers(1, &frame_ibo);\n  }\n  doneCurrent();\n}\n\nvoid CameraViewWidget::initializeGL() {\n  initializeOpenGLFunctions();\n\n  gl_shader = std::make_unique<GLShader>(frame_vertex_shader, frame_fragment_shader);\n  GLint frame_pos_loc = glGetAttribLocation(gl_shader->prog, \"aPosition\");\n  GLint frame_texcoord_loc = glGetAttribLocation(gl_shader->prog, \"aTexCoord\");\n\n  auto [x1, x2, y1, y2] = stream_type == VISION_STREAM_RGB_FRONT ? std::tuple(0.f, 1.f, 1.f, 0.f) : std::tuple(1.f, 0.f, 1.f, 0.f);\n  const uint8_t frame_indicies[] = {0, 1, 2, 0, 2, 3};\n  const float frame_coords[4][4] = {\n    {-1.0, -1.0, x2, y1}, // bl\n    {-1.0,  1.0, x2, y2}, // tl\n    { 1.0,  1.0, x1, y2}, // tr\n    { 1.0, -1.0, x1, y1}, // br\n  };\n\n  glGenVertexArrays(1, &frame_vao);\n  glBindVertexArray(frame_vao);\n  glGenBuffers(1, &frame_vbo);\n  glBindBuffer(GL_ARRAY_BUFFER, frame_vbo);\n  glBufferData(GL_ARRAY_BUFFER, sizeof(frame_coords), frame_coords, GL_STATIC_DRAW);\n  glEnableVertexAttribArray(frame_pos_loc);\n  glVertexAttribPointer(frame_pos_loc, 2, GL_FLOAT, GL_FALSE,\n                        sizeof(frame_coords[0]), (const void *)0);\n  glEnableVertexAttribArray(frame_texcoord_loc);\n  glVertexAttribPointer(frame_texcoord_loc, 2, GL_FLOAT, GL_FALSE,\n                        sizeof(frame_coords[0]), (const void *)(sizeof(float) * 2));\n  glGenBuffers(1, &frame_ibo);\n  glBindBuffer(GL_ELEMENT_ARRAY_BUFFER, frame_ibo);\n  glBufferData(GL_ELEMENT_ARRAY_BUFFER, sizeof(frame_indicies), frame_indicies, GL_STATIC_DRAW);\n  glBindBuffer(GL_ARRAY_BUFFER, 0);\n  glBindVertexArray(0);\n\n  vipc_client = std::make_unique<VisionIpcClient>(\"camerad\", stream_type, true);\n}\n\nvoid CameraViewWidget::showEvent(QShowEvent *event) {\n  timer->start(0);\n}\n\nvoid CameraViewWidget::hideEvent(QHideEvent *event) {\n  timer->stop();\n  vipc_client->connected = false;\n  latest_frame = nullptr;\n}\n\nvoid CameraViewWidget::mouseReleaseEvent(QMouseEvent *event) {\n  emit clicked();\n}\n\nvoid CameraViewWidget::resizeGL(int w, int h) {\n  if (!vipc_client->connected) {\n    return;\n  }\n\n  if (zoomed_view) {\n    if (stream_type == VISION_STREAM_RGB_FRONT) {\n      frame_mat = matmul(device_transform, get_driver_view_transform());\n    } else {\n      auto intrinsic_matrix = stream_type == VISION_STREAM_RGB_WIDE ? ecam_intrinsic_matrix : fcam_intrinsic_matrix;\n      float zoom = ZOOM / intrinsic_matrix.v[0];\n      if (stream_type == VISION_STREAM_RGB_WIDE) {\n        zoom *= 0.5;\n      }\n      float zx = zoom * 2 * intrinsic_matrix.v[2] / width();\n      float zy = zoom * 2 * intrinsic_matrix.v[5] / height();\n\n      const mat4 frame_transform = {{\n        zx, 0.0, 0.0, 0.0,\n        0.0, zy, 0.0, -y_offset / height() * 2,\n        0.0, 0.0, 1.0, 0.0,\n        0.0, 0.0, 0.0, 1.0,\n      }};\n      frame_mat = matmul(device_transform, frame_transform);\n    }\n  } else {\n    // fit frame to widget size\n    float w  = (float)width() / height();\n    float f = (float)vipc_client->buffers[0].width  / vipc_client->buffers[0].height;\n    frame_mat = matmul(device_transform, get_fit_view_transform(w, f));\n  }\n}\n\nvoid CameraViewWidget::paintGL() {\n  if (!latest_frame) {\n    glClearColor(0, 0, 0, 1.0);\n    glClear(GL_STENCIL_BUFFER_BIT | GL_COLOR_BUFFER_BIT);\n    return;\n  }\n\n  glViewport(0, 0, width(), height());\n\n  glBindVertexArray(frame_vao);\n  glActiveTexture(GL_TEXTURE0);\n\n  glBindTexture(GL_TEXTURE_2D, texture[latest_frame->idx]->frame_tex);\n  if (!Hardware::EON()) {\n    // this is handled in ion on QCOM\n    glTexImage2D(GL_TEXTURE_2D, 0, GL_RGB, latest_frame->width, latest_frame->height,\n                  0, GL_RGB, GL_UNSIGNED_BYTE, latest_frame->addr);\n  }\n\n  glUseProgram(gl_shader->prog);\n  glUniform1i(gl_shader->getUniformLocation(\"uTexture\"), 0);\n  glUniformMatrix4fv(gl_shader->getUniformLocation(\"uTransform\"), 1, GL_TRUE, frame_mat.v);\n\n  assert(glGetError() == GL_NO_ERROR);\n  glEnableVertexAttribArray(0);\n  glDrawElements(GL_TRIANGLES, 6, GL_UNSIGNED_BYTE, (const void *)0);\n  glDisableVertexAttribArray(0);\n  glBindVertexArray(0);\n}\n\nvoid CameraViewWidget::updateFrame() {\n  if (!vipc_client->connected && vipc_client->connect(false)) {\n    // init vision\n    for (int i = 0; i < vipc_client->num_buffers; i++) {\n      texture[i].reset(new EGLImageTexture(&vipc_client->buffers[i]));\n\n      glBindTexture(GL_TEXTURE_2D, texture[i]->frame_tex);\n      glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);\n      glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);\n\n      // BGR\n      glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_R, GL_BLUE);\n      glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_G, GL_GREEN);\n      glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_B, GL_RED);\n      assert(glGetError() == GL_NO_ERROR);\n    }\n    latest_frame = nullptr;\n    resizeGL(width(), height());\n  }\n\n  if (vipc_client->connected) {\n    VisionBuf *buf = vipc_client->recv();\n    if (buf != nullptr) {\n      latest_frame = buf;\n      update();\n      emit frameUpdated();\n    } else {\n      LOGE(\"visionIPC receive timeout\");\n    }\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/cameraview.h",
    "content": "#pragma once\n\n#include <memory>\n\n#include <QOpenGLFunctions>\n#include <QOpenGLWidget>\n\n#include \"cereal/visionipc/visionipc_client.h\"\n#include \"selfdrive/common/glutil.h\"\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/visionimg.h\"\n#include \"selfdrive/ui/ui.h\"\n\nclass CameraViewWidget : public QOpenGLWidget, protected QOpenGLFunctions {\n  Q_OBJECT\n\npublic:\n  using QOpenGLWidget::QOpenGLWidget;\n  explicit CameraViewWidget(VisionStreamType stream_type, bool zoom, QWidget* parent = nullptr);\n  ~CameraViewWidget();\n\nsignals:\n  void clicked();\n  void frameUpdated();\n\nprotected:\n  void paintGL() override;\n  void resizeGL(int w, int h) override;\n  void initializeGL() override;\n  void showEvent(QShowEvent *event) override;\n  void hideEvent(QHideEvent *event) override;\n  void mouseReleaseEvent(QMouseEvent *event) override;\n\nprotected slots:\n  void updateFrame();\n\nprivate:\n  bool zoomed_view;\n  VisionBuf *latest_frame = nullptr;\n  GLuint frame_vao, frame_vbo, frame_ibo;\n  mat4 frame_mat;\n  std::unique_ptr<VisionIpcClient> vipc_client;\n  std::unique_ptr<EGLImageTexture> texture[UI_BUF_COUNT];\n  std::unique_ptr<GLShader> gl_shader;\n\n  QTimer* timer;\n  VisionStreamType stream_type;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/controls.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/controls.h\"\n\n#include <QPainter>\n#include <QStyleOption>\n\nQFrame *horizontal_line(QWidget *parent) {\n  QFrame *line = new QFrame(parent);\n  line->setFrameShape(QFrame::StyledPanel);\n  line->setStyleSheet(R\"(\n    margin-left: 40px;\n    margin-right: 40px;\n    border-width: 1px;\n    border-bottom-style: solid;\n    border-color: gray;\n  )\");\n  line->setFixedHeight(2);\n  return line;\n}\n\nAbstractControl::AbstractControl(const QString &title, const QString &desc, const QString &icon, QWidget *parent) : QFrame(parent) {\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n  main_layout->setMargin(0);\n\n  hlayout = new QHBoxLayout;\n  hlayout->setMargin(0);\n  hlayout->setSpacing(20);\n\n  // left icon\n  if (!icon.isEmpty()) {\n    QPixmap pix(icon);\n    QLabel *icon = new QLabel();\n    icon->setPixmap(pix.scaledToWidth(80, Qt::SmoothTransformation));\n    icon->setSizePolicy(QSizePolicy(QSizePolicy::Fixed, QSizePolicy::Fixed));\n    hlayout->addWidget(icon);\n  }\n\n  // title\n  title_label = new QPushButton(title);\n  title_label->setStyleSheet(\"font-size: 50px; font-weight: 400; text-align: left;\");\n  hlayout->addWidget(title_label);\n\n  main_layout->addLayout(hlayout);\n\n  // description\n  if (!desc.isEmpty()) {\n    description = new QLabel(desc);\n    description->setContentsMargins(40, 20, 40, 20);\n    description->setStyleSheet(\"font-size: 40px; color: grey\");\n    description->setWordWrap(true);\n    description->setVisible(false);\n    main_layout->addWidget(description);\n\n    connect(title_label, &QPushButton::clicked, [=]() {\n      if (!description->isVisible()) {\n        emit showDescription();\n      }\n      description->setVisible(!description->isVisible());\n    });\n  }\n}\n\nvoid AbstractControl::hideEvent(QHideEvent *e) {\n  if(description != nullptr) {\n    description->hide();\n  }\n}\n\n// controls\n\nButtonControl::ButtonControl(const QString &title, const QString &text, const QString &desc, QWidget *parent) : AbstractControl(title, desc, \"\", parent) {\n  btn.setText(text);\n  btn.setStyleSheet(R\"(\n    QPushButton {\n      padding: 0;\n      border-radius: 50px;\n      font-size: 35px;\n      font-weight: 500;\n      color: #E4E4E4;\n      background-color: #393939;\n    }\n    QPushButton:pressed {\n      background-color: #4a4a4a;\n    }\n    QPushButton:disabled {\n      color: #33E4E4E4;\n    }\n  )\");\n  btn.setFixedSize(250, 100);\n  QObject::connect(&btn, &QPushButton::clicked, this, &ButtonControl::clicked);\n  hlayout->addWidget(&btn);\n}\n\n// ElidedLabel\n\nElidedLabel::ElidedLabel(QWidget *parent) : ElidedLabel({}, parent) {}\n\nElidedLabel::ElidedLabel(const QString &text, QWidget *parent) : QLabel(text.trimmed(), parent) {\n  setSizePolicy(QSizePolicy::Preferred, QSizePolicy::Preferred);\n  setMinimumWidth(1);\n}\n\nvoid ElidedLabel::resizeEvent(QResizeEvent* event) {\n  QLabel::resizeEvent(event);\n  lastText_ = elidedText_ = \"\";\n}\n\nvoid ElidedLabel::paintEvent(QPaintEvent *event) {\n  const QString curText = text();\n  if (curText != lastText_) {\n    elidedText_ = fontMetrics().elidedText(curText, Qt::ElideRight, contentsRect().width());\n    lastText_ = curText;\n  }\n\n  QPainter painter(this);\n  drawFrame(&painter);\n  QStyleOption opt;\n  opt.initFrom(this);\n  style()->drawItemText(&painter, contentsRect(), alignment(), opt.palette, isEnabled(), elidedText_, foregroundRole());\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/controls.h",
    "content": "#pragma once\n\n#include <QFrame>\n#include <QHBoxLayout>\n#include <QLabel>\n#include <QPushButton>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/widgets/toggle.h\"\n\nQFrame *horizontal_line(QWidget *parent = nullptr);\n\nclass ElidedLabel : public QLabel {\n  Q_OBJECT\n\npublic:\n  explicit ElidedLabel(QWidget *parent = 0);\n  explicit ElidedLabel(const QString &text, QWidget *parent = 0);\n\nsignals:\n  void clicked();\n\nprotected:\n  void paintEvent(QPaintEvent *event) override;\n  void resizeEvent(QResizeEvent* event) override;\n  void mouseReleaseEvent(QMouseEvent *event) override { emit clicked(); }\n  QString lastText_, elidedText_;\n};\n\n\nclass AbstractControl : public QFrame {\n  Q_OBJECT\n\npublic:\n  void setDescription(const QString &desc) {\n    if (description) description->setText(desc);\n  }\n\n  void setTitle(const QString &title) {\n    title_label->setText(title);\n  }\n\nsignals:\n  void showDescription();\n\nprotected:\n  AbstractControl(const QString &title, const QString &desc = \"\", const QString &icon = \"\", QWidget *parent = nullptr);\n  void hideEvent(QHideEvent *e) override;\n\n  QSize minimumSizeHint() const override {\n    QSize size = QFrame::minimumSizeHint();\n    size.setHeight(120);\n    return size;\n  };\n\n  QHBoxLayout *hlayout;\n  QPushButton *title_label;\n  QLabel *description = nullptr;\n};\n\n// widget to display a value\nclass LabelControl : public AbstractControl {\n  Q_OBJECT\n\npublic:\n  LabelControl(const QString &title, const QString &text = \"\", const QString &desc = \"\", QWidget *parent = nullptr) : AbstractControl(title, desc, \"\", parent) {\n    label.setText(text);\n    label.setAlignment(Qt::AlignRight | Qt::AlignVCenter);\n    hlayout->addWidget(&label);\n  }\n  void setText(const QString &text) { label.setText(text); }\n\nprivate:\n  ElidedLabel label;\n};\n\n// widget for a button with a label\nclass ButtonControl : public AbstractControl {\n  Q_OBJECT\n\npublic:\n  ButtonControl(const QString &title, const QString &text, const QString &desc = \"\", QWidget *parent = nullptr);\n  inline void setText(const QString &text) { btn.setText(text); }\n  inline QString text() const { return btn.text(); }\n\nsignals:\n  void clicked();\n\npublic slots:\n  void setEnabled(bool enabled) { btn.setEnabled(enabled); };\n\nprivate:\n  QPushButton btn;\n};\n\nclass ToggleControl : public AbstractControl {\n  Q_OBJECT\n\npublic:\n  ToggleControl(const QString &title, const QString &desc = \"\", const QString &icon = \"\", const bool state = false, QWidget *parent = nullptr) : AbstractControl(title, desc, icon, parent) {\n    toggle.setFixedSize(150, 100);\n    if (state) {\n      toggle.togglePosition();\n    }\n    hlayout->addWidget(&toggle);\n    QObject::connect(&toggle, &Toggle::stateChanged, this, &ToggleControl::toggleFlipped);\n  }\n\n  void setEnabled(bool enabled) { toggle.setEnabled(enabled); }\n\nsignals:\n  void toggleFlipped(bool state);\n\nprotected:\n  Toggle toggle;\n};\n\n// widget to toggle params\nclass ParamControl : public ToggleControl {\n  Q_OBJECT\n\npublic:\n  ParamControl(const QString &param, const QString &title, const QString &desc, const QString &icon, QWidget *parent = nullptr) : ToggleControl(title, desc, icon, false, parent) {\n    key = param.toStdString();\n    QObject::connect(this, &ToggleControl::toggleFlipped, [=](bool state) {\n      params.putBool(key, state);\n    });\n  }\n\n  void showEvent(QShowEvent *event) override {\n    if (params.getBool(key) != toggle.on) {\n      toggle.togglePosition();\n    }\n  };\n\nprivate:\n  std::string key;\n  Params params;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/drive_stats.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/drive_stats.h\"\n\n#include <QDebug>\n#include <QGridLayout>\n#include <QJsonObject>\n#include <QVBoxLayout>\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/request_repeater.h\"\n#include \"selfdrive/ui/qt/util.h\"\n\nconst double MILE_TO_KM = 1.60934;\n\nstatic QLabel* newLabel(const QString& text, const QString &type) {\n  QLabel* label = new QLabel(text);\n  label->setProperty(\"type\", type);\n  return label;\n}\n\nDriveStats::DriveStats(QWidget* parent) : QFrame(parent) {\n  metric_ = Params().getBool(\"IsMetric\");\n\n  QVBoxLayout* main_layout = new QVBoxLayout(this);\n  main_layout->setContentsMargins(50, 50, 50, 60);\n\n  auto add_stats_layouts = [=](const QString &title, StatsLabels& labels) {\n    QGridLayout* grid_layout = new QGridLayout;\n    grid_layout->setVerticalSpacing(10);\n    grid_layout->setContentsMargins(0, 10, 0, 10);\n\n    int row = 0;\n    grid_layout->addWidget(newLabel(title, \"title\"), row++, 0, 1, 3);\n    grid_layout->addItem(new QSpacerItem(0, 50), row++, 0, 1, 1);\n\n    grid_layout->addWidget(labels.routes = newLabel(\"0\", \"number\"), row, 0, Qt::AlignLeft);\n    grid_layout->addWidget(labels.distance = newLabel(\"0\", \"number\"), row, 1, Qt::AlignLeft);\n    grid_layout->addWidget(labels.hours = newLabel(\"0\", \"number\"), row, 2, Qt::AlignLeft);\n\n    grid_layout->addWidget(newLabel(\"Drives\", \"unit\"), row + 1, 0, Qt::AlignLeft);\n    grid_layout->addWidget(labels.distance_unit = newLabel(getDistanceUnit(), \"unit\"), row + 1, 1, Qt::AlignLeft);\n    grid_layout->addWidget(newLabel(\"Hours \", \"unit\"), row + 1, 2, Qt::AlignLeft);\n\n    main_layout->addLayout(grid_layout);\n  };\n\n  add_stats_layouts(\"ALL TIME\", all_);\n  main_layout->addStretch();\n  add_stats_layouts(\"PAST WEEK\", week_);\n\n  if (auto dongleId = getDongleId()) {\n    QString url = CommaApi::BASE_URL + \"/v1.1/devices/\" + *dongleId + \"/stats\";\n    RequestRepeater* repeater = new RequestRepeater(this, url, \"ApiCache_DriveStats\", 30);\n    QObject::connect(repeater, &RequestRepeater::receivedResponse, this, &DriveStats::parseResponse);\n  }\n\n  setStyleSheet(R\"(\n    DriveStats {\n      background-color: #333333;\n      border-radius: 10px;\n    }\n\n    QLabel[type=\"title\"] { font-size: 51px; font-weight: 500; }\n    QLabel[type=\"number\"] { font-size: 78px; font-weight: 500; }\n    QLabel[type=\"unit\"] { font-size: 51px; font-weight: 300; color: #A0A0A0; }\n  )\");\n}\n\nvoid DriveStats::updateStats() {\n  auto update = [=](const QJsonObject& obj, StatsLabels& labels) {\n    labels.routes->setText(QString::number((int)obj[\"routes\"].toDouble()));\n    labels.distance->setText(QString::number(int(obj[\"distance\"].toDouble() * (metric_ ? MILE_TO_KM : 1))));\n    labels.distance_unit->setText(getDistanceUnit());\n    labels.hours->setText(QString::number((int)(obj[\"minutes\"].toDouble() / 60)));\n  };\n\n  QJsonObject json = stats_.object();\n  update(json[\"all\"].toObject(), all_);\n  update(json[\"week\"].toObject(), week_);\n}\n\nvoid DriveStats::parseResponse(const QString& response) {\n  QJsonDocument doc = QJsonDocument::fromJson(response.trimmed().toUtf8());\n  if (doc.isNull()) {\n    qDebug() << \"JSON Parse failed on getting past drives statistics\";\n    return;\n  }\n  stats_ = doc;\n  updateStats();\n}\n\nvoid DriveStats::showEvent(QShowEvent* event) {\n  bool metric = Params().getBool(\"IsMetric\");\n  if (metric_ != metric) {\n    metric_ = metric;\n    updateStats();\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/drive_stats.h",
    "content": "#pragma once\n\n#include <QJsonDocument>\n#include <QLabel>\n\nclass DriveStats : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit DriveStats(QWidget* parent = 0);\n\nprivate:\n  void showEvent(QShowEvent *event) override;\n  void updateStats();\n  inline QString getDistanceUnit() const { return metric_ ? \"KM\" : \"Miles\"; }\n\n  bool metric_;\n  QJsonDocument stats_;\n  struct StatsLabels {\n    QLabel *routes, *distance, *distance_unit, *hours;\n  } all_, week_;\n\nprivate slots:\n  void parseResponse(const QString &response);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/input.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/input.h\"\n\n#include <QPushButton>\n\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/util.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n\n\nQDialogBase::QDialogBase(QWidget *parent) : QDialog(parent) {\n  Q_ASSERT(parent != nullptr);\n  parent->installEventFilter(this);\n\n  setStyleSheet(R\"(\n    * {\n      outline: none;\n      color: white;\n      font-family: Inter;\n    }\n    QDialogBase {\n      background-color: black;\n    }\n    QPushButton {\n      height: 160;\n      font-size: 55px;\n      font-weight: 400;\n      border-radius: 10px;\n      color: white;\n      background-color: #333333;\n    }\n    QPushButton:pressed {\n      background-color: #444444;\n    }\n\n  )\");\n}\n\nbool QDialogBase::eventFilter(QObject *o, QEvent *e) {\n  if (o == parent() && e->type() == QEvent::Hide) {\n    reject();\n  }\n  return QDialog::eventFilter(o, e);\n}\n\nint QDialogBase::exec() {\n  setMainWindow(this);\n  return QDialog::exec();\n}\n\nInputDialog::InputDialog(const QString &title, QWidget *parent, const QString &subtitle, bool secret) : QDialogBase(parent) {\n  main_layout = new QVBoxLayout(this);\n  main_layout->setContentsMargins(50, 55, 50, 50);\n  main_layout->setSpacing(0);\n\n  // build header\n  QHBoxLayout *header_layout = new QHBoxLayout();\n\n  QVBoxLayout *vlayout = new QVBoxLayout;\n  header_layout->addLayout(vlayout);\n  label = new QLabel(title, this);\n  label->setStyleSheet(\"font-size: 90px; font-weight: bold;\");\n  vlayout->addWidget(label, 1, Qt::AlignTop | Qt::AlignLeft);\n\n  if (!subtitle.isEmpty()) {\n    sublabel = new QLabel(subtitle, this);\n    sublabel->setStyleSheet(\"font-size: 55px; font-weight: light; color: #BDBDBD;\");\n    vlayout->addWidget(sublabel, 1, Qt::AlignTop | Qt::AlignLeft);\n  }\n\n  QPushButton* cancel_btn = new QPushButton(\"Cancel\");\n  cancel_btn->setFixedSize(386, 125);\n  cancel_btn->setStyleSheet(R\"(\n    font-size: 48px;\n    border-radius: 10px;\n    color: #E4E4E4;\n    background-color: #444444;\n  )\");\n  header_layout->addWidget(cancel_btn, 0, Qt::AlignRight);\n  QObject::connect(cancel_btn, &QPushButton::clicked, this, &InputDialog::reject);\n  QObject::connect(cancel_btn, &QPushButton::clicked, this, &InputDialog::cancel);\n\n  main_layout->addLayout(header_layout);\n\n  // text box\n  main_layout->addStretch(2);\n\n  QWidget *textbox_widget = new QWidget;\n  textbox_widget->setObjectName(\"textbox\");\n  QHBoxLayout *textbox_layout = new QHBoxLayout(textbox_widget);\n  textbox_layout->setContentsMargins(50, 0, 50, 0);\n\n  textbox_widget->setStyleSheet(R\"(\n    #textbox {\n      margin-left: 50px;\n      margin-right: 50px;\n      border-radius: 0;\n      border-bottom: 3px solid #BDBDBD;\n    }\n    * {\n      border: none;\n      font-size: 80px;\n      font-weight: light;\n      background-color: transparent;\n    }\n  )\");\n\n  line = new QLineEdit();\n  line->setStyleSheet(\"lineedit-password-character: 8226; lineedit-password-mask-delay: 1500;\");\n  textbox_layout->addWidget(line, 1);\n\n  if (secret) {\n    eye_btn = new QPushButton();\n    eye_btn->setCheckable(true);\n    eye_btn->setFixedSize(150, 120);\n    QObject::connect(eye_btn, &QPushButton::toggled, [=](bool checked) {\n      if (checked) {\n        eye_btn->setIcon(QIcon(ASSET_PATH + \"img_eye_closed.svg\"));\n        eye_btn->setIconSize(QSize(81, 54));\n        line->setEchoMode(QLineEdit::Password);\n      } else {\n        eye_btn->setIcon(QIcon(ASSET_PATH + \"img_eye_open.svg\"));\n        eye_btn->setIconSize(QSize(81, 44));\n        line->setEchoMode(QLineEdit::Normal);\n      }\n    });\n    eye_btn->setChecked(true);\n    textbox_layout->addWidget(eye_btn);\n  }\n\n  main_layout->addWidget(textbox_widget, 0, Qt::AlignBottom);\n  main_layout->addSpacing(25);\n\n  k = new Keyboard(this);\n  QObject::connect(k, &Keyboard::emitEnter, this, &InputDialog::handleEnter);\n  QObject::connect(k, &Keyboard::emitBackspace, this, [=]() {\n    line->backspace();\n  });\n  QObject::connect(k, &Keyboard::emitKey, this, [=](const QString &key) {\n    line->insert(key.left(1));\n  });\n\n  main_layout->addWidget(k, 2, Qt::AlignBottom);\n}\n\nQString InputDialog::getText(const QString &prompt, QWidget *parent, const QString &subtitle,\n                             bool secret, int minLength, const QString &defaultText) {\n  InputDialog d = InputDialog(prompt, parent, subtitle, secret);\n  d.line->setText(defaultText);\n  d.setMinLength(minLength);\n  const int ret = d.exec();\n  return ret ? d.text() : QString();\n}\n\nQString InputDialog::text() {\n  return line->text();\n}\n\nvoid InputDialog::show() {\n  setMainWindow(this);\n}\n\nvoid InputDialog::handleEnter() {\n  if (line->text().length() >= minLength) {\n    done(QDialog::Accepted);\n    emitText(line->text());\n  } else {\n    setMessage(\"Need at least \"+QString::number(minLength)+\" characters!\", false);\n  }\n}\n\nvoid InputDialog::setMessage(const QString &message, bool clearInputField) {\n  label->setText(message);\n  if (clearInputField) {\n    line->setText(\"\");\n  }\n}\n\nvoid InputDialog::setMinLength(int length) {\n  minLength = length;\n}\n\n// ConfirmationDialog\n\nConfirmationDialog::ConfirmationDialog(const QString &prompt_text, const QString &confirm_text, const QString &cancel_text,\n                                       QWidget *parent) : QDialogBase(parent) {\n  QFrame *container = new QFrame(this);\n  container->setStyleSheet(\"QFrame { border-radius: 0; background-color: #ECECEC; }\");\n  QVBoxLayout *main_layout = new QVBoxLayout(container);\n  main_layout->setContentsMargins(32, 120, 32, 32);\n\n  QLabel *prompt = new QLabel(prompt_text, this);\n  prompt->setWordWrap(true);\n  prompt->setAlignment(Qt::AlignHCenter);\n  prompt->setStyleSheet(\"font-size: 70px; font-weight: bold; color: black;\");\n  main_layout->addWidget(prompt, 1, Qt::AlignTop | Qt::AlignHCenter);\n\n  // cancel + confirm buttons\n  QHBoxLayout *btn_layout = new QHBoxLayout();\n  btn_layout->setSpacing(30);\n  main_layout->addLayout(btn_layout);\n\n  if (cancel_text.length()) {\n    QPushButton* cancel_btn = new QPushButton(cancel_text);\n    btn_layout->addWidget(cancel_btn);\n    QObject::connect(cancel_btn, &QPushButton::clicked, this, &ConfirmationDialog::reject);\n  }\n\n  if (confirm_text.length()) {\n    QPushButton* confirm_btn = new QPushButton(confirm_text);\n    btn_layout->addWidget(confirm_btn);\n    QObject::connect(confirm_btn, &QPushButton::clicked, this, &ConfirmationDialog::accept);\n  }\n\n  QVBoxLayout *outer_layout = new QVBoxLayout(this);\n  outer_layout->setContentsMargins(210, 170, 210, 170);\n  outer_layout->addWidget(container);\n}\n\nbool ConfirmationDialog::alert(const QString &prompt_text, QWidget *parent) {\n  ConfirmationDialog d = ConfirmationDialog(prompt_text, \"Ok\", \"\", parent);\n  return d.exec();\n}\n\nbool ConfirmationDialog::confirm(const QString &prompt_text, QWidget *parent) {\n  ConfirmationDialog d = ConfirmationDialog(prompt_text, \"Ok\", \"Cancel\", parent);\n  return d.exec();\n}\n\n\n// RichTextDialog\n\nRichTextDialog::RichTextDialog(const QString &prompt_text, const QString &btn_text,\n                               QWidget *parent) : QDialogBase(parent) {\n  QFrame *container = new QFrame(this);\n  container->setStyleSheet(\"QFrame { background-color: #1B1B1B; }\");\n  QVBoxLayout *main_layout = new QVBoxLayout(container);\n  main_layout->setContentsMargins(32, 32, 32, 32);\n\n  QLabel *prompt = new QLabel(prompt_text, this);\n  prompt->setWordWrap(true);\n  prompt->setAlignment(Qt::AlignLeft);\n  prompt->setTextFormat(Qt::RichText);\n  prompt->setStyleSheet(\"font-size: 42px; font-weight: light; color: #C9C9C9; margin: 45px;\");\n  main_layout->addWidget(new ScrollView(prompt, this), 1, Qt::AlignTop);\n\n  // confirm button\n  QPushButton* confirm_btn = new QPushButton(btn_text);\n  main_layout->addWidget(confirm_btn);\n  QObject::connect(confirm_btn, &QPushButton::clicked, this, &QDialog::accept);\n\n  QVBoxLayout *outer_layout = new QVBoxLayout(this);\n  outer_layout->setContentsMargins(100, 100, 100, 100);\n  outer_layout->addWidget(container);\n}\n\nbool RichTextDialog::alert(const QString &prompt_text, QWidget *parent) {\n  auto d = RichTextDialog(prompt_text, \"Ok\", parent);\n  return d.exec();\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/input.h",
    "content": "#pragma once\n\n#include <QDialog>\n#include <QLabel>\n#include <QLineEdit>\n#include <QString>\n#include <QVBoxLayout>\n#include <QWidget>\n\n#include \"selfdrive/ui/qt/widgets/keyboard.h\"\n\n\nclass QDialogBase : public QDialog {\n  Q_OBJECT\n\nprotected:\n  QDialogBase(QWidget *parent);\n  bool eventFilter(QObject *o, QEvent *e) override;\n\npublic slots:\n  int exec() override;\n};\n\nclass InputDialog : public QDialogBase {\n  Q_OBJECT\n\npublic:\n  explicit InputDialog(const QString &title, QWidget *parent, const QString &subtitle = \"\", bool secret = false);\n  static QString getText(const QString &title, QWidget *parent, const QString &substitle = \"\",\n                         bool secret = false, int minLength = -1, const QString &defaultText = \"\");\n  QString text();\n  void setMessage(const QString &message, bool clearInputField = true);\n  void setMinLength(int length);\n  void show();\n\nprivate:\n  int minLength;\n  QLineEdit *line;\n  Keyboard *k;\n  QLabel *label;\n  QLabel *sublabel;\n  QVBoxLayout *main_layout;\n  QPushButton *eye_btn;\n\nprivate slots:\n  void handleEnter();\n\nsignals:\n  void cancel();\n  void emitText(const QString &text);\n};\n\nclass ConfirmationDialog : public QDialogBase {\n  Q_OBJECT\n\npublic:\n  explicit ConfirmationDialog(const QString &prompt_text, const QString &confirm_text,\n                              const QString &cancel_text, QWidget* parent);\n  static bool alert(const QString &prompt_text, QWidget *parent);\n  static bool confirm(const QString &prompt_text, QWidget *parent);\n};\n\n// larger ConfirmationDialog for rich text\nclass RichTextDialog : public QDialogBase {\n  Q_OBJECT\n\npublic:\n  explicit RichTextDialog(const QString &prompt_text, const QString &btn_text, QWidget* parent);\n  static bool alert(const QString &prompt_text, QWidget *parent);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/keyboard.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/keyboard.h\"\n\n#include <vector>\n\n#include <QButtonGroup>\n#include <QHBoxLayout>\n#include <QMap>\n#include <QTouchEvent>\n#include <QVBoxLayout>\n\nconst QString BACKSPACE_KEY = \"⌫\";\nconst QString ENTER_KEY = \"→\";\n\nconst QMap<QString, int> KEY_STRETCH = {{\"  \", 5}, {ENTER_KEY, 2}};\n\nconst QStringList CONTROL_BUTTONS = {\"↑\", \"↓\", \"ABC\", \"#+=\", \"123\", BACKSPACE_KEY, ENTER_KEY};\n\nconst float key_spacing_vertical = 20;\nconst float key_spacing_horizontal = 15;\n\nKeyButton::KeyButton(const QString &text, QWidget *parent) : QPushButton(text, parent) {\n  setAttribute(Qt::WA_AcceptTouchEvents);\n  setFocusPolicy(Qt::NoFocus);\n}\n\nbool KeyButton::event(QEvent *event) {\n  if (event->type() == QEvent::TouchBegin || event->type() == QEvent::TouchEnd) {\n    QTouchEvent *touchEvent = static_cast<QTouchEvent *>(event);\n    if (!touchEvent->touchPoints().empty()) {\n      const QEvent::Type mouseType = event->type() == QEvent::TouchBegin ? QEvent::MouseButtonPress : QEvent::MouseButtonRelease;\n      QMouseEvent mouseEvent(mouseType, touchEvent->touchPoints().front().pos(), Qt::LeftButton, Qt::LeftButton, Qt::NoModifier);\n      QPushButton::event(&mouseEvent);\n      event->accept();\n      parentWidget()->update();\n      return true;\n    }\n  }\n  return QPushButton::event(event);\n}\n\nKeyboardLayout::KeyboardLayout(QWidget* parent, const std::vector<QVector<QString>>& layout) : QWidget(parent) {\n  QVBoxLayout* main_layout = new QVBoxLayout(this);\n  main_layout->setMargin(0);\n  main_layout->setSpacing(0);\n\n  QButtonGroup* btn_group = new QButtonGroup(this);\n  QObject::connect(btn_group, SIGNAL(buttonClicked(QAbstractButton*)), parent, SLOT(handleButton(QAbstractButton*)));\n\n  for (const auto &s : layout) {\n    QHBoxLayout *hlayout = new QHBoxLayout;\n    hlayout->setSpacing(0);\n\n    if (main_layout->count() == 1) {\n      hlayout->addSpacing(90);\n    }\n\n    for (const QString &p : s) {\n      KeyButton* btn = new KeyButton(p);\n      if (p == BACKSPACE_KEY) {\n        btn->setAutoRepeat(true);\n      } else if (p == ENTER_KEY) {\n        btn->setStyleSheet(\"background-color: #465BEA;\");\n      }\n      btn->setFixedHeight(135 + key_spacing_vertical);\n      btn_group->addButton(btn);\n      hlayout->addWidget(btn, KEY_STRETCH.value(p, 1));\n    }\n\n    if (main_layout->count() == 1) {\n      hlayout->addSpacing(90);\n    }\n\n    main_layout->addLayout(hlayout);\n  }\n\n  setStyleSheet(QString(R\"(\n    QPushButton {\n      font-size: 75px;\n      margin-left: %1px;\n      margin-right: %1px;\n      margin-top: %2px;\n      margin-bottom: %2px;\n      padding: 0px;\n      border-radius: 10px;\n      color: #dddddd;\n      background-color: #444444;\n    }\n    QPushButton:pressed {\n      background-color: #333333;\n    }\n  )\").arg(key_spacing_vertical / 2).arg(key_spacing_horizontal / 2));\n}\n\nKeyboard::Keyboard(QWidget *parent) : QFrame(parent) {\n  main_layout = new QStackedLayout(this);\n  main_layout->setMargin(0);\n\n  // lowercase\n  std::vector<QVector<QString>> lowercase = {\n    {\"q\",\"w\",\"e\",\"r\",\"t\",\"y\",\"u\",\"i\",\"o\",\"p\"},\n    {\"a\",\"s\",\"d\",\"f\",\"g\",\"h\",\"j\",\"k\",\"l\"},\n    {\"↑\",\"z\",\"x\",\"c\",\"v\",\"b\",\"n\",\"m\",BACKSPACE_KEY},\n    {\"123\",\"  \",\".\",ENTER_KEY},\n  };\n  main_layout->addWidget(new KeyboardLayout(this, lowercase));\n\n  // uppercase\n  std::vector<QVector<QString>> uppercase = {\n    {\"Q\",\"W\",\"E\",\"R\",\"T\",\"Y\",\"U\",\"I\",\"O\",\"P\"},\n    {\"A\",\"S\",\"D\",\"F\",\"G\",\"H\",\"J\",\"K\",\"L\"},\n    {\"↓\",\"Z\",\"X\",\"C\",\"V\",\"B\",\"N\",\"M\",BACKSPACE_KEY},\n    {\"123\",\"  \",\".\",ENTER_KEY},\n  };\n  main_layout->addWidget(new KeyboardLayout(this, uppercase));\n\n  // numbers + specials\n  std::vector<QVector<QString>> numbers = {\n    {\"1\",\"2\",\"3\",\"4\",\"5\",\"6\",\"7\",\"8\",\"9\",\"0\"},\n    {\"-\",\"/\",\":\",\";\",\"(\",\")\",\"$\",\"&&\",\"@\",\"\\\"\"},\n    {\"#+=\",\".\",\",\",\"?\",\"!\",\"`\",BACKSPACE_KEY},\n    {\"ABC\",\"  \",\".\",ENTER_KEY},\n  };\n  main_layout->addWidget(new KeyboardLayout(this, numbers));\n\n  // extra specials\n  std::vector<QVector<QString>> specials = {\n    {\"[\",\"]\",\"{\",\"}\",\"#\",\"%\",\"^\",\"*\",\"+\",\"=\"},\n    {\"_\",\"\\\\\",\"|\",\"~\",\"<\",\">\",\"€\",\"£\",\"¥\",\"•\"},\n    {\"123\",\".\",\",\",\"?\",\"!\",\"`\",BACKSPACE_KEY},\n    {\"ABC\",\"  \",\".\",ENTER_KEY},\n  };\n  main_layout->addWidget(new KeyboardLayout(this, specials));\n\n  main_layout->setCurrentIndex(0);\n}\n\nvoid Keyboard::handleButton(QAbstractButton* btn) {\n  const QString &key = btn->text();\n  if (CONTROL_BUTTONS.contains(key)) {\n    if (key == \"↓\" || key == \"ABC\") {\n      main_layout->setCurrentIndex(0);\n    } else if (key == \"↑\") {\n      main_layout->setCurrentIndex(1);\n    } else if (key == \"123\") {\n      main_layout->setCurrentIndex(2);\n    } else if (key == \"#+=\") {\n      main_layout->setCurrentIndex(3);\n    } else if (key == ENTER_KEY) {\n      main_layout->setCurrentIndex(0);\n      emit emitEnter();\n    } else if (key == BACKSPACE_KEY) {\n      emit emitBackspace();\n    }\n  } else {\n    if (\"A\" <= key && key <= \"Z\") {\n      main_layout->setCurrentIndex(0);\n    }\n    emit emitKey(key);\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/keyboard.h",
    "content": "#pragma once\n\n#include <QFrame>\n#include <QPushButton>\n#include <QStackedLayout>\n\nclass KeyButton : public QPushButton {\n  Q_OBJECT\n\npublic:\n  KeyButton(const QString &text, QWidget *parent = 0);\n  bool event(QEvent *event) override;\n};\n\nclass KeyboardLayout : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit KeyboardLayout(QWidget* parent, const std::vector<QVector<QString>>& layout);\n};\n\nclass Keyboard : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit Keyboard(QWidget *parent = 0);\n\nprivate:\n  QStackedLayout* main_layout;\n\nprivate slots:\n  void handleButton(QAbstractButton* m_button);\n\nsignals:\n  void emitKey(const QString &s);\n  void emitBackspace();\n  void emitEnter();\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/offroad_alerts.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/offroad_alerts.h\"\n\n#include <QHBoxLayout>\n#include <QJsonDocument>\n#include <QJsonObject>\n#include <QPushButton>\n\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n\nAbstractAlert::AbstractAlert(bool hasRebootBtn, QWidget *parent) : QFrame(parent) {\n  QVBoxLayout *main_layout = new QVBoxLayout(this);\n  main_layout->setMargin(50);\n  main_layout->setSpacing(30);\n\n  QWidget *widget = new QWidget;\n  scrollable_layout = new QVBoxLayout(widget);\n  widget->setStyleSheet(\"background-color: transparent;\");\n  main_layout->addWidget(new ScrollView(widget));\n\n  // bottom footer, dismiss + reboot buttons\n  QHBoxLayout *footer_layout = new QHBoxLayout();\n  main_layout->addLayout(footer_layout);\n\n  QPushButton *dismiss_btn = new QPushButton(\"Dismiss\");\n  dismiss_btn->setFixedSize(400, 125);\n  footer_layout->addWidget(dismiss_btn, 0, Qt::AlignBottom | Qt::AlignLeft);\n  QObject::connect(dismiss_btn, &QPushButton::clicked, this, &AbstractAlert::dismiss);\n\n  if (hasRebootBtn) {\n    QPushButton *rebootBtn = new QPushButton(\"Reboot and Update\");\n    rebootBtn->setFixedSize(600, 125);\n    footer_layout->addWidget(rebootBtn, 0, Qt::AlignBottom | Qt::AlignRight);\n    QObject::connect(rebootBtn, &QPushButton::clicked, [=]() { Hardware::reboot(); });\n  }\n  setStyleSheet(R\"(\n    * {\n      font-size: 48px;\n      color: white;\n    }\n    QFrame {\n      border-radius: 30px;\n      background-color: #393939;\n    }\n    QPushButton {\n      color: black;\n      font-weight: 500;\n      border-radius: 30px;\n      background-color: white;\n    }\n  )\");\n}\n\nint OffroadAlert::refresh() {\n  if (alerts.empty()) {\n    // setup labels for each alert\n    QString json = util::read_file(\"../controls/lib/alerts_offroad.json\").c_str();\n    QJsonObject obj = QJsonDocument::fromJson(json.toUtf8()).object();\n    // descending sort labels by severity\n    std::vector<std::pair<std::string, int>> sorted;\n    for (auto it = obj.constBegin(); it != obj.constEnd(); ++it) {\n      sorted.push_back({it.key().toStdString(), it.value()[\"severity\"].toInt()});\n    }\n    std::sort(sorted.begin(), sorted.end(), [=](auto &l, auto &r) { return l.second > r.second; });\n\n    for (auto &[key, severity] : sorted) {\n      QLabel *l = new QLabel(this);\n      alerts[key] = l;\n      l->setMargin(60);\n      l->setWordWrap(true);\n      l->setStyleSheet(QString(\"background-color: %1\").arg(severity ? \"#E22C2C\" : \"#292929\"));\n      scrollable_layout->addWidget(l);\n    }\n    scrollable_layout->addStretch(1);\n  }\n\n  int alertCount = 0;\n  for (const auto &[key, label] : alerts) {\n    QString text;\n    std::string bytes = params.get(key);\n    if (bytes.size()) {\n      auto doc_par = QJsonDocument::fromJson(bytes.c_str());\n      text = doc_par[\"text\"].toString();\n    }\n    label->setText(text);\n    label->setVisible(!text.isEmpty());\n    alertCount += !text.isEmpty();\n  }\n  return alertCount;\n}\n\nUpdateAlert::UpdateAlert(QWidget *parent) : AbstractAlert(true, parent) {\n  releaseNotes = new QLabel(this);\n  releaseNotes->setWordWrap(true);\n  releaseNotes->setAlignment(Qt::AlignTop);\n  scrollable_layout->addWidget(releaseNotes);\n}\n\nbool UpdateAlert::refresh() {\n  bool updateAvailable = params.getBool(\"UpdateAvailable\");\n  if (updateAvailable) {\n    releaseNotes->setText(params.get(\"ReleaseNotes\").c_str());\n  }\n  return updateAvailable;\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/offroad_alerts.h",
    "content": "#pragma once\n\n#include <map>\n\n#include <QLabel>\n#include <QVBoxLayout>\n\n#include \"selfdrive/common/params.h\"\n\nclass AbstractAlert : public QFrame {\n  Q_OBJECT\n\nprotected:\n  AbstractAlert(bool hasRebootBtn, QWidget *parent = nullptr);\n  QVBoxLayout *scrollable_layout;\n  Params params;\n\nsignals:\n  void dismiss();\n};\n\nclass UpdateAlert : public AbstractAlert {\n  Q_OBJECT\n\npublic:\n  UpdateAlert(QWidget *parent = 0);\n  bool refresh();\n\nprivate:\n  QLabel *releaseNotes = nullptr;\n};\n\nclass OffroadAlert : public AbstractAlert {\n  Q_OBJECT\n\npublic:\n  explicit OffroadAlert(QWidget *parent = 0) : AbstractAlert(false, parent) {}\n  int refresh();\n\nprivate:\n  std::map<std::string, QLabel*> alerts;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/prime.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/prime.h\"\n\n#include <QDebug>\n#include <QJsonDocument>\n#include <QJsonObject>\n#include <QLabel>\n#include <QPushButton>\n#include <QStackedWidget>\n#include <QTimer>\n#include <QVBoxLayout>\n#include <QrCode.hpp>\n\n#include \"selfdrive/ui/qt/request_repeater.h\"\n#include \"selfdrive/ui/qt/util.h\"\n\nusing qrcodegen::QrCode;\n\nPairingQRWidget::PairingQRWidget(QWidget* parent) : QWidget(parent) {\n  qrCode = new QLabel;\n  qrCode->setScaledContents(true);\n  QVBoxLayout* main_layout = new QVBoxLayout(this);\n  main_layout->addWidget(qrCode, 0, Qt::AlignCenter);\n\n  QTimer* timer = new QTimer(this);\n  timer->start(30 * 1000);\n  connect(timer, &QTimer::timeout, this, &PairingQRWidget::refresh);\n}\n\nvoid PairingQRWidget::showEvent(QShowEvent *event) {\n  refresh();\n}\n\nvoid PairingQRWidget::refresh() {\n  QString pairToken = CommaApi::create_jwt({{\"pair\", true}});\n  QString qrString = \"https://connect.comma.ai/?pair=\" + pairToken;\n  this->updateQrCode(qrString);\n}\n\nvoid PairingQRWidget::updateQrCode(const QString &text) {\n  QrCode qr = QrCode::encodeText(text.toUtf8().data(), QrCode::Ecc::LOW);\n  qint32 sz = qr.getSize();\n  // make the image larger so we can have a white border\n  QImage im(sz + 2, sz + 2, QImage::Format_RGB32);\n  QRgb black = qRgb(0, 0, 0);\n  QRgb white = qRgb(255, 255, 255);\n\n  for (int y = 0; y < sz + 2; y++) {\n    for (int x = 0; x < sz + 2; x++) {\n      im.setPixel(x, y, white);\n    }\n  }\n  for (int y = 0; y < sz; y++) {\n    for (int x = 0; x < sz; x++) {\n      im.setPixel(x + 1, y + 1, qr.getModule(x, y) ? black : white);\n    }\n  }\n  // Integer division to prevent anti-aliasing\n  int approx500 = (500 / (sz + 2)) * (sz + 2);\n  qrCode->setPixmap(QPixmap::fromImage(im.scaled(approx500, approx500, Qt::KeepAspectRatio, Qt::FastTransformation), Qt::MonoOnly));\n  qrCode->setFixedSize(approx500, approx500);\n}\n\nPrimeUserWidget::PrimeUserWidget(QWidget* parent) : QWidget(parent) {\n  mainLayout = new QVBoxLayout(this);\n  mainLayout->setMargin(0);\n  mainLayout->setSpacing(30);\n\n  // subscribed prime layout\n  QWidget *primeWidget = new QWidget;\n  primeWidget->setObjectName(\"primeWidget\");\n  QVBoxLayout *primeLayout = new QVBoxLayout(primeWidget);\n  primeLayout->setMargin(0);\n  primeWidget->setContentsMargins(60, 50, 60, 50);\n\n  QLabel* subscribed = new QLabel(\"✓ SUBSCRIBED\");\n  subscribed->setStyleSheet(\"font-size: 41px; font-weight: bold; color: #86FF4E;\");\n  primeLayout->addWidget(subscribed, 0, Qt::AlignTop);\n\n  primeLayout->addSpacing(60);\n\n  QLabel* commaPrime = new QLabel(\"comma prime\");\n  commaPrime->setStyleSheet(\"font-size: 75px; font-weight: bold;\");\n  primeLayout->addWidget(commaPrime, 0, Qt::AlignTop);\n\n  primeLayout->addSpacing(20);\n\n  QLabel* connectUrl = new QLabel(\"CONNECT.COMMA.AI\");\n  connectUrl->setStyleSheet(\"font-size: 41px; font-family: Inter SemiBold; color: #A0A0A0;\");\n  primeLayout->addWidget(connectUrl, 0, Qt::AlignTop);\n\n  mainLayout->addWidget(primeWidget);\n\n  // comma points layout\n  QWidget *pointsWidget = new QWidget;\n  pointsWidget->setObjectName(\"primeWidget\");\n  QVBoxLayout *pointsLayout = new QVBoxLayout(pointsWidget);\n  pointsLayout->setMargin(0);\n  pointsWidget->setContentsMargins(60, 50, 60, 50);\n\n  QLabel* commaPoints = new QLabel(\"COMMA POINTS\");\n  commaPoints->setStyleSheet(\"font-size: 41px; font-family: Inter SemiBold;\");\n  pointsLayout->addWidget(commaPoints, 0, Qt::AlignTop);\n\n  points = new QLabel(\"210\");\n  points->setStyleSheet(\"font-size: 91px; font-weight: bold;\");\n  pointsLayout->addWidget(points, 0, Qt::AlignTop);\n\n  mainLayout->addWidget(pointsWidget);\n\n  mainLayout->addStretch();\n\n  // set up API requests\n  if (auto dongleId = getDongleId()) {\n    QString url = CommaApi::BASE_URL + \"/v1/devices/\" + *dongleId + \"/owner\";\n    RequestRepeater *repeater = new RequestRepeater(this, url, \"ApiCache_Owner\", 6);\n    QObject::connect(repeater, &RequestRepeater::receivedResponse, this, &PrimeUserWidget::replyFinished);\n  }\n}\n\nvoid PrimeUserWidget::replyFinished(const QString &response) {\n  QJsonDocument doc = QJsonDocument::fromJson(response.toUtf8());\n  if (doc.isNull()) {\n    qDebug() << \"JSON Parse failed on getting points\";\n    return;\n  }\n\n  QJsonObject json = doc.object();\n  points->setText(QString::number(json[\"points\"].toInt()));\n}\n\nPrimeAdWidget::PrimeAdWidget(QWidget* parent) : QFrame(parent) {\n  QVBoxLayout* main_layout = new QVBoxLayout(this);\n  main_layout->setContentsMargins(80, 90, 80, 60);\n  main_layout->setSpacing(0);\n\n  QLabel *upgrade = new QLabel(\"Upgrade Now\");\n  upgrade->setStyleSheet(\"font-size: 75px; font-weight: bold;\");\n  main_layout->addWidget(upgrade, 0, Qt::AlignTop);\n  main_layout->addSpacing(50);\n\n  QLabel *description = new QLabel(\"Become a comma prime member at connect.comma.ai\");\n  description->setStyleSheet(\"font-size: 60px; font-weight: light; color: white;\");\n  description->setWordWrap(true);\n  main_layout->addWidget(description, 0, Qt::AlignTop);\n\n  main_layout->addStretch();\n\n  QLabel *features = new QLabel(\"PRIME FEATURES:\");\n  features->setStyleSheet(\"font-size: 41px; font-weight: bold; color: #E5E5E5;\");\n  main_layout->addWidget(features, 0, Qt::AlignBottom);\n  main_layout->addSpacing(30);\n\n  QVector<QString> bullets = {\"Remote access\", \"14 days of storage\", \"Developer perks\"};\n  for (auto &b: bullets) {\n    const QString check = \"<b><font color='#465BEA'>✓</font></b> \";\n    QLabel *l = new QLabel(check + b);\n    l->setAlignment(Qt::AlignLeft);\n    l->setStyleSheet(\"font-size: 50px; margin-bottom: 15px;\");\n    main_layout->addWidget(l, 0, Qt::AlignBottom);\n  }\n\n  setStyleSheet(R\"(\n    PrimeAdWidget {\n      border-radius: 10px;\n      background-color: #333333;\n    }\n  )\");\n}\n\n\nSetupWidget::SetupWidget(QWidget* parent) : QFrame(parent) {\n  mainLayout = new QStackedWidget;\n\n  // Unpaired, registration prompt layout\n\n  QWidget* finishRegistration = new QWidget;\n  finishRegistration->setObjectName(\"primeWidget\");\n  QVBoxLayout* finishRegistationLayout = new QVBoxLayout(finishRegistration);\n  finishRegistationLayout->setContentsMargins(30, 75, 30, 45);\n  finishRegistationLayout->setSpacing(0);\n\n  QLabel* registrationTitle = new QLabel(\"Finish Setup\");\n  registrationTitle->setStyleSheet(\"font-size: 75px; font-weight: bold; margin-left: 55px;\");\n  finishRegistationLayout->addWidget(registrationTitle);\n\n  finishRegistationLayout->addSpacing(30);\n\n  QLabel* registrationDescription = new QLabel(\"Pair your device with comma connect (connect.comma.ai) and claim your comma prime offer.\");\n  registrationDescription->setWordWrap(true);\n  registrationDescription->setStyleSheet(\"font-size: 55px; font-weight: light; margin-left: 55px;\");\n  finishRegistationLayout->addWidget(registrationDescription);\n\n  finishRegistationLayout->addStretch();\n\n  QPushButton* finishButton = new QPushButton(\"Pair device\");\n  finishButton->setFixedHeight(220);\n  finishButton->setStyleSheet(R\"(\n    QPushButton {\n      font-size: 55px;\n      font-weight: 400;\n      border-radius: 10px;\n      background-color: #465BEA;\n    }\n    QPushButton:pressed {\n      background-color: #3049F4;\n    }\n  )\");\n  finishRegistationLayout->addWidget(finishButton);\n  QObject::connect(finishButton, &QPushButton::clicked, this, &SetupWidget::showQrCode);\n\n  mainLayout->addWidget(finishRegistration);\n\n  // Pairing QR code layout\n\n  QWidget* q = new QWidget;\n  q->setObjectName(\"primeWidget\");\n  QVBoxLayout* qrLayout = new QVBoxLayout(q);\n  qrLayout->setContentsMargins(90, 90, 90, 90);\n\n  QLabel* qrLabel = new QLabel(\"Scan the QR code to pair.\");\n  qrLabel->setAlignment(Qt::AlignHCenter);\n  qrLabel->setStyleSheet(\"font-size: 47px; font-weight: light;\");\n  qrLayout->addWidget(qrLabel);\n  qrLayout->addSpacing(50);\n\n  qrLayout->addWidget(new PairingQRWidget);\n  qrLayout->addStretch();\n\n  // setup widget\n  QVBoxLayout *outer_layout = new QVBoxLayout(this);\n  outer_layout->setContentsMargins(0, 0, 0, 0);\n  outer_layout->addWidget(mainLayout);\n\n  mainLayout->addWidget(q);\n\n  primeAd = new PrimeAdWidget;\n  mainLayout->addWidget(primeAd);\n\n  primeUser = new PrimeUserWidget;\n  mainLayout->addWidget(primeUser);\n\n  mainLayout->setCurrentWidget(primeAd);\n\n  setFixedWidth(750);\n  setStyleSheet(R\"(\n    #primeWidget {\n      border-radius: 10px;\n      background-color: #333333;\n    }\n  )\");\n\n  // Retain size while hidden\n  QSizePolicy sp_retain = sizePolicy();\n  sp_retain.setRetainSizeWhenHidden(true);\n  setSizePolicy(sp_retain);\n\n  // set up API requests\n  if (auto dongleId = getDongleId()) {\n    QString url = CommaApi::BASE_URL + \"/v1.1/devices/\" + *dongleId + \"/\";\n    RequestRepeater* repeater = new RequestRepeater(this, url, \"ApiCache_Device\", 5);\n\n    QObject::connect(repeater, &RequestRepeater::receivedResponse, this, &SetupWidget::replyFinished);\n    QObject::connect(repeater, &RequestRepeater::failedResponse, this, &SetupWidget::parseError);\n  }\n  hide(); // Only show when first request comes back\n}\n\nvoid SetupWidget::parseError(const QString &response) {\n  show();\n  if (mainLayout->currentIndex() == 1) {\n    showQr = false;\n    mainLayout->setCurrentIndex(0);\n  }\n}\n\nvoid SetupWidget::showQrCode() {\n  showQr = true;\n  mainLayout->setCurrentIndex(1);\n}\n\nvoid SetupWidget::replyFinished(const QString &response) {\n  show();\n  QJsonDocument doc = QJsonDocument::fromJson(response.toUtf8());\n  if (doc.isNull()) {\n    qDebug() << \"JSON Parse failed on getting pairing and prime status\";\n    return;\n  }\n\n  QJsonObject json = doc.object();\n  if (!json[\"is_paired\"].toBool()) {\n    mainLayout->setCurrentIndex(showQr);\n  } else if (!json[\"prime\"].toBool()) {\n    showQr = false;\n    mainLayout->setCurrentWidget(primeAd);\n  } else {\n    showQr = false;\n    mainLayout->setCurrentWidget(primeUser);\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/prime.h",
    "content": "#pragma once\n\n#include <QLabel>\n#include <QStackedWidget>\n#include <QVBoxLayout>\n#include <QWidget>\n\nclass PairingQRWidget : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit PairingQRWidget(QWidget* parent = 0);\n\nprivate:\n  QLabel* qrCode;\n  void updateQrCode(const QString &text);\n  void showEvent(QShowEvent *event) override;\n\nprivate slots:\n  void refresh();\n};\n\nclass PrimeUserWidget : public QWidget {\n  Q_OBJECT\npublic:\n  explicit PrimeUserWidget(QWidget* parent = 0);\n\nprivate:\n  QVBoxLayout* mainLayout;\n  QLabel* points;\n\nprivate slots:\n  void replyFinished(const QString &response);\n};\n\nclass PrimeAdWidget : public QFrame {\n  Q_OBJECT\npublic:\n  explicit PrimeAdWidget(QWidget* parent = 0);\n};\n\nclass SetupWidget : public QFrame {\n  Q_OBJECT\n\npublic:\n  explicit SetupWidget(QWidget* parent = 0);\n\nprivate:\n  QStackedWidget* mainLayout;\n  PrimeAdWidget *primeAd;\n  PrimeUserWidget *primeUser;\n  bool showQr = false;\n\nprivate slots:\n  void parseError(const QString &response);\n  void replyFinished(const QString &response);\n  void showQrCode();\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/scrollview.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/scrollview.h\"\n\n#include <QScrollBar>\n#include <QScroller>\n\nScrollView::ScrollView(QWidget *w, QWidget *parent) : QScrollArea(parent) {\n  setWidget(w);\n  setWidgetResizable(true);\n  setVerticalScrollBarPolicy(Qt::ScrollBarAlwaysOff);\n  setHorizontalScrollBarPolicy(Qt::ScrollBarAlwaysOff);\n  setStyleSheet(\"background-color: transparent;\");\n\n  QString style = R\"(\n    QScrollBar:vertical {\n      border: none;\n      background: transparent;\n      width: 10px;\n      margin: 0;\n    }\n    QScrollBar::handle:vertical {\n      min-height: 0px;\n      border-radius: 5px;\n      background-color: white;\n    }\n    QScrollBar::add-line:vertical, QScrollBar::sub-line:vertical {\n      height: 0px;\n    }\n    QScrollBar::add-page:vertical, QScrollBar::sub-page:vertical {\n      background: none;\n    }\n  )\";\n  verticalScrollBar()->setStyleSheet(style);\n  horizontalScrollBar()->setStyleSheet(style);\n\n  QScroller *scroller = QScroller::scroller(this->viewport());\n  QScrollerProperties sp = scroller->scrollerProperties();\n\n  sp.setScrollMetric(QScrollerProperties::VerticalOvershootPolicy, QVariant::fromValue<QScrollerProperties::OvershootPolicy>(QScrollerProperties::OvershootAlwaysOff));\n  sp.setScrollMetric(QScrollerProperties::HorizontalOvershootPolicy, QVariant::fromValue<QScrollerProperties::OvershootPolicy>(QScrollerProperties::OvershootAlwaysOff));\n\n  scroller->grabGesture(this->viewport(), QScroller::LeftMouseButtonGesture);\n  scroller->setScrollerProperties(sp);\n}\n\nvoid ScrollView::hideEvent(QHideEvent *e) {\n  verticalScrollBar()->setValue(0);\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/scrollview.h",
    "content": "#pragma once\n\n#include <QScrollArea>\n\nclass ScrollView : public QScrollArea {\n  Q_OBJECT\n\npublic:\n  explicit ScrollView(QWidget *w = nullptr, QWidget *parent = nullptr);\nprotected:\n  void hideEvent(QHideEvent *e) override;\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/ssh_keys.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/ssh_keys.h\"\n\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/ui/qt/api.h\"\n#include \"selfdrive/ui/qt/widgets/input.h\"\n\nSshControl::SshControl() : ButtonControl(\"SSH Keys\", \"\", \"Warning: This grants SSH access to all public keys in your GitHub settings. Never enter a GitHub username other than your own. A comma employee will NEVER ask you to add their GitHub username.\") {\n  username_label.setAlignment(Qt::AlignRight | Qt::AlignVCenter);\n  username_label.setStyleSheet(\"color: #aaaaaa\");\n  hlayout->insertWidget(1, &username_label);\n\n  QObject::connect(this, &ButtonControl::clicked, [=]() {\n    if (text() == \"ADD\") {\n      QString username = InputDialog::getText(\"Enter your GitHub username\", this);\n      if (username.length() > 0) {\n        setText(\"LOADING\");\n        setEnabled(false);\n        getUserKeys(username);\n      }\n    } else {\n      params.remove(\"GithubUsername\");\n      params.remove(\"GithubSshKeys\");\n      refresh();\n    }\n  });\n\n  refresh();\n}\n\nvoid SshControl::refresh() {\n  QString param = QString::fromStdString(params.get(\"GithubSshKeys\"));\n  if (param.length()) {\n    username_label.setText(QString::fromStdString(params.get(\"GithubUsername\")));\n    setText(\"REMOVE\");\n  } else {\n    username_label.setText(\"\");\n    setText(\"ADD\");\n  }\n  setEnabled(true);\n}\n\nvoid SshControl::getUserKeys(const QString &username) {\n  HttpRequest *request = new HttpRequest(this, false);\n  QObject::connect(request, &HttpRequest::receivedResponse, [=](const QString &resp) {\n    if (!resp.isEmpty()) {\n      params.put(\"GithubUsername\", username.toStdString());\n      params.put(\"GithubSshKeys\", resp.toStdString());\n    } else {\n      ConfirmationDialog::alert(\"Username '\" + username + \"' has no keys on GitHub\", this);\n    }\n    refresh();\n    request->deleteLater();\n  });\n  QObject::connect(request, &HttpRequest::failedResponse, [=] {\n    ConfirmationDialog::alert(\"Username '\" + username + \"' doesn't exist on GitHub\", this);\n    refresh();\n    request->deleteLater();\n  });\n  QObject::connect(request, &HttpRequest::timeoutResponse, [=] {\n    ConfirmationDialog::alert(\"Request timed out\", this);\n    refresh();\n    request->deleteLater();\n  });\n\n  request->sendRequest(\"https://github.com/\" + username + \".keys\");\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/ssh_keys.h",
    "content": "#pragma once\n\n#include <QPushButton>\n\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/qt/widgets/controls.h\"\n\n// SSH enable toggle\nclass SshToggle : public ToggleControl {\n  Q_OBJECT\n\npublic:\n  SshToggle() : ToggleControl(\"Enable SSH\", \"\", \"\", Hardware::get_ssh_enabled()) {\n    QObject::connect(this, &SshToggle::toggleFlipped, [=](bool state) {\n      Hardware::set_ssh_enabled(state);\n    });\n  }\n};\n\n// SSH key management widget\nclass SshControl : public ButtonControl {\n  Q_OBJECT\n\npublic:\n  SshControl();\n\nprivate:\n  Params params;\n\n  QLabel username_label;\n\n  void refresh();\n  void getUserKeys(const QString &username);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/toggle.cc",
    "content": "#include \"selfdrive/ui/qt/widgets/toggle.h\"\n\n#include <QPainter>\n\nToggle::Toggle(QWidget *parent) : QAbstractButton(parent),\n_height(80),\n_height_rect(60),\non(false),\n_anim(new QPropertyAnimation(this, \"offset_circle\", this))\n{\n  _radius = _height / 2;\n  _x_circle = _radius;\n  _y_circle = _radius;\n  _y_rect = (_height - _height_rect)/2;\n  circleColor = QColor(0xffffff); // placeholder\n  green = QColor(0xffffff); // placeholder\n  setEnabled(true);\n}\n\nvoid Toggle::paintEvent(QPaintEvent *e) {\n  this->setFixedHeight(_height);\n  QPainter p(this);\n  p.setPen(Qt::NoPen);\n  p.setRenderHint(QPainter::Antialiasing, true);\n\n  // Draw toggle background left\n  p.setBrush(green);\n  p.drawRoundedRect(QRect(0, _y_rect, _x_circle + _radius, _height_rect), _height_rect/2, _height_rect/2);\n\n  // Draw toggle background right\n  p.setBrush(QColor(0x393939));\n  p.drawRoundedRect(QRect(_x_circle - _radius, _y_rect, width() - (_x_circle - _radius), _height_rect), _height_rect/2, _height_rect/2);\n\n  // Draw toggle circle\n  p.setBrush(circleColor);\n  p.drawEllipse(QRectF(_x_circle - _radius, _y_circle - _radius, 2 * _radius, 2 * _radius));\n}\n\nvoid Toggle::mouseReleaseEvent(QMouseEvent *e) {\n  if (!enabled) {\n    return;\n  }\n  const int left = _radius;\n  const int right = width() - _radius;\n  if ((_x_circle != left && _x_circle != right) || !this->rect().contains(e->localPos().toPoint())) {\n    // If mouse release isn't in rect or animation is running, don't parse touch events\n    return;\n  }\n  if (e->button() & Qt::LeftButton) {\n    togglePosition();\n    emit stateChanged(on);\n  }\n}\n\nvoid Toggle::togglePosition() {\n  on = !on;\n  const int left = _radius;\n  const int right = width() - _radius;\n  _anim->setStartValue(on ? left + immediateOffset : right - immediateOffset);\n  _anim->setEndValue(on ? right : left);\n  _anim->setDuration(animation_duration);\n  _anim->start();\n  repaint();\n}\n\nvoid Toggle::enterEvent(QEvent *e) {\n  QAbstractButton::enterEvent(e);\n}\n\nbool Toggle::getEnabled() {\n  return enabled;\n}\n\nvoid Toggle::setEnabled(bool value) {\n  enabled = value;\n  if (value) {\n    circleColor.setRgb(0xfafafa);\n    green.setRgb(0x33ab4c);\n  } else {\n    circleColor.setRgb(0x888888);\n    green.setRgb(0x227722);\n  }\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/widgets/toggle.h",
    "content": "#pragma once\n\n#include <QAbstractButton>\n#include <QMouseEvent>\n#include <QPropertyAnimation>\n\nclass Toggle : public QAbstractButton {\n  Q_OBJECT\n  Q_PROPERTY(int offset_circle READ offset_circle WRITE set_offset_circle CONSTANT)\n\npublic:\n  Toggle(QWidget* parent = nullptr);\n  void togglePosition();\n  bool on;\n  int animation_duration = 150;\n  int immediateOffset = 0;\n  int offset_circle() const {\n    return _x_circle;\n  }\n\n  void set_offset_circle(int o) {\n    _x_circle = o;\n    update();\n  }\n  bool getEnabled();\n  void setEnabled(bool value);\n\nprotected:\n  void paintEvent(QPaintEvent*) override;\n  void mouseReleaseEvent(QMouseEvent*) override;\n  void enterEvent(QEvent*) override;\n\nprivate:\n  QColor circleColor;\n  QColor green;\n  bool enabled = true;\n  int _x_circle, _y_circle;\n  int _height, _radius;\n  int _height_rect, _y_rect;\n  QPropertyAnimation *_anim = nullptr;\n\nsignals:\n  void stateChanged(bool new_state);\n};\n"
  },
  {
    "path": "selfdrive/ui/qt/window.cc",
    "content": "#include \"selfdrive/ui/qt/window.h\"\n\n#include <QFontDatabase>\n\n#include \"selfdrive/hardware/hw.h\"\n\nMainWindow::MainWindow(QWidget *parent) : QWidget(parent) {\n  main_layout = new QStackedLayout(this);\n  main_layout->setMargin(0);\n\n  onboardingWindow = new OnboardingWindow(this);\n  main_layout->addWidget(onboardingWindow);\n  QObject::connect(onboardingWindow, &OnboardingWindow::onboardingDone, [=]() {\n    main_layout->setCurrentWidget(homeWindow);\n  });\n\n  homeWindow = new HomeWindow(this);\n  main_layout->addWidget(homeWindow);\n  QObject::connect(homeWindow, &HomeWindow::openSettings, this, &MainWindow::openSettings);\n  QObject::connect(homeWindow, &HomeWindow::closeSettings, this, &MainWindow::closeSettings);\n  QObject::connect(&qs, &QUIState::uiUpdate, homeWindow, &HomeWindow::update);\n  QObject::connect(&qs, &QUIState::offroadTransition, homeWindow, &HomeWindow::offroadTransition);\n  QObject::connect(&qs, &QUIState::offroadTransition, homeWindow, &HomeWindow::offroadTransitionSignal);\n  QObject::connect(&device, &Device::displayPowerChanged, homeWindow, &HomeWindow::displayPowerChanged);\n\n  settingsWindow = new SettingsWindow(this);\n  main_layout->addWidget(settingsWindow);\n  QObject::connect(settingsWindow, &SettingsWindow::closeSettings, this, &MainWindow::closeSettings);\n  QObject::connect(&qs, &QUIState::offroadTransition, settingsWindow, &SettingsWindow::offroadTransition);\n  QObject::connect(settingsWindow, &SettingsWindow::reviewTrainingGuide, [=]() {\n    main_layout->setCurrentWidget(onboardingWindow);\n  });\n  QObject::connect(settingsWindow, &SettingsWindow::showDriverView, [=] {\n    homeWindow->showDriverView(true);\n  });\n\n  device.setAwake(true, true);\n  QObject::connect(&qs, &QUIState::uiUpdate, &device, &Device::update);\n  QObject::connect(&qs, &QUIState::offroadTransition, [=](bool offroad) {\n    if (!offroad) {\n      closeSettings();\n    }\n  });\n  QObject::connect(&device, &Device::displayPowerChanged, [=]() {\n     if(main_layout->currentWidget() != onboardingWindow) {\n       closeSettings();\n     }\n  });\n\n  // load fonts\n  QFontDatabase::addApplicationFont(\"../assets/fonts/opensans_regular.ttf\");\n  QFontDatabase::addApplicationFont(\"../assets/fonts/opensans_bold.ttf\");\n  QFontDatabase::addApplicationFont(\"../assets/fonts/opensans_semibold.ttf\");\n\n  // no outline to prevent the focus rectangle\n  setStyleSheet(R\"(\n    * {\n      font-family: Inter;\n      outline: none;\n    }\n  )\");\n  setAttribute(Qt::WA_NoSystemBackground);\n}\n\nvoid MainWindow::openSettings() {\n  main_layout->setCurrentWidget(settingsWindow);\n}\n\nvoid MainWindow::closeSettings() {\n  main_layout->setCurrentWidget(homeWindow);\n\n  if (QUIState::ui_state.scene.started) {\n    emit homeWindow->showSidebar(false);\n  }\n}\n\nbool MainWindow::eventFilter(QObject *obj, QEvent *event) {\n  // wake screen on tap\n  if (event->type() == QEvent::MouseButtonPress || event->type() == QEvent::TouchBegin) {\n    device.setAwake(true, true);\n  }\n\n#ifdef QCOM\n  // filter out touches while in android activity\n  const static QSet<QEvent::Type> filter_events({QEvent::MouseButtonPress, QEvent::MouseMove, QEvent::TouchBegin, QEvent::TouchUpdate, QEvent::TouchEnd});\n  if (HardwareEon::launched_activity && filter_events.contains(event->type())) {\n    HardwareEon::check_activity();\n    if (HardwareEon::launched_activity) {\n      return true;\n    }\n  }\n#endif\n  return false;\n}\n"
  },
  {
    "path": "selfdrive/ui/qt/window.h",
    "content": "#pragma once\n\n#include <QStackedLayout>\n#include <QWidget>\n\n#include \"selfdrive/ui/qt/home.h\"\n#include \"selfdrive/ui/qt/offroad/onboarding.h\"\n#include \"selfdrive/ui/qt/offroad/settings.h\"\n\nclass MainWindow : public QWidget {\n  Q_OBJECT\n\npublic:\n  explicit MainWindow(QWidget *parent = 0);\n\nprivate:\n  bool eventFilter(QObject *obj, QEvent *event) override;\n  void openSettings();\n  void closeSettings();\n\n  Device device;\n  QUIState qs;\n\n  QStackedLayout *main_layout;\n  HomeWindow *homeWindow;\n  SettingsWindow *settingsWindow;\n  OnboardingWindow *onboardingWindow;\n};\n"
  },
  {
    "path": "selfdrive/ui/soundd",
    "content": "#!/bin/sh\ncd \"$(dirname \"$0\")\"\nexport LD_LIBRARY_PATH=\"/system/lib64:$LD_LIBRARY_PATH\"\nexec ./_soundd\n"
  },
  {
    "path": "selfdrive/ui/soundd.cc",
    "content": "#include <sys/resource.h>\n\n#include <map>\n\n#include <QApplication>\n#include <QString>\n#include <QSoundEffect>\n\n#include \"cereal/messaging/messaging.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/ui.h\"\n\n// TODO: detect when we can't play sounds\n// TODO: detect when we can't display the UI\n\nclass Sound : public QObject {\npublic:\n  explicit Sound(QObject *parent = 0) {\n    // TODO: merge again and add EQ in the amp config\n    const QString sound_asset_path = Hardware::TICI() ? \"../assets/sounds_tici/\" : \"../assets/sounds/\";\n    std::tuple<AudibleAlert, QString, bool> sound_list[] = {\n      {AudibleAlert::CHIME_DISENGAGE, sound_asset_path + \"disengaged.wav\", false},\n      {AudibleAlert::CHIME_ENGAGE, sound_asset_path + \"engaged.wav\", false},\n      {AudibleAlert::CHIME_WARNING1, sound_asset_path + \"warning_1.wav\", false},\n      {AudibleAlert::CHIME_WARNING2, sound_asset_path + \"warning_2.wav\", false},\n      {AudibleAlert::CHIME_WARNING2_REPEAT, sound_asset_path + \"warning_2.wav\", true},\n      {AudibleAlert::CHIME_WARNING_REPEAT, sound_asset_path + \"warning_repeat.wav\", true},\n      {AudibleAlert::CHIME_ERROR, sound_asset_path + \"error.wav\", false},\n      {AudibleAlert::CHIME_PROMPT, sound_asset_path + \"error.wav\", false}\n    };\n    for (auto &[alert, fn, loops] : sound_list) {\n      QSoundEffect *s = new QSoundEffect(this);\n      QObject::connect(s, &QSoundEffect::statusChanged, this, &Sound::checkStatus);\n      s->setSource(QUrl::fromLocalFile(fn));\n      sounds[alert] = {s, loops ? QSoundEffect::Infinite : 0};\n    }\n\n    sm = new SubMaster({\"carState\", \"controlsState\"});\n\n    QTimer *timer = new QTimer(this);\n    QObject::connect(timer, &QTimer::timeout, this, &Sound::update);\n    timer->start();\n  };\n  ~Sound() {\n    delete sm;\n  };\n\nprivate slots:\n  void checkStatus() {\n    QSoundEffect *s = qobject_cast<QSoundEffect*>(sender());\n    assert(s->status() != QSoundEffect::Error);\n  }\n\n  void update() {\n    sm->update(100);\n    if (sm->updated(\"carState\")) {\n      // scale volume with speed\n      volume = util::map_val((*sm)[\"carState\"].getCarState().getVEgo(), 0.f, 20.f,\n                             Hardware::MIN_VOLUME, Hardware::MAX_VOLUME);\n    }\n    if (sm->updated(\"controlsState\")) {\n      const cereal::ControlsState::Reader &cs = (*sm)[\"controlsState\"].getControlsState();\n      setAlert({QString::fromStdString(cs.getAlertText1()),\n                QString::fromStdString(cs.getAlertText2()),\n                QString::fromStdString(cs.getAlertType()),\n                cs.getAlertSize(), cs.getAlertSound()});\n    } else if (sm->rcv_frame(\"controlsState\") > 0 && (*sm)[\"controlsState\"].getControlsState().getEnabled() &&\n               ((nanos_since_boot() - sm->rcv_time(\"controlsState\")) / 1e9 > CONTROLS_TIMEOUT)) {\n      setAlert(CONTROLS_UNRESPONSIVE_ALERT);\n    }\n  }\n\n  void setAlert(Alert a) {\n    if (!alert.equal(a)) {\n      alert = a;\n      // stop sounds\n      for (auto &[s, loops] : sounds) {\n        // Only stop repeating sounds\n        if (s->loopsRemaining() == QSoundEffect::Infinite) {\n          s->stop();\n        }\n      }\n\n      // play sound\n      if (alert.sound != AudibleAlert::NONE) {\n        auto &[s, loops] = sounds[alert.sound];\n        s->setLoopCount(loops);\n        s->setVolume(volume);\n        s->play();\n      }\n    }\n  }\n\nprivate:\n  Alert alert;\n  float volume = Hardware::MIN_VOLUME;\n  QMap<AudibleAlert, QPair<QSoundEffect*, int>> sounds;\n  SubMaster *sm;\n};\n\nint main(int argc, char **argv) {\n  setpriority(PRIO_PROCESS, 0, -20);\n\n  QApplication a(argc, argv);\n  Sound sound;\n  return a.exec();\n}\n"
  },
  {
    "path": "selfdrive/ui/spinner",
    "content": "#!/bin/sh\n\nif [ -f /EON ] && [ ! -f qt/spinner ]; then\n  cp qt/spinner_aarch64 qt/spinner\nelif [ -f /TICI ] && [ ! -f qt/spinner ]; then\n  cp qt/spinner_larch64 qt/spinner\nelif [ -f /JETSON ] && [ ! -f qt/spinner ]; then\n  cp qt/spinner_larch64 qt/spinner\nfi\n\nexport LD_LIBRARY_PATH=\"/system/lib64:$LD_LIBRARY_PATH\"\nexec ./qt/spinner \"$1\"\n"
  },
  {
    "path": "selfdrive/ui/text",
    "content": "#!/bin/sh\n\nif [ -f /EON ] && [ ! -f qt/text ]; then\n  cp qt/text_aarch64 qt/text\nelif [ -f /TICI ] && [ ! -f qt/text ]; then\n  cp qt/text_larch64 qt/text\nelif [ -f /JETSON ] && [ ! -f qt/text ]; then\n  cp qt/text_larch64 qt/text\nfi\n\nexport LD_LIBRARY_PATH=\"/system/lib64:$LD_LIBRARY_PATH\"\nexec ./qt/text \"$1\"\n"
  },
  {
    "path": "selfdrive/ui/translations/en-US.ts",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<!DOCTYPE TS>\n<TS version=\"2.1\" language=\"en_US\">\n<context>\n    <name>AdvancedNetworking</name>\n    <message>\n        <source>Back</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Tethering</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tethering Password</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>EDIT</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enter new tethering password</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>IP Address</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>DevicePanel</name>\n    <message>\n        <source>Dongle ID</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Serial</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Driver Camera</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>PREVIEW</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Preview the driver facing camera to help optimize device mounting position for best driver monitoring experience. (vehicle must be off)</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>openpilot requires the device to be mounted within 4° left or right and within 5° up or down. openpilot is continuously calibrating, resetting is rarely required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Reset Calibration</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>RESET</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure you want to reset calibration?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> Your device is pointed %1° %2 and %3° %4.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>up</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>down</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>right</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>left</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Review Training Guide</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>REVIEW</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Review the rules, features, and limitations of openpilot</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure you want to review the training guide?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Regulatory</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>VIEW</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Reboot</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure you want to reboot?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Power Off</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure you want to power off?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>DriveStats</name>\n    <message>\n        <source>Drives</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Hours </source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ALL TIME</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>PAST WEEK</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>KM</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Miles</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>Networking</name>\n    <message>\n        <source>Enter password</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>for </source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Wrong password</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Advanced</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>PrimeAdWidget</name>\n    <message>\n        <source>Upgrade Now</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Become a comma prime member at connect.comma.ai</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>PRIME FEATURES:</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Remote access</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>14 days of storage</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Developer perks</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>PrimeUserWidget</name>\n    <message>\n        <source>✓ SUBSCRIBED</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>comma prime</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>COMMA POINTS</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CONNECT.COMMA.AI</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>QObject</name>\n    <message>\n        <source>Auto Shutdown In</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> mins</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Auto Shutdown</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>FOLLOW</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>REL DIST</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>SPT</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>NOR</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ECO</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ACCEL</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>REL SPEED</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>OFF</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ENG RPM</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>REAL STEER</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DESIR STEER</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>openpilot Unavailable</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Waiting for controls to start</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>TAKE CONTROL IMMEDIATELY</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Controls Unresponsive</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to shutdown your device after the wait period specified.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to shutdown your device automatically.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>QWidget</name>\n    <message>\n        <source>Services</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Updater Service</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Reboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Log Service</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Uploader Service</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Athenad Service</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable On-Road Dashcam</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Appd Service</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable GPS Logger</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>This will store your track in /sdcard/gpx_logs/.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Camera Offset</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Hotspot On Boot</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable No Battery Support</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this option if your device does not have a battery.\nDo not use this if you have a C2, Reboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable White/Grey Panda Support</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this option ONLY on white / grey panda.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable No GPS Panda Support</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this option ONLY on Non-GPS Pandas.\nThis will need to recompile boardd (takes a while).\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Jetson Support</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this option if you intend to run dp on Nvidia Jetson.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Mark As Prebuilt</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Prebuilt Creates a file and improves boot speed.\nWARNING: You may need to disable it once switch to a new version.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>FLASH</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>RECOVER</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DELETE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ALCA Delay</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> secs</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ALCA Min Speed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> mph</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Cont. ALCA</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>LCA Min Speed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Blinker Off Recovery Delay</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Seconds after blinker off then OP will take back control.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Lateral Ctrl Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>0 = No Lateral Ctrl On Blinkers\n1 = Lane Change Assist (LCA)\n2 = Auto Lane Change Assist (ALCA)</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Allow Gas Pedal Pressed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Gear Safety Check</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Steering Ratio</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust to &lt; 10 to reset to stock value.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>RESET</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Steering Ratio Learner</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Use LQR Controller</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Driving Path Offset</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> cm</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Device Temp Check</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Max Ctrl Speed Check</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Mode</source>\n        <comment>0 = Default\n1 = Screen Off While Reversing\n2 = Screen Off While Driving</comment>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Screen Brightness</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>AUTO</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Alert Volume</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Speed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Lane Prediction</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Lead Car Indicator</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Event / Steer Icon</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Max Speed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Driver Monitor Indicator</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Side Info</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Top Info Bar</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>LAUNCH</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>If your current speed is greater than &apos;Override To&apos; but lower than &apos;Override At&apos;, it will use your current speed instead.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Turn On Cruise Speed Override</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable SnG Mod</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable ZSS Support</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable No Relay Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this will disable relay in your panda.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable EPS Mod Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this will increase steering, USE IT ONLY if you have a modded EPS firmware.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Force to display km/h in HUD</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if your HUD does not display km/h unit.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Smart MDPS Support</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this will increase steering and allow steering down to to 0.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable J533 + White Panda Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Credit to jyoung8607.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Timebomb Assist</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Hardware - General</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Hardware - Panda</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Reboot recommended.\nReboot?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Miscellaneous</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Flashing Panda Firmware</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Pandas Firmware Recovery</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Delete All Driving Log</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Longitudinal</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Lateral</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Language</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Volume</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Date/Time</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Assign Car Model:</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Toyota / Lexus</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Honda</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Hyundai / Kia / Genesis</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Volkswagen</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Lexus RX Low Gear/High RPM Fix</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>See: https://github.com/LexusRXopenpilotUG/openpilot\nCredit to @nelsonchen &amp; @sumedhekaru\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>OPEN</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tethering Settings</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>WiFi Settings</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Fan Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>0 = Default\n1 = Quiet\n2 = Full Speed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tap the button to update your panda firmware.\nThe device should reboot once if it finish updating.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tap the button ONLY if your panda ran into issue.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tap the button to delete ALL your driving logs.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Once the vehicle meets all ALCA criteria, it will wait for the seconds set here before peforming lane change automatically.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Once enabled, it will perform ALCA continuously.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to get automatic update.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to log your drive.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to upload your driving log.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to use cloud services such as comma prime.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to record screen, just like a dashcam.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to run your own android app.\nSee /data/openpilot/selfdrive/dragonpilot/HOWTO-APPD.md for more information.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust your camera position if your device is not mounted as per guidance.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ALCA minimum engage speed in mph.\n1 mph = 1.61 km/h.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>LCA minimum engage speed in mph.\n1 mph = 1.61 km/h.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish openpilot to stay engaged when gas is pressed.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish openpilot to only work on D drive.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to use LQR instead of PID or INDI controller.\nWORKS WELL ONLY ON SOME VEHICLES.\nMore linear steering experience.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust this if you wish to let openpilot drive slightly towards to left (+) or right (-)</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust your screen brightness.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust your alert volume.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display the lane/path prediction.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display the triangle lead car indicator.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Turn Signal / Blinkers</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display turn signals.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display the icon.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display your current SET cruise speed.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display steering angle / lead car distance / engine RPM.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display time / system temp / battery level.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Override Speed When Below</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Override feature will be enabled when set cruise speed is lower than this value.\n1 km/h = 0.62 mph.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> km/h</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Override Speed To</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Override set speed to this value.\n1 km/h = 0.62 mph</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Use Current Speed</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to fix stop and go (SnG) issue on some models.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you have ZSS module installed.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to assist you the 6 mins. LKA limit on some models.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display your current speed.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Manually Control Accel Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to adjust openpilot&apos;s acceleration control.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Manually Control Following Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to adjust openpilot&apos;s following distance.\nopenpilot by default keeps 1.8 secs distance to lead car.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable FM Physical Button Ctrl</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to link Following Mode (FM) control to the physical button.\nONLY WORK ON SOME VEHICLES.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable AM Physical Button Ctrl</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to link Accel Mode (AM) control to the physical button.\nONLY WORK ON SOME VEHICLES.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>SettingsWindow</name>\n    <message>\n        <source>Device</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Network</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Toggles</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Software</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DP - General</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DP - Controls</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DP - UI</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DP - Cars</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Navigation</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>BACK</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>SetupWidget</name>\n    <message>\n        <source>Finish Setup</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Pair your device with comma connect (connect.comma.ai) and claim your comma prime offer.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Pair device</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Scan the QR code to pair.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>Sidebar</name>\n    <message>\n        <source>PANDA\nONLINE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>PANDA\nOFFLINE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>NO\nPRIME</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CONNECT\nOFFLINE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CONNECT\nONLINE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CONNECT\nERROR</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>SATS\nSEARCHING</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>SATS: %1\n%2 m</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>TEMP</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>SoftwarePanel</name>\n    <message>\n        <source>failed to fetch update</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CHECK</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Git Branch</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Git Commit</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>OS Version</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Version</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Last Update Check</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>The last time openpilot successfully checked for an update. The updater only runs while the car is off.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Check for Update</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CHECKING</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Uninstall </source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>UNINSTALL</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure you want to uninstall?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>SshControl</name>\n    <message>\n        <source>Enter your GitHub username</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>REMOVE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ADD</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Warning: This grants SSH access to all public keys in your GitHub settings. Never enter a GitHub username other than your own. A comma employee will NEVER ask you to add their GitHub username.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>TogglesPanel</name>\n    <message>\n        <source>Use the openpilot system for adaptive cruise control and lane keep driver assistance. Your attention is required at all times to use this feature. Changing this setting takes effect when the car is powered off.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Lane Departure Warnings</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Receive alerts to steer back into the lane when your vehicle drifts over a detected lane line without a turn signal activated while driving over 31mph (50kph).</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Right-Hand Drive</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Allow openpilot to obey left-hand traffic conventions and perform driver monitoring on right driver seat.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Use Metric System</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display speed in km/h instead of mp/h.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Community Features</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Use features from the open source community that are not maintained or supported by comma.ai and have not been confirmed to meet the standard safety model. These features include community supported cars and community supported hardware. Be extra cautious when using these features</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Upload Raw Logs</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Upload full logs and full resolution video by default while on WiFi. If not enabled, individual logs can be marked for upload at my.comma.ai/useradmin.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Record and Upload Driver Camera</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Upload data from the driver facing camera and help improve the driver monitoring algorithm.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>塞 Disable use of lanelines (Alpha) 塞</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>In this mode openpilot will ignore lanelines and just drive how it thinks a human would.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Show ETA in 24h format</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Use 24h format instead of am/pm</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable openpilot</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>WifiUI</name>\n    <message>\n        <source>Scanning for networks...</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>CONNECTING...</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>FORGET</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Forget WiFi Network &quot;</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n</TS>\n"
  },
  {
    "path": "selfdrive/ui/translations/zh-CN.ts",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<!DOCTYPE TS>\n<TS version=\"2.1\" language=\"zh_CN\">\n<context>\n    <name>AdvancedNetworking</name>\n    <message>\n        <source>Back</source>\n        <translation>返回</translation>\n    </message>\n    <message>\n        <source>Enable Tethering</source>\n        <translation>启用热点</translation>\n    </message>\n    <message>\n        <source>Tethering Password</source>\n        <translation>热点密码</translation>\n    </message>\n    <message>\n        <source>EDIT</source>\n        <translation>编辑</translation>\n    </message>\n    <message>\n        <source>Enter new tethering password</source>\n        <translation>输入新的密码</translation>\n    </message>\n    <message>\n        <source>IP Address</source>\n        <translation>IP地址</translation>\n    </message>\n</context>\n<context>\n    <name>DevicePanel</name>\n    <message>\n        <source>Dongle ID</source>\n        <translation></translation>\n    </message>\n    <message>\n        <source>Serial</source>\n        <translation>序列号</translation>\n    </message>\n    <message>\n        <source>Driver Camera</source>\n        <translation>驾驶监控画面</translation>\n    </message>\n    <message>\n        <source>PREVIEW</source>\n        <translation>预览</translation>\n    </message>\n    <message>\n        <source>Preview the driver facing camera to help optimize device mounting position for best driver monitoring experience. (vehicle must be off)</source>\n        <translation>预览面向驾驶员的摄像头，以帮助优化设备安装位置，获得最佳的驾驶员监控体验。（引擎必须熄火）</translation>\n    </message>\n    <message>\n        <source>openpilot requires the device to be mounted within 4° left or right and within 5° up or down. openpilot is continuously calibrating, resetting is rarely required.</source>\n        <translation>openpilot 需要将设备固定在左右偏差 4° 以内，上下偏差 5° 以内。摄像头在后台持续自动校准，很少有需要重置的情况。</translation>\n    </message>\n    <message>\n        <source>Reset Calibration</source>\n        <translation>重置校准</translation>\n    </message>\n    <message>\n        <source>RESET</source>\n        <translation>重置</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to reset calibration?</source>\n        <translation>您确定要重置校准吗？</translation>\n    </message>\n    <message>\n        <source> Your device is pointed %1° %2 and %3° %4.</source>\n        <translation> 你的设备目前朝%2 %1° 以及朝%4 %3° 。</translation>\n    </message>\n    <message>\n        <source>up</source>\n        <translation>上</translation>\n    </message>\n    <message>\n        <source>down</source>\n        <translation>下</translation>\n    </message>\n    <message>\n        <source>right</source>\n        <translation>右</translation>\n    </message>\n    <message>\n        <source>left</source>\n        <translation>左</translation>\n    </message>\n    <message>\n        <source>Review Training Guide</source>\n        <translation>回顾使用手册</translation>\n    </message>\n    <message>\n        <source>REVIEW</source>\n        <translation>回顾</translation>\n    </message>\n    <message>\n        <source>Review the rules, features, and limitations of openpilot</source>\n        <translation>查看 Openpilot 使用条款、特性和局限性。</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to review the training guide?</source>\n        <translation>确定重新回顾使用手册吗？</translation>\n    </message>\n    <message>\n        <source>Regulatory</source>\n        <translation>监管</translation>\n    </message>\n    <message>\n        <source>VIEW</source>\n        <translation>显示</translation>\n    </message>\n    <message>\n        <source>Reboot</source>\n        <translation>重新启动</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to reboot?</source>\n        <translation>确定要重新启动吗？</translation>\n    </message>\n    <message>\n        <source>Power Off</source>\n        <translation>关机</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to power off?</source>\n        <translation>确定要关机吗？</translation>\n    </message>\n</context>\n<context>\n    <name>DriveStats</name>\n    <message>\n        <source>Drives</source>\n        <translation>行程</translation>\n    </message>\n    <message>\n        <source>Hours </source>\n        <translation>小时 </translation>\n    </message>\n    <message>\n        <source>ALL TIME</source>\n        <translation>全部</translation>\n    </message>\n    <message>\n        <source>PAST WEEK</source>\n        <translation>上周</translation>\n    </message>\n    <message>\n        <source>KM</source>\n        <translation>公里</translation>\n    </message>\n    <message>\n        <source>Miles</source>\n        <translation>英里</translation>\n    </message>\n</context>\n<context>\n    <name>Networking</name>\n    <message>\n        <source>Enter password</source>\n        <translation>输入密码</translation>\n    </message>\n    <message>\n        <source>for </source>\n        <translation></translation>\n    </message>\n    <message>\n        <source>Wrong password</source>\n        <translation>密码错误</translation>\n    </message>\n    <message>\n        <source>Advanced</source>\n        <translation>高级</translation>\n    </message>\n</context>\n<context>\n    <name>NvgWindow</name>\n    <message>\n        <source>FOLLOW</source>\n        <translation>车距</translation>\n    </message>\n    <message>\n        <source>REL DIST</source>\n        <translation>真实车距</translation>\n    </message>\n</context>\n<context>\n    <name>PrimeAdWidget</name>\n    <message>\n        <source>Upgrade Now</source>\n        <translation>马上升级</translation>\n    </message>\n    <message>\n        <source>Become a comma prime member at connect.comma.ai</source>\n        <translation>成为 connect.comma.ai 的高级会员</translation>\n    </message>\n    <message>\n        <source>PRIME FEATURES:</source>\n        <translation>高级会员特点：</translation>\n    </message>\n    <message>\n        <source>Remote access</source>\n        <translation>远程访问</translation>\n    </message>\n    <message>\n        <source>14 days of storage</source>\n        <translation>14 天云端行车记录</translation>\n    </message>\n    <message>\n        <source>Developer perks</source>\n        <translation>开发者特权</translation>\n    </message>\n</context>\n<context>\n    <name>PrimeUserWidget</name>\n    <message>\n        <source>✓ SUBSCRIBED</source>\n        <translation>✓ 已订阅</translation>\n    </message>\n    <message>\n        <source>comma prime</source>\n        <translation>comma 高级会员</translation>\n    </message>\n    <message>\n        <source>COMMA POINTS</source>\n        <translation>COMMA 点数</translation>\n    </message>\n    <message>\n        <source>CONNECT.COMMA.AI</source>\n        <translation>CONNECT.COMMA.AI</translation>\n    </message>\n</context>\n<context>\n    <name>QObject</name>\n    <message>\n        <source>Auto Shutdown In</source>\n        <translation></translation>\n    </message>\n    <message>\n        <source> mins</source>\n        <translation> 分钟</translation>\n    </message>\n    <message>\n        <source>Enable Auto Shutdown</source>\n        <translation>启用自动关机</translation>\n    </message>\n    <message>\n        <source>FOLLOW</source>\n        <translation>刹车时间</translation>\n    </message>\n    <message>\n        <source>REL DIST</source>\n        <translation>车距</translation>\n    </message>\n    <message>\n        <source>../assets/fonts/opensans_regular.ttf</source>\n        <translation>/system/fonts/NotoSansTC-Light.otf</translation>\n    </message>\n    <message>\n        <source>../assets/fonts/opensans_semibold.ttf</source>\n        <translation>/system/fonts/NotoSansTC-Regular.otf</translation>\n    </message>\n    <message>\n        <source>../assets/fonts/opensans_bold.ttf</source>\n        <translation>/system/fonts/NotoSansTC-Bold.otf</translation>\n    </message>\n    <message>\n        <source>SPT</source>\n        <translation>运动</translation>\n    </message>\n    <message>\n        <source>NOR</source>\n        <translation>普通</translation>\n    </message>\n    <message>\n        <source>ECO</source>\n        <translation>经济</translation>\n    </message>\n    <message>\n        <source>ACCEL</source>\n        <translation>加速模式</translation>\n    </message>\n    <message>\n        <source>REL SPEED</source>\n        <translation>速度</translation>\n    </message>\n    <message>\n        <source>OFF</source>\n        <translation>停机</translation>\n    </message>\n    <message>\n        <source>ENG RPM</source>\n        <translation>发动机</translation>\n    </message>\n    <message>\n        <source>REAL STEER</source>\n        <translation>实际转向</translation>\n    </message>\n    <message>\n        <source>DESIR STEER</source>\n        <translation>预测转向</translation>\n    </message>\n    <message>\n        <source>openpilot Unavailable</source>\n        <translation>Openpilot不可用</translation>\n    </message>\n    <message>\n        <source>Waiting for controls to start</source>\n        <translation>等待控制系统启动</translation>\n    </message>\n    <message>\n        <source>TAKE CONTROL IMMEDIATELY</source>\n        <translation>马上接管</translation>\n    </message>\n    <message>\n        <source>Controls Unresponsive</source>\n        <translation>系统无响应</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to shutdown your device after the wait period specified.</source>\n        <translation>设置定时关闭设备</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to shutdown your device automatically.</source>\n        <translation>自动关机</translation>\n    </message>\n</context>\n<context>\n    <name>QWidget</name>\n    <message>\n        <source>Services</source>\n        <translation>服务</translation>\n    </message>\n    <message>\n        <source>Enable Updater Service</source>\n        <translation>启用更新服务</translation>\n    </message>\n    <message>\n        <source>Reboot required.</source>\n        <translation>重启后生效。</translation>\n    </message>\n    <message>\n        <source>Enable Log Service</source>\n        <translation>启用记录服务</translation>\n    </message>\n    <message>\n        <source>Enable Uploader Service</source>\n        <translation>启用上传服务</translation>\n    </message>\n    <message>\n        <source>Enable Athenad Service</source>\n        <translation>启用云服务</translation>\n    </message>\n    <message>\n        <source>Enable On-Road Dashcam</source>\n        <translation>启用屏幕录像</translation>\n    </message>\n    <message>\n        <source>Enable Appd Service</source>\n        <translation>启用安卓应用服务</translation>\n    </message>\n    <message>\n        <source>Enable GPS Logger</source>\n        <translation>启用GPS记录</translation>\n    </message>\n    <message>\n        <source>This will store your track in /sdcard/gpx_logs/.\nReboot required.</source>\n        <translation>存在位置/sdcard/gpx_logs/。重启后生效</translation>\n    </message>\n    <message>\n        <source>Camera Offset</source>\n        <translation>相机偏移</translation>\n    </message>\n    <message>\n        <source>Enable Hotspot On Boot</source>\n        <translation>开机启动网络热点</translation>\n    </message>\n    <message>\n        <source>Enable No Battery Support</source>\n        <translation>启用无电池支持</translation>\n    </message>\n    <message>\n        <source>Enable this option if your device does not have a battery.\nDo not use this if you have a C2, Reboot required.</source>\n        <translation>如果你的设备没可以启用这个选项(C2不要使用)，重启后生效</translation>\n    </message>\n    <message>\n        <source>Enable White/Grey Panda Support</source>\n        <translation>老熊模式(白熊/灰熊)</translation>\n    </message>\n    <message>\n        <source>Enable this option ONLY on white / grey panda.\nReboot required.</source>\n        <translation>如果你是白熊或灰熊，请打开这个选项</translation>\n    </message>\n    <message>\n        <source>Enable No GPS Panda Support</source>\n        <translation>无GPS芯片支持</translation>\n    </message>\n    <message>\n        <source>Enable this option ONLY on Non-GPS Pandas.\nThis will need to recompile boardd (takes a while).\nReboot required.</source>\n        <translation></translation>\n    </message>\n    <message>\n        <source>Enable Jetson Support</source>\n        <translation>启用 Jetson 支持</translation>\n    </message>\n    <message>\n        <source>Enable this option if you intend to run dp on Nvidia Jetson.\nReboot required.</source>\n        <translation>如果您打算在 Nvidia Jetson 上运行 dp，请启用此选项。\n需要重新启动。</translation>\n    </message>\n    <message>\n        <source>Mark As Prebuilt</source>\n        <translation>启用预编译</translation>\n    </message>\n    <message>\n        <source>Prebuilt Creates a file and improves boot speed.\nWARNING: You may need to disable it once switch to a new version.</source>\n        <translation>预编译可以加快启动速度（如果升级新版本需要关闭后再升级）</translation>\n    </message>\n    <message>\n        <source>FLASH</source>\n        <translation>刷写</translation>\n    </message>\n    <message>\n        <source>DELETE</source>\n        <translation>删除</translation>\n    </message>\n    <message>\n        <source>ALCA Delay</source>\n        <translation>自动变道延迟</translation>\n    </message>\n    <message>\n        <source> secs</source>\n        <translation> 秒</translation>\n    </message>\n    <message>\n        <source>ALCA Min Speed</source>\n        <translation>自动换道最低启用速度</translation>\n    </message>\n    <message>\n        <source> mph</source>\n        <translation> mph</translation>\n    </message>\n    <message>\n        <source>Enable Cont. ALCA</source>\n        <translation>启用连续自动换道</translation>\n    </message>\n    <message>\n        <source>LCA Min Speed</source>\n        <translation>辅助换道最低启用速度</translation>\n    </message>\n    <message>\n        <source>Blinker Off Recovery Delay</source>\n        <translation>无盲区恢复延时</translation>\n    </message>\n    <message>\n        <source>Seconds after blinker off then OP will take back control.</source>\n        <translation>盲区无车后关闭几秒钟后，OP将收回控制权。</translation>\n    </message>\n    <message>\n        <source>Lateral Ctrl Mode</source>\n        <translation>变道模式</translation>\n    </message>\n    <message>\n        <source>0 = No Lateral Ctrl On Blinkers\n1 = Lane Change Assist (LCA)\n2 = Auto Lane Change Assist (ALCA)</source>\n        <translation>0 = 不启用\n1 = 辅助变道\n2=自动变道</translation>\n    </message>\n    <message>\n        <source>Use Accel Profile</source>\n        <translation>使用加速模板</translation>\n    </message>\n    <message>\n        <source>Use Following Profile</source>\n        <translation>使用跟车模板</translation>\n    </message>\n    <message>\n        <source>Allow Gas Pedal Pressed</source>\n        <translation>允许踩油门</translation>\n    </message>\n    <message>\n        <source>Enable Gear Safety Check</source>\n        <translation>启用档位安全检查</translation>\n    </message>\n    <message>\n        <source>Steering Ratio</source>\n        <translation>转向比</translation>\n    </message>\n    <message>\n        <source>Adjust to &lt; 10 to reset to stock value.</source>\n        <translation> 当值&lt;10 时重置值为原车值?_?</translation>\n    </message>\n    <message>\n        <source>RESET</source>\n        <translation>重置</translation>\n    </message>\n    <message>\n        <source>Enable Steering Ratio Learner</source>\n        <translation>启用转向比学习</translation>\n    </message>\n    <message>\n        <source>Use LQR Controller</source>\n        <translation>使用LQR控制器</translation>\n    </message>\n    <message>\n        <source>Driving Path Offset</source>\n        <translation>车道偏移</translation>\n    </message>\n    <message>\n        <source> cm</source>\n        <translation> cm</translation>\n    </message>\n    <message>\n        <source>Enable Device Temp Check</source>\n        <translation>启用温度监控</translation>\n    </message>\n    <message>\n        <source>Enable Max Ctrl Speed Check</source>\n        <translation>启用最大控制速度监控</translation>\n    </message>\n    <message>\n        <source>Display Mode</source>\n        <comment>0 = Default\n1 = Screen Off While Reversing\n2 = Screen Off While Driving</comment>\n        <translation>屏幕显示模式</translation>\n    </message>\n    <message>\n        <source>0 = Default\n1 = Screen Off While Reversing\n2 = Screen Off While Driving</source>\n        <translation>0 = 常亮\n1 = 倒车时关闭屏幕\n2 = 行车时关闭屏幕</translation>\n    </message>\t\n    <message>\n        <source>Screen Brightness</source>\n        <translation>屏幕亮度</translation>\n    </message>\n    <message>\n        <source>AUTO</source>\n        <translation>自动</translation>\n    </message>\n    <message>\n        <source>Alert Volume</source>\n        <translation>警告音量</translation>\n    </message>\n    <message>\n        <source>Display Speed</source>\n        <translation>显示行车速度</translation>\n    </message>\n    <message>\n        <source>Display Lane Prediction</source>\n        <translation>显示车道线预测</translation>\n    </message>\n    <message>\n        <source>Display Lead Car Indicator</source>\n        <translation>显示前车标记△</translation>\n    </message>\n    <message>\n        <source>Display Turn Signal / Blinkers</source>\n        <translation>显示转向灯/盲区显示</translation>\n    </message>\n    <message>\n        <source>Display Event / Steer Icon</source>\n        <translation>显示事件/转向图标</translation>\n    </message>\n    <message>\n        <source>Display Max Speed</source>\n        <translation>显示巡航速度</translation>\n    </message>\n    <message>\n        <source>Display Driver Monitor Indicator</source>\n        <translation>显示驾驶员监控标志</translation>\n    </message>\n    <message>\n        <source>Display Side Info</source>\n        <translation>显示侧边信息框</translation>\n    </message>\n    <message>\n        <source>Display Top Info</source>\n        <translation>显示顶部信息条</translation>\n    </message>\n    <message>\n        <source>LAUNCH</source>\n        <translation>运行</translation>\n    </message>\n    <message>\n        <source>Override At</source>\n        <translation>低速重写</translation>\n    </message>\n    <message>\n        <source>Override Speed When Below</source>\n        <translation>低于此速度将会触发重写</translation>\n    </message>\n    <message>\n        <source>Override feature will be enabled when set cruise speed is lower than this value.\n1 km/h = 0.62 mph.</source>\n        <translation>当设定巡航速度低于此值时，将启用重写功能\n1 km/h = 0.62 mph</translation>\n    </message>\n    <message>\n        <source>Override Speed To</source>\n        <translation>重写至</translation>\n    </message>\n    <message>\n        <source>Override set speed to this value.\n1 km/h = 0.62 mph</source>\n        <translation>将设定速度重写到此值。\n1 km/h = 0.62 mph</translation>\n    </message>\n    <message>\n        <source>If your current speed is greater than &apos;Override To&apos; but lower than &apos;Override At&apos;, it will use your current speed instead.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Turn On Cruise Speed Override</source>\n        <translation>启用低速重写</translation>\n    </message>\n    <message>\n        <source>Enable SnG Mod</source>\n        <translation>启用自动跟车补丁</translation>\n    </message>\n    <message>\n        <source>Enable ZSS Support</source>\n        <translation>启用ZSS支持</translation>\n    </message>\n    <message>\n        <source>Enable FM Physical Button Ctrl</source>\n        <translation>启用跟车模板按钮关联</translation>\n    </message>\n    <message>\n        <source>Enable AM Physical Button Ctrl</source>\n        <translation>启用加速模板按钮关联</translation>\n    </message>\n    <message>\n        <source>Enable No Relay Mode</source>\n        <translation>关闭继电器切换</translation>\n    </message>\n    <message>\n        <source>Enable this will disable relay in your panda.\nReboot required.</source>\n        <translation>开启这个选择将会关闭熊猫自动切换继电器</translation>\n    </message>\n    <message>\n        <source>Enable EPS Mod Mode</source>\n        <translation>启用EPS Mod增强</translation>\n    </message>\n    <message>\n        <source>Enable this will increase steering, USE IT ONLY if you have a modded EPS firmware.\nReboot required.</source>\n        <translation>启用这将增加转向，仅当您有改装的 EPS 固件时才使用它。\n需要重新启动。</translation>\n    </message>\n    <message>\n        <source>Force to display km/h in HUD</source>\n        <translation>强制在HUD上显示KM/H</translation>\n    </message>\n    <message>\n        <source>Enable this if your HUD does not display km/h unit.\nReboot required.</source>\n        <translation>如果你的HUD不显示KM/H单位，请打开这个选项</translation>\n    </message>\n    <message>\n        <source>Enable Smart MDPS Support</source>\n        <translation>启用智能 MDPS 支持</translation>\n    </message>\n    <message>\n        <source>Enable this will increase steering and allow steering down to to 0.\nReboot required.</source>\n        <translation>启用这将增加转向并允许转向下降到 0。\n需要重新启动。</translation>\n    </message>\n    <message>\n        <source>Enable J533 + White Panda Mode</source>\n        <translation>启用J533+白熊支持</translation>\n    </message>\n    <message>\n        <source>Credit to jyoung8607.\nReboot required.</source>\n        <translation>作者jyoung8607。\n需要重启</translation>\n    </message>\n    <message>\n        <source>Enable Timebomb Assist</source>\n        <translation>启用VW6分钟辅助</translation>\n    </message>\n    <message>\n        <source>Hardware - General</source>\n        <translation>设备-通用</translation>\n    </message>\n    <message>\n        <source>Hardware - Panda</source>\n        <translation>设备-Panda</translation>\n    </message>\n    <message>\n        <source>Reboot recommended.\nReboot?</source>\n        <translation>建议重启。\n重启？</translation>\n    </message>\n    <message>\n        <source>Miscellaneous</source>\n        <translation>其它</translation>\n    </message>\n    <message>\n        <source>Flashing Panda Firmware</source>\n        <translation>刷入Panda固件</translation>\n    </message>\n    <message>\n        <source>Are you sure?</source>\n        <translation>是否确认？</translation>\n    </message>\n    <message>\n        <source>Pandas Firmware Recovery</source>\n        <translation>Panda固件恢复</translation>\n    </message>\n    <message>\n        <source>Delete All Driving Log</source>\n        <translation>删除所有驾驶日志</translation>\n    </message>\n    <message>\n        <source>Longitudinal</source>\n        <translation>纵向</translation>\n    </message>\n    <message>\n        <source>Lateral</source>\n        <translation>横向</translation>\n    </message>\n    <message>\n        <source>Language</source>\n        <translation>系统语言</translation>\n    </message>\n    <message>\n        <source>Volume</source>\n        <translation>系统音量</translation>\n    </message>\n    <message>\n        <source>Date/Time</source>\n        <translation>系统时间</translation>\n    </message>\n    <message>\n        <source>Assign Car Model:</source>\n        <translation>指定车型：</translation>\n    </message>\n    <message>\n        <source>Toyota / Lexus</source>\n        <translation>丰田/雷克萨斯</translation>\n    </message>\n    <message>\n        <source>Honda</source>\n        <translation>本田</translation>\n    </message>\n    <message>\n        <source>Hyundai / Kia / Genesis</source>\n        <translation>现代/起亚/捷尼赛思</translation>\n    </message>\n    <message>\n        <source>Volkswagen</source>\n        <translation>大众</translation>\n    </message>\n    <message>\n        <source>Enable Lexus RX Low Gear/High RPM Fix</source>\n        <translation>启用 Lexus RX 低档/高转速 修正</translation>\n    </message>\n    <message>\n        <source>See: https://github.com/LexusRXopenpilotUG/openpilot\nCredit to @nelsonchen &amp; @sumedhekaru\nReboot required.</source>\n        <translation>参见：https://github.com/LexusRXopenpilotUG/openpilot\nvia @nelsonchen @sumedhekaru\n需要重新启动。</translation>\n    </message>\n    <message>\n        <source>OPEN</source>\n        <translation>打开</translation>\n    </message>\n    <message>\n        <source>Tethering Settings</source>\n        <translation>热点设置</translation>\n    </message>\n    <message>\n        <source>WiFi Settings</source>\n        <translation>WiFi设置</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to get automatic update.\nReboot required.</source>\n        <translation>自动升级，重启后生效。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to log your drive.\nReboot required.</source>\n        <translation>记录服务，重启后生效。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to upload your driving log.\nReboot required.</source>\n        <translation>上传日志，重启后生效。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to use cloud services such as comma prime.\nReboot required.</source>\n        <translation>云服务(需要COMMA会员),重启后生效。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to record screen, just like a dashcam.\nReboot required.</source>\n        <translation>屏幕录像(/sdcard/dashcam)，重启后生效。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to run your own android app.\nSee /data/openpilot/selfdrive/dragonpilot/HOWTO-APPD.md for more information.\nReboot required.</source>\n        <translation>使用安卓APP，重启后生效。\n/data/openpilot/selfdrive/dragonpilot/HOWTO-APPD.md</translation>\n    </message>\n    <message>\n        <source>Fan Mode</source>\n        <translation>散热风扇模式</translation>\n    </message>\n    <message>\n        <source>0 = Default\n1 = Quiet\n2 = Full Speed</source>\n        <translation>0 = 默认\n1 = 静音\n2 = 全速</translation>\n    </message>\n    <message>\n        <source>Tap the button to update your panda firmware.\nThe device should reboot once if it finish updating.</source>\n        <translation>点击按钮更新您的熊猫固件。\n如果完成更新，设备应重新启动一次。</translation>\n    </message>\n    <message>\n        <source>RECOVER</source>\n        <translation>刷写</translation>\n    </message>\n    <message>\n        <source>Tap the button ONLY if your panda ran into issue.</source>\n        <translation>仅当您的熊猫遇到问题时才点击按钮</translation>\n    </message>\n    <message>\n        <source>Tap the button to delete ALL your driving logs.</source>\n        <translation>删除所有行车记录信息</translation>\n    </message>\n    <message>\n        <source>Once the vehicle meets all ALCA criteria, it will wait for the seconds set here before peforming lane change automatically.</source>\n        <translation>一旦车辆满足所有 自动辅助变道 条件，它将等待此处设置的秒数，然后自动执行车道变换。</translation>\n    </message>\n    <message>\n        <source>ALCA minimum engage speed in mph.\n1 mph = 1.61 km/h.</source>\n        <translation>自动辅助变道最低接合速度（英里/小时）\n1 mph = 1.61 km/h</translation>\n    </message>\n    <message>\n        <source>Once enabled, it will perform ALCA continuously.</source>\n        <translation>一旦启用，它将连续执行 自动辅助变道。</translation>\n    </message>\n    <message>\n        <source>LCA minimum engage speed in mph.\n1 mph = 1.61 km/h.</source>\n        <translation>辅助变道 最低接合速度（英里/小时）。\n1 英里/小时 = 1.61 公里/小时。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish openpilot to stay engaged when gas is pressed.</source>\n        <translation>踩油门不退出Openpilot</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish openpilot to only work on D drive.</source>\n        <translation>如果您希望 openpilot 仅在 D 档启用，请启用此选项。</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to use LQR instead of PID or INDI controller.\nWORKS WELL ONLY ON SOME VEHICLES.\nMore linear steering experience.</source>\n        <translation>如果您希望使用 LQR 而不是 PID 或 INDI 控制器，请启用此选项。\n仅适用于某些车辆。\n更线性的转向体验。</translation>\n    </message>\n    <message>\n        <source>Adjust this if you wish to let openpilot drive slightly towards to left (+) or right (-)</source>\n        <translation>如果您希望让 openpilot 稍微向左 (+) 或向右 (-) 驱动，请调整此项</translation>\n    </message>\n    <message>\n        <source>Adjust your screen brightness.</source>\n        <translation>调整屏幕亮度</translation>\n    </message>\n    <message>\n        <source>Adjust your alert volume.</source>\n        <translation>调整告警音量</translation>\n    </message>\n    <message>\n        <source>Manually Control Accel Mode</source>\n        <translation>手动控制加速模式</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to adjust openpilot&apos;s acceleration control.</source>\n        <translation>如果你希望调整 openpilot 的加速控制，请启用此选项。</translation>\n    </message>\n    <message>\n        <source>Manually Control Following Mode</source>\n        <translation>手动控制跟车模式</translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to adjust openpilot&apos;s following distance.\nopenpilot by default keeps 1.8 secs distance to lead car.</source>\n        <translation>如果您希望调整 openpilot 的跟车距离，请启用此选项。\n默认情况下，openpilot 与引导车保持 1.8 秒的距离。</translation>\n    </message>\n    <message>\n        <source>Fan Mode</source>\n        <comment>0 = Default\n1 = Quiet\n2 = Full Speed</comment>\n        <translation>散热风扇模式</translation>\n    </message>\n    <message>\n        <source>Tap this to update your panda firmware.\nThe device should reboot once if it finish updating.</source>\n        <translation>点按此按钮可更新您的熊猫固件。\n如果完成更新，设备应重新启动一次</translation>\n    </message>\n    <message>\n        <source>Tap this ONLY if your panda ran into issue.</source>\n        <translation>仅当熊猫遇到问题时才点击此选项。</translation>\n    </message>\n    <message>\n        <source> kph</source>\n        <translation></translation>\n    </message>\n    <message>\n        <source>Use Current Speed</source>\n        <translation>使用当前速度</translation>\n    </message>\n    <message>\n        <source>Enable this to link Following Profile (FM) control to the physical button.\nONLY WORK ON SOME VEHICLES.\nReboot required.</source>\n        <translation>使用原车物理按钮控制 跟车模板 (FM)\n仅适用于某些车辆。\n需要重新启动。</translation>\n    </message>\n    <message>\n        <source>Enable this to link Accel Mode (AM) control to the physical button.\nONLY WORK ON SOME VEHICLES.\nReboot required.</source>\n        <translation>使用原车物理按钮控制 加速模板 (AM)。\n仅适用于某些车辆。\n需要重新启动。</translation>\n    </message>\n    <message>\n        <source>Display Turning Signal / Blinkers</source>\n        <translation>显示转向灯及盲区指显</translation>\n    </message>\n    <message>\n        <source>Display Top Info Bar</source>\n        <translation>显示顶部信息条</translation>\n    </message>\n    <message>\n        <source>Enable MapD</source>\n        <translation>启用OSM地图</translation>\n    </message>\n    <message>\n        <source>Use OSM to assist lateral/longitudinal control.\nPlease note:\n 1. This feature will works only when your car support OP longitudinal.\n2. MapD will contribute your route to OSM for future improvement automatically.\n3. You can add your own offset for mapd just follow the readme under /selfdrive/mapd/.\"</source>\n        <translation>启用OSM地图</translation>\n    </message>\n    <message>\n        <source>Enable vision based turn control</source>\n        <translation>启用基于视觉的转弯控制</translation>\n    </message>\n    <message>\n        <source>Use vision path predictions to estimate the appropiate speed to drive through turns ahead.</source>\n        <translation>使用视觉路径预测来估算适当的速度以通过前方弯道。</translation>\n    </message>\n    <message>\n        <source>Enable Speed Limit Control</source>\n        <translation>启用限速控制</translation>\n    </message>\n    <message>\n        <source>Use speed limit signs information from map data and car interface to automatically adapt cruise speed to road limits.</source>\n        <translation>使用来自地图数据和汽车界面的限速标志信息自动调整巡航速度以适应道路限制。</translation>\n    </message>\n    <message>\n        <source>Enable Speed Limit Offset</source>\n        <translation>启用限速控制偏移</translation>\n    </message>\n    <message>\n        <source>Set speed limit slightly higher than actual speed limit for a more natural drive.</source>\n        <translation>将速度限制设置为略高于实际速度限制，以实现更自然的驾驶。</translation>\n    </message>\n    <message>\n        <source>Enable Map Data Turn Control</source>\n        <translation>使用地图数据信息控制转向速度</translation>\n    </message>\n    <message>\n        <source>Use curvature info from map data to define speed limits to take turns ahead</source>\n        <translation>使用地图数据中的曲率信息来设置限速</translation>\n    </message>\n    <message>\n        <source>Show debug UI elements</source>\n        <translation>显示调试UI图标</translation>\n    </message>\n    <message>\n        <source>Show UI elements that aid debugging.</source>\n        <translation>显示有助于调试的UI元素。</translation>\n    </message>\n\n</context>\n<context>\n    <name>SettingsWindow</name>\n    <message>\n        <source>Device</source>\n        <translation>设备</translation>\n    </message>\n    <message>\n        <source>Network</source>\n        <translation>网络</translation>\n    </message>\n    <message>\n        <source>Toggles</source>\n        <translation>开关</translation>\n    </message>\n    <message>\n        <source>Software</source>\n        <translation>关于本机</translation>\n    </message>\n    <message>\n        <source>DP - General</source>\n        <translation>DP - 通用</translation>\n    </message>\n    <message>\n        <source>DP - Controls</source>\n        <translation>DP - 控制</translation>\n    </message>\n    <message>\n        <source>DP - UI</source>\n        <translation>DP - 显示</translation>\n    </message>\n    <message>\n        <source>DP - Cars</source>\n        <translation>DP - 车型</translation>\n    </message>\n    <message>\n        <source>DP - MapD</source>\n        <translation>DP - 地图</translation>\n    </message>\n    <message>\n        <source>Navigation</source>\n        <translation>导航</translation>\n    </message>\n    <message>\n        <source>BACK</source>\n        <translation>返回</translation>\n    </message>\n</context>\n<context>\n    <name>SetupWidget</name>\n    <message>\n        <source>Finish Setup</source>\n        <translation>完成设置</translation>\n    </message>\n    <message>\n        <source>Pair your device with comma connect (connect.comma.ai) and claim your comma prime offer.</source>\n        <translation>配对你的设备连接到comma</translation>\n    </message>\n    <message>\n        <source>Pair device</source>\n        <translation>设备配对</translation>\n    </message>\n    <message>\n        <source>Scan the QR code to pair.</source>\n        <translation>扫描QR配对</translation>\n    </message>\n</context>\n<context>\n    <name>Sidebar</name>\n    <message>\n        <source>PANDA\nONLINE</source>\n        <translation>熊猫\n已连线</translation>\n    </message>\n    <message>\n        <source>PANDA\nOFFLINE</source>\n        <translation>熊猫\n已离线</translation>\n    </message>\n    <message>\n        <source>NO\nPANDA</source>\n        <translation>熊猫\n未连接</translation>\n    </message>\n    <message>\n        <source>GOOD\nTEMP</source>\n        <translation>温度\n良好</translation>\n    </message>\n    <message>\n        <source>OK\nTEMP</source>\n        <translation>温度\n还行</translation>\n    </message>\n    <message>\n        <source>HIGH\nTEMP</source>\n        <translation>温度\n很高</translation>\n    </message>\n    <message>\n        <source>NO\nPRIME</source>\n        <translation>没有\n高级会员</translation>\n    </message>\n    <message>\n        <source>CONNECT\nOFFLINE</source>\n        <translation>云服务\n已离线</translation>\n    </message>\n    <message>\n        <source>CONNECT\nONLINE</source>\n        <translation>云服务\n已连线</translation>\n    </message>\n    <message>\n        <source>CONNECT\nERROR</source>\n        <translation>云服务\n连线错误</translation>\n    </message>\n    <message>\n        <source>SATS\nSEARCHING</source>\n        <translation>卫星\n搜寻中</translation>\n    </message>\n    <message>\n        <source>SATS: %1\n%2 m</source>\n        <translation>SATS: %1\n%2 m</translation>\n    </message>\n    <message>\n        <source>TEMP</source>\n        <translation>温度</translation>\n    </message>\n</context>\n<context>\n    <name>SoftwarePanel</name>\n    <message>\n        <source>failed to fetch update</source>\n        <translation>下载更新失败</translation>\n    </message>\n    <message>\n        <source>CHECK</source>\n        <translation>检查</translation>\n    </message>\n    <message>\n        <source>Git Branch</source>\n        <translation>Git 分支</translation>\n    </message>\n    <message>\n        <source>Git Commit</source>\n        <translation>Git 提交描述</translation>\n    </message>\n    <message>\n        <source>OS Version</source>\n        <translation>系统版本</translation>\n    </message>\n    <message>\n        <source>Version</source>\n        <translation>版本</translation>\n    </message>\n    <message>\n        <source>Last Update Check</source>\n        <translation>上次检查时间</translation>\n    </message>\n    <message>\n        <source>The last time openpilot successfully checked for an update. The updater only runs while the car is off.</source>\n        <translation>openpilot 上次成功检查更新的时间。 更新程序仅在熄火状态时可用。</translation>\n    </message>\n    <message>\n        <source>Check for Update</source>\n        <translation>检查更新</translation>\n    </message>\n    <message>\n        <source>CHECKING</source>\n        <translation>检查中</translation>\n    </message>\n    <message>\n        <source>Uninstall </source>\n        <translation>卸载</translation>\n    </message>\n    <message>\n        <source>UNINSTALL</source>\n        <translation>卸载</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to uninstall?</source>\n        <translation>确定卸载吗？</translation>\n    </message>\n</context>\n<context>\n    <name>SshControl</name>\n    <message>\n        <source>Warning: This grants SSH access to all public keys in your GitHub settings. Never enter a GitHub username other than your own. A comma employee will NEVER ask you to add their GitHub username.</source>\n        <translation>警告：这将授予对 GitHub 设置中所有公钥的 SSH 访问权限。 切勿输入别人的 GitHub 用户名。 逗号不会要求您添加他们的 GitHub 用户名。</translation>\n    </message>\n    <message>\n        <source>Enter your GitHub username</source>\n        <translation>输入你的Github用户名</translation>\n    </message>\n    <message>\n        <source>REMOVE</source>\n        <translation>移除</translation>\n    </message>\n    <message>\n        <source>ADD</source>\n        <translation>添加</translation>\n    </message>\n</context>\n<context>\n    <name>TogglesPanel</name>\n    <message>\n        <source>Use the openpilot system for adaptive cruise control and lane keep driver assistance. Your attention is required at all times to use this feature. Changing this setting takes effect when the car is powered off.</source>\n        <translation>使用 openpilot 的自适应巡航功能和车道保持功能，开启后您需要保持注意力集中，设置更改在重新启动车辆后生效。</translation>\n    </message>\n    <message>\n        <source>Enable Lane Departure Warnings</source>\n        <translation>启用车道偏离预警</translation>\n    </message>\n    <message>\n        <source>Receive alerts to steer back into the lane when your vehicle drifts over a detected lane line without a turn signal activated while driving over 31mph (50kph).</source>\n        <translation>车速在 50 km/h 以上，且未打转向灯的情况下，如果检测到车辆驶出当前车道线时，则会发出车道偏离警告。</translation>\n    </message>\n    <message>\n        <source>Enable Right-Hand Drive</source>\n        <translation>启用右驾模式</translation>\n    </message>\n    <message>\n        <source>Allow openpilot to obey left-hand traffic conventions and perform driver monitoring on right driver seat.</source>\n        <translation>允许 openpilot 遵守靠左行驶的交通惯例，同时对右侧驾驶员进行监控。</translation>\n    </message>\n    <message>\n        <source>Use Metric System</source>\n        <translation>使用公制单位</translation>\n    </message>\n    <message>\n        <source>Display speed in km/h instead of mp/h.</source>\n        <translation>启用后，速度会显示 km/h，否则显示 mph。</translation>\n    </message>\n    <message>\n        <source>Enable Community Features</source>\n        <translation>启用社区功能</translation>\n    </message>\n    <message>\n        <source>Use features from the open source community that are not maintained or supported by comma.ai and have not been confirmed to meet the standard safety model. These features include community supported cars and community supported hardware. Be extra cautious when using these features</source>\n        <translation>使用来自开源社区开发维护的功能，这些软硬件不受官方支持维护，有可能不符合安全标准，请谨慎使用。</translation>\n    </message>\n    <message>\n        <source>Upload Raw Logs</source>\n        <translation>上传Raw日志</translation>\n    </message>\n    <message>\n        <source>Upload full logs and full resolution video by default while on WiFi. If not enabled, individual logs can be marked for upload at my.comma.ai/useradmin.</source>\n        <translation>在 WiFi 上默认上传完整日志和全分辨率视频。 如果未启用，则可以在 my.comma.ai/useradmin 将单个日志标记为上传。</translation>\n    </message>\n    <message>\n        <source>Record and Upload Driver Camera</source>\n        <translation>记录并上传驾驶监控数据</translation>\n    </message>\n    <message>\n        <source>Upload data from the driver facing camera and help improve the driver monitoring algorithm.</source>\n        <translation>上传驾驶监控及LOG数据以帮助更好的改进</translation>\n    </message>\n    <message>\n        <source>塞 Disable use of lanelines (Alpha) 塞</source>\n        <translation>塞 忽略车道线(测试) 塞</translation>\n    </message>\n    <message>\n        <source>In this mode openpilot will ignore lanelines and just drive how it thinks a human would.</source>\n        <translation>启用这个模式后，Openpilot 将会忽略车道线驾驶。</translation>\n    </message>\n    <message>\n        <source>Use 24h format instead of am/pm</source>\n        <translation>使用24小时制</translation>\n    </message>\n    <message>\n        <source>Enable openpilot</source>\n        <translation>启用 Openpilot</translation>\n    </message>\n    <message>\n        <source>Show ETA in 24h format</source>\n        <translation>剩余时间使用24小时制</translation>\n    </message>\n</context>\n<context>\n    <name>WifiUI</name>\n    <message>\n        <source>Scanning for networks...</source>\n        <translation>正在扫描WiFi...</translation>\n    </message>\n    <message>\n        <source>CONNECTING...</source>\n        <translation>正在连接...</translation>\n    </message>\n    <message>\n        <source>FORGET</source>\n        <translation>忽略</translation>\n    </message>\n    <message>\n        <source>Forget WiFi Network &quot;</source>\n        <translation>忽略此WiFi</translation>\n    </message>\n</context>\n</TS>\n"
  },
  {
    "path": "selfdrive/ui/translations/zh-TW.ts",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<!DOCTYPE TS>\n<TS version=\"2.1\" language=\"zh_TW\">\n<context>\n    <name>AdvancedNetworking</name>\n    <message>\n        <source>Back</source>\n        <translation>首頁</translation>\n    </message>\n    <message>\n        <source>Enable Tethering</source>\n        <translation>啟用個人熱點</translation>\n    </message>\n    <message>\n        <source>Tethering Password</source>\n        <translation>個人熱點密碼</translation>\n    </message>\n    <message>\n        <source>EDIT</source>\n        <translation>編輯</translation>\n    </message>\n    <message>\n        <source>Enter new tethering password</source>\n        <translation>輸入新的個人熱點密碼</translation>\n    </message>\n    <message>\n        <source>IP Address</source>\n        <translation>IP 位置</translation>\n    </message>\n</context>\n<context>\n    <name>DevicePanel</name>\n    <message>\n        <source>Dongle ID</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Serial</source>\n        <translation>序號</translation>\n    </message>\n    <message>\n        <source>Driver Camera</source>\n        <translation>駕駛監控</translation>\n    </message>\n    <message>\n        <source>PREVIEW</source>\n        <translation>預覽</translation>\n    </message>\n    <message>\n        <source>Preview the driver facing camera to help optimize device mounting position for best driver monitoring experience. (vehicle must be off)</source>\n        <translation>預覽駕駛員監控鏡頭畫面，方便調整裝置安裝位置，更好的使用駕駛員監控功能。(車子必須在熄火的狀態)</translation>\n    </message>\n    <message>\n        <source>openpilot requires the device to be mounted within 4° left or right and within 5° up or down. openpilot is continuously calibrating, resetting is rarely required.</source>\n        <translation>openpilot 需要將裝置固定在左右偏差 4° 以內，上下偏差 5° 以内。鏡頭在後台會持續自動校準，很少有需要重置的情况。</translation>\n    </message>\n    <message>\n        <source>Reset Calibration</source>\n        <translation>重置校準</translation>\n    </message>\n    <message>\n        <source>RESET</source>\n        <translation>重置</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to reset calibration?</source>\n        <translation>您確定要重置校準嗎？</translation>\n    </message>\n    <message>\n        <source> Your device is pointed %1° %2 and %3° %4.</source>\n        <translation> 你的設備目前朝%2 %1° 以及朝%4 %3° 。</translation>\n    </message>\n    <message>\n        <source>up</source>\n        <translation>上</translation>\n    </message>\n    <message>\n        <source>down</source>\n        <translation>下</translation>\n    </message>\n    <message>\n        <source>right</source>\n        <translation>右</translation>\n    </message>\n    <message>\n        <source>left</source>\n        <translation>左</translation>\n    </message>\n    <message>\n        <source>Review Training Guide</source>\n        <translation>回顧使用教學</translation>\n    </message>\n    <message>\n        <source>REVIEW</source>\n        <translation>查看</translation>\n    </message>\n    <message>\n        <source>Review the rules, features, and limitations of openpilot</source>\n        <translation>查看 openpilot 的規則、功能和限制。</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to review the training guide?</source>\n        <translation>您確定要查看使用教學嗎？</translation>\n    </message>\n    <message>\n        <source>Regulatory</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>VIEW</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Reboot</source>\n        <translation>重新啟動</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to reboot?</source>\n        <translation>你確定要重新啟動嗎？</translation>\n    </message>\n    <message>\n        <source>Power Off</source>\n        <translation>關機</translation>\n    </message>\n    <message>\n        <source>Are you sure you want to power off?</source>\n        <translation>您確定要關機嗎？</translation>\n    </message>\n</context>\n<context>\n    <name>DriveStats</name>\n    <message>\n        <source>Drives</source>\n        <translation>行程</translation>\n    </message>\n    <message>\n        <source>Hours </source>\n        <translation>小時 </translation>\n    </message>\n    <message>\n        <source>ALL TIME</source>\n        <translation>總共</translation>\n    </message>\n    <message>\n        <source>PAST WEEK</source>\n        <translation>上周</translation>\n    </message>\n    <message>\n        <source>KM</source>\n        <translation>公里</translation>\n    </message>\n    <message>\n        <source>Miles</source>\n        <translation>英里</translation>\n    </message>\n</context>\n<context>\n    <name>Networking</name>\n    <message>\n        <source>Enter password</source>\n        <translation>輸入密碼</translation>\n    </message>\n    <message>\n        <source>for </source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Wrong password</source>\n        <translation>密碼錯誤</translation>\n    </message>\n    <message>\n        <source>Advanced</source>\n        <translation>進階</translation>\n    </message>\n</context>\n<context>\n    <name>NvgWindow</name>\n    <message>\n        <source>FOLLOW</source>\n        <translation type=\"vanished\">車距</translation>\n    </message>\n    <message>\n        <source>REL DIST</source>\n        <translation type=\"vanished\">真實車距</translation>\n    </message>\n</context>\n<context>\n    <name>PrimeAdWidget</name>\n    <message>\n        <source>Upgrade Now</source>\n        <translation>馬上升級</translation>\n    </message>\n    <message>\n        <source>Become a comma prime member at connect.comma.ai</source>\n        <translation>成為 connect.comma.ai 的高級會員</translation>\n    </message>\n    <message>\n        <source>PRIME FEATURES:</source>\n        <translation>高級會員特點：</translation>\n    </message>\n    <message>\n        <source>Remote access</source>\n        <translation>遠程訪問</translation>\n    </message>\n    <message>\n        <source>14 days of storage</source>\n        <translation>14 天的雲端行車記錄</translation>\n    </message>\n    <message>\n        <source>Developer perks</source>\n        <translation>開發者福利</translation>\n    </message>\n</context>\n<context>\n    <name>PrimeUserWidget</name>\n    <message>\n        <source>✓ SUBSCRIBED</source>\n        <translation>✓ 已訂閱</translation>\n    </message>\n    <message>\n        <source>comma prime</source>\n        <translation>comma 高級會員</translation>\n    </message>\n    <message>\n        <source>COMMA POINTS</source>\n        <translation>COMMA 點數</translation>\n    </message>\n    <message>\n        <source>CONNECT.COMMA.AI</source>\n        <translation>CONNECT.COMMA.AI</translation>\n    </message>\n</context>\n<context>\n    <name>QObject</name>\n    <message>\n        <source>Auto Shutdown In</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> mins</source>\n        <translation> 分鐘</translation>\n    </message>\n    <message>\n        <source>Enable Auto Shutdown</source>\n        <translation>啟用自動關機</translation>\n    </message>\n    <message>\n        <source>FOLLOW</source>\n        <translation>車距</translation>\n    </message>\n    <message>\n        <source>REL DIST</source>\n        <translation>相對車距</translation>\n    </message>\n    <message>\n        <source>../assets/fonts/opensans_regular.ttf</source>\n        <translation type=\"vanished\">/system/fonts/NotoSansTC-Light.otf</translation>\n    </message>\n    <message>\n        <source>../assets/fonts/opensans_semibold.ttf</source>\n        <translation type=\"vanished\">/system/fonts/NotoSansTC-Regular.otf</translation>\n    </message>\n    <message>\n        <source>../assets/fonts/opensans_bold.ttf</source>\n        <translation type=\"vanished\">/system/fonts/NotoSansTC-Bold.otf</translation>\n    </message>\n    <message>\n        <source>SPT</source>\n        <translation>運動</translation>\n    </message>\n    <message>\n        <source>NOR</source>\n        <translation>普通</translation>\n    </message>\n    <message>\n        <source>ECO</source>\n        <translation>經濟</translation>\n    </message>\n    <message>\n        <source>ACCEL</source>\n        <translation>加速模式</translation>\n    </message>\n    <message>\n        <source>REL SPEED</source>\n        <translation>相對速度</translation>\n    </message>\n    <message>\n        <source>OFF</source>\n        <translation>無</translation>\n    </message>\n    <message>\n        <source>ENG RPM</source>\n        <translation>引擎轉速</translation>\n    </message>\n    <message>\n        <source>REAL STEER</source>\n        <translation>實際轉向</translation>\n    </message>\n    <message>\n        <source>DESIR STEER</source>\n        <translation>預測轉向</translation>\n    </message>\n    <message>\n        <source>openpilot Unavailable</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Waiting for controls to start</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>TAKE CONTROL IMMEDIATELY</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Controls Unresponsive</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to shutdown your device after the wait period specified.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to shutdown your device automatically.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>QWidget</name>\n    <message>\n        <source>Services</source>\n        <translation>服務</translation>\n    </message>\n    <message>\n        <source>Enable Updater Service</source>\n        <translation>啟用自動更新服務</translation>\n    </message>\n    <message>\n        <source>Reboot required.</source>\n        <translation>需要重新啟動。</translation>\n    </message>\n    <message>\n        <source>Enable Log Service</source>\n        <translation>啟用記錄服務</translation>\n    </message>\n    <message>\n        <source>Enable Uploader Service</source>\n        <translation>啟用記錄上傳服務</translation>\n    </message>\n    <message>\n        <source>Enable Athenad Service</source>\n        <translation>啟用雲端連線服務</translation>\n    </message>\n    <message>\n        <source>Enable On-Road Dashcam</source>\n        <translation>啟用行車記錄器服務</translation>\n    </message>\n    <message>\n        <source>Enable Appd Service</source>\n        <translation>啟用安卓應用服務</translation>\n    </message>\n    <message>\n        <source>Enable GPS Logger</source>\n        <translation>啟用 GPS 記錄服務</translation>\n    </message>\n    <message>\n        <source>This will store your track in /sdcard/gpx_logs/.\nReboot required.</source>\n        <translation>這將會將您行車的 GPS 路徑儲存至 /sdcard/gpx_logs/ 裡。</translation>\n    </message>\n    <message>\n        <source>Camera Offset</source>\n        <translation>相機偏移</translation>\n    </message>\n    <message>\n        <source>Enable Hotspot On Boot</source>\n        <translation>啟用開機自動開啟個人熱點</translation>\n    </message>\n    <message>\n        <source>Enable No Battery Support</source>\n        <translation>啟用無安裝電池模組支持</translation>\n    </message>\n    <message>\n        <source>Enable this option if your device does not have a battery.\nDo not use this if you have a C2, Reboot required.</source>\n        <translation>開啟無電池模組的設備的支持。\n請勿在 C2 上使用本功能，需重新開機。</translation>\n    </message>\n    <message>\n        <source>Enable White/Grey Panda Support</source>\n        <translation>啟用白/灰 Panda 支持</translation>\n    </message>\n    <message>\n        <source>Enable this option ONLY on white / grey panda.\nReboot required.</source>\n        <translation>開啟對白/灰 Panda 的支持，請勿在別的上使用這個功能。\n需重新開機。</translation>\n    </message>\n    <message>\n        <source>Enable No GPS Panda Support</source>\n        <translation>啟用無 GPS 模組的 Panda 支持</translation>\n    </message>\n    <message>\n        <source>Enable this option ONLY on Non-GPS Pandas.\nThis will need to recompile boardd (takes a while).\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Jetson Support</source>\n        <translation>啟用 Jetson 支持</translation>\n    </message>\n    <message>\n        <source>Enable this option if you intend to run dp on Nvidia Jetson.\nReboot required.</source>\n        <translation>如果您打算在 Nvidia Jetson NX 上跑 op，請開啟這選項。\n需重新啟動。</translation>\n    </message>\n    <message>\n        <source>Mark As Prebuilt</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Prebuilt Creates a file and improves boot speed.\nWARNING: You may need to disable it once switch to a new version.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>FLASH</source>\n        <translation>刷寫</translation>\n    </message>\n    <message>\n        <source>RECOVER</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>DELETE</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ALCA Delay</source>\n        <translation>自動換道延遲</translation>\n    </message>\n    <message>\n        <source> secs</source>\n        <translation> 秒</translation>\n    </message>\n    <message>\n        <source>ALCA Min Speed</source>\n        <translation>自動換道最低啟用速度</translation>\n    </message>\n    <message>\n        <source> mph</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Cont. ALCA</source>\n        <translation>啟用連續自動換道</translation>\n    </message>\n    <message>\n        <source>LCA Min Speed</source>\n        <translation>輔助換道最低啟用速度</translation>\n    </message>\n    <message>\n        <source>Blinker Off Recovery Delay</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Seconds after blinker off then OP will take back control.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Lateral Ctrl Mode</source>\n        <translation>橫向控制模式</translation>\n    </message>\n    <message>\n        <source>0 = No Lateral Ctrl On Blinkers\n1 = Lane Change Assist (LCA)\n2 = Auto Lane Change Assist (ALCA)</source>\n        <translation>0 = 轉向燈開啟時，不控制方向盤\n1 = 輔助換道 (LCA)\n2 = 自動換道 (ALCA)</translation>\n    </message>\n    <message>\n        <source>Use Accel Profile</source>\n        <translation type=\"vanished\">使用可調加速模式</translation>\n    </message>\n    <message>\n        <source>Use Following Profile</source>\n        <translation type=\"vanished\">使用可調車距模式</translation>\n    </message>\n    <message>\n        <source>Allow Gas Pedal Pressed</source>\n        <translation>允許踩油門</translation>\n    </message>\n    <message>\n        <source>Enable Gear Safety Check</source>\n        <translation>啟用檔位安全檢查</translation>\n    </message>\n    <message>\n        <source>Steering Ratio</source>\n        <translation>轉向比</translation>\n    </message>\n    <message>\n        <source>Adjust to &lt; 10 to reset to stock value.</source>\n        <translation>本值設定至低於 10 後將會自動重設置原廠值。</translation>\n    </message>\n    <message>\n        <source>RESET</source>\n        <translation>重置</translation>\n    </message>\n    <message>\n        <source>Enable Steering Ratio Learner</source>\n        <translation>啟用轉向比自動學習功能</translation>\n    </message>\n    <message>\n        <source>Use LQR Controller</source>\n        <translation>使用 LQR 控制器</translation>\n    </message>\n    <message>\n        <source>Driving Path Offset</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> cm</source>\n        <translation> 公分</translation>\n    </message>\n    <message>\n        <source>Enable Device Temp Check</source>\n        <translation>啟用設備溫度監控</translation>\n    </message>\n    <message>\n        <source>Enable Max Ctrl Speed Check</source>\n        <translation>啟用最高車速監控</translation>\n    </message>\n    <message>\n        <source>Display Mode</source>\n        <comment>0 = Default\n1 = Screen Off While Reversing\n2 = Screen Off While Driving</comment>\n        <translation>螢幕顯示模式</translation>\n    </message>\n    <message>\n        <source>Screen Brightness</source>\n        <translation>螢幕亮度</translation>\n    </message>\n    <message>\n        <source>AUTO</source>\n        <translation>自動</translation>\n    </message>\n    <message>\n        <source>Alert Volume</source>\n        <translation>提示音量</translation>\n    </message>\n    <message>\n        <source>Display Speed</source>\n        <translation>顯示車速</translation>\n    </message>\n    <message>\n        <source>Display Lane Prediction</source>\n        <translation>顯示路線預測</translation>\n    </message>\n    <message>\n        <source>Display Lead Car Indicator</source>\n        <translation>顯示前車預測</translation>\n    </message>\n    <message>\n        <source>Display Turning Signal / Blinkers</source>\n        <translation type=\"vanished\">顯示轉向燈</translation>\n    </message>\n    <message>\n        <source>Display Event / Steer Icon</source>\n        <translation>顯示事件圖示</translation>\n    </message>\n    <message>\n        <source>Display Max Speed</source>\n        <translation>顯示巡航定速</translation>\n    </message>\n    <message>\n        <source>Display Driver Monitor Indicator</source>\n        <translation>顯示駕駛監控圖示</translation>\n    </message>\n    <message>\n        <source>Display Side Info</source>\n        <translation>顯示側邊資訊欄</translation>\n    </message>\n    <message>\n        <source>Display Top Info Bar</source>\n        <translation type=\"unfinished\">顯示上方資訊欄</translation>\n    </message>\n    <message>\n        <source>LAUNCH</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>If your current speed is greater than &apos;Override To&apos; but lower than &apos;Override At&apos;, it will use your current speed instead.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Turn On Cruise Speed Override</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable SnG Mod</source>\n        <translation>啟用 SnG 協助</translation>\n    </message>\n    <message>\n        <source>Enable ZSS Support</source>\n        <translation>啟用 ZSS 模組支持</translation>\n    </message>\n    <message>\n        <source>Enable No Relay Mode</source>\n        <translation>啟用無中繼器模式</translation>\n    </message>\n    <message>\n        <source>Enable this will disable relay in your panda.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable EPS Mod Mode</source>\n        <translation>啟用 EPS 破解支持</translation>\n    </message>\n    <message>\n        <source>Enable this will increase steering, USE IT ONLY if you have a modded EPS firmware.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Force to display km/h in HUD</source>\n        <translation>強制儀表上以 km/h 為顯示單位</translation>\n    </message>\n    <message>\n        <source>Enable this if your HUD does not display km/h unit.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Smart MDPS Support</source>\n        <translation>啟用 Smart MDPS 模組支持</translation>\n    </message>\n    <message>\n        <source>Enable this will increase steering and allow steering down to to 0.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable J533 + White Panda Mode</source>\n        <translation>啟用 J533 配套白 Panda 模式</translation>\n    </message>\n    <message>\n        <source>Credit to jyoung8607.\nReboot required.</source>\n        <translation>感謝 jyoung8607 提供。\n需重新啟動。</translation>\n    </message>\n    <message>\n        <source>Enable Timebomb Assist</source>\n        <translation>啟用方向盤控制時限協助功能</translation>\n    </message>\n    <message>\n        <source>Hardware - General</source>\n        <translation>硬體 - 一般</translation>\n    </message>\n    <message>\n        <source>Hardware - Panda</source>\n        <translation>硬體 - Panda</translation>\n    </message>\n    <message>\n        <source>Reboot recommended.\nReboot?</source>\n        <translation>我們建議您重新啟動\n要重新啟動嗎？</translation>\n    </message>\n    <message>\n        <source>Miscellaneous</source>\n        <translation>其它</translation>\n    </message>\n    <message>\n        <source>Flashing Panda Firmware</source>\n        <translation>刷新 Panda 韌體</translation>\n    </message>\n    <message>\n        <source>Are you sure?</source>\n        <translation>您確定嗎？</translation>\n    </message>\n    <message>\n        <source>Pandas Firmware Recovery</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Delete All Driving Log</source>\n        <translation>刪除所有的行駛記錄</translation>\n    </message>\n    <message>\n        <source>Longitudinal</source>\n        <translation>縱向控制 (油門/剎車)</translation>\n    </message>\n    <message>\n        <source>Lateral</source>\n        <translation>橫向控制 (方向盤)</translation>\n    </message>\n    <message>\n        <source>Language</source>\n        <translation>系統語言</translation>\n    </message>\n    <message>\n        <source>Volume</source>\n        <translation>系統音量</translation>\n    </message>\n    <message>\n        <source>Date/Time</source>\n        <translation>系統時間</translation>\n    </message>\n    <message>\n        <source>Assign Car Model:</source>\n        <translation>自定義車型：</translation>\n    </message>\n    <message>\n        <source>Toyota / Lexus</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Honda</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Hyundai / Kia / Genesis</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Volkswagen</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable Lexus RX Low Gear/High RPM Fix</source>\n        <translation>啟用 Lexus RX 低檔/高轉速 問題修正</translation>\n    </message>\n    <message>\n        <source>See: https://github.com/LexusRXopenpilotUG/openpilot\nCredit to @nelsonchen &amp; @sumedhekaru\nReboot required.</source>\n        <translation>詳情請看: https://github.com/LexusRXopenpilotUG/openpilot\n感謝 @nelsonchen 以及 @sumedhekaru 提供\n需重新啟動。</translation>\n    </message>\n    <message>\n        <source>OPEN</source>\n        <translation>開啟</translation>\n    </message>\n    <message>\n        <source>Tethering Settings</source>\n        <translation>網路分享設定</translation>\n    </message>\n    <message>\n        <source>WiFi Settings</source>\n        <translation>無網網路設定</translation>\n    </message>\n    <message>\n        <source>Fan Mode</source>\n        <translation>風扇模式</translation>\n    </message>\n    <message>\n        <source>0 = Default\n1 = Quiet\n2 = Full Speed</source>\n        <translation>0 = 標準\n1 = 安靜\n2 = 全速</translation>\n    </message>\n    <message>\n        <source>Tap the button to update your panda firmware.\nThe device should reboot once if it finish updating.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tap the button ONLY if your panda ran into issue.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Tap the button to delete ALL your driving logs.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Once the vehicle meets all ALCA criteria, it will wait for the seconds set here before peforming lane change automatically.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Once enabled, it will perform ALCA continuously.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to get automatic update.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to log your drive.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to upload your driving log.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to use cloud services such as comma prime.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to record screen, just like a dashcam.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to run your own android app.\nSee /data/openpilot/selfdrive/dragonpilot/HOWTO-APPD.md for more information.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust your camera position if your device is not mounted as per guidance.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>ALCA minimum engage speed in mph.\n1 mph = 1.61 km/h.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>LCA minimum engage speed in mph.\n1 mph = 1.61 km/h.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish openpilot to stay engaged when gas is pressed.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish openpilot to only work on D drive.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to use LQR instead of PID or INDI controller.\nWORKS WELL ONLY ON SOME VEHICLES.\nMore linear steering experience.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust this if you wish to let openpilot drive slightly towards to left (+) or right (-)</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust your screen brightness.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Adjust your alert volume.</source>\n        <translation>調整 openpilot 提示音音量。</translation>\n    </message>\n    <message>\n        <source>Enable this to display the lane/path prediction.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display the triangle lead car indicator.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Display Turn Signal / Blinkers</source>\n        <translation>顯示轉向燈</translation>\n    </message>\n    <message>\n        <source>Enable this to display turn signals.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display the icon.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display your current SET cruise speed.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display steering angle / lead car distance / engine RPM.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display time / system temp / battery level.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Override Speed When Below</source>\n        <translation>改寫定速當定速值底於</translation>\n    </message>\n    <message>\n        <source>Override feature will be enabled when set cruise speed is lower than this value.\n1 km/h = 0.62 mph.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source> km/h</source>\n        <translation></translation>\n    </message>\n    <message>\n        <source>Override Speed To</source>\n        <translation>改寫定速值為</translation>\n    </message>\n    <message>\n        <source>Override set speed to this value.\n1 km/h = 0.62 mph</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Use Current Speed</source>\n        <translation>使用目前車速值</translation>\n    </message>\n    <message>\n        <source>Enable this to fix stop and go (SnG) issue on some models.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you have ZSS module installed.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to assist you the 6 mins. LKA limit on some models.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to display your current speed.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Manually Control Accel Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to adjust openpilot&apos;s acceleration control.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Manually Control Following Mode</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this if you wish to adjust openpilot&apos;s following distance.\nopenpilot by default keeps 1.8 secs distance to lead car.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable FM Physical Button Ctrl</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to link Following Mode (FM) control to the physical button.\nONLY WORK ON SOME VEHICLES.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable AM Physical Button Ctrl</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Enable this to link Accel Mode (AM) control to the physical button.\nONLY WORK ON SOME VEHICLES.\nReboot required.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>SettingsWindow</name>\n    <message>\n        <source>Device</source>\n        <translation>設備</translation>\n    </message>\n    <message>\n        <source>Network</source>\n        <translation>網路</translation>\n    </message>\n    <message>\n        <source>Toggles</source>\n        <translation>設定</translation>\n    </message>\n    <message>\n        <source>Software</source>\n        <translation>軟體</translation>\n    </message>\n    <message>\n        <source>DP - General</source>\n        <translation>DP - 通用</translation>\n    </message>\n    <message>\n        <source>DP - Controls</source>\n        <translation>DP - 操控相關</translation>\n    </message>\n    <message>\n        <source>DP - UI</source>\n        <translation>DP - 介面相關</translation>\n    </message>\n    <message>\n        <source>DP - Cars</source>\n        <translation>DP - 車型相關</translation>\n    </message>\n    <message>\n        <source>Navigation</source>\n        <translation>導航</translation>\n    </message>\n    <message>\n        <source>BACK</source>\n        <translation>回上頁</translation>\n    </message>\n</context>\n<context>\n    <name>SetupWidget</name>\n    <message>\n        <source>Finish Setup</source>\n        <translation>完成設定</translation>\n    </message>\n    <message>\n        <source>Pair your device with comma connect (connect.comma.ai) and claim your comma prime offer.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Pair device</source>\n        <translation>配對設備</translation>\n    </message>\n    <message>\n        <source>Scan the QR code to pair.</source>\n        <translation>掃描 QR 碼配對。</translation>\n    </message>\n</context>\n<context>\n    <name>Sidebar</name>\n    <message>\n        <source>PANDA\nONLINE</source>\n        <translation>PANDA\n已連線</translation>\n    </message>\n    <message>\n        <source>PANDA\nOFFLINE</source>\n        <translation>PANDA\n已離線</translation>\n    </message>\n    <message>\n        <source>NO\nPRIME</source>\n        <translation>沒有\n高級會員</translation>\n    </message>\n    <message>\n        <source>CONNECT\nOFFLINE</source>\n        <translation>雲端服務\n已離線</translation>\n    </message>\n    <message>\n        <source>CONNECT\nONLINE</source>\n        <translation>雲端服務\n已連線</translation>\n    </message>\n    <message>\n        <source>CONNECT\nERROR</source>\n        <translation>雲端服務\n連線錯誤</translation>\n    </message>\n    <message>\n        <source>SATS\nSEARCHING</source>\n        <translation>衛星\n搜尋中</translation>\n    </message>\n    <message>\n        <source>SATS: %1\n%2 m</source>\n        <translation>SATS: %1\n%2 m</translation>\n    </message>\n    <message>\n        <source>TEMP</source>\n        <translation>溫度</translation>\n    </message>\n</context>\n<context>\n    <name>SoftwarePanel</name>\n    <message>\n        <source>failed to fetch update</source>\n        <translation>下載更新失敗</translation>\n    </message>\n    <message>\n        <source>CHECK</source>\n        <translation>檢查</translation>\n    </message>\n    <message>\n        <source>Git Branch</source>\n        <translation>Git 分支</translation>\n    </message>\n    <message>\n        <source>Git Commit</source>\n        <translation>Git 提交描述</translation>\n    </message>\n    <message>\n        <source>OS Version</source>\n        <translation>系統版本</translation>\n    </message>\n    <message>\n        <source>Version</source>\n        <translation>版本</translation>\n    </message>\n    <message>\n        <source>Last Update Check</source>\n        <translation>上次檢查時間</translation>\n    </message>\n    <message>\n        <source>The last time openpilot successfully checked for an update. The updater only runs while the car is off.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Check for Update</source>\n        <translation>檢查更新</translation>\n    </message>\n    <message>\n        <source>CHECKING</source>\n        <translation>檢查中</translation>\n    </message>\n    <message>\n        <source>Uninstall </source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>UNINSTALL</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Are you sure you want to uninstall?</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n<context>\n    <name>SshControl</name>\n    <message>\n        <source>Enter your GitHub username</source>\n        <translation>請輸入您 GitHub 的用戶名</translation>\n    </message>\n    <message>\n        <source>REMOVE</source>\n        <translation>移除</translation>\n    </message>\n    <message>\n        <source>ADD</source>\n        <translation>新增</translation>\n    </message>\n    <message>\n        <source>Warning: This grants SSH access to all public keys in your GitHub settings. Never enter a GitHub username other than your own. A comma employee will NEVER ask you to add their GitHub username.</source>\n        <translation>警告：這將授權給 GitHub 帳號中所有公鑰 SSH 訪問權限。切勿輸入非您自己的 GitHub 用戶名。comma 員工永遠不會要求您添加他們的 GitHub 用戶名。</translation>\n    </message>\n</context>\n<context>\n    <name>TogglesPanel</name>\n    <message>\n        <source>Use the openpilot system for adaptive cruise control and lane keep driver assistance. Your attention is required at all times to use this feature. Changing this setting takes effect when the car is powered off.</source>\n        <translation>使用 openpilot 的主動式巡航和車道保持功能，開啟後您仍需要保持注意力集中，設定變更在重新啟動車輛後生效。</translation>\n    </message>\n    <message>\n        <source>Enable Lane Departure Warnings</source>\n        <translation>啟用車道偏離警告</translation>\n    </message>\n    <message>\n        <source>Receive alerts to steer back into the lane when your vehicle drifts over a detected lane line without a turn signal activated while driving over 31mph (50kph).</source>\n        <translation>車速在 50 km/h (31 mph) 以上且未打轉向燈的情況下，如果偵測到車輛駛出目前車道線時，發出車道偏離警告。</translation>\n    </message>\n    <message>\n        <source>Enable Right-Hand Drive</source>\n        <translation>啟用右駕模式</translation>\n    </message>\n    <message>\n        <source>Allow openpilot to obey left-hand traffic conventions and perform driver monitoring on right driver seat.</source>\n        <translation>允許 openpilot 遵守靠左駕的交通慣例同時對右側駕駛進行監控。</translation>\n    </message>\n    <message>\n        <source>Use Metric System</source>\n        <translation>使用公制單位</translation>\n    </message>\n    <message>\n        <source>Display speed in km/h instead of mp/h.</source>\n        <translation>啟用後，速度單位顯示將從 mp/h 改為 km/h。</translation>\n    </message>\n    <message>\n        <source>Enable Community Features</source>\n        <translation>啟用社群維護功能</translation>\n    </message>\n    <message>\n        <source>Use features from the open source community that are not maintained or supported by comma.ai and have not been confirmed to meet the standard safety model. These features include community supported cars and community supported hardware. Be extra cautious when using these features</source>\n        <translation>使用來自開源社區開發維護的功能，這些軟硬體不受官方支援維護，有可能不符合安全標準，請謹慎使用。</translation>\n    </message>\n    <message>\n        <source>Upload Raw Logs</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Upload full logs and full resolution video by default while on WiFi. If not enabled, individual logs can be marked for upload at my.comma.ai/useradmin.</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Record and Upload Driver Camera</source>\n        <translation>記錄並上傳駕駛鏡頭影像</translation>\n    </message>\n    <message>\n        <source>Upload data from the driver facing camera and help improve the driver monitoring algorithm.</source>\n        <translation>上傳前置相機的錄像來協助我們提升駕駛監控的準確率。</translation>\n    </message>\n    <message>\n        <source>塞 Disable use of lanelines (Alpha) 塞</source>\n        <translation>塞 停用車道線判斷 (測試) 塞</translation>\n    </message>\n    <message>\n        <source>In this mode openpilot will ignore lanelines and just drive how it thinks a human would.</source>\n        <translation>在這種模式下，openpilot 將忽略車道線並按照人爲方式駕駛。</translation>\n    </message>\n    <message>\n        <source>Show ETA in 24h format</source>\n        <translation>預計到達時間單位改用 24 小時制</translation>\n    </message>\n    <message>\n        <source>Use 24h format instead of am/pm</source>\n        <translation>使用 24 小時制。(預設值為 12 小時制)</translation>\n    </message>\n    <message>\n        <source>Enable openpilot</source>\n        <translation>啟用 openpilot</translation>\n    </message>\n</context>\n<context>\n    <name>WifiUI</name>\n    <message>\n        <source>Scanning for networks...</source>\n        <translation>掃描無線網路中...</translation>\n    </message>\n    <message>\n        <source>CONNECTING...</source>\n        <translation>連線中...</translation>\n    </message>\n    <message>\n        <source>FORGET</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n    <message>\n        <source>Forget WiFi Network &quot;</source>\n        <translation type=\"unfinished\"></translation>\n    </message>\n</context>\n</TS>\n"
  },
  {
    "path": "selfdrive/ui/ui",
    "content": "#!/bin/sh\ncd \"$(dirname \"$0\")\"\nexport LD_LIBRARY_PATH=\"/system/lib64:$LD_LIBRARY_PATH\"\nif [ -f /JETSON ]; then\n  export LD_LIBRARY_PATH=\"/data/openpilot/phonelibs/mapbox-gl-native-qt/jarch64:$LD_LIBRARY_PATH\"\nfi\nexport QT_PLUGIN_PATH=\"../../phonelibs/qt-plugins/$(uname -m)\"\nexec ./_ui\n"
  },
  {
    "path": "selfdrive/ui/ui.cc",
    "content": "#include \"selfdrive/ui/ui.h\"\n\n#include <unistd.h>\n\n#include <cassert>\n#include <cmath>\n#include <cstdio>\n\n#include \"selfdrive/common/swaglog.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/visionimg.h\"\n#include \"selfdrive/common/watchdog.h\"\n#include \"selfdrive/hardware/hw.h\"\n#include \"selfdrive/ui/paint.h\"\n#include \"selfdrive/ui/qt/qt_window.h\"\n\n#define BACKLIGHT_DT 0.05\n#define BACKLIGHT_TS 10.00\n#define BACKLIGHT_OFFROAD 75\n\n\n// Projects a point in car to space to the corresponding point in full frame\n// image space.\nstatic bool calib_frame_to_full_frame(const UIState *s, float in_x, float in_y, float in_z, vertex_data *out) {\n  const float margin = 500.0f;\n  const vec3 pt = (vec3){{in_x, in_y, in_z}};\n  const vec3 Ep = matvecmul3(s->scene.view_from_calib, pt);\n  const vec3 KEp = matvecmul3(s->wide_camera ? ecam_intrinsic_matrix : fcam_intrinsic_matrix, Ep);\n\n  // Project.\n  float x = KEp.v[0] / KEp.v[2];\n  float y = KEp.v[1] / KEp.v[2];\n\n  nvgTransformPoint(&out->x, &out->y, s->car_space_transform, x, y);\n  return out->x >= -margin && out->x <= s->fb_w + margin && out->y >= -margin && out->y <= s->fb_h + margin;\n}\n\nstatic void ui_init_vision(UIState *s) {\n  // Invisible until we receive a calibration message.\n  s->scene.world_objects_visible = false;\n\n  for (int i = 0; i < s->vipc_client->num_buffers; i++) {\n    s->texture[i].reset(new EGLImageTexture(&s->vipc_client->buffers[i]));\n\n    glBindTexture(GL_TEXTURE_2D, s->texture[i]->frame_tex);\n    glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);\n    glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);\n\n    // BGR\n    glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_R, GL_BLUE);\n    glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_G, GL_GREEN);\n    glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_SWIZZLE_B, GL_RED);\n  }\n  assert(glGetError() == GL_NO_ERROR);\n}\n\nstatic int get_path_length_idx(const cereal::ModelDataV2::XYZTData::Reader &line, const float path_height) {\n  const auto line_x = line.getX();\n  int max_idx = 0;\n  for (int i = 0; i < TRAJECTORY_SIZE && line_x[i] < path_height; ++i) {\n    max_idx = i;\n  }\n  return max_idx;\n}\n\nstatic void update_leads(UIState *s, const cereal::ModelDataV2::Reader &model) {\n  auto leads = model.getLeadsV3();\n  auto model_position = model.getPosition();\n  for (int i = 0; i < 2; ++i) {\n    if (leads[i].getProb() > 0.5) {\n      float z = model_position.getZ()[get_path_length_idx(model_position, leads[i].getX()[0])];\n      calib_frame_to_full_frame(s, leads[i].getX()[0], leads[i].getY()[0], z + 1.22, &s->scene.lead_vertices[i]);\n    }\n  }\n}\n\nstatic void update_line_data(const UIState *s, const cereal::ModelDataV2::XYZTData::Reader &line,\n                             float y_off, float z_off, line_vertices_data *pvd, int max_idx) {\n  const auto line_x = line.getX(), line_y = line.getY(), line_z = line.getZ();\n  vertex_data *v = &pvd->v[0];\n  for (int i = 0; i <= max_idx; i++) {\n    v += calib_frame_to_full_frame(s, line_x[i], line_y[i] - y_off, line_z[i] + z_off, v);\n  }\n  for (int i = max_idx; i >= 0; i--) {\n    v += calib_frame_to_full_frame(s, line_x[i], line_y[i] + y_off, line_z[i] + z_off, v);\n  }\n  pvd->cnt = v - pvd->v;\n  assert(pvd->cnt <= std::size(pvd->v));\n}\n\nstatic void update_model(UIState *s, const cereal::ModelDataV2::Reader &model) {\n  UIScene &scene = s->scene;\n  auto model_position = model.getPosition();\n  float max_distance = std::clamp(model_position.getX()[TRAJECTORY_SIZE - 1],\n                                  MIN_DRAW_DISTANCE, MAX_DRAW_DISTANCE);\n\n  // update lane lines\n  const auto lane_lines = model.getLaneLines();\n  const auto lane_line_probs = model.getLaneLineProbs();\n  int max_idx = get_path_length_idx(lane_lines[0], max_distance);\n  for (int i = 0; i < std::size(scene.lane_line_vertices); i++) {\n    scene.lane_line_probs[i] = lane_line_probs[i];\n    update_line_data(s, lane_lines[i], 0.025 * scene.lane_line_probs[i], 0, &scene.lane_line_vertices[i], max_idx);\n  }\n\n  // update road edges\n  const auto road_edges = model.getRoadEdges();\n  const auto road_edge_stds = model.getRoadEdgeStds();\n  for (int i = 0; i < std::size(scene.road_edge_vertices); i++) {\n    scene.road_edge_stds[i] = road_edge_stds[i];\n    update_line_data(s, road_edges[i], 0.025, 0, &scene.road_edge_vertices[i], max_idx);\n  }\n\n  // update path\n  auto lead_one = model.getLeadsV3()[0];\n  if (lead_one.getProb() > 0.5) {\n    const float lead_d = lead_one.getX()[0] * 2.;\n    max_distance = std::clamp((float)(lead_d - fmin(lead_d * 0.35, 10.)), 0.0f, max_distance);\n  }\n  max_idx = get_path_length_idx(model_position, max_distance);\n  update_line_data(s, model_position, 0.5, 1.22, &scene.track_vertices, max_idx);\n}\n\nstatic void update_sockets(UIState *s) {\n  s->sm->update(0);\n}\n\nstatic void update_state(UIState *s) {\n  SubMaster &sm = *(s->sm);\n  UIScene &scene = s->scene;\n\n  // update engageability and DM icons at 2Hz\n  if (sm.frame % (UI_FREQ / 2) == 0) {\n    scene.engageable = sm[\"controlsState\"].getControlsState().getEngageable();\n    scene.dm_active = sm[\"driverMonitoringState\"].getDriverMonitoringState().getIsActiveMode();\n  }\n  if (sm.updated(\"modelV2\") && s->vg) {\n    auto model = sm[\"modelV2\"].getModelV2();\n    update_model(s, model);\n    update_leads(s, model);\n  }\n  if (sm.updated(\"liveCalibration\")) {\n    scene.world_objects_visible = true;\n    auto rpy_list = sm[\"liveCalibration\"].getLiveCalibration().getRpyCalib();\n    Eigen::Vector3d rpy;\n    rpy << rpy_list[0], rpy_list[1], rpy_list[2];\n    Eigen::Matrix3d device_from_calib = euler2rot(rpy);\n    Eigen::Matrix3d view_from_device;\n    view_from_device << 0,1,0,\n                        0,0,1,\n                        1,0,0;\n    Eigen::Matrix3d view_from_calib = view_from_device * device_from_calib;\n    for (int i = 0; i < 3; i++) {\n      for (int j = 0; j < 3; j++) {\n        scene.view_from_calib.v[i*3 + j] = view_from_calib(i,j);\n      }\n    }\n  }\n  if (sm.updated(\"pandaState\")) {\n    auto pandaState = sm[\"pandaState\"].getPandaState();\n    scene.pandaType = pandaState.getPandaType();\n    scene.ignition = pandaState.getIgnitionLine() || pandaState.getIgnitionCan();\n  } else if ((s->sm->frame - s->sm->rcv_frame(\"pandaState\")) > 5*UI_FREQ) {\n    scene.pandaType = cereal::PandaState::PandaType::UNKNOWN;\n  }\n  if (sm.updated(\"carParams\")) {\n    scene.longitudinal_control = sm[\"carParams\"].getCarParams().getOpenpilotLongitudinalControl();\n  }\n  #ifndef XNX\n  if (sm.updated(\"sensorEvents\")) {\n    for (auto sensor : sm[\"sensorEvents\"].getSensorEvents()) {\n      if (!scene.started && sensor.which() == cereal::SensorEventData::ACCELERATION) {\n        auto accel = sensor.getAcceleration().getV();\n        if (accel.totalSize().wordCount) { // TODO: sometimes empty lists are received. Figure out why\n          scene.accel_sensor = accel[2];\n        }\n      } else if (!scene.started && sensor.which() == cereal::SensorEventData::GYRO_UNCALIBRATED) {\n        auto gyro = sensor.getGyroUncalibrated().getV();\n        if (gyro.totalSize().wordCount) {\n          scene.gyro_sensor = gyro[1];\n        }\n      }\n    }\n  }\n  #endif\n  if (sm.updated(\"roadCameraState\")) {\n    auto camera_state = sm[\"roadCameraState\"].getRoadCameraState();\n\n    float max_lines = Hardware::EON() ? 5408 : 1904;\n    float max_gain = Hardware::EON() ? 1.0: 10.0;\n    float max_ev = max_lines * max_gain;\n\n    if (Hardware::TICI) {\n      max_ev /= 6;\n    }\n\n    float ev = camera_state.getGain() * float(camera_state.getIntegLines());\n\n    scene.light_sensor = std::clamp<float>(1.0 - (ev / max_ev), 0.0, 1.0);\n  }\n  scene.started = sm[\"deviceState\"].getDeviceState().getStarted() && scene.ignition;\n}\n\nstatic void update_params(UIState *s) {\n  const uint64_t frame = s->sm->frame;\n  UIScene &scene = s->scene;\n  if (frame % (5*UI_FREQ) == 0) {\n    scene.is_metric = Params().getBool(\"IsMetric\");\n  }\n}\n\nstatic void update_vision(UIState *s) {\n  if (!s->vipc_client->connected && s->scene.started) {\n    if (s->vipc_client->connect(false)) {\n      ui_init_vision(s);\n    }\n  }\n\n  if (s->vipc_client->connected) {\n    VisionBuf * buf = s->vipc_client->recv();\n    if (buf != nullptr) {\n      s->last_frame = buf;\n    } else if (!Hardware::PC() && !Hardware::JETSON()) {\n      LOGE(\"visionIPC receive timeout\");\n    }\n  } else if (s->scene.started) {\n    util::sleep_for(1000. / UI_FREQ);\n  }\n}\n\nstatic void update_status(UIState *s) {\n  if (s->scene.started && s->sm->updated(\"controlsState\")) {\n    auto controls_state = (*s->sm)[\"controlsState\"].getControlsState();\n    auto alert_status = controls_state.getAlertStatus();\n    if (alert_status == cereal::ControlsState::AlertStatus::USER_PROMPT) {\n      s->status = STATUS_WARNING;\n    } else if (alert_status == cereal::ControlsState::AlertStatus::CRITICAL) {\n      s->status = STATUS_ALERT;\n    } else {\n      s->status = controls_state.getEnabled() ? STATUS_ENGAGED : STATUS_DISENGAGED;\n    }\n  }\n\n  // Handle onroad/offroad transition\n  static bool started_prev = false;\n  if (s->scene.started != started_prev) {\n    if (s->scene.started) {\n      s->status = STATUS_DISENGAGED;\n      s->scene.started_frame = s->sm->frame;\n\n      s->scene.end_to_end = Params().getBool(\"EndToEndToggle\");\n      s->wide_camera = Hardware::TICI() ? Params().getBool(\"EnableWideCamera\") : false;\n\n      // Update intrinsics matrix after possible wide camera toggle change\n      if (s->vg) {\n        ui_resize(s, s->fb_w, s->fb_h);\n      }\n\n      // Choose vision ipc client\n      if (s->wide_camera) {\n        s->vipc_client = s->vipc_client_wide;\n      } else {\n        s->vipc_client = s->vipc_client_rear;\n      }\n    } else {\n      s->vipc_client->connected = false;\n    }\n  }\n  started_prev = s->scene.started;\n}\n\n\nQUIState::QUIState(QObject *parent) : QObject(parent) {\n  ui_state.sm = std::make_unique<SubMaster, const std::initializer_list<const char *>>({\n    \"modelV2\", \"controlsState\", \"liveCalibration\", \"deviceState\", \"roadCameraState\",\n    \"pandaState\", \"carParams\", \"driverMonitoringState\", \"sensorEvents\", \"carState\", \"liveLocationKalman\",\n  });\n\n  ui_state.fb_w = vwp_w;\n  ui_state.fb_h = vwp_h;\n  ui_state.scene.started = false;\n  ui_state.last_frame = nullptr;\n  ui_state.wide_camera = Hardware::TICI() ? Params().getBool(\"EnableWideCamera\") : false;\n\n  ui_state.vipc_client_rear = new VisionIpcClient(\"camerad\", VISION_STREAM_RGB_BACK, true);\n  ui_state.vipc_client_wide = new VisionIpcClient(\"camerad\", VISION_STREAM_RGB_WIDE, true);\n\n  ui_state.vipc_client = ui_state.vipc_client_rear;\n\n  // update timer\n  timer = new QTimer(this);\n  QObject::connect(timer, &QTimer::timeout, this, &QUIState::update);\n  timer->start(0);\n}\n\nvoid QUIState::update() {\n  update_params(&ui_state);\n  update_sockets(&ui_state);\n  update_state(&ui_state);\n  update_status(&ui_state);\n  update_vision(&ui_state);\n\n  if (ui_state.scene.started != started_prev || ui_state.sm->frame == 1) {\n    started_prev = ui_state.scene.started;\n    emit offroadTransition(!ui_state.scene.started);\n\n    // Change timeout to 0 when onroad, this will call update continuously.\n    // This puts visionIPC in charge of update frequency, reducing video latency\n    timer->start(ui_state.scene.started ? 0 : 1000 / UI_FREQ);\n  }\n\n  watchdog_kick();\n  emit uiUpdate(ui_state);\n}\n\nDevice::Device(QObject *parent) : brightness_filter(BACKLIGHT_OFFROAD, BACKLIGHT_TS, BACKLIGHT_DT), QObject(parent) {\n}\n\nvoid Device::update(const UIState &s) {\n  updateBrightness(s);\n  updateWakefulness(s);\n\n  // TODO: remove from UIState and use signals\n  QUIState::ui_state.awake = awake;\n}\n\nvoid Device::setAwake(bool on, bool reset) {\n  if (on != awake) {\n    awake = on;\n    Hardware::set_display_power(awake);\n    LOGD(\"setting display power %d\", awake);\n    emit displayPowerChanged(awake);\n  }\n\n  if (reset) {\n    awake_timeout = 30 * UI_FREQ;\n  }\n}\n\nvoid Device::updateBrightness(const UIState &s) {\n  // Scale to 0% to 100%\n  float clipped_brightness = 100.0 * s.scene.light_sensor;\n\n  // CIE 1931 - https://www.photonstophotos.net/GeneralTopics/Exposure/Psychometric_Lightness_and_Gamma.htm\n  if (clipped_brightness <= 8) {\n    clipped_brightness = (clipped_brightness / 903.3);\n  } else {\n    clipped_brightness = std::pow((clipped_brightness + 16.0) / 116.0, 3.0);\n  }\n\n  // Scale back to 10% to 100%\n  clipped_brightness = std::clamp(100.0f * clipped_brightness, 10.0f, 100.0f);\n\n  if (!s.scene.started) {\n    clipped_brightness = BACKLIGHT_OFFROAD;\n  }\n\n  int brightness = brightness_filter.update(clipped_brightness);\n  if (!awake) {\n    brightness = 0;\n  }\n\n  if (brightness != last_brightness) {\n    std::thread{Hardware::set_brightness, brightness}.detach();\n  }\n  last_brightness = brightness;\n}\n\nvoid Device::updateWakefulness(const UIState &s) {\n  awake_timeout = std::max(awake_timeout - 1, 0);\n\n  bool should_wake = s.scene.started || s.scene.ignition;\n  if (!should_wake) {\n    // tap detection while display is off\n    bool accel_trigger = abs(s.scene.accel_sensor - accel_prev) > 0.2;\n    bool gyro_trigger = abs(s.scene.gyro_sensor - gyro_prev) > 0.15;\n    should_wake = accel_trigger && gyro_trigger;\n    gyro_prev = s.scene.gyro_sensor;\n    accel_prev = (accel_prev * (accel_samples - 1) + s.scene.accel_sensor) / accel_samples;\n  }\n\n  setAwake(awake_timeout, should_wake);\n}\n"
  },
  {
    "path": "selfdrive/ui/ui.h",
    "content": "#pragma once\n\n#include <atomic>\n#include <map>\n#include <memory>\n#include <string>\n\n#include <QObject>\n#include <QTimer>\n#include <QColor>\n\n#include \"nanovg.h\"\n\n#include \"cereal/messaging/messaging.h\"\n#include \"cereal/visionipc/visionipc.h\"\n#include \"cereal/visionipc/visionipc_client.h\"\n#include \"common/transformations/orientation.hpp\"\n#include \"selfdrive/camerad/cameras/camera_common.h\"\n#include \"selfdrive/common/glutil.h\"\n#include \"selfdrive/common/mat.h\"\n#include \"selfdrive/common/modeldata.h\"\n#include \"selfdrive/common/params.h\"\n#include \"selfdrive/common/util.h\"\n#include \"selfdrive/common/visionimg.h\"\n\n#define COLOR_BLACK nvgRGBA(0, 0, 0, 255)\n#define COLOR_BLACK_ALPHA(x) nvgRGBA(0, 0, 0, x)\n#define COLOR_WHITE nvgRGBA(255, 255, 255, 255)\n#define COLOR_WHITE_ALPHA(x) nvgRGBA(255, 255, 255, x)\n#define COLOR_RED_ALPHA(x) nvgRGBA(201, 34, 49, x)\n#define COLOR_YELLOW nvgRGBA(218, 202, 37, 255)\n#define COLOR_RED nvgRGBA(201, 34, 49, 255)\n\ntypedef cereal::CarControl::HUDControl::AudibleAlert AudibleAlert;\n\n// TODO: this is also hardcoded in common/transformations/camera.py\n// TODO: choose based on frame input size\nconst float y_offset = Hardware::TICI() ? 150.0 : 0.0;\nconst float ZOOM = Hardware::TICI() ? 2912.8 : 2138.5;\n\ntypedef struct Rect {\n  int x, y, w, h;\n  int centerX() const { return x + w / 2; }\n  int centerY() const { return y + h / 2; }\n  int right() const { return x + w; }\n  int bottom() const { return y + h; }\n  bool ptInRect(int px, int py) const {\n    return px >= x && px < (x + w) && py >= y && py < (y + h);\n  }\n} Rect;\n\ntypedef struct Alert {\n  QString text1;\n  QString text2;\n  QString type;\n  cereal::ControlsState::AlertSize size;\n  AudibleAlert sound;\n  bool equal(const Alert &a2) {\n    return text1 == a2.text1 && text2 == a2.text2 && type == a2.type;\n  }\n} Alert;\n\nconst Alert CONTROLS_WAITING_ALERT = {\"openpilot Unavailable\", \"Waiting for controls to start\", \n                                      \"controlsWaiting\", cereal::ControlsState::AlertSize::MID,\n                                      AudibleAlert::NONE};\n\nconst Alert CONTROLS_UNRESPONSIVE_ALERT = {\"TAKE CONTROL IMMEDIATELY\", \"Controls Unresponsive\",\n                                           \"controlsUnresponsive\", cereal::ControlsState::AlertSize::FULL,\n                                           AudibleAlert::CHIME_WARNING_REPEAT};\nconst int CONTROLS_TIMEOUT = 5;\n\nconst int bdr_s = 30;\nconst int header_h = 420;\nconst int footer_h = 280;\n\nconst int UI_FREQ = 20;   // Hz\n\ntypedef enum UIStatus {\n  STATUS_DISENGAGED,\n  STATUS_ENGAGED,\n  STATUS_WARNING,\n  STATUS_ALERT,\n} UIStatus;\n\nconst QColor bg_colors [] = {\n  [STATUS_DISENGAGED] =  QColor(0x17, 0x33, 0x49, 0xc8),\n  [STATUS_ENGAGED] = QColor(0x17, 0x86, 0x44, 0xf1),\n  [STATUS_WARNING] = QColor(0xDA, 0x6F, 0x25, 0xf1),\n  [STATUS_ALERT] = QColor(0xC9, 0x22, 0x31, 0xf1),\n};\n\ntypedef struct {\n  float x, y;\n} vertex_data;\n\ntypedef struct {\n  vertex_data v[TRAJECTORY_SIZE * 2];\n  int cnt;\n} line_vertices_data;\n\ntypedef struct UIScene {\n\n  mat3 view_from_calib;\n  bool world_objects_visible;\n\n  cereal::PandaState::PandaType pandaType;\n\n  // modelV2\n  float lane_line_probs[4];\n  float road_edge_stds[2];\n  line_vertices_data track_vertices;\n  line_vertices_data lane_line_vertices[4];\n  line_vertices_data road_edge_vertices[2];\n\n  bool dm_active, engageable;\n\n  // lead\n  vertex_data lead_vertices[2];\n\n  float light_sensor, accel_sensor, gyro_sensor;\n  bool started, ignition, is_metric, longitudinal_control, end_to_end;\n  uint64_t started_frame;\n} UIScene;\n\ntypedef struct UIState {\n  VisionIpcClient * vipc_client;\n  VisionIpcClient * vipc_client_rear;\n  VisionIpcClient * vipc_client_wide;\n  VisionBuf * last_frame;\n\n  // framebuffer\n  int fb_w, fb_h;\n\n  // NVG\n  NVGcontext *vg;\n\n  // images\n  std::map<std::string, int> images;\n\n  std::unique_ptr<SubMaster> sm;\n\n  UIStatus status;\n  UIScene scene;\n\n  // graphics\n  std::unique_ptr<GLShader> gl_shader;\n  std::unique_ptr<EGLImageTexture> texture[UI_BUF_COUNT];\n\n  GLuint frame_vao, frame_vbo, frame_ibo;\n  mat4 rear_frame_mat;\n\n  bool awake;\n\n  float car_space_transform[6];\n  bool wide_camera;\n} UIState;\n\n\nclass QUIState : public QObject {\n  Q_OBJECT\n\npublic:\n  QUIState(QObject* parent = 0);\n\n  // TODO: get rid of this, only use signal\n  inline static UIState ui_state = {0};\n\nsignals:\n  void uiUpdate(const UIState &s);\n  void offroadTransition(bool offroad);\n\nprivate slots:\n  void update();\n\nprivate:\n  QTimer *timer;\n  bool started_prev = true;\n};\n\n\n// device management class\n\nclass Device : public QObject {\n  Q_OBJECT\n\npublic:\n  Device(QObject *parent = 0);\n\nprivate:\n  // auto brightness\n  const float accel_samples = 5*UI_FREQ;\n\n  bool awake;\n  int awake_timeout = 0;\n  float accel_prev = 0;\n  float gyro_prev = 0;\n  float last_brightness = 0;\n  FirstOrderFilter brightness_filter;\n\n  QTimer *timer;\n\n  void updateBrightness(const UIState &s);\n  void updateWakefulness(const UIState &s);\n\nsignals:\n  void displayPowerChanged(bool on);\n\npublic slots:\n  void setAwake(bool on, bool reset);\n  void update(const UIState &s);\n};\n"
  },
  {
    "path": "selfdrive/ui/ui.pro",
    "content": "HEADERS         = qt/widgets/drive_stats.h \\\n                  qt/offroad/settings.h \\\n                  ui.h\nSOURCES         = main.cc \\\n                  paint.cc \\\n                  paint_dp.cc \\\n                  qt/home.cc \\\n                  qt/widgets/prime.cc \\\n                  qt/widgets/setup.cc \\\n                  qt/widgets/drive_stats.cc \\\n                  qt/widgets/ssh_keys.cc \\\n                  qt/offroad/settings.cc \\\n                  qt/offroad/networking.cc \\\n                  qt/sidebar.cc \\\n                  qt/offroad/settings_dp.cc\n\nTRANSLATIONS    = translations/en-US.ts \\\n                  translations/zh-TW.ts \\\n                  translations/zh-CN.ts\n"
  },
  {
    "path": "selfdrive/ui/update_translations.sh",
    "content": "#!/bin/bash\n\nrm -fr translations/*.qm\nlupdate ui.pro #-noobsolete\n# lupdate finds and adds all strings wrapped in tr() to main_languagecode files\n#linguist translations/en-US.ts\n#linguist translations/zh-CN.ts\n\n# once translated, run\nlrelease ui.pro\n# which converts the translations to a binary file that enables fast lookups by the application"
  },
  {
    "path": "selfdrive/updated.py",
    "content": "#!/usr/bin/env python3\n\n# Safe Update: A simple service that waits for network access and tries to\n# update every 10 minutes. It's intended to make the OP update process more\n# robust against Git repository corruption. This service DOES NOT try to fix\n# an already-corrupt BASEDIR Git repo, only prevent it from happening.\n#\n# During normal operation, both onroad and offroad, the update process makes\n# no changes to the BASEDIR install of OP. All update attempts are performed\n# in a disposable staging area provided by OverlayFS. It assumes the deleter\n# process provides enough disk space to carry out the process.\n#\n# If an update succeeds, a flag is set, and the update is swapped in at the\n# next reboot. If an update is interrupted or otherwise fails, the OverlayFS\n# upper layer and metadata can be discarded before trying again.\n#\n# The swap on boot is triggered by launch_chffrplus.sh\n# gated on the existence of $FINALIZED/.overlay_consistent and also the\n# existence and mtime of $BASEDIR/.overlay_init.\n#\n# Other than build byproducts, BASEDIR should not be modified while this\n# service is running. Developers modifying code directly in BASEDIR should\n# disable this service.\n\nimport os\nimport datetime\nimport subprocess\nimport psutil\nimport shutil\nimport signal\nimport fcntl\nimport time\nimport threading\nfrom pathlib import Path\nfrom typing import List, Tuple, Optional\n\nfrom common.basedir import BASEDIR\nfrom common.params import Params\nfrom selfdrive.hardware import EON, TICI, HARDWARE\nfrom selfdrive.swaglog import cloudlog\nfrom selfdrive.controls.lib.alertmanager import set_offroad_alert\n\nLOCK_FILE = os.getenv(\"UPDATER_LOCK_FILE\", \"/tmp/safe_staging_overlay.lock\")\nSTAGING_ROOT = os.getenv(\"UPDATER_STAGING_ROOT\", \"/data/safe_staging\")\n\nNEOSUPDATE_DIR = os.getenv(\"UPDATER_NEOSUPDATE_DIR\", \"/data/neoupdate\")\n\nOVERLAY_UPPER = os.path.join(STAGING_ROOT, \"upper\")\nOVERLAY_METADATA = os.path.join(STAGING_ROOT, \"metadata\")\nOVERLAY_MERGED = os.path.join(STAGING_ROOT, \"merged\")\nFINALIZED = os.path.join(STAGING_ROOT, \"finalized\")\n\n\nclass WaitTimeHelper:\n  def __init__(self, proc):\n    self.proc = proc\n    self.ready_event = threading.Event()\n    self.shutdown = False\n    signal.signal(signal.SIGTERM, self.graceful_shutdown)\n    signal.signal(signal.SIGINT, self.graceful_shutdown)\n    signal.signal(signal.SIGHUP, self.update_now)\n\n  def graceful_shutdown(self, signum: int, frame) -> None:\n    # umount -f doesn't appear effective in avoiding \"device busy\" on NEOS,\n    # so don't actually die until the next convenient opportunity in main().\n    cloudlog.info(\"caught SIGINT/SIGTERM, dismounting overlay at next opportunity\")\n\n    # forward the signal to all our child processes\n    child_procs = self.proc.children(recursive=True)\n    for p in child_procs:\n      p.send_signal(signum)\n\n    self.shutdown = True\n    self.ready_event.set()\n\n  def update_now(self, signum: int, frame) -> None:\n    cloudlog.info(\"caught SIGHUP, running update check immediately\")\n    self.ready_event.set()\n\n  def sleep(self, t: float) -> None:\n    self.ready_event.wait(timeout=t)\n\n\ndef run(cmd: List[str], cwd: Optional[str] = None, low_priority: bool = False):\n  if low_priority:\n    cmd = [\"nice\", \"-n\", \"19\"] + cmd\n  return subprocess.check_output(cmd, cwd=cwd, stderr=subprocess.STDOUT, encoding='utf8')\n\n\ndef set_consistent_flag(consistent: bool) -> None:\n  os.sync()\n  consistent_file = Path(os.path.join(FINALIZED, \".overlay_consistent\"))\n  if consistent:\n    consistent_file.touch()\n  elif not consistent:\n    consistent_file.unlink(missing_ok=True)\n  os.sync()\n\n\ndef set_params(new_version: bool, failed_count: int, exception: Optional[str]) -> None:\n  params = Params()\n\n  params.put(\"UpdateFailedCount\", str(failed_count))\n  if failed_count == 0:\n    t = datetime.datetime.utcnow().isoformat()\n    params.put(\"LastUpdateTime\", t.encode('utf8'))\n\n  if exception is None:\n    params.delete(\"LastUpdateException\")\n  else:\n    params.put(\"LastUpdateException\", exception)\n\n  if new_version:\n    try:\n      with open(os.path.join(FINALIZED, f\"CHANGELOGS-DEV.md\"), \"rb\") as f:\n        r = f.read()\n      r = r[:r.find(b'\\n\\n')]  # Slice latest release notes\n      params.put(\"ReleaseNotes\", r + b\"\\n\")\n    except Exception:\n      params.put(\"ReleaseNotes\", \"\")\n    params.put_bool(\"UpdateAvailable\", True)\n\n\ndef setup_git_options(cwd: str) -> None:\n  # We sync FS object atimes (which NEOS doesn't use) and mtimes, but ctimes\n  # are outside user control. Make sure Git is set up to ignore system ctimes,\n  # because they change when we make hard links during finalize. Otherwise,\n  # there is a lot of unnecessary churn. This appears to be a common need on\n  # OSX as well: https://www.git-tower.com/blog/make-git-rebase-safe-on-osx/\n\n  # We are using copytree to copy the directory, which also changes\n  # inode numbers. Ignore those changes too.\n  git_cfg = [\n    (\"core.trustctime\", \"false\"),\n    (\"core.checkStat\", \"minimal\"),\n  ]\n  for option, value in git_cfg:\n    run([\"git\", \"config\", option, value], cwd)\n\n\ndef dismount_overlay() -> None:\n  if os.path.ismount(OVERLAY_MERGED):\n    cloudlog.info(\"unmounting existing overlay\")\n    args = [\"umount\", \"-l\", OVERLAY_MERGED]\n    if TICI:\n      args = [\"sudo\"] + args\n    run(args)\n\n\ndef init_overlay() -> None:\n\n  overlay_init_file = Path(os.path.join(BASEDIR, \".overlay_init\"))\n\n  # Re-create the overlay if BASEDIR/.git has changed since we created the overlay\n  if overlay_init_file.is_file():\n    git_dir_path = os.path.join(BASEDIR, \".git\")\n    new_files = run([\"find\", git_dir_path, \"-newer\", str(overlay_init_file)])\n    if not len(new_files.splitlines()):\n      # A valid overlay already exists\n      return\n    else:\n      cloudlog.info(\".git directory changed, recreating overlay\")\n\n  cloudlog.info(\"preparing new safe staging area\")\n\n  params = Params()\n  params.put_bool(\"UpdateAvailable\", False)\n  set_consistent_flag(False)\n  dismount_overlay()\n  if TICI:\n    run([\"sudo\", \"rm\", \"-rf\", STAGING_ROOT])\n  if os.path.isdir(STAGING_ROOT):\n    shutil.rmtree(STAGING_ROOT)\n\n  for dirname in [STAGING_ROOT, OVERLAY_UPPER, OVERLAY_METADATA, OVERLAY_MERGED]:\n    os.mkdir(dirname, 0o755)\n\n  if os.lstat(BASEDIR).st_dev != os.lstat(OVERLAY_MERGED).st_dev:\n    raise RuntimeError(\"base and overlay merge directories are on different filesystems; not valid for overlay FS!\")\n\n  # Leave a timestamped canary in BASEDIR to check at startup. The device clock\n  # should be correct by the time we get here. If the init file disappears, or\n  # critical mtimes in BASEDIR are newer than .overlay_init, continue.sh can\n  # assume that BASEDIR has used for local development or otherwise modified,\n  # and skips the update activation attempt.\n  consistent_file = Path(os.path.join(BASEDIR, \".overlay_consistent\"))\n  if consistent_file.is_file():\n    consistent_file.unlink()\n  overlay_init_file.touch()\n\n  os.sync()\n  overlay_opts = f\"lowerdir={BASEDIR},upperdir={OVERLAY_UPPER},workdir={OVERLAY_METADATA}\"\n\n  mount_cmd = [\"mount\", \"-t\", \"overlay\", \"-o\", overlay_opts, \"none\", OVERLAY_MERGED]\n  if TICI:\n    run([\"sudo\"] + mount_cmd)\n    run([\"sudo\", \"chmod\", \"755\", os.path.join(OVERLAY_METADATA, \"work\")])\n  else:\n    run(mount_cmd)\n\n  #git_diff = run([\"git\", \"diff\"], OVERLAY_MERGED, low_priority=True)\n  params.put(\"GitDiff\", \"\")\n  #cloudlog.info(f\"git diff output:\\n{git_diff}\")\n\n\ndef finalize_update() -> None:\n  \"\"\"Take the current OverlayFS merged view and finalize a copy outside of\n  OverlayFS, ready to be swapped-in at BASEDIR. Copy using shutil.copytree\"\"\"\n\n  # Remove the update ready flag and any old updates\n  cloudlog.info(\"creating finalized version of the overlay\")\n  set_consistent_flag(False)\n\n  # Copy the merged overlay view and set the update ready flag\n  if os.path.exists(FINALIZED):\n    shutil.rmtree(FINALIZED)\n  shutil.copytree(OVERLAY_MERGED, FINALIZED, symlinks=True)\n\n  set_consistent_flag(True)\n  cloudlog.info(\"done finalizing overlay\")\n\n\ndef handle_agnos_update(wait_helper):\n  from selfdrive.hardware.tici.agnos import flash_agnos_update, get_target_slot_number\n\n  cur_version = HARDWARE.get_os_version()\n  updated_version = run([\"bash\", \"-c\", r\"unset AGNOS_VERSION && source launch_env.sh && \\\n                          echo -n $AGNOS_VERSION\"], OVERLAY_MERGED).strip()\n\n  cloudlog.info(f\"AGNOS version check: {cur_version} vs {updated_version}\")\n  if cur_version == updated_version:\n    return\n\n  # prevent an openpilot getting swapped in with a mismatched or partially downloaded agnos\n  set_consistent_flag(False)\n\n  cloudlog.info(f\"Beginning background installation for AGNOS {updated_version}\")\n  set_offroad_alert(\"Offroad_NeosUpdate\", True)\n\n  manifest_path = os.path.join(OVERLAY_MERGED, \"selfdrive/hardware/tici/agnos.json\")\n  target_slot_number = get_target_slot_number()\n  flash_agnos_update(manifest_path, target_slot_number, cloudlog)\n  set_offroad_alert(\"Offroad_NeosUpdate\", False)\n\n\ndef handle_neos_update(wait_helper: WaitTimeHelper) -> None:\n  cur_neos = HARDWARE.get_os_version()\n  updated_neos = run([\"bash\", \"-c\", r\"unset REQUIRED_NEOS_VERSION && source launch_env.sh && \\\n                       echo -n $REQUIRED_NEOS_VERSION\"], OVERLAY_MERGED).strip()\n\n  cloudlog.info(f\"NEOS version check: {cur_neos} vs {updated_neos}\")\n  if cur_neos == updated_neos:\n    return\n\n  cloudlog.info(f\"Beginning background download for NEOS {updated_neos}\")\n  set_offroad_alert(\"Offroad_NeosUpdate\", True)\n\n  updater_path = os.path.join(OVERLAY_MERGED, \"installer/updater/updater\")\n  update_manifest = f\"file://{OVERLAY_MERGED}/installer/updater/update.json\"\n\n  neos_downloaded = False\n  start_time = time.monotonic()\n  # Try to download for one day\n  while not neos_downloaded and not wait_helper.shutdown and \\\n        (time.monotonic() - start_time < 60*60*24):\n    wait_helper.ready_event.clear()\n    try:\n      run([updater_path, \"bgcache\", update_manifest], OVERLAY_MERGED, low_priority=True)\n      neos_downloaded = True\n    except subprocess.CalledProcessError:\n      cloudlog.info(\"NEOS background download failed, retrying\")\n      wait_helper.sleep(120)\n\n  # If the download failed, we'll show the alert again when we retry\n  set_offroad_alert(\"Offroad_NeosUpdate\", False)\n  if not neos_downloaded:\n    raise Exception(\"Failed to download NEOS update\")\n  cloudlog.info(f\"NEOS background download successful, took {time.monotonic() - start_time} seconds\")\n\n\ndef check_git_fetch_result(fetch_txt):\n  err_msg = \"Failed to add the host to the list of known hosts (/data/data/com.termux/files/home/.ssh/known_hosts).\\n\"\n  return len(fetch_txt) > 0 and (fetch_txt != err_msg)\n\n\ndef check_for_update() -> Tuple[bool, bool]:\n  setup_git_options(OVERLAY_MERGED)\n  try:\n    git_fetch_output = run([\"git\", \"fetch\", \"--dry-run\"], OVERLAY_MERGED, low_priority=True)\n    return True, check_git_fetch_result(git_fetch_output)\n  except subprocess.CalledProcessError:\n    return False, False\n\n\ndef fetch_update(wait_helper: WaitTimeHelper) -> bool:\n  cloudlog.info(\"attempting git fetch inside staging overlay\")\n\n  setup_git_options(OVERLAY_MERGED)\n\n  git_fetch_output = run([\"git\", \"fetch\"], OVERLAY_MERGED, low_priority=True)\n  cloudlog.info(\"git fetch success: %s\", git_fetch_output)\n\n  cur_hash = run([\"git\", \"rev-parse\", \"HEAD\"], OVERLAY_MERGED).rstrip()\n  upstream_hash = run([\"git\", \"rev-parse\", \"@{u}\"], OVERLAY_MERGED).rstrip()\n  new_version = cur_hash != upstream_hash\n  git_fetch_result = check_git_fetch_result(git_fetch_output)\n\n  cloudlog.info(\"comparing %s to %s\" % (cur_hash, upstream_hash))\n  if new_version or git_fetch_result:\n    cloudlog.info(\"Running update\")\n\n    if new_version:\n      cloudlog.info(\"git reset in progress\")\n      r = [\n        run([\"git\", \"reset\", \"--hard\", \"@{u}\"], OVERLAY_MERGED, low_priority=True),\n        run([\"git\", \"clean\", \"-xdf\"], OVERLAY_MERGED, low_priority=True ),\n        run([\"git\", \"submodule\", \"init\"], OVERLAY_MERGED, low_priority=True),\n        run([\"git\", \"submodule\", \"update\"], OVERLAY_MERGED, low_priority=True),\n      ]\n      cloudlog.info(\"git reset success: %s\", '\\n'.join(r))\n\n      if EON and not os.path.isfile(\"/ONEPLUS\"):\n        handle_neos_update(wait_helper)\n      elif TICI:\n        handle_agnos_update(wait_helper)\n\n    # Create the finalized, ready-to-swap update\n    finalize_update()\n    cloudlog.info(\"openpilot update successful!\")\n  else:\n    cloudlog.info(\"nothing new from git at this time\")\n\n  return new_version\n\n\ndef main():\n  params = Params()\n\n  if params.get_bool(\"DisableUpdates\"):\n    raise RuntimeError(\"updates are disabled by the DisableUpdates param\")\n\n  if EON and os.geteuid() != 0:\n    raise RuntimeError(\"updated must be launched as root!\")\n\n  # Set low io priority\n  proc = psutil.Process()\n  if psutil.LINUX:\n    proc.ionice(psutil.IOPRIO_CLASS_BE, value=7)\n\n  # Check if we just performed an update\n  if Path(os.path.join(STAGING_ROOT, \"old_openpilot\")).is_dir():\n    cloudlog.event(\"update installed\")\n\n  ov_lock_fd = open(LOCK_FILE, 'w')\n  try:\n    fcntl.flock(ov_lock_fd, fcntl.LOCK_EX | fcntl.LOCK_NB)\n  except IOError as e:\n    raise RuntimeError(\"couldn't get overlay lock; is another updated running?\") from e\n\n  # Wait for IsOffroad to be set before our first update attempt\n  wait_helper = WaitTimeHelper(proc)\n  wait_helper.sleep(30)\n\n  overlay_init = Path(os.path.join(BASEDIR, \".overlay_init\"))\n  overlay_init.unlink(missing_ok=True)\n\n  first_run = True\n  last_fetch_time = 0\n  update_failed_count = 0\n\n  # Run the update loop\n  #  * every 1m, do a lightweight internet/update check\n  #  * every 10m, do a full git fetch\n  while not wait_helper.shutdown:\n    update_now = wait_helper.ready_event.is_set()\n    wait_helper.ready_event.clear()\n\n    # Don't run updater while onroad or if the time's wrong\n    time_wrong = datetime.datetime.utcnow().year < 2019\n    is_onroad = not params.get_bool(\"IsOffroad\")\n    if is_onroad or time_wrong:\n      wait_helper.sleep(30)\n      cloudlog.info(\"not running updater, not offroad\")\n      continue\n\n    # Attempt an update\n    exception = None\n    new_version = False\n    update_failed_count += 1\n    try:\n      init_overlay()\n\n      internet_ok, update_available = check_for_update()\n      if internet_ok and not update_available:\n        update_failed_count = 0\n\n      # Fetch updates at most every 10 minutes\n      if internet_ok and (update_now or time.monotonic() - last_fetch_time > 60*10):\n        new_version = fetch_update(wait_helper)\n        update_failed_count = 0\n        last_fetch_time = time.monotonic()\n\n        if first_run and not new_version and os.path.isdir(NEOSUPDATE_DIR):\n          shutil.rmtree(NEOSUPDATE_DIR)\n        first_run = False\n    except subprocess.CalledProcessError as e:\n      cloudlog.event(\n        \"update process failed\",\n        cmd=e.cmd,\n        output=e.output,\n        returncode=e.returncode\n      )\n      exception = f\"command failed: {e.cmd}\\n{e.output}\"\n      overlay_init.unlink(missing_ok=True)\n    except Exception as e:\n      cloudlog.exception(\"uncaught updated exception, shouldn't happen\")\n      exception = str(e)\n      overlay_init.unlink(missing_ok=True)\n\n    set_params(new_version, update_failed_count, exception)\n    wait_helper.sleep(60)\n\n  dismount_overlay()\n\n\nif __name__ == \"__main__\":\n  main()\n"
  },
  {
    "path": "selfdrive/version.py",
    "content": "#!/usr/bin/env python3\nimport os\nimport subprocess\nfrom typing import List, Optional\n\nfrom common.basedir import BASEDIR\nfrom selfdrive.swaglog import cloudlog\n\n\nTESTED_BRANCHES = ['devel', 'release2-staging', 'release3-staging', 'dashcam-staging', 'release2', 'release3', 'dashcam']\n\n\ndef run_cmd(cmd: List[str]) -> str:\n    return subprocess.check_output(cmd, encoding='utf8').strip()\n\n\ndef run_cmd_default(cmd: List[str], default: Optional[str] = None) -> Optional[str]:\n  try:\n    return run_cmd(cmd)\n  except subprocess.CalledProcessError:\n    return default\n\n\ndef get_git_commit(branch: str = \"HEAD\", default: Optional[str] = None) -> Optional[str]:\n  return run_cmd_default([\"git\", \"rev-parse\", branch], default=default)\n\n\ndef get_git_branch(default: Optional[str] = None) -> Optional[str]:\n  return run_cmd_default([\"git\", \"rev-parse\", \"--abbrev-ref\", \"HEAD\"], default=default)\n\n\ndef get_git_full_branchname(default: Optional[str] = None) -> Optional[str]:\n  return run_cmd_default([\"git\", \"rev-parse\", \"--abbrev-ref\", \"--symbolic-full-name\", \"@{u}\"], default=default)\n\n\ndef get_git_remote(default: Optional[str] = None) -> Optional[str]:\n  try:\n    local_branch = run_cmd([\"git\", \"name-rev\", \"--name-only\", \"HEAD\"])\n    tracking_remote = run_cmd([\"git\", \"config\", \"branch.\" + local_branch + \".remote\"])\n    return run_cmd([\"git\", \"config\", \"remote.\" + tracking_remote + \".url\"])\n  except subprocess.CalledProcessError:  # Not on a branch, fallback\n    return run_cmd_default([\"git\", \"config\", \"--get\", \"remote.origin.url\"], default=default)\n\n\ndef get_version():\n  with open(os.path.join(os.path.dirname(os.path.abspath(__file__)), \"common\", \"version.h\")) as _versionf:\n    version = _versionf.read().split('\"')[1]\n  return version\n\nversion = get_version()\nprebuilt = os.path.exists(os.path.join(BASEDIR, 'prebuilt'))\n\ntraining_version: bytes = b\"0.2.0\"\nterms_version: bytes = b\"2\"\n\ndirty: bool = True\ncomma_remote: bool = False\ntested_branch: bool = False\norigin = get_git_remote()\nbranch = get_git_full_branchname()\ncommit = get_git_commit()\n\nif (origin is not None) and (branch is not None):\n  try:\n    # Update the username to your Git-username\n    comma_remote = origin.startswith('git@github.com:efinilan') or origin.startswith('https://github.com/efinilan')\n    tested_branch = get_git_branch() in TESTED_BRANCHES\n\n    dirty = False\n\n    # Actually check dirty files\n    if not prebuilt:\n      # This is needed otherwise touched files might show up as modified\n      try:\n        subprocess.check_call([\"git\", \"update-index\", \"--refresh\"])\n      except subprocess.CalledProcessError:\n        pass\n      dirty = (subprocess.call([\"git\", \"diff-index\", \"--quiet\", branch, \"--\"]) != 0)\n\n      # Log dirty files\n      if dirty and comma_remote:\n        try:\n          dirty_files = \"\"#run_cmd([\"git\", \"diff-index\", branch, \"--\"])\n          cloudlog.event(\"dirty comma branch\", version=version, dirty=dirty, origin=origin, branch=branch,\n                         dirty_files=dirty_files, commit=commit, origin_commit=get_git_commit(branch))\n        except subprocess.CalledProcessError:\n          pass\n\n    dirty = dirty or (not comma_remote)\n    dirty = dirty or ('master' in branch)\n\n  except subprocess.CalledProcessError:\n    dirty = True\n    cloudlog.exception(\"git subprocess failed while checking dirty\")\n\n\nif __name__ == \"__main__\":\n  print(\"Dirty: %s\" % dirty)\n  print(\"Version: %s\" % version)\n  print(\"Remote: %s\" % origin)\n  print(\"Branch: %s\" % branch)\n  print(\"Prebuilt: %s\" % prebuilt)\n"
  },
  {
    "path": "site_scons/site_tools/cython.py",
    "content": "import re\nimport SCons\nfrom SCons.Action import Action\nfrom SCons.Scanner import Scanner\n\npyx_from_import_re = re.compile(r'^from\\s+(\\S+)\\s+cimport', re.M)\npyx_import_re = re.compile(r'^cimport\\s+(\\S+)', re.M)\ncdef_import_re = re.compile(r'^cdef extern from\\s+.(\\S+).:', re.M)\n\n\ndef pyx_scan(node, env, path, arg=None):\n  contents = node.get_text_contents()\n\n  # from <module> cimport ...\n  matches = pyx_from_import_re.findall(contents)\n  # cimport <module>\n  matches += pyx_import_re.findall(contents)\n\n  # Modules can be either .pxd or .pyx files\n  files = [m.replace('.', '/') + '.pxd' for m in matches]\n  files += [m.replace('.', '/') + '.pyx' for m in matches]\n\n  # cdef extern from <file>\n  files += cdef_import_re.findall(contents)\n\n  # Handle relative imports\n  cur_dir = str(node.get_dir())\n  files = [cur_dir + f if f.startswith('/') else f for f in files]\n\n  # Filter out non-existing files (probably system imports)\n  files = [f for f in files if env.File(f).exists()]\n  return env.File(files)\n\n\npyxscanner = Scanner(function=pyx_scan, skeys=['.pyx', '.pxd'], recursive=True)\ncythonAction = Action(\"$CYTHONCOM\")\n\n\ndef create_builder(env):\n  try:\n    cython = env['BUILDERS']['Cython']\n  except KeyError:\n    cython = SCons.Builder.Builder(\n      action=cythonAction,\n      emitter={},\n      suffix=cython_suffix_emitter,\n      single_source=1\n    )\n    env.Append(SCANNERS=pyxscanner)\n    env['BUILDERS']['Cython'] = cython\n  return cython\n\ndef cython_suffix_emitter(env, source):\n  return \"$CYTHONCFILESUFFIX\"\n\ndef generate(env):\n  env[\"CYTHON\"] = \"cythonize\"\n  env[\"CYTHONCOM\"] = \"$CYTHON $CYTHONFLAGS $SOURCE\"\n  env[\"CYTHONCFILESUFFIX\"] = \".cpp\"\n\n  c_file, _ = SCons.Tool.createCFileBuilders(env)\n\n  c_file.suffix['.pyx'] = cython_suffix_emitter\n  c_file.add_action('.pyx', cythonAction)\n\n  c_file.suffix['.py'] = cython_suffix_emitter\n  c_file.add_action('.py', cythonAction)\n\n  create_builder(env)\n\ndef exists(env):\n  return True\n"
  },
  {
    "path": "tools/openpilot_env.sh",
    "content": "if [ -z \"$OPENPILOT_ENV\" ]; then\n  export PYTHONPATH=\"/data/openpilot\"\n\n  unamestr=`uname`\n  if [[ \"$unamestr\" == 'Linux' ]]; then\n    export PATH=\"$HOME/.pyenv/bin:$PATH\"\n    eval \"$(pyenv virtualenv-init -)\"\n  elif [[ \"$unamestr\" == 'Darwin' ]]; then\n    # msgq doesn't work on mac\n    export ZMQ=1\n    export OBJC_DISABLE_INITIALIZE_FORK_SAFETY=YES\n  fi\n  eval \"$(pyenv init -)\"\n\n  export OPENPILOT_ENV=1\nfi\n"
  }
]